INTEGRATION, the VLSI journal 84 (2022) 62–71

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Integration
journal homepage: www.elsevier.com/locate/vlsi

On circuit developments to enable large scale circuit design while

computing with noise
Naveen Kumar Macha a, Md Arif Iqbal c, *, Bhavana Tejaswini Repalle b, Mostafizur Rahman c
a
Nvidia Corporation, 2788 San Tomas Expy, Santa Clara, CA 95051, USA
b
Marvell Semiconductor Inc, 5488 Marvell Lane, Santa Clara, CA 95054, USA
c
University of Missouri Kansas City, 801 E 51st St, Kansas City, MO 64110, USA

A R T I C L E I N F O A B S T R A C

Keywords: The conventional CMOS scaling trend faces device scaling limitations, interconnect bottleneck, and signal
Crosstalk computing integrity issues due to crosstalk, which is the unwanted interference of signals between neighboring metal lines.
Design constraints Traditional computing circuits always try to reduce the crosstalk noise by applying various circuit and layout
Large-scale circuit design
techniques. In contrast, Crosstalk computing is a new computing framework that can leverage this detrimental
Signal integrity
effect and convert it astutely to a useful feature. The Crosstalk is engineered into a logic computation principle by
leveraging deterministic signal interference for innovative circuit implementation. In this paper, we present a
comprehensive circuit framework for Crosstalk Computing and derives all the key circuit elements that can
enable this computing model for large-scale design. It also performs a comparison study between Crosstalk
circuits and existing CMOS-based approaches. The ability to design a wide range of logic circuits (basic and
complex logics) and programmable gates compact in design and minimal in transistor count is unique to
Crosstalk Computing, which leads to benefits in the circuit density, power, and performance. The circuit
simulation results designed at 7 nm show 3.4x improvement density, 62% reduction in Energy-Delay-Product
(EDP), and 34.5% improvement in performance compared to counterpart implementation in CMOS circuit style.

1. Introduction
MINIATURIZATION of Integrated Circuits (ICs), conventionally referred to
by Moore’s Law [1,2], has been offering unprecedented socio-economic
benefits. Thus, the past few decades have seen exponential growth in
digital electronics capabilities primarily due to the ability to scale ICs to
smaller dimensions while attaining power and performance benefits.
This scalability is now being challenged [3] due to the lack of scaled
transistors’ performance, leakage, and manufacturing complexities [4].
Specifically, the challenges are device and fundamental material limi­
tations such as quantum mechanical effects [5,6], short channel effects
[7], process variation [3], and device parasitics [3], etc. Recent research
directions like neuromorphic computing [8–15], Quantum-dot Cellular
Automata (QCA) [16], Single-Electron Transistors (SET) [17], nano­
magnetic and spintronic devices [18,19], Quantum Computing [20], etc.
are promising. However, they lack significant technology and ecosystem
development (from device and circuit to chip design) and suffer from
reliability and variability issues. Moreover, some of these approaches,
like Quantum Computing and Neuromorphic Computing, from their
current device and circuit development, reveal that they cannot serve as
a complete replacement solution for CMOS digital Chips but can only
solve specific problems efficiently [36–41]. Therefore, there is a need to
explore alternate computing approaches based on nanoscale mecha­
nisms/effects and possess the strong merits of conventional CMOS
computing and provide Power, Performance, and Area (PPA) improve­
ments over CMOS.
Crosstalk computing is a new computing framework where the
interconnect interference between nanoscale metal lines is intentionally
engineered to exhibit the programmable Boolean logic behavior. The
reliance on just the coupling between metal lines and not on the tran­
sistors for computing and the programmability aspects are the founda­
tions for better scalability, fault tolerance, and security [21–28,42,44].
To the best of our knowledge, as of now, there is no prior work in the
area of the Crosstalk computation. Most of the research is done on
calculation the amount of Crosstalk generated from a circuit and how to
mitigate them. Interestingly, Crosstalk Computing does not require
complete technology development, as in the case of emerging technol­
ogies. It can be realized with the established manufacturing setups of

* Corresponding author.
E-mail address: mibn8@mail.umkc.edu (M.A. Iqbal).

https://doi.org/10.1016/j.vlsi.2022.01.002
Received 1 June 2021; Received in revised form 11 September 2021; Accepted 1 January 2022
Available online 8 January 2022
0167-9260/© 2022 Elsevier B.V. All rights reserved.
N.K. Macha et al.
foundries; it leverages the existing fabrication flows, techniques, tools,
and materials. As Crosstalk Computing uses the Silicon-based fabrica­
tion technology matured over 60 years, the defects and variability issues
are expected to be less; thus, reliability and fault tolerance will be better
than the other emerging nanoelectronics devices and circuits.
As the Crosstalk technology relies on noise for computation, logic
cascading and maintaining signal strength become critical issues for
large-scale circuits. The output node of the Crosstalk circuit should be
able to drive the fanout gates in actual design and maintain the signal
integrity of binary voltage levels [21]. Our new circuit technique solved
the above issues, and we have also shown the experimental evidence of a
functioning Crosstalk computing chip at TSMC 65 nm technology in
Ref. [35]. Our demonstration of computing constructs, gate level con­
figurability, and foundry processes’ utilization show the technology’s
feasibility. In our previous work, we have not discussed Crosstalk cir­
cuits’ cascading circuit issues and solutions to overcome them. In this
work, we present for the first time all circuit developments and a design
framework needed for large-scale circuit implementation using Cross­
talk Computing. All the simulation work presented in this manuscript is
done using ASAP 7 nm PDK [43]. The framework provides the pathway
to overcome the cascading challenges, create robust signals at the output
nodes, and then details the design constraints. We have also imple­
mented large-scale designs from MCNC benchmark suits using ASAP 7
nm PDK and compared them with CMOS counterparts. Our results show
3.4x improvement density, 62% reduction in EDP, and 34.5%
improvement in performance compared to CMOS-based circuits. The
unique capabilities of Crosstalk computing can provide new opportu­
nities for future electronics.
The rest of the paper is organized as follows. Section II discusses the
Crosstalk Computing concept, provides the intuition for logic imple­
mentation. Section III presents the circuit techniques to implement basic
and complex logic circuits based on the input signal. Next, we discuss the
cascaded circuit issues in section IV and then present the solutions in
section V. In Section VI, we present the comparison of Crosstalk circuits
with the CMOS counterpart. Finally, Section VII concludes the paper.
2. Crosstalk Computing overview
Crosstalk computing leverages interference between closely coupled
signals carrying metal lines to do useful computation. The key compo­
nents necessary for this computation are: a) metal lines and their logic-
Fig. 1. Abstract view of Crosstalk fabric and Crosstalk primitive gates (AND and OR). A) Crosstalk Fabric; Coupling capacitances will be on the top denoted as
‘dielectric’ in between nano-metal lines denoted as ‘aggressor’ and ‘victim’. B). i) AND schematic, ii) Simulation results of AND gate, iii) OR schematic, iv) Simulation
results of OR gate.
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Integration 84 (2022) 62–71
specific arrangements to drive inputs, b) engineered coupling capaci­
tance between these lines, and c) synchronous clock inputs and one
transistor-based scheme to control the output behavior. Fig. 1A presents
an abstract view of a fabric that implements crosstalk computing, where
the metal lines are arranged on the top and the controlling transistors are
at the bottom. We intentionally arrange metal lines such that they can
interfere in a deterministic manner (Fig. 1A). Then we capture this
deterministic interference in a specific timeframe to ascertain logic. Let
us use an example of a two-input (A and B) logic. In Crosstalk, we would
drive these inputs in two adjacent metal lines, and in between those
lines, we will have another metal line to capture the interference charge
(or the output). In interconnect terminology, the driving inputs would
be called Aggressors (named Ag1 and Ag2). The interference capturing
line would be called the Victim (Vi). The victim would be intentionally
kept floating (not connected to the power supply or ground). As the
aggressors transition from 0 to 1 or 1 to 0, corresponding interference
would result in voltage gain or drop in the Victim node. If any of the
input transitions (A or B) from 0 to 1 result in a sufficiently high voltage
induction in the victim, we would achieve OR logic, and if only when
both A and B transition from 0 to 1, we notice high voltage induction in
victim node, we would call the metal arrangement as performing AND
logic.
To capture the behavior in circuits for large-scale integration, we
utilize a control transistor and a clock. With the help of the control
transistor, we periodically preset/sink the Victim node to the ground
and deterministically keep the Victim node floating (ready for charge
induction) during logic computation. Thus, crosstalk circuits operate in
logic Evaluation State (ES) and Discharge State (DS). In addition, an
inverter is attached to the victim node is required to achieve a complete
voltage swing for the following stages. Fundamentally though, the logic
computation happens due to the interference between interconnects and
without the help of the transistor.
3. Crosstalk Circuit Styles
The Crosstalk signal interference between two signal-carrying metal
lines will happen when there is a relative change in two nets’ potential/
voltage. Therefore, Crosstalk circuits can only detect a new logic level
through signal transition, and logic computation can happen when input
signal changes. Furthermore, the types of signal transitions can be
positive (0 → 1), negative (1 → 0), or both. Thus, based on the different
N.K. Macha et al.
transition types of signals, the Crosstalk circuits have been classified as
the following styles:
3.1. Positive Transition Crosstalk Circuits
Fig. 2A depicts the positive-transition Crosstalk circuits. In these
circuits, the initial state of the Vi node and all input aggressors during DS
state is 0. During the ES state, the input signals the transition from 0 → 1
on the aggressor lines, which results in charge accumulation on the
victim node. The 0 → 1 transition on inputs contributes charge to the Vi
node, thus identified as the logic 1. Whereas if logic 0, there is no signal
transition and no contribution of charge. Therefore, the working
mechanism in positive transition Crosstalk circuits is through the charge
summation principle. Fig. 2A shows the example of such circuits. When
signal A transitions from 0 → 1 on Ag1 or signal B transitions from 0 → 1
on Ag2 or when both the transition of the signal, the charge accumulates
on victim node and results in either NAND or NOR gate based on the
coupling strength and inverter trip-point. The discharge transistor drain
is connected to the victim line, and the source is connected to GND. In
this way, the victim node is refreshed to ground potential before the
arrival of any signal. Previous stage gates will maintain the initial state
of 0 on input aggressors.
The circuit figures also list the margin function for respective cir­
cuits. It signifies the number of quantized capacitances through which Vi
needs to see the transitions to flip the logic state at the inverter output. It
represents the circuit functionality, i.e., the number of inputs needed to
change their initial state to achieve the intended logic. The two inputs of
NAND and NOR (Fig. 2A) get quantized capacitances, CND and CNR
(specific to that circuit). The tables adjacent to the circuit diagram
(Fig. 2. A.i., B.i., C.i.) lists the margin function (CTM). A margin function
(CTM) for the Crosstalk gate indicates how many and what input must be
1 for the inverter to alter its state. CTM (2CND) for NAND states two in­
puts need to change 0->1 to flip the output state, CTM (CNR) for NOR
states, any single input needs to change 0->1 to flip the output state.
3.2. Negative Transition Crosstalk Circuits
The negative transition Crosstalk circuit mechanism is based on high
to low signal transition. Fig. 2B shows the example of a negative tran­
sition Crosstalk circuit. The main working principle of the Crosstalk
circuit remains the same, except this time, initial states are set to logic
high. In this case, input logic 1 does not lead to any transition on ag­
gressors. However, logic 0 makes 1 → 0 transitions and deterministically
subtracts the charge from Vi node which is also precharged to logic high.
In complement to NMOS discharge transistor in positive transition cir­
cuits, a PMOS transistor (Fig. 2B.(i&ii) is used as the precharge tran­
sistor, where the source is connected to the Vdd, and the drain is
connected to the victim net. Another end of the victim net is connected
to a buffer to achieve the AND and OR gate. Fig. 2B.iii shows that ES
Fig. 2. Different Crosstalk circuits based on signal transition. A) Positive Transition Crosstalk Circuits, B) Negative Transition Crosstalk Circuit, C) Dual Transition
Crosstalk Circuits.
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Integration 84 (2022) 62–71
state in Negative transition gates, i.e. when the Discharge signal is high
(opposite to Positive Transition gates).
It can be noticed from the schematic figures that the margin func­
tions of Crosstalk Negative transition gates (AND and OR) are in com­
plement to Positive transition Crosstalk Gates. CTM (CND) for AND gate
specifies that the output flips its state from 1 to 0 (as initial output state
is 1) when victim net experiences 1 → 0 transitions from a total coupling
capacitance greater than or equal to CND, which happens when either
one or both of the transition of the input from 1 → 0. Similarly, CTM
(2CNR) for OR gate states that the output is 0 only when the victim net
experiences 1 → 0 transitions from a total coupling capacitance greater
than or equal to 2CNR, which happens only when the transition of the
input from 1 → 0. Also, the coupling strength CND > CNR in case of the
negative transition Crosstalk gates, whereas CNR > CND in case of Posi­
tive transition Crosstalk gates. This is because previous stage gates will
maintain the initial state of 1 on input aggressors.
3.3. Dual Transition Crosstalk Circuits
The dual transition Crosstalk Circuits leverage both high-to-low and
low-to-high signal transition types for logic implementation purposes. In
this mechanism, both positive and negative transition aggressors co-
exist within the single gate. In Fig. 2C.(i)&(ii), the blue indicates a
positive transition net with 0 as the initial state. The green color in­
dicates a negative transition gate having logic 1 as the initial state. The
main differences in AND and OR gates are the arrangement of the
Discharge transistor and initial states of the Vi node and aggressors. As
depicted in Fig. 2C.i, the AND gate uses a discharge transistor (NMOS
connected to the GND), and the OR gate (Fig. 2C.ii) uses a precharge
transistor (PMOS connected to the VDD). Fig. 2C.iii shows the simula­
tion response of AND and OR gates with the correct functional response.
In both circuits, the initial state of input A is logic 0, and the initial
state of input B is logic 1. Input A adds the charge when input logic is 1,
while input B removes the charge when input logic is 0. Therefore, A and
B do not affect the Vi net when their input logic levels are 0 and 1,
respectively. These inputs maintain their previous logic levels from
initial states, leading to no signal transitions (therefore no output
change). Margin function for AND gate is CTM(CND), which means 0 → 1
transition on input A (note that input B experiences only 1 → 0 but not 0
→ 1 in ES state due to its initial state 1) can flip the inverter state pro­
vided the B does transition in the negative direction (1 → 0) and subtract
the charge. This can happen only during 11 input combinations (on A
and B), thus enables the AND gate design. The margin function for OR
gate is CTM (CNR), which means 1 → 0 transitions on input B (A never
transitions 1 → 0 in ES state) can flip the inverter provided the input A
does not transition in the positive direction (0 → 1); this can happen only
during 00 input combinations (on A and B), thus enables the OR gate
design. Note that input A never transitions 1 → 0 in ES state.
N.K. Macha et al.
3.4. Bypass branch circuits
Crosstalk circuits are analogous to the Perceptron model [6], where
the weighted summation of input variables passed through an activation
function defines the output. The crosstalk signal interference on the Vi
net through different coupling strengths is equivalent to weighted input
variable summation, and the activation function is the threshold func­
tion of the inverter. It is impossible to implement linearly inseparable
logic functions (XOR, etc.) with a single Perceptron. However, we can
cleverly fix the inseparable problem by using bypass branch circuits and
achieved single-stage XOR circuits. As shown in Fig. 3, the bypass
branch uses stacked PMOS or NMOS transistors acting as AND logic.
Four different bypass circuit styles are proposed and show in Fig. 3.
Without a bypass branch, Fig. 3.i shows just a NAND gate (evident from
its margin function CTM(2CXR)). NAND gate can be converted to XOR if
the gate is somehow tricked for 00 input combination to give 0 as the
output instead of 1. During ES state (Fig. 3i), when A = 0 and B = 0, the
two PMOS transistors turn on and pull the Vi node to 1 instead of 0 based
on Crosstalk Computing. Thus, the gate behaves as an XOR gate (at node
F) instead of the NAND gate.
Similarly, Fig. 3.ii is a NOR gate (evident from its margin function
CTM(CXNR)). NOR gate can be converted to XNOR if the gate is somehow
tricked for 11 input combinations to give 1 as the output instead of 0.
During ES state (Fig. 3.ii), when A = 1 and B = 1, the two NMOS tran­
sistors turn on and pull the Vi node to 0 instead of 1 based on Crosstalk
Computing. Thus, the gate behaves as an XNOR gate (at node F) instead
of AND gate. Fig. 3.iii & Fig. 3.iv are XNOR and XOR gates similar to the
last two gates, but the bypass branch is now implemented on the
aggressor side instead of the Vi node. Fig. 3.v shows the simulation result
of XOR and XNOR gate using the bypass branch circuit styles. For all
cases, the extra transistor driven by the Dis signal in the bypass branch
avoids VDD and GND shorts possible during the DS state (when Dis = 1).
Though the simulation responses are functionally correct, such
stacking or bypass branch mechanism has one main disadvantage:
leakage current through the bypass branch. When the Vi node floats
during the ES state, the leakage current seeps through the bypass branch
and accumulates as the unwanted charge on the Vi node, leading to logic
failure over time. However, this can be overcome by tightening the
timing window of the ES state, which in turn constricts the overall
timing constraints. Moreover, this technique increases the transistor
overhead due to the bypass branch. Finally, it also increases the delay
due to stacking, which are the trade-offs to achieving single-stage non-
linear logic gates.
4. Cascading circuit aspects
4.1. Cascading circuit issues
The cascading of Crosstalk circuits requires special attention.
Crosstalk circuits bring in certain transition constraints that necessitate
additional circuit techniques in cascaded circuit topology. As seen in
Fig. 3. Bypass branch Crosstalk circuits. i-iv) Circuit schematics, v) Simulation response.
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Integration 84 (2022) 62–71
previous sections, for correct logic evaluation, both aggressor and victim
nodes need to be either at zero or high before the evaluation period (in
DS state) and undergo high (0 → 1) or low (1 → 0) transitions, respec­
tively. In above discussions, the initial state requirement for the Vi node
is addressed by the discharge/precharge transistor. However, the initial
state requirement for input aggressors is mentioned to be taken care of
by the previous stage-gate or an additional circuit. We will discuss these
requirements for three kinds of Crosstalk circuits: positive, negative, and
dual transition Crosstalk circuits.
For positive transition gates (shown in blue), input aggressors must
initially be at logic 0 in the DS state. This requirement is automatically
met if non-inverting logic gates drive the given gate (AND, OR, etc.), as
shown in Fig. 4.i; this is because the output for all non-inverting gates in
CT circuits is the output is 0 in the DS state. Conversely, if the gate is
driven by inverting gates as shown in Fig. 4.ii, the driving gates’ DS state
outputs are 1. Therefore, if the following ES state evaluates to logic 1,
the input aggressor has no 0 → 1 transition (it remains 1 → 1). Hence,
logic 1 will not be detected for logic computation in the gate, leading to
incorrect output. Such connection of gates and corresponding nodes can
be called initial-state mismatch-nodes (in this case, logic 0 mismatch-
nodes). Initial-state mismatch nodes will be simply called mismatch
nodes in the subsequent discussion.
Similarly, for negative transition CT-gates, all input aggressors
require 1 as the initial state. For dual transition Crosstalk gates, some
input aggressors require 1 as the initial state and others 0. As shown in
Fig. 4.iii, inverting gates driving the negative transition gate (shown in
green color) inputs automatically meet the initial state requirement (i.e.,
1), but, as shown in Fig. 4.iv, if non-inverting gate drives these inputs,
there will be again state mismatch (logic 1 mismatch-nodes), leading to
logic failures. Because the practical circuits have many such cascaded
configurations/connection points, we can formulate two rules which
will enable functionally correct cascaded circuits. First, we observe that
all crosstalk gates have an initial state (0 or 1) for their input and output
nodes. Therefore, rule number one is to connect two nodes (output pin to
input pin or pin to an input pin) only if their initial states match. As
mismatch-nodes are inevitable in practical circuits, rule number two is
that any mismatch-nodes should be connected through some auxiliary
interface circuits that can fix the mismatch problem.
5. Solutions to fix mismatch nodes
This section presents three types of solutions that are incrementally
optimal. The first technique is to use some auxiliary/additional circuits
at mismatch node interfaces. The second technique is to leverage
different Crosstalk Circuit types (positive, negative, and dual transition
gates) to fix the mismatch nodes automatically. Finally, the third tech­
nique is to modify the CMOS inverter in Crosstalk circuits such that the
mismatch nodes at the output are fixed inherently. Thus, we can
simultaneously employ all these techniques for optimal circuit design.
N.K. Macha et al. Integration 84 (2022) 62–71

Fig. 4. Cascading Circuit issues: i) No Transition issue by connecting nodes with same initial state (0) ii) Mismatch node by connecting initial-state-one output to
initial-state-zero input iii) No Transition issue by connecting nodes with same initial-state (1) iv) Mismatch node by connecting initial-state-zero output to initial
state-one input.

5.1. Auxiliary initializer circuits to fix mismatch nodes

As these auxiliary circuits’ primary purpose is to initialize the input

aggressor nodes to the required logic state (0 or 1), it is appropriate to
call them initializers. Fig. 5 shows all the proposed auxiliary initializers.
Fig. 5.i shows the Input-Low-Initializer (ILI) to fix logic 0 mismatch
nodes, and Fig. 5.ii shows the Input-High-Initializer (IHI) to fix logic 1
mismatch nodes. The initializer circuit is a combination of a trans­
mission gate and discharge/precharge transistors. The transmission
gates in both the circuits (Fig. 5.i&ii)) turn off in the DS state and thus
isolates the input aggressor node (Ag) from the mismatch signal driven
by the previous stage-gate (Dr). In the case of ILI (Fig. 5i), the NMOS will
tie the Ag node to logic-low in DS state, ensuring that the next state
gate’s input aggressor receives only logic-low in DS state.
Similarly, in IHI, the PMOS transistor will tie the Ag node to logic-
high in the DS state. Fig. 5.iii&iv shows how ILI and IHI circuits can
be employed to fix the circuits in Fig. 4.ii&iv, respectively. Fig. 5.v&vi
are regenerative versions of ILI and IHI circuits. The only difference is
that they use tristate-inverter in place of transmission gate; thus, they
can be employed in circuit scenarios where drive-strength and signal-
Fig. 6. Cascading Circuit issues and solutions: i) Logic 1 mismatch node, ii)
integrity are the concerns (for example, when fanout is large). Employing ILI circuit to fix mismatch node, iii) Simulation response of
Next, the mismatch node issue and its fixture using the initializer the circuits.
circuit are demonstrated through simulations. Fig. 6.i shows a logic 1
mismatch node (node X) where the NAND gate drives an AND gate.
the ILI circuit used.
Fig. 6.ii employs an ILI circuit to fix the logic 1 mismatch node. Finally,
Fig. 6.iii shows the simulation responses. Panel-3 and panel-4 (from top)
correspond to output (Y) of Fig. 6.(i&ii), respectively. It can be observed 5.2. Leveraging positive, negative, and dual transition gates to fix
from panel-3 that the output always remains zero, showing incorrect mismatch nodes
logic behavior because node X never sees the 0 → 1 transition required to
detect logic 1 by the next stage AND gate (which is a positive transition Though IHI and ILI circuits fix the mismatch-node problems, they
gate). However, in panel-4 correct logic behavior is achieved because of add additional circuitry as each of these circuits requires 3 additional

Fig. 5. Initializers: i) Input-Low-Initializer ii) Input-High-Initializer iii) Using ILI iv) Using IHI v) Regenerative ILI vi) Regenerative IHI vii) in-built output low
initializer viii) in-built output high initializer.

66
N.K. Macha et al.
transistors. We can overcome this circuit overhead by combining posi­
tive, negative, and dual transition Crosstalk gates. We have seen that the
initial states (inputs and output) of the negative transition gate com­
plement a positive transition gate. That means, when we have a
mismatch node, we can alternately swap one of the gates (driver or load)
to a different transition gate and thus fix the mismatch problem. For
example, we can swap a positive transition gate to a negative transition
gate. Fig. 7 shows three common circuit configurations, column A: i, ii,
and iii, for which either driver or load gates can be swapped to negative
transition gates (Column C–H). A few combinations turn out to be legal
connections (shown with red right mark), while others are illegal con­
nections (shown with red cross mark) because of the mismatch nodes. In
case-I (first row), both the driver gates are non-inverting logic types (two
AND gates).
The output of both the AND gates is connected to the OR gate. As all
three gates in case-iA are positive transition gates (i.e., low to high
transition) and have 0 initial states for all the nodes, such cascading will
maintain proper functionality. However, in case-ii (second row) and
case-iii (third row), one or both the driver gates are inverting logic gates
(NAND), respectively. These inverting gates create mismatch nodes, as
discussed in the previous section. ILIs (Input Low Initializers) can be
used to avoid these mismatch nodes, as shown in case-iiB and case-iiiB.
These ILIs will ensure that the corresponding input aggressor sees the 0
→ 1 transition during every ES state. However, such initializers increase
the transistor count.
Alternately, circuit cases in column C–H show the swapping of driver
or load gates to negative transition gates, thus removing the need for ILI
circuits as in the circuit cases of column B. The column C–H circuit
configurations are combinations of positive and negative transition
gates (including legal and illegal connections) to achieve the same logic
as the base cases/configurations, iA, iiA, and iiiA. For example, in Case-I
(first row), i.A and i.H are the legal connections, but all other combi­
nations, i.C-i.G, lead to mismatch-nodes, hence illegal. That is, a positive
transition load gate (having 0 initial states for inputs) can only have all
non-inverting positive transition gates as drivers (Fig. 7i. A) but not one
or more negative transition non-inverting gates as in i.C and i.D (green-
color gates). Similarly, a negative transition load gate (having 1 initial
state for inputs) can only have all negative transition non-inverting gates
as inputs (i.H) but not one or more positive transition gates as in i.E, i.F,
and i.G (blue-color gates).
The case-ii (second row) describes the solution to connect one
inverting gate and non-inverting gates as inputs to a non-inverting gate.
ii.B applies the ILI circuit, but ii.C and ii.D alternately use positive and
negative transition gates to fix the mismatch-node problem. All other
possible combinations (ii.E-ii.H) are illegal. That is, as shown in ii.C, the
inverting input gate can be swapped to a negative transition gate (green
Fig. 7. Legal and illegal connections for cascading Crosstalk circuits.
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Integration 84 (2022) 62–71
colored gate), or, as shown in ii.D, the inverting input gate can remain as
a positive transition gate (blue colored). However, the other two gates
(input and load gate) are switched to negative transition gates (green
colored). Any other combinations in ii.E-iiH will not work. Finally, as
shown in iii.A, there are three solutions if all the inputs (here 2 inputs)
are driven by inverting gates. First, as shown in iii.B, we can add ILI
circuits between each driver and load gate. Second, as shown in iii.C, we
can switch the input inverting gates to negative transition gates (green
color gates). Third, as shown in iii.D, we can swap the loading gate
instead to a negative transition gate (green colored gate). All other
combinations, iii.E-iii.H, should be avoided. Thus, we can see that six
transistors overhead brought in by auxiliary circuits can be reclaimed by
using positive, negative, and dual transition Crosstalk gates in
combination.
The next example shows the usage of a dual-transition gate to
reclaim three transistors. Fig. 8 shows two different cascading styles for
implementing a Full Adder. In Fig. 8i, ILI is used for connecting inverted
Carry output to one of the inputs of the SUM circuit. This circuit needs
thirteen transistors in total, where three transistors are needed for the ILI
circuit. However, the same Full Adder can be implemented, as shown in
Fig. 8.ii, using only ten transistors by leveraging a dual transition type
SUM circuit.
The above circuit scenarios have a fanout of 2, but practical circuits
will also have a fanout greater than two. Fig. 9.i.A & 9.ii.A show fanout
cases in which we have conflicting initial state requirements from
different load gates. When we swap the positive transition gates with
negative transition gates in the circuits (to avoid initializer circuits), we
might arrive at a node with conflicting requirements. A few of the fanout
gates might demand a positive transition type driver gate. The remain­
ing gates can demand a negative transition type driver gate. Fig. 9.i.A &
9.ii.A show two such scenarios. Fanout gates G1 and G2 have mismatch-
nodes in two cases. In both cases, if we swap the driver gate (GDr) to a
negative transition type, as shown in Fig. 9.i.B & 9.ii.B, to fix the
mismatch node issue, the inputs of the other two gates, G3 and G4, will
turn out to be mismatch-nodes. In such a conflicting scenario, we can
resort to the initializer circuits as shown in Fig. 9.i.C & 9.ii.C. In Fig. 9.i.
C, all the negative transition gates’ inputs are grouped and driven
through a single IHI circuit. Similarly, in Fig. 9.ii.C, all the positive
transition gates’ inputs are grouped and driven through a single ILI
circuit. As drive strength can concern these ILI and IHI circuits in large
fanout scenarios, we can employ ILI and IHI circuits’ regenerative ver­
sions (Fig. 5.v&vi).
5.3. Crosstalk circuits with inherent output initializers
The Initializer circuit (ILI or IHI) can be merged with the CMOS
N.K. Macha et al. Integration 84 (2022) 62–71

Fig. 8. Two different cascading styles for implementing Full Adder. i) Implementation of Full Adder using initializers, ii) Implementation of Full Adder using dual
transition SUM circuit.

Fig. 9. Fan-out configuration for Crosstalk circuits.

inverter of the Crosstalk gate and form an inherent output initializer
circuit, as shown in Fig. 10. Fig. 10.i shows the Output Low Initializer
(OLI), where the NMOS discharge transistor connected at the output and
gated by Dis makes sure the output is 0 in DS (Dis = 1) state irrespective
of the Vi node initial state. The complementary PMOS transistor (gate by
Dis) in the circuit avoids the simultaneous turn-on of PMOS and NMOS
branches. This circuit technique automatically pulls all downstream
fanout aggressors to the ground, ensuring 0 → 1 transition in every ES
state.
Similarly, Fig. 10.ii shows the Output High Initializer (OHI), where
the precharge (PMOS) transistor connected at the output and gated by
the Dis’ signal will pull the output to 1 irrespective of Vi node signal
level. All down-stream fanout aggressors are automatically pulled to 1
using this circuit technique, ensuring 1 → 0 transitions in every ES state.
The in-built initializer circuits reduce the transistor count compared to
the previous two techniques and are also regenerative.
Fig. 10.iii shows the Crosstalk circuit using OLI. This circuit inher­
ently fixes all the cascading problems discussed in previous sections. The
circuit operates as follows. First, in every DS state, the Vi net is dis­
charged/initialized to ground through the M1 transistor, M2 is OFF, M3

68
N.K. Macha et al.
Fig. 10. i) Output Low Initializer (OLI), ii) Output High Initializer (OHI), iii) Crosstalk Gate with inherent output low initializer.
is ON, but the Dis signal will turn OFF the Pullup branch by turning OFF
M4 transistor. Now, the M5 turns ON and shorts the output node FI to the
ground; thus, the gate’s output, in turn, input aggressor/aggressors of
next stage gate/gates are initialized to 0.
It should be noticed that all nodes (Vi, FI, next stage input) that
require the initial state in the Crosstalk circuits will be automatically
initialized 0 using this circuit style (Fig. 9.iii). Thus, all circuits can be
connected freely without additional constraints or auxiliary circuits for
functional correctness using Crosstalk gates. Fig. 10.iii implements
inverting logic functions. For non-inverting logic functions, we will use
plane circuits discussed above because they inherently create an initial
state as 0 due to the two inverters connected on the Vi net. This circuit
also enables the Crosstalk circuits to be compatible with existing Syn­
thesis tools. The Place-and-Route (PnR) flows with only one additional
requirement of routing the Dis signal, which can be done through a
special route step. Thus, we can realize the crosstalk standard cell library
and use them similar to CMOS cell library in ASIC design flow and
Physical Design tools.
6. Example of large-scale implementation of Crosstalk circuits
We have implemented Crosstalk polymorphic logic gates in
Ref. [22], which can alter their logic behavior based on a control signal.
We show large-scale circuit implementation in this section using the
basic Crosstalk gates, Crosstalk polymorphic gates, and the design
techniques explained in the earlier sections. Different circuits such as
MCNC Benchmarking circuits [24] and 2-bit polymorphic
multiplier-adder-sorter [13] are designed. Fig. 10 shows the example of
two different large-scale circuit blocks, multiplier-adder-sorter circuit &
cm85a circuits from MCNC benchmarking suits [21]. Implementing
large circuits using Crosstalk gates requires attention on two aspects, i)
avoiding any possible mismatch nodes ii) maintaining signal integrity
and drive strength for the next stage gates. While mismatch nodes can be
avoided by using the circuit techniques discussed above, signal-integrity
and drive-strength requirements can be addressed by using repeaters (i.
e., CMOS inverters/buffers) at the output of CT-gates. The strength of
the repeater depends on the fanout load.
As shown in Fig. 10ii, Crosstalk gates are driving two fanout loads of
higher coupling capacitances at the second stage. We have also used the
initializer circuits to fix the mismatch-node problem. In Fig. 10ii, at the
third stage, a CT-NOR gate GNr (an inverting logic gate) drives the next
stage CT-homogenous gate Xm1. During DS state, it receives a logic high
carried to the next LE state, preventing the signal transition from 0 to 1,
leading to logic failure. This issue is resolved by using an initializer. An
ILI circuit is placed between inverting and non-inverting gate interfaces.
During the DS state, though the NOR (GNr) output is 1, the ILI circuit
(GI1) clamps the corresponding input aggressor to 0. The input signal is
passed through the ILI; thus, if logic evaluates to 1, the signal transitions
from 0 to 1. Another issue that few CT circuits face is insufficient
aggressor coupling strength to induce sufficient voltage to trip the
inverter.
For example, in the case of the CT-OR3 gate, the output needs to go
high even when any one of the inputs is one. That means a single input
69
Integration 84 (2022) 62–71
aggressor transition should induce a sufficient voltage on the Vi net to
trip the inverter. However, as net voltage induced on Vi net follows the
voltage division rule, increasing the coupling strengths will not solve the
problem. Instead, all the input aggressor couplings need to be increased;
equally, their ratio remains the same. Hence voltage induced remains
the same. This design conundrum can be solved by using the lower
threshold voltage transistors that bring down the inverter’s trip-point or
skewing the inverter, i.e., sizing PMOS and NMOS differently.
Fig. 10iii& iv show the simulation response of Multiplier-Adder-Sorter
and cm85a circuits, respectively. We can observe that the correct logic
functionality is maintained at all output nodes. As such, any large-scale
circuit can be implemented using CT-gates in this manner while main­
taining correct circuit functionality and achieving improved density,
power, and performance.
7. Benchmarking results and potential applications
Using these primitive logic gates and circuit styles discussed above,
we have designed larger circuits like cm85a, mux, and pcle from MCNC
benchmark suite, polymorphic Multiplier-Sorter-Adder unit, and
compared the results with CMOS at 7 nm. Compared to the CMOS, the
PPA (Power, Performance, and Area) benefits are significant for Cross­
talk logic-based implementations. Table 1 shows that the polymorphic
logic gates have over 6x the density, ~1.5x performance, and ~1.5x EDP
benefits. The benefits are primarily due to reduced transistor count.
They are projected to be higher for other large-scale designs by
leveraging Crosstalk Complex and Polymorphic logic gates [26]. The
benefits for the polymorphic Multiplier-Sorter-Adder unit were 3.4x,
70.5% in terms of density, and EDP with comparable performance to
CMOS. For cm85a and pcle circuits, the reduction in transistor count is
59% and 23%, respectively. As a result, crosstalk circuits show on
average 62% EDP benefits over CMOS counterparts. The benefits are
primarily due to the reduction in transistor count. However, the
reduction in EDP for the mux and pcle circuits is not much even though
transistor count reduction is maximum compared to other circuits. This
is because the implementation of the circuit requires many initializer
circuits, resulting in more switching activities, hence, less power
reduction and paying the performance penalty.
On the contrary, for the Adder-Sorter-Multiplier and cm85a circuit,
EDP reductions are more because they require less Buffer and initializer
circuits, hence less switching activity. The effect can also be seen for
performance (Table 1), where the pcle circuit shows better performance
than CMOS circuits. For example, the Crosstalk Adder-Multiplier-Sorter,
cm85a, and pcle circuits show 11%, 10%, and 53% improvement in
performance, respectively.
For proof of concepts, we have realized the Crosstalk computing el­
ements using MOSCAP available at TSMC 65 nm PDK. However, we
need Crosstalk-specific process innovations to realize the Crosstalk cir­
cuits efficiently. For that, we propose capacitance engineering between
input and output for Crosstalk circuits and should be placed in 3-D in
upper metal layers as shown in Fig. 1A. Depending on logic, the value
can range from 400 aF to a few fFs (calculated at 16 nm node). We
propose a 3-D organization to maximize density gains, where transistors
N.K. Macha et al. Integration 84 (2022) 62–71

Table 1
Benchmarking results at 7 nm.
27
MCNC Benchmark Circuits I/O Transistor Count Energy Delay Product (EDP) (x10− J s) Performance (ps)

CMOS Crosstalk CMOS Crosstalk %Reduction CMOS Crosstalk %Reduction CMOS Crosstalk %Reduction

Adder-Sorter-Multiplier 4/4 4/4 408 155 25 61.27 18.06 70.50 61.50 54.4 11.56
Cm85a 11/3 11/3 168 69 59.00 26.99 10.37 61.60 21.10 18.93 10.28
Mux 21/1 21/1 506 190 62.45 6.55 4.86 25.80 9.43 12.75 − 35.2
Pcle 19/9 19/9 328 252 23.17 6.51 5.50 91.60 15.04 7.07 53.00

are positioned in the bottom layer for control, and metals and engi­
neered capacitances are positioned in the 2nd Metal layer for
computing. We have done preliminary research and proposed 3-D
arrangement and choice of materials to obtain the required capaci­
tance. Our initial investigations revealed we could achieve the capaci­
tances required for Crosstalk circuits in a small footprint by 3-D device
and material innovations.
8. Conclusion
This paper presents different circuit styles utilizing the Crosstalk
Computing technique for large-scale design implementation. We have
also identified the cascading issues face by Crosstalk computing and
provided a lists solution to address those issues. Using the circuit
implement techniques discussed in this paper, we have also imple­
mented different large-scale circuits and benchmarked them with their
CMOS counterparts. Our benchmark results show promises for large-
scale design implementation. These results and framework for large-
scale circuit design can pave the way for the future adoption of Cross­
talk computing technology.
Author contribution
Naveen Kumar Macha: Conceptualization, Methodology, Formal
analysis, Validation, Visualization, Writing – review & editing. Md Arif
Iqbal: Conceptualization, Formal analysis, Investigation, Validation,
Data curation, Writing – original draft Bhavana Tejaswini Repalle:
Simulation, Validation, Visualization, Writing – review & editing Mos­
tafizur Rahman: contributed to Conceptualization, Project administra­
tion, and Supervision, Writing – review & editing.
Declaration of competing interest
The authors declare that they have no known competing financial
interests or personal relationships that could have appeared to influence
the work reported in this paper.
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