Verilog HDL Lab Codes

H. K. E.
Society’s
PDA College of Engineering, Kalaburagi
Department of Electronics and Communication Engineering
Digital Design Using Verilog HDL Laboratory (19ECL61)

Experiment 1
Verilog Code for all basic and universal gates
Main code:
module gates(
input a,b, //input ports
output m,n,o,p,q,r,s); //output ports
assign m=~a; //NOT gate
assign n=a&b; //AND gate
assign o=a|b; //OR gate
assign p=a^b; //XOR gate
assign q=~(a&b); //NAND gate
assign r=~(a|b); //NOR gate
assign s=~(a^b); //XNOR gate
endmodule
Testbench:
Module gates_tf(a,b,m,n,o,p,q,r,s);
reg a,b; //Input ports
wire m,n,o,p,q,r,s; //Output ports
gates uut(.a(a),.b(b),.m(m),.n(n),.o(o),.p(p),.q(q),.r(r),.s(s)); //Instantiating the module gates
initial begin
a=0;b=0;#20; //stimulus
a=0;b=1;#20;
a=1;b=0;#20;
a=1;b=1;#20;
$stop;
end
endmodule
H. K. E. Society’s
Experiment 2
Verilog Code for Combinational Circuits
Half Adder:
Main Code:
module ha(
input a,b, //input ports
output s,ca); //output ports
assign s=a^b; //expression for sum
assign ca=a&b; //expression for carry
endmodule
Testbench:
module ha_tf(a,b,s,ca);
reg a,b; //Input ports
wire s,ca; //Output ports
ha uut(.a(a),.b(b),.s(s),.ca(ca)); //Instantiating the module ha
initial begin
a=0;b=0;#20; //Stimulus
a=0;b=1;#20;
a=1;b=0;#20;
a=1;b=1;#20;
$stop;
end
endmodule
Half Subtractor:
Main Code:
module hs(
input a,b,
output d,br);
assign d=a^b; //expression for difference
assign br=~a&b; //expression for borrow
endmodule
Testbench:
module hs_tf(a,b,d,br);
reg a,b;
wire d,br;
hs uut(.a(a),.b(b),.d(d),.br(br));
initial begin
a=0;b=0;#20;
a=0;b=1;#20;
a=1;b=0;#20;
a=1;b=1;#20;
$stop;
end
endmodule
2:1 Multiplexer:
Main Code:
module mux(
input a,b,sel,
output y);
assign y=((~sel)&a)|(sel&b); //expression for multiplexer output
endmodule
Testbench:
module mux_tf(a,b,sel,y);
reg a,b,sel;
wire y;
mux uut(.a(a),.b(b),.sel(sel),.y(y));
initial begin
sel=0;a=0;b=0;#20;
sel=0;a=0;b=1;#20;
sel=0;a=1;b=0;#20;
sel=0;a=1;b=1;#20;
sel=1;a=0;b=0;#20;
sel=1;a=0;b=1;#20;
sel=1;a=1;b=0;#20;
sel=1;a=1;b=1;#20;
$stop;
end
endmodule
1:2 Demultiplexer:
Main Code:
module demux(
input a,sel,
output y1,y2);
assign y1=(~sel)&a; //expression for demultiplexer output
assign y2=sel&a; //expression for demultiplexer output
endmodule
Testbench:
module demux_tf(a,sel,y1,y2);
reg a,sel;
wire y1,y2;
demux uut(.a(a),.sel(sel),.y1(y1),.y2(y2));
initial begin
sel=0;a=0;#20;
sel=0;a=1;#20;
sel=1;a=0;#20;
sel=1;a=1;#20;
end
endmodule
4:2 Encoder:
Main code:
module enc_4to2(
input i3,i2,i1,i0,
output f1,f0);
assign f1=((~i3)&(i2)&(~i1)&(~i0))|((i3)&(~i2)&(~i1)&(~i0)); //expression for encoder output
assign f0=((~i3)&(~i2)&(i1)&(~i0))|((i3)&(~i2)&(~i1)&(~i0));//expression for encoder output
endmodule
Testbench:
module enc_4to2_tf(i3,i2,i1,i0,f1,f0);
reg i3,i2,i1,i0;
wire f1,f0;
enc_4to2 uut(.i3(i3),.i2(i2),.i1(i1),.i0(i0),.f1(f1),.f0(f0));
initial begin
i3=0;i2=0;i1=0;i0=1;#20;
i3=0;i2=0;i1=1;i0=0;#20;
i3=0;i2=1;i1=0;i0=0;#20;
i3=1;i2=0;i1=0;i0=0;#20;
$stop;
end
endmodule
2:4 Decoder:
Main Code:
module dec_2to4(
input i1,i0,
output f3,f2,f1,f0);
assign f0=(~i1)&(~i0);
assign f1=(~i1)&(i0);
assign f2=(i1)&(~i0);
assign f3=(i1)&(i0);
endmodule
Testbench:
module dec_2to4_tf(i1,i0,f3,f2,f1,f0);
reg i1,i0;
wire f3,f2,f1,f0;
dec_2to4 uut(.i1(i1),.i0(i0),.f3(f3),.f2(f2),.f1(f1),.f0(f0));
initial begin
i1=1;i0=1;#20;
i1=1;i0=0;#20;
i1=0;i0=1;#20;
i1=0;i0=0;#20;
end
endmodule
Experiment 3
Verilog Code for 1-bit Full Adder and Full Subtractor in all 3 modeling
styles
1-bit Full Adder in Dataflow modeling:

module fa_df(
input a,b,c,
output sum,carry);
assign sum=a^b^c;
assign carry=(a&b)|((a^b)&c);
endmodule
Testbench:
module fa_df_tf(a,b,c,sum,carry);
reg a,b,c;
wire sum,carry;
fa_df uut(.a(a),.b(b),.c(c),.sum(sum),.carry(carry));
initial begin
a=0;b=0;c=0;#20;
a=0;b=0;c=1;#20;
a=0;b=1;c=0;#20;
a=0;b=1;c=1;#20;
a=1;b=0;c=0;#20;
a=1;b=1;c=1;#20;
a=1;b=0;c=0;#20;
a=1;b=1;c=1;#20;
end
endmodule
1-bit Full Adder in Behavioral modeling:

module fa_bh(
input a,b,c,
output reg sum,carry);
always @ (a or b or c)
begin
sum=a^b^c;
carry=(a&b)|((a^b)&c);
end
endmodule
Testbench:
module fa_bh_tf(a,b,c,sum,carry);
reg a,b,c;
wire sum,carry;
fa_bh uut(.a(a),.b(b),.c(c),.sum(sum),.carry(carry));
initial begin
a=0;b=0;c=0;#20;
a=0;b=0;c=1;#20;
a=0;b=1;c=0;#20;
a=0;b=1;c=1;#20;
a=1;b=0;c=0;#20;
a=1;b=1;c=1;#20;
a=1;b=0;c=0;#20;
a=1;b=1;c=1;#20;
end
endmodule
1-bit Full Adder in Structural modeling:

module fa_st(
input a,b,c,
output sum,carry);
wire c1,c2,c3;
xor(c1,a,b);
and(c2,a,b);
xor(sum,c1,c);
and(c3,c1,c);
or(carry,c3,c1);
endmodule
Testbench:
module fa_st_tf(a,b,c,sum,carry);
reg a,b,c;
wire sum,carry;
fa_st uut(.a(a),.b(b),.c(c),.sum(sum),.carry(carry));
initial begin
a=0;b=0;c=0;#20;
a=0;b=0;c=1;#20;
a=0;b=1;c=0;#20;
a=0;b=1;c=1;#20;
a=1;b=0;c=0;#20;
a=1;b=1;c=1;#20;
a=1;b=0;c=0;#20;
a=1;b=1;c=1;#20;
end
endmodule
1-bit Full Subtractor in Dataflow modeling:

module fs_df(
input a,b,c,
output diff,br);
assign diff=a^b^c;
assign br=((~a)&b)|(~(a^b)&c);
endmodule
Testbench:
module fs_df_tf(a,b,c,sum,carry);
reg a,b,c;
wire sum,carry;
fs_df uut(.a(a),.b(b),.c(c),.diff(diff),.br(br));
initial begin
a=0;b=0;c=0;#20;
a=0;b=0;c=1;#20;
a=0;b=1;c=0;#20;
a=0;b=1;c=1;#20;
a=1;b=0;c=0;#20;
a=1;b=1;c=1;#20;
a=1;b=0;c=0;#20;
a=1;b=1;c=1;#20;
end
endmodule
1-bit Full Subtractor in Behavioral modeling:

module fs_bh(
input a,b,c,
output diff,br);
always @ (a or b or c)
begin
diff=a^b^c;
br=((~a)&b)|(~(a^b)&c);
end
endmodule
Testbench:
module fs_bh_tf(a,b,c,sum,carry);
reg a,b,c;
wire sum,carry;
fs_bh uut(.a(a),.b(b),.c(c),.diff(diff),.br(br));
initial begin
a=0;b=0;c=0;#20;
a=0;b=0;c=1;#20;
a=0;b=1;c=0;#20;
a=0;b=1;c=1;#20;
a=1;b=0;c=0;#20;
a=1;b=1;c=1;#20;
a=1;b=0;c=0;#20;
a=1;b=1;c=1;#20;
end
endmodule
1-bit Full Subtractor in Structural modeling:

module fs_st(
input a,b,c,
output diff,br);
wire d1,a1,b1,a2,b2;
xor(d1,a,b);
not(a1,a);
and(b1,a1,b);
xor(diff,d1,c);
not(a2,d1);
and(b2,a2,c);
or(br,b1,b2);
endmodule
Testbench:
module fs_df_tf(a,b,c,sum,carry);
reg a,b,c;
wire sum,carry;
fs_df uut(.a(a),.b(b),.c(c),.diff(diff),.br(br));
initial begin
a=0;b=0;c=0;#20;
a=0;b=0;c=1;#20;
a=0;b=1;c=0;#20;
a=0;b=1;c=1;#20;
a=1;b=0;c=0;#20;
a=1;b=1;c=1;#20;
a=1;b=0;c=0;#20;
a=1;b=1;c=1;#20;
end
endmodule
Experiment 4
Verilog Code for 4-bit Full Adder/Subtractor using 1-bit Full

adder/subtractor designed in previous experiment
4-bit Full Adder:
module fa(
input a,b,c,
output sum,carry);
assign sum=a^b^c;
assign carry=(a&b)|((a^b)&c);
endmodule
module fa_4b(
input [3:0] a,b,
input c,
output [3:0] sum,
output carry);
wire c1,c2,c3;
fa fa0(.sum(sum[0]),.carry(c1),.a(a[0]),.b(b[0]),.c(c));
fa fa1(.sum(sum[1]),.carry(c2),.a(a[1]),.b(b[1]),.c(c1));
fa fa2(.sum(sum[2]),.carry(c3),.a(a[2]),.b(b[2]),.c(c2));
fa fa3(.sum(sum[3]),.carry(carry),.a(a[3]),.b(b[3]),.c(c3));
endmodule
Testbench:
module fa_4b_tf(a,b,c,sum,carry);
reg [3:0] a;
reg [3:0] b;
reg c;
wire [3:0] sum;
wire carry;
fa_4b uut(.sum(sum),.carry(carry),.a(a),.b(b),.c(c));
initial begin
a=1100;b=1010;c=0;
#100;
a=1001;b=0111;c=1;
#100;
$stop;
end
endmodule
4-bit Subtractor:
module fs(
input a,b,c,
output diff,br);
assign diff=a^b^c;
assign br=((~a)&b)|(~(a^b)&c);
endmodule
module fs_4b(
input [3:0] a,b,
input c,
output [3:0] diff,
output br);
wire b1,b2,b3;
fs fs0(.diff(diff[0]),.br(b1),.a(a[0]),.b(b[0]),.c(c));
fs fs1(.diff(diff[1]),.br(b2),.a(a[1]),.b(b[1]),.c(b1));
fs fs2(.diff(diff[2]),.br(b3),.a(a[2]),.b(b[2]),.c(b2));
fs fs3(.diff(diff[3]),.br(br),.a(a[3]),.b(b[3]),.c(b3));
endmodule
Testbench:
module fs_4b_tf(a,b,c,diff,br);
reg [3:0] a;
reg [3:0] b;
reg c;
wire [3:0] diff;
wire br;
fs_4b uut(.diff(diff),.br(br),.a(a),.b(b),.c(c));
initial begin
a=1100;b=1010;c=0;
#100;
a=1001;b=0111;c=1;
#100;
$stop;
end
endmodule
Experiment 5
Verilog Code for 8-bit, 16-bit and 32-bit ALU
8-bit ALU:
module alu_8b(
input [7:0] a,b,
input [2:0] opc,
output reg [7:0] f);
always @(*)
begin
case(opc)
3’b000: begin f=a+b; $display("Addition"); end
3’b001: begin f=a-b; $display("Subtraction"); end
3’b010: begin f=a|b; $display("OR"); end
3’b011: begin f=a&b; $display("AND"); end
3’b100: begin f=a^b; $display(“XOR"); end
3’b101: begin f=~(a|b); $display("NOR"); end
3’b110: begin f=~(a&b); $display("NAND"); end
3’b111: begin f=~(a^b); $display("XNOR"); end
default:f=8’d0;
endcase
end
endmodule
Testbench:
module alu_8b_tf(a,b,opc,f);
reg [7:0]a,b;
reg [2:0] opc;
reg [2:0] count;
wire [7:0] f;
alu_8b uut(.a(a),.b(b),.opc(opc),.f(f));
initial begin
a=8’h50;b=8’h30;
for(count=0;count<4;count=count+1)
begin
opc=count;
#20;
end
end
endmodule
16-bit ALU:
module alu_4b(
input [15:0] a,b,
input [2:0] opc,
always @(*)
begin
case(opc)
default:f=16’d0;
endcase
end
endmodule
Testbench:
reg [15:0]a,b;
reg [2:0] opc;
reg [2:0] count;
wire [15:0] f;
initial begin
a=16’hAA;b=16’h55;
begin
opc=count;
#20;
end
end
endmodule
32-bit ALU:
module alu_32b(
input [31:0] a,b,
input [2:0] opc,
always @(*)
begin
case(opc)
default:f=32’d0;
endcase
end
endmodule
Testbench:
reg [31:0] a,b;
reg [2:0] opc;
reg [2:0] count;
wire [31:0] f;
initial begin
a=32’hEF;b=32’hBB;
begin
opc=count;
#20;
end
end
endmodule
Experiment 6
Verilog Code for design of SR, JK, D, T and master slave JK flip flop
SR Flip flop:
Main Code:
module srflipflop(
input s,r,clk,rst,
output reg q,qb
);
reg [1:0]sr;
always@(posedge clk,posedge rst)
begin
sr={s,r};
if(rst==0)
begin
case (sr)
2'd1:q=1'b0;
2'd2:q=1'b1;
2'd3:q=1'b1;
default: begin end
endcase
end
else
begin
q=1'b0;
end
qb=~q;
end
endmodule
Testbench:
module srff_tf;
// Inputs
reg s;
reg r;
reg clk;
reg rst;
// Outputs
wire q;
wire qb;
// Instantiate the Unit Under Test (UUT)

srflipflop uut (
.s(s),
.r(r),
.clk(clk),
.rst(rst),
.q(q),
.qb(qb)
);
initial begin
$monitor(clk,s,r,q,qb,rst);
s = 1'b0;
r = 1'b0;
rst= 1;
clk=1;
#10
rst=0;
s=1'b1;
r=1'b0;
#100
rst=0;
s=1'b0;
r=1'b1;
#100
rst=0;
s=1'b1;
r=1'b1;
#100
rst=0;
s=1'b0;
r=1'b0;
#100
rst=1;
s=1'b1;
r=1'b0;
end
always #25 clk= ~clk;
endmodule
JK Flip Flop:
Main Code:
module jkflipflop(
input clk,j,k,rst,
output reg q,
output reg qbar
);
reg [1:0] jk;
always @(posedge clk, posedge rst)

begin
jk={j,k};
if(rst==0)
begin
case(jk)
2'd1:q<=0;
2'd2:q<=1;
2'd3:q<=~q;
default: begin end
endcase
qbar=~q;
end
else
q=1'b0;
qbar=~q;
end
endmodule
Testbench:
module jk_tf;
// Inputs
reg clk;
reg j;
reg k;
reg rst;
// Outputs
wire q;
wire qbar;
always #5 clk=~clk;
jkflipflop uut (
.clk(clk),
.j(j),
.k(k),
.rst(rst),
.q(q),
.qbar(qbar)
);
initial begin
// Initialize Inputs
$monitor(clk,j,k,q,qbar,rst);
j=0;
k=0;
rst=1;
clk=1;
#10;
rst=0;
j=1;
k=0;
#100;
rst=0;
j=0;
k=1;
#100;
rst=0;
j=0;
k=0;
#100;
rst=1;
j=1;
k=0;
end
endmodule
D- Flip Flop:
Main Code:
module dff(
input d,rst,clk,
output reg q,qbar
);
always @(posedge clk,posedge rst)

begin
if(rst==0)
q=d;
else
q=0;
qbar=~q;
end
endmodule
Testbench:
module d_tf;
// Inputs
reg d;
reg rst;
reg clk;
// Outputs
wire q;
wire qbar;
always #10 clk=~clk;

dff uut (
.d(d),
.rst(rst),
.clk(clk),
.q(q),
.qbar(qbar)
);
initial begin
d = 0;
rst = 0;
clk = 0;
#100;
rst=0;
d=0;
#100;
rst=0;
d=1;
#100;
rst=1;
d=0;
#100;
rst=1;
d=1;
#100;
$stop;
end
endmodule
T – Flip Flop:
Main Code:
module tff(
input t,clk,rst,
output reg q,qbar
);
initial q=0;
always @(posedge clk)
begin
if (rst==0)
begin
q=0;
qbar=1;
end
else
begin
if(t==1)
begin
q=~q;
qbar=~qbar;
end
else
begin
q=q;
qbar=qbar;
end
end
end
endmodule
Testbench:
module t_tf;
// Inputs
reg t;
reg clk;
reg rst;
// Outputs
wire q;
wire qbar;
tff uut (
.t(t),
.clk(clk),
.rst(rst),
.q(q),
.qbar(qbar)
);
initial begin
t = 0;
clk = 0;
rst=0;
#100;
rst=0;
t=0;
#100;
rst=0;
t=1;
#100;
rst=1;
t=1;
#100;
$stop;
end
endmodule
Master Slave JK Flip Flop:

Main Code:
module masterslave(
input j,k,clk,resetn,
output q,qbar
);
wire mq,mqb,clkn,j1,k1,j2,k2;
assign j2=!resetn?0:j1;
assign k2=!resetn?1:k1;
and(j1,j,qbar);
and(k1,k,q);
not(clkn,clk);
sr_latch master(mq,mqb,clk,j2,k2);
sr_latch slave(q,qbar,clkn,mq,mqb);
endmodule
module sr_latch(
output q,qbar,
input g,s,r);
wire s1,r1;
and(s1,g,s);
and(r1,g,r);
nor(qbar,s1,q);
nor(q,r1,qbar);
endmodule
Testbench:
module msjk_tf;
// Inputs
reg clk;
reg j;
reg k;
reg resetn;
// Outputs
wire q;
wire qbar;
masterslave uut (
.clk(clk),
.j(j),
.k(k),
.resetn(resetn),
.q(q),
.qbar(qbar)
);
initial begin
clk = 1;
j = 0;
k = 0;
resetn = 1;
#20;
j=0;
k=0;
resetn=0;
#20;
j=0;
k=0;
resetn=1;
#100;
j=0;
k=1;
resetn=1;
#100;
j=1;
k=0;
resetn=1;
#100;
j=1;
k=1;
resetn=1;
end
endmodule
Experiment 7
Verilog Code for design of code converter
Binary to Gray code converter:

Main Code:
module b2g(
input [3:0] bin;
output reg [3:0] gr);
assign gr[3]=bin[3];
assign gr[2]=bin[3]^bin[2];
endmodule
Testbench:
module b2g_tf;
reg [3:0] bin;
wire [3:0] gr;
reg [3:0] i;
b2g uut(.bin(bin),.gr(gr));
initial begin
bin=4’b0;
#20;
for(i=0;i<=d15;i=i+1)
begin
bin=i;
end
end
endmodule
Gray to Binary code converter:

Main Code:
module g2b(
input [3:0] gr;
output [3:0] bin);
assign bin[3]=gr[3];
assign bin[2]=gr[3]^gr[2];
assign bin[1]=gr[3]^gr[2]^gr[1];
assign bin[0]=gr[3]^gr[2]^gr[1]^gr[0];
endmodule
Testbench:
module g2b_tf;
reg [3:0] gr;
wire [3:0] bin;
reg [3:0] i;
g2b uut(.bin(bin),.gr(gr));
initial begin
gr=4’b0;
#20;
for(i=0;i<=d15;i=i+1)
begin
gr=i;
end
end
endmodule
Experiment 8
Verilog Code for design of 4-bit binary and BCD Counter
4-bit binary up/down counter:

Main Code:
module ud_counter(
input clk,rst,up_down,
output reg [3:0] count);
initial count=0;
always @ (posedge clk)
begin
if(rst==1)
count<=0;
else
if(up_down==1)
count<=count+1;
else
count<=count-1;
end
endmodule
Testbench:
module ud_tf;
reg clk;
reg rst;
reg up_down;
wire [3:0] count;
ud_counter uut(.clk(clk),.rst(rst),.up_down(up_down),.count(count));
initial begin
clk=0;
rst=0;
up_down=0;
#20;
rst=1;
#200;
rst=0;
up_down=1;
#200;
rst=0;
up_down=0;
#200;
$stop;
end

endmodule
4-bit BCD counter:

Main Code:
module bcd_count(
input clk,rst,
output reg [3:0] count);
count=0;
begin
if(rst==0)
count<=0;
else
begin
if(count<9)
count=count+4’d1;
else
count=4’d0;
end
end
endmodule
Testbench:
module bcd_tf;
reg clk;
reg rst;
wire [3:0] count;
bcd_count uut(.clk(clk),.rst(rst),.count(count));
initial begin
clk=0;
rst=0;
#20;
rst=0;
#20;
rst=1;
#200;
$stop;
end
endmodule
4-bit Ring counter:

Main Code:
module ring_ctr #(parameter WIDTH=4)
(
input clk,
input rstn,
output reg [WIDTH-1:0] out
);
integer i;
begin
if (!rstn)
out <= 1;
else
begin
out[WIDTH-1] <= out[0];
for (i = 0; i < WIDTH-1; i=i+1)
begin
out[i] <= out[i+1];
end
end
end
endmodule
Testbench:
module tb;
parameter WIDTH = 4;
reg clk;
reg rstn;
wire [WIDTH-1:0] out;
ring_ctr uut (.clk (clk),.rstn (rstn),.out (out));
always #10 clk = ~clk;
initial begin
{clk, rstn} <= 0;
$monitor ("T=%0t out=%b", $time, out);
repeat (2) @(posedge clk);
rstn <= 1;
$finish;
end
endmodule
4-bit Johnson counter:

Main Code:
module johnson_ctr #(parameter WIDTH=4)
(
input clk,
input rstn,
output reg [WIDTH-1:0] out
);
integer i;
begin
if (!rstn)
out <= 1;
else
begin
out[WIDTH-1] <= ~out[0];
for (i = 0; i < WIDTH-1; i=i+1)
begin
out[i] <= out[i+1];
end
end
end
endmodule
Testbench:
module tb;
parameter WIDTH = 4;
reg clk;
reg rstn;
wire [WIDTH-1:0] out;
johnson_ctr uut (.clk (clk),.rstn (rstn),.out (out));
always #10 clk = ~clk;
initial begin
{clk, rstn} <= 0;
$monitor ("T=%0t out=%b", $time, out);
rstn <= 1;
$finish;
end
endmodule
Experiment 9
Verilog Code for design of 4-bit bidirectional shift register
Main Code:
module shift_reg #(parameter MSB=4) (
input d,clk,rstn,en,dir,
output reg [MSB-1:0] out);
begin
if (!rstn)
out <= 0;
else
begin
if (en)
case (dir)
0: out <= {out[MSB-2:0], d};
1: out <= {d, out[MSB-1:1]};
endcase
else
out <= out;
end
end
endmodule
module LCDmodule(clk, RxD, LCD_RS, LCD_RW, LCD_E, LCD_DataBus);

input clk, RxD;
output LCD_RS, LCD_RW, LCD_E;
output [7:0] LCD_DataBus;
wire RxD_data_ready;
wire [7:0] RxD_data;
async_receiver
deserialer(.clk(clk), .RxD(RxD), .RxD_data_ready(RxD_data_ready), .RxD_data(
RxD_data));
assign LCD_RW = 0;
assign LCD_DataBus = RxD_data;
wire Received_Escape = RxD_data_ready & (RxD_data==0);

wire Received_Data = RxD_data_ready & (RxD_data!=0);
reg [2:0] count;
always @(posedge clk) if(Received_Data | (count!=0)) count <= count + 1;
// activate LCD_E for 6 clocks, so at 25MHz, that's 6x40ns=240ns

reg LCD_E;
if(LCD_E==0)
LCD_E <= Received_Data;
else
LCD_E <= (count!=6);
reg LCD_instruction;
if(LCD_instruction==0)
LCD_instruction <= Received_Escape;
else
LCD_instruction <= (count!=7);
assign LCD_RS = ~LCD_instruction;
endmodule

Verilog HDL Lab Codes

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Verilog HDL Lab Codes

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H. K. E.

Digital Design Using Verilog HDL Laboratory (19ECL61)

1-bit Full Adder in Dataflow modeling:

1-bit Full Adder in Behavioral modeling:

1-bit Full Adder in Structural modeling:

1-bit Full Subtractor in Dataflow modeling:

1-bit Full Subtractor in Behavioral modeling:

1-bit Full Subtractor in Structural modeling:

Verilog Code for 4-bit Full Adder/Subtractor using 1-bit Full

// Instantiate the Unit Under Test (UUT)

always @(posedge clk, posedge rst)

always @(posedge clk,posedge rst)

always #10 clk=~clk;

// Instantiate the Unit Under Test (UUT)

Master Slave JK Flip Flop:

Binary to Gray code converter:

Gray to Binary code converter:

4-bit binary up/down counter:

always #10 clk=~clk;

4-bit BCD counter:

4-bit Ring counter:

4-bit Johnson counter:

module LCDmodule(clk, RxD, LCD_RS, LCD_RW, LCD_E, LCD_DataBus);

wire Received_Escape = RxD_data_ready & (RxD_data==0);

// activate LCD_E for 6 clocks, so at 25MHz, that's 6x40ns=240ns

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