EXP:2 Design of Binary Adders

2.1 Introduction
The purpose of this experiment is to introduce the design of simple combinational circuits, in
this case half adders, half subtractors, full adders and full subtractors. Software tools
Requirement Equipments:
Computer with Modelsim Software
Specifications:
HP Computer P4 Processor – 2.8 GHz, 2GB RAM, 160 GB Hard Disk
Softwares: Modelsim - 5.7c, Xilinx - 6.1i.
Algorithm
STEP 1: Open ModelSim XE II / Starter 5.7C
STEP 2: File -> Change directory -> D:\<register number>
STEP 3: File -> New Library -> ok
STEP 4: File -> New Source -> Verilog
STEP 5: Type the program
STEP 6: File -> Save -> <filename.v>
STEP 7: Compile the program
STEP 8: Simulate -> expand work -> select file -> ok
STEP 9: View -> Signals
STEP 10: Select values -> Edit -> Force -> input values
STEP 11: Add -> Wave -> Selected signals ->
Run STEP 12: Change input values and run
again
2.2 Logic Diagram
Figure 2.2.1Half adder

Figure 2.2.2 Full adder

Figure 2.2.3Halfsubtractor

Figure 2.2.4 Full subtractor 2.3 Pre lab Questions

1. What is meant by combinational circuits?
A combinational circuit is the digital logic circuit in which the output depends on the
combination of inputs at that point of time with total disregard to the past state of the inputs.
The digital logic gate is the building block of combinational circuits.
2. Write the sum and carry expression for half and full adder.
3. Write the difference and borrow expression for half and full subtractor.
4. What is signal? How it is declared?
A signal declaration contains one or more identifiers Each signal name is an identifier and
creates one separate signal. The (sub)type in the signal declaration can be of any scalar or
composite type.
VERILOG
Program
HALF ADDER:
Structural model Dataflow model Behaviouralmodel
modulehalfaddstr(sum,carry,a, modulehalfadddf(sum,carry,a, modulehalfaddbeh(sum,carry,a,b
b); b); );
outputsum,carry; outputsum,carry; outputsum,carry;
inputa,b; inputa,b; assign inputa,b;
xor(sum,a,b); sum = a ^ b; assign regsum,carry;
and(carry,a,b); carry=a&b; always @(a,b); sum
endmodule endmodule = a ^ b; carry=a&b;
endmodule

Truth table
Input Input
A B
0 0
0 1
1 0
1 1
Verilog Code
Output Output
S c
0 0
1 0
1 0
0 1
Structural Model
FULL ADDER:
Structural model Dataflow model Behaviouralmodel
module
fulladdstr(sum,carry,a,b,c)
; outputsum,carry;
inputa,b,c; xor
g1(sum,a,b,c); and
g2(x,a,b); and g3(y,b,c);
and g4(z,c,a); or
g5(carry,x,z,y);
endmodule
Truth Table
Input Input
A B
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
Verilog Code
modulefulladddf(sum,carry,a,b,c); modulefulladdbeh(sum,carry,a,b,c);
outputsum,carry; inputa,b,c; outputsum,carry; inputa,b,c;
assign sum = a ^ b^c; assign regsum,carry; always @ (a,b,c)
carry=(a&b) | (b&c) | sum = a ^ b^c;
(c&a); carry=(a&b) | (b&c) | (c&a);
endmodule endmodule
Input Output Output
C Sum carry
0 0 0
1 1 0
0 1 0
1 0 1
0 1 0
1 0 1
0 0 1
1 1 1
Structural model
HALF SUBTRACTOR:
Structural model Dataflow Model BehaviouralModel
modulehalfsubtstr(diff,borrow,a, modulehalfsubtdf(diff,borrow,a, modulehalfsubtbeh(diff,borrow,a,
b); b); b);
outputdiff,borrow; outputdiff,borrow; outputdiff,borrow;
inputa,b; inputa,b; inputa,b;
xor(diff,a,b); assign diff = a ^ b; assign regdiff,borrow;
and( borrow,~a,b); borrow=(~a&b); always @(a,b)
endmodule endmodule diff = a ^ b;
borrow=(~a&b);
endmodule

Truth Table
Input Input
A B
0 0
0 1
1 0
1 1
Output Output
D B
0 0
1 1
1 0
0 0

Verilog Code
Structural model
FULL SUBTRACTOR:
Structural model Dataflow Model BehaviouralModel
module modulefullsubtdf(diff,borrow,a,b,c) modulefullsubtbeh(diff,borrow,a,b,c)
fullsubtstr(diff,borrow,a,b,c) ; ;
; outputdiff,borrow; outputdiff,borrow; inputa,b,c;
outputdiff,borrow inputa,b,c; assign outputdiff,borrow;
; inputa,b,c; wire diff = a^b^c; always@(a,b,)
a0,q,r,s,t; assign borrow=(~a&b)|(~(a^b)&c); diff = a^b^c;
not(a0,a); endmodule borrow=(~a&b)|(~(a^b)&c);
xor(x,a,b); endmodule
xor(diff,x,c);
and(y,a0,b);
and(z,~x,c);
or(borrow,y,z);
endmodule

Truth Table
Input Input Input Output Output
A B C D B
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
Verilog Code
Structural Model
2.4 Post lab Questions
1. What are the signal assignment statements?
-A signal assignment statement modifies the target signal. It can appear inside a process
(sequential statement) or directly in an architecture (concurrent statement). The target signal
can be either a name (simple, selected, indexed, or slice) or an aggregate. A signal assignment
with no delay (or zero delays) will cause an event after delta delay, which means that the event
happens only when all of the currently active processes have finished executing (i.e. after one
simulation cycle).
2. What are the concurrent statements?
-Concurrent statements are used to define interconnected blocks and processes that
jointly describe the overall behavior or structure of a design. Concurrent statements execute
asynchronously with respect to each other.
3. Write short notes on: a) Process statement b) Block statement
Process statement
-Process Statements include a set of sequential statements that assign values to signals.
These statements allow you to perform step-by-step computations. Process Statements that
describe purely combinational behavior can also be used to create combinational logic. To
ensure that a process is combinational, its sensitivity list must contain all signals that are read
in the process. A sensitivity list contains the signals that cause the Process Statements to
execute if their values change.
Block statement
-The block statement is a way of grouping concurrent statements in an architecture. There
are two main purposes for using blocks: to improve the readability of the specification and to
disable some signals by using the guard expression (see guard for details).
4. Write about sequential statements.
 -The sequential domain is represented by a process or subprogram that contains
sequential statements. These statements are executed in the order in which they appear within
the process or subprogram, as in programming languages.
5. What is the difference b/w high impedance state of the signal(Z) and unknown state of the
signal(X).
-Z and X, are modeling abstractions: Z represents a high-impedance (an un-driven or tri-
stated signal) state, while X represents an unknown or indeterminate logic value. X’s can be
created intentionally or unintentionally. The most common occurrence of X is in uninitialized
registers or memories; X is used to represent the unknown value of these memory elements
prior to a reset.

2.5 Lab Report

Each individual will be required to submit a lab report. Use the format specified in the "Lab
Report Requirements” document available on the class web page. Be sure to include the
following items in your lab report:
Lab cover sheet with staff verification sign.
Answer the pre-lab questions
Complete VERILOG code design for all logic gates and output signal
waveforms Answer the post-lab questions

2.6 Grading
Pre-lab Work 20 points
Lab Performance 30 points
Post-lab Work 20 points
Lab report 30 points
For the lab performance - at a minimum, demonstrate the operation of all the logic gates to your
staff incharge
The lab report will be graded as follows (for the 30 points):
VERILOG code for each experiments 15
points
Output signal waveform for all experiments and its truth table 15
points