Paradiang, Ichinoshi B.

October 6, 2022
47325
CpE 121 – Intro to HDL

Lab Exercises

1. Write a Verilog code for the following truth table. Apply the gate-level and data
modeling.

a. Input Output b. Input Output

x y z F x y z F1 F2
0 0 0 0 0 0 0 0 1
0 0 1 1 0 0 1 1 0
0 1 0 1 0 1 0 1 1
0 1 1 0 0 1 1 0 0
1 0 0 1 1 0 0 1 1
1 0 1 1 1 0 1 1 1
1 1 0 0 1 1 0 0 0
1 1 1 1 1 1 1 1 0

Gate – Level Modeling (A):

module Act2_A(A,B,C,Q);
input A,B,C;
output Q;

//gate level modeling

wire w1,w2,w3,w4,w5,w6,w7;

not(w1, A);
not(w2, B);
not(w3, C);
and(w4, w1, B,w3);
and(w5, w2, C);
and(w6, A, w2);
and(w7, A, C);
or(Q, w4, w5, w6, w7);

endmodule

module act_tb;
reg a,b,c;
wire q;
Act2_A test(a,b,c,q);

initial begin
#10 $display("ABC | Q |");
a=0;b=0;c=0;
#10 $display("%b%b%b | %b |",a,b,c,q);
a=0;b=0;c=1;
#10 $display("%b%b%b | %b |",a,b,c,q);
a=0;b=1;c=0;
#10 $display("%b%b%b | %b |",a,b,c,q);
a=0;b=1;c=1;
#10 $display("%b%b%b | %b |",a,b,c,q);
a=1;b=0;c=0;
#10 $display("%b%b%b | %b |",a,b,c,q);
a=1;b=0;c=1;
#10 $display("%b%b%b | %b |",a,b,c,q);
a=1;b=1;c=0;
#10 $display("%b%b%b | %b |",a,b,c,q);
a=1;b=1;c=1;
#10 $display("%b%b%b | %b |",a,b,c,q);

end

endmodule

Data Flow Modeling( A):

module Act2_A(x,y,z,Q);
input x,y,z;
output Q;

//data flow modeling

assign Q = ~x&y&~z|~y&z|x&~y|x&z;

endmodule

module act_tb;
reg a,b,c;
wire q;

Act2_A test(a,b,c,q);

initial begin

#10 $display("ABC | Q |");

a=0;b=0;c=0;
#10 $display("%b%b%b | %b |",a,b,c,q);
a=0;b=0;c=1;
#10 $display("%b%b%b | %b |",a,b,c,q);
a=0;b=1;c=0;
#10 $display("%b%b%b | %b |",a,b,c,q);
a=0;b=1;c=1;
#10 $display("%b%b%b | %b |",a,b,c,q);
a=1;b=0;c=0;
#10 $display("%b%b%b | %b |",a,b,c,q);
a=1;b=0;c=1;
#10 $display("%b%b%b | %b |",a,b,c,q);
a=1;b=1;c=0;
#10 $display("%b%b%b | %b |",a,b,c,q);
a=1;b=1;c=1;
#10 $display("%b%b%b | %b |",a,b,c,q);

end

endmodule

Gate – Level Modeling (B):

module Act2_B(A,B,C,Q,Q2);
input A,B,C;
output Q, Q2;

//gate level modeling

wire w1,w2,w3,w4,w5,w6,w7,w8,w9;

not(w1, A);
not(w2, B);
not(w3, C);
and(w4, w1, B,w3);
and(w5, w2, C);
and(w6, A, w2);
and(w7, A, C);
or(Q, w4, w5, w6, w7);
and(w8, A, w2);
and(w9, w1, w3);
or(Q2, w8, w9);

endmodule

module act_tb;
reg a,b,c;
wire q,q2;

Act2_B test(a,b,c,q,q2);
initial begin
#10 $display("ABC | Q | Q2 |");
a=0;b=0;c=0;
#10 $display("%b%b%b | %b | %b |",a,b,c,q,q2);
a=0;b=0;c=1;
#10 $display("%b%b%b | %b | %b |",a,b,c,q,q2);
a=0;b=1;c=0;
#10 $display("%b%b%b | %b | %b |",a,b,c,q,q2);
a=0;b=1;c=1;
#10 $display("%b%b%b | %b | %b |",a,b,c,q,q2);
a=1;b=0;c=0;
#10 $display("%b%b%b | %b | %b |",a,b,c,q,q2);
a=1;b=0;c=1;
#10 $display("%b%b%b | %b | %b |",a,b,c,q,q2);
a=1;b=1;c=0;
#10 $display("%b%b%b | %b | %b |",a,b,c,q,q2);
a=1;b=1;c=1;
#10 $display("%b%b%b | %b | %b |",a,b,c,q,q2);

end

endmodule

Data Flow Modeling (B);

module Act2_B(x,y,z,Q,Q2);
input x,y,z;
output Q, Q2;

//data flow modeling

assign Q = ~x&y&~z|~y&z|x&~y|x&z;
assign Q2 = x&~y|~x&~z;

endmodule

module act_tb;
reg a,b,c;
wire q, q2;

Act2_B test(a,b,c,q,q2);

initial begin

#10 $display("ABC | Q | Q2 |");

a=0;b=0;c=0;
#10 $display("%b%b%b | %b | %b |",a,b,c,q,q2);
a=0;b=0;c=1;
#10 $display("%b%b%b | %b | %b |",a,b,c,q,q2);
a=0;b=1;c=0;
#10 $display("%b%b%b | %b | %b |",a,b,c,q,q2);
a=0;b=1;c=1;
#10 $display("%b%b%b | %b | %b |",a,b,c,q,q2);
a=1;b=0;c=0;
#10 $display("%b%b%b | %b | %b |",a,b,c,q,q2);
a=1;b=0;c=1;
#10 $display("%b%b%b | %b | %b |",a,b,c,q,q2);
a=1;b=1;c=0;
#10 $display("%b%b%b | %b | %b |",a,b,c,q,q2);
a=1;b=1;c=1;
#10 $display("%b%b%b | %b | %b |",a,b,c,q,q2);

end

endmodule

2. Write a Verilog code for the following description. Apply the gate-level and
data modeling. A combinational circuit have inputs, x , y , and z , and three
outputs, A, B , and C . When the binary input is 0, 1, 2, or 3, the binary output
is one greater than the input. When the binary input is 4, 5, 6, or 7, the binary
output is two less than the input.

Gate - Level Modeling:

module Act2_NO2(x,y,z,A,B,C);
input x,y,z;
output A, B, C;

//gate level modeling

wire w1,w2,w3,w4,w5,w6,w7,w8,w9,w10;

not(w1, x);
not(w2, y);
not(w3, z);
and(w4, y, z);
and(w5, x, y);
or(A, w4, w5);
and(w6, y, w3);
and(w7, w2, z);
and(w8, w2, x);
or(B, w6, w7, w8);
and(w9, w1, w3);
and(w10, x, w2);
or(C, w9, w10);

endmodule

module act_tb;
reg x,y,z;
wire A,B,C;

Act2_NO2 test(x,y,z,A,B,C);

initial begin
#10 $display("XYZ | A | B | C |");
x=0;y=0;z=0;
#10 $display("%b%b%b | %b | %b | %b |",x,y,z,A,B,C);
x=0;y=0;z=1;
#10 $display("%b%b%b | %b | %b | %b |",x,y,z,A,B,C);
x=0;y=1;z=0;
#10 $display("%b%b%b | %b | %b | %b |",x,y,z,A,B,C);
x=0;y=1;z=1;
#10 $display("%b%b%b | %b | %b | %b |",x,y,z,A,B,C);
x=1;y=0;z=0;
#10 $display("%b%b%b | %b | %b | %b |",x,y,z,A,B,C);
x=1;y=0;z=1;
#10 $display("%b%b%b | %b | %b | %b |",x,y,z,A,B,C);
x=1;y=1;z=0;
#10 $display("%b%b%b | %b | %b | %b |",x,y,z,A,B,C);
x=1;y=1;z=1;
#10 $display("%b%b%b | %b | %b | %b |",x,y,z,A,B,C);

end

endmodule

Data Flow Modeling:

module Act2_NO2(x,y,z,A,B,C);
input x,y,z;
output A, B, C;

//data flow modeling

assign A = y&z|x&y;
assign B = ~x&y&~z|~y&z|x&~y;
assign C = ~x&~z|x&z;

endmodule

module act_tb;
reg x,y,z;
wire A,B,C;

Act2_NO2 test(x,y,z,A,B,C);

initial begin
#10 $display("XYZ | A | B | C |");
x=0;y=0;z=0;
#10 $display("%b%b%b | %b | %b | %b |",x,y,z,A,B,C);
x=0;y=0;z=1;
#10 $display("%b%b%b | %b | %b | %b |",x,y,z,A,B,C);
x=0;y=1;z=0;
#10 $display("%b%b%b | %b | %b | %b |",x,y,z,A,B,C);
x=0;y=1;z=1;
#10 $display("%b%b%b | %b | %b | %b |",x,y,z,A,B,C);
x=1;y=0;z=0;
#10 $display("%b%b%b | %b | %b | %b |",x,y,z,A,B,C);
x=1;y=0;z=1;
#10 $display("%b%b%b | %b | %b | %b |",x,y,z,A,B,C);
x=1;y=1;z=0;
#10 $display("%b%b%b | %b | %b | %b |",x,y,z,A,B,C);
x=1;y=1;z=1;
#10 $display("%b%b%b | %b | %b | %b |",x,y,z,A,B,C);

end

endmodule