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Create a VHDL design program of a seven segment decoder with 4 std inputs (a,b,c,d)
0000-1001 and 7 std outputs (q1,q2,q3,q4,q5,q6,q7) equivalent seven segment display
of the input. Attached below is the truth table and the testbench.vhd of your design.

 Due date:  October 29, 2022

a b c d q1 q2 q3 q4 q5 q6 q7
0 0 0 0 1 1 1 1 1 1 0
0 0 0 1 0 1 1 0 0 0 0
0 0 1 0 1 1 0 1 1 0 1
0 0 1 1 1 1 1 1 0 0 1
0 1 0 0 0 1 1 0 0 1 1
0 1 0 1 1 0 1 1 0 1 1
0 1 1 0 1 0 1 1 1 1 1
0 1 1 1 1 1 1 0 0 0 0
1 0 0 0 1 1 1 1 1 1 1
1 0 0 1 1 1 1 1 0 1 1
--Testbench.vhd
-- Testbench for baseic decoder operation
library IEEE;
use IEEE.std_logic_1164.all;
 
entity testbench is
-- empty
end testbench; 
architecture tb of testbench is
-- DUT component
component decoder_operation is
port(
  a: in std_logic;
  b: in std_logic;
  c: in std_logic;
  d: in std_logic;
  q1: out std_logic;
  q2: out std_logic;
  q3: out std_logic;
  q4: out std_logic;
  q5: out std_logic;
  q6: out std_logic;
  q7: out std_logic);
end component;
signal a_in, b_in, c_in, d_in, q1_out, q2_out, q3_out, q4_out, q5_out, q6_out, q7_out:
std_logic;
begin
  -- Connect DUT
  DUT: decoder_operation port map(a_in, b_in, c_in, d_in, q1_out, q2_out, q3_out,
q4_out, q5_out, q6_out, q7_out);
  process
  begin
    a_in <= '0';
    b_in <= '0';
    c_in <= '0';
    d_in <= '0';
    wait for 1 ns;
    assert(q1_out='1' and q2_out='1' and q3_out='1' and q4_out='1' and q5_out='1' and
q6_out='1' and q7_out='0') report "Fail 0" severity error;
    a_in <= '0';
    b_in <= '0';
    c_in <= '0';
    d_in <= '1';
    wait for 1 ns;
    assert(q1_out='0' and q2_out='1' and q3_out='1' and q4_out='0' and q5_out='0' and
q6_out='0' and q7_out='0') report "Fail 1" severity error;
    a_in <= '0';
    b_in <= '0';
    c_in <= '1';
    d_in <= '0';
    wait for 1 ns;
    assert(q1_out='1' and q2_out='1' and q3_out='0' and q4_out='1' and q5_out='1' and
q6_out='0' and q7_out='1') report "Fail 2" severity error;
    a_in <= '0';
    b_in <= '0';
    c_in <= '1';
    d_in <= '1';
    wait for 1 ns;
    assert(q1_out='1' and q2_out='1' and q3_out='1' and q4_out='1' and q5_out='0' and
q6_out='0' and q7_out='1') report "Fail 3" severity error;
    a_in <= '0';
    b_in <= '1';
    c_in <= '0';
    d_in <= '0';
    wait for 1 ns;
    assert(q1_out='0' and q2_out='1' and q3_out='1' and q4_out='0' and q5_out='0' and
q6_out='1' and q7_out='1') report "Fail 4" severity error;
    a_in <= '0';
    b_in <= '1';
    c_in <= '0';
    d_in <= '1';
    wait for 1 ns;
    assert(q1_out='1' and q2_out='0' and q3_out='1' and q4_out='1' and q5_out='0' and
q6_out='1' and q7_out='1') report "Fail 5" severity error;
    a_in <= '0';
    b_in <= '1';
    c_in <= '1';
    d_in <= '0';
    wait for 1 ns;
    assert(q1_out='1' and q2_out='0' and q3_out='1' and q4_out='1' and q5_out='1' and
q6_out='1' and q7_out='1') report "Fail 6" severity error;
    a_in <= '0';
    b_in <= '1';
    c_in <= '1';
    d_in <= '1';
    wait for 1 ns;
    assert(q1_out='1' and q2_out='1' and q3_out='1' and q4_out='0' and q5_out='0' and
q6_out='0' and q7_out='0') report "Fail 7" severity error;
    a_in <= '1';
    b_in <= '0';
    c_in <= '0';
    d_in <= '0';
    wait for 1 ns;
    assert(q1_out='1' and q2_out='1' and q3_out='1' and q4_out='1' and q5_out='1' and
q6_out='1' and q7_out='1') report "Fail 8" severity error;
    a_in <= '1';
    b_in <= '0';
    c_in <= '0';
    d_in <= '1';
    wait for 1 ns;
    assert(q1_out='1' and q2_out='1' and q3_out='1' and q4_out='1' and q5_out='0' and
q6_out='1' and q7_out='1') report "Fail 9" severity error;
  
    -- Clear inputs
    a_in <= '0';
    b_in <= '0';
    c_in <= '0';
    d_in <= '0';
    assert false report "Test done." severity note;
    wait;
  end process;
end tb;

-- Code your design here

library IEEE;

use IEEE.std_logic_1164.all;

entity decoder_operation is

port(

a: in std_logic;

b: in std_logic;

c: in std_logic;

d: in std_logic;

q1: out std_logic;

 q2: out std_logic;

q3: out std_logic;

q4: out std_logic;

q5: out std_logic;

q6: out std_logic;

q7: out std_logic);

end decoder_operation;

architecture Behavioral of decoder_operation is

begin

process(a, b, c, d) is

begin

q1 <= a OR c OR (b AND d) OR (NOT b AND NOT d);

q2 <= (NOT b) OR (NOT c AND NOT d) OR (c AND d);

q3 <= b OR NOT c OR d;

q4 <= (NOT b AND NOT d) OR (c AND NOT d) OR (b AND NOT c AND d) OR (NOT b AND c) OR a;

q5 <= (NOT b AND NOT d) OR (c AND NOT d);

q6 <= a OR (NOT c AND NOT d) OR (b AND NOT c) OR (b AND NOT d);

q7 <= a OR (b AND NOT c) OR ( NOT b AND c) OR (c AND NOT d);

end process;

end Behavioral;