Kharkov National University of Radioelectronics

Centre for Education in English

Course: “System-on-chip”

Laboratory Work
Report #1

Student: Teacher:
Gr. КІУКІі-16-3 Prof. Eugenia Litvinova
Name

Kharkov 2020
Task of the Lab#1:
Using cloud service http://www.edaplayground.com create the following
projects.
You can login this service using Facebook or Google account.

Example 1. Gate Or

-- Testbench for OR gate -- Simple OR gate design

library IEEE; library IEEE;
use IEEE.std_logic_1164.all; use IEEE.std_logic_1164.all;

-- description of testbench entity -- description of entity

entity testbench is entity or_gate is
-- empty port( -- description of ports
end testbench; a: in std_logic;
b: in std_logic;
-- description of testbench architecture q: out std_logic);
architecture tb of testbench is end or_gate;
-- DUT component declaration
component or_gate is -- description of architecture
port( architecture rtl of or_gate is
a: in std_logic; begin
b: in std_logic; process(a, b) is
q: out std_logic); begin
end component; q <= a or b;
--Internal signals definition end process;
signal a_in, b_in, q_out: std_logic; end rtl;

begin
-- component instantiation of the DUT
-- Connect DUT (DUT: <entity name> PORT MAP ())

DUT: or_gate port map(a_in, b_in, q_out);

-- stimuli generation
process
begin
a_in <= '0';
b_in <= '0';
wait for 1 ns;
assert(q_out='0') report "Fail 0/0" severity error;

a_in <= '0';

b_in <= '1';
wait for 1 ns;
assert(q_out='1') report "Fail 0/1" severity error;
 a_in <= '1';
b_in <= 'X';
wait for 1 ns;
assert(q_out='1') report "Fail 1/X" severity error;

a_in <= '1';

b_in <= '1';
wait for 1 ns;
assert(q_out='1') report "Fail 1/1" severity error;

-- Clear inputs
a_in <= '0';
b_in <= '0';

assert false report "Test done." severity note;

wait;
end process;
end tb;

Add Results and waveform.

Example 2. Create projects for the following logic gates

1 2 3 1 2 3 1 2 3 1 2 3 1 2 3
0 0 0 0 0 0 0 0 0 0 0 1 0 0 1
0 1 0 0 1 1 0 1 1 0 1 1 0 1 0
1 0 0 1 0 1 1 0 1 1 0 1 1 0 0
1 1 1 1 1 1 1 1 0 1 1 0 1 1 0