Laboratorio 1.

-- Code your testbench here

-- or browse Examples

library IEEE;

use IEEE.std_logic_1164.all;

entity testbench is

end testbench;

architecture tb of testbench is

component pepito is

port(

A: in std_logic;

B: in std_logic;

S: out std_logic);

end component;

signal sa, sb, ss: std_logic;

begin

UUT: pepito

port map (A => sa, B => sb, S => ss);

process

begin

sa <= '0';

sb <= '0';
 wait for 1 ns;

sa <= '0';

sb <= '1';

wait for 1 ns;

sa <= '1';

sb <= '0';

wait for 1 ns;

sa <= '1';

sb <= '1';

wait for 1 ns;

wait;

end process;

end tb;
-- Code your design here

library IEEE;

use IEEE.std_logic_1164.all;

-- caja negra entradas y salidas o diseño

entity pepito is

port(

A: in std_logic;

B: in std_logic;

S: out std_logic);

end pepito;

architecture arq_pepito of pepito is

begin

-- Minterminos

--S <= ((not(A) and not(B)) or (A and B));

-- Maxterminos

S <= ((A or not(B)) and (not(A) or B));

end arq_pepito;
Laboratorio 2

-- Code your testbench here

-- or browse Examples

library IEEE;

use IEEE.std_logic_1164.all;

entity testbench is

end testbench;

architecture tb of testbench is

component pepito is

port(

A: in std_logic;

B: in std_logic;

C: in std_logic;

S: out std_logic;

COUT: out std_logic);

end component;

signal sa, sb, sc, ss, cout: std_logic;

begin

UUT: pepito

port map (A => sa, B => sb, C => sc, S => ss, COUT => cout);

process
begin

sa <= '0';

sb <= '0';

sc <= '0';

wait for 1 ns;

sa <= '0';

sb <= '0';

sc <= '1';

wait for 1 ns;

sa <= '0';

sb <= '1';

sc <= '0';

wait for 1 ns;

sa <= '0';

sb <= '1';

sc <= '1';

wait for 1 ns;

sa <= '1';

sb <= '0';

sc <= '0';

wait for 1 ns;

sa <= '1';

sb <= '0';
 sc <= '1';

wait for 1 ns;

sa <= '1';

sb <= '1';

sc <= '0';

wait for 1 ns;

sa <= '1';

sb <= '1';

sc <= '1';

wait for 1 ns;

wait;

end process;

end tb;
-- Code your design here

library IEEE;

use IEEE.std_logic_1164.all;

-- caja negra entradas y salidas o diseño

entity pepito is

port(

A: in std_logic;

B: in std_logic;

C: in std_logic;

S: out std_logic;

COUT: out std_logic);

end pepito;

architecture arq_pepito of pepito is

begin

-- Minterminos

COUT <= ((not(A) and B and C) or (A and not(B) and C) or (A and B and not(C)) or (A and B and C));

-- Minterminos

S <= ((not(A) and not(B) and C) or (not(A) and B and not(C)) or (A and not(B) and not(C)) or (A and
B and C));

end arq_pepito;
Laboratorio 3

-- or browse Examples

-- Code your testbench here

library IEEE;

use IEEE.std_logic_1164.all;

entity testbench is

end testbench;

architecture tb of testbench is

component pepito is

port(

A: in std_logic;

B: in std_logic;

C: in std_logic;

D: in std_logic;

S: out std_logic);

end component;

signal sa, sb, sc, sd, ss: std_logic;

begin

UUT: pepito

port map (A => sa, B => sb, C => sc, D => sd, S => ss);

process
begin

sa <= '0';

sb <= '0';

sc <= '0';

sd <= '0';

wait for 1 ns;

sa <= '0';

sb <= '0';

sc <= '0';

sd <= '1';

wait for 1 ns;

sa <= '0';

sb <= '0';

sc <= '1';

sd <= '0';

wait for 1 ns;

sa <= '0';

sb <= '0';

sc <= '1';

sd <= '1';

wait for 1 ns;

sa <= '0';

sb <= '1';

sc <= '0';

sd <= '0';
wait for 1 ns;

sa <= '0';

sb <= '1';

sc <= '0';

sd <= '1';

wait for 1 ns;

sa <= '0';

sb <= '1';

sc <= '1';

sd <= '0';

wait for 1 ns;

sa <= '0';

sb <= '1';

sc <= '1';

sd <= '1';

wait for 1 ns;

sa <= '1';

sb <= '0';

sc <= '0';

sd <= '0';

wait for 1 ns;

sa <= '1';

sb <= '0';

sc <= '0';
sd <= '1';

wait for 1 ns;

sa <= '1';

sb <= '0';

sc <= '1';

sd <= '0';

wait for 1 ns;

sa <= '1';

sb <= '0';

sc <= '1';

sd <= '1';

wait for 1 ns;

sa <= '1';

sb <= '1';

sc <= '0';

sd <= '0';

wait for 1 ns;

sa <= '1';

sb <= '1';

sc <= '0';

sd <= '1';

wait for 1 ns;

sa <= '1';

sb <= '1';
 sc <= '1';

sd <= '0';

wait for 1 ns;

sa <= '1';

sb <= '1';

sc <= '1';

sd <= '1';

wait for 1 ns;

wait;

end process;

end tb;
-- Code your design here

library IEEE;

use IEEE.std_logic_1164.all;

-- caja negra entradas y salidas o diseño

entity pepito is

port(

A: in std_logic;

B: in std_logic;

C: in std_logic;

D: in std_logic;

S: out std_logic);

end pepito;

architecture arq_pepito of pepito is

begin

-- Minterminos

S <= ((not(A) and B and C and D) or (A and not(B) and not(C) and D) or (A and not(B) and C and
not(D)) or (A and not(B) and C and D) or (A and B and not(C) and not(D)) or (A and B and not(C)
and D) or (A and B and C and not(D)) or (A and B and C and D));

end arq_pepito;
Laboratorio 4

-- or browse Examples

-- Code your testbench here

library IEEE;

use IEEE.std_logic_1164.all;

entity testbench is

end testbench;

architecture tb of testbench is

component Laboratorio4 is

port(

A: in std_logic;

B: in std_logic;

C: in std_logic;

D: in std_logic;

X: out std_logic;

Y: out std_logic;

Z: out std_logic);

end component;

signal sa, sb, sc, sd, sx, sy, sz: std_logic;

begin

UUT: Laboratorio4

port map (A => sa, B => sb, C => sc, D => sd, X=> sx, Y => sy,
Z => sz);

process

begin

sa <= '0';

sb <= '0';

sc <= '0';

sd <= '0';

wait for 1 ns;

sa <= '0';

sb <= '0';

sc <= '0';

sd <= '1';

wait for 1 ns;

sa <= '0';

sb <= '0';

sc <= '1';

sd <= '0';

wait for 1 ns;

sa <= '0';

sb <= '0';

sc <= '1';

sd <= '1';

wait for 1 ns;

sa <= '0';

sb <= '1';

sc <= '0';

sd <= '0';

wait for 1 ns;

sa <= '0';

sb <= '1';

sc <= '0';

sd <= '1';

wait for 1 ns;

sa <= '0';

sb <= '1';

sc <= '1';

sd <= '0';

wait for 1 ns;

sa <= '0';

sb <= '1';

sc <= '1';

sd <= '1';

wait for 1 ns;

sa <= '1';

sb <= '0';

sc <= '0';

sd <= '0';

wait for 1 ns;

sa <= '1';

sb <= '0';

sc <= '0';

sd <= '1';

wait for 1 ns;

sa <= '1';

sb <= '0';

sc <= '1';

sd <= '0';

wait for 1 ns;

sa <= '1';

sb <= '0';

sc <= '1';

sd <= '1';

wait for 1 ns;

sa <= '1';

sb <= '1';

sc <= '0';

sd <= '0';

wait for 1 ns;

sa <= '1';

sb <= '1';

sc <= '0';

sd <= '1';
 wait for 1 ns;

sa <= '1';

sb <= '1';

sc <= '1';

sd <= '0';

wait for 1 ns;

sa <= '1';

sb <= '1';

sc <= '1';

sd <= '1';

wait for 1 ns;

wait;

end process;

end tb;
-- Code your design here

library IEEE;

use IEEE.std_logic_1164.all;

-- caja negra entradas y salidas o diseño

entity Laboratorio4 is

port(

A: in std_logic;

B: in std_logic;

C: in std_logic;

D: in std_logic;

X: out std_logic;

Y: out std_logic;

Z: out std_logic);

end Laboratorio4;

architecture arq_Laboratorio4 of Laboratorio4 is

begin

-- Minterminos

X <= (not(A) and not(B) and not(C) and not(D)) or (A and not(B) and not(C) and not(D));

Y <= (not(A) and not(B) and C and not(D)) or (not(A) and B and not(C) and not(D)) or (not(A)
and B and (C) and not(D)) or (A and not(B) and C and not(D)) or (A and B and not(C) and
not(D)) or(A and B and C and not(D));
 Z <= (not(A) and not(B) and not (C) and not(D)) or (not(A) and not(B) and not(C) and D) or
(not(A) and B and not(C) and not(D)) or (not(A) and B and not(C) and D) or (not(A) and B
and C and D) or (A and not(B) and not(C) and D) or (A and not(B) and C and D) or (A and B
and not(C) and not(D)) or

(A and B and not(C) and D) or (A and B and C and D);

end arq_Laboratorio4;