Behavioral Code for Half Adder: Testbench for Behavioral Code:

library ieee; library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all; use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all; use ieee.std_logic_unsigned.all;

entity half_adder_behav is entity tb_half_adder_behav is

port (a, b: in std_logic; s, c: out std_logic); end tb_half_adder_behav;
end half_adder_behav;
architecture testbench of tb_half_adder_behav is
architecture behavioural of half_adder_behav is signal a, b: std_logic;
begin signal s, c: std_logic;
process (a, b) begin
if a = '1' then component half_adder_behav
s<= not b; port (a, b: in std_logic; s, c: out std_logic);
c<= b; end component;
else
s<= b; begin
c<= '0'; H1: half_adder_behav port map(a, b, s, c);
end if;
end process; process begin

end behavioural; a<='0'; b<='0';

wait for 10 ps;

a<='0'; b<='1';
wait for 10 ps;

a<='1'; b<='0';
wait for 10 ps;

a<='1'; b<='1';
wait for 10 ps;

end process;

end testbench;

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Structural Code for Half Adder: Testbench for Structural Code:

library ieee; library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
entity half_adder_str is use ieee.std_logic_arith.all;
port(a, b: in std_logic; s, c: out std_logic); use ieee.std_logic_unsigned.all;
end entity half_adder_str;
entity tb_half_adder_str is
library ieee; end entity tb_half_adder_str;
use ieee.std_logic_1164.all;
entity xor_gate is architecture testbench of tb_half_adder_str is
port(x, y: in std_logic; z: out std_logic);
end xor_gate; component half_adder_str is
port(a, b: in std_logic; s, c: out std_logic);
library ieee; end component;
use ieee.std_logic_1164.all;
entity and_gate is signal a, b, s, c: std_logic := '0';
port(m, n: in std_logic; o: out std_logic); begin
end and_gate;
H1: half_adder_str port map(a, b, s, c);
architecture behavioural1 of xor_gate is begin
z <= x xor y; stimulus_proc: process
end behavioural1; begin

architecture behavioural2 of and_gate is begin a <= '0'; b <= '0';

o <= m and n; wait for 10 ns;
end behavioural2;
a <= '0'; b <= '1';
architecture structure of half_adder_str is wait for 10 ns;
component xor_gate is
port (x, y: in std_logic; z: out std_logic); a <= '1'; b <= '0';
end component; wait for 10 ns;

component and_gate is a <= '1'; b <= '1';

port (m, n: in std_logic; o: out std_logic); wait for 10 ns;
end component;
begin end process;
I1: xor_gate port map(a, b, s);
I2: and_gate port map(a, b, c); end architecture testbench;
end architecture structure;

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Dataflow Code for Half Adder: Testbench for Dataflow Code:

library ieee; library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all; use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all; use ieee.std_logic_unsigned.all;

entity half_adder_dataf is entity tb_half_adder_dataf is

port (a, b: in bit; s, c: out bit); end entity tb_half_adder_dataf;
end half_adder_dataf;
architecture testbench of tb_half_adder_dataf is
architecture dataflow of half_adder_dataf is
begin component half_adder_dataf is
s<=a xor b; port(a, b: in bit; s, c: out bit);
c<=a and b; end component;

end dataflow; signal a, b, s, c: bit;

begin

H1: half_adder_dataf port map(a => a, b => b,

s => s, c => c);
process begin
a <= '0'; b <= '0';
wait for 10 ns;

a <= '0'; b <= '1';

wait for 10 ns;

a <= '1'; b <= '0';

wait for 10 ns;

a <= '1'; b <= '1';

wait for 10 ns;
end process;

end testbench;

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