A combinational circuit consists of logic gates whose outputs at any time are

determined from only the present combination of inputs and they have no
memory.

These circuits developed using AND, OR, NOT, NAND and NOR logic gates.
These logic gates are building blocks of combinational circuits. A
combinational circuit consists of input variables and output variables. Since
these circuits are not dependent upon previous input to generate any output,
so are combinational logic circuits. A combinational circuit can have an n
number of inputs and m number of outputs. In combinational circuits, the
output at any time is a direct function of the applied external inputs.

Q. Write VHDL code & design Circuit for the given equation “ (A or B) and (B or C) ”

-- Module Name: comb_entitty - Behavioral

-- Project Name:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity comb_entitty is

Port ( A : in STD_LOGIC;

B : in STD_LOGIC;

C : in STD_LOGIC;

out1 : inout STD_LOGIC;

out2 : inout STD_LOGIC;

Res : out STD_LOGIC);

end comb_entitty;
architecture Behavioral of comb_entitty is

begin

-- (A or B) and (B or C)

out1 <= A or B;

out2 <= B or C;

Res <= out1 and out2;

end Behavioral;
--------------------------------------------------------------------------------

-- Create Date: 06:42:53 02/14/2022

-- Design Name:

-- Module Name: /home/ise/comb1/comb_tb.vhd

-- Project Name: comb1

--------------------------------------------------------------------------------

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY comb_tb IS

END comb_tb;

ARCHITECTURE behavior OF comb_tb IS

 COMPONENT comb_entitty

PORT(

A : IN std_logic;

B : IN std_logic;

C : IN std_logic;

out1 : INOUT std_logic;

out2 : INOUT std_logic;

Res : OUT std_logic

);

END COMPONENT;

--Inputs

signal A : std_logic := '0';

signal B : std_logic := '0';

signal C : std_logic := '0';

signal out1 : std_logic;

signal out2 : std_logic;

--Outputs

signal Res : std_logic;

--constant <clock>_period : time := 10 ns;

BEGIN

uut: comb_entitty PORT MAP (

A => A,

B => B,

C => C,

out1 => out1,

out2 => out2,

 Res => Res

);

-- Stimulus process

stim_proc: process

begin

wait for 1 ps;

A <= '0';

B <= '0';

C <= '0';

wait for 1 ps;

A <= '0';

B <= '0';

C <= '1';

wait for 1 ps;

A <= '0';

B <= '1';

C <= '0';

wait for 1 ps;

A <= '0';

B <= '1';

C <= '1';

wait for 1 ps;

A <= '1';

B <= '0';

C <= '0';

wait for 1 ps;

A <= '1';

B <= '0';

C <= '1';

wait for 1 ps;

A <= '1';

B <= '1';

C <= '0';
 wait for 1 ps;

A <= '1';

B <= '1';

C <= '1';

end process;

END;