Relatório Exercício Computacional 01 - ES571/ES572 Circuitos Lógicos

Nome: Bruno Cardoso Holanda RA: 167542

Nome: Gabriel Vieira Caldana RA: 243612

2.1) Porta AND

Gráfico:

Gráfico 2 :
3) Multiplexador 2-para-1 de 1 bit
Gráfico:

Código:

“ library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity Multiplexador is
end Multiplexador ;
architecture behaviour of Multiplexador is
component Porta_not
port (S : in std_logic;
S2 : out std_logic);
end component;

component Porta_and_X
port (X : in std_logic;
S2 : in std_logic;
X2 : out std_logic);
end component;

component Porta_and_Y
port (Y : in std_logic;
S : in std_logic;
Y2 : out std_logic);
end component;
component Porta_or
port (X2 : in std_logic;
Y2 : in std_logic;
M : out std_logic);
end component;

signal X_in : std_logic;

signal Y_in : std_logic;
signal S_in : std_logic;
signal X2_out : std_logic;
signal Y2_out : std_logic;
signal S2_out : std_logic;
signal M_out : std_logic;

begin
dut1 : Porta_not port map (S => S_in , S2 => S2_out);
dut2 : Porta_and_X port map (X => X_in , S2 => S2_out , X2 => X2_out );
dut3 : Porta_and_Y port map (Y => Y_in , S => S_in , Y2 => Y2_out);
dut4 : Porta_or port map (X2 => X2_out , Y2 => Y2_out , M => M_out);

process
begin
X_in <= '0';
Y_in <= '0';
S_in <= '0';
wait for 1 ns;
assert(M_out='0') report "Erro na entrada 0/0/0" severity error;

X_in <= '0';

Y_in <= '0';
S_in <= '1';
wait for 1 ns;
assert(M_out='0') report "Erro na entrada 0/0/1" severity error;

X_in <= '0';

Y_in <= '1';
S_in <= '0';
wait for 1 ns;
assert(M_out='0') report "Erro na entrada 0/1/0" severity error;

X_in <= '0';

Y_in <= '1';
S_in <= '1';
wait for 1 ns;
assert(M_out='1') report "Erro na entrada 0/1/1" severity error;

X_in <= '1';

Y_in <= '0';
S_in <= '0';
wait for 1 ns;
assert(M_out='1') report "Erro na entrada 1/0/0" severity error;

X_in <= '1';

Y_in <= '0';
S_in <= '1';
wait for 1 ns;
assert(M_out='0') report "Erro na entrada 1/0/1" severity error;

X_in <= '1';

Y_in <= '1';
S_in <= '0';
wait for 1 ns;
assert(M_out='1') report "Erro na entrada 1/1/0" severity error;

X_in <= '1';

Y_in <= '1';
S_in <= '1';
wait for 1 ns;
assert(M_out='1') report "Erro na entrada 1/1/1" severity error;

X_in <= '0';

Y_in <= '0';
S_in <= '0';

end process;
end Behaviour; ”

Tabela Verdade :
4) Somador de 1 bit
Gráfico:

Código:

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity Somador is
end Somador ;
architecture behaviour of Somador is

component Porta_XOR_A_B
port ( A, B : in STD_LOGIC;
A1 : out STD_LOGIC);
end component;

component Porta_XOR_AB_C
port ( A1, Cin : in STD_LOGIC;
S : out STD_LOGIC);
end component;

component Porta_AND_AB_C
port (Cin: in std_logic;
A1 : in std_logic;
X0 : out std_logic);
end component;

component Porta_AND_A_B
port (B: in std_logic;
A : in std_logic;
X1 : out std_logic);
end component;

component Porta_OR
port (X0 : in std_logic;
X1 : in std_logic;
Cout : out std_logic);
end component;

signal A_in : std_logic;

signal B_in : std_logic;
signal Cin_in : std_logic;
signal A1_out : std_logic;
signal S_out : std_logic;
signal X0_out : std_logic;
signal X1_out : std_logic;
signal Cout_out : std_logic;

begin
dut1 : Porta_XOR_A_B port map (A => A_in , B => B_in , A1 => A1_out);
dut2 : Porta_XOR_AB_C port map (A1 => A1_out , Cin => Cin_in , S => S_out);
dut3 : Porta_AND_AB_C port map (A1 => A1_out , Cin => Cin_in , X0 => X0_out);
dut4 : Porta_AND_A_B port map (A => A_in , B => B_in , X1 => X1_out);
dut5 : Porta_OR port map (X0 => X0_out , X1 => X1_out, Cout => Cout_out);

process
begin
A_in <= '0';
B_in <= '0';
Cin_in <= '0';
wait for 1 ns;
assert(S_out='0') report "Erro na entrada 0/0/0" severity error;
assert(Cout_out='0') report "Erro na entrada 0/0/0" severity error;

A_in <= '0';

B_in <= '0';
Cin_in <= '1';
wait for 1 ns;
assert(S_out='1') report "Erro na entrada 0/0/1" severity error;
assert(Cout_out='0') report "Erro na entrada 0/0/1" severity error;

A_in <= '0';

B_in <= '1';
Cin_in <= '0';
wait for 1 ns;
assert(S_out='1') report "Erro na entrada 0/1/0" severity error;
assert(Cout_out='0') report "Erro na entrada 0/1/0" severity error;

A_in <= '0';

B_in <= '1';
Cin_in <= '1';
wait for 1 ns;
assert(S_out='0') report "Erro na entrada 0/1/1" severity error;
assert(Cout_out='1') report "Erro na entrada 0/1/1" severity error;

A_in <= '1';

B_in <= '0';
Cin_in <= '0';
wait for 1 ns;
assert(S_out='1') report "Erro na entrada 1/0/0" severity error;
assert(Cout_out='0') report "Erro na entrada 1/0/0" severity error;

A_in <= '1';

B_in <= '0';
Cin_in <= '1';
wait for 1 ns;
assert(S_out='0') report "Erro na entrada 1/0/1" severity error;
assert(Cout_out='1') report "Erro na entrada 1/0/1" severity error;

A_in <= '1';

B_in <= '1';
Cin_in <= '0';
wait for 1 ns;
assert(S_out='0') report "Erro na entrada 1/1/0" severity error;
assert(Cout_out='1') report "Erro na entrada 1/1/0" severity error;

A_in <= '1';

B_in <= '1';
Cin_in <= '1';
wait for 1 ns;
assert(S_out='1') report "Erro na entrada 1/1/1" severity error;
assert(Cout_out='1') report "Erro na entrada 1/1/1" severity error;

A_in <= '0';

B_in <= '0';
Cin_in <= '0';

end process;
end behaviour;