bài 4 :

code :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Decoder_1_16 is
Port (
input : in STD_LOGIC_VECTOR(3 downto 0);
enable : in STD_LOGIC;
outputs : out STD_LOGIC_VECTOR(15 downto 0)
);
end entity Decoder_1_16;

architecture Behavioral of Decoder_1_16 is

begin
process(input, enable)
begin
if enable = '0' then
case input is
when "0000" =>
outputs <= "0000000000000001";
when "0001" =>
outputs <= "0000000000000010";
when "0010" =>
outputs <= "0000000000000100";
when "0011" =>
outputs <= "0000000000001000";
when "0100" =>
outputs <= "0000000000010000";
when "0101" =>
outputs <= "0000000000100000";
when "0110" =>
outputs <= "0000000001000000";
when "0111" =>
outputs <= "0000000010000000";
when "1000" =>
outputs <= "0000000100000000";
when "1001" =>
outputs <= "0000001000000000";
when "1010" =>
outputs <= "0000010000000000";
when "1011" =>
outputs <= "0000100000000000";
when "1100" =>
outputs <= "0001000000000000";
when "1101" =>
outputs <= "0010000000000000";
when "1110" =>
outputs <= "0100000000000000";
when others =>
outputs <= "1000000000000000"; -- Tất cả các bit đều tắt
end case;
else
outputs <= (others => '0'); -- Tắt tất cả các bit nếu enable ở mức cao
end if;
end process;
end architecture Behavioral;
*Testbench :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Decoder_1_16_TB is
end entity Decoder_1_16_TB;

architecture Behavioral of Decoder_1_16_TB is

signal input : STD_LOGIC_VECTOR(3 downto 0) := "0000";
signal enable : STD_LOGIC := '0';
signal outputs : STD_LOGIC_VECTOR(15 downto 0);

component Decoder_1_16 is
Port (
input : in STD_LOGIC_VECTOR(3 downto 0);
enable : in STD_LOGIC;
outputs : out STD_LOGIC_VECTOR(15 downto 0)
);
end component;

begin
UUT: Decoder_1_16 port map (input, enable, outputs);

process
begin
-- Test case 1: Enable = '0'
input <= "1101";
enable <= '0';
wait for 10 ns;

-- Test case 2: Enable = '1'

enable <= '1';
wait for 10 ns;

-- Add more test cases as needed

-- End simulation
wait;
end process;
end architecture Behavioral;

bài 5
*code: