TAREA 1 3ER PARCIAL

Integrantes de Equipo:
Juan Hernandez Marquez
Edgar Arredondo Rivera
 6.21 Codificador Binario 4-2
LIBRARYRR ieee;
USE ieee.std_logic_1164.all;
ENTITY cod4to2 IS
PORT(w:IN STD LOGIC VECTOR(3DOWN TO 0);
En:IN STDLOGIC;
y:OUT STD LOGIC VECTOR(0 TO 1));
END cod4to2;

ARCHITECTURE Behavior OF cod4to2 IS

BEGIN
PROCESS(w, En)
BEGIN
IF En ’1’ THEN
CASE w IS
WHEN “0001”; =>
Y<=”00”;
WHEN ”0010” =>
y<=”01” ;
WHEN ”0100” =>
y<= ”10”
WHEN OTHERS
y<=”00”;
END CASE;
ELSE y <= ”0000”;
END IF;
END PROCESS;
END Behavior;

6.22 Codificador Binario 8-3

LIBRARYRR ieee;
USE ieee.std_logic_1164.all;
ENTITY cod8to3 IS
PORT(w:IN STD LOGIC VECTOR(7 DOWN TO 0);
En:IN STDLOGIC;
y:OUT STD LOGIC VECTOR(0 TO 2));
END cod8to3;

ARCHITECTURE Behavior OF cod8to3 IS

BEGIN
PROCESS(w, En)
BEGIN
IF En ’1’ THEN
 CASE w IS
WHEN “-1111111”; =>
Y<=”000”;
WHEN ”-0111111” =>
y<=”001” ;
WHEN”-1011111” =>
y<= ”010”
WHEN”-1101111” =>
Y<=”011”;
WHEN”-1110111” =>
y<=”010”;
WHEN”-1111011” =>
y<=”011”;
WHEN”-1111101” =>
y<=”110”;
WHEN OTHERS
y<=”111”;
END CASE;
ELSE y <= ”0000”;
END IF;
END PROCESS;
END Behavior;
 6.28 Codificador Binario:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY seg7 IS
PORT (bcd:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
leds:OUT STD_LOGIC_VECTOR(1 TO7 ));
ENDseg7;
ARCHITECTURE BehaviorOF seg7 IS
BEGIN
PROCESS(bcd)
BEGIN
CASE bcd IS
WHEN”0000” =>leds<= ”1111110”;
WHEN”0001” =>leds<=”0110000”;
WHEN”0010” =>leds<=”1101101”;
WHEN”0011” =>leds<=”1111001”;
WHEN”0100” =>leds<=”0110011”;
WHEN”0101” =>leds<=”1011011”;
WHEN”0110” =>leds<=”1011111”;
WHEN”0111” =>leds<=”1110000”;
WHEN”1000” =>leds<=”1111111”;
WHEN”1001” =>leds<=”1110011”;
WHENOTHERS =>leds<=”-------”;
ENDCASE;
ENDPROCESS;
ENDBehavior;