EXPERIMENT:- 3

AIM: - Implement 8:1 multiplexer and 3:8 decoder using VHDL.

Code: -
1. 8:1 Multiplexer

-- 8to1 mux
library ieee;
use ieee.std_logic_1164.all;
entity mux8to1 is
port (d : in std_logic_vector (7 downto 0);
s: in std_logic_vector (2 downto 0);
o : out std_logic);
end mux8to1;

architecture muxaurch of mux8to1 is

begin
process (d,s)
begin
case s is
when "000" => o<= d(0);
when "001" => o<= d(1);
when "010" => o<= d(2);
when "011" => o<= d(3);
when "100" => o<= d(4) ;
when "101" => o<= d(5);
when "110" => o<= d(6);
when others => o<= d(7);
end case;
end process;
end muxaurch;

2. 3:8 Decoder

--3 to 8 decoder
library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;

entity decoder1 is
Port (
A : in STD_LOGIC_VECTOR (2 downto 0);
Y : out STD_LOGIC_VECTOR (7 downto 0)
);
end decoder1;

architecture Behavioral of decoder1 is

begin
process (A)
begin
case A is
when "000" =>
Y <= "00000001";
when "001" =>
Y <= "00000010";
when "010" =>
Y <= "00000100";
when "011" =>
Y <= "00001000";
when "100" =>
Y <= "00010000";
when "101" =>
Y <= "00100000";
when "110" =>
Y <= "01000000";
when "111" =>
Y <= "10000000";
when others =>
Y <= (others => '0');
end case;
end process;
end Behavioral;

Circuit Diagram: -
Waveform: -