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  • Expt 3 Encoder 8 3

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    Steven Vazhappully
    8 views3 pages
    The document contains code for an 8x3 encoder and testbenches for behavioral, structural, and dataflow implementations of the encoder. The encoder code maps 8 input bits to a 3-bit output using logic gates or case statements. The testbenches simulate the encoder designs by applying input test patterns and checking the output responses.

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    expt_3_encoder_8_3

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    The document contains code for an 8x3 encoder and testbenches for behavioral, structural, and dataflow implementations of the encoder. The encoder code maps 8 input bits to a 3-bit output using logic gates or case statements. The testbenches simulate the encoder designs by applying input test patterns and checking the output responses.

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    © All Rights Reserved
    Download as ODT, PDF, TXT or read online from Scribd
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    8 views3 pages

    Expt 3 Encoder 8 3

    Uploaded by

    Steven Vazhappully
    The document contains code for an 8x3 encoder and testbenches for behavioral, structural, and dataflow implementations of the encoder. The encoder code maps 8 input bits to a 3-bit output using logic gates or case statements. The testbenches simulate the encoder designs by applying input test patterns and checking the output responses.

    Copyright:

    © All Rights Reserved
    Download as ODT, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 3

    Behavioral Code for 8x3 Encoder: Testbench for Behavioral Code:

    library ieee; library ieee;


    use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
    use ieee.std_logic_arith.all; use ieee.std_logic_arith.all;
    use ieee.std_logic_unsigned.all; use ieee.std_logic_unsigned.all;

    entity encoder_8_3_behav is entity tb_encoder_8_3_behav is


    port(d: in std_logic_vector(7 downto 0); end tb_encoder_8_3_behav;
    o: out std_logic_vector(2 downto 0));
    end encoder_8_3_behav; architecture testbench of tb_encoder_8_3_behav is
    component encoder_8_3_behav
    architecture behavioural of encoder_8_3_behav is port (d: in std_logic_vector(7 downto 0);
    begin o: out std_logic_vector(2 downto 0));
    process (d) end component;
    variable temp : std_logic_vector(2 downto 0); signal d: std_logic_vector(7 downto 0);
    begin signal o: std_logic_vector(2 downto 0);
    case d is begin
    when "00000001" => temp := "000"; u1 : encoder_8_3_behav port map (d => d, o => o);
    when "00000010" => temp := "001"; process begin
    when "00000100" => temp := "010"; d<="00000001";
    when "00001000" => temp := "011" ; wait for 10 ns;
    when "00010000" => temp := "100"; d<="00000010";
    when "00100000" => temp := "101"; wait for 10 ns;
    when "01000000" => temp := "110"; d<="00000100";
    when "10000000" => temp := "111"; wait for 10 ns;
    when others => temp := "XXX"; d<="00001000";
    end case; wait for 10 ns;
    o <= temp; d<="00010000";
    end process; wait for 10 ns;
    d<="00100000";
    end behavioural; wait for 10 ns;
    d<="01000000";
    wait for 10 ns;
    d<="10000000";
    wait for 10 ns;
    end process;
    end testbench;

    Waveform:

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    Structural Code for 8x3 Encoder: Testbench for Structural Code:

    library ieee; library ieee;


    use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
    use ieee.std_logic_arith.all; use ieee.std_logic_arith.all;
    use ieee.std_logic_unsigned.all; use ieee.std_logic_unsigned.all;

    entity encoder_8_3_struct is entity tb_encoder_8_3_struct is


    port (d: in std_logic_vector(7 downto 0); end tb_encoder_8_3_struct;
    o: out std_logic_vector(2 downto 0));
    end encoder_8_3_struct; architecture testbench of tb_encoder_8_3_struct is
    component encoder_8_3_struct
    architecture structural of encoder_8_3_struct is port (d: in std_logic_vector(7 downto 0);
    component or_4_gate is o: out std_logic_vector(2 downto 0));
    port(v, w, x, y: in std_logic; z: out std_logic); end component;
    end component; signal d: std_logic_vector(7 downto 0);
    begin signal o: std_logic_vector(2 downto 0);
    A1: or_4_gate port map(d(1), d(3), d(5), d(7), begin
    o(0));
    A2: or_4_gate port map(d(2), d(3), d(7), d(6), u1 : encoder_8_3_struct port map (d => d, o => o);
    o(1));
    A3: or_4_gate port map(d(4), d(5), d(6), d(7), process begin
    o(2)); d<="00000001";
    end structural; wait for 10 ns;
    d<="00000010";
    wait for 10 ns;
    d<="00000100";
    wait for 10 ns;
    d<="00001000";
    wait for 10 ns;
    d<="00010000";
    wait for 10 ns;
    d<="00100000";
    wait for 10 ns;
    d<="01000000";
    wait for 10 ns;
    d<="10000000";
    wait for 10 ns;
    end process;
    end testbench;

    Waveform:

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    Dataflow Code for 8x3 Encoder: Testbench for Dataflow Code:

    library ieee; library ieee;


    use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
    use ieee.std_logic_arith.all; use ieee.std_logic_arith.all;
    use ieee.std_logic_unsigned.all; use ieee.std_logic_unsigned.all;

    entity encoder_8_3_dataf is entity tb_encoder_8_3_dataf is


    port(d: in std_logic_vector(7 downto 0); end tb_encoder_8_3_dataf;
    o: out std_logic_vector(2 downto 0));
    end encoder_8_3_dataf; architecture testbench of tb_encoder_8_3_dataf is
    component encoder_8_3_dataf
    architecture dataflow of encoder_8_3_dataf is port (d: in std_logic_vector(7 downto 0);
    begin o: out std_logic_vector(2 downto 0));
    o(2) <= d(4) or d(5) or d(6) or d(7); end component;
    o(1) <= d(2) or d(3) or d(6) or d(7); signal d: std_logic_vector(7 downto 0);
    o(0) <= d(1) or d(3) or d(5) or d(7); signal o: std_logic_vector(2 downto 0);
    end dataflow; begin
    u1 : encoder_8_3_dataf port map (d => d, o => o);

    process begin
    d<="00000001";
    wait for 10 ns;
    d<="00000010";
    wait for 10 ns;
    d<="00000100";
    wait for 10 ns;
    d<="00001000";
    wait for 10 ns;
    d<="00010000";
    wait for 10 ns;
    d<="00100000";
    wait for 10 ns;
    d<="01000000";
    wait for 10 ns;
    d<="10000000";
    wait for 10 ns;
    end process;
    end testbench;
    Waveform:

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