Binary to BCD Converter

Shift and Add-3 Algorithm

1. Shift the 8 bits binary number left one bit,

2. If 8 shifts have taken place, the BCD Number is in Hundreds, Tens, and Units column,
3. If the binary value in any of the BCD columns is 5 or greater, add 3 to that value in that BCD
column,
4. Go to 1.

Example 1 Convert (E)16 to BCD Example 2 Convert (EE)16 to BCD

ADD3 Circuit

Vhdl Code

Library ieee;
Use ieee.std_logic_1164.all ;
Entity ADD3 is
Port(
X : In std_logic_vector (3 downto 0);
Xp3 : out std_logic_vector (3 downto 0));
End entity;
Architecture Bhv of ADD3 is
begin
with X select Xp3 <=
"0000" when "0000",
"0001" when "0001",
"0010" when "0010",
"0011" when "0011",
"0100" when "0100",
"1000" when "0101",
"1001" when "0110",
"1010" when "0111",
"1011" when "1000",
"1100" when "1001",
"----" when others;
end bhv;
Binary to BCD Converter Module

Library ieee;
Use ieee.std_logic_1164.all ;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
Entity Bin2BcdC is
Port(
X : In std_logic_vector (7 downto 0);
C, d, u: out std_logic_vector (3 downto 0));
End entity;
Architecture Behavioural of Bin2BCDC is
Component ADD3 is
Port(
X : In std_logic_vector (3 downto 0);
Xp3 : out std_logic_vector (3 downto 0));
End component;
-- Company: Enp Algiers signal XT1,RT1, XT2, RT2, XT3, RT3, XT4, RT4,
-- Engineer: MSCL XT5, RT5,XT6,RT6,XT7,RT7:std_logic_vector (3
-- Create Date: 23:32:06 downto 0);
04/14/2018
-- Design Name:
Begin
-- Module Name: bin2bcd - XT1<=('0',X(7),X(6),X(5));
Behavioral u1t: ADD3 port map (XT1, RT1);
-- Project Name: XT2<=(RT1(2),RT1(1),RT1(0),X(4));
-- Target Devices: Spartan 3E u2t: ADD3 port map (XT2, RT2);
-- Tool versions: Ise 14.1 XT3<=(RT2(2),RT2(1),RT2(0),X(3));
-- Description: Binary to BCD u3t: ADD3 port map (XT3, RT3);
Converter Based on Shift and XT4<=(RT3(2),RT3(1),RT3(0),X(2));
Add3 Algorithm u4t: ADD3 port map (XT4, RT4);
-- Dependencies: ADD3.vhd
XT6<=('0',RT1(3),RT2(3),RT3(3));
u6t: ADD3 port map (XT6, RT6);
XT5<=(RT4(2),RT4(1),RT4(0),X(1));
u5t: ADD3 port map (XT5, RT5);
XT7<=(RT6(2),RT6(1),RT6(0),RT4(3));
u7t: ADD3 port map (XT7, RT7);
c<="00"&RT6(3)&RT7(3);
d<=(RT7(2),RT7(1),RT7(0), RT5(3));
u<=(RT5(2),RT5(1),RT5(0), X(0));
end Behavioural;