8×3 encoder using VHDL

Decade Counter

library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use
IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity decade is
Port ( rst,clk: in std_logic;
q : buffer std_logic_vector(3 downto 0):="0000");
end decade ;

architecture Behavioral of decade is

begin
process(clk,rst) is
begin
if (CLK'event and clk='0') then
if(rst='1') or (q="1010") then
q<="0000";
else
q <= q+1;
end if;
end if;
end process;
end Behavioral;
Synchronous MOD-8 Counter

library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use
IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity mod8 is

Port ( rst,clk: in std_logic;

q : buffer std_logic_vector(2 downto 0):="000");
end mod8;

architecture Behavioral of mod8 is

begin
process(clk, rst) is
begin
if (CLK'event and clk='0') then
if(rst='1’) or (q= “111”) then
q<="000";
else
q <= q+1;
end if;
end if;
end process;
end Behavioral;