Practica No4.

Simulaciones mediante fuentes test bench

VHDL Module

entity Circuito_b is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
X : out STD_LOGIC);
end Circuito_b;

architecture Behavioral of Circuito_b is

begin
X <= '0' when A= "0000" else
'0' when A= "0001" else
'0' when A= "0010" else
'0' when A= "0011" else
'0' when A= "0100" else
'0' when A= "0101" else
'0' when A= "0110" else
'0' when A= "0111" else
'1' when A= "1000" else
'1' when A= "1001" else
'1' when A= "1010" else
'1' when A= "1011" else
'0' when A= "1100" else
'0' when A= "1101" else
'1' when A= "1110" else
'0' when A= "1111";

end Behavioral;
Test bench
BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: Circuito_b PORT MAP (
A => A,
X => X
);

-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
A <= "1011";
wait for 20 ns;
A <= "0110";
wait for 190 ns;
A <= "1111";
wait for 20 ns;
A <= "1001";
wait for 150 ns;
A <= "0101";
wait for 250 ns;
A <= "1001";
wait for 180 ns;
wait;
end process;

END;
VHDL Module

entity circuito_c is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
X : out STD_LOGIC);
end circuito_c;

architecture Behavioral of circuito_c is

begin
X <= '0' when A= "0000" else
'0' when A= "0001" else
'1' when A= "0010" else
'0' when A= "0011" else
'0' when A= "0100" else
'0' when A= "0101" else
'0' when A= "0110" else
'0' when A= "0111" else
'1' when A= "1000" else
'1' when A= "1001" else
'1' when A= "1010" else
'1' when A= "1011" else
'0' when A= "1100" else
'0' when A= "1101" else
'0' when A= "1110" else
'0' when A= "1111";

end Behavioral;
Test bench

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: circuito_c PORT MAP (
A => A,
X => X
);

-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
A <= "1010";
wait for 220 ns;
A <= "1011";
wait for 130 ns;
A <= "1111";
wait for 25 ns;
A<= "0101";
wait for 100 ns;
A <= "1100";
wait for 90 ns;
A <= "1001";
wait for 110 ns;

wait;
end process;

END;
VHDL Module

entity circuito_d is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
X : out STD_LOGIC);
end circuito_d;

architecture Behavioral of circuito_d is

begin
X <= '0' when A= "0000" else
'0' when A= "0001" else
'0' when A= "0010" else
'0' when A= "0011" else
'0' when A= "0100" else
'0' when A= "0101" else
'0' when A= "0110" else
'0' when A= "0111" else
'1' when A= "1000" else
'1' when A= "1001" else
'1' when A= "1010" else
'1' when A= "1011" else
'0' when A= "1100" else
'0' when A= "1101" else
'1' when A= "1110" else
'0' when A= "1111";

end Behavioral;
Test bench

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: circuito_d PORT MAP (
A => A,
X => X
);

-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
A <= "0101";
wait for 250 ns;
A <= "0010";
wait for 180 ns;
A <= "1111";
wait for 210 ns;
A <= "1010";
wait for 120 ns;
A <= "0101";
wait for 100 ns;
A <= "1101";
wait for 25 ns;
wait;
end process;

END;