Bi 1: Mch gii m BCD 7 on cho LED loi katot chung.

Library IEEE; use IEEE. STD_LOGIC_1164. ALL; use IEEE. STD_LOGIC_UNSIGNED. ALL; entity BCD to led 7 doan katot chung is port ( BCD: in std_logic_vector (3 DOWNTO 0); Led 7 doan katot chung: out std_ logic_vector (6 DOWNTO 0); end BCD to led 7 doan katot chung; architecture Behavioral of BCD to led 7 doan katot chung is begin with BCD select --abcdefg Led 7 doan katot chung <= "1111110" when x "0", "0110000" when x "1", "1101101" when x "2", "1111001" when x "3", "0110011" when x "4", "1011011" when x "5", "1011011" when x "6", "1110000" when x " 7",

"1111111" when x "8", "1111011" when x "9 ", "0000000" when others; end Behavioral;

Bi 2: JK ng b kch khi ti sn dng. Library IEEE; use IEEE. STD_LOGIC_1164. ALL; use IEEE. STD_LOGIC_UNSIGNED. ALL; entity JKFF is port ( JK, CLK : in std_logic; Q, not Q: out std_logic); end JKFF; architecture Behavioral of JKFF is signal Q temp: std_logic; signal JK: std_logic_vector (0 to 1); begin JK <= (J, K); Process (CLK) Begin If (CLK ' event and CLK = ' 1 ') then case JK is

when "00" => Null; when "01" => Q temp <= '0'; when "10" => Q temp <= '1'; when others => Q temp <= not Q temp; end case; end if; Q <= Q temp; end Behavional;

Bi 3: B m li 4 bit c u vo set hot ng ti sn m.

Library IEEE; use IEEE. STD_LOGIC_1164. ALL; use IEEE. STD_LOGIC_UNSIGNED. ALL; entity FSM is port ( CLK, SET, UP : in std_logic; z : out std_logic); end; architecture Behavioral of FSM is signal sreg : std_logic_vector ( 3 DOWNTO 0) constant s0 : std_ logic_vector ( 3 DOWNTO 0): = "0000";

Constant S1: std_logic_vector (3 DOWNTO 0): = "0001"; Constant S2: std_logic_vector (3 DOWNTO 0): = "0010"; Constant S3: std_logic_vector (3 DOWNTO 0): = "0011"; Constant S4: std_logic_vector (3 DOWNTO 0): = "0100"; Constant S5: std_logic_vector (3 DOWNTO 0): = "0101"; Constant S6: std_logic_vector (3 DOWNTO 0): = "0110"; Constant S7: std_logic_vector (3 DOWNTO 0): = "0111"; Constant S8: std_logic_vector (3 DOWNTO 0): = "1000"; Constant S9: std_logic_vector (3 DOWNTO 0): = "1001"; Constant S10: std_logic_vector (3 DOWNTO 0): = "1010"; Constant S11: std_logic_vector (3 DOWNTO 0): = "1011"; Constant S12: std_logic_vector (3 DOWNTO 0):

= "1100"; Constant S13: std_logic_vector (3 DOWNTO 0): = "1101"; Constant S14: std_logic_vector (3 DOWNTO 0): = "1110"; Constant S15: std_logic_vector (3 DOWNTO 0): = "1111"; Signal next_z : std_logic; Begin Sync : PROCESS (SET) Begin if CLK = '0 and CLK' event then if SET = '1' then sreg <= s15; else sreg <= next_sreg; end if; end if; END PROCESS; Comb : PROCESS (sreg, up) Begin Case sreg is WHEN s15 => If ( UP = '0' ) then

next_sreg <= s14; WHEN s14 => If ( UP = '0' ) then next_sreg <= s13; WHEN s13 => If ( UP = '0' ) then next_sreg <= s12; WHEN s12 => If ( UP = '0' ) then next_sreg <= s11; WHEN s11 => If ( UP = '0' ) then next_sreg <= s10; WHEN s10 => If ( UP = '0' ) then next_sreg <= s9; WHEN s9 => If ( UP = '0' ) then next_sreg <= s8; WHEN s8 => If ( UP = '0' ) then next_sreg <= s7; WHEN s7 =>

If ( UP = '0' ) then next_sreg <= s6; WHEN s6 => If ( UP = '0' ) then next_sreg <= s5; WHEN s5 => If ( UP = '0' ) then next_sreg <= s4; WHEN s4 => If ( UP = '0' ) then next_sreg <= s3; WHEN s3 => If ( UP = '0' ) then next_sreg <= s2; WHEN s2 => If ( UP = '0' ) then next_sreg <= s1; WHEN s1 => If ( UP = '0' ) then next_sreg <= s0; WHEN s0 => If ( UP = '0' ) then next_sreg <= s9;

end if; when others => next_ sreg <= s0 end case; end PROCESS; outputs : PROCESS (sreg, UP) begin if UP = '0' then if sreg = s0 then z <= '1'; else end if; end if; end PROCESS; end Behavioral; z <= '0';

NHM 7: o Vn Dng Nguyn Th Thanh H L Th Thy V nh Tin Triu nh Nguyn