Mid-Sem Assessment
VHDL Lab
Name: Siddhant Agarwal
Roll No. : 11710485
Section: EC-8
Q. Design and Simulate 8:1 MUX using 4:1 MUX.
Code:
VHDL (MUX)
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: [Link] 11/02/2020
-- Design Name:
-- Module Name: mux - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux is
port(
A: in std_logic_vector(7 downto 0);
S: in std_logic_vector(2 downto 0);
Z: out STD_LOGIC
);
end mux;
architecture Behavioral of mux is
component mux4 is
port (A: in std_logic_vector(3 downto 0);
S: in std_logic_vector(1 downto 0);
Z: out STD_LOGIC);
end component;
component mux2
port( A: in std_logic_vector (1 downto 0);
S: in STD_LOGIC;
Z: out STD_LOGIC);
end component;
signal m: std_logic_vector(1 downto 0);
begin
m1: mux4 port map(A(3 downto 0),S(1 downto 0),m(0));
m2: mux4 port map(A(7 downto 4),S(1 downto 0),m(1));
m3: mux2 port map(m,S(2),Z);
end Behavioral;
4:1 MUX Code
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity mux4 is
port(
A: in std_logic_vector(3 downto 0);
S: in std_logic_vector(1 downto 0);
Z: out STD_LOGIC
);
end mux4;
architecture bhv of mux4 is
begin
process (A,S) is
begin
if (S(0) ='0' and S(1) = '0') then
Z <= A(0);
elsif (S(0) ='1' and S(1) = '0') then
Z <= A(1);
elsif (S(0) ='0' and S(1) = '1') then
Z <= A(2);
else
Z <= A(3);
end if;
end process;
end bhv;
2:1 MUX Code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux2 is
port(A: in std_logic_vector(1 downto 0);
S: in STD_LOGIC;
Z: out STD_LOGIC);
end mux2;
architecture Behavioral of mux2 is
begin
process (A,S) is
begin
if (S ='0') then
Z <= A(0);
else
Z <= A(1);
end if;
end process;
end Behavioral;
Test Bench VHDL Code:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_mux IS
END tb_mux;
ARCHITECTURE behavior OF tb_mux IS
COMPONENT mux
PORT(
A : IN std_logic_vector(7 downto 0);
S : IN std_logic_vector(2 downto 0);
Z : OUT std_logic
);
END COMPONENT;
signal A : std_logic_vector(7 downto 0) := (others => '0');
signal S : std_logic_vector(2 downto 0) := (others => '0');
--Outputs
signal Z : std_logic;
BEGIN
uut: mux PORT MAP (
A => A,
S => S,
Z => Z
);
-- Stimulus process
stim_proc: process
begin
-- wait for 100 ns;
A<="10101010";
S<="000";
wait for 100 ns;
S<="001";
wait for 100 ns;
S<="010";
wait for 100 ns;
S<="011";
wait for 100 ns;
A<="11110000";
S<="000";
wait for 100 ns;
S<="001";
wait for 100 ns;
S<="010";
wait for 100 ns;
S<="011";
wait for 100 ns;
A<="00001111";
S<="000";
wait for 100 ns;
S<="001";
wait for 100 ns;
S<="010";
wait for 100 ns;
S<="011";
wait;
end process;
END;
Waveform
