Digital Integrated Circuits

(83-313)

Lecture 6:
Interconnect
Dr. Adam Teman
4 June 2020

Disclaimer: This course was prepared, in its entirety, by Adam Teman. Many materials were copied from sources freely available on the internet. When possible, these sources have been cited;
however, some references may have been cited incorrectly or overlooked. If you feel that a picture, graph, or code example has been copied from you and either needs to be cited or removed,
please feel free to email adam.teman@biu.ac.il and I will address this as soon as possible.
 Lecture Content

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June 4, 2020
 A First Glance at
Interconnect

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 The Wire

Transmitters Receivers

schematic view physical realization All-inclusive model Capacitance-only

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 Impact of Interconnect Parasitics
• Interconnect parasitics affect all the metrics we care about
• Reliability
• Performance
• Power Consumption
• Cost
• Classes of parasitics
• Capacitive
• Resistive
• Inductive

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 Modern Interconnect

Intel 10nm Interconnect Stack

Source: Intel, IEDM 2017
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 Capacitance

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 Capacitance of Wire Interconnect
CGSP CGSP
S S
CSBP CSBP
G G
B CDBP B
CGBP CDBP
CGBP
CGDP CGDP
D D
Vin CGDN Vout Vin CGDN Vout
D D
CDBN CDBN
CGBN Cwire CGBN
Cload
G B G B
CSBN CSBN
CGSN S CGSN S Simplified
Interconnect Model

Fanout
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 Capacitance: The Parallel Plate Model
• How can we reduce this capacitance? Typical numbers:
• Wire cap ~0.2 fF/um
• Gate cap ~2 fF/um
Current flow
• Diffusion cap ~2 fF/um
L

W Electrical-field lines

H
 di
t di Dielectric
c pp = WL
Substrate
tdi

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 Permittivity

Air Gaps (implemented in Intel 14nm)

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 Fringing Capacitance

(a)
(a)
H W - H/2
H W - H/2

w =W − H / 2
+

(W − H 2 )  di
(b)
2 di
(b)

C F mm  = c pp + c fringe = +
tdi log ( t di H )
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 Fringing versus Parallel Plate

C fringe C fringe  L
 0.05 fF
edge m CPP  W  L
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 A simple model for deriving wire cap
• Wiring capacitances in 0.25μm Cwire = C parallel _ plate W  L
aF/µm2 Bottom Plate + 2  C fringe  L

aF/µm
fringing parallel
Top Plate

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 Impact of Interwire Capacitance

Stanford: EE311
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 Coupling Capacitance and Delay

CC1

CC2 CL

Ctot = CL
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 Coupling Capacitance and Delay

CC1

CC2 CL
1

Ctot = CL + CC1 + CC 2
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 Coupling Capacitance and Delay

CC1

CC2 CL

Ctot = CL + 2 ( CC1 + CC 2 )
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 Example – Coupling Cap
• A pair of wires, each with a capacitance to ground of 5pF, have a 1pF coupling
capacitance between them.
• A square pulse of 1.8V (relative to ground)
is connected to one of the wires.
• How high will the noise pulse be
on the other wire?

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 Example – Coupling Cap
• Draw an Equivalent Circuit:

Vin  Ccoupled 1.8 1 p

VC 2 = = = 0.3V
Ccoupled + C2 1 p + 5 p
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 Coupling Waveforms
• Simulated coupling for Cagg=Cvictim
Aggressor
1.8

1.5

1.2

CC Cagg
Victim (undriven): 50%
0.9

Cvictim 0.6
Victim (half size driver): 16%

Victim (equal size driver): 8%

0.3
Victim (double size driver): 4%

0 200 400 600 800 1000 1200 1400 1800 2000

20 t (ps) © Adam Teman,

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 Shielding

Source: Kose, et al

21 Source: Design-reuse.com © Adam Teman,

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 Feedthrough Cap

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 Measuring Capacitance

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The Computer Hall of Fame
• The first computer or not the first computer?

Source: US Army.

• Electronic Numerical Integrator and Calculator

• 20,000 vacuum tubes, 1500 relays,

10,000 capacitors, 70,000 resistors
• 200kW, 30 tons, cost almost $500K
• Completed in 1946 at the University of Pennsylvania
by John Eckert and John Mauchly
• Used to calculate artillery firing tables for the
US Army's Ballistic Research Laboratory
• Lost the patent for being the first computer in 1973,
but it was the first general purpose programmable computer. Source: Wikipedia
 Resistance

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 Wire Resistance
R= L
HW
R= L
L
HW
Sheet Resistance
H Ro Metal Bulk
resistivity
L R1
Sheet Resistance (W*cm)
R2
H W Ro Silver (Ag) 1.6
Copper (Cu) 1.7
R1 R2 Gold (Au) 2.2
W
Aluminum (Al) 2.8
L L L 
R= = = Rsq , Rsq Tungsten (W) 5.3

A H W W H Molybdenum (Mo) 5.3

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 Sheet Resistance
• Typical sheet resistances for 180nm process

Layer Sheet Resistance (W/)

N-Well/P-Well 1000-1500
Diffusion (silicided) 3-10
Diffusion (no silicide) 50-200
Polysilicon (silicided) 3-10
Polysilicon (no silicide) 50-400 Silicides: WSi 2, TiSi 2, PtSi 2 and TaSi
Metal1 0.08
Conductivity: 8-10 times better than Poly
Metal2 0.05
Metal3 0.05
Metal4 0.03
mW
Metal5 0.02 R  100
Metal6 0.02 square
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 Contact Resistance
• Contact/Vias add extra resistance
• Similar to changing between roads on the way to a destination…
• Contact resistance is generally 2-20 Ω

• Make contacts bigger

• BUT… current “crowds” around the perimeter of a contact.
• There are also problems in deposition…
• Contacts/Vias have a maximum practical size.
• Use multiple contacts
• But does this add overlap capacitance?

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 Dealing with Resistance
• Selective Technology Scaling
• Don’t scale the H
• Use Better Interconnect Materials
• reduce average wire-length
• e.g. copper, silicides
• More Interconnect Layers
• reduce average wire-length
• Minimize Contact Resistance
• Use single layer routing
• When changing layers, use lots of contacts. 90nm Process

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 Interconnect Modeling

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 The Ideal Model
• In schematics, a wire has no parasitics:
• The wire is a single equipotential region.
• No effect on circuit behavior.
• Effective in first stages of design and for very short wires.

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 The Lumped Model
Rwire=1Ω
Driver
Cwire
Vout

Ron=1kΩ-10kΩ

Rdriver
Vout
Vin
DC
Clumped

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 The Distributed RC-line
• But actually, our wire is a distributed entity.
• We can find its behavior by breaking it up into small RC segments.

Vi −1 − Vi Vi − Vi +1 dVi Vi  2Vi

IC = − = cdx → rc = 2
rdx rdx dt t x
f ( x + dx ) − f ( x ) rc 2
lim
dx →0 dx
= f '( x) = L t pd = 0.38RC
2
Quadratic dependence The lumped model is
on wire length pessimistic
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 Step-response of RC wire
• Step-response of RC wire as a function of time and space

x=L/10 x=L/2 x=L

x=L/4

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 Modeling the distributed Cap Cw  0.2
fF
μm
• Let’s look at a driver with a distributed wire and an output load. W
• For the driver resistance,
R  0.1
we can lump the output load as a capacitor.
• For the wire resistance, we will use the distributed time constant.
• For the load capacitance, we can lump the wire and driver resistance.

Rinv Rwire

Cinv Cwire Cload Cinv Cwire Cload

 D = 0.69 Rinv ( Cinv + Cwire ) + 0.38RwireCwire + 0.69 ( Rinv + Rwire ) Cload

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 Elmore Delay Approximation
• Solving the diffusion equation for a given network is complex.
• Elmore proposed a reasonably accurate method to achieve an approximation of
the dominate pole.

R1 R2 R3
Vin Vout

C1 C2 C3

 elmore = R1C1 + ( R1 + R2 ) C2 + ( R1 + R2 + R3 ) C3
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 Elmore Generalized Ladder Chain
• Lets apply the Elmore approximation for our original distributed wire.
• Divide the wire into N equal segments of dx=L/N length with capacitance cdx
and resistance rdx.

 L  L L L
 N = c   r + 2r + .. + Nr 
 N  N N N
2  N ( N + 1) 
2
L
=   ( rc + 2rc + .. + Nrc ) = rcL  2 
N  2N 
2
rcL RC
lim  D = =
N → 2 2
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 Elmore Delay Approximation
For a complex network use the following method:
• Find all the resistors on the path from in to out.
• For every capacitor:
• Find all the resistors on the path from the input to the capacitor.
• Multiply the capacitance by the resistors that are also on the path to out.
• The dominant pole is approximately the sum of all these time constants.

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 Simple Elmore Delay Example
R1 R2
Vin Vout
C1 C2
R3

C3

 elmore = R1C1 + ( R1 + R2 ) C2 + ( R1 ) C3
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 General Elmore Delay Example

 elmore = R1C1 + R1C2 + ( R1 + R3 ) C3 + ( R1 + R3 ) C4 + ( R1 + R3 + Ri ) Ci

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RC-Models

T-Model
Pie Model

T-2 Model
Pie-2 Model

T-3 Model
Pie-3 Model

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 Using the Elmore Delay and Pi Model
• Inverter driving a wire and a load cap.

Cinv Cwire Cload

Rinv Rwire

Cinv Cwire/2 Cwire/2 Cload

 driver =  Cinv + Cwire 2  Rinv +  Cload + Cwire 2  ( Rinv + Rwire )

   
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 Dealing with long wires
• Repeater Insertion

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 Dealing with long wires
• Buffer Tree Insertion

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 Wire Scaling

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 Wire Scaling
• We could try to scale interconnect
at the same rate (S) as device dimensions.
• This makes sense for local wires
that connect smaller devices/gates.
• But global interconnections, such as clock
signals, buses, etc., won’t scale in length.
• Length of global interconnect is proportional
to die size or system complexity.
• Die Size increased by 6% per year (X2 @10 years) for a while.
• Devices have scaled, but complexity has grown!

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 Local Wire Scaling
• Looking at local interconnect:
• W, H, t, L all scale at 1/S
• C=LW/t→1/S
• R=L/WH →S So the delay of local
• RC=1 interconnect stays
constant.
• Reminder – Full Scaling of Transistors
• Ron=VDD/Ion α 1 But the delay of local
• tpd=RonCg α 1/S interconnect increases
relative to transistors!
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 Local Wire Scaling – Full Scaling
• What about fringe cap?

H H/S

t t/S

Cpp  WL Cfringe  L
t Cpp  S −1 Cfringe  S −1
Rwire  L tp,wire  RwireCwire Rwire  S tp,wire  const
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WH
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 Local Wire Scaling - Constant Thickness
• Wire thickness (height) wasn’t scaled!

H
H
t
t/S

Cpp  WL Cfringe  L
t Cpp  S −1 Cfringe  S −1
Rwire  L tp,wire  RwireCwire Rwire  const tp,wire  S −1
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WH
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 Local Wire Scaling – Interwire Capacitance
• Without scaling height, coupling gets much worse.
• Aspect ratio is limited and we eventually have to scale the height.

Cpp, side  LH Cpp, side  const

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D
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 Nature of Interconnect

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 Global Wire Scaling
• Looking at global interconnect:
• W, H, t scale at 1/S
• L doesn’t scale!
• C=LW/t→1
• R=L/WH → S2 Long wire
• RC=S2 !!! delay
increases
quadratically!!
!
• And if chip size grows, L actually increases!

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 Global Wire Scaling – Constant Thickness
• Leave thickness constant for global wires
• But wire delay still gets quadratically worse than gate delay…

H H

t t/S

Cpp  WL Cfringe  L
t Cpp  const Cfringe  const
Rwire  L tp,wire  RwireCwire Rwire  S tp,wire  S
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WH
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 Wire Scaling
• So whereas device speed increases with scaling:
• Local interconnect speed stays constant.
• Global interconnect delays increase quadratically.
• Therefore:
• Interconnect delay is often the limiting factor for speed.
• What can we do?
• Keep the wire thickness (H) fixed.
• This would provide 1/S for local wire delays
and S for constant length global wires.
• But fringing/coupling capacitance increase, so this is optimistic.

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 Wire Scaling
• What is done today?
• Low resistance metals.
• Low-K insulation.
• Low metals (M1, M2) are used for local
interconnect, so they are thin and dense.
• Higher metals are used for global routing,
so they are thicker, wider and spaced
farther apart.

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 Modern Interconnect

Intel 45 nm Stack [Moon08]

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Metal Stack Growth

Source: Tech Design Forums © Adam Teman,

June 4, 2020
 Further Reading

• J. Rabaey, “Digital Integrated Circuits” 2003, Chapter 4

• E. Alon, Berkeley EE-141, Lectures 15,16 (Fall 2009)

http://bwrc.eecs.berkeley.edu/classes/icdesign/ee141_f09/

• B. Nicolic, Berkeley EE-241, Lecture 3 (Spring 2011)

http://bwrc.eecs.berkeley.edu/classes/icdesign/ee241_s11

• Stanford EE311

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