Bal22 La d803p

5 4 3 2 1
PROJECT NAME : BAL22 15" , BAL32 17"

PCB NO : LA-D803P(Bristol)
Dell / Compal Confidential

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AMD Bristol
Schematic Document
L o
AMD R16M-M70 (23 X 23mm)+GDDR5 x4
E L
C
2016-06.21 Rev: 1.0 (A00)
r D C
@ : Un-pop Component
FX_R3@/A12_R3@/A10_R3@:APU R3 PN
FX_R1@/A12_R1@/A10_R1@:APU R1 PN
l f o
45@/ HDMI LOGO
PCB@/ MB part number
t ia
PCB_R3G@/PCB_R3T@PCB_R3H@:PCB R3 PN
r n
ST@ / stoney only
BR@ /Bristol only
id
4G_S@/4G_M@/4G_H@/2G_H@/2G_M@/2G_S:VRAM Strap Pin:
S4G_R1@:samsung R1/ H4G_R1@:Hynix R1 /M4G_R1@ :Micron R1
B
n f
S4G_R3@:samsung R3/ H4G_R3@:Hynix R3 /M4G_R3@ :Micron R3
DIS@/ GPU only
B
c o
M30@/ R16M1-M30
M70@ /R16M1-M70
a l M30_R3@/M70_R3@:GPU R3 PN
M30_R1@/M70_R1@:GPU R1 PN
UMA@/ UMA only
m p TI@/PARADE@/NRDSA@ : SATA
3234@/3246@ :Audio
EMI@/ESD@/RF@ : EMI, ESD ,RF Component
co
A
@EMI@/@ESD@/@RF@ : EMI, ESD,RF unpop A
KBBL@:for KB backlight use

PTP@/NPTP@/TP_WAKE@:Touch pad
HDT@ /Debug use Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2016/01/07 Deciphered Date 2017/01/07 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS A00
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. BAL22 LA-D803P
Date: Tuesday, June 21, 2016 Sheet 1 of 56
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VRAM 256M*16
GDDR5 *4 Page 38,39
64bit AMD R16M-M1-70
FCBGA631
35W 23x23mm
PEG 2.0 x4
Memory Bus Bristol support two CHs
DDR4-DIMM X2
1.2V DDR4
Page 13~14
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eDP Conn.
Page 16
Page 33~40
DP0 eDP USB 3.0 Port 1

Port 1
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USB 3.0 Conn. 1
USB 2.0 Conn. 1 Page 23
HDMI Conn.
Page 17
DP1 DDI AMD
Bristol
Processor USB2.0
E LPort 2
Port 2
USB 3.0 Conn. 2
USB 2.0 Conn. 2 Page 23
D
BGA 968
USB 2.0 Conn. 3
r
Port 6
C
PCI-E For DB C
Port 1
NGFF 2230
WiFi/BT4.0
x1
Page 20
Port 0
Ethernet
RTL8106E
10/100
x1
Page 19
l f o Port 4
Port 7
NGFF 2230
WiFi/BT4.0
Digital Camera /IR Camera
Page 20
Port 2
t ia Port 5
(With Digital MIC) Page 16
Touch Screen
Page 16
r n Port 0 Card Reader

RTS5170 Page 21
id
SATA HDD Conn. Port 0 SATA Rediver SATA3.0
Page 22
Page 22
f
Digital Mic.
B B
n
SATA ODD Conn. Port 1 SATA3.0
Page 22 HD Audio Audio Codec Headphone Jack /
o
ALC3234 Mic. Jack combo Page 25
Page 18
On IO/B
l c
SPI ROM
128Mb Page 10
SPI
Page 6~12 Int. Speaker R / L
Page 18
SUB-BOARDS
pa LPC Bus
33MHz
I2C
m Int.KBD ENE KBC PS/2

ODD BOARD I/O BOARD with KBBL KB9022QD Touch Pad
co
Page 24 Page 27 Page 24
A A
FAN CONN Page 24
I/O BOARD POWER BOARD LED BOARD Thermal Sensor

Security Classification Compal Secret Data Compal Electronics, Inc.
Block diagram
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5 4 3 2 1
Q2516 , Q135, Q2513 AO3416L

Platform Power Sequence 8 U4 AO4304
S5_MUX_CTRL
DMN66D
U2 LM393
Q2515 , Q2514 AO3416L
+VDDCR_FCH_ALW
+0.95Valw ->+0.95VS
0.95VS_PWR_EN#
LA-D803PR03 UI5 SY6288D
Vinafix.com+5V_USB_PWR1
D
2016/04/13 A2
UL3 SY6288C
+3ALW ->+LAN_VDD33
RTC_CLK
3 AH8
AD8
GFX_VR_ON
l y D
WOL_EN
USB_EN#
ACIN AG7
n
PWRGD_VGA
12a
VGATE @ BC17
o
B5
9c 10a
POK +3VGS
APU_FCH_POK AND APU_FCH_PWRGD_R 12
A1
A3 BC9 U74 ,SY6288C
AC A3 B5 +3VALW 34 110 84 99 98 32 UC61
9 10 PXS_PWREN
L
MODE +19V_VIN 2 +5VALW BB6
A2
PU703 PU100 8
+1.8VS
L
ISL95521HRZ +19VB SY8286 A2 B4 8c
6,20 3,13 APU SUSP# U2302 EM5209VF
+17.4V_BATT+
+3VLP,VL 2 EC_RSMRST# UC1
E
100 AE4
PXS_PWREN
DC 8 +VGA_CORE 12a
MODE 4 PBTN_OUT#
B1 122 AE1 PU1100 ,ISL62771
B2 PWRGD_VGA
D
+17.4V_BATT+ PQ717 +19VB A5 B7 112 UE1 6 PM_SLP_S3#
6 AK7 9 PWROK PGOOD 20
AON6414A EC_ON EC9022QD 5 PM_SLP_S5#
r
A4 B6 14 AH5
C
6a KB_RST# PWRGD_VGA C
ON/OFF 114 2 AY15
o
10d PLT_RST# AJ3 PR1112
f
13
APU_RST# 1 +1.35V_MEM_GFX
D15
DGPU_PWROK 10d PU1400 ,SYX198
l
18
0.775PW_EN APU_PWRGD C19 12 DGPU_PWROK
a
PU800, APL5336 3 17 PXS_PWREN
+0.775VALW AH1 BB12 AN7 AR14 U15,SY8286RAC
i
LDO 10b 12a
PQ801 0.95_1.8VALW_PWREN Ch1 +0.95VSDGPU
t
121 74 116 95 127 Ch2 +1.8VGS
PLT_RST#
B7
n
VGATE
7
VR_ON
r
7a 8e A5
SYSON
11
8 +1.8V_ALW PLT_RST_VGA#
id
PU200 ,RT8207 7 PXS_RST#
9 SUSP# PU600 ,RT8061 AND Gate UV1 AL27
7 +1.2V,+0.6VS
APU_PCIE_RST# UV2 DGPU
B
9d
n f SUSP#
U2301, EM5209VF
+5VS 8a
3
+0.95VALW
PU300 , RT8237
10c B
o
U2302, EM5209VF
8 +3VS 9c
c
8b 9
47K PU500 , ISL62771 +APU_CORE_GFX
VR_ON EN_GFX ENABLE_GFX
8 +APU_CORE_GFX
l
SUSP# PU400, RT9059 PR532 PR509 VGATE
+1.5VS LDO 8d PGOOD 20 9d
APU_PWRGD
a
GFX_VR_ON 9c 9 PWROK
GFX_PWRGD
10c
m p 9 PR1085
ENABLE_APU
8
PU1001
ISL62771
+APU_CORE
+APU_CORE_NB
9a
9b
co
APU_PWRGD APU_PWRGD_BUF JHDT1 APU_PWRGD
DH1 9c 9 PWROK VGATE
A
Debug connector PGOOD 20 9d A

Power Sequence diagram
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
A00
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5 4 3 2 1
5 4 3 2 1
Board ID Table for AD channel

Vcc 3.3V +/- 1%
Ra 100K +/- 1% BOARD ID Table
Board ID Rb V AD_BID min V AD_BID typ V AD_BID max EC AD3
Board ID USB3.0
0 0 0.000V 0.000V 0.300V 0x00 - 0x13
0 bristol EVT
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1 12K +/- 1% 0.347V 0.354V 0.360V 0x14 - 0x1E
1 bristol DVT1 Port1 NA
l
2 15K +/- 1% 0.423V 0.430V 0.438V 0x1F - 0x25
D 2 bristol DVT2 D
3 20K +/- 1% 0.541V 0.550V 0.559V 0x26 - 0x30
3
n
4 27K +/- 1% 0.691V 0.702V 0.713V 0x31 - 0x3A bristol XB Port2 USB3 connector 1
4
5 33K +/- 1% 0.807V 0.819V 0.831V 0x3B - 0x45
o
5 Port3 USB3 connector 2
6 43K +/- 1% 0.978V 0.992V 1.006V 0x46 - 0x54
6
7 56K +/- 1% 1.169V 1.185V 1.200V 0x55 - 0x64
7 Port4 NA
8 75K +/- 1% 1.398V 1.414V 1.430V 0x65 - 0x76
8
L
9 100K +/- 1% 1.634V 1.650V 1.667V 0x77 - 0x87
9 USB2.0
10 130K +/- 1% 1.849V 1.865V 1.881V 0x88 - 0x96
10 Stoney
L
11 160K +/- 1% 2.015V 2.031V 2.046V 0x97 - 0xA4
11 Stoney Port0 Card Reader
12 200K +/- 1% 2.185V 2.200V 2.215V 0xA5 - 0xAF
12 Stoney
E
13 240K +/- 1% 2.316V 2.329V 2.343V 0xB0 - 0xB7
13 Stoney Port1 Touch Screen Panel
14 270K +/- 1% 2.395V 2.408V 2.421V 0xB8 - 0xBF
14 Stoney
15 330K +/- 1% 2.521V 2.533V 2.544V 0xC0 - 0xC9
15 Stoney Port2 Camera
D
16 430K +/- 1% 2.667V 2.677V 2.687V 0xCA - 0xD4
16 Stoney
17 560K +/- 1% 2.791V 2.800V 2.808V 0xD5 - 0xDD
17 Stoney Port3 USB connector 1(D/B)
r
18 750K +/- 1% 2.905V 2.912V 2.919V 0xDE - 0xF0
C 18 Stoney C
19 NC 3.000V 3.300V 3.300V 0xF1 - 0xFF
19 Stoney Port4 NGFF Card (WLAN)
SMBUS Control Table
SOURCE BATT Charger DIMM Thermal

Sensor
l f o ULT
Port5
Port6
USB connector 1
USB connector 2
V V
a
EC_SMB_CK1 KB9022Q
i
EC_SMB_DA1 Port7 NA
V
t
EC_SMB_CK2 KB9022Q
EC_SMB_DA2 PCI EXPRESS
EC_I2C_TPCLK
EC_I2C_TPDAT
APU_SCLK0
KB9022Q
APU
V
r n Lane 1 10/100 LAN
id
APU_SDATA0 Link Lane 2 NGFF Card (WLAN)
APU_SCLK1
APU
f
APU_SDATA1 Lane 3
B
APU_SIC APU
V B
n
APU_SID Lane 4
c o CLOCK SIGNAL
CLKOUT_PCIE0 10/100 LAN

Lane 5
Lane 6
PEG (AMD)M70
PEG (AMD)M70
l
Symbol Note : Lane 7 PEG (AMD)M70
a
CLKOUT_PCIE1 NGFF Card (WLAN)
: means Digital Ground Lane 8 PEG (AMD)M70
m p : means Analog Ground

CLKOUT_PCIE2
CLKOUT_PCIE3
SATA0
SATA
HDD
co
SATA1 ODD
A GFX CLK dGPU A

Notes List
Size
A00
5 4 3 2 1
5 4 3 2 1
SMBus Block Diagram RPC64

2.2K
+3VS
RPC64 2.2K
BA15 APU_SCLK0 253 DIMM1 SMBUS Address [ ]
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AY17 APU_SDATA0 254
D 253
254
DIMM2
SMBUS Address [ ]
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Bristol
AG5 I2C_CLK_TP
RP20
RP20
2.2K
2.2K
+3VS_TOUCH
JTP
L o
L
AG4 I2C_DAT_TP
RC50
+1.8VS
D E
r
BB10 EGPIO145
C EGPIO146 RC55 C
o
BB9
f
+1.8VS
RPC25.1
l
RPC25.3
1K
1K
a
APU_SIC EC_SMB_CK2
i
N-MOS
B18
t
N-MOS
B17 APU_SID
QC79CZL@ EC_SMB_DA2
n
+3VS
+3VS
RPE1.6
RPE1.5
R17
1K
r
1K
2.2K
2.2K
R16 DIS@ RV5 45.3K
id
+3VGS
DIS@ RV6 45.3K
QV1
f
EC_SMB_CK2_R 0 RE33 EC_SMB_CK2 U7
79 N-MOS VGA_SMB_CK3 UV1 GPU SMBUS Address [ ]
B N-MOS B
n
80 0 EC_SMB_DA2 VGA_SMB_DA3 U8
RE34
EC_SMB_DA2_R
EC_SMB_CK2
o
10 U2407 thermal sensor
EC_SMB_DA2
9
KBC
KB9022QD
85
86
l c
pa RPE1.7
RPE1.8
2.2K
2.2K
+3VALW
m
PR770
EC_SMB_CK1_R 0 RE31 EC_SMB_CK1
0 ohm 4
77 SCL PU703 POWER
co
SDA Charger SMBUS Address [ ]
78 0 ohm 3
0 RE33
EC_SMB_DA1_R EC_SMB_DA1 PR769
A PR20 A
100 ohm 6
CLK_SMB PBATT1 BATT SMBUS Address [ ]
100 ohm CONN
DAT_SMB 5
PR18

SMBus block diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
A00
5 4 3 2 1
5 4 3 2 1
Main Func = CPU
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UC1B
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PCIE
U10 P_GPP_RXP[0] P_GPP_TXP[0] R1 PCIE_ATX_DRX_P0 CC2241 2 .1U_0402_16V7K

[19] PCIE_ARX_DTX_P0 U9 R2 PCIE_ATX_DRX_N0 CC2251 2 PCIE_ATX_C_DRX_P0 [19]
LAN P_GPP_RXN[0] P_GPP_TXN[0] .1U_0402_16V7K LAN
[19] PCIE_ARX_DTX_N0 PCIE_ATX_C_DRX_N0 [19]
L
T6 P_GPP_RXP[1] P_GPP_TXP[1] R4 PCIE_ATX_DRX_P1 CC2261 2 .1U_0402_16V7K
[20] PCIE_ARX_DTX_P1 T5 R3 PCIE_ATX_C_DRX_P1 [20]
WLAN P_GPP_RXN[1] P_GPP_TXN[1] PCIE_ATX_DRX_N1 CC2271 2 .1U_0402_16V7K WLAN
[20] PCIE_ARX_DTX_N1 PCIE_ATX_C_DRX_N1 [20]
T9 P_GPP_RXP[2] P_GPP_TXP[2] N1
L
T8 P_GPP_RXN[2] P_GPP_TXN[2] N2 6/27 Change to 0.22U, checklist Rev1.0
P7 P_GPP_RXP[3] P_GPP_TXP[3] N4
P6 P_GPP_RXN[3] P_GPP_TXN[3] N3
E
+0.95VS RC5421 2 196_0402_1% P_ZVDDP U7 P_ZVDDP P_ZVSS/P_RX_ZVDDP U6 P_ZVSS RC5411 2 196_0402_1%
PEG_GTX_C_HRX_P0 P10 M2 PEG_HTX_C_GRX_P0
D
P_GFX_RXP[0] P_GFX_TXP[0]
PEG_GTX_C_HRX_N0 P9 P_GFX_RXN[0] P_GFX_TXN[0] M1 PEG_HTX_C_GRX_N0
PEG_GTX_C_HRX_P1 N6 P_GFX_RXP[1] P_GFX_TXP[1] L1 PEG_HTX_C_GRX_P1

PEG_GTX_C_HRX_N1 N5 P_GFX_RXN[1] P_GFX_TXN[1] L2 PEG_HTX_C_GRX_N1
r
PEG_GTX_C_HRX_P2 N9 P_GFX_RXP[2] P_GFX_TXP[2] L4 PEG_HTX_C_GRX_P2
C PEG_GTX_C_HRX_N2 N8 L3 PEG_HTX_C_GRX_N2 C
P_GFX_RXN[2] P_GFX_TXN[2]
o
PEG_GTX_C_HRX_P3 L7 P_GFX_RXP[3] P_GFX_TXP[3] J1 PEG_HTX_C_GRX_P3
PEG_GTX_C_HRX_N3 L6 P_GFX_RXN[3] P_GFX_TXN[3] J2 PEG_HTX_C_GRX_N3
f
L10 P_GFX_RXP[4] P_GFX_TXP[4] J4
L9 P_GFX_RXN[4] P_GFX_TXN[4] J3
l
K6 P_GFX_RXP[5] P_GFX_TXP[5] H2
K5 P_GFX_RXN[5] P_GFX_TXN[5] H1
a
PEG_GTX_C_HRX_P[3..0] K9 P_GFX_RXP[6] P_GFX_TXP[6] G1 PEG_HTX_C_GRX_P[3..0]
[33] PEG_GTX_C_HRX_P[3..0] K8 G2 PEG_HTX_C_GRX_P[3..0] [33]
P_GFX_RXN[6] P_GFX_TXN[6]
i
PEG_GTX_C_HRX_N[3..0] PEG_HTX_C_GRX_N[3..0]
[33] PEG_GTX_C_HRX_N[3..0] J7 G4 PEG_HTX_C_GRX_N[3..0] [33]
P_GFX_RXP[7] P_GFX_TXP[7]
t
J6 P_GFX_RXN[7] P_GFX_TXN[7] G3
n
FP4 REV 0.93
APU R1 APU R3 FP4_BGA968
UC1
SA00009LB0L
UC1
SA00009LB1L
id r
f
FX_R1@ FX_R3@
S IC FX-9800P FM980PADY44AB 2.7G BGA 968P S IC FX-9800P FM980PADY44AB 2.7G A31!

B B
UC1
SA00009LC0L
A12_R1@
UC1
SA00009LC1L
A12_R3@
o n
c
S IC A12-9700P AM970PADY44AB 2.5G BGA 968P S IC A12-9700P AM970PADY44AB 2.5G A31!
UC1
a l
SA00009LD0L
UC1
SA00009LD1L
p
A10_R1@ A10_R3@
S IC A10-9600P AM960PADY44AB 2.4G BGA 968P S IC A10-9600P AM960PADY44AB 2.4G A31!
m
co
A A

FP4 PCIE/UMI
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom A00
5 4 3 2 1
5 4 3 2 1
Main Func = CPU

UC1A UC1I
[13] DDRA_SMA[13..0] DDRA_SDQ[63..0] [13] [14] DDRB_SMA[13..0] DDRB_SDQ[63..0] [14]
MEMORY A MEMORY B
DDRA_SMA0 AE28 MA_ADD[0] MA_DATA[0] H17 DDRA_SDQ0 DDRB_SMA0 AG31 MB_ADD[0] MB_DATA[0] A25 DDRB_SDQ0
DDRA_SMA1 Y27 MA_ADD[1] MA_DATA[1] J17 DDRA_SDQ1 DDRB_SMA1 AC30 MB_ADD[1] MB_DATA[1] C25 DDRB_SDQ1
DDRA_SMA2 Y29 MA_ADD[2] MA_DATA[2] F20 DDRA_SDQ2 DDRB_SMA2 AC31 MB_ADD[2] MB_DATA[2] C27 DDRB_SDQ2
DDRA_SMA3 Y26 MA_ADD[3] MA_DATA[3] H20 DDRA_SDQ3 DDRB_SMA3 AB32 MB_ADD[3] MB_DATA[3] D27 DDRB_SDQ3
DDRA_SMA4 W28 MA_ADD[4] MA_DATA[4] E17 DDRA_SDQ4 DDRB_SMA4 AA32 MB_ADD[4] MB_DATA[4] B24 DDRB_SDQ4
DDRA_SMA5 W29 MA_ADD[5] MA_DATA[5] F17 DDRA_SDQ5 DDRB_SMA5 AA33 MB_ADD[5] MB_DATA[5] B25 DDRB_SDQ5
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DDRA_SMA6 W26 MA_ADD[6] MA_DATA[6] K18 DDRA_SDQ6 DDRB_SMA6 AA31 MB_ADD[6] MB_DATA[6] B27 DDRB_SDQ6
DDRA_SMA7 U29 MA_ADD[7] MA_DATA[7] E20 DDRA_SDQ7 DDRB_SMA7 Y33 MB_ADD[7] MB_DATA[7] A27 DDRB_SDQ7
l
DDRA_SMA8 W25 MA_ADD[8] DDRB_SMA8 AA30 MB_ADD[8]
DDRA_SMA9 U26 MA_ADD[9] MA_DATA[8] A21 DDRA_SDQ8 DDRB_SMA9 W32 MB_ADD[9] MB_DATA[8] A29 DDRB_SDQ8
D DDRA_SMA10 AG29 MA_ADD[10] MA_DATA[9] C21 DDRA_SDQ9 DDRB_SMA10 AG32 MB_ADD[10] MB_DATA[9] C29 DDRB_SDQ9 D
DDRA_SMA11 U27 C23 DDRA_SDQ10 DDRB_SMA11 Y32 B32 DDRB_SDQ10
n
MA_ADD[11] MA_DATA[10] MB_ADD[11] MB_DATA[10]
DDRA_SMA12 T28 MA_ADD[12] MA_DATA[11] D23 DDRA_SDQ11 DDRB_SMA12 W33 MB_ADD[12] MB_DATA[11] D32 DDRB_SDQ11
DDRA_SMA13 AK26 MA_ADD[13] MA_DATA[12] B20 DDRA_SDQ12 DDRB_SMA13 AL31 MB_ADD[13] MB_DATA[12] B28 DDRB_SDQ12
DDRA_BG1 T26 MA_ADD[14]/MA_BG[1] MA_DATA[13] B21 DDRA_SDQ13 DDRB_BG1 W30 MB_ADD[14]/MB_BG[1] MB_DATA[13] B29 DDRB_SDQ13
[13] DDRA_BG1 [14] DDRB_BG1
o
MEM_MA_ACT# T25 MA_ADD[15]/MA_ACT_L MA_DATA[14] B23 DDRA_SDQ14 MEM_MB_ACT# V32 MB_ADD[15]/MB_ACT_L MB_DATA[14] A31 DDRB_SDQ14
[13] MEM_MA_ACT# A23 DDRA_SDQ15 [14] MEM_MB_ACT# C31 DDRB_SDQ15
MA_DATA[15] MB_DATA[15]
MA_DATA[16] G22 DDRA_SDQ16 MB_DATA[16] E30 DDRB_SDQ16

AG26 MA_BANK[0] MA_DATA[17] H22 DDRA_SDQ17 AH32 MB_BANK[0] MB_DATA[17] E31 DDRB_SDQ17
[13] DDRA_SBS0# AG27 E25 DDRA_SDQ18 [14] DDRB_SBS0# AG33 G33 DDRB_SDQ18
MA_BANK[1] MA_DATA[18] MB_BANK[1] MB_DATA[18]
[13] DDRA_SBS1# DDRA_BG0 T29 G25 DDRA_SDQ19 [14] DDRB_SBS1# DDRB_BG0 W31 G32 DDRB_SDQ19
L
MA_BANK[2]/MA_BG[0] MA_DATA[19] MB_BANK[2]/MB_BG[0] MB_DATA[19]
[13] DDRA_BG0 J20 DDRA_SDQ20 [14] DDRB_BG0 C33 DDRB_SDQ20
[13] DDRA_SDM[7..0] E19 E22 [14] DDRB_SDM[7..0] D25 D33
DDRA_SDM0 MA_DM[0] MA_DATA[21] DDRA_SDQ21 DDRB_SDM0 MB_DM[0] MB_DATA[21] DDRB_SDQ21
DDRA_SDM1 D21 MA_DM[1] MA_DATA[22] H23 DDRA_SDQ22 DDRB_SDM1 D29 MB_DM[1] MB_DATA[22] G30 DDRB_SDQ22
DDRA_SDM2 K21 MA_DM[2] MA_DATA[23] J23 DDRA_SDQ23 DDRB_SDM2 E33 MB_DM[2] MB_DATA[23] G31 DDRB_SDQ23
L
DDRA_SDM3 F29 MA_DM[3] DDRB_SDM3 J33 MB_DM[3]
DDRA_SDM4 AP28 MA_DM[4] MA_DATA[24] F26 DDRA_SDQ24 DDRB_SDM4 AR30 MB_DM[4] MB_DATA[24] J30 DDRB_SDQ24
DDRA_SDM5 AV26 MA_DM[5] MA_DATA[25] E27 DDRA_SDQ25 DDRB_SDM5 AW30 MB_DM[5] MB_DATA[25] J31 DDRB_SDQ25
DDRA_SDM6 AR22 MA_DM[6] MA_DATA[26] J26 DDRA_SDQ26 DDRB_SDM6 BC30 MB_DM[6] MB_DATA[26] L33 DDRB_SDQ26
DDRA_SDM7 BC22 J27 DDRA_SDQ27 DDRB_SDM7 BC26 L32 DDRB_SDQ27
E
MA_DM[7] MA_DATA[27] MB_DM[7] MB_DATA[27]
K29 MA_DM[8] MA_DATA[28] H25 DDRA_SDQ28 N33 MB_DM[8] MB_DATA[28] H32 DDRB_SDQ28
MA_DATA[29] E26 DDRA_SDQ29 MB_DATA[29] H33 DDRB_SDQ29
H19 MA_DQS_H[0] MA_DATA[30] G28 DDRA_SDQ30 B26 MB_DQS_H[0] MB_DATA[30] L30 DDRB_SDQ30
[13] DDRA_SDQS0 G19 G29 DDRA_SDQ31 [14] DDRB_SDQS0 A26 L31 DDRB_SDQ31
MA_DQS_L[0] MA_DATA[31] MB_DQS_L[0] MB_DATA[31]
[13] DDRA_SDQS0# B22 [14] DDRB_SDQS0# B30
D
MA_DQS_H[1] MB_DQS_H[1]
[13] DDRA_SDQS1 A22 AN26 DDRA_SDQ32 [14] DDRB_SDQS1 A30 AN31 DDRB_SDQ32
[13] DDRA_SDQS1# F23 AP29 DDRA_SDQ33 [14] DDRB_SDQS1# F32 AP32 DDRB_SDQ33
MA_DQS_H[2] MA_DATA[33] MB_DQS_H[2] MB_DATA[33]
[13] DDRA_SDQS2 E23 AR26 DDRA_SDQ34 [14] DDRB_SDQS2 E32 AT32 DDRB_SDQ34
[13] DDRA_SDQS2# G27 AP24 DDRA_SDQ35 [14] DDRB_SDQS2# K32 AU32 DDRB_SDQ35
[13] DDRA_SDQS3 [14] DDRB_SDQS3
r
F27 MA_DQS_L[3] MA_DATA[36] AN29 DDRA_SDQ36 J32 MB_DQS_L[3] MB_DATA[36] AN33 DDRB_SDQ36
[13] DDRA_SDQS3# AP25 AN27 DDRA_SDQ37 [14] DDRB_SDQS3# AR32 AN32 DDRB_SDQ37
C [13] DDRA_SDQS4 AP26 AR29 DDRA_SDQ38 [14] DDRB_SDQS4 AR33 AR31 DDRB_SDQ38 C
[13] DDRA_SDQS4# AW27 AR27 DDRA_SDQ39 [14] DDRB_SDQS4# AW32 AT33 DDRB_SDQ39
o
[13] DDRA_SDQS5 AV27 [14] DDRB_SDQS5 AW33
MA_DQS_L[5] MB_DQS_L[5]
[13] DDRA_SDQS5# AV22 AU26 DDRA_SDQ40 [14] DDRB_SDQS5# BA29 AU30 DDRB_SDQ40
[13] DDRA_SDQS6 [14] DDRB_SDQS6
f
AU22 MA_DQS_L[6] MA_DATA[41] AV29 DDRA_SDQ41 AY29 MB_DQS_L[6] MB_DATA[41] AV32 DDRB_SDQ41
[13] DDRA_SDQS6# BA21 AU25 DDRA_SDQ42 [14] DDRB_SDQS6# BA25 BA33 DDRB_SDQ42
[13] DDRA_SDQS7 AY21 AW25DDRA_SDQ43 [14] DDRB_SDQS7 AY25 AY32 DDRB_SDQ43
[13] DDRA_SDQS7# L27 AU29 DDRA_SDQ44 [14] DDRB_SDQS7# P32 AU33 DDRB_SDQ44
l
L26 MA_DQS_L[8] MA_DATA[45] AU28 DDRA_SDQ45 N32 MB_DQS_L[8] MB_DATA[45] AU31 DDRB_SDQ45
MA_DATA[46] AW26DDRA_SDQ46 MB_DATA[46] AW31DDRB_SDQ46
AE25 MA_CLK_H[0] MA_DATA[47] AT25 DDRA_SDQ47 AE33 MB_CLK_H[0] MB_DATA[47] AY33 DDRB_SDQ47
[13] DDRA_CLK0 [14] DDRB_CLK0
a
AE26 MA_CLK_L[0] AE32 MB_CLK_L[0]
[13] DDRA_CLK0# AD26 AV23 DDRA_SDQ48 [14] DDRB_CLK0# AE30 BC31 DDRB_SDQ48
MA_CLK_H[1] MA_DATA[48] MB_CLK_H[1] MB_DATA[48]
[13] DDRA_CLK1 [14] DDRB_CLK1
i
AD27 MA_CLK_L[1] MA_DATA[49] AW23DDRA_SDQ49 AE31 MB_CLK_L[1] MB_DATA[49] BB30 DDRB_SDQ49
[13] DDRA_CLK1# AB28 AV20 DDRA_SDQ50 [14] DDRB_CLK1# AD32 BB28 DDRB_SDQ50
MA_CLK_H[2] MA_DATA[50] MB_CLK_H[2] MB_DATA[50]
t
AB29 MA_CLK_L[2] MA_DATA[51] AW20DDRA_SDQ51 AD33 MB_CLK_L[2] MB_DATA[51] AY27 DDRB_SDQ51
AB25 MA_CLK_H[3] MA_DATA[52] AR23 DDRA_SDQ52 AC33 MB_CLK_H[3] MB_DATA[52] BB32 DDRB_SDQ52
AB26 MA_CLK_L[3] MA_DATA[53] AT23 DDRA_SDQ53 AC32 MB_CLK_L[3] MB_DATA[53] BA31 DDRB_SDQ53
MA_DATA[54] AR20 DDRA_SDQ54 MB_DATA[54] BC29 DDRB_SDQ54
n
N29 MA_RESET_L MA_DATA[55] AT20 DDRA_SDQ55 T33 MB_RESET_L MB_DATA[55] BB29 DDRB_SDQ55
[13] MEM_MA_RST# AE29 [14] MEM_MB_RST# AG30
MA_EVENT_L MB_EVENT_L
[13] MEM_MA_EVENT# [14] MEM_MB_EVENT#
r
MA_DATA[56] BB23 DDRA_SDQ56 MB_DATA[56] BB27 DDRB_SDQ56
P27 MA_CKE0 MA_DATA[57] BB22 DDRA_SDQ57 U32 MB_CKE0 MB_DATA[57] BB26 DDRB_SDQ57
[13] DDRA_CKE0 P29 BB20 DDRA_SDQ58 [14] DDRB_CKE0 U33 BB24 DDRB_SDQ58
MA_CKE1 MA_DATA[58] MB_CKE1 MB_DATA[58]
[13] DDRA_CKE1 AY19 DDRA_SDQ59 [14] DDRB_CKE1 AY23 DDRB_SDQ59
id
MA_DATA[60] BA23 DDRA_SDQ60 MB_DATA[60] BA27 DDRB_SDQ60
MA_DATA[61] BC23 DDRA_SDQ61 MB_DATA[61] BC27 DDRB_SDQ61
AK27 MA0_ODT[0] MA_DATA[62] BC21 DDRA_SDQ62 AL30 MB0_ODT[0] MB_DATA[62] BC25 DDRB_SDQ62
[13] DDRA_ODT0 AL26 BB21 DDRA_SDQ63 [14] DDRB_ODT0 AM32 BB25 DDRB_SDQ63
MA0_ODT[1] MA_DATA[63] MB0_ODT[1] MB_DATA[63]
[13] DDRA_ODT1 AH25 [14] DDRB_ODT1 AJ32
f
MA1_ODT[0] MB1_ODT[0]
AL25 MA1_ODT[1] MA_CHECK[0] K26 AM33 MB1_ODT[1] MB_CHECK[0] N30
MA_CHECK[1] K28 MB_CHECK[1] N31
B AH26 MA0_CS_L[0] MA_CHECK[2] N26 AJ33 MB0_CS_L[0] MB_CHECK[2] R33 B
[13] DDRA_SCS0# [14] DDRB_SCS0#
n
AL29 MA0_CS_L[1] MA_CHECK[3] N28 AL32 MB0_CS_L[1] MB_CHECK[3] R32
[13] DDRA_SCS1# AH29 J29 [14] DDRB_SCS1# AJ30 M32
MA1_CS_L[0] MA_CHECK[4] MB1_CS_L[0] MB_CHECK[4]
AL28 MA1_CS_L[1] MA_CHECK[5] K25 AL33 MB1_CS_L[1] MB_CHECK[5] M33
MA_CHECK[6] L29 R30
o
MB_CHECK[6]
MA_CHECK[7] N25 MB_CHECK[7] R31
AG24 MA_RAS_L/MA_RAS_L_ADD[16] AH33 MB_RAS_L/MB_RAS_L_ADD[16]
[13] DDRA_SRAS# AK29 [14] DDRB_SRAS# AK32
MA_CAS_L/MA_CAS_L_ADD[15] MB_CAS_L/MB_CAS_L_ADD[15]
[13] DDRA_SCAS# [14] DDRB_SCAS#
c
AH28 MA_WE_L/MA_WE_L_ADD[14] AJ31 MB_WE_L/MB_WE_L_ADD[14]
[13] DDRA_SWE# [14] DDRB_SWE#
T80 APU_MA_VREFDQ B19 MA_VREFDQ MA_ZVDDIO_MEM_S AD29 MEM_MA_ZVDDIO 1 2 APU_MB_VREFDQ A19 MB_VREFDQ MB_ZVDDIO_MEM_S AF32 MEM_MB_ZVDDIO 1 2
T45
l
1 +1.2V_DDR +1.2V_DDR
ST@ 2 T32 M_VREF RC611 RC75
+MEM_VREF
RC458 0_0402_5% 39.2_0402_1% 39.2_0402_1%
FP4 REV 0.93 FP4 REV 0.93
Place them close to APU within 1" Place them close to APU within 1"
a
FP4_BGA968 FP4_BGA968
follow hw11 reserve 10/29
EVENT# pull high
m p 0.6V reference voltage
co
+1.2V_DDR
+1.2V_DDR change to pop 11/30

2
A RC5 A
1K_0402_1% +MEM_VREF
RC6 1 2 1K_0402_5% MEM_MB_EVENT#
1
+1.2V_DDR
2
RC8
1 2 Security Classification Compal Secret Data Compal Electronics, Inc.
1K_0402_1% CC29 CC99 Issued Date 2016/01/07 2017/01/07 Title
RC6121 2 1K_0402_5% MEM_MA_EVENT# 1000P_0402_50V7K Deciphered Date
2 1
0.1U_0402_16V7K
FP4 DDR4 MEMORY I/F
1
Custom A00
5 4 3 2 1
A B C D E
Main Func = CPU reserve 0 ohm 11/24

+3VS
2
RC60 2 1 0_0402_5%
@ RC70
2.2K_0402_5%
DP1: HDMI
1
3 1
D
PANEL_BKLEN_EC
PANEL_BKLEN [27]
DP0: eDP QC2 MESS138W-G_SOT323-3
G
Vinafix.com
2
UC1C +1.8VS
l
DISPLAY/SVI2/JTAG/TEST
1 1
del colay crt circuit 10/16 B6 A9 DP_ZVSS RC4001 2 2K_0402_1%
n
DP2_TXP[0] DP_ZVSS
A6 DP2_TXN[0] DP_AUX_ZVSS B9 DP_AUX_ZVSS RC4011 2 150_0402_1%
DP_BLON G5 PANEL_BKLEN_EC
D7 DP2_TXP[1] DP_DIGON G6 ENVDD_R
o
C7 DP2_TXN[1] DP_VARY_BL F11 INVTPWM_R
A7 DP2_TXP[2] del edp hpd buffer 10/28

B7 DP2_TXN[2] DP2_AUXP H9
DP2_AUXN G9
remove cap for emi 10/16 Place near APU D9 DP2_TXP[3] DP2_HPD E9
C9
L
DP2_TXN[3]
DP1_AUXP F7
APU_HDMI_CLK [17]
HDMI_DP1_TXP0 A2 DP1_TXP[0] DP1_AUXN E7
[17] HDMI_DP1_TXP0 HDMI_DP1_TXN0 A3 F5 APU_HDMI_DATA [17]
DP1_TXN[0] DP1_HPD
[17] HDMI_DP1_TXN0 DP1_HPD [17] VDD_33 +3VS
L
HDMI_DP1_TXP1 B4 DP1_TXP[1] DP0_AUXP F8 +1.8VS
[17] HDMI_DP1_TXP1 HDMI_DP1_TXN1 A4 E8 EDP_AUXP [16] ENVDD 1 2
DP1_TXN[1] DP0_AUXN
[17] HDMI_DP1_TXN1 G8 DP0_HPD EDP_AUXN [16] +3VALW
HDMI DP0_HPD RC690
DP0_HPD [16] VDD_33
5
HDMI_DP1_TXP2 D5 DP1_TXP[2] UC64 4.7K_0402_5%
[17] HDMI_DP1_TXP2
HDMI_DP1_TXN2 C5 K24 CORETYPE 1 2 1 INVTPWM 1 2
E
DP1_TXN[2] RSVD_1 @
P
[17] HDMI_DP1_TXN2 E15 TEMPIN0 NC 4
TEMPIN0
T28 RC654 RC691
HDMI_DP1_TXP3 A5 E14 TEMPIN1 ENVDD_R 2 Y ENVDD [16]
DP1_TXP[3] TEMPIN1
T29 100K_0402_5% 4.7K_0402_5%
[17] HDMI_DP1_TXP3 A
G
HDMI_DP1_TXN3 B5 DP1_TXN[3] TEMPIN2 E12 TEMPIN2
[17] HDMI_DP1_TXN3 T30
TEMPINRETURN F14 TEMPINRETURN NL17SZ07DFT2G_SC70-5
T31
3
EDP_TXP0 E2 AK24 APU_TEST410 SA00004BV00 RPC45
D
DP0_TXP[0] TEST410
[16] EDP_TXP0 T32
EDP_TXN0 E1 DP0_TXN[0] TEST411 AL24 APU_TEST411 8
PANEL_BKLEN_EC 1
[16] EDP_TXN0 T33
eDP TEST4 P24 APU_TEST4 RC59 2 1 0_0402_5% ENVDD_R 7 2
T34
EDP_TXP1 E3 DP0_TXP[1] TEST5 N24 APU_TEST5 @ RPC30 @ 6 3
[16] EDP_TXP1 T35
EDP_TXN1 E4 DP0_TXN[1] TEST6 AN24 APU_TEST6 APU_TEST14 8 1 5 4
[16] EDP_TXN1 T36
r
TEST9 AB8 APU_TEST9 APU_TEST16 7 2
T38
D1 DP0_TXP[2] TEST10 Y9 APU_TEST10 APU_TEST17 6 3 reserve 0 ohm 11/24 100K_0804_8P4R_5%
2 T39 2
D2 DP0_TXN[2] TEST14 B10 APU_TEST14 APU_TEST11 5 4
D11 APU_TEST15
2014/08/12 Modify
o
TEST15
T40 +1.8VS
C1 DP0_TXP[3] TEST16 A10 APU_TEST16 1K_0804_8P4R_5%
+1.8VS B1 DP0_TXN[3] TEST17 C11 APU_TEST17
f
TEST11 B11 APU_TEST11
5
RC6731 2 0_0402_5% APU_SVT_R C15 SVT0 TEST18 A14 APU_TEST18 UC65
1 2 [48] APU_SVT
@ APU_SVT RC6691 2 0_0402_5% APU_SVC_R D17 SVC0 TEST19 B14 APU_TEST19 1
P
[48] APU_SVC NC
RC2 RC6701 2 0_0402_5% APU_SVD_R D19 SVD0 4
l
[48] APU_SVD INVTPWM_R 2 Y INVTPWM [16]
1K_0402_5%
A
G
1 @ 2 APU_SVC RC6821 BR@ 2 0_0402_5% GFX_SVT_R B15 SVT1 TEST28_H A13 APU_TEST28_H
[49] GFX_SVT T43
RC9 RC6751 BR@ 2 0_0402_5% GFX_SVC_R B16 SVC1 TEST28_L B13 APU_TEST28_L
T42 NL17SZ07DFT2G_SC70-5
[49] GFX_SVC
3
a
1K_0402_5% RC6811 BR@ 2 0_0402_5% GFX_SVD_R A18 SVD1 TEST31 P26 APU_TEST31
T41 SA00004BV00
1 2 [49] GFX_SVD E11
@ APU_SVD DP_STEREOSYNC/TEST36 APU_TEST36
i
RC10 APU_SIC B18 SIC TEST37 A17 APU_TEST37
1K_0402_5% APU_SID C17 SID add test point 10/16 RC58 2 1 0_0402_5% change to pu up11/19
t
T47 @
+1.8VS [9] APU_RST#
+1.8VS RC80 1 2 300_0402_5% APU_RST# D15 RESET_L
+1.8VS RC81 1 2 300_0402_5% APU_PWRGD C19 PWROK reserve 0 ohm 11/24
n
1 2 GFX_SVT [9,48,49] APU_PWRGD A15 APU_COREGFX_SEN_H [49]
@ PROCHOT_L
[9,27,41,42,48,49] H_PROCHOT# APU_ALERT# B17 APU_TEST36 1 2
RC13 ALERT_L
T44 +1.8VS
+1.8VS
r
1K_0402_5% VDDCR_GFX_SENSE H11 APU_COREGFX_SEN_H RC155
1 @ 2 GFX_SVC APU_TDI H15 TDI VDDCR_NB_SENSEJ12 1K_0402_5%
H14 APU_VDDNB_SEN [48]
RC14 APU_TDO TDO VDDCR_CPU_SENSEG12 APU_TEST37 1 @ 2
APU_TCK D13 AY18 APU_VDD_SEN [48]
1K_0402_5% TCK VDDP_SENSE
VDDP_SENSE RC117
id
1 @ 2 GFX_SVD +1.8VS APU_TMS G15 TMS 1K_0402_5%
T46
RC15 APU_TRST# J14 TRST_L VSS_SENSE H12 1 @ 2 1 2
C13 APU_VDD_RUN_FB_L [48]
1K_0402_5% APU_DBRDY DBRDY RC118 RC154
APU_DBREQ# A11 DBREQ_L 1K_0402_5% 1K_0402_5%
5
1 2
f
@ @
+1.8VS APU_COREGFX_SEN_L [49]
RC20 0_0402_5%
G
RPC25 EC_SMB_CK2 3 4 APU_SIC

[27,28,34] EC_SMB_CK2
HDT+
D
3 8 1 APU_SID QC79A FP4 REV 0.93 3

2
n
7 2 APU_ALERT# DMN63D8LDW_SOT363-6 FP4_BGA968
6 3 APU_SIC APU_TRST#_R
G
5 4 EC_SMB_DA2 6 1 APU_SID
[27,28,34] EC_SMB_DA2
D
CH1
QC79B 1
o
1K_0804_8P4R_5% DMN63D8LDW_SOT363-6 +1.8VS
HDT@ HDT debug + HDT@
0.01U_0402_16V7K
del cz@ 10/15
c
+3VS 2
change to 0.01u 10/19

JHDT1 CONN@
l
1 2 APU_TCK
1 2 +1.8VS
RC16 1 @ 2 1K_0402_5% EC_SMB_CK2 3 4 APU_TMS RPH1
3 4
a
RC17 1 @ 2 1K_0402_5% EC_SMB_DA2 APU_TCK 1 8
5 6 APU_TDI APU_TMS 2 7
PU at EC side 5 6 APU_TDI 3 6
7 8 APU_TDO APU_DBREQ# 4 5
p
HDT@ 7 8 HDT@
follow esd require 11/27 APU_TRST# 1 2 APU_TRST#_R 9 10 APU_PWRGD_BUF1 DH1 2 APU_PWRGD 1K_0804_8P4R_5%
RH21 33_0402_5% 9 10 DB2J31400L_SOD323-2 HDT@
RH22 1 2 11 12 APU_RST#_BUF 1 DH2 2 APU_RST# +1.8VS
+1.8VS @ESD@ HDT@ 10K_0402_5% 11 12 DB2J31400L_SOD323-2 RPH2
2 1 APU_RST# RH23 1 2 13 14 APU_DBRDY 1 8
m
HDT@
1 2 H_PROCHOT# CC51 0.1U_0402_16V7K HDT@ 10K_0402_5% 13 14 APU_TRST# 2 7
RC159 @ESD@ RH24 1 2 15 16 APU_DBREQ#_R 1 HDT@ 2 APU_DBREQ# APU_TEST19 3 6
1K_0402_5% 2 1 APU_PWRGD HDT@ 10K_0402_5% 15 16 RH25 33_0402_5% APU_TEST18 4 5
co
CC50 0.1U_0402_16V7K 17 18 APU_TEST19
17 18 1K_0804_8P4R_5%
19 20 APU_TEST18 HDT@
19 20
4 APU_TRST# 1 2 4
SAMTE_ASP-136446-07-B @ CH2
0.01U_0402_16V7K

FP4 DISP/MISC/HDT
Custom A00
A B C D E
A B C D E
Main Func = CPU VBIOS VBIOS_ID3 VBIOS_ID2 VBIOS_ID1 +3VS
(PCBA VRAM Size Config.) (AGPIO102) (AGPIO64) (AGPIO66)
2
change to reserve 12/17
2G GDDR5 0 0 0 RC693 DIS@
@ 4G GDDR5 0 0 1 10K_0402_5%
RC1 100K_0402_5%
2G DDR3 0 1 0 UMA: LOW
1
2 1
SKU_ID
DIS: HIGH
1 2
UC1D
Reserved 0 1 1
2
CC615 150P_0402_50V8J
Vinafix.com
y
OUTPUT ACPI/SD/AZ/GPIO/RTC/I2C/UART/MISC RC692 UMA@
RC602 1 2 33_0402_5% LPC_RST_A# BB12 LPC_RST_L SD0_WP/EGPIO101 BB2 KB_DET# KB_DET# [24]
BIOS ingore this table on DVT1 10K_0402_5%
[19,20,27] PLT_RST#
l
RC907 1 2 33_0402_5% APU_PCIE_RST#_R AN7 PCIE_RST_L/EGPIO26 SD0_PWR_CTRL/AGPIO102 BB5 VBIOS_ID3
OUTPUT SD0_CD/AGPIO25 BC2 AGPIO25 RC661 1 @ 2 0_0402_5%
H_PROCHOT# [8,27,41,42,48,49]
1
APU_PCIE_RST#_C 1 2 EC_RSMRST#_R AE4 RSMRST_L SD0_CLK/EGPIO95 BB4 +3VS
1 T51 1
CC912 150P_0402_50V8J SD0_CMD/EGPIO96 AY5 T75
add test point 12/8
n
RC51 2 @ 1 0_0402_5% +3VALW AE1 10 kΩ (± 5%)/+3VALW
PWR_BTN_L/AGPIO0 del ODD_EN# 12/7
VGATE [27,48,49] [27] PBTN_OUT# BC9
APU_FCH_PWRGD_R PWR_GOOD +3VALW/+1.8VALW SD no used can NC
APU_FCH_PWRGD 1 @ 2 SYS_RESET_L AF2 +3VALW
SYS_RESET_L/AGPIO1
APU_FCH_POK [27]
2
RC52 0_0402_5% APU_PCIE_WAKE# 2 @ 1 APU_PCIE_WAKE#_R AG2 WAKE_L/AGPIO2 SD0_DATA0/EGPIO97 BC3 RC12 1 @ 2 0_0402_5% TP_I2C_INT#_APU
[19,27] APU_PCIE_WAKE# BA3
INPUT
o
RC667 0_0402_5% SD0_DATA1/EGPIO98 T48 RC712 @ @
2
@ESD@ change to short pad 03/11 AK7 SLP_S3_L SD0_DATA2/EGPIO99 BC5 T49 10K_0402_5% @
[27] PM_SLP_S3#
2
CC23 100P_0402_50V8J OUTPUT AH5 SLP_S5_L SD0_DATA3/EGPIO100 BA5 T50
add test point 10/19 RC708
2 1 [27,42] PM_SLP_S5# BB6
APU_FCH_PWRGD OUTPUT SD0_LED/EGPIO93 10K_0402_5% RC710
PXS_PWREN [26,52]
1
S0A3 AE8 S0A3_GPIO/AGPIO10 10K_0402_5%
CH23 close to UC1 I/O S5_MUX_CTRL AH8 S5_MUX_CTRL/EGPIO42 SCL0/I2C2_SCL/EGPIO113 BA15 APU_SCLK0 VBIOS_ID1
[26] S5_MUX_CTRL APU_SCLK0 [13,14] set to SMbus
1
SDA0/I2C2_SDA/EGPIO114 AY17 APU_SDATA0
APU_SDATA0 [13,14]
1
RC40 1 2 15K_0402_5% APU_TEST0 AH6 VBIOS_ID2
L
TEST0
RC41 1 2 15K_0402_5% APU_TEST1 AK8 TEST1/TMS SCL1/I2C3_SCL/AGPIO19 AG5 I2C_CLK_TP
+3VALW_EC +3VALW +3VS I2C_CLK_TP [24]
change +3vs 12/21 RC42 1 2 15K_0402_5% APU_TEST2 AE3 TEST2 SDA1/I2C3_SDA/AGPIO20 AG4 I2C_DAT_TP set to I2C VBIOS_ID3
I2C_DAT_TP [24]
1
2
AY15 As close as possible to UC1D
4.7K_0402_5%
4.7K_0402_5%
+3.3VS [27] KB_RST# ESPI_RESET_L/KBRST_L/AGPIO129
2
@ BC19 2 1 2 1 @ @
L
GA20IN/AGPIO126
RC21 RC350 +3.3VS [27] GATEA20 AD7 LPC_PME_L/AGPIO22 AGPIO3 AL5 MEM_VOLT_SEL High @ESD@ @ESD@ RC711 @ RC707 RC709
VDD_33_S5 [27] EC_SCI# EC_SMI# 2 1 BB13 AL6 leave nc 10/20
@ @ LPC_SMI_L/AGPIO86 AGPIO4 High CC310.1U_0402_16V7K CC320.1U_0402_16V7K 10K_0402_5% 10K_0402_5% 10K_0402_5%
5
UC61 CZ-->S0, CZL->S5 RC666 0_0402_5% AGPIO5 AJ1 AGPIO5 del ODD_DA#_FCH 12/7
2
1
1 del ODD_DETECT# 12/7 AG3 AC_PRES/USB_OC4_L/IR_RX0/AGPIO23 AGPIO6/LDT_RST AJ3 APU_RST#_R RC662 1 @ 2 0_0402_5% APU_RST#
P
VDD_33_S5 APU_RST# [8]
1
NC 4 APU_FCH_PWRGD_R del TS_INT# 12/3 AD5 AH1 APU_PWRGD_R RC663 1 @ 2 0_0402_5% APU_PWRGD
IR_TX0/USB_OC5_L/AGPIO13 AGPIO7/LDT_PWROK
VDD_33_S5 APU_PWRGD [8,48,49]
E
APU_FCH_PWRGD 2 Y del TS_RST# 12/3 AL8 AJ4 AGPIO8 2 @ 1 TP_I2C_INT#_APU
IR_TX1/USB_OC6_L/AGPIO14 AGPIO8
A VDD_33_S5 TP_I2C_INT#_APU [24]
G
AN8 IR_RX1/AGPIO15 AGPIO9 AK5 RC22 0_0402_5%

AE2 AD8 GFX_VR_ON EC_LID_OUT# [27] +3VALW
NL17SZ07DFT2G_SC70-5 IR_LED_L/LLB_L/AGPIO12 VDDGFX_PD/AGPIO39 I/O
VDD_33_S5/OD GFX_VR_ON [49]
3
SA00004BV00 LAN_CLKREQ# BC15 INPUT AG8 GFX_PWRGD_APU 2 @ 1 GFX_VR_ON:

VDD_33_S0 [19] LAN_CLKREQ# CLK_REQ0_L/SATA_IS0_L/SATA_ZP0_L/AGPIO92 AGPIO40 I/O
GFX_PWRGD [27,48,49]
WLAN_CLKREQ# BB17 CLK_REQ1_L/AGPIO115 INPUT AGPIO64 AW15 VBIOS_ID2 RC664 0_0402_5% CZ only DISABLE GFX-->HIGH
1 @ 2
VDD_33_S0 [20] WLAN_CLKREQ# PWRGD_VGA BC17 AU15 SKU_ID AGPIO8 10K_0402_5% 2 1 RC932
VDD_33_S0 [52] PWRGD_VGA CLK_REQ2_L/AGPIO116 INPUT AGPIO65 ENABLE GFX-->LOW
D
RC53 0_0402_5% EGPIO131 BB18 CLK_REQ3_L/SATA_IS1_L/SATA_ZP1_L/EGPIO131 INPUT
VDD_33_S0 2 @ 1 0_0402_5% PEG_CLKREQ#_R BB16 AT15 VBIOS_ID1
2 2 VDD_33_S0 [34] PEG_CLKREQ# CLK_REQG_L/OSCIN/EGPIO132 INPUT AGPIO66/SHUTDOWN_L
CC999 CC1000 change to short pad 03/11 RC56 USB_OC0# AH9 USB_OC0_L/TRST_L/AGPIO16 AGPIO68/SGPIO_CLK AU12 BT_ON# AGPIO5 10K_0402_5% 2 1 RC933
[23] USB_OC0# AG1 AT14 AGPIO69 BT_ON# [20]
VDD_33_S5 [25] USB_OC1# USB_OC1# USB_OC1_L/TDI/AGPIO17 AGPIO69/SGPIO_LOAD
.1U_0402_16V7K .1U_0402_16V7K VDD_33_S5 AH2 USB_OC2_L/TCK/AGPIO18 AGPIO71/SGPIO_DATAOUT AR14 AND Gate, as before
r
1 1 2 1 AL9 BC13 PXS_RST# [33] add ph 12/8
@ USB_OC3_L/TDO/AGPIO24 AGPIO72/SGPIO_DATAIN
[27] EC_SMI# CAM_DETECT# [16] change to CAM_DETECT# 12/03
VDD_33_S5 RC665 0_0402_5%
10 kΩ (± 5%) / VSS HDA_BITCLK AU6 AZ_BITCLK/I2S_BCLK_MIC SPKR/AGPIO91 BA17 +3VS
2 APU_SPKR [18] 2
EMI@ 22–33Ω (± 5%) HDA_SDIN0 AR8 AZ_SDIN0/I2S_DATA_MIC[0]
[18] HDA_SDIN0
o
RPC13 22–33Ω (± 5%) HDA_SDIN1 AP6 AZ_SDIN1/I2S_LR_PLAYBACK BLINK/USB_OC7_L/AGPIO11 AN5 AGPIO11 CC15 @ remove br@ 12/8
1 8 HDA RST HDA_SDIN222–33Ω (± 5%) AR5 AZ_SDIN2/I2S_DATA_MIC[1]
+3VALW 1 2
[18] HDA_RST#_AUDIO 2 7 22–33Ω (± 5%) HDA RST 22–33Ω (± 5%) AU9 BB14 2 1 RC936
HDA_SYNC HVB_FUNCTION AGPIO69 10K_0402_5%
f
AZ_RST_L/I2S_LR_MIC GENINT1_L/AGPIO89
[18] HDA_SYNC_AUDIO 3 6 22–33Ω (± 5%) HDA_SYNC AT9 BA19 2 1 RC938
HDA_SDOUT AZ_SYNC/I2S_BCLK_PLAYBACK GENINT2_L/AGPIO90 0.1U_0402_16V7K PXS_PWREN 10K_0402_5%
[18] HDA_SDOUT_AUDIO 4 5 22–33Ω (± 5%) HDA_SDOUT AR7
HDA_BITCLK AZ_SDOUT/I2S_DATA_PLAYBACK
[18] HDA_BITCLK_AUDIO BC18
FANIN0/AGPIO84
33_0804_8P4R_5% EGPIO145 BB10 I2C0_SCL/EGPIO145 FANOUT0/AGPIO85 BB19
l
EGPIO146 BB9 I2C0_SDA/EGPIO146 change to pop 03/22
1 8 VDD_18 APU_I2C1_SCL BB7 I2C1_SCL/EGPIO147 UART0_CTS_L/EGPIO135 AY9
2 7 VDD_18 APU_I2C1_SDA BC7 I2C1_SDA/EGPIO148 UART0_RXD/EGPIO136 AW8
3 6 UART0_RTS_L/EGPIO137 AV5 UART no used can NC
a
4 5 10 kΩ (± 5%) / VDD_33_S5 RTC_CLK AG7 RTCCLK UART0_TXD/EGPIO138 AV8
UART0_INTR/AGPIO139 AW9
i
RPC14 ADD BR@ 11/16
del touch pad 3.3v ph leave touch side 12/09 32K_X1 AT1 X32K_X1 UART1_CTS_L/BT_I2S_BCLK/EGPIO140 AV11
1K_0804_8P4R_5% AU7
t
UART1_RXD/BT_I2S_SDI/EGPIO141
RPC64 UART1_RTS_L/EGPIO142 AT11 APU_PCIE_RST# 2 1 APU_PCIE_RST#_C
+3VS BR@
8 1 UART1_TXD/BT_I2S_SDO/EGPIO143 AR11 RC30 0_0402_5%
7 2 change net name 32K_X2 AT2 X32K_X2 UART1_INTR/BT_I2S_LRCLK/AGPIO144 AP9
6 3 APU_SCLK0
n
FP4 REV 0.93
5 4 APU_SDATA0 follow esd require 11/27
FP4_BGA968 For PCIE device reset on FS1
2.2K_0804_8P4R_5% +3VALW
r
(GFX,GLAN,WLAN,LVDS Travis)
CC14 @
+1.8VS @ESD@ APU_PCIE_RST #: Reset PCIE device on APU 1 2
2 1 EC_RSMRST#_R
+3VS 1 8 APU_I2C1_SCL CC52 0.1U_0402_16V7K 0.1U_0402_16V7K
id
5
2 7 APU_I2C1_SDA MC74VHC1G08DFT2G SC70 5P
3 6 GATEA20 @ RC25 2
P
4 5 KB_RST# APU_PCIE_RST#_C 1 2 B 4
1 Y APU_PCIE_RST# [19,20,33]
@ESD@ 33_0402_5%
A
G
RPC36 10K_8P4R_5% 2 1 SYS_RESET_L UC4 QCL10 LAN-APU,WLAN&ExCARD-FCH 20110803
8.2K_0402_5%
f
2
CC53 0.1U_0402_16V7K
150P_0402_50V8J
1
1
+1.8VS
CC16
RC26
@ @
RC27
3 RC47 1 @ 2 10K_0402_5% HVB_FUNCTION TP_I2C@ 10/28 @ @ 0_0402_5% 3
n
2
1
+3VS
2
+1.8VS follow AMD review 12/22 @ RC28
RC45 1 @ 2 10K_0402_5% BT_ON# del tp mos 12/01 1 2 PLT_RST#
o
RC50 1 2 10K_0402_5% EGPIO145 0_0402_5%
+3VALW RC55 1 2 10K_0402_5% EGPIO146
del APU_PCIE_WAKE# pull up 11/20
RTC_CLK BLINK/GPIO11 SYS_RST#
c
RC905 1 2 100K_0402_5% USB_OC0# LPC_CLK0_EC LPC_CLK1 LPC_FRAME# MEM_VOLT_SEL
RC906 1 2 100K_0402_5% USB_OC1#
<INT PU> <INT PU> <INT PU>
LDT_RST#/PG
BOOT FAIL CLKGEN SPI ROM Enhanced Reset logic COIN BATT OUTPUT TO NORMAL
+3VALW
H
l
+1.8V_ALW
TIMER ENABLE (DEFAULT) (default) ON BOARD APU RESET MODE
reserve for test1 10/28
RC33 1 @ 2 1K_0402_5% APU_TEST1
ENABLED (DEFAULT) (DEFAULT) (DEFAULT) (DEFAULT)
RC678 1 @ 2 2.2K_0402_5% APU_TEST0
a
RC683 1 @ 2 2.2K_0402_5% APU_TEST2 RSMRST# BOOT FAIL
1.8V /EC program to 1.8V OUTPUT display 47K 01/13 TIMER CLKGEN COIN BATT OUTPUT SHORT RST
L
1
del smbus 1 @ 11/12 DISABLED LPC ROM Traditional Reset logic: NOT ON TO PADS MODE
DISABLED
Check RSMRST delay 10ms RC346
BOARD
(DEFAULT)
p
RC942 1 2 10K_0402_5% PBTN_OUT# 47K_0402_5%
RC943 1 @ 2 100K_0402_5% EC_LID_OUT# del ph 11/24
RC944 1 PTP@ 2 10K_0402_5% S0A3 +3VS +3VALW
2
follow check list 11/11 EC_RSMRST# 1 2 EC_RSMRST#_R

[27] EC_RSMRST#
1
RC697 1 2 10K_0402_5% EGPIO131 DC3
RC694 1 NPTP@ 2 10K_0402_5% S0A3 DB2J31400L SOD323-2 @
RC695 1 2 10K_0402_5% HDA_SDIN1 RC902 RC904 RC925 RC928 RC949 RC951 RC954
m
RC49 1 @ 2 10K_0402_5% HVB_FUNCTION reserve 10K for hda sdin0 and bitclk 10/19 RB751 Max Vf=0.37V 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
RC696 1 2 10K_0402_5% HDA_SDIN2
2
RC703 1 @ 2 10K_0402_5% HDA_SDIN0
[10,27] LPC_FRAME#
RC706 1 @ 2 10K_0402_5% HDA_BITCLK
co
[10,27] LPC_CLK0_EC
[10] LPC_CLK1
MEM_VOLT_SEL
RTC_CLK
32.768KHz CRYSTAL SYS_RESET_L
AGPIO11
4 32K_X1 4
1
1
1
@ @ @ @ @ @
SJ100001K00 YC3 delete APU_RST#_EC/APU_PWRGD_EC reserve compoent 3/24 RC903 RC926 CC30 RC927 RC929 RC950 RC952 RC953
32.768KHZ_12.5PF_CM31532768DZFT 2K_0402_5% 2K_0402_5% 22P_0402_50V8J 2K_0402_5% 2K_0402_5% 2K_0402_5% 2.2K_0402_5% 2.2K_0402_5%
2
@EMI@
2
2
2 1 32K_X2
RC914
20M_0402_5% follow DG change to 2K reserve 10/13
1 1
change 22P to 18P 06/06
CC686 CC682 Security Classification Compal Secret Data Compal Electronics, Inc.
18P_0402_50V8J 18P_0402_50V8J 2016/01/07 2017/01/07 Title
2 2 Issued Date Deciphered Date
FP4 GPIO/AZ/MISC/STRAPS
Custom A00
A B C D E
A B C D E
Main Func = CPU

UC1E
CLK/SATA/USB/SPI/LPC
AU3 SATA_TX0P USBCLK/25M_48M_OSCAP8
[22] SATA_ATX_DRX_P0 AU4 SATA_TX0N
[22] SATA_ATX_DRX_N0 AP5 USB_ZVSS
USB_ZVSS RC6411 2 11.8K_0402_1%
HDD AV1 SATA_RX0N
[22] SATA_ARX_DTX_N0 AV2 AR2 USB20_CR_P0
SATA_RX0P USB_HSD0P
Vinafix.com
y
[22] SATA_ARX_DTX_P0 AR1 USB20_CR_N0 USB20_CR_P0 [25]
USB_HSD0N
USB20_CR_N0 [25] Card Reader
AY2 SATA_TX1P
l
[22] SATA_ATX_DRX_P1 AY1 AR3 USB20_TOUCH_P1
SATA_TX1N USB_HSD1P
[22] SATA_ATX_DRX_N1 AR4 USB20_TOUCH_P1 [16]
ODD USB_HSD1N USB20_TOUCH_N1 Touch screen panel
1 AW4 USB20_TOUCH_N1 [16] 1
SATA_RX1N
[22] SATA_ARX_DTX_N1 AW3 AN2 USB20_CAM_P2
n
SATA_RX1P USB_HSD2P
[22] SATA_ARX_DTX_P1 AN1 USB20_CAM_N2 USB20_CAM_P2 [16]
USB_HSD2N
USB20_CAM_N2 [16] Camera
RC90 2 1 1K_0402_1% SATA_ZVSS AW1 SATA_ZVSS
+0.95VS RC96 2 1 1K_0402_1% SATA_ZVDD AW2 SATA_ZVDDP USB_HSD3P AN3 USB20_JUSB1_P3

USB20_JUSB1_P3 [25]
o
DEVSLP0_HDD AT17 DEVSLP[0]/EGPIO67 USB_HSD3N AN4 USB20_JUSB1_N3 USB Conn IO PORT3
[22] DEVSLP0_HDD WL_OFF# AT12 USB20_JUSB1_N3 [25]
DEVSLP[1]/EGPIO70
[20] WL_OFF# SATA_ACT# BB15 AM1 USB20_MINI1_P4
SATA_ACT_L/AGPIO130 USB_HSD4P
[27,29] SATA_ACT# AM2 USB20_MINI1_N4 USB20_MINI1_P4 [20]
USB_HSD4N
USB20_MINI1_N4 [20] Mini Card (WLAN)
AU2 SATA_X1
change to @ 11/12 USB_HSD5P AL2 USB20_JUSB1_P5
1 2 DEVSLP0_HDD AL1 USB20_JUSB1_N5 USB20_JUSB1_P5 [23]
@ USB Conn MB PORT1
L
USB_HSD5N
+3VS USB20_JUSB1_N5 [23]
10K_0402_5%1 @ 2 RC44 WL_OFF#
10K_0402_5%1 2 RC46 SATA_ACT# AU1 SATA_X2 USB_HSD6P AL3 USB20_JUSB2_P6
delete 0 ohm 11/27 AL4 USB20_JUSB2_N6 USB20_JUSB2_P6 [23]
10K_0402_5% RC43 USB_HSD6N
USB20_JUSB2_N6 [23] USB Conn MB PORT2
L
CLK_PEG_VGA U4 GFX_CLKP USB_HSD7P AK2
[33] CLK_PEG_VGA CLK_PEG_VGA# U3 AJ2
VGA [33] CLK_PEG_VGA# GFX_CLKN USB_HSD7N
CLK_PCIE_LAN U1 GPP_CLK0P
[19] CLK_PCIE_LAN
CLK_PCIE_LAN# U2
E
LAN [19] CLK_PCIE_LAN# GPP_CLK0N
CLK_PCIE_WLAN W4 GPP_CLK1P
[20] CLK_PCIE_WLAN CLK_PCIE_WLAN#W3
WLAN [20] CLK_PCIE_WLAN# GPP_CLK1N
W1
D
GPP_CLK2P
W2 GPP_CLK2N
Y2 GPP_CLK3P
Y1 GPP_CLK3N
r
BC10 X25M_48M_OSC
2 AD2 USBSS_ZVSS RC6441 2 1K_0402_1% 2
USB_SS_ZVSS
AD1 USBSS_ZVDD RC6451 2 1K_0402_1%
o
USB_SS_ZVDDP
+0.95VALW
48M_X1 T2 X48M_X1
USB_SS_0TXP AA3
f
USB_SS_0TXN AA4
48M_X2 T1 X48M_X2 USB_SS_0RXP W9

USB_SS_0RXN W8
l
RC4491 2 33_0402_5% AW14 LPCCLK0/EGPIO74 USB_SS_1TXP AA2 USB3TP1_JUSB1
[9,27] LPC_CLK0_EC USB3TP1_JUSB1 [23]
RC4501 EMI@ 2 33_0402_5% AY13 LPCCLK1/EGPIO75 USB_SS_1TXN AA1 USB3TN1_JUSB1
[9] LPC_CLK1 USB3TN1_JUSB1 [23]
a
USB Conn PORT1
BB11 LAD0 USB_SS_1RXP W5 USB3RP1_JUSB1
[27] LPC_AD0 USB3RP1_JUSB1 [23]
i
BA11 LAD1 USB_SS_1RXN W6 USB3RN1_JUSB1
[27] LPC_AD1 AY11 USB3RN1_JUSB1 [23]
[27] LPC_AD2 LAD2
usb 3.0
t
BA13 LAD3 USB_SS_2TXP AC1 USB3TP2_JUSB2
[27] LPC_AD3 AV14 AC2 USB3TP2_JUSB2 [23]
LFRAME_L USB_SS_2TXN USB3TN2_JUSB2
[9,27] LPC_FRAME# BA1 USB3TN2_JUSB2 [23]
ESPI_ALERT_L/LDRQ0_L USB Conn PORT2
BC14 SERIRQ/AGPIO87 USB_SS_2RXP Y6 USB3RP2_JUSB2
n
[27] SERIRQ BC11 USB3RP2_JUSB2 [23]
RC643 10K_0402_5% LPC_CLKRUN_L/AGPIO88 USB_SS_2RXN Y7 USB3RN2_JUSB2
change to pu down 12/17 2 1 AGPIO21 AE9 USB3RN2_JUSB2 [23]
LPC_PD_L/AGPIO21
r
USB_SS_3TXP AC4
emc request 11/26 RC106 33_0402_5% USB_SS_3TXN AC3
APU_SPI_CLK 1 EMI@ 2 APU_SPI_CLK_R BC6 SPI_CLK/ESPI_CLK/EGPIO117
APU_SPI_CS1# BB8 SPI_CS1_L/EGPIO118 USB_SS_3RXP AB5
id
del share rom resistor 11/18 APU_SPI_CS1#_R AW7 SPI_CS2_L/ESPI_CS_L/EGPIO119 USB_SS_3RXN AB6
APU_SPI_MISO BA9 SPI_DI/ESPI_DATA/EGPIO120
APU_SPI_MOSI AY7 SPI_DO/EGPIO121
APU_SPI_WP# AW11 SPI_WP_L/EGPIO122
APU_SPI_HOLD# BA7
f
SPI_HOLD_L/EGPIO133
APU_SPI_TPMCS# AW12 SPI_TPM_CS_L/AGPIO76
EMI@
3 APU_SPI_CLK C27 1 2 FP4 REV 0.93
48MHz CRYSTAL 3
n
10P_0402_50V8J FP4_BGA968
7/25 Add, EMI request
48M_X2
o
+1.8VS 1 RC939 2 48M_X1
RC48
1M_0402_5%
2 1 APU_SPI_CS1#_R
c
2 1
10K_0402_5% 2 1
T52
a l +1.8VS
+1.8V_ALW
add test point 10/20 YC2
48MHZ_8PF_X3S048000D81H-W
Part Number = SJ10000AF00
p
@ 3 4
RC1672 1 2 0_0603_5% JH1 CONN@ 3 4
1 1
1 @ 2 APU_SPI_CS1# 1 8 +SPI_VCC
2 1 APU_SPI_TPMCS# RC1675 0_0402_5% APU_SPI_WP# 3 CS# VCC 6 APU_SPI_CLK C796 C797
RC646 APU_SPI_HOLD# 7 WP# SCLK 5 APU_SPI_MOSI 5.6P_0402_50V8D 5.6P_0402_50V8D
8MB SPI ROM 4 HOLD# SI/SIO0 2 APU_SPI_MISO 2 2
m
10K_0402_5%
2 1 GND SO/SIO1
CC635 @ ACES_91960-0084N_MX25L3206EM2I
.1U_0402_16V7K
co
UC5
APU_SPI_CS1# 1 8 +SPI_VCC
APU_SPI_MISO 2 CS# VCC 7 APU_SPI_HOLD#
APU_SPI_WP# 3 DO(IO1) HOLD#(IO3) 6 APU_SPI_CLK
4 +SPI_VCC 4 WP#(IO2) CLK 5 APU_SPI_MOSI 4
GND DI(IO0)
2 1 APU_SPI_HOLD# W25Q64FWSSIQ_SO8
RC642 10K_0402_5% APU_SPI_CLK 1 2 1 2
2 1 APU_SPI_WP# RC617 @EMI@ C636 @EMI@
RC640 10K_0402_5% 10_0402_5% 10P_0402_50V8J
2 1 APU_SPI_CS1#
RC639 10K_0402_5%
FP4 SATA/CLK/USB/SPI
Custom A00
A B C D E
A B C D E
Main Func = CPU
+1.2V_DDR
Vinafix.com
y
CC1008
CC1057
CC1058
CC1059
CC1060
CC1061
CC1062
CC1063
CC1064
CC1065
CC1066
CC1087
CC1088
CC1089
CC1090
CC1091
CC1092
CC1093
l
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
@ @ @
1 UC1F 1
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
180P_0402_50V8J
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
n
POWER
+1.2V_DDR P25 VDDIO_MEM_S3_1 VDDCR_CPU_1 U8 +APU_CORE +APU_CORE

P28 W7
3A VDDIO_MEM_S3_2 VDDCR_CPU_2
35A
CC1052
CC1128
CC1127
CC1125
CC1123
CC1122
CC1121
CC1120
CC1117
CC1068
CC1009
CC1010
CC1011
CC1015
CC1016
CC1053
CC1054
CC1055
T24 VDDIO_MEM_S3_3 VDDCR_CPU_3 W12
T27 VDDIO_MEM_S3_4 VDDCR_CPU_4 W15 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
o
U25 VDDIO_MEM_S3_5 VDDCR_CPU_5 W18
U28 VDDIO_MEM_S3_6 VDDCR_CPU_6 W21
180P_0402_50V8J
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
V30 VDDIO_MEM_S3_7 VDDCR_CPU_7 Y8
V33 Y10 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Under APU W24
VDDIO_MEM_S3_8
VDDIO_MEM_S3_9
VDDCR_CPU_8
VDDCR_CPU_9 Y13
W27 VDDIO_MEM_S3_10 VDDCR_CPU_10 Y16
+1.2V_DDR Y25 VDDIO_MEM_S3_11 VDDCR_CPU_11 Y19
L
Y28 VDDIO_MEM_S3_12 VDDCR_CPU_12 Y22
CC1111
CC1112
CC1113
CC1114
CC1115
CC1116
Y30 VDDIO_MEM_S3_13 VDDCR_CPU_13 AB7
1 1 1 1 1 1 AB24 VDDIO_MEM_S3_14 VDDCR_CPU_14 AB9
AB27 VDDIO_MEM_S3_15 VDDCR_CPU_15 AB12
AB30 VDDIO_MEM_S3_16 VDDCR_CPU_16 AB15
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
180P_0402_50V8J
180P_0402_50V8J
AB33 AB18
L
VDDIO_MEM_S3_17 VDDCR_CPU_17
2 2 2 2 2 2 AD25 VDDIO_MEM_S3_18 VDDCR_CPU_18 AB21
AD28 VDDIO_MEM_S3_19 VDDCR_CPU_19 AD6
BR@
BR@
BR@
BR@
BR@
BR@
BR@
BR@
BR@
BR@
BR@
BR@
BR@
BR@
BR@
BR@
BR@
BR@
BR@
AD30 VDDIO_MEM_S3_20 VDDCR_CPU_20 AD10
AE24 VDDIO_MEM_S3_21 VDDCR_CPU_21 AD13
AE27 AD16
E
VDDIO_MEM_S3_22 VDDCR_CPU_22 +APU_CORE_GFX
AF30 VDDIO_MEM_S3_23 VDDCR_CPU_23 AD19
CC1056 180P_0402_50V8J
CC1149 0.22U_0402_10V6K
CC1138 0.22U_0402_10V6K
CC1136 0.22U_0402_10V6K
CC1135 0.22U_0402_10V6K
CC1134 0.22U_0402_10V6K
CC1133 0.22U_0402_10V6K
CC1132 0.22U_0402_10V6K
CC1131 0.22U_0402_10V6K
CC1130 0.22U_0402_10V6K
CC1077 22U_0603_6.3V6M
CC1069 22U_0603_6.3V6M
CC1070 22U_0603_6.3V6M
CC1071 22U_0603_6.3V6M
CC1072 22U_0603_6.3V6M
CC1073 22U_0603_6.3V6M
CC1074 22U_0603_6.3V6M
CC1075 22U_0603_6.3V6M
CC1076 22U_0603_6.3V6M
AF33 VDDIO_MEM_S3_24 VDDCR_CPU_24 AD22
AG25 AE7
DIMMS/GND AG28
VDDIO_MEM_S3_25
VDDIO_MEM_S3_26
VDDCR_CPU_25
VDDCR_CPU_26 AE12
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
AH24 VDDIO_MEM_S3_27 VDDCR_CPU_42 AK9
@ AH27 VDDIO_MEM_S3_28 VDDCR_CPU_31 AG10
D
RC11 1 2 0_0402_5% VDDIO_AUDIO AH30 VDDIO_MEM_S3_29 VDDCR_CPU_43 AK10 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
+1.5VS
change to shortpad 03/10 AK25 VDDIO_MEM_S3_30 VDDCR_CPU_32 AG13
1 @ 2 0_0402_5% AK28 AK13
FOR DEBUG ONLY +1.8VS
RC18 AK30
VDDIO_MEM_S3_31
VDDIO_MEM_S3_32
VDDCR_CPU_44
VDDCR_CPU_33 AG16
AK33 VDDIO_MEM_S3_33 VDDCR_CPU_45 AK16
r
1 @ 2 AL27 VDDIO_MEM_S3_34 VDDCR_CPU_34 AG19
+3VS +3VS_APU +1.8VS +1.5VS
AM30 VDDIO_MEM_S3_35 VDDCR_CPU_46 AK19
CC1137
CC1100
CC1101
CC1102
2 RC119 0_0402_5% CC1005 1U_0402_6.3V6K

VDDCR_CPU_35 AG22 2
CC1006 1U_0402_6.3V6K
CC1007 1U_0402_6.3V6K
1 1 1 1 VDDIO_AUDIO AR19 VDDIO_AUDIO VDDCR_CPU_47 AK22
o
AH7
@
1 1 1 0.2A AE6 VDDP_GFX_2
VDDCR_CPU_36
VDDCR_CPU_28 AE18
+0.95VS +APU_CORE_NB
10U_0603_6.3V6M
22U_0603_6.3V6M
10U_0603_6.3V6M
0.22U_0402_10V6K
AE5 AE21
1.4A VDDP_GFX_1 VDDCR_CPU_29
f
2 2 2 2
CC1067
CC1146
CC1145
CC1144
CC1143
CC1142
CC1141
CC1140
CC1139
CC1095
CC1096
CC1097
CC1098
VDDCR_CPU_40 AH21
change to @ 10/20 change to pop 10/20 2 2 2 AP19 AG6
+3VS_APU VDD_33_1 VDDCR_CPU_30 1 1 1 1 1 1 1 1 1 1 1 1 1
AP21 AH12
0.2A VDD_33_2 VDDCR_CPU_37
VDDCR_CPU_49 AN6
180P_0402_50V8J
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
AP16 AH15
l
+1.8VS VDD_18_1 VDDCR_CPU_38
AP18 AH18 2 2 2 2 2 2 2 2 2 2 2 2 2
1.5A VDD_18_2 VDDCR_CPU_39
VDDCR_CPU_48 AL7
+1.8V_ALW AP10 VDD_18_S5_1 VDDCR_CPU_41 AK6
a
AR9 AE15
0.5A VDD_18_S5_2 VDDCR_CPU_27
AP15
i
+3VALW VDD_33_S5_1
AR15 L8
+3VALW +1.8V_ALW +VDDCR_FCH_ALW 0.2A VDD_33_S5_2 VDDCR_GFX_14
L13
+APU_CORE_GFX
VDDCR_GFX_15
35A
t
CC1124 10U_0603_6.3V6M
CC1126 0.22U_0402_10V6K
CC1085 10U_0603_6.3V6M
CC1086 0.22U_0402_10V6K
CC1108 10U_0603_6.3V6M
CC1109 10U_0603_6.3V6M
CC1110 0.22U_0402_10V6K
AN12 VDDP_S5_1 VDDCR_GFX_16 L16

+0.95VALW
AP12 L19
1 1 1 1 1 1 1 0.8A VDDP_S5_2 VDDCR_GFX_17
VDDCR_GFX_18 L22
Under APU
AP13 VDDCR_FCH_S5_1 VDDCR_GFX_19 N7
n
+VDDCR_FCH_ALW AR12 VDDCR_FCH_S5_2 VDDCR_GFX_20 N12
2 2 2 2 2 2 2 N15
0.2A AW19 VDDP_6
VDDCR_GFX_21
VDDCR_GFX_22 N18
+0.95VS
r
AU17 N21
7A AU19
VDDP_1
VDDP_2
VDDCR_GFX_23
VDDCR_GFX_24 P8
+APU_CORE_NB
CC1084
CC1082
CC1081
CC1079
CC1078
AV17 VDDP_3 VDDCR_GFX_25 P13
AV19 VDDP_4 VDDCR_GFX_26 P16 1 1 1 1 1
id
AW17 VDDP_5 VDDCR_GFX_27 P19
VDDCR_GFX_28 P22
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
AL12 VDDCR_NB_1 VDDCR_GFX_29 T7
+APU_CORE_NB 2 2 2 2 2
AL13 VDDCR_NB_2 VDDCR_GFX_1 F12
AL15 F15
+0.95VALW/+0.95VS OF APU ST :21A AL18
VDDCR_NB_3 VDDCR_GFX_2
G11
+VDDP_VS
f
AL21 G14
BR :17A AN13
J8
VDD_095 VDD_095_GFX AN16
VDDCR_NB_6
VDDCR_NB_7
VDDCR_GFX_5
VDDCR_GFX_6 J9
3 +0.95VS +0.95VS 3
AN19 J11
+VDDP_ALW
n
AN22 VDDCR_NB_9 VDDCR_GFX_8 K7
K12
+0.95VALW VDDCR_GFX_9
VDDCR_GFX_10 K13
ACROSS VDDNB AND VSS SPLIT
CC935
CC934
CC951
CC203
CC1118
CC1119
+RTC_APU_R +RTC_APU_R AR17 VDDBT_RTC_G VDDCR_GFX_11 K15
o
1 1 1 1 1 1 VDDCR_GFX_12 K16
CC1129
T12
del LC22 3/24 1
VDDCR_GFX_30
VDDCR_GFX_31 T15 OPEN
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K
10U_0603_6.3V6M
0.22U_0402_10V6K
VDDCR_GFX_32 T18
c
2 2 2 2 2 2 JP14
@ VDDCR_GFX_33 T21
0.22U_0402_10V6K
VDDCR_GFX_34 U13 2 1
2 VDDCR_GFX_35 U16 +RTCVCC 2 1
VDDCR_GFX_36 U19 JUMP_43X39
l
change to @ 06/15 VDDCR_GFX_37 U22
VDDCR_GFX_13 K19
JP12
FP4 REV 0.93 2 1
+CHGRTC 2 1 +3VLP
a
FP4_BGA968
JUMP_43X39
+0.95VS
BR@ BR@ +0.95VS
SHORT
CC949
CC950
CC1080
CC1083
CC1107
CC245
CC1104
CC1105
CC1106
CC1151
CC1150
p
CC1147
CC1148
1 1 1 1 1 1 1 1 1 1 1
1 1
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
0.22U_0402_10V6K
180P_0402_50V8J
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
2 2 2 2 2 2 2 2 2 2 2 +RTC_APU +RTCVCC
10U_0603_6.3V6M
0.22U_0402_10V6K
2 2
Vo=1.5V
m
DC3803
+RTC_APU 3 3 1 2 +RTCBATT
Vout 1 1 anode RC31 1K_0402_5%
2 Vin cathode 2
W=20mils GND anode
+CHGRTC
co
+RTC_APU_R RC93 1 2 1K_0402_5%
Under APU 1 1
RTC OF APU 1 1 Need OPEN CC119
UC101
CC120
BAS40C_SOT23-3
0.1U_0603_25V7K AP2138N-1.5TRG1_SOT23-3 680P_0603_50V8J
Close AE6, AE5
1
CC166 CC923 @ for Clear CMOS 2 2

4 0.22U_0402_10V6K 1U_0402_6.3V6K CLRP1 4
add 0.22u*5 11/13 2 2 SHORT PADS
2
JRTC1
1
1 2 +RTCBATT
2
3
GND 4
GND
ACES_50271-0020N-001
CONN@
change symbol 11/13 Security Classification Compal Secret Data Compal Electronics, Inc.
SP02000RO00
FP4 PWR
C A00
A B C D E
5 4 3 2 1
Main Func = CPU

UC1G UC1H
UC1J
GND GND
A8 VSS_1 VSS_63 L28 AE10 VSS_125 VSS_187 AV30
A12 VSS_2 VSS_64 M4 AE13 VSS_126 VSS_188 AV33 U30 RSVD_2
T173
A16 VSS_3 VSS_65 M30 AE16 VSS_127 VSS_189 AW22 U31 RSVD_3
T12
A20 VSS_4 VSS_66 N10 AE19 VSS_128 VSS_190 AY4 AN30 RSVD_4
T13
A24 VSS_5 VSS_67 N13 AE22 VSS_129 VSS_191 AY6
A28 VSS_6 VSS_68 N16 AF1 VSS_130 VSS_192 AY8
Vinafix.com
y
A32 VSS_7 VSS_69 N19 AF4 VSS_131 VSS_193 AY10
B2 VSS_8 VSS_70 N22 AG9 VSS_132 VSS_194 AY12
l
B8 VSS_9 VSS_71 N27 AG12 VSS_133 VSS_195 AY14
B12 VSS_10 VSS_72 P1 AG15 VSS_134 VSS_196 AY16
D B33 VSS_11 VSS_73 P2 AG18 VSS_135 VSS_197 AY20 D
C3 P4 AG21 AY22 FP4 REV 0.93
n
VSS_12 VSS_74 VSS_136 VSS_198
D4 VSS_13 VSS_75 P5 AH4 VSS_137 VSS_199 AY24
D6 VSS_14 VSS_76 P12 AH10 VSS_138 VSS_200 AY26 FP4_BGA968
o
D12 VSS_17 VSS_79 P21 AH19 VSS_141 VSS_203 BB1
D14 VSS_18 VSS_80 P30 AH22 VSS_142 VSS_204 BB33
D16 VSS_19 VSS_81 P33 AK1 VSS_143 VSS_205 BC4
D18 VSS_20 VSS_82 T4 AK4 VSS_144 VSS_206 BC8
D22 T13 AK15 BC16
L
VSS_22 VSS_84 VSS_146 VSS_208
D26 VSS_24 VSS_86 T19 AL16 VSS_148 VSS_210 BC24
L
F1 VSS_27 VSS_89 U5 AM4 VSS_151
F2 VSS_28 VSS_90 U12 AN9 VSS_152
F4 VSS_29 VSS_91 U15 AN10 VSS_153
F9 VSS_30 VSS_92 U18 AN15 VSS_154
F19 U21 AN18
E
VSS_31 VSS_93 VSS_155
F22 VSS_32 VSS_94 U24 AN21 VSS_156
F25 VSS_33 VSS_95 V1 AN25 VSS_157
F30 VSS_34 VSS_96 V2 AN28 VSS_158
F33 VSS_35 VSS_97 V4 AP1 VSS_159
G7 W10 AP2
D
G17 VSS_37 VSS_99 W13 AP4 VSS_161
G20 VSS_38 VSS_100 W16 AP7 VSS_162
G23 VSS_39 VSS_101 W19 AP22 VSS_163
G26 VSS_40 VSS_102 W22 AP27 VSS_164
r
H4 VSS_41 VSS_103 Y4 AP30 VSS_165
H30 VSS_42 VSS_104 Y5 AP33 VSS_166
C J5 Y12 AR6 C
J15 Y15 AR25
o
J19 VSS_45 VSS_107 Y18 AR28 VSS_169
J22 VSS_46 VSS_108 Y21 AT4 VSS_170
f
J25 VSS_47 VSS_109 Y24 AT19 VSS_171
J28 VSS_48 VSS_110 AB1 AT22 VSS_172
K1 VSS_49 VSS_111 AB2 AT30 VSS_173
K2 VSS_50 VSS_112 AB4 AU5 VSS_174
l
K4 VSS_51 VSS_113 AB10 AU8 VSS_175
K10 VSS_52 VSS_114 AB13 AU11 VSS_176
K22 VSS_53 VSS_115 AB16 AU14 VSS_177
a
K27 VSS_54 VSS_116 AB19 AU20 VSS_178
K30 VSS_55 VSS_117 AB22 AU23 VSS_179
i
K33 VSS_56 VSS_118 AD4 AU27 VSS_180
L5 VSS_57 VSS_119 AD9 AV4 VSS_181
t
L18 VSS_60 VSS_122 AD18 AV12 VSS_184 VSS_213 L24
L21 VSS_61 VSS_123 AD21 AV15 VSS_185 VSS_215 AL10
n
L25 VSS_62 VSS_124 AD24 AV25 VSS_186 VSS_214 AK21
r
FP4 REV 0.93 FP4 REV 0.93
FP4_BGA968 FP4_BGA968
n f id B
c o
a l
m p
co
A A

FP4 GND
Custom A00
5 4 3 2 1
A B C D E
Main Func = DIMM1 DDRA_SDQ[0..63]

DDRA_SDQ[0..63] [7]
+1.2V_DDR JDIMM1
+1.2V_DDR DDRA_SDM[0..7]
DDRA_SDM[0..7] [7]
1 2
DDRA_SDQ5 3 VSS1 VSS2 4 DDRA_SDQ4 DDRA_SMA[0..13]
DQ5 DQ4 DDRA_SMA[0..13] [7]
5 6
DDRA_SDQ1 7 VSS3 VSS4 8 DDRA_SDQ0
9 DQ1 DQ0 10
DDRA_SDQS0# 11 VSS5 VSS6 12 DDRA_SDM0
[7] DDRA_SDQS0# DQS0_c DM0_n/DBI0_n
DDRA_SDQS0 13 14
[7] DDRA_SDQS0 15 DQS0_t VSS7 16 1 2
DDRA_SDQ6 MEM_MA_RST#
DDRA_SDQ7 17 VSS8 DQ6 18 CD80 @ESD@
Vinafix.com
y
19 DQ7 VSS9 20 DDRA_SDQ2 100P_0402_50V8J
DDRA_SDQ3 21 VSS10 DQ2 22
DQ3 VSS11
l
23 24 DDRA_SDQ12
27 DQ13 VSS13 28 DDRA_SDQ8
1
DDRA_SDQ9 29 VSS14 DQ8 30 1
31 DQ9 VSS15 32 DDRA_SDQS1#
n
VSS16 DQS1_c DDRA_SDQS1# [7]
DDRA_SDM1 33 34 DDRA_SDQS1
35 DM1_n/DBI_n DQS1_t 36 DDRA_SDQS1 [7]
39 DQ15 DQ14 40
o
43 DQ10 DQ11 44
47 DQ21 DQ20 48
51 DQ17 DQ16 52
[7] DDRA_SDQS2# DQS2_c DM2_n/DBI2_n
L
DDRA_SDQS2 55 56 +1.2V_DDR
[7] DDRA_SDQS2 DQS2_t VSS27
57 58 DDRA_SDQ22
VSS30 DQ18 1 1 1 1 1 1 1 1 1 1 1 1 1 1
DDRA_SDQ19 63 64 CD81 CD82 CD83 CD84 CD85 CD86
65 DQ19 VSS31 66 DDRA_SDQ28 CD87
L
CD88 CD89 CD90 CD91 CD92 CD93 CD94
VSS32 DQ28
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
DDRA_SDQ29 67 68
DQ29 VSS33 2 2 2 2 2 2 2 2 2 2 2 2 2 2
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
69 70 DDRA_SDQ24
75 VSS36 DQS3_c 76 DDRA_SDQS3# [7]
DDRA_SDM3 DDRA_SDQS3
E
DM3_n/DBI3_n DQS3_t DDRA_SDQS3 [7]
77 78
81 DQ30 DQ31 82
DDRA_SDQ26 83 VSS39 VSS40 84 DDRA_SDQ27 +0.6V_DDR_VTT
85 DQ26 DQ27 86
87 VSS41 VSS42 88
D
89 CB5/NC CB4/NC 90
VSS43 VSS44 1 1 1
91 92 CD96 CD97
93 CB1/NC CB0/NC 94 CD95
VSS45 VSS46
10U_0603_6.3V6M
10U_0603_6.3V6M
95 96
DQS8_c DM8_n/DBI_n/NC 2 2 2
1U_0402_6.3V6K
97 98
r
99 DQS8_t VSS47 100
101 VSS48 CB6/NC 102
103 CB2/NC VSS49 104
2 2
105 VSS50 CB7/NC 106
CB3/NC VSS51
o
107 108 MEM_MA_RST#
VSS52 RESET_n MEM_MA_RST# [7]
DDRA_CKE0 109 110 DDRA_CKE1
[7] DDRA_CKE0 111 CKE0 CKE1 112 DDRA_CKE1 [7]
+1.2V_DDR
f
DDRA_BG1 113 VDD1 VDD2 114 MEM_MA_ACT#
[7] DDRA_BG1
DDRA_BG0 115 BG1 ACT_n 116 2 MEM_MA_ACT#
1 [7] Follow CRB design
[7] DDRA_BG0
DDRA_SMA12
117
119
BG0
VDD3
A12
ALERT_n
VDD4
A11
118
120 DDRA_SMA11 RD16 1K_0402_1%
reserve
121 122 +VREF_CA +1.2V_DDR
l
DDRA_SMA9 DDRA_SMA7
123 A9 A7 124
DDRA_SMA8 125 VDD5 VDD6 126 DDRA_SMA5
A8 A5
2
DDRA_SMA6 127 128 DDRA_SMA4 +1.2V_DDR +0.6V_DDR_VTT
A6 A4
a
129 130 RD17
DDRA_SMA3 131 VDD7 VDD8 132 DDRA_SMA2 1K_0402_1%
DDRA_SMA1 133 A3 A2 134 MEM_MA_EVENT#
i
A1 EVENT_n/NF MEM_MA_EVENT# [7]
10P_0402_50V8J
CD101
10P_0402_50V8J
CD102
10P_0402_50V8J
CD98
10P_0402_50V8J
CD99
10P_0402_50V8J
CD103
10P_0402_50V8J
CD100
10P_0402_50V8J
CD104
135 136
1
DDRA_CLK0 137 VDD9 VDD10 138 DDRA_CLK1 +VREF_CA 1 1 1 1 1 1 1
t
[7] DDRA_CLK0 DDRA_CLK0# 139 CK0_t CK1_t/NF 140 DDRA_CLK1# DDRA_CLK1 [7]
[7] DDRA_CLK0# 141 CK0_c CK1_c/NF 142 DDRA_CLK1# [7]
0.1U_0402_16V4Z
0.1U_0402_16V4Z
VDD11 VDD12
@RF@
@RF@
@RF@
@RF@
@RF@
@RF@
@RF@
1 @ 2 143 144 DDRA_SMA0
RD18 0_0402_5% DDRA_SBS1# 145 PARITY A0 146 DDRA_SMA10 @ 2 2 2 2 2 2 2
[7] DDRA_SBS1# BA1 A10/AP 1 1 1
2
n
147 148 CD105 CD106 CD107
DDRA_SCS0# 149 VDD13 VDD14 150 DDRA_SBS0# 4.7U_0402_6.3V6K RD19
[7] DDRA_SCS0# 151 CS0_n BA0 152 DDRA_SBS0# [7]
DDRA_SWE# DDRA_SRAS# 1K_0402_1%
DDRA_SRAS# [7]
r
[7] DDRA_SWE# 153 WE_n/A14 RAS_n/A16 154 2 2 2
VDD15 VDD16
2.2U_0402_6.3V6M
CD108
2.2U_0402_6.3V6M
CD109
2.2U_0402_6.3V6M
CD110
2.2U_0402_6.3V6M
CD111
2.2U_0402_6.3V6M
CD112
2.2U_0402_6.3V6M
CD113
2.2U_0402_6.3V6M
CD114
DDRA_ODT0 155 156 DDRA_SCAS#
[7] DDRA_ODT0 DDRA_SCAS# [7]
1
DDRA_SCS1# 157 ODT0 CAS_n/A15 158 DDRA_SMA13
[7] DDRA_SCS1# CS1_n A13 1 1 1 1 1 1 1
159 160 +VREF_CA
VDD17 VDD18
id
DDRA_ODT1 161 162
[7] DDRA_ODT1 ODT1 C0/CS2_n/NC
@RF@
@RF@
@RF@
@RF@
@RF@
@RF@
@RF@
163 164
165 VDD19 VREFCA 166 2 2 2 2 2 2 2
167 C1, CS3_n,NC SA2 168
171 DQ37 DQ36 172
f 1000P_0402_50V7K
DQ33 DQ32 1
175 176
CD115
3 [7] DDRA_SDQS4# DQS4_c DM4_n/DBI4_n 3
DDRA_SDQS4 179 180
n
[7] DDRA_SDQS4 181 DQS4_t VSS59 182 2
DDRA_SDQ39
o
c
VSS68 DQS5_c DDRA_SDQS5# [7]
201 DM5_n/DBI5_n DQS5_t 202 DDRA_SDQS5 [7]
DQ46 DQ47
l
205 206
209 DQ42 DQ43 210
DQ52 DQ53
a
213 214
217 DQ49 DQ48 218
[7] DDRA_SDQS6# DQS6_c DM6_n/DBI6_n +2.5V_MEM
p
DDRA_SDQS6 221 222
[7] DDRA_SDQS6 DQS6_t VSS79
223 224 DDRA_SDQ54
DDRA_SDQ51 229 VSS82 DQ50 230 +1.2V_DDR +1.2V_DDR
m
VSS86 DQ57 1 1 1
DDRA_SDQ56 237 238 CD119 CD120
239 DQ56 VSS87 240 DDRA_SDQS7# CD118
VSS88 DQS7_c DDRA_SDQS7# [7] 1 1
330U_D2_2V_Y
330U_D2_2V_Y
10U_0603_6.3V6M
10U_0603_6.3V6M
<Address: 000> DM7_n/DBI7_n DQS7_t DDRA_SDQS7 [7] 2 2 2
co
CD116
CD117
1U_0402_6.3V6K
243 244 + +
DDRA_SDQ62 245 VSS89 VSS90 246 DDRA_SDQ63 @
247 DQ62 DQ63 248
+2.5V_MEM DDRA_SDQ58 249 VSS91 VSS92 250 DDRA_SDQ59 2 2
251 DQ58 DQ59 252
253 VSS93 VSS94 254
4 4
[9,14] APU_SCLK0 255 SCL SDA 256 APU_SDATA0 [9,14]
+3VS VDDSPD SA0
257 258 +0.6V_DDR_VTT
259 VPP1 VTT 260
1 VPP2 SA1
261 262
CD121 GND1 GND2
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1
CD124
DEREN_40-42271-26001RHF CONN@
2 2016/01/07 2017/01/07 Title
Issued Date Deciphered Date
DDR4 SODIMM-I Socket
C A00
DIMM_A H:4mm RVS
A B C D E
A B C D E
Main Func = DIMM2

+1.2V_DDR JDIMM2 +1.2V_DDR
1 2
DDRB_SDQ5 3 VSS1 VSS2 4 DDRB_SDQ4
5 DQ5 DQ4 6 DDRB_SDQ[0..63]
DDRB_SDQ1 7 VSS3 VSS4 8 DDRB_SDQ0 DDRB_SDQ[0..63] [7]
9 DQ1 DQ0 10 DDRB_SDM[0..7]
VSS5 VSS6 DDRB_SDM[0..7] [7]
DDRB_SDQS0# 11 12 DDRB_SDM0
[7] DDRB_SDQS0# 13 DQS0_c DM0_n/DBI0_n 14 DDRB_SMA[0..13]
DDRB_SDQS0 DDRB_SMA[0..13] [7]
[7] DDRB_SDQS0 DQS0_t VSS7
15 16 DDRB_SDQ6
Vinafix.com
y
DDRB_SDQ7 17 VSS8 DQ6 18
19 DQ7 VSS9 20 DDRB_SDQ2
VSS10 DQ2
l
DDRB_SDQ3 21 22 MEM_MB_RST# 1 2
23 DQ3 VSS11 24 DDRB_SDQ12 CD125 @ESD@
DDRB_SDQ13 25 VSS12 DQ12 26 100P_0402_50V8J
1
27 DQ13 VSS13 28 DDRB_SDQ8 1
n
31 DQ9 VSS15 32 DDRB_SDQS1#
33 VSS16 DQS1_c 34 DDRB_SDQS1# [7]
DDRB_SDM1 DDRB_SDQS1
DM1_n/DBI_n DQS1_t DDRB_SDQS1 [7]
35 36
o
39 DQ15 DQ14 40
43 DQ10 DQ11 44
47 DQ21 DQ20 48
DDRB_SDQ17 49 VSS23 VSS24 50 DDRB_SDQ16 +1.2V_DDR
51 DQ17 DQ16 52
VSS25 VSS26
L
[7] DDRB_SDQS2# DQS2_c DM2_n/DBI2_n
DDRB_SDQS2 55 56 1 1 1 1 1 1 1 1 1 1 1 1 1 1
57 58 DDRB_SDQ22 CD126 CD127 CD128 CD129 CD130 CD131
DDRB_SDQ23 59 VSS28 DQ22 60 CD132 CD133 CD134 CD135 CD136 CD137 CD138 CD139
DQ23 VSS29
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
61 62 DDRB_SDQ18
VSS30 DQ18 2 2 2 2 2 2 2 2 2 2 2 2 2 2
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
DDRB_SDQ19 63 64
L
E
VSS36 DQS3_c DDRB_SDQS3# [7]
DDRB_SDM3 75 76 DDRB_SDQS3
DM3_n/DBI3_n DQS3_t DDRB_SDQS3 [7]
77 78 +0.6V_DDR_VTT
81 DQ30 DQ31 82
DQ26 DQ27 1 1 1
85 86 CD141 CD142
D
87 VSS41 VSS42 88 CD140
CB5/NC CB4/NC
10U_0603_6.3V6M
10U_0603_6.3V6M
89 90
VSS43 VSS44 2 2 2
1U_0402_6.3V6K
91 92
93 CB1/NC CB0/NC 94
95 VSS45 VSS46 96
r
97 DQS8_c DM8_n/DBI_n/NC 98
99 DQS8_t VSS47 100
101 VSS48 CB6/NC 102
2 2
103 CB2/NC VSS49 104
VSS50 CB7/NC
o
105 106
107 CB3/NC VSS51 108 MEM_MB_RST#
109 VSS52 RESET_n 110 MEM_MB_RST# [7]
DDRB_CKE0 DDRB_CKE1
f
[7] DDRB_CKE0 CKE0 CKE1 DDRB_CKE1 [7]
111 112 +1.2V_DDR
DDRB_BG1 113 VDD1 VDD2 114 MEM_MB_ACT#
[7] DDRB_BG1 BG1 ACT_n MEM_MB_ACT# [7]
DDRB_BG0 115 116 2 1
[7] DDRB_BG0 BG0 ALERT_n
117 118
119 VDD3 VDD4 120
l
DDRB_SMA12 DDRB_SMA11 RD20 1K_0402_1%
DDRB_SMA9 121 A12 A11 122 DDRB_SMA7
123 A9 A7 124
DDRB_SMA8 125 VDD5 VDD6 126 DDRB_SMA5
A8 A5
a
DDRB_SMA6 127 128 DDRB_SMA4 del +VREF_CA cap 10/20
129 A6 A4 130
DDRB_SMA3 131 VDD7 VDD8 132 DDRB_SMA2
i
DDRB_SMA1 133 A3 A2 134 MEM_MB_EVENT#
A1 EVENT_n/NF MEM_MB_EVENT# [7]
135 136
t
DDRB_CLK0 137 VDD9 VDD10 138 DDRB_CLK1
[7] DDRB_CLK0 139 CK0_t CK1_t/NF 140 DDRB_CLK1 [7]
DDRB_CLK0# DDRB_CLK1#
[7] DDRB_CLK0# CK0_c CK1_c/NF DDRB_CLK1# [7]
141 142
1 @ 2 143 VDD11 VDD12 144 DDRB_SMA0 +VREFB_CA +1.2V_DDR
PARITY A0
n
RD21 0_0402_5% DDRB_SBS1# 145 146 DDRB_SMA10
[7] DDRB_SBS1# BA1 A10/AP
147 148
VDD13 VDD14
2
DDRB_SCS0# 149 150 DDRB_SBS0#
DDRB_SBS0# [7]
r
[7] DDRB_SCS0# DDRB_SWE# 151 CS0_n BA0 152 DDRB_SRAS# RD30
[7] DDRB_SWE# 153 WE_n/A14 RAS_n/A16 154 DDRB_SRAS# [7]
1K_0402_1%
DDRB_ODT0 155 VDD15 VDD16 156 DDRB_SCAS#
[7] DDRB_ODT0 ODT0 CAS_n/A15 DDRB_SCAS# [7]
DDRB_SCS1# 157 158 DDRB_SMA13
1
[7] DDRB_SCS1# CS1_n A13
id
15mil 159 160
DDRB_ODT1 161 VDD17 VDD18 162
[7] DDRB_ODT1 163 ODT1 C0/CS2_n/NC 164
+VREFB_CA
0.1U_0402_16V4Z
0.1U_0402_16V4Z
165 VDD19 VREFCA 166
1000P_0402_50V7K
167 C1, CS3_n,NC SA2 168 @
VSS53 VSS54 1 1 1 1
2
DDRB_SDQ37 169 170 DDRB_SDQ36 CD153 CD155 CD154
f CD143
171 DQ37 DQ36 172 4.7U_0402_6.3V6K RD31
DDRB_SDQ33 173 VSS55 VSS56 174 DDRB_SDQ32 1K_0402_1%
175 DQ33 DQ32 176 2 2 2 2
3
DDRB_SDQS4# 177 VSS57 VSS58 178 DDRB_SDM4 3
n
[7] DDRB_SDQS4#
1
DDRB_SDQS4 179 DQS4_c DM4_n/DBI4_n 180
181 182 DDRB_SDQ39
o
c
199 VSS68 DQS5_c 200 DDRB_SDQS5# [7]
DDRB_SDM5 DDRB_SDQS5
DM5_n/DBI5_n DQS5_t DDRB_SDQS5 [7]
201 202
VSS69 VSS70
l
DDRB_SDQ46 203 204 DDRB_SDQ47
205 DQ46 DQ47 206
209 DQ42 DQ43 210 +2.5V_MEM
VSS73 VSS74
a
DDRB_SDQ52 211 212 DDRB_SDQ53
213 DQ52 DQ53 214
DDRB_SDQ49 215 VSS75 VSS76 216 DDRB_SDQ48 +1.2V_DDR +1.2V_DDR
217 DQ49 DQ48 218
VSS77 VSS78
p
[7] DDRB_SDQS6# DQS6_c DM6_n/DBI6_n
DDRB_SDQS6 221 222
[7] DDRB_SDQS6 223 DQS6_t VSS79 224 DDRB_SDQ54 1 1 1
VSS80 DQ54
330U_D3_2.5VY_R6M
330U_D3_2.5VY_R6M
DDRB_SDQ55 225 226 1 1 CD147 CD148
227 DQ55 VSS81 228 DDRB_SDQ50 CD146
VSS82 DQ50
CD144
CD145
10U_0603_6.3V6M
10U_0603_6.3V6M
DDRB_SDQ51 229 230 + +
DQ51 VSS83 2 2 2
1U_0402_6.3V6K
231 232 DDRB_SDQ60 @ @
m
235 DQ61 VSS85 236 DDRB_SDQ57 2 2
VSS88 DQS7_c DDRB_SDQS7# [7]
co
DDRB_SDM7 241 242 DDRB_SDQS7
243 DM7_n/DBI7_n DQS7_t 244 DDRB_SDQS7 [7]
+2.5V_MEM DDRB_SDQ62 245 VSS89 VSS90 246 DDRB_SDQ63
247 DQ62 DQ63 248
251 DQ58 DQ59 252
4 4
253 VSS93 VSS94 254
[9,13] APU_SCLK0 SCL SDA APU_SDATA0 [9,13]
255 256 +3VS
+3VS VDDSPD SA0
1 257 258
VPP1 VTT +0.6V_DDR_VTT
259 260
CD149 261 VPP2 SA1 262
GND1 GND2
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1
CD152
2 Security Classification Compal Secret Data Compal Electronics, Inc.
DEREN_40-42261-26001RHF CONN@ 2016/01/07 2017/01/07 Title
Issued Date Deciphered Date
DDR4 SODIMM-II Socket
C A00
<Address: 100> DIMM_B H:4mm STD
A B C D E
5 4 3 2 1
+APU_CORE_GFX
PU500
+19VB PL501 PWM P49
ISL62771HRTZ
Max:22A
Max:3.4A Max:5.5A
PJPDC1 +19V_ADPIN +19V_VIN +APU_CORE Max:22A
AC Adapter
+19V_ADPIN
PL1 PQ740
NMOSFET
PQ718
NMOSFET
Charger
PWM PU703 PQ717
+19VB PL1001
PU1001
PWM P48
P41
PR703 PL700 NMOSFET ISL62771HRTZ +APU_CORE_NB
Max:12A
ISL95520 P42 Max:5.5A
Vinafix.com
D
65W
AMD Bristol LA-D803P PR01

+17.4V_BATT+
PR765
1206
PL301
RX4 0805
PU300
PWM
RT8237EZQW
P47
+INV_PWR_SRC For LCD

Backlight
PJP301
+0.95VALWP PJP302
Max:11.3A
+0.95VALW
Max:2A
Max:8.5A
U15
LOAD SWITCH
APE8990 P26
0.95VSDGPU_OUT
J11
+0.95VSDGPU Max:2A
D
n l y
o
PL3 U4 +0.95VS
NMOSFET Max:8.5A
2015/12/4 AO4304L P26
+17.4V_BATT++
PL201
PU200
PWM P44
+0.675VSP PJP203 +0.675VS Max:2A 0603
+3VS_CAM
Max:0.5A
L
RT8207PGQW RX27
+1.35VP PJP200
PJP201
+1.35V Max:5A
PBATT1 UX4 +LCDVDD +LCDVDD_CONN
LOAD SWITCH LX1
Battery (4S) +VGA_CORE SY6288 P16 Max:1.5A
L
PU1100 P53
PL1101 PWM
P41 ISL62771HRTZ Max:34A +3VALW
+APU_CORE RM10 1206
+APU_CORE_NB Max:2A
E
PU1400 +1.35V_MEM_GFX
Max:2A RM7 1206
+3VS_WLAN_NGFF
PL1401 PWM
SYX198DQNC
P51
+1.35VGPUP PJP1401 Max:3.38A
+APU_CORE_GFX U74 AP2821
LOAD SWITCH +3VGS
Max:0.05A
D
P26
(+0.775VALW)
Max:7.8A Max:5.07A
DIS@
+VDDCR_FCH_ALW) PU100 PJP100 +3VALW U2302 3VS +3VS

PL102 PWM PJP102 LOAD SWITCH J511
APW8822 P43 APE8990 P26
r
C
+1.35V
+19VB C
+0.95VS Max:5.5A
o
TP_EN +3VALW Q12 P24 +3VS_TOUCH
+0.95VALW R39 Max:0.035A
f
+1.8VS
VDDCR_FCH_S5
+1.8V_ALW PU800 P50
PJP801 APL5336 LDO PJP802 +0.775VALW Max:0.2A
+3VS Q135,Q2513, Q2515
l
+3VALW
,Q2514 AO3416L +VDDCR_FCH_ALW
+1.5VS
Q2516 , Q2507 DMN66
U2 ,LM393 P26
Max:0.2A
a
PU400 P45 +1.5VSP +1.5VS
+RTCBATT PJP401 LDO PJP402
Max:0.3A
i
APL5930
t
PU1200 P52 +1.8VGSP
PJP1201 LDO
APL5930
PJP1202 +1.8VGS
Max:0.5A
n
PU600 +1.8V_ALW
PJP601 PWM
SY8003DFC
P46 PJP602 Max:2.0A
r
U15 +1.8VS_LS +1.8VS
UL3
LOAD SWITCH
+LAN_VDD33 LOAD SWITCH
APE8890 P26
J10 Max:1.5A
SY6288 P19
id
JP3 @
Max:0.07A
+3VS +VDD_TOUCH
R11 @ R14
f
0603
B
PJP101 +5VALW Max:7.8A R12
B
PJP103 P16
+APU_CORE
o n U2301
LOAD SWITCH
EM5209VF P26
UU3
USB Power SW
5VS J509
J510
Max:2.0A
+5V_USB_PWR2
+5VS +5VS
FE1 Fuse
@ P24
Max:7.0A
+5VS_KBL
Max:0.5A
c
+APU_CORE_NB SY6288 P25 RE59
UI5
Max:2.0A JP7 +5VS_ODD
USB Power SW +5V_USB_PWR1 @
l
+APU_CORE_GFX SY6288 P23
QS2 P22
SI3456
Max:2.0A
(+0.775VALW) NMOSFET
a
+VDDCR_FCH_ALW
+FAN_POWER
+1.35V
Max:1.0A
p
+0.95VS
+0.95VS
+0.95VALW
m
+1.8VS
+1.8V_ALW
co
+3VS
A A
+3VALW
+1.5VS
+RTCBATT

Green CLK
5 4 3 2 1
5 4 3 2 1
Main Func = LCD
1 @ 2 EDP_HPD
[8] DP0_HPD
+3VS +LCDVDD
R13 0_0402_5%
1
Vinafix.com
y
U1 +3VS
5 1 60mil RP1
IN OUT
l
100K_0402_5%
2
2
GND del reserve circuit 12/1
D 1 D
C17 4 3 2 1
4.7U_0603_6.3V6K EN OC
n
RX9
2 DX1
SY6288C20AAC_SOT23-5 10K_0402_5%
2 1 DISPOFF#
[27] BKOFF#
1
RX7 1 @ 2 0_0402_5% ENVDD_RE RB751V-40_SOD323-2
[8] ENVDD 10K_0402_5%
2 1 RP2
[27] EC_ENVDD
RX8 @ 0_0402_5%
2
change to SA000079400 2/4
L
CONN@
ACES_51540-04001-P01
+VDD_TOUCH 40
2 1 TS_EN_RR 39 40
L
[27] TS_EN_R 39
RX25 33_0402_5% 38
INVTPWM USB20_TOUCH_P1 37 38
[8] INVTPWM 36 37
USB20_TOUCH_N1
+LCDVDD +LCDVDD_CONN 35 36
35
1
W=60mils CAM_DETECT# 34
E
[9] CAM_DETECT# 34
RP3 33
1 2 100K_0402_5% USB20_CAM_P2_R 32 33
HCB2012KF-221T30_2P USB20_CAM_N2_R 31 32
LX1 30 31
+3VS_CAM
2
A_MIC_DATA 29 30
[18] A_MIC_DATA 29
change to SM01000EJ00 2/4 A_MIC_CLK 28
D
[18] A_MIC_CLK 28
27
26 27
IR_GND 26
25
DISPOFF# 24 25
INVTPWM 23 24
r
22 23
0.1U_0402_16V7K 2 1 C4314 EDP_TXP1_C 21 22
[8] EDP_TXP1 21
C 0.1U_0402_16V7K 2 1 C4313 EDP_TXN1_C 20 C
[8] EDP_TXN1 19 20
19
o
0.1U_0402_16V7K 2 1 C4312 EDP_TXP0_C 18
[8] EDP_TXP0 18
0.1U_0402_16V7K 2 1 C4311 EDP_TXN0_C 17
[8] EDP_TXN0 16 17
f
+19VB +INV_PWR_SRC +INV_PWR_SRC DBC_EN R6 1 @ 2 0_0402_5% DBC_EN_R 0.1U_0402_16V7K 2 1 C4322 EDP_AUXN_C 15 16
W=40mils [27] DBC_EN [8] EDP_AUXN 2 1 C4321 EDP_AUXP_C 14 15
0.1U_0402_16V7K
[8] EDP_AUXP 14
@ 13
13
1
R4 1 2 0_0805_5% 1 2 RX2 LCD_TST_C 12
[27] LCD_TEST 11 12
l
@ 100_0402_5% EDP_HPD
F1 1 2 R5 DBC_EN_R 10 11
10U_0603_25V6M
0.1U_0603_25V7K
0_0402_5% 9 10
1 1 9
SMD1812P150TF/24 1.5A UL/CSA/TUV 8
2
8
a
C5 C4 7
+LCDVDD_CONN 7
@ 6
2 2 5 6
i
4 5
1
@ 2 +DCBAT_CAM 3 4 42
t
R51 0_0805_5% 2 3 G2 41
+INV_PWR_SRC 2 G1
1
1
W=40mils
JEDP1
r n
B
Webcam PWR CTRL
+3VS +3VS_CAM
[10]
[10]
n f
USB20_CAM_P2
USB20_CAM_N2 id 1
4
MCM1012B900F06BP_4P
L3
2
EMI@
3
USB20_CAM_P2_R
USB20_CAM_N2_R
R7 1 @ 2 0_0402_5%
B
o
R16 0_0603_1%
2 @ 1 1 2 IR_GND
1 add 4.7u 12/2 R17 0_0402_5%
c
C18 @EMI@
change to shortpad 03/11 4.7U_0603_6.3V6K 1 2
R18 0_0402_5%
2 @EMI@
* Touch Screen Panel
a l +3VS +LCDVDD_CONN
0.1U_0402_10V7K
p
1 1 1
CX1
USB20_TOUCH_N1 C2 C3
+3VS +5VS [10] USB20_TOUCH_N1
1U_0402_10V6K
USB20_TOUCH_P1
0.1U_0402_16V7K
+VDD_TOUCH [10] USB20_TOUCH_P1 2 2 2
1
m
2
R11 R12
0_0603_5% 0_0603_1%
@
@ESD@
2
co
F2 @
TPAN_VDD_F 1 2 PESD5V0U2BT_SOT23-3
DX2
1.1A_24V_SMD1812P110TF-24
Place close to JEDP
1
A A
2 1
R14
0_0603_1%
@

eDP / webcam / TouchScreen
5 4 3 2 1
5 4 3 2 1
Main Func = HDMI
D3E: 5.6 ohm
Vinafix.com
D Place close to JHDMI
RI1
LI1
1 @EMI@ 2 0_0402_5%
EMI@ TMDS_L_TXCN
n l y W=40mils
change to +5v_hdmi
+5V_HDMI
D
1
TMDS_TXCN 2 1 TMDS_L_TXCN 2 1
o
@EMI@ +5VS
150_0402_5% 1
CI1 2 1 0.1U_0402_10V7K TMDS_TXCN FI1
[8] HDMI_DP1_TXN3 2 1 0.1U_0402_10V7K 3 4 RI3
CI2 TMDS_TXCP TMDS_TXCP TMDS_L_TXCP 1.5A_6V_1206L150PR~D CI9
[8] HDMI_DP1_TXP3
TMDS_L_TXCP .1U_0402_16V7K
2
CI3 2 1 0.1U_0402_10V7K TMDS_TX0N HCM1012GH900BP_4P +3VS 2
[8] HDMI_DP1_TXN2 2 1 0.1U_0402_10V7K 1 2
CI4 TMDS_TX0P pin vertical swap 12/14
[8] HDMI_DP1_TXP2
RI2 @EMI@ 0_0402_5%
L
CI5 2 1 0.1U_0402_10V7K TMDS_TX1N
[8] HDMI_DP1_TXN1 2 1 0.1U_0402_10V7K
CI6 TMDS_TX1P
[8] HDMI_DP1_TXP1
1
RI4 1 @EMI@ 2 0_0402_5%
CI7 2 1 0.1U_0402_10V7K TMDS_TX2N conn change follow D3E RI19
[8] HDMI_DP1_TXN0 2 1 0.1U_0402_10V7K LI2 EMI@
CI8 TMDS_TX2P TMDS_L_TX0N 10K_0402_5%
L
[8] HDMI_DP1_TXP0
1
TMDS_TX0N 2 1 TMDS_L_TX0N @EMI@
change conn 11/13
2
swap net 04/29 TX1 and TX2 group swap 3/21 150_0402_5% JHDMI1
TMDS_TX0P 3 4 TMDS_L_TX0P RI6 HDMI_HPLUG 19
HP_DET
1
2
3
4
4
3
2
1
TMDS_L_TX0P 18
2
RPI1 RPI2 HCM1012GH900BP_4P 17 +5V
499_0804_8P4R_1% 499_0804_8P4R_1% 1 2 pin vertical swap 12/14 CPU_DPB_CTRLDAT_R 16 DDC/CEC_GND
RI5 @EMI@ 0_0402_5% CPU_DPB_CTRLCLK_R 15 SDA
14 SCL
8
7
6
5
5
6
7
8
13 Reserved
1 @EMI@ 2 TMDS_L_TXCN 12 CEC
D
RI7 0_0402_5% TMDS_L_TX1N 11 CK-
CK_shield
1
LI3 EMI@ TMDS_L_TXCP 10
@EMI@ CK+
TMDS_TX1N 2 1 TMDS_L_TX1N TMDS_L_TX0N 9
150_0402_5% 8 D0-
RI9 TMDS_L_TX0P 7 D0_shield
r
+3VS TMDS_TX1P 3 4 TMDS_L_TX1P TMDS_L_TX1P TMDS_L_TX1N 6 D0+
2
D1-
1
5
D HCM1012GH900BP_4P pin vertical swap 12/14 TMDS_L_TX1P 4 D1_shield 20
C D1+ GND C
2 QI1 1 2 TMDS_L_TX2N 3 21
o
G 2N7002K_SOT23-3 RI8 @EMI@ 0_0402_5% 2 D2- GND 22
D2_shield GND
1
S TMDS_L_TX2P 1 23
RI20 D2+ GND
f
100K_0402_5% CONCR_099AKAC19NBLCNF
1 @EMI@ 2 DC232003600
RI10 0_0402_5%
2
HCM1012GH900BP_4P CONN@
l
TMDS_TX2P 3 4 TMDS_L_TX2P TMDS_L_TX2P
1
Design Guide p225 沒沒 @EMI@
150_0402_5%
Main: LTCX0064K00 (CIS ok)
TMDS_TX2N 2 1 TMDS_L_TX2N
(TEMP:DC021407310)
a
RI12
LI4 EMI@ TMDS_L_TX2N
2
i
1 2
RI11 @EMI@ 0_0402_5%
r n t 45@
Part Number
RO0000002HM
ROYALTY HDMI W/LOGO
Description
HDMI W/Logo:RO0000002HM
id
del emi reserve EMI part 0429
delete @emi@ before choke 11/27
+3VS
n f B
o
+5V_HDMI RPI3
8 1 APU_HDMI_CLK
7 2 APU_HDMI_DATA
6 3 CPU_DPB_CTRLDAT_R +3VS
c
5 4 CPU_DPB_CTRLCLK_R
2.2K_0804_8P4R_5%
CRB use 4.7k, bristol use 2.2k
1
l
C
QI3 2 1 2 HDMI_HPLUG
MMBT3904_NL_SOT23-3 B
E RI18 1
3
a
1
+3VS [8] DP1_HPD 150K_0402_5%
CI10 @
1
220P_0402_50V8J RI16
2 20K_0402_5%
p
RI17
2
100K_0402_5%
2
QI2B
2
DMN66D0LDW-7_SOT363-6
G
1 6 CPU_DPB_CTRLCLK_R
m
[8] APU_HDMI_CLK
S
D
5
G
co
4 3 CPU_DPB_CTRLDAT_R
[8] APU_HDMI_DATA
S
QI2A
DMN66D0LDW-7_SOT363-6
A A
remove esd 12/02

HDMI
A00
5 4 3 2 1
5 4 3 2 1
Main Func = Audio

moat moat
.1U_0402_16V7K
change to shortpad 03/11
+1.8VS +1.8V_AVDD
+5V_AVDD +5V_AVDD +5VS QA1 change to shortpad 03/11
+5VS 1.5A +5V_PVDD
2 LN2306LT1G_SOT23-3
CA17 Place close to Pin 26 RA4 0_0603_1%
@ change to 10V rate 04/21 add colay 03/07 2 @ 1 1 3 1 @ 2
S
Vinafix.com
CA10
CA11
1 2
RA1 0_0805_5% @ 1 RA5 0_0402_5% 1
1 1
l
CA1 1 CA2 CA3 1 CA4 1 2 0_0402_5%
G
+1.5VS
2
1
1
RA16 CA12
10U_0603_10V6M
10U_0603_10V6M
.1U_0402_16V7K
.1U_0402_16V7K
change to 10V rate 04/21 4.7U_0603_6.3V6K
D
2 2 +3VS 2 D
1 @ 2 0_0402_5%
.1U_0402_16V7K
4.7U_0603_10V6K
+1.8VS
2
2 2
+5V_PVDD
n
change to shortpad 03/11 RA15 Close pin40
+3V_DVDD
o
C6230, C6231 close CA15
1 1
CA16 +3V_DVDD +3V_1.8V_CPVDD
to UA1 pin1 +1.8V_AVDD
RA7 3234@ 0_0402_5%
.1U_0402_16V7K
Layout Note: Layout Note:
4.7U_0603_6.3V6K
2 2 1 2 +3V_1.8V_CPVDD
+3V_1.8V_CPVDD
Close pin41 Close pin46
3234@
RA6 3246@
41
46
26
40
36
L
9
UA1 1 2
PVDD1
PVDD2
AVDD1
AVDD2
DVDD
CPVDD
DVDD-IO
0_0402_5% 1 CA13 1 CA14
.1U_0402_16V7K
4.7U_0603_6.3V6K
RA14 1 3234@ 2 0_0402_5% 11
L
PC_BEEP_C CA42 1 2 0.1U_0402_16V7K 12 I2C_SDA 31
[9] HDA_RST#_AUDIO +Line1-VREFO-L
+3VS +3V_DVDD 3234@ I2C_SCL LINE1-VREFO-L 30 2 2
LINE1-VREFO-R +Line1-VREFO-R
[9] HDA_SYNC_AUDIO 10 29 +MIC2-VREFO +MIC2-VREFO
1 @ 2 6 SYNC MIC2-VREFO 28 CA23 1 2 2.2U_0603_6.3V6K
[9] HDA_BITCLK_AUDIO BIT-CLK VREF moat +3VALW +RTCVCC
CA5
CA6
RA2 0_0402_5% 5 35 CA24 1 2 1U_0603_16V7
E
[9] HDA_SDOUT_AUDIO HDA_SDIN0_R 8 SDATA-OUT CBN 37
1 1
25mA SDATA-IN CBP RA11 1 @ 2 0_0402_5%
4 20 V3D3_STB RA12 1 @ 2 0_0402_5%
RA8 1 @ 2 100K_0402_5% MIC_DATA_C 2 EAPD/DC DET 5VSTB
2 2 +3V_DVDD GPIO0/DMIC-DATA12
Close pin9 MIC_CLK_C 3 34 CA25 2 1 1U_0603_16V7
4.7U_0603_6.3V6K
change to shortpad 03/11 EC_MUTE# 47 GPIO1/DMIC-CLK CPVEE

.1U_0402_16V7K
D
[27] EC_MUTE# 48 PDB
add 100k follow vendor suggestion 12/4 RA13 2 1 100K_0402_5% SPDIFO/GPIO2/DMIC-DATA-34/DMIC-CLK-In/MIC-GPI
CA20 1 2 4.7U_0603_6.3V6K 27
CA21 1 2 10U_0603_6.3V6M 39 LDO1-CAP 17 RING2
CA22 1 2 4.7U_0603_6.3V6K 7 LDO2-CAP MIC2-L/RING2 18 SLEEVE RING2 [21]
r
LDO3-CAP MIC2-R/SLEEVE 19 SLEEVE [21]
MIC-CAP 24 MIC1-L CA26 1 2 10U_0603_6.3V6M
INT-SPK-L+ 42 LINE2-L 23
C SPK-L+ LINE2-R C
Speaker trace width >40mil INT-SPK-L- 43 22 LINE1-L
Layout Note: LINE1-L [21]
o
INT-SPK-R- 44 SPK-L- LINE1-L 21 LINE1-R
@ 2W4ohm speaker power SPK-R- LINE1-R LINE1-R [21]
INT-SPK-R+ 45 16 CA41 1 2 0.1U_0402_16V7K PC_BEEP_C RA49 1 2 1K_0402_1% PC_BEEP
Layout Note: SPK-R+ PCBEEP 32 3246@ HPOUT-L RA45 2 1
f
RA10 2 1 100K_0402_5%AUD_SENSE_A 13 HP-OUT-L 33 HPOUT-R HPOUT-L [21]
Place close to Pin 13 +3V_DVDD HP/LINE1 JD1 HP-OUT-R
10K_0402_5%
14 HPOUT-R [21]
15 MIC2/LINE2 JD2 25
SPDIFO/FRONT JD3/GPIO3 AVSS1 38
AVSS2
l
49
moat 1 THERMAL PAD
@ CA40
AUD_SENSE_A 1 2 JACK_SENSE_1# .1U_0402_16V7K ALC3234-CG_MQFN48_6X6
a
RA41 200K_0402_1% 2
i
JACK_SENSE_1# 2 @ 1 JACK_SENSE#
JACK_SENSE# [21]
RA42 0_0603_1%
t
HDA_SDIN0_R 1 2
RA43 33_0402_5% HDA_SDIN0 [9]
n
UA1
SA00008GJ00
r
3246@
ALC3246-CG_MQFN48_6X6
delete off-page 11/25

HDA_BITCLK_AUDIO 1
@EMI@
RA44
0_0402_5%
2
n f id B
o
1
@EMI@ change to SM01000NX00 2/4
MIC_CLK_C CA31
22P_0402_50V8J JSPK1 CONN@
c
2 INT-SPK-R+ EMI@ LA3 1 2 TAI-TECH HCB1005KF-800T20 0402 SPK_R+_CONN 1
INT-SPK-R- EMI@ LA4 1 2 TAI-TECH HCB1005KF-800T20 0402 SPK_R-_CONN 2 1 moat
INT-SPK-L+ EMI@ LA5 1 2 TAI-TECH HCB1005KF-800T20 0402 SPK_L+_CONN 3 2 change bom config 12/3
INT-SPK-L- EMI@ LA6 1 2 TAI-TECH HCB1005KF-800T20 0402 SPK_L-_CONN 4 3
4
l
1 @ 2
5 RA17 1 @ 20_0402_5%
Trace width for SPK-L+/SPK-L-/SPK-R+/SPK-R- 6 GND1 RA18 1 @ 20_0402_5%
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
GND2 RA19 1 @ 20_0402_5%
1 1 1 1
Speaker 4 ohm : 40mil
a
2
3
EMI@ CA27
EMI@ CA28
EMI@ CA30
1 20_0402_5%
EMI@ Ca29
close to JEDP1 12/29 JXT_WB247H-004S10M RA20 @
SP020017K10 RA21 0_0402_5%
AZ5125-02S.R7G_SOT23-3
AZ5125-02S.R7G_SOT23-3
1 @EMI@ Speaker 8 ohm : 20mil 2 2 2 2 ESD@ ESD@
p
CA9 DA1 DA2
10P_0402_50V8J
2
@
To eDP
1
RA22 1 2 0_0805_5%
follow emc require 11/27
m
EMI@
A_MIC_CLK LA1 1 2 BLM15BB221SN1D_2P MIC_CLK_C
[16] A_MIC_CLK A_MIC_DATA RA55 1 2 33_0402_5% MIC_DATA_C DA3
[16] A_MIC_DATA 2
EC Beep [27] BEEP#
co
1
1 PC_BEEP
@ CA39
6.8P_0402_50V 3
2 MCU Beep [9] APU_SPKR
A BAT54C-7-F_SOT23-3 A
del reserve 10k 12/01 GNDA GND

Layout Note: Reduce the stubs.
PC Beep Place on the moat between GND & GNDA.

Audio Codec ALC3234
A00
5 4 3 2 1
1 2 3 4 5
Main Func = LAN

followe nuvision Patrick suggestion
+LAN_VDD33 rising time : >0.5ms and <100ms +LAN_VDD10
+3VALW OPEN +LAN_VDD33
1 1
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0.1U_0402_25V6
0.1U_0402_25V6
JP3
CL5
CL6
2 1
l
2MM 2 2
A W=60mils W=60mils A
n
+3VALW +LAN_VDD33
o
CL9
1U_0402_6.3V6K UL3
2 1 5 1
IN OUT +3VALW
2
GND
WOL_EN 4 3 2 1
W=60mils
[27] WOL_EN EN OC followe nuvision Patrick suggestion
L
RL7 +LAN_VDD33
SY6288C20AAC_SOT23-5 10K_0402_5% +LAN_VDDREG
1.5A
2
RL5 0_0603_1%
RL6 2 @ 1
100K_0402_5%
4.7U_0603_6.3V6K
CL7
1 1 1
0.1U_0402_25V6
1
CL14
CL8
change to SA000079400 12/22 0.1U_0402_10V7K change to shortpad 03/11
2 2 2
D E Place close to UL1: Pin 32

follow nuvision Patrick suggestion
r
UL1 CL1, CL2 close to UL1 Pin 17, 18
MDI0+ 1 17 PCIE_ARX_DTX_P0_C 0.1U_0402_10V7K 2 1 CL1
4 MDIP0 HSOP 18 2 1 CL2 PCIE_ARX_DTX_P0 [6]
MDI1+ PCIE_ARX_DTX_N0_C 0.1U_0402_10V7K
PCIE_ARX_DTX_N0 [6]
o
MDI0- 2 MDIP1 HSON
+LAN_VDD10 MDI1- 5 MDIN0 change pin 12/15
MDIN1 13 PCIE_ATX_C_DRX_P0
f
HSIP 14 PCIE_ATX_C_DRX_P0 [6]
PCIE_ATX_C_DRX_N0 TL1
+LAN_VDD33 8 HSIN PCIE_ATX_C_DRX_N0 [6]
30 AVDD10 @ MDI1- 1 12 MDO1-
32 AVDD10 19 PLT_RST#_R 0_0402_5% 2 1 RL8 PLT_RST# MDI1+ 2 RD+ RX+ 11 MDO1+
AVDD33 PERSTB PLT_RST# [9,20,27] RD- RX-
l
23 1 @ 2 APU_PCIE_RST# +V_DAC 3 10 MCT0
+LAN_VDDREG DVDD33 APU_PCIE_RST# [9,20,33] RCT RCT
20 ISOLATEB RL9 0_0402_5% +V_DAC 4 9 MCT1
15 ISOLATEB MDI0- 5 TCT TCT 8 MDO0-
[10] CLK_PCIE_LAN REFCLK_P TD+ TX+
16 21 APU_PCIE_WAKE# MDI0+ 6 7 MDO0+
[10] CLK_PCIE_LAN#
a
REFCLK_N LANWAKEB APU_PCIE_WAKE# [9,27] TD- TX-
12 26 2 1
[9] LAN_CLKREQ# CLKREQB GPO +LAN_VDD33
i
XTLI 28 10K_0402_5% @ RL1 350UH_NS14-1-LF
XTLO 29 CKXTAL1
CKXTAL2 3 Place close to TCT pin
t
T94 27 NC 6 +V_DAC
T95 25 LED0 NC 7
LED1 NC 9 MCT0 RL14 1 2 75_0603_5%
NC 2
2.49K_0402_1%~D 1 2 RL2 31 10 followe nuvision Patrick suggestion MCT1 RL15 1 2 75_0603_5%
n
RSET NC 11 CL12
33 NC 22
GND NC 0.01U_0402_16V7K
24 1
T-GND_L
NC
RTL8106E-CG_QFN32_4X4
id
follow esd require reserve 12/2 EMI@
CL13
C 100P_1206_2KV8J C
EU3501 2
MDI1- 1 9 MDI1- T-GND
f
MDI1+ 2 8 MDI1+
MDI0- 4 7 MDI0- p/n swap 12/14
n
MDI0+ 5 6 MDI0+
o
3
@ESD@
c
JLAN1
8
+LAN_VDD33 +3VS PR4-
l
7
PR4+
CL10 MDO1- 6
PR2-
a
1
1 2 APU_PCIE_WAKE# 2 1 XTLI
RL10 10K_0402_5% RL3 5
1K_0402_5% 10P_0402_50V8J YL1 PR3-
1 2 4
XTAL0 GND0 PR3+
p
2
+3VS +LAN_VDD33 3 4 MDO1+ 3

ISOLATEB XTAL1 GND1 PR2+
CL11 25MHZ_10PF_7V25000014 MDO0- 2
2 1 XTLO PR1-
1
MDO0+ 1
RL4 10P_0402_50V8J PR1+ 9
m
15K_0402_1% GND 10
D
LAN_CLKREQ# 1 2 GND 11 D
RL11 @ 10K_0402_5% GND 12

2
GND
XTAL
co
WOL_EN 1 2 SANTA_130460-N T-GND
RL12 @ 10K_0402_5%
CONN@
Security Classification Compal Secret Data

Title
Compal Electronics, Inc.
Reserve 10K pull LAN_IO Issued Date 2016/01/07 Deciphered Date 2017/01/07
LAN RTL8106EUS
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom A00
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
BAL22 Sheet
Tuesday, June 21, 2016
LA-D803P
19 of 56
1 2 3 4 5
5 4 3 2 1
Main Func = WLAN

closed to pin 2, 4 +3VS_WLAN_NGFF
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y
+3VS_WLAN_NGFF +3VS_WLAN_NGFF
10P_0402_50V8J
CW14
10P_0402_50V8J
CW15
l
1 1
D D
change conn 12/3
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
RF@
RF@
2 1 2 1 2 2
10U_0603_6.3V6M
CW10
CW12
10U_0603_6.3V6M
CW11
CW13
+3VS_WLAN_NGFF @ @
o
1 2 1 2
NGFF WL Con (A Key)
2.2U_0402_6.3V6M
CW16
2.2U_0402_6.3V6M
CW17
1 1
RF@
RF@
JWLAN1
1 2 2 2
1 2
L
3 4
[10] USB20_MINI1_P4 5 3 4 6
[10] USB20_MINI1_N4 7 5 6
7
C
9
11
13
15
17
9
11
13
15
8
10
12
14
16
8
10
12
14
16
18
short gnd 12/2
D E C
r
19 17 18 20
For EC to detect
21 19 20 22 debug card insert.
23 21 22 24 RW8 1 2 100K_0402_5%
o
25 23 24 26
27 25 26 28 +3VS TO +3VS_WLAN_NGFF
f
[6] PCIE_ATX_C_DRX_P1 27 28
[6] PCIE_ATX_C_DRX_N1 29 30 E51_TX1 0_0402_5% 2 1 RW6 EC_TX
29 30 EC_TX [27]
31 32 E51_RX1 0_0402_5% 2 1 RW7 EC_RX
31 32 EC_RX [27]
33 34
l
[6] PCIE_ARX_DTX_P1 33 34
35 36
[6] PCIE_ARX_DTX_N1 35 36
37 38 +3VS 1 2 +3VS_WLAN_NGFF
37 38
a
[10] CLK_PCIE_WLAN CLK_PCIE_WLAN 39 40 RM7 0_1206_5%
CLK_PCIE_WLAN# 41 39 40 42
[10] CLK_PCIE_WLAN#
i
43 41 42 44 PLT_RST#_RW
WLAN_CLKREQ# 45 43 44 46 BT_ON#
t
[9] WLAN_CLKREQ# 45 46 BT_ON# [9]
WLAN_WAKE# 47 48 WL_OFF#_R Prevent Backdriver from +3VS_WLAN_NGFF to +3VS
[27] WLAN_WAKE# 47 48
49 50
51 49 50 52 +3VS_WLAN_NGFF +3VS
n
53 51 52 54
55 53 54 56
r
55 56
1
57 58 E51_TX2 0_0402_5% 2 @ 1 RW9 EC_TX change to @
59 57 58 60 E51_RX2 0_0402_5% 2 @ 1 RW10 EC_RX RW12
61 59 60 62 10K_0402_5%~D @ QW1
id
61 62
2
63 64 DII-DMN65D8LW-7~D
G
65 63 64 66
For V4DA2 debug board delete off-page 11/25
B B
2
67 65 66 WL_OFF#_R 1 3
67 WL_OFF# [10]
S
69 68
GND GND
n
1
C6
1
@
o
LCN_DAN05-67406-0100 RW13
0.1U_0402_16V7K
@ 2 10K_0402_5%~D @
PLT_RST#_RW 0_0402_5% 1 2 RW4
c
PLT_RST# [9,19,27]
2 @ 1 APU_PCIE_RST#
APU_PCIE_RST# [9,19,33]
2
0_0402_5% RW11
add part 12/2
a l
A
m p A
co
NGFF WLAN
5 4 3 2 1
5 4 3 2 1
Main Func = Audio Jack
RA25
RA26
+MIC2-VREFO 1 2
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y
1 2
change ok 12/21
l
2.2K_0402_5% ESD@
2.2K_0402_5% LA7 1 2 BLM15PX330SN1D_2P RING2_R
D [18] RING2 D
RA27 1 2 10_0402_1% AUD_HP1_JACK_L1 LA8 1 2 0_0402_5% AUD_PORTA_L_R_B
[18] HPOUT-L
n
1 2 LINE1-L_C RA28 1 2 1K_0402_5% EMI@
[18] LINE1-L
+Line1-VREFO-L CA32 10U_0603_10V6M RA29 1 2 4.7K_0402_5% LA8/LA9 change to 0ohm 05/03
EMI@
RA31 1 2 10_0402_1% AUD_HP1_JACK_R1 LA9 1 2 0_0402_5% AUD_PORTA_R_R_B
o
[18] HPOUT-R
1 2 LINE1-L_R RA32 1 2 1K_0402_5% LA10 1 2 BLM15PX330SN1D_2P SLEEVE_R
[18] LINE1-R
+Line1-VREFO-R CA33 10U_0603_10V6M RA33 1 2 4.7K_0402_5% ESD@
[18] SLEEVE
Layout Note:
Close to UA1
del cap and to place small board 12/1
L L
D E
C
f o r C
ia l
CLOSE TO JHP
r n t Universal Jack
(Global Headset Jack + mic phone in + line in support)
JHP1
id
AUD_PORTA_R_R_B SLEEVE_R 3
AUD_PORTA_L_R_B AUD_PORTA_L_R_B 1 G/M
L/R
f
SLEEVE_R [18] JACK_SENSE# JACK_SENSE# 5
RING2_R 5
B B
JACK_PLUG_DET 6
6
n
AUD_PORTA_R_R_B 2
R/L
3
2
L03ESDL5V0CC3-2_SOT23-3
DA4
AZ5123-02S.R7G_SOT23-3
DA5
JACK_PLUG_DET RING2_R 4
o
10 mils 7 M/G
GND
1
RA34
RA30
CA34
CA35
CA36
CA37
c
@
ESD@
ESD@
YUQIU_PJ753-F07J1BE-B
0_0402_5%
1
RA40
1 1 1 1 CONN@
l
1
ESD@
ESD@
ESD@
ESD@
@ @
a
2 2 2 2
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
10K_0402_5%
10K_0402_5%
change part 1217
m p
co
A A

JACK
5 4 3 2 1
A B C D E F G H
Main Func = HDD
RS23 RS37
del esd component 03/02
+3VS
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y
US2 TI@ US2 PARADE@ 0_0402_5% 0_0402_5%
SD028000080 SD028000080
1 D3E has no SATA redriver

PARADE@ PARADE@
l 1
0.01U_0402_16V7K
0.1U_0402_25V6K
SN75LVCP601RTJR PS8527CTQFN20GTR2-A2
n
1 1
2
SA00003ZX00 SA00007JU10
4.7K_0402_5%
RS33
4.7K_0402_5%
RS34
pin 9 8 means De-Emphasis
1
CS42
CS27
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
CH1 De-Emphasis =-6dB (NC is default)
2 2 CH2 De-Emphasis =-3dB (PU is -3dB)
o
DEW set to GND support GEN1/2/3 for TI
RS25
RS26
RS27
RS28
TI@ TI@
1
+3VS
2
10 nF check spec OK US2 @ TI@ TI@
RS19 1 20_0402_5% 7 6 DEW2
EN VDD 16 DEW1
CS37 1 2 0.01U_0402_16V7K SATA_ATX_C_DRX_P0 1 VDD
[10] SATA_ATX_DRX_P0
L
CS36 1 2 0.01U_0402_16V7K SATA_ATX_C_DRX_N0 2 A_INp 10
[10] SATA_ATX_DRX_N0 A_INn NC 20 HDD_REXT_SATA0
CS35 1 2 0.01U_0402_16V7K SATA_ARX_C_DTX_P0 5 REXT
[10] SATA_ARX_DTX_P0 B_OUTp
CS33 1 2 0.01U_0402_16V7K SATA_ARX_C_DTX_N0 4 9 HDD_A0_PRE0 DEVSLP[0] PU 10K, means not support DEVSLP function
[10] SATA_ARX_DTX_N0 B_OUTn A_PRE0 8 HDD_B0_PRE0
B_PRE0
L
+3VS RS29 1 @ 2 0_0402_5% HDD_B0_PRE1 17
RS30 1 @ 2 0_0402_5% HDD_A0_PRE1 19 B_PRE1 15 SATA_ATX_RC_DRX_P0 CS30 1 2 0.01U_0402_16V7K SATA_ATX_RC_DRX_P0_C
A_PRE1 A_OUTp 14 SATA_ATX_RC_DRX_N0 CS32 1 2 0.01U_0402_16V7K SATA_ATX_RC_DRX_N0_C JHDD1 CONN@
pin 17 19 means EQ0 and EQ1 RS20 1 @ 2 0_0402_5% 18 A_OUTn 14
EQ0 and EQ1 set 0dB 3 TEST 11 SATA_ARX_RC_DTX_P0 CS34 1 2 0.01U_0402_16V7K SATA_ARX_RC_DTX_P0_C DEVSLP[0] PU 10K, means not support DEVSLP function 13 GND
RS22 1 TI@ 20_0402_5% HDD_B0_EQ 13 GND B_INp 12 SATA_ARX_RC_DTX_N0 CS31 1 2 0.01U_0402_16V7K SATA_ARX_RC_DTX_N0_C GND
E
21 GND B_INn 12
EPAD +5V_HDD 12
11
SN75LVCP601RTJR_QFN20_4X4 10 11
+5V_HDD Source [10] DEVSLP0_HDD

RS8 1 2 0_0402_5% JHDD_P10
9
8
7
10
9
8
80 mils
D
+3VS SATA_ARX_RC_DTX_P0_C 6 7
SATA_ARX_RC_DTX_N0_C 5 6
+5VS +5V_HDD 4 5
JP13 SATA_ATX_RC_DRX_N0_C 3 4
RS38 1 @ 2 0_0402_5% 1 2 SATA_ATX_RC_DRX_P0_C 2 3
r
1 2 1 2
2 HDD_B0_EQ RS37 1 TI@ 20_0402_5% JUMP_43X79 1 2
ACES_51625-01201-001
DEW2 RS35 1 @ 2 4.7K_0402_5% SP010028W00
SHORT
o
DEW1 RS36 1 @ 2 4.7K_0402_5%
+5V_HDD
f
change to net name 2/4 HDD_B0_PRE0 RS21 1 @ 2 0_0402_5%
HDD_B0_PRE1 RS18 1 TI@ 2 0_0402_5%
1000P_0402_50V7K
0.1U_0402_25V6K
10U_0805_10V6K
HDD_A0_PRE1 RS23 1 TI@ 2 0_0402_5%
l
1 1 1
SATA_ATX_DRX_P0 RS41 1 NRDSA@2 0_0402_5% SATA_TX_P0 CS38 1NRDSA@
2 0.01U_0402_16V7K SATA_ATX_RC_DRX_P0_C HDD_A0_PRE0 RS24 1 @ 2 2K_0402_5%
CS5 CS6 CS7
SATA_ATX_DRX_N0 RS42 1 NRDSA@2 0_0402_5% SATA_TX_N0 CS39 1NRDSA@
2 0.01U_0402_16V7K SATA_ATX_RC_DRX_N0_C HDD_REXT_SATA0 RS31 1 @ 2 5.1K_0402_1%
a
2 2 2
i
SATA_ARX_DTX_P0 RS43 1 NRDSA@2 0_0402_5% SATA_RX_P0 CS40 1NRDSA@
2 0.01U_0402_16V7K SATA_ARX_RC_DTX_P0_C
t
SATA_ARX_DTX_N0 RS44 1 NRDSA@2 0_0402_5% SATA_RX_N0 CS41 1NRDSA@
2 0.01U_0402_16V7K SATA_ARX_RC_DTX_N0_C
r n
3
ODD Power Control
60 mils
SOC TX
SOC RX
n f [10] id
[10] SATA_ATX_DRX_P1
SATA_ATX_DRX_N1
SATA_ATX_DRX_P1
SATA_ATX_DRX_N1
SATA_ARX_DTX_P1
CS8
CS9
1
1
2
2
SATA_ATX_DRX_P1_C
0.01U_0402_16V7K
SATA_ATX_DRX_N1_C
0.01U_0402_16V7K
SATA_ARX_DTX_P1_C
SATA ODD Connector (FFC Type)
SATA_ATX_DRX_P1_C
1
3
JODD1
1 2
CONN@
2
4 SATA_ATX_DRX_P1_C
APU TX
3
o
[10] SATA_ARX_DTX_P1 3 4
CS13 0.01U_0402_16V7K SATA_ATX_DRX_N1_C 5 6 SATA_ATX_DRX_N1_C
SATA_ARX_DTX_N1 1 2 SATA_ARX_DTX_N1_C 7 5 6 8
need short 11/30 [10] SATA_ARX_DTX_N1
CS14 0.01U_0402_16V7K SATA_ARX_DTX_N1_C
SATA_ARX_DTX_P1_C
9
11
7
9
8
10
10
12
SATA_ARX_DTX_N1_C
SATA_ARX_DTX_P1_C APU RX
c
+5VS 13 11 12 14
+5VS_ODD ODD_DETECT# 15 13 14 16 ODD_DETECT#
15 16 T73
JP7 +5VS_ODD
17 18 +5VS_ODD
1 2 19 17 18 20
1 2 19 20
l
21 22
21 22
1000P_0402_50V7K
0.1U_0402_25V6K
10U_0805_10V6K
ODD_DA# 23 24 ODD_DA# T74

JUMP_43X79 23 24
1 1 1
25 26
GNDGND
a
CS10
CS11
CS12
ACES_50673-0120N-001
2 2 2 DC02151119A
m p change conn 11/30
co
4 4

HDD
A B C D E F G H
5 4 3 2 1
Main Func = USB3.0 Port1

+5V_USB_PWR1
JUSB1
Change USB3 port number from CPU change to 10V rate 04/21 USB3TP1_JUSB1_R 9
1 SSTX+
VBUS
10U_0603_10V6M
0.1U_0402_16V7K
USB3TN1_JUSB1_R 8
+5VALW SSTX-
47U_0805_6.3V4Z
47U_0805_6.3V4Z
USB20_JUSB1_P5_R 3
7 D+
1 1 1 GND
1
1 @EMI@ 2 @ USB20_JUSB1_N5_R 2 10
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D- GND
CU11
CU12
CU13
CU14
RU1 0_0402_5% USB3RP1_JUSB1_R 6 11
4 SSRX+ GND 12
1 1
2
GND GND
l
INPAQ HCM1012GD670A05P CU6 CU7 2 2 2 USB3RN1_JUSB1_R 5 13
USB3RN1_JUSB1 3 4 USB3RN1_JUSB1_R SSRX- GND
[10] USB3RN1_JUSB1
D 4.7U_0805_10V4Z 0.1U_0402_16V7K ACON_TARA4-9K1311 D
2 2
n
USB3RP1_JUSB1 2 1 USB3RP1_JUSB1_R
[10] USB3RP1_JUSB1 CONN@
LU1 EMI@
change to SM070004K00 06/3
3
1 @EMI@ 2
RU2 0_0402_5%
3
ESD@
1 @EMI@ 2 +5V_USB_PWR1 AZC199-02SPR7G_SOT23-3
+5VALW EU2602
1
RU3 0_0402_5%
UI5 ESD Follow D3E
1
INPAQ HCM1012GD670A05P_4P 1
L
USB3TN1_JUSB1 2 1 USB3TN1_JUSB1_C 3 4 USB3TN1_JUSB1_R 5 OUT change USB conn 11/12
[10] USB3TN1_JUSB1 IN 2
CU1 0.1U_0402_10V7K
USB_EN# 4 GND
2 1 USB3TP1_JUSB1_C 2 1 [25,27] USB_EN# EN 3
USB3TP1_JUSB1 USB3TP1_JUSB1_R USB_OC0#
[10] USB3TP1_JUSB1 OCB USB_OC0# [9]
CU2 0.1U_0402_10V7K 1
L
LU2 EMI@ SY6288D20AAC_SOT23-5 1 ESD Follow D3E
change to SM070004K00 06/3 CU8 SA00007AO00
0.1U_0402_16V7K
CU9
0.1U_0402_16V7K
1 @EMI@ 2 2
RU4 0_0402_5% 2
E
EU2601
USB3RN1_JUSB1_R 1 1 10 9 USB3RN1_JUSB1_R
change usb2.0 port number
1 @EMI@ 2 USB3RP1_JUSB1_R 2 2 9 8 USB3RP1_JUSB1_R
RU5 0_0402_5%
EMI@ USB3TN1_JUSB1_R 4 4 7 7 USB3TN1_JUSB1_R
D
MCM1012B900F06BP_4P
USB20_JUSB1_P5 3 4 USB20_JUSB1_P5_R USB3TP1_JUSB1_R 5 5 6 6 USB3TP1_JUSB1_R
[10] USB20_JUSB1_P5
3 3
USB20_JUSB1_N5 2 1 USB20_JUSB1_N5_R USB20_JUSB1_N5
r
[10] USB20_JUSB1_N5 8
1
LU3
C RU15 L05ESDL5V0NA-4_SLP2510P8-10-9 C
pin vertical swap 12/14 @ 300_0402_5% ESD@
o
1 @EMI@ 2
RU6 0_0402_5% USB connector1
2
1
f
@
CU10
15P_0402_50V8J
USB20 port1
2 USB30 port1
l
AMD request 5/16
a
Main Func = USB3.0 Port2
1 @EMI@ 2
n t i +5V_USB_PWR1
change to 10V rate 04/21 USB3TP2_JUSB2_R 9

1
JUSB2
SSTX+
VBUS
10U_0603_10V6M
0.1U_0402_16V7K
RU7 0_0402_5% USB3TN2_JUSB2_R 8
SSTX-
47U_0805_6.3V4Z
47U_0805_6.3V4Z
USB20_JUSB2_P6_R 3
r
INPAQ HCM1012GD670A05P 7 D+
1 1 1 GND
1
USB3RN2_JUSB2 3 4 USB3RN2_JUSB2_R @ USB20_JUSB2_N6_R 2 10
[10] USB3RN2_JUSB2 D- GND
CU16
CU17
CU18
CU19
USB3RP2_JUSB2_R 6 11
4 SSRX+ GND 12
id
2
USB3RP2_JUSB2 2 1 USB3RP2_JUSB2_R 2 2 2 USB3RN2_JUSB2_R 5 GND GND 13
[10] USB3RP2_JUSB2 SSRX- GND
LU4 EMI@ ACON_TARA4-9K1311
f
CONN@
1 @EMI@ 2
RU8 0_0402_5%
B B
3
2
3
ESD@
1 @EMI@ 2
RU9 0_0402_5% ESD Follow D3E AZC199-02SPR7G_SOT23-3
o
EU2604
1
change USB conn 11/12
INPAQ HCM1012GD670A05P
1
USB3TN2_JUSB2 2 1 USB3TN2_JUSB2_C 3 4 USB3TN2_JUSB2_R
[10] USB3TN2_JUSB2
CU3 0.1U_0402_10V7K
c
USB3TP2_JUSB2 2 1 USB3TP2_JUSB2_C 2 1 USB3TP2_JUSB2_R
[10] USB3TP2_JUSB2
CU4 0.1U_0402_10V7K
LU5 EMI@
l
1 @EMI@ 2
RU10 0_0402_5%
change usb2.0 port number
pa RU11
1 @EMI@ 2
0_0402_5%
USB20_JUSB2_N6
USB3RN2_JUSB2_R
USB3RP2_JUSB2_R
USB3TN2_JUSB2_R
EU2603
1 1
2 2
4 4
10 9
9 8
7 7
USB3RN2_JUSB2_R
USB3RP2_JUSB2_R
USB3TN2_JUSB2_R
1
EMI@ USB3TP2_JUSB2_R 5 5 6 6 USB3TP2_JUSB2_R

MCM1012B900F06BP_4P RU16
m
USB20_JUSB2_P6 3 4 USB20_JUSB2_P6_R @ 300_0402_5% 3 3
[10] USB20_JUSB2_P6
8
2
USB20_JUSB2_N6 2 1 USB20_JUSB2_N6_R 1 ESD Follow D3E
co
[10] USB20_JUSB2_N6
CU15 L05ESDL5V0NA-4_SLP2510P8-10-9
LU6 @ 15P_0402_50V8J ESD@
pin vertical swap 12/14
2
1 @EMI@ 2
A RU12 0_0402_5%
AMD request 5/16 USB connector2 A
USB20 port2
USB30 port2

USB3.0
A00
5 4 3 2 1
5 4 3 2 1
Main Func = Touch Pad
+3VS_TOUCH
+3VS_TOUCH
Touch pad
change to pop 03/02
* Key Board Back Light
2
Q9
G
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y
1 LN2306LT1G_SOT23-3
1 3 TP_I2C_INT#
[9] TP_I2C_INT#_APU
l
C19
S
+3VS_TOUCH 1U_0402_6.3V6K~D change to SP040002B00 0204
CONN@ 2
D R150 1 @ 2 0_0402_5% D
JTP1 +3VS_TOUCH
n
10 +5VS +5VS_KBL
9 GND
GND
1
8 0.5A_13.2V_MF-NSMF050-2
I2C_DAT_TP 7 8 R41 F3 @
[9] I2C_DAT_TP 6 7
I2C_CLK_TP EC_TP_INT# 1 2 TP_I2C_INT# 1 2
o
100K_0402_5% [27] EC_TP_INT# @
[9] I2C_CLK_TP 5 6 PTP@ 0_0402_5% RE338 20mil
5
1U_0603_10V6K
10U_0603_10V6M
TP_I2C_INT# 4 1 2 change to 10V rate 04/21
2
PTP_DIS# TP_LOCK# 3 4 PTP_DIS#
[27] PTP_DIS# 3 1
1
CE56
C34
TP_DATA 2 RE59
[27] TP_DATA 1 2
TP_CLK KBBL@ 0_0805_5% KBBL@
[27] TP_CLK 1 KBBL@
2
2
L
JXT_FP202DH-008M10M
SP010020L00 +3VS
L
RE68
Close to UE1 [9] KB_DET#
1 2
+3VALW +3VS_TOUCH 10K_0402_5% +5VS_KBL

+3VS_TOUCH Close to UC1
E
JKBBL1
1
TP_CLK 4.7K_0402_5% 1 2 R31 +3VS_TOUCH D 1
TP_DATA 4.7K_0402_5% 1 2 R32 RP20 TP_WAKE@ 2 KB_DET 2 1
I2C_DAT_TP 1 8 R35 G 3 2 5
I2C_CLK_TP 2 7 0_0402_5% QE4 KB_BL_PWM 4 3 G1 6
S
3
4 G2
1
TP_I2C_INT# 3 6 2N7002KW 1N SOT323-3
2
4 5 KBBL@ RE58 ACES_51575-00401-001
100K_0402_5%
2.2K_0804_8P4R_5% +3VS_TOUCH Discharge KBBL@ CONN@
TP_CLK
2
TP_DATA Q12 +3VS_TOUCH
r
@ESD@ C553
@ESD@ C551
NTK3139PT1G_SOT723-3
100P_0402_50V8J
100P_0402_50V8J
1 1
1
D Q8
D
C
3 1 1 2 2 KBBL@ C
[27] KB_LED_PWM
1 G
o
2 2 TP_WAKE@ TP_WAKE@ R38 S
3
C22 100_0603_1% LN2306LT1G_SOT23-3
G
2
1
.1U_0402_16V7K
f
2 D Q85
@EMI@ change to @ESD@ 12/16 1 2 TP_ON#_GATE 2 2N7002K_SOT23-3
[27] TP_EN
G
R39 S
l
20K_0402_1%
3
t ia
Main Func = FAN Control
r n +5VS
id
RE60 JKB1
1 @ 2 30 32
KSI7 29 30 GND 31
f
240_0402_1% KSI6 28 29 GND
KSI4 27 28
KSI2 26 27
KSI5 25 26
B B
n
KSI[0..7] KSI1 24 25
[27] KSI[0..7] 23 24
KSI3
KSO[0..16] KSI0 22 23
[27] KSO[0..16] 21 22
KSO5
21
o
KSO4 20
KSO7 19 20
KSO6 18 19
del fan control ic 12/2 +3VS KSO8 17 18
c
KSO3 16 17
KSO1 15 16
KSO2 14 15
KSO0 13 14
13
1
l
KSO12 12
R28 KSO16 11 12
100K_0402_5% KSO15 10 11
CAP LED Control KSO13 9 10
9
a
+5VS KSO14 8
LOW actived from KBC GPIO Q7
2
8
2
G
KSO9 7
R2
3 KSO11 6 7
3 1 CAP_LED_R# 2 R27 KSO10 5 6
[27] CAPS_LED 5
p
1 CAP_LED_Q 1 2 4
R1
CAP_LED
D
1K_0402_5% 3 4
+3VS +5VS 2 3
Q6 DDTA144VCA-7-F-GP CAPS_LED R36 1 @ 2 0_0402_5% 1 2
LN2306LT1G_SOT23-3 1
change to 10V rate 04/21
1
22U_0805_10V6M
1 STARC_132C30-100020-A2-R
m
R37
10K_0402_5%
10K_0402_5%
10K_0402_5%
CF4
0_0402_5%
2
change to pwm control 12/2

2 @
RF1
RF2
RF3
co
2
1
JFAN1
A
1 A
2 1
[27] FAN_PWM 2 1 3 2
[27] FAN_SPEED1 4 3
DF1
SDMK0340L-7-F_SOD323-2 4
5
6 GND1
GND2
JXT_WB247H-004S10M
CONN@
SP020017K10 Security Classification Compal Secret Data Compal Electronics, Inc.
FAN / TP / PWR SW / KBBL
A00
5 4 3 2 1
5 4 3 2 1
Main Func = IO Connector
RU18
1 @EMI@ 2
0_0402_5%
IO to MB CONN
EMI@
MCM1012B900F06BP_4P
Vinafix.com
y
USB20_CR_P0 3 4 USB20_CR_P0_R
[10] USB20_CR_P0
l
D D
USB20_CR_N0 2 1 USB20_CR_N0_R
[10] USB20_CR_N0
I/O Board Connector
n
LU8 change conn 11/13
+5VALW
o
1 @EMI@ 2 CONN@
RU17 0_0402_5% JIOB1
CU20
1 1
CU21
USB2.0 1
2 1
2
USB20_CR_N0_R 3
L
4.7U_0805_10V4Z
2 2
0.1U_0402_16V7K CardReader USB20_CR_P0_R 4
5
3
4
5
6
6
L
USB20_JUSB1_P3_R 7
USB20_JUSB1_N3_R 8 7
9 8
10 9
10
E
+5V_USB_PWR2 11
+5VALW 12 11
+3VS 12
UU3 +5V_USB_PWR2 13
1 14 13
5 OUT 15 14
D
IN 2 16 15
C GND 16 C
USB_EN# 4
[23,27] USB_EN# EN 3 USB_OC1# 17
USB_OC1# [9]
r
OCB 18 GND
1 GND
CU22 SY6288D20AAC_SOT23-5 1
SA00007AO00 CU23 ACES_51524-0160N-001
o
0.1U_0402_16V7K
2 0.1U_0402_16V7K
f
2
l
change conn 12/3
RU13
1 @EMI@ 2
LU7
0_0402_5%
t ia
n
USB20_JUSB1_P3 2 1 USB20_JUSB1_P3_R
[10] USB20_JUSB1_P3
r
USB20_JUSB1_N3 3 4 USB20_JUSB1_N3_R
[10] USB20_JUSB1_N3
B B
id
MCM1012B900F06BP_4P
EMI@
1 @EMI@ 2
f
RU14 0_0402_5%
n
2
choke Follow D3E
o
2
ESD@
AZC199-02SPR7G_SOT23-3
c
DU1
1
1
a l
A
m p Security Classification
Issued Date 2016/01/07
Compal Secret Data
Deciphered Date 2017/01/07 Title
A
co
IO-DB
B A00
5 4 3 2 1
A B C D E
Main Func = DC Interface

+5VS and +3VS switch +3VS to +3VGS
+1.8V_ALW to +1.8VS
SHORT 2000mA
Vinafix.com
y
DIS@
Max:7.0A
l
J509 @ U15 J11
2 1 1 14 0.95VSDGPU_OUT 1 2
+5VALW 2 1 +0.95VALW VIN1 VOUT1 1 2 +0.95VSDGPU
1
short change 0 ohm 12/17 +5VS 2 13 1 1
JUMP_43X118 R438 change to 47K 03/18 VIN1 VOUT1 C343 C625 JUMP_43X118
C2309
n
0.01U_0603_25V7K PXS_PWREN DIS@ 1 2 47K_0402_5% 0.95VSDGPU_ON 3 12 DIS@
1 2 1000P_0402_50V7K 0.1U_0402_10V6K
1 2 [9,52] PXS_PWREN ON1 CT1
U2301 J510 DIS@ add 0.1U 03/22
1 14 5VS 2 1 change to 10V rate 04/21 1
DIS@ 2 4 11 2
VIN1 VOUT1 2 1 +5VALW VBIAS GND
2 13 R440 C983 0.1U_0402_10V6K C344 330p change to 1000P 5/31
VIN1 VOUT1
C2307
10U_0805_10V4Z
C2308
10U_0603_10V6M
PXS_PWREN DIS@ 1 2 47K_0402_5% 1.8VSDGPU_ON 5 10 1 2
o
R2313 0_0402_5% JUMP_43X79
SUSP# 1 2 5VS_GATE 3 12 1 2 @ ON2 CT2 DIS@ 1000P_0402_50V7K
[27,44,46] SUSP# ON1 CT1 1 20mil(0.5A)
1
C5216 470P_0402_50V7K 1
DIS@ 2 6 9
+1.8V_ALW VIN2 VOUT2 +1.8VGS
4 11 C624 0.1U_0402_10V6K 7 8
10mil VBIAS GND @ 1
VIN2 VOUT2
1
2
5 10 2 modify for 1.8vgs sequence 2/4 C623 15 C622
ON2 CT2 0.1U_0402_10V6K GPAD 0.1U_0402_10V6K change to 0.1u 0402 1/13
6 9 @ EM5209VF DFN 14P DUAL LOAD SW DIS@
L
7 VIN2 VOUT2 8 2 2
VIN2 VOUT2 SA00007PM00
15
GPAD
EM5209VF DFN 14P DUAL LOAD SW
L
+3VS +3VGS
SA00007PM00
@ JP2
2 1
2 1
JUMP_43X39
E
DIS@
U74
5 1
IN OUT
2 +3VS
D
GND DIS@
PXS_PWREN 4 3 2 1
EN OC
+5VALW +3VALW
Max:5.07A +3VS 2
SY6288C20AAC_SOT23-5
R439 10K_0402_5% 2
4.7U_0603_6.3V6K
2
C620
C2322 0.01U_0603_25V7K J511 C621
1U_0402_6.3V6K
1 2 2 1
C626
U2302 3VS DIS@ 1U_0402_6.3V6K
1 14 2 1 1 1
2 VIN1 VOUT1 1 DIS@ 2
C2324
10U_0603_6.3V6M
C2323
10U_0603_6.3V6M
2 13 JUMP_43X118
10mil @
o
R2318 0_0402_5% VIN1 VOUT1 @ change to 1U 1/13
1 1
SUSP# 1 2 3VS_GATE 3 12 1 2 del susp and syson circuit 12/17
ON1 CT1 C5219 470P_0402_50V7K change to SA000079400 12/22
SHORT
f
4 11 @
1K_0402_5% VBIAS GND 2 2
SUSP# R437 1 2 +0.95VALW_ON 5 10 2 1
ON2 CT2 C349 330P_0402_50V7K +1.8VS
+1.8V_ALW
l
1 2 6 9 J10
C987 0.1U_0402_16V7K 1 2 7 VIN2 VOUT2 8 +1.8VS_LS 1 2
C24 @ VIN2 VOUT2 1 2
2
1U_0402_6.3V6K 15 JUMP_43X79
a
GPAD C26 del u75 12/18
EM5209VF DFN 14P DUAL LOAD SW .1U_0402_16V7K
1 1500mA
i
SA00007PM00
r n t +APU_CORE_NB
+5VALW
2
R56
id
+5VALW 1K_0402_5%
8
U2A
3 LM393DR_SO8
1
+
2
1 CORE_NB_GATE
+3VALW R2635 +0.775VALW +0.775MOS 2 O
f
-
G
100K_0402_5% +5VALW
4
2
6
+0.95VALW U4 +0.95VS
1
2
D
3 AO4354_SO8 R2634 G
3
n
+3VALW +5VALW 8 1 100K_0402_5% Q2516B S
2
1 7 2 DMN66D0LDW-7_SOT363-6
1
3
4.7U_0603_6.3V6K
C939
1U_0402_6.3V6K
C46
C940 6 3 1 1 +0.775MOS R54
1
5 5
D
4.7U_0603_6.3V6K S5_MUX_CTRL G
1K_0402_5%
[9] S5_MUX_CTRL
8
o
Q2516A S U2B
change to 10V rate 04/21 2 DMN66D0LDW-7_SOT363-6 R2636 5 LM393DR_SO8
P
4
1
2 @2 +
C2316
10U_0603_6.3V6M
C2318
10U_0603_6.3V6M
C2306
10U_0603_10V6M
C2305
10U_0603_10V6M
100K_0402_5% 7 0.775VALW_GATE
6 O
1 1
c
-
G
1
1
+5VALW
4
2
2 2 1 2 0.95VS_GATE
l
R1674 1
4.7K_0402_5% C16
1
.1U_0402_16V7K
D
a
2 2 +0.95VS
[27] 0.95VS_PWR_EN#
G
S Q84
2N7002K_SOT23-3 Q135 Q2513
3
+APU_CORE_NB AO3416L_SOT23-3 +VDDCR_FCH_ALW
p
AO3416L_SOT23-3
R1671 @
D
470_0603_5% 1 3 3 1
22U_0603_6.3V6M
22U_0603_6.3V6M
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
1 1 1
C2621
C2620
C2618
1 2
C432
C431
4.7U_0603_6.3V6K
G
G
2
2
CORE_NB_GATE
2
D Q83 @ del reserve circuit 12/2 2 2 2
0.95VS_PWR_EN# 2 2N7002K_SOT23-3
G Q2515 Q2514
S +0.775VALW AO3416L_SOT23-3 AO3416L_SOT23-3
co
3
D
1 3 3 1
S
1 1
C2619 C2622
4.7U_0603_6.3V6K 4.7U_0603_6.3V6K
G
G
2
2
4 0.775VALW_GATE 4
2 2

DC/DC Interface
A00
A B C D E
5 4 3 2 1
Main Func = KBC +RTC_APU_R Board IDAnalog Board ID definition,

Please see page 4.
1
D Q91 +3VALW
RTC_DIS 2 2N7002K_SOT23-3
G
2
Project ID S
RE20
3
+3VALW R1563 DVT1 use 100K_0402_1%
+EC_VCCA
Ra
100K_0402_5% RE22
+3VALW +3VALW_EC LE3 @
Vinafix.com
1
2
FBMA-L11-160808-800LMT_0603 AD_BID0
RE23 1 2 0.1U_0402_16V7K 0.1U_0402_16V7K +3VALW_EC 1 2 +EC_VCCA
2
Rc @ 100K_0402_1% RE13 0_0805_5% 1 1 1 1 2 2 1 @ 1
+3VLP CE17 CE3 CE4 CE14 CE13 CE10@ 0.1U_0402_16V7K RE22 CE39
D 1 @ @ CE21 12K_0402 +-1% Rb 0_0402_1% D
PID0 1 2 1000P_0402_50V7K
2 2 2 2 1 1 2 ECAGND 2
n
change to unpop 03/22 RE4 0_0805_5% SD034120280 EVT use
1
ECAGND [41]
2
@ 1@ 0.1U_0402_16V7K 0.1U_0402_16V7K 1000P_0402_50V7K 0.1U_0402_16V7K

RE24 CE47
Rd 0_0402_1% 2 1 +3VLP
o
RE14 0_0402_5%
2 DVT2 use XB use
1
111
125
0.1U_0402_16V7K Reserved for KB9012 RE22 @ RE22
22
33
96
67
UE1
VCC0
VCC_LPC
VCC
VCC
VCC
VCC
AVCC
change net name and pin location
L
GATEA20 1 21 BATT_CHG_LED# 15K_0402_1% 20K_0402_1%
[9] GATEA20 2 GATEA20/GPIO00 EC_VCCST_PG/GPIO0F 23 BATT_CHG_LED# [29]
KB_RST# BEEP#
[9] KB_RST# 3 KBRST#/GPIO01 BEEP#/GPIO10 26 BEEP# [18]
SERIRQ FAN_PWM SD034150280 SD034200280
[10] SERIRQ 4 SERIRQ EC_FAN_PWM/GPIO12 27 FAN_PWM [24]
LPC_FRAME# PWM Output ACOFF
+3VALW [9,10] LPC_FRAME# 5 LPC_FRAME# AC_OFF/GPIO13 ACOFF [42] 2 1
CE24 LPC_AD3 ECAGND
L
[10] LPC_AD3 7 LPC_AD3
@EMI@ 22P_0402_50V8J @EMI@ LPC_AD2 CE43 100P_0402_50V8J
2 1 [10] LPC_AD2 LPC_AD2
RE16 2 1 33_0402_5% LPC_AD1 8 63 BATT_TEMP
1 2 [10] LPC_AD1 10 LPC_AD1 VCIN1_BATT_TEMP/AD0/GPIO38 64 BATT_TEMP [41,42]
KSO1 LPC_AD0 LPC & MISC delete VCIN1_BATT_DROP 11/25
[10] LPC_AD0 LPC_AD0 VCIN1_BATT_DROP/AD1/GPIO39 65
RE62 @ 47K_0402_5% ADP_I
12 ADP_I/AD2/GPIO3A 66 ADP_I [42]
AD Input AD_BID0
E
1 2 [9,10] LPC_CLK0_EC 13 CLK_PCI_EC AD_BID/AD3/GPIO3B 75
KSO2 BATT_I
2 1 [9,19,20] PLT_RST# 37 PCIRST#/GPIO05 AD4/GPIO42 76 BATT_I [42]
RE63 @ 47K_0402_5% CE23 0.1U_0402_16V7K EC_RST# PANEL_BKLEN +5VALW
20 EC_RST# AD5/GPIO43 PANEL_BKLEN [8]
EC_SCI#
1 2 [9] EC_SCI# 38 EC_SCI#/GPIO0E
LID_SW# ESD@ PTP_DIS#_R
RE75 10K_0402_5% CLKRUN#/GPIO1D
change to pop 0503 68 GPU_AC_LIGHT USB_EN# RE504 1 2 10K_0402_5%
D
1 2 WLAN_WAKE# DA0/GPIO3C 70 del EN_DFAN1 12/03
DA Output EN_DFAN1/DA1/GPIO3D
RE70 10K_0402_5% RE5 0_0402_5% KSI0 55 71 EC_ENVDD
1 2 56 KSI0/GPIO30 DA2/GPIO3E 72 EC_ENVDD [16]
PTP_DIS# @ PTP_DIS#_R KSI1
1 2 [24] PTP_DIS# 57 KSI1/GPIO31 DA3/GPIO3F LCD_TEST [16]
@ EC_SMI# KSI2 CE40 100P_0402_50V8J
RE19 1K_0402_1% KSI3 58 KSI2/GPIO32 83 EC_MUTE# ACIN 2 1
r
59 KSI3/GPIO33 EC_MUTE#/PSCLK1/GPIO4A 84 EC_MUTE# [18]
KSI4 USB_EN#
1 2 60 KSI4/GPIO34 USB_EN#/PSDAT1/GPIO4B 85 USB_EN# [23,25]
EC_PME# KSI5
RE21 10K_0402_5% KSI[0..7] KSI6 61 KSI5/GPIO35 PSCLK2/GPIO4C 86
C [24] KSI[0..7] KSI6/GPIO36 PS2 Interface PSDAT2/GPIO4D C
KSI7 62 87 TP_CLK
TP_CLK [24]
o
1 2 EC_SCI# KSO[0..16] KSO0 39 KSI7/GPIO37 TP_CLK/GPIO4E 88 TP_DATA
[24] KSO[0..16] 40 KSO0/GPIO20 TP_DATA/GPIO4F TP_DATA [24]
RE61 10K_0402_5% KSO1
KSO2 41 KSO1/GPIO21 EC_LID_OUT# 1 2 EMI@
f
+3VS KSO3 42 KSO2/GPIO22 97 PID0 CE42 1000P_0402_50V7K
KSO4 43 KSO3/GPIO23 ENKBL/GPXIOA00 98 WOL_EN
44 KSO4/GPIO24 WOL_EN/GPXIOA01 99 WOL_EN [19] WOL_EN (Hi Active) 1 2 EMI@
PM_SLP_S5# PM_SLP_S3# KSO5 0.95VS_PWR_EN# EC_RSMRST#
1 @ 2 EC_SCI# KSO6 45 KSO5/GPIO25 Int. K/B ME_EN/GPXIOA02 109 0.95VS_PWR_EN# [26]
CE41 1000P_0402_50V7K
KSO6/GPIO26 Matrix VCIN0_PH1/GPXIOD00 VCIN0_PH [41]
l
RE66 10K_0402_5% 1 @EMI@ 1 @EMI@ KSO7 46
CE33 CE25 KSO8 47 KSO7/GPIO27
KSO8/GPIO28 SPI Device Interface
KSO9 48 119
KSO10 49 KSO9/GPIO29 MISO/GPIO5B 120
a
2 2 KSO11 50 KSO10/GPIO2A MOSI/GPIO5C 126
KSO11/GPIO2B SPI Flash ROM SPICLK/GPIO58
0.1U_0402_16V7K 0.1U_0402_16V7K KSO12 51 128 del spi signal 11/18
KSO12/GPIO2C SPICS#/GPIO5A
i
KSO13 52 For share ROM reserve
KSO14 53 KSO13/GPIO2D
KSO15 54 KSO14/GPIO2E 73 ERP_LOT6 EC_RSMRST# 1 2
ESD Request at SSI @
t
81 KSO15/GPIO2F EC_CIR_RX/AD6/GPIO40 74 ERP_LOT6 [41]
KSO16 VGATE VGATE [9,48,49] 4.7K_0402_5% RE48
TP_EN 82 KSO16/GPIO48 SYS_PWROK/AD7/GPIO41 89 DBC_EN
+3VALW [24] TP_EN KSO17/GPIO49 GPIO50 90 DBC_EN [16]
WLAN_WAKE# add pwr _led# 0.95_1.8VALW_PWREN1 @ 2
+3VS BATT_CHG_LED#/GPIO52 91 WLAN_WAKE# [20]
CAPS_LED 4.7K_0402_5% RE46
n
CAPS_LED#/GPIO53 CAPS_LED [24]
RPE1 EC_SMB_CK1 0_0402_5% 1 @ 2 RE31 EC_SMB_CK1_R 77 GPIO 92 PWR_LED#
1 8 [41,42] EC_SMB_CK1 EC_SMB_CLK1/GPIO44 PWR_LED#/GPIO54 PWR_LED# [29]
EC_SMB_DA1_R CHARGER EC_SMB_DA1 0_0402_5% 1 @ 2 RE32 EC_SMB_DA1_R 78 93 BATT_LOW_LED#
2 7 [41,42] EC_SMB_DA1 EC_SMB_DAT1/GPIO45 BATT_LOW_LED#/GPIO55 BATT_LOW_LED# [29]
EC_SMB_CK1_R EC_SMB_CK2 0_0402_5% 1 @ 2 RE33 EC_SMB_CK2_R 79 95 SYSON
r
3 6 [8,28,34] EC_SMB_CK2 EC_SMB_CLK2/GPIO46 SYSON/GPIO56 SYSON [44,45] +3VALW_EC
EC_SMB_DA2_R APU, GPU, Thermal EC_SMB_DA2 0_0402_5% 1 @ 2 RE34 EC_SMB_DA2_R 80 121 VR_ON
4 5 [8,28,34] EC_SMB_DA2 EC_SMB_DAT2/GPIO47 VR_ON/GPIO57 127 VR_ON [48,49]
EC_SMB_CK2_R 0.95_1.8VALW_PWREN
DPWROK_EC/GPIO59 0.95_1.8VALW_PWREN [45,47] 3.3V Due EC require 12/21
SM Bus
2.2K_0804_8P4R_5%
id
0_0402_5% 1 @ 2 RE37 PM_SLP_S3#_R 6 100 EC_RSMRST# 0.95VS_PWR_EN# RE505 1 2 10K_0402_5%
[9] PM_SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 EC_RSMRST# [9]
0_0402_5% 1 @ 2 RE38 PM_SLP_S5#_R 14 101 EC_LID_OUT#_R RE442 1
@ 0_0402_5%
[9,42] PM_SLP_S5# 1 2RE40 15 GPIO07 GPXIOA04 102 EC_LID_OUT# [9]
0_0402_5% @ EC_SMI#_R del VCIN1_PH 11/18
[9] EC_SMI# 16 GPIO08 VCIN1_ADP_PROCHOT/GPXIOA05 103 VCOUT1_PH delete off-page 11/25
[41] PS_ID 17 GPIO0A VCOUT1_PROCHOT#/GPXIOA06 104 1 2
0.775PW_EN VCOUT0 @
f
[50] 0.775PW_EN 18 GPIO0B VCOUT0_MAIN_PWR_ON/GPXIOA07 105 VCOUT0_PH# [28,43]
DEL GPIO0B(CE_EN) BKOFF# RE39 0_0402_5%
[51,52] DGPU_PWROK 19 GPIO0C BKOFF#/GPXIOA08 106 BKOFF# [16]
del TS_EN 12/03 GPIO GPO EC_TP_INT#
25 AC_PRESENT/GPIO0D GPXIOA09 107 EC_TP_INT# [24]
KB_LED_PWM del AD_I_HW2 11/18 Delay SUSP# 10ms
[24] KB_LED_PWM 28 PWM2/GPIO11 PCH_PWR_EN/GPXIOA10 108 1 2
B FAN_SPEED1 GPU_AC_LIGHT @ B
ACIN_65W [34]
n
1 [24]
2 FAN_SPEED1 EC_PME# 29 FAN_SPEED1/GPIO14 PWR_VCCST_PG/GPXIOA11
[9,19] APU_PCIE_WAKE# FANFB1/GPIO15
1.8VS RE51 0_0402_5%
0_0402_5% RE41 EC_TX 30
[20] EC_TX 31 EC_TX/GPIO16 110
EC_RX ACIN change to pop 12/9
[20] EC_RX 32 EC_RX/GPIO17 VCIN1_AC_IN/GPXIOD01 112 ACIN [34,41,42]
APU_FCH_POK EC_ON
[9] APU_FCH_POK PCH_PWROK/GPIO18 EC_ON/GPXIOD02 EC_ON [43]
[41,43] POK
o
34 114 ON/OFF#
RTC_DIS 36 SUSP_LED#/GPIO19 ON/OFF#/GPXIOD03 115 LID_SW# ON/OFF# [29]
NUM_LED#/GPIO1A GPI LID_SW#/GPXIOD04 LID_SW# [29]
116 SUSP# 0_0402_5%
SUSP#/GPXIOD05 117 SUSP# [26,44,46] 2 1
RD15 SATA_LED#_R
c
GPXIOD06 118 SATA_LED#_R [29]
PECI/GPXIOD07
1.8VS
change to fan_fb 12/2 PBTN_OUT# 122 @
[9] PBTN_OUT# 123 PBTN_OUT#/GPIO5D 124 2 1 1 2RE43
+V18R +1.8V_ALW SATA_ACT#_RR 0_0402_5% SATA_ACT# SATA_ACT# [10,29]
PM_SLP_S4#/GPIO5E AGND V18R/VCC_IO2 RE69 @ 0_0402_5%
l
GND
GND
GND
GND
GND
1 @ 2
+3VALW_EC
RE50 0_0402_5%
11
24
35
94
113
69
a
KB9022QD_LQFP128_14X14
20mil
LE4 del VCIN1_PH pull up resistor 11/18
ECAGND 2 1
FBMA-L11-160808-800LMT_0603
m p delete off-page 11/25
co
VCOUT1_PH 1 @ 2 H_PROCHOT#
H_PROCHOT# [8,9,41,42,48,49]
0_0402_5% RE42
D4
LID_SW# 1 2 TS_EN_R
TS_EN_R [16]
A RB751V-40_SOD323-2 A
change to compal symbol
del ce37 12/03

EC ENE-KB9012A4/KB9022QC
A00
5 4 3 2 1
5 4 3 2 1
Main Func = Thermal Sensor
Vinafix.com
D
Fintek thermal sensor
placed near by TOP DDR4
+3VS +3VS
n l y D
1
R2448
U2407 10K_0402_5%
L
@
2
1 10 EC_SMB_CK2
VDD SMCLK EC_SMB_CK2 [8,27,34]
L
REMOTE1+ 2 9 EC_SMB_DA2
DP1 SMDATA EC_SMB_DA2 [8,27,34]
1
C2498 REMOTE1- 3 8
DN1 ALERT#
E
0.1U_0402_10V6K
REMOTE2+ 4 7 R2450 1 @ 2
2 DP2/DN3 THERM# VCOUT0_PH# [27,43]
0_0402_5%
REMOTE2- 5 6
DN2/DP3 GND
C
F75303M_MSOP10
Address 1001_101xb
SA000046C00
r D C
Close U2407 REMOTE1+ BOTTOM DDR4
l f o REMOTE1,2 (+/-) :
Trace width/space:10/10 mil
a Trace length:<8"
1
REMOTE1+ C
i
1 @ C2500 2 Q2407
t
2200P_0402_25V7K B MMBT3904WH_SOT323-3
2
C2502 E
3
2200P_0402_25V7K REMOTE1-
2
n
REMOTE1-
r
REMOTE2+
B 1 BOTTOM CPU B
id
REMOTE2+
C2504
1
2200P_0402_25V7K C
2 REMOTE2- @ C2505 2 Q2408
f
2200P_0402_25V7K 2 B MMBT3904WH_SOT323-3
E
3
REMOTE2-
o n
l c
A
pa A
m
co
Thermal Sensor
5 4 3 2 1
5 4 3 2 1
Main Func = POWER BTN

+5VALW Power button
For ESD Reserved
Vinafix.com
y
CONN@ ESD@
1
LID_SW# EC2902 1 2 .1U_0402_16V7K
l
JPWR1
D R53 D
100K_0402_5% 6 8
WHITE_LED_PWR 5 6 G2 7
n
+5VALW NC 03/21 4 5 G1
LOW actived from KBC GPIO Q15
2
4
2
G
ON/OFF# 3
R2
3 LID_SW# 2 3
o
[27] LID_SW# 2
3 1 PWR_LED_R# 2 1
[27] PWR_LED# R1 +3VALW 1
1 WHITE_LED_PWR
D
JXT_FP226H-006S1BM
Q16 DDTA144VCA-7-F-GP
L
LN2306LT1G_SOT23-3
Pop only before MP
ON/OFF switch
E L
C
+5VALW
r D TOP Side
SW1
+3VLP
C
RE49 100K_0402_5%
1 2
Main Func = Battery BTN
1
f
S TACT SW TST71A-N-220-S017 SPST H0
2
+5VALW
a
ON/OFF# [27]
Q3
CE20 0.1U_0402_16V7K
1 ESD@
i
1
1
1000P_0402_50V7K
R2
3
EC2901
t
[27] BATT_LOW_LED# BATT_LOW_LED# 1 6BATT_LOW_LED_R# 2 ED2901
R1
1 BATT_LOW_LED
Q2A 2 2 AZ5725-01F_DFN2
Low actived from KBC GPIO
n
DMN66D0LDW-7_SOT363-6 BOT Side @ESD@
DDTA144VCA-7-F-GP
SW2
2
r
+5VALW
1 2
B
Low actived from KBC GPIO Q6102 B
5
id
R2
3
[27] BATT_CHG_LED# BATT_CHG_LED# 4 3BATT_CHG_LED_R# 2
R1
1 BATT_CHG_LED S TACT SW TST71A-N-220-S017 SPST H0
SATA HDD LED
f
Q2B
LOW actived from PCH GPIO DMN66D0LDW-7_SOT363-6
DDTA144VCA-7-F-GP @
n
+3VS
o
pin change 12/15 JLED1 CONN@
1
BATT_LOW_LED 2 1
c
BATT_CHG_LED 3 2
3
2
4
R23 4
l
10K_0402_5% 5
6 GND
GND
a
1
ACES_51524-0040N-001
[27] SATA_LED#_R SATA_LED#_R SP010022M00
p A
2
2N7002KW_SOT323-3
G
m
SATA_ACT# 3 1 BATT_CHG_LED_R#
[10,27] SATA_ACT# Issued Date 2016/01/07 Deciphered Date 2017/01/07 Title
S
co
Q5 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LED/PWR-DB
5 4 3 2 1
5 4 3 2 1
Main Func = Screw Hole

Follow EMC require add cap around +19VB 11/25
need to place separately
ZZZ ZZZ2 TRiPOD +19VB

Part Number Part Number
Vinafix.com
y
Description Description change to 25V rate 04/21
l
DAZ1PK00100 PCB BAL22 LA-D803P LS-D802P/D803P/D806P/D807P/D809P DAZ1PK00102 PCB BAL22 LA-D803P LS-D802P-3P/D806P-7P/D809P TRIPOD A31 !
@EMI@ C35
@EMI@ C36
@EMI@ C37
@EMI@ C38
@EMI@ C39
@EMI@ C40
PCB_R1@ PCB_R3T@ 1 1 1 1 1 1
D D
GCE HANNSTAR
n
ZZZ1 ZZZ3
2 2 2 2 2 2
Part Number Description Part Number Description
o
DAZ1PK00101 PCB BAL22 LA-D803P LS-D802P-3P/D806P/D807P/D809P GOLD A31 ! DAZ1PK00103 PCB BAL22 LA-D803P LS-D802P-3P/D806P-7P/9P HANNSTARB A31 !
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
PCB_R3G@ PCB_R3H@
H1 H2 H3 H4 H5
enlarge hole 04/23
H6 H7 1 1 1 1
L 1 1 1
L 1
@EMI@ C41 1000P_0402_50V7K
@EMI@ C42 1000P_0402_50V7K
@EMI@ C43 1000P_0402_50V7K
@EMI@ C44 1000P_0402_50V7K
@EMI@ C45 1000P_0402_50V7K
@EMI@ C47 1000P_0402_50V7K
@EMI@ C48 1000P_0402_50V7K
@EMI@ C49 1000P_0402_50V7K

HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA follow EMI require 12/15
@
CLIP1
E
1 2 2 2 2 2 2 2 2
1
1
1
EMIST_SQ-55G_1P
H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_5P6N H_3P0N
D
@
H8 H9 H10 H11 H12 H13 CLIP2
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA 1
1
r
EMIST_SQ-55G_1P
1
1
C C
o
H_3P5 H_3P5 H_3P5 H_3P2 H_3P2X2P6 H_6P0
HCPU1
HOLEA
HCPU2
HOLEA
HCPU3
HOLEA
HCPU4
HOLEA
l f
ia
1
H_3P7X4P3H_3P9 H_3P7 H_3P7X4P3
r n t
B
n f id B
FD1 FD2 FD3 FD4
c o
l
@ FIDUCAL @ FIDUCIAL @ FIDUCAL @ FIDUCIAL
del FD5 FD6 12/1
a
1
m p
co
A A

Screw Hole
Size
A00
5 4 3 2 1
5 4 3 2 1
SSID1 = TPM2.0
Vinafix.com
D
n l y D
L o
E L
C
r D C
l f o
t ia
rn
B
n fid B
c o
a l
m p
A
co Security Classification
Issued Date
Compal Secret Data
TPM
A
Custom A00
Date: Sheet 31 of 56
5 4 3 2 1
5 4 3 2 1
2016/02/24 Boot Enter S3 S3 Resume Shut Down

ACIN
EC Pin 110 Intput
EC_ON
EC Pin 112 Output
Vinafix.com
y
+5VALW 6.645ms
l
6.769ms
AC Plug +3VALW
D D
7.541ms
POK
EC Pin 34 Input
n
0.95_1.8VALW_PWREN
EC Pin 127 Output 71.34ms
o
+1.8V_ALW 72.20ms
0.95VALW 72.20ms
72.20ms
L
0.95VALW_POK
EC Pin 114 Intput ON/OFF

42.71ms rising time:37.46ns
L
EC Pin 100 Output EC_RSMRST#
16.16ms
RTC_CLK
E
95.60ms
EC Pin 122 Output PBTN_OUT#
PM_SLP_S5#
EC Pin 14 Intput 138.9ms
C
EC Pin 6 Intput
EC Pin 95 Output
PM_SLP_S3#
SYSON
139ms
640 us
r D 197.2ms
C
o
2.364ms
+1.2V_DDR
-39.89ms
EC Pin 116 Output 20 ms
f
SUSP#
EC Pin 99 Output 0.95VS_PWR_EN#
l
1 ms 893.8us 491.7us 769.7us
+5VS
a
768 us 1.375ms 376.2us 1.615ms
+3VS
i
220.5 µs 112us 264.6us
+1.8VS 287.4us
t
3.92 ms
+1.5VS 645.4ms 1.665ms 680.4us
n
700 µs 398.9us 249.9us
449.5us
+0.95VS
r
4.5 us 569.2µs 463.3us
3.96µs
0.6VS
121.0 ms
id
39.65ms 39.92ms
EC Pin 121 Output VR_ON
118.6ms
6.21 ms 120 ms 6.216ms 79.4ms

+APU_CORE
f
6.205 ms 207.8us 6.211ms
+APU_CORE_NB 290.5us
B 6.34 ms B
256.1us
n
6.302ms 400ns
EC Pin 74 Intput VGATE
BC9 138 ms rising time:31.49ns
39.48ms
139.3ms 39.48ms
(APU Intput) EC Pin 32 Output APU_FCH_POK
o
14.2ms 122ms 14.8ms 114.5ms
(APU Output) EC Pin 108 Input APU_PWRGD C19
c
14.8 ms 123.1ms 15.8ms 119.2ms
388ms 65.2ms
(APU Output) EC Pin 13 Intput PLT_RST#
15.79 ms 119.7ms 119ms
l
67.2ms 15.79ms
AN7 386ms
(APU Output) APU_PCIE_RST#
21.51 ms 116.5ms 21.5ms 120.3ms
D15 69.4ms
380.4ms
a
(APU Output) APU_RST#
EC Pin 118 Intput
(APU Output)
(APU Output)
m p
PXS_RST#
PXS_PWREN
1.24s
868.5 ms
2.237ms
153.1 ms
12.89 ms
555.7 ms
2.245 ms
155.2 ms
12.28 ms
co
+3VGS
190.3us 16.41 ms 176 us 15.90 ms

+1.8VGS
A <20ms A
6.013ms 6.177ms
6.010 ms 5.144 ms
+VGA_CORE
7.395ms 43.76ms
6.619ms 43.47ms
+1.35V_MEM_GFX

S5_MUX_CTRL
5 4 3 2 1
1 2 3 4 5
PEG_HTX_C_GRX_P[0..3]
[6] PEG_HTX_C_GRX_P[0..3]
PEG_HTX_C_GRX_N[0..3] No Use GPU Display Port outpud
[6] PEG_HTX_C_GRX_N[0..3]
PEG_GTX_C_HRX_P[0..3] @
[6] PEG_GTX_C_HRX_P[0..3]
UV1F
PEG_GTX_C_HRX_N[0..3] +VGA_CORE_M70
[6] PEG_GTX_C_HRX_N[0..3]
Vinafix.com
y
@ AB11
UV1A VARY_BL AB12
DIGON
l
place near UC1 12/08
A A
n
AL15
TXCAP_DPA3P AK14
PEG_HTX_C_GRX_P0 DIS@ 1 2CV312 0.22U_0402_16V7K PEG_HTX_GRX_P0 AF30 AH30 PEG_GTX_HRX_P0 DIS@ 1 2CV1 0.22U_0402_16V7K PEG_GTX_C_HRX_P0 TXCAM_DPA3N
PEG_HTX_C_GRX_N0 DIS@ 1 2CV306 0.22U_0402_16V7K PEG_HTX_GRX_N0 AE31 PCIE_RX0P PCIE_TX0P AG31 PEG_GTX_HRX_N0 DIS@ 1 2CV2 0.22U_0402_16V7K PEG_GTX_C_HRX_N0 AH16
PCIE_RX0N PCIE_TX0N TX0P_DPA2P
o
AJ15
TX0M_DPA2N
PEG_HTX_C_GRX_P1 DIS@ 1 2CV308 0.22U_0402_16V7K PEG_HTX_GRX_P1 AE29 AG29 PEG_GTX_HRX_P1 DIS@ 1 2CV3 0.22U_0402_16V7K PEG_GTX_C_HRX_P1 AL17
PEG_HTX_C_GRX_N1 DIS@ 1 2CV305 0.22U_0402_16V7K PEG_HTX_GRX_N1 AD28 PCIE_RX1P PCIE_TX1P AF28 PEG_GTX_HRX_N1 DIS@ 1 2CV4 0.22U_0402_16V7K PEG_GTX_C_HRX_N1 TX1P_DPA1P AK16
PCIE_RX1N PCIE_TX1N TX1M_DPA1N
AH18
PEG_HTX_C_GRX_P2 DIS@ 1 2CV307 0.22U_0402_16V7K PEG_HTX_GRX_P2 AD30 AF27 PEG_GTX_HRX_P2 DIS@ 1 2CV5 0.22U_0402_16V7K PEG_GTX_C_HRX_P2 TX2P_DPA0P AJ17
L
PEG_HTX_C_GRX_N2 DIS@ 1 2CV309 0.22U_0402_16V7K PEG_HTX_GRX_N2 AC31 PCIE_RX2P PCIE_TX2P AF26 PEG_GTX_HRX_N2 DIS@ 1 2CV6 0.22U_0402_16V7K PEG_GTX_C_HRX_N2 TX2M_DPA0N
PCIE_RX2N PCIE_TX2N AL19
NC_TXOUT_L3P AK18
PEG_HTX_C_GRX_P3 DIS@ 1 2CV313 0.22U_0402_16V7K PEG_HTX_GRX_P3 AC29 AD27 PEG_GTX_HRX_P3 DIS@ 1 2CV7 0.22U_0402_16V7K PEG_GTX_C_HRX_P3 NC_TXOUT_L3N
PEG_HTX_C_GRX_N3 DIS@ 1 2CV304 0.22U_0402_16V7K PEG_HTX_GRX_N3 AB28 PCIE_RX3P PCIE_TX3P AD26 PEG_GTX_HRX_N3 DIS@ 1 2CV8 0.22U_0402_16V7K PEG_GTX_C_HRX_N3
L
PCIE_RX3N PCIE_TX3N TMDP
AB30 AC25 AH20

AA31 PCIE_RX4P PCIE_TX4P AB25 TXCBP_DPB3P AJ19
PCIE_RX4N PCIE_TX4N TXCBM_DPB3N
E
change to 0.22uf for gen3 AL21
AA29 Y23 TX3P_DPB2P AK20
Y28 PCIE_RX5P PCIE_TX5P Y24 TX3M_DPB2N
PCIE_RX5N PCIE_TX5N AH22
TX4P_DPB1P AJ21
TX4M_DPB1N
D
Y30 AB27
W31 PCIE_RX6P PCIE_TX6P AB26 AL23
PCIE_RX6N PCIE_TX6N TX5P_DPB0P AK22
TX5M_DPB0N
W29 Y27 AK24
PCIE_RX7P PCIE_TX7P NC_TXOUT_U3P
r
V28 Y26 AJ23
PCIE_RX7N PCIE_TX7N NC_TXOUT_U3N
B B
V30 W24
o
U31 NC#V30 NC#W24 W23
NC#U31 NC#W23
2160856030-A0_FCBGA631
?
f
U29 V27
T28 NC#U29 NC#V27 U26
NC#T28 NC#U26
PCI EXPRESS INTERFACE

l
T30 U24
R31 NC#T30 NC#U24 U23
NC#R31 NC#U23
a
R29 T26
P28 NC#R29 NC#T26 T27
i
NC#P28 NC#T27 GPU R1 GPU R3
t
P30 T24
N31 NC#P30 NC#T24 T23
NC#N31 NC#T23
R16M-M70 R16M-M70
n
N29 P27
M28 NC#N29 NC#P27 P26
NC#M28 NC#P26
M30
L31
L29
K30
NC#M30
NC#L31
NC#L29
NC#K30
id r NC#P24
NC#P23
NC#M27
NC#N26
P24
P23
M27
N26
UV1
SA000098V0L
UV1
SA000098V1L
f
M70_R1@ M70_R3@
C CLOCK C
CLK_PEG_VGA AK30 S IC 216-0889-018 A0 R16M-M1-70 FCBGA 631P S IC 216-0889-018 A0 R16M-M1-70 A31!
[10] CLK_PEG_VGA PCIE_REFCLKP
n
[10] CLK_PEG_VGA# CLK_PEG_VGA# AK32
PCIE_REFCLKN +0.95VSDGPU
CALIBRATION
R16M-M30 R16M-M30
o
Y22 RV1 1 DIS@ 2 1.69K_0402_1%
PCIE_CALR_TX
RV2 1 DIS@ 2 1K_0402_1% N10 AA22 RV3 1 DIS@ 2 1K_0402_1% UV1 UV1
TEST_PG PCIE_CALR_RX
c
SA000087T0L SA000087T2L
PLT_RST_VGA# AL27
PERSTB M30_R1@ M30_R3@
l
2160856030-A0_FCBGA631 S IC 216-0890-010 A0 R16M-M1-30 FCBGA 631P S IC 216-0890-010 A0 R16M-M1-30 A31!
pa +3VGS
UV2
DIS@
5
m
PXS_RST# 1
P
[9] PXS_RST# IN1 4 PLT_RST_VGA#

APU_PCIE_RST# 2 O
[9,19,20] APU_PCIE_RST# IN2
G
co
1
3
RV4
MC74VHC1G08DFT2G_SC70-5 100K_0402_5%
D D
DIS@
2

Title
Issued Date 2016/01/07 Deciphered Date 2017/01/07
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL M30/M70_PCIE/DP
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom A00
Date:
BAL22 LA-D803P
Tuesday, June 21, 2016 Sheet 33 of 56
1 2 3 4 5
1 2 3 4 5
+3VGS
@
Resistor Divider Lookup Lable
UV1B +1.8VGS
U? 0402 1% resistors are equired PS_0[3:1]=001 Strap Name :
R_pu (ohm) R_pd (ohm) Bitd [3:1] PS_0[5:4]=11
1
RV5 RV6 AF2
PS_0[1] ROM_CONFIG[0]
NC#AF2
5
45.3K_0402_1% 45.3K_0402_1% AF4 NC 4.75k 000 RV8 PS_0[2] ROM_CONFIG[1]
G
QV1B DIS@ DIS@ NC#AF4 8.45K_0402_1%
DIS@ @ 1 N9 AG3 8.45k 2k 001 DIS@ PS_0[3] ROM_CONFIG[2]
T201
2
@ 1 L9 DBG_DATA16 NC#AG3 AG5 PS_0
T202 DBG_DATA15 NC#AG5
3 4 VGA_SMB_DA3 @ 1 AE9 DPA 4.53k 2k 010 PS_0[4] N/A
S
Vinafix.com
[8,27,28] EC_SMB_DA2 T203
y
DBG_DATA14
1
@ 1 Y11 AH3
D
1
0.68U_0402_10V
T204 DBG_DATA13 NC#AH3
@ 1 AE8 AH1 6.98k 4.99k 011 PS_0[5] AUD_PORT_CONN_PINSTRAP[0]
T205 DBG_DATA12 NC#AH1
2
DMN66D0LDW-7 2N SOT363-6 @ 1 AD9 CV29 RV9
l
G
T206 DBG_DATA11
QV1A @ 1 AC10 AK3 4.53k 4.99k 100 @ 2K_0402_1%
T207 DBG_DATA10 NC#AK3 2
DIS@ @ 1 AD7 AK1 DIS@
T208
2
@ 1 AC8 DBG_DATA9 NC#AK1
A
6 1 VGA_SMB_CK3
T209
@ 1 AC7 DBG_DATA8 DVO
AK5
3.24k 5.62k 101 A
S
[8,27,28] EC_SMB_CK2 T210 DBG_DATA7 NC#AK5
@ 1 AB9 AM3
D
3.4k 10k 110
n
T211 DBG_DATA6 NC#AM3
@ 1 AB8
T212 DBG_DATA5
DMN66D0LDW-7 2N SOT363-6 @ 1 AB7 AK6
T213
@ 1 AB4 DBG_DATA4 NC#AK6 AM5
4.75k NC 111
T214
@ 1 AB2 DBG_DATA3
DPB
NC#AM5 change to support gen3 11/24
T215 DBG_DATA2
@ 1 Y8 AJ7 Strap Name :
T216
o
+VGA_CORE +VGA_CORE_M70 @ 1 Y7 DBG_DATA1 NC#AJ7 AH6 +1.8VGS
T217 DBG_DATA0 NC#AH6 PS_1[3:1]=001
AK8
Capacitor Divider Lookup Lable
NC#AK8 PS_1[5:4]=11 PS_1[1] STRAP_BIF_GEN3_EN_A
1
M70@ AL7
RV367 1 2 0_0603_5% NC#AL7 DIS@
Cap (nF) Bitd [5:4] RV11
PS_1[2] TRAP_BIF_CLK_PM_EN
W6 8.45K_0402_1% PS_1[3] N/A
V6 NC#W6
del thermal sensor 11/19 680nF 00
2
NC#V6 V4 PS_1 PS_1[4] STRAP_TX_CFG_DRV_FULL_SWING
L
AC6 NC#V4 U5
NC#AC5 NC#U5 82nF 01
1
AC5 1 PS_1[5] STRAP_TX_DEEMPH_EN
0.68U_0402_10V
NC#AC6 W3 DIS@
AA5 NC#W3 V2
10nF 10 CV28 RV12
+1.8VGS AA6 NC#AA5 NC#V2 @ 2K_0402_1%
NC#AA6 DPC
Y4
NC 11 2
2
NC#Y4
L
+1.8VGS W5
RV152 @ NC#W5
2 1 GPIO19_CTF RV82 2 M70@ 1 4.7K_0402_5% BP_0 U1 AA3 PLL_Analog_out
+3VGS @ 1FB_VDDCI W1 NC#U1 NC#AA3 Y2
T222 NC#W1 NC#Y2
1
10K_0402_5% RV81 2 M70@ 1 4.7K_0402_5% BP_1 U3
NC#U3
2
Y6 J8 RV83
NC#Y6 NC#J8 +1.8VGS
E
RV154 1 @ 2 5.1K_0402_1% RV151 @ 1PLL_Analog_in AA1 16.2K_0402_1% PS_2[3:1]=000 Strap Name :
T221 NC#AA1
10K_0402_5% DIS@
DIS@
PS_2[5:4]=11
1
RV17 1 DIS@ 2 1K_0402_1% TESTEN PS_2[1] N/A
1
@
change bom structure to dis@ 11/24 RV28
+3VGS
I2C
8.45K_0402_1%
PS_2[2] N/A
@ 1 R1
PS_2[3] STRAP_BIOS_ROM_EN
D
T223
2
@ 1 R3 SCL PS_2
T224 SDA
1 8 JTAG_TDI_GPU PS_2[4] STRAP_BIF_VGA_DIS
1
2 7 JTAG_TMS_GPU AM26
change to 4.7K 11/23 1
0.082U_0402_16V
3 6 JTAG_TCK +VGA_CORE_M70 R AK26
4 5 JTAG_TRSTB U6
GENERAL PURPOSE I/O AVSSN#AK26 +3VGS CV11 RV13
PS_2[5] N/A
U10 GPIO_0 AL25 @ 4.75K_0402_1%
r
RV260 GPIO_1 G 2
RPV34 10K_8P4R_5% DIS@ 4.7K_0402_5% T10 AJ25 DIS@
2
GPIO_2 AVSSN#AJ25
1
@ +3VGS 1 2 VGA_SMB_DA3 U8
B
2 1 JTAG_TDO_GPU VGA_SMB_CK3 U7 SMBDATA AH24 RV162 B
VGA_AC__BATT T9 SMBCLK B AG25 4.7K_0402_5%
RV20 DIS@ RV369 @ 10K_0402_5% PCC_GPIO_6 T8 GPIO_5_AC_BATT AVSSN#AG25 @
o
1M_0402_5% T7 GPIO_6 DAC1 AH26
2
XTALOUT XTALIN P10 GPIO_7_BLON HSYNC AJ27 WAKEB
reserve 11/25 P4 GPIO_8_ROMSO VSYNC
GPIO_9_ROMSI
1
+1.8VGS
f
YV1 DIS@ P2
27MHZ_10PF_7V27000050 Reduce 3.3V TO 1.8V level shift for EXO. N6 GPIO_10_ROMSCK AD22 RV163
PS_3[3:1]=000 Strap Name :
+VGA_CORE_M70 GPIO_11 RSET
BOM contorl in POWER sheet N5
GPIO_12
4.7K_0402_5% PS_3[5:4]=11
1
3 1 N3 AG24 DIS@
3 1 Y9 GPIO_13 AVDD AE22 @
PS_3[1] BOARD_CONFIG[0] (Memory ID)
1 1
VRAM Type
2
CV18 GND GND CV17 GPU_VID3 N1 GPIO_14_HPD2 AVSSQ RV15
PS_3[2] BOARD_CONFIG[1] (Memory ID)
l
GPIO_15_PWRCNTL_0
8.2P_0402_50V8D
DIS@ 4 2
8.2P_0402_50V8D
DIS@
M4
R6 GPIO_16 VDD1DI
AE23
AD23
8.45K_0402_1% Need reference
PS_3[3] BOARD_CONFIG[2] (Memory ID) X76 Schematic
2
2 2 W10 GPIO_17_THERMAL_INT VSS1DI PS_3
GPIO19_CTF M2 GPIO_18
GPIO_19_CTF FutureASIC/SEYMOUR/PARK PS_3[4] AUD_PORT_CONN_PINSTRAP[1]
1
a
GPU_VID1 P8 AM12 1
0.68U_0402_10V
P7 GPIO_20_PWRCNTL_1 CEC_1 @
N8 GPIO_21 CV15 RV16
PS_3[5] AUD_PORT_CONN_PINSTRAP[2]
i
AK10 GPIO_22_ROMCSB AK12 M70@ 1 RV155 2 0_0402_5% SVI2_SVD @ 4.75K_0402_1%
AM10 GPIO_29 RSVD#AK12 AL11 M70@ 1 RV156 2 0_0402_5% SVI2_SVT SVI2_SVT [52] 2 SD034475180
2
1 @ 2 PEG_CLKREQ#_G N7 GPIO_30 RSVD#AL11 AJ11 M70@ 1 RV157 2 0_0402_5% SVI2_SVC
t
[9] PEG_CLKREQ# CLKREQB RSVD#AJ11
RV153 0_0402_5%
JTAG_TRSTB L6
JTAG_TDI_GPU L5 JTAG_TRSTB
reserve level shift colay resistor 11/20 JTAG_TCK L3 JTAG_TDI
JTAG_TCK
JTAG_TMS_GPU L1 AL13
n
JTAG_TDO_GPU K4 JTAG_TMS GENLK_CLK AJ13
TESTEN K7 JTAG_TDO GENLK_VSYNC
AF24 TESTEN
+3VGS +3VGS +3VGS +VGA_CORE_M70 NC#AF24
r
+1.8VGS AG13
SWAPLOCKA AH12
AB13 SWAPLOCKB
W8 GENERICA
2 GENERICB
2
2 W9
CV185 M30@ RV92 RV73 W7 GENERICC AC19 PS_0
id
0.1U_0402_10V7K 10K_0402_5% 10K_0402_5% M30@ CV183 AD10 GENERICD PS_0
1 @ M30@ AJ9 GENERICE AD19 PS_1
0.1U_0402_10V7K
1 @ 1 AL9 NC#AJ9 PS_1
1
M30@ T4935 NC#AL9 AE17 PS_2

@ UV4 @ AC14 PS_2
0_0402_5% 1 8 33_0402_5% @ 1 PX_EN AB16 HPD1 AE20 PS_3
f
VCCA VCCB T218 PX_EN PS_3
GPU_VID3 RV103 1 2 GPU_VID3_GPIO_15 2 7 RV101 1 2 SVI2_SVD
A1 B1 SVI2_SVD [52]
GPU_VID1 RV76 1 2 GPU_VID1_GPIO_20 3 6 RV100 1 2 SVI2_SVC
A2 B2 SVI2_SVC [52]
C DIR 5 4 AE19 C
0_0402_5% DIR GND 33_0402_5% AC16 TS_A
DBG_VREFG
2
@ @ add pd 10k11/23
n
S IC SN74AVC2T45DCTR_SM8
RV75 RV74 PEG_CLKREQ#_G DDC/AUX

10K_0402_5% 10K_0402_5% AE6
1
M30@ @ PLL/CLOCK DDC1CLK AE5
o
DDC1DATA
2
M30@
GPU_VID3 RV93 1 20_0402_5% SVI2_SVD AD2
AUX1P AD4 +VGA_CORE_M70
GPU_VID1 RV94 1 M30@ 20_0402_5% SVI2_SVC RV368 AUX1N
10K_0402_5% AC11
c
1
M30@ @ DDC2CLK AC13

+3VGS 10K_0402_5% CV182 10U_0603_6.3V6M DDC2DATA
RV102 2 1 DIR 2 1 XTALIN AM28 AD13
3.3V TO 1.8V LEVEL SHIF XTALOUT AK28 XTALIN
XTALOUT
AUX2P
AUX2N
AD11 change to 0 ohm 11/23
M30@ CV184
For JET/SUN to support SVI2 reaulator
l
2 1 0.1U_0402_10V7K RV29 1 DIS@ 2 10K_0402_5% AC22 AD20 FB_GND RV158 2 DIS@ 1 0_0402_5% VSSSENSE_VGA VSSSENSE_VGA [52]
DNI for TOPAZ RV59 1 DIS@ 2 10K_0402_5% AB22 XO_IN
XO_IN2
NC#AD20
NC#AC20
AC20 FB_VDDC RV159 2 DIS@ 1 0_0402_5% VCCSENSE_VGA VCCSENSE_VGA [52]
M30@
AE16
NC#AE16 AD16
a
NC#AD16
REMOVE THERMAL SENSOR SIGNAL 11/24
ADD GPU POWER SAVING MODE 11/26 SEYMOUR/FutureASIC
DDCVGACLK
AC1
+1.8VGS T4 AC3
2 @ 1 0_0402_5% LV2 DIS@ T2 DPLUS THERMAL DDCVGADATA +1.8VGS +3VGS
+3VALW
RV165 1 2 13mA DMINUS
p
BLM15BD121SN1D_0402
2 @ 1 DIS@ GPIO28 R5 +VGA_CORE 1 M70@ 2 1 M30@ 2
+3VGS GPIO28_FDO
RV164 0_0402_5% CV19 2 1 10U_0603_6.3V6M +TSVDD AD17 RV71 0_0402_5% RV72 0_0402_5%
DIS@ AC17 TSVDD
TSVSS
2
1 CV20 2 1 1U_0402_6.3V4Z VCCSENSE_VGA 1 M30@ 2
DIS@ VSSSENSE_VGA RV161 1 M30@ 2 10_0402_5% @
CV186 CV21 2 1 0.1U_0402_10V6K RV160 10_0402_5% RV84 RV87
10K_0402_5% 10K_0402_5% Boot-VID Code
m
0.1U_0402_10V7K 2160856030-A0_FCBGA631
2 RV21 1 M30@ 2 10K_0402_5% ? DIS@
@ Voltage
1
TOPAZ Thermal Address-->0x82 SVC SVD
SVI2_SVD
Selected (V)
Enable MLPS SVI2_SVC
co
UV3
DIS@ Enable --> Low 0 0 1.1
5
Disable --> High 0 1 1.0
2
[27,41,42] ACIN 1
P
D IN1 4 VGA_AC__BATT +3VGS D
[27] ACIN_65W 2 O @ RV88 1 0 0.9

IN2
G
RV89 10K_0402_5%
1 1 0.8
2
MC74VHC1G08DFT2G_SC70-5 10K_0402_5% DIS@

3
1
@
RV91
10K_0402_5%
2 @ 1 0_0402_5%
1
RV150
PCC_GPIO_6 1 2 OCP_L OCP_L [52]
2 RV90 @ 1K_0402_1%
@
CVT90
0.1U_0402_10V7K 1 Security Classification Compal Secret Data
Title
Peak Current Control (PCC) CKT Issued Date 2016/01/07 Deciphered Date 2017/01/07 M30/M70_MSIC
Reversed THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Date:
BAL22 LA-D803P
1 2 3 4 5
1 2 3 4 5
Vinafix.com
A
n l y A
L o
E L @
UV1E U?
D
AA27 A3
370mA (HDMI) No Use GPU Display Port outpud AB24 GND GND A30
+1.8VGS GND GND
RV27
188mA (Display Port) @
0_0603_1%
AB32
AC24 GND GND
AA13
AA16
GND GND
r
2 @ 1 +DP_VDDR UV1G U? AC26 AB10
AC27 GND GND AB15
B
AD25 GND GND AB6 B
CV26
CV27
CV35
DP POWER NC/DP POWER
AD32 GND GND AC9
1 1 1
o
AG15 AE11 AE27 GND GND AD6
@ @ @ AG16 DP_VDDR#AG15 NC#AE11 AF11 AF32 GND GND AD8
AF16 DP_VDDR#AG16 NC#AF11 AE13 AG27 GND GND AE7
10U_0603_6.3V6M
1U_0402_6.3V4Z
0.1U_0402_10V6K
2 2 2 AG17 DP_VDDR#AF16 NC#AE13 AF13 AH32 GND GND AG12
change to @ 11/25 AG18 DP_VDDR#AG17 NC#AF13 AG8 K28 GND GND AH10
AG19 DP_VDDR#AG18 NC#AG8 AG10 K32 GND GND AH28
AF14 DP_VDDR#AG19 NC#AG10 L27 GND GND B10
l
DP_VDDR#AF14 M32 GND GND B12
N25 GND GND B14
N27 GND GND B16
GND GND
a
P25 B18
AG20 AF6 P32 GND GND B20
AG21 DP_VDDC#AG20 NC#AF6 AF7 R27 GND GND B22
i
+0.95VSDGPU AF22 DP_VDDC#AG21 NC#AF7 AF8 T25 GND GND B24
RV30 0_0603_1% 280mA AG22 DP_VDDC#AF22 NC#AF8 AF9 T32 GND GND B26
t
2 @ 1 +DP_VDDC AD14 DP_VDDC#AG22 NC#AF9 U25 GND GND B6
DP_VDDC#AD14 U27 GND GND B8
V32 GND GND C1
CV30
CV33
CV34
W25 GND GND C32
1 1 1
n
AG14 AE1 W26 GND GND E28
@ @ @ AH14 DP_VSSR NC#AE1 AE3 W27 GND GND F10
DP_VSSR NC#AE3 GND GND
r
AM14 AG1 Y25 F12
10U_0603_6.3V6M
0.1U_0402_10V6K
1U_0402_6.3V4Z
2 2 2 AM16 DP_VSSR NC#AG1 AG6 Y32 GND GND F14
AM18 DP_VSSR NC#AG6 AH5 GND GND F16
change to @ 11/25 AF23 DP_VSSR NC#AH5 AF10 GND F18
DP_VSSR NC#AF10 GND
id
AG23 AG9 F2
AM20 DP_VSSR NC#AG9 AH8 GND F20
AM22 DP_VSSR NC#AH8 AM6 M6 GND F22
AM24 DP_VSSR NC#AM6 AM8 N13 GND GND F24
AF19 DP_VSSR NC#AM8 AG7 N16 GND GND F26
DP_VSSR NC#AG7 GND GND
f
AF20 AG11 N18 F6
AE14 DP_VSSR NC#AG11 N21 GND GND
GND F8
DP_VSSR P6 GND GND G10
C C
P9 GND GND G27
GND GND
n
R12 G31
AF17 AE10 R15 GND GND G8
DPAB_CALR NC#AE10 R17 GND GND H14
R20 GND GND H17
GND GND
o
T13 H2
T16 GND GND H20
2160856030-A0_FCBGA631 GND GND
? T18 H6
T21 GND GND J27
c
T6 GND GND J31
U15 GND GND K11
U17 GND GND K2
U20 GND GND K22
l
U9 GND GND K6
V13 GND GND
V16 GND
GND
a
V18
Y10 GND
Y15 GND
Y17 GND
GND
p
Y20
R11 GND A32
T11 GND VSS_MECH AM1
AA11 GND VSS_MECH AM32
M12 GND VSS_MECH
N11 GND
V11 GND
m
GND
2160856030-A0_FCBGA631
?
co
D D

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL M30/M70_Power/GND
Date:
BAL22 Sheet
LA-D803P
35 of 56
1 2 3 4 5
1 2 3 4 5
Vinafix.com
A
+VGA_CORE
VDDC
10uF
4
1uF
30
0.1uF
0 @
n l y A
o
VDDC and VDDCI TDC 28A UV1D +1.8VGS
+1.35V_MEM_GFX
U?
100mA
AM30 +PCIE_PVDD
VDDCI 1 3 3 2A MEM I/O PCIE_PVDD
PCIE
CV38
CV46
CV39
H13 AB23
CV179
VDDR1 NC#AB23 1 1 1 1
H16 AC23
H19 VDDR1 NC#AC23 AD24 DIS@ DIS@ DIS@ DIS@
CV43
CV44
CV45
CV40
CV47
CV48
CV41
CV42
CV49
CV50
CV51
CV52
CV53
L
J10 VDDR1 NC#AD24 AE24
CV174
CV175
CV176
CV177
CV178
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
10U_0603_6.3V6M
0.1U_0402_10V6K
1U_0402_6.3V4Z
0.01U_0402_16V7K
J23 VDDR1 NC#AE24 AE25 2 2 2 2
+0.95VSDGPU 10uF 1uF 0.1uF DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
DIS@ DIS@ DIS@ DIS@ DIS@
J24 VDDR1 NC#AE25 AE26
J9 VDDR1 NC#AE26 AF25
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
0.01U_0402_16V7K
0.01U_0402_16V7K
0.01U_0402_16V7K
0.01U_0402_16V7K
0.01U_0402_16V7K
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 K10 VDDR1 NC#AF25 AG26
L
K23 VDDR1 NC#AG26
PCIE_VDDC 2A 2 7 0 K24 VDDR1
K9 VDDR1 L23
L11 VDDR1 PCIE_VDDC L24
BIF_VDDC 0.8A 1 2 0
E
L20 VDDR1 PCIE_VDDC M22 +0.95VSDGPU
L21 VDDR1 PCIE_VDDC N22 2A
L22 VDDR1 PCIE_VDDC N23 +PCIE_VDDC 2 @ 1
SPLL_VDDC 100mA 1 1 1 VDDR1 PCIE_VDDC N24 0_0603_1%
CV54
CV55
CV56
CV57
CV58
CV59
CV60
CV120
CV121
PCIE_VDDC
D
R22 1 1 1 1 1 1 1 1 1 RV364
PCIE_VDDC T22
+1.8VGS 13mA LEVEL PCIE_VDDC U22 DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
LV3 DIS@ TRANSLATION PCIE_VDDC V22
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1 2 +VDD_CT AA20 PCIE_VDDC 2 2 2 2 2 2 2 2 2
+1.35V_MEM_GFX 10uF 2.2uF 0.1uF 0.01uF VDD_CT
r
BLM15BD121SN1D_0402 AA21
AB20 VDD_CT AA15
CV61
CV62
CV63
B
AB21 VDD_CT CORE VDDC N15 B
1 1 1 VDD_CT VDDC N17
VDDR1 2A 3 5 5 5
o
DIS@ DIS@ DIS@ +3VGS VDDC R13
LV4 DIS@ 25mA I/O VDDC R16
10U_0603_6.3V6M
0.1U_0402_10V6K
1U_0402_6.3V4Z
2 2 2 1 2 +VDDR3 AA17 VDDC R18
f
BLM15BD121SN1D_0402 AA18 VDDR3 VDDC Y21
AB17 VDDR3 VDDC T12
CV64
CV65
CV66
CV123
AB18 VDDR3 VDDC T15 +VGA_CORE
+1.8VGS 10uF 1uF 0.1uF 0.01uF 1 1 1 1 VDDR3 VDDC T17
l
DIS@ DIS@ DIS@ DIS@ V12 VDDC T20
Y12 VDDR4 VDDC U13
CV67
CV68
CV69
CV70
CV71
CV72
CV73
CV74
CV75
CV76
CV77
CV78
CV79
CV80
10U_0402_6.3V6M
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
2 2 2 2 U12 VDDR4 VDDC U16
PCIE_PVDD 100mA 1 1 1 1 VDDR4 VDDC 1 1 1 1 1 1 1 1 1 1 1 1 1 1
a
U18
VDDC V21 DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
VDDC V15
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
VDDC V17 2 2 2 2 2 2 2 2 2 2 2 2 2 2
MPLL_PVDD 90mA 1 1 1 VDDC V20
0
t
VDDC
POWER
Y13
VDDC Y16
VDDC Y18
SPLL_PVDD 75mA 1 1 1 VDDC AA12
0
n
VDDC M11
VDDC N12
VDDC
r
U11
VDD_CT 13mA 1 1 CIS SYMBOL VDDC
CV101
CV104
CV100
CV106
CV103
CV109
CV102
CV107
CV108
CV105
1 0 +1.8VGS
LV6 DIS@ 90mA PLL
1 1 1 1 1 1 1 1 1 1
id
1 2 +MPLL_PVDD DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
+DP_VDDR 40mA 1(@) 1(@) 1(@) BLM15BD221SN1D_2P
CV81
CV82
CV124
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
2 2 2 2 2 2 2 2 2 2
1 1 1
R21 0.8A
DIS@ DIS@ DIS@ BIF_VDDC U21 +BIF_VDDC
+DP_VDDC 1(@) 1(@) 1(@) 0 BIF_VDDC
f
10U_0603_6.3V6M
0.1U_0402_10V6K
1U_0402_6.3V4Z
2 2 2 L8
+1.8VGS MPLL_PVDD
C
LV7 DIS@ 75mA ISOLATED
C
n
1 2 +SPLL_PVDD CORE I/O
BLM15BD121SN1D_0402 M13
CV84
CV85
CV86
H7 VDDCI M15
1 1 1 SPLL_PVDD VDDCI M16
CV111
CV114
CV110
CV117
CV113
CV118
CV112
CV116
CV119
CV115
VDDCI
o
DIS@ DIS@ DIS@ M17 1 1 1 1 1 1 1 1 1 1
+0.95VSDGPU VDDCI M18
100mA
10U_0603_6.3V6M
0.1U_0402_10V6K
1U_0402_6.3V4Z
2 2 2 LV8 DIS@ VDDCI M20 DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
1 2 +SPLL_VDDC H8 VDDCI M21
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
BLM15BD121SN1D_0402 SPLL_VDDC VDDCI N20 2 2 2 2 2 2 2 2 2 2
CV91
CV92
CV93
J7 VDDCI
+3VGS 10uF 1uF 0.1uF 1 1 1 SPLL_PVSS
DIS@ DIS@ DIS@
l 10U_0603_6.3V6M
1U_0402_6.3V4Z
0.1U_0402_10V6K
2 2 2
VDDR3 25mA 1 3 0 2160856030-A0_FCBGA631
?
pa +BIF_VDDC 2
RV31
@ 1
+0.95VSDGPU
0_0805_5%
+VGA_CORE
CV122
CV181
CV180
1 2 2
m
DIS@ DIS@ DIS@
CV88
CV89
CV90
CV87
CV125
CV126
CV127
1 1 1 1
10U_0603_6.3V6M
1U_0402_6.3V4Z
1U_0402_6.3V4Z
2 1 1 add 0.1U *3 11/20
1 1 1
DIS@ DIS@ DIS@ DIS@
co
DIS@ DIS@ DIS@
10U_0603_6.3V6M
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
2 2 2 2
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
2 2 2
D D

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL M30/M70_Power
Date:
BAL22 Sheet
LA-D803P
36 of 56
1 2 3 4 5
1 2 3 4 5
M_DA[63..0]
[38,39] M_DA[63..0]
Vinafix.com
A
[38]
[39]
M0_MA[8..0]
M1_MA[8..0]
M0_MA[8..0]
M1_MA[8..0]
@
UV1C U?
n l y A
o
GDDR5/DDR3 GDDR5/DDR3
M_DA0 K27 K17 M0_MA0
M_DA1 J29 DQA0_0 MAA0_0/MAA_0 J20 M0_MA1
M_DA2 H30 DQA0_1 MAA0_1/MAA_1 H23 M0_MA2
M_DA3 H32 DQA0_2 MAA0_2/MAA_2 G23 M0_MA3
M_DA4 G29 DQA0_3 MAA0_3/MAA_3 G24 M0_MA4
L
M_DA5 F28 DQA0_4 MAA0_4/MAA_4 H24 M0_MA5
M_DA6 F32 DQA0_5 MAA0_5/MAA_5 J19 M0_MA6
+1.35V_MEM_GFX +1.35V_MEM_GFX M_DA7 F30 DQA0_6 MAA0_6/MAA_6 K19 M0_MA7
M_DA8 C30 DQA0_7 MAA0_7/MAA_7 G20 M0_MA8
M_DA9 F27 DQA0_8 MAA0_8/MAA_13 L17
L
M_DA10 A28 DQA0_9 MAA0_9/MAA_15
DQA0_10
1
1
M_DA11 C28 J14 M1_MA0
M_DA12 E27 DQA0_11 MAA1_0/MAA_8 K14 M1_MA1
RV33 RV32 M_DA13 G26 DQA0_12 MAA1_1/MAA_9 J11 M1_MA2
40.2_0402_1% 40.2_0402_1% M_DA14 D26 DQA0_13 MAA1_2/MAA_10 J13 M1_MA3
E
DIS@ DIS@ M_DA15 F25 DQA0_14 MAA1_3/MAA_11 H11 M1_MA4
2
M_DA16 A25 DQA0_15 MAA1_4/MAA_12 G11 M1_MA5

+MVREFDA +MVREFSA M_DA17 C25 DQA0_16 MAA1_5/MAA_BA2 J16 M1_MA6
M_DA18 E25 DQA0_17 MAA1_6/MAA_BA0 L15 M1_MA7
M_DA19 D24 DQA0_18 MAA1_7/MAA_BA1 G14 M1_MA8
DQA0_19 MAA1_8/MAA_14
1
D
1 1 M_DA20 E23 L16
MEMORY INTERFACE
M_DA21 F23 DQA0_20 MAA1_9/RSVD
RV34 CV94 RV35 CV95 M_DA22 D22 DQA0_21 E32 M_WCKA0_0
DQA0_22 WCKA0_0/DQMA0_0 M_WCKA0_0 [38]
100_0402_1% 1U_0402_6.3V4Z 100_0402_1% 1U_0402_6.3V4Z M_DA23 F21 E30 M_WCKA0_0#
2 DIS@ 2 DQA0_23 WCKA0B_0/DQMA0_1 M_WCKA0_0# [38]
DIS@ DIS@ DIS@ M_DA24 E21 A21 M_WCKA0_1
M_WCKA0_1 [38]
2
DQA0_24 WCKA0_1/DQMA0_2
r
M_DA25 D20 C21 M_WCKA0_1#
DQA0_25 WCKA0B_1/DQMA0_3 M_WCKA0_1# [38]
M_DA26 F19 E13 M_WCKA1_0
B DQA0_26 WCKA1_0/DQMA1_0 M_WCKA1_0 [39] B
M_DA27 A19 D12 M_WCKA1_0#
M_DA28 D18 E3 M_WCKA1_1
M_WCKA1_1 [39]
o
M_DA29 F17 DQA0_28 WCKA1_1/DQMA1_2 F4 M_WCKA1_1#
M_DA30 A17
M_DA31 C17 DQA0_30 H28 M_EDC_0
f
DQA0_31 EDCA0_0/QSA0_0 M_EDC_0 [38]
M_DA32 E17 C27 M_EDC_1
M_DA33 D16 A23 M_EDC_2
M_DA34 F15 E19 M_EDC_3
M_DA35 A15 E15 M_EDC_4
l
M_DA36 D14 D10 M_EDC_5
M_DA37 F13 D6 M_EDC_6
RV36 DIS@ RV37 DIS@ M_DA38 A13 G5 M_EDC_7
a
49.9_0402_1% 10_0402_1% M_DA39 C13
1 2 2 1 DRAM_RST_G M_DA40 E11 DQA1_7 H27 M_DBI0#
[38,39] DRAM_RST DQA1_8 DDBIA0_0/QSA0_0B M_DBI0# [38]
M_DA41 A11 A27 M_DBI1#
i
DQA1_9 DDBIA0_1/QSA0_1B M_DBI1# [38]
M_DA42 C11 C23 M_DBI2#
1
1 1 M_DA43 F11 C19 M_DBI3#
t
@ M_DA44 A9 C15 M_DBI4#
CV96 RV38 CV97 M_DA45 C9 E9 M_DBI5#
120P_0402_50V8J DQA1_13 DDBIA1_1/QSA1_1B M_DBI5# [39]
5.1K_0402_1% 68P_0402_50V8J M_DA46 F9 C5 M_DBI6#
2 2 DQA1_14 DDBIA1_2/QSA1_2B M_DBI6# [39]
DIS@ DIS@ M_DA47 D8 H4 M_DBI7#
n
M_DBI7# [39]
2
M_DA48 E7 DQA1_15 DDBIA1_3/QSA1_3B

M_DA49 A7 DQA1_16 L18 M_ADBI0
DQA1_17 ADBIA0/ODTA0 M_ADBI0 [38]
r
M_DA50 C7 K16 M_ADBI1
DQA1_18 ADBIA1/ODTA1 M_ADBI1 [39]
M_DA51 F7
M_DA52 A5 DQA1_19 H26 M_CLK0
DQA1_20 CLKA0 M_CLK0 [38]
M_DA53 E5 H25 M_CLK#0
DQA1_21 CLKA0B M_CLK#0 [38]
id
M_DA54 C3
M_DA55 E1 DQA1_22 G9 M_CLK1
Place close to GPU (within 25mm) M_DA56 G7 DQA1_23 CLKA1 H9 M_CLK#1
M_CLK1 [39]
and place componment within (5mm) close to each other M_DA57 G6 DQA1_24 CLKA1B M_CLK#1 [39]
M_DA58 G1 DQA1_25 G22 M_RAS#0
DQA1_26 RASA0B M_RAS#0 [38]
f
M_DA59 G3 G17 M_RAS#1
DQA1_27 RASA1B M_RAS#1 [39]
M_DA60 J6
M_DA61 J1 DQA1_28 G19 M_CAS#0
C C
DQA1_29 CASA0B M_CAS#0 [38]
M_DA62 J3 G16 M_CAS#1
DQA1_30 CASA1B M_CAS#1 [39]
n
M_DA63 J5
DQA1_31 H22 M_CS0B#0
CSA0B_0 M_CS0B#0 [38]
+MVREFDA K26 J22
+MVREFSA J26 MVREFDA CSA0B_1
MVREFSA
o
G13 M_CS1B#0
CSA1B_0 M_CS1B#0 [39]
J25 K13
RV39 1 DIS@ 2 120_0402_1% K25 NC#J25 CSA1B_1
MEM_CALRP0 K20 M_CKE0
c
CKEA0 M_CKE0 [38]
J17 M_CKE1
CKEA1 M_CKE1 [39]
G25 M_WE#0
WEA0B M_WE#0 [38]
DRAM_RST_G L10 H10 M_WE#1
l
DRAM_RST WEA1B M_WE#1 [39]
RV40 @ 1 2 51.1_0402_1% CV98 @1 2 0.1U_0402_16V4Z K8
RV41 @ 1 2 51.1_0402_1% CV99 @1 2 L7 CLKTESTA
CLKTESTB
a
0.1U_0402_16V4Z
2160856030-A0_FCBGA631
?
m p
co
D D

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL M30/M70_MEM
Date:
BAL22 LA-D803P
1 2 3 4 5
5 4 3 2 1
clamshell configuration 11/26

UV12 @ MF=0 UV13 @ MF=1
bit swap 12/09 bit swap 12/09
M_DA[0..31] MF=0 MF=1 MF=1 MF=0 MF=0 MF=1 MF=1 MF=0
[37] M_DA[0..31]
A4 M_DA19 A4 M_DA2
M_EDC_2 C2 DQ24 DQ0 A2 M_DA22 M_EDC_0 C2 DQ24 DQ0 A2 M_DA0
[37] M_EDC_2 EDC0 EDC3 DQ25 DQ1 [37] M_EDC_0 EDC0 EDC3 DQ25 DQ1
C13 B4 M_DA17 C13 B4 M_DA3
R13 EDC1 EDC2 DQ26 DQ2 B2 R13 EDC1 EDC2 DQ26 DQ2 B2
M_EDC_1
L M_DA20 H M_EDC_3
H M_DA1
Vinafix.com
y
R2 E4 M_DA18 R2 E4 M_DA6 L
+1.35V_MEM_GFX +1.35V_MEM_GFX EDC3 EDC0
BYTE0 DQ28 DQ4 E2 M_DA21
BYTE2 +1.35V_MEM_GFX EDC3 EDC0
BYTE3 DQ28 DQ4 E2 M_DA7
DQ29 DQ5 F4 M_DA16 DQ29 DQ5 F4 M_DA5
BYTE0
l
D DQ30 DQ6 DQ30 DQ6 D
M_DBI2# D2 F2 M_DA23 M_DBI0# D2 F2 M_DA4
[37] M_DBI2# DBI0# DBI3# DQ31 DQ7 [37] M_DBI0# DBI0# DBI3# DQ31 DQ7
D13 A11 D13 A11
M_DBI1# P13 DBI1# DBI2# DQ16 DQ8 A13 M_DBI3# P13 DBI1# DBI2# DQ16 DQ8 A13
1 DIS@ 2 M_CLK0 P2 B11 P2 B11
DBI3# DBI0# DQ18 DQ10 DBI3# DBI0# DQ18 DQ10
n
RV79 120_0402_1% B13 B13
M_CLK0 J12 DQ19 DQ11 E11 M_CLK0 J12 DQ19 DQ11 E11
[37] M_CLK0 CK DQ20 DQ12 CK DQ20 DQ12
M_CLK#0 J11 E13 M_CLK#0 J11 E13
[37] M_CLK#0 CK# DQ21 DQ13 CK# DQ21 DQ13
1 DIS@ 2 M_CLK#0 M_CKE0 J3 F11 M_CKE0 J3 F11
[37] M_CKE0 CKE# DQ22 DQ14 CKE# DQ22 DQ14
RV80 120_0402_1% F13 F13
DQ23 DQ15 DQ23 DQ15
o
U11 M_DA15 U11 M_DA30
M0_MA2 H11 DQ8 DQ16 U13 M_DA13 M0_MA4 H11 DQ8 DQ16 U13 M_DA28
[37] M0_MA2 BA0/A2 BA2/A4 DQ9 DQ17 BA0/A2 BA2/A4 DQ9 DQ17
M0_MA5 K10 T11 M_DA11 M0_MA3 K10 T11 M_DA31
[37] M0_MA5
M0_MA4 K11 BA1/A5 BA3/A3 H DQ10 DQ18 T13 M_DA9 L M0_MA2 K11 BA1/A5 BA3/A3 L DQ10 DQ18 T13 M_DA29
[37] M0_MA3
M0_MA3 H10
BA3/A3 BA1/A5
BYTE2 DQ12 DQ20
N11 M_DA10
BYTE0 M0_MA5 H10
BA3/A3 BA1/A5
BYTE1 DQ12 DQ20
N11 M_DA27 H
+1.35V_MEM_GFX N13 M_DA12 N13 M_DA26
DQ13 DQ21 M11 M_DA8 DQ13 DQ21 M11 M_DA24
BYTE3
M0_MA7 K4 DQ14 DQ22 M13 M_DA14 M0_MA0 K4 DQ14 DQ22 M13 M_DA25
[37] M0_MA7 A8/A7 A10/A0 DQ15 DQ23 A8/A7 A10/A0 DQ15 DQ23
2.37K_0402_1%
L
M0_MA1 H5 U4 M0_MA6 H5 U4
[37] M0_MA1
1
M0_MA0 H4 A9/A1 A11/A6 DQ0 DQ24 U2 M0_MA7 H4 A9/A1 A11/A6 DQ0 DQ24 U2
RV52 DIS@
del cap 11/24 M0_MA6 K5 T4 M0_MA1 K5 T4

M0_MA8 J5 T2 M0_MA8 J5 T2
[37] M0_MA8 A12/RFU/NC DQ3 DQ27 A12/RFU/NC DQ3 DQ27
N4 N4
A5 DQ4 DQ28 N2 A5 DQ4 DQ28 N2
2
VPP/NC DQ5 DQ29 VPP/NC DQ5 DQ29
L
U5 M4 U5 M4
VPP/NC DQ6 DQ30 M2 +1.35V_MEM_GFX VPP/NC DQ6 DQ30 M2
+FB0_VREFDL DQ7 DQ31 DQ7 DQ31
RV134 2 DIS@ 1 1K_0402_1% J1 +1.35V_MEM_GFX RV131 2 DIS@ 1 1K_0402_1% J1 +1.35V_MEM_GFX
MF MF
1U_0402_6.3V6K
5.49K_0402_1%
RV135 2 DIS@ 1 1K_0402_1% J10 RV133 2 DIS@ 1 1K_0402_1% J10

1
RV123 2 DIS@ 1 121_0402_1% J13 SEN B1 RV132 2 DIS@ 1 121_0402_1% J13 SEN B1
1 ZQ VDDQ ZQ VDDQ
E
CV394 DIS@
RV53 DIS@
D1 D1
VDDQ F1 VDDQ F1
M_ADBI0 J4 VDDQ M1 M_ADBI0 J4 VDDQ M1
2 [37] M_ADBI0 ABI# VDDQ ABI# VDDQ
M_RAS#0 G3 P1 M_CAS#0 G3 P1
[37] M_RAS#0 samsung R1 samsung R3
2
M_CS0B#0 G12 RAS# CAS# VDDQ T1 M_WE#0 G12 RAS# CAS# VDDQ T1
[37] M_CS0B#0 CS# WE# VDDQ CS# WE# VDDQ
M_CAS#0 L3 G2 M_RAS#0 L3 G2
[37] M_CAS#0 CAS# RAS# VDDQ CAS# RAS# VDDQ
M_WE#0 L12 L2 M_CS0B#0 L12 L2
[37] M_WE#0
D
WE# CS# VDDQ B3 WE# CS# VDDQ B3
C VDDQ VDDQ C
D3 D3
VDDQ F3 VDDQ F3
M_WCKA0_1# D5 VDDQ H3 M_WCKA0_0# D5 VDDQ H3 UV12 UV12
[37] M_WCKA0_1# WCK01# WCK23# VDDQ WCK01# WCK23# VDDQ
+1.35V_MEM_GFX M_WCKA0_1 D4 K3 M_WCKA0_0 D4 K3
[37] M_WCKA0_1 WCK01 WCK23 VDDQ WCK01 WCK23 VDDQ
M3 M3 SA000092D0L SA000092D1L
r
M_WCKA0_0# P5 VDDQ P3 M_WCKA0_1# P5 VDDQ P3
2.37K_0402_1%
M_WCKA0_0 P4 T3 M_WCKA0_1 P4 T3 S4G_R1@ S4G_R3@

1
E5 E5
VDDQ VDDQ
RV54 DIS@
N5 N5 S IC D5 256M32 K4G80325FB-HC03 FBGA 170P S IC D5 256M32 K4G80325FB-HC28 FBGA A31!

A10 VDDQ E10 A10 VDDQ E10
o
+FB0_VREFDL +FB0_VREFDL
U10 VREFD VDDQ N10 U10 VREFD VDDQ N10
+FB0_VREFCL J14 VREFD VDDQ B12 +FB0_VREFCL J14 VREFD VDDQ B12 UV13 UV13
2
VREFC VDDQ D12 VREFC VDDQ D12
f
VDDQ F12 VDDQ F12
VDDQ VDDQ SA000092D0L SA000092D1L
+FB0_VREFCL H12 H12
DRAM_RST J2 VDDQ K12 DRAM_RST J2 VDDQ K12 S4G_R1@ S4G_R3@
[37,39] DRAM_RST RESET# VDDQ RESET# VDDQ
1U_0402_6.3V6K
5.49K_0402_1%
M12 M12
VDDQ VDDQ
1
P12 P12 S IC D5 256M32 K4G80325FB-HC03 FBGA 170P S IC D5 256M32 K4G80325FB-HC28 FBGA A31!
l
1 VDDQ VDDQ
CV395 DIS@
RV55 DIS@
T12 T12
VDDQ G13 VDDQ G13
H1 VDDQ L13 H1 VDDQ L13
2 K1 VSS VDDQ B14 K1 VSS VDDQ B14
Hynix R1 Hynix R3
a
2
B5 VSS VDDQ D14 B5 VSS VDDQ D14

G5 VSS VDDQ F14 G5 VSS VDDQ F14
L5 VSS VDDQ M14 L5 VSS VDDQ M14
i
T5 VSS VDDQ P14 T5 VSS VDDQ P14
B10 VSS VDDQ T14 B10 VSS VDDQ T14 UV12 UV12
VSS VDDQ VSS VDDQ
t
D10 D10
G10 VSS G10 VSS
VSS VSS SA00009U10L SA00009U11L
L10 A1 L10 A1
P10 VSS VSSQ C1 P10 VSS VSSQ C1 H4G_R1@ H4G_R3@
T10 VSS VSSQ E1 T10 VSS VSSQ E1
n
+1.35V_MEM_GFX H14 VSS VSSQ N1 H14 VSS VSSQ N1
VSS VSSQ VSS VSSQ
S IC D5 256M32 K4G80325FB-HC03 FBGA 170P S IC D5 256M32 H5GC8H24MJR-R0C BGA A31!
K14 R1 K14 R1
+1.35V_MEM_GFX VSS VSSQ U1 +1.35V_MEM_GFX VSS VSSQ U1
VSSQ VSSQ
r
H2 H2
G1 VSSQ K2 G1 VSSQ K2 UV13 UV13
B VDD VSSQ VDD VSSQ B
L1 A3 L1 A3
CV198
CV213
CV230
CV235
CV233
CV210
CV211
CV157
CV155
CV158
G4 VDD VSSQ C3 G4 VDD VSSQ C3

1 1 1 1 1 1 1 1 1 1 VDD VSSQ VDD VSSQ
SA00009U10L SA00009U11L
L4 E3 L4 E3
id
follow intel 1209 C5 VDD VSSQ N3 C5 VDD VSSQ N3 H4G_R1@ H4G_R3@
R5 VDD VSSQ R3 R5 VDD VSSQ R3
2 2 2 2 2 2 2 2 2 2 C10 VDD VSSQ U3 C10 VDD VSSQ U3 S IC D5 256M32 K4G80325FB-HC03 FBGA 170P S IC D5 256M32 H5GC8H24MJR-R0C BGA A31!
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ R10 VDD VSSQ C4 R10 VDD VSSQ C4
D11 VDD VSSQ R4 D11 VDD VSSQ R4
G11 VDD VSSQ F5 G11 VDD VSSQ F5
f
L11 VDD VSSQ M5 L11 VDD VSSQ M5
P11 VDD VSSQ F10 P11 VDD VSSQ F10
G14 VDD
VDD
VSSQ
VSSQ
M10 G14 VDD
VDD
VSSQ
VSSQ
M10 Micron R1 Micron R3
L14 C11 L14 C11
VDD VSSQ R11 VDD VSSQ R11
n
VSSQ A12 VSSQ A12 UV12
VSSQ C12 VSSQ C12 UV12
VSSQ E12 VSSQ E12
VSSQ VSSQ SA00009TV0L
N12 N12 SA00009TV1L
VSSQ R12 VSSQ R12 M4G_R1@
o
170-BALL VSSQ U12 170-BALL VSSQ U12 M4G_R3@
VSSQ H13 VSSQ H13
Stitching Caps OPTION for MEM signals that have a change of reference plane voltage
VSSQ VSSQ
S IC D5 256M32 K4G80325FB-HC03 FBGA 170P
Add stitching caps when required, one cap per three signals SGRAM GDDR5 K13 SGRAM GDDR5 K13 S IC D5 256M32 MT51J256M32HF-70:A A31!
VSSQ A14 VSSQ A14
c
VSSQ C14 VSSQ C14
VSSQ E14 VSSQ E14 UV13
VSSQ N14 VSSQ N14 UV13
VSSQ R14 VSSQ R14
VSSQ VSSQ
SA00009TV0L
SAM 4G 11/17 U14 U14 SA00009TV1L
l
VSSQ VSSQ M4G_R1@
H5GC4H24AJR-R0C_BGA170 H5GC4H24AJR-R0C_BGA170 M4G_R3@
S IC D5 256M32 K4G80325FB-HC03 FBGA 170P
S IC D5 256M32 MT51J256M32HF-70:A A31!
a
+1.35V_MEM_GFX
CV238
CV248
CV243
CV242
CV247
CV342
CV344
CV343
CV341
p
A
1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2
10U_0603_6.3V6M
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@

remove cap to share 11/26
m Security Classification
Compal Secret Data
co
GDDR5_A0
A00
5 4 3 2 1
5 4 3 2 1
clamshell configuration 11/26

MF=0 MF=1
UV14 @ UV15 @
M_DA[32..63] MF=0 MF=1 MF=1 MF=0 MF=0 MF=1 MF=1 MF=0

[37] M_DA[32..63]
A4 M_DA41 bit swap 12/09 A4 M_DA60
M_EDC_5 C2 DQ24 DQ0 A2 M_DA42 M_EDC_7 C2 DQ24 DQ0 A2 M_DA62 bit swap 12/09
C13 B4 M_DA43 C13 B4 M_DA63
M_EDC_6 R13 EDC1 EDC2 DQ26 DQ2 B2 M_DA40 M_EDC_4 R13 EDC1 EDC2 DQ26 DQ2 B2 M_DA61
[37] M_EDC_6
R2 EDC2 EDC1 L DQ27 DQ3 E4 M_DA47 L
[37] M_EDC_4
R2 EDC2 EDC1 H DQ27 DQ3 E4 M_DA57 H
Vinafix.com
y
EDC3 EDC0 DQ28 DQ4 EDC3 EDC0 DQ28 DQ4
+1.35V_MEM_GFX +1.35V_MEM_GFX BYTE0 DQ29 DQ5
E2 M_DA44
BYTE1
+1.35V_MEM_GFX BYTE3 DQ29 DQ5
E2 M_DA58
BYTE3
F4 M_DA46 F4 M_DA56
M_DBI5# D2 DQ30 DQ6 F2 M_DA45 M_DBI7# D2 DQ30 DQ6 F2 M_DA59
l
D [37] M_DBI5# DBI0# DBI3# DQ31 DQ7 [37] M_DBI7# DBI0# DBI3# DQ31 DQ7 D
D13 A11 D13 A11
M_DBI6# P13 DBI1# DBI2# DQ16 DQ8 A13 M_DBI4# P13 DBI1# DBI2# DQ16 DQ8 A13
1 DIS@ 2 M_CLK1 P2 B11 P2 B11
RV85 120_0402_1% DBI3# DBI0# DQ18 DQ10 B13 DBI3# DBI0# DQ18 DQ10 B13
DQ19 DQ11 DQ19 DQ11
n
M_CLK1 J12 E11 M_CLK1 J12 E11
[37] M_CLK1 CK DQ20 DQ12 CK DQ20 DQ12
M_CLK#1 J11 E13 M_CLK#1 J11 E13
[37] M_CLK#1 CK# DQ21 DQ13 CK# DQ21 DQ13
1 DIS@ 2 M_CLK#1 M_CKE1 J3 F11 M_CKE1 J3 F11
[37] M_CKE1 CKE# DQ22 DQ14 CKE# DQ22 DQ14
RV86 120_0402_1% F13 F13
DQ23 DQ15 U11 M_DA52 DQ23 DQ15 U11 M_DA33
DQ8 DQ16 DQ8 DQ16
o
M1_MA2 H11 U13 M_DA54 M1_MA4 H11 U13 M_DA32
M1_MA5 K10 T11 M_DA50 M1_MA3 K10 T11 M_DA34
[37] M1_MA5
M1_MA4 K11 BA1/A5 BA3/A3 H DQ10 DQ18 T13 M_DA55 H M1_MA2 K11 BA1/A5 BA3/A3 L DQ10 DQ18 T13 M_DA35
[37] M1_MA3
M1_MA3 H10
BA3/A3 BA1/A5
BYTE2 DQ12 DQ20
N11 M_DA49
BYTE2 M1_MA5 H10
BA3/A3 BA1/A5
BYTE1 DQ12 DQ20
N11 M_DA36 L
N13 M_DA53 N13 M_DA39
DQ13 DQ21 M11 M_DA48 DQ13 DQ21 M11 M_DA38
BYTE0
M1_MA7 K4 DQ14 DQ22 M13 M_DA51 M1_MA0 K4 DQ14 DQ22 M13 M_DA37
L
M1_MA6 K5 T4 M1_MA1 K5 T4
M1_MA8 J5 T2 M1_MA8 J5 T2
[37] M1_MA8 A12/RFU/NC DQ3 DQ27 A12/RFU/NC DQ3 DQ27
N4 N4
A5 DQ4 DQ28 N2 A5 DQ4 DQ28 N2
U5 VPP/NC DQ5 DQ29 M4 U5 VPP/NC DQ5 DQ29 M4
VPP/NC DQ6 DQ30 VPP/NC DQ6 DQ30
L
M2 +1.35V_MEM_GFX M2
DQ7 DQ31 DQ7 DQ31
RV116 2 DIS@ 1 1K_0402_1% J1 +1.35V_MEM_GFX RV117 2 DIS@ 1 1K_0402_1% J1 +1.35V_MEM_GFX
RV118 2 DIS@ 1 1K_0402_1% J10 MF RV119 2 DIS@ 1 1K_0402_1% J10 MF
RV120 2 DIS@ 1 121_0402_1% J13 SEN B1 RV121 2 DIS@ 1 121_0402_1% J13 SEN B1
ZQ VDDQ D1 ZQ VDDQ D1
VDDQ VDDQ
E
F1 F1
M_ADBI1 J4 VDDQ M1 M_ADBI1 J4 VDDQ M1
[37] M_ADBI1 ABI# VDDQ ABI# VDDQ
M_RAS#1 G3 P1 M_CAS#1 G3 P1
[37] M_RAS#1 RAS# CAS# VDDQ RAS# CAS# VDDQ
M_CS1B#0 G12 T1 M_WE#1 G12 T1
[37] M_CS1B#0 CS# WE# VDDQ CS# WE# VDDQ
M_CAS#1 L3 G2 M_RAS#1 L3 G2
[37] M_CAS#1 CAS# RAS# VDDQ CAS# RAS# VDDQ
M_WE#1 L12 L2 M_CS1B#0 L12 L2
[37] M_WE#1 WE# CS# VDDQ WE# CS# VDDQ
B3 B3
samsung R1 samsung R3
D
VDDQ D3 VDDQ D3
C VDDQ VDDQ C
F3 F3
M_WCKA1_0# D5 VDDQ H3 M_WCKA1_1# D5 VDDQ H3
M_WCKA1_0 D4 K3 M_WCKA1_1 D4 K3
M3 M3
M_WCKA1_1# P5 VDDQ P3 M_WCKA1_0# P5 VDDQ P3
r
M_WCKA1_1 P4 T3 M_WCKA1_0 P4 T3 UV14 UV14
E5 E5
VDDQ N5 VDDQ N5
VDDQ VDDQ
SA000092D0L SA000092D1L
+FB1_VREFDL A10 E10 +FB1_VREFDL A10 E10
U10 VREFD VDDQ N10 U10 VREFD VDDQ N10
o
S4G_R1@ S4G_R3@
+FB1_VREFCL J14 VREFD VDDQ B12 +FB1_VREFCL J14 VREFD VDDQ B12
VREFC VDDQ D12 VREFC VDDQ D12
VDDQ VDDQ
S IC D5 256M32 K4G80325FB-HC03 FBGA 170P S IC D5 256M32 K4G80325FB-HC28 FBGA A31!
F12 F12
f
VDDQ H12 VDDQ H12
DRAM_RST J2 VDDQ K12 DRAM_RST J2 VDDQ K12 UV15 UV15
[37,38] DRAM_RST RESET# VDDQ RESET# VDDQ
M12 M12
+1.35V_MEM_GFX VDDQ P12 VDDQ P12
VDDQ VDDQ SA000092D0L SA000092D1L
T12 +1.35V_MEM_GFX T12
l
VDDQ G13 VDDQ G13 S4G_R1@ S4G_R3@
VDDQ VDDQ
2.37K_0402_1%
H1 L13 H1 L13
VSS VDDQ VSS VDDQ
1
del cap 11/24 K1 B14 K1 B14 S IC D5 256M32 K4G80325FB-HC03 FBGA 170P S IC D5 256M32 K4G80325FB-HC28 FBGA A31!
VSS VDDQ VSS VDDQ
RV48 DIS@
B5 D14 B5 D14
a
G5 VSS VDDQ F14 G5 VSS VDDQ F14
L5 VSS VDDQ M14 L5 VSS VDDQ M14
T5 VSS VDDQ P14 T5 VSS VDDQ P14
CV162
CV166
CV216
CV221
CV219
CV165
CV164
CV161
CV153
CV160
i
Hynix R1 Hynix R3
2
B10 VSS VDDQ T14 B10 VSS VDDQ T14

VSS VDDQ 1 1 1 1 1 1 1 1 1 1 VSS VDDQ
D10 D10
VSS VSS
t
+FB1_VREFDL G10 G10
L10 VSS A1 L10 VSS A1
VSS VSSQ 2 2 2 2 2 2 2 2 2 2 VSS VSSQ
1U_0402_6.3V6K
5.49K_0402_1%
P10 C1 P10 C1 UV14 UV14
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
VSS VSSQ VSS VSSQ
1
T10 E1 T10 E1
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
1 VSS VSSQ VSS VSSQ
CV390 DIS@
RV49 DIS@
H14 N1 H14 N1 SA00009U10L SA00009U11L
n
K14 VSS VSSQ R1 K14 VSS VSSQ R1
+1.35V_MEM_GFX VSS VSSQ U1 +1.35V_MEM_GFX VSS VSSQ U1 H4G_R1@ H4G_R3@
2 VSSQ H2 VSSQ H2
2
VSSQ VSSQ
r
G1 K2 G1 K2 S IC D5 256M32 K4G80325FB-HC03 FBGA 170P S IC D5 256M32 H5GC8H24MJR-R0C BGA A31!
L1 VDD VSSQ A3 L1 VDD VSSQ A3
B VDD VSSQ VDD VSSQ B
G4 C3 G4 C3
L4 VDD VSSQ E3 L4 VDD VSSQ E3
C5 VDD VSSQ N3 C5 VDD VSSQ N3 UV15 UV15
id
R5 VDD VSSQ R3 R5 VDD VSSQ R3
C10 VDD VSSQ U3 C10 VDD VSSQ U3
VDD VSSQ VDD VSSQ SA00009U10L SA00009U11L
+1.35V_MEM_GFX R10 C4 R10 C4
D11 VDD VSSQ R4 D11 VDD VSSQ R4 H4G_R1@ H4G_R3@
G11 VDD VSSQ F5 G11 VDD VSSQ F5
VDD VSSQ VDD VSSQ
2.37K_0402_1%
L11 M5 Stitching Caps OPTION for MEM signals that have a change of reference plane voltage L11 M5 S IC D5 256M32 K4G80325FB-HC03 FBGA 170P S IC D5 256M32 H5GC8H24MJR-R0C BGA A31!
f
1
P11 VDD VSSQ F10 Add stitching caps when required, one cap per three signals P11 VDD VSSQ F10
VDD VSSQ VDD VSSQ
RV50 DIS@
G14 M10 G14 M10

L14 VDD VSSQ C11 SAM 4G 11/17 L14 VDD VSSQ C11
VDD VSSQ R11 VDD VSSQ R11
VSSQ A12 VSSQ A12
Micron R1 Micron R3
n
2
VSSQ C12 VSSQ C12

VSSQ E12 VSSQ E12
+FB1_VREFCL VSSQ N12 VSSQ N12
VSSQ R12 VSSQ R12 UV14
VSSQ VSSQ
1U_0402_6.3V6K
5.49K_0402_1%
170-BALL U12 170-BALL U12 UV14
o
1
VSSQ H13 VSSQ H13

1 VSSQ VSSQ SA00009TV0L
CV391 DIS@
RV51 DIS@
SGRAM GDDR5 K13 SGRAM GDDR5 K13 SA00009TV1L

VSSQ A14 VSSQ A14 M4G_R1@
VSSQ C14 VSSQ C14 M4G_R3@
c
2 VSSQ E14 VSSQ E14 S IC D5 256M32 K4G80325FB-HC03 FBGA 170P
2
VSSQ N14 VSSQ N14

VSSQ VSSQ
S IC D5 256M32 MT51J256M32HF-70:A A31!
R14 R14
VSSQ U14 VSSQ U14
VSSQ VSSQ UV15
l
H5GC4H24AJR-R0C_BGA170 H5GC4H24AJR-R0C_BGA170 UV15
SA00009TV0L
SA00009TV1L
M4G_R1@
a
M4G_R3@
+1.35V_MEM_GFX S IC D5 256M32 K4G80325FB-HC03 FBGA 170P
S IC D5 256M32 MT51J256M32HF-70:A A31!
A
p
A
CV225
CV227
CV170
CV169
CV173
CV335
CV334
CV336
CV333
1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2
10U_0603_6.3V6M
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
m
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
remove cap to share 11/26

co
GDDR5_A1
A00
5 4 3 2 1
5 4 3 2 1
Power-Up/Down Sequence 1. All the ASIC supplies must reach their respective nominal voltages within 20 ms
of the start of the ramp-up sequence, though a shorter ramp-up duration is
preferred. The maximum slew rate on all rails is 50 mV/µs.
2. It is recommended that the 3.3-V rail ramp up first.
3. It is recommended that the 0.95-V rail reach at least 90% of its nominal value
no later than 2 ms from the start of VDDC ramping up.
Vinafix.com
y
4. The power rails that are shared with other components on the system should be
gated for the dGPU so that when the dGPU is powered down (for example
l
AMD PowerXpress? idle state), all the power rails are removed from the dGPU.
D The gate circuits must meet the slew rate requirement (such as ? 50 mV/µs). D
5. VDDC and VDD_CT should not ramp up simultaneously. For example, VDDC
n
should reach 90% before VDD_CT starts to ramp up (or vice versa).
6. For power down, reversing the ramp-up sequence is recommended.
VDDR3(3.3V)
+3VGS
< 20mS
>10uS
< 20mS
MCP GPP_B13 PCH_PLTRST#
DGPU_HOLD_RST#
AND
GATE
PCH_PLTRST#_EC
AND
GATE
L
PLT_RST_VGA#
o PERSTB
GPU
L
(DGPU_PWR_EN) GPP_D10
PCIE_VDDC(0.95V) GPP_D13 PXS_PWREN
+0.95VSDGPU
E
(PXS_PWREN with RC delay) DGPU_PWROK
GPP_D18
1.8V_IO(1.8V)
+1.8VGS
(PXS_PWREN with RC delay)
D
VDDC/VDDCI(0.8~1.15V)
+VGA_CORE
(PXS_PWREN)
r
VMEMIO(1.35V or 1.5V) +3VS +3VGS
C +1.5V_MEM_GFX > 100mS > 100mS (SW) C
(DGPU_PWROK with RC delay)

LDO 1
o
PXS_PWREN
PWRGOOD
f
DGPU_PWROK
+1.0V_PRIM +0.95VSDGPU +1.8V_PRIM +1.8VGS
PERSTb
> 100uS LDO 2 LDO 2
l
PXS_PWREN PXS_PWREN
PLT_RST_VGA# Asserted Before PERSTb
a
REFCLK B+ +VGA_CORE +1.35V_MEM +1.35V_MEM_GFX
CLK_PEG_VGA/CLK_PEG_VGA# PWM 3 LDO 3
i
PXS_PWREN DGPU_PWROK
t
Device in Device Hardware Reset Device CFG Accessible Device Powering down Device Powered down
DEVICE Reset or Working
n
No requirements
id r
B
n f B
c o For AMD R16M-M30/M70 VRAM Only

Memory ID R3 P/N Vendor Configuration Size
l
Samsung 2G Hynix 2G Micron 2G SA00009U10L Hynix H5GC8H24MJR-R0C 2GB
100
RV15 2G_S@ RV16 2G_S@ RV15 2G_H@ RV16 2G_H@ RV15 2G_M@ RV16 2G_M@
2GB
a
011 SA000092D0L SAMSUNG K4G80325FB-HC28
2GB
101 SA00009TV0L Micron MT51J256M32HF-70:A
p
6.98K_0402_1% 4.99K_0402_1% 4.53K_0402_1% 4.99K_0402_1% 3.24K_0402_1% 5.62K_0402_1%
SD000002680 SD034499180 SD034453180 SD034499180 SD034324180 SD034562180
Memory ID R3 P/N Vendor Configuration Size
Samsung 4G Hynix 4G Micron 4G
RV16
m
4G_S@ RV15 4G_H@ RV16 4G_H@ RV15 4G_M@ 110 SA00009U10L Hynix H5GC8H24MJR-R0C 4GB
co
000 SA000092D0L SAMSUNG K4G80325FB-HC28 4GB
4.75K_0402_1% 3.4K_0402_1% 10K_0402_1% 4.75K_0402_1% 4GB

A
111 SA00009TV0L Micron MT51J256M32HF-70:A A
SD034475180 SD034340180 SD034100280 SD034475180
2015/5/19 Modify
Jason

M30/M70_NOTE
5 4 3 2 1
A B C D
@ PJP1
2 1
2 1
JUMP_43X79
EMI@ PL1
+19V_VIN PR4 PSID@
HCB3225KF-151T50_2P 33_0402_5%
@ PJPDC1 +19V_ADPIN 1 2 1 3 PSID-3 1 2 PS_ID [27]
S
8 PQ6 PSID@
GND 7 FDV301N_G 1N SOT23-3
GND
1000P_0402_50V7K
1000P_0402_50V7K
G
2
1
6
100K_0402_1%
2200P_0402_50V7K
2200P_0402_50V7K
6 PR8
2
5 PSID@ PR3 PSID@
5
Vinafix.com
EMI@ PC1
EMI@ PC2
EMI@ PC3
EMI@ PC4
PR6
4 2 1
PSID@
PSID-2 +5VALW 2.2K_0402_5%
4
3
3
2
3 2 @ PD4
2
2 1 1 2 10K_0402_1%
TVNST52302AB0_SOT523-3 +3VALW
1
1
1
1 EMI@ PL4 C 1
HCB3225KF-151T50_2P PSID-1 2
B
15K_0402_1%
ACES_50458-00601-001
MMST3904-7-F_SOT323
@ PJP2 E
3
PR9
2 1 3
PSID@
PSID@
@ PR11 +5VALW
2 1 1 2 1
JUMP_43X79 PL2 2
o
BLM15AG102SN1D_2P
1
100K_0402_1%
PQ5
PSID 2 1 @ PD5
EMI@
BAV99W_SC70-3
1
@ PD6
BAV99W_SC70-3
+17.4V_BATT+
L
@ PJP3
2 1 +17.4V_BATT++
+17.4V_BATT+
2 1
3
JUMP_43X79
L
EMI@ PL3
HCB3225KF-151T50_2P
1 2 +17.4V_BATT++
+5VALW
1
1000P_0402_50V7K
0.01U_0402_25V7K
1
PC8
1
E
1
EMI@ PC7
PD2 PD3
2
TVNST52302AB0_SOT523-3 TVNST52302AB0_SOT523-3
EMI@
ESD@ ESD@
3
D
2
3
Battery Bot Side
PIN1 GND BATT_TEMP [27,42]
r
@ PBATT1
1
PIN2 GND 1 2
2 3
PIN3 GND
2 2
PR15 PR16
3 4 SYS_PRES PR20 200_0402_5% 10K_0402_1%
o
PIN4 SYS_PRES 4 5 100_0402_5% 1 2 1 2
5 6 +3VALW
PIN5 BATT_PRS 6 7
DAT_SMB 1 2
f
CLK_SMB 1 2
PIN6 DAT_SMB 7 8
8 9 PR18
PIN7 CLK_SMB 9 10 100_0402_5%
10 11
PIN8 Batt+
l
GND 12 EC_SMB_CK1 [27,42]
PIN9 Batt+ GND
PIN10 Batt+
a
ACES_50458-01001-P01_10P-T
SP021412220 EC_SMB_DA1 [27,42]
i
Other component (37.1)
ACES_50458-01001-P01_10P-T
r n t
PH1 under CPU bottem side :
CPU thermal protection at 92 +/- 3 degree C
+EC_VCCA
2
id
PR24
15K_0402_1%
1
[27] VCIN0_PH
f
1
3 3
n PH1
2
100K_0402_1%_TSM0B104F4251RZ
o
[27] ECAGND
Adapter protection:
if battery removed, adaptor only,
then trigger the H_PROCHOT#,
l
Battery protection:
asserts H_PROCHOT# when adaptor is
unplugged, keep low for 10ms
c [27] ERP_LOT6
Erp lot6 Circuit
@ PR14
1
0_0402_5%
2
+19V_VIN
3.3K_1206_5%
a
keep @ in BOM since battery can not till SW PROCHOT# is issued by EC
1
be removed by end user [27,34,42] ACIN @ PR12 0_0402_5%
PR5
1 2
H_PROCHOT#
+3VALW
p
[8,9,27,42,48,49] H_PROCHOT# +19V_VIN @ PR7 @
2
10K_0402_1%
3 2
1
1M_0402_1%
[27,43] POK
PR28
@ PR13 0_0402_5%
6
PR31 PC16 1 2
L2N7002DW1T1G_SC88-6
2
.1U_0402_16V7K PQ1B
m
PQ2A
1M_0402_1% 5
3 2
PC14 1 2 2
6
.1U_0402_16V7K @
L2N7002WT1G_SC70-3
4
1
D
PQ2B
100K_0402_1%
@
1
1
1
PQ3
PQ1A
BATT_TEMP 1 2 2
co
PR10
PR29
G 5 2
1M_0402_1%
100K_0402_1%
S PR33 1M_0402_1%
3
1
1
PR2 1
@
4
1
PR32
1M_0402_1%
2
4
@ 4
2
DELL CONFIDENTIAL/PROPRIETARY
PWR_DCIN/BATT CONN/OTP
A B C D
A B C D
Iada=0~3.33A(65W)
Iada=0~2.30A(45W)
ADP_I = 32*Iadapter*Rsense
Vinafix.com
1
+19VB
l y 1
L2N7002WT1G_SC70-3
n
1
D
PQ709
2
G
S
3
2 1 2 1
PR738 PR737
1M_0402_1% 3M_0402_5%
PR703
L
PQ740 PQ718 0.01_1206_1%
MDU1512RH_POWERDFN56-8-5 MDU1512RH_POWERDFN56-8-5 EMI@ PL704
1 1 1 4 1 2
2 2
5 3 3 5 2 3 1UH_PCMB053T-1R0MS_7A_20%
2200P_0402_25V7K
1000P_0402_50V7K
1000P_0402_50V7K
0.1U_0402_25V7K
+19V_VIN
EMI@
EMI@
EMI@
EMI@
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
2
@ PJP701
5600P_0402_25V7K
1
PC744
PC760
PC762
PC763
PC764
1 2
1 2
2
PC765
PC705
PC780
PC781
1
1
1
0_0402_5%
0_0402_5%
2_0402_5%
JUMP_43X118
2
PC742
PR778
PR772
PR740
@ @ @
1
@ @ @
2
2
4.02K_0402_1%
PC747
0.1U_0402_25V6
2 1
r D
4.02K_0402_1%
2 2
o
1
MDU1512RH_POWERDFN56-8-5
f
PR745
392K_0402_1%
100_0402_1%
2
2
1
5
PR762
PR763
+17.4V_BATT+
PR729
1 2
PC750 0.22U_0603_25V7K
l @ PR773 0_0603_5%
2
1 2 4
a
0.01UF_0402_25V7K
L2N7002WT1G_SC70-3
i
1
53.6K_0402_1%
1
1
D
PR732
0.1U_0402_25V7K
3
2
1
t
PQ712
PC711
2
[27] ACOFF
PQ717
PC779
G CMSRC
1
2
S
1 VDD_CHG
3
@ ASGATE
1
n
5
@
AON7408L_DFN8-5
r
100K_0402_1%
32
31
30
29
28
27
26
25
PU703 ISL88739HRZ-T_QFN32_4X4
For Learn Mode
PQ704
PR741
3S1P: CV = 13.95V CC: 1.9A
CSIN
CMSRC
OPCN
VBAT
CSIP
ASGATE
QPCP
BGATE
PC721 4
id
PR771
2.2_0603_5% 0.22U_0402_16V7K
ACIN_CHG 1 24 1 2 1 2
2
ACIN BOOT @ PR761 0_0603_5% PR765

PL700
ACIN 2 23 UGATE_CHG 1 2 0.01_1206_1%
3
2
1
[27,34,41] ACIN @ PR769 0_0402_5% ACOK UGATE 4.7UH_5.5A_20%_7X7X3_M +17.4V_BATT+
1
f
1 2 3 22 PHASE_CHG 1 2 1 4
158K_0402_1%
[27,41] EC_SMB_DA1 SDA PHASE

PR731
@ PR770 0_0402_5%
1 2 4 21 LGATE_CHG 2 3
680P_0603_50V7K 4.7_1206_5%
[27,41] EC_SMB_CK1 SCL LGATE
@EMI@ PR766
PR777 0_0402_5%
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V7K
5
3
1 2 5 20 VDDP_CHG 3
AON7506_DFN33-8-5
2
[8,9,27,41,48,49] H_PROCHOT# PROH PR774 1K_0402_1% PROCHOT# VDOP
1
PC778
PC775
PC776
PC777
PC761
PC766
1 2 6 19 VDD_CHG 1 2
[27] ADP_I @ PR775 0_0402_5% AMON VDO
2
PQ708
1 2 7 18 PR760 4.7_0402_5%
2
[27] BATT_I BMON DCIN 4 @ @
1U_0402_16V6K
1U_0402_16V6K
2
2
8 17
BATGONE
PSYS NTC
@EMI@ PC767
100K_0402_1%
CCLIM
ACLIM
COMP
PROG
AGND
CSON
CSOP
PC768
PC769
c
FSET
2200P_0402_25V7K
0.1U_0402_25V7K
1
2
0_0402_5%
3
2
1
2
1
PR757
Delay adaptor OC H_PROCHOT#
1
2
PC748
PC749
PR727
33
10
11
12
13
14
15
16
3
2ms while hybrid power PQ710
l
transition
2
0_0603_5%
@ LMUN5113T1G_SOT323-3
2
PR780
2
+3VALW PD704
a 1U_0603_25V6
VDD_CHG
2
2
0_0402_5%
VDD_CHG PR743 10_1206_5%
+19V_VIN
1
PR779
H_PROCHOT# 1 2 1 @
1
1
2
PC757
3 BA
PR791
1
1
@ PR790
200K_0402_1%
200K_0402_1%
10K_0402_5% @
1
1
160K_0402_1% LRB715FT1G_SOT323-3 [9,27] PM_SLP_S5# 2
1
PR781 D CCLIM
2
2
PR749
PR750
10K_0402_5% 1 2 2 PQ721
G PQ711
0.01U_0402_16V7K
RUM002N02GT2L_VMT3
BA
2
RUM002N02GT2L_VMT3
10K_0402_1%
ACLIM
3
1
m
PC790
D S PROG 1 2 LTC015EUBFS8TL_UMT3F
3
PQ720
PROH 2
1
G COMP PR742 2_0402_5%

2
2
PC708
co
182K_0402_1%
100_0402_1%
102K_0402_1%
S 0.1U_0402_25V6
3
1
PR764
560P_0402_50V7K
1
2
PR753
PR754
PR755
1 2
2
75K_0402_1%
66.5K_0402_1%
PC751
@ PR756 @ PR776 0_0402_5%

1
4
10K_0402_1% 4
1
2
2
PR751
PR752
1 2
0.015U_0402_25V7K
+3VALW
1
10P_0402_50V8J
PC752
PC753
1
BATT_TEMP [27,41]
PWR_CHARGER
A B C D
A B C D E
Vinafix.com
1
EMI@ PL102
HCB3225KF-151T50_2P PR102
n l y 1
o
1 2 499K_0402_1%
ENLDO_3V5V 1 2
PR100 +19VB
@ PJP105 2.2_0603_5% PC102
1
150K_0402_1%
1 2 3V_VIN BST_3V1 2 1 2
+19VB 1 2
PR103
JUMP_43X79 0.1U_0402_10V7K
2200P_0402_50V7K
L
1000P_0402_50V7K
1
PU100
2
1000P_0402_50V7K
1000P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
EMI@ PC100
EMI@ PC103
EMI@ PC130
EMI@ PC131
BS
IN
IN
IN
IN
1
1
PC105
@ PC104
L
LX_3V 6 20 PL100
2 LX LX 1.5UH_9A_20%_7X7X3_M
2
7 19 LX_3V 1 2
GND LX +3VALWP
@EMI@ PR106
8 18
E
SY8286BRAC_QFN20_3X3
GND GND
4.7_1206_5%
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
9 17
PG LDO +3VLP
1
PC106
PC107
PC108
PC109
@ PC110
10 16
NC NC
3VALWP
D
OUT
2
EN2
EN1
1
21
NC
FF
GND PC111 TDC 4.6 A
1 3V_SN 2
PR107 4.7U_0603_6.3V6M
Peak Current 5.75 A
11
12
13
14
15
680P_0603_50V7K
10K_0402_1%
@EMI@ PC112
1 2
+3VALWP 3.3V LDO 150mA~300mA OCP Current 9 A fix by IC
ENLDO_3V5V
2 2
Vout is 3.234V~3.366V
o
POK [27,41]
2
POK
l f @ PJP102
150K_0402_1%
PC113 PR108 +3VALWP 1 2 +3VALW
1 2
1
@ PR109
1000P_0402_25V8J 1K_0402_5%
EN_3V 3V_FB 1 2 1 2 JUMP_43X118
EMI@ PL103
ia
2
HCB3225KF-151T50_2P
t
1 2
1
150K_0402_1%
@ PJP103
@ PR110
PR111 +5VALWP 1 2 +5VALW
@ PJP106 2.2_0603_5% PC114 1 2
n
1 2 5V_VIN BST_5V 1 2 1 2 JUMP_43X118
+19VB 1 2
2
r
JUMP_43X79 0.1U_0402_10V7K
2200P_0402_50V7K
1000P_0402_50V7K
1
1000P_0402_50V7K
1000P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
EMI@ PC115
EMI@ PC116
EMI@ PC132
EMI@ PC133
PU102
id
1
BS
IN
IN
IN
IN
PC117
PC118
LX_5V 6 20 PL101
2
LX LX 2.2UH_7.8A_20%_7X7X3_M
7 19 LX_5V 1 2
f
GND LX +5VALWP
8 SY8286CRAC_QFN20_3X3 18
GND GND
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
PR112
680P_0603_50V7K 4.7_1206_5%
3 PC119 3
1
n
@EMI@
9 17 1 2
PC120
PC121
PC122
PC123
PC124
PG VCC
10 16
2
NC NC 4.7U_0603_6.3V6M
15V_SN
@ PR121 0_0402_5%
o
OUT
LDO
2
EN2
EN1
21
FF
EN_3V 1 2 GND
11
12
13
14
15
c PC125
@ PR113
+3VALWP VL
@EMI@
@ PR120 0_0402_5% 10K_0402_1%
2
EN_5V 1 2 1 2
ENLDO_3V5V
5V LDO 150mA~300mA
l
1
EN_5V
PC126
4.7U_0603_6.3V6M
POK
PR114
a
2.2K_0402_5%
5VALWP
2
150K_0402_1%
1 2
TDC 6 A
1
[27] EC_ON
@ PR115
PD102
Peak Current 7.5 A
p
@ PR116 0_0402_5% SDMK0340L-7-F_SOD323-2
[27,28] VCOUT0_PH#
1 2 1 2 OCP Current 9 A fix by IC
2
4.7U_0402_6.3V6M
1
1
1
150K_0402_1%
PC128
m
PR122 PC127 PR117
@ PR118
1M_0402_5% 1000P_0402_25V8J 1K_0402_5%
5V_FB 1 2 1 2
2
co 2
EN1 and EN2 dont't floating
4 4
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL PWR_3.3VALWP/5VALWP
A B C D E
5 4 3 2 1
@ PR200
0_0603_5%
BST_1.2V_R 1 2 BST_1.2V
0.6Volt +/- 5%
+1.2VP TDC 1.2A
EMI@ PL201
Vinafix.com
y
HCB3225KF-151T50_2P Peak Current 1.5A
1
1 2
l
PC200
D 0.1U_0402_10V7K D
2
@ PJP206
n
+19VB 2 1 +19VB_1.2V UG_1.2V
2 1 +0.6VSP
JUMP_43X79
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
1000P_0402_50V7K
2200P_0402_50V7K
0.1U_0402_25V6
o
1
1
LX_1.2V
10U_0805_6.3V6K
10U_0805_6.3V6K
EMI@ PC208
EMI@ PC201
PC206
PC212
EMI@ PC230
@EMI@ PC231
1
PC205
PC211
2
16
17
18
19
20
@ PU200
2
VLDOIN
PHASE
UGATE
BOOT
VTT
21
PAD
LG_1.2V 15 1
L
LGATE VTTGND
14 2
PGND VTTSNS
1
PR205
E
PQ201 11K_0402_1%
D1
D1
D1
G1
AON7934_DFN3X3A8-10 1 2 CS_1.2V 13 3
+1.2V_MEM PC204 CS RT8207PGQW _W QFN20_3X3 GND
TDC 6.7 A 10
D1 D2/S1
9 1U_0603_10V6K
1 2 12 4 VTTREF_1.2V
D
Peak Current 8.375 A PR206 VDDP VTTREF
OCP Current 10.2 A 5.1_0603_5%
G2
S2
S2
S2
1 2 VDD_1.2V 11 5
VDD VDDQ +1.2VP
1
r
PGOOD
5
1
PC210
TON
+5VALW
1
C PR210 0.033U_0402_16V7K C
FB
S5
S3
2
PC209 2.2_0603_5%
o
1U_0603_10V6K @ PC214
10
6
220P_0402_25V8J
2
1 2
+5VALW
FB_1.2V
TON_1.2V
PR207
EN_1.2V
EN_0.6VSP
l
60.4K_0402_1%
1 2 +1.2VP
PR208
a
@ PR209 +19VB_1.2V 1 2
10K_0402_1%
453K_0402_1%
1
1 2
+3VALW
1
@ PC213
For RT8207P
t
@ PR201 PR204
.1U_0402_16V7K
0_0402_5% 100K_0402_1%
2
1 2
[27,45] SYSON
2
n
PL200
1UH_11A_20%_7X7X3_M
+1.2VP
1
r
1 2 @ PC202
0.1U_0402_10V7K
2
id
@ PR202
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
0_0402_5%
1 2
f
[26,27,46] SUSP#
1
1
@EMI@ PC207
PC220
PC218
PC217
PC216
PC215
PC219
1
B 680P_0402_50V7K B
n
2
@ PC203
2
@ 0.1U_0402_10V7K
2
1
c o @EMI@ PR203
4.7_1206_5%
@ PJP201
2
1 2
1 2
l
JUMP_43X118
@ PJP200
a
+1.2VP 1 2 +1.2V_DDR
1 2
JUMP_43X118
p
Mode S3 S5 +1.2V_MEN +V_DDR_REF +0.6V_P
S5 L L off off off
S3 L H on on off
m
S0 H H on on on 2
@ PJP203
1
+0.6VSP 2 1 +0.6V_DDR_VTT
co
JUMP_43X79
A A
PWR_+1.2V_MEN/+0.6V_DDR_VTT
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D
+1.8VALWP
1
@ PJP602
JUMP_43X79
1 2
2
l y
+1.8V_ALW
n
D
PJP601
PU600 RT8061AZQW_WDFN10_3X3 PL601
4
@ 1UH_6.6A_20%_5X5X3_M
1 2 10 2 LX_1.8VALW 1 2
+3VALW
PG
1 2 PVIN LX +1.8VALWP
JUMP_43X79 9 3
22P_0402_50V8J
PVIN LX
2
L
4.7_1206_5%
1
1
PC601 8 PR603
PC603
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
SVIN
1
22U_0603_6.3V6M
@EMI@ PR606
10_0402_5%
6 FB_1.8VALW
PC605
PC606
PC607
2
2
EN_1.8VALW 5 FB
2
EN
NC
NC
TP
1 2
@ PR601 FB=0.6Volt
11
1
0_0402_5% PR604
1 2
[27,47] 0.95_1.8VALW_PWREN
1
20K_0402_1%
680P_0402_50V7K
@EMI@ PC604
0.1U_0402_10V7K
2
PC602
2
1
PR602
1M_0402_5%
@
2
D
1
Vout=0.6V* (1+Rup/Rdown)
1
PR605
r
10K_0402_1%
2
C C
+1.8V_PRIM
o
TDC 2 A
Peak Current 2.5 A
f
OCP Current 3.5A fix by IC
ia l
+5VALW
r n t +2.5VP
PJP902 @
1
1
JUMP_43X79
2
2
+2.5V_MEM
1
PC901
id
1U_0402_6.3V6K
2
4 9 5
@
PJP901 VDD GND NC
1 2 2.5V_VIN 3 6
f
+3VALW 1 2 VIN VOUT +2.5VP
1
JUMP_43X79 2 7
21.5K_0402_1%
10U_0805_10V6K
EN ADJ
1
1
B B
1 8 @ PC903
PC902
PR901
n
10U_0805_10V6K
PGOOD GND
1
0.01U_0402_25V7K
2
PC904
2
PU900
2
RT9059GSP_SO8 ADJ_2.5V
o
@ PR903
1
0_0402_5%
1 2 EN_2.5V
+2.5V
c
[27,44] SYSON
PR902
10K_0402_1% TDC 0.72 A
Peak Current 0.9 A
2
1
0.1U_0402_10V6K
l
PC905
2
a
Vout=0.8V* (1+Rup/Rdown)
m p
co
A A
Title
PWR_+1.8V_PRIM and +2.5V
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C A00
5 4 3 2 1
A B C D
Vinafix.com
1
n l y 1
L o
E L
2
r D 2
o
PJP402 @
+5VALW
f
1 2
+1.5VSP 1 2 +1.5VS
1
@ PC401
1U_0402_6.3V6K JUMP_43X79
l
2
9
4 5
GND
PJP401 VDD NC
@
1 2 3 6
a
1.5VS_VIN
+1.8V_ALW 1 2 VIN VOUT +1.5VSP
1
JUMP_43X79 2 7
8.87K_0402_1%
10U_0805_10V6K
i
EN ADJ
1
1 8
PC402
PR401
@ PC404
10U_0805_10V6K
PGOOD GND
1
0.01U_0402_25V7K
PC405
2
@ @ PU400 @
2
RT9059GSP_SO8 ADJ_1.5VS
+1.5VSP
n
@
@ PR403 TDC 0.3 A
1
0_0402_5%
Peak Current 0.375 A
r
[26,27,44] SUSP# 1 2 EN_1.5VS @
PR402
10K_0402_1%
2
1
id
0.1U_0402_10V6K
PC403
2
n f Vout=0.8V* (1+Rup/Rdown)
3
c o
a l
m p
4
Compal Secret Data
PWR_1.5VSP
4
A B C D
5 4 3 2 1
@ PJP303
2 1
2 1
JUMP_43X79
EMI@ PL301
HCB3225KF-151T50_2P
+19VB_VDDP_ALWP 1 2
+19VB
Vinafix.com
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
2200P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
1
1
l
PC302
EMI@ PC303
PC304
PC308
EMI@ PC320
EMI@ PC321
+3VS
2
D D
@EMI@
TDC=8.8A
5
Peak Current=11A
AON6552_DFN5X6-8-5
@ @ PJP301
OCP=13.2A PR302 +0.95VALWP 1 2 +0.95VALW
o
100K_0402_5% 1 2
4 JUMP_43X118
PQ301
2
@ PJP302
@ PR303 PC305 1 2
PU300 0_0603_5% 0.1U_0402_10V7K 1 2
PR304 1 10 1
BST_VDDP_ALWP 2 1 2 JUMP_43X118
3
2
1
42.2K_0402_1% PGOOD VBST
L
@ PR301 1 2 TRIP_VDDP_ALWP 2 9 UG_VDDP_ALWP PL302
0_0402_5% TRIP DRVH 1UH_11A_20%_7X7X3_M
1 2 EN_VDDP_ALWP3 8 LX_VDDP_ALWP 1 2
[27,45] 0.95_1.8VALW_PWREN EN SW +0.95VALWP
FB_VDDP_ALWP4 7
VFB V5IN +5VALW
1
0.1U_0402_16V7K
L
RF_VDDP_ALWP5 6 LG_VDDP_ALWP
AON6554_DFN5X6-8-5
TST DRVL
220U_D2_2VY_R15M
220U_D2_2VY_R15M
@ PC301 PR305 @EMI@ 1 1
1
11 4.7_1206_5%
TP
1
+ +
PC307
PC310
2
2
PR306 S IC RT8237EZQW(2) WDFN 10P PC306 4
PQ302
E
470K_0402_1% 1U_0603_10V6K
1
PC309 @EMI@ 2 2
2
680P_0402_50V7K
3
2
1
2
C
1
PR307
3.48K_0402_1%
2
r D C
o
1
PR308
f
10K_0402_1%
2
ia l
r n t
B
n f id B
c o
a l
m p
co
A A

P45-PWR_VDDP_ALWP(+0.95V)
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C A00
5 4 3 2 1
5 4 3 2 1
@ PJP1001
2 1
2 1
JUMP_43X79
+19VB_APU EMI@ PL1001

HCB3225KF-151T50_2P
1 2 +19VB
2200P_0402_50V7K
1000P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
1 1
33U_25V_M
33U_25V_M
1000P_0402_50V7K
1000P_0402_50V7K
+ +
PC1000
PC1001
Vinafix.com
1
PC1002
PC1003
PR1012=3.65K, PR1003=1.5K and
1
PC1004
EMI@ PC1071
EMI@ PC1072
EMI@ PC1073
EMI@ PC1074
PR1000
330P_0402_50V7K 2K_0402_1%
PR1013=200 to set loadline -4mV/A 2 2
2
1 2 1 2 UG_NB
2
PR1002
[8] APU_VDDNB_SEN
D PR1003 PR1004 PC1006 PR1005 D
10_0402_5% 1.5K_0402_1% 137K_0402_1% 390P_0402_50V7K 34K_0402_1%
SH000011P00 (DCR:0.66m± 7% )
1
n
1 2 1 2 1 2 1 2 1 2
+APU_CORE_NB
D1
G1
PQ1001 PL1002
@ PR1006 PC1007 PC1008 AON6992_DFN5X6D-8-7 0.15UH_29A_20%_7X7X4_MOLDING
0_0402_5% 1000P_0402_50V7K 220P_0402_50V8J LX_NB 7 LX_NB 1 4
D2/S1
+APU_CORE_NB
o
1 2 1 2 1 2 1 2
VSUMP_NB PR1007 PR1008 PC1009 2 3
1
@ PC1010 301_0402_1% 2.2_0603_5% 0.22U_0402_16V7K @EMI@
2.61K_0402_1%
G2
S2
S2
S2
1
330P_0402_50V7K BST_NB 1 2 1 2 PR1010

10K_0402_5%_ERTJ0ER103J
PR1009
4.7_1206_5%
0.022U_0402_25V7K
APU_CORE_NB
6
1 2
0.1U_0603_16V7K
TDC 12A
680P_0603_50V7K
11K_0402_1%
PC1011
1 2
1
PR1012
Peak Current 17A
1 2
PC1012
L
3.65K_0603_1%
PR1011
LG_NB
@EMI@
PC1013
VSUMP_NB 1 2 OCP current 21.25A
Load line -4mV/A
2
2
PR1013 PR1014
2
PH1000
200_0402_1% 1_0402_1%
PR1013 set 200 ohm to OCP 21.25A VSUMN_NB 1 2
FSW=400kHz
2
L
VSUMN_NB 1 2
1
@ PR1015 @PC1015
PH1000 near APU_CORE_NB choke 100_0402_1% 220P_0402_50V7K LG_NB
PC1014 1 2 1 2
2
LX_NB
E
0.1U_0603_50V7K
UG_NB
PR1086
BST_NB
150K_0402_1% 13.3K_0402_1% PR1016
1 2 1 2
41
40
39
38
37
36
35
34
33
32
31
D
1 2 PU1001
TP
ISUMP_NB
ISUMN_NB
VSEN_NB
FB_NB
COMP_NB
PGOOD_NB
LGATE_NB
PHASE_NB
UGATE_NB
BOOT_NB
@ PH1001 470K_0402_5%_TSM0B474J4702RE
1 30
r
PH1001 near APU_CORE_NB H/S mos NTC_NB BOOT2
1 2 IMON_NB 2 29
PC1018 1000P_0402_50V7K IMON_NB UGATE2
C 3 28 C
PR1018 133K_0402_1% [8] APU_SVC SVC PHASE2
1 2
o
4 27 +5VS
[8,9,27,41,42,49] H_PROCHOT# VR_HOT_L LGATE2
@ PR1021 100K_0402_1%
1 2 5 26
f
+3VS [8] APU_SVD SVD VDDP
ISL62771HRTZ-T_TQFN40_5X5 PR1026
+1.8VS @1 PR1023 20_0402_5% VDDIO_APU6 25 1 2
VDDIO VDD 1_0603_5%
1U_0603_10V6K
1
@ PR1028 0_0402_5% 7 24 LG1_APU

[8] APU_SVT SVT LGATE1
1
1 2 @ PR1085
1U_0603_10V6K
l
+1.5VS
PC1064 1 2 8
ENABLE_APU 23 LX1_APU
[27,49] VR_ON
2
ENABLE PHASE1
PC1063
PC1055
0.1U_0402_25V6K
2
VDDIO pin: 1.8VS for DDRII voltage level 0_0402_5% 9 22 UG1_APU
[8,9,49] APU_PWRGD PWROK UGATE1
1.5VS for DDRIII voltage level
a
1 2 10
IMON_APU 21 BST1_APU
IMON BOOT1 +3VS
PR1076
PGOOD
i
133K_0402_1%
ISUMN
ISUMP
COMP
ISEN2
ISEN1
VSEN
NTC
RTN
1 2 PC1062 FB
1
t
1000P_0402_50V7K
PR1087 PR1080
11
12
13
14
15
16
17
18
19
150K_0402_1% 13.3K_0402_1% 20 PR1070

1 2 1 2 100K_0402_5%
2
n
PH1002 near APU_CORE H/S mos 1 2 +5VS
VGATE [9,27,49]
2
r
@ PH1002
10K_0402_1%
PR1081
470K_0402_5%_TSM0B474J4702RE
1
id
15W@ PC1068
PC1060 PR1073 150P_0402_50V8J PR1078
f
1000P_0402_50V7K 301_0402_1% 210K_0402_1%
VSUM+_APU 1 2 1 2 1 2 1 2
330P_0402_50V7K
+19VB_APU
@ PC1059
APU_core (FP4)
2.61K_0402_1%
1
B 15W@ PR1047 PR1077 PC1057 B
n
10K_0402_5%_ERTJ0ER103J
TDC 22A(15W)
0.022U_0402_25V7K
0.1U_0603_16V7K
PR1079
1.62K_0402_1% 137K_0402_1% 390P_0402_50V7K

11K_0402_1%
1
1 2 1 2 1 2
PC1066
2200P_0402_50V7K
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
Peak Current 35A(15W)
2
1
1
PR1071
PC1053
0.1U_0402_25V6K
0.1U_0402_25V6K
OCP current 42A(15W)
1 2
PR1065 PC1037
o
Load line -2.1mV/A
2
1
PC1070
PC1039
PC1067
@EMI@ PC1056
EMI@ PC1069
@EMI@ PC1075
@EMI@ PC1076
2K_0402_1% 330P_0402_50V7K
2
PR1084=3.65K, PR1047=1.62K and 1 2 1 2

PH1003 near APU_CORE choke PR1066=422 to set loadline -2.1mV/A FSW=400kHz
PH1003
2
15W@
c
PR1066 PR1051
2
422_0402_1% 10_0402_5% UG1_APU

VSUM-_APU 1 2 1 2
+APU_CORE
15W@ PQ1007 15W@ PQ1008
@ PC1061 @ PR1075 AON6994_DFN5X6D-8-7 AON6994_DFN5X6D-8-7
l
1
@ PR1072 820P_0402_50V7K 0_0402_5%

SH000011P00 (DCR:0.66m± 7% )
1
PC1065 100_0402_1% 1 2
0.1U_0603_50V7K 1 2 1 2 APU_VDD_SEN [8]
D1
G1
D1
G1
2
LX1_APU PL1004
a
0.15UH_29A_20%_7X7X4_MOLDING
PR1066 set 422 ohm to OCP 42A 1 2 PC1038 7 7 LX1_APU 1 4
PR1082
APU_VDD_RUN_FB_L [8] D2/S1 D2/S1
+APU_CORE
0.01U_0402_50V7K
PR1067 0.22U_0402_16V7K
0_0402_5% 10_0402_5% 1
BST1_APU 2 1 2 2 3
1
PC1058
@ PR1069 1 2 @EMI@
G2
G2
S2
S2
S2
S2
S2
S2
p
1
PR1074
2.2_0603_5% 4.7_1206_5% PR1084
2
6
3.65K_0603_1%
VSUM+_APU1 2
@EMI@
1 2
PC1054
LG1_APU 680P_0603_50V7K PR1068
m
1_0402_1%
1
VSUM-_APU 2
2
A
Compal Secret Data
PWR_APU_CORE/APU_CORE_NB
A
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D
n l y D
o
32.4K_0402_1%
10K_0402_1%
10K_0402_1%
2
1
+5VALW
L
PR534
GFX@ PR502
GFX@ PR503
1
2
GFX@
41
40
39
L VDDGFX
38
37
36
35
34
33
32
31
PU500
TDC 22A(15W)
TP
ISUMP_NB
ISUMN_NB
VSEN_NB
FB_NB
COMP_NB
PGOOD_NB
LGATE_NB
PHASE_NB
UGATE_NB
BOOT_NB
E
Peak Current 35A(15W)
GFX@ PR501
1
100K_0402_1%
2 1 30 @ PJP501
OCP current 42A(15W)
GFX@ PR504 100K_0402_1% NTC_NB BOOT2 2
2 1
1 Load line -2.1mV/A
1 2 2 29
IMON_NB UGATE2 JUMP_43X79
FSW=400kHz
D
3 28
[8] GFX_SVC SVC PHASE2
4 27 +5VS +19VB_GFX GFX@EMI@ PL501
[8,9,27,41,42,48] H_PROCHOT# VR_HOT_L LGATE2
@ PR505 100K_0402_1% HCB3225KF-151T50_2P
1 2 5 26 1 2
+3VS [8] GFX_SVD SVD VDDP +19VB
ISL62771HRTZ-T_TQFN40_5X5 GFX@ PR507
2200P_0402_50V7K
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
r
1@ PR506 20_0402_5% VDDIO_GFX6 25 1 2
0.1U_0402_25V6
0.1U_0402_25V6
+1.8VS VDDIO VDD 1_0603_5%
1U_0603_10V6K
1
@ PR508 0_0402_5% 7 24 LG1_GFX

[8] GFX_SVT SVT LGATE1
1
C 1 2 C
@EMI@ PC525
@EMI@ PC522
PC504
PC505
PC506
@EMI@ PC507
GFX@EMI@ PC508
@ PR509
1U_0603_10V6K
+1.5VS
GFX@ PC501 1 2 8 23
o
GFX@ PC503
EN_GFX ENABLE_GFX LX1_GFX
2
ENABLE PHASE1
GFX@ PC502
0.1U_0402_25V6K
2
0_0402_5% 9 22 UG1_GFX
[8,9,48] APU_PWRGD PWROK UGATE1
f
1 2 IMON_GFX 10 21 BST1_GFX
GFX@ PR510 IMON BOOT1 +3VS
PGOOD
133K_0402_1%
ISUMN
ISUMP
COMP
ISEN2
ISEN1
VSEN
UG1_GFX
NTC
RTN
1 2 FB
l
1
1000P_0402_50V7K GFX@15W@ GFX@15W@
GFX@ PC509 GFX@ PR512 GFX@ PR513 PQ501 PQ502
11
12
13
14
15
16
17
18
19
150K_0402_1% 13.3K_0402_1% 20 @ PR511 AON6994_DFN5X6D-8-7 AON6994_DFN5X6D-8-7

1 2 1 2 100K_0402_1%
SH000011P00 (DCR:0.66m± 7% )
1
2
LX1_GFX
D1
G1
D1
G1
GFX@ PL502
i
PH501 near VDDGFX H/S mos 1 2 +5VS
VGATE [9,27,48] GFX@ PR514 GFX@ PC510 0.15UH_24A_20%_7X7X4_MOLDING
@ PH501 2.2_0603_5% 0.22U_0402_16V7K 7 7 LX1_GFX 1 4
D2/S1 D2/S1
+APU_CORE_GFX
2
t
470K_0402_5%_TSM0B474J4702RE GFX_PWRGD [9,27,48] BST1_GFX 1 2 1 2
2 3
10K_0402_1%
GFX@ PR515
@EMI@
G2
G2
S2
S2
S2
S2
S2
S2
1
PR516
4.7_1206_5%
1
6
n
GFX@ PR517
3.65K_0603_1%
GFX@15W@ @EMI@ VSUM+_GFX1 2
1 2
r
PC513 LG1_GFX PC511
GFX@ PC512 GFX@ PR519 150P_0402_50V8J GFX@ PR520 680P_0603_50V7K GFX@ PR518
270P_0402_50V7K 301_0402_1% 210K_0402_1% 1_0402_1%
VSUM+_GFX 1 2 1 2 1 2 1 2 1
VSUM-_GFX 2
2
330P_0402_50V7K
id
@ PC514
GFX@15W@ GFX@ GFX@

2.61K_0402_1%
1
PR521 PR522 PC515

10K_0402_5%_ERTJ0ER103J
0.1U_0603_16V7K
GFX@ PR523
0.022U_0402_25V7K
1.62K_0402_1% 137K_0402_1% 390P_0402_50V7K

11K_0402_1%
1
1 2 1 2 1 2
2
1
1
GFX@ PR524
GFX@ PC517
GFX@ PC516
GFX@ GFX@
f
1 2
PR525 PC518
2
2K_0402_1% 330P_0402_50V
2
1 2 1 2
PH502 near VDDGFX choke
GFX@ PH502
B GFX@15W@ B
n
PR526 GFX@ PR527
2
422_0402_1% 10_0402_5%
VSUM-_GFX 1 2 1 2 +APU_CORE_GFX
GFX@ PC520
o
@ PR529
1
GFX@ PR528 0.01U_0402_25V7K 0_0402_5%

PC519 GFX@ 1K_0402_1% 1 2
0.1U_0603_50V7K 1 2 1 2 APU_COREGFX_SEN_H [8]
2
c
1 2
APU_COREGFX_SEN_L [8]
0.01U_0402_50V7K
GFX@ PR531
@ PR530
0_0402_5% 10_0402_5%
1
GFX@ PC521
1 2
l
2
a
GFX@ PR532
47K_0402_1%
1 2
[27,48] VR_ON
EN_GFX
p
GFX@ PR533
1
10K_0402_1% D
1 2 2 GFX@
[9] GFX_VR_ON
G PQ504
L2N7002WT1G_SC70-3
1000P_0402_50V7K
S
3
1
m
PC523
Compal Secret Data
Deciphered Date 2017/01/07
Title
PWR_VDDGFX
A
5 4 3 2 1
A B C D
+3VALW +1.8V_ALW
1
PJP803 PJP801
1
JUMP_43X79 JUMP_43X79
2
@ @
2
Vinafix.com
y
PU800
1
VIN NC
8 +3VALW
l
2 7
GND NC
1
1 1
1
PC801 3 6 PC802
4.7U_0805_6.3V6K PR802 VREF VCNTL
2
1.33K_0402_1% 4 5 1U_0603_10V6K
VOUT NC
9
2
TP
o
G2992F1U_SO8
@ PR801
.1U_0402_16V7K
VDDCR_FCH_S5
1
0_0402_5% D
PC803
1 2 2
[27] 0.775PW_EN
1K_0402_1%
1
G
2
1
S PR803 PC804
3
L
@ PC805 PQ801 10U_0603_6.3V6M
2
0.1U_0402_10V7K
2
L2N7002WT1G_SC70-3
VDDCR_FCH_S5
@
2
PJP802
2
JUMP_43X79
1
1 +0.775VALW
E L
2
r D 2
l f o
t ia
r n
3
n f id 3
c o
a l
m p
4
Compal Secret Data
PWR_1.5V/VDDCR_FCH_S5
4
A B C D
5 4 3 2 1
Vinafix.com +3VS
@ PJP1402
l y
1
D D
+1.35VGPUP 1 2 +1.35V_MEM_GFX
PR1401 @ 1 2
n
VGA@EMI@ PL1402 100K_0402_5% JUMP_43X118
HCB3225KF-151T50_2P @EMI@ PR1408 @EMI@ PC1408
1 2 4.7_1206_5% 680P_0603_50V7K
2
VGA@ 1 2 SNUB_+1.35VGPU 1 2
o
PU1400
@ PJP1401 VGA@
+19VB 1
1 2
2 +19VB_+1.35VGPU 2
IN PG
9 @ PR1402
0_0603_5%
PC1407
0.1U_0402_10V7K VGA@
0.1U_0402_25V6
10U_0805_25V6K
0.1U_0402_25V6
3 1 BST_+1.35VGPU 1 2BST_+1.35VGPU_R1 2
2200P_0402_50V7K
2200P_0402_50V7K
JUMP_43X79 IN BS PL1401
1
VGA@EMI@ PC1401
@EMI@ PC1402
VGA@ PC1403
@EMI@ PC1420
@EMI@ PC1421
4
IN LX
6 LX_+1.35VGPU 1 2
+1.35VGPUP
330P_0402_50V7K
2
2
5 19 1UH_6.6A_20%_5X5X3_M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
IN LX
2
VGA@
1
VGA@
7 20 PR1409
PC1409
VGA@ PC1411
VGA@ PC1412
VGA@ PC1413
VGA@ PC1414
GND LX 10_0402_5%
8 14 FB_+1.35VGPU
2
GND FB
R1
1
@ PR1403 18 17 LDO_+1.35VGPU
0_0402_5% GND VCC 1 2
1
1 2 EN_+1.35VGPU 11 10 VGA@
[27,52] DGPU_PWROK EN NC PC1406 PR1410
E
ILMT_+1.35VGPU 13 12 2.2U_0402_6.3V6M 30.1K_0402_1%
2
ILMT NC
1
VGA@ @ PC1404 VGA@

+3VALW1
1
PR1404 0.1U_0402_25V6 2 15 16 FB=0.6V
1M_0402_1% BYP NC
2
@ PR1405 21 PR1411
+3VALW 0_0402_5% PAD Vout=0.6V* (1+R1/R2) R2 24K_0402_1%
D
2
SY8286RAC_QFN20_3X3 =0.6*(1+(30.1/24)) VGA@
2
1
VGA@
PC1405
Vout=1.35V
1
1U_0402_6.3V6K
2
@ PR1406
r
0_0402_5%
C C
2
o
1
@ PR1407
+1.35VGPU
f
0_0402_5%
TDC 4.9A
Peak Current 6.125A
2
OCP current 9A
The current limit is set to 6A, 9A or 12A when this pin

is pull low, floating or pull high
ia l
t
OCP setting ILMT(pin13)
6A Pull low
12A
9A Floating
Pull high
r n
B
n f id B
c o
a l
m p
co
A A

PWR_+1.35VGPU
5 4 3 2 1
5 4 3 2 1
+19VB_GPU @ PJP1101
2 1
2 1
JUMP_43X79
VGA@EMI@ PL1101
HCB3225KF-151T50_2P
1 2
+19VB
2200P_0402_50V7K
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
Vinafix.com
0.1U_0402_25V6K
0.1U_0402_25V6K
l
1
VGA@ PC1103
VGA@ PC1104
VGA@ PC1105
@EMI@ PC1106
VGA@EMI@ PC1107
@EMI@ PC1140
@EMI@ PC1141
AON6552_DFN5X6-8-5
D D
2
n
VGA@ PQ1101
UG2_VGA 4
SH000011H00 (DCR:0.98m± 5%)
3
2
1
10K_0402_1% VGA@
10K_0402_1% VGA@
@ VGA@ PL1102
0.22UH_24A_20%_7X7X4_MOLDING
LX2_VGA 1 4
32.4K_0402_1%
@ PR1103
VGA@
PC1108 VGA@ PR1104 2 3
+VGA_CORE
0_0603_5% 0.22U_0402_16V7K @EMI@ 10K_0402_1%
1
BST2_VGA 1 2 1 2 PR1107 ISEN2_VGA1 2
1
L
4.7_1206_5%
VGA@ PR1108
5
3.65K_0603_1%
AON6554_DFN5X6-8-5
AON6554_DFN5X6-8-5
+5VALW 1 2
PR1140
PR1105
PR1106
@EMI@ VSUM+_VGA
1 2
PC1109
VGA@ PQ1102
VGA@ PQ1103
680P_0603_50V7K VGA@ PR1110
L
1_0402_1%
LG2_VGA 4 4 1
VSUM-_VGA 2
2
VGA@
41
40
39
38
37
36
35
34
33
32
31
PU1100
TP
ISUMP_NB
ISUMN_NB
VSEN_NB
FB_NB
COMP_NB
PGOOD_NB
LGATE_NB
PHASE_NB
UGATE_NB
BOOT_NB
3
2
1
3
2
1
E
VGA_CORE
VGA@ PR1101 100K_0402_1% TDC 28A(M70)
1 2 1 30 BST2_VGA
VGA@ PR1111 100K_0402_1% NTC_NB BOOT2 Peak Current 42A(M70)
1 2 2
IMON_NB UGATE2
29 UG2_VGA OCP current 50A(M70)
Load line -1mV/A with M70
D
3 28 LX2_VGA
[34] SVI2_SVC SVC PHASE2
4 27 LG2_VGA +5VALW
FSW=300kHz
[34] OCP_L VR_HOT_L LGATE2
@ PR1112 100K_0402_1%
1 2 5 26
+3VS [34] SVI2_SVD SVD VDDP +19VB_GPU
ISL62771HRTZ-T_TQFN40_5X5 VGA@ PR1114
r
+1.8VGS 1@ PR1113 2 0_0402_5% 6
VDDIO_VGA 25 1 2
VDDIO VDD 1_0603_5%
1U_0603_10V6K
1
@ PR1115 0_0402_5% @ PR1116 7 24 LG1_VGA
2200P_0402_50V7K
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
[34] SVI2_SVT SVT LGATE1
1
C 1 2 C
0_0402_5%
1U_0603_10V6K
0.1U_0402_25V6
0.1U_0402_25V6
+3VGS
PC1101 1 2 8 23
o
VGA@ PC1111
ENABLE_VGA LX1_VGA
[9,26] PXS_PWREN
2
ENABLE PHASE1
VGA@ PC1110
0.1U_0402_25V6K
1
PWRGD_VGA 9 22 UG1_VGA
VGA@ PC1112
VGA@ PC1113
VGA@ PC1114
@EMI@ PC1115
VGA@EMI@ PC1116
@EMI@ PC1142
@EMI@ PC1143
VGA@
PWROK UGATE1
AON6552_DFN5X6-8-5
1 2 IMON_VGA 10 21 BST1_VGA
2
IMON BOOT1 +3VS
PR1117 VGA@
PGOOD
VGA@ PQ1104
133K_0402_1%
ISUMN
ISUMP
COMP
ISEN2
ISEN1
VSEN
UG1_VGA 4
NTC
RTN
1 2 VGA@ FB
l
1
1000P_0402_50V7K VGA@ VGA@
PC1117 PR1120 PR1121 VGA@ PR1122 SH000011H00 (DCR:0.98m± 5%)
11
12
13
14
15
16
17
18
19
150K_0402_1% 13.3K_0402_1% 20 VGA@ PR1119 0_0402_5%
3
2
1
1 2 1 2 100K_0402_1% 1 2 VGA@ PL1103
a
DGPU_PWROK [27,51] 0.22UH_24A_20%_7X7X4_MOLDING
2
LX1_VGA 1 4
VGA@ +VGA_CORE
i
PH1101 near GPU_CORE H/S mos 1 2 PWRGD_VGA [9] @ PR1123 PC1118 VGA@ PR1124 2 3
@ PH1101 0_0603_5% 0.22U_0402_16V7K @EMI@ 10K_0402_1%
1
t
470K_0402_5%_TSM0B474J4702RE PC1119 VGA@ BST1_VGA 1 2 1 2 PR1125 ISEN1_VGA1 2
0.22U_0402_10V6K 4.7_1206_5%
1 2 ISEN2_VGA VGA@ PR1126
5
3.65K_0603_1%
AON6554_DFN5X6-8-5
AON6554_DFN5X6-8-5
PC1120 VGA@ @EMI@ VSUM+_VGA1 2
1 2
n
0.22U_0402_10V6K PC1121
1 2
VGA@ PQ1105
VGA@ PQ1106
VSUM-_VGA ISEN1_VGA 680P_0603_50V7K VGA@ PR1128
1_0402_1%
r
VGA@ VGA@ VGA@ PC1123 LG1_VGA 4 4 1
VSUM-_VGA 2
2
PC1122 PR1129 180P_0402_50V8J @ PR1130
1000P_0402_50V7K 301_0402_1% 121K_0402_1%
VSUM+_VGA 1 2 1 2 1 2 1 2
PR1131 VGA@
330P_0402_50V7K
3
2
1
3
2
1
id
@ PC1124
VGA@ VGA@
2.61K_0402_1%
VGA@ PR1133
1
PR1134 PC1127
10K_0402_5%_ERTJ0ER103J
0.033U_0402_16V7K
0.15U_0603_16V7K
1K_0402_1% 137K_0402_1% 390P_0402_50V7K

11K_0402_1%
1
1 2 1 2 1 2
2
1
1
VGA@ PR1132
VGA@ PC1125
VGA@ PC1126
VGA@ VGA@
f
1 2
PR1135 PC1128
2
2K_0402_1% 330P_0402_50V
2
1 2 1 2
PH1102 near GPU_CORE choke
VGA@
PH1102
B VGA@ B
n
PR1136
2
470_0402_1%
VSUM-_VGA 1 2
@ PC1130
o
@ PR1138
1
VGA@ @ PR1137 820P_0402_50V7K 0_0402_5%

PC1129 100_0402_1% 1 2
0.1U_0603_50V7K 1 2 1 2 VCCSENSE_VGA [34]
2
c
1 2
VSSSENSE_VGA [34]
0.01U_0402_50V7K
@ PR1139
0_0402_5%
1
VGA@ PC1131
l
2
pa
m
A
Compal Secret Data
Title
PWR_VGA_CORE
A
5 4 3 2 1
5 4 3 2 1
APU_CORE
+APU_CORE_NB APU_CORE_NB +VDDGFX +VDDGFX
+APU_CORE 470uF*3
470uF*2 470uF*3
+APU_CORE +APU_CORE_NB +APU_CORE_GFX
Vinafix.com
l y
470U_X_2VY_R9M
470U_X_2VY_R9M
470U_X_2VY_R9M
470U_X_2VY_R9M
470U_X_2VY_R9M
470U_X_2VY_R9M
470U_X_2VY_R9M
470U_X_2VY_R9M
D 1 1 1 1 1 1 1 1 D
n
+ + + + + + + +
PC954
PC955
PC956
PC959
PC960
GFX@ PC967
GFX@ PC969
GFX@ PC968
2 2 2 2 2 2 2 2
+APU_CORE +APU_CORE_NB +APU_CORE_GFX
L o
L
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
PC911
PC912
PC913
PC914
PC915
PC916
PC917
PC931
PC932
PC933
PC934
PC941
PC942
PC943
PC944
PC945
PC946
PC947
PC948
PC949
PC950
2@ 2@ 2@ 2@ 2@ 2@ 2 2@ 2@ 2@ 2@
D
2@ 2@
E 2@ 2@ 2 2 2 2 2 2
f o r C
ia l
r n t
B
n f id B
c o +VGA_CORE
l 330U_2V_M
330U_2V_M
330U_2V_M
330U_2V_M
1 1 1 1
a PC836
PC837
PC838
PC839
+ + + +
2 2 2 2
p VGA@
VGA@
VGA@
VGA@
m
A
Compal Secret Data
Title
PWR_PROCESSOR DECOUPLING
A
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D Power block
n l y D
o
APU OTP
Page 41
Turn Off
DC IN
Input
Switch
Page 42
+19VB
+3VALWP: TDC:4.9A
+5VALWP: TDC:6A
L L EC_ON
E
SY8286BRAC/SY8286CRAC Page 43
C +3VALW
RT8061AZQW
r D
+1.8V_ALWP: TDC:2A 0.95_1.8VALW_PWREN C
CHARGER (HPB)
CV:13.5V CC:1.84A (3S1P) - 42Wh
ISL88739HRZ-T
l
+3VALW
f o +1.5VSP: TDC:0.3A
RT9059GSP
Page 46
SUSP#
Page 42
t ia +3VALW +1.8VGSP: TDC:0.5A

Page 45
n
Battery PXS_PWREN
RT9059GSP
id r +3VALW +VDDCR_FCH_S5: TDC:0.2A

Page 52
EC_ON
f
+VGA_CORE G2992F1U
B
PXS_PWREN TDC: 28A Page 50 B
n
ISL62771HRTZ-T
Page 53
c o +3VALW +2.5VP: TDC:0.2A

RT9059GSP
Page 52
SYSON
VR_ON
a l +APU_CORE
TDC: 22A
ISL62771HRTZ-T +VDDP_ALWP: TDC:8.8A
RT8237EZQW
0.95_1.8VALW_PWREN
p
Page 48
Page 47
m
+1.2VP/+0.6VSP: TDC:6.7A/1.2A SYSON
+APU_CORE_NB RT8207PGQW
co
VR_ON TDC: 12A Page 44
ISL62771HRTZ-T
A Page 48 A
+1.35VGPUP: TDC:3.5A PXS_PWREN

SY8286RAC
Page 51
+VDDGFX
GFX_VR_ON TDC: 22A Security Classification Compal Secret Data Compal Electronics, Inc.
ISL62771HRTZ-T PWR_POWER BLOCK DIAGRAM
Page 49 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
5 4 3 2 1
5 4 3 2 1
Version Change List ( P. I. R. List )

Vinafix.com Page 1
D
Item Page#
1 42
Title
CHARGER
Date
Request
2016/3/24
Owner
COMPAL customer recommend
Issue Description Solution Description
change PU703 from SA00009RO00 to SA00009Q50L
n l y
Rev.
0.2
D
3
42
42
CHARGER
CHARGER
2016/3/24
2016/3/24
COMPAL
COMPAL
adjust T/V setting
design change
change PR732 from 49.9K to 53.6K
add PC751 560P

change PR774 from 0 to 1K
change PC748 from 2200P to 0.1U
delete PC760 PC761 PC764
L o 0.2
0.2
L
4 46 +1.5VSP 2016/3/24 COMPAL change power rail from 1.5V to 1.8V by EE side delete all 1.5VS component 0.2
E
5 48 APU_CORE 2016/3/24 COMPAL design change to adjust APU_CORE setting delete PC1010 0.2
change PR1005 from 11.5K to 34K
D
6 49 VDD_GFX 2016/3/24 COMPAL design change to adjust GFX_CORE setting add PR534 32.4K 0.2
r
7 52 VGA_CORE 2016/3/24 COMPAL design change from EE recommend add PR1119 100K 0.2
C C
o
8 41 DCIN/BATT CONN/OTP 2016/5/06 COMPAL adjust OTP setting from thermal recommend change PR24 from 14K to 16.9K 0.3
f
9 41 DCIN/BATT CONN/OTP 2016/5/06 COMPAL design change to remove Erp lot6 circuit delete PR2,PR5,PR7,PR10,PQ1 0.3
l
10 44 +1.2V_MEN/+0.6V_DDR 2016/5/06 COMPAL adjust OCP setting change PR205 from 8.25K to 11K 0.3
a
11 42 CHARGER 2016/5/06 COMPAL design change change PQ740 from SB000014900 to SB00000SY00 0.3
12
13
53
41
PROCESSOR DECOUPLING
DCIN/BATT CONN/OTP
2016/5/06
2016/6/16
COMPAL
COMPAL design change from EMI recommend
n t
design change to meet stardust test result
i add PC917,PC945,PC946,PC947,PC948,PC949,PC950
change PC2,PC4 from 0.1U to 2200P

0.3
1.0
14
15
43
41
3.3VALWP/5VALWP
DCIN/BATT CONN/OTP
2016/6/16
2016/6/16
COMPAL
COMPAL
design change
adjust OCP setting
id r change PR103 from 499K to 150K

1.0
1.0
n f B
c o
a l
m p
A
Compal Secret Data
PWR-PIR
A
5 4 3 2 1
5 4 3 2 1
DVT1 change list
Item Page Date Rev. Reason for change Modify Item
Vinafix.com
D
n l y D
L o
E L
C
r D C
l f o
t ia
r n
B
n f id B
c o
a l
m p
co
A A

HW-PIR-1
5 4 3 2 1
5 4 3 2 1
DVT2 change list

Item Page Rev. Reason for change Modify Item
Date
Vinafix.com
D
n l y D
L o
E L
C
r D C
XB change list
l f o
Item Page Date Rev. Reason for change
t iaModify Item
r n
B
n f id B
c o
a l
m p
co
A A

HW-PIR-2
5 4 3 2 1

Bal22 La d803p

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Bal22 La d803p

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5 4 3 2 1

PROJECT NAME : BAL22 15" , BAL32 17"

Dell / Compal Confidential

KBBL@:for KB backlight use

DP0 eDP USB 3.0 Port 1

r n Port 0 Card Reader

m Int.KBD ENE KBC PS/2

FAN CONN Page 24

I/O BOARD POWER BOARD LED BOARD Thermal Sensor

Q2516 , Q135, Q2513 AO3416L

Security Classification Compal Secret Data Compal Electronics, Inc.

Board ID Table for AD channel

SOURCE BATT Charger DIMM Thermal

CLKOUT_PCIE0 10/100 LAN

m p : means Analog Ground

Security Classification Compal Secret Data Compal Electronics, Inc.

SMBus Block Diagram RPC64

BA15 APU_SCLK0 253 DIMM1 SMBUS Address [ ]

R16 DIS@ RV5 45.3K

Security Classification Compal Secret Data Compal Electronics, Inc.

Main Func = CPU

U10 P_GPP_RXP[0] P_GPP_TXP[0] R1 PCIE_ATX_DRX_P0 CC2241 2 .1U_0402_16V7K

PEG_GTX_C_HRX_P0 P10 M2 PEG_HTX_C_GRX_P0

PEG_GTX_C_HRX_P1 N6 P_GFX_RXP[1] P_GFX_TXP[1] L1 PEG_HTX_C_GRX_P1

APU R1 APU R3 FP4_BGA968

S IC FX-9800P FM980PADY44AB 2.7G BGA 968P S IC FX-9800P FM980PADY44AB 2.7G A31!

S IC A10-9600P AM960PADY44AB 2.4G BGA 968P S IC A10-9600P AM960PADY44AB 2.4G A31!

Security Classification Compal Secret Data Compal Electronics, Inc.

Main Func = CPU

MA_DATA[16] G22 DDRA_SDQ16 MB_DATA[16] E30 DDRB_SDQ16

EVENT# pull high

m p 0.6V reference voltage

+1.2V_DDR change to pop 11/30

Main Func = CPU reserve 0 ohm 11/24

A7 DP2_TXP[2] del edp hpd buffer 10/28

+1.8VS RC81 1 2 300_0402_5% APU_PWRGD C19 PWROK reserve 0 ohm 11/24

RPC25 EC_SMB_CK2 3 4 APU_SIC

3 8 1 APU_SID QC79A FP4 REV 0.93 3

change to 0.01u 10/19

Security Classification Compal Secret Data Compal Electronics, Inc.

Main Func = CPU VBIOS VBIOS_ID3 VBIOS_ID2 VBIOS_ID1 +3VS

(PCBA VRAM Size Config.) (AGPIO102) (AGPIO64) (AGPIO66)

VDD_33_S5 APU_RST# [8]

AN8 IR_RX1/AGPIO15 AGPIO9 AK5 RC22 0_0402_5%

SA00004BV00 LAN_CLKREQ# BC15 INPUT AG8 GFX_PWRGD_APU 2 @ 1 GFX_VR_ON:

follow check list 11/11 EC_RSMRST# 1 2 EC_RSMRST#_R

Main Func = CPU

+0.95VS RC96 2 1 1K_0402_1% SATA_ZVDD AW2 SATA_ZVDDP USB_HSD3P AN3 USB20_JUSB1_P3

48M_X2 T1 X48M_X2 USB_SS_0RXP W9

Main Func = CPU

+1.2V_DDR P25 VDDIO_MEM_S3_1 VDDCR_CPU_1 U8 +APU_CORE +APU_CORE

2 RC119 0_0402_5% CC1005 1U_0402_6.3V6K

AN12 VDDP_S5_1 VDDCR_GFX_16 L16

+RTC_APU_R +RTC_APU_R AR17 VDDBT_RTC_G VDDCR_GFX_11 K15

CC166 CC923 @ for Clear CMOS 2 2

Main Func = CPU

Security Classification Compal Secret Data Compal Electronics, Inc.

Main Func = DIMM1 DDRA_SDQ[0..63]

Main Func = DIMM2

AMD Bristol LA-D803P PR01

+INV_PWR_SRC For LCD

+VDDCR_FCH_ALW) PU100 PJP100 +3VALW U2302 3VS +3VS

Security Classification Compal Secret Data Compal Electronics, Inc.

Main Func = LCD