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  • GS452 GS552 GS752 NM-C781 PDF

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    Tintaytoner Zumpango
    246 views61 pages
    This document is a schematic for a CometLake_U42 laptop with DDR4 RAM and an Nvidia GPU. It contains confidential information about the laptop's hardware components and their connections. The schematic shows the Intel CPU, DDR4 SO-DIMM memory, Nvidia GPU, SATA and NVMe storage interfaces, USB, display, audio and network ports and controllers. It also lists components like the touchpad, sensors and chips managing power and thermal monitoring.

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    datasheet lenovo gs452

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    This document is a schematic for a CometLake_U42 laptop with DDR4 RAM and an Nvidia GPU. It contains confidential information about the laptop's hardware components and their connections. The schematic shows the Intel CPU, DDR4 SO-DIMM memory, Nvidia GPU, SATA and NVMe storage interfaces, USB, display, audio and network ports and controllers. It also lists components like the touchpad, sensors and chips managing power and thermal monitoring.

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    © All Rights Reserved
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    246 views61 pages

    GS452 GS552 GS752 NM-C781 PDF

    Uploaded by

    Tintaytoner Zumpango
    This document is a schematic for a CometLake_U42 laptop with DDR4 RAM and an Nvidia GPU. It contains confidential information about the laptop's hardware components and their connections. The schematic shows the Intel CPU, DDR4 SO-DIMM memory, Nvidia GPU, SATA and NVMe storage interfaces, USB, display, audio and network ports and controllers. It also lists components like the touchpad, sensors and chips managing power and thermal monitoring.

    Copyright:

    © All Rights Reserved
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    of 61

    A B C D E

    LCFC NM-C781
    1 1

    GS452/GS552/GS752 MB Schematics Document


    2 CometLake_U42 with DDR4 + Nvidia N16V-GM 2

    2018-01
    REV:0.1

    3 3

    4 4

    Security Classification LC Future Center Secret Data Title

    Issued Date 2015/08/20 Deciphered Date 2016/08/20 Cover Page


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    Size Document Number
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS441/FS540
    Date: Wednesday, October 16, 2019 Sheet 1 of 61
    A B C D E
    A B C D E

    NV N16x/N17x
    Package: FCBGA595 Memory Bus DDR4 SO-DIMM+MDx4
    1 PCI-Express 1.2V DDR4 Page 17/18 1

    4x Gen3
    VRAM: 256*32
    GDDR5*2: 2GB x1

    USB3.0 USB3.0 Conn


    HDMI (DDI 1) x1
    HDMI Conn.

    eDP x2
    eDP Conn x1

    Intel MCP
    SATA x1 x1
    SATA HDD Redriver for 17''
    comet Lake-U42 15W USB2.0 x1 USB3.0 Conn
    2 2

    NGFF PCI-Express
    SSD 4x Gen3
    USB2.0 Conn
    BGA-1528
    NGFF PCIe x1 46mm*24mm
    USB2.0 x1
    WLAN&BT x1
    FP Conn

    SPK Conn.
    Page 30
    HD Audio x1 SPI SPI ROM (16MB)
    Realtek W25Q128JVSIQ
    Page 07
    HP&Mic RTS5199
    3
    Combo Conn. USB2.0 x1 3

    Page 30 Page 43

    I2C Touch Pad


    Page 45
    Page 3~16

    SD Conn. LPC

    IO Board EC GPIO
    ITE IT8586E-LQFP128 HALL Sensor
    Page 44

    Int.KBD
    Page 45
    Thermal Sensor
    F75303M Page 39

    4 4

    Security Classification LC Future Center Secret Data Title


    Issued Date 2015/08/20 Deciphered Date 2016/08/20 Block Diagram
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS441/FS540
    Date: Wednesday, October 16, 2019 Sheet 2 of 61
    A B C D E
    A B C D E

    Voltage Rails ( O --> Means ON , X --> Means OFF )


    SIGNAL
    STATE SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

    Full ON HIGH HIGH HIGH ON ON ON ON


    Power Plane
    S3 (Suspend to RAM) LOW HIGH HIGH ON ON OFF OFF
    +3VALW +5VS

    +5VALW +1.2V +3VS S4 (Suspend to Disk) LOW LOW LOW ON OFF OFF OFF
    1 +VCCIO 1
    S5 (Soft OFF) LOW LOW LOW ON OFF OFF OFF
    V20B+ +3VALW_PCH +2.5V_DDR +VCCSTG
    +VCCSA
    +1.8VALW +VCCST +VCC_GT
    +1.05VALW +CPU_CORE
    State +0.6VS
    HSIO PORT Function BOM Structure BTO Item
    1 USB3.0 Conn @ Un-stuff
    2 USB3.0 Conn 14@ For 14" part
    3 NC 15@ For 15" part
    USB3.0 4 NC YOGA@ For YOGA530 part
    S0 O O O O 5 NC 530@ For 530S part
    6 NC
    1 USB3.0 Conn
    S3 O O O X 2 NC
    3 USB3.0 Conn CD@ For C cost down
    4 USB2.0 conn
    S3
    2
    Battery only O O O X USB2.0 5 Card reader EMC@ For EMC part 2

    6 Touch Screen EMC_15@ For EMC 15" part


    7 EMC_NS@
    S5 S4 Camera For EMC un-stuff part
    AC Only O O X X 8 NC EMC_PX@ For EMC PX part
    9 NC EMC_PXNS@ For EMC PX nu-stuff part
    10
    S5 S4 Bluetooth
    Battery only O X X X 5~8 DGPU
    X4
    S5 S4 ME@ For ME part
    9 WLAN
    AC & Battery X X X X PCIE 10 NC
    don't exist
    11 SATA HDD
    12 NC OPT@ For NV GPU part
    SMBUS Control Table 13~16 OPTN16@ For NV N16S-GTR GPU part
    PCIE/SATA SSD
    X4 OPTN17@ For NV N17S-G1 GPU part
    SOURCE BATT Charger DGPU IT8586E Memory PCH PMIC SODIMM Thermal WLAN
    Down Sensor WiMAX

    3 3
    EC_SMB_CK1 IT8586E
    V V X V X X X X X X
    EC_SMB_DA1 +3VL_EC +3VL_EC

    EC_SMB_CK2 IT8586E
    X X V V X V X X V X
    EC_SMB_DA2 +3VS +3VG_AON +3VS +3VALW_PCH TS@ For touch screen part
    TP@ For TOuch Pad Part
    EC_SMB_CK3 IT8586E UMA@
    X X X V X X V X X X For UMA part
    EC_SMB_DA3 +3VL_EC +3VL_EC

    PCH_SMB_CLK PCH
    X X X X X V X V X V
    PCH_SMB_DATA +3VALW_PCH +3VALW_PCH +3VS +3VS

    EC SMBus1 address EC SMBus2 address EC SMBus3 address PCH SM Bus address


    Device Address Device Address Device Address Device Address
    Smart Battery need to update Thermal Sensor(NCT7718W) 1001_100xb PMIC need to update DDR4 SODIMM need to update
    4 4
    Charger 0001 0010 b PCH need to update Wlan Reserved
    DGPU need to update

    Security Classification LC Future Center Secret Data Title

    Issued Date 2015/08/20 Deciphered Date 2016/08/20 Notes List


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS441/FS540
    Date: Wednesday, October 16, 2019 Sheet 3 of 61
    A B C D E
    5 4 3 2 1

    UC1A

    DDP*_CTRLDATA strapping sampled on the rising edge of PCH_PWROK CPU_HDMI_TXN2 AL5 AG4 CPU_EDP_TX0-
    34 CPU_HDMI_TXN2 CPU_HDMI_TXP2 DDI1_TXN_0 EDP_TXN_0 CPU_EDP_TX0+ CPU_EDP_TX0- 33
    HDMI D2 AL6 AG3
    34 CPU_HDMI_TXP2 CPU_HDMI_TXN1 DDI1_TXP_0 EDP_TXP_0 CPU_EDP_TX1- CPU_EDP_TX0+ 33
    AJ5 AG2
    34 CPU_HDMI_TXN1 CPU_HDMI_TXP1 AJ6 DDI1_TXN_1 EDP_TXN_1 AG1 CPU_EDP_TX1+ CPU_EDP_TX1- 33
    Port Strap Enable Disable HDMI D1 34 CPU_HDMI_TXP1 DDI1_TXP_1 EDP_TXP_1 CPU_EDP_TX1+ 33
    CPU_HDMI_TXN0 AF6 AJ4
    34 CPU_HDMI_TXN0 CPU_HDMI_TXP0 AF5 DDI1_TXN_2 EDP_TXN_2 AJ3
    GPP_E19 / Pull up to 3.3 V NC HDMI D0 34 CPU_HDMI_TXP0 DDI1_TXP_2 EDP_TXP_2
    Port 1 DDPB_CTRLDATA / with 2.2Kohm CPU_HDMI_CLKN AE5 AJ2
    D
    CNV_BT_IF_SELECT
    * HDMI CLK
    34
    34
    CPU_HDMI_CLKN
    CPU_HDMI_CLKP
    CPU_HDMI_CLKP AE6 DDI1_TXN_3
    DDI1_TXP_3
    EDP_TXN_3
    EDP_TXP_3
    AJ1 D

    GPP_E21 / Pull up to 3.3 V NC AC4


    AC3 DDI2_TXN_0 AH4 CPU_EDP_AUX#
    Port 2 DDPC_CTRLDATA with 2.2Kohm
    * AC1 DDI2_TXP_0
    DDI2_TXN_1
    EDP_AUX_N
    EDP_AUX_P
    AH3 CPU_EDP_AUX CPU_EDP_AUX#
    CPU_EDP_AUX
    33
    33
    GPP_E23 / Pull up to 3.3 V NC AC2
    AE4 DDI2_TXP_1 AM7
    Port 3 DDPD_CTRLDATA with 2.2Kohm * AE3 DDI2_TXN_2
    DDI2_TXP_2
    DISP_UTILS
    GPP_H17/ Pull up to 3.3 V NC AE1 AC7
    AE2 DDI2_TXN_3 DDI1_AUX_N AC6
    Reserve DPPF_CTRLDATA with 2.2Kohm * DDI2_TXP_3 DDI1_AUX_P
    DDI2_AUX_N
    AD4 +3VS
    AD3
    DDI2_AUX_P AG7
    100Ohm for CNL DDI3_AUX_N AG6
    DDI3_AUX_P

    2
    +VCCIO&EDP_COMP : RC404
    CN6 CPU_HDMI_HPD
    Trace Width: 20mil GPP_E13/DDPB_HPD0/DISP_MISC0 CPU_HDMI_HPD 34 10K_0402_5%
    Isolation Spacing: 25mil CM6
    GPP_E14/DDPC_HPD1/DISP_MISC1 CP7 CNVI_EN# RC432
    Max length: 100mil CNVI_EN# 40

    1
    GPP_E15/DPPD_HPD2/DISP_MISC2 CP6 GPP_E16 1 2 EC_SCI#
    GPP_E16/DPPE_HPD3/DISP_MISC3 CPU_EDP_HPD EC_SCI# 44
    CM7 0_0402_5%
    GPP_E17/EDP_HPD/DISP_MISC4 CPU_EDP_HPD 33
    CK11 PCH_ENBKL Change EC_SCI# to GPP_E16 based on CRB
    EDP_BKLTEN CG11 PCH_ENVDD PCH_ENBKL 33,44
    EDP_VDDEN PCH_ENVDD 33
    CH11 PCH_EDP_PWM
    EDP_BKLTCTL PCH_EDP_PWM 33
    +VCCIO

    RC406 2 1 24.9_0402_1% DP_COMP_OBS_DP AM6


    DISP_RCOMP
    PCH_HDMI_DDC_CLK CC8
    34 PCH_HDMI_DDC_CLK GPP_E18/DPPB_CTRLCLK/CNV_BT_HOST_WAKE#
    PCH_HDMI_DDC_DATACC9
    34 PCH_HDMI_DDC_DATA GPP_E19/DPPB_CTRLDATA RPC806
    CH4 CPU_EDP_HPD 1 4
    CH3 GPP_E20/DPPC_CTRLCLK PCH_ENVDD 2 3
    GPP_E21/DPPC_CTRLDATA
    100K_0404_4P2R_5%
    +3VS
    C CP4 C
    RPC401 CN4 GPP_E22/DPPD_CTRLCLK
    1 4 PCH_HDMI_DDC_CLK GPP_E23/DPPD_CTRLDATA
    2 3 PCH_HDMI_DDC_DATA CR26
    CP26 GPP_H16/DDPF_CTRLCLK
    2.2K_0404_4P2R_5% GPP_H17/DDPF_CTRLDATA

    @ 1 of 20
    WHISKEYLAKE-U_BGA1528

    +VCCSTG

    +VCCST_CPU

    2
    +VCCSTG

    1
    R95
    RC407 51_0402_1%
    1

    49.9_0402_1%
    @ UC1D
    RC408

    1
    1K_0402_5% 2 AA4 T6 PROC_TCK 1
    CATERR# IT13
    44 H_PECI CATERR# PROC_TCK PROC_TDI
    AR1 U6 1 IT10
    H_PECI
    2

    RC409 1 2 499 +-1% 0402 H_PROCHOT#_R Y4 PECI PROC_TDI Y5 PROC_TDO 1 IT9


    44,55 H_PROCHOT# H_THRMTRIP# PROCHOT# PROC_TDO PROC_TMS
    +VCCST_CPU RC410 2 1 1K_0402_5% BJ1 T5 1 IT11
    THRMTRIP# PROC_TMS AB6 PROC_TRST# 1 IT20
    PROC_TRST#

    2
    1 XDP_BPM0# U1
    PAD @ TC403 XDP_BPM1# BPM#_0 PCH_TCK
    1 U2 W6 1 IT12 RC176
    PAD @ TC404 XDP_BPM2# BPM#_1 PCH_TCK PROC_TDI
    1 U3 U5 51_0402_1%
    PAD @ TC405 1 XDP_BPM3# U4 BPM#_2 PCH_TDI W5 PROC_TDO
    PAD @ TC406 BPM#_3 PCH_TDO PROC_TMS
    P5

    1
    PCH_TMS Y6 PROC_TRST#
    PCH_TRST# P6 PROC_TCK
    B PCH_JTAGX B
    1 GPP_E3 CE9 W2 PROC_PREQ# 1 IT22
    PAD @ TC407 GPP_E3/CPU_GP0PROC_PREQ# PROC_PRDY# 1
    CN3 W1 IT21
    CB34 GPP_E7/CPU_GP1 PROC_PRDY#
    CC35 GPP_B3/CPU_GP2
    GPP_B4/CPU_GP3
    RC413 1 2 49.9_0402_1% PROC_OPI_RCOMP BP27
    RC414 1 2 49.9_0402_1% PCH_OPI_RCOMP BW25 PROC_POPIRCOMP
    L5 PCH_OPIRCOMP
    N5 RSVD35
    RSVD36

    4 of 20
    WHISKEYLAKE-U_BGA1528
    @

    A A

    Security Classification LC Future Center Secret Data Title

    Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (DDI,EDP)


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS441/FS540
    Date: Wednesday, October 16, 2019 Sheet 4 of 61
    5 4 3 2 1
    5 4 3 2 1

    UC1B
    V32
    DDR0_CKN_0/DDR0_CKN_0 V31 DDRA_CLK0# 17
    17 DDRA_DQ[0..15] DDRA_DQ0 DDR0_CKP_0/DDR0_CKP_0 DDRA_CLK0 17
    A26 T32
    DDRA_DQ1 D26 DDR0_DQ_0/DDR0_DQ_0 DDR0_CKN_1/DDR0_CKN_1 T31
    DDRA_DQ2 D28 DDR0_DQ_1/DDR0_DQ_1 DDR0_CKP_1/DDR0_CKP_1
    DDRA_DQ3 C28 DDR0_DQ_2/DDR0_DQ_2 U36
    D DDRA_DQ4 B26 DDR0_DQ_3/DDR0_DQ_3 DDR0_CKE_0/DDR0_CKE_0 U37 DDRA_CKE0 17 D
    DDRA_DQ5 C26 DDR0_DQ_4/DDR0_DQ_4 DDR0_CKE_1/DDR0_CKE_1 U34
    DDRA_DQ6 B28 DDR0_DQ_5/DDR0_DQ_5 DDR0_CKE_2/NC U35
    DDRA_DQ7 A28 DDR0_DQ_6/DDR0_DQ_6 DDR0_CKE_3/NC
    DDRA_DQ8 B30 DDR0_DQ_7/DDR0_DQ_7 AE32
    DDRA_DQ9 D30 DDR0_DQ_8/DDR0_DQ_8 DDR0_CS#_0/DDR0_CS#_0 AF32 DDRA_CS0# 17
    DDRA_DQ10 B33 DDR0_DQ_9/DDR0_DQ_9 DDR0_CS#_1/DDR0_CS#_1 AE31
    DDRA_DQ11 D32 DDR0_DQ_10/DDR0_DQ_10 DDR0_ODT_0/DDR0_ODT_0 AF31 DDRA_ODT0 17
    DDRA_DQ12 A30 DDR0_DQ_11/DDR0_DQ_11 NC/DDR0_ODT_1
    DDRA_DQ13 C30 DDR0_DQ_12/DDR0_DQ_12 AC37
    DDRA_DQ14 DDR0_DQ_13/DDR0_DQ_13 DDR0_CAB_9/DDR0_MA_0 DDRA_MA0 17
    B32 AC36
    DDRA_DQ15 DDR0_DQ_14/DDR0_DQ_14 DDR0_CAB_8/DDR0_MA_1 DDRA_MA1 17
    C32 AC34
    17 DDRA_DQ[32..47] DDRA_DQ32 H37 DDR0_DQ_15/DDR0_DQ_15 DDR0_CAB_5/DDR0_MA_2 AC35 DDRA_MA2 17
    DDRA_DQ33 DDR0_DQ_16/DDR0_DQ_32 NC/DDR0_MA_3 DDRA_MA3 17
    H34 AA35
    DDRA_DQ34 K34 DDR0_DQ_17/DDR0_DQ_33 NC/DDR0_MA_4 AB35 DDRA_MA4 17
    DDRA_DQ35 DDR0_DQ_18/DDR0_DQ_34 DDR0_CAA_0/DDR0_MA_5 DDRA_MA5 17
    K35 AA37
    DDRA_DQ36 DDR0_DQ_19/DDR0_DQ_35 DDR0_CAA_2/DDR0_MA_6 DDRA_MA6 17
    H36 AA36
    DDRA_DQ37 DDR0_DQ_20/DDR0_DQ_36 DDR0_CAA_4/DDR0_MA_7 DDRA_MA7 17
    H35 AB34
    DDRA_DQ38 DDR0_DQ_21/DDR0_DQ_37 DDR0_CAA_3/DDR0_MA_8 DDRA_MA8 17
    K36 W36
    DDRA_DQ39 K37 DDR0_DQ_22/DDR0_DQ_38 DDR0_CAA_1/DDR0_MA_9 Y31 DDRA_MA9 17
    DDRA_DQ40 DDR0_DQ_23/DDR0_DQ_39 DDR0_CAB_7/DDR0_MA_10 DDRA_MA10 17
    N36 W34 DDRA_MA11 17
    DDRA_DQ41 N34 DDR0_DQ_24/DDR0_DQ_40 DDR0_CAA_7/DDR0_MA_11 AA34
    DDR0_DQ_25/DDR0_DQ_41 DDR0_CAA_6/DDR0_MA_12 DDRA_MA12 17
    DDRA_DQ42 R37 AC32
    DDRA_DQ43 R34 DDR0_DQ_26/DDR0_DQ_42 DDR0_CAB_0/DDR0_MA_13 DDRA_MA13 17
    DDRA_DQ44 N37 DDR0_DQ_27/DDR0_DQ_43 AC31
    DDRA_DQ45 DDR0_DQ_28/DDR0_DQ_44 DDR0_CAB_2/DDR0_MA_14 DDRA_MA14_WE# 17
    N35 AB32
    DDRA_DQ46 DDR0_DQ_29/DDR0_DQ_45 DDR0_CAB_1/DDR0_MA_15 DDRA_MA15_CAS# 17
    R36 Y32
    18 DDRB_DQ[0..15] DDRA_DQ47 DDR0_DQ_30/DDR0_DQ_46 DDR0_CAB_3/DDR0_MA_16 DDRA_MA16_RAS# 17
    R35
    DDRB_DQ0 AN35 DDR0_DQ_31/DDR0_DQ_47 W32
    DDRB_DQ1 AN34 DDR0_DQ_32/DDR1_DQ_0 DDR0_CAB_4/DDR0_BA_0 AB31 DDRA_BS0# 17
    DDRB_DQ2 AR35 DDR0_DQ_33/DDR1_DQ_1 DDR0_CAB_6/DDR0_BA_1 V34 DDRA_BS1# 17
    DDRB_DQ3 DDR0_DQ_34/DDR1_DQ_2 DDR0_CAA_5/DDR0_BG_0 DDRA_BG0 17
    AR34
    C DDRB_DQ4 AN37 DDR0_DQ_35/DDR1_DQ_3 V35 C
    DDRB_DQ5 DDR0_DQ_36/DDR1_DQ_4 DDR0_CAA_8/DDR0_ACT# DDRA_ACT# 17
    AN36 W35
    DDRB_DQ6 AR36 DDR0_DQ_37/DDR1_DQ_5 DDR0_CAA_9/DDR0_BG_1 DDRA_BG1 17
    DDRB_DQ7 AR37 DDR0_DQ_38/DDR1_DQ_6 C27 DDRA_DQS#0 DDRA_DQS#[0..1]
    DDRB_DQ8 DDR0_DQ_39/DDR1_DQ_7
    DDR0_DQSN_0/DDR0_DQSN_0 DDRA_DQS0 17 DDRA_DQS#[0..1]
    AU35 D27
    DDRB_DQ9 AU34 DDR0_DQ_40/DDR1_DQ_8
    DDR0_DQSP_0/DDR0_DQSP_0 D31 DDRA_DQS#1 DDRA_DQS[0..1]
    DDRB_DQ10 DDR0_DQ_41/DDR1_DQ_9
    DDR0_DQSN_1/DDR0_DQSN_1 DDRA_DQS1 17 DDRA_DQS[0..1]
    AW35 C31
    DDRB_DQ11 AW34 DDR0_DQ_42/DDR1_DQ_10
    DDR0_DQSP_1/DDR0_DQSP_1 J35 DDRA_DQS#4 DDRA_DQS#[4..5]
    DDRB_DQ12 AU37 DDR0_DQ_43/DDR1_DQ_11
    DDR0_DQSN_2/DDR0_DQSN_4 J34 DDRA_DQS4 17 DDRA_DQS#[4..5]
    DDRB_DQ13 AU36 DDR0_DQ_44/DDR1_DQ_12
    DDR0_DQSP_2/DDR0_DQSP_4 P34 DDRA_DQS#5 DDRA_DQS[4..5]
    DDRB_DQ14 AW36 DDR0_DQ_45/DDR1_DQ_13
    DDR0_DQSN_3/DDR0_DQSN_5 P35 DDRA_DQS5 17 DDRA_DQS[4..5]
    DDRB_DQ15 AW37 DDR0_DQ_46/DDR1_DQ_14
    DDR0_DQSP_3/DDR0_DQSP_5 AP35 DDRB_DQS#0 DDRB_DQS#[0..1]
    18 DDRB_DQ[32..47] DDRB_DQ32 BA35 DDR0_DQ_47/DDR1_DQ_15
    DDR0_DQSN_4/DDR1_DQSN_0 AP34 DDRB_DQS0 18 DDRB_DQS#[0..1]
    DDRB_DQ33 BA34 DDR0_DQ_48/DDR1_DQ_32
    DDR0_DQSP_4/DDR1_DQSP_0 AV34 DDRB_DQS#1 DDRB_DQS[0..1]
    DDRB_DQ34 DDR0_DQ_49/DDR1_DQ_33
    DDR0_DQSN_5/DDR1_DQSN_1 DDRB_DQS1 18 DDRB_DQS[0..1]
    BC35 AV35
    DDRB_DQ35 BC34 DDR0_DQ_50/DDR1_DQ_34
    DDR0_DQSP_5/DDR1_DQSP_1 BB35 DDRB_DQS#4 DDRB_DQS#[4..5]
    DDRB_DQ36 DDR0_DQ_51/DDR1_DQ_35
    DDR0_DQSN_6/DDR1_DQSN_4 DDRB_DQS4 18 DDRB_DQS#[4..5]
    BA37 BB34
    DDRB_DQ37 BA36 DDR0_DQ_52/DDR1_DQ_36
    DDR0_DQSP_6/DDR1_DQSP_4 BF34 DDRB_DQS#5 DDRB_DQS[4..5]
    DDRB_DQ38 DDR0_DQ_53/DDR1_DQ_37
    DDR0_DQSN_7/DDR1_DQSN_5 DDRB_DQS5 18 DDRB_DQS[4..5]
    BC36 BF35
    DDRB_DQ39 BC37 DDR0_DQ_54/DDR1_DQ_38
    DDR0_DQSP_7/DDR1_DQSP_5
    DDRB_DQ40 BE35 DDR0_DQ_55/DDR1_DQ_39 W37
    DDRB_DQ41 DDR0_DQ_56/DDR1_DQ_40 NC/DDR0_ALERT# DDRA_ALERT# 17
    BE34 W31
    DDRB_DQ42 BG35 DDR0_DQ_57/DDR1_DQ_41 NC/DDR0_PAR F36 DDRA_PAR 17
    DDRB_DQ43 DDR0_DQ_58/DDR1_DQ_42 DDR_VREF_CA DDR_SA_VREFCA 17
    BG34 D35 SMVREF
    DDRB_DQ44 BE37 DDR0_DQ_59/DDR1_DQ_43 DDR0_VREF_DQ_0 D37
    DDR0_DQ_60/DDR1_DQ_44 DDR0_VREF_DQ_1
    WIDTH:20MIL
    DDRB_DQ45 BE36 E36 DDR_SB_VREFCA
    DDRB_DQ46 DDR0_DQ_61/DDR1_DQ_45 DDR1_VREF_DQ DDR_VTT_CNTL DDR_SB_VREFCA 18 SPACING: 20MIL
    BG36 C35
    DDRB_DQ47 BG37 DDR0_DQ_62/DDR1_DQ_46 DDR_VTT_CNTL DDR_VTT_CNTL
    DDR0_DQ_63/DDR1_DQ_47

    2 of 20
    B WHISKEYLAKE-U_BGA1528 B

    +3VALW
    1

    RC501
    100K_0402_5%
    1 2

    +1.2V
    CPU_DRAMPG_CNTL 55
    QC1
    C

    RC502 1 2 2 B
    1K_0402_5% LMBT3904WT1G_SOT323-3

    DDR_VTT_CNTL
    E
    32

    A A

    RC503 @
    10K_0402_5%
    1

    Security Classification LC Future Center Secret Data Title


    Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (DDR4)
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS441/FS540
    Date: Wednesday, October 16, 2019 Sheet 5 of 61
    5 4 3 2 1
    5 4 3 2 1

    UC1C
    17 DDRA_DQ[16..31]
    DDRA_DQ16 J22 AF28
    DDRA_DQ17 H25 DDR1_DQ_0/DDR0_DQ_16
    DDR1_CKN_0/DDR1_CKN_0 AF29 DDRB_CLK0# 18
    DDRA_DQ18 G22 DDR1_DQ_1/DDR0_DQ_17DDR1_CKP_0/DDR1_CKP_0 AE28 DDRB_CLK0 18
    DDRA_DQ19 H22 DDR1_DQ_2/DDR0_DQ_18
    DDR1_CKN_1/DDR1_CKN_1 AE29 DDRB_CLK1# 18
    DDRA_DQ20 F25 DDR1_DQ_3/DDR0_DQ_19DDR1_CKP_1/DDR1_CKP_1 DDRB_CLK1 18
    DDRA_DQ21 J25 DDR1_DQ_4/DDR0_DQ_20 T28
    DDRA_DQ22 G25 DDR1_DQ_5/DDR0_DQ_21DDR1_CKE_0/DDR1_CKE_0 T29 DDRB_CKE0 18
    D DDRA_DQ23 F22 DDR1_DQ_6/DDR0_DQ_22DDR1_CKE_1/DDR1_CKE_1 V28 DDRB_CKE1 18 D
    DDRA_DQ24 D22 DDR1_DQ_7/DDR0_DQ_23 DDR1_CKE_2/NC V29
    DDRA_DQ25 C22 DDR1_DQ_8/DDR0_DQ_24 DDR1_CKE_3/NC
    DDRA_DQ26 C24 DDR1_DQ_9/DDR0_DQ_25 AL37
    DDRA_DQ27 D24 DDR1_DQ_10/DDR0_DQ_26
    DDR1_CS#_0/DDR1_CS#_0 AL35 DDRB_CS0# 18
    DDRA_DQ28 A22 DDR1_DQ_11/DDR0_DQ_27
    DDR1_CS#_1/DDR1_CS#_1 AL36 DDRB_CS1# 18
    DDRA_DQ29 B22 DDR1_DQ_12/DDR0_DQ_28
    DDR1_ODT_0/DDR1_ODT_0 AL34 DDRB_ODT0 18
    DDRA_DQ30 A24 DDR1_DQ_13/DDR0_DQ_29 NC/DDR1_ODT_1 AG36 DDRB_ODT1 18
    DDRA_DQ31 B24 DDR1_DQ_14/DDR0_DQ_30DDR1_CAB_9/DDR1_MA_0 AG35 DDRB_MA0 18
    17 DDRA_DQ[48..63] DDRA_DQ48 G31 DDR1_DQ_15/DDR0_DQ_31DDR1_CAB_8/DDR1_MA_1 AF34 DDRB_MA1 18
    DDRA_DQ49 G32 DDR1_DQ_16/DDR0_DQ_48DDR1_CAB_5/DDR1_MA_2 AG37 DDRB_MA2 18
    DDRA_DQ50 H29 DDR1_DQ_17/DDR0_DQ_49 NC/DDR1_MA_3 AE35 DDRB_MA3 18
    DDRA_DQ51 H28 DDR1_DQ_18/DDR0_DQ_50 NC/DDR1_MA_4 AF35 DDRB_MA4 18
    DDRA_DQ52 G28 DDR1_DQ_19/DDR0_DQ_51DDR1_CAA_0/DDR1_MA_5 AE37 DDRB_MA5 18
    DDRA_DQ53 G29 DDR1_DQ_20/DDR0_DQ_52DDR1_CAA_2/DDR1_MA_6 AC29 DDRB_MA6 18
    DDRA_DQ54 H31 DDR1_DQ_21/DDR0_DQ_53DDR1_CAA_4/DDR1_MA_7 AE36 DDRB_MA7 18
    DDRA_DQ55 H32 DDR1_DQ_22/DDR0_DQ_54DDR1_CAA_3/DDR1_MA_8 AB29 DDRB_MA8 18
    DDRA_DQ56 L31 DDR1_DQ_23/DDR0_DQ_55DDR1_CAA_1/DDR1_MA_9 AG34 DDRB_MA9 18
    DDRA_DQ57 L32 DDR1_DQ_24/DDR0_DQ_56
    DDR1_CAB_7/DDR1_MA_10 AC28 DDRB_MA10 18
    DDR1_DQ_25/DDR0_DQ_57
    DDR1_CAA_7/DDR1_MA_11 DDRB_MA11 18
    DDRA_DQ58 N29 AB28
    DDR1_DQ_26/DDR0_DQ_58
    DDR1_CAA_6/DDR1_MA_12 DDRB_MA12 18
    DDRA_DQ59 N28 AK35
    DDRA_DQ60 L28 DDR1_DQ_27/DDR0_DQ_59
    DDR1_CAB_0/DDR1_MA_13 DDRB_MA13 18
    DDRA_DQ61 L29 DDR1_DQ_28/DDR0_DQ_60 AJ35
    DDRA_DQ62 N31 DDR1_DQ_29/DDR0_DQ_61
    DDR1_CAB_2/DDR1_MA_14 AK34 DDRB_MA14_WE# 18
    18 DDRB_DQ[16..31] DDRA_DQ63 N32 DDR1_DQ_30/DDR0_DQ_62
    DDR1_CAB_1/DDR1_MA_15 AJ34 DDRB_MA15_CAS# 18
    DDRB_DQ16 AJ29 DDR1_DQ_31/DDR0_DQ_63
    DDR1_CAB_3/DDR1_MA_16 DDRB_MA16_RAS# 18
    DDRB_DQ17 AJ30 DDR1_DQ_32/DDR1_DQ_16 AJ37
    DDRB_DQ18 AM32 DDR1_DQ_33/DDR1_DQ_17DDR1_CAB_4/DDR1_BA_0 AJ36 DDRB_BS0# 18
    DDRB_DQ19 AM31 DDR1_DQ_34/DDR1_DQ_18DDR1_CAB_6/DDR1_BA_1 W29 DDRB_BS1# 18
    DDRB_DQ20 AM30 DDR1_DQ_35/DDR1_DQ_19DDR1_CAA_5/DDR1_BG_0 DDRB_BG0 18
    DDRB_DQ21 AM29 DDR1_DQ_36/DDR1_DQ_20 Y28
    DDRB_DQ22 AJ31 DDR1_DQ_37/DDR1_DQ_21DDR1_CAA_9/DDR1_BG_1 W28 DDRB_BG1 18
    C DDRB_DQ23 AJ32 DDR1_DQ_38/DDR1_DQ_22DDR1_CAA_8/DDR1_ACT# DDRB_ACT# 18 C
    DDRB_DQ24 AR31 DDR1_DQ_39/DDR1_DQ_23 H24 DDRA_DQS#2 DDRA_DQS#[2..3]
    DDRB_DQ25 AR32 DDR1_DQ_40/DDR1_DQ_24
    DDR1_DQSN_0/DDR0_DQSN_2 G24 DDRA_DQS2 DDRA_DQS#[2..3] 17
    DDRB_DQ26 AV30 DDR1_DQ_41/DDR1_DQ_25
    DDR1_DQSP_0/DDR0_DQSP_2 C23 DDRA_DQS#3 DDRA_DQS[2..3]
    DDRB_DQ27 AV29 DDR1_DQ_42/DDR1_DQ_26
    DDR1_DQSN_1/DDR0_DQSN_3 D23 DDRA_DQS3 DDRA_DQS[2..3] 17
    DDRB_DQ28 AR30 DDR1_DQ_43/DDR1_DQ_27
    DDR1_DQSP_1/DDR0_DQSP_3 G30 DDRA_DQS#6 DDRA_DQS#[6..7]
    DDRB_DQ29 AR29 DDR1_DQ_44/DDR1_DQ_28
    DDR1_DQSN_2/DDR0_DQSN_6 H30 DDRA_DQS6 DDRA_DQS#[6..7] 17
    DDRB_DQ30 AV32 DDR1_DQ_45/DDR1_DQ_29
    DDR1_DQSP_2/DDR0_DQSP_6 L30 DDRA_DQS#7 DDRA_DQS[6..7]
    DDRB_DQ31 AV31 DDR1_DQ_46/DDR1_DQ_30
    DDR1_DQSN_3/DDR0_DQSN_7 N30 DDRA_DQS7 DDRA_DQS[6..7] 17
    18 DDRB_DQ[48..63] DDRB_DQ48 BA32 DDR1_DQ_47/DDR1_DQ_31
    DDR1_DQSP_3/DDR0_DQSP_7 AL31 DDRB_DQS#2 DDRB_DQS#[2..3]
    DDRB_DQ49 BA31 DDR1_DQ_48/DDR1_DQ_48
    DDR1_DQSN_4/DDR1_DQSN_2 AL30 DDRB_DQS2 DDRB_DQS#[2..3] 18
    DDRB_DQ50 BD31 DDR1_DQ_49/DDR1_DQ_49
    DDR1_DQSP_4/DDR1_DQSP_2 AU31 DDRB_DQS#3 DDRB_DQS[2..3]
    DDRB_DQ51 BD32 DDR1_DQ_50/DDR1_DQ_50
    DDR1_DQSN_5/DDR1_DQSN_3 AU30 DDRB_DQS3 DDRB_DQS[2..3] 18
    DDRB_DQ52 BA30 DDR1_DQ_51/DDR1_DQ_51
    DDR1_DQSP_5/DDR1_DQSP_3 BC31 DDRB_DQS#6 DDRB_DQS#[6..7]
    DDRB_DQ53 BA29 DDR1_DQ_52/DDR1_DQ_52
    DDR1_DQSN_6/DDR1_DQSN_6 BC30 DDRB_DQS6 DDRB_DQS#[6..7] 18
    DDRB_DQ54 BD29 DDR1_DQ_53/DDR1_DQ_53
    DDR1_DQSP_6/DDR1_DQSP_6 BH31 DDRB_DQS#7 DDRB_DQS[6..7]
    DDRB_DQ55 BD30 DDR1_DQ_54/DDR1_DQ_54
    DDR1_DQSN_7/DDR1_DQSN_7 BH30 DDRB_DQS7 DDRB_DQS[6..7] 18
    DDRB_DQ56 BG31 DDR1_DQ_55/DDR1_DQ_55
    DDR1_DQSP_7/DDR1_DQSP_7
    DDRB_DQ57 BG32 DDR1_DQ_56/DDR1_DQ_56 Y29
    DDRB_DQ58 BK32 DDR1_DQ_57/DDR1_DQ_57 NC/DDR1_ALERT# AE34 DDRB_ALERT# 18
    DDRB_DQ59 BK31 DDR1_DQ_58/DDR1_DQ_58 NC/DDR1_PAR BU31 CPU_DRAMRST#_R DDRB_PAR 18
    DDRB_DQ60 BG29 DDR1_DQ_59/DDR1_DQ_59 DRAM_RESET#
    DDRB_DQ61 BG30 DDR1_DQ_60/DDR1_DQ_60 BN28 SM_RCOMP_0 RC6011 2 121_0402_1%
    DDRB_DQ62 BK30 DDR1_DQ_61/DDR1_DQ_61 DDR_COMP_0 BN27 SM_RCOMP_1 RC6021 2 80.6_0402_1%
    DDRB_DQ63 BK29 DDR1_DQ_62/DDR1_DQ_62 DDR_COMP_1 BN29 SM_RCOMP_2 RC6031 2 100_0402_1%
    DDR1_DQ_63/DDR1_DQ_63 DDR_COMP_2

    @ 3 of 20
    WHISKEYLAKE-U_BGA1528

    B B

    +1.2V
    1

    RC604
    470_0402_5%
    2

    CPU_DRAMRST#_R RC605 2 1 0_0402_5%


    CPU_DRAMRST# 17,18
    0.1u_0201_10V6K

    1
    CC601

    2 @

    A A

    Security Classification LC Future Center Secret Data Title

    Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (DDR4)


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    Size Document Number
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS441/FS540
    Date: Wednesday, October 16, 2019 Sheet 6 of 61
    5 4 3 2 1
    5 4 3 2 1

    +3VALW_PCH

    SMBUS&SMLINK

    1
    RC3088
    100K_0402_5%

    2
    UC1E
    SPI_CLK_R CH37
    SPI_SO_R CF37 SPI0_CLK CK14 PCH_SMB_CLK
    SPI_SI_R CF36 SPI0_MISO GPP_C0/SMBCLK CH15 PCH_SMB_DATA +3VALW_PCH +3VS +3VS
    SPI_WP#_R SPI0_MOSI GPP_C1/SMBDATA SMB_ALERT#
    DIMM WLAN
    CF34 CJ15
    SPI_HOLD#_R CG34 SPI0_IO2 GPP_C2/SMBALERT#
    SPI_CS0#_R CG36 SPI0_IO3 CH14 SML0_CLK
    D
    CG35 SPI0_CS0# GPP_C3/SML0CLK CF15 SML0_DATA D
    SPI_CS2#_R CH34 SPI0_CS1# GPP_C4/SML0DATA CG15 SML0_ALERT#
    32 SPI_CS2#_R SPI0_CS2# GPP_C5/SML0ALERT#

    4
    3

    4
    3
    CN15 PCH_SML1_CLK RPC702
    GPP_C6/SML1CLK RPC701

    2
    +3VS CM15 PCH_SML1_DAT
    GPU, EC, Thermal Sensor 2.2K_0404_4P2R_5%

    G
    CF20 GPP_C7/SML1DATA CC34 SML1_ALERT# 2.2K_0404_4P2R_5%
    RPC7 CG22 GPP_D1/SPI1_CLK/BK1/SBK1 GPP_B23/SML1ALERT#/PCHHOT# Q4611

    1
    2

    1
    2
    4 1 SERIRQ CF22 GPP_D2/SPI1_MISO_IO1/BK2/SBK2
    3 2 KBRST# CG23 GPP_D3/SPI1_MOSI_IO0/BK3/SBK3 PCH_SMB_CLK 1 3
    GPP_D21/SPI1_IO2 LPC_AD0_R SMB_CLK_S3 18
    CH23 CA29 1 2

    S
    RE4418 0_0402_5%
    GPP_D22/SPI1_IO3 GPP_A1/LAD0/ESPI_IO0 LPC_AD1_R LPC_AD0_EC 44
    10K_0404_4P2R_5% CG20 BY29 RE4424 1 2 0_0402_5% L2N7002KWT1G_SOT323-3
    GPP_D0/SPI1_CS0#/BK0/SBK0 GPP_A2/LAD1/ESPI_IO1 LPC_AD1_EC 44

    2
    BY27 LPC_AD2_R RE4419 1 2 0_0402_5%

    G
    GPP_A3/LAD2/ESPI_IO2 LPC_AD3_R LPC_AD2_EC 44
    BV27 RE4420 1 2 0_0402_5%
    GPP_A4/LAD3/ESPI_IO3 LPC_FRAME# LPC_AD3_EC 44 Q4612
    CC701 1 2 KBRST# CA28
    GPP_A5/LFRAME#/ESPI_CS# SUS_STAT# LPC_FRAME# 44
    @ CH7 CA27 1
    CL_CLK GPP_A14/SUS_STAT#/ESPI_RESET# TC701 PCH_SMB_DATA
    CH8 1 3
    CH9 CL_DATA BV32 CLK_PCI_EC_R RC706 1 2 0_0402_5% SMB_DATA_S3 18

    S
    1000P_0402_50V7K
    CL_RST# GPP_A9/CLKOUT_LPC0/ESPI_CLK CLK_PCI_EC 44
    BV30 L2N7002KWT1G_SOT323-3
    GPP_A10/CLKOUT_LPC1 BY30 PM_CLKRUN# RC709 1 2 8.2K_0402_5%
    GPP_A8/CLKRUN# +3VS
    KBRST# BV29
    44 KBRST# GPP_A0/RCIN#/TIME_SYNC1
    SERIRQ BV28 +3VALW_PCH
    44 SERIRQ GPP_A6/SERIRQ
    5 of 20
    WHISKEYLAKE-U_BGA1528 SMB_ALERT# RC712 1 2 2.2K_0402_5%
    @

    TLS Confidentiality (Rising edge of RSMRST#)


    This signal has a weak internal pull-down.
    0 = Disable Intel ME Crypto Transport Layer Security(TLS) cipher suite (no
    SPI ROM confidentiality). (Default)
    LPC R/C close to PCH 1 = Enable Intel ME Crypto Transport Layer Security(TLS) cipher suite (with
    +3V_SPI confidentiality). Must be pulled up to support Intel AMT with TLS.
    LPC_AD3_EC EMC_NS@ Notes:
    CE4432 1 2 27P_0402_50V8J
    1. The internal pull-down is disabled after RSMRST# de-asserts.
    LPC_AD2_EC EMC_NS@
    C CE4428 1 2 27P_0402_50V8J 2. This signal is in the primary well. C
    4
    3

    RPC808 LPC_AD1_EC CE4429 1 2 27P_0402_50V8J EMC_NS@


    100K_0404_4P2R_5%
    LPC_AD0_EC CE4430 1 2 27P_0402_50V8J EMC_NS@ +3VALW_PCH
    1
    2

    CLK_PCI_EC RPC809
    CE4431 1 2 27P_0402_50V8J EMC_NS@
    SML0_CLK 3 2
    SPI_WP#_R 1 RC718 2 49.9_0402_1% SPI_WP# SML0_DATA 4 1

    SPI_HOLD#_R 1 RC720 2 49.9_0402_1% SPI_HOLD# 2.2K_0404_4P2R_5%


    SML0_ALERT# RC719 2 @ 1 2.2K_0402_5%

    SPI0_MOSI: Reserved (Rising edge of RSMRST#)


    SPI0_IO2: Reserved (Rising edge of RSMRST#)
    SPI0_IO3: Reserved (Rising edge of RSMRST#) eSPI or LPC (Rising edge of RSMRST# )
    External pull-up is required. Recommend 100K if pulled up to 3.3V or 75K if pulled This signal has a weak internal pull-down.
    up to 1.8V. This strap should sample HIGH. There should NOT be any on-board 0 = LPC Is selected for EC. (Default)
    device driving it to opposite direction during strap sampling. 1 = eSPI Is selected for EC.
    Notes:
    1. The internal pull-down is disabled after RSMRST# de-asserts.
    2. This signal is in the primary well.
    For SPI clk signal fine tune
    CC717 2 1 12P_0201_25V8-J +3VALW_PCH +3VS

    RC1154 1 @ 2 100K_0402_5%

    4
    3
    SPI_CLK RC703 1 2 49.9_0402_1% SPI_CLK_R RPC807
    44 SPI_CLK SPI_CLK_R 32

    2
    2.2K_0404_4P2R_5%

    G
    SPI_SO RC701 1 2 49.9_0402_1% SPI_SO_R
    44 SPI_SO SPI_SO_R 32

    1
    2
    PCH_SML1_CLK 6 1

    S
    B SPI_SI SPI_SI_R EC_SMB_CK2 26,39,44 B
    1 2 49.9_0402_1%

    D
    44 SPI_SI RC702
    SPI_SI_R 32

    5
    G
    QC3A @
    SPI_CS0# RC704 1 2 0_0402_5% SPI_CS0#_R L2N7002KDW1T1G_SOT363-6
    44 SPI_CS0#
    PCH_SML1_DAT 3 4

    S
    EC_SMB_DA2 26,39,44

    D
    +3VALW_PCH QC3B @
    L2N7002KDW1T1G_SOT363-6 +3VALW_PCH
    2

    NPI@ SML1_ALERT# RC724 1 @ 2 2.2K_0402_5%


    44 SML1_ALERT#
    2

    RC730
    0_0402_5% D2201
    MP@ RB520CM-30T2R_VMN2M2
    1
    1

    Intel DCI-OOB (Rising edge of RSMRST#)


    UC702 This signal has an internal pull-down.
    SPI_CS0# 1 8 +3V_SPI
    /CS VCC 0 = Disable Intel DCI-OOB (Default)
    SPI_SO 2 7 SPI_HOLD# 1 = Enable Intel DCI-OOB
    DO(IO1) /HOLD(IO3) Notes:
    1 1. The internal pull-down is disabled after RSMRST# de-asserts.
    SPI_WP# 3 6 SPI_CLK CC702
    /WP(IO2) CLK .1U_0402_10V6-K 2. When used as PCHHOT# and strap low, a 150K pull-up is needed to
    4 5 SPI_SI ensure it does not override the internal pull-down strap sampling.
    GND DI(IO0) 2 This signal is in the primary well.
    W25Q128JVSIQ_SO8

    A A

    Security Classification LC Future Center Secret Data Title

    Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (JTAG,SPI,LPC,SMB)


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS441/FS540
    Date: Wednesday, October 16, 2019 Sheet 7 of 61
    5 4 3 2 1
    5 4 3 2 1

    +3VS
    @OPT&GC6 Only for NV GPU SKU
    +3VS

    RC801 2 OPT@ 1 10K_0402_5% PXS_PWREN_R RC802 1 OPT@ 2 1K_0402_5%


    PXS_PWREN 23 FB_GC6_EN_R
    RC803 2 @ 1 10K_0402_5%
    RC806 2 @ 1 10K_0402_5% PXS_RST#_R RC804 1 OPT@ 2 0_0402_5%
    PXS_RST# 26 GPU_EVENT#
    RC813 2 GC6@ 1 10K_0402_5%
    Reserve for GPU sequence
    RC815 2 OPT@ 1 10K_0402_5% PXS_RST#_R RC816 2 @ 1 10K_0402_5% FB_GC6_EN_R

    CC801 1OPT@ 2 .01U_0402_16V7-K PXS_RST# RC817 2 @ 1 10K_0402_5% GPU_EVENT#

    D D

    +3VS

    1
    +1.8VALW RC2013
    10K_0402_5%
    UC1F
    RC3094 1 @ 2 20K_0402_5% CNVI_BRI_RSP CC27

    2
    RC15411 TPM@ 2 0_0402_5% TPM_SPI_IRQ#_R CC32 GPP_B15/GSPI0_CS0#
    RC3095 1 @ 2 20K_0402_5% CNVI_RGI_RSP 32 TPM_SPI_IRQ# CE28 GPP_A7/PIRQA#/GSPI0_CS1# CN22 +3VALW_PCH
    CE27 GPP_B16/GSPI0_CLK GPP_D9/ISH_SPI_CS#/GSPI2_CS0# CR22
    RC849 1 @ 2 10K_0402_5% CNVI_RGI_DT RC827 1 @ 2 2.2K_0402_5% GPP_B18 CE29 GPP_B17/GSPI0_MISO GPP_D10/ISH_SPI_CLK/GSPI2_CLK CM22
    +3VS GPP_B18/GSPI0_MOSI GPP_D11/ISH_SPI_MISO/GSPI2_MISO CP22 RC888 1 2 100K_0402_5%
    CA31 GPP_D12/ISH_SPI_MOSI/GSPI2_MOSI
    CA32 GPP_B19/GSPI1_CS0# CK22
    CC29 GPP_A11/PME#/GSPI1_CS1#/SD_VDD2_PWR_EN# GPP_D5/ISH_I2C0_SDA CH20
    +3VS CC30 GPP_B20/GSPI1_CLK GPP_D6/ISH_I2C0_SCL
    RC829 RC828 1 @ 2 2.2K_0402_5% GPP_B22 CA30 GPP_B21/GSPI1_MISO CH22
    PCH_TP_INT# +3VS GPP_B22/GSPI1_MOSI GPP_D7/ISH_I2C1_SDA
    1 2 CJ22
    10K_0402_5% CNVI_BRI_RSP CK20 GPP_D8/ISH_I2C1_SCL
    40 CNVI_BRI_RSP CNVI_RGI_DT R4684 1 CNVI@ 2 22_0402_5% CNVI_RGI_DT_R GPP_F5/CNV_BRI_RSP
    CG19 CJ27
    40 CNVI_RGI_DT CNVI_BRI_DT R4685 1 CNVI@ 2 22_0402_5% CNVI_BRI_DT_R CJ20 GPP_F6/CNV_RGI_DT GPP_H10/I2C5_SDA/ISH_I2C2_SDA CJ29
    RPC805 40 CNVI_BRI_DT
    1 4 PCH_I2C_SDA0 CNVI_RGI_RSP CH19 GPP_F4/CNV_BRI_DT GPP_H11/I2C5_SCL/ISH_I2C2_SCL
    PCH_I2C_SCL0 40 CNVI_RGI_RSP GPP_F7/CNV_RGI_RSP GPU_EVENT#
    2 3 CM24
    GPP_D13/ISH_UART0_RXD CN23 PCH_TP_INT# GPU_EVENT# 26
    UART_RX_DEBUG GPP_D14/ISH_UART0_TXD PCH_WLAN_OFF# PCH_TP_INT# 45
    1/16W_1K_5%_4P2R_0404 CR12 CM23
    UART 40 UART_RX_DEBUG UART_TX_DEBUG CP12 GPP_C20/UART2_RXD GPP_D15/ISH_UART0_RTS#/GSPI2_CS1# CR24 PCH_BT_OFF# PCH_WLAN_OFF# 40
    40 UART_TX_DEBUG GPP_C21/UART2_TXD GPP_D16/ISH_UART0_CTS#/SML0BALERT# PCH_BT_OFF# 40
    CN12
    +3VS CM12 GPP_C22/UART2_RTS# CG12 PXS_PWREN_R
    R258 T4 @ Touch PAD GPP_C23/UART2_CTS# GPP_C12/UART1_RXD/ISH_UART1_RXD CH12 PXS_RST#_R
    1 2 22_0402_5% 2 1RC830 PCH_I2C_SDA0 CM11 GPP_C13/UART1_TXD/ISH_UART1_TXD CF12 DGPU_PWROK
    C C
    1

    UART_RX_DEBUG 8 45 TP_I2C_SDA0 PCH_I2C_SCL0 CN11 GPP_C16/I2C0_SDA GPP_C14/UART1_RTS#/ISH_UART1_RTS# FB_GC6_EN_R DGPU_PWROK 23,57


    1/20W_49.9K_1%_0201 22_0402_5% 2 1RC831 CG14
    45 TP_I2C_SCL0 GPP_C17/I2C0_SCL GPP_C15/UART1_CTS#/ISH_UART1_CTS# FB_GC6_EN_R 23,26

    1
    T5 @ CK12 BW35 ISH_GP0 1 RC825
    1 R259 2 CJ12 GPP_C18/I2C1_SDA GPP_A18/ISH_GP0 BW34 TC824 @ PAD
    UART_TX_DEBUG 8 10K_0402_5%
    1

    1/20W_49.9K_1%_0201 GPP_C19/I2C1_SCL GPP_A19/ISH_GP1 CA37 UMA@


    CF27 GPP_A20/ISH_GP2 CA36 AOAC_ON#
    1
    TC1419@ PAD

    2
    CF29 GPP_H4/I2C2_SDA GPP_A21/ISH_GP3 CA35
    GPP_H5/I2C2_SCL GPP_A22/ISH_GP4 CA34
    CH27 GPP_A23/ISH_GP5 BW37 ISH_GP6 1
    GPP_H6/I2C3_SDA GPP_A12/ISH_GP6/BM_BUSY#/SX_EXIT_HOLDOFF# TC1415@ PAD
    CH28
    GPP_H7/I2C3_SCL
    CJ30
    CJ31 GPP_H8/I2C4_SDA
    GPP_H9/I2C4_SCL

    WHISKEYLAKE-U_BGA1528 6 of 20

    @
    +3VALW_PCH +1.8VALW
    2

    RC834
    2

    4.7K_0402_5%
    RC3101 HDA18@
    10K_0402_5% HDA_SDOUT
    1 1

    HDA18@
    Q4609 D
    1

    ME_FLASH# 2
    G
    1

    Q4610 D HDA18@ S L2N7002KWT1G_SOT323-3


    3

    ME_FLASH 2 UC1G
    44 ME_FLASH G RC837 1 2 1/20W_33_1%_0201 HDA_SYNC BN34 CH36
    30 HDA_SYNC_AUDIO HDA_BCLK BN37 HDA_SYNC/I2S0_SFRM GPP_G0/SD_CMD
    RC838 1 21/20W_10_1%_0201 CL35
    30 HDA_BITCLK_AUDIO HDA_BCLK/I2S0_SCLK GPP_G1/SD3_DATA0
    HDA18@ S L2N7002KWT1G_SOT323-3 RC840 1 2 1/20W_33_1%_0201 HDA_SDOUTBN36 CL36
    3

    30 HDA_SDOUT_AUDIO HDA_SDIN0 BN35 HDA_SDO/I2S0_TXD GPP_G2/SD3_DATA1 CM35


    30 HDA_SDIN0 HDA_SDI0/I2S0_RXD GPP_G3/SD3_DATA2
    BL36 CN35
    B
    PAD @
    1 BL35 HDA_SDI1/I2S1_RXD/SNDW1_DATA
    HDA_RST#/I2S1_SCLK/SNDW1_CLK
    GPP_G4/SD_DATA3
    GPP_G5/SD_CD#
    CH35 * B

    TC808 CK23 CK36


    RC842 1 2 0_0402_5% HDA_SDOUT GPP_D23/I2S_MCLK GPP_G6/SD_CLK CK34
    HDA33@ 1 BL37 GPP_G7/SD_WP
    PAD @ I2S1_SFRM/SNDW2_CLK
    TC809 BL34
    I2S1_TXD/SNDW2_DATA
    Default When
    Pin Name Strap Description Configuration Value Sampled
    CNVI_RF_RESET# CJ32
    40 CNVI_RF_RESET# CH32 GPP_H1/I2S2_SFRM/CNV_BT_I2S_BCLK/CNV_RF_RESET#
    GPP_H0/I2S2_SCLK/CNV_BT_I2S_SCLK
    Internal PD
    CNVI_MODEM_CLKREQ CH29 0 = Disable “Top Swap”
    +3VALW_PCH 40 CNVI_MODEM_CLKREQ GPP_H2/I2S2_TXD/CNV_BT_I2S_SDI/MODEM_CLKREQ
    CH30 SPKR / Top Swap 0 Rising edge
    +3VS GPP_H3/I2S2_RXD/CNV_BT_I2S_SDO
    GPP_A17/SD_VDD1_PWR_EN#/ISH_GP7
    BW36 GPP_B14 Override
    mode. (Default)
    1 = Enable “Top Swap”
    * of PCH_PWROK
    1

    RC836 1 @ 2 1K_0402_5% HDA_SDOUT CP24 BY31


    1

    RH829 RH830 CN24 GPP_D19/DMIC_CLK0/SNDW4_CLK GPP_A16/SD_1P8_SEL mode.


    1/20W_75K_1%_0201 71.5K_0402_1% RC845 GPP_D20/DMIC_DATA0/SNDW4_DATA CK33 SD_RCOMP
    HDA_SDO This signal has a weak internal pull-down. SD_1P8_RCOMP
    Internal PD
    0 = Enable security measures defined in the Flash Descriptor. CNVI@ @ @ 2.2K_0402_5% CK25 CM34 GSPI0_MOSI 0 = Disable “No Reboot” Rising edge
    CJ25 GPP_D17/DMIC_CLK1/SNDW3_CLK SD_3P3_RCOMP
    1 = Disable Flash Descriptor Security(override). This strap /GPP_B18 No Reboot mode. (Default) * 0 of PCH_PWROK
    2

    GPP_D18/DMIC_DATA1/SNDW3_DATA

    1
    should only be asserted high during external pull-up in
    2

    PCH_BEEP CF35 RC843 1 = Enable “No Reboot”


    manufacturing/debug environments ONLY. 30 PCH_BEEP GPP_B14/SPKR 200_0402_1% mode
    7 of 20
    WHISKEYLAKE-U_BGA1528
    GSPI1_MOSIBoot BIOS Internal PD Rising edge

    2
    M.2 CNV Mode Select (Rising edge of RSMRST#) @ 0
    /GPP_B22 Strap Bit 0 = SPI (Default) * of PCH_PWROK
    An external pull-up or pull-down is required. BBS 1 = LPC
    0 = Integrated CNVi enable.
    1 = Integrated CNVi disable.
    GPP_B18_NO_REBOOT
    0 = Disable ¨No Reboot〃 mode. (Default)
    〃 mode (PCH will disable the
    1 = Enable ¨No Reboot
    TCO
    Timer system reboot feature). This function is useful
    For EMI Close to PCH when running ITP/XDP.

    HDA_BCLK HDA_SYNC HDA_SDOUT

    A A
    1 1 1
    CC4220 @ CC4221 @ CC4219
    56P_50V_J_NPO_0201 2P_25V_NPO_0201 2P_25V_NPO_0201
    2 2 2

    Security Classification LC Future Center Secret Data Title

    Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (LPSS,ISH,AUDIO,SDIO)


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS441/FS540
    Date: Wednesday, October 16, 2019 Sheet 8 of 61
    5 4 3 2 1
    5 4 3 2 1

    20 PCIE_CRX_GTX_N[5..8]

    20 PCIE_CRX_GTX_P[5..8]

    20 PCIE_CTX_C_GRX_N[5..8]

    20 PCIE_CTX_C_GRX_P[5..8]
    D D

    UC1H
    PCIE_CRX_GTX_N5 BW9 CB5 USB30_RX_N1
    PCIE_CRX_GTX_P5 PCIE5_RXN/USB31_5_RXN PCIE1_RXN/USB31_1_RXN USB30_RX_P1 USB30_RX_N1 43
    BW8 CB6
    PCIE_CTX_C_GRX_N5 OPT@ 0.22U_0201_6.3V6-K 1 2 CC901 PCIE_CTX_GRX_N5 BW4 PCIE5_RXP/USB31_5_RXP
    PCIE5_TXN/USB31_5_TXN
    PCIE1_RXP/USB31_1_RXP
    PCIE1_TXN/USB31_1_TXN
    CA4 USB30_TX_N1 USB30_RX_P1
    USB30_TX_N1
    43
    43
    USB3.0
    PCIE_CTX_C_GRX_P5 OPT@ 0.22U_0201_6.3V6-K 1 2 CC902 PCIE_CTX_GRX_P5 BW3 CA3 USB30_TX_P1
    PCIE5_TXP/USB31_5_TXP PCIE1_TXP/USB31_1_TXP USB30_TX_P1 43
    PCIE_CRX_GTX_N6 BU6 BY8 USB30_RX_N2
    PCIE_CRX_GTX_P6 PCIE6_RXN/USB31_6_RXN PCIE2_RXN/USB31_2_RXN/SSIC_1_RXN USB30_RX_P2 USB30_RX_N2 41
    BU5 BY9
    PCIE_CTX_C_GRX_N6 PCIE_CTX_GRX_N6 PCIE6_RXP/USB31_6_RXP PCIE2_RXP/USB31_2_RXP/SSIC_1_RXP USB30_TX_N2 USB30_RX_P2 41
    OPT@ 0.22U_0201_6.3V6-K 1 2 CC905 BU4 CA2
    PCIE_CTX_C_GRX_P6 OPT@ 0.22U_0201_6.3V6-K 1 2 CC906 PCIE_CTX_GRX_P6 BU3 PCIE6_TXN/USB31_6_TXN PCIE2_TXN/USB31_2_TXN/SSIC_1_TXN CA1 USB30_TX_P2 USB30_TX_N2 41 USB3.0
    DGPU PCIE6_TXP/USB31_6_TXP PCIE2_TXP/USB31_2_TXP/SSIC_1_TXP USB30_TX_P2 41
    PCIE_CRX_GTX_N7 BT7 BY7
    PCIE_CRX_GTX_P7 BT6 PCIE7_RXN PCIE3_RXN/USB31_3_RXN BY6
    PCIE_CTX_C_GRX_N7 OPT@ 0.22U_0201_6.3V6-K 1 2 CC907 PCIE_CTX_GRX_N7 BU2 PCIE7_RXP PCIE3_RXP/USB31_3_RXP BY4
    PCIE_CTX_C_GRX_P7 OPT@ 0.22U_0201_6.3V6-K 1 2 CC903 PCIE_CTX_GRX_P7 BU1 PCIE7_TXN PCIE3_TXN/USB31_3_TXN BY3
    PCIE7_TXP PCIE3_TXP/USB31_3_TXP
    PCIE_CRX_GTX_N8 BU9 BW6
    PCIE_CRX_GTX_P8 BU8 PCIE8_RXN PCIE4_RXN/USB31_4_RXN BW5
    PCIE_CTX_C_GRX_N8 OPT@ 0.22U_0201_6.3V6-K 1 2 CC908 PCIE_CTX_GRX_N8 BT4 PCIE8_RXP PCIE4_RXP/USB31_4_RXP BW2
    PCIE_CTX_C_GRX_P8 OPT@ 0.22U_0201_6.3V6-K 1 2 CC904 PCIE_CTX_GRX_P8 BT3 PCIE8_TXN PCIE4_TXN/USB31_4_TXN BW1
    PCIE8_TXP PCIE4_TXP/USB31_4_TXP
    PCIE_PRX_DTX_N9 BP5 CE3 USB20_N1
    40 PCIE_PRX_DTX_N9 PCIE9_RXN USB2_1N USB20_N1 41
    40 PCIE_PRX_DTX_P9
    .1U_0402_10V6-K 1 2 CC918
    PCIE_PRX_DTX_P9
    PCIE_PTX_DRX_N9
    BP6
    BR2 PCIE9_RXP USB2_1P
    CE4 USB20_P1
    USB20_P1 41 USB3.0
    WLAN 40
    40
    PCIE_PTX_C_DRX_N9
    PCIE_PTX_C_DRX_P9
    .1U_0402_10V6-K 1 2 CC919 PCIE_PTX_DRX_P9 BR1 PCIE9_TXN
    PCIE9_TXP USB2_2N
    CE1 USB20_N2
    USB20_N2 45
    BN6 USB2_2P
    CE2 USB20_P2
    USB20_P2 45 Finger Print
    BN5 PCIE10_RXN CG3 USB20_N3
    PCIE10_RXP USB2_3N USB20_N3 43
    BR4
    BR3 PCIE10_TXN USB2_3P
    CG4 USB20_P3
    USB20_P3 43 USB3.0
    PCIE10_TXP CD3 USB20_N4
    USB2_4N USB20_N4 43
    38 SATA_PRX_DTX_N0
    SATA_PRX_DTX_N0
    SATA_PRX_DTX_P0
    BN10
    BN8 PCIE11_RXN/SATA0_RXN USB2_4P
    CD4 USB20_P4
    USB20_P4 43 USB2.0
    38 SATA_PRX_DTX_P0 SATA_PTX_DRX_N0 BN4 PCIE11_RXP/SATA0_RXP CG5 USB20_N5
    HDD 38 SATA_PTX_DRX_N0 SATA_PTX_DRX_P0 BN3 PCIE11_TXN/SATA0_TXN
    PCIE11_TXP/SATA0_TXP
    USB2_5N
    USB2_5P
    CG6 USB20_P5 USB20_N5
    USB20_P5
    30
    30 Card reader
    C 38 SATA_PTX_DRX_P0 C
    BL6 CC1 USB20_N6
    PCIE12_RXN/SATA1A_RXN USB2_6N USB20_N6 33
    BL5
    BN2 PCIE12_RXP/SATA1A_RXP USB2_6P
    CC2 USB20_P6
    USB20_P6 33 Touch Screen
    BN1 PCIE12_TXN/SATA1A_TXN CG8 USB20_N7
    PCIE12_TXP/SATA1A_TXP USB2_7N USB20_P7 USB20_N7 33
    CG9
    PCIE_PRX_DTX_N13 BK6
    PCIE13_RXN
    USB2_7P USB20_P7 33 Camera
    37 PCIE_PRX_DTX_N13 PCIE_PRX_DTX_P13 BK5 CB8
    37 PCIE_PRX_DTX_P13 PCIE_PTX_DRX_N13 BM4 PCIE13_RXP USB2_8N CB9
    37 PCIE_PTX_DRX_N13 PCIE_PTX_DRX_P13 BM3 PCIE13_TXN USB2_8P
    37 PCIE_PTX_DRX_P13 PCIE13_TXP CH5
    PCIE_PRX_DTX_N14 BJ6 USB2_9N CH6
    37 PCIE_PRX_DTX_N14 PCIE_PRX_DTX_P14 BJ5 PCIE14_RXN USB2_9P
    37 PCIE_PRX_DTX_P14 PCIE_PTX_DRX_N14 BL2 PCIE14_RXP CC3 USB20_N10
    37 PCIE_PTX_DRX_N14 PCIE_PTX_DRX_P14 BL1 PCIE14_TXN USB2_10N CC4 USB20_P10 USB20_N10 40 BT
    SSD 37 PCIE_PTX_DRX_P14 PCIE14_TXP USB2_10P USB20_P10 40
    PCIE_PRX_DTX_N15 BG5 CC5 USB2_COMP RC901 2 1 113_0402_1% USBRBIAS +3VALW_PCH
    37 PCIE_PRX_DTX_N15 PCIE_PRX_DTX_P15 PCIE15_RXN/SATA1B_RXN USB2_COMP USB2_ID Width 20Mil
    37 PCIE_PRX_DTX_P15 BG6 CE8 RC902 1 2 0_0402_5%
    PCIE_PTX_DRX_N15 BL4 PCIE15_RXP/SATA1B_RXP USB2_ID CC6 USB2_VBUSSENSE RC903 1 2 0_0402_5% Space 15Mil
    37 PCIE_PTX_DRX_N15 PCIE_PTX_DRX_P15 BL3 PCIE15_TXN/SATA1B_TXN USB2_VBUSSENSE Length 500Mil RPC810
    37 PCIE_PTX_DRX_P15 PCIE15_TXP/SATA1B_TXP USB_OC0# USB_OC0#
    CK6 USB_VBUSSENSE change 0ohm followC740 8 1
    PCIE_PRX_DTX_N16 BE5 GPP_E9/USB2_OC0#/GP_BSSB_CLK CK5 USB_OC1# USB_OC0# 43 USB_OC1# 7 2
    37 PCIE_PRX_DTX_N16 PCIE_PRX_DTX_P16 PCIE16_RXN/SATA2_RXN GPP_E10/USB2_OC1#/GP_BSSB_DI USB_OC2# USB_OC1# 41 USB_OC3#
    37 PCIE_PRX_DTX_P16 BE6 CK8 6 3
    PCIE_PTX_DRX_N16 PCIE16_RXP/SATA2_RXP GPP_E11/USB2_OC2# USB_OC3# USB_OC2# 43 USB_OC2#
    BJ4 CK9 5 4
    37 PCIE_PTX_DRX_N16 PCIE_PTX_DRX_P16 BJ3 PCIE16_TXN/SATA2_TXN GPP_E12/USB2_OC3#
    37 PCIE_PTX_DRX_P16 PCIE16_TXP/SATA2_TXP GPP_E4
    CP8 RC904 1 2 0_0402_5% 10K_0804_8P4R_5%
    GPP_E4/DEVSLP0 CR8 PCH_SATA_1_DEVSLP 1 EC_SMI# 44
    GPP_E5/DEVSLP1 TC1418
    RC905 1 2 100_0402_1% PCIE_RCOMPN CE6 CM8 PCH_SATA_DEVSLP
    PCIE_RCOMPP PCIE_RCOMP_N GPP_E6/DEVSLP2 PCH_SATA_DEVSLP 37
    CE5
    PCIE_RCOMP_P CN8 SATA0GP +3VS
    PCIE_RCOMPN and PCIE_RCOMPP CR28 GPP_E0/SATAXPCIE0/SATAGP0 CM10 SSD_1_PCIE_DET# 1
    Trace Width: 12-15mil CP28 GPP_H12/M2_SKT2/CFG_0 GPP_E1/SATAXPCIE1/SATAGP1 CP10 SSD_PCIE_DET# TC1417
    Differential between RCOMPP/RCOMPN GPP_H13/M2_SKT2/CFG_1 GPP_E2/SATAXPCIE2/SATAGP2 SSD_PCIE_DET# 37 SSD_PCIE_DET#
    CN28 10K_0402_5% 2 1 RC3105
    CM28 GPP_H14/M2_SKT2/CFG_2 CN7
    GPP_H15/M2_SKT2/CFG_3 GPP_E8/SATALED#/SPI1_CS1# SATA0GP 10K_0402_5% 2 @ 1 RC3106
    AR3
    RSVD37 SSD_1_PCIE_DET# 10K_0402_5% 2 @ 1 RC3116
    B WHISKEYLAKE-U_BGA1528 8 of 20 GPP_E4 B
    10K_0402_5% 1 @ 2 RC906
    @

    A A

    Security Classification LC Future Center Secret Data Title

    Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (PCIE,SATA,USB3,USB2)


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS441/FS540
    Date: Wednesday, October 16, 2019 Sheet 9 of 61
    5 4 3 2 1
    5 4 3 2 1

    TC1008
    RC3066&RC3065 &RC3097 需要
    +3VALW_PCH
    UC1I 100K_0402_5%
    change bom stucture :common design 14&15;
    CNV_WR_D0N CR30 15@&14or15@------@;14or17@---- KEEP

    1
    40 CNV_WR_D0N CNV_WR_D0P CP30 CNV_WR_D0N CN27 1 2 RC4527
    40 CNV_WR_D0P CNV_WR_D0P GPP_H18/CPU_C10_GATE# +1.8VALW
    CNV_WR_D1N CM30 CM27 +1.8VALW
    40 CNV_WR_D1N CNV_WR_D1P CN30 CNV_WR_D1N GPP_H19/TIMESYNC_0
    40 CNV_WR_D1P CNV_WR_D1P CF25 XTAL_Freq_Select RC3092 1 2 4.7K_0402_5%
    GPP_H21 / XTAL_FREQ_SELECT

    2 OPTN17@
    CNV_WT_D0N CN32 CN26 +1.8VALW
    40 CNV_WT_D0N CNV_WT_D0P CNV_WT_D0N GPP_H22 CM26 GPPC_H23

    RC805

    RC812

    RC814

    FP@ 2 RC3062

    2 RC3097

    2 RC3099

    2 RC3098

    2 RC3077
    CM32 RC3093 1 @ 2 10K_0402_5%
    40 CNV_WT_D0P CNV_WT_D0P GPP_H23

    1 RC809 2 OPT@
    @

    @
    CK17 BOARD_ID12

    @
    D CNV_WT_D1N CP33 GPP_F10 D
    40 CNV_WT_D1N CNV_WT_D1N

    10K_0402_5%
    CNV_WT_D1P CN33 RC1056
    40 CNV_WT_D1P CNV_WT_D1P

    1 RC807 2

    1 RC808 2

    10K_0402_5%1 RC811 2

    2
    10K_0402_5%
    BV35 GPD7 2 1

    10K_0402_5%
    GPD7 +3VALW

    17@
    CNV_WR_CLKN CN31 CN20 100K_0402_5%
    40 CNV_WR_CLKN CNV_WR_CLKN GPP_F3

    10K_0402_5% 1 TS@
    @

    @
    CNV_WR_CLKP CP31

    RC810

    10K_0402_5%
    40 CNV_WR_CLKP CNV_WR_CLKP CG25 RC1057
    CNV_WT_CLKN CP34 GPP_D4/IMGCLKOUT0/BK4/SBK4 CH25 10K_0402_5%

    10K_0402_5%1

    10K_0402_5%1

    10K_0402_5% 1

    10K_0402_5%1

    10K_0402_5%1

    10K_0402_5%1

    10K_0402_5%1
    40 CNV_WT_CLKN CNV_WT_CLKP CN34 CNV_WT_CLKN GPP_H20/IMGCLKOUT_1 BOARD_ID0
    @
    40 CNV_WT_CLKP CNV_WT_CLKP CR20 BOARD_ID0 BOARD_ID1

    2
    RC1020 1 2 150_0402_1% CP32 GPP_F12/EMMC_DATA0 CM20 BOARD_ID1 BOARD_ID2
    CR32 CNV_WT_RCOMP_0 GPP_F13/EMMC_DATA1 CN19 BOARD_ID2 BOARD_ID3
    CP20 CNV_WT_RCOMP_1 GPP_F14/EMMC_DATA2 CM19 BOARD_ID3 BOARD_ID4
    CK19 GPP_F0/CNV_PA_BLANKING GPP_F15/EMMC_DATA3 CN18 BOARD_ID4 BOARD_ID5
    CG17 GPP_F1 GPP_F16/EMMC_DATA4 CR18 BOARD_ID5 BOARD_ID6
    GPP_F2 GPP_F17/EMMC_DATA5 CP18 BOARD_ID6 BOARD_ID7
    TC1020 1 PAD @ CR14 GPP_F18/EMMC_DATA6 CM18 BOARD_ID7 BOARD_ID8
    1 PAD @ CP14 GPP_C8/UART0_RXD GPP_F19/EMMC_DATA7 BOARD_ID9
    TC1021 CN14 GPP_C9/UART0_TXD CM16 BOARD_ID8 BOARD_ID10
    GPP_C10/UART0_RTS# GPP_F20/EMMC_RCLK BOARD_ID9 BOARD_ID11

    10K_0402_5% 1 RC820 2 UMAorN16@


    CM14 CP16
    45 DELINK GPP_C11/UART0_CTS# GPP_F21/EMMC_CLK CR16 BOARD_ID10 BOARD_ID12
    GPP_F11/EMMC_CMD

    10K_0402_5%1 RC3066 2 14or17@


    CJ17 CN16 BOARD_ID11

    @
    GPP_F8/CNV_MFUART2_RXD GPP_F22/EMMC_RESET#

    2 NTS@
    UMA@

    10K_0402_5%1 RC3064 2 NFP@


    CH17

    @
    GPP_F9/CNV_MFUART2_TXD

    @
    CK15 EMMC_RCOMPRC10021 2 200_0402_1% @ @

    @
    CF17 EMMC_RCOMP
    GPP_F23/A4WP_PRESENT

    10K_0402_5% 1 RC826 2

    10K_0402_5% 1 RC818 2

    10K_0402_5% 1 RC819 2

    RC823 2

    RC3065 2

    RC3067 2

    RC3078 2
    RC3117

    RC821

    RC822

    RC824
    +3VS 1/20W_75K_1%_0201
    WHISKEYLAKE-U_BGA1528
    9 of 20
    @ @

    10K_0402_5%1

    10K_0402_5%1

    10K_0402_5%1

    10K_0402_5%1

    10K_0402_5%1

    10K_0402_5%1

    10K_0402_5%1
    RC3102 1 2 10K_0402_5% WLAN_CLKREQ#

    RPC3
    C 1 4 SSD_CLKREQ# C
    2 3 GPU_CLKREQ#

    10K_0404_4P2R_5%

    UC1J
    CLK_PCIE_GPU# AW2 AU1 CLK_PCIE_XDP# 1 TC1001
    20 CLK_PCIE_GPU# CLK_PCIE_GPU AY3 CLKOUT_PCIE_N_0 CLKOUT_ITPXDP_N AU2 CLK_PCIE_XDP 1
    DGPU TC1002
    20 CLK_PCIE_GPU GPU_CLKREQ# CF32 CLKOUT_PCIE_P_0 CLKOUT_ITPXDP_P
    20 GPU_CLKREQ# GPP_B5/SRCCLKREQ0# BT32 SUSCLK
    BC1 GPD8/SUSCLK SUSCLK 40
    BC2 CLKOUT_PCIE_N_1 CK3 XTAL24_U22_IN
    CE32 CLKOUT_PCIE_P_1 XTAL_IN CK2 XTAL24_U22_OUT
    GPP_B6/SRCCLKREQ1# XTAL_OUT
    BD3 CJ1 DIFFCLK_BIASREF 1 RC1007 2 60.4_0402_1%
    BC3 CLKOUT_PCIE_N_2 CLK_BIASREF CM3 CLKIN_XTAL_LCP
    CF30 CLKOUT_PCIE_P_2 CLKIN_XTAL CLKIN_XTAL_LCP 40
    GPP_B7/SRCCLKREQ2# BN31 RTC_X1
    CLK_PCIE_SSD# BH3 RTCX1 BN32 RTC_X2
    37 CLK_PCIE_SSD# CLK_PCIE_SSD BH4 CLKOUT_PCIE_N_3 RTCX2
    SSD 37 CLK_PCIE_SSD SSD_CLKREQ# CE31 CLKOUT_PCIE_P_3 SRTC_RST#
    BR37
    37 SSD_CLKREQ# GPP_B8/SRCCLKREQ3# SRTCRST# BR34 RTC_RST#
    CLK_PCIE_WLAN# BA1 RTCRST#
    40 CLK_PCIE_WLAN# CLK_PCIE_WLAN BA2 CLKOUT_PCIE_N_4
    WLAN 40 CLK_PCIE_WLAN WLAN_CLKREQ# CE30 CLKOUT_PCIE_P_4
    40 WLAN_CLKREQ# GPP_B9/SRCCLKREQ4#
    BE1
    BE2 CLKOUT_PCIE_N_5
    CF31 CLKOUT_PCIE_P_5
    GPP_B10/SRCCLKREQ5#
    B B

    10 of 20
    WHISKEYLAKE-U_BGA1528
    @

    1U_0402_6.3V6K
    CLKIN_XTAL_LCP RC2014 1 2 10K_0402_5%
    RC3035 2 1 0_0402_5%
    VCCRTC 1
    CC4237 1 2 33P_0402_50V8J

    CC1001
    EXC24CH900U_4P
    XTAL24_U22_IN_R 4 3 XTAL24_U22_IN @ RC1003
    4 3 1 2 2 SRTC_RST#
    20K_0402_1%
    XTAL24_U22_OUT_R 1 2 XTAL24_U22_OUT
    1 2 SUSCLK RC1001 1 @ 2 1K_0402_5% RC1004 RC1005
    L1 EMC_NS@ 1 2 RTC_RST# 1 2
    EC_RTC_RST# 44
    SM070004400

    1
    1U_0402_6.3V6K
    20K_0402_1% 1 0_0402_5%
    RC3034 1 2 0_0402_5%
    CC1002

    JCMOS2
    JCMOS1
    2 @
    @

    1
    RC10091 2 200K_0402_1% RTC_X1 Place Bottom

    A YC2 RC1008 2 1 10M_0402_5% RTC_X2 A


    4 3 XTAL24_U22_OUT_R
    NC2 3 YC1
    XTAL24_U22_IN_R 1 2 1 2
    1 1 NC1 1
    CC1005 CC1006 2 32.768KHZ_9PF_X1A0001410002 2
    12P_0402_50V8-J 24MHZ_12PF_7V24000023 15P_0402_50V8J
    2 2 CC1003 CC1004
    Security Classification LC Future Center Secret Data Title
    8P_50V_B_NPO_0402 8P_50V_B_NPO_0402
    1 1
    Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (CSI2,EMMC,CLOCK)
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    Size Document Number
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS441/FS540
    Date: Wednesday, October 16, 2019 Sheet 10 of 61
    5 4 3 2 1
    5 4 3 2 1

    2
    CC1101
    0.1U_0402_25V6
    EMC_NS@ UC1K
    1
    RC1101 1 2 0_0402_5% PLT_RST#_R BJ35 BJ37 PM_SLP_S0#1
    32 PLT_RST# SYS_RESET# CN10 GPP_B13/PLTRST# GPP_B12/SLP_S0# BU36 TC1110
    PCH_RSMRST#_R BR36 SYS_RESET# GPD4/SLP_S3# PM_SLP_S3# 44
    RC1102 1 2 0_0402_5% BU27
    44 EC_RSMRST# RSMRST# GPD5/SLP_S4# BT29 1 PM_SLP_S4# 44
    D 1 CPU_PROCPWRGD AR2 GPD10/SLP_S5# TC1109 D
    VCCST_PWRGD_R TC1101
    2 60.4_0402_1% VCCST_PWRGD BJ2 PROCPWRGD
    RC1103 1 BU29 1
    VCCST_PWRGOOD SLP_SUS# BT31 TC1407
    RC1106 1 2 0_0402_5% SYS_PWROK_RCR10 SLP_LAN# BT30
    44 SYS_PWROK PCH_PWROK_RBP31 SYS_PWROK GPD9/SLP_WLAN# PM_SLP_WLAN# 40
    RC1107 1 2 0_0402_5% BU37
    44 PCH_PWROK EC_RSMRST# RC1119 1 2 0_0402_5% PCH_DPWROK_R
    BP30 PCH_PWROK GPD6/SLP_A#
    DSW_PWROK BU28 PBTN_OUT#_R 1 RC1108 2 0_0402_5%
    SUSWARN# BV34 GPD3/PWRBTN# BU35 AC_PRESENT_R 2 RC1110 1 0_0402_5% PBTN_OUT# 44
    GPP_A13/SUSWARN#/SUSPWRDACK GPD1/ACPRESENT AC_PRESENT 44
    RC1189 1 @ 2 10K_0402_5% SUSACK# BY32 BV36 BATLOW#
    GPP_A15/SUSACK# GPD0/BATLOW# VCCRTC
    PCIE_WAKE# BU30
    40 PCIE_WAKE# PCH_LAN_WAKE# BU32 WAKE# BR35 INTVRMEN RC1109 2 1 1M_0402_5% +3VALW_PCH
    1 BU34 GPD2/LAN_WAKE# INTRUDER#
    TC1408 GPD11/LANPHYPC CC37 RC3100 1 2 100K_0402_5%
    GPP_B11/EXT_PWR_GATE# CC36
    32 FP_RESETN GPP_B2/VRALERT#
    BT27 RC1188 1 2 4.7K_0402_5% 3.0V Select (Input pin must always be driven to a valid logic level)
    INPUT3VSEL
    External pull-up or pull-down is required
    0 = 3.3V supply is 3.3V +/- 5%
    1 = 3.3V supply is 3.0V +/- 5%
    11 of 20 Note: This strap should only be used for specific targeted 1S battery systems
    WHISKEYLAKE-U_BGA1528
    @
    UC1Q

    1 CPU_CFG0 T4 F37
    TC1103 CFG_0 RSVD_TP5 F34
    1 CPU_CFG1 R4 RSVD_TP4
    +3VALW TC1126 1 CPU_CFG2 T3 CFG_1 CP36
    TC1409 1 CPU_CFG3 R3 CFG_2 IST_TRIG CN36
    @ IT19 CPU_CFG4 CFG_3 RSVD_TP3
    RC1112 1 2 8.2K_0402_5% BATLOW# J4
    C 1 CPU_CFG5M4 CFG_4 C
    PCIE_WAKE# TC1410 1 CPU_CFG6 J3 CFG_5
    RC1113 1 2 1K_0402_5% +VCCST_CPU BJ36
    TC1411 1 CPU_CFG7M3 CFG_6 RSVD72 BJ34
    TC1412 CFG_7 RSVD73

    2
    RPC6 R2
    1 4 AC_PRESENT_R RC1115 RC1172 N2 CFG_8 BK34
    2 3 PCH_LAN_WAKE# 1K_0402_5% 1K_0402_5% R1 CFG_9 TP1 BR18
    N1 CFG_10 TP3
    10K_0404_4P2R_5% RC1116 J2 CFG_11

    1
    1 2 VCCST_PWRGD_R L2 CFG_12
    44 EC_VCCST_PWRGD J1 CFG_13 BT9
    1 CFG_14 RSVD74
    +3VALW_PCH 22_0402_5% L1 BT8
    CC1102 CFG_15 RSVD75
    RC3118 1 @ 2 100K_0402_5% PM_SLP_S0# 1000P_0402_50V7K L3 BP8
    2 N3 CFG_16 RSVD76 BP9
    RC1117 1 @ 2 10K_0402_5% SUSWARN# CFG_18 RSVD77
    L4
    CFG_17 CR4
    +3VS N4 RSVD29
    CFG_19
    CP3
    AB5 RSVD26 CR3
    RC1118 1 2 10K_0402_5% SYS_RESET# CFG_RCOMP RSVD27

    2
    IT16 1 ITP_PMODE
    W4
    RC1163 @ ITP_PMODE
    49.9_0402_1% CG2
    CG1 RSVD25
    D5101 RSVD24 AU3

    1
    RC3083 1 2 100K_0402_5% PCH_RSMRST#_R @ RSVD78 AT3
    RC11221 2 0_0402_5% +3V_PWRGD_R 1 2 EC_RSMRST# RSVD79
    54 +3VALW_PG
    CC1103 2 1 1000P_0402_50V7K
    @ 54,55 ALW_PWRGD RC11231 2 0_0402_5% 1 2 H4
    RC3103 1 2 10K_0402_5% PCH_PWROK RB521CM-30T2R_VMN2M-2 2 H3 RSVD34 AN1
    1 RSVD33 RSVD8 AN2
    CC1104 1 2 1000P_50V_K_X7R_0201 CC1105 CC1107 BV24 RSVD9
    B BV25 RSVD22 AN4 B
    2200P_0402_50V7K 0.01U_0201_10V6K RSVD23 RSVD11
    RC3104 1 2 10K_0402_5% SYS_PWROK 2 1 AN3
    @
    Add to fix Reset&PWRGD test fail issue RSVD10
    0.01U_0201_10V6K
    CC4234 1 2 AL2
    @ RSVD80 AL1
    RSVD81

    G3
    RSVD69 AL4
    G4 RSVD82
    +3VALW RSVD70 AL3
    RSVD83
    U4404
    330P_0402_50V7K 1 2 CC1108 PLT_RST#_R 1 5 BK36 BP34
    PLT_RST# 2 NC VCC BK35 RSVD17 TP2 BP36
    100K_0402_5% 2 1 RC1124 3 A 4 RSVD16 VSS_392 BP35
    GND Y PLT_RST#_B 26,37,40,44 W3 TP5
    10K_0402_5% 1 @ 2 RC3069 AC_PRESENT_R SN74LVC1G17DCKR_SC70-5 AM4 RSVD35 C34
    RSVD7 RSVD68
    @
    RPC811 AM3 A34
    1 4 PM_SLP_S3# RC3107 RSVD71 RSVD_TP1 B35
    2 3 PM_SLP_S4# PLT_RST# 1 2 PLT_RST#_B RSVD67
    0_0402_5% CR35 1
    RSVD84 TC1414
    100K_0404_4P2R_5%
    A35
    D34 RSVD1 AH26
    RSVD30 RSVD66 AJ27
    G2 RSVD85
    G1 RSVD32
    RSVD31 E1
    SKTOCC#
    20 of 20

    WHISKEYLAKE-U_BGA1528
    A A
    @

    Security Classification LC Future Center Secret Data Title

    Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (SYSTEM PWR MANAGEMENT)
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    Size Document Number
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS441/FS540
    Date: Wednesday, October 16, 2019 Sheet 11 of 61

    5 4 3 2 1
    5 4 3 2 1

    +VCC_GT +VCC_GT
    Icc-GT Max=31A
    Voltage=0~1.52V
    IccMax=70A
    D Voltage=0~1.52V D
    +CPU_CORE +CPU_CORE Rename to +CPU_CORE for QS CPU UC1M

    A5 D15
    UC1L A6 VCCGT8 VCCGT58 D17
    AN9 AW24 A8 VCCGT9 VCCGT59 D18
    AN10 VCCCORE5 VCCCORE35 AW25 +CPU_CORE A11 VCCGT10 VCCGT60 D20
    AN24 VCCCORE1 VCCCORE36 AW26 A12 VCCGT1 VCCGT61 E4
    AN26 VCCCORE2 VCCCORE37 AW27 A14 VCCGT2 VCCGT64 F5
    AN27 VCCCORE3 VCCCORE38 AY24 A15 VCCGT3 VCCGT69 F6
    AP2 VCCCORE4 VCCCORE44 AY26 A17 VCCGT4 VCCGT70 F7
    AP9 VCCCORE6 VCCCORE45 BA5 A18 VCCGT5 VCCGT71 F8
    AP24 VCCCORE9 VCCCORE48 BA7 A20 VCCGT6 VCCGT72 F11
    AP26 VCCCORE7 VCCCORE49 BA8 AA9 VCCGT7 VCCGT65 F14
    AR5 VCCCORE8 VCCCORE50 BA25 AB2 VCCCORE75 VCCGT66 F17
    AR6 VCCCORE13 VCCCORE46 BA27 AB8 VCCCORE76 VCCGT67 F20
    AR7 VCCCORE14 VCCCORE47 BB2 AB9 VCCCORE77 VCCGT68 G11
    AR8 VCCCORE15 VCCCORE51 BB26 AB10 VCCCORE78 VCCGT73 G12
    AR10 VCCCORE16 VCCCORE52 BC5 AC8 VCCCORE79 VCCGT74 G14
    AR25 VCCCORE10 VCCCORE56 BC6 AD9 VCCCORE80 VCCGT75 G15
    AR27 VCCCORE11 VCCCORE57 BC7 AE8 VCCCORE81 VCCGT76 G17
    AT9 VCCCORE12 VCCCORE58 BC9 AE9 VCCCORE82 VCCGT77 G18
    AT24 VCCCORE19 VCCCORE59 BC10 AE10 VCCCORE83 VCCGT78 G20
    AT26 VCCCORE17 VCCCORE53 BC26 AF2 VCCCORE84 VCCGT79 H5
    AU5 VCCCORE18 VCCCORE54 BC27 AF8 VCCCORE85 VCCGT87 H6
    AU6 VCCCORE24 VCCCORE55 BD5 AF10 VCCCORE86 VCCGT88 H7
    AU7 VCCCORE25 VCCCORE63 BD8 AG8 VCCCORE87 VCCGT89 H8
    AU8 VCCCORE26 VCCCORE64 BD10 AG9 VCCCORE88 VCCGT90 H11
    AU9 VCCCORE27 VCCCORE60 BD25 AH9 VCCCORE89 VCCGT80 H12
    AU24 VCCCORE28 VCCCORE61 BD27 +CPU_CORE AJ8 VCCCORE90 VCCGT81 H14
    AU25 VCCCORE20 VCCCORE62 BE9 AJ10 VCCCORE91 VCCGT82 H15
    AU26 VCCCORE21 VCCCORE69 BE24 AK2 VCCCORE92 VCCGT83 H17
    AU27 VCCCORE22 VCCCORE65 BE25 VCORE_VCC_SEN RC1201 1 2 100_0402_1% AK9 VCCCORE93 VCCGT84 H18
    AV2 VCCCORE23 VCCCORE66 BE26 AL8 VCCCORE94 VCCGT85 H20
    AV5 VCCCORE30 VCCCORE67 BE27 AL9 VCCCORE95 VCCGT86 J7
    AV7 VCCCORE32 VCCCORE68 BF2 VCORE_VSS_SEN RC1203 1 2 100_0402_1% AL10 VCCCORE96 VCCGT95 J8
    AV10 VCCCORE33 VCCCORE70 BF9 AM8 VCCCORE97 VCCGT96 J11
    AV27 VCCCORE29 VCCCORE73 BF24 B3 VCCCORE98 VCCGT91 J14
    AW5 VCCCORE31 VCCCORE71 BF26 B4 VCCGT39 VCCGT92 J17
    AW6 VCCCORE39 VCCCORE72 BG27 B6 VCCGT40 VCCGT93 J20
    C AW7 VCCCORE40 VCCCORE74 B8 VCCGT41 VCCGT94 K2 C
    AW8 VCCCORE41 AN6 VCORE_VCC_SEN B11 VCCGT42 VCCGT98 K11
    AW9 VCCCORE42 VCC_SENSE AN5 VCORE_VSS_SEN VCORE_VCC_SEN 58 B14 VCCGT35 VCCGT97 L7
    AW10 VCCCORE43 VSS_SENSE VCORE_VSS_SEN 58 B17 VCCGT36 VCCGT100 L8
    VCCCORE34 AA3 CPU_SVID_ALERT#_R B20 VCCGT37 VCCGT101 L10
    BB9 VIDALERT# C2 VCCGT38 VCCGT99 M9
    BC24 RSVD3 AA1 CPU_SVID_CLK_R C3 VCCGT49 VCCGT102 N7
    AY9 RSVD4 VIDSCK C6 VCCGT51 VCCGT104 N8
    BB24 RSVD1 AA2 CPU_SVID_DAT_R C7 VCCGT52 VCCGT105 N9
    RSVD2 VIDSOUT C8 VCCGT53 VCCGT106 N10
    Y3 C11 VCCGT54 VCCGT103 P2
    RSVD5 C12 VCCGT43 VCCGT107 P8 +VCC_GT
    BG3 C14 VCCGT44 VCCGT108 R9
    VCCSTG1 +VCCSTG VCCGT45 VCCGT109
    C15 T8
    C17 VCCGT46 VCCGT111 T9 +CPU_CORE VCCGT_VCC_SEN RC1202 1 2 100_0402_1%
    C18 VCCGT47 VCCGT112 T10
    12 of 20 VCCGT48 VCCGT110
    C20 U8
    WHISKEYLAKE-U_BGA1528 D4 VCCGT50 VCCGT114 U10 VCCGT_VSS_SEN RC1204 1 2 100_0402_1%
    @ D7 VCCGT62 VCCGT113 V2
    D11 VCCGT63 VCCCORE100 V9
    D12 VCCGT55 VCCGT116 W8
    D14 VCCGT56 VCCGT117 W9
    Y10 VCCGT57 VCCGT118 Y8
    VCCCORE99 VCCCORE101
    SVID +VCCST_CPU E3 VCCGT_VCC_SEN
    VCCGT_SENSE D2 VCCGT_VSS_SEN VCCGT_VCC_SEN 58
    VSSGT_SENSE VCCGT_VSS_SEN 58
    13 of 20
    WHISKEYLAKE-U_BGA1528
    @
    1
    CC1201
    1/16W_43_5%_0402
    2

    1
    56_0402_5%

    @ 0.1U_0402_10V7K
    100_0402_1%

    @
    2
    1

    RC1206 2

    2
    RC1205

    RC1207

    B B

    RC1208 1 2 220_0402_1% CPU_SVID_ALERT#_R


    58 VR_SVID_ALRT#

    RC1209 1 2 0_0402_5% CPU_SVID_CLK_R


    58 VR_SVID_CLK

    RC1210 1 2 0_0402_5% CPU_SVID_DAT_R


    58 VR_SVID_DAT

    A A

    Security Classification LC Future Center Secret Data Title

    Issued Date 2016/12/14 Deciphered Date 2017/12/13 MCP (CPU PWR1)


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    Size Document Number
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS441/FS540
    Date: Wednesday, October 16, 2019 Sheet 12 of 61
    5 4 3 2 1
    5 4 3 2 1

    +VCCST_CPU +VCCIO +VCCSTG +VCCIO


    +VCCST_CPU +1.2V
    120mA
    UC1N

    0.1U_0402_10V7K
    RC1302 1 2 0_0402_5% AK24 Icc-IO Max=4A

    1U_0402_6.3V6K

    1U_0402_6.3V6K
    AD36 VCCIO1 AK26
    1 1 1 VDDQ1 VCCIO2 Voltage=0.95V
    AH32 AL24

    CC1343

    CC4223
    VDDQ2 VCCIO3

    CC4224
    RC1303 1 @ 2 0_0402_5% 2800mA AH36 AL25

    1U_0402_6.3V6K
    AM36 VDDQ3 VCCIO4 AL26
    2 2 2 1 VDDQ4 VCCIO5
    Reserved for VCCST/VCCSTG/VCCPLL AN32 AL27 4000mA

    CC1344
    D VDDQ5 VCCIO6 D
    power optimized AW32 AM25
    AY36 VDDQ6 VCCIO7 AM27
    2 BE32 VDDQ7 VCCIO8 BH24 +VCCSA
    BH36 VDDQ8 VCCIO9 BH25
    R32 VDDQ9 VCCIO10 BH26
    Y36 VDDQ10 VCCIO11 BH27 VCCSA_VCC_SEN RC1305 1 2 100_0402_1%
    VDDQ11 VCCIO12 BJ24
    VCCIO13 BJ26 +VCCSA VCCSA_VSS_SEN RC1306 1 2 100_0402_1%
    +1.2V +VCCSFR_OC VCCIO14 BP16
    BC28 VCCIO15 BP18
    RSVD1 VCCIO16
    Icc-ST Max=60mA Icc-SA Max=6A
    RC1307 1 2 0_0402_5% Voltage=1.05V +VCCST_CPU
    BP11 BG8 6A Voltage=0~1.52V
    BP2 VCCST1 VCCSA2 BG10

    1U_0402_6.3V6K
    VCCST2 VCCSA1 BH9
    1 VCCSA3
    Icc-STG Max=20mA BJ8 +VCCIO

    CC1345
    BG1 VCCSA5 BJ9
    Voltage=1.05V +VCCSTG
    BG2 VCCSTG1 VCCSA6 BJ10
    2 VCCSTG2 VCCSA4 BK8 VCCIO_SENSE RC3114 2 1 1/20W_100_1%_0201
    Icc-OC Max=120mA VCCSA9
    Voltage=1.2V +VCCSFR_OC BL27 BK25
    BM26 VCCPLL_OC1 VCCSA7 BK27 VSSIO_SENSE RC3115 2 1 1/20W_100_1%_0201
    VCCPLL_OC2 VCCSA8 BL8
    +VCCST_CPU +VCCPLL_CPU BR11 VCCSA13 BL9
    Icc-PLL Max=130mA VCCPLL1 VCCSA14
    Voltage=1.05V +VCCPLL_CPU 130mA
    BT11 BL10
    VCCPLL2 VCCSA10 BL24
    VCCSA11 BL26
    RC1308 VCCSA12 BM24
    120mA
    22UC_6.3VC_MC_X5RC_0603

    1 2 VCCSA15 BN25
    VCCSA16
    1U_0402_6.3V6K

    1U_0402_6.3V6K
    0.1U_0402_10V7K

    0_0402_5% BP28 VCCIO_SENSE


    1
    2 1 1 1 1 VCCIO_SENSE TC1301
    BP29 VSSIO_SENSE
    1
    CC4228

    CC1346

    CC4229
    VSSIO_SENSE TC1302
    CC1347

    CC1399
    10U_0603_10V6K BE7 VCCSA_VSS_SEN
    @ 1 2 2 2 2 VSSSA_SENSE BG7 VCCSA_VCC_SEN VCCSA_VSS_SEN 58
    @ VCCSA_SENSE VCCSA_VCC_SEN 58
    14 of 20 +1.2V 1x22uF, 11x10uF, 4x1uF
    WHISKEYLAKE-U_BGA1528
    C C
    @

    22U_0603_6.3V6-M
    CC1366

    10U_0603_6.3V6M
    CC4231

    10U_0603_6.3V6M
    CC4212

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    1U_0201_6.3V6-M

    1U_0201_6.3V6-M

    1U_0201_6.3V6-M

    1U_0201_6.3V6-M

    1U_0201_6.3V6-M

    1U_0201_6.3V6-M

    1U_0201_6.3V6-M
    1U_0201_6.3V6-M
    1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
    1

    CC1321

    CC1322

    CC1323

    CC1324

    CC4233

    CC4232

    CC4236
    CC4235
    CC4213

    CC4214

    CC1315

    CC1316

    CC1317

    CC1318

    CC1319

    CC1320
    2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
    UC1O 2
    K12
    K14 RSVD46 AA24 @ @ @
    K15 RSVD47 RSVD38 AA26 @
    K17 RSVD48 RSVD39 AB25
    K18 RSVD49 RSVD40 AC24
    K20 RSVD50 RSVD41 AC25
    RSVD51 RSVD42 +VCCIO
    L25 AC26
    M24 RSVD52 RSVD43 AD24 6x10uF, 8x1uF and reserve 4 0402
    M26 RSVD53 RSVD44 AD26
    P24 RSVD54 RSVD45

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M
    RSVD55 @ @ @

    1U_0201_6.3V6-M

    1U_0201_6.3V6-M

    1U_0201_6.3V6-M

    1U_0201_6.3V6-M

    1U_0201_6.3V6-M

    1U_0201_6.3V6-M

    1U_0201_6.3V6-M

    1U_0201_6.3V6-M

    1U_0201_6.3V6-M

    1U_0201_6.3V6-M

    1U_0201_6.3V6-M
    P26 V25
    R24 RSVD56 RSVD64 T25 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

    CC1303

    CC1304

    CC1305

    CC1306

    CC4218

    CC4225

    CC4226

    CC4227

    CC4222

    CC1367

    CC1368
    R25 RSVD57 RSVD65

    CC1307

    CC1308

    CC1309

    CC1310

    CC1301

    CC1302
    R26 RSVD58
    RSVD59
    2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
    W25
    V24 RSVD60
    RSVD61
    Y25
    Y24 RSVD62
    RSVD63

    15 of 20
    WHISKEYLAKE-U_BGA1528
    @
    B B

    +1.05VALW +VCCIO
    10U_0603_6.3V6M

    22U_0603_6.3V6-M
    10U_0603_6.3V6M

    C1301

    @ 1 1
    22U_0603_6.3V6-M
    CC1348

    1 1
    CC1351
    CC1349

    RC1309
    1 2 VCCIO_EN 2 2
    44 EC_VCCIO_EN 2 2 UC1302 @
    1 @
    0_0402_5% 1 14
    CC1350 2 IN1_1 OUT1_2 13
    0.01U_16V_K_X7R_0402 IN1_2 OUT1_1
    2 VCCIO_EN 3 12 CC1352 1 2 1000P_0402_50V7K
    @ 46 VCCIO_EN EN1 CT1
    +5VALW 4 11
    VBIAS GND
    VCCST_EN 5 10 CC1353 1 2 1000P_0402_50V7K
    +1.05VALW EN2 CT2 +VCCST_CPU
    RC1310 6 9
    1 2 VCCST_EN 7 IN2_1 OUT2_2 8
    44 EC_VCCST_EN IN2_2 OUT2_1
    10U_0603_6.3V6M

    10U_0603_6.3V6M

    1
    0_0402_5% 1 15 1
    CC1355 Thermal Pad
    CC1356

    CC1354

    0.01U_16V_K_X7R_0402
    2 G2898KD1U_TDFN14P_2X3
    @ 2 2

    A A
    @

    Security Classification LC Future Center Secret Data Title

    Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (CPU PWR2)


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS441/FS540
    Date: Wednesday, October 16, 2019 Sheet 13 of 61
    5 4 3 2 1
    5 4 3 2 1

    D D

    Refer to DOC# 566439-P58

    1.625A
    +1.05VALW

    1U_0402_6.3V6K
    UC1P
    +3VALW_PCH
    +1.8VALW 1
    BP20

    CC1402
    1U_0402_6.3V6K
    BW16 VCCPRIM_1P051 CB16
    1 Close to BP20 VCCPRIM_1P059 VCCPRIM_3P33
    BW18

    CC1410
    @ 2 BW19 VCCPRIM_1P0510
    BY16 VCCPRIM_1P0511
    Close to CP17 2 VCCPRIM_1P0512
    CA14 BR23 2mA
    VCCPRIM_1P0514 VCCRTC VCCRTC

    0.1U_0402_10V7K
    698mA CC15 BY20

    1U_0402_6.3V6K
    VCCPRIM_1P81 VCCPRIM_1P0513 +1.05VALW
    CD15 BP24 VCCRTCEXT 1 1
    CD16 VCCPRIM_1P84 DCPRTC

    CC1417
    CC1416
    CP17 VCCPRIM_1P85

    1U_0402_6.3V6K
    VCCPRIM_1P88 BR20 @1
    VCCPRIM_1P053 +1.05VALW 2 2
    CB22

    CC1413
    199mA

    1U_0402_6.3V6K
    +3VALW_PCH VCCPRIM_3P34
    Combine BP20 group
    1 1 Close to CP29 CB23 BT12
    VCCPRIM_3P35 VCCAPLL_1P053 +1.05VALW
    CC22

    CC1424

    1U_0402_6.3V6K
    @
    CC1421 CC23 VCCPRIM_3P36 BP14 9mA 2
    VCCPRIM_3P37 VCCA_BCLK_1P05 +1.05VALW 1
    0.1U_0402_10V7K CD22

    CC1422
    C 2 2 CD23 VCCPRIM_3P38 BR14 C
    CP29 VCCPRIM_3P39 VCCAPLL_1P051
    VCCPRIM_3P310 BU12 42mA 2
    VCCA_SRC_1P05 +1.05VALW RC1405
    4.26A BU15
    +1.05VALW VCCPRIM_CORE1
    BU22 CP5 2mA 1 2
    VCCPRIM_CORE2 VCCA_XTAL_1P05 +1.05VALW

    1
    BV15 1/10W_0_+-5%_0603

    1U_0402_6.3V6K
    VCCPRIM_CORE3

    22U_4V_M_X5R_0603
    Close to BV18 CC1414 BV16 BY24 1 1
    1U_0402_6.3V6K BV18 VCCPRIM_CORE4 VCCDPHY_1P242 CA24 +VCCDPHY_1P24

    CC1420

    CC4230
    2
    BV19 VCCPRIM_CORE5 VCCDPHY_1P244 @
    @ BV20 VCCPRIM_CORE6 BY23
    BV22 VCCPRIM_CORE7 VCCDPHY_1P241 CA23 2 2
    BW20 VCCPRIM_CORE8 VCCDPHY_1P243 CP25 610mA

    4.7U_0402_6.3V6M
    BW22 VCCPRIM_CORE9 VCCDPHY_EC_1P24
    +VCCDSW_1P0 VCCPRIM_CORE10 1
    CA12 BT23

    CC1415
    1U_0402_6.3V6K

    VCCPRIM_CORE11 VCCDSW_3P32 +3VALW


    CA16

    1U_0402_6.3V6K
    1 VCCPRIM_CORE12
    CA18 BR12
    CC1408

    27mA
    VCCPRIM_CORE13 VCCA_19P2_1P05 +1.05VALW 1 2
    CA19

    CC1409
    CA20 VCCPRIM_CORE14
    2 CB12 VCCPRIM_CORE15
    CB14 VCCPRIM_CORE16 2
    VCCPRIM_CORE17
    Close to CP25
    CB15 CC18 Close to BR24
    PCH Internal VRM BT24 VCCPRIM_CORE18 VCCPRIM_1P82 CC19
    VCCDSW_1P05 VCCPRIM_1P83 CD18
    VCCPRIM_1P86 +1.8VALW
    BU14 CD19
    VCCAPLL_1P054 VCCPRIM_1P87 CP23

    1U_0402_6.3V6K
    2.574A 1
    BV12 VCCPRIM_1P89 +3VALW_PCH
    +1.05VALW VCCPRIM_MPHY_1P051
    BW12 BW23

    CC1406
    VCCPRIM_MPHY_1P053 VCCPRIM_3P32
    Close to CP23
    BW14
    22U_0603_6.3V6-M

    1 VCCPRIM_MPHY_1P054 2
    BY12
    CC1403

    BY14 VCCPRIM_MPHY_1P055
    Close to BV12 VCCPRIM_MPHY_1P056 Combine CP29 group
    RC1406
    2 1 2 152mA BV2 BP23
    +1.05VALW VCCAMPHYPLL_1P05 VCCPRIM_3P31
    1U_0402_6.3V6K

    1/10W_0_+-5%_0603 1 BR15 CB36 1


    VCCAPLL_1P052 GPP_B0/CORE_VID0 CB35 1 TC1405
    CC1425

    280mA CC12 GPP_B1/CORE_VID1 TC1406


    +1.05VALW VCCDUSB_1P05
    2 Combine BT23 BR24
    +3VALW VCCDSW_3P31
    1 HDA33@20_0402_5% 6mA
    RC1403 BT20
    B +3VALW_PCH VCCHDA B
    +1.8VALW RC1488 1 HDA18@ 2 0_0201_5%
    +3VALW_PCH
    2mA BV23
    VCCSPI
    Combine BP20 group BT18
    +1.05VALW VCCPRIM_1P054
    BT19
    1U_0402_6.3V6K

    BU18 VCCPRIM_1P055
    1 VCCPRIM_1P057
    BU19
    CC1423

    VCCPRIM_1P058
    BT22
    2 BP22 VCCPRIM_1P056
    BV14 VCCPRIM_1P052
    +1.05VALW VCCPRIM_MPHY_1P052
    Combine BV12
    16 of 20
    WHISKEYLAKE-U_BGA1528
    @

    A A

    Security Classification LC Future Center Secret Data Title

    Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (PCH PWR)


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    Size Document Number
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS441/FS540
    Date: Wednesday, October 16, 2019 Sheet 14 of 61
    5 4 3 2 1
    5 4 3 2 1

    UC1T UC1R
    UC1S N6 CF23 CR34 BL7
    BT35 BY25 B37 VSS_290 VSS_362 V4 BT5 VSS_1 VSS_73 AE25
    D6 VSS_145 VSS_217 J18 CB3 VSS_291 VSS_363 BE30 BY5 VSS_2 VSS_74 BM33
    AL32 VSS_146 VSS_218 AU32 P10 VSS_292 VSS_364 CF28 CP35 VSS_3 VSS_75 CM5
    BT36 VSS_147 VSS_219 BY28 B5 VSS_293 VSS_365 W10 CM37 VSS_4 VSS_76 AE27
    D8 VSS_148 VSS_220 J21 CB33 VSS_294 VSS_366 BE31 CK37 VSS_5 VSS_77 BM35
    AL7 VSS_149 VSS_221 AV25 P3 VSS_295 VSS_367 CF3 AW1 VSS_6 VSS_78 CM9
    D D9 VSS_150 VSS_222 BY33 B7 VSS_296 VSS_368 W27 CM1 VSS_7 VSS_79 AE30 D
    AM10 VSS_151 VSS_223 J24 CB4 VSS_297 VSS_369 CF4 BD6 VSS_8 VSS_80 BM36
    BU11 VSS_152 VSS_224 AV28 P33 VSS_298 VSS_370 W30 AY4 VSS_9 VSS_81 CN13
    E23 VSS_153 VSS_225 BY35 B9 VSS_299 VSS_371 BF3 B34 VSS_10 VSS_82 AE7
    AM28 VSS_154 VSS_226 J33 CB7 VSS_300 VSS_372 CG33 E35 VSS_11 VSS_83 BM9
    E27 VSS_155 VSS_227 AV3 P36 VSS_301 VSS_373 W7 A4 VSS_12 VSS_84 CN17
    AM33 VSS_156 VSS_228 BY36 BA10 VSS_302 VSS_374 BF33 AE24 VSS_13 VSS_85 AF27
    BU23 VSS_157 VSS_229 J36 CC11 VSS_303 VSS_375 CG7 AE26 VSS_14 VSS_86 BN30
    E29 VSS_158 VSS_230 AV33 P4 VSS_304 VSS_376 BF36 AF25 VSS_15 VSS_87 CN21
    AM35 VSS_159 VSS_231 J6 BA28 VSS_305 VSS_377 Y26 AG24 VSS_16 VSS_88 AF3
    BU24 VSS_160 VSS_232 AV36 P7 VSS_306 VSS_378 BF4 AG26 VSS_17 VSS_89 BN7
    E31 VSS_161 VSS_233 C1 BA3 VSS_307 VSS_379 CH31 AH24 VSS_18 VSS_90 CN25
    BU25 VSS_162 VSS_234 K21 CC20 VSS_308 VSS_380 Y27 AH25 VSS_19 VSS_91 AF30
    E33 VSS_163 VSS_235 AV4 R27 VSS_309 VSS_381 BG25 B2 VSS_20 VSS_92 CN29
    AN25 VSS_164 VSS_236 C21 BB3 VSS_310 VSS_382 Y30 B36 VSS_21 VSS_93 AF33
    BU7 VSS_165 VSS_237 K22 CC25 VSS_311 VSS_383 BG28 C36 VSS_22 VSS_94 BP15
    E9 VSS_166 VSS_238 AV6 R28 VSS_312 VSS_384 CJ11 C37 VSS_23 VSS_95 AF36
    AN28 VSS_167 VSS_239 C25 BB33 VSS_313 VSS_385 Y33 CN1 VSS_24 VSS_96 AF4
    BV11 VSS_168 VSS_240 K24 CC28 VSS_314 VSS_386 CJ14 CN2 VSS_25 VSS_97 CN5
    F12 VSS_169 VSS_241 AV8 R29 VSS_315 VSS_387 Y35 CN37 VSS_26 VSS_98 AF7
    AN29 VSS_170 VSS_242 C29 BB36 VSS_316 VSS_388 BH28 CP2 VSS_27 VSS_99 BP25
    F15 VSS_171 VSS_243 K25 CC31 VSS_317 VSS_389 CJ19 D1 VSS_28 VSS_100 CN9
    AN30 VSS_172 VSS_244 AW28 R30 VSS_318 VSS_390 Y7 A32 VSS_29 VSS_101 AG10
    F18 VSS_173 VSS_245 C33 BB4 VSS_319 VSS_391 BH29 F33 VSS_30 VSS_102 BP3
    AN31 VSS_174 VSS_246 K27 CC7 VSS_320 VSS_392 CJ23 A3 VSS_31 VSS_103 CP1
    BV3 VSS_175 VSS_247 AW29 R31 VSS_321 VSS_393 BH32 BJ7 VSS_32 VSS_104 BP32
    F2 VSS_176 VSS_248 C4 BC25 VSS_322 VSS_394 CJ28 CJ36 VSS_33 VSS_105 CP11
    AN7 VSS_177 VSS_249 K28 CD11 VSS_323 VSS_395 BH33 A36 VSS_34 VSS_106 AH27
    BV31 VSS_178 VSS_250 AW3 T27 VSS_324 VSS_396 CJ33 BK10 VSS_35 VSS_107 BP33
    F21 VSS_179 VSS_251 C9 CD12 VSS_325 VSS_397 BH35 CJ4 VSS_36 VSS_108 CP13
    AN8 VSS_180 VSS_252 K29 T30 VSS_326 VSS_398 CJ35 AB27 VSS_37 VSS_109 AH28
    BV33 VSS_181 VSS_253 AW30 BC29 VSS_327 VSS_399 BP19 BK2 VSS_38 VSS_110 BP4
    C F24 VSS_182 VSS_254 CA11 CD14 VSS_328 VSS_400 BR16 CK1 VSS_39 VSS_111 CP15 C
    BV4 VSS_183 VSS_255 K3 T33 VSS_329 VSS_401 BY18 AB3 VSS_40 VSS_112 AH29
    F3 VSS_184 VSS_256 AW31 T35 VSS_330 VSS_402 BY19 BK28 VSS_41 VSS_113 BP7
    AP3 VSS_185 VSS_257 CA15 BC32 VSS_331 VSS_403 CC16 AB30 VSS_42 VSS_114 CP19
    BW11 VSS_186 VSS_258 K30 CD24 VSS_332 VSS_404 BU16 BK3 VSS_43 VSS_115 AH30
    F4 VSS_187 VSS_259 AY33 T36 VSS_333 VSS_405 CC14 CK4 VSS_44 VSS_116 CP21
    AP33 VSS_188 VSS_260 CA22 CD25 VSS_334 VSS_406 BR22 AB33 VSS_45 VSS_117 AH31
    BW15 VSS_189 VSS_261 K31 T7 VSS_335 VSS_407 BU20 BK33 VSS_46 VSS_118 BR19
    G21 VSS_190 VSS_262 AY35 BC8 VSS_336 VSS_408 CD20 CK7 VSS_47 VSS_119 CP27
    AP36 VSS_191 VSS_263 K32 CE33 VSS_337 VSS_409 BT14 AB36 VSS_48 VSS_120 AH33
    G27 VSS_192 VSS_264 B12 U26 VSS_338 VSS_410 BP12 BK4 VSS_49 VSS_121 BR25
    AP4 VSS_193 VSS_265 K4 BD28 VSS_339 VSS_411 CB24 CL2 VSS_50 VSS_122 AH35
    G33 VSS_194 VSS_266 B15 CE35 VSS_340 VSS_412 CC24 AB4 VSS_51 VSS_123 CP37
    AR28 VSS_195 VSS_267 CA25 U7 VSS_341 VSS_413 J5 BK7 VSS_52 VSS_124 AJ25
    G35 VSS_196 VSS_268 K9 BD33 VSS_342 VSS_414 U24 CM13 VSS_53 VSS_125 BT15
    G36 VSS_197 VSS_269 B18 CE36 VSS_343 VSS_415 BD7 AB7 VSS_54 VSS_126 AJ28
    AT33 VSS_198 VSS_270 CB11 V26 VSS_344 VSS_416 AR4 BL25 VSS_55 VSS_127 BT16
    BW24 VSS_199 VSS_271 L27 BD35 VSS_345 VSS_417 AU4 CM17 VSS_56 VSS_128 CP9
    G9 VSS_200 VSS_272 B21 CE7 VSS_346 VSS_418 AW4 AC10 VSS_57 VSS_129 AJ7
    AT35 VSS_201 VSS_273 L33 V27 VSS_347 VSS_419 BA6 BL28 VSS_58 VSS_130 CR2
    H21 VSS_202 VSS_274 B23 BD36 VSS_348 VSS_420 BC4 CM21 VSS_59 VSS_131 AK3
    AT36 VSS_203 VSS_275 L35 CF11 VSS_349 VSS_421 BE4 AC27 VSS_60 VSS_132 CR36
    BW7 VSS_204 VSS_276 B25 V3 VSS_350 VSS_422 BE8 BL29 VSS_61 VSS_133 AK33
    H27 VSS_205 VSS_277 CB18 BE10 VSS_351 VSS_423 BA4 CM25 VSS_62 VSS_134 D21
    AT4 VSS_206 VSS_278 L36 CF14 VSS_352 VSS_424 BD4 AC30 VSS_63 VSS_135 AK36
    BY11 VSS_207 VSS_279 B27 V30 VSS_353 VSS_425 BG4 BL30 VSS_64 VSS_136 BT25
    AU10 VSS_208 VSS_280 CB19 BE28 VSS_354 VSS_426 CJ2 CM29 VSS_65 VSS_137 D25
    BY15 VSS_209 VSS_281 L6 CF19 VSS_355 VSS_427 CJ3 BL31 VSS_66 VSS_138 AK4
    H9 VSS_210 VSS_282 B29 V33 VSS_356 VSS_428 AM5 CM31 VSS_67 VSS_139 BT28
    AU28 VSS_211 VSS_283 CB2 BE29 VSS_357 VSS_429 CM4 AD33 VSS_68 VSS_140 AL28
    BY22 VSS_212 VSS_284 N25 CF2 VSS_358 VSS_430 AC5 BL32 VSS_69 VSS_141 BT33
    J12 VSS_213 VSS_285 B31 V36 VSS_359 VSS_431 AG5 CM33 VSS_70 VSS_142 D5
    B AU29 VSS_214 VSS_286 CB20 BE3 VSS_360 VSS_432 CR6 AD35 VSS_71 VSS_143 AL29 B
    J15 VSS_215 VSS_287 N27 VSS_361 VSS_433 VSS_72 VSS_144
    VSS_216 VSS_288 CB25
    VSS_289 19 of 20
    17 of 20
    18 of 20 WHISKEYLAKE-U_BGA1528 WHISKEYLAKE-U_BGA1528
    WHISKEYLAKE-U_BGA1528 @ @
    @

    A A

    Security Classification LC Future Center Secret Data Title

    Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (VSS)


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    Size Document Number
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS441/FS540
    Date: Wednesday, October 16, 2019 Sheet 15 of 61
    5 4 3 2 1
    5 4 3 2 1

    TABLE : CPU ITP DEBUG REPORT


    Individual DCI 2.0
    No use Port w/o connector
    D D

    R591 NO ASM NO ASM ASM


    R593 NO ASM NO ASM ASM
    R594 NO ASM NO ASM ASM
    R595 NO ASM NO ASM ASM
    R596 NO ASM NO ASM ASM
    R657 NO ASM NO ASM ASM
    R658 NO ASM NO ASM ASM
    R102 NO ASM ASM NO ASM
    R597 NO ASM ASM NO ASM
    R9907 NO ASM ASM ASM
    JXDP1 NO ASM ASM NO ASM
    C70 NO ASM ASM NO ASM
    R96 NO ASM ASM NO ASM
    R101 NO ASM ASM NO ASM
    R9909 NO ASM ASM ASM
    R9910 NO ASM ASM ASM
    R9916 NO ASM ASM ASM
    R99 NO ASM ASM ASM
    R9912 NO ASM ASM ASM
    R9934 NO ASM ASM ASM
    R9930 NO ASM ASM ASM
    C C
    R9931 NO ASM ASM ASM
    R9932 NO ASM ASM ASM
    R9933 NO ASM ASM ASM

    LOGIC

    TABLE : PCH ITP DEBUG REPORT

    No use Individual DCI 2.0


    Port w/o connector

    R93 NO ASM ASM NO ASM


    JXDP1 NO ASM ASM NO ASM
    R9917 NO ASM ASM NO ASM
    R101 NO ASM ASM NO ASM
    R9908 NO ASM ASM NO ASM
    R9911 NO ASM ASM NO ASM
    R9913 NO ASM ASM NO ASM
    R9915 NO ASM ASM NO ASM

    LOGIC

    B TABLE : Functional Strap B

    GPP_B18/GSPI0_MOSI (No Reboot) R563


    HIGH Enable "No Reboot" Mode ASM
    LOW Disable "No Reboot" Mode (Default ) NO ASM LOGIC

    A A

    Security Classification LC Future Center Secret Data Title

    Issued Date 2016/12/14 Deciphered Date 2017/12/13 XDP


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    Size
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS441/FS540
    Date: Wednesday, October 16, 2019 Sheet 16 of 61
    5 4 3 2 1
    5 4 3 2 1

    Apply X76 BOM to control DDP Memory Down stuff components!


    DDRA_BG1_R R10177 1 2 0_0402_5% DDRA_BG1
    DDRA_BG1 5 DDRA_DQ[0..63]
    DDP@ DDRA_DQ[0..63] 5,6

    1
    UD1 UD2
    R10176 DDRA_DQS#[0..7]
    DDRA_MA0 P3 G2 DDRA_DQ1 DDRA_MA0 P3 G2 DDRA_DQ27 DDRA_DQS#[0..7] 5,6
    0_0402_5%
    DDRA_MA1 P7 A0 DQL0 F7 DDRA_DQ6 DDRA_MA1 P7 A0 DQL0 F7 DDRA_DQ25 SDP@ DDRA_DQS[0..7]
    DDRA_MA2 R3 A1 DQL1 H3 DDRA_DQ7 DDRA_MA2 R3 A1 DQL1 H3 DDRA_DQ31 DDRA_DQS[0..7] 5,6

    2
    DDRA_MA3 N7 A2 DQL2 H7 DDRA_DQ4 DDRA_MA3 N7 A2 DQL2 H7 DDRA_DQ28 Byte 3 DDRA_MA[0..13]
    DDRA_MA4 N3 A3 DQL3 H2 DDRA_DQ3 DDRA_MA4 N3 A3 DQL3 H2 DDRA_DQ30 DDRA_MA[0..13] 5
    DDRA_MA5 P8 A4 DQL4 H8 DDRA_DQ0 Byte 0 DDRA_MA5 P8 A4 DQL4 H8 DDRA_DQ29 +0.6VS +1.2V
    DDRA_MA6 P2 A5 DQL5 J3 DDRA_DQ2 DDRA_MA6 P2 A5 DQL5 J3 DDRA_DQ26
    DDRA_MA7 R8 A6 DQL6 J7 DDRA_DQ5 DDRA_MA7 R8 A6 DQL6 J7 DDRA_DQ24
    A7 DQL7 A7 DQL7

    1
    DDRA_MA8 R2 A3 DDRA_DQ10 DDRA_MA8 R2 A3 DDRA_DQ21
    A8 DQU0 A8 DQU0 2
    DDRA_MA9 R7 B8 DDRA_DQ13 DDRA_MA9 R7 B8 DDRA_DQ23 RD1702
    DDRA_MA10 M3 A9 DQU1 C3 DDRA_DQ11 DDRA_MA10 M3 A9 DQU1 C3 DDRA_DQ22 Byte 2 UD1_DDRA_UZQ R10145 1 SDP@ 2 0_0402_5% 0_0402_5% CD1702 MD@
    DDRA_MA11 T2 A10/AP DQU2 C7 DDRA_DQ9 DDRA_MA11 T2 A10/AP DQU2 C7 DDRA_DQ16 @
    D
    DDRA_MA12 M7 A11 DQU3 C2 DDRA_DQ14 Byte 1 DDRA_MA12 M7 A11 DQU3 C2 DDRA_DQ17 RD228 1 DDP@ 2 240_0402_1% 1
    .01U_0402_16V7-K D

    2
    DDRA_MA13 T8 A12/BC_N DQU4 C8 DDRA_DQ8 DDRA_MA13 T8 A12/BC_N DQU4 C8 DDRA_DQ18
    A13 DQU5 D3 DDRA_DQ15 A13 DQU5 D3 DDRA_DQ20 UD2_DDRA_UZQ R10147 1 SDP@ 2 0_0402_5% MD@
    DQU6 DQU6 1
    DDRA_MA14_WE# L2 D7 DDRA_DQ12 DDRA_MA14_WE# L2 D7 DDRA_DQ19 DDRA_CLK0# RD1704 1 2 1/20W_33_1%_0201
    5 DDRA_MA14_WE# DDRA_MA15_CAS# WE_N/A14 DQU7 DDRA_MA15_CAS# WE_N/A14 DQU7 DDRA_CLK0 +1.2V
    M8 M8 RD231 1 DDP@ 2 240_0402_1% @ CC501 RD1705 1 2 1/20W_33_1%_0201
    5 DDRA_MA15_CAS# DDRA_MA16_RAS# L8 CAS_N/A15 +1.2V DDRA_MA16_RAS# L8 CAS_N/A15 +1.2V 3.3P_50V_C_NPO_0402 MD@
    5 DDRA_MA16_RAS# RAS_N/A16 D1 RAS_N/A16 D1 UD3_DDRA_UZQ 2
    R10148 1 SDP@ 2 0_0402_5%
    DDRA_CLK0# K8 VDD1 J1 DDRA_CLK0# K8 VDD1 J1 DDRA_ALERT# RD1741 1 MD@ 2 49.9_0402_1%
    5 DDRA_CLK0# DDRA_CLK0 CK_C VDD2 DDRA_CLK0 CK_C VDD2
    K7 L1 K7 L1 RD232 1 DDP@ 2 240_0402_1%
    5 DDRA_CLK0 CK_T VDD3 CK_T VDD3
    R1 R1
    DDRA_CKE0 K2 VDD4 B3 DDRA_CKE0 K2 VDD4 B3 UD4_DDRA_UZQ R10151 1 SDP@ 2 0_0402_5%
    5 DDRA_CKE0 CKE VDD5 CKE VDD5 +0.6VS
    G7 G7
    DDRA_DQS#0 F3 VDD6 B9 DDRA_DQS#3 F3 VDD6 B9 RD233 1 DDP@ 2 240_0402_1%
    DDRA_DQS0 G3 DQSL_C VDD7 J9 DDRA_DQS3 G3 DQSL_C VDD7 J9
    DQSL_T VDD8 +1.2V DQSL_T VDD8 MD@
    DDRA_DQS#1 A7 L9 DDRA_DQS#2 A7 L9 DDRA_CS0# RD1708 1 2 1/20W_36_1%_0201
    +1.2V DDRA_DQS1 B7 DQSU_C VDD9 T9 DDRA_DQS2 B7 DQSU_C VDD9 T9 DDRA_ODT0 MD@
    RD1709 1 2 1/20W_36_1%_0201
    DQSU_T VDD10 DQSU_T VDD10 DDRA_CKE0 RD1710 1 MD@ 2 1/20W_36_1%_0201
    RD1712 1 2 0_0402_5% DDRA_DM1 E2 A1 RD1713 1 2 0_0402_5% DDRA_DM2 E2 A1
    RD1715 1 2 0_0402_5% DDRA_DM0 E7 NF/UDM_N/UDBI_N VDDQ1 C1 RD1716 1 2 0_0402_5% DDRA_DM3 E7 NF/UDM_N/UDBI_N VDDQ1 C1 DDRA_MA0 RD1711 1 MD@ 2 1/20W_36_1%_0201
    NF/LDM_N/LDBI_N VDDQ2 G1 NF/LDM_N/LDBI_N VDDQ2 G1 DDRA_MA1 RD1714 1 MD@ 2 1/20W_36_1%_0201
    DDRA_BS0# N2 VDDQ3 F2 DDRA_BS0# N2 VDDQ3 F2 DDRA_MA2 RD1717 1 MD@ 2 1/20W_36_1%_0201
    5 DDRA_BS0# DDRA_BS1# BA0 VDDQ4 DDRA_BS1# BA0 VDDQ4 +1.2V DDRA_MA3
    N8 J2 N8 J2 RD1718 1 MD@ 2 1/20W_36_1%_0201
    5 DDRA_BS1# BA1 VDDQ5 BA1 VDDQ5
    F8 F8
    DDRA_ACT# L3 VDDQ6 J8 DDRA_ACT# L3 VDDQ6 J8 DDRA_MA4 RD1719 1 MD@ 2 1/20W_36_1%_0201
    5 DDRA_ACT# DDRA_CS0# ACT_N VDDQ7 DDRA_CS0# ACT_N VDDQ7 DDRA_MA5
    L7 A9 L7 A9 +2.5V_DDR RD1720 1 MD@ 2 1/20W_36_1%_0201
    5 DDRA_CS0# CS_N VDDQ8 CS_N VDDQ8

    1
    DDRA_ALERT# P9 D9 DDRA_ALERT# P9 D9 DDRA_MA6 RD1721 1 MD@ 2 1/20W_36_1%_0201
    5 DDRA_ALERT# ALERT_N VDDQ9 +2.5V_DDR ALERT_N VDDQ9 1
    G9 G9 CD1701 RD1701 DDRA_MA7 RD1722 1 MD@ 2 1/20W_36_1%_0201
    DDRA_BG0 M2 VDDQ10 DDRA_BG0 M2 VDDQ10 .1U_0402_10V6-K 1.8K_0402_1%
    5 DDRA_BG0 BG0 BG0 DDRA_MA8
    B1 B1 MD@ RD1723 1 MD@ 2 1/20W_36_1%_0201
    DDRA_ODT0 VPP1 DDRA_ODT0 VPP1 @ 2 DDRA_MA9
    K3 R9 K3 R9 RD1724 1 MD@ 2 1/20W_36_1%_0201

    2
    5 DDRA_ODT0 ODT VPP2 ODT VPP2 DDRA_MA10

    MD@

    MD@

    MD@
    RD1725 1 MD@ 2 1/20W_36_1%_0201
    DDRA_PAR T3 M1 +VREF_CA_MD DDRA_PAR T3 M1 +VREF_CA_MD RD1703 DDRA_MA11 RD1726 1 MD@ 2 1/20W_36_1%_0201

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K
    5 DDRA_PAR PAR VREFCA PAR VREFCA 1 2 +VREF_CA_MD

    .047U_0402_16V7K
    1 1 1 1 5 DDR_SA_VREFCA
    RD1729 1 MD@ 2 10K_0402_5% TEN_UD1 N9 E1 RD1730 1 MD@ 2 10K_0402_5% TEN_UD2 N9 E1 1 1 2.7_0402_1% DDRA_MA12 RD1727 1 MD@ 2 1/20W_36_1%_0201
    TEN VSS1 TEN VSS1 MD@ CD1710

    .047U_0402_16V7K
    K1 K1 MD@ DDRA_MA13 RD1728 1 MD@ 2 1/20W_36_1%_0201
    VSS2 MD@1 1 VSS2 .1U_0402_10V6-K 1

    1
    CPU_DRAMRST# P1 N1 CD1706 CPU_DRAMRST# P1 N1 DDRA_MA14_WE# RD1731 1 MD@ 2 1/20W_36_1%_0201
    1

    CD1709
    6,18 CPU_DRAMRST# RESET_N VSS3 T1 .1U_0402_10V6-K 2 2 RESET_N VSS3 T1 2 2 DDRA_MA15_CAS# 1 2
    VSS4 VSS4 2 2 @ CD1704 RD1706 CD1703 RD1732 MD@ 1/20W_36_1%_0201
    F1 B2 F1 B2 .1U_0402_10V6-K DDRA_MA16_RAS# 1 2

    CD1705

    CD1707

    CD1708

    CD1711

    CD1712
    0.022U_16V_K_X7R_0402 1.8K_0402_1% RD1733 MD@ 1/20W_36_1%_0201
    H1 VSSQ1 VSS5 G8 2 2 @ H1 VSSQ1 VSS5 G8 MD@ 2 MD@
    2 @

    1
    A2 VSSQ2 VSS6 K9 A2 VSSQ2 VSS6 K9 DDRA_BG0 RD1734 1 MD@ 2 1/20W_36_1%_0201

    2
    D2 VSSQ3 VSS8 D2 VSSQ3 VSS8 RD1707 DDRA_BG1_R RD1816 1 DDP@ 2 1/20W_36_1%_0201
    E3 VSSQ4 T7 1 DDP@ 2 E3 VSSQ4 T7 1 DDP@ 2 24.9_0402_1% DDRA_BS0# RD1735 1 MD@ 2 1/20W_36_1%_0201
    A8 VSSQ5 VSS7 R10170 0_0402_5% A8 VSSQ5 VSS7 R10171 0_0402_5% MD@ DDRA_BS1# RD1736 1 MD@ 2 1/20W_36_1%_0201
    D8 VSSQ6 D8 VSSQ6

    2
    C E8 VSSQ7 M9 DDRA_BG1_R E8 VSSQ7 M9 DDRA_BG1_R DDRA_ACT# RD1737 1 MD@ 2 1/20W_36_1%_0201 C
    C9 VSSQ8 VSS9 C9 VSSQ8 VSS9 DDRA_PAR RD1738 1 MD@ 2 1/20W_36_1%_0201
    H9 VSSQ9 E9 UD1_DDRA_UZQ H9 VSSQ9 E9 UD2_DDRA_UZQ
    VSSQ10 VSS10 F9 VSSQ10 VSS10 F9
    ZQ ZQ
    1

    1
    RD1739 RD1740
    K4AAG165WA-BCWE_FBGA96 240_0402_1% K4AAG165WA-BCWE_FBGA96 240_0402_1%
    @ MD@ @ MD@
    2

    2
    +1.2V (1uF_0402_6.3V) *16
    Place 4 near each DRAM
    UD3
    UD4
    DDRA_MA0 P3 G2 DDRA_DQ43

    MD_N3T@

    MD_N3T@

    MD_N3T@
    DDRA_MA1 A0 DQL0 DDRA_DQ41 DDRA_MA0 DDRA_DQ63

    @
    P7 F7 P3 G2

    MD_N3T@

    MD_N3T@

    MD_N3T@

    MD_N3T@

    MD_N3T@

    MD_N3T@

    MD_N3T@

    MD_N3T@

    MD_N3T@
    DDRA_MA2 R3 A1 DQL1 H3 DDRA_DQ42 DDRA_MA1 P7 A0 DQL0 F7 DDRA_DQ60

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    4.3U_0402_4V6-M

    4.3U_0402_4V6-M

    4.3U_0402_4V6-M
    DDRA_MA3 A2 DQL2 DDRA_DQ45 DDRA_MA2 A1 DQL1 DDRA_DQ58 CD1840 CD1841 CD1842
    N7 H7 R3 H3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
    A3 DQL3 A2 DQL2

    3
    DDRA_MA4 N3 H2 DDRA_DQ46 DDRA_MA3 N7 H7 DDRA_DQ56
    Byte 5

    MD_3T@

    MD_3T@
    DDRA_MA5 A4 DQL4 DDRA_DQ40 DDRA_MA4 A3 DQL3 DDRA_DQ62

    MD_3T@
    P8 H8 N3 H2
    DDRA_MA6 P2 A5 DQL5 J3 DDRA_DQ47 DDRA_MA5 P8 A4 DQL4 H8 DDRA_DQ61 Byte 7

    4
    DDRA_MA7 R8 A6 DQL6 J7 DDRA_DQ44 DDRA_MA6 P2 A5 DQL5 J3 DDRA_DQ59 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
    DDRA_MA8 R2 A7 DQL7 A3 DDRA_DQ39 DDRA_MA7 R8 A6 DQL6 J7 DDRA_DQ57

    CD1713

    CD1714

    CD1715

    CD1716

    CD1717

    CD1718

    CD1719

    CD1720

    CD1721

    CD1722

    CD1723

    CD1724

    CD1725

    CD1726

    CD1727

    CD1728
    DDRA_MA9 R7 A8 DQU0 B8 DDRA_DQ36 DDRA_MA8 R2 A7 DQL7 A3 DDRA_DQ50
    DDRA_MA10 M3 A9 DQU1 C3 DDRA_DQ35 DDRA_MA9 R7 A8 DQU0 B8 DDRA_DQ49
    DDRA_MA11 T2 A10/AP DQU2 C7 DDRA_DQ37 DDRA_MA10 M3 A9 DQU1 C3 DDRA_DQ54
    DDRA_MA12 M7 A11 DQU3 C2 DDRA_DQ38 Byte 4 DDRA_MA11 T2 A10/AP DQU2 C7 DDRA_DQ48
    DDRA_MA13 T8 A12/BC_N DQU4 C8 DDRA_DQ32 DDRA_MA12 M7 A11 DQU3 C2 DDRA_DQ51 Byte 6 +1.2V
    (1OuF_0603_6.3V) *5
    A13 DQU5 D3 DDRA_DQ34 DDRA_MA13 T8 A12/BC_N DQU4 C8 DDRA_DQ53
    DDRA_MA14_WE# L2 DQU6 D7 DDRA_DQ33 A13 DQU5 D3 DDRA_DQ55 Place around the DRAMs
    DDRA_MA15_CAS# M8 WE_N/A14 DQU7 DDRA_MA14_WE# L2 DQU6 D7 DDRA_DQ52
    DDRA_MA16_RAS# CAS_N/A15 +1.2V DDRA_MA15_CAS# WE_N/A14 DQU7

    MD@

    MD@

    MD@

    MD@
    B L8 M8 B
    RAS_N/A16 D1 DDRA_MA16_RAS# L8 CAS_N/A15 +1.2V

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M
    DDRA_CLK0# K8 VDD1 J1 RAS_N/A16 D1
    CK_C VDD2 VDD1 1 1 1 1 1 1 1
    DDRA_CLK0 K7 L1 DDRA_CLK0# K8 J1 CD1734 CD1735
    CK_T VDD3 R1 DDRA_CLK0 K7 CK_C VDD2 L1 22P_0402_50V8-J 22P_0402_50V8-J
    DDRA_CKE0 K2 VDD4 B3 CK_T VDD3 R1 @ @
    CKE VDD5 G7 DDRA_CKE0 K2 VDD4 B3 2 2 2 2 2 2 2
    DDRA_DQS#5 F3 VDD6 B9 CKE VDD5 G7

    CD1729

    CD1730

    CD1731

    CD1732

    CD1733
    DDRA_DQS5 G3 DQSL_C VDD7 J9 DDRA_DQS#7 F3 VDD6 B9
    DDRA_DQS#4 A7 DQSL_T VDD8 L9 DDRA_DQS7 G3 DQSL_C VDD7 J9
    +1.2V DDRA_DQS4 B7 DQSU_C VDD9 T9 DDRA_DQS#6 A7 DQSL_T VDD8 L9
    DQSU_T VDD10 +1.2V DDRA_DQS6 B7 DQSU_C VDD9 T9
    RD1742 1 2 0_0402_5% DDRA_DM4 E2 A1 DQSU_T VDD10
    RD1743 1 2 0_0402_5% DDRA_DM5 E7 NF/UDM_N/UDBI_N VDDQ1 C1 RD1744 1 2 0_0402_5% DDRA_DM6 E2 A1
    NF/LDM_N/LDBI_N VDDQ2 G1 RD1745 1 2 0_0402_5% DDRA_DM7 E7 NF/UDM_N/UDBI_N VDDQ1 C1 +0.6VS
    DDRA_BS0# VDDQ3 NF/LDM_N/LDBI_N VDDQ2 (1uF_0402_6.3V) *8 (1OuF_0603_6.3V) *2
    N2 F2 G1 Place 2 near each DRAM Place around the DRAMs
    DDRA_BS1# N8 BA0 VDDQ4 J2 DDRA_BS0# N2 VDDQ3 F2
    BA1 VDDQ5 F8 DDRA_BS1# N8 BA0 VDDQ4 J2
    DDRA_ACT# VDDQ6 BA1 VDDQ5

    MD@
    L3 J8 F8

    MD_N3T@

    MD_N3T@

    MD_N3T@

    MD_N3T@

    MD_N3T@

    MD_N3T@

    MD_N3T@

    MD_N3T@
    DDRA_CS0# L7 ACT_N VDDQ7 A9 DDRA_ACT# L3 VDDQ6 J8

    10U_0603_6.3V6M

    10U_0603_6.3V6M
    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    4.3U_0402_4V6-M

    4.3U_0402_4V6-M
    DDRA_ALERT# CS_N VDDQ8 DDRA_CS0# ACT_N VDDQ7 CD1843 CD1844
    P9 D9 L7 A9 1 1 1 1 1 1 1 1 1 1 1 1

    3
    ALERT_N VDDQ9 G9 +2.5V_DDR DDRA_ALERT# P9 CS_N VDDQ8 D9 CD1759 CD1760
    DDRA_BG0 VDDQ10 ALERT_N VDDQ9 +2.5V_DDR

    MD_3T@

    MD_3T@
    M2 G9 22P_0402_50V8-J 22P_0402_50V8-J
    BG0 B1 DDRA_BG0 M2 VDDQ10 @ @

    4
    DDRA_ODT0 K3 VPP1 R9 BG0 B1 2 2 2 2 2 2 2 2 2 2 2 2
    ODT VPP2 DDRA_ODT0 VPP1
    MD@

    MD@

    K3 R9

    CD1749

    CD1750

    CD1751

    CD1752

    CD1753

    CD1754

    CD1755

    CD1756

    CD1757

    CD1758
    DDRA_PAR +VREF_CA_MD ODT VPP2

    MD@

    @
    T3 M1
    1U_0402_6.3V6K

    1U_0402_6.3V6K

    PAR VREFCA DDRA_PAR T3 M1 +VREF_CA_MD

    1U_0402_6.3V6K

    1U_0402_6.3V6K
    1 1 PAR VREFCA
    RD1746 1 MD@ 2 10K_0402_5% TEN_UD3 N9 E1 1 1
    TEN VSS1
    .047U_0402_16V7K

    K1 1 1 RD1747 1 MD@ 2 10K_0402_5% TEN_UD4 N9 E1


    VSS2 TEN VSS1

    .047U_0402_16V7K
    CPU_DRAMRST# P1 N1 MD@ CD1739 K1
    RESET_N VSS3 VSS2 1 1
    T1 .1U_0402_10V6-K 2 2 CPU_DRAMRST# P1 N1 MD@ CD1748
    F1 VSS4 B2 RESET_N VSS3 T1 .1U_0402_10V6-K 2 2 (1OuF_0603_6.3V) *3
    CD1738

    CD1740

    CD1741

    H1 VSSQ1 VSS5 G8 2 2 @ F1 VSS4 B2 +2.5V_DDR Place around the DRAMs

    CD1747

    CD1742

    CD1744
    A2 VSSQ2 VSS6 K9 H1 VSSQ1 VSS5 G8 2 2 @
    D2 VSSQ3 VSS8 A2 VSSQ2 VSS6 K9
    VSSQ4 1 DDP@ 2 VSSQ3 VSS8

    MD@

    MD@

    MD@

    MD@
    E3 T7 D2
    A8 VSSQ5 VSS7 R10172 0_0402_5% E3 VSSQ4 T7 1 DDP@ 2

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M
    D8 VSSQ6 A8 VSSQ5 VSS7 R10173 0_0402_5%
    VSSQ7 VSSQ6 1 1 1 1 1 1
    E8 M9 DDRA_BG1_R D8 CD1736 CD1737
    C9 VSSQ8 VSS9 E8 VSSQ7 M9 DDRA_BG1_R 22P_0402_50V8-J 22P_0402_50V8-J
    H9 VSSQ9 E9 UD3_DDRA_UZQ C9 VSSQ8 VSS9 @ @
    VSSQ10 VSS10 F9 H9 VSSQ9 E9 UD4_DDRA_UZQ 2 2 2 2 2 2
    ZQ VSSQ10 VSS10 F9

    CD1743

    CD1745

    CD1746

    CD1839
    ZQ
    1

    A A
    RD1748
    K4AAG165WA-BCWE_FBGA96 240_0402_1% RD1749
    @ MD@ K4AAG165WA-BCWE_FBGA96 240_0402_1%
    @ MD@
    2

    Security Classification LC Future Center Secret Data Title

    Issued Date 2017/06/24 Deciphered Date 2018/06/23 DDR4 Memory Down


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    Size
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS441/FS540
    Date: Wednesday, October 16, 2019 Sheet 17 of 61
    5 4 3 2 1
    5 4 3 2 1

    +1.2V

    DDR4 SO-DIMM

    1
    RD1801
    +1.2V +1.2V +1.2V +1.2V 240_0402_1%
    JDDR1B
    +1.2V +1.2V +1.2V +1.2V @
    JDDR1A

    2
    DDRB_MA3 131 132 DDRB_MA2
    1 2 6 DDRB_MA3 DDRB_MA1 133 A3 A2 134 DDRB_EVENT# DDRB_MA2 6
    DDRB_DQ17 3 VSS_1 VSS_2 4 DDRB_DQ22 6 DDRB_MA1 135 A1 EVENT_n 136
    5 DQ5 DQ4 6 DDRB_CLK0 137 VDD_9 VDD_10 138 DDRB_CLK1
    DDRB_DQ16 7 VSS_3 VSS_4 8 DDRB_DQ23 6 DDRB_CLK0 DDRB_CLK0# 139 CK0_t CK1_t 140 DDRB_CLK1# DDRB_CLK1 6
    9 DQ1 DQ0 10 DDRB_DQ[0..63] 6 DDRB_CLK0# 141 CK0_c CK1_c 142 DDRB_CLK1# 6
    DDRB_DQS#2 11 VSS_5 VSS_6 12 DDRB_DQ[0..63] 5,6 DDRB_PAR 143 VDD_11 VDD_12 144 DDRB_MA0
    DDRB_DQS2 13 DQS0_C DM0_n/DBIO_n/NC 14 DDRB_DQS#[0..7] 6 DDRB_PAR Parity A0 DDRB_MA0 6
    15 DQS0_t VSS_7 16 DDRB_DQ18 DDRB_DQS#[0..7] 5,6
    D D
    DDRB_DQ20 17 VSS_8 DQ6 18 DDRB_DQS[0..7] DDRB_BS1# 145 146 DDRB_MA10
    19 DQ7 VSS_9 20 DDRB_DQ19 DDRB_DQS[0..7] 5,6 6 DDRB_BS1# 147 BA1 A10/AP 148 DDRB_MA10 6
    DDRB_DQ21 21 VSS_10 DQ2 22 DDRB_CS0# 149 VDD_13 VDD_14 150 DDRB_BS0#
    23 DQ3 VSS_11 24 DDRB_DQ0 6 DDRB_CS0# DDRB_MA14_WE# 151 CS0_n BA0 152 DDRB_MA16_RAS# DDRB_BS0# 6
    DDRB_DQ5 25 VSS_12 DQ12 26 6 DDRB_MA14_WE# 153 WE_n/A14 RAS_n/A16 154 DDRB_MA16_RAS# 6
    27 DQ13 VSS_13 28 DDRB_DQ3 DDRB_ODT0 155 VDD_15 VDD_16 156 DDRB_MA15_CAS#
    DDRB_DQ4 29 VSS_14 DQ8 30 6 DDRB_ODT0 DDRB_CS1# 157 ODT0 CAS_n/A15 158 DDRB_MA13 DDRB_MA15_CAS# 6
    31 DQ9 VSS_15 32 DDRB_DQS#0 6 DDRB_CS1# 159 CS1_n A13 160 DDRB_MA13 6
    33 VSS_16 DQS1_c 34 DDRB_DQS0 DDRB_ODT1 161 VDD_17 VDD_18 162
    35 DM1_n/DBl1_n/NC DQS1_t 36 6 DDRB_ODT1 163 ODT1 C0/CS2_n/NC 164 +VREF_CA_DIMM
    DDRB_DQ1 37 VSS_17 VSS_18 38 DDRB_DQ6 165 VDD_19 VREFCA 166 DDRB_SA2
    DQ15 DQ14 C1/CS3_n/NC SA2

    2.2U_0402_6.3V6M
    39 40 167 168

    .1U_0402_10V6-K
    DDRB_DQ2 41 VSS_19 VSS_20 42 DDRB_DQ7 DDRB_DQ33 169 VSS_53 VSS_54 170 DDRB_DQ35 @1
    DQ10 DQ11 DQ37 DQ36 1

    CD1801
    43 44 171 172
    DDRB_DQ8 45 VSS_21 VSS_22 46 DDRB_DQ9 DDRB_DQ37 173 VSS_55 VSS_56 174 DDRB_DQ32
    47 DQ21 DQ20 48 175 DQ33 DQ32 176
    DDRB_DQ11 49 VSS_23 VSS_24 50 DDRB_DQ13 DDRB_DQS#4 177 VSS_57 VSS_58 178 2 2
    DQ17 DQ16 DDRB_DQS4 DQS4_c DM4_n/DBl4_n/NC

    CD1802
    51 52 179 180
    DDRB_DQS#1 53 VSS_25 VSS_26 54 181 DQS4_t VSS_59 182 DDRB_DQ34
    DDRB_DQS1 55 DQS2_c DM2_n/DBl2_n/NC 56 DDRB_DQ39 183 VSS_60 DQ39 184
    57 DQS2_t VSS_27 58 DDRB_DQ15 185 DQ38 VSS_61 186 DDRB_DQ36
    DDRB_DQ14 59 VSS_28 DQ22 60 DDRB_DQ38 187 VSS_62 DQ35 188
    61 DQ23 VSS_29 62 DDRB_DQ12 189 DQ34 VSS_63 190 DDRB_DQ45
    DDRB_DQ10 63 VSS_30 DQ18 64 DDRB_DQ41 191 VSS_64 DQ45 192
    65 DQ19 VSS_31 66 DDRB_DQ25 193 DQ44 VSS_65 194 DDRB_DQ40
    DDRB_DQ24 67 VSS_32 DQ28 68 DDRB_DQ44 195 VSS_66 DQ41 196
    69 DQ29 VSS_33 70 DDRB_DQ29 197 DQ40 VSS_67 198 DDRB_DQS#5
    DDRB_DQ28 71 VSS_34 DQ24 72 199 VSS_68 DQS5_c 200 DDRB_DQS5
    73 DQ25 VSS_35 74 DDRB_DQS#3 201 DM5_n/DBl5_n/NC DQS5_t 202
    +1.2V 75 VSS_36 DQS3_c 76 DDRB_DQS3 DDRB_DQ47 203 VSS_69 VSS_70 204 DDRB_DQ43
    77 DM3_n/DBl3_n/NC DQS3_t 78 205 DQ46 DQ47 206
    DDRB_DQ31 79 VSS_37 VSS_38 80 DDRB_DQ26 DDRB_DQ46 207 VSS_71 VSS_72 208 DDRB_DQ42
    81 DQ30 DQ31 82 209 DQ42 DQ43 210
    VSS_39 VSS_40 VSS_73 VSS_74
    1

    DDRB_DQ30 83 84 DDRB_DQ27 DDRB_DQ53 211 212 DDRB_DQ48


    85 DQ26 DQ27 86 213 DQ52 DQ53 214
    RD1802 RD1803 87 VSS_41 VSS_42 88 DDRB_DQ52 215 VSS_75 VSS_76 216 DDRB_DQ49
    240_0402_1% 240_0402_1% 89 CB5/NC CB4/NC 90 217 DQ49 DQ48 218
    91 VSS_43 VSS_44 92 DDRB_DQS#6 219 VSS_77 VSS_78 220
    2

    93 CB1/NC CB0/NC 94 DDRB_DQS6 221 DQS6_c DM6_n/DBl6_n/NC 222


    DDRB_DQS#8 95 VSS_45 VSS_46 96 223 DQS6_t VSS_79 224 DDRB_DQ55
    C DDRB_DQS8 97 DQS8_c DM8_n/DBI8_n/NC 98 DDRB_DQ54 225 VSS_80 DQ54 226 C
    99 DQS8_t VSS_47 100 227 DQ55 VSS_81 228 DDRB_DQ50
    101 VSS_48 CB6/NC 102 DDRB_DQ51 229 VSS_82 DQ50 230
    103 CB2/NC VSS_49 104 231 DQ51 VSS_83 232 DDRB_DQ56
    105 VSS_50 CB7/NC 106 DDRB_DQ60 233 VSS_84 DQ60 234
    107 CB3/NC VSS_51 108 CPU_DRAMRST# 235 DQ61 VSS_85 236 DDRB_DQ61
    DDRB_CKE0 109 VSS_52 RESET_n 110 DDRB_CKE1 CPU_DRAMRST# 6,17 DDRB_DQ57 237 VSS_86 DQ57 238

    .1U_0402_10V6-K
    6 DDRB_CKE0 111 CKE0 CKE1 112 DDRB_CKE1 6 @ 239 DQ56 VSS_87 240 DDRB_DQS#7
    VDD_1 VDD_2 1 VSS_88 DQS7_c

    CD1803
    DDRB_BG1 113 114 DDRB_ACT# 241 242 DDRB_DQS7
    6 DDRB_BG1 DDRB_BG0 115 BG1 ACT_n 116 DDRB_ALERT# DDRB_ACT# 6 243 DM7_n/DBl7_n/NC DQS7_t 244
    6 DDRB_BG0 117 BG0 ALERT_n 118 DDRB_ALERT# 6 DDRB_DQ59 245 VSS_89 VSS_90 246 DDRB_DQ62
    DDRB_MA12 119 VDD_3 VDD_4 120 DDRB_MA11 2 247 DQ62 DQ63 248
    6 DDRB_MA12 DDRB_MA9 121 A12 A11 122 DDRB_MA7 DDRB_MA11 6 DDRB_DQ58 249 VSS_91 VSS_92 250 DDRB_DQ63
    6 DDRB_MA9 123 A9 A7 124 DDRB_MA7 6 251 DQ58 DQ59 252
    DDRB_MA8 125 VDD_5 VDD_6 126 DDRB_MA5 SMB_CLK_S3 253 VSS_93 VSS_94 254 SMB_DATA_S3
    6 DDRB_MA8 DDRB_MA6 127 A8 A5 128 DDRB_MA4 DDRB_MA5 6 7 SMB_CLK_S3 1 2 +VDD_SPD 255 SCL SDA 256 DDRB_SA0 SMB_DATA_S3 7
    6 DDRB_MA6 A6 A4 DDRB_MA4 6 +3VS VDDSPD SA0
    129 130 257 258

    .1U_0402_10V6-K
    2.2U_0402_6.3V6M
    VDD_7 VDD_8 RD1804 VPP_1 VTT DDRB_SA1 +0.6VS
    1 1 259 260
    0_0603_5% VPP_2 SA1

    CD1805
    CD1804
    261 262
    GND_1 GND_2
    ARGOS_D4AR0-26001-1P40 2 2
    ME@ ARGOS_D4AR0-26001-1P40
    ME@

    RD1805
    1 2 +VPP
    +2.5V_DDR
    0_0603_5%
    +1.2V
    .1U_0402_10V6-K

    1
    CD1806

    Note:
    VREF trace width:20 mils at least
    1

    2 +1.2V
    RD1806 Spacing:20mils to other signal/planes
    1K_0402_1% Place near DIMM scoket
    B B
    2

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M
    RD1807
    +VREF_CA_DIMM

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K
    1 2
    5 DDR_SB_VREFCA
    2_0402_5%
    .1U_0402_10V6-K

    1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
    1 1 @ @ @ @
    CD1815
    1

    CD1817

    CD1818

    CD1819

    CD1820

    CD1816
    0.022U_16V_K_X7R_0402 RD1808 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
    2 2
    CD1821

    CD1822

    CD1823

    CD1824

    CD1825

    CD1826

    CD1827

    CD1828

    CD1829

    CD1830

    CD1831

    CD1832
    1K_0402_1%
    1

    RD1809
    2

    24.9_0402_1%
    2

    Layout Note:
    Place near DIMM

    +0.6VS +2.5V_DDR +1.2V

    @
    33P_0402_50V8J

    33P_0402_50V8J
    4.7U_0603_6.3V6M

    4.7U_0603_6.3V6M

    0.1U_0402_10V7K

    0.1U_0402_10V7K
    SPD address setting

    @
    1U_0402_6.3V6K

    1U_0402_6.3V6K

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1 1 1 1 1 1
    @

    @
    1 1 @1 1 1 1 1 1
    +3VS +3VS @
    +3VS @
    2 2 2 2 2 2

    CD1835

    CD1836
    2 2 2 2 2 2 2 2
    CD1833

    CD1834

    CD1837

    CD1838
    1

    CD1807

    CD1808

    CD1809

    CD1810

    CD1811

    CD1812

    CD1813

    CD1814

    RD1810 RD1811 RD1812


    0_0402_5% 0_0402_5% 0_0402_5%
    @ @
    For EMC Near JDDRL1
    2

    1 2

    DDRB_SA0 DDRB_SA1 DDRB_SA2


    1

    A A
    RD1814
    RD1813 0_0402_5% RD1815
    0_0402_5% 0_0402_5%
    2
    2

    SPD Address = 010


    Security Classification LC Future Center Secret Data Title
    Issued Date 2015/08/20 Deciphered Date 2016/08/20 DDR4 SO-DIMM
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    Size Document Number
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS441/FS540
    Date: Wednesday, October 16, 2019 Sheet 18 of 61
    5 4 3 2 1
    5 4 3 2 1

    N16x GPIO

    GPIO I/O ACTIVE Function Description Performance Mode P0 TDP and EDP-Continuous current (GDDR5)
    GPIO0 OUT - GPU Core VDD PWM control signal
    FBVDDQ Other
    Min FBVDD (GPU+Mem) (1.05V)
    GPIO1 OUT N/A FB Enable for GC6 2.0 GPU Mem Core Clk NVVDD (1.35V) (1.35V) (6) (3.3V)
    Products (W) (W) (MHz) (V) (A) (W) (A) (W) (A) (W) (mA) (W) (mA) (W)
    D GPIO2 OUT N/A D

    N16S-GMR 16 1.6 849 TBD 19 TBD 2 TBD 4.2 TBD 800 TBD 60 TBD
    GPIO3 OUT N/A
    N16S-GTR 18 1.7 967 26.5 2 4.2 800 60
    GPIO4 OUT N/A

    GPIO5 OUT N/A GPU power sequencing---3V3_MAIN_EN

    GPIO6 IN - GPU wake signal for GC6 2.0

    GPIO7 OUT N/A

    GPIO8 I/O - System side PCIe reset Monitor

    GPIO9 I/O N/A 2.2K Pull-up

    GPIO10 OUT FBVREF_ALTV for GDDR5

    GPIO11 OUT - N16x Multi-level Straps


    GPIO12 IN AC Power Detect Input (10K pull High)
    Physical Logical Logical Logical Logical
    GPIO13 OUT - Phase Shedding Strapping pin Power Rail Strapping Bit3 Strapping Bit2 Strapping Bit1 Strapping Bit0
    ROM_SCLK +3VGS SOR3_EXPOSED SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED
    GPIO14 IN N/A
    ROM_SI +3VGS RAM_CFG[3] RAM_CFG[2] RAM_CFG[1] RAM_CFG[0]
    C C
    GPIO15 IN N/A ROM_SO +3VGS DEVID_SEL PCIE_CFG SMB_ALT_ADDR VGA_DEVICE
    STRAP0 +3VGS Reserved(keep pull-up and pull-down footprint and stuff 50Kohm pull-up)
    GPIO16 N/A
    STRAP1 +3VGS
    GPIO17 IN N/A STRAP2 +3VGS
    Reserved(keep pull-up and pull-down footprint and not stuff by default)
    STRAP3 +3VGS
    GPIO18 IN N/A
    STRAP4 +3VGS
    GPIO19 IN N/A

    GPIO20 N/A

    GPIO21 OUT GPU PCIe self-reset control

    OVERT OUT Active Low Thermal Catastrophic Over Temperature

    B B

    A A

    Security Classification LC Future Center Secret Data Title

    Issued Date 2015/08/20 Deciphered Date 2016/08/20 VGA Notes List


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS441/FS540
    Date: Wednesday, October 16, 2019 Sheet 19 of 61
    5 4 3 2 1
    5 4 3 2 1

    +3.3V_1.8V_AON +3V_1.8VGS +3.3V_1.8V_AON

    2
    RV2005 RV2006
    0_0402_5% 0_0402_5%

    2
    @ OPT@ +1.0VGS
    RV2007
    10K_0402_5% UV1A ? COMMON INS35853665

    1
    OPT@ 1/14 PCI_EXPRESS
    1
    CV2027 Under Near GPU and PS

    1
    D D
    0.1u_0201_10V6K

    OPTN17@

    OPTN17@

    OPTN17@

    OPTN17@

    OPTN17@
    @

    4.7U_0603_6.3V6M

    4.7U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    22U_0603_6.3V6-M
    4.7U_0402_6.3V6M
    2

    OPT@

    OPT@
    2

    1U_0402_6.3V6K
    AA22 PEX_DVDD
    PLT_RST_VGA# AC7 PEX_DVDD_1 AB23 1 1 1 1 2 2 1
    26 PLT_RST_VGA# PEX_DVDD_2 N16:+1.05VGS(recommend)
    OPT@ QV2001 AC24
    1 3 CLK_REQ_GPU# AC6 PEX_RST_N PEX_DVDD_3 AD25 +1.0VGS(Used)

    CV2011

    CV2002

    CV2003

    CV2012

    CV2004
    10 GPU_CLKREQ#

    CV2001

    CV2010
    PEX_CLKREQ_N PEX_DVDD_4 AE26 N17:+1.0VGS
    PEX_DVDD_5 2 2 2 2 1 1 2
    CLK_PCIE_GPU AE8 AE27
    10 CLK_PCIE_GPU CLK_PCIE_GPU# PEX_REFCLK PEX_DVDD_6
    LSI1012XT1G_SC-89-3 AD8
    10 CLK_PCIE_GPU# PEX_REFCLK_N
    RV2009 1 @ 2 0_0402_5%

    2
    PCIE_CRX_GTX_P5 OPT@ CV2005 1 2 0.22U_0201_6.3V6-K PCIE_CRX_C_GTX_P5 AC9 PEX_HVDD +3V_1.8VGS
    RV2008 PCIE_CRX_GTX_N5 OPT@ CV2013 1 2 0.22U_0201_6.3V6-K PCIE_CRX_C_GTX_N5 AB9 PEX_TX0
    10K_0402_5% PEX_TX0_N
    @ PCIE_CTX_C_GRX_P5 AG6 2000mA Under GPU Near GPU GPU and PS OPTN17@
    PCIE_CTX_C_GRX_N5 AG7 PEX_RX0 AA10 (below 150mils) PEX_HVDD 2 1 0_0805_5%

    1
    PEX_RX0_N PEX_HVDD_1

    OPT@

    OPT@
    AA12

    OPTN17@

    OPTN17@
    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    22U_0603_6.3V6-M
    RV2001

    CV2018 OPTN17@
    PCIE_CRX_GTX_P6 PCIE_CRX_C_GTX_P6 PEX_HVDD_2 +1.0VGS

    OPT@

    4.7U_0603_6.3V6M

    4.7U_0603_6.3V6M
    OPT@ CV2006 1 2 0.22U_0201_6.3V6-K AB10 AA13

    33P_0402_50V8J
    OPT@
    PCIE_CRX_GTX_N6 OPT@ CV2007 1 2 0.22U_0201_6.3V6-K PCIE_CRX_C_GTX_N6 AC10 PEX_TX1 PEX_HVDD_3 AA16 OPTN16@
    1 1 1 1 2 2 1 1

    OPT_RF@
    PEX_TX1_N PEX_HVDD_4 1 1

    CV2022
    AA18 2 1 0_0805_5%
    PCIE_CTX_C_GRX_P6 AF7 PEX_HVDD_5 AA19
    PCIE_CTX_C_GRX_N6 AE7 PEX_RX1 PEX_HVDD_6 AA20 RV2002

    CV2014

    CV2008

    CV2015

    CV2016

    CV2019

    CV2020

    CV2021
    CV2017
    PEX_RX1_N PEX_HVDD_7 AA21 2 2 2 2 1 1 2 2
    2 2
    PCIE_CRX_GTX_P7 OPT@ CV2009 1 2 0.22U_0201_6.3V6-K PCIE_CRX_C_GTX_P7 AD11 PEX_HVDD_8 AB22 PEX_HVDD
    PCIE_CRX_GTX_N7 OPT@ CV2023 1 2 0.22U_0201_6.3V6-K PCIE_CRX_C_GTX_N7 AC11 PEX_TX2 PEX_HVDD_9 AC23 N16:+1.05VGS(recommend)
    PEX_TX2_N PEX_HVDD_10 AD24 +1.0VGS(Used)
    PCIE_CTX_C_GRX_P7 AE9 PEX_HVDD_11 AE25
    PEX_RX2 PEX_HVDD_12 N17:+1.8VGS
    PCIE_CTX_C_GRX_N7 AF9 AF26
    PEX_RX2_N PEX_HVDD_13 AF27 For RF
    PCIE_CRX_GTX_P8 OPT@ CV2024 1 2 0.22U_0201_6.3V6-K PCIE_CRX_C_GTX_P8 AC12 PEX_HVDD_14
    PCIE_CRX_GTX_N8 OPT@ CV2025 1 2 0.22U_0201_6.3V6-K PCIE_CRX_C_GTX_N8 AB12 PEX_TX3 Change by Bourne 20170412
    PEX_TX3_N
    PCIE_CTX_C_GRX_P8 AG9
    PCIE_CTX_C_GRX_N8 AG10 PEX_RX3
    PEX_RX3_N
    AB13
    AC13 PEX_TX4
    PEX_TX4_N
    C C
    AF10 +3.3V_1.8V_AON
    9 PCIE_CRX_GTX_N[5..8] PEX_RX4
    AE10
    PEX_RX4_N
    9 PCIE_CRX_GTX_P[5..8]
    AD14 OPTN16@
    AC14 PEX_TX5 AA8 PEX_PLL_HVDD RV2003 1 2 0_0402_5%
    PEX_PLL_HVDD
    9 PCIE_CTX_C_GRX_N[5..8] PEX_TX5_N PEX_PLL_HVDD_1
    PEX_PLL_HVDD_2
    AA9 +3V_1.8VGS N16:+3.3V_AON
    AE12
    9 PCIE_CTX_C_GRX_P[5..8] PEX_RX5 N17:+1.8VGS

    .1U_0402_10V6-K
    AF12 1 OPTN17@
    PEX_RX5_N

    OPT@
    CV2026
    RV2004 1 2 0_0402_5%
    AC15
    AB15 PEX_TX6
    PEX_TX6_N 2 Change by Bourne 20170412
    AG12
    AG13 PEX_RX6
    PEX_RX6_N
    Under GPU
    AB16
    AC16 PEX_TX7 (below 150mils)
    PEX_TX7_N PEX_DVDD/Q Decouling
    AF13
    AE13 PEX_RX7
    PEX_RX7_N
    AD17 MLCC N16 N17 location
    AC17 PEX_TX8
    PEX_TX8_N
    1.0uF 1 1
    AE15
    AF15 PEX_RX8 Under
    PEX_RX8_N 4.7uF 0 1
    AC18
    PEX_TX9 Near
    AB18
    PEX_TX9_N
    4.7uF 1 2
    AG15
    AG16 PEX_RX9 10uF 0 2 Midway
    PEX_RX9_N

    PEX LANES 15 - 4 ARE DEFEATURED


    AB19
    PEX_TX10
    22uF 0 1
    AC19
    PEX_TX10_N
    AF16
    B
    AE16 PEX_RX10 B
    PEX_RX10_N PEX_HVDD/Q Decouling
    AD20
    AC20 PEX_TX11
    PEX_TX11_N
    MLCC N16 N17 location
    AE18
    AF18 PEX_RX11
    PEX_RX11_N 1.0uF 1 4 Under
    AC21
    PEX_TX12 Near
    AB21
    PEX_TX12_N
    4.7uF 1 2
    AG18
    AG19 PEX_RX12 10uF 1 2 Midway
    PEX_RX12_N
    AD23
    PEX_TX13
    22uF 1 1
    AE23
    PEX_TX13_N
    AF19
    AE19 PEX_RX13
    PEX_RX13_N
    AF24
    AE24 PEX_TX14
    PEX_TX14_N
    AE21
    AF21 PEX_RX14
    PEX_RX14_N PEX_PLL_HVDD/Q Decouling
    AG24
    AG25 PEX_TX15
    PEX_TX15_N
    MLCC N16 N17 location
    AG21
    AG22 PEX_RX15
    PEX_RX15_N 0.1uF 1 1 Near
    AF25 PEX_TERMP 2.49K_0402_1% 2 OPT@ 1 RV2010
    PEX_TERMP

    N17S-G1-A1_GB2C-64-595 @
    A A

    Security Classification LC Future Center Secret Data Title

    Issued Date 2015/08/20 Deciphered Date 2016/08/20 GPU_PCIE Interface


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS441/FS540
    Date: Wednesday, October 16, 2019 Sheet 20 of 61
    5 4 3 2 1
    5 4 3 2 1

    UV1B ? COMMON INS35854731


    2/14 FBA
    FBA_D0 E18
    FBA_D1 F18 FBA_D0
    FBA_D2 E16 FBA_D1
    FBA_D3 F17 FBA_D2
    FBA_D4 D20 FBA_D3
    27,28 FBA_D[0..63] FBA_D5 FBA_D4
    D21
    FBA_D6 F20 FBA_D5
    27,28 FBA_CMD[31..0] FBA_D7 E21 FBA_D6
    FBA_D8 E15 FBA_D7
    27,28 FBA_EDC[7..0] FBA_D9 D15 FBA_D8
    FBA_D10 F15 FBA_D9
    D 27,28 FBA_DBI[7..0] FBA_D11 FBA_D10 D
    F13
    FBA_D12 C13 FBA_D11
    FBA_D13 B13 FBA_D12
    FBA_D14 E13 FBA_D13
    FBA_D15 D13 FBA_D14
    FBA_D16 B15 FBA_D15
    FBA_D17 C16 FBA_D16
    FBA_D18 A13 FBA_D17
    FBA_D19 A15 FBA_D18
    FBA_D20 B18 FBA_D19
    FBA_D21 A18 FBA_D20
    FBA_D22 A19 FBA_D21
    FBA_D23 C19 FBA_D22
    FBA_D24 B24 FBA_D23 +1.35VGS
    FBA_D25 C23 FBA_D24
    FBA_D26 A25 FBA_D25
    FBA_D27 A24 FBA_D26
    FBA_D28 A21 FBA_D27
    FBA_D28

    1
    FBA_D29 B21
    FBA_D29

    1
    FBA_D30 C20 RV210
    FBA_D31 C21 FBA_D30 RV209
    FBA_D31 10K_0402_1%
    FBA_D32 R22 OPT@ 10K_0402_1%
    FBA_D33 R24 FBA_D32 C27 FBA_CMD0 OPT@

    2
    FBA_D34 T22 FBA_D33 FBA_CMD0 C26 FBA_CMD1

    2
    FBA_D35 R23 FBA_D34 FBA_CMD1 E24 FBA_CMD2 FBA_CMD14
    FBA_D36 N25 FBA_D35 FBA_CMD2 F24 FBA_CMD3
    FBA_D37 N26 FBA_D36 FBA_CMD3 D27 FBA_CMD4 FBA_CMD30
    FBA_D38 N23 FBA_D37 FBA_CMD4 D26 FBA_CMD5
    FBA_D39 N24 FBA_D38 FBA_CMD5 F25 FBA_CMD6
    FBA_D40 V23 FBA_D39 FBA_CMD6 F26 FBA_CMD7
    FBA_D41 V22 FBA_D40 FBA_CMD7 F23 FBA_CMD8 FBA_CMD13
    FBA_D42 T23 FBA_D41 FBA_CMD8 G22 FBA_CMD9
    FBA_D43 U22 FBA_D42 FBA_CMD9 G23 FBA_CMD10
    FBA_D44 Y24 FBA_D43 FBA_CMD10 G24 FBA_CMD11 FBA_CMD29
    FBA_D45 AA24 FBA_D44 FBA_CMD11 F27 FBA_CMD12
    FBA_D46 Y22 FBA_D45 FBA_CMD12 G25 FBA_CMD13
    FBA_D46 FBA_CMD13

    1
    FBA_D47 AA23 G27 FBA_CMD14
    FBA_D48 AD27 FBA_D47 FBA_CMD14 G26 FBA_CMD15 RV212 RV211
    C C
    FBA_D49 AB25 FBA_D48 FBA_CMD15 M24 FBA_CMD16
    FBA_D49 FBA_CMD16 10K_0402_1% 10K_0402_1%
    FBA_D50 AD26 M23 FBA_CMD17 OPT@ OPT@
    FBA_D51 AC25 FBA_D50 FBA_CMD17 K24 FBA_CMD18

    2
    FBA_D52 AA27 FBA_D51 FBA_CMD18 K23 FBA_CMD19
    FBA_D53 AA26 FBA_D52 FBA_CMD19 M27 FBA_CMD20
    FBA_D54 W26 FBA_D53 FBA_CMD20 M26 FBA_CMD21
    FBA_D55 Y25 FBA_D54 FBA_CMD21 M25 FBA_CMD22
    FBA_D56 R26 FBA_D55 FBA_CMD22 K26 FBA_CMD23
    FBA_D57 T25 FBA_D56 FBA_CMD23 K22 FBA_CMD24
    FBA_D58 N27 FBA_D57 FBA_CMD24 J23 FBA_CMD25
    FBA_D59 R27 FBA_D58 FBA_CMD25 J25 FBA_CMD26
    FBA_D60 V26 FBA_D59 FBA_CMD26 J24 FBA_CMD27
    FBA_D61 V27 FBA_D60 FBA_CMD27 K27 FBA_CMD28
    FBA_D62 W27 FBA_D61 FBA_CMD28 K25 FBA_CMD29
    FBA_D63 W25 FBA_D62 FBA_CMD29 J27 FBA_CMD30 +1.35VGS
    FBA_D63 FBA_CMD30 J26 FBA_CMD31
    FBA_CMD31 B19
    FBA_DBI0 D19 FBA_CMD32 F22 RV2105 2 @ 1 60.4_0402_1%
    FBA_DBI1 D14 FBA_DQM0 FBA_CMD34 J22 RV2106 2 @ 1 60.4_0402_1%
    FBA_DBI2 C17 FBA_DQM1 FBA_CMD35
    FBA_DBI3 C22 FBA_DQM2
    FBA_DBI4 P24 FBA_DQM3
    FBA_DBI5 W24 FBA_DQM4
    FBA_DBI6 AA25 FBA_DQM5
    FBA_DBI7 U25 FBA_DQM6
    FBA_DQM7

    FBA_EDC0 E19
    FBA_EDC1 C15 FBA_DQS_WP0
    FBA_EDC2 B16 FBA_DQS_WP1 D24 FBA_CLK0
    FBA_EDC3 B22 FBA_DQS_WP2 FBA_CLK0 D25 FBA_CLK0# FBA_CLK0 27
    FBA_EDC4 R25 FBA_DQS_WP3 FBA_CLK0_N FBA_CLK0# 27
    N22 FBA_CLK1
    FBA_EDC5 W23 FBA_DQS_WP4 FBA_CLK1 FBA_CLK1 28
    M22 FBA_CLK1#
    FBA_EDC6 AB26 FBA_DQS_WP5 FBA_CLK1_N FBA_CLK1# 28
    FBA_EDC7 T26 FBA_DQS_WP6
    FBA_DQS_WP7

    B FBA_WCLK01 B
    F19 D18
    C14 FBA_DQS_RN0 FBA_WCK01 C18 FBA_WCLK01# FBA_WCLK01 27
    FBA_DQS_RN1 FBA_WCK01_N FBA_WCLK23 FBA_WCLK01# 27
    A16 D17
    A22 FBA_DQS_RN2 FBA_WCK23 D16 FBA_WCLK23# FBA_WCLK23 27
    FBA_DQS_RN3 FBA_WCK23_N FBA_WCLK45 FBA_WCLK23# 27
    P25 T24
    FBA_DQS_RN4 FBA_WCK45 FBA_WCLK45# FBA_WCLK45 28
    W22 U24
    AB27 FBA_DQS_RN5 FBA_WCK45_N V24 FBA_WCLK67 FBA_WCLK45# 28
    FBA_DQS_RN6 FBA_WCK67 FBA_WCLK67# FBA_WCLK67 28 +FB_PLLAVDD PEX_HVDD
    T27 V25
    FBA_DQS_RN7 FBA_WCK67_N FBA_WCLK67# 28 Place close to BGA
    200mA LV2101
    PEX_HVDD
    F16 Under GPU Near GPU 1 2 N16:+1.05VGS(recommend)
    FB_PLL_AVDD_1 HCB1608KF-300T60_2P
    P22 +FB_PLLAVDD +1.0VGS(Used)
    FB_PLL_AVDD_2 OPT@ N17:+1.8VGS

    .1U_0402_10V6-K

    OPT@
    .1U_0402_10V6-K

    .1U_0402_10V6-K

    .1U_0402_10V6-K
    1

    22U_0603_6.3V6-M
    1 1 1

    OPTN17@ CV2104
    H22 Place close to ball 1

    OPT@
    CV2101

    OPT@ CV2102

    OPTN17@ CV2103
    FB_REFPLL_AVDD
    30ohms (ESR=0.01) 0603 Bead
    2
    2 2 2
    2

    CV2105
    .1U_0402_10V6-K

    .1U_0402_10V6-K

    .1U_0402_10V6-K

    1 1 1
    OPT@
    CV2106

    CV2107

    CV2108
    OPTN17@

    OPTN17@

    D23 2 2 2
    FB_VREF

    N17S-G1-A1_GB2C-64-595 @

    FB_PLL/Q Decouling
    MLCC N16 N17 location
    A
    0.1uF 2 4 Under
    A

    22uF 1 1 Near

    Security Classification LC Future Center Secret Data Title

    Issued Date 2015/08/20 Deciphered Date 2016/08/20 GPU_MEM Interface


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS441/FS540
    Date: Wednesday, October 16, 2019 Sheet 21 of 61
    5 4 3 2 1
    5 4 3 2 1

    +VGA_CORE
    +VGA_CORE
    Under GPU 12x4.7uF 5x1uF
    CV2201 CV2202 CV2203 CV2204 CV2205 CV2206 CV2207 CV2208 CV2209 CV2210 CV2211 CV2212 CV2213 CV2214 CV2215 CV2216 CV2217 CV2218
    UV1G ? COMMON INS35856873 +VGA_CORE UV1C ? COMMON INS37185662

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    4.7U_0402_6.3V6M

    4.7U_0402_6.3V6M

    4.7U_0402_6.3V6M

    4.7U_0402_6.3V6M

    4.7U_0402_6.3V6M

    4.7U_0402_6.3V6M

    4.7U_0402_6.3V6M

    4.7U_0402_6.3V6M

    4.7U_0402_6.3V6M

    4.7U_0402_6.3V6M

    4.7U_0402_6.3V6M

    4.7U_0402_6.3V6M

    33P_0402_50V8J
    6/14 XVDD 11/14 NVVDD

    OPTN17@
    K10 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

    OPTNS@

    OPTN17@

    OPTNS@

    OPTNS@

    OPTN17@
    VDD_001

    OPT@

    OPT@

    OPT@

    OPT@

    OPT@

    OPT@

    OPT@

    OPT@

    OPT@

    OPT@
    K12

    OPT@

    OPT_RF@
    G1 N4 K14 VDD_002
    G2 XVDD_1 XVDD_36 N5 K16 VDD_003
    G3 XVDD_2 XVDD_37 N7 K18 VDD_004 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
    G4 XVDD_3 XVDD_38 P3 L13 VDD_005
    G5 XVDD_4 XVDD_39 P4 L15 VDD_006
    D
    G6 XVDD_5 XVDD_40 P6 M10 VDD_007 D
    G7 XVDD_6 XVDD_41 R1 M12 VDD_008
    H3 XVDD_7 XVDD_42 R2 M16 VDD_009
    H4 XVDD_8 XVDD_43 R3 M18 VDD_010
    H6 XVDD_9 XVDD_44 R4 N11 VDD_011
    J1 XVDD_10 XVDD_45 R5 N13 VDD_012
    J2 XVDD_11 XVDD_46 R6 N15 VDD_013 Near GPU 4x4.7uF 11x10uF 4x22uF
    J3 XVDD_12 XVDD_47 R7 N17 VDD_014
    J4 XVDD_13 XVDD_48 T1 P14 VDD_015 CV2219CV2220 CV2221 CV2222 CV2223 CV2224 CV2226 CV2229 CV2231 CV2233
    CV2225 CV2227 CV2228 CV2230 CV2232 CV2234 CV2235 CV2236 CV2237 CV2238 CV2239 CV2240
    J5 XVDD_14 XVDD_49 T2 R11 VDD_016
    J6 XVDD_15 XVDD_50 T3 R13 VDD_017

    4.7U_0603_6.3V6M

    4.7U_0603_6.3V6M

    4.7U_0603_6.3V6M

    4.7U_0603_6.3V6M

    4.7U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M
    XVDD_16 XVDD_51 VDD_018

    OPTN17_NS@

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    OPTN17_NS@

    10U_0603_6.3V6M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    33P_0402_50V8J
    J7 T4 R15

    OPTN17@

    OPTN17_NS@
    XVDD_17 XVDD_52 VDD_019 1 1 1 1 1 1 1 1 1 1

    OPTNS@

    OPTNS@

    OPTN17@

    OPTN17_NS@

    OPTN17@

    OPTN17@

    OPTN17@

    OPTN17@

    RF_NS@
    K1 T5 R17 1 1 1 1 1 1 1 1 1 1 2 2

    OPT@

    OPT@

    OPT@

    OPTN17@

    OPTN17@

    OPTNS@

    OPTN17@

    OPTNS@

    OPTNS@
    K2 XVDD_18 XVDD_53 T6 T10 VDD_020
    K3 XVDD_19 XVDD_54 T7 T12 VDD_021
    K4 XVDD_20 XVDD_55 U3 T16 VDD_022
    XVDD_21 XVDD_56 VDD_023 2 2 2 2 2 2 2 2 2 2
    K5 U4 T18 2 2 2 2 2 2 2 2 2 2 1 1
    K6 XVDD_22 XVDD_57 U6 U13 VDD_024
    K7 XVDD_23 XVDD_58 V1 U15 VDD_025
    L3 XVDD_24 XVDD_59 V2 +VGA_CORE V10 VDD_026
    L4 XVDD_25 XVDD_60 V3 V12 VDD_027 CV88 Use virtual Symbol for diff value
    M1 XVDD_26 XVDD_61 V4 V14 VDD_028
    M2 XVDD_27 XVDD_62 V5 RV2201 1 @ 2 0_0402_5% V16 VDD_029
    M3 XVDD_28 XVDD_63 V6 RV2202 1 2 0_0402_5% V18 VDD_030
    XVDD_29 XVDD_64 @ VDD_031
    M4
    XVDD_30 XVDD_65
    V7 NVVDD/Q Decouling
    M5 W1
    M7 XVDD_31 XVDD_66 W2
    XVDD_32 XVDD_67
    N1
    XVDD_33 XVDD_68
    W3
    VDD_SENSE
    F2 NVVDD_VCC_SENSE
    NVVDD_VSS_SENSE NVVDD_VCC_SENSE 57 MLCC N16 N17 location
    N2 W4 F1
    XVDD_34 XVDD_69 GND_SENSE NVVDD_VSS_SENSE 57
    N3
    XVDD_35 4.7uF
    trace width: 16mils
    10 12
    differential voltage sensing. Under
    differential signal routing. 1.0uF 4 5
    N17S-G1-A1_GB2C-64-595 N17S-G1-A1_GB2C-64-595 47uF 1 0
    @

    @
    C C

    10uF 0 11
    Near
    22uF 1 4
    4.7uF 5 4
    330uF 1 2
    +1.35VGS

    UV1D ? COMMON INS35857178


    12/14 FBVDDQ

    B26 +1.35VGS
    C25 FBVDDQ_01
    E23 FBVDDQ_02 +VGA_CORE
    FBVDDQ_03 1x10uF 3x22uF
    E26
    F14 FBVDDQ_04 Under GPU(below 150mils) 8x10uF 2x10uF Near GPU UV1F ? COMMON INS35856561
    F21 FBVDDQ_05 CV2241 CV2242 CV2243 CV2244 CV2245 CV2246 CV2247 CV2248 CV2249 CV2250
    CV2251 CV2252 CV2253 CV2254 7/14 VDDS
    G13 FBVDDQ_06
    G14 FBVDDQ_07

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    10U_0603_6.3V6M
    FBVDDQ_08
    0.1U_0402_25V6

    10U_0603_6.3V6M

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K
    G15 L11

    OPTN17_NS@
    FBVDDQ_09 VDDS_1
    OPTN17@

    OPTN17@

    OPTN17@

    OPTN17@
    G16 1 2 1 1 1 1 1 1 1 1 1 1 1 2 L17
    OPTNS@

    OPTN17@

    OPTN17@

    OPTN17@

    FBVDDQ_10 VDDS_2
    OPTNS@

    OPT@

    OPT@

    OPT@
    G18 M14
    OPT@

    G19 FBVDDQ_11 P10 VDDS_3


    G20 FBVDDQ_12 P12 VDDS_4
    G21 FBVDDQ_13 2 1 2 2 2 2 2 2 2 2 2 2 2 1 P16 VDDS_5
    L22 FBVDDQ_14 P18 VDDS_6
    L24 FBVDDQ_19 T14 VDDS_7
    L26 FBVDDQ_20 U11 VDDS_8
    M21 FBVDDQ_21 U17 VDDS_9
    N21 FBVDDQ_22 VDDS_10
    B
    R21 FBVDDQ_23 B
    FBVDDQ_24 CV32 CV686 Use virtual Symbol for diff value
    T21
    V21 FBVDDQ_25
    W21 FBVDDQ_26
    H24 FBVDDQ_27 FBVDD/Q Decouling
    H26 FBVDDQ_15
    J21 FBVDDQ_16 F4 1 TV2201 @
    K21 FBVDDQ_17 MLCC N16 N17 location VDDS_SENSE F3 FB_CLAMP RV2203 1 OPTN16@ 2 10K_0402_5%
    FBVDDQ_18 GNDS_SENSE

    0.1uF 2 0 N17S-G1-A1_GB2C-64-595

    @
    1.0uF 2 8
    Under
    4.7uF 2 0
    10uF 0 2
    10uF 1 1
    Near
    22uF 1 3
    +1.35VGS

    FB_CAL_PD_VDDQ
    D22 RV2204 1 OPT@ 2 40.2_0402_1% CALIBRATION PIN GDDR5

    FB_CAL_PU_GND
    C24 RV2205 1 OPT@ 2 40.2_0402_1% FB_CAL_x_PD_VDDQ 40.2Ohm
    A A

    FB_CAL_TERM_GND
    B25 RV2206 1 OPT@ 2 60.4_0402_1% FB_CAL_x_PU_GND 40.2Ohm
    Place near balls
    FB_CAL_xTERM_GND 60.4Ohm

    Security Classification LC Future Center Secret Data Title


    N17S-G1-A1_GB2C-64-595
    Issued Date 2015/08/20 Deciphered Date 2016/08/20 GPU_+VGA_CORE,FBVDDQ
    @

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS441/FS540
    Date: Wednesday, October 16, 2019 Sheet 22 of 61
    5 4 3 2 1
    5 4 3 2 1

    N16 3V3_MAIN(N17 VDD_18) Decouling Discharge


    +3V_1.8VGS
    +1.35VGS
    Under GPU Near GPU MLCC N16 N17 location +5VALW

    1
    UV1E ? COMMON INS35858730 +VDD18 RV2301 1 OPT@ 2 0_0402_5%

    OPT@

    OPT@
    RV2302

    1
    14/14 VDD18

    1U_0402_6.3V6K

    4.7U_0402_6.3V6M
    0.1uF 2 2

    .1U_0402_10V6-K

    .1U_0402_10V6-K
    1 1 1 1 Under RV2303 470_0603_5%

    OPT@

    OPT@
    CV2301

    CV2302
    G8 Change by Bourne 20170412 OPTNS@
    VDD18_1 47K_0402_5%
    G9

    2
    VDD18_2 G10 1.0uF 1 1 OPTNS@
    1V8_AON_1 G12 2 2 2 2

    2
    CV2303

    CV2304
    1V8_AON_2 Near

    3
    D
    4.7uF 1 1 FBVDDQ_PWR_EN# 5 QV2301B
    G
    LBSS138DW1T1G_SOT363-6
    S

    4
    OPTNS@

    6
    D D D
    FBVDDQ_PWR_EN 2
    +3.3V_1.8V_AON QV2301A
    G
    N16 3V3_AON(N17 1V8_AON) Decouling S LBSS138DW1T1G_SOT363-6

    1
    Under GPU Near GPU OPTNS@
    VDD_AON RV2304 1 OPT@ 2 0_0402_5%
    MLCC N16 N17 location

    OPT@

    OPT@
    1U_0402_6.3V6K

    4.7U_0402_6.3V6M
    .1U_0402_10V6-K

    .1U_0402_10V6-K
    N17S-G1-A1_GB2C-64-595 1 1 1 1 0.1uF 1 2 Under
    OPT@
    +5VALW +3.3V_1.8V_AON
    @

    CV2305

    CV2306
    OPTN17@

    1
    2 2 2 2 1.0uF 1 1 RV2306 RV2305

    CV2307

    CV2308
    Near 47K_0402_5% 470_0603_5%
    OPTNS@ OPTNS@ +3V_1.8VGS
    4.7uF 1 1 OPTNS@

    3 2
    D
    PXS_PWREN# 5

    1
    G L2N7002KDW1T1G_SOT363-6 1
    OPTNS@ RV2308 CV2309
    QV2302B
    470_0603_5% 10U_0603_6.3V6M

    6
    D S

    4
    PXE_VDD & 1V8_AON PXS_PWREN 2 OPTNS@ GC6@
    L2N7002KDW1T1G_SOT363-6 2
    G

    2
    RV2307 QV2302A

    1
    S D

    1
    PXS_PWREN 1 OPT@ 2 0_0402_5% PXS_PWR_EN_R 2 OPTNS@
    8 PXS_PWREN PXS_PWR_EN_R 56 G
    QV2303
    1

    RV2309 S L2N7002KWT1G_SOT323-3
    100K_0402_5%

    3
    @
    2

    C C

    +3VS +3.3V_1.8V_AON
    DV2301 @

    DGPU_PWROK 1 2
    2

    1 2 RV2310 RV2311
    10K_0402_5% 10K_0402_5%
    RB521CM-30T2R_VMN2M-2 @ OPT@ RV2316 建虚拟料号,N16=470 ohm,N17=5.11
    ohm
    1

    DV2302 +1.0VGS
    PXS_PWREN 2 RV2313
    1 PXE_VDD_EN 2 1 PXE_VDD_EN_R RV109 change to 470ohm 0805 for N16 GPU
    1.8VGS_PWR_EN 2 RV27 1 3 PXE_VDD_EN_R 55
    30K_0402_5%
    1

    0_0402_5% OPTNS@
    LBAT54AWT1G_SOT323-3 RV2314 2

    1
    OPT@ OPT@ 10K_0402_5%

    1
    @ D5102 OPT@ CV2310 RV2316
    +5VALW RV2315 470_0805_5%
    0.22U_6.3V_K_X5R_0402 5.11_0805_1%
    2

    1 2 1
    OPT@
    OPTN17@ @

    2
    1 2

    2
    RB521CM-30T2R_VMN2M-2

    1
    RV2317
    47K_0402_5%
    +1.8VG_AON TO +1.8VGS

    1
    OPT@

    D
    2
    +1.0VGS_PWR_EN# 2 QV2304
    G AO3402_SOT-23-3
    +3VS
    OPTN17@

    S
    +3VS
    +3VALW

    3
    1

    1
    D
    1

    RV2320 PXE_VDD_EN_R 2 QV2305

    1
    RV2318 10K_0402_5% @ G LBSS139WT1G_SC70-3
    B B
    82K_0402_1% RV2319 OPT@ S

    1
    @ +1.0VGS 10K_0402_5% D
    @

    2
    DV2303 @ PEX_PWROK 2 QV2306
    2

    PXS_PWREN RV2321 1 @ 2 0_0402_5% 2 2 G LBSS139WT1G_SC70-3

    1
    1 D OPTN16@
    1

    NVVDD_EN 57 S

    3
    1.8VGS_PWR_EN RV2323 1 OPT@ 2 0_0402_5% 3 2 QV2307
    26,56 1.8VGS_PWR_EN RV2322
    G LBSS139WT1G_SC70-3
    1K_0402_5%
    1

    +3V_1.8VGS RV2325 1 @ 2 0_0402_5% LBAT54AWT1G_SOT323-3 S@


    @

    3
    .1U_0402_10V6-K
    RV2324 QV2308 1
    @
    CV2311
    C

    RV2326 1 OPT@ 2 0_0402_5% 100K_0402_1%


    2

    @ 2 B
    LMBT3904WT1G_SOT323-3
    .1U_0402_10V6-K
    2

    1 2
    @
    CV2312

    +5VALW +VGA_CORE
    3

    2 @

    1
    RV2328
    47K_0402_5% RV2327
    OPTNS@ 10_0603_5%
    OPTNS@

    3 2
    D
    NVVDD_EN# QV2309B
    5
    DV2304 G LBSS138DW1T1G_SOT363-6

    6
    FB_GC6_EN_R RV2329 1 GC6@ 2 0_0402_5% GC6_EN 2 D OPTNS@
    8,26 FB_GC6_EN_R S

    4
    1 FBVDDQ_PWR_EN NVVDD_EN 2 QV2309A
    DGPU_PWROK OPT@ FBVDDQ_PWR_EN 56
    RV2330 1 2 10K_0402_5% 3 G
    8,57 DGPU_PWROK LBSS138DW1T1G_SOT363-6
    @ S

    1
    PEX_PWROK RV2332 1 2 0_0402_5% BAV70W_SOT323-3 OPTNS@
    1

    GC6@
    RV2333 1 2 0_0402_5% RV2331
    .1U_0402_10V6-K

    1 NGC6@ 200K_0402_5%
    OPT@
    CV2313

    GC6@
    2

    A A
    2

    Security Classification LC Future Center Secret Data Title

    Issued Date 2015/08/20 Deciphered Date 2016/08/20 GPU_AON/MAIN PWR/SEQUENCE


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS441/FS540
    Date: Wednesday, October 16, 2019 Sheet 23 of 61
    5 4 3 2 1
    5 4 3 2 1

    UV1H ? COMMON INS35859464


    13/14 GND

    D D
    A2 K11
    AB17 GND_001 GND_057 K13
    AB20 GND_005 GND_058 K15
    AB24 GND_006 GND_059 K17
    AC2 GND_007 GND_060 L10
    AC22 GND_008 GND_061 L12
    AC26 GND_009 GND_062 L14
    AC5 GND_010 GND_063 L16
    AC8 GND_011 GND_064 L18
    AD12 GND_012 GND_065 L5
    AD13 GND_013 GND_069 M11
    A26 GND_014 GND_070 M13
    AD15 GND_002 GND_071 M15
    AD16 GND_015 GND_072 M17
    AD18 GND_016 GND_073 N10
    AD19 GND_017 GND_074 N12
    AD21 GND_018 GND_075 N14
    AD22 GND_019 GND_076 N16
    AE11 GND_020 GND_077 N18
    AE14 GND_021 GND_078 P11
    AE17 GND_022 GND_079 P13
    AE20 GND_023 GND_080 P15
    AB11 GND_024 GND_081 P17
    AF1 GND_003 GND_082 P23
    AF11 GND_025 GND_084 P26
    AF14 GND_026 GND_085 R10
    AF17 GND_027 GND_087 R12
    AF20 GND_028 GND_088 R14
    AF23 GND_029 GND_089 R16
    AF5 GND_030 GND_090 R18
    AF8 GND_031 GND_091 T11
    AG2 GND_032 GND_092 T13
    AG26 GND_033 GND_093 T15
    AB14 GND_034 GND_094 T17
    B1 GND_004 GND_095 U10
    B11 GND_035 GND_096 U12
    B14 GND_036 GND_097 U14
    B17 GND_037 GND_098 U16
    C C
    B20 GND_038 GND_099 U18
    B23 GND_039 GND_100 U23
    B27 GND_040 GND_102 U26
    B5 GND_041 GND_103 V11
    B8 GND_042 GND_105 V13
    E11 GND_043 GND_106 V15
    E14 GND_044 GND_107 V17
    E17 GND_045 GND_108 Y2
    E2 GND_046 GND_109 Y23
    E20 GND_047 GND_110 Y26
    E22 GND_048 GND_111 Y5
    E25 GND_049 GND_112 AA7
    E5 GND_050 GND_F AB7
    E8 GND_051 GND_H
    GND_052

    H2 P2
    H5 GND_053 GND_083 P5
    L2 GND_056 GND_086 U2
    GND_066 GND_101 U5
    GND_104

    H23 L23
    H25 GND_054 GND_067 L25
    GND_055 GND_068

    N17S-G1-A1_GB2C-64-595
    @

    B B

    A A

    Security Classification LC Future Center Secret Data Title

    Issued Date 2015/08/20 Deciphered Date 2016/08/20 GPU_GND


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS441/FS540
    Date: Wednesday, October 16, 2019 Sheet 24 of 61
    5 4 3 2 1
    5 4 3 2 1

    PEX_PLLVDD/Q Decouling UV1J ? COMMON INS35860124


    4/14 IFPAB
    MLCC N16 N17 location DVI HDMI DP
    SL/DL
    1.0uF 1 NA Under
    AC4
    IFPA_L3_N AC3
    TXC/TXC
    IFPA_L3
    1uF 1 NA UV1I ? COMMON INS35860218
    Near 5/14 NC AA6
    IFPAB_RSET Y3
    TXD0/0
    4.7uF 1 NA IFPA_L2_N Y4
    +PEX_PLLVDD AA14 IFPA_L2
    AA15 NC_1
    +1.0VGS AB6 NC_2 AA2
    TXD1/1
    D PEX_SVDD_3V3 AB8 NC_3 W7 IFPA_L1_N AA3 D
    AD10 NC_4 IFPAB_PLLVDD IFPA_L1
    RV2501 2 OPTN16@1 0_0402_5% Under GPU Near GPU +PEX_PLLVDD AD7 NC_5
    1 @ 2 PEX_TSTCLK_OUT AE22 NC_6 AA1
    TXD2/2

    1U_0402_6.3V6K

    4.7U_0402_6.3V6M
    CV2502 OPTN16@

    OPTN16@
    RV2502 200_0402_1% AE3 NC_7 IFPA_L0_N AB1
    NC_8 IFPA_L0

    .1U_0402_10V6-K
    1 1 1 AE4
    NC_9

    CV2501
    OPTN16@
    +3.3V_1.8V_AON AF2
    PEX_TSTCLK_OUT# AF22 NC_10 AA5
    AF3 NC_11 IFPA_AUX_SDA_N AA4
    PEX_PLLVDD NC_12 IFPA_AUX_SCL

    1
    2 2 2 Differential signal AF4

    CV2503
    N16:+1.0VGS(recommend) NC_13
    RV2504 AG3
    N17:NC 10K_0402_5% D10 NC_14 AB4
    @ E10 NC_15 IFPB_L3_N AB5
    TXC
    F10 NC_16 IFPB_L3

    2
    F5 NC_17
    +3.3V_1.8V_AON MULTI_STRAP_REF0_GND F6 NC_18 W6 AB2
    TXD0/3
    W5 NC_19 IFP_IOVDD_1 IFPB_L2_N AB3
    NC_20 Y6 IFPB_L2
    OPTN16@ 1

    1
    RV2503 2 0_0402_5% PEX_SVDD_3V3 IFP_IOVDD_2
    RV2505 TXD1/4 AD2
    IFPB_L1_N
    4.7U_0402_6.3V6M

    4.7U_0402_6.3V6M
    40.2K_0402_1% AD3
    OPTN16@

    OPTN16@

    OPTN16@ IFPB_L1
    1 1 N17S-G1-A1_GB2C-64-595

    2
    AD1

    @
    TXD2/5
    IFPB_L0_N AE1
    PEX_SVDD_3V3
    CV2504

    CV2505

    IFPB_L0
    N16:+3.3V_AON(recommend) 2 2
    N17:NC AD5
    IFPB_AUX_SDA_N AD4
    IFPB_AUX_SCL
    Near GPU UV1K ? COMMON INS35860067
    10/14 MISC2

    IFPAB (DEFEATURED 0N GM108)

    PEX_SVDD/Q Decouling N17S-G1-A1_GB2C-64-595


    D12 1

    @
    ROM_CS_N TV2501 @
    C
    MLCC N16 N17 location B12 ROM_SI
    C

    ROM_SI ROM_SO ROM_SI 29


    A12
    ROM_SO ROM_SCLK ROM_SO 29
    Near STRAP0 D1 C12
    4.7uF 2 NA 29 STRAP0
    STRAP1 D2 STRAP0 ROM_SCLK ROM_SCLK 29
    29 STRAP1 STRAP1
    STRAP2 E4
    29 STRAP2 E3 STRAP2
    STRAP3
    29 STRAP3 STRAP3
    STRAP4 D3
    29 STRAP4 STRAP4
    STRAP5 C1
    29 STRAP5 STRAP5

    D11 RV2506 2 @ 1
    BUFRST_N 10K_0402_5%

    XS_PLLVDD/Q Decouling
    MLCC N16 N17 location
    0.1uF 1 1 Under
    N17S-G1-A1_GB2C-64-595
    PEX_HVDD

    @
    N16:+1.05VGS(recommend) 22uF 1 0 Near
    +1.0VGS(Used)
    N17:+1.8VGS
    PEX_HVDD LV2501
    Under GPU XS_PLLVDD
    1 2 1 OPT@
    LV2502 2 0_0402_5%
    HCB1608KF-300T60_2P UV1L ? COMMON INS35860348
    OPT@ 9/14 XTAL_PLL +3.3V_1.8V_AON
    OPT@

    OPT@

    CV2507 @
    .1U_0402_10V6-K

    .1U_0402_10V6-K
    22U_0603_6.3V6-M
    4.7U_0402_6.3V6M

    30ohms (ESR=0.05) Bead 1 1 XS_PLLVDD L6


    OPT@

    1 1
    CV2506

    SP_PLLVDD M6 XS_PLLVDD
    SP_PLLVDD

    2
    B GPCPLL_AVDD B
    F11
    VID_PLLVDD N6 GPCPLL_AVDD RV2507
    2 2 VID_PLLVDD
    2 2 @
    CV2508

    CV2509

    10K_0402_5%
    150mA

    1
    RV2508
    2 OPT@ 1 A10
    XTALSSIN C10 XTALOUT
    XTAL_SSIN XTAL_OUTBUFF
    Under GPU(below 150mils)
    OPT@ 10K_0402_5%
    LV2503 SP_PLLVDD XTAL_IN
    1 2 0_0402_5% C11 B10 XTAL_OUT
    XTAL_IN XTAL_OUT

    1
    N17S-G1-A1_GB2C-64-595
    .1U_0402_10V6-K

    .1U_0402_10V6-K

    OPT@
    RV2509

    @
    1 1
    OPT@

    OPT@
    CV2510

    CV2511

    OPTN17@ 10K_0402_5%
    RV25101 2 0_0402_5% VID_PLLVDD

    2
    2 2

    RV2511 1 OPT@ 2 10M_0402_5% XTAL_OUT

    2
    OPTN17@ R4712
    1
    LV2504 2 0_0402_5% GPCPLL_AVDD 51_0402_1%
    YV1
    .1U_0402_10V6-K

    1 OPT@

    1
    XTAL_IN
    CV2514
    OPTN17@

    1 4
    OSC1 GND2
    2 3 XTAL_OUT_R
    2 GND1 OSC2
    GPCPLL_AVDD/Q Decouling
    OPT@

    12P_0402_50V8-J

    12P_0402_50V8-J
    OPT@
    1 1
    SP_PLLVDD & VID_PLLVDD/Q Decouling 27MHZ_10PF_7V27000050
    OPT@
    MLCC N16 N17 location MLCC N16 N17 location
    CV2512

    CV2513
    2 2
    A A
    0.1uF NA 1 Under Under
    0.1uF 2 2
    4.7uF NA 1 10uF 1 0
    Near Near
    22uF NA 1 47uF 1 0

    Security Classification LC Future Center Secret Data Title

    Issued Date 2015/08/20 Deciphered Date 2016/08/20 GPU_STRAP/DP/HDMI


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS441/FS540
    Date: Wednesday, October 16, 2019 Sheet 25 of 61
    5 4 3 2 1
    5 4 3 2 1

    +3.3V_1.8V_AON +3.3V_1.8V_AON
    UV1M ? COMMON INS35861009
    8/14 MISC1 GPU Address 0x9E

    2
    2
    RV2602
    RV2601
    2.2K_0402_5% QV2601A

    2
    2.2K_0402_5% OPT@
    OPT@
    D9 VGA_SMB_CK2

    G1
    I2CS_SCL D8 VGA_SMB_DA2 OPT@ PJT7838_SOT363-6

    1
    1
    OVERT# A6 I2CS_SDA VGA_SMB_CK2 1 6
    AE2 OVERT A9 I2CC_SCL S1 D1 EC_SMB_CK2 7,39,44
    TS_VREF I2CC_SCL B9 I2CC_SDA
    I2CC_SDA Internal Thermal Sensor
    2 @ 1 0_0402_5%
    D E12 D

    .1U_0402_10V6-K
    1 THERMDN C9 I2CB_SCL RV2603

    @
    F12 I2CB_SCL C8 I2CB_SDA

    5
    THERMDP I2CB_SDA QV2601B OPT@

    CV2601

    G2
    2 PJT7838_SOT363-6
    VGA_SMB_DA2 4 3
    S2 D2 EC_SMB_DA2 7,39,44

    C6 NVVDD_PWM_VID
    GPIO0 FB_GC6_EN NVVDD_PWM_VID 57 RV2604 2 @ 1 0_0402_5%
    B2 PU AT EC SIDE, +3VS AND 4.7K
    GPIO1 D6 GPU_EVENT#_R
    GPIO2 C7 NVVDDS_PWM 1
    GPIO3 1.8VGS_PWR_EN_R TV2601
    PLT_RST_VGA# @ F9
    RV174 1 2 56_0402_5% GPIO4 A3
    1 GPIO5 A4 PSI_VGA
    CV218 GPIO6 B6 PSI_VGA 57
    220P_0201_25V7-K GPIO7 MEM_VDD_CTL
    E9
    @ GPIO8 VGA_ALERT#
    F8
    2

    2 GPIO9 C5 GPIO10_FBVREF_ALTV +3.3V_1.8V_AON +3VALW +3VS


    GPIO10 GPIO10_FBVREF_ALTV 27
    E7
    GPIO11 VGA_AC_DET_R 2 1
    D7 VGA_AC_DET 44

    2
    OVERT# 3 1 GPIO12 DV2601 OPT@ RV2609
    WRST# 44 B4
    GPIO13 10K_0402_5%
    B3 LRB751V-40T1G_SOD323-2
    GPIO14 GC6N17@

    2
    1 C3 RV2610
    CV221 GPIO15 SYS_PEX_RST_MON#_GPU
    QV24 D5 RV2606 1 2 0_0402_5% SYS_PEX_RST_MON# RV2613 10K_0402_5%
    0.01U_0201_10V6K GPIO16 D4 FB_GC6_EN_R
    OPTN16@ 10K_0402_5% GC6N17@

    1
    @ LSI1012XT1G_SC-89-3 GPIO17 FB_GC6_EN_R 8,23
    2 C2 @
    @ GPIO18 F7

    1
    GPIO19 E6

    3
    GPIO20 GPU_PEX_RST_HOLD#_GPU GPU_PEX_RST_HOLD# GC6N17@ QV2602B
    C4 RV2607 1 2 0_0402_5%
    GPIO21 VGA_CRT_DATA

    D2
    A7 OPTN16@
    GPIO22 VGA_CRT_CLK 5 PJT7838_SOT363-6
    B7 G2
    GPIO23

    S2
    6
    N17S-G1-A1_GB2C-64-595
    QV2602A

    4
    @

    D1
    FB_GC6_EN 2 PJT7838_SOT363-6
    C G1 C
    @

    S1
    MEM_VDD_CTL RV1397 1 2 0_0402_5% SYS_PEX_RST_MON#

    2
    RV2614 GC6N17@

    1
    10K_0402_5%
    GC6@

    1
    UV1N ? COMMON INS35861249
    3/14 JTAG +3.3V_1.8V_AON GC6N16@
    RV2615 1 2 0_0402_5%
    2.2K_0404_4P2R_5%
    1 AE5 VGA_CRT_DATA 2 3
    TV2602 JTAG_TCK VGA_CRT_CLK
    1 AE6 1 4
    TV2603 1 AF6 JTAG_TDI @
    TV2604 JTAG_TDO RPV4
    1 AD6
    2 TV2605 JTAG_TMS 2.2K_0404_4P2R_5%
    10K_0402_5% OPT@ 1 RV2611 AG4
    10K_0402_5% 2 OPT@ 1 RV2612 TESTMODE AD9 JTAG_TRST_N I2CB_SCL 2 3
    NVJTAG_SEL I2CB_SDA 1 4 +3.3V_1.8V_AON +3.3V_1.8V_AON
    @ RPV3

    .1U_0402_10V6-K
    2.2K_0404_4P2R_5%

    2
    1

    @
    I2CC_SCL

    CV2604
    2 3
    I2CC_SDA 1 4 RV2616
    10K_0402_5%
    @
    RPV2 GC6@ 2

    2
    MEM_VDD_CTL RV224 1 @ 2 10K_0402_5%
    +3.3V_1.8V_AON

    N17S-G1-A1_GB2C-64-595 GPU_EVENT#_R 3 1 GPU_EVENT#


    GPU_EVENT# 8
    @

    1.8VGS_PWR_EN_R RV18 2 OPT@ 1 1K_0402_1%


    GC6@
    QV2604
    OVERT# RV20 1 OPT@ 2 10K_0402_5% LSI1012XT1G_SC-89-3

    VGA_ALERT# RV2619 1 @ 2 0_0402_5%


    RV23 1 OPT@ 2 10K_0402_5%
    B B
    VGA_AC_DET_R RV26 1 OPT@ 2 100K_0402_5%

    PSI_VGA RV29 1 @ 2 10K_0402_5%

    GPU_PEX_RST_HOLD# RV31 1 OPT@ 2 10K_0402_5% +3VS


    +3VS

    2
    RV2921
    10K_0402_5%
    OPT@

    2
    RV2922
    10K_0402_5%
    +3.3V_1.8V_AON OPT@ 1.8VGS_PWR_EN

    1
    +3VS 1.8VGS_PWR_EN 23,56
    +3.3V_1.8V_AON

    1
    2

    3
    RV2617 RV2618 RV2622 QV2704B

    D2
    0_0402_5% 10K_0402_5% 10K_0402_5% 5 PJT7838_SOT363-6
    OPT@ OPTN16@ OPT@ G2
    OPT@

    S2
    +1.8VGARST 1

    6
    .1U_0402_10V6-K

    4
    OPT@
    CV2605

    QV2704A

    D1
    1.8VGS_PWR_EN_R 2 PJT7838_SOT363-6
    G1
    2 OPT@

    S1
    DV2602
    5

    UV2602 GPU_PEX_RST_HOLD# 2

    1
    PLT_RST#_B 1 1
    P

    11,37,40,44 PLT_RST#_B B SYS_PEX_RST_MON# PLT_RST_VGA# 20


    4 3
    2 Y
    8 PXS_RST# A
    G

    LBAT54AWT1G_SOT323-3
    MC74VHC1G09DFT2G_SC70-5 OPTN16@
    3

    OPT@ OPTNS@
    1

    RV2631 1 2 0_0402_5%
    1

    1.8VGS_PWR_EN_R RV2923 1 2 0_0402_5% 1.8VGS_PWR_EN


    RV2620
    RV2621 OPTN17@
    A 100K_0402_5% 100K_0402_5% A
    OPT@ OPT@
    2
    2

    RC1557 has PD

    Security Classification LC Future Center Secret Data Title

    Issued Date 2015/08/20 Deciphered Date 2016/08/20 GPU_GPIO/JTAG


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS441/FS540
    Date: Wednesday, October 16, 2019 Sheet 26 of 61
    5 4 3 2 1
    5 4 3 2 1

    Lower 32 bits
    MF=0 No Mirror
    21,28 FBA_D[0..63]
    +1.35VGS
    21,28 FBA_CMD[31..0]
    UM5
    21,28 FBA_EDC[7..0]
    MF=0 MF=1 MF=1 MF=0 Close to VRAM
    21,28 FBA_DBI[7..0]
    A4 FBA_D0 CV741 CV743 CV742 CV623 CV621 CV622 CV625
    FBA_EDC0 C2 DQ24 DQ0 A2 FBA_D1

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K
    FBA_EDC1 C13 EDC0 EDC3 DQ25 DQ1 B4 FBA_D2
    D D
    FBA_EDC2 EDC1 EDC2 DQ26 DQ2 FBA_D3 1 1 1 1 1 1 1

    OPT_NS@
    R13 B2 BYTE0

    OPT_NS@

    OPT_NS@

    OPT_NS@

    OPT_NS@

    OPT_NS@
    EDC2 EDC1 DQ27 DQ3

    OPT@
    FBA_EDC3 R2 E4 FBA_D4
    EDC3 EDC0 DQ28 DQ4 E2 FBA_D5
    DQ29 DQ5 F4 FBA_D6
    DQ30 DQ6 2 2 2 2 2 2 2
    FBA_DBI0 D2 F2 FBA_D7
    FBA_DBI1 D13 DBI0# DBI3# DQ31 DQ7 A11 FBA_D8
    FBA_DBI2 P13 DBI1# DBI2# DQ16 DQ8 A13 FBA_D9
    OPT@ FBA_DBI3 P2 DBI2# DBI1# DQ17 DQ9 B11 FBA_D10
    FBA_CLK0 RV193 1 2 40.2_0402_1% DBI3# DBI0# DQ18 DQ10
    21 FBA_CLK0 B13 FBA_D11
    FBA_CLK0 DQ19 DQ11 FBA_D12
    BYTE1
    FBA_CLK0# J12 E11
    RV194 1 OPT@ 2 40.2_0402_1% FBA_CLK0# J11 CK DQ20 DQ12 E13 FBA_D13
    21 FBA_CLK0#
    FBA_CMD14 J3 CK# DQ21 DQ13 F11 FBA_D14 CV744 CV745 CV746 CV627 CV628 CV630 CV629
    1 CKE# DQ22 DQ14 F13 FBA_D15

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K
    CV228 DQ23 DQ15 FBA_D16

    1U_0402_6.3V6K
    U11
    0.01U_0201_10V6K FBA_CMD2 DQ8 DQ16 FBA_D17 1 1 1 1 1 1 1
    H11 U13

    OPT_NS@

    OPT@

    OPT_NS@

    OPT_NS@

    OPT_NS@

    OPT_NS@
    OPT@ FBA_CMD4 BA0/A2 BA2/A4 DQ9 DQ17 FBA_D18

    OPT_NS@
    2 K10 T11
    FBA_CMD3 K11 BA1/A5 BA3/A3 DQ10 DQ18 T13 FBA_D19
    FBA_CMD1 BA2/A4 BA0/A2 DQ11 DQ19 FBA_D20
    BYTE2
    H10 N11 2 2 2 2 2 2 2
    BA3/A3 BA1/A5 DQ12 DQ20 N13 FBA_D21
    DQ13 DQ21 M11 FBA_D22
    FBA_CMD6 K4 DQ14 DQ22 M13 FBA_D23
    FBA_CMD11 H5 A8/A7 A10/A0 DQ15 DQ23 U4 FBA_D24
    FBA_CMD10 H4 A9/A1 A11/A6 DQ0 DQ24 U2 FBA_D25
    FBA_CMD7 K5 A10/A0 A8/A7 DQ1 DQ25 T4 FBA_D26
    FBA_CMD9 J5 A11/A6 A9/A1 DQ2 DQ26 T2 FBA_D27
    A12/RFU/NC DQ3 DQ27 N4 FBA_D28 Around VRAM
    DQ4 DQ28 FBA_D29
    BYTE3
    A5 N2
    U5 VPP/NC1 DQ5 DQ29 M4 FBA_D30
    VPP/NC2 DQ6 DQ30 M2 FBA_D31 CV747 CV748 CV750 CV749 CV751 CV752 CV753
    DQ7 DQ31
    +1.35VGS

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M
    RV182 1 OPT@ 2 1K_1%_0201 J1
    RV183 1 OPT@ 2 1K_1%_0201 FBA_SEN0 J10 MF 1 1
    SEN 1 1 1 1 1

    OPT@

    OPT@

    OPT@

    OPT@

    OPT@
    RV185 1 2 121_0402_1% OPT@ J13 B1
    ZQ VDDQ1

    OPT_NS@

    OPT_NS@
    D1
    VDDQ2 F1
    VDDQ3 2 2
    FBA_CMD8 J4 M1 2 2 2 2 2
    FBA_CMD12 G3 ABI# VDDQ4 P1
    C FBA_CMD0 G12 RAS# CAS# VDDQ5 T1 C
    FBA_CMD15 L3 CS# WE# VDDQ6 G2
    FBA_CMD5 L12 CAS# RAS# VDDQ7 L2
    WE# CS# VDDQ8 B3
    VDDQ9 D3
    VDDQ10 F3
    FBA_WCLK01# D5 VDDQ11 H3
    21 FBA_WCLK01# FBA_WCLK01 WCK01# WCK23# VDDQ12
    D4 K3
    21 FBA_WCLK01 WCK01 WCK23 VDDQ13 M3
    FBA_WCLK23# P5 VDDQ14 P3
    21 FBA_WCLK23# FBA_WCLK23 WCK23# WCK01# VDDQ15
    P4 T3
    21 FBA_WCLK23 WCK23 WCK01 VDDQ16 E5
    VDDQ17 N5
    A10 VDDQ18 E10
    FBA_VREFC VREFD1 VDDQ19
    U10 N10
    +1.35VGS FBA_VREFC J14 VREFD2 VDDQ20 B12
    VREFC VDDQ21 D12
    CV224 1 VDDQ22 F12
    820P_0402_25V7 VDDQ23 H12
    VDDQ24
    1

    FBA_CMD13 J2 K12 +1.35VGS


    RV192 OPT@ 2 RESET# VDDQ25 M12
    549_0402_1% VDDQ26 P12
    OPT@ VDDQ27 T12
    VDDQ28 G13
    1 2

    FBA_VREFC H1 VDDQ29 L13 CV2606 CV2607 CV2608 CV2609


    K1 VSS1 VDDQ30 B14

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K
    B5 VSS2 VDDQ31 D14 CV2622

    4.3U_0402_4V6-M
    RV191 VSS3 VDDQ32 1 1 1 1

    OPT_N3T@

    OPT_N3T@

    OPT_N3T@

    OPT_N3T@
    G5 F14

    3
    1.33K_0402_1% VSS4 VDDQ33

    OPT_3T@
    L5 M14
    OPT@ VSS5 VDDQ34
    T5 P14
    2

    B10 VSS6 VDDQ35 T14

    4
    VSS7 VDDQ36 2 2 2 2
    D10
    G10 VSS8
    L10 VSS9 A1
    P10 VSS10 VSSQ1 C1
    T10 VSS11 VSSQ2 E1
    H14 VSS12 VSSQ3 N1
    K14 VSS13 VSSQ4 R1
    B B
    VSS14 VSSQ5 U1
    VSSQ6 H2
    +1.35VGS G1 VSSQ7 K2
    L1 VDD1 VSSQ8 A3
    VDD2 VSSQ9 +1.35VGS
    G4 C3
    FBA_VREFC L4 VDD3 VSSQ10 E3
    RV190 C5 VDD4 VSSQ11 N3
    R5 VDD5 VSSQ12 R3
    931_0402_1% C10 VDD6 VSSQ13 U3
    2 1 VDD7 VSSQ14 CV2610 CV2611 CV2612 CV2613
    R10 C4
    VDD8 VSSQ15

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K
    D11 R4 CV2623

    4.3U_0402_4V6-M
    OPT@ G11 VDD9 VSSQ16 F5 1 1 1 1

    OPT_N3T@

    OPT_N3T@

    OPT_N3T@

    OPT_N3T@
    VDD10 VSSQ17

    3
    OPT_3T@
    L11 M5
    P11 VDD11 VSSQ18 F10
    1

    D QV26
    G14 VDD12 VSSQ19 M10
    2

    4
    26 GPIO10_FBVREF_ALTV LBSS139WT1G_SC70-3 L14 VDD13 VSSQ20 C11 2 2 2 2
    G VDD14 VSSQ21 R11
    OPT@
    1

    S VSSQ22 A12
    3

    RV208 VSSQ23 C12


    100K_0402_5% VSSQ24 E12
    OPT@ VSSQ25 N12
    VSSQ26 R12
    2

    170-BALL VSSQ27 U12


    VSSQ28 H13
    SGRAM GDDR5 VSSQ29 K13
    VSSQ30 A14
    VSSQ31 C14
    VSSQ32 E14
    VSSQ33 N14
    VSSQ34 R14
    VSSQ35 U14
    VSSQ36
    @ H5GQ1H24AFR-T2L_BGA170

    A A

    Security Classification LC Future Center Secret Data Title

    Issued Date 2015/08/20 Deciphered Date 2016/08/20 GPU_GDDR5_Rank0_[31:0]


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS441/FS540
    Date: Wednesday, October 16, 2019 Sheet 27 of 61
    5 4 3 2 1
    5 4 3 2 1

    upper 32 bits

    21,27 FBA_D[0..63] MF=0 No Mirror


    21,27 FBA_CMD[31..0]
    UM14
    21,27 FBA_EDC[7..0]
    MF=0 MF=1 MF=1 MF=0
    D 21,27 FBA_DBI[7..0] D
    A4 FBA_D32
    FBA_EDC4 C2 DQ24 DQ0 A2 FBA_D33
    FBA_EDC5 C13 EDC0 EDC3 DQ25 DQ1 B4 FBA_D34
    FBA_EDC6 R13 EDC1 EDC2 DQ26 DQ2 B2 FBA_D35
    FBA_EDC7 EDC2 EDC1 DQ27 DQ3 FBA_D36
    BYTE4
    R2 E4
    EDC3 EDC0 DQ28 DQ4 E2 FBA_D37
    DQ29 DQ5 F4 FBA_D38
    FBA_DBI4 D2 DQ30 DQ6 F2 FBA_D39
    FBA_DBI5 D13 DBI0# DBI3# DQ31 DQ7 A11 FBA_D40
    FBA_DBI6 P13 DBI1# DBI2# DQ16 DQ8 A13 FBA_D41
    FBA_DBI7 P2 DBI2# DBI1# DQ17 DQ9 B11 FBA_D42
    DBI3# DBI0# DQ18 DQ10 B13 FBA_D43
    FBA_CLK1 DQ19 DQ11 FBA_D44
    BYTE5 +1.35VGS
    J12 E11
    FBA_CLK1# J11 CK DQ20 DQ12 E13 FBA_D45 Close to VRAM
    FBA_CMD30 J3 CK# DQ21 DQ13 F11 FBA_D46
    FBA_CLK1 OPT@ CKE# DQ22 DQ14 FBA_D47
    RV195 1 2 40.2_0402_1% F13 CV654 CV729 CV650 CV651 CV653 CV652 CV730
    21 FBA_CLK1 DQ23 DQ15 FBA_D48
    U11
    FBA_CLK1# RV196 1 OPT@ 2 40.2_0402_1% FBA_CMD18 H11 DQ8 DQ16 U13 FBA_D49

    10U_0603_6.3V6M

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K
    21 FBA_CLK1# FBA_CMD20 BA0/A2 BA2/A4 DQ9 DQ17 FBA_D50

    10U_0603_6.3V6M
    K10 T11
    1 BA1/A5 BA3/A3 DQ10 DQ18 1 1 1 1 1 1 1

    OPT_NS@

    OPT_NS@
    FBA_CMD19 K11 T13 FBA_D51

    OPT@

    OPT@

    OPT_NS@

    OPT_NS@

    OPT_NS@
    CV649 FBA_CMD17 H10 BA2/A4 BA0/A2 DQ11 DQ19 N11 FBA_D52
    0.01U_0201_10V6K BA3/A3 BA1/A5 DQ12 DQ20 FBA_D53
    BYTE6
    N13
    OPT@ DQ13 DQ21 M11 FBA_D54
    2 DQ14 DQ22 2 2 2 2 2 2 2
    FBA_CMD22 K4 M13 FBA_D55
    FBA_CMD27 H5 A8/A7 A10/A0 DQ15 DQ23 U4 FBA_D56
    FBA_CMD26 H4 A9/A1 A11/A6 DQ0 DQ24 U2 FBA_D57
    FBA_CMD23 K5 A10/A0 A8/A7 DQ1 DQ25 T4 FBA_D58
    FBA_CMD25 J5 A11/A6 A9/A1 DQ2 DQ26 T2 FBA_D59
    A12/RFU/NC DQ3 DQ27 N4 FBA_D60
    DQ4 DQ28 FBA_D61
    BYTE7
    A5 N2 CV731 CV732 CV733 CV638 CV639 CV641 CV640
    U5 VPP/NC1 DQ5 DQ29 M4 FBA_D62
    VPP/NC2 DQ6 DQ30

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K
    M2 FBA_D63
    DQ7 DQ31
    1 1 1 1 1 1 1

    OPT_NS@
    +1.35VGS

    OPT_NS@

    OPT_NS@

    OPT_NS@

    OPT_NS@

    OPT_NS@
    RV197 1 OPT@ 2 1K_1%_0201 J1

    OPT@
    RV198 1 OPT@ 2 1K_1%_0201 FBA_SEN1 J10 MF
    RV201 1 2 121_0402_1% OPT@ J13 SEN B1
    ZQ VDDQ1 D1 2 2 2 2 2 2 2
    C VDDQ2 F1 C
    FBA_CMD24 J4 VDDQ3 M1
    FBA_CMD28 G3 ABI# VDDQ4 P1
    FBA_CMD16 G12 RAS# CAS# VDDQ5 T1
    FBA_CMD31 L3 CS# WE# VDDQ6 G2
    FBA_CMD21 L12 CAS# RAS# VDDQ7 L2
    WE# CS# VDDQ8 B3
    VDDQ9 D3 Around VRAM
    VDDQ10 F3
    FBA_WCLK45# D5 VDDQ11 H3 CV734 CV735 CV736 CV737 CV738 CV739 CV740
    21 FBA_WCLK45# FBA_WCLK45 WCK01# WCK23# VDDQ12
    D4 K3
    21 FBA_WCLK45 WCK01 WCK23 VDDQ13

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M
    M3
    FBA_WCLK67# P5 VDDQ14 P3 1 1 1 1 1 1 1

    OPT@

    OPT@

    OPT@

    OPT@
    21 FBA_WCLK67# FBA_WCLK67 P4 WCK23# WCK01# VDDQ15 T3

    OPT_NS@

    OPT_NS@

    OPT_NS@
    21 FBA_WCLK67 WCK23 WCK01 VDDQ16 E5
    VDDQ17 N5
    FBA_VREFC VDDQ18 2 2 2 2 2 2 2
    A10 E10
    U10 VREFD1 VDDQ19 N10
    FBA_VREFC J14 VREFD2 VDDQ20 B12
    VREFC VDDQ21 D12
    1 VDDQ22
    CV665 F12
    820P_0402_25V7 VDDQ23 H12
    FBA_CMD29 J2 VDDQ24 K12
    OPT@ 2 RESET# VDDQ25 M12
    VDDQ26 P12
    VDDQ27 T12
    VDDQ28 G13
    H1 VDDQ29 L13
    K1 VSS1 VDDQ30 B14
    B5 VSS2 VDDQ31 D14
    G5 VSS3 VDDQ32 F14
    L5 VSS4 VDDQ33 M14
    VSS5 VDDQ34 +1.35VGS
    T5 P14
    B10 VSS6 VDDQ35 T14
    D10 VSS7 VDDQ36
    G10 VSS8
    L10 VSS9 A1
    VSS10 VSSQ1 CV2618 CV2619 CV2620 CV2621
    B P10 C1 CV2625 B
    VSS11 VSSQ2

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K
    T10 E1

    4.3U_0402_4V6-M
    H14 VSS12 VSSQ3 N1 1 1 1 1

    OPT_N3T@

    OPT_N3T@

    OPT_NS@

    OPT_N3T@

    OPT_3T@
    VSS13 VSSQ4

    3
    K14 R1
    VSS14 VSSQ5 U1
    VSSQ6 H2

    4
    +1.35VGS G1 VSSQ7 K2 2 2 2 2
    L1 VDD1 VSSQ8 A3
    G4 VDD2 VSSQ9 C3
    L4 VDD3 VSSQ10 E3
    C5 VDD4 VSSQ11 N3
    R5 VDD5 VSSQ12 R3
    C10 VDD6 VSSQ13 U3
    R10 VDD7 VSSQ14 C4
    D11 VDD8 VSSQ15 R4
    G11 VDD9 VSSQ16 F5
    L11 VDD10 VSSQ17 M5
    P11 VDD11 VSSQ18 F10 +1.35VGS
    G14 VDD12 VSSQ19 M10
    L14 VDD13 VSSQ20 C11
    VDD14 VSSQ21 R11
    VSSQ22 A12
    VSSQ23 C12 CV2614 CV2615 CV2616 CV2617 CV2624
    VSSQ24 E12

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K
    VSSQ25 N12

    4.3U_0402_4V6-M
    OPT_NS@
    VSSQ26 1 1 1 1

    OPT_NS@

    OPT_NS@

    OPT_NS@

    OPT_NS@
    R12

    3
    170-BALL VSSQ27 U12
    VSSQ28 H13
    SGRAM GDDR5 VSSQ29 K13

    4
    VSSQ30 2 2 2 2
    A14
    VSSQ31 C14
    VSSQ32 E14
    VSSQ33 N14
    VSSQ34 R14
    VSSQ35 U14
    VSSQ36
    @
    H5GQ1H24AFR-T2L_BGA170
    A A

    Security Classification LC Future Center Secret Data Title

    Issued Date 2015/08/20 Deciphered Date 2016/08/20 GPU_GDDR5_Rank0_[64:32]


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS441/FS540
    Date: Wednesday, October 16, 2019 Sheet 28 of 61
    5 4 3 2 1
    5 4 3 2 1

    +3.3V_1.8V_AON
    X76
    GPU FB Memory (GDDR5) RAMCFG[4:0] STRAP2 STRAP1 STRAP0

    2
    RV2901 RV2902 RV2903 Samsung 8Gb K4G80325FB-HC28 0(0x0000) L L L
    100K_0402_5% 100K_0402_5% 100K_0402_5%
    @ @ @
    8Gb Micron 8Gb MT51J256M32HF-70:A 1(0x0001) L L H

    1
    D D

    25 STRAP0 STRAP0
    25 STRAP1 STRAP1 Hynix 8Gb H5GC8H24MJR-R0C 2(0x0010) L H L
    25 STRAP2 STRAP2

    2
    RV2904 RV2905 RV2906
    100K_0402_5% 100K_0402_5% 100K_0402_5%
    @ @ @
    1

    1
    +3.3V_1.8V_AON
    STRAP5 STRAP4 STRAP3 SMB_ALT_ADDR DEVID_SEL PCIE_CFG VGA_DEVICE

    L L L 0 0 0 0
    2

    2
    RV2907 RV2908 RV2909
    100K_0402_5% 100K_0402_5% 100K_0402_5% 1: SMB_ALT_ADDR ENABLE
    @ @ @
    C 0: SMB_ALT_ADDR DISABLE C
    1

    1: DEVID_SEL REBRAND
    25 STRAP3 STRAP3
    25 STRAP4 STRAP4 0: DEVID_SEL ORIGNAL
    25 STRAP5 STRAP5

    1: PCIE_CFG LOW POWER


    2

    0: PCIE_CFG HIGH POWER


    RV2910 RV2911 RV2912
    100K_0402_5% 100K_0402_5% 100K_0402_5%
    @ @ @ 1: VGA_DEVICE ENABLE
    1

    0: VGA_DEVICE DISABLE

    Strap5 is NC pin on N16

    DEVID_SEL
    0 (Default)
    B B
    1

    +3V_1.8VGS +3.3V_1.8V_AON PCIE_CFG


    ROM_SO ROM_SI ROM_SCLK SOR_EXPOSED[3:0] 1:ENABLE 0:DISABLE 0 (Default)
    2
    2

    RV2914
    RV2913
    0_0402_5%
    0_0402_5% 0000 SOR0/1/2/3 DISABLE 1
    OPTN17@ N17S-G1 H H M
    OPTN16@
    1
    1

    N16S-GTR SMBUS_ALT_ADDR
    2

    RV2915 RV2916 RV2917 0 0x9E (Default)


    100K_0402_5% 100K_0402_5% 100K_0402_5%
    @ @ @
    1 0x9C (Multi-GPU usage)
    1

    25 ROM_SI
    ROM_SI
    ROM_SO
    VGA_DEVICE
    25 ROM_SO ROM_SCLK
    25 ROM_SCLK 0 3D Device (Class Code 302h)
    2

    RV2918 RV2919 RV2920 1 VGA Device (Default)


    100K_0402_5% 100K_0402_5% 100K_0402_5%
    @ @ @
    1

    A A

    Security Classification LC Future Center Secret Data Title

    Issued Date 2015/08/20 Deciphered Date 2016/08/20 GPU_MISC


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS441/FS540
    Date: Wednesday, October 16, 2019 Sheet 29 of 61
    5 4 3 2 1
    5 4 3 2 1

    DVDD_IO @
    +3VALW
    CPU HDA BUS power
    RA3025 1 2 1K_0402_5% CA423 1 @2 0.1U_6.3V_K_X5R_0402

    1 2 RA27 DVDD_IO
    DA3002
    1/2W_0.01_1%_0603_50PPM/C 3
    +1.8VALW 44 EC_BEEP
    HDA33@ RA3023 CA3017

    2
    1 1 2 1 2 BEEP
    1mA RA3027
    1 2 RA726 @ 0_0402_5% 8 PCH_BEEP 2 1K_0402_5% 0.1U_6.3V_K_X5R_0402
    D D

    10K_0402_5%
    2
    1/2W_0.01_1%_0603_50PPM/C BAT54CW_SOT323-3

    RA3024
    HDA18@ @
    RA3026 1 2 0_0402_5%

    1
    @

    COLSE To Connector
    HDA_BITCLK_AUDIO
    C C
    1
    CA3018
    33P_0402_50V8J
    EMC_NS@ 2

    For EMI

    +5VS
    +5VS +3VS JIO2
    1
    +5VS +3VL +3VS JIO1 2 1
    JIO3 1 BEEP 3 2
    1 2 1 4 3
    +3VS 2 1 BEEP 3 2 5 4
    2 3 +3VL 5
    BEEP 3 4 6
    3 4 30,36 NOVO_BTN# 6
    4 5 7
    4 NOVO_BTN# 5 30,44 EC_MUTE# 7
    5 6 8
    +3VL 5 30,36 NOVO_BTN# EC_MUTE# 6 8
    6 7 9
    30,36 NOVO_BTN# 6 30,44 EC_MUTE# 7 9,30 USB20_N5 9
    7 8 10
    30,44 EC_MUTE# 8 7 USB20_N5 9 8 9,30 USB20_P5 11 10
    8 9,30 USB20_N5 USB20_P5 9 11
    9 10 12
    B 9,30 USB20_N5 9 9,30 USB20_P5 10 30,33 DMIC_CLK 12 B
    10 11 13
    9,30 USB20_P5 10 DMIC_CLK 11 30,33 DMIC_DATA 13
    11 12 14
    11 30,33 DMIC_CLK DMIC_DATA 12 14
    12 30,33 DMIC_DATA 13 15
    30,33 DMIC_CLK 13 12 14 13 8,30 HDA_BITCLK_AUDIO 16 15
    30,33 DMIC_DATA 13 HDA_BITCLK_AUDIO 14 8,30 HDA_SDOUT_AUDIO 16
    14 15 17
    14 8,30 HDA_BITCLK_AUDIO HDA_SDOUT_AUDIO 15 8,30 HDA_SDIN0 17
    15 16 18
    8,30 HDA_BITCLK_AUDIO 16 15 8,30 HDA_SDOUT_AUDIO HDA_SDIN0 17 16 8,30 HDA_SYNC_AUDIO 19 18
    8,30 HDA_SDOUT_AUDIO 16 8,30 HDA_SDIN0 HDA_SYNC_AUDIO 17 DVDD_IO 19
    17 18 +1.8VS 20
    8,30 HDA_SDIN0 18 17 8,30 HDA_SYNC_AUDIO 19 18 21 20
    8,30 HDA_SYNC_AUDIO 18 DVDD_IO 19 30,36,45 ON/OFFBTN# 21
    DVDD_IO 19 +1.8VS 20 30,44 PWR_LED1# 22
    20 19 ON/OFFBTN# 21 20 25 23 22
    +1.8VS 20 30,36,45 ON/OFFBTN# 21 GND1 30,44 PWR_LED2# 23
    21 22 26 24
    GND1 30,44 PWR_LED1# 22 GND2 +3VALW 24
    22 30,44 PWR_LED2# 23 25
    GND2 24 23 26 25
    +3VALW 24 +1.8VS 26
    27
    HIGHS_FC5AF201-1151H HIGHSTAR_FC5AF241-2931H 28 27
    +3VS 28
    ME@ ME@ 29 32
    30 29 GND2 31
    +5VS 30 GND1

    HIGHS_FC5AF301-2931H

    20Pin CONN 24Pin CONN


    ME@

    30Pin CONN

    A A

    Security Classification LC Future Center Secret Data Title

    Issued Date 2015/08/20 Deciphered Date 2016/08/20 CODEC_RTS5199


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS441/FS540
    Date: Wednesday, October 16, 2019 Sheet 30 of 61
    5 4 3 2 1
    5 4 3 2 1

    D D

    C C

    B B

    A A

    Title
    <Title>

    Size Document Number Rev


    A FS441/FS540 0.1

    Date: Wednesday, October 16, 2019 Sheet 31 of 61


    5 4 3 2 1
    5 4 3 2 1

    +3VALW +3V_TPM

    R2101
    1 2

    1/2W_0.01_1%_0603_50PPM/C

    C2101

    C2103

    C2104
    TPM@ 1 2 1 1

    0.1U_6.3V_K_X5R_0201

    C2102
    10U_0603_6.3V6M

    0.1U_6.3V_K_X5R_0201

    0.1U_6.3V_K_X5R_0201
    @ +3V_TPM

    TPM@ TPM@ @
    2 1 2 2
    D D

    +3VALW

    2
    R2102
    @ 10K_0402_5% R2103 R2104
    TPM@ 10K_0402_5% @ 10K_0402_5%

    22
    U2101

    1
    1

    VDD3

    VDD2

    NCI/VDD1
    1

    1
    TPM@
    R2110 2 1 0_0402_5% TPM_IRQ# 18
    8 TPM_SPI_IRQ# PIRQ# 3
    NCI1 4 R10178 1 @ 2 0_0402_5%
    R2105 2 TPM@ 1 49.9_0402_1% TPM_MOSI 21 NCI2 5
    7 SPI_SI_R 2 1 TPM_MISOI 24 MOSI NCI3 10
    R2106 49.9_0402_1%
    7 SPI_SO_R MISO NCI4
    TPM@ 11
    NCI5 12
    NCI6 13
    R2107 2 TPM@ 1 0_0402_5% TPM_CS2# 20 NCI7 14
    7 SPI_CS2#_R CS# VDD/NCI8 15
    R2108 2 TPM@ 1 49.9_0402_1% TPM_CLK 19 NCI9 16
    7 SPI_CLK_R SCLK GND/NCI10 25
    17 NCI11 26
    11,32 PLT_RST# RST# NCI12 27
    6 NCI13 28
    GPIO NCI14 31
    TPM_PP 7 NCI15
    PP

    29 R2111 1 @ 2 0_0402_5%
    NC1 PLT_RST# 11,32

    1
    30
    NC2

    GND1

    GND2

    GND3

    GND4

    GND5
    R2112
    0_0402_5%
    C @ C
    SLB9670VQ2.0FW7.61_VQFN32_5X5

    23

    32

    33
    2

    9
    TPM@

    TABLE

    Pin TCG Infineon ST Micro Nuvoton NATIONZ


    No
    PTP Spec (v38) SLB9670VQ2.0 FW 7.61 ST33HTPH2E32AHB4 NPCT750LABYX Z32H330TC

    1 VDD NC/VDD NC VSB VDD


    2 GND GND GND NC GND
    B
    3 GPIO NC NC NC NC B
    4 GPIO NC NC PP/GPIO6 NC
    5 NC NC NC NC NC
    6 VNC/GPIO GPIO GPIO GPIO3 NC
    7 GPIO/VDD PP PP NC PP
    8 VDD VDD NC VHIO VDD

    9 GND GND NC NC GND


    10 VNC NC NC NC NC
    11 NC NC NC NC NC
    12 NC NC NC NC NC
    13 VNC/GPIO NC NC GPIO4 NC
    14 VDD NC/VDD NC NC VDD
    15 NC NC NC NC NC
    16 GND NC/GND NC GND GND

    17 SPI_RST# RST# SPI_RST# PLTRST# SPI_RST#


    18 SPI_PIRQ# PIRQ# SPI_PIRQ# PIRQ#/GPIO2 SPI_PIRQ#
    19 SPI_CLK SCLK SPI_CLK SCLK SPI_CLK
    20 SPI_CS# CS# SPI_CS# SCS#/GPIO5 SPI_CS#
    21 MOSI MOSI MOSI MOSI/GPIO7 MOSI
    22 VDD VDD VPS VHIO VDD
    23 GND GND NC GND GND
    24 MISO MISO MISO MISO MISO

    A A
    25 NC NC NC NC NC
    26 NC NC NC NC NC
    27 NC NC NC NC NC
    28 NC NC NC NC NC
    29 VNC/GPIO NC NC SDA/GPIO0 NC
    30 VNC/GPIO NC NC SCL/GPIO1 NC
    31 VNC NC NC NC NC
    32 GND GND NC NC GND Security Classification LC Future Center Secret Data Title
    TPM
    Issued Date 2012/07/01 Deciphered Date 2014/07/01
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS441/FS540
    Date: Wednesday, October 16, 2019 Sheet 32 of 61
    5 4 3 2 1
    5 4 3 2 1

    CMOS Camera
    +3VS LCD POWER CIRCUIT +LEDVDD +3VS +3VS_EDP
    +LCDVDD +LCDVDD_CON V20B+
    F3806 W=40mils
    1 W=60mils F3301

    0.047U_0402_16V7K
    .1U_0402_10V6-K
    C3306 For RF 1 2 1 2
    U3301 R120

    10U_0603_6.3V6M
    .1U_0402_10V6-K 1 1
    2

    C3303
    5 1 1 2 3A_32V_ERBRD3R00X C3304
    2 IN OUT 1A_32V_ERBRD1R00X @

    0.1U_0402_25V7-K

    C3305
    33P_0402_50V8J
    .1U_0402_10V6-K

    4.7U_0805_25V6-K
    @
    4.7U_0603_6.3V6K
    D 2 1/2W_0.01_1%_0603_50PPM/C @ D
    GND 2 2

    1
    1 1 1 1 1

    C3312
    @
    PCH_ENVDD

    C3311
    4 3 @
    4 PCH_ENVDD EN OCB

    C3307

    C3308

    C3309

    2
    SY6288C20AAC_SOT23-5 2 2 2 2 @ EMI request
    F3806：MB bom change source SP040004X00；
    the source no symbol

    U3301 EN PIN VIH MIN 1.35V


    EMI Request

    +3VS JEDP1

    +LEDVDD 1
    1

    2
    2
    R3312 3 2
    PCH_ENBKL 1 @ 2 0_0402_5% 4.7K_0402_5% 4 3
    4,44 PCH_ENBKL CPU_EDP_TX0+ 4
    R3311 @ C3319 1 2 0.1U_0402_25V6 EDP_TX0+ 5
    4 CPU_EDP_TX0+ EDP_TX0+ 5
    6
    BKOFF# 1 2 0_0402_5% 1 DISPOFF# CPU_EDP_TX0- C3320 1 2 0.1U_0402_25V6 EDP_TX0- EDP_TX0- 7 6
    44 BKOFF# 4 CPU_EDP_TX0- 7
    R3313 8
    EDP_TX1+ 9 8
    +3VS CPU_EDP_TX1+ C3321 1 2 0.1U_0402_25V6 EDP_TX1+ EDP_TX1- 10 9
    4 CPU_EDP_TX1+ 10
    11
    CPU_EDP_TX1- C3322 1 2 0.1U_0402_25V6 EDP_TX1- EDP_AUX 12 11
    4 CPU_EDP_TX1- 12
    2

    EDP_AUX# 13
    R3314 14 13
    1K_0402_5% DISPOFF# 15 14
    @ CPU_EDP_AUX# C3355 1 2 0.1U_0402_25V6 EDP_AUX# INVT_PWM 16 15
    C 4 CPU_EDP_AUX# CPU_EDP_HPD 16 C
    17
    4 CPU_EDP_HPD
    1

    R3316 1 2 0_0402_5% INVT_PWM CPU_EDP_AUX C3356 1 2 0.1U_0402_25V6 EDP_AUX 18 17


    4PCH_EDP_PWM 4 CPU_EDP_AUX +LCDVDD_CON 18
    19
    19
    1

    20
    21 20
    R3317 DMIC_CLK 21
    22
    100K_0402_5% 30 DMIC_CLK DMIC_DATA 22
    23
    30 DMIC_DATA 23
    +3VS_EDP 24
    2

    25 24
    26 25
    27 26
    USB20_P7_R 28 27
    USB20_N7_R 29 28 ME@
    30 29
    31 30
    32 G1
    G2
    EMI request close to connector Camera
    R3308 1 2 0_0402_5% DRAPH_FC5AF301-3181H

    DMIC_DATA DMIC_CLK DISPOFF# INVT_PWM


    L3301 @
    USB20_N7 1 2 USB20_N7_R
    9 USB20_N7 1 2
    1 1 1 1
    @ C10202 @ C3323 @ @
    C3324 C3325 USB20_P7 4 3 USB20_P7_R
    100P_0402_50V8J 100P_0402_50V8J 470P_0402_50V7K 470P_0402_50V7K 9 USB20_P7 4 3
    2 2 2 2 EXC24CH900U_4P

    R3309 1 2 0_0402_5%

    For EMI

    B B

    Touch Screen

    +5VS +3VS

    R101791 TS@ 2 0_0402_5%


    +5VS_TS
    close to connector JTS1
    R26 1 @ 2 0_0402_5% 1
    +5VS_TS USB20_P6_CONN R24 1 TS@ 2 0_0402_5% R28 2 TS@ 1 TS_RS 2 1
    44 EC_TS_ON 2
    AZ5725-01F.R7GR_DFN1006P2X2

    1 0_0402_5% 3
    USB20_N6_CONN C25 USB20_N6_CONN 4 3
    EMC_NS@ USB20_P6_CONN 4
    0.1u_0201_10V6K 5
    5
    1

    D2 D5104 EXC24CH900U_4P TS@ 6


    USB20_P6 4 3 USB20_P6_CONN 2 6 7
    1

    9 USB20_P6 4 3 GND1
    EMC_NS@

    8
    GND2
    USB20_N6 1 2 USB20_N6_CONN HIGHS_WS83061-S0171-HF
    9 USB20_N6 1 2
    ME@
    L15
    2
    2

    R23 1 TS@ 2 0_0402_5%


    AZ5515-02FPR7GR_DFN1006P3X
    EMC_NS@ For EMI
    For ESD
    A A

    Security Classification LC Future Center Secret Data Title

    Issued Date 2015/08/20 Deciphered Date 2016/08/20 eDP/CAMERA.


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS441/FS540
    Date: Wednesday, October 16, 2019 Sheet 33 of 61
    5 4 3 2 1
    5 4 3 2 1

    +5VS +5VS_HDMI_F +5VS_HDMI


    F1 use 1.1A
    F3401
    1 3 1 2

    S
    Q3404 1
    1.1A_8V_1206L110THYR C3409
    .1U_0402_10V6-K

    G
    2
    LP2301ALT1G_SOT23-3
    46 SUSP 2

    D D

    CPU_HDMI_TXP0 C3405 1 2 .1U_0402_10V6-K HDMI_TX0_DP_C HDMI_TX0_DP_C R3401 1 2 470_0402_5%


    4 CPU_HDMI_TXP0
    CPU_HDMI_TXN0 C3406 1 2 .1U_0402_10V6-K HDMI_TX0_DN_C HDMI_TX0_DN_C R3402 1 2 470_0402_5%
    4 CPU_HDMI_TXN0 +5VS_HDMI
    CPU_HDMI_TXP1 C3403 1 2 .1U_0402_10V6-K HDMI_TX1_DP_C HDMI_TX1_DP_C R3403 1 2 470_0402_5%
    4 CPU_HDMI_TXP1
    CPU_HDMI_TXN1 C3404 1 2 .1U_0402_10V6-K HDMI_TX1_DN_C HDMI_TX1_DN_C R3404 1 2 470_0402_5%
    4 CPU_HDMI_TXN1

    2
    1
    CPU_HDMI_TXP2 C3401 1 2 .1U_0402_10V6-K HDMI_TX2_DP_C HDMI_TX2_DP_C R3405 1 2 470_0402_5% RP3401
    4 CPU_HDMI_TXP2
    2.2K_0404_4P2R_5%
    CPU_HDMI_TXN2 C3402 1 2 .1U_0402_10V6-K HDMI_TX2_DN_C HDMI_TX2_DN_C R3406 1 2 470_0402_5% +5VS_HDMI
    4 CPU_HDMI_TXN2 JHDMI1

    3
    4
    CPU_HDMI_CLKP C3407 1 2 .1U_0402_10V6-K HDMI_CLK_DP_C HDMI_CLK_DP_C R3408 1 2 470_0402_5%
    4 CPU_HDMI_CLKP DDPB_CLK_U
    18 15
    CPU_HDMI_CLKN C3408 1 2 .1U_0402_10V6-K HDMI_CLK_DN_C HDMI_CLK_DN_C R3409 1 2 470_0402_5% +5V_Power SCL 16 DDPB_DATA_U
    4 CPU_HDMI_CLKN SDA
    HDMI_TX0_DP_CON 7
    TMDS_Data0+

    1
    D HDMI_TX0_DN_CON 9 13
    2 HDMI_TX1_DP_CON 4 TMDS_Data0- CEC 17
    +3VS Q3403 HDMI_TX1_DN_CON TMDS_Data1+ DDC/CEC_Ground HDMI_DET
    G 6 19
    L2N7002KWT1G_SOT323-3 HDMI_TX2_DP_CON 1 TMDS_Data1- Hot_Plug_Detect
    S HDMI_TX2_DN_CON 3 TMDS_Data2+

    3
    TMDS_Data2-
    1 2 8 14
    5 TMDS_Data0_Shield Utility
    R3411 TMDS_Data1_Shield
    2
    100K_0402_5% TMDS_Data2_Shield
    @
    20
    11 GND1 21
    HDMI_CLK_DP_CON 10 TMDS_Clock_Shield GND2 22
    HDMI_CLK_DN_CON 12 TMDS_Clock+ GND3 23
    TMDS_Clock- GND4

    ALLTO_C128AF-K1935-L
    C C
    ME@

    For EMC 2
    EMC_HDMI_R@
    1 0_0402_5% HDMI_CLK_DP_CON
    R3418

    L3404

    1
    HDMI_CLK_DP_C 4 3
    4 3 R3423
    220_0402_1% D3402
    HDMI_CLK_DN_C 1 2 HDMI_DET 1 1 10 9 HDMI_DET
    +3VS 1 2

    2
    EXC24CH900U_4P DDPB_CLK_U 2 2 9 8 DDPB_CLK_U
    EMC_HDMI_R@
    EMC_CMC@
    R3419 2 1 0_0402_5% HDMI_CLK_DN_CON DDPB_DATA_U 4 4 7 7 DDPB_DATA_U
    EMC_HDMI_R@
    2

    +5VS_HDMI 5 5 6 6 +5VS_HDMI
    R3407
    2

    Q3402 3 3
    G

    1M_0402_5% For EMC


    8
    1

    R3412 2 1 0_0402_5% HDMI_TX0_DP_CON


    CPU_HDMI_HPD 3 1 HDMI_DET EMC_HDMI_R@
    4 CPU_HDMI_HPD
    S

    AZ1045-04F_DFN2510P10E-10-9
    L3401 EMC_NS@
    2

    1
    L2N7002KWT1G_SOT323-3 HDMI_TX0_DP_C 4 3
    4 3 R3420
    R3410 D3401
    EMC_CMC@ 220_0402_1%
    20K_0402_5% HDMI_TX0_DN_C HDMI_CLK_DP_CON HDMI_CLK_DP_CON
    1 2 1 1 10 9
    B 1 2 B
    1

    2
    EXC24CH900U_4P HDMI_CLK_DN_CON 2 2 9 8 HDMI_CLK_DN_CON
    EMC_HDMI_R@
    R3413 2 1 0_0402_5% HDMI_TX0_DN_CON HDMI_TX0_DP_CON 4 4 7 7 HDMI_TX0_DP_CON
    EMC_HDMI_R@
    +3VS HDMI_TX0_DN_CON HDMI_TX0_DN_CON
    5 5 6 6

    3 3
    2

    8
    G

    R3414 2 1 0_0402_5% HDMI_TX1_DP_CON


    EMC_HDMI_R@
    AZ1045-04F_DFN2510P10E-10-9
    PCH_HDMI_DDC_DATA 1 6 DDPB_DATA_U L3402
    S

    4 PCH_HDMI_DDC_DATA EMC_NS@

    1
    D

    HDMI_TX1_DP_C 4 3
    4 3 EMC_CMC@ R3421
    Q3401A D3403
    220_0402_1%
    L2N7002KDW1T1G_SOT363-6 HDMI_TX1_DN_C 1 2 HDMI_TX1_DN_CON 1 1 10 9 HDMI_TX1_DN_CON
    1 2

    2
    5

    EXC24CH900U_4P HDMI_TX1_DP_CON 2 2 9 8 HDMI_TX1_DP_CON


    G

    EMC_HDMI_R@
    R3415 2 1 0_0402_5% HDMI_TX1_DN_CON HDMI_TX2_DN_CON 4 4 7 7 HDMI_TX2_DN_CON
    EMC_HDMI_R@
    PCH_HDMI_DDC_CLK 4 3 DDPB_CLK_U HDMI_TX2_DP_CON 5 5 6 6 HDMI_TX2_DP_CON
    S

    4 PCH_HDMI_DDC_CLK
    D

    3 3
    Q3401B
    L2N7002KDW1T1G_SOT363-6 R3416 2 1 0_0402_5% HDMI_TX2_DP_CON 8
    EMC_HDMI_R@

    L3403 AZ1045-04F_DFN2510P10E-10-9
    1

    HDMI_TX2_DP_C 4 3
    4 3 EMC_NS@
    EMC_CMC@ R3422
    220_0402_1%
    HDMI_TX2_DN_C 1 2
    1 2
    2

    EXC24CH900U_4P
    EMC_HDMI_R@
    A A
    R3417 2 1 0_0402_5% HDMI_TX2_DN_CON
    EMC_HDMI_R@

    Security Classification LC Future Center Secret Data Title

    Issued Date 2015/08/20 Deciphered Date 2016/08/20 HDMI_CONN


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS441/FS540
    Date: Wednesday, October 16, 2019 Sheet 34 of 61
    5 4 3 2 1
    A B C D E F G H

    1.Project name and info update----P1

    2.CE4432&CE4428&CE4429&CE4430&CE4431 Bom structure update-----P7

    3.RC730 Bom structure Update(origin MP@)----P7

    1
    4.R4684&r4685 33ohm change 22ohm----P8 1

    5.RC842 &RC3101 &Q4610 &Q4609 &RC834 BOM stucture change----P8;

    6.RH829 71.5K change 75K ----P8

    7.add RC3116 For PU reserve----P9

    8.add RC3117 75K PD For PU GPP_F23 according PDG P484 ----P10

    9.Board ID BOM stucture update----P10

    10.reseve RC3118 for PM_SLP_S0# 100k PU ----P11

    11.add VCCIO_SENSE&VSSIO_SENSE PU&PD Res(RC3114&RC3115) ----P13

    2 12.C66&C67&C68&C69&C10195&C10196&C10197&C10198 0402 change 0201----P38 2

    13.RD1712&RD1715&RD1713&RD1716&RD1742&RD1743&RD1744&RD1745 R-Short change R0402----P17

    14.RD1704&RD1705 36ohm change 33ohm----P17

    15.SPD link need confirm----P18

    15.GPU strap need confirm----P29

    17.RC3114&RC3115 0402 change 0201---P13 Id=3.2A

    18.PR1607 delete---P54

    19.add PC1614@ &PC1615&PC1120@&PC1121@---P54

    3 20.Load switch swap U13---P46 3

    21.add 17 connector Jbatt2---P52

    22.PR1106&PR1101&PR1107 change 0201；


    如下电容delete：PC6055；PC6053；PC6058
    PC6059；PC6054
    add :SB00000VT00+USM GPIO default low

    4 4

    Security Classification LC Future Center Secret Data Title


    Issued Date 2015/08/20 Deciphered Date 2016/08/20 Blank
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    B 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS441/FS540
    Date: Wednesday, October 16, 2019 Sheet 35 of 61
    A B C D E F G H
    5 4 3 2 1

    D D

    NOVO switch
    ON/OFF switch +3VL
    +3VL +3VALW

    2
    2

    2
    R3611
    R3606 R3608 100K_0402_5%
    100K_0402_5% 100K_0402_5% R3607 1 2
    @ 200_0402_1%

    1
    1

    ON/OFFBTN# R3612 1 2 ON/OFF


    30,45 ON/OFFBTN# ON/OFF 44

    AZ5123-01F.R7GR_DFN1006P2X2
    0_0402_5%
    NOVO# D3615 2
    44 NOVO#

    1
    1 NOVO_BTN# D25 J5 1 2 @
    NOVO_BTN# 30

    1
    ON/OFF 3 @ SHORT PADS 1
    BAT54CW_SOT323-3 C9
    0.1U_0402_25V6
    @ 2

    2
    J6 1 2 @
    EMC_NS@

    2
    SHORT PADS
    C C

    LID switch

    +3VL
    B B

    U3601
    R3602 1 2 0_0402_5% +VCC_LID 2
    VCC
    2
    R3603
    @ C3601 3 1 2 0_0402_5% LID_SW#
    OUTPUT LID_SW# 44
    .01U_0402_16V7-K
    1 1
    GND 2
    AH9247-W-7_SC59-3 C3602
    100P_0402_50V8J
    1
    EMC_NS@

    A A

    Security Classification LC Future Center Secret Data Title

    Issued Date 2015/08/20 Deciphered Date 2016/08/20 HALL Sensor


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS441/FS540
    Date: Wednesday, October 16, 2019 Sheet 36 of 61
    5 4 3 2 1
    5 4 3 2 1

    +3VS
    +3VS_SSD
    R3701
    1 2 Min 3A
    1/2W_0.01_1%_0603_50PPM/C

    0.1U_0402_10V7K
    4.7U_0603_6.3V6K
    1 1 1 1

    10U_0603_6.3V6M

    10U_0603_6.3V6M
    @

    D D
    2 2 2 2

    C3701

    C3702

    C3703

    C3704
    @ @
    @

    +3VS_SSD

    JSSD1

    1 2
    3 GND_1 3.3V_1 4

    0.1U_0402_10V7K
    5 GND_2 3.3V_2 6 1 1

    10U_0603_6.3V6M
    9 PCIE_PRX_DTX_N13 7 PERN3 N/C_2 8
    9 PCIE_PRX_DTX_P13 PERP3 N/C_3
    9 10
    0.22U_0402_10V6K 1 2 C3705 PCIE_PTX_C_DRX_N13 11 GND_3 DAS/DSS# 12
    9 PCIE_PTX_DRX_N13 1 2 C3706 PCIE_PTX_C_DRX_P13 13 PETN3 3.3V_3 14 2 2
    0.22U_0402_10V6K

    C10175

    C10176
    9 PCIE_PTX_DRX_P13 PETP3 3.3V_4
    C 15 16 C
    17 GND_4 3.3V_5 18
    9 PCIE_PRX_DTX_N14 PERN2 3.3V_6
    19 20 @
    9 PCIE_PRX_DTX_P14 PERP2 N/C_4
    21 22
    0.22U_0402_10V6K 1 2 C3707 PCIE_PTX_C_DRX_N14 23 GND_5 N/C_5 24
    9 PCIE_PTX_DRX_N14 PETN2 N/C_6

    1
    0.22U_0402_10V6K 1 2 C3708 PCIE_PTX_C_DRX_P14 25 26
    9 PCIE_PTX_DRX_P14 PETP2 N/C_7
    27 28 R3702
    29 GND_6 N/C_8 30
    9 PCIE_PRX_DTX_N15 PERN1 N/C_9 10K_0402_5%
    31 32
    9 PCIE_PRX_DTX_P15 33 PERP1 N/C_10 34 @

    2
    0.22U_0402_10V6K 1 2 C3709 PCIE_PTX_C_DRX_N15 35 GND_7 N/C_11 36
    9 PCIE_PTX_DRX_N15 PCIE_PTX_C_DRX_P15 PETN1 N/C_12
    0.22U_0402_10V6K 1 2 C3710 37 38 R3703 1 2 0_0402_5%
    9 PCIE_PTX_DRX_P15 PETP1 DEVSLP PCH_SATA_DEVSLP 9
    39 40
    41 GND_8 N/C_13 42
    9 PCIE_PRX_DTX_P16 43 PERN0/SATA-B+ N/C_14 44
    9 PCIE_PRX_DTX_N16 45 PERP0/SATA-B- N/C_15 46
    0.22U_0402_10V6K 1 2 C3711 PCIE_PTX_C_DRX_N16 47 GND_9 N/C_16 48
    9 PCIE_PTX_DRX_N16 PCIE_PTX_C_DRX_P16 PETN0/SATA-A- N/C_17 PLT_RST#_B
    9 PCIE_PTX_DRX_P16 0.22U_0402_10V6K 1 2 C3712 49 50
    PETP0/SATA-A+ PERST# SSD_CLKREQ_Q# PLT_RST#_B 11,26,40,44
    51 52 R3704 1 2 0_0402_5%
    GND_10 CLKREQ# SSD_CLKREQ# 10
    53 54 1
    10 CLK_PCIE_SSD# REFCLKN PEWAKE# TP3701
    55 56
    10 CLK_PCIE_SSD 57 REFCLKP N/C_18 58
    +3VS_SSD GND_11 N/C_19
    59 NC NC 60
    61 NC NC 62
    63 NC NC 64 +3VS_SSD
    1

    65 NC NC 66
    R3706 67 68
    100K_0402_5% SSD_DET 69 N/C_1 SUSCLK 70
    @ 71 PEDET 3.3V_7 72

    0.1U_0402_10V7K
    73 GND_12 3.3V_8 74
    1 1

    10U_0603_6.3V6M
    2

    75 GND_13 3.3V_9
    R3705 1 2 0_0402_5% GND_14
    9 SSD_PCIE_DET#
    77 76
    PEG1 PEG2 2 2

    C10177

    C10178
    1

    D Q3701 ARGOS_NASM0-S6701-TS40
    2 ME@ @
    B B
    G
    SSD_DET#
    L2N7002KWT1G_SOT323-3 S 0--SATA Change Symbol to SP070013X00 amy 0614
    3

    @
    1--PCIE

    A A

    Security Classification LC Future Center Secret Data Title

    Issued Date 2015/08/20 Deciphered Date 2016/08/20 NGFF_SSD_1


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS441/FS540
    Date: Wednesday, October 16, 2019 Sheet 37 of 61
    5 4 3 2 1
    5 4 3 2 1

    +5VS_HDD +5VS
    D R3801 SATA_PTX_DRX_P0 SATA_NRE@ RF3709 1 SATA_PTX_DRX_P0_R SATA_PTX_DRX_P0_CON D
    2 0_0201_5% SATA_NRE@ CF3735 1 2 0.01U_6.3V_K_X7R_0201
    9 SATA_PTX_DRX_P0
    2 1
    SATA_PTX_DRX_N0 SATA_NRE@ RF3710 1 2 0_0201_5% SATA_PTX_DRX_N0_R SATA_NRE@ CF3736 1 2 0.01U_6.3V_K_X7R_0201 SATA_PTX_DRX_N0_CON
    9 SATA_PTX_DRX_N0
    1 1 1 1 1 1 1/2W_0.01_1%_0603_50PPM/C
    1
    C3805 C3811 C3806 C3808 C3809 SATA_PRX_DTX_N0 SATA_NRE@ RF3711 1 2 0_0201_5% SATA_PRX_DTX_N0_R SATA_NRE@ CF3737 1 2 0.01U_6.3V_K_X7R_0201 SATA_PRX_DTX_N0_CON
    33P_0402_50V8J 33P_0402_50V8J .1U_0402_10V6-K 10U_0805_10V6K 10U_0805_10V6K C10183 C10184 9 SATA_PRX_DTX_N0
    RF_NS@ RF_NS@ @ 22U_10V_M_X5R_0603 22U_10V_M_X5R_0603 SATA_PRX_DTX_P0 SATA_NRE@ RF3712 1 2 0_0201_5% SATA_PRX_DTX_P0_R SATA_NRE@ CF3738 1 2 0.01U_6.3V_K_X7R_0201 SATA_PRX_DTX_P0_CON
    2 2 2 2 2 2 2 9 SATA_PRX_DTX_P0
    @ @

    For EMC

    +5VS_HDD JHDD1

    10 11
    +3VS SATA_PTX_DRX_P0_CON 9 10 GND1
    SATA_PTX_DRX_N0_CON 8 9 12
    7 8 GND2
    7

    2
    SATA_PRX_DTX_N0_CON 6
    R10184 +3VS SATA_PRX_DTX_P0_CON 5 6
    4.7K_0402_5% 4 5
    SATA_RE@ 3 4
    2 3

    1
    U4405 1 2
    C C
    @ C10192 1 2 0.1u_0201_10V6K 7 10 1
    EN VDD1 20
    VDD2 1 1
    SATA_PTX_DRX_P0 SATA_RE@ C66 1 2 0.01U_6.3V_K_X7R_0201 SATA_PTX_P0 1 C10194 HIGHS_FC5AF101-2931H
    9 SATA_PTX_DRX_P0 SATA_PTX_DRX_N0 SATA_RE@ C67 A_INP
    1 2 0.01U_6.3V_K_X7R_0201 SATA_PTX_N0 2 6 REXT C10193 0.01U_0201_10V6K ME@
    9 SATA_PTX_DRX_N0 A_INN REXT 16 DEW 0.1u_0201_10V6K @
    SATA_PRX_DTX_P0 SATA_RE@ C68 1 2 0.01U_6.3V_K_X7R_0201 SATA_PRX_P0 5 DEW 2 2
    9 SATA_PRX_DTX_P0 SATA_PRX_DTX_N0 SATA_RE@ C69 1 2 0.01U_6.3V_K_X7R_0201 SATA_PRX_N0 4 B_OUTP 9 A_DE
    9 SATA_PRX_DTX_N0 B_OUTN A_DE 8 B_DE
    A_EQ1 17 B_DE
    A_EQ2 18 A_EQ1 15 SATA_R_PTX_P0 SATA_RE@ C10195 1 2 0.01U_6.3V_K_X7R_0201 SATA_PTX_DRX_P0_CON
    B_EQ1 19 A_EQ2 A_OUTP 14 SATA_R_PTX_N0 SATA_RE@ C10196 1 2 0.01U_6.3V_K_X7R_0201 SATA_PTX_DRX_N0_CON
    B_EQ2 13 B_EQ1 A_OUTN
    B_EQ2 11 SATA_R_PRX_P0 SATA_RE@ C10198 1 2 0.01U_6.3V_K_X7R_0201 SATA_PRX_DTX_P0_CON
    3 B_INP 12 SATA_R_PRX_N0 SATA_RE@ C10197 1 2 0.01U_6.3V_K_X7R_0201 SATA_PRX_DTX_N0_CON
    21 GND1 B_INN
    EPAD
    PS8527CTQFN20GTR2A2_TQFN20_4X4

    +3VS

    B A_EQ1 B
    SATA_RE@ 1 R10209 2 1/20W_4.7K_5%_0201 @ 1 R10201 2 1/20W_4.7K_5%_0201

    SATA_RE@ 1 R10210 2 1/20W_4.7K_5%_0201 A_EQ2 @ 1 R10202 2 1/20W_4.7K_5%_0201

    SATA_RE@ 1 R10211 2 1/20W_4.7K_5%_0201 B_EQ1 @ 1 R10203 2 1/20W_4.7K_5%_0201

    SATA_RE@ 1 R10212 2 1/20W_4.7K_5%_0201 B_EQ2 @ 1 R10204 2 1/20W_4.7K_5%_0201

    1 R10213 2 4.99K_0402_1% REXT @ 1 R10205 2 1/20W_4.7K_5%_0201

    SATA_RE@ 1 R10214 2 1/20W_4.7K_5%_0201 DEW @ 1 R10206 2 1/20W_4.7K_5%_0201

    SATA_RE@ 1 R10215 2 1/20W_4.7K_5%_0201 SATA_RE@ A_DE 1 R10207 2 1/20W_4.7K_5%_0201

    SATA_RE@ 1 R10216 2 1/20W_4.7K_5%_0201 SATA_RE@ B_DE 1 R10208 2 1/20W_4.7K_5%_0201

    REXT：external res for output swiing adjustment


    it canbe left open or tie to GND,internally generated bias
    current be used and the output is as default swing setting;
    the pin canbe connected 4.99k to GND,the output swing
    willbe at the default value with Reference to the ex RES

    DEW:De-emphasis width setting for A&B

    A A

    Security Classification LC Future Center Secret Data Title

    Issued Date 2015/08/20 Deciphered Date 2016/08/20 SATA HDD CONN


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS441/FS540
    Date: Wednesday, October 16, 2019 Sheet 38 of 61
    5 4 3 2 1
    5 4 3 2 1

    SMSC thermal sensor Near GPU&VRAM


    placed near DIMM REMOTE1+ REMOTE2+
    Near CPU core

    1
    1
    C10157 Q3902 1 Q3901
    C3901

    C
    100P_0402_50V8J OPT@ 2 B 2 B
    2 LMBT3904WT1G_SOT323-3 100P_0402_50V8J LMBT3904WT1G_SOT323-3
    +3VS +3VS 2

    E
    OPT@
    D D
    REMOTE1- REMOTE2-

    3
    1
    C2401

    1
    0.1U_0402_10V7K R2404 R2403 +3VALW +3VALW Near CPU
    2 4.7K_0402_5% 4.7K_0402_5%
    U3901

    1
    R3903

    2
    R3904
    EC_SMB_CK2 13.7K_0402_1%
    1 1 10 13.7K_0402_1%
    VCC SCL EC_SMB_CK2 7,26,44 @
    @
    C2403 REMOTE1+ 2 9 EC_SMB_DA2
    EC_SMB_DA2 7,26,44

    2
    2200P_0402_50V7K DP1 SDA NTC_V1 NTC_V2 NTC_V2
    2 REMOTE1- 3 8 SEN_ALERT_N NTC_V1 44
    DN1 ALERT#

    1
    44
    REMOTE2+ 4 7 SEN_THERM_N R3905 R3906
    DP2 THERM#
    1
    REMOTE2- 5 6 100K_0402_1%_TSM0B104F4251RZ 100K_0402_1%_TSM0B104F4251RZ
    C2405 DN2 GND @ @

    2
    2200P_0402_50V7K
    2
    F75303M_MSOP10

    REMOTE+/-_R, REMOTE1+/-, REMOTE2+/-:


    Trace width/space:10/10 mil
    C C
    Trace length:<8" +3VALW
    Close to FAN connector

    1
    R3908
    13.7K_0402_1%

    2
    44 NTC_V3

    1
    R3907

    100K_0402_1%_TSM0B104F4251RZ

    2
    B B
    +5VS +5VS_FAN1
    FAN
    R3915
    1 2
    +5VLP +5VLP +5VLP
    1 1
    C3907 1/5W_0.01_1%_0402_100PPM/C C3908 @
    10U_0805_10V6K .1U_0402_10V6-K

    HW thermal sensor
    2

    2
    C3904 0.1U_0402_10V7K

    2 2
    1 @
    R3909 R3910
    @ @ 21.5K_0402_1%
    21.5K_0402_1%
    @
    2 +5VS_FAN1
    1

    U3902 @
    1 8 TMSNS1 R3911 1 @ 2 NTC_V1 JFAN1
    VCC TMSNS1 NTC_V1 44
    0_0402_5% 44 EC_FAN_PWM1 1
    2 7 PHYST1 R3912 1 @ 2 2 1
    GND RHYST1 44 EC_FAN_SPEED1 2
    10K_0402_5% 3
    3 6 TMSNS2 R3913 1 @ 2 NTC_V2 4 3
    54 EC_ON_R OT1 TMSNS2 NTC_V2 44 4
    0_0402_5%
    4 5 PHYST2 R3914 1 @ 2 5
    OT2 RHYST2 10K_0402_5% 6 GND1
    G718TM1U_SOT23-8 GND2

    over temperature threshold: HIGHS_WS33040-S0351-HF


    ME@
    RSET=3*RTMH
    A A
    92+/-30C
    Hysteresis temperature threshold.
    RHYST=(RSET*RTML)/(3*RTML-RSET)
    56+/-30C Title
    Security Classification LC Future Center Secret Data
    Issued Date 2016/08/16 Deciphered Date 2017/08/15 Thermal sensor/FAN CONN.
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS441/FS540
    Date: Wednesday, October 16, 2019 Sheet 39 of 61
    5 4 3 2 1
    A B C D E

    Mini-Express Card(WLAN/WiMAX)
    +3VALW +3V_WLAN

    R2236
    +3VALW
    1 2
    +3VALW
    1 1
    1/2W_0.01_1%_0603_50PPM/C

    1
    U4403 R2234
    R2225
    C10188
    75K_0402_5% 5 1 1 2 100U_1206_6.3V6M
    @ IN OUT

    2
    2 1/2W_0.01_1%_0603_50PPM/C @

    2
    GND
    @ 1
    WLAN_PWR_EN

    C2212
    0.01U_0402_25V7K
    4 3
    EN OCB

    1
    1
    Q2202 D R2229 SY6288C20AAC_SOT23-5 2@
    2 200K_0402_5% @
    4 CNVI_EN# G

    2
    R2226 S L2N7002KWT1G_SOT323-3
    @

    3
    75K_0402_5%
    @

    2
    @

    R2223 1 @ 2 0_0402_5%
    11 PM_SLP_WLAN#

    1
    R2233 1 2 0_0402_5% R2224
    44,46,54 SUSP#
    200K_0402_5%
    @ @
    +3V_WLAN

    2
    NC if use SUSP# +3V_WLAN

    RC832 1 2 10K_0402_5% PCH_WLAN_OFF#


    RC833 1 2 10K_0402_5% PCH_BT_OFF#

    +1.8VALW

    0.01U_0402_25V7K
    2 1 1 1 2

    10U_0603_6.3V6M
    .1U_0402_10V6-K
    RC3096 1 @ 2 20K_0402_5% CNVI_BRI_DT

    C10181

    C10179
    RC848 20K_0402_5% CNVI_RGI_DT
    1 2
    2 2 2

    C10180
    JWLAN1
    @
    1 2 @ @
    USB20_P10 3 GND1 3.3VAUX1 4
    9 USB20_P10 USB20_N10 USB_D+ 3.3VAUX2
    5 6 1
    9 USB20_N10 7 USB_D- LED1# 8 T4001
    CNV_WR_D1N 9 GND2 PCM_CLK/I2S_SCK 10 R4026 1 CNVI@ 2 0_0402_5%
    10 CNV_WR_D1N CNV_WR_D1P SDIO_CLK PCM_SYNC/I2S_WS CNVI_RF_RESET# 8
    11 12
    10 CNV_WR_D1P 13 SDIO_CMD PCM_IN/I2S_SD_IN 14 R4021 1 CNVI@ 2 0_0402_5%
    CNV_WR_D0N SDIO_DATA0 PCM_OUT/I2S_SD_OUT CNVI_MODEM_CLKREQ 8
    15 16 1
    10 CNV_WR_D0N CNV_WR_D0P 17 SDIO_DATA1 LED#2 18 T4002
    10 CNV_WR_D0P SDIO_DATA2 GND11
    19 20
    CNV_WR_CLKN 21 SDIO_DATA3 UART_WAKE# 22 R4022 1 CNVI@ 2 22_0402_5%
    10 CNV_WR_CLKN CNV_WR_CLKP 23 SDIO_WAKE# UART_RXD CNVI_BRI_RSP 8
    10 CNV_WR_CLKP SDIO_RESET#

    KEY E
    25 PIN24~PIN31 NC PIN 24
    27 26
    29 28
    31 30

    33 32
    GND3 UART_TXD CNVI_RGI_RSP_R CNVI_RGI_DT 8
    35 34 R4055 1 CNVI@ 2 22_0402_5%
    +3V_WLAN 9 PCIE_PTX_C_DRX_P9 37 PETP0 UART_CTS 36 CNVI_RGI_RSP 8
    +3VS 9 PCIE_PTX_C_DRX_N9 PETN0 UART_RTS EC_TX_RSVD CNVI_BRI_DT 8
    39 38 R4006 1 @ 2 0_0402_5%
    41 GND4 VENDOR_DEFINED1 40 EC_RX_RSVD R4007 1 @ 2 0_0402_5%
    WLAN 9 PCIE_PRX_DTX_P9
    2

    43 PERP0 VENDOR_DEFINED2 42
    9 PCIE_PRX_DTX_N9 PERN0 VENDOR_DEFINED3
    2

    R4066 45 44
    G

    10K_0402_5% 47 GND5 COEX3 46


    Q4008 10 CLK_PCIE_WLAN REFCLKP0 COEX2
    @ 49 48
    3 10 CLK_PCIE_WLAN# REFCLKN0 COEX1 SUSCLK_R 3
    51 50 R4010 1 2 0_0402_5%
    SUSCLK 10
    1

    3 1 WLAN_CLKREQ_Q# 53 GND6 SUSCLK 52 PLT_RST#_B


    10 WLAN_CLKREQ# CLKREQ0# PERST0# PLT_RST#_B 11,26,37,44
    S

    R4012 1 2 0_0402_5% PCIE_WAKE#_WLAN 55 54 BT_OFF# R4013 1 2 1K_0402_5%


    11 PCIE_WAKE# 57 PEWAKE0# W_DISABLE2# 56 WLAN_OFF# PCH_BT_OFF# 8
    L2N7002KWT1G_SOT323-3 @ R4014 1 2 0_0402_5%
    GND7 W_DISABLE1# PCH_WLAN_OFF# 8

    R4011 1 2 0_0402_5% CNV_WT_D1N 59 58 SMB_DATA_S3_R R4697 1 2 0_0402_5%


    10 CNV_WT_D1N CNV_WT_D1P RSRVD/PETP1 I2C_DATA SMB_CLK_S3_R EC_RX 41,44
    61 60 R4017 1 2 0_0402_5%
    10 CNV_WT_D1P 63 RSRVD/PETN1 I2C_CLK 62 EC_TX 41,44
    CNV_WT_D0N 65 GND8 ALERT# 64 R101831 @ 2 0_0402_5%
    10 CNV_WT_D0N CNV_WT_D0P RSRVD/PERP1 RSRVD CLKIN_XTAL_LCP 10
    67 66
    10 CNV_WT_D0P RERVD/PERN1 UIM_SWP/PERST1#

    1
    69 68
    CNV_WT_CLKN 71 GND9 UIM_POWER_SNK/CLKREQ1# 70 R4018
    10 CNV_WT_CLKN CNV_WT_CLKP 73 RSRVD/REFCLKP1 UIM_POWER_SRC/GPIO1/PEWAKE1# 72 100K_0402_5%
    10 CNV_WT_CLKP RSRVD/REFCLKN1 3.3VAUX3
    75 74
    GND10 3.3VAUX4

    2
    77 76
    GND15 GND14

    +3V_WLAN
    ARGOSY_NASE0-S6701-TSH4
    ME@

    0.01U_0402_25V7K
    1 1 1

    10U_0603_6.3V6M
    .1U_0402_10V6-K
    C10162

    C10163

    2 2 2 GPP_F6_CNV_RGI_DT:M.2 CNV Mode Select (Rising edge of RSMRST#)


    C10158 An external pull-up or pull-down is required.
    0 = Integrated CNVi enable.
    @ 1 = Integrated CNVi disable.

    4 4

    Security Classification LC Future Center Secret Data Title

    Issued Date 2016/12/14 Deciphered Date 2017/12/13 NGFF_WLAN


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS441/FS540
    Date: Wednesday, October 16, 2019 Sheet 40 of 61
    A B C D E
    5 4 3 2 1

    +3VALW
    D D

    1
    PR5924
    100K_0201_5%
    @
    PJ401
    PU1101

    2
    2 1 +3VALW_VIN 2 7 +3VALW_PG

    0.1U_0402_25V6

    10U_25V_M_X5R_0603

    10U_25V_M_X5R_0603
    V20B+ 2 1 IN1 PG +3VALW_PG 11

    EMC_NS@
    1 1 3 1 +3VALW_BST 1 2PC1115
    IN2 BS

    1
    4

    PC1101
    JUMP_43X79 IN3 .1U_0603_25V7K

    PC1102

    PC1103
    @ 5
    PL1101 @

    2
    2 2 6 LX1 15 PJ402
    14 GND1 LX2 16 +3VALW_LX 1 2 +3VALW_P
    2 1
    GND2 LX3 2 1 +3VALW

    1
    17
    GND3

    22UC_6.3VC_MC_X5RC_0603

    22UC_6.3VC_MC_X5RC_0603

    22UC_6.3VC_MC_X5RC_0603

    22UC_6.3VC_MC_X5RC_0603

    22UC_6.3VC_MC_X5RC_0603

    22UC_6.3VC_MC_X5RC_0603
    0_0402_5% PR1102 2.2UH_PCMB063T-2R2MS_8A_20%
    PR1103 100K_0402_5% PR1109 2.2_0805_5% JUMP_43X79
    +3VALW_EN PR1106 +3VALW_P
    1 2 1 2 9 11 EMC_NS@ 1 1 1 1 1 1
    31,41 EC_ON +3VALW_VIN 1 2 8 EN1 OUT

    PC1105

    PC1106

    PC1107

    PC1108

    PC1120

    PC1121
    1 2
    EN2 +3VALW_FB

    @
    10

    0.1U_0402_25V6
    1 2 +5VALW_EN 10K_0201_1% FF

    1
    26 EC_ON_R 12 PC1114 2 2 2 2 2 2

    PC1116
    TEST 100mA

    1
    0_0402_5% 13 1000P_0402_50V7K
    +3VLP 3VALW:

    2
    PR1104 PR1105 PR1107 LDO
    EMC_NS@

    2
    1/16W_82K_1%_0402 1/20W_1M_1%_0201
    SY8386BRHC_QFN16_2P5X2P5
    1
    TDC=6A
    PC1112
    2 OCP=8A

    2
    4.7U_0603_6.3V6K @ @
    2 1 2 1 2
    OVP=120%
    1

    PQ9710
    PC1111
    1000P_0402_25V7-K
    PR1108
    1K_0402_1% Fsw=600KHz
    2
    44 EC_USM SSM3K15AMFV_2-1L1B
    3
    1

    PR1120
    100K_0402_5%
    2

    +3VLP +3VL
    PJ404 @
    C C
    2 1
    2 1

    JUMP_43X39

    +3VALW

    1
    PR1605
    100K_0402_5%

    V20B+

    2
    @ PU1601
    PJ405
    2 1 +5V_VIN 2 7 ALW_PWRGD
    0.1U_0402_25V6

    10U_25V_M_X5R_0603

    10U_25V_M_X5R_0603

    2 1 IN1 PG ALW_PWRGD 11,55


    EMC_NS@

    1 1 3 1 +5VBS 1 2
    IN2 BS +5VALW
    1

    4 PC1605 1.5UH_PCMB063T-1R5MS_10A_20%
    PC1601

    IN3 PL1601 @

    SY8388CRHC_QFN16_2P5X2P5
    JUMP_43X79 0.1U_0603_25V7K PJ406
    PC1602

    PC1603

    5 +5VLX 1 2 +5VALW_P 2 1
    8A
    2

    LX1 2 1

    1
    2 2 15
    LX2

    22UC_6.3VC_MC_X5RC_0603

    22UC_6.3VC_MC_X5RC_0603

    22UC_6.3VC_MC_X5RC_0603

    22UC_6.3VC_MC_X5RC_0603

    22UC_6.3VC_MC_X5RC_0603

    22UC_6.3VC_MC_X5RC_0603
    16 PR1608
    6 LX3 2.2_0805_5% JUMP_43X79
    14 GND1
    17 GND2 EMC_NS@ 1 1 1 1 1 1

    PC1610

    PC1611

    PC1612

    PC1613

    PC1615

    PC1614
    1 2
    GND3 11 +5VALW_P
    OUT
    PR1601 10 PC1608 2 2 2 2 2 2
    +5VALW_EN 1 2 +5VALW1_P 9 FF 1000P_0402_50V7K 5VALW:

    2
    +5V_VIN 1 2 8 EN1 12
    0_0402_5% PR1603 EN2 LDO +5VLP EMC_NS@ TDC=8A
    100mA
    0.1U_0402_10V7K

    13 +5VVCC
    OCP=12A
    PC1604

    4.7U_0603_6.3V6M
    10K_0402_1% VCC
    1

    1 1
    1

    @ @
    PC1607 OVP=120%
    1M_0402_5%

    B @ B
    2

    Fsw=600KHz
    1M_0402_5%
    PR1602

    4.7U_0603_6.3V6K
    2 2
    PR1604
    2

    PC1609

    PC1606
    2

    +5VFB 1 2 1 2

    100P_0402_50V8J PR1609
    1K_0402_1%

    A A

    Security Classification LC Future Center Secret Data Title

    Issued Date 2015/08/20 Deciphered Date 2016/08/20 PWR_3VALW/5VALW


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S350 ADA
    Date: Wednesday, October 16, 2019 Sheet 40 of 44
    5 4 3 2 1
    5 4 3 2 1

    RIGHT SIDE USB3.0 PORT x1


    +USB_VCCA

    close to USB Conn


    +5VALW +USB_VCCA

    U4401 1

    2
    5 1
    IN OUT C10199 C4102
    1
    C4401 2 100U_1206_6.3V6M 1U_0402_10V6K

    1
    1U_0402_6.3V6K GND 2
    USB_OC1# @
    43,44 USB_ON# 4 3
    D 2 ENB OCB USB_OC1# 9 D

    SY6288D20AAC_SOT23-5

    Low Active 2A

    +USB_VCCA

    JUSB2

    USB30_TX_R_P2 9
    1 StdA_SSTX+
    USB30_TX_R_N2 8 VBUS
    USB20_P1_R 3 StdA_SSTX-
    7 D+
    USB20_N1_R 2 GND_DRAIN 10
    USB30_RX_R_P2 6 D- GND_2 11
    4 StdA_SSRX+ GND_3 12
    USB30_RX_R_N2 5 GND_1 GND_4 13
    StdA_SSRX- GND_5

    ALLTO_C19043-10905-L
    ME@

    R4109 1 @ 2 0_0402_5%

    C
    USB20_N1 4
    EXC24CH900U_4P
    3 USB20_N1_R
    For ESD C

    9 USB20_N1 4 3

    USB20_P1 1 2 USB20_P1_R EMC@ D4102


    9 USB20_P1 1 2 USB30_RX_R_N2 USB30_RX_R_N2
    10 1
    L4101 EMC@ NC1 Line-1
    USB30_RX_R_P2 9 2 USB30_RX_R_P2
    R4111 1 @ 2 0_0402_5% NC2 Line-2
    USB30_TX_R_N2 7 4 USB30_TX_R_N2
    NC3 Line-3
    USB30_TX_R_P2 6 5 USB30_TX_R_P2
    NC4 Line-4
    3
    GND1
    EMC 8
    GND2
    AZ1143-04F-R7G_DFN2510P10E10

    R4310 1 2 0_0402_5%

    L4308
    close to USB Conn
    USB30_RX_P2 1 2 USB30_RX_R_P2
    9 USB30_RX_P2 1 2

    USB30_RX_N2 4 3 USB30_RX_R_N2
    9 USB30_RX_N2 4 3
    EXC24CH900U_4P
    EMC_NS@ +USB_VCCA USB20_P1_R
    R4309 1 2 0_0402_5%
    USB20_N1_R

    AZ5725-01F.R7GR_DFN1006P2X2
    1

    2
    D4103

    1
    B D4101 B

    EMC_NS@

    2
    2

    3
    R4313 1 2 0_0402_5% AZ5515-02FPR7GR_DFN1006P3X
    EMC@
    L4307
    USB30_TX_P2 C4105 1 2 .1U_0402_10V6-K USB30_TX_C_P2 1 2 USB30_TX_R_P2
    9 USB30_TX_P2 1 2

    USB30_TX_N2 C4106 1 2 .1U_0402_10V6-K USB30_TX_C_N2 4 3 USB30_TX_R_N2


    9 USB30_TX_N2 4 3
    EXC24CH900U_4P
    EMC_NS@

    R4311 1 2 0_0402_5%

    A A

    Security Classification LC Future Center Secret Data Title

    Issued Date 2015/08/20 Deciphered Date 2016/08/20 USB3 PORT_LEFT


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS441/FS540
    Date: Wednesday, October 16, 2019 Sheet 41 of 61
    5 4 3 2 1
    5 4 3 2 1

    D D

    C C

    B B

    A A

    Security Classification LC Future Center Secret Data Title

    Issued Date 2015/08/20 Deciphered Date 2016/08/20 Blank


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    Size Document Number
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Rev
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS441/FS540
    Date: Wednesday, October 16, 2019 Sheet 42 of 61
    5 4 3 2 1
    A B C D E

    Right SIDE USB3.0 PORT +USB_VCCB

    +5VALW +USB_VCCB
    close to USB Conn
    U4301
    5 1
    IN OUT
    1
    C4301 2 1
    1U_0402_6.3V6K GND

    2
    4 3 USB_OC0# C10200
    2 41,44 USB_ON# ENB OCB USB_OC0# 9 100U_1206_6.3V6M C4304
    SY6288D20AAC_SOT23-5 2
    1U_0402_10V6K

    1
    @

    1 Low Active 2A 1

    R4314 1 @ 2 0_0402_5%

    EXC24CH900U_4P
    USB20_N3 4 3 USB20_N3_R
    9 USB20_N3 4 3

    USB20_P3 1 2 USB20_P3_R
    For ESD
    9 USB20_P3 1 2
    L4306 EMC@ EMC@
    D4310 +USB_VCCB
    R4312 1 @ 2 0_0402_5% USB30_RX_R_N1 10 1 USB30_RX_R_N1
    NC1 Line-1
    USB30_RX_R_P1 9 2 USB30_RX_R_P1 JUSB1
    NC2 Line-2
    USB30_TX_R_N1 7 4 USB30_TX_R_N1 USB30_TX_R_P1 9
    NC3 Line-3 1 StdA_SSTX+
    R4114 1 2 0_0402_5% USB30_TX_R_P1 6 5 USB30_TX_R_P1 USB30_TX_R_N1 8 VBUS
    NC4 Line-4 USB20_P3_R 3 StdA_SSTX-
    3 7 D+
    L4103 GND1 USB20_N3_R 2 GND_DRAIN 10
    USB30_RX_P1 1 2 USB30_RX_R_P1 8 USB30_RX_R_P1 6 D- GND_2 11
    9 USB30_RX_P1 1 2 GND2 StdA_SSRX+ GND_3
    4 12
    AZ1143-04F-R7G_DFN2510P10E10 USB30_RX_R_N1 5 GND_1 GND_4 13
    USB30_RX_N1 4 3 USB30_RX_R_N1 StdA_SSRX- GND_5
    9 USB30_RX_N1 4 3
    EXC24CH900U_4P
    EMC_NS@
    R4115 1 2 0_0402_5%
    close to USB Conn ALLTO_C19043-10905-L
    ME@

    +USB_VCCB USB20_P3_R

    USB20_N3_R
    2 2

    2
    R4112 1 2 0_0402_5% D4311

    EMC_NS@ D4309

    AZ5725-01F.R7GR_DFN1006P2X2
    1
    C4311
    L4102 AZ5515-02FPR7GR_DFN1006P3X
    USB30_TX_P1 1 2 .1U_0402_10V6-KUSB30_TX_C_P1 1 2 USB30_TX_R_P1
    9 USB30_TX_P1 1 2

    2
    C4312
    USB30_TX_N1 1 2 .1U_0402_10V6-KUSB30_TX_C_N1 4 3 USB30_TX_R_N1
    9 USB30_TX_N1

    3
    4 3
    EXC24CH900U_4P
    EMC_NS@ EMC@
    R4113 1 2 0_0402_5%

    +USB2_VCCA
    USB2.0 PORT x1
    +5VALW +USB2_VCCA
    1
    For ESD

    2
    U4402 C10201
    1 5 1 100U_1206_6.3V6M C10174
    3
    C10169 IN OUT 2 3
    1U_0402_10V6K
    close to USB Conn

    1
    1U_0402_6.3V6K 2
    GND @
    2 USB_ON# 4 3 USB_OC2#
    41,44 USB_ON# ENB OCB USB_OC2# 9
    SY6288D20AAC_SOT23-5
    +USB2_VCCA USB20_N4_R

    Low Active 2A USB20_P4_R


    +USB2_VCCA

    2
    AZ5725-01F.R7GR_DFN1006P2X2
    1

    D48
    AZC199-02S.R7G_SOT23-3
    1

    EMC@ 1 1
    C4995 C4996
    D5103 470P_0402_50V7K 1U_0603_25V6M
    @
    EMC_NS@ 2 2
    2

    R4691 1 @ 2 0_0402_5%
    @
    2

    JUSB3
    L4309 1
    USB20_P4 4 3 USB20_P4_R USB20_N4_R 2 VBUS
    9 USB20_P4

    1
    4 3 USB20_P4_R 3 D-
    4 D+ 5
    USB20_N4 1 2 USB20_N4_R GND GND1 6
    9 USB20_N4 1 2 GND2 7
    EXC24CH900U_4P GND3 8
    EMC@ GND4
    R4690 1 @ 2 0_0402_5%
    ALLTO_C107G1-10803-L
    ME@

    4 4

    Security Classification LC Future Center Secret Data Title

    Issued Date 2015/08/20 Deciphered Date 2016/08/20 USB3 Port_Right & USB2.0
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS441/FS540
    Date: Wednesday, October 16, 2019 Sheet 43 of 61
    A B C D E
    5 4 3 2 1

    +3VS

    +3VL_EC +3VL_EC
    RE4401
    1
    CE4410+3VS 1 2
    +3VL
    1

    1
    .1U_0402_10V6-K
    RE4404 RE4460 1/2W_0.01_1%_0603_50PPM/C +3VL_EC
    2 +3VL_EC_R
    100K_0402_5% 100K_0402_5%
    UMA@ OPTN16@ EC_PCHHOT# 1 2 SML1_ALERT# +3VL_EC
    @ SML1_ALERT# 7 LE4401 1 2 0_0603_5%
    2

    2
    EC_ID1 EC_ID0 0_0402_5% RE279 +3VS
    All capacitors close to EC 1 1

    .1U_0402_10V6-K

    .1U_0402_10V6-K
    1

    1
    Close EC Close EC +3VL_EC

    CE4408

    CE4409
    RE4406 RE4461 @ @ @
    100K_0402_5% 100K_0402_5% CE4401 1 1 1 1 1 1

    .1U_0402_10V6-K

    .1U_0402_10V6-K

    .1U_0402_10V6-K

    .1U_0402_10V6-K

    .1U_0402_10V6-K

    .1U_0402_10V6-K
    2 2

    CE4402

    CE4403

    CE4404

    CE4405

    CE4406

    CE4407
    OPT@ OPTN17@ 1 2 VCOREVCC

    2
    +3VL_EC_R EC_FAN_SPEED1 RE4411 2 1 10K_0402_5%
    2

    D 1/2W_0.01_1%_0603_50PPM/C 2 2 2 2 2 2 D
    .1U_0402_10V6-K LE4402 1 2 0_0603_5% EC_AGND EC_FAN_PWM1 RE4413 1 @ 2 10K_0402_5%
    R4615
    1
    RE4408 2 0_0402_5% LPC_FRAME# RE4414 1 2 10K_0402_5%

    1
    @

    CPU_VR_READY RE4423 1 2 10K_0402_5%


    EC_AGND
    minimum trace width 12 mil EC_TP_ON RE4415 1 @ 2 10K_0402_5%

    114
    121
    127
    12

    11

    26
    50
    92

    74
    3
    UE4401
    ENBKL RE4425 1 @ 2 100K_0402_5%

    VSTBY1
    VSTBY2
    VSTBY3
    VSTBY4
    VSTBY5
    VCC

    VSTBY(PLL)

    AVCC
    VBAT

    VCORE
    26 WRST# KBRST#_EC PWR_LED1#
    RE4416 2 1 0_0402_5% 4 24
    7 KBRST# SERIRQ_EC KBRST#/GPB6 PWM0/GPA0 PWR_LED# PWR_LED1# 30
    RE4417 2 1 0_0402_5% 5 25 For PMIC
    +3VL_EC 7 SERIRQ SERIRQ/GPM6 PWM1/GPA1 PWR_LED# 45
    RE4421 1 2 0_0402_5% LPC_FRAME#_EC 6 28 BATT_LOW_LED#
    +3VALW +3VL_EC
    7 LPC_FRAME# LPC_AD3_EC 7 LFRAME#/GPM5 PWM2/GPA2 29 BATT_CHG_LED# BATT_LOW_LED# 45
    DE4401 7 LPC_AD3_EC BATT_CHG_LED# 45
    1 2 LPC_AD2_EC 8 LAD3/GPM3 PWM3/GPA3 30 EC_FAN_PWM1
    7 LPC_AD2_EC LAD2/GPM2 PWM PWM4/GPA4 EC_FAN_PWM1 39
    LPC_AD1_EC 9 31 PWR_LED2#

    1
    7 LPC_AD1_EC LPC_AD0_EC 10 LAD1/GPM1 PWM5/GPA5 32 EC_BEEP PWR_LED2# 30
    LRB751V-40T1G_SOD323-2 7 LPC_AD0_EC CLK_PCI_EC LAD0/GPM0 PWM6/SSCK/GPA6 EC_VCCST_EN EC_BEEP 30 RE4427 RE4428
    13 LPC 34
    @1 2 7 CLK_PCI_EC 14 LPCCLK/GPM4 PWM7/RIG1#/GPA7 120 FP_PWR_EN EC_VCCST_EN 13 0_0402_5% 0_0402_5%
    WRST#
    EC_SMI# WRST# TMRI0/GPC4 FP_PWR_EN 45 @
    100K_0402_5% RE4422 15 124 SUSP#
    1U_0402_6.3V6K

    9 EC_SMI# EC_RX ECSMI#/GPD4 TMRI1/GPC6 SUSP# 40,46,54


    16 RPE4401

    2
    1 40,41 EC_RX PWUREQ#/BBO/SMCLK2ALT/GPC7
    EC_TX 17 66 NTC_V1 EC_SMB_DA3 1 4
    CE4411

    40,41 EC_TX LPCPD#/GPE6 ADC0/GPI0 NTC_V1 39


    PLT_RST#_B 22 67 NTC_V2 EC_SMB_CK3 2 3
    11,26,37,40 PLT_RST#_B LPCRST#/GPD2 ADC1/GPI1 NTC_V2 39
    EC_SCI# 23 68 BATT_TEMP
    2 4 EC_SCI# EC_RTCRST#_ON ECSCI#/GPD3 ADC2/GPI2 NTC_V3 BATT_TEMP 52,53
    126 ADC 69 NTC_V3 39 2.2K_0404_4P2R_5%
    GA20/GPB5 ADC3/GPI3 70 CPU_VR_READY
    IT8586E/AX ADC4/GPI4
    ADC5/DCD1#/GPI5
    71
    72 RE4426 1
    ADP_I
    2 0_0402_5%
    CPU_VR_READY
    ADP_I 53
    58

    ADC6/DSR1#/GPI6 PSYS 53,58

    45 KSI[0..7]
    KSI[0..7] KSI0 58
    KSI0/STB#
    LQFP-128L ADC7/CTS1#/GPI7
    73 SYS_PWROK
    SYS_PWROK 11
    +3VL_EC
    KSI1 59 78 EC_TS_ON
    KSI1/AFD# DAC2/TACH0B/GPJ2 EC_TS_ON 33
    KSO[0..17] KSI2 60 79 EC_TP_ON
    45 KSO[0..17] KSI2/INIT# DAC3/TACH1B/GPJ3 H_PROCHOT#_EC EC_TP_ON 45
    C KSI3 61 DAC 80 C
    KSI4 62 KSI3/SLIN# DAC4/DCD0#/GPJ4 81 ENBKL R4401 2 1 0_0402_5% EC_ON RE4430 2 1 100K_0402_5%
    KSI4 DAC5/RIG0#/GPJ5 PCH_ENBKL 4,33
    KSI5 63
    KSI6 64 KSI5 85 EC_ON_GPIO 1 RE4429 2 0_0402_5% EC_ON RE4458 2 @ 1 100K_0402_5%
    65 KSI6 PS2CLK0/TMB0/CEC/GPF0 86 PBTN_OUT# EC_ON 54,55
    KSI7
    KSI7 PS2DAT0/TMB1/GPF1 EC_SMB_CK3 PBTN_OUT# 11
    KSO0 36 87 SUSP# RE4432 1 2 100K_0402_5%
    37 KSO0/PD0 GPF2 88 EC_SMB_DA3 EC_SMB_CK3 55
    KSO1 Int. K/B PS2
    KSO1/PD1 GPF3 EC_SMB_DA3 55
    KSO2 38 89 2 1
    RE4586 0_0201_5% SYSON RE4433 1 2 100K_0402_5%
    KSO3 39 KSO2/PD2 Matrix PS2CLK2/GPF4 90
    DELINK_R 45
    KSO3/PD3 PS2DAT2/GPF5 GPIO_AL0 45 EC_VCCST_EN
    KSO4 40 RE4434 1 @ 2 100K_0402_5%
    KSO5 41 KSO4/PD4 96 CAPS_LED#
    +3VS KSO5/PD5 EXTERNAL SERIAL FLASH GPH3/ID3 CAPS_LED# 45
    2.2K_0404_4P2R_5% KSO6 42 97 PCH_PWR_EN EC_VCCIO_EN RE4435 1 @ 2 100K_0402_5%
    EC_SMB_CK2 KSO6/PD6 GPH4/ID4 EC_VCCST_PWRGD PCH_PWR_EN 55
    2 3 KSO7 43 98 R4402 1
    EC_SMB_DA2 KSO7/PD7 GPH5/ID5 PCH_PWROK EC_VCCST_PWRGD 11 EC_VCCST_PWRGD OD output ENBKL 2 100K_0402_5%
    1 4 KSO8 44 99
    KSO8/ACK# GPH6/ID6 PCH_PWROK 11
    KSO9 45
    RPE4403 KSO10 46 KSO9/BUSY 101 EC_SPI_CS0# RE4446 2 1 0_0402_5% SPI_CS0#
    KSO11 51 KSO10/PE NC1 102 EC_SPI_SI RE4448 2 1 0_0402_5% SPI_SI SPI_CS0# 7
    +3VL_EC 52 KSO11/ERR# NC2 103 EC_SPI_SO 2 1 SPI_SO SPI_SI 7 Add to fix Reset&PWRGD test fail issue
    KSO12 SPI Flash ROM RE4450 0_0402_5%
    KSO12/SLCT NC3 EC_SPI_CLK SPI_CLK SPI_SO 7 VDDQ_PGOOD
    RPE4402 KSO13 53 105 RE4452 1 2 49.9_0402_1% CE4412 1 2 .01U_0402_16V7-K
    2 3 EC_SMB_DA1 KSO14 54 KSO13 NC4 SPI_CLK 7
    1 4 EC_SMB_CK1 KSO15 55 KSO14 PM_SLP_S4# CE4413 1 2 1000P_0402_50V7K EMC_NS@
    KSO16 56 KSO15 108 ACIN#
    2.2K_0404_4P2R_5% KSO17 57 KSO16/SMOSI/GPC3 AC_IN# 109 LID_SW#
    KSO17/SMISO/GPC5 UART LID_SW# LID_SW# 36 PM_SLP_S3# CE4414 1 2 1000P_0402_50V7K EMC_NS@

    36 ON/OFF ON/OFF 110 82 EC_USM


    EC_USM 54 SYSON CE4415 1 2 1000P_0402_50V7K EMC_NS@
    EC_ON RE4436 2 @ 1 0_0402_5% 111 PWRSW# EGAD/GPE1 83 VDDQ_PGOOD
    XLP_OUT SM Bus EGCS#/GPE2 VDDQ_PGOOD 55
    EC_SMB_CK1 115 84 EC_VPP_PWREN NOVO# CE4416 1 2 .01U_0402_16V7-K
    52,53 EC_SMB_CK1 EC_SMB_DA1 SMCLK1/GPC1 EGCLK/GPE3 EC_VPP_PWREN 55
    Charger & Battery 116
    52,53 EC_SMB_DA1 H_PECI 2 43_0402_5% PECI_EC SMDAT1/GPC2 EC_MUTE#
    4 H_PECI RE44371 117 GPIO 77
    EC_MUTE# 30
    EC_ID1 118 SMCLK2/PECI/GPF6 GPJ1 100 GPG2 PECI_EC CE4417 2 1 47P_0402_50V8J EMC_NS@
    EC_SMB_CK2 94 SMDAT2/PECIRQT#/GPF7 SSCE0#/GPG2 106 BKOFF#
    7,26,39 EC_SMB_CK2 EC_SMB_DA2 CRX1/SIN1/SMCLK3/GPH1/ID1 SSCE1#/GPG0 ME_FLASH BKOFF# 33 BATT_TEMP CE4418
    GPU SENSOR Thermal 95 104 1 2 100P_0402_50V8J EMC_NS@
    7,26,39 EC_SMB_DA2 CTX1/SOUT1/GPH2/SMDAT3/ID2 DSR0#/GPG6 ME_FLASH 8
    107 SYSON
    DTR1#/SBUSY/GPG1/ID7 119 EC_RSMRST#_R RE4459 1 SYSON
    21K_0402_5%55 EC_RSMRST#
    +3VL ACIN# CE4419 1 2 100P_0402_50V8J EMC_NS@
    CRX0/GPC0 EC_VCCIO_EN EC_RSMRST# 11
    123
    CTX0/TMA0/GPB2 PM_SLP_S3# EC_VCCIO_EN 13
    RE4438 1 2 0_0402_5% 112 18
    VSTBY0 RI1#/GPD0 PM_SLP_S4# PM_SLP_S3# 11 CE4420
    RE4439 1 2 0_0402_5% 125 21 PM_SLP_S4# 11 ON/OFF 1 2 @ 1U_0402_6.3V6K
    B 58 EC_VR_ON GPE4 RI2#/GPD1 B
    WAKE UP 76 NOVO# NOVO# 36
    +5VALW TACH2/GPJ0 48 EC_FAN_SPEED1
    TACH1A/TMA1/GPD7 EC_FAN_SPEED1 39 PLT_RST#_B CE4421 2 1 220P_0402_50V7K EMC_NS@
    47 2 @ RE45871 0_0201_5%
    USB_ON# 33 TACH0A/GPD6 19 FP_RESETN_R 45
    USB_ON# 41,43 USB_ON# EC_PCHHOT# GINT/CTS0#/GPD5 L80HLAT/BAO/GPE0 NUM_LED# 45
    RE4440 2 1 100K_0402_5% 35 GPIO 20 GPIO_SCL 45
    RTS1#/GPE5 L80LLAT/GPE7
    EC_ID0 93
    CLKRUN#/GPH0/ID0 For ESD
    +3VL
    EMC Request
    RE4442 1 @ 2 10K_0402_5% BKOFF# VGA_AC_DET 2
    26 VGA_AC_DET AC_PRESENT CK32KE/GPJ7
    128 Clock EMC_NS@ EMC_NS@
    11 AC_PRESENT CK32K/GPJ6
    RE4443 2 1 100K_0402_5% LID_SW# CLK_PCI_EC RE61 1 2 10_0402_5% CE23 1 2 10P_0402_50V8J

    RE4445
    1 2 10K_0402_5% BKOFF#
    AVSS
    VSS1

    VSS2
    VSS3
    VSS4
    VSS5
    VSS6

    RE4447 1 2 0_0402_5% H_PROCHOT# 4,55


    53,58 VR_HOT#
    IT8586E-AX_LQFP128_14X14

    1
    113
    122
    27
    49
    91

    75
    1

    RE4451 2
    100_0402_5% CE4423
    47P_0402_50V8J
    1

    2
    EC_AGND EMC_NS@

    1
    QE4402 D
    H_PROCHOT#_EC 2
    G
    +3VL
    S L2N7002KWT1G_SOT323-3

    3
    +3VL_EC
    2

    RE4456 1 2 10K_0402_5% GPG2 RE4453


    EC_RTC_RST# 10
    100K_0402_5%
    1

    RE4457 1 @ 2 10K_0402_5% GPG2 QE4401 D


    EC_RTCRST#_ON 2
    1

    ACIN# RE4454 1 2 0_0402_5%


    G
    1

    A A

    RE4455 S L2N7002KWT1G_SOT323-3
    1

    D QE4403
    3

    when mirror, GPG2 pull high 2


    10K_0402_5%
    ACIN 53
    when no mirror, GPG2 pull low @ G
    2

    S
    L2N7002KWT1G_SOT323-3
    3

    Security Classification LC Future Center Secret Data Title

    Issued Date 2015/08/20 Deciphered Date 2016/08/20 EC_ITE8586


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS441/FS540
    Date: Wednesday, October 16, 2019 Sheet 44 of 61
    5 4 3 2 1
    5 4 3 2 1

    K/B Connector TP/B Connector


    +3VS TP_PWR
    R4509
    JKB1
    1 2
    R84 1 2 0_0402_5% PWR_CAPS_LED 32 33
    +3VALW CAPS_LED# CAPS_LED#_R 32 GND1
    R275 1 2 200_0402_1% 31 34 1/2W_0.01_1%_0603_50PPM/C
    KSI[0..7] 44 CAPS_LED# 31 GND2
    KSO15 30 1
    KSI[0..7] 44 30
    KSO10 29 C4509
    KSO[0..17] KSO11 28 29 .1U_0402_10V6-K
    KSO[0..17] 44 28
    KSO14 27
    KSO13 26 27 2
    KSO12 25 26
    KSO3 24 25
    KSO6 23 24
    KSO8 22 23
    KSO7 21 22
    KSO4 20 21
    D
    KSO2 19 20 D
    KSI0 18 19
    KSO1
    KSO5
    17
    16
    18
    17
    close to Conn
    KSI3 15 16
    KSI2 14 15
    KSO0 13 14 TP_I2C_SCL0
    The KB pin (PWR_LED#)only for S145IWL KB, 13 TP_I2C_SDA0
    KSI5 12 JTP1
    100P_0402_50V8J 1 2 C4503 PWR_CAPS_LED IML 14&15&17 NC PIN；R281&R280&R10174 需要 KSI4 11 12 EC_TP_ON_R 1
    change bom stucture :common design 14&15; 11 1

    3
    EMC_NS@ KSO9 10 TP_INT# 2
    KB15or17@------stuff KSI6 9 10 3 2 DT4501
    KSI7 8 9 TP_I2C_SDA0 4 3
    100P_0402_50V8J 1 2 C4504 CAPS_LED# KSI1 7 8 TP_I2C_SCL0 5 4 EMC_NS@
    EMC_NS@ KSO16 R281 1 2 0_0402_5% KSO16_R 6 7 6 5
    KSO17_R 6 TP_PWR 6
    KSO17 R280 1 2 0_0402_5% 5
    NUM_LED# R101741 2 200_0402_1% NUM_LED#_R 4 5 7
    NUM_LED#_R 44 NUM_LED# PWR_LED# 4 GND1
    100P_0201_25V8J 1 2 C118 R101751 KB145@ 2 200_0402_1% 3 8
    44 PWR_LED# 3 GND2
    EMC_15_NS@ 30,36 ON/OFFBTN# ON/OFFBTN# R10218 1 KB145@ 2 0_0402_5% 2
    R10219 1 KB145@ 2 0_0402_5% 1 2 HIGHS_FC5AF061-2931H
    1
    ME@
    AZC199-02S.R7G_SOT23-3

    1
    KSO15 R10220 1 KB350@ 2 0_0402_5% KSO15_R HIGHS_FC8AR321-3160-1H For ESD
    KSI1 R10221 1 KB350@ 2 0_0402_5% KSI1_R ME@

    For ESD
    CAPS_LED# NUM_LED#_R PWR_LED#
    JTP2
    R4510 1 2 0_0402_5% EC_TP_ON_R 1
    44 EC_TP_ON TP_INT# 1
    R4511 1 2 0_0402_5% 2
    8 PCH_TP_INT# 2
    3
    3
    1

    4
    D4501 D23 D46 5 4
    1

    AZ5123-01F.R7GR_DFN1006P2X2 AZ5123-01F.R7GR_DFN1006P2X2 AZ5123-01F.R7GR_DFN1006P2X2 TP_I2C_SDA0 6 5


    8 TP_I2C_SDA0 TP_I2C_SCL0 6
    EMC_NS@ EMC_15_NS@ EMC_NS@ 7
    8 TP_I2C_SCL0 8 7
    TP_PWR 8
    2

    1 1 9
    C C4511 10 GND1 C
    C4510
    2

    GND2
    100P_0402_50V8J 100P_0402_50V8J

    EMC@ 2 2 EMC@ HIGHS_FC5AF081-2931H


    ME@

    BATT_LOW_LED, Finger Print Connector


    Low ,Amber,if over 90%,ChG_LED(White)
    PWM +3VL +3VALW
    FP@ FP_PWR
    BATT_LOW_LED# LED1 1 2 R4514 1 2 470_0402_5% R101821 2 0_0402_5% @
    44 BATT_LOW_LED# +3VALW
    R10217 1 2 0_0402_5%
    L-C192JFCT-LCFC_SUPER_AMBER
    1

    L4310
    USB20_N2 4 3 USB20_N2_CONN R10180 1 @ 2 0_0402_5%
    1

    9 USB20_N2 4 3
    D4504
    AZ5123-01F.R7GR_DFN1006P2X2 Q4613
    EMC_NS@ USB20_P2 1 2 USB20_P2_CONN RI4617
    9 USB20_P2 1 2 +3VL 3

    D
    1 1 FP@ 2
    2

    EXC24CH900U_4P
    EMC_NS@ 1/2W_0.01_+-1%_0603_50PPM/C 1 C2061
    2

    1
    R101811 2 0_0402_5%

    G
    2
    FP@ RI3803 LP2301ALT1G_SOT-23-3 0.1u_0201_10V6K
    FP@ 100K_0201_5% FP@ FP@
    2
    RI3804 RI3805

    2
    1 2 1@ 2 FP_PWR_EN

    10K_0201_5% 1 0_0201_5%
    FP@ FP@

    1
    BATT_CHG_LED GPIO QI3802 CI3802
    0.1U_6.3V_K_X5R_0201
    2
    BATT_CHG_LED# 44
    44 BATT_CHG_LED# LED2 1 2 R4516 1 2 1.5K_0402_5% +5VALW FP_PWR_EN 2
    FP_PWR +3VS FP@
    B B

    1
    L-C192WDT-LCFC_WHITE SSM3K15AMFV_2-1L1B

    3
    RC3123 @ RI3806
    1

    1 2 DELINK 100K_0201_5%
    1

    1/20W_2.2K_5%_0201 DELINK_R FP@


    D4506

    2
    2 RC3124 1 GPIO_AL0
    AZ5725-01F.R7GR_DFN1006P2X2
    1
    @ 1/20W_4.7K_5%_0201
    EMC_NS@
    RI4618
    GPIO_SCL
    2

    2 RC3125 1 100K_0201_5%
    @ 1/20W_4.7K_5%_0201 FP@
    2

    2 RC3126 1 FP_RESETN_R
    1

    @ 1/20W_4.7K_5%_0201
    RC4528
    1/20W_4.7K_5%_0201
    @
    2

    PWR_LED# LED3 1 2 R4672 1 2 470_0402_5%


    44 PWR_LED# +3VALW
    L-C192WDT-LCFC_WHITE
    ME@
    1

    D16 FP_PWR HIGHS_FC5AF081-2931H


    1

    AZ5725-01F.R7GR_DFN1006P2X2 10
    EMC_NS@ 9 GND2
    GND1
    8
    USB20_N2_CONN 8
    2

    7
    USB20_P2_CONN 6 7
    2

    5 6
    44 DELINK_R 5
    RC4522 1 @ 2 0_0201_5% DELINK_R 4
    close to Conn 10
    44
    DELINK
    GPIO_AL0
    GPIO_AL0 RC4523 1 FP@
    FP_RESETNRC4524 1 FP@
    2 0_0201_5% GPIO_AL0_R
    2 0_0201_5% FP_RESETN_R
    3
    2
    4
    3
    11 FP_RESETN GPIO_SCL RC4525 1 @ 2
    2 0_0201_5% GPIO_SCL_R 1
    For ESD 44 GPIO_SCL 1
    USB20_N2_CONN 44 FP_RESETN_R
    JFP2
    USB20_P2_CONN

    EMC_FP@
    1

    D5110 D4135
    DELINK_R 10 1 DELINK_R
    NC1 Line-1
    LED Stute LED Behavior GPIO_AL0_R 9 2 GPIO_AL0_R
    White_on(battery：21%~100%) NC2 Line-2
    A
    System on FP_RESETN_R7 4 FP_RESETN_R A
    Amber_on(battery：0%~20%) NC3 Line-3
    Standby White_on(battery：21%~100%) GPIO_SCL_R
    6 5 GPIO_SCL_R
    Power Button
    3

    NC4 Line-4
    LID closed Amber_Blink_3S(battery：0%~20%)
    3 AZ5515-02FPR7GR_DFN1006P3X
    OFF GND1
    System off EMC_FP@
    8
    OFF GND2
    Battery only
    Charging AZ1143-04F-R7G_DFN2510P10E10
    Amber_on(battery：1%~90%)
    Charging
    White_on(battery：91%~100%)

    Security Classification LC Future Center Secret Data Title

    Issued Date 2015/08/20 Deciphered Date 2016/08/20 KB/TP_CONN.


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS441/FS540
    Date: Wednesday, October 16, 2019 Sheet 45 of 61
    5 4 3 2 1
    A B C D E

    Load Switch +3VS, C173 --> 2.74ms


    +5VALW To +5VS +5VS, C176 --> 2.03ms
    +3VALW To +3VS VIN 5V and 3.3V (VBIAS=5V), IMAX(per channel)=6A, Rds=16mohm +1.8VALW
    Q4601
    +1.8VS

    Need Short +5VS LP2301ALT1G_SOT23-3


    +5VALW
    0.6A
    G2898KD1U_TDFN14P_2X3

    D
    J12 @ 3 1
    +5VS_LS

    0.1U_0402_10V7K
    1 14 1 2

    0.1U_0402_10V7K
    2 IN1_1 OUT1_2 13 1 2
    IN1_2 OUT1_1 1 1

    C4609
    JUMP_43X79

    G
    1 1

    C4610
    2

    0.1U_0402_10V7K

    0.1U_0402_10V7K
    1 C177 C3916 5VSON 3 12 C176 1 2 1
    EN1 CT1 1 1
    1U_0402_6.3V6K .01U_0402_16V7-K 1000P_0201_50V7-K C174 C3917
    EMC@ 4 11 0.1u_0201_10V6K 0.01U_0201_10V6K 2 2
    2 2 +5VALW VBIAS GND 1 1

    C4611
    @ EMC@ R4603

    C4612
    +3VALW 3VSON 5 10 C173 1 2 2 2 SUSP 1 2
    EN2 CT2 2200P_0402_25V7-K +3VS
    6 9 J11 @ 0_0402_5% 2 2

    1
    7 IN2_1 OUT2_2 8 +3VS_LS 1 2
    1 IN2_2 OUT2_1 1 2 R4604 1
    C178 @ @
    1 @ 470K_0402_5%
    1U_0402_6.3V6K 15 JUMP_43X79 C175 C4613
    @ Thermal Pad 0.1u_0201_10V6K 0.1U_0402_10V7K
    2 U13
    Need Short 2

    2
    @
    2

    +5VLP

    R64

    1
    SUSP#1 2 0_0402_5% 3VSON
    44 SUSP#
    R4605
    100K_0402_5%

    2
    R27
    1 2 0_0402_5% 5VSON SUSP
    34 SUSP
    1 1

    L2N7002KWT1G_SOT323-3
    2 2
    C180 C179
    1U_0402_6.3V6K 1U_0402_6.3V6K

    1
    2 2 Q4602 D
    2
    40,44,54 SUSP# G

    3
    EMC demand +3VALW +3VALW_PCH

    +3VL Q4625
    +5VS LP2301ALT1G_SOT-23-3

    1
    +3VALW +3VALW_PCH

    D
    R11043 3 1
    @ 100K_0201_5%

    R4323

    G
    2

    2
    1 2
    @
    1

    0.1U_0402_10V7K
    PC6173 PC6175 PC6177 +3VALW PCH_PWR_EN# 1 2 R11042 PCH_PWR_EN#_R
    PC6174 PC6176 PC6178 1/3W_0.005_+-1%_0805 @ 10K_0201_5%
    1000P_0402_25V7-K

    1000P_0402_25V7-K

    1000P_0402_25V7-K
    0.1U_0402_25V7-K

    0.1U_0402_25V7-K

    0.1U_0402_25V7-K

    1
    2

    1
    1 1
    C4622
    @ @ @ @ @ @ C4621 C4624 R11060 1

    1
    22U_0603_6.3V6-M .01U_0402_16V7-K @ 100K_0201_5% CC4238
    @ EMC@ 2 Q4626 0.1U_6.3V_K_X5R_0201
    3 2 2 SSM3K15AMFV_2-1L1B 3

    2
    @ 2 @ 2
    44 PCH_PWR_EN @

    3
    For DisCharge +5VALW +VCCSTG +3VALW_PCH DISCHARGER
    Reserve for VCCSGT discharge
    1

    +0.6VS +2.5V_DDR
    R4624 +3VALW_PCH
    200_0402_5%
    1

    @
    R4607 R4608
    2

    47_0603_5% 200_0402_5% R4625


    @ @ 100K_0402_5% R11076
    1

    @ Q4607 D 100_0402_5%
    2

    VCCIO_EN# 2
    G @
    1 2
    1

    D Q4603 D Q4604
    1

    2 SUSP 2 SUSP Q4608 D @ S Q4628


    3

    G G 2
    13 VCCIO_EN
    G L2N7002KWT1G_SOT323-3
    S L2N7002KWT1G_SOT323-3 S L2N7002KWT1G_SOT323-3 PCH_PWR_EN# 2
    3

    @ @ @ S
    3

    SSM3K15AMFV_2-1L1B
    3

    4 L2N7002KWT1G_SOT323-3 4
    SIT CHANGE @

    Need double check enable signal and the resistance


    Security Classification LC Future Center Secret Data Title

    Issued Date 2015/08/20 Deciphered Date 2016/08/20


    DC V TO VS INTERFACE
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    Size Document Number
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS441/FS540
    Date: Wednesday, October 16, 2019 Sheet 46 of 61
    A B C D E
    5 4 3 2 1

    B2 A2
    D
    +3VLP PCH_PWR_EN# 2 D

    Q25,+3V_PCH

    V
    V
    AC A1
    MODE VIN

    V V
    A2 A4 B5
    3 +3V_PCH

    V
    PU301 PU904

    V
    B+
    +3VALW
    BATT BATT V 1
    DPWROK_EC
    V
    MODE

    V V V
    B1
    4
    PCH_RSMRST#
    EC 14
    PM_DRAM_PWRGD
    5 PBTN_OUT#

    V
    EC_ON PM_SLP_S3# PCH 15
    PM_SLP_S4# H_CPUPWRGD CPU

    V V
    A3 B4 PM_SLP_S5#
    PM_SLP_SUS# 6

    V
    CPU_PLTRST# 16
    12
    PCH_PWROK

    V V
    C C

    B3 13
    SYS_PWROK

    V
    ON/OFF V
    NOVO

    NVDD_PWR_EN
    (DIS)
    Vb
    +VGA_CORE

    V
    11 VR_REDY SYSON 7 +1.35V
    PU801
    PU501

    V
    DGPU_PWROK
    DGPU_PWR_EN
    10 Va (DIS)

    V
    PU901 VR_ON +1.5VS_VGA

    V
    Q31
    V

    PU601

    V
    +CPU_CORE
    +5VS

    B B

    V
    Q32 +1.05VSP_VGA

    V
    SUSP#,SUSP 9 +3VS PU702

    V
    VGA

    V
    PU602
    +1.5VS +3VS_VGA

    V
    Q27

    V
    PU502
    +0.675V
    8
    SUS_VCCP PU701
    V
    +1.05VS

    A A

    Security Classification LC Future Center Secret Data Title

    Issued Date 2015/08/20 Deciphered Date 2016/08/20 Power sequence block


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    Size Document Number
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS441/FS540
    Date: Wednesday, October 16, 2019 Sheet 47 of 61
    5 4 3 2 1
    5 4 3 2 1

    CPU ZZZ6 SAM_VR_N16@ ZZZ12 SAM_VR_N17@

    UC1 10510U@ UC1 10210U@ UC1 10110U@


    UC1 6405U@ UC1 5205U@

    V2G SAM N16 V2G SAM N17


    X7648812005 X7648A12003 VRAM_Samsung
    Intel i7-10510U 1.8G/4C/8M Intel i5-10210U 1.6G/4C/6M Intel i3-10110U 2.1G/2C/4M Intel 6405U 2.4G/2C/2M Intel 5205U 1.9G/2C/2M
    SA0000A7E00 SA0000A5G00 SA0000A7K00
    SA0000AHR00 SA0000AHS00
    D D

    ZZZ5 Hyn_VR_N16@ ZZZ13 Hyn_VR_N17@

    HYNIX V2G N16S HYNIX V2G N17S


    X7648912001 X7648812006 VRAM_Hynix

    ZZZ4 Mic_VR_N16@ ZZZ14 Mic_VR_N17@


    GPU
    OPTN17@
    UV1 OPTN16@ UV1 OPTN17@ RV2316 OPTN17@ RV2316 OPTN16@
    OPTN16@ RV2313
    RV2313
    V2G MIC N16 V2G MIC N17
    X7648A12002 X7648812007 VRAM_Micron
    N16S-GTR-S-A2 NB N17S-G3-A1 5.11_0805_1% 470_0805_5% 10K_0402_5%
    SA00007QA10 SA0000ADH00 SD00001NQ00 SD00247008J 30K_0402_5% SD02810028J
    SD02830028J

    C C

    PCB_MB
    ZZZ1 GS452@ ZZZ10 GS552@ ZZZ11 GS752@

    NM-C781 NM-C781 NM-C781


    DA600016S00 DA600016S00 DA600016S00
    ZZZ9 SAM_DRAM@

    D4G SAM
    X7648812008 DRAM_Samsung

    ZZZ8 Hyn_DRAM@

    HYNIX D4G
    X7648812009 DRAM_Hynix
    B B

    ZZZ7 Mic_DRAM@

    D4G MIC
    X7648812003 DRAM_Micron

    SO_DIMM only
    RC805 NMD@ RC812 NMD@ RC811 NMD@

    SO_DIMM SO_DIMM SO_DIMM


    SD02810028J SD02810028J SD02810028J

    A A

    Security Classification LC Future Center Secret Data Title

    Issued Date 2015/08/20 Deciphered Date 2016/08/20 Virtual symbol


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS441/FS540
    Date: Wednesday, October 16, 2019 Sheet 48 of 61
    5 4 3 2 1
    5 4 3 2 1

    Hole
    PCB Fedical Mark PAD MD Shielding
    H2
    HOLEA
    D
    FD4901 FD4902 FD4903 FD4904 FD4905 FD4906 D

    SH1 SH2 SH3 SH4 SH5 SH6


    1

    SPRING_FINGER_6.2X1.64 SPRING_FINGER_6.2X1.64 SPRING_FINGER_6.2X1.64 SPRING_FINGER_6.2X1.64 SPRING_FINGER_6.2X1.64


    SPRING_FINGER_6.2X1.64

    1
    PAD_C10P0D8P0

    1
    1

    1
    H3 H4 H5 H6 H7 H8
    HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
    1

    1
    C
    PAD_CT7P0B6P0D3P2 PAD_CT7P0B6P0D3P2 PAD_CT7P0B6P0D3P2 PAD_CT7P0B6P0D3P2 PAD_CT7P0B6P0D3P2 PAD_CT7P0B6P0D3P2 C

    H9 H10
    HOLEA HOLEA

    H17 H18
    1

    HOLEA HOLEA SODIMM Shielding

    PAD_C7P0D4P0 PAD_C7P0D4P0
    1

    1
    PAD_O2P5X3P0D2P5X3P0N PAD_O2P5X3P0D2P5X3P0N SH11 SH13
    H11 H12 H13 SH10 SH12
    SHIELDING_SUL-35A2M_9P2X3P3_1P SH14
    SHIELDING_SUL-35A2M_9P2X3P3_1P
    HOLEA HOLEA HOLEA SHIELDING_SUL-35A2M_9P2X3P3_1P SHIELDING_SUL-35A2M_9P2X3P3_1P SHIELDING_SUL-35A2M_9P2X3P3_1P
    1

    B B

    PAD_C7P0D2P8 PAD_C7P0D2P8 PAD_C7P0D2P8

    1
    1

    1
    HICT1 HICT2

    1
    HOLEA HOLEA

    1
    H14

    1
    HOLEA
    1

    1
    1

    PAD_C2P5D2P5N
    PAD_C2P5D2P5N

    PAD_C7P0D2P4
    HICT3
    HOLEA
    H15 H16
    HOLEA HOLEA
    1

    PAD_C2P5D2P5N
    1

    A A
    PAD_CT7P0B10P0D4P0 PAD_CT7P0B10P0D4P0

    Security Classification LC Future Center Secret Data Title


    Issued Date 2015/08/20 Deciphered Date 2016/08/20 Hole
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    B 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS441/FS540
    Date: Wednesday, October 16, 2019 Sheet 49 of 61
    5 4 3 2 1
    5 4 3 2 1

    V20B+
    +5VS
    Richtek
    +5VALW/8A
    LV5083AGQUF
    Adaptor 65W
    D D
    +1.05VGS/2.1A

    Converter +3VS

    FOR SYSTEM +1.0VALW/6A


    +3VALW/ 6A
    EN PGOOD

    +1.8VALW/1A

    TI Richtek +1.35V/8A Silergy +2.5V/1A

    BQ24780SRUYR LV5095B LV5028AGQV


    Battery Charger Switch Mode SYS PMIC
    EN
    C C

    Switch Mode FOR VRAM PGOOD


    +1.2V/6A

    UPI +0.6VS/2A

    SMBus UP1666QQKF +VGA_CORE/30A

    EN Switch Mode
    PGOOD
    FOR GPU VDDC

    Battery IA Core/42A
    Richtek
    polymer RT3602ACGQW VCCGT/18A

    3S1P/2S2P Switch Mode VCCSA/4A


    EN FOR CPU Core
    PGOOD
    B B

    A A

    Security Classification LC Future Center Secret Data Title

    Issued Date 2018/07/10 Deciphered Date 2018/07/10 PWR-Power Diagram


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.3
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 140S-WHL
    Date: Wednesday, October 16, 2019 Sheet 50 of 61
    5 4 3 2 1
    5 4 3 2 1

    PJ102 @ PJ101 @
    JUMP_43X79 JUMP_43X79
    1 2 1 2
    1 2 1 2 VIN
    3.25A HCB2012KF-121T50_0805
    JDCIN1 PF5101 PL5101
    1 ADPIN 1 2 APDIN_F 1 2
    1 2
    GND1 EMC@
    3 7A_24VDC_F1206HI7000V024TM
    GND2

    1000P_0201_50V7-K
    470P_0201_50V7-K
    4
    GND3 @

    1000P_0201_50V7-K

    470P_0201_50V7-K
    5 HCB2012KF-121T50_0805
    GND4

    EMC@

    EMC@
    PC5101

    PC5102
    6 PL5102
    GND5

    2
    EMC@

    EMC@
    PC5103

    PC5104
    D 7 1 2 D
    GND6
    EMC_NS@
    HIGHS_PJSS0026-8B01H

    1
    ME@

    +3VL

    1
    PR5101
    0_0402_5%

    2
    1

    PR5102
    C C
    45.3K_0402_1%
    VCCRTC @ RTC_VCC
    2

    1
    JRTC1
    3 2 PR5103 1 1
    2 1
    PD5101 1K_0603_5% 3 2
    GND1
    2

    PC5105 BAT54CW_SOT323-3 4
    1U_0402_6.3V6K GND2
    @
    1

    HIGHS_WS33020-S0351-HF
    ME@
    change symbol to SP021510283 by amy 0620

    RTC_VCC 20MIL
    +3VL 20MIL
    VCCRTC 20MIL

    B B

    A A

    Security Classification LC Future Center Secret Data Title

    Issued Date 2018/07/10 Deciphered Date 2018/07/10 PWR-DCIN / RTC charger


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    Size Document Number
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 140S-WHL
    Date: Wednesday, October 16, 2019 Sheet 51 of 61
    5 4 3 2 1
    5 4 3 2 1

    D SUYIN_125022HB008M202ZL VBAT EMC@ D

    JBATT1
    10A HCB2012KF-121T50_0805
    BATT+
    1 PL5201
    1 2 1 2
    9 2 3 EC_SMCA PR5201 1 2 100_0402_1%
    GND1 3 EC_SMDA EC_SMB_CK1 44,53
    10 4 1 2 1 2
    GND2 4 EC_SMB_DA1 44,53
    5 PR5202 100_0402_1%
    5 6 PR5922 1 @ 2 0_0402_5% PL5202
    6 7 HCB2012KF-121T50_0805
    7

    3
    8 EMC@
    8 RTC_VCC

    1
    PC5201 PC5202
    ME@ 1000P_0201_50V7-K 0.01U_0201_25V6-K
    EMC@ EMC@

    2
    Just reserved for RTC integrated into Battery

    PD5201
    AZC199-02S.R7G_SOT23-3
    JBATT2 VBAT EMC_NS@

    1
    1
    1 2
    2 3 EC_SMCA
    9 3 4 EC_SMDA
    10 GND1 4 5
    GND2 5
    6
    6 PR5203 2S1P polymer battery
    7 1 2
    7 8 100K_0402_1%
    +3VALW voltage level: +5.5V ~
    8
    C 8.8 V C
    PR5204
    HIGHSTAR_WS33081-S120S-1H 1 2
    BATT_TEMP 44,53
    ME@ 10K_0402_5%

    ONLY for 17''

    1
    1
    PD5202
    AZ5215-01F_DFN1006P2E2
    EMC_NS@

    2
    2

    B B

    A A

    Security Classification LC Future Center Secret Data Title

    Issued Date 2018/07/10 Deciphered Date 2018/07/10 PWR-BATTERY CONN/OTP


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    Size Document Number
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 140S-WHL
    Date: Wednesday, October 16, 2019 Sheet 52 of 61
    5 4 3 2 1
    5 4 3 2 1

    VIN
    PQ5301 PQ5302
    AONS32314_DFN8-5 AONR32340C_DFN8-5 N2
    N1 PR5301
    1 1 PJ5301 @ 0.01_1206_1%
    2 2 S1 5 JUMP_43X118 V20B+
    5 3 3 S2 D 1 2 1 4
    S3 1 2

    G
    2 3
    D D

    220P_0402_50V7K

    470P_0402_50V7K

    680P_0402_50V7K
    470P_0201_50V7-K

    4700P_0402_50V7-K

    6800P_0402_25V7-K
    10U_25V_M_X5R_0603

    10U_25V_M_X5R_0603
    0.022U_0402_25V7K

    0.01U_0201_25V6-K
    4

    EMC_NS@

    EMC_NS@
    PC5301
    2 2

    1
    EMC_NS@

    EMC_NS@

    EMC_NS@

    EMC_NS@

    EMC_NS@

    EMC_NS@
    PC5303

    PC5304

    PC5305

    PC5306

    PC5307

    PC5308

    PC5309

    PC5310
    1

    PC5302
    PR5302

    2
    4.7_0603_5% 1 1

    5
    0.1U_0201_25V6-K

    2
    PQ5303
    PC5311
    AON6324_DFN8-5
    1 2

    BQ24780_BATDRV 1 PR5303 2 BQ24780_BATDRV_R 4

    2
    09/09 NC MEC part
    0_0603_5%
    PC5312 PC5313
    0.1U_0201_25V6-K 0.1U_0201_25V6-K

    3
    2
    1
    2
    PR5304
    499K_0402_1% PC5314
    0.01U_0201_25V6-K

    1
    VIN BATT+

    2
    BAT54CW_SOT323-3
    PD5301
    2

    3
    V20B+

    4.02K_0603_1%
    VIN

    1
    1

    1
    4.02K_0603_1%

    10U_0805_25V6K

    10U_0805_25V6K
    0.1U_0201_25V6-K
    ACN

    EMC_NS@
    ACP
    PR5305

    PR5306

    1
    PC5318

    PC5315

    PC5319
    10_1206_5%
    2
    1

    PR5308
    BQ24780_VDD
    2

    2
    2

    5
    C PR5307 0.47U_25V_K_X5R_0603 PU5301 C
    7.15K_0402_1% 44.2K_0402_1%

    ACN
    ACP
    PC5317
    1 2 PC5316

    1
    PR5309 2 1 780_VCC 28 24 1 2

    2
    VCC REGN PQ5304
    1 2 ACDET 6 2.2U_10V_K_X5R_0603 4
    PC5320 ACDET PR5310 PC5321 AON7380_DFN8-5
    0.01U_0402_25V7K 25 BST_CHG 1 2 2 1
    BTST PR5311
    2.2_0603_5% 0.047U_0603_16V7K PL5301 0.01_1206_1% 6A

    3
    2
    1
    3
    CMSRC HIDRV
    26 DH_CHG 2.2UH_PCMB063T-2R2MS_8A_20% BATT+
    @ 1 2 CHG 1 4

    5
    PR53122 1 20K_0402_1% 4
    ACDRV

    1
    @ 2 3
    PR5313 2 1100K_0402_1% 27 LX_CHG PR5314

    10U_0805_25V6K

    10U_0805_25V6K

    10U_0805_25V6K

    10U_0805_25V6K
    BQ24780_VDD PHASE 2.2_0805_5%

    1
    PR5315 1 2 0_0402_5% ACIN_R 5 PQ5305

    PC5322

    PC5323

    PC5324

    PC5325
    44 ACIN ACOK EMC_NS@
    4

    2
    PR5316 1 2 0_0402_5% EC_SMB_DA1_R 11 AON7380_DFN8-5

    2
    44,52 EC_SMB_DA1 SDA 23 DL_CHG

    470P_0201_25V7K
    LODRV

    1
    2
    PR5317 1 2 0_0402_5% EC_SMB_CK1_R 12 22 PC5327

    PC5326

    3
    2
    1
    44,52 EC_SMB_CK1 SCL GND 1000P_0402_50V7K

    2
    BQ24780SRUYR_QFN28_4X4 EMC_NS@

    1
    PR5318 1 2 0_0402_5% ADP_I_R 7 29 @

    0.1U_0201_25V6-K

    0.1U_0201_25V6-K
    44 ADP_I IADP PAD

    2
    IDCHG 8 18 BQ24780_BATDRV

    PC5328

    PC5329
    IDCHG BATDRV
    9 PR5319 10_0603_5%

    1
    44,58 PSYS PMON 17 2 1
    BATSRC
    20K_0402_1%
    100P_0201_25V8J

    100P_0201_25V8J

    100P_0201_25V8J
    2

    20 SRP_R 2 1 SRP

    0.1U_0201_25V6-K
    PR5341 0_0402_5% SRP
    2

    1 2 10 PR5320 10_0603_5%
    PR5321

    PC5332

    44,58 VR_HOT#
    PC5330

    PROCHOT#

    2
    PC5331

    PC5333
    1

    13
    1

    CMPIN
    @
    1

    1
    BATPRES#
    TB_STAT#
    14
    CMPOUT 19 SRN_R 2 1 SRN
    B
    ILIM 21 SRN PR5322 10_0603_5% B
    ILIM
    2

    16

    15
    PR5323
    0_0402_5%
    09/19 PR331 change from 147K to 133K
    PR5324 PR5325
    1

    1 2 ILIM_R 1 2 TB_STAT#
    +3VALW BATT_TEMP 44,52
    30K_0402_1%
    133K_0402_1%
    0.01U_0201_25V6-K

    1
    2

    PC5334

    PR5326
    100K_0402_1%
    1

    V20B+ EMC demand

    ACDECT setting 17.2V


    Charge current limit HW=7A
    1

    1
    PC6161 PC6163 PC6165 PC6167 PC6169 PC6171
    DC discharge limit =26A PC6162 PC6164 PC6166 PC6168 PC6170 PC6172
    1000P_0402_25V7-K

    1000P_0402_25V7-K

    1000P_0402_25V7-K

    1000P_0402_25V7-K

    1000P_0402_25V7-K

    1000P_0402_25V7-K
    0.1U_0402_25V7-K

    0.1U_0402_25V7-K

    0.1U_0402_25V7-K

    0.1U_0402_25V7-K

    0.1U_0402_25V7-K

    0.1U_0402_25V7-K
    2

    2
    Discharge current limit HW=9A during Turbo boost @ @ @ @ @ @ @ @ @ @ @ @

    A A

    Security Classification LC Future Center Secret Data Title

    Issued Date 2018/07/10 Deciphered Date 2018/07/10 PWR-CHARGER


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.3
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 140S-WHL
    Date: Wednesday, October 16, 2019 Sheet 53 of 61
    5 4 3 2 1
    5 4 3 2 1

    D D
    PR521
    1 2 0_0402_5%
    EC_ON 44,54

    PMIC_VCC 1 2 0_0402_5%
    PR522 @ ALW_PWRGD 11,54
    +5VALW
    +5VLP PR502 @
    1 2
    10_0603_5%
    PR520
    VDDQ_EN

    PMIC_EN
    PR501 1 2 0_0402_5% 1 2
    44 SYSON 10_0603_5%
    PC500
    PR503 1 2 0_0402_5% VTT_EN 1 2
    5 CPU_DRAMPG_CNTL PR505
    VDDQ_P 1 2 2.2U_0603_6.3V6K
    PR507 1 2 0_0402_5% +1.8VALW_L_EN

    VSYS_PMIC
    10_0402_5%

    1
    1 2 +1.05VALW_EN PC502
    PR506 0_0402_5% +3VALW
    44 PCH_PWR_EN 0.1U_0201_25V6-K

    2
    PR508 1 2 +2.5V_DDR_EN
    44 EC_VPP_PWREN

    28

    27

    41
    PU500

    9
    0_0402_5%

    100K_0402_5%
    0.1u_0201_10V6K

    0.1u_0201_10V6K

    0.1u_0201_10V6K

    0.1u_0201_10V6K

    0.1u_0201_10V6K

    VSYS

    VCC

    PMIC_EN

    GND
    PR510

    1
    +2.5V_DDR_EN 29 25 PMIC_SMB_DAT1 1 2 0_0402_5%

    PC504

    PC506

    PC505

    PC503

    PC508

    PR513
    R_0402
    EN_LDO1 SDA EC_SMB_DA3 44
    PR511
    +1.8VALW_L_EN 1 26 PMIC_SMB_CLK1 1 2 0_0402_5%
    EC_SMB_CK3 44

    1
    EN_LDO2 SCL
    +1.05VALW_EN 11 24 PMIC_ALERT# PR512 2 1 0_0402_5%
    @ @ @ @ @ @ H_PROCHOT# 4,44

    2
    EN_V1P0A OT
    +1.0VGS_B_EN 16 22 +1.05VALW_PG 1 PAD @ PTC501
    EN_V1P8A PG_V1P0A
    C VDDQ_PGOOD 44 C
    VDDQ_EN 31 21 +1.0VGS_B_PG 1 PAD @ PTC502
    EN_VDDQ PG_V1P8A
    VTT_EN VDDQ_PGOOD

    22UC_6.3VC_MC_X5RC_0603
    PR525 36 23
    1 2 +1.0VGS_B_EN EN_VTT PG_VDDQ PL500
    23 PXE_VDD_EN_R PR5502
    0_0402_5% +5VALW PJ501 LX_1P05
    1UH_PCMB063T-1R0MS_12A_20%
    +1.05VALW_FB
    12 1 2 1 2
    6A PCH and to N16 GPU PMIC load switch

    0.1U_0402_25V6
    OPT@ 1 2 +1.05VALW_B_VIN 7 LX_V1P0A1 13 +1.05VALW

    22UC_6.3VC_MC_X5RC_0603

    22UC_6.3VC_MC_X5RC_0603

    22UC_6.3VC_MC_X5RC_0603

    22UC_6.3VC_MC_X5RC_0603

    22UC_6.3VC_MC_X5RC_0603

    22UC_6.3VC_MC_X5RC_0603
    UMA@
    1M_0402_5%
    1 2 VIN_V1P0A1 LX_V1P0A2

    1
    8 14 if need to change to R33 choke 1/3W_0.005_+-1%_0805_LE_200PPM/C

    PC537
    1 VIN_V1P0A2 LX_V1P0A3 1 1 1 1 1 1

    1
    @
    15

    PR519

    PC509

    PC511

    PC512

    PC513

    PC514

    PC515

    PC516
    JUMP_43X118 PC510 LX_V1P0A4

    2
    @ 10 +1.05VALW_FB
    0.1u_0201_10V6K

    2
    2 VO_V1P0A 2 2 2 2 2 2
    PJ509 EMC_NS@

    2
    +1.0VGS_B_VIN PL502 PR5504
    1 2 17 @ @
    +5VALW 1 2 19 LX_V1P8A1 18 LX_1P0 1 2 +1.0VGS_FB 1 2
    1 VIN_V1P8A LX_V1P8A2 +1.0VGS N17 GPU/ setting to 1.0V, 2.1A

    22UC_6.3VC_MC_X5RC_0603

    22UC_6.3VC_MC_X5RC_0603
    PC534 1UH_PH041H-1R0MS_3.8A_20%
    09/08 reserve one pull down JUMP_43X79 22UC_6.3VC_MC_X5RC_0603 20 +1.0VGS_FB 1/3W_0.005_+-1%_0805_LE_200PPM/C
    1 1
    @ OPT@
    VO_V1P8A OPT@
    N16 GPU/ setting to 1.05V, 2.1A

    PC535

    PC536
    2 OPT@
    PC529 33 UG_VDDQ
    +1.2V_P UGATE_VDDQ PC518 2 2
    1 210U_0603_10V6K 38 PR1031
    VIN_VTT 32 BST_VDDQ 1 2 2 1
    BS_VDDQ

    OPT@

    OPT@
    PR5507
    0.1U_50V_M_X7R_0603
    1 2 39 0_0603_5%

    LX_1P05
    +0.6VS VTT

    LX_1P0
    34 LX_VDDQ
    1 LX_VDDQ
    1/5W_0.01_1%_0402_100PPM/C PC519
    1A 40
    22UC_6.3VC_MC_X5RC_0603
    VSNS_VTT LGATE_VDDQ
    35 LG_VDDQ

    1
    PR515 @ 2 37 +1.2V_P
    1 2 30 VSNS_VDDQ PR1029 PR1030
    33K_0402_1% CS_VDDQ 4.7_0603_5% 4.7_0603_5%

    PJ502 PR5508
    1A EMC_NS@ EMC_OPTNS@ 14" N17S-G1 1.8VGS 0.3A
    @

    2
    2 1 +2.5V_DDR_VIN 5 6 +2.5V_P 2 1
    +3VALW 2 1
    PC521
    VIN_LDO1 LDO1 +2.5V_DDR 15" N17P-G0 1.8VGS 1.6A

    1
    1 2 1/5W_0.01_1%_0402_100PPM/C
    JUMP_43X39 1 2 PC520 PC1109 PC1110
    B B
    1200P_0402_50V7-K 1200P_0402_50V7-K
    1A

    2
    22UC_6.3VC_MC_X5RC_0603 PR5509
    10U_0603_10V6K EMC_NS@ EMC_OPTNS@
    3 +1.8VALW_L_P 2 1
    4 LDO2 +1.8VALW
    VIN_LDO2 2

    22UC_6.3VC_MC_X5RC_0603
    1/5W_0.01_1%_0402_100PPM/C
    FB_LDO2

    2
    110K_0402_1%
    1

    PR516

    PC522
    PJ510 @ LV5075BGQV_VQFN40_5X5
    2 1 +1.8VALW_L_VIN V20B+

    +1.8VALW_L_FB
    +3VALW 2 1 2

    1
    JUMP_43X39 1
    PC523 PJ507
    VDDQ_P 2 1
    10U_0603_10V6K PQ500 2 1
    2

    0.1U_0201_25V6-K
    AONR32340C_DFN8-5

    5
    JUMP_43X118

    10U_0805_25V6K

    10U_0805_25V6K
    PC524
    @

    1
    PC525

    PC526
    2

    2
    UG_VDDQ

    EMC_NS@
    PR517 4
    G
    75K_0402_1%

    S3
    S2
    S1
    +1.2V

    1
    6A

    3
    2
    1
    0.47UH_PCMB053T-R47MS_13A_20%
    PR5501
    PL501
    LX_VDDQ 1 2 +1.2V_P 1 2

    22UC_6.3VC_MC_X5RC_0603

    22UC_6.3VC_MC_X5RC_0603

    22UC_6.3VC_MC_X5RC_0603

    22UC_6.3VC_MC_X5RC_0603

    22UC_6.3VC_MC_X5RC_0603
    1/3W_0.005_+-1%_0805_LE_200PPM/C

    2
    1 1 1 1 1
    PQ501 4.7_0603_5%

    PC527

    PC528

    PC530

    PC517
    PC1113
    PR518
    AON7380_DFN8-5
    2 2 2 2 2
    EMC_NS@

    1
    LG_VDDQ 4

    1
    A A
    PC533
    1200P_0402_50V7-K

    3
    2
    1

    2
    EMC_NS@
    @

    Security Classification LC Future Center Secret Data Title

    Issued Date 2018/07/10 Deciphered Date 2018/07/10 PWR PMIC-DDR4/1.0ALW/1.8ALW


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 140S-WHL
    Date: Wednesday, October 16, 2019 Sheet 55 of 61
    5 4 3 2 1
    A B C D

    V20B+
    PR5601 OPT@
    1.5A PC3603
    1 2
    0.1U_50V_M_X7R_0603

    10U_0805_25V6K

    10U_0805_25V6K
    PR3601
    1/3W_0.005_+-1%_0805_LE_200PPM/C +1.35V_BST 1 2+1.35V_BST_R 1 2

    1
    PC3601

    PC3602
    10_0603_5%
    OPT@ OPT@ 08/09 PL3601 from 053Tto 063T- SKY
    PD3601 OPT@ +1.35VGS

    2
    1 2 PU3601

    18

    5
    PL3601
    0.68UH_PCMB063T-R68MS_16A_20% PJ3602 8A

    VBOOT
    AGND
    LRB751V-40T1G_SOD323-2 +1.35V_VIN 12 3 +1.35V_LX 1 2 +1.35V_P 2 1
    OPTNS@
    OPT@ OPT@ VIN4 SW_1 2 1

    22UC_6.3VC_MC_X5RC_0603

    22UC_6.3VC_MC_X5RC_0603

    22UC_6.3VC_MC_X5RC_0603

    22UC_6.3VC_MC_X5RC_0603

    22UC_6.3VC_MC_X5RC_0603

    22UC_6.3VC_MC_X5RC_0603
    OPT@ JUMP_43X118
    1 2 +1.35V_EN 16 4
    23 FBVDDQ_PWR_EN EN4 SW_2 1 1 1 1 1 1 @

    PC3611

    PC3606

    PC3607

    PC3612

    PC3608

    PC3613
    PR706

    1
    1
    100K_0402_5% 1 2 PC3604 PC3605 OPTNS@ 1

    OPT@ 0.022U_0402_25V7K 15 +1.35V_FB 1 2 PR3603


    25 FB 2.2_0603_5% 2 2 2 2 2 2
    OPT@ NC_3

    1
    0.1U_0402_25V6 EMC_OPTNS@

    OPTNS@
    OPT@

    OPT@
    23 PR3606

    2
    NC_2

    OPTNS@
    22

    +1.35V_SN
    1K_0402_1%
    NC_1

    OPT@

    OPT@
    OPT@

    1
    6
    +5VALW

    2
    PGND_1 PR3607

    1
    7 1/16W_41.2K_1%_0402
    2 1 24 PGND_2 PC3619 +1.35V_FB_1 OPT@
    NGC6@ VCC_SW 8 1000P_0402_50V7K
    Vout=1.35V±5%

    2
    PGND_3

    1
    PC3616 OPT@ 1U_0402_6.3V6K EMC_OPTNS@ PC3620 Vset=1.36V±2%
    9 560P_0402_50V7-K 09/08 change PR3607 from 41.2K to 21K
    1.8VGS_PWR_EN 1 PR3610 2 MAIN_PWR_EN 19 PGND_4
    OPT@ 09/19 change PR3609 from 21K to 42.2K
    OCP>12A

    2
    23,26 1.8VGS_PWR_EN EN2 10
    2.2K_0402_5% +3.3V_1.8V_AON PR3605 PGND_5
    OPT@ Vref=0.6V
    1 2 1 2 VIN1_3.3V_1.8V 21 11 +1.35V_FB
    VIN2 PGND_6 +3V_1.8VGS OVP=(1.25~1.35)*Vref

    1
    PC3614 OPTN16@ 0.047U_0402_25V7K 1/5W_0.01_1%_0402_100PPM/C
    1 2 20
    PC3615 1U_0402_6.3V6K VOUT2 PR3609
    UVP=(0.7~0.8)*Vref
    PXS_PWR_EN_R

    1U_0402_6.3V6K
    OPTNS@ 28 31.6K_0402_1%
    23 PXS_PWR_EN_R EN3 OPT@
    Fsw=700Khz

    2
    1

    OPT@
    PC3618
    1 2
    1 26 +3.3V_1.8V_AON
    LSW1 RDS=36~50mohm,Io=0.5A
    PC3621 VIN3_1 VOUT3_1
    OPT@ 0.1U_0402_25V6 LSW2 RDS=18~25mohm,Io=1A

    2
    +3.3V_1.8V_AON_IN 2 27
    VIN3_2 VOUT3_2
    LSW3 RDS=5~7mohm,Io=3.5A

    1
    29 PC3623
    VIN3_3
    1U_0402_6.3V6K

    TH_ALT

    PGOOD
    OPT@

    2
    VCC
    +3.3V_1.8V_AON_IN

    +3VS

    14

    17

    13
    PR3613

    2
    2 1
    PC3622
    0_0402_5% +3V_1.8VGS 1U_0402_6.3V6K

    +1.35V_VCC
    1
    +3.3V_1.8V_AON

    1
    +1.8V_VGA
    OPTN16@ PR3615 OPTNS@ PR3611 PR3612
    2 2

    PR3614 2 1 100K_0402_1% 100K_0402_1%


    2 1 OPTNS@ OPTNS@
    0_0402_5%

    2
    0_0402_5%
    NGC6@
    OPTN17@

    1
    09/08 change RV1394 to PR3615 PC3629
    1U_0402_6.3V6K

    2
    OPT@
    09/08 change RV1395 to PR3613
    09/08 change RV1396 to PR3614

    +1.8VALW +1.8V_VGA

    PJ9
    2 1
    2 1

    JUMP_43X39
    @
    +1.8VS

    PJ10
    2 1
    2 1

    JUMP_43X39
    @

    3 3

    4 4

    Security Classification LC Future Center Secret Data Title

    Issued Date 2018/07/10 Deciphered Date 2018/07/10 PWR-VGA-PMIC


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    Size Document Number
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
    Custom 0.3
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 140S-WHL
    Date: Wednesday, October 16, 2019 Sheet 56 of 61
    A B C D
    5 4 3 2 1

    PWM-VID Specification
    N17 Config N16 Config B
    RT8816 PSI UP1666 PSI Phase Configuration
    Vmin(V) 0.3 0.6
    1.6V~5.5V 1.6~5.5V 2Phase CCM
    Vmax(V) 1.3 1.2
    1.08~1.35V 1~1.4V 2Phase DEM
    Vboot(V) 0.8 0.9
    0.7~0.88V 0.4V~0.8V 1Phase CCM
    Vstep(mV) 6.25 6.25
    0~0.4V 0~0.2V 1Phase DEM
    N(level) 160 96
    Fpwm(KHz) 675 1.125 V20B+
    D Tdmin(nS) 9.26 9.26 +VGA_CORE_VIN D
    PR5701
    T(uS) <100 <100 1 2

    +5VALW 1/3W _0.005_+-1%_0805_LE_200PPM/C

    EMC_OPTNS@

    0.1U_0201_25V6-K

    10U_0805_25V6K

    10U_0805_25V6K
    OPT@

    1
    PC801

    1
    PC802

    PC803
    1

    2
    5
    PR801
    PU801
    2_0603_5% PQ801
    OPT@ AON6380_DFN8-5
    OPT@ OPT@

    2
    NVVDD_PVCC 18
    PVCC NVVDD_HG1
    OPT@
    2 4
    UGATE1

    1
    PC804 PR805
    +3.3V_1.8V_AON PC805
    1U_0402_6.3V6K 2.2_0603_5%
    1 NVVDD_BS11 2 1 2
    OPT@

    3
    2
    1
    BOOT1
    1

    21 OPT@
    PR806 GND 0.22U_0603_25V7K
    5.1K_0402_1% OPT@
    PL801 +VGA_CORE
    OPT@ PHASE1
    20 NVVDD_PH1 1 2 30A

    2200P_0402_50V7K 1/8W_1_5%_0805
    2

    1
    OPT@ 0.22UH_PCMB063T-R22MS_23A_20%

    22UC_6.3VC_MC_X5RC_0603

    22UC_6.3VC_MC_X5RC_0603

    22UC_6.3VC_MC_X5RC_0603

    22UC_6.3VC_MC_X5RC_0603

    22UC_6.3VC_MC_X5RC_0603

    22UC_6.3VC_MC_X5RC_0603
    1 2 0_0402_5% NVVDD_PSI_R 4

    PR803
    PR802

    EMC_OPT@

    330U_D2_2V_Y

    330U_D2_2V_Y
    26 PSI_VGA PSI OPT@ 1 1
    1 1 1 1 1 1

    PC806

    PC807

    PC809

    PC810

    PC811

    PC812

    PC808

    PC813
    PR804 OPT@ PR807 OPTNS@ PQ802 + +
    1 2 1 2 AON6324_DFN8-5
    +3VS

    2
    1K_0402_1% 5.1K_0402_1% 19 NVVDD_LG1 4
    LGATE1 OPT@ 2 2 2 2 2 2 2 2
    13 1
    8,23 DGPU_PWROK PGOOD

    OPT@

    OPT@
    PC814
    PR808

    EMC_OPT@
    OPTNS@ NVVDD_EN_R
    23 NVVDD_EN
    1 2 3 OPT@ OPT@

    3
    2
    1
    EN 2

    OPTNS@

    OPTNS@
    OPT@

    OPT@
    1/16W_37.4K_1%_0402 V20B+
    1

    C PC815 C
    PD801 0.1U_0402_10V7K +VGA_CORE_VIN PR5702
    1 2 OPTNS@
    2

    OPT@ 1 2
    LRB751V-40T1G_SOD323-2

    EMC_OPTNS@
    1/3W _0.005_+-1%_0805_LE_200PPM/C

    10U_0805_25V6K

    10U_0805_25V6K
    0.1U_0201_25V6-K
    1 2 NVVDD_VID_R 5 14 NVVDD_HG2
    26 NVVDD_PWM_VID VID UGATE2 OPT@

    1
    PC830

    PC833

    PC831
    1

    PR809 PR810 PQ803


    PC817
    0_0402_5% PC816 2.2_0603_5%

    2
    0.1U_0402_10V7K 15 NVVDD_BS21 2 1 2 4 AON6380_DFN8-5
    OPT@
    2

    BOOT2
    OPTNS@ OPT@
    OPT@ 0.22U_0603_25V7K +VGA_CORE
    OPT@ OPT@
    OPT@ PL802

    3
    2
    1
    09/08 change 1U to 0.1uh
    16 NVVDD_PH2 1 2
    2 1 NVVDD_VREF 8 PHASE2

    2200P_0402_50V7K 1/8W_1_5%_0805

    22UC_6.3VC_MC_X5RC_0603

    22UC_6.3VC_MC_X5RC_0603
    VREF

    1
    0.22UH_PCMB063T-R22MS_23A_20%

    PR811
    PC818

    EMC_OPT@

    330U_D2_2V_Y
    OPT@ 1 1 1
    1

    PC821

    PC820
    0.1U_0402_25V7-K

    OPTNS@

    PC819
    PR812 +
    OPT@ 20.5K_0402_1%

    2
    2 2
    OPTNS@ NVVDD_LG2 2
    17 PQ804 1
    2

    LGATE2 AON6324_DFN8-5

    OPT@

    OPT@
    4

    PC824

    EMC_OPT@
    OPT@

    1
    NVVDD_REFIN 7
    REFIN PR5921 2 PR814
    2

    30K_0402_5% 100_0402_1%
    1

    PR833 UPI_OPT@ 1 2

    3
    2
    1
    PR813

    2
    82.5K_0402_1% OPT@
    16.5K_0402_1%
    PR816
    UPI_OPT@
    OPTNS@ PR815
    1

    6.19K_0402_1% PR817
    2

    1 2 1 2 NVVDD_VIDBUF 6 0_0402_5%
    1

    PC825 REFADJ 10 NVVDD_FBRTN 1 2


    OPTNS@ FBRTN NVVDD_VSS_SENSE 22
    0.01U_0402_25V7K 4.32K_0402_1% OPT@
    1

    B B
    OPTNS@ OPTNS@
    2

    1
    PR818 PC826 PC827 VR Remote Sense - Tie to GPU sense points
    309_0402_1% 4700P_0402_25V7-K 11 NVVDD_FB 1000P_0402_25V7-K
    FB
    OPTNS@ OPTNS@ OPTNS@
    2

    2
    PR824
    PR819
    2

    0_0402_5%
    2 1NVVDD_FS 9 12 NVVDD_SS 1 2
    FS/OC COMP NVVDD_VCC_SENSE 22
    OPT@
    V20B+ 475K_0402_1%
    PR825
    PR820 RT_OPT@ 100_0402_1%
    2 1 1 2 +VGA_CORE

    2.2_0603_5% OPT@
    RT_OPT@
    UP1666QQKF_WQFN20_3X3
    PR821 set OC and PC837 set external SS for RT8816
    1

    UPI_OPTNS@

    PC849 OPTNS@
    1000P_0402_25V7-K
    1

    RT_OPTNS@

    RT_OPT@

    1U_0402_25V6-K PR832
    1000P_0402_25V7-K
    2

    1
    PC836

    PR834 51K_0402_1%
    110K_0402_1%

    RT_OPT@
    2

    PC837

    PR821

    100K_0402_1% UPI_OPT@
    UPI_OPT@
    2

    PR827
    Vboot=0.8V
    2

    0_0402_5%
    2
    2

    1 2 NVVDD_FBRTN PC834
    1000P_0402_25V7-K
    Ripple=±20mV
    UPI_OPT@
    UPI_OPT@ TDC=28.5A Iccmax=55A OCP>75A
    PR820,PR819,PC849 set TON for RT8816
    1
    2

    PR826
    TDC=30A Iccmax=60.1A OCP>80A
    0_0402_5%
    RT_OPT@ PR833,PR834 set FS/OC for UP1666 Vref=2V
    PR833=82.5,PR834=100k, OCP=85A change by 0705-sky
    1

    FUVP:Vfb=0.2V
    SUVP:Vcomp=3V
    PR832,PC834,PR836 set COMP for UP1666 OVP:Vfb=2V
    Fsw=320KHz
    A
    PR816,PR812,PR815,PR813,PR818,PC826 BOM structure control for N16 or N17 A

    Component Value N17 N16


    R1(KΩ) PR816 6.19 20
    R2(KΩ) PR812 20.5 20
    R3(KΩ) PR815 4.32 2 UPI_OPT@ : for UP1666 Security Classification LC Future Center Secret Data Title
    R4(KΩ) PR813 16.5 18
    RT_OPT@ : for RT8816A Issued Date 2018/07/10 Deciphered Date 2018/07/10 PWR-VGA_CORE
    R5(KΩ) PR818 0.309 0
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    Size Document Number Rev
    C(nF) PC826 4.7 2.7 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Custom 0.3
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 140S-WHL
    Date: Wednesday, October 16, 2019 Sheet 57 of 60
    5 4 3 2 1
    5 4 3 2 1

    +VCCST_CPU
    +5VALW +5VALW V20B+
    +VCCST_CPU

    8.2_0603_5%
    1

    2
    PR5802
    PC5801 2.2_0603_5%
    1U_0402_6.3V6K PR5801

    1
    75_0402_1%

    100_0402_1%
    45.3_0402_1%

    2.2_0402_1%
    PR5803

    PR5804

    PR5805

    PR5806
    1

    1
    2.2U_0603_10V7K

    4.7U_0603_6.3V6K
    @ +VCCST_CPU 2 2

    PC5803
    D D

    VR_PVCC
    2

    1K_0402_1%
    PC5802
    @

    1
    44,53 PSYS

    PR5808
    VR_VCC
    PR5809 PR5807
    PU5801 bom need change to RT3602AH( SA00009B600 )--sky-0704

    VR_VRMP
    1
    1 1

    1K_0402_1%
    10_0402_1% PC5804 54.9_0402_1% @
    VR_SVID_DAT_1

    PR5810
    2 1 0.1U_0402_25V7-K

    2
    VR_SVID_DAT 12
    PR5811 @

    2
    0_0402_5%
    VR_SVID_ALRT#_1 2 1

    2
    VR_SVID_ALRT# 12
    PR5812 @ RT3602AHGQW_WQFN52_6X6

    18

    13

    12
    49.9_0402_1% PU5801
    VR_SVID_CLK_1 2 1 20K_0402_1%

    PVCC

    VCC

    VIN
    VR_SVID_CLK 12 1 PR5813 2 50 42
    PSYS VR_READY CPU_VR_READY 44
    VREF 1 2 VR_EN 41
    44 EC_VR_ON EN 35
    PR5814
    VR_HOT VR_HOT# 44,53
    0_0402_5%
    VR_SVID_DAT_1 36
    VDIO 26 GT_BST 1 2 1 2 499_0402_1%
    VR_SVID_ALRT#_1 BOOT_AUXI
    3.83K_0402_1%

    19.1K_0402_1%

    37 2.2_0603_5% PR5818
    ALERT
    1

    6.81K_0402_1%

    PR5815 PC5805 1 2
    VR_SVID_CLK_1 GT_PH_R 59
    PR5816

    PR5817

    PR5821

    38 25 0.22U_0603_16V7K
    VCLK UGATE_AUXI GT_UG 59
    649_0402_1% 2.2K_0402_3%_TSM0B222H3953RE
    PR5819 PH5801
    24 1 2 1 2
    2

    PHASE_AUXI GT_PH 59 +VCC_GT_R 59


    SET1 2
    SET1 23 1 2
    LGATE_AUXI GT_LG 59
    1.21K_0402_1%

    2.2K_0402_1%
    1

    SET2 5 PR5822
    SET2
    PR5820

    1/16W_69.8_1%_0402 4.12K_0402_1%
    1

    33 GT_CSP 1 2
    ISENP_AUXI
    PR5823

    SET3 6 PC5806 0.47U_0402_25V6K


    SET3
    3.16K_0402_1%

    32
    2

    ISENN_AUXI
    1

    1
    VREF
    PR5824

    0.22U_0603_16V7K
    2
    1

    1/16W_15_+-1%_0402

    PC5807
    SA_BST
    PR5825

    14 1 2 0.1U_0402_25V6

    2
    BOOT_SA
    1

    PC5808
    46 PR5826 2.2_0603_5%
    2

    VREF06/PSET
    1
    PR5827

    0.47U_0402_25V6K 3.9_0402_1%

    422_0402_1%

    2
    PR5828

    1/16W_37.4K_1%_0402 15 1 PR5829 2
    2

    UGATE_SA SA_UG 59 SA_PH_R 59


    1

    GT_Imon
    63.4_0402_1%

    1 2 34
    IMON_AUXI
    PR5830

    C 29.4K_0402_1% PR5831 C
    2

    1
    1 PR5832 2 16 PH5802
    10_0402_5% 2.2K_0402_1%
    2

    PHASE_SA SA_PH 59 1 PR5833 2 1 2


    PH5803 +VCCSA_R 59
    2 51.1K_0402_1% 1.82K_0402_1%
    2

    1 PR5835 2 Vcore_Imon
    PC5809

    1 PR5834 2 1 2 1 17
    IMON_MAIN LGATE_SA SA_LG 59
    100_0402_1%
    1 1 2
    @
    100K_0402_1%_TSM0B104F4251RZ SA_Imon 43
    1 PR5836 2 sky 0908: change PH5802 from
    PR5837
    57.6K_0402_1%
    IMON_SA
    ISENP_SA
    44 SA_CSP 2
    PC5810
    1
    0.47U_0402_25V6K
    SL200003K00 to SD000004O8J
    45
    ISENN_SA

    1
    330P_0402_50V7K 82P_0402_50V9-G 51 0.1U_0402_25V6
    12,58 VCORE_VCC_SEN VSEN_MAIN

    0.22U_0603_16V7K
    PC5812 PC5813 2.2_0603_5% PC5811
    1 2 1 2 22 Vcore_BST1 1 PR5839 2

    2
    BOOT_MAIN

    PC5815
    1 2 1 2 Vcore_COMP 4
    12,58 VCORE_VCC_SEN COMP_MAIN

    2
    PR5840 PR5841 21
    UGATE_MAIN Vcore_UG1 59
    2

    10K_0402_1% 61.9K_0402_1% @ 1/16W_348_1%_0402


    PC5814@ 2 1 2 1 Vcore_FB 3

    1
    FB_MAIN 20 PR5843
    1000P_0402_50V7K @ PC5816 PR5842 @
    1

    PHASE_MAIN Vcore_PH1 58,59 1 2


    470P_0402_50V7K 16.9K_0402_1%
    52 Vcore_PH1_R 59
    12 VCORE_VSS_SEN RGND_MAIN 19
    LGATE_MAIN Vcore_LG1 59 1 2
    +CPU_CORE1 59
    PC5817 0.47U_0402_25V6K
    270P_50V_K_X7R_0402 @
    PC5818 68P_0402_50V8J 31 10 1 2
    12,58 VCCGT_VCC_SEN VSEN_AUXI ISEN1P_MAIN
    PC5819 PR5845
    1 2 1 2 7 180K_0402_1%
    ISEN1N_MAIN

    1
    1 2 1 2 GT_COMP 30 0.1U_0402_25V6 1/16W_348_1%_0402
    12,58 VCCGT_VCC_SEN COMP_AUXI U42@
    10K_0402_1% PR5848 PC5820 1 PR5849 2
    Vcore_PH2_R 59
    2

    PC5821 PR5847 39

    2
    2 1 2 1 1/16W_23.2K_1%_0402 GT_FB 28 DRVEN DRVEN 59
    1000P_0402_50V7K
    @ FB_AUXI U42@
    @ PC5822 PR5850 @ 40 1 2 PR5920 1 2 0_0402_5%
    1

    PWM_MAIN Vcore_PWM 59 +CPU_CORE2 59


    470P_0402_50V7K 16.9K_0402_1% PC5823 0.47U_0402_25V6K U42@
    29
    12 VCCGT_VSS_SEN RGND_AUXI 9 1 2
    PC5824 68P_0402_50V8J
    220P_0402_50V7K PC5825 ISEN2P_MAIN PR5851 0_0402_5%
    U22@
    1 2 1 2 8
    B ISEN2N_MAIN B
    1 2

    1
    1 2 1 2 SA_COMP 47 +5VALW VREF 0.1U_0402_25V6
    13 VCCSA_VCC_SEN COMP_SA 10K_0402_1%
    10K_0402_1% U22@ 110K_0402_1% PC5826
    11 TSEN_CORE PR5919 2 PR5856 1 2 1 2 1
    PR5854 PR5855 U42@

    2
    TSEN_MAIN
    2

    PC5827 2 1 2 1 1/16W 48.7K +-1% 0402 SA_FB 49 15.8K_0402_1%


    1000P_0402_50V7K PC5828 @ PR5859 @ FB_SA PR5857 PR5858
    @ VREF
    470P_0402_50V7K 16.9K_0402_1% 49.9_0402_1%
    1

    48 PR5861 PH5804
    110K_0402_1% PR5862
    13 VCCSA_VSS_SEN RGND_SA 27 TSEN_GT 2 PR5860 1 2 1 2 1 2 1
    TSEN_AUXI 12.4K_0402_1%
    GND

    1/16W_464_1%_0402
    PH5805

    2
    100K_0402_1%_TSM0B104F4251RZ
    @
    2 1
    53

    PR5864
    16.9K_0402_1%
    100K_0402_1%_TSM0B104F4251RZ

    1
    Place close to MOSFET

    1
    PR5869
    1/16W_23.2K_1%_0402

    2 1 1M_0402_1% 1 2 PR5917 Vcore_Imon


    58,59 Vcore_PH1
    PC5829 10P_0402_50V8J

    2 1 1M_0402_1% 1 2 PR5918
    59 Vcore_PH2
    PC5830 10P_0402_50V8J
    U42@ U42@

    A A

    Security Classification LC Future Center Secret Data Title

    Issued Date 2018/07/10 Deciphered Date 2018/07/10 PWR-CPU-CORE-1


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    Size
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
    A2 0.3
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 140S-WHL
    Date: Wednesday, October 16, 2019 Sheet 58 of 61
    5 4 3 2 1
    5 4 3 2 1

    HCB2012KF-121T50_0805 V20B+
    PL5905
    GT_VIN 1 2

    10U_0805_25V6K

    10U_0805_25V6K
    0.1U_0201_25V6-K
    1 1

    1
    Vboot=0V Loadline=3.1mΩ

    EMC@
    PC5901

    PC5902

    PC5903
    PQ5901 Ripple=+30mV/-10mV(0A~0.5A)

    2
    2 2
    AON6380_DFN8-5
    +VCC_GT Ripple=±10mV(0.5A~TDC)
    4
    58 GT_UG Ripple=±15mV(TDC~Iccmax)
    0.15UH_PCME063T-R15MS0R907_37A_20% TDC=18A Iccmax=31A OCP=37A
    PL5901
    GT_PH 1 2
    OVP=VID+370mV~VID+430mV

    3
    2
    1
    58 GT_PH
    D
    18A Max Overshoot:70mv/10us D

    2200P_0402_50V7K 1/8W_1_5%_0805
    1
    PQ5908 @ @ UVP=VID-370mV~VID-225mV

    2
    EMC@
    PR5901
    AON6324_DFN8-5
    PJ5902 PJ5912 Fsw=550Khz
    JUMPER JUMPER

    1
    4

    2
    58 GT_LG
    1 +VCC_GT_R 58

    EMC@
    PC5926
    3
    2
    1
    2
    GT_PH_R 58

    V20B+
    HCB2012KF-121T50_0805
    PL5906
    CPU_VIN 1 2

    33U_D2_25VM_R40M
    10U_0805_25V6K

    10U_0805_25V6K

    10U_0805_25V6K

    10U_0805_25V6K
    5
    1

    0.1U_0201_25V6-K
    PQ5902 1 1 1 1 HCB2012KF-121T50_0805

    PC5988
    AON6380_DFN8-5 + PL5907

    PC5927

    PC5929

    PC5930

    PC5978

    PC5979
    1 2

    EMC@

    2
    4 2 2 2 2 2
    58 Vcore_UG1
    U22 :21A
    @ U42: 48A
    +CPU_CORE

    3
    2
    1
    0.15UH_PCME063T-R15MS0R907_37A_20%
    PL5902
    1 2
    58 Vcore_PH1
    Vboot=0V Loadline=1.8mΩ

    2200P_0402_50V7K 1/8W_1_5%_0805
    1
    PQ5903 @ @ Ripple=+30mV/-10mV(0A~0.5A)

    2
    EMC@
    PR5902
    AON6324_DFN8-5
    C PJ5905 PJ5906 Ripple=±10mV(0.5A~TDC) C
    JUMPER JUMPER

    1
    4
    Ripple=±15mV(TDC~Iccmax)

    2
    58 Vcore_LG1
    +CPU_CORE1 58
    1 TDC=21A/48A Iccmax=32A/70A

    EMC@
    PC5956
    OCP=37A / 74A

    3
    2
    1
    2 Vcore_PH1_R 58
    Max Overshoot:70mv/10us
    OVP=VID+370mV~VID+430mV
    UVP=VID-370mV~VID-225mV
    Fsw=550Khz

    10U_0805_25V6K

    10U_0805_25V6K
    +5VALW 0.22U_0603_16V7K CPU_VIN

    0.1U_0201_25V6-K
    PC5957 1 1

    1
    1 2 1 2

    PC5958

    PC5959

    PC5960
    PR5903
    2.2_0603_5% U42@ PQ5904

    2
    2

    2 2
    U42@ AON6380_DFN8-5
    PR5904
    U42@ 2.2_0603_5% U42@
    PU5901 4 U42@ @ @
    4 Vcore_BST2
    +CPU_CORE
    1

    Vcore_VCC 8 BOOT
    0_0402_5% VCC 3 Vcore_UG2 0.15UH_PCME063T-R15MS0R907_37A_20%
    U42@ Vcore_PWM_D UGATE
    1U_0402_10V6K

    1 PR5905 2 5 PL5903
    3
    2
    1
    58 Vcore_PWM PWM 2 Vcore_PH2 1 2
    PHASE
    1

    Vcore_EN
    PC5961

    2200P_0402_50V7K 1/8W_1_5%_0805
    1 2 1
    58 DRVEN EN
    5

    1
    10_0402_5% 7 Vcore_LG2 @ @
    U42@ LGATE U42@

    2
    U42@
    PR5907
    U42@ PR5906 6 PQ5905
    2

    GND1 9 Vcore_PH2 58
    AON6324_DFN8-5 PJ5907 PJ5908
    GND2
    JUMPER JUMPER

    1
    RT9610CGQW_WDFN8_2X2 U42@

    2
    4
    U42@ 1 +CPU_CORE2 58

    U42@
    PC5964
    3
    2
    1

    B 2 B
    Vcore_PH2_R 58

    ME require, so PC5500/PC5501 reverve


    for EE noise debug-sky 0814 PR903
    SA_VIN 1
    10U_0805_25V6K

    2
    PQ5906 V20B+
    10U_25V_M_X5R_0603

    10U_25V_M_X5R_0603

    AONR32340C_DFN8-5
    @

    @
    0.1U_0201_25V6-K
    5

    2 2 1 1/3W_0.005_+-1%_0805_LE_200PPM/C Vboot=0V Loadline=10.3Ω


    1

    PC5976

    PC5977
    D

    EMC@
    PC5965

    PC5967

    Ripple=+30mV/-10mV(0A~0.5A)
    2

    1 1 2
    4
    Ripple=±10mV(0.5A~TDC)
    G
    Ripple=±15mV(TDC~Iccmax)
    S3
    S2
    S1

    TDC=4A Iccmax=4.5A OCP=7A


    +VCCSA
    3
    2
    1

    Max Overshoot:70mv/10us
    58 SA_UG
    0.47UH_PCMB042T-R47MS_7A_20% OVP=VID+370mV~VID+430mV
    1 2
    58 SA_PH
    PL5904 UVP=VID-370mV~VID-225mV
    2200P_0402_50V7K 1/8W_1_5%_0805

    58 SA_LG
    5

    @ @ Fsw=550Khz
    4A
    2

    2
    EMC_NS@
    PR5908

    PQ5907
    AON7380_DFN8-5 PJ5910 PJ5911
    JUMPER JUMPER
    1

    1
    2

    4
    +VCCSA_R 58
    1
    A A
    EMC_NS@
    PC5975
    3
    2
    1

    2 SA_PH_R 58

    Security Classification LC Future Center Secret Data Title

    Issued Date 2018/07/10 Deciphered Date 2018/07/10 PWR-CPU-CORE-2


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    Size
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
    A2 0.3
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 140S-WHL
    Date: Wednesday, October 16, 2019 Sheet 59 of 61
    5 4 3 2 1
    A
    B
    C
    D

    +VCC_GT

    +VCC_GT

    2
    1
    1
    +
    @

    2
    1
    2 3
    2
    1
    PC6125

    +VCCSA
    22UC_6.3VC_MC_X5RC_0603 PC6110 PC6077 PC6031

    @
    10U_0603_6.3V6M 220U_D2_2VM_R6M 10U_0603_6.3V6M
    +CPU_CORE

    2
    1
    2
    1
    2
    1

    +CPU_CORE
    2
    1
    +

    PC6126 PC6111 PC6032

    +CPU_CORE
    22UC_6.3VC_MC_X5RC_0603 10U_0603_6.3V6M 10U_0603_6.3V6M PC6001

    2
    1
    +
    330U_D2_2V_Y

    5
    5

    2
    1
    2
    1
    PC6078

    2
    1
    PC6112 330U_D2_2V_Y PC6033
    PC6127 10U_0603_6.3V6M 2 1 10U_0603_6.3V6M
    2
    1
    +

    @
    22UC_6.3VC_MC_X5RC_0603

    N3T@

    2
    1
    2
    1
    PC6056 U42@ PC6002

    2
    1
    PC6113 1U_0402_6.3V6K PC6034 330U_D2_2V_Y
    PC6128 10U_0603_6.3V6M 2 1 10U_0603_6.3V6M

    @
    22UC_6.3VC_MC_X5RC_0603

    @
    N3T@

    2
    1
    2
    1
    2
    1
    +

    PC6057

    2
    1
    PC6114 1U_0402_6.3V6K PC6035 PC6003
    PC6129 10U_0603_6.3V6M 10U_0603_6.3V6M 330U_D2_2V_Y
    22UC_6.3VC_MC_X5RC_0603

    2
    1
    PC6036

    2
    1
    10U_0603_6.3V6M
    PC6079
    22UC_6.3VC_MC_X5RC_0603

    2
    1

    @
    2
    1
    2
    1
    PC6115
    PC6130 10U_0603_6.3V6M PC6080 @
    2
    1

    22UC_6.3VC_MC_X5RC_0603 22UC_6.3VC_MC_X5RC_0603

    2
    1
    PC6037

    2
    1
    2
    1

    PC6116 10U_0603_6.3V6M
    10U_0603_6.3V6M PC6081 2 1 @ PC6004
    2
    1

    22UC_6.3VC_MC_X5RC_0603 22UC_6.3VC_MC_X5RC_0603

    @
    2
    1
    PC6060 PC6038

    N3T@

    2
    1
    2
    1

    PC6117 1U_0402_6.3V6K 10U_0603_6.3V6M


    10U_0603_6.3V6M PC6082 @ PC6005
    2
    1

    22UC_6.3VC_MC_X5RC_0603 22UC_6.3VC_MC_X5RC_0603

    2
    1
    PC6039

    2
    1
    2
    1

    PC6118 10U_0603_6.3V6M

    2
    1
    @

    10U_0603_6.3V6M PC6083 PC6006


    2
    1

    PC6131 22UC_6.3VC_MC_X5RC_0603 22UC_6.3VC_MC_X5RC_0603


    10U_0603_6.3V6M PC6040
    2
    1

    10U_0603_6.3V6M

    +VCCSA

    2
    1
    2
    1
    PC6007
    2
    1

    PC6132 PC6119 22UC_6.3VC_MC_X5RC_0603


    10U_0603_6.3V6M 10U_0603_6.3V6M PC6041
    2
    1

    10U_0603_6.3V6M

    2
    1
    2
    1
    2
    1
    @

    PC6008
    2
    1

    PC6133 PC6120 PC6084 22UC_6.3VC_MC_X5RC_0603


    10U_0603_6.3V6M 10U_0603_6.3V6M 22UC_6.3VC_MC_X5RC_0603 PC6042
    10U_0603_6.3V6M

    @
    2
    1
    2
    1
    2
    1
    PC6134 PC6121 PC6085
    10U_0603_6.3V6M 10U_0603_6.3V6M 22UC_6.3VC_MC_X5RC_0603
    2
    1

    2
    1
    2
    1
    2
    1
    2
    1

    remove 1U_0402 CAP 15PCS N3T@-20190718 PC6009


    PC6135 PC6122 PC6086 PC6043 22UC_6.3VC_MC_X5RC_0603

    4
    4

    10U_0603_6.3V6M 10U_0603_6.3V6M 22UC_6.3VC_MC_X5RC_0603 10U_0603_6.3V6M


    2
    1

    2
    1
    2
    1
    2
    1
    2
    1

    PC6010
    PC6136 PC6123 PC6087 PC6044 22UC_6.3VC_MC_X5RC_0603
    10U_0603_6.3V6M 10U_0603_6.3V6M 22UC_6.3VC_MC_X5RC_0603 10U_0603_6.3V6M
    2
    1

    @
    @

    2
    1
    2
    1
    2
    1

    PC6011
    PC6124 PC6088 PC6045 22UC_6.3VC_MC_X5RC_0603

    @
    2
    1
    10U_0603_6.3V6M 22UC_6.3VC_MC_X5RC_0603 10U_0603_6.3V6M
    2
    1

    PC6137
    2
    1

    10U_0603_6.3V6M PC6012
    PC6046 22UC_6.3VC_MC_X5RC_0603

    @
    2
    1
    10U_0603_6.3V6M
    @
    2
    1

    PC6138
    @

    10U_0603_6.3V6M PC6013
    2
    1

    22UC_6.3VC_MC_X5RC_0603

    @
    2
    1
    2
    1 PC6047
    PC6139 PC6100 10U_0603_6.3V6M
    @

    10U_0603_6.3V6M 22UC_6.3VC_MC_X5RC_0603
    2
    1

    @
    2
    1
    2
    1
    2
    1

    PC6048
    PC6140 PC6101 10U_0603_6.3V6M PC6014
    10U_0603_6.3V6M 22UC_6.3VC_MC_X5RC_0603 22UC_6.3VC_MC_X5RC_0603

    +VCC_GT
    @

    2
    1
    2
    1
    2
    1

    PC6141 2 1 PC6102 PC6015


    10U_0603_6.3V6M 22UC_6.3VC_MC_X5RC_0603 22UC_6.3VC_MC_X5RC_0603
    PC6089
    2
    1
    2
    1

    1U_0402_6.3V6K
    2
    1

    PC6103 PC6016
    22UC_6.3VC_MC_X5RC_0603 PC6049 22UC_6.3VC_MC_X5RC_0603
    @

    10U_0603_6.3V6M
    2
    1
    2
    1

    @
    2
    1

    PC6104 PC6017
    22UC_6.3VC_MC_X5RC_0603 PC6050 22UC_6.3VC_MC_X5RC_0603
    @

    10U_0603_6.3V6M
    2
    1
    2
    1

    2 1
    PC6105 PC6018
    22UC_6.3VC_MC_X5RC_0603 4 3 22UC_6.3VC_MC_X5RC_0603
    3T@

    2 1 4.3U_0402_4V6-M
    PC6155

    @
    PC6146
    1U_0402_6.3V6K

    +VCCSA
    2 1
    2
    1

    2 1
    PC6019
    PC6142 4 3 22UC_6.3VC_MC_X5RC_0603
    3T@

    1U_0402_6.3V6K
    4.3U_0402_4V6-M
    2
    1

    PC6156 PC6020

    3
    3

    2 1 2 1 22UC_6.3VC_MC_X5RC_0603

    remove 1U_0402 CAP 4PCS N3T@-20190718


    2
    1

    PC6143 PC6150 2 1
    1U_0402_6.3V6K 1U_0402_6.3V6K PC6021
    2 1 4 3 22UC_6.3VC_MC_X5RC_0603
    3T@
    @

    2 1
    4.3U_0402_4V6-M

    @
    2
    1

    PC6144
    1U_0402_6.3V6K PC6149 PC6157 PC6022
    1U_0402_6.3V6K 22UC_6.3VC_MC_X5RC_0603
    2 1
    2 1

    @
    PC6145
    1U_0402_6.3V6K 2 1 4 3
    3T@

    2 1
    4.3U_0402_4V6-M
    2
    1

    4 3

    @
    PC6151 4.3U_0402_4V6-M PC6158 PC6023
    1U_0402_6.3V6K 22UC_6.3VC_MC_X5RC_0603
    PC6159
    @
    @
    2
    1

    2 1
    PC6024
    PC6152 22UC_6.3VC_MC_X5RC_0603
    1U_0402_6.3V6K
    @
    2
    1

    PC6025
    22UC_6.3VC_MC_X5RC_0603
    2 1
    2
    1

    @
    4 3 PC6026
    4.3U_0402_4V6-M 22UC_6.3VC_MC_X5RC_0603
    @
    2
    1

    PC6160
    PC6027
    22UC_6.3VC_MC_X5RC_0603

    Issued Date
    Security Classification
    +2PCS_1U_0402_6V= sky_07_09
    VCCGT: 1PCS_330U_D2_2V+1PCS_220U_D2_2V

    +2PCS_1U_0402_6V=07-09 sky
    VCCSA:5PCS_22U_0603_6V+6PCS_10U_0603_6V
    +10PCS_22U_0603_6V+9PCS_9U_0603_6V

    2
    2

    2018/07/10
    Deciphered Date
    LC Future Center Secret Data
    sky modify_20180925
    sky modify_20180709
    Vender modify_20180705

    layout change PC6024/PC6025

    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
    2018/07/10

    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    PC6003 @ and stuff 6 pcs 22U/0603

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    +16PCS_1U_0201_6V=

    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    to PC6036/PC6046

    Date:
    change 10U/0402 to 10U/0603, 1U/0201 to 1U/0402

    Custom
    Title
    CPU_CORE: 2PCS_330U_D2_2V+1PCS_220U_D2_2V

    Size Document Number


    +13PCS_22U_0603_6V+18PCS_10U_0402_6V

    1
    1

    Wednesday, October 16, 2019


    Sheet
    140S-WHL
    PWR-CPU Decoupling Cap

    60
    of
    61
    Rev
    0.3
    A
    B
    C
    D
    5 4 3 2 1

    PU801 RT_OPT@ PU801 UPI_OPT@

    RT8816AGQW_WQFN20_3X3 UP1666QQKF WQFN 20P CONTROLLER


    SA000081U00 SA00008G000
    GPU solution
    Component Value N17 N16S-GTR
    R1(KΩ) PR816 6.19 20
    D D
    OPTN17@ OPTN17@ OPTN17@ OPTN17@ OPTN17@ OPTN17@ OPTN17@ OPTN17@
    PR816 PR812 PR815 PR813 PR818 PC826 PR808 PC815 OPTN17@
    R2(KΩ) PR812 20.5 20
    PR3610
    R3(KΩ) PR815 4.32 2
    R4(KΩ) PR813 16.5 18
    6.19K_0402_1% 20.5K_0402_1% 4.32K_0402_1% 16.5K_0402_1% 309_0402_1% 4700P_0402_25V 18K_0402_1% 0.22U_0402_10V6K
    R5(KΩ) PR818 0.309 0
    SD000015G00 SD03420528J SD00000J28J SD03416528J SD00001XX00 SE075472K8J SD00000058J SE095224K0J 0_0402_5%
    SD02800008J
    C(nF) PC826 4.7 2.7
    N17 solution

    OPTN16@ OPTN16@ OPTN16@ OPTN16@ OPTN16@ OPTN16@ OPTN16@ OPTN16@ OPTN16@


    PR816 PR812 PR815 PR813 PR818 PC826 PR808 PC815 PR3610

    20K_0402_1% 20K_0402_1% 2K_0402_5% 18K_0402_1% 0_0402_5% 2700P_0402_50V 18K_0402_1% 0.22U_0402_10V6K 2.2K_0402_5%


    SD03420028J SD03420028J SD03420018J SD00000058J SD02800008j SE00000ZJ00 SD00000058J SE095224K0J SD02822018J
    N16 solution

    U42@ U42@ U42@ U42@


    PR5835 PR5841 PR5861 PR5869

    C C

    1.8K +-1% 0402 61.9K +-1% 0402 464 +-1% 0402 23.2K +-1% 0402 U42 solution
    SD00000R58J SD03461928J SD00001CP00 SD00001NZ00

    U22@ U22@ U22@ U22@


    PR5835 PR5841 PR5861 PR5869

    U22 solution
    2.32K +-1% 0402 47.5K +-1% 0402 1.8K +-1% 0402 19.6K +-1% 0402
    SD000016300 SD03447528J SD00000R58J SD00000358J

    B B

    A A

    Security Classification LC Future Center Secret Data Title

    Issued Date 2015/08/20 Deciphered Date 2016/08/20 NGFF_SSD_1


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.2
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EYG10
    Date: Wednesday, October 16, 2019 Sheet 61 of 60
    5 4 3 2 1

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