A B C D E

1 1

LCFC Confidential
El
GS454/GS554 NM-D031 MB
et
2 2

ro
Schematics Document

-X
https://vinafix.com
ICL U42 With DDR4 +
Te
Nvidia N16V-GM

ch
3 3

ni
2019-10

ca
REV:1.0

l
4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 Cover Page

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday, December 06, 2019 Sheet 1 of 60
A B C D E
 A B C D E

LCFC confidential

NV N16x/N17x
Package: FCBGA595 Memory Bus DDR4 SO-DIMM+MDx4
1
PCI-Express 1.2V DDR4 Page 17/18 1

4x Gen3
VRAM: 256*32
GDDR5*2: 2GB x1

USB3.0 USB3.0 Conn

HDMI (DDI 1) x1
HDMI Conn.

x1
eDP x2

El
eDP Conn x1 USB3.0 Conn

Intel MCP

et
x1
SATA x1 USB2.0 Conn
SATA HDD
Ice Lake-U42 15W USB2.0
2 2

ro
NGFF PCI-Express Finger print
SSD 4x Gen3

-X
BGA1526
NGFF PCIe x1 50mm*25mm

https://vinafix.com
USB2.0 x1
WLAN&BT

Te
SPI SPI ROM (16MB)
W25Q128JVSIQ
Page 07

SPK Conn.
Page 30

ch
HD Audio x1
Realtek
HP&Mic RTS5199
3 Combo Conn. USB2.0 x1 3

Page 30 Page 43

ni
I2C Touch Pad
Page 45
Page 3~16

ca
SD Conn. LPC

IO Board EC GPIO
HALL Sensor

l
ITE IT8227E-LQFP128
Page 44

Int.KBD
Page 45 Thermal Sensor
F75303M Page 39

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 Block Diagram

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Tuesday, December 10, 2019 Sheet 2 of 60
A B C D E
 5 4 3 2 1

B2 A2
D
+3VLP PCH_PWR_EN# 2 D

Q25,+3V_PCH

V
V
AC A1
MODE VIN

V V
A2 A4 B5
3

V
PU301 PU904 +3V_PCH

V
B+
+3VALW
BATT BATT V 1
DPWROK_EC
V
MODE

V V V
B1
4
PCH_RSMRST#
EC 14

El
PM_DRAM_PWRGD
5

V
PBTN_OUT#

EC_ON PM_SLP_S3# PCH 15

PM_SLP_S4# H_CPUPWRGD CPU

V V
A3 B4 PM_SLP_S5#

et
PM_SLP_SUS# 6

V
CPU_PLTRST# 16
12
PCH_PWROK

V V
C C

ro
B3 13
SYS_PWROK

V
ON/OFF V
NOVO

-X
NVDD_PWR_EN

https://vinafix.com
(DIS)
Vb
+VGA_CORE

V
11 VR_REDY SYSON 7 +1.35V PU801

Te
V
PU501
DGPU_PWROK
DGPU_PWR_EN
10 Va (DIS)

V
+1.5VS_VGA

V
PU901 VR_ON Q31
V

PU601

V
ch
+CPU_CORE
+5VS

B B

V
Q32 +1.05VSP_VGA

V
+3VS PU702

V
SUSP#,SUSP 9 VGA

ni V
PU602
+1.5VS +3VS_VGA

ca
V

V
Q27

V
PU502
+0.675V

l
8
SUS_VCCP PU701
V
+1.05VS

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 Power sequence block

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday, December 06, 2019 Sheet 47 of 60
5 4 3 2 1
 5 4 3 2 1

V20B+
+5VS
Richtek
+5VALW/8A
LV5083AGQUF
Adaptor 65W
D D

Converter +3VS

FOR SYSTEM VCCIN_AUX/14A

+3VALW/ 6A
EN PGOOD

+1.8VALW/4A

El
+1.35V/8A Silergy +2.5V/1A
TI Richtek

et
BQ24780SRUYR LV5095B LV5116A
Battery Charger Switch Mode SYS PMIC
EN
C C

ro
Switch Mode FOR VRAM +1.2V/8A
PGOOD

UPI +0.6VS/1A

-X
SMBus UP1666QQKF +VGA_CORE/30A

https://vinafix.com
EN Switch Mode
PGOOD
FOR GPU VDDC

Te
Battery Richtek
polymer RT3612EB VCCIN/39A

ch
3S1P/2S2P Switch Mode
EN FOR CPU Core
PGOOD
B B

ni
ca
l
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/07/10 Deciphered Date 2018/07/10 PWR-Power Diagram

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday, December 06, 2019 Sheet 50 of 60
5 4 3 2 1
 A B C D E

Voltage Rails ( O --> Means ON , X --> Means OFF )

SIGNAL
STATE SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

Full ON HIGH HIGH HIGH ON ON ON ON

Power Plane
+3VALW S3 (Suspend to RAM) LOW HIGH HIGH ON ON OFF OFF

+5VALW +1.2V S4 (Suspend to Disk) LOW LOW LOW ON OFF OFF OFF
+5VS
1 1

V9B+ +3VALW_PCH +2.5V_DDR +3VS S5 (Soft OFF) LOW LOW LOW ON OFF OFF OFF
+1.8VS
+1.8VALW +VCCST +CPU_CORE

VCC_AUX +0.6VS
State +VCCSTG
HSIO PORT Function BOM Structure BTO Item
1 USB3.0 Conn @ Un-stuff
2 USB3.0 Conn 14@ For 14" part
3 NC 15@ For 15" part
USB3.0

El
4 NC
S0 O O O O 5
6
1 USB3.0 Conn
S3 O O O X

et
2 USB3.0 Conn
3 NC CD@ For cost down
S3 4 NC
2
Battery only O O O X USB2.0 5 Camere EMC@ For EMC part 2

ro
6 Touch Screen EMC_15@ For EMC 15" part
S5 S4 7 Finger Print EMC_NS@ For EMC un-stuff part
AC Only O O X X 8 Card Reader
9 USB2.0 conn

-X
S5 S4 10 Bluetooth
Battery only O X X X 5~8 DGPU

https://vinafix.com
X4
S5 S4 9 WLAN
ME@ For ME part

Te
AC & Battery X X X X PCIE 10 NC
don't exist
11 SATA HDD UMA@ For UMA part
12 NC OPT@ For NV GPU part
SMBUS Control Table 13~16 OPTN16@ For NV N16S-GTR GPU part
PCIE/SATA SSD
OPTN17@

ch
X4 For NV N17S-G1 GPU part
SOURCE BATT Charger DGPU IT8227E Memory PCH PMIC SODIMM Thermal WLAN
Down Sensor WiMAX

3 3
EC_SMB_CK1 IT8227E V V X V X X X X X X

ni
EC_SMB_DA1 +3VL_EC +3VL_EC

EC_SMB_CK0 IT8227E X X V V X X X X V X
EC_SMB_DA0 +3VS +3VG_AON +3VS TS@ For touch screen part

ca
TP@ For TOuch Pad Part
EC_SMB_CK3 IT8227E X X X V X X V X X X
EC_SMB_DA3 +3VAWL

PCH_SMB_CLK PCH X X X X X V X V X X

l
PCH_SMB_DATA +3VALW_PCH +3VALW_PCH +3VS

EC SMBus1 address EC SMBus2 address EC SMBus3 address PCH SM Bus address

Device Address Device Address Device Address Device Address
Smart Battery need to update Thermal Sensor(NCT7718W) 1001_100xb PMIC need to update DDR4 SODIMM need to update
4 4
Charger 0001 0010 b DGPU need to update

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 Notes List

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday, December 06, 2019 Sheet 3 of 60
A B C D E
 5 4 3 2 1

UC1A
CPU_EDP_TX0- Y5 BB5
33 CPU_EDP_TX0- CPU_EDP_TX0+ DDIA_TXN_0 TCP0_TX_N0
Y3 BB6
33 CPU_EDP_TX0+ CPU_EDP_TX1- Y1 DDIA_TXP_0 TCP0_TX_P0 AV6
33 CPU_EDP_TX1- CPU_EDP_TX1+ DDIA_TXN_1 TCP0_TX_N1
Y2 AV5
33 CPU_EDP_TX1+ DDIA_TXP_1 TCP0_TX_P1
V2 BH2
V1 DDIA_TXN_2 TCP0_TXRX_N0 BH1
V3 DDIA_TXP_2 TCP0_TXRX_P0 BF1
V5 DDIA_TXN_3 TCP0_TXRX_N1 BF2
DDIA_TXP_3 TCP0_TXRX_P1
CPU_EDP_AUX# W4 AY5
33 CPU_EDP_AUX# CPU_EDP_AUX DDIA_AUX_N TCP0_AUX_N
W3 AY6
D 33 CPU_EDP_AUX DDIA_AUX_P TCP0_AUX_P D
CPU_HDMI_TXN2 AE3
34 CPU_HDMI_TXN2 CPU_HDMI_TXP2 AE5 DDIB_TXN_0 AR5
HDMI D2 34 CPU_HDMI_TXP2 CPU_HDMI_TXN1 AE2 DDIB_TXP_0 TCP1_TX_N0 AR6
34 CPU_HDMI_TXN1 CPU_HDMI_TXP1 DDIB_TXN_1 TCP1_TX_P0
HDMI D1 AE1 AL5
34 CPU_HDMI_TXP1 CPU_HDMI_TXN0 DDIB_TXP_1 TCP1_TX_N1
AC5 AL3
34 CPU_HDMI_TXN0 CPU_HDMI_TXP0 AC3 DDIB_TXN_2 TCP1_TX_P1 BD2
HDMI D0 34 CPU_HDMI_TXP0 CPU_HDMI_CLKN AC1 DDIB_TXP_2 TCP1_TXRX_N0 BD1
34 CPU_HDMI_CLKN CPU_HDMI_CLKP DDIB_TXN_3 TCP1_TXRX_P0
HDMI CLK AC2 BB1
34 CPU_HDMI_CLKP DDIB_TXP_3 TCP1_TXRX_N1 BB2
AD3 TCP1_TXRX_P1
AD4 DDIB_AUX_N AN3
DDIB_AUX_P TCP1_AUX_N AN5
DP15 TCP1_AUX_P
DJ17 GPP_E22/DDPA_CTRLCLK/PCIE_LNK_DOWN
GPP_E23/DDPA_CTRLDATA/BK4/SBK4 BF6
PCH_HDMI_DDC_CLK DL40 TCP2_TX_N0 BF5
34 PCH_HDMI_DDC_CLK PCH_HDMI_DDC_DATA GPP_H16/DDPB_CTRLCLK TCP2_TX_P0
DP42 BJ5
34 PCH_HDMI_DDC_DATA GPP_H17/DDPB_CTRLDATA TCP2_TX_N1 BJ6
DL17 TCP2_TX_P1 BL1
GPP_E19 DK17 GPP_E18/DDP1_CTRLCLK/TBT_LSX0_TXD TCP2_TXRX_N0 BL2
GPP_E19/DDP1_CTRLDATA/TBT_LSX0_RXD TCP2_TXRX_P0

El
BM2
DN17 TCP2_TXRX_N1 BM1
GPP_E21 DP17 GPP_E20/DDP2_CTRLCLK/TBT_LSX1_TXD TCP2_TXRX_P1
GPP_E21/DDP2_CTRLDATA/TBT_LSX1_RXD BG6
DK34 TCP2_AUX_N BG5
GPP_D10 DL34 GPP_D9/ISH_SPI_CS_N/DDP3_CTRLCLK/GSPI2_CS0_N/TBT_LSX2_TXD TCP2_AUX_P
GPP_D10/ISH_SPI_CLK/DDP3_CTRLDATA/GSPI2_CLK/TBT_LSX2_RXD
DN33 BP6
GPP_D12 DL33 GPP_D11/ISH_SPI_MISO/DDP4_CTRLCLK/GSPI2_MISO/TBT_LSX3_TXD TCP3_TX_N0 BP5
GPP_D12/ISH_SPI_MOSI/DDP4_CTRLDATA/GSPI2_MOSI/TBT_LSX3_RXD TCP3_TX_P0

et
BV5
CPU_EDP_HPD DW11 TCP3_TX_N1 BV6
33 CPU_EDP_HPD CPU_HDMI_HPD GPP_E14/DPPE_HPDA/DISP_MISCA TCP3_TX_P1
CV42 BR1
34 CPU_HDMI_HPD GPP_A18/DDSP_HPDB/DISP_MISCB TCP3_TXRX_N0
CV39 BR2
CY43 GPP_A19/DDSP_HPD1/DISP_MISC1 TCP3_TXRX_P0 BT2
USB_OC1# CR41 GPP_A20/DDSP_HPD2/DISP_MISC2 TCP3_TXRX_N1 BT1
41 USB_OC1# USB_OC2# CT41 GPP_A14/USB_OC1_N/DDSP_HPD3/DISP_MISC3 TCP3_TXRX_P1
42 USB_OC2# DV14 GPP_A15/USB_OC2_N/DDSP_HPD4/DISP_MISC4 BT6
C C
GPP_E17 TCP3_AUX_N

ro
BT5
PCH_ENVDD DN21 TCP3_AUX_P
33 PCH_ENVDD EDP_VDDEN
PCH_ENBKL DL19 AY1 TCRCOMP_N RC401 1 2 1/20W_150_1%_0201
33,44 PCH_ENBKL PCH_EDP_PWM EDP_BKLTEN TC_RCOMP_N TCRCOMP_P
33 PCH_EDP_PWM DU19 AY2
1 DSI_DE_TE_2 J3 EDP_BKLTCTL TC_RCOMP_P
+3VS TP401 @ RSVD_1 CT38
1 DISP_UTILS D2 GPP_A17/DISP_MISCC CV43
TP402 @ EDP_COMP R2 DISP_UTILS GPP_A21 CV41
RPC401 DISP_RCOMP GPP_A22
10f 19

1
PCH_HDMI_DDC_CLK

-X
1 4
2 3 PCH_HDMI_DDC_DATA RC402
ICELAKE-U_BGA1526
1/20W_150_1%_0201
2.2K_0404_4P2R_5% @

2
+3VALW_PCH

https://vinafix.com

Te
1/20W_4.7K_1%_0201 2 @ 1 RC403 GPP_E19

1/20W_20K_5%_0201 2 @ 1 RC404

1/20W_4.7K_5%_0201 2 @ 1 RC405 GPP_E21

1/20W_20K_5%_0201 2 @ 1 RC406

1/20W_4.7K_5%_0201 2 @ 1 RC407 GPP_D10

ch
1/20W_20K_5%_0201 2 @ 1 RC408

1/20W_4.7K_5%_0201 2 @ 1 RC409 GPP_D12

B
1/20W_20K_5%_0201 2 @ 1 RC410

An external pull-up resistor is required if the pin is

Vinafix.com B

used as HDMI Display I2C, instead of TBT LSx

0 = DDPx I2C / TBT LSx pins at 1.8V

ni
1 = DDPx I2C / TBT LSx pins at 3.3V

+1.8VALW_PCH
GPIO Group Power Supply

ca
RC411 1 2 10K_0201_5% USB_OC1#
GPP_A 1.8V
RC412 1 2 10K_0201_5% USB_OC2#
GPP_B/C/D/E 3.3V

1 2 100K_0201_5%CPU_EDP_HPD
GPP_F 1.8V(only)
RC413

GPP_G/H 3.3V

l
CC401
2 1 GPP_R/S 1.8V
0.33U 10V K X5R 0402
@ GPD 3.3V(only)
RPC402
4 1 PCH_ENVDD
3 2 PCH_ENBKL

100K_0404_4P2R_5%

CC402
2 1
A A
0.33U 10V K X5R 0402
@

Security Classification LC Future Center Secret Data Title

Issued Date 2018/12/04 Deciphered Date 2018/08/20 S740-ICL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Name Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday, December 06, 2019 Sheet 4 of 60
5 4 3 2 1
 5 4 3 2 1

DDRA_DQS#[0..7] DDRB_CLK0#
18 DDRA_DQS#[0..7]
DDRA_DQS[0..7]
18 DDRA_DQS[0..7] 1
CC502
DDRB_DQS#[0..7]
330P_0402_50V8J
17 DDRB_DQS#[0..7]
@
DDRB_DQS[0..7] 2
17 DDRB_DQS[0..7] DDRB_CLK0
SO_DIMM
MD
UC1B
17 DDRB_DQ[0..63]
UC1C
18 DDRA_DQ[0..63] DDRA_DQ0 DDRA_CLK0#
CA48 BL48
D DDRA_DQ1 DDRA_DQ0_0/DDR0_DQ0_0 DDRA_CLK_N/DDR0_CLK_N_0 DDRA_CLK0 DDRA_CLK0# 18 DDRB_DQ0 DDRB_CLK0# D
CA47 BL47 AK48 Y48
DDRA_DQ2 CA49 DDRA_DQ0_1/DDR0_DQ0_1 DDRA_CLK_P/DDR0_CLK_P_0 BF42 DDRA_CLK1# DDRA_CLK0 18 DDRB_DQ1 AK45 DDRC_DQ0_0/DDR1_DQ0_0 DDRC_CLK_N/DDR1_CLK_N_0 Y47 DDRB_CLK0 DDRB_CLK0# 17
DDRA_DQ3 BV49 DDRA_DQ0_2/DDR0_DQ0_2 DDRB_CLK_N/DDR0_CLK_N_1 BF43 DDRA_CLK1 DDRA_CLK1# 18 DDRB_DQ2 AK49 DDRC_DQ0_1/DDR1_DQ0_1 DDRC_CLK_P/DDR1_CLK_P_0 M43 DDRB_CLK0 17
DDRA_DQ4 DDRA_DQ0_3/DDR0_DQ0_3 DDRB_CLK_P/DDR0_CLK_P_1 DDRA_CLK1 18 DDRB_DQ3 DDRC_DQ0_2/DDR1_DQ0_2 DDRD_CLK_N/DDR1_CLK_N_1
CA45 AG47 M42
DDRA_DQ5 BV47 DDRA_DQ0_4/DDR0_DQ0_4 BG49 DDRA_CKE0 DDRB_DQ4 AK47 DDRC_DQ0_3/DDR1_DQ0_3 DDRD_CLK_P/DDR1_CLK_P_1
DDRA_DQ6 DDRA_DQ0_5/DDR0_DQ0_5 DDRA_CKE0/DDR0_CKE0 DDRA_CKE0 18 DDRB_DQ5 DDRC_DQ0_4/DDR1_DQ0_4 DDRB_CKE0
BV45 BJ47 AG45 U45
DDRA_DQ7 BV48 DDRA_DQ0_6/DDR0_DQ0_6 DDRA_CKE1/NC BF38 DDRB_DQ6 AG48 DDRC_DQ0_5/DDR1_DQ0_5 DDRC_CKE0/DDR1_CKE0 V46 DDRB_CKE0 17
DDRA_DQ8 CC42 DDRA_DQ0_7/DDR0_DQ0_7 DDRB_CKE0/NC BF41 DDRA_CKE1 DDRB_DQ7 AG49 DDRC_DQ0_6/DDR1_DQ0_6 DDRC_CKE1/NC M41
DDRA_DQ9 DDRA_DQ1_0/DDR0_DQ1_0 DDRB_CKE1/DDR0_CKE1 DDRA_CKE1 18 DDRB_DQ8 DDRC_DQ0_7/DDR1_DQ0_7 DDRD_CKE0/NC
CC39 AJ38 P43
DDRA_DQ10 CC43 DDRA_DQ1_1/DDR0_DQ1_1 BM38 DDRA_CS0# DDRB_DQ9 AL39 DDRC_DQ1_0/DDR1_DQ1_0 DDRD_CKE1/DDR1_CKE1
DDRA_DQ11 CE38 DDRA_DQ1_2/DDR0_DQ1_2 DDRA_CS_0/DDR0_CS_N_0 BM42 DDRA_CS0# 18 DDRB_DQ10 AJ39 DDRC_DQ1_1/DDR1_DQ1_1 V42 DDRB_CS0#
DDRA_DQ12 DDRA_DQ1_3/DDR0_DQ1_3 DDRA_CS_1/NC DDRB_DQ11 DDRC_DQ1_2/DDR1_DQ1_2 DDRC_CS_0/DDR1_CS_N_0 DDRB_CS0# 17
CC38 BP42 AL43 V39
DDRA_DQ13 CE39 DDRA_DQ1_4/DDR0_DQ1_4 DDRB_CS_0/NC BG42 DDRA_CS1# DDRB_DQ12 AL38 DDRC_DQ1_3/DDR1_DQ1_3 DDRC_CS_1/NC Y39
DDRA_DQ14 DDRA_DQ1_5/DDR0_DQ1_5 DDRB_CS_1/DDR0_CS_N_1 DDRA_CS1# 18 DDRB_DQ13 DDRC_DQ1_4/DDR1_DQ1_4 DDRD_CS_0/NC
CE42 AJ42 T39
DDRA_DQ15 CE43 DDRA_DQ1_6/DDR0_DQ1_6 BM43 DDRA_BS0# DDRB_DQ14 AL42 DDRC_DQ1_5/DDR1_DQ1_5 DDRD_CS_1/DDR1_CS_N_1
DDRA_DQ16 DDRA_DQ1_7/DDR0_DQ1_7 DDRB_CA4/DDR0_BA0 DDRA_BS1# DDRA_BS0# 18 DDRB_DQ15 DDRC_DQ1_6/DDR1_DQ1_6 DDRB_BS0#
BT48 BG39 AJ43 T38
DDRA_DQ17 BT47 DDRA_DQ2_0/DDR0_DQ2_0 NC/DDR0_BA1 DDRA_BS1# 18 DDRB_DQ16 AB49 DDRC_DQ1_7/DDR1_DQ1_7 DDRD_CA4/DDR1_BA0 T42 DDRB_BS1# DDRB_BS0# 17
DDRA_DQ18 DDRA_DQ2_1/DDR0_DQ2_1 DDRA_BG0 DDRB_DQ17 DDRC_DQ2_0/DDR1_DQ2_0 NC/DDR1_BA1 DDRB_BS1# 17
BT49 BB49 AB48
DDRA_DQ19 DDRA_DQ2_2/DDR0_DQ2_2 DDRA_CA5/DDR0_BG0 DDRA_BG1 DDRA_BG0 18 DDRB_DQ18 DDRC_DQ2_1/DDR1_DQ2_1 DDRB_BG0
BN49 BD47 AE49 R45
DDRA_DQ20 DDRA_DQ2_3/DDR0_DQ2_3 NC/DDR0_BG1 DDRA_BG1 18 DDRB_DQ19 DDRC_DQ2_2/DDR1_DQ2_2 DDRC_CA5/DDR1_BG0 DDRB_BG1 DDRB_BG0 17
BT45 AE47 N47
DDRA_DQ21 DDRA_DQ2_4/DDR0_DQ2_4 DDRA_MA0 DDRB_DQ20 DDRC_DQ2_3/DDR1_DQ2_3 NC/DDR1_BG1 DDRB_BG1 17
BN47 BB48 AE48
DDRA_DQ22 DDRA_DQ2_5/DDR0_DQ2_5 NC/DDR0_MA0 DDRA_MA1 DDRA_MA0 18 DDRB_DQ21 DDRC_DQ2_4/DDR1_DQ2_4 DDRB_MA0

El
BN45 BL49 AB47 P42
DDRA_DQ23 BN48 DDRA_DQ2_6/DDR0_DQ2_6 NC/DDR0_MA1 BG38 DDRA_MA2 DDRA_MA1 18 DDRB_DQ22 AB45 DDRC_DQ2_5/DDR1_DQ2_5 NC/DDR1_MA0 Y49 DDRB_MA1 DDRB_MA0 17
DDRA_DQ24 DDRA_DQ2_7/DDR0_DQ2_7 DDRB_CA5/DDR0_MA2 DDRA_MA3 DDRA_MA2 18 DDRB_DQ23 DDRC_DQ2_6/DDR1_DQ2_6 NC/DDR1_MA1 DDRB_MA2 DDRB_MA1 17
BV42 BL45 AE45 U48
DDRA_DQ25 BV39 DDRA_DQ3_0/DDR0_DQ3_0 NC/DDR0_MA3 BJ46 DDRA_MA4 DDRA_MA3 18 DDRB_DQ24 AD38 DDRC_DQ2_7/DDR1_DQ2_7 DDRD_CA5/DDR1_MA2 Y45 DDRB_MA3 DDRB_MA2 17
DDRA_DQ26 DDRA_DQ3_1/DDR0_DQ3_1 NC/DDR0_MA4 DDRA_MA5 DDRA_MA4 18 DDRB_DQ25 DDRC_DQ3_0/DDR1_DQ3_0 NC/DDR1_MA3 DDRB_MA4 DDRB_MA3 17
BV43 BG48 AD39 U47
DDRA_DQ27 BW38 DDRA_DQ3_2/DDR0_DQ3_2 DDRA_CA0/DDR0_MA5 BE45 DDRA_MA6 DDRA_MA5 18 DDRB_DQ26 AE39 DDRC_DQ3_1/DDR1_DQ3_1 NC/DDR1_MA4 R49 DDRB_MA5 DDRB_MA4 17
DDRA_DQ28 DDRA_DQ3_3/DDR0_DQ3_3 DDRA_CA2/DDR0_MA6 DDRA_MA7 DDRA_MA6 18 DDRB_DQ27 DDRC_DQ3_2/DDR1_DQ3_2 DDRC_CA0/DDR1_MA5 DDRB_MA6 DDRB_MA5 17
BV38 BG45 AE43 U49
DDRA_DQ29 DDRA_DQ3_4/DDR0_DQ3_4 DDRA_CA4/DDR0_MA7 DDRA_MA8 DDRA_MA7 18 DDRB_DQ28 DDRC_DQ3_3/DDR1_DQ3_3 DDRC_CA2/DDR1_MA6 DDRB_MA7 DDRB_MA6 17
BW39 BG47 AE38 M47
DDRA_DQ30 BW42 DDRA_DQ3_5/DDR0_DQ3_5 DDRA_CA3/DDR0_MA8 BE47 DDRA_MA9 DDRA_MA8 18 DDRB_DQ29 AD43 DDRC_DQ3_4/DDR1_DQ3_4 DDRC_CA4/DDR1_MA7 M45 DDRB_MA8 DDRB_MA7 17
DDRA_DQ3_6/DDR0_DQ3_6 DDRA_CA1/DDR0_MA9 DDRA_MA9 18 DDRC_DQ3_5/DDR1_DQ3_5 DDRC_CA3/DDR1_MA8 DDRB_MA8 17

et
DDRA_DQ31 BW43 BJ38 DDRA_MA10 DDRB_DQ30 AD42 R47 DDRB_MA9
DDRA_DQ32 AY48 DDRA_DQ3_7/DDR0_DQ3_7 NC/DDR0_MA10 BB47 DDRA_MA11 DDRA_MA10 18 DDRB_DQ31 AE42 DDRC_DQ3_6/DDR1_DQ3_6 DDRC_CA1/DDR1_MA9 P39 DDRB_MA10 DDRB_MA9 17
DDRA_DQ33 DDRB_DQ0_0/DDR0_DQ4_0 NC/DDR0_MA11 DDRA_MA12 DDRA_MA11 18 DDRB_DQ32 DDRC_DQ3_7/DDR1_DQ3_7 NC/DDR1_MA10 DDRB_MA11 DDRB_MA10 17
AY47 BE48 J48 N46
DDRA_DQ34 DDRB_DQ0_1/DDR0_DQ4_1 NC/DDR0_MA12 DDRA_MA13 DDRA_MA12 18 DDRB_DQ33 DDRD_DQ0_0/DDR1_DQ4_0 NC/DDR1_MA11 DDRB_MA12 DDRB_MA11 17
AY49 BM39 J45 R48
DDRA_DQ35 DDRB_DQ0_2/DDR0_DQ4_2 DDRB_CA0/DDR0_MA13 DDRA_MA14_WE# DDRA_MA13 18 DDRB_DQ34 DDRD_DQ0_1/DDR1_DQ4_1 NC/DDR1_MA12 DDRB_MA13 DDRB_MA12 17
AU45 BG43 J49 Y41
DDRA_DQ36 DDRB_DQ0_3/DDR0_DQ4_3 DDRB_CA2/DDR0_MA14WE_N DDRA_MA15_CAS# DDRA_MA14_WE# 18 DDRB_DQ35 DDRD_DQ0_2/DDR1_DQ4_2 DDRD_CA0/DDR1_MA13 DDRB_MA14_WE# DDRB_MA13 17
AY45 BJ42 G47 V41
DDRA_DQ37 AU47 DDRB_DQ0_4/DDR0_DQ4_4 DDRB_CA1/DDR0_MA15CAS_N BM41 DDRA_MA16_RAS# DDRA_MA15_CAS# 18 DDRB_DQ36 J47 DDRD_DQ0_3/DDR1_DQ4_3 DDRD_CA2/DDR1_MA14WE_N Y42 DDRB_MA15_CAS# DDRB_MA14_WE# 17
DDRA_DQ38 AU48 DDRB_DQ0_5/DDR0_DQ4_5 DDRB_CA3/DDR0_MA16RAS_N DDRA_MA16_RAS# 18 DDRB_DQ37 G45 DDRD_DQ0_4/DDR1_DQ4_4 DDRD_CA1/DDR1_MA15CAS_N V47 DDRB_MA16_RAS# DDRB_MA15_CAS# 17
C C
DDRA_DQ39 DDRB_DQ0_6/DDR0_DQ4_6 DDRA_ODT0 DDRB_DQ38 DDRD_DQ0_5/DDR1_DQ4_5 DDRD_CA3/DDR1_MA16RAS_N DDRB_MA16_RAS# 17

ro
AU49 BJ39 G48
DDRA_DQ40 DDRB_DQ0_7/DDR0_DQ4_7 NC/DDR0_ODT_0 DDRA_ODT1 DDRA_ODT0 18 DDRB_DQ39 DDRD_DQ0_6/DDR1_DQ4_6 DDRB_ODT0
AY42 BB45 E48 V43
DDRA_DQ41 AY38 DDRB_DQ1_0/DDR0_DQ5_0 NC/DDR0_ODT_1 DDRA_ODT1 18 DDRB_DQ40 J38 DDRD_DQ0_7/DDR1_DQ4_7 NC/DDR1_ODT_0 V38 DDRB_ODT0 17
DDRA_DQ42 AY43 DDRB_DQ1_1/DDR0_DQ5_1 BY47 DDRA_DQS#0 DDRB_DQ41 G39 DDRD_DQ1_0/DDR1_DQ5_0 NC/DDR1_ODT_1
DDRA_DQ43 BB39 DDRB_DQ1_2/DDR0_DQ5_2 DDRA_DQSN_0/DDR0_DQSN_0 BY46 DDRA_DQS0 DDRB_DQ42 G38 DDRD_DQ1_1/DDR1_DQ5_1 AH46 DDRB_DQS#0
DDRA_DQ44 AY39 DDRB_DQ1_3/DDR0_DQ5_3 DDRA_DQSP_0/DDR0_DQSP_0 CC41 DDRA_DQS#1 DDRB_DQ43 G42 DDRD_DQ1_2/DDR1_DQ5_2 DDRC_DQSN_0/DDR1_DQSN_0 AH47 DDRB_DQS0
DDRA_DQ45 BB38 DDRB_DQ1_4/DDR0_DQ5_4 DDRA_DQSN_1/DDR0_DQSN_1 CE41 DDRA_DQS1 DDRB_DQ44 J39 DDRD_DQ1_3/DDR1_DQ5_3 DDRC_DQSP_0/DDR1_DQSP_0 AJ41 DDRB_DQS#1
DDRA_DQ46 BB42 DDRB_DQ1_5/DDR0_DQ5_5 DDRA_DQSP_1/DDR0_DQSP_1 BR47 DDRA_DQS#2 DDRB_DQ45 J42 DDRD_DQ1_4/DDR1_DQ5_4 DDRC_DQSN_1/DDR1_DQSN_1 AL41 DDRB_DQS1
DDRA_DQ47 BB43 DDRB_DQ1_6/DDR0_DQ5_6 DDRA_DQSN_2/DDR0_DQSN_2 BR46 DDRA_DQS2 DDRB_DQ46 G43 DDRD_DQ1_5/DDR1_DQ5_5 DDRC_DQSP_1/DDR1_DQSP_1 AC47 DDRB_DQS#2
DDRA_DQ48 DDRB_DQ1_7/DDR0_DQ5_7 DDRA_DQSP_2/DDR0_DQSP_2 DDRA_DQS#3 DDRB_DQ47 DDRD_DQ1_6/DDR1_DQ5_6 DDRC_DQSN_2/DDR1_DQSN_2 DDRB_DQS2

-X
AR48 BV41 J43 AC46
DDRA_DQ49 AR47 DDRB_DQ2_0/DDR0_DQ6_0 DDRA_DQSN_3/DDR0_DQSN_3 BW41 DDRA_DQS3 DDRB_DQ48 B43 DDRD_DQ1_7/DDR1_DQ5_7 DDRC_DQSP_2/DDR1_DQSP_2 AE41 DDRB_DQS#3
DDRA_DQ50 AR49 DDRB_DQ2_1/DDR0_DQ6_1 DDRA_DQSP_3/DDR0_DQSP_3 AV46 DDRA_DQS#4 DDRB_DQ49 D43 DDRD_DQ2_0/DDR1_DQ6_0 DDRC_DQSN_3/DDR1_DQSN_3 AD41 DDRB_DQS3
DDRA_DQ51 AM45 DDRB_DQ2_2/DDR0_DQ6_2 DDRB_DQSN_0/DDR0_DQSN_4 AV47 DDRA_DQS4 DDRB_DQ50 A43 DDRD_DQ2_1/DDR1_DQ6_1 DDRC_DQSP_3/DDR1_DQSP_3 H47 DDRB_DQS#4
DDRA_DQ52 AR45 DDRB_DQ2_3/DDR0_DQ6_3 DDRB_DQSP_0/DDR0_DQSP_4 AY41 DDRA_DQS#5 DDRB_DQ51 C40 DDRD_DQ2_2/DDR1_DQ6_2 DDRD_DQSN_0/DDR1_DQSN_4 H46 DDRB_DQS4
DDRA_DQ53 AM47 DDRB_DQ2_4/DDR0_DQ6_4 DDRB_DQSN_1/DDR0_DQSN_5 BB41 DDRA_DQS5 DDRB_DQ52 C43 DDRD_DQ2_3/DDR1_DQ6_3 DDRD_DQSP_0/DDR1_DQSP_4 G41 DDRB_DQS#5

https://vinafix.com
DDRA_DQ54 AM48 DDRB_DQ2_5/DDR0_DQ6_5 DDRB_DQSP_1/DDR0_DQSP_5 AN46 DDRA_DQS#6 DDRB_DQ53 D40 DDRD_DQ2_4/DDR1_DQ6_4 DDRD_DQSN_1/DDR1_DQSN_5 J41 DDRB_DQS5
DDRA_DQ55 AM49 DDRB_DQ2_6/DDR0_DQ6_6 DDRB_DQSN_2/DDR0_DQSN_6 AN47 DDRA_DQS6 DDRB_DQ54 B40 DDRD_DQ2_5/DDR1_DQ6_5 DDRD_DQSP_1/DDR1_DQSP_5 C42 DDRB_DQS#6
DDRA_DQ56 AT42 DDRB_DQ2_7/DDR0_DQ6_7 DDRB_DQSP_2/DDR0_DQSP_6 AR41 DDRA_DQS#7 DDRB_DQ55 A40 DDRD_DQ2_6/DDR1_DQ6_6 DDRD_DQSN_2/DDR1_DQSN_6 D42 DDRB_DQS6
DDRA_DQ57 AT39 DDRB_DQ3_0/DDR0_DQ7_0 DDRB_DQSN_3/DDR0_DQSN_7 AT41 DDRA_DQS7 DDRB_DQ56 B35 DDRD_DQ2_7/DDR1_DQ6_7 DDRD_DQSP_2/DDR1_DQSP_6 D36 DDRB_DQS#7

Te
DDRA_DQ58 AR43 DDRB_DQ3_1/DDR0_DQ7_1 DDRB_DQSP_3/DDR0_DQSP_7 DDRB_DQ57 D35 DDRD_DQ3_0/DDR1_DQ7_0 DDRD_DQSN_3/DDR1_DQSN_7 C36 DDRB_DQS7
DDRA_DQ59 AT38 DDRB_DQ3_2/DDR0_DQ7_2 BF39 DDRA_PAR DDRB_DQ58 A35 DDRD_DQ3_1/DDR1_DQ7_1 DDRD_DQSP_3/DDR1_DQSP_7
DDRA_DQ60 DDRB_DQ3_3/DDR0_DQ7_3 NC/DDR0_PAR DDRA_ACT# DDRA_PAR 18 DDRB_DQ59 DDRD_DQ3_2/DDR1_DQ7_2 DDRB_PAR
AR38 BE49 D38 P38
DDRA_DQ61 DDRB_DQ3_4/DDR0_DQ7_4 NC/DDR0_ACT_N DDRA_ALERT# DDRA_ACT# 18 DDRB_DQ60 DDRD_DQ3_3/DDR1_DQ7_3 NC/DDR1_PAR DDRB_ACT# DDRB_PAR 17
AR39 BD46 C35 M48
DDRA_DQ62 AR42 DDRB_DQ3_5/DDR0_DQ7_5 NC/DDR0_ALERT_N DDRA_ALERT# 18 DDRB_DQ61 C38 DDRD_DQ3_4/DDR1_DQ7_4 NC/DDR1_ACT_N M49 DDRB_ALERT# DDRB_ACT# 17
DDRA_DQ63 DDRB_DQ3_6/DDR0_DQ7_6 DDRB_DQ62 DDRD_DQ3_5/DDR1_DQ7_5 NC/DDR1_ALERT_N DDRB_ALERT# 17
AT43 M38 B38
DDRB_DQ3_7/DDR0_DQ7_7 RSVD_73 C44 DDR_SA_VREFCA DDRB_DQ63 A38 DDRD_DQ3_6/DDR1_DQ7_6
2 1/20W_100_1%_0201 DDR_RCOMP_0 DDR0_VREF_CA DDR_SB_VREFCA DDR_SA_VREFCA 18 DDRD_DQ3_7/DDR1_DQ7_7
RC501 1 D47 B45
DDR_RCOMP_0 DDR1_VREF_CA DDR_SB_VREFCA 17
RC502 1 2 1/20W_100_1%_0201 DDR_RCOMP_1 E46 M39 DDR_VTT_CNTL 3 of 19
2 1/20W_100_1%_0201 DDR_RCOMP_2 DDR_RCOMP_1 DDR_VTT_CTL CPU_DRAMRST#_R ICELAKE-U_BGA1526
RC503 1 C47 DK47
DDR_RCOMP_2 2 of 19 DRAM_RESET_N @

ch
ICELAKE-U_BGA1526
@

B B

ni
+3VALW

1
RC504
100K_0402_5%

ca 2
+1.2V
CPU_DRAMPG_CNTL 55
+1.2V
1

1
RC505 RC506 C
1/16W_470_1%_0402 1 2 2 QC501
1K_0402_5% B MMBT3904WH_SOT323-3

l
E
RC507
2

3
CPU_DRAMRST#_R 1 2
CPU_DRAMRST# 17,18
0_0402_5% DDR_VTT_CNTL
@ 1
CC501

2
0.1U_6.3V_K_X5R_0201
@
2 RC508
10K_0402_5%
@

1
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/12/04 Deciphered Date 2018/08/20 S740-ICL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Name Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday, December 06, 2019 Sheet 5 of 60
5 4 3 2 1
 5 4 3 2 1

+VCCSTG_TERM

RC601 1 2 51_0402_5% PCH_JTAG_TDO_CPU

RC602 1 @ 2 51_0402_5% PCH_JTAG_TDI_CPU

RC603 1 @ 2 51_0402_5% PCH_JTAG_TMS_CPU

RC604 1 2 1K_0402_5% H_PROCHOT#

RC605 1 2 51_0402_5% PCH_TCK_JTAGX_CPU

D D
UC1D

CATERR# J4 P3 PCH_TCK_JTAGX_CPU
H_PECI CD5 CATERR_N PROC_TCK K5 PCH_JTAG_TDI_CPU
44 H_PECI PECI PROC_TDI
+3VALW_PCH RC606 1 2 499_0402_1% H_PROCHOT#_R C3 K3 PCH_JTAG_TDO_CPU
13,44,55 H_PROCHOT# H_THRMTRIP# PROCHOT_N PROC_TDO PCH_JTAG_TMS_CPU
E3 P4
RC607 1 2 100K_0402_5% GPP_E6 THRMTRIP_N PROC_TMS N1 XDP_TRST_CPU_N 1 TP601 @
RC608 1 2 1/20W_49.9_1%_0201 PROC_OPI_RCOMP CJ41 PROC_TRST_N
RC609 1 @ 2 4.7K_0402_5% RC610 1 2 1/20W_49.9_1%_0201 PCH_OPI_RCOMP DU3 PROC_POPIRCOMP N5 XDP_TRST_CPU_N
RC611 1 @ 2 1/20W_49.9_1%_0201 EDRAM_OPIO_RCOMP A14 PCH_OPIRCOMP PCH_TRST_N R5 PCH_JTAG_TCK 1 TP602 @
RC612 1 @ 2 1/20W_49.9_1%_0201 CPU_EOPIO_RCOMP B14 RSVD_25 PCH_TCK K1 PCH_JTAG_TDI_CPU
RSVD_26 PCH_TDI K2 PCH_JTAG_TDO_CPU
DBG_PMODE DL15 PCH_TDO N3 PCH_JTAG_TMS_CPU
PM_SLP_S0IX_R_N: DBG_PMODE PCH_TMS N2 PCH_TCK_JTAGX_CPU
External pull-up is required. PCH_JTAGX
This strap should sample HIGH. There should NOT be DV11
44 EC_SCI# GPP_E3/CPU_GP0 PROC_PRDY_N
any on-board device driving it to opposite direction DT11 P6 1 TP603 @
44 EC_SMI CR38 GPP_E7/CPU_GP1 PROC_PRDY_N M6 PROC_PREQ_N 1
during strap sampling. TP604 @
CR39 GPP_B3/CPU_GP2 PROC_PREQ_N
GPP_B4/CPU_GP3
GPP_E6 DT12
RC613 1 @ 2 0_0201_5% GPP_H2 DJ38 GPP_E6
40 PCIE_WAKE#_WLAN_R GPP_H2/CNV_BT_I2S_SDO

El
DL38
+3VALW_PCH GPP_H19/TIME_SYNC0

1 @ 2 1/20W_4.7K_5%_0201 GPP_H2 ICELAKE-U_BGA1526

RC614
@ 4 of 19

GPP_H2(PCIE_WAKE#_WLAN_R):
This signal has a 20K+/-30% internal pull-down.

et
0 = Master Attached Flash Sharing (MAFS) is enabled. (Default)
1 = Slave Attached Flash Sharing (SAFS) is enabled.
Notes:
1. The internal pull-down is disabled after RSMRST# de-asserts.
2. This signal is in the primary well

C C

ro
+VCCST_CPU

RC615 1 2 1K_0402_5% H_THRMTRIP#

RC616 1 @ 2 1/20W_49.9_1%_0201 CATERR#

-X
+3VS
UC1G
RC617 1 2 10K_0402_5% EC_SCI# CE46
RC618 1 2 1/20W_33_1%_0201 HDA_BCLK_R CY46 GPP_G6/SD_CLK CC48
30 HDA_BITCLK_AUDIO HDA_SYNC_R GPP_R0/HDA_BCLK/I2S0_SCLK GPP_G1/SD_DATA0
RC619 1 2 1/20W_33_1%_0201 CV49 CC49
30 HDA_SYNC_AUDIO 1 2 1/20W_33_1%_0201 HDA_SDO_R CY47 GPP_R1/HDA_SYNC/I2S0_SFRM GPP_G2/SD_DATA1 CC47
RC620

https://vinafix.com
30 HDA_SDOUT_AUDIO HDA_SDIN0 GPP_R2/HDA_SDO/I2S0_TXD GPP_G3/SD_DATA2
CV45 CF45
30 HDA_SDIN0 GPP_R3/HDA_SDI0/I2S0_RXD GPP_G4/SD_DATA3
DA47 CC45
GPP_R4/HDA_RST_N GPP_G0/SD_CMD CF49
SD3.0
+1.8VALW_PCH DP33 GPP_G7/SD_WP CE47

Te
GPP_D19/I2S_MCLK GPP_G5/SD_CD_N
DC45 DK38
GPP_A23/I2S1_SCLK GPP_H0/CNV_BT_I2S_SDO @
1

DA49 DG38 WIFI_WAKE_N RC621 1 2 0_0201_5% PCIE_WAKE#_WLAN_R

RC622 DA45 GPP_R5/HDA_SDI1/I2S1_SFRM GPP_H1/SD_PWR_EN_N/CNV_BT_I2S_SDO
DA48 GPP_R6/I2S1_TXD CJ43 SD_COMP RC623 1 2 1/20W_200_1%_0201
4.7K_0402_5%
CT49 GPP_R7/I2S1_RXD SD3_RCOMP
@ RC624 1 2 33_0402_5% CNVI_RF_RESET#_PCH CT48 GPP_A7/I2S2_SCLK
2

HDA_SDO_R 0_0402_5% 2 1 RC625 40 CNVI_RF_RESET# CV47 GPP_A8/I2S2_SFRM/CNV_RF_RESET_N DG36

ME_FLASH 44 CNVI_MODEM_CLKREQ_PCH CT47 GPP_A10/I2S2_RXD GPP_S6/SNDW4_CLK/DMIC_CLK0
RC626 1 2 33_0402_5% DG34
40 CNVI_MODEM_CLKREQ GPP_A9/I2S2_TXD/MODEM_CLKREQ GPP_S7/SNDW4_DATA/DMIC_DATA0
GPP_R2(HDA_SDO_R): SNDW_RCOMP
This signal has a 20K ±30% internal pull-down. CY39 CV38 RC627 1 2 1/20W_200_1%_0201
CY38 GPP_S0/SNDW1_CLK SNDW_RCOMP

ch
0 = Enable security measures defined in the Flash Descriptor. (Default) GPP_S1/SNDW1_DATA
1 = Disable Flash Descriptor Security (override). This strap should only AUDIO
be asserted high using external Pull-up in manufacturing/debug DB39
DD38 GPP_S2/SNDW2_CLK
environments ONLY. GPP_S3/SNDW2_DATA
Notes: DF38
1. The internal pull-down is disabled after PCH_PWROK is high. DD39 GPP_S4/SNDW3_CLK/DMIC_CLK1
B 2. This signal is in the primary well. GPP_S5/SNDW3_DATA/DMIC_DATA1 B

ICELAKE-U_BGA1526 7 of 19

ni
@

39P_50V_J_NPO_0402 2 1 CC601 HDA_BCLK_R

@ 2P_25V_C_NPO_0201 2 1 CC602 HDA_SYNC_R

ca
@ 2P_25V_C_NPO_0201 2 1 CC603 HDA_SDO_R

@ 10P_0201_50V8F 2 1 CC605 HDA_SDIN0

75K_0402_1% 2 1 RC631 CNVI_RF_RESET#_PCH

EMC_NS@ 33P_0201_50V8-J 2 1 CC604 CNVI_MODEM_CLKREQ_PCH

l
+3VALW_PCH

RC632 1 @ 2 100K_0201_5% DBG_PMODE

A RC633 1 @ 2 1K_0201_5% A

DBG_PMODE(Reserved): Rising edge of RSMRST#

This strap has a 20 kohm ± 30% internal pull-up.
This strap should sample high. There should NOT be
any on-board device driving it to opposite direction
during strap sampling.
Notes:
1. The internal pull-up is disabled after RSMRST# deasserts.
2. This signal is in the primary well. Security Classification LC Future Center Secret Data Title

Issued Date 2018/12/04 Deciphered Date 2018/08/20 S740-ICL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Name Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday, December 06, 2019 Sheet 6 of 60
5 4 3 2 1
 5 4 3 2 1

UC1E
PCH_SPI_CLK DB42
PCH_SPI_SI DD43 SPI0_CLK DK27 PCH_SMB_CLK
PCH_SPI_SO SPI0_MOSI GPP_C0/SMBCLK PCH_SMB_DATA

SMBUS
DF43 DP24
PCH_SPI_IO2 SPI0_MISO GPP_C1/SMBDATA PCH_SMB_ALERT#

SPI 0
DF42 DL24
D PCH_SPI_IO3 DD41 SPI0_IO2 GPP_C2/SMBALERT_N D
PCH_SPI_CS0# DB43 SPI0_IO3
DF41 SPI0_CS0_N DK24 PCH_SML0_CLK
DB41 SPI0_CS1_N GPP_C3/SML0CLK DJ24 PCH_SML0_DATA

SML 0
SPI0_CS2_N GPP_C4/SML0DATA DP22 PCH_SML0_ALERT#
GPP_C5/SML0ALERT_N
DV16
DT16 GPP_E11/SPI1_CLK/BK1/SBK1 DN22 PCH_SML1_CLK
GPP_E13/SPI1_MOSI/BK3/SBK3 GPP_C6/SML1CLK/SUSWARN_N/SUSPWRDNACK

SML1
PCH_SML1_DATA

SPI 1
DU18 DL22
DT18 GPP_E12/SPI1_MISO/BK2/SBK2 GPP_C7/SML1DATA/SUSACK_N
DW18 GPP_E1/SPI1_IO2
DW16 GPP_E2/SPI1_IO3 CR47 ESPI_CLK_R RC702 2 1 1/20W_49.9_1%_0201
+3VALW_PCH GPP_E10/SPI1_CS_N/BK0/SBK0 GPP_A5/ESPI_CLK ESPI_IO0_R ESPI_CLK 44
DU16 CN45 RC703 1 2 1/20W_10_1%_0201
GPP_E8/SATALED_N/SPI1_CS1_N GPP_A0/ESPI_IO0 ESPI_IO1_R ESPI_IO0 44
CN48 RC704 1 2 1/20W_10_1%_0201
GPP_A1/ESPI_IO1 ESPI_IO2_R ESPI_IO1 44
CN49 RC705 1 2 1/20W_10_1%_0201
ESPI_IO2 44

eSPI
DV19 GPP_A2/ESPI_IO2 CN47 ESPI_IO3_R RC706 1 2 1/20W_10_1%_0201

MLINK
DW19 CL_CLK GPP_A3/ESPI_IO3 CT45 ESPI_CS#_R 1 2 ESPI_IO3 44
RPC701 RC707 0_0402_5% @
PCH_SML0_CLK CL_DATA GPP_A4/ESPI_CS_N ESPI_CS# 44
4 1 DT19 CR46
PCH_SML0_DATA CL_RST_N GPP_A6/ESPI_RESET_N ESPI_RST# 44
3 2 GPP_C2(PCH_SMB_ALERT#):
This signal is used to wake the system or generate SMI#.
2.2K_0404_4P2R_5% External Pull-up resistor is required.Rising edge of RSMRST#

El
RPC702 This signal has a 20K+/-30% internal pull-down. ICELAKE-U_BGA1526 5of 19
PCH_SML1_CLK 0 = Disable Intel ME Crypto Transport Layer Security (TLS)
2 3 cipher suite (no confidentiality). (Default) @
1 4 PCH_SML1_DATA
1 = Enable Intel ME Crypto Transport Layer Security (TLS)
2.2K_0404_4P2R_5%
cipher suite (with confidentiality). Must be
pulled up to support Intel AMT with TLS.
RC708 1 2 4.7K_0402_5% PCH_SMB_ALERT# Notes: +3VALW_PCH
1. The internal pull-down is disabled after RSMRST# de-asserts. +3VS
2. This signal is in the primary well.

et
RC701 1 @ 2 4.7K_0402_5% PCH_SML0_ALERT#
+3VS
GPP_C5(PCH_SML0_ALERT#):
Rising edge of RSMRST#

4
3

4
3
This signal has a 20K+/-30% internal pull-down.
0 = Enable eSPI. (Default) RPC703 RPC704

2
1 = Disable eSPI. 2.2K_0404_4P2R_5% 2.2K_0404_4P2R_5%

G
C C
Notes:

ro
QC701A
1. The internal pull-down is disabled after RSMRST# de-asserts.

1
2

1
2
2. This signal is in the primary well PCH_SMB_CLK 6 1

S
SMB_CLK_S3 18

D
2N7002KDWH_SOT363-6

5
G
+1.8VALW_PCH
QC701B
ESPI_CS# PCH_SMB_DATA

-X
1K_0402_5% 2 @ 1 RC709 3 4

S
SMB_DATA_S3 18

D
75K_0402_1% 2 @ 1 RC710 2N7002KDWH_SOT363-6

https://vinafix.com

Te
ESPI_RST# RC712 1 2 75K_0402_1%

@ CC701 1 2 0.033UC_10VC_KC_X5RC_0201

ch
+3VALW_PCH +3V_SPI

Vinafix.com
RC711 1 2 0_0402_5% @

DC701
B B
2 1
+3VALW_PCH
2 1

ni
RB521CM-30T2R_VMN2M-2
150K_0402_5% 2 @ 1 RC714 PCH_SPI_CS0# RC715 1 2 0_0402_5% @ SPI_CS# @

100K_0402_5% 2 1 RC716 PCH_SPI_SI RC717 1 2 49.9_0402_1% SPI_SI

100K_0402_5% 2 1 RC718 PCH_SPI_IO2 RC719 1 2 49.9_0402_1% SPI_IO2 +3V_SPI

ca
100K_0402_5% 2 1 RC720 PCH_SPI_IO3 RC721 1 2 49.9_0402_1% SPI_IO3
1
PCH_SPI_SI / PCH_SPI_WP#(IO2) / PCH_SPI_HOLD#(IO3):
External pull-up is required. Recommend 100K if pulled CC702
up to 3.3V or 75K if pulled up to 1.8V. 0.1U_6.3V_K_X5R_0201
UC702 2
This strap should sample HIGH. There should NOT be SPI_CS#
any on-board device driving it to opposite direction 1 8
44 SPI_CS# /CS VCC
during strap sampling. SPI_SO 2 7 SPI_IO3
44 SPI_SO DO(IO1) /HOLD(IO3)

l
SPI_IO2 3 6 SPI_CLK
/WP(IO2) CLK SPI_CLK 44
4 5 SPI_SI
GND DI(IO0) SPI_SI 44

PCH_SPI_SO RC722 1 2 49.9_0402_1% SPI_SO RC723 1 @ 2 100K_0402_5% W25Q128JVSIQ_SO8

PCH_SPI_CLK RC724 1 2 49.9_0402_1% SPI_CLK CC703 1 2 5P_50V_B_NPO_0402
EMC_NS@

RC713 1 2 100K_0402_5%

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/12/04 Deciphered Date 2018/08/20 S740-ICL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Name Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday, December 06, 2019 Sheet 7 of 60
5 4 3 2 1
 5 4 3 2 1

+3VS
RPC801
PCH_I2C1_SDA_TP 1 4
PCH_I2C1_SCL_TP 2 3

UC1F 2.2K_0404_4P2R_5%
PCH_TP_INT# RC801 1 2 10K_0402_5%
PCH_TP_INT# CH48 DV33
45 PCH_TP_INT# GPP_B18 GPP_B16/GSPI0_CLK GPP_D13/ISH_UART0_RXD FPR_DELINK
CF48 DW33
PCH_WLAN_PERST# GPP_B18/GSPI0_MOSI GPP_D14/ISH_UART0_TXD FPR_RESET_C FPR_DELINK 45
CF47 DT33 RC852 1 2 0_0402_5% @ +3VS
40 PCH_WLAN_PERST# PCH_WLAN_OFF# GPP_B17/GSPI0_MISO GPP_D15/ISH_UART0_RTS_N/GSPI2_CS1_N/IMGCLKOUT5 FPR_RESET 45
CH49 DU33
D 40 PCH_WLAN_OFF# PCH_BEEP GPP_B15/GSPI0_CS0_N GPP_D16/ISH_UART0_CTS_N/CNV_WCEN UART2_TXD D
CH47 RC802 1 2 49.9K_0402_1%
30 PCH_BEEP GPP_B14/SPKR/TIME_SYNC1/GSPI0_CS1_N DK22 FB_GC6_EN_R UART2_RXD 1 2 49.9K_0402_1%
FB_GC6_EN_R 23,26 RC803
CL47 GPP_C12/UART1_RXD/ISH_UART1_RXD DW24 GPU_EVENT#
GPP_B20/GSPI1_CLK GPP_C13/UART1_TXD/ISH_UART1_TXD PXS_PWREN_R GPU_EVENT# 26 FPR_DELINK
CK47 DV24 RC804 1 OPT@ 2 1K_0201_5% RC890 1 @ 2 2.2K_0402_5%
GPP_B22/GSPI1_MOSI GPP_C14/UART1_RTS_N/ISH_UART1_RTS_N PXS_RST#_R PXS_PWREN 23
CK46 DU24 RC805 1 2 0_0402_5% @
GPP_B21/GSPI1_MISO GPP_C15/UART1_CTS_N/ISH_UART1_CTS_N PXS_RST# 26
CH45
SML1_ALERT# CL48 GPP_B19/GSPI1_CS0_N CN43
GPP_B23/SML1ALERT_N/PCHHOT_N/GSPI1_CS1_N GPP_B5/ISH_I2C0_SDA CN42
DGPU_PWROK DP21 GPP_B6/ISH_I2C0_SCL
23,58 DGPU_PWROK DK21 GPP_C8/UART0_RXD CN41
DL21 GPP_C9/UART0_TXD GPP_B7/ISH_I2C1_SDA CL43
DJ22 GPP_C10/UART0_RTS_N GPP_B8/ISH_I2C1_SCL
GPP_C11/UART0_CTS_N CL41
UART2_RXD DT22 GPP_B9/I2C5_SDA/ISH_I2C2_SDA CJ39
UART2_TXD DW22 GPP_C20/UART2_RXD GPP_B10/I2C5_SCL/ISH_I2C2_SCL DU36
DEBUG GPP_C21/UART2_TXD GPP_D0/ISH_GP0
DV22 DV36
DU22 GPP_C22/UART2_RTS_N GPP_D1/ISH_GP1 DW36
GPP_C23/UART2_CTS_N GPP_D2/ISH_GP2 DT36
DT24 GPP_D3/ISH_GP3 DU34
DT23 GPP_C16/I2C0_SDA GPP_D17/ISH_GP4 DW34
TS GPP_C17/I2C0_SCL GPP_D18/ISH_GP5 DT14
PCH_I2C1_SDA_TP GPP_E15/ISH_GP6

El
DW23 DU14
45 PCH_I2C1_SDA_TP PCH_I2C1_SCL_TP DU23 GPP_C18/I2C1_SDA GPP_E16/ISH_GP7
TP 45 PCH_I2C1_SCL_TP GPP_C19/I2C1_SCL
DU41
DV41 GPP_H4/I2C2_SDA
SENSOR GPP_H5/I2C2_SCL
DW41
DT41 GPP_H6/I2C3_SDA +3VS
GPP_H7/I2C3_SCL

et
DT40 PXS_PWREN_R RC807 1 OPT@ 2 10K_0201_5%
DW40 GPP_H8/I2C4_SDA/CNV_MFUART2_RXD
GPP_H9/I2C4_SCL/CNV_MFUART2_TXD RC808 1 @ 2 10K_0201_5%
6 of 19
ICELAKE-U_BGA1526
@

C C
+3VS

ro
PXS_RST#_R RC809 1 @ 2 10K_0201_5%

RC810 1 OPT@ 2 10K_0201_5%

RC811 1 @ 2 100K_0201_5% PCH_WLAN_PERST#

FB_GC6_EN_R

-X
RC812 1 @ 2 10K_0201_5%

https://vinafix.com
+3VS
+3VALW_PCH +3VS +3VS
GPU_EVENT# RC813 1 OPT@ 2 10K_0201_5%
RC814 1 @ 2 1/20W_150K_5%_0201 SML1_ALERT# RC815 1 @ 2 4.7K_0402_5% PCH_BEEP RC816 1 @ 2 1/20W_4.7K_5%_0201 GPP_B18

Te
RC817 1 @ 2 10K_0201_5%
RC818 1 2 1/20W_20K_5%_0201 GPP_B14(PCH_BEEP): RC819 1 @ 2 1/20W_20K_5%_0201
Rising edge of PCH_PWROK
The strap has a 20 kohm ± 30% internal pull-down.
0 = Disable Top Swap mode. (Default) PXS_RST#
GPP_B23(SML1_ALERT#): 1 = Enable Top Swap mode. This inverts an address on access to SPI GPP_B18:Rising edge of PCH_PWROK CC801 1 2 0.01U_6.3V_K_X7R_0201
This signal has a 20K+-30% internal pull-down. The signal has a weak internal pull-down.
0 = 38.4 MHz clock (direct from crystal) (default) and firmware hub, so the processor believes it fetches the alternate
1 = 19.2 MHz clock (derived from 38.4 MHz crystal) boot block instead of the original boot-block. PCH will invert A16 0 = Disable No Reboot mode. (Default) OPT@
Notes: (default) for cycles going to the upper two 64-KB blocks in the FWH 1 = Enable No Reboot mode (PCH will disable the
1. The internal pull-down is disabled after RSMRST# de-asserts or the appropriate address lines (A16, A17, or A18) as selected TCO Timer system reboot feature). This function is
2.When used as PCHHOT# and strap low, a 150K pull-up
in Top Swap Block size soft strap. useful when running ITP/XDP. DGPU_PWROK RC820 1 UMA@ 2 10K_0201_5%

ch
is needed to ensure it does not override the internal pull-down
strap sampling. Notes: Notes:
3. This signal is in the primary well 1. The internal pull-down is disabled after PCH_PWROK is high. 1. The internal pull-down is disabled after CC1445 1 2 0.01U_6.3V_K_X7R_0201
2. Software will not be able to clear the Top Swap bit until the system PCH_PWROK is high. EMC_NS@
is rebooted. 2. This signal is in the primary well.
3. The status of this strap is readable using the Top Swap bit
(Bus0, Device31, Function0, offset DCh, bit4).
B B
4. This signal is in the primary well.

ni
ca
l
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/12/04 Deciphered Date 2018/08/20 S740-ICL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Name Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday, December 06, 2019 Sheet 8 of 60
5 4 3 2 1
 5 4 3 2 1

20 PCIE_CRX_GTX_N[5..8]

20 PCIE_CRX_GTX_P[5..8]

20 PCIE_CTX_C_GRX_N[5..8]

20 PCIE_CTX_C_GRX_P[5..8]

UC1H
PCIE_CRX_GTX_N7 CV7 DJ8 USB30_RX_N1
PCIE_CRX_GTX_P7 PCIE7_RXN PCIE1_RXN/USB31_1_RXN USB30_RX_P1 USB30_RX_N1 41
CV6 DJ6
PCIE_CTX_C_GRX_N7 PCIE_CTX_GRX_N7 PCIE7_RXP PCIE1_RXP/USB31_1_RXP USB30_TX_N1 USB30_RX_P1 41
PCIE_CTX_C_GRX_P7
OPT@ 0.22U_0201_6.3V6-K 1 2 CC901
PCIE_CTX_GRX_P7
DD3
PCIE7_TXN PCIE1_TXN/USB31_1_TXN
DJ2
USB30_TX_P1 USB30_TX_N1 41 USB3.0 Port1
OPT@ 0.22U_0201_6.3V6-K 1 2 CC902 DD5 DJ1
D
dGPU PCIE_CRX_GTX_N8 CT6
PCIE7_TXP PCIE1_TXP/USB31_1_TXP
DG9 USB30_RX_N2
USB30_TX_P1 41 D

PCIE_CRX_GTX_P8 CT7 PCIE8_RXN PCIE2_RXN/USB31_2_RXN DG7 USB30_RX_P2 USB30_RX_N2 41

PCIE_CTX_C_GRX_N8 PCIE_CTX_GRX_N8 PCIE8_RXP PCIE2_RXP/USB31_2_RXP USB30_TX_N2 USB30_RX_P2 41
OPT@ 0.22U_0201_6.3V6-K 1 2 CC903 DA3 DJ3 USB3.0 Port2
PCIE_CTX_C_GRX_P8 PCIE_CTX_GRX_P8 PCIE8_TXN PCIE2_TXN/USB31_2_TXN USB30_TX_P2 USB30_TX_N2 41
OPT@ 0.22U_0201_6.3V6-K 1 2 CC904 DA5 DJ5
PCIE8_TXP PCIE2_TXP/USB31_2_TXP USB30_TX_P2 41
PCIE_PRX_DTX_N9 CP7 DE7
40 PCIE_PRX_DTX_N9 PCIE_PRX_DTX_P9 PCIE9_RXN PCIE3_RXN/USB31_3_RXN
CP6 DE9
40 PCIE_PRX_DTX_P9 PCIE9_RXP PCIE3_RXP/USB31_3_RXP
CC905 1 2 0.1U_6.3V_K_X5R_0201 PCIE_PTX_DRX_N9 DA2 DF3
WLAN 40
40
PCIE_PTX_C_DRX_N9
PCIE_PTX_C_DRX_P9
CC906 1 2 0.1U_6.3V_K_X5R_0201 PCIE_PTX_DRX_P9 DA1 PCIE9_TXN PCIE3_TXN/USB31_3_TXN DF5
PCIE9_TXP PCIE3_TXP/USB31_3_TXP
CM7 DC7
CM6 PCIE10_RXN PCIE4_RXN/USB31_4_RXN DC9
CY3 PCIE10_RXP PCIE4_RXP/USB31_4_RXP DF2
CY4 PCIE10_TXN PCIE4_TXN/USB31_4_TXN DF1
PCIE10_TXP PCIE4_TXP/USB31_4_TXP
SATA_PRX_DTX_N0 CK7 DA6 PCIE_CRX_GTX_N5
37 SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 PCIE11_RXN/SATA0_RXN PCIE5_RXN/USB31_5_RXN PCIE_CRX_GTX_P5
CK6 DA7
37 SATA_PRX_DTX_P0 SATA_PTX_DRX_N0 PCIE11_RXP/SATA0_RXP PCIE5_RXP/USB31_5_RXP PCIE_CTX_GRX_N5 PCIE_CTX_C_GRX_N5
CW2 DE4 CC907 2 1 0.22U_0201_6.3V6-K OPT@
HDD 37 SATA_PTX_DRX_N0 SATA_PTX_DRX_P0 CW1 PCIE11_TXN/SATA0_TXN PCIE5_TXN/USB31_5_TXN DE3 PCIE_CTX_GRX_P5 CC908 2 1 0.22U_0201_6.3V6-K OPT@ PCIE_CTX_C_GRX_P5
37 SATA_PTX_DRX_P0 PCIE11_TXP/SATA0_TXP PCIE5_TXP/USB31_5_TXP
PCIE_CRX_GTX_N6
dGPU

El
CJ6 CY7
CJ7 PCIE12_RXN/SATA1A_RXN PCIE6_RXN/USB31_6_RXN CY6 PCIE_CRX_GTX_P6
CW5 PCIE12_RXP/SATA1A_RXP PCIE6_RXP/USB31_6_RXP DD1 PCIE_CTX_GRX_N6 CC909 2 1 0.22U_0201_6.3V6-K OPT@ PCIE_CTX_C_GRX_N6
CW3 PCIE12_TXN/SATA1A_TXN PCIE6_TXN/USB31_6_TXN DD2 PCIE_CTX_GRX_P6 CC910 2 1 0.22U_0201_6.3V6-K OPT@ PCIE_CTX_C_GRX_P6
PCIE12_TXP/SATA1A_TXP PCIE6_TXP/USB31_6_TXP
PCIE_PRX_DTX_N13 CG7 DN8 USB20_N1
USB20_N1 41
37
37
PCIE_PRX_DTX_N13
PCIE_PRX_DTX_P13
PCIE_PRX_DTX_P13
PCIE_PTX_DRX_N13
CG6
CT3
PCIE13_RXN
PCIE13_RXP
USB2N_1
USB2P_1
DP8 USB20_P1
USB20_P1 41 USB3.0 Port2
37 PCIE_PTX_DRX_N13 PCIE_PTX_DRX_P13 CT5 PCIE13_TXN DK11 USB20_N2
USB20_N2 41
PCIE13_TXP USB2N_2
USB3.0 Port1

et
37 PCIE_PTX_DRX_P13 DJ11 USB20_P2
PCIE_PRX_DTX_N14 CE6 USB2P_2 USB20_P2 41
37 PCIE_PRX_DTX_N14 PCIE_PRX_DTX_P14 CE7 PCIE14_RXN DP13
37 PCIE_PRX_DTX_P14 PCIE_PTX_DRX_N14 CT2 PCIE14_RXP USB2N_3 DN13
PCIE14_TXN USB2P_3
TBT
37 PCIE_PTX_DRX_N14 PCIE_PTX_DRX_P14 CT1
37 PCIE_PTX_DRX_P14 PCIE14_TXP DK10
SSD 37 PCIE_PRX_DTX_N15
PCIE_PRX_DTX_N15 CC5
PCIE15_RXN/SATA1B_RXN
USB2N_4
USB2P_4
DJ10 Type-C B
C PCIE_PRX_DTX_P15 CC6 C
37 PCIE_PRX_DTX_P15 PCIE_PTX_DRX_N15 PCIE15_RXP/SATA1B_RXP USB20_N5

ro
CR3 DL5
37
37
PCIE_PTX_DRX_N15
PCIE_PTX_DRX_P15
PCIE_PTX_DRX_P15 CR4 PCIE15_TXN/SATA1B_TXN
PCIE15_TXP/SATA1B_TXP
USB2N_5
USB2P_5
DL3 USB20_P5 USB20_N5
USB20_P5
33
33
Camera
PCIE_PRX_DTX_N16 CA6 DP11 USB20_N6
37 PCIE_PRX_DTX_N16
37 PCIE_PRX_DTX_P16
PCIE_PRX_DTX_P16
PCIE_PTX_DRX_N16
CA5 PCIE16_RXN/SATA2_RXN
PCIE16_RXP/SATA2_RXP
USB2N_6
USB2P_6
DN11 USB20_P6 USB20_N6
USB20_P6
33
33 Touch Screen
CP1
37 PCIE_PTX_DRX_N16 PCIE_PTX_DRX_P16 CP2 PCIE16_TXN/SATA2_TXN DK13 USB20_N7
37 PCIE_PTX_DRX_P16 PCIE16_TXP/SATA2_TXP USB2N_7 DJ13 USB20_P7 USB20_N7 45
USB2P_7 USB20_P7 45 Finger Print
DW12
40 PCH_BT_OFF# GPP_E0/SATAXPCIE0/SATAGP0 USB20_N8

-X
CR42 DN6
37 SSD_PCIE_DET#
SSD_PCIE_DET# CR43 GPP_A12/SATAXPCIE1/SATAGP1
GPP_A13/SATAXPCIE2/SATAGP2
USB2N_8
USB2P_8
DP6 USB20_P8 USB20_N8
USB20_P8
30
30 Card reader
USB_OC0# DW14 DL2 USB20_N9
41 USB_OC0# USB_OC3# GPP_E9/USB_OC0_N USB2N_9 USB20_P9 USB20_N9 42
CT43
GPP_A16/USB_OC3_N USB2P_9
DL1
USB20_P9 42 USB2.0

https://vinafix.com
DU12 DP10 USB20_N10
GPP_E4/DEVSLP0 USB2N_10 USB20_P10 USB20_N10 40
DU11
PCH_SATA_2_DEVSLP CV48 GPP_E5/DEVSLP1 USB2P_10
DN10
USB20_P10 40 BT
GPP_A11/SATA_DEVSLP2 DL6 USB2_ID 1 2 0_0201_5%
Native OD output RC901 @

Te
DT38 USB_ID
DW38 GPP_H12/M2_SKT2_CFG0 DL11 USB2_VBUSSENSE RC902 1 @ 2 0_0201_5%
DV38 GPP_H13/M2_SKT2_CFG1 USB_VBUSSENSE
+3VALW_PCH DU38 GPP_H14/M2_SKT2_CFG2 DN5 USB2_COMP RC903 1 2 1/16W_113_1%_0402
GPP_H15/M2_SKT2_CFG3 USB2_COMP
RC904 1 2 10K_0201_5% USB_OC0# RC905 1 2 1/20W_100_1%_0201 PCIE_RCOMPN DN1 CD3
PCIE_RCOMPP DN3 PCIE_RCOMPN RSVD_81
PCIE_RCOMPP
8 of 19

+1.8VALW_PCH ICELAKE-U_BGA1526
@

ch
RC906 1 2 10K_0201_5% USB_OC3#

RC907 1 2 10K_0201_5% SSD_PCIE_DET#

RC908 2 1 10K_0201_5% PCH_SATA_2_DEVSLP

B +1.8VALW_PCH PCH_SATA_DEVSLP B
PCH_SATA_DEVSLP 37
2

ni
RC909
100K_0402_5%

3
D2
1

5
G2 QC901B

S2
PJT7838_SOT363-6

ca
6

4
D1

PCH_SATA_2_DEVSLP 2
G1 QC901A
S1
1

PJT7838_SOT363-6

l
@
PCH_SATA_2_DEVSLP RC910 1 2 0_0402_5% PCH_SATA_DEVSLP

1. DEVSLP is an open-drain pin on the PCH side and is not required external pull-up orpull-down. The PCH will
tri-state this pin to signal to the SATA device that it may enter a lower power state (pin will go high due to pull-up
that’s internal to the SATAdevice, per DEVSLP specification). PCH will drive pin low to signal an exit fromDEVSLP state.
2. DEVSLP is supported in direct connect, mSATA/mPCIe, uSSD, M.2.
3. 1 DEVSLP pin is required to support EACH DEVSLP enabled RAID storage device.
(Example: 2 DEVSLP pins are required to support 2 DEVSLP RAID storage devices).
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/12/04 Deciphered Date 2018/08/20 S740-ICL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Name Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday, December 06, 2019 Sheet 9 of 60
5 4 3 2 1
 5 4 3 2 1

UC1I

BOARD_ID0
Vinafix.com +1.8VALW_PCH
D12 DP27
C12 CSI_E_CLK_N GPP_F8/EMMC_DATA0 DU30 BOARD_ID1
B12 CSI_E_CLK_P GPP_F9/EMMC_DATA1 DT30 BOARD_ID2 CNVI_RGI_RSP RC1000 1 @ 2 20K_0402_5%
A12 CSI_E_DN_0 GPP_F10/EMMC_DATA2 DT29 BOARD_ID3
G13 CSI_E_DP_0 GPP_F11/EMMC_DATA3 DV30 BOARD_ID4 CNVI_BRI_RSP RC1001 1 @ 2 20K_0402_5%
F13 CSI_E_DN_1 GPP_F12/EMMC_DATA4 DU29 BOARD_ID5
CSI_E_DP_1 GPP_F13/EMMC_DATA5

eMMC
DW30 BOARD_ID6
K10 GPP_F14/EMMC_DATA6 DW29 BOARD_ID7
L10 CSI_F_CLK_N GPP_F15/EMMC_DATA7 DV28 BOARD_ID8
L8 CSI_F_CLK_P GPP_F7/EMMC_CMD DW28 BOARD_ID9
M8 CSI_F_DN_0 GPP_F16/EMMC_RCLK DN27 BOARD_ID10 +1.8VALW_PCH
M11 CSI_F_DP_0 GPP_F17/EMMC_CLK DT28 BOARD_ID11
D
L11 CSI_F_DN_1 GPP_F18/EMMC_RESET_N DU28 EMMC_COMP RC1003 1 2 200_0402_1% RC1002 1 @ 2 4.7K_0402_5% D
CSI_F_DP_1 EMMC_RCOMP
D9 CNVI_BRI_DT_R RC1004 1 @ 2 1/20W_20K_5%_0201
C9 CSI_D_CLK_N DV45 CNV_WT_D0N
CSI_D_CLK_P CNV_WT_D0N CNV_WT_D0P CNV_WT_D0N 40
A7 DU45
CSI_D_DN_0 CNV_WT_D0P CNV_WT_D1N CNV_WT_D0P 40
B7 DU44
B9 CSI_D_DP_0 CNV_WT_D1N DT44 CNV_WT_D1P CNV_WT_D1N 40
CSI_D_DN_1 CNV_WT_D1P CNV_WT_CLKN CNV_WT_D1P 40 GPP_F0 /CNV_BRI_DT /UART0_RTS#
A9 DL42 XTAL Frequency Selection, Rising edge of RSMRST#
CSI_D_DP_1 CNV_WT_CLKN CNV_WT_CLKP CNV_WT_CLKN 40
D7 DK42 This strap has a 20 kohm ± 30% internal pull-down.
C7 CSI_D_DN_2/CSI_C_DN_0 CNV_WT_CLKP CNV_WT_CLKP 40
This strap should not be pulled high since 24 MHz crystal is not

CSI2
D8 CSI_D_DP_2/CSI_C_DP_0 DP44 CNV_WR_D0N
CSI_D_DN_3/CSI_C_CLK_N CNV_WR_D0N CNV_WR_D0P CNV_WR_D0N 40 supported on the PCH.
C8 DN44
CSI_D_DP_3/CSI_C_CLK_P CNV_WR_D0P DG42 CNV_WR_D1N CNV_WR_D0P 40 0 = 38.4 MHz (default)
G11 CNV_WR_D1N DG44 CNV_WR_D1P CNV_WR_D1N 40 1 = 24 MHz
J11 CSI_H_CLK_N CNV_WR_D1P DK44 CNV_WR_CLKN CNV_WR_D1P 40 Notes:
F6 CSI_H_CLK_P CNV_WR_CLKN DJ44 CNV_WR_CLKP CNV_WR_CLKN 40 1. The internal pull-down is disabled after RSMRST# de-asserts.
CNV_WR_CLKP 40 2. This signal is in the primary well.

CNVi
G6 CSI_H_DN_0 CNV_WR_CLKP
G10 CSI_H_DP_0 DT45 CNV_WT_RCOMP RC1005 1 2 150_0402_1%
F10 CSI_H_DN_1 CNV_WT_RCOMP
G8 CSI_H_DP_1 DL29 CNVI_BRI_RSP
CSI_H_DN_2/CSI_G_DN_0 GPP_F1/CNV_BRI_RSP/UART0_RXD CNVI_RGI_DT_R CNVI_BRI_RSP 40
J8 DP31 RC1006 1 2 1/20W_22_5%_0201
CSI_H_DP_2/CSI_G_DP_0 GPP_F2/CNV_RGI_DT/UART0_TXD CNVI_BRI_DT_R CNVI_RGI_DT 40 +1.8VALW_PCH

El
K6 DL31 RC1007 1 2 1/20W_22_5%_0201
L6 CSI_H_DN_3/CSI_G_CLK_N GPP_F0/CNV_BRI_DT/UART0_RTS_N DN29 CNVI_RGI_RSP CNVI_BRI_DT 40
CSI_H_DP_3/CSI_G_CLK_P GPP_F3/CNV_RGI_RSP/UART0_CTS_N CNVI_RGI_RSP 40 CNVI_RGI_DT_R RC1009 1 2 100K_0402_5%
RC1008 1 2 100_0402_1% CSI2_COMP B4 DJ29 BOARD_ID12
CSI_RCOMP GPP_F4/CNV_RF_RESET_N DP29 RC1011 1 @ 2 4.7K_0402_5%
DT34 GPP_F6/CNV_PA_BLANKING DL27 WP_PRESENT RC1010 1 2 1/20W_75K_5%_0201
DP38 GPP_D4/IMGCLKOUT0 GPP_F19/A4WP_PRESENT DK29
DK36 GPP_H20/IMGCLKOUT1 GPP_F5/MODEM_CLKREQ
DL36 GPP_H21/IMGCLKOUT2
GPP_H22/IMGCLKOUT3 GPP_F2 /CNV_RGI_DT /UART0_TXD:

et
DN38 M.2 CNVI MODES, Rising edge of RSMRST#
GPP_H23/IMGCLKOUT4
A weak external pull-up is required.
0 = Integrated CNVi enabled.
1 = Integrated CNVi disabled.
Note:
ICELAKE-U_BGA1526 9of 19 When a RF companion chip is connected to the PCH CNVi interface,
C +3VS @ the device internal pulldown resistor will pull the strap low to C
enable CNVi interface.

ro
10K_0201_5% 2 @ 1 RC1012 WLAN_CLKREQ#

10K_0201_5% 2 1 RC1013 SSD_CLKREQ#

10K_0201_5% 2 1 RC1014 GPU_CLKREQ#

-X
UC1J

CLK_PCIE_WLAN# CJ3 CF5

40
40
CLK_PCIE_WLAN#
CLK_PCIE_WLAN
CLK_PCIE_WLAN
WLAN_CLKREQ#
CJ5
DK33
CLKOUT_PCIE_N0
CLKOUT_PCIE_P0
CLKOUT_PCIE_N5
CLKOUT_PCIE_P5
CF3
DP40
BOARD ID

https://vinafix.com
40 WLAN_CLKREQ# GPP_D5/SRCCLKREQ0_N GPP_H11/SRCCLKREQ5_N +1.8VALW_PCH
CLK_PCIE_SSD# CL2
37 CLK_PCIE_SSD# CLK_PCIE_SSD CLKOUT_PCIE_N1 RTC_X1
CL1 DL48
37 CLK_PCIE_SSD SSD_CLKREQ# CLKOUT_PCIE_P1 RTCX1 RTC_X2
DN34 DL49
37 SSD_CLKREQ#

Te
GPP_D6/SRCCLKREQ1_N RTCX2
CLK_PCIE_GPU# CL3 DT47 RTC_RST#
20 CLK_PCIE_GPU# CLK_PCIE_GPU CLKOUT_PCIE_N2 RTCRST_N SRTC_RST#

100K_0201_5%

100K_0201_5%

100K_0201_5%

100K_0201_5%

100K_0201_5%

100K_0201_5%

100K_0201_5%

100K_0201_5%

100K_0201_5%

100K_0201_5%

100K_0201_5%

100K_0201_5%

100K_0201_5%
CL5 DK46
20 CLK_PCIE_GPU CLKOUT_PCIE_P2 SRTCRST_N

1
GPU_CLKREQ#

RC833

RC832

RC831

RC830

RC829

RC828

RC827

RC826

RC825

RC824

RC823

RC822

RC821
DP34
20 GPU_CLKREQ# GPP_D7/SRCCLKREQ2_N

1
DF49 SUSCLK
GPD8/SUSCLK SUSCLK 40
CK3
CK4 CLKOUT_PCIE_N3
CLKOUT_PCIE_P3 XTAL_PCH_38P4M_IN

17@

15@

NTS@

@
DP36 DW8 @ @

2
GPP_D8/SRCCLKREQ3_N XTAL_IN DU8 XTAL_PCH_38P4M_OUT

2
CJ2 XTAL_OUT
CJ1 CLKOUT_PCIE_N4 BOARD_ID0
DN40 CLKOUT_PCIE_P4 DU6 XCLK_BIASREF RC1016 1 2 1/20W_60.4_1%_0201 BOARD_ID1

ch
GPP_H10/SRCCLKREQ4_N XCLK_BIASREF BOARD_ID2
BOARD_ID3
10of 19 BOARD_ID4
BOARD_ID5
ICELAKE-U_BGA1526 BOARD_ID6
1K_0402_5% 2 @ 1 RC1015 SUSCLK
@ BOARD_ID7
B BOARD_ID8 B
BOARD_ID9
BOARD_ID10
BOARD_ID11

ni
BOARD_ID12

1
100K_0201_5%
RC846

100K_0201_5%
RC845

100K_0201_5%
RC844

100K_0201_5%
RC843

100K_0201_5%
RC842

100K_0201_5%
RC841

100K_0201_5%
RC840

100K_0201_5%
RC839

100K_0201_5%
RC838

100K_0201_5%
RC837

100K_0201_5%
RC836

100K_0201_5%
RC835

100K_0201_5%
RC834
1

1
XTAL_PCH_38P4M_IN XTAL_PCH_38P4M_IN_R

1415@

1417@

TS@

@
RC1017 1 2 0_0402_5%

2
@
@ @ @ @ @ @ @ @

ca
2

2
LC1000
4 3
4 3

1 2 14" 00(R839,R838)
1 2 BOARD_ID5..4 15" 01(R839,R825)
EXC24CH500U_4P 17" 10(R826,R838)
EMC_NS@ Sumsang 0000

l
BOARD_ID6/7/8/9 Hynix 0001
XTAL_PCH_38P4M_OUT RC1021 1 2 0_0402_5% XTAL_PCH_38P4M_OUT_R M icron 0010
RTC_X1

RTC_X2
XTAL_PCH_38P4M_IN_R 1
RC10231 2 200K_0402_1% XTAL_PCH_38P4M_OUT_R VCCRTC CC1000
RC1022 1 2 10M_0402_5% 1U_6.3V_K_X5R_0201
YC1001 YC1000 RC1018 1 2 20K_0402_1% 2 RTC_RST# RC1019 1 2 0_0402_5% @
1 2 EC_RTC_RST# 44
4 3 RC1020 1 2 20K_0402_1% SRTC_RST#
NC1 OSC2 32.768KHZ 9PF 202934-PG14 1
1 2 1 1 CC1001
OSC1 NC2 1U_6.3V_K_X5R_0201
A
1 1 CC1002 CC1003 A
CC1004 CC1005 10P_0402_50V8J 10P_0402_50V8J 2
38.4MHZ_10PF_7R38400001 2 2
10P_0402_50V8J 10P_0402_50V8J
2 2

Security Classification LC Future Center Secret Data Title

Issued Date 2018/12/04 Deciphered Date 2018/08/20 S740-ICL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Name Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday, December 06, 2019 Sheet 10 of 60
5 4 3 2 1
 5 4 3 2 1

UC1K

PM_SLP_SUS# DM49 CY42 PBTN_OUT#_R

44 PM_SLP_SUS# PM_SLP_S5# DF45 SLP_SUS_N GPD3/PWRBTN_N DE46 AC_PRESENT_R PBTN_OUT#_R 44
PM_SLP_S4# GPD10/SLP_S5_N GPD1/ACPRESENT AC_PRESENT_R 44
DC48 DH48 BATLOW# 1
44 PM_SLP_S4# PM_SLP_S3# DF47 GPD5/SLP_S4_N GPD0/BATLOW_N TP1102 @
44 PM_SLP_S3# PM_SLP_A# GPD4/SLP_S3_N
DH47 CL39
PM_SLP_S0# CL45 GPD6/SLP_A_N GPP_B11/PMCALERT DU40 CPU_C10_GATE#
44 PM_SLP_S0# GPP_B12/SLP_S0_N GPP_H18/CPU_C10_GATE_N DG40 SX_EXIT_HOLDOFF# 1 TP1101 @
PM_SLP_WLAN# DE49 GPP_H3/SX_EXIT_HOLDOFF_N/CNV_BT_I2S_SDO
40 PM_SLP_WLAN# PM_SLP_LAN# DN48 GPD9/SPL_WLAN_N DL45
SLP_LAN_N WAKE_N PCIE_WAKE# 40
PCH_RSMRST#_R DG49 DE47 PCH_LAN_WAKE#
SYS_RESET# DK19 RSMRST_N GPD_2/LAN_WAKE_N DF48 PCH_CNVI_EN# RC1100 1 2 0_0402_5% @
D PLT_RST#_R SYS_RESET_N GPD11/LANPHYPC/DSWLDO_MON CNVI_EN# 40 D
RC1101 1 2 0_0201_5% @ CM49
26,37,40,44 PLT_RST# GPP_B13/PLTRST_N CE4 VCCST_OVERRIDE_R 2 0_0201_5% @ VCCST_OVERRIDE
RC1102 1 VCCST_OVERRIDE 46
VCCST_OVERRIDE CF2 VCCST_PWRGD_R RC1103 1 2 60.4_0402_1%
PCH_DPWROK_R VCCST_PWRGD VCCSTPWRGOOD_TCSS EC_VCCST_PWRGD 44
DR48 CE3 RC1104 1 2 0_0201_5% @
RC1105 1 2 0_0201_5% @ PCH_PWROK_R DN47 DSW_PWROK VCCSTPWRGOOD_TCSS CF1 CPU_PROCPWRGD 1
44 PCH_PWROK SYS_PWROK_R PCH_PWROK PROCPWRGD
RC1106 1 2 0_0201_5% @ DP19 TP1100 @
44 SYS_PWROK SYS_PWROK DC47
INPUT3VSEL DN49 GPD7
INTRUDER# DR47 INPUT3VSEL
INTRUDER_N
11 of 19

ICELAKE-U_BGA1526
@

DSW_PWROK and RSMRST# are always separate power good signals +3VALW

El

2
PCH_DPWROK RC1107 1 2 0_0402_5% @ PCH_DPWROK_R RC1135 EC_VCCST_PWRGD
44 PCH_DPWROK
100K_0201_5%
RC1108 1 2 10K_0402_5% @

3
D
5 QC1101B
EC_RSMRST# RC1109 1 2 0_0402_5% @ PCH_RSMRST#_R G
44 EC_RSMRST# 2N7002KDWH_SOT363-6

6
et
D
RC1110 1 2 10K_0402_5% PM_SLP_S3# 2 S @

4
G

S QC1101A

1
2N7002KDWH_SOT363-6
@
C C
+3VALW_PCH

ro
RC1111 2 @ 1 4.7K_0402_5% INPUT3VSEL +VCCST_CPU

RC1112 2 1 100K_0402_5% EC_VCCST_PWRGD RC1113 1 2 1K_0402_5%

Glitch Free Requirements:

CAD NOTE: Pull-up resistor is required if a device is monitoring SLP_S0#
INPUT3VSEL: 3V SELECT STRAP before RSMRST# de-assertion +3VS

-X
LOW-> 3.3V +/-5% 100K for 3.3V Signaling Mode SYS_RESET#
HIGH->3.0V +/-5% 75K for 1.8V Signaling Mode RC1114 1 2 10K_0201_5%

+3VALW_PCH

https://vinafix.com
PM_SLP_S0# RC1115 1 2 100K_0201_5%
+3VALW_PCH

Te
PCIE_WAKE# RC1116 1 2 10K_0201_5%
VCCRTC
PCH_LAN_WAKE# RC1117 1 2 10K_0402_5%
Glitch Free Requirements:
RC1118 1 @ 2 1M_0402_5% INTRUDER# Cap or pull-down resistor is required PBTN_OUT#_R RC1119 1 @ 2 100K_0201_5%
Option 1:Cap Implementation
330 nF for 3.3v Ramp Rate from 5-50ms BATLOW# RC1120 1 2 100K_0201_5%
RC1121 1 2 10K_0402_5%
33 nF for 3.3V Ramp Rate Less than 5ms AC_PRESENT_R RC1122 1 2 100K_0402_5%
@
CC11002 1 0.1U_6.3V_K_X5R_0201 Option 2:Pull-down Resistor Implementation CPU_C10_GATE# RC1123 1 @ 2 1/20W_20K_5%_0201

ch
100K for 3.3V Signaling Mode
75K for 1.8V Signaling Mode

SPI Voltage Configuration:

PM_SLP_SUS# RC1126 1 2 100K_0201_5%
The VCCSPI voltage (3.3V or 1.8V) is selected via a hard strap
B on the INTRUDER#. PCH_PWROK B
This strap sets the SPI interface signaling voltage at the rising edge @ CC1101 1 2 0.033UC_10VC_KC_X5RC_0201 RC1124 1 2 10K_0201_5%
of RTCRST#. Designers should strap this pin to match the expected SYS_PWROK RC1125 1 2 10K_0201_5%
interface operational voltage for their target SPI device as follows. PM_SLP_S3# RC1128 1 2 100K_0201_5%
0 = SPI interface operation voltage is 3.3V

ni
VCCST_OVERRIDE RC1127 1 2 100K_0402_5%
(ground through a 10kohm resistor) @ CC1102 1 2 0.033UC_10VC_KC_X5RC_0201
1 = SPI interface operation voltage is 1.8V
(pulled up with 1 Mohm to VCCRTC)
PM_SLP_S4# RC1129 1 2 100K_0201_5%

@ CC1103 1 2 0.033UC_10VC_KC_X5RC_0201

ca
PCH_RSMRST#_R CC1107 2 1 1000P_0201_50V7-K EMC_NS@ PM_SLP_A# @ RC1130 1 2 100K_0201_5%
PCH_DPWROK_R CC1109 2 1 1000P_0201_50V7-K EMC_NS@ @ CC1104 1 2 0.033UC_10VC_KC_X5RC_0201
SYS_RESET# CC1444 2 1 1000P_0201_50V7-K EMC_NS@
PM_SLP_WLAN# @ RC1131 1 2 100K_0201_5%
FOR EMC
@ CC1105 1 2 0.033UC_10VC_KC_X5RC_0201

l
PM_SLP_LAN# @ RC1132 1 2 100K_0201_5%

@ CC1106 1 2 0.033UC_10VC_KC_X5RC_0201

PM_SLP_S5# @ RC1133 1 2 100K_0201_5%

@ CC1108 1 2 0.033UC_10VC_KC_X5RC_0201

PLT_RST# RC1134 1 2 100K_0201_5%

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/12/04 Deciphered Date 2018/08/20 S740-ICL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Name Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday, December 06, 2019 Sheet 11 of 60
5 4 3 2 1
 5 4 3 2 1

+VCCIN UC1L +VCCIN

A19 CJ35
AC12 VCCIN_1 VCCIN_52 CK10 +1.2V UC1M +1.2V
V13 VCCIN_2 VCCIN_53 J32
W12 VCCIN_3 VCCIN_54 CL34 AA37 BP39
Y13 VCCIN_4 VCCIN_55 CL35 +VCCST_CPU AG36 VDDQ_1 VDDQ_31 BR37
K29 VCCIN_5 VCCIN_56 CN34 AJ36 VDDQ_2 VDDQ_32 BT38
K31 VCCIN_6 VCCIN_57 CN35 RC1201 1 2 100_0402_1% VR_SVID_DAT AL36 VDDQ_3 VDDQ_33 AC35
B19 VCCIN_7 VCCIN_58 CP33 AL49 VDDQ_4 VDDQ_34 BU37
B23 VCCIN_8 VCCIN_59 CR34 RC1202 1 2 56_0402_5% VR_SVID_ALRT# AN36 VDDQ_5 VDDQ_35 BU49
B27 VCCIN_9 VCCIN_60 A29 AP37 VDDQ_6 VDDQ_36 CA39
B29 VCCIN_10 VCCIN_61 CR35 RC1203 1 @ 2 1/16W_45.3_1%_0402 VR_SVID_CLK AR36 VDDQ_7 VDDQ_37 CB49
BN10 VCCIN_11 VCCIN_62 CT33 AR37 VDDQ_8 VDDQ_38 L38
BP11 VCCIN_12 VCCIN_63 CT34 AT36 VDDQ_9 VDDQ_39 L49
VCCIN_13 VCCIN_64 CAD NOTE: VDDQ_10 VDDQ_40
BP9 CT35 Alert signal must be routed between Clk and Data signals AT49 N36
BR10 VCCIN_14 VCCIN_65 CU33 AA49 VDDQ_11 VDDQ_41 T49
VCCIN_15 VCCIN_66 to minimize Cross-Talk. VDDQ_12 VDDQ_42
BT11 D19 AV36 AC37
D
A21 VCCIN_16 VCCIN_67 D21 AW37 VDDQ_13 VDDQ_43 AD35 D
BT9 VCCIN_17 VCCIN_68 D23 AY36 VDDQ_14 VDDQ_44 AD36
BU10 VCCIN_18 VCCIN_69 D24 BA37 VDDQ_15 VDDQ_45 AE36
BV36 VCCIN_19 VCCIN_70 D27 BA49 VDDQ_16 VDDQ_46 AF49
BV9 VCCIN_20 VCCIN_71 AA12 BB36 VDDQ_17 VDDQ_47
BW10 VCCIN_21 VCCIN_72 D29 BD36 VDDQ_18 C33
BW36 VCCIN_22 VCCIN_73 F19 BE37 VDDQ_19 RSVD_77
BW9 VCCIN_23 VCCIN_74 F21 BF36 VDDQ_20 A33
BY10 VCCIN_24 VCCIN_75 F23 BF37 VDDQ_21 RSVD_2 B33
C19 VCCIN_25 VCCIN_76 F24 AB36 VDDQ_22 RSVD_3
C23 VCCIN_26 VCCIN_77 F27 BF49 VDDQ_23 BG9
A23 VCCIN_27 VCCIN_78 F29 BG36 VDDQ_24 VCC1P8A_1 BJ9
C27 VCCIN_28 VCCIN_79 G1 BJ36 VDDQ_25 VCC1P8A_2 BM9
C29 VCCIN_29 VCCIN_80 G19 BL37 VDDQ_26 VCC1P8A_3 BW1
VCCIN_30 VCCIN_81 VDDQ_27 VCC1P8A_4 0.7A
CA36 G23 BM49 BW2 +VCC1P8A
CA9 VCCIN_31 VCCIN_82 AB1 BN37 VDDQ_28 VCC1P8A_5
CB10 VCCIN_32 VCCIN_83 G27 BP38 VDDQ_29 R35
CC11 VCCIN_33 VCCIN_84 G29 VDDQ_30 VCCSTG_OUT_3 V34
CC36 VCCIN_34 VCCIN_85 H19 0.605A CB1 VCCSTG_OUT_4 T34
VCCIN_35 VCCIN_86 +VCCST_CPU VCCST VCCSTG_OUT_5
CC9 H23 U35
CD10 VCCIN_36 VCCIN_87 H27 0.119A BY1 VCCSTG_OUT_6 AB34
VCCIN_37 VCCIN_88 +VCCSTG_CPU VCCSTG VCCSTG_OUT_7 +VCCSTG_OUT_R

El
CE11 H29 W35
A24 VCCIN_38 VCCIN_89 J18 RSVD_74 AA35
CE34 VCCIN_39 VCCIN_90 J20 RSVD_75 Y34
CE35 VCCIN_40 VCCIN_91 J22 INTERNAL RAIL.F33 RSVD_76
VCCIN_41 VCCIN_92 +VCCSTG_OUT VCCSTG_OUT_1
CF10 J23 G33
CF33 VCCIN_42 VCCIN_93 AB13 VCCSTG_OUT_2 CD2
VCCIN_43 VCCIN_94 VCCPLL_1 +VCC1.05_OUT_SFR 0.09A
CG11 J26 INTERNAL RAIL. E5
VCCIN_44 VCCIN_95 +VCCSTG_OUT_LGC VCCSTG_OUT_LGC
CG34 J28 CG38
CG35 VCCIN_45 VCCIN_96 K17 VCCPLL_OC_1 CG41
VCCIN_46 VCCIN_97 VCCPLL_OC_2

et
CH10 K19 +VCCIN CG42
J30 VCCIN_47 VCCIN_98 K21 VCCPLL_OC_3 CG49
VCCIN_48 VCCIN_99 VCCPLL_OC_4 +VCCSFR_OC 0.16A
CJ11 K23
VCCIN_49 VCCIN_100

1
A27 K24 AD7 INTERNAL RAIL. +VCCIO_OUT
CJ34 VCCIN_50 VCCIN_101 K27 RC1204 VCCIO_OUT
VCCIN_51 VCCIN_102 M1 1/20W_100_1%_0201
VCCIN_103 U1 ICELAKE-U_BGA1526
C VR_SVID_ALRT# H1 VCCIN_104 @ 13 of 19 C
56 VR_SVID_ALRT#

2
VR_SVID_CLK VIDALERT

ro
H2 F17
56 VR_SVID_CLK VR_SVID_DAT VIDSCK VCCIN_SENSE VCCIN_SENSE 56
H3 G17
56 VR_SVID_DAT VIDSOUT VSSIN_SENSE VSSIN_SENSE 56

ICELAKE-U_BGA1526

1
@ 12 of 19 RC1205
2 1/20W_100_1%_0201

-X
+VCCST_CPU

https://vinafix.com

1U_6.3V_M_X5R_0201
1U_6.3V_M_X5R_0201

CC1213
1 VCCST:

Te

CC1212
1 1x1uF 0402 Close SOC
+1.8VALW_PCH +VCC1P8A +VCCSTG_OUT_LGC +VCCSTG_TERM
1x0402 (holder）
2
0.7A 2
RC1208 1 2 0_5%_0603 @ RC1206 1 2 0_5%_0603 @ @
22UC_6.3VC_MC_X5RC_0603
10U 6.3V M X5R 0402

0.1U_6.3V_K_X5R_0201

1 1 1
CC1204

CC1205

CC1206

VCC1P8A
1x10uF 0402 close toBGA
1x0603(hold)
2 2 2 W>1.8mm

ch
@
@

+VCCSTG_CPU
B B

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201
VCCSTG:
1 1 1x1uF 0402 Close SOC

CC1214

CC1215
1x0402 (holder）

ni
+1.2V +VCCSFR_OC If VCCST is enabled by SLP_S4#, 2 2
no power gate is required for @
VCCPLL_OC and it can
0.16A be merged with VDDQ directly.
RC1207 1 2 0_0402_5% @
1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

VCCPLL_OC:

ca
1 1 1x1uF 0402 Close SOC
CC1216

CC1217

1x0402 (holder）
2 2
@

l
+VCCSTG_OUT_R
+VCCSTG_OUT

RC1210 1 2 0_5%_0603 @
1U_6.3V_M_X5R_0201

1
CC1211

A 2 A
@

Security Classification LC Future Center Secret Data Title

Issued Date 2018/12/04 Deciphered Date 2018/08/20 S740-ICL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Name Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday, December 06, 2019 Sheet 12 of 60
5 4 3 2 1
 5 4 3 2 1

+1.8VALW +1.8VALW_PCH

PJ1301
1 2
1 2
+VCCIN_AUX JUMP_43X39

UC1N +VCCPRIM_3P3
@
AH1 DF23
AW10 VCCIN_AUX_1 VCCPRIM_3P3_2 DG26
AY11 VCCIN_AUX_2 VCCPRIM_3P3_3 DG28 +3VALW_PCH +VCCPDSW_3P3
AY9 VCCIN_AUX_3 VCCPRIM_3P3_4
BA10 VCCIN_AUX_4 +VCCPRIM_1P8 4mA
D
BB9 VCCIN_AUX_5 RC1302 1 2 0_0402_5% @ D
VCCIN_AUX_6

1U_6.3V_M_X5R_0201
CH1 DF15 VCCDSW_3P3:
CK11 VCCIN_AUX_7 VCCPRIM_1P8_2 DF17
VCCIN_AUX_8 VCCPRIM_1P8_3 1 1x0402(holder）DE31

CC1301
CL10 DF18
CM11 VCCIN_AUX_9 VCCPRIM_1P8_4 DF20
CN1 VCCIN_AUX_10 VCCPRIM_1P8_5 DG17
AJ1 VCCIN_AUX_11 VCCPRIM_1P8_6 DG18 2
CN10 VCCIN_AUX_12 VCCPRIM_1P8_7 DG20 @
CP11 VCCIN_AUX_13 VCCPRIM_1P8_8 DF34
CR10 VCCIN_AUX_14 VCCPRIM_1P8_9
CT11 VCCIN_AUX_15
CU10 VCCIN_AUX_16
CV1 VCCIN_AUX_17 +3VALW_PCH +VCCPRIM_3P3
CV11 VCCIN_AUX_18 202mA
CW10 VCCIN_AUX_19 DW37 INTERNAL RAIL. RC1303 1 2 0_0402_5% @
VCCIN_AUX_20 VCCLDOSTD_0P85 +VCCLDOSTD_OUT_0P85
CY11 VCCPRIM_3P3:
VCCIN_AUX_21

1U_6.3V_M_X5R_0201

0.1U_6.3V_K_X5R_0201
DC1 DW15 0.165A +VCCA_CLKLDO_1P8 1 1 1x0402(holder）DG26
VCCIN_AUX_22 VCCA_CLKLDO_1P8

CC1302

CC1303
AL1
P13 VCCIN_AUX_23 DW32 INTERNAL RAIL. 1x0402(holder）DF23
VCCIN_AUX_24 VCCDPHY_1P24 +VCCDPHY_1P24
R12
T13 VCCIN_AUX_25 DD34 INTERNAL RAIL. 2 2
VCCIN_AUX_26 VCCDSW_1P05 +VCCDSW_1P05

El
U12 @ @
DC11 VCCIN_AUX_27 BY2
+VCCIN_AUX DE12 VCCIN_AUX_28 VCC1P05_1 CB2
DF12 VCCIN_AUX_29 VCC1P05_2 CC1 FET TO VCCST_CPU & VCCSTG_CPU
VCCIN_AUX_30 VCC1P05_3 +VCC1.05_OUT_FET
AM1
AN1 VCCIN_AUX_31 CD1 SHORT TO CPU SIDE VCCPLL.
VCCIN_AUX_32 VCCPLL_2 +VCC1.05_OUT_SFR
1

AT11
RC1304 AT9 VCCIN_AUX_33 DG31 INTERNAL RAIL.
100_0402_1% AU10 VCCIN_AUX_34 VCCPRIM_1P05_1
VCCIN_AUX_35

et
AV9 DG29 +3VALW_PCH +V3.3A_1.8A_PCH_SPI
VCCIN_AUX_36 VCCPRIM_1P05_2 VCCPRIM_1P05 is internal supply rail.
2

VCCIN_AUX_VCCSENSE BF9 DF29 Do not connect to external supply 3mA SPI

55 VCCIN_AUX_VCCSENSE VCCIN_AUX_VSSSENSE VCCIN_AUX_VCCSENSE VCCPRIM_1P05_3 Merge the pins together.
BD9 RC1305 1 2 0_0402_5% @
55 VCCIN_AUX_VSSSENSE VCCIN_AUX_VSSSENSE DF31 +VCC1.05_OUT_PCH
VCCPRIM_1P05_4
1

1U_6.3V_M_X5R_0201

0.1U_6.3V_K_X5R_0201
RC1306 DG33 VCCRTC 1 1
VCCRTC

CC1304

CC1305
C 100_0402_1% +V1.05A_BYPASS 1.05V 0.2A DJ15 C
VCC_V1P05EXT_1P05

ro
DE31 +VCCPDSW_3P3
1.05V / 0.76V 0.2A CY34 VCCDSW_3P3
+VNN_BYPASS
2

VCC_VNNEXT_1P05 DF26 VID[1] VID[0] VCCIN_AUX 2 2

VCCPGPPR +VCCPGPPR_3P3_1P8
+VCCPRIM_3P3
DC33 0 0 0
VCCPRIM_3P3_1 CL38 VCCIN_AUX_VID0 0 1 1.1 @ @
GPP_B0/CORE_VID0 VCCIN_AUX_VID1 VCCIN_AUX_VID0 55
+VCCPRIM_1P8
DD35 CJ38 1 0 1.65
VCCPRIM_1P8_1 GPP_B1/CORE_VID1 CN38 GPPC_B2_VRALERT_N VCCIN_AUX_VID1 55
1 1 1.8
DB34 GPP_B2/VRALERT_N
+V3.3A_1.8A_PCH_SPI VCCSPI

-X
ICELAKE-U_BGA1526
@
14 of 19

https://vinafix.com +1.8VALW_PCH

Te
+VCCPRIM_1P8
+3VALW_PCH PJ1308 1.3A
1 2
1 2

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201
JUMP_43X39
RC1312 VCCPRIM_1P8:
@ 1 1 1

CC1308

CC1309

CC1310
20K_0201_5% 1x0402(holder）DG20
DC1301

2
2 1 GPPC_B2_VRALERT_N 2 2 2
6,44,55 H_PROCHOT#
2 1 @ @ @

ch
RB521CM-30T2R_VMN2M-2

RC1314 1 @ 2 0_0402_5%

B B
+1.8VALW_PCH +VCCPGPPR_3P3_1P8

5mA

ni
RC1307 1 2 0_0402_5% @
VCCPGPPR:Audio Power:

1U_6.3V_M_X5R_0201

0.1U_6.3V_K_X5R_0201
1 1

CC1306

CC1307
2 2
@ @

ca
VCCRTC +VCC1.05_OUT_SFR +VCCDSW_1P05 +VCCDPHY_1P24 +VCCLDOSTD_OUT_0P85 +V1.05A_BYPASS +VNN_BYPASS +VCCPRIM_1P8 +VCCA_CLKLDO_1P8

0.165A

l
RC1310 1 2 0_5%_0603 @ VCCA_CLKLDO_1P8:
1

1
1U_6.3V_M_X5R_0201

0.1U_6.3V_K_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

100K_0201_5%

1K_0402_5%

By Default: 47uF 0603 is stuffed

1 1 1 1 1 1 1 with a 0 Ohm resistor; Inductor is
CC1316

CC1317

CC1218

CC1219

CC1312

CC1313
4.7U_0402_6.3V6M

CC1311
2.2U_0402_6.3V6M

RC1309

RC1311

LC1301
placeholder; 100mOhm Resistor is

0_0402_5%
1 2 stuffed only when Inductor is

RC1313
0.6UH_HBLE041B-R60MSA_7.65A_20% stuffed.
2 2 2 2 2 2 2 @ @ Place the component near to package
2

@ @ pin
@ DW15 right after signal breakout.

2
It is recommended to have GND
shield around the VCC trace

47U_6.3V_M_X5R_0805_H1.25

1U_6.3V_M_X5R_0201
1 1 routing, and minimum of 4nH of loop

CC1314

CC1315
inductance from BGA to LC filter

2 2

A VCCRTC: VCCPLL: VCCDSW_1P05: VCCDSW_1P05: VCCLDOSTD_0P85 For volume segment platform this rail is disabled. @ A
Keep the pin floating (do not short this pin to
1x0.1uF 0402 DG33 1x1uF 0402 SOC 1x1uF 0402 DD34 1x4.7uF 0402 1x2.2uF 0402 ground).
1x1uF 0402 1x0402 (holder） edge w/i3 mm edge w/i 3 mm

Security Classification LC Future Center Secret Data Title

Issued Date 2018/12/04 Deciphered Date 2018/08/20 S740-ICL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Name Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday, December 06, 2019 Sheet 13 of 60
5 4 3 2 1
 5 4 3 2 1

UC1O UC1P

A11 AF45 BT3 CR37

A46 VSS_1 VSS_75 AF47 BT39 VSS_149 VSS_223 CR45
D
BA45 VSS_2 VSS_76 AG1 BT41 VSS_150 VSS_224 CR49 D
BA47 VSS_3 VSS_77 AG11 BT42 VSS_151 VSS_225 CT37 UC1Q
BB11 VSS_4 VSS_78 AG3 BT43 VSS_152 VSS_226 CT39 DJ33 F11
BB3 VSS_5 VSS_79 AG38 BT7 VSS_153 VSS_227 CT42 DJ36 VSS_297 VSS_362 F31
BB7 VSS_6 VSS_80 AG39 BU45 VSS_154 VSS_228 CT9 DJ42 VSS_298 VSS_363 F45
BC37 VSS_7 VSS_81 AG41 BU47 VSS_155 VSS_229 CU45 DK3 VSS_299 VSS_364 F47
BD3 VSS_8 VSS_82 A31 BV1 VSS_156 VSS_230 CU47 DK4 VSS_300 VSS_365 F8
BD38 VSS_9 VSS_83 AG42 BV11 VSS_157 VSS_231 CU49 DK49 VSS_301 VSS_366 G21
BD39 VSS_10 VSS_84 AG43 BV2 VSS_158 VSS_232 CV3 DK6 VSS_302 VSS_367 G24
BD41 VSS_11 VSS_85 AG5 BV3 VSS_159 VSS_233 CV34 DK8 VSS_303 VSS_368 G3
A48 VSS_12 VSS_86 AG9 BV7 VSS_160 VSS_234 CV35 DL10 VSS_304 VSS_369 G31
BD42 VSS_13 VSS_87 AH2 BW3 VSS_161 VSS_235 CV5 DL13 VSS_305 VSS_370 G36
BD43 VSS_14 VSS_88 AH37 BW37 VSS_162 VSS_236 CV9 DL44 VSS_306 VSS_371 G49
BD45 VSS_15 VSS_89 AH45 BW5 VSS_163 VSS_237 CY41 DL47 VSS_307 VSS_372 G5
BD49 VSS_16 VSS_90 AH49 BW6 VSS_164 VSS_238 CY45 DM47 VSS_308 VSS_373 H17
BD5 VSS_17 VSS_91 AJ2 BW7 VSS_165 VSS_239 CY49 DN15 VSS_309 VSS_374 H21
BD6 VSS_18 VSS_92 AJ3 BY37 VSS_166 VSS_240 CY9 DN19 VSS_310 VSS_375 H24
BD7 VSS_19 VSS_93 A34 BY45 VSS_167 VSS_241 D13 DN24 VSS_311 VSS_376 H31
BE1 VSS_20 VSS_94 AK37 BY49 VSS_168 VSS_242 D17 DN31 VSS_312 VSS_377 H33
BE2 VSS_21 VSS_95 AL2 C11 VSS_169 VSS_243 D31 DN36 VSS_313 VSS_378 H36
BF3 VSS_22 VSS_96 AL45 C13 VSS_170 VSS_244 D44 DN42 VSS_314 VSS_379 H45
VSS_23 VSS_97 VSS_171 VSS_245 VSS_315 VSS_380

El
A49 AL47 C14 D49 DP45 H49
BF45 VSS_24 VSS_98 AL6 C17 VSS_172 VSS_246 DA10 DR49 VSS_316 VSS_381 J10
BF47 VSS_25 VSS_99 AM2 C21 VSS_173 VSS_247 DA33 DT1 VSS_317 VSS_382 J13
BF7 VSS_26 VSS_100 AM37 C24 VSS_174 VSS_248 DA9 DT10 VSS_318 VSS_383 J16
BG3 VSS_27 VSS_101 AN2 C31 VSS_175 VSS_249 DB32 DT15 VSS_319 VSS_384 J36
BG41 VSS_28 VSS_102 AN38 C34 VSS_176 VSS_250 DB35 DT20 VSS_320 VSS_385 J6
BG7 VSS_29 VSS_103 AN39 C39 VSS_177 VSS_251 DB38 DT27 VSS_321 VSS_386 K11
BH37 VSS_30 VSS_104 A36 C48 VSS_178 VSS_252 DB45 DT3 VSS_322 VSS_387 K33
BJ1 VSS_31 VSS_105 AN41 C49 VSS_179 VSS_253 DB47 DT32 VSS_323 VSS_388 K8
VSS_32 VSS_106 VSS_180 VSS_254 VSS_324 VSS_389

et
BJ2 AN42 C6 DB49 DT37 L36
BJ3 VSS_33 VSS_107 AN43 CA3 VSS_181 VSS_255 DC3 DT42 VSS_325 VSS_390 L39
AA45 VSS_34 VSS_108 AN45 CA38 VSS_182 VSS_256 DC49 DT49 VSS_326 VSS_391 L41
BJ41 VSS_35 VSS_109 AN49 CA41 VSS_183 VSS_257 DC5 DT6 VSS_327 VSS_392 L42
BJ43 VSS_36 VSS_110 AN6 CA42 VSS_184 VSS_258 DC6 DT7 VSS_328 VSS_393 L43
BJ45 VSS_37 VSS_111 AR1 CA43 VSS_185 VSS_259 DD37 DT8 VSS_329 VSS_394 L45
BJ49 VSS_38 VSS_112 AR11 CA7 VSS_186 VSS_260 DD42 DU1 VSS_330 VSS_395 L47
C BJ7 VSS_39 VSS_113 AR2 CB37 VSS_187 VSS_261 DE10 DU10 VSS_331 VSS_396 M10 C
VSS_40 VSS_114 VSS_188 VSS_262 VSS_332 VSS_397

ro
BM11 AR3 CB45 DE13 DU15 M3
BM3 VSS_41 VSS_115 A39 CB47 VSS_189 VSS_263 DE17 DU2 VSS_333 VSS_398 M36
BM45 VSS_42 VSS_116 AR7 CC3 VSS_190 VSS_264 DE18 DU20 VSS_334 VSS_399 M5
BM47 VSS_43 VSS_117 AR9 CC7 VSS_191 VSS_265 DE20 DU27 VSS_335 VSS_400 N45
BM5 VSS_44 VSS_118 AT3 CE37 VSS_192 VSS_266 DE22 DU32 VSS_336 VSS_401 N49
AA47 VSS_45 VSS_119 AT45 CE45 VSS_193 VSS_267 DE23 DU37 VSS_337 VSS_402 P11
BM6 VSS_46 VSS_120 AT47 CE49 VSS_194 VSS_268 DE26 DU48 VSS_338 VSS_403 P41
BM7 VSS_47 VSS_121 AT5 CE9 VSS_195 VSS_269 DE28 DU49 VSS_339 VSS_404 P8
BP1 VSS_48 VSS_122 AT6 CG37 VSS_196 VSS_270 DE29 DU7 VSS_340 VSS_405 R3
VSS_49 VSS_123 VSS_197 VSS_271 VSS_341 VSS_406

-X
BP2 AT7 CG39 DE33 DV2 R37
BP3 VSS_50 VSS_124 AU37 CG43 VSS_198 VSS_272 DE45 DV44 VSS_342 VSS_407 T11
BP43 VSS_51 VSS_125 AV11 CG45 VSS_199 VSS_273 DE6 DV48 VSS_343 VSS_408 T36
BP7 VSS_52 VSS_126 A42 CG47 VSS_200 VSS_274 DF13 DV8 VSS_344 VSS_409 T41
BR45 VSS_53 VSS_127 AV3 CG9 VSS_201 VSS_275 DF22 DW1 VSS_345 VSS_410 T43
BR49 VSS_54 VSS_128 AV38 CH3 VSS_202 VSS_276 DF28 DW10 VSS_346 VSS_411 T45

https://vinafix.com
AB11 VSS_55 VSS_129 AV39 CH5 VSS_203 VSS_277 DF33 DW2 VSS_347 VSS_412 T47
AB3 VSS_56 VSS_130 AV41 CJ37 VSS_204 VSS_278 DF35 DW20 VSS_348 VSS_413 U3
AB38 VSS_57 VSS_131 AV42 CJ42 VSS_205 VSS_279 DF39 DW27 VSS_349 VSS_414 U37
AB39 VSS_58 VSS_132 AV43 CJ9 VSS_206 VSS_280 DG10 DW44 VSS_350 VSS_415 U5

Te
AB41 VSS_59 VSS_133 AV45 CK45 VSS_207 VSS_281 DG12 DW46 VSS_351 VSS_416 V11
A17 VSS_60 VSS_134 AV49 CK49 VSS_208 VSS_282 DG13 DW48 VSS_352 VSS_417 V36
AB42 VSS_61 VSS_135 AV7 CK9 VSS_209 VSS_283 DG15 DW49 VSS_353 VSS_418 V45
AB43 VSS_62 VSS_136 AY3 CL37 VSS_210 VSS_284 DG22 DW7 VSS_354 VSS_419 V49
AB5 VSS_63 VSS_137 A44 CL42 VSS_211 VSS_285 DG23 E11 VSS_355 VSS_420 V9
AB6 VSS_64 VSS_138 AY7 CL49 VSS_212 VSS_286 DG47 E34 VSS_356 VSS_421 W37
AC45 VSS_65 VSS_139 B17 CM45 VSS_213 VSS_287 DG6 E36 VSS_357 VSS_422 Y36
AC49 VSS_66 VSS_140 B2 CM47 VSS_214 VSS_288 DH1 E39 VSS_358 VSS_423 Y38
AD10 VSS_67 VSS_141 B21 CM9 VSS_215 VSS_289 DH3 E42 VSS_359 VSS_424 Y43
AD11 VSS_68 VSS_142 B24 CN3 VSS_216 VSS_290 DH45 E6 VSS_360 VSS_425 Y9
AD34 VSS_69 VSS_143 B3 CN37 VSS_217 VSS_291 DH5 VSS_361 VSS_426 DE15
AD37 VSS_70 VSS_144 B31 CN39 VSS_218 VSS_292 DJ19 VSS_427

ch
A3 VSS_71 VSS_145 B48 CN5 VSS_219 VSS_293 DJ21 ICELAKE-U_BGA1526
AE6 VSS_72 VSS_146 BA1 CP9 VSS_220 VSS_294 DJ27 @
AF37 VSS_73 VSS_147 BA2 CR32 VSS_221 VSS_295 DJ31
VSS_74 VSS_148 VSS_222 VSS_296 17 of 19

15 of 19 16of 19
ICELAKE-U_BGA1526 ICELAKE-U_BGA1526
B B
@ @

ni
ca
Vinafix.com

l
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/12/04 Deciphered Date 2018/08/20 S740-ICL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Name Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday, December 06, 2019 Sheet 15 of 60
5 4 3 2 1
 5 4 3 2 1

PROCESSOR CFG STRAPS

+VCCIO_OUT

RC1606 1 2 1K_0201_5%
UC1R
CFG0 RC1601 1 @ 2 1K_0201_5%
N34 DA11
AK10 RSVD_TP_27 RSVD_TP_35 CL32
BT36 RSVD_TP_28 RSVD_TP_36 CN32
AH10 RSVD_7 RSVD_TP_37 CY35
D
BC10 RSVD_TP_29 RSVD_32 DB37 D
CH33 RSVD_TP_30 RSVD_33 DF37
RSVD_TP_31 RSVD_34 Stall reset sequence after PCU
CJ32 BF11 IST_TP_0 1 TP1601 Test_Point_12MIL
AM10 RSVD_12 IST_TP_0 BD11 IST_TP_1 1 TP1602 Test_Point_12MIL PLL lock until de-asserted
BH10 RSVD_TP_32 IST_TP_1 BE10 IST_TRIG_0 1 TP1603 Test_Point_12MIL
J34 RSVD_TP_33 IST_TRIG_0 BF10 IST_TRIG_1 1 TP1604 Test_Point_12MIL
1:Normal(Default)
Y11
L34
RSVD_TP_34

RSVD_9
IST_TRIG_1

PCH_IST_TP_0
CW33
CY32
PCH_IST_TP_0
PCH_IST_TP_1
1
1
TP1605 Test_Point_12MIL
TP1607 Test_Point_12MIL
CFG0 *
RSVD_10 PCH_IST_TP_1 0:Stall
AJ11 CY37
CG32 RSVD_17 RSVD_27 CV37
RSVD_21 RSVD_28

CK33 +VCCIO_OUT
BP41 RSVD_22 G34
AL11 RSVD_20 RSVD_35 H34
BG11 RSVD_23 RSVD_46 DJ34 CFG1 RC1607 1 2 1K_0201_5%
AN11 RSVD_24 RSVD_48 DK31
M13 RSVD_16 RSVD_49 DK15 CFG8 RC1608 1 2 1K_0201_5%
TP_M34 RSVD_18 RSVD_50

El
Test_Point_12MIL TP1608 1 M34 CP3
RSVD_19 RSVD_51 CP5 CFG9 RC1609 1 2 1K_0201_5%
RSVD_52 AN9
RSVD_53 AN7 CFG10 RC1610 1 2 1K_0201_5%
RSVD_54 AF10
DU42 RSVD_36 AE11 CFG12 RC1611 1 2 1K_0201_5%
DW42 RSVD_42 RSVD_37 H5
D33 RSVD_43 RSVD_38 D1 CFG13 RC1612 1 2 1K_0201_5%
L13 RSVD_44 RSVD_39 DJ40
RSVD_45 RSVD_40

et
K13 DK40
RSVD_47 RSVD_41

ICELAKE-U_BGA1526
18 of 19
@
C C

ro
CFG4 RC1602 1 2 1K_0402_5%

-X
UC1S

CFG0 AG6 A47

CFG1 AE7 CFG_0 RSVD_TP_1 B47
AG7 CFG_1 RSVD_TP_2
Test_Point_12MIL TP1611 1 AD9 CFG_2 C1

https://vinafix.com
CFG4 AE9 CFG_3 RSVD_57 E1
AB9 CFG_4
CFG_5
RSVD_58 Embedded Display Port Presence Strap
Test_Point_12MIL TP1613 1 AJ6 CT32
AB7 CFG_6 RSVD_TP_10 CV32
1:Disable

Te
CFG8 V10 CFG_7 RSVD_TP_11
CFG9 AJ5 CFG_8 G15
CFG10 Y10 CFG_9 RSVD_79 F15 CFG4
0:Enable(Default)
CFG12
CFG13
AJ7
AB10
AL7
CFG_10
CFG_11
CFG_12
RSVD_80

RSVD_TP_5
BW11
CA11
*
AL9 CFG_13 RSVD_TP_6
AJ9 CFG_14 C16
CFG_15 VSS_428 A16
CFG16 V6 VSS_429
Test_Point_12MIL TP1615 1 V7 CFG_16 C2
CFG_17 RSVD_55 A4

ch
CFG18 Y6 RSVD_56
Y7 CFG_18 DP5
CFG_19 RSVD_65 DR5
RC1603 2 1 1/20W_49.9_1%_0201 AD6 RSVD_66
CFG_RCOMP D14
Test_Point_12MIL TP1617 1 T9 RSVD_59 E16
B
Test_Point_12MIL TP1618 1 T7 BPM_N_0 RSVD_60 B

Test_Point_12MIL TP1619 1 T10 BPM_N_1 DV6

Test_Point_12MIL TP1620 1 T6 BPM_N_2 RSVD_TP_13 DW6
BPM_N_3 RSVD_TP_14

ni
BJ11 DP2
BL10 RSVD_62 RSVD_TP_24 DP1
RSVD_63 RSVD_TP_25
Test_Point_12MIL TP1621 1 AV1 DW4
RSVD_TP_17 RSVD_TP_15 DV4
AT2 RSVD_TP_16
AT1 RSVD_TP_18 CM33
AU1 RSVD_TP_20 TP_3 DB10 CFG16 RC1604 1 2 51_0402_5%

ca
AU2 RSVD_TP_19 TP_4
RSVD_TP_21 R1 CFG18 RC1605 1 2 51_0402_5%
AV2 RSVD_TP_12
RSVD_TP_22 DW3
DP3 RSVD_TP_7 DV3
DT2 RSVD_67 RSVD_TP_8
RSVD_68 DH49
AR10 RSVD_TP_9
AP10 RSVD_69 DL8
BP36 RSVD_71 RSVD_TP_23
RSVD_70

l
BM36 DW47
RSVD_72 TP_1 DV47
J15 TP_2 DU47
K15 VSS_430 VSS_432
VSS_431 P10
TP1622 1 C5 RSVD_TP_26
Test_Point_12MIL D4 SKTOCC_N
A5 RSVD_78
RSVD_64
19 of 19

ICELAKE-U_BGA1526
@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/12/04 Deciphered Date 2018/08/20 S740-ICL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Name Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday, December 06, 2019 Sheet 16 of 60
5 4 3 2 1
 5 4 3 2 1

+0.6VS +1.2V

DDR4 Memory Down DDRB_BG1_R

DDP@
2 0_0201_5% DDRB_BG1

1
RD1701 1 DDRB_BG1 5 2
RD1702 CD1701

1
0_0402_5% .01U_0402_16V7-K
RD1765 @ M D@
0_0201_5% 1

2
SDP@

2
DDRB_CLK0#
RD1704 1 M D@ 2 1/20W_39_5%_0201
UD1701 UD1702 DDRB_CLK0 RD1705 1 M D@ 2 1/20W_39_5%_0201
DDRB_M A0 P3 G2 DDRB_DQ11 DDRB_M A0 P3 G2 DDRB_DQ61
5 DDRB_M A0 DDRB_M A1 P7 A0 DQL0 F7 DDRB_DQ8 DDRB_M A1 P7 A0 DQL0 F7 DDRB_DQ60
5 DDRB_M A1 DDRB_M A2 R3 A1 DQL1 H3 DDRB_DQ14 DDRB_M A2 R3 A1 DQL1 H3 DDRB_DQ59
5 DDRB_M A2 DDRB_M A3 N7 A2 DQL2 H7 DDRB_DQ15 DDRB_M A3 N7 A2 DQL2 H7 DDRB_DQ57 +0.6VS
5 DDRB_M A3 DDRB_M A4 N3 A3 DQL3 H2 DDRB_DQ9 DDRB_M A4 N3 A3 DQL3 H2 DDRB_DQ62
5 DDRB_M A4 DDRB_M A5 P8 A4 DQL4 H8 DDRB_DQ10 Byte 1 DDRB_M A5 P8 A4 DQL4 H8 DDRB_DQ58 Byte 7 UD1_DDRB_UZQ
RD1706 1 SDP@ 2 0_0402_5%
5 DDRB_M A5 DDRB_M A6 P2 A5 DQL5 J3 DDRB_DQ12 DDRB_M A6 P2 A5 DQL5 J3 DDRB_DQ63 DDRB_M A0
RD1713 1 M D@ 2 1/20W_39_5%_0201
5 DDRB_M A6 DDRB_M A7 R8 A6 DQL6 J7 DDRB_DQ13 DDRB_M A7 R8 A6 DQL6 J7 DDRB_DQ56 1 DDP@ 2 240_0402_1% DDRB_M A1
D RD1709 RD1714 1 M D@ 2 1/20W_39_5%_0201 D
5 DDRB_M A7 DDRB_M A8 R2 A7 DQL7 A3 DDRB_DQ4 DDRB_M A8 R2 A7 DQL7 A3 DDRB_DQ45 DDRB_M A2 RD1716 1 M D@ 2 1/20W_39_5%_0201
5 DDRB_M A8 DDRB_M A9 R7 A8 DQU0 B8 DDRB_DQ6 DDRB_M A9 R7 A8 DQU0 B8 DDRB_DQ42 DDRB_M A3
RD1717 1 M D@ 2 1/20W_39_5%_0201
5 DDRB_M A9 DDRB_M A10 M3 A9 DQU1 C3 DDRB_DQ1 DDRB_M A10 M3 A9 DQU1 C3 DDRB_DQ47 UD2_DDRB_UZQ 1 SDP@ 2 0_0402_5%
RD1711
5 DDRB_M A10 DDRB_M A11 T2 A10/AP DQU2 C7 DDRB_DQ3 DDRB_M A11 T2 A10/AP DQU2 C7 DDRB_DQ41 DDRB_M A4 1 2 1/20W_39_5%_0201
RD1719 M D@
5 DDRB_M A11 DDRB_M A12 M7 A11 DQU3 C2 DDRB_DQ0 Byte 0 DDRB_M A12 M7 A11 DQU3 C2 DDRB_DQ46 Byte 5 RD1712 1 DDP@ 2 240_0402_1% DDRB_M A5
RD1720 1 M D@ 2 1/20W_39_5%_0201
5 DDRB_M A12 DDRB_M A13 T8 A12/BC_N DQU4 C8 DDRB_DQ7 DDRB_M A13 T8 A12/BC_N DQU4 C8 DDRB_DQ40 DDRB_M A6 RD1722 1 M D@ 2 1/20W_39_5%_0201
5 DDRB_M A13 A13 DQU5 D3 DDRB_DQ2 A13 DQU5 D3 DDRB_DQ43 DDRB_M A7 1 2 1/20W_39_5%_0201
RD1723 M D@
DDRB_M A14_WE# L2 DQU6 D7 DDRB_DQ5 DDRB_M A14_WE# L2 DQU6 D7 DDRB_DQ44 UD3_DDRB_UZQ 1 SDP@ 2 0_0402_5% DDRB_M A8 1 2 1/20W_39_5%_0201
RD1715 RD1725 M D@
5 DDRB_M A14_WE# DDRB_M A15_CAS# M8 WE_N/A14 DQU7 DDRB_M A15_CAS# M8 WE_N/A14 DQU7
5 DDRB_M A15_CAS# DDRB_M A16_RAS# L8 CAS_N/A15 +1.2V DDRB_M A16_RAS# L8 CAS_N/A15 +1.2V 1 DDP@ 2 240_0402_1% DDRB_M A9 1 2 1/20W_39_5%_0201
RD1718 RD1726 M D@
5 DDRB_M A16_RAS# RAS_N/A16 D1 RAS_N/A16 D1 DDRB_M A10 RD1727 1 M D@ 2 1/20W_39_5%_0201
DDRB_CLK0# K8 VDD1 J1 DDRB_CLK0# K8 VDD1 J1 DDRB_M A11 1 2 1/20W_39_5%_0201
5 DDRB_CLK0# DDRB_CLK0 DDRB_CLK0 UD4_DDRB_UZQ DDRB_M A12 RD1728 M D@
K7 CK_C VDD2 L1 K7 CK_C VDD2 L1 RD1721 1 SDP@ 2 0_0402_5% RD1729 1 M D@ 2 1/20W_39_5%_0201
5 DDRB_CLK0 CK_T VDD3 R1 CK_T VDD3 R1
DDRB_CKE0 K2 VDD4 B3 DDRB_CKE0 K2 VDD4 B3 1 DDP@ 2 240_0402_1%
5 DDRB_CKE0 RD1724
CKE VDD5 G7 CKE VDD5 G7 DDRB_M A13 RD1730 1 M D@ 2 1/20W_39_5%_0201
DDRB_DQS#1 F3 VDD6 B9 DDRB_DQS#7 F3 VDD6 B9 DDRB_M A14_WE#
DDRB_DQ[0..63] RD1731 1 M D@ 2 1/20W_39_5%_0201
DDRB_DQS1 G3 DQSL_C VDD7 J9 DDRB_DQS7 G3 DQSL_C VDD7 J9 DDRB_M A15_CAS#
RD1734 1 M D@ 2 1/20W_39_5%_0201
DDRB_DQS#0 A7 DQSL_T VDD8 L9 DDRB_DQ[0..63] 5 DDRB_DQS#5 A7 DQSL_T VDD8 L9 DDRB_M A16_RAS#
DDRB_DQS#[0..7] RD1737 1 M D@ 2 1/20W_39_5%_0201
+1.2V DDRB_DQS0 B7 DQSU_C VDD9 T9 +1.2V DDRB_DQS5 B7 DQSU_C VDD9 T9
DQSU_T VDD10 DDRB_DQS#[0..7] 5 DQSU_T VDD10
DDRB_DQS[0..7]
RD17321 2 0_0402_5%@ DDRB_DM 1 E2 A1 RD1733 1 2 0_0402_5%@ DDRB_DM 2 E2 A1 +1.2V DDRB_BG0
RD1738 1 M D@ 2 1/20W_39_5%_0201
RD17351 2 0_0402_5%@ DDRB_DM 0 E7 NF/UDM_N/UDBI_N VDDQ1 C1 DDRB_DQS[0..7] 5
RD1736 1 2 0_0402_5%@ DDRB_DM 3 E7 NF/UDM_N/UDBI_N VDDQ1 C1 DDRB_BG1_R
RD1739 1 DDP@ 2 1/20W_39_5%_0201
NF/LDM_N/LDBI_N VDDQ2 G1 NF/LDM_N/LDBI_N VDDQ2 G1
DDRB_BS0# N2 VDDQ3 F2 DDRB_BS0# N2 VDDQ3 F2 DDRB_BS0#
5 DDRB_BS0# RD1740 1 M D@ 2 1/20W_39_5%_0201
DDRB_BS1# N8 BA0 VDDQ4 J2 DDRB_BS1# N8 BA0 VDDQ4 J2 DDRB_BS1#
5 DDRB_BS1# 1 RD1741 1 M D@ 2 1/20W_39_5%_0201

1
BA1 VDDQ5 F8 BA1 VDDQ5 F8 CD1702
DDRB_ACT # L3 VDDQ6 J8 DDRB_ACT # L3 VDDQ6 J8 DDRB_ACT #
5 DDRB_ACT # 0.1U_6.3V_K_X5R_0201 RD1743 RD1742 1 M D@ 2 1/20W_39_5%_0201
DDRB_CS0# L7 ACT_N VDDQ7 A9 DDRB_CS0# L7 ACT_N VDDQ7 A9 1.8K_0402_1% DDRB_PAR RD1744 1 M D@ 2 1/20W_39_5%_0201
5 DDRB_CS0# DDRB_ALERT # CS_N VDDQ8 DDRB_ALERT # CS_N VDDQ8 @ 2
P9 D9 P9 D9 M D@
5 DDRB_ALERT # ALERT_N VDDQ9 G9 +2.5V_DDR ALERT_N VDDQ9 G9 DDRB_CKE0 RD1710 1 M D@ 2 1/20W_39_5%_0201
+2.5V_DDR

2
DDRB_BG0 M2 VDDQ10 DDRB_BG0 M2 VDDQ10
5 DDRB_BG0 BG0 B1 BG0 B1 DDRB_CS0#
RD1707 1 M D@ 2 1/20W_39_5%_0201
DDRB_ODT 0 K3 VPP1 R9 DDRB_ODT 0 K3 VPP1 R9 1 RD1748 2 M D@ +VREF_CA_M D
5 DDRB_ODT 0 ODT VPP2 ODT VPP2 5 DDR_SB_VREFCA DDRB_ODT 0

CD1703
1U_6.3V_M_X5R_0201

CD1704
1U_6.3V_M_X5R_0201
2.7_0402_1% RD1708 1 M D@ 2 1/20W_39_5%_0201

El
DDRB_PAR +VREF_CA_M D DDRB_PAR +VREF_CA_M D

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201
T3 M1 1 1 T3 M1 1
5 DDRB_PAR

1
PAR VREFCA PAR VREFCA

CD1707

CD1709
T EN_UD1 T EN_UD2 1
1 1

.047U_0402_16V7K

0.1U_6.3V_K_X5R_0201

.047U_0402_16V7K

0.1U_6.3V_K_X5R_0201
RD1745 1 M D@ 2 10K_0402_5% N9 E1 RD1747 1 M D@ 2 10K_0402_5% N9 E1 1 1 CD1711 CD1712

CD1710
TEN VSS1 TEN VSS1 RD1749

CD1705 MD@

CD1706

CD1708
K1 1 1 K1 0.022U_16V_K_X7R_0402 0.1U_6.3V_K_X5R_0201
CPU_DRAM RST # VSS2 2 2 CPU_DRAM RST # VSS2 2 1.8K_0402_1%

MD@

MD@
P1 N1 P1 N1 M D@
5,18 CPU_DRAM RST # RESET_N VSS3 T1 RESET_N VSS3 T1 M D@ 2 @
2 2

2
1
F1 VSS4 B2 F1 VSS4 B2 2 2
VSSQ1 VSS5 2 2 VSSQ1 VSS5 RD1752

MD@
H1 G8 H1 G8
VSSQ2 VSS6 VSSQ2 VSS6 24.9_0402_1% +1.2V

MD@
A2 K9 @ A2 K9 @ @
C
D2 VSSQ3 VSS8 D2 VSSQ3 VSS8 M D@ C

E3 VSSQ4 T7 1 DDP@ 2 E3 VSSQ4 T7 1 DDP@ 2 DDRB_ALERT # RD1746 1 M D@ 2 49.9_0402_1%

2
A8 VSSQ5 VSS7 RD1750 0_0402_5% A8 VSSQ5 VSS7 RD1751 0_0402_5%
VSSQ6 VSSQ6

et
D8 D8
E8 VSSQ7 M9 DDRB_BG1_R E8 VSSQ7 M9 DDRB_BG1_R
C9 VSSQ8 VSS9 C9 VSSQ8 VSS9
H9 VSSQ9 E9 UD1_DDRB_UZQ H9 VSSQ9 E9 UD2_DDRB_UZQ
VSSQ10 VSS10 VSSQ10 VSS10 VDDQ:
F9 F9 16x1uF 4 per DRAM
ZQ ZQ
5x10uF distribute evenly across dram
1

1
+1.2V
RD1753 RD1754
240_0402_1% 240_0402_1%
K4AAG165WA-BCWE_FBGA96 M D@ K4AAG165WA-BCWE_FBGA96 M D@ First DRAM 1x10uF 4x1uF 2nd DRAM 1x10uF 4x1uF
@ @
2

2
ro

CD1729
4.3U_0402_4V6-M

CD1723
1U_6.3V_M_X5R_0201

CD1724
1U_6.3V_M_X5R_0201

CD1719
1U_6.3V_M_X5R_0201

CD1713
1U_6.3V_M_X5R_0201

CD1732
10U 6.3V M X5R 0402

CD1731
4.3U_0402_4V6-M

CD1715
1U_6.3V_M_X5R_0201

CD1716
1U_6.3V_M_X5R_0201

CD1717
1U_6.3V_M_X5R_0201

CD1728
1U_6.3V_M_X5R_0201

CD1733
10U 6.3V M X5R 0402

CD1742
22P_0402_50V8-J
1 1 1 1 1 1 1 1 1 1 1

3
2

4
2 2 2 2 2 2 2 2 2 2 2@

MD_3T@

MD_N3T@

MD_N3T@

MD_N3T@

MD@

MD_3T@

MD_N3T@

MD_N3T@

MD@
UD1703
UD1704
DDRB_M A0 P3 G2 DDRB_DQ36
DDRB_M A1 P7 A0 DQL0 F7 DDRB_DQ38 DDRB_M A0 P3 G2 DDRB_DQ18
DDRB_M A2 R3 A1 DQL1 H3 DDRB_DQ34 DDRB_M A1 P7 A0 DQL0 F7 DDRB_DQ17
DDRB_M A3 A2 DQL2 DDRB_DQ35 DDRB_M A2 A1 DQL1 DDRB_DQ23

-X
N7 H7 R3 H3 UD1701 UD1704
DDRB_M A4 N3 A3 DQL3 H2 DDRB_DQ32 DDRB_M A3 N7 A2 DQL2 H7 DDRB_DQ21
DDRB_M A5 P8 A4 DQL4 H8 DDRB_DQ39 Byte 4 DDRB_M A4 N3 A3 DQL3 H2 DDRB_DQ19
DDRB_M A6 P2 A5 DQL5 J3 DDRB_DQ33 DDRB_M A5 P8 A4 DQL4 H8 DDRB_DQ16 Byte 2 3rd DRAM 1x10uF 4x1uF 4th DRAM 2x10uF 4x1uF
DDRB_M A7 R8 A6 DQL6 J7 DDRB_DQ37 DDRB_M A6 P2 A5 DQL5 J3 DDRB_DQ20
DDRB_M A8 R2 A7 DQL7 A3 DDRB_DQ49 DDRB_M A7 R8 A6 DQL6 J7 DDRB_DQ22
DDRB_M A9 R7 A8 DQU0 B8 DDRB_DQ51 DDRB_M A8 R2 A7 DQL7 A3 DDRB_DQ26
DDRB_M A10 A9 DQU1 DDRB_DQ50 DDRB_M A9 A8 DQU0 DDRB_DQ30

CD1721
1U_6.3V_M_X5R_0201

CD1725
1U_6.3V_M_X5R_0201

CD1722
1U_6.3V_M_X5R_0201

CD1718
1U_6.3V_M_X5R_0201

CD1734
10U 6.3V M X5R 0402

CD1730
4.3U_0402_4V6-M

1U_6.3V_M_X5R_0201

CD1727
1U_6.3V_M_X5R_0201

CD1726
1U_6.3V_M_X5R_0201

CD1714
1U_6.3V_M_X5R_0201

CD1735
10U 6.3V M X5R 0402

CD1736
10U 6.3V M X5R 0402

CD1741
22P_0402_50V8-J
M3 C3 R7 B8

https://vinafix.com
DDRB_M A11 A10/AP DQU2 DDRB_DQ55 DDRB_M A10 A9 DQU1 DDRB_DQ31

CD1720 @
T2 C7 M3 C3
DDRB_M A12 A11 DQU3 DDRB_DQ52 Byte 6 DDRB_M A11 A10/AP DQU2 DDRB_DQ29 1 1 1 1 1 1 1 1 1 1 1 1

3
M7 C2 T2 C7
DDRB_M A13 T8 A12/BC_N DQU4 C8 DDRB_DQ54 DDRB_M A12 M7 A11 DQU3 C2 DDRB_DQ28 Byte 3
A13 DQU5 D3 DDRB_DQ48 DDRB_M A13 T8 A12/BC_N DQU4 C8 DDRB_DQ24

4
DDRB_M A14_WE# DQU6 DDRB_DQ53 A13 DQU5 DDRB_DQ27 2 2 2 2 2@ 2 2 2 2 2 2 2

MD_N3T@

MD_N3T@

MD_3T@

MD_N3T@

MD_N3T@

MD@

MD@
L2 D7 D3
DDRB_M A15_CAS# M8 WE_N/A14 DQU7 DDRB_M A14_WE# L2 DQU6 D7 DDRB_DQ25
@
DDRB_M A16_RAS# CAS_N/A15 +1.2V DDRB_M A15_CAS# WE_N/A14 DQU7

Te
L8 M8
RAS_N/A16 D1 DDRB_M A16_RAS# L8 CAS_N/A15 +1.2V
DDRB_CLK0# K8 VDD1 J1 RAS_N/A16 D1
B DDRB_CLK0 K7 CK_C VDD2 L1 DDRB_CLK0# K8 VDD1 J1 B
CK_T VDD3 R1 DDRB_CLK0 K7 CK_C VDD2 L1
DDRB_CKE0 VDD4 CK_T VDD3 UD1703 UD1702
K2 B3 R1
CKE VDD5 G7 DDRB_CKE0 K2 VDD4 B3
DDRB_DQS#4 F3 VDD6 B9 CKE VDD5 G7
DDRB_DQS4 G3 DQSL_C VDD7 J9 DDRB_DQS#2 F3 VDD6 B9
DDRB_DQS#6 A7 DQSL_T VDD8 L9 DDRB_DQS2 G3 DQSL_C VDD7 J9
+1.2V DDRB_DQS6 B7 DQSU_C VDD9 T9 DDRB_DQS#3 A7 DQSL_T VDD8 L9
DQSU_T VDD10 +1.2V DDRB_DQS3 B7 DQSU_C VDD9 T9
RD1755 1 2 0_0402_5%@ DDRB_DM 4 E2 A1 DQSU_T VDD10
RD1756 1 2 0_0402_5%@ DDRB_DM 5 E7 NF/UDM_N/UDBI_N VDDQ1 C1 RD1757 1 2 0_0402_5%@ DDRB_DM 6 E2 A1
NF/LDM_N/LDBI_N VDDQ2 G1 RD1758 1 2 0_0402_5%@ DDRB_DM 7 E7 NF/UDM_N/UDBI_N VDDQ1 C1
DDRB_BS0# N2 VDDQ3 F2 NF/LDM_N/LDBI_N VDDQ2 G1
DDRB_BS1# N8 BA0 VDDQ4 J2 DDRB_BS0# N2 VDDQ3 F2

ch
BA1 VDDQ5 F8 DDRB_BS1# N8 BA0 VDDQ4 J2
DDRB_ACT # L3 VDDQ6 J8 BA1 VDDQ5 F8
DDRB_CS0# ACT_N VDDQ7 DDRB_ACT # VDDQ6 +2.5V_DDR
L7 A9 L3 J8
DDRB_ALERT # P9 CS_N VDDQ8 D9 DDRB_CS0# L7 ACT_N VDDQ7 A9
ALERT_N VDDQ9 G9 +2.5V_DDR DDRB_ALERT # P9 CS_N VDDQ8 D9
DDRB_BG0 VDDQ10 ALERT_N VDDQ9 +2.5V_DDR
VPP:
M2 G9
8x1uF

CD1737
10U 6.3V M X5R 0402

CD1738
10U 6.3V M X5R 0402

CD1739
10U 6.3V M X5R 0402

CD1740
10U 6.3V M X5R 0402
BG0 DDRB_BG0 VDDQ10

CD1745
22P_0402_50V8-J

CD1746
22P_0402_50V8-J
B1 M2
DDRB_ODT 0 K3 VPP1 R9 BG0 B1 3x10uF
ODT VPP2 DDRB_ODT 0 VPP1 1 1 1 1 1 1
K3 R9
DDRB_PAR +VREF_CA_M D ODT VPP2
CD1747
1U_6.3V_M_X5R_0201

CD1749
1U_6.3V_M_X5R_0201

T3 M1
PAR VREFCA DDRB_PAR +VREF_CA_M D

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201
1 1 T3 M1

MD@

MD@

MD@

MD@
T EN_UD3 PAR VREFCA 2 2 2 2 2@ 2@
.047U_0402_16V7K

0.1U_6.3V_K_X5R_0201

CD1751 MD@

CD1752
RD1759 1 M D@ 2 10K_0402_5% N9 E1 1 1
TEN VSS1 2 10K_0402_5% T EN_UD4
CD1748 MD@

CD1750

K1 1 1 RD1760 1 M D@ N9 E1
CPU_DRAM RST # VSS2 TEN VSS1

CD1753 MD@
.047U_0402_16V7K

CD1754
0.1U_6.3V_K_X5R_0201
P1 N1 K1 1 1
RESET_N VSS3 T1 2 2 CPU_DRAM RST # P1 VSS2 N1

ni
VSS4 RESET_N VSS3 2 2
MD@

MD@

F1 B2 T1
H1 VSSQ1 VSS5 G8 2 2 F1 VSS4 B2 @
A2 VSSQ2 VSS6 K9 @ H1 VSSQ1 VSS5 G8 2 2
D2 VSSQ3 VSS8 A2 VSSQ2 VSS6 K9 @
E3 VSSQ4 T7 1 DDP@ 2 D2 VSSQ3 VSS8
A8 VSSQ5 VSS7
RD1761 0_0402_5% E3 VSSQ4 T7 1 DDP@ 2
D8 VSSQ6 A8 VSSQ5 VSS7 +0.6VS
RD1762 0_0402_5%
E8 VSSQ7 M9 DDRB_BG1_R D8 VSSQ6
C9 VSSQ8 VSS9 E8 VSSQ7 M9 DDRB_BG1_R
VSSQ9 UD3_DDRB_UZQ VSSQ8 VSS9
VTT:
H9 E9 C9 8x1uF
VSSQ10 VSS10 VSSQ9 UD4_DDRB_UZQ

CD1743

CD1744

CD1755
1U_6.3V_M_X5R_0201

CD1756
1U_6.3V_M_X5R_0201

CD1757
1U_6.3V_M_X5R_0201

CD1758
1U_6.3V_M_X5R_0201

CD1759
1U_6.3V_M_X5R_0201

CD1760
1U_6.3V_M_X5R_0201

CD1761
1U_6.3V_M_X5R_0201

CD1762
1U_6.3V_M_X5R_0201

CD1764
10U 6.3V M X5R 0402

CD1763
10U 6.3V M X5R 0402

CD1765
22P_0402_50V8-J

CD1766
22P_0402_50V8-J
F9 H9 E9

ca
4.3U_0402_4V6-M

4.3U_0402_4V6-M
ZQ VSSQ10 VSS10 F9
2x10uF
1 1 1 1 1 1 1 1 1 1 1 1
1

3
ZQ
1

RD1763
240_0402_1% RD1764

4
K4AAG165WA-BCWE_FBGA96 2 2 2 2 2 2 2 2 2 2 2 2

MD_3T@

MD_3T@

MD_N3T@

MD_N3T@

MD_N3T@

MD_N3T@

MD_N3T@

MD_N3T@

MD@
A M D@ 240_0402_1% A
@ K4AAG165WA-BCWE_FBGA96 M D@ @ @ @
2

@
2

l
Security Clas s ification LC Future Center Secret Data Title

Issued Date 2017/06/24 Deciphered Date 2018/06/23 DDR4 Memory Down

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Docum ent Num ber Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday , December 06, 2019 Sheet 17 of 60
5 4 3 2 1
 5 4 3 2 1

DDR4 SO-DIMM +1.2V

1
+1.2V +1.2V
JDDR1B
RD1801
+1.2V JDDR1A +1.2V 240_0402_1%
@
DDRA_MA3 131 132 DDRA_MA2

2
1 2 DDRA_MA1 133 A3 A2 134 DDRA_EVENT#
DDRA_DQ61 3 VSS_1 VSS_2 4 DDRA_DQ60 135 A1 EVENT_n 136
5 DQ5 DQ4 6 DDRA_CLK0 137 VDD_9 VDD_10 138 DDRA_CLK1
DDRA_DQ62 VSS_3 VSS_4 DDRA_DQ58 5 DDRA_CLK0 DDRA_CLK0# CK0_t CK1_t DDRA_CLK1# DDRA_CLK1 5
7 8 139 140
9 DQ1 DQ0 10 DDRA_DQ[0..63] 5 DDRA_CLK0# 141 CK0_c CK1_c 142 DDRA_CLK1# 5
DDRA_DQS#7 VSS_5 VSS_6 DDRA_DQ[0..63] 5 DDRA_PAR VDD_11 VDD_12 DDRA_MA0
11 12 143 144
DDRA_DQS7 DQS0_C DM0_n/DBIO_n/NC DDRA_DQS#[0..7] 5 DDRA_PAR Parity A0
13 14
DQS0_t VSS_7 DDRA_DQ57 DDRA_DQS#[0..7] 5
15 16
D DDRA_DQ56 17 VSS_8 DQ6 18 DDRA_DQS[0..7] DDRA_BS1# 145 146 DDRA_MA10 D
19 DQ7 VSS_9 20 DDRA_DQ59 DDRA_DQS[0..7] 5 5 DDRA_BS1# 147 BA1 A10/AP 148
DDRA_DQ63 21 VSS_10 DQ2 22 DDRA_MA[0..13] DDRA_CS0# 149 VDD_13 VDD_14 150 DDRA_BS0#
DQ3 VSS_11 DDRA_DQ53 DDRA_MA[0..13] 5 5 DDRA_CS0# DDRA_MA14_WE# CS0_n BA0 DDRA_MA16_RAS# DDRA_BS0# 5
23 24 5 DDRA_MA14_WE#
151 152
DDRA_DQ51 VSS_12 DQ12 WE_n/A14 RAS_n/A16 DDRA_MA16_RAS# 5
25 26 153 154
27 DQ13 VSS_13 28 DDRA_DQ55 DDRA_ODT0 155 VDD_15 VDD_16 156 DDRA_MA15_CAS#
DDRA_DQ54 29 VSS_14 DQ8 30 5 DDRA_ODT0 DDRA_CS1# 157 ODT0 CAS_n/A15 158 DDRA_MA13 DDRA_MA15_CAS# 5
31 DQ9 VSS_15 32 DDRA_DQS#6 5 DDRA_CS1# 159 CS1_n A13 160
33 VSS_16 DQS1_c 34 DDRA_DQS6 DDRA_ODT1 161 VDD_17 VDD_18 162
35 DM1_n/DBl1_n/NC DQS1_t 36 5 DDRA_ODT1 163 ODT1 C0/CS2_n/NC 164 +VREF_CA_DIMM
DDRA_DQ50 37 VSS_17 VSS_18 38 DDRA_DQ49 165 VDD_19 VREFCA 166 DDRA_SA2
DQ15 DQ14 C1/CS3_n/NC SA2

0.1U_6.3V_K_X5R_0201

2.2U_0402_6.3V6M
39 40 167 168
DDRA_DQ48 VSS_19 VSS_20 DDRA_DQ52 DDRA_DQ25 VSS_53 VSS_54 DDRA_DQ28

CD1801

CD1802
41 42 169 170 1 1
43 DQ10 DQ11 44 171 DQ37 DQ36 172
DDRA_DQ35 45 VSS_21 VSS_22 46 DDRA_DQ37 DDRA_DQ24 173 VSS_55 VSS_56 174 DDRA_DQ26
47 DQ21 DQ20 48 175 DQ33 DQ32 176
DDRA_DQ39 49 VSS_23 VSS_24 50 DDRA_DQ38 DDRA_DQS#3 177 VSS_57 VSS_58 178 2 2
51 DQ17 DQ16 52 DDRA_DQS3 179 DQS4_c DM4_n/DBl4_n/NC 180
DDRA_DQS#4 53 VSS_25 VSS_26 54 181 DQS4_t VSS_59 182 DDRA_DQ31 @
DDRA_DQS4 55 DQS2_c DM2_n/DBl2_n/NC 56 DDRA_DQ29 183 VSS_60 DQ39 184
57 DQS2_t VSS_27 58 DDRA_DQ32 185 DQ38 VSS_61 186 DDRA_DQ30
DDRA_DQ33 VSS_28 DQ22 DDRA_DQ27 VSS_62 DQ35

El
59 60 187 188
61 DQ23 VSS_29 62 DDRA_DQ34 189 DQ34 VSS_63 190 DDRA_DQ22
DDRA_DQ36 63 VSS_30 DQ18 64 DDRA_DQ19 191 VSS_64 DQ45 192
65 DQ19 VSS_31 66 DDRA_DQ40 193 DQ44 VSS_65 194 DDRA_DQ23
DDRA_DQ44 67 VSS_32 DQ28 68 DDRA_DQ21 195 VSS_66 DQ41 196
69 DQ29 VSS_33 70 DDRA_DQ42 197 DQ40 VSS_67 198 DDRA_DQS#2
DDRA_DQ41 71 VSS_34 DQ24 72 199 VSS_68 DQS5_c 200 DDRA_DQS2
73 DQ25 VSS_35 74 DDRA_DQS#5 201 DM5_n/DBl5_n/NC DQS5_t 202
+1.2V 75 VSS_36 DQS3_c 76 DDRA_DQS5 DDRA_DQ18 203 VSS_69 VSS_70 204 DDRA_DQ17
DM3_n/DBl3_n/NC DQS3_t DQ46 DQ47

et
77 78 205 206
DDRA_DQ46 79 VSS_37 VSS_38 80 DDRA_DQ43 DDRA_DQ20 207 VSS_71 VSS_72 208 DDRA_DQ16
81 DQ30 DQ31 82 209 DQ42 DQ43 210
DDRA_DQ47 83 VSS_39 VSS_40 84 DDRA_DQ45 DDRA_DQ6 211 VSS_73 VSS_74 212 DDRA_DQ5
DQ26 DQ27 DQ52 DQ53
1

85 86 213 214
RD1802 87 VSS_41 VSS_42 88 DDRA_DQ3 215 VSS_75 VSS_76 216 DDRA_DQ7
RD1803 89 CB5/NC CB4/NC 90 217 DQ49 DQ48 218
240_0402_1% 240_0402_1% 91 VSS_43 VSS_44 92 DDRA_DQS#0 219 VSS_77 VSS_78 220
C C
CB1/NC CB0/NC DDRA_DQS0 DQS6_c DM6_n/DBl6_n/NC

ro
93 94 221 222
2

DDRA_DQS#8 95 VSS_45 VSS_46 96 223 DQS6_t VSS_79 224 DDRA_DQ4

DDRA_DQS8 97 DQS8_c DM8_n/DBI8_n/NC 98 DDRA_DQ2 225 VSS_80 DQ54 226
99 DQS8_t VSS_47 100 227 DQ55 VSS_81 228 DDRA_DQ0
101 VSS_48 CB6/NC 102 DDRA_DQ1 229 VSS_82 DQ50 230
103 CB2/NC VSS_49 104 231 DQ51 VSS_83 232 DDRA_DQ8
105 VSS_50 CB7/NC 106 DDRA_DQ9 233 VSS_84 DQ60 234
107 CB3/NC VSS_51 108 CPU_DRAMRST# 235 DQ61 VSS_85 236 DDRA_DQ10
DDRA_CKE0 VSS_52 RESET_n DDRA_CKE1 CPU_DRAMRST# 5,17 DDRA_DQ12 VSS_86 DQ57

0.1U_6.3V_K_X5R_0201
109 110 237 238
5 DDRA_CKE0 CKE0 CKE1 DDRA_CKE1 5 DQ56 VSS_87 DDRA_DQS#1

-X
CD1803
111 112 1 239 240
DDRA_BG1 113 VDD_1 VDD_2 114 DDRA_ACT# 241 VSS_88 DQS7_c 242 DDRA_DQS1
5 DDRA_BG1 DDRA_BG0 BG1 ACT_n DDRA_ALERT# DDRA_ACT# 5 DM7_n/DBl7_n/NC DQS7_t
115 116 243 244
5 DDRA_BG0 BG0 ALERT_n DDRA_ALERT# 5 DDRA_DQ14 VSS_89 VSS_90 DDRA_DQ13
117 118 245 246
DDRA_MA12 119 VDD_3 VDD_4 120 DDRA_MA11 2@ 247 DQ62 DQ63 248
DDRA_MA9 121 A12 A11 122 DDRA_MA7 DDRA_DQ15 249 VSS_91 VSS_92 250 DDRA_DQ11

https://vinafix.com
123 A9 A7 124 251 DQ58 DQ59 252
DDRA_MA8 125 VDD_5 VDD_6 126 DDRA_MA5 SMB_CLK_S3 253 VSS_93 VSS_94 254 SMB_DATA_S3
DDRA_MA6 A8 A5 DDRA_MA4 7 SMB_CLK_S3 +VDD_SPD SCL SDA DDRA_SA0 SMB_DATA_S3 7
127 128 255 256
129 A6 A4 130 257 VDDSPD SA0 258

2.2U_0402_6.3V6M
+0.6VS

Te
VDD_7 VDD_8 VPP_1 VTT DDRA_SA1

0.1U_6.3V_K_X5R_0201
1 1 259 260
VPP_2 SA1

CD1804

CD1805
+3VS RD1804 1 @ 2 0_5%_0603 261 262
GND_1 GND_2
ARGOS_D4AR0-26001-1P40 2 2
ME@ ARGOS_D4AR0-26001-1P40
ME@

+2.5V_DDR RD1805 1 @ 2 0_5%_0603 +VPP VDDSPD:

+1.2V 1x2.2uF
0.1U_6.3V_K_X5R_0201

ch
1x0.1uF
1
CD1806

RD1806
2 1K_0402_1%
B B
+2.5V_DDR
2

RD1807 1 2 2_0402_5% +VREF_CA_DIMM +1.2V 2nd DRAM 1x10uF 4x1uF

ni
5 DDR_SA_VREFCA
VPP:

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201
0.1U_6.3V_K_X5R_0201

1 1x1uF
1

CD1812

CD1811

CD1814

CD1813
CD1815 1 1x10uF

0.1U_6.3V_K_X5R_0201
CD1816

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

0.1U_6.3V_K_X5R_0201
0.022U_16V_K_X7R_0402 RD1808 VDDQ: 1 1 1 1

CD1836
CD1818

CD1819

CD1820

CD1822

CD1823

CD1824

CD1817

CD1821

CD1833

CD1834

CD1835

CD1837
33P_0402_50V8J

CD1838
33P_0402_50V8J
1K_0402_1% 8x1uF
2
8x10uF 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1

2
2

RD1809 2 2@ 2 2@

ca
24.9_0402_1%
2@ 2@ 2 2 2 2@ 2 2 2 2@ 2 2 2 2
@ @ @ @ @ @
2

+3VS +3VS +3VS

l
1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201
1

CD1825

CD1826

CD1828

CD1829

CD1830

CD1832

CD1831

RD1810 RD1811 RD1812 CD1827 +0.6VS

1 1 1 1 1 1 1 1
0_0402_5% 0_0402_5% 0_0402_5%
@ @ @
VTT:
2

2@ 2 2 2 2 2 2 2

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201
DDRA_SA0 DDRA_SA1 DDRA_SA2 2x1uF

CD1809

CD1810

CD1807

CD1808
@ @
1x10uF
1 1 1 1
1

RD1813 RD1814 RD1815

0_0402_5% 0_0402_5% 0_0402_5% 2 2 2 2@
@ @
A @ @ @ A
2

SPD Address = A0
Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 DDR4 SO-DIMM

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday, December 06, 2019 Sheet 18 of 60
5 4 3 2 1
 5 4 3 2 1

+3.3V_1.8V_AON +3V_1.8VGS +3.3V_1.8V_AON

2
RV2001 RV2002 RV2003
0_0402_5% 10K_0402_5%
0_0402_5% +1.0VGS
@ OPT@
@
UV1A ? COMMON INS35853665

1
1/14 PCI_EXPRESS
CV2003 1 Under Near GPU and PS
D D
0.1U_6.3V_K_X5R_0201

CV2008
10U 6.3V M X5R 0402

CV2009 OPTN17@
10U 6.3V M X5R 0402
@

OPTN17@
CV2004 OPT@
1U_6.3V_M_X5R_0201

CV2005 OPTN17@
4.7U_0402_6.3V6M

CV2006 OPT@
4.7U_0402_6.3V6M

CV2007 OPTN17@
4.7U_0402_6.3V6M
2

22U_0603_6.3V6-M
2 2

2
AA22 1 1 1 1 PEX_DVDD
PLT_RST_VGA# AC7 PEX_DVDD_1 AB23
26 PLT_RST_VGA# PEX_DVDD_2 1 N16:+1.05VGS(recommend)
OPT@ QV2001 AC24
CLK_REQ_GPU# PEX_RST_N PEX_DVDD_3 1 1 +1.0VGS(Used)

OPTN17@
10 GPU_CLKREQ#
1 3 AC6 AD25
PEX_CLKREQ_N PEX_DVDD_4 2 2 2 2 N17:+1.0VGS

CV2010
AE26
CLK_PCIE_GPU AE8 PEX_DVDD_5 AE27 2
10 CLK_PCIE_GPU CLK_PCIE_GPU# AD8 PEX_REFCLK PEX_DVDD_6
LSI1012XT1G_SC-89-3
10 CLK_PCIE_GPU# PEX_REFCLK_N
RV2004 1 @ 2 0_0402_5% PCIE_CRX_GTX_P5 OPT@ CV2001 1 2 0.22U_0201_6.3V6-K PCIE_CRX_C_GTX_P5 AC9 PEX_HVDD +3V_1.8VGS
PCIE_CRX_GTX_N5 OPT@ CV2011 1 2 0.22U_0201_6.3V6-K PCIE_CRX_C_GTX_N5 AB9 PEX_TX0
PEX_TX0_N
2000mA

2
PCIE_CTX_C_GRX_P5 AG6 Under GPU Near GPU GPU and PS OPTN17@
RV2005 PCIE_CTX_C_GRX_N5 PEX_RX0 (below 150mils) PEX_HVDD
AG7 AA10 2 1 0_0805_5%
10K_0402_5% PEX_RX0_N PEX_HVDD_1 AA12
@ PCIE_CRX_GTX_P6 PEX_HVDD_2 RV2006
2 0.22U_0201_6.3V6-K PCIE_CRX_C_GTX_P6 +1.0VGS

CV2014 OPT@
1U_6.3V_M_X5R_0201

CV2015 OPTN17@
1U_6.3V_M_X5R_0201

CV2016
1U_6.3V_M_X5R_0201

CV2017
1U_6.3V_M_X5R_0201

CV2018 OPT@
4.7U_0402_6.3V6M

CV2019 OPTN17@
4.7U_0402_6.3V6M

CV2020 OPT@
10U 6.3V M X5R 0402

CV2021 OPTN17@
10U 6.3V M X5R 0402

CV2022 OPT@
22U_0603_6.3V6-M

CV2023 OPT_RF@
33P_0402_50V8J
OPT@ CV2012 1 AB10 AA13
PCIE_CRX_GTX_N6 OPT@ CV2013 1 2 0.22U_0201_6.3V6-K PCIE_CRX_C_GTX_N6 AC10 PEX_TX1 PEX_HVDD_3 AA16 OPTN16@
1 PEX_TX1_N PEX_HVDD_4 AA18
1 1 1 1 1 1 2 2 1 1
2 1 0_0805_5%
PCIE_CTX_C_GRX_P6 AF7 PEX_HVDD_5 AA19
PCIE_CTX_C_GRX_N6 PEX_RX1 PEX_HVDD_6 RV2007

El
AE7 AA20
PEX_RX1_N PEX_HVDD_7 AA21 2 2 2 2 2 2 1 1 2 2
PCIE_CRX_GTX_P7 OPT@ CV2002 1 2 0.22U_0201_6.3V6-K PCIE_CRX_C_GTX_P7 AD11 PEX_HVDD_8 AB22 @ @ PEX_HVDD
PCIE_CRX_GTX_N7 OPT@ CV2024 1 2 0.22U_0201_6.3V6-K PCIE_CRX_C_GTX_N7 AC11 PEX_TX2 PEX_HVDD_9 AC23 N16:+1.05VGS(recommend)
PEX_TX2_N PEX_HVDD_10 AD24 +1.0VGS(Used)
PCIE_CTX_C_GRX_P7 AE9 PEX_HVDD_11 AE25
PCIE_CTX_C_GRX_N7 PEX_RX2 PEX_HVDD_12 N17:+1.8VGS
AF9 AF26
PEX_RX2_N PEX_HVDD_13 AF27 For RF
PCIE_CRX_GTX_P8 OPT@ CV2025 1 2 0.22U_0201_6.3V6-K PCIE_CRX_C_GTX_P8 AC12 PEX_HVDD_14
PEX_TX3

et
PCIE_CRX_GTX_N8 OPT@ CV2026 1 2 0.22U_0201_6.3V6-K PCIE_CRX_C_GTX_N8 AB12
PEX_TX3_N Change by Bourne 20170412
PCIE_CTX_C_GRX_P8 AG9
PCIE_CTX_C_GRX_N8 AG10 PEX_RX3
PEX_RX3_N
AB13
AC13 PEX_TX4
C
PEX_TX4_N C
+3.3V_1.8V_AON

ro
9 PCIE_CRX_GTX_N[5..8]
AF10
AE10 PEX_RX4
PEX_RX4_N
9 PCIE_CRX_GTX_P[5..8]
AD14 OPTN16@
AC14 PEX_TX5 AA8 PEX_PLL_HVDD RV2008 1 2 0_0402_5% PEX_PLL_HVDD
9 PCIE_CTX_C_GRX_N[5..8] PEX_TX5_N PEX_PLL_HVDD_1
PEX_PLL_HVDD_2
AA9 +3V_1.8VGS N16:+3.3V_AON
AE12

0.1U_6.3V_K_X5R_0201
9 PCIE_CTX_C_GRX_P[5..8] AF12 PEX_RX5
1 OPTN17@ N17:+1.8VGS
PEX_RX5_N

CV2027
RV2009 1 2 0_0402_5%

OPT@
-X
AC15
AB15 PEX_TX6
PEX_TX6_N 2 Change by Bourne 20170412
AG12
AG13 PEX_RX6
PEX_RX6_N

https://vinafix.com
AB16
AC16 PEX_TX7
PEX_TX7_N PEX_DVDD/Q Decouling
Under GPU
AF13
(below 150mils)

Te
AE13 PEX_RX7
PEX_RX7_N
AD17 MLCC N16 N17 location
AC17 PEX_TX8
PEX_TX8_N
AE15
1.0uF 1 1
AF15 PEX_RX8 Under
PEX_RX8_N 4.7uF 0 1
AC18
AB18 PEX_TX9
4.7uF 1 2 Near
PEX_TX9_N
AG15

ch
AG16 PEX_RX9 10uF 0 2 Midway
PEX_RX9_N

PEX LANES 15 - 4 ARE DEFEATURED

AB19
AC19 PEX_TX10
22uF 0 1
PEX_TX10_N
AF16
B
AE16 PEX_RX10 B
PEX_RX10_N PEX_HVDD/Q Decouling
AD20
AC20 PEX_TX11

ni
PEX_TX11_N
AE18
MLCC N16 N17 location
AF18 PEX_RX11
PEX_RX11_N 1.0uF 1 4 Under
AC21
AB21 PEX_TX12
4.7uF 1 2 Near
PEX_TX12_N
AG18

ca
AG19 PEX_RX12 10uF 1 2 Midway
PEX_RX12_N
AD23
AE23 PEX_TX13
22uF 1 1
PEX_TX13_N
AF19
AE19 PEX_RX13
PEX_RX13_N
AF24
AE24 PEX_TX14
PEX_TX14_N

l
AE21
AF21 PEX_RX14
PEX_RX14_N PEX_PLL_HVDD/Q Decouling
AG24
AG25 PEX_TX15
PEX_TX15_N
MLCC N16 N17 location
AG21
AG22 PEX_RX15
PEX_RX15_N 0.1uF 1 1 Near
AF25 PEX_TERMP 2.49K_0402_1% 2 OPT@ 1 RV2010
PEX_TERMP

N17S-G1-A1_GB2C-64-595 @
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 GPU_PCIE Interface

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday, December 06, 2019 Sheet 20 of 60
5 4 3 2 1
 5 4 3 2 1

UV1B ? COMMON INS35854731

2/14 FBA
FBA_D0 E18
FBA_D1 F18 FBA_D0
FBA_D2 E16 FBA_D1
27,28 FBA_D[0..63] FBA_D3 FBA_D2
F17
FBA_D4 D20 FBA_D3
27,28 FBA_CMD[31..0] FBA_D5 D21 FBA_D4
FBA_D6 F20 FBA_D5
27,28 FBA_EDC[7..0] FBA_D7 FBA_D6
E21
FBA_D8 E15 FBA_D7
27,28 FBA_DBI[7..0] FBA_D9 FBA_D8
D15
D FBA_D10 F15 FBA_D9 D
FBA_D11 F13 FBA_D10
FBA_D12 C13 FBA_D11
FBA_D13 B13 FBA_D12
FBA_D14 E13 FBA_D13
FBA_D15 D13 FBA_D14
FBA_D16 B15 FBA_D15
FBA_D17 C16 FBA_D16
FBA_D18 A13 FBA_D17
FBA_D19 A15 FBA_D18
FBA_D20 B18 FBA_D19
FBA_D21 A18 FBA_D20
FBA_D22 A19 FBA_D21
FBA_D23 C19 FBA_D22
FBA_D24 B24 FBA_D23 +1.35VGS
FBA_D25 C23 FBA_D24
FBA_D26 A25 FBA_D25
FBA_D27 A24 FBA_D26
FBA_D28 A21 FBA_D27
FBA_D29 B21 FBA_D28

1
FBA_D30 C20 FBA_D29
FBA_D31 FBA_D30 RV2101 RV2102
C21

El
FBA_D32 R22 FBA_D31 10K_0402_1% 10K_0402_1%
FBA_D33 FBA_D32 FBA_CMD0 OPT@ OPT@
R24 C27
FBA_D34 T22 FBA_D33 FBA_CMD0 C26 FBA_CMD1

2
FBA_D35 R23 FBA_D34 FBA_CMD1 E24 FBA_CMD2
FBA_D36 N25 FBA_D35 FBA_CMD2 F24 FBA_CMD3 FBA_CMD14
FBA_D37 N26 FBA_D36 FBA_CMD3 D27 FBA_CMD4
FBA_D38 N23 FBA_D37 FBA_CMD4 D26 FBA_CMD5 FBA_CMD30
FBA_D39 N24 FBA_D38 FBA_CMD5 F25 FBA_CMD6
FBA_D40 V23 FBA_D39 FBA_CMD6 F26 FBA_CMD7

et
FBA_D41 V22 FBA_D40 FBA_CMD7 F23 FBA_CMD8
FBA_D42 T23 FBA_D41 FBA_CMD8 G22 FBA_CMD9 FBA_CMD13
FBA_D43 U22 FBA_D42 FBA_CMD9 G23 FBA_CMD10
FBA_D44 Y24 FBA_D43 FBA_CMD10 G24 FBA_CMD11 FBA_CMD29
FBA_D45 AA24 FBA_D44 FBA_CMD11 F27 FBA_CMD12
FBA_D46 Y22 FBA_D45 FBA_CMD12 G25 FBA_CMD13
FBA_D47 AA23 FBA_D46 FBA_CMD13 G27 FBA_CMD14

1
C FBA_D48 AD27 FBA_D47 FBA_CMD14 G26 FBA_CMD15 C

ro
FBA_D49 FBA_D48 FBA_CMD15 FBA_CMD16 RV2103 RV2104
AB25 M24
FBA_D50 AD26 FBA_D49 FBA_CMD16 M23 FBA_CMD17 10K_0402_1% 10K_0402_1%
FBA_D51 FBA_D50 FBA_CMD17 FBA_CMD18 OPT@ OPT@
AC25 K24
FBA_D52 AA27 FBA_D51 FBA_CMD18 K23 FBA_CMD19

2
FBA_D53 AA26 FBA_D52 FBA_CMD19 M27 FBA_CMD20
FBA_D54 W26 FBA_D53 FBA_CMD20 M26 FBA_CMD21
FBA_D55 Y25 FBA_D54 FBA_CMD21 M25 FBA_CMD22
FBA_D56 R26 FBA_D55 FBA_CMD22 K26 FBA_CMD23
FBA_D57 T25 FBA_D56 FBA_CMD23 K22 FBA_CMD24

-X
FBA_D58 N27 FBA_D57 FBA_CMD24 J23 FBA_CMD25
FBA_D59 R27 FBA_D58 FBA_CMD25 J25 FBA_CMD26
FBA_D60 V26 FBA_D59 FBA_CMD26 J24 FBA_CMD27
FBA_D61 V27 FBA_D60 FBA_CMD27 K27 FBA_CMD28
FBA_D62 W27 FBA_D61 FBA_CMD28 K25 FBA_CMD29

https://vinafix.com
FBA_D63 W25 FBA_D62 FBA_CMD29 J27 FBA_CMD30 +1.35VGS
FBA_D63 FBA_CMD30 J26 FBA_CMD31
FBA_CMD31 B19
FBA_DBI0 D19 FBA_CMD32 F22 RV2105 2 @ 1 60.4_0402_1%
FBA_DBI1 D14 FBA_DQM0 FBA_CMD34 J22 RV2106 2 @ 1 60.4_0402_1%

Te
FBA_DBI2 C17 FBA_DQM1 FBA_CMD35
FBA_DBI3 C22 FBA_DQM2
FBA_DBI4 P24 FBA_DQM3
FBA_DBI5 W24 FBA_DQM4
FBA_DBI6 AA25 FBA_DQM5
FBA_DBI7 U25 FBA_DQM6
FBA_DQM7

FBA_EDC0 E19
FBA_EDC1 C15 FBA_DQS_WP0
FBA_EDC2 B16 FBA_DQS_WP1 D24 FBA_CLK0
FBA_CLK0 27

ch
FBA_EDC3 B22 FBA_DQS_WP2 FBA_CLK0 D25 FBA_CLK0#
FBA_EDC4 R25 FBA_DQS_WP3 FBA_CLK0_N N22 FBA_CLK1 FBA_CLK0# 27
FBA_EDC5 W23 FBA_DQS_WP4 FBA_CLK1 M22 FBA_CLK1# FBA_CLK1 28
FBA_EDC6 AB26 FBA_DQS_WP5 FBA_CLK1_N FBA_CLK1# 28
FBA_EDC7 T26 FBA_DQS_WP6
FBA_DQS_WP7
B B
F19 D18 FBA_WCLK01
FBA_DQS_RN0 FBA_WCK01 FBA_WCLK01# FBA_WCLK01 27
C14 C18
FBA_DQS_RN1 FBA_WCK01_N FBA_WCLK23 FBA_WCLK01# 27
A16 D17
FBA_DQS_RN2 FBA_WCK23 FBA_WCLK23# FBA_WCLK23 27
A22 D16

ni
FBA_DQS_RN3 FBA_WCK23_N FBA_WCLK45 FBA_WCLK23# 27
P25 T24
W22 FBA_DQS_RN4 FBA_WCK45 U24 FBA_WCLK45# FBA_WCLK45 28
AB27 FBA_DQS_RN5 FBA_WCK45_N V24 FBA_WCLK67 FBA_WCLK45# 28 PEX_HVDD
FBA_DQS_RN6 FBA_WCK67 FBA_WCLK67# FBA_WCLK67 28
T27 V25 +FB_PLLAVDD Place close to BGA
FBA_DQS_RN7 FBA_WCK67_N FBA_WCLK67# 28 200mA
Near GPU LV2101 PEX_HVDD
Under GPU

ca
F16 2 1 N16:+1.05VGS(recommend)
FB_PLL_AVDD_1 +1.0VGS(Used)

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201
SBK160808T-300Y-N
P22 +FB_PLLAVDD N17:+1.8VGS

CV2101 OPT@

CV2102 OPT@

CV2103 OPTN17@

CV2104 OPTN17@

CV2105 OPT@
22U_0603_6.3V6-M
FB_PLL_AVDD_2 OPT@
Place close to ball 1
H22 1 1 1 1
FB_REFPLL_AVDD 30ohms (ESR=0.01) 0603 Bead
0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

2
CV2106 OPT@

CV2107 OPTN17@

CV2108 OPTN17@

2 2 2 2
1 1 1

l
2 2 2
D23
FB_VREF

N17S-G1-A1_GB2C-64-595 @

N17S Add 2x0.1u

FB_PLL/Q Decouling

MLCC N16 N17 location

A A

0.1uF 2 4 Under

22uF 1 1 Near

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 GPU_MEM Interface

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday, December 06, 2019 Sheet 21 of 60
5 4 3 2 1
 5 4 3 2 1

+VGA_CORE
+VGA_CORE
Under GPU 12x4.7uF 5x1uF
+VGA_CORE CV2201 CV2202 CV2203 CV2204 CV2205 CV2206 CV2207 CV2208 CV2209 CV2210 CV2211 CV2212 CV2213 CV2214 CV2215 CV2216 CV2217 CV2218
UV1C ? COMMON INS37185662
UV1G ? COMMON INS35856873

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

33P_0402_50V8J
11/14 NVVDD

OPTN17@
6/14 XVDD
K10 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

OPTNS@

OPTN17@

OPTNS@

OPTNS@

OPTN17@
VDD_001

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
K12

OPT@

OPT_RF@
K14 VDD_002
G1 N4 VDD_003
XVDD_1 XVDD_36 K16
G2 N5 VDD_004 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
XVDD_2 XVDD_37 K18
G3 N7 VDD_005
XVDD_3 XVDD_38 L13
G4 P3 VDD_006
XVDD_4 XVDD_39 L15
D G5 P4 VDD_007 D
XVDD_5 XVDD_40 M10
G6 P6 VDD_008
XVDD_6 XVDD_41 M12
G7 R1 VDD_009
XVDD_7 XVDD_42 M16
H3 R2 VDD_010
XVDD_8 XVDD_43 M18
H4 R3 VDD_011
XVDD_9 XVDD_44 N11
H6 R4 VDD_012
XVDD_10 XVDD_45 N13
J1 R5 VDD_013 Near GPU 4x4.7uF 11x10uF 4x22uF
XVDD_11 XVDD_46 N15
J2 R6 VDD_014
XVDD_12 XVDD_47 N17
J3 R7 VDD_015 CV2219CV2220 CV2221 CV2222 CV2223 CV2224 CV2225 CV2226 CV2227 CV2228 CV2229 CV2230 CV2231 CV2232 CV2233 CV2234 CV2235 CV2236 CV2237 CV2238 CV2239 CV2240
XVDD_13 XVDD_48 P14
J4 T1 VDD_016
XVDD_14 XVDD_49 R11
J5 T2 VDD_017

22U_0603_6.3V6-M

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

XVDD_15 XVDD_50 R13

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

33P_0402_50V8J
J6 T3 VDD_018

OPTN17_NS@

OPTN17_NS@

OPTN17_NS@
XVDD_16 XVDD_51 R15

OPTN17_NS@

OPTN17@

OPTN17@

RF_NS@
J7 T4 VDD_019

OPTNS@

OPTNS@

OPTN17@

OPTN17@

OPTN17@

OPTN17@

OPTN17@

OPTN17@

OPTNS@

OPTN17@

OPTNS@

OPTNS@
XVDD_17 XVDD_52 R17 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2

OPT@

OPT@

OPT@
K1 T5 VDD_020
XVDD_18 XVDD_53 T10
K2 T6 VDD_021
XVDD_19 XVDD_54 T12
K3 T7 VDD_022
XVDD_20 XVDD_55 T16 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1
K4 U3 VDD_023
XVDD_21 XVDD_56 T18
K5 U4 VDD_024
XVDD_22 XVDD_57 U13
K6 U6 VDD_025
XVDD_23 XVDD_58 U15
K7 V1 VDD_026
XVDD_24 XVDD_59 +VGA_CORE V10
L3 V2 VDD_027
XVDD_25 XVDD_60 V12 CV88 Use virtual Symbol for diff value
L4 V3 VDD_028

El
XVDD_26 XVDD_61 V14
M1 V4 VDD_029
XVDD_27 XVDD_62 V16
M2 V5 RV2201 1 @ 2 0_0402_5% VDD_030
XVDD_28 XVDD_63 V18
M3 V6 RV2202 1 2 0_0402_5% VDD_031
M4 XVDD_29 XVDD_64 V7 @ NVVDD/Q Decouling
M5 XVDD_30 XVDD_65 W1
M7 XVDD_31 XVDD_66 W2
XVDD_32 XVDD_67 F2 NVVDD_VCC_SENSE MLCC N16 N17 location
N1 W3 VDD_SENSE NVVDD_VSS_SENSE NVVDD_VCC_SENSE 58
XVDD_33 XVDD_68 F1 NVVDD_VSS_SENSE 58
N2 W4 GND_SENSE
N3 XVDD_34 XVDD_69

et
XVDD_35 4.7uF 10 12
trace width: 16mils Under
differential voltage sensing.
differential signal routing. 1.0uF 4 5

N17S-G1-A1_GB2C-64-595
N17S-G1-A1_GB2C-64-595 47uF 1 0
C C

@
@

ro
10uF 0 11
Near
22uF 1 4
4.7uF 5 4

-X
330uF 1 2
+1.35VGS

https://vinafix.com
UV1D ? COMMON INS35857178
12/14 FBVDDQ

B26 +1.35VGS

Te
C25 FBVDDQ_01
E23 FBVDDQ_02 +VGA_CORE
FBVDDQ_03 1x10uF 3x22uF
E26
F14 FBVDDQ_04 Under GPU(below 150mils) 8x10uF 2x10uF Near GPU UV1F ? COMMON INS35856561
F21 FBVDDQ_05 CV2247 CV2241 CV2242 CV2243 CV2244 CV2248 CV2245 CV2249 CV2250 CV2251 CV2252 CV2253 CV2254 CV2246 7/14 VDDS
G13 FBVDDQ_06
FBVDDQ_07
0.1U_6.3V_K_X5R_0201

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

10U 6.3V M X5R 0402

G14
FBVDDQ_08
10U 6.3V M X5R 0402

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

OPTN17_NS@
G15 L11

OPTN17@
FBVDDQ_09 1 1 1 2 VDDS_1
OPTN17@

OPTN17@

OPTN17@
G16 1 2 1 1 1 1 1 1 1 1 L17
OPTNS@

OPTN17@

OPTN17@

OPTN17@

OPT@

OPT@
FBVDDQ_10 VDDS_2
OPTNS@

OPT@

G18 M14
OPT@

G19 FBVDDQ_11 P10 VDDS_3

G20 FBVDDQ_12 P12 VDDS_4

ch
FBVDDQ_13 2 2 2 1 VDDS_5
G21 2 1 2 2 2 2 2 2 2 2 P16
L22 FBVDDQ_14 P18 VDDS_6
L24 FBVDDQ_19 T14 VDDS_7
L26 FBVDDQ_20 U11 VDDS_8
M21 FBVDDQ_21 U17 VDDS_9
N21 FBVDDQ_22 VDDS_10
B
R21 FBVDDQ_23 B
FBVDDQ_24 CV32 CV686 Use virtual Symbol for diff value
T21
V21 FBVDDQ_25
W21 FBVDDQ_26
FBVDD/Q Decouling

ni
H24 FBVDDQ_27
H26 FBVDDQ_15
J21 FBVDDQ_16 F4 1 TV2201 @
K21 FBVDDQ_17 MLCC N16 N17 location VDDS_SENSE F3 FB_CLAMP RV2203 1 OPTN16@2 10K_0402_5%
FBVDDQ_18 GNDS_SENSE

0.1uF 2 0 N17S-G1-A1_GB2C-64-595

@
ca
1.0uF 2 8
Under
4.7uF 2 0
10uF 0 2
10uF 1 1

l
Near
22uF 1 3
+1.35VGS

FB_CAL_PD_VDDQ
D22 RV2204 1 OPT@ 2 40.2_0402_1% CALIBRATION PIN GDDR5

FB_CAL_PU_GND
C24 RV2205 1 OPT@ 2 40.2_0402_1% FB_CAL_x_PD_VDDQ 40.2Ohm
A A

FB_CAL_TERM_GND
B25 RV2206 1 OPT@ 2 60.4_0402_1% FB_CAL_x_PU_GND 40.2Ohm
Place near balls
FB_CAL_xTERM_GND 60.4Ohm

Security Classification LC Future Center Secret Data Title

N17S-G1-A1_GB2C-64-595 Issued Date 2015/08/20 Deciphered Date 2016/08/20 GPU_+VGA_CORE,FBVDDQ
@

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday, December 06, 2019 Sheet 22 of 60
5 4 3 2 1
 5 4 3 2 1

N16 3V3_MAIN(N17 VDD_18) Decouling Discharge

+3V_1.8VGS
+5VALW +1.35VGS
Under GPU Near GPU MLCC N16 N17 location
@
UV1E ? COMMON INS35858730 +VDD18 RV2301 1 2 0_0402_5%

1
14/14 VDD18
0.1uF 2 2

CV2301
0.1U_6.3V_K_X5R_0201

CV2302
0.1U_6.3V_K_X5R_0201

CV2303
1U_6.3V_M_X5R_0201

CV2304
4.7U_0402_6.3V6M
Under RV2302
G8 RV2303
VDD18_1 1 1 1 1 47K_0402_5% 470_0603_5%
G9
VDD18_2 G10 1.0uF 1 1 OPTNS@ OPTNS@
1V8_AON_1 G12

3 2
1V8_AON_2 2 2 2 2
Near

OPT@

OPT@

OPT@

OPT@
D
4.7uF 1 1 FBVDDQ_PWR_EN# 5 QV2301B
G LBSS138DW1T1G_SOT363-6

6
D
S

4
D FBVDDQ_PWR_EN 2 OPTNS@ D
QV2301A
G
+3.3V_1.8V_AON S LBSS138DW1T1G_SOT363-6

1
N16 3V3_AON(N17 1V8_AON) Decouling OPTNS@
Under GPU Near GPU
VDD_AON RV2304 1 @ 2 0_0402_5%
MLCC N16 N17 location

CV2305
0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

1U_6.3V_M_X5R_0201
CV2306 OPTN17@

CV2307 OPT@

CV2308 OPT@
4.7U_0402_6.3V6M
N17S-G1-A1_GB2C-64-595 1 1 1 1 0.1uF 1 2 Under +5VALW +3.3V_1.8V_AON
@

2
OPT@
1.0uF 1 1

1
2 2 2 2 RV2305
Near RV2306
47K_0402_5%
470_0603_5%
4.7uF 1 1 OPTNS@ OPTNS@

3 2
D
PXS_PWREN# 5 QV2302B
G

El
2N7002KDWH_SOT363-6

6
D
PXS_PWREN 2 QV2302A S OPTNS@
PXE_VDD & 1V8_AON

4
G +3V_1.8VGS
2N7002KDWH_SOT363-6
S OPTNS@

1
PXS_PWREN RV2307 1 @ 2 0_0402_5% PXS_PWR_EN_R

1
8 PXS_PWREN PXS_PWR_EN_R 57 1
RV2308 CV2309
470_0603_5% 10U 6.3V M X5R 0402

et
RV2309 OPTNS@ GC6@
2
100K_0402_5%

2
@

1
2

D
2 OPTNS@
G
C QV2303 C

ro
+3VS S L2N7002KWT1G_SOT323-3
DV2301 @

3
+3.3V_1.8V_AON
DGPU_PWROK 1 2
2

1 2
RB521CM-30T2R_VMN2M-2 RV2310 RV2311
10K_0402_5% 10K_0402_5%
@ OPT@ RV2316 建虚拟料号,N16=470 ohm,N17=5.11 ohm

-X
1

DV2302 +5VALW +1.0VGS

PXS_PWREN 2 RV2313
RV2312 1 PXE_VDD_EN 2 1 PXE_VDD_EN_R RV109 change to 470ohm 0805 for N16 GPU
1.8VGS_PWR_EN PXE_VDD_EN_R 57
1 2 3
30K_0402_5%

https://vinafix.com
OPT@
1

0_0402_5% LBAT54AWT1G_SOT323-3 2

1
@ OPT@ RV2314

1
OPT@ CV2310
10K_0402_5% D2301 RV2317
0.22U_0402_10V6K RV2315 RV2316 470_0805_5%
@ 1 47K_0402_5% 5.11_0805_1%

Te
1 2 OPT@
2

OPT@ OPTN17@ @

2
1 2

2
RB521CM-30T2R_VMN2M-2

+1.8VG_AON TO +1.8VGS

1
D
+1.0VGS_PWR_EN# 2 QV2304
G

Vinafix.com
AO3402_SOT-23-3

ch
OPTN17@

S
+3VS

3
1
D
1

PXE_VDD_EN_R 2 QV2305
RV2318 G LBSS139WT1G_SC70-3
B B
82K_0402_1% OPT@ S

1
@ D
@ 2 QV2306
DV2303
2

PXS_PWREN G LBSS139WT1G_SC70-3
RV2321 1 2 0_0402_5% 2

ni
@
NVVDD_EN OPTN16@ S
1

3
1.8VGS_PWR_EN NVVDD_EN 58
RV2323 1 @ 2 0_0402_5% 3
26,57 1.8VGS_PWR_EN
RV2324 1 @ 2 0_0402_5% LBAT54AWT1G_SOT323-3
1

+3V_1.8VGS
RV2325
RV2326 1 @ 2 0_0402_5% 100K_0402_1%
@

ca
2

+5VALW +VGA_CORE

1
RV2327
47K_0402_5% RV2328
OPTNS@ 10_0603_5%

l
OPTNS@

3 2
D
NVVDD_EN# 5 QV2309B
DV2304 G LBSS138DW1T1G_SOT363-6

6
FB_GC6_EN_R RV2329 1 @ 2 0_0402_5% GC6_EN 2 D OPTNS@
8,26 FB_GC6_EN_R S

4
1 FBVDDQ_PWR_EN FBVDDQ_PWR_EN 57 NVVDD_EN 2 QV2309A
DGPU_PWROK OPT@
RV2330 1 2 10K_0402_5% 3 G
8,58 DGPU_PWROK LBSS138DW1T1G_SOT363-6
S

1
1

BAV70W-7-F_SOT323-3 OPTNS@
RV2333
GC6@
CV2313 OPT@
0.1U_6.3V_K_X5R_0201

200K_0402_5%
1 GC6@
2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 GPU_AON/MAIN PWR/SEQUENCE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday, December 06, 2019 Sheet 23 of 60
5 4 3 2 1
 5 4 3 2 1

UV1H ? COMMON INS35859464

13/14 GND

D D
A2 K11
AB17 GND_001 GND_057 K13
AB20 GND_005 GND_058 K15
AB24 GND_006 GND_059 K17
AC2 GND_007 GND_060 L10
AC22 GND_008 GND_061 L12
AC26 GND_009 GND_062 L14
AC5 GND_010 GND_063 L16
AC8 GND_011 GND_064 L18
AD12 GND_012 GND_065 L5
AD13 GND_013 GND_069 M11
A26 GND_014 GND_070 M13
AD15 GND_002 GND_071 M15
AD16 GND_015 GND_072 M17
AD18 GND_016 GND_073 N10
AD19 GND_017 GND_074 N12
AD21 GND_018 GND_075 N14
AD22 GND_019 GND_076 N16
AE11 GND_020 GND_077 N18
AE14 GND_021 GND_078 P11
AE17 GND_022 GND_079 P13
GND_023 GND_080

El
AE20 P15
AB11 GND_024 GND_081 P17
AF1 GND_003 GND_082 P23
AF11 GND_025 GND_084 P26
AF14 GND_026 GND_085 R10
AF17 GND_027 GND_087 R12
AF20 GND_028 GND_088 R14
AF23 GND_029 GND_089 R16
AF5 GND_030 GND_090 R18
GND_031 GND_091

et
AF8 T11
AG2 GND_032 GND_092 T13
AG26 GND_033 GND_093 T15
AB14 GND_034 GND_094 T17
B1 GND_004 GND_095 U10
B11 GND_035 GND_096 U12
B14 GND_036 GND_097 U14
C B17 GND_037 GND_098 U16 C
GND_038 GND_099

ro
B20 U18
B23 GND_039 GND_100 U23
B27 GND_040 GND_102 U26
B5 GND_041 GND_103 V11
B8 GND_042 GND_105 V13
E11 GND_043 GND_106 V15
E14 GND_044 GND_107 V17
E17 GND_045 GND_108 Y2
E2 GND_046 GND_109 Y23
GND_047 GND_110

-X
E20 Y26
E22 GND_048 GND_111 Y5
E25 GND_049 GND_112 AA7
E5 GND_050 GND_F AB7
E8 GND_051 GND_H
GND_052

https://vinafix.com

Te
H2 P2
H5 GND_053 GND_083 P5
L2 GND_056 GND_086 U2
GND_066 GND_101 U5
GND_104

ch
H23 L23
H25 GND_054 GND_067 L25
GND_055 GND_068

N17S-G1-A1_GB2C-64-595
@

B B

ni
ca
l
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 GPU_GND

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday, December 06, 2019 Sheet 24 of 60
5 4 3 2 1
 5 4 3 2 1

PEX_PLLVDD/Q Decouling

MLCC N16 N17 location UV1J ? COMMON INS35860124

4/14 IFPAB

1.0uF 1 NA Under DVI HDMI DP

SL/DL

1uF 1 NA AC4
Near TXC/TXC
IFPA_L3_N AC3
IFPA_L3
4.7uF 1 NA AA6
IFPAB_RSET Y3
TXD0/0
UV1I ? COMMON INS35860218 IFPA_L2_N Y4
D +1.0VGS
IFPA_L2 D
5/14 NC
OPTN16@
TXD1/1 AA2
RV2501 2 1 0_0402_5% Under GPU Near GPU +PEX_PLLVDD +PEX_PLLVDD AA14 W7 IFPA_L1_N AA3
AA15 NC_1 IFPAB_PLLVDD IFPA_L1

0.1U_6.3V_K_X5R_0201

1U_6.3V_M_X5R_0201

4.7U_0402_6.3V6M
AB6 NC_2

CV2501 OPTN16@

CV2502 OPTN16@

CV2503 OPTN16@
PEX_SVDD_3V3 AB8 NC_3 AA1
TXD2/2
1 1 1 AD10 NC_4 IFPA_L0_N AB1
AD7 NC_5 IFPA_L0
PEX_PLLVDD 1 @ 2 PEX_TSTCLK_OUT AE22 NC_6
N16:+1.0VGS(recommend) RV2502 200_0402_1% AE3 NC_7 AA5
2 2 2 NC_8 IFPA_AUX_SDA_N
N17:NC AE4 AA4
+3.3V_1.8V_AON AF2 NC_9 IFPA_AUX_SCL
PEX_TSTCLK_OUT# AF22 NC_10
AF3 NC_11 AB4
NC_12 IFPB_L3_N

1
+3.3V_1.8V_AON Differential signal AF4 TXC AB5
RV2503 AG3 NC_13 IFPB_L3
10K_0402_5% D10 NC_14
@ E10 NC_15 W6 AB2
TXD0/3
F10 NC_16 IFP_IOVDD_1 IFPB_L2_N AB3

2
F5 NC_17 Y6 IFPB_L2
MULTI_STRAP_REF0_GND F6 NC_18 IFP_IOVDD_2

El
OPTN16@ NC_19
RV2504 2 1 0_0402_5% PEX_SVDD_3V3 W5 TXD1/4 AD2
NC_20 IFPB_L1_N AD3
4.7U_0402_6.3V6M

4.7U_0402_6.3V6M
IFPB_L1

1
OPTN16@

OPTN16@

1 1 RV2505
40.2K_0402_1% TXD2/5 AD1
OPTN16@ IFPB_L0_N AE1
PEX_SVDD_3V3 N17S-G1-A1_GB2C-64-595 IFPB_L0
CV2504

CV2505

2
N16:+3.3V_AON(recommend) 2 2

@
N17:NC AD5

et
IFPB_AUX_SDA_N AD4
Change by Bourne 20170412 IFPB_AUX_SCL
Change by Bourne 20170412 Near GPU
IFPAB (DEFEATURED 0N GM108)

C
PEX_SVDD/Q Decouling C
N17S-G1-A1_GB2C-64-595

ro
UV1K ? COMMON INS35860067

@
MLCC N16 N17 location 10/14 MISC2

4.7uF 2 NA Near
D12 1
ROM_CS_N TV2501 @
B12 ROM_SI
ROM_SI ROM_SO ROM_SI 29

-X
A12
ROM_SO ROM_SCLK ROM_SO 29
STRAP0 D1 C12
29 STRAP0 STRAP0 ROM_SCLK ROM_SCLK 29
STRAP1 D2
29 STRAP1 STRAP1
STRAP2 E4
29 STRAP2 STRAP2
STRAP3 E3
29 STRAP3 D3 STRAP3
STRAP4

https://vinafix.com
29 STRAP4 STRAP4
STRAP5 C1
29 STRAP5 STRAP5

Te
D11 RV2506 2 @ 1 10K_0402_5%
BUFRST_N

XS_PLLVDD/Q Decouling
MLCC N16 N17 location
PEX_HVDD Under
N16:+1.05VGS(recommend) 0.1uF 1 1
+1.0VGS(Used)

ch
N17:+1.8VGS 22uF 1 0 Near
PEX_HVDD N17S-G1-A1_GB2C-64-595

@
LV2501
1 2 OPT@ LV2502 1 @ 2 0_0402_5% Under GPU XS_PLLVDD
0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

SBK160808T-300Y-N UV1L ? COMMON INS35860348

CV2509
22U_0603_6.3V6-M

B B
CV2508
4.7U_0402_6.3V6M

CV2507 OPT@

CV2506

1 1 9/14 XTAL_PLL
30ohms (ESR=0.05) Bead SP_PLLVDD & VID_PLLVDD/Q Decouling
1 1 XS_PLLVDD L6
SP_PLLVDD M6 XS_PLLVDD +3.3V_1.8V_AON
MLCC N16 N17 location

ni
2 2 GPCPLL_AVDD F11 SP_PLLVDD
OPT@

2 2 VID_PLLVDD GPCPLL_AVDD
OPT@

@ N6
VID_PLLVDD

2
0.1uF 2 2 Under 150mA RV2507
10K_0402_5%
10uF 1 0 @
Near

1
10K_0402_5% 2 OPT@ 1 RV2508 XTALSSIN A10 C10 XTALOUT
47uF 1 0

ca
XTAL_SSIN XTAL_OUTBUFF
Change by Bourne 20170412 Under GPU(below 150mils)
LV2503 1 @ 2 0_0402_5% SP_PLLVDD

1
XTAL_IN C11 B10 XTAL_OUT
XTAL_IN XTAL_OUT RV2509
0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

N17S-G1-A1_GB2C-64-595 10K_0402_5%
CV2510 OPT@

CV2511 OPT@

OPTN17@ OPT@

@
1 1
RV2510 1 2 0_0402_5% VID_PLLVDD

2
2 2 RV2511 1 OPT@ 2 10M_0402_5% XTAL_OUT

l 2
R2501
51_0402_1%
YV2501
OPT@

1
OPTN17@ XTAL_IN 1 4
LV2504 1 2 0_0402_5% GPCPLL_AVDD OSC1 GND2
2 3 XTAL_OUT_R
GND1 OSC2
0.1U_6.3V_K_X5R_0201

12P_0402_50V8-J

12P_0402_50V8-J
1
OPT@
CV2512 OPTN17@

OPT@
GPCPLL_AVDD/Q Decouling 1
27MHZ_10PF_7V27000050
1
OPT@
2
CV2513

CV2514
A MLCC N16 N17 location 2 2 A

0.1uF NA 1 Under

4.7uF NA 1
Near
22uF NA 1
Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 GPU_STRAP/DP/HDMI

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday, December 06, 2019 Sheet 25 of 60
5 4 3 2 1
 5 4 3 2 1

UV1M ? COMMON INS35861009

8/14 MISC1
+3.3V_1.8V_AON +3.3V_1.8V_AON

GPU Address 0x9E

3
4
D9 VGA_SMB_CLK
I2CS_SCL Internal Thermal Sensor RPV4
D8 VGA_SMB_DATA

2
A6 I2CS_SDA 2.2K_0404_4P2R_5%
OVERT# QV2601A
OVERT A9 I2CC_SCL OPT@

G1
AE2 PJT7838_SOT363-6
TS_VREF I2CC_SCL B9 I2CC_SDA OPT@

2
1
VGA_SMB_CLK 1 6
I2CC_SDA EC_SMB_CK0 39,44
S1 D1

0.1U_6.3V_K_X5R_0201
CV2601
D 1 E12 D
THERMDN C9 I2CB_SCL
F12 I2CB_SCL C8 I2CB_SDA

5
THERMDP I2CB_SDA
2 QV2601B

G2
@ PJT7838_SOT363-6
VGA_SMB_DATA 4 3 OPT@
S2 D2 EC_SMB_DA0 39,44

C6 NVVDD_PWM_VID
GPIO0 B2 FB_GC6_EN NVVDD_PWM_VID 58 PU AT EC SIDE, +3VS AND 4.7K
GPIO1 D6 GPU_EVENT#_R
GPIO2 C7 NVVDDS_PWM 1
GPIO3 1.8VGS_PWR_EN_R TV2601
PLT_RST_VGA# @ F9
RV2605 1 2 56_0402_5% GPIO4 A3
1 GPIO5 A4 PSI_VGA
CV2602 GPIO6 B6 PSI_VGA 58
220P_0201_25V7-K GPIO7 E9 MEM_VDD_CTL
@ GPIO8 VGA_ALERT#
2 F8
2

GPIO9 C5 GPIO10_FBVREF_ALTV +3.3V_1.8V_AON +3VALW +3VS

GPIO10 E7 GPIO10_FBVREF_ALTV 27
GPIO11 D7 VGA_AC_DET_R 2 1
VGA_AC_DET 44

2
El
OVERT# 3 1 GPIO12 DV2601 OPT@ RV2606
WRST# 44 B4
GPIO13 RB751V-40_SOD323-2 10K_0402_5%
B3
GPIO14 GC6N17@

2
1 C3 RV2609
CV2603 GPIO15 D5 SYS_PEX_RST_MON#_GPU 2 0_0402_5% SYS_PEX_RST_MON#
QV2602 RV2607 1 RV2608 10K_0402_5%
0.01U_0201_10V6K GPIO16 FB_GC6_EN_R
D4 OPTN16@ 10K_0402_5% GC6N17@

1
@ LSI1012XT1G_SC-89-3 GPIO17 FB_GC6_EN_R 8,23
2 C2 @
@ GPIO18 F7

1
GPIO19 E6

3
GPIO20 C4 GPU_PEX_RST_HOLD#_GPU GPU_PEX_RST_HOLD# QV2603B
RV2610 1 2 0_0402_5%

et
GPIO21 VGA_CRT_DATA

D2
A7 OPTN16@
GPIO22 VGA_CRT_CLK 5 PJT7838_SOT363-6
B7 G2
GPIO23
GC6N17@

S2
6
N17S-G1-A1_GB2C-64-595
QV2603A

4
@

D1
FB_GC6_EN 2 PJT7838_SOT363-6
C G1 C

ro
@
MEM_VDD_CTL SYS_PEX_RST_MON#

S1
RV2611 1 2 0_0402_5%

2
RV2612 GC6N17@

1
10K_0402_5%
GC6@

1
UV1N ? COMMON INS35861249
3/14 JTAG +3.3V_1.8V_AON GC6N16@

-X
RV2613 1 2 0_0402_5%
2.2K_0404_4P2R_5%
1 AE5 VGA_CRT_DATA 2 3
TV2602 JTAG_TCK VGA_CRT_CLK
1 AE6 1 4
TV2603 JTAG_TDI
1 AF6 @
TV2604 1 AD6 JTAG_TDO RPV1

https://vinafix.com
TV2605 JTAG_TMS 2.2K_0404_4P2R_5%
10K_0402_5% 2 OPT@ 1 RV2614 AG4
10K_0402_5% 2 OPT@ 1 RV2615 TESTMODE AD9 JTAG_TRST_N I2CB_SCL 2 3
NVJTAG_SEL I2CB_SDA 1 4 +3.3V_1.8V_AON +3.3V_1.8V_AON
@ RPV2

Te

0.1U_6.3V_K_X5R_0201
2.2K_0404_4P2R_5%
1

CV2604
2
I2CC_SCL 2 3
I2CC_SDA 1 4 RV2616
10K_0402_5% 2
@
RPV3 GC6@
@

2
MEM_VDD_CTL RV2617 1 @ 2 10K_0402_5%
+3.3V_1.8V_AON

N17S-G1-A1_GB2C-64-595 GPU_EVENT#_R 3 1 GPU_EVENT#

ch
GPU_EVENT# 8
@

1.8VGS_PWR_EN_R RV2618 2 OPT@ 1 1K_0402_1%

GC6@
QV2604
OVERT# RV2619 1 OPT@ 2 10K_0402_5% LSI1012XT1G_SC-89-3
VGA_ALERT# RV2621 1 @ 2 0_0402_5%
RV26201 OPT@ 2 10K_0402_5%
B B
VGA_AC_DET_R RV26221 OPT@ 2 100K_0402_5%
PSI_VGA RV26231 @ 2 10K_0402_5%

ni
GPU_PEX_RST_HOLD# RV26241 OPT@ 2 10K_0402_5% +3VS
+3VS

Vinafix.com

2
RV2625
10K_0402_5%
OPT@

2
RV2626

ca
10K_0402_5%
OPT@ 1.8VGS_PWR_EN

1
+3VS 1.8VGS_PWR_EN 23,57

1
2

3
RV2627 QV2605B

D2
0_0402_5% 5 PJT7838_SOT363-6
+3.3V_1.8V_AON G2
@
0.1U_6.3V_K_X5R_0201

OPT@

S2
+3.3V_1.8V_AON
+1.8VGARST 1

CV2605 OPT@

l
6

4
2

QV2605A

D1
RV2629 1.8VGS_PWR_EN_R 2
G1 PJT7838_SOT363-6
2

2 RV2628 10K_0402_5%
10K_0402_5% OPT@ OPT@

S1
OPTN16@ DV2602
1
5

UV2603 GPU_PEX_RST_HOLD# 2

1
PLT_RST# 1 1
P

11,37,40,44 PLT_RST# PLT_RST_VGA# 20

1

B 4 SYS_PEX_RST_MON# 3
2 Y
8 PXS_RST# A
G

LBAT54AWT1G_SOT323-3
1

MC74VHC1G09DFT2G_SC70-5 OPTN16@
3

OPT@ OPTNS@
RV2630
1

1.8VGS_PWR_EN_R RV2632 1 2 0_0402_5% 1.8VGS_PWR_EN

100K_0402_5% RV2631 1 2 0_0402_5%
RV2633
OPT@
A 100K_0402_5% OPTN17@ A
2

OPT@
2

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 GPU_GPIO/JTAG

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday, December 06, 2019 Sheet 26 of 60
5 4 3 2 1
 5 4 3 2 1

Lower 32 bits
MF=0 No Mirror
21,28 FBA_D[0..63]
+1.35VGS
21,28 FBA_CMD[31..0]
UM2701
21,28 FBA_EDC[7..0]
MF=0 MF=1 MF=1 MF=0 Close to VRAM
21,28 FBA_DBI[7..0]
A4 FBA_D0 CV2703 CV2704 CV2705 CV2701 CV2702 CV2706 CV2707
FBA_EDC0 C2 DQ24 DQ0 A2 FBA_D1

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201
D FBA_EDC1 C13 EDC0 EDC3 DQ25 DQ1 B4 FBA_D2 D
FBA_EDC2 EDC1 EDC2 DQ26 DQ2 FBA_D3 1 1 1 1 1 1 1

OPT_NS@
R13 B2 BYTE0

OPT_NS@

OPT_NS@

OPT_NS@

OPT_NS@

OPT_NS@
FBA_EDC3 EDC2 EDC1 DQ27 DQ3 FBA_D4

OPT@
R2 E4
EDC3 EDC0 DQ28 DQ4 E2 FBA_D5
DQ29 DQ5 F4 FBA_D6
DQ30 DQ6 2 2 2 2 2 2 2
FBA_DBI0 D2 F2 FBA_D7
FBA_DBI1 D13 DBI0# DBI3# DQ31 DQ7 A11 FBA_D8
FBA_DBI2 P13 DBI1# DBI2# DQ16 DQ8 A13 FBA_D9
OPT@ FBA_DBI3 P2 DBI2# DBI1# DQ17 DQ9 B11 FBA_D10
FBA_CLK0 RV2702 1 2 40.2_0402_1% DBI3# DBI0# DQ18 DQ10
21 FBA_CLK0 B13 FBA_D11
FBA_CLK0 DQ19 DQ11 FBA_D12 BYTE1
FBA_CLK0# J12 E11
RV2701 1 OPT@ 2 40.2_0402_1% FBA_CLK0# CK DQ20 DQ12 FBA_D13
21 FBA_CLK0# J11 E13
FBA_CMD14 J3 CK# DQ21 DQ13 F11 FBA_D14 CV2709 CV2710 CV2711 CV2712 CV2713 CV2714 CV2715
1 CKE# DQ22 DQ14 F13 FBA_D15

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201
CV2708 DQ23 DQ15 FBA_D16

1U_6.3V_M_X5R_0201
0.01U_0201_10V6K U11
FBA_CMD2 H11 DQ8 DQ16 U13 FBA_D17 1 1 1 1 1 1 1

OPT_NS@

OPT@

OPT_NS@

OPT_NS@

OPT_NS@

OPT_NS@
OPT@ FBA_CMD4 BA0/A2 BA2/A4 DQ9 DQ17 FBA_D18

OPT_NS@
2 K10 T11
FBA_CMD3 K11 BA1/A5 BA3/A3 DQ10 DQ18 T13 FBA_D19
FBA_CMD1 BA2/A4 BA0/A2 DQ11 DQ19 FBA_D20
BYTE2
H10 N11 2 2 2 2 2 2 2
BA3/A3 BA1/A5 DQ12 DQ20 N13 FBA_D21
DQ13 DQ21 M11 FBA_D22
FBA_CMD6 K4 DQ14 DQ22 M13 FBA_D23

El
FBA_CMD11 H5 A8/A7 A10/A0 DQ15 DQ23 U4 FBA_D24
FBA_CMD10 H4 A9/A1 A11/A6 DQ0 DQ24 U2 FBA_D25
FBA_CMD7 K5 A10/A0 A8/A7 DQ1 DQ25 T4 FBA_D26
FBA_CMD9 J5 A11/A6 A9/A1 DQ2 DQ26 T2 FBA_D27
A12/RFU/NC DQ3 DQ27 N4 FBA_D28
BYTE3 Around VRAM
A5 DQ4 DQ28 N2 FBA_D29
U5 VPP/NC1 DQ5 DQ29 M4 FBA_D30
VPP/NC2 DQ6 DQ30 M2 FBA_D31 CV2716 CV2717 CV2718 CV2719 CV2720 CV2721 CV2722
DQ7 DQ31

et
+1.35VGS

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
RV27031 OPT@ 2 1K_1%_0201 J1
RV27041 OPT@ 2 1K_1%_0201 FBA_SEN0 J10 MF 1 1
SEN 1 1 1 1 1

OPT@

OPT@

OPT@

OPT@

OPT@
RV2705 1 2 121_0402_1% OPT@ J13 B1
ZQ VDDQ1

OPT_NS@

OPT_NS@
D1
VDDQ2 F1
FBA_CMD8 VDDQ3 2 2
J4 M1 2 2 2 2 2
FBA_CMD12 G3 ABI# VDDQ4 P1
C FBA_CMD0 G12 RAS# CAS# VDDQ5 T1
C

ro
FBA_CMD15 L3 CS# WE# VDDQ6 G2
FBA_CMD5 L12 CAS# RAS# VDDQ7 L2
WE# CS# VDDQ8 B3
VDDQ9 D3
VDDQ10 F3
FBA_WCLK01# D5 VDDQ11 H3
21 FBA_WCLK01# FBA_WCLK01 WCK01# WCK23# VDDQ12
D4 K3
21 FBA_WCLK01 WCK01 WCK23 VDDQ13 M3
FBA_WCLK23# P5 VDDQ14 P3

-X
21 FBA_WCLK23# FBA_WCLK23 WCK23# WCK01# VDDQ15
P4 T3
21 FBA_WCLK23 WCK23 WCK01 VDDQ16 E5
VDDQ17 N5
A10 VDDQ18 E10
FBA_VREFC VREFD1 VDDQ19
U10 N10

https://vinafix.com
+1.35VGS FBA_VREFC J14 VREFD2 VDDQ20 B12
VREFC VDDQ21 D12
CV2723 1 VDDQ22 F12
820P_0402_25V7 VDDQ23 H12
VDDQ24
1

FBA_CMD13 J2 K12

Te
RV2706 OPT@ RESET# VDDQ25 +1.35VGS
2 M12
549_0402_1% VDDQ26 P12
OPT@ VDDQ27 T12
VDDQ28 CV2724 CV2725 CV2726 CV2727 CV2728
G13
1 2

FBA_VREFC H1 VDDQ29 L13

K1 VSS1 VDDQ30 B14

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

4.3U_0402_4V6-M
B5 VSS2 VDDQ31 D14

OPT_3T@
RV2707 VSS3 VDDQ32 1 1 1 1

OPT_N3T@

OPT_N3T@

OPT_N3T@

OPT_N3T@
G5 F14

3
1.33K_0402_1% VSS4 VDDQ33
L5 M14
OPT@ VSS5 VDDQ34
T5 P14
2

B10 VSS6 VDDQ35 T14

4
2 2 2 2

ch
D10 VSS7 VDDQ36
G10 VSS8
L10 VSS9 A1
P10 VSS10 VSSQ1 C1
T10 VSS11 VSSQ2 E1
H14 VSS12 VSSQ3 N1
B K14 VSS13 VSSQ4 R1 B
VSS14 VSSQ5 U1
VSSQ6 H2
+1.35VGS G1 VSSQ7 K2
L1 VDD1 VSSQ8 A3

ni
VDD2 VSSQ9 +1.35VGS
G4 C3
FBA_VREFC L4 VDD3 VSSQ10 E3
RV2708 C5 VDD4 VSSQ11 N3 CV2732 CV2733 CV2729 CV2730
VDD5 VSSQ12 CV2731
R5 R3

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

4.3U_0402_4V6-M
931_0402_1% VDD6 VSSQ13
C10 U3

OPT_3T@
2 1 VDD7 VSSQ14 1 1 1 1

OPT_N3T@

OPT_N3T@

OPT_N3T@

OPT_N3T@
R10 C4

3
D11 VDD8 VSSQ15 R4
OPT@ VDD9 VSSQ16

ca
G11 F5
L11 VDD10 VSSQ17 M5

4
VDD11 VSSQ18 2 2 2 2
P11 F10
1

D QV2701 G14 VDD12 VSSQ19 M10

2 VDD13 VSSQ20
26 GPIO10_FBVREF_ALTV LBSS139WT1G_SC70-3 L14 C11
G VDD14 VSSQ21 R11
OPT@ VSSQ22
1

S A12
3

RV2709 VSSQ23 C12

100K_0402_5% VSSQ24 E12
OPT@ VSSQ25 N12
VSSQ26 R12

l
2

170-BALL VSSQ27 U12

VSSQ28 H13
SGRAM GDDR5 VSSQ29 K13
VSSQ30 A14
VSSQ31 C14
VSSQ32 E14
VSSQ33 N14
VSSQ34 R14
VSSQ35 U14
VSSQ36
@ H5GQ1H24AFR-T2L_BGA170

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 GPU_GDDR5_Rank0_[31:0]

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday, December 06, 2019 Sheet 27 of 60
5 4 3 2 1
 5 4 3 2 1

upper 32 bits

21,27 FBA_D[0..63]
MF=0 No Mirror
21,27 FBA_CMD[31..0]
UM2801
21,27 FBA_EDC[7..0]
MF=0 MF=1 MF=1 MF=0
D 21,27 FBA_DBI[7..0] D
A4 FBA_D32
FBA_EDC4 C2 DQ24 DQ0 A2 FBA_D33
FBA_EDC5 C13 EDC0 EDC3 DQ25 DQ1 B4 FBA_D34
FBA_EDC6 R13 EDC1 EDC2 DQ26 DQ2 B2 FBA_D35
FBA_EDC7 EDC2 EDC1 DQ27 DQ3 FBA_D36
BYTE4
R2 E4
EDC3 EDC0 DQ28 DQ4 E2 FBA_D37
DQ29 DQ5 F4 FBA_D38
FBA_DBI4 D2 DQ30 DQ6 F2 FBA_D39
FBA_DBI5 D13 DBI0# DBI3# DQ31 DQ7 A11 FBA_D40
FBA_DBI6 P13 DBI1# DBI2# DQ16 DQ8 A13 FBA_D41
FBA_DBI7 P2 DBI2# DBI1# DQ17 DQ9 B11 FBA_D42
DBI3# DBI0# DQ18 DQ10 B13 FBA_D43
FBA_CLK1 DQ19 DQ11 FBA_D44
BYTE5 +1.35VGS
J12 E11
FBA_CLK1# J11 CK DQ20 DQ12 E13 FBA_D45 Close to VRAM
FBA_CMD30 J3 CK# DQ21 DQ13 F11 FBA_D46
FBA_CLK1 OPT@ CKE# DQ22 DQ14 FBA_D47
RV2801 1 2 40.2_0402_1% F13 CV2802 CV2803 CV2804 CV2805 CV2806 CV2807 CV2808
21 FBA_CLK1 DQ23 DQ15 U11 FBA_D48
FBA_CLK1# RV2802 1 OPT@ 2 40.2_0402_1% FBA_CMD18 H11 DQ8 DQ16 U13 FBA_D49

10U 6.3V M X5R 0402

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201
21 FBA_CLK1# FBA_CMD20 BA0/A2 BA2/A4 DQ9 DQ17 FBA_D50

10U 6.3V M X5R 0402

K10 T11
1 FBA_CMD19 BA1/A5 BA3/A3 DQ10 DQ18 FBA_D51 1 1 1 1 1 1 1

OPT_NS@

OPT_NS@
K11 T13

OPT@

OPT@

OPT_NS@

OPT_NS@

OPT_NS@
CV2801 FBA_CMD17 H10 BA2/A4 BA0/A2 DQ11 DQ19 N11 FBA_D52
BYTE6

El
0.01U_0201_10V6K BA3/A3 BA1/A5 DQ12 DQ20 FBA_D53
N13
OPT@ DQ13 DQ21 M11 FBA_D54
2 DQ14 DQ22 2 2 2 2 2 2 2
FBA_CMD22 K4 M13 FBA_D55
FBA_CMD27 H5 A8/A7 A10/A0 DQ15 DQ23 U4 FBA_D56
FBA_CMD26 H4 A9/A1 A11/A6 DQ0 DQ24 U2 FBA_D57
FBA_CMD23 K5 A10/A0 A8/A7 DQ1 DQ25 T4 FBA_D58
FBA_CMD25 J5 A11/A6 A9/A1 DQ2 DQ26 T2 FBA_D59
A12/RFU/NC DQ3 DQ27 N4 FBA_D60
DQ4 DQ28 FBA_D61 BYTE7
A5 N2 CV2814 CV2809 CV2810 CV2811 CV2812 CV2813 CV2815

et
U5 VPP/NC1 DQ5 DQ29 M4 FBA_D62
VPP/NC2 DQ6 DQ30 FBA_D63

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201
M2
DQ7 DQ31

OPT_NS@
+1.35VGS
1 1 1 1 1 1 1

OPT_NS@

OPT_NS@

OPT_NS@

OPT_NS@

OPT_NS@
RV28031 OPT@ 2 1K_1%_0201 J1

OPT@
RV28041 OPT@ 2 1K_1%_0201 FBA_SEN1 J10 MF
RV2805 1 2 121_0402_1% OPT@ J13 SEN B1
ZQ VDDQ1 D1 2 2 2 2 2 2 2
C VDDQ2 F1
C

ro
FBA_CMD24 J4 VDDQ3 M1
FBA_CMD28 G3 ABI# VDDQ4 P1
FBA_CMD16 G12 RAS# CAS# VDDQ5 T1
FBA_CMD31 L3 CS# WE# VDDQ6 G2
FBA_CMD21 L12 CAS# RAS# VDDQ7 L2
WE# CS# VDDQ8 B3
VDDQ9 D3 Around VRAM
VDDQ10 F3
FBA_WCLK45# D5 VDDQ11 H3 CV2816 CV2817 CV2818 CV2819 CV2820 CV2821 CV2822

-X
21 FBA_WCLK45# FBA_WCLK45 WCK01# WCK23# VDDQ12
D4 K3
21 FBA_WCLK45 WCK01 WCK23 VDDQ13

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
M3
FBA_WCLK67# P5 VDDQ14 P3 1 1 1 1 1 1 1

OPT@

OPT@

OPT@

OPT@
21 FBA_WCLK67# FBA_WCLK67 WCK23# WCK01# VDDQ15
P4 T3

OPT_NS@

OPT_NS@

OPT_NS@
21 FBA_WCLK67 WCK23 WCK01 VDDQ16 E5

https://vinafix.com
VDDQ17 N5
FBA_VREFC VDDQ18 2 2 2 2 2 2 2
A10 E10
U10 VREFD1 VDDQ19 N10
FBA_VREFC J14 VREFD2 VDDQ20 B12
VREFC VDDQ21 D12

Te
1 VDDQ22
CV2823 F12
820P_0402_25V7 VDDQ23 H12
FBA_CMD29 J2 VDDQ24 K12
OPT@ 2 RESET# VDDQ25 M12
VDDQ26 P12
VDDQ27 T12
VDDQ28 G13
H1 VDDQ29 L13
K1 VSS1 VDDQ30 B14
B5 VSS2 VDDQ31 D14
G5 VSS3 VDDQ32 F14

ch
L5 VSS4 VDDQ33 M14
VSS5 VDDQ34 +1.35VGS
T5 P14
B10 VSS6 VDDQ35 T14
D10 VSS7 VDDQ36
VSS8 CV2828
G10 CV2824 CV2825 CV2826 CV2827
L10 VSS9 A1
VSS10 VSSQ1

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201
B P10 C1 B
VSS11 VSSQ2

4.3U_0402_4V6-M
T10 E1
VSS12 VSSQ3

OPT_3T@
H14 N1
VSS13 VSSQ4

OPT_N3T@

OPT_N3T@

OPT_NS@

OPT_N3T@
K14 R1 1 1 1 1

3
VSS14 VSSQ5 U1

ni
VSSQ6 H2
+1.35VGS G1 VSSQ7 K2

4
VDD1 VSSQ8 2 2 2 2
L1 A3
G4 VDD2 VSSQ9 C3
L4 VDD3 VSSQ10 E3
C5 VDD4 VSSQ11 N3
R5 VDD5 VSSQ12 R3
VDD6 VSSQ13

ca
C10 U3
R10 VDD7 VSSQ14 C4
D11 VDD8 VSSQ15 R4
G11 VDD9 VSSQ16 F5
L11 VDD10 VSSQ17 M5
P11 VDD11 VSSQ18 F10 +1.35VGS
G14 VDD12 VSSQ19 M10
L14 VDD13 VSSQ20 C11
VDD14 VSSQ21 R11
VSSQ22 CV2829 CV2830 CV2831 CV2832 CV2833
A12
VSSQ23 C12

l
VSSQ24 E12

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

4.3U_0402_4V6-M
VSSQ25 N12

OPT_NS@
VSSQ26 1 1 1 1

OPT_NS@

OPT_NS@

OPT_NS@

OPT_NS@
R12

3
170-BALL VSSQ27 U12
VSSQ28 H13
SGRAM GDDR5 VSSQ29 K13

4
VSSQ30 2 2 2 2
A14
VSSQ31 C14
VSSQ32 E14
VSSQ33 N14
VSSQ34 R14
VSSQ35 U14
VSSQ36
@
H5GQ1H24AFR-T2L_BGA170
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 GPU_GDDR5_Rank0_[64:32]

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday, December 06, 2019 Sheet 28 of 60
5 4 3 2 1
 5 4 3 2 1

+5VS
+3VS J1
+3VL 1
2 1
BEEP 3 2
4 3
RA3001 1 2 1K_0402_5% CA3001 1 2 0.1U_6.3V_K_X5R_0201 5 4
NOVO# R3001 1 2 200_0402_1% NOVO_BTN# 6 5
44 NOVO# EC_MUTE# 6
7
DA3001 44 EC_MUTE# 7
8
3 USB20_N8 9 8
D 44 EC_BEEP 9 USB20_N8 USB20_P8 9 D
10
1 9 USB20_P8 10
RA3002 1 2 1K_0402_5% CA3002 1 2 0.1U_6.3V_K_X5R_0201 BEEP 11
12 11
33 DMIC_CLK 12
8 PCH_BEEP
2 33 DMIC_DATA
13
14 13
14

2
BAT54CW_SOT323-3 15
6 HDA_BITCLK_AUDIO 16 15
@ RA3003
6 HDA_SDOUT_AUDIO 17 16
10K_0402_5%
6 HDA_SDIN0 17
@ 18
6 HDA_SYNC_AUDIO 18
RA3004 1 2 0_0402_5% @ DVDD_IO
19

1
20 19
+1.8VS 20
21
22 GND1
GND2
HIGHS_FC5AF201-1151H
ME@

CPU HDA BUS power 1.8VALW

El
+5VS

DVDD_IO +3VS J2
+1.8VALW 1mA +3VL 1
2 1
BEEP 3 2
RA3006 1 2 0_5%_0603 @ DVDD_IO 4 3
4

et
5
+3VALW NOVO_BTN# 6 5
6

2
EC_MUTE# 7
@ RA3007 8 7
RA3005 1 2 0.01_0603_1% 0_0402_5% USB20_N8 9 8
@ USB20_P8 10 9
11 10

1
C DMIC_CLK 12 11 C
DMIC_DATA 12

ro
13
14 13
HDA_BITCLK_AUDIO 15 14
HDA_SDOUT_AUDIO 16 15
HDA_BITCLK_AUDIO HDA_SDIN0 17 16
HDA_SYNC_AUDIO 18 17
19 18
DVDD_IO 19
1 +1.8VS
20
CA3003 ON/OFF 21 20 25
44,45 ON/OFF PWR_LED1# 21 GND1

-X
33P_0402_50V8J 22 26
44 PWR_LED1# PWR_LED2# 22 GND2
EMC_NS@
44 PWR_LED2#
23
2 24 23
+3VALW 24
HIGHSTAR_FC5AF241-2931H

https://vinafix.com
ME@

Te
ch
+5VS

+3VS J3
+3VL 1
2 1
BEEP 3 2
B
4 3 B
5 4
NOVO_BTN# 6 5
EC_MUTE# 7 6

ni
8 7
USB20_N8 9 8
USB20_P8 10 9
11 10
DMIC_CLK 12 11
DMIC_DATA 13 12
14 13
HDA_BITCLK_AUDIO 15 14

ca
HDA_SDOUT_AUDIO 16 15
HDA_SDIN0 17 16
HDA_SYNC_AUDIO 18 17
19 18
DVDD_IO 19
+1.8VS 20
ON/OFF 21 20
PWR_LED1# 22 21
PWR_LED2# 23 22
24 23
+3VALW 24
25
25

l
26
+1.8VS 26
27
28 27
+3VS 28
29 32
30 29 GND2 31
+5VS 30 GND1

HIGHS_FC5AF301-2931H
ME@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 CODEC_RTS5199

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday, December 06, 2019 Sheet 30 of 60
5 4 3 2 1
 5 4 3 2 1

+3VS
LCD POWER CIRCUIT CMOS Camera
+3VS +3VS_EDP
FI3301 W=40mils
CG3301 +LCDVDD_CON
1
W=60mils 1 2
UG3301

0.1U_6.3V_K_X5R_0201
0.1U_6.3V_K_X5R_0201

10U 6.3V M X5R 0402

0.047U_0402_16V7K
5 1 1 1A_32V_ERBRD1R00X

CI3301
D 2 IN OUT D

CI3302

CI3303
1 2

4.7U_0402_6.3V6M

0.1U_6.3V_K_X5R_0201

33P_0402_50V8J
2
GND
PCH_ENVDD 1 1 1 2

CG3302

CG3303

CG3304
4 3
4 PCH_ENVDD EN OCB 2 1
SY6288C20AAC_SOT23-5 @ @
2 2 2
@ @ CPU_EDP_TX0+ CG3305 1 2 0.1U_6.3V_K_X5R_0201 EDP_TX0+
4 CPU_EDP_TX0+
CPU_EDP_TX0- CG3306 1 2 0.1U_6.3V_K_X5R_0201 EDP_TX0-
4 CPU_EDP_TX0-
EMI request
For RF CPU_EDP_TX1+ EDP_TX1+
CG3307 1 2 0.1U_6.3V_K_X5R_0201
V9B+ +LEDVDD 4 CPU_EDP_TX1+
FG3301 CPU_EDP_TX1- CG3308 1 2 0.1U_6.3V_K_X5R_0201 EDP_TX1-
1 2 4 CPU_EDP_TX1-

0.47U_25V_K_X5R_0603

2200P_25V_K_X7R_0402
3A_32V_ERBRD3R00X
CG3309 CPU_EDP_AUX# EDP_AUX#

CG3310
1 1 CG3311 1 2 0.1U_6.3V_K_X5R_0201
4 CPU_EDP_AUX#
CPU_EDP_AUX EDP_AUX JEDP1

El
CG3312 1 2 0.1U_6.3V_K_X5R_0201
4 CPU_EDP_AUX 1
2 2 +LEDVDD 1
2
3 2
4 3
5 4
EDP_TX0+ 6 5
EDP_TX0- 7 6
8 7
EMI Request 8
Camera

et
EDP_TX1+ 9
RI3301 1 2 0_0402_5% @ EDP_TX1- 10 9
11 10
EDP_AUX 12 11
LI3301 EDP_AUX# 13 12
+3VS USB20_N5 1 2 USB20_N5_R 14 13
9 USB20_N5 1 2 15 14
DISPOFF#
C INVT_PWM 16 15 C
16
2

USB20_P5 USB20_P5_R CPU_EDP_HPD

ro
4 3 17
9 USB20_P5 4 3 4 CPU_EDP_HPD 17
RG3302 +LCDVDD_CON
18
PCH_ENBKL RG3303 1 @ 2 0_0402_5% 4.7K_0402_5% EXC24CH900U_4P 19 18
4,44 PCH_ENBKL 20 19
@ @
21 20
1

RI3302 1 2 0_0402_5% @ DMIC_CLK 22 21

1 @ 2 0_0402_5% 30 DMIC_CLK DMIC_DATA 23 22
BKOFF# RG3304 DISPOFF#
44 BKOFF# 30 DMIC_DATA 24 23
+3VS_EDP 24
25
25

-X
26
27 26
+3VS USB20_P5_R 28 27
USB20_N5_R 29 28
30 29
EMI request 30
2

31

https://vinafix.com
RG3305 32 G1
1K_0402_5% DMIC_DATA DMIC_CLK DISPOFF# INVT_PWM G2
@ DRAPH_FC5AF301-3181H
1 1 1 1 ME@
@
1

Te
RG3306 1 2 0_0402_5% INVT_PWM
4 PCH_EDP_PWM
CG3410 CG3313 CG3314 CG3315
1

100P_0402_50V8J 100P_0402_50V8J 470P_0402_50V7K 470P_0402_50V7K

2 @ 2 @ 2 @ 2 @
RG3307
100K_0402_5%
2

ch
Vinafix.com
B B

Touch Screen

ni
+5VS +5VS_TS

RG3310 1 @ 2 0_0402_5%

ca
RG3309 1 2 0_0402_5% @ USB20_P6_CONN
+5VS_TS +3VS 1
CG3316
USB20_N6_CONN 0.1u_0201_10V6K
AZ5725-01F.R7GR_DFN1006P2X2

TS@
AZ5423-01F.R7GR_DFN1006P2E2

AZ5423-01F.R7GR_DFN1006P2E2
1

LG3301 RG3308 1 2 0_0402_5% @ 2 +5VS_TS

USB20_P6 USB20_P6_CONN
EMC_NS@

4 3
1

9 USB20_P6 4 3 JTS1
DG3301

EMC_NS@

DG3302

EMC_NS@

DG3303

1
USB20_N6 1 2 USB20_N6_CONN RG3311 1 2 0_0402_5% @ TS_RS 2 1
9 USB20_N6 1 2 44 EC_TS_ON 3 2
3

l
USB20_N6_CONN
2

EXC24CH900U_4P 4
EMC_NS@ USB20_P6_CONN 5 4
2

6 5
6 7
RG3312 1 2 0_0402_5% @ GND1 8
GND2
HIGHS_WS83061-S0171-HF
ME@
For EMI For ESD

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 eDP/CAMERA.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday, December 06, 2019 Sheet 33 of 60
5 4 3 2 1
 5 4 3 2 1

+3VS

2
G
CPU_HDMI_TXP2 CG3401 1 2 0.1U_6.3V_K_X5R_0201 HDMI_TX2_DP_C
4 CPU_HDMI_TXP2 CPU_HDMI_TXN2 HDMI_TX2_DN_C
CG3402 1 2 0.1U_6.3V_K_X5R_0201
4 CPU_HDMI_TXN2
CPU_HDMI_TXP1 CG3403 1 2 0.1U_6.3V_K_X5R_0201 HDMI_TX1_DP_C PCH_HDMI_DDC_DATA 1 6 DDPB_DATA_U

S
4 CPU_HDMI_TXP1 CPU_HDMI_TXN1 HDMI_TX1_DN_C 4 PCH_HDMI_DDC_DATA

D
CG3404 1 2 0.1U_6.3V_K_X5R_0201
4 CPU_HDMI_TXN1 QG3401A
2N7002KDWH_SOT363-6
CPU_HDMI_TXP0 CG3405 1 2 0.1U_6.3V_K_X5R_0201 HDMI_TX0_DP_C
4 CPU_HDMI_TXP0 CPU_HDMI_TXN0 HDMI_TX0_DN_C
CG3406 1 2 0.1U_6.3V_K_X5R_0201
4 CPU_HDMI_TXN0

5
G
D CPU_HDMI_CLKP HDMI_CLK_DP_C D
CG3407 1 2 0.1U_6.3V_K_X5R_0201
4 CPU_HDMI_CLKP CPU_HDMI_CLKN 1 2 0.1U_6.3V_K_X5R_0201 HDMI_CLK_DN_C
CG3408
4 CPU_HDMI_CLKN
PCH_HDMI_DDC_CLK 4 3 DDPB_CLK_U

S
4 PCH_HDMI_DDC_CLK

D
QG3401B
2N7002KDWH_SOT363-6

+3VS
Need to change about 470Ohm 5%-575412 Page115 Rev0.8
RG3425 2 @ 1 0_0402_5%
HDMI_TX0_DP_C RG3401 1 2 470_0402_5%
+1.8VALW
HDMI_TX0_DN_C RG3402 1 2 470_0402_5%
HDMI_TX1_DP_C RG3403 1 2 470_0402_5% RG3405 1 2 0_0402_5% @
HDMI_TX1_DN_C RG3404 1 2 470_0402_5%

2
HDMI_TX2_DP_C RG3406 1 2 470_0402_5% RG3408

El
1M_0402_5%

2
HDMI_TX2_DN_C RG3407 1 2 470_0402_5%
QG3403

1
HDMI_CLK_DP_C RG3409 1 2 470_0402_5%
CPU_HDMI_HPD 3 1 HDMI_DET
HDMI_CLK_DN_C 1 2 470_0402_5% 4 CPU_HDMI_HPD
RG3410

2
LSI1012XT1G_SC-89-3
1

D RG3411

et
+3VS
2 20K_0402_5%
QG3404 Maybe 2N7002 is ok?
G
L2N7002KWT1G_SOT323-3

1
S
3

1 2
C RG3412 C

ro
100K_0402_5%
@

-X
@ HDMI_TX0_DP_CON
RG3413 1 2 0_0402_5%

F1 use 1.1A
1

LG3401
HDMI_TX0_DP_C 4 3 RG3414

https://vinafix.com
4 3 +5VS_HDMI_F +5VS_HDMI
DG3401 +5VS
270_0402_1%
HDMI_CLK_DP_CON 1 1 HDMI_CLK_DP_CON
EMC_HDMI_R@ 10 9
HDMI_TX0_DN_C 1 2 FG3401
2

1 2 HDMI_CLK_DN_CON 2 2 8 HDMI_CLK_DN_CON 1 3 1 2
9

S
Te
EXC24CH900U_4P
EMC_HDMI@ HDMI_TX0_DP_CON 4 4 7 7 HDMI_TX0_DP_CON 1.1A_8V_1206L110THYR

G
2
RG3415 1 @ 2 0_0402_5% HDMI_TX0_DN_CON HDMI_TX0_DN_CON 5 5 6 HDMI_TX0_DN_CON QG3402
6 1
LP2301ALT1G_SOT23-3 CG3409
3 3 0.1U_6.3V_K_X5R_0201
46 SUSP
8 2

AZ1045-04F_DFN2510P10E-10-9
RG3416 1 2 0_0402_5% @ HDMI_TX1_DP_CON EMC_NS@

ch
LG3402
2

HDMI_TX1_DP_C 4 3 DG3402
4 3 RG3417 HDMI_TX1_DN_CON 1 1 10 9 HDMI_TX1_DN_CON
270_0402_1%
HDMI_TX1_DN_C 1 2 EMC_HDMI_R@
B 1 2 HDMI_TX1_DP_CON 2 2 8 HDMI_TX1_DP_CON B
9
+5VS_HDMI
1

EXC24CH900U_4P HDMI_TX2_DN_CON HDMI_TX2_DN_CON

4 4 7 7
EMC_HDMI@
HDMI_TX2_DP_CON 5 5 6 HDMI_TX2_DP_CON

ni
RG3418 1 2 0_0402_5% @ HDMI_TX1_DN_CON 6

2
1
3 3 RPG1
2.2K_0404_4P2R_5%
8 +5VS_HDMI
HDMI_TX2_DP_CON JHDMI1
RG3419 1 2 0_0402_5% @

3
4
AZ1045-04F_DFN2510P10E-10-9
EMC_NS@ 18 15 DDPB_CLK_U

ca
LG3403 +5V_Power SCL 16 DDPB_DATA_U
SDA
2

HDMI_TX2_DP_C 4 3
4 3 RG3420 HDMI_TX0_DP_CON 7
HDMI_TX0_DN_CON 9 TMDS_Data0+ 13
270_0402_1%
HDMI_TX2_DN_C 1 2 EMC_HDMI_R@ DG3403 HDMI_TX1_DP_CON 4 TMDS_Data0- CEC 17
1 2 HDMI_DET 1 1 HDMI_DET HDMI_TX1_DN_CON TMDS_Data1+ DDC/CEC_Ground HDMI_DET
10 9 6 19
1

EXC24CH900U_4P HDMI_TX2_DP_CON 1 TMDS_Data1- Hot_Plug_Detect

EMC_HDMI@ DDPB_CLK_U 2 2 8 DDPB_CLK_U HDMI_TX2_DN_CON 3 TMDS_Data2+
9
TMDS_Data2-
RG3421 1 2 0_0402_5% @ HDMI_TX2_DN_CON DDPB_DATA_U 4 4 7 7 DDPB_DATA_U 8 14
TMDS_Data0_Shield Utility

l
5
+5VS_HDMI 5 5 6 +5VS_HDMI 2 TMDS_Data1_Shield
6
TMDS_Data2_Shield
3 3 20
11 GND1 21
8 HDMI_CLK_DP_CON 10 TMDS_Clock_Shield GND2 22
HDMI_CLK_DN_CON 12 TMDS_Clock+ GND3 23
RG3422 1 2 0_0402_5% @ HDMI_CLK_DP_CON TMDS_Clock- GND4
AZ1045-04F_DFN2510P10E-10-9
LG3404 EMC_NS@
2

HDMI_CLK_DP_C 4 3
4 3 ALLTO_C128AF-K1935-L
RG3423 For EMC
270_0402_1% ME@
HDMI_CLK_DN_C 1 2 EMC_HDMI_R@
1 2
1

A EXC24CH900U_4P A
EMC_HDMI@

RG3424 1 2 0_0402_5% @ HDMI_CLK_DN_CON

For EMC

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 HDMI_CONN

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday, December 06, 2019 Sheet 34 of 60
5 4 3 2 1
 5 4 3 2 1

M.2 SSD
Vinafix.com +3VS

PJ3701
+3VS_SSD

+3VS_SSD 1 2 Min 3A
JSSD1 1 2

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

4.7U_0402_6.3V6M

0.1U_6.3V_K_X5R_0201
JUMP_43X39

CF3705

CF3706

CF3707

CF3708
1 2
3 GND_1 3.3V_1 4
@ 1 1 1 1
GND_2 3.3V_2

10U 6.3V M X5R 0402

CF3703
0.1U_6.3V_K_X5R_0201
5 6 1 1
9 PCIE_PRX_DTX_N13 PERN3 N/C_2

CF3701
7 8
9 PCIE_PRX_DTX_P13 PERP3 N/C_3 2 2 2 2
9 10
0.22U_0402_10V6K 1 2 CF3702 PCIE_PTX_C_DRX_N13 11 GND_3 DAS/DSS# 12 @ @ @ @
9 PCIE_PTX_DRX_N13 PCIE_PTX_C_DRX_P13 PETN3 3.3V_3 2 2@
0.22U_0402_10V6K 1 2 CF3704 13 14
D 9 PCIE_PTX_DRX_P13 PETP3 3.3V_4 D
15 16
17 GND_4 3.3V_5 18
9 PCIE_PRX_DTX_N14 19 PERN2 3.3V_6 20
9 PCIE_PRX_DTX_P14 PERP2 N/C_4
21 22
0.22U_0402_10V6K 1 2 CF3709 PCIE_PTX_C_DRX_N14 23 GND_5 N/C_5 24
9 PCIE_PTX_DRX_N14 PCIE_PTX_C_DRX_P14 PETN2 N/C_6
9 PCIE_PTX_DRX_P14 0.22U_0402_10V6K 1 2 CF3710 25 26
PETP2 N/C_7

1
27 28
29 GND_6 N/C_8 30 RF3702
9 PCIE_PRX_DTX_N15 PERN1 N/C_9 10K_0402_5%
31 32
9 PCIE_PRX_DTX_P15 33 PERP1 N/C_10 34 +3VS_SSD
@
0.22U_0402_10V6K 1 2 CF3711 PCIE_PTX_C_DRX_N15 35 GND_7 N/C_11 36
9 PCIE_PTX_DRX_N15

2
0.22U_0402_10V6K 1 2 CF3712 PCIE_PTX_C_DRX_P15 37 PETN1 N/C_12 38 PCH_SATA_DEVSLP
9 PCIE_PTX_DRX_P15 PETP1 DEVSLP PCH_SATA_DEVSLP 9

1
39 40
41 GND_8 N/C_13 42 +3VS_SSD RF3704
9 PCIE_PRX_DTX_P16 PERN0/SATA-B+ N/C_14 SSD_PCIE_DET#
43 44 100K_0402_5%
9 PCIE_PRX_DTX_N16 PERP0/SATA-B- N/C_15 SSD_PCIE_DET# 9
45 46 @
GND_9 N/C_16

1
0.22U_0402_10V6K 1 2 CF3713 PCIE_PTX_C_DRX_N16 47 48
9 PCIE_PTX_DRX_N16

2
PETN0/SATA-A- N/C_17

3
0.22U_0402_10V6K 1 2 CF3714 PCIE_PTX_C_DRX_P16 49 50 PLT_RST# RF3705
9 PCIE_PTX_DRX_P16 PLT_RST# 11,26,40,44 D
51 PETP0/SATA-A+ PERST# 52 SSD_CLKREQ_Q# RF3703 1 2 0_0402_5% @ 100K_0402_5% 5 QF3701B
GND_10 CLKREQ# SSD_CLKREQ# 10
53 54 @ G
10 CLK_PCIE_SSD# REFCLKN PEWAKE#

6
55 56 D 2N7002KDWH_SOT363-6
10 CLK_PCIE_SSD

2
REFCLKP N/C_18 SSD_DET

El
57 58 2 S

4
GND_11 N/C_19 G @
59 NC NC 60
61 NC NC 62 QF3701A S

1
63 NC NC 64 +3VS_SSD 2N7002KDWH_SOT363-6
65 NC NC 66 @
67 68
SSD_DET 69 N/C_1 SUSCLK 70
71 PEDET 3.3V_7 72
GND_12 3.3V_8

et
CF3715
10U 6.3V M X5R 0402

CF3716
0.1U_6.3V_K_X5R_0201
73 74
SSD_DET# 75 GND_13 3.3V_9 1 1 SSD_DET RF3707 1 2 0_0402_5% @ SSD_PCIE_DET#
GND_14
SATA-->GND 77 76
PCIE-->NC PEG1 PEG2 2 2@

ARGOS_NASM0-S6701-TS40
C ME@ +3VS_SSD C

ro
RF3706 2 @ 1 100K_0402_5% PCH_SATA_DEVSLP

-X
SATA

9 SATA_PTX_DRX_P0
SATA_PTX_DRX_P0 RF3709 1 2 0_0201_5% SATA_NRE@ SATA_PTX_DRX_P0_R CF3735 1
https://vinafix.com
2 0.01U_6.3V_K_X7R_0201 SATA_NRE@ SATA_PTX_DRX_P0_CON

9 SATA_PTX_DRX_N0
9 SATA_PRX_DTX_P0
9 SATA_PRX_DTX_N0
Te
SATA_PTX_DRX_N0 RF3710 1 2 0_0201_5% SATA_NRE@ SATA_PTX_DRX_N0_R CF3736 1 2 0.01U_6.3V_K_X7R_0201 SATA_NRE@ SATA_PTX_DRX_N0_CON
+5VS +5VS_HDD
SATA_PRX_DTX_P0 RF3712 1 2 0_0201_5% SATA_NRE@ SATA_PRX_DTX_P0_R CF3738 1 2 0.01U_6.3V_K_X7R_0201 SATA_NRE@ SATA_PRX_DTX_P0_CON
SATA_PRX_DTX_N0 RF3711 1 SATA_PRX_DTX_N0_R SATA_PRX_DTX_N0_CON
2 0_0201_5% SATA_NRE@ CF3737 1 2 0.01U_6.3V_K_X7R_0201 SATA_NRE@ PJ3708
1 2
1 2

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
JUMP_43X39
@

CF3717

CF3718

CF3719
10U 6.3V M X5R 0402

CF3720
10U 6.3V M X5R 0402

CF3721
0.1U_6.3V_K_X5R_0201

CF3722 RF_NS@
33P_0402_50V8J

CF3723 RF_NS@
33P_0402_50V8J
1 1 1 1 1 1 1

ch
2@ 2@ 2@ 2 2 2 2
SATA Redriver +3VS +3VS

B B
2

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201
CF3732 @

CF3733 SATA_RE@

RF3713
1/20W_4.7K_5%_0201 1 1
SATA_RE@

ni
1

@ UF1
0.1U_6.3V_K_X5R_0201 2 1 CF3734 7 10 2 2
EN VDD1 20
SATA_PTX_DRX_P0 CF3728 1 2 0.01U_6.3V_K_X7R_0201 SATA_RE@ SATA_PTX_DRX_P0_C 1 VDD2
SATA_PTX_DRX_N0 CF3729 1 2 0.01U_6.3V_K_X7R_0201 SATA_RE@ SATA_PTX_DRX_N0_C 2 A_INP 6 REXT
A_INN REXT 16 DEW
SATA_PRX_DTX_P0 CF3731 1 2 0.01U_6.3V_K_X7R_0201 SATA_RE@ SATA_PRX_DTX_P0_C 5 DEW

ca
SATA_PRX_DTX_N0 CF3730 1 2 0.01U_6.3V_K_X7R_0201 SATA_RE@ SATA_PRX_DTX_N0_C 4 B_OUTP 9 A_DE
B_OUTN A_DE 8 B_DE
A_EQ1 17 B_DE
A_EQ2 18 A_EQ1 15 SATA_PTX_DRX_P0_RE CF3725 1 2 0.01U_6.3V_K_X7R_0201 SATA_RE@ SATA_PTX_DRX_P0_CON
B_EQ1 19 A_EQ2 A_OUTP 14 SATA_PTX_DRX_N0_RE CF3724 1 2 0.01U_6.3V_K_X7R_0201 SATA_RE@ SATA_PTX_DRX_N0_CON
B_EQ2 13 B_EQ1 A_OUTN
B_EQ2 11 SATA_PRX_DTX_P0_RE CF3727 1 2 0.01U_6.3V_K_X7R_0201 SATA_RE@ SATA_PRX_DTX_P0_CON
3 B_INP 12 SATA_PRX_DTX_N0_RE CF3726 1 2 0.01U_6.3V_K_X7R_0201 SATA_RE@ SATA_PRX_DTX_N0_CON
21 GND1 B_INN
EPAD

l
PS8527CTQFN20GTR2A2_TQFN20_4X4
SATA_RE@
+5VS_HDD

JHDD1
1
2 1
+3VS 3 2
4 3
SATA_PRX_DTX_P0_CON 5 4
SATA_RE@ 1/20W_4.7K_5%_0201 2 1 RF3715 A_EQ1 @ 1/20W_4.7K_5%_0201 2 1 RF3723 SATA_PRX_DTX_N0_CON 6 5
7 6
SATA_RE@ 1/20W_4.7K_5%_0201 2 1 RF3716 A_EQ2 @ 1/20W_4.7K_5%_0201 2 1 RF3724 SATA_PTX_DRX_N0_CON 8 7 12
SATA_PTX_DRX_P0_CON 9 8 GND2
SATA_RE@ 1/20W_4.7K_5%_0201 2 1 RF3717 B_EQ1 @ 1/20W_4.7K_5%_0201 2 1 RF3725 10 9 11
A
10 GND1 A
SATA_RE@ 1/20W_4.7K_5%_0201 2 1 RF3718 B_EQ2 @ 1/20W_4.7K_5%_0201 2 1 RF3726
HIGHS_FC5AF101-2931H
SATA_RE@ 4.99K_0402_1% 2 1 RF3719 REXT @ 1/20W_4.7K_5%_0201 2 1 RF3727 ME@

SATA_RE@ 1/20W_4.7K_5%_0201 2 1 RF3720 DEW @ 1/20W_4.7K_5%_0201 2 1 RF3728

SATA_RE@ 1/20W_4.7K_5%_0201 2 1 RF3721 A_DE SATA_RE@ 1/20W_4.7K_5%_0201 2 1 RF3729

SATA_RE@ 1/20W_4.7K_5%_0201 2 1 RF3722 B_DE SATA_RE@ 1/20W_4.7K_5%_0201 2 1 RF3730

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 NGFF_SSD_1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday, December 06, 2019 Sheet 37 of 60
5 4 3 2 1
 5 4 3 2 1

SMSC thermal sensor

+3VS

RS3901 1 2 10K_0402_5% SEN_THERM_N Near CPU core Near GPU&VRAM

RS3902 1 2 10K_0402_5% @ SEN_ALERT_N
REMOTE2+ REMOTE1+
D D
1

1
CS3902 C 1 C
+3VS 2 QS3902 CS3901 2 QS3901
100P_0402_50V8J
B MMBT3904WH_SOT323-3 100P_0402_50V8J B MMBT3904WH_SOT323-3
2 E E

3
2
1
CS3903 REMOTE2- REMOTE1-
0.1U_6.3V_K_X5R_0201
2 US3901 +3VALW +3VALW

1 10 EC_SMB_CK0
1 VCC SCL EC_SMB_CK0 26,44

1
CS3904
2200P_0402_50V7K REMOTE1+ 2 9 EC_SMB_DA0 RS3904 RS3903
DP1 SDA EC_SMB_DA0 26,44
13.7K_0402_1% 13.7K_0402_1%
2 REMOTE1- 3 8 SEN_ALERT_N @
DN1 ALERT#

2
REMOTE2+ 4 7 SEN_THERM_N NTC_V2 NTC_V1
DP2 THERM# NTC_V2 44 NTC_V1 44
1

1
CS3905 REMOTE2- 5 6
DN2 GND

El
2200P_0402_50V7K RS3907 RS3906
100K_0402_1%_NCP15WF104F03RC 100K_0402_1%_NCP15WF104F03RC
2 F75303M_MSOP10 @

2
REMOTE1+/-, REMOTE2+/-:
Trace width/space:10/10 mil
Trace length:<8"

et
C C

ro
-X
FAN Conn

https://vinafix.com

Te
+5VS

ch
+5VS_FAN1 +5VS_FAN1
JFAN1

44 EC_FAN_PWM
1
RS3909 1 2 0_0402_5% @ 1
2
44 EC_FAN_SPEED 2
3
4 3
B 1 1 4 B
CS3907 5
CS3906
0.1U_6.3V_K_X5R_0201 GND1
10U 6.3V M X5R 0402 6
@ GND2
2 @ 2

ni
HIGHS_WS33040-S0351-HF
ME@

ca
l
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2016/08/16 Deciphered Date 2017/08/15 Thermal sensor/FAN CONN.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday, December 06, 2019 Sheet 39 of 60
5 4 3 2 1
 A B C D E

Mini-Express Card(WLAN/WiMAX)
+3V_WLAN
+3VALW_PCH

+3VALW RN4001 1 2 0_5%_0603 @

+3VALW
UN4001

1
RN4002 5 1 RN4003 1 @ 2 0.01_0603_1%
1
75K_0402_5% IN OUT 1

0.01U_0402_25V7K

100U_1206_6.3V6M
@ 2
GND
1

1
WLAN_PWR_EN

CN4001

CN4002
4 3
EN OCB
SY6288C20AAC_SOT23-5

2
1
D @ 2@

1
2 @
11 CNVI_EN#
G QN4001

1
RN4004
RN4005 S 200K_0402_5%

3
75K_0402_5% @ @

2
@ L2N7002KWT1G_SOT323-3
2

+3V_WLAN
RN4006 1 @ 2 0_0402_5%
11 PM_SLP_WLAN#

CN4003
0.1U_6.3V_K_X5R_0201

CN4004
0.01U_0402_25V7K

CN4005
10U 6.3V M X5R 0402
RN4007 1 @ 2 0_0402_5%
44,46 SUSP#

El
RN4008 1 1 1
200K_0402_5%
@
@ @ @
2

NC if use SUSP# 2 2 2

JWLAN1
1 2
GND1 3.3VAUX1

et
USB20_P10 3 4
+3V_WLAN 9 USB20_P10 USB20_N10 5 USB_D+ 3.3VAUX2 6
9 USB20_N10 USB_D- LED1#
7 8
CNV_WR_D1N 9 GND2 PCM_CLK/I2S_SCK 10 CNVI_RF_RESET#_R RN4010 1 2 0_0402_5% @
10 CNV_WR_D1N CNV_WR_D1P SDIO_CLK PCM_SYNC/I2S_WS CNVI_RF_RESET# 6
11 12
PCH_WLAN_OFF# 10 CNV_WR_D1P SDIO_CMD PCM_IN/I2S_SD_IN CNVI_MODEM_CLKREQ_R
RN4011 1 2 10K_0402_5% @ 13 14 RN4012 1 2 0_0402_5% @
PCH_BT_OFF# CNV_WR_D0N SDIO_DATA0 PCM_OUT/I2S_SD_OUT CNVI_MODEM_CLKREQ 6
RN4009 1 2 10K_0402_5% @ 15 16
10 CNV_WR_D0N CNV_WR_D0P 17 SDIO_DATA1 LED#2 18
2 2
10 CNV_WR_D0P SDIO_DATA2 GND11

ro
19 20
+1.8VALW CNV_WR_CLKN 21 SDIO_DATA3 UART_WAKE# 22 CNVI_BRI_RSP_R RN4013 1 2 22_0402_5% CNVI@
10 CNV_WR_CLKN CNV_WR_CLKP 23 SDIO_WAKE# UART_RXD CNVI_BRI_RSP 10
2 20K_0402_5% CNVI_BRI_DT 10 CNV_WR_CLKP SDIO_RESET#
RN4014 1 @

RN4015 1 2 20K_0402_5% @ CNVI_RGI_DT

KEY E
25 PIN24~PIN31 NC PIN 24
27 26

-X
29 28
31 30

33 32 CNVI_RGI_DT
PCIE_PTX_C_DRX_P9 GND3 UART_TXD CNVI_RGI_RSP_R CNVI_RGI_DT 10
35 34 RN4016 1 2 22_0402_5% CNVI@
9 PCIE_PTX_C_DRX_P9 PCIE_PTX_C_DRX_N9 37 PETP0 UART_CTS 36 CNVI_BRI_DT CNVI_RGI_RSP 10

https://vinafix.com
9 PCIE_PTX_C_DRX_N9 PETN0 UART_RTS EC_TX_RSVD EC_TX CNVI_BRI_DT 10
39 38 RN4017 1 2 0_0402_5% @
PCIE_PRX_DTX_P9 41 GND4 VENDOR_DEFINED1 40 EC_RX_RSVD RN4018 1 2 0_0402_5% @ EC_RX
9 PCIE_PRX_DTX_P9 PCIE_PRX_DTX_N9 PERP0 VENDOR_DEFINED2
PCIE 43 42
9 PCIE_PRX_DTX_N9 PERN0 VENDOR_DEFINED3
45 44

Te
CLK_PCIE_WLAN 47 GND5 COEX3 46
+3V_WLAN 10 CLK_PCIE_WLAN CLK_PCIE_WLAN# REFCLKP0 COEX2
49 48
+3VS 10 CLK_PCIE_WLAN# REFCLKN0 COEX1 SUSCLK_R
51 50 RN4019 1 2 0_0402_5% @
WLAN_CLKREQ_Q# GND6 SUSCLK WLAN_PERST# SUSCLK 10
53 52
CLKREQ0# PERST0#
2

PCIE_WAKE#_WLAN 55 54 BT_OFF# RN4020 1 2 0_0402_5% @

PEWAKE0# W_DISABLE2# PCH_BT_OFF# 9
2

RN4021 57 56 WLAN_OFF# RN4022 1 2 0_0402_5% @

G

GND7 W_DISABLE1# PCH_WLAN_OFF# 8

QN4002 10K_0402_5%

@ CNV_WT_D1N 59 58 WLAN_SMB_DATA RN4023 1 2 0_0402_5% @

10 CNV_WT_D1N EC_RX 44
1

3 1 WLAN_CLKREQ_Q# CNV_WT_D1P 61 RSRVD/PETP1 I2C_DATA 60 WLAN_SMB_CLK RN4024 1 2 0_0402_5% @

10 WLAN_CLKREQ# 10 CNV_WT_D1P RSRVD/PETN1 I2C_CLK EC_TX 44
S

63 62
GND8 ALERT#

1
L2N7002KWT1G_SOT323-3 CNV_WT_D0N 65 64 1

ch
10 CNV_WT_D0N CNV_WT_D0P 67 RSRVD/PERP1 RSRVD 66 T4001
RN4026
10 CNV_WT_D0P RERVD/PERN1 UIM_SWP/PERST1#
RN4025 1 2 0_0402_5% @ 69 68 100K_0402_5%
CNV_WT_CLKN 71 GND9 UIM_POWER_SNK/CLKREQ1# 70
10 CNV_WT_CLKN CNV_WT_CLKP RSRVD/REFCLKP1 UIM_POWER_SRC/GPIO1/PEWAKE1#
73 72
10 CNV_WT_CLKP

2
75 RSRVD/REFCLKN1 3.3VAUX3 74
GND10 3.3VAUX4
3 3
77 76
GND15 GND14
+3V_WLAN
ARGOS_NASE0-S6701-TS40

ni
+3V_WLAN
PCIE_WAKE#_WLAN_R(GPP_H2) ME@

0.01U_0402_25V7K

0.1U_6.3V_K_X5R_0201

10U 6.3V M X5R 0402

strap pin at PCH side, default internal 20K PD 1 1 1
1

CN4006

CN4007

CN4008
R3506 request by CNVi check list
RN4027
200K is to make sure GPP_H2 strap low at RSMRST# 200K_0402_5%
GPP_H2 internal PD disabled after RSMRST# CNVI@ 2 2 2
@

ca
2

RN4028 1 @ 2 0_0402_5% PCIE_WAKE#_WLAN

11 PCIE_WAKE#

RN4029 1 2 0_0402_5% @
6 PCIE_WAKE#_WLAN_R

l
RN4030 1 2 0_0402_5% @ WLAN_PERST#
11,26,37,44 PLT_RST#

RN4031 2 @ 1 0_0402_5%
8 PCH_WLAN_PERST#

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2016/12/14 Deciphered Date 2017/12/13 NGFF_WLAN

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday, December 06, 2019 Sheet 40 of 60
A B C D E
 5 4 3 2 1

USB3.0 Port1 +USB_VCCA

+5VALW
UI4101
5 1
IN OUT
1
CI4101 2
1U_10V_M_X5R_0201 GND
4 3 USB_OC1#
2 ENB OCB USB_OC1# 4 +USB_VCCA +USB_VCCA
SY6288D20AAC_SOT23-5
JUSB2

41,44 USB_ON# USB30_TX_R_P2

Low Active 2A 9
StdA_SSTX+

100U_1206_6.3V6M

1U_0402_10V6K
1
USB30_TX_R_N2 VBUS

CI4103
1 8
D USB20_P1_R StdA_SSTX- D

CI4102
3
D+

2
7
USB20_N1_R 2 GND_DRAIN 10
2 @ USB30_RX_R_P2 6 D- GND_2 11

1
RI4101 1 @ 2 0_0402_5% 4 StdA_SSRX+ GND_3 12
USB30_RX_R_N2 5 GND_1 GND_4 13
StdA_SSRX- GND_5
LI4101
USB20_N1 4 3 USB20_N1_R
9 USB20_N1 4 3 ALLTO_C19043-10905-L
ME@
USB20_P1 1 2 USB20_P1_R
9 USB20_P1 1 2
EXC24CH900U_4P
EMC@

RI4104 1 @ 2 0_0402_5%

El
RI4105 1 2 0_0402_5% @

LI4102 +USB_VCCA USB20_P1_R

USB30_TX_P2 CI4104 1 2 0.1U_6.3V_K_X5R_0201 USB30_TX_C_P2 1 2 USB30_TX_R_P2 DI4102
9 USB30_TX_P2 1 2 USB20_N1_R
USB30_RX_R_N2 10 1 USB30_RX_R_N2
NC1 Line-1

1
USB30_TX_N2 CI4105 1 2 0.1U_6.3V_K_X5R_0201 USB30_TX_C_N2 4 3 USB30_TX_R_N2
9 USB30_TX_N2 USB30_RX_R_P2 9 2 USB30_RX_R_P2

AZ5725-01F.R7GR_DFN1006P2X2
4 3

2
AZ5515-02FPR7GR_DFN1006P3X
NC2 Line-2

1
DI4101

et
EXC24CH900U_4P USB30_TX_R_N2 7 4 USB30_TX_R_N2
EMC_NS@ NC3 Line-3

EMC@

DI4105
EMC_NS@ USB30_TX_R_P2 USB30_TX_R_P2
6 5
NC4 Line-4

2
RI4106 1 2 0_0402_5% @
3
GND1

2
8

3
C GND2 C

ro
RI4107 1 2 0_0402_5% @ AZ1143-04F-R7G_DFN2510P10E10
EMC@

LI4103
USB30_RX_P2 1 2 USB30_RX_R_P2
9 USB30_RX_P2 1 2
EMC
USB30_RX_N2 4 3 USB30_RX_R_N2
9 USB30_RX_N2 4 3

-X
EXC24CH900U_4P
EMC_NS@

RI4108 1 2 0_0402_5% @

https://vinafix.com

Te
+5VALW +USB_VCCB
USB3.0 Port2 5
UI4301
1
IN OUT
1 +USB_VCCB
CI4303 2 +USB_VCCB
1U_10V_M_X5R_0201 GND
4 3 USB_OC0#
2 ENB OCB USB_OC0# 9 JUSB1

100U_1206_6.3V6M
SY6288D20AAC_SOT23-5

ch
USB30_TX_R_P1 9
1

1U_0402_10V6K
41,44 USB_ON# StdA_SSTX+

2
CI4301
1

CI4302
USB30_TX_R_N1 8 VBUS
Low Active 2A USB20_P2_R 3 StdA_SSTX-

1
2 7 D+
USB20_N2_R 2 GND_DRAIN 10
B @ USB30_RX_R_P1 D- GND_2 B
6 11
4 StdA_SSRX+ GND_3 12
USB30_RX_R_N1 5 GND_1 GND_4 13
RI4301 1 @ 2 0_0402_5% StdA_SSRX- GND_5

ni
ALLTO_C19043-10905-L
LI4301
USB20_N2 4 3 USB20_N2_R ME@
9 USB20_N2 4 3

USB20_P2 1 2 USB20_P2_R
9 USB20_P2 1 2

ca
EXC24CH900U_4P
EMC@

RI4302 1 @ 2 0_0402_5%

DI4301
+USB_VCCB USB30_RX_R_N1 10 1 USB30_RX_R_N1 USB20_P2_R
NC1 Line-1
AZ5725-01F.R7GR_DFN1006P2X2

RI4303 1 2 0_0402_5% @ USB30_RX_R_P1 9 2 USB30_RX_R_P1 USB20_N2_R

NC2 Line-2

l
1

USB30_TX_R_N1 USB30_TX_R_N1

AZ5515-02FPR7GR_DFN1006P3X
7 4
NC3 Line-3

2
LI4302
1

USB30_TX_P1 USB30_TX_C_P1 USB30_TX_R_P1 USB30_TX_R_P1 USB30_TX_R_P1

EMC_NS@

DI4302

CI4304 1 2 0.1U_6.3V_K_X5R_0201 1 2 6 5
9 USB30_TX_P1 1 2 NC4 Line-4

EMC@

DI4509
3
USB30_TX_N1 CI4305 1 2 0.1U_6.3V_K_X5R_0201 USB30_TX_C_N1 4 3 USB30_TX_R_N1 GND1
9 USB30_TX_N1 4 3
2

8
EXC24CH900U_4P GND2
2

EMC_NS@ AZ1143-04F-R7G_DFN2510P10E10

3
EMC@
RI4304 1 2 0_0402_5% @

A RI4305 1 2 0_0402_5% @ A
EMC
LI4303
USB30_RX_P1 1 2 USB30_RX_R_P1
9 USB30_RX_P1 1 2

USB30_RX_N1 4 3 USB30_RX_R_N1
9 USB30_RX_N1 4 3
EXC24CH900U_4P
EMC_NS@ Title
Security Classification LC Future Center Secret Data
RI4306 1 2 0_0402_5% @ Issued Date 2015/08/20 Deciphered Date 2016/08/20 USB3 PORT_LEFT
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday, December 06, 2019 Sheet 41 of 60
5 4 3 2 1
 A B C D E

USB2.0 PORT x1
+USB2_VCCA

+USB2_VCCA JUSB3
1
+5VALW +USB2_VCCA USB20_N9_R 2 VBUS
1
UI4302 USB20_P9_R 3 D- 1
D+

100U_1206_6.3V6M
5 1 4 5
IN OUT GND GND1

470P_0402_50V7K
1 1 6
GND2

CI4307

CI4308
CI4306 2 1 7
1U_10V_M_X5R_0201 GND GND3 8
4 3 USB_OC2# GND4
2 ENB OCB USB_OC2# 4 2 ALLTO_C107G1-10803-L
SY6288D20AAC_SOT23-5 2 ME@
@

USB_ON#
41,44 USB_ON# Low Active 2A

+5VALW

RI4307 2 @ 1 100K_0201_5% USB_ON#

USB20_N9_R

El
+USB2_VCCA USB20_P9_R

2
RI4308 1 @ 2 0_0402_5%

1
1
LI4304
USB20_P9 4 3 USB20_P9_R DI4306
9 USB20_P9 4 3

et
DI4305 AZC199-02S.R7G_SOT23-3
USB20_N9 USB20_N9_R

2
1 2 EMC@
9 USB20_N9 1 2

2
EXC24CH900U_4P AZ5725-01F.R7GR_DFN1006P2X2
EMC@ EMC_NS@

1
2 2

ro
RI4309 1 @ 2 0_0402_5%

EMC

-X
https://vinafix.com

Te
ch
3 3

ni
ca
l
4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 USB3 Port_Right & USB2.0
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday, December 06, 2019 Sheet 42 of 60
A B C D E
 5 4 3 2 1

+3VL_EC +3VL_EC +3VL_EC_R

+3VL VCC_LPC_ESPI
RE4402 1 2 0_5%_0603@ +1.8VALW

0.1U_6.3V_K_X5R_0201

1000P_50V_K_X7R_0201
1 1 +3VL +3VALW VCC_FSPI
RE4403 1 2 0_5%_0603 @ RE4404 1 2 0_0402_5% @ +3VS

CE4407

CE4408

0.1U_6.3V_K_X5R_0201
0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201
1 RE4405 1 2 0_0402_5% @
2 2 EC_FAN_SPEED

CE4409
1 1 1 1 1 1 RE4409 1 2 100K_0402_5%

0.1U_6.3V_K_X5R_0201
RE4406 1 @ 2 0_0402_5%
CPU_VR_READY

CE4401

CE4402

CE4403

CE4404

CE4405

CE4406
1 RE4410 1 2 10K_0402_5%
2

CE4410
RE4407 1 2 0_5%_0603@
2 2 2 2 2 2 RPE1
EC_SMB_DA0 1 4
2 EC_SMB_CK0 2 3
GPU/Thermal sensor
2.2K_0404_4P2R_5%
EC_AGND

+3VL_EC
D D

EC_SMB_DA3 RPE2
1 4
EC_SMB_CK3 2 3
PMIC
2.2K_0404_4P2R_5%

VCC_LPC_ESPI VCC_FSPI +3VL_EC RPE3

EC_SMB_CK1 1 4
+3VL_EC_R EC_SMB_DA1 2 3
Battery/Charger
2.2K_0404_4P2R_5%

UE4401
LID_SW#

114
121

106

127
RE4421 1 2 100K_0201_5%

11
26
50
92

74
IT8227E-CX_LQFP128_16X16
1 EC_ESPI_IO0
2 0_0201_5%@ 10 87 EC_SMB_CK0
RE4415

VSTBY1
VSTBY2
VSTBY3
VSTBY4
VSTBY5
VCC

AVCC
VFSPI

VSTBY(PLL)
7 ESPI_IO0 1 EC_ESPI_IO1
2 0_0201_5%@ 9 EIO0/LAD0/GPM0(3) SMCLK0/GPF2 88 EC_SMB_DA0 EC_SMB_CK0 26,39
RE4416 GPU/Thermal sensor
7 ESPI_IO1 1 EC_ESPI_IO2
2 0_0201_5%@ 8 EIO1/LAD1/GPM1(3) SMDAT0/GPF3 115 EC_SMB_CK1 EC_SMB_DA0 26,39 EC_USB_ON#
7 ESPI_IO2 RE4417 SM BUS EC_SMB_CK1 52,53 RE4424 2 1 100K_0201_5%
RE4418 1 EC_ESPI_IO3
2 0_0201_5%@ 7 EIO2/LAD2/GPM2(3) SMCLK1/GPC1 116 EC_SMB_DA1
7 ESPI_IO3 EC_ESPI_RST# 22 EIO3/LAD3/GPM3(3) SMDAT1/GPC2 117 PECI_EC 2 1 43_5%_0201 EC_SMB_DA1 52,53 Battery/Charger
RE4438 H_PECI 6
ON/OFF RE4426 1 2 100K_0402_5%
RE4419 1 EC_ESPI_CLK
2 0_0201_5%@ 13 ERST#/LPCRST#/GPD2 PECI/SMCLK2/GPF6(3) 118
7 ESPI_CLK EC_ESPI_CS# ESCK/LPCCLK/GPM4(3) SMDAT2/PECIRQT#/GPF7(3)
7 ESPI_CS# RE4420 1 2 0_0201_5%@ 6 NOVO# RE4428 2 1 100K_0402_5%
ECS#/LFRAME#/GPM5(3)
EC_ON_3VALW_R
RE4429 2 1 100K_0402_5%

El
EC_RTCRST#_ON 126
5 GA20/GPB5(3) 85 1 IT12
PLT_RST# 15 ALERT#/SERIRQ/GPM6(3) PS2CLK0/CEC/TMB0/GPF0 86 PBTN_OUT#
11,26,37,40,44 PLT_RST# LPC RE4436 1 2 0_0201_5%@
PBTN_OUT#_R 11
EC_SCI# 23 PLTRST#/ECSMI#/GPD4(3) PS2DAT0/TMB1/GPF1 89 3VALW_PCH_EN
6 EC_SCI# 14 ECSCI#/GPD3 PS/2 PS2CLK2/GPF4 90 EC_ON_1.8V 3VALW_PCH_EN 46
WRST#
4 WRST# PS2DAT2/GPF5 EC_ON_1.8V 55
KBRST#/GPB6(3)
IT8227E-CX PWM0/GPA0
24 PWR_LED#
PWR_LED1# PWR_LED# 45

LQFP128 25
BATT_LOW_LED# PWR_LED1# 30

et
PWM1/GPA1 28
BKOFF# 113 PWM2/GPA2 29 BATT_CHG_LED# BATT_LOW_LED# 45
33 BKOFF# LID_SW# 123 CRX0/GPC0 PWM3/GPA3 30 EC_FAN_PWM BATT_CHG_LED# 45
45 LID_SW# CTX0/TMA0/GPB2(3) CIR SMCLK5/PWM4/GPA4 31 PWR_LED2# EC_FAN_PWM 39
SMDAT5/PWM5/GPA5 PWR_LED2# 30

H_PROCHOT#_EC 80
PWM
RE4586 1 @ 2 0_0201_5% 119 DAC4/DCD0#/GPJ4(3) 47 EC_FAN_SPEED
55 VDDQ_PGOOD FP_PWR_EN_R DSR0#/GPG6 TACH0A/GPD6(3) PM_SLP_S4#_R EC_FAN_SPEED 39
C
45 FP_PWR_EN RE4585 1 2 0_0201_5%@ 33 48 RE4422 1 2 0_0201_5% @
PM_SLP_S4# 11 C
RE4430 1 @ 2 0_0402_5% GINT/CTS0#/GPD5 TACH1A/TMA1/GPD7(3) GPG1:Def:GPO-L

ro
11,26,37,44 PLT_RST# EC_ON_3VALW_R
RE4437 1 2 0_0201_5%@ 81 120
RESETN 45
1 2 0_0402_5% @ EC_ESPI_RST# 54 EC_ON DAC5/RIG0#/GPJ5(3) TMRI0/GPC4(3) 124 SUSP#
RE4432
7 ESPI_RST# EC_TX 17 TMRI1/GPC6(3) SUSP# 40,46
40 EC_TX EC_RX 16 TXD/SOUT0/LPCPD#/GPE6
40 EC_RX RXD/SIN0/PWUREQ#/BBO/SMCLK2ALT/GPC7(3)
+3VL_EC ADP_I 71 107 EC_VR_ON
53 ADP_I SYS_PWROK 72 ADC5/DCD1#/GPI5(3) GPE4 18 PM_SLP_S3#_R EC_VR_ON 56
11 SYS_PWROK UART port RE4444 1 2 0_0201_5% @
PM_SLP_S3# 11
PSYS 73 ADC6/DSR1#/GPI6(3) WAKE UP RI1#/GPD0(3) 21 EC_USB_ON# RE4443 1 2 0_0201_5% @
53,56 PSYS PCH_DPWROK_EC ADC7/CTS1#/GPI7(3) RI2#/GPD1 USB_ON# 41
11 PCH_DPWROK RE4431 2 1 1K_0201_5% 35
EC_VCCST_EN RTS1#/GPE5
1

34
46 EC_VCCST_EN CPU_VR_READY PWM7/RIG1#/GPA7
1

122 112

-X
RE4433 56 CPU_VR_READY EC_SMB_DA3 DTR1#/SBUSY/GPG1/ID7 RING#/PWRFAIL#/CK32KOUT/LPCRST#/GPB7 when mirror, GPG2 pull high
DE4401 100K_0402_5% 95 110 ON/OFF when no mirror, GPG2 pull low +3VL_EC
55 EC_SMB_DA3 EC_SMB_CK3 94 CTX1/SOUT1/GPH2/SMDAT3/ID2 PWRSW/GPB3 111 ON/OFF 30,45
RB521CS-30GT2RA_VMN2-2 PMIC
2

55 EC_SMB_CK3 CRX1/SIN1/SMCLK3/GPH1/ID1 GPB4 109

@ NOVO# GPG2 RE4434 1 2 100K_0402_5%
2

1 2 EC_SPI_CLK 105 GPB1 108 ACIN# NOVO# 30

7 SPI_CLK RE4445 49.9_1%_0201
WRST# RE4446 1 2 0_0201_5%@ EC_SPI_CS0# 101 FSCK GPB0 RE4435 1 @ 2 100K_0402_5%
26 WRST# 7 SPI_CS# EC_SPI_SI FSCE#
1U_6.3V_M_X5R_0201

1 RE4447 1 2 0_0201_5%@ 102 EXTERNAL SERIAL FLASH

https://vinafix.com
7 SPI_SI EC_SPI_SO FMOSI NTC_V1
CE4412

WRST# MIN 10us RE4449 1 2 0_0201_5%@ 103 66

7 SPI_SO FMISO ADC0/GPI0(3) 67 PM_SLP_S0#_R NTC_V1 39
RE4425 1 2 0_0201_5% @
PM_SLP_S0# 11
KSO16 56 ADC1/GPI1(3) 68 NTC_V2
2 57 KSO16/SMOSI/GPC3(3) ADC2/GPI2(3) 69 PM_SLP_SUS#_R NTC_V2 39
KSO17 RE4427 1 2 0_0201_5% @
PM_SLP_SUS# 11
EC_BEEP 32 KSO17/SMISO/GPC5(3) ADC3/GPI3(3) 70
30 EC_BEEP PWM6/SSCK/GPA6 ADC4/GPI4(3) GPIO_SCL 11

Te
GPG2 100 A/D D/A
PCH_ENBKL EC_ENBKL SSCE0#/GPG2
GPG0:Def:GPO-H 4,33 PCH_ENBKL RE4423 1 2 0_0402_5% @ 125 SPI ENABLE
SSCE1#/GPG0 76 EC_VCCST_PWRGD
KSO0 36 TACH2A/GPJ0 77 EC_MUTE# EC_VCCST_PWRGD 11
KSO1 37 KSO0/PD0 TACH2B/GPJ1 78 EC_TP_ON EC_MUTE# 30
KSO2 38 KSO1/PD1 DAC2/TACH0B/GPJ2(3) 79 ME_FLASH EC_TP_ON 45
KSO3 39 KSO2/PD2 DAC3/TACH1B/GPJ3(3) ME_FLASH 6
40 KSO3/PD3 EC_VCCST_EN
KSO4 RE4440 1 @ 2 100K_0402_5%
KSO5 41 KSO4/PD4
KSO6 42 KSO5/PD5 SUSP# RE4441 1 2 100K_0402_5%
KSO7 43 KSO6/PD6
KSO8 44 KSO7/PD7 BKOFF# RE4442 1 2 10K_0402_5%
KSI[0..7] KSO9 45 KSO8/ACK#
45 KSI[0..7] KSO9/BUSY

ch
KSO10 46
KSO[0..17] KSO11 51 KSO10/PE 2 BATT_TEMP EC_ON_1.8V RE4580 1 2 100K_0201_5%
45 KSO[0..17] 52 KSO11/ERR# GPJ7 128 AC_PRESENT BATT_TEMP 52,53
KSO12 CLOCK RE4450 1 2 0_0201_5%@
AC_PRESENT_R 11
53 KSO12/SLCT GPJ6 EC_VPP_PWREN
KSO13 RE4581 1 2 100K_0201_5%
KSO14 54 KSO13
KSO15 55 KSO14 84 EC_VPP_PWREN EC_VR_ON RE4582 1 2 100K_0201_5%
KSO15 KBMX EGCLK/GPE3 83 EC_VPP_PWREN 55
EGCS#/GPE2 82 VGA_AC_DET_EC GPIO_AL0 45 EC_USM
B RE4448 1 2 0_0201_5%@ RE4583 1 2 100K_0201_5% B
KSI0 58 EGAD/GPE1 VGA_AC_DET 26
KSI1 59 KSI0/STB# 3VALW_PCH_EN RE4584 1 2 100K_0201_5%
KSI2 60 KSI1/AFD# 19 NUM_LED#
61 KSI2/INIT# SMCLK4/L80HLAT/BAO/GPE0 20 EC_TS_ON NUM_LED# 45 GPIO_AL0
KSI3 RE4587 2 1 1/20W_49.9K_1%_0201
KSI4 62 KSI3/SLIN# SMDAT4/L80LLAT/GPE7 EC_TS_ON 33

ni
63 KSI4 GPIO 3 EC_USM PWR_LED1#
KSI5
EC_USM 54 RE4588 1 2 100K_0201_5% @
KSI6 64 KSI5 GPH7 99 PCH_PWROK
65 KSI6 ID6/GPH6 98 EC_SMI_R PCH_PWROK 11 PWR_LED2#
KSI7 RE4579 1 2 0_0201_5% @ RE4589 1 2 100K_0201_5% @
KSI7 ID5/GPH5 97 EC_SMI 6
ID4/GPH4 96 CAPS_LED# DELINK 45
VCORE

ID3/GPH3 93 EC_RSMRST#_EC CAPS_LED# 45

RE4452 1 2 1K_0201_5%
AVSS
VSS1
VSS2
VSS3
VSS4
VSS5

CLKRUN#/ID0/GPH0 EC_RSMRST# 11

ca
1
27
49
91
104

75

12

SA0000A8N00

CE4411 Emergency Power Loss Early De-assertion of DSW_PWROK control circuit

VCOREVCC 2 1

Vinafix.com
ALW_PWRGD EC_RSMRST#
54 +3VALW_PG RE4453 1 @ 2 0_0402_5% DE4402 1 2
EC_AGND 0.1U_6.3V_K_X5R_0201
RB521CS-30GT2RA_VMN2-2
1 2 0_0402_5% @ PCH_DPWROK
54,55 +5VALW_PG RE4454 DE4403 1 2

RB521CS-30GT2RA_VMN2-2

l
CPU_VR_READY CE4413 1 2 EMC_NS@ 0.1U_6.3V_K_X5R_0201
VDDQ_PGOOD CE4414 1 2 EMC_NS@ 0.01U_6.3V_K_X7R_0201
PM_SLP_S4# CE4415 1 2 EMC_NS@ 1000P_0201_50V7-K
+3VL
EC_RTC_RST# 10 PM_SLP_S3#
RE4455 1 2 0_0402_5% @ H_PROCHOT# 6,13,55 CE4416 1 2 EMC_NS@ 1000P_0201_50V7-K
53,56 VR_HOT#
1

Power side install NOVO# CE4417 1 2 0.1U_6.3V_K_X5R_0201

1

RE4456 1 QE4401
100K_0402_5% RE4457 CE4418 SSM3K15AMFV_2-1L1B PECI_EC CE4419 1 2 EMC_NS@ 47P_0201_25V8-J
EC_RTCRST#_ON 2
100_0402_5% 47P_0201_25V8-J
EMC_NS@ BATT_TEMP CE4420 1 2 EMC_NS@ 100P_0201_25V8J
2

ACIN# RE4458 1 2 0_0402_5% @ 2

1 2

RE4459 ACIN# CE4421 1 2 EMC_NS@ 100P_0201_25V8J

1

A 10K_0402_5% A
QE4402 ON/OFF CE4422 1 2 EMC_NS@ 1U_6.3V_M_X5R_0201
2

2 H_PROCHOT#_EC 2 PLT_RST#
CE4423 1 2 EMC_NS@ 220P_0201_25V7-K
ACIN 53
QE4403
SSM3K15AMFV_2-1L1B SSM3K15AMFV_2-1L1B
3

@ For ESD

Security Classification LC Future Center Secret Data Title

Issued Date 2017/09/01 Deciphered Date 2017/09/01 EC ITE8586LQFP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Docum ent Num ber Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Cus tom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Monday, December 30, 2019 Sheet 44 of 60
5 4 3 2 1
 5 4 3 2 1

K/B Connector PWR_CAPS_LED

RI4501 1 2 0_0402_5% @ 32
JKB1
33
+3VALW CAPS_LED# RI4502
CAPS_LED#_R 32 GND1
1 2 200_0402_1% 31 34
44 CAPS_LED# 30 31 GND2
KSO15
KSO10 29 30
KSO11 28 29
KSI[0..7] KSO14 27 28
KSI[0..7] 44 27
KSO13 26
KSO[0..17] KSO12 25 26
KSO[0..17] 44 25
KSO3 24
KSO6 23 24
KSO8 22 23
KSO7 21 22
KSO4 20 21
ON/OFF RI4503 1 2 0_0402_5% @ ON/OFFBTN# KSO2 19 20
30,44 ON/OFF 19
KSI0 18
KSO1 17 18
D
J4501 J4502 KSO5 16 17 D
1 16

2
CI4501 KSI3 15
0.1U_6.3V_K_X5R_0201 SHORT PADS SHORT PADS KSI2 14 15
@ @ @ KSO0 13 14

1
2 KSI5 12 13
KSI4 11 12
KSO9 10 11
KSI6
KSI7
9
8
10
9
TP/B Connector
KSI1 7 8
KSO16 6 7 JTP1 JTP2
KSO17 5 6 RI4507 1 2 0_0402_5% @ EC_TP_ON_R 1 EC_TP_ON_R 1
NUM_LED#_R 5 44 EC_TP_ON TP_INT# 1 TP_INT# 1
RI4504 1 1517@ 2 200_0402_1% 4 RI4508 1 2 0_0402_5% @ 2 2
44 NUM_LED# PWR_LED# 4 8 PCH_TP_INT# 2 2
RI4505 1 S145@ 2 200_0402_1% 3 3 3
ON/OFFBTN# RI4627 1 S145@ 2 0_0201_5% 2 3 PCH_I2C1_SDA_TP 4 3 4 3
2 8 PCH_I2C1_SDA_TP PCH_I2C1_SCL_TP 4 4
RI4628 1 S145@ 2 0_0201_5% 1 5 5
1 8 PCH_I2C1_SCL_TP 6 5 PCH_I2C1_SDA_TP 6 5
1 1 TP_PWR 6 PCH_I2C1_SCL_TP 6
HIGHS_FC8AR321-3160-1H 7
CI4507 7
KSO15 RI4623 1 S350@ 2 0_0201_5% KSO15_R ME@ CI4506 100P_0402_50V8J 7 TP_PWR
8
KSI1 RI4624 1 S350@ 2 0_0201_5% KSI1_R 100P_0402_50V8J EMC_NS@ 8 GND1 8
EMC_NS@ 2 2 GND2 9
GND1

El
HIGHS_FC5AF061-2931H 10
ME@ GND2
HIGHS_FC5AF081-2931H
ME@
CAPS_LED#_R NUM_LED#_R PWR_LED# ON/OFFBTN# PWR_CAPS_LED

+3VS TP_PWR PCH_I2C1_SCL_TP

AZ5123-01F.R7GR_DFN1006P2X2

AZ5123-01F.R7GR_DFN1006P2X2

AZ5123-01F.R7GR_DFN1006P2X2
PCH_I2C1_SDA_TP

AZ5123-01F.R7GR_DFN1006P2X2
1
RI4506 1 2 0_0402_5% @
1

3
et
100P_0402_50V8J

EMC@

DI4504

100P_0402_50V8J
2

1
EMC@

EMC_NS@

1517@

EMC_15_NS@
100P_0201_25V8J

EMC_NS@

EMC_NS@

CI4505
2 2 DI4505
1

1
DI4501

CI4503

CI4504

DI4503

1
DI4502

CI4502 EMC_NS@
1 0.1U_6.3V_K_X5R_0201
1 1
2 2
2

C C
2

ro
AZC199-02S.R7G_SOT23-3

1
For EMC

-X
+3VS_FP
44 BATT_LOW_LED#
BATT_LOW_LED# LED1 1 2 RI4509 1 2 470_0402_5% +3VALW Finger Print Connector

1
L-C192JFCT-LCFC_SUPER_AMBER

https://vinafix.com
1

RI4622
330_0402_1%
1

D4501
AZ5123-01F.R7GR_DFN1006P2X2

1 2
Te
EMC_NS@ +3VL +3VS_FP
+3VL QI4501
2

LP2301ALT1G_SOT23-3
FP@
2

1
FP_PWR_EN# 2 QI4502
1
3 1 CI4508

D
RI3803
1/20W_200K_5%_0201 1 0.1u_0201_10V6K SSM3K15AMFV_2-1L1B

3
BATT_CHG_LED# LED2 1 2 RI4510 1 2 470_0402_5% FP@ CI4510 FP@ FP@
44 BATT_CHG_LED# +3VALW 1 2
0.047U_0402_25V_X7R_0402 CI4511

G
2

2
L-C192WDT-LCFC_WHITE FP@ 0.1u_0201_10V6K
1

RI4525 1 2 0_0201_5% @ 2 @
2 +3VS_FP

ch
1

1
0_0201_5% 1 @ 2 RI4619 FP_PWR_EN
D4502 GPIO_AL0
RI4621 RI4521 2 @ 1 1/20W_4.7K_5%_0201
AZ5725-01F.R7GR_DFN1006P2X2
100K_0201_5%
EMC_NS@ GPIO_SCL
FP@ 1 RI4522 2 @ 1 1/20W_4.7K_5%_0201
2

CI4509

2
FP_PWR_EN# 0.1u_0201_10V6K RI4523 2 @ 1 1/20W_4.7K_5%_0201 FPR_RESET
2

B B
@

1
QI3802 2

FPR_RESET RI4524 1 @ 2 1/20W_4.7K_5%_0201

ni
44 FP_PWR_EN 2
PWR_LED# LED3 1 2 RI4511 1 2 470_0402_5% DELINK_R RI4618 1 @ 2 100K_0201_5%
44 PWR_LED# +3VALW

1
SSM3K15AMFV_2-1L1B

3
L-C192WDT-LCFC_WHITE RI3806 FP@
1

100K_0201_5%
FP@
1

2
D4503

ca
AZ5725-01F.R7GR_DFN1006P2X2 +3VS_FP JFP1
EMC_NS@ 10
GND2
2

9
GND1
2

RI4513 1 2 0_0402_5% @ 8
USB20_N7_CONN 7 8
LI4501 USB20_P7_CONN 6 7
USB20_N7 1 2 USB20_N7_CONN RI4620 1 @ 2 0_0201_5% 5 6
9 USB20_N7 1 2 8 FPR_DELINK DELINK_R 5
44 DELINK RI4515 1 2 0_0201_5% @ 4
DELINK GPIO_AL0 RI4516 1 2 GPIO_AL0_R 3 4
0_0201_5% @
44 GPIO_AL0 3

l
USB20_P7 4 3 USB20_P7_CONN RESETN RI4517 1 @ 2 0_0201_5% FPR_RESET 2
9 USB20_P7 4 3 44 RESETN 2
1
HALL Sensor EXC24CH900U_4P
EMC_NS@
44
8 FPR_RESET
GPIO_SCL
GPIO_SCL RI4518 1 2 0_0201_5% @ GPIO_SCL_R 1
HIGHS_FC5AF081-2931H
ME@
RI4514 1 2 0_0402_5% @
+3VL
US4501 USB20_N7_CONN +3VS_FP
@
+VCC_LID

AZ5515-02FPR7GR_DFN1006P3X

AZ5725-01F.R7GR_DFN1006P2X2
RS4501 1 2 0_0402_5% 2 DI4508
VCC DELINK_R 10 1 DELINK_R USB20_P7_CONN
2 NC1 Line-1
CS4501 3 RS4502 1 @ 2 0_0402_5% LID_SW# GPIO_AL0_R 9 2 GPIO_AL0_R
OUTPUT LID_SW# 44 NC2 Line-2

1
.01U_0402_16V7-K
1 FPR_RESET FPR_RESET

EMC_FP@

EMC_NS@
@ 1 2 7 4

1
GND NC3 Line-3

DI4506

DI4507
A CS4502 A
AH9247-W-7_SC59-3 100P_0402_50V8J GPIO_SCL_R 6 5 GPIO_SCL_R
EMC_NS@ NC4 Line-4
1 3
GND1

2
8

2
GND2
AZ1143-04F-R7G_DFN2510P10E10
EMC_FP@

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 KB/TP_CONN.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Tuesday, December 10, 2019 Sheet 45 of 60
5 4 3 2 1
 A B C D E

+3VALW to PCH
+3VALW

PJ4602
1
1 2
2
+3VALW_PCH
Load Switch +3VS, C173 --> 2.74ms
CX4601
1 JUMP_43X39 +5VALW To +5VS +5VS, C176 --> 2.03ms
@
1U_6.3V_M_X5R_0201
@ UX4608
+3VALW To +3VS VIN 5V and 3.3V (VBIAS=5V), IMAX(per channel)=6A, Rds=16mohm
2 1 14 +5VS
IN1_1 OUT1_2 +5VALW
Need Short
2 13 1
1 IN1_2 OUT1_1 CX4607 G2898KD1U_TDFN14P_2X3 J12 @
1
3 12 CX4622 1 2 1800P_25V_K_X7R_0201 0.1U_6.3V_K_X5R_0201 1 14 +5VS_LS 1 2
44 3VALW_PCH_EN EN1 CT1 2 IN1_1 OUT1_2 13 1 2
@
VBIAS 4 11 2 IN1_2 OUT1_1 JUMP_43X79
@ 1 1
VBIAS GND

0.01U_0402_25V7K
C4624
1 C177 C3916 5VSON 3 12 C176 1 2 1 1
5 10 CX4623 1 2 1000P_50V_K_X7R_0201 1U_0402_6.3V6K .01U_0402_16V7-K EN1 CT1 1000P_0201_50V7-K C174 C3917
EN2 CT2 EMC@ 4 11 0.1u_0201_10V6K 0.01U_0201_10V6K
+5VALW VBIAS GND

1
@ 6 9 @ 2 2 @ EMC@
2 RX4633 7 IN2_1 OUT2_2 8 +3VALW 3VSON 5 10 C173 1 2 2 2
IN2_2 OUT2_1 EN2 CT2 +3VS
0_0201_5% 2200P_0402_25V7-K
@ 15 6 9 J11 @
Thermal Pad 7 IN2_1 OUT2_2 8 +3VS_LS 1 2
1

2
TPS22976DPUR_WSON_2X3 C178 IN2_2 OUT2_1 1 2
@ 1U_0402_6.3V6K 15 JUMP_43X79

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K
@ Thermal Pad
Need Short

C175

C4625

C4626
2 U13 1 1 1

RX4632 1 2 0_0201_5% VBIAS

+3VALW @
2 2@ 2@

El
+1.8VALW to +1.8VS

et
+1.8VALW +1.8VS

RX4601 1 @ 2 1/2W_0.01_+-1%_0603_50PPM/C +5VL

@
QX4601 SUSP# R64 1 2 0_0402_5% 3VSON
0.6A 40,44,46 SUSP#

1
S

3 1 LP2301ALT1G_SOT23-3
RX4630
0.1U_6.3V_K_X5R_0201

2 100K_0402_5% 2
CX4602

RX4603
10K_0402_5%

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

ro
G
2
2

CX4603

CX4604

CX4605

1 1 1 1 @

2
SUSP R27 1 2 0_0402_5% 5VSON
SUSP 34
1 1
2 2 2 2

1
@

D C180 C179
1

@ @ 2 1U_0402_6.3V6K 1U_0402_6.3V6K
40,44,46 SUSP# 2 2
@ G QX4606
SUSP RX4604 1 2 0_0402_5% L2N7002KWT1G_SOT323-3

-X
S

3
1

1 CX4609
RX4606
0.1U_6.3V_K_X5R_0201
470K_0402_5%
@
2

https://vinafix.com
2

Te
+VCCST_CPU +VCCSTG_CPU

VCCST&VCCSTG

ch
RX4614 1 2 0_0402_5% @

+3VALW +3VALW +3VALW VccSTG and VccST are

merged and gated by
SLP_S4#
2

3 1 3
RX4619 RX4618 CX4619
100K_0201_5% 100K_0201_5% 0.1U_6.3V_K_X5R_0201

UX4605 2

ni
1

3V3_VCCST_OVERRIDE 1 5
INB VCC
2
INA
6

3 4 PM_SLP_VCCST_OVRD RX4622 1 2 0_0201_5% @

GND OUT Y
PM_SLP_VCCST_OVRD_R
D1

D2

2 5 MC74VHC1G32DFT1G_SOT353-5
11 VCCST_OVERRIDE G1 G2
1

+VCC1.05_OUT_FET

ca
RX4625 +3VALW
S1

S2

OR Gate 200K_0402_5%
QX4602A QX4602B @ 1
1

PJT7838_SOT363-6 PJT7838_SOT363-6 1 CX4618

2

CX4620 +3VALW 10U 6.3V M X5R 0402

0.1U_6.3V_K_X5R_0201 +VCCST_CPU_LS +VCCST_CPU
2
2
EC_VCCST_EN +VCCST_EN 1
RX4621 1 2 0_0402_5% @ UX4606 UX4604
44 EC_VCCST_EN 1 5 2 4
CX4617 RX4620 1 2 0_0402_5% @
INB VCC VIN VOUT

l
1U_6.3V_M_X5R_0201
+3VALW 2 2 5 3
INA VBIAS NC If VCCST is enabled by SLP_S4#, no power
3 4 VCCST_EN_R RX4624 1 2 0_0201_5% @ VCCST_EN 6 1 gate is required for VCCPLL_OC and it can
GND OUT Y ON GND be merged with VDDQ directly.
1 If VCCST is enabled by SLP_S3#, a power
CX4621 MC74VHC1G32DFT1G_SOT353-5 EM5201BJ-45_SOT23-6
gate is required for VCCPLL_OC.
UX4607 0.1U_6.3V_K_X5R_0201 OR Gate
1 5
55 VCCIN_AUX_VID0 INB VCC 2 PM_SLP_VCCST_OVRD RX4623 1 @ 2 0_0201_5%
2
55 VCCIN_AUX_VID1 INA

1
3 4 VCCIN_AUX_VALID RX4628 1 2 0_0201_5% @ VCCIN_AUX_VCCST_R
GND OUT Y RX4627
1

MC74VHC1G32DFT1G_SOT353-5 200K_0402_5%
OR Gate

2
4 RX4629 4
200K_0402_5%
@
2

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20

DC V TO VS INTERFACE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Tuesday, December 10, 2019 Sheet 46 of 60
A B C D E
 5 4 3 2 1

PJ5101 @ PJ5102 @
JUMP_43X79 JUMP_43X79
1 2 1 2
1 2 1 2 VIN
3.25A HCB2012KF-121T50_0805
JDCIN1 PF5101 PL5101
1 ADPIN 1 2 APDIN_F 1 2
1 2
GND1 EMC@
3 7A_24VDC_F1206HI7000V024TM
GND2 4

470P_0201_50V7-K

1000P_0201_50V7-K
GND3 5 @ HCB2012KF-121T50_0805

1000P_0201_50V7-K

470P_0201_50V7-K
GND4

EMC@

EMC@
6 PL5102

PC5101

PC5102
GND5

2
EMC@

EMC@
D 7 1 2 D

PC5103

PC5104
GND6
EMC_NS@
HIGHS_PJSS0026-8B01H

1
ME@

change symbol to DC021508142 by amy 0704

+3VL

El
2
PR5101
@ 0_0402_5%

et
VCCRTC 1

PR5102
C C
45.3K_0402_1%

ro
@ RTC_VCC
2

1
JRTC1
3 2 PR5103 1 1
2 1

-X
PD5101 1K_0603_5% 3 2
GND1
2

BAT54CW_SOT323-3 4
PC5105 GND2
1U_0402_6.3V6K
1

https://vinafix.com
HIGHS_WS33020-S0351-HF
@ ME@
change symbol to SP021510283 by amy 0620

Te
RTC_VCC 20MIL
+3VL 20MIL
VCCRTC 20MIL

ch
B B

ni
ca
l
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/07/10 Deciphered Date 2018/07/10 PWR-DCIN / RTC charger

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARYPROPERTYOF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAYNOT BE TRANSFERED FROMTHE CUSTODYOF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BYLC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAYBE USED BYOR DISCLOSED TO ANYTHIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday, December 06, 2019 Sheet 51 of 60
5 4 3 2 1
 5 4 3 2 1

SUYIN_125022HB008M202ZL VBAT EMC@

D
JBATT1 10A HCB2012KF-121T50_0805
BATT+
D

1 PL5201
1 2 1 2
9 2 3 EC_SMCA PR5201 1 2100_0402_1%
10 GND1
GND2
3
4
4 EC_SMDA 1 2
EC_SMB_CK1
EC_SMB_DA1
44,53
44,53
1 2 2S1P polymer battery
5 PR5202 100_0402_1%
5 6 PL5202 voltage level: +5.5V ~
6
7
7 HCB2012KF-121T50_0805 8.8 V

3
8 EMC@
8

1
PC5201 PC5202
ME@ 1000P_0201_50V7-K 0.01U_0201_25V6-K
EMC@ EMC@

2
VBAT
JBATT2

El
PD5201
1 AZC199-02S.R7G_SOT23-3
1 2 EMC_NS@

1
2 3 EC_SMCA
9 3 4 EC_SMDA
10 GND1 4 5
GND2 5 6

et
6 7
7 8
8 PR5203
1 2
+3VALW
100K_0402_1%
HIGHSTAR_WS33081-S120S-1H
C C
ME@ PR5204

ro
1 2
BATT_TEMP 44,53
10K_0402_5%

1
1

-X
PD5202
AZ5215-01F_DFN1006P2E2
EMC_NS@
2

https://vinafix.com
2

Te
ch
B B

ni
ca
l
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/07/10 Deciphered Date 2018/07/10 PWR-BATTERY CONN/OTP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday, December 06, 2019 Sheet 52 of 60
5 4 3 2 1
 5 4 3 2 1

VIN
PQ100 PQ101
AONS32314_DFN8-5 AONR32340C_DFN8-5 N2
N1
PR100
1 1 0.01_1206_1%
2 2 S1 5 V9B+
5 3 3 S2 D 1 4
S3

G
2 3
D D

470P_0201_50V7-K

220P_0402_50V7K

470P_0402_50V7K

680P_0402_50V7K

4700P_0402_50V7-K

6800P_0402_25V7-K
10U_25V_M_X5R_0603

10U_25V_M_X5R_0603
0.022U_0402_25V7K

0.01U_0201_25V6-K
4

EMC_NS@

EMC_NS@
PC100
2 2

1
EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@
PC102

PC103

PC104

PC105

PC106

PC107

PC108

PC109
1

PC101
PR101

2
4.7_0603_5% 1 1

5
0.1U_0201_25V6-K

2
PQ102
PC110
AON6324_DFN8-5
1 2
@
BQ24780_BATDRV 1 2 BQ24780_BATDRV_R 4

2
09/09 NC MEC part
PC111 PC112 PR102
0.1U_0201_25V6-K 0.1U_0201_25V6-K 0_0402_5%

3
2
1
2
PR103
499K_0402_1% PC113
0.01U_0201_25V6-K

1
VIN BATT+

2
El
BAT54CW_SOT323-3
PD100
2

3
V9B+

et
4.02K_0603_1%
VIN

1
1

1
4.02K_0603_1%

10U_0805_25V6K

10U_0805_25V6K
0.1U_0201_25V6-K
EMC_NS@
ACN
ACP
PR105

PR106

1
10_1206_5%

PC114

PC115

PC116
2
1

PR104
BQ24780_VDD
2

2
2

5
C PR107 0.47U_25V_K_X5R_0603 PU100 C

ro
7.15K_0402_1% 44.2K_0402_1%

ACP

ACN
PC117
1 2 PC118

1
PR108 2 1 780_VCC 28 24 1 2

2
VCC REGN PQ103
1 2 ACDET 6 2.2U_10V_K_X5R_0603 4
PC119 ACDET PR109 PC120 AON7380_DFN8-5
0.01U_0402_25V7K 25 BST_CHG 1 2 2 1
BTST PR110
2.2_0603_5% 0.047U_0603_16V7K PL100 0.01_1206_1% 6A

3
2
1
DH_CHG
BATT+

-X
3 26 2.2UH_PCMB063T-2R2MS_8A_20%
CMSRC HIDRV 1 2 CHG 1 4
@

5
PR111 2 1 20K_0402_1% 4
ACDRV

1
@ 2 3
PR112 2 1100K_0402_1% 27 LX_CHG PR113

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
BQ24780_VDD PHASE
@ 2.2_0805_5%

https://vinafix.com

1
PR114 1 2 0_0402_5% ACIN_R 5 PQ104

PC122

PC121

PC123

PC124
44 ACIN ACOK EMC_NS@
@ 4

2
PR115 1 2 0_0402_5% EC_SMB_DA1_R 11 AON7380_DFN8-5

2
44,52 EC_SMB_DA1 SDA 23 DL_CHG

470P_0201_25V7K
Te
LODRV

1
@

2
PR116 1 2 0_0402_5% EC_SMB_CK1_R 12 22 PC126

PC125

3
2
1
44,52 EC_SMB_CK1 SCL GND 1000P_0402_50V7K

2
@ BQ24780SRUYR_QFN28_4X4 EMC_NS@

1
PR117 1 2 0_0402_5% ADP_I_R 7 29 @

0.1U_0201_25V6-K

0.1U_0201_25V6-K
44 ADP_I IADP PAD

2
8 18 BQ24780_BATDRV

PC127

PC128
IDCHG
IDCHG BATDRV
9 PR118 10_0603_5%

1
44,56 PSYS PMON 17 2 1
BATSRC
20K_0402_1%
100P_0201_25V8J

100P_0201_25V8J

100P_0201_25V8J
2

PR121 @ 20 SRP_R 2 1 SRP

ch

0.1U_0201_25V6-K
SRP
2

1 2 0_0402_5% 10 10_0603_5%
PR119

PC131

44,56 VR_HOT# PR120

PC129

PROCHOT#

2
PC130

PC132
1

13
1

CMPIN
@
1

1
14

BATPRES#
TB_STAT#
CMPOUT 19 SRN_R 2 1 SRN
B
ILIM 21 SRN PR122 10_0603_5% B
ILIM
2

ni
16

15
PR123
0_0402_5% @
09/19 PR331 change from 147K to 133K
PR124 PR125
1

1 2 ILIM_R 1 2 TB_STAT#
+3VALW BATT_TEMP 44,52
30K_0402_1%
133K_0402_1%
0.01U_0201_25V6-K

ca
2

PC133

PR126
100K_0402_1%
1

ACDECT setting 17.2V

l
Charge current limit HW=7A
DC discharge limit =26A
Discharge current limit HW=9A during Turbo boost

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/07/10 Deciphered Date 2018/07/10 PWR-CHARGER

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday, December 06, 2019 Sheet 53 of 1
5 4 3 2 1
 5 4 3 2 1

+3VALW
D D

1
PR5924
100K_0201_5%
@
PJ401
PU1101

2
2 1 +3VALW_VIN 2 7 +3VALW_PG
V9B+ +3VALW_BST +3VALW_PG 44

0.1U_0402_25V6
2 1 IN1 PG

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603
3 1 1 2PC1115

EMC_NS@
1 1 IN2 BS

1
4

PC1101
JUMP_43X79 IN3 .1U_0603_25V7K

PC1102

PC1103
@ 5

2
2 2 6 LX1 15 PL1101
PJ402
14 GND1 LX2 16 +3VALW_LX 1 2 +3VALW_P 1 2
GND2 LX3 1 2 +3VALW

1
17
PR1103 GND3 PR1102 2.2UH_PCMB063T-2R2MS_8A_20% JUMP_43X118

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
100K_0402_5% 2.2_0805_5%
1 2 PR1109 1
@ 2 0_0402_5% +3VALW_EN PR1106 9 11 +3VALW_P @
44 EC_ON +3VALW_VIN 1 2 8 EN1 OUT EMC_NS@ 1 1 1 1 1 1

PC1105

PC1106

PC1107

PC1108

PC1120

PC1121
1 2
10 +3VALW_FBEN2

@
@ 2 0_0402_5% +5VALW_EN
PR1105 1

0.1U_0402_25V6
10K_0201_1% FF

1
12 PC1114 2 2 2 2 2 2
100mA

PC1116
TEST

1
13 1000P_0402_50V7K
+3VLP

2
LDO
PR1104 PR1107 EMC_NS@
3VALW:

2
1/16W_82K_1%_0402 1/20W_1M_1%_0201 1

El
SY8386BRHC_QFN16_2P5X2P5
PC1112 TDC=6A
2

2
1
2 4.7U_0603_6.3V6K 1 2 1 2
@ @
OCP=8A
PQ9710
PC1111 PR1108
OVP=120%
2
1000P_0402_25V7-K 1K_0402_1% Fsw=600KHz
44 EC_USM SSM3K15AMFV_2-1L1B
3

et
+3VLP +3VL
PJ9919
C C
1 2
1 2
JUMP_43X39

ro
@

+5VLP +5VL
PJ9717
1 2
1 2
JUMP_43X39

-X
@ +3VALW

1
PR1605
100K_0402_5%

https://vinafix.com
V9B+

2
@ PU1601
PJ405
2 1 +5V_VIN 2 7 +5VALW_PG
+5VALW_PG 44,55
0.1U_0402_25V6

2 1 IN1 PG
10U_25V_M_X5R_0603

10U_25V_M_X5R_0603

Te
3 1 +5VBS 1 2
EMC_NS@

1 1 IN2 BS +5VALW
1

4 PC1605
PC1601

JUMP_43X79 IN3 0.1U_0603_25V7K PJ406

PC1602

PC1603

SY8388CRHC_QFN16_2P5X2P5
5 +5VLX PL1601 1 2 1.5UH_PCMB063T-1R5MS_10A_20% +5VALW_P 1 2 8A
2

LX1 1 2

1
2 2 15
LX2 16 PR1608 JUMP_43X118

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
6 LX3 2.2_0805_5%
14 GND1 @
17 GND2 EMC_NS@ 1 1 1 1 1 1

PC1610

PC1611

PC1612

PC1613

PC1615

PC1614
1 2
GND3 11 +5VALW_P
OUT
10 PC1608 2 2 2 2 2 2
+5VALW_EN 9 FF 1000P_0402_50V7K
5VALW:

2
+5V_VIN 1 2 8 EN1 12
EN2 LDO +5VLP EMC_NS@

ch
PR1603
TDC=8A
0.1U_0402_10V7K

4.7U_0603_6.3V6M
13 +5VVCC 100mA
PC1604

10K_0402_1% VCC
1

1 1 OCP=12A
1

1M_0402_5%

PC1606
PC1607 @ @
OVP=120%
PR1604

B @ 4.7U_0603_6.3V6K B
1M_0402_5%
2

PR1602

2 2
Fsw=600KHz
2

PC1609
2

+5VFB 1 2 1 2
PR1609
1000P_25V_K_X7R_0402 1K_0402_1%

ni
ca
l
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 PWR_3VALW/5VALW

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Docum ent Num ber Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Cus tom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S350 ADA
Date: Friday, December 06, 2019 Sheet 54 of 44
5 4 3 2 1
 5 4 3 2 1

@
P_LV5116A_EN
PR9800 1 2 0_0402_5%
44,54 +5VALW_PG
@
VTT_EN
5 CPU_DRAMPG_CNTL PR9801 1 2 0_0402_5%

@
+1.8VALW_EN
PR9802 1 2 0_0402_5%
44 EC_ON_1.8V V9B+
@
VDDQ_VPP_EN
PR9803 1 2 0_0402_5%
44 EC_VPP_PWREN

2
D
+5VL D
PR9804
2.2_0603_5%

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K
1 P_LV5116A_VCC_30 P_LV5116A_VSY S_10

1
2

2
PC9800

PC9801

PC9802

PC9803
2
PR9806 1
+5VALW 2.2_0603_5% PC9805

1
1U_0402_10V6K PC9804
@ @ @ @ 1 0.1U_25V_K_X7R_0402 +3VALW
2 PJ9807 @
2 1 2 1
2
2 1 1A

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
PR9808
2.2_0603_5% PC9806 JUMP_43X39
1U_0402_10V6K
1 PU9800
1 1
6

PC9807

PC9808
36 VSYS @
VCC
P_LV5116A_PVCC_30 4 27 P_+1.8VALW_VIN_S 2 2 +1.8VALW
PVCC V1P8A_IN
P_VDDQ_UG_30 1
PR9810 @ VDDQ_HG 25 P_+1.8VALW_LX_S 1 2 +1.8VALW_P 1 2 4A
1 2P_VDDQ_BST_R_30 1 2 P_VDDQ_BST_30 40 V1P8A_PH1 1 2

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
VDDQ_BOOT

1
26 PL9800 PJ9803
PC9892 0_0603_5% V1P8A_PH2 2 1 PR9812 1UH_PCMB053T-1R0MS_7A_20% JUMP_43X79
P_VDDQ_LX_30 2 29 +1.8VALW_P +3VALW
0.1U_25V_K_X5R_0402 JUMP_43X39 4.7_0603_5%
VDDQ_PH V1P8A_SNS PC9816 PJ9808 @ 1 1 1 1
@
P_VDDQ_LX_SENS_10 P_VDDQ_VPP_IN 1A EMC_NS@
39 9 10U 6.3V M X5R 0402 2 1

1 2
VDDQ_SWSNS VPP_IN 2 1
P_VDDQ_LG_30 3 8 P_VDDQ_VPP +VDDQ_OUT

PC9809

PC9812

PC9810

PC9811
VDDQ_LG VPP PC9814 2 2 2 2
@
13 P_VTT_IN_30 1A 2 1 1200P_50V_K_X7R_0402

2
P_VDDQ_SENS_10 12 VT T _IN 2 1
2 1 VDDQ_SNS 14 P_VDDQ_VTT EMC_NS@
PJ9809

El
PC9893 @ VT T 2 1 JUMP_43X39 @ +0.6VS
0.1U_25V_K_X7R_0402 15
P_VCCIN_AUX_EN_10 23 VT T _SNS PC9894
AUX_DRVEN
P_LV5116A_DDR_ID_10
10U 6.3V M X5R 0402
P_VDDQ_VTT 1 2 1A
28 1 2

10U 6.3V M X5R 0402

P_VCCIN_AUX_PWM_10 21 DDR_ID 1 PJ9805
AUX_PWM 20 P_LV5116A_AUX_CS_10
PR9816 1 2 300K_0402_1%

PC9817
JUMP_43X39
AUX_CS
5 P_LV5116A_VDDQ_CS_10
PR9817 1 2 1/16W_240K_1%_0402 +3VALW +3VALW
@
P_VCCIN_AUX_LXSENS_10 22 VDDQ_CS 2
@
P_VCCIN_AUX_VCCSENSE_10 AUX_SWSNS
PR9818 1 2 0_0402_5% +VCCIN_AUX OCP=41A
13 VCCIN_AUX_VCCSENSE P_VCCIN_AUX_VCCSENSE_10 19 P_LV5116A_V1P8A_CTRL_10

2
24 +2.5V_DDR
AUX_SNS V1P8A_CT RL
2
PC9818
P_LV5116A_AUX_SET_10 +VDDQ OCP=13A

et
1000P_0402_50V7K 30 PR9828 PR9829
C @
1
P_VCCIN_AUX_VSSSENSE_10
@ AUX_SET 100K_0402_5% 100K_0402_5%
P_VDDQ_VPP 1 2 1A C
PR9819 1 2 0_0402_5% 6,13,44 H_PROCHOT# PR9820 1 2 0_0402_5% P_LV5116A_PROCHOT# 7 1 2
13 VCCIN_AUX_VSSSENSE VCCIN_AUX_VID0

22UC_6.3VC_MC_X5RC_0603
PROCHOT # 16 PJ9802
P_VCCIN_AUX_PG_1011 AUX_VID0 VCCIN_AUX_VID0 13,46
PR9821 1 2 100K_0402_5% JUMP_43X39
+3VALW PG_ARAIL VCCIN_AUX_VID1
17
PR9823 1 2 100K_0402_5% VDDQ_PGOOD 10 AUX_VID1 VCCIN_AUX_VID1 13,46 @

10U 6.3V M X5R 0402

+3VALW PG_DDR P_LV5116A_CLK_5

2
33 PR9824 1 2 0_0402_5%

PC9813
44 VDDQ_PGOOD @ EC_SMB_CK3 44 1 1
SCL

PC9815
34 P_LV5116A_DAT_5
PR9825 1 @ 2 0_0402_5% PR9833 PR9834
P_LV5116A_EN SDA EC_SMB_DA3 44
38 10K_0402_5% 10K_0402_5%
@ PM IC_EN @ @ 2 2

1
1 2 PR9827 P_LV5116A_DIGITAL_CTL_10 37

ro
0_0402_5% @
DIGIT AL_CT RL P_VCCIN_AUX_VSSSENSE_10
10K_0402_5% 1 2 PR9826 18
+5VL +1.8VALW_EN 35 AUX_RGND +5VALW +5VALW +5VALW
SLP_SUS#
VDDQ_VPP_EN 32 41
DIGITAL_CTRL Control Mode

100K_0402_5%

100K_0402_5%
SLP_S4# GND

2
AUX_VID1 AUX_VID0 Vout_AUX

10K_0402_5%
VTT_EN 31

PR9830

PR9831

PR9832
DDR_VT T _CT RL
High HW Control
0 0 0V

1
P_LV5116A_DDR_ID_10
Low SW Control LV5116AGQW_WQFN40_5X5 @
P_LV5116A_V1P8A_CTRL_10
@
P_LV5116A_AUX_SET_10 0 1 1.1V

-X

2
P_VCCIN_AUX_VIN_S V9B+ 1 0 1.65V

0_0402_5%

10K_0402_5%

10K_0402_5%
PR9835

PR9836

PR9837
AUX_SET VCCIN_AUX Internal RAMP
PJ9806
1 1 1.8V
1 2 3A High RAMP1

1
1 2 @ @
10U_25V_M_X5R_0603

10U_25V_M_X5R_0603
0.1U_0201_25V6-K

P_VCCIN_AUX_BST_R_30 JUMP_43X79
Low RAMP2 DDR_ID Type VPP VDDQ VTT/VDDQTX

https://vinafix.com
EMC@

@
P_VCCIN_AUX_BST_30

PC9820

PC9821

PC9822

+5VALW 1 1
1

PR9839 @
5

1 2 1 2
Floating RAMP3 Low DDR4 2.5V 1.2V VDDQ/2(VTT)
PQ9800
2

PC9819 0_0603_5% AON6380_DFN8-5 2 2

--
2

0.22U_25V_K_X5R_0402 Floating LPDDR4 1.8V 1.1V

Te
PR9840
P_VCCIN_AUX_UG_30
4
2.2_0603_5% DIGITAL_CTRL V1P8A_CTRL V1P8A Sequence V9B+
PU9801
4
1 High LPDDR4X 1.8V 1.1V 0.6V(VDDQTX)
+VCCIN_AUX
2200P_0402_50V7K

P_VCCIN_AUX_VCC_30 BOOT
1

8
@

High Low V1P8A follow PMIC_EN

PC9824

VCC 3 P_VCCIN_AUX_UG_30
1.5A
3
2
1

P_VCCIN_AUX_PWM_10 5 UGAT E 2 PJ9810

1U_0402_10V6K

PWM 2 P_VCCIN_AUX_LX_S 1 2 P_VDDQ_VIN_S 1 2

High High V1P8A follow SLP_SUS#

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603
0.1U_25V_K_X7R_0402
P_VCCIN_AUX_EN_10
1

1 PHASE 1 2
PC9823

PL9801
P_VCCIN_AUX_LG_30

330U_D2_2.5VY_R9M
EN 7

5
0.22UH_CMMS063T-R22MS2R107_26A_20% 1
6 LGAT E JUMP_43X79
Low Low V1P8A follow PMIC_EN PQ9801

PC9828

PC9827
1 1 1

D
2

GND1
1

B 9 + @ B

EMC_NS@
PC9825

PC9826
AONR32340C_DFN8-5
GND2
2

PR9842 PJ9800
5

RT9610CGQW_WDFN8_2X2
PQ9802
2.2_0805_5% JUMPER
2
Low High V1P8A follow I2C P_VDDQ_UG_30 4 2 2 2
EMC_NS@ @
1

G
AON6324_DFN8-5
2

S3
S2
S1
place close to VCCIN_ALX LMOS drain

ch
+VDDQ_OUT +1.2V
1

4
8A

3
2
1
PC9829
PL9802
1000P_0201_50V7-K PJ9804
2

P_VCCIN_AUX_LXSENS_10 P_VDDQ_LX_30 1 2 1 2
Rdson=2.8mohm@Vth=4.5V EMC_NS@ 1 2
PQ9803
3
2
1

0.47UH_PCMB053T-R47MS_13A_20% JUMP_43X118

5
AON7380_DFN8-5
@

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
2

2
PJ9801 1 1 1 1 1 1

PC9830

PC9831

PC9832

PC9833

PC9834

PC9835
+VCCIN_AUX VCCIN_AUX Vout CAP Config Vboot=1.8V Loadline=6mΩ 4.7_0603_5%
PR9844
JUMPER
P_VDDQ_LG_30 @

1
4
AC+DC Ripple=(-10%~+5%)*VOUT EMC_NS@ 2 2 2 2 2 2
#1:Pure MLCC 22U/0603*20pcs

1
TDC=14A Iccmax=32A Rdson=10.5mohm@Vth=4.5V
place close to VDDQ LMOS drain

1
ni
#2:POSCAP+MLCC 330U/9mohm*1pcs+22U/0603*7pcs CURRENT LIMIT=45A @ @

3
2
1
PC9851
1200P_50V_K_X7R_0402
Max Overshoot:2.13v/500us

2
EMC_NS@
OVP=(1.2~1.3)*Vref P_VDDQ_LX_SENS_10 P_VDDQ_SENS_10
22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

UVP=(0.45~0.55)*Vref
1

1
PC9836

PC9837

PC9838

PC9839

PC9840

PC9841

PC9842

PC9843

PC9844

PC9845

PC9846

PC9847

PC9848

PC9849

PC9850

Fsw=600Khz
2

ca
@ @ @ @ @ @ @
22U_0603_6.3V6-M

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
1

1
PC9863

PC9858

PC9864

PC9866

PC9871

PC9853

PC9854

PC9855

PC9856
PC9859

PC9860

PC9861

PC9862
2

l
A A
@
@ @ @ @
@ @ @ @ @ @ @ @

1 1 1 1 1 1 1 1 1 1 1
1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201
PC9872

PC9875

PC9877

PC9880

PC9881

PC9882

PC9883

PC9884

PC9885

PC9886

PC9887

2 2 2 2 2 2 2 2 2 2 2 Title
Security Classification LC Future Center Secret Data
Issued Date 2015/08/20 Deciphered Date 2016/08/20 PWR PMIC-LV5116
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
@ @ @ @ @ DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS D 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday, December 06, 2019 Sheet 55 of 2
5 4 3 2 1
 5 4 3 2 1

+5VALW +5VALW
+3VS

4.7_0603_5%
2

2.2_0603_5%
PR3400

PR3401
1

1
D @ D

1K_0402_1%
4.7U_0402_6.3V6M

2.2U_0402_6.3V6M

PR3403
PR3402

2
54.9_0402_1% @

PC3400

PC3401
PU3400

2
RT3612EBGQW-02_WQFN32_4X4 V9B+
P_VCCIN_PVCC_20 29
PVCC VR_HOT
2
VR_HOT# 44,53 CPU_VIN
+VCCST_CPU +VCCST_CPU 8A
PL9902
P_VCCIN_VCC_20 10 24 1 2
VCC VR_RDY CPU_VR_READY 44
HCB2012KF-121T50_0805

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603

33U_D2_25VM_R40M
0.1U_0201_25V6-K
1
PR3405 @ 1

1K_0402_1%
P_VCCIN_BST1_R_30
0_0402_5%

PR3404
1 1 1
1U_0402_6.3V6K

1/16W_45.3_1%_0402

VR_PSY S PL9901

1
1 @ 2 9 +

PC3403

PC3404

PC3405

PC3448
44,53 PSY S PSYS P_VCCIN_BST1_301
1

1 2 25 2 1 2 1 2
PC3402

PC3485
2 PR3409 1

2 PR3410 1

PR3448 BOOT 1 PC3406 HCB2012KF-121T50_0805

100_0402_1%

110_0402_1%

2
0_0402_5% PR3406 0.22U_0603_25V7K 2 2 2 2
PR3407

+VCCIN
2

@ @ @ 2.2_0603_5% EMC@
P_VCCIN_EN_10 P_VCCIN_UG1_30
PR3411 1 2 23 26 1 4 PQ3400 @
44 EC_VR_ON VRON UGAT E1
0_0402_5% AON6380_DFN8-5 @
20A Vboot=1.8V Loadline= 2mohm

2200P_0402_50V7K
2

2 1

@
PC3407
0.22UH_CMMS063T-R22MS2R107_26A_20%
PC9895 @
P_VCCIN_PH1_S Ripple=30mV(0A~1A)

330U_D2_2.5VY_R9M
@ 0.1U_25V_K_X7R_0402 27 2 2 1 1

5 3
2
1
VR_SVID_DAT_R PHASE1
PR3408 1 2 0_0402_5% 4
12 VR_SVID_DAT VDIO Ripple=30mV(1A~5A)

PC3418
PL3400 +
PR3412
Ripple=15mV(5A~TDC)

AON6324_DFN8-5

AON6324_DFN8-5
P_VCCIN_LG1_30

2
@ 28 2.2_0805_5% PJ3402 PJ3403
VR_SVID_ALRT#_R LGAT E1 2
PR3413 1 2 0_0402_5% 3 EMC_NS@ JUMPER JUMPER
12 VR_SVID_ALRT# ALERT PR3415
TDC=39A Iccmax=70A

PQ3401

PQ3402
@ @

1
4 P_VCCIN_LG1_30 4
0_0402_5% PR3416 1
@ @ 4.22K_0402_1%
OCP=112A
VR_SVID_CLK_R
PR3414 1 2 0_0402_5% 5 1 2 1 2 PC3408
12 VR_SVID_CLK VCLK
1200P_50V_K_X7R_0402
Max Overshoot:200mv/500us
P_VCCIN_ISEN1P_10 2 EMC_NS@
CPU_VIN 20 PR3417 1 21/16W_1.15K_1%_0402
OVP=VID+400mV

El

3
2
1

3
2
1
ISEN1P
1 2 @
1 2 P_VCCIN_VIN_10 22 PC3409 0.1U_0402_25V7-K
P_VCCIN_ISEN1P_R_10
CPU_VIN UVP=VID-150mV
VIN 19 P_VCCIN_ISEN1N_10 1 2 P_VCCIN_ISEN1N_R_10
2.2_0402_1%
Fsw=600 Khz

0.1U_0402_25V7-K
ISEN1N

1
PR3418 PR3419

PC3411
680_0402_1% PC3410
0.1U_0402_25V7-K

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603
2

0.1U_0201_25V6-K
2 1 1 1
P_VCCIN_BST2_R_30

1
RT3612EB_VREF

PC3412

PC3413

PC3414

PC3453
5
1 2 1 2 12 1 P_VCCIN_BST2_301 2 1 2PC3416 PQ3403
VREF06 BOOT 2

2
PR3421 AON6380_DFN8-5 2 2 2

et
0.47U_0402_25V-K PR3420 2.2_0603_5% 0.22U_0603_25V7K EMC@
C RT3612EB_VREF PC3415 3.9_0402_1% C
P_VCCIN_IMON_NTC_10 32 P_VCCIN_UG2_30
1 4 @ +VCCIN
UGAT E2

2200P_0402_50V7K
@
13.7K_0402_1% 0.22UH_CMMS063T-R22MS2R107_26A_20%

PC3445
RT3612EB_VREF 1 2 1 2 P_VCCIN_IMON_R_10 1 P_VCCIN_IMON_10
PR3423 2 11
PR3422 @ IM ON 31 P_VCCIN_PH2_S 2 2 1 20A

5 3
2
1
14K_0402_1% PH3400 PHASE2

330U_D2_2.5VY_R9M
5

1
@ 100K_0402_1%_NCP15WF104F03RC PL3401 1
1 2 PR3425

AON6324_DFN8-5

AON6324_DFN8-5
24.9K_0402_1% 1/16W_86.6K_1%_0402

P_VCCIN_LG2_30

2
PR3424 30 2.2_0805_5% PJ3400 PJ3401 +

PC3417
LGAT E2
1

22.1K_0402_1% EMC_NS@ JUMPER JUMPER

PQ3404

PQ3405
1.33K_0402_1%

34K_0402_1%

ro
PR3426

PR3427

PR3428

@ P_VCCIN_SET1_10 P_VCCIN_LG2_30 4 @ @

1
8 PR3429 PR3430 4 1 2
@ SET 1 0_0402_5% 4.22K_0402_1%
1 @ 2 1 2 PC3419
2

P_VCCIN_ISEN2P_10 1200P_50V_K_X7R_0402
17 PR3431 1 21/16W_1.15K_1%_0402 2 EMC_NS@

3
2
1

3
2
1
ISEN2P
P_VCCIN_SET2_10 @
1/16W_1.18K_1%_0402

7 1 2 PC3420
SET 2 P_VCCIN_ISEN2P_R_10
1

0.1U_0402_25V7-K
18 P_VCCIN_ISEN2N_10 1 2 P_VCCIN_ISEN2N_R_10
PR3432

1/16W_28.7K_1%_0402

ISEN2N
1

2
PR3434

@ @ PR3433 PC3421
680_0402_1% 0.1U_0402_25V7-K
2

1
1

-X

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
P_VCCIN_SET3_10 6 14
PR3436
2

SET 3 VSEN
1

1
180P_25V_J_NPO_0402
150_0402_1%
PR3437

PC3426

PC3427

PC3428

PC3429

PC3430

PC3431

PC3432

PC3433

PC3434

PC3435

PC3436

PC3437

PC3438

PC3439

PC3440

PC3441

PC3442

PC3443
PC3422
1

PC3423 1 2 100P_0402_50V8J 1 2
1/16W_29.4_1%_0402

2
RT3612EB_VREF 15 P_VCCIN_COMP_10
PR3438

@ 110K_0402_1% COM P 1 2 1 2
VCCIN_SENSE 12
2

2P_VCCIN_TSEN_R_10 P_VCCIN_TSEN_10
1

1 2 PR3442 1 21 PR3439 PR3440

1/16W_374_1%_0402

T SEN
PR3443

PR3441 1/16W_28K_1%_0402 1/16W_8.45K_1%_0402

https://vinafix.com
P_VCCIN_FB_10 @ @ @ @ @ @ @ @ @ @
2

2
19.6K_0402_1% 16 1 2 1 2
FB @
PH3401 @ PR3444 PC3425 @ PC3424
2 1 16.9K_0402_1% 470P_0402_50V7K 1000P_0402_50V7K
2

1
100K_0402_1%_NCP15WF104F03RC 33 13
GND RGND VSSIN_SENSE 12
Place close to MOSFET 34+8；

Te
1

PR3445
14K_0402_1%

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
1

1
PC3447

PC3452

PC3458

PC3460

PC3461

PC3462

PC3463
2

PC3444

PC3446

PC3449

PC3450

PC3451

PC3455

PC3457
1

2
PR3449
1/16W_237_1%_0402 @
B @ @ @ @ @ @ @ B
@ @ @ @ @ @
2

ch
1 1 1 1 1 1 1 1 1 1 1

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201
PC3464

PC3465

PC3466

PC3467

PC3468

PC3469

PC3473

PC3476

PC3477

PC3478

PC3479
2 2 2 2 2 2 2 2 2 2 2

@ @ @ @ @ @ @

ni
ca
l
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 PWR-CPU_CORE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS D 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday, December 06, 2019 Sheet 56 of 3
5 4 3 2 1
 A B C D

V9B+
PJ9902 @
1.5A 2 1 PC9902

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603
2 1 PR9900 0.1U_0603_25V7-M
+1.35V_BST 1 2+1.35V_BST_R 1 2
JUMP_43X79 1 1

PC9900

PC9901
OPT@ 10_0603_5% OPT@
PD9900
OPT@ +1.35VGS
2 2

18
PU9900

5
1 2 PL9900
PJ9901
0.68UH_PCMB063T-R68MS_16A_20%
8A

VBOOT
AGND
LRB751V-40T1G_SOD323-2 +1.35V_VIN 12 3 +1.35V_LX 1 2 +1.35V_P 2 1

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
VIN4 SW_1 2 1
OPT_NS@ OPT@ OPT@
+1.35V_EN
OPT@ JUMP_43X118
1 23 FBVDDQ_PWR_EN 1 2 16 4 1 1 1 1 1 1 1
EN4 SW_2

PC9905

PC9906

PC9907

PC9908

PC9909

PC9910
PR9901 @

1
100K_0402_5% 1 2 PC9903 OPT@ PC9904 OPTNS@
15 +1.35V_FB 1 2
OPT@ 0.022U_0402_25V7K
FB
PR9902
25 2.2_0603_5% 2 2 2 2 2 2

1
NC_3 0.1U_0402_25V6 EMC_OPTNS@

OPTNS@

OPTNS@
23

OPT@

OPT@

OPT@

OPT@
PR9903

2
22 NC_2

+1.35V_SN
1K_0402_1%
NC_1
OPT@

1
6

2
PGND_1
+5VALW

1
7 PR9904
2 1 PC9911 24 PGND_2 PC9912 +1.35V_FB_1 42.2K_0402_1%
VCC_SW 8
1U_0402_6.3V6K 1000P_0402_50V7K OPT@

2
PGND_3
OPT@ EMC_OPTNS@ PC9913
PR9905 0_0402_5% 9 560P_0402_50V7-K
1.8VGS_PWR_EN 1 2 MAIN_PWR_EN 19 PGND_4
OPT@
Vout=1.35V±5%

2
23,26 1.8VGS_PWR_EN +3.3V_1.8V_AON EN2 10
@
PGND_5 Vset=1.36V±2%

2
PC9914 1 2 PC9915 21 11 +1.35V_FB
0.1U_0402_25V6 1U_0402_6.3V6K VIN2 PGND_6 OCP>12A
0.5A

1
PJ9907
OPT_NS@ OPT_NS@ +3V_1.8VGS
Vref=0.6V

1
20 +3V_1.8VGS_R 2 1
VOUT2 @ 2 1 0.5A PR9907
OVP=(1.25~1.35)*Vref

El
PXS_PWR_EN_R 28 1 2 31.6K_0402_1%
23 PXS_PWR_EN_R EN3 JUMP_43X39
PC9917 OPT@
UVP=(0.7~0.8)*Vref

2
+3.3V_1.8V_AON_IN PJ9906
PC9916 1U_0402_6.3V6K OPT@ +3.3V_1.8V_AON
2 0.1U_0402_25V6 1 26 +3.3V_1.8V_AON_R 2 1
OPT_NS@
VIN3_1 VOUT3_1 @ 2 1 Fsw=700Khz
2 27 1A
1A LSW1 RDS=36~50mohm,Io=0.5A
1

VIN3_2 VOUT3_2 JUMP_43X39

1
29 PC9918
PC9919 VIN3_3
1U_0402_6.3V6K
LSW2 RDS=18~25mohm,Io=1A

PGOOD
TH_ALT
OPT@

et
1U_0402_6.3V6K LSW3 RDS=5~7mohm,Io=3.5A

2
VCC
OPT_NS@

14

17

13
+1.35V_VCC
2

1
2 2

ro
PR9908 PR9909
100K_0402_1% 100K_0402_1%
OPT_NS@ OPT_NS@

2
1
PC9920
1U_0402_6.3V6K

2
OPT@

-X
https://vinafix.com
+3.3V_1.8V_AON_IN
+3VS
PR9910

Te
2 1
0_0402_5%
+1.8VALW OPTN16@
PR9911
2 1
0_0402_5%
OPTN17@

ch
3
+3VALW 3

+3VALW

ni
1

2
PC9921 PR9912 +1.0VGS
1U_0402_6.3V6K 100K_0402_5%
+1.8VALW

2
OPT@ PJ9905
1A

1
PU9901 +1.0V_P 2 1
1A

1/20W_100K_1%_02011/20W_24.9K_1%_0201
PJ9908 6 7 @ 2 1
2 1 +1.0VGS_VIN 5 VCNTL POK
Vout=1.0V±5%

ca

220P_0402_50V7K
4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

2
2 1 VIN 3 JUMP_43X39

22U_0603_6.3V6-M

22U_0603_6.3V6-M
1
VOUT1

PR9913

PC9924
4 @
1

JUMP_43X39 VOUT2
PC9922

PC9923

1
@ 9 EN 2 OPT@

GND

2
EPAD FB

PC9925

PC9926
2

1
@

2
+1.0V_FB

1
@ OPT@
APL5930CKAI-TRG_SO8 @ OPT@

1
OPT@

l
PR9915
PR9916 1 2 0_0402_5% @ 1.0VGS_EN OPT@

2
23 PXE_VDD_EN_R

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/15 Deciphered Date 2013/08/15 PWR-VGA-PMIC

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday, December 06, 2019 Sheet 57 of 5
A B C D
 5 4 3 2 1

PWM-VID Specification
N17 Config N16 Config B RT8816 PSI UP1666 PSI Phase Configuration
Vmin(V) 0.3 0.6 1.6V~5.5V 1.6~5.5V 2Phase CCM
Vmax(V) 1.3 1.2 1.08~1.35V 1~1.4V 2Phase DEM
Vboot(V) 0.8 0.9 0.7~0.88V 0.4V~0.8V 1Phase CCM
Vstep(mV) 6.25 6.25 0~0.4V 0~0.2V 1Phase DEM
N(level) 160 96
Fpwm(KHz) 675 1.125 V9B+
Tdmin(nS) 9.26 9.26 +VGA_CORE_VIN PJ7000
D 1 2 D
T(uS) <100 <100 1 2 4A
JUMP_43X79
+5VALW @

1U_25V_K_X5R_0402
0.1U_0201_25V6-K
1 1 1

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603
EMC_OPTNS@

1
PC7000

PC7001

PC7002

PC7003
2
PQ7000

1
OPT@ 2 2 2

5
PR7000 AON6380_DFN8-5
PU7000
2_0603_5%
OPT@ @
OPT@ OPT@

2
NVVDD_PVCC 18
PVCC 2 NVVDD_HG1 4
UGATE1

1
+3.3V_1.8V_AON PC7004 PR7003
PC7005
1U_0402_6.3V6K 2.2_0603_5% 0.22U_0603_25V7K
1 NVVDD_BS1 1 2 1 2
OPT@ OPT@

3
2
1
BOOT1
1

21 OPT@
PR7001 GND
5.1K_0402_1%
PL7000 +VGA_CORE
20 NVVDD_PH1 NVVDD_PH1 1 2
OPT@ PHASE1

EMC_OPTNS@
2

1
El
@ PQ7001 0.22UH_PCMB063T-R22MS_23A_20%

1/8W_1_5%_0805
PR70021 2 0_0402_5% NVVDD_PSI_R 4 AON6324_DFN8-5

PR7004
26 PSI_VGA PSI OPT@ 1

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
330U_D2_2V_Y
PR7005 OPT@ PR7006OPTNS@ 1 1 1 1 1 1
1 2 1 2 +

PC7007

PC7009

PC7010

PC7011

PC7012

PC7013

PC7014
+3VS

2
1K_0402_1% 5.1K_0402_1% 19 NVVDD_LG1 4
13 LGATE1
PGOOD 1
8,23 DGPU_PWROK 2 2 2 2 2 2 2
OPT@
PR7007 OPT@

2200P_0402_50V7K
EMC_OPTNS@
PC7008
1 2 NVVDD_EN_R 3
23 NVVDD_EN

3
2
1
EN 2

et
PD7000 OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
OPT@
1

C 1/16W_23.2K_1%_0402 PC7015 C
1 2 0.1U_0402_10V7K +VGA_CORE_VIN V9B+
OPT@ PJ7001
2

1 2
1 2
RB521CM-30T2R_VMN2M-2 PQ7003 1 2 4A

5
PR70081 2 0_0402_5% NVVDD_VID_R 5 14 NVVDD_HG2 AON6380_DFN8-5

1U_25V_K_X5R_0402
26 NVVDD_PWM_VID VID UGATE2 JUMP_43X79
OPT@

0.1U_0201_25V6-K
10U_25V_M_X5R_0603

10U_25V_M_X5R_0603
1 1 1
1

1
@ OPTNS@ PR7009 @

ro

PC7018

PC7019

PC7020

PC7021
PC7017
PC7016 2.2_0603_5%
0.1U_0402_10V7K 15 NVVDD_BS2 1 2 1 2
2

2
BOOT2 4 2 2 2
OPT@ 0.22U_0603_25V7K +VGA_CORE
OPT@ PL7001 @
09/08 change 1U to 0.1uh OPT@ OPT@

EMC_OPTNS@
3
2
1
16 NVVDD_PH2 NVVDD_PH2 1 2
2 1 NVVDD_VREF 8 PHASE2

EMC_OPTNS@
1
VREF PQ7004

1/8W_1_5%_0805
-X
0.22UH_PCMB063T-R22MS_23A_20% 1

5
AON6324_DFN8-5

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
330U_D2_2V_Y
PC7022 1 1

PR7010
OPT@
1

0.1U_0402_25V7-K +

PC7023

PC7024

PC7025
PR7011 OPT@
OPT@ 20.5K_0402_1%

2
2 2 2
OPTNS@ NVVDD_LG2
17 4

https://vinafix.com
1
2

LGATE2

OPT@

OPT@
2200P_0402_50V7K

OPT@
PC7026

EMC_OPTNS@
1
NVVDD_REFIN 7
REFIN PR7012 2
2

3
2
1
30K_0402_1% PR7015

Te
1

PR7014 UPI_OPT@ 100_0402_1%

PR7013 82.5K_0402_1% 1 2

2
16.5K_0402_1% UPI_OPT@
OPTNS@ PR7016
PR7017 OPT@
1

6.19K_0402_1%
Vboot=0.8V
2

1 2 1 2 NVVDD_VIDBUF 6 @
1

REFADJ 10 NVVDD_FBRTN PR7018 1 2 0_0402_5%

PC7027 OPTNS@ RGND NVVDD_VSS_SENSE 22 Ripple=±20mV
0.01U_0402_25V7K 4.32K_0402_1%
1

B B
OPTNS@ OPTNS@ TDC=28.5A Iccmax=55A OCP>75A
2

PR7019 PC7028
309_0402_1% 4700P_0402_25V7-K 11 NVVDD_FB
VSNS VR Remote Sense - Tie to GPU sense points TDC=30A Iccmax=60.1A OCP>80A
OPTNS@ OPTNS@
2

1
PC7029

ch
PR7020 Vref=2V
2

1000P_0402_25V7-K
2 1NVVDD_FS 9 12 NVVDD_SS
OPTNS@ FUVP:Vfb=0.2V

2
TON OCSET/SS @
V9B+ 475K_0402_1% PR7021 1 2 0_0402_5%
SUVP:Vcomp=3V
PR7022 RT_OPT@
COMP---UPI NVVDD_VCC_SENSE 22

2 1 PR7023
OVP:Vfb=2V
100_0402_1%
2.2_0603_5% 1 2 +VGA_CORE
Fsw=320KHz
UP1666QQKF_WQFN20_3X3
RT_OPT@
1

UPI_OPTNS@
1

PC7030 OPTNS@ OPT@

PR7025 RT_OPT@
1

1000P_0402_25V7-K

ni
1U_0402_25V6-K
2

51K_0402_1%
1000P_0402_25V7-K
PC7031

RT_OPT@ PR7024
2

110K_0402_1%
2

UPI_OPT@
PC7032

PR7026

100K_0402_1%
UPI_OPT@
2

PR7027
2

0_0402_5%
2
2

NVVDD_FBRTN PC7033
1 2
1000P_0402_25V7-K
UPI_OPT@ UPI_OPT@ RT_OPTNS@
1

PR820,PR819,PC849 set TON for RT8816

ca
2

PR7028
0_0402_5%
RT_OPT@ PR833,PR834 set FS/OC for UP1666
1

PR833=82.5,PR834=100k, OCP=85A
PR821 set OC and PC837 set external SS for RT8816
PR832,PC834,PR836 set COMP for UP1666

l
A A
PR816,PR812,PR815,PR813,PR818,PC826 BOM structure control for N16 or N17
Component Value N17 N16
R1(KΩ) PR7017 6.19 20
R2(KΩ) PR7011 20.5 20
R3(KΩ) PR7016 4.32 2 UPI_OPT@ : for UP1666 Title
Security Classification LC Future Center Secret Data
R4(KΩ) PR7013 16.5 18
RT_OPT@ : for RT8816A Issued Date 2015/08/20 Deciphered Date 2016/08/20 PWR-VGA_CORE
R5(KΩ) PR7019 0.309 0
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Docum ent Num ber Rev
C(nF) PC7028 4.7 2.7 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Cus tom GS44D/GS54D 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, December 06, 2019 Sheet 58 of 4
5 4 3 2 1
 5 4 3 2 1

+3.3V_1.8V_AON
X76
GPU FB Memory (GDDR5) RAMCFG[4:0] STRAP2 STRAP1 STRAP0

2
RV2901 RV2902 RV2903 Samsung 8Gb K4G80325FB-HC28 0(0x0000) L L L
100K_0402_5% 100K_0402_5% 100K_0402_5%
@ @ @
8Gb Micron 8Gb MT51J256M32HF-70:A 1(0x0001) L L H

1
D D

25 STRAP0 STRAP0
STRAP1 Hynix 8Gb H5GC8H24MJR-R0C 2(0x0010) L H L
25 STRAP1
25 STRAP2 STRAP2

2
RV2904 RV2905 RV2906
100K_0402_5% 100K_0402_5% 100K_0402_5%
@ @ @
1

El
+3.3V_1.8V_AON
STRAP5 STRAP4 STRAP3 SMB_ALT_ADDR DEVID_SEL PCIE_CFG VGA_DEVICE

et
L L L 0 0 0 0
2

2
RV2907 RV2908 RV2909
100K_0402_5% 100K_0402_5% 100K_0402_5% 1: SMB_ALT_ADDR ENABLE
@ @ @
C 0: SMB_ALT_ADDR DISABLE C
1

ro
1: DEVID_SEL REBRAND
25 STRAP3 STRAP3
STRAP4 0: DEVID_SEL ORIGNAL
25 STRAP4
25 STRAP5 STRAP5

1: PCIE_CFG LOW POWER

2

-X
0: PCIE_CFG HIGH POWER
RV2910 RV2911 RV2912
100K_0402_5% 100K_0402_5% 100K_0402_5%
@ @ @ 1: VGA_DEVICE ENABLE
1

https://vinafix.com
0: VGA_DEVICE DISABLE

Te
Strap5 is NC pin on N16

ch
DEVID_SEL
0 (Default)
B B
1

ni
+3V_1.8VGS +3.3V_1.8V_AON PCIE_CFG
ROM_SO ROM_SI ROM_SCLK SOR_EXPOSED[3:0] 1:ENABLE 0:DISABLE 0 (Default)
2
2

RV2914
RV2913
0_0402_5%
0_0402_5% 0000 SOR0/1/2/3 DISABLE 1
OPTN17@ N17S-G1 H H M
OPTN16@

ca
1
1

N16S-GTR SMBUS_ALT_ADDR
2

RV2915 RV2916 RV2917 0 0x9E (Default)

100K_0402_5% 100K_0402_5% 100K_0402_5%
@ @ @
1 0x9C (Multi-GPU usage)
1

l
ROM_SI VGA_DEVICE
25 ROM_SI ROM_SO
25 ROM_SO ROM_SCLK
25 ROM_SCLK 0 3D Device (Class Code 302h)
2

RV2918 RV2919 RV2920 1 VGA Device (Default)

100K_0402_5% 100K_0402_5% 100K_0402_5%
@ @ @
1

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 GPU_MISC

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday, December 06, 2019 Sheet 29 of 60
5 4 3 2 1
 D

0.1
Rev

60
of
14
GS44D/GS54D
Sheet
Friday, December 06, 2019
1

1
Document Name
S740-ICL
Title

Date:
Size
C
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
2018/08/20

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
l LC Future Center Secret Data
ca
Deciphered Date
ni
2

2
https://vinafix.com

ch

2018/12/04
Te

Security Classification
Issued Date
-X
3

3
12P_50V_F_COG_0402

+1.8VALW_PCH
CC1443 EMC_NS@
ro
1

2
3x0402 (holder）back Outer row
6x1uF 0402 Back ,Outer row
2x10uF 0402 back Outer row

2x22uF 0603 (SODIMM need)

et
12P_50V_F_COG_0402
CC1442 EMC_NS@

2
1x0603(holder)

+3VALW_PCH
El
12P_50V_F_COG_0402
10U 6.3V M X5R 0402
CC1441 EMC_NS@
CC1423
@

2
1

2
VDDQ:

10U 6.3V M X5R 0402

CC1417
@
1

10U 6.3V M X5R 0402

CC1416
@
1

EMC CAPS refer CRB

10U 6.3V M X5R 0402 1U_6.3V_M_X5R_0201
CC1420 CC1427
@

@
1

2
10U 6.3V M X5R 0402 1U_6.3V_M_X5R_0201
CC1403 CC1431 12P_50V_F_COG_0402
@

@
CC1439 EMC_NS@
1

2
4

4
1

2
10U 6.3V M X5R 0402 1U_6.3V_M_X5R_0201

+VCCIN_AUX
CC1422 CC1412 100P_0402_50V8J
@

@
CC1438 EMC_NS@
1

2
10U 6.3V M X5R 0402 1U_6.3V_M_X5R_0201 1U_6.3V_M_X5R_0201
CC1421 CC1425 CC1433
@

@
1

2
10U 6.3V M X5R 0402 1U_6.3V_M_X5R_0201 1U_6.3V_M_X5R_0201
CC1404 CC1407 CC1408
@

@
1

2
10U 6.3V M X5R 0402 1U_6.3V_M_X5R_0201 1U_6.3V_M_X5R_0201

EMC CAPS refer CRB

CC1419 CC1411 CC1410 0.1U_6.3V_K_X5R_0201

@
CC1437 EMC_NS@
1

2
10U 6.3V M X5R 0402 10U 6.3V M X5R 0402 1U_6.3V_M_X5R_0201 1U_6.3V_M_X5R_0201
CC1406 CC1418 CC1424 CC1430

@
12P_50V_F_COG_0402
1

2
CC1436 EMC_NS@

2
10U 6.3V M X5R 0402 10U 6.3V M X5R 0402 1U_6.3V_M_X5R_0201 1U_6.3V_M_X5R_0201
CC1415 CC1413 CC1409 CC1429

@
100P_0402_50V8J
1

2
CC1435 EMC_NS@

+VCCIN

2
10U 6.3V M X5R 0402 10U 6.3V M X5R 0402 1U_6.3V_M_X5R_0201 1U_6.3V_M_X5R_0201
CC1405 CC1401 CC1434 CC1428

@
1

2
10U 6.3V M X5R 0402 1U_6.3V_M_X5R_0201 1U_6.3V_M_X5R_0201
10U 6.3V M X5R 0402 CC1402 CC1432 CC1426

@
CC1414

2
5

5
1

2
+1.2V

A
 5 4 3 2 1

POWER U42@ U42@ U42@ U42@ U42@ U42@ U42@ U42@

PR3423 PR3424 PR3422 PR3439 PR3426 PR3432 PR3434 PR3438

13.7K +-1% 0402 22.1K +-1% 0402 14K +-1% 0402 28K +-1% 0402 86.6K +-1% 0402 24.9K +-1% 0402 1.18K +-1% 0402 29.4 +-1% 0402
SD03413728J SD03422128J SD03414028J SD000015J00 SD00001PM00 SD03424928J SD00001DI00 SD00001BC00

U22@ U22@ U22@ U22@ U22@ U22@ U22@ U22@

D D
PR3423 PR3424 PR3422 PR3439 PR3426 PR3432 PR3434 PR3438

20.5K +-1% 0402 25.5K +-1% 0402 11.5K +-1% 24.3K +-1% 130K +-1% 0402 22.6K +-1% 0402 1.1K +-1% 0402 40.2 +-1% 0402
SD03420528J SD03425528J SD03411528J SD000011300 SD03413038J SD000019W00 SD03411018J SD034402A8J

El
et
C C

ro
-X
https://vinafix.com

Te
ch
B B

ni
ca
l
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/20 Deciphered Date 2016/08/20 POWER CHANGE LIST

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Tuesday, December 10, 2019 Sheet 59 of 62
5 4 3 2 1
 5 4 3 2 1

GPU
CPU RV2317 OPTN17@ RV2317 OPTN16@

UC1 1035G4@ UC1 1035G1@ UC1 1005G1@ UC1 1065G7@

D D
MP PN
MP PN MP PN MP PN 5.11_0805_1% 470_0805_5%
SD00001NQ00 SD00247008J

Intel i5-1035G4 1.1G/4C Intel i5-1035G1 1G/4C/6M Intel i3-1005G1 1.2G/2C/4M Intel i7-1065G7 1.3G/4C/8M
SA0000A4T20 SA0000A8W30 SA0000A9V10 SA0000A4U10

VRAM
DRAM_Samsung DRAM_Hynix DRAM_Micron

ZZZ1 SAM_DRAM@ ZZZ1 Hyn_DRAM@ ZZZ1 Mic_DRAM@

D4G SAM HYNIX D4G D4G MIC

El
X7648112001 X7648112002 X7648112003

SO_DIMM only

et
C C

ro
PCB_MB HDMI Royalty

-X
ZZZ
ZZZ ZZZ2 HDMI@

NM-D031 NM-D031 HDMI PN

https://vinafix.com

Te
DAZ1K000100 RO00000040J
DAZ1JZ00100
15@
14@

ch
B B

ni
ca
l
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 Virtual symbol

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Tuesday, December 10, 2019 Sheet 48 of 60
5 4 3 2 1
 5 4 3 2 1

PCB Fedical Mark PAD

FD4901 FD4902 FD4903 FD4904 FD4905 FD4906

1
D
MD Shielding D

SH4901 SH4902 SH4903 SH4904 SH4905 SH4906

CPU Thermal Hole
H4902 H4904 H4906 H4907
HOLEA HOLEA HOLEA HOLEA
1

1
1

1
PAD_CT7P0B6P0D3P2 PAD_CT7P0B6P0D3P2 PAD_CT7P0B6P0D3P2 PAD_CT7P0B6P0D3P2

El
SPRING_FINGER_6.2X1.64 SPRING_FINGER_6.2X1.64 SPRING_FINGER_6.2X1.64 SPRING_FINGER_6.2X1.64 SPRING_FINGER_6.2X1.64 SPRING_FINGER_6.2X1.64

GPU Thermal Hole

et
C
H4903 H4905 C
HOLEA HOLEA
1

ro
PAD_CT7P0B6P0D3P2 PAD_CT7P0B6P0D3P2
SODIMM Shielding

-X
SH4911
SH4907 SH4908 SH4909 SH4910

H4908
HOLEA
H4909
HOLEA
H4910
HOLEA
H4911
HOLEA
https://vinafix.com

Te 1

1
1

1
B B
PAD_C7P0D4P0 PAD_C7P0D4P0 PAD_O2P5X3P0D2P5X3P0N PAD_O2P5X3P0D2P5X3P0N

ch
H4912 H4913 H4914 H4901 SHIELDING_SUL-35A2M_9P2X3P3_1P SHIELDING_SUL-35A2M_9P2X3P3_1P SHIELDING_SUL-35A2M_9P2X3P3_1P SHIELDING_SUL-35A2M_9P2X3P3_1P SHIELDING_SUL-35A2M_9P2X3P3_1P
HOLEA HOLEA HOLEA HOLEA

ni
1

PAD_C7P0D2P8 PAD_C7P0D2P8 PAD_C7P0D2P8 PAD_C10P0D8P0

ca
H4915 H4916 H4917
HOLEA HOLEA HOLEA
1

l
A A
PAD_C7P0D2P4 PAD_CT7P0B10P0D4P0 PAD_CT7P0B10P0D4P0

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 Hole
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday, December 06, 2019 Sheet 49 of 60
5 4 3 2 1
 5 4 3 2 1

N16x GPIO

GPIO I/O ACTIVE Function Description Performance Mode P0 TDP and EDP-Continuous current (GDDR5)
GPIO0 OUT - GPU Core VDD PWM control signal
FBVDDQ Other
Min FBVDD (GPU+Mem) (1.05V)
GPIO1 OUT N/A FB Enable for GC6 2.0 GPU Mem Core Clk NVVDD (1.35V) (1.35V) (6) (3.3V)
Products (W) (W) (MHz) (V) (A) (W) (A) (W) (A) (W) (mA) (W) (mA) (W)
D GPIO2 OUT N/A D

N16S-GMR 16 1.6 849 TBD 19 TBD 2 TBD 4.2 TBD 800 TBD 60 TBD
GPIO3 OUT N/A
N16S-GTR 18 1.7 967 26.5 2 4.2 800 60
GPIO4 OUT N/A

GPIO5 OUT N/A GPU power sequencing---3V3_MAIN_EN

GPIO6 IN - GPU wake signal for GC6 2.0

GPIO7 OUT N/A

GPIO8 I/O - System side PCIe reset Monitor

GPIO9 I/O N/A 2.2K Pull-up

El
GPIO10 OUT FBVREF_ALTV for GDDR5

GPIO11 OUT - N16x Multi-level Straps

GPIO12 IN AC Power Detect Input (10K pull High)

et
Physical Logical Logical Logical Logical
GPIO13 OUT - Phase Shedding Strapping pin Power Rail Strapping Bit3 Strapping Bit2 Strapping Bit1 Strapping Bit0
ROM_SCLK +3VGS SOR3_EXPOSED SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED
GPIO14 IN N/A
ROM_SI +3VGS RAM_CFG[3] RAM_CFG[2] RAM_CFG[1] RAM_CFG[0]
C C

ro
GPIO15 IN N/A ROM_SO +3VGS DEVID_SEL PCIE_CFG SMB_ALT_ADDR VGA_DEVICE
STRAP0 +3VGS Reserved(keep pull-up and pull-down footprint and stuff 50Kohm pull-up)
GPIO16 N/A
STRAP1 +3VGS
GPIO17 IN N/A STRAP2 +3VGS
Reserved(keep pull-up and pull-down footprint and not stuff by default)
STRAP3 +3VGS

-X
GPIO18 IN N/A
STRAP4 +3VGS
GPIO19 IN N/A

https://vinafix.com
GPIO20 N/A

GPIO21 OUT GPU PCIe self-reset control

Te
OVERT OUT Active Low Thermal Catastrophic Over Temperature

ch
B B

ni
ca
l
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 VGA Notes List

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44D/GS54D
Date: Friday, December 06, 2019 Sheet 19 of 60
5 4 3 2 1