A B C D E

LCFC Confidential
1 1

L340-IRH +N17P-G0 MB Schematics Document

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co
Coffee Lake-R with DDR4 + Nvidia N17P-G0-K1-A1

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2 2

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2019-03-20

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REV:1.0
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3 3
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Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2018/09/20 Cover Page

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FG541/FG741
Date: Tuesday, March 26, 2019 Sheet 1 of 69
A B C D E
 A B C D E

LCFC confidential
Board name:NM-C362
MB P/N:DA800013U10
NV: N17P-G0-K1-A1 Intel CPU DDR4 SO-DIMM x1
Package: GB4C-128 Coffee Lake-H 30/35W Page 12
PCI-Express
Page 24~30 PCIe Port 1~4 16x Gen3 Memory Bus (Dual Channel)
BGA-1440 DDR4 Memory Down
1 1

VRAM: 256M*32 1.2V DDR4 2400MT/s

GDDR5*3: 3GB 42mm*28mm 4pcs x16 Page 13
Page 31~34
Page 5~11

DMI *4
1GB/s * 4 Total 4GB/s

USB3.0 x1 USB3.0 Left Conn

HDMI 2.0 (DDI 1) USB3.0 Port1
HDMI Conn. USB2.0 x1

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USB2.0 Port1 Page 46
Page 39

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USB3.0 x1 USB3.0 Left Conn
USB2.0 x1 USB3.0 Port3
eDP x2 Lane

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eDP Conn USB2.0 Port3 Page 46
eDP x2 Lane

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Int. Camera Conn. USB2.0 x1 USB3.0 x1 Type-C IC
2
USB2.0 Port4 USB2.0 x1 Realtek RTS5449E Type-C Conn 2
Page 48
Intel PCH

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Page 48
Int. MIC Conn.
Cannon Lake-H

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Page 38

SATA HDD SATA Gen3 x1

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Page 47 SATA Port0

PCIe Gen1 x1 NGFF WLAN&BT/CNVi

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PCIe Port13
FCBGA USB2.0 x1
USB2.0 Port14

26mm*24mm CNVi
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M.2 CRF Module
PCIE SSD Page 45

(or Optane Memory)

Page 45
PCIe Port 9~12 LAN Chip
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PCIe Gen1 x1 RJ45 Conn.

Realtek_RTL8111GUL Page 43
3 3
PCIe Port5 Page 42
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SPK Conn. SPI SPI ROM (16MB)

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Page 35 Codec W25Q128JVSIQ

HD Audio Page 18
I2C
HP&Mic Combo Conn. Realtek ALC3287
Page 35 Page 3~16

LPC
Page 35 USB2.0 Port5 TPM (Reserved)
Z32H320TC Page 37
EC Touch Pad
ITE IT8586E-LQFP
Page 49 Page 50

4
Int.KBD Thermal Sensor 4

(Reserved)
Page 50 Page 44

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2018/09/20 Block Diagram

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
FG541/FG741 1.0

Date: Tuesday, March 26, 2019 Sheet 2 of 69

A B C D E
 A B C D E

Voltage Rails ( O --> Means ON , X --> Means OFF )

SIGNAL
STATE SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

Full ON HIGH HIGH HIGH ON ON ON ON

Power Plane
S3 (Suspend to RAM) LOW HIGH HIGH ON ON OFF OFF
+3VALW +5VS

+5VALW +1.2V +3VS S4 (Suspend to Disk) LOW LOW LOW ON OFF OFF OFF
1 +VCCIO 1
S5 (Soft OFF) LOW LOW LOW ON OFF OFF OFF
V20B+ +3VALW_PCH +2.5V_DDR +VCCSTG
+VCCSA
+1.8VALW +VCCST +VCC_GT
+1.0VALW +CPU_CORE
State +0.6VS
HSIO PORT Function BOM Structure BTO Item
1 USB3.0 Conn Left @ Not stuff
2 USB Type-C
15or17@ For 15" or 17" part

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3 USB3.0 Conn Left
USB3.0 I5@ For I5 CPU
4 USB Type-C
I7@ For I7 CPU
S0 O O O O

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ES_CPU@ For ES CPU
CD@ For C cost down
1 USB3.0 Conn Left
EMC@ For EMC part
S3 O O O X

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2 USB Type-C
EMC_NS@ For EMC nu-stuff part
3 USB3.0 Conn Left
ME@ For ME part

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S3 8 Camera OPT@ For NV GPU part
2
Battery only O O O X USB2.0 14 Bluetooth OPT_NS@ For NV GPU not stuff part 2

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TPM@ For TPM part
S5 S4 8111GUL@ For 8111GUL LAN
O O X X 8111H@

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AC Only For 8111H LAN
NM-C362@ For PCB P/N
S5 S4 GST@ For GST Transformer
Battery only O X X X INPAQ@ For INPAQ Transformer

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0~15 DGPU AJOHO@ For AJOHO Transformer
S5 S4 X16 PCIE M8GX3@ For Micron VRAM X76
AC & Battery X X X X CPU S8GX3@ For Samsung VRAM X76

kS
14 LAN
don't exist H8GX3@ For Hynix VRAM X76
PCIE 13 WLAN
S8G_VR@ For Samsung VRAM
H8G_VR@ For Hnix VRAM
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SMBUS Control Table M8G_VR@ For Micron VRAM
DRAM_S8G@ For Samsung DRAM X76
SOURCE BATT Charger DGPU IT8586E Memory PCH PMIC SODIMM Thermal WLAN
DRAM_M8G@ For Micron DRAM X76
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Down Sensor WiMAX 9~12 Optane Memory

X4 PCIE DRAM_H8G@ For Hynix DRAM X76
3
MD_S8Gb@ For Samsung DRAM 3
EC_SMB_CK1 IT8586E
V V X V X X X X X X 4 HDD MD_H8Gb@ For Hnix DRAM
ot

EC_SMB_DA1 +3VL_EC +3VL_EC MD_M8Gb@ For Micron DRAM

SATA
USB@ For USB part
N

EC_SMB_CK2 IT8586E
X X V V X V X X V X DEBUG@ For USB DEBUG part
EC_SMB_DA2 +3VS +3VG_AON +3VS +3VALW_PCH RF@ For RF part
RF_NS@ For RF unstuff part
EC_SMB_CK3 IT8586E
X X X V X X V X X X CNVI@ For CNVI part
EC_SMB_DA3 +3VL_EC +3VL_EC
BL@ For BL part
PCH_SMB_CLK PCH
X X X X X V X V X V NON_BL@ For NON-BL part
PCH_SMB_DATA +3VALW_PCH +3VALW_PCH +3VS +3VS
AOAC@ For AOAC part

SDP@ For SDP memory part

DDP@ For DDP memory part

EC SMBus1 address EC SMBus2 address EC SMBus3 address PCH SM Bus address
CNL_H@ For CNL PCH part
Device Address Device Address Device Address Device Address
MD@ For memory down part
Smart Battery need to update Thermal Sensor(NCT7718W) 1001_100xb PMIC need to update DDR4 SODIMM need to update
4
DCI@ For DCI part 4
Charger 0001 0010 b PCH need to update Wlan Reserved
DGPU need to update UART@ For UART part

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2018/09/20 Notes List

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FG541/FG741
Date: Tuesday, March 26, 2019 Sheet 3 of 69
A B C D E
 5 4 3 2 1

+3.3V_LDO_RTS5400

2.2K
RTS5400
+3VALW RTS5400_SM_SCL
D
RTS5400_SM_SDA D

+3VALW
Dual MOS Control
2.2K

EC_SMB_CK0
EC_SMB_DA0

+3VALW_R

Battery JBATT2 Change IC PU102

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2.2K
BQ24780SRUYR

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EC
EC_SMB_CK1
IT8226 EC_SMB_DA1

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C C

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+3VS_AON +3VALW_PCH

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2.2K 2.2K

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NV GPU( UV1 ) PCH( UH1 )
+3VS VGA_SMB_CK2
SML1CLK
VGA_SMB_DA2
SML1DATA
Thermal sensor U1

ch
Dual MOS
+3VS_AON
Control Dual MOS
+3VS
Control
F75303M
2.2K

kS
EC_SMB_CK2
EC_SMB_DA2
B
oo B
eb

SMBUS Control Table

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WLAN Thermal PCH TP

SOURCE VGA BATT IT8586E SODIMM WiMAX Sensor Module charger
DDR1 DDR2 WLAN TP
EC_SMB_CK1 IT8226 V
N

+3VALW_PCH +3VS EC_SMB_DA1 +3VALW X V +3VALW X X X X X V

EC_SMB_CK2 IT8226 V V V V
X X X X X
PCH
EC_SMB_DA2 +3VS +3VGS +3VS +3VS +3VALW_PCH

2.2K 2.2K PCH_SMB_CLK PCH

+3VS PCH_SMB_DATA +3VALW_PCH X X X V V X V X X
+3VS +3VS +3VALW_PCH
Control

Dual MOS EC SM Bus1 address EC SM Bus2 address PCH SM Bus address

A
Device Address A
VGA_SMB_CK2 DDR DIMMA
PCH_SMBCLK VGA_SMB_DA2
Device Device Address 1010 000Xb

PCH_SMBDATA Smart Battery 0X16 Thermal Sensor F75303M 1001_100xb DDR DIMMB 1010 010Xb
Charger 0001 0010 b VGA 0x41(default) WLAN Rsvd
PCH need to update

RTS5400 0xD4

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/26 Deciphered Date 2018/09/20 Blank4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FG541/FG741
Date: Tuesday, March 26, 2019 Sheet 4 of 69
5 4 3 2 1
 5 4 3 2 1

25 PCIE_CRX_GTX_N[0..15]

25 PCIE_CRX_GTX_P[0..15]

PCIE_CTX_C_GRX_N[0..15] 25

PCIE_CTX_C_GRX_P[0..15] 25
D D

UC1C
PCIE_CRX_GTX_P15 E25 B25 PCIE_CTX_GRX_P15 OPT@ CC32 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_P15
PCIE_CRX_GTX_N15 D25 PEG_RXP_0 PEG_TXP_0 A25 PCIE_CTX_GRX_N15 OPT@ CC16 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_N15
PEG_RXN_0 PEG_TXN_0
PCIE_CRX_GTX_P14 E24 B24 PCIE_CTX_GRX_P14 OPT@ CC31 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_P14
PCIE_CRX_GTX_N14 F24 PEG_RXP_1 PEG_TXP_1 C24 PCIE_CTX_GRX_N14 OPT@ CC15 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_N14
PEG_RXN_1 PEG_TXN_1
PCIE_CRX_GTX_P13 E23 B23 PCIE_CTX_GRX_P13 OPT@ CC30 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_P13
PCIE_CRX_GTX_N13 D23 PEG_RXP_2 PEG_TXP_2 A23 PCIE_CTX_GRX_N13 OPT@ CC14 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_N13

m
PEG_RXN_2 PEG_TXN_2
PCIE_CRX_GTX_P12 E22 B22 PCIE_CTX_GRX_P12 OPT@ CC29 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_P12
PCIE_CRX_GTX_N12 F22 PEG_RXP_3 PEG_TXP_3 C22 PCIE_CTX_GRX_N12 OPT@ CC13 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_N12
PEG_RXN_3 PEG_TXN_3

co
PCIE_CRX_GTX_P11 E21 B21 PCIE_CTX_GRX_P11 OPT@ CC28 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_P11
PCIE_CRX_GTX_N11 D21 PEG_RXP_4 PEG_TXP_4 A21 PCIE_CTX_GRX_N11 OPT@ CC12 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_N11
PEG_RXN_4 PEG_TXN_4
PCIE_CRX_GTX_P10 E20 B20 PCIE_CTX_GRX_P10 OPT@ CC27 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_P10
PCIE_CRX_GTX_N10 F20 PEG_RXP_5 PEG_TXP_5 C20 PCIE_CTX_GRX_N10 OPT@ CC11 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_N10
PEG_RXN_5 PEG_TXN_5

s.
PCIE_CRX_GTX_P9 E19 B19 PCIE_CTX_GRX_P9 OPT@ CC26 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_P9
PCIE_CRX_GTX_N9 D19 PEG_RXP_6 PEG_TXP_6 A19 PCIE_CTX_GRX_N9 OPT@ CC10 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_N9
PEG_RXN_6 PEG_TXN_6

ic
PCIE_CRX_GTX_P8 E18 B18 PCIE_CTX_GRX_P8 OPT@ CC25 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_P8
PCIE_CRX_GTX_N8 F18 PEG_RXP_7 PEG_TXP_7 C18 PCIE_CTX_GRX_N8 OPT@ CC9 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_N8
C PEG_RXN_7 PEG_TXN_7 C
PCIE_CRX_GTX_P7 PCIE_CTX_GRX_P7 PCIE_CTX_C_GRX_P7

at
D17 A17 OPT@ CC24 1 2 0.22U_0201_6.3V6-K
PCIE_CRX_GTX_N7 E17 PEG_RXP_8 PEG_TXP_8 B17 PCIE_CTX_GRX_N7 OPT@ CC8 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_N7
PEG_RXN_8 PEG_TXN_8
PCIE_CRX_GTX_P6 F16 C16 PCIE_CTX_GRX_P6 OPT@ CC23 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_P6
PCIE_CRX_GTX_N6 E16 PEG_RXP_9 PEG_TXP_9 B16 PCIE_CTX_GRX_N6 OPT@ CC7 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_N6

em
PEG_RXN_9 PEG_TXN_9
PCIE_CRX_GTX_P5 D15 A15 PCIE_CTX_GRX_P5 OPT@ CC22 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_P5
PCIE_CRX_GTX_N5 E15 PEG_RXP_10 PEG_TXP_10 B15 PCIE_CTX_GRX_N5 OPT@ CC6 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_N5
PEG_RXN_10 PEG_TXN_10
PCIE_CRX_GTX_P4 F14 C14 PCIE_CTX_GRX_P4 OPT@ CC21 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_P4
PCIE_CRX_GTX_N4 E14 PEG_RXP_11 PEG_TXP_11 B14 PCIE_CTX_GRX_N4 OPT@ CC5 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_N4
PEG_RXN_11 PEG_TXN_11

ch
PCIE_CRX_GTX_P3 D13 A13 PCIE_CTX_GRX_P3 OPT@ CC20 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_P3
PCIE_CRX_GTX_N3 E13 PEG_RXP_12 PEG_TXP_12 B13 PCIE_CTX_GRX_N3 OPT@ CC4 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_N3
PEG_RXN_12 PEG_TXN_12
PCIE_CRX_GTX_P2 F12 C12 PCIE_CTX_GRX_P2 OPT@ CC19 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_P2
PCIE_CRX_GTX_N2 E12 PEG_RXP_13 PEG_TXP_13 B12 PCIE_CTX_GRX_N2 OPT@ CC3 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_N2

kS
PEG_RXN_13 PEG_TXN_13
PCIE_CRX_GTX_P1 D11 A11 PCIE_CTX_GRX_P1 OPT@ CC18 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_P1
PCIE_CRX_GTX_N1 E11 PEG_RXP_14 PEG_TXP_14 B11 PCIE_CTX_GRX_N1 OPT@ CC2 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_N1
PEG_RXN_14 PEG_TXN_14
PCIE_CRX_GTX_P0 F10 C10 PCIE_CTX_GRX_P0 OPT@ CC17 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_P0
VCCIO PEG_RXP_15 PEG_TXP_15
oo
PCIE_CRX_GTX_N0 E10 B10 PCIE_CTX_GRX_N0 OPT@ CC1 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_N0
PEG_RXN_15 PEG_TXN_15

RC1 2 1 24.9_0402_1% PEG_COMP G2

PEG_RCOMP
CAD Note:
Place R_comp inside CPU cavity
eb

Trace width=12 mils ,Spacing=15mil

DMI_CRX_PTX_P0 DMI_CTX_PRX_P0
B
Max length= 400 mils. 19 DMI_CRX_PTX_P0 DMI_CRX_PTX_N0
D8
E8 DMI_RXP_0 DMI_TXP_0
B8
A8 DMI_CTX_PRX_N0 DMI_CTX_PRX_P0 19 B
19 DMI_CRX_PTX_N0 DMI_RXN_0 DMI_TXN_0 DMI_CTX_PRX_N0 19
DMI_CRX_PTX_P1 DMI_CTX_PRX_P1
ot

E6 C6
19 DMI_CRX_PTX_P1 DMI_CRX_PTX_N1 F6 DMI_RXP_1 DMI_TXP_1 B6 DMI_CTX_PRX_N1 DMI_CTX_PRX_P1 19
19 DMI_CRX_PTX_N1 DMI_RXN_1 DMI_TXN_1 DMI_CTX_PRX_N1 19
DMI_CRX_PTX_P2 D5 B5 DMI_CTX_PRX_P2
19 DMI_CRX_PTX_P2 DMI_CRX_PTX_N2 E5 DMI_RXP_2 DMI_TXP_2 A5 DMI_CTX_PRX_N2 DMI_CTX_PRX_P2 19
N

19 DMI_CRX_PTX_N2 DMI_RXN_2 DMI_TXN_2 DMI_CTX_PRX_N2 19

DMI_CRX_PTX_P3 J8 D4 DMI_CTX_PRX_P3
19 DMI_CRX_PTX_P3 DMI_CRX_PTX_N3 J9 DMI_RXP_3 3 OF 13 DMI_TXP_3 B4 DMI_CTX_PRX_N3 DMI_CTX_PRX_P3 19
19 DMI_CRX_PTX_N3 DMI_RXN_3 DMI_TXN_3 DMI_CTX_PRX_N3 19
COFFEELAKE-H-CPU_BGA1440
@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/26 Deciphered Date 2018/09/20 CPU (1/7) DMI,PEG

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FG541/FG741
Date: Tuesday, March 26, 2019 Sheet 5 of 69
5 4 3 2 1
 5 4 3 2 1

CFG STRAPS for CPU

UC1E

RC28 1 @ 2 0_0402_5% CPU_BCLK B31 BN25 CFG0

17 PCH_CPU_BCLK CPU_BCLK# BCLKP CFG_0
RC29 1 @ 2 0_0402_5% A32 BN27 CFG1 @ PAD 1
17 PCH_CPU_BCLK# BCLKN CFG_1 BN26 TC89
CFG2
CPU_PCIBCLK CFG_2
VCCST 17 PCH_CPU_PCIBCLK
RC15 1 @ 2 0_0402_5%
CPU_PCIBCLK#
D35
PCI_BCLKP CFG_3
BN28 CFG3
CFG3 41 Stall reset sequence after PCU PLL lock until de-asserted
RC13 1 @ 2 0_0402_5% C36 BR20 CFG4
17 PCH_CPU_PCIBCLK# PCI_BCLKN CFG_4 BM20 CFG5  1 = (Default) Normal Operation;
17 PCH_CPU_NSSC_CLK
RC17 1 @ 2 0_0402_5% CPU_NSSC_CLK
CPU_NSSC_CLK#
E31
CLK24P
CFG_5
CFG_6
BT20 CFG6 * No stall.
RC16 1 2 0_0402_5% D31 BP20 CFG7
1
17 PCH_CPU_NSSC_CLK#
@
CLK24N CFG_7 BR23 CFG8 @ PAD 1 CFG0
CFG_8 TC77

1
RC76 CFG_9
BR22 CFG9 @ PAD 1
TC78  0 = Stall.
CC1404 RC66 RC3043 BT23 CFG10 @ PAD 1
56.2_0402_1% CFG_10 TC79
0.1u_0201_10V6K 100_0402_1% 100_0402_1% BT22 CFG11 @ PAD 1
2 CFG_11 TC80
@ CFG_12
BM19 CFG12 @ PAD 1
TC81 Reserved configuration lane
BR19 CFG13 @ PAD 1
CFG_13 TC82

2
D D
BP19 CFG14 @ PAD 1
1 2 VR_SVID_ALRT#_R BH31 CFG_14 BT19 1 TC83
RC65 220_0402_5% CFG15 @ PAD
63 SVID_ALERT# VR_SVID_CLK VIDALERT# CFG_15 TC84
63 SVID_CLK
RC3 1 @ 2 0_0402_5%
VR_SVID_DAT
BH32
VIDSCK CFG1 N/A
RC14 1 @ 2 0_0402_5% BH29 BN23 @ PAD 1
63 SVID_DATA H_PROCHOT#_R VIDSOUT CFG_17 TC85
49,61,63 H_PROCHOT# RC9 1 2 499_0402_1% BR30 BP23 @ PAD 1
PROCHOT# CFG_16 TC86
BP22 @ PAD 1
1 2 1K_0402_5% 1 2 DDR_PG_CTRL BT13 CFG_19 BN22 1 TC87
VCCSTG RC7 CC178 .1U_0402_10V6-K @ PAD
DDR_VTT_CNTL CFG_18 TC88
@ PCI Express* Static x16 Lane Numbering Reversal
change from VCCST to VCCSTG 0619
BR27 @ PAD 1
BPM#_0 TC27
BT27 1
BPM#_1 BM31
@ PAD
1 TC28  1 = Normal operation
VCCST_PWRGD H13 BPM#_2 BT30
@
@
PAD
PAD 1
TC29 CFG2
VCCST_PWRGD BPM#_3 TC42

16 H_CPUPWRGD
RC32 1 2 1/20W_22_5%_0201 CPUPWRGOOD_R
BUF_CPU_RST#
BT31
PROCPWRGD
* 0 = Lane numbers reversed.
14 CPU_PLTRST# RC22 1 @ 2 0_0402_5% BP35 BT28 XDP_TDO 41
H_PM_SYNC RESET# PROC_TDO
14 H_PM_SYNC H_PM_DOWN_R
BM34
PM_SYNC PROC_TDI
BL32
XDP_TDI 41 Reserved configuration lane.
RC33 1 2 20_0402_5% BP31 BP28
14 H_PM_DOWN EC_PECI BT34 PM_DOWN PROC_TMS BR28 XDP_TMS 41
14,49 EC_PECI THRMTRIP#_CPU PECI PROC_TCK XDP_TCK 41
RC34 1 @ 2 0_0402_5% J31

m
14,25 H_THRMTRIP# THERMTRIP#
PROC_TRST#
BP30
XDP_TRST# 41 CFG3 N/A
VCCST RC11 1 2 1K_0402_5% BR33 BL30
SKTOCC# PROC_PREQ# XDP_PREQ# 41
BN1 BP27 XDP_PRDY# 41
PROC_SELECT# PROC_PRDY#
H_CATERR#

co
1 @ 2 10K_0402_5% BM30
CATERR#
RC174
CFG_RCOMP
BT25 eDP enable
1 1 1 AT13

33P_0402_50V8J
ZVM#

2
.1U_0402_10V6-K
CC176

.1U_0402_10V6-K
CC177
AW13

CC175
MSM#
 1 = Disabled.
AU13 RC175
2 @2 @2 AY13 RSVD1

s.
RSVD2
49.9_0402_1%
close to CPU CFG4

1
 0 = Enabled.
5 OF 13
*
COFFEELAKE-H-CPU_BGA1440

ic
+3VALW +3VS
@
PCI Express* Bifurcation
C C
UC1M
2

at
2

RC178  00 = 1 x8, 2 x4 PCI Express*

RC177
100K_0402_5%
+1.2V 100K_0402_5% E2
RSVD_TP5 VCCST  01 = reserved
1 PAD E3
@
TC111
@ E1 IST_TRIG CFG[6:5]  10 = 2 x8 PCI Express*
1

em
RSVD_TP4
1

D1
RSVD_TP3
1

CPU_DRAMPG_CNTL  11 = 1 x16 PCI Express*

CPU_DRAMPG_CNTL 61 *

1
RC18 BR1 BK28
1K_0402_5% BT2 RSVD_TP1 RSVD11 BJ28 RC57
RSVD_TP2 RSVD10 51_0402_5%
1

C BN35
RSVD15
@ PEG Training
2

2 QC1

2
B J24
MMBT3904WH_SOT323-3
*

ch
RSVD28
E H24
RSVD27
 1 = (default) PEG Train
3

BN33 immediately following

DDR_PG_CTRL BL34 RSVD14
XDP_PREQ#
RSVD13
CFG7 RESET# deassertion.
N29
RSVD30
R14  0 = PEG Wait for BIOS for training.

kS
RSVD31
2

AE29
RC179 AA14 RSVD33
10K_0402_5% AP29 RSVD32
@ AP14 RSVD5
A36 RSVD4
VSS_A36 Reserved configuration lane.
1

oo
Debug Pin A37
VSS_A37
Logic Buffer CPU_TRIGIN H23
CFG[19:8] N/A
PCH_TRIGIN RC4 1 2 30_0402_1% CPU_TRIGOUT J23 PROC_TRIGIN
22 PCH_TRIGIN PROC_TRIGOUT
22 CPU_TRIGIN 1 F30
CC174 RSVD24
eb

.1U_0402_10V6-K
@ E30
2 RSVD23

B B
B30 BL31
C30 RSVD7 RSVD12 AJ8
RSVD21 RSVD3
ot

G13
RSVD25
G3 VCCIO
J3 RSVD26 C38
RSVD29 RSVD22 C1
RSVD20 BR2
N

BR35 RSVD17 BP1

BR31 RSVD19 RSVD16 B38
+3VS +3VALW VCCST BH30 RSVD18 RSVD8 B2
RSVD9 RSVD6
13 OF 13
2

COFFEELAKE-H-CPU_BGA1440
R292 R291 RC75 @
10K_0402_5% 10K_0402_5% 1K_0402_5%

1
@
RC139 RC140 RC141 RC142 RC143 RC144
1

1K_0402_5% 1K_0402_5% 1K_0402_5% 1K_0402_5% 1K_0402_5% 1K_0402_5%

@ @ @
RC50 1 2 VCCST_PWRGD CFG3

2
60.4_0402_1%
CFG1 CFG7
CFG6
CFG5
CFG4
1

Q1 D Q2 D CC179 CFG2
CPUCORE_ON 2 2 330P_0402_50V8J CFG0
49,63 CPUCORE_ON G G
2

RC146

1
1

1
1

S 1 S L2N7002KWT1G_SOT323-3 1K_0402_5%
3

R322 @ RC56 RC53 RC54 RC52 RC51 RC55

L2N7002KWT1G_SOT323-3 CC33 @ 1K_0402_1% 1K_0402_5% 1K_0402_5% 1K_0402_5% 1K_0402_5% 1K_0402_5% 1K_0402_5%
0.022U_0402_16V7-K @ @ @ @
2

2 @

2
2

2
2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/26 Deciphered Date 2018/09/20 CPU (2/7) PM, XDP, CLK, CFG
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
FG541/FG741 1.0

Date: Tuesday, March 26, 2019 Sheet 6 of 69

5 4 3 2 1
 5 4 3 2 1

DDRA_DQ[0..63] 12
UC1A
DDRA_DQ0 DDRB_DQ[0..63] 13
AG1 BR6 UC1B
12 DDRA_CLK0 AG2 DDR0_CKP_0/DDR0_CKP_0 DDR0_DQ_0/DDR0_DQ_0 BT6 DDRA_DQ1 AM9 BT11 DDRB_DQ0
12 DDRA_CLK0# DDR0_CKN_0/DDR0_CKN_0 DDR0_DQ_1/DDR0_DQ_1 DDRA_DQ2 13 DDRB_CLK0 DDR1_CKP_0/DDR1_CKP_0 DDR1_DQ_0/DDR0_DQ_16 DDRB_DQ1
AK2 BP3 AN9 BR11
DDR0_CKP_1/DDR0_CKP_1 DDR0_DQ_2/DDR0_DQ_2 DDRA_DQ3 13 DDRB_CLK0# DDR1_CKN_0/DDR1_CKN_0 DDR1_DQ_1/DDR0_DQ_17 DDRB_DQ2
AK1 BR3 AM7 BT9
AL3 DDR0_CKN_1/DDR0_CKN_1 DDR0_DQ_3/DDR0_DQ_3 BN5 DDRA_DQ4 13 DDRB_CLK1 AM8 DDR1_CKP_1/DDR1_CKP_1 DDR1_DQ_2/DDR0_DQ_18 BR8 DDRB_DQ3
NC/DDR0_CKP_2 DDR0_DQ_4/DDR0_DQ_4 DDRA_DQ5 13 DDRB_CLK1# DDR1_CKN_1/DDR1_CKN_1 DDR1_DQ_3/DDR0_DQ_19 DDRB_DQ4
AK3 BP6 AM11 BP11
AL2 NC/DDR0_CKN_2 DDR0_DQ_5/DDR0_DQ_5 BP2 DDRA_DQ6 AM10 NC/DDR1_CKP_2 DDR1_DQ_4/DDR0_DQ_20 BN11 DDRB_DQ5
AL1 NC/DDR0_CKP_3 DDR0_DQ_6/DDR0_DQ_6 BN3 DDRA_DQ7 AJ10 NC/DDR1_CKN_2 DDR1_DQ_5/DDR0_DQ_21 BP8 DDRB_DQ6
D NC/DDR0_CKN_3 DDR0_DQ_7/DDR0_DQ_7 BL4 DDRA_DQ8 AJ11 NC/DDR1_CKP_3 DDR1_DQ_6/DDR0_DQ_22 BN8 DDRB_DQ7 D
AT1 DDR0_DQ_8/DDR0_DQ_8 BL5 DDRA_DQ9 NC/DDR1_CKN_3 DDR1_DQ_7/DDR0_DQ_23 BL12 DDRB_DQ8
12 DDRA_CKE0 DDR0_CKE_0/DDR0_CKE_0 DDR0_DQ_9/DDR0_DQ_9 DDRA_DQ10 DDR1_DQ_8/DDR0_DQ_24 DDRB_DQ9
AT2 BL2 AT8 BL11
AT3 DDR0_CKE_1/DDR0_CKE_1 DDR0_DQ_10/DDR0_DQ_10 BM1 DDRA_DQ11 13 DDRB_CKE0 AT10 DDR1_CKE_0/DDR1_CKE_0 DDR1_DQ_9/DDR0_DQ_25 BL8 DDRB_DQ10
DDR0_CKE_2/DDR0_CKE_2 DDR0_DQ_11/DDR0_DQ_11 DDRA_DQ12 13 DDRB_CKE1 DDR1_CKE_1/DDR1_CKE_1 DDR1_DQ_10/DDR0_DQ_26 DDRB_DQ11
AT5 BK4 AT7 BJ8
DDR0_CKE_3/DDR0_CKE_3 DDR0_DQ_12/DDR0_DQ_12 BK5 DDRA_DQ13 AT11 DDR1_CKE_2/DDR1_CKE_2 DDR1_DQ_11/DDR0_DQ_27 BJ11 DDRB_DQ12
AD5 DDR0_DQ_13/DDR0_DQ_13 BK1 DDRA_DQ14 DDR1_CKE_3/DDR1_CKE_3 DDR1_DQ_12/DDR0_DQ_28 BJ10 DDRB_DQ13
12 DDRA_CS0# DDR0_CS#_0/DDR0_CS#_0 DDR0_DQ_14/DDR0_DQ_14 DDRA_DQ15 DDR1_DQ_13/DDR0_DQ_29 DDRB_DQ14
AE2 BK2 AF11 BL7
AD2 DDR0_CS#_1/DDR0_CS#_1 DDR0_DQ_15/DDR0_DQ_15 BG4 DDRA_DQ16 13 DDRB_CS0# AE7 DDR1_CS#_0/DDR1_CS#_0 DDR1_DQ_14/DDR0_DQ_30 BJ7 DDRB_DQ15
NC/DDR0_CS#_2 DDR0_DQ_16/DDR0_DQ_32 DDRA_DQ17 13 DDRB_CS1# DDR1_CS#_1/DDR1_CS#_1 DDR1_DQ_15/DDR0_DQ_31 DDRB_DQ16
AE5 BG5 AF10 BG11
NC/DDR0_CS#_3 DDR0_DQ_17/DDR0_DQ_33 BF4 DDRA_DQ18 AE10 NC/DDR1_CS#_2 DDR1_DQ_16/DDR0_DQ_48 BG10 DDRB_DQ17
DDRA_ODT0 AD3 DDR0_DQ_18/DDR0_DQ_34 BF5 DDRA_DQ19 NC/DDR1_CS#_3 DDR1_DQ_17/DDR0_DQ_49 BG8 DDRB_DQ18
12 DDRA_ODT0 DDR0_ODT_0/DDR0_ODT_0 DDR0_DQ_19/DDR0_DQ_35 DDRA_DQ20 DDRB_ODT0 DDR1_DQ_18/DDR0_DQ_50 DDRB_DQ19
AE4 BG2 AF7 BF8
AE1 NC/DDR0_ODT_1 DDR0_DQ_20/DDR0_DQ_36 BG1 DDRA_DQ21 13 DDRB_ODT0 DDRB_ODT1 AE8 DDR1_ODT_0/DDR1_ODT_0 DDR1_DQ_19/DDR0_DQ_51 BF11 DDRB_DQ20
NC/DDR0_ODT_2 DDR0_DQ_21/DDR0_DQ_37 DDRA_DQ22 13 DDRB_ODT1 NC/DDR1_ODT_1 DDR1_DQ_20/DDR0_DQ_52 DDRB_DQ21
AD4 BF1 AE9 BF10
NC/DDR0_ODT_3 DDR0_DQ_22/DDR0_DQ_38 BF2 DDRA_DQ23 AE11 NC/DDR1_ODT_2 DDR1_DQ_21/DDR0_DQ_53 BG7 DDRB_DQ22
DDRA_BA0 AH5 DDR0_DQ_23/DDR0_DQ_39 BD2 DDRA_DQ24 NC/DDR1_ODT_3 DDR1_DQ_22/DDR0_DQ_54 BF7 DDRB_DQ23
12 DDRA_BA0 DDR0_CAB_4/DDR0_BA_0 DDR0_DQ_24/DDR0_DQ_40 DDR1_DQ_23/DDR0_DQ_55
DDRA_BA1 AH1 BD1 DDRA_DQ25 AH10 BB11 DDRB_DQ24
12 DDRA_BA1 DDR0_CAB_6/DDR0_BA_1 DDR0_DQ_25/DDR0_DQ_41 13 DDRB_MA16_RAS# DDR1_CAB_3/DDR1_MA_16 DDR1_DQ_24/DDR0_DQ_56
AU1 BC4 DDRA_DQ26 AH11 BC11 DDRB_DQ25
12 DDRA_BG0 DDR0_CAA_5/DDR0_BG_0 DDR0_DQ_26/DDR0_DQ_42 DDRA_DQ27 13 DDRB_MA14_WE# DDR1_CAB_2/DDR1_MA_14 DDR1_DQ_25/DDR0_DQ_57 DDRB_DQ26
BC5 AF8 BB8

m
DDR0_DQ_27/DDR0_DQ_43 DDRA_DQ28 13 DDRB_MA15_CAS# DDR1_CAB_1/DDR1_MA_15 DDR1_DQ_26/DDR0_DQ_58 DDRB_DQ27
AH4 BD5 BC8
12 DDRA_MA16_RAS# AG4 DDR0_CAB_3/DDR0_MA_16 DDR0_DQ_28/DDR0_DQ_44 BD4 DDRA_DQ29 AH8 DDR1_DQ_27/DDR0_DQ_59 BC10 DDRB_DQ28
12 DDRA_MA14_WE# DDR0_CAB_2/DDR0_MA_14 DDR0_DQ_29/DDR0_DQ_45 DDRA_DQ30 13 DDRB_BA0 DDR1_CAB_4/DDR1_BA_0 DDR1_DQ_28/DDR0_DQ_60 DDRB_DQ29
AD1 BC1 AH9 BB10
12 DDRA_MA15_CAS# DDR0_CAB_1/DDR0_MA_15 DDR0_DQ_30/DDR0_DQ_46 BC2 DDRA_DQ31 13 DDRB_BA1 AR9 DDR1_CAB_6/DDR1_BA_1 DDR1_DQ_29/DDR0_DQ_61 BC7 DDRB_DQ30
12 DDRA_MA[0..9] DDRA_MA0 DDR0_DQ_31/DDR0_DQ_47 DDRA_DQ32 13 DDRB_BG0 DDR1_CAA_5/DDR1_BG_0 DDR1_DQ_30/DDR0_DQ_62 DDRB_DQ31

co
AH3 AB1 BB7
DDRA_MA1 DDR0_CAB_9/DDR0_MA_0 DDR0_DQ_32/DDR1_DQ_0 DDRA_DQ33 13 DDRB_MA[0..9] DDRB_MA0 DDR1_DQ_31/DDR0_DQ_63 DDRB_DQ32
AP4 AB2 AJ9 AA11
DDRA_MA2 AN4 DDR0_CAB_8/DDR0_MA_1 DDR0_DQ_33/DDR1_DQ_1 AA4 DDRA_DQ34 DDRB_MA1 AK6 DDR1_CAB_9/DDR1_MA_0 DDR1_DQ_32/DDR1_DQ_16 AA10 DDRB_DQ33
DDRA_MA3 AP5 DDR0_CAB_5/DDR0_MA_2 DDR0_DQ_34/DDR1_DQ_2 AA5 DDRA_DQ35 DDRB_MA2 AK5 DDR1_CAB_8/DDR1_MA_1 DDR1_DQ_33/DDR1_DQ_17 AC11 DDRB_DQ34
DDRA_MA4 AP2 NC/DDR0_MA_3 DDR0_DQ_35/DDR1_DQ_3 AB5 DDRA_DQ36 DDRB_MA3 AL5 DDR1_CAB_5/DDR1_MA_2 DDR1_DQ_34/DDR1_DQ_18 AC10 DDRB_DQ35
DDRA_MA5 AP1 NC/DDR0_MA_4 DDR0_DQ_36/DDR1_DQ_4 AB4 DDRA_DQ37 DDRB_MA4 AL6 NC/DDR1_MA_3 DDR1_DQ_35/DDR1_DQ_19 AA7 DDRB_DQ36
DDRA_MA6 AP3 DDR0_CAA_0/DDR0_MA_5 DDR0_DQ_37/DDR1_DQ_5 AA2 DDRA_DQ38 DDRB_MA5 AM6 NC/DDR1_MA_4 DDR1_DQ_36/DDR1_DQ_20 AA8 DDRB_DQ37

s.
DDRA_MA7 AN1 DDR0_CAA_2/DDR0_MA_6 DDR0_DQ_38/DDR1_DQ_6 AA1 DDRA_DQ39 DDRB_MA6 AN7 DDR1_CAA_0/DDR1_MA_5 DDR1_DQ_37/DDR1_DQ_21 AC8 DDRB_DQ38
DDRA_MA8 AN3 DDR0_CAA_4/DDR0_MA_7 DDR0_DQ_39/DDR1_DQ_7 V5 DDRA_DQ40 DDRB_MA7 AN10 DDR1_CAA_2/DDR1_MA_6 DDR1_DQ_38/DDR1_DQ_22 AC7 DDRB_DQ39
DDRA_MA9 AT4 DDR0_CAA_3/DDR0_MA_8 DDR0_DQ_40/DDR1_DQ_8 V2 DDRA_DQ41 DDR1_CAA_4/DDR1_MA_7 DDR1_DQ_39/DDR1_DQ_23
DDRA_MA10 AH2 DDR0_CAA_1/DDR0_MA_9 DDR0_DQ_41/DDR1_DQ_9 U1 DDRA_DQ42 DDRB_MA8 AN8 W8 DDRB_DQ40

ic
12 DDRA_MA10 DDRA_MA11 DDR0_CAB_7/DDR0_MA_10 DDR0_DQ_42/DDR1_DQ_10 DDRA_DQ43 DDRB_MA9 DDR1_CAA_3/DDR1_MA_8 DDR1_DQ_40/DDR1_DQ_24 DDRB_DQ41
AN2 U2 AR11 W7
12 DDRA_MA11 DDRA_MA12 AU4 DDR0_CAA_7/DDR0_MA_11 DDR0_DQ_43/DDR1_DQ_11 V1 DDRA_DQ44 DDRB_MA10 AH7 DDR1_CAA_1/DDR1_MA_9 DDR1_DQ_41/DDR1_DQ_25 V10 DDRB_DQ42
12 DDRA_MA12 DDRA_MA13 DDR0_CAA_6/DDR0_MA_12 DDR0_DQ_44/DDR1_DQ_12 DDRA_DQ45 13 DDRB_MA10 DDRB_MA11 DDR1_CAB_7/DDR1_MA_10 DDR1_DQ_42/DDR1_DQ_26 DDRB_DQ43
C AE3 V4 AN11 V11 C
12 DDRA_MA13 AU2 DDR0_CAB_0/DDR0_MA_13 DDR0_DQ_45/DDR1_DQ_13 U5 DDRA_DQ46 13 DDRB_MA11 DDRB_MA12 AR10 DDR1_CAA_7/DDR1_MA_11 DDR1_DQ_43/DDR1_DQ_27 W11 DDRB_DQ44

at
12 DDRA_BG1 DDRA_ACT# DDR0_CAA_9/DDR0_BG_1 DDR0_DQ_46/DDR1_DQ_14 DDRA_DQ47 13 DDRB_MA12 DDRB_MA13 DDR1_CAA_6/DDR1_MA_12 DDR1_DQ_44/DDR1_DQ_28 DDRB_DQ45
AU3 U4 AF9 W10
12 DDRA_ACT# DDR0_CAA_8/DDR0_ACT# DDR0_DQ_47/DDR1_DQ_15 DDRA_DQ48 13 DDRB_MA13 DDRB_BG1 DDR1_CAB_0/DDR1_MA_13 DDR1_DQ_45/DDR1_DQ_29 DDRB_DQ46
R2 AR7 V7
DDRA_PAR AG3 DDR0_DQ_48/DDR1_DQ_32 P5 DDRA_DQ49 13 DDRB_BG1 DDRB_ACT# AT9 DDR1_CAA_9/DDR1_BG_1 DDR1_DQ_46/DDR1_DQ_30 V8 DDRB_DQ47
12 DDRA_PAR DDRA_ALERT# NC/DDR0_PAR DDR0_DQ_49/DDR1_DQ_33 DDRA_DQ50 13 DDRB_ACT# DDR1_CAA_8/DDR1_ACT# DDR1_DQ_47/DDR1_DQ_31 DDRB_DQ48
AU5 R4 R11
12 DDRA_ALERT# NC/DDR0_ALERT# DDR0_DQ_50/DDR1_DQ_34 P4 DDRA_DQ51 DDRB_PAR AJ7 DDR1_DQ_48/DDR1_DQ_48 P11 DDRB_DQ49

em
DDR0_DQ_51/DDR1_DQ_35 DDRA_DQ52 13 DDRB_PAR DDRB_ALERT# NC/DDR1_PAR DDR1_DQ_49/DDR1_DQ_49 DDRB_DQ50
R5 AR8 P7
12 DDRA_DQS#[0..7] DDRA_DQS#0 DDR0_DQ_52/DDR1_DQ_36 DDRA_DQ53 13 DDRB_ALERT# NC/DDR1_ALERT# DDR1_DQ_50/DDR1_DQ_50 DDRB_DQ51
BR5 P2 R8
DDRA_DQS#1 BL3 DDR0_DQSN_0/DDR0_DQSN_0DDR0_DQ_53/DDR1_DQ_37 R1 DDRA_DQ54 DDR1_DQ_51/DDR1_DQ_51 R10 DDRB_DQ52
DDRA_DQS#2 DDR0_DQSN_1/DDR0_DQSN_1DDR0_DQ_54/DDR1_DQ_38 DDRA_DQ55 13 DDRB_DQS#[0..7] DDRB_DQS#0 DDR1_DQ_52/DDR1_DQ_52 DDRB_DQ53
BG3 P1 BN9 P10
DDRA_DQS#3 BD3 DDR0_DQSN_2/DDR0_DQSN_4DDR0_DQ_55/DDR1_DQ_39 M4 DDRA_DQ56 DDRB_DQS#1 BL9 DDR1_DQSN_0/DDR0_DQSN_2DDR1_DQ_53/DDR1_DQ_53 R7 DDRB_DQ54
DDRA_DQS#4 AA3 DDR0_DQSN_3/DDR0_DQSN_5DDR0_DQ_56/DDR1_DQ_40 M1 DDRA_DQ57 DDRB_DQS#2 BG9 DDR1_DQSN_1/DDR0_DQSN_3DDR1_DQ_54/DDR1_DQ_54 P8 DDRB_DQ55
DDRA_DQS#5 U3 DDR0_DQSN_4/DDR1_DQSN_0DDR0_DQ_57/DDR1_DQ_41 L4 DDRA_DQ58 DDRB_DQS#3 BC9 DDR1_DQSN_2/DDR0_DQSN_6DDR1_DQ_55/DDR1_DQ_55 L11 DDRB_DQ56
DDRA_DQS#6 P3 DDR0_DQSN_5/DDR1_DQSN_1DDR0_DQ_58/DDR1_DQ_42 L2 DDRA_DQ59 DDRB_DQS#4 AC9 DDR1_DQSN_3/DDR0_DQSN_7DDR1_DQ_56/DDR1_DQ_56 M11 DDRB_DQ57

ch
DDRA_DQS#7 L3 DDR0_DQSN_6/DDR1_DQSN_4DDR0_DQ_59/DDR1_DQ_43 M5 DDRA_DQ60 DDRB_DQS#5 W9 DDR1_DQSN_4/DDR1_DQSN_2DDR1_DQ_57/DDR1_DQ_57 L7 DDRB_DQ58
DDR0_DQSN_7/DDR1_DQSN_5DDR0_DQ_60/DDR1_DQ_44 M2 DDRA_DQ61 DDRB_DQS#6 R9 DDR1_DQSN_5/DDR1_DQSN_3DDR1_DQ_58/DDR1_DQ_58 M8 DDRB_DQ59
12 DDRA_DQS[0..7] DDRA_DQS0 DDR0_DQ_61/DDR1_DQ_45 DDRA_DQ62 DDRB_DQS#7 DDR1_DQSN_6/DDR1_DQSN_6DDR1_DQ_59/DDR1_DQ_59 DDRB_DQ60
BP5 L5 M9 L10
DDRA_DQS1 BK3 DDR0_DQSP_0/DDR0_DQSP_0 DDR0_DQ_62/DDR1_DQ_46 L1 DDRA_DQ63 DDR1_DQSN_7/DDR1_DQSN_7DDR1_DQ_60/DDR1_DQ_60 M10 DDRB_DQ61
DDRA_DQS2 BF3 DDR0_DQSP_1/DDR0_DQSP_1 DDR0_DQ_63/DDR1_DQ_47 13 DDRB_DQS[0..7] DDRB_DQS0 BP9 DDR1_DQ_61/DDR1_DQ_61 M7 DDRB_DQ62
DDRA_DQS3 BC3 DDR0_DQSP_2/DDR0_DQSP_4 BA2 DDRB_DQS1 BJ9 DDR1_DQSP_0/DDR0_DQSP_2 DDR1_DQ_62/DDR1_DQ_62 L8 DDRB_DQ63

kS
DDRA_DQS4 AB3 DDR0_DQSP_3/DDR0_DQSP_5 NC/DDR0_ECC_0 BA1 DDRB_DQS2 BF9 DDR1_DQSP_1/DDR0_DQSP_3 DDR1_DQ_63/DDR1_DQ_63
DDRA_DQS5 V3 DDR0_DQSP_4/DDR1_DQSP_0 NC/DDR0_ECC_1 AY4 DDRB_DQS3 BB9 DDR1_DQSP_2/DDR0_DQSP_6 AW11
DDRA_DQS6 R3 DDR0_DQSP_5/DDR1_DQSP_1 NC/DDR0_ECC_2 AY5 DDRB_DQS4 AA9 DDR1_DQSP_3/DDR0_DQSP_7 NC/DDR1_ECC_0 AY11
DDRA_DQS7 M3 DDR0_DQSP_6/DDR1_DQSP_4 NC/DDR0_ECC_3 BA5 DDRB_DQS5 V9 DDR1_DQSP_4/DDR1_DQSP_2 NC/DDR1_ECC_1 AY8
DDR0_DQSP_7/DDR1_DQSP_5 NC/DDR0_ECC_4 BA4 DDRB_DQS6 P9 DDR1_DQSP_5/DDR1_DQSP_3 NC/DDR1_ECC_2 AW8
AY3 DDR CHANNEL A NC/DDR0_ECC_5 AY1 DDRB_DQS7 L9 DDR1_DQSP_6/DDR1_DQSP_6 NC/DDR1_ECC_3 AY10
DDR0_DQSP_8/DDR0_DQSP_8 NC/DDR0_ECC_6 DDR1_DQSP_7/DDR1_DQSP_7 NC/DDR1_ECC_4
BA3 1 OF 13 AY2
oo AW10
DDR0_DQSN_8/DDR0_DQSN_8 NC/DDR0_ECC_7 AW9 NC/DDR1_ECC_5 AY7
COFFEELAKE-H-CPU_BGA1440 AY9 DDR1_DQSP_8/DDR1_DQSP_8 NC/DDR1_ECC_6 AW7
DDR1_DQSN_8/DDR1_DQSN_8 NC/DDR1_ECC_7
@
eb

12 DDR_SA_VREFCA DDR_SA_VREFCA BN13 G1 SM_RCOMP0

+V_DDR_REF_R BP13 DDR_VREF_CA DDR CHANNEL B DDR_RCOMP_0 H1 SM_RCOMP1
+V_DDR_REFB_R BR13 DDR0_VREF_DQ DDR_RCOMP_1 J2 SM_RCOMP2
2 OF 13
B DDR1_VREF_DQ DDR_RCOMP_2 B

COFFEELAKE-H-CPU_BGA1440
ot

@
DDRA_CLK0#

1
CC1390
N

3.3P_0201_50V8-C
@
2 @
DDRA_CLK0 PAD TC109 1 +VREF_DQ_DIMM_R RC36 1 @ 2 0_0402_5% +V_DDR_REF_R
RC37 1 2 0_0402_5% +V_DDR_REFB_R
+VREF_DQ_DIMMB_R

CAD Note:
Follow 1.0PDG to reserve 3.3P_0201 capacitor Trace width= 20 mil, Spcing=20 mils
between DDRA_CLK0 and DDRA_CLK0# --SF0904 DDR_VREF_CA : Connected to
DDR0_VREF_DQ : NC
VREF_CA on DIMM CH-A

DDR1_VREF_DQ : Connected to VREF_CA on DIMM CH-B

DDR4 COMPENSATION SIGNALS

SM_RCOMP0 RC5 1 2 121_0402_1%

SM_RCOMP1 RC6 1 2 75_0402_1%

SM_RCOMP2 RC8 1 2 100_0402_1%

CAD Note:
Trace width=12~15 mil, Spcing=20 mils
Max trace length= 500 mil
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/26 Deciphered Date 2018/09/20 CPU (3/7) DDRVI

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
FG541/FG741 1.0

Date: Tuesday, March 26, 2019 Sheet 7 of 69

5 4 3 2 1
 5 4 3 2 1

UC1D

D K36 D29 CPU_EDP_TX0+ D

DDI1_TXP_0 EDP_TXP_0 CPU_EDP_TX0- CPU_EDP_TX0+ 38
K37 E29
DDI1_TXN_0 EDP_TXN_0 CPU_EDP_TX1+ CPU_EDP_TX0- 38
J35 F28
DDI1_TXP_1 EDP_TXP_1 CPU_EDP_TX1- CPU_EDP_TX1+ 38
J34 E28
DDI1_TXN_1 EDP_TXN_1 CPU_EDP_TX1- 38
H37 A29
H36 DDI1_TXP_2 EDP_TXP_2 B29
J37 DDI1_TXN_2 EDP_TXN_2 C28
J38 DDI1_TXP_3 EDP_TXP_3 B28
DDI1_TXN_3 EDP_TXN_3
D27 C26 CPU_EDP_AUX
DDI1_AUXP EDP_AUXP CPU_EDP_AUX# CPU_EDP_AUX 38
E27 B26
DDI1_AUXN EDP_AUXN CPU_EDP_AUX# 38
H34
H33 DDI2_TXP_0
F37 DDI2_TXN_0 A33 VCCIO
G38 DDI2_TXP_1 EDP_DISP_UTIL

m
F34 DDI2_TXN_1
F35 DDI2_TXP_2 D37 EDP_COMP 2 1
E37 DDI2_TXN_2 DISP_RCOMP 24.9_0402_1% RC49
DDI2_TXP_3

co
E36
DDI2_TXN_3 COMPENSATION PU FOR eDP
F26
E26 DDI2_AUXP CAD Note:Trace width=20 mils ,Spacing=25mil,

s.
DDI2_AUXN
Max length=100 mils.
C34
D34 DDI3_TXP_0
DDI3_TXN_0

ic
B36
B34 DDI3_TXP_1
C F33 DDI3_TXN_1 C
DDI3_TXP_2

at
E33
C33 DDI3_TXN_2
B33 DDI3_TXP_3
DDI3_TXN_3 G27 PROC_AUDIO_CLK_CPU
PROC_AUDIO_CLK PROC_AUDIO_CLK_CPU 16
G25 PROC_AUDIO_SDO_CPU

em
A27 PROC_AUDIO_SDO_CPU 16
B27 DDI3_AUXP PROC_AUDIO_SDI G29 PROC_AUDIO_SDI_CPU_R RC180 1 2 20_0402_1%
DDI3_AUXN PROC_AUDIO_SDO PROC_AUDIO_SDI_CPU 16
4 of 13
Place near CPU.
COFFEELAKE-H-CPU_BGA1440
@

1
ch
RH762
33_0402_5%
@

2
kS
1
CH264
oo
10P_0402_50V8J
2@
eb

B B
ot
N

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/26 Deciphered Date 2018/09/20 CPU (4/7) eDP, DDI
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
A3 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FG541/FG741
Date: Tuesday, March 26, 2019 Sheet 8 of 69
5 4 3 2 1
 5 4 3 2 1

VCCGFXCORE VCCGFXCORE
VCCCPUCORE VCCCPUCORE VCCCPUCORE
UC1J VCCCPUCORE UC1K
UC1I AT14 BD35
AA13 AH13 K14 W35 AT31 VCCGT1 VCCGT80 BD36
AA31 VCC1 VCC64 AH14 L13 VCC125 VCC188 W36 AT32 VCCGT2 VCCGT81 BE31
AA32 VCC2 VCC65 AH29 L14 VCC126 VCC189 W37 AT33 VCCGT3 VCCGT82 BE32
AA33 VCC3 VCC66 AH30 N13 VCC127 VCC190 W38 AT34 VCCGT4 VCCGT83 BE33
AA34 VCC4 VCC67 AH31 N14 VCC128 VCC191 Y29 AT35 VCCGT5 VCCGT84 BE34
AA35 VCC5 VCC68 AH32 N30 VCC129 VCC192 Y30 AT36 VCCGT6 VCCGT85 BE35
AA36 VCC6 VCC69 AJ14 N31 VCC130 VCC193 Y31 AT37 VCCGT7 VCCGT86 BE36
AA37 VCC7 VCC70 AJ29 N32 VCC131 VCC194 Y32 AT38 VCCGT8 VCCGT87 BE37
AA38 VCC8 VCC71 AJ30 N35 VCC132 VCC195 Y33 AU14 VCCGT9 VCCGT88 BE38
AB29 VCC9 VCC72 AJ31 N36 VCC133 VCC196 Y34 AU29 VCCGT10 VCCGT89 BF13
AB30 VCC10 VCC73 AJ32 N37 VCC134 VCC197 Y35 AU30 VCCGT11 VCCGT90 BF14
AB31 VCC11 VCC74 AJ33 N38 VCC135 VCC198 Y36 AU31 VCCGT12 VCCGT91 BF29
AB32 VCC12 VCC75 AJ34 P13 VCC136 VCC199 AU32 VCCGT13 VCCGT92 BF30
AB35 VCC13 VCC76 AJ35 P14 VCC137 AU35 VCCGT14 VCCGT93 BF31
AB36 VCC14 VCC77 AJ36 P29 VCC138 AU36 VCCGT15 VCCGT94 BF32
AB37 VCC15 VCC78 AK31 P30 VCC139 AU37 VCCGT16 VCCGT95 BF35
AB38 VCC16 VCC79 AK32 P31 VCC140 AU38 VCCGT17 VCCGT96 BF36
AC13 VCC17 VCC80 AK33 P32 VCC141 AV29 VCCGT18 VCCGT97 BF37
D AC14 VCC18 VCC81 AK34 P33 VCC142 AV30 VCCGT19 VCCGT98 BF38 D
AC29 VCC19 VCC82 AK35 P34 VCC143 AV31 VCCGT20 VCCGT99 BG29
AC30 VCC20 VCC83 AK36 P35 VCC144 AV32 VCCGT21 VCCGT100 BG30
AC31 VCC21 VCC84 AK37 P36 VCC145 AV33 VCCGT22 VCCGT101 BG31
AC32 VCC22 VCC85 AK38 R13 VCC146 AV34 VCCGT23 VCCGT102 BG32
AC33 VCC23 VCC86 AL13 R31 VCC147 AV35 VCCGT24 VCCGT103 BG33
AC34 VCC24 VCC87 AL29 R32 VCC148 AV36 VCCGT25 VCCGT104 BG34
AC35 VCC25 VCC88 AL30 R33 VCC149 AW14 VCCGT26 VCCGT105 BG35
AC36 VCC26 VCC89 AL31 R34 VCC150 AW31 VCCGT27 VCCGT106 BG36
AD13 VCC27 VCC90 AL32 R35 VCC151 AW32 VCCGT28 VCCGT107 BH33
AD14 VCC28 VCC91 AL35 R36 VCC152 AW33 VCCGT29 VCCGT108 BH34
AD31 VCC29 VCC92 AL36 R37 VCC153 AW34 VCCGT30 VCCGT109 BH35
AD32 VCC30 VCC93 AL37 R38 VCC154 AW35 VCCGT31 VCCGT110 BH36
AD33 VCC31 VCC94 AL38 T29 VCC155 AW36 VCCGT32 VCCGT111 BH37
AD34 VCC32 VCC95 AM13 T30 VCC156 AW37 VCCGT33 VCCGT112 BH38
AD35 VCC33 VCC96 AM14 T31 VCC157 AW38 VCCGT34 VCCGT113 BJ16
AD36 VCC34 VCC97 AM29 T32 VCC158 AY29 VCCGT35 VCCGT114 BJ17
AD37 VCC35 VCC98 AM30 T35 VCC159 AY30 VCCGT36 VCCGT115 BJ19
AD38 VCC36 VCC99 AM31 T36 VCC160 AY31 VCCGT37 VCCGT116 BJ20
AE13 VCC37 VCC100 AM32 T37 VCC161 AY32 VCCGT38 VCCGT117 BJ21
AE14 VCC38 VCC101 AM33 T38 VCC162 AY35 VCCGT39 VCCGT118 BJ23
AE30 VCC39 VCC102 AM34 U29 VCC163 AY36 VCCGT40 VCCGT119 BJ24
AE31 VCC40 VCC103 AM35 U30 VCC164 AY37 VCCGT41 VCCGT120 BJ26
AE32 VCC41 VCC104 AM36 U31 VCC165 AY38 VCCGT42 VCCGT121 BJ27
AE35 VCC42 VCC105 AN13 U32 VCC166 BA13 VCCGT43 VCCGT122 BJ37
AE36 VCC43 VCC106 AN14 U33 VCC167 BA14 VCCGT44 VCCGT123 BJ38
AE37 VCC44 VCC107 AN31 U34 VCC168 BA29 VCCGT45 VCCGT124 BK16
AE38 VCC45 VCC108 AN32 U35 VCC169 BA30 VCCGT46 VCCGT125 BK17
AF29 VCC46 VCC109 AN33 U36 VCC170 BA31 VCCGT47 VCCGT126 BK19
AF30 VCC47 VCC110 AN34 V13 VCC171 BA32 VCCGT48 VCCGT127 BK20
AF31 VCC48 VCC111 AN35 V14 VCC172 BA33 VCCGT49 VCCGT128 BK21
AF32 VCC49 VCC112 AN36 V31 VCC173 BA34 VCCGT50 VCCGT129 BK23
AF33 VCC50 VCC113 AN37 V32 VCC174 BA35 VCCGT51 VCCGT130 BK24

m
AF34 VCC51 VCC114 AN38 V33 VCC175 BA36 VCCGT52 VCCGT131 BK26
AF35 VCC52 VCC115 AP13 V34 VCC176 BB13 VCCGT53 VCCGT132 BK27
AF36 VCC53 VCC116 AP30 V35 VCC177 BB14 VCCGT54 VCCGT133 BL15
AF37 VCC54 VCC117 AP31 V36 VCC178 BB31 VCCGT55 VCCGT134 BL16
AF38 VCC55 VCC118 AP32 V37 VCC179 BB32 VCCGT56 VCCGT135 BL17
AG14 VCC56 VCC119 AP35 V38 VCC180 BB33 VCCGT57 VCCGT136 BL23
AG31 VCC57 VCC120 AP36 W13 VCC181 BB34 VCCGT58 VCCGT137 BL24
VCC58 VCC121 VCC182 VCCGT59 VCCGT138

co
AG32 AP37 W14 BB35 BL25
AG33 VCC59 VCC122 AP38 W29 VCC183 BB36 VCCGT60 VCCGT139 BL26
AG34 VCC60 VCC123 K13 W30 VCC184 BB37 VCCGT61 VCCGT140 BL27
AG35 VCC61 VCC124 W31 VCC185 BB38 VCCGT62 VCCGT141 BL28
AG36 VCC62 W32 VCC186 BC29 VCCGT63 VCCGT142 BL36
VCC63 VCC187 10 OF 13 BC30 VCCGT64 VCCGT143 BL37
COFFEELAKE-H-CPU_BGA1440 BC31 VCCGT65 VCCGT144 BM15
BC32 VCCGT66 VCCGT145 BM16
VCCCORE_SENSE @ VCCGT67 VCCGT146
AG37 BC35 BM17
VCC_SENSE AG38 VSSCORE_SENSE BC36 VCCGT68 VCCGT147 BM36

s.
C 9 OF 13 VSS_SENSE BC37 VCCGT69 VCCGT148 BM37 C
COFFEELAKE-H-CPU_BGA1440 BC38 VCCGT70 VCCGT149 BN15
BD13 VCCGT71 VCCGT150 BN16
@ VCCGT72 VCCGT151
BD14 BN17
BD29 VCCGT73 VCCGT152 BN36
BD30 VCCGT74 VCCGT153 BN37

ic
BD31 VCCGT75 VCCGT154 BN38
BD32 VCCGT76 VCCGT155 BP15 CRB place to CPU
CRB place to CPU BD33 VCCGT77 VCCGT156 BP16
BD34 VCCGT78 VCCGT157 BP17 VCCGFXCORE
VCCCPUCORE
BP37 VCCGT79 VCCGT158 BR37
VCCGT_SENSE
VCC_SENSE BP38 VCCGT159 VCCGT164 BT15

at
VCCGT160 VCCGT165

1
BR15 BT16 RC60
BR16 VCCGT161 VCCGT166 BT17 100_0402_1%
1

RC59 BR17 VCCGT162 VCCGT167 BT37

100_0402_1% VCCGT163 VCCGT168

2
AH37 VSSGT_SENSE
VSSGT_SENSE AH38 VCCGT_SENSE 63 VCCGT_SENSE
2

VCCGT_SENSE
11 OF 13

em
63 VSSGT_SENSE
VCCCORE_SENSE COFFEELAKE-H-CPU_BGA1440

1
63 VCCCORE_SENSE @
RC63
100_0402_1%

2
VSSCORE_SENSE
63 VSSCORE_SENSE
1

ch
RC62
100_0402_1%
2

VCCGFXCORE

kS
10uF 10pcs，CD 1pcs

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

1 1 1 1 1 1 1 1 1 1

CC98

CC108

CC107

CC110

CC106

CC105

CC104

CC102

CC103

CC109
CD@
B
oo 2 2 2 2 2 2 2 2 2 2 B

VCCCPUCORE

10uF 21pcs,CD 4pcs

1uF 12pcs，CD 2pcs
10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
eb

1 1
1 1 1 1 CD75 CD76
CC62

CC80

CC79

CC82

CC78

CC77

CC76

CC75

CC81

CC91

CC88

CC92

CC89

CC86

CC87

CC93

CC85

33P_0402_50V8J 33P_0402_50V8J
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 RF_NS@ RF_NS@
CD@ CC74

CD@ CC83

CD@ CC84

CD@ CC90

2 2
2 2 2 2

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1
CD77 CD78

CH157

CH158

CH159

CH160

CH162

CH161

CH164

CH163

CH165

CH167

CH166

CH169
33P_0402_50V8J 33P_0402_50V8J

RF_NS@

RF_NS@
2 2 2 2 2 2 2 2 2 2 2 2 2 2

CD@

CD@
ot

Near CPU
Near CPU
1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K
N

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1U_0201_6.3V6K

1U_0201_6.3V6K

1 1
CH93

CH94

CH95

CH96

CH97

CH98

CH99

CH100

CH101

CH102

CH103

CH104

CH105

CH106

CH107

CH108

CH109

CH110

CH111

CH112

CH113

CH114

CH115

CH116
CD@

CD@

CD@

CD@

CD@

CD@

CD@

CD@

CD@

CD@

CD@

CD@

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
2 2
CD@

CD@

1uF 48pcs,CD 3pcs，24pcs @(delete6pcs)

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1 1 1
CH121

CH122

CH123

CH124

CH125

CH126

CH127

CH128

CH129

CH130

CH131

CH132

CH133

CH134

CH135

CH136

CH137

CH138
CD@

CD@

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
2 2 2
A
@

A
@

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/26 Deciphered Date 2018/09/20 CPU (5/7) PWR, BYPASS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
D 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FG541/FG741
Date: Tuesday, March 26, 2019 Sheet 9 of 69
5 4 3 2 1
 5 4 3 2 1

10uF 7pcs
VCCSA

VCCSA +1.2V
UC1L

J30 AA6

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

VCCSA1 VDDQ1 1 1 1 1 1 1 1 1 1
K29 AE12 CD79 CD80
K30 VCCSA2 VDDQ2 AF5

CC136

CC137

CC138

CC139

CC140

CC141

CC142
33P_0402_50V8J 33P_0402_50V8J
K31 VCCSA3 VDDQ3 AF6 RF_NS@ RF_NS@

CD@
K32 VCCSA4 VDDQ4 AG5 2 2 2 2 2 2 2 2 2
+1.2V
K33 VCCSA5 VDDQ5 AG9
K34 VCCSA6 VDDQ6 AJ12
K35 VCCSA7 VDDQ7 AL11

10U_0603_6.3V6M
L31 VCCSA8 VDDQ8 AP6
VCCSA9 VDDQ9 1
L32 AP7
L35 VCCSA10 VDDQ10 AR12

CC172
D
L36
L37
L38
VCCSA11
VCCSA12
VCCSA13
VDDQ11
VDDQ12
VDDQ13
AR6
AT12
AW6
2 Near CPU D

M29 VCCSA14 VDDQ14 AY6

1U_0402_6.3V6K
VCCSA15 VDDQ15 1
M30 J5
M31 VCCSA16 VDDQ16 J6

CH223
M32 VCCSA17 VDDQ17 K12
1uF 1pcs

CD@
M33 VCCSA18 VDDQ18 K6 2
M34 VCCSA19 VDDQ19 L12
M35 VCCSA20 VDDQ20 L6
M36 VCCSA21 VDDQ21 R6
VCCIO VCCSA22 VDDQ22 T6
VDDQ23 W6
VDDQ24 Y12
AG12 VDDQ25
G15 VCCIO1 +1.2V
G17 VCCIO2
G19 VCCIO3 BH13
G21 VCCIO4 VCCPLL_OC1 BJ13
VCCIO5 VCCPLL_OC2
+1.2V
VDDQ DECOUPLING
10uF 11pcs,CD 1pcs
10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

H15 G11

m
1 1 1 1 1 1 VCCIO6 VCCPLL_OC3 VCCST
H16
H17 VCCIO7 H30
CC1397

CC1396

CC1395

CC147

CC148

CC149

1U_0402_6.3V6K

1U_0402_6.3V6K
VCCIO8 VCCST 1 1
H19 VCCSTG
CD@

CD@

CD@

2 2 2 2 2 2 H20 VCCIO9 H29

CC150

CH252

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
VCCIO10 VCCSTG2

co
H21

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

CC1394
VCCIO11 2 2 1 1 1 1 1 1 1 1 1 1 1
H26 G30

1U_0402_6.3V6K

1U_0402_6.3V6K
VCCIO12 VCCSTG1 VCCST 1 1
H27

1U_0402_6.3V6K

CC51

CC52

CC53

CC54

CC55

CC56

CC57

CC58

CC59

CC60
VCCIO13 1
J15 H28

CH249

CH250

CD@
J16 VCCIO14 VCCPLL1 J28 2 2 2 2 2 2 2 2 2 2 2

CH242
J17 VCCIO15 VCCPLL2 2 2
J19 VCCIO16 2

s.
J20 VCCIO17 M38 VCCSA_SENSE
J21 VCCIO18 VCCSA_SENSE M37 VSSSA_SENSE
J26 VCCIO19 VSSSA_SENSE
VCCIO20 H14 VCC_IO_SEN
22uF 4pcs
J27

ic
10uF 6pcs,CD 3pcs

C10120
VCCIO21 VCCIO_SENSE J14 VSSIO_SENSE_R

1U_0402_6.3V6K
VSSIO_SENSE 1 1
C 12 OF 13 C

CH251

@
COFFEELAKE-H-CPU_BGA1440

at
47U_0805_6.3V6-M

CC63
22U_0603_6.3V6-M

22U_0603_6.3V6-M
CC64
22U_0603_6.3V6-M

CC65
22U_0603_6.3V6-M

CC66
@ 2 2 1 1 1 1

2 2 2 2
Follow PDG Rev1.0 0828SF

em
ch
CRB place to CPU CRB place to CPU
VCCSA VCCIO
VCCSA_SENSE VCCIO_SENSE

kS
1

1
RC151 RC155
100_0402_1% 100_0402_1%
@
oo
2

2
63 VCCSA_SENSE 62 VCC_IO_SEN
VSSIO_SENSE_R
63 VSSSA_SENSE
1

1
eb

RC149 RC153
@
100_0402_1% 100_0402_1%
2

2
B B
ot
N

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/26 Deciphered Date 2018/09/20 CPU (6/7) PWR, BYPASS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
FG541/FG741 1.0

Date: Tuesday, March 26, 2019 Sheet 10 of 69

5 4 3 2 1
 5 4 3 2 1

D D
UC1F UC1G UC1H
A10 AK4 AW5 BJ15 BN4 F15
A12 VSS_1 VSS_82 AL10 AY12 VSS_163 VSS_244 BJ18 BN7 VSS_325 VSS_409 F17
A16 VSS_2 VSS_83 AL12 AY33 VSS_164 VSS_245 BJ22 BP12 VSS_326 VSS_410 F19
A18 VSS_3 VSS_84 AL14 AY34 VSS_165 VSS_246 BJ25 BP14 VSS_327 VSS_411 F2
A20 VSS_4 VSS_85 AL33 B9 VSS_166 VSS_247 BJ29 BP18 VSS_328 VSS_412 F21
A22 VSS_5 VSS_86 AL34 BA10 VSS_167 VSS_248 BJ30 BP21 VSS_329 VSS_413 F23
A24 VSS_6 VSS_87 AL4 BA11 VSS_168 VSS_249 BJ31 BP24 VSS_330 VSS_414 F25
A26 VSS_7 VSS_88 AL7 BA12 VSS_169 VSS_250 BJ32 BP25 VSS_331 VSS_415 F27
A28 VSS_8 VSS_89 AL8 BA37 VSS_170 VSS_251 BJ33 BP26 VSS_332 VSS_416 F29
A30 VSS_9 VSS_90 AL9 BA38 VSS_171 VSS_252 BJ34 BP29 VSS_333 VSS_417 F3
A6 VSS_10 VSS_91 AM1 BA6 VSS_172 VSS_253 BJ35 BP33 VSS_334 VSS_418 F31
A9 VSS_11 VSS_92 AM12 BA7 VSS_173 VSS_254 BJ36 BP34 VSS_335 VSS_419 F36
AA12 VSS_12 VSS_93 AM2 BA8 VSS_174 VSS_255 BK13 BP7 VSS_336 VSS_420 F4
AA29 VSS_13 VSS_94 AM3 BA9 VSS_175 VSS_256 BK14 BR12 VSS_337 VSS_421 F5
AA30 VSS_14 VSS_95 AM37 BB1 VSS_176 VSS_257 BK15 BR14 VSS_338 VSS_422 F8
AB33 VSS_15 VSS_96 AM38 BB12 VSS_177 VSS_258 BK18 BR18 VSS_339 VSS_423 F9
AB34 VSS_16 VSS_97 AM4 BB2 VSS_178 VSS_259 BK22 BR21 VSS_340 VSS_424 G10
AB6 VSS_17 VSS_98 AM5 BB29 VSS_179 VSS_260 BK25 BR24 VSS_341 VSS_425 G12
AC1 VSS_18 VSS_99 AN12 BB3 VSS_180 VSS_261 BK29 BR25 VSS_342 VSS_426 G14

m
AC12 VSS_19 VSS_100 AN29 BB30 VSS_181 VSS_262 BK6 BR26 VSS_343 VSS_427 G16
AC2 VSS_20 VSS_101 AN30 BB4 VSS_182 VSS_263 BL13 BR29 VSS_344 VSS_428 G18
AC3 VSS_21 VSS_102 AN5 BB5 VSS_183 VSS_264 BL14 BR34 VSS_345 VSS_429 G20
AC37 VSS_22 VSS_103 AN6 BB6 VSS_184 VSS_265 BL18 BR36 VSS_346 VSS_430 G22
VSS_23 VSS_104 VSS_185 VSS_266 VSS_347 VSS_431

co
AC38 AP10 BC12 BL19 BR7 G23
AC4 VSS_24 VSS_105 AP11 BC13 VSS_186 VSS_267 BL20 BT12 VSS_348 VSS_432 G24
AC5 VSS_25 VSS_106 AP12 BC14 VSS_187 VSS_268 BL21 BT14 VSS_349 VSS_433 G26
AC6 VSS_26 VSS_107 AP33 BC33 VSS_188 VSS_269 BL22 BT18 VSS_350 VSS_434 G28
AD10 VSS_27 VSS_108 AP34 BC34 VSS_189 VSS_270 BL29 BT21 VSS_351 VSS_435 G4
AD11 VSS_28 VSS_109 AP8 BC6 VSS_190 VSS_271 BL33 BT24 VSS_352 VSS_436 G5
AD12 VSS_29 VSS_110 AP9 BD10 VSS_191 VSS_272 BL35 BT26 VSS_353 VSS_437 G6

s.
AD29 VSS_30 VSS_111 AR1 BD11 VSS_192 VSS_273 BL38 BT29 VSS_354 VSS_438 G8
AD30 VSS_31 VSS_112 AR13 BD12 VSS_193 VSS_274 BL6 BT32 VSS_355 VSS_439 G9
AD6 VSS_32 VSS_113 AR14 BD37 VSS_194 VSS_275 BM11 BT5 VSS_356 VSS_440 H11
AD8 VSS_33 VSS_114 AR2 BD6 VSS_195 VSS_276 BM12 C11 VSS_357 VSS_441 H12

ic
AD9 VSS_34 VSS_115 AR29 BD7 VSS_196 VSS_277 BM13 C13 VSS_358 VSS_442 H18
AE33 VSS_35 VSS_116 AR3 BD8 VSS_197 VSS_278 BM14 C15 VSS_359 VSS_443 H22
AE34 VSS_36 VSS_117 AR30 BD9 VSS_198 VSS_279 BM18 C17 VSS_360 VSS_444 H25
C C
AE6 VSS_37 VSS_118 AR31 BE1 VSS_199 VSS_280 BM2 C19 VSS_361 VSS_445 H32

at
AF1 VSS_38 VSS_119 AR32 BE2 VSS_200 VSS_281 BM21 C21 VSS_362 VSS_446 H35
AF12 VSS_39 VSS_120 AR33 BE29 VSS_201 VSS_282 BM22 C23 VSS_363 VSS_447 J10
AF13 VSS_40 VSS_121 AR34 BE3 VSS_202 VSS_283 BM23 C25 VSS_364 VSS_448 J18
AF14 VSS_41 VSS_122 AR35 BE30 VSS_203 VSS_284 BM24 C27 VSS_365 VSS_449 J22
AF2 VSS_42 VSS_123 AR36 BE4 VSS_204 VSS_285 BM25 C29 VSS_366 VSS_450 J25

em
AF3 VSS_43 VSS_124 AR37 BE5 VSS_205 VSS_286 BM26 C31 VSS_367 VSS_451 J32
AF4 VSS_44 VSS_125 AR38 BE6 VSS_206 VSS_287 BM27 C37 VSS_368 VSS_452 J33
AG10 VSS_45 VSS_126 AR4 BF12 VSS_207 VSS_288 BM28 C5 VSS_369 VSS_453 J36
AG11 VSS_46 VSS_127 AR5 BF33 VSS_208 VSS_289 BM29 C8 VSS_370 VSS_454 J4
AG13 VSS_47 VSS_128 AT29 BF34 VSS_209 VSS_290 BM3 C9 VSS_371 VSS_455 J7
AG29 VSS_48 VSS_129 AT30 BF6 VSS_210 VSS_291 BM33 D10 VSS_372 VSS_456 K1
AG30 VSS_49 VSS_130 AT6 BG12 VSS_211 VSS_292 BM35 D12 VSS_373 VSS_457 K10
AG6 VSS_50 VSS_131 AU10 BG13 VSS_212 VSS_293 BM38 D14 VSS_374 VSS_458 K11

ch
AG7 VSS_51 VSS_132 AU11 BG14 VSS_213 VSS_294 BM5 D16 VSS_375 VSS_459 K2
AG8 VSS_52 VSS_133 AU12 BG37 VSS_214 VSS_295 BM6 D18 VSS_376 VSS_460 K3
AH12 VSS_53 VSS_134 AU33 BG38 VSS_215 VSS_296 BM7 D20 VSS_377 VSS_461 K38
AH33 VSS_54 VSS_135 AU34 BG6 VSS_216 VSS_297 BM8 D22 VSS_378 VSS_462 K4
AH34 VSS_55 VSS_136 AU6 BH1 VSS_217 VSS_298 BM9 D24 VSS_379 VSS_463 K5
AH35 VSS_56 VSS_137 AU7 BH10 VSS_218 VSS_299 BN12 D26 VSS_380 VSS_464 K7

kS
AH36 VSS_57 VSS_138 AU8 BH11 VSS_219 VSS_300 BN14 D28 VSS_381 VSS_465 K8
AH6 VSS_58 VSS_139 AU9 BH12 VSS_220 VSS_301 BN18 D3 VSS_382 VSS_466 K9
AJ1 VSS_59 VSS_140 AV37 BH14 VSS_221 VSS_302 BN19 D30 VSS_383 VSS_467 L29
AJ13 VSS_60 VSS_141 AV38 BH2 VSS_222 VSS_303 BN2 D33 VSS_384 VSS_468 L30
AJ2 VSS_61 VSS_142 AW1 BH3 VSS_223 VSS_304 BN20 D6 VSS_385 VSS_469 L33
AJ3 VSS_62 VSS_143 AW12 BH4 VSS_224 VSS_305 BN21 D9 VSS_386 VSS_470 L34
VSS_63 VSS_144 VSS_225 VSS_306 VSS_387 VSS_471
AJ37 AW2
oo BH5 BN24 E34 M12
AJ38 VSS_64 VSS_145 AW29 BH6 VSS_226 VSS_307 BN29 E35 VSS_388 VSS_472 M13
AJ4 VSS_65 VSS_146 AW3 BH7 VSS_227 VSS_308 BN30 E38 VSS_389 VSS_473 N10
AJ5 VSS_66 VSS_147 AW30 BH8 VSS_228 VSS_309 BN31 E4 VSS_390 VSS_474 N11
AJ6 VSS_67 VSS_148 AW4 BH9 VSS_229 VSS_310 BN34 E9 VSS_391 VSS_475 N12
W4 VSS_68 VSS_149 U6 T2 VSS_230 VSS_311 P38 N3 VSS_392 VSS_476 N2
W5 VSS_69 VSS_150 V12 T3 VSS_231 VSS_312 P6 N33 VSS_393 VSS_477 BT8
eb

Y10 VSS_70 VSS_151 V29 T33 VSS_232 VSS_313 R12 N34 VSS_394 VSS_478 BR9
Y11 VSS_71 VSS_152 V30 T34 VSS_233 VSS_314 R29 N4 VSS_395 VSS_479
Y13 VSS_72 VSS_153 A14 T4 VSS_234 VSS_315 AY14 N5 VSS_396 A3
Y14 VSS_73 VSS_154 AD7 T5 VSS_235 VSS_316 BD38 N6 VSS_397 VSS_A3 A34
B
Y37 VSS_74 VSS_155 V6 T7 VSS_236 VSS_317 R30 N7 VSS_398 VSS_A34 A4 B
Y38 VSS_75 VSS_156 W1 T8 VSS_237 VSS_318 T1 N8 VSS_399 VSS_A4 B3
VSS_76 VSS_157 VSS_238 VSS_319 VSS_400 VSS_B3
ot

Y7 W12 T9 T10 N9 B37

Y8 VSS_77 VSS_158 W2 U37 VSS_239 VSS_320 T11 P12 VSS_401 VSS_B37 BR38
Y9 VSS_78 VSS_159 W3 U38 VSS_240 VSS_321 T12 P37 VSS_402 VSS_BR38 BT3
AK29 VSS_79 VSS_160 W33 BJ12 VSS_241 VSS_322 T13 M14 VSS_403 VSS_BT3 BT35
AK30 VSS_80 VSS_161 W34 BJ14 VSS_242 VSS_323 T14 M6 VSS_404 VSS_BT35 BT36
VSS_81 6 OF 13 VSS_162 VSS_2437 OF 13 VSS_324 N1 VSS_405 VSS_BT36 BT4
N

COFFEELAKE-H-CPU_BGA1440 COFFEELAKE-H-CPU_BGA1440 F11 VSS_406 VSS_BT4 C2

F13 VSS_407 VSS_C2 D38
@ @ VSS_4088 OF 13 VSS_D38
COFFEELAKE-H-CPU_BGA1440
@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/26 Deciphered Date 2018/09/20 CPU (6/7) PWR, VSS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
FG541/FG741 1.0

Date: Tuesday, March 26, 2019 Sheet 11 of 69

5 4 3 2 1
 5 4 3 2 1

+1.2V

DDRA_DQ[0..63]
DDRA_DQ[0..63] 7
UD1 @ UD2 @ DDRA_DQS#[0..7]
1 DDRA_DQS#[0..7] 7

1
@ MD@
DDRA_MA0 P3 G2 DDRA_DQ2 DDRA_MA0 P3 G2 DDRA_DQ18 CD119 RD45 DDRA_DQS[0..7]
DDRA_MA1 P7 A0 DQ0 F7 DDRA_DQ3 DDRA_MA1 P7 A0 DQ0 F7 DDRA_DQ19 DDRA_DQS[0..7] 7
0.1u_0201_10V6K 1.8K_0402_1%
DDRA_MA2 R3 A1 DQ1 H3 DDRA_DQ6 DDRA_MA2 R3 A1 DQ1 H3 DDRA_DQ22 2 DDRA_MA[0..13]
DDRA_MA3 N7 A2 DQ2 H7 DDRA_DQ1 DDRA_MA3 N7 A2 DQ2 H7 DDRA_DQ21 DDRA_MA[0..13] 7
A3 DQ3 A3 DQ3

2
DDRA_MA4 N3 H2 DDRA_DQ7 DDRA_MA4 N3 H2 DDRA_DQ23
DDRA_MA5 P8 A4 DQ4 H8 DDRA_DQ0 DDRA_MA5 P8 A4 DQ4 H8 DDRA_DQ17 +0.6VS
DDRA_MA6 P2 A5 DQ5 J3 DDRA_DQ4 DDRA_MA6 P2 A5 DQ5 J3 DDRA_DQ16 RD46 1 2 MD@ +VREF_CA_MD
DDRA_MA7 R8 A6 DQ6 J7 DDRA_DQ5 DDRA_MA7 R8 A6 DQ6 J7 DDRA_DQ20 7 DDR_SA_VREFCA
2.7_0402_1%
DDRA_MA8 R2 A7 DQ7 A3 DDRA_DQ11 DDRA_MA8 R2 A7 DQ7 A3 DDRA_DQ30
DDRA_MA9 A8 DQ8 DDRA_DQ13 DDRA_MA9 A8 DQ8 DDRA_DQ28
1

1
R7 B8 R7 B8 MD@ 1
DDRA_MA10 M3 A9 DQ9 C3 DDRA_DQ14 DDRA_MA10 M3 A9 DQ9 C3 DDRA_DQ26 CD111 RD47 @
DDRA_MA11 T2 A10/AP DQ10 C7 DDRA_DQ12 DDRA_MA11 T2 A10/AP DQ10 C7 DDRA_DQ25 0.022U_0201_6.3V6-K MD@ 1.8K_0402_1% CD112 DDRA_CS0# RD51 1 MD@ 2 36_0402_1%
DDRA_MA12 M7 A11 DQ11 C2 DDRA_DQ15 DDRA_MA12 M7 A11 DQ11 C2 DDRA_DQ31 2 0.1u_0201_10V6K DDRA_ODT0 RD52 1 MD@ 2 36_0402_1%
DDRA_MA13 T8 A12/BC_N DQ12 C8 DDRA_DQ8 DDRA_MA13 T8 A12/BC_N DQ12 C8 DDRA_DQ24 2
A13 DQ13 A13 DQ13

2
DDRA_DQ10 DDRA_DQ27 DDRA_CKE0

1
D3 D3 RD53 1 MD@ 2 36_0402_1%
D
DDRA_MA14_WE# L2 DQ14 D7 DDRA_DQ9 DDRA_MA14_WE# L2 DQ14 D7 DDRA_DQ29 RD48 D
7 DDRA_MA14_WE# DDRA_MA15_CAS# WE_N/A14 DQ15 DDRA_MA15_CAS# WE_N/A14 DQ15 DDRA_MA0
M8 M8 24.9_0402_1% MD@ RD54 1 MD@ 2 36_0402_1%
7 DDRA_MA15_CAS# DDRA_MA16_RAS# L8 CAS_N/A15 +1.2V DDRA_MA16_RAS# L8 CAS_N/A15 +1.2V DDRA_MA1 1 2
RD55 MD@ 36_0402_1%
7 DDRA_MA16_RAS# RAS_N/A16 D1 RAS_N/A16 D1 DDRA_MA2 1 2
RD56 MD@ 36_0402_1%
VDD1 VDD1

2
DDRA_CLK0# K8 J1 DDRA_CLK0# K8 J1 DDRA_MA3 RD57 1 MD@ 2 36_0402_1%
7 DDRA_CLK0# DDRA_CLK0 CK_C VDD2 DDRA_CLK0 CK_C VDD2
K7 L1 K7 L1
7 DDRA_CLK0 CK_T VDD3 CK_T VDD3 DDRA_MA4
R1 R1 RD58 1 MD@ 2 36_0402_1%
DDRA_CKE0 K2 VDD4 B3 DDRA_CKE0 K2 VDD4 B3 DDRA_MA5 RD59 1 MD@ 2 36_0402_1%
7 DDRA_CKE0 CKE VDD5 CKE VDD5 DDRA_MA6
G7 G7 RD60 1 MD@ 2 36_0402_1%
DDRA_DQS#0 F3 VDD6 B9 DDRA_DQS#2 F3 VDD6 B9 DDRA_MA7 RD61 1 MD@ 2 36_0402_1%
DDRA_DQS0 G3 LDQS_C VDD7 J9 DDRA_DQS2 G3 LDQS_C VDD7 J9
DDRA_DQS#1 A7 LDQS_T VDD8 L9 DDRA_DQS#3 A7 LDQS_T VDD8 L9 UD1_DDRA_UZQ R10145 1 SDP@ 2 0_0402_5% DDRA_MA8 RD62 1 MD@ 2 36_0402_1%
+1.2V DDRA_DQS1 B7 UDQS_C VDD9 T9 +1.2V DDRA_DQS3 B7 UDQS_C VDD9 T9 DDRA_MA9 RD63 1 MD@ 2 36_0402_1%
UDQS_T VDD10 UDQS_T VDD10 DDRA_MA10 RD64 1 MD@ 2 36_0402_1%
DDRA_DM1 DDRA_DM3 RD228 1 DDP@ 2 240_0402_1% DDRA_MA11
RD65 1 @ 2 0_0402_5% E2 A1 RD66 1 @ 2 0_0402_5% E2 A1 RD67 1 MD@ 2 36_0402_1%
RD68 1 @ 2 0_0402_5% DDRA_DM0 E7 NF/UDM_N/UDBI_N VDDQ1 C1 RD69 1 @ 2 0_0402_5% DDRA_DM2 E7 NF/UDM_N/UDBI_N VDDQ1 C1
NF/LDM_N/LDBI_N VDDQ2 G1 NF/LDM_N/LDBI_N VDDQ2 G1 UD2_DDRA_UZQ R10147 1 SDP@ 2 0_0402_5% DDRA_MA12 RD70 1 MD@ 2 36_0402_1%
DDRA_BA0 N2 VDDQ3 F2 DDRA_BA0 N2 VDDQ3 F2 DDRA_MA13 RD71 1 MD@ 2 36_0402_1%
7 DDRA_BA0 DDRA_BA1 BA0 VDDQ4 DDRA_BA1 BA0 VDDQ4 DDRA_MA14_WE# RD72
N8 J2 N8 J2 1 MD@ 2 36_0402_1%
7 DDRA_BA1 BA1 VDDQ5 BA1 VDDQ5 RD231 1 DDP@ 2 240_0402_1% DDRA_MA15_CAS#RD73
F8 F8 1 MD@ 2 36_0402_1%
DDRA_ACT# L3 VDDQ6 J8 DDRA_ACT# L3 VDDQ6 J8
7 DDRA_ACT# DDRA_CS0# ACT_N VDDQ7 DDRA_CS0# ACT_N VDDQ7 UD3_DDRA_UZQ
L7 A9 L7 A9 R10148 1 SDP@ 2 0_0402_5%
7 DDRA_CS0# DDRA_ALERT# P9 CS_N VDDQ8 D9 DDRA_ALERT# P9 CS_N VDDQ8 D9 DDRA_MA16_RAS#RD74 1 MD@ 2 36_0402_1%
7 DDRA_ALERT# ALERT_N VDDQ9 G9 +2.5V_DDR ALERT_N VDDQ9 G9 +2.5V_DDR DDRA_BG0 1 MD@ 2
1 DDP@ 2 240_0402_1% RD75 36_0402_1%
DDRA_BG0 VDDQ10 DDRA_BG0 VDDQ10 RD232 DDRA_BA0
M2 M2 RD76 1 MD@ 2 36_0402_1%
7 DDRA_BG0 BG0 BG0 DDRA_BA1
B1 B1 RD77 1 MD@ 2 36_0402_1%
DDRA_ODT0 K3 VPP1 R9 DDRA_ODT0 K3 VPP1 R9 UD4_DDRA_UZQ R10151 1 SDP@ 2 0_0402_5%
7 DDRA_ODT0 ODT VPP2 ODT VPP2 DDRA_ACT# 1 MD@ 2
RD78 36_0402_1%
DDRA_PAR T3 M1 +VREF_CA_MD DDRA_PAR T3 M1 +VREF_CA_MD DDRA_PAR RD79 1 MD@ 2 36_0402_1%

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
7 DDRA_PAR PAR VREFCA PAR VREFCA RD233 1 DDP@ 2 240_0402_1%
1 1 1 1
RD94 1 MD@ 2 10K_0402_5% TEN_UD1 N9 E1 MD@ CD@ RD95 1 MD@ 2 10K_0402_5% TEN_UD2 N9 E1 MD@ MD@ DDRA_BG1_R RD234 1 DDP@ 2 36_0402_1%

0.1u_0201_10V6K

0.1u_0201_10V6K
.047U_0201_6.3V6K

.047U_0201_6.3V6K
TEN VSS1 TEN VSS1 +0.6VS
K1 1 1 K1 1 1
PCH_DRAMRST# P1 VSS2 N1 @ PCH_DRAMRST# P1 VSS2 N1 MD@ @ +1.2V

m
13,16 PCH_DRAMRST# RESET_N VSS3 T1 2 2 RESET_N VSS3 T1 2 2
VSS4 VSS4

2
F1 B2 MD@ @ F1 B2

CD121

CD123

CD124

CD125
0.1u_0201_10V6K

0.1u_0201_10V6K
@1 H1 VSSQ1 VSS5 G8 2 2 H1 VSSQ1 VSS5 G8 2 2 RD98
VSSQ2 VSS6 1 VSSQ2 VSS6 DDRA_ALERT# RD86 1 MD@ 2 49.9_0402_1%
A2 E9 UD1_DDRA_UZQ A2 E9 UD2_DDRA_UZQ @

CD113

CD120

CD114

CD122
VSSQ3 VSS7 VSSQ3 VSS7 0_0402_5%
D2 K9 D2 K9
E3 VSSQ4 VSS8 M9 DDRA_BG1_R E3 VSSQ4 VSS8 M9 DDRA_BG1_R
VSSQ5 VSS9 VSSQ5 VSS9

1
2 A8 2 A8 DDRA_CLK0# RD49 1 MD@ 2 36_0402_1%
CD47

CD48

co
D8 VSSQ6 T7 D8 VSSQ6 T7
E8 VSSQ7 NC E8 VSSQ7 NC C10121
VSSQ8 VSSQ8
1

1
C9 C9 1 2
H9 VSSQ9 RD101 H9 VSSQ9 RD102
VSSQ10 0_0402_5% VSSQ10 0_0402_5% DDRA_CLK0 RD50 1 MD@ 2 36_0402_1% 0.01U_0201_10V6K
C C
F9 DDP@ F9 DDP@ MD@
ZQ ZQ
2

2
1

1
Follow 1.0PDG add termination 0.01UF_0201 capacitor

s.
MD@ RD39 MT40A512M16HA083EA_FBGA96 RD40 MT40A512M16HA083EA_FBGA96
240_0402_1% MD@ 240_0402_1%
between DDRA_CLK0 and DDRA_CLK0#
2

2
R13 DDP@ 0R short Terminate CLK signals PH to VDDQ --SF0904

ic
DDRA_BG1_R R105751 2 0_0402_5% DDRA_BG1
DDRA_BG1 7
DDP@

1
+1.2V
R10576 (1uF_0402_6.3V) *16

at
0_0402_5% Place 4 near each DRAM
SDP@

2
R17 SDP@ 0R PD

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
UD3 @ 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
UD4 @ MD@ CD@ MD@ MD@ CD@ CD@ CD@ MD@ MD@ MD@ MD@ CD@ MD@ CD@ MD@ MD@

em
DDRA_MA0 P3 G2 DDRA_DQ47
DDRA_MA1 P7 A0 DQ0 F7 DDRA_DQ45 DDRA_MA0 P3 G2 DDRA_DQ59
DDRA_MA2 R3 A1 DQ1 H3 DDRA_DQ42 DDRA_MA1 P7 A0 DQ0 F7 DDRA_DQ56 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
DDRA_MA3 N7 A2 DQ2 H7 DDRA_DQ41 DDRA_MA2 R3 A1 DQ1 H3 DDRA_DQ63

CD126

CD127

CD128

CD129

CD130

CD131

CD132

CD133

CD134

CD135

CD136

CD137

CD138

CD139

CD140

CD141
DDRA_MA4 N3 A3 DQ3 H2 DDRA_DQ43 DDRA_MA3 N7 A2 DQ2 H7 DDRA_DQ60
DDRA_MA5 P8 A4 DQ4 H8 DDRA_DQ40 DDRA_MA4 N3 A3 DQ3 H2 DDRA_DQ62
DDRA_MA6 P2 A5 DQ5 J3 DDRA_DQ46 DDRA_MA5 P8 A4 DQ4 H8 DDRA_DQ61
DDRA_MA7 R8 A6 DQ6 J7 DDRA_DQ44 DDRA_MA6 P2 A5 DQ5 J3 DDRA_DQ58
DDRA_MA8 R2 A7 DQ7 A3 DDRA_DQ34 DDRA_MA7 R8 A6 DQ6 J7 DDRA_DQ57
DDRA_MA9 R7 A8 DQ8 B8 DDRA_DQ37 DDRA_MA8 R2 A7 DQ7 A3 DDRA_DQ52
DDRA_MA10 M3 A9 DQ9 C3 DDRA_DQ39 DDRA_MA9 R7 A8 DQ8 B8 DDRA_DQ48

ch
DDRA_MA11 T2 A10/AP DQ10 C7 DDRA_DQ32 DDRA_MA10 M3 A9 DQ9 C3 DDRA_DQ55
DDRA_MA12 M7 A11 DQ11 C2 DDRA_DQ38 DDRA_MA11 T2 A10/AP DQ10 C7 DDRA_DQ54 +1.2V +1.2V
DDRA_MA13 A12/BC_N DQ12 DDRA_DQ33 DDRA_MA12 A11 DQ11 DDRA_DQ53
(1OuF_0603_6.3V) *5
T8 C8 M7 C2
A13 DQ13 D3 DDRA_DQ35 DDRA_MA13 T8 A12/BC_N DQ12 C8 DDRA_DQ50 Place around the DRAMs
DDRA_MA14_WE# L2 DQ14 D7 DDRA_DQ36 A13 DQ13 D3 DDRA_DQ51
DDRA_MA15_CAS# M8 WE_N/A14 DQ15 DDRA_MA14_WE# L2 DQ14 D7 DDRA_DQ49
DDRA_MA16_RAS# L8 CAS_N/A15 +1.2V DDRA_MA15_CAS# M8 WE_N/A14 DQ15
RAS_N/A16 D1 DDRA_MA16_RAS# L8 CAS_N/A15 +1.2V
DDRA_CLK0# K8 VDD1 J1 RAS_N/A16 D1

kS

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
DDRA_CLK0 K7 CK_C VDD2 L1 DDRA_CLK0# K8 VDD1 J1
CK_T VDD3 CK_C VDD2 1 1 1 1 1 1 1
B R1 DDRA_CLK0 K7 L1 CD@ CD@ MD@ MD@ CD@ CD109 CD110 B
DDRA_CKE0 K2 VDD4 B3 CK_T VDD3 R1 22P_0402_50V8-J 22P_0402_50V8-J
CKE VDD5 G7 DDRA_CKE0 K2 VDD4 B3 RF@ RF@
DDRA_DQS#5 F3 VDD6 B9 CKE VDD5 G7 2 2 2 2 2 2 2
LDQS_C VDD7 VDD6

CD142

CD143

CD144

CD145

CD146
DDRA_DQS5 G3 J9 DDRA_DQS#7 F3 B9
DDRA_DQS#4 A7 LDQS_T VDD8 L9 DDRA_DQS7 G3 LDQS_C VDD7 J9
+1.2V DDRA_DQS4 B7 UDQS_C VDD9 T9 DDRA_DQS#6 A7 LDQS_T VDD8 L9
UDQS_T VDD10 +1.2V DDRA_DQS6 B7 UDQS_C VDD9 T9
RD87 1 @ 2 0_0402_5% DDRA_DM4 E2 A1
oo UDQS_T VDD10
RD88 1 @ 2 0_0402_5% DDRA_DM5 E7 NF/UDM_N/UDBI_N VDDQ1 C1 RD89 1 @ 2 0_0402_5% DDRA_DM6 E2 A1
NF/LDM_N/LDBI_N VDDQ2 G1 RD90 1 @ 2 0_0402_5% DDRA_DM7 E7 NF/UDM_N/UDBI_N VDDQ1 C1
DDRA_BA0 N2 VDDQ3 F2 NF/LDM_N/LDBI_N VDDQ2 G1
DDRA_BA1 N8 BA0 VDDQ4 J2 DDRA_BA0 N2 VDDQ3 F2
BA1 VDDQ5 F8 DDRA_BA1 N8 BA0 VDDQ4 J2
DDRA_ACT# L3 VDDQ6 J8 BA1 VDDQ5 F8
DDRA_CS0# L7 ACT_N VDDQ7 A9 DDRA_ACT# L3 VDDQ6 J8
DDRA_ALERT# CS_N VDDQ8 DDRA_CS0# ACT_N VDDQ7 +2.5V_DDR
(1OuF_0603_6.3V) *3 +2.5V_DDR
P9 D9 L7 A9
Place around the DRAMs
eb

ALERT_N VDDQ9 G9 +2.5V_DDR DDRA_ALERT# P9 CS_N VDDQ8 D9

DDRA_BG0 M2 VDDQ10 ALERT_N VDDQ9 G9 +2.5V_DDR
BG0 B1 DDRA_BG0 M2 VDDQ10
DDRA_ODT0 K3 VPP1 R9 BG0 B1
ODT VPP2 DDRA_ODT0 K3 VPP1 R9

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
DDRA_PAR T3 M1 +VREF_CA_MD ODT VPP2
1 1 1 1 1
1U_0402_6.3V6K

1U_0402_6.3V6K

PAR VREFCA DDRA_PAR T3 M1 +VREF_CA_MD MD@ MD@ CD@ CD157 CD148

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 PAR VREFCA
RD96 1 MD@ 2 10K_0402_5% TEN_UD3 N9 E1 CD@ CD@ 22P_0402_50V8-J 22P_0402_50V8-J
0.1u_0201_10V6K

1 1
.047U_0201_6.3V6K

TEN VSS1 K1 RD97 1 MD@ 2 10K_0402_5% TEN_UD4 N9 E1 CD@ MD@ RF@ RF@
1 1

0.1u_0201_10V6K
.047U_0201_6.3V6K
ot

PCH_DRAMRST# P1 VSS2 N1 MD@ @ TEN VSS1 K1 2 2 2 2 2

RESET_N VSS3 VSS2 1 1

CD152

CD156

CD147
T1 2 2 PCH_DRAMRST# P1 N1 MD@ @
@ F1 VSS4 B2 RESET_N VSS3 T1 2 2
CD150

CD151
0.1u_0201_10V6K

H1 VSSQ1 VSS5 G8 2 2 @ F1 VSS4 B2

CD154

CD155
0.1u_0201_10V6K

1 VSSQ2 VSS6 VSSQ1 VSS5 2 2

A2 E9 UD3_DDRA_UZQ H1 G8
CD115

CD149

VSSQ3 VSS7 1 VSSQ2 VSS6

D2 K9 A2 E9 UD4_DDRA_UZQ

CD116

CD153
E3 VSSQ4 VSS8 M9 DDRA_BG1_R D2 VSSQ3 VSS7 K9
2 A8 VSSQ5 VSS9 E3 VSSQ4 VSS8 M9 DDRA_BG1_R
CD107

D8 VSSQ6 T7 2 A8 VSSQ5 VSS9

CD108

E8 VSSQ7 NC D8 VSSQ6 T7
C9 VSSQ8 E8 VSSQ7 NC
1

H9 VSSQ9 C9 VSSQ8 +0.6VS +0.6VS

(1uF_0402_6.3V) *8 (1OuF_0603_6.3V) *2

1
VSSQ10 RD99 H9 VSSQ9
F9 0_0402_5% VSSQ10 RD100 Place 2 near each DRAM Place around the DRAMs
ZQ DDP@ 0_0402_5%
F9
ZQ DDP@
1

RD43 MT40A512M16HA083EA_FBGA96
2

10U_0603_6.3V6M

10U_0603_6.3V6M
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
MD@ 240_0402_1% RD44 MT40A512M16HA083EA_FBGA96 1 1 1 1 1 1 1 1 1 1 1 1
MD@ 240_0402_1% MD@ MD@ CD@ CD@ MD@ MD@ MD@ CD168 CD169
A A
22P_0402_50V8-J 22P_0402_50V8-J
2

RF@ RF@
2

2 2 2 2 2 2 2 2 2 2 2 2

CD158

CD159

CD160

CD161

CD162

CD163

CD164

CD165

CD166

CD167
CD@ CD@ CD@

Security Classification LC Future Center Secret Data Title

Issued Date 2016/12/14 Deciphered Date 2018/09/20 DDR4 Memory Down

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FG541/FG741
Date: Tuesday, March 26, 2019 Sheet 12 of 69
5 4 3 2 1
 5 4 3 2 1

+1.2V

DDR4 SO-DIMM DDRB_DQ[0..63]

DDRB_DQ[0..63] 7

1
DDRB_DQS#[0..7] RD91
DDRB_DQS#[0..7] 7
+1.2V +1.2V +1.2V +1.2V +1.2V +1.2V +1.2V +1.2V 240_0402_1% @
JDDR1A DDRB_DQS[0..7] JDDR1B
DDRB_DQS[0..7] 7

2
1 2 DDRB_MA3 131 132 DDRB_MA2
DDRB_DQ4 3 VSS_1 VSS_2 4 DDRB_DQ5 7 DDRB_MA3 DDRB_MA1 133 A3 A2 134 DDRB_EVENT# DDRB_MA2 7
5 DQ5 DQ4 6 7 DDRB_MA1 135 A1 EVENT_n 136
DDRB_DQ0 7 VSS_3 VSS_4 8 DDRB_DQ1 DDRB_CLK0 137 VDD_9 VDD_10 138 DDRB_CLK1
9 DQ1 DQ0 10 7 DDRB_CLK0 DDRB_CLK0# 139 CK0_t CK1_t 140 DDRB_CLK1# DDRB_CLK1 7
DDRB_DQS#0 11 VSS_5 VSS_6 12 7 DDRB_CLK0# 141 CK0_c CK1_c 142 DDRB_CLK1# 7
DDRB_DQS0 13 DQS0_C DM0_n/DBIO_n/NC 14 DDRB_PAR 143 VDD_11 VDD_12 144 DDRB_MA0
15 DQS0_t VSS_7 16 DDRB_DQ3 7 DDRB_PAR Parity A0 DDRB_MA0 7
DDRB_DQ2 17 VSS_8 DQ6 18
D 19 DQ7 VSS_9 20 DDRB_DQ6 DDRB_BA1 145 146 DDRB_MA10 D
DDRB_DQ7 21 VSS_10 DQ2 22 7 DDRB_BA1 147 BA1 A10/AP 148 DDRB_MA10 7
23 DQ3 VSS_11 24 DDRB_DQ9 DDRB_CS0# 149 VDD_13 VDD_14 150 DDRB_BA0
DDRB_DQ10 25 VSS_12 DQ12 26 7 DDRB_CS0# DDRB_MA14_WE# 151 CS0_n BA0 152 DDRB_MA16_RAS# DDRB_BA0 7
27 DQ13 VSS_13 28 DDRB_DQ8 7 DDRB_MA14_WE# 153 WE_n/A14 RAS_n/A16 154 DDRB_MA16_RAS# 7
DDRB_DQ14 29 VSS_14 DQ8 30 DDRB_ODT0 155 VDD_15 VDD_16 156 DDRB_MA15_CAS#
31 DQ9 VSS_15 32 DDRB_DQS#1 7 DDRB_ODT0 DDRB_CS1# 157 ODT0 CAS_n/A15 158 DDRB_MA13 DDRB_MA15_CAS# 7
33 VSS_16 DQS1_c 34 DDRB_DQS1 7 DDRB_CS1# 159 CS1_n A13 160 DDRB_MA13 7
35 DM1_n/DBl1_n/NC DQS1_t 36 DDRB_ODT1 161 VDD_17 VDD_18 162
DDRB_DQ11 37 VSS_17 VSS_18 38 DDRB_DQ13 7 DDRB_ODT1 163 ODT1 C0/CS2_n/NC 164 +VREF_CA_DIMM
39 DQ15 DQ14 40 165 VDD_19 VREFCA 166 DDRB_SA2
DDRB_DQ15 41 VSS_19 VSS_20 42 DDRB_DQ12 167 C1/CS3_n/NC SA2 168

0.1u_0201_10V6K

2.2U_0402_6.3V6M
43 DQ10 DQ11 44 DDRB_DQ35 169 VSS_53 VSS_54 170 DDRB_DQ33
VSS_21 VSS_22 DQ37 DQ36 1 1
DDRB_DQ16 45 46 DDRB_DQ22 171 172 @
47 DQ21 DQ20 48 DDRB_DQ39 173 VSS_55 VSS_56 174 DDRB_DQ38
DDRB_DQ17 49 VSS_23 VSS_24 50 DDRB_DQ18 175 DQ33 DQ32 176
51 DQ17 DQ16 52 DDRB_DQS#4 177 VSS_57 VSS_58 178 2 2
DDRB_DQS#2 53 VSS_25 VSS_26 54 DDRB_DQS4 179 DQS4_c DM4_n/DBl4_n/NC 180

CD1

CD2
DDRB_DQS2 55 DQS2_c DM2_n/DBl2_n/NC 56 181 DQS4_t VSS_59 182 DDRB_DQ32
57 DQS2_t VSS_27 58 DDRB_DQ19 DDRB_DQ36 183 VSS_60 DQ39 184
DDRB_DQ21 59 VSS_28 DQ22 60 185 DQ38 VSS_61 186 DDRB_DQ37
61 DQ23 VSS_29 62 DDRB_DQ23 DDRB_DQ34 187 VSS_62 DQ35 188

m
DDRB_DQ20 63 VSS_30 DQ18 64 189 DQ34 VSS_63 190 DDRB_DQ41
65 DQ19 VSS_31 66 DDRB_DQ27 DDRB_DQ45 191 VSS_64 DQ45 192
DDRB_DQ25 67 VSS_32 DQ28 68 193 DQ44 VSS_65 194 DDRB_DQ44
69 DQ29 VSS_33 70 DDRB_DQ28 DDRB_DQ40 195 VSS_66 DQ41 196
DDRB_DQ30 71 VSS_34 DQ24 72 197 DQ40 VSS_67 198 DDRB_DQS#5

co
73 DQ25 VSS_35 74 DDRB_DQS#3 199 VSS_68 DQS5_c 200 DDRB_DQS5
+1.2V 75 VSS_36 DQS3_c 76 DDRB_DQS3 201 DM5_n/DBl5_n/NC DQS5_t 202
77 DM3_n/DBl3_n/NC DQS3_t 78 DDRB_DQ47 203 VSS_69 VSS_70 204 DDRB_DQ46
DDRB_DQ29 79 VSS_37 VSS_38 80 DDRB_DQ26 205 DQ46 DQ47 206
81 DQ30 DQ31 82 DDRB_DQ42 207 VSS_71 VSS_72 208 DDRB_DQ43
DDRB_DQ24 83 VSS_39 VSS_40 84 DDRB_DQ31 209 DQ42 DQ43 210
DQ26 DQ27 VSS_73 VSS_74
1

85 86 DDRB_DQ48 211 212 DDRB_DQ51

s.
RD92 RD93 87 VSS_41 VSS_42 88 213 DQ52 DQ53 214
240_0402_1% 240_0402_1% 89 CB5/NC CB4/NC 90 DDRB_DQ52 215 VSS_75 VSS_76 216 DDRB_DQ54
91 VSS_43 VSS_44 92 217 DQ49 DQ48 218
93 CB1/NC CB0/NC 94 DDRB_DQS#6 219 VSS_77 VSS_78 220

ic
VSS_45 VSS_46 DQS6_c DM6_n/DBl6_n/NC
2

DDRB_DQS#8 95 96 DDRB_DQS6 221 222

DDRB_DQS8 97 DQS8_c DM8_n/DBI8_n/NC 98 223 DQS6_t VSS_79 224 DDRB_DQ55
99 DQS8_t VSS_47 100 DDRB_DQ53 225 VSS_80 DQ54 226
C
101 VSS_48 CB6/NC 102 227 DQ55 VSS_81 228 DDRB_DQ50 C
CB2/NC VSS_49 DDRB_DQ49 VSS_82 DQ50

at
103 104 229 230
105 VSS_50 CB7/NC 106 231 DQ51 VSS_83 232 DDRB_DQ61
107 CB3/NC VSS_51 108 PCH_DRAMRST# DDRB_DQ59 233 VSS_84 DQ60 234
DDRB_CKE0 109 VSS_52 RESET_n 110 DDRB_CKE1 PCH_DRAMRST# 12,16 235 DQ61 VSS_85 236 DDRB_DQ57
7 DDRB_CKE0 111 CKE0 CKE1 112 DDRB_CKE1 7 DDRB_DQ62 237 VSS_86 DQ57 238
VDD_1 VDD_2 1 DQ56 VSS_87
DDRB_BG1 113 114 DDRB_ACT# CD3 239 240 DDRB_DQS#7

em
7 DDRB_BG1 DDRB_BG0 115 BG1 ACT_n 116 DDRB_ALERT# DDRB_ACT# 7 241 VSS_88 DQS7_c 242 DDRB_DQS7
0.1u_0201_10V6K
7 DDRB_BG0 117 BG0 ALERT_n 118 DDRB_ALERT# 7 243 DM7_n/DBl7_n/NC DQS7_t 244
@
DDRB_MA12 119 VDD_3 VDD_4 120 DDRB_MA11 2 DDRB_DQ58 245 VSS_89 VSS_90 246 DDRB_DQ60
7 DDRB_MA12 DDRB_MA9 121 A12 A11 122 DDRB_MA7 DDRB_MA11 7 247 DQ62 DQ63 248
7 DDRB_MA9 123 A9 A7 124 DDRB_MA7 7 DDRB_DQ56 249 VSS_91 VSS_92 250 DDRB_DQ63
DDRB_MA8 125 VDD_5 VDD_6 126 DDRB_MA5 251 DQ58 DQ59 252
7 DDRB_MA8 DDRB_MA6 127 A8 A5 128 DDRB_MA4 DDRB_MA5 7 SMB_CLK_S3 253 VSS_93 VSS_94 254 SMB_DATA_S3
7 DDRB_MA6 129 A6 A4 130 DDRB_MA4 7 1 16
2 SMB_CLK_S3 +VDD_SPD 255 SCL SDA 256 DDRB_SA0 SMB_DATA_S3 16
+3VS RD1 @
VDD_7 VDD_8 0_0603_5% 257 VDDSPD SA0 258

ch
VPP_1 Vtt DDRB_SA1 +0.6VS
1 1 259 260
VPP_2 SA1
ARGOS_D4AS0-26001-1P60 CD4 CD5 261 262
2.2U_0402_6.3V6M 0.1u_0201_10V6K GND_1 GND_2
ME@ 2 2 ARGOS_D4AS0-26001-1P60
ME@

kS
RD2 1 @ 2 +VPP
+2.5V_DDR
0_0603_5%

+1.2V
oo
+VREF_DQ_DIMMB_R 1
@
CD117 Note:
1

+0.6VS +2.5V_DDR
0.1u_0201_10V6K
2 VREF trace width:20 mils at least Layout Note:
RD3
Place near DIMM
eb

1K_0402_1% Spacing:20mils to other signal/planes

Place near DIMM scoket

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
CD@

CD@

CD@
B 1 1 1 1 1 1 1 1 B
RD4 1 2 +VREF_CA_DIMM
2_0402_5%
ot

1 @
2 2 2 2 2 2 2 2

CD118
1

CD10
1

CD13 @

CD6

CD7

CD8

CD9

CD11

CD12
0.022U_0201_6.3V6-K RD5 CD14
2 1K_0402_1% 0.1u_0201_10V6K
2
N
1

RD6
24.9_0402_1%

+1.2V
2

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
CD@

CD@

CD@

CD@
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
CD20

CD21

CD22

CD24

CD25

CD26
CD19

CD23

CD27

CD28

CD29

CD30

CD31

CD32

CD33

CD34
+3VS +3VS +3VS

+1.2V
1

RD7 RD8 RD9

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

0_0402_5% 0_0402_5% 0_0402_5%

RF@

RF@

@ @ @
4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

0.1u_0201_10V6K

0.1u_0201_10V6K

33P_0402_50V8J

33P_0402_50V8J
2

1 1 1 1 1 1
DDRB_SA0 DDRB_SA1 DDRB_SA2
A A
2 2 2 2 2 2
CD15

CD16

CD17

CD18

CD36

CD37
1

RD10 RD11 RD12

0_0402_5% 0_0402_5% 0_0402_5%
@ @ @
For EMC
Near JDDRL1
2

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2018/09/20 DDR4 SO-DIMM

SPD Address = 2H THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
FG541/FG741 1.0

Date: Tuesday, March 26, 2019 Sheet 13 of 69

5 4 3 2 1
 5 4 3 2 1

+3VS

1
RH133 UH1C
10K_0402_5% AR2 G36 PCIE_PRX_DTX_N9
D AT5 CL_CLK PCIE9_RXN F36 PCIE_PRX_DTX_P9 PCIE_PRX_DTX_N9 45 D
AU4 CL_DATA PCIE9_RXP C34 PCIE_PTX_DRX_N9 PCIE_PRX_DTX_P9 45 NGFF SSD
CL_RST# PCIE9_TXN PCIE_PTX_DRX_N9 45

2
D34 PCIE_PTX_DRX_P9
PCIE9_TXP PCIE_PTX_DRX_P9 45
P48
V47 GPP_K8 K37 PCIE_PRX_DTX_N10
GPP_K9 PCIE10_RXN PCIE_PRX_DTX_P10 PCIE_PRX_DTX_N10 45
V48 J37
GPP_K10 PCIE10_RXP PCIE_PTX_DRX_N10 PCIE_PRX_DTX_P10 45
W47 C35
GPP_K11 PCIE10_TXN PCIE_PTX_DRX_P10 PCIE_PTX_DRX_N10 45
B35 NGFF SSD
PCIE10_TXP PCIE_PTX_DRX_P10 45
L47
L46 GPP_K0 F44
EC_SCI# RH95 1 @ 2 0_0201_5% U48 GPP_K1 PCIE15_RXN/SATA2_RXN E45
20,49 EC_SCI# GPP_K2 PCIE15_RXP/SATA2_RXP
PAD 1 U47 B40
Reserve interrupt for UCMcx IT36 @ N48 GPP_K3 PCIE15_TXN/SATA2_TXN C40
N47 GPP_K4 PCIE15_TXP/SATA2_TXP
P47 GPP_K5 L41
GPP_K6 PCIE16_RXN/SATA3_RXN

m
R46 M40
GPP_K7 PCIE16_RXP/SATA3_RXP B41
PCIE_PTX_DRX_P11 C36 PCIE16_TXN/SATA3_TXN C41
45 PCIE_PTX_DRX_P11 PCIE_PTX_DRX_N11 PCIE11_TXP/SATA0A_TXP PCIE16_TXP/SATA3_TXP
B36

co
45 PCIE_PTX_DRX_N11 PCIE_PRX_DTX_P11 PCIE11_TXN/SATA0A_TXN
NGFF SSD 45 PCIE_PRX_DTX_P11
F39
PCIE11_RXP/SATA0A_RXP PCIE17_RXN/SATA4_RXN
K43
SATA_PRX_DTX_N0 47
PCIE_PRX_DTX_N11 G38 K44
45 PCIE_PRX_DTX_N11 PCIE11_RXN/SATA0A_RXN PCIE17_RXP/SATA4_RXP SATA_PRX_DTX_P0 47
A42 HDD
PCIE17_TXN/SATA4_TXN SATA_PTX_DRX_N0 47
AR42 B42
GPP_F10/SATA_SCLOCK PCIE17_TXP/SATA4_TXP SATA_PTX_DRX_P0 47
AR48

s.
AU47 GPP_F11/SATA_SLOAD P41
AU46 GPP_F13/SATA_SDATAOUT0 PCIE18_RXN/SATA5_RXN R40
GPP_F12/SATA_SDATAOUT1 PCIE18_RXP/SATA5_RXP C42

ic
CH15 1 2 0.1u_0201_10V6K PCIE_PTX_DRX_N14 C39 PCIE18_TXN/SATA5_TXN D42
42 PCIE_PTX_C_DRX_N14 PCIE_PTX_DRX_P14 PCIE14_TXN/SATA1B_TXN PCIE18_TXP/SATA5_TXP
LAN CH16 1 2 0.1u_0201_10V6K D39
C 42 PCIE_PTX_C_DRX_P14 PCIE_PRX_DTX_N14 PCIE14_TXP/SATA1B_TXP SATA_LED#
C
42 PCIE_PRX_DTX_N14 D46 AK48 RH15 1 2 10K_0402_5% +3VS

at
PCIE_PRX_DTX_P14 C47 PCIE14_RXN/SATA1B_RXN GPP_E8/SATA_LED# AH41
42 PCIE_PRX_DTX_P14 PCIE14_RXP/SATA1B_RXP GPP_E0/SATAXPCIE0/SATAGP0 AJ43 SSD_DET#
CH17 1 2 0.1u_0201_10V6K PCIE_PTX_DRX_N13 B38 GPP_E1/SATAXPCIE1/SATAGP1 AK47 SSD_DET# 45
45 PCIE_PTX_C_DRX_N13 PCIE_PTX_DRX_P13 PCIE13_TXN/SATA0B_TXN GPP_E2/SATAXPCIE2/SATAGP2 change to SATA PORT1 by Bing 0621
CH18 1 2 0.1u_0201_10V6K C38 AN47

em
45 PCIE_PTX_C_DRX_P13 PCIE_PRX_DTX_N13 PCIE13_TXP/SATA0B_TXP GPP_F0/SATAXPCIE3/SATAGP_3
WLAN 45 PCIE_PRX_DTX_N13 C45 AM46
PCIE_PRX_DTX_P13 C46 PCIE13_RXN/SATA0B_RXN GPP_F1/SATAXPCIE4/SATAGP4 AM43
45 PCIE_PRX_DTX_P13 PCIE13_RXP/SATA0B_RXP GPP_F2/SATAXPCIE5/SATAGP5 AM47
PCIE_SATA_PTX_DRX_P12 E37 GPP_F3/SATAXPCIE6/SATAGP6 AM48
45 PCIE_SATA_PTX_DRX_P12 PCIE_SATA_PTX_DRX_N12 PCIE12_TXP/SATA1A_TXP GPP_F4/SATAXPCIE7/SATAGP7
D38
NGFF SSD 45 PCIE_SATA_PTX_DRX_N12 PCIE_SATA_PRX_DTX_P12 J41 PCIE12_TXN/SATA1A_TXN AU48
45 PCIE_SATA_PRX_DTX_P12 PCH_EDP_PW M 38

ch
PCIE_SATA_PRX_DTX_N12 H42 PCIE12_RXP/SATA_1A_RXP GPP_F21/EDP_BKLTCTL AV46
45 PCIE_SATA_PRX_DTX_N12 PCIE12_RXN/SATA1A_RXN GPP_F20/EDP_BKLTEN PCH_EDP_ENBKL 38
B44 AV44
PCIE20_TXP/SATA7_TXP GPP_F19/EDP_VDDEN PCH_EDP_ENVDD 38
A44
R37 PCIE20_TXN/SATA7_TXN AD3 THRMTRIP#_PCH RH34 1 2 620_0402_5%
PCIE20_RXP/SATA7_RXP THRMTRIP# H_THRMTRIP# 6,25
R35 AF2 PCH_PECI RH35 1 2 13_0402_5%

kS
PCIE20_RXN/SATA7_RXN PECI EC_PECI 6,49
D43 AF3 H_PM_SYNC_R RH13 1 2 30_0402_1%
PCIE19_TXP/SATA6_TXP PM_SYNC CPU_PLTRST# H_PM_SYNC 6
C44 AG5
PCIE19_TXN/SATA6_TXN PLTRST_CPU# H_PM_DOW N CPU_PLTRST# 6
N42 AE2 H_PM_DOW N 6
M44 PCIE19_RXP/SATA6_RXP PM_DOWN
PCIE19_RXN/SATA6_RXN 3 OF 13
oo

1
CANNONLAKE-H-PCH_FCBGA874 1 1

.1U_0402_10V6-K
CH280

.1U_0402_10V6-K
CH281
@
@ RH836
10K_0201_5%
@2 @2
eb

2
B B
ot
N

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/26 Deciphered Date 2018/09/20 PCH (1/9) PCIe/SATA/GPPFG
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
A3
FG541/FG741 1.0

Date: Tuesday, March 26, 2019 Sheet 14 of 69

5 4 3 2 1
 5 4 3 2 1

Follow PDG add R/C 1010SF

close to PCH
LPC_AD0 CC1399 1 2 27P_0402_50V8J EMC_NS@

LPC_AD1 CC1403 1 2 27P_0402_50V8J EMC_NS@

+3VS
LPC_AD2 CC1402 1 2 27P_0402_50V8J EMC_NS@
HM370 only have 4(#1-#4) USB3.1 GEN2 port
LPC_AD3 CC1400 1 2 27P_0402_50V8J EMC_NS@
D D

1
UH1F
46 USB30_TX_N1 USB30_TX_N1 F9 BB39 LPC_AD0_R RH128 1 @ 2 0_0201_5%
46 USB30_TX_P1 USB30_TX_P1 USB31_1_TXN GPP_A1/LAD0/ESPI_IO0 LPC_AD1_R LPC_AD0 49
F7 AW37 1 2
LEFT USB3.0 46 USB30_RX_N1 USB30_RX_N1 D11 USB31_1_TXP
USB31_1_RXN
GPP_A2/LAD1/ESPI_IO1
GPP_A3/LAD2/ESPI_IO2
AV37 LPC_AD2_R
RH130
RH131 1
@
@ 2
0_0201_5%
0_0201_5%
LPC_AD1
LPC_AD2
49
49
RH104
10K_0402_5%
RH113
10K_0402_5%
46 USB30_RX_P1 USB30_RX_P1 C11 BA38 LPC_AD3_R RH132 1 @ 2 0_0201_5%
USB31_1_RXP GPP_A4/LAD3/ESPI_IO3 LPC_AD3 49

2
48 USB30_TX_N2 USB30_TX_N2 C3
48 USB30_TX_P2 USB30_TX_P2 D4 USB31_2_TXN BE38 LPC_FRAME#
Type-C 48
48
USB30_RX_N2
USB30_RX_P2
USB30_RX_N2
USB30_RX_P2
B9 USB31_2_TXP
USB31_2_RXN
GPP_A5/LFRAME#/ESPI_CS0#
GPP_A6/SERIRQ/ESPI_CS1#
AW35 SERIRQ
TPM_PIRQ#
LPC_FRAME# 49
SERIRQ 49
C9 BA36 RH863 1 TPM@ 2 0_0402_5%
USB31_2_RXP GPP_A7/PIRQA#/ESPI_ALERT0# BE39 KBRST# TPM_SPI_PIRQ# 37
GPP_A0/RCIN#/ESPI_ALERT1# KBRST# 49
C17 BF38
C16 USB31_6_TXN GPP_A14/SUS_STAT#/ESPI_RESET#

m
G14 USB31_6_TXP For LPC_CLK
F14 USB31_6_RXN R：0Ω to 22Ω
USB31_6_RXP BB36 CLK_PCI_EC_R RH84 1 2 22_0402_5% CLK_PCI_EC
GPP_A9/CLKOUT_LPC0/ESPI_CLK CLK_PCI_EC 49

co
C15 BB34
B15 USB31_5_TXN GPP_A10/CLKOUT_LPC1
J13 USB31_5_TXP T48 PCH_SMI# RH821 @1 2 0_0402_5%
USB31_5_RXN GPP_K19/SMI# EC_SMI# 49
K13 T47
USB31_5_RXP GPP_K18/NMI# RH129 @1 2 10K_0402_5% +3VS 1

s.
46 USB30_TX_P3 USB30_TX_P3 G12 AH40 EMC_NS@
46 USB30_TX_N3 USB30_TX_N3 F11 USB31_3_TXP GPP_E6/SATA_DEVSLP2 AH35 NGFF SSD CE52
LEFT USB3.0 46 USB30_RX_P3 USB30_RX_P3 C10 USB31_3_TXN
USB31_3_RXP
GPP_E5/SATA_DEVSLP1
GPP_E4/SATA_DEVSLP0
AL48
DEVSLP0 45
10P_0402_50V8J

ic
46 USB30_RX_N3 USB30_RX_N3 B10 AP47 change DEVSLP to SATA Port1 by Bing 0621 2
USB31_3_RXN GPP_F9/SATA_DEVSLP7 AN37 H：Sleep Mode
C USB30_TX_P4 C14 GPP_F8/SATA_DEVSLP6 AN46 L：Active Mode
reserved for EMC need 0803SF C
48 USB30_TX_P4 USB31_4_TXP GPP_F7/SATA_DEVSLP5
USB30_TX_N4

at
B14 AR47
Type-C 48
48
USB30_TX_N4
USB30_RX_P4 USB30_RX_P4
USB30_RX_N4
J15 USB31_4_TXN
USB31_4_RXP
6 OF 13 GPP_F6/SATA_DEVSLP4
GPP_F5/SATA_DEVSLP3
AP48
48 USB30_RX_N4 K16
USB31_4_RXN

em
CANNONLAKE-H-PCH_FCBGA874
@

ch
kS
oo
eb

+3VS

B RH853 @ B
DDPB_CLK 2 1 2.2K_0402_5%
ot

UH1E
HDMI_HPD RH26 1 @ 2 0_0402_5% GPP_I0 AT6 AL13 DDPB_CLK DDPB_DATA RH823 2 @ 1 2.2K_0402_5%
39 HDMI_HPD GPP_I0/DDPB_HPD0/DISP_MISC0 GPP_I5/DDPB_CTRLCLK
1 AN10 AR8 DDPB_DATA
TH40 GPP_I1/DDPC_HPD1/DISP_MISC1 GPP_I6/DDPB_CTRLDATA DDPC_CLK
AP9 AN13 1 PAD @ +3VS
PAD @ GPP_I2/DPPD_HPD2/DISP_MISC2 GPP_I7/DDPC_CTRLCLK TH35
N

CNVI_EN# AL15 AL10 DDPC_DATA

45 CNVI_EN# GPP_I3/DPPE_HPD3/DISP_MISC3 GPP_I8/DDPC_CTRLDATA DDPD_CLK
AL9 1 PAD @
GPP_I9/DDPD_CTRLCLK DDPD_DATA TH36 DDPC_DATA RH10 @
AR3 2 1 2.2K_0402_5%
GPP_I10/DDPD_CTRLDATA AN40
GPP_F23/DDPF_CTRLDATA AT49 DDPD_DATA RH16 @ 2 1 2.2K_0402_5%
GPP_F22/DDPF_CTRLCLK
AP41
PCH_EDP_HPD AN6 GPP_F14/EXT_PWR_GATE#/PS_ON#
38 PCH_EDP_HPD GPP_I4/EDP_HPD/DISP_MISC4
GPP_K23/IMGCLKOUT1
M45 DDPB_CTRLDATA
L48 The signal has a weak internal pull-down.
GPP_K22/IMGCLKOUT0
GPP_K21
T45
T46
* H Port B is detected.
GPP_K20 AJ47 L Port B is not detected.
5 OF 13 GPP_H23/TIME_SYNC0
CANNONLAKE-H-PCH_FCBGA874 DDPC_CTRLDATA
@ The signal has a weak internal pull-down.
H Port C is detected.
* L Port C is not detected. (Default)
DDPD_CTRLDATA
The signal has a weak internal pull-down.
H Port D is detected.
A
* L Port D is not detected. (Default)
A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/26 Deciphered Date 2018/09/20 PCH (2/9) USB3/GPPAEFGHI
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
A3 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FG541/FG741
Date: Tuesday, March 26, 2019 Sheet 15 of 69
5 4 3 2 1
 5 4 3 2 1

+3VALW_PCH
*HDA_SDO This signal has a weak internal pull-down.
0 = Enable security measures defined in the Flash Descriptor.
1 = Disable Flash Descriptor Security (override). This

2
strap should only be asserted high using external pull- RH25
up in manufacturing/debug environments ONLY. @ 1K_0402_5% +1.2V

1
RH9 1 @ 2 0_0402_5%
49 ME_FLASH

1
UH1D
RH805 1 2 33_0402_5% HDA_BIT_CLK BD11 BF36 RH756
35 HDA_BITCLK_AUDIO HDA_SDIN0 HDA_BCLK/I2S0_SCLK GPP_A12/BM_BUSY#/ISH_GP6/SX_EXIT_HOLDOFF# PM_CLKRUN#
BE11 AV32 470_0402_5%
35 HDA_SDIN0 HDA_SDOUT HDA_SDI0/I2S0_RXD GPP_A8/CLKRUN#
D RH806 1 2 33_0402_5% BF12 D
35 HDA_SDOUT_AUDIO HDA_SYNC HDA_SDO/I2S0_TXD
RH804 1 2 33_0402_5% BG13 BF41
35 HDA_SYNC_AUDIO HDA_SYNC/I2S0_SFRM GPD11/LANPHYPC

2
1 HDA_RST# BE10 BD42
PAD TH39 HDA_RST#/I2S1_SCLK GPD9/SLP_WLAN# PM_SLP_WLAN# 45
@ BF10
BE12 HDA_SDI1/I2S1_RXD BB46
I2S1_TXD/SNDW2_DATA DRAM_RESET# PCH_DRAMRST# 12,13
BD12 BE32
I2S1_SFRM/SNDW2_CLK GPP_B2/VRALERT# BF33
PLACE NEAR PCH GPP_B1/GSPI1_CS1#/TIME_SYNC1 BE29
RH754 2 1 30_0402_1% PROC_AUDIO_SDO_PCH AM2 GPP_B0/GSPI0_CS1# R47
8 PROC_AUDIO_SDO_CPU HDACPU_SDO GPP_K17/ADR_COMPLETE
AN3 AP29
8 PROC_AUDIO_SDI_CPU HDACPU_SDI GPP_B11/I2S_MCLK
RH755 2 1 30_0402_1% PROC_AUDIO_CLK_PCH AM3 AU3 SYS_PWROK_R RH193 1 @ 2 0_0402_5%
8 PROC_AUDIO_CLK_CPU HDACPU_SCLK SYS_PWROK SYS_PWROK 41,49
AV18 BB47 WAKE# RH69 1 @ 2 0_0402_5%
GPP_D8/I2S2_SCLK WAKE# SLP_A# PCIE_WAKE# 42,45,49
AW18 BE40 1 PAD @
CNVI_MODEM_CLKREQ GPP_D7/I2S2_RXD GPD6/SLP_A# SLP_LAN# TH30
BA17 BF40 1 PAD @
CNVI_RF_RESET# GPP_D6/I2S2_TXD/MODEM_CLKREQ SLP_LAN# SLP_S0 TH31
BE16 BC28 1 PAD @
GPP_D5/I2S2_SFRM/CNV_RF_RESET# GPP_B12/SLP_S0# PM_SLP_S3#_R TH32
BF15 BF42 RH70 1 @ 2 0_0402_5%
GPP_D20/DMIC_DATA0/SNDW4_DATA GPD4/SLP_S3# PM_SLP_S4#_R PM_SLP_S3# 49
BD16 BE42 RH71 1 @ 2 0_0402_5%
GPP_D19/DMIC_CLK0/SNDW4_CLK GPD5/SLP_S4# PM_SLP_S5#_R 1 PM_SLP_S4# 49
AV16 BC42
GPP_D18/DMIC_DATA1/SNDW3_DATA GPD10/SLP_S5# TH33 PAD @
AW15
GPP_D17/DMIC_CLK1/SNDW3_CLK BE45 SUSCLK
PCH_RTCRST# GPD8/SUSCLK SUSCLK 45 SUSACK#_R
BE47 BF44 BATLOW#
PCH_SRTCRST# BD46 RTCRST# GPD0/BATLOW# BE35 SUSACK#_R
SRTCRST# GPP_A15/SUSACK# SUSWARN#_R RH745 1 @ 2 0_0201_5%
BC37 SUSWARN#_R
RH12 1 @ 2 0_0402_5% PCH_PWROK_R AY42 GPP_A13/SUSWARN#/SUSPWRDNACK
41,49 PCH_PWROK PCH_RSMRST#_R PCH_PWROK
RH14 1 @ 2 0_0402_5% BA47
41,49 EC_RSMRST# RSMRST#

m
BG44 PCH_LAN_WAKE#
PCH_DPWROK_R AW41 GPD2/LAN_WAKE# BG42 PCH_AC_PRESENT_R RH76 1 @ 2 0_0402_5%
SMB_ALERT# DSW_PWROK GPD1/ACPRESENT PM_SLP_SUS#_R PM_SLP_SUS# AC_PRESENT 49
BE25 BD39 RC89 1 @ 2 0_0402_5%
PCH_SMBCLK GPP_C2/SMBALERT# SLP_SUS# PM_PWRBTN#_R PM_SLP_SUS# 49
BE26 BE46 RH75 1 @ 2 0_0402_5%
EC_RSMRST# PCH_SMBDATA GPP_C0/SMBCLK GPD3/PWRBTN# SYS_RESET# PBTN_OUT# 41,49
RC1710 2 @ 1 0_0402_5% BF26 AU2
SMB0_ALERT# GPP_C1/SMBDATA SYS_RESET# SYS_RESET# 41
BF24 AW29
GPP_C5/SML0ALERT# GPP_B14/SPKR PCH_BEEP 35
SML0CLK BF25 AE3

co
PCH_DPWROK_R GPP_C3/SML0CLK CPUPWRGD H_CPUPWRGD 6
RC81 1 @ 2 0_0402_5% SML0DATA BE24
DPWROK_EC 49 SMB1_ALERT# GPP_C4/SML0DATA
BD33 AL3
GPP_B23/SML1ALERT#/PCHHOT# ITP_PMODE ITP_PMODE 41
SML1CLK BF27 AH4
GPP_C6/SML1CLK PCH_JTAGX JTAGX 41
+3VALW_PCH SML1DATA BE27 AJ4
GPP_C7/SML1DATA PCH_JTAG_TMS PCH_TMS 41
AH3
PCH_JTAG_TDO PCH_TDO 41
SUSWARN#_R AH2
RH56 1 @ 2 10K_0402_5% PCH_JTAG_TDI PCH_TDI 41
AJ3
PCH_JTAG_TCK PCH_TCK 41
4 OF 13

s.
+3VALW CANNONLAKE-H-PCH_FCBGA874
@

RH17 1 2 10K_0402_5% PM_PWRBTN#_R RSMRST# sequence control circuit

1EC_RSMRST#
PCH_AC_PRESENT_R
SVT un-stuff0322SF

ic
RH58 1 2 10K_0402_5%
RH60 1 2 10K_0402_5% BATLOW#
RC278 1 @ 2 0_0201_5%
RH80 1 2 1K_0402_5% WAKE# +3VL
C RH747 1 2 10K_0201_5% PCH_LAN_WAKE# CMOS RC279 1 @ 2 0_0201_5% C
+3VALW

2
at
RC276 RC273
W=20mils W=20mils 0_0402_5% 100K_0402_5%
1 @

1
+3VS VCCRTC +RTCVCC +RTCVCC CH4 @
1U_0402_6.3V6K JME1

3 2

1
SHORT PADS @
2 D QH3B

2
RH67 1 2 10K_0402_5% SYS_RESET# RH2 1 2 0_0402_5% RH3 1 2 20K_0402_5% PCH_SRTCRST#
PM_CLKRUN# 5
RH65 1 2 8.2K_0402_5%

em
@ 1 G
CH1

6
PCH_RTCRST# RC1624 1 @ D QH3A
1U_0402_6.3V6K RH4 1 2 20K_0402_5% 2 0_0402_5%
EC_RTC_RST# 49 S 2 RC272 1 @ 2 0_0201_5%
@ ALW_PWRGD 60

4
2 @ 1 G

1
CNVI_RF_RESET# CH5 JCMOS1
RH829 1 CNVI@ 2 75K_0402_5% L2N7002KDW1T1G_SOT363-6
1U_0402_6.3V6K SHORT PADS S
CNVi@
RH830 1 2 71.5K_0402_1% CNVI_MODEM_CLKREQ @

1
2 L2N7002KDW1T1G_SOT363-6

2
@
RH18 1 2 100K_0402_5% SYS_PWROK_R
RH54 2 1 10K_0402_5% PCH_PWROK
RH59 1 2 10K_0402_5% PCH_RSMRST#_R

ch
RH61 1 2 100K_0402_5% PCH_DPWROK_R
@

+3VALW_PCH
EMC request add 0322SF AS EMC request
HDA_RST# close to PCH
HDA_SDOUT
+3VALW_PCH RH28 1 @ 2 1K_0402_5% PCH_BEEP
PCH_SRTCRST# PCH_RTCRST# PCH_PWROK SYS_PWROK_R PCH_DPWROK_R HDA_SDIN0

kS
RPH3
1 4 SML0DATA SPKR / GPP_B14
2 3 SML0CLK The signal has a weak internal pull-down. 1 1 1 1 1 1

CH83 EMC@

.1U_0402_10V6-K

CH84 EMC@

.1U_0402_10V6-K

CH85 EMC@

.1U_0402_10V6-K

CH283 EMC_NS@

2.2P_0402_50V8-C

CH284 EMC_NS@

2.2P_0402_50V8-C

CH286 EMC_NS@

2.2P_0402_50V8-C
0 = Disable ¨Top Swap
〃

@ mode. (Default)
1 = Enable ¨Top Swap
〃

2.2K_0404_4P2R_5% mode. This inverts an address

* on access to SPI and firmware hub, so the processor
believes it fetches the alternate boot block instead of
1
CH294
1
CH293 2 2 2 2 2 2
1000P_0201_50V7-K 1000P_0201_50V7-K
RH765 1 2 2.2K_0402_5% SMB_ALERT# RH768 @1 2 2.2K_0402_5% the original boot-block. PCH will invert A16 (default)
RH766 @1 2 2.2K_0402_5% SMB0_ALERT# RH769 @1 2 2.2K_0402_5%
oo EMC@ EMC@
for cycles going to the upper two 64-KB blocks in the 2 2
RH767 @1 2 2.2K_0402_5% SMB1_ALERT# RH770 @1 2 2.2K_0402_5% FWH or the appropriate address lines (A16, A17, or
A18) as selected in Top Swap Block size soft strap
Strap (handled through FITC).

GPP_C2 /SMBALERT#
This signal has a weak internal pull-down.
eb

0 = Disable Intel ME Crypto Transport Layer Security

(TLS) cipher suite (no confidentiality). (Default)
1 = Enable Intel ME Crypto Transport Layer Security DIMM1, DIMM2, WLAN, TP RPH8 +3VS GPU, EC, Thermal Sensor
1 4
+3VS +3VALW_PCH
(TLS) cipher suite (with confidentiality). Must be

2
B RPH4 RPH7 2 3 B

G
2

pulled up to support Intel AMT with TLS. +3VALW_PCH

1 4 2N7002KDWH 1 4
+3VS
G

2 3 Vth= min 1V, max 2.5V 2 3 2.2K_0404_4P2R_5%

ESD 2KV
GPP_C5 /SML0ALERT#
2.2K_0404_4P2R_5% 2.2K_0404_4P2R_5% SML1CLK 6 1 EC_SMB_CK2
This signal has a weak internal pull-down. EC_SMB_CK2 28,44,49

S
ot

PCH_SMBCLK 6 1 SMB_CLK_S3

D
0 = LPC is selected (for EC). (Default) SMB_CLK_S3 13
S

5
QH2A L2N7002KDW1T1G_SOT363-6
D

1 = eSPI is selected (for EC).

G
5

QH1A L2N7002KDW1T1G_SOT363-6
G

GPP_B23 /SML1ALERT# /PCHHOT#

0 = Disable Intel DCI-OOB (Default) SML1DATA 3 4 EC_SMB_DA2
EC_SMB_DA2 28,44,49

S
1 = Enable Intel DCI-OOB PCH_SMBDATA 3 4 SMB_DATA_S3

D
SMB_DATA_S3 13
S
N

Note:When used as PCHHOT# and strap low, a 150K QH2B L2N7002KDW1T1G_SOT363-6

D

pull-up is needed to ensure it does not override the QH1B L2N7002KDW1T1G_SOT363-6

internal pull-down strap sampling.

For CNVI function update:change GPIO Group D to 1.8V and delete level shift1205SF

CNVI_MODEM_CLKREQ CNVI_RF_RESET#
CNVI_MODEM_CLKREQ 45 CNVI_RF_RESET# 45

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/26 Deciphered Date 2018/09/20 PCH (3/9) HDA,RTC,SMBUS,PM

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FG541/FG741
Date: Tuesday, March 26, 2019 Sheet 16 of 69
5 4 3 2 1
 5 4 3 2 1

UH1G
BE33 Y3
GPP_A16/CLKOUT_48 CLKOUT_ITPXDP Y4
D7 CLKOUT_ITPXDP_P
6 PCH_CPU_NSSC_CLK C6 CLKOUT_CPUNSSC_P B6
6 PCH_CPU_NSSC_CLK# CLKOUT_CPUNSSC CLKOUT_CPUPCIBCLK PCH_CPU_PCIBCLK# 6
A6
CLKOUT_CPUPCIBCLK_P PCH_CPU_PCIBCLK 6
D B8 D
6 PCH_CPU_BCLK CLKOUT_CPUBCLK_P
C8 AJ6
6 PCH_CPU_BCLK# CLKOUT_CPUBCLK CLKOUT_PCIE_N0 AJ7
XTAL24_OUT U9 CLKOUT_PCIE_P0
XTAL24_IN U10 XTAL_OUT AH9
XTAL_IN CLKOUT_PCIE_N1 AH10
RH6 1 2 60.4_0402_1% PCH_CLK_BIASREF T3 CLKOUT_PCIE_P1
XCLK_BIASREF AE14 CLK_PCIE_W LAN#
PCH_RTCX1 CLKOUT_PCIE_N2 CLK_PCIE_WLAN# 45
PDG_0.71 60Ω±1 % BA49 AE15 CLK_PCIE_W LAN WLAN
CRB 60.4Ω±1% PCH_RTCX2 RTCX1 CLKOUT_PCIE_P2 CLK_PCIE_W LAN 45
+3VS BA48
need to confirm RTCX2 AE6 CLK_PCIE_LAN#
CLKOUT_PCIE_N3 CLK_PCIE_LAN# 42
BF31 AE7 CLK_PCIE_LAN LAN
GPP_B5/SRCCLKREQ0# CLKOUT_PCIE_P3 CLK_PCIE_LAN 42
BE31
W LAN_CLKREQ# AR32 GPP_B6/SRCCLKREQ1# AC2
45 W LAN_CLKREQ# GPP_B7/SRCCLKREQ2# CLKOUT_PCIE_N4
LAN_CLKREQ# BB30 AC3
42 LAN_CLKREQ# GPP_B8/SRCCLKREQ3# CLKOUT_PCIE_P4
BA30

m
RH90 1 @ 2 10K_0402_5% W LAN_CLKREQ# AN29 GPP_B9/SRCCLKREQ4# AB2
AE47 GPP_B10/SRCCLKREQ5# CLKOUT_PCIE_N5 AB3
SSD_CLKREQ# AC48 GPP_H0/SRCCLKREQ6# CLKOUT_PCIE_P5
45 SSD_CLKREQ# GPP_H1/SRCCLKREQ7#
LAN_CLKREQ#

co
RH89 1 2 10K_0402_5% AE41 W4
AF48 GPP_H2/SRCCLKREQ8# CLKOUT_PCIE_N6 W3
RH93 1 2 10K_0402_5% SSD_CLKREQ# AC41 GPP_H3/SRCCLKREQ9# CLKOUT_PCIE_P6
GPU_CLKREQ# AC39 GPP_H4/SRCCLKREQ10# W7 CLK_PCIE_SSD#
25 GPU_CLKREQ# GPP_H5/SRCCLKREQ11# CLKOUT_PCIE_N7 CLK_PCIE_SSD# 45
RH94 1 2 10K_0402_5% GPU_CLKREQ# AE39 W6 CLK_PCIE_SSD M.2 SSD
CLK_PCIE_SSD 45

s.
AB48 GPP_H6/SRCCLKREQ12# CLKOUT_PCIE_P7
AC44 GPP_H7/SRCCLKREQ13# AC14
AC43 GPP_H8/SRCCLKREQ14# CLKOUT_PCIE_N8 AC15
GPP_H9/SRCCLKREQ15# CLKOUT_PCIE_P8

ic
V2 U2
C V3 CLKOUT_PCIE_N15 CLKOUT_PCIE_N9 U3 C
CLKOUT_PCIE_P15 CLKOUT_PCIE_P9

at
T2 AC9
T1 CLKOUT_PCIE_N14 CLKOUT_PCIE_N10 AC11
CLKOUT_PCIE_P14 CLKOUT_PCIE_P10
AE9 CLK_PCIE_GPU#

em
AA1
CLKOUT_PCIE_N13 CLKOUT_PCIE_N11 CLK_PCIE_GPU# 25
Y2 AE11 CLK_PCIE_GPU GPU
CLKOUT_PCIE_P13 CLKOUT_PCIE_P11 CLK_PCIE_GPU 25
AC7 R6
CLKOUT_PCIE_N12 CLKIN_XTAL CLKIN_XTAL_LCP 45
AC6 RH824 1 2 10K_0402_5%
CLKOUT_PCIE_P12
7 OF 13
CANNONLAKE-H-PCH_FCBGA874

ch
@
change from 0ohm to 10K on 1002SF

kS
change to 200K±1% on 0703
oo
RH92 2 1 200K_0402_1%

YH2
eb

XTAL24_IN_LR RH30 XTAL24_IN

4 3 1 2
NC2 3
XTAL24_OUT RH32 XTAL24_OUT_LR 0_0402_5%
B 1 2 1 2 B
1 NC1 @
0_0402_5%
ot

1 1
@ 24MHZ_12PF_7V24000023
CH9 CH10
15P_0402_50V8J 15P_0402_50V8J
2 2
N

PCH_RTCX1

RH1 1 2 10M_0402_5% PCH_RTCX2

YH1
1 2

Default De-Pop, if want to Pop in BOM, need change PN to SM070004400 32.768KHZ_9PF_X1A0001410002

1 1
CH2 CH3
@
10P_0402_50V8J 10P_0402_50V8J
EXC24CH500U_4P
XTAL24_IN 4 3 XTAL24_IN_LR 2 2
4 3

XTAL24_OUT 1 2 XTAL24_OUT_LR
1 2
L33

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/26 Deciphered Date 2018/09/20 PCH (3/9) CLOCK,GPPBH
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
A3 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FG541/FG741
Date: Tuesday, March 26, 2019 Sheet 17 of 69
5 4 3 2 1
 5 4 3 2 1

RH8581 @ 2 0_0402_5%
49 EC_SPI_SI
RH8591 2 0_0402_5%
D
To EC 49 EC_SPI_SO
49 EC_SPI_CLK
RH8601
@
@ 2 0_0402_5%
D

UH1A
SPI_SI_F RH1091 @ 2 0_0402_5% BE36 AV29 PLT_RST#
GPP_A11/PME#/SD_VDD2_PWR_EN# GPP_B13/PLTRST# PLT_RST# 28,37,41,42,45,49

1
SPI_SO_F RH1111 2 0_0402_5%
To flash ROM SPI_CLK_PCH_F RH1051
@
2 0_0402_5%
R15
R13 RSVD9 GPP_K16/GSXCLK
Y47
Y46
RH43 1
100K_0402_5% CH295
@ RSVD10 GPP_K12/GSXDOUT Y48 220P_0201_25V7-K
RH8261 @ 2 0_0402_5% AL37 GPP_K13/GSXSLOAD W46 EMC@
VSS_247 GPP_K14/GSXDIN

2
1 PAD AN35 AA45 2
TH37 TP_1 GPP_K15/GSXSRESET#
@
SPI_SI_R RH8541 @ 2 0_0402_5% SPI_SI AU41 AL47
SPI_SO_R RH8551 @ 2 0_0402_5% SPI_SO BA45 SPI0_MOSI GPP_E3/CPU_GP0 AM45
RH8621 @ 2 0_0402_5% SPI_CS0# AY47 SPI0_MISO GPP_E7/CPU_GP1 BF32
49 EC_SPI_CS0# SPI_CLK_PCH_R SPI_CLK_PCH SPI0_CS0# GPP_B3/CPU_GP2
RH8561 @ 2 0_0402_5% AW47 BC33
SPI_CS0#_F RH8611 @ 2 0_0402_5% AW48 SPI0_CLK GPP_B4/CPU_GP3
SPI0_CS1# AE44 +3VALW_PCH
SPI_WP# AY48 GPP_H18/SML4ALERT# AJ46
41 SPI_WP# SPI_HOLD# SPI0_IO2 GPP_H17/SML4DATA
BA46 AE43
SPI_CS2# AT40 SPI0_IO3 GPP_H16/SML4CLK AC47 RH825 1 2 100K_0402_5% Follow PDG:100K
SPI_WP#_F RH2501 @ 2 0_0402_5% SPI0_CS2# GPP_H15/SML3ALERT# AD48
BE19 GPP_H14/SML3DATA AF47 Strap PIN

m
SPI_HOLD#_F RH2521 @ 2 0_0402_5% BF19 GPP_D1/SPI1_CLK/SBK1_BK1 GPP_H13/SML3CLK AB47 RH753 1 @ 2 4.7K_0402_5% Follow CRB:4.7K
BF18 GPP_D0/SPI1_CS#/SBK0_BK0 GPP_H12/SML2ALERT# AD47
BE18 GPP_D3/SPI1_MOSI/SBK3_BK3 GPP_H11/SML2DATA AE48
BC17 GPP_D2/SPI1_MISO/SBK2_BK2 GPP_H10/SML2CLK
BD17 GPP_D22/SPI1_IO3 BB44 RH743 2 1 1M_0402_5%
+RTCVCC

co
GPP_D21/SPI1_IO2 INTRUDER#
1 OF 13
CANNONLAKE-H-PCH_FCBGA874
@

s.
change TPM interface to SPI,need double check_SF20180530 +3VALW_PCH

SPI_CLK_PCH_R RC4710 2 TPM@ 1 33_0402_5%

TPM_SPI_CLK 37
change to 100K pull-up on 0703

ic
SPI_CS2# GPP_H15 /SML3ALERT# (Strap reserved)
RC4712 1 TPM@ 2 0_0402_5% 1 2 100K_0402_5% SPI_WP#
TPM_SPI_CS# 37 RH123 External pull-up is required. Recommend 100K if pulled
up to 3.3V or 75K if pulled up to 1.8V.
C SPI_SO_R RC4714 2 TPM@ 1 33_0402_5% RH125 1 2 100K_0402_5% SPI_HOLD# RH771 1 @ 2 1K_0402_5% This strap should sample HIGH. There should NOT be C
TPM_SPI_MISO 37

at
any on-board device driving it to opposite direction
SPI_SI_R during strap sampling.
RC4716 2 TPM@ 1 33_0402_5%
TPM_SPI_MOSI 37 Power Plane: Primary Well
RH772 1 @ 2 1K_0402_5% SPI_SO
GPP_H12 /SML2ALERT#
This signal has a weak internal pull-down.

em
RH773 1 2 100K_0402_5% SPI_SI RH833 1 @ 2 1K_0402_5% 0 = Master Attached Flash Sharing (MAFS) enabled
SPI_SI_XDP 41
(Default)
change to 100K pull-up on 0704 1 = Slave Attached Flash Sharing (SAFS) enabled.
Warning: This strap must be configured to ‘0’
(SAFS is disabled) if the eSPI or LPC
SPI0_MOSI,SPI0_MISO,SPI0_IO[2:3] all have internal pull up strap is configured to ‘0’ (eSPI i s
disabled)
SPI0_MOSI Notes:
External pull-up is required. Recommend 100K if pulled 1. The internal pull-down is disabled after RSMRST#

ch
up to 3.3V or 75K if pulled up to 1.8V. de-asserts.
This strap should sample HIGH. There should NOT be 2. This signal is in the primary well.
any on-board device driving it to opposite direction
during strap sampling.

SPI0_IO2

kS
External pull-up is required. Recommend 100K if pulled
up to 3.3V or 75K if pulled up to 1.8V.
This strap should sample HIGH. There should NOT be
any on-board device driving it to opposite direction
during strap sampling.

SPI0_IO3
oo External pull-up is required. Recommend 100K if pulled
up to 3.3V or 75K if pulled up to 1.8V.
This strap should sample HIGH. There should NOT be
+3V_SPI any on-board device driving it to opposite direction
128Mb Flash ROM，change to SA00008A300 SF0911 during strap sampling.
+3VALW_PCH NPI@ 2 1 +3V_SPI
D2201 RB520CM-30T2R_VMN2M2
eb

RC1711 2 0_0402_5%
@ 1
+3VS
UC3 CH13
RC1721 @ 2 0_0402_5% SPI_CS0#_F 1 8 .1U_0402_10V6-K
B /CS VCC 2 B
SPI_SO_F 2 7 SPI_HOLD#_F
ot

DO(IO1) /HOLD(IO3)
+3V_SPI
SPI_WP#_F 3 6 SPI_CLK_PCH_F
1. If support DS3, connect to +3VS and don't support EC mirror code; /WP(IO2) CLK

* 2. If don't support DS3, connect to +3VALW_PCH and support EC mirror code. 4

GND DI(IO0)
5 SPI_SI_F
2
N

W25Q128JVSIQ_SO8 RH119 1
EMC_NS@ 10_0402_5%@
CH268
5P_50V_B_NPO_0402
1

2
1
CH11
EMC_NS@ 10P_0402_50V8J
2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/26 Deciphered Date 2018/09/20 PCH (5/9) SPI,SMBUS,GPPBEGH

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
A2
FG541/FG741 1.0

Date: Tuesday, March 26, 2019 Sheet 18 of 69

5 4 3 2 1
 5 4 3 2 1

UH1B
DMI_CTX_PRX_N0 K34 J3 USB20_N1
5 DMI_CTX_PRX_N0
5 DMI_CTX_PRX_P0
DMI_CTX_PRX_P0
DMI_CRX_PTX_N0
J35
C33
DMI0_RXN
DMI0_RXP
USB2N_1
USB2P_1
J2
N13
USB20_P1
USB20_N2
USB20_N1
USB20_P1
46
46 LEFT USB3.0
5
5
DMI_CRX_PTX_N0
DMI_CRX_PTX_P0
DMI_CRX_PTX_P0
DMI_CTX_PRX_N1
B33
G33
DMI0_TXN
DMI0_TXP
USB2N_2
USB2P_2
N15
K4
USB20_P2
USB20_N3
USB20_N2
USB20_P2
48
48 Type-C
5 DMI_CTX_PRX_N1
D
5 DMI_CTX_PRX_P1
DMI_CTX_PRX_P1
DMI_CRX_PTX_N1
F34
C32
DMI1_RXN
DMI1_RXP
USB2N_3
USB2P_3
K3
M10
USB20_P3 USB20_N3
USB20_P3
46
46 LEFT USB3.0 D

5 DMI_CRX_PTX_N1 DMI_CRX_PTX_P1 DMI1_TXN USB2N_4

B32 L9
5 DMI_CRX_PTX_P1 DMI_CTX_PRX_N2 DMI1_TXP USB2P_4
5 DMI_CTX_PRX_N2 K32 M1
DMI_CTX_PRX_P2 J32 DMI2_RXN USB2N_5 L2
5 DMI_CTX_PRX_P2 DMI_CRX_PTX_N2 DMI2_RXP USB2P_5
C31 K7
5 DMI_CRX_PTX_N2 DMI_CRX_PTX_P2 DMI2_TXN USB2N_6
B31 K6
5 DMI_CRX_PTX_P2 DMI_CTX_PRX_N3 DMI2_TXP USB2P_6
5 DMI_CTX_PRX_N3 G30 L4
DMI_CTX_PRX_P3 F30 DMI3_RXN USB2N_7 L3
5 DMI_CTX_PRX_P3 DMI_CRX_PTX_N3 DMI3_RXP USB2P_7 USB20_N8
C29 G4 +3VALW_PCH
5
5
DMI_CRX_PTX_N3
DMI_CRX_PTX_P3
DMI_CRX_PTX_P3 B29
A25
DMI3_TXN
DMI3_TXP
USB2N_8
USB2P_8
G5
M6
USB20_P8 USB20_N8
USB20_P8
38
38 Camera
B25 DMI7_TXP USB2N_9 N8
P24 DMI7_TXN USB2P_9 H3
R24 DMI7_RXP USB2N_10 H2
C26 DMI7_RXN USB2P_10 R10
DMI6_TXP USB2N_11 RPH5
B26 P9
F26 DMI6_TXN USB2P_11 G1
DMI6_RXP USB2N_12 USB_OC4# 4 5
G26 G2 USB_OC5#
DMI6_RXN USB2P_12 3 6
B27 N3 USB_OC6#
DMI5_TXP USB2N_13 2 7
C27 N2 USB_OC7#
DMI5_TXN USB2P_13 USB20_N14 1 8
L26 E5
M26
D29
DMI5_RXP
DMI5_RXN
USB2N_14
USB2P_14
F6 USB20_P14 USB20_N14
USB20_P14
45
45 BT 10K_1206_8P4R_5%
E28 DMI4_TXP AH36 USB_OC0#
K29 DMI4_TXN GPP_E9/USB2_OC0# AL40 USB_OC1# RPH6
DMI4_RXP GPP_E10/USB2_OC1# USB_OC2# USB_OC1# 46
M29 AJ44 RC1728 2 @ 1 0_0402_5% USB_OC0#
DMI4_RXN GPP_E11/USB2_OC2# USB_OC3# TYPE_C_OCP# 48 4 5
AL41

m
USB_OC3# 3 6
G17
F16
GPP_E12/USB2_OC3#
PCIE1_RXN/USB31_7_RXN GPP_F15/USB2_OC4#
AV47
AR35
USB_OC4#
USB_OC5#
9/05 Reserve TYPE_C_OCP# to PCH USB_OC2# SF USB_OC2# 2 7
PCIE1_RXP/USB31_7_RXP GPP_F16/USB2_OC5# USB_OC1# 1 8
A17 AR37 USB_OC6#
B17 PCIE1_TXN/USB31_7_TXN GPP_F17/USB2_OC6# AV43 USB_OC7#
R21 PCIE1_TXP/USB31_7_TXP GPP_F18/USB2_OC7#
10K_1206_8P4R_5%
PCIE2_RXN/USB31_8_RXN

co
P21 F4 Within 500 mils RH127 2 1 113_0402_1%
B18 PCIE2_RXP/USB31_8_RXP USB2_COMP F3 RC184 2 1 1K_0402_5%
C18 PCIE2_TXN/USB31_8_TXN USB2_VBUSSENSE U13 +3VALW_PCH
K18 PCIE2_TXP/USB31_8_TXP RSVD11 G3 RC183 2 1 1K_0402_5%
J18 PCIE3_RXN/USB31_9_RXN USB2_ID
B19 PCIE3_RXP/USB31_9_RXP BE41 GPD7 1 RH814 2
C19 PCIE3_TXN/USB31_9_TXN GPD7 100K_0402_5%
C N18 PCIE3_TXP/USB31_9_TXP G45 Strap Pin, refer PDG C

s.
R18 PCIE4_RXN/USB31_10_RXN PCIE24_TXP G46
D20 PCIE4_RXP/USB31_10_RXP PCIE24_TXN Y41
C20 PCIE4_TXN/USB31_10_TXN PCIE24_RXP Y40
PCIE4_TXP/USB31_10_TXP PCIE24_RXN

2
F20 G48
G20 PCIE5_RXN PCIE23_TXP G49 RH837

ic
B21 PCIE5_RXP PCIE23_TXN W44 @
PCIE5_TXN PCIE23_RXP 10K_0201_5%
A22 W43
K21 PCIE5_TXP PCIE23_RXN H48
PCIE6_RXN PCIE22_TXP

1
J21 H47
D21 PCIE6_RXP PCIE22_TXN U41

at
C21 PCIE6_TXN PCIE22_RXP U40
L24 PCIE6_TXP PCIE22_RXN F46
J24 PCIE7_RXN PCIE21_TXP G47
C23 PCIE7_RXP PCIE21_TXN R44
B23 PCIE7_TXN PCIE21_RXP T43
F24 PCIE7_TXP PCIE21_RXN
PCIE8_RXN

em
G24
B24 PCIE8_RXP
C24 PCIE8_TXN
PCIE8_TXP 2 OF 13
CANNONLAKE-H-PCH_FCBGA874
@

ch
+3VS

kS
@ PCH_GPU_EVENT#
RH19 2 1 10K_0402_5%

Need to confirm with intel 0526@Stone

B +1.8VALW B

UH1M
RH815 1 2 10K_0201_5% GPP_J4
oo
PXS_PWREN RC10 2 @ 1 0_0402_5% PXS_PWREN_R AW13 BD4 CNVI_WR_CLK_N
28,29 PXS_PWREN PCH_GPU_EVENT# GPP_G0/SD_CMD CNV_WR_CLKN CNVI_WR_CLK_N 45
GPP_J6 BE9 BE3 CNVI_WR_CLK_P
RH809 1 2 20K_0402_5% RH812 1 @ 2 2.2K_0402_5% 28 PCH_GPU_EVENT# GPP_G1/SD_A0 CNV_WR_CLKP CNVI_WR_CLK_P 45
BF8
BF9 GPP_G2/SD_A1 BB3 CNVI_WR_D0_N
RH810 1 @ 2 2.2K_0201_5% GPP_J9 RH808 1 @ 2 2.2K_0201_5% PXS_RST# @ PXS_RST#_R GPP_G3/SD_A2 CNV_WR_D0N CNVI_WR_D0_N 45
RC12 2 1 0_0201_5% BG8 BB4 CNVI_WR_D0_P
Strap Pin 28 PXS_RST#
BE8 GPP_G4/SD_A3 CNV_WR_D0P BA3 CNVI_WR_D1_N
CNVI_WR_D0_P 45
GPP_G5/SD_CD# CNV_WR_D1N CNVI_WR_D1_N 45
BD8 BA2 CNVI_WR_D1_P
eb

PCH_FB_GC6_EN GPP_G6/SD_CLK CNV_WR_D1P CNVI_WR_D1_P 45

AV13
28 PCH_FB_GC6_EN GPP_G7/SD_WP BC5 CNVI_WT_CLK_N CNVI_WT_CLK_N 45
CNV_WT_CLKN BB6 CNVI_WT_CLK_P
+1.8VALW CNV_WT_CLKP CNVI_WT_CLK_P 45
AP3
AP2 GPP_I11/M2_SKT2_CFG0 BE6 CNVI_WT_D0_N
GPP_I12/M2_SKT2_CFG1 CNV_WT_D0N CNVI_WT_D0_N 45
AN4 BD7 CNVI_WT_D0_P
GPP_I13/M2_SKT2_CFG2 CNV_WT_D0P CNVI_WT_D0_P 45
AM7 BG6 CNVI_WT_D1_N
GPP_I14/M2_SKT2_CFG3 CNV_WT_D1N CNVI_WT_D1_N 45
BF6 CNVI_WT_D1_P
ot

CNV_WT_D1P CNVI_WT_D1_P 45
AV6 BA1 R10391 1 CNVI@ 2
RH831 RH832 GPP_J0/CNV_PA_BLANKING CNV_WT_RCOMP
AY3 150_0402_1%
20K_0402_5% 20K_0402_5% GPP_ J1 / CPU_C10_GATE#
AR13 B12 PCIE_RCOMN
@ @ GPP_J11/A4WP_PRESENT PCIE_RCOMPN
AV7 A13 PCIE_RCOMP RH741 2 1 100_0402_1% CAD Note:
AW3 GPP_J10 PCIE_RCOMPP BE5 SD_1P8_RCOMP RH742 1 2 200_0402_1% Trace width=15 mils ,Spacing=15mil
2

AT10 GPP_J2 SD_1P8_RCOMP BE4 SD_3P3_RCOMP RH819 1 2 200_0402_1%

GPP_J4 GPP_J3 SD_3P3_RCOMP Max length= N/A mils.
N

45 CNVI_BRI_DT R10389 1 CNVI@ 2 33_0402_5% AV4 BD1

AY2 GPP_J4/CNV_BRI_DT_UART0B_RTS# GPPJ_RCOMP_1P8_1 BE1 RCOMP_1P8 RH820 1 2 200_0402_1%
45 CNVI_BRI_RSP GPP_J5/CNV_BRI_RSP/UART0B_RXD GPPJ_RCOMP_1P8_2 0602 Stone: Add refer to EDS&CRB
R10393 1 CNVI@ 2 33_0402_5% GPP_J6 BA4 BE2
45 CNVI_RGI_DT GPP_J6/CNV_RGI_DT/UART0B_TXD GPPJ_RCOMP_1P8_3
AV3
45 CNVI_RGI_RSP GPP_J7/CNV_RGI_RSP/UART0B_CTS#
AW2 Y35
GPP_J9 AU9 GPP_J8/CNV_MFUART2_RXD RSVD12 Y36
GPP_J9/CNV_MFUART2_TXD RSVD13
BC1 CNVI_LDO_MON 1
RSVD14 TH38 @
13 OF 13 AL35
TP_2
CANNONLAKE-H-PCH_FCBGA874
@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/26 Deciphered Date 2018/09/20 Blank

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FG541/FG741 1.0

Date: Tuesday, March 26, 2019 Sheet 19 of 69

5 4 3 2 1
 5 4 3 2 1

+3VS
Bit 6 Boot BIOS
Destination

RH160 2 @ 1 10K_0402_5% PCH_BT_OFF#

0 SPI (Default)
GPP_B22 /GSPI1_MOSI (Boot BIOS Strap Bit BBS)
RH161 2 @ 1 10K_0402_5% PCH_WLAN_OFF# This Signal has a weak internal pull-down.
This field determines the destination of accesses to the
BIOS memory range. Also controllable using Boot BIOS 1 LPC
Destination bit (Bus0, Device31, Function0, offset DCh,bit6)
0: SPI(default)
1: LPC
D Notes: D
1. The internal pull-down is disabled after PCH_PWROK is high.
4. This signal is in the primary well.
Add Board ID reserve 1130SF
+3VALW_PCH +3VALW_PCH +3VALW_PCH
Strap PIN

UH1K
RH750 1 @ 2 4.7K_0402_5% BA26 RH848 RH852 RH846 RH152 RH155 RH153 RH163 RH774 RH776
PCH_WLAN_OFF# BD30 GPP_B22/GSPI1_MOSI BA20
45 PCH_WLAN_OFF# GPP_B21/GSPI1_MISO GPP_D9/ISH_SPI_CS#/GSPI2_CS0#

2
PCH_CMOS_ON# AU26 BB20

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%
DIMM_ONLY@

DIMM_ONLY@
38 PCH_CMOS_ON# GPP_B20/GSPI1_CLK GPP_D10/ISH_SPI_CLK/GSPI2_CLK
AW26 BB16

DIMM_ONLY@
1 N17P@
GPP_B19/GSPI1_CS0# GPP_D11/ISH_SPI_MISO/GP_BSSB_CLK/GSPI2_MISO AN18 @ @ 17@ @

@
GPP_B18_NO_REBOOT BE30 GPP_D12/ISH_SPI_MOSI/GP_BSSB_DI/GSPI2_MOSI
41 GPP_B18_NO_REBOOT GPP_B18/GSPI0_MOSI
BD29 BF14
42,49 LAN_PWR_ON# GPP_B17/GSPI0_MISO GPP_D16/ISH_UART0_CTS#/CNV_WCEN

1
BF29 AR18
BB26 GPP_B16/GSPI0_CLK GPP_D15/ISH_UART0_RTS#/GSPI2_CS1#/CNV_WFEN BF17 PCH_GPA17
GPP_B15/GSPI0_CS0# GPP_D14/ISH_UART0_TXD/I2C2_SCL BE17 PCH_GPA18
GPP_D13/ISH_UART0_RXD/I2C2_SDA PCH_GPH19
EC_SCI# RH780 1 @ 2 0_0402_5% BB24 PCH_GPA19

m
14,49 EC_SCI# PCH_BT_OFF# GPP_C9/UART0A_TXD PCH_GPA20
BE23 PCH_GPH21
45 PCH_BT_OFF# PCH_TP_INT# AP24 GPP_C8/UART0A_RXD AG45 PCH_GPA21
50 PCH_TP_INT# GPP_C11/UART0A_CTS# GPP_H20/ISH_I2C0_SCL PCH_GPH19 PCH_GPA23
BA24 AH46
46 USBDEBUG GPP_C10/UART0A_RTS# GPP_H19/ISH_I2C0_SDA PCH_GPA22

co
BD21 AH47
AW24 GPP_C15/UART1_CTS#/ISH_UART1_CTS# GPP_H22/ISH_I2C1_SCL AH48 PCH_GPH21
AP21 GPP_C14/UART1_RTS#/ISH_UART1_RTS# GPP_H21/ISH_I2C1_SDA
25,28 VGA_PWRGD VGA_ALERT#_PCH GPP_C13/UART1_TXD/ISH_UART1_TXD RH847
AU24 RH849 RH851 RH157 RH158 RH159 RH195 RH775 RH777
GPP_C12/UART1_RXD/ISH_UART1_RXD AV34 PCH_GPA23

2
GPP_A23/ISH_GP5

@ 2

2
PCH_GPA22

10K_0402_5%

10K_0402_5%
AV21 AW32

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%
GPP_C23/UART2_CTS# GPP_A22/ISH_GP4

1 N18P@
AW21 BA33 PCH_GPA21

s.
PCH_UART2_TXD BE20 GPP_C22/UART2_RTS# GPP_A21/ISH_GP3 BE34 PCH_GPA20 @
@ 15@ @ @ @

@
45 PCH_UART2_TXD PCH_UART2_RXD GPP_C21/UART2_TXD GPP_A20/ISH_GP2 PCH_GPA19
BD20 BD34
45 PCH_UART2_RXD GPP_C20/UART2_RXD GPP_A19/ISH_GP1 BF35 PCH_GPA18

1
GPP_A18/ISH_GP0

1
BE21 BD38 PCH_GPA17

ic
50 TP_I2C_SCL0 GPP_C19/I2C1_SCL GPP_A17/SD_VDD1_PWR_EN#/ISH_GP7
BF21
50 TP_I2C_SDA0 PCH_RTS5455_SCL BC22 GPP_C18/I2C1_SDA
PCH_RTS5455_SDA BF23 GPP_C17/I2C0_SCL
C C
BE15 GPP_C16/I2C0_SDA

at
BE14 GPP_D4/ISH_I2C2_SDA/I2C3_SDA/SBK4_BK4
GPP_D23/ISH_I2C2_SCL/I2C3_SCL 11 OF 13
CANNONLAKE-H-PCH_FCBGA874
@

em
ch
DRAM Memory Down(DDR4) DRAMCFG PCH_GPA23 PCH_GPA22 PCH_GPA21
Samsung 8Gb
K4A8G165WC-BCTD 0(0x000) L/RH775 L/RH777 L/RH195

kS
2666 MT/s
Hynix 8Gb
8Gb 2666 MT/s H5AN8G6NCJR-VKC 1(0x001) L/RH775 L/RH777 H/RH163
+1.8VS_AON reservd by Bing 0627
PCH is input Micron 8Gb
SKU ID MT40A512M16LY-075:E 2(0x010) L/RH775 H/RH776 L/RH195
2666 MT/s
oo
HT Micron 8Gb
2
G

2666 MT/s HTH5AN8G6NAFR-VKD 3(0x011) L/RH775 H/RH776 H/RH163

3 1 VGA_ALERT#_PCH
28 VGA_ALERT# Board ID Description Stuff R Smart 8Gb
SDQC8G8W16XCTD9N1T 4(0x100) H/RH774 L/RH777 L/RH195
S

2666 MT/s
eb

QV22
LBSS139WT1G_SC70-3 0 15" EG530 RH157 5(0x101) H/RH774 L/RH777 H/RH163
@
PCH_GPA18
B B
1 17" EG730 RH152 6(0x110) H/RH774 H/RH776 L/RH195
ot

0 Reserved RH158 SODIMM only 7(0x111) H/RH774 H/RH776 H/RH163

reservd for UCMcx by Bing 0718
PCH_GPA19
+3VALW_PCH 1 Reserved RH155
RP5
N

PCH_RTS5455_SDA 1 4
PCH_RTS5455_SCL 2 3 0 non-KB BL RH159
2.2K_0404_4P2R_5% PCH_GPA20
@ 1 KB BL RH153

0 Reserved RH847
PCH_GPA17
1 Reserved RH846

0 Reserved RH849
PCH_GPH19
1 Reserved RH848

0 Reserved RH851
PCH_GPH21
1 Reserved RH852

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/26 Deciphered Date 2018/09/20 PCH (6/9) GPPPABCD, I2C
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
FG541/FG741 1.0

Date: Tuesday, March 26, 2019 Sheet 20 of 69

5 4 3 2 1
 5 4 3 2 1

+3VS +3VALW_PCH

1
1
RH760
RH759
@ 0_0805_5%
0_0805_5%
@
+VCCPFUSE_3P3

2
2
+VCCPRIM_1P05
D D
@ 2 0_0402_5% +3VALW_PCH_R
RH220 1
Need short

1
+1.05VALW +VCCPRIM_1P05
RH789
0_0805_5%
JC2 UH1H
@ 1 2 AA22 AW9
1 2 VCCPRIM_1P05_1 VCCPRIM_3P3_2 +VCCPHV_3P3
AA23
+VCCPRIM_FUSE_1P05 2 @ VCCPRIM_1P05_2 +VCCPGPPA
AB20 BF47
JUMP_43X79 AB22 VCCPRIM_1P05_3 DCPRTC_1 BG47
@ VCCPRIM_1P05_4 DCPRTC_2 2 @

.1U_0402_10V6-K
RH791 1 2 0_0402_5% AB23 RH222 1 2 0_0402_5%
AB27 VCCPRIM_1P05_5 V23

CH26
+VCCPRIM_CNV_HVLDO_1P05 VCCPRIM_1P05_6 VCCPRIM_3P3_5 +VCCPUSB2_3P3 +VCCPGPPBC
AB28 AN44 @
VCCPRIM_1P05_7 VCCSPI +3V_SPI 1
AB30
@ VCCPRIM_1P05_8 @
RH790 1 2 0_0402_5% 4.174A (VCCPRIM_1P05) AD20 BC49 RH223 1 2 0_0402_5%
AD23 VCCPRIM_1P05_9 VCCRTC_1 BD49
VCCPRIM_1P05_10 VCCRTC_2 +VCCRTC_3P3 +VCCPGPPEF
+VCCDUSB_1P05 AD27
AD28 VCCPRIM_1P05_11 AN21
@ VCCPRIM_1P05_12 VCCPGPPG_3P3 +VCCPGPPG @
RH792 1 2 0_0402_5% AD30 AY8 +VCCPHVLDO_3P3 RH224 1 2 0_0402_5%
+VCCPRIM_1P05 +VCCMPHY_1P05 AF23 VCCPRIM_1P05_13 VCCPRIM_3P3_3 BB7
VCCPRIM_1P05_16 VCCPRIM_3P3_4 +VCCPGPPG
+VCCDSW_1P05 AF27

m
JC4 AF30 VCCPRIM_1P05_17 AC35
VCCPRIM_1P05_18 VCCPGPPHK_1 +VCCPGPPHK @
RH793 1 @ 2 0_0402_5% 1 2 U26 AC36 RH225 1 2 0_0402_5%
@ 1 2 U29 VCCPRIM_1P05_23 VCCPGPPHK_2 AE35
VCCPRIM_1P05_24 VCCPGPPEF_1 +VCCPGPPEF +VCCPUSB2_3P3
+VCCCLPLLEBB_1P05 V25 AE36
JUMP_43X79 VCCPRIM_1P05_25 VCCPGPPEF_2

co
V27 @
VCCPRIM_1P05_26 RH226 1 2 0_0402_5%
@ Add Jump by Bing 0627 V28 AN24
RH794 1 2 0_0402_5% VCCPRIM_1P05_27 VCCPGPPD +VCCPGPPD +VCCPGPPEF +VCCPGPPHK
V30
V31 VCCPRIM_1P05_28 AN26 +VCCPGPPHK
+VCCAZPLL_1P05 VCCPRIM_1P05_29 VCCPGPPBC_1 AP26
VCCPGPPBC_2 +VCCPGPPBC

.1U_0402_10V6-K
AD31

.1U_0402_10V6-K
@ +VCCPRIM_FUSE_1P05 @
RH795 1 2 0_0402_5% VCCPRIM_1P05_14 RH784 1 2 0_0402_5%
AE17 AN32

s.
+VCCPRIM_CNV_HVLDO_1P05 +VCCPGPPA 1 1
VCCPRIM_1P05_15 VCCPGPPA

CH270
+VCCA_SRC_1P05 +VCCPHV_3P3

CH81
+VCCDUSB_1P05 W22 AT44 +VCCPFUSE_3P3
W23 VCCDUSB_1P05_1 VCCPRIM_3P3_1 @
@ RH746 1 2 0_0402_5% @ @
RH797 1 2 0_0402_5% VCCDUSB_1P05_2 2 2
BE48

ic
VCCDSW_3P3_1 +VCCDSW +VCCPHVLDO_3P3
+VCCA_OCPLL1_1P05 BG45 BE49
+VCCDSW_1P05 VCCDSW_1P05_1 VCCDSW_3P3_2
BG46
VCCDSW_1P05_2 @
C @ BB14 +VCCHDA RH785 1 2 0_0402_5% C
RH787 1 2 0_0402_5%
W31 VCCHDA

at
+VCCCLPLLEBB_1P05 VCCPRIM_MPHY_1P05
+VCCA_OC_1P05 +VCCAZPLL_1P05 D1 AG19
E1 VCCPRIM_1P05_21 VCCPRIM_1P8_3 AG20 +VCCPGPPD
@ VCCPRIM_1P05_22 VCCPRIM_1P8_4 AN15
RH798 1 2 0_0402_5% VCCPRIM_1P8_5
+VCCAMPHYPLL_1P05 C49 AR15 @
D49 VCCAMPHYPLL_1P05_1 VCCPRIM_1P8_6 BB11 RH221 1 2 0_0402_5%

em
+VCCA_BCLKPLL2_1P05 VCCAMPHYPLL_1P05_2 VCCPRIM_1P8_7 +VCCPRIM_1P8
E49
@ VCCAMPHYPLL_1P05_3 AF19
RH799 1 2 0_0402_5%
P2 VCCPRIM_1P8_1 AF20 Option1:Use external VRM(default)
+VCCA_XTAL_1P05 VCCA_XTAL_1P05_1 VCCPRIM_1P8_2 +VCCPHVLDO_1P8 stuff RH816,unstuff RH807
P3
VCCA_XTAL_1P05_2 AG31 Option2:Use internal LDO
VCCPRIM_1P05_20 +VCCFHV1_1P05 unstuff RH816,stuff RH807
+VCCA_SRC_1P05 W19 AF31 +VCCFHV0_1P05 RH807
VCCA_SRC_1P05_1 VCCPRIM_1P05_19 +VCCPHVLDO_1P8 +VCCPRIM_1P8 1 @
+VCCPRIM_1P05 W20 1 2 0_0402_5% 2 0_0402_5%
VCCA_SRC_1P05_2 +1.8VALW
+VCCFHV1_1P05 AK22 @

ch
VCCPRIM_1P24_1 +VCCLDOSRAM_IN_1P24 RH816
+VCCA_OCPLL1_1P05 C1 AK23
@ VCCAPLL_1P05_4 VCCPRIM_1P24_2
RH199 1 2 0_0402_5% C2
VCCAPLL_1P05_5 AJ22
+VCCFHV0_1P05 V19 VCCDPHY_1P24_1 AJ23
+VCCA_OC_1P05 VCCA_BCLK_1P05 VCCDPHY_1P24_2 +VCCDPHY_1P24 1 1
BG5

CH278
1U_0402_6.3V6K

C10118
4.7U_0603_6.3V6K
@ VCCDPHY_1P24_3 +VCCDPHY_1P24_MAR
RH200 1 2 0_0402_5% B1

kS
+VCCA_BCLKPLL2_1P05 B2 VCCAPLL_1P05_1 8 OF 13 K47 @
B3 VCCAPLL_1P05_2 VCCMPHY_SENSE K46 2 2
VCCAPLL_1P05_3 VSSMPHY_SENSE
CANNONLAKE-H-PCH_FCBGA874
@
oo
@ +VCCDPHY_1P24
RH817 1 2 0_0402_5%

+VCCDPHY_1P24_MAR @ +VCCLDOSRAM_IN_1P24
+VCCPRIM_1P05 RH818 1 2 0_0402_5%
+VCCMPHY_1P05 +VCCDSW_1P05 +VCCA_BCLKPLL2_1P05 +VCCDUSB_1P05
eb

4.7U_0603_6.3V6K
1

C10119
CH253
22U_0603_6.3V6-M

1U_0402_6.3V6K

.1U_0402_10V6-K

1 1 1 1 2 1 2
CH29
22U_0603_6.3V6-M

CH30
1U_0402_6.3V6K

1U_0402_6.3V6K
CH25

1U_0402_6.3V6K
CH272

CH292

Place close to BG5

B 2 B
CH279

@ @ +VCCPRIM_1P05
2 2 2 2 @ 1 2 1
ot

+VCCA_XTAL_1P05

RH827 1 @ 2 0_0603_5%
N

CH276
22U_0603_6.3V6-M

CH274
22U_0603_6.3V6-M
1 1
+VCCAMPHYPLL_1P05
VCCRTC +VCCRTC_3P3
LH2 1 @ 2 0_0603_5% 2@ 2@ @
RH216 1 2 0_0402_5%

1 1 1

1U_0402_6.3V6K

.1U_0402_10V6-K
folllow PDG:
CH255
1U_0402_6.3V6K

CH273
22U_0603_6.3V6-M

CH275
22U_0603_6.3V6-M
placeholder LC filter 1 1

CH245
If used,need to confirm LC spec

CH244
2 2 @ 2 @
2 2

+3VALW +VCCHDA

@
RC292 1 2 0_0402_5%
+3VALW_PCH +VCCDSW

RH206 1 @ 2 0_0402_5%

+3VS +3VALW

@
LH3 1 @ 2 0_0402_5% RH205 1 2 0_0402_5%

.1U_0402_10V6-K
+VCCA_OCPLL1_1P05 +VCCPHVLDO_3P3 +VCCCLPLLEBB_1P05 +VCCAZPLL_1P05 +VCCA_OC_1P05

.1U_0402_10V6-K
2 1

CH248

CH271
A A
@
.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

1 2
2 1 1 1 2 1
CH287
1U_0402_6.3V6K

CH288

CH289

CH290
1U_0402_6.3V6K

CH291
1U_0603_25V7K
C10050

1@ 2 2@ 2@ 1@ 2@

Security Classification LC Future Center Secret Data Title

follow CRB
Issued Date 2015/02/26 Deciphered Date 2018/09/20 PCH (7/9) PWR
reservd by Bing 0627 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
FG541/FG741 1.0

Date: Tuesday, March 26, 2019 Sheet 21 of 69

5 4 3 2 1
 5 4 3 2 1

UH1L
BG3 M24
BG33 VSS_145 VSS_196 M32 UH1I
BG37 VSS_146 VSS_197 M34 A2 AL12
BG4 VSS_147 VSS_198 M49 A28 VSS_1 VSS_73 AL17
BG48 VSS_148 VSS_199 M5 A3 VSS_2 VSS_74 AL21
C12 VSS_149 VSS_200 N12 A33 VSS_3 VSS_75 AL24
D C25 VSS_150 VSS_201 N16 A37 VSS_4 VSS_76 AL26 D
C30 VSS_151 VSS_202 N34 A4 VSS_5 VSS_77 AL29
C4 VSS_152 VSS_203 N35 A45 VSS_6 VSS_78 AL33
C48 VSS_153 VSS_204 N37 A46 VSS_7 VSS_79 AL38
C5 VSS_154 VSS_205 N38 A47 VSS_8 VSS_80 AM1
D12 VSS_155 VSS_206 P26 A48 VSS_9 VSS_81 AM18
D16 VSS_156 VSS_207 P29 A5 VSS_10 VSS_82 AM32 UH1J
D17 VSS_157 VSS_208 P4 A8 VSS_11 VSS_83 AM49 Y14
D30 VSS_158 VSS_209 P46 AA19 VSS_12 VSS_84 AN12 RSVD7 Y15
D33 VSS_159 VSS_210 R12 AA20 VSS_13 VSS_85 AN16 RSVD8
VSS_160 VSS_211 VSS_14 VSS_86 U37
D8 R16 AA25 AN34 RSVD6
VSS_161 VSS_212 VSS_15 VSS_87 U35
E10 R26 AA27 AN38 RSVD5
E13 VSS_162 VSS_213 R29 AA28 VSS_16 VSS_88 AP4 N32
E15 VSS_163 VSS_214 R3 AA30 VSS_17 VSS_89 AP46 RSVD3 R32
E17 VSS_164 VSS_215 R34 AA31 VSS_18 VSS_90 AR12 RSVD4
VSS_165 VSS_216 VSS_19 VSS_91

m
E19 R38 AA49 AR16 AH15
E22 VSS_166 VSS_217 R4 AA5 VSS_20 VSS_92 AR34 RSVD2 AH14
E24 VSS_167 VSS_218 T17 AB19 VSS_21 VSS_93 AR38 RSVD1
E26 VSS_168 VSS_219 T18 AB25 VSS_22 VSS_94 AT1

co
E31 VSS_169 VSS_220 T32 AB31 VSS_23 VSS_95 AT16
E33 VSS_170 VSS_221 T4 AC12 VSS_24 VSS_96 AT18 AL2
E35 VSS_171 VSS_222 T49 AC17 VSS_25 VSS_97 AT21 PREQ#
10 OF 13 AM5 PCH_PREQ# 41
E40 VSS_172 VSS_223 T5 AC33 VSS_26 VSS_98 AT24 PRDY# AM4 PCH_PRDY# 41

s.
VSS_173 VSS_224 VSS_27 VSS_99 CPU_TRST# CPU_TRST# 41
E42 T7 AC38 AT26 AK3 PCH_TRIGOUT RH7581 2 30_0402_1% CPU_TRIGIN 6
C VSS_174 VSS_225 VSS_28 VSS_100 TRIGGER_OUT C
E8 U12 AC4 AT29 AK2
VSS_175 VSS_226 VSS_29 VSS_101 TRIGGER_IN PCH_TRIGIN 6
F41 U15 AC46 AT32

ic
F43 VSS_176 VSS_227 U17 AD1 VSS_30 VSS_102 AT34 CANNONLAKE-H-PCH_FCBGA874
F47 VSS_177 VSS_228 U21 AD19 VSS_31 VSS_103 AT45
VSS_178 VSS_229 VSS_32 VSS_104 @
G44 U24 AD2 AV11

at
G6 VSS_179 VSS_230 U33 AD22 VSS_33 VSS_105 AV39
H8 VSS_180 VSS_231 U38 AD25 VSS_34 VSS_106 AW10
J10 VSS_181 VSS_232 V20 AD49 VSS_35 VSS_107 AW4
J26 VSS_182 VSS_233 V22 AE12 VSS_36 VSS_108 AW40

em
J29 VSS_183 VSS_234 V4 AE33 VSS_37 VSS_109 AW46
J4 VSS_184 VSS_235 V46 AE38 VSS_38 VSS_110 B47
J40 VSS_185 VSS_236 W25 AE4 VSS_39 VSS_111 B48
J46 VSS_186 VSS_237 W27 AE46 VSS_40 VSS_112 B49
J47 VSS_187 VSS_238 W28 AF22 VSS_41 VSS_113 BA12
VSS_188 VSS_239 VSS_42 VSS_114

ch
J48 W30 AF25 BA14
J9 VSS_189 VSS_240 Y10 AF28 VSS_43 VSS_115 BA44
K11 VSS_190 VSS_241 Y12 AG1 VSS_44 VSS_116 BA5
K39 VSS_191 VSS_242 Y17 AG22 VSS_45 VSS_117 BA6
M16 VSS_192 VSS_243 Y33 AG23 VSS_46 VSS_118 BB41

kS
M18 VSS_193 VSS_244 AG25 VSS_47 VSS_119 BB43
M21 VSS_194 Y38 AG27 VSS_48 VSS_120 BB9
VSS_19512 OF 13VSS_245 Y9 AG28 VSS_49 VSS_121 BC10
VSS_246 AG30 VSS_50 VSS_122 BC13
oo
VSS_51 VSS_123
B CANNONLAKE-H-PCH_FCBGA874 AG49 BC15 B
AH12 VSS_52 VSS_124 BC19
@ VSS_53 VSS_125
AH17 BC24
AH33 VSS_54 VSS_126 BC26
AH38 VSS_55 VSS_127 BC31
eb

AJ19 VSS_56 VSS_128 BC35

AJ20 VSS_57 VSS_129 BC40
AJ25 VSS_58 VSS_130 BC45
AJ27 VSS_59 VSS_131 BC8
VSS_60 VSS_132
ot

AJ28 BD43
AJ30 VSS_61 VSS_133 BE44
AJ31 VSS_62 VSS_134 BF1
AK19 VSS_63 VSS_135 BF2
N

AK20 VSS_64 VSS_136 BF3

AK25 VSS_65 VSS_137 BF48
AK27 VSS_66 VSS_138 BF49
AK28 VSS_67 VSS_139 BG17
AK30 VSS_68 VSS_140 BG2
AK31 VSS_69 VSS_141 BG22
AK4 VSS_70 VSS_142 BG25
AK46 VSS_71 VSS_143 BG28
VSS_72 9 OF 13 VSS_144
CANNONLAKE-H-PCH_FCBGA874
@
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/26 Deciphered Date 2018/09/20 PCH (9/9) VSS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
B
FG541/FG741 1.0

Date: Tuesday, March 26, 2019 Sheet 22 of 69

5 4 3 2 1
 5 4 3 2 1

D D

m
co
s.
ic
C C

at
em
ch
kS
oo
eb

B B
ot
N

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2018/09/20 Cover Page

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
FG541/FG741 1.0

Date: Tuesday, March 26, 2019 Sheet 23 of 69

5 4 3 2 1
 5 4 3 2 1

STRAP2 STRAP1 STRAP0 RAMCFG[4:0] H=High: Tied to 1.8V

N17P-G1 GPIO M=Middle: Tied to 0.9V
L L L 00000
L=Low: Tied to 0V
GPIO I/O ACTIVE Function Description I/O Termination L H L 00010

GPIO0 OUT - PWM Output to control NVVDD L H H 00011

GPIO1 OUT - FB Enable for GC6 2.1 H H L 00110

GPIO2 IN - GPU wake signal for GC6 2.1 H H H 00111

D D

GPIO3 OUT - PWM Output to control the SRAM power supply

ROM_SO ROM_SI ROM_SCLK SOR_EXPOSED[3:0] 1:ENABLE 0:DISABLE
GPIO4 OUT - GPU power sequencing for GC6 2.1 --- 1V8_MAIN_EN
L L L 1111 DEFAULT SOR0/1/2/3 ENABLE
GPIO5 IN N/A Active low Frame Lock
L L H 1110
GPIO6 OUT - Phase Shedding, NVVDD_PSI
L H L 1101
GPIO7 OUT N/A Panel Backlight enable
L H H 1100
GPIO8 OUT - Memory voltage Control
H L L 1011
GPIO9 I/O - Active Low Thermal Alert

m
H L H 1010
GPIO10 OUT - Memory VREF Control (100K pull Down)

co
H H L 1001
GPIO11 OUT - Panel Power enable
H H H 1000
GPIO12 IN - AC power detect or power supply overdraw input (10K pull High)
L L

s.
M 0111
GPIO13 OUT N/A LCD Panel Backlight Enable
L M L 0110

ic
GPIO14 IN N/A Hot Plug Detect for IFPA
L M H 0101
C GPIO15 IN N/A Hot Plug Detect for IFPB C

at
L H M 0100
GPIO16 OUT - System side PCIe reset monitor
H L M 0011
GPIO17 IN N/A Hot Plug Detect for IFPD

em
H M L 0010
GPIO18 IN N/A Hot Plug Detect for IFPE
H M H 0001
GPIO19 OUT N/A 3D Vision L/R Signal
H H M 0000

ch
GPIO20 N/A GC5_MODE

GPIO21 I/O N/A UNUSED

1:SMB_ALT_ADDR ENABLE
STRAP5 STRAP4 STRAP3 SMB_ALT_ADDR DEVID_SEL PCIE_CFG VGA_DEVICE

kS
GPIO22 I/O N/A UNUSED 0:SMB_ALT_ADDR DISABLE
M H H 1 1 1 1
GPIO23 OUT - GPU PCIe self-reset control 1:DEVID_SEL REBRAND
M H L 1 1 1 0 0:DEVID_SEL ORIGNAL
oo
GPIO24 IN N/A Hot Plug Detect for IFPF
M L H 1 1 0 1 1:PCIE_CFG LOW POWER
GPIO25 N/A UNUSED
0:PCIE_CFG HIGH POWER
M L L 1 1 0 0
GPIO26 N/A UNUSED
eb

1:VGA_DEVICE ENABLE
L H M 1 0 1 1
GPIO27 IN N/A Hot Plug Detect for IFPC 0:VGA_DEVICE DISABLE
B B
L M H 1 0 1 0
ot

L M L 1 0 0 1

L L M 1 0 0 0
N

H H H 0 1 1 1
N17P-G1 Power Sequence
H H L 0 1 1 0

H L H 0 1 0 1

H L L 0 1 0 0

+1.8VS_AON NVVDDS/+1.0VGS L H H 0 0 1 1

+1.8VGS L H L 0 0 1 0
NVVDD
NVVDD L L H 0 0 0 1 DEFAULT

NVVDDS/+1.0VGS L L L 0 0 0 0

FBVDDQ

A A
1. All power rail ramp up time should be larger than 40us 1. NVVDDS/PEX_DVDD must ramp down before NVVDD, all
and is recommended to be less than 2ms. other power rails can ramp down together with NVVDD.

2. T (from 1V8_MAIN_EN to PEX_DVDD/NVVDD_Pgood) 2. All 3.3V devices that connect to the GPU must be
must NOT exceed 4ms. ramp down before 1V8_AON; GPU can NOT have any 3.3V
leakage path after 1V8_AON and 1.8V_MAIN power down.
3. All 3.3V devices that connect to the GPU must be
powered after 1V8_AON; GPU can NOT have any 3.3V 3. The previous power rail must ramp down to 10% before
leakage path before 1V8_AON present. the next power rail can start ramping down.
Security Classification LC Future Center Secret Data Title
4. The previous power rail must ramp up to 90% before
the next power rail can start ramping up.
Issued Date 2015/08/20 Deciphered Date 2016/08/20 VGA Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
FG541/FG741 1.0

Date: Tuesday, March 26, 2019 Sheet 24 of 68

5 4 3 2 1
 5 4 3 2 1

UV1A
1/17 PCI_EXPRESS
3A
D +1.0VGS D
2000mA
Under GPU(below 150mils) Near GPU Mid way
PEX_DVDD AG19
PLT_RST_VGA#

10U 6.3V M X5R 0402

AJ12 PEX_RST PEX_DVDD AG21 1 1 1 1 1 1 2 1 1 1
28 PLT_RST_VGA#

33P_0402_50V8J

33P_0402_50V8J
22U_0603_6.3V6-M
4.7U_0402_6.3V6M

4.7U_0402_6.3V6M
PEX_DVDD AG22

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K
CLK_REQ_GPU# AK12 PEX_CLKREQ PEX_DVDD AG24
AH21

OPT@

OPT@

OPT@

OPT@

CV6 OPT@

CV7 OPT@

CV8 OPT@

OPT@
PEX_DVDD

RF_NS@

RF_NS@
CLK_PCIE_GPU AL13 AH25 2 2 2 2 2 2 1 2 2 2
17 CLK_PCIE_GPU PEX_REFCLK PEX_DVDD
CLK_PCIE_GPU# AK13

CV14

CD85

CD86
17 CLK_PCIE_GPU# PEX_REFCLK

CV2

CV3

CV4

CV5
PCIE_CRX_GTX_P0 CV12 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_P0 AK14 PEX_TX0
5 PCIE_CRX_GTX_P0 PCIE_CRX_GTX_N0 PCIE_CRX_C_GTX_N0
5 PCIE_CRX_GTX_N0 CV13 1 2 0.22U_0201_6.3V6-K OPT@ AJ14 PEX_TX0

PCIE_CTX_C_GRX_P0 AN12
5 PCIE_CTX_C_GRX_P0
5 PCIE_CTX_C_GRX_N0
PCIE_CTX_C_GRX_N0 AM12
PEX_RX0
PEX_RX0 PEX_HVDD
PEX_HVDD
AG13
AG15
Near GPU 1A
PCIE_CRX_GTX_P1 CV17 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_P1 AH14 PEX_TX1 PEX_HVDD AG16
5 PCIE_CRX_GTX_P1 PCIE_CRX_GTX_N1 PCIE_CRX_C_GTX_N1 AG14
5 PCIE_CRX_GTX_N1 CV19 1 2 0.22U_0201_6.3V6-K OPT@ PEX_TX1 PEX_HVDD AG18 VGA_MAIN_3V_1.8V VGA_MAIN_3V_1.8V

PCIE_CTX_C_GRX_P1 AN14
PEX_HVDD AG25 Under GPU(below 150mils) Near GPU Mid way
5 PCIE_CTX_C_GRX_P1 PEX_RX1 PEX_HVDD AH15

2
PCIE_CTX_C_GRX_N1 AM14

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

PEX_RX1 PEX_HVDD AH18 1 1 1 1 1 1 2 2 1
5 PCIE_CTX_C_GRX_N1

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M
AH26 RV29

22U_0603_6.3V6-M
PEX_HVDD

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K
PCIE_CRX_GTX_P2 CV22 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_P2 AK15 PEX_TX2 PEX_HVDD AH27 0_0402_5%
5 PCIE_CRX_GTX_P2 PCIE_CRX_GTX_N2 PCIE_CRX_C_GTX_N2
CV23 1 2 0.22U_0201_6.3V6-K OPT@ AJ15 AJ27
When VGA_PWRGD is work, CV66 is 100K

OPT@

OPT@

OPT@

OPT@

CV306 OPT@

CV307 OPT@

CV9 OPT@

CV10 OPT@

OPT@
5 PCIE_CRX_GTX_N2 PEX_TX2 PEX_HVDD
AK27 2 2 2 2 2 2 1 1 2
PEX_HVDD

1
PCIE_CTX_C_GRX_P2 AP14 PEX_RX2 PEX_HVDD AL27 VGA_MAIN_3V_1.8V +1.8VS_AON
5 PCIE_CTX_C_GRX_P2 @

CV18
PCIE_CTX_C_GRX_N2 AP15 PEX_RX2 PEX_HVDD AM28 RV8 1 @ 2
5 PCIE_CTX_C_GRX_N2 20,28 VGA_PWRGD

CV303

CV302

CV304

CV305
PEX_HVDD AN28

2
PCIE_CRX_GTX_P3 CV24 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_P3 AL16 75K_0402_5%
5 PCIE_CRX_GTX_P3 PEX_TX3 1

2
PCIE_CRX_GTX_N3 CV25 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_N3 AK16 CV66

OPT@
5 PCIE_CRX_GTX_N3 PEX_TX3
.1U_0402_10V6-K
PCIE_CTX_C_GRX_P3 AN15

co
5 PCIE_CTX_C_GRX_P3 PEX_RX3 @ @

10K_0402_5%
10K_0402_5%
PCIE_CTX_C_GRX_N3 AM15 2
5 PCIE_CTX_C_GRX_N3 PEX_RX3

1
1
PCIE_CRX_GTX_P4 CV26 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_P4 AK17

RV31
PEX_TX4

RV30
5 PCIE_CRX_GTX_P4 PCIE_CRX_GTX_N4 PCIE_CRX_C_GTX_N4
5 PCIE_CRX_GTX_N4 CV27 1 2 0.22U_0201_6.3V6-K OPT@ AJ17 PEX_TX4

2
5 PCIE_CTX_C_GRX_P4
PCIE_CTX_C_GRX_P4 AN17 PEX_RX4
MAX:100mA
PCIE_CTX_C_GRX_N4 AM17 PEX_RX4
5 PCIE_CTX_C_GRX_N4 CLK_REQ_GPU#

s.
17 GPU_CLKREQ# 1 3
PCIE_CRX_GTX_P5 CV28 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_P5 AH17 PEX_TX5 Near GPU VGA_MAIN_3V_1.8V
5 PCIE_CRX_GTX_P5 PCIE_CRX_GTX_N5 PCIE_CRX_C_GTX_N5 AG17
5 PCIE_CRX_GTX_N5 CV29 1 2 0.22U_0201_6.3V6-K OPT@ PEX_TX5 N17 1.8V
PEX_PLL_HVDD AH12
PEX_PLL_HVDD RV7 1 @ 2 0_0402_5% QV5
PCIE_CTX_C_GRX_P5 AP17 PEX_RX5 LSI1012XT1G_SC-89-3
5 PCIE_CTX_C_GRX_P5 PCIE_CTX_C_GRX_N5

2
AP18 LBSS139WT1G OPT@

ic
5 PCIE_CTX_C_GRX_N5 PEX_RX5 1

0.1U_6.3V_K_X5R_0201
Vds=50V RV33
PCIE_CRX_GTX_P6 CV30 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_P6 AK18 @ 10K_0402_5%
5 PCIE_CRX_GTX_P6 PCIE_CRX_GTX_N6 PCIE_CRX_C_GTX_N6
PEX_TX6 Vgs= +-20V
5 PCIE_CRX_GTX_N6 CV34 1 2 0.22U_0201_6.3V6-K OPT@ AJ18 PEX_TX6 N16 3.3V Vgs(th)=0.5V--1V 1 @ 2
C 2 RV35 C

OPT@

1
PCIE_CTX_C_GRX_P6 AN18 0_0402_5%

CV131
5 PCIE_CTX_C_GRX_P6 PEX_RX6

at
PCIE_CTX_C_GRX_N6 AM18 PEX_RX6
5 PCIE_CTX_C_GRX_N6
PCIE_CRX_GTX_P7 CV35 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_P7 AL19 PEX_TX7
5 PCIE_CRX_GTX_P7 PCIE_CRX_GTX_N7 PCIE_CRX_C_GTX_N7
5 PCIE_CRX_GTX_N7 CV36 1 2 0.22U_0201_6.3V6-K OPT@ AK19 PEX_TX7

PCIE_CTX_C_GRX_P7 AN20 PEX_RX7

5 PCIE_CTX_C_GRX_P7 PCIE_CTX_C_GRX_N7 AM20
5 PCIE_CTX_C_GRX_N7 PEX_RX7

em
PCIE_CRX_GTX_P8 CV452 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_P8 AK20 PEX_TX8
5 PCIE_CRX_GTX_P8 PCIE_CRX_GTX_N8 PCIE_CRX_C_GTX_N8
5 PCIE_CRX_GTX_N8 CV39 1 2 0.22U_0201_6.3V6-K OPT@ AJ20 PEX_TX8

PCIE_CTX_C_GRX_P8 AP20 PEX_RX8

5 PCIE_CTX_C_GRX_P8 PCIE_CTX_C_GRX_N8 AP21 PEX_RX8
5 PCIE_CTX_C_GRX_N8
PCIE_CRX_GTX_P9 CV40 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_P9 AH20 PEX_TX9
5 PCIE_CRX_GTX_P9 PCIE_CRX_GTX_N9 PCIE_CRX_C_GTX_N9 AG20
5 PCIE_CRX_GTX_N9 CV42 1 2 0.22U_0201_6.3V6-K OPT@ PEX_TX9 CV33 1 2 0.1u_0201_10V6K
OPT@
PCIE_CTX_C_GRX_P9 AN21

ch
5 PCIE_CTX_C_GRX_P9 PEX_RX9
PCIE_CTX_C_GRX_N9 AM21 PEX_RX9 CV37 1 2 0.1u_0201_10V6K
5 PCIE_CTX_C_GRX_N9
OPT@
PCIE_CRX_GTX_P10 CV43 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_P10 AK21
5 PCIE_CRX_GTX_P10 PCIE_CRX_GTX_N10 CV44 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_N10 AJ21
PEX_TX10 MAX:250mA CV32 1 2 0.1u_0201_10V6K
DG Require 0.1U *3Pcs
5 PCIE_CRX_GTX_N10 PEX_TX10
OPT@
PCIE_CTX_C_GRX_P10 AN23 PEX_RX10
5 PCIE_CTX_C_GRX_P10 PCIE_CTX_C_GRX_N10 AM23 CORE_PLLVDD
5 PCIE_CTX_C_GRX_N10 PEX_RX10 CV16 1 2 0.1u_0201_10V6K
UV1O

kS
VGA_MAIN_3V_1.8V OPT@
PCIE_CRX_GTX_P11 CV45 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_P11 AL22 PEX_TX11 30 ohms @100MHz (ESR=0.05) 11/17 XTAL_PLL
5 PCIE_CRX_GTX_P11 PCIE_CRX_GTX_N11 PCIE_CRX_C_GTX_N11 AK22
5 PCIE_CRX_GTX_N11 CV46 1 2 0.22U_0201_6.3V6-K OPT@ PEX_TX11 +1.8VS_AON
LV1 2 1 CORE_PLLVDD AD8 XS_PLLVDD
PCIE_CTX_C_GRX_P11 AP23 PEX_RX11 OPT@ H26 GPCPLL_AVDD
5 PCIE_CTX_C_GRX_P11 PCIE_CTX_C_GRX_N11 AP24 PEX_RX11 HCB1608KF-300T60_2P AE8 SP_PLLVDD
5 PCIE_CTX_C_GRX_N11

22U_0603_6.3V6-M
1 1
PCIE_CRX_GTX_P12 PCIE_CRX_C_GTX_P12 AK23

2
4.7U_0402_6.3V6M
5 PCIE_CRX_GTX_P12 CV47 1 2 0.22U_0201_6.3V6-K OPT@ PEX_TX12 AD7 VID_PLLVDD
PCIE_CRX_GTX_N12 CV48 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_N12 AJ23 RV211
5 PCIE_CRX_GTX_N12 PEX_TX12
oo 10K_0402_5%

CV15 OPT@
@
PCIE_CTX_C_GRX_P12 AN24 2 2 @
5 PCIE_CTX_C_GRX_P12 PEX_RX12

CV11
PCIE_CTX_C_GRX_N12 AM24 PEX_RX12
5 PCIE_CTX_C_GRX_N12

1
PCIE_CRX_GTX_P13 CV49 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_P13 AH23 PEX_TX13 XTALSSIN H1 XTAL_SSIN XTAL_OUTBUFF J4 XTALOUT
5 PCIE_CRX_GTX_P13 PCIE_CRX_GTX_N13 PCIE_CRX_C_GTX_N13 AG23
5 PCIE_CRX_GTX_N13 CV50 1 2 0.22U_0201_6.3V6-K OPT@ PEX_TX13

2
PCIE_CTX_C_GRX_P13 AN26 PEX_RX13 RV14 XTAL_IN H3 XTAL_IN XTAL_OUT H2 XTAL_OUT
5 PCIE_CTX_C_GRX_P13 PCIE_CTX_C_GRX_N13 AM26

1
eb

5 PCIE_CTX_C_GRX_N13 PEX_RX13 10K_0402_5%

OPT@ N17P-G1_FCBGA908 @ RV46
PCIE_CRX_GTX_P14 CV54 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_P14 AK24 PEX_TX14 COMMON RV209 10K_0402_5%
5 PCIE_CRX_GTX_P14

1
PCIE_CRX_GTX_N14 CV55 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_N14 AJ24 PEX_TX14 ? 1 2 OPT@
5 PCIE_CRX_GTX_N14
INS37068455 10M_0402_5%

2
PCIE_CTX_C_GRX_P14 AP26 PEX_RX14 OPT@
B 5 PCIE_CTX_C_GRX_P14 PCIE_CTX_C_GRX_N14 AP27 B
5 PCIE_CTX_C_GRX_N14 PEX_RX14

PCIE_CRX_GTX_P15 CV56 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_P15 AL25 YV1

5 PCIE_CRX_GTX_P15 PEX_TX15
ot

PCIE_CRX_GTX_N15 CV57 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_N15 AK25 PEX_TX15

5 PCIE_CRX_GTX_N15 XTAL_IN 1 4
PCIE_CTX_C_GRX_P15 AN27 PEX_TERMP OPT@ OSC1 GND2
5 PCIE_CTX_C_GRX_P15 PEX_RX15 PEX_TERMP AP29 1 2
PCIE_CTX_C_GRX_N15 AM27 PEX_RX15 RV34 2 3 XTAL_OUT
5 PCIE_CTX_C_GRX_N15 GND1 OSC2
2.49K_0402_1%
1 1
27MHZ_10PF_7V27000050
N

CV262 OPT@ CV263

Change PEG from X8 to X16 N17P-G1_FCBGA908 8P_50V_B_NPO_0402 8P_50V_B_NPO_0402
2 2
SF SDV 20170810 INS37068967
?
OPT@ OPT@

COMMON
@

1 @ 2
WRST# 49
RV20

+1.8VS_AON
0_0402_5% For SWG mode
1 @ 2
H_THRMTRIP# 6,14
RV1
1

0_0402_5%
RV2
1
For UMA mode
choose one @ 10K_0402_5%
D 2
@
CV1
0.1u_0201_10V6K
3
2

5 QV1B LBSS138LT1G
G LBSS138DW1T1G_SOT363-6 Vds=50V
S @ Id=200mA
4

D Rdson=Max10ohm
6

OVERT# 2 QV1A
Vgs= +-20V
28 OVERT# Vgs(th)=0.5V--1V
G LBSS138DW1T1G_SOT363-6
S @
1

A A

D
1

1
PLT_RST_VGA# 1 @ 2 2 QV2
RV3 G LBSS139WT1G_SC70-3 CV20
0_0402_5% S @ @ 0.1u_0201_10V6K
2
3

1
CV21
@ 0.1u_0201_10V6K
2

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 N17P_(1/6):PEG I/F

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FG541/FG741
Date: Tuesday, March 26, 2019 Sheet 25 of 68
5 4 3 2 1
 5 4 3 2 1

UV1L UV1M
5/17 IFPAB 7/17 IFPEF

DVI HDMI DP

SL/DL

TXC/TXC IFPA_L3 AN6

D
TXC/TXC IFPA_L3 AM6 DVI HDMI DP D
2 @ 1 IFPAB_RSET AJ8 IFPAB_RSET
RV68 1K_0402_1% SL/DL
AN3 CORE_PLLVDD AB4
TXD0/0 IFPA_L2 IFPE_AUX_SDA HDMI1_DAT 39
CORE_PLLVDD AP3 AB3
TXD0/0 IFPA_L2 IFPE_AUX_SCL HDMI1_CLK 39
RV1124 1 @ 2 0_0603_5% +IFPEF_PLLVDD AB8 IFPEF_PLLVDD
RV69 1 2 1/10W_0_+-5%_0603 +IFPAB_PLLVDD AH8 IFPAB_PLLVDD
@ IFPA_L1 AM5 IFPE_L3 AC5 HDMI1_TXC-
TXD1/1 TXC/TXC HDMI1_TXC- 39
AN5 2 1 IFPEF_RSET AD6 AC4 HDMI1_TXC+
1
TXD1/1 IFPA_L1
RV1140 OPT@ 1K_0402_1%
IFPEF_RSET TXC/TXC IFPE_L3 HDMI1_TXC+ 39 HDMI CLK
1

0.1u_0201_10V6K
AC3 HDMI1_TX0-

0.1u_0201_10V6K
CV459 IFPE_L2 HDMI1_TX0- 39
AK6 CV461 TXD0/0 AC2 HDMI1_TX0+
TXD2/2 IFPA_L0 IFPE_L2 HDMI1_TX0+ 39 HDMI D0

@
AL6 TXD0/0

OPT@
2 IFPA_L0
TXD2/2 2 IFPE TXD1/1 IFPE_L1 AC1 HDMI1_TX1-
HDMI1_TX1+ HDMI1_TX1- 39
IFPE_L1 AD1 HDMI D1
TXD1/1 HDMI1_TX1+ 39
IFPA_AUX_SDA AH6
IFPA_AUX_SCL AJ6 IFPE_L0 AD3 HDMI1_TX2-
TXD2/2 HDMI1_TX2+ HDMI1_TX2- 39
IFPE_L0 AD2 HDMI D2
TXD2/2 HDMI1_TX2+ 39

TXC IFPB_L3 AH9

+1.0VGS IFPB_L3 AJ9
TXC
RV72 1 2 0_0603_5% +IFPAB_IOVDD AG8

m
@ IFP_IOVDD
IFPB_L2 AP5
TXD0/3
AG9 AP6
1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

IFP_IOVDD TXD0/3 IFPB_L2

1 1 1 1 1
4.7U_0402_6.3V6M

0.1u_0201_10V6K

0.1u_0201_10V6K

TXD1/4 IFPB_L1 AL7

co
AM7 +1.0VGS
CV445 OPT@

OPT@

OPT@

TXD1/4 IFPB_L1 DVI HDMI DP

2 2 2 2 2
@

SL/DL
OPT@
CV69

CV1175

AM8 RV337 1 2 0_0603_5% +IFPF_IOVDD AC7

CV70

CV71

TXD2/5 IFPB_L0 @ IFP_IOVDD

TXD2/5 IFPB_L0 AN8 IFPF_AUX_SDA AF2
IFPF_AUX_SCL AF3
AC8

s.
IFP_IOVDD
IFPB_AUX_SDA AL8

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201
IFPB_AUX_SCL AK8 1 1 1 1 1 IFPF_L3 AF1

4.7U_0402_6.3V6M
TXC
AG1

0.1u_0201_10V6K

0.1u_0201_10V6K
TXC IFPF_L3
near GPU under GPU

ic
AD5

@
CV460 OPT@

OPT@

OPT@
IFPF_L2
IFPAB 2 2 2 2 2 TXD0/3
IFPF_L2 AD4
IFPF TXD0/3

OPT@
CV463

CV1176
C AF5 C

CV462

CV446
N17P-G1_FCBGA908 TXD1/4 IFPF_L1
INS37070627 TXD1/4 IFPF_L1 AF4

at
?
COMMON TXD2/5 IFPF_L0 AE4
@ IFPF_L0 AE3
TXD2/5

near GPU under GPU

em
UV1N
N17P-G1_FCBGA908
INS37070736
6/17 IFPCD ?
COMMON

ch
@

2 1 IFPCD_RSET AF8 IFPCD_RSET

RV73 EDP_OPT@ 1K_0402_1% UV1K
4/17 NC

kS
AC6 NC
AG10 NC
CORE_PLLVDD AG12
DVI HDMI DP NC
AG26 NC
SL/DL AG7 NC
LV4 1 2 1/10W_0_+-5%_0603 +IFPCD_PLLVDD AF7 IFPCD_PLLVDD IFPC_AUX_SDA AG2 AJ11 NC
EDP_OPT@ AG3 AJ26
oo
IFPC_AUX_SCL NC
1 AJ28 NC
AJ4
0.1u_0201_10V6K

NC
CV222 IFPC_L3 AG4 AJ5 NC
TXC/TXC
EDP_OPT@ IFPC_L3 AG5 AK26 NC
2 TXC/TXC
AK9 NC
IFPC_L2 AH4 AL10 NC
IFPC TXD0/0
IFPC_L2 AH3 AL11 NC
eb

TXD0/0 AL9 NC
IFPC_L1 AJ2 AM9 NC
TXD1/1
IFPC_L1 AJ3 AN2 NC
TXD1/1
AN9 NC
B
IFPC_L0 AJ1 AP8 NC
B
TXD2/2 AK1 C15
IFPC_L0 NC
TXD2/2 D19 NC
ot

D20 NC
D23 NC
D26 NC
V32 NC
IFPD_AUX- RV1259 1 2 100K_0402_5%
+1.0VGS
N

EDP_OPT@
IFPD_AUX+ RV113 1 2 100K_0402_5% N17P-G1_FCBGA908
EDP_OPT@ INS37070514
?
LV5 1 @ 2 0_0603_5% +IFPC_IOVDD AF6 IFP_IOVDD COMMON
DVI HDMI DP
SL/DL @
AG6 IFP_IOVDD IFPD_AUX_SDA AK2
1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

IFPD_AUX- 38
1 1 1 1 1 IFPD_AUX_SCL AK3
4.7U_0402_6.3V6M

IFPD_AUX+ 38
0.1u_0201_10V6K

0.1u_0201_10V6K

AK5
@
CV227 OPT@

OPT@

OPT@

TXC IFPD_L3
2 2 2 2 2 AK4
TXC IFPD_L3
OPT@
CV1177

CV1174

AL4
CV223

CV68

IFPD_L2
IFPD TXD0/3
TXD0/3 IFPD_L2 AL3

IFPD_L1 AM4 IFPD_L1-

TXD1/4 IFPD_L1- 38
TXD1/4 IFPD_L1 AM3 IFPD_L1+
IFPD_L1+ 38
near GPU under GPU IFPD_L0 AM2 IFPD_L0-
TXD2/5 IFPD_L0+ IFPD_L0- 38
IFPD_L0 AM1
TXD2/5 IFPD_L0+ 38

N17P-G1_FCBGA908
INS37070845
A ? A
COMMON
@

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 N17P_(2/6):DIGITAL OUT I/F

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
FG541/FG741 1.0

Date: Tuesday, March 26, 2019 Sheet 26 of 68

5 4 3 2 1
 5 4 3 2 1

MAX:250mA MAX:250mA
30ohms (ESR=0.01) Bead +FB_PLLAVDD
VGA_MAIN_3V_1.8V
P/N;SM010007W00
200mA
+FB_PLLAVDD
GDDR5
1 2
LV7
OPT@ Mode H - Mirror Mode Mapping
HCB1608KF-300T60_2P

DATA Bus
Place close to BGA
UV1C Address 0..31 32..63
INS37072105
? FBx_CMD0 CS#
COMMON
D D
3/17 FBB FBx_CMD1 A3_BA3
UV1B FBx_CMD2 A2_BA0
INS38060350
33,34 FBC_D[0..63]
?
FBC_D0
FBx_CMD3 A4_BA2
COMMON G9 FBB_D0
FBC_D1 E9
2/17 FBA
FBC_D2
FBB_D1 FBx_CMD4 A5_BA1
G8 FBB_D2
FBC_D3 F9
FBC_D4
FBB_D3 FBx_CMD5 WE#
F11 FBB_D4
31,32 FBA_D[0..63] FBC_D5 G11
FBA_D0 FBC_D6
FBB_D5 FBx_CMD6 A7_A8
L28 FBA_D0 F12 FBB_D6
FBA_D1 M29 FBC_D7 G12
FBA_D2
FBA_D1
FBC_D8
FBB_D7 FBx_CMD7 A6_A11
L29 FBA_D2 +FB_PLLAVDD G6 FBB_D8
FBA_D3 M28 FBC_D9 F5
FBA_D4
FBA_D3
FBC_D10
FBB_D9 FBx_CMD8 ABI#
N31 FBA_D4 E6 FBB_D10
FBA_D5 P29 K27 FB_REFPLL_AVDD_GPU 1 2 0_0603_5% FBC_D11 F6
FBA_D6
FBA_D5 FB_REFPLL_AVDD RV301 @
FBC_D12
FBB_D11 FBx_CMD9 A12_RFU
R29 FBA_D6 F4 FBB_D12
FBA_D7 P28 FBC_D13 G4
FBA_D8
FBA_D7
FBC_D14
FBB_D13 FBx_CMD10 A0_A10
J28 E2

0.1U_6.3V_K_X5R_0201
FBA_D9
FBA_D8 1 FBC_D15
FBB_D14
H29 FBA_D9 F3 FBB_D15 FBx_CMD11 A1_A9
FBA_D10 J29 FBC_D16 C2
FBA_D10 FBB_D16
FBA_D11 H28 FBC_D17 D4
FBA_D12
FBA_D11
2 FBC_D18
FBB_D17 FBx_CMD12 RAS#
G29 D3

OPT@
FBA_D12 FBB_D18
FBA_D13 E31 FBC_D19 C1 FBx_CMD13 RST#

CV172
FBA_D13 FBB_D19
FBA_D14 E32 FBC_D20 B3
FBA_D14 FBB_D20
FBA_D15 F30 FBC_D21 C4
FBA_D16
FBA_D15
FBC_D22
FBB_D21 FBx_CMD14 CKE#
C34 FBA_D16 B5 FBB_D22
FBA_D17 D32 FBC_D23 C5
FBA_D18
FBA_D17 Under GPU
FBC_D24
FBB_D23 FBx_CMD15 CAS#
B33 FBA_D18 A11 FBB_D24
FBA_D19 C33 FBC_D25 C11
FBA_D20
FBA_D19
FBC_D26
FBB_D25 FBx_CMD16 CS#
F33 FBA_D20 D11 FBB_D26
FBA_D21 F32 FBC_D27 B11
FBA_D22
FBA_D21
FBC_D28
FBB_D27 FBx_CMD17 A3_BA3
H33 FBA_D22 D8 FBB_D28
FBA_D23 H32 FBC_D29 A8
FBA_D23 FBB_D29 FBx_CMD18 A2_BA0

m
FBA_D24 P34 FBC_D30 C8
FBA_D24 FBB_D30
FBA_D25 P32 FBC_D31 B8
FBA_D26
FBA_D25
FBC_D32
FBB_D31 FBx_CMD19 A4_BA2
P31 FBA_D26 F24 FBB_D32
FBA_D27 P33 FBC_D33 G23 D13 FBC_CS#_L
FBA_D28
FBA_D27
FBC_D34
FBB_D33 FBB_CMD0
FBC_MA3_BA3_L FBC_CS#_L 33 FBx_CMD20 A5_BA1
C L31 FBA_D28 E24 FBB_D34 FBB_CMD1 E14 C
FBA_D29 L34 FBC_D35 G24 F14 FBC_MA2_BA0_L FBC_MA3_BA3_L 33
FBA_D30
FBA_D29
FBC_D36
FBB_D35 FBB_CMD2
FBC_MA4_BA2_L FBC_MA2_BA0_L 33 FBx_CMD21 WE#
L32 FBA_D30 D21 FBB_D36 FBB_CMD3 A12

co
FBA_D31 L33 FBC_D37 E21 B12 FBC_MA5_BA1_L FBC_MA4_BA2_L 33
FBA_D32
FBA_D31
FBC_D38
FBB_D37 FBB_CMD4
FBC_WE#_L FBC_MA5_BA1_L 33 FBx_CMD22 A7_A8
AG28 FBA_D32 G21 FBB_D38 FBB_CMD5 C14
FBA_D33 AF29 U30 FBA_CS#_L FBC_D39 F21 B14 FBC_MA7_MA8_L FBC_WE#_L 33
FBA_D34
FBA_D33 FBA_CMD0 FBA_CS#_L 31 FBB_D39 FBB_CMD6 FBC_MA7_MA8_L 33 FBx_CMD23 A6_A11
AG29 FBA_D34 FBA_CMD1 T31 FBA_MA3_BA3_L FBC_D40 G27 FBB_D40 FBB_CMD7 G15 FBC_MA6_MA11_L
FBA_D35 FBA_MA3_BA3_L 31 FBC_MA6_MA11_L 33
AF28 FBA_D35 FBA_CMD2 U29 FBA_MA2_BA0_L FBC_D41 D27 FBB_D41 FBB_CMD8 F15 FBC_ABI#_L
FBx_CMD24 ABI#
FBA_D36 AD30 R34 FBA_MA4_BA2_L FBA_MA2_BA0_L 31 FBC_D42 G26 E15 FBC_MA12_RFU_L FBC_ABI#_L 33
FBA_D36 FBA_CMD3 FBA_MA4_BA2_L 31 FBB_D42 FBB_CMD9 FBC_MA12_RFU_L 33
FBA_D37 AD29 R33 FBA_MA5_BA1_L FBC_D43 E27 D15 FBC_MA0_MA10_L
FBA_D38
FBA_D37 FBA_CMD4 FBA_MA5_BA1_L 31 FBC_D44
FBB_D43 FBB_CMD10
FBC_MA1_MA9_L FBC_MA0_MA10_L 33 FBx_CMD25 A12_RFU
AC29 FBA_D38 FBA_CMD5 U32 FBA_WE#_L E29 FBB_D44 FBB_CMD11 A14
FBA_D39 AD28 U33 FBA_MA7_MA8_L FBA_WE#_L 31 FBC_D45 F29 D14 FBC_RAS#_L FBC_MA1_MA9_L 33
FBx_CMD26 A0_A10

s.
FBA_D39 FBA_CMD6 FBA_MA7_MA8_L 31 FBB_D45 FBB_CMD12 FBC_RAS#_L 33
FBA_D40 AJ29 U28 FBA_MA6_MA11_L FBC_D46 E30 A15 FBC_RST#_L
FBA_D40 FBA_CMD7 FBA_MA6_MA11_L 31 FBB_D46 FBB_CMD13 FBC_RST#_L 33
FBA_D41 AK29 V28 FBA_ABI#_L FBC_D47 D30 B15 FBC_CKE_L
FBA_D42
FBA_D41 FBA_CMD8
FBA_MA12_RFU_L FBA_ABI#_L 31 FBC_D48
FBB_D47 FBB_CMD14
FBC_CAS#_L FBC_CKE_L 33 FBx_CMD27 A1_A9
AJ30 FBA_D42 FBA_CMD9 V29 A32 FBB_D48 FBB_CMD15 C17
FBA_D43 AK28 V30 FBA_MA0_MA10_L FBA_MA12_RFU_L 31 FBC_D49 C31 D18 FBC_CS#_H FBC_CAS#_L 33
FBA_D44
FBA_D43 FBA_CMD10 FBA_MA0_MA10_L 31 FBB_D49 FBB_CMD16 FBC_CS#_H 34 FBx_CMD28 RAS#
AM29 FBA_D44 FBA_CMD11 U34 FBA_MA1_MA9_L FBC_D50 C32 FBB_D50 FBB_CMD17 E18 FBC_MA3_BA3_H
FBA_MA1_MA9_L 31 FBC_MA3_BA3_H 34

ic
FBA_D45 AM31 U31 FBA_RAS#_L FBC_D51 B32 F18 FBC_MA2_BA0_H
FBA_D46
FBA_D45 FBA_CMD12 FBA_RAS#_L 31 FBB_D51 FBB_CMD18 FBC_MA2_BA0_H 34 FBx_CMD29 RST#
AN29 FBA_D46 FBA_CMD13 V34 FBA_RST#_L FBC_D52 D29 FBB_D52 FBB_CMD19 A20 FBC_MA4_BA2_H
FBA_D47 AM30 V33 FBA_CKE_L FBA_RST#_L 31 FBC_D53 A29 B20 FBC_MA5_BA1_H FBC_MA4_BA2_H 34
FBA_D48
FBA_D47 FBA_CMD14 FBA_CKE_L 31 FBB_D53 FBB_CMD20 FBC_MA5_BA1_H 34 FBx_CMD30 CKE#
AN31 FBA_D48 FBA_CMD15 Y32 FBA_CAS#_L FBC_D54 C29 FBB_D54 FBB_CMD21 C18 FBC_WE#_H
FBA_D49 AN32 AA31 FBA_CS#_H FBA_CAS#_L 31 FBC_D55 B29 B18 FBC_MA7_MA8_H FBC_WE#_H 34
FBA_D50
FBA_D49 FBA_CMD16 FBA_CS#_H 32 FBB_D55 FBB_CMD22 FBC_MA7_MA8_H 34 FBx_CMD31 CAS#
AP30 FBA_D50 FBA_CMD17 AA29 FBA_MA3_BA3_H FBC_D56 B21 FBB_D56 FBB_CMD23 G18 FBC_MA6_MA11_H
FBA_D51 AA28 FBA_MA2_BA0_H FBA_MA3_BA3_H 32 FBC_D57 FBC_ABI#_H FBC_MA6_MA11_H 34

at
AP32 FBA_D51 FBA_CMD18 C23 FBB_D57 FBB_CMD24 G17
FBA_D52 AM33 AC34 FBA_MA4_BA2_H FBA_MA2_BA0_H 32 FBC_D58 A21 F17 FBC_MA12_RFU_H FBC_ABI#_H 34
FBA_D52 FBA_CMD19 FBA_MA4_BA2_H 32 FBB_D58 FBB_CMD25 FBC_MA12_RFU_H 34
FBA_D53 AL31 AC33 FBA_MA5_BA1_H FBC_D59 C21 D16 FBC_MA0_MA10_H
FBA_D53 FBA_CMD20 FBA_MA5_BA1_H 32 FBB_D59 FBB_CMD26 FBC_MA0_MA10_H 34
FBA_D54 AK33 AA32 FBA_WE#_H FBC_D60 B24 A18 FBC_MA1_MA9_H
FBA_D54 FBA_CMD21 FBA_WE#_H 32 FBB_D60 FBB_CMD27 FBC_MA1_MA9_H 34
FBA_D55 AK32 AA33 FBA_MA7_MA8_H FBC_D61 C24 D17 FBC_RAS#_H
FBA_D55 FBA_CMD22 FBA_MA7_MA8_H 32 FBB_D61 FBB_CMD28 FBC_RAS#_H 34
FBA_D56 AD34 Y28 FBA_MA6_MA11_H FBC_D62 B26 A17 FBC_RST#_H
FBA_D56 FBA_CMD23 FBA_MA6_MA11_H 32 FBB_D62 FBB_CMD29 FBC_RST#_H 34
FBA_D57 AD32 Y29 FBA_ABI#_H FBC_D63 C26 B17 FBC_CKE_H
FBA_D57 FBA_CMD24 FBA_ABI#_H 32 FBB_D63 FBB_CMD30 FBC_CKE_H 34
FBA_D58 AC30 W31 FBA_MA12_RFU_H E17 FBC_CAS#_H

em
FBA_D58 FBA_CMD25 FBA_MA12_RFU_H 32 FBB_CMD31 FBC_CAS#_H 34
FBA_D59 AD33 Y30 FBA_MA0_MA10_H G14
FBA_D59 FBA_CMD26 FBA_MA0_MA10_H 32 FBB_CMD32
FBA_D60 AF31 AA34 FBA_MA1_MA9_H FBC_DBI0# E11 G20
FBA_D60 FBA_CMD27 FBA_MA1_MA9_H 32 33 FBC_DBI0# FBB_DQM0 FBB_CMD33
FBA_D61 AG34 Y31 FBA_RAS#_H FBC_DBI1# E3 C12 FBB_DEBUG0 1 @ 2 1.55V
FBA_D61 FBA_CMD28 FBA_RAS#_H 32 FBB_DQM1 FBB_CMD34 +1.35VGS
FBA_D62 AG32 Y34 FBA_RST#_H 33 FBC_DBI1# FBC_DBI2# A3 C20 RV121
FBA_D62 FBA_CMD29 FBA_RST#_H 32 FBB_DQM2 FBB_CMD35
FBA_D63 AG33 Y33 FBA_CKE_H 33 FBC_DBI2# FBC_DBI3# C9 60.4_0402_1%
FBA_D63 FBA_CMD30 FBA_CKE_H 32 FBB_DQM3
V31 FBA_CAS#_H 33 FBC_DBI3# FBC_DBI4# F23
FBA_CMD31 FBA_CAS#_H 32 FBB_DQM4
R28 34 FBC_DBI4# FBC_DBI5# F27 FBB_DEBUG1 1 @ 2
FBA_CMD32 34 FBC_DBI5# FBB_DQM5
FBA_DBI0# P30 AC28 FBC_DBI6# C30 RV122
FBA_DQM0 FBA_CMD33 FBB_DQM6
31 FBA_DBI0# FBA_DBI1# F31 R32 FBA_DEBUG0 1 2 34 FBC_DBI6# FBC_DBI7# A24
B 31 FBA_DBI1# FBA_DQM1 FBA_CMD34 @
+1.35VGS 1.55V 34 FBC_DBI7# FBB_DQM7 60.4_0402_1%
B
FBA_DBI2# F34 AC32 RV119
FBA_DQM2 FBA_CMD35
31 FBA_DBI2# FBA_DBI3# M32 60.4_0402_1%
FBA_DQM3

ch
31 FBA_DBI3# FBA_DBI4# AD31 FBC_EDC0 D10
32 FBA_DBI4# FBA_DQM4 33 FBC_EDC0 FBB_DQS_WP0
FBA_DBI5# AL29 FBA_DEBUG1 1 @ 2 FBC_EDC1 D5
FBA_DQM5 FBB_DQS_WP1
32 FBA_DBI5# FBA_DBI6# AM32 RV120 33 FBC_EDC1 FBC_EDC2 C3 D12 FBC_CLK0
FBA_DQM6 FBB_DQS_WP2 FBB_CLK0
32 FBA_DBI6# FBA_DBI7# AF34 60.4_0402_1% 33 FBC_EDC2 FBC_EDC3 B9 E12 FBC_CLK0# FBC_CLK0 33
FBA_DQM7 FBB_DQS_WP3 FBB_CLK0
32 FBA_DBI7# 33 FBC_EDC3 FBC_EDC4 E23 E20 FBC_CLK1 FBC_CLK0# 33
FBB_DQS_WP4 FBB_CLK1
34 FBC_EDC4 FBC_EDC5 E28 F20 FBC_CLK1# FBC_CLK1 34
34 FBC_EDC5 FBB_DQS_WP5 FBB_CLK1 FBC_CLK1# 34
FBA_EDC0 M31 FBC_EDC6 B30 +1.35VGS
FBA_DQS_WP0 FBB_DQS_WP6
31 FBA_EDC0 FBA_EDC1 G31 34 FBC_EDC6 FBC_EDC7 A23
FBA_DQS_WP1 FBB_DQS_WP7
31 FBA_EDC1 FBA_EDC2 E33 R30 FBA_CLK0 +1.35VGS 34 FBC_EDC7

kS
FBA_DQS_WP2 FBA_CLK0
31 FBA_EDC2 FBA_EDC3 M33 R31 FBA_CLK0# FBA_CLK0 31
FBA_DQS_WP3 FBA_CLK0
31 FBA_EDC3 FBA_EDC4 AB31 FBA_CLK1 FBA_CLK0# 31 FBC_WCK0

1
AE31 FBA_DQS_WP4 FBA_CLK1 D9 FBB_DQS_RN0 FBB_WCK01 F8
32 FBA_EDC4 FBA_EDC5 AK30 AC31 FBA_CLK1# FBA_CLK1 32 E4 E8 FBC_WCK0_N FBC_WCK0 33 RV309 RV308
FBA_DQS_WP5 FBA_CLK1 FBB_DQS_RN1 FBB_WCK01
32 FBA_EDC5 FBA_EDC6 FBA_CLK1# 32 FBC_WCK1 FBC_WCK0_N 33

1
AN33 FBA_DQS_WP6 B2 FBB_DQS_RN2 FBB_WCK23 A5 10K_0402_5% 10K_0402_5%
32 FBA_EDC6 FBA_EDC7 AF33 RV306 RV307 A9 A6 FBC_WCK1_N FBC_WCK1 33 OPT@ OPT@
FBA_DQS_WP7 FBB_DQS_RN3 FBB_WCK23
32 FBA_EDC7 OPT@ 10K_0402_5% OPT@ 10K_0402_5% D22 D24 FBC_WCK2 FBC_WCK1_N 33
FBB_DQS_RN4 FBB_WCK45
FBC_WCK2 34

2
D28 D25 FBC_WCK2_N FBC_CKE_L
FBB_DQS_RN5 FBB_WCK45 FBC_WCK2_N 34
M30 FBA_DQS_RN0 FBA_WCK01 K31 FBA_WCK0 A30 FBB_DQS_RN6 FBB_WCK67 B27 FBC_WCK3 FBC_CKE_H
FBA_WCK0 31 FBC_WCK3 34

2
H30 L30 FBA_WCK0_N FBA_CKE_L B23 C27 FBC_WCK3_N
E34
FBA_DQS_RN1 FBA_WCK01
H34 FBA_WCK1 FBA_WCK0_N 31
oo FBA_CKE_H
FBB_DQS_RN7 FBB_WCK67
FBC_WCK3_N 34 FBC_RST#_L
FBA_DQS_RN2 FBA_WCK23
M34 J34 FBA_WCK1_N FBA_WCK1 31 D6 FBC_RST#_H
FBA_DQS_RN3 FBA_WCK23 FBB_WCKB01
AF30 AG30 FBA_WCK2 FBA_WCK1_N 31 FBA_RST#_L D7
FBA_DQS_RN4 FBA_WCK45 FBA_WCK2 32 FBB_WCKB01
AK31 FBA_DQS_RN5 FBA_WCK45 AG31 FBA_WCK2_N FBA_RST#_H
FBB_WCKB23 C6
AJ34 FBA_WCK3 FBA_WCK2_N 32

1
AM34 FBA_DQS_RN6 FBA_WCK67 FBB_WCKB23 B6
AF32 AK34 FBA_WCK3_N FBA_WCK3 32 F26 RV125 RV126
FBA_DQS_RN7 FBA_WCK67 FBB_WCKB45
FBA_WCK3_N 32 E26 10K_0402_5% 10K_0402_5%
FBB_WCKB45
1

1
FBA_WCKB01 J30 FBB_WCKB67 A26 OPT@ OPT@
J31 RV123 RV124 A27
eb

FBA_WCKB01 FBB_WCKB67

2
FBA_WCKB23 J32 10K_0402_5% 10K_0402_5%
J33 OPT@ OPT@ H17 FB_PLL_AVDD
FBA_WCKB23 FBB_PLL_AVDD
FBA_WCKB45 AH31
2

2
AJ31

0.1U_6.3V_K_X5R_0201
FBA_WCKB45 1
FBA_WCKB67 AJ32 N17P-G1_FCBGA908
FBA_WCKB67 AJ33 +FB_PLLAVDD @
H31 U27 FB_PLL_AVDD 1 2 0_0603_5% 2

OPT@
FB_VREF FBA_PLL_AVDD RV305 @

CV176
ot
22U_0603_6.3V6-M
0.1U_6.3V_K_X5R_0201

1 1 1
A N17P-G1_FCBGA908 A
1U_0201_6.3V6K

@
@

OPT@

2 2 2
OPT@

CV175
CV173

CV174

Under GPU
N

Under GPU Near GPU

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 N17P_(3/6):VRAM I/F

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FG541/FG741
Date: Tuesday, March 26, 2019 Sheet 27 of 68
5 4 3 2 1
 5 4 3 2 1

+1.8VS_AON
+1.8VS_AON

2
UV1P
INS37075787 RV130 GPU FB Memory (GDDR5) RAMCFG[4:0] STRAP2 STRAP1 STRAP0

2
? 0_0402_5%
COMMON OPT@ RV187 RV188 RV189
12/17 MISC2 100K_0402_5% 100K_0402_5% 100K_0402_5% Samsung 8Gb K4G80325FB-HC28 0(0x0000) L/RV194 L/RV193 L/RV192

1
@ @ @

1
Micron 8Gb MT51J256M32HF-70:B 4(0x0004) H/RV189 L/RV193 L/RV192
ROM_CS H6 PAD 1 ROM_SO ROM_SI ROM_SCLK SOR_EXPOSED[3:0] 1:ENABLE 0:DISABLE STRAP2
TC1

2
ROM_SI
@ N17P-G0-K1 Hynix 8Gb H5GC8H24AJR-R0C 5(0x0005) H/RV189 L/RV193 H/RV187
ROM_SI H5 RV197 RV198 RV199 STRAP1
H7 ROM_SO
ROM_SO
ROM_SCLK
100K_0402_5% 100K_0402_5% 100K_0402_5% H H H 1000 SOR0/1/2 DISABLE
STRAP0 J2 H4 OPT@ OPT@ OPT@ STRAP0 Micron 8Gb MT51J256M32HF-80 :B 4(0x0004) H/RV189 L/RV193 L/RV192
STRAP1 J7
STRAP0 ROM_SCLK SOR3 ENABLE
STRAP1

1
D STRAP2 J6 STRAP2 D

2
STRAP3 J5 STRAP3
STRAP4 J3 STRAP4
ROM_SO RV192 RV193 RV194
1 @ MULTI_STRAP
2 0_0402_5% J1
STRAP5 STRAP5 100K_0402_5% 100K_0402_5% 100K_0402_5%
ROM_SI @ @ @
RV17
1

1
RV16 ROM_SCLK
40.2K_0402_1% BUFRST E1
@

1
2

2
RV203
@ 10K_0402_5% RV200 RV201 RV202
100K_0402_5% 100K_0402_5% 100K_0402_5%
@ @ @

1
N17P-G1_FCBGA908
@ E1 is FB_CLAMP of N16P +1.8VS_AON

STRAP5 STRAP4 STRAP3 SMB_ALT_ADDR DEVID_SEL PCIE_CFG VGA_DEVICE

2
+3VS
RV19 RV21 RV74 L L H 0 0 0 1
100K_0402_5% 100K_0402_5% 100K_0402_5%
OPT@ @ @

2
+3VALW RV12
@

1
10K_0402_5% RV51 1 2 0_0402_5% 1: SMB_ALT_ADDR ENABLE
PCH_FB_GC6_EN 19

m
OPT@ STRAP5
0: SMB_ALT_ADDR DISABLE

2
RV57 STRAP4

1
10K_0402_5%
FB_GC6_EN_R
OPT@ STRAP3 1: DEVID_SEL REBRAND
0: DEVID_SEL ORIGNAL

1
D

co
2

2
5 QV7B
G LBSS138DW 1T1G_SOT363-6 RV78 RV75 RV77 1: PCIE_CFG LOW POWER
S OPT@ 100K_0402_5% 100K_0402_5% 100K_0402_5%

4
@ OPT@ OPT@ 0: PCIE_CFG HIGH POWER

1
D

6
FB_GC6_EN 2 QV7A 1: VGA_DEVICE ENABLE
G LBSS138DW 1T1G_SOT363-6

s.
S OPT@ 0: VGA_DEVICE DISABLE

1
1
C C
RV313
10K_0402_5%
OPT@
+1.8VS_AON PLT_RST_VGA#

ic
PLT_RST_VGA#
RV55 1 @ 2 0_0402_5% VGA_MAIN_3V_1.8V +3VS
1

+1.8VS_AON +3VS
Add RV13 for VGA_MAIN_3V_1.8V and change RV88 from stuff to ns
2

RV1137 RV1136
RV1139
+1.8VS_AON
HLZ SIT 0922 BAT54AW
1K_0402_5% 1K_0402_5%

at
VF=0.32V @ IF=1mA
2

1
@ 0_0402_5% @ @

2
RV1138 RV13 RV334
Reserve RV333 & DV9 & RV334 & RV335 for DG new sequence
2

0_0402_5% 0_0402_5% 10K_0402_1% RV104

@
Hai Y520 SVT
1

@ 10K_0402_5%
DV9 OPT@
1

2
2
1

1
RPV1 PXS_PWREN RV220 1 2 0_0402_5% 3
19,29 PXS_PWREN 1 DV3

em
2.2K_0404_4P2R_5% NVVDD_EN 29,68
OPT@ 1V8_MAIN_EN_R 2 RV49 2 @ 1 0_0402_5% 2
67 VDDQPW ROK 1
+1.8VS_AON
5

VGA_PWRGD 20,25
3
4

1
+1.8VS_AON +3VS BAT54AW _SOT323-3 RV64 2 @ 1 0_0402_5% 3
67 1.0VGS_PG
G2

RV335
VGA_SMB_CK2 100K_0402_1%

2
4 3 BAT54AW _SOT323-3
S2 D2 EC_SMB_CK2 16,44,49 @
RV59
1
RV333 1 @ 2 0_0402_5% OPT@

2
RV319 @ 0_0402_5%
QV3B

1
PJT7838_SOT363-6 10K_0402_5%
OPT@ RV320

1
OPT@
10K_0402_5% Add DV3 for VGA_PWRGD
2
2

ch
OPT@
ADD PXS_PWREN for NVVDDS & 1V0_MAIN_EN Power down HLZ SIT 0922

2
+1.8VS_AON +3VS
G1

2
VGA_SMB_DA2 1 6
HLZ SIV 0725
S1 D1 EC_SMB_DA2 16,44,49 GPU_EVENT# @
3 1GPU_EVENT#_R RV318 1 2 0_0402_5% DV8
PCH_GPU_EVENT# 19
PXS_PWREN

1
QV3A For Optimus Power OFF 1 2

2
PJT7838_SOT363-6 PU AT EC SIDE, +3VS AND 4.7K QV8 RV331
OPT@ LSI1012XT1G_SC-89-3 RB751V-40_SOD323-2 RV89 8.2K_0402_1%
OPT@ OPT@ @ 10K_0402_5% OPT@ Use RV331 & RV330 and unstuff RV89 based on NV suggestion

kS
@
HLZ SIV 0811

2
RV317 1 @ 2 0_0402_5% 1V8_MAIN_EN_R RV1135 1 2 0_0402_5%
DV7

1
For GC6 Power OFF 1V8_MAIN_EN RV1134 1 @ 2 0_0402_5%2
1 RV98 2 @ 1 0_0402_5%
NVVDD_PW RGD 3 1V0_MAIN_EN 30,67
For Power ON 68 NVVDD_PW RGD

1
+3VS
+1.8VS_AON BAT54AW _SOT323-3 RV330
B
oo OPT@ 10K_0402_1% B
@

2
+3VALW
Delete RV40 & RV97 0ohm & RV54 (ns) Delete RV96(ns) RV1129
10K_0402_5%
NVVDDS_VID RV336 2 @ 1 10K_0402_5% HLZ SIV 0725 HLZ SIT 0922 OPT@

2
+1.8VS_AON RV1132

1
10K_0402_5%
1V8_MAIN_EN RV27 2 OPT@ 1 10K_0402_5% OPT@ 1V8_MAIN_EN_R
UV1Q 1V8_MAIN_EN_R 29
eb

INS37074849
? Delete FRM_LCK#

1
D

3
COMMON DV4
FB_GC6_EN_R @
2

10/17 MISC1 RV110 1 2 0_0402_5% 2 5 QV32B

RV214 NVVDD_PSI RV28 1 @ 2 10K_0402_5% G LBSS138DW 1T1G_SOT363-6
100K_0402_5% 1 S OPT@
FBVDDQ_PW R_EN 30,67

4
OPT@
I2CS_SCL T4 VGA_SMB_CK2 +1.8VS_AON VGA_ALERT# RV23 1 OPT@ 2 10K_0402_5% 1.0VGS_PG RV325 1 @ 2 0_0402_5% 3
1

VGA_SMB_DA2 D

6
I2CS_SDA T3 Internal Thermal Sensor VGA_AC_DET_R RV26 1 OPT@ 2 100K_0402_5% 1V8_MAIN_EN 2 QV32A
VGA_EDID_CLK

1
OVERT# M1 R2 RV212 1 2 2.2K_0402_5% OPT@ BAT54CW _SOT323-3 LBSS138DW 1T1G_SOT363-6
ot

25 OVERT# OVERT I2CC_SCL G

R3 VGA_EDID_DATA RV210 1 2 2.2K_0402_5% OPT@ RV112 OPT@
I2CC_SDA
Change signal from NVVDDS_PWRGD to 1.0VGS_PG OPT@ S

1
1
TV5 @ 1 AP9 TS_VREF 200K_0402_5%
I2CB_SCL R7 I2CB_SCL
I2CB_SDA
RV22 1 2 2.2K_0402_5% OPT@
SYS_PEX_RST_MON#
HLZ SIT 0922 OPT@ RV1133
K4 THERMDN I2CB_SDA R6 RV25 1 2 2.2K_0402_5% OPT@ RV39 1 @ 2 10K_0402_5% 10K_0402_5% @

2
K3 THERMDP

2
GPU_PEX_RST_HOLD# RV18 1 @ 2 10K_0402_5% NVVDD_PW RGD RV1123 1 2 14.7K_0402_1%
P6 NVVDD_VID OPT@
N

GPIO0 NVVDD_VID 68
TV1 @ 1 AM10 JTAG_TCK GPIO1 M3 FB_GC6_EN
TV2 @ 1 AP11 L6 GPU_EVENT# 1
JTAG_TMS GPIO2
NVVDDS_VID
NVVDD & NVVDDS merge
TV3 @ 1 AM11 P5
TV4 @ 1 AP12
JTAG_TDI GPIO3
P7 1V8_MAIN_EN NVVDDS_VID PU to 1V8_AON only 0831SF CV458
JTAG_TDO GPIO4 .1U_0402_10V6-K
AN11 JTAG_TRST GPIO5 L7 MEM_VREF RV32 2 OPT@ 1 100K_0402_5% 2
AK11 M7 NVVDD_PSI_GPU 2 1 0_0402_5% GPU_FRAME_LOCK# 38 OPT@
NVJTAG_SEL GPIO6 RV107 @
NVVDD_PSI 68
Combine NVVDD_PSI&NVVDDS_PSI
2

RV37
GPIO7 N8
L3 VRAM_VDDQ_ADJ GPU_EDP_PW M 38 @DG-07875-001 V04 Delete 3D VISION
GPIO8 VRAM_VDDQ_ADJ 67
10K_0402_5% GPIO9 M2 VGA_ALERT# VGA_MAIN_3V_1.8V +1.8VS_AON
MEM_VREF
2

OPT@ GPIO10 L1
MEM_VREF 31,33
RV24 GPIO11 M5
GPU_EDP_ENVDD 38
1

10K_0402_5% GPIO12 N3 VGA_AC_DET_R +3VS

OPT@ GPIO13 M4 +3VS
GPU_EDP_ENBKL 38
GPIO14 N4 +1.8VS_AON
@
1

2
GPIO15 P2 RV322 RV38 1 2 0_0402_5%
GPIO16 R8 SYS_PEX_RST_MON#_R 1 @ 2 SYS_PEX_RST_MON# RV52 RV50
1
GPIO17 M6 0_0402_5% IFPD_HPD 10K_0402_5% @ OPT@ 10K_0402_5%
IFPE_HPD IFPD_HPD 38 VRAM_VDDQ_ADJ

2
GPIO18 R1 RV41 2 @ 1 10K_0402_5% CV58
P3 IFPE_HPD 39 .1U_0402_10V6-K DV2
GPIO19 RV216

1
P4 GC5_MODE 1 @ TV7 10K_0402_5% 2 OPT@ GPU_PEX_RST_HOLD# 2
GPIO20
GPIO21 P1 RV43 2 OPT@ 1 10K_0402_5% @ 1 PLT_RST_VGA#
P8 SYS_PEX_RST_MON# 3 PLT_RST_VGA# 25
GPIO22 RV321

1
A T8 GPU_PEX_RST_HOLD#_R 1 @ 2 GPU_PEX_RST_HOLD# A
GPIO23

1
GPIO24 L2 0_0402_5% UV2
R4 PLT_RST# 1 BAT54AW _SOT323-3 RV311
GPIO25 18,37,41,42,45,49 PLT_RST#

P
R5 B 4 SYS_PEX_RST_MON# @ @ 100K_0402_5%
GPIO26 Y
GPIO27 U3 2
19 PXS_RST# A

G
@

2
N17P-G1_FCBGA908 MC74VHC1G09DFT2G_SC70-5 RV44 1 2 0_0402_5%
VGA_ALERT# 20

3
@ GPIO24 is N16 BUFRST# OPT@

1
GPIO25 is N16 CRT SCL

1
GPIO26 is N16 CRT SDA VGA_ALERT#
RV217 RV324
2 1 100K_0402_5% 100K_0402_5%
DV6 RB751V-40_SOD323-2 OPT@ OPT@

2
OPT@

2
VGA_AC_DET_R 2 1
VGA_AC_DET 49
DV1 RB751V-40_SOD323-2 Title
@
Security Classification LC Future Center Secret Data
Issued Date 2015/08/20 Deciphered Date 2016/08/20 N17P_(4/6):GPIO
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
D 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FG541/FG741
Date: Tuesday, March 26, 2019 Sheet 28 of 68
5 4 3 2 1
 5 4 3 2 1

5A Peak 8A UV1E UV1F

+1.35VGS
INS37078337 INS37078176 1.8V Total 1A (AON+MAIN)
? ?
0.5A
UV1G
COMMON COMMON INS37077573
14/17 FBVDDQ 17/17 VDD18/AON ?
NVVDD
Under GPU(below 150mils) +1.8VS_AON COMMON
AA27 FBVDDQ Under GPU Near GPU 8/17 VDDS
1 1 1 1 1 1 1 1 1 1 1 1 AA30 FBVDDQ
+VDD_AON @
AB27 FBVDDQ 1V8_AON J8 RV65 2 1 0_0603_5% AA12 VDDS
1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K
AB33 FBVDDQ 1V8_AON K8 AA16 VDDS
AC27 AA19
@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
FBVDDQ 1 1 1 1 VDDS

4.7U_0402_6.3V6M
0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201
2 2 2 2 2 2 2 2 2 2 2 2 AD27 L8 AA23
FBVDDQ VDD18 VDDS

1U_0201_6.3V6K
AE27 FBVDDQ VDD18 M8 AC14 VDDS
AF27 AC21

OPT@

OPT@

OPT@

CV118 OPT@
FBVDDQ VDDS
CV114

CV103

CV104

CV105

CV106

CV115

CV112

CV113

CV99

CV100

CV101

CV102
AG27 2 2 2 2 M14
FBVDDQ VDDS
B13 M21

CV116

CV443
D FBVDDQ VDDS D
B16 FBVDDQ P12 VDDS

CV117
B19 FBVDDQ P16 VDDS
Cost down list: +1.35VGS E13 FBVDDQ P19 VDDS
1U 3Pcs E16 P23
Under GPU(below 150mils) E19
H10
FBVDDQ
FBVDDQ 0.5A T14
T21
VDDS
VDDS
FBVDDQ VDDS

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

H11 VGA_MAIN_3V_1.8V U17
2 2 2 2 FBVDDQ VDDS
H12 FBVDDQ V18 VDDS
H13 FBVDDQ N17P-G1_FCBGA908 W14 VDDS
H14 +VDD_MAIN RV53 2 @ 1 0_0603_5% W21

CV87 OPT@

CV88 OPT@
CV86 CD@
FBVDDQ @ VDDS
1 1 1 1 H15 FBVDDQ
H16 FBVDDQ 1 1 1 1

4.7U_0402_6.3V6M
0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201
H18

CV94
FBVDDQ

1U_0201_6.3V6K
H19 FBVDDQ VDDS_SENSE U1 1 IT34 PAD
@
H20

OPT@

OPT@

OPT@

CV122 OPT@
FBVDDQ
H21 FBVDDQ
2 2 2 2
GNDS_SENSE U2 1 IT35 PAD
@
H22

CV119

CV120
FBVDDQ
H23 FBVDDQ

CV121
+1.35VGS H24 N17P-G1_FCBGA908
FBVDDQ
Near GPU H8
H9
FBVDDQ
FBVDDQ Under GPU Near GPU NVVDD
@ & NVVDDS merge
L27
test point only 0831SF

m
Near GPU FBVDDQ
M27 FBVDDQ
10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
2 2 1 1 1 1 1 N27 FBVDDQ
P27
33P_0402_50V8J

33P_0402_50V8J

1 1 FBVDDQ
R27 FBVDDQ
trace width: 16mils
T27
CALIBRATION PIN GDDR5
@
CV95 OPT@

CV89 OPT@

FBVDDQ

co
OPT@

OPT@

OPT@
1 1 2 2 2 2 2 T30 differential voltage sensing.

OPT@
RF_NS@

RF_NS@

FBVDDQ
CV90

CV91

CV97

CV92

CV93
2 2 T33 FBVDDQ
19A Peak 42A Cost down list: differential signal routing.
V27
FB_CAL_x_PD_VDDQ 40.2Ohm
CD89

CD90

FBVDDQ
W27 FBVDDQ 4.7U 1Pcs
W30 FBVDDQ
NVVDD
1U 1Pcs
W33
Y27
FBVDDQ FB_CAL_x_PU_GND 40.2Ohm

s.
FBVDDQ
Near GPU
FB_CAL_xTERM_GND 60.4Ohm

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
10U_0603_6.3V6M

10U_0603_6.3V6M
1 2 2 1 1 1

330U_D2_2.5VY_R9M
ic
FBVDDQ_SENSE F1
FBVDDQ_SENSE_GPU RV90 1
@
2 0_0402_5%
+
POSCAP

OPT@

OPT@

OPT@
@

@
FBVDD_VCC_SENSE 67 1 1 2 2 2
@

CV430

CV431

CV432
C FBVDDQ_SENSE_GND_GPU 2 C
PROBE_FB_GND F2 RV91 1 @ 2 0_0402_5%

CV428

CV429
at

CV425
FB_CAL_PD_VDDQ J27 FBCAL_VDDQ 1 2 +1.35VGS
RV92 40.2_0402_1% OPT@
FB_CAL_PU_GND H27
FBCAL_GND 1 2
RV93 40.2_0402_1% OPT@
FB_CALTERM_GND H25
FBCAL_TERM 1 2

em
RV94 60.4_0402_1% OPT@
Under GPU
Place near balls
N17P-G1_FCBGA908

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
@ 2 2 2 2 2 1 1 1 1 1

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K
+1.35VGS

OPT@

OPT@

OPT@

OPT@
CD@
1 1 1 1 1 2 2 2 2 2

ch

OPT@

OPT@

OPT@

OPT@

OPT@
CV433

CV434

CV435

CV436

CV437
FBVDD_VCC_SENSE @
RV310 1 2 2_0402_5%

CV438

CV439

CV440

CV441

CV442
PLACE MIDWAY BETWEEN FBA AND FBB

kS
Follow NV suggestion for NVVDDS Hai Y520 SVT
oo +1.8VALW

22U_0603_6.3V6-M
1 1

CV1184
CV1185
1U_0402_6.3V6K
2 2
DV10 @ OPT@
@
3
RV1264 1 2 0_0402_5%
eb

2
OPT@ 2
+3VS +5VALW 2 RV1265 1 OPT@ 2 47K_0402_5% @ UV11 +1.8VS_AON
0.1U_0402_25V6
100K_0402_5% 1 14
CV1186 IN1_1 OUT1_2

22U_0603_6.3V6-M
RV1260 2 13

1U_0402_6.3V6K
LBAT54SW T1G_SOT323-3
1

B B
OPT@

IN1_2 OUT1_1
1

1 1

CV1189

CV1187
1
2

PXS_PWREN
ot

RV108 RV1261 1 @ 2 100K_0402_5% 3 12 CV1188 1 2 1000P_0201_50V7-K

RV109 47K_0402_5% EN1 CT1 OPT@
OPT@
10K_0402_5% @ 4 11 2 2
+5VALW VBIAS GND
OPT@
@
2

RV12661 @ 2 0_0402_5% RV58 1 @ 2 47K_0402_5% 1V8_MAIN_EN_U 5 10 CV1190 1 2 1000P_0201_50V7-K

28 1V8_MAIN_EN_R EN2 CT2
1

PXS_PWREN#
+1.8VS_AON OPT@ VGA_MAIN_3V_1.8V
N

6 9
0.1U_0402_25V6

@ IN2_1 OUT2_2
1

RV1267 1 2 0_0402_5% 2 7 8
28,68 NVVDD_EN 1 IN2_2 OUT2_1
1

D DV11 RV84
CV38

PXS_PWREN @ 1
2 3
RV1263 1 2 0_0402_5% @ 100K_0402_5% 15
19,28 PXS_PWREN VGA_MAIN_3V_1.8V Enable CV1191 Thermal Pad
G
OPT@

1 @ 1U_0402_6.3V6K CV74
QV18 1 2 OPT@
OPT@
2

10U 6.3V M X5R 0402

1

S 2N7002KW _SOT323-3 OPT@ G2898KD1U_TDFN14P_2X3 2

3

@ 2RV1262 1 OPT@ 20K_0402_5%

2
@ RV115

1
100K_0402_5% LBAT54SW T1G_SOT323-3 +5VALW RV85
47_0603_5%
2

2
RV86
47K_0402_5%
@

1
D
+1.8VGS_PWR_EN# 2
G
QV20
S 2N7002KW _SOT323-3

1
D

3
1V8_MAIN_EN_U @
2
+1.8VS_AON G
QV9
S 2N7002KW _SOT323-3

3
@
Add +1.8V-AON discharger circuit HLZ SIV 0811
1

RV66
470_0603_5%
@
2

A A
1

D
PXS_PWREN# 2
G
QV13
S 2N7002KW _SOT323-3
3

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 N17P_(5/6):PWR

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
FG541/FG741 1.0

Date: Tuesday, March 26, 2019 Sheet 29 of 68

5 4 3 2 1
 5 4 3 2 1

Follow NV suggestion for NVVDD Hai Y520 SVT

UV1I
INS37080704
UV1J
INS37081288
UV1H
INS37079967
47A Peak90A UV1D
INS37080201
? ? ? ?
COMMON COMMON COMMON COMMON
NVVDD NVVDD

D
A2
A33
GND
GND
15/17 GND_1/2
GND
GND
AM25
AN1 N19 GND
16/17 GND_2/2

GND T28
9/17 XVDD

CONFIGURABLE
NEAR GPU UNDER GPU 13/17 NVVDD

D
AA13 AN10 N2 T32 POWER NVVDD AA14
GND GND GND GND VDD
AA15 AN13 N21 T5 CHANNELS AA21

RF_NS@
GND GND GND GND VDD

RF_NS@
AA17 AN16 N23 T7 U4 AB13

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
GND GND GND GND XVDD 2 2 2 2 2 1 1 1 1 1 1 1 1 VDD
AA18 AN19 N28 U12 U5 1 AB15

4.7U_0603_6.3V6K
33P_0402_50V8J

33P_0402_50V8J

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K
GND GND GND GND XVDD 1 1 1 VDD

4.7U_0603_6.3V6K
AA20 GND GND AN22 N30 GND GND U14 XVDD U6 AB17 VDD
AA22 AN25 N32 U16 U7 AB18

@
OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
CD@

CD@

CD@

CD@
GND GND GND GND XVDD VDD
1 1 1 1 1 2 2 2 2 2 2 2 2

CV1183 OPT@
AB12 AN30 N33 U19 U8 AB20

CV150 OPT@
GND GND GND GND XVDD 2 VDD
AB14 AN34 N5 U21 V1 2 2 2 AB22

CV148

CV135

CV136

CV147

CV138
GND GND GND GND XVDD VDD
AB16 AN4 N7 U23 V2 AC12

CD94

CD93
GND GND GND GND XVDD VDD

CV139

CV140

CV141

CV142

CV143

CV144

CV145

CV146
AB19 GND GND AN7 P13 GND GND V12 XVDD V3 AC16 VDD
AB2 GND GND AP2 P15 GND GND V14 XVDD V4 AC19 VDD
AB21 GND GND AP33 P17 GND GND V16 AC23 VDD
AB23 GND GND B1 P18 GND GND V19 M12 VDD
AB28 GND GND B10 P20 GND GND V21 XVDD V5 M16 VDD
AB30 GND GND B22 P22 GND GND V23 XVDD V6 M19 VDD

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
AB32 B25 R12 W13 V7 M23

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
GND GND GND GND XVDD 2 2 2 2 VDD
AB5 GND GND B28 R14 GND GND W15 XVDD V8 1 1 1 1 1 1 1 N13 VDD
AB7 GND GND B31 R16 GND GND W17 XVDD W2 N15 VDD
AC13 B34 R19 W18 W3 N17

OPT@

OPT@

OPT@
CD@
GND GND GND GND XVDD VDD

@
OPT@

OPT@

m
CD@
AC15 B4 R21 W20 W4 1 1 1 1 N18
GND GND GND GND XVDD 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 VDD

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
AC17 B7 R23 W22 W5 N20

CV151

CV152

CV153

CV1182
GND GND GND GND XVDD VDD
AC18 GND GND C10 T13 GND GND W28 XVDD W7 N22 VDD

CV1178

CV1181

CV1180

CV1179
AC20 C13 T15 Y12 P14

CV137

CV134

CV149
GND GND GND GND VDD
2 2 2 2 2 2 2 2

co
AC22 GND GND C19 T17 GND GND Y14 P21 VDD
AE2 C22 T18 Y16 W8 R13

@
OPT@

OPT@

OPT@

OPT@

OPT@
CV154

CV155

CV156

CV157

CV158

CV159

CV160
CD@

CD@
GND GND GND GND XVDD VDD

CV161
AE28 GND GND C25 T2 GND GND Y19 XVDD Y1 R15 VDD
AE30 GND GND C28 T20 GND GND Y21 XVDD Y2 R17 VDD
AE32 GND GND C7 T22 GND GND Y23 XVDD Y3 R18 VDD
AE33 D2 AG11 AH11 Y4 R20

s.
GND GND GND GND XVDD VDD
C AE5 GND GND D31 XVDD Y5 R22 VDD C
AE7 GND GND D33 XVDD Y6 T12 VDD
AH10 GND GND E10 XVDD Y7 T16 VDD

ic
AH13 GND GND E22 XVDD Y8 T19 VDD
AH16 GND GND E25 T23 VDD
AH19 GND GND E5 1 1 1 1 1 1 1 U13 VDD

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
AH2 GND GND E7 XVDD AA1 U15 VDD

at
AH22 GND GND F28 XVDD AA2 U18 VDD
AH24 GND GND F7 XVDD AA3 U20 VDD
AH28 G10 AA4 2 2 2 2 2 2 2 U22
GND GND XVDD VDD
AH29 G13 AA5 V13
delete 330UF

@
OPT@

OPT@

OPT@

OPT@
CV164

CV165

CV166

CV167

CV168

CV169
CD@

CD@
GND GND XVDD VDD

CV170
AH30 G16 AA6 V15

em
GND GND XVDD VDD
AH32 GND GND G19 XVDD AA7 V17 VDD
AH33
AH5
AH7
GND
GND
GND
GND
GND
GND
G2
G22
G25
GND_OPT C16
GND_OPT W32
XVDD AA8
POSCAP 0831SF V20
V22
W12
VDD
VDD
VDD
AJ7 GND GND G28 Optional CMD GNDs (2) W16 VDD
AK10 GND GND G3 NC for 4-Lyr cards W19 VDD
AK7 G30 W23

ch
GND GND VDD
AL12 GND GND G32 N17P-G1_FCBGA908 Y13 VDD
AL14 GND GND G33 @ Y15 VDD
AL15 GND GND G5 Y17 VDD
AL17 GND GND G7 N17P-G1_FCBGA908 Y18 VDD
AL18 GND GND K2 @ Y20 VDD

kS
AL2 GND GND K28 Y22 VDD
AL20 GND GND K30
AL21 GND GND K32
AL23 GND GND K33 Change QV6/RV48/QV4/RV62 from REV@ to ns Hai Y520 SVT
AL24 GND GND K5
AL26 K7
GND GND
oo
B B
AL28 GND GND M13
AL30 GND GND M15
AL32 M17 +1.35VGS
GND GND
AL33 M18
AL5
GND
GND
GND
GND M20 Change NVVDDS & +1.0VGS discharge circuit
HLZ SIV 0725

1
+5VALW
eb

AM13 GND GND M22

AM16 GND GND N12 RV61
AM19 GND GND N14 @ 470_0603_5%

1
AM22 GND GND N16 VDD_SENSE L4
NVVDD +1.0VGS RV48

2
@ 47K_0402_5%
ot

GND_SENSE L5
N17P-G1_FCBGA908

3
@ D QV6B
5 N17P-G1_FCBGA908
G 2N7002KDWH_SOT363-6
15_0805_1%

15_0805_1%

15_0805_1%

15_0805_1%

15_0805_1%

15_0805_1%

15_0805_1%

@
N
2 RV332 1

RV45 1

2 RV326 1

2 RV327 1

RV63 1

2 RV328 1

2 RV329 1

@ NVVDD_VSS_SENSE
Add RV332 for NVVDDS discharge Hai Y520 SVT S
68 NVVDD_VSS_SENSE
OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

4
6
D QV6A NVVDD_VCC_SENSE
+5VALW 68 NVVDD_VCC_SENSE
2
28,67 FBVDDQ_PWR_EN 2N7002KDWH_SOT363-6
G
2

@ trace width: 16mils

1

S
RV60 1 differential voltage sensing.
47K_0402_5% differential signal routing.
1

OPT@
D

D
2

2 2
A
G G A
LBSS139WT1G_SC70-3

QV11 QV29 QV12

D
1

AO3402_SOT-23-3 AO3402_SOT-23-3
3

2
OPT@

28,67 1V0_MAIN_EN
G OPT@ OPT@
S Security Classification LC Future Center Secret Data Title
3

Issued Date 2015/08/20 Deciphered Date 2016/08/20 N17P_(6/6):PWR,VSS

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FG541/FG741
Date: Tuesday, March 26, 2019 Sheet 30 of 68
5 4 3 2 1
 5 4 3 2 1

Memory Partition A - Lower 64 bits(MF=0) UV4

MF=0 MF=1 MF=1 MF=0

FBA_D0 FBA_D[0..7] 27 BYTE0 DQ0-DQ7/EDC0/DBI0#/WCK0

A4
FBA_EDC0 C2 DQ24 DQ0 A2 FBA_D1
27 FBA_EDC0 FBA_EDC1 EDC0 EDC3 DQ25 DQ1 FBA_D2
C13 B4
27 FBA_EDC1 FBA_EDC2 EDC1 EDC2 DQ26 DQ2 FBA_D3
R13 B2
27 FBA_EDC2 FBA_EDC3 EDC2 EDC1 DQ27 DQ3 FBA_D4
R2 E4
27 FBA_EDC3 EDC3 EDC0 DQ28 DQ4 FBA_D5
E2
DQ29 DQ5 F4 FBA_D6
FBA_DBI0# D2 DQ30 DQ6 F2 FBA_D7
27 FBA_DBI0# FBA_DBI1# DBI0# DBI3# DQ31 DQ7 FBA_D8 FBA_D[8..15] 27 BYTE1 DQ8-DQ15/EDC1/DBI1#/WCK0
D13 A11
27 FBA_DBI1# FBA_DBI2# DBI1# DBI2# DQ16 DQ8 FBA_D9
P13 A13
27 FBA_DBI2# FBA_DBI3# DBI2# DBI1# DQ17 DQ9 FBA_D10
D
P2 B11 D
27 FBA_DBI3# DBI3# DBI0# DQ18 DQ10 FBA_D11
B13
FBA_CLK0 J12 DQ19 DQ11 E11 FBA_D12
27 FBA_CLK0 FBA_CLK0# CK DQ20 DQ12 FBA_D13
J11 E13
27 FBA_CLK0# FBA_CKE_L CK# DQ21 DQ13 FBA_D14
J3 F11
27 FBA_CKE_L CKE# DQ22 DQ14 FBA_D15
F13 BYTE2 DQ16-DQ23/EDC2/DBI2#/WCK1
DQ23 DQ15 FBA_D16 FBA_D[16..23] 27
U11
FBA_MA2_BA0_L H11 DQ8 DQ16 U13 FBA_D17
27 FBA_MA2_BA0_L FBA_MA5_BA1_L BA0/A2 BA2/A4 DQ9 DQ17 FBA_D18
K10 T11
27 FBA_MA5_BA1_L FBA_MA4_BA2_L BA1/A5 BA3/A3 DQ10 DQ18 FBA_D19
K11 T13
27 FBA_MA4_BA2_L FBA_MA3_BA3_L BA2/A4 BA0/A2 DQ11 DQ19 FBA_D20
H10 N11
27 FBA_MA3_BA3_L BA3/A3 BA1/A5 DQ12 DQ20 FBA_D21
N13
DQ13 DQ21 M11 FBA_D22
FBA_MA7_MA8_L K4 DQ14 DQ22 M13 FBA_D23
27 FBA_MA7_MA8_L FBA_MA1_MA9_L A8/A7 A10/A0 DQ15 DQ23 FBA_D24 FBA_D[24..31] 27 BYTE3 DQ24-DQ31/EDC3/DBI3#/WCK1
H5 U4
27 FBA_MA1_MA9_L FBA_MA0_MA10_L A9/A1 A11/A6 DQ0 DQ24 FBA_D25
H4 U2
27 FBA_MA0_MA10_L FBA_MA6_MA11_L A10/A0 A8/A7 DQ1 DQ25 FBA_D26
K5 T4
27 FBA_MA6_MA11_L FBA_MA12_RFU_L A11/A6 A9/A1 DQ2 DQ26 FBA_D27
J5 T2
27 FBA_MA12_RFU_L A12/RFU/NC DQ3 DQ27 FBA_D28
N4
A5 DQ4 DQ28 N2 FBA_D29
U5 VPP/NC1 DQ5 DQ29 M4 FBA_D30
VPP/NC2 DQ6 DQ30 M2 FBA_D31
DQ7 DQ31
RV127 2 1 1K_0402_1% @ J1 +1.35VGS
RV129 2 1 1K_0402_1% @ J10 MF
2 1 121_0402_1% J13 SEN B1
Cost down list:

m
RV131 @
ZQ VDDQ1
VDDQ2
D1
F1
2A Peak 3A 22U 2Pcs
Follow DG FBA_ABI#_L VDDQ3
J4 M1
27 FBA_ABI#_L FBA_RAS#_L ABI# VDDQ4
G3 P1
FBA_CLK0 27 FBA_RAS#_L FBA_CS#_L RAS# CAS# VDDQ5
1 2 G12 T1

co
27 FBA_CS#_L FBA_CAS#_L CS# WE# VDDQ6
RV133 L3 G2 +1.35VGS UV4 SIDE
27 FBA_CAS#_L FBA_WE#_L CAS# RAS# VDDQ7
40.2_0402_1% L12 L2
27 FBA_WE#_L WE# CS# VDDQ8
1

@ B3
RV134 VDDQ9 D3

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

80.6_0402_1% @ VDDQ10 F3 2 2 2 2 2 2 2 2 2

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K
FBA_WCK0_N D5 VDDQ11 H3
27 FBA_WCK0_N FBA_WCK0 D4 WCK01# WCK23# VDDQ12 K3 GDDR5

s.
C 27 FBA_WCK0 WCK01 WCK23 VDDQ13 C
2

FBA_CLK0# 1 2 M3
Mode H - Mirror Mode Mapping

@
RV135 FBA_WCK1_N P5 VDDQ14 P3 1 1 1 1 1 1 1 1 1
27 FBA_WCK1_N FBA_WCK1 WCK23# WCK01# VDDQ15
40.2_0402_1% P4 T3

CV313

CV314

CV315
1 27 FBA_WCK1 WCK23 WCK01 VDDQ16
@ E5

CV188

CV308

CV309

CV310

CV311

CV312
0.01U_0402_25V7K

VDDQ17

ic
VDDQ18
N5 DATA Bus
A10 E10
2 U10 VREFD1 VDDQ19 N10
+FBA_VREFC0 VREFD2 VDDQ20
Address 0..31 32..63
J14 B12 AROUND DRAM CLOSE TO DRAM
@

VREFC VDDQ21 D12 FBx_CMD0 CS#

CV177

at
VDDQ22 F12
VDDQ23
FBA_RST#_L VDDQ24
H12 FBx_CMD1 A3_BA3
J2 K12 2 2 2 2 2 2 2

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K
27 FBA_RST#_L RESET# VDDQ25

1
VDDQ26
M12 FBx_CMD2 A2_BA0
P12
VDDQ27 T12 FBx_CMD3 A4_BA2

2@

2@

2@

2@

2@

@
em
VDDQ28 G13 1 1 1 1 1 1 1

CV316

CV317

CV318

CV319

CV320
H1 VDDQ29 L13 FBx_CMD4 A5_BA1

CV321

CV322

CV323

CV324

CV325

CV326

CV327
K1 VSS1 VDDQ30 B14
VSS2 VDDQ31
B5
VSS3 VDDQ32
D14 FBx_CMD5 WE#
G5 F14
VSS4 VDDQ33
L5
VSS5 VDDQ34
M14 FBx_CMD6 A7_A8
T5 P14 AROUND DRAM CLOSE TO DRAM
VSS6 VDDQ35
B10
VSS7 VDDQ36
T14 FBx_CMD7 A6_A11
D10

ch
VSS8
G10
VSS9
FBx_CMD8 ABI#
L10 A1
P10 VSS10 VSSQ1 C1
VSS11 VSSQ2 FBx_CMD9 A12_RFU
T10 E1
VSS12 VSSQ3
H14
VSS13 VSSQ4
N1 FBx_CMD10 A0_A10
K14 R1
+1.35VGS VSS14 VSSQ5 U1 +1.35VGS FBx_CMD11 A1_A9

kS
VSSQ6 H2
VSSQ7 UNDER DRAM
G1
VDD1 VSSQ8
K2 FBx_CMD12 RAS#
L1 A3
VDD2 VSSQ9
G4 C3 2 FBx_CMD13 RST#

1U_0201_6.3V6K
2

1U_0201_6.3V6K
2

1U_0201_6.3V6K
2

1U_0201_6.3V6K
L4 VDD3 VSSQ10 E3
C5 VDD4 VSSQ11 N3
B VDD5 VSSQ12 FBx_CMD14 CKE# B
R5 R3

@
VDD6
oo VSSQ13 1 1 1 1
C10
VDD7 VSSQ14
U3 FBx_CMD15 CAS#
R10 C4

CV357

CV350

CV351

CV352
VDD8 VSSQ15
D11
VDD9 VSSQ16
R4 FBx_CMD16 CS#
G11 F5
VDD10 VSSQ17
L11
VDD11 VSSQ18
M5 FBx_CMD17 A3_BA3
P11 F10
VDD12 VSSQ19
G14 M10 FBx_CMD18 A2_BA0
eb

L14 VDD13 VSSQ20 C11

VDD14 VSSQ21 UNDER DRAM
R11 FBx_CMD19 A4_BA2
VSSQ22 A12
VSSQ23 C12 2 2 2 2 FBx_CMD20 A5_BA1

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K
VSSQ24 E12
VSSQ25
VSSQ26
N12 FBx_CMD21 WE#
R12

@
VSSQ27 1 1 1 1
ot

170-BALL
VSSQ28
U12 FBx_CMD22 A7_A8
H13

CV358

CV354

CV355

CV356
VSSQ29
SGRAM GDDR5
VSSQ30
K13 FBx_CMD23 A6_A11
A14
VSSQ31 C14
VSSQ32 FBx_CMD24 ABI#
E14
VSSQ33
N

+1.35VGS VSSQ34
N14 FBx_CMD25 A12_RFU
R14
VSSQ35
VSSQ36
U14 FBx_CMD26 A0_A10
@ FBx_CMD27 A1_A9
1

RV136 H5GC2H24BFR-T2C_BGA170 FBx_CMD28 RAS#

549_0402_1%
OPT@
16 mil FBx_CMD29 RST#
2

1 OPT@ 2 +FBA_VREFC0 FBx_CMD30 CKE#

+FBA_VREFC0 32
RV137
1

931_0402_1% RV138 1 FBx_CMD31 CAS#

1.33K_0402_1% CV178
1

OPT@ 820P_0402_25V7
A QV26 @ A
2
LSI1012XT1G_SC-89-3
2

2
28,33 MEM_VREF
3

OPT@

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 N17P_GDDR5_A Lower

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
FG541/FG741 1.0

Date: Tuesday, March 26, 2019 Sheet 31 of 68

5 4 3 2 1
 5 4 3 2 1

Memory Partition A- Upper 64 bits(MF=0)

UV6

MF=0 MF=1 MF=1 MF=0

FBA_D32 FBA_D[32..39] 27 BYTE4 DQ32-DQ39/EDC4/DBI4#/WCK2

A4
FBA_EDC4 C2 DQ24 DQ0 A2 FBA_D33
27 FBA_EDC4 FBA_EDC5 EDC0 EDC3 DQ25 DQ1 FBA_D34
C13 B4
27 FBA_EDC5 FBA_EDC6 EDC1 EDC2 DQ26 DQ2 FBA_D35
R13 B2
27 FBA_EDC6 FBA_EDC7 EDC2 EDC1 DQ27 DQ3 FBA_D36
R2 E4
27 FBA_EDC7 EDC3 EDC0 DQ28 DQ4 FBA_D37
E2
DQ29 DQ5 F4 FBA_D38
FBA_DBI4# D2 DQ30 DQ6 F2 FBA_D39
27 FBA_DBI4# FBA_DBI5# DBI0# DBI3# DQ31 DQ7 FBA_D40 FBA_D[40..47] 27 BYTE5 DQ40-DQ47/EDC5/DBI5#/WCK2
D13 A11
27 FBA_DBI5# FBA_DBI6# DBI1# DBI2# DQ16 DQ8 FBA_D41
P13 A13
27 FBA_DBI6# FBA_DBI7# DBI2# DBI1# DQ17 DQ9 FBA_D42
D
P2 B11 D
27 FBA_DBI7# DBI3# DBI0# DQ18 DQ10 FBA_D43
B13
FBA_CLK1 J12 DQ19 DQ11 E11 FBA_D44
27 FBA_CLK1 FBA_CLK1# CK DQ20 DQ12 FBA_D45
J11 E13
27 FBA_CLK1# FBA_CKE_H CK# DQ21 DQ13 FBA_D46
J3 F11
27 FBA_CKE_H CKE# DQ22 DQ14 FBA_D47
F13 BYTE6 DQ48-DQ55/EDC6/DBI6#/WCK3
DQ23 DQ15 FBA_D48 FBA_D[48..55] 27
U11
FBA_MA2_BA0_H H11 DQ8 DQ16 U13 FBA_D49
27 FBA_MA2_BA0_H FBA_MA5_BA1_H BA0/A2 BA2/A4 DQ9 DQ17 FBA_D50
K10 T11
27 FBA_MA5_BA1_H FBA_MA4_BA2_H K11 BA1/A5 BA3/A3 DQ10 DQ18 T13 FBA_D51
27 FBA_MA4_BA2_H FBA_MA3_BA3_H H10 BA2/A4 BA0/A2 DQ11 DQ19 N11 FBA_D52
27 FBA_MA3_BA3_H BA3/A3 BA1/A5 DQ12 DQ20 FBA_D53
N13
DQ13 DQ21 M11 FBA_D54
FBA_MA7_MA8_H DQ14 DQ22 FBA_D55
BYTE7 DQ56-DQ63/EDC7/DBI7#/WCK3
27 FBA_MA7_MA8_H K4 M13
FBA_MA1_MA9_H A8/A7 A10/A0 DQ15 DQ23 FBA_D56 FBA_D[56..63] 27
H5 U4
27 FBA_MA1_MA9_H FBA_MA0_MA10_H A9/A1 A11/A6 DQ0 DQ24 FBA_D57
H4 U2
27 FBA_MA0_MA10_H FBA_MA6_MA11_H A10/A0 A8/A7 DQ1 DQ25 FBA_D58
K5 T4
27 FBA_MA6_MA11_H FBA_MA12_RFU_H A11/A6 A9/A1 DQ2 DQ26 FBA_D59
J5 T2
27 FBA_MA12_RFU_H A12/RFU/NC DQ3 DQ27 FBA_D60
Follow DG N4
A5 DQ4 DQ28 N2 FBA_D61
U5 VPP/NC1 DQ5 DQ29 M4 FBA_D62
FBA_CLK1 1 2 VPP/NC2 DQ6 DQ30 M2 FBA_D63
RV148 DQ7 DQ31
40.2_0402_1% RV143 2 1 1K_0402_1% OPT@ J1 +1.35VGS
OPT@ RV145 2 1 1K_0402_1% OPT@ J10 MF
SEN
1

2 1 121_0402_1% J13 B1

m
RV147 OPT@
RV149 ZQ VDDQ1 D1
80.6_0402_1% @ VDDQ2 F1
FBA_ABI#_H J4 VDDQ3 M1
27 FBA_ABI#_H FBA_RAS#_H ABI# VDDQ4
G3 P1
27 FBA_RAS#_H RAS# CAS# VDDQ5
2

FBA_CLK1# 1 2 FBA_CS#_H G12 T1

co
27 FBA_CS#_H FBA_CAS#_H CS# WE# VDDQ6
L3 G2
RV150
40.2_0402_1%
27 FBA_CAS#_H FBA_WE#_H L12 CAS# RAS# VDDQ7 L2
Cost down list: GDDR5
1
2A Peak 3A
0.01U_0402_25V7K

27 FBA_WE#_H WE# CS# VDDQ8 22U 2Pcs

OPT@
VDDQ9
VDDQ10
B3
D3 Mode H - Mirror Mode Mapping
F3
2 FBA_WCK2_N D5 VDDQ11 H3
OPT@

27 FBA_WCK2_N FBA_WCK2 WCK01# WCK23# VDDQ12

D4 K3 DATA Bus
CV196

s.
C 27 FBA_WCK2 WCK01 WCK23 VDDQ13 C
M3 +1.35VGS UV6 SIDE
FBA_WCK3_N P5 VDDQ14 P3
27 FBA_WCK3_N FBA_WCK3 WCK23# WCK01# VDDQ15
Address 0..31 32..63
P4 T3
27 FBA_WCK3 WCK23 WCK01 VDDQ16 E5 FBx_CMD0 CS#

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

VDDQ17

ic
N5 2 2 2 2 2 2 2

1U_0201_6.3V6K
2

1U_0201_6.3V6K
2

1U_0201_6.3V6K
VDDQ18
A10
VREFD1 VDDQ19
E10 FBx_CMD1 A3_BA3
U10 N10
+FBA_VREFC0 VREFD2 VDDQ20
J14 B12 FBx_CMD2 A2_BA0

CV329 OPT@

CV330 OPT@

CV332 OPT@

CV334 OPT@

CV333 OPT@

CV335 OPT@

CV336 OPT@

CV337 OPT@
CV331 CD@
VREFC VDDQ21 D12 1 1 1 1 1 1 1 1 1

at
VDDQ22
VDDQ23
F12 FBx_CMD3 A4_BA2
H12
FBA_RST#_H J2 VDDQ24 K12
27 FBA_RST#_H RESET# VDDQ25 FBx_CMD4 A5_BA1
M12
VDDQ26
VDDQ27
P12 FBx_CMD5 WE#
T12 AROUND DRAM CLOSE TO DRAM

em
VDDQ28
VDDQ29
G13 FBx_CMD6 A7_A8
H1 L13
VSS1 VDDQ30
K1
VSS2 VDDQ31
B14 FBx_CMD7 A6_A11
B5 D14

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
2 2 2 2 2 2 2

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K
VSS3 VDDQ32

1
G5
VSS4 VDDQ33
F14 FBx_CMD8 ABI#
L5 M14
T5 VSS5 VDDQ34 P14 FBx_CMD9 A12_RFU

CV345 OPT@

CV344 OPT@

CV346 OPT@

CV347 OPT@

CV348 OPT@

CV328 OPT@
CV343 CD@
VSS6 VDDQ35

OPT@ 2

OPT@ 2

@ 2

OPT@ 2

@ 2
B10 T14 1 1 1 1 1 1 1
16 mil

CV338

CV339

CV340

CV341

CV342
VSS7 VDDQ36
D10 FBx_CMD10 A0_A10

ch
G10 VSS8
VSS9
+FBA_VREFC0
L10
VSS10 VSSQ1
A1 FBx_CMD11 A1_A9
P10 C1
31 +FBA_VREFC0 VSS11 VSSQ2
T10
VSS12 VSSQ3
E1 FBx_CMD12 RAS#
1 H14 N1 AROUND DRAM CLOSE TO DRAM
VSS13 VSSQ4
+1.35VGS
K14
VSS14 VSSQ5
R1 FBx_CMD13 RST#
CV197 U1

kS
VSSQ6 H2
820P_0402_25V7
2 OPT@ VSSQ7 FBx_CMD14 CKE#
G1 K2
VDD1 VSSQ8
L1
VDD2 VSSQ9
A3 FBx_CMD15 CAS#
G4 C3
VDD3 VSSQ10
L4
VDD4 VSSQ11
E3 FBx_CMD16 CS#
B
C5 N3 +1.35VGS B
VDD5 VSSQ12
R5 R3 UNDER DRAM FBx_CMD17 A3_BA3
VDD6
oo VSSQ13
C10 U3
VDD7 VSSQ14
R10
VDD8 VSSQ15
C4 FBx_CMD18 A2_BA0
D11 R4 2 2 2 2

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K
G11 VDD9 VSSQ16 F5
VDD10 VSSQ17 FBx_CMD19 A4_BA2
L11 M5
VDD11 VSSQ18
P11 F10 FBx_CMD20 A5_BA1

CV365 OPT@

CV361 OPT@
CV360 CD@

CV359 CD@
G14 VDD12 VSSQ19 M10 1 1 1 1
eb

VDD13 VSSQ20
L14
VDD14 VSSQ21
C11 FBx_CMD21 WE#
R11
VSSQ22
VSSQ23
A12 FBx_CMD22 A7_A8
C12
VSSQ24
VSSQ25
E12 FBx_CMD23 A6_A11
N12
VSSQ26 R12
VSSQ27 UNDER DRAM FBx_CMD24 ABI#
ot

170-BALL U12
VSSQ28
VSSQ29
H13 FBx_CMD25 A12_RFU
SGRAM GDDR5 K13 2

1U_0201_6.3V6K
2

1U_0201_6.3V6K
2

1U_0201_6.3V6K
2

1U_0201_6.3V6K
VSSQ30
VSSQ31
A14 FBx_CMD26 A0_A10
C14
VSSQ32 E14 FBx_CMD27 A1_A9

CV362 OPT@

CV363 OPT@

CV364 OPT@
CV366 CD@
VSSQ33 1 1 1 1
N

N14
VSSQ34
VSSQ35
R14 FBx_CMD28 RAS#
U14
VSSQ36
FBx_CMD29 RST#
@
FBx_CMD30 CKE#
H5GC2H24BFR-T2C_BGA170
FBx_CMD31 CAS#

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 N17P_GDDR5_A Upper

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
FG541/FG741 1.0

Date: Tuesday, March 26, 2019 Sheet 32 of 68

5 4 3 2 1
 5 4 3 2 1

Memory Partition B - Lower 32 bits(MF=0)

UV8

MF=0 MF=1 MF=1 MF=0

A4 FBC_D0 FBC_D[0..7] 27 BYTE0 DQ0-DQ7/EDC0/DBI0#/WCK0

FBC_EDC0 C2 DQ24 DQ0 A2 FBC_D1
27 FBC_EDC0 FBC_EDC1 C13 EDC0 EDC3 DQ25 DQ1 B4 FBC_D2
27 FBC_EDC1 FBC_EDC2 R13 EDC1 EDC2 DQ26 DQ2 B2 FBC_D3
27 FBC_EDC2 FBC_EDC3 R2 EDC2 EDC1 DQ27 DQ3 E4 FBC_D4
27 FBC_EDC3 EDC3 EDC0 DQ28 DQ4 E2 FBC_D5
DQ29 DQ5 F4 FBC_D6
FBC_DBI0# D2 DQ30 DQ6 F2 FBC_D7
27 FBC_DBI0# FBC_DBI1# D13 DBI0# DBI3# DQ31 DQ7 A11 FBC_D8 FBC_D[8..15] 27 BYTE1 DQ8-DQ15/EDC1/DBI1#/WCK0
D 27 FBC_DBI1# DBI1# DBI2# DQ16 DQ8 D
FBC_DBI2# P13 A13 FBC_D9
27 FBC_DBI2# FBC_DBI3# P2 DBI2# DBI1# DQ17 DQ9 B11 FBC_D10
27 FBC_DBI3# DBI3# DBI0# DQ18 DQ10 B13 FBC_D11
FBC_CLK0 J12 DQ19 DQ11 E11 FBC_D12
27 FBC_CLK0 FBC_CLK0# J11 CK DQ20 DQ12 E13 FBC_D13
27 FBC_CLK0# FBC_CKE_L J3 CK# DQ21 DQ13 F11 FBC_D14
27 FBC_CKE_L CKE# DQ22 DQ14 F13 FBC_D15
DQ23 DQ15 U11 FBC_D16 FBC_D[16..23] 27 BYTE2 DQ16-DQ23/EDC2/DBI2#/WCK1
FBC_MA2_BA0_L H11 DQ8 DQ16 U13 FBC_D17
27 FBC_MA2_BA0_L FBC_MA5_BA1_L K10 BA0/A2 BA2/A4 DQ9 DQ17 T11 FBC_D18
27 FBC_MA5_BA1_L FBC_MA4_BA2_L K11 BA1/A5 BA3/A3 DQ10 DQ18 T13 FBC_D19
27 FBC_MA4_BA2_L FBC_MA3_BA3_L H10 BA2/A4 BA0/A2 DQ11 DQ19 N11 FBC_D20
27 FBC_MA3_BA3_L BA3/A3 BA1/A5 DQ12 DQ20 FBC_D21
N13
DQ13 DQ21 M11 FBC_D22
FBC_MA7_MA8_L K4 DQ14 DQ22 M13 FBC_D23
27 FBC_MA7_MA8_L FBC_MA1_MA9_L H5 A8/A7 A10/A0 DQ15 DQ23 U4 FBC_D24 FBC_D[24..31] 27 BYTE3 DQ24-DQ31/EDC3/DBI3#/WCK1
Follow DG 27 FBC_MA1_MA9_L FBC_MA0_MA10_L H4 A9/A1 A11/A6 DQ0 DQ24 U2 FBC_D25
27 FBC_MA0_MA10_L FBC_MA6_MA11_L K5 A10/A0 A8/A7 DQ1 DQ25 T4 FBC_D26
FBC_CLK0 1 2 27 FBC_MA6_MA11_L FBC_MA12_RFU_L J5 A11/A6 A9/A1 DQ2 DQ26 T2 FBC_D27
27 FBC_MA12_RFU_L A12/RFU/NC DQ3 DQ27 FBC_D28
RV163 N4
40.2_0402_1% A5 DQ4 DQ28 N2 FBC_D29
OPT@ U5 VPP/NC1 DQ5 DQ29 M4 FBC_D30
VPP/NC2 DQ6 DQ30
1

M2 FBC_D31

m
RV164 DQ7 DQ31
80.6_0402_1% @ RV157 2 1 1K_0402_1% OPT@ J1 +1.35VGS
RV159 2 1 1K_0402_1% OPT@ J10 MF
RV161 2 1 121_0402_1% OPT@ J13 SEN B1
ZQ VDDQ1
2

D1

co
VDDQ2 F1
FBC_CLK0# 1 2 FBC_ABI#_L J4 VDDQ3 M1
27 FBC_ABI#_L FBC_RAS#_L G3 ABI# VDDQ4 P1
RV165
27 FBC_RAS#_L FBC_CS#_L G12 RAS# CAS# VDDQ5 T1
40.2_0402_1% 1 27 FBC_CS#_L FBC_CAS#_L L3 CS# WE# VDDQ6 G2
Cost down list:
2A Peak 3A
OPT@
0.01U_0402_25V7K

27 FBC_CAS#_L
27 FBC_WE#_L
FBC_WE#_L L12 CAS# RAS# VDDQ7 L2 22U 2Pcs
WE# CS# VDDQ8 B3

s.
2 VDDQ9 D3
VDDQ10
OPT@

F3
C
FBC_WCK0_N D5 VDDQ11 H3 GDDR5 C
CV215

27 FBC_WCK0_N FBC_WCK0 D4 WCK01# WCK23# VDDQ12 K3 +1.35VGS UV8 SIDE Mode H - Mirror Mode Mapping

ic
27 FBC_WCK0 WCK01 WCK23 VDDQ13 M3
FBC_WCK1_N P5 VDDQ14 P3
27 FBC_WCK1_N FBC_WCK1 P4 WCK23# WCK01# VDDQ15 T3

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

27 FBC_WCK1 WCK23 WCK01 VDDQ16 E5 DATA Bus

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K
VDDQ17 2 2 2 2 2 2 2 2 2

at
N5
A10 VDDQ18 E10
VREFD1 VDDQ19
Address 0..31 32..63

CV368 OPT@

CV369 OPT@

CV371 OPT@

CV370 OPT@

CV373 OPT@

CV372 OPT@

CV375 OPT@

CV376 OPT@
U10 N10

CV374 CD@
+FBC_VREFC0 J14 VREFD2 VDDQ20 B12 1 1 1 1 1 1 1 1 1
VREFC VDDQ21 FBx_CMD0 CS#
D12
VDDQ22 F12 FBx_CMD1 A3_BA3

em
VDDQ23 H12
FBC_RST#_L J2 VDDQ24 K12
27 FBC_RST#_L RESET# VDDQ25 FBx_CMD2 A2_BA0
M12
VDDQ26
VDDQ27
P12 AROUND DRAM CLOSE TO DRAM FBx_CMD3 A4_BA2
T12
VDDQ28
VDDQ29
G13 FBx_CMD4 A5_BA1
H1 L13
VSS1 VDDQ30
K1 B14 FBx_CMD5 WE#

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K
VSS2 VDDQ31 2 2 2 2 2 2 2

1
B5 D14

ch
VSS3 VDDQ32
G5
VSS4 VDDQ33
F14 FBx_CMD6 A7_A8

CV382 OPT@

CV384 OPT@

CV383 OPT@

CV385 OPT@

CV386 OPT@

CV387 OPT@
L5 M14

CV367 CD@
VSS5 VDDQ34

OPT@ 2

OPT@ 2

@ 2

OPT@ 2

@ 2
T5 P14 1 1 1 1 1 1 1
FBx_CMD7 A6_A11

CV377

CV378

CV379

CV380

CV381
B10 VSS6 VDDQ35 T14
VSS7 VDDQ36
D10
VSS8 FBx_CMD8 ABI#
G10

kS
VSS9
L10
VSS10 VSSQ1
A1 FBx_CMD9 A12_RFU
P10 C1
VSS11 VSSQ2
T10
VSS12 VSSQ3
E1 AROUND DRAM CLOSE TO DRAM FBx_CMD10 A0_A10
H14 N1
VSS13 VSSQ4
K14
VSS14 VSSQ5
R1 FBx_CMD11 A1_A9
U1
+1.35VGS VSSQ6 H2 FBx_CMD12 RAS#
G1
oo VSSQ7 K2
VDD1 VSSQ8
L1
VDD2 VSSQ9
A3 FBx_CMD13 RST#
B
G4 C3 B
VDD3 VSSQ10
L4
VDD4 VSSQ11
E3 +1.35VGS FBx_CMD14 CKE#
C5 N3 UNDER DRAM
VDD5 VSSQ12
R5
VDD6 VSSQ13
R3 FBx_CMD15 CAS#
C10 U3
eb

VDD7 VSSQ14
R10 C4 FBx_CMD16 CS#

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K
VDD8 VSSQ15 2 2 2 2
D11 R4
VDD9 VSSQ16
G11
VDD10 VSSQ17
F5 FBx_CMD17 A3_BA3

CV394 OPT@

CV388 OPT@

CV390 OPT@
L11 M5

CV389 CD@
VDD11 VSSQ18 1 1 1 1
P11
VDD12 VSSQ19
F10 FBx_CMD18 A2_BA0
G14 M10
VDD13 VSSQ20
L14 C11 FBx_CMD19 A4_BA2
ot

VDD14 VSSQ21 R11

VSSQ22
VSSQ23
A12 FBx_CMD20 A5_BA1
C12
VSSQ24
VSSQ25
E12 FBx_CMD21 WE#
N12 UNDER DRAM
VSSQ26 R12 FBx_CMD22 A7_A8
N

170-BALL VSSQ27 U12

VSSQ28 H13 FBx_CMD23 A6_A11

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K
VSSQ29 2 2 2 2
SGRAM GDDR5 K13
VSSQ30
VSSQ31
A14 FBx_CMD24 ABI#

CV395 OPT@

CV393 OPT@

CV392 OPT@
C14

CV391 CD@
+1.35VGS VSSQ32 1 1 1 1
VSSQ33
E14 FBx_CMD25 A12_RFU
N14
VSSQ34
VSSQ35
R14 FBx_CMD26 A0_A10
U14
VSSQ36
1

FBx_CMD27 A1_A9
RV166
549_0402_1%
16 mil @
FBx_CMD28 RAS#
OPT@ H5GC2H24BFR-T2C_BGA170
FBx_CMD29 RST#
2

1 OPT@ 2 +FBC_VREFC0
+FBC_VREFC0 34
RV167 FBx_CMD30 CKE#
1

931_0402_1% 1
RV168 CV216 FBx_CMD31 CAS#
1.33K_0402_1% 820P_0402_25V7
A OPT@ OPT@ A
2
2
1

QV28
LSI1012XT1G_SC-89-3
2
28,31 MEM_VREF
3

OPT@
Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 N17P_GDDR5_B Lower

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
FG541/FG741 1.0

Date: Tuesday, March 26, 2019 Sheet 33 of 68

5 4 3 2 1
 5 4 3 2 1

Memory Partition B - Upper 32 bits(MF=0)

UV10

MF=0 MF=1 MF=1 MF=0

A4 FBC_D32 FBC_D[32..39] 27 BYTE4 DQ32-DQ39/EDC4/DBI4#/WCK2

FBC_EDC4 C2 DQ24 DQ0 A2 FBC_D33
27 FBC_EDC4 FBC_EDC5 C13 EDC0 EDC3 DQ25 DQ1 B4 FBC_D34
27 FBC_EDC5 FBC_EDC6 R13 EDC1 EDC2 DQ26 DQ2 B2 FBC_D35
27 FBC_EDC6 FBC_EDC7 R2 EDC2 EDC1 DQ27 DQ3 E4 FBC_D36
27 FBC_EDC7 EDC3 EDC0 DQ28 DQ4 E2 FBC_D37
DQ29 DQ5 F4 FBC_D38
FBC_DBI4# D2 DQ30 DQ6 F2 FBC_D39
27 FBC_DBI4# FBC_DBI5# D13 DBI0# DBI3# DQ31 DQ7 A11 FBC_D40 FBC_D[40..47] 27 BYTE5 DQ40-DQ47/EDC5/DBI5#/WCK2
27 FBC_DBI5# FBC_DBI6# P13 DBI1# DBI2# DQ16 DQ8 A13 FBC_D41
D 27 FBC_DBI6# DBI2# DBI1# DQ17 DQ9 D
FBC_DBI7# P2 B11 FBC_D42
27 FBC_DBI7# DBI3# DBI0# DQ18 DQ10 B13 FBC_D43
FBC_CLK1 J12 DQ19 DQ11 E11 FBC_D44
27 FBC_CLK1 FBC_CLK1# J11 CK DQ20 DQ12 E13 FBC_D45
27 FBC_CLK1# FBC_CKE_H J3 CK# DQ21 DQ13 F11 FBC_D46
27 FBC_CKE_H CKE# DQ22 DQ14 F13 FBC_D47
DQ23 DQ15 U11 FBC_D48 FBC_D[48..55] 27 BYTE6 DQ48-DQ55/EDC6/DBI6#/WCK3
FBC_MA2_BA0_H H11 DQ8 DQ16 U13 FBC_D49
27 FBC_MA2_BA0_H FBC_MA5_BA1_H K10 BA0/A2 BA2/A4 DQ9 DQ17 T11 FBC_D50
27 FBC_MA5_BA1_H FBC_MA4_BA2_H K11 BA1/A5 BA3/A3 DQ10 DQ18 T13 FBC_D51
Follow DG 27 FBC_MA4_BA2_H FBC_MA3_BA3_H H10 BA2/A4 BA0/A2 DQ11 DQ19 N11 FBC_D52
27 FBC_MA3_BA3_H BA3/A3 BA1/A5 DQ12 DQ20 N13 FBC_D53
FBC_CLK1 1 2 DQ13 DQ21 M11 FBC_D54
FBC_MA7_MA8_H K4 DQ14 DQ22 M13 FBC_D55
BYTE7 DQ56-DQ63/EDC7/DBI7#/WCK3
RV178
27 FBC_MA7_MA8_H FBC_MA1_MA9_H H5 A8/A7 A10/A0 DQ15 DQ23 U4 FBC_D56 FBC_D[56..63] 27
40.2_0402_1%
OPT@ 27 FBC_MA1_MA9_H FBC_MA0_MA10_H H4 A9/A1 A11/A6 DQ0 DQ24 U2 FBC_D57
27 FBC_MA0_MA10_H A10/A0 A8/A7 DQ1 DQ25
1

FBC_MA6_MA11_H K5 T4 FBC_D58
RV179 27 FBC_MA6_MA11_H FBC_MA12_RFU_H J5 A11/A6 A9/A1 DQ2 DQ26 T2 FBC_D59
80.6_0402_1% @ 27 FBC_MA12_RFU_H A12/RFU/NC DQ3 DQ27 N4 FBC_D60
A5 DQ4 DQ28 N2 FBC_D61
U5 VPP/NC1 DQ5 DQ29 M4 FBC_D62
VPP/NC2 DQ6 DQ30
2

M2 FBC_D63
DQ7 DQ31

m
FBC_CLK1# 1 2 RV172 2 1 1K_0402_1% OPT@ J1 +1.35VGS
RV180 RV174 2 1 1K_0402_1% OPT@ J10 MF
40.2_0402_1% RV175 2 1 121_0402_1% OPT@ J13 SEN B1
0.01U_0402_25V7K

1 ZQ VDDQ1
OPT@ D1
VDDQ2 F1

co
FBC_ABI#_H J4 VDDQ3 M1
2 27 FBC_ABI#_H FBC_RAS#_H ABI# VDDQ4 Cost down list:
OPT@

G3 P1
27 FBC_RAS#_H FBC_CS#_H G12 RAS# CAS# VDDQ5 T1 2A Peak 3A 22U 2Pcs
CV234

27 FBC_CS#_H FBC_CAS#_H L3 CS# WE# VDDQ6 G2

27 FBC_CAS#_H FBC_WE#_H L12 CAS# RAS# VDDQ7 L2
27 FBC_WE#_H WE# CS# VDDQ8 B3
VDDQ9 D3 GDDR5

s.
VDDQ10 F3
C 27 FBC_WCK2_N
FBC_WCK2_N D5
WCK01# WCK23#
VDDQ11
VDDQ12
H3
+1.35VGS UV10 SIDE Mode H - Mirror Mode Mapping C
FBC_WCK2 D4 K3
27 FBC_WCK2 WCK01 WCK23 VDDQ13 M3

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

ic
FBC_WCK3_N P5 VDDQ14 P3 DATA Bus

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K
27 FBC_WCK3_N WCK23# WCK01# VDDQ15 2 2 2 2 2 2 2 2 2
FBC_WCK3 P4 T3
27 FBC_WCK3 WCK23 WCK01 VDDQ16 E5
VDDQ17
Address 0..31 32..63

CV397 OPT@

CV400 OPT@

CV402 OPT@

CV401 OPT@

CV404 OPT@

CV403 OPT@
N5

CV398 CD@

CV399 CD@

CV405 CD@
VDDQ18 1 1 1 1 1 1 1 1 1

at
A10 E10 FBx_CMD0 CS#
U10 VREFD1 VDDQ19 N10
+FBC_VREFC0 J14 VREFD2 VDDQ20 B12
VREFC VDDQ21 FBx_CMD1 A3_BA3
D12
VDDQ22 F12
VDDQ23 FBx_CMD2 A2_BA0
H12

em
FBC_RST#_H J2 VDDQ24 K12
27 FBC_RST#_H RESET# VDDQ25 AROUND DRAM Cost down CLOSE TO DRAM FBx_CMD3 A4_BA2
M12
VDDQ26 P12
VDDQ27 FBx_CMD4 A5_BA1
T12
VDDQ28 G13 FBx_CMD5 WE#

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K
VDDQ29 2 2 2 2 2 2 2

1
H1 L13
K1 VSS1 VDDQ30 B14
VSS2 VDDQ31 FBx_CMD6 A7_A8

CV412 OPT@

CV413 OPT@

CV414 OPT@

CV415 OPT@

CV396 OPT@
B5 D14

CV411 CD@

CV416 CD@
VSS3 VDDQ32

OPT@ 2

OPT@ 2

OPT@ 2

2
G5 F14 1 1 1 1 1 1 1
FBx_CMD7 A6_A11

CV406

CV408

CV407

CV409

CV410
ch
L5 VSS4 VDDQ33 M14
T5 VSS5 VDDQ34 P14 FBx_CMD8 ABI#

@
B10 VSS6 VDDQ35 T14
16 mil D10 VSS7 VDDQ36
FBx_CMD9 A12_RFU
G10 VSS8
VSS9
L10 A1 AROUND DRAM CLOSE TO DRAM FBx_CMD10 A0_A10

kS
+FBC_VREFC0 P10 VSS10 VSSQ1 C1
33 +FBC_VREFC0 VSS11 VSSQ2
T10
VSS12 VSSQ3
E1 FBx_CMD11 A1_A9
1 H14 N1
VSS13 VSSQ4
CV235
+1.35VGS
K14
VSS14 VSSQ5
R1 FBx_CMD12 RAS#
820P_0402_25V7 U1
VSSQ6
2
OPT@
VSSQ7
H2 FBx_CMD13 RST#
G1 K2
VDD1
oo VSSQ8
L1
VDD2 VSSQ9
A3 +1.35VGS FBx_CMD14 CKE#
G4 C3 UNDER DRAM
VDD3 VSSQ10
B
L4
VDD4 VSSQ11
E3 FBx_CMD15 CAS# B
C5 N3
VDD5 VSSQ12
R5 R3 FBx_CMD16 CS#

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K
VDD6 VSSQ13 2 2 2 2
C10 U3
VDD7 VSSQ14
R10 C4 FBx_CMD17 A3_BA3
eb

VDD8 VSSQ15

CV423 OPT@

CV417 OPT@

CV419 OPT@

CV418 OPT@
D11 R4
VDD9 VSSQ16 1 1 1 1
G11
VDD10 VSSQ17
F5 FBx_CMD18 A2_BA0
L11 M5
VDD11 VSSQ18
P11
VDD12 VSSQ19
F10 FBx_CMD19 A4_BA2
G14 M10
VDD13 VSSQ20
L14
VDD14 VSSQ21
C11 FBx_CMD20 A5_BA1
R11
ot

VSSQ22
VSSQ23
A12 FBx_CMD21 WE#
C12 UNDER DRAM
VSSQ24
VSSQ25
E12 FBx_CMD22 A7_A8
N12
VSSQ26 R12 FBx_CMD23 A6_A11

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K
VSSQ27 2 2 2 2
170-BALL U12
N

VSSQ28
VSSQ29
H13 FBx_CMD24 ABI#

CV424 OPT@

CV422 OPT@

CV420 OPT@
K13

CV421 CD@
SGRAM GDDR5
VSSQ30 1 1 1 1
VSSQ31
A14 FBx_CMD25 A12_RFU
C14
VSSQ32
VSSQ33
E14 FBx_CMD26 A0_A10
N14
VSSQ34
VSSQ35
R14 FBx_CMD27 A1_A9
U14
VSSQ36
FBx_CMD28 RAS#
@
FBx_CMD29 RST#
H5GC2H24BFR-T2C_BGA170
FBx_CMD30 CKE#
FBx_CMD31 CAS#

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 N17P_GDDR5_B Upper

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
FG541/FG741 1.0

Date: Tuesday, March 26, 2019 Sheet 34 of 68

5 4 3 2 1
 5 4 3 2 1

+1.8V_AUDIO
DVDD_IO +3VS
+3VALW DVDD_IO Analog power for DACs, ADCs
1 @ 2 0_0402_5%

0.1U_0201_6.3V6-K

2.2U_0402_6.3V6M
RA213

+5VD

+5VA
2 2

CA192
2.2U_0402_6.3V6M

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

CA4
+1.8VS
1 2 2 1 1 1
1 2 0_0402_5%

CA193

CA180

10U 6.3V M X5R 0402

RA216 @

CA179
CA2

18

46

41

40

20
3
D +1.8VALW D

CD@
UA1
2 1 1 2

CPVDD/AVDD2
PVDD2

PVDD1

AVDD1
DVDD

DVDD-IO
RA227 1 2 0_0402_5%
@ 2 SPKR_MUTE#
PDB
14 HDA_BITCLK_AUDIO
HPOUT_L BCLK HDA_BITCLK_AUDIO 16
27
HPOUT-L 15 HDA_SYNC_AUDIO
Close to Pin7 HPOUT_R SYNC HDA_SYNC_AUDIO 16
26
HPOUT-R 47
MIC2_VREFOL 28 JD2 100K_0402_1% 2 @ 1RA205
+5VS +5VA MIC2-VREFO-L @ PLUG_IN +3VS
48 JSENSE RA204 2 1
0_0402_5%
+5VD MIC2_VREFOR 29 JD1
+5VS LA25 MIC2-VREFO-R CA197 2 1 0.1U_0201_6.3V6-K
@
RA7 1 2 0_0603_5% EMC_NS@ 1 @
1 2 SPDIF-OUT/GPIO2/DMIC-DATA34/DMIC-CLK-IN
DMIC_DATA_R @
4 2 1 0_0402_5%
0.1U_0201_6.3V6-K

1U_0402_6.3V6K

BLM15PD600SN1D_2P RA19 DMIC_DATA 38

RING2_CONN 30 GPIO0/DMIC-DATA12
2 2 MIC2-L/RING2 @
5 DMIC_CLK_R 2 1 0_0402_5%
CA20

10U_0603_6.3V6M

10U_0603_6.3V6M

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K
1 1 2 2 RA18
@ RING3_CONN GPIO1/DMIC-CLK DMIC_CLK 38
RA10 1 2 31
CA42

CA194

CA178

CA18

CA19
0_0603_5%
@ MIC2-R/SLEEVE 6
1 1 PC_BEEP 34 I2C-DATA
2 2 1 1 PCBEEP 7
I2C-CLK
+5VA
8
RA203 1 2 10K_0402_5% VDD_STB 33 NC1
5VSTB 9
LINE2-R 35 NC2
LINE2-R 10
LINE2-L 36 NC3
LINE2-L 11

m
NC4
12
NC5

+1.8VS +1.8V_AUDIO CA48 1 2 1U_0402_6.3V6K 23 45 SPK_R+

CBP SPK-OUT-R+
RA225 1 @ 2 0_0402_5% 24 44 SPK_R-
CBN SPK-OUT-R-

co
43 SPK_L-
+1.8VALW SPK-OUT-L-
42 SPK_L+
RA226 1 2 0_0402_5% 2.2U_0402_6.3V6M 2 1 CA41 32 SPK-OUT-L+
MIC2-CAP 13
2.2U_0402_6.3V6M 2 1 CA44 38 DC DET/EAPD
VREF
2.2U_0402_6.3V6M 1 2 CA1 19 16 SDATA_IN 33_0402_5% 2 1 RA16
LDO3-CAP SDATA-IN HDA_SDIN0 16

s.
C 2.2U_0402_6.3V6M 1 2 CA185 21 17 HDA_SDOUT_AUDIO C
LDO2-CAP SDATA-OUT HDA_SDOUT_AUDIO 16
DA4 2.2U_0402_6.3V6M 1 2 CA43 39
EC_MUTE# 1 2 @ SPKR_MUTE# LDO1-CAP 25
49 EC_MUTE# CPVEE
1

Thermal Pad
2

ic
LRB751V-40T1G_SOD323-2 RA43 CA47
10K_0402_5% 1U_0402_6.3V6K

AVSS1

AVSS2
@
RA35 1 2 0_0402_5% @
1
2

ALC3287-CG_MQFN48_6X6

37

22

49

at
CA3
RA5 1 2 4.7K_0402_5% 1 2

0.1U_0201_6.3V6-K
DA1

em
2 RA6 CA40
49 EC_BEEP#
1PC_BEEP1 1 2 1 2 PC_BEEP
3
16 PCH_BEEP
4.7K_0402_5% 0.1U_0201_6.3V6-K
1

LBAT54CW T1G_SOT323-3
@ RA14
@ 10K_0402_5%
@
RA211 1 2 0_0402_5%
2

ch
Speaker
ME@
JSPK1
SPK_R+ RA222 @ SPK_R+_CONN
RA223 1 CD@ 2 15_0402_5% 1 2 0_0603_5% 1
SPK_R- RA221 @ SPK_R-_CONN 1
RA224 1 CD@ 2 15_0402_5% 1 2 0_0603_5% 2

kS
SPK_L+ RA30 @ SPK_L+_CONN 2
HDA_SYNC_AUDIO RA32 1 CD@ 2 15_0402_5% 1 2 0_0603_5% 3
SPK_L- RA34 @ SPK_L-_CONN 3
RA33 1 CD@ 2 15_0402_5% 1 2 0_0603_5% 4
HDA_SDOUT_AUDIO 4
RA1 1 2 0_0402_5%
5
EMC_NS@ 1 2 27_0402_5%HDA_BITCLK_AUDIO GND1
6
CA183

CA184

CA29

CA30

CA31

1500P_50V_K_X7R_0402
CA32

1500P_50V_K_X7R_0402
CA181

1500P_50V_K_X7R_0402
CA182

1500P_50V_K_X7R_0402
RA27 EMC_NS@
220P_0201_25V7-K

220P_0201_25V7-K

220P_0201_25V7-K

220P_0201_25V7-K

@ HDA_SDIN0 GND2
RA4 1 2 0_0402_5% 2 2 2 2
1 1 1 1 ACES_88231-04001
DMIC_CLK
@ DMIC_DATA
1 2 0_0402_5%
22P_0201_258J

22P_0201_258J

33P_0201_50V8-J

33P_0201_50V8-J

EMC@

EMC@

EMC@

EMC@
RA9
B 1 1
oo 1 1
2 2 2 2 B
CD@

CD@

CD@

CD@
EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

100P_0201_25V8J

100P_0201_25V8J

1 1 1 1
CA23

CA24

CA25

CA26

EMC@

EMC_NS@

1 1
1 2 0_0402_5%
CA38

CA39

RA12
EMC_NS@
2 2 2 2
2 2
GND GNDA
Audio Jack
eb

For EMI
ME@
RA228 CA187
JHP1
0_0402_5% 470P_0201_50V7-K
1 @ 2 1 2 @ A_HP_OUTL_R
MIC2_VREFOL RA37 2 1 2.2K_0402_5% RING2_CONN 3
HPOUT_L RA21 1 2 56_0402_5% A_HP_OUTL_R 1 G/M
RING3_CONN RA2 L
RING2_CONN 10K_0402_5%
LINE2-L CA5 1 @ 2 1U_0402_6.3V6K PLUG_IN 5
A_HP_OUTL_R 1 @ 2 5
A_HP_OUTR_R
LINE2-R CA6 1 @ 2 1U_0402_6.3V6K 6
ot

PLUG_IN RA229 CA188 6

0_0402_5% 470P_0201_50V7-K HPOUT_R A_HP_OUTR_R
1 2 1 2 @ A_HP_OUTR_R RA20 1 2 56_0402_5% 2
@ R
AZ5123-01F.R7GR_DFN1006P2X2

AZ5123-01F.R7GR_DFN1006P2X2

AZ5123-01F.R7GR_DFN1006P2X2

AZ5123-01F.R7GR_DFN1006P2X2

AZ5123-01F.R7GR_DFN1006P2X2

MIC2_VREFOR RA38 2 1 2.2K_0402_5% RING3_CONN 4

RA3 M/G
1

1
47P_0201_25V8-J

10K_0402_5%
7

100P_0201_25V8J

100P_0201_25V8J
1 2
EMC_NS@

1 DA5 DA6 DA7 DA8 DA9 @ MS

1

100P 25V J NPO 0201

100P 25V J NPO 0201

1 2 1 1
CA189

CA196

CA195

EMC@

CA190

EMC@

CA191
SINGA_2SJ3095-140111F
N
EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC@

2 @ @
2 1 2 2
2

2
2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2018/09/20 Codec & CR_RTS5199

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
D 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FG541/FG741
Date: Tuesday, March 26, 2019 Sheet 35 of 69
5 4 3 2 1
 5 4 3 2 1

D D

m
co
C C

s.
ic
at
em
ch
kS
B B

oo
eb
ot
N

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2018/09/20 Cardreader

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FG541/FG741
Date: Tuesday, March 26, 2019 Sheet 36 of 69
5 4 3 2 1
 5 4 3 2 1

+3VALW +3VALW_TPM
D D

RTPM1 1 TPM@ 2 0_0603_5%

10U_0603_6.3V6M

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201
2 2 2 2

CTPM1

CTPM3 TPM@

CTPM4 TPM@

C257
@ @
1 1 1 1
+3VALW_TPM

+3VALW_TPM

2
2

1
R2103 R2104

m
R2102 10K_0402_5% R505 @ 10K_0402_5%

22
UTPM1

1
10K_0402_5% TPM@ @ 0_0402_5%
TPM@

VDD3

VDD2

NCI/VDD1
1

1
1

2
co
18
15 TPM_SPI_PIRQ# PIRQ# 3
NCI1 4
21 NCI2 5
18 TPM_SPI_MOSI 24 MOSI NCI3 10
18 TPM_SPI_MISO MISO NCI4 11
NCI5 12

s.
NCI6 13
20 NCI7 14
18 TPM_SPI_CS# CS# VDD/NCI8 15
19 NCI9 16

ic
18 TPM_SPI_CLK SCLK GND/NCI10 25
PLT_RST# 17 NCI11 26
RST# NCI12 27
C C
6 NCI13 28

at
GPIO NCI14 31
TPM_PP 7 NCI15
PP

29 R1124 1 @ 2 0_0402_5%

em
NC1 PLT_RST# 18,28,41,42,45,49

1
30
NC2

GND1

GND2

GND3

GND4

GND5
R1123
@ 0_0402_5%

SLB9670VQ2.0FW7.61_VQFN32_5X5

23

32

33
TPM@

ch
kS
oo
eb

B B
ot
N

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2018/09/20 TPM

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
FG541/FG741 1.0

Date: Tuesday, March 26, 2019 Sheet 37 of 69

5 4 3 2 1
 5 4 3 2 1

LCD POWER CIRCUIT

+3VS
+LCDVDD +LCDVDD_CON CMOS Camera +3VS Need short +3VS_CMOS_R
J1 @
1 2
U5 1 2
5 1 @ W=60mils
R263 1 2 0_0805_5%
IN OUT W=40 mils JUMP_43X39

RF_NS@
1 2
GND +3VS_CMOS

0.1u_0201_10V6K

33P_0402_50V8J
EDP_ENVDD 4 3 LP2301ALT1G_SOT23-3
C1

4.7U_0402_6.3V6M
1 1 1
0.1u_0201_10V6K EN OCB @ @ W=40mils
Q7 3 1 R3 1 2 0_0603_5%

D
2 SY6288C20AAC_SOT23-5

0.01U_0201_10V6K
@

C121

@
2 2 2 1 1 1 1@
C5 C3 F4
U5 EN PIN VIH MIN 1.5V

G
C4

C122

C123

2
0.1u_0201_10V6K 0.1u_0201_10V6K 1 2
10U_0603_6.3V6M
@ CD@
2 2 2 0.5A_32V_ERBRD0R50X 2

C6
CMOS_ON# R5 1 @ 2 @
V20B+ +LEDVDD For RF 100K_0402_5%
1 1
1 2
2A 80 mil C9 C10
2A 80 mil R17 @ 0_0805_5%
0.01U_0201_25V6-K 0.1u_0201_10V6K
EMC_NS@ @

EMC@
CD@
2 2

4.7U_0805_25V6-K

0.1U_0201_25V6-K
F3 1 1
For EMI
D
1 2 Close to R5 D

2 2
3A_32V_0497003PKRHF

C14

C15
EMI Request

R10565 1 2 0_0402_5% EDP_ENVDD

14 PCH_EDP_ENVDD R296 1 @ 2 0_0402_5% CMOS_ON#
20 PCH_CMOS_ON#
JEDP1
R10566 1 2 0_0402_5% +LEDVDD
1
28 GPU_EDP_ENVDD 1 2 2 1
@ R297 @ 0_0402_5%
49 EC_CMOS_ON# 3 2
4 3
EDP_TX0+ 4
1

5
R1 EDP_TX0- 6 5
100K_0402_5% 7 6
EDP_TX1+ 8 7
EDP_TX1- 9 8
9
2

+3VS 10
EDP_AUX 11 10
EDP_AUX# 12 11
13 12
13

2
DISPOFF# 14
R9 R8 15 14
100K_0402_1% 100K_0402_1% @ INVT_PWM 16 15
17 16
@ 18 17
18

1
eDP_HPD_CON 19

m
GSYNC# 20 19
EDP_AUX_R R10573 1 @ 2 0_0402_5% EDP_AUX 21 20
EDP_AUX#_R R10574 1 +LCDVDD_CON 21
@ 2 0_0402_5% EDP_AUX# 22
23 22
+3VS 23
24
35 DMIC_DATA 24

2
35 DMIC_CLK 25
R15 R13 26 25
26

co
100K_0402_1% 100K_0402_1% @ 27
@ 2 0_0402_5% USB20_P8_R 27
@ R182 1 28
19 USB20_P8 @ 28
R183 1 2 0_0402_5% USB20_N8_R 29
19 USB20_N8 29

1
CPU_EDP_TX0+ EDP_CPU@ C19 1 2 .1U_0402_10V6-K EDP_TX0+ 30
8 CPU_EDP_TX0+ +3VS_CMOS 30
CPU_EDP_TX0- 1 2 .1U_0402_10V6-K EDP_TX0- 31
8 CPU_EDP_TX0-
EDP_CPU@ C16 W=40mils 32 G1
CPU_EDP_TX1+ EDP_TX1+ 1 G2
EDP_CPU@ C17 1 2 .1U_0402_10V6-K C24
8 CPU_EDP_TX1+ CPU_EDP_TX1- 1 2 .1U_0402_10V6-K EDP_TX1-
EDP_CPU@ C18 .047U_0201_6.3V6K DRAPH_FC5AF301-3181H
8 CPU_EDP_TX1-
EMC_NS@ ME@
CPU_EDP_AUX EDP_CPU@ C20 1 2 .1U_0402_10V6-K EDP_AUX 2

s.
8 CPU_EDP_AUX CPU_EDP_AUX# 1 2 .1U_0402_10V6-K EDP_AUX#
EDP_CPU@ C21
8 CPU_EDP_AUX#

EMI request
IFPD_L0+ @ C10139 1 2 .1U_0402_10V6-K EDP_TX0+
26 IFPD_L0+ IFPD_L0- EDP_TX0-
@ C10138 1 2 .1U_0402_10V6-K

ic
26 IFPD_L0-
IFPD_L1+ @ C10140 1 2 .1U_0402_10V6-K EDP_TX1+
26 IFPD_L1+ IFPD_L1- EDP_TX1-
@ C10141 1 2 .1U_0402_10V6-K
26 IFPD_L1-
C IFPD_AUX+ EDP_AUX C
@ C10143 1 2 .1U_0402_10V6-K
26 IFPD_AUX+ IFPD_AUX- EDP_AUX#
@ C10142 1 2 .1U_0402_10V6-K
26 IFPD_AUX-

at
+3VS
+1.8VS_AON
2

2
RV1253 RV1282
+3VALW 2.2K_0402_5% 10K_0402_5%
EDP_OPT@

em
+3VALW
+3VS
1

R10569 1 2 0_0402_5% ENBKL

1
2

RV1252 @ @
2

2
10K_0402_5% RV1283
+LCDVDD GPU_FRAME_LOCK# 28
R10 EDP_OPT@ 10K_0402_5%
4.7K_0402_5%
3

@ EDP_OPT@
1

3
QV37B
D2
1

1
5 PJT7838_SOT363-6 QV38B
ENBKL 1 2

D2
R11 @ G2 @

1
5 PJT7838_SOT363-6
0_0402_5% G2
RV1258
S2

10K_0402_5% @

ch S2
1 @ 2 0_0402_5%
R12 DISPOFF#
4
6

49 BKOFF# EDP_OPT@

4
6
QV37A
D1

GPU_EDP_ENBKL 2 @
1 2 PJT7838_SOT363-6 QV38A

D1
R14 0_0402_5% ENBKL 28 GPU_EDP_ENBKL G1 2
14 PCH_EDP_ENBKL ENBKL 49 GSYNC# PJT7838_SOT363-6
G1
1

S1

EDP_OPT@
@

S1
R10568
100K_0402_5%
1

Vgs(th)≤1.0V
1

1
kS
R16
2

100K_0402_5%

Vgs(th)≤1.0V
2

+3VS
oo
2

RV1248
+3VALW 2.2K_0402_5%
EDP_OPT@
1

+3VS R10570 1 2 0_0402_5% INVT_PWM EMI request

2

RV1247 @
10K_0402_5% DMIC_CLK INVT_PWM
DISPOFF#
EDP_OPT@
2

eb

R18

470P_0201_50V7-K

470P_0201_50V7-K
100P_0201_25V8J
3

EDP_OPT@
1K_0402_5%

EMC_NS@

EMC_NS@
1

QV36B 1 1 1
D2

@
EMC_NS@

5 PJT7838_SOT363-6
G2
1

1 2 INVT_PWM 2 2 2
S2

R19 0_0402_5%
14 PCH_EDP_PWM
C11

C12

C13
B B
4
6

EDP_OPT@
1

QV36A
D1

R20 GPU_EDP_PWM 2
100K_0402_5% 28 GPU_EDP_PWM G1 PJT7838_SOT363-6
ot
1

S1

EDP_OPT@
2

R10567
100K_0402_5%
1

Vgs(th)≤1.0V
2

+1.8VS_AON
For EMI
PCH_EDP_HPD R10223 1 2 eDP_HPD_CON L12 EMC_NS@
0_0402_5% USB20_N8 1 2 USB20_N8_R
15 PCH_EDP_HPD
1

1 2
R317
update by SF 10K_0402_5% USB20_P8 4 3 USB20_P8_R
1

EDP_OPT@ 4 3
R10400 20181023 EXC24CH900U_4P
2

100K_0402_5%
IFPD_HPD R10571 1 2 0_0402_5%
28 IFPD_HPD
2

@
EDP_OPT@
Q181
MMBT3904WH_SOT323-3
1

C
2 R318 1 2 100K_0402_5% R319 1 2 0_0402_5% R10572 1 @ 2 0_0402_5%eDP_HPD_CON
B EDP_OPT@
E EDP_OPT@
3

1
1

C366 1
R324 C367
220P_0402_50V7K
100K_0402_5% 220P_0402_50V7K
EDP_OPT@
EDP_OPT@ 2 EDP_OPT@
2
2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2018/09/20 eDP/CMOS/Touch screen

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FG541/FG741
Date: Tuesday, March 26, 2019 Sheet 38 of 69
5 4 3 2 1
 5 4 3 2 1

+1.8VS_AON

2 @ 1 0_0402_5%
R10498

EXC24CH500U_4P

1
RRE59
10K_0402_5%
HDMI1_TX0- CRE261 2 0.1u_0201_10V6K HDMI1_TX0-_C 4 3 HDMI1_TX0-_R
26 HDMI1_TX0- 4 3

HDMI D0 HDMI1_TX0+ CRE251 2 0.1u_0201_10V6K HDMI1_TX0+_C 1 2 HDMI1_TX0+_R

26 HDMI1_TX0+ 1 2

2
L2 EMC_NS@
@
R10505 2 1 0_0402_5% IFPE_HPD
28 IFPE_HPD

QRE3
MMBT3904W H_SOT323-3

1
C
@ 2 RRE57 1 2 100K_0402_5% RRE58 1 2 0_0402_5% HDMI1_HPD_CON
R10499 2 1 0_0402_5%
B
EXC24CH500U_4P E

3
HDMI1_TX1- CRE281 2 0.1u_0201_10V6K HDMI1_TX1-_C 4 3 HDMI1_TX1-_R 1

1
D 26 HDMI1_TX1- 4 3 CRE9 D
RRE56 220P_0402_50V7K RRE62
HDMI D1 HDMI1_TX1+ 2 0.1u_0201_10V6K HDMI1_TX1+_C HDMI1_TX1+_R 100K_0402_5% 100K_0402_5%
26 HDMI1_TX1+ CRE271 1 2 2
1 2
L3 EMC_NS@

2
2 @ 1 0_0402_5%
R10504

2 @ 1 0_0402_5%
R10500
+3VS
EXC24CH500U_4P
HDMI1_TX2- CRE301 2 0.1u_0201_10V6K HDMI1_TX2-_C 4 3 HDMI1_TX2-_R
26 HDMI1_TX2- 4 3
HDMI D2
HDMI1_TX2+ CRE291 2 0.1u_0201_10V6K HDMI1_TX2+_C 1 2 HDMI1_TX2+_R
26 HDMI1_TX2+ 1 2

HPD
L4 EMC_NS@
@
R10503 2 1 0_0402_5%

1
RRE61

2
2 @ 1 0_0402_5% 1M_0402_5%
R10501

G
EXC24CH500U_4P

2
HDMI_HPD HDMI1_HPD_CON

1
HDMI1_TXC- CRE321 2 0.1u_0201_10V6K HDMI1_CLK-_C 4 3 HDMI1_CLK-_R 15 HDMI_HPD
26 HDMI1_TXC- 4 3

D
HDMI1_TXC+ 2 0.1u_0201_10V6K HDMI1_CLK+_C HDMI1_CLK+_R
HDMI CLK 26 HDMI1_TXC+ CRE311 1
1 2
2 QRE6
L5 PJA138K_SOT23-3
EMC_NS@
@
R10502 2 1 0_0402_5%

m
co
HDMI1_TX0+_C 1 2 499_0402_1% HDMI1_TX0+_B @
R31 R10426 1 2 0_0402_5%

HDMI1_TX0-_C 1 2 499_0402_1% HDMI1_TX0-_B @

R32 R10427 1 2 0_0402_5%

HDMI1_TX1+_C 1 2 499_0402_1% HDMI1_TX1+_B @

R33 R10428 1 2 0_0402_5%

HDMI1_TX1-_C HDMI1_TX1-_B @
R34 1 2 499_0402_1% R10429 1 2 0_0402_5%
+5VS +5VS_HDMI1_F +5VS_HDMI1

s.
HDMI1_TX2+_C HDMI1_TX2+_B @
C R37 1 2 499_0402_1% R10430 1 2 0_0402_5% QRE4 C
LP2301ALT1G_SOT23-3
HDMI1_TX2-_C 1 2 499_0402_1% HDMI1_TX2-_B @
R38 R10431 1 2 0_0402_5% F2
1 3 1 2

S
HDMI1_CLK+_C 1 2 499_0402_1% HDMI1_CLK+_B @
R29 R10432 1 2 0_0402_5%
1.1A_8V_1206L110THYR

ic
HDMI1_CLK-_C 1 2 499_0402_1% HDMI1_CLK-_B @
R30 R10433 1 2 0_0402_5%

G
2

2
1
CRE11 @ R10539 R10540 @
.1U_0402_10V6-K 0_0805_5% 0_0805_5%
51 SUSP
2

1
D Q13 D4321 D4322

1
at
2 RB751V-40_SOD323-2 RB751V-40_SOD323-2
+3VS @ @
G 2N7002KW _SOT323-3

1
NV suggestion
R42 1 @ 2 RRE15 RRE16
2.2K_0402_5% 2.2K_0402_5%
100K_0402_5%

em

2
JHDMI2 ME@

18 15 HDMI1_CLK_CON
+5V_Power SCL 16 HDMI1_DAT_CON
SDA
HDMI1_TX0+_R R10319 1 2 5.1_0402_1% HDMI1_TX0+_CON 7
HDMI1_TX0-_R R10320 1 2 5.1_0402_1% HDMI1_TX0-_CON 9 TMDS_Data0+ 13
HDMI1_TX1+_R R10321 1 2 5.1_0402_1% HDMI1_TX1+_CON 4 TMDS_Data0- CEC 17
HDMI1_TX1-_R R10322 1 2 5.1_0402_1% HDMI1_TX1-_CON 6 TMDS_Data1+ DDC/CEC_Ground 19 HDMI1_HPD_CON
HDMI1_TX2+_R R10323 1 2 5.1_0402_1% HDMI1_TX2+_CON 1 TMDS_Data1- Hot_Plug_Detect
HDMI1_TX2-_R 1 2 HDMI1_TX2-_CON 3 TMDS_Data2+
Close to JHDMI1 R10324 5.1_0402_1%

ch
TMDS_Data2-
D3 D6 D7 8 14
5 TMDS_Data0_Shield Utility
HDMI1_HPD_CON 1 1 10 9 HDMI1_HPD_CON HDMI1_TX0-_R 1 1 10 9 HDMI1_TX0-_R HDMI1_TX1-_R 1 1 10 9 HDMI1_TX1-_R TMDS_Data1_Shield
2
TMDS_Data2_Shield
HDMI1_DAT_CON 2 2 9 8 HDMI1_DAT_CON HDMI1_TX0+_R 2 2 9 8 HDMI1_TX0+_R HDMI1_TX1+_R 2 2 9 8 HDMI1_TX1+_R
20
11 GND1 21
HDMI1_CLK_CON 4 4 7 7 HDMI1_CLK_CON HDMI1_CLK-_R 4 4 7 7 HDMI1_CLK-_R HDMI1_TX2-_R 4 4 7 7 HDMI1_TX2-_R TMDS_Clock_Shield GND2
HDMI1_CLK+_R R10325 1 2 5.1_0402_1% HDMI1_CLK+_CON 10 22
HDMI1_CLK-_R R10326 1 2 5.1_0402_1% HDMI1_CLK-_CON 12 TMDS_Clock+ GND3 23
+5VS_HDMI1 5 5 6 6 +5VS_HDMI1 HDMI1_CLK+_R 5 5 6 6 HDMI1_CLK+_R HDMI1_TX2+_R 5 5 6 6 HDMI1_TX2+_R

kS
TMDS_Clock- GND4

3 3 3 3 3 3

8 8 8 ALLTO_C128S9-K1935-L
For EMC
AZ1045-04F_DFN2510P10E-10-9 AZ1045-04F_DFN2510P10E-10-9 For EMC AZ1045-04F_DFN2510P10E-10-9
EMC_NS@ EMC_NS@ EMC_NS@
B
oo B
eb

VGA_MAIN_3V_1.8V +1.8VS_AON VGA_MAIN_3V_1.8V +1.8VS_AON

2

ot

R10537 R10538 R10535 R10536

@ 0_0402_5% @ 0_0402_5% @ 0_0402_5% @ 0_0402_5%
1

AUX
N
1

NV suggestion
RRE55 RRE54
10K_0402_5% 10K_0402_5%
2
G1

HDMI1_DAT_CON 6 1
D1 S1 HDMI1_DAT 26

PJT7838_SOT363-6
Q37A
5
G2

HDMI1_CLK_CON 3 4
D2 S2 HDMI1_CLK 26

Vgs(th)≤1V PJT7838_SOT363-6
Q37B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2018/09/20 HDMI_CONN

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
D 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FG541/FG741
Date: Tuesday, March 26, 2019 Sheet 39 of 69
5 4 3 2 1
 5 4 3 2 1

D D

m
co
C C

s.
ic
at
em
ch
kS
B B
oo
eb
ot
N

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2018/09/20 P35-Blank

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
FG541/FG741 1.0

Date: Tuesday, March 26, 2019 Sheet 40 of 69

5 4 3 2 1
 5 4 3 2 1

@ XDP_TCK
JTAGX R591 1 2 0_0402_5%
16 JTAGX

PCH_TMS XDP_TMS 18 SPI_WP#

R593 1 @ 2 0_0402_5%
TABLE : CPU ITP DEBUG REPORT 16 PCH_TMS
D D

1
PCH_TDI R594 1 @ 2 0_0402_5% XDP_TDI
16 PCH_TDI
R597
Individual DCI 2.0 CPU_TRST# R595 1 @ 2 0_0402_5% XDP_TRST# @ 1K_0402_1%
No use Port w/o connector 22 CPU_TRST#
PCH_TDO R596 1 @ 2 0_0402_5% XDP_TDO
16 PCH_TDO

2
R591 NO ASM NO ASM ASM PCH_PRDY# R657 1 @ 2 0_0402_5% XDP_PRDY#
22 PCH_PRDY#
R593 NO ASM NO ASM ASM PCH_PREQ# R658 1 @ 2 0_0402_5% XDP_PREQ# Reference Intel document 546884 SKL PHG
22 PCH_PREQ#
R594 NO ASM NO ASM ASM
R595 NO ASM NO ASM ASM
R596 NO ASM NO ASM ASM
R657 NO ASM NO ASM ASM
R658 NO ASM NO ASM ASM Delete R93

m
2
VCCST
R102 NO ASM ASM NO ASM RC176

co
51_0402_1%
R597 NO ASM ASM NO ASM
DCI@ Mount RC176 to enable
R9907 NO ASM ASM ASM DCI function

1
2

2
R168 R169
JXDP1 NO ASM ASM NO ASM 51_0402_1% 51_0402_1%

s.
@ @
C70 NO ASM ASM NO ASM

1
R96 NO ASM ASM NO ASM

ic
R101 NO ASM ASM NO ASM XDP_TMS
PCH_TDI R217 1 @ 2 0_0402_5% TDI
C
R9909 NO ASM ASM ASM XDP_TDI +1.05VALW +3VALW +1.05VALW C
PCH_TDO R218 1 @ 2 0_0402_5% TDO
R9910 NO ASM ASM ASM

at
VCCST
R9916 NO ASM ASM ASM
@ 2
R99 NO ASM ASM ASM

em
C70
R9912 NO ASM ASM ASM DCI@

2
0.1U_0402_25V6
R233 R4681 1
R9934 NO ASM ASM ASM 51_0402_1% @ 2.2K_0402_5% @ 1K_0402_5%
R234
R9930 NO ASM ASM ASM

1
R9931 NO ASM ASM ASM R99 1 @ 2 0_0402_5%

ch
16 PCH_TCK @
R219 1 2 0_0402_5% PAD 1 @
R9932 NO ASM ASM ASM 6 XDP_TCK IT21
PCH_TMS R220 1 @ 2 0_0402_5%
R9933 NO ASM ASM ASM R221 1 @ 2 0_0402_5% PAD 1 @
6 XDP_TMS 1 @ 2 1 IT22
R222 0_0402_5% TDI PAD @
6 XDP_TDI @ IT23
R223 1 2 0_0402_5% PAD 1 @

kS
6 XDP_TRST# 1 @ 2 1 IT24
6 XDP_TDO R224 0_0402_5% TDO PAD @
IT25
LOGIC PAD 1 @
16 SYS_RESET# @ IT26
R225 1 2 1K_0402_5% PAD 1 @
18,28,37,42,45,49 PLT_RST# IT27
R226 1 2 1K_0402_5%
TABLE : PCH ITP DEBUG REPORT 16,49 PCH_PWROK
@ PAD 1 @
16 ITP_PMODE IT16
oo
R228 1 @ 2 0_0402_5% PAD 1 @
No use Individual DCI 2.0 16,49 SYS_PWROK IT29
Port w/o connector EC_RSMRST# @
R229 1 2 1K_0402_5% PAD 1 @
16,49 EC_RSMRST# IT30
R230 1 DCI@ 2 0_0402_5% PAD 1 @
R93 NO ASM ASM NO ASM
eb

6 CFG3 IT31
need change to 1.5K refer CRB
JXDP1 NO ASM ASM NO ASM place within 500mil of T-connection
B R9917 NO ASM ASM NO ASM B

R231 1 @ 2 0_0402_5% PAD 1 @

R101 NO ASM ASM NO ASM 6 XDP_PRDY# @ IT32
ot

R232 1 2 0_0402_5% PAD 1 @

6 XDP_PREQ# IT33
R9908 NO ASM ASM NO ASM
R9911 NO ASM ASM NO ASM
R9913 NO ASM ASM NO ASM
N

Change XDP CONN to Test Point

R9915 NO ASM ASM NO ASM HLZ SVD 0527
+3V_SPI
Ref Y530 add 1207SF +3VALW

LOGIC +3VS
GPP_B18_NO_REBOOT

1
* 0 = Disable ¨No Reboot
〃

mode. (Default) R10420

2
1 = Enable ¨No Reboot
〃

mode (PCH will disable the 2.2K_0402_5%

TABLE : Functional Strap TCO R10419
@ 1K_0402_5%
Timer system reboot feature). This function is useful @
1

GPP_B18/GSPI0_MOSI (No Reboot) R563

2
when running ITP/XDP.
R563

1
HIGH Enable "No Reboot" Mode ASM 1K_0402_5% Place near PCH PAD 1 @
@ 18 SPI_SI_XDP IT15
LOW Disable "No Reboot" Mode (Default ) NO ASM LOGIC PAD 1 @
16,49 PBTN_OUT# IT17
2

GPP_B18_NO_REBOOT
GPP_B18_NO_REBOOT 20

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2018/09/20 Blank

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
FG541/FG741 1.0

Date: Tuesday, March 26, 2019 Sheet 41 of 69

5 4 3 2 1
 5 4 3 2 1

+3VALW TO +3VALW_LAN
+3VALW_LAN rising time (10%~90%):
+3VALW +3VALW_LAN
0.5ms＜spec＜100ms +3VALW_LAN +LAN_VDDREG
Need short
JL1 1 2 @ width : 40 mils RL1 1
@
2 0_0603_5%
1 2
JUMP_43X79
D 1 1 D
+3VALW LP2301ALT1G_SOT23-3 CL2

0.1u_0201_10V6K

0.1u_0201_10V6K
4.7U_0402_6.3V6M

4.7U_0402_6.3V6M
CL6 CL7 CL1 0.1u_0201_10V6K
3 1 @ CL4 1 CL5 1 1 1
4.7U_0402_6.3V6M
Q14

0.01U_0201_10V6K
2 2

0.1u_0201_10V6K
RL2 1 CL8 CL9 1 2 2 2 2

G
100K_0201_5% @ @ @

2
@
@ 2
2

2
RL3 1 @ 2
20,49 LAN_PWR_ON#
1/20W_47K_5%_0201
Close to Pin11 Close to Pin32 Close to Pin11 Close to Pin32
+3VALW_LAN +3VS

+3VALW_LAN

2
G
RL4 @

2
@
manual change the Codec PN to RTL8111H-CG_QFN32_4X4 10K_0201_5%
QL1
@

co
RL5 UL1

1
10K_0201_5% LAN_CLKREQ#_R 1 3
LAN_CLKREQ# 17

S
1
2N7002KW_SOT323-3
RL7 1 @ 2 0_0201_5% PCIE_WAKE#_R
16,45,49 PCIE_WAKE#

s.
RL6 1 @ 2 0_0201_5%
45,49 LAN_WAKE#
33 RL18 1 @ 2 0_0201_5%
32+3VALW_LAN GND 16 CLK_PCIE_LAN#
C
1 2 31 AVDD33_2 REFCLK_N 15 CLK_PCIE_LAN CLK_PCIE_LAN# 17 C
RL8 RSET

ic
30+LAN_VDD10 RSET REFCLK_P 14 PCIE_PTX_C_DRX_N14 CLK_PCIE_LAN 17
2.49K_0402_1%
29LAN_XTALO AVDD10 HSIN 13 PCIE_PTX_C_DRX_P14 PCIE_PTX_C_DRX_N14 14
28LAN_XTALI CKXTAL2 HSIP 12 LAN_CLKREQ#_R PCIE_PTX_C_DRX_P14 14
@ 1 CKXTAL1 CLKREQB

at
+3VS TL3 27 11 +3VALW_LAN
LAN_PWR_ON# RL12 1 @ 2 0_0201_5% LAN_DISABLE# 26 LED0 AVDD33_1 10 LAN_MDI3-
1 25 LED1/GPIO MDIN3 9 LAN_MDI3+ LAN_MDI3- 43
TL4
LED2 MDIP3 LAN_MDI3+ 43
1

+LAN_REGOUT 24 8 +LAN_VDD10
@ +LAN_VDDREG 23 REGOUT AVDD10_2 7 LAN_MDI2-

em
RL9
+LAN_VDD10 22 VDDREG MDIN2 6 LAN_MDI2+ LAN_MDI2- 43
1K_0402_1%
PCIE_WAKE#_R 21 DVDD10 MDIP2 5 LAN_MDI1- LAN_MDI2+ 43
20 LANW AKEB MDIN1 4 LAN_MDI1+ LAN_MDI1- 43
ISOLATE#
ISOLATEB MDIP1 LAN_MDI1+ 43
2

PLT_RST# 19 3 +LAN_VDD10
18,28,37,41,45,49 PLT_RST# 2 0.1u_0201_10V6K PCIE_PRX_C_DTX_N14 18 PERSTB AVDD10_1 LAN_MDI0-
14 PCIE_PRX_DTX_N14 CL10 1 2
1 @ 2 0_0201_5% LAN_PWR_ON# 2 0.1u_0201_10V6K PCIE_PRX_C_DTX_P14 17 HSON MDIN0 LAN_MDI0+ LAN_MDI0- 43
ISOLATE# RL10 14 PCIE_PRX_DTX_P14 CL11 1 1
HSOP MDIP0 LAN_MDI0+ 43

ch
CL10 close to Pin18
1

RL11 CL11 close to Pin17

15K_0201_1%
@

kS
2

RTL8111GUL-CG QFN 32P

@
oo
B B
eb

LAN_XTALI
For RTL8111GUL(SWR mode, reserved)
LAN_XTALO_R 1 2 LAN_XTALO For RTL8111H (LDO mode)
RL21 1K_0402_5% +LAN_VDD10
YL1 LL1 1 2 8111GUL@
ot

2.2UH_NLC252018T-2R2J-N_5%
1 4
OSC1 GND2 +LAN_REGOUT RL20 1 2 8111H@
2 3 0_0805_5%
GND1 OSC2
N

1 8111H@ 1 1 1 1 1 1 1 1
1 1 CL15
CL12 25MHZ_10PF_7V25000014 CL13 CL33 CL16 CL17 CL18 CL19 CL20 CL21 CL22
15P_0402_50V8J 15P_0402_50V8J 1124SF Add CL33 0.1u_0201_10V6K
4.7U_0402_6.3V6M
0.1u_0201_10V6K 0.1u_0201_10V6K 0.1u_0201_10V6K 0.1u_0201_10V6K 0.1u_0201_10V6K 1U_0402_6.3V6K 0.1u_0201_10V6K
2 2 2 2 2 2 2 2 2
2 2
close to pin

Close to Pin3, 8, 22, 30 Close to Pin22(Reserved)

Layout Note: LL1 must be
+LAN_VDD10
within 200mil to Pin24,
21180125SF Add D65 For EMC CL15,CL16 must be within
200mil to LL1
Need change to AZ5815/ +LAN_REGOUT: Width =60mil
1

EMC_8111H@
D65 SC40000BM00, S DIO_ESD
1

A AZ5825-01F.R7GR DFN1006P2E A
AZ5815-01F.R7GR DFN1006P2E, A.2,EG531
2
2

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2018/09/20 LAN_RTL8111H_CG

D65 only change P/N from SC40000BM00 to SC400007X00 2019/1/23
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
FG541/FG741 1.0

Date: Tuesday, March 26, 2019 Sheet 42 of 69

5 4 3 2 1
 5 4 3 2 1

0907SF change DL1/DL2 to

S DIO(BR) AZ1215-04S.R7G SOT23-6L TCT 24
TL1
MCT1
@
TCT1
1 MCT

PN:SC300005900 for 8111H 42 LAN_MDI0+

LAN_MDI0+ 23
MX1+ TD1+
2 LAN_MDO0+

LAN_MDI0- 22 3 LAN_MDO0-
42 LAN_MDI0- MX1- TD1-

1
D EMC_GST@ D
21 4 MCT RL17
MCT2 TCT2 20_0603_5%
DL1 & DL2 only change P/N from

1
LAN_MDI1+ 20 5 LAN_MDO1+
42 LAN_MDI1+ MX2+ TD2+ DL3

1
SC300006100 to SC300006N00 2019/1/23

2
LAN_MDI1- 19 6 LAN_MDO1- PDT5061_DO-214AA
42 LAN_MDI1- MX2- TD2- EMC_GST@
18 7 MCT

2
MCT3 TCT3 EMC

2
LAN_MDI2+ 17 8 LAN_MDO2+
DL1 42 LAN_MDI2+ MX3+ TD3+
LAN_MDI2- 16 9 LAN_MDO2-
42 LAN_MDI2- MX3- TD3-
LAN_MDI3+ 4 3 LAN_MDI2-
15 10 MCT
MCT4 TCT4
1 1
LAN_MDI3+ 14 11 LAN_MDO3+ CL32 CL25

m
42 LAN_MDI3+ MX4+ TD4+
5 2 0.022U_0603_50V7K 1000P_1206_2KV7-K
LAN_MDI3- 13 12 LAN_MDO3- EMC_GST@ EMC_GST@
42 LAN_MDI3- MX4- TD4- 2 2
1 EMC

co
CL24
0.01U_0201_25V6-K BOTH_GST5009 LF
LAN_MDI3- 6 1 LAN_MDI2+
EMC_GST@
2
AZ1513-04S.R7G SOT23

s.
C EMC_8111H@ EMC C

ic
CHASSIS1_GND

at
DL2

LAN_MDI1+ 4 3 LAN_MDI0-
Add TL2 co-lay TL1 1009SF

em
TL2 @
5 2 TCT 24 1 MCT
TCT1 GND
LAN_MDI0+ 23 2 LAN_MDO0+
TD1+ MX1+ JRJ1 ME@

ch
LAN_MDI0- 22 3 LAN_MDO0- 12
LAN_MDI1- 6 1 LAN_MDI0+ TD1- MX1- GND_4
21 4 11
AZ1513-04S.R7G SOT23 TCT2 NC1 GND_3

kS
EMC_8111H@ LAN_MDI1+ 20 5 LAN_MDO1+ 10
TD2+ MX2+ LAN_MDO0+ 1 GND_2
LAN_MDI1- 19 6 LAN_MDO1- TX_DA+ 9
TD2- MX2- LAN_MDO0- 2 GND_1
18 7 TX_DA-
oo
B TCT3 NC2 LAN_MDO1+ 3 B
LAN_MDI2+ 17 8 LAN_MDO2+ RX_DB+
Place Close to TL1 TD3+ MX3+ LAN_MDO2+
CHASSIS1_GND
4
LAN_MDI2- 16 9 LAN_MDO2- BI_DC+
EMC TD3- MX3-
eb

LAN_MDO2- 5
15 10 BI_DC-
TCT4 NC3 LAN_MDO1- 6
LAN_MDI3+ 14 11 LAN_MDO3+ RX_DB-
1204SF update, TD4+ MX4+ LAN_MDO3+ 7
ot

LAN_MDI3- 13 12 LAN_MDO3- BI_DD+

4 R-Short place on DC-IN CONN & LAN CONN, TD4- MX4- LAN_MDO3- 8
BI_DD-
2 R-Short place on LAN CONN & HDMI CONN AJOHO_N-8660GR
N

ALLTO_C10235-10839-L

RL14 1
@
2 0_0603_5% If stuff TL2,, J13 need short 8/16 Update RJ45 P/N DC021608091 wei
1 @ 2 J13 @
RL15 0_0603_5%
MCT 1 2
@ 1 2
RL16 1 2 0_0603_5%
JUMP_43X79
1 @ 2
RL22 0_0603_5%

A CHASSIS1_GND A
1 @ 2
RL23 0_0603_5%

1 @ 2
RL24 0_0603_5% Title
EMC
Security Classification LC Future Center Secret Data
Issued Date 2015/08/20 Deciphered Date 2018/09/20 LAN_Transformer
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
CHASSIS1_GND AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
B
FG541/FG741 1.0

Date: Tuesday, March 26, 2019 Sheet 43 of 69

5 4 3 2 1
 5 4 3 2 1

R175 1 @ 2 0_0402_5% REMOTE1+

Close to U1 REMOTE+_R R176 1 @ 2 0_0402_5% REMOTE2+ REMOTE1+

Near GPU&VRAM REMOTE2+
Near CPU core
1

1
REMOTE+_R 1 C46 C

1
1 C45 C 100P_0201_25V8J 2 Q16
C44 REMOTE-_R R177 1 @ 2 0_0402_5% REMOTE2- 100P_0201_25V8J 2 Q15 @ B MMBT3904WH_SOT323-3
2200P_0201_25V7-K @ B MMBT3904WH_SOT323-3 2 E @

3
@ 2 E @ REMOTE2-

3
2 REMOTE-_R R178 1 @ 2 0_0402_5% REMOTE1- REMOTE1-

+3VALW
D REMOTE+/-_R, REMOTE1+/-, REMOTE2+/-: +3VALW D

Trace width/space:10/10 mil Near CPU

Trace length:<8"

1
R36
13.7K_0402_1% R25
13.7K_0402_1%
SMSC thermal sensor

2
NTC_V1
placed near DIMM

2
NTC_V2

1
+3VS R287
U1 @ 100K_0402_1%_NCP15WF104F03RC R288
1 8 EC_SMB_CK2 100K_0402_1%_NCP15WF104F03RC
VDD SCL EC_SMB_CK2 16,28,49

2
REMOTE+_R 2 7 EC_SMB_DA2

m
1 D+ SDA EC_SMB_DA2 16,28,49

2
C47

2
0.1u_0201_10V6K REMOTE-_R 3 6
@ D- ALERT# R184
2

co
+3VS R51 2 @ 1 4 5 @ 0_0402_5%
10K_0402_5% T_CRIT# GND
NCT7718W_MSOP8

1
Address 1001_101xb

s.
ic
for layout optimized, change the EC_AGND to GND
C C

at
+5VLP +5VLP
+5VLP

em
HW thermal sensor

2
R252 R253 +3VALW
1
C7 21.5K_0402_1% 21.5K_0402_1%
0.1u_0201_10V6K @
@
@

ch
1

1
2

1
U4 @ R10530
1 8 TMSNS1 R196 1 @ 2 0_0402_5% NTC_V1 13.7K_0402_1%
VCC TMSNS1 NTC_V1 49
2 7 PHYST1 R6 1 @ 2 10K_0402_5%

kS
GND RHYST1

2
NTC_V3
NTC_V2 NTC_V3 49
3 6 TMSNS2 R197 1 @ 2 0_0402_5%
49,60,61 EC_ON OT1 TMSNS2 NTC_V2 49

1
4 5 PHYST2 R7 1 @ 2 10K_0402_5% R10529
OT2 RHYST2 100K_0402_1%_NCP15WF104F03RC
oo
G718TM1U_SOT23-8

over temperature threshold:

2
RSET=3*RTMH

2
R10528
eb

92+/-30C 0_0402_5%

B
Hysteresis temperature threshold. B
RHYST=(RSET*RTML)/(3*RTML-RSET)

1
@
56+/-30C
ot
N

FAN Conn
need check ME SDV CONN list
Change to SP011411114 ref ME conn list,20181017SF update

ME@ JFAN1
0.5A +5VS ACES_50228-00871-001

@ +5VS_FAN1
R52 1 2 0_0603_5% 8
7 8
1 1 49 EC_FAN1_SPEED 7
C50 49 EC_FAN1_PWM 6
C49 .1U_0402_10V6-K 5 6 10
10U_0805_10V6K @ 4 5 GND2
2 2 3 4
49 EC_FAN2_PWM 3
49 EC_FAN2_SPEED 2 9
1 2 GND1
0.5A +5VS 1
A A
@ +5VS_FAN2
R75 1 2 0_0603_5%

1 1
C60
C81 .1U_0402_10V6-K
10U_0805_10V6K @ Title
2 2 Security Classification LC Future Center Secret Data
Issued Date 2016/08/16 Deciphered Date 2018/09/20 Thermal sensor/FAN CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FG541/FG741
Date: Tuesday, March 26, 2019 Sheet 44 of 69
5 4 3 2 1
 A B C D E

+3VS_WLAN

RC832 1 2 10K_0402_5% PCH_W LAN_OFF#

RC833 1 2 10K_0402_5% PCH_BT_OFF# +3VS_WLAN

for wlan same power source issue 0719SF

+3VS +3VALW +3VS_WLAN

10U 6.3V M X5R 0402

1 1 1

Mini-Express Card(WLAN/WiMAX)

C10128
+3VS
@ @ @
2 C10137 2 C10127 2
@
R2236 1 2 0_0603_5% 0.1u_0201_10V6K 1U_0402_6.3V6K

1 JW LAN1 ME@ 1

1
1 2
+3VALW R10506 1 @ 2 0_0603_5% 3 GND1 3.3VAUX1 4 R258 R259
19 USB20_P14 USB_D+ 3.3VAUX2
5 6 1 @ T2 49.9K_0402_1% 49.9K_0402_1%
+3VALW 19 USB20_N14 7 USB_D- LED1# 8
CNVI_WR_D1_N @ CNVI_WGR_D1_R_N GND2 PCM_CLK/I2S_SCK @ UART@ UART@
R10369 1 2 0_0402_5% 9 10 R10381 1 2 0_0402_5%
19 CNVI_WR_D1_N SDIO_CLK PCM_SYNC/I2S_WS CNVI_RF_RESET# 16

2
CNVI_WR_D1_P R10370 1 @ 2 0_0402_5% CNVI_WGR_D1_R_P 11 12
19 CNVI_WR_D1_P SDIO_CMD PCM_IN/I2S_SD_IN

1
13 14 R10392 1 2 0_0402_5%
U4403 CNVI_WR_D0_N @ CNVI_WGR_D0_R_N SDIO_DATA0 PCM_OUT/I2S_SD_OUT CNVI_MODEM_CLKREQ 16
R2225 R10371 1 2 0_0402_5% 15 16 1 @ T3 @
5 1 1 2 0_0603_5% 19 CNVI_WR_D0_N CNVI_WR_D0_P 1 2 0_0402_5% CNVI_WGR_D0_R_P 17 SDIO_DATA1 LED#2 18
75K_0402_5% R2234 @ R10372 @
IN OUT 19 CNVI_WR_D0_P SDIO_DATA2 GND11
@ 19 20
2 CNVI_WR_CLK_N R10373 1 @ 2 0_0402_5% CNVI_WGR_CLK_R_N 21 SDIO_DATA3 UART_WAKE# 22 UART_RX_DEBUG_R R256 1 @ 2 0_0402_5%
2 GND 19 CNVI_WR_CLK_N CNVI_WR_CLK_P 1 2 0_0402_5% CNVI_WGR_CLK_R_P 23 SDIO_WAKE# UART_RXD PCH_UART2_RXD 20
R10374
W LAN_PW R_EN 19 CNVI_WR_CLK_P SDIO_RESET#
4 3 1 @
EN OCB
R10382 1 CNVI@ 2 22_0402_5%

0.1u_0201_10V6K
@

1
CNVI_BRI_RSP 19
1

D R2229 SY6288C20AAC_SOT23-5 C53 KEY E

2 Q2202 200K_0402_5% 2 25 PIN24~PIN31 NC PIN 24
15 CNVI_EN# @ @
G 2N7002KW _SOT323-3 @ +3VS +3VS_WLAN WLAN 27 26 R10383 1 2 0_0402_5%
CNVI_RGI_DT 19
1

@ 29 28

2
R2226 S 31 30
3

75K_0402_5% @ R2072

2
@ Q165 10K_0402_5% 33 32 UART_TX_DEBUG_R R257 1 @ 2 0_0402_5%

G
GND3 UART_TXD PCH_UART2_TXD 20
35 34 R10385 1 CNVI@ 2 22_0402_5%
14 PCIE_PTX_C_DRX_P13 PETP0 UART_CTS CNVI_RGI_RSP 19
2

37 36
14 PCIE_PTX_C_DRX_N13 PETN0 UART_RTS CNVI_BRI_DT 19

1
EC_TX_RSVD
WLAN 39
GND4 VENDOR_DEFINED1
38
EC_RX_RSVD
R62 1 @ 2 0_0402_5%
3 1 41 40 R63 1 @ 2 0_0402_5%
14 PCIE_PRX_DTX_P13 43 PERP0 VENDOR_DEFINED2 42

D
14 PCIE_PRX_DTX_N13 PERN0 VENDOR_DEFINED3
R2223 1 @ 2 0_0402_5% L2N7002KWT1G_SOT323-3 45 44
16 PM_SLP_W LAN# 47 GND5 COEX3 46
17 CLK_PCIE_W LAN REFCLKP0 COEX2
49 48
1 2 0_0402_5% 17 CLK_PCIE_W LAN# 51 REFCLKN0 COEX1 50 SUSCLK_R 1 @ 2 0_0402_5%
R2233 @ R55
49,51,60 SUSP# 1 @ 2 0_0402_5% W LAN_CLKREQ_Q# 53 GND6 SUSCLK 52 PLT_RST# SUSCLK 16
17 W LAN_CLKREQ# R61
PCIE_WAKE#_W LAN CLKREQ0# PERST0# BT_OFF# PLT_RST# 18,28,37,41,42,49
R262 1 AOAC@ 2 0_0402_5% 55 54 R53 1 2 1K_0402_5%

m
16,42,49 PCIE_WAKE# 57 PEWAKE0# W_DISABLE2# 56 W LAN_OFF# 1 2 0_0402_5% PCH_BT_OFF# 20
change WLAN CLKREQ# PH power source 0329SF
R56
GND7 W_DISABLE1# PCH_W LAN_OFF# 20
R57 1 @ 2 0_0402_5% @
42,49 LAN_W AKE#
If support AOAC, NC R61; 19 CNVI_WT_D1_N
CNVI_WT_D1_N R10380 1 @ 2 0_0402_5% CNVI_WT_D1_R_N 59 58 W LAN_SMB_DATA R58 1 @ 2 0_0402_5%
EC_RX 46,49
CNVI_WT_D1_P CNVI_WT_D1_R_P RSRVD/PETP1 I2C_DATA W LAN_SMB_CLK
if not support AOAC, stuff R61. 19 CNVI_WT_D1_P
R10379 1
@
2 0_0402_5% 61
63 RSRVD/PETN1 I2C_CLK
60
62
R59 1 2 0_0402_5%
EC_TX 46,49
@
CNVI_WT_D0_N R10378 1 @ 2 0_0402_5% CNVI_WT_D0_R_N 65 GND8 ALERT# 64 R89 1 2 0_0402_5%

co
19 CNVI_WT_D0_N CNVI_WT_D0_P 1 2 0_0402_5% CNVI_WT_D0_R_P 67 RSRVD/PERP1 RSRVD 66 CLKIN_XTAL_LCP 17
R10377 @
19 CNVI_WT_D0_P 69 RERVD/PERN1 UIM_SWP/PERST1# 68
@

1
CNVI_WT_CLK_N R10376 1 @ 2 0_0402_5% CNVI_WT_CLK_R_N 71 GND9 UIM_POWER_SNK/CLKREQ1# 70
19 CNVI_WT_CLK_N CNVI_WT_CLK_P R10375 1 2 0_0402_5% CNVI_WT_CLK_R_P 73 RSRVD/REFCLKP1
UIM_POWER_SRC/GPIO1/PEWAKE1# 72 R186
19 CNVI_WT_CLK_P @ RSRVD/REFCLKN1 3.3VAUX3 100K_0402_5%
75 74
GND10 3.3VAUX4
77 76

2
GND15 GND14 PLT_RST#

s.
2 ARGOS_NASE0-S6701-TS40 1 2
+3VS_WLAN C381
220P_0201_25V7-K
8/16 Update Conn. P/N SP070013200 wei @
2

ic

10U 6.3V M X5R 0402

1 1 1

1U_0402_6.3V6K

C10135
0.1u_0201_10V6K

C10134

C10136
2 2 2

at
em
ch
M.2 SSD(SATA/PCIE)

kS
NEW +3.3V_NGFF
+3VS HLZ SDV 0601
J8 2A JSSD1

1 2
1 2 +3.3V_NGFF 1 2
3 GND_1 3.3V_1 4
JUMP_43X79 1 1 PCIE_PRX_DTX_N9 5 GND_2 3.3V_2 6
22U_0603_6.3V6-M

4.7U_0402_6.3V6M
@ 14 PCIE_PRX_DTX_N9 PERN3 N/C_2 8 2
1 PCIE_PRX_DTX_P9 7
oo
.1U_0402_10V6-K
3 14 PCIE_PRX_DTX_P9 PERP3 N/C_3 10 3
C239

9 C238
GND_3 DAS/DSS#/LED1# 12
CD@ C240

C241
PCIE_PTX_DRX_N9 CC170 2 1 0.22U_0402_10V6K PCIE_PTX_DRX_N9_C 11
2 2 14 PCIE_PTX_DRX_N9 PETN3 3.3V_3 14 .1U_0402_10V6-K
1

CD@
2 PCIE_PTX_DRX_P9 CC171 2 1 0.22U_0402_10V6K PCIE_PTX_DRX_P9_C 13
14 PCIE_PTX_DRX_P9 15 PETP3 3.3V_4 16 +3.3V_NGFF
PCIE_PRX_DTX_N10 17 GND_4 3.3V_5 18
14 PCIE_PRX_DTX_N10 PCIE_PRX_DTX_P10 19 PERN2 3.3V_6 20
14 PCIE_PRX_DTX_P10 21 PERP2 N/C_4 22
PCIE_PTX_DRX_N10 CC166 2 1 0.22U_0402_10V6K PCIE_PTX_DRX_N10_C 23 GND_5 N/C_5 24
14 PCIE_PTX_DRX_N10 PCIE_PTX_DRX_P10 PCIE_PTX_DRX_P10_C PETN2 N/C_6 26

2
CC1317 2 1 0.22U_0402_10V6K 25
14 PCIE_PTX_DRX_P10 PETP2 N/C_7 28
eb

27 R4679
PCIE_PRX_DTX_N11 29 GND_6 N/C_8 30 10K_0402_5%
14 PCIE_PRX_DTX_N11 PCIE_PRX_DTX_P11 31 PERN1 N/C_9 32 @
14 PCIE_PRX_DTX_P11 PERP1 N/C_10 34
33
GND_7 N/C_11 36

1
PCIE_PTX_DRX_N11 CC168 2 1 0.22U_0402_10V6K PCIE_PTX_DRX_N11_C 35
14 PCIE_PTX_DRX_N11 PCIE_PTX_DRX_P11 PCIE_PTX_DRX_P11_C PETN1 N/C_12 38 DEVSLP0_R DEVSLP0_R
CC169 2 1 0.22U_0402_10V6K 37 1 2 R4678 DEVSLP0
14 PCIE_PTX_DRX_P11 39 PETP1 DEVSLP 40 DEVSLP0 15
0_0402_5%
PCIE_SATA_PRX_DTX_P12 41 GND_8 N/C_13 42 @
14 PCIE_SATA_PRX_DTX_P12 PCIE_SATA_PRX_DTX_N12 PERN0/SATA-B+ N/C_14 44
43 Ac coupling-Cap place near NGFF CONN within 500mil
14 PCIE_SATA_PRX_DTX_N12 PERP0/SATA-B- N/C_15 46

2
45
GND_9 N/C_16 48
ot

PCIE_SATA_PTX_DRX_N12 CC39 2 1 0.22U_0402_10V6K PCIE_SATA_PTX_DRX_N12_C 47 R4680

14 PCIE_SATA_PTX_DRX_N12 PCIE_SATA_PTX_DRX_P12 2 1 PCIE_SATA_PTX_DRX_P12_C 49 PETN0/SATA-A- N/C_17 50 PLT_RST#
CC165 0.22U_0402_10V6K 10K_0402_5%
14 PCIE_SATA_PTX_DRX_P12 51 PETP0/SATA-A+ PERST# 52 SSD_CLKREQ#
CLK_PCIE_SSD# GND_10 CLKREQ# 54 SSD_CLKREQ# 17
53 1
17 CLK_PCIE_SSD# REFCLKN PEWAKE# 56

1
CLK_PCIE_SSD 55
17 CLK_PCIE_SSD REFCLKP NC18 58 @
57 TP76
GND_11 NC19
59 NC NC 60
N

61 NC NC 62 +3.3V_NGFF
63 NC NC 64
65 NC NC 66

1
67 68 +3.3V_NGFF
SSD_DET 69 N/C_1 SUSCLK 70 R274
71 PEDET 3.3V_7 72 10K_0402_5%
73 GND_12 3.3V_8 74
75 GND_13 3.3V_9 76
1 1
77 GND_14 PEG2

2
PEG1 1

22U_0603_6.3V6-M
.1U_0402_10V6-K

.1U_0402_10V6-K
C106

C107
SSD_DET R249 1 2 0_0402_5% SSD_DET#

C237
2 2 SSD_DET# 14
ARGOS_NASM0-S6701-TS20
2
ME@
PEDET (PE_DTCT)

1
R290 SATA Device GND
@
10K_0402_5% PCIe Device Open
For optane
Add C927 due to signal waveform abnormal SSD_DET#

2
HLZ SIV 0811 0 - SATA
PLT_RST#
4
1 - PCIE 4

1
C927
220P_0201_25V7-K
@
2

Security Classification LC Future Center Secret Data Title

Issued Date 2016/12/14 Deciphered Date 2018/09/20 NGFF WLAN&SSD

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
D 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FG541/FG741
Date: Tuesday, March 26, 2019 Sheet 45 of 69
A B C D E
 A B C D E

+USB_VCCA

C55 1 2

+
220U_6.3V_M

C1117 1 2
@ 47U_0805_6.3V6-M
LEFT SIDE USB3.0 PORT x2 C125 1 2
@ 1U_0402_10V6K

+5VALW +USB_VCCA C127 1 2

U2 @ 1U_0402_10V6K
5 1
IN OUT JUSB1 ME@
1
C128 2
1U_0402_6.3V6K GND USB30_TX_P1 C126 1 2 0.1u_0201_10V6K USB30_TX_C_P1 R95 1 2 0_0402_5% USB30_TX_R_P1 9
USB_OC1# 15 USB30_TX_P1 StdA_SSTX+
4 3 1
2 49 USB_ON# ENB OCB USB_OC1# 19 USB30_TX_N1 C124 1 VBUS
2 0.1u_0201_10V6K USB30_TX_C_N1 R96 1 2 0_0402_5% USB30_TX_R_N1 8
15 USB30_TX_N1 USB20_P1 1 2 0_0402_5% USB20_P1_R 3 StdA_SSTX-
SY6288D20AAC_SOT23-5 1 R97 @
19 USB20_P1 D+
1 C140 7 1
1000P_0201_50V7-K USB20_N1 R93 1 @ 2 0_0402_5% USB20_N1_R 2 GND_DRAIN 10
19 USB20_N1 USB30_RX_P1 USB30_RX_R_P1 D- GND_2
Low Active 2A EMC_NS@ R94 1 2 0_0402_5% 6 11
2 15 USB30_RX_P1 4 StdA_SSRX+ GND_3 12
USB30_RX_N1 R98 1 2 0_0402_5% USB30_RX_R_N1 5 GND_1 GND_4 13
15 USB30_RX_N1 StdA_SSRX- GND_5

ALLTO_C190AG-10939-L

09/05 Update USBConn. P/N DC021609011 wei

L13 EMC_NS@
USB30_RX_N1 1 2 USB30_RX_R_N1
1 2

USB30_RX_P1 4 3 USB30_RX_R_P1
4 3
EXC24CH900U_4P USB20_P1_R
+USB_VCCA
USB20_N1_R
L16 EMC_NS@ D12
USB30_TX_C_N1 1 2 USB30_TX_R_N1 USB30_RX_R_N1 1 10 USB30_RX_R_N1

AZ5725-01F.R7GR_DFN1006P2X2
1 2 Line-1 NC1

2
D11
D13 USB30_RX_R_P1 2 9 USB30_RX_R_P1

1
USB30_TX_C_P1 4 3 USB30_TX_R_P1 AZC199-02S.R7G_SOT23-3 Line-2 NC2
4 3 EMC@ USB30_TX_R_N1 4 7 USB30_TX_R_N1
EXC24CH900U_4P Line-3 NC3
USB30_TX_R_P1 5 6 USB30_TX_R_P1
Line-4 NC4

2
EMC_NS@ 3
GND1

2
EXC24CH900U_4P

m
USB20_P1 4 3 USB20_P1_R 8
4 3 GND2
AZ1143-04F-R7G_DFN2510P10E10

1
USB20_N1 1 2 USB20_N1_R
1 2 EMC@
L8 EMC@
EMC

co
EMC

s.
2 +USB_VCCA 2

C2060 1 2
@ 1U_0402_10V6K

ic
C2059 1 2
@ 1U_0402_10V6K

L30 EMC_NS@ JUSB3 ME@

USB30_RX_N3 1 2 USB30_RX_R_N3
1 2 USB30_TX_P3 C2058 1 2 0.1u_0201_10V6K USB30_TX_C_P3 R3119 1 @ 2 0_0402_5% USB30_TX_R_P3 9

at
15 USB30_TX_P3 StdA_SSTX+
1
USB30_RX_P3 4 3 USB30_RX_R_P3 USB30_TX_N3 C2057 1 2 0.1u_0201_10V6K USB30_TX_C_N3 R3116 1 @ 2 0_0402_5% USB30_TX_R_N3 8 VBUS
4 3 15 USB30_TX_N3 USB20_P3_S USB20_P3_R StdA_SSTX-
R3103 1 @ 2 0_0402_5% 3
EXC24CH900U_4P 7 D+
USB20_N3_S R942 1 @ 2 0_0402_5% USB20_N3_R 2 GND_DRAIN 10
USB30_RX_P3 R3117 1 @ 2 0_0402_5% USB30_RX_R_P3 6 D- GND_2 11
15 USB30_RX_P3 4 StdA_SSRX+ GND_3 12
L29 EMC_NS@
USB30_TX_C_N3 1 2 USB30_TX_R_N3 USB30_RX_N3 R3114 1 @ 2 0_0402_5% USB30_RX_R_N3 5 GND_1 GND_4 13

em
1 2 15 USB30_RX_N3 StdA_SSRX- GND_5

USB30_TX_C_P3 4 3 USB30_TX_R_P3 ALLTO_C190AG-10939-L

4 3
EXC24CH900U_4P 09/05 Update USBConn. P/N DC021609011 wei
FOR ESD Close to Connector D45
EXC24CH900U_4P USB30_RX_R_N3 1 10 USB30_RX_R_N3 UARTA_P80_EN
USB20_P3_S 4 3 USB20_P3_R USB20_P3_R +USB_VCCA Line-1 NC1
4 3 USB30_RX_R_P3 2 9 USB30_RX_R_P3
USB20_N3_R Line-2 NC2
USB20_N3_S 1 2 USB20_N3_R USB30_TX_R_N3 4 7 USB30_TX_R_N3

ch
1 2 Line-3 NC3
3

1
D64 R538
AZ5725-01F.R7GR_DFN1006P2X2

USB30_TX_R_P3 USB30_TX_R_P3

2
L17 EMC@ 5 6

AZ5725-01F.R7GR_DFN1006P2X2
D43

EMC_NS@

1
Line-4 NC4
1

100K_0402_5%
AZC199-02S.R7G_SOT23-3 R537
EMC@ D34 3 0_0402_5% DEBUG@
1

GND1
@

2
EMC_NS@ 8
GND2

2
AZ1143-04F-R7G_DFN2510P10E10

2
2

kS
EMC@
2
1

3
oo 3

For USB Debug Function

eb

09/20SF add USB debug follow TINY5

change from SA00007WL0D to SA00007WL00 SF1001
ot

SVT non-staff0322SF
N

2 DEBUG@1 0_0402_5% USB_UART_SEL

+3VALW
20 USBDEBUG
R531
USBDEBUG Kernel debug
Set input Set input
+3VALW
Set output Low ENABLE
DEBUG@
1

DEBUG@ U3
R547
1/16W _10K_5%_0402
R533 2 DEBUG@1 0_0402_5% SOUTA_C 1 10
45,49 EC_TX 1D+ VCC
UARTA_P80_EN POST 80
2

USB_UART_SEL R536 2 DEBUG@1 0_0402_5% SINA_C 2 9 USB_UART_SEL

45,49 EC_RX 1D- S
3 8 USB20_P3_S
19 USB20_P3 2D+ D+ Set input DISABLE
NCY3958Y USB20_N3_S
1

D 4 7
UARTA_P80_EN 19 USB20_N3 2D- D- Set output Low ENABLE
2
G L2N7002KWT1G_SOT323-3 5 6
Q56 GND1 OE#
S 11
DEBUG@ GND2
3

4 4

NCT3958Y_DFN10_3X3 OE# S FUNCTION

H X DISABLE

L L D(+/-) to 1D(+/-)
USB20_P3 R539 2 @ 1 0_0402_5% USB20_P3_S
L H D(+/-) to 2D(+/-)

USB20_N3 R541 2 @ 1 0_0402_5% USB20_N3_S

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2018/09/20 USB3.0 PORT (LEFT)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
D 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FG541/FG741
Date: Tuesday, March 26, 2019 Sheet 46 of 69
A B C D E
 A B C D E F G H

SATA HDD Conn.

ME@
1 ELCO_006809610010846 1

1
SATA_PTX_DRX_P0 C66 1 2 0.01U_0201_10V6K SATA_PTX_C_DRX_P0 2 1
14 SATA_PTX_DRX_P0 2
+5VS_HDD SATA_PTX_DRX_N0 C67 1 2 0.01U_0201_10V6K SATA_PTX_C_DRX_N0 3 11
14 SATA_PTX_DRX_N0 3 GND1
4
SATA_PRX_DTX_N0 C68 1 2 0.01U_0201_10V6K SATA_PRX_C_DTX_N0 5 4
14 SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 C69 1 2 0.01U_0201_10V6K SATA_PRX_C_DTX_P0 6 5
14 SATA_PRX_DTX_P0 7 6 12
1 1 1 1 1 8 7 GND2
C74 C76 C75 C77 C78 8
9
33P_0201_50V8-J 33P_0201_50V8-J 0.1u_0201_10V6K 10U_0805_10V6K 10U_0805_10V6K 9
10
RF@ RF_NS@ @ +5VS +5VS_HDD 10
2 2 2 2 2
Need short
JHDD1
J3 1 2 @
1 2

m
JUMP_43X79
For RF

co
s.
ic
2 2

at
em
ch
kS
oo
3 3
eb
ot
N

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2018/09/20 HDD/ODD CONN

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FG541/FG741
Date: Tuesday, March 26, 2019 Sheet 47 of 69
A B C D E F G H
 5 4 3 2 1

VBUS_P0
Need short +5VALW
+5VALW
J14 2 1
2 1 @

100K_0402_1%

100K_0402_1%

100K_0402_1%
R117 JUMP_43X39
+5VALW

2
VBUS_P0 F10
+5VALW 100K_0402_1%

R104

R105

R108
1 2
D D
U7 @

2
2A_32V_ERBRD2R00X
1 12

1
AZ5725-01F.R7GR_DFN1006P2X2

IN1 OUT

150U_B2_6.3VM_R35M
2
10U_0805_25V6K

4.7U_0805_25V6-K

0.47U_0402_25V6-K

0.47U_0402_25V6-K

0.47U_0402_25V6-K

0.47U_0402_25V6-K
FAULT#

22U_0603_6.3V6-M

22U_0603_6.3V6-M
IN2
1

D38 5 FAULT# R10527 2 1 0_0402_5% TYPE_C_OCP#

EC_VBUS_EN 2 FAULT TYPE_C_OCP# 19
1 4
C918

C919

C920

C1334

C921

C922
1 1
1

49 EC_VBUS_EN EN SINK#
1

1
1 R118 @ 0_0402_5% 11 CC2
EMC_NS@

3 CC2
+ CHG POL#
9
@ @ @ @ @
1.5A CC1
CC1
2

2
2 2 8
REF 6 1 2 0_0402_5%
2

SINK# R10507

1
2 SINK TYPE_C_DFP 49

2
10
GND1
2

R103 13 7 POL# R10508 1 2 0_0402_5%

C1333
C10122
GND2 POL TYPE_C_ST 49

C213
100K_0402_1%

@
2

2
TPS25820DSSR_WSON12_3X2

m
VBUS_P0

co
R943 1 @ 2 0_0402_5%
3A
L23 EMC@
1 2 C_DP
19 USB20_P2 1 2

s.
4 3 C_DM
19 USB20_N2 4 3
EXC24CH900U_4P

ic

25
26
27
28
JP1 ME@
R91 1 @ 2 0_0402_5%

GND5
GND6
GND7
GND8
C C

at
24 1
Power_GND_B12 GND_A1
C_RX1_P_C 23 2 C_TX1_P_C
SSRXp1_B11 SSTXp1_A2
C_RX1_N_C 22 3 C_TX1_N_C
SSRXn1_B10 SSTXn1_A3

em
R944 2 1 0_0402_5% 21 4
VBUS_B9 VBUS_A4
EXC24CH900U_4P 20 5 CC1
USB30_TX_N2 C10131 1 2 0.1U_0201_6.3V6-K C_TX2_N SBU2_B8 CC1_A5
15 USB30_TX_N2 C_TX2_N 2 1 C_TX2_N_C
USB30_TX_P2 C10130 1 2 0.1U_0201_6.3V6-K C_TX2_P 2 1
15 USB30_TX_P2 C_DM 19 6 C_DP
Dn2_B7 Dp1_A6
C_TX2_P 3 4 C_TX2_P_C C_DP 18 7 C_DM
USB30_RX_N2 C10125 1 2 0.33U 10V K X5R 0402 C_RX2_N 3 4 Dp2_B6 Dn1_A7

ch
15 USB30_RX_N2 USB30_RX_P2 C_RX2_P
C10126 1 2 0.33U 10V K X5R 0402 L24 EMC_NS@
15 USB30_RX_P2 CC2 17 8
CC2_B5 SBU1_A8
R3107 2 1 0_0402_5% 16 9
CC1 VBUS_B4 VBUS_A9
USB30_TX_N4 C10132 1 2 0.1U_0201_6.3V6-K C_TX1_N
15 USB30_TX_N4 CC2 C_TX2_N_C 15 10 C_RX2_N_C
USB30_TX_P4 C10133 1 2 0.1U_0201_6.3V6-K C_TX1_P SSTXn2_B3 SSRXn2_A10

kS
15 USB30_TX_P4 R100 2 1 0_0402_5%

2
D47 EMC_NS@ C_TX2_P_C 14 11 C_RX2_P_C
L25 EMC_NS@ SSTXp2_B2 SSRXp2_A11
USB30_RX_N4 C10123 1 2 0.33U 10V K X5R 0402 C_RX1_N
15 USB30_RX_N4 C_RX2_P 3 4 C_RX2_P_C 13 12
USB30_RX_P4 C10124 1 2 0.33U 10V K X5R 0402 C_RX1_P 3 4 GND_B1 GND_A12
15 USB30_RX_P4

GND12
GND11
GND10
GND9
C_RX2_N 2 1 C_RX2_N_C
2
oo 1
R10414 1 2 220K_0201_5%
EXC24CH900U_4P HIGHS_UB11246-15A0C-1H
R10415 1 2 220K_0201_5%

32
31
30
29
R10416 1 2 220K_0201_5% R101 2 1 0_0402_5%
R10417 1 2 220K_0201_5%
AZC199-02S.R7G_SOT23-3

1
eb

Ref intel PDG(571391)Rev1.8 Type-C USB-IF update 0802SF R3135 1 2 0_0402_5%

B B
EXC24CH900U_4P
C_RX1_N 1 2 C_RX1_N_C C_DM D20
ot

1 2 C_DP D36 C_TX1_P_C 1 10 C_TX1_P_C

C_RX1_P_C 1 10 C_RX1_P_C Line-1 NC1
Line-1 NC1
3

2
C_RX1_P 4 3 C_RX1_P_C D48 EMC_NS@ C_TX1_N_C 2 9 C_TX1_N_C
4 3 C_RX1_N_C 2 9 C_RX1_N_C Line-2 NC2
L31 EMC_NS@ Line-2 NC2 C_RX2_N_C C_RX2_N_C
4 7
N

R3137 1 2 0_0402_5% C_TX2_N_C 4 7 C_TX2_N_C Line-3 NC3

Line-3 NC3 C_RX2_P_C C_RX2_P_C
5 6
C_TX2_P_C 5 6 C_TX2_P_C Line-4 NC4
1 2 0_0402_5% Line-4 NC4
R3136 3
3 GND1
GND1
L32 EMC_NS@ 8
C_TX1_P 4 3 C_TX1_P_C 8 GND2
4 3 GND2
AZ1143-04F-R7G_DFN2510P10E10
AZC199-02S.R7G_SOT23-3 AZ1143-04F-R7G_DFN2510P10E10 For ESD EMC_NS@
1

C_TX1_N 1 2 EMC_NS@
1 2
EXC24CH900U_4P
R3138 1 2 0_0402_5% C_TX1_N_C

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2018/09/20 3D Camera

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
FG541/FG741 1.0

Date: Tuesday, March 26, 2019 Sheet 48 of 69

5 4 3 2 1
 5 4 3 2 1

1 2 0_0603_5%
For ESD For EMI RE1 @ +3VL
+3VL_EC +3VL_EC_R
PLT_RST# CLK_PCI_EC RE2 1 2 33_0402_5%
EMC@ @
LE1 1 2 0_0603_5%
1 2 0_0603_5%
1
CE1 CE2
1 Close EC RE3 @ +3VALW
220P_0201_25V7-K 22P_0402_50V8-J 1 1
+3VL_EC CE4 CE5
@ EMC@
2 2 0.1u_0201_10V6K 1000P_0201_50V7-K
CE3 1 2 VCOREVCC

0.1u_0201_10V6K +3VL_EC All capacitors close to EC 1 2 0_0603_5%

2
EC_AGND
2
LE2 @

CD@

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K
1 1 1 @1 1 @ 1
+3VL_EC_R EC_AGND
+3VS
D 2 2 2 2 2 2 +3VL_EC D
Change RE6 to 0ohm jump

CE10

CE11
CE6

CE7

CE8

CE9
RE6 1 @ 2 0_0402_5%
+3VS

1
RE5
10K_0402_5%
minimum trace width 12 mil EC_FAN2_SPEED RE278 1 2 10K_0402_5%

114
121
127
12

11

26
50
92

74
3
UE1

2
EC_FAN1_SPEED RE10 1 2 10K_0402_5%
LAN_WAKE#

VSTBY1
VSTBY2
VSTBY3
VSTBY4
VSTBY5
VCC

AVCC
VBAT

VCORE

VSTBY(PLL)
LAN_WAKE# 42,45

EC_FAN2_PWM RE279 1 @ 2 10K_0402_5%

EC_FAN1_PWM RE11 1 @ 2 10K_0402_5%

25 WRST# PWR_LED#
RE56 1 @ 2 0_0402_5% 4 24
15 KBRST# KBRST#/GPB6 PWM0/GPA0 PWR_LED# 50 LPC_FRAME#
RE59 1 @ 2 0_0402_5% 5 25 RE7 1 @ 2 10K_0402_5%
+3VL_EC 15 SERIRQ SERIRQ/GPM6 PWM1/GPA1 BATT_CHG_LED# 50
RE60 1 @ 2 0_0402_5% LPC_FRAME#_EC 6 28
15 LPC_FRAME# LPC_AD3 7 LFRAME#/GPM5 PWM2/GPA2 29 EC_BKL_EN BATT_LOW_LED# 50 1 2 100K_0402_5%
ENBKL RE9 @
15 LPC_AD3 LPC_AD2 LAD3/GPM3 PWM3/GPA3 EC_FAN2_PWM EC_BKL_EN 50
DE1 1 2 @ 8 PWM 30

m
15 LPC_AD2 LPC_AD1 LAD2/GPM2 PWM4/GPA4 EC_FAN1_PWM EC_FAN2_PWM 44
9 31 EC_CMOS_ON#
15 LPC_AD1 LPC_AD0 10 LAD1/GPM1 PWM5/GPA5 32 EC_FAN1_PWM 44 RE275 1 @ 2 10K_0402_5%
RB751V-40_SOD323-2
15 LPC_AD0 CLK_PCI_EC LAD0/GPM0 PWM6/SSCK/GPA6 EC_VBUS_EN EC_BEEP# 35
13 LPC 34
1 2 15 CLK_PCI_EC 14 LPCCLK/GPM4 PWM7/RIG1#/GPA7 120 LAN_WAKE# EC_VBUS_EN 48
WRST#
WRST# TMRI0/GPC4
change for EC_VBUS_EN 20180910SF

co
RE8 1 15 124 SUSP#
15 EC_SMI# EC_RX ECSMI#/GPD4 TMRI1/GPC6 SUSP# 45,51,60 +3VALW +3VL_EC
100K_0402_5% 16 For PMIC
CE12 45,46 EC_RX EC_TX 17 PWUREQ#/BBO/SMCLK2ALT/GPC7 66
1U_0402_6.3V6K 45,46 EC_TX LPCPD#/GPE6 ADC0/GPI0 NTC_V1 44
PLT_RST# 22 67
2 18,28,37,41,42,45 PLT_RST# LPCRST#/GPD2 ADC1/GPI1 NTC_V2 44

1
23 68 BATT_TEMP
14,20 EC_SCI# EC_RTCRST#_ON ECSCI#/GPD3 ADC2/GPI2 BATT_TEMP 58,59
126 ADC 69 RE273 RE274
GA20/GPB5 ADC3/GPI3 NTC_V3 44
70

s.
IT8586E/AX ADC4/GPI4
ADC5/DCD1#/GPI5
71
72 ADAPTER_ID_R RE280 1 @
CPUCORE_ON
ADP_I 59
2 0_0402_5%
6,63
0_0402_5%
@
@ 0_0402_5%

LQFP-128L ADC6/DSR1#/GPI6 ADAPTER_ID 58 +3VL_EC

2
73 RE276 1 @ 2 0_0402_5%
ADC7/CTS1#/GPI7 PSYS 59,63
KSI[0..7] KSI0 58 RPE4

ic
50 KSI[0..7] KSI0/STB#

1
KSI1 59 78 PAD 1 @ EC_SMB_DA3 1 4
KSO[0..17] 60 KSI1/AFD# DAC2/TACH0B/GPJ2 79 CPU_PWRGD IT37 EC_SMB_CK3 2 3
KSI2 RE65
50 KSO[0..17] KSI2/INIT# DAC3/TACH1B/GPJ3 H_PROCHOT#_EC CPU_PWRGD 63
C KSI3 61 DAC 80 100K_0402_5% C
KSI4 62 KSI3/SLIN# DAC4/DCD0#/GPJ4 81 2.2K_0404_4P2R_5%

at
KSI4 DAC5/RIG0#/GPJ5 ENBKL 38
KSI5 63
KSI5

2
+3VL_EC KSI6 64 85 EC_ON_GPIO RE57 1 @ 2 0_0402_5%
65 KSI6 PS2CLK0/TMB0/CEC/GPF0 86 EC_ON 44,60,61 +5VALW
KSI7
KSI7 PS2DAT0/TMB1/GPF1 EC_SMB_CK3 PBTN_OUT# 16,41
KSO0 36 87 USB_ON#
EC_SMB_CK1 1 37 KSO0/PD0 GPF2 88 EC_SMB_DA3 EC_SMB_CK3 61,63 RE15 1 2 100K_0402_5%
RPE2 PAD @ KSO1 Int. K/B PS2

em
EC_SMB_DA1 EC_SMB_DA1 IT1 KSO1/PD1 GPF3 EC_SMB_DA3 61,63
2 3 PAD 1 @ KSO2 38 89 +3VL_EC
1 4 EC_SMB_CK1 PAD 1 @
IT2
KSO3 39 KSO2/PD2 Matrix PS2CLK2/GPF4 90 EC_LID_OUT# PM_SLP_SUS# 16
1 IT3 40 KSO3/PD3 PS2DAT2/GPF5 EC_LID_OUT# 50
PAD @ KSO4
IT4 KSO4/PD4
2.2K_0404_4P2R_5% PAD 1 @ KSO5 41 EXTERNAL SERIAL FLASH 96 SUSP# RE18 1 @ 2 100K_0402_5%
IT5 42 KSO5/PD5 GPH3/ID3 97 CAPS_LED# 50
KSO6
KSO6/PD6 GPH4/ID4 PCH_PWR_EN 51,61
KSO7 43 98
KSO7/PD7 GPH5/ID5 SYS_PWROK 16,41
KSO8 44 99
+3VS 1 45 KSO8/ACK# GPH6/ID6 PCH_PWROK 16,41 CPUCORE_ON
KSI7 PAD @ KSO9 RE270 1 2 100K_0402_5%

ch
IT6 KSO9/BUSY EC_SPI_CS0#
KSI6 PAD 1 @ KSO10 46 101
1 IT7 51 KSO10/PE NC1 102 EC_SPI_SI EC_SPI_CS0# 18
RPE3 WRST# PAD @ KSO11 SUSP# RE19 1 2 100K_0402_5%
EC_SMB_CK2 IT8 KSO11/ERR# NC2 EC_SPI_SO EC_SPI_SI 18
1 4 KSO12 52 SPI Flash ROM 103
EC_SMB_DA2 KSO12/SLCT NC3 EC_SPI_CLK EC_SPI_SO 18 SYSON_R
2 3 KSO13 53 105 RE21 1 2 100K_0402_5%
KSO13 NC4 EC_SPI_CLK 18
For factory EC flash KSO14 54
KSO14
2.2K_0404_4P2R_5% KSO15 55

kS
KSO16 56 KSO15 108 ACIN#
57 KSO16/SMOSI/GPC3 AC_IN# LID_SW# EC_VCCIO_EN
KSO17
KSO17/SMISO/GPC5 UART LID_SW#
109
LID_SW# 50
RE268 1 @ 2 100K_0402_5%

50 ON/OFF ON/OFF 110 82 TYPE_C_DFP 48

EC_ON RE58 2 1 0_0402_5% 111 PWRSW# EGAD/GPE1 83
@
XLP_OUT SM Bus EGCS#/GPE2 VDDQ_PGOOD 61
EC_SMB_CK1 115
oo 84 EC_VPP_PWREN Add to fix Reset&PWRGD test fail issue
58,59 EC_SMB_CK1 EC_SMB_DA1 SMCLK1/GPC1 EGCLK/GPE3 EC_VPP_PWREN 61
116
1 58,59
2 33_0402_5% EC_SMB_DA1 PECI_EC 117 SMDAT1/GPC2 77 VDDQ_PGOOD CE51 1 2
6,14 EC_PECI RE24
SMCLK2/PECI/GPF6 GPIO GPJ1 EC_MUTE# 35
0.01U_0201_10V6K
118 100 GPG2
20,42 LAN_PWR_ON# EC_SMB_CK2 94 SMDAT2/PECIRQT#/GPF7 SSCE0#/GPG2 106
16,28,44 EC_SMB_CK2 EC_SMB_DA2 CRX1/SIN1/SMCLK3/GPH1/ID1 SSCE1#/GPG0 EC_CMOS_ON# 38 PM_SLP_S4#
95 104 CE50 1 2 EMC_NS@ 1000P_0201_50V7-K
+3VL 16,28,44 EC_SMB_DA2 CTX1/SOUT1/GPH2/SMDAT3/ID2 DSR0#/GPG6 SYSON_R ME_FLASH 16
107 RE271 1 @ 2 0_0402_5% SYSON
eb

DTR1#/SBUSY/GPG1/ID7 119 SYSON 51,61

BKOFF#
CRX0/GPC0 BKOFF# 38 EC_VCCIO_EN PM_SLP_S3#
123 RE55 2 @ 1 0_0402_5% CE21 1 2 EMC_NS@ 1000P_0201_50V7-K
CTX0/TMA0/GPB2 EC_VCCIO_EN 62
RE27 1 @ 2 0_0402_5% 112 18
VSTBY0 RI1#/GPD0 PM_SLP_S3# 16
RE281 1 2 0_0402_5% 125 21 PM_SLP_S4# 16
B 16 DPWROK_EC GPE4 RI2#/GPD1 B
@ WAKE UP 76 NOVO# 50 SYSON CE13 1 2 EMC_NS@ 1000P_0201_50V7-K
TYPE_C_ST RE283 1 2 0_0402_5% TACH2/GPJ0 48 EC_FAN2_SPEED
TACH1A/TMA1/GPD7 EC_FAN2_SPEED 44
ot

@ 47 EC_FAN1_SPEED
TACH0A/GPD6 EC_FAN1_SPEED 44
USB_ON# 33 19 VGA_AC_DET
46 USB_ON#
48 TYPE_C_ST RE282 1 @ 2 0_0402_5% 35 GINT/CTS0#/GPD5
GPIO
L80HLAT/BAO/GPE0 20
VGA_AC_DET 28 EMC Request
EC_RSMRST#_R RTS1#/GPE5 L80LLAT/GPE7 NUM_LED# 50
R10577 1 2 1K_0402_5% 93
16,41 EC_RSMRST# CLKRUN#/GPH0/ID0 Reserve for VGA_AC_DET
N

PCIE_WAKE# 2
16,42,45 PCIE_WAKE# CK32KE/GPJ7
128 Clock
+3VL 16 AC_PRESENT CK32K/GPJ6

RE34 1 @ 2 0_0402_5% H_PROCHOT# 6,61,63

RE35 1 @ 2 10K_0402_5% ON/OFF 59 VR_HOT#
AVSS
VSS1

VSS2
VSS3
VSS4
VSS5
VSS6

EC_RTC_RST# 16

1
RE36 1 @ 2 10K_0402_5% BKOFF# 1
IT8586E-AX_LQFP128_14X14 RE267 CE14
113
122
1

27
49
91

75

RE38 2 1 100K_0402_5% LID_SW# 100_0402_5% 47P_0201_25V8-J

EMC_NS@
2

1
QE3 D

1 2
EC_RTCRST#_ON 2
RE40 1 2 10K_0402_5% BKOFF# QE1 D G
EC_AGND H_PROCHOT#_EC 2 +3VL
G S 2N7002KW_SOT323-3

3
1
for EC version update to EX, manual modify PN to FX
2N7002KW_SOT323-3 S RE50

2
10K_0402_5%
RE42
100K_0402_5%

2
1
+3VL +3VS ACIN# RE262 1 @ 2 0_0402_5%
PECI_EC EMC_NS@ CE15 1 2 47P_0201_25V8-J
+3VL_EC

1
BATT_TEMP EMC_NS@ CE16 1 2 100P_0201_25V8J D QE2
1
A GPG2 RE43 2 @ 1 10K_0402_5% CE19 2 A
ACIN 59
ACIN# EMC_NS@ CE17 1 2 100P_0201_25V8J 0.1u_0201_10V6K G
GPG2 RE44 2 1 10K_0402_5%
NOVO# ON/OFF @ CE18 1 2 1U_0402_6.3V6K 2 S 2N7002KW_SOT323-3

3
GPG2 RE46 2 @ 1 10K_0402_5% @

when mirror, GPG2 pull high

when no mirror, GPG2 pull low 1
CE48
0.01U_0201_10V6K Title
EMC_NS@
Security Classification LC Future Center Secret Data
2
Issued Date 2015/08/20 Deciphered Date 2018/09/20 EC ITE8586LQFP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
FG541/FG741 1.0

Date: Tuesday, March 26, 2019 Sheet 49 of 69

5 4 3 2 1
 5 4 3 2 1

ON/OFF switch +3VL +3VALW

Novo button NOVO_BTN#

2
SW2

1
R82 R83 4 D24

1
100K_0402_5% 100K_0402_5% AZ5123-01F.R7GR_DFN1006P2X2
@ 5 EMC@
R261 1 @ 2 0_0402_5%

2
NTC325-EKJ-A160T_3P

2
NOVO# D15 2 8/16 Del Power Button wei
49 NOVO#
1 NOVO_BTN#
ON/OFFBTN#
ON/OFF R85 1 @ 2 0_0402_5% 3 @
8/31 Update the P/N SN100008W00 wei

AZ5123-01F.R7GR_DFN1006P2X2
BAT54CW_SOT323-3

1
D25

1
D D

+3VALW +3VL

LID switch

2
2

2
EMC@

2
R111 R114
100K_0402_5% 100K_0402_5%
@

1
ON/OFFBTN# R119 1 @ 2 0_0402_5% ON/OFF 1
ON/OFF 49
C1104
U14 100P_0201_25V8J
J5 1 2 @ 1
GND 2
1
SHORT PADS C1105 3 R10418 1 @ LID_SW#
2 0_0402_5%
0.01U_0201_10V6K OUTPUT LID_SW# 49
J6 1 2 @
R264 1 2 2 +VCC_LID 2
+3VL VCC
SHORT PADS 0_0402_5%
AH9247-W-7_SC59-3

m
KBD symbol:
K/B Connector KSI[0..7]
KSI[0..7] 49
1.20180821SF update to SP011807040 ME@
KB Backlight Connector
KSO[0..17]

co
KSO[0..17] 49 HIGHS_FC8AR321-3160-1H

ON/OFFBTN#
1
2 1 update BL circuit and need too be confirm conn pin define 0925SF
EMC_NS@ PWR_LED# R285 1 2 200_0402_1% 3 2
3 LED_KB_C
PWR_CAPS_LED C133 1 2 100P_0201_25V8J R279 1 2 200_0402_1% NUM_LED#_R 4
49 NUM_LED# KSO17_R 4
KSO17 R281 1 @ 2 0_0402_5% 5
KSO16 R280 1 @ 2 0_0402_5% KSO16_R 6 5
6 1

s.
KSI1 7 D
KSI7 8 7
8 EC_BKL_EN 2 Q121
KSI6 9 49 EC_BKL_EN
KSO9 10 9 G PJA138K_SOT23-3
10 S BL@
KSI4 11

2
KSI5 12 11
3

ic
12 R116
EMC@ KSO0 13
CAPS_LED# 1 2 100P_0201_25V8J 14 13 100K_0402_5%
C117 KSI2
KSI3 15 14 BL@
C NUM_LED#_R C118 1 2 100P_0201_25V8J KSO5 16 15 C

1
KSO1 17 16
17

at
EMC@ KSI0 18
19 18
8/23 PWR LED function under check KSO2
KSO4 20 19
KSO7 21 20
KSO8 22 21 +5VS
CAPS_LED# NUM_LED#_R PWR_LED# KSO6 23 22 0.5A
JKBL1 ME@
KSO3 24 23 1

em
KSO12 25 24 LED_KB_C 2 1
KSO13 26 25 R343 1 2 0_0603_5% 3 2 6
KSO14 27 26 BL@ 4 3 GND2 5
27 4 GND1
1

KSO11 28 1
D22 D23 D46 KSO10 29 28 C1110 CVILU_CF50041D0RN-10-NH
1

AZ5123-01F.R7GR_DFN1006P2X2 AZ5123-01F.R7GR_DFN1006P2X2 AZ5123-01F.R7GR_DFN1006P2X2 KSO15 30 29 0.1u_0201_10V6K

EMC@ EMC@ EMC@ CAPS_LED# R275 1 2 200_0402_1% CAPS_LED#_R 31 30 34 @
49 CAPS_LED# PWR_CAPS_LED 31 GND2 2
R84 1 @ 2 0_0402_5% 32 33
+3VALW 32 GND1
2

JKB1

ch
2

For EMC

kS
TP/B Connector TP_PWR
Finger Print Connector +3VS TP_PWR
R10412 1 2 2.2K_0201_5% TP_I2C_SDA0
follow OD V1.5 delete finger print function 0927SF R141 1 @ 2 0_0402_5%
R10413 1 2 2.2K_0201_5% TP_I2C_SCL0
oo

0.1u_0201_10V6K

1
1 RG49
RG50
@
10K_0402_5%
10K_0402_5%
2

C114

2
ELCO_04-6809-606-110-846-+
R4675 1 @ 2 0_0402_5% EC_LID_OUT#_R 6
49 EC_LID_OUT# TP_INT# 6
R4676 1 @ 2 0_0402_5% 5
eb

20 PCH_TP_INT# 5
4 8
TP_I2C_SDA0 3 4 GND2
20 TP_I2C_SDA0 TP_I2C_SCL0 2 3 7
20 TP_I2C_SCL0 1 2 GND1
TP_PWR 1
TP_I2C_SCL0

100P_0201_25V8J

100P_0201_25V8J
B JTP1 ME@ B
TP_I2C_SDA0 1 1

EMC_NS@

EMC_NS@
3

2
ot

DT1 2 2

C115

C116
EMC_NS@
N

AZC199-02S.R7G_SOT23-3
1

For EMC

BATT_LOW_LED# LED2 1 2 R143 1 2 470_0402_5%

49 BATT_LOW_LED# +3VALW
L-C192JFCT-LCFC_SUPER_AMBER
1

D18
1

AZ5123-01F.R7GR_DFN1006P2X2
EMC_NS@
2
2

BATT_CHG_LED# LED3 1 2 R144 1 2 1.5K_0402_5%

49 BATT_CHG_LED# +5VALW
L-C192WDT-LCFC_WHITE
1

D19
1

AZ5725-01F.R7GR_DFN1006P2X2
EMC_NS@
2
2

A A

PWR_LED#
PWR_LED# LED4 1 2 R4672 1 2 1.5K_0402_5%
49 PWR_LED# +5VALW
1

L-C192WDT-LCFC
D16
1

AZ5725-01F.R7GR_DFN1006P2X2
EMC_NS@

PWR_LED Change to M/B (310->320) 08/17

2
2

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2018/09/20 KBD/PWR/IO/LED/TP Conn.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FG541/FG741
Date: Tuesday, March 26, 2019 Sheet 50 of 69
5 4 3 2 1
 A B C D E

+1.8VALW +1.05VALW
VCCSTG & VCCST change to Dual Switch 0906SF
VCCSTG

C2085

C2086

C2091

C2092

C2087

C2088

C2089

C2090
+1.05VALW
1 1 1 1 1 1 1 1

EMC_NS@

EMC_NS@

EMC_NS@
EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

1U_0402_6.3V6K
22U_0603_6.3V6-M

22U_0603_6.3V6-M
0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K
2 2 2 2 2 2 2 2 1 1 1 1

CC1250

C1102
CC71
CC72
1U_0402_6.3V6K
2 2 2 2
@ UC4 @
1 14
2 IN1_1 OUT1_2 13
IN1_2 OUT1_1
SUSP# 3 12 CC1293 1 2 1000P_0201_50V7-K
1 EN1 CT1 1
4 11
+5VALW VBIAS GND
SYSON 5 10 CC1292 1 2 1000P_0201_50V7-K
49,61 SYSON EN2 CT2
+1.05VALW VCCST
6 9
7 IN2_1 OUT2_2 8
IN2_2 OUT2_1
1@
15
Thermal Pad CC1392
1 10U_0603_6.3V6M
G2898KD1U_TDFN14P_2X3 2
CC1393
1U_0402_6.3V6K
2

EMC

m
co
+5VALW
+3VALW Need short +3VALW_PCH +1.8VALW +1.8VS

0.6A

s.
J7 Q35
1

1 2 @
1 2 3 1

D
R155
JUMP_43X79
100K_0402_5% LP2301ALT1G_SOT23-3

ic
1 1

C201
0.1u_0201_10V6K

C203
0.1u_0201_10V6K
@ 1

G
2

2
C1103
PCH_PWR_EN#_R PCH_PWR_EN# @ @
2 R158 1 @ 2 100K_0402_5% 22U_0603_6.3V6-M LP2301ALT1G_SOT23-3 Id=3.2A @
2 2
2
@

at
2 1 1
3 1

C204
0.1u_0201_10V6K

C205
0.1u_0201_10V6K
Q29 @

D
@
1

Q30 D SUSP 1 2
PCH_PWR_EN 2 R201 0_0402_5%
49,61 PCH_PWR_EN 1 @ 2 2
G C130

G
@

1
0.01U_0201_10V6K 1

em
S 2N7002KW_SOT323-3

C202
0.1u_0201_10V6K
@ @ R202
3

2
1

@ 470K_0402_5%
@
R162 PCH_PWR_EN#_R 2

2
100K_0402_5%
@ 1
2

C131
0.1u_0201_10V6K

ch
@
2

1
R87
100K_0402_5%
@ 8/29 Add +1.8VS Circuit for Audio wei

kS
2
For DisCharge
oo
+0.6VS +2.5V_DDR
+5VLP +5VALW

1
R159 R278
1

eb

47_0603_5% 200_0402_5%
R156 R157
@ @
100K_0402_5% 100K_0402_5%
@

2
2

3 3

1
D Q11 D Q33
SUSP
39 SUSP 2 SUSP 2 SUSP
ot

G G

S 2N7002KW_SOT323-3 S 2N7002KW_SOT323-3

3
@ @
1

Q10 D
2
N

45,49,60 SUSP# G

S 2N7002KW_SOT323-3
3

08/29: Need double check enable signal and the resistance

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2018/09/20 DC V TO VS INTERFACE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
FG541/FG741 1.0

Date: Tuesday, March 26, 2019 Sheet 51 of 69

A B C D E
 5 4 3 2 1

B2 A2
D
+3VLP PCH_PWR_EN# 2 D

Q25,+3V_PCH

V
V
AC A1
MODE VIN
A2 A4 B5

V V
3 +3V_PCH
PU301 PU904

V
B+
BATT BATT V +3VALW
1
DPWROK_EC
V
MODE

V
B1
4
PCH_RSMRST#
EC

coV V
m
14
PM_DRAM_PWRGD
5 PBTN_OUT#

V
EC_ON PM_SLP_S3# PCH 15
PM_SLP_S4# H_CPUPWRGD CPU
A3 B4

V V
PM_SLP_S5#

s.
PM_SLP_SUS# 6
CPU_PLTRST# 16

V
12

ic
PCH_PWROK

V
C C

at
B3 13
SYS_PWROK

V
V
ON/OFF V

em
NOVO

NVDD_PWR_EN

ch
(DIS)
Vb
+VGA_CORE
+1.35V

V
11 VR_REDY SYSON 7 PU801
PU501

V
kS
DGPU_PWROK
DGPU_PWR_EN
oo
10 Va (DIS)
+1.5VS_VGA

V
PU901 VR_ON Q31

V
PU601
V

+CPU_CORE

V
+5VS
eb

B B
Q32 +1.05VSP_VGA

V
ot

SUSP#,SUSP 9 +3VS PU702

VGA

V
N

PU602

V
+1.5VS +3VS_VGA

V
Q27
PU502

V
+0.675V
8
SUS_VCCP PU701
V
+1.05VS

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2018/09/20 Power sequence block

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FG541/FG741
Date: Tuesday, March 26, 2019 Sheet 52 of 69
5 4 3 2 1
 5 4 3 2 1

ZZZ8 HDMI@ UC1 I7_MP@

UC1 I5_MP@
ZZZ1 PCB@ UC1 I5_QS@

HDMI PN S IC CL8068404121905 SRF6X U0 2.4G 12 ! S IC CL8068404121817 SRF6U U0 2.6G 12 !

PCB 1B4 NM-C362 REV1 M/B RO00000040J SA0000A0N10 S IC CL8068404121905 QRR5 U0 2.4G BGA
SA0000A0P10
DA800013U10
PCB_MB HDMI Logo SA0000A0P00
MP CPU OS CPU

UL1 8111H@ UL1 8111GUL@ UH1 PCH_QS@

UH1 PCH_MP@

D D
RTL8111H-CG RTL8111GUL-CG S IC FHHM370 QNYF B0 FCBGA 874P PCH
SA000074W00 SA000060V00 S IC FH82HM370 SR40B B0 BGA 874P PCH 12! SA000096P00
LAN Chip SA00009AG00
MP PCH
QS PCH

TL1 GST@ TL1 2ND_TR@ TL2 AJOHO@ TL2 INPAQ@

UV1 GPU@

BOTH_GST5009 LF BOTH_GST5009 LF FORM_ N-8660GR FORM_ IN-8660GR

SP050008G00 SP050008M00 SP050009K00 SP050009Q00 N17P-G0-K1-A1
Transformer New Transformer
SA00009XZ00

GPU

m
ZZZ4 DRAM_S8G@ ZZZ2 DRAM_M8G@ ZZZ3 DRAM_H8G@ ZZZ9 M8GX3@ ZZZ11 S8GX3@ ZZZ10 H8GX3@

co
ALT. GROUP PARTS SAMSUNG D4G FG541ALT. GROUP PARTS MICRON D4G FG541
ALT. GROUP PARTS HYNIX D4G FG541 ALT. GROUP PARTS MICRON V3G FG541 ALT. GROUP PARTS SAMSUNG V3G FG541ALT. GROUP PARTS HYNIX V3G FG541
X7646T1200A X7646T1200B X7646T1200C X7646T12007 X7646T12008 X7646T12009
DRAM X76 BOM VRAM X76 BOM

s.
UD1 MD_S8Gb@ UD2 MD_S8Gb@ UD3 MD_S8Gb@ UD4 MD_S8Gb@ RH775 MD_S8Gb@ RH777 MD_S8Gb@ RH195 MD_S8Gb@
UV10 S8G_VR@ UV6 S8G_VR@ UV8 S8G_VR@ RV194 S8G_VR@ RV193 S8G_VR@ RV192 S8G_VR@ PR5512 S8G_VR@

ic
C K4A8G165WC-BCTD K4A8G165WC-BCTD K4A8G165WC-BCTD K4A8G165WC-BCTD 10K_0402_5% 10K_0402_5% 10K_0402_5% C
SA00008PE00 SA00008PE00 SA00008PE00 SA00008PE00 SD02810028J SD02810028J SD02810028J K4G80325FB-HC28 K4G80325FB-HC28 K4G80325FB-HC28 100K_0402_5% 100K_0402_5% 100K_0402_5% 41.2K_0402_1%

at
SA000081C00 SA000081C00 SA000081C00 SD02810038J SD02810038J SD02810038J
SD000009K0J
2666MT/s DRAM_Samsung 8G
VRAM_Samsung 8GX3

em
UD1 MD_H8Gb@ UD2 MD_H8Gb@ UD3 MD_H8Gb@ UD4 MD_H8Gb@ RH775 MD_H8Gb@ RH777 MD_H8Gb@ RH163 MD_H8Gb@

UV10 H8G_VR@ UV6 H8G_VR@ UV8 H8G_VR@

RV189 H8G_VR@ RV193 H8G_VR@ RV187 H8G_VR@ PR5512 H8G_VR@

H5AN8G6NCJR-VKC H5AN8G6NCJR-VKC H5AN8G6NCJR-VKC H5AN8G6NCJR-VKC 10K_0402_5% 10K_0402_5% 10K_0402_5%

SA000090T10 SA000090T10 SA000090T10 SA000090T10 SD02810028J SD02810028J SD02810028J

2666MT/s DRAM_Hynix 8G H5GC8H24AJR-R0C H5GC8H24AJR-R0C H5GC8H24AJR-R0C

ch
SA000081630 SA000081630 SA000081630 100K_0402_5% 100K_0402_5% 100K_0402_5% 41.2K_0402_1%
SD02810038J SD02810038J SD02810038J
VRAM_Hynix 8GX3 SD000009K0J

UD1 MD_M8Gb@ UD2 MD_M8Gb@ UD3 MD_M8Gb@ UD4 MD_M8Gb@ RH775 MD_M8Gb@ RH776 MD_M8Gb@ RH195 MD_M8Gb@

kS
UV10 M8G_VR@ UV6 M8G_VR@ UV8 M8G_VR@ RV189 M8G_VR@ RV193 M8G_VR@ RV192 M8G_VR@ PR5512 M8G_VR@

MT40A512M16LY-075:E MT40A512M16LY-075:E MT40A512M16LY-075:E MT40A512M16LY-075:E 10K_0402_5% 10K_0402_5% 10K_0402_5%

SA00008F930 SA00008F930 SA00008F930 SA00008F930 SD02810028J SD02810028J SD02810028J
MT51J256M32HF-70:B MT51J256M32HF-70:B MT51J256M32HF-70:B 100K_0402_5% 100K_0402_5% 100K_0402_5% 41.2K_0402_1%
2666MT/s DRAM_Micron 8G SA000081730 SA000081730 SA000081730 SD02810038J SD02810038J SD02810038J
SD000009K0J
oo VRAM_Micron 8GX3
eb

ZZZ14 M8GX3_NEW@

B B

ALT. GROUP PARTS MIC V3GB FG541

ot

X7646T1200D

NEW VRAM X76 BOM

NEW DRAM X76
N

UD1 MD_HTM8Gb@ UD2 MD_HTM8Gb@ UD3 MD_HTM8Gb@ UD4 MD_HTM8Gb@ RH775 MD_HTM8Gb@ RH776 MD_HTM8Gb@ RH163 MD_HTM8Gb@ UV10 M8G_VR1@ UV6 M8G_VR1@ UV8 M8G_VR1@ RV189 M8G_VR1@ RV193 M8G_VR1@ RV192 M8G_VR1@ PR5512 M8G_VR@

HTH5AN8G6NAFR-VKD HTH5AN8G6NAFR-VKD HTH5AN8G6NAFR-VKD HTH5AN8G6NAFR-VKD 10K_0402_5% 10K_0402_5% 10K_0402_5% MT51J256M32HF-80 :B MT51J256M32HF-80 :B MT51J256M32HF-80 :B 100K_0402_5% 100K_0402_5% 100K_0402_5% 41.2K_0402_1%
SA0000A3C00 SA0000A3C00 SA0000A3C00 SA0000A3C00 SD02810028J SD02810028J SD02810028J SA00007Z930 SA00007Z930 SA00007Z930 SD02810038J SD02810038J SD02810038J
SD000009K0J

NEW DRAM 2666MT/s DRAM_Micron 8G NEW VRAM VRAM_Micron 8GX3

UD1 MD_SMT8Gb@ UD2 MD_SMT8Gb@ UD3 MD_SMT8Gb@ UD4 MD_SMT8Gb@ RH774 MD_SMT8Gb@ RH777 MD_SMT8Gb@ RH195 MD_SMT8Gb@ GPU FB Memory (GDDR5) RAMCFG[4:0] STRAP2 STRAP1 STRAP0

Samsung 8Gb K4G80325FB-HC28 0(0x0000) L/RV194 L/RV193 L/RV192

SDQC8G8W16XCTD9N1TSDQC8G8W16XCTD9N1T SDQC8G8W16XCTD9N1T SDQC8G8W16XCTD9N1T 10K_0402_5% 10K_0402_5% 10K_0402_5% Micron 8Gb MT51J256M32HF-70:B 4(0x0004) H/RV189 L/RV193 L/RV192
SA00009RR00 SA00009RR00 SA00009RR00 SA00009RR00 SD02810028J SD02810028J SD02810028J
NEW DRAM 2666MT/s DRAM_SMART 8G N17P-G0-K1 Hynix 8Gb H5GC8H24AJR-R0C 5(0x0005) H/RV189 L/RV193 H/RV187

Micron 8Gb MT51J256M32HF-80 :B 4(0x0004) H/RV189 L/RV193 L/RV192

DRAM Memory Down(DDR4) DRAMCFG PCH_GPA23 PCH_GPA22 PCH_GPA21
Samsung 8Gb
2666 MT/s K4A8G165WC-BCTD 0(0x000) L/RH775 L/RH777 L/RH195
A A
Hynix 8Gb
8Gb 2666 MT/s H5AN8G6NCJR-VKC 1(0x001) L/RH775 L/RH777 H/RH163
Micron 8Gb
2666 MT/s MT40A512M16LY-075:E 2(0x010) L/RH775 H/RH776 L/RH195
Micron 8Gb
2666 MT/s HTH5AN8G6NAFR-VKD 3(0x011) L/RH775 H/RH776 H/RH163
Smart 8Gb
2666 MT/s SDQC8G8W16XCTD9N1T 4(0x100) H/RH774 L/RH777 L/RH195

5(0x101) H/RH774 L/RH777 H/RH163 Security Classification LC Future Center Secret Data Title

6(0x110) H/RH774 H/RH776 L/RH195

Issued Date 2015/08/20 Deciphered Date 2018/09/20 Virtual symbol
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
SODIMM only 7(0x111) H/RH774 H/RH776 H/RH163 DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
FG541/FG741 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Tuesday, March 26, 2019 Sheet 53 of 69

5 4 3 2 1
 5 4 3 2 1

GPU Thermal Holex2 Close to RJ45 DC-IN x2

CPU Thermal Holex3 WLAN Standoff

H10 H11
H1 H2 H3
HOLEA HOLEA
D HOLEA HOLEA HOLEA D
PCB Fedical Mark PAD

1
1

1
FD1 FD2 FD3 FD4 FD5 FD6
PAD_CT5P5B6P0D2P4 PAD_CT5P5B6P0D2P4
PAD_D2P4 PAD_D2P4 PAD_D2P4
1

1
H4 H5 H6 H7 H8 H13 H14
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA

1
m
PAD_C6P0D4P0 PAD_C6P0D4P0 PAD_C6P0D4P0 PAD_C6P0D4P0 PAD_C6P0D4P0 PAD_C6P0D3P3 PAD_C6P0D3P3

co
s.
H16 H17 H18
H9 H12 H15
C HOLEA HOLEA HOLEA C
HOLEA HOLEA HOLEA

ic

1
1

1
at
PAD_C2P7D2P7N PAD_CT6P0B7P0D3P7 PAD_D3P4x2P7 PAD_CT5P6B7P0D3P0 PAD_CT5P6B7P0D3P0 PAD_C7P0D3P0
CHASSIS1_GND

em
Close to Audio jack

follow layout list update 20181010SF

ch
kS
SH7 ME@ SH8 ME@ SH9 ME@
oo
B 1 1 1 B
1 1 1
eb

SHIELDING_SUL-35A2M_9P2X3P3_1P SHIELDING_SUL-35A2M_9P2X3P3_1P SHIELDING_SUL-35A2M_9P2X3P3_1P

ot

SH10 ME@ SH11 ME@ SH12 ME@

1 1 1
N

1 1 1

SHIELDING_SUL-35A2M_9P2X3P3_1P SHIELDING_SUL-35A2M_9P2X3P3_1P SHIELDING_SUL-35A2M_9P2X3P3_1P

USB3.0 Shielding
DDR4 Shielding
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2018/09/20 Hole
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
B
FG541/FG741 1.0

Date: Tuesday, March 26, 2019 Sheet 54 of 69

5 4 3 2 1
 5 4 3 2 1

D D

m
co
s.
C C

ic
at
em
ch
kS
B
oo B
eb
ot
N

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2018/09/20 Cover Page

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
D 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FG541/FG741
Date: Tuesday, March 26, 2019 Sheet 55 of 69
5 4 3 2 1
 5 4 3 2 1

D D

m
co
s.
C C

ic
at
em
ch
kS
oo
B B
eb
ot
N

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2018/09/20 Cover Page
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
B
FG541/FG741 1.0

Date: Tuesday, March 26, 2019 Sheet 56 of 69

5 4 3 2 1
 5 4 3 2 1

B+ +5VLP/ 100mA
Richtek Silergy
Adaptor RT6585B +5VALW/10A SY8032 +1.0VGS/2A
D
EC_ON_5V EN1 Switch Mode Converter
D

FOR SYS ALW_PWRGD 1V0_MAIN_EN EN

135W/20V PGOOD FOR GPU PGOOD
Page 60
Page 70
EC_ON EN2 +3VLP/ 100mA

+3VALW/ 8A GMT
G9661 +2.5V/600mA
SYSON EN LDO
FOR DDR PGOOD

Richtek Page 62
+1.2V/10A
RT8231

m
Switch Mode +0.6VS/1A
SYSON S5 FOR DDR Silergy

co
SM_PG_CTRL S3 Page 61 PGOOD
SY8033 +1.8VALW/3.4A
EC_ON_1.8V EN Converter
FOR GPU PGOOD
Page 70

s.
Silergy
TI SY8286 +1.05VALW/ 6A
Converter

ic
C
BQ24780SRUYR FOR PCH
C

EC_ON_1V EN PGOOD
Battery Charger Page 63

at
Switch Mode
Page 59 AOS

em
RT8237E FBVDDQ/ 20A
Converter
VRAM_VDDQ_ADJ EN PGOOD VDDQPWROK
FOR GPU
Page 69

ch
SMBus

Silergy
SY8286 VCCIO/ 6A

kS
Converter
SUSP# EN FOR CPU PGOOD VCCIO_PG
Page 64
oo
MPS VCC_CORE/80A/124A

MP2949
eb

B VCCGT/25A/32A B
Switch Mode
FOR CPU Core VCCSA/10A
CPUCORE_ON EN
Page 65-68 PGOOD
ot

CPU_PWRGD

Battery Richtek
Li-ion RT8813D
N

NVVDD/60A/127A
3S1P/52.5WH Switch Mode
NVVDD_EN EN FOR GPU NVVDD PGOOD NVVDD_PWRGD
Page 71

Richtek
NCP81278 NVVDDS/18A/30.7A
Switch Mode
NVVDDS_EN EN FOR GPU NVVDD PGOOD NVVDDS_PWRGD
Page 71

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/26 Deciphered Date 2018/09/20 Power Diagram

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
FG541/FG741 1.0

Date: Tuesday, March 26, 2019 Sheet 57 of 69

5 4 3 2 1
 5 4 3 2 1

+3VL
PL101 EMC@
HCB2012KF-121T50_0805
VIN
1 2
JDCIN1

1
PL102 EMC@

2 APDIN
HCB2012KF-121T50_0805
1 2
PR101
0_0402_5%
VCCRTC
POWER1
7 4 PD101

EMC@

EMC@
GND4 POWER2 RTC_VCC

2
PR103

1000P_0402_50V7K
3 BAT54CW_SOT323-3

PC104 EMC@
ADAPTER_ID 49,58

0.1U_0402_25V6
1000P_0402_50V7K
6 DETECT 1 2 VCCRTC_D 3

PC101 EMC@

0.1U_0402_25V6
GND3

1
1
D GND1 45.3K_0402_1% 1 D
5 JRTC1
PR104

PC103
GND2 @

2
1 1 2 RTC_VCC_R 2

PC102
1 2
2 3 1K_0402_1%
HIGHS_PJSSS56-B5000-1H GND1 4
ME@ GND2

1
PC105
HIGHS_WS33020-S0351-HF 1U_0402_10V6K
ME@ @

2
DC IN：1.DC IN connect apply for PN HIGHS_PJSSS56-B5000-1H_5P-T ,need replace
connector rate current 7A RTC：1. 0ohm delete
2.the max VCCRTC < 3.2V specification

m
3.RTC cable 35mm

co
s.
ic
C C

at
PL103 EMC@
HCB2012KF-121T50_0805
ME@ 1 2

em
ALLTO_C51126-112Z9-C
JBATT1 VMB BATT+
1 PL104 EMC@
1 2 HCB2012KF-121T50_0805
2 3 1 2
3 4
4 5 EC_SMCA
5 6 EC_SMDA

ch
6 7
7 8
3

1
PC106 PC107
8 9
9 10
1000P_0402_50V7K 0.01U_0402_25V7K +3VALW
10 11 EMC@ EMC@
2

2
11 12

kS
12 13
1

100_0402_1%

GND1 14
PR105

GND2 15
1

100_0402_1%

GND3 16
PR106

GND4

1
2

oo PR109
2

PD103 750_0603_1%
EC_SMB_CK1 49,59
AZC199-02S.R7G_SOT23-3

2
EMC_NS@
EC_SMB_DA1 49,59
eb

ADAPTER_ID 49,58

680P_0402_50V7K
PR107 1 2 100K_0402_1%
+3VALW

AZ5123-01F.R7GR_DFN1006P2X2
B B
@

1
0.1U_0402_25V6
ot

1
PC108

PC109

PD102
BATT_TEMP_IN 1 2 @
BATT_TEMP 49,59 A/D

2
PR108
10K_0402_1%

2
N

battery IN:
1.20180821SF update to SP011808066
2.battery connector 12pin per pin 4.5A

ADP_ID:1. cost down solution

2.EC initial ID function

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2018/09/20 Cover Page

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
FG541/FG741 1.0

Date: Tuesday, March 26, 2019 Sheet 58 of 69

5 4 3 2 1
 5 4 3 2 1

D D

PQ311 N1 PQ312 N2
AON6366E_DFN8-5 AONS32314_DFN8-5
PR301
1 1 0.01_1206_1%
2 2

VIN 3 3 5 1 4
V20B+
2 3 1 PQ314

1
PC353

0.01U_0402_25V7K

0.01U_0402_25V7K
4

5
PC351 PC352 AONS32314_DFN8-5

1
4700P_0402_50V7K 2200P_0402_50V7K 0.01U_0402_25V7K

EMC@

EMC@
ACDRV_FG

PC303

PC304

2
2
EMC@ EMC@
5

EMC@

2
2

2
ACDRV_BG
470P_0402_50V7K

0.022U_0402_25V7K
BQ24780_BATDRV 4
PC301

m
1

PC302
4.7_0603_5%
PR302
2

3
2
1
1
0.1U_0402_25V7-K PR303

co
499K_0402_1%
PC305
2

PC308

2
1 2 0.01U_0402_25V7K

2
VIN VIN BATT+

0.1U_0402_25V7-K

0.1U_0402_25V7-K
1

s.
PC306
V20B+

PC307
BAT54CW_SOT323-3

2
2

ic
PD301
4.02K_0603_1%

4.02K_0603_1%
1

C C
PR310

PR311

at
1

DIS_CHG
10U_0805_25V6K

10U_0805_25V6K
2200P_0402_50V7K
1

PC310
2

2
PR313

PC313

PC314
43K_0402_1% PR314

em

EMC@
10_1206_5%

1
ACN
ACP
BQ24780_VDD
2

1
PR315

1
2 1
PC315 PC316

ACN
ACP
1U_0603_25V6K 2.2U_10V_K_X5R_0603

ch
7.15K_0402_1%

5
1 2 780_VCC 28 24 1 2
VCC REGN

AON6380_DFN8-5
1 2 ACDET 6 0.047U_0603_16V7K
ACDET PR316 PC318

PQ316
PC309 25 BST_CHG 1 2 2 1
0.01U_0402_25V7K BTST 4

kS
2.2_0603_5%
CMSRC 3 26 DH_CHG
CMSRC HIDRV 2.2UH_PCMB063T-2R2MS_8A_20% PR317
ACDRV 4 PL301 0.01_1206_1%
ACDRV

3
2
1
BATT+
BQ24780SRUYR_QFN28_4X4
27 PH_CHG 1 2 1 4
PHASE
oo

5
PR325 1 2 0_0402_5% ACIN_R 5 2 3
ACOK

1
49 ACIN
PR320 1 2 0_0402_5% EC_SMB_DA1_R 11 PR321
SDA

AON6380_DFN8-5
49,58 EC_SMB_DA1 23 DL_CHG 2.2_0805_5%
LODRV
PU301

EMC_NS@ PC327

PQ317

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
2

2
PR322 1 2 0_0402_5% EC_SMB_CK1_R 12 22 4 2 1

PC340

PC319
eb

SCL GND

1 2
49,58 EC_SMB_CK1

PC320

PC342
0.1U_0402_25V7-K

0.1U_0402_25V7-K

0.1U_0402_25V7-K

1
PR323 1 2 0_0402_5% ADP_I_R 7 29 PC321
49 ADP_I IADP PAD

1
PC324 1000P_0402_50V7K

PC322

PC323
3
2
1

2
B BQ24780_BATDRV B
100P_0402_50V8J PC325 1 2 100P_0402_50V8J IDCHG 8 18 EMC_NS@
1 2 IDCHG BATDRV
@

2
ot

9
49,63 Psys PMON 17 PR338 2 110_0603_5%
0_0402_5% BATSRC
PR341 SRP_R
20 2 1 SRP
20K_0402_1%

100P_0402_50V8J

SRP
2

1 2 10 PR328 10_0603_5%
49 VR_HOT# PROCHOT#
N
PR340

13
PC341

CMPIN
BATPRES#

14
TB_STAT#

CMPOUT
1

19 SRN_R 2 1 SRN
ILIM 21 SRN PR329 10_0603_5%
ILIM
16

15
2

PR330
0_0402_5%
TB_STAT#
1

1 2 ILIM_R 1 2
+3VALW BATT_TEMP 49,58
PR331 PR332
0.1U_0402_25V7-K

143K_0402_1% 32.4K_0402_1%
2

PC328

PR333
100K_0402_1%
1

A A

charge current：1C 5A
charge voltage：12.6V
charge frequency：800K
ILIM pin：charge7A, turbo-discharge-10A
Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2018/09/20 Cover Page

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
FG541/FG741 1.0

Date: Tuesday, March 26, 2019 Sheet 59 of 69

5 4 3 2 1
 5 4 3 2 1

D D

V20B+
@ +5VLP
1.5A 2
PJ3501
1 +3VALW_VIN
2 1 PU401 Vout=3.3V±5%

25
0.1U_0201_25V6-K
LV5083AGQUF_UQFN36_5X4
Vset=3.37V±1.5%

10U_0805_25V6K

10U_0805_25V6K
1

1
JUMP_43X79 PR3511 PC3541

EMC@
+3VALW

PC3535

VDDSW
+3VALW_BS 1
3 2 1 2
OCP=12A

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
PC3534

PC3536
11 BOOT1 10_0603_5%
VIN1 PL3501

2
1 +3VALW_LX
0.1U_0603_25V7-M
1 2 +3VALW_P 2
PJ3502
1
8A OVP=(1.15~1.25)*Vout
LX1_1 2 2 1
1
PR5913
2 +3VALW_EN 10 LX1_2 35 2.2UH_PCMB063T-2R2MS_8A_20% JUMP_43X79
UVP=(0.55~0.65)*Vout
EN1 LX1_3 1 1 1 1
44,49,60,61 EC_ON @
Fsw=500Khz

1
@ 6 +3VALW_P

m PC3539

PC3543

PC3544

PC3542
0_0402_5% PC3537 +3VALW_PG 9 VOUT1
0.1U_0201_25V6-K PGOOD1 +3VALW 2 2 2 2

2
PC3538
4
V20B+ VBYP3

co
1 2 7
VCC1 +3VLP PC3545
@ 1U_0402_25V6-K
100mA +3VL
2.5A 2
PJ3503
1 +5VALW_VIN LDO3
5 1 2
+3VLP @
2 1 PJ3505
0.1U_0201_25V6-K
4.7U_0603_6.3V6K 2 1

s.
PR3512

10U_0805_25V6K

10U_0805_25V6K
2 1
1

1
JUMP_43X79 PC3554
EMC@
PC3546

PC3547

PC3548
14 22 +5VALW_BS 1 2 1 2
VIN2 BOOT2 JUMP_43X39 +5VALW
+3VALW
2

2
23 10_0603_5% 0.1U_0603_25V7-M PL3502 PJ3504
8A Vout=5V±3%

ic
LX2_1 24 +5VALW_LX 1 2 +5VALW_P 2 1
LX2_2 36 2 1
1 2 +3/5VALW_EN 15 LX2_3
1.5UH_PCMB063T-2R2MS_8A_20%
Vset=5.1V±1.5%

22UC_6.3VC_MC_X5RC_0603
C 1 1 1 1 JUMP_43X79 C
44,49,60,61 EC_ON EN2 19 +5VALW_P
OCP=12A

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
@

at
PR5914 VOUT2

PC3555

PC3552

PC3553

PC3551
1

0_0402_5%
+5VALW 2 2 2 2 OVP=(1.15~1.25)*Vout
2

PC3549 16
100K_0402_5%

100K_0402_5%

PGOOD2
2

0.1U_0201_25V6-K
UVP=(0.55~0.65)*Vout
PR3513

@
PR3514

em
PC3550 VBYP5
21
Fsw=500Khz
+5VLPPC3559
1

1 2 18
@ VCC2
1

100mA

+3VALW_LX

+5VALW_LX
ALW_PWRGD 16 20 1 2
1U_0402_6.3V6-K
+3VALW_PG

LDO5
+3VALW
4.7U_0603_6.3V6K
Need Short

ch
33
VINSW1

1
1 @ +3VS
PJ3506 PR3508 PR3509
PC3566 29 +3VS_SW 1 2 2.2_0805_5% 2.2_0805_5%
22UC_6.3VC_MC_X5RC_0603 VOUTSW1 1 2 EMC_NS@ EMC_NS@
2 @ 1

1
JUMP_43X79

kS

+3VALW_SN 2

1+5VALW_SN 2
31 3VS_SS PC3564 @
SS1 22UC_6.3VC_MC_X5RC_0603 PC5978

2
2

2
1 2 +3VS_EN 30 @ 0.1U_0201_25V6-K
45,49,51 SUSP# ENSW1 PC3562
PR5915 +5VALW 2200p_0402_25V7-K @ +5VS

1
0_0402_5% PJ3507
oo
2

34 28 +5VS_SW 1 2
VINSW2 VOUTSW2 1 2

1
PC3530 1 PC3533
1U_0402_25V6-K 1 JUMP_43X79 PC3532 1000P_0402_50V7K
1

2
1
PC3565 26 5VS_SS @ 1000P_0402_50V7K EMC_NS@
SS2

2
22UC_6.3VC_MC_X5RC_0603 PC3563 PC5979 EMC_NS@
2

2
PGND_2

PGND_1

AGND_2

AGND_3

AGND_1

@ 27 22UC_6.3VC_MC_X5RC_0603 0.1U_0201_25V6-K
ENSW2

2
PC3561 2
eb

@
2200p_0402_25V7-K

1
1 2 +5VS_EN
8
13

12

17

32
2

PR5916
B B
0_0402_5% PC3531
1U_0402_25V6-K
1

ot
N

VOUT=3.07V
TDC=6A
OCP=10A
Fsw=600Khz

VOUT=5.01V
TDC=8A
A OCP=12A A

Fsw=600Khz

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2018/09/20 Cover Page

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
FG541/FG741 1.0

Date: Tuesday, March 26, 2019 Sheet 60 of 69

5 4 3 2 1
 A B C D

PR501 1 2 0_0402_5% VDDQ_EN

49,51 SYSON
PC508 @
0.1U_0402_10V7K
2 1

PR503 1 2 0_0402_5% VTT_EN

6 CPU_DRAMPG_CNTL
PC503 @
0.1U_0402_10V7K
2 1

+1.8VALW _B_EN
49,51 PCH_PWR_EN
PR507 1 2 0_0402_5% PMIC_VCC
PC506 @
1
0.1U_0402_10V7K PR520 1

2 1 PR521
10_0603_5%
1 2 1 2
+5VLP EC_ON 44,49,60
PR506 1 2 0_0402_5% +1.05VALW_EN PC500
2.2U_10V_K_X5R_0603 0_0402_5%
PC505 @ 1 2
0.1U_0402_10V7K
2 1
PR505
VDDQ_VIN 1 2
10_0402_1%
PR508 1 2 0_0402_5% +2.5V_DDR_EN

VSYS_PMIC
49 EC_VPP_PWREN PC502
SH00000PK0J, S COIL 0.47UH +-20% PCMB063T-R47MS 18A

PMIC_EN
PC504 @ 1 2
0.1U_0402_10V7K
2 1 1U_0402_25V6-K +3VALW

28

27

41
9
PMIC_EN
VCC

GND
VSYS
PR525 2 1 1M_0402_5% +1.8VALW _L_EN
+2.5V_DDR_EN 29 25 PMIC_SMB_DAT1 PR510 1 2 0_0402_5%
EN_LDO1 SDA EC_SMB_DA3 49,63

100K_0402_1%
+1.8VALW _L_EN 1 26 PMIC_SMB_CLK1 PR511 1 2 0_0402_5%
EN_LDO2 SCL EC_SMB_CK3 49,63

1
PR513
R_0402
+1.05VALW_EN 11 24 PMIC_ALERT# PR512 2 1 0_0402_5%
EN_V1P0A OT H_PROCHOT# 6,49,63
+1.8VALW _B_EN 16 22 +1.05VALW_PG @ 1 PAD PTC501
EN_V1P8A PG_V1P0A @

2
VDDQ_EN 31 21 +1.8VALW _B_PG 1 PAD PTC502
EN_VDDQ PG_V1P8A @
VTT_EN 36 23 VDDQ_PGOOD
EN_VTT PG_VDDQ VDDQ_PGOOD 49
@

m
PL503
PJ502
PJ501 @1 12 LX_1P05 1 2 +1.05VALW_FB 2 1 +1.05VALW

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
2 +1.05VALW_B_VIN 7 LX_V1P0A1 13 2 1
+5VALW 2 1 VIN_V1P0A1 LX_V1P0A2

EMC_NS@
8 14 PR535 PC544 0.47UH_PCMB063T-R47MS_18A_20% 1 1 1 1 1 1 JUMP_43X79
VIN_V1P0A2 LX_V1P0A3

0.1U_0402_10V7K
1 15 4.7_0603_5% 1200P_0402_50V7-K
JUMP_43X39 PC509 LX_V1P0A4

1
1 2 1 2

PC511

PC512

PC513

PC514

PC515

PC516
10 +1.05VALW_FB
EMC_NS@ EMC_NS@

PC510

co
22UC_6.3VC_MC_X5RC_0603 VO_V1P0A 2 2 2 2 2 2

2
2
PJ503 17
@
@1 PL502 @ @ PJ504
2 +1.8VALW _B_VIN 19 LX_V1P8A1 18 LX_1P8 1 2 +1.8VALW _FB 2 1 +1.8VALW
+5VALW 2 1
1
VIN_V1P8A LX_V1P8A2
20 +1.8VALW _FB
PR536 PC539
4.7_0603_5% 1200P_0402_50V7-K
1UH_PH041H-1R0MS_3.8A_20% 2
JUMP_43X79
1

JUMP_43X39 VO_V1P8A 1 1
PC534 1 2 1 2
22UC_6.3VC_MC_X5RC_0603
2 PC517 33 UG_VDDQ EMC_NS@ EMC_NS@ PC535
22UC_6.3VC_MC_X5RC_0603
PC536
22UC_6.3VC_MC_X5RC_0603

s.
2 1 2 +1.2V_P 38 UGATE_VDDQ 0.1U_0603_25V7-M 2 2 2

VIN_VTT 32 BST_VDDQ 1 2 2 1
PJ505 BS_VDDQ @
@1 10U_0603_6.3V6M PR526 PJ508
2 VTT 39 0_0603_5% PC518 VDDQ_VIN 2 1 V20B+
+0.6VS 2 1
1
VTT
LX_VDDQ
34 LX_VDDQ 2 1

0.1U_0402_25V7-K
5

ic
10U_0805_25V6K

10U_0805_25V6K
JUMP_43X39 40 35 LG_VDDQ JUMP_43X39

EMC@
PC519

PC524
VSNS_VTT LGATE_VDDQ

AON7380_DFN8-5

1
22UC_6.3VC_MC_X5RC_0603

PC525

PC526
2 PR515 @ 37 +1.2V_P

PQ501
1 2 CS_VDDQ 30 VSNS_VDDQ
CS_VDDQ

2
UG_VDDQ 4
33K_0402_1%

at
PJ506 @1 PJ507 @1
2 +2.5V_DDR_VIN 5 6 +2.5V_P 2
+3VALW 2 1
2
VIN_LDO1 LDO1 2 1
+2.5V_DDR

3
2
1
1 0.47UH_PCMB063T-R47MS_18A_20%
JUMP_43X39 PC521 JUMP_43X39
@

22UC_6.3VC_MC_X5RC_0603
PL501 PJ509
10U_0603_6.3V6M
+1.2V

PC520
1 LX_VDDQ 1 2 +1.2V_P 2 1
3 2 2 1

em
LDO2

2
4
VIN_LDO2 JUMP_43X79

5
2 2.2_0805_5% 1 1 1 1 1 1
FB_LDO2 PR518

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
AON7516_DFN8-5
EMC_NS@

PC538

PC527

PC528

PC529

PC530

PC531
PU501

1
2 2 2 2 2 2

PQ502
LV5075BGQV_QFN40_5X5 LG_VDDQ 4

1
@ @
PC533
1000P_0402_50V7K

2
EMC_NS@

3
2
1
ch
1.2V: setting 1.21V

kS
TDC:8A
OCP:125mV/25A
OVP:120%
frequency:1Mhz
0.47UH_PCMC063T-R47MN_17.5A_20% DCR no limit
3
oo 1.05V: setting 1.05V
3

TDC:6A
OCP:10A
OVP:120%
frequency:1Mhz
1.8V: setting 1.81V
eb

TDC:3A
OCP:6A
OVP:120%
frequency:1Mhz
ot
N

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2018/09/20 Cover Page

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
D 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FG541/FG741
Date: Tuesday, March 26, 2019 Sheet 61 of 69
A B C D
 A B C D

1 1

+3VS

1
@

m
PR704
100K_0402_1%

PU702

co
2
PJ701
2 1 +VCCIO_VIN 5 9 +VCCIO_PG
V20B+ 2 1 IN1 PG +VCCIO_BS

SY8286RAC_QFN20_3X3
4 1 1 2
@ JUMP_43X79 3 IN2 BS PC702
2 IN3 0.1U_0603_25V7-M PL701

2200P_0402_50V7K
IN4

s.
6 1UH_PCMB063T-1R0MS_12A_20% @

EMC@
10U_0805_25V6K

10U_0805_25V6K
LX1
2

1
7 19 PJ2402
PC701

PC703

PC704
8 GND1 LX2 20 +VCCIO_SW 1 2 +VCCIO_P 2 1
2

18 GND2 LX3 2 1 VCCIO 2

ic
GND3
1

2
21 JUMP_43X79

EMC_NS@
4.7_0603_5%
GND4

1
14 +VCCIO_FB

PR711
1 1 1 1

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
PR712 FB PR714

at
2 1 13 12 10_0402_1%

PC708

PC709

PC715

PC716
11 ILMT NC3 10
@ EN NC1

1
0_0402_5% 16 PC712 2 2 2 2
NC2

2
15 220P_0402_50V7K
PR701 BYP 17 1 2

em
1 2 +VCCIO_EN VCC
49 EC_VCCIO_EN

680P_0402_50V7K
EMC_NS@
1

PC718
0.1U_0402_10V7K

2.2U_0402_10V6-K
0_0402_5%

1
1

2
PR708 PR709

PC720

2
@
499_0402_1%

PC677
35.7K_0402_1%

ch
2

2
PR713
1 2
VCC_IO_SEN 10

kS
0_0402_5%

1
PR710

60.4K_0402_1%
oo

2
3 3
eb
ot
N

VCCIO:FB=0.6V/0.954V
TDC=6A
OCP:10A
4
OVP:120% 4

frequency:500Khz
remove sense pull high in power side
Security Classification LC Future Center Secret Data Title
Issued Date 2015/08/20 Deciphered Date 2018/09/20 Cover Page
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
FG541/FG741 1.0

Date: Tuesday, March 26, 2019 Sheet 62 of 69

A B C D
 5 4 3 2 1

+3VALW
+3VL
L340 H82 PN:SA00009Q400

1
AGND_2949
PR5842 PR2905
4.7_0402_5% 4.7_0402_5% +3VS
@
PR5841

2
PR5840 0_0402_5%

1
49,59 PSYS 1 2 1 2 AGND_2949
PC2903
@ 1U_0402_10V6K

MP2949A_VDD33
PR2915 0_0402_5% JP2

2
MP2949A_VDD18
1 2 PC2902
1
PC2904 V20B+ 1

10K_0402_1%

10K_0402_1%

10K_0402_1%
6,49 CPUCORE_ON 1

2
4.7U_0603_6.3V6K 1 2 2 5

PR2948

PR2911

PR2912
D
3 2 GND1 6 D
0_0402_5% 2 0.01U_0402_25V7K 4 3 GND2
PR2908 4
VCCST AGND_2949
2 PR2907 1 2 1

1
AGND_2949

44

26
@ CVILU_CI1804M2HR0-NH
PU2901 133K_0402_1%
2M_0402_1% AGND_2949 ME@

1
PC2901

75_0402_1%
100_0402_1%

VDD33

VDD18
45.3_0402_1%
0.1U_0402_25V7-K MP2949A_PSYS 46 47 MP2949A_VINSEN

PR2903

PR2902

PR2901
PSYS VIN_SEN
PR2920

2
MP2949A_EN 37 30 MP2949A_VRRDY 2 1
EN VRRDY CPU_PWRGD 49

1
@
2 PR2904 1 49.9_0402_1% MP2949A_SCLK 27 35 MP2949A_SLPS0# 0_0402_5%
6 SVID_CLK SCLK SLP_S0#
PR2906
2 1 0_0402_5% MP2949A_ALT# 29 32 MP2949A_SDAP
6 SVID_ALERT# ALT# SDA_P

2 PR2909 1 10_0402_1% MP2949A_SDIO# 28 33 MP2949A_SCLP

m
6 SVID_DATA SDIO SCL_P

PMBUS PU at 3V_EC in EE page

PR2918
2 PR5926 1 0_0402_5% 31 36 MP2949A_PE 2 1
6,49,61 H_PROCHOT# VRHOT# PE AGND_2949

PMBUS address: 20H

co
10K_0402_1%

1.43K_0402_1% 2 1 PR2919 MP2949A_VDIFFA 6 +3VALW

VDIFFA 34 +3VALW PR2962
STB SYNC 64,65,66
2.15K_0402_1% 2 1 PR2922 MP2949A_VDIFFB 10

2
VDIFFB 3 2

s.

G
4 1
8.25K_0402_1% 2 1 PR2923 MP2949A_VDIFFC 14
VDIFFC
38 49,61 EC_SMB_DA3 EC_SMB_DA3 MP2949A_SDAP 2.2K_0404_4P2R_5%
PWM6 PWM6_SA 66 6 1

ic

S
D
MP2949A_VFBA 7

5
VFBA 39 PQ294A L2N7002KDW1T1G_SOT363-6

G
MP2949A_VFBB PWM5 PWM5_GT 65
C 11 C
VFBB

at
MP2949A_VFBC 15 40
VFBC PWM4 PWM4_VCORE 64 49,61 EC_SMB_CK3 EC_SMB_CK3 3 4 MP2949A_SCLP

S
D
PQ294B L2N7002KDW1T1G_SOT363-6
41 PWM3_VCORE 64
PWM3

em
PR2925 1 2 0_0402_5% MP2949A_VOSENA 8 42
9 VCCCORE_SENSE VOSENA PWM2 PWM2_VCORE 64

9 VSSCORE_SENSE PR2926 1 2 0_0402_5% MP2949A_VORTNA 9

VORTNA 43
PWM1 PWM1_VCORE 64 CS1_VCORE 64
PR2929 1 2 0_0402_5% MP2949A_VOSENB 12
9 VCCGT_SENSE VOSENB CS2_VCORE 64

ch
9 VSSGT_SENSE PR2930 1 2 0_0402_5% MP2949A_VORTNB 13 CS3_VCORE 64
VORTNB

CS4_VCORE 64
PR2933 1 2 0_0402_5% MP2949A_VOSENC 16
10 VCCSA_SENSE VOSENC
PR2935 1 2 0_0402_5% MP2949A_VORTNC 17 5 PR2934 1 2 1.5K_0402_1%

kS
10 VSSSA_SENSE VORTNC CS1

4 PR2936 1 2 1.5K_0402_1%
CS2 CSSUMA 63
18
63 CSSUMA CS_SUMA
19 3 PR2938 1 2 1.5K_0402_1%
63 CSSUMB CS_SUMB CS3
oo
20
63 CSSUMC CS_SUMC 2 PR2939 1 2 1.5K_0402_1%
CS4

1 PR2940 1 2 1.5K_0402_1% CSSUMB 63

CS5
eb

61.9K_0402_1% 2 1 PR2941 MP2949A_IREF 24 48 PR2942 1 2 1.5K_0402_1%

AGND_2949 IREF CS6 CSSUMC 63
PR2943
B B
1 2
MP2949A_IMONA AGND_2949 CS6_SA 66
21
IMONA
ot

25 MP2949A_ADDRP 0_0402_5%
CS5_GT 65
560P_0402_50V7-K

ADDR_P PR2960
MP2949A_IMONB 22 1 2 MP2949A_VDD18
IMONB
1

PC2906

PR2944 0_0402_5%
N
1

26.1K_0402_1% @
115K_0402_1%

220P_0402_50V7K
2

MP2949A_IMONC 23 45
PR2945

IMONC TEMP TEMP 64,65,66

1

PC2907

332K_0402_1%
2

AGND
PR2946

68P_0402_50V8J
2

2
PC2908

PR2947
2

49

1
MP2949AGQKT-0247-Z_TQFN48_6X6 49.9K_0402_1%
2

PC2909
1.37K_0402_1%
1

PJ2901 @ 1U_0402_10V6K
3.4K_0402_1%

2
PR2951 1 2
PR2949

PR2950

499_0402_1%
JUMPER
2

AGND_2949
AGND_2949

AGND_2949 AGND_2949 AGND_2949

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2018/09/20 Cover Page

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
FG541/FG741 1.0

Date: Tuesday, March 26, 2019 Sheet 63 of 69

5 4 3 2 1
 5 4 3 2 1

8A
1
V20B+

10U_0805_25V6K

10U_0805_25V6K

22U_25V_M
1

1
+
VCCCPUCORE

PC3001

PC3002

PC3004
5
PR5843
PC3003
0.01U_0402_25V7K
@
PQ3001

2
1 2 HG_A1 2
Phase1 AON6380_DFN8-5 EMC@
68A
PU3001 2.2_0402_5%
3 12 4
63 PWM1_VCORE PWM HGATE

330U_D2_2V_Y

330U_D2_2V_Y

330U_D2_2V_Y
VCCCPUCORE

330U_B2_2.5VM_R9M
PC3005 PR3027 1 1 1 1

PC5860
4 1 1 2 1 2
63,64,65,66 SYNC SYNC BST + + + +

PC3006

PC3007

PC3008
2 0.22U_0402_25V6-K 0_0603_5% PL3001
63,64,65,66 TEMP TEMP

3
2
1
0.15UH_PCME064T-R15MS0R667_36A_20%
5 11 SW_A1 1 2 2 2 2 2
63 CS1_VCORE CS SW @

1
13 9 LG_A1 @ @
EPAD LGATE

2
8
PR3001 @ 21pcs 22uf MLCC
1/8W_2.2_5%_0805 PJ3001 PJ3002
D
+5VALW VCC
ISENP
7 EMC@ JUMPER JUMPER D

1
10
GND

2
6

CPUCORE_SN1
ISENN

1
4
1

MP8693GDT-Z_TQFN12_2x3 PR3002
PC3010 PQ3002 2.26K_0402_1%

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
1U_0402_10V6K PC3022 1 1 1 1 1 1 1 1 1 1
2

PC3015
3
2
1

2
1
AON6324_DFN8-5 1 2

PC3011

PC3012

PC3013

PC3014

PC3016

PC3017

PC3018

PC3019

PC3020
PC3021
2200P_0402_50V7K 2 2 2 2 2 2 2 2 2 2
0.47U_0402_25V6K

2
EMC@
4.7K +-1% TSM0A472F34D1RZ @ @
PR3004
PR3005 PH3001 PR3006
1 2 1 2 1 2 1 2

110_0402_1% 511_0402_1% 523_0402_1%

PR3007
1 2

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
PR3008
1 1 1 1 1 1 1 1 1 1
1 2 1.5K_0402_1%

PC3034
PC3031

PC3032

PC3033

PC3035

PC3036

PC3037

PC3038

PC3039

PC3040
110_0402_1%
2 2 2 2 2 2 2 2 2 2

V20B+ @ @

m
10U_0805_25V6K

10U_0805_25V6K
5

1
PC3041

PC3042
PR5844
PQ3003 PC3043
HG_A2
1 2 AON6380_DFN8-5 0.01U_0402_25V7K
VCCCPUCORE

2
EMC@

Phase263 PU3002 2.2_0402_5%

co
3 12 4
PWM2_VCORE PWM HGATE PC3044 PR3028

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
4 1 1 2 1 2 1 1 1 1 1 1 1 1
63,64,65,66 SYNC SYNC BST
2 0.22U_0402_25V6-K 0_0603_5% PL3002

PC3023

PC3024

PC3025

PC3026

PC3027

PC3028

PC3029

PC3030
63,64,65,66 TEMP TEMP

3
2
1
0.15UH_PCME064T-R15MS0R667_36A_20%
5 11 SW_A2 1 2 2 2 2 2 2 2 2 2
63 CS2_VCORE CS SW

s.
13 9 @ @ @
EPAD LGATE

1
@

2
8 PR3009 @
+5VALW VCC

2
7 1/8W_2.2_5%_0805 PJ3003
10 ISENP PJ3004
GND JUMPER

1 1
6 LG_A2 4 EMC@

ic
ISENN JUMPER

1
CPUCORE_SN2
1

MP8693GDT-Z_TQFN12_2x3 PQ3004 PR3010

PC3045 2.26K_0402_1%
C 1U_0402_10V6K C
2

3
2
1
AON6324_DFN8-5
PC3047

at
1
PC3046
1 2
Vboot=0V Loadline=1.8mΩ
2200P_0402_50V7K
0.47U_0402_25V6K Ripple=+30mV/-10mV(0A-0.5A)

2
EMC@
PR3012
PR3013
4.7K +-1% TSM0A472F34D1RZ
PH3002 PR3014
Ripple=±10mV(0.5A-TDC)

em
1 2 1 2 1 2 1 2
Ripple=±15mV(TDC-Iccmax)
110_0402_1% 511_0402_1% 523_0402_1% TDC=80A (H42 =60A)
PR3015 Iccmax=128A(H42 =86) OCP=155A(H42=96A)
1 2
OVP=VID+400mV
PR3016
1 2
1.5K_0402_1% OVP=2V(during SS)
UVP=VID-300mV

ch
110_0402_1%

Phase3 V20B+ Fsw=500Khz

10U_0805_25V6K

10U_0805_25V6K
1

1
PC3048

PC3049

PR5845
5

PC3050
1 2 HG_A3 PQ3005 0.01U_0402_25V7K
2

AON6380_DFN8-5 EMC@

kS
2.2_0402_5%
PU3003
63 PWM3_VCORE
3
PWM HGATE
12
PC3051 PR3029
4
VCCCPUCORE
4 1 1 2 1 2
63,64,65,66 SYNC SYNC BST
2 0.22U_0402_25V6-K 0_0603_5% PL3003
63,64,65,66 TEMP TEMP
3
2
1

0.15UH_PCME064T-R15MS0R667_36A_20%
5 11 SW_A3 1 2
63 CS3_VCORE CS SW
oo
5

13 9 @
EPAD LGATE
1

2
PQ3006
8 AON6324_DFN8-5 PR3017 PJ3005 @
+5VALW VCC

2
7 1/8W_2.2_5%_0805 JUMPER
ISENP
1

10 PJ3006
GND 6 LG_A3 4 EMC@
ISENN JUMPER
2

1
CPUCORE_SN3
1

1
eb

MP8693GDT-Z_TQFN12_2x3
PC3052 PR3018
1U_0402_10V6K 2.26K_0402_1%
2

3
2
1

PC3054
2
1

B B
PC3053 1 2
2200P_0402_50V7K
2
ot

EMC@ 0.47U_0402_25V6K
4.7K +-1% TSM0A472F34D1RZ
PR3020
PR3021 PH3003 PR3022
1 2 1 2 1 2 1 2

110_0402_1% 511_0402_1% 523_0402_1%

N

PR3025
1 2
PR3024
1.5K_0402_1%
1 2

110_0402_1%

8A
V20B+
10U_0805_25V6K

10U_0805_25V6K
1

1
PC5853

PC5854
5

PC5855
PR5849 0.01U_0402_25V7K
PQ5809
2

1 2 HG_A4 EMC@
Phase4 AON6380_DFN8-5

PU5803 2.2_0402_5%
3 12 4
63 PWM4_VCORE PWM HGATE
4 1 1
PC5856
2 1
PR5850
2
VCCCPUCORE
63,64,65,66 SYNC SYNC BST
2 0.22U_0402_25V6-K 0_0603_5% PL5804
63,64,65,66 TEMP TEMP
3
2
1

0.15UH_PCME064T-R15MS0R667_36A_20%
5 11 SW_A4 1 2
63 CS4_VCORE CS SW
LG_A4
1

13 9 @ @
EPAD LGATE
5

PR5851
8 1/8W_2.2_5%_0805 PJ5504 PJ5505
+5VALW VCC
ISENP
7 JUMPER JUMPER
1

10 EMC@
GND
2

6
CPUCORE_SN4

ISENN
1

4
1

MP8693GDT-Z_TQFN12_2x3 PR5852
PC5857 PQ5810 2.26K_0402_1%
1U_0402_10V6K PC5858
2

3
2
1

2
1

AON6324_DFN8-5 1 2
PC5859
A 2200P_0402_50V7K A
0.47U_0402_25V6K
2

EMC@ 4.7K +-1% TSM0A472F34D1RZ

PR5853
PR5854 PH3202 PR5855
1 2 1 2 1 2 1 2

110_0402_1% 511_0402_1% 523_0402_1%

PR5856
1 2
PR5857
1 2 1.5K_0402_1%

110_0402_1%

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2018/09/20 Cover Page

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FG541/FG741
Date: Tuesday, March 26, 2019 Sheet 64 of 69
5 4 3 2 1
 5 4 3 2 1

D D

m
V20B+
6A

co
10U_0805_25V6K

10U_0805_25V6K
1

1
PC3130

PC3131
PC3132
0.01U_0402_25V7K Vboot=0V Loadline=2.7mΩ

s.
EMC@
Ripple=+30mV/-10mV(0A-0.5A)
Ripple=±10mV(0.5A-TDC)
Ripple=±15mV(TDC-Iccmax)

ic
PR5847
C 1 2
TDC=25A Iccmax=32A OCP=6548A C

5
OVP=2V(during SS) OVP=VID+400mV

at
2.2_0402_5% PQ3103
AON6380_DFN8-5 UVP=VID-300mV
HG_B2 4
Fsw=500Khz

em
PU3102
3 12
63 PWM5_GT PWM HGATE PC3133 PR3118
63,64,66 SYNC
4
SYNC BST
1 1 2 1 2
VCCGFXCORE

3
2
1
2 0.22U_0402_25V6-K 0_0603_5% PL3102
63,64,66 TEMP TEMP
5 11 SW_B2
0.15UH_PCME064T-R15MS0R667_36A_20%
1 2
32A

ch
63 CS5_GT CS SW

1
13 9
EPAD LGATE PQ3104 PR3109

330U_D2_2V_Y

330U_D2_2V_Y
8 AON6324_DFN8-5 1/8W_2.2_5%_0805 @ @ 1 1
+5VALW VCC

2
7
10 ISENP EMC@ PJ3103 PJ3104 + +

PC3105

PC3106
kS
GND

2
6 LG_B2 4

GFXCORE_SN2
ISENN JUMPER JUMPER

1
2 2
1

MP8693GDT-Z_TQFN12_2x3
PC3134 @
1U_0402_10V6K
2

3
2
1

1
oo

1
PR3110
PC3135 2.26K_0402_1%
2200P_0402_50V7K

2
EMC@
PC3136 0.33U_10V_K_X5R_0402
1 2

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
eb

1 1 1 1 1 1 1 1 1 1
4.7K +-1% TSM0A472F34D1RZ

PC3110

PC3111

PC3112

PC3113

PC3114

PC3115

PC3116

PC3118

PC3119

PC3117
PR3112
PR3113 PH3102 PR3114
B
1 2 1 2 1 2 1 2 2 2 2 2 2 2 2 2 2 2 B
ot

511_0402_1% 523_0402_1% @
120_0402_1%
PR3115
1 2
PR3116
1.5K_0402_1%
N

1 2

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
120_0402_1% 1 1 1 1 1 1 1 1 1 1

PC3120

PC3121

PC3122

PC3123

PC3124

PC3125

PC3126

PC3127

PC3128

PC3129
2 2 2 2 2 2 2 2 2 2

@ @ @ @

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2018/09/20 Cover Page

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
FG541/FG741 1.0

Date: Tuesday, March 26, 2019 Sheet 65 of 69

5 4 3 2 1
 5 4 3 2 1

D D
V20B+ Vboot=1.05V Loadline=10.3mΩ
Ripple=+30mV/-10mV(0A-0.5A)
Ripple=±10mV(0.5A-TDC)

10U_0805_25V6K

10U_0805_25V6K
1

1
Ripple=±15mV(TDC-Iccmax)

PC3201

PC3202
PC3203
PR5848 0.01U_0402_25V7K
TDC=10A Iccmax=11.1A OCP=18A

2
1 2 HG_C1 EMC@
OVP=2V(during SS) OVP=VID+400mV

5
2.2_0402_5%
UVP=VID-300mV

AON7380_DFN8-5

m
Fsw=500Khz

PQ3201
PU3201
3 12 4
63 PWM6_SA PWM HGATE PC3204 PR3209

co
4 1 1 2 1 2
63,64,65 SYNC SYNC BST 0.47UH_PCMB063T-R47MS3R675_18A_20% VCCSA
63,64,65 TEMP
2
TEMP
0.22U_0402_25V6-K 0_0603_5%
PL3201 10A

3
2
1

s.
5 11 SW_C1 1 2
C 63 CS6_SA CS SW C

1
13 9 LG_C1

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
ic
EPAD LGATE

5
PR3201

AON7516_DFN8-5
8 1/8W_2.2_5%_0805 @ @ 1 1 1 1 1 1 1 1
+5VALW VCC

2
7

PQ3202

at
10 ISENP EMC@ PJ3201 PJ3202

PC3205

PC3206

PC3207

PC3208

PC3209

PC3210

PC3211

PC3212
GND

2
6 JUMPER JUMPER
ISENN

1
4 2 2 2 2 2 2 2 2

VCCSA_SN
1

MP8693GDT-Z_TQFN12_2x3

em
2
PC3213 @ @
1U_0402_10V6K PR3202
2

1.5K_0402_1% @

3
2
1

1
PC3214
PC3215

ch

1
2200P_0402_50V7K

2
1 2
EMC@

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
0.22U_0402_25V6-K

kS
1 1 1 1 1 1
4.7K +-1% TSM0A472F34D1RZ
PR3204 PR3206
PR3205 PH3201

PC3216

PC3217

PC3218

PC3219

PC3220

PC3221
1 2 1 2 1 2 1 2
2 2 2 2 2 2
oo
B 910_0402_1% 511_0402_1% 240_0402_1% B
@ @
PR3207
2 1
eb

PR3208
1.5K_0402_1%
1 2

910_0402_1%
ot
N

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2018/09/20 Cover Page
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
B
FG541/FG741 1.0

Date: Tuesday, March 26, 2019 Sheet 66 of 69

5 4 3 2 1
 A B C D

PR5501
+1.35VGS_BST 1 2
PJ5503 @

0.1U_0603_25V7-M
2.2_0603_5% 2 1
2 1 +1.35VGS

PC5504
JUMP_43X118

20
1 1

2
BST
PJ5501 @ PL5501 PJ5502 @
+1.35VGS_VIN +1.35VGS_LX +1.35VGS_P
V20B+ 2
2 1
1 7
IN_1 LX_1
10 1 2 2
2 1
1

1
EMC_NS@
JUMP_43X118 0.47UH_PCMB063T-R47MS_18A_20% JUMP_43X118

10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6
8 11

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
PR5503
IN_2 LX_2

1
2.2_0805_5%

PC5501

PC5502
1 1 1 1 1 1
EMC_NS@ PR5506

PC5503

AOZ2264QI-20_QFN23_4X4
9 16 10_0402_1%

PC5514

PC5515

PC5516

PC5517

PC5518

PC5519
IN_3 LX_3

1 2
PR5502 PC5521 2 2 2 2 2 2

2
2.2_0603_5% 22 17 1000P_0402_50V9-J PC5523
2 1 IN_4 LX_4 1 2
+5VALW EMC_NS@ @ @ @

2
PC5505 18 1500P_0402_50V7-K
1 2 21 LX_5
VCC

PU5501
PR5508
4.7U_0603_6.3V6K

m
PR5504 0_0402_5% 5 +1.35VGS_FB 1 2 FBVDD_VCC_SENSE_R
1 2 +1.35VGS_EN 2 FB
28,30 FBVDDQ_PWR_EN EN

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
10.2K_0402_1% 1 1 1 1 1 1 1 1

1
PR5505 12
PGND_1

2
110K_0402_1% PR5512

PC5506

PC5507

PC5508

PC5509

PC5510

PC5511

PC5512

PC5513
0_0402_5%
co 1
PD5802 PR5924 +1.35VGS_VIN 1 2 TON 6 41.2K_0402_1%

PR5509
TON 2 2 2 2 2 2 2 2
2

3 2 1 13 PR5513
PC5520 PGND_2
8.06K_0402_1%

2
1 0_0402_5% @ @ @

+1.35VGS_FB_R3
.1U_0402_10V6-K @
1

1
@ @ 3 14
@ PFM PGND_3

2
LBAT54SWT1G_SOT323-3 2 2 1

s.
PC5522
PR5925 0.01U_0402_25V7K 15
0_0402_5% 1 2 SS 23 PGND_4
@ SS

ic
19
PGND_5 29 FBVDD_VCC_SENSE
28 VDDQPWROK 1
2
PGOOD PR5514 D
2

1
at
28 VRAM_VDDQ_ADJ

AGND
1 2 2 PQ5501
1 2 G
+3VS LBSS139WT1G_SC70-3
VRAM_VDDQ_ADJ 0_0402_5%
S

3
PR5511

4
100K_0402_1%
L = 1.354V PR5512 32.4k for Micron RAM 1.55V; PR5512 41.2k for 1.5V, EE use 76 bom control

em
PR5505=110K-FSW=550K H = 1.507V

ch
kS
+3VS
oo 1

PR540
0_0402_5% PR5839
2 1
+5VALW 100K_0402_1%

PC545
2
eb

1 2 1.0VGS_PG 28

1U_0402_6.3V6K PU502 APL5930CKAI-TRG_SO8

PJ510 @ 6 7
3

2 1 PC546 5 VCNTL POK PJ511 @ 3

+1.2V 2 1 10U_0603_6.3V6M VIN 3 2 1

+1.0VGS
ot

PR537 1 2 VOUT1 4 2 1
26.1K_0402_1%

1 2 JUMP_43X79 8 VOUT2
28,30 1V0_MAIN_EN EN JUMP_43X79
1

9 2
GND

0_0402_5% 2 1 EPAD FB
PR538

1 22UC_6.3VC_MC_X5RC_0603
N

PC548
1

0.1U_0402_25V6
PC547
1 2

PD5803 PR5922 @
3 2 1 2
100K_0402_1%
PR539

1 0_0402_5%
@ PR5923 @
LBAT54SWT1G_SOT323-3 2 2 1
2

0_0402_5%
@

1.35VGS
FB:0.6V/1.35V
TDC=11A
ICCMAX=20A
OCP=25A
FSW=550K
4
LDO-1.0VGS 4

TDC:1A
iccmax:1.1A
FB:0.8V/1.0V

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 Cover Page

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
FG541/FG741 1.0

Date: Tuesday, March 26, 2019 Sheet 67 of 69

A B C D
 5 4 3 2 1

D D

V20B+

2200P_0402_25V7-K

10U_0805_25V6K

10U_0805_25V6K
EMC@
1

1
PC5809

PC5801

PC5802
5

2
AON6380_DFN8-5
PR5801
2.2_0603_5%
1 2 NVVDD_PVCC 21
+5VALW

PQ5801
PVCC

1U_0402_6.3V6K
2 NVVDD_HG1 4
UGATE1

PC5803
PC5804
PR5802 PR5807
5.1K_0402_1% 1 NVVDD_BS1 1 2 1 2
BOOT1

3
2
1
1 2
+1.8VS_AON 25 2.2_0603_5% 0.22U_0603_25V7K
GND
PL5801
24 NVVDD_PH1 1 2
PHASE1
NVVDD

EMC_NS@ EMC_NS@
PSI open drain

1000P_0402_50V9-J 4.7_0805_5%
PR5803

330U_D2_2V_Y
5

1
0.22UH_PCME064T-R22MS0R985_28A_20%

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
1 1 1 1

330U_D2_2V_Y

330U_D2_2V_Y

330U_D2_2V_Y
AON6324_DFN8-5
NVVDD_PSI_R
H:1.8V 1 2 4

PR5808
28 NVVDD_PSI PSI 1 1 1 1 1 1 1
PR5804 PR5805 + + + +

PC5806

PC5807

PC5847

PC5850
L:0V 10K_0402_1% 5.1K_0402_1% @

PQ3502

PC5814

PC5815

PC5816

PC5817

PC5819

PC5820

PC5818
1 2 0_0402_5% 1 2
+3VS

m
1 2
23 NVVDD_LG1 4 2 2 2 2 2 2 2 2 2 2 2
@ 16 LGATE1

PC5813
28 NVVDD_PW RGD PGOOD @
PR5806 30K_0402_1%

2
1 2 NVVDD_EN_R 3
28,29 NVVDD_EN EN

3
2
1
1

1M_0402_5%
.1U_0402_10V6-K
@

PR5838
PR5837

co
PD5801 @
V20B+

PC5808

5
3 1 2

2200P_0402_25V7-K
10K_0402_1%

10U_0805_25V6K

10U_0805_25V6K
2

AON6380_DFN8-5
1
3K_0402_5%

EMC@
PC5823

PC5825

PC5826
NVVDD_VID_R NVVDD_HG2

1
LBAT54SW T1G_SOT323-3 2 1 2 5 17

PQ5804
VID UGATE2 4

0.1U_0402_10V7K
PR5836
PC5821

2
1
PR5810

PC5822
PR5809 18 NVVDD_BS2 1 2 1 2

s.
C 1 2
@ BOOT2 C
28 NVVDD_VID

RT8813DGQW_WQFN24_4X4
2

3
2
1
2.2_0603_5% 0.22U_0603_25V7K
0_0402_5%
PL5802
19 NVVDD_PH2 1 2

ic
1 2 NVVDD_VREF 8 PHASE2 NVVDD

1000P_0402_50V9-J 4.7_0805_5%
VREF

EMC_NS@ EMC_NS@
0.22UH_PCME064T-R22MS0R985_28A_20%

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
5

1
PC5827

PR5812
1 1 1 1 1 1 1
20.5K_0402_1%

AON6324_DFN8-5
1

.1U_0402_10V6-K

PQ5805
PR5811

PC5828

PC5829

PC5830

PC5831

PC5832

PC5833

PC5834
PU5801

at
2 2 2 2 2 2 2

1 2
20 NVVDD_LG2 4
LGATE2
2

PC5835
NVVDD_REFIN 7
REFIN

2
1

2
309_0402_1% 16.5K_0402_1%

3
2
1
PR5814
PR5813

em
100_0402_1%
PR5817
2

1
0.01U_0402_25V7K

PR5815 PR5816 1 2
1

4.32K_0402_1% 6.19K_0402_1% NVVDD_VSS_SENSE 30

PC5836

2 NVVDD_VIDBUF 6
1

@ 1 2 1
REFADJ 0_0402_5%
4700P_0402_25V7-K

1000P_0402_25V7-K
10 NVVDD_RGND
RGND
2

VR Remote Sense - connector to GPU sense points

PR5818

1
PC5838

PC5837
@
2

11 NVVDD_VSEN
VSNS
2

2
PR5820

ch
PR5821 1 2
1 2 1 2 NVVDD_FS 9 12 NVVDD_COMP NVVDD_VCC_SENSE 30
V20B+

22K_0402_1%
TON ILIM
0_0402_5%

1
2.2_0603_5% PR5819

PR5835
1U_0402_25V6-K

442K_0402_1%
1

2
@
PC5839

1
PR5819-=442k/fsw=350k
PR5823

16.5K_0402_1%
100_0402_1%
2

2
PR5822 16.5K/OCP 150A

kS PR5822

1000P_0402_25V7-K
V20B+

1
1

PC5851
PR5918

2200P_0402_25V7-K
2

5
@

10U_0805_25V6K

10U_0805_25V6K
2 1
+5VALW

AON6380_DFN8-5
NVVDD

1
EMC@
PR5824 PR5825

PC5841

PC5842

PC5843
0_0402_5% 10K_0402_1% 2.2_0603_5%

PQ5807
@ NVVDD_PH1 1 2 NVVDD_ISEN1 15 1 2 4
VCC/ISEN1

2
PC5845
+5VALW
B
oo PC5840 PU5802
NVVDD_BS3 1
PR5829 0.22U_0603_25V7K B
1U_0402_6.3V6K 4 2 1 2
1 2 2 1 8 BOOT
VCC

3
2
1
3 2.2_0603_5% NVVDD_HG3
PR5919 22 NVVDD_PW M3 5 UGATE PL5803
PWM3 PWM NVVDD_PH3
100K_0402_1%
@
PR5826
10K_0402_1% NVVDD_EN_R 1
PR5830
2 PW M3_EN 1
EN
PHASE
2 1 2
NVVDD

0.1U_0402_10V7K
NVVDD_PH2 2 NVVDD_ISEN2 NVVDD_LG3
2

1
1 14 7 0.22UH_PCME064T-R22MS0R985_28A_20%
TALERT/ISEN2 6 LGATE
PR5918/PR5919 @ FOR TWO PHASE
PR5917 PQ5808 PR5831

PC5846
0_0402_5% GND1

1
0_0402_5% @ 9 AON6324_DFN8-5 4.7_0805_5%
eb

GND2
EMC_NS@
RT9610CGQW _WDFN8_2X2
1

2
4
@
PR5828

1
13.3K_0402_1% PC5848
NVVDD_PH3 1 2 NVVDD_ISEN3 13 1000P_0402_50V9-J
TSNS/ISEN3
EMC_NS@

3
2
1

2
PR5917 @ FOR TWO PHASE
ot
N

A
VBOOT:0.8V A

VID voltage:0.3V~1.3V
TDC:50A
ICCMAX:100A
OCP:50A*3=150A
frequency:350K*3=1050khz

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 Cover Page

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
D 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FG541/FG741
Date: Tuesday, March 26, 2019 Sheet 68 of 69
5 4 3 2 1
 5 4 3 2 1

D D

m
co
s.
C C

ic
at
em
ch
kS
oo
B B
eb
ot
N

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2018/09/20 Cover Page
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
B
FG541/FG741 1.0

Date: Tuesday, March 26, 2019 Sheet 69 of 69

5 4 3 2 1