A B C D E

1 1

LCFC Confidential
2
Chelsea -SKY M/B Schematics Document 2

INTEL SKYLAKE Mobile ULT Platform

INTEL SKY Y-series CPU + LPDDR3 Memory

2015-08-13
REV:1.0
3 3

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2014/11/15 Deciphered Date 2013/11/08 Cover Page
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Miix4
Date: Monday, August 17, 2015 Sheet 1 of 37
A B C D E
 5 4 3 2 1

D
LCFC-Chelsea Refresh Block diagram D

Micro HDMI Conn. DDI-Port1 Memory BUS-ChannelA&B LPDDR3-1866

16Gbx32
1.2V LPDDR3 1866MT/S
eDP-Port[0:3]
eDP Conn. USB 2.0-Port1
USB 3.0-Port1
USB30
SATA Gen3 Port 1
NGFF SSD
USB 3.0-Port4 3D Camera
Micro SIM Conn Intel Skylake-Y Platform
NGFF WWAN USB20-Port5+I2C
Internal GPS/GNSS DC_IN Combo USB
USB 2.0-Port2
PCIe Port3 20*16.5*0.91
NGFF Wlan&BT
SPK Conn. USB20-Port6 BGA 1515 USB20-Port3 Docking Conn
C C

(1W x 2)

Array D-MIC Conn. HD Audio Cardreader

Codec ALC3240 PCIE-Port4 Micro SD Conn
BH611FJ1LN

Audio Combo Conn. I2C Touch Screen

iphone type CSI2+I2C
Front Camera Conn

SPI BUS
Flash LED SPI ROM
(8MB)
Camera PMIC
I2C
TPS68470A I2C
Rear Camera Conn I2C
LPC BUS
CSI2 G-Sensor ALS
BMA222E AL3010
B B

EC SMBUS Battery
IT8586VG-AX_VFBGA128

Sub-board
Reserved I2C I2C Reserved
Flash LED FPC
ALS G-Sensor Hall Sensor Thermal Sensor
AL3010 BMA222E F75303M

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/11/15 Deciphered Date 2013/11/08 Block Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Miix4
Date: Monday, August 17, 2015 Sheet 2 of 37
5 4 3 2 1
 A B C D E

Voltage Rails ( O --> Means ON , X --> Means OFF ) BOM Structure Table Board ID Table
Board ID Description PCB Revision
+5VS BOM Structure BOM Structure
+3VALW TI@ TI MIPI camera mount MIRROR@ EC Mirror-code enable
Power Plane +3VS
+5VALW TPM@ TPM module UNMIRROR@ EC Mirror-code disable
+DDR_1.2V +1.8VS
B+ DEBUG@ DEBUG CARD Part DA8@ PCB
+DDR_1.8V +DDR_0.6VS
+1.0VALW +3VALW_PCH ME@ ME part(connector, hole) UPI@ UPI MIPI camera mount
+3VL +CPU_CORE
+1.8VALW RF@ RF request
+CPU_VCCIO
EMC@ EMC request
1
State +5VLP +CPU_VCCPRIM +CPU_VCCGT 1
CD@ COST DOWN Part
+CPU_VCCSA
REV@ RESERVER Part

S0 O O O O O BOM Configuration Table

SKU Description BOM Config
S3 O O O O X
SKU1

DS3 O O X O X
SKU2

S5 S4/AC Only O O O X X

S5 S4 O X X X X
Battery only

S5 S4 X X X X X
2 AC & Battery 2

don't exist
SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# +VALW +VALW_PCH +V +VS Clock

Full ON HIGH HIGH HIGH ON ON ON ON ON

S1(Power On Suspend) LOW HIGH HIGH ON ON ON ON LOW X76&VGA Configuration Table

SKU Description BOM Config
S3 (Suspend to RAM) LOW LOW HIGH ON ON ON OFF OFF

DS3 (Suspend to RAM) LOW LOW HIGH ON LOW ON OFF OFF

S4 (Suspend to Disk) LOW LOW LOW ON ON OFF OFF OFF

S5 (Soft OFF) LOW LOW LOW ON ON OFF OFF OFF

SMBUS Control Table

SOURCE Sensor ALS BATT Thermal charger

Sensor
3 3

EC_SMB_CLK1 IT8586
EC_SMB_DAT1 +3VALW_EC X X V X V

EC_SMB_CLK3 IT8586 V V
EC_SMB_DAT3 +3VS +3VS +3VS X X X

EC_SMB_CLK0 IT8586
X X X V X
EC_SMB_DAT0 +3VS +3VS
PCB And LOGO ConfigZZZ3
ZZZ15 NUVOTON@

PCB LOGO
PCB 10K NM-A641 REV0 M/B
S IC NPCT650LAAWX TSSOP 28P TPM
ZZZ9 M3@ ZZZ16 M5@ ZZZ17 M7@
ZZZ4 HDMI@

CPU
SM Bus address PCIE PORT LIST USB Port Table
USB20 USB30 SR2EN SR2EM SR2EM
Device address Port Device USB USB HDMI LOGO
Battery 0001 011X b
1 1
BT WWAN ZZZ6 HY8G@ ZZZ7 MIC8G@ ZZZ8 SAM8G@ ZZZ12 HY4G@ ZZZ13 MIC4G@ ZZZ14 SAM4G@
EC1 2 2
EXHCI/XHCI

Charger
1 3 EC
3 X
4
Sensor VRAM 4

EC3 2 5 DC in combine 4 3D camera

ALS
3 WLAN 7 POGO USB HYNIX 8G MICRON8G SAMSUNG 8G HYNIX 4G MICRON 4G SAMSUNG 4G
Thermal Sensor 1001_100xb
EC0 4 CR 9 WWAN
PCH THM

TP
5
PCH Title
Security Classification LC Future Center Secret Data
Issued Date 2014/11/15 Deciphered Date 2013/11/08 Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Miix4
Date: Monday, August 17, 2015 Sheet 3 of 37
A B C D E
 5 4 3 2 1

?
SKYLAKE_ULX
UC1A
DISPLAY
A46 H45
18 CPU_HDMI_TX2- DDI1_TXN[0] EDP_TXN[0] CPU_EDP_TX0- 17
C46 F45 DDP*_CTRLDATA
18 CPU_HDMI_TX2+ DDI1_TXP[0] EDP_TXP[0] CPU_EDP_TX0+ 17
C48 J44 This signal has a weak internal pull-down.
18 CPU_HDMI_TX1- DDI1_TXN[1] EDP_TXN[1] CPU_EDP_TX1- 17
A48 G44 0 = Port B is not detected.
18 CPU_HDMI_TX1+ DDI1_TXP[1] EDP_TXP[1] CPU_EDP_TX1+ 17
B45 J46
D
18
18
CPU_HDMI_TX0-
CPU_HDMI_TX0+
D45 DDI1_TXN[2]
DDI1_TXP[2]
EDP_TXN[2]
EDP_TXP[2]
G46
CPU_EDP_TX2-
CPU_EDP_TX2+
17
17
*1 = Port B is detected.
D
B47 H43
18 CPU_HDMI_CLK- DDI1_TXN[3] EDP_TXN[3] CPU_EDP_TX3- 17
D47 eDP F43
18 CPU_HDMI_CLK+ DDI1_TXP[3] EDP_TXP[3] CPU_EDP_TX3+ 17
DDI pull up at HDMI side.
A42 J42
DDI2_TXN[0] EDP_AUXN CPU_EDP_AUX- 17
C42 G42
A44 DDI2_TXP[0] EDP_AUXP CPU_EDP_AUX+ 17
C44 DDI2_TXN[1] A40 EDP_DISP_ULT 1 @
B41 DDI2_TXP[1] EDP_DISP_UTIL TC166 +CPU_VCCIO
D41 DDI2_TXN[2] H41
B43 DDI2_TXP[2] DDI1_AUXN F41 24.9_0402_1%
DDI2_TXN[3] DDI1_AUXP RC4
D43 J40
DDI2_TXP[3] DDI2_AUXN G40 EDP_COMP 1 2
L6 DDI2_AUXP
18 HDMI_DDC_CLK H6 GPP_E18/DDPB_CTRLCLK C11 PCH_HDMI_HPD
GPP_E19/DDPB_CTRLDATA GPP_E13/DDPB_HPD0 PCH_HDMI_HPD 18 +VCCIOA_OUT & EDP_COMP :
18 HDMI_DDC_DATA L10 RC3026
GPP_E14/DDPC_HPD1 Trace Width: 20mil
H4 M7 1 2 0_0402_5% Space: 25mil
GPP_E20/DDPC_CTRLCLK GPP_E15/DDPD_HPD2 EC_SCI# 9,25
1 F4 F6
@ TC171 GPP_E21/DDPC_CTRLDATA GPP_E16/DDPE_HPD3 A7 @
Max length: 100mil
GPP_E17/EDP_HPD PCH_EDP_HPD 17
M5
L4 GPP_E22 D4
GPP_E23 eDP_BKLEN B6 PCH_BKLT_CTRL PCH_BKLT_EN 17,25
EDP_COMP A50 eDP_BKLCTL D3 PCH_LCD_VDDEN PCH_BKLT_CTRL 17
DISPLAY SIDEBANDS
eDP_RCOMP eDP_VDDEN PCH_LCD_VDDEN 17
1 OF 20
SKYLAKE-Y_FCBGA1515
REV = 1 ?
@

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/11/15 Deciphered Date 2013/08/05 MCP (DDI,EDP)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Miix4
Date: Monday, August 17, 2015 Sheet 4 of 37
5 4 3 2 1
 5 4 3 2 1

+CPU_VCCSTG

Debug Port DG
2 1 CPU_PROCHOT# Merged MCP XDP-SFF-26Pin Connector Pinout
RC19 1K_0402_1%
?
SKYLAKE_ULX
UC1D
+CPU_VCCSTG
+CPU_VCCST TC15 @ 1 CATERR# H49 D53 XDP_TCK
F49 CATERR# PROC_TCK C54 XDP_TDI XDP_TDI 2 1
25 CPU_PECI CPU_PROCHOT# 1 PECI PROC_TDI
2 PROCHOT# J48 G48 XDP_TDO RC1546 51_0402_5%
25 CPU_PROCHOT# PROCHOT# PROC_TDO
RC20 499_0402_1% THRMTRIP# H47 C59 XDP_TMS XDP_TDO 2 1
D
RC57 1 2 0_0402_5% SKTOCC# B62 THERMTRIP# PROC_TMS F47 XDP_TRST# RC1543 51_0402_5% D
2 1 THRMTRIP# SKTOCC# PROC_TRST# XDP_TMS 2 1
1 XDP_BPM0# H51 JTAG B53 PCH_JTAG_TCK
RC143 1K_0402_1% TC11 @ RC1547 51_0402_5%
TC12 @ 1 XDP_BPM1# J50 BPM#[0] PCH_JTAG_TCK C50 XDP_TDI
TC13 @ 1 XDP_BPM2# F51 BPM#[1] PCH_JTAG_TDI B51 XDP_TDO
130 degree output ,for breakpoint and performance monitor signal BPM#[2] PCH_JTAG_TDO
TC14 @ 1 XDP_BPM3# G50 A52 XDP_TMS XDP_TCK 1 2
BPM#[3] PCH_JTAG_TMS C52 XDP_TRST# RC1551 51_0402_5%
TPM_ID1 E11 PCH_TRST# B49 XDP_TCK PCH_JTAG_TCK 1 @ 2
TPM_ID2 M9 GPP_E3/CPU_GP0 JTAGX RC1552 51_0402_5%
BD8 GPP_E7/CPU_GP1 XDP_TRST# 1 @ 2
BC11 GPP_B3/CPU_GP2 RC1553 51_0402_5%
GPP_B4/CPU_GP3 For Boundary Scan
TPM_ID1 Description
RC155 1 2 49.9_0402_1% BN17
RC156 1 2 49.9_0402_1% BP16 PROC_POPIRCOMP
PCH_OPIRCOMP
0 NO physical TPM CPU MISC
4 OF 20
SKYLAKE-Y_FCBGA1515
1 physical TPM REV = 1 ?
@

TPM_ID2 Description

0 NATIONZ TPM

1 NUVOTON TPM

C +3VS C
2

2
10K_0402_5%

10K_0402_5%
RC3029

RC3031

TPM@
1

TPM_ID1

TPM_ID2
2

2
10K_0402_5%

10K_0402_5%
RC3030

RC3032
1

UNTPM@ @

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/11/15 Deciphered Date 2013/08/05 MCP (XDP,JATG)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Miix4
Date: Tuesday, August 18, 2015 Sheet 5 of 37
5 4 3 2 1
 5 4 3 2 1

DDRA_DQS#[0..7]
15 DDRA_DQS#[0..7]

15 DDRA_DQS[0..7]
DDRA_DQS[0..7] Non-interleave ballmap
DDRB_DQS#[0..7]
16 DDRB_DQS#[0..7]
DDRB_DQS[0..7] ?
16 DDRB_DQS[0..7] SKYLAKE_ULX
UC1B ?
BC62 SKYLAKE_ULX
UC1C
15 DDRA_DQ[0..7] DDRA_DQ0 AG61 DDR0_CKN[0] DDRA_CLK0# 15
BC60
DDRA_DQ1 AH60 DDR0_DQ[0] DDR0_CKP[0] DDRA_CLK0 16
15 DDRB_DQ[0..7] DDRB_DQ0
BA60 BC41 BK36
DDRA_DQ2 AK62 DDR0_DQ[1] DDR0_CKN[1] DDRA_CLK1# 15 DDRB_DQ1 DDR0_DQ[32]/DDR1_DQ[0] DDR1_CKN[0] DDRB_CLK0# 16
BA62 BC39 BM36
DDRA_DQ3 AK60 DDR0_DQ[2] DDR0_CKP[1] DDRA_CLK1 15 DDRB_DQ2 DDR0_DQ[33]/DDR1_DQ[1] DDR1_CKP[0] DDRB_CLK0 16
BG41 BD32
DDRA_DQ4 AH62 DDR0_DQ[3] DDRB_DQ3 DDR0_DQ[34]/DDR1_DQ[2] DDR1_CKN[1] DDRB_CLK1# 16
BB57 BE39 BF32
DDRA_DQ5 AG63 DDR0_DQ[4] DDR0_CKE[0] DDRA_CKE0 15 DDRB_DQ4 DDR0_DQ[35]/DDR1_DQ[3] DDR1_CKP[1] DDRB_CLK1 16
BC58 BF42
D DDRA_DQ6 AL61 DDR0_DQ[5] DDR0_CKE[1] DDRA_CKE1 15 DDRB_DQ5 DDR0_DQ[36]/DDR1_DQ[4] D
BE57 BD42 BN33
DDRA_DQ7 AL63 DDR0_DQ[6] DDR0_CKE[2] DDRA_CKE2 15 DDRB_DQ6 DDR0_DQ[37]/DDR1_DQ[5] DDR1_CKE[0] DDRB_CKE0 16
AW61 BG39 BK32
15 DDRA_DQ[8..15] DDRA_DQ8 AM60 DDR0_DQ[7] DDR0_CKE[3] DDRA_CKE3 15 DDRB_DQ7 DDR0_DQ[38]/DDR1_DQ[6] DDR1_CKE[1] DDRB_CKE1 16
BE41 BG33
DDRA_DQ9 AM62 DDR0_DQ[8] 16 DDRB_DQ[8..15] DDRB_DQ8 DDR0_DQ[39]/DDR1_DQ[7] DDR1_CKE[2] DDRB_CKE2 16
AW63 BC43 BH30
DDRA_DQ10 AT60 DDR0_DQ[9] DDR0_CS#[0] DDRA_CS0# 15 DDRB_DQ9 DDR0_DQ[40]/DDR1_DQ[8] DDR1_CKE[3] DDRB_CKE3 16
BJ57 BD46
DDRA_DQ11 AR61 DDR0_DQ[10] DDR0_CS#[1] DDRA_CS1# 15 DDRB_DQ10 DDR0_DQ[41]/DDR1_DQ[9]
BN61 BG43 BM30
DDRA_DQ12 AN61 DDR0_DQ[11] DDR0_ODT[0] DDRA_ODT0 15 DDRB_DQ11 DDR0_DQ[42]/DDR1_DQ[10] DDR1_CS#[0] DDRB_CS0# 16
BG45 BJ33
DDRA_DQ13 AN63 DDR0_DQ[12] DDRB_DQ12 DDR0_DQ[43]/DDR1_DQ[11] DDR1_CS#[1] DDRB_CS1# 16
AW59 BC45 BC35
DDRA_DQ14 AR63 DDR0_DQ[13] DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] DDRA_CAA0 15 DDRB_DQ13 DDR0_DQ[44]/DDR1_DQ[12] DDR1_ODT[0] DDRB_ODT0 16
AW55 BE43
DDRA_DQ15 AT62 DDR0_DQ[14] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] DDRA_CAA1 15 DDRB_DQ14 DDR0_DQ[45]/DDR1_DQ[13]
BF62 BE45 BK30
15 DDRA_DQ[16..23] DDRA_DQ16 AT56 DDR0_DQ[15] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] DDRA_CAA2 15 DDRB_DQ15 DDR0_DQ[46]/DDR1_DQ[14] DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] DDRB_CAA0 16
AV56 BF46 BN31
DDRA_DQ17 AR55 DDR1_DQ[0]/DDR0_DQ[16] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] DDRA_CAA3 16 15 DDRB_DQ[16..23] DDRB_DQ16 DDR0_DQ[47]/DDR1_DQ[15] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] DDRB_CAA1 16
AW57 BM28 BM32
DDRA_DQ18 AN57 DDR1_DQ[1]/DDR0_DQ[17] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] DDRA_CAA4 15 DDRB_DQ17 DDR1_DQ[32]/DDR1_DQ[16] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] DDRB_CAA2 16
AV58 BN27 BL37
DDRA_DQ19 AN55 DDR1_DQ[2]/DDR0_DQ[18] DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] DDRA_CAA5 15 DDRB_DQ18 DDR1_DQ[33]/DDR1_DQ[17] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] DDRB_CAA3 16
BA56 BK28 BG31
DDRA_DQ20 AR57 DDR1_DQ[3]/DDR0_DQ[19] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] DDRA_CAA6 15 DDRB_DQ19 DDR1_DQ[34]/DDR1_DQ[18] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] DDRB_CAA4 16
BD59 BL25 BN37
DDRA_DQ21 AT58 DDR1_DQ[4]/DDR0_DQ[20] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] DDRA_CAA7 15 DDRB_DQ20 DDR1_DQ[35]/DDR1_DQ[19] DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] DDRB_CAA5 16
BD61 BN25 BJ37
DDRA_DQ22 AM58 DDR1_DQ[5]/DDR0_DQ[21] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# DDRA_CAA8 15 DDRB_DQ21 DDR1_DQ[36]/DDR1_DQ[20] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] DDRB_CAA6 16
BG61 BL27 BJ35
DDRA_DQ23 AM56 DDR1_DQ[6]/DDR0_DQ[22] DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] DDRA_CAA9 15 DDRB_DQ22 DDR1_DQ[37]/DDR1_DQ[21] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] DDRB_CAA7 16
BJ25 BM34
15 DDRA_DQ[24..31] DDRA_DQ24 AL55 DDR1_DQ[7]/DDR0_DQ[23] DDRB_DQ23 DDR1_DQ[38]/DDR1_DQ[22] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# DDRB_CAA8 16
BK59 BJ27 BN35
DDRA_DQ25 AL57 DDR1_DQ[8]/DDR0_DQ[24] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] DDRA_CAB0 16 15 DDRB_DQ[24..31] DDRB_DQ24 DDR1_DQ[39]/DDR1_DQ[23] DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1] DDRB_CAA9 16
BL62 BM24
DDRA_DQ26 AH58 DDR1_DQ[9]/DDR0_DQ[25] DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15] DDRA_CAB1 15 DDRB_DQ25 DDR1_DQ[40]/DDR1_DQ[24]
BJ61 BK24 BG37
DDRA_DQ27 AH56 DDR1_DQ[10]/DDR0_DQ[26] DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14] DDRA_CAB2 15 DDRB_DQ26 DDR1_DQ[41]/DDR1_DQ[25] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13] DDRB_CAB0 16
AV60 BN21 BE37
DDRA_DQ28 AK58 DDR1_DQ[11]/DDR0_DQ[27] DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16] DDRA_CAB3 15 DDRB_DQ27 DDR1_DQ[42]/DDR1_DQ[26] DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15] DDRB_CAB1 16
BN62 BJ23 BC37
DDRA_DQ29 AK56 DDR1_DQ[12]/DDR0_DQ[28] DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] DDRA_CAB4 15 DDRB_DQ28 DDR1_DQ[43]/DDR1_DQ[27] DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14] DDRB_CAB2 16
BB61 BL23 BF34
DDRA_DQ30 AG55 DDR1_DQ[13]/DDR0_DQ[29] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] DDRA_CAB5 15 DDRB_DQ29 DDR1_DQ[44]/DDR1_DQ[28] DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16] DDRB_CAB3 16
BL61 BN23 BC33
DDRA_DQ31 AG57 DDR1_DQ[14]/DDR0_DQ[30] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] DDRA_CAB6 15 DDRB_DQ30 DDR1_DQ[45]/DDR1_DQ[29] DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[4] DDRB_CAB4 16
BM59 BJ21 BF30
15 DDRA_DQ[32..39] DDRA_DQ32 BE55 DDR1_DQ[15]/DDR0_DQ[31] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] DDRA_CAB7 15 DDRB_DQ31 DDR1_DQ[46]/DDR1_DQ[30] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2] DDRB_CAB5 16
BN58 BL21 BD36
DDRA_DQ33 BC55 DDR0_DQ[16]/DDR0_DQ[32] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] DDRA_CAB8 16 15 DDRB_DQ[32..39] DDRB_DQ32 DDR1_DQ[47]/DDR1_DQ[31] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] DDRB_CAB6 16
AV62 BN45 BG35
DDRA_DQ34 BG53 DDR0_DQ[17]/DDR0_DQ[33] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] DDRA_CAB9 15 DDRB_DQ33 DDR0_DQ[48]/DDR1_DQ[32] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] DDRB_CAB7 16
BM46 BC31
DDRA_DQ35 BE53 DDR0_DQ[18]/DDR0_DQ[34] DDRB_DQ34 DDR0_DQ[49]/DDR1_DQ[33] DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] DDRB_CAB8 16
BB63 1 @ BL43 BF36
DDRA_DQ36 BC53 DDR0_DQ[19]/DDR0_DQ[35] DDR0_MA[3] TC90 DDRB_DQ35 DDR0_DQ[50]/DDR1_DQ[34] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0] DDRB_CAB9 16
BL57 BK46
DDRA_DQ37 BG55 DDR0_DQ[20]/DDR0_DQ[36] DDR0_MA[4] DDRB_DQ36 BN43 DDR0_DQ[51]/DDR1_DQ[35] BJ31
DDRA_DQ38 BD52 DDR0_DQ[21]/DDR0_DQ[37] AJ61 DDRA_DQS#0 DDRB_DQ37 BL45 DDR0_DQ[52]/DDR1_DQ[36] DDR1_MA[3] BK34
DDRA_DQ39 BF52 DDR0_DQ[22]/DDR0_DQ[38] DDR0_DQSN[0] AJ63 DDRA_DQS0 DDRB_DQ38 BJ45 DDR0_DQ[53]/DDR1_DQ[37] DDR1_MA[4]
15 DDRA_DQ[40..47] DDRA_DQ40 BC51 DDR0_DQ[23]/DDR0_DQ[39] DDR0_DQSP[0] DDR0_DQ[54]/DDR1_DQ[38]
AP62 DDRA_DQS#1 DDRB_DQ39 BJ43 BD40 DDRB_DQS#0
DDRA_DQ41 BE51 DDR0_DQ[24]/DDR0_DQ[40] DDR0_DQSN[1] 16 DDRB_DQ[40..47] DDR0_DQ[55]/DDR1_DQ[39] DDR0_DQSN[4]/DDR1_DQSN[0]
AP60 DDRA_DQS1 DDRB_DQ40 BM42 BF40 DDRB_DQS0
DDRA_DQ42 BC49 DDR0_DQ[25]/DDR0_DQ[41] DDR0_DQSP[1] AP56 DDRA_DQS#2 DDRB_DQ41 BN41 DDR0_DQ[56]/DDR1_DQ[40] DDR0_DQSP[4]/DDR1_DQSP[0] BD44 DDRB_DQS#1
DDRA_DQ43 BE49 DDR0_DQ[26]/DDR0_DQ[42] DDR1_DQSN[0]/DDR0_DQSN[2] AP58 DDRA_DQS2 DDRB_DQ42 BJ41 DDR0_DQ[57]/DDR1_DQ[41] DDR0_DQSN[5]/DDR1_DQSN[1] BF44 DDRB_DQS1
C C
DDRA_DQ44 BG51 DDR0_DQ[27]/DDR0_DQ[43] DDR1_DQSP[0]/DDR0_DQSP[2] AJ57 DDRA_DQS#3 DDRB_DQ43 BN39 DDR0_DQ[58]/DDR1_DQ[42] DDR0_DQSP[5]/DDR1_DQSP[1] BK26 DDRB_DQS#2
DDRA_DQ45 BG49 DDR0_DQ[28]/DDR0_DQ[44] DDR1_DQSN[1]/DDR0_DQSN[3] AJ55 DDRA_DQS3 DDRB_DQ44 BK42 DDR0_DQ[59]/DDR1_DQ[43] DDR1_DQSN[4]/DDR1_DQSN[2] BM26 DDRB_DQS2
DDRA_DQ46 BF48 DDR0_DQ[29]/DDR0_DQ[45] DDR1_DQSP[1]/DDR0_DQSP[3] BD54 DDRA_DQS#4 DDRB_DQ45 BL41 DDR0_DQ[60]/DDR1_DQ[44] DDR1_DQSP[4]/DDR1_DQSP[2] BM22 DDRB_DQS#3
DDRA_DQ47 BD48 DDR0_DQ[30]/DDR0_DQ[46] DDR0_DQSN[2]/DDR0_DQSN[4] BF54 DDRA_DQS4 DDRB_DQ46 BL39 DDR0_DQ[61]/DDR1_DQ[45] DDR1_DQSN[5]/DDR1_DQSN[3] BK22 DDRB_DQS3
15 DDRA_DQ[48..55] DDRA_DQ48 BJ55 DDR0_DQ[31]/DDR0_DQ[47] DDR0_DQSP[2]/DDR0_DQSP[4] DDR0_DQ[62]/DDR1_DQ[46] DDR1_DQSP[5]/DDR1_DQSP[3]
BF50 DDRA_DQS#5 DDRB_DQ47 BJ39 BK44 DDRB_DQS#4
DDRA_DQ49 BL55 DDR1_DQ[16]/DDR0_DQ[48] DDR0_DQSN[3]/DDR0_DQSN[5] 16 DDRB_DQ[48..55] DDR0_DQ[63]/DDR1_DQ[47] DDR0_DQSN[6]/DDR1_DQSN[4]
BD50 DDRA_DQS5 DDRB_DQ48 BF28 BM44 DDRB_DQS4
DDRA_DQ50 BJ53 DDR1_DQ[17]/DDR0_DQ[49] DDR0_DQSP[3]/DDR0_DQSP[5] BM54 DDRA_DQS#6 DDRB_DQ49 BD28 DDR1_DQ[48] DDR0_DQSP[6]/DDR1_DQSP[4] BM40 DDRB_DQS#5
DDRA_DQ51 BL53 DDR1_DQ[18]/DDR0_DQ[50] DDR1_DQSN[2]/DDR0_DQSN[6] BK54 DDRA_DQS6 DDRB_DQ50 BG25 DDR1_DQ[49] DDR0_DQSN[7]/DDR1_DQSN[5] BK40 DDRB_DQS5
DDRA_DQ52 BN55 DDR1_DQ[19]/DDR0_DQ[51] DDR1_DQSP[2]/DDR0_DQSP[6] BK50 DDRA_DQS#7 DDRB_DQ51 BC27 DDR1_DQ[50] DDR0_DQSP[7]/DDR1_DQSP[5] BD26 DDRB_DQS#6
DDRA_DQ53 BN53 DDR1_DQ[20]/DDR0_DQ[52] DDR1_DQSN[3]/DDR0_DQSN[7] BM50 DDRA_DQS7 DDRB_DQ52 BG27 DDR1_DQ[51] DDR1_DQSN[6] BF26 DDRB_DQS6
DDRA_DQ54 BM52 DDR1_DQ[21]/DDR0_DQ[53] DDR1_DQSP[3]/DDR0_DQSP[7] DDRB_DQ53 BE27 DDR1_DQ[52] DDR1_DQSP[6] BF22 DDRB_DQS#7
DDRA_DQ55 BK52 DDR1_DQ[22]/DDR0_DQ[54] BG57 DDRB_DQ54 BE25 DDR1_DQ[53] DDR1_DQSN[7] BD22 DDRB_DQS7
15 DDRA_DQ[56..63] DDRA_DQ56 BL51 DDR1_DQ[23]/DDR0_DQ[55] DDR0_ALERT# DDRB_DQ55 DDR1_DQ[54] DDR1_DQSP[7]
BM56 BC25
DDRA_DQ57 BJ51 DDR1_DQ[24]/DDR0_DQ[56] DDR0_PAR 16 DDRB_DQ[56..63] DDRB_DQ56 DDR1_DQ[55]
BF24 BD34
DDRA_DQ58 BL49 DDR1_DQ[25]/DDR0_DQ[57] AR53 DDRB_DQ57 BD24 DDR1_DQ[56] DDR1_ALERT# BD30
DDRA_DQ59 BJ49 DDR1_DQ[26]/DDR0_DQ[58] DDR_VREF_CA DDR_SM_VREFCA 15 DDRB_DQ58 DDR1_DQ[57] DDR1_PAR
AN53 BG21 BP20
DDRA_DQ60 BN49 DDR1_DQ[27]/DDR0_DQ[59] DDR0_VREF_DQ DDR_SA_VREFDQ 15 DDRB_DQ59 DDR1_DQ[58] DRAM_RESET#
AW53 BC23
DDRA_DQ61 BN51 DDR1_DQ[28]/DDR0_DQ[60] DDR1_VREF_DQ DDR_SB_VREFDQ 16 DDRB_DQ60 DDR1_DQ[59]
BE23 BF64 SM_RCOMP_0 1 2
DDRA_DQ62 BK48 DDR1_DQ[29]/DDR0_DQ[61] BN47 DDR_VTT_CNTL DDRB_DQ61 BG23 DDR1_DQ[60] DDR_RCOMP[0] BJ64 SM_RCOMP_1 1 2
DDRA_DQ63 BM48 DDR1_DQ[30]/DDR0_DQ[62] DDR_VTT_CNTL DDRB_DQ62 BC21 DDR1_DQ[61] DDR_RCOMP[1] BC64 SM_RCOMP_2 1 2
DDR CH - A DDR CH - B
DDR1_DQ[31]/DDR0_DQ[63] DDRB_DQ63 BE21 DDR1_DQ[62] DDR_RCOMP[2]
SMVREF DDR1_DQ[63]
RC26 200_0402_1%
WIDTH:20MIL RC25 80.6_0402_1%
SPACING: 20MIL RC24 162_0402_1%
2 OF 20
SKYLAKE-Y_FCBGA1515
3 OF 20
REV = 1 ?
SKYLAKE-Y_FCBGA1515
@ REV = 1 ?
@ Need to check the resistor value

+3VALW
B B
1

RC50
100K_0402_5%
2

CPU_DRAMPG_CNTL 35
+CPU_VDDQ
1

C
RC48 1 2 2 QC14
1K_0402_5% B
E
3

MMBT3904WH_SOT323-3

DDR_VTT_CNTL
2

RC49
10K_0402_5%
@
1

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/11/15 Deciphered Date 2013/08/05 MCP (DDR)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Miix4
Date: Monday, August 17, 2015 Sheet 6 of 37
5 4 3 2 1
 5 4 3 2 1

+3VALW_PCH

@
SML0_ALERT# 2 1
+VCCHDA ? R687 2.2K_0402_5%
UC1G SKYLAKE_ULX SMB_ALERT# 2 1
R688 2.2K_0402_5%
RC47 1 @ 2 1K_0402_5% HDA_SDOUT RC43 1 2 33_0402_5% HDA_SYNC BJ19 AH9 SML1_ALERT# 1 2
23 PCH_HDA_SYNC HDA_BCLK HDA_SYNC/I2S0_SFRM GPP_G0/SD_CMD R689 150K_0402_5%
RC42 1 2 33_0402_5% BK18 AH11
23 PCH_HDA_BCLK HDA_SDOUT HDA_BLK/I2S0_SCLK GPP_G1/SD_DATA0
BK16 AG12
HDA_SDO This signal has a weak internal pull-down. PCH_HDA_SDIN0 BL15 HDA_SDO/I2S0_TXD GPP_G2/SD_DATA1 AF9 PCH_SML1_CLK 1 4
23 PCH_HDA_SDIN0 HDA_SDI0/I2S0_RXD GPP_G3/SD_DATA2 PCH_SML1_DAT 2 3
* 0 = Enable security measures defined in the Flash Descriptor.
1 = Disable Flash Descriptor Security(override). This strap
BL17
BL19 HDA_SDI1/I2S1_RXD
HDA_RST#/I2S1_SCLK
GPP_G4/SD_DATA3
GPP_G5/SD_CD#
AF11
AG8 RPC27 10K_0404_4P2R_5%
should only be asserted high during external pull-up in V5 AG10 @
BL12 GPP_D23/I2S_MCLK SDIO/SDXC GPP_G6/SD_CLK AE12
manufacturing/debug environments ONLY. RC45 1 2 33_0402_5% HDA_SDOUT BK14 I2S1_SFRM GPP_G7/SD_WP +3VALW_PCH
23 PCH_HDA_SDOUT I2S1_TXD
D AUDIO BL4 1 @ D
RC46 1 2 0_0402_5% GPP_A17/SD_PWR_EN#/ISH_GP7 BN4 PCH_WWAN_OFF# TC82
25 PCH_ME_PROTECT GPP_A16/SD_1P8_SEL
For EMI AT13 PCH_WWAN_OFF# 21
PCH_HDA_SDIN0 AT11 GPP_F1/I2S2_SFRM BF1 SD_RCOMP 1 2 RPC25
AP11 GPP_F0/I2S2_SCLK SD_RCOMP 200_0402_1% SML0_CLK 1 8
AT5 GPP_F2/I2S2_TXD RC1537 SML0_DATA 2 7
GPP_F3/I2S2_RXD AJ8 PCH_SMB_CLK 3 6
1 P_IRQ 26
@ GPP_F23 PCH_SMB_DATA 4 5
CC7 V3
10P_0402_50V8J TC124
@ 1 V11 GPP_D19/DMIC_CLK0 10K_0804_8P4R_5%
2 GPP_D20/DMIC_DATA0 @
U12
U8 GPP_D17/DMIC_CLK1
PCH_BEEP AV3 GPP_D18/DMIC_DATA1
23 PCH_BEEP GPP_B14/SPKR

7 OF 20
The signal has a weak internal pull-down. SKYLAKE-Y_FCBGA1515
REV = 1 ?
0 = Disable “ Top Swap” mode. (Default
) @
+3VS
1 = Enable “ Top Swap” mode
.

2 1 PCH_BEEP
R684 2.2K_0402_5% +3VS
@

PCH_SPI_CS0# RC64 1 2 0_0402_5% SPI_CS0#

25 PCH_SPI_CS0#
PCH_SPI_SI RC52 1 2 15_0402_5% SPI_SI ?
25 PCH_SPI_SI SKYLAKE_ULX
UC1E
PCH_SPI_SO RC53 1 2 15_0402_5% SPI_SO
25 PCH_SPI_SO SPI_CLK PCH_SMB_CLK PM_CLKRUN#
AU10 AC12 1 2
PCH_SPI_CLK RC65 1 2 15_0402_5% SPI_CLK SPI_SO AU12 SPI0_CLK GPP_C0/SMBCLK W6 PCH_SMB_DATA
25 PCH_SPI_CLK SPI_SI SPI0_MISO GPP_C1/SMBDATA SMB_ALERT#
AT3 W8 R3024 8.2K_0402_5%
SPI_WP# AV11 SPI0_MOSI GPP_C2/SMBALERT#
SPI_HOLD# AV13 SPI0_IO2 SPI - FLASH SMBUS, SMLINK
W4 SML0_CLK
SPI_CS0# AU4 SPI0_IO3 GPP_C3/SML0CLK AC10 SML0_DATA
C C
AU6 SPI0_CS0# GPP_C4/SML0DATA AA6 SML0_ALERT#
AU8 SPI0_CS1# GPP_C5/SML0ALERT#
+3V_SPI SPI0_CS2# AA4 PCH_SML1_CLK
SPI - TOUCH GPP_C6/SML1CLK W10 PCH_SML1_DAT
P9 GPP_C7/SML1DATA BB6 SML1_ALERT#
N8 GPP_D1 GPP_B23/SML1ALERT#/PCHHOT#
P3 GPP_D2 BK11
GPP_D3 GPP_A1/LAD0/ESPI_IO0
1

W12 BJ8 LPC_AD0 25,26

RC61 RC60 V7 GPP_D21 LPC GPP_A2/LAD1/ESPI_IO1 BG10 LPC_AD1 25,26
1K_0402_5% 1K_0402_5% N6 GPP_D22 GPP_A3/LAD2/ESPI_IO2 BP5 LPC_AD2 25,26
GPP_D0 GPP_A4/LAD3/ESPI_IO3 BP7 LPC_AD3 25,26
F12 GPP_A5/LFRAME#/ESPI_CS# BJ6 SUS_STAT# 1 @ LPC_FRAME# 25,26
C LINK
2

D12 CL_CLK GPP_A14/SUS_STAT#/ESPI_RESET# TC81 RC173 22_0402_5%

B12 CL_DATA BJ10 CLKOUT0 1 2
CL_RST# GPP_A9/CLKOUT_LPC0/ESPI_CLK PCH_PCI_CLK 25
BF5 CLKOUT1 1 2
SPI_WP# PCH_SPI_WP# GPP_A10/CLKOUT_LPC1 PM_CLKRUN# PCH_TPM_CLK 26
RC54 1 2 15_0402_5% BH11
EC_KBRST# BL10 GPP_A8/CLKRUN# RC174 TPM@ 22_0402_5%
25 EC_KBRST# GPP_A0/RCIN#
@ BN8
25,26 EC_INT_SERIRQ GPP_A6/SERIRQ
SPI_HOLD# RC55 1 2 15_0402_5% PCH_SPI_HOLD#
5 OF 20
SKYLAKE-Y_FCBGA1515
@ REV = 1 ?
@ @
1 2
R3005 100_0402_1%
SPI_HOLD# for SKL ES Sample
1. 1K PD, unmont 1K PU with HOLD functionality disabled
* 2. 100ohm PD, 1K PU, disabled after RSMRST# de-assertion

B B

+3VALW_PCH +3V_SPI

RC1711 2 0_0402_5%
for signal SMB_ALERT#:
+3VS
This signal has a weak internal pull-down.
RC1721 @ 2 0 = Disable Intel ME Crypto Transport Layer Security
0_0402_5%
(TLS) cipher suite (no confidentiality). (Default)
+3V_SPI 1 = Enable Intel ME Crypto Transport Layer Security
1. If support DS3, connect to +3VS and don't support EC mirror code; (TLS) cipher suite (with confidentiality). Must be
2. If don't support DS3, connect to +3VALW_PCH and support EC mirror code.
pulled up to support Intel AMT with TLS and Intel
SBA (Small Business Advantage) with TLS.

+3V_SPI

UC4
A A
PCH_SPI_CS0# 1 8
PCH_SPI_SO 2 /CS VCC 7 PCH_SPI_HOLD#
PCH_SPI_WP# 3 DO(IO1) /HOLD(IO3) 6 PCH_SPI_CLK
/WP(IO2) CLK 1
4 5 PCH_SPI_SI CC8
GND DI(IO0) .1U_0402_10V6-K
9
PAD_GND 2
W25Q64FVZPIG_WSON8_6X5

Security Classification LC Future Center Secret Data Title

Issued Date 2014/11/15 Deciphered Date 2013/08/05 MCP (RTC&AUDIO&SATA&SMBUS)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Miix4
Date: Monday, August 17, 2015 Sheet 7 of 37
5 4 3 2 1
 5 4 3 2 1

RC71 2 1 1M_0402_5%

YC2
+3VS
?
SKYLAKE_ULX XTAL24_OUT
UC1J 2 3
RPC3 @ GND1 OSC2
1 8 PCIE_CLKREQ#1 CLOCK SIGNALS XTAL24_IN 1 4
2 7 PCIE_CLKREQ#2 H35 J34 CLK_PCIE_XDP# 1 @ TC85 OSC1 GND2
3 6 PCIE_CLKREQ#0 F35 CLKOUT_PCIE_N1 CLKOUT_ITPXDP_N G34 CLK_PCIE_XDP 1 @ TC87
CLKOUT_PCIE_P1 CLKOUT_ITPXDP_P 1
4 5 PCIE_CLKREQ#5 PCIE_CLKREQ#1 AV9 1 24MHZ_6PF_7V24000032
GPP_B6/SRCCLKREQ1# BA15 SUSCLK CC11
GPD8/SUSCLK SUSCLK 21 2.7P_0402_50V9-B
10K_0804_8P4R_5% J36 CC12
RPC4 G36 CLKOUT_PCIE_N2 M1 XTAL24_IN +VCCCLK5 2.7P_0402_50V9-B 2
1 8 SYS_RESET# PCIE_CLKREQ#2 BD10 CLKOUT_PCIE_P2 XTAL24_IN L2 XTAL24_OUT 2
2 7 SATAGP1 GPP_B7/SRCCLKREQ2# XTAL24_OUT
SATAGP1 9 DIFFCLK_BIASREF
3 6 J38 P1 1 2 Differential Clock Bias Reference:
21 CLK_PCIE_WLAN# CLKOUT_PCIE_N3 XCLK_BIASREF
4 5 PIRQA# G38 RC72 2.7K_0402_1%
D PIRQA# 9,20 21 CLK_PCIE_WLAN WLAN_CLKREQ# CLKOUT_PCIE_P3 RTC_X1 D
AV5 BN19 Width: 12-15Mil
9,21 WLAN_CLKREQ# GPP_B8/SRCCLKREQ3# RTCX1 RTC_X2 RTC_X1
10K_0804_8P4R_5% BP18 Space:12Mil
H37 RTCX2
24 CLK_PCIE_CR#
F37 CLKOUT_PCIE_N4 BH18 SRTC_RST#
Length: 500Mil
24 CLK_PCIE_CR CR_CLKREQ# AV7 CLKOUT_PCIE_P4 SRTCRST# BN12 RTC_RST# need to check R value RC32 2 1 10M_0402_5% RTC_X2
9,24 CR_CLKREQ# GPP_B9/SRCCLKREQ4# RTCRST# RTC_RST# 25
2 1 PCH_PLT_RST# H39 YC1
RC92 100K_0402_5% F39 CLKOUT_PCIE_N5 1 2
PCIE_CLKREQ#5 BC5 CLKOUT_PCIE_P5
GPP_B10/SRCCLKREQ5# 32.768KHZ_9PF_X1A000141000200
2 2
PCIE_CLKREQ#0 BB10
GPP_B5/SRCCLKREQ0# CC4 CC5
9P_0402_50V8J 9P_0402_50V8J
10 OF 20 1 1
SKYLAKE-Y_FCBGA1515
REV = 1 ?
@

CRYSTAL
? 1, Space 15MIL
SKYLAKE_ULX
UC1K 2, No trace under crystal
SYSTEM POWER MANAGEMENT 3, Place on oppsosit side of MCP for temp influence
BC9 PCH_SLP_S0#_R RC1611 2 0_0402_5%
PCH_PLT_RST# GPP_B12/SLP_S0# PCH_SLP_S0# 12,25
BB8 AY14 PCH_SLP_S3#_R RC1421 2 0_0402_5%
21,22,24,25,26 PCH_PLT_RST# SYS_RESET# GPP_B13/PLTRST# GPD4/SLP_S3# PCH_SLP_S3# 25
H2 BF16 PCH_SLP_S4#_R RC1441 2 0_0402_5%
EC_RSMRST# SYS_RESET# GPD5/SLP_S4# PCH_SLP_S4# 25
BJ12 BH14 PCH_SLP_S5# 1 @ TC39
25 EC_RSMRST# RSMRST# GPD10/SLP_S5#
TC189 @ 1 A62 BN10 VCCRTC
VCCST_PWRGD 1 2 VCCST_PWRGD_R B61 PROCPWRGD SLP_SUS# BP11
R3031 60.4_0402_1% VCCST_PWRGD SLP_LAN# BH16
RC1451 2 0_0402_5% EC_SYS_PWROK_R J1 GPD9/SLP_WLAN# BE17
+3VALW_PCH 25 EC_SYS_PWROK EC_PCH_PWROK_R SYS_PWROK GPD6/SLP_A# SRTC_RST#
RC1461 2 0_0402_5% BP14 2 1
25 EC_PCH_PWROK EC_RSMRST# PCH_PWROK
1 2 BN15 BF14 EC_PBTN_OUT#_R 1 2 20K_0402_1% RC33
DSW_PWROK GPD3/PWRBTN# EC_PBTN_OUT# 25
RC140 0_0402_5% BD14 AC_PRESENT RC141 0_0402_5% RTC_RST# 2 1
BL6 GPD1/ACPRESENT BD16 BATLOW# 20K_0402_1% RC34
25 SUSPWRDNACK SUSACK#_R GPP_A13/SUSWARN#/SUSPWRDNACK GPD0/BATLOW#
not need reserve TC129 @ 1 BF9
GPP_A15/SUSACK# BF7 PME# 1 @ TC89 1 1
GPP_A11/PME#

1U_0402_10V6K

1U_0402_10V6K
PCIE_WAKE#

CC6

CC9
C RC79 1 @ 2 10K_0402_5% SUSPWRDNACK BP9 BG19 INTRUDER# C
21 PCIE_WAKE# LAN_WAKE# WAKE# INTRUDER#
BE15
GPD2/LAN_WAKE#

1
BC15 BC7 PCH_EXTPWR_GATE#
GPD11/LANPHYPC GPP_B11/EXT_PWR_GATE# PCH_EXTPWR_GATE# 13 2 2
BB16 BD6 VRALERT# 1 @ TC138
GPD7/RSVD GPP_B2/VRALERT#

AC_PRESENT 11 OF 20 TP71
RC81 1 2 10K_0402_5%
SKYLAKE-Y_FCBGA1515 @
REV = 1 ? VCCRTC
@
RPC5
1 8 BATLOW#
2 7 PCIE_WAKE# INTRUDER# RC41 2 1 1M_0402_5%
3 6 LAN_WAKE#
4 5 PCH_EXTPWR_GATE# CRB use 330K
+CPU_VCCST
10K_0804_8P4R_5%
PCH_EXTPWR_GATE# :Reserve pull up only?
2

EMC_NS@ RC137
1 2 EC_PCH_PWROK 1K_0402_5%
CC104 1000P_0402_50V7K
EMC_NS@
1

1 2 EC_SYS_PWROK RC139 SUSCLK 1 2

CC101 1000P_0402_50V7K VCCST_PWRGD 1 2 0_0402_5% 1K_0402_5% RC66
EC_VCCST_PWRGD 25
@

2
@ VCCRTC
CC140
1000P_0402_50V7K
1
DC1
SDM10U45LP-7_DFN1006-2-2 1 2

CC17
1U_0402_10V6K

CC26
.1U_0402_10V6-K
+3VL 2 1
B B

2 1
RC88 1 2 0_0402_5% AC_PRESENT
25 EC_PCH_ACIN RC35
RC1491 DC37 @
1 2 BAT_D 2 1 1 2
RTC_VCC

1
0_0402_5% SDM10U45LP-7_DFN1006-2-2
1.5K_0402_5% RC36
45.3K_0402_1%

2
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/11/15 Deciphered Date 2013/08/05 MCP (Clock,PM)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Miix4
Date: Monday, August 17, 2015 Sheet 8 of 37
5 4 3 2 1
 5 4 3 2 1

+3VALW_PCH
The signal has a weak internal pull-down. RPC17
+3VS 0 = Disable “ No Reboot” mode. (Default) USB_OC1# 8 1
1 = Enable “ No Reboot” mod
e USB_OC0# 7 2
USB_OC3# 6 3
@ USB_OC2# 5 4
2 1 GPP_B18
R685 2.2K_0402_5% 10K_0804_8P4R_5% +3VS
SKYLAKE_ULX ?
@ UC1H
2 1 GPP_B22
USB3.0 stand port
R686 2.2K_0402_5%
The signal has a weak internal pull-down. C20 C16 ISH_I2C0_SDA 1
RPC50
4 @
USB30_RX_N1 19
0 = boot from SPI. (Default) PCIE1_RXN/USB3_5_RXN USB3_1_RXN

1
A20 A16 ISH_I2C0_SCL 2 3
PCIE1_RXP/USB3_5_RXP USB3_1_RXP USB30_RX_P1 19
R690 G20 G16
1 = enable boot to LPC,
2.2K_0402_5% J20 PCIE1_TXN/USB3_5_TXN USB3_1_TXN J16
USB30_TX_N1 19
1K_0404_4P2R_5%
PCIE1_TXP/USB3_5_TXP SSIC / USB3 USB3_1_TXP USB30_TX_P1 19
@ RPC44
+1.8VALW B19 B15 SATAGP0 8 1
USB30_RX_N2 21

2
D19 PCIE2_RXN/USB3_6_RXN USB3_2_RXN/SSIC_1_RXN D15 WLAN_CLKREQ# 7 2
PCIE2_RXP/USB3_6_RXP USB3_2_RXP/SSIC_1_RXP USB30_RX_P2 8,21
21 WLAN_CLKREQ#
F19 F15 SATAGP2 6 3
D PCIE2_TXN/USB3_6_TXN USB3_2_TXN/SSIC_1_TXN USB30_TX_N2 21 CR_CLKREQ# D
RPC46 @ H19 H15 5 4
PCH_I2C_SDA2 PCIE2_TXP/USB3_6_TXP USB3_2_TXP/SSIC_1_TXP USB30_TX_P2 8,24
21 CR_CLKREQ#
4 1
3 2 PCH_I2C_SCL2 C22 C18 10K_0804_8P4R_5%
2.2K_0404_4P2R_5%
21 PCIE_PRX_DTX_N3
A22 PCIE3_RXN USB3_3_RXN/SSIC_2_RXN A18
reserve for WWAN
21 PCIE_PRX_DTX_P3 PCIE3_RXP USB3_3_RXP/SSIC_2_RXP
G22 G18 +3VS
RPC48
WLAN 21 PCIE_PTX_DRX_N3
J22 PCIE3_TXN USB3_3_TXN/SSIC_2_TXN J18
PCH_I2C_SDA3 21 PCIE_PTX_DRX_P3 PCIE3_TXP USB3_3_TXP/SSIC_2_TXP
1 8 @
2 7 PCH_I2C_SCL3 B21 B17
24 PCIE_PRX_DTX_N4 PCIE4_RXN USB3_4_RXN USB30_RX_N4 22
3 6 PCH_I2C_SDA4 D21 D17
24 PCIE_PRX_DTX_P4 PCIE4_RXP USB3_4_RXP USB30_RX_P4 22
4 5 PCH_I2C_SCL4 F21 F17
CR24 PCIE_PTX_DRX_N4
H21 PCIE4_TXN USB3_4_TXN H17
USB30_TX_N4 3D camera
22
RPC47
24 PCIE_PTX_DRX_P4 PCIE4_TXP USB3_4_TXP USB30_TX_P4 22 ISH_I2C1_SDA
2.2K_0804_8P4R_5% 1 4
C24 AJ6 ISH_I2C1_SCL 2 3
PCIE5_RXN USB2N_1 USB20_N1 19
A24 AJ4
+3VALW_PCH G24 PCIE5_RXP USB2P_1 USB20_P1 19 USB2.0 stand port 1K_0404_4P2R_5%
J24 PCIE5_TXN AH5
PCIE5_TXP USB2N_5 USB20_N2 32 +3VS
RPC49 @ AH3
1 8 PCH_I2C_SCL1 B23 USB2P_5 USB20_P2 32 DC IN combine port
2 7 PCH_I2C_SDA1 D23 PCIE6_RXN PCIE/USB3/SATA AF5
PCH_I2C_SDA0 PCIE6_RXP USB2N_7 USB20_N3 28 G_INT1
3 6 F23 AF3 1 4
4 5 PCH_I2C_SCL0 H23 PCIE6_TXN USB2 USB2P_7 USB20_P3 28 POGO 2 3 G_INT2
PCIE6_TXP AL6
USB2N_3 USB20_N4 21
2.2K_0804_8P4R_5% C26 AL4 RPC51 10K_0404_4P2R_5%
A26 PCIE7_RXN/SATA0_RXN USB2P_3 USB20_P4 21 BT RPC45
AO5804EL_SC89-6 G26 PCIE7_RXP/SATA0_RXP AG6 1 8 PCH_3D_PWREN#
PCIE7_TXN/SATA0_TXN USB2N_9 USB20_N5 21 PCH_WLAN_OFF#
J26 AG4 2 7
QC45A PCIE7_TXP/SATA0_TXP USB2P_9 USB20_P5 21 WWAN 3 6 PCH_BT_OFF#
B25 AM3 4 5 THS_IRQ
20 SATA_PRX_DTX_N1 PCIE8_RXN/SATA1A_RXN USB2N_2 USB20_N6 25
PCH_I2C_SCL0 6 1 D25 AM5
PM_I2C_SCL0 26 20 SATA_PRX_DTX_P1
F25 PCIE8_RXP/SATA1A_RXP USB2P_2 USB20_P6 25 Reserved for EC 10K_0804_8P4R_5%
+3VS @ +3VS
SSD 20 SATA_PTX_DRX_N1
H25 PCIE8_TXN/SATA1A_TXN N2 USB2_COMP_R 1 2
20 SATA_PTX_DRX_P1 PCIE8_TXP/SATA1A_TXP USB2_COMP
RPC28 ISH@ AF7 R3002 1 2 113_0402_1%
1 4 C28 USB2_ID AE6 RC1052 1 0_0402_5%
2 2 3 A28 PCIE9_RXN USB2_VBUSSENSE RC106 1K_0402_5%
5 PCIE9_RXP
G28 N12 USB_OC0#
PCIE9_TXN GPP_E9/USB2_OC0# USB_OC1# USB_OC0# 19
1K_0404_4P2R_5% Impedance Compensation Inputs J28 M11
@ PCIE9_TXP GPP_E10/USB2_OC1# F8 USB_OC2#
PCH_I2C_SDA0 GPP_E11/USB2_OC2# USB_OC3# USB_OC2# 32
C 3 4 Width 12~15Mil B27 B8 C
PM_I2C_SDA0 26 PCIE10_RXN GPP_E12/USB2_OC3#
Space >12Mil D27
F27 PCIE10_RXP F10
AO5804EL_SC89-6
Length 500Mil H27 PCIE10_TXN GPP_E4/DEVSLP0 H10
FULL_CARD_POWER_OFF# 21
+1.8VS
QC45B RC119 PCIE10_TXP GPP_E5/DEVSLP1 PCH_SATA_DEVSLP 20
L8 WWAN@
PCIE_RCOMPN GPP_E6/DEVSLP2 EC_SENSOR_INT 25
1 2 A9
PCIE_RCOMPP B10 PCIE_RCOMPN G11 SATAGP0 2 1 RC103 PCH_GNSS_DISABLE#
QC47A PCIE_RCOMPP GPP_E0/SATAXPCIE0/SATAGP0
AO5804EL_SC89-6 J11 SATAGP1
100_0402_1% PROC_PRDY# GPP_E1/SATAXPCIE1/SATAGP1 SATAGP1 8
1 D51 N10 SATAGP2 10K_0402_5%
PCH_I2C_SCL1 6 1 @ TC169 1 PROC_PREQ# B55 PROC_PRDY# GPP_E2/SATAXPCIE2/SATAGP2 +3VS
PM_I2C_SCL1 25,28 PROC_PREQ#
8,20 PIRQA# @ TC170 PIRQA# BF3 H8 1 2
+3VS GPP_A7/PIRQA# GPP_E8/SATALED# EC_SCI# 4,25
@ +3VS RC3027
RPC29 8 OF 20 0_0402_5%
4 1
2 SKYLAKE-Y_FCBGA1515
5 3 2 REV = 1 ?

2
10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%
@
2.2K_0404_4P2R_5%
@ ?
SKYLAKE_ULX

RC83

RC85

RC86

RC87
PCH_I2C_SDA1 3 4 UC1F
PM_I2C_SDA1 25,28

1
LPSS ISH
BC3 @ LTE@ @ @
QC47B AW10 GPP_B15/GSPI0_CS# P11 BOARD_ID0
AO5804EL_SC89-6 AW6 GPP_B16/GSPI0_CLK GPP_D9 T7
GPP_B18 BB4 GPP_B17/GSPI0_MISO GPP_D10 T5 BOARD_ID1
GPP_B18/GSPI0_MOSI GPP_D11 T11
QC43A GPP_D12
AO5804EL_SC89-6 PCH_WLAN_OFF# BB2 BOARD_ID2
21 PCH_WLAN_OFF# PCH_BT_OFF# GPP_B19/GSPI1_CS# ISH_I2C0_SDA
AW12 P7
PCH_I2C_SCL2 6 1
21 PCH_BT_OFF#
AW4 GPP_B20/GSPI1_CLK GPP_D5/ISH_I2C0_SDA P5 ISH_I2C0_SCL ISH_I2C0_SDA G
28 Sensor BOARD_ID3
PM_I2C_SCL2 22 ISH_I2C0_SCL 28
GPP_B22 AW8 GPP_B21/GSPI1_MISO
GPP_B22/GSPI1_MOSI
GPP_D6/ISH_I2C0_SCL Light sensor
+1.8VS +1.8VS T9 ISH_I2C1_SDA
GPP_D7/ISH_I2C1_SDA ISH_I2C1_SCL ISH_I2C1_SDA 28
@ AC8 T3
RPC21 21 UART_RX_DEBUG GPP_C8/UART0_RXD GPP_D8/ISH_I2C1_SCL ISH_I2C1_SCL 28 sensor debug hooks

2
10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%
4 1 AA8
2 21 UART_TX_DEBUG GPP_C9/UART0_TXD
5 3 2 AA10 AM7 PCH_GNSS_DISABLE#
GPP_C10/UART0_RTS# GPP_F10/I2C5_SDA/ISH_I2C2_SDA PCH_GNSS_DISABLE# 21
AA12 AT9
GPP_C11/UART0_CTS# GPP_F11/I2C5_SCL/ISH_I2C2_SCL

RC84

RC89

RC90

RC91
@ 2.2K_0404_4P2R_5%
BOARD_ID0 AD5 U10

1
PCH_I2C_SDA2 3 4 BOARD_ID1 AD7 GPP_C20/UART2_RXD GPP_D13/ISH_UART0_RXD/SML0BDATA U4
B PM_I2C_SDA2 22 BOARD_ID2 GPP_C21/UART2_TXD GPP_D14/ISH_UART0_TXD/SML0BCLK B
AD3 U6 @ @ @
BOARD_ID3 AD9 GPP_C22/UART2_RTS# GPP_D15/ISH_UART0_RTS# V9
GPP_C23/UART2_CTS# GPP_D16/ISH_UART0_CTS#/SML0BALERT# UN_LTE@
QC43B PCH_I2C_SDA0 AD11 AC6
AO5804EL_SC89-6 PCH_I2C_SCL0 AB3 GPP_C16/I2C0_SDA GPP_C12/UART1_RXD/ISH_UART1_RXD AC4
reserved GPP_C17/I2C0_SCL GPP_C13/UART1_TXD/ISH_UART1_TXD AB7
PCH_I2C_SDA1 AB9 GPP_C14/UART1_RTS#/ISH_UART1_RTS# AB5
PCH_I2C_SCL1 AB11 GPP_C18/I2C1_SDA GPP_C15/UART1_CTS#/ISH_UART1_CTS#
QC46A
AO5804EL_SC89-6
touch panel GPP_C19/I2C1_SCL BF11
PCH_I2C_SDA2 GPP_A18/ISH_GP0 ISH_GP0 28
AP3 BD2 BOARD_ID3 Description
PCH_I2C_SCL3 PCH_I2C_SCL2 GPP_F4/I2C2_SDA GPP_A19/ISH_GP1 PCH_3D_PWREN# 22
6 1 AP7 BJ1 G_INT1
PM_I2C_SCL3 WF
22 Camera GPP_F5/I2C2_SCL GPP_A20/ISH_GP2 BL3 G_INT2
G_INT1 26 G sensor interrupt
+1.8VS +1.8VS PCH_I2C_SDA3 AP5 GPP_A21/ISH_GP3 BJ3 PCH_THS_RST#
G_INT2 28 light sensor interrupt 0 NO LTE SKU
@ PCH_I2C_SCL3 AT7 GPP_F6/I2C3_SDA GPP_A22/ISH_GP4 BD4 THS_IRQ PCH_THS_RST# 28
4
RPC26
1
UF Camera GPP_F7/I2C3_SCL GPP_A23/ISH_GP5 BJ4
THS_IRQ 28
2 PCH_I2C_SDA4 Sx_EXIT_HOLDOFF#/GPP_A12/BM_BUSY#/ISH_GP6 ISH_GP6 28
5 3 2 AN4 1 LTE SKU
PCH_I2C_SCL4 AN6 GPP_F8/I2C4_SDA
@ 2.2K_0404_4P2R_5%
P Sensor GPP_F9/I2C4_SCL

PCH_I2C_SDA3 3 4 BOARD ID table

PM_I2C_SDA3 22 6 OF 20 BOARD_ID2 BOARD_ID1 BOARD_ID0 DRAM
SKYLAKE-Y_FCBGA1515 0 0 0 4G SK HYNIX
?
REV = 1 0 0 1 4G MICRON
QC46B @ 0 1 0 4G SAMSUNG
AO5804EL_SC89-6 0 1 1 8G SK HYNIX
1 0 0 8G MICRON
0_0402_5%
GPIO Mapping 1 0 1 8G SAMSUNG
ISH_I2C0_SCL 1 2 GroupA/B/C/D/E/G -- Usued for 3.3V power plane 1 1 0
RC159 1 1 1
@
GroupF-Used for 1.8V Power Plane
QC173A
AO5804EL_SC89-6 PCH_I2C_SCL0 1 2 PM_I2C_SCL0
RC147 0_0402_5%
PCH_I2C_SCL4 6 1 PCH_I2C_SDA0 1 2 PM_I2C_SDA0 +3VS
PM_I2C_SCL4 26
RC148 0_0402_5%
I2C Mapping
+1.8VS +1.8VS @ 0_0402_5% GroupC -- Usued for 3.3V power plane
@ RPC30 ISH_I2C0_SDA 1 2
4 1 RC160
GroupF-Used for 1.8V Power Plane
A
2 3 2 0_0402_5% PCH_THS_RST# 10K_0402_5% 2 @ 1 RC94 A
5
PCH_I2C_SCL1 1 2 PM_I2C_SCL1
@ 2.2K_0404_4P2R_5% RC149 0_0402_5%
I2C Assignment 10K_0402_5% 2 @ 1 RC95
@ PCH_I2C_SDA1 1 2 PM_I2C_SDA1 I2C0--sensor
PCH_I2C_SDA4 3 4 RC150 0_0402_5%
PM_I2C_SDA4 26 PCH_I2C_SCL2 1 2 PM_I2C_SCL2 I2C1--Touch panel
RC151 0_0402_5% I2C2--WF camera
QC173B
PCH_I2C_SDA2 1 2 PM_I2C_SDA2 I2C3--UF camera
RC152 0_0402_5% I2C4--P sensor
AO5804EL_SC89-6 PCH_I2C_SCL3 1 2 PM_I2C_SCL3
RC153 0_0402_5% Title
PCH_I2C_SDA3 1 2 PM_I2C_SDA3 Security Classification LC Future Center Secret Data
RC154
PCH_I2C_SCL4 1 2 PM_I2C_SCL4
Issued Date 2014/11/15 Deciphered Date 2013/08/05 MCP (GPIO,USB,PCIE)
RC157 0_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
@ AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
PCH_I2C_SDA4 1 2 PM_I2C_SDA4 C 1.0
RC158 @ 0_0402_5%
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Miix4
Date: Monday, August 17, 2015 Sheet 9 of 37
5 4 3 2 1
 5 4 3 2 1

CPU_CFG4 1 2
RC67 1K_0402_1%
D CFG4 Setting: D
1K PD, used for Enable EDP Panel

SKYLAKE_ULX ?
UC1T

@ TC142 1 CPU_CFG0 G52 BL64

F53 CFG[0] RSVD_TP_04 BG47
@ TC143 1 CPU_CFG2 J52 CFG[1] RSVD_TP_03
H53 CFG[2] BA17
CPU_CFG4 H55 CFG[3] RSVD_TP_02 AY18
D55 CFG[4] RSVD_TP_01
C56 CFG[5] BF18
F55 CFG[6] RSVD_37 BE19
D61 CFG[7] RSVD_36
G58 CFG[8]
D57 CFG[9] BA23
F61 CFG[10] TP5 AY22
J60 CFG[11] TP6
J58 CFG[12]
H61 CFG[13] R12
H59 CFG[14] RSVD_35 P13
CFG[15] RSVD_34 M15
J54 RSVD_33 L16
G54 CFG[16] RSVD_32
CFG[17] L18
G56 RSVD_31 M17
J56 CFG[18] RSVD_30
CFG[19] AH7
1 2 CFG_RCOMP_R A54 RSVD_29
R3006 CFG_RCOMP K12
49.9_0402_1% A60 RSVD_28 H12
ITP_PMODE RSVD_27
B4 BN3
B3 RSVD_01 RSVD_26 BP3
RSVD_02 RSVD_25
C C
F3 L22
F1 RSVD_03 RSVD_24 M23
RSVD_04 RSVD_23
VCCST L36 BN1
L38 RSVD_05 TP4
RSVD_06 AY20
RSVD_22
1

BA19 BA21
R3007 BB18 RSVD_07 RSVD_21 R3009
150_0402_5% RSVD_08 BB14 RSVD_BB14 1 2
BC19 RSVD_20
BD18 RSVD_09 M25 0_0402_5%
2

RSVD_10 RSVD_19 L24

D49 RSVD_18
M21 RSVD_11 L28
RSVD_L20 L20 RSVD_12 RSVD_17 M27
M19 RSVD_13 RSVD_16
RSVD_14 BJ15
TP1
1

L26 BJ17
@ R3008 RSVD_15 RESERVED SIGNALS TP2
10K_0402_5%
20 OF 20
SKYLAKE-Y_FCBGA1515
2

REV = 1 ?
@

B SKYLAKE_ULX ? B
UC1I

H29 H31
F29 CSI2_DN0 CSI2_CLKN0 F31
F33 CSI2_DP0 CSI2_CLKP0 D31
CSI2_DN1 CSI2_CLKN1 PCH_CSI2_CLKN1 22
H33 B31 WF
CSI2_DP1 CSI2_CLKP1 PCH_CSI2_CLKP1 22
J30 C34
CSI2_DN2 CSI2_CLKN2 PCH_CSI2_CLKN0 22
G30 CSI-2 A34 UF
CSI2_DP2 CSI2_CLKP2 PCH_CSI2_CLKP0 22
J32 D39 R3003
G32 CSI2_DN3 CSI2_CLKN3 B39 100_0402_1%
CSI2_DP3 CSI2_CLKP3 A11 CSI2_COMP_R 1 2
D29 CSI2_COMP N4
22 PCH_CSI2_DN2 CSI2_DN4 GPP_D4/FLASHTRIG PCH_FLASH__STROBE 22
B29
22 PCH_CSI2_DP2 C32 CSI2_DP4 eMMC
WF 22 PCH_CSI2_DN3 A32 CSI2_DN5 AN12
22 PCH_CSI2_DP3 C30 CSI2_DP5 GPP_F13/EMMC_DATA0 AP9
A30 CSI2_DN6 GPP_F14/EMMC_DATA1 AN10
D33 CSI2_DP6 GPP_F15/EMMC_DATA2 AJ10
B33 CSI2_DN7 GPP_F16/EMMC_DATA3 AM9
CSI2_DP7 GPP_F17/EMMC_DATA4 AL12
D35 GPP_F18/EMMC_DATA5 AJ12
22 PCH_CSI2_DN0 B35 CSI2_DN8 GPP_F19/EMMC_DATA6 AN8
22 PCH_CSI2_DP0 C36 CSI2_DP8 GPP_F20/EMMC_DATA7
UF 22 PCH_CSI2_DN1 A36 CSI2_DN9 AL10
22 PCH_CSI2_DP1 D37 CSI2_DP9 GPP_F21/EMMC_RCLK AL8
B37 CSI2_DN10 GPP_F22/EMMC_CLK AM11
C38 CSI2_DP10 GPP_F12/EMMC_CMD
A38 CSI2_DN11 BC1 EMMC_RCOMP_R 1 2
CSI2_DP11 EMMC_RCOMP R3004 200_0402_1%
9 OF 20
SKYLAKE-Y_FCBGA1515
REV = 1 ?
@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/11/15 Deciphered Date 2013/08/05 MCP (OTHER)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Miix4
Date: Monday, August 17, 2015 Sheet 10 of 37

5 4 3 2 1
 5 4 3 2 1

CPU_CORE +CPU_VCCGT +CPU_VCCGT

CPU_CORE +CPU_VCCGT
SKYLAKE_ULX
?
SKYLAKE_ULX ?
Place on secondary side, underneath the package
UC1L UC1M x12
24A 24A
A64 M58 AA53 AC53
AE32 VCC_01 VCC_90 N34 AB62 VCCGT_01 VCCGT_107 AC63
VCC_02 VCC_89 VCCGT_02 VCCGT_106

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K
AE40 N54 AC47 AD62 1 1 1 1 1 1 1 1 1 1 1 1
VCC_03 VCC_88 VCCGT_03 VCCGT_105

CC1110

CC1111

CC1112

CC1113

CC1114

CC1115

CC1116

CC1117

CC1118

CC1119

CC1120

CC1121
AH41 N63 AC55 AE59
AN32 VCC_04 VCC_87 P64 AD54 VCCGT_04 VCCGT_104 AF46
AT33 VCC_05 VCC_86 R61 AD64 VCCGT_05 VCCGT_103 AG53
AT41 VCC_06 VCC_85 V41 AE61 VCCGT_06 VCCGT_102 AK47 2 2 2 2 2 2 2 2 2 2 2 2
J64 VCC_07 VCC_84 AC41 AF47 VCCGT_07 VCCGT_101 AN44
L48 VCC_08 VCC_83 AE38 AJ53 VCCGT_08 VCCGT_100 AN51
M33 VCC_09 VCC_82 AH32 AK49 VCCGT_09 VCCGT_99 AT49
M43 VCC_10 VCC_81 AL41 AN46 VCCGT_10 VCCGT_98 N48 +CPU_VCCGT CD@ CD@
M53 VCC_11 VCC_80 AT32 AT43 VCCGT_11 VCCGT_97 T44
VCC_12 VCC_79 VCCGT_12 VCCGT_96
Place on secondary side, underneath the package
M64 AT40 AT50 T51 x12 placeholder--not Stuff
D
N40 VCC_13 VCC_78 H63 N50 VCCGT_13 VCCGT_95 U59 D
N59 VCC_14 VCC_77 L46 T46 VCCGT_14 VCCGT_94 V58
P60 VCC_15 VCC_76 L63 T54 VCCGT_15 VCCGT_93 W55
VCC_16 VCC_75 VCCGT_16 VCCGT_92

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K
R57 M41 U61 Y43 1 1 1 1 1 1 1 1 1 1 1 1
VCC_17 VCC_74 VCCGT_17 VCCGT_91

CC1182

CC1183

CC1184

CC1185

CC1186

CC1187

CC1188

CC1189

CC1190

CC1191

CC1192

CC1193
T41 M51 V60 Y50 @ @ @ @ @ @ @ @ @ @
AA32 VCC_18 VCC_73 M62 W57 VCCGT_18 VCCGT_90 Y60
AE33 VCC_19 VCC_72 N38 Y44 VCCGT_19 VCCGT_89 AB56
AE41 VCC_20 VCC_71 N57 Y51 VCCGT_20 VCCGT_88 AC43 2 2 2 2 2 2 2 2 2 2 2 2
AK32 VCC_21 VCC_70 P58 Y62 VCCGT_21 VCCGT_87 AC50
AN41 VCC_22 VCC_69 R41 AB54 VCCGT_22 VCCGT_86 AC59
AT35 VCC_23 VCC_68 T32 AB64 VCCGT_23 VCCGT_85 AD58
B64 VCC_24 VCC_67 Y41 AC49 VCCGT_24 VCCGT_84 AE55 +CPU_VCCGT
L40 VCC_25 VCC_66 AC32 AC57 VCCGT_25 VCCGT_83 AF43
VCC_26 VCC_65 VCCGT_26 VCCGT_82
Place on secondary side, underneath the package
L50 AE36 AD56 AF50 x12 placeholder--not Stuff
M35 VCC_27 VCC_64 AF41 AE53 VCCGT_27 VCCGT_81 AK44
M45 VCC_28 VCC_63 AL32 AE63 VCCGT_28 VCCGT_80 AK51
M56 VCC_29 VCC_62 AR41 AF49 VCCGT_29 VCCGT_79 AN49
VCC_30 VCC_61 VCCGT_30 VCCGT_78

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K
N32 AT38 AK43 AT46 1 1 1 1 1 1 1 1 1 1 1 1
VCC_31 VCC_60 VCCGT_31 VCCGT_77

CC1212

CC1213

CC1215

CC1214

CC1217

CC1216

CC1219

CC1218

CC1221

CC1220

CC1222

CC1223
N42 F64 AK50 N44 @ @ @ @ @ @ @ @ @ @ @ @
N61 VCC_32 VCC_59 L44 AN47 VCCGT_32 VCCGT_76 R53
P62 VCC_33 VCC_58 L54 AT44 VCCGT_33 VCCGT_75 T49
R59 VCC_34 VCC_57 M39 AT51 VCCGT_34 VCCGT_74 U55 2 2 2 2 2 2 2 2 2 2 2 2
V32 VCC_35 VCC_56 M49 R51 VCCGT_35 VCCGT_73 V54
AA41 VCC_36 VCC_55 M60 CPU_CORE T47 VCCGT_36 VCCGT_72 V64
AE35 VCC_37 VCC_54 N36 RC3015 U53 VCCGT_37 VCCGT_71 W61
AF32 VCC_38 VCC_53 N55 100_0402_1% U63 VCCGT_38 VCCGT_70 Y47
AK41 VCC_39 VCC_52 1 2 V62 VCCGT_39 VCCGT_69 Y56
AR32 VCC_40 L34 CPU_VCC_SENSE W59 VCCGT_40 VCCGT_68 AN50
AT36 VCC_41 VCC_SENSE L32 CPU_VSS_SENSE CPU_VCC_SENSE 36 Y46 VCCGT_41 VCCGT_67 AT47 +CPU_VCCGT
D64 VCC_42 VSS_SENSE 1 2 CPU_VSS_SENSE 36 Y54 VCCGT_42 VCCGT_66 N46
VCC_43 VCCGT_43 VCCGT_65
Place on the same side
L42 Y64 T43 1U x2>10U x2>47U x9
L52 VCC_44 100_0402_1% AB58 VCCGT_44 VCCGT_64 T50
M37 VCC_45 B58 SVID_ALERT# RC3017 AC44 VCCGT_45 VCCGT_63 U57
VCC_46 VIDALERT# VCCGT_46 VCCGT_62

10U_0402_6.3V6-M

10U_0402_6.3V6-M
1U_0201_6.3V6-K

1U_0201_6.3V6-K
M47 A56 SVID_CLK AC51 V56
VCC_47 VIDSCK VCCGT_47 VCCGT_61

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
R63 A58 SVID_DAT AC61 W53 1 1 1 1 1 1 1 1
VCC_48 VIDSOUT VCCGT_48 VCCGT_60

CC1122

CC1123

CC1124

CC1125

CC1179

CC1151

CC1194

CC1172
P56 VCCSTG AD60 W63 @ @
R32 VCC_49 AA26 AE57 VCCGT_49 VCCGT_59 Y49 +CPU_VCCGT
Y32 VCC_50 VCCSTG_02 AC26 AF44 VCCGT_50 VCCGT_58 Y58 RC3018
C C
VCC_51 VCCSTG_01 AF51 VCCGT_51 VCCGT_57 AN43 100_0402_1% 2 2 2 2 2 2 2 2
AK46 VCCGT_52 VCCGT_56 1 2
CPU POWER 1 OF 4 VCCGT_53
AB60 N52 CPU_VCCGT_SENSE
VCCGT_54 VCCGT_SENSE CPU_VCCGT_SENSE 36
AC46 P52 CPU_VSSGT_SENSE
VCCGT_55 VSSGT_SENSE CPU_VSSGT_SENSE 36
12 OF 20 1 2
CPU POWER 2 OF 4
SKYLAKE-Y_FCBGA1515 100_0402_1%
REV = 1 ?
13 OF 20 RC3019
@ SKYLAKE-Y_FCBGA1515
CPU_CORE Place on secondary side, underneath the package
REV = 1 ? X20
@
VCCST

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K
1 1 1 1 1 1 1 1 1 1

CC1095

CC1096

CC1097

CC1098

CC1099

CC1100

CC1101

CC1102

CC1196

CC1197
2 2 2 2 2 2 2 2 2 2
.1U_0402_10V6-K

@
1

CC42

@
CD@
2

100_0402_1%
56_0402_5%

54.9_0402_1%

2
RC1544
RC131

RC132

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K
1 1 1 1 1 1 1 1 1 1
1

CC1103

CC1104

CC1105

CC1106

CC1107

CC1108

CC1109

CC1198

CC1199

CC1200
2 2 2 2 2 2 2 2 2 2
RC1331 2 220_0402_5% SVID_ALERT#
6 CPU_SVID_ALRT#
CD@ CD@
RC1341 2 0_0402_5% SVID_CLK
36 CPU_SVID_CLK
CPU_CORE Place on secondary side, underneath the package
X12 placeholder not stuff
RC1351 2 0_0402_5% SVID_DAT
36 CPU_SVID_DAT

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K
B B
1 1 1 1 1 1 1 1 1 1

CC1206

CC1207

CC1208

CC1209

CC1210

CC1201

CC1202

CC1203

CC1204

CC1205
1, Alert# Route Between CLK and Data @ @ @ @ @ @ @ @

2 2 2 2 2 2 2 2 2 2

CPU_CORE
Place on secondary side, underneath the package
X8

10U_0402_6.3V6-M
10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
1 1 1 1 1 1 1 1

CC1086

CC1085

CC1084

CC1080

CC1082

CC1083

CC1081

CC1087
2 2 2 2 2 2 2 2

CD@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/11/15 Deciphered Date 2013/08/05 MCP (Power)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Miix4
Date: Monday, August 17, 2015 Sheet 11 of 37
5 4 3 2 1
 5 4 3 2 1
+CPU_VCCIO

Place on secondary side, underneath the package

+CPU_VDDQ +CPU_VCCIO +CPU_VCCSA x9
?
SKYLAKE_ULX SKYLAKE_ULX ?
2A UC1N UC1O +CPU_VCCG0

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K
4.1A 1 1 1 1 1 1 1 1 1

CC1158

CC1159

CC1160

CC1161

CC1168

CC1169

CC1170

CC1171

CC1241
AH64 AC23 AA29 AA35
BA27 VDDQ_01 VCCIO_13 AF24 AF30 VCCSA_01 VCCG0_12 R38
BA37 VDDQ_02 VCCIO_12 AN26 AN29 VCCSA_02 VCCG0_11 Y35
BA49 VDDQ_03 VCCIO_11 AC24 L30 VCCSA_03 VCCG0_10 AA38 2 2 2 2 2 2 2 2 2
BP32 VDDQ_04 VCCIO_10 AF26 T30 VCCSA_04 VCCG0_09 T35
VDDQ_05 VCCIO_09 VCCSA_05 VCCG0_08
Processor IA cores gated power rail,
BP50 AR26 AC29 Y38 connects to board capacitors for filtering.
AK64 VDDQ_06 VCCIO_08 AE23 AH29 VCCSA_06 VCCG0_07 AC35
BA29 VDDQ_07 VCCIO_07 AH26 AN30 VCCSA_07 VCCG0_06 T38 +CPU_VCCIO CD@ CD@
BA41 VDDQ_08 VCCIO_06 AT26 M31 VCCSA_08 VCCG0_05 AC38
BA51 VDDQ_09 VCCIO_05 AE24 V29 VCCSA_09 VCCG0_04 V35
VDDQ_10 VCCIO_04 VCCSA_10 VCCG0_03
Place on secondary side, underneath the package
BP34 AK26 AC30 R35 x4
BP56 VDDQ_11 VCCIO_03 AE26 AK29 VCCSA_11 VCCG0_02 V38 +CPU_VCCG1
AT64 VDDQ_12 VCCIO_02 AL26 +CPU_VCCIO AR29 VCCSA_12 VCCG0_01
BA31 VDDQ_13 VCCIO_01 N30 VCCSA_13 AF35
VDDQ_14 VCCSA_14 VCCG1_12

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K
BA43 AV26 Y29 AK38 1 1 1 1
VDDQ_15 VCCIO_DDR_26 VCCSA_15 VCCG1_11

CC1155

CC1156

CC1157

CC1242
BN64 AV36 AE29 AR35
BP40 VDDQ_16 VCCIO_DDR_25 AV46 AK30 VCCSA_16 VCCG1_10 AF38
D BP58 VDDQ_17 VCCIO_DDR_24 AW31 VCCSA_17 VCCG1_09 D
VDDQ_18 VCCIO_DDR_23
3A +CPU_VCCSA_DDR R29
VCCSA_18 VCCG1_08
AL35
2 2 2 2
AV64 AW41 Y30 AR38
BA33 VDDQ_19 VCCIO_DDR_22 AW51 AF29 VCCSA_19 VCCG1_07 AH35 CD@
BA45 VDDQ_20 VCCIO_DDR_21 AV28 AL29 VCCSA_20 VCCG1_06 AL38
BP24 VDDQ_21 VCCIO_DDR_20 AV38 T29 VCCSA_21 VCCG1_05 AH38
BP42 VDDQ_22 VCCIO_DDR_19 AV48 +CPU_VCCSA VCCSA_22 VCCG1_04 AN35 +CPU_VCCIO
BP64 VDDQ_23 VCCIO_DDR_18 AW33 RC3022 AT29 VCCG1_03 AK35
BA25 VDDQ_24 VCCIO_DDR_17 AW43 AT30 VCCSA_DDR_01 VCCG1_02 AN38
VDDQ_25 VCCIO_DDR_16
100_0402_1%
VCCSA_DDR_02 VCCG1_01
Place on secondary side, underneath the package
BA35 AV30 2 1 x7 palceholder
BA47 VDDQ_26 VCCIO_DDR_15 AV40 CPU_VCCSA_SENSE M29
BP26 VDDQ_27 VCCIO_DDR_14 36
AV50 CPU_VCCSA_SENSE CPU_VSSSA_SENSE N28 VCCSA_SENSE
BP48 VDDQ_28 VCCIO_DDR_13 36
AW35 CPU_VSSSA_SENSE 2 1 VSSSA_SENSE
VDDQ_29 VCCIO_DDR_12 CPU POWER 4 OF 4

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K
VDDQC BA39 AW45 1 1 1 1 1 1 1
VDDQC VCCIO_DDR_11 100_0402_1%

CC1246

CC1247

CC1248

CC1249

CC1250

CC1251

CC1252
AV32 @ @ @ @ @ @ @
VCCIO_DDR_10 RC3023
1.0V 100mA VCCST V26
VCCST_01 VCCIO_DDR_09
AV42 15 OF 20
Y26 AW27
VCCST_02 VCCIO_DDR_08 SKYLAKE-Y_FCBGA1515 2 2 2 2 2 2 2
AW37 REV = 1 ?
VCCSTG R26 VCCIO_DDR_07 AW47
VCCSTG_03 VCCIO_DDR_06 @
T26 AV34
VCCSTG_04 VCCIO_DDR_05 AV44
VCCPLL_OC AE27 VCCIO_DDR_04 AW29 +CPU_VCCIO
AF27 VCCPLL_OC_01 VCCIO_DDR_03 AW39 RC3020 +CPU_VCCIO
VCCPLL_OC_02 VCCIO_DDR_02 AW49 100_0402_1%
VCCIO_DDR_01
1.0V 100mA VCCPLL R27
VCCPLL_01
1 2 Place on secondary side, underneath the package
T27 AT24 x3 palceholder
VCCPLL_02 VCCIO_SENSE CPU_VCCIO_SENSE 34
AR24
VSSIO_SENSE CPU_VSSIO_SENSE 34

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K
1 2 1 1 1
CPU POWER 3 OF 4

CC1243

CC1244

CC1245
Place as close to the package as possible @ @ @
100_0402_1%
RC3021
14 OF 20 2 2 2
+CPU_VCCIO +CPU_VCCIO
SKYLAKE-Y_FCBGA1515
REV = 1 ?
@

1U_0201_6.3V6-K

22U_0603_6.3V6-M

1U_0201_6.3V6-K
+CPU_VCCSA
Sustain voltage for processor standby modes 1 1 1 Place on secondary side, underneath the package

CC1152

CC1153

CC1224
@ x10 placeholder
Gated sustain voltage for processor standby modes
+CPU_VCCST VCCST
+CPU_VCCSTG VCCSTG 2 2 2

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K
+DDR_1.2V Need short +CPU_VDDQ 2 1 1 1 1 1 1 1 1 1 1 1

CC1139

CC1140

CC1141

CC1142

CC1143

CC1144

CC1145

CC1154

CC1253

CC1254
R3011 0_0603_5% 2 1 @ @ @ @ @ @ @ @ @ @
0.1u_0201_10V6K

0.1u_0201_10V6K
JC1 @ 1 R3012 0_0603_5% 1
CC1174

CC1175
1 2
1 2 2 2 2 2 2 2 2 2 2 2

JUMP_43X79 2 2

Processor PLLs power rails +CPU_VDDQ

C C
+CPU_VDDQ VCCPLL_OC Place on secondary side, underneath the package +CPU_VCCSA
RC275 Processor PLLs power rails x9
1 2 0_0402_5% Place as close to the package as possible
+CPU_VCCST VCCPLL

1U_0201_6.3V6-K
UN_PLL_OC@ +CPU_VCCSA +CPU_VCCSA_DDR

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K
2 1 1 1 1 1 1 1 1 1 1 1 1
0.1u_0201_10V6K

CC1985

CC1986

CC1162

CC1163

CC1164

CC1165

CC1166

CC1167

CC1229

CC1230

CC1231
R3013 0_0603_5% 1 1 1
CC1178

CC1211
system memory clk power 2 1 @
+CPU_VDDQ VDDQC RC1501 0_0603_5% CC1195
2 2 2 2 2 2 2 2 2 2 2 22U_0402_4V6-M
1 2 2 CD@ 2 2
0_0603_5% R3010
0.1u_0201_10V6K

1
CC1173

+CPU_VDDQ
+1.0VALW +CPU_VCCST
2 AON7408L_DFN8-5 Place on secondary side, underneath the package +CPU_VCCSA_DDR Place on secondary side, underneath the package
QC12 x9 for VCCSA_DDR

1
S1

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K
5 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1
D S2

CC1988

CC1987

CC1232

CC1233

CC1234

CC1235

CC1236

CC1237

CC1238

CC1240

CC1239

CC1255

CC1256
1 3 @
CC222 S3 CC1150
G

0.1U_0402_16V4Z @ 22U_0402_4V6-M
2 2 2 2 2 2 2 2 2 2 2 2 2 2
4

B+ 2
RC69
+5VALW 1 2
1

RC70 CD@ CD@

10K_0402_5%
1

1 470_0603_5%
RC63
6

QC167A D @ R3028 +CPU_VCCG1 +CPU_VCCG0

1 2 EN_VCCST# 2 CC223 62K_0402_5% @ Place on secondary side, underneath the package
2

G 0.01U_0402_25V7K Place on secondary side, underneath the package x6

2
2N7002KDWH_SOT363-6 6 x6
2

47K_0402_5% S QC168A
1

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K
1 1 1 1 1 1

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

CC1957

CC1959

CC1961

CC1963

CC1965

CC1967
@ 1 1 1 1 1 1
3

CC1969

CC1971

CC1974

CC1975

CC1977

CC1979
QC167B D EN_VCCST# 2
RC62 1 2 0_0402_5%
5
25 EC_VCCST_PWREN G 2 2 2 2 2 2
2N7002KDWH_SOT363-6 AO5804EL_SC89-6 2 2 2 2 2 2
S 1
1
4

CC228
0.1U_0402_16V4Z @
+CPU_VCCG0 CD@ CD@
2 +CPU_VCCG1 CD@ CD@ CD@
Place on secondary side, underneath the package
B Place on secondary side, underneath the package B
x6
x6
+1.0VALW +CPU_VCCSTG
AON7408L_DFN8-5

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K
QC13 1 1 1 1 1 1
0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

CC1958

CC1960

CC1962

CC1964

CC1966

CC1968
1 1 1 1 1 1
CC1970

CC1972

CC1973

CC1976

CC1978

CC1980
1 CD@
5 S1 2 2 2 2 2 2 2
D S2 3 2 2 2 2 2 2
1 S3
CC224
G

0.1U_0402_16V4Z @
4

B+ 2
RC74
+3VALW
+5VALW 1 2
1

RC76
10K_0402_5%
1

1 1 470_0603_5%
RC75
6

When PCH is idle and processor is in C10 state, CC233 QC170A D @ R3029
0.1U_0402_16V4Z 1 2 EN_VCCSTG# 2 CC225 62K_0402_5% @
2

UC5 G 0.01U_0402_25V7K
2 2
2N7002KDWH_SOT363-6 3
2

1 5 47K_0402_5% S QC168B
8,25 PCH_SLP_S0#
1

A VCC
EC_SUS_VCCP 2 +CPU_VDDQ VCCPLL_OC
25,34 EC_SUS_VCCP B
3

QC170B D EN_VCCSTG# 5 @ AON7408L_DFN8-5

3 4 RC77 1 2 0_0402_5% 5 QC15
GND Y G
Slp_S3 enable
2N7002KDWH_SOT363-6 AO5804EL_SC89-6
4
350mA
74LVC1G08SE-7_SOT353-5 S 1
1
4

CC229 5 S1 2
0.1U_0402_16V4Z @ D S2 3
1 S3
CC226
G

RC1577 1 2 0_0402_5% 2 0.1U_0402_16V4Z @

VCCPLL_OC@
4

B+ 2
@ RC82
+3VALW
+5VALW 1 2

1
VCCPLL_OC@ RC93
10K_0402_5%
1

1 VCCPLL_OC@ 1 470_0603_5%
RC80
6

CC234 QC171A D @ R3030

0.1U_0402_16V4Z 1 2 EN_VCCPLL_OC# 2 CC227 62K_0402_5% @

2
UC6 VCCPLL_OC@ G 0.01U_0402_25V7K
2 2
2N7002KDWH_SOT363-6 6
2

PCH_SLP_S0# 1 5 47K_0402_5% S QC172A

1

A VCC VCCPLL_OC@ VCCPLL_OC@

VCCST : Sustain voltage for processor in Standby modes
EC_SUS_VCCP 2
B
3

0_0402_5% QC171B D EN_VCCPLL_OC# 2 @

A VCCPLL : CPU PLL power rails 3 4 RC98 1 2 5 A
GND Y G
Slp_S3 enable
VCCPLL_OC: CPU digital PLL power rails VCCPLL_OC@ 2N7002KDWH_SOT363-6 AO5804EL_SC89-6
74LVC1G08SE-7_SOT353-5 S 1
4

VCCPLL_OC@ 1 VCCPLL_OC@
VCCSTG : Gated version of VCCST CC230
0.1U_0402_16V4Z @

1 2 2
0_0402_5%
RC1578 @

Security Classification LC Future Center Secret Data Title

Issued Date 2014/11/15 Deciphered Date 2013/08/05 MCP(Power1)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Miix4
Date: Monday, August 17, 2015 Sheet 12 of 37

5 4 3 2 1
 5 4 3 2 1

+CPU_VCCPRIM +VCCMPHYGT_1P0 +3VALW_PCH

+1.0VALW

1 1 1522mA
@ 1 2 +VCCPGPPA
@ CC144 CC151 0_0603_5% RC269
0.1u_0201_10V6K 0.1u_0201_10V6K 2 1
2 2 1 2 RC270 0_0603_5%
1
0_0603_5% RC3028
CC145 @
?
SKYLAKE_ULX
UC1P 0.1u_0201_10V6K
2
+1.0VALW 1.0V 599mA +VCCPRIM_1P0 AH18 AT1 +VCCPGPPA 3.3V 20mA
+VCCPRIM_1P0 AH19 VCCPRIM_1P0_01 VCCPGPPA_02 AU2
AK18 VCCPRIM_1P0_02 VCCPGPPA_01 AV1 +VCCPGPPB
VCCPRIM_1P0_03 VCCPGPPB_02
+VCCPGPPB 3.3V 4mA
2 1 AL18 AW2
VCCPRIM_1P0_04 VCCPGPPB_01 AH1
D
RC268 0_0603_5% 1 1 1 VCCPGPPC_02
+VCCPGPPC 3.3V 6mA 2 1
D
@ 1.1A +CPU_VCCPRIM AE18 AJ2 1 RC295 0_0603_5%
AE19 VCCPRIM_CORE_01 VCCPGPPC_01 AF1
CC141 CC169 CC170
VCCPRIM_CORE_02 VCCPGPPD_02
+VCCPGPPD 3.3V 8mA
0.1u_0201_10V6K 0.1u_0201_10V6K 0.1u_0201_10V6K AF18 AG2 CC149 @
2 2 2 AF19 VCCPRIM_CORE_03 VCCPGPPD_01 AA2
VCCPRIM_CORE_04 VCCPGPPE_02
+VCCPGPPE 3.3V 6mA 0.1u_0201_10V6K
2
AR16 AB1
AT16 VCCPRIM_CORE_05 VCCPGPPE_01 AN2
VCCPRIM_CORE_06 VCCPGPPF_02
+VCCPGPPF 1.8V 161mA
+VCCMPHYAON_1P0 AP1
+DCPDSW_1P0 VCCPGPPF_01 +VCCPGPPC
de-coupling AL2
DCPDSW_1P0_01 VCCPGPPG_02
AN15 +VCCPGPPG 3.3V 41mA
2 1 AM1 AP13
RC271 0_0603_5% CD@ DCPDSW_1P0_02 VCCPGPPG_01 2 1
1 1
1.0V 22mA +VCCMPHYAON_1P0 V1 AC2 +VCCPRIM_3P3 1 RC278 0_0603_5%
CC158 CC173 W2 VCCMPHYAON_1P0_01 VCCPRIM_3P3_04 AD1
VCCMPHYAON_1P0_02 VCCPRIM_3P3_03 CC150 @
0.1u_0201_10V6K 0.1u_0201_10V6K
2 2 1.0V 836mA +VCCMPHYGT_1P0_R T1 AA15 +VCCPRIM_1P0 0.1u_0201_10V6K
T15 VCCMPHYGT_1P0_01 VCCPRIM_1P0_10 AA16 2
T16 VCCMPHYGT_1P0_02 VCCPRIM_1P0_09
+VCCAPLL_1P0 U2 VCCMPHYGT_1P0_03 AE15
LC33 VCCMPHYGT_1P0_04 VCCATS_02
+VCCATS 1.8V 6mA
AE16 +VCCPGPPD
1 2 +VCCAMPHYPLL_1P0 VCCATS_01
1.0V 88mA V15
VCCAMPHYPLL_1P0_01
BLM15GG471SN1D_2P 1 1 V16 AK19 +VCCRTCPRIM_3P3 3.3V 1mA 2 1
RC273 @ VCCAMPHYPLL_1P0_02 VCCRTCPRIM_3P3_02 AL19 RC279 0_0603_5%
VCCRTCPRIM_3P3_01 1
1 2 0_0402_5% CC198 CC177 1.0V 26mA +VCCAPLL_1P0 AA18
22U_0402_4V6-M AA19 VCCAPLL_1P0_01 AR19
2 2
0.1u_0201_10V6K VCCAPLL_1P0_02 VCCRTC_02
VCCRTC 3.0V 1mA CC152 @
@ AT19 0.1u_0201_10V6K
+VCCPRIM_1P0 AH13 VCCRTC_01 2
AH15 VCCPRIM_1P0_05 AT18
VCCPRIM_1P0_06 DCPRTC_02
+DCPRTC RTC de-coupling
+VCCCLK1 AV18
+VCCDSW_3P3 DCPRTC_01 +VCCPGPPE
3.3V 71mA AL15
VCCDSW_3P3_01
2 1 AM13 V18 +VCCCLK1 1.0V 35mA
RC286 0_0603_5% VCCDSW_3P3_02 VCCCLK1_02 Y18 2 1
1 VCCCLK1_01
3.3V 68mA +VCCHDA AT23
VCCHDA_01 1 RC280 0_0603_5%
@ CC168 +3V_SPI AV22 V19 +VCCCLK2 1.0V 29mA
VCCHDA_02 VCCCLK2_02 Y19 CC155 @
0.1u_0201_10V6K VCCCLK2_01
2 AT15 0.1u_0201_10V6K
VCCSPI_01 2

0.1u_0201_10V6K
1 3.3V 11mA AV15
VCCSPI_02 VCCCLK3_02
V23 +VCCCLK3 1.0V 24mA
CC1258
Y23
+VCCSRAM_1P0 AA21 VCCCLK3_01
+VCCCLK2 VCCSRAM_1P0_01 +VCCPGPPG
C
LC36 2
1.0V 565mA AA23
VCCSRAM_1P0_02 VCCCLK4_02
V21 +VCCCLK4 1.0V 33mA C
@ AK23 Y21
1 2 AL23 VCCSRAM_1P0_03 VCCCLK4_01 2 1
AN23 VCCSRAM_1P0_04 R21
BLM15PX121SN1D_2P 1 1 VCCSRAM_1P0_05 VCCCLK5_02
+VCCCLK5 1.0V 4mA 1 RC282 0_0603_5%
@ @ AR23 R23
RC274 CC194 CC185 VCCSRAM_1P0_06 VCCCLK5_01 CC157 @
1 2 0_0402_5% 22U_0402_4V6-M 0.1u_0201_10V6K 3.3V 75mA +VCCPRIM_3P3 AH21 R19 +VCCCLK6 0.1u_0201_10V6K
2 2 AK21 VCCPRIM_3P3_01 VCCCLK6_02 T19 2
VCCPRIM_3P3_02 VCCCLK6_01
1.0V 10mA
+VCCPRIM_1P0 AR21 PCH POWER BA13
+VCCCLK3 VCCPRIM_1P0_07 GPP_B0/CORE_VID0 VID0 34 +VCCPRIM_3P3
AT21 BB12
VCCPRIM_1P0_08 GPP_B1/CORE_VID1 VID1 34
2 1 1.0V 33mA +VCCAPLLEBB_1P0 R15 2 1
RC288 0_0603_5% R16 VCCAPLLEBB_1P0_01 +CPU_VCCPRIM RC283 0_0603_5%
1 VCCAPLLEBB_1P0_02 1 1
@ @
16 OF 20
CC186 SKYLAKE-Y_FCBGA1515 CC183 CC160 @
0.1u_0201_10V6K REV = 1 ? 0.1u_0201_10V6K 0.1u_0201_10V6K
2 RC3025 2 2
@
1 2 0_0402_5%
CPU_VCCPRIM_SENSE 34
+VCCCLK4 RC3024 +VCCRTCPRIM_3P3
LC35
@ 1 2 0_0402_5%
1 2 CPU_VSSPRIM_SENSE 34 2 1
BLM15PX121SN1D_2P 1 1 1 1 RC285 0_0603_5%
RC287 @
1 2 0_0402_5% CC193 CC187 CC1176 CC184
22U_0402_4V6-M @ 0.1u_0201_10V6K 1U_0201_6.3V6-K 0.1u_0201_10V6K
2 2 2 2

+VCCCLK5 +VCCHDA @
LC34
@ RC292
1 2 1 2 0_0402_5%
BLM15PX121SN1D_2P 1 1 1
RC289 @
LC37
1 2 0_0402_5% CC192 CC188 CC159
22U_0402_4V6-M@ 0.1u_0201_10V6K 0.1u_0201_10V6K 1 2
2 2 2 BLM15GG471SN1D_2P
B B

+VCCDSW_3P3
+VCCCLK6 +1.0VALW +VCCMPHYGT_1P0
AON7408L_DFN8-5 2 1
2 1 QC16 1 RC293 0_0603_5%
RC291 0_0603_5% 1
@ REV@ CC190
CC189 1 0.1u_0201_10V6K +1.8VALW
5 S1 2 2
0.1u_0201_10V6K D S2
2 3
1 S3
CC231
G

0.1U_0402_16V4Z @ +VCCATS
4

+VCCMPHYGT_1P0 B+ 2 2 1
+VCCMPHYGT_1P0_R RC99
1 RC284 0_0603_5%
1 2

1
2 1 CC1177
RC272 0_0603_5% 1 1 1 @ RC101 1U_0201_6.3V6-K
10K_0402_5%
1
@ @ 470_0603_5% 2
1
CC175 CC176 CC180 6 REV@ R3027
22U_0402_4V6-M 1U_0201_6.3V6-K 0.1u_0201_10V6K +5VALW QC7A CC232 62K_0402_5% @

2
2 2 2 0.01U_0402_25V7K
RC96 2 +VCCPGPPF
3
2

1 2PCH_EXTPWR_GATE 2 @ QC172B
2 1
+VCCAMPHYPLL_1P0 @ RC281 0_0603_5%
LC32 47K_0402_5% 1
@ 3 AO5804EL_SC89-6 PCH_EXTPWR_GATE 5 @ @
1 2 QC7B 1 CC156
BLM15PX121SN1D_2P 1 1 0.1u_0201_10V6K
RC290 @ @ AO5804EL_SC89-6 2
1 2 0_0402_5% CC191 CC178 PCH_EXTPWR_GATE#5 4
22U_0402_4V6-M@ 8 PCH_EXTPWR_GATE#
0.1u_0201_10V6K AO5804EL_SC89-6
2 2 VCCRTC +DCPDSW_1P0 +DCPRTC

4
+VCCSRAM_1P0

0.1u_0201_10V6K

1U_0201_6.3V6-K

1U_0201_6.3V6-K

0.1u_0201_10V6K
1 1

CC1180

CC153
A 1 1 A

CC154

CC1181
2 1
RC276 0_0603_5% 1 PCH will drive EXT_PWR_GATE# low when all the high speed I/O controllers (xHCI, 2 2
@ CC181
SATA and PCIe*) are idle or have no devices attached. 2 2
0.1u_0201_10V6K
2

+VCCAPLLEBB_1P0
Security Classification LC Future Center Secret Data Title
2 1
RC277 0_0603_5% 1 Issued Date 2014/11/15 Deciphered Date 2013/08/05 MCP (Power2)
CC182
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
0.1u_0201_10V6K AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
2 C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Miix4
Date: Monday, August 17, 2015 Sheet 13 of 37
5 4 3 2 1
 5 4 3 2 1

? ?
SKYLAKE_ULX ?
UC1Q UC1R SKYLAKE_ULX UC1S SKYLAKE_ULX

A14 K23 BH20 AR50 AF33 R46

AA36 VSS_01 VSS_140 K33 BH32 VSS_141 VSS_278 AT27 AF58 VSS_279 VSS_414 R6
AA47 VSS_02 VSS_139 K43 BH42 VSS_142 VSS_277 AU59 AH16 VSS_280 VSS_413 T23
AA57 VSS_03 VSS_138 K53 BH52 VSS_143 VSS_276 AV24 AH33 VSS_281 VSS_412 T56
AC15 VSS_04 VSS_137 L61 BJ47 VSS_144 VSS_275 AW21 AH46 VSS_282 VSS_411 V13
AC27 VSS_05 VSS_136 N20 BL1 VSS_145 VSS_274 AY26 AH54 VSS_283 VSS_410 V36
AE10 VSS_06 VSS_135 R10 BL47 VSS_146 VSS_273 AY36 AK15 VSS_284 VSS_409 V47
AE43 VSS_07 VSS_134 R24 BM18 VSS_147 VSS_272 AY46 AK33 VSS_285 VSS_408 Y11
D
AE50 VSS_08 VSS_133 R40 BN6 VSS_148 VSS_271 BA1 AK7 VSS_286 VSS_407 Y27 D
AF16 VSS_09 VSS_132 R49 BP38 VSS_149 VSS_270 BA58 AL27 VSS_287 VSS_406 Y5
AF40 VSS_10 VSS_131 T13 BP60 VSS_150 VSS_269 BB22 AL43 VSS_288 VSS_405 BB26
AF62 VSS_11 VSS_130 T33 E16 VSS_151 VSS_268 BB32 AL50 VSS_289 VSS_404 BB36
AH24 VSS_12 VSS_129 T60 E26 VSS_152 VSS_267 BB42 AM64 VSS_290 VSS_403 BB46
AH40 VSS_13 VSS_128 V27 E36 VSS_153 VSS_266 BB52 AN24 VSS_291 VSS_402 BB59
AH49 VSS_14 VSS_127 V43 E46 VSS_154 VSS_265 BC47 AN59 VSS_292 VSS_401 BD38
AK1 VSS_15 VSS_126 V50 E56 VSS_155 VSS_264 BE12 AR15 VSS_293 VSS_400 BE31
AK24 VSS_16 VSS_125 Y15 J3 VSS_156 VSS_263 BE47 AR33 VSS_294 VSS_399 BF38
AK40 VSS_17 VSS_124 Y33 K15 VSS_157 VSS_262 BG12 AR44 VSS_295 VSS_398 BG17
AL16 VSS_18 VSS_123 Y9 K25 VSS_158 VSS_261 BG4 AR51 VSS_296 VSS_397 BG63
AL33 VSS_19 VSS_122 AA24 K35 VSS_159 VSS_260 BH22 AT54 VSS_297 VSS_396 BH26
AL46 VSS_20 VSS_121 AA40 K45 VSS_160 VSS_259 BH34 AU61 VSS_298 VSS_395 BH38
AL53 VSS_21 VSS_120 AA49 K55 VSS_161 VSS_258 BH44 AV52 VSS_299 VSS_394 BH48
AN18 VSS_22 VSS_119 AA59 M3 VSS_162 VSS_257 BH54 AW23 VSS_300 VSS_393 BH59
AN33 VSS_23 VSS_118 AC16 N22 VSS_163 VSS_256 BJ62 AY28 VSS_301 VSS_392 BK38
AP64 VSS_24 VSS_117 AC33 R30 VSS_164 VSS_255 BL29 AY38 VSS_302 VSS_391 BL33
AR2 VSS_25 VSS_116 AE2 R43 VSS_165 VSS_254 BL8 AY48 VSS_303 VSS_390 BM14
AR4 VSS_26 VSS_115 AE44 R50 VSS_166 VSS_253 BM20 BA11 VSS_304 VSS_389 BN29
AR47 VSS_27 VSS_114 AE51 T18 VSS_167 VSS_252 BP22 BA64 VSS_305 VSS_388 BP30
AR6 VSS_28 VSS_113 AF21 T36 VSS_168 VSS_251 BP44 BB24 VSS_306 VSS_387 BP52
AU55 VSS_29 VSS_112 AF54 T62 VSS_169 VSS_250 D6 BB34 VSS_307 VSS_386 C40
AV16 VSS_30 VSS_111 AF64 V30 VSS_170 VSS_249 E18 BB44 VSS_308 VSS_385 D8
AW17 VSS_31 VSS_110 AH27 V44 VSS_171 VSS_248 E28 BB54 VSS_309 VSS_384 E22
AY16 VSS_32 VSS_109 AH43 V51 VSS_172 VSS_247 E38 BD20 VSS_310 VSS_383 E32
AY32 VSS_33 VSS_108 AH50 Y16 VSS_173 VSS_246 E48 BE29 VSS_311 VSS_382 E42
AY42 VSS_34 VSS_107 AK11 Y36 VSS_174 VSS_245 E59 BF20 VSS_312 VSS_381 E52
AY52 VSS_35 VSS_106 AK27 Y7 VSS_175 VSS_244 J5 BG15 VSS_313 VSS_380 G14
BA5 VSS_36 VSS_105 AK5 AA27 VSS_176 VSS_243 K17 BG6 VSS_314 VSS_379 J7
BA9 VSS_37 VSS_104 AL21 AA43 VSS_177 VSS_242 K27 BH24 VSS_315 VSS_378 K21
BB28 VSS_38 VSS_103 AL36 AA50 VSS_178 VSS_241 K37 BH36 VSS_316 VSS_377 K31
BB38 VSS_39 VSS_102 AL47 AA61 VSS_179 VSS_240 K47 BH46 VSS_317 VSS_376 K41
BB48 VSS_40 VSS_101 AL59 AC18 VSS_180 VSS_239 L14 BH56 VSS_318 VSS_375 K51
BC17 VSS_41 VSS_100 AN19 AC36 VSS_181 VSS_238 N14 BK20 VSS_319 VSS_374 L59
BD56 VSS_42 VSS_99 AN36 AE21 VSS_182 VSS_237 N24 BL31 VSS_320 VSS_373 N18
BE33 VSS_43 VSS_98 AR10 AE46 VSS_183 VSS_236 R33 BM11 VSS_321 VSS_372 P54
BF56 VSS_44 VSS_97 AR27 AE8 VSS_184 VSS_235 R44 BM38 VSS_322 VSS_371 R2
BG2 VSS_45 VSS_96 AR40 AF23 VSS_185 VSS_234 R55 BP28 VSS_323 VSS_370 R4
C C
BG8 VSS_46 VSS_95 AR49 AF56 VSS_186 VSS_233 T21 BP46 VSS_324 VSS_369 R47
BH28 VSS_47 VSS_94 AR8 AG59 VSS_187 VSS_232 T40 C14 VSS_325 VSS_368 R8
BH40 VSS_48 VSS_93 AU57 AH30 VSS_188 VSS_231 T64 D62 VSS_326 VSS_367 T24
BH50 VSS_49 VSS_92 AV20 AH44 VSS_189 VSS_230 V33 E20 VSS_327 VSS_366 T58
BJ29 VSS_50 VSS_91 AW19 AH51 VSS_190 VSS_229 V46 E30 VSS_328 VSS_365 Y3
BK56 VSS_51 VSS_90 AY24 AK13 VSS_191 VSS_228 Y1 E40 VSS_329 VSS_364 AA33
BL35 VSS_52 VSS_89 AY34 AK3 VSS_192 VSS_227 Y24 E50 VSS_330 VSS_363 AA46
BM16 VSS_53 VSS_88 AY44 AK54 VSS_193 VSS_226 Y40 F62 VSS_331 VSS_362 AA55
BP36 VSS_54 VSS_87 BA53 AL24 VSS_194 VSS_225 AA30 J62 VSS_332 VSS_361 AB13
BP54 VSS_55 VSS_86 BB20 AL40 VSS_195 VSS_224 AA44 K19 VSS_333 VSS_360 AC21
D10 VSS_56 VSS_85 BB30 AL49 VSS_196 VSS_223 AA51 K29 VSS_334 VSS_359 AD13
E14 VSS_57 VSS_84 BB40 AM54 VSS_197 VSS_222 AA63 K39 VSS_335 VSS_358 AE4
E24 VSS_58 VSS_83 BB50 AN21 VSS_198 VSS_221 AC19 K49 VSS_336 VSS_357 AE49
E34 VSS_59 VSS_82 BC29 AN40 VSS_199 VSS_220 AC40 L57 VSS_337 VSS_356 AF15
E44 VSS_60 VSS_81 BD63 AR12 VSS_200 VSS_219 AE30 N16 VSS_338 VSS_355 AF36
E54 VSS_61 VSS_80 BE35 AR30 VSS_201 VSS_218 AE47 N26 VSS_339 VSS_354 AF60
J14 VSS_62 VSS_79 BF59 AR43 VSS_202 VSS_217 AF13 R18 VSS_340 VSS_353 AH23
J9 VSS_63 VSS_78 BG29 AP54 VSS_203 VSS_216 AU53 R36 VSS_341 VSS_352 BP1
AH47 VSS_64 VSS_77 AL30 AR18 VSS_204 VSS_215 AU63 AY40 VSS_342 VSS_351 A5
AJ59 VSS_65 VSS_76 AL44 AR36 VSS_205 VSS_214 AV54 V49 VSS_343 VSS_350 D1
AK16 VSS_66 VSS_75 AL51 AR46 VSS_206 VSS_213 AW25 Y13 VSS_344 VSS_349
AK36 VSS_67 VSS_74 AN16 AR59 VSS_207 VSS_212 AY30 AH36 VSS_345 BP62
AK9 VSS_68 VSS_73 AN27 BA3 VSS_208 VSS_211 AY50 V40 VSS_346 VSS_348
V24 VSS_69 VSS_72 BA7 VSS_209 VSS_210 VSS_347
GND 3 OF 3
VSS_70 VSS_71
GND 1 OF 3 GND 2 OF 3
19 OF 20
SKYLAKE-Y_FCBGA1515
17 OF 20 18 OF 20 REV = 1 ?
SKYLAKE-Y_FCBGA1515 SKYLAKE-Y_FCBGA1515 @
REV = 1 ? REV = 1 ?
@ @

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/11/15 Deciphered Date 2013/08/05 MCP (VSS)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Miix4
Date: Monday, August 17, 2015 Sheet 14 of 37
5 4 3 2 1
 5 4 3 2 1

UD1B +DDR_1.8V +DDR_0.6VS

UD1A
DDRA_DQS#[0..7] B2 A3
DDRA_DQS#[0..7] DDRA_DQ0 VSS1 VDD1_1
L8 P9 B5 A4
DDRA_DQS[0..7] DM0 DQ0 VSS2 VDD1_2

1U_0201_6.3V6-K

1U_0201_6.3V6-K

1U_0201_6.3V6-K

1U_0201_6.3V6-K
G8 N9 DDRA_DQ5 C5 A5
6 DDRA_DQS[0..7] DM1 DQ1 VSS3 VDD1_3

0.1U_0201_6.3V6-K
P8 N10 DDRA_DQ1 E4 A6
DM2 DQ2 VSS4 VDD1_4

22U_0402_4V6-M
DDRA_DQ[0..31] D8 N11 DDRA_DQ2 E5 A10
6 DDRA_DQ[0..31] DM3 DQ3 VSS5 VDD1_5 1 1 1 1 1 1

CD237

CD187

CD186

CD185

CD184

CD165
M8 DDRA_DQ6 F5 U3
DDRA_DQ[32..63] DQ4 M9 DDRA_DQ7 H2 VSS6 VDD1_6 U5 EMC_NS@
6 DDRA_DQ[32..63] DDRA_CAA0 DQ5 DDRA_DQ4 VSS7 VDD1_7
R2 M10 J12 U4
6 DDRA_CAA0 DDRA_CAA1 CA0 DQ6 DDRA_DQ3 VSS8 VDD1_8 2 2 2 2 2 2
P2 M11 K2 U6
6 DDRA_CAA1 DDRA_CAA2 CA1 DQ7 DDRA_DQ14 VSS9 VDD1_9
N2 F11 L6 U10 +DDR_1.2V
6 DDRA_CAA2 DDRA_CAA3 CA2 DQ8 DDRA_DQ12 VSS10 VDD1_10
N3 F10 M5
6 DDRA_CAA3 DDRA_CAA4 CA3 DQ9 DDRA_DQ8 VSS11
M3 F9 N4 A8
6 DDRA_CAA4 DDRA_CAA5 CA4 DQ10 DDRA_DQ9 VSS12 VDD2_1
F3 F8 N5 A9
6 DDRA_CAA5 DDRA_CAA6 CA5 DQ11 DDRA_DQ11 VSS13 VDD2_2
E3 E11 R4 D4
6 DDRA_CAA6 DDRA_CAA7 CA6 DQ12 DDRA_DQ15 VSS14 VDD2_3
E2 E10 R5 D5 +DDR_1.8V
6 DDRA_CAA7 DDRA_CAA8 CA7 DQ13 DDRA_DQ13 VSS15 VDD2_4
D2 E9 T2 D6
D 6 DDRA_CAA8 DDRA_CAA9 CA8 DQ14 DDRA_DQ10 VSS16 VDD2_5 D
C2 D9 T3 G5
6 DDRA_CAA9 CA9 DQ15 VSS17 VDD2_6

10U_0402_6.3V6M

10U_0402_6.3V6M

1U_0201_6.3V6-K

1U_0201_6.3V6-K

1U_0201_6.3V6-K
T8 DDRA_DQ24 T4 H5
+DDR_0.6VS DQ16 VSS18 VDD2_7

10U_0402_6.3V6-M
K3 T9 DDRA_DQ29 T5 H6
6 DDRA_CKE0 CKE0 DQ17 VSS19 VDD2_8

0.1U_0201_6.3V6-K
K4 T10 DDRA_DQ31 H12 1 1 1 1 1 1
6 DDRA_CKE1 CKE1 DQ18 VDD2_9

CD167

CD168

CD169

CD159

CD160

CD172
RPD1 T11 DDRA_DQ30 J5 1
DQ19 VDD2_10

CD238
1 4 DDRA_CAA0 J3 R8 DDRA_DQ25 B6 J6
DDRA_CAA1 6 DDRA_CLK0 CK DQ20 DDRA_DQ28 VSSQ1 VDD2_11
2 3 J2 R9 B12 K5 EMC_NS@
6 DDRA_CLK0# CK# DQ21 DDRA_DQ26 VSSQ2 VDD2_12 2 2 2 2 2 2
R10 C6 K6
68_0404_4P2R_1% B3 DQ22 R11 DDRA_DQ27 D12 VSSQ3 VDD2_13 K12 2 @ @
B4 ZQ0 DQ23 C11 DDRA_DQ17 E6 VSSQ4 VDD2_14 L5
ZQ1 DQ24 C10 DDRA_DQ16 F6 VSSQ5 VDD2_15 P4
RPD2
1 4 DDRA_CAA2 U12 DQ25 C9 DDRA_DQ18 F12 VSSQ6 VDD2_16 P5
2 3 DDRA_CAA3 U1 U12 DQ26 C8 DDRA_DQ22 G6 VSSQ7 VDD2_17 P6
DNU_1 DQ27 VSSQ8 VDD2_18

1
243_0402_1%

243_0402_1%
T1 B11 DDRA_DQ20 G9 U9
DNU_2 DQ28 VSSQ9 VDD2_19

RD100
RD1
68_0404_4P2R_1% B1 B10 DDRA_DQ21 H10 U8 +DDR_1.2V
A12 DNU_3 DQ29 B9 DDRA_DQ19 K10 VSSQ10 VDD2_20 +DDR_1.2V
A1 DNU_4 DQ30 B8 DDRA_DQ23 L9 VSSQ11 F2
RPD3
1 4 DDRA_CAA4 A2 DNU_5 DQ31 M6 VSSQ12 VDDCA_1 G2

2
2 3 DDRA_CAA8 A13 DNU_6 L10 DDRA_DQS0 M12 VSSQ13 VDDCA_2 H3
B13 DNU_7 DQS0 G10 DDRA_DQS1 N6 VSSQ14 VDDCA_3 L2 +DDR_1.2V
68_0404_4P2R_1% T13 DNU_8 DQS1 P10 DDRA_DQS3 P12 VSSQ15 VDDCA_4 M2
DNU_9 DQS2 VSSQ16 VDDCA_5

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

1U_0201_6.3V6-K

1U_0201_6.3V6-K

1U_0201_6.3V6-K

1U_0201_6.3V6-K

1U_0201_6.3V6-K
U2 D10 DDRA_DQS2 R6
DNU_10 DQS3 VSSQ17

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K
RPD4 U13 T6 A11
1 4 DDRA_CAA7 DNU_11 L11 DDRA_DQS#0 T12 VSSQ18 VDDQ_1 C12
DQS0# VSSQ19 VDDQ_2 1 1 1 1 1 1 1 1 1 1 1 1

CD269

CD270

CD239

CD183

CD162

CD161

CD182

CD155

CD156

CD157

CD158

CD181
2 3 DDRA_CAA6 DDRA_CS0# L3 G11 DDRA_DQS#1 E8
6 DDRA_CS0# DDRA_CS1# CS0# DQS1# DDRA_DQS#3 VDDQ_3
L4 P11 C3 E12
6 DDRA_CS1# CS1# DQS2# DDRA_DQS#2 VSSCA1 VDDQ_4
68_0404_4P2R_1% D11 D3 G12
DDRA_ODT0 J8 DQS3# F4 VSSCA2 VDDQ_5 H8 2 2 2 2 2 2 2 2 2 2 2 @2
6 DDRA_ODT0 ODT VSSCA3 VDDQ_6
RPD5 G3 H9
1 4 DDRA_CAA9 C4 G4 VSSCA4 VDDQ_7 H11
2 3 DDRA_CAA5 K9 NC_1 J4 VSSCA5 VDDQ_8 J9 CD@
R3 NC_2 M4 VSSCA6 VDDQ_9 J10
68_0404_4P2R_1% NC_3 P3 VSSCA7 VDDQ_10 K8
VSSCA8 VDDQ_11 K11 +DDR_1.2V
RPD6 VDDQ_12 L12
2 3 DDRA_CKE0 K4E8E304EB-EGCE_FBGA178 VDDQ_13 N8
VDDQ_14 1
1 4 DDRA_CKE1 N12
VDDQ_15

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K
C @ R12 CD209 C
80.6_0404_4P2R_1% VDDQ_16 U11 0.047U_0402_16V7K
VDDQ_17 2 1 1 1 1 1 1 1 1 1 1 1 1

CD262

CD263

CD265

CD264

CD266

CD243

CD244

CD245

CD246

CD247

CD248

CD249
RPD7 +VREF_CA
H4
2 3 DDRA_CS0# VREF_CA J11 +VREF_DQA
1 4 DDRA_CS1# VREF_DQ 2 2 2 2 2 2 2 2 2 2 2 2
1
80.6_0404_4P2R_1% K4E8E304EB-EGCE_FBGA178 CD210
0.047U_0402_16V7K
80.6_0402_1% 1 2 RD129 DDRA_ODT0 2
@

+DDR_0.6VS +DDR_1.8V +DDR_1.2V

UD2B
37.4_0402_1% 2 1 RD130 DDRA_CLK0 UD2A
B2 A3
VSS1 VDD1_1

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6-M

1U_0201_6.3V6-K

1U_0201_6.3V6-K
37.4_0402_1% 2 1 RD131 DDRA_CLK0# L8 P9 DDRA_DQ33 B5 A4
DM0 DQ0 VSS2 VDD1_2

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K
G8 N9 DDRA_DQ36 C5 A5
+DDR_0.6VS P8 DM1 DQ1 N10 DDRA_DQ38 E4 VSS3 VDD1_3 A6
DM2 DQ2 VSS4 VDD1_4 1 1 1 1 1 1 1 1 1 1 1

C1955
CD240

CD150

CD149

CD179

CD174

CD164

CD163

CD153

CD151

CD154
D8 N11 DDRA_DQ32 E5 A10
DM3 DQ3 M8 DDRA_DQ39 F5 VSS5 VDD1_5 U3
RPD8
1 4 DDRA_CAB0 DQ4 M9 DDRA_DQ34 H2 VSS6 VDD1_6 U5 +DDR_1.2V
2 3 DDRA_CAB1 DDRA_CAB0 R2 DQ5 M10 DDRA_DQ35 J12 VSS7 VDD1_7 U4 2 2 2 2 2@ 2 2 2 2 2 2
6 DDRA_CAB0 DDRA_CAB1 CA0 DQ6 DDRA_DQ37 VSS8 VDD1_8
P2 M11 K2 U6
6 DDRA_CAB1 DDRA_CAB2 CA1 DQ7 DDRA_DQ45 VSS9 VDD1_9
68_0404_4P2R_1% N2 F11 L6 U10
6 DDRA_CAB2 DDRA_CAB3 CA2 DQ8 DDRA_DQ43 VSS10 VDD1_10
N3 F10 M5 CD@
6 DDRA_CAB3 DDRA_CAB4 CA3 DQ9 DDRA_DQ44 VSS11
RPD9 M3 F9 N4 A8
DDRA_CAB2 6 DDRA_CAB4 DDRA_CAB5 CA4 DQ10 DDRA_DQ41 VSS12 VDD2_1
1 4 F3 F8 N5 A9 CD@
DDRA_CAB3 6 DDRA_CAB5 DDRA_CAB6 CA5 DQ11 DDRA_DQ42 VSS13 VDD2_2
2 3 E3 E11 R4 D4
6 DDRA_CAB6 DDRA_CAB7 CA6 DQ12 DDRA_DQ46 VSS14 VDD2_3
E2 E10 R5 D5
6 DDRA_CAB7 DDRA_CAB8 CA7 DQ13 DDRA_DQ40 VSS15 VDD2_4
68_0404_4P2R_1% D2 E9 T2 D6
6 DDRA_CAB8 DDRA_CAB9 CA8 DQ14 DDRA_DQ47 VSS16 VDD2_5
C2 D9 T3 G5
6 DDRA_CAB9 CA9 DQ15 DDRA_DQ55 VSS17 VDD2_6
RPD10 T8 T4 H5
1 4 DDRA_CAB4 K3 DQ16 T9 DDRA_DQ49 T5 VSS18 VDD2_7 H6 +DDR_1.2V
DDRA_CAB5 6 DDRA_CKE2 CKE0 DQ17 DDRA_DQ48 VSS19 VDD2_8
2 3 K4 T10 H12
6 DDRA_CKE3 CKE1 DQ18 DDRA_DQ50 VDD2_9
T11 J5
DQ19 VDD2_10

1
B DDRA_DQ54 B
68_0404_4P2R_1% J3 R8 B6 J6
6 DDRA_CLK1 CK DQ20 DDRA_DQ53 VSSQ1 VDD2_11
J2 R9 B12 K5 RD173
6 DDRA_CLK1# CK# DQ21 DDRA_DQ51 VSSQ2 VDD2_12
RPD11 R10 C6 K6 8.2K_0402_1%
1 4 DDRA_CAB6 B3 DQ22 R11 DDRA_DQ52 D12 VSSQ3 VDD2_13 K12
2 3 DDRA_CAB7 B4 ZQ0 DQ23 C11 DDRA_DQ58 E6 VSSQ4 VDD2_14 L5 RD172

2
ZQ1 DQ24 C10 DDRA_DQ60 F6 VSSQ5 VDD2_15 P4 10_0402_1%
68_0404_4P2R_1% U12 DQ25 C9 DDRA_DQ56 F12 VSSQ6 VDD2_16 P5 1 2 +VREF_DQA
U12 DQ26 DDRA_DQ57 VSSQ7 VDD2_17 6 DDR_SA_VREFDQ
U1 C8 G6 P6 +DDR_1.2V
DNU_1 DQ27 VSSQ8 VDD2_18
1

1
243_0402_1%

243_0402_1%

RPD12 T1 B11 DDRA_DQ62 G9 U9 Trace width:20 mils

DNU_2 DQ28 VSSQ9 VDD2_19
RD101

RD102

1 4 DDRA_CAB8 B1 B10 DDRA_DQ63 H10 U8 1

2 3 DDRA_CAB9 A12 DNU_3 DQ29 B9 DDRA_DQ59 K10 VSSQ10 VDD2_20 CD207
Space:20mils
A1 DNU_4 DQ30 B8 DDRA_DQ61 L9 VSSQ11 F2 0.022U_0402_16V7-K
DNU_5 DQ31 VSSQ12 VDDCA_1

1
68_0404_4P2R_1% A2 M6 G2
2

A13 DNU_6 L10 DDRA_DQS4 M12 VSSQ13 VDDCA_2 H3 +DDR_1.2V 2 RD174

RPD13 DNU_7 DQS0 VSSQ14 VDDCA_3

1
B13 G10 DDRA_DQS5 N6 L2 8.2K_0402_1%
2 3 DDRA_CKE2 T13 DNU_8 DQS1 P10 DDRA_DQS6 P12 VSSQ15 VDDCA_4 M2
1 4 DDRA_CKE3 U2 DNU_9 DQS2 D10 DDRA_DQS7 R6 VSSQ16 VDDCA_5 RD171

2
U13 DNU_10 DQS3 T6 VSSQ17 A11 24.9_0402_1%
80.6_0404_4P2R_1% DNU_11 L11 DDRA_DQS#4 T12 VSSQ18 VDDQ_1 C12

2
DDRA_CS0# L3 DQS0# G11 DDRA_DQS#5 VSSQ19 VDDQ_2 E8
DDRA_CS1# L4 CS0# DQS1# P11 DDRA_DQS#6 C3 VDDQ_3 E12
CS1# DQS2# D11 DDRA_DQS#7 D3 VSSCA1 VDDQ_4 G12
DDRA_ODT0 J8 DQS3# F4 VSSCA2 VDDQ_5 H8 +DDR_1.2V
+DDR_0.6VS ODT G3 VSSCA3 VDDQ_6 H9
C4 G4 VSSCA4 VDDQ_7 H11
NC_1 VSSCA5 VDDQ_8

1
K9 J4 J9
R3 NC_2 M4 VSSCA6 VDDQ_9 J10 RD169
37.4_0402_1% 2 1 RD132 DDRA_CLK1 NC_3 P3 VSSCA7 VDDQ_10 K8 8.2K_0402_1%
VSSCA8 VDDQ_11 K11
37.4_0402_1% 2 1 RD133 DDRA_CLK1# VDDQ_12 L12
RD6

2
K4E8E304EB-EGCE_FBGA178 VDDQ_13 N8
VDDQ_14 1
N12 1 2 +VREF_CA
VDDQ_15 6 DDR_SM_VREFCA +VREF_CA 16
@ R12 CD211
VDDQ_16 U11 0.047U_0402_16V7K 5.11_0402_1%
VDDQ_17 2 Trace width:20 mils
1 Space:20mils
H4 +VREF_CA CD20
VREF_CA J11 +VREF_DQA 0.022U_0402_16V7-K
VREF_DQ

1
A 1 A
2 RD170

1
K4E8E304EB-EGCE_FBGA178 CD212 8.2K_0402_1%
0.047U_0402_16V7K
2 RD8
@

2
24.9_0402_1%

2
Security Classification LC Future Center Secret Data Title
Issued Date 2014/11/15 Deciphered Date 2013/08/05 LPDDR3-CHA
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Miix4
Date: Monday, August 17, 2015 Sheet 15 of 37
5 4 3 2 1
 5 4 3 2 1

UD3B +DDR_1.8V
DDRB_DQS#[0..7] UD3A
6 DDRB_DQS#[0..7]
B2 A3
DDRB_DQS[0..7] L8 P9 DDRB_DQ9 B5 VSS1 VDD1_1 A4 +DDR_0.6VS
6 DDRB_DQS[0..7] DM0 DQ0 DDRB_DQ15 VSS2 VDD1_2
G8 N9 C5 A5
DDRB_DQ[0..31] P8 DM1 DQ1 N10 DDRB_DQ10 E4 VSS3 VDD1_3 A6
6 DDRB_DQ[0..31] DM2 DQ2 DDRB_DQ11 VSS4 VDD1_4
D8 N11 E5 A10
DDRB_DQ[32..63] DM3 DQ3 VSS5 VDD1_5

1U_0201_6.3V6-K

1U_0201_6.3V6-K

1U_0201_6.3V6-K

1U_0201_6.3V6-K
M8 DDRB_DQ12 F5 U3
6 DDRB_DQ[32..63] DQ4 VSS6 VDD1_6

0.1U_0201_6.3V6-K
M9 DDRB_DQ13 H2 U5
DQ5 VSS7 VDD1_7

22U_0402_4V6-M
DDRB_CAA0 R2 M10 DDRB_DQ14 J12 U4 1 1 1 1 1 1
+DDR_0.6VS 6 DDRB_CAA0 CA0 DQ6 VSS8 VDD1_8

CD235

CD202

CD203

CD204

CD205

CD176
DDRB_CAA1 P2 M11 DDRB_DQ8 K2 U6
6 DDRB_CAA1 DDRB_CAA2 CA1 DQ7 DDRB_DQ7 VSS9 VDD1_9
N2 F11 L6 U10 +DDR_1.2V EMC_NS@
6 DDRB_CAA2 DDRB_CAA3 CA2 DQ8 DDRB_DQ2 VSS10 VDD1_10
RPD14 N3 F10 M5
DDRB_CAA0 6 DDRB_CAA3 DDRB_CAA4 CA3 DQ9 DDRB_DQ5 VSS11 2 2 2 2 2 2
4 1 M3 F9 N4 A8
DDRB_CAA1 6 DDRB_CAA4 DDRB_CAA5 CA4 DQ10 DDRB_DQ4 VSS12 VDD2_1
3 2 F3 F8 N5 A9
6 DDRB_CAA5 DDRB_CAA6 CA5 DQ11 DDRB_DQ3 VSS13 VDD2_2
E3 E11 R4 D4
6 DDRB_CAA6 DDRB_CAA7 CA6 DQ12 DDRB_DQ6 VSS14 VDD2_3
68_0404_4P2R_1% E2 E10 R5 D5
6 DDRB_CAA7 DDRB_CAA8 CA7 DQ13 DDRB_DQ0 VSS15 VDD2_4
D2 E9 T2 D6
D 6 DDRB_CAA8 DDRB_CAA9 CA8 DQ14 DDRB_DQ1 VSS16 VDD2_5 D
RPD16 C2 D9 T3 G5
DDRB_CAA2 6 DDRB_CAA9 CA9 DQ15 DDRB_DQ35 VSS17 VDD2_6
4 1 T8 T4 H5 +DDR_1.8V
3 2 DDRB_CAA3 K3 DQ16 T9 DDRB_DQ33 T5 VSS18 VDD2_7 H6
6 DDRB_CKE0 CKE0 DQ17 DDRB_DQ36 VSS19 VDD2_8
K4 T10 H12
6 DDRB_CKE1 CKE1 DQ18 DDRB_DQ32 VDD2_9
68_0404_4P2R_1% T11 J5
DQ19 VDD2_10

1U_0201_6.3V6-K

1U_0201_6.3V6-K

1U_0201_6.3V6-K
J3 R8 DDRB_DQ34 B6 J6
6 DDRB_CLK0 CK DQ20 VSSQ1 VDD2_11

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
0.1U_0201_6.3V6-K
RPD17 J2 R9 DDRB_DQ38 B12 K5 1 1 1 1 1 1
6 DDRB_CLK0# CK# DQ21 VSSQ2 VDD2_12

CD189

CD190

CD191

CD223

CD224

CD225
4 1 DDRB_CAA5 R10 DDRB_DQ37 C6 K6 1
DQ22 VSSQ3 VDD2_13

CD236
3 2 DDRB_CAA4 B3 R11 DDRB_DQ39 D12 K12
B4 ZQ0 DQ23 C11 DDRB_DQ43 E6 VSSQ4 VDD2_14 L5 EMC_NS@
68_0404_4P2R_1% ZQ1 DQ24 C10 DDRB_DQ45 F6 VSSQ5 VDD2_15 P4 2 2 2 2 2 2
U12 DQ25 C9 DDRB_DQ41 F12 VSSQ6 VDD2_16 P5 2
U1 U12 DQ26 C8 DDRB_DQ40 G6 VSSQ7 VDD2_17 P6
RPD18
DNU_1 DQ27 VSSQ8 VDD2_18

1
243_0402_1%

243_0402_1%
4 1 DDRB_CAA6 T1 B11 DDRB_DQ42 G9 U9 CD@
DNU_2 DQ28 VSSQ9 VDD2_19

RD134
DDRB_CAA7

RD2
3 2 B1 B10 DDRB_DQ46 H10 U8 +DDR_1.2V
A12 DNU_3 DQ29 B9 DDRB_DQ47 K10 VSSQ10 VDD2_20
68_0404_4P2R_1% A1 DNU_4 DQ30 B8 DDRB_DQ44 L9 VSSQ11 F2 +DDR_1.2V
A2 DNU_5 DQ31 M6 VSSQ12 VDDCA_1 G2

2
A13 DNU_6 L10 DDRB_DQS1 M12 VSSQ13 VDDCA_2 H3
RPD19
4 1 DDRB_CAA8 B13 DNU_7 DQS0 G10 DDRB_DQS0 N6 VSSQ14 VDDCA_3 L2 +DDR_1.2V
3 2 DDRB_CAA9 T13 DNU_8 DQS1 P10 DDRB_DQS4 P12 VSSQ15 VDDCA_4 M2
U2 DNU_9 DQS2 D10 DDRB_DQS5 R6 VSSQ16 VDDCA_5
DNU_10 DQS3 VSSQ17

10U_0402_6.3V6-M

1U_0201_6.3V6-K

1U_0201_6.3V6-K

1U_0201_6.3V6-K

1U_0201_6.3V6-K

1U_0201_6.3V6-K
68_0404_4P2R_1% U13 T6 A11
DNU_11 VSSQ18 VDDQ_1

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K
L11 DDRB_DQS#1 T12 C12
RPD15 DQS0# VSSQ19 VDDQ_2

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
L3 G11 DDRB_DQS#0 E8 1 1 1 1 1 1 1 1 1 1 1 1
6 DDRB_CS0# CS0# DQS1# VDDQ_3

CD267

CD268

CD241

CD199

CD198

CD201

CD200

CD193

CD194

CD195

CD196

CD171
2 3 DDRB_CKE0 L4 P11 DDRB_DQS#4 C3 E12
DDRB_CKE1 6 DDRB_CS1# CS1# DQS2# DDRB_DQS#5 VSSCA1 VDDQ_4
1 4 D11 D3 G12
J8 DQS3# F4 VSSCA2 VDDQ_5 H8
6 DDRB_ODT0 ODT VSSCA3 VDDQ_6 2 2 2 2 2 2 2 2 2 2 2 2
80.6_0404_4P2R_1% G3 H9
C4 G4 VSSCA4 VDDQ_7 H11
RPD20 NC_1 VSSCA5 VDDQ_8
K9 J4 J9 CD@ CD@
2 3 DDRB_CS0# R3 NC_2 M4 VSSCA6 VDDQ_9 J10
1 4 DDRB_CS1# NC_3 P3 VSSCA7 VDDQ_10 K8
VSSCA8 VDDQ_11 K11
80.6_0404_4P2R_1% VDDQ_12 L12 +DDR_1.2V
80.6_0402_1% 1 2 RD150 DDRB_ODT0 K4E8E304EB-EGCE_FBGA178 VDDQ_13 N8
VDDQ_14 1
N12
VDDQ_15 R12
C @ CD213 C
+DDR_0.6VS VDDQ_16

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K
U11 0.047U_0402_16V7K
VDDQ_17 2
1 1 1 1 1 1 1 1 1 1 1

CD260

CD261

CD258

CD259

CD257

CD251

CD253

CD252

CD254

CD255

CD256
H4 +VREF_CA
VREF_CA J11 +VREF_DQB
37.4_0402_1% 2 1 RD148 DDRB_CLK0 VREF_DQ
1 2 2 2 2 2 2 2 2 2 2 2
37.4_0402_1% 2 1 RD146 DDRB_CLK0# K4E8E304EB-EGCE_FBGA178 CD214
0.047U_0402_16V7K
2
@

+DDR_0.6VS +DDR_1.8V
+DDR_1.2V

UD4B
UD4A
B2 A3
L8 P9 DDRB_DQ18 B5 VSS1 VDD1_1 A4
RPD21
DM0 DQ0 VSS2 VDD1_2

10U_0402_6.3V6-M

1U_0201_6.3V6-K

1U_0201_6.3V6-K
4 1 DDRB_CAB0 G8 N9 DDRB_DQ17 C5 A5
DM1 DQ1 VSS3 VDD1_3

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K
3 2 DDRB_CAB3 P8 N10 DDRB_DQ16 E4 A6
DM2 DQ2 VSS4 VDD1_4

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
D8 N11 DDRB_DQ23 E5 A10 1 1 1 1 1 1 1 1 1 1 1
DM3 DQ3 VSS5 VDD1_5

CD242

CD216

CD215

CD229

CD232

CD206

CD208

CD170

CD234

CD233

CD218
68_0404_4P2R_1% M8 DDRB_DQ22 F5 U3
DQ4 M9 DDRB_DQ19 H2 VSS6 VDD1_6 U5 +DDR_1.2V
DDRB_CAB0 R2 DQ5 M10 DDRB_DQ20 J12 VSS7 VDD1_7 U4
RPD22 6 DDRB_CAB0
4 1 DDRB_CAB5 DDRB_CAB1 P2 CA0 DQ6 M11 DDRB_DQ21 K2 VSS8 VDD1_8 U6 2 2 2 2 2 2 2 2 2 2 2
DDRB_CAB4 6 DDRB_CAB1 DDRB_CAB2 CA1 DQ7 DDRB_DQ26 VSS9 VDD1_9
3 2 N2 F11 L6 U10
6 DDRB_CAB2 DDRB_CAB3 CA2 DQ8 DDRB_DQ28 VSS10 VDD1_10
N3 F10 M5 CD@
6 DDRB_CAB3 DDRB_CAB4 CA3 DQ9 DDRB_DQ29 VSS11
68_0404_4P2R_1% M3 F9 N4 A8
6 DDRB_CAB4 DDRB_CAB5 CA4 DQ10 DDRB_DQ24 VSS12 VDD2_1
F3 F8 N5 A9
6 DDRB_CAB5 DDRB_CAB6 CA5 DQ11 DDRB_DQ25 VSS13 VDD2_2
RPD23 E3 E11 R4 D4
DDRB_CAB2 6 DDRB_CAB6 DDRB_CAB7 CA6 DQ12 DDRB_DQ31 VSS14 VDD2_3
4 1 E2 E10 R5 D5
DDRB_CAB1 6 DDRB_CAB7 DDRB_CAB8 CA7 DQ13 DDRB_DQ30 VSS15 VDD2_4
3 2 D2 E9 T2 D6
6 DDRB_CAB8 DDRB_CAB9 CA8 DQ14 DDRB_DQ27 VSS16 VDD2_5
C2 D9 T3 G5
6 DDRB_CAB9 CA9 DQ15 DDRB_DQ49 VSS17 VDD2_6
68_0404_4P2R_1% T8 T4 H5
K3 DQ16 T9 DDRB_DQ48 T5 VSS18 VDD2_7 H6 +DDR_1.2V
6 DDRB_CKE2 CKE0 DQ17 DDRB_DQ53 VSS19 VDD2_8
RPD24 K4 T10 H12
DDRB_CAB7 6 DDRB_CKE3 CKE1 DQ18 DDRB_DQ52 VDD2_9
4 1 T11 J5
DQ19 VDD2_10

1
B DDRB_CAB6 DDRB_DQ51 B
3 2 J3 R8 B6 J6
6 DDRB_CLK1 CK DQ20 DDRB_DQ55 VSSQ1 VDD2_11
J2 R9 B12 K5 RD176
6 DDRB_CLK1# CK# DQ21 DDRB_DQ50 VSSQ2 VDD2_12
68_0404_4P2R_1% R10 C6 K6 8.2K_0402_1%
B3 DQ22 R11 DDRB_DQ54 D12 VSSQ3 VDD2_13 K12
B4 ZQ0 DQ23 C11 DDRB_DQ58 E6 VSSQ4 VDD2_14 L5 RD177
RPD25

2
4 1 DDRB_CAB9 ZQ1 DQ24 C10 DDRB_DQ60 F6 VSSQ5 VDD2_15 P4 10_0402_1%
3 2 DDRB_CAB8 U12 DQ25 C9 DDRB_DQ61 F12 VSSQ6 VDD2_16 P5 1 2 +VREF_DQB
U12 DQ26 DDRB_DQ56 VSSQ7 VDD2_17 6 DDR_SB_VREFDQ
U1 C8 G6 P6 +DDR_1.2V
DNU_1 DQ27 VSSQ8 VDD2_18
1

1
243_0402_1%

243_0402_1%

68_0404_4P2R_1% T1 B11 DDRB_DQ62 G9 U9

DNU_2 DQ28 VSSQ9 VDD2_19
RD142

RD140

B1 B10 DDRB_DQ63 H10 U8 1

RPD26 DNU_3 DQ29 DDRB_DQ59 VSSQ10 VDD2_20
A12 B9 K10 CD228
2 3 DDRB_CKE3 A1 DNU_4 DQ30 B8 DDRB_DQ57 L9 VSSQ11 F2 0.022U_0402_16V7-K
DNU_5 DQ31 VSSQ12 VDDCA_1

1
1 4 DDRB_CKE2 A2 M6 G2
2

A13 DNU_6 L10 DDRB_DQS2 M12 VSSQ13 VDDCA_2 H3 +DDR_1.2V 2 RD178

DNU_7 DQS0 VSSQ14 VDDCA_3

1
80.6_0404_4P2R_1% B13 G10 DDRB_DQS3 N6 L2 8.2K_0402_1%
T13 DNU_8 DQS1 P10 DDRB_DQS6 P12 VSSQ15 VDDCA_4 M2
U2 DNU_9 DQS2 D10 DDRB_DQS7 R6 VSSQ16 VDDCA_5 RD175

2
U13 DNU_10 DQS3 T6 VSSQ17 A11 24.9_0402_1%
+DDR_0.6VS DNU_11 L11 DDRB_DQS#2 T12 VSSQ18 VDDQ_1 C12

2
DDRB_CS0# L3 DQS0# G11 DDRB_DQS#3 VSSQ19 VDDQ_2 E8
DDRB_CS1# L4 CS0# DQS1# P11 DDRB_DQS#6 C3 VDDQ_3 E12
CS1# DQS2# D11 DDRB_DQS#7 D3 VSSCA1 VDDQ_4 G12
37.4_0402_1% 2 1 RD166 DDRB_CLK1 DDRB_ODT0 J8 DQS3# F4 VSSCA2 VDDQ_5 H8
ODT G3 VSSCA3 VDDQ_6 H9
37.4_0402_1% 2 1 RD154 DDRB_CLK1# C4 G4 VSSCA4 VDDQ_7 H11
K9 NC_1 J4 VSSCA5 VDDQ_8 J9
R3 NC_2 M4 VSSCA6 VDDQ_9 J10
NC_3 P3 VSSCA7 VDDQ_10 K8
VSSCA8 VDDQ_11 K11
VDDQ_12 L12
K4E8E304EB-EGCE_FBGA178 VDDQ_13 N8
VDDQ_14 1
N12
VDDQ_15 R12
@ CD230
VDDQ_16 U11 0.047U_0402_16V7K
VDDQ_17 2
H4 +VREF_CA
VREF_CA +VREF_DQB +VREF_CA 15
J11
VREF_DQ
A 1 A

K4E8E304EB-EGCE_FBGA178 CD231
0.047U_0402_16V7K
2
@

Security Classification LC Future Center Secret Data Title

Issued Date 2014/11/15 Deciphered Date 2013/08/05 LPDDR3-CHB
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Miix4
Date: Monday, August 17, 2015 Sheet 16 of 37
5 4 3 2 1
 5 4 3 2 1

+3VS
EDP Panel

2
R43
1K_0402_5% number of pixel:2160X1440
@

1
+3VS_LCDVCC_R
1 2 LCD_BKLT_CTRL
+5VALW +3VS 4 PCH_BKLT_CTRL
R185 0_0402_5% JLVDS

1
W=60mils 1
1

1
R82
100K_0402_5%

0.1u_0201_10V6K
R3034 1 C51 1 2 0.1u_0201_10V6K CPU_EDP_AUX-_C 2
4 CPU_EDP_AUX- 2

C28
33_0402_5% @ C50 1 2 0.1u_0201_10V6K CPU_EDP_AUX+_C 3
4 CPU_EDP_AUX+ 3

4.7U_0402_6.3V6M
1 4
4

C24
R5 LCD_BKLT_CTRL 5

2
100K_0402_5% 2 LCD_BKLT_EN 6 5

2
EDP_HPD_OUT 7 6
3 2 7
8
28 PANEL_DE

2
Q167B Q9 9 8
+3VS_LCDVCC 9

3
S
AO5804EL_SC89-6 R7 10
5 1 2 2
G
LP2301ALT1G_SOT23-3 +3VS_LCDVCC 11 10
220K_0402_5% 12 11
D +3VS_LCDVCC_R +3VS C42 1 2 0.1u_0201_10V6K CPU_EDP_TX0-_C 13 12
1 4 CPU_EDP_TX0-

1
D C43 1 2 0.1u_0201_10V6K CPU_EDP_TX0+_C 14 13 D
4 4 CPU_EDP_TX0+ 14
C2 15
15

2
6 .1U_0402_10V6-K 1 2 C44 1 2 0.1u_0201_10V6K CPU_EDP_TX1-_C 16
2 4 CPU_EDP_TX1- 16
0_0603_5% R2 R47 C45 1 2 0.1u_0201_10V6K CPU_EDP_TX1+_C 17
4 CPU_EDP_TX1+ 17
Q167A 1K_0402_5% 18
18

0.1u_0201_10V6K

4.7U_0402_6.3V6M
AO5804EL_SC89-6 1 1 @ C46 1 2 0.1u_0201_10V6K CPU_EDP_TX2-_C 19
4 CPU_EDP_TX2- 19

C23

C22
PCH_LCD_VDDEN 1 2 0_0402_5% 2 C47 1 2 0.1u_0201_10V6K CPU_EDP_TX2+_C 20
4 PCH_LCD_VDDEN 4 CPU_EDP_TX2+

1
21 20
R6 2 1 LCD_BKLT_EN C48 1 2 0.1u_0201_10V6K CPU_EDP_TX3-_C 22 21
25 EC_BKLT_EN 4 CPU_EDP_TX3- 22

1
2 2

R83
100K_0402_5%
R349 1K_0402_5% C49 1 2 0.1u_0201_10V6K CPU_EDP_TX3+_C 23
1 4 CPU_EDP_TX3+ 23
2 @ 1 24
4,25 PCH_BKLT_EN 24

1
R81
100K_0402_5%

0.1u_0201_10V6K
R350 1K_0402_5% 1 25
25

C29
@ 26
27 26
+LCD_VDD

2
28 27
2 29 28 31

2
30 29 GND1 32
30 GND2

ELCO_046809630310846+
ME@

B+ FPC:
1. pin to pin with EDP Panel, check the panel pin definition
2. check the HSYNC for Touch screen board

2
R235 +3VS
100K_0402_5%

2
1
2 1 LVDS_VDD_EN# R46
R237 1K_0402_5%
100K_0402_5% @

1
1 2 EDP_HPD_OUT
4 PCH_EDP_HPD
R184 0_0402_5%

1
Q17

1
DMG1012T-7_SOT523-3
PCH_LCD_VDDEN 2 R80
1 100K_0402_5%

0.1u_0201_10V6K
1

3
C25
@ C209

2
0.1U_0402_25V6
2
2

C +3VS_LCDVCC C

1
R45
100K_0402_5%
@

2
B+ Q25 +LCD_VDD CPU_EDP_AUX-_C
M A X ：8 . 7 V AO3401A_SOT23-3
M I N ：6 . 0 V CPU_EDP_AUX+_C
S

3 1 1 2
0_0603_5% R3

1
R232
G

1 1
2

100K_0402_5%
LVDS_VDD_EN# C200 C212 @
10U_0603_25V6-M 0.1U_0402_25V6

2
2 2

NOTE

1. AC 19V/DC 8.2V
2. AO5800E for VDS concern
3. R235, R237 for VGS concern
4. C200 for voltage concern

B B

Reserve for other function

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/11/15 Deciphered Date 2013/11/08 LCD
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Miix4
Date: Monday, August 17, 2015 Sheet 17 of 37
5 4 3 2 1
 5 4 3 2 1

TMDS CPU_HDMI_TX0+ CV255 1 2 0.1u_0201_10V6K HDMI_TX0+_C

DDC ESD
4 CPU_HDMI_TX0+
CPU_HDMI_TX0- CV256 1 2 0.1u_0201_10V6K HDMI_TX0-_C +3VS +3VS 5V_HDMI_S0
4 CPU_HDMI_TX0-
CPU_HDMI_TX1+ CV257 1 2 0.1u_0201_10V6K HDMI_TX1+_C
4 CPU_HDMI_TX1+
CPU_HDMI_TX1- CV258 1 2 0.1u_0201_10V6K HDMI_TX1-_C
4 CPU_HDMI_TX1-
RP9 RP8
CPU_HDMI_TX2+ CV259 1 2 0.1u_0201_10V6K HDMI_TX2+_C 2.2K_0404_4P2R_5% 2.2K_0404_4P2R_5% HDMI_CLK+_CON
4 CPU_HDMI_TX2+

3
4

3
4
HDMI_CLK-_CON
CPU_HDMI_TX2- CV260 1 2 0.1u_0201_10V6K HDMI_TX2-_C
4 CPU_HDMI_TX2- D31 EMC_NS@
CPU_HDMI_CLK+ CV261 1 2 0.1u_0201_10V6K HDMI_CLK+_C 2 1 1 10 9
4 CPU_HDMI_CLK+

2
1

2
1
CPU_HDMI_CLK- CV262 1 2 0.1u_0201_10V6K HDMI_CLK-_C 2 2 9 8
4 CPU_HDMI_CLK-
1 6 HDMI_DDC_CLK_CON 4 4 7 7
D 4 HDMI_DDC_CLK D
5 5 6 6
5 Q153A
@ AO5804EL_SC89-6 3 3
1 2
R865 0_0402_5% 8
L13 4 3 HDMI_DDC_DAT_CON
HDMI_CLK-_C HDMI_CLK-_CON 4 HDMI_DDC_DATA
1 2
1 2 AZ1045-04F_DFN2510P10E-10-9
EMC@ Q153B HDMI_TX0+_CON
HDMI_CLK+_C 4 3 HDMI_CLK+_CON AO5804EL_SC89-6 HDMI_TX0-_CON
4 3
EXC24CH900U_4P

1
@
2
H-PLUG +3VS
HDMI_TX1+_CON
R866 0_0402_5% HDMI_TX1-_CON
@

2
1 2 D32 EMC_NS@
R867 0_0402_5% R862 1 1 10 9
L12 1M_0402_5%
HDMI_TX0-_C 1 2 HDMI_TX0-_CON 2 2 9 8
1 2
2

1
EMC@ 4 4 7 7
HDMI_TX0+_C 4 3 HDMI_TX0+_CON
4 3 5 5 6 6
EXC24CH900U_4P PCH_HDMI_HPD 1 6 HDMI_HPD_OUT
4 PCH_HDMI_HPD
@ 3 3

2
1 2
R868 0_0402_5% Q160A R885 8
@ AO5804EL_SC89-6 20K_0402_5%
1 2
R869 0_0402_5% AZ1045-04F_DFN2510P10E-10-9

1
L14 HDMI_TX2-_CON
HDMI_TX1-_C 1 2 HDMI_TX1-_CON HDMI_TX2+_CON
1 2
EMC@
HDMI_TX1+_C 4 3 HDMI_TX1+_CON
4 3 HDMI_DDC_CLK_CON
C C
EXC24CH900U_4P HDMI_HPD_OUT

1
@
2
CONN
R870 0_0402_5% 5V_HDMI_S0 D34 EMC_NS@
@ 1 1 10 9
1 2
R871 0_0402_5% 2 2 9 8
L15
HDMI_TX2+_C 1 2 HDMI_TX2+_CON 4 4 7 7
1 2
250mA
EMC@ F1 5 5 6 6
HDMI_TX2-_C 4 3 HDMI_TX2-_CON 1 3 Q5 1 2

S
4 3 +5VS
AO3401A_SOT23-3 2 3 3
EXC24CH900U_4P 0.5A_8V_KMC3S050RY
@ CV263 8

G
2
1 2 SUSP# 0.1u_0201_10V6K
27 SUSP# 1
R872 0_0402_5%
@
AZ1045-04F_DFN2510P10E-10-9

5V_HDMI_S0
HDMI_DDC_DAT_CON

HDMI_CLK+_C R342 1 2470_0402_5% HDMI Type D

HDMI_CLK-_C R344 1 2470_0402_5% ME@
CV264 1 2 0.1u_0201_10V6K JHDMI
HDMI_TX0+_C R381 1 2470_0402_5% 19 17 HDMI_DDC_CLK_CON
5V_HDMI_S0 +5V_POWER SCL 18 HDMI_DDC_DAT_CON
HDMI_TX0-_C R382 1 2470_0402_5% SDA
B HDMI_TX0+_CON B
9
HDMI_TX1+_C R383 1 2470_0402_5% HDMI_TX0-_CON 11 TMDS_DATA0+ 15
HDMI_TX1+_CON 6 TMDS_DATA0- CEC 16
HDMI_TX1-_C R384 1 2470_0402_5% HDMI_TX1-_CON 8 TMDS_DATA1+ DDC/CEC_GROUND 1 HDMI_HPD_OUT
HDMI_TX2+_CON 3 TMDS_DATA1- HOT_PLUG_DETECT
HDMI_TX2+_C R385 1 2470_0402_5% HDMI_TX2-_CON 5 TMDS_DATA2+ 2 @
TMDS_DATA2- RESERVED#2 HDMI_CLK-_CON 1 2
HDMI_TX2-_C R389 1 2470_0402_5% 10 C26 3.3P_0402_50V8-C
7 TMDS_DATA0_SHIELD @
4 TMDS_DATA1_SHIELD HDMI_CLK+_CON 1 2
3 TMDS_DATA2_SHIELD C27 3.3P_0402_50V8-C
Q160B 20
13 GND0 21
AO5804EL_SC89-6 TMDS_CLOCK_SHIELD GND1
5 HDMI_CLK+_CON 12 22 @
+3VS TMDS_CLOCK+ GND2
HDMI_CLK-_CON 14 23 HDMI_TX0-_CON 1 2
TMDS_CLOCK- GND3 C1967 3.3P_0402_50V8-C
@
4 HDMI_TX0+_CON 1 2
C1964 3.3P_0402_50V8-C

ALLTO_C11455-11929-L
@
HDMI_TX1-_CON 1 2
C1966 3.3P_0402_50V8-C
@
HDMI_TX1+_CON 1 2
C1965 3.3P_0402_50V8-C

@
HDMI_TX2-_CON 1 2
C32 3.3P_0402_50V8-C
@
HDMI_TX2+_CON 1 2
C33 3.3P_0402_50V8-C

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/11/15 Deciphered Date 2013/11/08 HDMI
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Miix4
Date: Monday, August 17, 2015 Sheet 18 of 37
5 4 3 2 1
 5 4 3 2 1

@
USB30 R880 1 2 0_0402_5%

L68
USB20_N1 1 2 USB20_N1_CON
9 USB20_N1 1 2
EMC@
USB20_P1 4 3 USB20_P1_CON
9 USB20_P1 4 3
EXC24CH900U_4P
R881 1 2 0_0402_5%

@
@
R876 1 2 0_0402_5%

EXC24CH900U_4P
D D
1 2USB30_TX_N1_C 4 3 USB30_TX_N1_CON
9 USB30_TX_N1 C185 4 3
0.1u_0201_10V6K EMC@
1 2USB30_TX_P1_C 1 2 USB30_TX_P1_CON
9 USB30_TX_P1 C186 1 2
0.1u_0201_10V6K L69
R877 1 2 0_0402_5%
@

R878 1 2 0_0402_5%
@
EXC24CH900U_4P
USB30_RX_N1 4 3 USB30_RX_N1_CON
9 USB30_RX_N1 4 3
EMC@
USB30_RX_P1 1 2 USB30_RX_P1_CON
9 USB30_RX_P1 1 2
L70
R879 1 2 0_0402_5%
@

+5VALW
+5V_USB30

0.1u_0201_10V6K

100U_1206_6.3V6M
0.1u_0201_10V6K

C187

C15
1 1 1
C184

@
U8
5 1
2 IN OUT 2 2
2
GND
4 3
25,32 EC_USB_ON# EN FLG USB_OC0# 9
C C

G517F2T11U SOT-23

Current limit : 2.2A

+5V_USB30

ME@
JUSB30
1
USB20_N1_CON 2 VBUS
USB20_P1_CON D- USB type A
3
4 D+
USB30_RX_N1_CON 5 GND1
USB30_RX_P1_CON 6 SSRX- 10
7 SSRX+ GND3 11
USB30_TX_N1_CON 8 GND2 GND4 12
USB30_TX_P1_CON 9 SSTX- GND5 13
SSTX+ GND6

ALLTO_C107MJ-10939-L

B B

+5V_USB30
USB30_TX_P1_CON USB20_N1_CON
USB30_TX_N1_CON
USB20_P1_CON
D33 EMC_NS@
1 1 10 9
2

2
EMC_NS@

D9
AZ5725-01F_DFN1006P2X2

EMC_NS@

D10
AZ5725-01F_DFN1006P2X2

EMC_NS@

D17
AZ5725-01F_DFN1006P2X2

2 2 9 8
2

4 4 7 7

5 5 6 6
1

3 3
1

AZ1045-04F_DFN2510P10E-10-9
USB30_RX_P1_CON
USB30_RX_N1_CON

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/11/15 Deciphered Date 2013/11/08 SSD&USB30 Type C
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Miix4
Date: Monday, August 17, 2015 Sheet 19 of 37
5 4 3 2 1
 5 4 3 2 1

SSD

D +3VS +3.3V_NGFF D

MAX 1.5A
1 2
R23

10U_0402_6.3V6-M

0.1u_0201_10V6K
0_0603_5%

10U_0402_6.3V6M

C1019
4.7U_0402_6.3V6M

C207
1 1 1 1

C137

C146
@
2 2 2 2

+3.3V_NGFF
JSSD
C C
1 2
3 CONFIG_3 3.3V_1 4
5 GND1 3.3V_2 6
7 GND2 FULL_CARD_POWER_OFF#(O)(0/1.8Vor3.3V) 8
9 USB_D+ W_DISABLE1#(O)(0/3.3V) 10 1 @
11 USB_D- GPIO_9/DAS/DSS#(I/O)/LED#(I)(0/3.3V)
GND3 TP74
13 NC NC 12
15 NC NC 14
17 NC NC 16
19 NC NC 18

21 20
23 CONFIG_0 GPIO_5(I/O)(0/1.8V) 22
25 GPIO_11(I/O)(0/1.8V) GPIO_6(I/O)(0/1.8V) 24
27 DPR(O)(0/1.8V) GPIO_7(I/O)(0/1.8V) 26
29 GND4 GPIO_10(I/O)(0/1.8V) 28
31 PERn1/USB3.0-Rx-/SSIC-RxN GPIO_8(I/O)(0/1.8V) 30
33 PERp1/USB3.0-Rx+/SSIC-RxP UIM-RESET(I) 32
35 GND5 UIM-CLK(I) 34
37 PETn1/USB3.0-Tx-/SSIC-TxN UIM-DATA(I/O) 36
39 PETp1/USB3.0-Tx+/SSIC-TxP UIM-PWR(I) 38 DEVSLP R70 1 2 0_0402_5%
SATA_PRX_C_DTX_P1 GND6 DEVSLP(O) PCH_SATA_DEVSLP 9
0.01U_0201_10V6K 1 2 C1947 41 40
9 SATA_PRX_DTX_P1 SATA_PRX_C_DTX_N1 PERn0/SATA-B+ GPIO_0(I/O)(0/1.8V*)
0.01U_0201_10V6K 1 2 C1946 43 42 @
9 SATA_PRX_DTX_N1 PERp0/SATA-B- GPIO_1(I/O)(0/1.8V*)

2
45 44
0.01U_0201_10V6K 1 2 C1944 SATA_PTX_C_DRX_N1 47 GND7 GPIO_2(I/O)(0/1.8V*) 46 @ R608
9 SATA_PTX_DRX_N1 SATA_PTX_C_DRX_P1 PETn0/SATA-A- GPIO_3(I/O)(0/1.8V*)
0.01U_0201_10V6K 1 2 C1945 49 48 10K_0402_5%
9 SATA_PTX_DRX_P1 PETp0/SATA-A+ GPIO_4(I/O)(0/1.8V*)
51 50
53 GND8 PERST#(O)(0/3.3V) 52

1
55 REFCLKn CLKREQ#(I/O)(0/3.3V) 54
57 REFCLKp PEWAKE#(I/O)(0/3.3V) 56
59 GND9 NC1 58
61 ANTCTL0(I)(0/1.8V) NC2 60
63 ANTCTL1(I)(0/1.8V) COEX3(I/O)(0/1.8V) 62
65 ANTCTL2(I)(0/1.8V) COEX2(I/O)(0/1.8V) 64
67 ANTCTL3(I)(0/1.8V) COEX1(I/O)(0/1.8V) 66
B
PIRQA# R3038 1 2 0_0402_5% 69 RESET#(O)(0/1.8V) SIM_DETECT(O) 68 B
8,9 PIRQA# CONFIG_1 SUSCLK(32kHz)(O)(0/3.3V)
71 70
GND10 3.3V_3
2

@ 73 72
R3037 75 GND11 3.3V_4 74
CONFIG_2 3.3V_5 +3.3V_NGFF
0_0402_5%
77 76
GND13 GND12
1

LCN_DAN05-67136-0121

ME@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/11/15 Deciphered Date 2013/11/08 SSD&USB30 Type C
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Miix4
Date: Monday, August 17, 2015 Sheet 20 of 37
5 4 3 2 1
 5 4 3 2 1

Mini Card(WLAN/WiMAX)
+3VS_WLAN

+3VS 1 2
R31

22U_0603_6.3V6-M
0_0603_5%

C78

0.1u_0201_10V6K

0.1u_0201_10V6K
1 1 1

C53

C79
+3VS

2 2 2

+3VS_WLAN

JWLAN ME@
D D

1
1 2
R890 1 2 0_0402_5% USB20_P4_R 3 GND1 3.3V_1 4 R3015 R3019
9 USB20_P4 USB_D+ 3.3V_2
R892 1 2 0_0402_5% USB20_N4_R 5 6 1 @ TP52 49.9K_0402_1% 49.9K_0402_1%
9 USB20_N4 USB_D- LED1#(I)(OD)
7 8
9 GND2 PCM_CLK/I2S_SCK(O/I)(0/1.8V) 10

2
11 SDIO_CLK(O)(0/1.8V) PCM_SYNC/I2S_WS(O/I)(0/1.8V) 12
13 SDIO_CMD(I/O)(0/1.8V) PCM_IN/I2S_SD_IN(I)(0/1.8V) 14
15 SDIO_DATA0(I/O)(0/1.8V) PCM_OUT/I2S_SD_OUT(O)(0/1.8V) 16 1 @ TP61
+3VS_WLAN 17 SDIO_DATA1(I/O)(0/1.8V) LED2#(I)(OD) 18
19 SDIO_DATA2(I/O)(0/1.8V) GND11 20
21 SDIO_DATA3(I/O)(0/1.8V) UART_WAKE#(I)(0/3.3V) 22 UART_RX_DEBUG_R R256 1 2 0_0402_5%
SDIO_WAKE#(I)(0/1.8V) UART_RXD(I)(0/1.8V) UART_RX_DEBUG 9
23
SDIO_RESET#(O)(0/1.8V)
2

@ R2525 25 NC NC 24
10K_0402_5% 27 NC KEY E NC 26
29 NC PIN24~PIN31 NC PIN NC 28
31 NC NC 30
1

WLAN_PCIE_WAKE#

0.1u_0201_10V6K 33 32 UART_TX_DEBUG_R R3014 1 2 0_0402_5%

GND3 UART_TXD(O)(0/1.8V) UART_TX_DEBUG 9
C263 1 2 PCIE_PTX_C_DRX_P3 35 34
9 PCIE_PTX_DRX_P3 PETp0 UART_CTS(I)(0/1.8V)
C264 1 2 PCIE_PTX_C_DRX_N3 37 36
9 PCIE_PTX_DRX_N3 PETn0 UART_ RTS(O)(0/1.8V)
39 38 R124 1 2 0_0402_5% EC_TX_R
0.1u_0201_10V6K 41 GND4 VENDOR_DEFINED1 40 R125 1 2 0_0402_5% BT_OFF#
9 PCIE_PRX_DTX_P3 PERp0 VENDOR_DEFINED2
43 42
9 PCIE_PRX_DTX_N3 PERn0 VENDOR_DEFINED3
45 44
47 GND5 COEX3(I/O)(0/1.8V) 46
8 CLK_PCIE_WLAN REFCLKp0 COEX2(I/O)(0/1.8V)
49 48
8 CLK_PCIE_WLAN# REFCLKn0 COEX1(I/O)(0/1.8V)
51 50
WLAN_CLKREQ# GND6 SUSCLK(32kHz)(O)(0/3.3V) SUSCLK 8
8,9 WLAN_CLKREQ# 53 52
PCIE_WAKE# CLKREQ0#(I/O)(0/3.3V) PERST0#(O)(0/3.3V) PCH_PLT_RST# 8,22,24,25,26
8 PCIE_WAKE# 1 @ 2 WLAN_PCIE_WAKE# 55 54 BT_OFF#
R120 0_0402_5% 57 PEWAKE0#(I/O)(0/3.3V) W_DISABLE2#(O)(0/3.3V) 56
GND7 W_DISABLE1#(O)(0/3.3V) PCH_WLAN_OFF# 9

59 58 @ 1 TP68
61 RESERVED/PETp1 I2C_DATA(I/O)(0/3.3V) 60 @ 1 TP82
63 RESERVED/PETn1 I2C_CLK(O)(0/3.3V) 62 @ 1 TP111
65 GND8 ALERT#(I)(0/3.3V) 64 EC_TX_R
67 RESERVED/PERp1 RESERVED 66
BT_OFF# R123 1 2 1K_0402_5% 69 RESERVED/PERn1 UIM_SWP/PERST1# 68 +3VS_WLAN
PCH_BT_OFF# 9 GND9 UIM_POWER_SNK/CLKREQ1#
71 70
73 RESERVED/REFCLKp1 UIM_POWER_SRC/GPIO1/PEWAKE1# 72
EC_TX_R R187 1 2 100_0402_1% 75 RESERVED/REFCLKn1 3.3V_3 74
EC_TX 25 GND10 3.3V_4
BT_OFF# R188 1 2 100_0402_1% 77 76
EC_RX 25 GND15 GND14
LCN_DAN05-67136-0122
1

C C
R192
100K_0402_5%
2

WLAN&BT Combo module circuits

BT on module BT on module
Enable Disable

* BT_CRTL H L
PCH_BT_ON# L H

Mini Card(WWAN)
+3VS +3VS_WWAN

R24 1 2 0_0603_5%

WWAN@
1.1A average +3VS_WWAN
+3VS_WWAN
+3VS_WWAN
R55
100K_0402_5%
1

2
@ WWAN@ WWAN@
R886 R626
+3VS_WWAN
22U_0603_6.3V6-M

22U_0603_6.3V6-M

0.1u_0201_10V6K

0.1u_0201_10V6K

0.01U_0201_10V6K

0.01U_0201_10V6K

B 47K_0402_5% B
10K_0402_5%
R886 change to 10K or lower is better if huawei wwan card is used.
C81

C82

C341

C342

1 1 1 1 1 1 JWWAN
2
C83

C84

1
1 2
@ @ 3 CONFIG_3 3.3V_1 4 @
2 2 2 2 2 2 5 GND1 3.3V_2 6 R129 1 2 0_0402_5%
USB20_P5_R GND2 FULL_CARD_POWER_OFF#(O)(0/1.8Vor3.3V) FULL_CARD_POWER_OFF# 9
7 8 R133 1 2 0_0402_5%
USB20_N5_R USB_D+ W_DISABLE1#(O)(0/3.3V) PCH_WWAN_OFF# 7
9 10
WWAN@ 11 USB_D- GPIO_9/DAS/DSS#(I/O)/LED#(I)(0/3.3V)
WWAN@ WWAN@ WWAN@ GND3

13 NC NC 12
15 NC NC 14
17 NC NC 16
19 NC NC 18 UIM_RFU pin(C6) :reserved for future use ,not connect

R121 @ 0_0402_5% 21 20 ME@

R887 1 2 0_0402_5% USB20_P5_R PCIE_WAKE# 1 2WWAN_PCIE_WAKE# 23 CONFIG_0 GPIO_5(I/O)(0/1.8V) 22 JMICRO
9 USB20_P5 P_IRQ_R GPIO_11(I/O)(0/1.8V) GPIO_6(I/O)(0/1.8V) UIM_SIM_DETECT
1 2 25 24 1
USB20_N5_R 26 P_IRQ_R DPR(O)(0/1.8V) GPIO_7(I/O)(0/1.8V) CD
R888 1 2 0_0402_5% 0_0402_5% R3041 27 26 R134 1 2 0_0402_5% 2
9 USB20_N5 USB30_RX_N2_CON GND4 GPIO_10(I/O)(0/1.8V) PCH_GNSS_DISABLE# 9 C8
@ 29 28 R226 0_0402_5% 3 18
USB30_RX_P2_CON 31 PERn1/USB3.0-Rx-/SSIC-RxN GPIO_8(I/O)(0/1.8V) 30 UIM_RESET UIM_DATA 1 2 UIM_DATA_R 4 C4 GND8 17
33 PERp1/USB3.0-Rx+/SSIC-RxP UIM-RESET(I) 32 UIM_CLK UIM_PWR UIM_CLK 5 C7 GND7 16
@ @ USB30_TX_N2_CON 35 GND5 UIM-CLK(I) 34 UIM_DATA 6 C3 GND6 15
1 2 USB30_TX_N2_C R901 1 2 0_0402_5% USB30_TX_N2_CON USB30_TX_P2_CON 37 PETn1/USB3.0-Tx-/SSIC-TxN UIM-DATA(I/O) 36 UIM_RESET 7 C6 GND5 14
9 USB30_TX_N2 PETp1/USB3.0-Tx+/SSIC-TxP UIM-PWR(I) C2 GND4
C192 0.1u_0201_10V6K 39 38 8 13
1 2 USB30_TX_P2_C R902 1 2 0_0402_5% USB30_TX_P2_CON 41 GND6 DEVSLP(O) 40 9 C5 GND3 12
9 USB30_TX_P2 PERn0/SATA-B+ GPIO_0(I/O)(0/1.8V*) C1 GND2
C194 0.1u_0201_10V6K @ 43 42 10 11
PERp0/SATA-B- GPIO_1(I/O)(0/1.8V*) N/A GND1

0.1u_0201_10V6K
@ 45 44 1
GND7 GPIO_2(I/O)(0/1.8V*)

C1030
4.7U_0402_6.3V6M
47 46 1 1 WWAN@
PETn0/SATA-A- GPIO_3(I/O)(0/1.8V*)

C85
49 48 UIM_PWR C1956 T-SOL_159-1020302601
51 PETp0/SATA-A+ GPIO_4(I/O)(0/1.8V*) 50 WWAN@ 47P_0402_50V8-J
53 GND8 PERST#(O)(0/3.3V) 52 2
USB30_RX_N2 R904 1 2 0_0402_5% USB30_RX_N2_CON 55 REFCLKn CLKREQ#(I/O)(0/3.3V) 54 2 2
9 USB30_RX_N2 REFCLKp PEWAKE#(I/O)(0/3.3V)

1
@ 57 56
USB30_RX_P2 R903 1 2 0_0402_5% USB30_RX_P2_CON 59 GND9 NC1 58 R1549
9 USB30_RX_P2 ANTCTL0(I)(0/1.8V) NC2
61 60 WWAN@ 51_0402_5%
@ 63 ANTCTL1(I)(0/1.8V) COEX3(I/O)(0/1.8V) 62
65 ANTCTL2(I)(0/1.8V) COEX2(I/O)(0/1.8V) 64 WWAN@

2
WWAN_RESET# 1 2 WWAN_RESET#_R 67 ANTCTL3(I)(0/1.8V) COEX1(I/O)(0/1.8V) 66 UIM_SIM_DETECT
25 WWAN_RESET# RESET#(O)(0/1.8V) SIM_DETECT(O) C1956,R1549 EMC Parts
0_0402_5% R130 69 68
71 CONFIG_1 SUSCLK(32kHz)(O)(0/3.3V) 70 +3VS_WWAN
@ 1 GND10 3.3V_3
73 72
C1963 @ 75 GND11 3.3V_4 74
33P_0201_50V8-J CONFIG_2 3.3V_5
2 77 76 UIM_PWR
GND13 GND12 UIM_DATA_R
UIM_CLK

UIM_PWR
Pulling low RESET# more than 20 ms UIM_RESET
+1.8VS

2
A LCN_DAN05-67136-0121 A

AZ5725-01F_DFN1006P2X2

AZ5725-01F_DFN1006P2X2

AZ5725-01F_DFN1006P2X2

AZ5725-01F_DFN1006P2X2
WWAN_RESET#_R

2
EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@
ME@

D4012

D4013

D4014

D4015
@
1

RE27 R95

1
@ 10K_0402_5% 1M_0402_5% Q168
DMG1012T-7_SOT523-3

1
WWAN_RESET# 1 2 2
2

0_0402_5% R3039
UIM_SIM_DETECT WWAN@ WWAN@
3

UIM_PWR
1

RE28
@ 10K_0402_5% Title
Security Classification LC Future Center Secret Data
2

R416
Issued Date 2014/11/15 Deciphered Date
Reserve
2013/11/08 CONN(WLAN&KB&PWRB&UART)
2

@ 4.7K_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1

UIM_RESET D 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Miix4
Date: Monday, August 17, 2015 Sheet 21 of 37
5 4 3 2 1
 5 4 3 2 1

MIPI_ICA R96 1 2 0_0402_5%

MIPI Camera FLASH_3V3

10U_0402_6.3V6M C1982
100U_1206_6.3V6M

100U_1206_6.3V6M

100U_1206_6.3V6M

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K
10U_0402_6.3V6M
+3VS +MIPI_VDD +3VALW +3VS +MIPI_SUS

C1985

C1984

C1983

C1981
5A MIPI_ICB R102 1 2 0_0402_5% 1 1 1 1 1 1 1 1

C1976

C1977

C1978
0_0603_5% 0_0603_5% FLASH_3V3
1 2 1 2 +MIPI_VDD U30 3A 到 6A 可可setti ng . FLASH_3V3 WF@
L1 2 2 2 2 2
R3044 0_0603_5% R37 WF@ 2 2 2
1 2 2 @ 1 D1 F3 +WLED_SW 1 2
R3045 R39 0_0603_5% B6 3V3_VDD_01 WLED_SW_03 F2 WF@ WF@ WF@
+3VS FLASH_3V3 A7 3V3_VDD_02 WLED_SW_02 F1 +MIPI_WLED 2.2UH_HMME32251E-2R2MSR_3.9A_20% WF@ WF@ WF@
G6 3V3_VDD_03 WLED_SW_01
3V3_VDD_04 WF@
0_0603_5% +MIPI_SUS H5 E3
1 2 3V3_VDD_05 WLED_OUT_03 E2
R3046 B5 WLED_OUT_02 E1
3V3_SUS WLED_OUT_01 FLASH_GND
D @ 1 D3 D
+MIPI_VDD TP147 MIPI_SDA GPIO0
D6 H3 @1 TP146
MIPI_SCL F6 GPIO1 DRV_WLED2
@ 1 MIPI_CLK C3 GPIO2
TP156 ANA2_PWRCNTL C4 GPIO3 MIPI_WLED_DRV1
H1
GPIO4 DRV_WLED1 MIPI_WLED_DRV1 28 +MIPI_VCM
0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K
UF_PWRCNTL C6
GPIO5
C1020
4.7U_0402_6.3V6M
10U_0402_6.3V6M

1 1 1 1 1 @ 1 E6
TP144 GPIO6
C228

C229

C230
C138

H2 G3 VCM_PD 2 1
8,21,24,25,26 PCH_PLT_RST# SENSOR_PWRCNTL RESET_IN WLED_GND_03
E4
2 2 2 2 2 @ 1 E5 S_RESETN G2 R97 @ 10K_0402_5%
TC95 MIPI_IDLE S_ENABLE WLED_GND_02 +MIPI_VIO1
@ 1 D4
TC94 S_IDLE
C1 G1
CD@ D2 S_VSYNC WLED_GND_01
10 PCH_FLASH__STROBE S_STROBE MIPI_WLED_NTC MIPI_SDA
C2 4 1
+MIPI_PLLVDD WLED_NTC MIPI_WLED_NTC 28 MIPI_SCL
WF@ 3 2
A5 B2 MIPI_WLED_LEDA1 2 RPE682 2.2K_0404_4P2R_5%
@ 1 PLL_VDD ILEDA D39 SDM10U45LP-7_DFN1006-2-2 FLASH_GND +MIPI_VDD
TC191 R3032 WF@
PLL_COMP1 A3 100_0402_5%
+MIPI_SUS +MIPI_PLLVDD PLL_COMP1 B3 MIPI_WLED_LEDB1 2 1 2 +MIPI_VCORE1 MIPI_WLED_LEDA 4 1
PLL_COMP2 ILEDB MIPI_WLED_LED 25,28 MIPI_WLED_LEDB
A4 D40 SDM10U45LP-7_DFN1006-2-2 3 2
R42 0_0402_5% PLL_COMP2 G7 +MIPI_CORE_SW 1 2 @ RPE681 2.2K_0404_4P2R_5%
1 2 B4 CORE_SW
PLL_GND
1.2V 500mA
0.1u_0201_10V6K

H6 1 2 L3 1UH_HMME32251E-1R0MSR_4.4A_20%
CORE_FB
C1021
4.7U_0402_6.3V6M

0.1u_0201_10V6K

1 1
C231

MIPI_OSC_IN
2.2U_0402_6.3V6M

1 1 @ B1 H7 R249 0_0402_5%
OSC_IN CORE_GND FLASH_3V3 +MIPI_WLED +MIPI_VCORE1
C239
C233

@
MIPI_OSC_OUT A1 D5 MIPI_HCLKA
2 2 OSC_OUT HCLK_A +MIPI_VSIO2 +MIPI_VIO1
2 2

10U_0402_6.3V6M C141
C5 MIPI_HCLKB
HCLK_B +MIPI_VSIO2

1U_0201_6.3V6-K

1U_0201_6.3V6-K
10U_0402_6.3V6M

10U_0603_10V6K

10U_0603_10V6K
MIPI_ICA G4
I2C_ICA

C1022
4.7U_0402_6.3V6M
C140
PLL_GND 1 1 1 1 1 1 1
+MIPI_VCORE2

CC1131

CC1130
C143

C144
MIPI_ICB F4 C7 1.2V 150mA
I2C_ICB AUX1_OUT +MIPI_VCM WF@ @
slave address:0x00 PM_I2C_SDA2 F5 A6 1.8V 100mA WF@
9 PM_I2C_SDA2 SDA AUX2_OUT 2 2 2 2 2 2 2
PLL_GND WF@ WF@ @ @
PM_I2C_SCL2 G5 H4 2.8V 500mA +MIPI_VANA1
9 PM_I2C_SCL2 SCL VCM_OUT
R49 0_0402_5% +MIPI_VSIO1
PLL_COMP1 PLL_COMP2 1 2 A2 B7 2.8V 200mA
GND ANA_OUT +MIPI_VIO1
R3017
8.2K_0402_1%

R3016
8.2K_0402_1%

C C
1

D7 1.8V 150mA
F7 S_IO_OUT
IO_GND E7
IO_OUT
1.8V 50mA FLASH_GND FLASH_GND
0.01U_0402_25V7K C1949

TPS68470_DSBGA56
2

+MIPI_VCORE2 +MIPI_VANA1 +MIPI_VSIO1 +MIPI_VCM

2200P_0402_50V7K C1951
2200P_0402_50V7K C1952
0.01U_0402_25V7K

1 1 1 1
WF@
+MIPI_VDD +MIPI_VANA2

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
C1950

1 1 2 1 1 2 WF@ 1 1 2 WF@ 1 1 2

CC1982
1U_0402_10V6K

C1971
.1U_0402_10V6-K

C1969
.1U_0402_10V6-K

CC1983
1U_0402_10V6K

C1972
.1U_0402_10V6-K

CC1984
1U_0402_10V6K

C1973
.1U_0402_10V6-K
C1968
CC1127

CC1129

CC1126

CC1128
2 2 2 2 WF@

4.7U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
1 1 1 2 WF@
2 2 1 2 2 1 2 2 1 2 2 1

C1023

C1970
.1U_0402_10V6-K
C142

CC1132
150mA
WF@ WF@
2 2 2 1 WF@
PLL_GND PLL_GND WF@
U6
@ 2 1 3 4
VIN VOUT

220P_0402_50V7K
RC73 2 1 1M_0402_5% R41 0_0603_5%

21.5K_0402_1%
2 1
GND

C1131
R3023
Y5 5 For WF power:
ANA2_PWRCNTL 1 SET
2 3 MIPI_OSC_OUT PLL_GND SHDN +MIPI_VSIO1 For UF power:
1
GND1 OSC2 2 +MIPI_VCORE2
C234
0.1u_0201_10V6K
APL5325BI-TRG_SOT23-5 +MIPI_VANA1

2
MIPI_OSC_IN 1 4
OSC1 GND2 +MIPI_VCM +MIPI_VANA2
2 1 2
1

8.45K_0402_1%
1 20MHZ_6PF_XTL571200-L150-016 R3047 0_0603_5%

1
CC13 CC14 @ 2 1

R3018
4.7P_0402_50V8B @ 4.7P_0402_50V8B R3048 0_0603_5%
2
2
slave address:0x20

2
FLASH_GND JWF ME@

CC13 ,CC14 May be NC Base on validate result TC172 @ 1 2 TC174

R250 0_0402_5% 1 2 @

1
MIPI_HCLKA 1 2 MIPI_HCLKA_R 3 4
B 10 PCH_CSI2_CLKP1 3 4 PCH_CSI2_DN3 10 B
0_0402_5%
MIPI_HCLKB 1 2 MIPI_HCLKB_R 5 6
10 PCH_CSI2_CLKN1 5 6 PCH_CSI2_DP3 10

68P_0201_25V8-J
R251

1
+3VS +3VS_3D

68P_0201_25V8-J
TC173 @ 7 8 @ TC176
7 8 TC175 @
0.6A 1 1

1
@ 1 1 MIPI_SDA 9 10
9 10 PCH_CSI2_DN2 10
C1959

C1960
2 1 C1958 @ @ C1957
R44 0_0603_5% @ @ 33P_0201_50V8-J 33P_0201_50V8-J MIPI_SCL 11 12
2 2 TC184 @ 11 12 PCH_CSI2_DP2 10

1
2 2 13 14 @

1
Q42 3D@ 13 14 TC177
+MIPI_VCM 15 16 +MIPI_VSIO1
15 16
S

3 1
LP2301ALT1G_SOT23-3 @ 3D@ SENSOR_PWRCNTL_R 17 18 MIPI_HCLKA_R
17 18
C1024
4.7U_0402_6.3V6M

1 1 1 1 1 0_0402_5%
C1986
0.1u_0201_10V6K

C1988
0.1u_0201_10V6K

C240
0.1u_0201_10V6K

C241
0.1u_0201_10V6K

@ @ 1 2 VCM_PD 19 20 +MIPI_VANA1
G
2

3D@ R243 0_0402_5% 19 20

SENSOR_PWRCNTL 1 2 SENSOR_PWRCNTL_R R240 21 22
21 22

1
2 2 2 2 2 0_0402_5% @ @
UF_PWRCNTL 1 2 UF_PWRCNTL_R 23 24 TC185 TC186
1 2 SENSOR_PWRCNTL_R 2 1 WF@ 23 24
9 PCH_3D_PWREN#

0.1u_0201_10V6K

0.1u_0201_10V6K
R292 0_0402_5% R244 R241
0.1u_0201_10V6K

0.1u_0201_10V6K

3D@ 1 1 100K_0402_5% HRS_DF37NC-24DS-0P4V-51

1

C235

C236
1 1 1 @
C1987
0.1u_0201_10V6K

C237

C242

R3049 @ @ UF_PWRCNTL_R 2 1
@ 470K_0402_5% R242
2 2 100K_0402_5%
2 2 2
2

JUF ME@ TC188 @ TC187 @

23

1
GND2
slave address:0x6C 1 2 +MIPI_VANA2
3 1 2 4 +MIPI_VCORE2
3D@ 5 3 4 6 MIPI_HCLKB_R
R897 1 2 0_0402_5% 7 5 6 8
3D@ 9 7 8 10
EXC24CH900U_4P VSYNC Signal for two WF camera in future ,now NC. 9 PM_I2C_SDA3 UF_PWRCNTL_R 11 9 10 12
PM_I2C_SCL3 9
1 2 USB30_TX_N4_C 4 3 USB30_TX_N4_CON 13 11 12 14 PCH_CSI2_DP1 10
9 USB30_TX_N4 4 3 10 PCH_CSI2_DN1 13 14
C188 0.1u_0201_10V6K ME@ 15 16
A J3D 10 PCH_CSI2_CLKP0 15 16 PCH_CSI2_CLKN0 10 A
EMC_NS@ 17 18
1 2 USB30_TX_P4_C 1 2 USB30_TX_P4_CON 1 19 17 18 20 PCH_CSI2_DP0 10
9 USB30_TX_P4 1 2 USB30_RX_N4_CON 1 10 PCH_CSI2_DN0 19 20
C189 0.1u_0201_10V6K 2 21
2 21

1
L81 USB30_RX_P4_CON 3 11 22 @ @ @
3D@ 3 GND1 GND1
R898 1 2 0_0402_5% 4 TC178 TC179 TC180
4

1
3D@ USB30_TX_N4_CON 5 @ @ @
5 HRS_FH35C-21S-0P3SHW-50
3D@ USB30_TX_P4_CON 6 TC181 TC182 TC183
R899 1 2 0_0402_5% 7 6 12
8 7 GND2
EXC24CH900U_4P 9 8
USB30_RX_N4 4 3 USB30_RX_N4_CON +3VS_3D 10 9
9 USB30_RX_N4 4 3 10 Security Classification LC Future Center Secret Data Title
EMC_NS@
USB30_RX_P4 1 2 USB30_RX_P4_CON
I-PEX_20347-310E-12
Issued Date 2014/11/15 Deciphered Date 2013/11/08 MCU
9 USB30_RX_P4 1 2
L82 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
R900 1 2 0_0402_5% Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Miix4
3D@ Date: Monday, September 14, 2015 Sheet 22 of 37

5 4 3 2 1
 5 4 3 2 1

CODEC
UA1

4.7U_0402_6.3V6M
+5VS
10 20 +5VA 0_0603_5% 1200mA
DC_DET AVDD1 33 +1.8V_SYSA 2 1 +5V_AUD
AVDD2 1

CA325
7 PCH_HDA_BCLK RA4 1 PCH_HDA_BCLK_R
2 0_0402_5% 5
BCLK

10U_0402_6.3V6M
10U_0603_6.3V6M
29 +1.8V_SYS 1 RA20 1 1 1 1
CPVDD

4.7U_0402_6.3V6M

CA383

CA327
0.1u_0201_10V6K

CA320
0.1u_0201_10V6K
CA384
9
7 PCH_HDA_SYNC SYNC ALC3240-CG 2

CA326
1 +3V_AUD
1 2 PCH_HDA_SDIN0_R 7 DVDD
7 PCH_HDA_SDIN0 SDATA-IN +3V_AUD_IO 2 2 2@ 2 2
7 PCH_HDA_SDOUT RA3 22_0402_5% 4 8 AUDIO_AGND
SDATA-OUT DVDD-IO
1

CA318
0.1u_0201_10V6K
34 +5V_AUD
DMIC_DATA_R 2 PVDD1 39
D DMIC_CLK_R 3 GPIO0/DMIC-DATA12 PVDD2 D
GPIO1/DMIC-CLK 2

1U_0201_6.3V6-K
SPKR_MUTE# 40 22 1
HPOUT-JD 1 2 HPOUT-JD_R 12 PDB VREF

CA382
R1 200K_0402_1% HP/LINE1-JD(JD1) 23 MIC2-VREFO +3VS
BEEP 11 MIC2-VREFO
13 PCBEEP 24 2 2 1 +3V_AUD
SLEEVE 14 MIC2-L(PORT-F-L)/RING2 LINE1-VREFO-L RA18 0_0603_5%
MIC2-R(PORT-F-R)/SLEEVE
1 1 5mA

1U_0201_6.3V6-K

CA330
0.1u_0201_10V6K
27 AUDIO_AGND

CA380
15 CPVEE 28
1 MIC2-CAP CBN
17 30 1
LINE1-R(PORT-C-R) CBP 2 2

1U_0201_6.3V6-K
CA324 18

CA388
LINE1-L(PORT-C-L) 1

4.7U_0402_6.3V6M

1U_0201_6.3V6-K
4.7U_0402_6.3V6M 21

CA385
2 LDO1-CAP 1

CA328
AUDIO_AGND 32
LDO2-CAP 2

4.7U_0402_6.3V6M
SPK_L+ 35 6
SPK-OUT-LP LDO3-CAP 2

4.7U_0402_6.3V6M
SPK_L- 36 1
SPK-OUT-LN 2

CA329
+3V_AUD SPK_R- 37 16 RA5 1 2 0_0402_5%
SPK_R+ 38 SPK-OUT-RN VD33STB
SPK-OUT-RP 1

CA331
AUDIO_AGND RA6 1 2 0_0402_5% AUDIO_AGND
1

19 @ 2
R4 HPOUT-L 25 AVSS1 31 +3VALW_PCH
HPOUT-L(PORT-I-L) AVSS2 2 CPU HDA BUS power
100K_0402_1% HPOUT-R 26 AUDIO_AGND
HPOUT-R(PORT-I-R) 41 +3VALW +3VL 2 1
GND(Thermal_Pad) RA27 0_0603_5%
2

HPOUT-JD_R
ALC3240-CG_MQFN40_5X5 +3V_AUD 1 2 +3V_AUD_IO
AUDIO_AGND
RA19 0_0402_5% 1mA
@
+5VS

0_0402_5% 2 1 +5VA
1 2 SPKR_MUTE# RA21 0_0603_5%
25 EC_MUTE#

2.2U_0402_6.3V6M
RA15 VD33STB:Power for combo jack depop circuit at system shutdown mode. 1 1 19mA
2

CA317
0.1u_0201_10V6K
CA381
RA2 1 2 0_0402_5%
C RA23 C
10K_0402_5% AVDD1:Analog power for mixers ,IO ports
RA8 1 2 0_0402_5% 2 2
CA381 change to 2.2U_0402_10V
DVDD-IO:Digital power for HDA link
1

RA12 1 2 0_0402_5%

RA13 1 2 0_0402_5% DVDD:Digital power for digital I/0 circuit

AVDD2:Analog power for DACS ,ADCS AUDIO_AGND

AUDIO_AGND
DA1
PVDD1,PVDD2:Power supply for full-bridge left and right channel +1.8VS
25 EC_BEEP 3 CA323
RA16
0.1u_0201_10V6K
1 1 2 1 2 BEEP 2 1 +1.8V_SYS
RA25 0_0603_5%
7 PCH_BEEP 2 131mA
1K_0402_5%
2

BAT54CW_SOT323-3
RA24
10K_0402_5%
+1.8V_SYS 2 1 +1.8V_SYSA
RA26 0_0603_5%
1

26mA

@
RA17 1 2 0_0402_5%

CA378
470P_0201_25V7K
L75 EMC@ BLM15BX750SN1D_2P
SPK_L+ 1 2 SPK_L+_CON 1
L76 BLM15BX750SN1D_2P MIC2-VREFO
SPK_L- 1 2 SPK_L-_CON PCH_HDA_BCLK_R DMIC_CLK DMIC_DATA_R
EMC@ D4006 D4009 AUDIO_AGND
2

1
2

2200P_0402_50V7K

2200P_0402_50V7K
22P_0201_25V8

EMC_NS@

EMC_NS@
1 1 1
AZ5725-01F_DFN1006P2X2
EMC_NS@

AZ5725-01F_DFN1006P2X2
EMC_NS@

CA104

CA105
CA16
RA28 1 2 0_0402_5% RA683
2

1 1 2.2K_0402_5% EMC@
EMC@
1000P_0201_50V7-K
CA152

EMC@
1000P_0201_50V7-K
CA153

@
B 2 2 2 B

2
SLEEVE SLEEVE 28
2 2
1

4 ohm ,0.7W
HPOUT-L 1 2 HP_L_CON
HP_L_CON 28
1

RA57 47_0402_1%
0.418A RMS HPOUT-R 1 2 HP_R_CON
HP_R_CON 28
ELCO_046809604X10846+ RA59 47_0402_1%
HPOUT-JD HPOUT-JD 28
@ 6
RA29 1 2 0_0402_5% GND2
4
EMC@ BLM15BX750SN1D_2P 3 4
SPK_R- L77 1 2 BLM15BX750SN1D_2P SPK_R-_CON 2 3
SPK_R+ 1 2 SPK_R+_CON 1 2
L78 EMC@ D4010 D4011 1
2

5
GND1
AZ5725-01F_DFN1006P2X2
EMC_NS@

AZ5725-01F_DFN1006P2X2
EMC_NS@

RA30 1 2 0_0402_5%
2

1 1 JSPK ME@
EMC@
1000P_0201_50V7-K
CA154

EMC@
1000P_0201_50V7-K
CA155

2 2
1

L85
@ 4.7NH_HCI1005F-4N7S-M8_30%
1

2 1

1 2 0_0402_5% DMIC_DATA_R
28 DMIC_DATA
RA22 1 2 DMIC_CLK_R
28 DMIC_CLK
RA11 22_0402_5%
@
2 1

L84 4.7NH_HCI1005F-4N7S-M8_30%

A SPK_L+ 1 2 EMC_NS@ 1 2 EMC_NS@ A

RA194 15_0402_5% CA173 220P_0201_25V7-K

SPK_L- 1 2 EMC_NS@ 1 2 EMC_NS@

RA195 15_0402_5% CA174 220P_0201_25V7-K

SPK_R+ 1 2 EMC_NS@ 1 2 EMC_NS@

RA196 15_0402_5% CA175 220P_0201_25V7-K

SPK_R- 1 2 EMC_NS@ 1 2 EMC_NS@

RA197 15_0402_5% CA176 220P_0201_25V7-K Title
Security Classification LC Future Center Secret Data
RA194,RA195,RA196,RA197 will to be changed to 15ohm
Place Close To Codec Issued Date 2014/11/15 Deciphered Date 2013/11/08 AUDIO
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Miix4
Date: Monday, August 17, 2015 Sheet 23 of 37
5 4 3 2 1
 5 4 3 2 1

D D

Card Reader
+3VS +3VS_CR

1 2
RW34
4.7U_0402_6.3V6M

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K
0_0603_5%
1 1 1 1
CW2

CW3

CW13

CW16
2 2 2 2

VID;1217
DID:8621
UW1

1 28 +3VS_CR
8 CLK_PCIE_CR# PE_REFCLKM PE_33VCCAIN +CARD_3V
2 27 LDO_V12 CW15 1 2 0.1u_0201_10V6K
8 CLK_PCIE_CR PE_REFCLKP PE_PDLL_12VCCAIN JREAD1
R873 1 2191_0402_1% 3 26 SD_D2_R
PE_REXT SD_D2 4
C C
VDD

.1U_0402_10V6-K
CW182 1 2 0.1u_0201_10V6K PCIE_PTX_C_DRX_N4 4 25 SD_D3_R
9 PCIE_PTX_DRX_N4 PE_RXM SD_D3 SD_CLK
1 1 5
CW183 1 2 0.1u_0201_10V6K PCIE_PTX_C_DRX_P4 5 24 SD_CMD_R SD_CMD 3 CLK
9 PCIE_PTX_DRX_P4 PE_RXP SD_CMD CMD
BH611FJ1LN CW19 @ CW20
CW179 1 2 0.1u_0201_10V6K PCIE_PRX_C_DTX_P4 6 23 SD_CLK_R 4.7U_0402_6.3V6M 6
9 PCIE_PRX_DTX_P4 PE_TXP 28-QFN SD_CLK 2 2 VSS
CW180 1 2 0.1u_0201_10V6K PCIE_PRX_C_DTX_N4 7 22 SD_D0_R SD_D0 7
9 PCIE_PRX_DTX_N4 PE_TXM SD_D0 SD_D1 DAT0
8
CW14 1 2 4.7U_0402_6.3V6M LDO_V12 8 21 SD_D1_R SD_D2 1 DAT1
LDO_12VOUT SD_D1 SD_D3 2 DAT2
+3VS_CR
Close to Connector CD/DAT3
9 20
LDO_VIN1 CLKREQ# CR_CLKREQ# 8,9 SD_CD# 9
CW4 1 2 1U_0201_6.3V6-K 10 19 SD_WP SD_DET
LDO_CAP SD_WPI 10
11 18 SD_CD# 11 SD_DET_GND1
LDO_VIN2 SD_CD# 12 SD_DET_GND2
12 17 13 SD_DET_GND3
MAIN_LDO_EN SD_IO_LDO_CAP SD_DET_GND4

4.7U_0402_6.3V6M

0.1u_0201_10V6K
PCH_PLT_RST# 13 16 +3VS_CR
1,22,25,26 PCH_PLT_RST# PE_RST# SD_IO_SKT_33VIN
1 1

CW17

CW18
14 15 +CARD_3V T-SOL_158-1030902601
GND SD_SKT_33VOUT
29
Exposed_Pad 2 2 ME@ SD / MMC
CW182,CW183 Close to CPU. BH611FJ1LN_QFN28_4X4

FOR EMI
B B
0_0402_5%
SD_D0_R 1 2 SD_D0
RW3 CW5 1 2 5.6P_0402_50V8-D
0_0402_5%
EMC_NS@
SD_D1_R 1 2 SD_D1
RW4 CW6 1 2 5.6P_0402_50V8-D
SD_WP RW10 1 2 0_0402_5% SD_CD# 0_0402_5%
EMC_NS@
SD_D2_R 1 2 SD_D2
RW5 CW7 1 2 5.6P_0402_50V8-D
0_0402_5%
EMC_NS@
SD_D3_R 1 2 SD_D3
For micro SD 插SDW P signal RW6 CW8 1 2 5.6P_0402_50V8-D
0_0402_5%
EMC_NS@
SD_CMD_R 1 2 SD_CMD
RW7 CW11 1 2 5.6P_0402_50V8-D
0_0402_5%
EMC_NS@
SD_CLK_R 1 2 SD_CLK
RW8 CW12 1 2 5.6P_0402_50V8-D
EMC_NS@

Close to UW1 Placement

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/11/15 Deciphered Date 2013/11/08 SSD&USB30 Type C
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Miix4
Date: Monday, August 17, 2015 Sheet 24 of 37
5 4 3 2 1
 5 4 3 2 1

PWR +3VALW_EC

EC_VOL_UP# 4 1
EC_VOL_DOWN# 3 2
+3VALW_EC
+3VALW_EC +3VALW_EC_VCCA RPE683 100K_0404_4P2R_5%
LID_PAD# 2 1
RE196 @ 10K_0402_5%
+3VALW 2 @ 1 1 2

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K
RE1 0_0603_5% 1 1 1 1 1 1 1 0_0603_5% RE22 1 1 LID_SW# 2 1

CE15

CE11

CE10

CE9

CE8

CE7

CE6

CE3

CE4
1000P_0201_25V7K
@ @ @ @ RE197 @ 10K_0402_5%

+3VL 1 2
2 2 2 2 2 2 2 2 2 EC_SMB_CLK1 4 1
RE5 0_0603_5% EC_SMB_DAT1 3 2
RPE680 2.2K_0404_4P2R_5%
1 2
RE23
0_0603_5% EC_ONOFF_BTN# 4 1
D EC_USB_ON# 3 2 D
EC_AGND RPE204 100K_0404_4P2R_5%

DOCK_DET# 1 2100K_0402_5%
RE51
EC_WC_EN# 2 1
+3VS +3VALW_EC +3VALW_EC_VCCA
RE21 10K_0402_5%
1 2 VCOREVCC
CE12 0.1u_0201_10V6K EC_ON 1 2100K_0402_5%
RE712

0.1u_0201_10V6K
VCCRTC FBE36 VCCRTC_EC 1

CE13
BLM15PX121SN1D_2P
1 2 SIGN_LED# 2 1
@ RE713 10K_0402_5%
1 2 2
LED@
RE188 0_0402_5%

D10
K10
D4
D5
UE1

K5

K4
E4

E9
J4

J5
VBAT
for register keep +3VS

VBAT

VCORE

VCC

VSTBY1
VSTBY2
VSTBY3
VSTBY4
VSTBY5
VSTBY(PLL)

AVCC
@
EC_USB20_P6 2 1
RE691 1.5K_0402_5%
EMC_NS@ 2 1 PCH_PCI_CLK EC_SMB_CLK3 1 4
RE254 33_0402_5% EC_KBRST# H4 M5 EC_SMB_DAT3 2 3
7 EC_KBRST# EC_INT_SERIRQ KBRST#/GPB6 PWM0/GPA0 EC_ON_1.8V 34,35
1 G2 N5 @
7,26 EC_INT_SERIRQ SERIRQ/GPM6 PWM1/GPA1 SIGN_LED# PCH_THS_RST#_EC 28
7,26 LPC_FRAME# H1 M6 2.2K_0404_4P2R_5% RPE203
CE339 H2 LFRAME#/GPM5 PWM2/GPA2 N6 EC_VOL_UP# EC_SMB_CLK0 1 4
7,26 LPC_AD3 LAD3/GPM3 PWM3/GPA3 EC_VOL_UP# 28 EC_SMB_DAT0
10P_0402_50V8J J1 PWM K6 RE219 1 8396@ 2 0_0402_5% 2 3
2 EMC_NS@ 7,26 LPC_AD2 LAD2/GPM2 PWM4/GPA4 PM_I2C_SCL1 9,28
J2 J6 RE225 1 8396@ 2 0_0402_5%
7,26 LPC_AD1 LAD1/GPM1 PWM5/GPA5 PM_I2C_SDA1 9,28
K1 M7 2.2K_0404_4P2R_5% RPE202
7,26 LPC_AD0 PCH_PCI_CLK LAD0/GPM0 PWM6/SSCK/GPA6 EC_SUS_VCCP EC_BEEP 23
7 PCH_PCI_CLK K2 LPC K7
LPCCLK/GPM4 PWM7/RIG1#/GPA7 EC_VOL_DOWN# EC_SUS_VCCP 12,34 EC_INT_SERIRQ
WRST# L1 C2 1 4
WRST# TMRI0/GPC4 EC_SUSP EC_VOL_DOWN# 28 EC_KBRST#
L2 E1 2 3
8 EC_VCCST_PWRGD EC_RX ECSMI#/GPD4 TMRI1/GPC6 EC_SUSP 27
M2 RPE205 10K_0404_4P2R_5%
21 EC_RX PWUREQ#/BBO/SMCLK2ALT/GPC7
+3VALW_EC 0_0402_5% M1 G10
21 EC_TX LPCPD#/GPE6 ADC0/GPI0 VR_CPU_PWROK 36 EC_MUTE#
8,21,22,24,26 PCH_PLT_RST# 1 2 M4 G13 2 @ 1
EC_SCI# LPCRST#/GPD2 ADC1/GPI1 BATT_TEMP NTC_V 26
RE217 N4 G12 RE179 10K_0402_5%
4,9 EC_SCI# LID_PAD# ECSCI#/GPD3 ADC2/GPI2 BATT_TEMP 32 EC_SCI#
26 LID_PAD# F1 ADC F9 2 1
GA20/GPB5 ADC3/GPI3 EC_WC_EN# 32
1
RE220
100K_0402_5%

C F13 DOCK_DET# 0_0402_5% RE206 10K_0402_5% C

IT8586VG/AX ADC4/GPI4 DOCK_DET# 28
1

F10 1 2 EC_SENSOR_INT 2 8396@ 1

ADC5/DCD1#/GPI5 VR_ADP_I 32
DE23 F12 RE13 @1 TP152 RE180 10K_0402_5%
RB751V-40_SOD323-2
@ J12
VFBGA128 ADC6/DSR1#/GPI6
ADC7/CTS1#/GPI7
E13
0_0402_5%
USB_ID_N 32 EC_LID_OUT# 2 1
2

J13 KSI0/STB# D12 1 2 RE207 10K_0402_5%

SUSPWRDNACK 8
2

J9 KSI1/AFD# DAC2/TACH0B/GPJ2 C13 RE216 @1 TP157

WRST# H12 KSI2/INIT# DAC3/TACH1B/GPJ3 B13 EC_PROCHOT#
KSI3/SLIN# DAC DAC4/DCD0#/GPJ4
H9 C12 PCH_BKLT_EN PCH_BKLT_EN 4,17 EC_RSMRST#_R 1 8
KSI4 DAC5/RIG0#/GPJ5
1U_0201_6.3V6-K
CE20

1 H10 EC_SUSP 2 7
EC_I2CDATA H13 KSI5 A11 EC_RTCRST_ON EC_SYS_PWROK 3 6
EC_I2CCLK G9 KSI6 PS2CLK0/TMB0/CEC/GPF0 B11 EC_PCH_PWROK 4 5
KSI7 PS2DAT0/TMB1/GPF1 EC_SMB_CLK0 EC_PBTN_OUT# 8
M8 A10 RPE5 10K_0804_8P4R_5%
2 KSO0/PD0 GPF2 EC_SMB_DAT0 EC_SMB_CLK0 26Thermal
J7 Int. K/B PS2 B10
KSO1/PD1 GPF3 EC_SMB_DAT0 26Sensor
N9 Matrix D9 @1 TP141
M9 KSO2/PD2 PS2CLK2/GPF4 B9 RE226 1 8396@ 2 0_0402_5%
KSO3/PD3 PS2DAT2/GPF5 EC_SENSOR_INT 9 EC_VR_EN
K8 1 4
J8 KSO4/PD4 A9 @1 TP139 EC_VCCST_PWREN 2 3
KSO5/PD5 EXTERNAL SERIAL FLASH GPH3/ID3
+3VL +3VALW_EC N10 B8 @1 TP149 RPE206 10K_0404_4P2R_5%
M10 KSO6/PD6 GPH4/ID4 A8 EC_USB20_N6 RE214 1 @ 2 0_0402_5%
KSO7/PD7 GPH5/ID5 EC_USB20_P6 USB20_N6 9
N11 B7 RE215 1 @ 2 0_0402_5%
KSO8/ACK# GPH6/ID6 USB20_P6 9
K9 0_0402_5%
KSO9/BUSY
1

1
RE221
100K_0402_5%

RE223
100K_0402_5%

N12 A7 EC_SPI_CS0# 1 2 0_0402_5%

KSO10/PE NC1 EC_SPI_SI PCH_SPI_CS0# 7
@ N13 B6 RE15 1 2 0_0402_5%
KSO11/ERR# NC2 EC_SPI_SO PCH_SPI_SI 7
M13 SPI Flash ROM A6 RE17 1 2 0_0402_5% PCH_SPI_SO 7
L12 KSO12/SLCT NC3 B5 EC_SPI_CLK RE19 1 2 EC_SUS_VCCP 2 1
KSO13 NC4 PCH_SPI_CLK 7
L13 RE20 RE14 10K_0402_5%
2

K12 KSO14
TP155 1@ K13 KSO15 A4 EC_ACIN# PCH_BKLT_EN 1 2
GPG2 EC_LID_OUT# J10 KSO16/SMOSI/GPC3 AC_IN# A3 LID_SW#
28 EC_LID_OUT# KSO17/SMISO/GPC5 UART LID_SW# LID_SW# 26
RE52 100K_0402_5%

28 EC_ONOFF_BTN# EC_ONOFF_BTN# B4 A13 EC_SYS_PWROK EC_SYS_PWROK 8

PWRSW# EGAD/GPE1
1
RE222
100K_0402_5%
UNMIRROR@

EC_ON 1 @ 2 0_0402_5% A2 SM Bus A12 DDR_PWRGD 35

RE228 EC_SMB_CLK1 B3 XLP_OUT EGCS#/GPE2 B12 DCIN_USB_EN
32 EC_SMB_CLK1 EC_SMB_DAT1 SMCLK1/GPC1 EGCLK/GPE3 DCIN_USB_EN 32
BATT charger32 B2
EC_SMB_DAT1 SMDAT1/GPC2 BATT_TEMP
1 2PECI B1 GPIO D13 RE227 1 2 0_0402_5% 1 2
5 CPU_PECI SMCLK2/PECI/GPF6 GPJ1 EC_ON 33,35
RE18 43_0402_5% C1 E7 GPG2 EMC_NS@ CE17 100P_0201_25V8J
8 EC_PCH_PWROK
2

E8 SMDAT2/PECIRQT#/GPF7 SSCE0#/GPG2 E6
26 EC_SMB_CLK3 CRX1/SIN1/SMCLK3/GPH1/ID1 SSCE1#/GPG0 EC_PCH_ACIN 8
Sensor D7 D6
B 26 EC_SMB_DAT3 CTX1/SOUT1/SMDAT3/GPH2/ID2 DSR0#/GPG6 EC_SYSON PCH_ME_PROTECT 7 B
A5
DTR1#/SBUSY/GPG1/ID7 EC_BKLT_EN EC_SYSON 27,35
20MIL D1
CRX0/GPC0 POGO_EN# EC_BKLT_EN 17
GPG2 0_0402_5% D2
CTX0/TMA0/GPB2 POGO_EN# 28
*H MIRROR CODE EN +3VL 1 2 A1
VSTBY0 RI1#/GPD0
N1
PCH_SLP_S3# 8
L MIRROR CODE DISABLE RE202 EC_MUTE# E2 N3
23 EC_MUTE# GPE4 RI2#/GPD1 PCH_SLP_S4# 8
WAKE UP E12
TACH2/GPJ0 EC_VR_EN PCH_SLP_S0# 8,12
M12
TACH1A/TMA1/GPD7 VCCIO_PWRGD EC_VR_EN 36
M11
EC_X1 EC_USB_ON# TACH0A/GPD6 VCCIO_PWRGD 34
N7 M3
19,32 EC_USB_ON# GINT/CTS0#/GPD5 L80LLAT/GPE7 EC_VCCST_PWREN 12
@ N8 GPIO N2
EC_X2 27 PCH_PWREN# RTS1#/GPE5 L80HLAT/BAO/GPE0 WWAN_RESET# 21
2 1 1 2EC_RSMRST#_R D8
8 EC_RSMRST# CLKRUN#/GPH0/ID0
RE8 RE218 100_0402_5%
1

10M_0402_5%
EC_X1 R3040
RE707 G1
CK32KE/GPJ7
WWAN_RESET# need to be configured as OD. 100_0402_5%
@ 470K_0402_5% EC_X2 F2 Clock SIGN_LED# 1 2 1 2
CK32K/GPJ6 MIPI_WLED_LED 22,28
D4018
YE1 @ SDM10U45LP-7_DFN1006-2-2
2

1 2 LED@
RE182 LED@
32.768KHZ_12.5PF_200458-PG14 10K_0402_5%
AVSS

@
VSS1

VSS2
VSS3
VSS4
VSS5
VSS6
18P_0402_50V8J

18P_0402_50V8J
CE21

CE22

2 2
2

@ @
E5

H5
F4
F5
G4
G5

E10

IT8586VG-AX_VFBGA128
1 1

JECBUG ME@
EC_AGND EC_I2CDATA RE24 1 2 0_0402_5% 1 5
EC_I2CCLK RE25 1 2 0_0402_5% 2 1 GND1
3 2
@
4 3 6
@
4 GND2
TP136 1@
+3VALW_EC TP137 1@ ACES_50208-00408-001
WRST# @1 TP133 TP138 1@
0_0402_5% EC_SMB_CLK1 @1 TP134
2
RE587
10K_0402_5%

1 2 EC_SMB_DAT1 @1 TP135
A 32,36 VR_HOT# RE16 A
@ For off -li ne pr ogr a mm i ng烧
烧 EC cod
e
RTC_RST# 8 CPU_PROCHOT# 5 KSI-6 (pin-H13 --> I2C_DATA)
1

EC_ACIN# 2 1 KSI-7 (pin-G9 --> I2C_CLK)

RE262 QE3 QE1 SMDAT0/GPF3(pin-B10)
0_0402_5% DMG1012T-7_SOT523-3 DMG1012T-7_SOT523-3
EC_RTCRST_ON 2 EC_PROCHOT# 2 SMCLK0/GPF2(pin-A10)
1

QE4
3

3
1

DMG1012T-7_SOT523-3
2 2 1 VR_ACIN 32 RE50 Title
RE203 100K_0402_5% Security Classification LC Future Center Secret Data
@ 1K_0402_5%
Issued Date 2014/11/15 Deciphered Date 2013/11/08 ECT8386
3

@
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Miix4
Date: Monday, August 17, 2015 Sheet 25 of 37
5 4 3 2 1
 5 4 3 2 1

TPM +3VS +3VS_TPM G-SENSOR

R112 1 2 0_0603_5%
20mA
+3VALW TPM@
+3VS +3VS_GSR 0_0402_5%
2 1 0_0603_5% 1 2 EC_SMB_CLK3_R
9 PM_I2C_SCL0

0.1u_0201_10V6K
R3035 0_0603_5% 1 2 R222
@ 1 20mA R117 R221 1 @ 2 0_0402_5%
25 EC_SMB_CLK3

C139
TPM@ R219 1 @ 2 0_0402_5% UG25
1 1 25 EC_SMB_DAT3

CG3382
0.1u_0201_10V6K

CG3383
0.1u_0201_10V6K
0_0402_5% 1 12 +3VS_GSR
2 1 2 EC_SMB_DAT3_R 2 SDO SCx 11
9 PM_I2C_SDA0 SDx PS
R224 0_0402_5% 10
2 @2 +3VS_GSR G_INT1 1 2 G_INT1_R 5 CSB
9 G_INT1 INT1
R233 6 9
+3VS_TPM 3 INT2 GND 8
D
7 VDDIO GNDIO 4 D
VDD NC
UTPM1
1 24 BMA222E_LGA12_2X2
2 NC_1 VDD3 10
3 NC_2 VDD1 TPM@
7 NC_3 28 R113 1 2 10K_0402_5%
PP LPCPD# 27
SERIRQ EC_INT_SERIRQ 7,25 0416 update
6 26
NC_4 LAD0 LPC_AD0 7,25
9 23
NC_7 LAD1 LPC_AD1 7,25
22
LFRAME# LPC_FRAME# 7,25
4 20
GND_1 LAD2 LPC_AD2 7,25
11 17
GND_2 LAD3 LPC_AD3 7,25
18
GND_3 25
R3036 1 2 0_0603_5%5 GND_4 21 R115 1 2 0_0402_5%
NC_5 LCLK PCH_TPM_CLK 7
8 19 +3VS_TPM
12 NC_6 VDD2 15 R116 1 2 0_0402_5%
NUVOTON@
13 NC_8 CLK_RUN#
+3VALW 14 NC_9 16
NC_10 LRESET# PCH_PLT_RST# 8,21,22,24,25

Z32H320TC-LPC-T28-LT1_TSSOP28
NATIONZ@
Light Sensor 0_0402_5%
PM_I2C_SCL0 1 2
EC_SMB_CLK0_R 28
R228
EC_SMB_CLK3 R227 1 @ 2 0_0402_5%

EC_SMB_DAT3 R225 1 2 0_0402_5%

@ 0_0402_5%
PM_I2C_SDA0 1 2
EC_SMB_DAT0_R 28
R229

C C

P Sensor

+1.8VS +1.8VS_PSENSOR
THM Sensor REMOTE1+ R126 0_0402_5%
1 1 2
20mA
C451
+3VS +3VS_TSR 2200P_0402_50V7K
0_0603_5% 2 REMOTE1-

2
1 2 4.7NH_HCI1005F-4N7S-M8_30%
20mA R122 Close U35
REMOTE2+
1 1 PSENSOR@
L4
C658 PSENSOR@ C1962

1
2200P_0402_50V7K +3VS_TSR 3.9P_0402_50V8-B
2 2 1
+3VS_TSR

C183
.1U_0402_10V6-K
REMOTE2- PSENSOR@ 1
C1961 U102 PSENSOR@
L2 2.7P_0402_50V9-B
U35 330_0402_5%
1 2 1 2 2 1
28 PSENSOR_CRX P0.1
1

2 4 2 +1.8VS_PSENSOR
10mA P0.2 VCCD
1 10 EC_SMB_CLK0 R625 R624 100NH_LQW18ANR10J00D_5% R3033 3
VCC SCL EC_SMB_CLK0 25 P0.4
10K_0402_5% 10K_0402_5% PSENSOR@ PSENSOR@ 8
P0.6
C1934
1U_0402_6.3V6K

C180
.1U_0402_10V6-K

1 1 REMOTE1+ 2 9 EC_SMB_DAT0 @ @ 5
DP1 SDA EC_SMB_DAT0 25 P_IRQ P_IRQ_R VDDIO
R252 1 2 0_0402_5% 9
7 P_IRQ PSoC
2

REMOTE1- 3 8 THM_ALERT# 10 P1.1

DN1 ALERT# 11 P1.2 6
PSENSOR@
B 2 2 REMOTE2+ 4 7 THM_SHDN# 12 P1.3 VDD B
DP2 THERM# P1.6

C181
.1U_0402_10V6-K

C182
.1U_0402_10V6-K

C1937
1U_0402_6.3V6K
21 P_IRQ_R 1 1 1
REMOTE2- 5 6 +1.8VS_PSENSOR 13 7
DN2 GND 14 P1.7 VSS PSENSOR@
@ 9 PM_I2C_SDA4 P3.0
15 @
New Part 9 PM_I2C_SCL4
16 P3.1 17 2 2 2
SMBus address: 1001_101xb P3.2 Thermal_GND
1

F75303M_MSOP10 1

2200P_0402_50V7K
external diode:2 R630

C1953
PSENSOR@ 10K_0402_5% PSENSOR@ CY8C4014LQI-421_QFN16_3X3
Product ID: 21h PSENSOR@
Close to memory side 2
2

REMOTE1+ P_IRQ_R PSENSOR@

1
1

C
C982 2 Q137 R631
100P_0402_50V8J B @ 10K_0402_5%
2 @ E
3

REMOTE1- MMBT3904WH_SOT323-3
2

+3VL +3VALW
1

Close to CPU side

R627 R629 Hall Sensor
REMOTE2+ 13.7K_0402_1% 13.7K_0402_1%
@ +3VALW_HSR
1 U40
1

C
2

C984 2 Q138 LID_SW# 4 3

100P_0402_50V8J B 25 LID_SW# Out1 Vdd
2 @ E +3VALW_HSR
3

REMOTE2- MMBT3904WH_SOT323-3 2 0_0402_5%

1

C204 LID_PAD# 1 2 1 2
25 LID_PAD# Out2 Gnd
RH101 .1U_0402_10V6-K R223
REMOTE2+/-: +3VL 20mA @ 2 HGDEDM011A_MAP4_1P1X0P9
2

100K_0402_1%_TSM0B104F4251RZ 1 C197
Trace width/space:10/10 mil 2
R628 2 1 .1U_0402_10V6-K C193
Trace length:<8"
2

A 0_0402_5% R132 0_0603_5% 1 @ .1U_0402_10V6-K A

1
C195
0.1u_0201_10V6K

1
@
1

2
25
NTC_V

Security Classification LC Future Center Secret Data Title

Issued Date 2014/11/15 Deciphered Date 2013/11/08 CONN(THM&FAN&RTN&SPKR&TP)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Miix4
Date: Monday, August 17, 2015 Sheet 26 of 37
5 4 3 2 1

REMOTE2+/-:
Trace width/space:10/10 mil
Trace length:<8"
 5 4 3 2 1

+1.8VALW +1.8VS

1 AON7408L_DFN8-5 1
C226 Q12 C227
0.1U_0402_16V4Z @ @ 0.1U_0402_16V4Z +5VALW +5VLP
2 1 2
5 S1 2
D S2

1
3
S3

1
R231 R234

470_0603_5%
R69
100K_0402_5% 100K_0402_5%
@

4
B+ R68

2
@

2
1 2 SUSP#
SUSP# 18
+5VALW
D D
Enable: 100K_0402_5% 6 6 6

0.01U_0402_25V7K
VIH=1.2V~5.5V

C58
1 Q163A 1 REV@ Q164A Q16A
VIL=0~0.4V
AO5804EL_SC89-6
C112 +5VS SUSP# 2 2 SUSP# 2 EC_SUSP
1U_0402_10V6K EC_SUSP 25
U56
2 1 14 AO5804EL_SC89-6 2 AO5804EL_SC89-6
VIN1_1 VOUT1_2 1
2 13 C216
0_0402_5% VIN1_2 VOUT1_1 .1U_0402_10V6-K 1 1 1
EC_SUSP 1 2 3 12 5VS_CT1
R264 EN1 SS1 2
@
4 11
0_0402_5% BIAS GND
1 2 5 10 3VS_CT2
R265 +3VALW EN2 SS2 +3VS
0.01U_0402_25V7K
C114 @

1 6 9 +5VALW +5VLP
7 VIN2_1 VOUT2_2 8 +1.8VALW +DDR_1.8V
VIN2_2 VOUT2_1 1
1 C215
15 @ .1U_0402_10V6-K
GPAD

1
2 C113 @
1U_0402_10V6K G5016KD1U TDFN 2 AON7408L_DFN8-5 R230 R236
2 1 1
C232 Q13 C238 100K_0402_5% 100K_0402_5%
0.1U_0402_16V4Z @ @ 0.1U_0402_16V4Z
0522 new symbol for haydn .

2
2 1 2
5 S1 2 SYSON#
D S2 3
S3

1
3

470_0603_5%
R72
5VS_CT1 3VS_CT2
1000P_0402_50V7K

1000P_0402_50V7K
Q16B

4
1 1 B+ AO5804EL_SC89-6
C101

C102

@
R71 @ 5
EC_SYSON 25,35

2
1 2
2 2 Q164B
100K_0402_5% 3 3 4

0.01U_0402_25V7K
C59
Q163B 1 REV@
C C
SYSON# 5 5 SYSON#

AO5804EL_SC89-6 2 AO5804EL_SC89-6
4 4

+3VALW +3VALW_PCH

R25 1 2 0_0603_5%

+3VALW_PCH

+3VALW
1
@
Q23 @ C219
LP2301ALT1G_SOT23-3 .1U_0402_10V6-K
2
S

3 1
.1U_0402_10V6-K
C37

C30 @
0.01U_0402_25V7K
G

1 1
2
@

2 2

B PCH_PWREN# B
2 1
25 PCH_PWREN#
R11
@ 10K_0402_5% 1
C441
.1U_0402_10V6-K
1

R238 @
@ 2
470K_0402_5%
2

+5VS +3VS +DDR_0.6VS

+DDR_1.2V
2

@ R257 @ R245 @ R247

22_0402_5% 22_0402_5% 22_0402_5% @ R246
22_0402_5%
R118
1

SUSP# 1 2 0_0402_5%
1

REV@ 6 3 6 3
REV@ REV@
REV@ Q165A Q165B Q166A Q166B
AO5804EL_SC89-6 AO5804EL_SC89-6 AO5804EL_SC89-6 AO5804EL_SC89-6
2 5 2 SYSON# R12 1 2 0_0402_5%
5

REV@ REV@

A
1 4 1 4 A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/11/15 Deciphered Date 2013/11/08 POWER SWITCH
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Miix4
Date: Monday, August 17, 2015 Sheet 27 of 37
5 4 3 2 1
 5 4 3 2 1

IO Conn +3VS +3VS_THS +3VS +3VS_DMIC +3VS +3VS_LSR BUTTON

0_0603_5% Vol up/down button SW1
0_0603_5% 1 2
2 1 1 2 R131 1 1 2
25 EC_VOL_UP# 1 2

C196
0.1u_0201_10V6K
R22 0_0603_5% R34 20mA

0.1u_0201_10V6K

0.1u_0201_10V6K
R3042 1 2 0_0402_5% 1 500mA(Max: 300mA) 1 @ 3 4
GND1 GND2

C31

C34
EXC24CH900U_4P
500mA(Max: 300mA) 2
@ @ TESTPAD TP37 1 5
USB20_N3 4 3 USB20_N3_CON GND3
9 USB20_N3 4 3 2 2
EMC_NS@ EVPAKB11A_3P
USB20_P3 1 2 USB20_P3_CON
9 USB20_P3 1 2
L83 C1935 1 2 220P_0402_50V7K
R3043 1 2 0_0402_5%
D4001
1 2
D 1 2 D
EMC_NS@
AZ5725-01F_DFN1006P2X2

WIRELESS_IN
ME@ ME@
JPOGO JDEBUG
13 ISH_I2C0_SCL 1
GND1 9 ISH_I2C0_SCL ISH_I2C0_SDA 1
1 2
1 9 ISH_I2C0_SDA ISH_I2C1_SCL 2
2 3
2 9 ISH_I2C1_SCL ISH_I2C1_SDA 3
3 4
4 3
4
9 ISH_I2C1_SDA
5 4
5
Vol up/down button SW2
5 ISH_GP0 6
5 9 ISH_GP0 ISH_GP6 6
6 7 25 EC_VOL_DOWN# 1 2
USB20_N3_CON 6 9 ISH_GP6 7 1 2
+3VALW_POGO 7 8
USB20_P3_CON 8 7 9 8 3 4
9 8 10 9 GND1 GND2
10 9 11 10 1 5
10 11 TESTPAD TP38 GND3
11 12
11 12
0.1u_0201_10V6K

25 DOCK_DET# 12 13
12 14 14 13 EVPAKB11A_3P
1 GND2 14
2

C1974

+3VS 15
C1975 16 15 20
ELCO_046809612X10846+ 16 GND_PAD2
0.22U_0402_10V6K 17 19
1

2 18 17 GND_PAD1 C1936 1 2 220P_0402_50V7K

EMC@ 18

EMC@ ELCO_006238018410846+
D4002
1 2
+3VS_THS 1 2
ELCO_046809610X10846+ EMC_NS@
AZ5725-01F_DFN1006P2X2
slave address:0x10 12
GND2 JAUDIO ME@
10 7
9 10 1 GND1
C C
9,25 PM_I2C_SDA1 9 HP_L_CON 1
9,25 PM_I2C_SCL1 8 23 HP_L_CON 2
R127 7 8 HP_R_CON 3 2
9 THS_IRQ 7 23 HP_R_CON 3
9 PCH_THS_RST# 1 2 0_0402_5% 0_0402_5% 6 23 HPOUT-JD HPOUT-JD 4
EC_LID_OUT# 1 2 5 6 SLEEVE 5 4
25 EC_LID_OUT# 5 23 SLEEVE 5
R128 17 PANEL_DE RE224 4 6
1 2 0_0402_5% 3 4 6 8
25 PCH_THS_RST#_EC
2 3
2
GND2 ON/OFF button SW3
@ 1 ELCO_046809606X10846+
1 1 2
25 EC_ONOFF_BTN# 1 2
11 AUDIO_AGND
GND1 3 4
lid off touch disable ME@ GND1 GND2
JTHS
TESTPAD TP39 1 5
GND3

EVPAKB11A_3P

C1939 1 2 220P_0402_50V7K

D4003
1 2
+MIPI_WLED 1 2
ME@ EMC_NS@
JLED CVILU_CI4202M2HRD-NH
AZ5725-01F_DFN1006P2X2
13
1 GND1 4
2 1 2 GND2
2 26 PSENSOR_CRX 2
22 3 MIPI_WLED_DRV1
4 3 1
+MIPI_VDD 5 4 1 3
22 MIPI_WLED_NTC 5 GND1
6
+3VS_LSR 22,25 MIPI_WLED_LED
7 6
JPSEN
8 7 ME@
9 8 Configure PU PD Voltage POGO_EN# +3VALW_POGO
26 EC_SMB_CLK0_R 9
0_0402_5% 10
26
B EC_SMB_DAT0_R G_INT2 G_INT2_R11 10 B
1 2
9 G_INT2
R239 12 11 No docking
12 14
100K NC 3.3V 3.3V 0V
GND2

ELCO_046809612X10846+ KB and TP enable

+3VALW +3VALW_POGO 100K 300K 2.475V 0V 3.3V

LP2301ALT1G_SOT23-3
KB and TP disable(0-15 degree)
100K 300K 2.475V 3.3V 0V
S

QC40 3 1
KB and TP disable(345-360 degree)
0.1u_0201_10V6K

0.1u_0201_10V6K
1 1 100K 300K 2.475V 3.3V 0V
2

+3VS_DMIC
CC1074

CC1075
@ @
G
2

RC296
JMIC ME@
10K_0402_5% KB and TP disable after calculate angle 150K
5 2 2
GND1 0_0402_5%
100K 1.98V 0V 3.3V
1

1 1 2
1 25 POGO_EN#
23 DMIC_CLK 2 RC294
3 2 @
23 DMIC_DATA 3
1

0.1u_0201_10V6K

4 1
4
CC1076

R248
6 @ 470K_0402_5%
GND2
2 Configure PU PD Voltage
ELCO_046809604X10846+
2

HPOUT-JD
No docking
100K NC 3.3V
HP_R_CON
DOCK_DET# +3VALW_POGO WIRELESS_IN
HP_L_CON 10W CHG Docking
AZ5215-01F_DFN1006P2E2

AZ5215-01F_DFN1006P2E2

100K 50K 1.1V

SLEEVE USB20_N3_CON EMC@
AZ5215-01F_DFN1006P2E2

AZ5215-01F_DFN1006P2E2

AZ5215-01F_DFN1006P2E2

AZ5215-01F_DFN1006P2E2

20W CHG Docking

2

A USB20_P3_CON A
100K 83K 1.496V
EMC@
EMC_NS@

EMC_NS@

EMC_NS@
AZ5725-01F_DFN1006P2X2

AZ5725-01F_DFN1006P2X2

AZ5725-01F_DFN1006P2X2

AZ5725-01F_DFN1006P2X2
DA10

DA11
DA7

DA9
2

1
1

EMC_NS@
AZ5215-01F_DFN1006P2E2

D4016
D13
1

2
1

D4017

2
D4019

D4020
D11

D12
1

2
2

EMC@ Title
EMC_NS@ EMC@ Security Classification LC Future Center Secret Data
EMC@
EMC_NS@
Issued Date 2014/11/15 Deciphered Date 2013/11/08 Screw and Hole
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Miix4
Date: Monday, August 17, 2015 Sheet 28 of 37
5 4 3 2 1
 5 4 3 2 1

PAD_C4P0D2P2 PAD_CT3P2B2P8D1P6
H19 H8 H17 PAD_CT3P6B3P8D2P6
HOLEA HOLEA HOLEA H20 H21 H24 H22
HOLEA HOLEA HOLEA HOLEA PAD_D2P0X0P5
FD1 FD2 FD3 FD4 FD5 FD6 H25 H26 H27
HOLEA HOLEA HOLEA

1
1

1
PAD_C4P0D2P2 PAD_CT3P2B2P8D1P6 PAD_CT3P2B2P8D1P7
PAD_CT3P6B3P8D2P6 PAD_CT3P6B3P8D2P6 PAD_CT3P6B3P8D2P6 PAD_CT3P6B3P8D2P6
PAD_C4P0D2P2 PAD_D2P0X0P5 PAD_D2P0X0P5 PAD_D2P0X0P5
H1 H3 H4 H6 H9 H10 H13 H14 H15 H18 H23
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
1

1
PAD_C4P0D2P2 PAD_C4P0D2P2 PAD_C4P0D2P2 PAD_C4P0D2P2 PAD_C4P0D2P2 PAD_C4P0D2P2 PAD_C4P0D2P2 PAD_C4P0D2P2 PAD_C4P0D2P2 PAD_C4P0D2P2 PAD_C4P0D2P2

Height 1.0 Height 1.8

SH65 SH78
SH1 SH15
1 1
1 1 1 1
1 1 Height 0.6
SHIEDING_10X1P5X1P0_1P SHIEDING_10X1P5X1P0_1P
SHIELDING_10X1P5X1P8_1P SHIELDING_10X1P5X1P8_1P
D SH47 SH59 D
SH67 SH79 SH193
SH3 SH31 1 1
1 1 1 1 1
1 1 1 1 1
1 1 SHIELDING_10X1P5X0P6_1P SHIELDING_10X1P5X0P6_1P
SHIEDING_10X1P5X1P0_1P SHIEDING_10X1P5X1P0_1P SHIELDING_10X1P5X0P6_1P
SHIELDING_10X1P5X1P8_1P SHIELDING_10X1P5X1P8_1P
SH66 SH81
SH4 SH16 SH36 SH48 SH61
1 1 SH183 SH194
1 1 1 1 1 1 1
1 1 1 1 1 1 1
SHIEDING_10X1P5X1P0_1P SHIEDING_10X1P5X1P0_1P 1 1
SHIELDING_10X1P5X1P8_1P SHIELDING_10X1P5X1P8_1P SHIELDING_10X1P5X0P6_1P SHIELDING_10X1P5X0P6_1P SHIELDING_10X1P5X0P6_1P
SHIELDING_10X1P5X0P6_1P SHIELDING_10X1P5X0P6_1P
SH68 SH83 SH49
SH5 SH18
1 1 1
1 1 1 1 1
1 1
SHIEDING_10X1P5X1P0_1P SHIEDING_10X1P5X1P0_1P SHIELDING_10X1P5X0P6_1P
SHIELDING_10X1P5X1P8_1P SHIELDING_10X1P5X1P8_1P

SH29 SH84 SH50 SH62

SH6 SH19 SH172 SH184
1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1
SHIEDING_10X1P5X1P0_1P SHIEDING_10X1P5X1P0_1P SHIELDING_10X1P5X0P6_1P SHIELDING_10X1P5X0P6_1P
SHIELDING_10X1P5X1P8_1P SHIELDING_10X1P5X1P8_1P SHIELDING_10X1P5X0P6_1P SHIELDING_10X1P5X0P6_1P
SH85
SH24
1 SH32 SH39 SH51 SH63
1 1
1 1 1 1 1
SHIEDING_10X1P5X1P0_1P 1 1 1 1
SHIEDING_10X1P5X1P0_1P
SHIELDING_10X1P5X1P8_1P SHIELDING_10X1P5X0P6_1P SHIELDING_10X1P5X0P6_1P SHIELDING_10X1P5X0P6_1P
SH87

1
1 SH9 SH22 SH34 Length 10
SH74 SH40 SH52 SH64
1 1 1 SH174
1 SHIEDING_10X1P5X1P0_1P 1 1 1 1 1 1
1 1 1 1 1
SHIELDING_10X1P5X1P8_1P SHIELDING_10X1P5X1P8_1P SHIELDING_10X1P5X1P8_1P 1
SHIEDING_10X1P5X1P0_1P SH86 SHIELDING_10X1P5X0P6_1P SHIELDING_10X1P5X0P6_1P SHIELDING_10X1P5X0P6_1P
SHIELDING_10X1P5X0P6_1P
1 SH41 SH54
SH75 1 SH176 SH188
1 1
1 SHIEDING_10X1P5X1P0_1P 1 1 1 1
1 1 1
SHIELDING_10X1P5X0P6_1P SHIELDING_10X1P5X0P6_1P
SHIEDING_10X1P5X1P0_1P SH88 SHIELDING_10X1P5X0P6_1P SHIELDING_10X1P5X0P6_1P

SH76 1 SH42 SH53

1
1 1 1
1 SHIEDING_10X1P5X1P0_1P 1 1

SHIEDING_10X1P5X1P0_1P SHIELDING_10X1P5X0P6_1P SHIELDING_10X1P5X0P6_1P

SH56
SH77
1
1 1
1
SHIELDING_10X1P5X0P6_1P
SHIEDING_10X1P5X1P0_1P
SH12 SH25

1 1 SH44 SH55
1 1 SH177
1 1
SHIELDING_10X1P5X1P8_1P SHIELDING_10X1P5X1P8_1P 1 1 1
1
SH13 SH26 SHIELDING_10X1P5X0P6_1P SHIELDING_10X1P5X0P6_1P
C SHIELDING_10X1P5X0P6_1P C
1 1 SH45 SH57
1 1
1 1
SHIELDING_10X1P5X1P8_1P SHIELDING_10X1P5X1P8_1P 1 1

SHIELDING_10X1P5X0P6_1P SHIELDING_10X1P5X0P6_1P

SH46 SH58

1 1
1 1

SHIELDING_10X1P5X0P6_1P SHIELDING_10X1P5X0P6_1P

Height 1.0 Height 1.8 Height 0.6

SH91 SH117 SH130 SH156
SH199
1 1 1 1
1 1 1 1 1
1
SHIELDING_5X1P5X1P0_1P SHIEDING_5X1P5X1P8_1P SHIEDING_5X1P5X1P8_1P SHIELDING_5X1P5X0P6_1P
SHIELDING_5X1P5X0P6_1P

SH118 SH131 SH144 SH157

SH200 SH214
1 1 1 1
1 1 1 1 1 1
1 1
SHIEDING_5X1P5X1P8_1P SHIEDING_5X1P5X1P8_1P SHIELDING_5X1P5X0P6_1P SHIELDING_5X1P5X0P6_1P
SHIELDING_5X1P5X0P6_1P SHIELDING_5X1P5X0P6_1P
SH119 SH133 SH145 SH158
SH201 SH213
1 1 1 1 SH226
1 1 1 1 1 1
1 1 1
SHIEDING_5X1P5X1P8_1P SHIEDING_5X1P5X1P8_1P SHIELDING_5X1P5X0P6_1P SHIELDING_5X1P5X0P6_1P 1
SHIELDING_5X1P5X0P6_1P SHIELDING_5X1P5X0P6_1P
SH239 SHIELDING_5X1P5X0P6_1P
SH146 SH159
1 SH202
1 1 1
1 1 1
SHIEDING_5X1P5X1P8_1P 1
SHIELDING_5X1P5X0P6_1P SHIELDING_5X1P5X0P6_1P
SHIELDING_5X1P5X0P6_1P

SH95 SH108 SH121 SH134 SH147 SH160

SH203
1 1 1 1 1 1
1 1 1 1 1 1 1
1
SHIELDING_5X1P5X1P0_1P SHIELDING_5X1P5X1P0_1P SHIEDING_5X1P5X1P8_1P SHIEDING_5X1P5X1P8_1P SHIELDING_5X1P5X0P6_1P SHIELDING_5X1P5X0P6_1P
SHIELDING_5X1P5X0P6_1P
B B
SH96 SH122 SH135 SH148 SH161
SH204
1 SH136 1 1 1 1 SH232
1 1 1 1 1 1

SHIELDING_5X1P5X1P0_1P 1
1
SHIEDING_5X1P5X1P8_1P SHIEDING_5X1P5X1P8_1P SHIELDING_5X1P5X0P6_1P SHIELDING_5X1P5X0P6_1P
1
1
1
Length 5
SHIELDING_5X1P5X0P6_1P
SHIELDING_5X1P5X1P0_1P SH124 SH149 SHIELDING_5X1P5X0P6_1P
SH205
1 1 SH240
1 1 1
1 1
SHIEDING_5X1P5X1P8_1P SHIELDING_5X1P5X0P6_1P 1
SHIELDING_5X1P5X0P6_1P
SHIELDING_5X1P5X0P6_1P
SH98 SH123 SH150
SH163 SH241
1 1 1
1 1 1 1 1
1 1
SHIELDING_5X1P5X1P0_1P SH237
SHIEDING_5X1P5X1P8_1P SHIELDING_5X1P5X0P6_1P
SHIELDING_5X1P5X0P6_1P SHIELDING_5X1P5X0P6_1P
1
1 SH139 SH165
SH140 SH208
SHIEDING_5X1P5X1P8_1P 1 1
1 SH238 1 1 1
1 1
1 SHIEDING_5X1P5X1P8_1P SHIELDING_5X1P5X0P6_1P
SHIELDING_5X1P5X1P0_1P 1 SHIELDING_5X1P5X0P6_1P

SHIEDING_5X1P5X1P8_1P
SH126 SH152
SH235
1 1 SH233
1 1 1
1 1
SHIEDING_5X1P5X1P8_1P SHIELDING_5X1P5X0P6_1P 1
SHIEDING_5X1P5X1P8_1P
SH128 SHIELDING_5X1P5X0P6_1P
SH222
1 SH236
1 1
1 1
SHIEDING_5X1P5X1P8_1P 1
SHIELDING_5X1P5X0P6_1P
SHIEDING_5X1P5X1P8_1P
SH127 SH154
SH138 SH223
1 1
1 1 1 1
1 1
SHIEDING_5X1P5X1P8_1P SHIELDING_5X1P5X0P6_1P
SHIEDING_5X1P5X1P8_1P SHIELDING_5X1P5X0P6_1P

SH129 SH142

1 1
1 1

SHIEDING_5X1P5X1P8_1P SHIEDING_5X1P5X1P8_1P

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/11/15 Deciphered Date 2013/11/08 Screw and Hole
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
E 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Miix4
Date: Monday, August 17, 2015 Sheet 29 of 37

5 4 3 2 1
 5 4 3 2 1

01/06:
1.Change EC to 8386 3/9: 6/17:
2.modify JPOGO pin define . 1.Change JAUDIO to ELCO_046809606X10846+ follow ME Connector list 1.Change D11,D12,D13,D4016,D4017 to AZ5423-01F.R7GR_DFN1006P2E2 follow EMC suggestion.
3.Change U40 to APX8132HAI-TRG_SOT23-3 2.Change JMIC to ELCO_046809604X10846+ follow ME Connector list 2.Change CC4 to 9P_0402_50V8J follow crystal vendor suggestion.
3.Change JTHS to ELCO_046809610X10846+ follow ME Connector list 3.Change RPE683,RPE204 to 100K_0404_4P2R_5%
4.Change JPOGO,JLED to ELCO_046809612X10846+ follow ME Connector list 4.Change RE712 to 100K_0402_5%
5.Change signal MIPI_SDA pull up power plane to +MIPI_VIO1
01/12: 6.Add UC4 ,colay with UC3 For ME height concern.
1.Change EC to 8586 7.Reserve pull down for signal P_IRQ
2.Change U40 to HGDEDM011A_MAP4_1P1X0P9 8.Add pull down resistor for GPP_B22 6/19:
9.change L69,L70,L81,L82 to EXC24CH900U_4P 1.Add CAP CC1981,CD239,CD240,CD241,CD242
10.Change L32,L33,L34,L35,L36 to BLM15PX121SN1D_2P For ME height concern.
01/13:
1.Change U35 to F75303M_MSOP10
D SVT D

3/10:
1.Change JCMOS1 to TP71
01/21: 2. Change EDP power switch to MOS for ME Height concern.
1.Add P senosr part schematic 3.chang DC2,DC3 to UC5,UC6 (74LVC1G08SE-7_SOT353-5) For leakage issue. 7/17:
2.Move light sensor to DB. 4.Change R22,R132,RA18,RA20,RA21,RA25,RA26 to R short for ME height concern 1.Mount C237 and C235 for signal UF_PWRCNTL quality.
5.pull up to +3VALW_EC for signal EC_ON ,POGO_EN# 2..Change C143,C144 to SE00000XO0J
6.add resistor RE262 3.Change C138,C142,C146,CD149,CD150,CD161,CD162,CD167,CD168,CD179,CD182,CD183,
01/26: 7.combine power part schematic CD189,CD190,CD191,CD198,CD199,CD200,CD215,CD216,CD229,CC1080,CC1081,
1.Change Codec to ALC3240-CG_MQFN40_5X5 8.Modify EDP pin define. CC1083,CC1084,CC1085,CC1086,CC1087 to SE00000UD8J

7/30:
01/30: 3/11: 1.Add C1968 and C1969 to solve WF camera garbage issue,.
1.Change JWWAN to ARGOS_NARB0-M6701-TS15 follow ME request. 1.Change L4 to 18NH_HCI1005F-18NJ-M8_5% follow vendor suggestion.
2.pull up +3VALW_EC for signal EC_WC_EN

8/2:
2/3: 3/12: 1.Change Y5 to 20MHZ_6PF_XTL571200-L150-016 follow vendor suggstion.
1.Add o ohm resistor for Power manager signal. 1.Delete CA386,CA387 2.Reserve 0.1uF cap for power +MIPI_VANA2
2.Mount RE207 3.Change RC292 to 0402 size o ohm resistor .
3.combine power part schematic 4.Add 1uF and 0.1uF caps for mipi camera power.
2/9:
1.update UF Camera connector follow ME connector list ,
3/13: 8/3:
1.Modify JPOGO pin define. 1.Change JLVDS to ELCO_046809630310846+ follow ME request .
2.Modify Jmic pin define.
2/11: 3.Combine power part schematic
1.Modify J3D pin define.
2.Reserved ESD component for SIM Card interface.
3.Swap USB2.0 port2,port3 signal for layout concern 8/4:
1.Mount LC37 for SKL 5.67GHz signal noise issue
C 3/16: 2.Add C1974 and C1975 follow EMC suggestion. C
1.change SW1,SW2,SW3 to IPTG14K-Q-T-R_5P follow ME suggestion. 3.Mount Q168 for WWAN reset signal.
2/12: 2.set signal VID0 pull up to +3VALW.
1.Delete Audio jack signal RING2 4.Add TPM_ID1 and TPM_ID2 Signal to identify TPM Mount or not .
2.Swap JLVDS pin define . 5.Change R115,R116，R133,R134,R226
，R240,R243,R250,R2,R3,RE22,R23,R31,RW34,R34,R37,R117,R122,R131,RC269 ,
R3010,RC3028,RC159,RC160,R222,R224,R228,R229,R233,R239,R126,RW3,RW4,RW5,RW6,RW7,RW8,RE13,RE15,RA15,
RE16,RE17,RE19,RE20,RC64,RC88,RC134,RC135,RC139,RC149,RC150,RC151,RC152,RC153,RC154,RE202,RE216,RE217,R223,RE224,
2/13: SIV R244,R251,RC294,R628,RC1491,R3009,,RC3027,RA4,R6,R42,R49,RC62,RC77,RC171,R256,R3014,RE262,R264,R265,R3037
to R short .
1.Change some resistor to R short for layout concern.
2.modify +CPU_VCCSTG and VCCPLL_OC enable control method
3.Swap JTHS,JAUDIO pin define. 4/13:
4.Add hole symbol 1.unmount C193，CW3,C215,C216,CV263 8/5:
CC1197,CC1105,CC1096,CC1103,CC1082, 1.Reserve bead L83 follow EMC request .
CC1111,CC1120 2.Reserve bead L84,L85 follow RF request .
2/14: 3.Combine power part schematic.
1.Modify touch panel signal HSYNC . CC1157,CC1160,CC1169
3.Swap JPOGO pin define. CC1236,CC1229,CC1233
CC1958,CC1965,CC1961,CC1971,CC1974,CC1977
CD154,CD156,CD164,CD225,CD232,CD171,CD201
CC173,CC1132,C230 for components quantity down 8/8:
2/25: 2.Change EDP Part diff signal name. 1.Modify mipi camera schematic.
1.Modify Camera part schematic.

2/26: 4/14:
1.Delete UPI Colay component. 1.move signal EC_SENSOR_INT to GPF5
2.Add JDEBUG connector 2.move signal EC_SCI# to GPP_E8
3.combine power part schematic

4/16:
2/28: 1.Change R3034 to 33 ohm for LCDVCC fall time fail.
B 1.Swap JPOGO, JTHS pin define 2.Change JSPK to ELCO_046809604X10846+ follow ME connector list B
2. Modify Hole size . 3.Change L68,L12,L13,L14,L15 to EXC24CH900U_4P
4.Change SW1,SW2,SW3 to EVPAKB11A_5P follow ME request.

3/2:
1.update RPC28 to 1K_0404_4P2R_5%
2.Add 1.0 height clip. 4/20:
3.Modify Camera part schematic. 1.Change signal EC_VOL_UP# and EC_VOL_DOWN# pull up power plane to +3VALW.
4.combine power part schematic
5.Change CC1150 to 22U_0402_4V6-M
4/23:
1.Reserve GPP_E15 for SCI function
2.Add test point for signal PCH_FLASH__STROBE
3/3: 3.Change YC1 to X1A000141000200 ,CC4 to 8P_0402_50V8J,CC5 to 9P_0402_50V8J follow vendor suggestion
1.Change JDEBUG to ELCO_006238018410846+ 4.Add 0 ohm resistor for JSSD pin69.
2.Change P sensor to cypress solution (CY8C4014LQI-421_QFN16_3X3) 5.Change D11,D12,D13 to AZ5215-01F_DFN1006P2E2 follow EMC suggestion
6.Reserve D4016 follow EMC suggestion
7.Reserve C26,C27,C1967,C1964,C1966,C1965,C32.C33 follow EMC suggestion.
8.Add D4017 follow EMC suggestion
3/4: 9.Change PL105 to EXC24CH900U_4P follow EMC suggestion
1.Add R3015,R3019 for debug function
2.Change L75,L76,L77,L78 to BLM18PG221SN1D_2P

4/25:
3/5: 1.Change R887,R888,RW10,RC46,RC57,R96,R102,RC105,R184,R185,RE188,RA2,RA8,R124,R125,R890,R892,RE23 to R short for components quantity down.
1.Change U30 to SA00007AT10
2.reserve I2C interface for 8396 EC.

3/6: SIT
1.Reserve CD235， CD236,CD237,CD238 Follow EMC suggestion.
A A
2.reserve EC debug connector JECBUG
3.combine power part schematic . 6/8:
1.Reserve Q168 For wwan reset#
2.change R3002 to SD00001KH00
3.Change U56 to SA000067600
3/7: 4.Reserve LED schematic
1.Change QC7 to 2N7002KDWH_SOT363-6

Security Classification LC Future Center Secret Data Title

3/9:
1.Change CA384 to 10U_0402_6.3V6M for ME height concern. Issued Date 2014/11/15 Deciphered Date 2013/11/08 HW_Change_List
2.Change CC192,CC193,CC194,CC191,CC198,CC175,CD165,CD176 to 22U_0402_4V6-M for ME height concern.
3.Change QC7 to AO5804EL_SC89-6 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
4.Change C200 to 10U_0603_25V6-M for ME height concern. C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Miix4
Date: Monday, August 17, 2015 Sheet 30 of 37
5 4 3 2 1
 5 4 3 2 1

+5VLP
Silergy Silergy
SY8286CRAC SY8032ABC
D Converter +5VALW Converter +1.8V D

AC Adapter FOR SYSTEM/LPDDR3

EN FOR SYSTEM PGOOD EN PGOOD

Silergy +3VLP
SY8286BRAC
Converter +3VALW

EN FOR SYSTEM PGOOD

TI
BQ24770RUYR B+ Silergy
SY8210AQVC +1.2V
Battery Charger Converter
Switch Mode
C
+0.6 C

FOR LPDDR3
EN PGOOD

SMBus
MPS
NB682GD VCCIO for Premium only
Converter
Battery EN FOR CPU/PCH PGOOD

Li-ion

MPS
NB682GD PRIM_CORE for Premium only
Converter
B EN FOR CPU/PCH PGOOD B

Silergy
+5VALW SY8104ADC
Converter +1.0VALW

EN PGOOD
FOR CPU/PCH

CPU_CORE

Intersil
ISL95852-HIZ-T GFX_CORE
PMIC
VCCSA
A A
EN
PGOOD

Security Classification LC Future Center Secret Data Title

Issued Date 2014/02/20 Deciphered Date 2014/02/20 NVDC Charger
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. MIXX4
Date: Monday, August 17, 2015 Sheet 31 of 37
5 4 3 2 1
 5 4 3 2 1

V_PATH_R

V_CHG

PR100
1 2

0.1U_0402_25V6
10U_0805_25V6K

10U_0805_25V6K
0.01_1206_LE_0.5%

PC101
ADIN_1

PC161

PC100
V_PATH

2
PJ104
D 2 1 D
ADIN_1 PQ100 +3VL 2 1
AON7754_DFN8-5 PQ101
AON7752_DFN8-5 B+ BATT+_1 JUMP_43X79

1
1 @
2 1 PJ105 PR120
5 3 2 2 1 100K_0402_5%
2 1

5
3 5 R_0402
PR121

2
0.1U_0402_25V6
JUMP_43X79
PC104

4
2
@ 1 2
25 BATT_TEMP

4
1

PC103
PC102 1 2 PQ102

MBAT_PRES#_R
10U_0805_25V6K

10U_0805_25V6K
2200P_0402_50V7K 4 1

1
0_0402_5%

47U_B3_10VM_R45M
0.1U_0402_25V6 AON7400AL_DFN8-5

2
2

1
+

4.7_0402_5%
PC105

PC107

PC181

PC110
PR101
PC106

3
2
1

2
1U_0603_25V7K 2
PR102 BATT+_1
0.1U_0402_25V6

1
1 2 PQ103
AON7405_DFN8-5 PF100 BATT+ JBATT1
1 12A_24V_F1206HB12V024T/M 9
0_0402_5% PL100 PR104
2
8A 1 GND1
6A 1
1

1 2 1 2 BAT_IN 3 5 1 2 2
2

5
0.047U_0402_25V7K
PR103 3
EC_SMCA 3

0.1U_0402_25V6
432K_0201_1% 2.2UH_PCMB061H-2R2MS_6A_20% 0.01_0805_LE_1% 4
4

1
PC108

PC109
EC_SMDA 5

4
VREGN PR189 6 5
RTC_VCC
2

1 6

1
PQ104 2.2_0805_5% PC112 7

2
7

1
ACDET PR105 PR106 4 EMC_NS@ 8
8

1000P_0402_50V7K
4.02K_0402_1% 4.02K_0402_1% PC111 AON7754_DFN8-5 VREGN 10

1 2

2
GND2
1

1U_0603_10V6-K

2
1

CHGVCC
PR107
PR112
2

2
73.2K_0201_1% PR108 PR109 PC162 DRAPH_WS33081-S3101-HF

3
2
1
1
0_0402_5% 0_0402_5% 1000P_0402_50V9-J PR111 BGATE_N 2 1 ME@

2
PR110 EMC_NS@ 383K_0402_1%
2

100_0402_1%
0.1U_0402_25V6

0.1U_0402_25V6
0_0402_5% EMC@

2
0_0402_5%

100_0402_1%

PR114
1

PC115

PR113
PC113

1
PC114
1000P_0201_25V7K

2
2

2
PR115

28

27

26

25

24

23

22

29

2
47K_0402_1%

VCC

PHASE

HIDRV

BTST

REGN

LODRV

GND

POWERPAD
PC116

1
1 21 1 2
+3VL ACN NC
PR116 25,32 EC_SMB_CLK1
2 20 1 2 0.1U_0402_25V6
C ACP SRP C
PR117
1 0_0402_5%
2

3 19 2
CMSRC SRN 25,32 EC_SMB_DAT1
PR118
100K_0201_5% 0_0402_5%
4 PU100 18 BGATE_N
ACDRV BATDRV#
PR119
1

5 17 1 2 BATT+
25 VR_ACIN ACOK BAT
BQ24770RUYR_QFN28_4X4
10_0603_5%

1
ACDET 6 16
ACDET CELL
PR141
PC117

2
1

2 1 7 15 BATT_TEMP
25 VR_ADP_I IADP BATPRES#
PR193 0.1U_0402_25V6

PROCHOT#
0_0402_5%

CMPOUT
0_0402_5%

CMPIN
IDCHG

PMON

SDA
2

SCL
VUSB
USB_ID_N

+5VALW
8

10

11

12

13

14
2A

100U_1206_6.3V6M
1 1 1
EXC24CH900U_4P

C111
C100 C103
USB20_N2 4 3 USB20_N2_CON .1U_0402_10V6-K .1U_0402_10V6-K
4 3 2 2 2
100P_0201_25V8J

100P_0201_25V8J

EMC@
1

1
PC118

PC119

USB20_P2 1 2 USB20_P2_CON
PSYS_CPU 36 1 2
PR188
30K_0402_1% PL105
2

U100
5 1
2

IN OUT
2
GND R101
EC_USB_ON# 4 3 2 1
19,25 EC_USB_ON# EN FLG USB_OC2# 9
B+ ADIN_1
PR125
ME@ 0_0402_5%
25,36 VR_HOT# 2 1 G517F2T11U SOT-23
DRAPH_WS33081-S3101-HF

0_0402_5% 10 ADIN
25,32 EC_SMB_DAT1 GND2 8 PF101 PL101
PR130 8
PD104 25,32 EC_SMB_CLK1 7 PR128 7A_32V_TR-3216FF7-R HCB2012KF-121T50_0805
2 1 1 2 CHGVCC 7 6 0_0402_5% 2 1 1 2
6 5 USB20_N2_CON 1 2 @ EMC@
5 PR546 USB20_N2 9
1

USB20_P2_CON

0.1U_0402_25V6
B SDM10U45LP-7_DFN1006-2-2 4 1 2 B

AZ5425-01F_DFN1006P2E2
10_0603_5% 4 USB20_P2 9

1
USB_ID_P 1 USB_ID

0.1U_0402_25V6
PC124 3 2

AZ5725-01F_DFN1006P2X
@ PL102

AZ5425-01F_DFN1006P2E2
3

1
1U_0603_25V7K

PC121
PD105 2 PR126 HCB2012KF-121T50_0805

1
2

PC122
2 1 1 0_0402_5% 1 2 PR129 PR127

1
1 0_0402_5%

1
200K_0402_5%

PD102

PD103
9 2.2_0805_5% 470K_0402_5%
GND1

PD101

PR545
SDM10U45LP-7_DFN1006-2-2 EMC@

1
1
PJP100 PC561

2
2

10U_0805_25V6K
2

2
EMC@ 0.1U_0402_25V6

1
@

PC123
EMC_NS@

2
EMC_NS@
ADIN_1
WIRELESS_IN_1 PQ105 PQ106 PQ107 VUSB
WIRELESS_IN PQ121 PQ122 AON2409L_DFN8 AON2409L_DFN8 AON7405_DFN8-5
AON2409L_DFN8 AON2409L_DFN8 7 2A 7 1
7 2A 7 1 4 4 1 2
PF102 PL503 1 4 4 1 2 2 3 5 2A

100K_0402_1%
7A_32V_TR-3216FF7-R HCB2012KF-121T50_0805 2 2 2A 5 8 8 5

1
WIRELESS_IN_R 2A

0.47U_0402_25V6K
2 1 1 2 5 8 8 5 6 6

1
100K_0402_1%

PR183
EMC@ 6 6

4
1

1
100K_0402_1%

LTA044EUBFS8TL_UMT3F-3 PC127
0.1U_0402_25V6

PR131

3
1

1
PR170
0.1U_0402_25V6

0.1U_0402_25V6
PL504 470K_0402_5% PD108
3

3
1

LTA044EUBFS8TL_UMT3F-3
200K_0402_1%
PC556

PR138

0.1U_0402_25V6
HCB2012KF-121T50_0805 DFLZ5V6-7_POWERDI123-2

2
2

3
LTA044EUBFS8TL_UMT3F-3
PC557

PC128
1 2
@

2
3

3
200K_0402_1%
PR167

PC156

2
PR132
EMC@
@
1

1
1

2 +3VALW
2

1
2 2

PQ170
PR162

1
200K_0402_1%
2

PR136

1
PQ131 PQ150 100K_0402_5%
@
1

1
@ PR135
200K_0402_5%

2
+3VL

2
3
PQ109B D
PQ109A

1
PR160 ADIN USB_ID_P 5
PD107

6
200K_0402_1% G D 2N7002KDWH_SOT363-6

1
PR134 2N7002KDWH_SOT363-6 2 USB_OPEN 2 1
DCIN_USB_EN 25
6
D PR133 200K_0402_1% S G

4
2 USB_ID 200K_0402_1% PQ132B

2
RB751V-40_SOD323-2

3
2N7002KDWH_SOT363-6

200K_0402_5%
PQ132A G D S
PD106

1
PR547
2N7002KDWH_SOT363-6 5 USB_ID_N

2
S 1 2USB_OPEN G
1

USB_ID_N 25 S

4
A CH520N4-45GP A

2N7002KDWH_SOT363-6

2N7002KDWH_SOT363-6
3

6
D @ D

PQ108B
D 5 USB_ID 2

PQ123B
5 G G PQ108A
PQ123A G 2N7002KDWH_SOT363-6
6

1
D S S

1
1

1
2 S PR137 PC129
4

25 EC_WC_EN# G PR165 33K_0402_5%

39K_0402_1% 0.1U_0402_25V6

2
S @
1

2
2N7002KDWH_SOT363-6
2

Security Classification LC Future Center Secret Data Title

Issued Date 2014/02/20 Deciphered Date 2014/02/20 NVDC Charger
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
D 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. MIXX4
Date: Monday, August 17, 2015 Sheet 32 of 37
5 4 3 2 1
 5 4 3 2 1

B+ B++
PJ200 PC203
2A

4.7U_0603_10V6-K

4.7U_0603_10V6-K
2 1 +3VBS 1 2
2 1

1M_0402_5%
0.1U_0402_25V6
1

1
PC201

PC202

PR200
0.1U_0603_25V7-M

PC200
JUMP_43X79
+3VALW

1
@

2
21

IN5

IN3

IN2

IN1

BS
GND4 PL200 PJ201
+3VLX 6 20 +3VLX 1 2 +3VALW_P 2 1
LX LX3 2 1

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
1.5UH_PCMB061H-1R5MS_6.5A_20%
7 19
GND1 LX2

1
JUMP_43X79
+3VLP 5A

PC204

PC205

PC206

PC207
8 18
GND2 GND3

1
D D
100mA @

2
+3V_PWRGD 9 17 PR202
PG LDO 4.7_0603_5%

4.7U_0603_6.3V6K
10 16 EMC_NS@
NC1 NC3

1
OUT

NC2

1 2
EN2

EN1

PC209
FF
PU200

2
SY8286BRAC_QFN20_3X3 PC210

11

12

13

+3VALW_P 14

15
PTP200 680P_0402_50V7K

2
PAD EMC_NS@
B++
PR201
1 2 +3VALW_EN @
25,35 EC_ON

0_0402_5%

1
PC211
@ PC208 PR203 PR204
0.1U_0402_25V6 1M_0402_5% +3VALW_FB 1 2 1 2

2
1000P_0402_25V7-K 1K_0402_1%

2
+3VL
+3VLP
PJ202
2 1
2 1

JUMP_43X39

C C

+3VALW

2
PR205
100K_0402_5%
PR206 @

1
+3V_PWRGD 1 2

B+
5A 0_0402_5% @
PR207
PJ203 PU201 +5V_PWRGD 1 2
4.7U_0603_10V6-K

4.7U_0603_10V6-K

2 1 +5VALWIN 5 9 PC217
2 1 4 IN1 PG
0.1U_0402_25V6

1 1 +5VBS 1 2 0_0402_5% @
3 IN2 BS
1

1
47U_B3_10VM_R45M
PC212

PC213

+5VALW

SY8286CRAC_QFN20_3X3
+ 2 IN3
PC216

PC215

JUMP_43X79 PR243 0.1U_0603_25V7-M

1M_0402_5% IN4 6
6A
2

7 LX1 19 PL201 PJ204

@ 2 GND1 LX2
8 20 +5VLX 1 2 +5VALW_P 2 1
2

GND2 LX3 2 1

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
18
21 GND3 1.5UH_PCMB061H-1R5MS_6.5A_20%
PR208 GND4

1
14 +5VALW_P JUMP_43X79
OUT

PC219

PC220

PC221

PC222

PC223

PC224
EC_ON 1 2 +5VALW_EN 12 PR209
+5VALWIN 11 EN1 13 +5VFB +5VLP 4.7_0603_5% @

2
EN2 FF EMC_NS@
0_0402_5% 15
100mA

2
10 LDO
NC1
1M_0402_5%

4.7U_0603_6.3V6K
+5VALWVCC 16 17
NC2 VCC
1

1
2+5VALWVCC
1

1
PR211

PC227
PC228

PC226
@ PC225 680P_0402_50V7K PR212

2
0.1U_0402_25V6 EMC_NS@ +5VFB 1 2 1 2
2

2
1U_0603_25V6M
2

@ 1000P_0402_25V7-K 1K_0402_1%
PC218
B B
1

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/02/20 Deciphered Date 2014/02/20 3VALWP/5VALWP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. MIXX4
Date: Monday, August 17, 2015 Sheet 33 of 37

5 4 3 2 1
 A B C D

PR301
1 2
12,25 EC_SUS_VCCP

0_0402_5%

1
@ PC308

2
0.1U_0402_25V6 PR384

2
0_0402_5%
+3VALW

PR383

1
+3VALW 1 2

0_0402_5%
@

6
+CPU_VCCIO

C1

C0

EN

LP#
7 PL300
2 MODE
PGND
1
B+ NB682GD-Z_QFN13_2X3
0.68UH_CMME041H-R68MS_7.3A_20% PJ301
5A
1

8 1 2 2 1
SW 2 1

0.1U_0603_25V7-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
PJ300
2A

2
4.7U_0603_10V6-K

4.7U_0603_10V6-K
2 1 1
2 1 VIN

1
AGND
VOUT

PC303
0.1U_0402_25V6
9 JUMP_43X79
BST

3V3
PC301

PC302

PC304

PC305

PC306

PC307
PR300 PR372

PG

1
JUMP_43X39

PC300
0_0603_5% 4.7_0603_5% @

2
PU300 1 2 EMC_NS@

13

12

11

10
@ +3VALW

12
+3VALW
PR543 PC372

2
1 2 680P_0402_50V7K

2
1
PR304 EMC_NS@
100K_0402_5% 5.1_0603_5%
PC309

2
4.7U_0603_6.3V6K

1
PR321
25 VCCIO_PWRGD CPU_VCCIO_SENSE_R 1 2

5.1_0603_5%
VCCIO_GND
PR322 1 20_0402_5%
CPU_VCCIO_SENSE 12

VCCIO_GND PR325 1 20_0402_5%

+CPU_VCCPRIM_P CPU_VSSIO_SENSE 12

2
PR323 +3VALW PJ306
5.1_0603_5% 1 2

4.7U_0603_6.3V6K
PR544 JUMPER

1
1 2

PC319
@

1
VCCPRIM_SENSE_R
5.1_0603_5%
+3VALW VCCIO_GND

2
2
PR307
100K_0402_5%

@ VCCPRIM_GND

1
PR305
0_0603_5%
B+ 1 2

0.1U_0603_25V7-M
PJ302
2A +CPU_VCCPRIM_IN

4.7U_0603_10V6-K

4.7U_0603_10V6-K
2 1

13

12

11

10
2 1

2
0.1U_0402_25V6

PU301
1

1
+CPU_VCCPRIM
PC311

PC312

PC313
VOUT

AGND

3V3
PG
JUMP_43X39
PC310

2 9 PL301 2

1
1 BST
2

@ 2 VIN 0.68UH_CMME041H-R68MS_7.3A_20% PJ303

8 +CPU_VCCPRIM_LX 1 2 +CPU_VCCPRIM_P 2 1
5A
SW 2 1

1
NB682GD-Z_QFN13_2X3
+3VALW

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
2 PR371
PGND 7 4.7_0603_5% JUMP_43X79
MODE

1
LP#
EMC_NS@

EN
C1

C0
2

PC314

PC315

PC316

PC317
@

1 2
PR550

2
100K_0402_5%
PC371
680P_0402_50V7K
PR548
1

2
EMC_NS@
1 2
13 VID1
0_0402_5% +3VALW
PR549
1 2
13 VID0
PR542
2

0_0402_5% PR551 VCCPRIM_SENSE_R 1 2

100K_0402_5% CPU_VCCPRIM_SENSE 13
PR541
VCCPRIM_GND 1 0_0402_5%
2
1

CPU_VSSPRIM_SENSE 13

+3VALW PJ307 0_0402_5%

PR306
1 2
1 2 +CPU_VCCPRIM_EN
25,34,35 EC_ON_1.8V JUMPER
0_0402_5%
@
1

@ PC318 VCCPRIM_GND
0.1U_0402_25V6
2

3 3

B+
PU502 PR310 PC324
PJ304 0_0603_5% 0.1U_0603_25V7-M
2
2 1
1 +1.0VALW_IN 4
IN BS
6 +1.0VALW_BS
1 2 1 2 PL302 +1.0VALW
0.1U_0402_25V6

4.7U_0603_10V6-K

4.7U_0603_10V6-K
1

1.0UH_PCMB041B-1R0MS_4.2A_20% PJ305
JUMP_43X39 EMC@
1

1
PC321

PC323

PC365

+1.0VALW_EN 2 5 +1.0VALW_LX 1 2 +1.0VALW_P 2 1

EN LX 2 1
2

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
@
2

3 1 JUMP_43X79
GND FB

0.1U_0402_25V6
PR312

PC361

PC326

PC327

PC328
4.7_0603_5% @

PC329
SY8104ADC_TSOT23-6 EMC_NS@
PR537
2

2
1 2

1 2
25,34,35 EC_ON_1.8V
1
1M_0402_5%

0.1U_0402_25V6

PC333
0_0402_5%
1

680P_0402_50V7K PR314 EMC@

2
1
PR343

PC555

EMC_NS@ PC334 90.9K_0402_1%

1

220P_0402_50V7K
2

2
2

+1.0VALW_FB
1

PR317
133K_0402_1%
2

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 1.35VS/+0.675VS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
D 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. MIXX4
Date: Monday, August 17, 2015 Sheet 34 of 37
A B C D
 A B C D

PR400
1 2 +DDR_S5

1M_0402_5%
25,27 EC_SYSON

PR444
0_0402_5%

2
PC400
0.1U_0402_10V7K

2
@

PR401
2 1 +DDR_S3
6 CPU_DRAMPG_CNTL PC401

1M_0402_5%
0.1U_0603_25V7-M
1
0_0402_5% 1

PR443
1 2

2
PC402
0.1U_0402_10V7K

2
@ PU400 PL400

12

11
SY8210AQVC_QFN19_3X4 PJ401
0.68UH_CMMB051B-R68MS_6.6A_20%
1 2 +DDR_1.2VP 2 1
+DDR_1.2V

BS

LX
2 1

JUMP_43X118

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
16
FB

0.1U_0402_25V6
9 PR402 @
B+ PGND

PC403

PC406

PC404

PC405
8 +DDR_1.2VP 4.7_0603_5%
VDDQSNS

PC407
PJ400 EMC_NS@
+DDR_0.6VS

2
4.7U_0603_10V6-K

4.7U_0603_10V6-K
2 1 10 7 +DDR_1.2VP

1 2
2 1 IN VLDOIN

0.1U_0402_25V6
PC415
2A
1

1
PC410

PC411
JUMP_43X79 6 330P_0402_50V8J
VTT

1
PC409
@ EMC@ PC414
+3VALW

22U_0603_6.3V6-M
PC412
2 5 680P_0402_50V7K PR403

2
17 VTTSNS EMC_NS@ 102K_0402_1% EMC@
ILMT 4

2
VTTGND

2
1U_0402_6.3V6K
1 PR404 2 18 3 PR405
PG VTTREF 1K_0402_1%

PC416
10K_0402_5% 2 +DDR_S3
19 S3

1
OT 1 +DDR_S5

2
S5

SGND
VCC

BYP
25 DDR_PWRGD

14

1 13

15

1
4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
+DDR_1.2VP PR406

1
Place close to IC 100K_0402_1%

PC417

PC418
2

2
1

22U_0603_6.3V6-M
PC461
2 2

2
+1.8VALW_L
2A
PL401
PJ402 PU401 1.0UH_PCMB041B-1R0MS_4.2A_20% PJ403
+3VALW 2
2 1
1 1A 1.8VALW_VIN 3
IN LX
6 1.8VALW_LX 1 2 2
2 1
1
+1.8VALW
22U_0603_6.3V6-M

22U_0603_6.3V6-M

JUMP_43X79 5 1 JUMP_43X79
NC FB
1

1
@ @
PC419

PC420

7 PR408
EN 4.7_0603_5%
2

68P_0402_50V8J

22U_0603_6.3V6-M

22U_0603_6.3V6-M
4 2 EMC_NS@
9 PGND1 PG PR409

2
PGND2

1
8 20K_0402_1%
SGND

PC421

PC422

PC423
1
SY8003DFC_DFN8_2X2

2
PR413 @ PC424
2 1 1.8VALW_EN 680P_0402_50V7K
25,33 EC_ON

2
0_0402_5% EMC_NS@
+3VALW
1

PR414
1

PR411 PC425
3 2 1 1M_0402_5% .1U_0402_10V6-K 1.8VALW_FB 3
25,34 EC_ON_1.8V
2

1
2

0_0402_5%

1
PR407
100K_0402_5% PR412
@ 10K_0402_1%
2

1.8VALW_PWRGD

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 1.2VS/+0.6VS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. MIXX4
Date: Monday, August 17, 2015 Sheet 35 of 37
A B C D
 5 4 3 2 1

+5VALW

PR500
1 2 B+
10_0603_5%

1U_0402_10V6K
1

47U_B3_10VM_R45M
PC501
PC500
1U_0402_10V6K

47U_B3_10VM_R45M

4.7U_0603_10V6-K

4.7U_0603_10V6-K

0.1U_0402_25V6
1 1

EMC@
PC502

1
+ +

PC503

PC581

PC582

PC583
2
2

2
2 2

D D

1
PC504
1U_0603_6.3V7-K PC505 PU500

D1

D8

D3

D6

D4
D5
H1
H3
H8

C8
C7
C6
C5

C4
C3
C2
C1
A8
A7
A6
A5
A4
A3
A2
A1
1U_0603_6.3V7-K ISL95852-HIZ-T_WLCSP64

PVCC_IA

PVCC_GT

VCC1

VCC2

AGND1
ANGD2
AGND3
AGND4
AGND5

PGND8
PGND7
PGND6
PGND5
PGND4
PGND3
PGND2
PGND1

VIN_GT4
VIN_GT3
VIN_GT2
VIN_GT1

VIN_IA4
VIN_IA3
VIN_IA2
VIN_IA1
0.2UH_PDLE051E-R20ME4R005-56_15A_20% +CPU_VCCGT
PC508 PL500
PR502
100K_0402_1% D2 1 2 1 2
BOOT_IA

1
2 1 IMON_IA E1
IMON_IA

1
PR503 B4 PR538 1
IMON_GT PHASE_IA4

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
PC507 2 1 2 1 100K_0402_1% H6 B3 0.22U_0402_10V6K 4.7_0603_5% PR506 PR504 1 1 1 1 1 1
IMON_SA PHASE_IA3

1
1_0402_5% + PC540

PC584

PC585

PC586

PC587

PC588

PC589
100K_0402_1% B2 EMC_NS@
IMON_SA PHASE_IA2

PC531

PC532

PC533

PC534

PC535

PC536

PC539
180P_0402_50V8-J PC509 2 1 PR505 2 1 E8 B1 3.65K_0402_1% 220U_B15G_2.5VM_R30M

1 2
180P_0402_50V8-J IMON_GT PHASE_IA1
PH500 PR507

2
PC522 2 1180P_0402_50V8-J 2.61K_0402_1% 2 2 2 2 2 2 2
PC558 1 2 1 2
680P_0402_50V7K

2
EMC_NS@ 10K_0402_1%_TSM0A103F34D1RZ

G1 1 PR508 2
PC523 2 1 0.01U_0201_10V6K PR509
1 2 3.01K_0402_1% COMP_IA H2 ISENP_IA PC524
COMP_IA 2 1
PC525 2 1 0.01U_0201_10V6K PR511
1 2 3.01K_0402_1% COMP_GT H7 F1 1 2 11K_0402_1%
COMP_GT ISENN_IA
COMP_IA PC526 1 2 220P_0402_50V7K PC527 2 10.01U_0201_10V6K1 PR5122 COMP_SA G3 PR510 0.022U_0402_25V7K
3.01K_0402_1% COMP_SA 1.3K_0402_1% 0.2UH_PDLE051E-R20ME4R005-56_15A_20% CPU_CORE
PR513 1 2 100K_0402_1% G6
COMP_GT CNFG PC529 PL501
PC528 1 2220P_0402_50V7K
D7 1 2 1 2
BOOT_GT
32 PSYS_CPU

220U_B15G_2.5VM_R30M
COMP_SA PC530 1 2220P_0402_50V7K B8 1
PR516 PHASE_GT4

47U_0805_6.3V6-M

47U_0805_6.3V6-M

47U_0805_6.3V6-M

47U_0805_6.3V6-M

47U_0805_6.3V6-M

47U_0805_6.3V6-M
B7 0.22U_0402_10V6K PR514 PR515
PHASE_GT3

1
+3VALW PSYS_CPU_R 1_0402_5% +

PC513
1 2 E7 B6
PSYS PHASE_GT2

PC510

PC511

PC512

PC515

PC516

PC517
B5 3.65K_0402_1%
IMVP_VR_CPU_OK PHASE_GT1 PC541 PR518
F3 PR517
PH501

2
0_0402_5% VR_RDY 2 1 2 1 2.61K_0402_1% 2
2

H_VR_ENABLE F4 1 2 1 2
PR519 VR_EN 680P_0402_50V7K 4.7_0603_5%
10K_0402_5% CPU_SVID_CLK_R F5 EMC_NS@ EMC_NS@ 10K_0402_1%_TSM0A103F34D1RZ
SCLK
1

1M_0402_5%
CPU_SVID_DAT_R F6 G8 1 PR520 2
PR521
1

SDA ISENP_GT
PR582

CPU_SVID_ALRT#_R PR522
1 2 E5 2 1
PC542
25 VR_CPU_PWROK ALERT# 11K_0402_1%
F8 1 2
C PR524 ISENN_GT C
E6
2

1 0_0402_5% VRHOT# 0.022U_0402_25V7K

ISENN_SA

ISENP_SA
2

FCCM_SA
PWM_SA
@ 1.3K_0402_1%

RTN_GT
25 EC_VR_EN

RTN_SA
RTN_IA

FB_GT

LG_SA
PR581

FB_IA

FBSA
0_0402_5% 1 2
25,32 VR_HOT#

G2

F2

G7

F7

G4

G5

E4

E3

E2

H5

H4
VCCST 0_0402_5%

ISENN_N_SA

ISENN_P_SA
+5VALW
1

100_0402_1%

PC543
1
PR580

2.2K_0402_1%
PR579 PC580
B+

0.1u_0201_10V6K
45.3_0402_1%

PC545

PR529
PR525
1U_0402_10V6-K
2

1
PR526

PC544
2

2
1

2
PR552
1

82P_0402_50V9-G
2

2
6
CPU_SVID_ALRT#_R

10U_0603_10V6K

10U_0603_10V6K
2 1
11 CPU_SVID_ALRT#

1
PC546

PC547
VCC
2
2.1K_0402_1% 2

0_0402_5%

1
82P_0402_50V9-G

0_0402_5%

0_0402_5%
PR527
2PR528

2
CPU_SVID_CLK_R

PC548
PR576 2 1 49.9_0402_1% 1
11 CPU_SVID_CLK UGATE

2
3
4
9
+CPU_VCCSA
PR530 PC549

1
PQ500
PR578 2 1 10_0402_1% CPU_SVID_DAT_R 2 7 2 1 2 1 2 AON7934L_DFN10
11 CPU_SVID_DAT FCCM BOOT

22P_0402_50V8-J
1 PL502

2
10 0.47UH_PCMB041B-R47MS_6A_20%
1.2K_0402_1%1 0_0402_5%

1
0.22U_0402_10V6K SA_LX 1 2

1
8 SA_LX PR540
3 PHASE 8 4.7_0603_5% PR531 PR532
PWM 1_0402_5%

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
EMC_NS@
2

1
3.65K_0402_1%
11 CPU_VCCGT_SENSE

7
6
5

1 2

PC550

PC551

PC552

PC553
PR533

POWERPAD
PH502 PR534

2
0_0402_5% 5
11 CPU_VSSGT_SENSE

2
LGATE PC560 1 2 1 2
680P_0402_50V7K

GND
11 CPU_VCC_SENSE
1

2
10K_0402_1%_TSM0A103F34D1RZ
EMC_NS@ 2.61K_0402_1%
PU501
11 CPU_VSS_SENSE ISENN_P_SA 1 PR535 2

4
1

ISL95808HRZ-TS2378_DFN8_2X2 PC554
PR536
PR583 2 1 11K_0402_1%
12 CPU_VCCSA_SENSE 1K_0402_5% ISENN_N_SA 1 2
12 CPU_VSSSA_SENSE 0.015U_0402_25V7-K
2

1.1K_0402_1%

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/02/20 Deciphered Date 2014/02/20 IMVP8
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
D 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. MIXX4
Date: Monday, August 17, 2015 Sheet 36 of 37
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/02/20 Deciphered Date 2014/02/20 IMVP8
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. MIXX4
Date: Monday, August 17, 2015 Sheet 37 of 37
5 4 3 2 1