A B C D E

1 1

LCFC Confidential
BYG43
Lenovo Yoga 700 (14)
2
NM-A601 REV1.0 2

Haydn SKL M/B Schematics Document

INTEL SKYLAKE-U Platform
INTEL SKL U-series CPU + DDR3L DIMM+ NV N16S-GT

2015-07-20
REV:1.0
3 3

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2014/01/11 Deciphered Date 2013/11/08 Cover Page
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Haydn-S
Date: Wednesday, July 22, 2015 Sheet 1 of 46
A B C D E
 5 4 3 2 1

Yoga 700(14) Block diagram

D D

32.768KHz
Page 7 Memory BUS-ChannelB SO-DIMM DDR3L
Page 14
24MHz
Page 8 1.35V DDR3L 1333/1600 MT/s
VRAM DDR3L SINGLE N15S/N16S-GT PCIE-Port5 UP TO 8G
1~2G 4psc Page 15-23
GEN2
USB 2.0-Port0 Int. Camera
Page 24
Micro HDMI Conn. DDI-Port1
Page 25 USB 2.0-Port1
USB 3.0-Port2 USB 3.0/2.0 Right
eDP-Port[0:1] Intel CPU Page 32
eDP Conn.
Page 24
SKYLAKE-U 2+2 TDP 15W
USB 2.0-Port2
SATA Gen3 Port 0 USB 3.0/2.0 Left
SATA/SSHD 42x24x1.27 BGA USB 3.0-Port1
Page 32

PCIe Port3 BGA 1356

C
PCIe Mini Card USB 2.0-Port3 Cardreader C

SPK Conn. WIFI with BT support, USB 2.0-Port4 IO/CONN Realtek RTS5170 SD/MMC Conn.
Page 30
(1W x 2)

Int. MIC Conn. HD Audio USB 2.0-Port6 Touch Screen

Codec CX20752
Page 24

HP&Mic Combo Conn. USB 2.0-Port7 DC_IN Combo USB port

iphone type USB 2.0 Port 7

SPI BUS SPI ROM

(8MB) Page 7
Page 4~13

G-Sensor LPC BUS I2C BUS SPI ROM

(4MB) reserve Page 7
BMA222E
B 32.768KHz B

Page 29
E-compass I2C EC Battery
G-sensor ITE IT8396 128VFBGA Page 37
BMC150 Page 29 SMBUS
Thermal Sensor
ALS NCT7718W Page 31
AL3010
Sensor Board  Touch Pad Int.KBD LID PAD LID
Page 31 Page 30

USB Board 

Sub-board
DMIC  SUB

Sensor SUB
A A

USB SUB

Security Classification LC Future Center Secret Data Title

Issued Date 2014/01/11 Deciphered Date 2013/11/08 Block Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Haydn-S
Date: Wednesday, July 22, 2015 Sheet 2 of 46
5 4 3 2 1
 A B C D E

Voltage Rails ( O --> Means ON , X --> Means OFF ) BOM Structure Table Board ID Table
Board ID Description PCB Revision
+5VS BOM Structure BOM Structure
DA8@ PCB MIRROR@ EC Mirror-code enable
Power Plane +3VS
UMA@ UMA SKU part UNMIRROR@ EC Mirror-code disableable
+1.5VS
B+ DEBUG@ DEBUG CARD Part OPT@ Discrete GPU SKU part
+1.05VS
+3VALW_PCH +1.35V_CPU ME@ ME part(connector, hole) N15SGT@ For N15S-GT GPU part
+3VL +3VALW +1.35V +0.68VS
RF@ RF request GC6@ GC62.0 support part
+CPU_CORE
1
State +5VLP +5VALW EMC@ EMC request RANKA@ For VRAM RankA part
1
CD@ COST DOWN Part
REV@ RESERVER Part

S0 O O O O O O BOM Configuration Table

SKU Description BOM Config
S3 O O O O X O
SKU1

DS3 O O X O X X
SKU2

S5 S4/AC Only O O O X X X
S5 S4 O X X X X
Battery only X

S5 S4 X X X X X
2 AC & Battery X 2

don't exist
SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# +VALW +VALW_PCH +V +VS Clock

Full ON HIGH HIGH HIGH ON ON ON ON ON

S1(Power On Suspend) LOW HIGH HIGH ON ON ON ON LOW X76&VGA Configuration Table

SKU Description BOM Config
S3 (Suspend to RAM) LOW LOW HIGH ON ON ON OFF OFF

DS3 (Suspend to RAM) LOW LOW HIGH ON LOW ON OFF OFF

S4 (Suspend to Disk) LOW LOW LOW ON ON OFF OFF OFF

S5 (Soft OFF) LOW LOW LOW ON ON OFF OFF OFF

SMBUS Control Table

GPU Thermal
SOURCE Sensor ALS BATT touch sensor SODIMM Sensor PCH charger

3 3

EC_SMB_CLK1 IT8386
EC_SMB_DAT1 +3VALW_EC X X V X X X X X V
+3VLP

EC_SMB_CLK3 IT8386
V V X X X X X X X
EC_SMB_DAT3 +3VS +3VS +3VS

EC_SMB_CLK0 IT8386
X X X X X V V V X
EC_SMB_DAT0 +3VS +3VS +3VALW_PCH
PCB And LOGO Config ZZZ3 DA8@
SMB_CLK PCH
X X X V X X X X
SMB_DATA +3VALW_PCH
X PCB LOGO
+3VS
PCB BYG43 NM-A601 NS-A601/A602
ZZZ1 2.3G@ ZZZ2 2.5G@
ZZZ4 HDMI@ ZZZ5 USB30@

SM Bus address PCIE PORT LIST USB Port Table CPU

USB20 USB30 Intel i5-6200U 2.3G/2C/3M Intel i7-6500U 2.5G/2C/4M
Device address Port Device CAMERA Left USB HDMI LOGO USB30 LOGO
Battery 0001 011X b
0 1
1 Right USB Right USB ZZZ6 HY2G@ ZZZ7 MIC2G@ ZZZ8 SAM2G@
EC1 2
EXHCI/XHCI

Charger
4
1 X 2 Left USB 3 X 4
Sensor
X CARD READER X
VRAM
EC3 ALS
2 3 4
3 WLAN 4 BT HYNIX 2G MICRON 2G SAMSUNG 2G
Thermal Sensor 1001_100xb
EC0 4 X 5 Sensor
PCH THM
5 GPU 6 TOUCH PANEL
PCH TP
7 DC_IN combo USB2.0 Title
Security Classification LC Future Center Secret Data
Issued Date 2014/01/11 Deciphered Date 2013/11/08 Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Haydn-S
Date: Thursday, July 23, 2015 Sheet 3 of 46
A B C D E
 5 4 3 2 1

SKL_ULT ?
UC1A

27 PCH_HDMI_TX2- PCH_HDMI_TX2- E55 C47 PCH_EDP_TX0- PCH_EDP_TX0- 26 1 2 PCH_BKLT_EN

PCH_HDMI_TX2+ F55 DDI1_TXN[0] EDP_TXN[0] C46 PCH_EDP_TX0+ RC6 100K_0402_5%
27 PCH_HDMI_TX2+ DDI1_TXP[0] EDP_TXP[0] PCH_EDP_TX0+ 26
PCH_HDMI_TX1- E58 D46 PCH_EDP_TX1- 1 2 PCH_LCD_VDDEN
27 PCH_HDMI_TX1- DDI1_TXN[1] EDP_TXN[1] PCH_EDP_TX1- 26
27 PCH_HDMI_TX1+ PCH_HDMI_TX1+ F58 C45 PCH_EDP_TX1+ PCH_EDP_TX1+ 26 RC7 100K_0402_5%
PCH_HDMI_TX0- F53 DDI1_TXP[1] EDP_TXP[1] A45
27 PCH_HDMI_TX0- DDI1_TXN[2] EDP_TXN[2]
27 PCH_HDMI_TX0+ PCH_HDMI_TX0+ G53 B45
PCH_HDMI_CLK- F56 DDI1_TXP[2] EDP_TXP[2] A47
27 PCH_HDMI_CLK- DDI1_TXN[3] EDP_TXN[3]
PCH_HDMI_CLK+ G56 B47
27 PCH_HDMI_CLK+ DDI1_TXP[3] EDP_TXP[3]
D D
C50 E45 PCH_EDP_AUX- PCH_EDP_AUX- 26
D50 DDI2_TXN[0] DDI EDP EDP_AUXN F45 PCH_EDP_AUX+
DDI2_TXP[0] EDP_AUXP PCH_EDP_AUX+ 26
C52
D52 DDI2_TXN[1] B52
A50 DDI2_TXP[1] EDP_DISP_UTIL
B50 DDI2_TXN[2] G50
D51 DDI2_TXP[2] DDI1_AUXN F50
C51 DDI2_TXN[3] DDI1_AUXP E48
DDI2_TXP[3] DDI2_AUXN F48
DDI2_AUXP G46
DISPLAY SIDEBANDS DDI3_AUXN F46
PCH_HDMI_DDC_CLK L13 DDI3_AUXP
27 PCH_HDMI_DDC_CLK GPP_E18/DDPB_CTRLCLK
27 PCH_HDMI_DDC_DAT PCH_HDMI_DDC_DAT L12 L9 PCH_HDMI_HPD PCH_HDMI_HPD 27
GPP_E19/DDPB_CTRLDATA GPP_E13/DDPB_HPD0 L7
N7 GPP_E14/DDPC_HPD1 L6 GPP_E15 RC181 1 2 0_0402_5%
GPP_E20/DDPC_CTRLCLK GPP_E15/DDPD_HPD2 EC_SCI# 7,30
N8 N9
GPP_E21/DDPC_CTRLDATA GPP_E16/DDPE_HPD3 L10 PCH_EDP_HPD
GPP_E17/EDP_HPD PCH_EDP_HPD 26
N11
N12 GPP_E22/DDPD_CTRLCLK R12 PCH_BKLT_EN
GPP_E23/DDPD_CTRLDATA EDP_BKLTEN PCH_BKLT_EN 26,30
R11 PCH_BKLT_CTRL PCH_BKLT_CTRL 26
24.9_0402_1% RC5 2 1 EDP_COMP E52 EDP_BKLTCTL U13 PCH_LCD_VDDEN
+VCCIO EDP_RCOMP EDP_VDDEN PCH_LCD_VDDEN 26
1 OF 20
+VCCIO&EDP_COMP : SKYLAKE-U_BGA1356
Trace Width: 20mil REV = 1 ?
Isolation Spacing: 25mil @
Max length: 100mil

+VCCST_CPU
C C
+VCCSTG

1
RC1625
1

@ 49.9_0402_1%
RC19 DDP*_CTRLDATA strapping sampled on the rising edge of PWROK
1K_0402_5% UC1D SKL_ULT ?

2
check PROCHOT# circuit with PWR
CATERR# D63 Port Strap Enable Disable
2

CPU_PECI_R A54 CATERR#

30 CPU_PECI_R PECI
CPU_PROCHOT# RC13 1 2 CPU_PROCHOT#_R C65 JTAG Pull up to 3.3 V
30 CPU_PROCHOT# PROCHOT#
18 H_THRMTRIP# 499 +-1% 0402 H_THRMTRIP# C63 Port 1 DDPB_CTRLDATA with 2.2Kohm NC
A65 THERMTRIP# B61 XDP_TCK
SKTOCC# PROC_TCK D60 XDP_TDI
CPU MISC PROC_TDI
Pull up to 3.3 V
1

PAD @ TP11 1 XDP_BPM0# C55 A61 XDP_TDO Port 2 DDPC_CTRLDATA with 2.2Kohm NC
RC143 PAD @ TP12 1 XDP_BPM1# D55 BPM#[0] PROC_TDO C60 XDP_TMS
PAD @ TP13 1 XDP_BPM2# B54 BPM#[1] PROC_TMS B59 XDP_TRST#
1K_0402_5% BPM#[2] PROC_TRST#
PAD @ TP14 1 XDP_BPM3# C56
BPM#[3] B56 PCH_JTAG_TCK 1 PAD @
TP29
2

PAD @ TP162 1 GPP_E3 A6 PCH_JTAG_TCK D59 PCH_JTAG_TDI

check H_THRMTRIP# if need to connector to EC GPP_E3/CPU_GP0 PCH_JTAG_TDI
PAD @ TP163 1 GPP_E7 A7 A56 PCH_JTAG_TDO
+VCCST_CPU PAD @ TP164 1 GPP_B3 BA5 GPP_E7/CPU_GP1 PCH_JTAG_TDO C59 PCH_JTAG_TMS
GPP_B3/CPU_GP2 PCH_JTAG_TMS
Port DDI PROCESSOR Pin Names HDMI* Mapping
PAD @ TP165 1 GPP_B4 AY5 C61 PCH_JTAG_TRST# Port 1 DDI1_TXN[0] HDMIxC_TX2_DN
GPP_B4/CPU_GP3 PCH_TRST# A59 JTAGX
RC155 1 2 49.9_0402_1% PROC_OPI_RCOMP AT16 JTAGX DDI1_TXP[0] HDMIxC_TX2_DP
RC156 1 2 49.9_0402_1% PCH_OPI_RCOMP AU16 PROC_POPIRCOMP DDI1_TXN[1] HDMIxC_TX1_DN
RC157 1 @ 2 49.9_0402_1% EDRAM_OPIO_RCOMP H66 PCH_OPIRCOMP DDI1_TXP[1] HDMIxC_TX1_DP
OPCE_RCOMP
RC170 1 @ 2 49.9_0402_1% EOPIO_RCOMP H65
OPC_RCOMP
DDI1_TXN[2] HDMIxC_TX0_DN
DDI1_TXP[2] HDMIxC_TX0_DP
4 OF 20 DDI1_TXN[3] HDMIxC_CLK_DN
SKYLAKE-U_BGA1356 DDI1_TXP[3] HDMIxC_CLK_DP
REV = 1 ?
@
DDPB_HPD DDI1_HPD_Q
DDPB_CTRLCLK DDI1_CTRL_CK
DDPB_CTRLDATA DDI1_CTRL_DATA

XDP_TCK RC1546 1 2 0_0402_5% JTAGX RC1551 1 2 51_0402_5%

B B
DisplayPort* Disabling and Termination
XDP_TDO RC1547 1 2 0_0402_5% PCH_JTAG_TDO RC1543 1 2 51_0402_5% +VCCSTG
Pin Name Recommendation
DDPC_AUXP No Connect
XDP_TDI RC1548 1 2 0_0402_5% PCH_JTAG_TDI
DDPC_AUXN No Connect
XDP_TMS RC1549 1 2 0_0402_5% PCH_JTAG_TMS DDPC_HPD No Connect
DDI2_TXP[3:0] No Connect
XDP_TRST# RC1550 1 2 0_0402_5% PCH_JTAG_TRST# DDI2_TXN[3:0] No Connect
DDPC_CTRLCLK No Connect
DDPC_CTRLDATA No Connect
check JTAG circuit?

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/01/11 Deciphered Date 2013/11/08 MCP (DDI,EDP)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Haydn-S
Date: Wednesday, July 22, 2015 Sheet 4 of 46
5 4 3 2 1
 5 4 3 2 1

DDRA_DQ[63:0] 16

SKL-U interleaved, DDRA_DQS[7:0]

DDRA_DQS#[7:0]
16

16

D ? ? D
SKL_ULT SKL_ULT
UC1B UC1C

AU53
DDR0_CKN[0] DDRA_CLK0# 16
DDRA_DQ0 AL71 AT53 AF65 AN45
DDR0_DQ[0] DDR0_CKP[0] DDRA_CLK0 16 DDR1_DQ[0]/DDR0_DQ[16] DDR1_CKN[0]
DDRA_DQ1 AL68 AU55 AF64 AN46
DDR0_DQ[1] DDR0_CKN[1] DDRA_CLK1# 16 DDR1_DQ[1]/DDR0_DQ[17] DDR1_CKN[1]
DDRA_DQ2 AN68 AT55 AK65 AP45
DDR0_DQ[2] DDR0_CKP[1] DDRA_CLK1 16 DDR1_DQ[2]/DDR0_DQ[18] DDR1_CKP[0]
DDRA_DQ3 AN69 AK64 AP46
DDRA_DQ4 AL70 DDR0_DQ[3] BA56 AF66 DDR1_DQ[3]/DDR0_DQ[19] DDR1_CKP[1]
DDR0_DQ[4] DDR0_CKE[0] DDRA_CKE0 16 DDR1_DQ[4]/DDR0_DQ[20]
DDRA_DQ5 AL69 BB56 AF67 AN56
DDR0_DQ[5] DDR0_CKE[1] DDRA_CKE1 16 DDR1_DQ[5]/DDR0_DQ[21] DDR1_CKE[0]
DDRA_DQ6 AN70 AW56 AK67 AP55
DDRA_DQ7 AN71 DDR0_DQ[6] DDR0_CKE[2] AY56 AK66 DDR1_DQ[6]/DDR0_DQ[22] DDR1_CKE[1] AN55
DDRA_DQ8 AR70 DDR0_DQ[7] DDR0_CKE[3] AF70 DDR1_DQ[7]/DDR0_DQ[23] DDR1_CKE[2] AP53
DDRA_DQ9 AR68 DDR0_DQ[8] AU45 AF68 DDR1_DQ[8]/DDR0_DQ[24] DDR1_CKE[3]
DDR0_DQ[9] DDR0_CS#[0] DDRA_CS0# 16 DDR1_DQ[9]/DDR0_DQ[25]
DDRA_DQ10 AU71 AU43 AH71 BB42
DDR0_DQ[10] DDR0_CS#[1] DDRA_CS1# 16 DDR1_DQ[10]/DDR0_DQ[26] DDR1_CS#[0]
DDRA_DQ11 AU68 AT45 AH68 AY42
DDR0_DQ[11] DDR0_ODT[0] DDRA_ODT0 16 DDR1_DQ[11]/DDR0_DQ[27] DDR1_CS#[1]
DDRA_DQ12 AR71 AT43 AF71 BA42
DDR0_DQ[12] DDR0_ODT[1] DDRA_ODT1 16 DDR1_DQ[12]/DDR0_DQ[28] DDR1_ODT[0]
DDRA_DQ13 AR69 AF69 AW42
DDRA_DQ14 AU70 DDR0_DQ[13] BA51 AH70 DDR1_DQ[13]/DDR0_DQ[29] DDR1_ODT[1]
DDR0_DQ[14] DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] DDRA_MA5 16 DDR1_DQ[14]/DDR0_DQ[30]
DDRA_DQ15 AU69 BB54 AH69 AY48
DDR0_DQ[15] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] DDRA_MA9 16 DDR1_DQ[15]/DDR0_DQ[31] DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5]
DDRA_DQ16 BB65 BA52 AT66 AP50
DDR0_DQ[16]/DDR0_DQ[32] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] DDRA_MA6 16 DDR1_DQ[16]/DDR0_DQ[48] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9]
DDRA_DQ17 AW65 AY52 AU66 BA48
DDR0_DQ[17]/DDR0_DQ[33] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] DDRA_MA8 16 DDR1_DQ[17]/DDR0_DQ[49] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6]
DDRA_DQ18 AW63 AW52 AP65 BB48
DDR0_DQ[18]/DDR0_DQ[34] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] DDRA_MA7 16 DDR1_DQ[18]/DDR0_DQ[50] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8]
DDRA_DQ19 AY63 AY55 AN65 AP48
DDR0_DQ[19]/DDR0_DQ[35] DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] DDRA_BS2# 16 DDR1_DQ[19]/DDR0_DQ[51] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]
DDRA_DQ20 BA65 AW54 AN66 AP52
DDR0_DQ[20]/DDR0_DQ[36] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] DDRA_MA12 16 DDR1_DQ[20]/DDR0_DQ[52] DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]
DDRA_DQ21 AY65 BA54 AP66 AN50
DDR0_DQ[21]/DDR0_DQ[37] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] DDRA_MA11 16 DDR1_DQ[21]/DDR0_DQ[53] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12]
DDRA_DQ22 BA63 BA55 AT65 AN48
DDR0_DQ[22]/DDR0_DQ[38] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# DDRA_MA15 16 DDR1_DQ[22]/DDR0_DQ[54] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]
DDRA_DQ23 BB63 AY54 AU65 AN53
DDR0_DQ[23]/DDR0_DQ[39] DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] DDRA_MA14 16 DDR1_DQ[23]/DDR0_DQ[55] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT#
DDRA_DQ24 BA61 AT61 AN52
DDRA_DQ25 AW61 DDR0_DQ[24]/DDR0_DQ[40] AU46 AU61 DDR1_DQ[24]/DDR0_DQ[56] DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]
DDR0_DQ[25]/DDR0_DQ[41] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] DDRA_MA13 16 DDR1_DQ[25]/DDR0_DQ[57]
DDRA_DQ26 BB59 AU48 AP60 BA43
DDR0_DQ[26]/DDR0_DQ[42] DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15] DDRA_CAS# 16 DDR1_DQ[26]/DDR0_DQ[58] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]
DDRA_DQ27 AW59 AT46 AN60 AY43
DDR0_DQ[27]/DDR0_DQ[43] DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14] DDRA_WE# 16 DDR1_DQ[27]/DDR0_DQ[59] DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]
DDRA_DQ28 BB61 AU50 AN61 AY44
DDR0_DQ[28]/DDR0_DQ[44] DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16] DDRA_RAS# 16 DDR1_DQ[28]/DDR0_DQ[60] DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]
DDRA_DQ29 AY61 AU52 AP61 AW44
DDR0_DQ[29]/DDR0_DQ[45] DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] DDRA_BS0# 16 DDR1_DQ[29]/DDR0_DQ[61] DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]
DDRA_DQ30 BA59 AY51 AT60 BB44
DDR0_DQ[30]/DDR0_DQ[46] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] DDRA_MA2 16 DDR1_DQ[30]/DDR0_DQ[62] DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]
DDRA_DQ31 AY59 AT48 AU60 AY47
DDR0_DQ[31]/DDR0_DQ[47] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] DDRA_BS1# 16 DDR1_DQ[31]/DDR0_DQ[63] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]
DDRA_DQ32 AY39 AT50 AU40 BA44
DDR0_DQ[32]/DDR1_DQ[0] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] DDRA_MA10 16 DDR1_DQ[32]/DDR1_DQ[16] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]
C DDRA_DQ33 AW39 BB50 AT40 AW46 C
DDR0_DQ[33]/DDR1_DQ[1] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] DDRA_MA1 16 DDR1_DQ[33]/DDR1_DQ[17] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]
DDRA_DQ34 AY37 AY50 AT37 AY46
DDR0_DQ[34]/DDR1_DQ[2] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] DDRA_MA0 16 DDR1_DQ[34]/DDR1_DQ[18] DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1]
DDRA_DQ35 AW37 BA50 AU37 BA46
DDR0_DQ[35]/DDR1_DQ[3] DDR0_MA[3] DDRA_MA3 16 DDR1_DQ[35]/DDR1_DQ[19] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]
DDRA_DQ36 BB39 BB52 AR40 BB46
DDR0_DQ[36]/DDR1_DQ[4] DDR0_MA[4] DDRA_MA4 16 DDR1_DQ[36]/DDR1_DQ[20] DDR1_MA[3]
DDRA_DQ37 BA39 AP40 BA47
DDRA_DQ38 BA37 DDR0_DQ[37]/DDR1_DQ[5] AM70 DDRA_DQS#0 AP37 DDR1_DQ[37]/DDR1_DQ[21] DDR1_MA[4]
DDRA_DQ39 BB37 DDR0_DQ[38]/DDR1_DQ[6] DDR0_DQSN[0] AM69 DDRA_DQS0 AR37 DDR1_DQ[38]/DDR1_DQ[22] AH66
DDRA_DQ40 AY35 DDR0_DQ[39]/DDR1_DQ[7] DDR0_DQSP[0] AT69 DDRA_DQS#1 AT33 DDR1_DQ[39]/DDR1_DQ[23] DDR1_DQSN[0]/DDR0_DQSN[2] AH65
DDRA_DQ41 AW35 DDR0_DQ[40]/DDR1_DQ[8] DDR0_DQSN[1] AT70 DDRA_DQS1 AU33 DDR1_DQ[40]/DDR1_DQ[24] DDR1_DQSP[0]/DDR0_DQSP[2] AG69
DDRA_DQ42 AY33 DDR0_DQ[41]/DDR1_DQ[9] DDR0_DQSP[1] BA64 DDRA_DQS#2 AU30 DDR1_DQ[41]/DDR1_DQ[25] DDR1_DQSN[1]/DDR0_DQSN[3] AG70
DDRA_DQ43 AW33 DDR0_DQ[42]/DDR1_DQ[10] DDR0_DQSN[2]/DDR0_DQSN[4] AY64 DDRA_DQS2 AT30 DDR1_DQ[42]/DDR1_DQ[26] DDR1_DQSP[1]/DDR0_DQSP[3] AR66
DDRA_DQ44 BB35 DDR0_DQ[43]/DDR1_DQ[11] DDR0_DQSP[2]/DDR0_DQSP[4] AY60 DDRA_DQS#3 AR33 DDR1_DQ[43]/DDR1_DQ[27] DDR1_DQSN[2]/DDR0_DQSN[6] AR65
DDRA_DQ45 BA35 DDR0_DQ[44]/DDR1_DQ[12] DDR0_DQSN[3]/DDR0_DQSN[5] BA60 DDRA_DQS3 AP33 DDR1_DQ[44]/DDR1_DQ[28] DDR1_DQSP[2]/DDR0_DQSP[6] AR61
DDRA_DQ46 BA33 DDR0_DQ[45]/DDR1_DQ[13] DDR0_DQSP[3]/DDR0_DQSP[5] BA38 DDRA_DQS#4 AR30 DDR1_DQ[45]/DDR1_DQ[29] DDR1_DQSN[3]/DDR0_DQSN[7] AR60
DDRA_DQ47 BB33 DDR0_DQ[46]/DDR1_DQ[14] DDR0_DQSN[4]/DDR1_DQSN[0] AY38 DDRA_DQS4 AP30 DDR1_DQ[46]/DDR1_DQ[30] DDR1_DQSP[3]/DDR0_DQSP[7] AT38
DDRA_DQ48 AY31 DDR0_DQ[47]/DDR1_DQ[15] DDR0_DQSP[4]/DDR1_DQSP[0] AY34 DDRA_DQS#5 AU27 DDR1_DQ[47]/DDR1_DQ[31] DDR1_DQSN[4]/DDR1_DQSN[2] AR38
DDRA_DQ49 AW31 DDR0_DQ[48]/DDR1_DQ[32] DDR0_DQSN[5]/DDR1_DQSN[1] BA34 DDRA_DQS5 AT27 DDR1_DQ[48] DDR1_DQSP[4]/DDR1_DQSP[2] AT32
DDRA_DQ50 AY29 DDR0_DQ[49]/DDR1_DQ[33] DDR0_DQSP[5]/DDR1_DQSP[1] BA30 DDRA_DQS#6 AT25 DDR1_DQ[49] DDR1_DQSN[5]/DDR1_DQSN[3] AR32
DDRA_DQ51 AW29 DDR0_DQ[50]/DDR1_DQ[34] DDR0_DQSN[6]/DDR1_DQSN[4] AY30 DDRA_DQS6 AU25 DDR1_DQ[50] DDR1_DQSP[5]/DDR1_DQSP[3] AR25
DDRA_DQ52 BB31 DDR0_DQ[51]/DDR1_DQ[35] DDR0_DQSP[6]/DDR1_DQSP[4] AY26 DDRA_DQS#7 AP27 DDR1_DQ[51] DDR1_DQSN[6] AR27
DDRA_DQ53 BA31 DDR0_DQ[52]/DDR1_DQ[36] DDR0_DQSN[7]/DDR1_DQSN[5] BA26 DDRA_DQS7 AN27 DDR1_DQ[52] DDR1_DQSP[6] AR22
DDRA_DQ54 BA29 DDR0_DQ[53]/DDR1_DQ[37] DDR0_DQSP[7]/DDR1_DQSP[5] AN25 DDR1_DQ[53] DDR1_DQSN[7] AR21
DDRA_DQ55 BB29 DDR0_DQ[54]/DDR1_DQ[38] AW50 AP25 DDR1_DQ[54] DDR1_DQSP[7]
DDRA_DQ56 AY27 DDR0_DQ[55]/DDR1_DQ[39] DDR0_ALERT# AT52 AT22 DDR1_DQ[55] AN43
DDRA_DQ57 AW27 DDR0_DQ[56]/DDR1_DQ[40] DDR0_PAR AU22 DDR1_DQ[56] DDR1_ALERT# AP43
DDRA_DQ58 AY25 DDR0_DQ[57]/DDR1_DQ[41] AY67 AU21 DDR1_DQ[57] DDR1_PAR AT13 DDRA_DRAMRST#_R
DDR0_DQ[58]/DDR1_DQ[42] DDR_VREF_CA DDR_SM_VREFCA 16 SMVREF DDR1_DQ[58] DRAM_RESET#
DDRA_DQ59 AW25 AY68 WIDTH:20MIL AT21 AR18 SM_RCOMP_0 RC20 1 2 121_0402_1%
DDR0_DQ[59]/DDR1_DQ[43] DDR0_VREF_DQ DDR_SA_VREFDQ 16 DDR1_DQ[59] DDR_RCOMP[0]
DDRA_DQ60 BB27 DDR CH - A BA67 1 @ SPACING: 20MIL AN22 AT18 SM_RCOMP_1 RC21 1 2 80.6_0402_1%
DDRA_DQ61 BA27 DDR0_DQ[60]/DDR1_DQ[44] DDR1_VREF_DQ TP22 AP22 DDR1_DQ[60] DDR_RCOMP[1] AU18 SM_RCOMP_2 RC22 1 2 100_0402_1%
DDRA_DQ62 BA25 DDR0_DQ[61]/DDR1_DQ[45] AW67 DDR_VTT_CNTL AP21 DDR1_DQ[61] DDR_RCOMP[2]
DDRA_DQ63 BB25 DDR0_DQ[62]/DDR1_DQ[46] DDR_VTT_CNTL AN21 DDR1_DQ[62] DDR CH - B
DDR0_DQ[63]/DDR1_DQ[47] DDR1_DQ[63]
2 OF 20
3 OF 20
SKYLAKE-U_BGA1356 SKYLAKE-U_BGA1356
REV = 1 ? REV = 1 ?
@ @

B B

+1.35V

2
+3VALW RC15

470_0402_5%
1

RD55

1
RC422 1 2 DDRA_DRAMRST#_R
16 DDRA_DRAMRST#
100K_0402_5% 1
0_0402_5%
CC23
2

@
2 .1U_0402_10V6-K
CPU_DRAMPG_CNTL 40
+1.35V
1

C
RC452 1 2 2 QC142
1K_0402_5% B
E
3

MMBT3904WH_SOT323-3

DDR_VTT_CNTL
2

RC432
10K_0402_5%
@
1

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/01/11 Deciphered Date 2013/11/08 MCP (DDR3L)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Haydn-S
Date: Wednesday, July 22, 2015 Sheet 5 of 46
5 4 3 2 1
 5 4 3 2 1

?
SKL_ULT
UC1E
+3VALW_PCH +3VS +3VS
SPI - FLASH
SMBUS, SMLINK
SPI_CLK RC1539 1 2 15_0402_5% SPI_CLK_R SPI_CLK_R AV2 R7 PCH_SMB_CLK
30 SPI_CLK SPI0_CLK GPP_C0/SMBCLK
SPI_CLK_1 RC1538 1 @ 2 33_0402_5% SPI_SO_R AW3 R8 PCH_SMB_DATA DIMM1, TP
SPI_SI_R AV3 SPI0_MISO GPP_C1/SMBDATA R10 SMB_ALERT#
SPI0_MOSI GPP_C2/SMBALERT#

3
4

4
3
SPI_WP#_R AW2 RPC20
SPI_SO RC53 1 2 15_0402_5% SPI_SO_R SPI_HOLD#_R AU4 SPI0_IO2 R9 SML0_CLK RPC24
30 SPI_SO SPI0_IO3 GPP_C3/SML0CLK

2
SPI_SO_1 RC177 1 @ 2 33_0402_5% SPI_CS0#_R AU3 W2 SML0_DATA 2.2K_0404_4P2R_5% 2.2K_0404_4P2R_5%

G
D SPI_CS1#_R AU2 SPI0_CS0# GPP_C4/SML0DATA W1 SML0_ALERT# D
AU1 SPI0_CS1# GPP_C5/SML0ALERT#

2
1

1
2
SPI0_CS2# W3 PCH_SML1_CLK
SPI_SI RC52 1 2 15_0402_5% SPI_SI_R GPP_C6/SML1CLK V3 PCH_SML1_DAT PCH_SMB_CLK QC2A 6 1
GPU, EC, Thermal Sensor

S
30 SPI_SI SPI - TOUCH GPP_C7/SML1DATA PM_SMB_CLK 16,32
SPI_SI_1 RC1751 @ 2 33_0402_5% AM7 SML1_ALERT#

D
M2 GPP_B23/SML1ALERT#/PCHHOT# 2N7002KDWH_SOT363-6
GPP_D1/SPI1_CLK

5
M3

G
J4 GPP_D2/SPI1_MISO
SPI_CS0# RC51 1 2 0_0402_5% SPI_CS0#_R V1 GPP_D3/SPI1_MOSI
30 SPI_CS0# GPP_D21/SPI1_IO2
SPI_CS1# RC1741 @ 2 0_0402_5% SPI_CS1#_R V2
M1 GPP_D22/SPI1_IO3 AY13 PCH_SMB_DATA QC2B 3 4
LPC

S
GPP_D0/SPI1_CS# GPP_A1/LAD0/ESPI_IO0 LPC_AD0 28,30 PM_SMB_DAT 16,32
BA13

D
GPP_A2/LAD1/ESPI_IO1 LPC_AD1 28,30
BB13 2N7002KDWH_SOT363-6
C LINK GPP_A3/LAD2/ESPI_IO2 LPC_AD2 28,30
AY12
GPP_A4/LAD3/ESPI_IO3 LPC_AD3 28,30
G3 BA12
CL_CLK GPP_A5/LFRAME#/ESPI_CS# LPC_FRAME# 28,30
G2 BA11 SUS_STAT# 1
G1 CL_DATA GPP_A14/SUS_STAT#/ESPI_RESET# TP81@
CL_RST#
AW9 PCH_PCI_CLK_R RC173 2 1 22_0402_5% +3VALW_PCH
+3V_SPI GPP_A9/CLKOUT_LPC0/ESPI_CLK PCH_PCI_CLK 30
EC_KBRST# 1 2 KBRST# AW13 AY9 CLK_PCI_TPM_R RC1541 2 1 22_0402_5%
30 EC_KBRST# GPP_A0/RCIN# GPP_A10/CLKOUT_LPC1 CLK_PCI_TPM 28
RC182 0_0402_5% AW11 PM_CLKRUN# TPM@
EC_INT_SERIRQ 1 2 SERIRQ AY11 GPP_A8/CLKRUN# SMB_ALERT# 2.2K_0402_5% 2 1 RC1562
28,30 EC_INT_SERIRQ GPP_A6/SERIRQ
RC183 0_0402_5%
5 OF 20
1

SKYLAKE-U_BGA1356
RC60 RC61 REV = 1
?
1K_0402_5% 1K_0402_5%
Check with BIOS, SPI is Dual mode or quad mode @
2

SPI_WP#_R RC54 1 2 15_0402_5% SPI_WP#

+3VALW_PCH
C @ +3V_SPI check CLKRUN# / SUS_STAT# signal if need to connect +3VS C
SPI_HOLD#_R RC55 1 2 15_0402_5% SPI_HOLD# RPC23
+3VS +3VALW_PCH SML0_CLK 4 1
@ SML0_DATA 3 2
RC171 1 2 0_0402_5% PM_CLKRUN# RC111 1 2 8.2K_0402_5%
2.2K_0404_4P2R_5%
RC1721 @ 2
0_0402_5%
+3V_SPI +3V_SPI
* +3VALW_PCH
1. If support DS3, connect to +3VS and don't support EC mirror code;
2. If don't support DS3, connect to +3VALW_PCH and support EC mirror code.
@
1

SML0_ALERT# RC1564 2 1 2.2K_0402_5%

RC179 RC180
1K_0402_5% 1K_0402_5%
@ @ This signal has a weak internal pull-down.
0 = LPC Is selected for EC. (Default)
2

1 = eSPI Is selected for EC.

SPI_WP#_R RC176 1 @ 2 33_0402_5% SPI_WP#_1
Notes:
1. The internal pull-down is disabled after RSMRST#
SPI_HOLD#_R RC178 1 @ 2 33_0402_5% SPI_HOLD#_1 de-asserts.
2. This signal is in the primary wel
+3V_SPI Rising edge of RSMRST#
UC3
SPI_CS0# 1 8
CS# VCC +3VALW_PCH
SPI_SO 2 7 SPI_HOLD# 1
DO HOLD# CC8
+3VALW_PCH Follow CRB, need to check the strap ? SPI_WP# 3 6 SPI_CLK .1U_0402_10V6-K SML1_ALERT# RC1569 1 2150K_0402_5%
B WP# CLK B
@ 4 5 SPI_SI 2
RC1568 2 1 20K_0402_5% SPI_SO_R GND DI +3VALW_PCH +3VS +3VS To enable Direct Connect Interface (DCI), a 150K pull up resistor will need to be
@ added to PCHHOT# pin. This pin must be low during the rising edge of RSMRST#.
RC1565 2 1 20K_0402_5% SPI_SI_R W25Q64FVSSIQ_SO8 (Refer to WW52_MOW)
@
RC1578 2 1 20K_0402_5% SPI_WP#_R

4
3

4
3
@
RC1580 2 1 20K_0402_5% SPI_HOLD#_R RPC25 RPC26

2
+3V_SPI 2.2K_0404_4P2R_5% 2.2K_0404_4P2R_5%

G
UC6

1
2

1
2
SPI_CS1# 1 8
SPI_SO_1 2 CS# VCC 7 SPI_HOLD#_1 PCH_SML1_CLK QC10A 6 1 @

S
DO HOLD# EC_SMB_CLK0 18,30,32
SPI_WP#_1 3 6 SPI_CLK_1

D
WP# CLK 1
Follow CRB, need to check the strap ? 4 5 SPI_SI_1 CC97 2N7002KDWH_SOT363-6
GND DI

5
.1U_0402_10V6-K

G
@ W25Q32FVSSIQ_SO8 @
RC1567 2 1 4.7K_0402_5% SPI_SO_R 2
@
@
RC1566 2 1 4.7K_0402_5% SPI_SI_R PCH_SML1_DAT QC10B 3 4 @

S
EC_SMB_DAT0 18,30,32
@

D
RC1581 2 1 4.7K_0402_5% SPI_WP#_R 2N7002KDWH_SOT363-6

RC64 1 2 1K_0402_5% SPI_HOLD#_R

@
ES@ change to @不上件

Based on WW36 SKL U&Y WOM,

RC64 populated for SKL U ES sample.
In this case, customers must ensure that the
A SPI flash device on the platform A
has HOLD functionality disabled by default.

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 MPC (MISC,JTAG,SPI,LPC,SMB)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Haydn-S
Date: Wednesday, July 22, 2015 Sheet 6 of 46
5 4 3 2 1
 5 4 3 2 1

+3VS +3VS

1 UMA@ 2 GC6_FB_EN @
RC1 10K_0402_5% +3VS RC1561 1 2 2.2K_0402_5% GPP_B18

2
1 2 PCH_GPU_EVENT# @
SKL_ULT ?
RC2 10K_0402_5% RC1563 1 2 2.2K_0402_5% GPP_B22 UC1F RC314 RC503 RC569 RC584
1 2 PXS_PWREN_R 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
LPSS ISH
RC3 10K_0402_5% @ OPT@
1 @ 2 PCH_GPU_RST#_R

1
RC4 10K_0402_5% AN8 P2 BOARD_ID0 BOARD_ID0
AP7 GPP_B15/GSPI0_CS# GPP_D9 P3 BOARD_ID1 BOARD_ID1
AP8 GPP_B16/GSPI0_CLK GPP_D10 P4 BOARD_ID2
GPP_B17/GSPI0_MISO GPP_D11 8 BOARD_ID2
1 @ 2 GC6_FB_EN GPP_B18 AR7 P1 BOARD_ID3 BOARD_ID3
RC8 10K_0402_5% GPP_B18/GSPI0_MOSI GPP_D12

2
D 1 2 PCH_GPU_RST#_R AM5 M4 ISH_I2C0_SDA D
GPP_B19/GSPI1_CS# GPP_D5/ISH_I2C0_SDA ISH_I2C0_SDA 29
RC9 100K_0402_5% AN7 N3 ISH_I2C0_SCL RC566 RC512 RC372 RC598
GPP_B20/GSPI1_CLK GPP_D6/ISH_I2C0_SCL ISH_I2C0_SCL 29
1 @ 2 PXS_PWREN_R 0_0402_5% 2 @ 1 RC184 EC_SCI#_R AP5 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
4,30 EC_SCI# GPP_B21/GSPI1_MISO
RC10 100K_0402_5% GPP_B22 AN5 N1 ISH_I2C1_SDA UMA@ @ @
GPP_B22/GSPI1_MOSI GPP_D7/ISH_I2C1_SDA ISH_I2C1_SDA 29
1 @ 2 PCH_GPU_EVENT# N2 ISH_I2C1_SCL
ISH_I2C1_SCL 29

1
RC11 10K_0402_5% AB1 GPP_D8/ISH_I2C1_SCL
31 UART_RX_DEBUG GPP_C8/UART0_RXD
AB2 AD11
31 UART_TX_DEBUG GPP_C9/UART0_TXD GPP_F10/I2C5_SDA/ISH_I2C2_SDA
W4 AD12
AB3 GPP_C10/UART0_RTS# GPP_F11/I2C5_SCL/ISH_I2C2_SCL
GPP_C11/UART0_CTS#
BOM Control :BOARD_ID1
Connect to GPU signal :
GC6_FB_EN 18 GC6_FB_EN GC6_FB_EN AD1 U1
PXS_PWREN RC39 1 OPT@ 21K_0402_5%PXS_PWREN_R AD2 GPP_C20/UART2_RXD GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA U2
PCH_GPU_EVENT# 20 PXS_PWREN GPP_C21/UART2_TXD GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL
18 PCH_GPU_RST# PCH_GPU_RST# RC40 1 OPT@ 20_0402_5% PCH_GPU_RST#_R AD3 U3
PCH_GPU_RST# PCH_GPU_EVENT# AD4 GPP_C22/UART2_RTS# GPP_D15/ISH_UART0_RTS# U4
18 PCH_GPU_EVENT# GPP_C23/UART2_CTS# GPP_D16/ISH_UART0_CTS#/SML0BALERT#
PCH_PLT_RST#
PXS_PWREN AC1
PCH_I2C_SDA0 U7 GPP_C12/UART1_RXD/ISH_UART1_RXD AC2
GPP_C16/I2C0_SDA GPP_C13/UART1_TXD/ISH_UART1_TXD
BOARD_ID0 BOARD_ID1 Description
PCH_I2C_SCL0 U6 AC3
GPP_C17/I2C0_SCL GPP_C14/UART1_RTS#/ISH_UART1_RTS# AB4 EC_SENSOR_INT
GPP_C15/UART1_CTS#/ISH_UART1_CTS# EC_SENSOR_INT 30
PCH_WLAN_OFF# U8
+3VS 31 PCH_WLAN_OFF# GPP_C18/I2C1_SDA
PCH_BT_OFF# U9 AY8 ISH_GP0 0 0 UMA
31 PCH_BT_OFF# GPP_C19/I2C1_SCL GPP_A18/ISH_GP0 ISH_GP0 29
BA8 ISH_GP1
GPP_A19/ISH_GP1 ISH_GP1 29
RPC68 AH9 BB7 ISH_GP2
GPP_F4/I2C2_SDA GPP_A20/ISH_GP2 ISH_GP2 29
1 4 PCH_WLAN_OFF# AH10 BA7 ISH_GP3
GPP_F5/I2C2_SCL GPP_A21/ISH_GP3 ISH_GP3 29
2 3 PCH_BT_OFF# AY7 DIS
AH11 GPP_A22/ISH_GP4 AW7
GPP_F6/I2C3_SDA GPP_A23/ISH_GP5 0 1
+3VALW_PCH 10K_0404_4P2R_5% AH12 AP13 GPP_A12 1 TP205 @
GPP_F7/I2C3_SCL GPP_A12/BM_BUSY#/ISH_GP6
AF11 check GPP_A12
RPC69 AF12 GPP_F8/I2C4_SDA
1 4 PCH_I2C_SDA0 GPP_F9/I2C4_SCL
2 3 PCH_I2C_SCL0
C 6 OF 20 C
SKYLAKE-U_BGA1356
10K_0404_4P2R_5% REV = 1 ? ISH_I2C0_SDA RC25311 ISH@ 2 0_0402_5% EC_SMB_DAT3
EC_SMB_DAT3 28,30
@ ISH_I2C0_SCL RC25321 ISH@ 2 0_0402_5% EC_SMB_CLK3
@ SKL_ULT ? EC_SMB_CLK3 28,30
UC1G

AUDIO

RC43 1 2 33_0402_5% HDA_SYNC BA22

29 PCH_HDA_SYNC HDA_SYNC/I2S0_SFRM
RC42 1 2 33_0402_5% HDA_BCLK AY22
+3VALW_PCH +3VS 29 PCH_HDA_BCLK HDA_BLK/I2S0_SCLK
HDA_SDOUT BB22 SDIO/SDXC
BA21 HDA_SDO/I2S0_TXD
29 PCH_HDA_SDIN0 HDA_SDI0/I2S0_RXD
RC1600 1 @ 2 1K_0402_5% AY21 AB11
RC44 1 2 33_0402_5% HDA_RST# AW22 HDA_SDI1/I2S1_RXD GPP_G0/SD_CMD AB13
29 PCH_HDA_RST# HDA_RST#/I2S1_SCLK GPP_G1/SD_DATA0
RC47 1 @ 2 1K_0402_5% HDA_SDOUT J5 AB12
AY20 GPP_D23/I2S_MCLK GPP_G2/SD_DATA1 W12
* AW20 I2S1_SFRM
I2S1_TXD
GPP_G3/SD_DATA2
GPP_G4/SD_DATA3
W11
HDA_SDO This signal has a weak internal pull-down. W10
AK7 GPP_G5/SD_CD# W8
0 = Enable security measures defined in the Flash Descriptor. GPP_F1/I2S2_SFRM GPP_G6/SD_CLK
AK6 W7
1 = Disable Flash Descriptor Security(override). This strap GPP_F0/I2S2_SCLK GPP_G7/SD_WP
AK9
should only be asserted high during external pull-up in AK10 GPP_F2/I2S2_TXD BA9
manufacturing/debug environments ONLY. GPP_F3/I2S2_RXD GPP_A17/SD_PWR_EN#/ISH_GP7 BB9
GPP_A16/SD_1P8_SEL
H5 AB7 SD_RCOMP RC49 1 2 200_0402_1%
D7 GPP_D19/DMIC_CLK0 SD_RCOMP
GPP_D20/DMIC_DATA0
For EMI D8 AF13
PCH_HDA_SDIN0 C8 GPP_D17/DMIC_CLK1 GPP_F23
GPP_D18/DMIC_DATA1
PCH_BEEP AW5
29 PCH_BEEP GPP_B14/SPKR
1
EMC_NS@
B CC7 B
10P_0402_50V8J 7 OF 20 AO5804EL_SC89-6
2 SKYLAKE-U_BGA1356
REV = 1 ? QC45A
@ PCH_I2C_SCL0 6 1
EC_I2C_CLK4 30
+3VS +3VS @

@
RC45 1 2 33_0402_5% HDA_SDOUT RC14 1 2 2.2K_0402_5% PCH_BEEP 2
29 PCH_HDA_SDOUT
RC46 1 2 0_0402_5% 5
30 PCH_ME_PROTECT

@
PCH_I2C_SDA0 3 4
EC_I2C_DAT4 30

QC45B
Default When AO5804EL_SC89-6
Pin Name Strap Description Configuration Value Sampled
Internal PD
0 = Disable “Top Swap”
SPKR / Top Swap 0 Rising edge
GPP_B14 Override
mode. (Default)
1 = Enable “Top Swap”
* of PCH_PWROK PCH_I2C_SCL0 RC2533 1 2 0_0402_5% EC_I2C_CLK4
PCH_I2C_SDA0 RC2534 1 2 0_0402_5% EC_I2C_DAT4
mode.
Internal PD
0 = Disable “No Reboot”
GSPI0_MOSINo Reboot
A
/GPP_B18
mode. (Default)
1 = Enable “No Reboot”
* 0 Rising edge A

mode of PCH_PWROK

Internal PD
0 = SPI (Default) Title
GSPI1_MOSIBoot BIOS 1 = LPC
* Rising edge Security Classification LC Future Center Secret Data
/GPP_B22 Strap Bit 0 of PCH_PWROK Issued Date 2014/12/11 Deciphered Date 2015/12/11 MCP (LPSS,ISH,AUDIO,SDIO)
BBS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Haydn-S
Date: Wednesday, July 22, 2015 Sheet 7 of 46
5 4 3 2 1
 5 4 3 2 1

D D

SKL_ULT
?
UC1H

SSIC / USB3
PCIE/USB3/SATA
H8 USB30_RX_N1 29
USB3_1_RXN G8
USB3_1_RXP USB30_RX_P1 29 Left USB3.0
H13 C13 USB30_TX_N1 29
G13 PCIE1_RXN/USB3_5_RXN USB3_1_TXN D13
PCIE1_RXP/USB3_5_RXP USB3_1_TXP USB30_TX_P1 29
B17
A17 PCIE1_TXN/USB3_5_TXN J6
PCIE1_TXP/USB3_5_TXP USB3_2_RXN/SSIC_1_RXN USB30_RX_N2 33
H6 USB30_RX_P2 33 Right USB3.0
G11 USB3_2_RXP/SSIC_1_RXP B13
PCIE2_RXN/USB3_6_RXN USB3_2_TXN/SSIC_1_TXN USB30_TX_N2 33
F11 A13 USB30_TX_P2 33
D16 PCIE2_RXP/USB3_6_RXP USB3_2_TXP/SSIC_1_TXP
C16 PCIE2_TXN/USB3_6_TXN J10
PCIE2_TXP/USB3_6_TXP USB3_3_RXN/SSIC_2_RXN H10
H16 USB3_3_RXP/SSIC_2_RXP B15
G16 PCIE3_RXN USB3_3_TXN/SSIC_2_TXN A15
D17 PCIE3_RXP USB3_3_TXP/SSIC_2_TXP
C17 PCIE3_TXN E10
PCIE3_TXP USB3_4_RXN F10
G15 USB3_4_RXP C15
F15 PCIE4_RXN USB3_4_TXN D15
B19 PCIE4_RXP USB3_4_TXP
A19 PCIE4_TXN AB9
PCIE4_TXP USB2N_1 USB20_N0 26
AB10 USB20_P0 26 Camera_Conn
F16 USB2P_1
E16 PCIE5_RXN AD6
PCIE5_RXP USB2N_2 USB20_N1 33
C19 AD7 USB20_P1 33 Right USB2.0
D19 PCIE5_TXN USB2P_2
C PCIE5_TXP AH3 C
USB2N_3 USB20_N2 29
31 PCIE_PRX_DTX_N6 PCIE_PRX_DTX_N6 G18 AJ3 USB20_P2 29 Left USB2.0
PCIE_PRX_DTX_P6 F18 PCIE6_RXN USB2P_3
WLAN 31 PCIE_PRX_DTX_P6 PCIE6_RXP
PCIE631 CC177 2 1 .1U_0402_10V6-K PCIE_PTX_DRX_N6 D20 AD9 USB20_N3 29
PCIE_PTX_C_DRX_N6 PCIE6_TXN USB2N_4
CC188 2 1 .1U_0402_10V6-K PCIE_PTX_DRX_P6 C20 AD10 USB20_P3 29 Card Reader
31 PCIE_PTX_C_DRX_P6 PCIE6_TXP USB2P_4
SATA_PRX_DTX_N0 F20 AJ1 USB20_N4 31
33 SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 E20 PCIE7_RXN/SATA0_RXN USB2N_5 AJ2
PCIE7_RXP/SATA0_RXP USB2P_5 USB20_P4 31 Mini Card BT
33 SATA_PRX_DTX_P0 SATA_PTX_DRX_N0 B21 USB2
33 SATA_PTX_DRX_N0 SATA_PTX_DRX_P0 A21 PCIE7_TXN/SATA0_TXN AF6
33 SATA_PTX_DRX_P0 PCIE7_TXP/SATA0_TXP USB2N_6 AF7
USB2P_6 EC T8396 Sensor
G21
F21 PCIE8_RXN/SATA1A_RXN AH1
PCIE8_RXP/SATA1A_RXP USB2N_7 USB20_N6 26
D21 AH2 USB20_P6 26 Touch Panel
C21 PCIE8_TXN/SATA1A_TXN USB2P_7
PCIE8_TXP/SATA1A_TXP AF8
USB2N_8 USB20_N7 38
PCIE_CRX_GTX_N0 E22 AF9 USB20_P7 38 DC_IN combo USB2.0
PCIE_CRX_GTX_P0 E23 PCIE9_RXN USB2P_8
PCIE_CTX_C_GRX_N0 0.22U_0402_10V6K OPT@1 2 CC16 PCIE_CTX_GRX_N0 B23 PCIE9_RXP AG1
PCIE_CTX_C_GRX_P0 0.22U_0402_10V6K OPT@1 2 CC14 PCIE_CTX_GRX_P0 A23 PCIE9_TXN USB2N_9 AG2
PCIE9_TXP USB2P_9
PCIE_CRX_GTX_N1 F25 AH7
PCIE_CRX_GTX_P1 E25 PCIE10_RXN USB2N_10 AH8
PCIE_CTX_C_GRX_N1 0.22U_0402_10V6K OPT@1 2 CC15 PCIE_CTX_GRX_N1 D23 PCIE10_RXP USB2P_10
third-part dGPU PCIEP9 PCIE10_TXN
PCIE_CTX_C_GRX_P1 0.22U_0402_10V6K OPT@1 2 CC17 PCIE_CTX_GRX_P1 C23 AB6 USB2_COMP RC118 2 1 113_0402_1% USBRBIAS
PCIE10_TXP USB2_COMP AG3 USB2_ID RC2535 2 1 0_0402_5%
USB2_ID Width 20Mil
PCIE_RCOMPN and PCIE_RCOMPP RC119 1 2 100_0402_1% PCIE_RCOMPN F5 AG4 USB2_VBUSSENSE RC2536 2 1 1K_0402_5% Space 15Mil
PCIE_RCOMPP E5 PCIE_RCOMPN USB2_VBUSSENSE
Trace Width: 12-15mil PCIE_RCOMPP A9 Length 500Mil
USB_OC0# USB_OC0# 33
Differential between RCOMPP/RCOMPN PAD @ TP20 1 XDP_PRDY# D56 GPP_E9/USB2_OC0# C9 USB_OC1#
PROC_PRDY# GPP_E10/USB2_OC1# USB_OC1# 29
PAD @ TP19 1 XDP_PREQ# D61 D9 USB_OC2#
PIRQA# BB11 PROC_PREQ# GPP_E11/USB2_OC2# B9 USB_OC3#
B GPP_A7/PIRQA# GPP_E12/USB2_OC3# USB_OC3# 38 B
PCIE_CRX_GTX_N2 E28 J1 GPP_E4
PCIE_CRX_GTX_P2 E27 PCIE11_RXN/SATA1B_RXN GPP_E4/DEVSLP0 J2
PCIE_CTX_C_GRX_N2 0.22U_0402_10V6K OPT@1 2 CC18 PCIE_CTX_GRX_N2 D24 PCIE11_RXP/SATA1B_RXP GPP_E5/DEVSLP1 J3
PCIE_CTX_C_GRX_P2 0.22U_0402_10V6K OPT@1 2 CC19 PCIE_CTX_GRX_P2 C24 PCIE11_TXN/SATA1B_TXN GPP_E6/DEVSLP2
PCIE_CRX_GTX_N3 E30 PCIE11_TXP/SATA1B_TXP H2 SATA0GP
PCIE_CRX_GTX_P3 F30 PCIE12_RXN/SATA2_RXN GPP_E0/SATAXPCIE0/SATAGP0 H3 SATA1GP
PCIE_CTX_C_GRX_N3 0.22U_0402_10V6K OPT@1 2 CC20 PCIE_CTX_GRX_N3 A25 PCIE12_RXP/SATA2_RXP GPP_E1/SATAXPCIE1/SATAGP1 G4 SATA2GP
PCIE_CTX_C_GRX_P3 0.22U_0402_10V6K OPT@1 2 CC21 PCIE_CTX_GRX_P3 B25 PCIE12_TXN/SATA2_TXN GPP_E2/SATAXPCIE2/SATAGP2
PCIE12_TXP/SATA2_TXP H1 BOARD_ID2
GPP_E8/SATALED# BOARD_ID2 7

8 OF 20 +3VS
SKYLAKE-U_BGA1356
REV = 1 ?
@
@
GPP_E4 RC1617 2 1 10K_0402_5%
+3VALW_PCH

18 PCIE_CRX_GTX_N[0..3] +3VS
RPC2 RPC17
18 PCIE_CRX_GTX_P[0..3] 1 8 SATA1GP USB_OC0# 8 1
2 7 SATA0GP USB_OC1# 7 2
3 6 SATA2GP USB_OC3# 6 3
18 PCIE_CTX_C_GRX_N[0..3]
4 5 PIRQA# USB_OC2# 5 4
18 PCIE_CTX_C_GRX_P[0..3]
10K_0804_8P4R_5% 10K_0804_8P4R_5%

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 MCP (PCIE,SATA,USB3,USB2)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Haydn-S
Date: Wednesday, July 22, 2015 Sheet 8 of 46
5 4 3 2 1
 5 4 3 2 1

UC1I
SKL_ULT ?

CSI-2

A36 C37
B36 CSI2_DN0 CSI2_CLKN0 D37
C38 CSI2_DP0 CSI2_CLKP0 C32
D38 CSI2_DN1 CSI2_CLKN1 D32
C36 CSI2_DP1 CSI2_CLKP1 C29
D D36 CSI2_DN2 CSI2_CLKN2 D29 D
A38 CSI2_DP2 CSI2_CLKP2 B26
B38 CSI2_DN3 CSI2_CLKN3 A26
CSI2_DP3 CSI2_CLKP3
C31 E13 CSI2_COMP RC73 1 2 100_0402_1%
D31 CSI2_DN4 CSI2_COMP B7
C33 CSI2_DP4 GPP_D4/FLASHTRIG
D33 CSI2_DN5
A31 CSI2_DP5 EMMC
B31 CSI2_DN6 AP2
check the Pull up resistor CSI2_DP6 GPP_F13/EMMC_DATA0
A33 AP1
+3VS B33 CSI2_DN7 GPP_F14/EMMC_DATA1 AP3
CSI2_DP7 GPP_F15/EMMC_DATA2 AN3
RPC3 @ A29 GPP_F16/EMMC_DATA3 AN1
1 8 PCIE_CLKREQ2# B29 CSI2_DN8 GPP_F17/EMMC_DATA4 AN2
2 7 PCIE_CLKREQ3# C28 CSI2_DP8 GPP_F18/EMMC_DATA5 AM4
3 6 PCIE_CLKREQ1# D28 CSI2_DN9 GPP_F19/EMMC_DATA6 AM1
4 5 PCIE_CLKREQ4# A27 CSI2_DP9 GPP_F20/EMMC_DATA7
B27 CSI2_DN10 AM2
10K_0804_8P4R_5% C27 CSI2_DP10 GPP_F21/EMMC_RCLK AM3
RPC4 D27 CSI2_DN11 GPP_F22/EMMC_CLK AP4
4 1 WLAN_CLKREQ# CSI2_DP11 GPP_F12/EMMC_CMD
3 2 GPU_PCIE_CLKREQ# AT1 EMMC_RCOMP RC50 1 2 200_0402_1%
EMMC_RCOMP
10K_0404_4P2R_5% 9 OF 20
SKYLAKE-U_BGA1356
REV = 1 ?
@

SUSCLK RC95 1 @ 2 1K_0402_5%

UC1J SKL_ULT ?

C CLOCK SIGNALS C

CLK_PCIE_GPU# D42
18 CLK_PCIE_GPU# CLKOUT_PCIE_N0
PCIE CLK0 GPU CLK_PCIE_GPU C42
18 CLK_PCIE_GPU CLKOUT_PCIE_P0
GPU_PCIE_CLKREQ# AR10
18 GPU_PCIE_CLKREQ# GPP_B5/SRCCLKREQ0#
B42
A42 CLKOUT_PCIE_N1 F43 CLK_PCIE_XDP# 1 TP85 @
PCIE_CLKREQ1# AT7 CLKOUT_PCIE_P1 CLKOUT_ITPXDP_N E43 CLK_PCIE_XDP 1 TP87 @
GPP_B6/SRCCLKREQ1# CLKOUT_ITPXDP_P
D41 BA17 SUSCLK
CLKOUT_PCIE_N2 GPD8/SUSCLK SUSCLK 31
C41
PCIE_CLKREQ2# AT8 CLKOUT_PCIE_P2 E37 XTAL24_IN
GPP_B7/SRCCLKREQ2# XTAL24_IN E35 XTAL24_OUT +VCCCLK5
D40 XTAL24_OUT
C40 CLKOUT_PCIE_N3 E42 DIFFCLK_BIASREF RC72 1 2 2.7K_0402_1% RC1555
PCIE_CLKREQ3# AT10 CLKOUT_PCIE_P3 XCLK_BIASREF DIFFCLK_BIASREF 1 2 60.4_0402_1%
GPP_B8/SRCCLKREQ3# AM18 RTC_X1 Cannonlake@
B40 RTCX1 AM20 RTC_X2
A40 CLKOUT_PCIE_N4 RTCX2
PCIE_CLKREQ4# AU8 CLKOUT_PCIE_P4 AN18 SRTC_RST#
GPP_B9/SRCCLKREQ4# SRTCRST# AM16 RTC_RST#
CLK_PCIE_WLAN# E40 RTCRST#
31 CLK_PCIE_WLAN# CLKOUT_PCIE_N5
PCIE CLK5 WLAN CLK_PCIE_WLAN E38
31 CLK_PCIE_WLAN CLKOUT_PCIE_P5
WLAN_CLKREQ# AU7
31 WLAN_CLKREQ# GPP_B10/SRCCLKREQ5#
1
CC3
VCCRTC 1U_0402_10V6K
10 OF 20
SKYLAKE-U_BGA1356 2
REV = 1 ?
RC33 1 2 20K_0402_1% SRTC_RST#
B @ RC34 1 2 20K_0402_1% RTC_RST# B
RTC_RST# 30
1
CC6
1U_0402_10V6K

1
2

TP71
RTC_X1 @
check if need to change to 1M_0402_1% follow PDG, RC71 2 1 1M_0402_5%
CRB is 1M_0402_5% YC2 RC32 2 1 10M_0402_5% RTC_X2

2 3 XTAL24_OUT YC1
GND1 OSC2 1 2
XTAL24_IN 1 4
OSC1 GND2 32.768KHZ_12.5PF_202740-PG14
2 2
1
1 24MHZ_6PF_7V24000032 CC4 CC5
CC12 CC11 9P_0402_50V8-B 9P_0402_50V8-B
4.7P_0402_50V8B 4.7P_0402_50V8B 1 1
@ 2@
2

need to use 38.4MHz (30ohm) for Cannonlake-u

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 MCP (CSI2,EMMC,CLOCK)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Haydn-S
Date: Wednesday, July 22, 2015 Sheet 9 of 46
5 4 3 2 1
 5 4 3 2 1

SKL_ULT
?
UC1K
SYSTEM POWER MANAGEMENT
AT11 PM_SLP_S0# 1 @
GPP_B12/SLP_S0# AP15 PCH_SLP_S3#_R TP236 RC58 1 2 0_0402_5%
GPD4/SLP_S3# PCH_SLP_S3# 12,30
PCH_PLT_RST# AN10 BA16 PCH_SLP_S4#_R RC56 1 2 0_0402_5%
18,28,30,31 PCH_PLT_RST# GPP_B13/PLTRST# GPD5/SLP_S4# PCH_SLP_S4# 30
SYS_RESET# B5 AY16 1 @
D AY17 SYS_RESET# GPD10/SLP_S5# TP53 D
30 EC_RSMRST# RSMRST# AN15 1 @
TP21 @ 1 CPU_PROCPWRGD A68 SLP_SUS# AW15 TP55
VCCST_PWRGD_R RC93 1 2 60.4_0402_1% VCCST_PWRGD B65 PROCPWRGD SLP_LAN# BB17
VCCST_PWRGD GPD9/SLP_WLAN# AN16
RC139 1 2 0_0402_5% SYS_PWROK_R B6 GPD6/SLP_A#
30 EC_SYS_PWROK SYS_PWROK
RC126 1 2 0_0402_5% PCH_PWROK_R BA20 BA15 EC_PBTN_OUT#_R RC2526 1 2 0_0402_5%
30 EC_PCH_PWROK PCH_PWROK GPD3/PWRBTN# EC_PBTN_OUT# 30
PCH_DPWROK_R BB20 AY15 PCH_ACIN
DSW_PWROK GPD1/ACPRESENT AU13 BATLOW#
EC_SUSWARN# AR13 GPD0/BATLOW#
TP5 @ 1 EC_SUSACK#_R AP11 GPP_A13/SUSWARN#/SUSPWRDNACK VCCRTC
GPP_A15/SUSACK# AU11 PME# 1 @ TP89
PCIE_WAKE# BB15 GPP_A11/PME# AP16 INTVRMEN RC41 2 1 330K_0402_5%
31 PCIE_WAKE# WAKE# INTRUDER#
LAN_WAKE# AM15
AW17 GPD2/LAN_WAKE# AM10 1 @ TP93
AT15 GPD11/LANPHYPC GPP_B11/EXT_PWR_GATE# AM11 1 @ TP96
GPD7/RSVD GPP_B2/VRALERT#

11 OF 20
SKYLAKE-U_BGA1356
REV = 1 ?
@

PCH_ACIN 0_0402_5% 2 1 RC65

EC_PCH_ACIN 30
+3VALW_PCH +3VS

RC74 1 2 10K_0402_5% PCH_ACIN RC80 1 2 10K_0402_5% SYS_RESET#

RC75 1 2 8.2K_0402_5% BATLOW#

C RC76 1 2 1K_0402_5% PCIE_WAKE# Follow CRB change to 1kohm C

+3VALW_PCH

+VCCST_CPU +VCCSTG

RC78 @1 2 10K_0402_5% EC_SUSWARN#

2
RC90 1 2 10K_0402_5% LAN_WAKE# @
+3VALW RC137 RC1554
1K_0402_5% 1K_0402_5%

2
1 2 EMC_NS@ EC_RSMRST#

1
CC1254 1000P_0402_50V7K RC136
10K_0402_5% VCCST_PWRGD_R
1 2 EMC_NS@ PCH_PWROK_R

3
CC104 1000P_0402_50V7K D

1
5 QC6B 2
@
1 2 EMC_NS@ PCH_DPWROK_R G
CC103 1000P_0402_50V7K 2N7002KDWH_SOT363-6 CC140

6
D S 1000P_0402_50V7K

4
1 2 EMC_NS@ SYS_PWROK_R RC138 1 2 0_0402_5% 2 QC6A 1
30 EC_VCCST_PWRGD @ EMC_NS@
CC101 1000P_0402_50V7K G
@ 1 2N7002KDWH_SOT363-6
1 2 EMC@ PCH_PLT_RST# CC46 S

1
CC1255 33P_0402_50V8J 0.01U_0402_16V7K
@
EMC_NS@
2
PCH_SLP_S3# DC4 1 2 @

B
For EMC RB751V-40_SOD323-2 B

RC1599 1 2 0_0402_5%

100K_0402_5% 2 1 RC92 PCH_PLT_RST#

PCH_DPWROK_R RC192 1 2 0_0402_5% EC_RSMRST#

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 MCP (SYSTEM PWR MANAGEMENT)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Haydn-S
Date: Wednesday, July 22, 2015 Sheet 10 of 46
5 4 3 2 1
 5 4 3 2 1

+CPU_CORE ? +CPU_CORE +VCC_GT

SKL_ULT SKL_ULT ?
UC1L +VCC_GT UC1M
CPU POWER 1 OF 4
CPU POWER 2 OF 4
A30 G32 +CPU_CORE +VCC_GT N70
A34 VCC_A30 VCC_G32 G33 A48 VCCGT_N70 N71
A39 VCC_A34 VCC_G33 G35 A53 VCCGT_A48 VCCGT_N71 R63
A44 VCC_A39 VCC_G35 G37 A58 VCCGT_A53 VCCGT_R63 R64
AK33 VCC_A44 VCC_G37 G38 VCORE_VCC_SEN RC77 1 2 100_0402_1% VCCGT_VCC_SEN RC83 1 2 100_0402_1% A62 VCCGT_A58 VCCGT_R64 R65
AK35 VCC_AK33 VCC_G38 G40 A66 VCCGT_A62 VCCGT_R65 R66
AK37 VCC_AK35 VCC_G40 G42 AA63 VCCGT_A66 VCCGT_R66 R67
AK38 VCC_AK37 VCC_G42 J30 VCORE_VSS_SEN RC82 1 2 100_0402_1% VCCGT_VSS_SEN RC98 1 2 100_0402_1% AA64 VCCGT_AA63 VCCGT_R67 R68
AK40 VCC_AK38 VCC_J30 J33 AA66 VCCGT_AA64 VCCGT_R68 R69
AL33 VCC_AK40 VCC_J33 J37 AA67 VCCGT_AA66 VCCGT_R69 R70
AL37 VCC_AL33 VCC_J37 J40 AA69 VCCGT_AA67 VCCGT_R70 R71
AL40 VCC_AL37 VCC_J40 K33 AA70 VCCGT_AA69 VCCGT_R71 T62
D VCC_AL40 VCC_K33 VCCGT_AA70 VCCGT_T62 D
AM32 K35 AA71 U65
AM33 VCC_AM32 VCC_K35 K37 AC64 VCCGT_AA71 VCCGT_U65 U68
AM35 VCC_AM33 VCC_K37 K38 AC65 VCCGT_AC64 VCCGT_U68 U71
AM37 VCC_AM35 VCC_K38 K40 AC66 VCCGT_AC65 VCCGT_U71 W63
AM38 VCC_AM37 VCC_K40 K42 AC67 VCCGT_AC66 VCCGT_W63 W64
G30 VCC_AM38 VCC_K42 K43 AC68 VCCGT_AC67 VCCGT_W64 W65
VCC_G30 VCC_K43 AC69 VCCGT_AC68 VCCGT_W65 W66
K32 E32 VCORE_VCC_SEN AC70 VCCGT_AC69 VCCGT_W66 W67
RSVD_K32 VCC_SENSE VCORE_VCC_SEN 44 VCCGT_AC70 VCCGT_W67
E33 VCORE_VSS_SEN SVID AC71 W68
VSS_SENSE VCORE_VSS_SEN 44 VCCGT_AC71 VCCGT_W68
TP91 1 AK32 +VCCST_CPU J43 W69
@ RSVD_AK32 B63 CPU_SVID_ALERT#_R J45 VCCGT_J43 VCCGT_W69 W70
AB62 VIDALERT# A63 CPU_SVID_CLK_R J46 VCCGT_J45 VCCGT_W70 W71
P62 VCCOPC_AB62 VIDSCK D64 CPU_SVID_DAT_R J48 VCCGT_J46 VCCGT_W71 Y62
V62 VCCOPC_P62 VIDSOUT J50 VCCGT_J48 VCCGT_Y62
VCCOPC_V62 G20 J52 VCCGT_J50
VCCSTG_G20 +VCCSTG VCCGT_J52

.1U_0402_10V6-K
H63 @ J53 AK42
VCC_OPC_1P8_H63 VCCGT_J53 VCCGTX_AK42

1
J55 AK43
VCCGT_J55 VCCGTX_AK43

CC42
TP94 1 +V1.8S_EDRAM G61 J56 AK45
VCC_OPC_1P8_G61 VCCGT_J56 VCCGTX_AK45

1
56_0402_5%

100_0402_1%

100_0402_1%
@ J58 AK46

2
VCCGT_J58 VCCGTX_AK46

RC131

RC1544

RC132
TP95 1 AC63 J60 AK48
@
TP97 1 AE63 VCCOPC_SENSE K48 VCCGT_J60 VCCGTX_AK48 AK50
@ VSSOPC_SENSE K50 VCCGT_K48 VCCGTX_AK50 AK52
AE62 K52 VCCGT_K50 VCCGTX_AK52 AK53

2
TP99 1 +VCCEOPIO AG62 VCCEOPIO_AE62 @ K53 VCCGT_K52 VCCGTX_AK53 AK55
@ VCCEOPIO_AG62 K55 VCCGT_K53 VCCGTX_AK55 AK56
TP100 1 AL63 K56 VCCGT_K55 VCCGTX_AK56 AK58
TP101
@ 1 AJ62 VCCEOPIO_SENSE K58 VCCGT_K56 VCCGTX_AK58 AK60
@ VSSEOPIO_SENSE RC133 1 2 220_0402_1% CPU_SVID_ALERT#_R K60 VCCGT_K58 VCCGTX_AK60 AK70
44 VR_SVID_ALRT# VCCGT_K60 VCCGTX_AK70
L62 AL43 删除测点
12 OF 20 L63 VCCGT_L62 VCCGTX_AL43 AL46
SKYLAKE-U_BGA1356 ? VCCGT_L63 VCCGTX_AL46
REV = 1 RC134 1 2 0_0402_5% CPU_SVID_CLK_R L64 AL50
44 VR_SVID_CLK VCCGT_L64 VCCGTX_AL50
@ L65 AL53
L66 VCCGT_L65 VCCGTX_AL53 AL56
RC1545 1 2 0_0402_5% CPU_SVID_DAT_R L67 VCCGT_L66 VCCGTX_AL56 AL60
44 VR_SVID_DAT VCCGT_L67 VCCGTX_AL60
L68 AM48
L69 VCCGT_L68 VCCGTX_AM48 AM50
L70 VCCGT_L69 VCCGTX_AM50 AM52
C VCCGT_L70 VCCGTX_AM52 C
L71 AM53
M62 VCCGT_L71 VCCGTX_AM53 AM56
1, Alert# Route Between CLK and Data VCCGT_M62 VCCGTX_AM56
N63 AM58
N64 VCCGT_N63 VCCGTX_AM58 AU58
N66 VCCGT_N64 VCCGTX_AU58 AU63
N67 VCCGT_N66 VCCGTX_AU63 BB57
N69 VCCGT_N67 VCCGTX_BB57 BB66
VCCGT_N69 VCCGTX_BB66 TP235
TP202
VCCGT_VCC_SEN J70 AK62 VCCGTX_SENSE 1
44 VCCGT_VCC_SEN VCCGT_SENSE VCCGTX_SENSE
VCCGT_VSS_SEN J69 AL61 VSSGTX_SENSE 1
44 VCCGT_VSS_SEN VSSGT_SENSE VSSGTX_SENSE
@
13 OF 20 @
SKYLAKE-U_BGA1356
REV = 1 ?
@

+CPU_CORE

13x10uF 0402 +VCC_GT Backside Cap 8x10uF 0402

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
1 1 1 1 1 1 1 1 1 1 1 1 1 1
CC1086

CC1085

CC1084

CC1080

CC1082

CC1236

CC1237

CC1093

CC1092

CC1091

CC1087

CC1089

CC1238

CC1239

1 1 1 1 1 1 1 1

CC1122

CC1123

CC1124

CC1125

CC1126

CC1127

CC1128

CC1129
2 2 2 2 2 2 2 2 2 2 2 2 2 2
@ 2 2 2 2 2 2 2 2
B B

+VCC_GT
Backside Cap 10x1uF 0201
+CPU_CORE

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M
15x1uF 0201
1 1 1 1 1 1 1 1 1 1 1 1

CC1110

CC1111

CC1112

CC1113

CC1114

CC1115

CC1116

CC1117

CC1118

CC1119

CC1240

CC1241
1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2
CC1095

CC1096

CC1097

CC1098

CC1099

CC1100

CC1101

CC1102

CC1103

CC1104

CC1105

CC1106

CC1107

CC1108

CC1109

@ @ @ @ @ @
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
@ @ @ @ @ @ @

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 MCP (CPU PWR1)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Haydn-S
Date: Wednesday, July 22, 2015 Sheet 11 of 46
5 4 3 2 1
 5 4 3 2 1

+VCCIO
3.1A 2x10uF, 4x1uF

10U_0402_6.3V6M

10U_0402_6.3V6M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0402_10V6K

1U_0402_10V6K

1U_0402_10V6K

1U_0402_10V6K
@ CC1218

@ CC1230

@ CC1231

@ CC1232
+VCCIO 1 1 1 1 1 1 1 1 1 1

CC1152

CC1153

CC1158

CC1159

CC1160

CC1161
+1.35V_CPU
?
UC1N SKL_ULT

CPU POWER 3 OF 4 2 2 2 2 2 2 2 2 2 2
+1.35V_CPU
AU23 AK28 @
AU28 VDDQ_AU23 VCCIO_AK28 AK30
AU35 VDDQ_AU28 VCCIO_AK30 AL30
2A , 3x22uF, 6x10uF, 4x1uF VDDQ_AU35 VCCIO_AL30
AU42 AL42
BB23 VDDQ_AU42 VCCIO_AL42 AM28
BB32 VDDQ_BB23 VCCIO_AM28 AM30 +VCCSA
VDDQ_BB32 VCCIO_AM30
22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M
BB41 AM42
BB47 VDDQ_BB41 VCCIO_AM42
D 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VDDQ_BB47 D
C1093

C1094

C1095

CC1168

CC1169

CC1170

CC1171

CC1222

CC1223

CC1243

CC1244

CC1224

CC1225

CC1226

CC1227
BB51 AK23 +VCCSA
VDDQ_BB51 VCCSA_AK23 AK25
VCCSA_AK25 G23
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 VCCSA_G23
4.5A 10x10uF, 7x1uF
+VDDQ_CPU_CLK AM40 G25
@ @ @ VDDQC VCCSA_G25 G27
VCCSA_G27

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M
+VCCST_CPU A18 G28
VCCST VCCSA_G28 J22
VCCSA_J22 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

CC1132

CC1133

CC1134

CC1135

CC1136

CC1137

CC1138

CC1251

CC1252

CC1253

CC1139

CC1140

CC1141

CC1142

CC1143

CC1144

CC1145
+VCCSTG A22 J23
VCCSTG_A22 VCCSA_J23 J27
AL23 VCCSA_J27 K23
+VCCSFR_OC VCCPLL_OC VCCSA_K23 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
K25
K20 VCCSA_K25 K27 @ @ @
K21 VCCPLL_K20 VCCSA_K27 K28
+VCCPLL_CPU VCCPLL_K21 VCCSA_K28 K30
+VCCSTG +VCCST_CPU VCCSA_K30
+VDDQ_CPU_CLK AM23 VCCIO_SENSE 1 TP204 @
VCCIO_SENSE AM22 VSSIO_SENSE 1 TP157 @
120mA VSSIO_SENSE

1U_0402_10V6K
+1.35V_CPU RC1497 1 2 0_0402_5% +VCCIO RC103 1 2 0_0402_5% H21 VCCSA_VSS_SEN
VSSSA_SENSE VCCSA_VSS_SEN 44
1U_0201_6.3V6-M

10U_0402_6.3V6M

1 H20 VCCSA_VCC_SEN
VCCSA_SENSE VCCSA_VCC_SEN 44

1U_0402_10V6K

CC86
1@ 1 +VCCST_CPU RC1604 1 2 0_0402_5%
CC1229

CC1228

1
14 OF 20

CC87
@ SKYLAKE-U_BGA1356
2 REV =1 ?
2 2 @
2

+VCCSA
+VCCSFR_OC +VCCPLL_CPU

120mA
RC104 1 2 0_0402_5% +VCCST_CPU RC105 1 2 0_0402_5%
1U_0201_6.3V6-M

1U_0402_10V6K
0.1U_0402_10V7K
VCCSA_VCC_SEN RC101 1 2 100_0402_1%
1 1 1

CC1249
CC85

CC84
C C
VCCSA_VSS_SEN RC102 1 2 100_0402_1% +1.0VALW +VCCST_CPU
2 2 2 @

RC1605 1 2 0_0402_5%

Reserved for VCCST/VCCSTG/VCCPLL power optimized

+1.0VALW +VCCST_CPU
+1.0VALW AON7408L_DFN8-5 +VCCIO QC19
QC11 AO3402_SOT-23-3
B B

1 3
1 D S
S1

10U_0603_6.3V6M

10U_0603_6.3V6M
5 2 CC79
D S2

1
G
22U_0603_6.3V6-M

10U_0603_6.3V6M

3 1 1
S3
10U_0603_6.3V6M

22U_0603_6.3V6-M

CC80
1 1 @ RC135

2
G
CC71

CC72

1 1 470_0603_5%
CC1250

C1102
4

1
@ 2 2 @

2
2 2 @ RC124
2 2 470_0603_5% B+

1
1 2 RC142
B+ 100K_0402_5% QC14
DMG1012T-7_SOT523-3
+3VALW VCCST_EN# 2

1
+3VALW RC127 1 2 100K_0402_5%
QC13 6 @

3
0.01U_0402_25V7K

0.01U_0402_25V7K
6 DMG1012T-7_SOT523-3
1 VCCIO_EN# 2 QC16A 1
CC77

CC81
QC12A AO5804EL_SC89-6
AO5804EL_SC89-6 @ RC1411 2 VCCST_EN# 2

3
RC128 1 2VCCIO_EN# 2 47K_0402_5%
47K_0402_5% 2 2
2

@
RC1575 1
47K_0402_5% 1
3
3
QC16B
1

QC12B AO5804EL_SC89-6
AO5804EL_SC89-6 EC_VCCST_EN 5
30 EC_VCCST_EN
RC1577 1 2 0_0402_5% VCCIO_EN 5
30 EC_VCCIO_EN
+VCCST_CPU switch
DC1 1 2 @
10,30 PCH_SLP_S3# 4
RB751V-40_SOD323-2 4
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 MCP (CPU PWR2)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Haydn-S
Date: Wednesday, July 22, 2015 Sheet 12 of 46
5 4 3 2 1
 5 4 3 2 1

+1.0VALW 0_0603_5%1 2 RC1503 +VCCAMPHY

+1.0VALW 0_0603_5%1 2 RC1504 +VCCAPLL_1P0

D +VCCHDA D

+3VS RC1585 1 @ 2 0_0402_5%

+3VALW_PCH RC1586 1 2 0_0402_5%

+1.0VALW RC1620 1 2 0_0402_5% VCCMPHYON_1P0_L1

1U_0402_10V6K
@
1

CC144
2

+3VALW_PCH

0.696A
+1.0VALW

1U_0402_10V6K
Near AB19
1

CC141
@ @ @ @ @

1U_0402_10V6K

1U_0402_10V6K

1U_0402_10V6K

1U_0402_10V6K

1U_0402_10V6K
22mA 2.574A 1 1 1 1 1
+1.0VALW +1.0VALW ?

CC156

CC164

CC172

CC173

CC174
1U_0402_10V6K
22U_0603_6.3V6-M
1 1 2 SKL_ULT

CC158
UC1O

CC153
CPU POWER 4 OF 4 2 2 2 2 2
+VCCDSW_1P0 2 2 +3VALW_PCH
AB19

1U_0402_10V6K

1U_0402_10V6K
@
AB20 VCCPRIM_1P0_AB19 AK15 20mA
1 VCCPRIM_1P0_AB20 VCCPGPPA
Near Y15 1 +3VALW_PCH
P18 AG15

CC145

CC175
4mA

1U_0402_10V6K
@
2.1A VCCPRIM_1P0_P18 VCCPGPPB Y16 6mA
+1.0VALW Near AF18 VCCPGPPC 1
AF18 Y15

CC176
@ 8mA
2 AF19 VCCPRIM_CORE_AF18 VCCPGPPD T16 6mA 2
VCCPRIM_CORE_AF19 VCCPGPPE +1.8VALW
V20 AF16 161mA

1U_0402_10V6K
1U_0201_6.3V6-M
22U_0603_6.3V6-M

C C
VCCPRIM_CORE_V20 VCCPGPPF +1.8VALW 2
1 1 PCH Internal VRM V21 AD15 41mA 1
VCCPRIM_CORE_V21 VCCPGPPG
CC148

CC147

CC142
@ +3VALW_PCH
AL1 V19

1U_0402_10V6K
Near N15

.1U_0402_10V6-K
DCPDSW_1P0 VCCPRIM_3P3_V19
2 2 2 1 1
K17 T1

CC143
+1.0VALW CC149
88mA VCCMPHYON_1P0_L1 L1 VCCMPHYAON_1P0_K17 VCCPRIM_1P0_T1
+VCCAMPHY VCCMPHYAON_1P0_L1 AA1 6mA
N15 VCCATS_1P8 2 2
1U_0402_10V6K
22U_0603_6.3V6-M

@ N16 VCCMPHYGT_1P0_N15 AK17 1mA

1 1 VCCMPHYGT_1P0_N16 VCCRTCPRIM_3P3
C1096

N17
CC151

P15 VCCMPHYGT_1P0_N17 AK19 1mA

VCCMPHYGT_1P0_P15 VCCRTC_AK19 VCCRTC
P16 BB14

1U_0402_10V6K
Near K15

.1U_0402_10V6-K
2 2 VCCMPHYGT_1P0_P16 VCCRTC_BB14
1 1
K15 BB10 VCCRTCEXT

CC1242
CC146
L15 VCCAMPHYPLL_1P0_K15 DCPRTC

0.1U_0402_10V7K
VCCAMPHYPLL_1P0_L15 A14 35mA
VCCCLK1 +1.0VALW 2 2
22mA V15
1U_0402_10V6K

+VCCAPLL_1P0 VCCAPLL_1P0 1

CC58
K19 29mA 0_0603_5%1 2 RC1587 +1.0VALW

0.1U_0402_10V7K
1 VCCCLK2
AB17
CC154
22U_0603_6.3V6-M

+1.0VALW VCCPRIM_1P0_AB17 1
Y18 L21

CC56
@ 24mA

22U_0603_6.3V6-M
1 VCCPRIM_1P0_Y18 VCCCLK3 +1.0VALW 2
C1097

+VCCHDA @ 1
2

C1098
0.118A AD17 N20 33mA
1U_0402_10V6K

1 +3VALW_PCH VCCDSW_3P3_AD17 VCCCLK4 +VCCCLK4 2

AD18
CC165

2 @ AJ17 VCCDSW_3P3_AD18 L19 4mA

VCCDSW_3P3_AJ17 VCCCLK5 +VCCCLK5 2
2 68mA AJ19 A10 10mA
VCCHDA VCCCLK6 +1.0VALW

1U_0402_10V6K
+3VALW_PCH
11mA AJ16 AN11 1 TP179 @ PAD 1
VCCSPI GPP_B0/CORE_VID0

CC57
AN13 1 TP180 @ PAD
0.642A AF20 GPP_B1/CORE_VID1
+1.0VALW VCCSRAM_1P0_AF20
AF21
1U_0402_10V6K

1 VCCSRAM_1P0_AF21 2
T19
CC159

Near AF20 VCCSRAM_1P0_T19

T20
VCCSRAM_1P0_T20
2 75mA AJ21
+3VALW_PCH VCCPRIM_3P3_AJ21
1U_0402_10V6K

1
AK20
CC171

+1.0VALW VCCPRIM_1P0_AK20
N18 +VCCCLK4 0_0603_5%1 2 RC1588 +1.0VALW
B 2 VCCAPLLEBB B
1U_0402_10V6K

1
CC169

22U_0603_6.3V6-M
15 OF 20 @
SKYLAKE-U_BGA1356 1

C1099
2 REV = 1 ?
@
2
33mA
+1.0VALW
Near A18
+VCCCLK5 0_0603_5%1 2 RC1589 +1.0VALW

22U_0603_6.3V6-M
@ 1

C1100
2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 MCP (PCH PWR)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Haydn-S
Date: Wednesday, July 22, 2015 Sheet 13 of 46
5 4 3 2 1
 5 4 3 2 1

SKL_ULT
UC1Q ?
SKL_ULT
UC1P ?
SKL_ULT ?
GND 2 OF 3 UC1R
GND 1 OF 3
AT63 BA49 GND 3 OF 3
A5 AL65 AT68 VSS_AT63 VSS_BA49 BA53 F8 L18
A67 VSS_A5 VSS_AL65 AL66 AT71 VSS_AT68 VSS_BA53 BA57 G10 VSS_F8 VSS_L18 L2
A70 VSS_A67 VSS_AL66 AM13 AU10 VSS_AT71 VSS_BA57 BA6 G22 VSS_G10 VSS_L2 L20
D AA2 VSS_A70 VSS_AM13 AM21 AU15 VSS_AU10 VSS_BA6 BA62 G43 VSS_G22 VSS_L20 L4 D
AA4 VSS_AA2 VSS_AM21 AM25 AU20 VSS_AU15 VSS_BA62 BA66 G45 VSS_G43 VSS_L4 L8
AA65 VSS_AA4 VSS_AM25 AM27 AU32 VSS_AU20 VSS_BA66 BA71 G48 VSS_G45 VSS_L8 N10
AA68 VSS_AA65 VSS_AM27 AM43 AU38 VSS_AU32 VSS_BA71 BB18 G5 VSS_G48 VSS_N10 N13
AB15 VSS_AA68 VSS_AM43 AM45 AV1 VSS_AU38 VSS_BB18 BB26 G52 VSS_G5 VSS_N13 N19
AB16 VSS_AB15 VSS_AM45 AM46 AV68 VSS_AV1 VSS_BB26 BB30 G55 VSS_G52 VSS_N19 N21
AB18 VSS_AB16 VSS_AM46 AM55 AV69 VSS_AV68 VSS_BB30 BB34 G58 VSS_G55 VSS_N21 N6
AB21 VSS_AB18 VSS_AM55 AM60 AV70 VSS_AV69 VSS_BB34 BB38 G6 VSS_G58 VSS_N6 N65
AB8 VSS_AB21 VSS_AM60 AM61 AV71 VSS_AV70 VSS_BB38 BB43 G60 VSS_G6 VSS_N65 N68
AD13 VSS_AB8 VSS_AM61 AM68 AW10 VSS_AV71 VSS_BB43 BB55 G63 VSS_G60 VSS_N68 P17
AD16 VSS_AD13 VSS_AM68 AM71 AW12 VSS_AW10 VSS_BB55 BB6 G66 VSS_G63 VSS_P17 P19
AD19 VSS_AD16 VSS_AM71 AM8 AW14 VSS_AW12 VSS_BB6 BB60 H15 VSS_G66 VSS_P19 P20
AD20 VSS_AD19 VSS_AM8 AN20 AW16 VSS_AW14 VSS_BB60 BB64 H18 VSS_H15 VSS_P20 P21
AD21 VSS_AD20 VSS_AN20 AN23 AW18 VSS_AW16 VSS_BB64 BB67 H71 VSS_H18 VSS_P21 R13
AD62 VSS_AD21 VSS_AN23 AN28 AW21 VSS_AW18 VSS_BB67 BB70 J11 VSS_H71 VSS_R13 R6
AD8 VSS_AD62 VSS_AN28 AN30 AW23 VSS_AW21 VSS_BB70 C1 J13 VSS_J11 VSS_R6 T15
AE64 VSS_AD8 VSS_AN30 AN32 AW26 VSS_AW23 VSS_C1 C25 J25 VSS_J13 VSS_T15 T17
AE65 VSS_AE64 VSS_AN32 AN33 AW28 VSS_AW26 VSS_C25 C5 J28 VSS_J25 VSS_T17 T18
AE66 VSS_AE65 VSS_AN33 AN35 AW30 VSS_AW28 VSS_C5 D10 J32 VSS_J28 VSS_T18 T2
AE67 VSS_AE66 VSS_AN35 AN37 AW32 VSS_AW30 VSS_D10 D11 J35 VSS_J32 VSS_T2 T21
AE68 VSS_AE67 VSS_AN37 AN38 AW34 VSS_AW32 VSS_D11 D14 J38 VSS_J35 VSS_T21 T4
AE69 VSS_AE68 VSS_AN38 AN40 AW36 VSS_AW34 VSS_D14 D18 J42 VSS_J38 VSS_T4 U10
AF1 VSS_AE69 VSS_AN40 AN42 AW38 VSS_AW36 VSS_D18 D22 J8 VSS_J42 VSS_U10 U63
AF10 VSS_AF1 VSS_AN42 AN58 AW41 VSS_AW38 VSS_D22 D25 K16 VSS_J8 VSS_U63 U64
AF15 VSS_AF10 VSS_AN58 AN63 AW43 VSS_AW41 VSS_D25 D26 K18 VSS_K16 VSS_U64 U66
AF17 VSS_AF15 VSS_AN63 AP10 AW45 VSS_AW43 VSS_D26 D30 K22 VSS_K18 VSS_U66 U67
AF2 VSS_AF17 VSS_AP10 AP18 AW47 VSS_AW45 VSS_D30 D34 K61 VSS_K22 VSS_U67 U69
AF4 VSS_AF2 VSS_AP18 AP20 AW49 VSS_AW47 VSS_D34 D39 K63 VSS_K61 VSS_U69 U70
AF63 VSS_AF4 VSS_AP20 AP23 AW51 VSS_AW49 VSS_D39 D44 K64 VSS_K63 VSS_U70 V16
AG16 VSS_AF63 VSS_AP23 AP28 AW53 VSS_AW51 VSS_D44 D45 K65 VSS_K64 VSS_V16 V17
AG17 VSS_AG16 VSS_AP28 AP32 AW55 VSS_AW53 VSS_D45 D47 K66 VSS_K65 VSS_V17 V18
AG18 VSS_AG17 VSS_AP32 AP35 AW57 VSS_AW55 VSS_D47 D48 K67 VSS_K66 VSS_V18 W13
C AG19 VSS_AG18 VSS_AP35 AP38 AW6 VSS_AW57 VSS_D48 D53 K68 VSS_K67 VSS_W13 W6 C
AG20 VSS_AG19 VSS_AP38 AP42 AW60 VSS_AW6 VSS_D53 D58 K70 VSS_K68 VSS_W6 W9
AG21 VSS_AG20 VSS_AP42 AP58 AW62 VSS_AW60 VSS_D58 D6 K71 VSS_K70 VSS_W9 Y17
AG71 VSS_AG21 VSS_AP58 AP63 AW64 VSS_AW62 VSS_D6 D62 L11 VSS_K71 VSS_Y17 Y19
AH13 VSS_AG71 VSS_AP63 AP68 AW66 VSS_AW64 VSS_D62 D66 L16 VSS_L11 VSS_Y19 Y20
AH6 VSS_AH13 VSS_AP68 AP70 AW8 VSS_AW66 VSS_D66 D69 L17 VSS_L16 VSS_Y20 Y21
AH63 VSS_AH6 VSS_AP70 AR11 AY66 VSS_AW8 VSS_D69 E11 VSS_L17 VSS_Y21
AH64 VSS_AH63 VSS_AR11 AR15 B10 VSS_AY66 VSS_E11 E15
AH67 VSS_AH64 VSS_AR15 AR16 B14 VSS_B10 VSS_E15 E18
AJ15 VSS_AH67 VSS_AR16 AR20 B18 VSS_B14 VSS_E18 E21
AJ18 VSS_AJ15 VSS_AR20 AR23 B22 VSS_B18 VSS_E21 E46 18 OF 20
VSS_AJ18 VSS_AR23 VSS_B22 VSS_E46 SKYLAKE-U_BGA1356
AJ20 AR28 B30 E50 REV = 1 ?
AJ4 VSS_AJ20 VSS_AR28 AR35 B34 VSS_B30 VSS_E50 E53
AK11 VSS_AJ4 VSS_AR35 AR42 B39 VSS_B34 VSS_E53 E56 @
AK16 VSS_AK11 VSS_AR42 AR43 B44 VSS_B39 VSS_E56 E6
AK18 VSS_AK16 VSS_AR43 AR45 B48 VSS_B44 VSS_E6 E65
AK21 VSS_AK18 VSS_AR45 AR46 B53 VSS_B48 VSS_E65 E71
AK22 VSS_AK21 VSS_AR46 AR48 B58 VSS_B53 VSS_E71 F1
AK27 VSS_AK22 VSS_AR48 AR5 B62 VSS_B58 VSS_F1 F13
AK63 VSS_AK27 VSS_AR5 AR50 B66 VSS_B62 VSS_F13 F2
AK68 VSS_AK63 VSS_AR50 AR52 B71 VSS_B66 VSS_F2 F22
AK69 VSS_AK68 VSS_AR52 AR53 BA1 VSS_B71 VSS_F22 F23
AK8 VSS_AK69 VSS_AR53 AR55 BA10 VSS_BA1 VSS_F23 F27
AL2 VSS_AK8 VSS_AR55 AR58 BA14 VSS_BA10 VSS_F27 F28
AL28 VSS_AL2 VSS_AR58 AR63 BA18 VSS_BA14 VSS_F28 F32
AL32 VSS_AL28 VSS_AR63 AR8 BA2 VSS_BA18 VSS_F32 F33
AL35 VSS_AL32 VSS_AR8 AT2 BA23 VSS_BA2 VSS_F33 F35
AL38 VSS_AL35 VSS_AT2 AT20 BA28 VSS_BA23 VSS_F35 F37
AL4 VSS_AL38 VSS_AT20 AT23 BA32 VSS_BA28 VSS_F37 F38
AL45 VSS_AL4 VSS_AT23 AT28 BA36 VSS_BA32 VSS_F38 F4
AL48 VSS_AL45 VSS_AT28 AT35 F68 VSS_BA36 VSS_F4 F40
AL52 VSS_AL48 VSS_AT35 AT4 BA45 VSS_F68 VSS_F40 F42
B AL55 VSS_AL52 VSS_AT4 AT42 VSS_BA45 VSS_F42 BA41 B
AL58 VSS_AL55 VSS_AT42 AT56 VSS_BA41
AL64 VSS_AL58 VSS_AT56 AT58
VSS_AL64 VSS_AT58
17 OF 20

16 OF 20 SKYLAKE-U_BGA1356
SKYLAKE-U_BGA1356 REV = 1 ?
REV = 1 ?
@
@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 MCP (VSS)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Haydn-S
Date: Wednesday, July 22, 2015 Sheet 14 of 46
5 4 3 2 1
 5 4 3 2 1

?
SKL_ULT
UC1S

RESERVED SIGNALS-1

D CPU_CFG0 E68 BB68 删除测点 D

PAD @ TP142 1 CPU_CFG1 B67 CFG[0] RSVD_TP_BB68 BB69 1 TP174 @ PAD
PAD @ TP143 1 CPU_CFG2 D65 CFG[1] RSVD_TP_BB69
PAD @ TP144 1 XDP_CPU_CFG3 D67 CFG[2] AK13 1 TP175 @ PAD
CFG[3] RSVD_TP_AK13

2
CPU_CFG4 E70 AK12 1 TP176 @ PAD +VCCST_CPU
RC1618 PAD @ TP146 1 CPU_CFG5 C68 CFG[4] RSVD_TP_AK12 UC1T SKL_ULT ?
1K_0402_5% PAD @ TP147 1 CPU_CFG6 D68 CFG[5] BB2 删除测点
PAD @ TP148 1 CPU_CFG7 C67 CFG[6] RSVD_BB2 BA3 删除测点 SPARE
CFG[7] RSVD_BA3

2
1 PAD @ TP153 1 CPU_CFG8 F71
CFG[8]

1
RC106 PAD @ TP150 1 CPU_CFG9 G69 +1.8VALW AW69 F6
@ CFG[9] RSVD_AW69 RSVD_F6
1K_0402_5% PAD @ TP151 1 CPU_CFG10 F70 AU5 AW68 E3 RC1619
PAD @ TP152 1 CPU_CFG11 G68 CFG[10] TP5 AT5 AU56 RSVD_AW68 RSVD_E3 C11 150_0402_5%
PAD @ TP168 1 CPU_CFG12 H70 CFG[11] TP6 AW48 RSVD_AU56 RSVD_C11 B11 @

1
PAD @ TP154 1 CPU_CFG13 G71 CFG[12] Cannonlake@ C7 RSVD_AW48 RSVD_B11 A11

2
PAD @ TP155 1 CPU_CFG14 H69 CFG[13] D5 RC1582 2 1 0_0402_5% U12 RSVD_C7 RSVD_A11 D12
PAD @ TP156 1 CPU_CFG15 G70 CFG[14] RSVD_D5 D4 RC1583 2 1 0_0402_5% U11 RSVD_U12 RSVD_D12 C12
CFG[15] RSVD_D4 B2 Cannonlake@ H11 RSVD_U11 RSVD_C12 F52 RSVD_F52
PAD @ TP159 1 CPU_CFG16 E63 RSVD_B2 C2 RSVD_H11 RSVD_F52
PAD @ TP158 1 CPU_CFG17 F63 CFG[16] RSVD_C2
CFG[17] B3
RSVD_B3 20 OF 20
PAD @ TP161 1 CPU_CFG18 E66 A3
CFG[18] RSVD_A3 SKYLAKE-U_BGA1356
PAD @ TP160 1 CPU_CFG19 F66 REV = 1 ?
C CFG[19] AW1 C
RSVD_AW1 @
CFG_RCOMP E60
CFG_RCOMP E1
PAD @ TP166 1 XDP_ITP_PMODE E8 RSVD_E1 E2
ITP_PMODE RSVD_E2
2

RC162 AY2 BA4

AY1 RSVD_AY2 RSVD_BA4 BB4 删除测点
49.9_0402_1% RSVD_AY1 RSVD_BB4
D1 A4
1

D3 RSVD_D1 RSVD_A4 C4
RSVD_D3 RSVD_C4
K46 BB5 1 TP199 @ PAD
K45 RSVD_K46 TP4
RSVD_K45 A69
AL25 RSVD_A69 B69
AL27 RSVD_AL25 RSVD_B69 need to check with Intel
RSVD_AL27 AY3 RSVD_AY3
C71 RSVD_AY3
RSVD_C71

2
删除测点B70 D71
删除测点 RSVD_B70 RSVD_D71 C70 RC107
F60 RSVD_C70
RSVD_F60 0_0402_5%
C54
B A52 RSVD_C54 D54 B

1
RSVD_A52 RSVD_D54
PAD @ TP171 1 BA70 AY4
BA68 RSVD_TP_BA70 TP1 BB3 删除测点
删除测点 RSVD_TP_BA68 TP2 need to check with Intel
J71 AY71 VSS_AY71
J68 RSVD_J71 VSS_AY71 AR56 1 TP167 @ PAD
RSVD_J68 ZVM#

2
PAD @ TP169 1 F65 AW71 删除测点
PAD @ TP170 1 G65 VSS_F65 RSVD_TP_AW71 AW70 删除测点 RC108
VSS_G65 RSVD_TP_AW70
0_0402_5%
F61 AP56 1 TP206 @ PAD
E61 RSVD_F61 MSM# C64 PROC_SELECT# 1 2 +VCCST_CPU

1
RSVD_E61 PROC_SELECT# R228 100K_0402_5%
Cannonlake@
19 OF 20
SKYLAKE-U_BGA1356
Default REV = 1 ?
Pin Name Strap Description Configuration Value @

A CFG[4] Display Port —1 = eDP Disabled 1 A

Presence strap —0 = eDP Enabled * Security Classification LC Future Center Secret Data Title
Issued Date 2014/12/11 Deciphered Date 2015/12/11 MCP (CFG,RESERVED)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Haydn-S
Date: Wednesday, July 22, 2015 Sheet 15 of 46
5 4 3 2 1
 A B C D E F G H

+1.35V

1
+1.35V +1.35V
DDR SO-DIMM RD11
1.82K_0402_1%

Trace width:20 mils RD12 For RF request

2
2_0402_5% JDDRL
Space:20mils  1 2 +VREF_DQ_DIMMA 1 2
5 DDR_SA_VREFDQ VREF_DQ VSS_2
3 4 DDRA_DQ0
VSS_1 DQ4

CD95
33P_0402_16V7K
RF_NS@

CD104
33P_0402_16V7K
RF_NS@
1 DDRA_DQ1 5 6 DDRA_DQ4
DQ0 DQ5 DDRA_DQ[63:0] 5

CD103
2.2U_0603_6.3V6K

CD108
.1U_0402_10V6-K
CD29 RD13 1 1 DDRA_DQ5 7 8 1 1
0.022U_0402_16V7-K 1.82K_0402_1% 9 DQ1 VSS_4 10 DDRA_DQS#0
VSS_3 DQS0# DDRA_MA[15:0] 5
11 12 DDRA_DQS0
2 CD@ 13 DM0 DQS0 14
DDRA_DQS[7:0] 5

2
VSS_5 VSS_6

1
2 2 DDRA_DQ6 15 16 DDRA_DQ2 2 2
RD14 DDRA_DQ7 17 DQ2 DQ6 18 DDRA_DQ3
1 DQ3 DQ7 DDRA_DQS#[7:0] 5 1
24.9_0402_1% 19 20
DDRA_DQ12 21 VSS_7 VSS_8 22 DDRA_DQ13
DDRA_DQ9 23 DQ8 DQ12 24 DDRA_DQ8

2
25 DQ9 DQ13 26
DDRA_DQS#1 27 VSS_9 VSS_10 28
DDRA_DQS1 29 DQS1# DM1 30
DQS1 RESET# DDRA_DRAMRST# 5
31 32
DDRA_DQ14 33 VSS_11 VSS_12 34 DDRA_DQ11
DDRA_DQ10 35 DQ10 DQ14 36 DDRA_DQ15
37 DQ11 DQ15 38
DDRA_DQ20 39 VSS_13 VSS_14 40 DDRA_DQ17
DDR Swap Table DQ16 DQ20
DDRA_DQ21 41 42 DDRA_DQ16
43 DQ17 DQ21 44
DDRA_DQS#2 45 VSS_15 VSS_16 46
New Net Name Pin Number Old Net Name DQS2# DM2
DDRA_DQS2 47 48
49 DQS2 VSS_18 50 DDRA_DQ22
DDRA_DQ18 51 VSS_17 DQ22 52 DDRA_DQ19
DDRA_DQ23 53 DQ18 DQ23 54
55 DQ19 VSS_20 56 DDRA_DQ24
DDRA_DQ29 57 VSS_19 DQ28 58 DDRA_DQ28
DDRA_DQ25 59 DQ24 DQ29 60
61 DQ25 VSS_22 62 DDRA_DQS#3
63 VSS_21 DQS3# 64 DDRA_DQS3
65 DM3 DQS3 66
DDRA_DQ26 67 VSS_23 VSS_24 68 DDRA_DQ31
DDRA_DQ30 69 DQ26 DQ30 70 DDRA_DQ27
71 DQ27 DQ31 72
VSS_25 VSS_26

5 DDRA_CKE0 DDRA_CKE0 73 74 DDRA_CKE1

CKE0 CKE1 DDRA_CKE1 5
75 76
77 VDD_1 VDD_2 78 DDRA_MA15
DDRA_BS2# 79 NC_1 A15 80 DDRA_MA14
5 DDRA_BS2# BA2 A14
81 82
DDRA_MA12 83 VDD_3 VDD_4 84 DDRA_MA11
DDRA_MA9 85 A12/BC# A11 86 DDRA_MA7
87 A9 A7 88
DDRA_MA8 89 VDD_5 VDD_6 90 DDRA_MA6
2 2
DDRA_MA5 91 A8 A6 92 DDRA_MA4
93 A5 A4 94
DDRA_MA3 95 VDD_7 VDD_8 96 DDRA_MA2
DDRA_MA1 97 A3 A2 98 DDRA_MA0
99 A1 A0 100
DDRA_CLK0 101 VDD_9 VDD_10 102 DDRA_CLK1
5 DDRA_CLK0 CK0 CK1 DDRA_CLK1 5
5 DDRA_CLK0# DDRA_CLK0# 103 104 DDRA_CLK1#
CK0# CK1# DDRA_CLK1# 5
105 106
DDRA_MA10 107 VDD_11 VDD_12 108 DDRA_BS1# +1.35V
A10/AP BA1 DDRA_BS1# 5
5 DDRA_BS0# DDRA_BS0# 109 110 DDRA_RAS#
BA0 RAS# DDRA_RAS# 5
111 112
VDD_13 VDD_14

1
5 DDRA_WE# DDRA_WE# 113 114 DDRA_CS0#
WE# S0# DDRA_CS0# 5
5 DDRA_CAS# DDRA_CAS# 115 116 DDRA_ODT0 RD6
CAS# ODT0 DDRA_ODT0 5
117 118 1.82K_0402_1%
DDRA_MA13 119 VDD_15 VDD_16 120 DDRA_ODT1
A13 ODT1 DDRA_ODT1 5
DDRA_CS1# 121 122 Trace width:20 mils RD9
5 DDRA_CS1#

2
123 S1# NC_2 124 2_0402_5%
125 VDD_17 VDD_18 126 +VREF_CA
Space:20mils  1 2
TEST VREF_CA DDR_SM_VREFCA 5
127 128 1
VSS_27 VSS_28

.1U_0402_10V6-K
DDRA_DQ33 129 130 DDRA_DQ37 CD20
DDRA_DQ36 131 DQ32 DQ36 132 DDRA_DQ32 0.022U_0402_16V7-K
DQ33 DQ37 1 1
133 134 CD94 CD98
DDRA_DQS#4 135 VSS_29 VSS_30 136 4.7U_0603_6.3V6K 2
DQS4# DM4

1
DDRA_DQS4 137 138
139 DQS4 VSS_32 140 DDRA_DQ34 2 2 RD7
DDRA_DQ39 141 VSS_31 DQ38 142 DDRA_DQ35 1.82K_0402_1% RD8
DDRA_DQ38 143 DQ34 DQ39 144 24.9_0402_1%
145 DQ35 VSS_34 146 DDRA_DQ45

2
DDRA_DQ44 147 VSS_33 DQ44 148 DDRA_DQ40
DDRA_DQ41 149 DQ40 DQ45 150
151 DQ41 VSS_35 152 DDRA_DQS#5 CD@
153 VSS_36 DQS5# 154 DDRA_DQS5
155 DM5 DQS5 156
DDRA_DQ46 157 VSS_37 VSS_38 158 DDRA_DQ43
DDRA_DQ47 159 DQ42 DQ46 160 DDRA_DQ42
161 DQ43 DQ47 162
DDRA_DQ48 163 VSS_39 VSS_40 164 DDRA_DQ52
3
VDDQ(2A) DQ48 DQ52 3
Decoupling CAP DDRA_DQ53 165 166 DDRA_DQ49
167 DQ49 DQ53 168
DDRA_DQS#6 169 VSS_41 VSS_42 170
4 PCS 1UF CAP Near Each Side Of DIMM VDD Pin DQS6# DM6
4PCS 10UF CAP Near Each Side Of DIMM VDD Pin DDRA_DQS6 171 172
173 DQS6 VSS_44 174 DDRA_DQ51
DDRA_DQ55 175 VSS_43 DQ54 176 DDRA_DQ50
VTT(700mA) DQ50 DQ55
Decoupling CAP DDRA_DQ54 177 178
179 DQ51 VSS_46 180 DDRA_DQ61
DDRA_DQ56 181 VSS_45 DQ60 182 DDRA_DQ57
4PCS 0.1UF CAP Near The DIMM DQ56 DQ61
2PCS 10UF CAP On the VTT Island DDRA_DQ60 183 184
185 DQ57 VSS_48 186 DDRA_DQS#7
187 VSS_47 DQS7# 188 DDRA_DQS7
189 DM7 DQS7 190
DDRA_DQ62 191 VSS_49 VSS_50 192 DDRA_DQ58
DDRA_DQ63 193 DQ58 DQ62 194 DDRA_DQ59
195 DQ59 DQ63 196
+0.68VS RD16 1 2 0_0402_5% 197 VSS_51 VSS_52 198
199 SA0 EVENT# 200
+3VS VDDSPD SDA PM_SMB_DAT 6,32
201 202
SA1 SCL PM_SMB_CLK 6,32
203 204 +0.68VS
VTT_1 VTT_2
2

1 1 1 1 1 1 1 1
.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

10U_0603_6.3V6M

10U_0603_6.3V6M

2.2U_0603_6.3V6K

.1U_0402_10V6-K

RD22 205 206

GND1 GND2
CD115

CD65

CD66

CD88

CC53

CC55

CD102

CD99

0_0402_5% 207 208

BOSS1 BOSS2
2 2 2 2 2 2 2 2
1

LCN_DAN06-K4406-0103

CD@ ME@ DIMM ADRESS:

SA1:SA0 00
CD@

+1.35V

4 4
10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1
10U_0603_6.3V6M

CD97

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CD100

CD106

CD96

CD101

CD105

CD93

CD91

CD90

CD107

CD109

CD110

CD111

CD112

CD113

CD114

2
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

Security Classification LC Future Center Secret Data Title

CD@ CD@ CD@ CD@
CD@ CD@ CD@ CD@
Issued Date 2013/03/26 Deciphered Date 2013/02/01 DDR3L
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Haydn-S
Date: Wednesday, July 22, 2015 Sheet 16 of 46
A B C D E F G H
 5 4 3 2 1

N15x GPIO
Performance Mode P0 TDP at Tj = 102 C* (DDR3)
GPIO I/O ACTIVE Function Description
FBVDDQ PCI Express I/O and Other
GPU Mem NVCLK FBVDD (GPU+Mem) (1.05V) PLLVDD
GPIO0 OUT - FB Enable for GC6 2.0 (4) (1,5) /MCLK NVVDD (1.35V) (1.35V) (6) (1.05V) (3.3V)
Products (W) (W) (MHz) (V) (A) (W) (A) (W) (A) (W) (mA) (W) (mA) (W) (mA) (W)
D GPIO1 OUT N/A D

N14X
GPIO2 OUT N/A 128bit TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
2GB
DDR3
GPIO3 OUT N/A

GPIO4 OUT N/A

GPIO5 OUT N/A GPU power sequencing---3V3_MAIN_EN

GPIO6 IN - GPU wake signal for GC6 2.0

GPIO7 OUT N/A

GPIO8 I/O - System side PCIe reset Monitor

GPIO9 I/O N/A 2.2K Pull-up

N15x Multi-level Straps
GPIO10 OUT N/A

GPIO11 OUT - GPU Core VDD PWM control signal

GPIO12 IN AC Power Detect Input (10K pull High)

Physical Logical Logical Logical Logical
GPIO13 OUT - Phase Shedding Strapping pin Power Rail Strapping Bit3 Strapping Bit2 Strapping Bit1 Strapping Bit0
C ROM_SCLK +3VGS SOR3_EXPOSED SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED C
GPIO14 IN N/A
ROM_SI +3VGS RAM_CFG[3] RAM_CFG[2] RAM_CFG[1] RAM_CFG[0]
GPIO15 IN N/A ROM_SO +3VGS DEVID_SEL PCIE_CFG SMB_ALT_ADDR VGA_DEVICE
STRAP0 +3VGS Reserved(keep pull-up and pull-down footprint and stuff 50Kohm pull-up)
GPIO16 N/A
STRAP1 +3VGS
GPIO17 IN N/A STRAP2 +3VGS
Reserved(keep pull-up and pull-down footprint and not stuff by default)
STRAP3 +3VGS
GPIO18 IN N/A
STRAP4 +3VGS
GPIO19 IN N/A

GPIO20 N/A SMBUS_ALT_ADDR

GPIO21 OUT GPU PCIe self-reset control 0 0x9E (Default)

OVERT OUT Active Low Thermal Catastrophic Over Temperature 1 0x9C (Multi-GPU usage)

N15V-GM Power Sequence

B
N15x Binary Straps B

+3VG_AON Other Power rail

+VGA_CORE
+3VG_AON
Physical
tNVVDD >0 Power Rail Strap Mapping
Strapping pin
+1.35VGS
Tpower-off <10ms ROM_SCLK +3VGS SMB_ALT_ADDR
tFBVDDQ >0
ROM_SI +3VGS SUB_VENDOR
+1.05VS_VGA
ROM_SO +3VGS VGA_DEVICE
tPEX_VDD >0
STRAP0 +3VGS RAM_CFG[0]
1.all GPU power rails should be turned off within 10ms STRAP1 +3VGS RAM_CFG[1]
1. all power rail ramp up time should be larger than 40us 2. Optimus system VDD33 avoids drop down earlier than NVDD and FBVDDQ
STRAP2 +3VGS RAM_CFG[2]
STRAP3 +3VGS RAM_CFG[3]
STRAP4 +3VGS PCIE_MAX_SPEED
N15S-GT Power Sequence

+3VG_AON

+VGA_CORE
A A

tNVVDD >0
+1.05VS_VGA

+1.35VGS
tPEX_VDD >0
Security Classification LC Future Center Secret Data Title

1. all power rail ramp up time should be larger than 40us and less than 2ms . Issued Date 2013/08/08 Deciphered Date 20140213 VGA Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Haydn-S
Date: Wednesday, July 22, 2015 Sheet 17 of 46
5 4 3 2 1
 5 4 3 2 1

7 GC6_FB_EN RV1 1 GC6@ 2 0_0402_5% FB_GC6_EN_R

RV2 1 GC6@ 2 0_0402_5% GPU_EVENT#

7 PCH_GPU_EVENT#

8 PCIE_CRX_GTX_N[0..3]

8 PCIE_CRX_GTX_P[0..3]

8 PCIE_CTX_C_GRX_N[0..3]
UV1A
8 PCIE_CTX_C_GRX_P[0..3]
+3VGS
Part 1 of 6 1 RV175 2 0_0402_5%
H_THRMTRIP# 4
PCIE_CTX_C_GRX_P0 AG6 C6 FB_GC6_EN @
D PEX_RX0 GPIO0 FB_GC6_EN 22 D

.1U_0402_10V6-K
+3VG_AON +3VG_AON PCIE_CTX_C_GRX_N0 AG7 B2
PEX_RX0_N GPIO1

1
PCIE_CTX_C_GRX_P1 AF7 D6 1
PCIE_CTX_C_GRX_N1 AE7 PEX_RX1 GPIO2 C7 RV4
PCIE_CTX_C_GRX_P2 AE9 PEX_RX1_N GPIO3 F9 10K_0402_5% CV1
PEX_RX2 GPIO4
2

PCIE_CTX_C_GRX_N2 AF9 A3 3VGS_PWR_EN @ @

PEX_RX2_N GPIO5 3VGS_PWR_EN 20,43

3
RV3 RV5 PCIE_CTX_C_GRX_P3 AG9 A4 GPU_EVENT#_R D 2

2
PEX_RX3 GPIO6

5
2.2K_0402_5% 2.2K_0402_5% PCIE_CTX_C_GRX_N3 AG10 B6 5

G
OPT@ OPT@ AF10 PEX_RX3_N GPIO7 E9 SYS_PEX_RST_MON# G
AE10 NC81 GPIO8 F8 VGA_ALERT#
A6 Symbol update to OVER QV2B
1

NC82 GPIO9

6
AE12 C5 D S 2N7002KDWH_SOT363-6

4
VGA_SMB_CK2 4
S
3 AF12 NC83 GPIO10 E7 NVVDD_PWM_VID DV1 OVERT# 2 @
EC_SMB_CLK0 6,30,32 NC84 GPIO11 NVVDD_PWM_VID 43

D
AG12 D7 VGA_AC_DET_R 2 1 @ 1 G
NC85 GPIO12 TV6
AG13 B4 PSI_VGA_R @ QV2A

GPIO
QV1B AF13 NC86 GPIO13 B3 RB751V-40_SOD323-2 S 2N7002KDWH_SOT363-6

1
2N7002KDWH_SOT363-6 AE13 NC87 GPIO14 C3 @
NC88 GPIO15 2 RV6
2

OPT@ AE15 D5 1 PSI_VGA

G

NC1 GPIO16 PSI_VGA 43

1
RV7 2 @ 1 0_0402_5% AF15 D4 N15SGT@ 0_0402_5% D
NC2 GPIO17

.1U_0402_10V6-K
AG15 C2 PLT_RST_VGA# 1 RV8 2 0_0402_5% 2 1
AG16 NC3 GPIO18 F7 @ G
NC4 GPIO19

.1U_0402_10V6-K
VGA_SMB_DA2 1 6 AF16 E6 QV3 CV2
S

EC_SMB_DAT0 6,30,32 NC5 GPIO20

D

AE16 C4 GPU_PEX_RST_HOLD# S 2N7002KW_SOT323-3 @

3
AE18 NC6 GPIO21 @ 2
NC7 1
QV1A AF18 A6 OVERT# CV3
2N7002KDWH_SOT363-6 AG18 NC8 OVERT AB6
AG19 NC9 NC33 @
OPT@
RV9 2 @ 1 0_0402_5% AF19 NC10 RV174 2
PU AT CPU SIDE, +3VS AND 2.2K NC11
AE19 PLT_RST_VGA# 1 2 1K_0402_5%
NC12

.1U_0402_10V6-K
AE21 AG3
AF21 NC13 NC97 AF4 @
NC14 NC98 1
AG21 AF3 CV218
NC15 NC99

2
AG22 @

G
NC16 +3VG_AON +3VG_AON
2
+3VS PCIE_CRX_GTX_P0 CV10 OPT@1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_P0 AC9 AE3
PEX_TX0

DACs
RV10 PCIE_CRX_GTX_N0 CV13 OPT@1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_N0 AB9 NC100 AE4 OVERT# 3 1
PEX_TX0_N NC101 WRST# 30

D
+3VGARST 2 @ 1 PCIE_CRX_GTX_P1 CV8 OPT@1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_P1 AB10
PCIE_CRX_GTX_N1 CV9 OPT@1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_N1 AC10 PEX_TX1
PEX_TX1_N 1 QV23

.1U_0402_10V6-K
PCI EXPRESS
C 0_0402_5% +3VG_AON PCIE_CRX_GTX_P2 CV6 OPT@1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_P2 AD11 1 C
PCIE_CRX_GTX_N2 CV7 OPT@1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_N2 AC11 PEX_TX2 W5 CV221 2N7002KW_SOT323-3 RV13
RV12 1 2 0_0402_5% PCIE_CRX_GTX_P3 CV4 OPT@1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_P3 AC12 PEX_TX2_N NC102 AE2 0.01U_0402_25V7K 10K_0402_5% CV12
@
PEX_TX3 NC103

2
change to @ PCIE_CRX_GTX_N3 CV5 OPT@1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_N3 AB12 AF2 @ 2 GC6@ GC6@

G
SA000812600 74LVC1G08SE-7 AB13 PEX_TX3_N NC104 2

1
AC13 NC89
1 NC90
AD14
UV2 CV11 AC14 NC91 GPU_EVENT#_R 3 1 GPU_EVENT#
NC92

D
.1U_0402_10V6-K AC15
PCH_PLT_RST# 1 5 2 OPT@ AB15 NC93 QV4
10,28,30,31 PCH_PLT_RST# A VCC NC94
AB16 B7 VGA_CRT_CLK 2N7002KW_SOT323-3
2 AC16 NC95 I2CA_SCL A7 VGA_CRT_DATA GC6@
7 PCH_GPU_RST# B AD17 NC96 I2CA_SDA
I2C,if not use, can be soft grounded
Connect to CPU GPIO
3 4 SYS_PEX_RST_MON# AC17 NC17 C9 I2CB_SCL 1 @ 2 RV15
GND Y AC18 NC18 I2CB_SCL C8 I2CB_SDA
and delete pull up resistor ---colin 0_0402_5%
NC19 I2CB_SDA

I2C
AB18
74LVC1G08SE-7_SOT353-5 AB19 NC20 A9 I2CC_SCL
AC19 NC21 I2CC_SCL B9 I2CC_SDA
OPT@ NC22 I2CC_SDA
2 1 AD20
RV14 10K_0402_5% AC20 NC23 D9 VGA_SMB_CK2 +3VG_AON +3VG_AON
OPT@ AC21 NC24 I2CS_SCL D8 VGA_SMB_DA2
NC25 I2CS_SDA Internal Thermal Sensor
AB21
1 2 RV16 AD23 NC26
@ 0_0402_5% AE23 NC27 VGA_CRT_DATA RV17 1 2 3VGS_PWR_EN RV18 2 1
AF24 NC28 60mA OPT@ 2.2K_0402_5% OPT@ 10K_0402_5%
AE24 NC29 L6 +PLLVDD VGA_CRT_CLK RV19 1 2 OVERT# RV20 1 2
AG24 NC30 CORE_PLLVDD M6 OPT@ 2.2K_0402_5% OPT@ 10K_0402_5%
AG25 NC31 SP_PLLVDD I2CB_SCL RV22 1 2 VGA_ALERT# RV23 1 2
NC32 N6
45mA 1 2 RV24 +SP_PLLVDD OPT@ 2.2K_0402_5% OPT@ 10K_0402_5%
VID_PLLVDD @ 0_0402_5% I2CB_SDA RV25 1 2 VGA_AC_DET_R RV26 1 2
45mA OPT@ 2.2K_0402_5% OPT@ 100K_0402_5%
+3VGS +3VG_AON 9 CLK_PCIE_GPU CLK_PCIE_GPU AE8 I2CC_SCL RV28 1 2 PSI_VGA RV29 1 2
CLK_PCIE_GPU# AD8 PEX_REFCLK OPT@ 2.2K_0402_5% OPT@ 10K_0402_5%
9 CLK_PCIE_GPU# PEX_REFCLK_N
CLK_REQ_GPU# AC6 I2CC_SDA RV30 1 2 GPU_PEX_RST_HOLD#RV31 1 2
PEX_CLKREQ_N OPT@ 2.2K_0402_5% OPT@ 10K_0402_5%
1 2 RV32 PEX_TSTCLK_OUT AF22 XTALOUT RV33 1 2

CLK
Differential signal @ 200_0402_1% PEX_TSTCLK_OUT# AE22 PEX_TSTCLK C11 XTAL_IN @ 10K_0402_5% OVERT# RV27 1 2
PEX_TSTCLK_N XTAL_IN
2

0526 new symbol for haydn . B10 XTAL_OUT @ 100K_0402_5%

B
RV180 RV37 XTAL_OUT B

2.2K_0402_5% 10K_0402_5% PLT_RST_VGA# AC7 A10 XTALSSIN 1 OPT@ 2 RV34 10K_0402_5%

GC6@ @ 1 2 RV35 PEX_TERMP AF25 PEX_RST_N XTAL_SSIN C10 XTALOUT 1 OPT@ 2 RV36 10K_0402_5%
PEX_TERMP XTAL_OUTBUFF Under GPU(below 150mils)
DV6 OPT@ 2.49K_0402_1% 180ohms (ESR=0.2) Bead
1

GPU_PEX_RST_HOLD# 3
1 PLT_RST_VGA# N15S-GT-S-A2_FCBGA595 +SP_PLLVDD 1 2 LV1 +1.05VGS
SYS_PEX_RST_MON# 2 N15SGT@

22U_0805_6.3V6M
4.7U_0402_6.3V6M
0.1U_0402_10V7K

0.1U_0402_10V7K
150mA 1
CV15
1
CV16
1
CV17
1
CV18 PBY100505T-181Y-N_2P
BAT54AW_SOT323-3 OPT@
GC6@ 4.7uFX1 ,0.1uFX2 , 22uFX1
2 2 2 2
1 2 RV39 OPT@ OPT@ OPT@ OPT@
@ 0_0402_5%

1 2 RV38
change to BAT54A for cost down OPT@ 10M_0402_5%
YV1
Under GPU Near GPU 30ohms (ESR=0.05) Bead
+3VG_AON +3VG_AON XTAL_IN 1 4
OSC1 GND2 +PLLVDD 1 2 LV2 +1.05VGS
2 3 XTAL_OUT
GND1 OSC2
1 1 PBY100505T-300Y-N_2P
2

1 1
RV40 RV41 CV21 CV22 OPT@
10K_0402_5% 10K_0402_5% CV19 27MHZ_10PF_7V27000050 CV20 0.1U_0402_10V7K 22U_0603_6.3V6-M
OPT@ @ 12P_0402_50V8-J 12P_0402_50V8-J OPT@ 2 2
2 OPT@ 2
0.1uFX1 , 22uFX1
OPT@ OPT@ OPT@
1

+3VG_AON +3VG_AON
.1U_0402_10V6-K

.1U_0402_10V6-K

1 1
CV23 CV24
OPT@ @
2

2
2

A 2 RV44 2 RV45 A
2
G

10K_0402_5% 10K_0402_5%
OPT@ @
1

9 GPU_PCIE_CLKREQ# 6 1 CLK_REQ_GPU# FB_GC6_EN_R 1 3 FB_GC6_EN

D

QV6
2

2N7002KW_SOT323-3
QV5A RV46 @ RV47
AO5804EL_SC89-6 10K_0402_5% 10K_0402_5%
OPT@ @ 3
Connect to CPU GPIO GC6@ Title
1 2 RV48 QV5B 1 2 RV49 Security Classification LC Future Center Secret Data
1

@ 0_0402_5% GC6@ 0_0402_5%

Issued Date 2013/08/08 Deciphered Date 20140213 N15X_PCIE/ DAC/ GPIO
OPT@ 5
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
4
AO5804EL_SC89-6
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Haydn-S
Date: Wednesday, July 22, 2015 Sheet 18 of 46
5 4 3 2 1
 5 4 3 2 1

D D
UV1C

Part 3 of 6 F11
AC3 NC50 AD10
AC4 NC105 NC51 AD7
Y4 NC106 NC52
Y3 NC107 V5
B19 Symbol update to FBA_CMD32
AA3 NC108 FERMI_RSVD1 V6
AA2 NC109 FERMI_RSVD2 G1
AB1 NC110 NC56 G2
NC111 NC57

NC
AA1 G3
AA4 NC112 NC58 G4
AA5 NC113 NC59 G5
NC114 NC60 G6
NC61 G7
AB5 NC62 V1
AB4 NC115 NC63 V2
AB3 NC116 NC64 W1
AB2 NC117 NC65 W2
AD3 NC118 NC66 W3
AD2 NC119 NC67 W4
AE1 NC120 NC68
AD1 NC121
AD4 NC122
AD5 NC123
NC124 D11 2 1 RV50
BUFRST_N @ 10K_0402_5%
Symbol update to GPIO8

LVDS/TMDS
T2
T3 NC125 D10
T1 NC126 PGOOD
R1 NC127 E10
R2 NC128 NC71

GENERAL
R3 NC129 F10
N2 NC130 NC72
N3 NC131 +3VG_AON
NC132 D1 STRAP0
STRAP0 STRAP0 25
C D2 STRAP1 C
STRAP1 STRAP1 25
V3 E4 STRAP2
NC133 STRAP2 STRAP2 25

1
V4 E3 STRAP3
NC134 STRAP3 STRAP3 25
U3 D3 STRAP4 RV21
NC135 STRAP4 STRAP4 25
U4 C1 10K_0402_5%
T4 NC136 NC73
NC137 @
T5

2
R4 NC138 F6 MULTI_STRAP_REF0_GND
R5 NC139 MULTI_STRAP_REF0_GND F4
NC140 MULTI_STRAP_REF1_GNDMLS_REF1 F5
MULTI_STRAP_REF2_GND

2
N1 RV51
M1 NC34
NC35 40.2K_0402_1%
M2 F12 N15SGT@
M3 NC36 THERMDP

1
K2 NC37 E12
K3 NC38 THERMDN
K1 NC39
J1 NC40
NC41

M4 F2 VCCSENSE_VGA
NC42 VDD_SENSE VCCSENSE_VGA 43
M5
L3 NC43
NC44 trace width: 16mils
L4
K4 NC45 differential voltage sensing.
NC46 differential signal routing.
K5
J4 NC47 F1 VSSSENSE_VGA
NC48 GND_SENSE VSSSENSE_VGA 43

J5
N4 NC49
N5 NC141 TEST
NC142
P3 AD9 TESTMODE 1 OPT@ 2 RV52
P4 NC143 TESTMODE AE5 @ 1 10K_0402_5%
B NC144 JTAG_TCK TV1 B
AE6 @ 1
JTAG_TDI TV2
AF6 @ 1
JTAG_TDO TV3
J2 AD6 @ 1
NC145 JTAG_TMS TV4
J3 AG4 1 2 RV53
NC146 JTAG_TRST_N OPT@ 10K_0402_5%

H3
H4 NC147
NC148 SERIAL
D12 @ 1
ROM_CS_N TV5
B12 ROM_SI
ROM_SI ROM_SI 25
A12 ROM_SO
ROM_SO ROM_SO 25
C12 ROM_SCLK
ROM_SCLK ROM_SCLK 25

N15S-GT-S-A2_FCBGA595
N15SGT@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 20140213 N15X_LVDS/ HDMI/ THERM
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Haydn-S
Date: Wednesday, July 22, 2015 Sheet 19 of 46
5 4 3 2 1
 5 4 3 2 1

4.7uFX2 ,1uFX2 ,0.1uFX2 ,22uFX1 ,10uFX1 Near GPU 4.7uFX1 ,1uFX1 , 22uFX1 ,10uFX1
UV1D
+1.35VGS Near GPU Under GPU(below 150mils) 2000mA +1.05VGS
3.5A Part 4 of 6
B26 AA10 For RF
C25 FBVDDQ_01 PEX_IOVDDQ_1 AA12

22U_0805_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

33P_0402_50V8J
0.1U_0402_10V7K

0.1U_0402_10V7K

1U_0402_6.3V6K
4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
FBVDDQ_02 PEX_IOVDDQ_2

CV33

CV37

CV39

CV215
1U_0603_25V6M

1U_0603_25V6M
E23 AA13 1 1 2 1
FBVDDQ_03 PEX_IOVDDQ_3

CV25

CV26

CV27

CV28

CV29

CV30

CV31

CV32
1 2 1 1 1 1 1 1 E26 AA16
F14 FBVDDQ_04 PEX_IOVDDQ_4 AA18
F21 FBVDDQ_05 PEX_IOVDDQ_5 AA19 RF_OPTNS@
G13 FBVDDQ_06 PEX_IOVDDQ_6 AA20 2 2 1 2
2 1 2 2 2 2 2 2 G14 FBVDDQ_07 PEX_IOVDDQ_7 AA21 OPT@ OPT@
FBVDDQ_08 PEX_IOVDDQ_8 OPT@
CD@ OPT@ OPT@ OPT@ OPT@ CD@ OPT@ OPT@ G15 AB22
G16 FBVDDQ_09 PEX_IOVDDQ_9 AC23
D FBVDDQ_10 PEX_IOVDDQ_10 Under GPU(below 150mils) +1.05VGS PEX_IOVVDD/Q Decouling D
G18 AD24
G19 FBVDDQ_11 PEX_IOVDDQ_11 AE25
G20 FBVDDQ_12 PEX_IOVDDQ_12 AF26

22U_0805_6.3V6M
FBVDDQ_13 PEX_IOVDDQ_13 1 MLCC N15S-GT

CV43
G21 AF27
L22 FBVDDQ_14 PEX_IOVDDQ_14
Symbol update to FBVDDQ_AON L24 FBVDDQ_19
H24/H26/J21/K21 L26 FBVDDQ_20 AA22 2
Under Near +3VG_AON
1.0uF 1
M21 FBVDDQ_21 PEX_IOVDD_1 AB23
N21 FBVDDQ_22 PEX_IOVDD_2 AC24 OPT@

1U_0402_6.3V6K
.1U_0402_10V6-K

4.7U_0603_6.3V6K
FBVDDQ_23 PEX_IOVDD_3 4.7uF 1

CV47

CV48

CV49
R21 AD25 1 1 1

POWER
T21 FBVDDQ_24 PEX_IOVDD_4 AE26
V21 FBVDDQ_25 PEX_IOVDD_5 AE27
W21 FBVDDQ_26 PEX_IOVDD_6 10uF 1
FBVDDQ_27 2 2 2
Symbol update to 3V3_AON
4.7uFX1 ,1uFX1 , 0.1uFX1 OPT@ OPT@ OPT@
H24 22uF 1
H26 FBVDDQ_AON_1 +3VG_AON
J21 FBVDDQ_AON_2 G10
FBVDDQ_AON_3 3V3_AON_1 Place near balls(Under GPU) Place near GPU
K21 G12
FBVDDQ_AON_4 3V3_AON_2 +3VGS

V7 G8 +VDD33 RV54 1 2 0_0402_5%

NC149 3V3_MAIN_1 G9 @

1U_0402_6.3V6K
.1U_0402_10V6-K

.1U_0402_10V6-K

4.7U_0603_6.3V6K
3V3_MAIN_2

CV50

CV51

CV52

CV53
+1.35VGS 1 1 1 1 4.7uFX1 ,1uFX1 , 0.1uFX2
W7
AA6 NC150
W6 NC151 D22 FB_CAL_VDDQ 1 2 RV55
Y6 NC152 FB_CAL_VDDQ OPT@ 40.2_0402_1% 2 2 2 2
NC153 OPT@ OPT@ OPT@ OPT@
C24 FB_CAL_GND 1 2 RV56
FB_CAL_GND OPT@ 42.2_0402_1%

M7 B25 FB_CAL_TERM 1 2 RV57

CALIBRATION PIN DDR3
N7 NC154 FB_CAL_TERM OPT@ 51.1_0402_1%
T6 NC155
P6 NC156 FB_CAL_x_PD_VDDQ 40.2Ohm
NC157
Place near balls
C
FB_CAL_x_PU_GND 42.2Ohm C

T7 +3VG_AON
R7 NC158
NC159 Under GPU(below 150mils) FB_CAL_xTERM_GND 51.1Ohm
U6
R6 NC160 AA8

.1U_0402_10V6-K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
NC161 PEX_PLL_HVDD_1

CV55

CV56

CV57
AA9 1 1 1
PEX_PLL_HVDD_2
4.7uFX2 ,0.1uFX1
AB8
PEX_SVDD_3V3
2 2 2
J7 OPT@ OPT@ OPT@ 120ohm (ESR=0.18) Bead +1.05VGS
K7 NC76 120mA
K6 NC77 AA14 +PEX_PLLVDD 2 @ 1 LV3
NC78 PEX_PLLVDD_1

1U_0603_25V6M
H6 AA15 HCB1608KF-121T30_0603

.1U_0402_10V6-K

4.7U_0603_6.3V6K
NC79 PEX_PLLVDD_2

CV58

CV59

CV60
J6 1 1 1
NC80 @
1 2 RV62
0_0603_5%
2 2 2
OPT@ OPT@ OPT@
N15S-GT-S-A2_FCBGA595
N15SGT@
Place near balls 4.7uFX1 ,1uFX1 , 0.1uFX1
+3.3VS TO +3VG_AON

+3VS +3VG_AON

+5VALW
S

3 1
1

QV11 OPT@
1

B B
RV63 OPT@
G

1 1 1
2

47K_0402_5% @ LP2301ALT1G_SOT23-3 CV62 RV64 CV63

CV61 0.01U_0402_25V7K 470_0603_5% 10U_0603_6.3V6M +1.35V +1.35VGS
.1U_0402_10V6-K @ @ OPT@ +1.35V TO +1.35VGS AON6414AL_DFN8-5
2

2 2 2
2

PXS_PWREN# 1 2 RV65 1
10K_0402_5% 2
OPT@ 1 5 3
6

QV12A OPT@ CV67 CV68 CV69 CV70

220U_B2_2.5VM_R15M
D
3

2 CV64 QV12B CV65 CV66

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

.1U_0402_16V7K
D 1
7 PXS_PWREN

1
G .1U_0402_10V6-K PXS_PWREN# 5 1 1 QV14 OPT@ 1 1 1

4
2N7002KDWH_SOT363-6 2 G + RV67
1

OPT@ S 2N7002KDWH_SOT363-6 470_0603_5%

1

OPT@ S @
4

2 2 2 2 2 2

OPT@

OPT@

OPT@

OPT@
@

@
RV66 OPT@

2
100K_0402_5%
3
2

B+ QV10B
+5VALW
1 OPT@2 RV68 FBVDDQ_PWR_EN# 5 @
100K_0402_5%

+3VG_AON +3VGS AO5804EL_SC89-6

RV69 1

6
QV17A D 4
+3.3VS TO +3VGS 1 2 FBVDDQ_PWR_EN# 2 CV71
G 0.01U_0402_25V7K
2N7002KDWH_SOT363-6 2 OPT@
47K_0402_5% OPT@ S

1
RV171 1 2 OPT@
0_0603_5% @

3
0_0402_5% QV17B D
+5VALW RV228 1 2 5
22 FBVDDQ_PWR_EN
S

3 1 G
QV16 GC6@ 2N7002KDWH_SOT363-6
1

OPT@ OPT@ S

4
1

RV71 GC6@
G

1 1 1 1
2

A 47K_0402_5% @ CV73 RV72 CV74 CV506 A

CV72 LP2301ALT1G_SOT23-3 0.01U_0402_25V7K 470_0603_5% 10U_0603_6.3V6M .1U_0402_10V6-K
.1U_0402_10V6-K GC6@ @ GC6@ OPT@
2

2 2 2 2
2

DGPU_PWR_EN# 1 2
RV73 4.7K_0402_5%
GC6@ 1
6

QV19A D
3

2 CV75 QV19B D
18,43 3VGS_PWR_EN G .1U_0402_10V6-K DGPU_PWR_EN# 5
2N7002KDWH_SOT363-6 2 GC6@ G
Security Classification LC Future Center Secret Data Title
1

GC6@ S 2N7002KDWH_SOT363-6
1

GC6@ S
Issued Date 2013/08/08 Deciphered Date 20140213 N15X_Power
4

RV74 N15SGT@
100K_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
2

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Haydn-S
Date: Wednesday, July 22, 2015 Sheet 20 of 46
5 4 3 2 1
 5 4 3 2 1

D D

UV1E
UV1F
A2 Part 5 of 6 K11 +VGA_CORE +VGA_CORE
A26 GND_001 GND_057 K13 Part 6 of 6
AB11 GND_002 GND_058 K15
GND_003 GND_059 4.7uFX15 ,1uFX4 ,47uFX1 ,22uFX1 ,330uFX1
AB14 K17 K10 V18
AB17 GND_004 GND_060 L10 K12 VDD_001 VDD_041 V16
AB20 GND_005 GND_061 L12 +VGA_CORE K14 VDD_002 VDD_040 V14
AB24 GND_006 GND_062 L14 K16 VDD_003 VDD_039 V12
GND_007 GND_063 Under GPU VDD_004 VDD_038
AC2 L16 K18 V10
AC22 GND_008 GND_064 L18 L11 VDD_005 VDD_037 U17
GND_009 GND_065 VDD_006 VDD_036

POWER
AC26 L2 L13 U15
AC5 GND_010 GND_066 L23 L15 VDD_007 VDD_035 U13

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
AC8 GND_011 GND_067 L25 L17 VDD_008 VDD_034 U11
AD12 GND_012 GND_068 L5 M10 VDD_009 VDD_033 T18
GND_013 GND_069 1 1 1 1 1 1 1 1 1 1 1 1 1 VDD_010 VDD_032

CV76

CV77

CV78

CV79

CV80

CV81

CV82

CV83

CV84

CV85

CV86

CV87

CV88
AD13 M11 M12 T16
AD15 GND_014 GND_070 M13 M14 VDD_011 VDD_031 T14
AD16 GND_015 GND_071 M15 M16 VDD_012 VDD_030 T12
AD18 GND_016 GND_072 M17 2 2 2 2 2 2 2 2 2 2 2 2 2 M18 VDD_013 VDD_029 T10
AD19 GND_017 GND_073 N10 N11 VDD_014 VDD_028 R17
AD21 GND_018 GND_074 N12 OPT@ CD@ OPT@ OPT@ OPT@ OPT@ OPT@ OPT@ OPT@ OPT@ @ @ @ N13 VDD_015 VDD_027 R15
AD22 GND_019 GND_075 N14 N15 VDD_016 VDD_026 R13
AE11 GND_020 GND_076 N16 N17 VDD_017 VDD_025 R11
AE14 GND_021 GND_077 N18 P10 VDD_018 VDD_024 P18
AE17 GND_022 GND_078 P11 P12 VDD_019 VDD_023 P16
GND_023 GND_079 For RF VDD_020 VDD_022
AE20 P13 P14

33P_0402_50V8J
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
GND_024 GND_080 VDD_021

CV89

CV90

CV91

CV92

CV213
AF1 P15 1 1 1 1 1
GND_025 GND_081
GND

AF11 P17
AF14 GND_026 GND_082 P2
AF17 GND_027 GND_083 P23
AF20 GND_028 GND_084 P26 2 2 2 2 2
C C
AF23 GND_029 GND_085 P5 OPT@ OPT@ OPT@ OPT@ RF_OPTNS@
AF5 GND_030 GND_086 R10
AF8 GND_031 GND_087 R12
AG2 GND_032 GND_088 R14
AG26 GND_033 GND_089 R16 N15S-GT-S-A2_FCBGA595
B1 GND_034 GND_090 R18

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
GND_035 GND_091 N15SGT@
B11 T11
B14 GND_036 GND_092 T13
GND_037 GND_093 1 1 1 1 1 1 1 1 1 1

CV93

CV94

CV95

CV96

CV97

CV98

CV99

CV100

CV101

CV102
B17 T15
B20 GND_038 GND_094 T17
B23 GND_039 GND_095 U10
B27 GND_040 GND_096 U12 2 2 2 2 2 2 2 2 2 2
B5 GND_041 GND_097 U14
B8 GND_042 GND_098 U16 OPT@ OPT@ OPT@ CD@ CD@ @ @ @ @ @
E11 GND_043 GND_099 U18
E14 GND_044 GND_100 U2
E17 GND_045 GND_101 U23
E2 GND_046 GND_102 U26
E20 GND_047 GND_103 U5

33P_0402_50V8J
GND_048 GND_104

CV214
E22 V11 1 1 1 1
E25 GND_049 GND_105 V13
E5 GND_050 GND_106 V15 CV103 CV104 CV105
E8 GND_051 GND_107 V17 RF_OPTNS@
GND_052 GND_108 22U_0603_6.3V6-M 22U_0603_6.3V6-M 22U_0603_6.3V6-M
H2 Y2 2 2 2 2
H23 GND_053 GND_109 Y23 OPT@ OPT@ CD@
GND_054 GND_110 For RF
H25 Y26
H5 GND_055 GND_111 Y5
GND_056 GND_112

Near GPU
AA7
GND_113 AB7
GND_114

N15S-GT-S-A2_FCBGA595
B B
N15SGT@

+VGA_CORE
+5VALW
1

RV173
2

470_0603_5%
RV172 @
47K_0402_5%
6 2

@
QV21A D
1

2
G
3

QV21B D 2N7002KDWH_SOT363-6
5 @ S
41,43 EN_VGA
1

G
2N7002KDWH_SOT363-6
@ S
4

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 20140213 N15X_+VGA CORE, GND
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Haydn-S
Date: Wednesday, July 22, 2015 Sheet 21 of 46
5 4 3 2 1
 5 4 3 2 1

FBA_D[0..63]
23,24 FBA_D[0..63]

23,24 FBA_DQM[7..0]
23,24 FBA_DQS[7..0]
23,24 FBA_DQS#[7..0]

UV1B
D D

Part 2 of 6

FBA_D0 E18 C27 FBA_CS0#

FBA_D00 FBA_CMD00 FBA_CS0# 23
FBA_D1 F18 C26
FBA_D2 E16 FBA_D01 FBA_CMD01 E24 FBA_ODT0
FBA_D02 FBA_CMD02 FBA_ODT0 23
FBA_D3 F17 F24 FBA_CKE0
FBA_D03 FBA_CMD03 FBA_CKE0 23
FBA_D4 D20 D27 FBA_A14
FBA_D5 D21 FBA_D04
FBA_D05
FBA_CMD04
FBA_CMD05
D26 FBA_RST#
FBA_A14
FBA_RST#
23,24
23,24
CMD mapping mod Mode D
FBA_D6 F20 F25 FBA_A9
FBA_D06 FBA_CMD06 FBA_A9 23,24
FBA_D7 E21 F26 FBA_A7 Rank0
FBA_D07 FBA_CMD07 FBA_A7 23,24
FBA_D8 E15 F23 FBA_A2
FBA_D08 FBA_CMD08 FBA_A2 23,24
FBA_D9 D15 G22 FBA_A0 Address 0..31 32..63
FBA_D09 FBA_CMD09 FBA_A0 23,24
FBA_D10 F15 G23 FBA_A4
FBA_D10 FBA_CMD10 FBA_A4 23,24
FBA_D11 F13 G24 FBA_A1 FBx_CMD0 CS0#
FBA_D11 FBA_CMD11 FBA_A1 23,24
FBA_D12 C13 F27 FBA_BA0
FBA_D12 FBA_CMD12 FBA_BA0 23,24
FBA_D13 B13 G25 FBA_WE FBx_CMD1
FBA_D13 FBA_CMD13 FBA_WE 23,24
FBA_D14 E13 G27
FBA_D15 D13 FBA_D14 FBA_CMD14 G26 FBA_CAS#
FBA_D15 FBA_CMD15 FBA_CAS# 23,24 FBx_CMD2 ODT0
FBA_D16 B15 M24 FBA_CS1#
FBA_D16 FBA_CMD16 FBA_CS1# 24
FBA_D17 C16 M23 FBx_CMD3 CKE0
FBA_D18 A13 FBA_D17 FBA_CMD17 K24 FBA_ODT1
FBA_D18 FBA_CMD18 FBA_ODT1 24
FBA_D19 A15 K23 FBA_CKE1 FBx_CMD4 A14 A14
FBA_D19 FBA_CMD19 FBA_CKE1 24
FBA_D20 B18 M27 FBA_A13
FBA_D20 FBA_CMD20 FBA_A13 23,24
FBA_D21 A18 M26 FBA_A8 FBx_CMD5 RST RST
FBA_D21 FBA_CMD21 FBA_A8 23,24
FBA_D22 A19 M25 FBA_A6
FBA_D22 FBA_CMD22 FBA_A6 23,24
FBA_D23 C19 K26 FBA_A11 FBx_CMD6 A9 A9
FBA_D23 FBA_CMD23 FBA_A11 23,24
FBA_D24 B24 K22 FBA_A5
FBA_D24 FBA_CMD24 FBA_A5 23,24
FBA_D25 C23 J23 FBA_A3 FBx_CMD7 A7 A7
FBA_D25 FBA_CMD25 FBA_A3 23,24
FBA_D26 A25 J25 FBA_BA2
FBA_D26 FBA_CMD26 FBA_BA2 23,24
FBA_D27 A24 J24 FBA_BA1 FBx_CMD8 A2 A2
FBA_D27 FBA_CMD27 FBA_BA1 23,24
FBA_D28 A21 K27 FBA_A12
FBA_D28 FBA_CMD28 FBA_A12 23,24
FBA_D29 B21 K25 FBA_A10 FBx_CMD9 A0 A0
FBA_D29 FBA_CMD29 FBA_A10 23,24
FBA_D30 C20 J27 FBA_RAS#
FBA_D30 FBA_CMD30 FBA_RAS# 23,24
FBA_D31 C21 J26 FBx_CMD10 A4 A4
FBA_D32 R22 FBA_D31 FBA_CMD31 B19 +1.35VGS
C FBA_D33 R24 FBA_D32 FBA_CMD32 Symbol update to FBA_CMD34/35 FBx_CMD11 A1 A1 C

INTERFACE A
FBA_D34 T22 FBA_D33 F22 RV121 2 @ 1 60.4_0402_1%
FBA_D35 R23 FBA_D34 FBA_CMD34 J22 RV122 2 1 60.4_0402_1%
FBA_D35 FBA_CMD35 FBx_CMD12 BA0 BA0
FBA_D36 N25 @
FBA_D37 N26 FBA_D36 D19 FBA_DQM0 FBx_CMD13 WE WE

MEMORY
FBA_D38 N23 FBA_D37 FBA_DQM0 D14 FBA_DQM1
FBA_D39 N24 FBA_D38 FBA_DQM1 C17 FBA_DQM2
30ohms (ESR=0.01) Bead FBA_D39 FBA_DQM2 FBx_CMD14 A15 A15
FBA_D40 V23 C22 FBA_DQM3
FBA_D41 V22 FBA_D40 FBA_DQM3 P24 FBA_DQM4
+1.05VGS +FB_PLLAVDD FBA_D41 FBA_DQM4 FBx_CMD15 CAS# CAS#
FBA_D42 T23 W24 FBA_DQM5
FBA_D43 U22 FBA_D42 FBA_DQM5 AA25 FBA_DQM6
200mA FBA_D43 FBA_DQM6 FBx_CMD16 CS1#
FBA_D44 Y24 U25 FBA_DQM7
1 2 LV4 FBA_D45 AA24 FBA_D44 FBA_DQM7
FBA_D45 FBx_CMD17
HCB1608KF-300T60_2P FBA_D46 Y22 F19 FBA_DQS#0
FBA_D47 AA23 FBA_D46 FBA_DQS_RN0 C14 FBA_DQS#1
OPT@ FBA_D47 FBA_DQS_RN1 FBx_CMD18 ODT1
FBA_D48 AD27 A16 FBA_DQS#2
FBA_D49 AB25 FBA_D48 FBA_DQS_RN2 A22 FBA_DQS#3
Place close to BGA FBA_D49 FBA_DQS_RN3 FBx_CMD19 CKE1
FBA_D50 AD26 P25 FBA_DQS#4
FBA_D51 AC25 FBA_D50 FBA_DQS_RN4 W22 FBA_DQS#5
0.1uFX2 ,22uFX1 FBA_D51 FBA_DQS_RN5 FBx_CMD20 A13 A13
FBA_D52 AA27 AB27 FBA_DQS#6
FBA_D53 AA26 FBA_D52 FBA_DQS_RN6 T27 FBA_DQS#7
Place close to BGA Place close to ball FBA_D53 FBA_DQS_RN7 FBx_CMD21 A8 A8
FBA_D54 W26
FBA_D55 Y25 FBA_D54 E19 FBA_DQS0
+FB_PLLAVDD FBA_D55 FBA_DQS_WP0 FBx_CMD22 A6 A6
22U_0603_6.3V6-M

FBA_D56 R26 C15 FBA_DQS1

0.1U_0402_10V7K

0.1U_0402_10V7K

FBA_D56 FBA_DQS_WP1
CV111

CV112

CV113

1 1 1 FBA_D57 T25 B16 FBA_DQS2 FBx_CMD23 A11 A11

FBA_D58 N27 FBA_D57 FBA_DQS_WP2 B22 FBA_DQS3
FBA_D59 R27 FBA_D58 FBA_DQS_WP3 R25 FBA_DQS4
FBA_D59 FBA_DQS_WP4 FBx_CMD24 A5 A5
FBA_D60 V26 W23 FBA_DQS5
2 2 2 FBA_D61 V27 FBA_D60 FBA_DQS_WP5 AB26 FBA_DQS6
FBA_D61 FBA_DQS_WP6 FBx_CMD25 A3 A3
OPT@ FBA_D62 W27 T26 FBA_DQS7
OPT@ OPT@ FBA_D63 W25 FBA_D62 FBA_DQS_WP7
FBA_D63 FBx_CMD26 BA2 BA2
D24 FBA_CLK0
FBA_CLK0 FBA_CLK0 23
F16 D25 FBA_CLK0# FBx_CMD27 BA1 BA1
FB_PLLAVDD_1 FBA_CLK0_N FBA_CLK0# 23
P22
FB_PLLAVDD_2 N22 FBA_CLK1
FBA_CLK1 FBA_CLK1 24 FBx_CMD28 A12 A12
D23 M22 FBA_CLK1#
FB_VREF FBA_CLK1_N FBA_CLK1# 24
+FB_PLLAVDD FBx_CMD29 A10 A10
Place close to ball D18
B
1 2 CV115 H22 FBA_WCK01 C18 B
FB_DLLAVDD FBA_WCK01_N FBx_CMD30 RAS# RAS#
OPT@ 0.1U_0402_10V7K D17
FB_GC6_EN RV119 1 @ 2 0_0402_5% FB_CLAMP F3 FBA_WCK23 D16
FB_CLAMP FBA_WCK23_N FBx_CMD31
RV120 1 OPT@ 2 10K_0402_5% T24
FBA_WCK45 U24
FBA_WCK45_N FBx_CMD32
V24
FBA_WCK67 V25
FBA_WCK67_N FBx_CMD33
FBx_CMD34 DBG0
FBx_CMD35 DBG1
N15S-GT-S-A2_FCBGA595
N15SGT@

RV123 DV4 GC6@

18 FB_GC6_EN FB_GC6_EN 1 2 0_0402_5% GC6_EN 2
@ 1
FBVDDQ_PWR_EN 20
3
1

+3VGS RV124 1 2 BAV70W-7-F_SOT323-3

10K_0402_5% RV125
200K_0402_5%
OPT@ GC6@
41,43 DGPU_PWROK
2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 20140213 N15X_MEM Interface
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Haydn-S
Date: Wednesday, July 22, 2015 Sheet 22 of 46
5 4 3 2 1
 5 4 3 2 1

at least 16 mils width(optimal)

20 mils spacing to other signals /planes FBA_D[0..63] 22,24
+1.35VGS
D D
1

RANKA@
FBA_DQM[7..0] 22,24
RV128
1.33K_0402_1% UV6 UV5
FBA_DQS[7..0] 22,24
2

+FBA_VREFCA0 +FBA_VREFCA0 M8 E3 FBA_D25 +FBA_VREFCA0 M8 E3 FBA_D12

VREFCA DQL0 VREFCA DQL0 FBA_DQS#[7..0] 22,24
+FBA_VREFDQ0 H1 F7 FBA_D28 +FBA_VREFDQ0 H1 F7 FBA_D11
VREFDQ DQL1 VREFDQ DQL1 CMD mapping mod Mode D
1

1 F2 FBA_D27 F2 FBA_D15
RANKA@ CV116 FBA_A0 N3 DQL2 F8 FBA_D29 FBA_A0 N3 DQL2 F8 FBA_D8
22,24 FBA_A0 A0 DQL3 Group3 A0 DQL3 Group1
RV127 .01U_0402_16V7-K FBA_A1 P7 H3 FBA_D26 FBA_A1 P7 H3 FBA_D9 Rank0
22,24 FBA_A1 A1 DQL4 A1 DQL4
1.33K_0402_1% RANKA@ FBA_A2 P3 H8 FBA_D30 FBA_A2 P3 H8 FBA_D14
2 22,24 FBA_A2 A2 DQL5 A2 DQL5
FBA_A3 N2 G2 FBA_D24 FBA_A3 N2 G2 FBA_D13 Address 0..31 32..63
22,24 FBA_A3
2

FBA_A4 P8 A3 DQL6 H7 FBA_D31 FBA_A4 P8 A3 DQL6 H7 FBA_D10

22,24 FBA_A4 A4 DQL7 A4 DQL7
FBA_A5 P2 FBA_A5 P2 FBx_CMD0 CS0#
22,24 FBA_A5 A5 A5
FBA_A6 R8 FBA_A6 R8
22,24 FBA_A6 A6 A6
FBA_A7 R2 D7 FBA_D1 FBA_A7 R2 D7 FBA_D17 FBx_CMD1
22,24 FBA_A7 A7 DQU0 A7 DQU0
FBA_A8 T8 C3 FBA_D6 FBA_A8 T8 C3 FBA_D23
22,24 FBA_A8 A8 DQU1 A8 DQU1
FBA_A9 R3 C8 FBA_D2 FBA_A9 R3 C8 FBA_D18 FBx_CMD2 ODT0
22,24 FBA_A9 A9 DQU2 A9 DQU2
FBA_A10 L7 C2 FBA_D5 FBA_A10 L7 C2 FBA_D20
22,24 FBA_A10 A10/AP DQU3 A10/AP DQU3
+1.35VGS FBA_A11 R7 A7 FBA_D0 Group0 FBA_A11 R7 A7 FBA_D16 Group2 FBx_CMD3 CKE0
22,24 FBA_A11 A11 DQU4 A11 DQU4
FBA_A12 N7 A2 FBA_D7 FBA_A12 N7 A2 FBA_D21
22,24 FBA_A12 A12/BC DQU5 A12/BC DQU5
FBA_A13 T3 B8 FBA_D3 FBA_A13 T3 B8 FBA_D22 FBx_CMD4 A14 A14
22,24 FBA_A13 A13 DQU6 A13 DQU6
1

FBA_A14 T7 A3 FBA_D4 FBA_A14 T7 A3 FBA_D19

22,24 FBA_A14 A14 DQU7 A14 DQU7
RANKA@ FBx_CMD5 RST RST
RV167 +1.35VGS +1.35VGS
1.33K_0402_1% FBx_CMD6 A9 A9
FBA_BA0 M2 B2 FBA_BA0 M2 B2
22,24 FBA_BA0
2

+FBA_VREFDQ0 FBA_BA1 N8 BA0 VDD_1 D9 FBA_BA1 N8 BA0 VDD_1 D9

22,24 FBA_BA1 BA1 VDD_2 BA1 VDD_2 FBx_CMD7 A7 A7
FBA_BA2 M3 G7 FBA_BA2 M3 G7
22,24 FBA_BA2 BA2 VDD_3 BA2 VDD_3
1

1 K2 K2 FBx_CMD8 A2 A2
RANKA@ CV216 VDD_4 K8 VDD_4 K8
RV168 .01U_0402_16V7-K VDD_5 N1 VDD_5 N1
VDD_6 VDD_6 FBx_CMD9 A0 A0
1.33K_0402_1% RANKA@ FBA_CLK0 J7 N9 FBA_CLK0 J7 N9
2 22 FBA_CLK0 CK VDD_7 CK VDD_7
FBA_CLK0# K7 R1 FBA_CLK0# K7 R1 FBx_CMD10 A4 A4
22 FBA_CLK0#
2

FBA_CKE0 K9 CK VDD_8 R9 FBA_CKE0 K9 CK VDD_8 R9

22 FBA_CKE0 CKE VDD_9 CKE VDD_9
FBx_CMD11 A1 A1
C C
FBA_ODT0 K1 A1 FBA_ODT0 K1 A1 FBx_CMD12 BA0 BA0
22 FBA_ODT0 ODT VDDQ_1 ODT VDDQ_1
FBA_CS0# L2 A8 FBA_CS0# L2 A8
22 FBA_CS0# CS VDDQ_2 CS VDDQ_2
FBA_RAS# J3 C1 FBA_RAS# J3 C1 FBx_CMD13 WE WE
22,24 FBA_RAS# RAS VDDQ_3 RAS VDDQ_3
FBA_CAS# K3 C9 FBA_CAS# K3 C9
22,24 FBA_CAS# CAS VDDQ_4 CAS VDDQ_4
FBA_WE L3 D2 FBA_WE L3 D2 FBx_CMD14 A15 A15
22,24 FBA_WE WE VDDQ_5 WE VDDQ_5
E9 E9
VDDQ_6 F1 VDDQ_6 F1
VDDQ_7 VDDQ_7 FBx_CMD15 CAS# CAS#
FBA_DQS3 F3 H2 FBA_DQS1 F3 H2
FBA_CLK0 FBA_DQS0 C7 DQSL VDDQ_8 H9 FBA_DQS2 C7 DQSL VDDQ_8 H9
DQSU VDDQ_9 DQSU VDDQ_9 FBx_CMD16 CS1#
FBx_CMD17
1

FBA_DQM3 E7 A9 FBA_DQM1 E7 A9
RV129 FBA_DQM0 D3 DML VSS_1 B3 FBA_DQM2 D3 DML VSS_1 B3
DMU VSS_2 DMU VSS_2 FBx_CMD18 ODT1
162_0402_1% E1 E1
RANKA@ VSS_3 G8 VSS_3 G8
VSS_4 VSS_4 FBx_CMD19 CKE1
FBA_DQS#3 G3 J2 FBA_DQS#1 G3 J2
2

FBA_DQS#0 B7 DQSL VSS_5 J8 FBA_DQS#2 B7 DQSL VSS_5 J8

DQSU VSS_6 DQSU VSS_6 FBx_CMD20 A13 A13
FBA_CLK0# M1 M1
VSS_7 M9 VSS_7 M9
VSS_8 VSS_8 FBx_CMD21 A8 A8
P1 P1
FBA_RST# T2 VSS_9 P9 FBA_RST# T2 VSS_9 P9
22,24 FBA_RST# RESET VSS_10 RESET VSS_10 FBx_CMD22 A6 A6
1

T1 T1
RV131 1 2 RV130 L8 VSS_11 T9 L8 VSS_11 T9
ZQ VSS_12 ZQ VSS_12 FBx_CMD23 A11 A11

1
10K_0402_5% 243_0402_1%
RANKA@ RANKA@ RV132 FBx_CMD24 A5 A5
J1 B1 243_0402_1% J1 B1
2

L1 NC1 VSSQ_1 B9 RANKA@ L1 NC1 VSSQ_1 B9

NC2 VSSQ_2 NC2 VSSQ_2 FBx_CMD25 A3 A3
J9 D1 J9 D1

2
FBA_ODT0 L9 NC3 VSSQ_3 D8 L9 NC3 VSSQ_3 D8
NC4 VSSQ_4 NC4 VSSQ_4 FBx_CMD26 BA2 BA2
M7 E2 M7 E2
NC5 VSSQ_5 E8 NC5 VSSQ_5 E8
VSSQ_6 VSSQ_6 FBx_CMD27 BA1 BA1
FBA_CKE0 F9 F9
VSSQ_7 G1 VSSQ_7 G1
VSSQ_8 VSSQ_8 FBx_CMD28 A12 A12
G9 G9
VSSQ_9 VSSQ_9
1

FBx_CMD29 A10 A10

RV133 RV134 96-BALL 96-BALL
10K_0402_5% 10K_0402_5% SDRAM DDR3 SDRAM DDR3 FBx_CMD30 RAS# RAS#
B B
RANKA@ RANKA@ K4W4G1646B-HC11_FBGA96 K4W4G1646B-HC11_FBGA96
@ @ FBx_CMD31
2

FBx_CMD32
FBx_CMD33
FBx_CMD34 DBG0
FBx_CMD35 DBG1

+1.35VGS UV6 SIDE +1.35VGS +1.35VGS UV5 SIDE +1.35VGS

For RF
1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M
33P_0402_50V8J

33P_0402_50V8J
0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
CV117

CV118

CV119

CV120

CV121

CV122

CV127

CV129

CV130

CV131

CV132

CV133

CV134

CV139
1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2 2
For RF
RANKA@ RANKA@ RANKA@ RANKA@ CD@ RANKA@ RF_OPTNS@ RANKA@ RANKA@ CD@ RANKA@ RANKA@ RANKA@ RF_OPTNS@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 20140213 DDR3 VRAM Rank0_L
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Haydn-S
Date: Wednesday, July 22, 2015 Sheet 23 of 46
5 4 3 2 1
 5 4 3 2 1

at least 16 mils width(optimal)

20 mils spacing to other signals /planes

+1.35VGS
1

D FBA_D[0..63] 22,23 D
RANKA@
RV135
1.33K_0402_1%
UV8 UV7
2

+FBA_VREFCA1
FBA_DQM[7..0] 22,23
+FBA_VREFCA1 M8 E3 FBA_D53 +FBA_VREFCA1 M8 E3 FBA_D40
VREFCA DQL0 VREFCA DQL0
1

1 +FBA_VREFDQ1 H1 F7 FBA_D55 +FBA_VREFDQ1 H1 F7 FBA_D43

VREFDQ DQL1 VREFDQ DQL1 FBA_DQS[7..0] 22,23
RANKA@ CV141 F2 FBA_D52 F2 FBA_D41
RV136 .01U_0402_16V7-K FBA_A0 N3 DQL2 F8 FBA_D50 FBA_A0 N3 DQL2 F8 FBA_D42
22,23 FBA_A0 A0 DQL3 A0 DQL3 Group5 FBA_DQS#[7..0] 22,23
1.33K_0402_1% RANKA@ FBA_A1 P7 H3 FBA_D48 Group6 FBA_A1 P7 H3 FBA_D45
2 22,23
22,23
FBA_A1
FBA_A2
FBA_A2 P3 A1 DQL4 H8 FBA_D51 FBA_A2 P3 A1 DQL4 H8 FBA_D47 CMD mapping mod Mode D
2

FBA_A3 N2 A2 DQL5 G2 FBA_D54 FBA_A3 N2 A2 DQL5 G2 FBA_D44

22,23 FBA_A3 A3 DQL6 A3 DQL6
FBA_A4 P8 H7 FBA_D49 FBA_A4 P8 H7 FBA_D46 Rank0
22,23 FBA_A4 A4 DQL7 A4 DQL7
FBA_A5 P2 FBA_A5 P2
22,23 FBA_A5 A5 A5
FBA_A6 R8 FBA_A6 R8 Address 0..31 32..63
22,23 FBA_A6 A6 A6
FBA_A7 R2 D7 FBA_D32 FBA_A7 R2 D7 FBA_D57
22,23 FBA_A7 A7 DQU0 A7 DQU0
FBA_A8 T8 C3 FBA_D39 FBA_A8 T8 C3 FBA_D63 FBx_CMD0 CS0#
22,23 FBA_A8 A8 DQU1 A8 DQU1
FBA_A9 R3 C8 FBA_D33 FBA_A9 R3 C8 FBA_D59
22,23 FBA_A9 A9 DQU2 A9 DQU2
+1.35VGS FBA_A10 L7 C2 FBA_D36 FBA_A10 L7 C2 FBA_D62 FBx_CMD1
22,23 FBA_A10 A10/AP DQU3 A10/AP DQU3
FBA_A11 R7 A7 FBA_D35 Group4 FBA_A11 R7 A7 FBA_D56 Group7
22,23 FBA_A11 A11 DQU4 A11 DQU4
FBA_A12 N7 A2 FBA_D38 FBA_A12 N7 A2 FBA_D61 FBx_CMD2 ODT0
22,23 FBA_A12 A12/BC DQU5 A12/BC DQU5
1

FBA_A13 T3 B8 FBA_D34 FBA_A13 T3 B8 FBA_D58

22,23 FBA_A13 A13 DQU6 A13 DQU6
RANKA@ FBA_A14 T7 A3 FBA_D37 FBA_A14 T7 A3 FBA_D60 FBx_CMD3 CKE0
22,23 FBA_A14 A14 DQU7 A14 DQU7
RV169
1.33K_0402_1% +1.35VGS +1.35VGS FBx_CMD4 A14 A14
2

+FBA_VREFDQ1 FBA_BA0 M2 B2 FBA_BA0 M2 B2 FBx_CMD5 RST RST

22,23 FBA_BA0 BA0 VDD_1 BA0 VDD_1
FBA_BA1 N8 D9 FBA_BA1 N8 D9
22,23 FBA_BA1 BA1 VDD_2 BA1 VDD_2
1

1 FBA_BA2 M3 G7 FBA_BA2 M3 G7 FBx_CMD6 A9 A9

22,23 FBA_BA2 BA2 VDD_3 BA2 VDD_3
RANKA@ CV217 K2 K2
RV170 .01U_0402_16V7-K VDD_4 K8 VDD_4 K8
VDD_5 VDD_5 FBx_CMD7 A7 A7
1.33K_0402_1% RANKA@ N1 N1
2 FBA_CLK1 J7 VDD_6 N9 FBA_CLK1 J7 VDD_6 N9
22 FBA_CLK1 FBx_CMD8 A2 A2
2

FBA_CLK1# K7 CK VDD_7 R1 FBA_CLK1# K7 CK VDD_7 R1

22 FBA_CLK1# CK VDD_8 CK VDD_8
FBA_CKE1 K9 R9 FBA_CKE1 K9 R9 FBx_CMD9 A0 A0
22 FBA_CKE1 CKE VDD_9 CKE VDD_9
FBx_CMD10 A4 A4
C FBA_ODT1 K1 A1 FBA_ODT1 K1 A1 C
22 FBA_ODT1 ODT VDDQ_1 ODT VDDQ_1
FBA_CS1# L2 A8 FBA_CS1# L2 A8 FBx_CMD11 A1 A1
22 FBA_CS1# CS VDDQ_2 CS VDDQ_2
FBA_RAS# J3 C1 FBA_RAS# J3 C1
22,23 FBA_RAS# RAS VDDQ_3 RAS VDDQ_3
FBA_CAS# K3 C9 FBA_CAS# K3 C9 FBx_CMD12 BA0 BA0
22,23 FBA_CAS# CAS VDDQ_4 CAS VDDQ_4
FBA_WE L3 D2 FBA_WE L3 D2
22,23 FBA_WE WE VDDQ_5 WE VDDQ_5
FBA_CLK1 E9 E9 FBx_CMD13 WE WE
VDDQ_6 F1 VDDQ_6 F1
FBA_DQS6 F3 VDDQ_7 H2 FBA_DQS5 F3 VDDQ_7 H2
DQSL VDDQ_8 DQSL VDDQ_8 FBx_CMD14 A15 A15
1

FBA_DQS4 C7 H9 FBA_DQS7 C7 H9
RV137 DQSU VDDQ_9 DQSU VDDQ_9
FBx_CMD15 CAS# CAS#
162_0402_1%
FBA_DQM6 E7 A9 FBA_DQM5 E7 A9 FBx_CMD16 CS1#
RANKA@ FBA_DQM4 D3 DML VSS_1 B3 FBA_DQM7 D3 DML VSS_1 B3
2

DMU VSS_2 E1 DMU VSS_2 E1

VSS_3 VSS_3 FBx_CMD17
FBA_CLK1# G8 G8
FBA_DQS#6 G3 VSS_4 J2 FBA_DQS#5 G3 VSS_4 J2
DQSL VSS_5 DQSL VSS_5 FBx_CMD18 ODT1
FBA_DQS#4 B7 J8 FBA_DQS#7 B7 J8
DQSU VSS_6 M1 DQSU VSS_6 M1
VSS_7 VSS_7 FBx_CMD19 CKE1
M9 M9
VSS_8 P1 VSS_8 P1
VSS_9 VSS_9 FBx_CMD20 A13 A13
FBA_RST# T2 P9 FBA_RST# T2 P9
22,23 FBA_RST# RESET VSS_10 RESET VSS_10
T1 T1 FBx_CMD21 A8 A8
L8 VSS_11 T9 L8 VSS_11 T9
FBA_CKE1 ZQ VSS_12 ZQ VSS_12
FBx_CMD22 A6 A6

1
J1 B1 RV141 J1 B1 FBx_CMD23 A11 A11
NC1 VSSQ_1 NC1 VSSQ_1
1

FBA_ODT1 L1 B9 243_0402_1% L1 B9
RV140 J9 NC2 VSSQ_2 D1 RANKA@ J9 NC2 VSSQ_2 D1
NC3 VSSQ_3 NC3 VSSQ_3 FBx_CMD24 A5 A5
243_0402_1% L9 D8 L9 D8

2
RANKA@ M7 NC4 VSSQ_4 E2 M7 NC4 VSSQ_4 E2
NC5 VSSQ_5 NC5 VSSQ_5 FBx_CMD25 A3 A3
1

E8 E8
2

RV138 RV139 VSSQ_6 F9 VSSQ_6 F9

VSSQ_7 VSSQ_7 FBx_CMD26 BA2 BA2
10K_0402_5% 10K_0402_5% G1 G1
RANKA@ RANKA@ VSSQ_8 G9 VSSQ_8 G9
VSSQ_9 VSSQ_9 FBx_CMD27 BA1 BA1
2

96-BALL 96-BALL FBx_CMD28 A12 A12

SDRAM DDR3 SDRAM DDR3
K4W4G1646B-HC11_FBGA96 K4W4G1646B-HC11_FBGA96 FBx_CMD29 A10 A10
B B
@ @
FBx_CMD30 RAS# RAS#
FBx_CMD31
FBx_CMD32
FBx_CMD33
FBx_CMD34 DBG0
FBx_CMD35 DBG1

+1.35VGS UV8 SIDE +1.35VGS +1.35VGS UV7 SIDE +1.35VGS

For RF For RF
1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M
33P_0402_50V8J

33P_0402_50V8J
0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
CV142

CV143

CV144

CV145

CV146

CV147

CV152

CV154

CV155

CV156

CV157

CV158

CV159

CV164
1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2 2

RANKA@ RANKA@ CD@ RANKA@ RANKA@ RANKA@ RANKA@ RANKA@ RANKA@ RANKA@ RANKA@ CD@
RF_OPTNS@ RF_OPTNS@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 20140213 DDR3 VRAM Rank0_H
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Haydn-S
Date: Wednesday, July 22, 2015 Sheet 24 of 46
5 4 3 2 1
 5 4 3 2 1

+3VG_AON Physical Logical Logical Logical Logical

Strapping pin Power Rail Strapping Bit3 Strapping Bit2 Strapping Bit1 Strapping Bit0
D D
ROM_SCLK +3VGS SOR3_EXPOSED SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED
ROM_SI +3VGS RAM_CFG[3] RAM_CFG[2] RAM_CFG[1] RAM_CFG[0]
ROM_SO +3VGS DEVID_SEL PCIE_CFG SMB_ALT_ADDR VGA_DEVICE

2
RV146 RV147 RV148 RV149 RV150 STRAP0 +3VGS Reserved(keep pull-up and pull-down footprint and stuff 50Kohm pull-up)
49.9K_0402_1% 4.99K_0402_1% 24.9K_0402_1% 4.99K_0402_1% 45.3K_0402_1%
N15SGT@ @ @ @ @ STRAP1 +3VGS

1
STRAP2 +3VGS
19 STRAP0 STRAP0 Reserved(keep pull-up and pull-down footprint and not stuff by default)
19 STRAP1 STRAP1 STRAP3 +3VGS
19 STRAP2 STRAP2
19 STRAP3 STRAP3 STRAP4 +3VGS
19 STRAP4 STRAP4

DEVID_SEL
2

2
Pull-up to
RV151 RV152 RV153 RV154 RV155 Resistor Values Pull-down to Gnd
45.3K_0402_1% 4.99K_0402_1% 15K_0402_1% 4.99K_0402_1% 45.3K_0402_1%
+3VGS
0 (Default)
@ @ @ @ @ 4.99K 1000 0000
1

1
10K 1001 0001 1
15K 1010 0010
20K 1011 0011 PCIE_CFG
24.9K 1100 0100
0 (Default)
30.1K 1101 0101
34.8K 1110 0110 1
+3VGS 45.3K 1111 0111
C C

SMBUS_ALT_ADDR
N15x Binary Straps
0 0x9E (Default)
2

2 Physical
RV156 RV157 RV158 Power Rail Strap Mapping
4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
Strapping pin
1 0x9C (Multi-GPU usage)
@ @ @ ROM_SCLK +3VGS SMB_ALT_ADDR
1

ROM_SI +3VGS SUB_VENDOR

ROM_SO +3VGS VGA_DEVICE VGA_DEVICE
19 ROM_SI ROM_SI
19 ROM_SO ROM_SO STRAP0 +3VGS RAM_CFG[0] 0 3D Device (Class Code 302h)
19 ROM_SCLK ROM_SCLK
STRAP1 +3VGS RAM_CFG[1]
1 VGA Device (Default)
2

STRAP2 +3VGS RAM_CFG[2]

RV159 RV160 RV161
X76 20K_0402_1% 4.99K_0402_1% 4.99K_0402_1% STRAP3 +3VGS RAM_CFG[3]
@ N15SGT@ N15SGT@
STRAP4 +3VGS PCIE_MAX_SPEED
1

X76

GPU FB Memory (DDR3) ROM_SI ROM_SO ROM_SCLK STRAP0 STRAP1 STRAP2 STRAP3 STRAP4
B H5TC4G63CFR-N0C 0x2 B
Hynix VRAM X76 VRAM P/N
900MHz 256M x 16 PD 15K
MT41J256M16HA-093G:E 0x4 Samsung X7607312002 SA000063F20
Micron
900MHz 256M x 16 PD 24.9K
Micron X7607312003 SA000060I10
K4W4G1646E-BC1A 0x1
Samsung
900MHz 256M x 16 PD 10K Hynix X7607312001 SA00007DU10
N16S-GT PD 4.99K PD 4.99K PU 49.9K Un-stuff Un-stuff Un-stuff Un-stuff
H5TC2G63FFR-11C 0x9
Hynix
900MHz 128M x 16 PU 10K

Micron MT41J128M16JT-093G:K 0xA

900MHz
128M x 16 PU 15K
Samsung K4W2G1646Q-BC1A 0xB
900MHz
128M x 16 PU 20K

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 20140213 N15X_MISC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Haydn-S
Date: Wednesday, July 22, 2015 Sheet 25 of 46
5 4 3 2 1
 5 4 3 2 1

LCD
PWR +3VS
+3VS_LCDVCC
U9
5 1 1 2
IN OUT 0_0603_5% R2

C22
4.7U_0402_6.3V6M

C23
.1U_0402_10V6-K
2 1 1
GND
4 3
EN
AP22802AW5-7_SOT25-5
FLG
2 2
Hot-Plug

0210 change
PCH_LCD_VDDEN R183 1 2 0_0402_5%
4 PCH_LCD_VDDEN

B+

C21
.1U_0402_10V6-K
1
@
D D
2

2
R351 R235 2
0_0402_5% 100K_0402_5%
1

1
R237 2 1 LVDS_VDD_EN#
100K_0402_5% EDP_HPD_OUT R184 1 2 0_0402_5%
PCH_EDP_HPD 4

0.1U_0402_25V6
1

1
D

1
C209
2
G Q17 R80

2
C25
.1U_0402_10V6-K

1 2N7002KW_SOT323-3 100K_0402_5%
@

S
3

2
2

B+ +LCD_VDD
L31 EDP_HPD
1@ 2
BLM15PX121SN1D_2P *EDP EN,EDP-HPD EN
2 EDP EN, EDP-HPD Disabled, 10K PU Via VCCIO
1

EDP Disabled, NC
C200
10U_0805_25V6K

C206
0.1U_0402_25V6

L38
1@ 2
2

BLM15PX121SN1D_2P 1

Q25
S

3 1
AO3401A_SOT23-3

Q17
G
2

换5800E
LVDS_VDD_EN#
Q25
换 AO3401A

BKLT CNTL +3VS

C
For LCD CONN YOGA3_11" C
2

R43 JLVDS ME@

1K_0402_5%
@ 1
C42 1 2 .1U_0402_10V6-K PCH_EDP_TX1-_C 2 1
4 PCH_EDP_TX1-
1

C43 1 2 .1U_0402_10V6-K PCH_EDP_TX1+_C 3 2

4 PCH_EDP_TX1+ 3
R185 1 2 0_0402_5% LCD_BKLT_CTRL 4
4 PCH_BKLT_CTRL 4
4 PCH_EDP_TX0- C38 1 2 .1U_0402_10V6-K PCH_EDP_TX0-_C 5
C39 1 2 .1U_0402_10V6-K PCH_EDP_TX0+_C 6 5
4 PCH_EDP_TX0+ 6 Touch
1

C28
.1U_0402_10V6-K
@

0529 1 7 +3VS 500mA(Max: 200mA) +3VALW_TOUCH

R24 C40 1 2 .1U_0402_10V6-K PCH_EDP_AUX+_C 8 7
Change R347 to R-Short 4 PCH_EDP_AUX+ 8
100K_0402_5% 4 PCH_EDP_AUX- C41 1 2 .1U_0402_10V6-K PCH_EDP_AUX-_C 9 +3VS 500mA(Max: 300mA) +3VS_TOUCH 0_0603_5% 2 @ 1 R25
10 9
2 10

C44
.1U_0402_10V6-K

C45
.1U_0402_10V6-K
CD@
+3VS_LCDVCC 11 2 1 1 1
2

12 11 R22 0_0603_5% CD@

12

C32
.1U_0402_10V6-K

C31
.1U_0402_10V6-K
CD@
40MIL EDP_HPD_OUT 13 1 1
LCD_BKLT_EN 14 13 CD@
LCD_BKLT_CTRL 15 14 2 2
16 15
16 2
Touch Panel Poer USB20 Port6 2
+LCD_VDD 17
18 17
19 18
20 19
21 20 +3VALW +3VALW_TOUCH
22 21
+3VS_DMIC 22
DMIC_DATA RA286 1 2 0_0402_5% 23
29 DMIC_DATA 23
DMIC_CLK RA287 1 2 0_0402_5% 24 0_0603_5% 2 @ 1 R3005
29 DMIC_CLK 24
25
26 25
2 1 D2 1 2 LCD_BKLT_EN MCU_I2C_RE_SDA 27 26
30 EC_LID_OUT# 28 MCU_I2C_RE_SDA 27
R39 1K_0402_5% MCU_I2C_RE_SCL 28
28 MCU_I2C_RE_SCL 28
@ +3VS 1 2 29
RB751V-40_SOD323-2 R26 0_0603_5% 30 29
@ +3VS_CMOS 31 30 +3VALW_TOUCH
8 USB20_P0 31 +3VALW
1A 32
8 USB20_N0 32
33 Q2
34 33 LP2301ALT1G_SOT23-3 ID=2.8A
+3VS_TOUCH 34
35
8 USB20_N6 35

D
+3VALW_TOUCH 36 3 1
8 USB20_P6 36
37
EC_LID_OUT# R227 1 2 0_0402_5% 38 37
38

C338
.1U_0402_10V6-K

C339
0.01U_0402_25V7K
39 41 @

G
1 1

2
40 39 GND1 42
LCD背光控制，LID控制以及PCH的热键控制都NC，直接由EC来做背光控制. 30 WIN8_BUTTON# 40 GND2
I-PEX_20374-040E-31 @
2 2

1 2
B 30,33,38 EC_USB_ON# B
R909 0_0402_5%

for win8 button wake up 1

C340
.1U_0402_10V6-K
2 1 LCD_BKLT_EN @
30 EC_BKLT_EN 2
R349 1K_0402_5%
1

2 @ 1
4,30 PCH_BKLT_EN
R54
100K_0402_5%

C29
.1U_0402_10V6-K

R350 1K_0402_5% 1
CD@
PCH_BKLT_EN 0415 update
2

2
USB20_N6

USB20_P6 +3VS_TOUCH

0801 reserve for touch panel

2

2
D8 D7
2

AZ5425-01F_DFN1006P2E2 AZ5425-01F_DFN1006P2E2 U55

2
AZ5123-01F.R7G_DFN1006P2X2
EMC_NS@ EMC_NS@ EMC_NS@
1

1
1

1
+3VALW_TOUCH

1
R169
10K_0402_5%
@

2
Camera WIN8_BUTTON#

+3VS +3VS_CMOS

2
A A

500mA(Max: 117mA) U57

2
DMIC AZ5725-01F_DFN1006P2X2 1

CG381
470P_0402_50V8-J
2 1 EMC_NS@
RG20 0_0603_5%
500mA(Max: 20mA) 2

CG16
.1U_0402_10V6-K

CG17
10U_0603_6.3V6M
@

1
1 1
+3VS +3VS_DMIC DMIC_DATA

1
DMIC_CLK
2 1
R5 0_0603_5% 2 2
2
2

CG3379 2 C1938 C1937

.1U_0402_10V6-K 47P_0402_50V8J 47P_0402_50V8J
CD@ @ @
1
1

CD@
1

Security Classification LC Future Center Secret Data Title

Issued Date 2014/01/11 Deciphered Date 2013/11/08 LCD
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Haydn-S
Date: Wednesday, July 22, 2015 Sheet 26 of 46
5 4 3 2 1
 5 4 3 2 1

TMDS CV255 1 2 .1U_0402_10V6-K HDMI_TX0+_C

DDC ES
4 PCH_HDMI_TX0+
CV256 1 2 .1U_0402_10V6-K HDMI_TX0-_C +3VS +3VS 5V_HDMI_S0
4 PCH_HDMI_TX0-

4 PCH_HDMI_TX1+ CV257 1 2 .1U_0402_10V6-K HDMI_TX1+_C

4 PCH_HDMI_TX1- CV258 1 2 .1U_0402_10V6-K HDMI_TX1-_C

RP9 RP8
4 PCH_HDMI_TX2+ CV259 1 2 .1U_0402_10V6-K HDMI_TX2+_C 2.2K_0404_4P2R_5% 2.2K_0404_4P2R_5% HDMI_CLK+_CON HDMI_TX1+_CON

3
4

3
4
HDMI_CLK-_CON HDMI_TX1-_CON
4 PCH_HDMI_TX2- CV260 1 2 .1U_0402_10V6-K HDMI_TX2-_C
D31 EMC_NS@ D32 EMC_NS@

2
CV262 1 2 .1U_0402_10V6-K HDMI_CLK+_C 1 1 10 9 1 1 10 9

G
4 PCH_HDMI_CLK+

2
1

2
1
4 PCH_HDMI_CLK- CV263 1 2 .1U_0402_10V6-K HDMI_CLK-_C 2 2 9 8 2 2 9 8

1 6 HDMI_DDC_CLK_CON 4 4 7 7 4 4 7 7

S
D 4 PCH_HDMI_DDC_CLK D

D
5 5 6 6 5 5 6 6
Q153A

5
G
2N7002KDWH_SOT363-6 3 3 3 3
1 2
R865 @ 0_0402_5% 8 8
L13 4 3 HDMI_DDC_DAT_CON

S
4 PCH_HDMI_DDC_DAT

D
HDMI_CLK+_C 1 2 HDMI_CLK+_CON
1 2 AZ1045-04F_DFN2510P10E-10-9 AZ1045-04F_DFN2510P10E-10-9
Q153B HDMI_TX0+_CON HDMI_TX2+_CON
HDMI_CLK-_C 4 3 HDMI_CLK-_CON 2N7002KDWH_SOT363-6 HDMI_TX0-_CON HDMI_TX2-_CON
4 3
EMC@ HDMI2012F2SF-900T04_4P

1 2
H-PLUG +3VS

R866 @ 0_0402_5%

2
1 2
R867 @ 0_0402_5% R862
L12 1M_0402_5%
HDMI_TX0+_C 1 2 HDMI_TX0+_CON D34 EMC_NS@
1 2

2
HDMI_HPD_OUT 1 1 10 9 HDMI_HPD_OUT

G
1
HDMI_TX0-_C 4 3 HDMI_TX0-_CON HDMI_DDC_CLK_CON 2 2 9 8 HDMI_DDC_CLK_CON
4 3
EMC@ HDMI2012F2SF-900T04_4P 1 6 HDMI_HPD_OUT HDMI_DDC_DAT_CON 4 4 7 7 HDMI_DDC_DAT_CON

S
4 PCH_HDMI_HPD

2
1 2 5V_HDMI_S0 5 5 6 6 5V_HDMI_S0
R868 @ 0_0402_5% Q155A R885
2N7002KDWH_SOT363-6 20K_0402_5% 3 3
1 2
R869 @ 0_0402_5% 8

1
L14
HDMI_TX1+_C 1 2 HDMI_TX1+_CON
1 2 AZ1045-04F_DFN2510P10E-10-9

HDMI_TX1-_C 4 3 HDMI_TX1-_CON
4 3
C C
EMC@ HDMI2012F2SF-900T04_4P

1 2
CONN
R870 @ 0_0402_5% 5V_HDMI_S0

1 2
R871 @ 0_0402_5%
L15
HDMI_TX2+_C 1 2 HDMI_TX2+_CON
1 2
1A
F1
HDMI_TX2-_C 4 3 HDMI_TX2-_CON 1 3 Q5 1 2

S
4 3 +5VS
AO3401A_SOT23-3 1 CD@
EMC@ HDMI2012F2SF-900T04_4P 0.5A_8V_KMC3S050RY

C261
.1U_0402_10V6-K
G
2
1 2
34 SUSP 2
R872 @ 0_0402_5%

HDMI_CLK+_C R342 1 2470_0402_5%

HDMI_CLK-_C R344 1 2470_0402_5%

MINI HDMI
ME@
CONN
C263 2 1 .1U_0402_10V6-K JHDMI
HDMI_TX0+_C R381 1 2470_0402_5% 5V_HDMI_S0 19 17 HDMI_DDC_CLK_CON
+5V_POWER SCL 18 HDMI_DDC_DAT_CON
HDMI_TX0-_C R382 1 2470_0402_5% SDA
B B
HDMI_TX0+_CON 9
HDMI_TX1+_C R383 1 2470_0402_5% HDMI_TX0-_CON 11 TMDS_DATA0+ 15
HDMI_TX1+_CON 6 TMDS_DATA0- CEC 16
HDMI_TX1-_C R384 1 2470_0402_5% HDMI_TX1-_CON 8 TMDS_DATA1+ DDC/CEC_GROUND 1 HDMI_HPD_OUT
HDMI_TX2+_CON 3 TMDS_DATA1- HOT_PLUG_DETECT
HDMI_TX2+_C R385 1 2470_0402_5% HDMI_TX2-_CON 5 TMDS_DATA2+ 2
TMDS_DATA2- RESERVED#2
HDMI_TX2-_C R389 1 2470_0402_5% 10
7 TMDS_DATA0_SHIELD
4 TMDS_DATA1_SHIELD
TMDS_DATA2_SHIELD
3

D 20
5 Q155B 13 GND0 21
+3VS TMDS_CLOCK_SHIELD GND1
G 2N7002KDWH_SOT363-6 HDMI_CLK+_CON 12 22
HDMI_CLK-_CON 14 TMDS_CLOCK+ GND2 23
S TMDS_CLOCK- GND3
4

ACON_AHRW0-AK1200

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/01/11 Deciphered Date 2013/11/08 HDMI
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Haydn-S
Date: Wednesday, July 22, 2015 Sheet 27 of 46
5 4 3 2 1
 5 4 3 2 1

G-SENSOR
+3VS +3VS

+3VS +3VS
CG24 2 1.1U_0402_10V6-K
UG25
CD@ RPG1 1 12 EC_SMB_CLK3
2.2K_0404_4P2R_5% EC_SMB_DAT3 2 SDO SCx 11
SDx PS

3
4
10
5 CSB
UG16 6 INT1 9
1 8 3 INT2 GND 8
D VCCA VCCB 7 VDDIO GNDIO 4 D

2
1
EC_SMB_CLK3 2 7 MCU_I2C_RE_SCL VDD NC
7,30 EC_SMB_CLK3 A1 B1 MCU_I2C_RE_SCL 26
EC_SMB_DAT3 3 6 MCU_I2C_RE_SDA BMA222E_LGA12_2X2
7,30 EC_SMB_DAT3 A2 B2 MCU_I2C_RE_SDA 26
1 1

CG3380
.1U_0402_10V6-K
CD@

CG3381
.1U_0402_10V6-K
CD@
4 5 +3VS
GND OE

2
RG47 2 2 0416 update
NTSX2102GU8_XQFN8_1P2X1P4
100K_0402_5%

NEW symbol for Haydn 0604

1
+3VS
1
1

EC_SMB_CLK3 1 2 MCU_I2C_RE_SCL
RG911 RG910 R873 @ 0_0402_5%
2.2K_0402_5% 2.2K_0402_5% EC_SMB_DAT3 1 2 MCU_I2C_RE_SDA
R874 @ 0_0402_5%
2
2

EC_SMB_CLK3

EC_SMB_DAT3

When use ISH change RG911/RG910 to 1K

C C

+3VS
+3VS_TPM
1A RTPM11 TPM@ 2 0_0603_5%
1 1
1 CTPM3
CTPM4 CTPM1 .1U_0402_10V6-K
TPM .1U_0402_10V6-K
2
10U_0603_6.3V6M
2
TPM@
B TPM@ TPM@ B
2

+3VS_TPM
UTPM1
1 24
2 NC_1 VDD3 10
3 NC_2 VDD1
7 NC_3 28 RTPM2 1 TPM@ 2 10K_0402_5%
PP LPCPD# 27 SERIRQ_TPM RTPM5 1 TPM@ 2 0_0402_5%
6 SERIRQ 26 1 TPM@ 2 0_0402_5% EC_INT_SERIRQ 6,30
LPC_AD0_TPM RTPM6
NC_4 LAD0 LPC_AD0 6,30
9 23 LPC_AD1_TPM RTPM7 1 TPM@ 2 0_0402_5%
NC_7 LAD1 LPC_AD1 6,30
22 LPC_FRAME#_TPM RTPM8 1 TPM@ 2 0_0402_5%
LFRAME# LPC_FRAME# 6,30
4 20 LPC_AD2_TPM RTPM9 1 TPM@ 2 0_0402_5%
GND_1 LAD2 LPC_AD2 6,30
11 17 LPC_AD3_TPM RTPM10 1 TPM@ 2 0_0402_5%
18 GND_2 LAD3 LPC_AD3 6,30
GND_3 25 +3VS_TPM
5 GND_4 21
NC_5 LCLK CLK_PCI_TPM 6
8 19
12 NC_6 VDD2 15 RTPM4 1 TPM@ 2 0_0402_5%
13 NC_8 CLK_RUN#
14 NC_9 16
NC_10 LRESET# PCH_PLT_RST# 10,18,30,31

Z32H320TC_TSSOP28
TPM@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/01/11 Deciphered Date 2013/11/08 MCU
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Haydn-S
Date: Wednesday, July 22, 2015 Sheet 28 of 46
5 4 3 2 1
 5 4 3 2 1

JIO HDA CARDREADER USB CONN +3VALW +3VS

+5VS +5VALW

2 2 2 2
C204 C194 C201 C202
D D
.1U_0402_10V6-K .1U_0402_10V6-K .1U_0402_10V6-K .1U_0402_10V6-K
@ @ @ @
1 1 1 1

+5VALW HRS_FH52E-40S-0P5SH

40
+5VS 39 40
38 39 42
37 38 GND2 41
+3VALW +3VS 36 37 GND1
35 36
34 35
33 34
DA1 33
7 PCH_HDA_RST# 32
32

RA28 Close to JIO

30 EC_BEEP 3 7 PCH_HDA_BCLK 1 RA28 2PCH_HDA_BCLK_RC 31
CA323 0_0402_5% 30 31
7 PCH_HDA_SYNC 30
1 1 2PC_BEEP_R 29
7 PCH_HDA_SDIN0 29
.1U_0402_10V6-K 7 PCH_HDA_SDOUT 28
2 27 28 PCH_HDA_RST#
7 PCH_BEEP 27
PC_BEEP_R 26
26
2

BAT54CW_SOT323-3 25 PCH_HDA_SYNC
30 EC_MUTE# 25
RA20 24
23 24 PCH_HDA_SDOUT
10K_0402_5% 26 DMIC_DATA 23
22

CA23 EMC_NS@

CA24 EMC_NS@
EMC@
26 DMIC_CLK 22
21 RA27 1 2 PCH_HDA_BCLK_RC
1

20 21 27_0402_5%
30 USB_CHG_EN 20
19

EMC_NS@
RA20 PCH_HDA_SDIN0
8 USB_OC1# 19
Add for Beep Noise on 5/21 18
18

CA25

CA26
17
8 USB20_N3 17
16

68P_0402_50V8J

22P_0402_50V8-J

22P_0402_50V8-J

33P_0402_50V8J

33P_0402_50V8J
CARD READER 8 USB20_P3
15 16
15 1 1 1 1 1

CA22
14

EMC_NS@
8 USB20_N2 14
13
Left USB_CONN 8 USB20_P2 13

EMC@
12
11 12 2 2 2 2 2
8 USB30_TX_P1 11
10
8 USB30_TX_N1 10
C 9 C
8 9
8 USB30_RX_P1
7 8 For EMI
8 USB30_RX_N1 7
6
5 6
30 LID_SW# 5
4
30 LID_PAD# 4
3
30 CHG_MOD1 3
30 CHG_MOD2 2
1 2
30 CHG_MOD3 1
JIO ME@

NEW symbol for Haydn 0609

B B

JDEBUG
ISH_I2C0_SCL 1
7 ISH_I2C0_SCL 1
ISH_I2C0_SDA 2
7 ISH_I2C0_SDA 2
ISH_I2C1_SCL 3
7 ISH_I2C1_SCL 3
ISH_I2C1_SDA 4
7 ISH_I2C1_SDA 4
5
ISH_GP0 6 5
7 ISH_GP0 6
ISH_GP1 7
7 ISH_GP1 7
ISH_GP2 8
7 ISH_GP2 8
ISH_GP3 9
7 ISH_GP3 9
10
11 10
12 11
13 12
14 13
+3VS 15 14
16 15 20
17 16 GND_PAD2 19
18 17 GND_PAD1
18
ELCO_006238018410846+

ME@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/01/11 Deciphered Date 2013/11/08 AUDIO
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Haydn-S
Date: Wednesday, July 22, 2015 Sheet 29 of 46
5 4 3 2 1
 5 4 3 2 1

PWR

+3VALW_EC
+3VALW_EC +3VALW_EC_VCCA
@ RE16 1 2 0_0402_5% CPU_PROCHOT# 4
2 1 2 1 38,44 VR_HOT#
+3VALW
RE1 0_0603_5% 1 1 1 1 1 1 1 RE22 0_0603_5% 1 1

CE15
1U_0402_10V6K

CE11
.1U_0402_10V6-K

CE10
.1U_0402_10V6-K

CE9
.1U_0402_10V6-K

CE8
.1U_0402_10V6-K

CE7
.1U_0402_10V6-K

CE6
.1U_0402_10V6-K

CE3
.1U_0402_10V6-K

CE4
1000P_0402_50V7K

1
D
+3VL 2 1 EC_PROCHOT# 2 QE1
RE5 0_0603_5% @2 2 2 2 2 2 2 2 2 G 2N7002KW_SOT323-3
S

3
2 1
CD@ CD@ RE23 0_0603_5% +3VALW_EC

EC_AGND
8986 EC_USB_ON# 2
RE704
1
10K_0402_5%
D D
LID_PAD# 2 1
+3VS RE196 @ 10K_0402_5%

20MIL
.1U_0402_10V6-K 2 1 CE13
+3VALW_EC +3VALW_EC_VCCA EC_SMB_CLK1 4 1
EC_SMB_DAT1 3 2
2 1 CE1 VCOREVCC RPE680
.1U_0402_10V6-K 20MIL 20MIL 2.2K_0404_4P2R_5%
EC_PWR_LED# 2 1
VCCRTC FBE36 VCCRTC_EC RE682 2.2K_0402_5%
BLM15PX121SN1D_2P EC_BATTCHG_LED# 4 1
1 2 EC_BATTLOW_LED# 3 2
@ RPE683
RE188 1 2 0_0402_5% 2.2K_0404_4P2R_5%

EC_SYSON @ 2 1 DE3 PCH_SLP_S4#

D10
K10
D4
D5
RB751V-40_SOD323-2

K5

K4

E4

E9
VBAT

J4

J5
UE1
for register keep
EC_VR_ON @ 2 1 DE2 PCH_SLP_S3# EC_ON 2 1

VBAT

VCC
VSTBY_05
VFSPI
VSTBY_04
VSTBY_03

VSTBY_02

VSTBY_01

AVCC
VCORE
RB751V-40_SOD323-2 RE712 100K_0402_5%

+3VS

EC_KBRST# H4 EC_I2C_DAT4 2 1
6EC_KBRST# KBRST#/GPB6
EC_INT_SERIRQ G2 M5 EC_PWR_LED# RE721 4.7K_0402_5%
6,28 EC_INT_SERIRQ ALERT#/SERIRQ/GPM6 PWM0/GPA0 EC_PWR_LED# 31
CC1 @ 2 1 CPU_PECI 6,28 LPC_FRAME# H1 N5 EC_BATTCHG_LED# EC_I2C_CLK4 2 1
ECS#/LFRAME#/GPM5 PWM1/GPA1 EC_BATTCHG_LED# 31
47P_0402_50V8J H2 M6 EC_BATTLOW_LED# RE722 4.7K_0402_5%
6,28 LPC_AD3 EIO3/LAD3/GPM3 PWM2/GPA2 EC_BATTLOW_LED# 31
J1 N6 EC_VOL_UP#
6,28 LPC_AD2 EIO2/LAD2/GPM2 PWM3/GPA3 EC_VOL_UP# 32
J2 PWM K6 EC_FAN_PWM1 LPC_FRAME# 2 @ 1
6,28 LPC_AD1 EIO1/LAD1/GPM1 PWM4/SMCLK5/GPA4 EC_FAN_PWM1 32
K1 J6 EC_FAN_PWM RE711 10K_0402_5%
6,28 LPC_AD0 EIO0/LAD0/GPM0 PWM5/SMDAT5/GPA5 EC_FAN_PWM 32
6 PCH_PCI_CLK PCH_PCI_CLK K2 LPC M7 EC_KBLED_PWREN 2 @ 1
ESCK/LPCCLK/GPM4 PWM6/SSCK/GPA6 EC_BEEP 29
WRST# L1 K7 EC_VR_ON RE693 10K_0402_5%
WRST# PWM7/RIG1#/GPA7 EC_VR_ON 44
L2 C2 EC_VOL_DOWN# RPE3
10 EC_VCCST_PWRGD ECSMI#/GPD4 TMRI0/GPC4 EC_VOL_DOWN# 32
EC_RX M2 E1 EC_SUSP# EC_TP_CLK 2 3
31 EC_RX SIN0/PWUREQ#/BBO/SMCLK2ALT/GPC7 TMRI1/GPC6 EC_SUSP# 34,40
M1 EC_TP_DATA 1 4
31 EC_TX SOUT0/LPCPD#/GPE6
EMC@ 2 1 PCH_PCI_CLK 10,18,28,31 PCH_PLT_RST# RE217 1 2 0_0402_5% M4 G10 RE714 1 2 0_0402_5%
ERST#/LPCRST#/GPD2 ADC0/GPI0 CPU_VR_READY 44
RE254 33_0402_5% EC_SCI# N4 G13 EC_VOL_UP# 2 10K_0404_4P2R_5%
1
4,7 EC_SCI# ECSCI#/GPD3 ADC1/SMINT0/GPI1 NTC_V 38
2 LID_PAD# F1 G12 BATT_TEMP RE184 10K_0402_5%
29 LID_PAD# GA20/GPB5 ADC2/SMINT1/GPI2 BATT_TEMP 38
ADC F9 RE717 1 2 0_0402_5% EC_VOL_DOWN# 2 1
ADC3/SMINT2/GPI3 BAT_I 38
CE339 F13 RE185 10K_0402_5%
ADC4/SMINT3/GPI4 EC_KBLED_PWREN 31
18P_0402_50V8J F10 RE13 1 2 0_0402_5% EC_MUTE# 2 @ 1
1 EMC@ ADC5/DCD1#/GPI5 VR_ADP_I 38
F12 RE179 10K_0402_5%
ADC6/DSR1#/GPI6 CHG_MOD2 29
J12 E13 EC_ROTATION_LOCK#2 1
31 KSI0 KSI0/STB# ADC7/CTS1#/GPI7 USB_ID_N 38
J13 RE187 10K_0402_5%

C
31
31
31
31
KSI1
KSI2
KSI3
KSI4
J9
H12
H9
KSI1/AFD#
KSI2/INIT#
KSI3/SLIN#
KSI4
IT8396 DAC
DAC2/TACH0B/SMINT6/GPJ2
DAC3/TACH1B/SMINT7/GPJ3
DAC4/DCD0#/GPJ4
D12
C13
B13
RE216 1
RE718 1
2 0_0402_5%
2 0_0402_5%
EC_PROCHOT#
EC_VCCIO_EN
EC_SENSOR_INT
12
7
EC_FAN_PWM 1
RPE225
4 @
C

+3VALW_EC H10 C12 PCH_BKLT_EN 4,26 EC_FAN_PWM1 2 3

31 KSI5 KSI5 DAC5/RIG0#/GPJ5
H13
31 KSI6 KSI6
G9 A11 EC_RTCRST_ON 10K_0404_4P2R_5%
31 KSI7 KSI7 PS2CLK0/TMB0/CEC/GPF0
M8 B11 EC_RX 2 @ 1
31 KSO0 KSO0/PD0 PS2DAT0/TMB1/GPF1 EC_PBTN_OUT# 10
1
RE220
100K_0402_5%

J7 A10 RE11 1 2 0_0402_5% RE207 10K_0402_5%

31 KSO1 KSO1/PD1 SMCLK0/SMINT8/GPF2 EC_SMB_CLK0 6,18,32
1

N9 PS2 B10 RE12 1 2 0_0402_5% GPU Thermal PCH

31 KSO2 KSO2/PD2 SMDAT0/SMINT9/GPF3 EC_SMB_DAT0 6,18,32
DE23 M9 Int. K/B D9 EC_TP_CLK RPE224
RB751V-40_SOD323-2
31 KSO3
K8 KSO3/PD3 PS2CLK2/SMINT10/GPF4 B9 EC_TP_DATA
EC_TP_CLK 32 Sensor EC_FAN_SPEED1 1 4
31 KSO4
J8 KSO4/PD4 Matrix PS2DAT2/SMINT11/GPF5 EC_TP_DATA 32
EC_FAN_SPEED 2 3
@ 31 KSO5
2

N10 KSO5/PD5 A9
31 KSO6 EC_CAPS_LED# 31
2

M10 KSO6/PD6 GPH3/ID3/YM B8 10K_0404_4P2R_5%

31 KSO7 KSO7/PD7 GPH4/ID4/YP USB_CHG_EN 29
WRST# N11 EXTERNAL SERIAL FLASH A8 WIN8_BUTTON#
WRST# 18 31 KSO8 KSO8/ACK# GPH5/ID5/DM WIN8_BUTTON# 26
K9 B7 CHG_MOD1 EC_SCI# 2 1
31 KSO9 KSO9/BUSY GPH6/ID6/DP CHG_MOD1 29
1 N12 RE206 10K_0402_5%
31 KSO10 KSO10/PE
CE20
1U_0402_10V6K

N13 A7 EC_SPI_CS0# RE204 1 2 MIRROR@ 0_0402_5% RPE200

31 KSO11 KSO11/ERR# FSCE#/GPG3 SPI_CS0# 6
M13 B6 EC_SPI_SI RE205 1 2 MIRROR@ 0_0402_5% EC_INT_SERIRQ 1 4
31 KSO12 KSO12/SLCT FMOSI/GPG4 SPI_SI 6
L12 SPI Flash ROM A6 EC_SPI_SO RE208 1 2 MIRROR@ 0_0402_5% SPI_SO 6 EC_KBRST# 2 3
2 31 KSO13 KSO13 FMISO/GPG5
L13 B5 EC_SPI_CLK RE212 1 2 MIRROR@ 0_0402_5%
31 KSO14 KSO14 FSCK/GPG7 SPI_CLK 6
K12 10K_0404_4P2R_5%
31 KSO15 KSO15
32 EC_ROTATION_LOCK# K13
J10 KSO16/SMOSI/GPC3 A4 EC_ACIN# CPU_VR_READY 2 1
26 EC_LID_OUT# KSO17/SMISO/GPC5 AC_IN#/GPB0
UART A3 LID_SW# LID_SW# 29 RE720 10K_0402_5%
+3VL +3VALW_EC LID_SW#/GPB1 EC_SENSOR_INT 2 1
RE10 @ 10K_0402_5%
32 EC_ONOFF_BTN# EC_ONOFF_BTN# B4 A13 EC_SYS_PWROK EC_SYS_PWROK 10
RE713 1 @ 2 0_0402_5% A2 PWRSW/GPB3 EGAD/GPE1 A12
39 EC_ON XLP_OUT/GPB4 SM Bus EGCS#/GPE2 EC_PCH_ACIN 10
1

1
RE221
100K_0402_5%

RE223
100K_0402_5%
MIRROR@

BATT charger EC_SMB_CLK1 B3 B12 DCIN_USB_EN EC_RSMRST#_R 2 1

38 EC_SMB_CLK1 SMCLK1/GPC1 EGCLK/GPE3 DCIN_USB_EN 38
@ EC_SMB_DAT1 B2 RE7 10K_0402_5%
38 EC_SMB_DAT1 SMDAT1/GPC2
1 2 CPU_PECI B1 EC_SYS_PWROK 2 1
4 CPU_PECI_R SMCLK2/PECI/GPF6
RC12 43_0402_5% C1 D13 RE219 1 2 0_0402_5% EC_ON RE181 10K_0402_5%
10 EC_PCH_PWROK SMDAT2/PECIRQT#/GPF7 SMINT5/GPJ1
EC_SMB_CLK3_R E8 E7 GPG2 EC_SYSON 2 1
2

EC_SMB_DAT3_R D7 CRX1/SIN1/SMCLK3/GPH1/ID1 SSCE0#/GPG2 E6 CHG_MOD3 RE3 10K_0402_5%

Sensor CTX1/SOUT1/SMDAT3/GPH2/ID2 GPIO SSCE1#/GPG0 CHG_MOD3 29
D6
DSR0#/GPG6 PCH_ME_PROTECT 7
GPG2 20MIL A5 EC_SYSON RPE2
BTN#/GPG1 EC_SYSON 34,40
+3VL RE202 1 2 0_0402_5% D1 EC_SUSP# 1 4
CRX0/GPC0 EC_BKLT_EN 26
A1 D2 EC_ON_5V EC_PCH_PWROK 2 3
VSTBY0 CTX0/TMA0/GPB2 EC_ON_5V 39
EC_MUTE# E2 WAKE UP N1
29 EC_MUTE# GPE4 RI1#/GPD0 PCH_SLP_S3# 10,12
1
RE222
100K_0402_5%
UNMIRROR@

N3 10K_0404_4P2R_5%
RI2#/GPD1 PCH_SLP_S4# 10
E12 EC_NOVO_BTN#_R
TACH2/SMINT4/GPJ0 M12 EC_FAN_SPEED1 EC_VCCST_EN 2 @ 1
26,33,38 EC_USB_ON# TACH1A/TMA1/GPD7 EC_FAN_SPEED1 32
EC_USB_ON# N7 M11 EC_FAN_SPEED RE14 10K_0402_5%
PCH_PWR_EN N8 GINT/CTS0#/GPD5 TACH0A/GPD6 M3 EC_I2C_DAT4 EC_FAN_SPEED 32 EC_VCCIO_EN 2 @ 1
34,41,42 PCH_PWR_EN GPIO EC_I2C_DAT4 7
2

RE218 1 2 EC_RSMRST#_R D8 RTS1#/GPE5 L80LLAT/SMDAT4/GPE7 N2 EC_I2C_CLK4 RE716 10K_0402_5%

10 EC_RSMRST# CLKRUN#/GPH0/ID0 L80HLAT/BAO/SMCLK4/GPE0 EC_I2C_CLK4 7
0_0402_5%

GPG2 EC_X1 G1
EC_VCCST_EN RE715 1 2 0_0402_5% EC_X2 F2 VCORE2
*H MIRROR CODE EN 12 EC_VCCST_EN CK32K/GPJ6
B B
L MIRROR CODE DISABLE Clock
1

RE182 BATT_TEMP 1 2
EC_X1 CE17 100P_0402_50V8J
VSS_01

VSS_02

VSS_03

VSS_04

VSS_05

VSS_06

10K_0402_5%
AVSS

@ EMC_NS@
2 1 EC_X2
2

RE8 @ 10M_0402_5%
1

IT8396VG-192-AX_VFBGA128
E5

H5

F4

F5

G4

G5

E10

RE707
RTC_RST# 9
0_0402_5%

1
QE3 D
YE1 EC_RTCRST_ON 2
2

EC_X1_R 1 2 @ G

1
2 32.768KHZ_12.5PF_200458-PG14 2 EC_AGND 2N7002KW_SOT323-3 S

3
RE50
CE21 CE22 100K_0402_5%
.1U_0402_10V6-K 18P_0402_50V8J
1 @ 1 EC_SMB_CLK3_R RE709 1 ECSH@ 2 0_0402_5%
EC_SMB_CLK3 7,28

2
EC_SMB_DAT3_R RE710 1 ECSH@ 2 0_0402_5%
EC_SMB_DAT3 7,28

CRYSTAL
1,Space 15MIL
2,No trace under crystal

EC DSW Signal
+3VALW_EC +3VL +3VALW_EC

+3VL
2

+3VL +3VALW_EC RE31 @ RE32

2
RE586
100K_0402_5%

0_0402_5% 0_0402_5%
@
1

KSI7 @1 TP131 TP136 1@

1

KSI6 @1 TP132 TP137 1@ @ RE183 EC_ONOFF_BTN# 2 1

RE262 WRST# @1 TP133 TP138 1@ RE197 100K_0402_5% RE186 10K_0402_5%
1

EC_ACIN# 2 1 EC_SMB_CLK1 @1 TP134 100K_0402_5% LID_SW# 2 @ 1

EC_SMB_DAT1 @1 TP135 DE40 RE189 10K_0402_5%
2

0_0402_5% 2 EC_NOVO_BTN#_R
0604
1
32 EC_NOVO_BTN#
For off-line programming烧录EC code
3 EC_ONOFF_BTN#
1

QE15 D KSI-6 (pin-H13 --> I2C_DATA) 1

CE5
.1U_0402_10V6-K

2N7002KW_SOT323-3 2 2 1 VR_ACIN 38 KSI-7 (pin-G9 --> I2C_CLK)

G RE203 BAT54CW_SOT323-3
1K_0402_5%
SMDAT0/GPF3(pin-B10)
A S @ @
SMCLK0/GPF2(pin-A10) 2 A
3

Security Classification LC Future Center Secret Data Title

Issued Date 2014/01/11 Deciphered Date 2013/11/08 ECIT8396
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Haydn-S
Date: Wednesday, July 22, 2015 Sheet 30 of 46
5 4 3 2 1
 5 4 3 2 1

WIFI&BT Board Connector

+3VS_WLAN

Mini Card(WLAN/WiMAX) +3VS

C79
.1U_0402_10V6-K
1

Need short
+3VS_WLAN JWLAN ME@ 2
J2 @

1
+3VS 1 2 1 2
1 2 R113 1 2 0_0402_5% USB20_P4_R 3 GND1 3.3VAUX1 4 R3003 R3004
8 USB20_P4 USB_D+ 3.3VAUX2
JUMP_43X79 8 USB20_N4 R114 1 2 0_0402_5% USB20_N4_R 5 6 @ 1 TP52 49.9K_0402_1% 49.9K_0402_1%
7 USB_D- LED#1 8
9 GND2 PCM_CLK 10

2
11 SDIO_CLK PCM_SYNC 12
13 SDIO_CMD PCM_IN 14
15 SDIO_DAT0
SDIO_DAT1
PCM_OUT
LED#2
16 @ 1 TP61 KB BL

22U_0603_6.3V6-M
17 18
SDIO_DAT2 GND11

C78
1 1 19 20
D C53 21 SDIO_DAT3 UART_WAKE 22 UART_RX_DEBUG_R R256 1 2 0_0402_5% D
SDIO_WAKE UART_RX UART_RX_DEBUG 7
.1U_0402_10V6-K 23
SDIO_RESET
2 2
+5VS +5VS_LED
KEY E Q24
25 PIN24~PIN31 NC PIN 24 LP2301ALT1G_SOT23-3
27 26 +5VS

D
29 28 3 1
31 30

C205 CD@
.1U_0402_10V6-K
33 32 UART_TX_DEBUG_R R3002 1 2 0_0402_5% ID=2.8A

G
UART_TX_DEBUG 7

2
GND3 UART_TX

2
35 34 1
8 PCIE_PTX_C_DRX_P6 PETP0 UART_CTS
37 36 R254
8 PCIE_PTX_C_DRX_N6 PETN0 UART_RTS
39 38 EC_TX_RSVD R65 1 @ 2 0_0402_5% EC_TX_R 10K_0402_5%
41 GND4 CLink_RESET 40 EC_RX_RSVD R66 1 @ 2 0_0402_5% BT_CTRL#
8 PCIE_PRX_DTX_P6 PERP0 CLink_DATA 2
43 42
8 PCIE_PRX_DTX_N6

1
45 PERN0 CLink_CLK 44 R109 1 2 0_0402_5%
47 GND5 COEX3 46
9 CLK_PCIE_WLAN REFCLKP0 COEX2

1
49 48 D
9 CLK_PCIE_WLAN# REFCLKN0 COEX1

C213
.1U_0402_10V6-K
R126 51 50 R125 1 2 0_0402_5% 2
GND6 SUSCLK SUSCLK 9 30 EC_KBLED_PWREN
9 WLAN_CLKREQ# WLAN_CLKREQ# 1 2 0_0402_5% WLAN_CLKREQ#_R 53 52 R121 1 2 0_0402_5% G 1
CLKEQ0# PERSTO# PCH_PLT_RST# 10,18,28,30

2
10 PCIE_WAKE# R120 1 @ 2 0_0402_5% WLAN_PCIE_WAKE# 55 54 BT_CTRL#
57 PEWAKE0# RSRVD/W_DISABLE#2 56 WL_OFF# R261 Q20 S @

3
GND7 W_DISABLE#1 100K_0402_5% 2N7002KW_SOT323-3
2
59 58 @ 1 TP68

1
61 RSRVD/PETP1 I2C_DATA 60 @ 1 TP82
63 RSRVD/PETN1 I2C_CLK 62 @ 1 TP111
65 GND8 NFC_I2C_IRQ(MGPIO5) 64 EC_TX_R
67 RSRVD/PERP1 NFC_Reset#(MGPIO7) 66
69 RERVD/PERN1 RSRVD7 68 +3VS_WLAN
71 GND9 RSRVD8 70
73 RSRVD1 RSRVD12 72
75 RSRVD2 3.3VAUX3 74
GND10 3.3VAUX4

C203 CD@
.1U_0402_10V6-K
77 76 1
GND15 GND14

+3VS_WLAN
DEREN_40-42313-06742RHFL 2 +5VS_LED

JKBBL ME@

2
1 5
RC2525 2 1 GND1
10K_0402_5%
NEW symbol for Haydn 0609 3 2
@ 4 3 6
4 GND2

1
C WLAN_PCIE_WAKE# ACES_51524-0040N-001 C

NEW symbol for Haydn 0530

BT_CTRL# R105 1 2 1K_0402_5% EC_TX_R R187 1 2 100_0402_1% EC_TX

PCH_BT_OFF# 7 EC_TX 30
WL_OFF# 1 2 DEBUG@
PCH_WLAN_OFF# 7
R110 0_0402_5% BT_CTRL# R188 1 2 100_0402_1% EC_RX
WLAN&BT Combo module circuits DEBUG@
EC_RX 30

BT on module BT on module

1
Enable Disable R191
100K_0402_5%
DEBUG@
* BT_CRTL H L

2
PCH_BT_ON# L H

Keyboard Connector
2

D4007
2

AZ5123-01F.R7G_DFN1006P2X2
ACES_50519-02601-001
EMC_NS@
28 26 KSI1
G2 26 KSI1 30
1

27 25 KSI7
G1 25 KSI7 30
24 KSI6
KSI6 30
1

LED300 R3000 24 23 KSO9

23 KSO9 30
EC_PWR_LED# 1 2 1 2 +3VALW 22 KSI4
30 EC_PWR_LED# 22 KSI4 30
2 21 KSI5
21 KSI5 30
100_0402_5% 20 KSO0
KSO0 30
3

C1942 12-21C-T3D-CP1Q2B12Y-2C_WHITE 20 19 KSI2

19 KSI2 30
220P_0402_50V7K 18 KSI3
1 18 KSI3 30
17 KSO5
17 KSO5 30
16 KSO1
16 KSO1 30
15 KSI0
15 KSI0 30
B 14 KSO2 B
14 KSO2 30
13 KSO4
LED301 13 KSO4 30
12 KSO7
12 KSO7 30
11 KSO8
11 KSO8 30
EC_BATTLOW_LED# 3 10 KSO6
30 EC_BATTLOW_LED# R3001 10 KSO6 30
9 KSO3
9 KSO3 30
1 1 2 +3VALW 8 KSO12
8 KSO12 30
7 KSO13
7 KSO13 30
EC_BATTCHG_LED# 2 6 KSO14
30 EC_BATTCHG_LED# 150_0402_5% 6 KSO14 30
2

5 KSO11
5 KSO11 30
D4008 4 KSO10
2

4 KSO10 30
12-22-S2ST3D-C30-2C_WHI-ORG AZ5123-01F.R7G_DFN1006P2X2 3 KSO15
3 KSO15 30
2 2 2 +3VALW_CAPLED R101 1 2 100_0402_5%
2 +3VS
EMC_NS@ 1 R102 1 @ 2 100_0402_5%
1 +3VALW
C1943 C1948
EC_CAPS_LED# 30
1

220P_0402_50V7K
220P_0402_50V7K JKB ME@
1 1
1

2
D13
D4006
2

2
AZ5725-01F_DFN1006P2X2

AZ5123-01F.R7G_DFN1006P2X2

EMC@ EMC_NS@
1

1
1

EC_PWR_LED#

EC_BATTCHG_LED# +3VALW_CAPLED C117 1 2 EMC_NS@ 100P_0402_50V8J EC_CAPS_LED# C133 1 2 EMC_NS@ 100P_0402_50V8J

EC_BATTLOW_LED# KSO2 C89 1 2 EMC_NS@ 100P_0402_50V8J KSO1 C90 1 2 EMC_NS@ 100P_0402_50V8J

KSO15 C92 1 2 EMC_NS@ 100P_0402_50V8J KSO7 C93 1 2 EMC_NS@ 100P_0402_50V8J

KSO6 C94 1 2 EMC_NS@ 100P_0402_50V8J KSI2 C95 1 2 EMC_NS@ 100P_0402_50V8J

EMC_NS@ EMC_NS@ EMC_NS@
KSO8 C96 1 2 EMC_NS@ 100P_0402_50V8J KSO5 C97 1 2 EMC_NS@ 100P_0402_50V8J
2

D4 D5 D6
KSO13 C98 1 2 EMC_NS@ 100P_0402_50V8J KSI3 C99 1 2 EMC_NS@ 100P_0402_50V8J
2

2
AZ5725-01F_DFN1006P2X2

AZ5725-01F_DFN1006P2X2

AZ5725-01F_DFN1006P2X2

KSO12 C100 1 2 EMC_NS@ 100P_0402_50V8J KSO14 C109 1 2 EMC_NS@ 100P_0402_50V8J

KSO11 C119 1 2 EMC_NS@ 100P_0402_50V8J KSI7 C110 1 2 EMC_NS@ 100P_0402_50V8J

1

A KSO10 C107 1 2 EMC_NS@ 100P_0402_50V8J KSI6 C122 1 2 EMC_NS@ 100P_0402_50V8J A

1

KSO3 C116 1 2 EMC_NS@ 100P_0402_50V8J KSI5 C108 1 2 EMC_NS@ 100P_0402_50V8J

KSO4 C115 1 2 EMC_NS@ 100P_0402_50V8J KSI4 C123 1 2 EMC_NS@ 100P_0402_50V8J

KSI0 C121 1 2 EMC_NS@ 100P_0402_50V8J KSO9 C111 1 2 EMC_NS@ 100P_0402_50V8J

KSO0 C124 1 2 EMC_NS@ 100P_0402_50V8J KSI1 C120 1 2 EMC_NS@ 100P_0402_50V8J

Reserve
For EMC

Security Classification LC Future Center Secret Data Title

Issued Date 2014/01/11 Deciphered Date 2013/11/08 CONN(WLAN&KB&PWRB&UART)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS D 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Haydn-S
Date: Wednesday, July 22, 2015 Sheet 31 of 46
5 4 3 2 1
 5 4 3 2 1

THERMAL SENSOR AND FAN

NOVO button
Rotation button SW4003
SW4000 30 EC_NOVO_BTN# EC_NOVO_BTN# 1 4
EC_ROTATION_LOCK# 1 4 1 4
30 EC_ROTATION_LOCK# 1 4

TESTPAD 1 2 3
TP43 2 3
TESTPAD 1 2 3
TP41 2 3
EVQP7L01K_4P
+5VS EVQP7L01K_4P C1940 1 2 220P_0402_50V7K
C1934 1 2 220P_0402_50V7K
JFANC ME@ D4004
1A R223 1 5 D4000 1 2
1 2 2 1 GND1 1 2 1 2
3 2 1 2 EMC_NS@
D 1 1 3 D
0_0603_5% 4 6 EMC_NS@
C986 C175 4 GND2 ON/OFF button AZ5725-01F_DFN1006P2X2

2
10U_0603_6.3V6M
2
.1U_0402_10V6-K Vol up/down button AZ5725-01F_DFN1006P2X2
SW4004
@ ACES_50208-00408-001 SW4001 EC_ONOFF_BTN# 1 4
30 EC_ONOFF_BTN# 1 4
EC_VOL_UP# 1 4
30 EC_VOL_UP# 1 4
0530 New symbol
30 EC_FAN_SPEED 0530 New symbol
30 EC_FAN_PWM TESTPAD TP39 1 2 3
1 2 3 2 3
TESTPAD TP37 2 3
EVQP7L01K_4P
EVQP7L01K_4P C1939 1 2 220P_0402_50V7K
C1935 1 2 220P_0402_50V7K
D4003
D4001 1 2
1 2 1 2
1 2 EMC_NS@
EMC_NS@ AZ5725-01F_DFN1006P2X2
Vol up/down button AZ5725-01F_DFN1006P2X2
+5VS SW4002
30 EC_VOL_DOWN# EC_VOL_DOWN# 1 4
JFANS ME@ 1 4
1A R224 1 5 0530 New symbol
1 2 2 1 GND1
3 2 1 2 3
1 1 3 TESTPAD TP38 2 3
0_0603_5% 4 6
C987 C176 4 GND2
10U_0603_6.3V6M .1U_0402_10V6-K EVQP7L01K_4P
2 2 @ ACES_50208-00408-001 C1936 1 2 220P_0402_50V7K

30 EC_FAN_SPEED1 D4002
1 2
30 EC_FAN_PWM1 1 2
EMC_NS@
AZ5725-01F_DFN1006P2X2
C C

Touch Pad Connector

+3VS
+3VS_TP

Nuvoton thermal sensor

2
+3VS
R222
Address 1001_100xb 0_0402_5% PM_SMB_CLK
PM_SMB_DAT
10mA U35 EMC_NS@ EMC_NS@ EMC_NS@

1
1 8 EC_SMB_CLK0 ACES_50505-00641-001 D3 D11 D12
VDD SCL EC_SMB_CLK0 6,18,30

2
+3VS_TP 6 8
5 6 G2 7
C1933
1U_0402_10V6K

C179
.1U_0402_10V6-K

C181
.1U_0402_10V6-K

AZ5725-01F_DFN1006P2X2

AZ5725-01F_DFN1006P2X2

AZ5725-01F_DFN1006P2X2
1 1 REMOTE+_R 2 7 EC_SMB_DAT0 1 1

2
D+ SDA EC_SMB_DAT0 6,18,30 30 EC_TP_CLK
4 5 G1
C1020
4.7U_0402_6.3V6M
30 EC_TP_DATA
REMOTE-_R 3 6 THM_ALERT# 3 4
D- ALERT# PM_SMB_CLK 2 3
6,16 PM_SMB_CLK
@2 2 THM_SHDN# 4 5 2 2 PM_SMB_DAT 1 2
T_CRIT# GND 6,16 PM_SMB_DAT 1

1
NCT7718W_MSOP8 ME@

1
JTP

B B

+3VS

THM_ALERT# R625 1 2 10K_0402_5%

@

THM_SHDN# R624 1 2 10K_0402_5%

@

Close to memory side Close to GPU&VRAM

REMOTE1+ REMOTE2+
1 1
1

C C
C982 2 Q137 C983 2 Q138
100P_0402_50V8J B MMST3904-7-F_SOT323-3 100P_0402_50V8J B MMST3904-7-F_SOT323-3
2 @ E 2 @ E
3

REMOTE1- REMOTE2-

UMA@ OPT@

REMOTE1+/-:
Trace width/space:10/10 mil
Trace length:<8"

UMA@
Close U35 REMOTE1+ R176 1 2 0_0402_5%
A A
REMOTE+_R REMOTE2+ R175 1 OPT@ 2 0_0402_5% REMOTE+_R
1
REMOTE2- R178 1 OPT@ 2 0_0402_5% REMOTE-_R
C451
2200P_0402_50V7K REMOTE1- R177 1 2 0_0402_5%
2 REMOTE-_R
UMA@

Security Classification LC Future Center Secret Data Title

Issued Date 2014/01/11 Deciphered Date 2013/11/08 CONN(THM&FAN&RTN&SPKR&TP)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Haydn-S
Date: Wednesday, July 22, 2015 Sheet 32 of 46
5 4 3 2 1
 5 4 3 2 1

USB30 USB30_TX_N2_CON
L68 USB30_TX_P2_CON
USB20_N1 1 2 USB20_N1_CON USB20_N1_CON
1 2 D33 EMC_NS@
R876,R877 COLAY WITH L68 USB20_P1_CON 1 1 10 9 +5VALW +5V_USB30
USB20_P1 4 3 USB20_P1_CON
4 3 2 2 +5VALW +5V_USB30
9 8

2
EXC24CH900U_4P 1 U8 1 1
EMC@ D9 D10 4 4 7 7 5 1

2
C184 IN OUT C187 C15
AZ5425-01F_DFN1006P2E2 AZ5425-01F_DFN1006P2E2
EMC_NS@ 5 5 6 6 .1U_0402_10V6-K 2 .1U_0402_10V6-K 100U_1206_6.3V6M
EMC_NS@ 2 GND 2 2
EMC@ 3 3 EC_USB_ON# 4 3
EXC24CH900U_4P 26,30,38 EC_USB_ON# EN FLG USB_OC0# 8

1
USB30_TX_R_N2 4 3 USB30_TX_N2_CON 8 AP22802BW5-7_SOT25-5

1
D 4 3 D
Low Active 2A
R880,R881 COLAY WITH L69
USB30_TX_R_P2 1 2 USB30_TX_P2_CON AZ1045-04F_DFN2510P10E-10-9 Change to SA000079400 G517F2T11U
1 2 USB30_RX_N2_CON
L69 USB30_RX_P2_CON

EMC@
EXC24CH900U_4P
USB30_RX_N2 4 3 USB30_RX_N2_CON Left USB3.0/2.0
4 3
R878,R879 COLAY WITH L70
USB30_RX_P2 1 2 USB30_RX_P2_CON
1 2 +5V_USB30
L70
JUSB30 ME@

2
C185 1 2USB30_TX_R_P2 R880 1 @ 2 0_0402_5% USB30_TX_P2_CON 9
8 USB30_TX_P2 SSTX+
.1U_0402_10V6-K 1 D4005

2
+5V_USB30 VBUS
C186 1 2USB30_TX_R_N2 R881 1 @ 2 0_0402_5% USB30_TX_N2_CON 8 10 AZ5725-01F_DFN1006P2X2
8 USB30_TX_N2 SSTX- GND_PAD1
.1U_0402_10V6-K USB20_N1 R876 1 2 0_0402_5% USB20_N1_CON 2 11 EMC_NS@
8 USB20_N1 D- GND_PAD2
@ 4 12
USB20_P1 R877 1 @ 2 0_0402_5% USB20_P1_CON 3 GND GND_PAD3 13
8 USB20_P1 D+ GND_PAD4

1
USB30_RX_P2 R878 1 2 0_0402_5% USB30_RX_P2_CON 6
8 USB30_RX_P2 SSRX+
@ 7

1
USB30_RX_N2 R879 1 2 0_0402_5% USB30_RX_N2_CON 5 GND_D
8 USB30_RX_N2 SSRX-
@

DEREN_40-42039-00901RHF-L
NEW symbol for Haydn 0604

C C

MSATA (Full Card) JSATA ME@

1
0.01U_0402_25V7K 1 2 C1946 SATA_PTX_C_DRX_P0 2 1
8 SATA_PTX_DRX_P0 2
0.01U_0402_25V7K 1 2 C1945 SATA_PTX_C_DRX_N0 3 11
8 SATA_PTX_DRX_N0 3 GND1
4
0.01U_0402_25V7K 1 2 C1947 SATA_PRX_C_DTX_N0 5 4
8 SATA_PRX_DTX_N0 5
0.01U_0402_25V7K 1 2 C1949 SATA_PRX_C_DTX_P0 6
8 SATA_PRX_DTX_P0 6
7 12
8 7 GND2
+5VS_MSATA 2A 8
9
10 9
10

ELCO_006809610010846

New Symbol
B B

R891 2A
1 2
+5VS +5VS_MSATA
0_0603_5%
C1955
22U_0603_6.3V6-M

1 1 1
C1956
4.7U_0402_6.3V6M
@

C1950
.1U_0402_10V6-K
2 2 2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/01/11 Deciphered Date 2013/11/08 CONN(MSATA&USB30&USB20)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Haydn-S
Date: Wednesday, July 22, 2015 Sheet 33 of 46
5 4 3 2 1
 5 4 3 2 1

+1.35V +1.35V_CPU
+3VALW +5VALW +5VLP
PJ13 Enable:
VIH=1.2V~5.5V
1 VIL=0~0.4V

1
PJ_43x79_6
C112 +3VS R231 R234
1 1U_0402_10V6K U56 100K_0402_5% 100K_0402_5%
@ 2 1 14 1 @
C214 2 VIN1_1 VOUT1_2 13 C216

2
.1U_0402_10V6-K VIN1_2 VOUT1_1 .1U_0402_10V6-K
2 1 2 @ EC_SUSP# R264 1 2 0_0402_5% 3 12 3VS_CT1 SUSP
EN1 SS1 2 SUSP 27
R16 0_0603_5%
@ 4 11
D BIAS GND D

1
R265 1 2 0_0402_5% 5 10 5VS_CT2 +5VS D
+5VALW EN2 SS2 Q16 2 EC_SUSP#
EC_SUSP# 30,40

0.01U_0402_25V7K
C114 @
1 6 9 1 2N7002KW_SOT323-3 G
7 VIN2_1 VOUT2_2 8 C215
VIN2_2 VOUT2_1 .1U_0402_10V6-K S
1

3
15
2 C113 GPAD 2
1U_0402_10V6K APL3523AQBI-TRG_TDFN14_2X3
+5VALW +5VALW +5VS +3VS +5VS 2

0522 new symbol for haydn .

Change to G5016KD1U
1 1
+5VALW +5VLP
C1957 C1958
.1U_0402_10V6-K .1U_0402_10V6-K C226 1 2 EMC_NS@ C1960 1 2 EMC_NS@ 3VS_CT1 5VS_CT2
2 2

1000P_0402_50V7K

1000P_0402_50V7K
EMC_NS@ EMC_NS@ .1U_0402_10V6-K .1U_0402_10V6-K

1
C1959 1 2 EMC_NS@ C1961 1 2 EMC_NS@ 1 1

C101

C102

@
.1U_0402_10V6-K .1U_0402_10V6-K R230 @ R236
100K_0402_5% 100K_0402_5%
REV@
+3VALW +1.0VALW +3VALW +3VS 2 2

2
SYSON#

1
D
C1965 1 2 EMC_NS@ C1962 1 2 EMC_NS@ Q19 2
G EC_SYSON 30,40
.1U_0402_10V6-K .1U_0402_10V6-K 2N7002KW_SOT323-3
C1964 1 2 EMC_NS@ C1963 1 2 EMC_NS@ REV@
.1U_0402_10V6-K .1U_0402_10V6-K S

3
C C

For High speed signal cross moat concern.

+3VALW +3VALW_PCH

2 1
R13 0_0603_5%

22U_0603_6.3V6-M
+5VALW
1 1

C1103
@
Q23 C219
LP2301ALT1G_SOT23-3 .1U_0402_10V6-K
1

2 2
@

D
R155 3 1
10K_0402_5%

.1U_0402_10V6-K
@

C37

C30
0.01U_0402_25V7K
@ @

G
1 1
2

2
PCH_PWR_EN#
@
2 2
1

Q30 D
30,41,42 PCH_PWR_EN PCH_PWR_EN 2
G
PCH_PWR_EN# 2 R11 1
@ S 2N7002KW_SOT323-3 0_0402_5%
3
1

B @ 1 B

C441
.1U_0402_10V6-K
@
1
R162
100K_0402_5% R238
2
470K_0402_5%
2

@
@

+5VS +3VS +0.68VS +1.35V

2

@ R257 @ R245 @ R248 @ R246

22_0402_5% 22_0402_5% 22_0402_5% 22_0402_5%
1

SUSP 1 2
R118 0_0402_5%
REV@
6

D D Q148 D Q156 D
2 Q146A 5 Q146B 2 SYSON# 1 2 2
G 2N7002KDWH_SOT363-6 G 2N7002KDWH_SOT363-6 G R117 0_0402_5% G
REV@
S S S 2N7002KW_SOT323-3 S 2N7002KW_SOT323-3
1

A A
REV@ REV@ REV@ REV@

Security Classification LC Future Center Secret Data Title

Issued Date 2014/01/11 Deciphered Date 2013/11/08 POWER SWITCH
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Haydn-S
Date: Wednesday, July 22, 2015 Sheet 34 of 46
5 4 3 2 1
 5 4 3 2 1

FD1 FD2 FD3 FD4 FD5 FD6

D 0801 DFB需求新增 D
1

1
PAD_CT6P0B7P0D3P6 PAD_CT6P0
H1 H12 H14 H15 H16 H2 H4 H5
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
1

1
PAD_CT6P0B7P0D3P6 PAD_CT6P0B7P0D3P6 PAD_CT6P0B7P0D3P6 PAD_CT6P0B7P0D3P6 PAD_CT6P0B7P0D3P6 PAD_CT6P0 PAD_CT6P0 PAD_CT6P0

PAD_C7P0D4P3 PAD_RT4P0X2P0 PAD_C7P0D5P6

H18 H19
H3 H6 H10 HOLEA HOLEA H11
HOLEA HOLEA HOLEA HOLEA

1
1

1
PAD_C7P0D4P3 PAD_C7P0D4P3 PAD_C7P0D4P3 PAD_C7P0D5P6
PAD_RT4P0X2P0 PAD_RT4P0X2P0

PAD_C7P0D2P3 PAD_CT7P0ShapeB7P0X8P25D2P3
H7 H9 H13 H17
C HOLEA HOLEA HOLEA HOLEA C
1

PAD_C7P0D2P3 PAD_C7P0D2P3 PAD_C7P0D2P3 PAD_CT7P0ShapeB7P0X8P25D2P3

PAD_ShapeT6P0X5P5 PAD_O2P7X2P2D2P7X2P2N
PAD_C2P2D2P2N SH1 ME@ SH2 ME@ SH3 ME@

H20 H21 1 1 1
HOLEA HOLEA H22 1 1 1
HOLEA

SPRING_FINGER_6.2X1.64 SPRING_FINGER_6.2X1.64 SPRING_FINGER_6.2X1.64

1

PAD_ShapeT6P0X5P5 PAD_O2P7X2P2D2P7X2P2N
PAD_C2P2D2P2N

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/01/11 Deciphered Date 2013/11/08 Screw and Hole
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Haydn-S
Date: Wednesday, July 22, 2015 Sheet 35 of 46
5 4 3 2 1
 5 4 3 2 1

SDV
1/19:
1.Firstly initial

1/21:
1.PCH ISH reserve sensor solution

1/22:
1.U8 USB power switch change to AP22802BW5-7_SOT25-5
from AP2820CMMTR-G1_MSOP8

1/28:
D 1.EC change to IT8986 from IT8386 D

2/4
1.EC_ON change to GPJ1
2.GPU 1.05VGS source change to +1.0VALW
3.BAT_I change to GPI3
4.CPU_VR_READY change to GPI0
5.EC_VR_ON change to GPA7
6.EC_VCCIO_EN change to GPJ2
7.VGA_AC_DET change to GPJ3
8.VGA 1.05VGS HW load switch del

2/9
1.Add VDDQ_PGOOD to EC GPJ3

2/10
1.RC138,QC6,RC136 change to unmount
2.RC1599 change to mount
3.U9 change to AP22802AW5-7_SOT25-5 from AP2821KTR-G1_SOT23-5

2/11 **
1.Add SH1/SH2/SH3 shielding
2.RC1585 unmount,RC1586 mount

2/12
1.Del C224/C225/C217/C218/C226/C220
2.RC157/RC170 change to unmount
3.Del PR138,Add PR1015/PR1016
C 4.Del PD109/PD110 Add PD111 C
5.Add PR1017

2/13
1.Del TP203/TP172/TP173/TP177/TP178
2.Del UC8/RC1591/DC2/CC1247/JC2/CC1248
3.Del UC7/RC1590/DC3/CC1245/RC1592/CC1246
4.QC12/QC16 change to AO5804EL_SC89-6 from 2N7002KDWH_SOT363-6
5.QC13/QC14 change to DMG1012T-7_SOT523-3 from 2N7002KW_SOT323-3

2/24
1.JDDRL.181 change to DDRA_DQ56 from DDRA_DQ61
2.JDDRL.180 change to DDRA_DQ61 from DDRA_DQ56
3.JDDRL.191 change to DDRA_DQ62 from DDRA_DQ59
4.JDDRL.192 chnage to DDRA_DQ58 from DDRA_DQ62
5.JDDRL.194 change to DDRA_DQ59 from DDRA_DQ58
6.RC59 change to @

2/25
1.Add JDEBUG connector for Intel ISH debug
2.VRAM Hynix change to H5TC4G63CFR-N0C
3.VRAM Samsung change to K4W4G1646E-BC1A
4.CC165 change to @
5.CC57 change to 1uf from 0.1uf and mount
6.U56 VIN1/VIN2,VOUT1/VOUT2 swap

2/28
B 1.Del TP197,TP198,TP200,TP40,TP141,TP44,TP189,TP191,TP196, B
TP183,TP185,TP184,TP181,TP194,TP187,TP182,TP188,TP193,TP190,TP192,TP201,TP195,TP186,TP236

3/2 *****
1.Del RC1596,RC1597,Add RPC68
2.Change RPC4 to 10K_0404_4P2R_5% from 10K_0804_8P4R_5%
3.Change UV2 to 74LVC1G08SE-7_SOT353-5 from 74LVC1G08GW_SOT353-1-5

3/3
1.JDEBUG change to ELCO_006238018410846+
2.Reserve RE720 for CPU_VR_READY pull high +3VS
3.UTPM1 change to Z32H320TC_TSSOP28 from ST33ZP24AR28PVSP_TSSOP28
4.RTPM2 change to 10K from 4.7K
5.Del RE214/RE215/RE708,Del RE690/RE691@
6.Add RE721/RE722 10K pull high +3VS
7.Del VDDQ_PGOOD Add EC_SENSOR_INT
8.WIN8_BUTTON# change to EC PIN A8, CHG_MOD1 change to EC PIN B7
9.Add EC_I2C_DAT4 to EC PIN M3, Add EC_I2C_CLK4 to EC PIN N2
10.Add RPC69/RC2533/RC2534/QC45

3/4
1.RE10 pin2 change to EC_SENSOR_INT from EC_ON_5V
2.Update JDEBUG symbol
3.Reserve CC1255, C1957/C1958/C226/C1959/C1960/C1961/C1962/C1963/C1964/C1965 for EMC

3/5
1.Del TP90/TP92
A A

3/9
1.Add RC2535 0ohm, Add RC2536 1K to GND

3/10
1.H17 change to PAD_CT7P0ShapeB7P0X8P25D2P3 from PAD_C7P0D2P3
Security Classification LC Future Center Secret Data Title
3/11 Issued Date 2014/01/11 Deciphered Date 2013/11/08 HW_Change_List
1.RC64 change to @ from ES@
2.CC23 change to @ THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Haydn-S
Date: Wednesday, July 22, 2015 Sheet 36 of 46
5 4 3 2 1
 5 4 3 2 1

+5VLP/ 100mA
Silergy
D
SY8286CRAC +5VALW/6A D
Converter
EN FOR SYSTEM PGOOD
PAGE 39

Silergy +3VLP/ 100mA

AC Adapter
SY8286BRAC +3VALW
ANPEC
20V/40W/65W Converter +3VALW/ 4A
+1.8VALW/200mA
FOR SYSTEM APL5325BI-TRG
EN PGOOD EN
PAGE 39 LDO
PAGE 42

Silergy
+1.35V/10A
NB685GQ-Z
Converter
+0.68V/1A
FOR DDR3L
EN PGOOD
TI PAGE 40
C C

BQ24770RUYR
B+
Battery Charger Silergy
Switch Mode SY8288RAC +1.0VALW/8A
IO Board / Page38 Converter
EN FOR CPU/PCH PGOOD
PAGE 41

SMBus
Onsemi CPU_CORE / 21A
NCP81206MNTXG
Switch Mode +VCCSAE / 4A
FOR CPU IMVP7
EN
Battery PAGE 44 +VCC_GT / 18A
Li-ion PGOOD

B
2S2P /46WH B
Onsemi
NCP81272MNTWG +VGA_CORE/31A
VIDs
Switch Mode
EN FOR GPU VDDC PGOOD
PAGE 43

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/01/11 Deciphered Date 2013/11/08 PWR_BLOCK DIAGRAM
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Haydn-SKL
Date: Wednesday, July 22, 2015 Sheet 37 of 46
5 4 3 2 1
 5 4 3 2 1

V_PATH

PQ101 PL105 EMC_NS@

1/27: Please double-side mount PC103,PC104,PC105,PC106 to avoid EE noise.
ADIN_1 AON6414AL_DFN8-5 PQ102 2.2UH_SPV-YT12N2R2N-O1_2A_30%
AON7408L_DFN8-5 1 2 V_CHG

1 3 PR101
2 2 PJ101
5 3 1 5 V_CHG_J 2 1 2 1
2 1
JUMP_43X79 0.01_1206_1%

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
1

1
3/4: 需平均分布在B+的shape上，请EMC指定摆放位置。

PC103

PC104

PC105

PC106
@

1
PC135 PC148

2200P_0402_50V7K
PC134 0.01U_0402_25V7K 0.1U_0402_25V6 1/28: Move RTC schematic to power portion.

2
2

1
PC101 1000P_0402_50V7K EMC@ EMC@

4.7_0402_5%

715_ACP
PC102
EMC@ @
B+

PR141
0.1U_0402_25V6 @

2
EMC request

1
AGATE_R EMC request +3VL VCCRTC
PD111
1

D
PR103 待调 2
D

0.1U_0402_25V7-K

0.1U_0402_25V7-K

0.1U_0402_25V7-K

0.1U_0402_25V7-K

0.1U_0402_25V7-K

0.1U_0402_25V7-K

0.1U_0402_25V7-K

0.1U_0402_25V7-K
1
RTC_VCC_R

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@
430K_0402_1% 1 1 PR1015 2
PR1017

1U_0402_6.3V6K

.1U_0402_10V6-K
PC140

PC141

PC142

PC143

PC144

PC145

PC146

PC147
PR102 0.1U_0402_25V6 1.5K_0402_5%
1 2 3 2
PC107
2

1
PC138

PC139
4.02K_0402_1%

2
V_PATH 1 2 0_0402_5% PR1016
2

ACDET BAT54CW_SOT323-3 45.3K_0402_1%

2
1
@

2
BATT+
PD101
1

AGATE
PR104 1 2

4.02K_0402_1%

0.1U_0402_25V6
2

1
68K_0402_1%

PC108

1
RTC_VCC

PR106

CHG_VCC_R
PC109 RB751V-40_SOD323-2 RTC_VCC_R
2

2
0.1U_0402_25V6 1/27: Please double-side mount PC111,PC112,PC113,PC114 to avoid EE noise.

2
ADIN_1
PR105 PD102

1
B+
CHRG_GND CHRG_GND CHRG_GND 1 2 1 2
1/28: Change PC111,PC112,PC113,PC114 from SE00000QK00 10U 25V 0805 H0.85 to SE000011I00 10U 16V 0805 H0.85 . PJ103
30 VR_ADP_I
1 2
1 2

VR_ACIN
10_0805_1%

CMSRC
ACDET
PC110 RB751V-40_SOD323-2
100P_0402_50V8J JUMP_43X39

5
PQ103 @

47U_B2_10V_R70M
CHG_VCC

AON6552_DFN8-5
1

PC115
CHRG_GND

10U_0805_16V6-K

10U_0805_16V6-K

10U_0805_16V6-K

10U_0805_16V6-K
1

1
+3VL +

PC111

PC112

PC113

PC114
PC118 4

ACN
IADP

ACOK
ACDET

ACDRV

CMSRC

ACP
30 BAT_I

2
1U_0603_25V6M 2

2
2

PC116 100P_0402_50V8J
PR107 CHRG_GND 2 1 8
IBAT VCC
28 @ @ BATT+
100K_0402_5%
CHG_DH_R

3
2
1
PC117 100P_0402_50V8J
2 1 9 27 PQ104
CHRG_GND
1

VR_ACIN PMON PHASE AO4407AL_SO8 PF101 BATT+_2

30 VR_ACIN PR109

2
PC119 PR110 1 8 12A_24V_F1206HB12V024T/M JBATT1
10 26 CHG_DH 1 2 PL101 2 7 PJ102
8A 1
44 Psys PROCHOT# HIDRV 1
0.047U_0402_25V7K CHG_PAHSE 1 2 2 1 3 6 2 1 BATT+_F 1 2 2

1
PR111 0_0402_5% 2.2UH_PCMB063T-2R2MS_8A_20% 5 2 1 EC_SMCA 3 2 9
11 25 1
CHG_BTST 2CHG_BTST_R 0.01_1206_1% JUMP_43X79 EC_SMDA 4 3 GND1 10
SDA BTST 4 GND2

1
PU101 PQ105 @ 5 11

4
5 GND3

1
0_0402_5% PC120 6 12

AON6414AL_DFN8-5
RTC_VCC 6 GND4

1
PR108 1 2 0_0402_5% CHG_VR_HOT# 12 BQ24770RUYR_QFN28_4X4 24 REG_CHG 1 2 10U_0805_25V6K PC137 PC121 7
30,44 VR_HOT# CHRG_GND

2
SCL REGN PC127 8 7
0.1U_0402_25V6

2
8

1000P_0402_50V7K
1U_0402_10V6K EMC_NS@

2
EC_SMB_DAT1 PR138 1 2 0_0402_5% EC_SMB_DAT1_R 13 23 CHG_DL4
CMPIN LODRV SUYIN_125022HB008M200ZL
EMC request
BGATE_R ME@
PR114
EC_SMB_CLK1 PR139 1 2 0_0402_5% EC_SMB_CLK1_R 14 22
C CMPOUT GND BGATE 1 2 C

3
2
1
BATPRES#

1
29 EMC@

100_0402_1%
BATDRV#
POWERPAD

PR116
PC122 0_0402_5%

100_0402_1%
PR115
PC124 PC123

CELL

SRN

SRP
BAT

ILIM

1
0.1U_0402_25V6 0.1U_0402_25V6

2
CHRG_GND 1 2 PC125

2
1000P_0402_50V7K
MBAT_PRES#_R 15

16

17

18

19

20

21

2
CHRG_GND 0.1U_0402_25V6 CHRG_GND @

PR118

BGATE
CHG_ILIM 1 2 REG_CHG
BAT

30 EC_SMB_CLK1

1
PR119 300K_0402_1%
47K_0402_1%
PR120
30 EC_SMB_DAT1

MBAT_PRES#_R
1 2
BATT+_2
10_0603_5% CHRG_GND
+3VL
1

PC126 715_SRN

1
0.1U_0402_25V6
2

PR121
100K_0402_5%
R_0402
CHRG_GND
PR122

2
J101
1 2 1 2
30 BATT_TEMP
JUMPER 0_0402_5%

CHRG_GND

+5VALW
VUSB
PL102
HCB2012KF-121T50_0805 2A 0609 220UF change to B2 SIZE
1 2 1

100U_1206_6.3V6M

100U_1206_6.3V6M
EMC@
ADIN C118
AC adapter 20V PL103 .1U_0402_10V6-K
1 1 1
2

C103

C104
B PF102 HCB2012KF-121T50_0805 EMC@ C105 B
1 2 ADIN_F 1 2 ADIN_3 .1U_0402_10V6-K
2 2 2 EMC@
F1206HI7000V024TM EMC@ @
1

2.2_0805_5%
1
ME@ U101
2

PR124
BELLW_80188-2321 PR123 PC129 5 1
PR126 470K_0402_5% PC128 @ IN OUT
1 0_0402_5% 0.1U_0402_25V6 0.1U_0402_25V6 2
2

9 1 2 USB20_N7_CON 1 2 @ EMC@ EMC@ GND

USB20_N7 8
8 GND4 2 3 USB20_P7_CON 1 2 2 EC_USB_ON# 4 3
GND3 3 USB20_P7 8 26,30,33 EC_USB_ON# EN FLG
7 4 USB_ID @
GND2 4 10U_0805_25V6K
1
PC130

6 5 PR125 G517F2T11U_SOT25-5
GND1 5 0_0402_5% @
AZ5123-01F.R7G_DFN1006P2X2

AZ5425-01F_DFN1006P2E2

AZ5425-01F_DFN1006P2E2

2
1

PR127
PJP1
1

1
PD106

USB_OC3#_R 1 2
USB_OC3# 8
PD104

PD105

0_0402_5%
2

2
2

ADIN_1
PQ106 PQ107
EMC@ EMC_NS@ EMC_NS@ SI4483ADY-T1-GE3_SO8 AO4407AL_SO8 PQ108 VUSB
8 1 1 8 AO4407AL_SO8
7 2 ADIN_2 2 7 1 8
6 3 3 6 2 7
5 5 3 6
+3VL +3VALW
1

0.47U_0402_25V6K
PC131

100K_0402_5%
4

4
1

1
0.1U_0402_25V6
2

4
1

1
PR142

PC132
PR128 PR129
200K_0402_1% 470K_0402_5% PD109 PR130 PR131
+3VALW DFLZ5V6-7_POWERDI123-2 13.7K_0402_1% 13.7K_0402_1%

2
@
2

2
3
+3VALW ADIN_GATE

2
LTA044EUBFS8TL_UMT3F-3
VUSB_GATE NTC_V_R

1
2
1

PR134
1

1
PR133 200K_0402_5%

1
200K_0402_1%

PQ111
PR132 PH101
200K_0402_1% PD107 PR135

2
RB751V-40_SOD323-2 100K_0402_5% 100K_0402_1%_TSM0B104F4251RZ
2

PR136
2

2
1 2 USB_OPEN 0_0402_5%

2
A
USB_ID_N 30 A
EXC24CH900U_4P USB_OPEN_N

1
USB20_N7 4 3 USB20_N7_CON USB_OPEN_D
4 3 PD108
3

6
D PQ109A D D D RB751V-40_SOD323-2
USB20_P7 1 2 USB20_P7_CON 5 USB_ID 2 USB_ID 5 2 USB_OPEN 2 1
1 2 G G G G DCIN_USB_EN 30
PQ110B
PL104 EMC@ PQ109B 2N7002KDWH_SOT363-6
1

30
S 2N7002KDWH_SOT363-6 S S S PQ110A

NTC_V
4

1
1

2N7002KDWH_SOT363-6 PR137 PC133 2N7002KDWH_SOT363-6 PR143

200K_0402_5% 100K_0402_5%
0.1U_0402_25V6
2
2

2
Security Classification LC Future Center Secret Data Title

Issued Date 2014/01/11 Deciphered Date 2013/11/08 PWR_NVDC Charger

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS D 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Haydn-SKL
Date: Wednesday, July 22, 2015 Sheet 38 of 46

5 4 3 2 1
 5 4 3 2 1

1/27: Please double-side mount PC203,PC204 to avoid EE noise.

B+ 1/28: Change PC203,PC204 from SE00000QK00 10U 25V 0805 H0.85 to SE000011I00 10U 16V 0805 H0.85 .
@
PJ201 1.5A PU201
2 1 +3V_VIN 5 9 +3V_PWRGD
2 1 4 IN1 PG 1 +3VBS 1 2

10U_0805_16V6-K

10U_0805_16V6-K
0.1U_0402_25V6
3 IN2 BS

1M_0402_5%
PC201
+3VALW

SY8286BRAC_QFN20_3X3
2 IN3

PC202

PC203

PC204

PR201
JUMP_43X79 0.1U_0603_25V7-M
IN4 6 @ 4A

2
EMC@ 7 LX1 19 PL201 PJ202
8 GND1 LX2 20 +3VLX 1 2 +3VALW_P 2 1

2
18 GND2 LX3 2 1

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
2.2UH_PCMB063T-2R2MS_8A_20%
21 GND3
GND4

1
JUMP_43X79

PC205

PC206

PC207

PC208
2 1 +3VALW_EN 12 14 +3VALW_P PR204
D 30 EC_ON +3V_VIN 11 EN1 OUT 2.2_0805_5% D

2
0_0402_5% EN2 13 +3VALW_FB EMC_NS@
PR203 10 FF

2
15 NC1
16 NC2 17
100mA +3VLP

0.1U_0402_25V6
NC3 LDO

1
1M_0402_5%
1

1
PC209
PC211

4.7U_0603_6.3V6K
1
PR206
@ 1200P_0402_50V7-K

2
PC210
EMC_NS@

2
2
PC213
PR209
1 2 1 2

1000P_0402_50V7K 1K_0402_1%
+3VL
+3VLP @
PJ203
2 1
2 1

JUMP_43X39

C C

+3VALW

1/27: Please double-side mount PC214,PC215 to avoid EE noise.

2
1/28: Change PC214,PC215 from SE00000QK00 10U 25V 0805 H0.85 to SE000011I00 10U 16V 0805 H0.85. PR217
100K_0402_5%
2/4: Reserve +3/5V_PWRGD circuit. @
PR215

1
+3V_PWRGD 2 1
0_0402_5%
@
B+
@
PJ204 1.5A PU202 PR216
2 1 +5V_VIN 5 9 +5V_PWRGD 2 1
220U_D_10VM_R25M

2 1 4 IN1 PG 1 +5VBS 1 2 +5VALW

10U_0805_25V6-K

10U_0805_16V6-K

10U_0805_16V6-K

0_0402_5%
0.1U_0402_25V6

1 IN2 BS
1

3 PC217 @

SY8286CRAC_QFN20_3X3
+ IN3
PC218

PC219

PC214

PC215

PC216

JUMP_43X79 2 0.1U_0603_25V7-M
IN4 6 @ 6A
2

EMC@ 7 LX1 19 PL202 PJ205

2 8 GND1 LX2 20 +5VLX 1 2 +5VALW_P 2 1
18 GND2 LX3 2 1

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
@ PR218
@ 21 GND3 10_0402_5% 1.5UH_PCMB063T-1R5MS_10A_20%
GND4

1
PR210 14 +5VALW_OUT 1 2+5VALW_P JUMP_43X79
OUT

PC220

PC221

PC222

PC223

PC224

PC225
EC_ON 2 1 +5VALW_EN 12 PR211
0_0402_5% +5V_VIN 11 EN1 13 +5VALW_FB 2.2_0805_5%

2
@ EN2 FF EMC_NS@
15
100mA +5VLP

2
10 LDO
16 NC1 17 +5VVCC
0.1U_0402_25V6

NC2 VCC

1
1M_0402_5%

PR212 1 2 0_0402_5%

4.7U_0603_6.3V6K
1

30 EC_ON_5V
PC226

1U_0603_25V6M
PC228

1
PR213

PC227
@ 1200P_0402_50V7-K

2
B B

PC229
EMC_NS@
2

2
2

PC230
PR214
1 2 1 2

1000P_0402_50V7K 1K_0402_1%

3VALWP 5VALWP
VFB=2V TDC 5A
TDC 5A
Fsw=350KHZ Fsw=300KHZ
OCP:7.8A~9.5A OCP:7.8A~9.5A
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/02/20 Deciphered Date 2014/02/20 PWR_3VALWP/5VALWP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Haydn-SKL
Date: Wednesday, July 22, 2015 Sheet 39 of 46

5 4 3 2 1
 5 4 3 2 1

1/27: Please double-side mount PC302,PC303 to avoid EE noise.

1/28: Change PC302,PC303 from SE00000QK00 10U 25V 0805 H0.85 to SE000011I00 10U 16V 0805 H0.85 .
B+ @ 2A
PJ301
2 1 1.35V_B+
2 1

10U_0805_16V6-K

10U_0805_16V6-K
0.1U_0402_25V6
1

1
PC301

PC302

PC303
JUMP_43X79
0.1U_0603_25V7-M

2
0_0603_5%
@ PU301 PR302 PC304
1 10 BST_1.35V 1 2 2 1 0.68UH_PCMB063T-R68MN_16A_20% @
VIN BST PL301 PJ302
D PR301 D
9 LX_1.35V 1 2 1.35V_P 2 1
5 CPU_DRAMPG_CNTL 1 2 S3_1.35V 16 SW 2 1
+1.35V

NB685GQ-Z_QFN16_3X3
EN1

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
PR303 JUMP_43X118
0_0402_5% 30,34 EC_SYSON 1 2 S5_1.35V 15 13 1.35V_FB @ 220P_0402_50V7K
EN2 FB

1
PC306

PC309

PC307

PC308
2.2_0805_5%
2 1 2 1

EMC_NS@
PR304
1A DIS ------10A

PR305
2 1 0_0402_5% 1M_0402_5% @ PC305

2
30,34 EC_SUSP# 0_0402_5% 2 @ 1 VDDQ_PGOOD 12 6 1.35V_P PR306

2
@ PC311 PR307 100K_0402_1% PG VDDQ +0.68VSP

1
PC312 @ 0.1U_0402_10V7K DDR_3V3 3

2
3V3

1
499_0402_1%
1U_0603_25V6M
5

41.2K_0402_1%
0.1U_0402_10V7K

1.35V_SN
VTT

PR308

PR310
@

2
@
1200P_0402_50V7-K
4.7_0402_5%
4
AGND

PR309

PC313
8
VTTS

1
2

EMC_NS@
2

2
PGND

PC314
7 VTTREF

22U_0603_6.3V6-M
+3VALW VTTREF

1
1

PC315
Mode 14 11
MODE OTW#

1U_0402_6.3V6K
2
1.35V_FB PJ304

2
1

PC316
1.35V_GND PR311 2 1
+0.68VSP 2 1 +0.68VS
0_0402_5%

1
2
PR312 JUMP_43X79

1
33K_0402_1% @

1.35V_GND

2
1.35V_GND

1.35V_GND

C C
PJ305
1 2

JUMPER
@

1.35V_GND

B B

A
+1.35VP A

Vout=1.367V
Iocp min=13A fro DIS SKU
Iocp min=6A fro UMA SKU

Security Classification LC Future Center Secret Data Title

Issued Date 2014/01/11 Deciphered Date 2013/11/08 PWR_1.35V/0.68VS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Haydn-SKL
Date: Wednesday, July 22, 2015 Sheet 40 of 46
5 4 3 2 1
 5 4 3 2 1

Fsw=800KHZ
Vfb=0.6V
1/27: Please double-side mount PC402,PC403 to avoid EE noise. Vout=1.051V
1/28: Change PC402,PC403 from SE00000QK00 10U 25V 0805
H0.85 to SE000011I00 10U 16V 0805 H0.85 .
+3VALW OCP:12A

1
PR409
100K_0402_5%
R_0402
B+ @ PR410
PJ401 0_0402_5%

2
JUMP_43X39 PU203 PC404 @
D D
2 1 B+_1.0V 5 9 2
0.1U_0603_25V7K 1
2 1 4 IN1 PG 1 1.0VP_BS 1 2

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6
3 IN2 BS

1
PC401

PC403

PC402

SY8288RAC_QFN20_3X3
2 IN3 +1.0VALW
IN4 6
PL401 8A

2
7 LX1 19 PJ402
@ 8 GND1 LX2 20 1.0VP_LX 1 2 1.0V_P 2 1
18 GND2 LX3 2 1

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
21 GND3 1UH_PCMB063T-1R0MS_12A_20% JUMP_43X118
EMC@ GND4

1
14 @
FB

PC406

PC407

PC408

PC409

PC410

PC411
PR404
+3VALW 1 2 PR401 +1.0VALW_ILNT 13 12 PR405

2
100K_0402_5% @ 1 2 1.0V_EN 11 ILMT NC3 10 2.2_0805_5%
30,34,42 PCH_PWR_EN EN NC1

680P_0402_50V7K 1K_0402_1%
16 EMC_NS@
0_0402_5% 15 NC2
+3VALW

2
BYP
1

PR407
17 1.0VLDO
VCC

2
PR406

0.1U_0402_25V6
1M_0402_5% PR403 PR408

4.7U_0603_6.3V6K

2
1

1
1M_0402_5%

@ PC405
@

4.7U_0603_6.3V6K
20K_0402_1%

PC412
@
2

1
PC413
2

1
PC414

1
1000P_0402_50V9-J

PC415
2
EMC_NS@

2
1.0VP_FB

680P 1K

2
PR411
29.4K_0402_1%

1
C C

+3VS
2

PR412
10K_0402_5%
@
+1.05VSP_VGA +1.05VGS
1

PU402
2A
PJ403 PL402 PJ404
+3VALW 2 1 1.05VMP_VIN 4 3 1.05VMP_LX 1 2 2 1
2 1 IN LX 1UH_PH041H-1R0MS_3.8A_20% 2 1
5 2
22U_0805_6.3V6M

22U_0805_6.3V6M

JUMP_43X39 OPT@ JUMP_43X39

PG GND
1

1
OPT@ OPT@
PC416

PC417

6 1 PR413
FB EN

OPT@
2.2_0805_5%
2

68P_0402_50V8J
EMC_NS@
SY8032ABC_SOT23-6

1
75K_0402_1%

22U_0805_6.3V6M

22U_0805_6.3V6M
2

1
OPT@
OPT@ FB=0.6Volt

PR414

PC418

PC419

PC421
1
OPT@ OPT@

2
PC420

2
2 1000P_0402_50V9-J
EMC_NS@
B B

PR415
2 1 1.05VGS_EN 1.05VMP_FB
21,43 EN_VGA
0_0402_5% OPT@ OPT@

1
@
1

PR417
1

PR416 PC422 100K_0402_1%

PR418 0_0402_5% 1M_0402_5% 0.22U_0402_10V6K OPT@
1 2 @
22,43 DGPU_PWROK
2

2
2

OPT@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/01/11 Deciphered Date 2013/11/08 PWR_1.0VALW/1.05VGS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Haydn-SKL
Date: Wednesday, July 22, 2015 Sheet 41 of 46
5 4 3 2 1
 5 4 3 2 1

+1.8VALW_L
+1.8VALW
D D

PJ501 PU501 PJ502

200mA 200mA
2 1 +1.8VALW_VIN 3 4 2 1
+3VALW 2 1 VIN VOUT 2 1
2

22U_0805_6.3V6M
JUMP_43X39 GND JUMP_43X39

1
5 +1.8VALW_FB @
SET

PC503
@ PC501 1 PC502 @
4.7U_0603_6.3V6K SHDN PR501 220P_0402_50V7K

2
30K_0402_1%
APL5325BI-TRG_SOT23-5

2
1
2 1 EN_+1.8VALW
30,34,41 PCH_PWR_EN
PR503

.1U_0402_10V6-K
0_0402_5% 23.7K_0402_1%

PC504
PR502

2
2
@

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/01/11 Deciphered Date 2013/11/08 PWR_+1.8VALW
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Haydn-SKL
Date: Wednesday, July 22, 2015 Sheet 42 of 46
5 4 3 2 1
 5 4 3 2 1

+3VGS
1/27: Please double-side mount PC603,PC604 to avoid EE noise.

2
PR601
1/28: Change PC603,PC604 from SE00000QK00 10U 25V 0805 H0.85 to SE000011I00 10U 16V 0805 H0.85 .
10K_0402_5% 2/9: Change PC601,PC602 from PCME063T-R24MS1R145 to PCMB063T-R22MS for common material use.
@ PD601
RB751V-40_SOD323-2

1
OPT@
2 1 1 2 EN_VGA +VGA_B+
18,20 3VGS_PWR_EN EN_VGA 21,41

1
0_0402_5% PC601 PJ601
PR602 PR603 .1U_0402_10V6-K 2 1 B+
100K_0402_5% 2 1 OPT@ 2 1

2
@
PR604 JUMP_43X79

2
10K_0402_1%

10U_0805_25V6K

10U_0805_25V6K
0.1U_0603_25V7K
OPT@ @

1
D D

PC603

PC604
PC602
18 NVVDD_PWM_VID NVVDD_PWM_VID

NVVDD_PWM_VID

AON6372_DFN8-5

2
18 PSI_VGA PSI_VGA

VSSSENSE_VGA 4
19 VSSSENSE_VGA ICCMAX=51A

PQ601
19 VCCSENSE_VGA VCCSENSE_VGA OPT@ OPT@ ICCTDC=26A
PR605 PC605 OPT@
0_0603_5% 0.22U_0603_16V7K OCP=64A

3
2
1
22,41 DGPU_PWROK DGPU_PWROK 2 1BOOT1_2_VGA 1 2 PR606 OPT@
OPT@ 0_0402_5%
2 1 UGATE1_2_VGA PL601 +VGA_CORE
0.22UH_PCMB063T-R22MS_23A_20%
1 2

BOOT1_VGA
OPT@

5
10P_0402_50V8J
1

1
AON6764_DFN8-5
PC606
PR607

330U_B2_2VM_R15M

330U_B2_2VM_R15M
2.2_0805_5% 1 1

2
LGATE1_VGA 4 @

PQ602

PC607

PC608
+ +

1SNUB1_VGA 2
OPT@
2 2

3
2
1
EN_VGA
UGATE1_VGA OPT@

PSI_VGA
PC609
2700P_0402_50V7-K
OPT@

PHASE1_VGA
1 2 PU601 PC610
OPT@ 1000P_0402_50V9-J OPT@ OPT@

21

2
5

1
@

VID

PSI

EN

HG1

BST1

PAD
PR610 PR609 PC611
20K_0402_1% 20K_0402_1% 4.7U_0603_6.3V6K
VREF_VGA 2 1 2 1VIDBUF 6 20
OPT@ OPT@ VIDBUF PH1 1 2 OPT@
C C

1
7 19
PR611 REFIN LG1 PR612
PR613 PR614 2K_0402_1% 2.2_0603_5%
0_0402_5% 18K_0402_1% OPT@ 8 18 PVCC_VGA 2 1 +5VS 1/27: Please double-side mount PC615,PC616 to avoid EE noise.
OPT@ OPT@ VREF NCP81272MNTXG_QFN20_3X3PVCC

2
2 1 2 1 OPT@ 1/28: Change PC615,PC616 from SE00000QK00 10U 25V 0805
9 17
FS LG2 H0.85 to SE000011I00 10U 16V 0805 H0.85 .
PC612 1 2 OPT@ REFIN_VGA

COMP/ILMT
PC613 10 16 +VGA_B+
FBRTN PH2

PGOOD
0.01U_0603_50V7K 2700P_0402_50V7-K
PR615 OPT@1 2 VREF_VGA

BST2
HG2
100_0402_5%

FB
2 1 PR616
OPT@ 2 1 OPT@ FS

11

12

13

14

15

10U_0805_25V6K

10U_0805_25V6K
0.1U_0603_25V7K
39K_0402_1%

1
PC615

PC616
PC614
PR617

AON6372_DFN8-5
0_0402_5% BOOT2_VGA

2
VSSSENSE_VGA OPT@2 1 VSS_SEN
UGATE2_VGA 4

PQ603
FB_VGA
1

PC617 PC618 OPT@ OPT@

1000P_0402_50V7K 47P_0402_50V8J PR620 PC619 PR619 PC620 OPT@

3
2
1
OPT@ 1 2FB1_VGA 1 2 1 2 COMP_VGA 0_0603_5% 0.22U_0603_16V7K OPT@
2

PR621 51_0402_1% OPT@ 10P_0402_50V8J PR624 2 1 BOOT2_2_VGA 1 2

0_0402_5% OPT@ PR622 OPT@ PC621 10K_0402_5% OPT@ PL602 +VGA_CORE
VCCSENSE_VGA 2 1 VCC_SEN 1 2 1 2FB2_VGA1 PR623 2 2 1 +3VS 0.22UH_PCMB063T-R22MS_23A_20%

1
OPT@ @ PHASE2_VGA 1 2
10K_0402_1% 100P_0402_50V8J 82K_0402_1%OPT@ PR608 OPT@

5
OPT@ 75K_0402_1%
PR625 OPT@ DGPU_PWROK

1
100_0402_5%

AON6764_DFN8-5
2
1 2 PR626
+VGA_CORE

330U_B2_2VM_R15M
OPT@ 2.2_0805_5% 1
B B
LGATE2_VGA 4 @

PQ604

PC622
+

1SNUB2_VGA 2
2

3
2
1
OPT@

PC623 OPT@
1000P_0402_50V9-J

2
@

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
1

1
PC624

PC625

PC626

PC627

PC628
2

2
@ @ @
OPT@ OPT@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/01/11 Deciphered Date 2013/08/05 PWR-VGA_CORE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Haydn-SKL
Date: Wednesday, July 22, 2015 Sheet 43 of 46
5 4 3 2 1
 5 4 3 2 1

+VCCST_CPU
+5VS +5VS B+

1
PR701 PR702

1
1K_0402_1%

45.3_0402_1%
2.2_0603_5% 2.2_0603_5%
+VCCST_CPU

1
75_0402_1%
100_0402_1%
PR706
PC701

PR703

PR704

PR705
1U_0402_6.3V6K

2
@

2.2U_0603_10V7K

2.2U_0603_10V7K
D D

2
2

2
PC702

PC703
Psys 38

VR_VRMP
VR_PVCC
1

1
VR_VCC
PC704

1
0.01U_0402_25V7K

1K_0402_1%

1K_0402_1%

2
PR708

PR709
PR707 PR710
54.9_0402_1% @ 10_0402_1%
@ VR_SVID_DAT_1 2 1

18

13

12
VR_SVID_DAT 11
@ 20K_0402_1% PU701 NCP81206MNTXG_QFN52_6X6 PR711

2
0_0402_5% 1 PR712 2 50 36 VR_SVID_DAT_1 0_0402_5%

VRMP
PVCC

VCC
PSYS SDIO 38 VR_SVID_CLK_1 VR_SVID_ALRT#_1 2 1
PR713 SCLK 37 VR_SVID_ALRT# 11
VR_SVID_ALRT#_1 PR714
2 1 VR_EN 41 ALERT# 49.9_0402_1%
30 EC_VR_ON EN VR_SVID_CLK_1 2 1
VR_SVID_CLK 11
39
DRON DRON 45
42
30 CPU_VR_READY VR_RDY
35
30,38 VR_HOT# VRHOT# PR715 PC707
26 Vcore_BST 1 2 1 2
BST3 23.2K_0402_1%
2.7K_0402_1% 1500P_0402_50V7-K
VCORE PORTION 2.2_0603_5% 0.22U_0603_16V7K 1 PR716 2 SW3
1 PR718 2 2 1 PC708 Vcore_COMP 30 25
COMP_1a HG3 HG3 45 +CPU_CORE
20K_0402_1%
PH701
1 2 2 PR719 1Vcore_ILIM 31 22K_0402_1%
PC705 15P_0402_50V8J 1 2 ILIM_1a 24 1 PR722 2 2 1
SW3 SW3 45
1.37K_0402_1% 1000P_0402_50V7K PC709
1 PR723 2 Vcore_VSP 28 100K_0402_1%_TSM0B104F4251RZ
11 VCORE_VCC_SEN VSP_1a
1 2 1 2 23
LG3/ICCMAX_1b LG3 45
2

PC711 PR720 PC706 1000P_0402_50V7K 1K_0402_1% 11K_0402_1% 1 2

1000P_0402_50V7K 1.37K_0402_1% 1 PR721 2 Vcore_VSN 29 1 PR724 2 PC710 2200P_0402_50V7K
470P_0402_50V7K VSN_1a
1

1 2 2 1 Vcore_IOUT 34 33 Vcore_CSP 1 2
11 VCORE_VSS_SEN IOUT_1a CSP_1a
330P_0402_50V7K PC712 PC713 PC714 3300P_0402_50V7-K
2 1 27 32
PR725 TSENSE_1ph CSN_1a
C C
39.2K_0402_1%
Vcore_TSENSE
VCCGT PORTION 107K_0402_1%
1

7 GT_CSSUM 1 PR728 2 SW1

PR727 CSSUM_2ph
MOSFET

0_0402_5% 6 GT_CSCOMP PR729 1 2 75K_0402_1% 1 2 PR730

100K_0402_1%_TSM0B104F4251RZ

470P_0402_50V7K CSCOMP_2ph 143K_0402_1%

2 1 PC715 1 2
2

PH702 1 2 PC716
2 PR731 1 GT_IOUT 1 220K_0402_5%_ERTJ0EV224J 330P_0402_50V7K
IOUT_2ph
1

5 GT_ILIM 2 1 1 2 +VCC_GT
12.4K_0402_1%

30K_0402_1%
.1U_0402_10V6-K

ILIM_2ph
1
PH703

PR733

PC718

100K_0402_1% PR732 12.7K_0402_1% PC717 330P_0402_50V7K

Place close to

1 PR734 2 8 GT_CSREF 1 2
CSREF_2ph

0.22U_0603_16V7K
2

GT_DIFFOUT 2 14 GT_BST 1 2 PR735

0.01U_0402_25V7K
2

DIFFOUT_2ph/ICCMAX_2ph BST1

PC722
470P_0402_50V7K 2200P_0402_50V7K PR736 2.2_0603_5% 10_0402_1%

PC723
1 PR737 2 1 2 1 PR738 2 1 2 GT_COMP 4
COMP_2ph

1
49.9_0402_1% PC719 13.7K_0402_1% PC720 15
HG1 HG1 45
1 2 1 2

1
PR739 PC721 10P_0402_50V8J

2
1K_0402_1% GT_FB 3 16 PC724
FB_2ph SW1 SW1 45
0.047U_0402_16V7K

2
17
LG1/ROSC LG1 45
PR762 PR743
0_0402_5% 2 1
1 2 GT_VSP 51 14K_0402_1%
11 VCCGT_VCC_SEN VSP_2ph 10 GT_CSP1 1 2 SW1
CSP1_2ph
2

1.5K_0402_1% PR744
PC725 1 PR745 2 GT_VSN 52 1.8K_0402_1%
1000P_0402_50V7K VSN_2ph 9 GT_CSP2 1 2
+5VS
1

1 2 CSP2_2ph
11 VCCGT_VSS_SEN
PC726 2200P_0402_50V7K 22 0_0402_5%
BST2 PR761

GT_TSENSE 11 21
B TSENSE_2ph HG2 B

20 PR748
1.5K_0402_1% 0.015U_0402_25V7-K SW2 51.1K_0402_1%
1 PR747 2 2 1 PC727 SA_COMP 47 40 1 2
COMP_1b PWM/ADDR_VBOOT 133K_0402_1%
1 2 PR751 1 PR750 2
VCCSA PORTION VCCSA_Phase 45
1

PC728 15P_0402_50V8J 2 1 SA_ILIM 46

ILIM_1b PWM 45 +VCCSA
PR749 35.7K_0402_1%
PH704
0_0402_5% 1 2 22K_0402_1%
100K_0402_1%_TSM0B104F4251RZ

1000P_0402_50V7K PC729 1 PR753 2 2 1

3.4K_0402_1% 22.6K_0402_1%
2

1 PR754 2 SA_VSP 49 19 Vcore_ICCMAX 1 PR755 2 100K_0402_1%_TSM0B104F4251RZ

12 VCCSA_VCC_SEN VSP_1b LG2/ICCMAX_1a
3.4K_0402_1%
1

2 1 1 2 1 2
12.4K_0402_1%

1K_0402_1%
.1U_0402_10V6-K
1
PH705

PR756

PC730

PC732 PR760 PC731 1000P_0402_50V7K 1 PR757 2 SA_VSN 48 PC733 560P_0402_50V7-K

VSN_1b
IOUT_1b

1000P_0402_50V7K 44 SA_CSP 1 2
1

CSP_1b
EPAD

1 2 PC734 560P_0402_50V7-K
12 VCCSA_VSS_SEN
2

330P_0402_50V7K PC735 45
2

CSN_1b
43

53

SA_Iout
1

1
470P_0402_50V7K PR759
PC736 133K_0402_1%
2
2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/09/03 Deciphered Date 2012/09/03 PWR_CPU_CORE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Haydn-SKL
Date: Wednesday, July 22, 2015 Sheet 44 of 46
5 4 3 2 1
 5 4 3 2 1

1/27: Please double-side mount PC802,PC803 to avoid EE noise.

1/28: Change PC802,PC803 from SE00000QK00 10U 25V 0805 H0.85 to SE000011I00 10U 16V 0805 H0.85 . +CPU_CORE
PJ801
CPU_VIN 2 1
2 1 B+

10U_0805_25V6K

10U_0805_25V6K

47U_B2_10V_R70M

47U_B2_10V_R70M
0.1U_0402_25V7-K
1

1
PC802

PC803
JUMP_43X79

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
1 1

EMC@
PC801

PC814

PC815
@

1
+ +

PC804

PC805

PC806

PC807

PC808

PC809

PC810

PC811

PC812

PC813
2

2
2 2
4
44 HG3
PQ801
AON6372_DFN8-5 @ @ @
D
+CPU_CORE D
0.15UH_PCMB063T-R15MS_30A_20%

3
2
1
1 2
44 SW3
PL801

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
PR801

330U_B2_2VM_R15M
1

1
2.2_0805_5%

PC817

PC818

PC819

PC820

PC821

PC822

PC823

PC824

PC825

PC826
+

PC816
EMC_NS@

2
4
44 LG3 2
PQ802

1
AON6764_DFN8-5
PC827
1200P_0402_50V7-K

3
2
1

2
EMC_NS@

1/27: Please double-side mount PC830,PC831 to avoid EE noise.

1/28: Change PC830,PC831 from SE00000QK00 10U 25V 0805 H0.85 to SE000011I00 10U 16V 0805 H0.85 .
2/9: Change PC802 from PCMB063T-R47MS to PCMB053T-R47MS for layout limit.

PJ802
PR804 PC828 VCCSA_IN 2 1
1 2 1 2 2 1 B+

5
JUMP_43X39

47U_B2_10V_R70M
1
2.2_0603_5% 0.22U_0603_16V7K

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V7-K
1

1
+

PC830

PC831

PC870
VCCSA_BST

EMC@
PC829
PQ803

2
4 2
AON7408L_DFN8-5
2.2_0603_5% PU801 @ @
PR805 1
C
+5VS 1 2 +VCCSA_VCC 4 BST +VCCSA C

3
2
1
VCC 8 VCCSA_HG PL802
1 2 VCCSA_PWM 2 DRVH
1U_0402_10V6K

0.47UH_PCMB053T-R47MS_13A_20%
44 PWM 0_0402_5% PR806 PWM 7 VCCSA_Phase 1 2
SW
1
PC832

1 2 VCCSA_EN 3
44 DRON EN
10_0402_5% PR807 5 VCCSA_LG

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
DRVL

1
9 AON7506_DFN
2

FLAG

1
PC833

PC834

PC835

PC836

PC837

PC838

PC839

PC867

PC868

PC869
6 PR808
GND 2.2_0805_5%
NCP81253MNTBG_DFN8_2X2 PQ804 EMC_NS@

2
2
4

1
PC840
1200P_0402_50V7-K

3
2
1

2
EMC_NS@

VCCSA_Phase 44

1/27: Please double-side mount PC842,PC843 to avoid EE noise.

1/28: Change PC842,PC843 from SE00000QK00 10U 25V 0805 H0.85 to SE000011I00 10U 16V 0805 H0.85 .
B
PJ803 +VCC_GT B
GT_VIN 2 1
2 1 B+
5

JUMP_43X79
10U_0805_25V6K

10U_0805_25V6K

@
0.1U_0402_25V7-K
1

1
PC842

PC843

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
EMC@
PC841

1
PC847

PC848

PC849

PC850

PC851

PC852

PC853

PC854

PC855

PC856

PC857

PC858

PC859
2

4
44 HG1
PQ805

2
AON6372_DFN8-5

+VCC_GT @ @
3
2
1

0.15UH_PCMB063T-R15MS_30A_20%
1 2
44 SW1
PL803
5

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
1

330U_B2_2VM_R15M

330U_B2_2VM_R15M

1 1

1
PC860

PC861

PC862

PC863

PC864

PC865

PC866
PR811
2.2_0805_5% + +
PC844

PC845

EMC_NS@

2
4
44 LG1
2

PQ806 2 2
AON6764_DFN8-5 @ @
1

PC846
3
2
1

1200P_0402_50V7-K
2

EMC_NS@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/11/08 Deciphered Date 2013/11/08 PWR_CPU_Core
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Haydn-SKL
Date: Wednesday, July 22, 2015 Sheet 45 of 46
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/01/11 Deciphered Date 2013/11/08 PWR_Change list
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Haydn-SKL
Date: Wednesday, July 22, 2015 Sheet 46 of 46
5 4 3 2 1