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A B C D E

1 1

LA-G881P
Coffee Lake-S 95W
CNL PCH-H with nVIDIA N18E
REV : 1.0
2 2

2018.12.14

@ : Nopop Component
EMI@,ESD@,RF@ : EMI/ESD/RF part
CONN@ : Connector Component
@EMI@,@ESD@,@RF@ : Total debug Component
CNVI@:For WLAN
NOCP@/OCP@:For Hinge up OCP
3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/03/29 2019/03/29
Cover Page
Issued Date Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 1 of 101
A B C D E
Block Diagram
A B C D E

USB3.1 USB PD I2C P.46

TypeC CYPD4126
connector DP4+3

DGFF CARD FFS P.36

N18E-G1 KXCNL-1010
P.7~15
Mini DP P.26
DP 1.4
connector N18E-G2
N18E-G3 PEG(Gen3)x8
HDMI P.27
port8~port15

Intel CPU
HDMI 2.0
connector
1 1

eDP panel
Coffee Lake-S
P.25

LGA881P
eDP 1.3 Memory Bus 2DPC
support G-SYNC DDR4-SODIMM x4
P.12~15

1.2V DDR4 2133 MHz

95W
DP 1.4 (DDI 1)
P.30
CIO/USB3.1 P.28~29
USB3.1
TypeC Thunderbolt DP 1.4 (DDI 2)
connector
P.30
Alpine Ridge SP PCIE(Gen3)x4
USB PD TPS65982DC I2C/USB2 port21~port24

PEG(Gen3)x4
port4~port7 P.46
P.32 Head/B
P.31
PCIe re-driver DMI x 4
DS80PCI402 USB2.0 port4 P.38 P.39
AlienFX / ELC , STM32F070CB Tron/B
Caldera USB3.0 port8
connector
P.16~22
P.39
USB2.0 port3 USB2.0 port10 P.41
PWR/B
Keyboard
2 2

USB2.0 port7
P.33 P.33
Digital camera(with digital MIC)
RJ45 Transformer P.33

connector QVPA2014R 2.5 Gigabit LAN PCI-E port15


2.5GB RTL8125-CG USB3.0 port6
USB2.0 port1 USB connector 1 , left side P.26

USB3.0(Gen1) with power share


P.34
PCI-E port16
M.2 2230
Intel PCH
USB3.0 port7 USB TypeA connector 2
USB2.0 port14
WiFi + BT
P.27
USB2.0 port2 USB3.0(Gen1) right side

CNL PCH-H
Intel/Killer CNVi

BGA 874
USB3.0 port5
P.35
USB TypeA connector 3 P.27
SSD1 M.2 2280

Z390
PCI-E port 17~20 USB2.0 port8
USB3.0(Gen1) Right side
PCIe+SATA SATA 3.0
P.35
SSD2 M.2 2280 PCI-E port 09~12 USB2.0 port9 P.25

PCIe+SATA SATA3.0 Tobii (17" only)

ISH P.23
P.36
SATA3.0 Gyro+Accel Sensor
30 pin connector with option:HDD
cable 2.5 HDD x1
digital MIC
3 3

HD Audio
Audio codec
P.17
Realtek Headphone/MIC Global headset combo JACK
SPI ROM SPI
ALC3282
128Mbit
Headphone/MIC Retaskable combo JACK

I2S
P.39
I2C
AMP TI
TAS2557 Speaker
Touch pad

AMP TI
TAS2557 Speaker

PS2
DC in 1.00V dGPU
Battery Core
eSPI Bus AMP TI
TAS2557 Speaker
P.43
3V/5V 2.5V Charger
AMP TI
TAS2557 Speaker
P.42
I2C ENE SMB
KC3810
4 4

KB9542QB
P.37
Thermal Sensor
System CPU dGPU
1.2V Vcore 1.35V P.42
I2C SPI
KC3810 Audio/B
Hall Sensor

Security Classification Compal Secret Data Compal Electronics, Inc.


FAN1 FAN2
2018/03/29 2019/03/29
Block Diagrams
Issued Date Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 2 of 101
A B C D E
A

Board ID Table for AD channel


Vcc 3.3V +/- 1%
Ra 100K +/- 1%
Board ID Rb V AD_BID min V AD_BID typ V AD_BID EC
max AD3
0 0 0.000V 0.000V 0.300V
0x00 - 0x13
1 12K +/- 1% 0.347V 0.354V 0.360V
0x14 - 0x1E PCH-H Z390
2 15K +/- 1% 0.423V 0.430V 0.438V
0x1F - 0x25
3 20K +/- 1% 0.541V 0.550V 0.559V
0x26 - 0x30 HSIO USB3.1 PCIe SATA3 Function USB2 Function
4 27K +/- 1% 0.691V 0.702V 0.713V
0x31 - 0x3A 0 1 1 JUSB1(Powershare)
5 33K +/- 1% 0.807V 0.819V 0.831V
0x3B - 0x45
6 43K +/- 1% 0.978V 0.992V 1.006V
0x46 - 0x54 1 2 2 JUSB2
7 56K +/- 1% 1.169V 1.185V 1.200V
0x55 - 0x64 2 3 3 Caldera
8 75K +/- 1% 1.398V 1.414V 1.430V
0x65 - 0x76
9 100K +/- 1% 1.634V 1.650V 1.667V
0x77 - 0x87 3 4 4 ELC
4 5 JUSB3 5
5 6 JUSB1(Powershare) 6
Board ID table
NV PCB Revision 6 7 1 JUSB2 7 Camera
0 EVT 7 8 2 Caldera 8 JUSB3
1 DVT-1
2 DVT-2 8 9 3 9 Tobii
3 Pilot 9 10 4 10 Per-key
10 5 11 Thunderbolt PD
11 6 12
Voltage Rails 12 7 13
Power Plane Description S0 S4 /S3
S5 13 8 14 Bluetooth
VIN Adapter power supply N/A N/A
N/A
BATT+ Battery power supply N/A N/A
N/A 14 9
+19VB AC or battery power rail for power circuit N/A N/A
N/A 15 10 JSSD2 , 2280
+VCC_CORE Core voltage for CPU ON OFF
OFF
+VCC_GT Sliced graphics power rail ON OFF
OFF 16 11 0a SATA/PCIe x4
+0.6VS_VTT DDR +0.6VS power rail for DDR terminator ON OFF
OFF 17 12 1a
+1VALW System +1VALW power rail ON ON*
ON
+1V_PRIM System +1VALW power rail ON ON*
ON 18 13 0b JHDD
+VCCIO +1.0VS IO power rail ON OFF
OFF 19 14 1b
+VGA_PCIE +1.0VS power rail for GPU ON OFF
OFF
+MEM_GFX +1.5VS power rail for GPU ON OFF
OFF 20 15 2 LAN
+1.2V_VDDQ DDR-IV +1.2V power rail ON OFF
ON 21 16 3 WLAN
+1VS_VCCST +1.0V power rail for CPU ON OFF
ON
+1VS_VCCSTG +1.0VS power rail for CPU ON OFF
OFF 22 17 4
+3VALW System +3VALW always on power rail ON ON*
ON 23 18 5 JSSD1 , 2280
+3VLP +19VB to +3VLP power rail for suspend power ON ON
ON
+3VALW_DSW +3VALW power for PCH DSW rails ON ON*
ON 24 19 SATA/PCIe x4
+3V_LAN
+3VS
+3VALW power for LAN power rails
System +3VS power rail ON
ON ON*
ON
OFF
OFF
25 20 Symbol Note :
+1.8VALW +1.8VALW power rail for PCH ON OFF
OFF 26 21
+3VGS +3VS power rail for GPU ON OFF
OFF 27 22 Digital Ground
+5VALW System +5VALW power rail ON ON*
ON Thunderbolt
28 23
Analog Ground
+5VS System +5VS power rail ON OFF
OFF
+3VL_RTC RTC power ON ON
ON 29 24
+VCC_SA System Agent power rail ON OFF
OFF
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF

1K
4 Free Fall Sensor SMBUS Address [0x1D]
SMBUS Address [0x9A] 1K
+3VS
6

BE26 PCH_SMBCLK 253 DIMM1 SMBUS Address [0xA0] PCB


BF26 PCH_SMBDATA 254

253 DIMM2 SMBUS Address [0xA2] FPC


1 1

254

253 DIMM3 SMBUS Address [0xA4] Module


254
499

+3VS
253 DIMM4 SMBUS Address [0xA6]
499 254
SMBUS Address [0x6A]
Cannon Lake
PCH-H BF25 SML0CLK 11 PI6CEQ20200 15 JTP SMBUS Address [0x2C]
BE24 SML0DATA 10 16 Coaxial/Wire(eDP+LCDVDD)
Coaxial/Wire 30 Pin(60Hz)

Panel
U2407 SMBUS Address [0x9A]
DGFF
10
Thermal sensor 30/ 40 Pin(eDP+MIC+Camera) 40 Pin(144Hz)
1K 4.7K 9 Hinge
1K
+3V_PCH 4.7K
+3VS Speaker x4

BF27 SML1CLK
N-MOS
EC_SMB_CK2 8
U2408 SMBUS Address [0x98] Wire 10Pin
N-MOS Thermal sensor Alien Head 6Pin+LCDVDD 4Pin
BE27 SML1DATA EC_SMB_DA2 7
4.7K Fbeam FPC 68 Pin x2
+3VS Wire 14Pin
4.7K (Alien Head+MIC+Camera)
JDGFF1 JDGFF2
N-MOS UG9 Audio/B Wire 30 Pin
FFC 16 Pin
2.2K
N-MOS
VGA_SMB_CK2 BJ8 GPU SMBUS Address [0x9E] JAUDIO TP module
VGA_SMB_DA2 BH8 Lid +Codec JTP
2.2K
+3VS AMP x4 +AMP PWR
LED x 6

UM8 SMBUS Address [0xB2]

M/B
79 EC_SMB_CK2 50 PCIE redriver
FFC 6 Pin Head/B
80 EC_SMB_DA2 49
2.2K Function/B LEDx2
Wire 13 Pin
16 JPK SMBUS Address [0xC2]
2.2K
+3VALW
17 Per-key KB Battery Thermal sensor Cemera
FFC 10 Pin
0 ohm PU703
77 EC_SMB_CK1
0 ohm
SCL 4
Power Charger SMBUS Address [0x12]
78 EC_SMB_DA1 SDA 3
100 ohm
5 PBATT1
100 ohm
6 SMBUS Address [0x16] Wire 6 Pin Wire 2 Pin
0 ohm PUS1 PWR TBN/B FFC 6 Pin Tobii Host Tobii Illumination
ENE 0 ohm
22 ISL95338
SMBUS Address [0x90]
4Pin - 2Pin
KB9542QB 21 JPWR
on / off SW

0 ohm PUS2 30 Pin


22 ISL95338
0 ohm
21 SMBUS Address [0x92] LED x2 JHDD JTRON FPC |
24 Pin
UT4 Backlight FPC
B5 TPS65982
A5 SMBUS Address [0x70]
Default:FPC 6 Pin
Wire
DTC:PCB KSI/KSO FPC 24Pin Tobii Eye Sensor
UT6 Coaxia/wire 20 pin 20 Pin
50 DS80PCI402SQ SMBUS Address [0x] 20 Pin
49 4.7k 6 Pin 6 Pin 6 Pin 6 Pin
UT7
11 PI6CEQ20200 SMBUS Address [0x] 4.7k
+3VALW
10
2.5" HDD Per-key

Tron light

Tron light

Tron light

Tron light
17 EC_ESB_CLK 1
UE6 Keyboard

LED x 1
KB3810

LED x 1

LED x 1

LED x 1
18 EC_ESB_DAT 4
AMP
119/120/126 AMP_SPI_MISO/AMP_SPI_MOSI/AMP_SPI_SCLK TAS2557
128 AMP_SPI_CS_L1 SMBUS Address [?] 1
UE10
KB3810
4
AMP
68 AMP_SPI_CS_L2 TAS2557
34 AMP_SPI_CS_R1
15 AMP_SPI_CS_R2 AMP
TAS2557

AMP
TAS2557

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/03/29 2019/03/29
Notes List
Issued Date Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Si ze Document Number Rev

LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Dat e: Tuesday, January 08, 2019 Sheet 3 of 101
A
5 4 3 2 1

IMVP_VR_ON ISL6617CRZ SIC632CDT1GE3


ISL95829CHRTZ
(PUI07) (PUI01)
(PUZ01) (PUI02)
MB
ISL6617CRZ SIC632CDT1GE3
+VCC_CORE
(PUI08) (PUI01)
Audio Board (PUI02)

ISL6617CRZ SIC632CDT1GE3
(PUI09) (PUI01)
DGFF Board (PUI02)

SIC632CDT1GE3
+VCCGT
(PU507)
(PU510)
IMVP_VR_ON ISL95870BHRZ
+VCCSA
D D

(PUA01)
ADAPTER ADAPTER 13600mA (PJP200 PJP201) APE8937GN2
+1.2VP +1.2V_DDR +1.2V_VCCPLL_OC
SYSON
RT8207PGQW (UZ21)
(PU201)
2100mA (PJP202)
+0.6VSP +0.6VS JDIMM1/2 /3/ 4

PCH_PWR_EN TPS51212DSCR 5820mA (PJP102 PJP103) SYSON TPS22961


+1VALWP +1VALW +VCCST
(PU101) (U19)
ISL95338HRTZ ISL95338HRTZ
(PUS1) (PUS2) SUSP# TPS22961
+VCCSTG
NVVDD1_EN UP9511PQGJ 118000mA (U20)
(PU6000) +NVVDD1

NVVDD2_EN UP1666QQKF 39000mA


+SDC_IN (PU6400) +NVVDD2

SUSP# SY8286RAC 4480mA (PJPF02)


+VCCIOP +VCCIO
(PU509)
CHARGER
ISL88739AHRZ FBVDD/Q_EN RT8812AGQW 23000mA (PJPW2,PJPW3,PJPW4)
(PU703) +1.35VS_VGAP +1.35VS_VGA
(PUW1)
+PWR_SRC
NVVDD2_PGOOD SY8286RAC 2100mA (PJP801)
+1.0VS_VGAP +PEX_VDD
ISL88739A (PU801)

PCH_PWR_EN SY8286RAC 2100mA (PJP1802) 1V8_AON_EN


+1.8VSP +1.8VALW +1V8_AON N17E-G1 GB4-256
BATTERY (PU1801) AOZ1331
(UG9)
1V8_MAIN_EN (UG12)
+1V8_AON
Fuse +INV_PWR_SRC +1V8_MAIN N17E-G1 GB4-256
(UG9)
C C

KB9542QB
+EC_VCCA
(UE5)
F75305M
KC3810 (U2407)
(UE6/ UE10)
F75397M
3/5V_B+ TPS51225CRUKR 9128mA (PJP301) (PJP304) PCH_PWR_EN SY6288C20AAC
+3VALWP +3VALW +3V_PCH (U2408)
(PU301) (U18)
SUSP# AOZ1331 (J5)
+3VS PI6CEQ20200LIEX
(U17)
(UM4)
EN_W OL#
SY6288D20AAC RTL8125-CG
+3VALW_LAN DS80PCI402
(UL14) (UL1)
(UM8)
RT53 +3VALW_PD TP_EN (RT111 ) AOZ1336 TP Conn.
+3VS_TOUCH
3V_ELC_ON
(UT5) (JTP)
SY6288C20AAC
+3.3V_ELC NGFF Conn.
(UE9) RN20 +3V_WLAN
(JWLAN)
RT95 +3VALW_TBT ALPINE-RIDGE
RH614 +3VS_ACC
(UT1)
RT97 +3VS_TBT_SX KXCNL-1010
(US1)
PCH_ENVDD EDP FC Conn.
AOZ1334DI-02 +LCDVDD
(JFC)
(UV64)
SUSP#
AOZ1334DI-02 (JP6) NGFF Conn. JEDP Conn.
+3VSP_SSD +3VALW_SSD
B (U16) (JSSD1/2) (JEDP) B

TP_EN (RT111 ) AOZ1336 TP Conn.


+3VS_TOUCH AP2337SA-7
(UT5) (JTP) +3VS_DP JDP Conn.
(UV18)
NGFF Conn.
RN22 +3V_WLAN
(JWLAN) 3V3_SYS_EN TPS22961DNYR
+3V3_SYS
DS80PCI402SQ (UG14)
(UT6)
PCH_PWR_EN RT9059GSP (PJP1802)
+1.8VSP +1.8VALW
(PU1801)

RT9297GQW (PJP1202)
+12VP +12V_FAN
(PU1201)
PM_SLP_S4# RT9059GSP (PJP1301) (PJP2502)
+2.5V_MEMP +2.5V_MEM
(PU2501)
SI3456DDV
+5VS_TP_LED JTP Conn.
+5VALW USB_PW R_EN SY6288C20AAC (Q2409)
+5V_USB_PWR2
13330mA (PJP302 PJP303) (UU3)
3/5V_B+ TPS51225CRUKR +5VALWP
FV3
(PU301) PWRSHARE_EN_EC# TPS2546RTER +HDMI_5V_OUT JHDMI Conn.
+5V_USB_PWR1
(UU1) (JP3)
+5V_HDD
USB_PW R_EN TPS25810RVCR
+5V_USBC_VBUS
(UU7)
JPK
SUSP# AOZ1331 (J4)
+5VS
5VS_GATE (U17)
JKBBL
SY6288D20AAC
+5V_TOBII
EC_EN_AMP (UE12)
PQ8 B+_BIAS
JKB3
JKB1

A A

SY8286CRAC 4400mA (PJP502) EM5209VF


+5VP_AMP +5V_AMP +5VS_AUDIO LA31 +5VS_AVDD1
(PU501) (UA11)
RT9058-33GX 105mA (PJP402) EM5209VF LA33 +3VS_CPVDD
+3.3VP_AMP +3.3V_AMP +3VS_AUDIO
(PU401) (UA11) ALC3282-CG
(UA1)
LA32 +3.3V_1.8V_DVDD

AOZ1336
+1.8VS_AUDIO RA201 +1.8VS_AVDD2
(UT5)

TAS2557YZR
Security Classification Compal Secret Data Compal Electronics, Inc.
2018/03/29 2019/03/29 Title

Power MAP
Issued Date Deciphered Date
RT9059GSP 266mA (PJP1303) (UA3/UA5/UA6/UA7 )
+1.8VP_AMP +1.8V_AMP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Re v
(PU1301) LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 4 of 101
5 4 3 2 1
5 4 3 2 1

+3VS PR802

+3VS PR8204

1V8_EN +1.8VALW
15 PU802 G0 +1.35VS_VGA_PGOOD

+5VALW +1.35VS_VGA
G6A +1.0VS_VGA_PGOOD PU8200
PR14 FBVDD/Q_EN G7
16 PR8212
20K RT8812A
DG5
PQ3 B+_BIAS GPU_GC6_FB_EN FBVDD/Q_EN
SI3457CDV PR8216
PMOS +1.0VS_VGA_PGOOD
15
123
H_VCCST_PWRGD
RH154 H13 SOC
CPU1
D D

DG5 +3VS PR821


OVERT#
10
+1.0VS_VGA_PGOOD
Will Modify 9 G6A
DGPU_PWR_EN ME_SUS_PWR_ACK 11 G5A NVVDD2_PGOOD
1 71 NVVDD1_PGOOD +PEX_VDD
BD19 DGPU_PWROK PR801 PU800
AJ44 SY8286 G6
ACIN1_AV_IN 7a AC_PRESENT PEX_VDD_EN
ACIN 110 110 BB15 17 PR823
NVVDD2_PGOOD
DG6 G5A
POK PM_SLP_SUS# 8
38 BB13 AJ39 13
NVVDD_EN NVVDD2_EN
PR6230 PU6200
+NVVDD2
GPU_GC6_FB_EN NCP81278 G5
9 AW27 BB5 G4A NVVDD1_PGOOD 1.8VS_PGOOD
PBTN_OUT# PR6201
106 AT13
ACIN G0A
@ +3V3_SYS
UE10
PM_SLP_S5# 12 Will Modify
14 BA13 DG3 OVERT# PR6107
KC3810
A5 B6
7
A1 14
AC VIN 5 A2 +3VALW PM_SLP_S3# NVVDD1_PGOOD
6 AW15 G8 DG3 G4A
MODE
PU700 B+ PU100 +5VALW
BQ24780SRUYR TPS51225 13
CRUKR SUSACK# 9 +1.35VS_VGA_PGOOD NVVDD1_EN
UE5
BATT+ CHARGER 97 BB19 NVVDD_EN
+3VLP,VL 19
EC9022QD PCH
PR6131 PU6100 +NVVDD1
A3 B3 G4
18 SYS_PWROK UH1 CLKREQ#_GPU PEX_CLKREQ#
G3 +3V3_SYS 1.8VS_PGOOD
PR6103
NCP81278
DC 74 AY1
MODE BC24 QG5 BL26 G0A
B1 @
B2 7
BATT+ VCOUT0_PH# PCH_DPWROK Will Modify
GPU
PQ703 104 127 AV11
NMOS
C UG9 20
3V3_SYS_EN
UG14
+3V3_SYS
G3 C

EC_RSMRST# 10
A4 B5 100 BA11
G2 +1V8_MAIN 10K SY6288
112 PG515
EC_ON
19
PCIRST# TC7SH08FU PCH_PLTRST#
A6 B4 13 4 BB27 1V8_MAIN_EN +1V8_MAIN
SW1 (UH3) G2
ON/OFFBTN# G9 1V8_AON_EN UG12
+3VALW +1VALWP_PGOOD 22 +1V8_AON
DGPU_HOLD_RST# SYS_PEX_RST_MON#
PR301
BE2 G1
114 AL36
PCH_PWR_EN 9 TPS512212 +1VALW
107 UG10 G10 1V8_MAIN_EN G1A
3 (PU300) BB27 PCH_PLTRST# BE1

SY6288C20AAC +3V_PCH
(U18) +1V8_AON G1
17
PCH_PWROK
32 AW11
+1VALWP_PGOOD
122 KB_RST#
2 AT17

73 PM_SLP_S4# BD15
13
GPU power on
SY8003DFC +2.5V_MEMP SM_PG_CTRL BT13 G0 G1 G2 G4 G5 G6 G7
7 UC1
(PU1300)
121 101 116 95 15

SYSON TPS22961DNYR +VCCST


Compal Net
(U19) 13b
15
13a G1
+1.8VS_AON
VR_PWRGD

SYSON +1.2VP BH29


IMVP_VR_ON

8
Compal Net
B RT8207MZQW BH31 G2 B
(PU201) +1.8VS_MAIN
15 SM_PG_CTRL +0.6VSP BH32
7 15a
G1
+3V3_SYS G3 +1.8VS_AON

SVID Bus
14a

SUSP# AOZ1331 +3VS


16 (U17)
+NVVDD1 G4 G2
+5VS, +3VS
+1.8VS_MAIN

SUSP# SY8286RAC +NVVDD2 G5


(PU509)
+VCCIO G3
+3V3_SYS
+PEX_VDD G6
SUSP# APE8937GN2
(UZ21)
+1.2V_VCCPLL_OC 43,44,45
+1.35VS_VGA G7 +NVVDD1 G4
SVID Bus

SUSP# TPS22961DNYR
(U20)
+VCCSTG G5
+NVVDD2

IMVP_VR_ON +VCC_CORE
PR523 48 PCH_PLTRST# +PEX_VDD G6
ISL95855 SIC632
(PU500) (PU502/503/504) UM3 CDRA_RST#
47 CALDERA_RST# 22
16 TC7SH08FU +1.35VS_VGA G7

for power down sequence VR_PWRGD


16 +VCCGT JCDRA
UE6 Caldera
SIC632
(PU507/510)
KC3810
CALDERA_ PWRGD

A @ Q7A IMVP_VR_ON
+3VS
PR515
15 2 GPU power off G7 G6 G5 G4
A

G3
PM_SLP_S3# @ Q8A @ Q7B H_VCCST_PWRGD +VCCSA DGPU_PWROK
SIC531 19
(PU511) G2
@ Q8B SUSP#

G1
PM_SLP_S4# DMN65D8LDW SYSON
(Q9) @

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/03/29 2019/03/29
Power Sequence
Issued Date Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 5 of 101
5 4 3 2 1
5 4 3 2 1

UC1E

W5 H15
<15> PCH_CPU_BCLK_P BCLKP CFG_0 CFG0 <79>
W4 F15 CFG0 1 @ 2
CPU_PECI <15> PCH_CPU_BCLK_N BCLKN CFG_1
R394 1 2 0_0402_5% F16 RH637 1K_0402_5%
<58> EC_PECI CFG_2 CFG2 <79>
W1 H16
<15> PCH_CPU_PCIBCLK_P PCI_BCLKP CFG_3 CFG3 <79>
W2 F19 CFG2 1 2
<15> PCH_CPU_PCIBCLK_N PCI_BCLKN CFG_4 CFG4 <79>
H18 RH184 1K_0402_5%
CFG_5 CFG5 <79>
K9 G21
<15> CPU_24MHZ_P CLK24P CFG_6 CFG6 <79>
@ RC11 2 1 43_0402_1% J9 H20 CFG4 1 @ 2
<13> H_PECI <15> CPU_24MHZ_N CLK24N CFG_7 CFG7 <79>
G16 RH185 1K_0402_5%
D
+1.05V_VCCST CFG_8 CFG8 <79> D
E16
CFG_9 CFG9 <79>
F17 CFG5 1 2
CFG_10 CFG10 <79>
H17 RH186 1K_0402_5%
CFG_11 CFG11 <79>
G20
CFG_12 CFG12 <79>

1
RC3 F20 CFG6 1 2
CFG_13 CFG13 <79>
1K_0402_1% F21 RH187 1K_0402_5%
H_CPU_SVIDALRT# CFG_14 CFG14 <79>
E39 H19
VR_SVID_CLK_R VIDALERT# CFG_15 CFG15 <79>
E38 CFG7 1 @ 2
VR_SVID_OUT_R E40 VIDSCK F14 RH188 1K_0402_5%
CFG17 <79>

2
1 RC4 2 499_0402_1% H_PROCHOT#_R C39 VIDSOUT CFG_17 E14
<58,82,85,91> H_PROCHOT# PROCHOT# CFG_16 CFG16 <79>
F18
DDR_VTT_CNTL CFG_19 CFG19 <79>
AC36 G18
Orion use
CPU_PLTRST# DDR_VTT_CNTL CFG_18 CFG18 <79>
CC1 2 1 ESD@ 1 @ 2 AC38
<13> PROC_DETECT# SKTOCC#
100P_0402_50V8J RC356 0_0402_5% D16
CC2 2 1 @ESD@ CPU_PECI BPM#_0 D17
5P_0402_50V8C BPM#_1 G14
CC3 2 1 @ESD@ H_PM_SYNC_R +1.05V_VCCST VCCST_PWEGD_R U2 BPM#_2 H14
100P_0402_50V8J VCCST_PWRGD BPM#_3
F8
<12> H_CPUPWRGD PROCPWRGD

1
CC4 2 1 ESD@ H_CPUPWRGD RC2 CPU_PLTRST# E7 H13 XDP_TDO +1.05V_VCCST
<13> CPU_PLTRST# RESET# PROC_TDO XDP_TDI XDP_TDO <12,79>
100P_0402_50V8J 1K_0402_1% <13> H_PM_SYNC_R E8 G12 XDP_TDI <12,79>
RC5 2 1 PM_DOWN_R D8 PM_SYNC PROC_TDI F13 XDP_TMS

ESD request Close to CPU as possible


<13> H_PM_DOWN PM_DOWN PROC_TMS XDP_TMS <12,79>
20_0402_1% CPU_PECI G7 F11 PCH_JTAG_TCK
PCH_JTAG_TCK <12,79>
XDP_TMS 51_0402_5% 2 CMC@ 1 RH103
R395 1 2 0_0402_5% THERMTRIP#_R D11 PECI PROC_TCK
<13> H_THERMTRIP#

2
THERMTRIP# F12 CPU_XDP_TRST# XDP_TDI 51_0402_5% 2 CMC@ 1 RH495
PROC_TRST# XDP_PREQ# CPU_XDP_TRST# <17,79>
B9
PROC_SELECT# PROC_PREQ# XDP_PREQ# <17,79>
TC2 AB36 B10 XDP_PRDY# XDP_TDO 100_0402_1% 2 CMC@ 1 RH627
PROC_SELECT# PROC_PRDY# XDP_PRDY# <17,79>

CFL-S schematic check list v1.6 P16


RC693 1 2 51_0402_1% H_CATERR# D13
+1.05V_VCCST CATERR# M11 CFG_RCOMP 1 2
CFG_RCOMP RC26 49.9_0402_1%

+1.05V_VCCST
CFL_S62_IP_CRB_CFLS_LGA
C +1.05V_VCCST @ C

PCI EXPRESS STATIC LANE REVERSAL FOR ALL PEG PORTS


1

RC16
56_0402_1%
1: Normal Operation; Lane # definition
1

R396
RC17 CFG2 matches socket pin map definition
1 2 VR_SVID_ALRT#_L

*
<91> VR_SVID_ALRT#
2

100_0402_1%
0_0402_5% 0:Lane Reversed
1

RC19
2

To Power
220_0402_1%
Display Port Presence Strap

*
2

1 : Disabled; No Physical Display Port


<91> VR_SVID_CLK
R397 1 2 0_0402_5% VR_SVID_CLK_R
VR_SVID_OUT_R
CFG4 attached to Embedded Display Port
R398 1 2 0_0402_5%
<91> VR_SVID_OUT H_CPU_SVIDALRT#
0 : Enabled; An external Display Port device is
connected to the Embedded Display Port

PCIE Port Bifurcation Straps

To Thunderbolt
11: (Default) x16 - Device 1 functions 1 and 2 disabled
UC1D
CFG[6:5] 10: x8, x8 - Device 1 function 1 enabled ; function 2
C21 E10
<42> CPU_DP1_P0
D21 DDI1_TXP_0 EDP_TXP_0 D10
disabled
<42> CPU_DP1_N0 DDI1_TXN_0 EDP_TXN_0
+1.05V_VCCST
<42> CPU_DP1_P1
D22
DDI1_TXP_1 EDP_TXP_1
D9 01: Reserved - (Device 1 function 1 disabled ; function
E22 C9
2 enabled)

*
<42> CPU_DP1_N1 DDI1_TXN_1 EDP_TXN_1
B23 H10
<42> CPU_DP1_P2 DDI1_TXP_2 EDP_TXN_2
B
<42> CPU_DP1_N2
A23
DDI1_TXN_2 EDP_TXP_2
G10 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled B
1

RC12 C23 G9
<42> CPU_DP1_P3 DDI1_TXP_3 EDP_TXN_3
1K_0402_5% D23 F9
<42> CPU_DP1_N3 DDI1_TXN_3 EDP_TXP_3
PEG DEFER TRAINING
B13 D12

*
VCCST_PWEGD_R <42> CPU_DP1_AUXP DDI1_AUXP EDP_AUXP
1 2 C13 E12
<58,78> H_VCCST_PWRGD <42> CPU_DP1_AUXN
2

DDI1_AUXN EDP_AUXN
RC13 60.4_0402_1% 1: (Default) PEG Train immediately following xxRESETB
<42> CPU_DP2_P0
B18
DDI2_TXP_0 CFG7 de assertion
A18
<42> CPU_DP2_N0 DDI2_TXN_0
D18 D14
<42> CPU_DP2_P1 DDI2_TXP_1 EDP_DISP_UTIL
<42> CPU_DP2_N1
E18
DDI2_TXN_1
+VCCIO 0: PEG Wait for BIOS for training
C19
<42> CPU_DP2_P2 DDI2_TXP_2 EDP_RCOMP
D19 M9 RC10 2 1 24.9_0402_1%
<42> CPU_DP2_N2 DDI2_TXN_2 DISP_RCOMP
D20
EDP_RCOMP
<42> CPU_DP2_P3 DDI2_TXP_3
E20
<42> CPU_DP2_N3
Min Trace Width = 20 mils
DDI2_TXN_3

Isolation Spacing = 25 mils


A12
<42> CPU_DP2_AUXP DDI2_AUXP
B12
Trace Length < 100 mils
<42> CPU_DP2_AUXN DDI2_AUXN
B14
A14 DDI3_TXP_0
C15 DDI3_TXN_0
B15 DDI3_TXP_1
B16 DDI3_TXN_1
A16 DDI3_TXP_2
C17 DDI3_TXN_2
B17 DDI3_TXP_3
DDI3_TXN_3 V3
PROC_AUDIO_CLK CPU_DISPA_BCLK <12>
B11 V2
+1.2V_DDR DDI3_AUXP PROC_AUDIO_SDI CPU_DISPA_SDI CPU_DISPA_SDO <12>
C11 U1 RC1 1 2 30_0402_5%
DDI3_AUXN PROC_AUDIO_SDO CPU_DISPA_SDI_R <12>
+3VS
RC1 Close to CPU
For ODT & VTT CFL_S62_IP_CRB_CFLS_LGA
1 power control @
@
A CH197 UC2 A
1

@ 0.1U_0402_10V7K 5 1
RH525 2 VCC NC
2 DDR_VTT_CNTL

To Power
330K_0402_5%
4 A
@ Y 3
2

RC684 1 2 0_0402_5% GND


<87> SM_PG_CTRL
74AUP1G07GW_TSSOP5

Compal Electronics, Inc.


@
Security Classification Compal Secret Data
RC685 1 2 0_0402_5%
Issued Date 2018/03/29 Deciphered Date 2019/03/29 Title
CFL-S JTAG/XDP/DDI
PM_SLP_S3# <12,58,62,78,83,85>

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 6 of 101
5 4 3 2 1
5 4 3 2 1

D D

UC1C

B8 A5
B7 PEG_RXP_0 PEG_TXP_0 A6
PEG_RXN_0 PEG_TXN_0
C7 B4
C6 PEG_RXP_1 PEG_TXP_1 B5
PEG_RXN_1 PEG_TXN_1
D6 C3
D5 PEG_RXP_2 PEG_TXP_2 C4
PEG_RXN_2 PEG_TXN_2
C E5 D2 C
E4 PEG_RXP_3 PEG_TXP_3 D3
PEG_RXN_3 PEG_TXN_3
F6 E1 PEG_CTX_GRX_P11 CC58 1 2 0.22U_0201_6.3V
<74> PEG_CRX_GTX_P11 PEG_RXP_4 PEG_TXP_4 PEG_CTX_GRX_N11 PEG_CTX_C_GRX_P11 <74>
F5 E2 CC63 1 2 0.22U_0201_6.3V
<74> PEG_CRX_GTX_N11 PEG_RXN_4 PEG_TXN_4 PEG_CTX_C_GRX_N11 <74>
G5 F2 PEG_CTX_GRX_P10 CC61 1 2 0.22U_0201_6.3V

Caldera TX
<74> PEG_CRX_GTX_P10 PEG_RXP_5 PEG_TXP_5 PEG_CTX_GRX_N10 PEG_CTX_C_GRX_P10 <74>
G4 F3 CC62 1 2 0.22U_0201_6.3V

Caldera RX
<74> PEG_CRX_GTX_N10 PEG_RXN_5 PEG_TXN_5 PEG_CTX_C_GRX_N10 <74>
H6 G1 PEG_CTX_GRX_P9 CC59 1 2 0.22U_0201_6.3V
<74> PEG_CRX_GTX_P9 PEG_RXP_6 PEG_TXP_6 PEG_CTX_GRX_N9 PEG_CTX_C_GRX_P9 <74>
H5 G2 CC56 1 2 0.22U_0201_6.3V
<74> PEG_CRX_GTX_N9 PEG_RXN_6 PEG_TXN_6 PEG_CTX_C_GRX_N9 <74>
J5 H2 PEG_CTX_GRX_P8 CC57 1 2 0.22U_0201_6.3V
<74> PEG_CRX_GTX_P8 PEG_RXP_7 PEG_TXP_7 PEG_CTX_GRX_N8 PEG_CTX_C_GRX_P8 <74>
J4 H3 CC60 1 2 0.22U_0201_6.3V
<74> PEG_CRX_GTX_N8 PEG_RXN_7 PEG_TXN_7 PEG_CTX_C_GRX_N8 <74>
K6 J1 PEG_CTX_GRX_P7 CC20 1 2 0.22U_0402_6.3V7K
<37> PEG_CRX_GTX_P7 PEG_RXP_8 PEG_TXP_8 PEG_CTX_C_GRX_P7 <37>
K5 J2 PEG_CTX_GRX_N7 CC21 1 2 0.22U_0402_6.3V7K
<37> PEG_CRX_GTX_N7 PEG_RXN_8 PEG_TXN_8 PEG_CTX_C_GRX_N7 <37>
L5 K2 PEG_CTX_GRX_P6 CC18 1 2 0.22U_0402_6.3V7K
<37> PEG_CRX_GTX_P6 PEG_RXP_9 PEG_TXP_9 PEG_CTX_C_GRX_P6 <37>
L4 K3 PEG_CTX_GRX_N6 CC19 1 2 0.22U_0402_6.3V7K
<37> PEG_CRX_GTX_N6 PEG_RXN_9 PEG_TXN_9 PEG_CTX_C_GRX_N6 <37>

GPU TX
M6 L1 PEG_CTX_GRX_P5 CC16 1 2 0.22U_0402_6.3V7K
<37> PEG_CRX_GTX_P5 PEG_RXP_10 PEG_TXP_10 PEG_CTX_C_GRX_P5 <37>
M5 L2 PEG_CTX_GRX_N5 CC17 1 2 0.22U_0402_6.3V7K

GPU RX
<37> PEG_CRX_GTX_N5 PEG_RXN_10 PEG_TXN_10 PEG_CTX_C_GRX_N5 <37>
N5 M2 PEG_CTX_GRX_P4 CC14 1 2 0.22U_0402_6.3V7K
<37> PEG_CRX_GTX_P4 PEG_RXP_11 PEG_TXP_11 PEG_CTX_C_GRX_P4 <37>
N4 M3 PEG_CTX_GRX_N4 CC15 1 2 0.22U_0402_6.3V7K
<37> PEG_CRX_GTX_N4 PEG_RXN_11 PEG_TXN_11 PEG_CTX_C_GRX_N4 <37>
P6 N1 PEG_CTX_GRX_P3 CC12 1 2 0.22U_0402_6.3V7K
<37> PEG_CRX_GTX_P3 PEG_RXP_12 PEG_TXP_12 PEG_CTX_C_GRX_P3 <37>
P5 N2 PEG_CTX_GRX_N3 CC13 1 2 0.22U_0402_6.3V7K
<37> PEG_CRX_GTX_N3 PEG_RXN_12 PEG_TXN_12 PEG_CTX_C_GRX_N3 <37>
B +VCCIO B
R5 P2 PEG_CTX_GRX_P2 CC10 1 2 0.22U_0402_6.3V7K
<37> PEG_CRX_GTX_P2 PEG_RXP_13 PEG_TXP_13 PEG_CTX_C_GRX_P2 <37>
R4 P3 PEG_CTX_GRX_N2 CC11 1 2 0.22U_0402_6.3V7K
<37> PEG_CRX_GTX_N2 PEG_RXN_13 PEG_TXN_13 PEG_CTX_C_GRX_N2 <37>
1

RC14 T6 R2 PEG_CTX_GRX_P1 CC8 1 2 0.22U_0402_6.3V7K


<37> PEG_CRX_GTX_P1 PEG_RXP_14 PEG_TXP_14 PEG_CTX_C_GRX_P1 <37>
24.9_0402_1% T5 R1 PEG_CTX_GRX_N1 CC9 1 2 0.22U_0402_6.3V7K
<37> PEG_CRX_GTX_N1 PEG_RXN_14 PEG_TXN_14 PEG_CTX_C_GRX_N1 <37>
U5 T2 PEG_CTX_GRX_P0 CC6 1 2 0.22U_0402_6.3V7K
<37> PEG_CRX_GTX_P0 PEG_RXP_15 PEG_TXP_15 PEG_CTX_C_GRX_P0 <37>
U4 T3 PEG_CTX_GRX_N0 CC7 1 2 0.22U_0402_6.3V7K
<37> PEG_CRX_GTX_N0 PEG_CTX_C_GRX_N0 <37>
2

PEG_RXN_15 PEG_TXN_15

PEG_RCOMP L7
PEG_RCOMP
Typ- suggest 220nF. The change in AC capacitor
PEG_RCOMP value from 100nF to 220nF is to enable
Trace Width = 5 mils DMI_CRX_PTX_P0 Y3 AC2 DMI_CTX_PRX_P0 compatibility with future platforms having PCIE
Trace Spacing to Other Signals =15 mils <14> DMI_CRX_PTX_P0 DMI_CRX_PTX_N0 Y4 DMI_RXP_0 DMI_TXP_0 AC1 DMI_CTX_PRX_N0
DMI_CTX_PRX_P0 <14>
Gen3 (8GT/s)
<14> DMI_CRX_PTX_N0 DMI_CTX_PRX_N0 <14>
Trace Length < 600 mils DMI_RXN_0 DMI_TXN_0
DMI_CRX_PTX_P1 AA4 AD3 DMI_CTX_PRX_P1
<14> DMI_CRX_PTX_P1 DMI_CRX_PTX_N1 AA5 DMI_RXP_1 DMI_TXP_1 DMI_CTX_PRX_P1 <14>
AD2 DMI_CTX_PRX_N1
<14> DMI_CRX_PTX_N1 DMI_RXN_1 DMI_TXN_1 DMI_CTX_PRX_N1 <14>
DMI_CRX_PTX_P2 AB4 AE2 DMI_CTX_PRX_P2
<14> DMI_CRX_PTX_P2 DMI_CRX_PTX_N2 AB3 DMI_RXP_2 DMI_TXP_2 DMI_CTX_PRX_P2 <14>
AE1 DMI_CTX_PRX_N2
<14> DMI_CRX_PTX_N2 DMI_RXN_2 DMI_TXN_2 DMI_CTX_PRX_N2 <14>
DMI_CRX_PTX_P3 AC4 AF2 DMI_CTX_PRX_P3
<14> DMI_CRX_PTX_P3 DMI_CRX_PTX_N3 AC5 DMI_RXP_3 DMI_TXP_3 DMI_CTX_PRX_P3 <14>
AF3 DMI_CTX_PRX_N3
<14> DMI_CRX_PTX_N3 DMI_RXN_3 DMI_TXN_3 DMI_CTX_PRX_N3 <14>

A A

CFL_S62_IP_CRB_CFLS_LGA
@

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2018/03/29 Deciphered Date 2019/03/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CFL-S DMI/PEG
Size Document Number Rev
LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 7 of 101
5 4 3 2 1
5 4 3 2 1

Channel A Channel B
<23,25> DDR_A_D[0..63] <24,26> DDR_B_D[0..63]
<23,25> DDR_A_MA[0..13] <24,26> DDR_B_MA[0..13]
<23,25> DDR_A_DQS#[0..7] <24,26> DDR_B_DQS#[0..7]
D <23,25> DDR_A_DQS[0..7] <24,26> DDR_B_DQS[0..7] D

UC1A UC1B
DDR_A_D0 AE38 AW18 DDR_B_D0 AD34 AM20
DDR_A_D1 DDR0_DQ_0/DDR0_DQ_0 DDR0_CKP_0 DDR_A_CLK0 <25> DDR_B_D1 DDR1_DQ_0/DDR0_DQ_16 DDR1_CKP_0 DDR_B_CLK0 <26>
AE37 AV18 AD35 AM21
DIMM2 DIMM4
DDR_A_D2 DDR0_DQ_1/DDR0_DQ_1 DDR0_CKN_0 DDR_A_CLK#0 <25> DDR_B_D2 DDR1_DQ_1/DDR0_DQ_17 DDR1_CKN_0 DDR_B_CLK#0 <26>
AG38 AW17 AG35 AP22
DDR_A_D3 DDR0_DQ_2/DDR0_DQ_2 DDR0_CKP_1 DDR_A_CLK1 <25> DDR_B_D3 DDR1_DQ_2/DDR0_DQ_18 DDR1_CKP_1 DDR_B_CLK1 <26>
AG37 AY17 AH35 AP21
DDR_A_D4 DDR0_DQ_3/DDR0_DQ_3 DDR0_CKN_1 DDR_A_CLK#1 <25> DDR_B_D4 DDR1_DQ_3/DDR0_DQ_19 DDR1_CKN_1 DDR_B_CLK#1 <26>
AE39 AW16 AE35 AN20
DDR_A_D5 DDR0_DQ_4/DDR0_DQ_4 DDR0_CKP_2 DDR_A_CLK2 <23> DDR_B_D5 DDR1_DQ_4/DDR0_DQ_20 DDR1_CKP_2 DDR_B_CLK2 <24>
AE40 AV16 AE34 AN21
DIMM1 DIMM3
DDR_A_D6 DDR0_DQ_5/DDR0_DQ_5 DDR0_CKN_2 DDR_A_CLK#2 <23> DDR_B_D6 DDR1_DQ_5/DDR0_DQ_21 DDR1_CKN_2 DDR_B_CLK#2 <24>
AG39 AT16 AG34 AP19
DDR_A_D7 DDR0_DQ_6/DDR0_DQ_6 DDR0_CKP_3 DDR_A_CLK3 <23> DDR_B_D7 DDR1_DQ_6/DDR0_DQ_22 DDR1_CKP_3 DDR_B_CLK3 <24>
AG40 AU16 AH34 AP20
DDR_A_D8 DDR0_DQ_7/DDR0_DQ_7 DDR0_CKN_3 DDR_A_CLK#3 <23> DDR_B_D8 DDR1_DQ_7/DDR0_DQ_23 DDR1_CKN_3 DDR_B_CLK#3 <24>
AJ38 AK35
DDR_A_D9 AJ37 DDR0_DQ_8/DDR0_DQ_8 AY24 DDR_B_D9 AL35 DDR1_DQ_8/DDR0_DQ_24 AY29
DIMM2 DIMM4
DDR_A_D10 DDR0_DQ_9/DDR0_DQ_9 DDR0_CKE_0 DDR_A_CKE0 <25> DDR_B_D10 DDR1_DQ_9/DDR0_DQ_25 DDR1_CKE_0 DDR_B_CKE0 <26>
AL38 AW24 AK32 AV29
DDR_A_D11 DDR0_DQ_10/DDR0_DQ_10 DDR0_CKE_1 DDR_A_CKE1 <25> DDR_B_D11 DDR1_DQ_10/DDR0_DQ_26 DDR1_CKE_1 DDR_B_CKE1 <26>
AL37 AV24 AL32 AW29
DIMM1 DIMM3
DDR_A_D12 DDR0_DQ_11/DDR0_DQ_11 DDR0_CKE_2 DDR_A_CKE2 <23> DDR_B_D12 DDR1_DQ_11/DDR0_DQ_27 DDR1_CKE_2 DDR_B_CKE2 <24>
AJ40 AV25 AK34 AU29
DDR_A_D13 DDR0_DQ_12/DDR0_DQ_12 DDR0_CKE_3 DDR_A_CKE3 <23> DDR_B_D13 DDR1_DQ_12/DDR0_DQ_28 DDR1_CKE_3 DDR_B_CKE3 <24>
AJ39 AL34
DDR_A_D14 AL39 DDR0_DQ_13/DDR0_DQ_13 AW12 DDR_B_D14 AK31 DDR1_DQ_13/DDR0_DQ_29 AP17
DIMM2 DIMM4
DDR_A_D15 DDR0_DQ_14/DDR0_DQ_14 DDR0_CS#_0 DDR_A_CS#0 <25> DDR_B_D15 DDR1_DQ_14/DDR0_DQ_30 DDR1_CS#_0 DDR_B_CS#0 <26>
AL40 AU11 AL31 AN15
DDR_A_D16 DDR0_DQ_15/DDR0_DQ_15 DDR0_CS#_1 DDR_A_CS#1 <25> DDR_B_D16 DDR1_DQ_15/DDR0_DQ_31 DDR1_CS#_1 DDR_B_CS#1 <26>
AN38 AV13 AP35 AN17
DIMM1 DIMM3
DDR_A_D17 DDR0_DQ_16/DDR0_DQ_32 DDR0_CS#_2 DDR_A_CS#2 <23> DDR_B_D17 DDR1_DQ_16/DDR0_DQ_48 DDR1_CS#_2 DDR_B_CS#2 <24>
AN40 AV10 AN35 AM15
DDR_A_D18 DDR0_DQ_17/DDR0_DQ_33 DDR0_CS#_3 DDR_A_CS#3 <23> DDR_B_D18 DDR1_DQ_17/DDR0_DQ_49 DDR1_CS#_3 DDR_B_CS#3 <24>
AR38 AN32
DDR_A_D19 AR37 DDR0_DQ_18/DDR0_DQ_34 AW11 DDR_B_D19 AP32 DDR1_DQ_18/DDR0_DQ_50 AM16
DIMM2 DIMM4
DDR_A_D20 DDR0_DQ_19/DDR0_DQ_35 DDR0_ODT_0 DDR_A_ODT0 <25> DDR_B_D20 DDR1_DQ_19/DDR0_DQ_51 DDR1_ODT_0 DDR_B_ODT0 <26>
AN39 AU14 AN34 AL16
DDR_A_D21 DDR0_DQ_20/DDR0_DQ_36 DDR0_ODT_1 DDR_A_ODT1 <25> DDR_B_D21 DDR1_DQ_20/DDR0_DQ_52 DDR1_ODT_1 DDR_B_ODT1 <26>
AN37 AU12 AP34 AP15
DIMM1 DIMM3
DDR_A_D22 DDR0_DQ_21/DDR0_DQ_37 DDR0_ODT_2 DDR_A_ODT2 <23> DDR_B_D22 DDR1_DQ_21/DDR0_DQ_53 DDR1_ODT_2 DDR_B_ODT2 <24>
AR39 AY10 AN31 AL15
DDR_A_D23 DDR0_DQ_22/DDR0_DQ_38 DDR0_ODT_3 DDR_A_ODT3 <23> DDR_B_D23 DDR1_DQ_22/DDR0_DQ_54 DDR1_ODT_3 DDR_B_ODT3 <24>
AR40 AP31
C DDR_A_D24 AW37 DDR0_DQ_23/DDR0_DQ_39 AY13 DDR_A_BA0 DDR_B_D24 AL29 DDR1_DQ_23/DDR0_DQ_55 AN18 DDR_B_RAS# C
DDR_A_D25 DDR0_DQ_24/DDR0_DQ_40 DDR0_BA_0 DDR_A_BA1 DDR_A_BA0 <23,25> DDR_B_D25 DDR1_DQ_24/DDR0_DQ_56 DDR1_MA_16 DDR_B_WE# DDR_B_RAS# <24,26>
AU38 AV15 DDR_A_BA1 <23,25> AM29 AL17 DDR_B_WE# <24,26>
DDR_A_D26 AV35 DDR0_DQ_25/DDR0_DQ_41 DDR0_BA_1 AW23 DDR_A_BG0 DDR_B_D26 AP29 DDR1_DQ_25/DDR0_DQ_57 DDR1_MA_14 AP16 DDR_B_CAS#
DDR_A_D27 DDR0_DQ_26/DDR0_DQ_42 DDR0_BG_0 DDR_A_BG0 <23,25> DDR_B_D27 DDR1_DQ_26/DDR0_DQ_58 DDR1_MA_15 DDR_B_CAS# <24,26>
AW35 AR29
DDR_A_D28 AU37 DDR0_DQ_27/DDR0_DQ_43 AW13 DDR_A_RAS# DDR_B_D28 AM28 DDR1_DQ_27/DDR0_DQ_59 AL18 DDR_B_BA0
DDR_A_D29 DDR0_DQ_28/DDR0_DQ_44 DDR0_MA_16 DDR_A_WE# DDR_A_RAS# <23,25> DDR_B_D29 DDR1_DQ_28/DDR0_DQ_60 DDR1_BA_0 DDR_B_BA1 DDR_B_BA0 <24,26>
AV37 AV14 DDR_A_WE# <23,25> AL28 AM18 DDR_B_BA1 <24,26>
DDR_A_D30 AT35 DDR0_DQ_29/DDR0_DQ_45 DDR0_MA_14 AY11 DDR_A_CAS# DDR_B_D30 AR28 DDR1_DQ_29/DDR0_DQ_61 DDR1_BA_1 AW28 DDR_B_BG0
DDR_A_D31 DDR0_DQ_30/DDR0_DQ_46 DDR0_MA_15 DDR_A_CAS# <23,25> DDR_B_D31 DDR1_DQ_30/DDR0_DQ_62 DDR1_BG_0 DDR_B_BG0 <24,26>
AU35 AP28
DDR_A_D32 AY8 DDR0_DQ_31/DDR0_DQ_47 AW15 DDR_A_MA0 DDR_B_D32 AR12 DDR1_DQ_31/DDR0_DQ_63 AL19 DDR_B_MA0
DDR_A_D33 AW8 DDR0_DQ_32/DDR1_DQ_0 DDR0_MA_0 AU18 DDR_A_MA1 DDR_B_D33 AP12 DDR1_DQ_32/DDR1_DQ_16 DDR1_MA_0 AL22 DDR_B_MA1
DDR_A_D34 AV6 DDR0_DQ_33/DDR1_DQ_1 DDR0_MA_1 AU17 DDR_A_MA2 DDR_B_D34 AM13 DDR1_DQ_33/DDR1_DQ_17 DDR1_MA_1 AM22 DDR_B_MA2
DDR_A_D35 AU6 DDR0_DQ_34/DDR1_DQ_2 DDR0_MA_2 AV19 DDR_A_MA3 DDR_B_D35 AL13 DDR1_DQ_34/DDR1_DQ_18 DDR1_MA_2 AM23 DDR_B_MA3
DDR_A_D36 AU8 DDR0_DQ_35/DDR1_DQ_3 DDR0_MA_3 AT19 DDR_A_MA4 DDR_B_D36 AR13 DDR1_DQ_35/DDR1_DQ_19 DDR1_MA_3 AP23 DDR_B_MA4
DDR_A_D37 AV8 DDR0_DQ_36/DDR1_DQ_4 DDR0_MA_4 AU20 DDR_A_MA5 DDR_B_D37 AP13 DDR1_DQ_36/DDR1_DQ_20 DDR1_MA_4 AL23 DDR_B_MA5
DDR_A_D38 AW6 DDR0_DQ_37/DDR1_DQ_5 DDR0_MA_5 AV20 DDR_A_MA6 DDR_B_D38 AM12 DDR1_DQ_37/DDR1_DQ_21 DDR1_MA_5 AW26 DDR_B_MA6
DDR_A_D39 AY6 DDR0_DQ_38/DDR1_DQ_6 DDR0_MA_6 AU21 DDR_A_MA7 DDR_B_D39 AL12 DDR1_DQ_38/DDR1_DQ_22 DDR1_MA_6 AY26 DDR_B_MA7
DDR_A_D40 AY4 DDR0_DQ_39/DDR1_DQ_7 DDR0_MA_7 AT20 DDR_A_MA8 DDR_B_D40 AP10 DDR1_DQ_39/DDR1_DQ_23 DDR1_MA_7 AU26 DDR_B_MA8
DDR_A_D41 AV4 DDR0_DQ_40/DDR1_DQ_8 DDR0_MA_8 AT22 DDR_A_MA9 DDR_B_D41 AR10 DDR1_DQ_40/DDR1_DQ_24 DDR1_MA_8 AW27 DDR_B_MA9
DDR_A_D42 AT1 DDR0_DQ_41/DDR1_DQ_9 DDR0_MA_9 AY14 DDR_A_MA10 DDR_B_D42 AR7 DDR1_DQ_41/DDR1_DQ_25 DDR1_MA_9 AP18 DDR_B_MA10
DDR_A_D43 AT2 DDR0_DQ_42/DDR1_DQ_10 DDR0_MA_10 AU22 DDR_A_MA11 DDR_B_D43 AP7 DDR1_DQ_42/DDR1_DQ_26 DDR1_MA_10 AU27 DDR_B_MA11
DDR_A_D44 AV3 DDR0_DQ_43/DDR1_DQ_11 DDR0_MA_11 AV22 DDR_A_MA12 DDR_B_D44 AR9 DDR1_DQ_43/DDR1_DQ_27 DDR1_MA_11 AV27 DDR_B_MA12
DDR_A_D45 AW4 DDR0_DQ_44/DDR1_DQ_12 DDR0_MA_12 AV12 DDR_A_MA13 DDR_B_D45 AP9 DDR1_DQ_44/DDR1_DQ_28 DDR1_MA_12 AR15 DDR_B_MA13
DDR_A_D46 AT4 DDR0_DQ_45/DDR1_DQ_13 DDR0_MA_13 AV23 DDR_A_BG1 DDR_B_D46 AR6 DDR1_DQ_45/DDR1_DQ_29 DDR1_MA_13 AY28 DDR_B_BG1
DDR_A_D47 DDR0_DQ_46/DDR1_DQ_14 DDR0_BG_1 DDR_A_ACT# DDR_A_BG1 <23,25> DDR_B_D47 DDR1_DQ_46/DDR1_DQ_30 DDR1_BG_1 DDR_B_ACT# DDR_B_BG1 <24,26>
AT3 AU24 AP6 AU28
DDR_A_D48 DDR0_DQ_47/DDR1_DQ_15 DDR0_ACT# DDR_A_ACT# <23,25> DDR_B_D48 DDR1_DQ_47/DDR1_DQ_31 DDR1_ACT# DDR_B_ACT# <24,26>
AP2 AM10
DDR_A_D49 AM4 DDR0_DQ_48/DDR1_DQ_32 AY15 DDR_B_D49 AL10 DDR1_DQ_48/DDR1_DQ_48 AL20
DDR_A_D50 DDR0_DQ_49/DDR1_DQ_33 DDR0_PAR DDR_A_PAR <23,25> DDR_B_D50 DDR1_DQ_49/DDR1_DQ_49 DDR1_PAR DDR_B_PAR <24,26>
AP3 AT23 DDR_A_ALERT# <23,25> AM7 AY25 DDR_B_ALERT# <24,26>
DDR_A_D51 AM3 DDR0_DQ_50/DDR1_DQ_34 DDR0_ALERT# DDR_B_D51 AL7 DDR1_DQ_50/DDR1_DQ_50 DDR1_ALERT#
DDR_A_D52 AP4 DDR0_DQ_51/DDR1_DQ_35 DDR_B_D52 AM9 DDR1_DQ_51/DDR1_DQ_51
DDR_A_D53 AM2 DDR0_DQ_52/DDR1_DQ_36 AF39 DDR_A_DQS#0 DDR_B_D53 AL9 DDR1_DQ_52/DDR1_DQ_52 AF34 DDR_B_DQS#0
DDR_A_D54 AP1 DDR0_DQ_53/DDR1_DQ_37 DDR0_DQSN_0/DDR0_DQSN_0 AK39 DDR_A_DQS#1 DDR_B_D54 AM6 DDR1_DQ_53/DDR1_DQ_53 DDR1_DQSN_0/DDR0_DQSN_2 AK33 DDR_B_DQS#1
DDR_A_D55 AM1 DDR0_DQ_54/DDR1_DQ_38 DDR0_DQSN_1/DDR0_DQSN_1 AP39 DDR_A_DQS#2 DDR_B_D55 AL6 DDR1_DQ_54/DDR1_DQ_54 DDR1_DQSN_1/DDR0_DQSN_3 AN33 DDR_B_DQS#2
DDR_A_D56 AK3 DDR0_DQ_55/DDR1_DQ_39 DDR0_DQSN_2/DDR0_DQSN_4 AU36 DDR_A_DQS#3 DDR_B_D56 AJ6 DDR1_DQ_55/DDR1_DQ_55 DDR1_DQSN_2/DDR0_DQSN_6 AN29 DDR_B_DQS#3
DDR_A_D57 AH1 DDR0_DQ_56/DDR1_DQ_40 DDR0_DQSN_3/DDR0_DQSN_5 AW7 DDR_A_DQS#4 DDR_B_D57 AJ7 DDR1_DQ_56/DDR1_DQ_56 DDR1_DQSN_3/DDR0_DQSN_7 AN13 DDR_B_DQS#4
DDR_A_D58 AK4 DDR0_DQ_57/DDR1_DQ_41 DDR0_DQSN_4/DDR1_DQSN_0 AU3 DDR_A_DQS#5 DDR_B_D58 AE6 DDR1_DQ_57/DDR1_DQ_57 DDR1_DQSN_4/DDR1_DQSN_2 AR8 DDR_B_DQS#5
B DDR_A_D59 AH2 DDR0_DQ_58/DDR1_DQ_42 DDR0_DQSN_5/DDR1_DQSN_1 AN3 DDR_A_DQS#6 DDR_B_D59 AF7 DDR1_DQ_58/DDR1_DQ_58 DDR1_DQSN_5/DDR1_DQSN_3 AM8 DDR_B_DQS#6 B
DDR_A_D60 AH4 DDR0_DQ_59/DDR1_DQ_43 DDR0_DQSN_6/DDR1_DQSN_4 AJ3 DDR_A_DQS#7 DDR_B_D60 AH7 DDR1_DQ_59/DDR1_DQ_59 DDR1_DQSN_6/DDR1_DQSN_6 AG6 DDR_B_DQS#7
DDR_A_D61 AK2 DDR0_DQ_60/DDR1_DQ_44 DDR0_DQSN_7/DDR1_DQSN_5 DDR_B_D61 AH6 DDR1_DQ_60/DDR1_DQ_60 DDR1_DQSN_7/DDR1_DQSN_7
DDR_A_D62 AH3 DDR0_DQ_61/DDR1_DQ_45 AF38 DDR_A_DQS0 DDR_B_D62 AE7 DDR1_DQ_61/DDR1_DQ_61 AF35 DDR_B_DQS0
DDR_A_D63 AK1 DDR0_DQ_62/DDR1_DQ_46 DDR0_DQSP_0/DDR0_DQSP_0 AK38 DDR_A_DQS1 DDR_B_D63 AF6 DDR1_DQ_62/DDR1_DQ_62 DDR1_DQSP_0/DDR0_DQSP_2 AL33 DDR_B_DQS1
DDR0_DQ_63/DDR1_DQ_47 DDR0_DQSP_1/DDR0_DQSP_1 AP38 DDR_A_DQS2 DDR1_DQ_63/DDR1_DQ_63 DDR1_DQSP_1/DDR0_DQSP_3 AP33 DDR_B_DQS2
AU33 DDR0_DQSP_2/DDR0_DQSP_4 AV36 DDR_A_DQS3 AR25 DDR1_DQSP_2/DDR0_DQSP_6 AN28 DDR_B_DQS3
AT33 DDR0_ECC_0 DDR0_DQSP_3/DDR0_DQSP_5 AV7 DDR_A_DQS4 AR26 DDR1_ECC_0 DDR1_DQSP_3/DDR0_DQSP_7 AN12 DDR_B_DQS4
AW33 DDR0_ECC_1 DDR0_DQSP_4/DDR1_DQSP_0 AU2 DDR_A_DQS5 AM26 DDR1_ECC_1 DDR1_DQSP_4/DDR1_DQSP_2 AP8 DDR_B_DQS5
AV31 DDR0_ECC_2 DDR0_DQSP_5/DDR1_DQSP_1 AN2 DDR_A_DQS6 AM25 DDR1_ECC_2 DDR1_DQSP_5/DDR1_DQSP_3 AL8 DDR_B_DQS6
AU31 DDR0_ECC_3 DDR0_DQSP_6/DDR1_DQSP_4 AJ2 DDR_A_DQS7 AP26 DDR1_ECC_3 DDR1_DQSP_6/DDR1_DQSP_6 AG7 DDR_B_DQS7
AV33 DDR0_ECC_4 DDR0_DQSP_7/DDR1_DQSP_5 AP25 DDR1_ECC_4 DDR1_DQSP_7/DDR1_DQSP_7
AW31 DDR0_ECC_5 AV32 AL25 DDR1_ECC_5 AN25
AY31 DDR0_ECC_6 DDR0_DQSP_8/DDR0_DQSP_8 AU32 AL26 DDR1_ECC_6 DDR1_DQSP_8/DDR1_DQSP_8 AN26
DDR0_ECC_7 DDR0_DQSN_8/DDR0_DQSN_8 DDR1_ECC_7 DDR1_DQSN_8/DDR1_DQSN_8

DDR CHANNEL B
Trace width / Spacing = 10 / 12 mils
DDR CHANNEL A AB40 +0.6V_VREF_CA
DDR_VREF_CA AC40 SA_DIMM_VREFDQ
DDR0_VREF_DQ TC7
AC39 +0.6V_VREF_DQ
DDR1_VREF_DQ

CFL_S62_IP_CRB_CFLS_LGA CFL_S62_IP_CRB_CFLS_LGA Trace width / Spacing = 10 / 12 mils


@ @

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2018/03/29 Deciphered Date 2019/03/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CFL-S DDR4
Size Document Number Rev
LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 8 of 101
5 4 3 2 1
5 4 3 2 1

35A
+VCC_CORE +VCC_CORE

49A PLACE ALL BELOW CAPS ON


+VCCGT

TOP SIDE NEAR CPU SOCKET


+VCCSA
UC1G UC1H

A25 H32 AA34


A26 VCC1 VCC90 J21 AA35 VCCGT1
A27 VCC2 VCC93 F32 47U_0805_6.3V6M 47U_0805_6.3V6M 22U_0603_6.3V6M AA36 VCCGT2
A28 VCC3 VCC68 F33 AA37 VCCGT3
D
A29 VCC4 VCC69 F34 AA38 VCCGT4 D
VCC5 VCC70 1 1 1 1 1 1 VCCGT5
A30 G23 CC52 CC51 CC50 CC49 CC47 CC48 AB33
B25 VCC6 VCC73 G24 AB34 VCCGT6
B27 VCC24 VCC74 G25 G36 VCCGT7
B29 VCC25 VCC75 G26 2 2 2 2 2 2 G37 VCCGT8
B31 VCC26 VCC76 G27 +1.2V_DDR G38 VCCGT9
B32 VCC27 VCC77 G28 47U_0805_6.3V6M 47U_0805_6.3V6M 22U_0603_6.3V6M G39 VCCGT10
B33 VCC28 VCC78 G29 G40 VCCGT11
B34 VCC29 VCC79 J22 H36 VCCGT12

PLACE ALL BELOW CAPS ON


B35 VCC30 VCC94 J23 H38 VCCGT13

PLACE ALL ABOVE CAPS ON 2.5A TOP SIDE NEAR CPU SOCKET
B36 VCC31 VCC95 J24 H40 VCCGT14

1.05V / 11A
UC1I
VCC32 VCC96 VCCGT15
TOP SIDE OF CPU CAVITY
B37 J25 J36
C25 VCC33 VCC97 J26 AA7 AT18 22U_0603_6.3V6M 22U_0603_6.3V6M J37 VCCGT16
C26 VCC34 VCC98 J27 AB6 VCCSA2 VDDQ1 AT21 J38 VCCGT17
C27 VCC35 VCC99 J28 AB7 VCCSA3 VDDQ2 AU13 J39 VCCGT18
VCC36 VCC100 1 1 1 1 VCCSA4 VDDQ3 1 1 1 1 VCCGT19
C28 J29 CC29 CC28 CC26 CC27 AB8 AU15 CC22 CC23 CC24 CC25 J40
C29 VCC37 VCC101 J30 AC7 VCCSA5 VDDQ4 AU19 K36 VCCGT20
C30 VCC38 VCC102 J31 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M AC8 VCCSA6 VDDQ5 AU23 K38 VCCGT21
C32 VCC39 VCC103 K16 2 2 2 2 N7 VCCSA7 VDDQ6 AV11 2 2 2 2 K40 VCCGT22
C34 VCC40 VCC106 K18 P7 VCCSA8 VDDQ7 AV17 L34 VCCGT23
C36 VCC41 VCC107 K20 R7 VCCSA9 VDDQ8 AV21 22U_0603_6.3V6M 22U_0603_6.3V6M L35 VCCGT24
D25 VCC42 VCC108 K21 T7 VCCSA10 VDDQ9 AW10 L36 VCCGT25
D27 VCC43 VCC109 K23 U7 VCCSA11 VDDQ10 AW14 L37 VCCGT26
D29 VCC44 VCC110 K25 Y6 VCCSA12 VDDQ11 AW25 L38 VCCGT27
D31 VCC45 VCC111 K27 Y7 VCCSA15 VDDQ12 AY12 L39 VCCGT28
D32 VCC46 VCC112 K29 Y8 VCCSA16 VDDQ13 AY16 L40 VCCGT29
D33 VCC47 VCC113 K31 W7 VCCSA17 VDDQ14 AY18 +1.2V_VCCPLL_OC M33 VCCGT30

PLACE ALL ABOVE CAPS ON


D34 VCC48 VCC114 L14 V7 VCCSA14 VDDQ15 AY23 M34 VCCGT31
VCC49 VCC117 VCCSA13 VDDQ16 VCCGT32
TOP SIDE OF CPU CAVITY
D35 L15 +VCCIO AA6 S0IX@ M36
D36 VCC50 VCC118 L16 VCCSA1 AJ9 VCCPLL_OC RC21 1 2 0_0402_5% M38 VCCGT33

0.95V/5.5A 100mA
+1.2V_DDR
E24 VCC51 VCC119 L17 VCCPLL_OC M40 VCCGT34
E25 VCC52 VCC120 L18 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M AK11 N34 VCCGT35
E26 VCC53 VCC121 L19 AK14 VCCIO2 NS0IX@ N35 VCCGT36
E27 VCC54 VCC122 L20 AK24 VCCIO3 RC25 1 2 0_0402_5% N36 VCCGT37
VCC55 VCC123 1 1 1 1 1 1 VCCIO4 VCCGT38
E28 L21 CC32 CC33 CC34 CC35 CC36 CC37 AJ23 N37
VCC56 VCC124 VCCIO1 VCCGT39
C E29
VCC57 VCC125
L22 M8
VCCIO5
For NON-S0IX N38
VCCGT40
C
E30 L23 P8 2 N39
E32 VCC58 VCC126 L24 2 2 2 2 2 2 T8 VCCIO6 CC46 @ N40 VCCGT41
E34 VCC59 VCC127 L25 U8 VCCIO7 1U_0201_6.3V6M P33 VCCGT42
E36 VCC60 VCC128 L26 22U_0805_6.3V6M~D 22U_0603_6.3V6M 22U_0603_6.3V6M W8 VCCIO8 SE00000UC00 P34 VCCGT43
F23 VCC61 VCC129 L27 +1.05V_VCCST VCCIO9 1 P36 VCCGT44
F24 VCC62 VCC130 L28 P38 VCCGT45

1.05V/120mA V5
F25 VCC63 VCC131 L29 +1.05V_VCCST P40 VCCGT46
F27 VCC64 VCC132 L30 R34 VCCGT47
F29 VCC65 VCC133 M13 V6 VCCST1 R35 VCCGT48
F31 VCC66 VCC136 M14 VCCST2 R36 VCCGT49
VCC67 VCC137 VCCGT50
G30
VCC80 VCC138
M16 9/12:change from SE000000I10 to SE00000M000*2 V4
VCCPLL
R37
VCCGT51
G32 M18 R38
H22 VCC81 VCC139 M20 R39 VCCGT52
H23 VCC84 VCC140 M22 R40 VCCGT53
VCC85 VCC141 VCCGT54

22U_0603_6.3V6M

22U_0603_6.3V6M
H25 M24 1 1 1 T33
H27 VCC86 VCC142 M26 T34 VCCGT55
VCC87 VCC143 VCCGT56

CC38

CC30
H29 M28 CC31 T36
H31 VCC88 VCC144 M30 1U_0201_6.3V6M T38 VCCGT57
AJ11 VCC89 VCC145 AJ12 2 2 2 SE00000UC00 T40 VCCGT58
AJ13 VCC7 VCC8 AJ14 AD5 VCCSA_SENSE U34 VCCGT59

Place as close to socket as possible


VCC9 VCC10 VCCSA_SENSE VCCIO_SENSE VCCSA_SENSE <96> VCCGT60
AJ15 AJ16 AF4 VCCIO_SENSE <89> U35
AJ17 VCC11 VCC12 AJ18 VCCIO_SENSE AE4 VSSSAIO_SENSE U36 VCCGT61
VCC13 VCC14 VSS_SAIO_SENSE VSSSAIO_SENSE <96> VCCGT62
AJ19 AJ20 U37
AJ21 VCC15 VCC16 U38 VCCGT63
VCC17 U39 VCCGT64
M32 AJ29 U40 VCCGT65 +VCCGT
L31 VCC146 VCC22 AK21 V33 VCCGT66
K32 VCC134 VCC23 F35 V34 VCCGT67
J33 VCC115 VCC71 F37 V36 VCCGT68
H33 VCC104 VCC72 G35 +VCC_CORE V38 VCCGT69
VCC91 VCC83 VCCGT70

1
G34 H34 CFL_S62_IP_CRB_CFLS_LGA V40 RC691
AJ25 VCC82 VCC92 J35 @ W34 VCCGT71
VCC18 VCC105 VCCGT72 100_0402_1%
AJ26 K34 W35
AJ27 VCC19 VCC116 L33 W36 VCCGT73
VCC20 VCC135 VCCGT74
1

B AJ28 RC197 W37 B

2
VCC21 W38 VCCGT75 F39
100_0402_1% VCCGT76 VCCGT_SENSE VCCGT_VCC_SEN <91>
Y33 F38 VCCGT_VSS_SEN <91>
Y34 VCCGT77 VSSGT_SENSE
Y36 VCCGT78
2

C38 Y38 VCCGT79


VCC_SENSE VCORE_VCC_SEN <91> VCCGT80

1
D38 VCORE_VSS_SEN <91> RC690
VSS_SENSE
100_0402_1%

CFL_S62_IP_CRB_CFLS_LGA CFL_S62_IP_CRB_CFLS_LGA
1

@ RC686 @

2
100_0402_1%
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2018/03/29 Deciphered Date 2019/03/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CFL-S POWER
Size Document Number Rev
LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 9 of 101
5 4 3 2 1
5 4 3 2 1

UC1F UC1K UC1L

A4 AK5 AR3 AN1 D40 D4


AG2 VSS_NCTF_A4 VSS_AK5 AK8 AR4 VSS_AR3 VSS_AN1 AN4 K4 VSS_NCTF_D40 VSS_D4 D7
AG3 VSS_AG2 VSS_AK8 AK9 AR5 VSS_AR4 VSS_AN4 AN5 K7 VSS_K4 VSS_D7 D24
AG33 VSS_AG3 VSS_AK9 AL14 AR24 VSS_AR5 VSS_AN5 AN6 K39 VSS_K7 VSS_D24 D26
AG36 VSS_AG33 VSS_AL14 AL11 AR27 VSS_AR24 VSS_AN6 AN7 L3 VSS_K39 VSS_D26 D28
AG4 VSS_AG36 VSS_AL11 AL1 AR30 VSS_AR27 VSS_AN7 AN8 L6 VSS_L3 VSS_D28 D30
AG5 VSS_AG4 VSS_AL1 AL2 AR31 VSS_AR30 VSS_AN8 AN9 L9 VSS_L6 VSS_D30 D37
AH33 VSS_AG5 VSS_AL2 AL21 AR32 VSS_AR31 VSS_AN9 AN10 L13 VSS_L9 VSS_D37 D39 UC1J
D D
AG8 VSS_AH33 VSS_AL21 AL24 AR33 VSS_AR32 VSS_AN10 AN11 L32 VSS_L13 VSS_D39 E3
AH36 VSS_AG8 VSS_AL24 AL27 AR34 VSS_AR33 VSS_AN11 AN14 M1 VSS_L32 VSS_E3 E6 RSVD_TP2 J8 AC37
VSS_AH36 VSS_AL27 TC16 @
AH37 AL3 AR35 VSS_AR34 VSS_AN14 AN16 M4 VSS_M1 VSS_E6 E9 RSVD_TP1 J7 RSVD_TP2 RSVD4 AB35
VSS_AH37 VSS_AL3 TC15 @
AH38 AL30 AR36 VSS_AR35 VSS_AN16 AN19 M7 VSS_M4 VSS_E9 E11 IST_TRIG L8 RSVD_TP1 RSVD1 AB37
VSS_AH38 VSS_AL30 TC13 @
AH39 AL36 AT5 VSS_AR36 VSS_AN19 AN22 M10 VSS_M7 VSS_E11 E13 RSVD_TP3 K8 IST_TRIG RSVD2 AB38
VSS_AH39 VSS_AL36 TC12 @
AH5 AL4 AT6 VSS_AT5 VSS_AN22 AN23 M12 VSS_M10 VSS_E13 E15 RSVD_TP3 RSVD3 AJ22
AH40 VSS_AH5 VSS_AL4 AL5 AT7 VSS_AT6 VSS_AN23 AN24 M15 VSS_M12 VSS_E15 E17 RSVD8 AV1 RSVD5 D15
VSS_AH40 VSS_AL5 TC17 @
AJ1 AM11 AT8 VSS_AT7 VSS_AN24 AN27 M17 VSS_M15 VSS_E17 E19 For debug RSVD9 AW2 RSVD8 RSVD12 K11
VSS_AJ1 VSS_AM11 TC18 @
AH8 AM14 AT9 VSS_AT8 VSS_AN27 AN30 M19 VSS_M17 VSS_E19 E21 RSVD9 RSVD21
AG1 VSS_AH8 VSS_AM14 AM17 AT10 VSS_AT9 VSS_AN30 AN36 M21 VSS_M19 VSS_E21 E23 H8
A15 VSS_AG1 VSS_AM17 AM19 AT11 VSS_AT10 VSS_AN36 AP5 M23 VSS_M21 VSS_E23 E31 RSVD13
A13 VSS_A15 VSS_AM19 AM24 AT12 VSS_AT11 VSS_AP5 AP11 M25 VSS_M23 VSS_E31 E33 RSVD20 K10
VSS_A13 VSS_AM24 TC19 @
A24 AM27 AT13 VSS_AT12 VSS_AP11 AP14 M27 VSS_M25 VSS_E33 E35 RSVD24 L10 RSVD20
VSS_A24 VSS_AM27 TC14 @
AA3 AM30 AT14 VSS_AT13 VSS_AP14 AP24 M29 VSS_M27 VSS_E35 E37 RSVD24
AA33 VSS_AA3 VSS_AM30 AM31 AT17 VSS_AT14 VSS_AP24 AP27 M35 VSS_M29 VSS_E37 F1 J17
A11 VSS_AA33 VSS_AM31 AM32 AT24 VSS_AT17 VSS_AP27 AP30 M37 VSS_M35 VSS_F1 F4 B39 RSVD18
A17 VSS_A11 VSS_AM32 AM33 AT25 VSS_AT24 VSS_AP30 AP36 M39 VSS_M37 VSS_F4 F7 C40 RSVD10 J15
AA8 VSS_A17 VSS_AM33 AM34 AT26 VSS_AT25 VSS_AP36 AP37 N3 VSS_M39 VSS_F7 F10 J19 RSVD11 RSVD17 J14
AB39 VSS_AA8 VSS_AM34 AM35 AT27 VSS_AT26 VSS_AP37 AP40 N6 VSS_N3 VSS_F10 F22 RSVD19 RSVD16
AC33 VSS_AB39 VSS_AM35 AM36 AT28 VSS_AT27 VSS_AP40 AR1 N8 VSS_N6 VSS_F22 F26 G8 AU9
AC3 VSS_AC33 VSS_AM36 AM37 AT29 VSS_AT28 VSS_AR1 AR2 N33 VSS_N8 VSS_F26 F28 AY3 VSS_G8 RSVD7 AU10
AB5 VSS_AC3 VSS_AM37 AM38 AT30 ?VSS_AT29 VSS_AR2 AR11 P1 VSS_N33 VSS_F28 F30 VSS_AY3 RSVD6
AC34 VSS_AB5 VSS_AM38 AM39 AT31 VSS_AT30 VSS_AR11 AR14 P4 VSS_P1 VSS_F30 F36 RC692 1 2 30_0402_5% D1
VSS_AC34 VSS_AM39 <17> PCH_TRIGGER
AC35 AM40 AT32 VSS_AT31 VSS_AR14 AR16 P35 VSS_P4 VSS_F36 F40 1 2 CPU_2_PCH_TRIG_C B3 PROC_TRIGIN J13
VSS_AC35 VSS_AM40 <17> CPU_TRIGGER
AC6 AM5 AT34 VSS_AT32 VSS_AR16 AR17 P37 VSS_P35 VSS_F40 G3 RC36 20_0402_5% PROC_TRIGOUT RSVD15 K13
AD33 VSS_AC6 VSS_AM5 AK7 AT36 VSS_AT34 VSS_AR17 AR18 P39 VSS_P37 VSS_G3 G6 L12 RSVD23 J11
AD1 VSS_AD33 VSS_AK7 AK6 AT37 VSS_AT36 VSS_AR18 AR19 R3 VSS_P39 VSS_G6 G11 K12 RSVD25 RSVD14
AD38 VSS_AD1 VSS_AK6 AK40 AT38 VSS_AT37 VSS_AR19 AR20 R6 VSS_R3 VSS_G11 G13 RSVD22
C AD39 VSS_AD38 VSS_AK40 AK37 AT39 VSS_AT38 VSS_AR20 AR21 R8 VSS_R6 VSS_G13 G15 C
AD4 VSS_AD39 VSS_AK37 AK36 AT40 VSS_AT39 VSS_AR21 AR22 R33 VSS_R8 VSS_G15 G17
AD6 VSS_AD4 VSS_AK36 AK30 AU1 VSS_AT40 VSS_AR22 AR23 T1 VSS_R33 VSS_G17 G19
AD40 VSS_AD6 VSS_AK30 AK29 AU4 VSS_AU1 VSS_AR23 AT15 T4 VSS_T1 VSS_G19 G22 CFL_S62_IP_CRB_CFLS_LGA
AD7 VSS_AD40 VSS_AK29 AJ24 AU5 VSS_AU4 VSS_AT15 AU39 T35 VSS_T4 VSS_G22 G31 @
AD8 VSS_AD7 VSS_AJ24 AJ30 AU7 VSS_AU5 VSS_AU39 AU40 T37 VSS_T35 VSS_G31 G33
AE3 VSS_AD8 VSS_AJ30 AK22 AU25 VSS_AU7 VSS_AU40 AV39 T39 VSS_T37 VSS_G33 H1
AE36 VSS_AE3 VSS_AK22 AK27 AU30 VSS_AU25 VSS_AV39 AW38 U3 VSS_T39 VSS_H1 H4
AE5 VSS_AE36 VSS_AK27 AJ4 AU34 VSS_AU30 VSS_AW38 C5 U6 VSS_U3 VSS_H4 H7
AE33 VSS_AE5 VSS_AJ4 AJ5 AV2 VSS_AU34 VSS_C5 C8 U33 VSS_U6 VSS_H7 H9
AF1 VSS_AE33 VSS_AJ5 AJ8 AV5 VSS_AV2 VSS_C8 C10 V1 VSS_U33 VSS_H9 H11
AE8 VSS_AF1 VSS_AJ8 AK10 AV9 VSS_AV5 VSS_C10 C37 V8 VSS_V1 VSS_H11 H12
AF33 VSS_AE8 VSS_AK10 AK12 AV26 VSS_AV9 VSS_C37 B24 V35 VSS_V8 VSS_H12 H21
AF36 VSS_AF33 VSS_AK12 AK13 AV28 VSS_AV26 VSS_B24 B26 V37 VSS_V35 VSS_H21 H24
AF37 VSS_AF36 VSS_AK13 AK15 AV30 VSS_AV28 VSS_B26 B28 V39 VSS_V37 VSS_H24 H26
AF40 VSS_AF37 VSS_AK15 AK16 AV34 VSS_AV30 VSS_B28 B30 W3 VSS_V39 VSS_H26 H28
AF5 VSS_AF40 VSS_AK16 AK17 AV38 VSS_AV34 VSS_B30 B38 W6 VSS_W3 VSS_H28 H30
AF8 VSS_AF5 VSS_AK17 AK18 AW3 VSS_AV38 VSS_B38 C2 W33 VSS_W6 VSS_H30 H35
A7 VSS_AF8 VSS_AK18 AK19 AW5 VSS_AW3 VSS_NCTF_C2 C12 Y5 VSS_W33 VSS_H35 H37
AJ31 VSS_A7 VSS_AK19 AK20 AW9 VSS_AW5 VSS_C12 C14 Y35 VSS_Y5 VSS_H37 H39
AJ32 VSS_AJ31 VSS_AK20 AK23 AW30 VSS_AW9 VSS_C14 C16 Y37 VSS_Y35 VSS_H39 J3
AJ33 VSS_AJ32 VSS_AK23 AK25 AW32 VSS_AW30 VSS_C16 C18 K15 VSS_Y37 VSS_J3 J6
AJ34 VSS_AJ33 VSS_AK25 AK26 AW34 VSS_AW32 VSS_C18 C20 K17 VSS_K15 VSS_J6 J10
AJ35 VSS_AJ34 VSS_AK26 AK28 AW36 VSS_AW34 VSS_C20 C22 K19 VSS_K17 VSS_J10 J12
AJ36 VSS_AJ35 VSS_AK28 AD36 AY5 VSS_AW36 VSS_C22 C24 K22 VSS_K19 VSS_J12 J16
AD37 VSS_AJ36 VSS_AD36 AY7 VSS_AY5 VSS_C24 C31 K24 VSS_K22 VSS_J16 J18
VSS_AD37 AY9 VSS_AY7 VSS_C31 C33 K26 VSS_K24 VSS_J18 J20
CFL_S62_IP_CRB_CFLS_LGA AY27 VSS_AY9 VSS_C33 C35 K28 VSS_K26 VSS_J20 J32
@ AY30 VSS_AY27 VSS_C35 B6 K30 VSS_K28 VSS_J32 J34
B VSS_AY30 VSS_B6 K33 VSS_K30 VSS_J34 K1 B
K35 VSS_K33 VSS_K1 K14
CFL_S62_IP_CRB_CFLS_LGA K37 VSS_K35 VSS_K14
@ L11 VSS_K37
VSS_L11

CFL_S62_IP_CRB_CFLS_LGA
@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2018/03/29 Deciphered Date 2019/03/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CFL-S GND, RSVD
Size Document Number Rev
LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 10 of 101
5 4 3 2 1
5 4 3 2 1

+3V_PCH +3VS

RH99 2 1 100K_0402_5% GPP_H15 CNP-H


UH1A
#571182_CNL_PCH_H_EDS_V1_Rev0.7 BE36 AV29 PCH_PLTRST#
PCH_PLTRST# <74> 1
External pull-up is required. Recommend 100K if pulled
GPP_A11/PME#/SD_VDD2_PWR_EN# GPP_B13/PLTRST# CH201

up to 3.3V or 75K if pulled up to 1.8V.


0.1U_0201_6.3V6K
RH1 intel check list spec : R15 Y47
571007_CFL_MOW_Archive_WW22_2017
RSVD2 GPP_K16/GSXCLK TBT_FORCE_PWR <42> 2
Route from XDP_HOOK[3] to PCH-H SPI0_MOSI
R13 Y46
STUFF R on GPP_H15
RSVD1 GPP_K12/GSXDOUT Y48
by placing a 1.5K± 5 % s eri es r esi st or.
RH1 close to UH4
D GPP_K13/GSXSLOAD W46 UH3
D
AL37 GPP_K14/GSXDIN AA45 TC7SH08FU_SSOP5
VSS GPP_K15/GSXSRESET#

5
AN35 PCH_PLTRST# 1
TP B 4

P
PCH_SPI_0_SI Y PCIRST# <42,51,52,58,68>
RH1 1 2 1K_0402_1% AU41 AL47 2
<79> XDP_SPI_SI PCH_SPI_0_SO SPI0_MOSI GPP_E3/CPU_GP0 A
BA45 AM45
SPI0_MISO GPP_E7/CPU_GP1

1
G
PCH_SPI_0_CS# AY47 BF32 RH1024 RH199
PCH_SPI_0_CLK AW47 SPI0_CS0# GPP_B3/CPU_GP2 BC33 100K_0402_5% 100K_0402_5%

3
+3V_PCH AW48 SPI0_CLK GPP_B4/CPU_GP3
SPI0_CS1# AE44 +RTC_CELL
PCH_SPI_0_WP# AY48 GPP_H18/SML4ALERT# AJ46
<79> PCH_SPI_0_WP#

2
RH100 1 @ 2 4.7K_0402_5% GPP_H12 PCH_SPI_0_HOLD# BA46 SPI0_IO2 GPP_H17/SML4DATA AE43
AT40 SPI0_IO3 GPP_H16/SML4CLK AC47 GPP_H15
SPI0_CS2# GPP_H15/SML3ALERT# AD48
This signal has a weak internal pull-down.
GPP_H14/SML3DATA

2
BE19 AF47 RH531
0 = Master Attached Flash Sharing (MAFS) enabled (Default)
BF19 GPP_D1/SPI1_CLK/SBK1_BK1 GPP_H13/SML3CLK AB47 GPP_H12
GPP_D0/SPI1_CS#/SBK0_BK0 GPP_H12/SML2ALERT# 1M_0402_5%
FFS_INT2
1 = Slave Attached Flash Sharing (SAFS) enabled.
BF18 AD47
<15,67> FFS_INT2 FFS_INT1 GPP_D3/SPI1_MOSI/SBK3_BK3 GPP_H11/SML2DATA
BE18 AE48
Notes:
<15,67> FFS_INT1 BC17 GPP_D2/SPI1_MISO/SBK2_BK2 GPP_H10/SML2CLK
TC29
1. This signal is in the primary well.

1
TC30 BD17 GPP_D22/SPI1_IO3 1 OF 13 BB44 INTRUDER#
GPP_D21/SPI1_IO2 INTRUDER#
Warning: This strap must be configured to 0 if t he
eSPI or LPC strap is configured to 0
CNP-H_BGA874 Rev1.0

@

+3V_PCH

+3V_PCH
1
CH49
0.1U_0402_16V7K
RPH5 2
1 2 100K_0402_5% PCH_SPI_0_SI PCH_SPI_0_HOLD# 4 5 PCH_SPI_0_HOLD#_R UH4
RH631
PCH_SPI_0_SO 3 6 PCH_SPI_0_SO_R PCH_SPI_0_CS# 1 8
PCH_SPI_0_SI 2 7 PCH_SPI_0_SI_R PCH_SPI_0_SO_R 2 CS# VCC 7 PCH_SPI_0_HOLD#_R
RH632 1 2 100K_0402_5% PCH_SPI_0_SO PCH_SPI_0_WP# 1 8 PCH_SPI_0_WP#_R PCH_SPI_0_WP#_R 3 DO(IO1) IO 6 PCH_SPI_0_CLK_R
4 IO2 CLK 5 PCH_SPI_0_SI_R
C C
33_0804_8P4R_5% GND DI(IO0)
RH633 1 2 100K_0402_5% PCH_SPI_0_WP#
W25Q128JVSIQ_SO8

1
PCH_SPI_0_CLK 1 2 PCH_SPI_0_CLK_R @EMI@
RH104 EMI@ 33_0402_1% RH591
RH634 1 2 100K_0402_5% PCH_SPI_0_HOLD# 33_0402_5%
1
EMI@

2
CH246 1
RH635 1 2 20K_0402_5%~D PCH_SPI_0_CS# 22P_0402_50V8J @EMI@
2 CH232
33P_0402_50V8J
RH636 1 2 20K_0402_5%~D PCH_SPI_0_CLK 2

CFL-H PDG rev1.1


pull-up 20K for SPI0_MOSI, SPI0_MISO,SPI0_IO2/3
pull-down 20K for SPI0_MLK, SPI0_CS[2:0]#

CNP-H
UH1F +1.8VS_EC
F9 BB39
B USB31_1_TXN GPP_A1/LAD0/ESPI_IO0 ESPI_IO0 <58> B
F7 AW37
D11 USB31_1_TXP GPP_A2/LAD1/ESPI_IO1 AV37 ESPI_IO1 <58>
USB31_1_RXN GPP_A3/LAD2/ESPI_IO2 ESPI_IO2 <58> ESPI_SERIRQ
C11 BA38 RH111 1 2 10K_0402_5%~D
USB31_1_RXP GPP_A4/LAD3/ESPI_IO3 ESPI_IO3 <58>
C3
D4 USB31_2_TXN BE38 ESPI_FRAME# ESPI_KB_RST# RH518 1 2 10K_0402_5%~D
B9 USB31_2_TXP GPP_A5/LFRAME#/ESPI_CS0# AW35 ESPI_SERIRQ ESPI_FRAME# <58>
USB31_2_RXN GPP_A6/SERIRQ/ESPI_CS1# ESPI_SERIRQ <58>
C9 BA36
USB31_2_RXP GPP_A7/PIRQA#/ESPI_ALERT0# BE39 ESPI_KB_RST#

Left JUSB1 Charger


GPP_A0/RCIN#/ESPI_ALERT1# ESPI_RST# ESPI_KB_RST# <58>
C17 BF38
<71> USB3_PTX_DRX_N6 USB31_6_TXN GPP_A14/SUS_STAT#/ESPI_RESET# ESPI_RST# <58>
C16
<71> USB3_PTX_DRX_P6 G14 USB31_6_TXP BB36 EMI@ RH89 1 2 33_0402_5%
<71> USB3_PRX_DTX_N6 USB31_6_RXN GPP_A9/CLKOUT_LPC0/ESPI_CLK CLK_PCI_ESPI <58>
F14 BB34
<71> USB3_PRX_DTX_P6 C15 USB31_6_RXP GPP_A10/CLKOUT_LPC1

Right JUSB3
<72> USB3_PTX_DRX_N5 USB31_5_TXN
B15 T48 1 @RF@
<72> USB3_PTX_DRX_P5 USB31_5_TXP GPP_K19/SMI#
J13 T47 CH244
<72> USB3_PRX_DTX_N5 K13 USB31_5_RXN GPP_K18/NMI# 10P_0402_50V8J
<72> USB3_PRX_DTX_P5 USB31_5_RXP
G12 AH40 2
F11 USB31_3_TXP GPP_E6/SATA_DEVSLP2 AH35
USB31_3_TXN GPP_E5/SATA_DEVSLP1 DEVSLP1 <68>
C10 AL48
B10 USB31_3_RXP GPP_E4/SATA_DEVSLP0 AP47 DEVSLP0 <67>
USB31_3_RXN GPP_F9/SATA_DEVSLP7 AN37
C14 GPP_F8/SATA_DEVSLP6 AN46
B14 USB31_4_TXP GPP_F7/SATA_DEVSLP5 AR47
USB31_4_TXN GPP_F6/SATA_DEVSLP4 DEVSLP4 <68>
J15 AP48
K16 USB31_4_RXP 6 OF 13 GPP_F5/SATA_DEVSLP3
USB31_4_RXN
CNP-H_BGA874 Rev1.0

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/03/29 2019/03/29
PCH (1/7) SPI, ESPI
Issued Date Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 11 of 101
5 4 3 2 1
5 4 3 2 1

+3V_PCH

RP2 1 2 33_0201_5% HDA_SDOUT


<56> HDA_SDOUT_R HDA_SYNC
RP6 1 2 33_0201_5% WAKE# RH453 1 2 1K_0402_5%
<56> HDA_SYNC_R 1 2 33_0201_5% HDA_RST#
RP7
TC28 PCH_BATLOW# RH515 1 2 8.2K_0402_5%
AC_PRESENT RH533 1 @ 2 8.2K_0402_5%

EC interface
D D
WAKE_PCH# RH545 1 2 10K_0402_5%

High eSPI
Low(default) LPC
+3V_PCH

+3V_PCH
RF@ ME_SUS_PWR_ACK RH506 1 @ 2 1M_0402_5%
CH243 2 1 10P_0402_50V8J CNP-H
RH1023 1 2 4.7K_0402_5% SML0ALERT# UH1D SYS_RESET# RH571 1 2 8.2K_0402_5%
RT707 1 2 33_0402_5% HDA_BIT_CLK BD11 BF36
<56> HDA_BIT_CLK_R HDA_BCLK/I2S0_SCLK GPP_A12/BM_BUSY#/ISH_GP6/SX_EXIT_HOLDOFF#
BE11 AV32 CLKRUN#
<56> HDA_SDIN 1 2 33_0402_5% HDA_SDOUT BF12 HDA_SDI0/I2S0_RXD GPP_A8/CLKRUN#
RH16 +3VS
<58> ME_EN HDA_SYNC HDA_SDO/I2S0_TXD
BG13 BF41
HDA_SYNC/I2S0_SFRM GPD11/LANPHYPC
HDA_RST# BE10 BD42 CLKRUN# RH85 1 2 8.2K_0402_5%
BF10 HDA_RST#/I2S1_SCLK GPD9/SLP_WLAN#
BE12 HDA_SDI1/I2S1_RXD BB46
I2S1_TXD/SNDW2_DATA DRAM_RESET# H_DRAMRST# <23>
BD12 BE32
I2S1_SFRM/SNDW2_CLK GPP_B2/VRALERT# BF33
GPP_B1/GSPI1_CS1#/TIME_SYNC1 BE29
RH39 1 2 20_0402_5% CPU_DISPA_SDO_R AM2 GPP_B0/GSPI0_CS1# R47
<6> CPU_DISPA_SDO AN3 HDACPU_SDO GPP_K17/ADR_COMPLETE AP29
<6> CPU_DISPA_SDI_R CPU_DISPA_BCLK_R HDACPU_SDI GPP_B11/I2S_MCLK
RH38 1 2 30_0402_5% AM3 AU3
<6> CPU_DISPA_BCLK HDACPU_SCLK SYS_PWROK SYS_PWROK <58>
AV18 BB47 WAKE# RH4 2 @ 1 0_0402_5%
GPP_D8/I2S2_SCLK WAKE# PCIE_WAKE# <51,58>
AW18 BE40
BA17 GPP_D7/I2S2_RXD GPD6/SLP_A# BF40 RH1018 2 1 0_0402_5%
+3V_PCH <52> CLKREQ_CNV# GPP_D6/I2S2_TXD/MODEM_CLKREQ SLP_LAN# TBT_PCIE_WAKE# <42,58>
BE16 BC28
<52> CNV_RF_RESET# GPP_D5/I2S2_SFRM/CNV_RF_RESET# GPP_B12/SLP_S0#
BF15 BF42
BD16 GPP_D20/DMIC_DATA0/SNDW4_DATA GPD4/SLP_S3# BE42 PM_SLP_S3# <6,58,62,78,83,85>
GPP_D19/DMIC_CLK0/SNDW4_CLK GPD5/SLP_S4# PM_SLP_S4# <58,78>
RH95 1 @ 2 4.7K_0402_5% SMBALERT# AV16 BC42
AW15 GPP_D18/DMIC_DATA1/SNDW3_DATA GPD10/SLP_S5# PM_SLP_S5# <58,62>
GPP_D17/DMIC_CLK1/SNDW3_CLK BE45
This signal has a weak internal Pull-down.
GPD8/SUSCLK PCH_BATLOW# SUSCLK <68>
BF44
PCH_BATLOW# <42>
0 = Disable Intel ME Crypto Transport Layer Security
GPD0/BATLOW# BE35 SUSACK# RH1016 2 @ 1 0_0402_5%
PCH_RTCRST# GPP_A15/SUSACK# ME_SUS_PWR_ACK PCH_PWR_EN <12,58,78,88,98>
(TLS) cipher suite (no confidentiality). (Default)
C BE47 BC37 C
<59> PCH_RTCRST# PCH_SRTCRST# BD46 RTCRST# GPP_A13/SUSWARN#/SUSPWRDNACK
1 = Enable Intel ME Crypto Transport Layer Security
<59> PCH_SRTCRST# SRTCRST#

(TLS) cipher suite (with confidentiality). Must be AY42 BG44 WAKE_PCH#


<58> PCH_PWROK PCH_PWROK GPD2/LAN_WAKE#
pulled up to support Intel AMT with TLS.
EC_RSMRST# BA47 BG42 AC_PRESENT 2 1 @ DH1
<58> EC_RSMRST# RSMRST# GPD1/ACPRESENT VCIN1_AC_IN <58,85>
Notes:
BD39 RB751V-40_SOD323-2
SLP_SUS# BE46 PBTN_OUT#
1. The internal Pull-down is disabled after RSMRST#
GPD3/PWRBTN# PBTN_OUT# <58>

1
PCH_DPWROK SYS_RESET#

10K_0402_5%
@ RH1025
RH1017 2 1 0_0402_5% AW41 AU2
de-asserts. SMBALERT# BE25 DSW_PWROK SYS_RESET# AW29 HDA_SPKR
PCH_SMBCLK GPP_C2/SMBALERT# GPP_B14/SPKR HDA_SPKR <56>
2. This signal is in the primary well.
BE26 AE3
<23,24,25,26,63,67> PCH_SMBCLK PCH_SMBDATA GPP_C0/SMBCLK CPUPWRGD H_CPUPWRGD <6>
BF26
<23,24,25,26,63,67> PCH_SMBDATA BF24 GPP_C1/SMBDATA AL3
SML0ALERT#
XDP_ITP_PMODE <79>

2
SML0CLK BF25 GPP_C5/SML0ALERT# ITP_PMODE AH4
<74> SML0CLK GPP_C3/SML0CLK PCH_JTAGX PCH_JTAG_TCK <6,79>
SML0DATA BE24 AJ4
<74> SML0DATA PCH_SML1ALERT# BD33 GPP_C4/SML0DATA PCH_JTAG_TMS AH3 XDP_TMS <6,79>
GPP_B23/SML1ALERT#/PCHHOT# PCH_JTAG_TDO XDP_TDO <6>
SML1CLK BF27 AH2
+RTC_CELL BE27 GPP_C6/SML1CLK PCH_JTAG_TDI AJ3 XDP_TDI <6,79>
SML1DATA 4 OF 13
GPP_C7/SML1DATA PCH_JTAG_TCK XDP_TCK1 <79>
RH83 1 2 20K_0402_5%~D PCH_SRTCRST# CNP-H_BGA874 Rev1.0

@
1
CH52 +3VS
1U_0603_10V6K~D
2 +3V_PCH

HDA_SPKR RH600 1 @ 2 100K_0402_5%


RH63 1 @ 2 150K_0402_1% PCH_SML1ALERT#

Top Swap Override


+RTC_CELL
This signal has an internal pull-down. 0 = Disable Top Swap mode (Default)
PCH_RTCRST# 0 = Disable IntelR DCI-OOB (Default) 1 = Enable Top Swap mode.
1 = Enable IntelR DCI-OOB
RH84 1 2 20K_0402_5%~D
The internal Pull-down is disabled af t er PCH P WR OK i s hi gh.
1. The internal pull-down is disabled after RSMRST# de-asserts.
CLRP1 in DIMM door
1
2. When used as PCHHOT# and strap low, a 150K
1

pull-up is needed to ensure it does not override the


CH53 CLRP1

internal pull-down strap sampling.


1U_0603_10V6K~D SHORT PADS
B 2 B
2

+3VS
+3VALW

1
@

1
RH2 RH5
10K_0402_5% 1K_0402_5%

+3V_PCH +3VS

2
2
PBTN_OUT# SYS_RESET#
RH460 1 2 1K_0402_5% SML1CLK

RH461 1 2 1K_0402_5% SML1DATA

0.1U_0402_10V
CH174
1

+3VS 0.1U_0402_10V @
2

CH175
SML1CLK 6 1 +1.8VALW +3VALW
EC_SMB_CK2 <37,58,63,74,77>
2

RH501 1 2 499_0402_1% SML0CLK

2
QH5A
RH502 1 2 499_0402_1% SML0DATA DMN66D0LDW-7
5

RH463 1 2 1K_0402_5% PCH_SMBCLK SML1DATA 3 4


EC_SMB_DA2 <37,58,63,74,77>

1
RH462 1 2 1K_0402_5% PCH_SMBDATA QH5B RH1027 RH1026
DMN66D0LDW-7 10K_0402_5% 10K_0402_5%

RH88 1 2 10K_0402_5% EC_RSMRST#

2
A A

2
G
SUSACK# 3 1 PCH_PWR_EN
PCH_PWR_EN <12,58,78,88,98>

D
QH1
MESS138W-G_SOT323-3

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/03/29 2019/03/29
PCH (2/7) PM,HDA,SMB,JTAG
Issued Date Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 12 of 101
5 4 3 2 1
5 4 3 2 1

UH1

S IC A31 FHSSKU04 QNDQ A1 BGA 874P PCH-H


SA0000B4I0L
CPCHES@

D D
UH1 CNP-H
UH1C
AR2 G36
CL_CLK PCIE9_RXN PCIE_PRX_DTX_N9 <68>
AT5 F36

M.2 SSD Slot#1


CL_DATA PCIE9_RXP PCIE_PTX_DRX_N9 PCIE_PRX_DTX_P9 <68>
AU4 C34 0.22U_0201_6.3V 2 1 CH202
CL_RST# PCIE9_TXN PCIE_PTX_DRX_P9 PCIE_PTX_C_DRX_N9 <68>
D34 0.22U_0201_6.3V 2 1 CH203

PCIe/SATA
PCIE9_TXP PCIE_PTX_C_DRX_P9 <68>
S IC A31 FHZ390 QQLP B0 BGA 874P PCH-H P48
GPP_K8
SA0000C500L V47
<87> XMP1 GPP_K9
CPCHQS@ V48 K37
<87> XMP2 GPP_K10 PCIE10_RXN PCIE_PRX_DTX_N10 <68>
W47 J37
GPP_K11 PCIE10_RXP PCIE_PTX_DRX_N10 PCIE_PRX_DTX_P10 <68>
C35 0.22U_0201_6.3V 2 1 CH204
PCIE10_TXN PCIE_PTX_DRX_P10 PCIE_PTX_C_DRX_N10 <68>
L47 B35 0.22U_0201_6.3V 2 1 CH205
GPP_K0 PCIE10_TXP PCIE_PTX_C_DRX_P10 <68>
L46

LAN
U48 GPP_K1 F44
GPP_K2 PCIE15_RXN/SATA2_RXN PCIE_PRX_DTX_N15 <51>
U47 E45
GPP_K3 PCIE15_RXP/SATA2_RXP PCIE_PRX_DTX_P15 <51>
N48 B40
GPP_K4 PCIE_15_SATA_2_TXN PCIE_PTX_DRX_N15 <51>
N47 C40
GPP_K5 PCIE15_TXP/SATA2_TXP PCIE_PTX_DRX_P15 <51>
P47

WLAN
R46 GPP_K6 L41
GPP_K7 PCIE16_RXN/SATA3_RXN PCIE_PRX_DTX_N16 <52>
M40

M.2 SSD Slot#2


PCIE_PTX_DRX_P11 PCIE16_RXP/SATA3_RXP PCIE_PRX_DTX_P16 <52>
0.22U_0201_6.3V 2 1 CH206 C36 B41
<68> PCIE_PTX_C_DRX_P11 PCIE_PTX_DRX_N11 PCIE11_TXP/SATA0A_TXP PCIE16_TXN/SATA3_TXN PCIE_PTX_DRX_N16 <52>
0.22U_0201_6.3V 2 1 CH207 B36 C41

PCIe/SATA
<68> PCIE_PTX_C_DRX_N11 PCIE11_TXN/SATA0A_TXN PCIE16_TXP/SATA3_TXP PCIE_PTX_DRX_P16 <52>
F39
<68> PCIE_PRX_DTX_P11 PCIE11_RXP/SATA0A_RXP
G38 K43
<68> PCIE_PRX_DTX_N11 PCIE11_RXN/SATA0A_RXN PCIE17_RXN/SATA4_RXN PCIE_PRX_DTX_N17 <68>
K44

M.2 SSD Slot#1


PCIE17_RXP/SATA4_RXP PCIE_PTX_DRX_N17 PCIE_PRX_DTX_P17 <68>
AR42 A42 0.22U_0201_6.3V 2 1 CH210
GPP_F10/SATA_SCLOCK PCIE17_TXN/SATA4_TXN PCIE_PTX_DRX_P17 PCIE_PTX_C_DRX_N17 <68>
AR48 B42 0.22U_0201_6.3V 2 1 CH211

PCIe/SATA
GPP_F11/SATA_SLOAD PCIE17_TXP/SATA4_TXP PCIE_PTX_C_DRX_P17 <68>
AU47
AU46 GPP_F13/SATA_SDATAOUT0 P41
GPP_F12/SATA_SDATAOUT1 PCIE18_RXN/SATA5_RXN PCIE_PRX_DTX_N18 <68>
R40
PCIE18_RXP/SATA5_RXP PCIE_PTX_DRX_N18 PCIE_PRX_DTX_P18 <68>
C39 C42 0.22U_0201_6.3V 2 1 CH212
PCIE14_TXN/SATA1B_TXN PCIE18_TXN/SATA5_TXN PCIE_PTX_DRX_P18 PCIE_PTX_C_DRX_N18 <68>
D39 D42 0.22U_0201_6.3V 2 1 CH213
PCIE14_TXP/SATA1B_TXP PCIE18_TXP/SATA5_TXP PCIE_PTX_C_DRX_P18 <68>
D46
C47 PCIE14_RXN/SATA1B_RXN AK48 PCH_SATADET#
PCIE14_RXP/SATA1B_RXP GPP_E8/SATA_LED# PCH_SATADET# <67>

SATA HDD
C
CH227 1 2 0.01U_0201_16V7 SATA_PTX_DRX_N0 B38 AH41 C
<67> SATA_PTX_C_DRX_N0 SATA_PTX_DRX_P0 PCIE13_TXN/SATA0B_TXN GPP_E0/SATAXPCIE0/SATAGP0 SATA_GP0 <67>
CH228 1 2 0.01U_0201_16V7 C38 AJ43
<67> SATA_PTX_C_DRX_P0 SATA_PRX_DTX_N0 PCIE13_TXP/SATA0B_TXP GPP_E1/SATAXPCIE1/SATAGP1 SATA_GP1 <68>
CH229 1 2 0.01U_0201_16V7 C45 AK47 +3VS
<67> SATA_PRX_C_DTX_N0 SATA_PRX_DTX_P0 PCIE13_RXN/SATA0B_RXN GPP_E2/SATAXPCIE2/SATAGP2
CH230 1 2 0.01U_0201_16V7 C46 AN47

M.2 SSD Slot#2


<67> SATA_PRX_C_DTX_P0 PCIE13_RXP/SATA0B_RXPGPP_F0/SATAXPCIE3/SATAGP_3 AM46
PCIE_PTX_DRX_P12 GPP_F1/SATAXPCIE4/SATAGP4 SATA_GP4 <68>
0.22U_0201_6.3V 2 1 CH208 E37 AM43

PCIe/SATA
<68> PCIE_PTX_C_DRX_P12 PCIE_PTX_DRX_N12 PCIE12_TXP/SATA1A_TXP GPP_F2/SATAXPCIE5/SATAGP5 PCH_SATADET#
0.22U_0201_6.3V 2 1 CH209 D38 AM47 1 2
<68> PCIE_PTX_C_DRX_N12 PCIE12_TXN/SATA1A_TXN GPP_F3/SATAXPCIE6/SATAGP6
J41 AM48 RH512 10K_0402_5%
<68> PCIE_PRX_DTX_P12 PCIE12_RXP/SATA_1A_RXP GPP_F4/SATAXPCIE7/SATAGP7
H42
<68> PCIE_PRX_DTX_N12 PCIE12_RXN/SATA1A_RXN AU48
0.22U_0201_6.3V 2 1 CH217 PCIE_PTX_DRX_P20 B44 GPP_F21/EDP_BKLTCTL AV46

M.2 SSD Slot#1


<68> PCIE_PTX_C_DRX_P20 PCIE_PTX_DRX_N20 PCIE20_TXP/SATA7_TXP GPP_F20/EDP_BKLTEN
0.22U_0201_6.3V 2 1 CH216 A44 AV44
<68> PCIE_PTX_C_DRX_N20 PCIE20_TXN/SATA7_TXN GPP_F19/EDP_VDDEN
R37

PCIe/SATA
<68> PCIE_PRX_DTX_P20 PCIE20_RXP/SATA7_RXP H_THERMTRIP#_R
R35 AD3 RH79 1 2 620_0402_5%
<68> PCIE_PRX_DTX_N20 PCIE_PTX_DRX_P19 PCIE20_RXN/SATA7_RXN THRMTRIP# H_THERMTRIP# <6>
0.22U_0201_6.3V 2 1 CH215 D43 AF2
<68> PCIE_PTX_C_DRX_P19 PCIE_PTX_DRX_N19 PCIE19_TXP/SATA6_TXP PECI H_PM_SYNC H_PECI <6>
0.22U_0201_6.3V 2 1 CH214 C44 AF3 RH15 1 2 30_0402_5%
<68> PCIE_PTX_C_DRX_N19 PCIE19_TXN/SATA6_TXN PM_SYNC H_PM_SYNC_R <6>
N42 AG5
<68> PCIE_PRX_DTX_P19 PCIE19_RXP/SATA6_RXP 3 OF 13 PLTRST_CPU# CPU_PLTRST# <6>
M44 AE2
<68> PCIE_PRX_DTX_N19 PCIE19_RXN/SATA6_RXN PM_DOWN H_PM_DOWN <6>
CNP-H_BGA874 Rev1.0

1
@
RH14
12.1_0402_1%

2
B B
+3VS
CNP-H
UH1E
AL13 CPU_DP1_CTRL_CLK
GPP_I5/DDPB_CTRLCLK AR8 CPU_DP1_CTRL_DATA
AT6 GPP_I6/DDPB_CTRLDATA AN13 CPU_DP2_CTRL_CLK PCH_DP3_CTRL_DATA 2.2K_0402_5% 2 1 RH601
<42> CPU_DP1_HPD GPP_I0/DDPB_HPD0/DISP_MISC0 GPP_I7/DDPC_CTRLCLK CPU_DP2_CTRL_DATA
AN10 AL10
<42> CPU_DP2_HPD GPP_I1/DDPC_HPD1/DISP_MISC1 GPP_I8/DDPC_CTRLDATA PCH_DP4_CTRL_DATA
AP9 AL9 2.2K_0402_5% 2 1 RH602
AL15 GPP_I2/DPPD_HPD2/DISP_MISC2 GPP_I9/DDPD_CTRLCLK AR3 PCH_DP3_CTRL_DATA
GPP_I3/DPPE_HPD3/DISP_MISC3 GPP_I10/DDPD_CTRLDATA AN40 PCH_DP4_CTRL_DATA
GPP_F23/DDPF_CTRLDATA AT49
GPP_F22/DDPF_CTRLCLK CPU_DP1_CTRL_CLK 2.2K_0402_5% 2 1 RH604
AP41
GPP_F14/PS_ON# PROC_DETECT# <6> CPU_DP1_CTRL_DATA RH605
AN6 2.2K_0402_5% 2 1
GPP_I4/EDP_HPD/DISP_MISC4
M45 CPU_DP2_CTRL_CLK 2.2K_0402_5% 2 1 RH607
GPP_K23/IMGCLKOUT1 STRAP3_PCH <37>
L48
GPP_K22/IMGCLKOUT0 STRAP5_PCH <37> CPU_DP2_CTRL_DATA
T45 2.2K_0402_5% 2 1 RH606
1

RH9 GPP_K21 T46


DDP[B..F]CTRLDATA
100K_0402_5% 5 OF 13 GPP_K20 AJ47
GPP_H23/TIME_SYNC0
This signal has a weak internal Pull-down.
0 = Port B~D is not detected.
CNP-H_BGA874 Rev1.0
2

1 = Port B,C,D is detected. (Default)


@

Notes:
1. The internal Pull-down is disabled after
PCH_PWROK de-asserts.
2. This signal is in the primary well.

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/03/29 2019/03/29
PCH (3/7) SATA,DDC,PCIE
Issued Date Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 13 of 101
5 4 3 2 1
5 4 3 2 1

CNP-H

JUSB1 (Left) side (Power Share,Debug Port)


UH1B
K34 J3

JUSB2 (Right)
<7> DMI_CTX_PRX_N0 J35 DMI0_RXN USB2N_1 J2 USB20_N1 <71>
<7> DMI_CTX_PRX_P0 DMI0_RXP USB2P_1 USB20_P1 <71>
C33 N13

Caldera
<7> DMI_CRX_PTX_N0 B33 DMI0_TXN USB2N_2 N15 USB20_N2 <72>
<7> DMI_CRX_PTX_P0 G33 DMI0_TXP USB2P_2 K4 USB20_P2 <72>
<7> DMI_CTX_PRX_N1 USB20_N3 <74>

AlienFX/ELC
F34 DMI1_RXN USB2N_3 K3
<7> DMI_CTX_PRX_P1 C32 DMI1_RXP USB2P_3 M10 USB20_P3 <74>
<7> DMI_CRX_PTX_N1 DMI1_TXN USB2N_4 USB20_N4 <62>
B32 L9
<7> DMI_CRX_PTX_P1 K32 DMI1_TXP USB2P_4 M1 USB20_P4 <62>

Touch screen
<7> DMI_CTX_PRX_N2 J32 DMI2_RXN USB2N_5 L2
<7> DMI_CTX_PRX_P2 DMI2_RXP USB2P_5
D C31 K7 D

Digital camera
<7> DMI_CRX_PTX_N2 B31 DMI2_TXN USB2N_6 K6 USB20_N6 <37>
<7> DMI_CRX_PTX_P2 DMI2_TXP USB2P_6 USB20_P6 <37>
G30 L4

JUSB3 (Right)
<7> DMI_CTX_PRX_N3 F30 DMI3_RXN USB2N_7 L3 USB20_N7 <37>
<7> DMI_CTX_PRX_P3 C29 DMI3_RXP USB2P_7 G4 USB20_P7 <37>
<7> DMI_CRX_PTX_N3 USB20_N8 <72>

Tobii (17" only)


B29 DMI3_TXN USB2N_8 G5
<7> DMI_CRX_PTX_P3 A25 DMI3_TXP USB2P_8 M6 USB20_P8 <72>
USB20_N9 <75>

Per key
B25 DMI7_TXP USB2N_9 N8
P24 DMI7_TXN USB2P_9 H3 USB20_P9 <75>
DMI7_RXP USB2N_10 USB20_N10 <63>

Thunderbolt PD
R24 H2
DMI7_RXN USB2P_10 USB20_P10 <63>
C26 R10
B26 DMI6_TXP USB2N_11 P9 USB20_N11 <44>
DMI6_TXN USB2P_11 USB20_P11 <44> +3V_PCH
F26 G1
G26 DMI6_RXP USB2N_12 G2
B27 DMI6_RXN USB2P_12 N3 10K_8P4R_5%

BT
C27 DMI5_TXP USB2N_13 N2 USB_OC0# 4 5
L26 DMI5_TXN USB2P_13 E5 USB_OC1# 3 6
DMI5_RXP USB2N_14 USB20_N14 <52> USB_OC3#
M26 F6 2 7
D29 DMI5_RXN USB2P_14 USB20_P14 <52> USB_OC2# 1 8
E28 DMI4_TXP AH36 USB_OC0#
DMI4_TXN GPP_E9/USB2_OC0# USB_OC1# USB_OC0# <71> RPH6
K29 AL40
M29 DMI4_RXP GPP_E10/USB2_OC1# AJ44 USB_OC2# USB_OC1# <72>
DMI4_RXN GPP_E11/USB2_OC2# AL41 USB_OC3#

Right JUSB2
G17 GPP_E12/USB2_OC3# AV47
<72> USB3_PRX_DTX_N7 F16 PCIE1_RXN/USB31_7_RXN GPP_F15/USB2_OC4# AR35
<72> USB3_PRX_DTX_P7 PCIE1_RXP/USB31_7_RXP GPP_F16/USB2_OC5#
A17 AR37

USB2_COMP
<72> USB3_PTX_DRX_N7 B17 PCIE1_TXN/USB31_7_TXN GPP_F17/USB2_OC6# AV43
<72> USB3_PTX_DRX_P7 PCIE1_TXP/USB31_7_TXP GPP_F18/USB2_OC7#
R21

Caldera Trace Width = 5 mils


<74> USB3_PRX_DTX_N8 P21 PCIE2_RXN/USB31_8_RXN F4 USB2_COMP 1 2 113_0402_1%
RH109 +3V_PCH
<74> USB3_PRX_DTX_P8 B18 PCIE2_RXP/USB31_8_RXP USB2_COMP F3 1 2 1K_0402_5%
RH580

Trace Spacing to Other Signals = 15 mils


<74> USB3_PTX_DRX_N8 PCIE2_TXN/USB31_8_TXN USB2_VBUSSENSE
C18 U13
<74> USB3_PTX_DRX_P8 K18 PCIE2_TXP/USB31_8_TXP RSVD1 G3 1 2 1K_0402_5%
RH581

Trace Length < 1000 mils


J18 PCIE3_RXN/USB31_9_RXN USB2_ID
PCIE3_RXP/USB31_9_RXP GPD_7

1
B19 BE41 RH594
C19 PCIE3_TXN/USB31_9_TXN GPD7
PCIE3_TXP/USB31_9_TXP PCIE_CTX_C_TRX_P24 100K_0402_5%
N18 G45 CH247 1 2 0.22U_0201_6.3V
R18 PCIE4_RXN/USB31_10_RXN PCIE24_TXP G46 PCIE_CTX_C_TRX_N24 1 2 PCIE_CTX_TRX_P24 <45>
CH248 0.22U_0201_6.3V
PCIE4_RXP/USB31_10_RXP PCIE24_TXN PCIE_CRX_C_TTX_P24 PCIE_CTX_TRX_N24 <45>
D20 Y41 CH249 1 2 0.22U_0201_6.3V GPD_7
PCIE_CRX_C_TTX_N24 PCIE_CRX_TTX_P24 <45>

2
C20 PCIE4_TXN/USB31_10_TXN PCIE24_RXP Y40 CH250 1 2 0.22U_0201_6.3V
F20 PCIE4_TXP/USB31_10_TXP PCIE24_RXN G48 PCIE_CTX_C_TRX_P23 1 2 PCIE_CRX_TTX_N24 <45>
CH251 0.22U_0201_6.3V
PCIE5_RXN PCIE23_TXP PCIE_CTX_C_TRX_N23 PCIE_CTX_TRX_P23 <45>
G20 G49 CH252 1 2 0.22U_0201_6.3V
PCIE5_RXP PCIE23_TXN PCIE_CRX_C_TTX_P23 PCIE_CTX_TRX_N23 <45>

1
B21 W44 CH253 1 2 0.22U_0201_6.3V RH11

Thunderbolt
PCIE5_TXN PCIE23_RXP PCIE_CRX_C_TTX_N23 PCIE_CRX_TTX_P23 <45>
A22 W43 CH254 1 2 0.22U_0201_6.3V 10K_0402_5%
K21 PCIE5_TXP PCIE23_RXN H48 PCIE_CTX_C_TRX_P22 1 2 PCIE_CRX_TTX_N23 <45>
CH255 0.22U_0201_6.3V @
J21 PCIE6_RXN PCIE22_TXP H47 PCIE_CTX_C_TRX_N22 1 2 PCIE_CTX_TRX_P22 <45>
CH256 0.22U_0201_6.3V
PCIE6_RXP PCIE22_TXN PCIE_CRX_C_TTX_P22 PCIE_CTX_TRX_N22 <45>
D21 U41 CH257 1 2 0.22U_0201_6.3V

2
C21 PCIE6_TXN PCIE22_RXP U40 PCIE_CRX_C_TTX_N22 1 2 PCIE_CRX_TTX_P22 <45>
CH258 0.22U_0201_6.3V
PCIE6_TXP PCIE22_RXN PCIE_CTX_C_TRX_P21 PCIE_CRX_TTX_N22 <45>
B23 F46 CH259 1 2 0.22U_0201_6.3V
C23 PCIE7_TXP PCIE21_TXP G47 PCIE_CTX_C_TRX_N21 1 2 PCIE_CTX_TRX_P21 <45>
CH260 0.22U_0201_6.3V

X'tal Input:
J24 PCIE7_TXN PCIE21_TXN R44 PCIE_CRX_C_TTX_P21 1 2 PCIE_CTX_TRX_N21 <45>
CH261 0.22U_0201_6.3V
PCIE7_RXP PCIE21_RXP PCIE_CRX_C_TTX_N21 PCIE_CRX_TTX_P21 <45>
C L24 T43 CH262 1 2 0.22U_0201_6.3V C

High: Differential
F24 PCIE7_RXN PCIE21_RXN PCIE_CRX_TTX_N21 <45>
G24 PCIE8_RXN

Low: Single ended


B24 PCIE8_RXP
C24 PCIE8_TXN 2 OF 13
PCIE8_TXP
CNP-H_BGA874 Rev1.0

nVidia GPU_ID N17_ID1 N17_ID0 RH25 N17EG3@ RH27 N17EG3@

N17EG3 H H
N17EG2 H L
N17EG1 L H S RES 1/20W 10K +-5% 0201 S RES 1/20W 10K +-5% 0201
SD043100280 SD043100280
N17PG1 L L
RH25 N17EG2@ RH28 N17EG2@

+3V_PCH +3V_PCH S RES 1/20W 10K +-5% 0201 S RES 1/20W 10K +-5% 0201
SD043100280 SD043100280
BOARD_ID 1 2 10K_0201_5% N17_ID1 1 2 10K_0201_5%
RH21 RH25 @ RH26 N17EG1@ RH27 N17EG1@
RH26 1 @ 2 10K_0201_5%

N17_ID0 1 2 10K_0201_5%
RH27 @
RH28 1 @ 2 10K_0201_5%
+3VS S RES 1/20W 10K +-5% 0201 S RES 1/20W 10K +-5% 0201
+3VALW @GSYNC@ SD043100280 SD043100280
GSYNC_ID 1 2 10K_0201_5%
RH29
1 2 8.2K_0402_5% BT_OFF# 1 2 8.2K_0402_5% BT_OFF# 1 2 10K_0201_5%
RH517 @ RH706 @ RH30
@NGSYNC@
1 2 8.2K_0402_5% W L_OFF# 1 2 8.2K_0402_5% W L_OFF#
RH520 @ RH707 @

1 2 10K_0402_5% EC_SCI#
RH521
+3VS
2 1 49.9K_0402_1% UART_2_PRXD_DTXD
RC62 CNP- H
UH1K
2 1 49.9K_0402_1% UART_2_PTXD_DRXD
B RC63 RPC7 B
BBS_BIT0 BA26 BA20 BOARD_ID I2C_0_SDA 1 8
BD30 GPP_B22/GSPI1_MOSI GPP_D9/ISH_SPI_CS#/GSPI2_CS0# BB20 DGPU_HOLD_RST# I2C_0_SCL 2 7
<62> ELC_RESET EC_SCI# AU26 GPP_B21/GSPI1_MISO GPP_D10/ISH_SPI_CLK/GSPI2_CLK BB16 PEX_RST# DGPU_HOLD_RST# <37> I2C2_SDA 3 6
1 2 10K_0402_5% DGPU_PW ROK <58> EC_SCI# VROM_SEL AW26 GPP_B20/GSPI1_CLK GPP_D11/ISH_SPI_MISO/GP_BSSB_CLK/GSPI2_MISO AN18 DGPU_PW R_EN PEX_RST# <37> I2C2_SCL 4 5
RH516 @
GPP_B19/GSPI1_CS0# GPP_D12/ISH_SPI_MOSI/GP_BSSB_DI/GSPI2_MOSI DGPU_PW R_EN <58>
1 2 10K_0402_5% VROM_SEL NRB_BIT BE30 BF14 N17_ID1
RH588 @ 10K_0804_8P4R_5%
BD29 GPP_B18/GSPI0_MOSI GPP_D16/ISH_UART0_CTS#/CNV_WCEN AR18 N17_ID0
<62> ELC_BOOT_MODE BF29 GPP_B17/GSPI0_MISO GPP_D15/ISH_UART0_RTS#/GSPI2_CS1#/CNV_WFEN BF17 I2C2_SCL
<37> GC6_FB_EN BB26 GPP_B16/GSPI0_CLK GPP_D14/ISH_UART0_TXD/I2C2_SCL BE17 I2C2_SDA I2C2_SCL <66> +3VS
<37> GC6_EVENT# GPP_B15/GSPI0_CS0# GPP_D13/ISH_UART0_RXD/I2C2_SDA I2C2_SDA <66>
BB24
1 2 10K_0402_5% VROM_SEL BE23 GPP_C9/UART0A_TXD
RH589 @
To G+Gyro sensor
W L_OFF# AP24 GPP_C8/UART0A_RXD
<52> W L_OFF# BT_OFF# BA24 GPP_C11/UART0A_CTS# DGPU_PW R_EN 1 2 10K_0201_5%
RH537
<52> BT_OFF# GPP_C10/UART0A_RTS# AG45
BD21 GPP_H20/ISH_I2C0_SCL AH46 ISH_I2C0_SCL <66>
<37> HDMI_HPD_PCH GPP_C15/UART1_CTS#/ISH_UART1_CTS# GPP_H19/ISH_I2C0_SDA ISH_I2C0_SDA <66>
AW24
+5VALW <37> DP_HPD_PCH GPP_C14/UART1_RTS#/ISH_UART1_RTS#
RT694 1 RTD3@ 2 0_0201_5% AP21 AH47
<42> TBT_PCIE_W AKE_N AU24 GPP_C13/UART1_TXD/ISH_UART1_TXD GPP_H22/ISH_I2C1_SCL AH48 ISH_I2C1_SCL <66> +3V_PCH
<42> TBT_RTD3_RST# GPP_C12/UART1_RXD/ISH_UART1_RXD GPP_H21/ISH_I2C1_SDA ISH_I2C1_SDA <66>
JW DB AV21
<42> TBT_CIO_PLUG_EVENT# GPP_C23/UART2_CTS#
1 AW21
UART_2_PTXD_DRXD 2 1 UART_2_PTXD_DRXD BE20 GPP_C22/UART2_RTS# AV34 PCH_ACC1_INT1
UART_2_PRXD_DTXD 3 2 5 <52> UART_2_PTXD_DRXD UART_2_PRXD_DTXD BD20 GPP_C21/UART2_TXD GPP_A23/ISH_GP5 AW32 PCH_GYRO_INT2 PCH_ACC1_INT1 <66>
3 G1 <52> UART_2_PRXD_DTXD GPP_C20/UART2_RXD GPP_A22/ISH_GP4 PCH_GYRO_INT2 <66>
4 6 BA33 CLKDET# RH558 1 @ 2 10K_0201_5%
4 G2 BE21 GPP_A21/ISH_GP3 BE34
<42> RTD3_USB_PW R_EN GPP_C19/I2C1_SCL GPP_A20/ISH_GP2 ISH_GP1
ACES_88266-04001 BF21 BD34
<42> RTD3_CIO_PWR_EN I2C_0_SCL BC22 GPP_C18/I2C1_SDA GPP_A19/ISH_GP1 BF35 ISH_GP1 <58>
CONN@ CLKDET#
<63> I2C_0_SCL I2C_0_SDA BF23 GPP_C17/I2C0_SCL GPP_A18/ISH_GP0 BD38 DGPU_PRSNT#
<63> I2C_0_SDA GPP_C16/I2C0_SDA GPP_A17/SD_VDD1_PWR_EN#/ISH_GP7
BE15
<58,63> TP_INT# DGPU_PW ROK GPP_D4/ISH_I2C2_SDA/I2C3_SDA/SBK4_BK4
BE14 11 OF 13
GPP_D23/ISH_I2C2_SCL/I2C3_SCL

2
@
CNP-H_BGA874 Rev1.0 RH135 +3V_PCH
@ 10K_0402_5%
BBS_BIT0 2 1 4.7K_0402_5%~D
RH130 @

1
Boot BIOS Strap Bit (internal PD)
HIGH LPC
LOW(DEFAULT) SPI

+3V_PCH

NRB_BIT 2 1 4.7K_0402_5%~D
A RH524 @ A

NO REBOOT mode (internal PD)


HIGH Enable
LOW(DEFAULT) Disable

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/03/29 2019/03/29
PCH (4/7) DMI,PCIE,USB,I2C
Issued Date Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 14 of 101
5 4 3 2 1
5 4 3 2 1

+1.8VALW

@ RH181 1 2 20K_0402_1% CNV_BRI_PRX_DTX

@ RH182 1 2 20K_0402_1% CNV_RGI_PRX_DTX CNP-H


UH1M
@ RH180 1 2 10K_0402_5% CPU_VCCIO_PWR_GATE#
AW13 BD4
1 2 4.7K_0402_5% CNV_BRI_PTX_DRX BE9 GPP_G0/SD_CMD CNV_WR_CLKN BE3 CLK_CNV_PRX_DTX_N <52>
RH603
GPP_G1/SD_DATA0 CNV_WR_CLKP CLK_CNV_PRX_DTX_P <52>
BF8
D
BF9 GPP_G2/SD_DATA1 BB3 D

575179_Intel_Pulsar_CNVio_Schematic_Checklist_Rev3.1 BG8 GPP_G3/SD_DATA2 CNV_WR_D0N BB4 CNV_PRX_DTX_N0 <52>


GPP_G4/SD_DATA3 CNV_WR_D0P CNV_PRX_DTX_P0 <52>
BE8 BA3
BD8 GPP_G5/SD_CD# CNV_WR_D1N BA2 CNV_PRX_DTX_N1 <52>
GPP_G6/SD_CLK CNV_WR_D1P CNV_PRX_DTX_P1 <52>
AV13
GPP_G7/SD_WP BC5
AP3 CNV_WT_CLKN BB6 CLK_CNV_PTX_DRX_N <52>
+1.8V_PRIM GPP_I11/M2_SKT2_CFG0 CNV_WT_CLKP CLK_CNV_PTX_DRX_P <52>
AP2
AN4 GPP_I12/M2_SKT2_CFG1 BE6
GPP_I13/M2_SKT2_CFG2 CNV_WT_D0N CNV_PTX_DRX_N0 <52>
AM7 BD7
GPP_I14/M2_SKT2_CFG3 CNV_WT_D0P CNV_PTX_DRX_P0 <52>
BG6
AV6 CNV_WT_D1N BF6 CNV_PTX_DRX_N1 <52>
GPP_J0/CNV_PA_BLANKING CNV_WT_D1P CNV_PTX_DRX_P1 <52>
RH219 1 2 20K_0402_1% CNV_RGI_PTX_DRX_R CPU_VCCIO_PWR_GATE# AY3 BA1 CNV_WT_RCOMP RH213 1 2 150_0402_1%
AR13 GPP_J1/CPU_C10_GATE# CNV_WT_RCOMP
@ RH220 1 2 10K_0402_5% AV7 GPP_J11/A4WP_PRESENT B12 PCIE_RCOMPN RH193 1 2 100_0402_1%
AW3 GPP_J10 PCIE_RCOMPN A13 PCIE_RCOMPP
AT10 GPP_J_2 PCIE_RCOMPP BE5 SD_RCOMP_1P8 RH214 1 2 200_0402_1%
An external pull-high or pull-down is required RH1021 1 2 0_0201_5% CNV_BRI_PTX_DRX AV4 GPP_J_3 SD_1P8_RCOMP BE4 SD_RCOMP_3P3 RH215 1 2 200_0402_1%
<52> CNV_BRI_PTX_DRX_R CNV_BRI_PRX_DTX AY2 GPP_J4/CNV_BRI_DT/UART0B_RTS# SD_3P3_RCOMP BD1
<52> CNV_BRI_PRX_DTX CNV_RGI_PTX_DRX GPP_J5/CNV_BRI_RSP/UART0B_RXD GPPJ_RCOMP_1P81
0 = Intergrated CNVi enable
RH200 1 2 0_0201_5% BA4 BE1
<52> CNV_RGI_PTX_DRX_R CNV_RGI_PRX_DTX GPP_J6/CNV_RGI_DT/UART0B_TXD GPPJ_RCOMP_1P82 GPPJ_RCOMP_1P8
1 = Intergrated CNVi disable
AV3 BE2 RH216 1 2 200_0402_1%
<52> CNV_RGI_PRX_DTX AW2 GPP_J7/CNV_RGI_RSP/UART0B_CTS# GPPJ_RCOMP_1P83
GPP_J9 AU9 GPP_J8/CNV_MFUART2_RXD Y35
GPP_J9/CNV_MFUART2_TXD RSVD2 Y36
RSVD3
BC1 T372 PAD~D @
RSVD1

#571483_CFL_H_RVP_CRB_TDK_Rev0p7
13 OF 13 AL35 T135 PAD~D @
TP

Recommend external test point


CNP-H_BGA874 Rev1.0

@
+1.8V_PRIM

RH218 2 @ 1 10K_0402_5% GPP_J9


C C

The signal has a weak internal pull-down


0 = VCCPSPI is connected to 3.3V rail
1 = VCCPSPI is connected to 1.8V rail
Note: If VCCPSPI is connected to 1.8V rail, this pin
strap must be a 1 for the proper functionality
PCH_RTCX1

of the SPI (Flash) I/Os CNP-H


UH1G RH70
BE33 10M_0402_5%
GPP_A16/CLKOUT_48 1 2 PCH_RTCX2
PCH_XDP_CLK_N

Net : XCLK_BIASREF
D7 Y3 T49 PAD~D TP@
<6> CPU_24MHZ_P C6 CLKOUT_CPUNSSC_P CLKOUT_ITPXDP# Y4 PCH_XDP_CLK_P T50 PAD~D TP@
<6> CPU_24MHZ_N CLKOUT_CPUNSSC# CLKOUT_ITPXDP_P

Trace Width/Space: 15mil /15 mil


YH1
B8 B6 32.768KHZ_X1A000141000300
<6> PCH_CPU_BCLK_P CLKOUT_CPUBCLK_P CLKOUT_CPUPCIBCLK# PCH_CPU_PCIBCLK_N <6>

Max Trace Length: 1000 mil


C8 A6
<6> PCH_CPU_BCLK_N CLKOUT_CPUBCLK# CLKOUT_CPUPCIBCLK_P PCH_CPU_PCIBCLK_P <6>
1 2
XTAL24_OUT U9 AJ6
+1VALW XTAL24_IN XTAL_OUT CLKOUT_PCIE_N0 CLK_PEG_N0 <37>
U10 AJ7
XTAL_IN CLKOUT_PCIE_P0 CLK_PEG_P0 <37>
XCLK_BIASREF 1 1
RH71 1 @ 2 2.7K_0402_1% T3 AH9 CH45 CH46
XCLK_BIASREF CLKOUT_PCIE_N1 CLK_PCIE_N1 <68> 10P_0402_50V8J 10P_0402_50V8J
AH10
1 2 XCLK_BIASREF PCH_RTCX1 BA49 CLKOUT_PCIE_P1 CLK_PCIE_P1 <68>
RH590 60.4_0402_1% PCH_RTCX2 BA48 RTCX1 AE14 2 2
RTCX2 CLKOUT_PCIE_N2 AE15 CLK_PCIE_N2 <68>

PEG(dGPU)
+3VS CLKOUT_PCIE_P2 CLK_PCIE_P2 <68>
BF31
<37> CLKREQ_PEG#0 GPP_B5/SRCCLKREQ0#
RP3 BE31 AE6

SSD1
4 5 CLKREQ_PEG#0 <68> CLKREQ_PCIE#1 AR32 GPP_B6/SRCCLKREQ1# CLKOUT_PCIE_N3 AE7 CLK_PCIE_N3 <45>
CLKREQ_PCIE#1 <68> CLKREQ_PCIE#2 GPP_B7/SRCCLKREQ2# CLKOUT_PCIE_P3 CLK_PCIE_P3 <45>
3 6 BB30

SSD2
2 7 CLKREQ_PCIE#2 <42> CLKREQ_PCIE#3 BA30 GPP_B8/SRCCLKREQ3# AC2 EMI@
CLKREQ_PCIE#4 <51> CLKREQ_PCIE#4 GPP_B9/SRCCLKREQ4# CLKOUT_PCIE_N4 CLK_PCIE_N4 <51>
1 8 AN29 AC3 RH91
<52> CLKREQ_PCIE#5 CLK_PCIE_P4 <51>

Thunderbolt
AE47 GPP_B10/SRCCLKREQ5# CLKOUT_PCIE_P4 33_0201_5%
<58,74> CLKREQ_PEG#6 AC48 GPP_H0/SRCCLKREQ6# AB2
10K_0804_8P4R_5%
GPP_H1/SRCCLKREQ7# CLKOUT_PCIE_N5 CLK_PCIE_N5 <52> XTAL24_IN_R XTAL24_IN

LAN
+3VS AE41 AB3 1 2
AF48 GPP_H2/SRCCLKREQ8# CLKOUT_PCIE_P5 CLK_PCIE_P5 <52>
CLKREQ_PEG#6 GPP_H3/SRCCLKREQ9#

WLAN
RP5 1 2 10K_0201_5% AC41 W4
B CLKREQ_PCIE#5 GPP_H4/SRCCLKREQ10# CLKOUT_PCIE_N6 CLK_PEG_N6 <74> B
RP8 1 2 10K_0201_5% AC39 W3 RH72
FFS_INT2 GPP_H5/SRCCLKREQ11# CLKOUT_PCIE_P6 CLK_PEG_P6 <74>

Caldera
RP9 1 2 10K_0201_5% AE39 1M_0402_5%~D
FFS_INT1 FFS_INT2 <11,67> GPP_H6/SRCCLKREQ12# XTAL24_OUT_R XTAL24_OUT
RP10 1 2 10K_0201_5% AB48 W7 1 2 1 2
FFS_INT1 <11,67> AC44 GPP_H7/SRCCLKREQ13# CLKOUT_PCIE_N7 W6
AC43 GPP_H8/SRCCLKREQ14# CLKOUT_PCIE_P7 EMI@
GPP_H9/SRCCLKREQ15# AC14 YH2 RH92
V2 CLKOUT_PCIE_N8 AC15 24MHZ 12PF +-10PPM 7M24090001 33_0201_5%
V3 CLKOUT_PCIE_N15 CLKOUT_PCIE_P8
CLKOUT_PCIE_P15 U2 1 3
T2 CLKOUT_PCIE_N9 U3 2 4
T1 CLKOUT_PCIE_N14 CLKOUT_PCIE_P9 1 1
CLKOUT_PCIE_P14 AC9 CH47 CH48
AA1 CLKOUT_PCIE_N10 AC11 15P_0402_50V 15P_0402_50V
Y2 CLKOUT_PCIE_N13 CLKOUT_PCIE_P10
CLKOUT_PCIE_P13 2 2
AE9
AC7 CLKOUT_PCIE_N11 AE11
AC6 CLKOUT_PCIE_N12 CLKOUT_PCIE_P11 RN117
CLKOUT_PCIE_P12 7 OF 13 R6 REFCLK_CNV_H CNVI@ 1 2 REFCLK_CNV
CLKIN_XTAL REFCLK_CNV <52>
0_0201_5%
CNP-H_BGA874 Rev1.0

@ RH628 2 1 10K_0402_5%

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/03/29 2019/03/29
PCH (5/7) CNVI, CLK
Issued Date Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 15 of 101
5 4 3 2 1
5 4 3 2 1

+VCCRTCEXT

+1VALW +3V_PCH
CNP-H
UH1H 2
AA22 AW9
AA23 VCCPRIM_1P051 VCCPRIM_3P32
VCCPRIM_1P052

0.1U_0402_10V7K
CH264
AB20 BF47
VCCPRIM_1P053 DCPRTC1 +VCCRTCEXT 1
AB22 BG47
AB23 VCCPRIM_1P054 DCPRTC2
AB27 VCCPRIM_1P055 V23
D
AB28 VCCPRIM_1P056 VCCPRIM_3P35 D
AB30 VCCPRIM_1P057 AN44
AD20 VCCPRIM_1P058 VCCSPI
AD23 VCCPRIM_1P059 BC49
+1V_MPHY VCCPRIM_1P0510 VCCRTC1 +RTC_CELL
+1VALW AD27 BD49 1 2
AD28 VCCPRIM_1P0511 VCCRTC2 CH226 0.1U_0402_10V7K +1.8V_PRIM
AD30 VCCPRIM_1P0512 AN21
RH12 1 2 0_0805_5% AF23 VCCPRIM_1P0513 VCCPGPPG_3P3 AY8
AF27 VCCPRIM_1P0516 VCCPRIM_3P33 BB7
AF30 VCCPRIM_1P0517 VCCPRIM_3P34
VCCPRIM_1P0518 AC35
U26 VCCPGPPHK1 AC36
U29 VCCPRIM_1P0523 VCCPGPPHK2 AE35
V25 VCCPRIM_1P0524 VCCPGPPEF1 AE36
+1VALW V27 VCCPRIM_1P0525 VCCPGPPEF2
V28 VCCPRIM_1P0526 AN24 +3VALW
V30 VCCPRIM_1P0527 VCCPGPPD AN26
+1VALW V31 VCCPRIM_1P0528 VCCPGPPBC1 AP26
VCCPRIM_1P0529 VCCPGPPBC2 +3V_PCH
AD31 AN32
VCCPRIM_1P0514 VCCPGPPA
AE17 AT44
+1VALW VCCPRIM_1P0515 VCCPRIM_3P31 BE48 RH6 1 @ 2 0_0402_5%
W22 VCCDSW_3P31 BE49 RH7 1 2 0_0402_5%
W23 VCCDUSB_1P051 VCCDSW_3P32
+1V_MPHY VCCDUSB_1P052 BB14
BG45 VCCHDA AG19
VCCDSW_1P051 VCCPRIM_1P83

2.2P_0402_50V8
BG46 AG20 2 1
W31 VCCDSW_1P052 VCCPRIM_1P84 AN15 +1.8V_PRIM +1.8VALW
VCCPRIM_MPHY_1P05 VCCPRIM_1P85

CH231
AR15
VCCPRIM_1P86

0.1U_0402_10V7K
CH245
D1 BB11 1 2
LH2 E1 VCCPRIM_1P0521 VCCPRIM_1P87 1 2
+1.05V_XTAL +1.05V_VCCAMPHYPLL 1 2 +1.05V_VCCAMPHYPLL C49 VCCPRIM_1P0522 AF19 RH599
2.2UH_FCI1608F_10% D49 VCCAMPHYPLL_1P051 VCCPRIM_1P81 AF20 RH598 1 @ 2 0_0402_5% 0_0402_5%
VCCAMPHYPLL_1P052 VCCPRIM_1P82 +1.8V_PRIM
E49
LH1 VCCAMPHYPLL_1P053
1 1 AG31
+1.05V_XTAL VCCPRIM_1P0520 +1VALW
CH56 CH263 1 2 P2 AF31
47U_0805_6.3V6M 47U_0805_6.3V6M 2.2UH_FCI1608F_10% P3 VCCA_XTAL_1P051 VCCPRIM_1P0519 AK22
C +1.24V_DPHY C
W19 VCCA_XTAL_1P052 VCCPRIM_1P241 AK23
2 2 W20 VCCA_SRC_1P051 VCCPRIM_1P242
VCCA_SRC_1P052 AJ22
C1 VCCDPHY_1P241 AJ23
C2 VCCAPLL_1P054 VCCDPHY_1P242 BG5
VCCAPLL_1P055 VCCDPHY_1P243 +1.24V_DPHY

Close to P2, P3 Close to C49, D49, E49


V19
VCCA_BCLK_1P05 K47
B1 VCCMPHY_SENSE K46
VCCAPLL_1P051 VSSMPHY_SENSE 1

4.7U_0402_6.3V6M
B2
B3 VCCAPLL_1P052 8 OF 13
VCCAPLL_1P053

CH36
CNP-H_BGA874 Rev1.0 2
@

9/11:change from SE000000K80 to SE00000UC00*2


9/12:change from SE000000I10 to SE00000M000*2
+1V_MPHY +1VALW +1V_MPHY +1VALW +1.8V_PRIM +3V_PCH +3V_PCH
22U_0603_6.3V6M

22U_0603_6.3V6M

1 1 1 1 1 1 1 1 1 1 1 1 1 1

0.1U_0402_10V7K

0.1U_0402_10V7K
1U_0201_6.3V6M
CH82 SE00000UC00

1U_0201_6.3V6M
CH83 SE00000UC00

CH189

CH181

1U_0201_6.3V6M
CH180 SE00000UC00

1U_0201_6.3V6M
CH183 SE00000UC00

1U_0201_6.3V6M
CH187 SE00000UC00

1U_0201_6.3V6M
CH184 SE00000UC00

1U_0201_6.3V6M
CH188 SE00000UC00

1U_0201_6.3V6M
CH185 SE00000UC00

1U_0201_6.3V6M
CH177 SE00000UC00

1U_0201_6.3V6M
CH176 SE00000UC00

CH190

CH192
2 2 2 2 2 2 2 2 2 2 2 2 2 2

B B

Close to B1,B2,B3,C1,C2 Close to U26,U29V25,V27,V28,V30,V31 Close to C49,D49,E49 Close to AF31,AG31,AD31,AA22,AA23 Close to AG19,AG20 Close to AE35,AE36 Close to AC35,AC36
,AB20,AB22,AB23,AB27,AB28,AB30 ,AR15,AN15,BB11
,AD20,AD23,AD27,AD28,AD30,AF23
,AF27,AF30,AE17

+3V_PCH +3V_PCH +RTC_CELL +1.8V_PRIM


1U_0603_10V6K

0.1U_0402_10V7K

4.7U_0603_6.3V6M

1 1 1 1 1 1
0.1U_0402_10V7K

@
CH182

1U_0201_6.3V6M
CH81 SE00000UC00

1U_0201_6.3V6M
CH80 SE00000UC00

CH173

CH233
CH186

2 2 2 2 2 2

A A

Close to AY8,BB7 Close to BE48,BE49 Close to BC49,BD49 Close to AG19,AG20


,AR15,AN15,BB11

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/03/29 2019/03/29
PCH (6/7) PWR
Issued Date Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 16 of 101
5 4 3 2 1
5 4 3 2 1

D D

CNP-H
UH1L
CNP-H
UH1I BG3 M24
A2 AL12 BG33 VSS VSS M32
A28 VSS VSS AL17 BG37 VSS VSS M34
A3 VSS VSS AL21 BG4 VSS VSS M49 CNP-H
A33 VSS VSS AL24 BG48 VSS VSS M5 UH1J
A37 VSS VSS AL26 C12 VSS VSS N12 Y14
A4 VSS VSS AL29 C25 VSS VSS N16 RSVD7 Y15
A45 VSS VSS AL33 C30 VSS VSS N34 RSVD8 U37
A46 VSS VSS AL38 C4 VSS VSS N35 RSVD6 U35
A47 VSS VSS AM1 C48 VSS VSS N37 RSVD5
A48 VSS VSS AM18 C5 VSS VSS N38 N32
A5 VSS VSS AM32 D12 VSS VSS P26 RSVD3 R32
A8 VSS VSS AM49 D16 VSS VSS P29 RSVD4
AA19 VSS VSS AN12 D17 VSS VSS P4 AH15
AA20 VSS VSS AN16 D30 VSS VSS P46 RSVD2 AH14
AA25 VSS VSS AN34 D33 VSS VSS R12 RSVD1
AA27 VSS VSS AN38 D8 VSS VSS R16
AA28 VSS VSS AP4 E10 VSS VSS R26
AA30 VSS VSS AP46 E13 VSS VSS R29 AL2
AA31 VSS VSS AR12 E15 VSS VSS R3 PREQ# AM5 XDP_PREQ# <6,79>
AA49 VSS VSS AR16 E17 VSS VSS R34 PRDY# AM4 XDP_PRDY# <6,79>
AA5 VSS VSS AR34 E19 VSS VSS R38 CPU_TRST# AK3 CPU_XDP_TRST# <6,79>
AB19 VSS VSS AR38 E22 VSS VSS R4 TRIGGER_OUT AK2 PCH_TRIGGER <10>
AB25 VSS VSS AT1 E24 VSS VSS T17 TRIGGER_IN CPU_TRIGGER <10>
AB31 VSS VSS AT16 E26 VSS VSS T18 10 OF 13
AC12 VSS VSS AT18 E31 VSS VSS T32 CNP-H_BGA874 Rev1.0
C AC17 VSS VSS AT21 E33 VSS VSS T4 C
VSS VSS VSS VSS @
AC33 AT24 E35 T49
AC38 VSS VSS AT26 E40 VSS VSS T5
AC4 VSS VSS AT29 E42 VSS VSS T7
AC46 VSS VSS AT32 E8 VSS VSS U12
AD1 VSS VSS AT34 F41 VSS VSS U15
AD19 VSS VSS AT45 F43 VSS VSS U17
AD2 VSS VSS AV11 F47 VSS VSS U21
AD22 VSS VSS AV39 G44 VSS VSS U24
AD25 VSS VSS AW10 G6 VSS VSS U33
AD49 VSS VSS AW4 H8 VSS VSS U38
AE12 VSS VSS AW40 J10 VSS VSS V20
AE33 VSS VSS AW46 J26 VSS VSS V22
AE38 VSS VSS B47 J29 VSS VSS V4
AE4 VSS VSS B48 J4 VSS VSS V46
AE46 VSS VSS B49 J40 VSS VSS W25
AF22 VSS VSS BA12 J46 VSS VSS W27
AF25 VSS VSS BA14 J47 VSS VSS W28
AF28 VSS VSS BA44 J48 VSS VSS W30
AG1 VSS VSS BA5 J9 VSS VSS Y10
AG22 VSS VSS BA6 K11 VSS VSS Y12
AG23 VSS VSS BB41 K39 VSS VSS Y17
AG25 VSS VSS BB43 M16 VSS VSS Y33
AG27 VSS VSS BB9 M18 VSS VSS Y38
AG28 VSS VSS BC10 M21 VSS 12 OF 13 VSS Y9
AG30 VSS VSS BC13 VSS VSS
AG49 VSS VSS BC15 CNP-H_BGA874 Rev1.0
AH12 VSS VSS BC19
VSS VSS @
AH17 BC24
AH33 VSS VSS BC26
AH38 VSS VSS BC31
AJ19 VSS VSS BC35
B AJ20 VSS VSS BC40 B
AJ25 VSS VSS BC45
AJ27 VSS VSS BC8
AJ28 VSS VSS BD43
AJ30 VSS VSS BE44
AJ31 VSS VSS BF1
AK19 VSS VSS BF2
AK20 VSS VSS BF3
AK25 VSS VSS BF48
AK27 VSS VSS BF49
AK28 VSS VSS BG17
AK30 VSS VSS BG2
AK31 VSS VSS BG22
AK4 VSS VSS BG25
AK46 VSS 9 OF 13 VSS BG28
VSS VSS
CNP-H_BGA874 Rev1.0

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/03/29 2019/03/29
PCH (7/7) GND
Issued Date Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev

LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 17 of 101
5 4 3 2 1
A B C D E

1 1

2 2

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/03/29 2019/03/29
Reserved
Issued Date Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 18 of 101
A B C D E
A B C D E

1 1

2 2

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/03/29 2019/03/29
Reserved
Issued Date Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 19 of 101
A B C D E
A B C D E

1 1

2 2

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/03/29 2019/03/29
Reserved
Issued Date Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 20 of 101
A B C D E
A B C D E

1 1

2 2

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/03/29 2019/03/29
Reserved
Issued Date Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 21 of 101
A B C D E
A B C D E

1 1

2 2

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/03/29 2019/03/29
Reserved
Issued Date Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 22 of 101
A B C D E
Interleaved
A B C D E

JDIMM1 Layout Note:


Place near JDIMM1
Layout Note: For RF
Place near JDIMM1

10uF*8 +1.2V_DDR
1 +3VS +3VS +3VS +1.2V_DDR 1uF*8 +1.2V_DDR 1
330uF*1 +1.2V_DDR

@RF@

@RF@
0.5P_0402_50V8

10P_0402_50V8J
SA0 SA1 SA2
@ @ 1 1

2
RD1 RD2 RD3 1

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

CH240

CH241
0_0402_5% 0_0402_5% 0_0402_5% 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
+ CD17
2 2

CD1

CD2

CD3

CD4

CD5

CD6

CD7

CD8

1U_0201_6.3V6M
CD9 SE00000UC00

1U_0201_6.3V6M
CD10 SE00000UC00

1U_0201_6.3V6M
CD11 SE00000UC00

1U_0201_6.3V6M
CD12 SE00000UC00

1U_0201_6.3V6M
CD13 SE00000UC00

1U_0201_6.3V6M
CD14 SE00000UC00

1U_0201_6.3V6M
CD15 SE00000UC00

1U_0201_6.3V6M
CD16 SE00000UC00
DIMM1 1 0 0
330U_D2_2VM_R6M
SA0_DIM1 SA1_DIM1 SA2_DIM1
1

1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

DIMM2 0 0 0
@
2

2
RD4 RD5 RD6
0_0402_5% 0_0402_5% 0_0402_5%

DIMM3 1 1 0
1

1
PLACE ALL THE BELOW RESISTORS CLOSE TO SODIMM DIMM4 0 1 0 Layout Note:
PLACE THE CAP WITHIN 200 MILS
FROM THE JDIMM1

2.2uF*1

(4.0 mm) STD


+0.6V_DDR_REFCA_A
0.1uF*1
+1.2V_DDR JDIMM1B +1.2V_DDR
REVERSE
1 2
111 141
VDD1 VDD11
CD18 CD19 112
VDD2 VDD12
142 Layout Note:
117 147
2
0.1U_0402_16V7K
1
2.2U_0402_6.3V6M
118 VDD3 VDD13 148 Place near JDIMM1
123 VDD4 VDD14 153
124 VDD5 VDD15 154 +0.6VS
JDIMM1A VDD6 VDD16
129 159
DDR_A_D0 DDR_A_D[0..7] <8,25> VDD7 VDD17
137 REVERSE 8 130 160
<8> DDR_A_CLK2
139 CK0(T) DQ0 7 DDR_A_D1 135 VDD8 VDD18 163 +0.6VS 10uF*1
2 <8> DDR_A_CLK#2
138 CK0#(C) DQ1 20 DDR_A_D2 136 VDD9 VDD19 +2.5V_MEM 2
<8> DDR_A_CLK3
140 CK1(T) DQ2 21 DDR_A_D3 VDD10 1uF*2
<8> DDR_A_CLK#3 CK1#(C) DQ3 DDR_A_D4 +0.6V_DDR_REFCA_A
4 VDDSPD1 255 258
109 DQ4 3 DDR_A_D5 VDDSPD VTT
<8> DDR_A_CKE2 CKE0 DQ5 DDR_A_D6 1 1 1 1
+3VS

10U_0603_6.3V6M

10U_0603_6.3V6M
110 16 164 257
<8> DDR_A_CKE3 CKE1 DQ6 DDR_A_D7 VREFCA VPP1

1U_0201_6.3V6M
CD21 SE00000UC00

1U_0201_6.3V6M
CD28 SE00000UC00
17 259
DQ7 VPP2

CD20

CD24
149 13
<8> DDR_A_CS#2 S0# DQS0(T) DDR_A_DQS0 <8,25> 2 2 2 2
157 11 1 99
<8> DDR_A_CS#3 S1# DQS0#(C) DDR_A_DQS#0 <8,25> VSS1 VSS48

2
TP_DIMM1_CHA_S2# 162 RD58 2 102
TP_DIMM1_CHA_S3# 165 S2#/C0 DDR_A_D8 DDR_A_D[8..15] <8,25> VSS2 VSS49
TD1 @ 28 0_0603_5% 5 103
TD2 @ S3#/C1 DQ8 29 DDR_A_D9 6 VSS3 VSS50 106
155 DQ9 41 DDR_A_D10 9 VSS4 VSS51 107
<8> DDR_A_ODT2 ODT0 DQ10 DDR_A_D11 VSS5 VSS52
161 42 10 167
<8> DDR_A_ODT3

1
ODT1 DQ11 24 DDR_A_D12 VDDSPD1 14 VSS6 VSS53 168
115 DQ12 25 DDR_A_D13 15 VSS7 VSS54 171
<8,25> DDR_A_BG0 BG0 DQ13 DDR_A_D14 VSS8 VSS55
113 38 18 172
<8,25> DDR_A_BG1 BG1 DQ14 DDR_A_D15 VSS9 VSS56
150 37 1 2 19 175
<8,25> DDR_A_BA0 BA0 DQ15 VSS10 VSS57
145 34 CD22 CD23 22 176
<8,25> DDR_A_BA1 BA1 DQS1(T) DDR_A_DQS1 <8,25> VSS11 VSS58
32 .1U_0402_16V7K 2.2U_0402_6.3V6M 23 180
<8,25> DDR_A_MA[0..13] DDR_A_MA0 DQS1#(C) DDR_A_DQS#1 <8,25> VSS12 VSS59
144 26 181
DDR_A_MA1 A0 DDR_A_D16 DDR_A_D[16..23] <8,25> VSS13 VSS60
DDR_A_MA2
133
A1 DQ16
50
DDR_A_D17
2 1 27
VSS14 VSS61
184 Layout Note:
132 49 30 185
DDR_A_MA3 131 A2 DQ17 62 DDR_A_D18 31 VSS15 VSS62 188 Place near JDIMM1
DDR_A_MA4 128 A3 DQ18 63 DDR_A_D19 35 VSS16 VSS63 189
DDR_A_MA5 126 A4 DQ19 46 DDR_A_D20 36 VSS17 VSS64 192

PLACE NEAR TO PIN


DDR_A_MA6 127 A5 DQ20 45 DDR_A_D21 39 VSS18 VSS65 193
DDR_A_MA7 122 A6 DQ21 58 DDR_A_D22 40 VSS19 VSS66 196
DDR_A_MA8 125 A7 DQ22 59 DDR_A_D23 43 VSS20 VSS67 197 +2.5V_MEM 10uF*1
DDR_A_MA9 121 A8 DQ23 55 44 VSS21 VSS68 201
DDR_A_MA10 146 A9 DQS2(T) 53 DDR_A_DQS2 <8,25>
47 VSS22 VSS69 202 1uF*1
DDR_A_MA11 A10_AP DQS2#(C) DDR_A_DQS#2 <8,25> VSS23 VSS70
120 48 205
DDR_A_MA12 A11 DDR_A_D24 DDR_A_D[24..31] <8,25> VSS24 VSS71
119 70 51 206 1 1
DDR_A_MA13 A12 DQ24 DDR_A_D25 VSS25 VSS72

10U_0603_6.3V6M
158 71 52 209
A13 DQ25 DDR_A_D26 VSS26 VSS73

1U_0201_6.3V6M
CD27 SE00000UC00
151 83 56 210
+1.2V_DDR <8,25> DDR_A_W E# A14_WE# DQ26 DDR_A_D27 +1.2V_DDR VSS27 VSS74

CD25
156 84 57 213
<8,25> DDR_A_CAS# A15_CAS# DQ27 DDR_A_D28 VSS28 VSS75 2 2
152 66 60 214
<8,25> DDR_A_RAS# A16_RAS# DQ28 DDR_A_D29 VSS29 VSS76
67 61 217
114 DQ29 79 DDR_A_D30 64 VSS30 VSS77 218
<8,25> DDR_A_ACT# ACT# DQ30 DDR_A_D31 VSS31 VSS78
80 65 222
DQ31 VSS32 VSS79

1
143 76 RD51 68 223
<8,25> DDR_A_PAR PARITY DQS3(T) DDR_A_DQS3 <8,25> VSS33 VSS80
116 74 470_0402_1% 69 226
<8,25> DDR_A_ALERT# DIMM1_CHA_EVENT# 134 ALERT# DQS3#(C) DDR_A_DQS#3 <8,25> VSS34 VSS81
RD7 1 2 240_0402_1% 72 227
3
DDR_A_DRAMRST# EVENT# DDR_A_D32 DDR_A_D[32..39] <8,25> VSS35 VSS82 3
108 174 73 230
RESET# DQ32 173 DDR_A_D33 77 VSS36 VSS83 231

2
DQ33 187 DDR_A_D34 DDR_A_DRAMRST# 1 2 78 VSS37 VSS84 234
DQ34 DDR_A_D35 H_DRAMRST# <12> VSS38 VSS85
254 186 RD52 0_0402_5% 81 235
<12,24,25,26,63,67> PCH_SMBDATA SDA DQ35 DDR_A_D36 DDR_B_DRAMRST# VSS39 VSS86
253 170 1 2 82 238
<12,24,25,26,63,67> PCH_SMBCLK SCL DQ36 DDR_A_D37 <24,26> DDR_B_DRAMRST# VSS40 VSS87
169 RD62 0_0402_5% 85 239
SA2_DIM1 166 DQ37 183 DDR_A_D38 86 VSS41 VSS88 243
SA1_DIM1 260 SA2 DQ38 182 DDR_A_D39 89 VSS42 VSS89 244
SA0_DIM1 SA1 DQ39 VSS43 VSS90

0.1U_0402_16V7K~D
256 179 1 90 247
DDR_A_DRAMRST# SA0 DQS4(T) DDR_A_DQS4 <8,25> VSS44 VSS91
177 93 248
<25> DDR_A_DRAMRST# DQS4#(C) DDR_A_DQS#4 <8,25> VSS45 VSS92

CD125
@ESD@
94 251
DDR_A_D40 DDR_A_D[40..47] <8,25> VSS46 VSS93
92 195 98 252
CB0_NC DQ40 DDR_A_D41 2 VSS47 VSS94
0.1U_0402_16V7K~D

1 91 194
101 CB1_NC DQ41 207 DDR_A_D42 262 261
CB2_NC DQ42 DDR_A_D43 GND1 GND2
CD134
@ESD@

105 208
88 CB3_NC DQ43 191 DDR_A_D44
2 87 CB4_NC DQ44 190 DDR_A_D45
100 CB5_NC DQ45 203 DDR_A_D46 LOTES_ADDR0205-P001A02~D
104 CB6_NC DQ46 204 DDR_A_D47 CONN@
97 CB7_NC DQ47 200
DQS8(T) DQS5(T) DDR_A_DQS5 <8,25>
95 198
+1.2V_DDR DQS8#(C) DQS5#(C) DDR_A_DQS#5 <8,25>
DDR_A_D48 DDR_A_D[48..55] <8,25> +1.2V_DDR
216
12 DQ48 215 DDR_A_D49
33 DM0#/DBI0# DQ49 228 DDR_A_D50
54 DM1#/DBI1# DQ50 229 DDR_A_D51
75 DM2#/DBI2# DQ51 211 DDR_A_D52

DIMM1/2 Side CPU Side


178 DM3#/DBI3# DQ52 212 DDR_A_D53
199 DM4#/DBI4# DQ53 224 DDR_A_D54
DM5#/DBI5# DQ54 1
2

220 225 DDR_A_D55 CD29


241 DM6#/DBI6# DQ55 221 .1U_0402_16V7K RD8
DM7#/DBI7# DQS6(T) DDR_A_DQS6 <8,25> +0.6V_DDR_REFCA_A +0.6V_VREF_CA
96 219 1K_0402_1%
DM8#/DBI8# DQS6#(C) DDR_A_DQS#6 <8,25> 2
1

DDR_A_D56 DDR_A_D[56..63] <8,25>


237 1 2
DQ56 236 DDR_A_D57 RD9 2_0402_1%
DQ57 DDR_A_D58 1
249
DQ58
2

250 DDR_A_D59 RD10 CD31


DQ59 DDR_A_D60 1
232 1K_0402_1% @ CD30 0.022U_0402_25V7K
DQ60 233 DDR_A_D61 .1U_0402_16V7K 2
4 DQ61 245 DDR_A_D62 4
DQ62
2

246 DDR_A_D63 2 RD11


1

DQ63 242
DDR_A_DQS7 <8,25> 24.9_0402_1%
DQS7(T) 240
DQS7#(C) DDR_A_DQS#7 <8,25>
1

LOTES_ADDR0205-P001A02~D
CONN@

Security Classification
2018/03/29
Compal Secret Data
2019/03/29
Compal Electronics, Inc.
DDR4_DIMM1
Issued Date Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 23 of 101
A B C D E
Interleaved
A B C D E

JDIMM2 Layout Note:


Place near JDIMM3 10uF*8
1uF*8
Layout Note: For RF
Place near JDIMM3
330uF*1

1 +1.2V_DDR +1.2V_DDR +1.2V_DDR 1


+1.2V_DDR
+3VS +3VS +3VS SA0 SA1 SA2

@RF@

@RF@
1

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

0.5P_0402_50V8

10P_0402_50V8J
DIMM1 1 0 0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
@ + CD80
2

CD64

CD65

CD66

CD67

CD68

CD69

CD70

CD71

1U_0201_6.3V6M
CD72 SE00000UC00

1U_0201_6.3V6M
CD73 SE00000UC00

1U_0201_6.3V6M
CD74 SE00000UC00

1U_0201_6.3V6M
CD75 SE00000UC00

1U_0201_6.3V6M
CD76 SE00000UC00

1U_0201_6.3V6M
CD77 SE00000UC00

1U_0201_6.3V6M
CD78 SE00000UC00

1U_0201_6.3V6M
CD79 SE00000UC00

CH236

CH237
RD26 RD27 RD28 330U_D2_2VM_R6M
0_0402_5% 0_0402_5% 0_0402_5%
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

SA0_DIM3 SA1_DIM3 SA2_DIM3 DIMM2 0 0 0


1

1
@ @
DIMM3 1 1 0
2

2
RD29 RD30 RD31
0_0402_5% 0_0402_5% 0_0402_5%

DIMM4 0 1 0
1

1
PLACE ALL THE BELOW RESISTORS CLOSE TO SODIMM

Layout Note:

(8.0 mm) RVS


PLACE THE CAP WITHIN 200 MILS
FROM THE JDIMM3 +1.2V_DDR JDIMM2B +1.2V_DDR
REVERSE
111 141
VDD1 VDD11
112
VDD2 VDD12
142 Layout Note:
117 147
VDD3 VDD13 Place near JDIMM3
+0.6V_DDR_REFCA_B
2.2uF*1 118
VDD4 VDD14
148
123 153
0.1uF*1 124 VDD5 VDD15 154 +0.6VS
JDIMM2A VDD6 VDD16
1 2 129 159
DDR_B_D0 DDR_B_D[0..7] <8,26> VDD7 VDD17
137 REVERSE 8 130 160
<8> DDR_B_CLK2
139 CK0(T) DQ0 7 DDR_B_D1 CD81 CD82 135 VDD8 VDD18 163 +0.6VS 10uF*1
2 <8> DDR_B_CLK#2
138 CK0#(C) DQ1 20 DDR_B_D2 136 VDD9 VDD19 +2.5V_MEM 2
<8> DDR_B_CLK3
140 CK1(T) DQ2 21 DDR_B_D3 2
.1U_0402_16V7K
1
2.2U_0402_6.3V6M
VDD10 1uF*2
<8> DDR_B_CLK#3 CK1#(C) DQ3 DDR_B_D4 +0.6V_DDR_REFCA_B
4 VDDSPD3 255 258
109 DQ4 3 DDR_B_D5 VDDSPD VTT
<8> DDR_B_CKE2 CKE0 DQ5 DDR_B_D6 1 1 1 1

10U_0603_6.3V6M

10U_0603_6.3V6M
110 16 164 257
<8> DDR_B_CKE3 CKE1 DQ6 DDR_B_D7 VREFCA VPP1

1U_0201_6.3V6M
CD84 SE00000UC00

1U_0201_6.3V6M
CD90 SE00000UC00
17 259
DQ7 VPP2

CD83

CD87
149 13
<8> DDR_B_CS#2 S0# DQS0(T) DDR_B_DQS0 <8,26> 2 2 2 2
157 11 1 99
<8> DDR_B_CS#3 TP_DIMM3_CHB_S2# 162 S1# DQS0#(C) DDR_B_DQS#0 <8,26> VSS VSS
2 102
TP_DIMM3_CHB_S3# 165 S2#/C0 DDR_B_D8 DDR_B_D[8..15] <8,26> VSS VSS
TD5 @ 28 5 103
TD6 @ S3#/C1 DQ8 29 DDR_B_D9 +3VS 6 VSS VSS 106
155 DQ9 41 DDR_B_D10 9 VSS VSS 107
<8> DDR_B_ODT2 ODT0 DQ10 DDR_B_D11 VSS VSS
161 42 10 167
<8> DDR_B_ODT3 ODT1 DQ11 DDR_B_D12 VSS VSS
24 14 168
DQ12 VSS VSS

2
115 25 DDR_B_D13 RD60 15 171
<8,26> DDR_B_BG0 BG0 DQ13 DDR_B_D14 VSS VSS
113 38 0_0603_5% 18 172
<8,26> DDR_B_BG1 BG1 DQ14 DDR_B_D15 VSS VSS
150 37 19 175
<8,26> DDR_B_BA0 BA0 DQ15 VSS VSS
145 34 22 176
<8,26> DDR_B_BA1 BA1 DQS1(T) DDR_B_DQS1 <8,26> VSS VSS
32 23 180
<8,26> DDR_B_MA[0..13] DDR_B_DQS#1 <8,26>

1
DDR_B_MA0 144 DQS1#(C) VDDSPD3 26 VSS VSS 181
DDR_B_MA1 A0 DDR_B_D16 DDR_B_D[16..23] <8,26> VSS VSS
DDR_B_MA2
133
A1 DQ16
50
DDR_B_D17
27
VSS VSS
184 Layout Note:
132 49 30 185
DDR_B_MA3 131 A2 DQ17 62 DDR_B_D18 31 VSS VSS 188 Place near JDIMM3
DDR_B_MA4 A3 DQ18 DDR_B_D19 1 2 VSS VSS
128 63 CD85 CD86 35 189
DDR_B_MA5 126 A4 DQ19 46 DDR_B_D20 .1U_0402_16V7K 2.2U_0402_6.3V6M 36 VSS VSS 192
DDR_B_MA6 127 A5 DQ20 45 DDR_B_D21 39 VSS VSS 193
DDR_B_MA7 122 A6 DQ21 58 DDR_B_D22 2 1 40 VSS VSS 196
DDR_B_MA8 125 A7 DQ22 59 DDR_B_D23 43 VSS VSS 197 +2.5V_MEM 10uF*1
DDR_B_MA9 121 A8 DQ23 55 44 VSS VSS 201
DDR_B_MA10 146 A9 DQS2(T) 53 DDR_B_DQS2 <8,26>
47 VSS VSS 202 1uF*1
DDR_B_MA11 A10_AP DQS2#(C) DDR_B_DQS#2 <8,26> VSS VSS
120 48 205

PLACE NEAR TO PIN


DDR_B_MA12 A11 DDR_B_D24 DDR_B_D[24..31] <8,26> VSS VSS
119 70 51 206 1 1
DDR_B_MA13 A12 DQ24 DDR_B_D25 VSS VSS

10U_0603_6.3V6M
158 71 52 209
A13 DQ25 DDR_B_D26 VSS VSS

1U_0201_6.3V6M
CD89 SE00000UC00
151 83 56 210
<8,26> DDR_B_W E# A14_WE# DQ26 DDR_B_D27 VSS VSS

CD88
156 84 57 213
<8,26> DDR_B_CAS# A15_CAS# DQ27 DDR_B_D28 VSS VSS 2 2
152 66 60 214
<8,26> DDR_B_RAS# A16_RAS# DQ28 DDR_B_D29 VSS VSS
67 61 217
114 DQ29 79 DDR_B_D30 64 VSS VSS 218
+1.2V_DDR <8,26> DDR_B_ACT# ACT# DQ30 80 DDR_B_D31 65 VSS VSS 222
143 DQ31 76 68 VSS VSS 223
<8,26> DDR_B_PAR PARITY DQS3(T) DDR_B_DQS3 <8,26> VSS VSS
116 74 69 226
<8,26> DDR_B_ALERT# DIMM3_CHB_EVENT# 134 ALERT# DQS3#(C) DDR_B_DQS#3 <8,26> VSS VSS
RD32 1 2 240_0402_1% 72 227
3
DDR_B_DRAMRST# EVENT# DDR_B_D32 DDR_B_D[32..39] <8,26> VSS VSS 3
108 174 73 230
RESET# DQ32 173 DDR_B_D33 77 VSS VSS 231
DQ33 187 DDR_B_D34 78 VSS VSS 234
254 DQ34 186 DDR_B_D35 81 VSS VSS 235
<12,23,25,26,63,67> PCH_SMBDATA SDA DQ35 DDR_B_D36 VSS VSS
253 170 82 238
<12,23,25,26,63,67> PCH_SMBCLK SCL DQ36 DDR_B_D37 VSS VSS
169 85 239
SA2_DIM3 166 DQ37 183 DDR_B_D38 86 VSS VSS 243
SA1_DIM3 260 SA2 DQ38 182 DDR_B_D39 89 VSS VSS 244
SA0_DIM3 256 SA1 DQ39 179 90 VSS VSS 247
SA0 DQS4(T) DDR_B_DQS4 <8,26> VSS VSS
177 93 248
DQS4#(C) DDR_B_DQS#4 <8,26> VSS VSS
94 251
DDR_B_D40 DDR_B_D[40..47] <8,26> VSS VSS
92 195 98 252
91 CB0_NC DQ40 194 DDR_B_D41 VSS VSS
DDR_B_DRAMRST# 101 CB1_NC DQ41 207 DDR_B_D42 262 261
<23,26> DDR_B_DRAMRST# CB2_NC DQ42 DDR_B_D43 GND GND
105 208
88 CB3_NC DQ43 191 DDR_B_D44
CB4_NC DQ44 DDR_B_D45
0.1U_0402_16V7K~D

1 87 190
100 CB5_NC DQ45 203 DDR_B_D46 LOTES_ADDR0070-P025A~D
CB6_NC DQ46 DDR_B_D47
CD133
@ESD@

104 204 CONN@


97 CB7_NC DQ47 200
2 DQS8(T) DQS5(T) DDR_B_DQS5 <8,26>
95 198
+1.2V_DDR DQS8#(C) DQS5#(C) DDR_B_DQS#5 <8,26>
DDR_B_D48 DDR_B_D[48..55] <8,26>
216
12 DQ48 215 DDR_B_D49 +1.2V_DDR
33 DM0#/DBI0# DQ49 228 DDR_B_D50
54 DM1#/DBI1# DQ50 229 DDR_B_D51
75 DM2#/DBI2# DQ51 211 DDR_B_D52
178 DM3#/DBI3# DQ52 212 DDR_B_D53
199 DM4#/DBI4# DQ53 224 DDR_B_D54

DIMM3/4 Side CPU Side


220 DM5#/DBI5# DQ54 225 DDR_B_D55
241 DM6#/DBI6# DQ55 221
DM7#/DBI7# DQS6(T) DDR_B_DQS6 <8,26> 1
2

96 219 CD131
DM8#/DBI8# DQS6#(C) DDR_B_DQS#6 <8,26> RD55
.1U_0402_16V7K
1K_0402_1% +0.6V_DDR_REFCA_B +0.6V_VREF_DQ
2
DDR_B_D56 DDR_B_D[56..63] <8,26>
237
1

DQ56 236 DDR_B_D57


DQ57 249 DDR_B_D58 1 2
DQ58 250 DDR_B_D59 RD57 2_0402_1%
DQ59 DDR_B_D60 1
232
DQ60
2

233 DDR_B_D61 RD54 CD130


DQ61 DDR_B_D62 1
4 245 1K_0402_1% @ CD132 0.022U_0402_25V7K 4
DQ62 246 DDR_B_D63 .1U_0402_16V7K 2
DQ63 242
DQS7(T) DDR_B_DQS7 <8,26>
2

240 2 RD56
1

DQS7#(C) DDR_B_DQS#7 <8,26>


24.9_0402_1%
1

LOTES_ADDR0070-P025A~D
CONN@

Security Classification
2018/03/29
Compal Secret Data
2019/03/29
Compal Electronics, Inc.
DDR4_DIMM2
Issued Date Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 24 of 101
A B C D E
Interleaved
A B C D E

JDIMM3 Layout Note:


Place near JDIMM2
10uF*8
1uF*8
Layout Note: For RF
Place near JDIMM2

330uF*1
1 +3VS +3VS +3VS +1.2V_DDR +1.2V_DDR +1.2V_DDR +1.2V_DDR 1

SA0 SA1 SA2

@RF@

@RF@
@ @ @
2

2
RD12 RD13 RD14

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

0.5P_0402_50V8

10P_0402_50V8J
DIMM1 1 0 0
0_0402_5% 0_0402_5% 0_0402_5% 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

CD32

CD33

CD34

CD35

CD36

CD37

CD38

CD39

1U_0201_6.3V6M
CD40 SE00000UC00

1U_0201_6.3V6M
CD41 SE00000UC00

1U_0201_6.3V6M
CD42 SE00000UC00

1U_0201_6.3V6M
CD43 SE00000UC00

1U_0201_6.3V6M
CD44 SE00000UC00

1U_0201_6.3V6M
CD45 SE00000UC00

1U_0201_6.3V6M
CD46 SE00000UC00

1U_0201_6.3V6M
CD47 SE00000UC00

CH238

CH239
+ CD48
SA0_DIM2 SA1_DIM2 SA2_DIM2
330U_D2_2VM_R6M
1

1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

DIMM2 0 0 0
2
2

2
RD15 RD16 RD17

DIMM3 1 1 0
0_0402_5% 0_0402_5% 0_0402_5%
1

1
DIMM4 0 1 0
PLACE ALL THE BELOW RESISTORS CLOSE TO SODIMM

(8.0 mm) STD


Layout Note:
PLACE THE CAP WITHIN 200 MILS
FROM THE JDIMM2 Layout Note:
+1.2V_DDR JDIMM3B +1.2V_DDR Place near JDIMM2
REVERSE
111 141
112 VDD1 VDD11 142
VDD2 VDD12
+0.6V_DDR_REFCA_A
2.2uF*1 117
VDD3 VDD13
147
+0.6VS
JDIMM3A 0.1uF*1 118
VDD4 VDD14
148 10uF*1
123 153
137 REVERSE 8 DDR_A_D0 DDR_A_D[0..7] <8,23>
124 VDD5 VDD15 154 +0.6VS 1uF*2
<8> DDR_A_CLK0 CK0(T) DQ0 DDR_A_D1 2 2 VDD6 VDD16
139 7 CD51 129 159
<8> DDR_A_CLK#0 CK0#(C) DQ1 DDR_A_D2 VDD7 VDD17
138 20 .1U_0402_16V7K CD52 130 160 1 1 1 1
<8> DDR_A_CLK1 CK1(T) DQ2 DDR_A_D3 VDD8 VDD18

10U_0603_6.3V6M

10U_0603_6.3V6M
140 21 2.2U_0402_6.3V6M 135 163
<8> DDR_A_CLK#1 CK1#(C) DQ3 DDR_A_D4 1 1 VDD9 VDD19 +2.5V_MEM

1U_0201_6.3V6M
CD50 SE00000UC00

1U_0201_6.3V6M
CD58 SE00000UC00
4 136
2 DQ4 DDR_A_D5 VDD10 2

CD49

CD53
109 3
<8> DDR_A_CKE0 CKE0 DQ5 DDR_A_D6 +0.6V_DDR_REFCA_A 2 2 2 2
110 16 VDDSPD2 255 258
<8> DDR_A_CKE1 CKE1 DQ6 DDR_A_D7 VDDSPD VTT
17
149 DQ7 13 164 257
<8> DDR_A_CS#0 S0# DQS0(T) DDR_A_DQS0 <8,23> VREFCA VPP1
157 11 259
<8> DDR_A_CS#1 TP_DIMM2_CHA_S2# 162 S1# DQS0#(C) DDR_A_DQS#0 <8,23> VPP2
TP_DIMM2_CHA_S3# 165 S2#/C0 DDR_A_D8 DDR_A_D[8..15] <8,23>
TD3 @ 28 1 99
TD4 @ S3#/C1 DQ8 29 DDR_A_D9 2 VSS VSS 102
155 DQ9 41 DDR_A_D10 5 VSS VSS 103
<8> DDR_A_ODT0 ODT0 DQ10 DDR_A_D11 +3VS VSS VSS
161 42 6 106
<8> DDR_A_ODT1 ODT1 DQ11 DDR_A_D12 VSS VSS
24 9 107
115 DQ12 25 DDR_A_D13 10 VSS VSS 167
<8,23> DDR_A_BG0 BG0 DQ13 DDR_A_D14 VSS VSS
113 38 14 168
<8,23> DDR_A_BG1 BG1 DQ14 VSS VSS

2
150 37 DDR_A_D15 RD59 15 171
<8,23> DDR_A_BA0 BA0 DQ15 VSS VSS
145 34 0_0603_5% 18 172
<8,23> DDR_A_BA1 BA1 DQS1(T) DDR_A_DQS1 <8,23> VSS VSS
32 19 175
<8,23> DDR_A_MA[0..13] DDR_A_MA0 DQS1#(C) DDR_A_DQS#1 <8,23> VSS VSS
144 22 176
DDR_A_MA1 A0 DDR_A_D16 DDR_A_D[16..23] <8,23> VSS VSS
133 50 23 180

1
DDR_A_MA2 132 A1 DQ16 49 DDR_A_D17 VDDSPD2 26 VSS VSS 181
DDR_A_MA3 131 A2 DQ17 62 DDR_A_D18 27 VSS VSS 184
DDR_A_MA4 A3 DQ18 DDR_A_D19 VSS VSS
DDR_A_MA5
128
A4 DQ19
63
DDR_A_D20
30
VSS VSS
185 Layout Note:
126 46 31 188
DDR_A_MA6 127 A5 DQ20 45 DDR_A_D21 CD54
1 2
CD55 35 VSS VSS 189 Place near JDIMM2
DDR_A_MA7 122 A6 DQ21 58 DDR_A_D22 .1U_0402_16V7K 2.2U_0402_6.3V6M 36 VSS VSS 192
DDR_A_MA8 125 A7 DQ22 59 DDR_A_D23 39 VSS VSS 193
DDR_A_MA9 121 A8 DQ23 55 2 1 40 VSS VSS 196
DDR_A_MA10 A9 DQS2(T) DDR_A_DQS2 <8,23> VSS VSS
146 53 43 197
DDR_A_MA11 120 A10_AP DQS2#(C) DDR_A_DQS#2 <8,23>
44 VSS VSS 201 +2.5V_MEM 10uF*1
DDR_A_MA12 A11 DDR_A_D24 DDR_A_D[24..31] <8,23> VSS VSS
119 70 47 202
DDR_A_MA13 158 A12 DQ24 71 DDR_A_D25 48 VSS VSS 205 1uF*1
PLACE NEAR TO PIN
151 A13 DQ25 83 DDR_A_D26 51 VSS VSS 206
<8,23> DDR_A_W E# A14_WE# DQ26 DDR_A_D27 VSS VSS
156 84 52 209 1 1
<8,23> DDR_A_CAS# A15_CAS# DQ27 DDR_A_D28 VSS VSS

10U_0603_6.3V6M
152 66 56 210
<8,23> DDR_A_RAS# A16_RAS# DQ28 DDR_A_D29 VSS VSS

1U_0201_6.3V6M
CD59 SE00000UC00
67 57 213
DQ29 DDR_A_D30 VSS VSS

CD56
114 79 60 214
+1.2V_DDR <8,23> DDR_A_ACT# ACT# DQ30 80 DDR_A_D31 61 VSS VSS 217 2 2
143 DQ31 76 64 VSS VSS 218
<8,23> DDR_A_PAR PARITY DQS3(T) DDR_A_DQS3 <8,23> VSS VSS
116 74 65 222
<8,23> DDR_A_ALERT# DIMM2_CHA_EVENT# ALERT# DQS3#(C) DDR_A_DQS#3 <8,23> VSS VSS
RD18 1 2 134 68 223
EVENT# DDR_A_D32 DDR_A_D[32..39] <8,23> VSS VSS
240_0402_1% 108 174 69 226
<23> DDR_A_DRAMRST# RESET# DQ32 DDR_A_D33 VSS VSS
173 72 227
DQ33 187 DDR_A_D34 73 VSS VSS 230
3 3
254 DQ34 186 DDR_A_D35 77 VSS VSS 231
<12,23,24,26,63,67> PCH_SMBDATA SDA DQ35 DDR_A_D36 VSS VSS
253 170 78 234
<12,23,24,26,63,67> PCH_SMBCLK SCL DQ36 DDR_A_D37 VSS VSS
169 81 235
SA2_DIM2 166 DQ37 183 DDR_A_D38 82 VSS VSS 238
SA1_DIM2 260 SA2 DQ38 182 DDR_A_D39 85 VSS VSS 239
SA0_DIM2 256 SA1 DQ39 179 86 VSS VSS 243
SA0 DQS4(T) DDR_A_DQS4 <8,23> VSS VSS
177 89 244
DQS4#(C) DDR_A_DQS#4 <8,23> VSS VSS
90 247
DDR_A_D40 DDR_A_D[40..47] <8,23> VSS VSS
92 195 93 248
91 CB0_NC DQ40 194 DDR_A_D41 94 VSS VSS 251
101 CB1_NC DQ41 207 DDR_A_D42 98 VSS VSS 252
105 CB2_NC DQ42 208 DDR_A_D43 VSS VSS
88 CB3_NC DQ43 191 DDR_A_D44 262 261
87 CB4_NC DQ44 190 DDR_A_D45 GND GND
100 CB5_NC DQ45 203 DDR_A_D46
104 CB6_NC DQ46 204 DDR_A_D47
97 CB7_NC DQ47 200 LOTES_ADDR0069-P009A
DQS8(T) DQS5(T) DDR_A_DQS5 <8,23>
95 198 CONN@
+1.2V_DDR DQS8#(C) DQS5#(C) DDR_A_DQS#5 <8,23>
DDR_A_D48 DDR_A_D[48..55] <8,23>
216
12 DQ48 215 DDR_A_D49
33 DM0#/DBI0# DQ49 228 DDR_A_D50
54 DM1#/DBI1# DQ50 229 DDR_A_D51
75 DM2#/DBI2# DQ51 211 DDR_A_D52
178 DM3#/DBI3# DQ52 212 DDR_A_D53
199 DM4#/DBI4# DQ53 224 DDR_A_D54
220 DM5#/DBI5# DQ54 225 DDR_A_D55
241 DM6#/DBI6# DQ55 221
DM7#/DBI7# DQS6(T) DDR_A_DQS6 <8,23>
96 219
DM8#/DBI8# DQS6#(C) DDR_A_DQS#6 <8,23>

DDR_A_D56 DDR_A_D[56..63] <8,23>


237
DQ56 236 DDR_A_D57
DQ57 249 DDR_A_D58
DQ58 250 DDR_A_D59
DQ59 232 DDR_A_D60
DQ60 233 DDR_A_D61
DQ61 245 DDR_A_D62
DQ62 246 DDR_A_D63
DQ63 242
DQS7(T) DDR_A_DQS7 <8,23>
4 240 4
DQS7#(C) DDR_A_DQS#7 <8,23>

LOTES_ADDR0069-P009A
CONN@

need to change footprint


Security Classification
2018/03/29
Compal Secret Data
2019/03/29
Compal Electronics, Inc.
DDR4_DIMM3
Issued Date Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 25 of 101
A B C D E
Interleaved
A B C D E

JDIMM4 Layout Note:


Place near JDIMM4 10uF*8
1uF*8
Layout Note: For RF
Place near JDIMM4
330uF*1

1 +3VS +3VS +3VS +1.2V_DDR +1.2V_DDR +1.2V_DDR +1.2V_DDR 1

SA0 SA1 SA2

@RF@

@RF@
@ @
2

2
RD38 RD39 RD40

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

0.5P_0402_50V8

10P_0402_50V8J
DIMM1 1 0 0
0_0402_5% 0_0402_5% 0_0402_5% 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

CD94

CD95

CD96

CD97

CD98

CD99

CD100

CD101

1U_0201_6.3V6M
CD102 SE00000UC00

1U_0201_6.3V6M
CD103 SE00000UC00

1U_0201_6.3V6M
CD104 SE00000UC00

1U_0201_6.3V6M
CD105 SE00000UC00

1U_0201_6.3V6M
CD106 SE00000UC00

1U_0201_6.3V6M
CD107 SE00000UC00

1U_0201_6.3V6M
CD108 SE00000UC00

1U_0201_6.3V6M
CD109 SE00000UC00

CH234

CH235
+ CD110
SA0_DIM4 SA1_DIM4 SA2_DIM4
330U_D2_2VM_R6M
1

1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

DIMM2 0 0 0
2
@
2

2
RD41 RD42 RD43

DIMM3 1 1 0
0_0402_5% 0_0402_5% 0_0402_5%
1

1
DIMM4 0 1 0
PLACE ALL THE BELOW RESISTORS CLOSE TO SODIMM

(4.0 mm) RVS


Layout Note:
PLACE THE CAP WITHIN 200 MILS
FROM THE JDIMM4 Layout Note:
+1.2V_DDR JDIMM4B +1.2V_DDR Place near JDIMM4
REVERSE
111 141
112 VDD1 VDD11 142
VDD2 VDD12
+0.6V_DDR_REFCA_B
2.2uF*1 117
VDD3 VDD13
147
+0.6VS
0.1uF*1 118
VDD4 VDD14
148 10uF*1
123 153
137
JDIMM4A
REVERSE 8 DDR_B_D0 DDR_B_D[0..7] <8,24>
124 VDD5 VDD15 154 +0.6VS 1uF*2
<8> DDR_B_CLK0 CK0(T) DQ0 DDR_B_D1 2 2 VDD6 VDD16
139 7 CD113 129 159
<8> DDR_B_CLK#0 CK0#(C) DQ1 DDR_B_D2 VDD7 VDD17
138 20 .1U_0402_16V7K CD114 130 160 1 1 1 1
<8> DDR_B_CLK1 CK1(T) DQ2 DDR_B_D3 VDD8 VDD18

10U_0603_6.3V6M

10U_0603_6.3V6M
140 21 2.2U_0402_6.3V6M 135 163
<8> DDR_B_CLK#1 CK1#(C) DQ3 DDR_B_D4 1 1 +0.6V_DDR_REFCA_B VDD9 VDD19 +2.5V_MEM

1U_0201_6.3V6M
CD112 SE00000UC00

1U_0201_6.3V6M
CD119 SE00000UC00
4 136
2 DQ4 DDR_B_D5 VDD10 2

CD111

CD115
109 3
<8> DDR_B_CKE0 CKE0 DQ5 DDR_B_D6 2 2 2 2
110 16 VDDSPD4 255 258
<8> DDR_B_CKE1 CKE1 DQ6 DDR_B_D7 VDDSPD VTT
17
149 DQ7 13 164 257
<8> DDR_B_CS#0 S0# DQS0(T) DDR_B_DQS0 <8,24> VREFCA VPP1
157 11 259
<8> DDR_B_CS#1 TP_DIMM4_CHB_S2# 162 S1# DQS0#(C) DDR_B_DQS#0 <8,24> VPP2
TP_DIMM4_CHB_S3# 165 S2#/C0 DDR_B_D8 DDR_B_D[8..15] <8,24>
TD7 @ 28 1 99
TD8 @ S3#/C1 DQ8 29 DDR_B_D9 2 VSS1 VSS48 102
155 DQ9 41 DDR_B_D10 +3VS 5 VSS2 VSS49 103
<8> DDR_B_ODT0 ODT0 DQ10 DDR_B_D11 VSS3 VSS50
161 42 6 106
<8> DDR_B_ODT1 ODT1 DQ11 DDR_B_D12 VSS4 VSS51
24 9 107
115 DQ12 25 DDR_B_D13 10 VSS5 VSS52 167
<8,24> DDR_B_BG0 BG0 DQ13 VSS6 VSS53

2
113 38 DDR_B_D14 RD61 14 168
<8,24> DDR_B_BG1 BG1 DQ14 DDR_B_D15 VSS7 VSS54
150 37 0_0603_5% 15 171
<8,24> DDR_B_BA0 BA0 DQ15 VSS8 VSS55
145 34 18 172
<8,24> DDR_B_BA1 BA1 DQS1(T) DDR_B_DQS1 <8,24> VSS9 VSS56
32 19 175
<8,24> DDR_B_MA[0..13] DDR_B_MA0 DQS1#(C) DDR_B_DQS#1 <8,24> VSS10 VSS57
144 22 176

1
DDR_B_MA1 A0 DDR_B_D16 DDR_B_D[16..23] <8,24> VSS11 VSS58
133 50 VDDSPD4 23 180
DDR_B_MA2 132 A1 DQ16 49 DDR_B_D17 26 VSS12 VSS59 181
DDR_B_MA3 131 A2 DQ17 62 DDR_B_D18 27 VSS13 VSS60 184
DDR_B_MA4 A3 DQ18 DDR_B_D19 VSS14 VSS61
DDR_B_MA5
128
A4 DQ19
63
DDR_B_D20 1 2 30
VSS15 VSS62
185 Layout Note:
126 46 31 188
DDR_B_MA6 127 A5 DQ20 45 DDR_B_D21
CD116
.1U_0402_16V7K
CD117
2.2U_0402_6.3V6M 35 VSS16 VSS63 189 Place near JDIMM4
DDR_B_MA7 122 A6 DQ21 58 DDR_B_D22 36 VSS17 VSS64 192
DDR_B_MA8 125 A7 DQ22 59 DDR_B_D23 2 1 39 VSS18 VSS65 193
DDR_B_MA9 121 A8 DQ23 55 40 VSS19 VSS66 196
DDR_B_MA10 A9 DQS2(T) DDR_B_DQS2 <8,24> VSS20 VSS67
146 53 43 197
DDR_B_MA11 120 A10_AP DQS2#(C) DDR_B_DQS#2 <8,24>
44 VSS21 VSS68 201 +2.5V_MEM 10uF*1
DDR_B_MA12 A11 DDR_B_D24 DDR_B_D[24..31] <8,24> VSS22 VSS69
119 70 47 202

PLACE NEAR TO PIN


DDR_B_MA13 158 A12 DQ24 71 DDR_B_D25 48 VSS23 VSS70 205 1uF*1
151 A13 DQ25 83 DDR_B_D26 51 VSS24 VSS71 206
<8,24> DDR_B_W E# A14_WE# DQ26 DDR_B_D27 VSS25 VSS72
156 84 52 209 1 1
<8,24> DDR_B_CAS# A15_CAS# DQ27 DDR_B_D28 VSS26 VSS73

10U_0603_6.3V6M
152 66 56 210
<8,24> DDR_B_RAS# A16_RAS# DQ28 DDR_B_D29 VSS27 VSS74

1U_0201_6.3V6M
CD120 SE00000UC00
67 57 213
DQ29 DDR_B_D30 VSS28 VSS75

CD118
114 79 60 214
+1.2V_DDR <8,24> DDR_B_ACT# ACT# DQ30 80 DDR_B_D31 61 VSS29 VSS76 217 2 2
143 DQ31 76 64 VSS30 VSS77 218
<8,24> DDR_B_PAR PARITY DQS3(T) DDR_B_DQS3 <8,24> VSS31 VSS78
116 74 65 222
<8,24> DDR_B_ALERT# DIMM4_CHB_EVENT# ALERT# DQS3#(C) DDR_B_DQS#3 <8,24> VSS32 VSS79
RD44 1 2 240_0402_1% 134 68 223
EVENT# DDR_B_D32 DDR_B_D[32..39] <8,24> VSS33 VSS80
108 174 69 226
<23,24> DDR_B_DRAMRST# RESET# DQ32 DDR_B_D33 VSS34 VSS81
173 72 227
DQ33 187 DDR_B_D34 73 VSS35 VSS82 230
3 3
254 DQ34 186 DDR_B_D35 77 VSS36 VSS83 231
<12,23,24,25,63,67> PCH_SMBDATA SDA DQ35 DDR_B_D36 VSS37 VSS84
253 170 78 234
<12,23,24,25,63,67> PCH_SMBCLK SCL DQ36 DDR_B_D37 VSS38 VSS85
169 81 235
SA2_DIM4 166 DQ37 183 DDR_B_D38 82 VSS39 VSS86 238
SA1_DIM4 260 SA2 DQ38 182 DDR_B_D39 85 VSS40 VSS87 239
SA0_DIM4 256 SA1 DQ39 179 86 VSS41 VSS88 243
SA0 DQS4(T) DDR_B_DQS4 <8,24> VSS42 VSS89
177 89 244
DQS4#(C) DDR_B_DQS#4 <8,24> VSS43 VSS90
90 247
DDR_B_D40 DDR_B_D[40..47] <8,24> VSS44 VSS91
92 195 93 248
91 CB0_NC DQ40 194 DDR_B_D41 94 VSS45 VSS92 251
101 CB1_NC DQ41 207 DDR_B_D42 98 VSS46 VSS93 252
105 CB2_NC DQ42 208 DDR_B_D43 VSS47 VSS94
88 CB3_NC DQ43 191 DDR_B_D44 262 261
87 CB4_NC DQ44 190 DDR_B_D45 GND1 GND2
100 CB5_NC DQ45 203 DDR_B_D46
104 CB6_NC DQ46 204 DDR_B_D47 LOTES_ADDR0206-P001A02~D
97 CB7_NC DQ47 200
DQS8(T) DQS5(T) DDR_B_DQS5 <8,24> CONN@
95 198
+1.2V_DDR DQS8#(C) DQS5#(C) DDR_B_DQS#5 <8,24>
DDR_B_D48 DDR_B_D[48..55] <8,24>
216
12 DQ48 215 DDR_B_D49
33 DM0#/DBI0# DQ49 228 DDR_B_D50
54 DM1#/DBI1# DQ50 229 DDR_B_D51
75 DM2#/DBI2# DQ51 211 DDR_B_D52
178 DM3#/DBI3# DQ52 212 DDR_B_D53
199 DM4#/DBI4# DQ53 224 DDR_B_D54
220 DM5#/DBI5# DQ54 225 DDR_B_D55
241 DM6#/DBI6# DQ55 221
DM7#/DBI7# DQS6(T) DDR_B_DQS6 <8,24>
96 219
DM8#/DBI8# DQS6#(C) DDR_B_DQS#6 <8,24>

DDR_B_D56 DDR_B_D[56..63] <8,24>


237
DQ56 236 DDR_B_D57
DQ57 249 DDR_B_D58
DQ58 250 DDR_B_D59
DQ59 232 DDR_B_D60
DQ60 233 DDR_B_D61
DQ61 245 DDR_B_D62
DQ62 246 DDR_B_D63
DQ63 242
DQS7(T) DDR_B_DQS7 <8,24>
4 240 4
DQS7#(C) DDR_B_DQS#7 <8,24>

LOTES_ADDR0206-P001A02~D
CONN@

Security Classification
2018/03/29
Compal Secret Data
2019/03/29
Compal Electronics, Inc.
DDR4_DIMM4
Issued Date Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 26 of 101
A B C D E
5 4 3 2 1

D D

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/03/29 2019/03/29 Title

Reversed
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 27 of 101
5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/03/29 2019/03/29 Title

Reversed
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 28 of 101
5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/03/29 2019/03/29 Title

Reversed
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 29 of 101
5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/03/29 2019/03/29 Title

Reversed
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 30 of 101
5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/03/29 2019/03/29 Title

Reversed
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 31 of 101
5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/03/29 2019/03/29 Title

Reversed
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 32 of 101
5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/03/29 2019/03/29 Title

Reversed
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 33 of 101
5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/03/29 2019/03/29 Title

Reversed
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 34 of 101
5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/03/29 2019/03/29 Title

Reversed
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 35 of 101
5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/03/29 2019/03/29 Title

Reversed
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 36 of 101
5 4 3 2 1
5 4 3 2 1

+5VS

+5VS +3VS 40mil(1A)


JDG

.1U_0402_16V7K
1 1
1 2 CLIP2
2

0.1U_0402_16V7K

10U_0805_6.3V6M

10U_0603_6.3V6M

0.1U_0402_10V6K

CE61
1 1 1 1 1 1 3
3 1

82P_0402_50V8J
@RF@ CV957

82P_0402_50V8J
@RF@ CV956
4
4 5 2
5 EMIST_SQ-42G-2_1P

CV805

CV806

CV902

CV903
D 6 D
2 2 2 2 2 2 6 CONN@ JFC
7
7 8 1
8 9 2 1

470P_0402_50V7K
470P_0402_50V7K
9 <63> HEAD_LED_R_DRV# 2
10 3
10 +PWR_SRC 1 1 <63> HEAD_LED_G_DRV#
4 3

EMI@ CV24
EMI@ CV23
<63> HEAD_LED_B_DRV# 4
5
ACES_50293-0107N-P02 5
100mil(2.5A, 5VIA) CONN@ 2 2 +LCDVDD 6
7 6
8 7
9 8
+LCDVDD 9

2 DP channels from GPU


10
10

+3VS

10U_0603_6.3V6M
11

( A & B & EDP)


PTH1

0.1U_0402_10V7K
1 1 12
PTH2

CV1084

CV1085
CVILUX CI1110M2VR0-NH 10P
2 2 CONN@
1 1
X-Beam I/per pin=0.5A CV21
4.7U_0805_10V4Z
CV19
0.1U_0402_10V7K
I/per connector=0.75A
Place close to JFC pin 8~10
2 2

Close to JDGFF1 pin H7


JDGFF1
JDGFF2
H1 A1
<56> MIC_CLK H1 P P A1 PEG_CRX_C_GTX_P7
H2 A2 <7> PEG_CRX_GTX_P7 CV64 1 2 0.22U_0402_6.3V7K H1 A1 PEG_CTX_C_GRX_P3 <7>
<56> MIC_DATA12 H2 N N A2 PEG_CRX_C_GTX_N7 H1 P P A1
H3 A3 <7> PEG_CRX_GTX_N7 CV1086 1 2 0.22U_0402_6.3V7K H2 A2 PEG_CTX_C_GRX_N3 <7>
H4 H3 G G A3 A4 H3 H2 N N A2 A3
<14> USB20_N6
H5 H4 P P A4 A5
PEX_RST# <14>
CV1087 1 2 0.22U_0402_6.3V7K PEG_CRX_C_GTX_P6 H4 H3 G G A3 A4
<14> USB20_P6 H5 N N A5 BKOFF# <58> <7> PEG_CRX_GTX_P6 PEG_CRX_C_GTX_N6 H4 P P A4 PEG_CTX_C_GRX_P1 <7>
H6 A6 <7> PEG_CRX_GTX_N6 CV1088 1 2 0.22U_0402_6.3V7K H5 A5 PEG_CTX_C_GRX_N1 <7>
H7 H6 G G A6 A7 H6 H5 N N A5 A6
<14> USB20_N7 H7 P P A7 CLK_PEG_P0 <15> PEG_CRX_C_GTX_P5 H6 G G A6
H8 A8 <7> PEG_CRX_GTX_P5 CV1089 1 2 0.22U_0402_6.3V7K H7 A7 PEG_CTX_C_GRX_P0 <7>
<14> USB20_P7 H8 N N A8 CLK_PEG_N0 <15> PEG_CRX_C_GTX_N5 H7 P P A7
H9 A9 <7> PEG_CRX_GTX_N5 CV1090 1 2 0.22U_0402_6.3V7K H8 A8 PEG_CTX_C_GRX_N0 <7>
H10 H9 G G A9 A10 H9 H8 N N A8 A9
H10 A10 H10 H9 G G A9 A10
H10 A10 EC_AC_BAT# <58>
G1 B1
G2 G1 G G B1
B2 G1 B1
<77> REMOTE2-
G3 G2 P P B2
B3 CV1091 1 2 0.22U_0402_6.3V7K PEG_CRX_C_GTX_P4 G2 G1 G G B1
B2
C <77> REMOTE2+ G3 N N B3 <7> PEG_CRX_GTX_P4 PEG_CRX_C_GTX_N4 G2 P P B2 PEG_CTX_C_GRX_P5 <7> C
G4 B4 <7> PEG_CRX_GTX_N4 CV1092 1 2 0.22U_0402_6.3V7K G3 B3 PEG_CTX_C_GRX_N5 <7>
STRAP5_PCH G5 G4 G G B4
B5 G4 G3 N N B3
B4
G6 G5 P P B5
B6 CV1093 1 2 0.22U_0402_6.3V7K PEG_CRX_C_GTX_P3 G5 G4 G G B4
B5
<58,78,88,98> PCH_PWR_EN G6 N N B6 <7> PEG_CRX_GTX_P3 PEG_CRX_C_GTX_N3 G5 P P B5 PEG_CTX_C_GRX_P2 <7>
G7 B7 <7> PEG_CRX_GTX_N3 CV1094 1 2 0.22U_0402_6.3V7K G6 B6 PEG_CTX_C_GRX_N2 <7>
G8 G7 G G B7
B8 G7 G6 N N B6
B7
G9 G8 P P B8
B9 CV1095 1 2 0.22U_0402_6.3V7K PEG_CRX_C_GTX_P1 G8 G7 G G B7
B8
<14> DP_HPD_PCH G9 N N B9 <7> PEG_CRX_GTX_P1 PEG_CRX_C_GTX_N1 G8 P P B8 PEG_CTX_C_GRX_P4 <7>
G10 B10 <7> PEG_CRX_GTX_N1 CV1096 1 2 0.22U_0402_6.3V7K G9 B9 PEG_CTX_C_GRX_N4 <7>
G10G G B10
G10 G9 N N B9
B10
F1 C1 G10G G B10
<58> GPU_OVERT# F1 P P C1
<14> HDMI_HPD_PCH F2 C2 F1 C1
F3 F2 N N C2 C3
DGPU_HOLD_RST# <14> <12,58,63,74,77> EC_SMB_CK2
F2 F1 P P C1 C2
F3 G G C3 <12,58,63,74,77> EC_SMB_DA2 F2 N N C2 DGPU_PWR_EN <58>
F4 C4 F3 C3
<58> EN_INVPWR F4 P P C4 PEG_CRX_C_GTX_P2 F3 G G C3
F5 C5 +5VALW <7> PEG_CRX_GTX_P2 CV1097 1 2 0.22U_0402_6.3V7K F4 C4 PEG_CTX_C_GRX_P6 <7>
F6 F5 N N C5 C6 CV1098 1 2 0.22U_0402_6.3V7K PEG_CRX_C_GTX_N2 F5 F4 P P C4 C5
F6 G G C6 <7> PEG_CRX_GTX_N2 F5 N N C5 PEG_CTX_C_GRX_N6 <7>
F7 C7 +3VALW F6 C6
<59> LCD_TEST F7 P P C7 PEG_CRX_C_GTX_P0 F6 G G C6
<58> TS_EN F8 N C8 <7> PEG_CRX_GTX_P0 CV1099 1 2 0.22U_0402_6.3V7K F7 C7 PEG_CTX_C_GRX_P7 <7>
F9 F8 N C8 C9 CV1100 1 2 0.22U_0402_6.3V7K PEG_CRX_C_GTX_N0 F8 F7 P P C7 C8
F9 C9 <7> PEG_CRX_GTX_N0 F8 N N C8 PEG_CTX_C_GRX_N7 <7>
<58> GPU_STRAP5_EC F10 C10 <15> CLKREQ_PEG#0 F9 C9
F10 C10 F10 F9 C9 C10
STRAP3_PCH F10 C10 GC6_FB_EN <14>
E1 D1 PCH_PLTRST# <74>
E2 E1 D1 D2 ENVDD E1 D1
+5VALW E2 D2 +5VALW E1 D1
+5VS E9 D9 +3VS E2 D2 GC6_EVENT# <14>
E9 D9 <58> EC_ENBKL E2 D2
E10 D10 +5VS E9 D9 +3VS
E10 D10 E10 E9 D9 D10
E10 D10

UNIMI_FBGCAX011
UNIMI_FBGCAX011

+3VALW

W=60 mils
Strap to PCH LCD power control

10U_0603_6.3V6M
NOCP@ CV1080

10U_0603_6.3V6M
NOCP@ CV1081
1 1

10P_0402_50V8J
1
+LCDVDD

CV1076
NOCP@RF@
B B
+3V_PCH 2 2
2 NOCP@

W=60 mils
UV64
1 6
IN OUT
1

RG555 2
10K_0201_1% 3 IN 7
+5VALW VBIAS VCC_PAD

47U_0603_6.3V6M

NOCP@ CV1079

10U_0603_6.3V6M

NOCP@ CV1082

10P_0402_50V8J

NOCP@RF@

470P_0402_50V7K

EMI@ CV1101

470P_0402_50V7K

EMI@ CV1109
ENVDD 4 5 1 1 1 1
ON GND

1
STRAP3_PCH AOZ1334DI-02_DFN8-7_3X3
<13> STRAP3_PCH
2

CV1083
2 2 2 2
1 NOCP@

2
CV1078
0.1U_0402_10V7K
+3V_PCH
2
1

RG556
10K_0201_1%

STRAP5_PCH
<13> STRAP5_PCH
2

Vout=3.3V

LCD power control


Imax=1.33A
OCP(min):1.8A
(typ):2A
(max):2.2A
+LCDVDD
+3VALW
OCP@

W=60 mils W=60 mils


UV65
6 1
IN OUT

@EMI@ CV1102
5 2
SET GND
10P_0402_50V8J

10U_0603_6.3V6M
OCP@ CV1105

10U_0603_6.3V6M
OCP@ CV1106

47U_0603_6.3V6M

10U_0603_6.3V6M

OCP@ CV1107

10P_0402_50V8J

OCP@RF@

2200P_0402_25V7K
1 1 1 RV4 OCP@ 1 1

@ CV1104
4 3 1 2ENVDD
DSG FLAG/EN

1
CV1103
OCP@RF@

CV1108
100K_0402_1%
OCP@ OCP@
G517AH1TP1U_TSOT23-6
1

2 2 2 RV1 RV2 2 2

2
A A
10.5K_0402_1% 100_0402_5%
2

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/03/29 2019/03/29 Title

DGFF connector
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 37 of 101
5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/03/29 2019/03/29 Title

Reversed
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 38 of 101
5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/03/29 2019/03/29 Title

Reversed
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 39 of 101
5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/03/29 2019/03/29 Title

Reversed
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 40 of 101
5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/03/29 2019/03/29 Title

Reversed
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 41 of 101
5 4 3 2 1
5 4 3 2 1

NRTD3@
TBT_RST#_R RT1 1 2 0_0201_5% PCIRST# PCIRST# <11,51,52,58,68>
CONN@
CLIP1 TBT_PCIE_WAKE_N RT10 1 2 0_0201_5%
TBT_PCIE_WAKE# <12,58>
CLIP_10P2X7P2_SHIELDING_CASE1
EC0XQ000G00
UT1A
CT3 1 2 0.22U_0201_6.3V PCIE_CTX_C_RD_TRX_P21 Y23 V23 PCIE_CRX_C_RD_TTX_P21 0.22U_0201_6.3V 2 1 CT14
<45> PCIE_CTX_RD_TRX_P21 PCIE_CTX_C_RD_TRX_N21 PCIE_RX0_P PCIE_TX0_P PCIE_CRX_RD_TTX_P21 <45>
CT15 1 2 0.22U_0201_6.3V Y22 V22 PCIE_CRX_C_RD_TTX_N21 0.22U_0201_6.3V 2 1 CT16
<45> PCIE_CTX_RD_TRX_N21 PCIE_RX0_N PCIE_TX0_N PCIE_CRX_RD_TTX_N21 <45>
CT1 1 2 0.22U_0201_6.3V PCIE_CTX_C_RD_TRX_P22 T23 P23 PCIE_CRX_C_RD_TTX_P22 0.22U_0201_6.3V 2 1 CT12

PCIE TX
<45> PCIE_CTX_RD_TRX_P22 PCIE_CTX_C_RD_TRX_N22 PCIE_RX1_P PCIE_TX1_P PCIE_CRX_RD_TTX_P22 <45>
CT13 1 2 0.22U_0201_6.3V T22 P22 PCIE_CRX_C_RD_TTX_N22 0.22U_0201_6.3V 2 1 CT2

PCIe GEN3
<45> PCIE_CTX_RD_TRX_N22 PCIE_RX1_N PCIE_TX1_N PCIE_CRX_RD_TTX_N22 <45>
CT4 1 2 0.22U_0201_6.3V PCIE_CTX_C_RD_TRX_P23 M23 K23 PCIE_CRX_C_RD_TTX_P23 0.22U_0201_6.3V 2 1 CT109
<45> PCIE_CTX_RD_TRX_P23 PCIE_CTX_C_RD_TRX_N23 M22 PCIE_RX2_P PCIE_TX2_P PCIE_CRX_RD_TTX_P23 <45>
CT18 1 2 0.22U_0201_6.3V K22 PCIE_CRX_C_RD_TTX_N23 0.22U_0201_6.3V 2 1 CT108
<45> PCIE_CTX_RD_TRX_N23 PCIE_RX2_N PCIE_TX2_N PCIE_CRX_RD_TTX_N23 <45>
D
CT5 1 2 0.22U_0201_6.3V PCIE_CTX_C_RD_TRX_P24 H23 F23 PCIE_CRX_C_RD_TTX_P24 0.22U_0201_6.3V 2 1 CT111
D
<45> PCIE_CTX_RD_TRX_P24 PCIE_CTX_C_RD_TRX_N24 PCIE_RX3_P PCIE_TX3_P PCIE_CRX_C_RD_TTX_N24 0.22U_0201_6.3V PCIE_CRX_RD_TTX_P24 <45>
CT21 1 2 0.22U_0201_6.3V H22 F22 2 1 CT110
<45> PCIE_CTX_RD_TRX_N24 PCIE_RX3_N PCIE_TX3_N PCIE_CRX_RD_TTX_N24 <45>

PCIE CLK
CLK_PCIE_P3_C V19 L4 TBT_RST#_R +3VALW
<45> CLK_PCIE_P3_C CLK_PCIE_N3_C PCIE_REFCLK_100_IN_P PERST_N
T19
<45> CLK_PCIE_N3_C CLKREQ_PCIE#3_R PCIE_REFCLK_100_IN_N
2 1 AC5 N16 PCIE_RBIAS RT3 1 2 3.01K_0201_1%
<15,45> CLKREQ_PCIE#3 PCIE_CLKREQ_N PCIE_RBIAS
RT2 0_0201_5%
CT6 1 2 0.1U_0201_6.3V6K CPU_DP1_P0_C AB7 R2
<6> CPU_DP1_P0 CPU_DP1_N0_C DPSNK0_ML0_P DPSRC_ML0_P 1 RTD3@
<6> CPU_DP1_N0 CT7 1 2 0.1U_0201_6.3V6K AC7 R1 CT5361
DPSNK0_ML0_N DPSRC_ML0_N 0.1U_0402_10V6K
CT8 1 2 0.1U_0201_6.3V6K CPU_DP1_P1_C AB9 N2
<6> CPU_DP1_P1 CPU_DP1_N1_C DPSNK0_ML1_P DPSRC_ML1_P 2
<6> CPU_DP1_N1 CT9 1 2 0.1U_0201_6.3V6K AC9 N1
DPSNK0_ML1_N DPSRC_ML1_N

SOURCE PORT 0
CT10 1 2 0.1U_0201_6.3V6K CPU_DP1_P2_C AB11 L2

SINK PORT 0
CPU DDI1
<6> CPU_DP1_P2 DPSNK0_ML2_P DPSRC_ML2_P

5
CT23 1 2 0.1U_0201_6.3V6K CPU_DP1_N2_C AC11 L1
<6> CPU_DP1_N2 DPSNK0_ML2_N DPSRC_ML2_N 1 PCIRST#

VCC
CT11 1 2 0.1U_0201_6.3V6K CPU_DP1_P3_C AB13 J2 TBT_RST#_R4 IN B
<6> CPU_DP1_P3 CPU_DP1_N3_C DPSNK0_ML3_P DPSRC_ML3_P <45> TBT_RST#_R OUT Y
CT24 1 2 0.1U_0201_6.3V6K AC13 J1 2TBT_RTD3_RST#
<6> CPU_DP1_N3 DPSNK0_ML3_N DPSRC_ML3_N IN A TBT_RTD3_RST# <14>

GND
1
CT25 1 2 0.1U_0201_6.3V6K CPU_DP1_AUXP_C Y11 W19 RT693
+3VALW_TBT <6> CPU_DP1_AUXP CPU_DP1_AUXN_C DPSNK0_AUX_P DPSRC_AUX_P
CT26 1 2 0.1U_0201_6.3V6K W11 Y19 100K_0402_5%
<6> CPU_DP1_AUXN DPSNK0_AUX_N DPSRC_AUX_N @RTD3@ UT3 RTD3@

3
CPU_DP1_HPD AA2 G1 TBT_SRC_HPD RT4 1 2 1M_0201_1% NL17SZ08DFT2G_SC70-5
CPU_DP1_AUXN_C <13> CPU_DP1_HPD DPSNK0_HPD DPSRC_HPD
RT76 1 @ 2 100K_0201_5%

2
CPU_DP2_AUXN_C RT77 1 @ 2 100K_0201_5% CPU_DDC1CLK Y5 N6 DPSRC_RBIAS RT5 1 2 14K_0402_1%
CPU_DP1_AUXP_C RT78 1 @ 2 100K_0201_5% CPU_DDC1DATA R4 DPSNK0_DDC_CLK DPSRC_RBIAS
CPU_DP2_AUXP_C RT79 1 @ 2 100K_0201_5% DPSNK0_DDC_DATA U1
CPU_DP2_P0_C GPIO_0 TBT_I2C_SDA <44>
<6> CPU_DP2_P0 CT27 1 2 0.1U_0201_6.3V6K AB15 U2
TBT_I2C_SCL <44>
CT28 1 2 0.1U_0201_6.3V6K CPU_DP2_N0_C AC15 DPSNK1_ML0_P GPIO_1 V1 TBT_EE_WP_N 1 2
<6> CPU_DP2_N0 DPSNK1_ML0_N GPIO_2 TBT_TMU_CLK_OUT
V2 @ RT733 0_0402_5%

LC GPIO
CPU_DP2_P1_C GPIO_3 TBT_PCIE_WAKE_N @ T2
<6> CPU_DP2_P1 CT29 1 2 0.1U_0201_6.3V6K AB17 W1 TBT_PCIE_WAKE_N <14>
+3.3V_LC CT30 1 2 0.1U_0201_6.3V6K CPU_DP2_N1_C AC17 DPSNK1_ML1_P GPIO_4 W2 TBT_CIO_PLUG_EVENT#
<6> CPU_DP2_N1 DPSNK1_ML1_N GPIO_5 TBT_CIO_PLUG_EVENT# <14>
Y1 RT724 1 2 100K_0201_5%
CT31 1 2 0.1U_0201_6.3V6K CPU_DP2_P2_C AB19 GPIO_6 Y2 RT725 1 2 100K_0201_5%

CPU DDI2
<6> CPU_DP2_P2 CPU_DP2_N2_C DPSNK1_ML2_P GPIO_7 TBT_SRC_CFG1
CT32 1 2 0.1U_0201_6.3V6K AC19 AA1 RT11 1 2 1M_0201_1%

SINK PORT 1
<6> CPU_DP2_N2 DPSNK1_ML2_N GPIO_8 TBTA_I2C_INT
C J4 TBTA_I2C_INT <44>
C
CT33 1 2 0.1U_0201_6.3V6K CPU_DP2_P3_C AB21 POC_GPIO_0 E2 TBTB_I2C_INT
<6> CPU_DP2_P3 CPU_DP2_N3_C DPSNK1_ML3_P POC_GPIO_1 RTD3_USB_PWR_EN_R
RT6 RT7 RT8 RT9 CT34 1 2 0.1U_0201_6.3V6K AC21 D4 RT12 1 2 0_0201_5%

POC GPIO
<6> CPU_DP2_N3 DPSNK1_ML3_N POC_GPIO_2 RTD3_USB_PWR_EN <14>
1

TBT_FORCE_PWR_R
10K_0201_5%

10K_0201_5%

10K_0201_5%

10K_0201_5%

H4 RT13 1 2 0_0201_5%
CPU_DP2_AUXP_C POC_GPIO_3 TBT_FORCE_PWR <11>
CT35 1 2 0.1U_0201_6.3V6K Y12 F2 BATLOW# RT14 1 @ 2 0_0201_5% PCH_BATLOW# <12>
<6> CPU_DP2_AUXP CPU_DP2_AUXN_C DPSNK1_AUX_P POC_GPIO_4 SUSP#_R
CT36 1 2 0.1U_0201_6.3V6K W12 D2 RT15 1 2 0_0201_5% SUSP# <56,58,59,68,78,87,89>
<6> CPU_DP2_AUXN DPSNK1_AUX_N POC_GPIO_5 RTD3_CIO_PWR_EN_R
F1 RT16 1 2 0_0201_5% RTD3_CIO_PWR_EN <14>
CPU_DP2_HPD Y6 POC_GPIO_6
<13> CPU_DP2_HPD
2

TBT_TDI DPSNK1_HPD E1 TBT_TEST_EN RT17 1 2 100_0201_5%


TBT_TMS CPU_DDC2CLK Y8 TEST_EN
TBT_TCK CPU_DDC2DATA N4 DPSNK1_DDC_CLK AB5 TBT_TEST_PWG RT18 1 2 100_0201_5%

Misc
TBT_TDO DPSNK1_DDC_DATA TEST_PWR_GOOD YT1
2 1 DPSNK_RBIAS Y18 F4 TBT_RESET_N 25MHZ_20PF_XRCGB25M000F2P18R0
+3VALW_TBT DPSNK_RBIAS RESET_N TBT_RESET_N <44>
RT19 14K_0402_1% RT23 1 2 0_0201_5%
TBT_TDI TBT_RESET_N_EC <45,59>
Y4 D22 TBT_XTAL_25_IN RT116 1 2 0_0402_5% EMI@ 1 3
TBT_TMS V4 TDI XTAL_25_IN D23 TBT_XTAL_25_OUT RT117 1 2 0_0402_5% EMI@ 1 3
TBTA_LSTX TBT_TCK TMS XTAL_25_OUT 1 NC NC 1
RT21 2 @ 1 10K_0201_5% T4 CT37 CT38
TCK
CLKREQ_PCIE#3_R RT20 2 1 10K_0201_5% TBT_TDO W4
TDO MISC EE_DI
AB3 TBT_EE_DI
TBT_EE_DO
27P_0201_25V
2 4
27P_0201_25V
AC4
TBT_RTD3_RST# RT695 2 @RTD3@1 10K_0201_5% 2 1 TBT_RBIAS H6 EE_DO AC3 TBT_EE_CS_N 2 2
RT25 4.75K_0402_0.5% TBT_RSENSE J6 RBIAS EE_CS_N AB4 TBT_EE_CLK_R 1 2 TBT_EE_CLK
TBT_RST#_R RT723 2 1 10K_0201_5%
RTD3@ RSENSE EE_CLK
A15 B7 RT52 EMI@
<44> TBT_A_TRX_DTX_P1 PA_RX1_P PB_RX1_P
B15 A7

Close to UT1
<44> TBT_A_TRX_DTX_N1 15_0402_5%
PA_RX1_N PB_RX1_N
CT39 1 2 0.22U_0201_6.3V TBT_A_TTX_DRX_P1 A17 A9
CPU_DDC1CLK <44> TBT_A_TTX_C_DRX_P1 TBT_A_TTX_DRX_N1 PA_TX1_P PB_TX1_P
RT127 1 2 100K_0201_5% CT40 1 2 0.22U_0201_6.3V B17 B9
CPU_DDC1DATA <44> TBT_A_TTX_C_DRX_N1 PA_TX1_N PB_TX1_N
RT126 1 2 100K_0201_5%
CPU_DDC2CLK RT129 1 2 100K_0201_5% CT41 1 2 0.22U_0201_6.3V TBT_A_TTX_DRX_P0 A19 A11
CPU_DDC2DATA <44> TBT_A_TTX_C_DRX_P0 TBT_A_TTX_DRX_N0 PA_TX0_P PB_TX0_P
RT128 1 2 100K_0201_5% CT42 1 2 0.22U_0201_6.3V B19 B11
<44> TBT_A_TTX_C_DRX_N0 PA_TX0_N PB_TX0_N
B21 A13

Closed to UT1

TBT PORTS
<44> TBT_A_TRX_DTX_P0 PA_RX0_P PB_RX0_P
A21 B13
<44> TBT_A_TRX_DTX_N0 PA_RX0_N PB_RX0_N

Port A

PORT B
CPU_DP1_HPD RT38 1 2 100K_0201_5% CT43 1 2 0.1U_0201_6.3V6K TBT_A_AUX_P Y15 Y16
CPU_DP2_HPD <44> TBT_A_AUX_P_C TBT_A_AUX_N PA_DPSRC_AUX_P PB_DPSRC_AUX_P
B RT39 1 2 100K_0201_5% <44> TBT_A_AUX_N_C CT44 1 2 0.1U_0201_6.3V6K W15 W16 B
TBTA_LSTX RT40 1 2 1M_0201_1% PA_DPSRC_AUX_N PB_DPSRC_AUX_N +3.3V_TBT_SX
TBTA_HPD RT41 1 2 100K_0201_5% E20 E19
TBTA_LSRX <44> TBT_A_USB20_P PA_USB2_D_P PB_USB2_D_P TBT_I2C_SDA
RT42 1 2 1M_0201_1% D20 D19 RT26 2 1 3.3K_0201_5%
<44> TBT_A_USB20_N PA_USB2_D_N PB_USB2_D_N TBT_I2C_SCL RT27 2 1 3.3K_0201_5%
TBTA_LSTX A5 B4 NC_B4 TBT_PCIE_WAKE_N RT28 2 1 10K_0201_5%
<44> TBTA_LSTX TBTA_LSRX PA_LS_G1 PB_LS_G1 NC_B5 TBT_CIO_PLUG_EVENT#
<44> TBTA_LSRX A4 B5 RT29 2 1 10K_0201_5%
TBTA_HPD PA_LS_G2 PB_LS_G2 NC_G2 SUSP#_R

POC
POC
M4 G2 RT30 2 @ 1 10K_0201_5%
<44> TBTA_HPD PA_LS_G3 PB_LS_G3 BATLOW# RT31 2 1 10K_0201_5%
2 1 PA_USB2_RBIAS H19 F19 PB_USB2_RBIAS 1 2 TBTA_I2C_INT RT32 2 1 10K_0201_5%
RT43 499_0201_1% PA_USB2_RBIAS PB_USB2_RBIAS RT44 499_0201_1% TBTB_I2C_INT RT33 2 1 10K_0201_5%
AC23 D6 RTD3_CIO_PWR_EN_R RT36 2 @ 1 10K_0201_5%
AB23 THERMDA MONDC_SVR NC_B4 RT86 2 @ 1 10K_0201_5%
THERMDA A23 TBT_FORCE_PWR_R RT94 2 @ 1 10K_0201_5%
V18 ATEST_P B23
PCIE_ATEST ATEST_N

1
AC1
TEST_EDM DEBUG USB2_ATEST
E18 RT726
100K_0201_5%
+3.3V_FLASH L15 W13

Close to UT2
N15 FUSE_VQPS_64 MONDC_DPSNK_0
FUSE_VQPS_128 W18

2
C23 MONDC_DPSNK_1 TBT_EE_DI RT98 1 2 0_0201_5%
1 MONDC_CIO_0 TBT_EE_DO PD_EE_DI <44>
CT45 C22 AB2 RT99 1 2 0_0201_5%
MONDC_CIO_1 MONDC_DPSRC TBT_EE_CS_N PD_EE_DO <44>
0.1U_0201_6.3V6K RT100 1 2 0_0201_5%
TBT_EE_CLK PD_EE_CS_N <44>
ALPINE-RIDGE_BGA337 RT101 1 2 0_0201_5% PD_EE_CLK <44>
2
UT2
RT50 1 2 2.2K_0201_5% TBT_EE_CS_N 1 8
RT49 1 2 2.2K_0201_5% TBT_EE_DO 2 CS# VCC 7 TBT_HOLD_N 2 1
RT48 1 2 3.3K_0201_5% TBT_EE_WP_N 3 DO(IO1) HOLD#(IO3) 6 TBT_EE_CLK
4 WP#(IO2) CLK 5 TBT_EE_DI RT51
GND DI(IO0) 3.3K_0201_5% TBT_TMU_CLK_OUT RT34 1 2 100K_0201_5%
W25Q80DVSSIG_SO8 TBT_FORCE_PWR_R RT35 1 2 100K_0201_5%
RTD3_USB_PWR_EN_R RT37 1 2 100K_0201_5%
1

@EMI@ TBT_RESET_N RT80 1 @ 2 100K_0201_5%


A A
RT122 NC_B4 RT45 1 2 100K_0201_5%
33_0402_5% NC_B5 RT46 1 2 100K_0201_5%
NC_G2 RT47 1 2 100K_0201_5%
2

1
@EMI@
CT156
22P_0402_50V8J~D

Compal Electronics, Inc.


2
Security Classification Compal Secret Data
2018/03/29 2019/03/29
Close to UT2 Thunderbolt (1/2)
Issued Date Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 42 of 101
5 4 3 2 1
5 4 3 2 1

+3VALW_TBT_S5 +3.3V_TBT_SX +3.3V_TBT_SX +3VALW

1 2 1 2
RT97 0_0402_5% RT729 0_0402_5% +3VALW_TBT
+3VALW_TBT_S5 +3VALW_TBT +3.3V_LC +3.3V_TBT_SX
UT10 +3VALW_TBT
@ 1 2

1U_0201_6.3V6M

47U_0603_6.3V6M

47U_0603_6.3V6M
3 +3VALW_TBT LT4
OUT 1 1 1
1 2 1UH_LQM18PN1R0MFHD_20%

0.1U_0201_6.3V6K

1U_0201_6.3V6M

CT153

CT154

CT155
1 @ RT730 0_0805_5% 1 1
IN

@RF@ CH242
1 2 CT46 CT47
2 RT95 0_0805_5% 2 2 2
GND

1U_0201_6.3V6M

1U_0201_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10P_0402_50V8J
D 2 2 1 1 1 1 1 1 1 D

CT48

CT49

CT50

CT51

CT52

CT53
SA000080300
+0.9V_DP

R13
2 2 2 2 2 2 2

R6

H9
UT1B

F8
L8 A2
L11 VCC0P9_DP VCC3P3_SVR A3

VCC3P3_SX

VCC3P3A
VCC3P3_LC

VCC3P3_S0
VCC0P9_DP VCC3P3_SVR

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
1 1 1 1 1 1 1 L12 B3
CT54 CT57 CT58 CT59 CT60 CT61 CT62 M8 VCC0P9_DP VCC3P3_SVR
T11 VCC0P9_DP
T12 VCC0P9_DP L9 +0.9V_SVR
2 2 2 2 2 2 2 L6 VCC0P9_DP VCC0P9_SVR M9
VCC0P9_ANA_DPSRC VCC0P9_SVR

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
M6 E12 1 1 1 1 1 1 1
V11 VCC0P9_ANA_DPSRC VCC0P9_SVR_ANA E13 CT63 CT64 CT65 CT66 CT67 CT68 CT69
V12 VCC0P9_ANA_DPSNK VCC0P9_SVR_ANA F11
+0.9V_PCIE V13 VCC0P9_ANA_DPSNK VCC0P9_SVR_ANA F12
VCC0P9_ANA_DPSNK VCC0P9_SVR_ANA F13 2 2 2 2 2 2 2
M13 VCC0P9_SVR_ANA F15
M15 VCC0P9_PCIE VCC0P9_SVR_ANA J9
VCC0P9_PCIE VCC0P9_SVR_SENSE

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
1 1 1 1 M16
CT55 CT70 CT71 CT72 L19 VCC0P9_PCIE LT1
N19 VCC0P9_ANA_PCIE_1 C1 TBT_SVR_IND 1 2
L18 VCC0P9_ANA_PCIE_1 SVR_IND C2 0.6UH_MND-04ABIR60M-XGL_20%
2 2 2 2 VCC0P9_ANA_PCIE_2 SVR_IND

47U_0603_6.3V6M

47U_0603_6.3V6M

47U_0603_6.3V6M
M18 D1 1 1 1
+0.9V_USB N18 VCC0P9_ANA_PCIE_2 SVR_IND CT73 CT74 CT75
VCC0P9_ANA_PCIE_2

VCC
R15 A1
R16 VCC0P9_USB SVR_VSS B1 2 2 2
+0.9V_CIO VCC0P9_USB SVR_VSS
1U_0201_6.3V6M

1U_0201_6.3V6M

1 1 B2
CT77 CT56 R8 SVR_VSS
R9 VCC0P9_CIO
R11 VCC0P9_CIO
2 2 R12 VCC0P9_CIO F18 +0.9V_LVR_OUT
VCC0P9_CIO VCC0P9_LVR
1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
1 1 1 H18
+3.3V_ANA_PCIE VCC0P9_LVR

10U_0402_6.3V6M

10U_0402_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
CT78 CT79 CT80 L16 J11 1 1 1 1
+3.3V_ANA_USB2 J16 VCC3P3_ANA_PCIE VCC0P9_LVR H11 CT81 CT82 CT83 CT84
C VCC3P3_ANA_USB2 VCC0P9_LVR_SENSE C
2 2 2 A6 V5
VSS_ANA VSS_ANA 2 2 2 2

10K_0201_5%

1U_0201_6.3V6M

1U_0201_6.3V6M
1 1 A8 V6
VSS_ANA VSS_ANA

2
RT200 CT85 CT86 A10 V8
A12 VSS_ANA VSS_ANA V9
A14 VSS_ANA VSS_ANA V15
2 2 A16 VSS_ANA VSS_ANA V16
1 A18 VSS_ANA VSS_ANA V20
A20 VSS_ANA VSS_ANA W5
A22 VSS_ANA VSS_ANA W6
B6 VSS_ANA VSS_ANA W8
B8 VSS_ANA VSS_ANA W9
B10 VSS_ANA VSS_ANA W20
B12 VSS_ANA VSS_ANA W22
B14 VSS_ANA VSS_ANA W23
B16 VSS_ANA VSS_ANA Y9
B18 VSS_ANA VSS_ANA Y13
B20 VSS_ANA VSS_ANA Y20
B22 VSS_ANA VSS_ANA AA22
D8 VSS_ANA VSS_ANA AA23
D9 VSS_ANA VSS_ANA AB6
D11 VSS_ANA VSS_ANA AB8
D12 VSS_ANA VSS_ANA AB10
D13 VSS_ANA VSS_ANA AB12
D15 VSS_ANA VSS_ANA AB14
D16 VSS_ANA VSS_ANA AB16
D18 VSS_ANA VSS_ANA AB18

GND
E8 VSS_ANA VSS_ANA AB20
E9 VSS_ANA VSS_ANA AB22
E11 VSS_ANA VSS_ANA AC6
E15 VSS_ANA VSS_ANA AC8
E16 VSS_ANA VSS_ANA AC10
E22 VSS_ANA VSS_ANA AC12
E23 VSS_ANA VSS_ANA AC14
F9 VSS_ANA VSS_ANA AC16
B F16 VSS_ANA VSS_ANA AC18 B
F20 VSS_ANA VSS_ANA AC20
G22 VSS_ANA VSS_ANA AC22
G23 VSS_ANA VSS_ANA D5
H1 VSS_ANA VSS E4
H2 VSS_ANA VSS E5
H12 VSS_ANA VSS E6
H13 VSS_ANA VSS F5
H15 VSS_ANA VSS F6
H16 VSS_ANA VSS H5
H20 VSS_ANA VSS H8
J5 VSS_ANA VSS J8
J18 VSS_ANA VSS J12
J19 VSS_ANA VSS J13
J20 VSS_ANA VSS J15
J22 VSS_ANA VSS L13
J23 VSS_ANA VSS M11
K1 VSS_ANA VSS M12
K2 VSS_ANA VSS N8
L5 VSS_ANA VSS N9
L20 VSS_ANA VSS N11
L22 VSS_ANA VSS N12
L23 VSS_ANA VSS N13
M1 VSS_ANA VSS T6
M2 VSS_ANA VSS T8
M5 VSS_ANA VSS T9
M19 VSS_ANA VSS T13
M20 VSS_ANA VSS T15
N5 VSS_ANA VSS T16
N20 VSS_ANA VSS T18
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA

N22 VSS_ANA VSS AB1


N23 VSS_ANA VSS AC2
VSS_ANA VSS
ALPINE-RIDGE_BGA337
R5

T20
T1
T2
T5
P1
P2

R18
R19
R20
R22
R23

U22
U23

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/03/29 2019/03/29
Thunderbolt (2/2)
Issued Date Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 43 of 101
5 4 3 2 1
5 4 3 2 1

DT2 ESD@
TBT_A_TTX_C_DRX_P0 1 2
PESD5V0H1BSF_SOD962-2-2
SC40000AT00
DT3 ESD@
+5VALW +TBTA_VBUS
+3VALW_TBT_S5 +3VALW_PD TBT_A_TTX_C_DRX_N0 1 2

60mil 3A 60mil 3A
PESD5V0H1BSF_SOD962-2-2
SC40000AT00
1 2 DT4 ESD@

10P_0402_50V8J
RT53 0_0402_5% 1 1 1 1 1
+3VALW TBT_A_TRX_DTX_P0

4.7U_0603_10V6K

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
CT90 CT157 CT91 CT92 CT93 1 2

CV1074
@RF@
CT106 PESD5V0H1BSF_SOD962-2-2

3
1U_0603_25V6K DT1 DT15 SC40000AT00
D 1 2 2 2 2 2 2 SDM10U45-7_SOD523-2~D PESD24VS2UT_SOT23-3 DT5 ESD@ D

2
RT731 0_0402_5% ESD@

2
TBT_A_TRX_DTX_N0 1 2
@
PESD5V0H1BSF_SOD962-2-2

2
TBTA_LDO_BMC

Close to UT4
SC40000AT00

1
+1.8VD_TBTA_LDO DT6 ESD@
1 +1.8VA_TBTA_LDO
+3VALW CT88
0.1U_0402_10V6K TBT_A_TTX_C_DRX_P1 1 2
1 1 1
PESD5V0H1BSF_SOD962-2-2
2 CT98 CT99 CT100 SC40000AT00
2.2U_0402_16V6K 4.7U_0603_10V6K 4.7U_0603_10V6K DT7 ESD@
1

2
RT732 2 2 2 RT22
10K_0201_5% +3VALW_PD +3.3V_FLASH 0_0201_5% TBT_A_TTX_C_DRX_N1 1 2
@ PESD5V0H1BSF_SOD962-2-2
SC40000AT00

Master0:0 ohm
+3VALW_TBT_S5 DT8 ESD@
1
2

1
CT101

Slave1:93.1K ohm
@ 10U_0402_6.3V6M TBT_A_TRX_DTX_P1 1 2
10K_0201_5% 1 2 RT107 PD_IRQ# 0.6A PESD5V0H1BSF_SOD962-2-2
2 SC40000AT00
DT9 ESD@

H10

C11
D11
A11
B11

B10

A10
H1

B1

K1

A2

E1

A6
A7
A8
B7

B9

A9
UT4
RT83 1 2 0_0201_5% F1 TBT_A_TRX_DTX_N1 1 2
I2C_ADDR PESD5V0H1BSF_SOD962-2-2

VIN_3V3

VDDIO

LDO_1V8A

PP_CABLE

PP_5V0
PP_5V0
PP_5V0
PP_5V0

PP_HV
PP_HV
PP_HV
PP_HV

HV_GATE1

HV_GATE2
SENSEP
LDO_1V8D

LDO_BMC

SENSEN
RT720 1 2 0_0201_5% TBT_I2C_SDA_R D1 SC40000AT00
<42> TBT_I2C_SDA TBT_I2C_SCL_R I2C_SDA1
<42> TBT_I2C_SCL RT721 1 2 0_0201_5% D2 DT11 ESD@
RT722 1 2 0_0201_5% TBTA_I2C_INT_R C1 I2C_SCL1
<42> TBTA_I2C_INT I2C_IRQ1_N +3.3V_TBT_SX_R +3.3V_TBT_SX TBT_A_CC1 1 2
PESD5V0H1BSF_SOD962-2-2
RT59 1 2 0_0201_5% TBTA_I2C_SDA1_R A5 SC40000AT00
<45,58,82,83,84,85> EC_SMB_DA1 TBTA_I2C_SCL1_R I2C_SDA2
<45,58,82,83,84,85> EC_SMB_CK1 RT60 1 2 0_0201_5% B5 H11 1 @ 2 DT12 ESD@
PD_IRQ# B6 I2C_SCL2 VBUS J10 RT61 0_0201_5%
<58> PD_IRQ# I2C_IRQ2_N VBUS TBT_A_CC2
J11 1 2
B2 VBUS K11 PESD5V0H1BSF_SOD962-2-2
T64 TP@ GPIO0 VBUS
C2 1 SC40000AT00
T65 TP@ GPIO1
T114 TP@ D10 CT102 DT13 ESD@
G11 GPIO2 1U_0201_6.3V6M
T120 TP@ GPIO3 TBT_A_SBU1
C10 1 2
<42> TBTA_HPD GPIO4 2
E10 H2 PESD5V0H1BSF_SOD962-2-2
T121 TP@ GPIO5 VOUT_3V3
G10 SC40000AT00
T122 TP@ GPIO6 +3.3V_FLASH
T70 TP@ D7 DT14 ESD@
GPIO8 H6 GPIO7
C GPIO8 G1 TBT_A_SBU2 1 2
C
PD_EE_CLK A3 LDO_3V3 PESD5V0H1BSF_SOD962-2-2
<42> PD_EE_CLK PD_EE_DI SPI_CLK
B4 1 SC40000AT00
<42> PD_EE_DI PD_EE_DO SPI_MOSI
<14> USB20_P11 RT115 1 2 0_0402_5% <42> PD_EE_DO A4 CT103
RT114 1 2 0_0402_5% PD_EE_CS_N B3 SPI_MISO K6 TBT_A_USB20_PT 10U_0402_6.3V6M
<14> USB20_N11 <42> PD_EE_CS_N SPI_SS_N C_USB_TP TBT_A_USB20_NT
L6
@ RT113 1 2 0_0402_5% USB20_P11_R L5 C_USB_TN 2
<42> TBT_A_USB20_P USB20_N11_R USB_RP_P
@ RT112 1 2 0_0402_5% K5
<42> TBT_A_USB20_N USB_RP_N
RT62 2 1100K_0201_5% PD_UART E2 K7 TBT_A_USB20_PB
F2 UART_TX C_USB_BP L7 TBT_A_USB20_NB
UART_RX C_USB_BN
LT2
F4 EMI@
+3.3V_FLASH T62 TP@ SWD_DATA TBT_A_USB20_NT TBT_A_USB20_L_NT
T63 TP@ G4 4 3
SWD_CLK L9 TBT_A_CC1 CT112 1 2 220P_0201_25V7K 4 3
C_CC1 L10 TBT_A_CC2 CT113 1 2 220P_0201_25V7K +3.3V_FLASH
C_CC2 TI's Requirement TBT_A_USB20_PT 1 2 TBT_A_USB20_L_PT
RT63 2 1 100K_0201_5%TBTA_MRESET E11 1 2
MRESET
DLM0NSN900HY2D_4P
1

RT124 K9 RPD_G1 RT64 1 2 10K_0201_5%


RPD_G1

1
10K_0201_5% TBTA_LSTX L4 K10 RPD_G2 RT65 1 2 10K_0201_5% RT66 RT67
<42> TBTA_LSTX TBTA_LSRX TBT_LSTX/R2P RPD_G2
K4 10K_0201_5% 10K_0201_5%
<42> TBTA_LSRX TBT_LSRX/P2R
LT3
EMI@
2

GPIO8 +3.3V_TBT_SX RT68 2 1 100K_0201_5%TBTA_DIG_AUD_P L3 E4 DEBUG_CTL1 TBT_A_USB20_NB 4 3 TBT_A_USB20_L_NB

2
RT69 2 1 100K_0201_5%TBTA_DIG_AUD_N K3 DIG_AUD_P/DEBUG3 DEBUG_CTL1 D5 DEBUG_CTL2 4 3
DIG_AUD_N/DEBUG4 DEBUG_CTL2
@ TBT_A_USB20_PB 1 2 TBT_A_USB20_L_PB
1 2
1

RT125 RT70 RT71 2 1 100K_0201_5%TBTA_DEBUG1 L2


10K_0201_5% 100K_0201_5% RT72 2 1 100K_0201_5%TBTA_DEBUG2 K2 DEBUG1
DEBUG2 DLM0NSN900HY2D_4P
K8 TBT_A_SBU1
TBT_A_AUX_P_C J1 C_SBU1
<42> TBT_A_AUX_P_C
2

TBT_A_AUX_N_C J2 AUX_P L8 TBT_A_SBU2


<42> TBT_A_AUX_N_C AUX_N C_SBU2
DT10
1

RT73 1 @ 2 BUSPOWER# F10 TBT_A_USB20_L_NT 1 9 TBT_A_USB20_L_NT


+3.3V_FLASH BUSPOWER_N RESET_N
100K_0201_5% RT130 0_0201_5% F11 1 @ 2
RESET_N TBT_RESET_N <42> TBT_A_USB20_L_PT TBT_A_USB20_L_PT
RT102 0_0201_5% 2 8
TBTA_ROSC G2
R_OSC TBT_A_USB20_L_NB 4 7 TBT_A_USB20_L_NB
2

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
B B
TBT_A_USB20_L_PB 5 6 TBT_A_USB20_L_PB
1

RT75 SN1703018ZQZR BGA96P


15K_0201_1%
D6

F5

H4
H5

D8

F6
F7
F8

H7
H8
A1

E5
E6
E7

G5

B8

E8

G6
G7
G8

L1
1 2 BUSPOWER# L11 3
RT131 0_0201_5%
2

1 TVW DF1004AD0_DFN9
ESD@ SC300003Z00
CT104

2
0.22U_0402_10V6K
SC300003Z00 (ESD use)
<59> PD_RESET 1
RT109
2
0_0402_5%
SC300002800 (symbol)
+TBTA_VBUS +TBTA_VBUS
1

RT108
0_0402_5%
@ JUSBC
A1 B12
GND1 GND3
2

A2 B11
<42> TBT_A_TTX_C_DRX_P1 SSTXP1 SSRXP1 TBT_A_TRX_DTX_P1 <42>
A3 B10
<42> TBT_A_TTX_C_DRX_N1 SSTXN1 SSRXN1 TBT_A_TRX_DTX_N1 <42>
CT94 1 2 0.47U_0402_25V6K A4 B9 CT96 1 2 0.47U_0402_25V6K
VBUS1 VBUS3
TBT_A_CC2 A5 B8 TBT_A_SBU1

GPN : TPS65982DCZQZR , SA0000AX700


CC1 SUB2
TBT_A_USB20_L_PB A6 B7 TBT_A_USB20_L_NT

Special PN : SN1703018ZQZR
TBT_A_USB20_L_NB A7 DP1 DN2 B6 TBT_A_USB20_L_PT
DN1 DP2
TBT_A_SBU2 A8 B5 TBT_A_CC1
SUB1 CC2

Bottom
CT95 1 2 0.47U_0402_25V6K A9 B4 CT97 1 2 0.47U_0402_25V6K

TOP
VBUS2 VBUS4
A10 B3
<42> TBT_A_TRX_DTX_N0 SSRXN2 SSTXN2 TBT_A_TTX_C_DRX_N0 <42>
A11 B2
<42> TBT_A_TRX_DTX_P0 SSRXP2 SSTXP2 TBT_A_TTX_C_DRX_P0 <42>
A12 B1
GND2 GND4

1 4
A GND5 GND8 A
2 3
5 GND6 GND7 6
GND9 GND10
JAE_DX07S024JJ5R1200~D
CONN@

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/03/29 2019/03/29
PD+USB3.1 type C
Issued Date Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 44 of 101
5 4 3 2 1
5 4 3 2 1

+3VALW_TBT_S5 +2.5VOUT_TBT
+3VALW

RT260 1 @ 2 0_0603_5% +2.5VOUT_TBT


+3VALW_TBT_S5

1 1 1 1 1 1 1

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
CT122 CT121

CT201

CT203

CT204

CT200

CT202
4.7U_0805_10V4Z 0.1U_0402_16V7K

1
2 2 RT222 2 2 2 2 2
UT8 1K_0201_1%
1
5 OUT
IN 1

22U_0603_6.3V6M
CT124
2

2
D
4 GND D
<59> TBT_S5_OFF# EN 3 1 2 TBT_PRSNT
OCB +3VS 2
RT132 UT6

14
41
36
51
9
10K_0402_5%
1 SY6288D20AAC_SOT23-5 @

VDD
VDD
VDD
VDD
VDD
1
CT123 RT223 1 45
D <14> PCIE_CRX_TTX_P21 2 OUTB_0+ INB_0+ 44 PCIE_CRX_RD_TTX_P21 <42>
0.1U_0402_16V7K 1K_0201_1%

PCIE RX
<14> PCIE_CRX_TTX_N21 OUTB_0- INB_0- PCIE_CRX_RD_TTX_N21 <42>

1
2 TBT_RST#_R <42> 3 43
2 <14> PCIE_CRX_TTX_P22 4 OUTB_1+ INB_1+ 42 PCIE_CRX_RD_TTX_P22 <42>
G
<14> PCIE_CRX_TTX_N22 OUTB_1- INB_1- PCIE_CRX_RD_TTX_N22 <42>
S 5 40
<14> PCIE_CRX_TTX_P23 PCIE_CRX_RD_TTX_P23 <42>

2
QE65 6 OUTB_2+ INB_2+ 39
<14> PCIE_CRX_TTX_N23 PCIE_CRX_RD_TTX_N23 <42>

3
2N7002W-T/R7_SOT323-3 7 OUTB_2- INB_2- 38
<14> PCIE_CRX_TTX_P24 OUTB_3+ INB_3+ PCIE_CRX_RD_TTX_P24 <42>
8 37
<14> PCIE_CRX_TTX_N24 OUTB_3- INB_3- PCIE_CRX_RD_TTX_N24 <42>

+3VALW_TBT_S5 @ RT220 1 2 1K_0201_1% 10 35


<14> PCIE_CTX_TRX_P21 INA_0+ OUTA_0+ PCIE_CTX_RD_TRX_P21 <42>
11 34

PCIE TX
<14> PCIE_CTX_TRX_N21 12 INA_0- OUTA_0- 33 PCIE_CTX_RD_TRX_N21 <42>
<14> PCIE_CTX_TRX_P22 INA_1+ OUTA_1+ PCIE_CTX_RD_TRX_P22 <42>
13 32
1 2 1K_0201_1% TBT_ENSMB <14> PCIE_CTX_TRX_N22 15 INA_1- OUTA_1- 31 PCIE_CTX_RD_TRX_N22 <42>
RT221
<14> PCIE_CTX_TRX_P23 INA_2+ OUTA_2+ PCIE_CTX_RD_TRX_P23 <42>
16 30
<14> PCIE_CTX_TRX_N23 INA_2- OUTA_2- PCIE_CTX_RD_TRX_N23 <42>
17 29
<14> PCIE_CTX_TRX_P24 18 INA_3+ OUTA_3+ 28 PCIE_CTX_RD_TRX_P24 <42>
<14> PCIE_CTX_TRX_N24 INA_3- OUTA_3- PCIE_CTX_RD_TRX_N24 <42>
54 TBT_DEMB1
TBT_EQA1 DEMB1/AD0 TBT_DEMB0
9/11:change from SE000000K80 to SE00000UC00*2 19
EQA1 DEMB0/AD1
53
TBT_EQA0 20 52 TBT_PRSNT
21 EQA0 PRSNT 50 TBT_DEMA1
+3VALW_TBT_S5 TBT_RXDET RATE DEMA1/SCL TBT_DEMA0
+3VALW_TBT_S5 22 49
RXDET DEMA0/SDA 48 TBT_ENSMB

W=20 mils
TBT_SDTH +3VALW_TBT_S5 ENSMB TBT_EQB1
1 2 47
23 EQB1/AD2 46 TBT_EQB0
RT217 24 LPBK EQB0/AD3
1K_0201_1% 25 VIN
VDD_SEL
1

RT216 1 2 TBT_RXDET TBT_SDTH 26


SD_TH/READ_EN

10U_0603_6.3V6M

10U_0603_6.3V6M
1K_0201_1% 27 55
ALL_DONE DAP_GND

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
1 2 @ RT218 1 1 1 1 1 1
<42,59> TBT_RESET_N_EC
1K_0201_1% @

1
CT207

CT218

CT208

CT206

CT217

CT205
C @ RT708 RT219 C
2

0_0402_5% 1K_0201_1% RT241 DS80PCI402SQNOPB_WQFN54_10X5P5


2 2 2 2 2 2 1K_0201_1%

2
EQ*MB

+3VALW_TBT_S5 1 2 +3VALW_TBT_S5 1 2
@ RT231 1K_0201_1% @ RT228 1K_0201_1%

+3VALW_TBT_S5 1 2 TBT_EQA1 1 2 TBT_EQB1


RT229 1K_0201_1% RT224 1K_0201_1%
+3VALW_TBT_S5 +3VALW_TBT_S5
2 1
1 1
0.1U_0402_10V7K

0.1U_0402_10V7K
@ CT214

CT215

RT250 CT216
1

2.2_0402_1% 22U_0603_6.3V6M
1

RT243 @ RT242 RT244 +3VALW_TBT_S5


1K_0402_1% 4.7K_0402_5% 1K_0402_1% 2 2 1 2 1 2
+3VALW_TBT_S5 +3VALW_TBT_S5
2

@ RT226 1K_0201_1% @ RT225 1K_0201_1%

RT705 UT7 1 2 TBT_EQA0 1 2 TBT_EQB0


2

0_0201_5% 1 20 RT230 20K_0201_5% @ RT227 20K_0201_5%


PLL_BW_SEL VDDA

1
RT714
4.7K_0402_5%

4.7K_0402_5%
RT713
2 1 2 19
<15> CLK_PCIE_P3 SRCIN GNDA
RT706 2 1 3 18 @ RT248 2 1 475_0402_1%
B <15> CLK_PCIE_N3 SRCIN# IRef B
0_0201_5% 4 17 RT702 1 2 0_0201_5%
5 OE_0# OE_1# 16 CLKREQ_PCIE#3 <42>
+3VALW_TBT_S5 VDD VDD +3VALW_TBT_S5
6 15
2

7 GND GND 14 RT246 2 @ 1 33_0201_1% @ CT211 1 2 0.01U_0402_16V7K 2


CLK0 CLK1 CLK_PCIE_P3_C <42>
8 13 RT245 2 @ 1 33_0201_1% @ CT212 1 2 0.01U_0402_16V7K
CLK0# CLK1# CLK_PCIE_N3_C <42>
9 12

De-emphasis setting
10 VDD VDD 11
SDATA SCLK
1 1
0.1U_0402_10V7K

0.1U_0402_10V7K

1
1

1
1U_0201_6.3V6M

1U_0201_6.3V6M
CT210

CT209

1 1
RT712
604_0402_1%

604_0402_1%
RT711

PI6CEQ20200LIEX RT249 RT247


CT213

CT219

@ 49.9_0402_1% 49.9_0402_1% +3VALW_TBT_S5 +3VALW_TBT_S5


2 2
2 2
2
2

2
0_0201_5%

0_0201_5%
1
1

9/11:change from SE000000K80 to SE00000UC00*2 1 2 TBT_DEMA1 1 2 TBT_DEMB1


RT717

RT716

@ RT236 1K_0201_1% RT240 1K_0201_1%


@ @ 1 2 1 2
0_0201_5%
1
1

RT235 20K_0201_5% @ RT238 20K_0201_5%


0_0201_5%
2
2

RT718

RT719

EC_SMB_DA1
<44,58,82,83,84,85> EC_SMB_DA1 EC_SMB_CK1
<44,58,82,83,84,85> EC_SMB_CK1 @ @
EC_SMB_CK1 RT709 2 @ 1 0_0201_5% TBT_DEMA1
2
2

EC_SMB_DA1 RT710 2 @ 1 0_0201_5% TBT_DEMA0


+3VALW_TBT_S5 +3VALW_TBT_S5

CLK_PCIE_P3 RT728 2 @ 1 0_0201_5% CLK_PCIE_P3_C


CLK_PCIE_N3 RT727 2 @ 1 0_0201_5% CLK_PCIE_N3_C 1 2 TBT_DEMA0 1 2 TBT_DEMB0
@ RT233 1K_0201_1% @ RT237 1K_0201_1%
1 2 1 2
@ RT234 1K_0201_1% @ RT239 1K_0201_1%

*
PCIe Clock Buffer UT7 RT248 RT245 / RT246 CT214 CT211 / CT212
A A
Pericom (SA00007JZ00) SD034475080 SD041330A80 SE102104K00 SE076103K80
X7680231L09 (475 +-1% 0402) (33 +-1% 0201) (0.1U +-10% 0402) (.01U 16V K X7R 0402)

IDT (SA00007ZU00) SD034412080 SD00000AD80 SE00000QL10 SE076104K80


X7680231L10 (412 +-1% 0402) (27 +-1% 0402) (1U +-10% 0402) (.1U 16V K X7R 0402)

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/03/29 2019/03/29
Thunderbolt Re-driver
Issued Date Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 45 of 101
5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/03/29 2019/03/29 Title

Reversed
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 46 of 101
5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/03/29 2019/03/29 Title

Reversed
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 47 of 101
5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/03/29 2019/03/29 Title

Reversed
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 48 of 101
5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/03/29 2019/03/29 Title

Reversed
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 49 of 101
5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/03/29 2019/03/29 Title

Reversed
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 50 of 101
5 4 3 2 1
5 4 3 2 1

I/O PADS 3.3V IO 1.8V IO LL2 need close to rUL11.6 and placement the same layer
LL1 need close to rUL10.6 and placement the same layer
ISOLATEB RL1, RL4 connect RL1, RL4 NC LL4 need close to rUL13.6 and placement the same layer
CLKREQB RL2, RL3 NC RL2, RL3 connect
LANWAKEB

2.5V 1.8V
PERSTB
GPI
GPIO8
UL10 UL11

+3VALW_LAN 4 5 LL1 +VDD25


+3VALW_LAN
4 5 LL2 +VDD18 5/9 vendor advice
PGND NC 1UH_AHP252010HF-1R0M_20% PGND NC 1UH_AHP252010HF-1R0M_20%
+DVDD3318 +3VALW_LAN 3
IN LX
6 1 2 3
IN LX
6 1 2
RTL8125CG RL24 RL25 Voltage of VDD18

22U_0603_6.3V6M
CL20 1 1
RL1 1 2 0_0402_5% +VDD18 1 2 SW R_25_PG 2 7 1 @ 2 @EMI@ @EMI@ 1 2 SW R_18_PG 2 7 SW R_25_PG
1@
+3VALW_LAN
D D
1 1 1 1 1

47.5K_0402_1%
PG EN

1
PG EN

1
ES sample 50K 21.5K

CL24
RL20 100K_0402_1% RL57 0_0402_5% CL21 CL28 CL29 CL22 CL23 RL23 100K_0402_1% CL25 CL26 CL27

20K_0402_1%
2.5V_FB 1.8V_FB

1
RL2 1 @ 2 0_0402_5% 1 8 1 8

RL21

RL24
FB SGND FB SGND
2.0V
2 2

22U_0603_6.3V6M
CL1 1 CL2 1 9 9
PGND 2 2 2 PGND 2 2 2

100P_0402_50V8J

2200P_0402_25V7K

6800P_0402_25V7K

22U_0402_6.3V6M

22U_0402_6.3V6M

100P_0402_50V8J

22U_0402_6.3V6M

22U_0402_6.3V6M
2

2
2.5V_FB 1.8V_FB

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D
SY8003EDFC_DFN8_2X2 SY8003EDFC_DFN8_2X2
Close to DVDD3318

2
2 2
MP sample 50K 25K 1.8V
pin41, 46

1
RL22 RL25
15K_0402_1% 10K_0402_1%

0.9V

2
UL13
+3VALW_LAN +3VALW
+3VALW_LAN 4 5 LL4 +VDD09

3.3V
PGND NC 1UH_AHP252010HF-1R0M_20%
POW _MODE1
RL3 1 @ 2 4.7K_0402_5% 3
IN LX
6 1 2 +3VALW_LAN
1 POW _EXT_SW R
RL4 1 2 4.7K_0402_5% 1 1 CL103 1 2 2 7 1 1
PG EN +AVDD33

1
51.1K_0402_1%
CL118 CL117 RL42 100K_0402_1% CL101 CL102 1 @ RL30 1 2
0.9V_FB

RL41
1 8 CL104 CL40 CL41 CL42 CL43 CL44 0_0603_5%
2 FB SGND

22U_0603_6.3V6M
4.7U_0805_10V4Z 0.1U_0402_16V7K 9 1 1 1 1 1
2 2 PGND 2 2

100P_0402_50V8J

22U_0402_6.3V6M
0.9V_FB 2

22U_0402_6.3V6M
+3VALW_LAN SY8003EDFC_DFN8_2X2
2 10uF close to AVDD33

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D
UL14
2 2 2 2 2
pin 4, 12, 20, 28, 84
1 4/3 vendor advice
OUT

1
5 RL41 (50K), RL43
IN 2 1 RL43(100K). 100K_0402_1%
+DVDD3318 GND

22U_0603_6.3V6M
CL120
4
<59> EN_W OL# EN 3 1 2
OCB +3VS
1 RL69
LAN_GPI

2
RL5 1 2 4.7K_0402_5% CL119 10K_0402_5% 2
SY6288D20AAC_SOT23-5
1 2 4.7K_0402_5% PCIE_WAKE#
RL6
2

0.1U_0402_16V7K
@ RL58 1 2 10K_0402_5% CLKREQ_PCIE#4
+DVDD33 RL44 1 2
0_0603_5%
@ RL8 1 2 4.7K_0402_5% PCIRST# CL45 1 CL46 1

Close to DVDD33

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D
+3VS
2 2
pin34, 71
RL9 1 2 1K_0402_5% ISOLATE#
UL1
RL10 1 2 15K_0402_5%

<13> PCIE_PRX_DTX_P15
CL5 2 1 0.1U_0402_16V7K
PCIE_PRX_C_DTX_P15
PCIE_PRX_C_DTX_N15
57 33 +DVDD09
HSOP DVDD09_1

LAN power Noise for measurement Power Sequence for measurement


CL6 2 1 0.1U_0402_16V7K 56 44

2.5V
<13> PCIE_PRX_DTX_N15
C +3VALW_LAN PCIE_PTX_C_DRX_P15
HSON DVDD09_2 50 C

<13> PCIE_PTX_DRX_P15
CL7 2 1 0.1U_0402_16V7K
PCIE_PTX_C_DRX_N15
61
HSIP
DVDD09_3
DVDD09_4
51 +VDD25
CL8 2 1 0.1U_0402_16V7K 62 72
LAN_GPIO0 <13> PCIE_PTX_DRX_N15 HSIN DVDD09_5
RL52 1 @ 2 10K_0402_5% 73

+3VALW < 30mV (Vpeak to Vpeak) +3VALW Rising time (10%~90%)>0.5mS, <100mS +AVDD25
RL51 1 @ 2 10K_0402_5% 58 DVDD09_6 RL45 1 2
<15> CLK_PCIE_P4 REFCLK_P +DVDD18
+VDD25 < 30mV (Vpeak to Vpeak) +VDD25 Rising time (10%~90%)>0.5mS, <100mS
59 35 CL47 CL48 CL49 CL50 CL51 0_0603_5%
<15> CLK_PCIE_N4 REFCLK_N DVDD18_1 52 1 1 1 1 1

+VDD18 < 30mV (Vpeak to Vpeak) +VDD18 Rising time (10%~90%)>0.5mS, <100mS
PCIRST# 45 DVDD18_2 70
CLKREQ_PCIE#4
+3VALW_LAN <11,42,52,58> PCIRST# 42 PERSTB DVDD18_3

+VDD09 < 30mV (Vpeak to Vpeak) +DVDD33 +VDD09 Rising time (10%~90%)>0.5mS, <100mS Close to AVDD25
<15> CLKREQ_PCIE#4 CLKREQB

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D
34
DVDD33_1 2 2 2 2 2
pin10, 14, 26, 83, 86
RL11 1 2 2.49K_0402_1% 82 71
LAN_GPIO1 RSET DVDD33_2
RL54 1 @ 2 10K_0402_5%
RL53 1 @ 2 10K_0402_5% 41 +DVDD3318
The power sequence :
DVDD3318_1 46
PCIE_WAKE# DVDD3318_2

+3VALW>+VDD25>+VDD18>+VDD09
43
<12,58> PCIE_WAKE# ISOLATE# 49 LANWAKEB 1 +AVDD09
ISOLATEB AVDD09_1 7
AVDD09_2 17
CKXTAL1 RL12 1 EMI@ 2 33_0201_1% CKXTAL1_R 79 AVDD09_3 23
+3VALW_LAN 2 33_0201_1% CKXTAL2_R CKXTAL1 AVDD09_4

EEPROM
CKXTAL2 RL13 1 EMI@ 78 80
CKXTAL2 AVDD09_5 +DVDD25_UPS
TP@ PAD~D T360 76 9/11:change from SE000000K80 to SE00000UC00*2 RL46 1 2
CK25_XTAL 3 +AVDD18 0_0603_5%
AVDD18_1 5 CL52 1 CL53 1
AVDD18_2 19 CL90 1 2 1U_0402_6.3V6K~D
Close to DVDD25_UPS
UL4 LAN_ACTIVITY# AVDD18_3

0.1U_0402_16V7K~D
TP@ PAD~D T364 31 21 CL91 1 2 1U_0201_6.3V6M
LAN_GPIO4 LAN_SPISCK LED0/GPIO2 AVDD18_4
pin66

10U_0603_6.3V6M~D
1 8 TP@ PAD~D T365 32 81 CL121 1 2 1U_0201_6.3V6M
LAN_SPISCK 2 CS VCC 7 LAN_SPICS# 37 LED1/EESK/SPISCK/GPIO3 AVDD18_5 2 2
YL1 TP@ PAD~D T370 CL92 1 2 1U_0201_6.3V6M
1 @ 2 LAN_SPISI 3 SK NC 6 4 3 1 2 33P_0201_25V8J LAN_SPISO 38 SPICSB/GPIO5
CKXTAL2 TP@ PAD~D T366 CL122 1 2 1U_0201_6.3V6M
LAN_SPISO 4 DI ORG 5 LAN_SPISI 39 LED2/EEDO/SPISO/GPIO6 2
RL60 CL4 TP@ PAD~D T367 CL93 1 2 1U_0201_6.3V6M
DO GND LAN_GPIO8 LED3/EEDI/SPISI/GPIO7 AVDD18_LDO_OUT_1
0.1U_0402_10V6K

4.7K_0402_5% 1 2 1 CKXTAL1 1 2 TP@ PAD~D T371 40 6 CL123 1 2 1U_0201_6.3V6M


AT93C46D-TH-T_TSSOP8 33P_0201_25V8J CL3 GPIO8 AVDD18_LDO_OUT_2 11 CL94 1 2 1U_0201_6.3V6M
AVDD18_LDO_OUT_3
CL100

@ 25MHZ_20PF_7M25000153 13 CL124 1 2 1U_0201_6.3V6M


ORG pin:
AVDD18_LDO_OUT_4
LAN_MDIP0
18 +VDD18
Connected to VCC : 64 words of 16 bits each
2 87 AVDD18_LDO_OUT_5 22 CL95 1 2 1U_0201_6.3V6M

1.8V
LAN_MDIN0 MDIP0 AVDD18_LDO_OUT_6
Connected to GND : 128 words of 8 bits each YL1 Crystal requirement must follow Spec 88 27 CL125 1 2 1U_0201_6.3V6M
LAN_MDIP1
LAN_MDIN1
8 MDIN0 AVDD18_LDO_OUT_7 77 CL96 1 2 1U_0201_6.3V6M +AVDD18 RL47 1 2
9 MDIP1 AVDD18_LDO_OUT_8 85 CL126 1 2 1U_0201_6.3V6M CL54 CL55 CL56 CL57 CL58 0_0603_5%
LAN_MDIP2 15 MDIN1 AVDD18_LDO_OUT_9 CL97 1 2 1U_0201_6.3V6M 1 1 1 1 1
LAN_MDIN2 16 MDIP2 10 CL127 1 2 1U_0201_6.3V6M
LAN_MDIP3 24 MDIN2 AVDD25_1 14 CL98 1 2 1U_0402_6.3V6K~D
Close to AVDD18
LAN_MDIN3 MDIP3 AVDD25_2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D
25 26
MDIN3 AVDD25_3 2 2 2 2 2
pin3, 5, 19, 21, 81
83
AVDD25_4 86 +AVDD25
RL14 1 2 4.7K_0402_1% 69 AVDD25_5
POW _MODE1
POW _EXT_SW R
68 SCANM 4 +AVDD33
67 POW_MODE1 AVDD33_1 12
POW_EXT_SWR AVDD33_2 20
LAN_GPI 48 AVDD33_3 28
TP@ PAD~D T361
LAN_GPIO0
+VDD25 TP@ PAD~D T368
LAN_GPIO1
29 GPI
GPIO0/PPS_PIN
AVDD33_4
AVDD33_5
84
TP@ PAD~D T369 30
B TP@ PAD~D T362
LAN_GPIO4 36 GPIO1 53 +EVDD18 B
GPIO4/EECS/SCL EVDD18 +DVDD18 RL48 1 2
47 54 +EVDD09 0_0603_5%
74 NC1 EVDD09_1 55 CL59 1 CL60 1 CL61 1
75 NC2 EVDD09_2 63
Close to DVDD18
2

NC3 EVDD09_3

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D
RL70
+DVDD25_UPS
pin35, 52, 70
0_0603_5% 60
GND1 DVDD25_UPS
66
+DVDD18_UPS 9/11:change from SE000000K80 to SE00000UC00*2 2 2 2
89 65
GND2 DVDD18_UPS 64 CL99 1 2 1U_0201_6.3V6M

0.9V
UL2 DVDD09_UPS
1

1 24 RJ45_CT3 1 2 RJ45_CT CL129 1 2 1U_0201_6.3V6M


TDCT1 TXCT RL15 75_0402_1%~D
LAN_MDIN0 2 23 RJ45_MDIN0 E3000-CG QFN 88P E-LAN CTRL

LAN_MDIP0
TD1+ TX1+
RJ45_MDIP0
+VDD09
3 22
TD1- TX1-
4 21 RJ45_CT2
RL16 1 2 75_0402_1%~D +AVDD09 RL38 1 2
LAN_MDIN1
TDCT2 TXCT2
RJ45_MDIN1
CL66 CL67 CL68 CL69 CL70 0_0603_5% +EVDD18 RL50 1 2
5 20 1 1 1 1 1 0_0603_5%
TD2+ TX2+ CL62 1 CL63 1
LAN_MDIP1 6 19 RJ45_MDIP1

Close to AVDD09
TD2- TX2-

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

0.1U_0402_16V7K~D

10U_0603_6.3V6M~D
Close to EVDD18
RJ45_CT1 2 2 2 2 2
pin1, 7, 17, 23, 80
7 18 RL17 1 2 75_0402_1%~D RL71 2 1 130_0402_5%~D
TDCT3 TXCT3 +3VALW_LAN 2 2
pin53
LAN_MDIN2 RJ45_MDIN2 1
8 17 @EMI@
TD3+ TX3+ CL31
LAN_MDIP2 9 16 RJ45_MDIP2
TD3- TX3- 470P_0402_50V7K
2
10 15 RJ45_CT0
RL18 1 2 75_0402_1%~D
TDCT4 TXCT4
LAN_MDIN3 11 14 RJ45_MDIN3
TD4+ TX4+ 2
LAN_MDIP3 12 13 RJ45_MDIP3
CL10 +DVDD09 RL39 1 2 +DVDD18_UPS RL49 1 2
TD4- TX4- 10P_1808_3KV7K~D @EMI@ CL109 2 1 470P_0402_50V7K 0_0603_5% 0_0603_5%
1 CL72 CL71 2 CL73 2 CL74 2 CL75 2 CL76 2 CL64 1 CL65 1
SANTA_130456-931 2
@EMI@ CL108 2 1 470P_0402_50V7K
Close to DVDD09 Close to DVDD18_UPS

0.1U_0402_16V7K~D

10U_0603_6.3V6M~D
SP050009M00

pin33, 44, 50, 51, 72, 73 pin65


BOTH_QVP2014R 12
Green-Orange LED+
EVT SP050009K00
1 1 1 1 1 1 2 2

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M
LAN_SPISO
DVT SP050009L00(change to SP050009M00) RL67 2 1 130_0402_5%~D 13
Orange LED-
LAN_SPISCK
0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

RL68 2 1 130_0402_5%~D 11
1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K

Green LED- 14
RJ45_MDIP0 1 GND
PR1+ 15
RJ45_MDIN0 2 GND
PR1-
RJ45_MDIP1 3
1 1 1 1 1 1 1 1
RJ45_MDIP2
PR2+ +EVDD09 RL40 1 2
4 0_0603_5%
A PR3+ CL77 1 CL78 1 CL79 1 CL80 1 CL81 1 CL82 1 A
2 2 2 2 2 2 2 2 RJ45_MDIN2 5
Place 0.1uF x 2 close to each
PR3-

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D
EMI@ CL9

EMI@ CL110

EMI@ CL111

EMI@ CL112

EMI@ CL113

EMI@ CL114

EMI@ CL115

EMI@ CL116

RJ45_MDIN1
pin54, 55, 63
6
PR2- 2 2 2 2 2 2
RJ45_MDIP3 7
PR4+
RJ45_MDIN3 8
PR4-
RL66 2 1 330_0402_5% 9
+3VALW_LAN Yellow LED+
LAN_ACTIVITY#
@EMI@ 2 1 10
CL107 470P_0402_50V7K Yellow LED-

JLAN

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/03/29 2019/03/29
LAN RTL8125
Issued Date Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 51 of 101
5 4 3 2 1
5 4 3 2 1

+3VS +3V_WLAN
+3V_WLAN closed to pin 2, 4

BIOS debug
1 2
@ RN20 0_0805_5%

+3V_PCH

10P_0402_50V8J

4.7U_0805_10V4Z

0.1U_0402_10V7K

22U_0603_6.3V6M~D

0.1U_0402_10V7K~D
1 1 1 1 1
@
CNV_BRI_PRX_DTX_R

CN5
RF@

CN2

CN1
1 2 RN1 1 2 0_0402_5%
<14> UART_2_PRXD_DTXD

CN3

CN4
RN122 0_0805_5% @
RN120 1 2 0_0402_5% CNV_RGI_PTX_DRX_R 2 2 2 2 2 +1.8VALW
<14> UART_2_PTXD_DRXD

D D

CNV_RF_RESET#_D RH722 1 2 1K_0201_5%


CLKREQ_CNV#_D RH723 1 2 1K_0201_5%

M.2 2230 SLOT (Type E)


+3V_PCH

CNV_RF_RESET# RH724 1 @ 2 1K_0201_5%


JW LAN
1 2 CLKREQ_CNV# RH725 1 @ 2 1K_0201_5%
3 GND 3.3VAUX 4
<14> USB20_P14 USB_D+ 3.3VAUX
5 6
<14> USB20_N14 USB_D- LED1#
7 8
CNVI@ RN105 1 2 0_0201_5% CNV_PRX_DTX_N1_R 9 GND PCM_CLK 10 CNV_RF_RESET#_D
<15> CNV_PRX_DTX_N1 CNV_PRX_DTX_P1_R SIDO_CLK PCM_SYNC
CNVI@ RN106 1 2 0_0201_5% 11 12
<15> CNV_PRX_DTX_P1 SDIO_CMD PCM_IN CLKREQ_CNV#_D
13 14
CNVI@ RN103 1 2 0_0201_5% CNV_PRX_DTX_N0_R 15 SDO_DAT0 PCM_OUT 16
CNVI Rx
<15> CNV_PRX_DTX_N0 CNV_PRX_DTX_P0_R SDO_DAT1 LED2#
CNVI@ RN104 1 2 0_0201_5% 17 18
For CNVI
<15> CNV_PRX_DTX_P0 SDO_DAT2 GND
19 20
CNVI@ RN102 1 2 0_0201_5% CLK_CNV_PRX_DTX_N_R 21 SDO_DAT3 UART_WAKE# 22 CNV_BRI_PRX_DTX_R CNVI@ RN109 1 2 0_0201_5%
<15> CLK_CNV_PRX_DTX_N CLK_CNV_PRX_DTX_P_R SDIO_WAKE# UART_RX CNV_BRI_PRX_DTX <15>
CNVI@ RN101 1 2 0_0201_5% 23
<15> CLK_CNV_PRX_DTX_P SDIO_RESET#

32 CNV_RGI_PTX_DRX_R <15>
C 33 UART_TX 34 CNV_RGI_PRX_DTX_R CNVI@ RN111 1 2 0_0201_5% C
GND UART_CTS CNV_RGI_PRX_DTX <15>
CN6 2 1 0.1U_0402_16V7K PCIE_PTX_C_DRX_P16 35 36 CNV_BRI_PTX_DRX_R <15>
<13> PCIE_PTX_DRX_P16 PETP0 UART_RTS
CN7 2 1 0.1U_0402_16V7K PCIE_PTX_C_DRX_N16 37 38 CNVI@ RN118 1 2 0_0201_5%
EC detect debug card insert
<13> PCIE_PTX_DRX_N16 PETN0 RESERVED EC_TX <58>
39 40 CNVI@ RN119 1 2 0_0201_5%
GND RESERVED EC_RX <58>
41 42
<13> PCIE_PRX_DTX_P16 PERP0 RESERVED
43 44
<13> PCIE_PRX_DTX_N16 PERN0 COEX3
45 46
47 GND COEX2 48
<15> CLK_PCIE_P5 REFCLKP0 COEX1
49 50 SUSCLK <68>
<15> CLK_PCIE_N5 REFCLKN0 SUSCLK
51 52
GND PERST0# BT_OFF#_R PCIRST# <11,42,51,58,68>
53 54
<15> CLKREQ_PCIE#5 CLKEQ0# W_DISABLE2# W L_OFF#_R
55 56
57 PEWAKE0# W_DISABLE1# 58
CNVI@ RN123 1 2 0_0201_5% CNV_PTX_C_DRX_N1 59 GND I2C_DATA 60
<15> CNV_PTX_DRX_N1 CNV_PTX_C_DRX_P1 RSRVD/PETP1 I2C_CLK
CNVI@ RN124 1 2 0_0201_5% 61 62
For CNVI
<15> CNV_PTX_DRX_P1 RSRVD/PETN1 ALERT REFCLK_CNV_R
63 64 CNVI@ RN113 1 2 0_0201_5%
CNVI TX
CNV_PTX_C_DRX_N0 GND RESERVED REFCLK_CNV <15>
CNVI@ RN125 1 2 0_0201_5% 65 66
<15> CNV_PTX_DRX_N0 CNV_PTX_C_DRX_P0 RSRVD/PERP1 RESERVED
CNVI@ RN126 1 2 0_0201_5% 67 68
<15> CNV_PTX_DRX_P0 RSRVD/PERN1 RESERVED +3V_WLAN
69 70
CNVI@ RN108 1 2 0_0201_5% CLK_CNV_PTX_DRX_N_R 71 GND RESERVED 72

closed to pin 72, 74


<15> CLK_CNV_PTX_DRX_N RESERVED 3.3VAUX
CNVI@ RN107 1 2 0_0201_5% CLK_CNV_PTX_DRX_P_R 73 74
<15> CLK_CNV_PTX_DRX_P RESERVED 3.3VAUX
75
GND
+3V_WLAN 2 1 EC_TX
77 76 100K_0402_5% RN30
MTG77 MTG76

Device side
1 1

22U_0603_6.3V6M~D

0.1U_0402_10V7K~D
LOTES_APCI0128-P005A
+3V_PCH CONN@

CN8

CN9
B B

Device side
2 2

CNV_RF_RESET#_D +3V_PCH
1

RN7
100K_0201_5%

PCH side
3

CLKREQ_CNV#_D

1
RN9
2

PCH side
100K_0201_5%

3
6

5
4

CNV_RF_RESET# 2 QN8B DN1 MAIN@


<12> CNV_RF_RESET# WL_OFF#_R
L2N7002DW1T1G_SC88-6 2 1
W L_OFF# <14>
6

QN9B RB751S40T1G_SOD523-2

4
1

QN8A CLKREQ_CNV# 2 L2N7002DW1T1G_SC88-6


<12> CLKREQ_CNV#
1

CNVI@ 75K_0402_1% L2N7002DW1T1G_SC88-6 DN2 MAIN@


RN6 BT_OFF#_R 2 1
BT_OFF# <14>
1

CNVI@ 75K_0402_1% QN9A RB751S40T1G_SOD523-2


2

RN8 L2N7002DW1T1G_SC88-6
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/03/29 2019/03/29 Title

WLAN(w/CNVi)/BT
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 52 of 101
5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/03/29 2019/03/29 Title

Reversed
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 53 of 101
5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/03/29 2019/03/29 Title

Reversed
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 54 of 101
5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/03/29 2019/03/29 Title

Reversed
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 55 of 101
5 4 3 2 1
A B C D E

1 1

M/B to Audio/B

JAUDIO
1
B+_BIAS 2 1
3 2
4 3
5 4
<58> BEEP# 6 5
<58> DEPOP#_EC 6
7
To EC <58> EC_AMP_RST# 8 7
<58> EC_CODEC_EAPD# 9 8
<42,58,59,68,78,87,89> SUSP# 9
10
<58,62> LID_SW# 11 10
<58> SPK_SEL 11
<58> I2C0_SDA_EC 12
13 12
<58> I2C0_SCL_EC 13
14
<58> AMP_SPI_CS_L1 14
15
2 <58> AMP_SPI_CS_L2 16 15 2
<58> AMP_SPI_CS_R1 16
17
<58> AMP_SPI_CS_R2 18 17
<58> AMP_SPI_MOSI 19 18
<58> AMP_SPI_MISO 19
20
<58> AMP_SPI_SCLK 21 20
22 21
<12> HDA_SPKR 23 22
<12> HDA_SYNC_R 24 23
<12> HDA_SDIN 24
25
<12> HDA_SDOUT_R 26 25
27 26 31
28 27 GND 32
<12> HDA_BIT_CLK_R 29 28 GND 33
<37> MIC_DATA12 29 GND
30 34
<37> MIC_CLK 30 GND

ACES_50473-0300M-P01

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/03/29 2019/03/29 Title
Audio Conn.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 56 of 101
A B C D E
5 4 3 2 1

D D

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/03/29 2019/03/29 Title

Reversed
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 57 of 101
5 4 3 2 1
5 4 3 2 1

+3VALW +3VLP
+VCCST_PECI +1.05V_VCCST +3VLP

1 2 +3VALW_EC EMI@ LE1 +EC_VCCA 1 @ 2


RE78 0_0603_5% FBMA-L11-160808-800LMT_0603 RH613 0_0402_5%
1 @ 2 1 2 1

1
RE79 0_0603_5% 1 1 2 2 RE684
CE29 CE30 @EMI@ @EMI@ CE171 10K_0402_5%
1
CE31 CE32 CE172 0.1U_0402_10V7K
1000P_0402_50V7K 1000P_0402_50V7K 0.1U_0402_10V7K 2

0.1U_0402_10V7K
2 2 1 1

0.1U_0402_10V7K

2
+3VLP 2 ECAGND SW TRAP
ECAGND <82>

CE171 Close to UE5


@ @

1
RE77 RE685
0_0402_5% 10K_0402_5%
RE705 1 @ 2 0_0402_5%
D RE706 1 2 0_0402_5% +VCCST_PECI D
+1.8VALW

2
2
CE34 +3VALW
2 1
2 1 0.1U_0402_16V7K CE174
.047U_0402_16V7K +V18R 1 2 +3VALW_EC
RE24 0_0603_5%

Ra

2
1 2 PCIRST_R# RE64
<11,42,51,52,68> PCIRST#
RE681 0_0201_5% 100K_0402_1%

111

117

124
1 2 PM_SLP_S4_R# UE5 RE66

22
33
96

67
<12,78,90> PM_SLP_S4#

9
RE680 0_0201_5%
1 2 PM_SLP_S3_R# AD_BID

VCC0

VCC_IO2
VCC_LPC
VCC
VCC
VCC

AVCC
PECI_VTT
<6,12,62,78,83,85> PM_SLP_S3#

1
RE679 0_0201_5%
PM_SLP_S5_R#
1 2 LPC/eSPI & MISC 1

Rb
<12,62> PM_SLP_S5#
RE678 0_0201_5% 1 21
<14> ISH_GP1 GA20/GPIO00 PWM0/GPIO0F CDRA_LED_WHITE_MOS <74>

2
RE646 1 2 0_0201_5% 2 23 RE66 CE28 @S RES 1/16W 20K +-1% 0402
<11> ESPI_KB_RST# KBRST#/GPIO01 PWM1/GPIO10 BEEP# <56>
<11> ESPI_SERIRQ
3
SERIRQ PWM Output FANPWM0/GPIO12
26
CPU_FAN_PWM <77> 27K_0402_1%
2
0.1U_0402_10V7K SD028200280
4 27
<11> ESPI_FRAME# LFRAME#/ESPI_CS# FANPWM1/GPIO13 GPU_FAN_PWM <77>
5
<11> ESPI_IO3 LAD3/ESPI_IO3
7 CE35 2 1 100P_0402_50V8J ECAGND
<11> ESPI_IO2

1
8 LAD2/ESPI_IO2 63
<11> ESPI_IO1 LAD1/ESPI_IO1 AD0/GPIO38 VCIN_ BATT_TEMP <82,85>
10 64
<11> ESPI_IO0 LAD0/ESPI_IO0 AD1/GPIO39 PCIE_WAKE# <12,51>
65
AD2/GPIO3A AD_BID ADP_I <82,85>
<11> CLK_PCI_ESPI PCIRST_R#
12
PCICLK/ESPICLK AD Input AD3/GPIO3B
66
13 75
EVT 00.SD028000080 0_0402_5%
PCIRST#/GPIO05 AD4/GPIO42 USBCHG_DET_EC# <71>
37 76 1 2 EC_ENBKL <37>
ECRST# AD5/GPIO43
DVT-1 01.SD034120280 12K_0402_1%
RE694 1 2 0_0201_5% 20 RE701 0_0201_5%
<14> EC_SCI# SCI#/GPIO0E
38

DVT-2 GCE/TRIPOD 02.SD034150280 15K_0402_1%


<14,63> TP_INT# CLKRUN#/GPIO1D
14
<11> ESPI_RST# GPIO07/ESPI_RST# 68
DVT-2 HSB 03.SD028200280 20K_0402_5%
DA0/GPIO3C AMP_SPI_CS_L2 <56>
DA Output DA1/GPIO3D
70 SW TRAP

DVT-2.1 04.SD034270280 27K_0402_1%


55 71
<56> DEPOP#_EC KSI0/GPIO30 DA2/GPIO3E ACOK_ISL95338_1 <82>
56 72
PVT 05.SD034330280 33K_0402_1%
<62,74> CALDERA_PRSNT# KSI1/GPIO31 DA3/GPIO3F ACOK_ISL95338_2 <82>
57
<63> PW R_R_EC KSI2/GPIO32 EC_CLK1
06.SD034430280 43K_0402_1%
58 83 RE668 1 2 0_0201_5%
<71> CTL1 KSI3/GPIO33 SCL2/GPIO4A EC_DAT1 I2C0_SCL_EC <56>
EDICS 59 84 RE669 1 2 0_0201_5% I2C0_SDA_EC <56>
07.SD034560280 56K_0402_1%
EDICLK 60 KSI4/GPIO34 SDA2/GPIO4B 85
+3VALW KSI5/GPIO35 SCL3/GPIO4C GPU_OVERT# <37>
EDIDI 61 86 1 2
08.SD034750280 75K_0402_1%
KSI6/GPIO36 SDA3/GPIO4D TP_CLK EC_SSD <68>
EDIDO 62 87 RE702 0_0201_5%
KSI7/GPIO37 PSCLK3/GPIO4E TP_CLK <63>
09.SD034100380 100K_0402_1%
TP_DATA
<71> CTL2
39
KSO0/GPIO20 PS2 Interface PSDAT3/GPIO4F
88
TP_DATA <63>
RE201 1 2 10K_0402_5% SPK_SEL 40
-------------------------------------------------------------------------------------------
<74> CDR_TXRX_GOOD KSO1/GPIO21
41
C <75> TOBII_PW R_EN# HT_EN KSO2/GPIO22 C

10.SD034130380 130K_0402_1%
42 97
KSO3/GPIO23 SHICS#/GPIO60 DGPU_PW R_EN <14,37>
RE689 1 2 10K_0402_5% GPU_STRAP5_EC 43 98

11.SD034160380 160K_0402_1%
<15> CLKREQ_PEG#6 KSO4/GPIO24 SHICLK/GPIO61 I2C_INT <63>
<56> SPK_SEL
44
KSO5/GPIO25 Int. K/B GPIO SHIDO/GPIO62
99
ME_EN <12>
45 109
Matrix
12.SD034200380 200K_0402_1%
<74> CALDERA_RST# KSO6/GPIO26 VCIN0/GPIO78 VCIN0_PH1 <82>
RE688 1 2 10K_0402_5% DEPOP#_EC 46
<74> CALDERA_PWRGD KSO7/GPIO27
13.SD000001B80 240K_0402_1%
47
<37> EN_INVPW R KSO8/GPIO28
48 119
14.SD00000G280 270K_0402_1%
<83> OFF_FWEN_1 KSO9/GPIO29 MISO_SHR_ROM/GPIO5B AMP_SPI_MISO <56>
49 120
<74> CALDERA_ON KSO10/GPIO2A MOSI_SHR_ROM/GPIO5C AMP_SPI_MOSI <56>
SPI ROM SPICLK_SHR_ROM/GPIO58
15.SD034330380 330K_0402_1%
50 126
<71> PW RSHARE_EN_EC# KSO11/GPIO2B AMP_SPI_SCLK <56>
51 128

16.SD028430380 430K_0402_5%
+3VALW_EC <72> USB_PWR_EN1 KSO12/GPIO2C SPICS#_SHR_ROM/GPIO5A AMP_SPI_CS_L1 <56>
52
<63> PW R_B_EC KSO13/GPIO2D
53
17.SD034560380 560K_0402_1%
<37> GPU_STRAP5_EC KSO14/GPIO2E PM_SLP_S4_R#
RE90 54 73
<37> TS_EN
18.SD00000AL80 750K_0402_1%
+3VS 5 4 EC_SMB_CK1 81 KSO15/GPIO2F AD6/GPIO40 74 SYS_PWROK
EC_SMB_DA1 <63> TP_EN KSO16/GPIO48 AD7/GPIO41 PD_IRQ# SYS_PWROK <12>
6 3 82 89
EC_SMB_CK2 <37,82> EC_AC_BAT# KSO17/GPIO49 LOCK#/GPIO50 PD_IRQ# <44>
7 2 90
EC_SMB_DA2 GPIO52 EC_AMP_RST# <56>
8 1 91
EC_SMB_CK1 CAPSLED#/GPIO53 FW PG_ISL95338_2 <82,84>
<44,45,82,83,84,85> EC_SMB_CK1 EC_SMB_DA1
77
SCL0/GPIO44 GPIO WDT_LED/GPIO54
92
EC_EAPD# PW R_LED# <63>
+3VALW
2.2K_0804_8P4R_5% 78 93
<44,45,82,83,84,85> EC_SMB_DA1 EC_SMB_CK2 SDA0/GPIO45 SCROLED#/GPIO55
79 95 2
<12,37,63,74,77> EC_SMB_CK2 EC_SMB_DA2 SCL1_BT/GPIO46 GPIO56 SYSON <78,87>
80 121 2
<12,37,63,74,77> EC_SMB_DA2 SDA1_BT/GPIO47 GPIO57/XCLK32K IMVP_VR_ON <78,91,96> EC_AMP_RST#
<56> AMP_SPI_CS_R2
15
SCL4/GPIO08 SMBUS GPIO59/DPWROK
127
TBT_PCIE_WAKE# <12,42>
CE42 10K_0402_5% 2 1 RE695
19 ESD@ CE38 0.1U_0402_10V7K
<82> PS_ID_2 EC_ESB_CLK SDA4/GPIO0D 1 LID_SW#
17 0.1U_0402_10V7K 10K_0402_5% 2 1 RE70
<59> EC_ESB_CLK EC_ESB_DAT SCL5/GPIO0B 1
18 100
PCH_PWROK <59> EC_ESB_DAT SDA5/GPIO0C FANFB2/RSMRST# EC_RSMRST# <12,79> +3VS
2 1 101
FANFB3/GPIO64 VR_PWRGD <91>
RE75 10K_0402_5% 102
VCIN1/GPIO65 VCOUT1_PROCHOT# VCIN1_ADP_PROCHOT <82>
USB_PWR_EN1 GPIO VCOUT1/GPIO66
103
2 1 104 @
PM_SLP_S3_R# VCOUT0/GPIO67 VCOUT0_MAIN_PWR_ON# <86> EC_CODEC_EAPD#
RE645 10K_0402_5% 6 105 100K_0402_1% 2 1 RE696
GPIO04 GPIO68 BKOFF# <37>
16 106
<82> PS_ID_1 OWM/GPIO0A GPIO69 PBTN_OUT# <12>
25 107 2 1 RE74
<63> TP_LED_EN PWM2/GPIO11 GPIO6A PM_SLP_S5_R# PCH_PWR_EN <12,37,78,88,98>
28 108 43_0402_1%
<77> CPU_FAN_FB 29 FANFB0/GPIO14 GWG/GPIO6B +3VLP
<77> GPU_FAN_FB EC_TX FANFB1/GPIO15
PM_SLP_S3_R# <52> EC_TX EC_RX
30
TXD/GPIO16 GPIO 100P_0402_50V8J 2 1 CE40
2 1 31 110
<52> EC_RX PCH_PWROK RXD/GPIO17 AC_IN/GPIO79 VCIN1_AC_IN <12,62,83,84,85>
32 112
<12> PCH_PWROK AMP_SPI_CS_R1 POWER_FAIL1/GPIO18 GPIO7A/ALW_PWR_EN EC_ON <86>
CE41 ESD@ 34 114 ON/OFF# ON/OFF# 100K_0402_1% 2 1 RE63
<56> AMP_SPI_CS_R1 PWM3/GPIO19 GPIO7B/ON/OFFBTN# LID_SW# ON/OFF# <63,77>
0.1U_0402_10V7K
<83> FWPG_ISL95338_1
36
NUMLED#/GPIO1A GPIO GPIO7C/LID_IN
115
LID_SW# <56,62>
116

Reserve for abnormal shutdown


PM_SLP_S5_R# GPIO7D SUSP# <42,56,59,68,78,87,89>
2 1
118 EC_PECI_R 1 2
B
PECI EC_PECI <6> B
CE45 ESD@ 122 43_0402_1% RE76
<88> +1VALWP_PGOOD XCLKI/GPIO5D
0.1U_0402_10V7K 123
<6,78> H_VCCST_PWRGD GPIO5E

Please close to EC
@
125 1 2 EC_RSMRST#
GPIO7E CDR_BTN# <74> <86> POK
DE2 RB751V-40_SOD323-2
AGND

@
GND
GND
GND
GND
GND

1 2 PCH_PWROK
KB9542Q-B_LQFP128_14X14 DE3 RB751V-40_SOD323-2
SA0000BEZ10
11
24
35
94
113

69

W=20 mils
@
JDBG
1 EDICS ECAGND 2 1 +3VALW
1 2 EDICLK
2 3 EDIDI LE2
3 4 EDIDO FBMA-L11-160808-800LMT_0603
4 5 HT_EN +3VALW
5

1
RE700 +3V_TOUCH
CVILU_CH31052VA00-NH 10K_0402_5%

Test point only

1
RE698 EC_EAPD# TP_CLK RE100 2 1 4.7K_0402_5%

2
+3VS 10K_0402_5%
<6,82,85,91> H_PROCHOT# TP_DATA RE101 2 1 4.7K_0402_5%

3
QE64B
DMN66D0LDW-7_SOT363-6~D

2
1

RE84 5
10K_0402_5% ESD@
TC20 CLK_PCI_ESPI LID_SW# 1 2

6
TC21 ESPI_SERIRQ CE43 0.1U_0402_10V7K

4
TC22 ESPI_FRAME# D QE64A ESD@
2
1

TC23 ESPI_IO0 QE2 2 1 2 VCOUT1_PROCHOT# 2 DMN66D0LDW-7_SOT363-6~D PCH_PWROK 1 2


ESPI_IO1 <56> EC_CODEC_EAPD#
TC24 2N7002W-T/R7_SOT323-3 G CE44 0.1U_0402_10V7K
TC25 ESPI_IO2 RE85 ESD@
ESPI_IO3
S 1 SYS_PWROK
TC26 CE51 53.6K_0402_5% @ 1 2
3

1
1
0.033U_0402_25V RE699 CE46 0.1U_0402_10V7K
10K_0402_5%
2

2
A A

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/03/29 2019/03/29
P44-EC ENE-KB9542 QFN
Issued Date Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 58 of 101
5 4 3 2 1
5 4 3 2 1

D D

+3VALW +3VALW
1

1
47K_0402_5%

47K_0402_5%
UE10 UE6
EC_ESB_CLK EC_ESB_CLK
RE530

RE704
1 13 1 13
<58> EC_ESB_CLK ESB_CLK TEST_EN# ESB_CLK TEST_EN#
2 14 EC_RTCRST 2 14
<62> BATT_CHG_LED# GPIO00 GPIO08/CAS_DAT <83> OFF_PMOS_1 GPIO00 GPIO08/CAS_DAT
2

2
3 15 3 15
RST# GPIO09 LDO_EN <63> RST# GPIO09
EC_ESB_DAT 4 16 EC_ESB_DAT 4 16
<58> EC_ESB_DAT ESB_DAT GPIO0A OFF_FW EN_2 <84> 2 ESB_DAT GPIO0A

0.1U_0402_16V7K~D
2
0.1U_0402_16V7K~D

<62> BATT_LOW _LED# 5 17 <84> OFF_PMOS_2 5 17


GPIO01 GPIO0B PTP_LID_CLOSE# <63> GPIO01 GPIO0B

CE202
1
CE63

6 18 1 2 6 18
1 <63> ELC_EC# GPIO02 GPIO0C/PWM0 3V_ELC_ON <62> <63> PTP_KBBL# GPIO02 GPIO0C/PWM0
RE703 0_0201_5%
7 19 7 19
<51> EN_W OL# GPIO03 GPIO0D/PWM1 TBT_RESET_N_EC <42,45> GPIO03 GPIO0D/PWM1
8 20 EC_SRTCRST 8 20
<44> PD_RESET GPIO04 GPIO0E/PWM2 GPIO04 GPIO0E/PWM2
9 21 9 21
to eDP conn
<37> LCD_TEST GPIO05 GPIO0F/PWM3 TBT_S5_OFF# <45> GPIO05 GPIO0F/PWM3
C 10 22 RTC_CELL 10 22 C
<74> CDRA_LED_RED_MOS GPIO06 GPIO10/ESB_RUN# GPIO06 GPIO10/ESB_RUN#
11 23 11 23
<82> EC_EN_AMP GPIO07/CAS_CLK GPIO11/BaseAddOpt GPIO07/CAS_CLK GPIO11/BaseAddOpt
12 24 +3VALW 12 24 +3VALW
GND VCC GND VCC

GND

GND
W=60 mils W=60 mils
1 1

.1U_0402_16V7K

.1U_0402_16V7K
KC3810_QFN24_4X4 KC3810_QFN24_4X4

CE62

CE201
25

25
2 2

<12> PCH_RTCRST# <12> PCH_SRTCRST#

QE5A QE5B
DMN66D0LDW -7_SOT363-6~D DMN66D0LDW -7_SOT363-6~D

3
+RTC_CELL
2 EC_RTCRST 5 EC_SRTCRST

1
RE650 RE693

4
D 10K_0402_5% 10K_0402_5%
1

B QE58 2 RTC_CELL B
2N7002W -T/R7_SOT323-3 G

2
S
1
3

RE662 +1.8VALW +1.8VS_EC


10K_0402_5%
2

1 RE50 1 @ 2 0_0603_5%
+3VALW CE204

4.7U_0805_10V4Z
2

UE13
1 2 EC_ESB_CLK 5 1
RE642 4.7K_0402_5% IN OUT
1 2 EC_ESB_DAT 2
GND 1

22U_0603_6.3V6M
CE203
RE643 4.7K_0402_5%
4 3 1 2 +3VS
<42,56,58,68,78,87,89> SUSP# EN OC RE707
1 2
CE205 SY6288C20AAC_SOT23-5 10K_0402_5%

2
0.1U_0402_16V7K

A A
3V_ELC_ON RE83 1 2 10K_0402_5%

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/03/29 2019/03/29 Title

EC ENE-KB9022
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 59 of 101
5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/03/29 2019/03/29
Reserved
Issued Date Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 60 of 101
5 4 3 2 1
A

1K
4 Free Fall Sensor SMBUS Address [0x1D]
SMBUS Address [0x9A] 1K
+3VS
6

BE26 PCH_SMBCLK 253 DIMM1 SMBUS Address [0xA0]


BF26 PCH_SMBDATA 254

253 DIMM2 SMBUS Address [0xA2]


254

253 DIMM3 SMBUS Address [0xA4]


254
499

+3VS
253 DIMM4 SMBUS Address [0xA6]
499 254
SMBUS Address [0x6A]
Cannon Lake
PCH-H BF25 SML0CLK 11 PI6CEQ20200 15 JTP SMBUS Address [0x2C]
BE24 SML0DATA 10 16

10 U2407 SMBUS Address [0x9A]


1K 4.7K 9 Thermal sensor

+3V_PCH +3VS
1K 4.7K

BF27 SML1CLK
N-MOS
EC_SMB_CK2 8
U2408 SMBUS Address [0x98]
N-MOS Thermal sensor
BE27 SML1DATA EC_SMB_DA2 7
4.7K

+3VS
4.7K

N-MOS UG9
2.2K
N-MOS
VGA_SMB_CK2 BJ8 GPU SMBUS Address [0x9E]
VGA_SMB_DA2 BH8
+3VS
2.2K
UM8 SMBUS Address [0xB2]
79 EC_SMB_CK2 50 PCIE redriver
80 EC_SMB_DA2 49
2.2K
16 JPK SMBUS Address [0xC2]
1 1

+3VALW Per-key KB
2.2K 17

0 ohm PU703
77 EC_SMB_CK1
0 ohm
SCL 4
Power Charger SMBUS Address [0x12]
78 EC_SMB_DA1 SDA 3
100 ohm
5 PBATT1
100 ohm
6 SMBUS Address [0x16]

ENE
0 ohm PUS1
22 ISL95338
0 ohm SMBUS Address [0x90]
KB9542QB 21
0 ohm PUS2
22 ISL95338
0 ohm
21 SMBUS Address [0x92]
UT4
B5 TPS65982
A5 SMBUS Address [0x70]
UT6
50 DS80PCI402SQ SMBUS Address [0x]
49 4.7k
UT7
11 PI6CEQ20200 SMBUS Address [0x] 4.7k
+3VALW
10
UE6
17 EC_ESB_CLK 1 KB3810
18 EC_ESB_DAT 4
AMP
119/120/126 AMP_SPI_MISO/AMP_SPI_MOSI/AMP_SPI_SCLK TAS2557
128 AMP_SPI_CS_L1 SMBUS Address [?] 1
UE10
KB3810
4
AMP
68 AMP_SPI_CS_L2 TAS2557
34 AMP_SPI_CS_R1
15 AMP_SPI_CS_R2 AMP
TAS2557

AMP
TAS2557

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/03/29 2019/03/29
SMB/I2C Block Diagrams
Issued Date Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 61 of 101
A
5 4 3 2 1

9/11:change from SE000000K80 to SE00000UC00*2

+3.3V_ELC LE4 +VDDA


BLM15AG121SN1D_L0402_2P

1 2 +3.3V_ELC
.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
1 1 1 1 1 1 1 1

.1U_0402_16V7K
1

1
CE59

CE60

CE1

CE6

CE170 SE00000UC00

CE177 SE00000UC00

CE7 SE00000UC00

CE9 SE00000UC00
@

CE169
RE657
2 2 2 2 2 2 2 2 10K_0402_5%
2
<14> ELC_BOOT_MODE

2
1
D D

BOOT0 = 1 HW bootloader
RE5
100K_0402_5%

BOOT0 = 0 SW bootloader
EMI@
RE18

2
0_0201_5% +3VS +3VS +3VALW
+3.3V_ELC
OSC24M_IN_R 1 2 OSC24M_IN

RE3 @

2
1M_0402_5%~D RE690 RE691
1 2 OSC24M_OUT_R 1 2 OSC24M_OUT 10K_0402_5% 10K_0402_5% RE4
10K_0402_5% UE1
EMI@

2
G
YE1 RE19 44

1
12MHZ 12PF +-10PPM X3S012000DC1H-X 0_0201_5% 3 1 NRST 7 BOOT0
<14> ELC_RESET NRST
1 OSC24M_OUT
1 3 QE59 6

D
2 4 2N7002W-T/R7_SOT323-3 CE8 OSC24M_IN 5 PF1-OSC_OUT
1 1 0.1U_0402_16V7K 4 PF0-OSC_IN
CE2 CE5 2 +VDDA 3 PC15-OSC32_OUT
15P_0402_50V 15P_0402_50V PC14-OSC32_IN
2 2 9
+3.3V_ELC 8 VDDA
VSSA
48
36 VDD4 +3.3V_ELC
24 VDD3
1 VDD2
+3.3V_ELC VDD1
47
+3.3V_ELC 35 VSS3
23 VSS2
VSS1

1
+3.3V_ELC RE692
10K_0402_5%

2
RE8 2 RE6 RE7
PC13
10K_0402_5% 100K_0402_5% 100K_0402_5%
PCIE_GEN3#_GEN2 28 38

2
27 PB15 PA15 37 SYS_SWCLK
26 PB14 PA14 34 SYS_SWDIO

1
1

1
RE1 RE2 1 2 25 PB13 PA13 33
<56,58> LID_SW# PB12 PA12 USB20_P4 <14>
1K_0402_1% 1K_0402_1% DE1 22 32
C <58,74> CALDERA_PRSNT# PB11 PA11 USB20_N4 <14> C
SDMK0340L-7-F_SOD323-2~D 21 31
<74> CDR_ON_ELC 46 PB10 PA10 30
2 45 PB9 PA9 29 +3.3V_ELC

2
43 PB8 PA8 17 SPI_MOSI JELC
<63,74> I2C_DAT PB7 PA7 SPI_MISO SYS_SWDIO
42 16 1 2
<63,74> I2C_CLK PB6 PA6 SPI_CLK 1 2 SYS_SWCLK
41 15 3 4
40 PB5 PA5 14 SPI_CS# 5 3 4 6
39 PB4 PA4 13 BATT_LOW _LED 7 5 6 8
RE651 1 2 0_0402_5% 20 PB3 PA3 12 SLP_S3 9 7 8 10 NRST
<75> TOBII_INT# BATT_CHG_LED PB2 PA2 SLP_S5 9 10
19 11
ACIN# 18 PB1 PA1 10
PB0 PA0
STM32F070CBT6TR_LQFP48_7X7 CVILU_CH51102M100-0P
SA0000AW J20 CONN@
+3.3V_ELC
1

RE15
100K_0402_5% SPI_CLK 15_0402_5% 2 EMI@ 1 RE11 SPI_CLK_R

SLP_S3 2 1
2

12P_0402_50V8J CE173 @EMI@

+3.3V_ELC

RE11,CE173Close UE1
3

5 QE1A
<6,12,58,78,83,85> PM_SLP_S3#
D
G

S
DMN66D0LDW-7_SOT363-6
1

RE16
4

100K_0402_5%

SLP_S5
2

+3.3V_ELC +3VALW +3.3V_ELC


UE2
3

5 QE4A SPI_MOSI 15_0402_5% 2 1 RE9 5 2 1 2 SPI_MISO


<12,58> PM_SLP_S5# DI SO
D

+3.3V_ELC RE10 15_0402_5%


G

DMN66D0LDW-7_SOT363-6
1

RE17 UE9 SPI_CLK_R 6


S

100K_0402_5% 5 1 CLK
4

IN OUT 1 2 SPI_CS# 1
B B
2 RE12 10K_0402_5%~D CS
1 GND 1 1
ACIN# CE22 CE64 CE65 1 2 7
2

4.7U_0603_10V 4 3 1 2 0.1U_0402_16V7K 10U_0402_6.3V6M RE13 10K_0402_5%~D HOLD


EN OC +3VS
1 2 3
2 SY6288C20AAC_SOT23-5 RE20 2 2 RE14 10K_0402_5%~D WP
3

5 QE3A +3.3V_ELC 10K_0402_5% 8 4


<58,85> VCIN1_AC_IN +3.3V_ELC VCC VSS
D
G

DMN66D0LDW-7_SOT363-6

.1U_0402_16V7K
GD25Q80CSIGR SOP8
S

1
4

CE19
RE21
100K_0402_5%
+3.3V_ELC behavior
<59> 3V_ELC_ON 2

S0 S3 S4 S5
+3.3V_ELC BATT_LOW _LED
2

AC IN (battery low) ON ON ON ON
AC IN (battery full) ON ON OFF OFF
1

RE23 2 QE3B
<59> BATT_LOW _LED#
D

100K_0402_5%
G

DMN66D0LDW-7_SOT363-6
BATT only ON ON OFF OFF
S
1

BATT_CHG_LED
2

Update PWR BTN LED behavior when AC IN (battery full) at S4


6

2 QE1B
<59> BATT_CHG_LED#
D
G

S
DMN66D0LDW-7_SOT363-6
1

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/03/29 2019/03/29
ELC (1) STM32F070CB
Issued Date Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 62 of 101
5 4 3 2 1
5 4 3 2 1

To power board
+5VALW +5VALW

+5VALW_LED +5VALW_LED
CONN@
ACES_50611-0060B-P01
1 2
PW R_R# 3 1 2 4 PW R_R#
ELC_EC# ELC_EC# PW R_G# 5 3 4 6 PW R_G#
<59> ELC_EC# PW R_B# PW R_B#

1
7 5 6 8
RE158 RE156 ON/OFF# 9 7 8 10 ON/OFF#
<58> ON/OFF# 11 9 10 12
10K_0402_5% 10K_0402_5%

5
11 12

AD0 1
PW R_R_7313# 4 3 PW R_R# PW R_G_7313# 4 3 PW R_G# JPW R

2
AD1 1
QE22B QE21B

AD2 0

1
+3.3V_ELC +3.3V_ELC +3.3V_ELC DMN66D0LDW -7_SOT363-6~D DMN66D0LDW -7_SOT363-6~D
D RE157 RE155 D

AD3 0
1K_0402_1% 1K_0402_1%

1
RE25 1

6 2

6 2
4.7K_0402_1% CE24
UE3 .1U_0402_16V7K
QE22A QE21A
1

RE40 RE43 24 27 2 2 DMN66D0LDW -7_SOT363-6~D 2 DMN66D0LDW -7_SOT363-6~D

To Tron Rear LED

2
RESET Vcc <58> PW R_R_EC
4.7K_0402_1%~D 4.7K_0402_1%~D
3 HEAD_LED_R_DRV#

24 pins
I2C_CLK OUT0 HEAD_LED_G_DRV# HEAD_LED_R_DRV# <37>
25 4

1
<62,74> I2C_CLK I2C_DAT 26 SCL OUT1 5 HEAD_LED_B_DRV# HEAD_LED_G_DRV# <37>
2

<62,74> I2C_DAT SDA OUT2 TP_LED_R#_DRV# HEAD_LED_B_DRV# <37> +5VS


6
AD0_0 31 OUT3 8 TP_LED_G#_DRV#
AD1_0 32 A0 OUT4 9 TP_LED_B#_DRV# 2 1 .1U_0402_16V7K
CE86
AD2_0 1 A1 OUT5 10 PW R_R_7313#
AD3_0 2 A2 OUT6 11 PW R_G_7313#
A3 OUT7 PW R_B_7313# JTRON
14
12 OUT8 15 TRONT_LED_R_DRV# 1
TRONT_LED_G_DRV#
1

13 N.C. OUT9 16 2 1
N.C. OUT10 TRONT_LED_B_DRV# +5VS 2
RE42 RE44 28 17 3

Power LED
29 N.C. OUT11 19 TRONB_LED_R_DRV# 4 3
4.7K_0402_1%~D 4.7K_0402_1%~D +5VALW 1
30 N.C. OUT12 20 TRONB_LED_G_DRV# TRONB_LED_R_DRV# 5 4
CE175
N.C. OUT13 21 TRONB_LED_B_DRV# TRONT_LED_R_DRV# 6 5
.1U_0402_16V7K
2

OUT14 22 ELC_EC# TRONB_LED_G_DRV# 7 6


TRONT_LED_G_DRV#
1

OUT15

1
RE31 2 8 7
7 23 +5VALW TRONB_LED_B_DRV# 9 8
10K_0402_5%~D RE154
18 GND GND 33 TRONT_LED_B_DRV# 10 9
10K_0402_5%
GND GND

5
+5VALW 11 10
PW R_B_7313# 4 3 PW R_B# 12 11
2

2
TLC59116FIRHBR_VQFN32_5X5 13 12

1
RE28 14 13
QE13B TRONB_LED_R_DRV# 15 14
100K_0402_5%
TRONT_LED_R_DRV#

1
DMN66D0LDW -7_SOT363-6~D 16 15
TRONB_LED_G_DRV# 17 16
RE160 QE8
S
Power_LED TRONT_LED_G_DRV#

3
1K_0402_1% 2 18 17

2
TRONB_LED_B_DRV#
G
19 18
TRONT_LED_B_DRV# 20 19

6 2
LP2301ALT1G 1P SOT-23-3 21 20
+5VS 21
22
+5VS

6
22
D
QE13A 2 QE4B 1 23

1
<58> PW R_LED# 23
D

2 DMN66D0LDW -7_SOT363-6~D CE87 24


G

<58> PW R_B_EC DMN66D0LDW -7_SOT363-6 +5VALW_LED 24


.1U_0402_16V7K 25
S

1 G1
CE176 26

1
2 .1U_0402_16V7K G2

1
2 ACES_50238-02471-002

NOTE:
C C

CE86 close to JTRON PIN1 and PIN3


CE175 close to JTRON PIN2 and PIN4
CE87 close to JTRON PIN21 and PIN23
1 2
+3VALW
RT111 0_0603_5%

CE176 close to JTRON PIN22 and PIN24


1 @ 2 +3V_TOUCH
+3VS
RT110 0_0603_5% UT5

1 7
2 VIN VOUT 8
VIN VOUT

Touchpad LED circuit


3 6
<58> TP_EN ON CT
1 1
4

2200P_0402_25V7K

0.1U_0402_10V6K
VBIAS 5

CT117
GND 9

CT118
GND 2 2
9/11:change from SE000000K80 to SE00000UC00*2
B+_BIAS +5VS AOZ1336_DFN8_2X2
Q2409
6 AO6424A_TSOP6 +5VS_TP_LED
5
300K_0402_5%~D

2
2

.1U_0402_16V7K

1 1 4

To touchpad module
+3V_TOUCH
R179

S
C29

1 1 +3V_TOUCH
2
1U_0201_6.3V6M
C2508 SE00000UC00

1U_0201_6.3V6M
C2501 SE00000UC00

5V_TP_LED
3 G
1

1
RE663 +5VS_TP_LED
2 2
10K_0201_5%

5V_TP_LED
+3VALW

TP_LED_B_DRV

10U_0603_6.3V6M~D

39_0402_5%~D
RT89
1

2
EN_TPLED

1
JTP

TP_LED_G_DRV
+3V_TOUCH

CT116
18
GND18

470K_0402_5%~D
RT88
1 17
1 GND17

TP_LED_R_DEV
2 +3V_TOUCH
L2N7002WT1G 1N SC-70-3

1.5M_0402_5%~D

0.1U_0402_25V6K~D

D
1

1
R180

2 @ 16

2
<58> TP_LED_EN

1
16

GND
C2509

G RE661 15
2 TP_LED_B#_DRV# 14 15
Q2410 S 10K_0201_5% TP_LED_G#_DRV#

1
14

GND
RT90 13
3

TP_LED_R#_DRV#

3
8.2_0402_5%~D RE33 12 13
2

12

ATTN

DMN66D0LDW-7_SOT363-6~D
10K_0201_5% 11

2
2 1 5 10 11

QT2B
+3V_TOUCH TP_INT# 10

BACK LIGHT
9

2
<14,58> TP_INT# PTP_KBBL# 8 9
<59> PTP_KBBL# PTP_LID_CLOSE# 8

LID CLOSE
7

4
<59> PTP_LID_CLOSE# 7
B 6 B
TP_CLK_R
6

1
6

3VS
CT115 RE654 1 2 0_0402_5% 5
<58> TP_CLK TP_DATA_R 5
0.047U_0402_25V7K 1 RE655 1 2 0_0402_5% 4
<58> TP_DATA 4
DMN66D0LDW-7_SOT363-6~D

2 3
QT2A

PS2_CLK
2

0.1U_0402_10V6K
1 2 0_0402_5% I2C_0_SCL_R 2 3
RE71
<14> I2C_0_SCL I2C_0_SDA_R 2

C2
1 2 0_0402_5% 1

PS2_DAT
RE653
2 <14> I2C_0_SDA 1
1

ACES_51625-01601-001

GND
1
100P_0402_50V8J~D
CT114

CONN@
RE659 1 @ 2 0_0402_5%

I2C_CLK
<12,23,24,25,26,67> PCH_SMBCLK
RE660 1 @ 2 0_0402_5%
2 <12,23,24,25,26,67> PCH_SMBDATA

I2C_DATA

+5VS

Per Key pin define


JPK
21
1 GND1
2 1

Pin1~5 VBUS
RE200 1 @EMI@ 2 0_0201_5% 3 2
+3VS 4 3
4

Pin6 NC
5
DLM0NSN900HY2D_4P 6 5
USB20_N10_R 6

Pin7~9 GND
4 3 7
<14> USB20_N10 4 3 8 7
8
1

Pin10 D-
9
1 2 USB20_P10_R USB20_N10_R 10 9
RE656
<14> USB20_P10 1 2 USB20_P10_R 10

Pin11 D+
10K_0402_5% 11
LE7 EMI@ 12 11
12

Pin12~14 GND
13
2

1 @EMI@ 2 14 13
14

Pin15 I2C_INT
RE202 0_0201_5% 15
<58> I2C_INT 16 15
<12,37,58,74,77> EC_SMB_CK2 16

Pin16 I2C_CLK
17
<12,37,58,74,77> EC_SMB_DA2 18 17
<59> LDO_EN 18

Pin17 I2C_DAT
19
A 20 19 22 A
20 GND2

Pin18 LDO_EN
ACES_51519-02001-P01

Pin19~20 NC
3

CONN@
TVNST52302AB0_SOT523-3
DK3
ESD@

TVNST52302AB0_SOT523-3
DK2
ESD@

TVNST52302AB0_SOT523-3
DK1
ESD@
1

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/03/29 2019/03/29
ELC (2) TP/PW/HEAD/TRON/PK
Issued Date Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 63 of 101
5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/03/29 2019/03/29 Title

ELC (4) Per Key


Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 64 of 101
5 4 3 2 1
A B C D E

1 1

2 2

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/03/29 2019/03/29
Reserve
Issued Date Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 65 of 101
A B C D E
5 4 3 2 1

+1.8VALW

10K_0201_5% 2 1 RS11 PCH_ACC1_INT1


10K_0201_5% 2 1 RS12 PCH_GYRO_INT2

+3VS +3VS_ACC

+3VS_ACC
D D
1 @ 2
RH614 0_0402_5% 1K_0402_5% 2 1 RS18 ISH_I2C0_SCL
1K_0402_5% 2 1 RS19 ISH_I2C0_SDA

+3VS_ACC
+3VS_ACC US2

5 4 ACC1_INT1 RH619 1 2 0_0402_5% PCH_ACC1_INT1


VDDIO INT1 GYRO_INT2 PCH_ACC1_INT1 <14>
8 9 RH1015 1 2 0_0402_5% PCH_GYRO_INT2
+3VS_ACC VDD INT2 PCH_GYRO_INT2 <14>

RS10 2 1 10K_0201_5% GYRO_ADD 1


SDO/SA0 +3VS_ACC

To PCH ISH 2
SDx NC
10
.1U_0402_16V7K

.1U_0402_16V7K

1 1 3 12 RS9 1 2 100K_0201_5%
SCx CS
RH617 1 2 0_0402_5% I2C3_SCL 13
<14> ISH_I2C0_SCL I2C3_SDA SCL
CS18

CS17

RH618 1 2 0_0402_5% 14
2 2 <14> ISH_I2C0_SDA SDA
11 7
NC GND 6
GND

LSM6DSLUSTR_LGA14_2P5X3

CS18,CS17 Close to US2


C C

+3VS_ACC

+3VS_ACC 10K_0201_5% 2 1 RS16 @ ACC_ADDRESS


+3VS_ACC
@
@ RH31 1 2 0_0402_5% US3
<14> I2C2_SCL
@ RH32 1 2 0_0402_5%
<14> I2C2_SDA
9
VDD
.1U_0402_16V7K

.1U_0402_16V7K

1 1 10
@ @ VDD_IO 12 ACC_INT1 @ RH622 1 2 0_0402_5% PCH_ACC1_INT1
@ RH620 1 2 0_0402_5% ISH_I2C1_SCL_R 1 INT1 11 ACC_INT2 @ RH623 1 2 0_0402_5% PCH_GYRO_INT2
<14> ISH_I2C1_SCL ISH_I2C1_SDA_R SCL/SPC INT2
CS20

CS19

@ RH621 1 2 0_0402_5% 4
2 2 <14> ISH_I2C1_SDA ACC_ADDRESS SDA/SDI/SDO
3
@ RS15 1 2 100K_0201_5% 2 SA0/SDO 6
+3VS_ACC CS GND
B 7 B
5 GND 8
RES GND

LIS2DH12TR_LGA12_2X2

CS20,CS19 Close to US3

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/03/29 2019/03/29 Title

Reversed
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 66 of 101
5 4 3 2 1
A B C D E F G H

+5VS +5V_HDD
1 1
@ JP3
1 2
1 2
JUMP_43X118
JHDD
1
+5V_HDD <13> SATA_PRX_C_DTX_N0 1
2

HDD/SSD5
<13> SATA_PRX_C_DTX_P0 2
3
4 3
<13> SATA_PTX_C_DRX_N0 4
5
<13> SATA_PTX_C_DRX_P0 5
6
6

10U_0603_25V6M

0.1U_0402_25V6K~D

1000P_0402_50V7K~D
7
<11> DEVSLP0 7

10P_0402_50V8J

22U_0402_6.3V6M
1 1 1 1 8
SATA_GP0 9 8
9

CV1073
@RF@

CS1

CS6

CS5

CS16
10
RS17 1 @ 2 0_0201_5% 11 10
2 2 2 2 <13> PCH_SATADET# FFS_INT2_CONN 11
12

2
13 12
14 13
15 14
16 15
17 16
+5V_HDD 17
18
19 18
20 19
21 20
22 G1
2 23 G2 2
24 G3
G4
ACES_50406-02071-001
CONN@

+3VS
+3VS

Free Fall Sensor for HDD


.1U_0402_16V7K

10U_0603_6.3V6M

1 1

2
RS2
10K_0201_5%
CS7

CS2

2 2

1
US1
LNG3DM 10
<13> SATA_GP0
SATA_GP0

1 RES 13
14 VDD_IO RES 15
VDD RES 16
11 RES
<11,15> FFS_INT1 FFS_INT2 INT 1
9 5
<11,15> FFS_INT2 INT 2 GND 12
3 7 GND 3
6 SDO/SA0
<12,23,24,25,26,63> PCH_SMBDATA SDA / SDI / SDO
4
<12,23,24,25,26,63> PCH_SMBCLK SCL/SPC 2
8 NC 3
CS NC
KXCNL-1010_LGA16_3X3

+5VS

+3VS
1

RS1
100K_0201_5%
@
2
G

FFS_INT2 3 1 1 2 FFS_INT2_CONN
S

DS1
QS3 SDM10U45-7_SOD523-2~D
L2N7002W T1G_SC-70-3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/03/29 2019/03/29 Title

SATA HDD Connector


Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 67 of 101
A B C D E F G H
5 4 3 2 1

PCIe / SATA SSD PCIe / SATA SSD


JSSD1 , 2280 +3VALW_SSD
JSSD2 , 2280 +3VALW_SSD

JSSD2
JSSD1 1 2
1 2 3 GND 3P3VAUX 4
3 GND 3P3VAUX 4 5 GND 3P3VAUX 6
D GND 3P3VAUX <13> PCIE_PRX_DTX_N9 PERn3 NC EC_SSD D
5 6 7 8
<13> PCIE_PRX_DTX_N20 PERn3 NC EC_SSD <13> PCIE_PRX_DTX_P9 PERp3 NC
7 8 9 10
<13> PCIE_PRX_DTX_P20 PERp3 NC EC_SSD <58> GND DAS/DSS#
9 10 11 12
GND DAS/DSS# <13> PCIE_PTX_C_DRX_P9 PETn3 3P3VAUX
11 12 13 14
<13> PCIE_PTX_C_DRX_N20 PETn3 3P3VAUX <13> PCIE_PTX_C_DRX_N9 PETp3 3P3VAUX
13 14 15 16
<13> PCIE_PTX_C_DRX_P20 PETp3 3P3VAUX GND 3P3VAUX
15 16 17 18
GND 3P3VAUX <13> PCIE_PRX_DTX_N10 PERn2 3P3VAUX
17 18 19 20
<13> PCIE_PRX_DTX_N19 PERn2 3P3VAUX <13> PCIE_PRX_DTX_P10 PERp2 NC
19 20 21 22
<13> PCIE_PRX_DTX_P19 PERp2 NC GND NC
21 22 23 24
GND NC <13> PCIE_PTX_C_DRX_P10 PETn2 NC
23 24 25 26
<13> PCIE_PTX_C_DRX_N19 PETn2 NC <13> PCIE_PTX_C_DRX_N10 PETp2 NC
25 26 27 28
<13> PCIE_PTX_C_DRX_P19 PETp2 NC GND NC
27 28 29 30
GND NC <13> PCIE_PRX_DTX_N11 PERn1 NC
29 30 31 32
<13> PCIE_PRX_DTX_N18 PERn1 NC <13> PCIE_PRX_DTX_P11 PERp1 NC
31 32 33 34
<13> PCIE_PRX_DTX_P18 PERp1 NC GND NC
33 34 35 36
GND NC <13> PCIE_PTX_C_DRX_N11 PETn1 NC
35 36 37 38
<13> PCIE_PTX_C_DRX_N18 PETn1 NC <13> PCIE_PTX_C_DRX_P11 PETp1 DEVSLP DEVSLP1 <11>
37 38 39 40
<13> PCIE_PTX_C_DRX_P18 PETp1 DEVSLP DEVSLP4 <11> GND NC
39 40 41 42
GND NC <13> PCIE_PRX_DTX_P12 PERn0/SATA-B+ NC
41 42 43 44
<13> PCIE_PRX_DTX_P17 PERn0/SATA-B+ NC <13> PCIE_PRX_DTX_N12 PERp0/SATA-B- NC
43 44 45 46
<13> PCIE_PRX_DTX_N17 PERp0/SATA-B- NC GND NC
45 46 47 48
GND NC <13> PCIE_PTX_C_DRX_N12 PETn0/SATA-A- NC
47 48 49 50 PCIRST#
<13> PCIE_PTX_C_DRX_N17 PETn0/SATA-A- NC <13> PCIE_PTX_C_DRX_P12 PETp0/SATA-A+ PERST#
49 50 PCIRST# 51 52
<13> PCIE_PTX_C_DRX_P17 PETp0/SATA-A+ PERST# PCIRST# <11,42,52,58> GND CLKREQ# CLKREQ_PCIE#2 <15>
51 52 53 54
GND CLKREQ# CLKREQ_PCIE#1 <15> <15> CLK_PCIE_N2 REFCLKN PEWake#
53 54 55 56
<15> CLK_PCIE_N1 REFCLKN PEWake# <15> CLK_PCIE_P2 REFCLKP NC
55 56 57 58
<15> CLK_PCIE_P1 REFCLKP NC GND NC
57 58
GND NC

67 68 SUSCLK
67 68 SUSCLK SATA_GP1 69 NC SUSCLK(32kHz) 70
SATA_GP4 NC SUSCLK(32kHz) SUSCLK <12,52> PEDET(OC-PCIe/GND-SATA) 3P3VAUX
69 70 71 72
71 PEDET(OC-PCIe/GND-SATA) 3P3VAUX 72 73 GND 3P3VAUX 74
73 GND 3P3VAUX 74 75 GND 3P3VAUX
C 75 GND 3P3VAUX GND 76 C
GND 76 GND1 77
GND1 77 GND2
GND2 LOTES_APCI0181-P001A
LOTES_APCI0096-P002A CONN@
CONN@

+3VALW_SSD +3VALW_SSD
+3VALW
2

R363 R365

4.4m ohm/6A
10K_0201_5% 10K_0201_5%

10U_0603_6.3V6M

10U_0603_6.3V6M
1 1
1

SATA_GP4 SATA_GP1

C2515

C2514
<13> SATA_GP4 <13> SATA_GP1
+3VSP_SSD
2 2

PEDET Module Type PEDET Module Type 1


U16
IN OUT
6
2
3 IN 7

0 SATA 0 SATA
+5VALW VBIASVCC_PAD

47U_0603_6.3V6M

10U_0603_6.3V6M
B 4 5 1 1 B
<42,56,58,59,78,87,89> SUSP# ON GND

C2513

C2512
AOZ1334DI-02_DFN8-7_3X3

1 PCIe 1 PCIe
2 2
1
C2516
0.1U_0402_10V7K
2

JSSD1 JSSD2 +3VSP_SSD +3VALW_SSD


+3VALW_SSD
+3VALW_SSD +3VALW_SSD @ JP6
1 2
1 2
JUMP_43X118
.047U_0402_16V7K

.047U_0402_16V7K

22U_0402_6.3V6M

22U_0402_6.3V6M

22U_0402_6.3V6M

150U_B2_6.3VM_R35M

150U_B2_6.3VM_R35M
33P_0402_50V8J

33P_0402_50V8J

1 1 1 1 1 1 1 1 1
.047U_0402_16V7K

.047U_0402_16V7K

22U_0402_6.3V6M

22U_0402_6.3V6M

22U_0402_6.3V6M
33P_0402_50V8J

33P_0402_50V8J
1 1 1 1 1 1 1
C623

C621

C618

C617

C622

C635

C636

+ +
C625

C627

C620

C628

C624

C637

C638

C631

C641
2 2 2 2 2 2 2
2 2 2 2 2 2 2 2 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/03/29 2019/03/29
NGFF SSD
Issued Date Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 68 of 101
5 4 3 2 1
A B C D E

1 1

2 2

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/03/29 2019/03/29
Reserved
Issued Date Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 69 of 101
A B C D E
A B C D E

1 1

2 2

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/03/29 2019/03/29
Reserved
Issued Date Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 70 of 101
A B C D E
5 4 3 2 1

+3VLP +3VLP +3VLP +3VLP

USB charge for DC S5


+5V_USB_PWR1
+5VALW

Power share

SDMK0340L-7-F_SOD323-2
1

1
220K_0402_5%
1 RU4
100K_0402_5% RU5 DU8 1
CU7 1 CU26

W=80 mils
0.1U_0402_16V7K CU47 0.1U_0402_16V7K
2 UU1 0.1U_0402_10V7K

2
1 12 2
IN OUT 2
13 9
<14> USB_OC0# FAULT# NC CU27

5
D D
1
2 11 CHR_USB20_N1 2 1 2 NC 4

P
<14> USB20_N1 DM_OUT DM_IN CHR_USB20_P1 A Y USBCHG_DET_D <86>
3 10
<14> USB20_P1 DP_OUT DP_IN 2.2U_0603_6.3V6K

G
+3VLP RU1 1 2 10K_0402_5% 4 15 RU2 2 1 19.1K_0402_1% UU5
ILIM_SEL ILIM1

1
5 16 RU3 2 1 19.1K_0402_1% RU6

3
<58> PWRSHARE_EN_EC# EN ILIM0 1M_0402_5%
6
<58> CTL1 CTL1 TC7SZ14FU_SSOP5~D
7 14
<58> CTL2 CTL2 GND
+3VLP 1 2 8 17 DU6

2
RU7 10K_0402_5% CTL3 GPAD 2 1
TPS2546RTER_QFN16_3X3 USBCHG_DET#
USBCHG_DET_EC# <58>
Layout Note: For RF SDMK0340L-7-F_SOD323-2
Place near JUSB1 1
CU28
1
CU29
+5V_USB_PWR1 0.1U_0402_16V7K 0.1U_0402_16V7K
2 2

150U_B2_6.3VM_R35M
1

0.5P_0402_50V8

10P_0402_50V8J

47U_0805_6.3V6M

10U_0603_6.3V6M~D
LU3 1 1 1 1
+
CHR_USB20_P1 CHR_USB20_P1_R

CU242

CU243

CU6

CU2

CU3
4 3
4 3
2 2 2 2 2
CHR_USB20_N1 CHR_USB20_N1_R +5V_USB_PWR1

RF@

RF@
1 2
1 2

DLM0NSN900HY2D_4P
EMI@
JUSB1
1
CHR_USB20_P1_R 3 VBUS
CHR_USB20_N1_R 2 D+
C USB3_PRX_RD_DTX_P6 6 D- C
USB3_PRX_RD_DTX_N6 5 SSRX+
USB3_PTX_C_DRX_P6 9 SSRX-
USB3_PTX_C_DRX_N6 8 SSTX+ 11
USBCHG_DET# 10 SSTX- GND 12
+3VS 4 DET# GND 13
7 GND GND 14
GND GND
1 2
CU108 0.1U_0402_16V7K TAIWI_USB050-10B7CRL-TWD
CONN@
1 2 UU6 ESD@

2
CU109 0.01U_0402_16V7K 1 DU9
13 VDD PESD5V0U2BT_SOT23-3
VDD
SCA00000T00
USB3_A_EQ1 15 4 USB3_B_EQ1
USB3_A_DE0 16 A_EQ1/SDA_CTL B_EQ1/I2C_ADDR1 3 USB3_B_DE0

1
USB3_A_EQ0 17 A_DE0/SCL_CTL B_DE0/I2C_ADDR0 2 USB3_B_EQ0
USB3_A_DE1 18 A_EQ0/NC B_EQ0/NC 6 USB3_B_DE1
A_DE1/NC B_DE1/NC
1 0.1U_0402_10V7K USB3_PTX_C_RD_DRX_P6
To Conn
CU12 2 19 12 USB3_PTX_RD_DRX_P6 CU114 2 1 0.1U_0402_10V7K USB3_PTX_C_DRX_P6

From PCH
<11> USB3_PTX_DRX_P6 A_INp A_OUTp
CU110 2 1 0.1U_0402_10V7K USB3_PTX_C_RD_DRX_N6 20 11 USB3_PTX_RD_DRX_N6 CU113 2 1 0.1U_0402_10V7K USB3_PTX_C_DRX_N6
<11> USB3_PTX_DRX_N6 A_INn A_OUTn

From Conn
USB3_PRX_RD_DTX_P6 9 22 USB3_PRX_C_RD_DTX_P6 CU111 2 1 0.1U_0402_10V7K
To PCH
USB3_PRX_RD_DTX_N6 B_INp B_OUTp USB3_PRX_C_RD_DTX_N6 USB3_PRX_DTX_P6 <11>
8 23 CU112 2 1 0.1U_0402_10V7K
+3VS B_INn B_OUTn USB3_PRX_DTX_N6 <11>

USB3_PD# 5
7 PD# 10 DU2
@ R371 1 2 4.7K_0402_5% USB3_A_EQ1 USB3_TEST 14 REXT GND 21 USB3_PRX_RD_DTX_N6 1 9 USB3_PRX_RD_DTX_N6
@ R372 1 2 4.7K_0402_5% USB3_A_DE0 24 TEST/NC GND 25
@ R373 1 2 4.7K_0402_5% USB3_A_EQ0 I2C_EN GPAD USB3_PRX_RD_DTX_P6 2 8 USB3_PRX_RD_DTX_P6
@ R374 1 2 4.7K_0402_5% USB3_A_DE1 PS8713BTQFN24GTR2-A_TQFN24_4X4
B USB3_PTX_C_DRX_N6 4 7 USB3_PTX_C_DRX_N6 B
@ R375 1 2 4.7K_0402_5% USB3_TEST @ @
2

USB3_PTX_C_DRX_P6 5 6 USB3_PTX_C_DRX_P6
2K_0402_5%
R393

4.99K_0402_1%
R369

0_0402_5%
R370

@ R376 1 2 4.7K_0402_5% USB3_B_EQ1


@ R377 1 2 4.7K_0402_5% USB3_B_DE0

SC300003Z00 (ESD use)


@ R378 1 2 4.7K_0402_5% USB3_B_EQ0 3
1

USB3_B_DE1
SC300002800 (symbol)
@ R379 1 2 4.7K_0402_5%
TVWDF1004AD0_DFN9
ESD@ SC300003Z00
R406 1 2 4.7K_0402_5% USB3_A_EQ1
R407 1 2 4.7K_0402_5% USB3_A_DE0
R400 1 2 4.7K_0402_5% USB3_A_EQ0
R399 1 2 4.7K_0402_5% USB3_A_DE1

R411 1 2 4.7K_0402_5% USB3_TEST

R402 1 2 4.7K_0402_5% USB3_B_EQ1


R403 1 2 4.7K_0402_5% USB3_B_DE0
R404 1 2 4.7K_0402_5% USB3_B_EQ0
R405 1 2 4.7K_0402_5% USB3_B_DE1

Parade_PS8713B
USB3_TEST
A_EQ0 A_EQ1 B_EQ0 B_EQ1 Recommended EQ LFPS swing adjust. 3.3V tolerant.
Internally pulled down 150KΩ .
A 0 0 0 0 loss up to 9.5dB L: Normal LFPS swing (default) A

H: Tune down LFPS swing


0 1 0 1 loss up to 4.5dB

1 0 1 0 loss up to 13dB

1 1 1 1 loss up to 7.5dB Security Classification Compal Secret Data Compal Electronics, Inc.
2018/03/29 2019/03/29
USB3.0/2.0 TPS2546/PS8713
Issued Date Deciphered Date Title
Both A_EQ&B_EQ have internal pull-down 150k
PD# pin have internal pull-up 150k THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 71 of 101
5 4 3 2 1
5 4 3 2 1

+5VALW +5V_USB_PW R2

+5V_USB_PW R2 +5V_USB_PWR2 +5V_USB_PWR2

1 1 1
CU48 CU46 CU45
10U_0402_6.3V6M 0.1U_0402_10V7K 0.1U_0402_10V7K

47U_0805_6.3V6M

10U_0603_6.3V6M~D
1 1 RF@ 1 RF@ 1
2 2 2
Layout Note: For RF

10P_0402_50V8J

10P_0402_50V8J
W=80 mils
CU101 RF@ CU244 RF@

1
CU10

CU11
D
5
UU3
1
CU102
0.5P_0402_50V8
CU245
0.5P_0402_50V8 Place near JUSB2 JUSB3 D
IN OUT 2 2 2 2

2
2
GND
4 3
<58> USB_PW R_EN1 EN OC USB_OC1# <14>

1 SY6288C20AAC_SOT23-5 1
CU17
CU16 0.1U_0402_16V7K
0.1U_0402_16V7K
2 2

CU49 2 1 0.1U_0402_10V7K USB3_PTX_C_DRX_P7


<14> USB3_PTX_DRX_P7 +5V_USB_PW R2

USB3_PTX_C_DRX_N7 DU12 JUSB2


CU50 2 1 0.1U_0402_10V7K
<14> USB3_PTX_DRX_N7 USB3_PRX_DTX_N7 USB3_PRX_DTX_N7
1 9 1
USB20_N2_R 2 VBUS
USB3_PRX_DTX_P7 USB3_PRX_DTX_P7 2 8 USB3_PRX_DTX_P7 USB20_P2_R 3 D-
<14> USB3_PRX_DTX_P7 D+
4
USB3_PTX_C_DRX_N7 4 7 USB3_PTX_C_DRX_N7 USB3_PRX_DTX_N7 5 GND
C USB3_PRX_DTX_N7 USB3_PRX_DTX_P7 6 STDA_SSRX- 10 C
<14> USB3_PRX_DTX_N7 USB3_PTX_C_DRX_P7 USB3_PTX_C_DRX_P7 STDA_SSRX+ GND
5 6 7 11
USB3_PTX_C_DRX_N7 8 GND GND 12
USB3_PTX_C_DRX_P7 9 STDA_SSTX- GND 13
RU123 1 @EMI@ 2 0_0201_5% STDA_SSTX+ GND
3
ACON_TCRAY-9U1U91
LU4 EMI@ TVW DF1004AD0_DFN9 CONN@
1 2 USB20_N2_R SC300003Z00
<14> USB20_N2 1 2 1 ESD@
@EMI@ CU104
SC300003Z00 (ESD use) ESD@

2
3.3P_0201_25V8B USB20_P2_R
SC300002800 (symbol)
4 3 DU10
<14> USB20_P2 4 3 2 PESD5V0U2BT_SOT23-3
DLM0NSN900HY2D_4P SCA00000T00
1 @EMI@ 2
RU124 0_0201_5%

1
CU106 2 1 0.1U_0402_10V7K USB3_PTX_C_DRX_P5 DU13
<11> USB3_PTX_DRX_P5 USB3_PRX_DTX_N5 USB3_PRX_DTX_N5
B 1 9 B

CU107 2 1 0.1U_0402_10V7K USB3_PTX_C_DRX_N5 USB3_PRX_DTX_P5 2 8 USB3_PRX_DTX_P5 +5V_USB_PW R2


<11> USB3_PTX_DRX_N5
USB3_PTX_C_DRX_N5 USB3_PTX_C_DRX_N5 JUSB3
4 7
USB3_PRX_DTX_P5 1
<11> USB3_PRX_DTX_P5 USB3_PTX_C_DRX_P5 USB3_PTX_C_DRX_P5 USB20_N8_R VBUS
5 6 2
USB20_P8_R 3 D-
USB3_PRX_DTX_N5 4 D+
<11> USB3_PRX_DTX_N5 USB3_PRX_DTX_N5 GND
5
3 USB3_PRX_DTX_P5 6 STDA_SSRX- 10
7 STDA_SSRX+ GND 11
TVW DF1004AD0_DFN9 USB3_PTX_C_DRX_N5 8 GND GND 12
USB3_PTX_C_DRX_P5 STDA_SSTX- GND
ESD@ SC300003Z00 9 13
STDA_SSTX+ GND
RU125 1 @EMI@ 2 0_0201_5%
SC300003Z00 (ESD use) ACON_TCRAY-9U1U91

1
LU5 EMI@
2 USB20_N8_R
SC300002800 (symbol) CONN@
<14> USB20_N8 1 2 1
ESD@

2
@EMI@ CU105 DU11
4 3 3.3P_0201_25V8B USB20_P8_R PESD5V0U2BT_SOT23-3
<14> USB20_P8 4 3 2 SCA00000T00
DLM0NSN900HY2D_4P

1 @EMI@ 2

1
RU126 0_0201_5%

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/03/29 2019/03/29 Title

USB3.0/2.0 (TypeA port)


Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 72 of 101
5 4 3 2 1
A B C D E

1 1

2 2

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/03/29 2019/03/29
Reserved
Issued Date Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 73 of 101
A B C D E
5 4 3 2 1

+3VALW

0.1U_0402_10V7K
1

CM70
2

5
1
+3VALW <58> CDR_TXRX_GOOD B 4

Caldera connector

P
O CDR_ON_ELC <62>
2
A

G
1

3
RM41 TC7SH08FU_SSOP5~D
D 100K_0402_5% UM7 D
JCDRA +5VALW
1

2
Caldera_ON 2 CALDERA_ON <58>
Caldera_PWRGD 3 PEG_CTX_C_GRX_P8 CALDERA_PW RGD <58>
T0+ PEG_CTX_C_GRX_N8 PEG_CTX_C_GRX_P8 <7>
4
T0- PEG_CTX_C_GRX_N8 <7>

1
5
GND PEG_CTX_C_GRX_P9

1
6 RM42 RM91
T1+ 7 PEG_CTX_C_GRX_N9 PEG_CTX_C_GRX_P9 <7> +5VALW
470K_0402_5% 549_0402_1%
T1- 8 PEG_CTX_C_GRX_N9 <7>
GND 9 PEG_CTX_C_GRX_P10

2
T2+ 10 PEG_CTX_C_GRX_N10 PEG_CTX_C_GRX_P10 <7> CDRA_LED_WHITE_R
PEG_CTX_C_GRX_N10 <7>

2
T2-

1
11 +3VALW RM92
GND 12 PEG_CTX_C_GRX_P11 +3VALW

CDRA_LED WHITE 20 mils


100K_0402_5%~D
T3+ 13 PEG_CTX_C_GRX_N11 PEG_CTX_C_GRX_P11 <7>

0.1U_0402_10V7K
T3- PEG_CTX_C_GRX_N11 <7>

CDRA_LED WHITE_R 20 mils


14 1
S
GND PEG_CRX_RD_GTX_P8

3
15 2 1 2
PEG_CRX_RD_GTX_P8

2
PEG_CRX_RD_GTX_N8
G
R0+

1
16

CM23
RM5
R0- 17 PEG_CRX_RD_GTX_N8
10K_0402_5% RM6 QM1
GND 18 PEG_CRX_RD_GTX_P9 2 10K_0402_5% LP2301ALT1G 1P SOT-23-3
R1+ PEG_CRX_RD_GTX_N9 PEG_CRX_RD_GTX_P9
19 UM3 QM2B
R1- PEG_CRX_RD_GTX_N9

6
D
20 2

1
GND CALDERA_PRSNT#

5
D

21 1 <58> CDRA_LED_WHITE_MOS
G

CALDERA_PRSNT# 22 CDRA_RST# CALDERA_PRSNT# <58,62> 4 B CALDERA_RST# <58> CDRA_LED_WHITE


DMN66D0LDW -7_SOT363-6
S

P
PLTRST# 23 O 2
PCH_PLTRST# <11,37>

1
GND 24 PEG_CRX_RD_GTX_P10 A
PEG_CRX_RD_GTX_N10 PEG_CRX_RD_GTX_P10

G
R2+ 25 TC7SH08FU_SSOP5
R2- PEG_CRX_RD_GTX_N10
26

221 ohm for white LED


CDRA_LED_WHITE CDR_BTN# <58>

3
BUTTON# 27 +5VALW
LED_WHITE 28 CDRA_LED_RED

316 ohm for red LED


LED_RED

2
29 RM17
GND 30 PEG_CRX_RD_GTX_P11 +5VALW
PEG_CRX_RD_GTX_P11 100K_0402_5%

on dock cable side


R3+ PEG_CRX_RD_GTX_N11

1
31 RM93
R3- 32 PEG_CRX_RD_GTX_N11
100_0402_1%
GND 33 CLK_PCIE_DGPU_C
CLK_PCIE_DGPU_C

1
REFCLK+ CLK_PCIE_DGPU#_C

1
34 RM94
REFCLK- 35 CLK_PCIE_DGPU#_C CDRA_LED_RED_R

CDRA_LED RED 20 mils


100K_0402_5%~D

2
GND 36 USB3_PRX_C_DTX_N8 2 1 CI38
0.1U_0402_10V6K
SSTX+ USB3_PRX_C_DTX_P8 USB3_PRX_DTX_N8 <14>

CDRA_LED RED_R 20 mils


37 0.1U_0402_10V6K 2 1 CI39
S
SSTX- USB3_PRX_DTX_P8 <14> LM1

3
38 2

2
USB20_P3_R
G
GND 39 3 4
USBD+ 40 USB20_N3_R 3 4 USB20_P3 <14>
QM3
USBD- 41 LP2301ALT1G 1P SOT-23-3
GND 42 2 1 QM2A
SSRX+ USB3_PTX_DRX_N8 <14> 2 1 USB20_N3 <14>

3
D
43 5
USB3_PTX_DRX_P8 <14>

1
SSRX-
D

44 <59> CDRA_LED_RED_MOS
G

GND 45 CDRA_CLK 1 2 0_0201_5% DLM0NSN900HY2D_4P


RM1 DMN66D0LDW -7_SOT363-6
S

I2C_CLK CDRA_DAT I2C_CLK <62,63> EMI@ CDRA_LED_RED


46 RM2 1 2 0_0201_5%
I2C_DAT <62,63>

4
I2C_DATA 47
GND 48
C GND 49 C
GND 50
GND

TE_2260531-1
CONN@

+2.5VOUT

EQ*MB
+2.5VOUT

DEM*EGPU
1 1 1 1 1
0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
CM9

CM32

CM34

CM35

CM36

2 2 2 2 2 +3VS
1 @ 2 1 @ 2
+3VS +3VS
RM76 1K_0201_1% RM26 1K_0201_1%

1 2 EQA1 1 2 EQB1
RM70 1K_0201_1% RM23 1K_0201_1% 1 2 DEMB1
RM86 1K_0201_1%

To CPU RX From Caldera TX


1 @ 2
UM8 RM62 1K_0201_1%
14
41
36
51
9
VDD
VDD
VDD
VDD
VDD

1 2 PEG_CRX_C_RD_GTX_P11 1 45 PEG_CRX_RD_GTX_P11
CM64 0.22U_0201_6.3V
<7> PEG_CRX_GTX_P11 PEG_CRX_C_RD_GTX_N11 OUTB_0+ INB_0+ PEG_CRX_RD_GTX_N11
CM65 1 2 0.22U_0201_6.3V 2 44
<7> PEG_CRX_GTX_N11 1 2 PEG_CRX_C_RD_GTX_P8 3 OUTB_0- INB_0- 43 PEG_CRX_RD_GTX_P8
CM67 0.22U_0201_6.3V +3VS
<7> PEG_CRX_GTX_P8 1 2 PEG_CRX_C_RD_GTX_N8 4 OUTB_1+ INB_1+ 42 PEG_CRX_RD_GTX_N8 1 2 1 2
CM69 0.22U_0201_6.3V +3VS @ +3VS @
<7> PEG_CRX_GTX_N8 PEG_CRX_C_RD_GTX_P10 OUTB_1- INB_1- PEG_CRX_RD_GTX_P10
CM68 1 2 0.22U_0201_6.3V 5 40 RM81 1K_0201_1% RM85 1K_0201_1%
<7> PEG_CRX_GTX_P10 1 2 PEG_CRX_C_RD_GTX_N10 6 OUTB_2+ INB_2+ 39 PEG_CRX_RD_GTX_N10
CM62 0.22U_0201_6.3V
<7> PEG_CRX_GTX_N10 PEG_CRX_C_RD_GTX_P9 OUTB_2- INB_2- PEG_CRX_RD_GTX_P9
CM63 1 2 0.22U_0201_6.3V 7 38 1 2 EQA0 1 2 EQB0
<7> PEG_CRX_GTX_P9 1 2 PEG_CRX_C_RD_GTX_N9 8 OUTB_3+ INB_3+ 37 PEG_CRX_RD_GTX_N9 1 2
CM66 0.22U_0201_6.3V RM84 1K_0201_1% RM82 1K_0201_1% @ DEMB0
<7> PEG_CRX_GTX_N9 OUTB_3- INB_3- RM79 1K_0201_1%
B 10 35 1 2 B
11 INA_0+ OUTA_0+ 34 RM75 1K_0201_1%
12 INA_0- OUTA_0- 33
13 INA_1+ OUTA_1+ 32
INA_1- OUTA_1- +3VS
15 31
16 INA_2+ OUTA_2+ 30
17 INA_2- OUTA_2- 29
18 INA_3+ OUTA_3+ 28
INA_3- OUTA_3-
2

54 DEMB1 RM61 RM66


EQA1 19 DEMB1/AD0 53 DEMB0 20K_0402_5% 1K_0201_1%

PCIE_CLK_BUFFER
20 EQA1 DEMB0/AD1 52 2 1 CALDERA_PRSNT#
EQA0
21 EQA0 PRSNT 50
22 RATE DEMA1/SCL 49 EC_SMB_CK2 <12,37,58,63,77>
+3VS +3VS
1

RXDET DEMA0/SDA 48 EC_SMB_DA2 <12,37,58,63,77>

W=20 mils
ENSMB 47 EQB1
23 EQB1/AD2 46 EQB0
1 2 VGA_EN 24 LPBK EQB0/AD3 +3VS
VIN
1

25 RM64
VGA_EN 26 VDD_SEL +3VS +3VS
RM14 1K_0201_1%
SD_TH/READ_EN
10U_0603_6.3V6M

10U_0603_6.3V6M

1K_0201_1% 27 55 @ 2 1
ALL_DONE DAP_GND
1

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

RM87 1 1 1 1 1 1 1 1

0.1U_0402_10V7K

0.1U_0402_10V7K
CM16

CM17
10K_0201_5% RM18 CM19
2
1

1
CM29

CM30

CM37

CM31

CM33

CM38

@ 2.2_0402_1% 22U_0603_6.3V6M

1
RM72 DS80PCI402SQNOPB_WQFN54_10X5P5 RM21 RM96 RM20 @
2 2 2 2 2 2 10K_0201_5% 1K_0402_1% 4.7K_0402_5% 1K_0402_1% 2 2

Tie 1k ohm to VDD = Register Access SMBus Slave mode


2

2
@

FLOAT = Read External EEPROM (Master SMBUS Mode)


2

UM4

2
1 20

Tie 1k ohm to GND = Pin Mode


2 PLL_BW_SEL VDDA 19
<15> CLK_PEG_P6 3 SRCIN GNDA 18 RM25 2 @ 1 475_0402_1%
<15> CLK_PEG_N6 SRCIN# IRef
4 17
OE_0# OE_1# CLKREQ_PEG#6 <15>
9/11:change from SE000000K80 to SE00000UC00*2 5
VDD VDD
16
+3VS
+3VS 6 15 @
7 GND GND 14 2 1 CLK_PCIE_DGPU_C
@ CM98 1 2 0.01U_0402_16V7K
8 CLK0 CLK1 13 CLK_PCIE_DGPU#_C
RM27 2 @ 1 33_0402_1% CM99 1 2 0.01U_0402_16V7K
CLK0# CLK1#

*
9 12 RM28 33_0402_1%
10 VDD VDD 11 @
SDATA SCLK
PCIe Clock Buffer UM4 RM25 RM27 / RM28 CM16 CM98 / CM99 0.1U_0402_10V7K 1 1

0.1U_0402_10V7K

1
1
49.9_0402_1%
RM29

49.9_0402_1%
RM38
CM18

CM20
1 1
PI6CEQ20200LIEX
SD034475080 SD034330A80 SE102104K00 SE076103K80

1U_0201_6.3V6M
CM21 SE00000UC00

1U_0201_6.3V6M
CM22 SE00000UC00
Pericom (SA00007JZ00) 2 2 @
X7680231L09 (475 +-1% 0402) (33 +-1% 0402) (0.1U +-10% 0402) (.01U 16V K X7R 0402)
2 2

2
2
IDT (SA00007ZU00) SD034412080 SD00000AD80 SE00000QL10 SE076104K80
X7680231L10 (412 +-1% 0402) (27 +-1% 0402) (1U +-10% 0402) (.1U 16V K X7R 0402)

A A
<12> SML0DATA
<12> SML0CLK 9/11:change from SE000000K80 to SE00000UC00*2

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/03/29 2019/03/29
Caldera Docking
Issued Date Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 74 of 101
5 4 3 2 1
5 4 3 2 1

+5VALW

+3VALW
+5V_TOBII
D 1 1 D
CE80 CE82

W=80mils
4.7U_0805_10V4Z 0.1U_0402_10V6K
UE12

1
RE652 2 2 1 +5VALW
5 OUT
10K_0402_5% IN 2
4 GND
EN 3 1 2

2
OCB RE161 10K_0402_5%
SY6288D20AAC_SOT23-5
<58> TOBII_PW R_EN#

1 1
CE79 CE81
0.1U_0402_10V6K 0.1U_0402_10V6K
2 2

Tobii Conn.
Near JTOBII
C C

+3VALW +5V_TOBII
JTOBII
@ 8 +5V_TOBII
RE647 1 2 0_0402_5% 7 GND
GND

2
RE300 6
5 6
LE3 10K_0201_1% 5
USB20_N9_R

10P_0402_50V8J
4
1 2 USB20_N9_R USB20_P9_R 3 4
<14> USB20_N9 1 2 3

CV1071
@RF@
2

1
1 2
USB20_P9_R <62> TOBII_INT# 1
4 3
<14> USB20_P9

2
4 3 ACES_50228-0067N-001
CONN@
DLM0NSN900HY2D_4P
@
1 2
RE648 0_0402_5%

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/03/29 2019/03/29 Title

Tobii (17" Only)


Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 75 of 101

5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/03/29 2019/03/29
Reserved
Issued Date Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 76 of 101
5 4 3 2 1
5 4 3 2 1

Fintek thermal sensor


+3VS
+3VS +3VS +3VS

1
1 R181 1
C2498 U2407 10K_0402_5% C2531
0.1U_0402_10V6K @ 0.1U_0402_10V6K
U2408 EC_SMB_CK2
@ R408 1 2 4.7K_0402_5%
2 1 10 2 1 2 EC_SMB_DA2
D REMOTE4+ @ R409 1 2 4.7K_0402_5% D

2
VCC SCL EC_SMB_CK2 <12,37,58,63,74> D+ VCC
REMOTE1+ 2 9 REMOTE4- 3 6 THERM# @ R410 1 2 4.7K_0402_5%
DP1 SDA EC_SMB_DA2 <12,37,58,63,74> D- ALERT#
3 8 EC_SMB_CK2 8 4
REMOTE2- THERM#
<37> REMOTE2- DN ALERT# SCL THERM#
4 7 EC_SMB_DA2 7 5
<37> REMOTE2+ DP2 THERM# SDA GND
REMOTE3+ 5 6 1 @ 2 REMOTE3-
DN3 DP3 GND/DN3 R185 0_0402_5% F75397M_MSOP8

REMOTE1- 1 @ 2 REMOTE2- F75305M_MSOP10


Power Button-TOP side
R412 0_0402_5%

Address 1001_101xb
SW 2
EVQPLHA15_4P
3 1 ON/OFF#
ON/OFF# <58>
4 2 1
C1
.1U_0402_16V7K

5
6
2

REMOTE1,2,3,4 (+/-) : Power ON circuit


Trace width/space:10/10 mil
Trace length:<8"
+3VS +5VS +12V_FAN

Power Button-BOT side

22U_0603_6.3V6M

22U_0805_25V6M
Close U2407

1
CF4

CF6
10K_0402_5%

10K_0402_5%

10K_0402_5%
CPU PWR

2
SW 3

RF1

RF2

RF3
REMOTE1+ REMOTE1+ EVQPLHA15_4P
1 3 1 ON/OFF#
C JFAN1

1
1

C2502 @ C2500 2 Q2407 1 4 2 1


2200P_0402_25V7K 2200P_0402_25V7K B 2 1 C5360
MMBT3904W H_SOT323-3 2
2 REMOTE1- E 3 .1U_0402_16V7K
2

<58> CPU_FAN_PW M 2 1 4 3 6
REMOTE1-
3

<58> CPU_FAN_FB

5
6
C REMOTE2+ DF1 5 4 6 7 2 C
SDMK0340L-7-F_SOD323-2 5 7
1

SSD
ACES_50273-0050N-001

CPU FAN Control circuit


C2510 CONN@
2200P_0402_25V7K
2 REMOTE2- REMOTE3+ SP02001DG00

REMOTE3+ C
1

1 @ C2511 2 Q2411
2200P_0402_25V7K B MMBT3904W H_SOT323-3
C5361 E
2

2200P_0402_25V7K REMOTE3-
3

2 REMOTE3-

Ambient Temp.
+3VS +5VS +12V_FAN

Close U2408
REMOTE4+

22U_0805_6.3VAM
C
1
1

@ C2532 2 Q2412

22U_0805_25V6M
CF5
2200P_0402_25V7K B MMBT3904W H_SOT323-3

1
10K_0402_5%

10K_0402_5%

10K_0402_5%
REMOTE4+

CF7
E
2

2
REMOTE4- 2
1
3

RF4

RF5

RF6

2
C2533
2200P_0402_25V7K
2 REMOTE4- JFAN2

1
1
2 1
3 2
<58> GPU_FAN_PW M 2 1 4 3 6
<58> GPU_FAN_FB 4 6
DF2 5 7
SDMK0340L-7-F_SOD323-2 5 7
ACES_50273-0050N-001
CONN@

GPU FAN Control circuit


SP02001DG00

B B

Fiducial Mark
PCB Screw Hole
H42 H43 H44 H45 H46 H47 H48 FD11 FD10 FD1 FD2
H_3P8 H_3P0-G H_3P0-G H_3P0-G H_3P0-G H_3P0-G H_3P0-G @ FIDUCIAL @ FIDUCIAL @ FIDUCIAL @ FIDUCIAL
@ @ @ @ @ @ @
1

H49 H50 H51 H52 H53 H54 H55


H_3P0-G H_3P0-G H_3P0-G H_3P0-G H_3P0-G H_3P0-G H_3P0-G
@ @ @ @ @ @ @
1

H56 H57 H58 H59 H60 H70 H65


H_3P2 H_3P3 H_3P2 H_3P3 H_3P2 H_3P2 H_3P8-G
@ @ @ @ @ @ @
1

H1 H2 H3 H4 H5 H8 H63
H_3P8-G H_3P8-G H_3P8-G H_3P8-G H_3P8-G H_3P8-G H_3P8
@ @ @ @ @ @ @
1

H72 H73
H_3P0N H_4P0X3P0N
@ @
1

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/03/29 2019/03/29
PWRBTN/Thermal/SCREW/FAN
Issued Date Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 77 of 101
5 4 3 2 1
A B C D E

+5VS and +3VS switch


20mohm/6A per channel +VCCST switch
4.4mohm/6A
+3VALW +3VS

TR=12.5us@Vin=1.05V
@
U17 J5
1 14 3VS 2 1
VIN1 VOUT1 2 1
2
VIN1 VOUT1
13 9/11:change from SE000000K80 to SE00000UC00*2
C2507 JUMP_43X79
3VS_GATE +1VALW

0.1U_0402_10V7K

10U_0402_6.3V6M

10U_0603_6.3V6M
SUSP# R174 1 2 10K_0402_5% 3 12 1 2 1 1 1
<42,56,58,59,68,87,89> SUSP# ON1 CT1

W=10 mils
470P_0402_50V7K
+1.05V_VCCST

C2523

C256

C257
4 11 U19
VBIAS GND C2506 1
1
R182 1 2 0_0402_5% 5VS_GATE 5 10 1 2 2 2 2 2 VIN1 1
ON2 CT2 220P_0402_50V8J +5VALW VIN2
6 9 5VS +5VALW 7 6
1 VIN2 VOUT2 1 1 VIN thermal VOUT
C258 +5VALW 7 8
VIN2 VOUT2 1

1U_0201_6.3V6M
C4 SE00000UC00

1U_0201_6.3V6M
C5 SE00000UC00
0.1U_0402_16V7K 3 1
VBIAS

0.1U_0402_10V7K

47U_0805_6.3V6M
15 +5VS C2521
GPAD

1
2 @ 2 2 4 5
0.1U_0402_10V7K ON GND
2

C6

C8
AOZ1331_SON14_2X3 J4
2 1 2

2
2 1 AOZ1334DI-01_DFN8-7_3X3
JUMP_43X79
+5VALW +3VALW +5VALW

0.1U_0402_10V7K

10U_0402_6.3V6M

10U_0603_6.3V6M
1 1 1

C2524

C260

C261
SYSON
<58,87> SYSON
2 2 2

0.1U_0402_10V7K

10U_0603_6.3V6M

0.1U_0402_10V7K

10U_0603_6.3V6M

0.1U_0402_10V7K
Main source A OS S A00008 A800 ( SI C A OZ1334 DI- 01 DF N 8P SI NGLE L OAD S W
)
1 1 1 1 1

2nd source APE C S A00006V300 ( SI C APE8939 GN3 DF N 8P L OAD S W I T CH)


C2525

C262

C263

C264

C265


3rd source E MC S A00008R600 ( SI C E M5201V DF N3X3 8P L OAD S W I TCH)


2 2 2 2 2

+3VALW_PCH switch
20mohm/6A per channel
+3VALW

2 2
10U_0603_6.3V6M

0.1U_0402_10V7K

1 1
+3V_PCH
C269

C270

@
2 2 U18 J6
5 1 2 1
IN OUT 2 1
2

W=10 mils
JUMP_43X79
GND

0.1U_0402_10V7K

10U_0402_6.3V6M

10U_0603_6.3V6M
1 1 1
4 3 1 2 +3V_PCH
<12,37,58,88,98> PCH_PWR_EN EN OC

C2522

C266

C267
SY6288C20AAC_SOT23-5 R367
10K_0402_5% 2 2 2
C268
1

0.01U_0402_16V
2

add for power down sequence


For meet tPLT17 & tCPU28 power down sequence.
tPLT17 : 1us (Max)
IMVP_VR_ON <58,91,96>

tCPU28 : 1us (Max)


6

3 Q7A 3

For meet tPLT15 power down sequence(Un-Stuff)


DMN66D0LDW-7_SOT363-6

tPLT15 : 1us (Max)


2

+1.2V_VCCPLL_OC switch
22mohm/4A
1

TR=520us@Vin=0.8V
+3VALW
+3VALW
1

R307 SYSON
H_VCCST_PWRGD <6,58> +1.2V_DDR +1.2V_VCCPLL_OC
1

100K_0402_1% R325
100K_0402_1% UZ21
3

Q7B Q9B 1 7
2

DMN66D0LDW-7_SOT363-6 DMN66D0LDW-7_SOT363-6 2 VIN VOUT 8


2

PM_SLP_S3_H 5 PM_SLP_S4_H 5 VIN VOUT


1
SUSP# 3 6 C3 1 2
ON CT @ C11
6

Q9A 2200P_0402_25V7K 2.2U_0402_6.3VX5R


4

DMN66D0LDW-7_SOT363-6 4 2
+5VALW VBIAS
6

Q8A 2 1 5
DMN66D0LDW-7_SOT363-6 <12,58,90> PM_SLP_S4# GND 9
1 GND
2 C2518
<6,12,58,62,83,85> PM_SLP_S3# C2519
0.1U_0402_10V7K
1

SUSP# 2 AOZ1336DI_DFN8_2X2
2
1

0.1U_0402_10V7K
3

Q8B
DMN66D0LDW-7_SOT363-6
5

4 4
4

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/03/29 2019/03/29
DC/DC Interface
Issued Date Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 78 of 101
A B C D E
5 4 3 2 1

D D

+3V_PCH JPCMC CMC_DEBUG_36P


+1VALW
OBS DATA JTAG/RC/HOOKS
RC9 1 CMC@ 2 1K_0402_5% XDP_SPI_SI
1 22
<6> CFG0 DATA_0 VCCOBS_AB
XDP_HOOK[3] 3
5 DATA_1
<6> CFG2 DATA_2
7
<6> CFG3 DATA_3
9 28
<6> CFG4 DATA_4 XDP_TRST* CPU_XDP_TRST# <6,17>
11 29
<6> CFG5 DATA_5 XDP_TDI XDP_TDI <6,12>
13 30
<6> CFG6 DATA_6 XDP_TMS PCH_JTAG_TCK XDP_TMS <6,12>
15 32
+1VALW <6> CFG7 DATA_7 XDP_TCK0 XDP_TCK1 PCH_JTAG_TCK <6,12>
31
XDP_TCK1 XDP_TCK1 <12>
17 35
<6> CFG17 DATA_CLK_1P XDP_TDO XDP_TDO <6>
21
XDP_ITP_PMODE <6> CFG16 DATA_CLK_1N
RC353 1 CMC@ 2 1K_0402_5% 33
XDP_PREQ* XDP_PREQ# <6,17>
2 34
<6> CFG8 DATA_8 XDP_PRDY* XDP_PRDY# <6,17>
XDP_HOOK[6] 4
<6> CFG9 DATA_9 XDP_HOOK0
C 6 27 RC355 1 CMC@ 2 1K_0402_1% C
<6> CFG10 DATA_10 HOOK_0 XDP_SPI_SI EC_RSMRST# <58>
8 25
<6> CFG11 DATA_11 HOOK_3 XDP_ITP_PMODE XDP_SPI_SI <11>
10 26
<6> CFG12 DATA_12 HOOK_6 XDP_ITP_PMODE <12>
12
<6> CFG13 DATA_13 XDP_SPI_IO2
14 24 RC354 1 CMC@ 2 1K_0402_1%
<6> CFG14 DATA_14 XDP_PRSNT_PCH* PCH_SPI_0_W P# <11>
16 23 RC688 1 2 1.5K_0402_5%
PCH_JTAG_TCK <6> CFG15 DATA_15 XDP_PRSNT_CPU*
RC35 2 CMC@ 1 51_0402_1%
18 19
XDP_TCK1 <6> CFG19 DATA_CLK_2P GND
RC348 2 @CMC@1 51_0402_1% 20 36
<6> CFG18 DATA_CLK_2N <MT> GND
RC687 2 @CMC@1 51_0402_1% CPU_XDP_TRST#

INTEL_CMC_PRIMARY
CONN@

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/03/29 2019/03/29 Title

CMC Conn
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 79 of 101
5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/03/29 2019/03/29
Reserved
Issued Date Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 80 of 101
5 4 3 2 1
5 4 3 2 1

Power block
+19V_VIN_1 ISL95338
+PWR_SRC
Adpater 1
Always
D D

Buck mode +3VALWP:


Page 51 +5VALWP: +5VALW
TPS51225CRUKR Page 54

+19V_VIN_2 ISL95338 Turn Off


Adapter 2 Buck mode +1.2VP/+0.6VSP:
Page 52 RT8207PGQW
Page 55
CPU OTP
Page 50

CHARGER +1VALWP:
CC: TPS51212DSCR
CV: Page 56

ISL88739A
+3VALW
Page 53
+1.8VSP:
RT9059
C C

Page 66

3Cell-2Parallel
90W Battery
BATT+ +VCCIO:
SY8286RAC
Page 57

2.5V_MEMP:
+VCC_CORE: RT9059GSP
+VCCGT Page 58

ISL95829C
Page 59,60,61,62,63 +12VP:
RT9297
Page 67
+VCCSA;
B B

ISL95870B
Page 64

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/05/16 2019/03/29
PWR_POWER BLOCK DIAGRAM
Issued Date Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 81 of 101
5 4 3 2 1
A B C D

@
PJPDC1
EMI@ PL1
5A_Z80_0805_2P
+19V_VIN_1
Adapter connector: 1 2

1.PSI D _ 1
13 +19V_ADPIN_1 EMI@ PL2
13
2.G ND
12 5A_Z80_0805_2P
12 11 1 2
3.G ND

1M_0402_1%
11

1
10 EMI@ PL3
4.G ND
10 9 5A_Z80_0805_2P +3VALW

3300P_0402_50V7-K

3300P_0402_50V7-K

2200P_0402_50V7K

2200P_0402_50V7K
9
5.G ND
8 1 2

100P_0402_50V8J

100P_0402_50V8J

PR36
8

1
7
6.G ND
EMI@ PL4
7 6

EMI@PC19

EMI@PC20

EMI@ PC2

EMI@ PC4
5A_Z80_0805_2P
7.G ND
ACOK_ISL95338_1 <58>

2
6 5 1 2

8.+19V_ A D PI N _ 1

2
5 4

EMI@ PC1

EMI@ PC3
EMI@ PL5

1000P_0402_50V7K
4

205K_0402_1%
1
9.+19V_ A D PI N _ 1
3 5A_Z80_0805_2P

2.2K_0402_1%
3

1
2 1 2
10.+19V_ A D PI N _ 1
2

1
1

PC23
PR35
11.+19V_ A D PI N _ 1
1

2
12.+19V_ A D PI N _ 1
PR3

PR4
2
ACES_50493-01301-P01
13.+19V_ A D PI N _ 1
33_0402_5%
1 1

EMI@ PL6 PSID_1-1 1 3 PSID_1-3 1 2 PS_ID_1 <58>

2
BLM15HG601SN1D_2P PQ1

S
PSID_1 1 2 FDV301N_G 1N SOT23-3

G
2
PR5

100K_0402_1%
1
10K_0402_1%
PSID_1-4 1 2
+5VALW

PR1
PJPDC2
EMI@ PL7
+19V_VIN_2 @ C

1
@ 5A_Z80_0805_2P PD1 PSID_1-2 2 PQ2

1
1 2 SM24_SOT23 B MMST3904-7-F_SOT323-3
Adapter connector: 13 +19V_ADPIN_2 EMI@ PL8 E

1.PSI D _ 2
13

1
12 5A_Z80_0805_2P

15K_0402_1%

3
12
2.G ND
11 1 2

1M_0402_1%
11

1
10 EMI@ PL9
3.G ND

PR2
10 9 5A_Z80_0805_2P

3300P_0402_50V7-K

3300P_0402_50V7-K

2200P_0402_50V7K

2200P_0402_50V7K
4.G ND
9 8 1 2 +3VALW

100P_0402_50V8J

100P_0402_50V8J

PR38

2
8

1
5.G ND
7 EMI@ PL10
7 6
6.G ND
EMI@PC21

EMI@PC22

EMI@ PC6

EMI@ PC8
5A_Z80_0805_2P ACOK_ISL95338_2 <58>

2
6 5 1 2
7.G ND
2

2
5 4

EMI@ PC5

EMI@ PC7
EMI@ PL11

1000P_0402_50V7K
8.+19V_ A D PI N _ 2
4

205K_0402_1%
1
3 5A_Z80_0805_2P
3

1
9.+19V_ A D PI N _ 2
2 1 2

2.2K_0402_1%
2 1

PC24
10.+19V_ A D PI N _ 2

PR37
1

1
11.+19V_ A D PI N _ 2

2
2
ACES_50493-01301-P01
12.+19V_ A D PI N _ 2
PR8

PR9
13.+19V_ A D PI N _ 2
33_0402_5%
EMI@ PL12 PSID_2-1 1 3 PSID_2-3 1 2 PS_ID_2 <58>

2
BLM15HG601SN1D_2P PQ3

S
PSID_2 1 2 FDV301N_G 1N SOT23-3 PR18

1K_0402_1%

G
2
PR10 JRTC PD5
BATT+

100K_0402_1%
1
10K_0402_1% 1 1 2 JRTC1 2
2 2

PSID_2-4 1 2 1 2 1
+5VALW +RTC_CELL
+3VLP
2 3 1 2 3

PR6
EMI@ PL13 BATT++ GND 4
GND
BATT+

9A Z80 10M 1812_2P C BAS40CW _SOT323-3

2
2

1
1 2 PSID_2-2 2 PQ4 ACES_50271-0020N-001 1K_0402_1%
B MMST3904-7-F_SOT323-3 @
EMI@ PL14 E PR15

1
9A Z80 10M 1812_2P

15K_0402_1%
RTC

3
1 2 BATT++ @
PD2

PR7
1
SM24_SOT23
100P_0402_50V8J
1

1
1000P_0402_50V7K
0.022U_0402_25V7K

0.01UF_0402_25V7K

2
1

EMI@PC11

EMI@PC12
PC10

6
EMI@ PC9

PQ8
2

SI3457CDV-T1-GE3_TSOP6 5
2

PD3 PD4 2

+PWR_SRC B+_BIAS
EMI@

TVNST52302AB0_SOT523-3 TVNST52302AB0_SOT523-3 4 1
EMI@ EMI@

D
100K_0402_1%
@ PBATT1

0.1U_0402_25V6
0.22U_0603_25V7K
1

G
Battery connector:
2

1
1

PR19

PC18

PC16
1.BATT++

3
1 2 VCIN_ BATT_TEMP <58,85>
+3VLP
2
2.BATT++
3

2
3 4
3.BATT++
PR16

2
4 5 CLK_SMB 1 2 PR14
4.BATT++
5 6 DAT_SMB 1 PR11 2 100_0402_1% 10K_0402_1% 100K_0402_1%
6
5.CLK_SMB
7 BATT_PRS 1 PR12 2 100_0402_1% VCIN_ BATT_TEMP 1 2 1 2 VSB_N_001
7 +3VALW_EC

1
SYS_PRES

1VSB_N_003
8
6.DAT_ SM B
PR13 100_0402_1%
8 9 PR17
7.BATT_PRS
9 10 100K_0402_1%

8.SYS_ PRE S
10 11 @ PR20
Battery 90W
11 EC_SMB_CK1 <44,45,58,83,84,85>
9.G ND
12 0_0402_5% D

2
12 @
13 1 2 VSB_N_002 2
90W/12V=7.5A
PQ9
10.G N D <59> EC_EN_AMP
13 EC_SMB_DA1 <44,45,58,83,84,85>
G L2N7002W T1G 1N SC-70-3
11.G N D ACES_51481-01371-P01 S

12.G N D

3
3 3

.1U_0402_16V7K
1

PC17
PR34
100K_0402_1% @

2
2
battery unplug prochot For PROCHOT
<58> ADP_I adapter unplug prochot-1 adapter unplug prochot-2 CPU thermal protection
@ PR44
VCIN0_PH
330W
+3VALW
Trig = 1V
0_0402_5%
1 2
VCIN1_ADP_PROCHOT= 0.85V
@ PR45
<6,58,85,91> H_PROCHOT# <58> EC_AC_BAT# +3VALW
0_0402_5%
93 +/- 3 degree C
reset = 0.81V
H_PROCHOT# 1 2 EC_AC_BAT# 1 2
Recover = 2.28V +3VALW_EC +3VLP
240W @ PR27
H_PROCHOT# 1 50 +/- 3 degree C
VCIN1_ADP_PROCHOT=0.63V
0_0402_5% 2

1
@ PC14 PR22

14.7K_0402_1%

14.7K_0402_1%
reset = 0.59V

2
1U_0603_25V6K 10K_0402_1% PR40 @ PR42
D

PR24

PR25
@ 10K_0402_1% 0_0402_5%

L2N7002DW1T1G_SC88-6
1

6
VCIN_ BATT_TEMP 1 2 2 PQ7 PC15

L2N7002DW1T1G_SC88-6
6
G L2N7002W T1G 1N SC-70-3 PR23 0.1U_0402_25V6 PC25 @

2
110K_0402_1% 1 2 PQ6A_GATE 2

PQ6A
S 0.1U_0402_25V6

1
1 2 PQ10A_GATE 2

PQ10A
<58> VCIN0_PH1
3
100K_0402_1%
1

1
PR21
L2N7002DW1T1G_SC88-6

1
3
@PR28

100K_0402_1%

L2N7002DW1T1G_SC88-6

1
3

1
PR41 PH1
5 100K_0402_1%
PQ6B

100K_0402_1%_B25/50 4250K
<83> FWPG_ISL95338_1
2

PQ10B
<58> VCIN1_ADP_PROCHOT <58,84> FWPG_ISL95338_2

L2N7002WT1G 1N SC-70-3
2

L2N7002WT1G 1N SC-70-3
4

2
D

4
1

1
PR26 @ PC13 D PQ10A_GATE 2
<58> ECAGND
1

1
100K_0402_1% .1U_0402_16V7K PQ6A_GATE 2

PQ12
G

PQ11
4 G S 4

S
2

3
2

3
Security Classification Compal Secret Data Compal Electronics, Inc.
2018/05/16 2018/12/31
PWR_DC/BATT Conn/OTP/RTC
Issued Date Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 82 of 101
A B C D
A B C D

@PQS26 @ PQS22
AO3409_SOT23-3 AO3409_SOT23-3

1 3 3 1

S
S

D
D

0.022U_0603_50V7K
1

1M_0402_5% G
G
2

2
1

PCS82

PRS86
2
@ @

2
@
PRS87

1
1M_0402_5%
@ PQS23
L2N7002W T1G 1N SC-70-3
1 1

2
EMI@ @ PRS92
PLS01 0_0402_5% D
+SDC_IN

1
1UH_MMD-10CZN1R0M-R1L_20A_20% 1 2 2
P1 P2 1 2 <59> OFF_PMOS_1 G
+19V_VIN_1 PQS10
S
EMZB08P03H_EDFN5X6-8-5

3
1 @ PJPS01
PRS01
2
3 5 1 4 1 2
1 2

1
2 3

200K_0402_1%
JUMP_43X118

22U_B2_25VM_R100M
0.022U_0603_50V7K
DMP3056L-7 1P SOT23-3
PRS63
@ PJPS02 PQS05

22U_B2_25VM_R100M
1

1
PQS12
PRS59 PQS01 PQS03

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M
1

4
0.005_2512_1%

5
@ 1M_0402_5% 1 2 +

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M
S
1 2

5
2

PCS69

PCS71

PCS72

PCS01

PCS02

PCS03

PCS06
100K_0402_1%
@ +

CSSN_1
CSSP_1

AON6314_N_DFN56-8-5
2
G
1

1
PCS76

PCS75

PCS04

PCS05
169K_0402_1%

JUMP_43X118

2200P_0402_50V7K

2200P_0402_50V7K

AON6380_DFN5X6-8-5

AON6380_DFN5X6-8-5
2
PRS58 2

PCS2508

PCS2509
PDS03
D

2
1
4 2
PRS57

SMF4L22A_SOD123FL2

2
@ 4 4

100K_0402_1%
2

PRS60
2

2
1

@EMI@

@EMI@
1_0402_1%
@

PRS03
@ PRS02

3 2

1
PRS61 1_0402_1%
L2N7002DW1T1G_SC88-6

L2N7002DW1T1G_SC88-6

1
2
3
6

1M_0402_5%

3
2
1

3
2
1
2

2
2 5
PQS13A

PQS13B PCS19 PLS02

2
4.7U_0402_6.3V6M 1UH_SRPG1005-1R0M-AD_30A_20%
@ @ 1 2 1 2
1

1U_0402_25V6K
1
20K_0402_1%

1U_0402_25V6K

680P_0603_50V7K 4.7_1206_5%
1

1
PRS62

EMI@ PRS83
PCS20

PCS21
PQS04
@ PQS02

AON7380_DFN3X3-8-5
2 2
2

5
1

5
2.2_0603_5%

2
PRS04

AON6380_DFN5X6-8-5
4

1
4

EMI@ PCS79
0.22U_0402_25V6K
1 2
1
PRS06

BST1_R_ISL95338_1
0_0805_5%

2
PCS22
PDS01

1
2
3
2 1

3
2
1
P1 ISL95338_N001
RB751V-40_SOD323-2

ADPS_ISL95338_1

BST1_ISL95338_1
CSIN_ISL95338_1
CSIP_ISL95338_1
1

ADP_ISL95338_1

UG1_ISL95338_1

LG1_ISL95338_1
LX1_ISL95338_1
PCS67
1U_0402_25V6K

2
1
PRS08
10_1206_5%

P1 PRS09
PUS1 4.7_0402_5%
2

ISL95338HRTZ-T_TQFN32_4X4 1 2 VDD_ISL95338_1

16

15

14

13

12

11

10

33
9
PCS24

ADP

CSIP

ADPS

UGATE1
BOOT1

PHASE1

LGATE1

GND
CSIN
1

PRS75 PCS23 PCS25 1U_0402_6.3V6K


1

1M_0402_5% 1U_0402_25V6K
1U_0402_6.3V6K DCIN_ISL95338_1 17 8 VDDP_ISL95338_1 1 2
1 2 DCIN VDDP
PQS18 VDD_ISL95338_1 18 7 LG2_ISL95338_1
2

VDD_ISL95338_1 L2N7002W T1G 1N SC-70-3 @ PRS73 0_0402_5% VDD LGATE2


2

ACIN_R_1 1 2 ACIN_ISL95338_1 19 6 LX2_ISL95338_1


FRWEN PHASE2
@ PRS10 20 5 UG2_ISL95338_1
0.01UF_0402_25V7K

D 0_0402_5% RVSEN UGATE2 PCS26 PRS11


49.9K_0402_1%
1

PRS94 2 1 2SDA_ISL95338_1 21 4 BST2_ISL95338_1 1 2BST2_R_ISL95338_1


1 2
<58> OFF_FWEN_1
L2N7002DW1T1G_SC88-6

<44,45,58,82,84,85> EC_SMB_DA1 SDA BOOT2


2
PRS76

PCS84

100K_0402_1% G
S 1 2SCL_ISL95338_1 22 3 VOUTS_ISL95338_1 0.22U_0402_25V6K
<44,45,58,82,84,85> EC_SMB_CK1 SCL VOUTS
6

@ PRS13 2.2_0603_5%
3

3 3
1

23 2 +SDC_IN
PQS29A

PRS77 @ PRS12 0_0402_5%


2

2 0_0402_5% PROCHOT# CSOP 1 2


100K_0402_1%
FW PG_ISL95338_1 24 1
<58,82> FWPG_ISL95338_1 FRWPG CSON
L2N7002DW1T1G_SC88-6

COMPR
COMPF
RVSPG
ADDR0

ADDR1
1

PROG

VOUT
REF
3

PQS29B

PRS54
VDD_ISL95338_1 1 2
5
58,85> VCIN1_AC_IN 25

26

27

28

29

30

31

32
100K_0402_1%
1

PRS53

PROG_ISL95338_1

COMP_ISL95338_1

REF_ISL95338_1

VOUT_ISL95338_1
200K_0402_1%
4

2
+SDC_IN

@ PRS19
PRS18 0_0402_5%
+3VALW 1 2 1 2
182K_0402_1% +SDC_PWR

@ PQS31
1

LMUN5113T1G_SOT323-3 PRS20
2.2K_0402_1%

0.1U_0402_25V6
2.2K_0402_1%
3

1K_0402_1%
@ PRS15
@PRS14
1

0_0603_5%

PCS28
1

2
PRS96

PCS27
2

560P_0402_50V7K
2

SDA_ISL95338_1
ISL95338_N003

SCL_ISL95338_1 PCS29
2

@ PQS32 0.022U_0603_50V7K
LMUN5236T1G_SOT323-3
1

@ PRS98
0_0402_5%
PQS32_2 2
4 4

<6,12,58,62,78,85> PM_SLP_S3# 1 2

PRS99
+SDC

0_0402_5%
1 2
<6,12,58,62,78,85> VCIN1_AC_IN
3

@
1
0_0603_5%
PRS97

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/05/16 2018/12/31
PWR_Dual adapter1(ISL95338)
Issued Date Deciphered Date Title
+SDC_PWR 2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 83 of 101
A B C D
A B C D

@PQS27 @ PQS24
AO3409_SOT23-3 AO3409_SOT23-3

1 3 3 1

D
S
D

0.022U_0603_50V7K

1M_0402_5%

G
G
2

2
1

PCS83

PRS89
@ @

2
@
PRS90
1 1

1
1M_0402_5%

EMI@

2
PLS10 @ PRS93
D
@ +SDC_IN
1UH_MMD-10CZN1R0M-R1L_20A_20% 0_0402_5% PQS28
+19V_VIN_2

1
1 2 1 2 2 L2N7002W T1G 1N SC-70-3
PQS15
P3 P4 <59> OFF_PMOS_2 G
EMZB08P03H_EDFN5X6-8-5 S
1 PRS21 @ PJPS03

3
2

22U_B2_25VM_R100M
3 5 1 4 1 2 1
1 2

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M
1
2 3

PCS62
JUMP_43X118 +

200K_0402_1%

0.022U_0603_50V7K
DMP3056L-7 1P SOT23-3

1
PRS70

PCS78

PCS77

PCS31

PCS32
@ PJPS04 PQS09 PQS11

22U_B2_25VM_R100M
1

1
PRS67 PQS07

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M
4
1

5
1 2 2

PQS16
@ 1M_0402_5% 0.005_2512_1% +
S

AON6314_N_DFN56-8-5

2
1 2
1

5
2

PCS70

PCS73

PCS74

PCS30

PCS42

PCS61
100K_0402_1%

CSSN_2

AON6380_DFN5X6-8-5
G

2
1

1
@ JUMP_43X118
169K_0402_1%

CSSP_2

AON6380_DFN5X6-8-5
2
2
PRS66

PDS04
D

2
1
4 4
PRS69

@EMI@ PCS2510

@EMI@ PCS2511
2200P_0402_50V7K

2200P_0402_50V7K
SMF4L22A_SOD123FL2

1
@ 100K_0402_1% 4
2

PRS64

@
2

2
1

1_0402_1%
1

PRS23
@
3 2

1_0402_1%

1
PRS68
L2N7002DW1T1G_SC88-6

L2N7002DW1T1G_SC88-6

3
2
1

1
2
3
6

1M_0402_5% PRS22

3
2
1
2
2 5
PQS17A

PQS17B

2
PCS48 PLS04

2
4.7U_0402_6.3V6M 1UH_SRPG1005-1R0M-AD_30A_20%
@ @ 1 2 1 2
1

1U_0402_25V6K
1
20K_0402_1%

1U_0402_25V6K

680P_0603_50V7K 4.7_1206_5%
1

1
PRS65

EMI@ PRS85
PCS49

PCS50
2 2

PQS06 PQS08
2

5
@

AON7380_DFN3X3-8-5
1

2.2_0603_5%

AON6380_DFN5X6-8-5
2
PRS24
4 4

EMI@ PCS81
0.22U_0402_25V6K
1 2
2
PRS26

BST1_R_ISL95338_2
0_0805_5%

2
PCS51
PDS02

3
2
1

1
2
3
2 1

1
P3 ISL95338_N004

ADPS_ISL95338_2
RB751V-40_SOD323-2

BST1_ISL95338_2
CSIN_ISL95338_2
CSIP_ISL95338_2
ADP_ISL95338_2

UG1_ISL95338_2

LG1_ISL95338_2
LX1_ISL95338_2
PCS68

2
1U_0402_25V6K
1

PRS41

1
P3 10_1206_5%

PRS29
PUS2 4.7_0402_5%
2

ISL95338HRTZ-T_TQFN32_4X4 1 2 VDD_ISL95338_2

16

15

14

13

12

11

10

33
9
1

PRS80 PCS53

ADP

CSIP

ADPS

UGATE1
BOOT1

PHASE1

LGATE1

GND
CSIN
1M_0402_5% PCS52 PCS54 1U_0402_6.3V6K
2

1U_0402_25V6K 1U_0402_6.3V6K DCIN_ISL95338_2 17 8 VDDP_ISL95338_2 2 1


1 2 DCIN VDDP
PQS19 VDD_ISL95338_2 18 7 LG2_ISL95338_2
2

VDD_ISL95338_2 L2N7002W T1G 1N SC-70-3 @ PRS74 0_0402_5% VDD LGATE2


1 2 ACIN_ISL95338_2 19 6 LX2_ISL95338_2
FRWEN PHASE2
20 5 UG2_ISL95338_2
0.01UF_0402_25V7K

D @ PRS30 0_0402_5% RVSEN UGATE2 PCS55 PRS31


49.9K_0402_1%
1

PRS95 2 1 2SDA_ISL95338_2 21 4 BST2_ISL95338_2 1 2BST2_R_ISL95338_2


1 2
<59> OFF_FWEN_2
L2N7002DW1T1G_SC88-6

<44,45,58,82,83,85> EC_SMB_DA1 SDA BOOT2


2
PRS79

PCS85

3
100K_0402_1% G 3

S 1 2SCL_ISL95338_2 22 3 VOUTS_ISL95338_2 0.22U_0402_25V6K 2.2_0603_5%


<44,45,58,82,83,85> EC_SMB_CK1 SCL VOUTS
6

1
1

23 2 +SDC_IN
PQS30A

PRS78 @ PRS32 0_0402_5%


2

2 PROCHOT# CSOP @ PRS33


100K_0402_1%
FW PG_ISL95338_2 24 1 0_0402_5%
<58,82> FWPG_ISL95338_2 FRWPG CSON 1 2
L2N7002DW1T1G_SC88-6

COMPR
COMPF
RVSPG
ADDR0

ADDR1
1

PROG

VOUT
REF
3

PQS30B

PRS56
VDD_ISL95338_2 1 2
5
58,85> VCIN1_AC_IN
25

26

27

28

29

30

31

32
100K_0402_1%
1

PRS55
PROG_ISL95338_2

COMP_ISL95338_2

REF_ISL95338_2

VOUT_ISL95338_2
200K_0402_1%
4

VDD_ISL95338_2
+3VALW
2

PRS38
1 2 @ PRS39
182K_0402_1% 0_0402_5%
1 2
1

2.2K_0402_1%
2.2K_0402_1%

+SDC_PWR
@ PRS35
@PRS34

PRS40
2

SDA_ISL95338_2 1K_0402_1%
560P_0402_50V7K

0.1U_0402_25V6
1

SCL_ISL95338_2
1
PCS56

PCS57
1

2
ISL95338_N006

PCS58
1

0.022U_0603_50V7K
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/05/16 2018/12/31
PWR_Dual adapter2(ISL95338)
Issued Date Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 84 of 101
A B C D
A B C D

+PWR_SRC

ADP_I = 32*Iadapter*Rsense

EMI@ PL711

100U_D3L_25VM_R60M

100U_D3L_25VM_R60M

100U_D3L_25VM_R60M
PR703 1 1 1
1UH_PCMB063T-1R0MS_12A_20%
1 4 1 2
+SDC_IN
+ + +

PC797

PC798

PC800
2 3
1 1

2 2 2

2200P_0402_50V7K

2200P_0402_50V7K
1000P_0402_25V8J

1000P_0402_25V8J
0.1U_0402_25V6
EMI@

EMI@

EMI@

EMI@

EMI@
10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M
0.001_2512_1%

PC764
1

1
PC760

PC762

PC763
PDS706

PC765

PC705

PC780

PC781

PC794
1_0402_5%
PD706 SMF4L22A_SOD123FL2

1
PR772

2_0402_5%
@ @

2
2

PR740
P1 PC747

2
1 0.1U_0402_25V6
2 1

2
3
P3

0.01U_0402_25V7K
0.033U_0402_25V7K
BAT54CW_SOT323-3

@ PC793
PC792
PQ717
PR745 EMB04N03H_EDFN5X6-8-5

2
100_0402_1%

BATT+
392K_0402_1%
1

5
1 2

PC791 1000P_0402_25V8J

PC750 0.22U_0603_25V7K
PR729

1
PD705
PR773
SS5P10-M3-86A_TO277A3
1 2 4
2

0.01UF_0402_25V7K

0_0603_5%
1

1
53.6K_0402_1%

3
2
PR732

0.1U_0402_25V7K

3
2
1
PC711

30 ASGATE_CHG2

28 OPCN_CHG 2

2
29 CMSRC_CHG

PC779
25 BGATE_CHG
1

27 QPCP_CHG

26 VBAT_CHG
31 CSIN_CHG
32 CSIP_CHG
1 VDD_CHG
2

1
@

PQ704
AON6354_N_DFN56-8-5
2 2

4
100K_0402_1%

PU703 ISL88739AHRZ-T_QFN32_4X4
3S2P: CV = CC=
PR741

PR771 PC721

CSIN

CMSRC

OPCN

VBAT
ASGATE

BGATE
CSIP

QPCP
0_0603_5% 0.47U_0402_25V6K
ACIN_CHG 1 24 BST_CHG 1 2BST_CHG_R 1 2
ACIN BOOT @ PR761 0_0603_5% PL700
2

3
2
1
2 23 UG_CHG 1 2 UG_CHG_R
<12,58,62,83,84> VCIN1_AC_IN @ PR769
1
0_0402_5%
2 SDA_CHG 3
ACOK UGATE
22 LX_CHG
2.2UH_12A_20%_10X10X4_M
1 2 1
PR765
4
BATT+
<44,45,58,82,83,84> EC_SMB_DA1 SDA PHASE
1
200K_0402_1%

@ PR770 0_0402_5%
1 2 SCL_CHG 4 21 LG_CHG 2 3
PR731

<44,45,58,82,83,84> EC_SMB_CK1 @ PR777 0_0402_5% SCL LGATE

1000P_0603_50V7K 4.7_1206_5%
5

1
1 2 PROCHOT#_CHG 5 20 VDOP_CHG

EMI@ PR766

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M
0.1U_0402_25V7K
<6,58,82,91> H_PROCHOT# PR774 1K_0402_1% PROCHOT# VDOP 0.005_2512_1%
2

AMON_CHG 19 VDD_CHG

PQ708
1 2 6 1 2

ISEN1P_CHG
EMP21N03HC_EDFN5X6-8
<58> ADP_I AMON VDO

1
PC778

PC775

PC776

PC777

PC761

PC766
ISEN1N_CHG
@ PR775 0_0402_5%
1 2BMON_CHG 7 18 DCIN_CHG PR760 4.7_0402_5% 4

2
@ PR792 0_0402_5% BMON DCIN

2
1 2 PSYS_CHG 8 17 NTC_CHG

2.2U_0402_16V6K

2.2U_0402_16V6K
<91> P_SYS PSYS NTC

2
BATGONE

EMI@ PC767
100K_0402_1%
CCLIM

ACLIM
COMP
PROG
AGND

CSON

CSOP

PC768

PC769
FSET
2200P_0402_25V7K
0.1U_0402_25V7K

3
2
1
2
10.5K_0402_1%

2
1

PR757
1

2
PC748

PC749

PR727

9
33

10

11

12
BATGONE_CHG 13

14

15

16
@ PD704

10U_0603_25V6M

10U_0603_25V6M
2

1
BAT54CW_SOT323-3

CCLIM_CHG

ACLIM_CHG
COMP_CHG
2

PROG_CHG

CSON_CHG

CSOP_CHG
FSET_CHG
3
P1

1
VDD_CHG

PC795

PC796
PR743 10_1206_5%

1U_0603_25V6
2
@ PR779 1 2 1
0_0402_5%

2
2
2

PC757
P3
200K_0402_1%

PDS705

1
3
1 2 BA_PWR 3
2

2
PR749

0_0402_5%

RB751V-40_SOD323-2
PR750

1 2

10K_0402_1%
@
PR742 2_0402_5%
1

2
PC708

2
0.1U_0402_25V6
255K_0402_1%

0.033U_0402_25V7K 100_0402_1%

102K_0402_1%
2

1
1 2
PR764
560P_0402_50V7K

PQ709
1
2
PR753

PR754

PR755

LMUN5113T1G_SOT323-3
2

3
200K_0402_1%

365K_0402_1%

@ PR756 @ PR776 0_0402_5%

1
PC751

0_0603_5%
10K_0402_1%
1

1 2 2

PR793
+3VALW
1
2

2
PR751

PR752

@
2

2
PC752

@
10P_0402_50V8J

2
PC753

PQ710
LMUN5236T1G_SOT323-3
1

1
VCIN_ BATT_TEMP <58,82>

1
2
<6,12,58,62,78,83> PM_SLP_S3#

BA
3

1
0_0603_5%
PRB66

2 BA_PWR
4 4

DELL CONFIDENTIAL/PROPRIETARY
Security Classification Compal Secret Data Compal Electronics, Inc.
2018/05/16 2018/12/31
PWR_CHARGER
Issued Date Title
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 85 of 101
A B C D
A B C D

+3VLP
PC302
4.7U_0402_6.3V6M
Input Current: 13.06A 1 2

3.4V*13.04A/0.85/12V=4.35A
5.16V*16.7A/0.85/12V=8.45A
1 1

PR301 PR302
10K_0402_1% 15.8K_0402_1%
1 2 1 2
VFB=2V VFB=2V
Output capacitor ESR need follow
PR303 PR304
14.3K_0402_1% 10K_0402_1%
below equation to make sure feed back
1 2 1 2 loop stability
ESR=20mV*L*fsw/2V

EMI@ PL311
3/5V_B+

1
5A_Z80_0805_2P PR305 PR306
1 2 54.9K_0402_1% 61.9K_0402_1%
EMI@ PL312 POK need pull high, it
5A_Z80_0805_2P
+PWR_SRC 1 2 3/5V_B+ will pull high on VS
transfer circuit

22U_0805_25V6M

22U_0805_25V6M
1

1
FB_3V

FB_5V

PC303

PC304
PQ301

CS2

CS1
1000P_0402_50V7K

2200P_0402_50V7K

22U_0805_25V6M

22U_0805_25V6M
1U_0402_25V6K

0.1U_0402_25V6

AON7534_DFN3X3-8-5

2
1

5
EMI@ PC301

EMI@ PC305

EMI@ PC306

EMI@ PC307

PC308

PC309
<58> POK

5
PU301 PQ303
2

1
AON7534_DFN3X3-8-5
4 21

VFB2

VFB1
CS2

VREG3

CS1
3V_EN 6 PAD
EN2 20 5V_EN 4
EN1 @ PR307
DCR = 18mohm 7
PGOOD 19
200_0402_1%
VCLK_5V1 2
DCR = 6mohm

1
2
3
VCLK
PL301 LX_3V 8 TPS51225CRUKR_QFN20_3X3

3
2
1
2
1.5UH_MMD-10CZN1R5M-R1L_16A_20% PC310 PR309 SW2 18 LX_5V PL302
2

1 2 LX_3V 0.1U_0402_25V6 0_0603_5% SW1 PR308 PC311 1.5UH_MMD-10CZN1R5M-R1L_16A_20%


+3VALWP 2BST2_3V1 BST_3V LX_5V
1 2 9
VBST2
0_0603_5%
BST_5V
1 2 +5VALWP
17 1 2BST2_5V1 2

AON7508_DFN8-5
VBST1
1 1

PQ302
UG_3V 10 0.1U_0402_25V6

AON7508_DFN8-5
1 1

220U_D2_6.3VY_R15M

220U_D2_6.3VY_R15M
DRVH2
1

5
16 UG_5V
4.7_1206_5%

680P_0603_50V8J 4.7_1206_5%
+ +
220U_D2_6.3VY_R15M

220U_D2_6.3VY_R15M

ESR = 15mohm
DRVH1

1
PQ304
EMI@ PR310

EMI@ PR311

PC314

PC315
+ +

VREG5
DRVL2

DRVL1
PC312

PC313

VO1
2 2

VIN
2 2 4 4
2
SNB_3V

2
11

12

13

14

15
LG_3V

SNB_5V
LG_5V
680P_0603_50V8J

ESR = 15mohm
1

1
EMI@ PC316

EMI@ PC317
1
2
3

3
2
1
3/5V_B+ +5VALWP
3.3VALWP
2

2
VL
Vout=3.4V
TDC=9.128A

1
PC318
Peak Current 13.04A 4.7U_0402_6.3V6M 5VALWP
OCP current 15.65A OVP=Vout*(112.5%~117.5%) Vout=5.16V

2
FSW=355kHz TDC=13.33A
TYP MAX OCP=Vtrip/Rdson+Iripple/2 Peak Current 15.4A (12.73+2.26+0.41)
H/S Rds(on) : 6.7mohm 8.5mohm Vtrip=Ics(min)*Rcs/8+1mV OCP current 18.48A
L/S Rds(on) : 3.3mohm 4.1mohm Vcs=Ics*vcs should be in the range of 0.2~2V FSW=300kHz
TYP MAX
EN
Vout=VFB*(1+Rtop/Rbot) H/S Rds(on) : 6.7mohm 8.5mohm
Rising=1.6~0.3V @ PR312
VFB=2V L/S Rds(on) : 3.3mohm 4.1mohm
3
0_0402_5% 3

3V_EN 1 2

@ PR313
0_0402_5%
5V_EN 1 2 PJP302 PJP301
+5VALWP 1 2 +5VALW +3VALWP 1 2 +3VALW
1 2 1 2
PD301 PR314 JUMP_43X118 @ JUMP_43X118 @
2 2.2K_0402_1% PJP303 PJP304
3V_5V_EN

<58> EC_ON 1PD100_3/5V1 2 1 2 1 2


3 1 2 1 2
<71> USBCHG_DET_D JUMP_43X118 @ JUMP_43X118 @
BAS40CW_SOT323-3

@ PR315
0_0402_5%
1 2
<58> VCOUT0_MAIN_PWR_ON#
200K_0402_1%

4.7U_0402_6.3V6M
1
PR317

PC319
2
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/05/16 2018/12/31
PWR_+3.3VALWP/+5VALWP
Issued Date Title
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 86 of 101
A B C D
5 4 3 2 1

Input Current: 1.17A


1.2V*9.93A/0.85/12V=1.17A

D D

Pin19 need pull separate from +1.2VP.


If you have +1.2V and +0.6V sequence question, +0.6VSP
you can change from +1.2VP to +1.2VS. TDC 2.1A
+PWR_SRC 1
PJP203@
2 1.2V_B+ PR200 Peak Current 3A
1 2 2.2_0603_5%

+1.2VP
JUMP_43X39 2200P_0402_50V7K BST_1.2V 1 2 BOOT_1.2V
0.1U_0402_25V6

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M
1

1U_0402_25V6K

1000P_0402_50V7K
+0.6VSP
EMI@ PC200

EMI@ PC201

PC202

PC203

@ PC220

@ PC219

1
DH_1.2V

EMI@ PC208

EMI@ PC216
2

2
SW _1.2V

10U_0603_6.3V6M

10U_0603_6.3V6M
1
PC204

AON6380_DFN5X6-8-5
5

1
0.1U_0603_25V7K

PC205

PC206
PQ200
PU201

16

17

18

19

20
C C

2
21

VLDOIN
PHASE

VTT
UGATE

BOOT
4 PAD
DL_1.2V 15 1
LGATE VTTGND

14 2
PL201 PR201 PGND VTTSNS

1
2
3
1UH_MMD-10CZN1R0M-R1L_20A_20% 11K_0402_1%

+1.2VP
1 2 1 2 CS_1.2V 13 3
PC207 CS RT8207PGQW _W QFN20_3X3 GND
1U_0603_10V6K
1

1 2VDDP_1.2V
12 4 VTTREF_1.2V
@EMI@ PR202 30MA_30V_0.5UA_0.4V_SOD323-2 VDDP VTTREF
1 1
4.7_1206_5% 5 PQ201 PD200
220U 2.5V Y D2 ESR9M H1.9 SX

220U 2.5V Y D2 ESR9M H1.9 SX

+1.2VP
+ + AON6354_N_DFN56-8-5 PR203 2 1 11 5
SNB_1.2V 5.1_0603_5% VDD VDDQ
PC209

PC215

1 2

1
+5VALW
VDD_1.2V

PGOOD
1 2 PC210
2 2
+1.2VP @EMI@ PC211 4 0.033U_0402_16V7K

TON
TDC=13.6A 680P_0402_50V7K

FB
S5

S3

2
2.2_0603_5%
Ipeak=19.43A
2

2
PC212

6
10
OCP=23.3A 2.2U_0402_6.3V6M

PR204
Switching Frequency: 285kHz
1
2
3

2
PR205

PGOOD_1.2V

FB_1.2V
+1.2VP

EN_0.6VSP
12K_0402_1%

EN_1.2V
1
1 2
@ PR210

TON_1.2V
B
OVP: 110%~120% +3VALW
1 2 B

VFB=0.75V, Vout=1.2V PR206

1
100K_0402_1% 887K_0402_1%
TYP MAX

1
1.2V_B+ 1 2 PR213

20K_0402_1%

60.4K_0402_1%
H/S Rds(on) : 8.2mohm 10.5mohm @ PR208 60.4K_0402_1%
L/S Rds(on) : 4.0mohm 5.2mohm 0_0402_5%

PR207

PR215
1 2

L2N7002DW1T1G_SC88-6
<58,78> SYSON

2
@

XMP1-2
2

2
@ PJP201 PR212

6
Mode Level +0.6VSP VTTREF_1.2V 1
1 2
2 @ PC213 1K_0402_1%

1
S5 L off off

PQ202A
0.1U_0402_10V7K
JUMP_43X118 2 XMP1-1 2 1 XMP1 <13>
S3 L off on @ PJP200

2
S0 H on on +1.2VP 1
1 2
2 +1.2V_DDR

1
XMP2-2

100K_0402_1%
0.1U_0402_25V6
1
JUMP_43X118 @ PR209

PC217

PR216
Note: S3 - sleep ; S5 - power off 2 1

L2N7002DW1T1G_SC88-6
<42,56,58,59,68,78,89> SUSP#

2
0_0402_5%

2
3
2 1

PQ202B
<6> SM_PG_CTRL
PJP202@
1 2 @ PR211 5XMP2-1 2 1 XMP2 <13>
+0.6VSP 1 2 +0.6VS 0_0402_5% PR214

@ PC214
0.1U_0402_10V7K

1
JUMP_43X39 1K_0402_1%

100K_0402_1%
@

PC218

@ PR217
0.1U_0402_25V6
2

2
@

2
A A

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/05/16 2018/12/31 Title

PWR_1.2VP/0.6VSP
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 87 of 101
5 4 3 2 1
5 4 3 2 1

PJP101@

+PWR_SRC
+1VALWP_B+ 1 2
1 2
JUMP_43X39

10U_0603_25V6M

10U_0603_25V6M

1U_0402_25V6K
2200P_0402_50V7K

1000P_0402_50V7K
0.1U_0402_25V6
+3VALW

1
EMI@ PC102

EMI@ PC103

PC104

PC105

EMI@ PC106

EMI@ PC101
@

2
5
1
PR101
Input Current: 0.86A

AON7408L_DFN8-5
D 100K_0402_1% D
<58> +1VALWP_PGOOD
4 1.05V*8.31A/0.85/12V=0.86A

PQ101
2
PR102 PC107
PU101 2.2_0603_5% 0.1U_0603_25V7K
PR103 1 10 BST_+1VALW P 1 2BST2_+1VALW
1 P 2
97.6K_0402_1% PGOOD VBST

3
2
1
1 2 TRIP_+1VALW P 2 9 UG_+1VALW P PL101
PR104 TRIP DRVH 1UH_11A_20%_7X7X3_M

+1VALWP
1 2 EN_+1VALW P 3 8 SW _+1VALW P 1 2
<12,37,58,78,98> PCH_PW R_EN EN SW

+5VALW
FB_+1VALW P 4 7
100K_0402_1% VFB V5IN

AON7752_DFN3X3EP8-5
5

1
RF_+1VALW P 5 6 LG_+1VALW P

0.1U_0402_16V7K
TST DRVL

PQ102
PR105 @EMI@ 1 1
+1VALW

1
11 4.7_1206_5%

220U 2.5V Y D2 ESR9M H1.9 SX

220U 2.5V Y D2 ESR9M H1.9 SX


PC108
TP

1
+ +
Vout=1.05V

1
PR106 TPS51212DSCR_SON10_3X3 PC109 4

PC110

PC111
2

2
TDC 5.82A
470K_0402_1% 1U_0603_6.3V6M SNB_+1VALW P
PC112 @EMI@ 2 2
Peak Current 8.31A

1
680P_0402_50V7K

2
OCP current 10.07A
FSW=290kHz

3
2
1

2
Vout=0.7V* (1+Rup/Rdown)
Switching Frequency: 290kHz
C PR107
4.99K_0402_1%
OVP: 120%-130% C

1 2 VFB=0.7V
TYP MAX
Rup H/S Rds(on) : 22.7mohm 32mohm
L/S Rds(on) : 11.6mohm 14.5mohm
1

PR108
Rdown

10K_0402_1%
2

@ PJP102
+1VALWP 1
1 2
2 +1VALW
JUMP_43X118

@ PJP103
1 2
1 2
JUMP_43X118

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/05/16 2018/12/31 Title

PWR_+1VALWP
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 88 of 101
5 4 3 2 1
5 4 3 2 1

Input Current: 0.6A


0.95V*6.4A/0.85/12V=0.6A
10K_0402_1%

+3VS
VCCIO_PGOOD 2 1

+PWR_SRC @ PRF02

+VCCIOP +VCCIO
PJPF01 @ PJPF02
1 2 B+_VCCIO 1 2
1 2 1 2
JUMP_43X39 JUMP_43X118 @

10U_0603_25V6M

1U_0402_25V6K

1000P_0402_50V7K
PUF01

EMI@ PCF02
0.1U_0402_25V6
2200P_0402_50V7K
1

1
2 9 PRF03 PCF06

EMI@ PCF01

PCF03

EMI@ PCF04

EMI@ PCF05
IN PG 0_0603_5% 0.1U_0603_25V7K
3 1 BST_VCCIO 1 2BST2_VCCIO 1 2 PLF01

2
+VCCIOP
2

2
D IN BS 1UH_PCMB042T-1R0MS_4.5A_20%
D
4 6 LX_VCCIO 1 2
IN LX
5 19
IN LX

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
1
7 20 PRF04
GND LX

1
PCF08

PCF10
4.7_1206_5%
8 14 FB_VCCIO

PCF07

PCF09
GND FB @EMI@

330P_0402_50V7K

2
@ PRF01 18 17 VCC_VCCIO

2
GND VCC

1
SNB_VCCIO

PCF11

100_0402_5%
<42,56,58,59,68,78,87> SUSP# 1 2 EN_VCCIO 11 10

PRF05
EN NC

4.7U_0402_6.3V6M

2
ILIM_VCCIO 13 12
ILMT NC

1
0_0402_5%

PCF13
0.22U_0402_10V6K

2
1

1
+3VALW 15 16 PCF14
PCF12

1M_0402_1%
BYP NC
PRF06

680P_0603_50V7K

2
@ 21 @EMI@
Rup
2

2
PAD
SY8286RAC_QFN20_3X3

2.2U_0402_6.3V6M
2

PRF07 @ PRF08

PCF15
1
2 1 SENSE_VCCIO 1 2
VCCIO_SENSE <9>

+3VALW 21K_0402_1%

2
0_0402_5%
2

1
PRF09 @

35.7K_0402_1%
Rdown

PRF10
0_0402_5%
1

2
2

PRF11 @
0_0402_5%

C C
1

+VCCIOP (0.95V)
TDC 4.48 A
Peak Current 6.4 A
OCP Current 9 A Fix by IC
TYP MAX
Choke DCR 24.0mohm , 27.0mohm

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/05/16 2018/12/31
PWR_+VCCIO
Issued Date Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 89 of 101
5 4 3 2 1
A B C D

Input Current:0.41A
2.5V*0.7A/0.85/5V=0.41A

+3VALW
1 1

@ PR2501

2 1 +2.5VSP_ON
<58,78> PM_SLP_S4#

1
0_0402_5% @ PR2503

0.1U_0402_16V7K
1

1M_0402_1%
100K_0402_1%

1
PR2502

PC2501
Input 0.7A @

2
PU2501

9
@ PJP2501 +2.5VSP_PGOOD 1 8
2 PGOOD GND 7 +2.5VSP_ADJ
+5VALW

GND
1 2 +2.5VSP_VIN 3 EN ADJ 6
1 2 4 VIN VOUT 5 +2.5V_MEMP
VDD NC
JUMP_43X79 RT9059GSP_SO8

1
1

1
PR2504

22U_0603_6.3V6M

22U_0603_6.3V6M

1
PC2502

PC2503

22P_0603_50V8
21.5K_0402_1%

1
@ PC2504

22U_0603_6.3V6M

22U_0603_6.3V6M
2

PC2505

PC2506
2
2

2
PR2506
1 2
Vout=0.8V* (1+Rup/Rdown)

1
Rdown
2
2.2_0402_1% PR2505 2

10K_0402_1%

1
2.2U_0402_6.3V6K
PC2507

2
2
@ PJP2502

1 2
+2.5V_MEMP 1 2 +2.5V_MEM
JUMP_43X79

+2.5V_MEM
TDC 0.49A
Peak Current 0.7A
OCP Current 3.5A

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/05/16 2018/12/31 Title

PWR_+2.5V_MEM
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 90 of 101
A B C D
5 4 3 2 1

<6,58,82,85> H_PROCHOT#

47P_0402_50V8J~D
+5VS

PCZ02
+1.05V_VCCST CPU_B+

2
0_0402_5%

0_0402_5%
1
PRZ02

PRZ04
1_0402_5%
0.1U_0402_25V6
D D

1
PCZ03

PRZ03
PCZ01
45.3_0402_1%

75_0402_1%

100_0402_1%
@ @

PRZ06
PRZ01

PRZ05

1
@ 1U_0402_16V6K

2
2

2
2 1 1 2 1 2
<6> VR_SVID_CLK
@ PRZ07 0_0402_5% 49.9_0402_1% PRZ08
2 1 1 2
<6> VR_SVID_ALRT#
PRZ11 @ PRZ09 0_0402_5% 0_0402_5% @ PRZ10
1 2 2 1 1 2 1 2
PHZ01 <6> VR_SVID_OUT
@ PRZ12 0_0402_5% 10_0402_1% PRZ13
95.3K_0402_1% 1 2 PCZ04
0.22U_0603_25V7K
PCZ05
470K_0402_5%_B25/50 4700K
1 2
PRZ15
330P_0402_50V7K PRZ14
27.4K_0402_1%
12.4K_0402_1% +3VS
1 2 1 2
PCZ06 PRZ16
1000P_0402_50V7K 1 2

1
PCZ07 1 2 1.91K_0402_1%

150K_0402_1%

210K_0402_1%
9.31K_0402_1%

48.7K_0402_1%
1

PRZ17

PRZ18

PRZ19

PRZ20
1 2 @ PRZ21

68P_0402_50V8J <58> VR_PWRGD


1 2

2
2
PCZ08 PRZ22 PCZ09 PRZ23 0_0402_5%
2 1 2 1 @ PRZ24
1 2 1 2 1 2
<58,78,96> IMVP_VR_ON

VCC_VCORE
1500P_0402_50V7K
6800P_0402_25V7K 2K_0402_1% 2K_0402_1% 0_0402_5%

PUZ01
PCZ10 PRZ25 <85> P_SYS PRZ27
C 1200P_0402_50V7K 316_0402_1% ISL95829CHRTZ-T_TQFN48_6X6 C
1 2 1 2 48.7K_0402_1%

48
47
46
45
44
43
42
41
40
39
38
37
1
1 2

0_0402_5%
PRZ26

VCC
VIN
VR_ENABLE
VR_READY

SDA
SCLK
VR_HOT#

PROG1
PROG2
PROG3
PROG4
ALERT#
PRZ28
2.8K_0402_1% @
2 1
<9> VCCGT_VCC_SEN

2
1 36
2 PSYS PROG5 35 @ PRZ44
<9> VCCGT_VSS_SEN IMON_B PWM_C
3 34 0_0402_5%
+5VS
4 NTC_B FCCM_C 33 1 2
5 COMP_B ISUMN_C 32
FB_B ISUMP_C
1
PCZ11 6 31
RTN_B RTN_C
0.01UF_0402_25V7K 7 30
8 ISUMP_B FB_C 29
2

9 ISUMN_B COMP_C 28
10 ISEN1_B IMON_C 27
<95> ISUMP_GT ISEN2_B PWM3_A
11 26
12 FCCM_B PWM2_A 25
PWM1_B PWM1_A
4.42K_0402_1%
1

1
PRZ29

PRZ31 PCZ14
PRZ30
11K_0402_1%

49

ISUMN_A
ISUMP_A
PWM2_B

COMP_A

ISEN1_A
ISEN2_A
ISEN3_A
FCCM_A
EP
1

0.022U_0402_16V7K
0.15U_0402_16V7K

IMON_A
1 2 1 2
PCZ12

NTC_A

RTN_A
FB_A
PCZ13

PWM3_VCORE <94>
1 2

1K_0402_1% 2200P_0402_50V7K
2

10K +-5% 0402 B25/50 4250K PWM2_VCORE <93>

13
14
15
16
17
18
19
20
21
22
23
24
PHZ02 PRZ32 PWM1_VCORE <92>
1 2
<95> ISUMN_GT
2

FCCM_VCORE <92,93,94>
243_0402_1%
1

1 2
PCZ15
.1U_0402_16V7K

PCZ17 <94> ISEN3_VCORE PCZ16 0.022U_0402_25V7K


2

B ISEN2_GT <95> B
1 2
1 2
0.022U_0402_25V7K ISUMN_VCORE <92,93,94>
<93> ISEN2_VCORE PCZ18 0.022U_0402_25V7K
PCZ20
0.022U_0402_25V7K 1 2
ISEN1_GT <95>
1 2 PHZ03

1
PRZ33 <92> ISEN1_VCORE PCZ19 0.022U_0402_25V7K
10K +-5% 0402 B25/50 4250K

.1U_0402_16V7K

0.022U_0402_16V7K
PCZ21
<95> FCCM_GT

11K_0402_1%
1
1 2

0.22U_0402_25V6K

PRZ34
<95> PWM1_GT

1
523_0402_1%

PCZ22

PCZ23

2
<95> PWM2_GT PCZ24 PRZ35

1
1 2 1 2 PRZ36
2.61K_0402_1%
2200P_0402_50V7K 1K_0402_1%
ISUMP_VCORE <92,93,94>

2
VCORE_VSS_SEN <9>
PRZ37 VCORE_VCC_SEN <9>
12.4K_0402_1% 1 2 2 1
1 2

2
PRZ38 PCZ25 PCZ26

20M_0402_5%
1
330P_0402_50V7K

1K_0402_1% 100P_0402_50V8J 0.01UF_0402_25V7K

PRZ45
1

PRZ39
PCZ27
2

27.4K_0402_1%
2

1000P_0402_50V7K

2 1
470K_0402_5%_B25/50 4700K

2K_0402_1%

2
2

1
76.8K_0402_1% @
PRZ40

PHZ04

1
2

PRZ42
PCZ28

PRZ41
1

6.04K_0402_1%
2

PRZ43
1

1
1

2
68P_0402_50V8J

1.27K_0402_1%
2
1

PCZ29

PCZ31

A A
1500P_0402_50V7K

PCZ30
2

8200P_0402_25V7K
1

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/05/16 2018/12/31 Title

PWR_VCORE_ISL95829C
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 91 of 101
5 4 3 2 1
A B C D

+5VS

PRI201
698_0402_1% PCI204

1
CORE_V1N 1 2 1U_0402_6.3V6K

47P_0402_50V8J

2
PCI205

1
2.2U_0402_16V6K PUI07 @ PRI209

PCI201
ISL6617CRZ-T_DFN10_3X3 0_0402_5%
PRI210 1 10 1 2 PWM1_IA

2
100_0402_1% ISENA+ PWMA PRI208 PRI207
CORE_V1P 1 2 2 9 1 2 1 2
@ PRI206 ISENA- VCC 10K_0402_1% 15K_0402_1%
1 2 3 8 1 2
1 1

<91> PWM1_VCORE PWMIN IOUT


PRI204 30.1K_0402_1% PRI202
CORE_V2N 0_0402_5% 1 2 4 7
ISENB+ EN_PH_SYNC @ PRI205
698_0402_1%
5 6 1 2 PWM2_IA

47P_0402_50V8J
+VCC_CORE
PCI203 ISENB- PWMB

1
TDC PL2 :150A
11

PCI202
2.2U_0402_16V6K 0_0402_5%
GND
PRI203
Peak Current 193A

2
OCP Current
100_0402_1%
CORE_V2P 1 2

PCI06 DCR 0.98mohm +/-5%


PRI11 Load Line 1.6mV/A
+5VS
1 2 1 2
1_0402_5%
@ PRI13 0_0402_5% 1U_0402_6.3V6K
PWM1_IA 1 2

10K_0402_1%
2

2
1_0402_5%
+PWR_SRC CPU_B+
@ PRI15 0_0402_5%

PRI12

PRI14
PCI07 1 2 PUI01

1 2
<91,93,94> FCCM_VCORE 1
2 PWM CGND
28
27
+VCC_CORE

1
PCI08 3 ZCD_EN# GL 26
EMI@ PLI12 1U_0402_6.3V6K 0.22U_0603_16V7K 4 VCIN DSBL# 25
1 2 1 2 5 CGND THWn 24
6 BOOT VDRV 23 PLI01
Use 0603 size
9A Z80 10M 1812_2P 1 PRI16 2 7 NC PGND 22 0.22UH_MMD-06DZIR22MEM2L__32A_20%
EMI@ PLI11 8 PHASE GL 21 VCC_CORE_PH1 1 4
1 2 2.2_0603_1% 9 VIN SW 20
10 VIN SW 19 CORE_V1P 2 3

@EMI@ PCI17 @EMI@ PRI17


PGND SW

1
9A Z80 10M 1812_2P 11 18
12 SW SW 17

33P_0603_50V8J 10_1206_5%
13 SW SW 16 PRI18 PRI19
14 SW SW 15 7.5K_0603_1% 200K_0402_1%
1 SW SW 1 2 1 2
100U_25V_M
1000P_0402_50V7K

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M
1U_0402_25V6K

2200P_0402_50V7K

2
EMI@ PCI16
+

0.1U_0402_25V6
SIC632CDT1GE3_POWERPAK31_5X5
1

1
EMI@ PCI09

EMI@ PCI10

PCI11

PCI12

PCI13

PCI14

PCI139

EMI@ PCI15
2 2

<91> ISEN1_VCORE

2
2

10_0402_1%
2

2
PRI22

PRI20
2
200K_0402_1%
1 2
<93,94> CORE_V3N

1
PRI23
200K_0402_1%
1 2
<93,94> CORE_V5N

<91,93,94>
ISUMP_VCORE

<91,93,94>
ISUMN_VCORE

<93,94>
CORE_V1N
PCI18
PRI27
+5VS
1 2 1 2
1_0402_5%
@ PRI28 0_0402_5% 1U_0402_6.3V6K
PWM2_IA 1 2

10K_0402_1%
2

2
1_0402_5%

@ PRI31 0_0402_5%
PRI29

PRI30
3 FCCM_VCORE 1 2 PUI02 3

PCI19 1 28
2 PWM CGND 27
1

1
1 2 3 ZCD_EN# GL 26
PCI20 4 VCIN DSBL# 25
1U_0402_6.3V6K 1 2 5 CGND THWn 24
6 BOOT VDRV 23 PLI02
0.22U_0603_16V7K
Use 0603 size 1 2 7 NC PGND 22 0.22UH_MMD-06DZIR22MEM2L__32A_20%
PRI32 8 PHASE GL 21 VCC_CORE_PH2 1 4
2.2_0603_1% 9 VIN SW 20
10 VIN SW 19 CORE_V2P 2 3
11 PGND SW 18
12 SW SW 17
13 SW SW 16 PRI33 PRI34
1 1 SW SW
14 15
100U_25V_M

100U_25V_M

7.5K_0603_1% 200K_0402_1%
10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

1000P_0402_50V7K
1U_0402_25V6K
2200P_0402_50V7K

SW SW 1 2 1 2
EMI@ PCI25

+ +
0.1U_0402_25V6

@EMI@ PRI35
1

1
PCI21

EMI@ PCI27

EMI@ PCI28
PCI140

PCI146

PCI147

PCI148

PCI141

EMI@ PCI26

SIC632CDT1GE3_POWERPAK31_5X5

10_1206_5%
2 2 ISEN1_VCORE
2

ISUMP_VCORE

2
10_0402_1%
2
PRI37

PRI36
200K_0402_1%
1 2
<93,94> CORE_V4N

1
@EMI@ PCI29
33P_0603_50V8J

1
2 PRI38
200K_0402_1%
1 2

ISUMN_VCORE
<93,94> CORE_V6N

4 4

<93,94>
CORE_V2N
Security Classification Compal Secret Data Compal Electronics, Inc.
2018/05/16 2018/12/31
PWR_+VCC_CORE
Issued Date Title
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 92 of 101
A B C D
A B C D

+5VS

PRI218
698_0402_1% PCI206

1
CORE_V3N 1 2 1U_0402_6.3V6K

47P_0402_50V8J

2
PCI209

1
2.2U_0402_16V6K PUI08 @ PRI212

PCI208
ISL6617CRZ-T_DFN10_3X3 0_0402_5%
PRI220 1 10 1 2 PWM3_IA

2
100_0402_1% ISENA+ PWMA PRI217 PRI214
CORE_V3P 1 2 2 9 1 2 1 2
@ PRI213 ISENA- VCC 10K_0402_1% 15K_0402_1%
1 2 3 8 1 2
1 1

<91> PWM2_VCORE PWMIN IOUT


PRI211 30.1K_0402_1% PRI216
+VCC_CORE
CORE_V4N 0_0402_5% 1 2 4 7
ISENB+ EN_PH_SYNC
TDC PL2 :150A
698_0402_1% @ PRI219
5 6 1 2 PWM4_IA

47P_0402_50V8J
Peak Current 190A
PCI207 ISENB- PWMB

1
11
OCP Current

PCI210
2.2U_0402_16V6K 0_0402_5%
GND

DCR 0.98mohm +/-5%


PRI215 2

2
100_0402_1%
CORE_V4P 1 2
Load Line 1.6mV/A
PCI35
PRI52
+5VS
1 2 1 2
@ PRI53 0_0402_5% 1_0402_5%
PWM3_IA 1 2 1U_0402_6.3V6K

10K_0402_1%
2

2
1_0402_5%
@ PRI56 0_0402_5%
1 2
CPU_B+

PRI54

PRI55
<91,92,94> FCCM_VCORE PUI03
PCI36
1U_0402_6.3V6K 1
2 PWM CGND
28
27
+VCC_CORE

1
1 2 3 ZCD_EN# GL 26
PCI37 4 VCIN DSBL# 25
1 2 5 CGND THWn 24
6 BOOT VDRV 23 PLI03
0.22U_0603_16V7K
Use 0603 size 1 2 7 NC PGND 22 0.22UH_MMD-06DZIR22MEM2L__32A_20%
PRI57 8 PHASE GL 21 VCC_CORE_PH3 1 4
2.2_0603_1% 9 VIN SW 20
10 VIN SW 19 CORE_V3P 2 3

@EMI@ PRI58
11 PGND SW 18
SW SW

1
12 17

10_1206_5%
13 SW SW 16 PRI59 PRI60
14 SW SW 15 7.5K_0603_1% 200K_0402_1%
10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

1000P_0402_50V7K
1U_0402_25V6K
2200P_0402_50V7K
SW SW 1 2 1 2

EMI@ PCI41
0.1U_0402_25V6
1

1
PCI38

PCI39

PCI40

EMI@ PCI43

EMI@ PCI44
PCI142

EMI@ PCI42
SIC632CDT1GE3_POWERPAK31_5X5

2
2 2

<91> ISEN2_VCORE
2

@EMI@ PCI45
33P_0603_50V8J
1

2
PRI62

10_0402_1%
200K_0402_1%

PRI61
2
1 2
<92,94> CORE_V1N

<91,92,94>
ISUMP_VCORE

1
PRI63
200K_0402_1%
1 2
<92,94> CORE_V5N

<91,92,94>

<92,94>
ISUMN_VCORE

CORE_V3N
PCI46
PRI67
+5VS
1 2 1 2
@ PRI68 0_0402_5% 1_0402_5%
PWM4_IA 1 2 1U_0402_6.3V6K

10K_0402_1%
2

2
1_0402_5%

@ PRI71 0_0402_5%
FCCM_VCORE 1 2
PRI69

PRI70
3
PCI48 PUI04 3

1U_0402_6.3V6K 1 28
2 PWM CGND 27
1

1
1 2 3 ZCD_EN# GL 26
PCI47 4 VCIN DSBL# 25
1 2 5 CGND THWn 24
6 BOOT VDRV 23 PLI04
0.22U_0603_16V7K
Use 0603 size 1 2 7 NC PGND 22 0.22UH_MMD-06DZIR22MEM2L__32A_20%
PRI72 8 PHASE GL 21 VCC_CORE_PH4 1 4
2.2_0603_1% 9 VIN SW 20
10 VIN SW 19 CORE_V4P 2 3

@EMI@ PRI73
11 PGND SW 18
SW SW

1
12 17

10_1206_5%
13 SW SW 16 PRI74 PRI75
14 SW SW 15 7.5K_0603_1% 200K_0402_1%
10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

1000P_0402_50V7K
1U_0402_25V6K
2200P_0402_50V7K

SW SW 1 2 1 2
EMI@ PCI52
0.1U_0402_25V6
1

1
PCI49

PCI50

PCI51

EMI@ PCI54

EMI@ PCI55
PCI143

EMI@ PCI53

SIC632CDT1GE3_POWERPAK31_5X5

2
ISEN2_VCORE
2

@EMI@ PCI56
33P_0603_50V8J
1

ISUMP_VCORE

2
PRI77

10_0402_1%
200K_0402_1%

PRI76
2
1 2
<92,94> CORE_V2N

1
PRI78
200K_0402_1%
1 2

ISUMN_VCORE
<92,94> CORE_V6N

<92,94>
CORE_V4N
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/05/16 2018/12/31
PWR_+VCC_CORE
Issued Date Title
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 93 of 101
A B C D
A B C D

+5VS

PRI230
698_0402_1% PCI211

1
CORE_V5N 1 2 1U_0402_6.3V6K

47P_0402_50V8J

2
PCI214

1
2.2U_0402_16V6K PUI09 @ PRI224

PCI213
ISL6617CRZ-T_DFN10_3X3 0_0402_5%
PRI221 1 10 1 2 PWM5_IA

2
100_0402_1% ISENA+ PWMA PRI229 PRI226
CORE_V5P 1 2 2 9 1 2 1 2
@ PRI225 ISENA- VCC 10K_0402_1% 15K_0402_1%
1 2 3 8 1 2
1 1

<91> PWM3_VCORE PWMIN IOUT


PRI223 30.1K_0402_1% PRI228
+VCC_CORE
CORE_V6N 0_0402_5% 1 2 4 7
ISENB+ EN_PH_SYNC
TDC PL2 :150A
698_0402_1% @ PRI222
5 6 1 2 PWM6_IA

47P_0402_50V8J
Peak Current 190A
PCI212 ISENB- PWMB

1
11
OCP Current

PCI215
2.2U_0402_16V6K 0_0402_5%
GND

DCR 0.98mohm +/-5%


PRI227
2

2
100_0402_1%
CORE_V6P 1 2
Load Line 1.6mV/A
PCI62
PRI92
+5VS
1 2 1 2
@ PRI93 0_0402_5% 1_0402_5%
PWM5_IA 1 2 1U_0402_6.3V6K

10K_0402_1%
2

2
1_0402_5%
@ PRI96 0_0402_5%
1 2
CPU_B+

PRI94

PRI95
<91,92,93> FCCM_VCORE PUI05
PCI63
1U_0402_6.3V6K 1
2 PWM CGND
28
27
+VCC_CORE

1
1 2 3 ZCD_EN# GL 26
PCI64 4 VCIN DSBL# 25
1 2 5 CGND THWn 24
6 BOOT VDRV 23 PLI05
0.22U_0603_16V7K
Use 0603 size 1 2 7 NC PGND 22 0.22UH_MMD-06DZIR22MEM2L__32A_20%
PRI97 8 PHASE GL 21 VCC_CORE_PH5 1 4
2.2_0603_1% 9 VIN SW 20
10 VIN SW 19 CORE_V5P 2 3

@EMI@ PRI98
11 PGND SW 18
SW SW

1
12 17

10_1206_5%
13 SW SW 16 PRI99 PRI100
14 SW SW 15 7.5K_0603_1% 200K_0402_1%
10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

1000P_0402_50V7K
1U_0402_25V6K
2200P_0402_50V7K
SW SW 1 2 1 2

EMI@ PCI68
0.1U_0402_25V6
1

1
PCI65

PCI66

PCI67

EMI@ PCI70

EMI@ PCI71
PCI144

EMI@ PCI69
SIC632CDT1GE3_POWERPAK31_5X5

2
2 2

<91> ISEN3_VCORE
2

@EMI@ PCI72
33P_0603_50V8J
1

2
PRI102

10_0402_1%
200K_0402_1%

PRI101
2
1 2
<92,93> CORE_V1N

1
PRI103
200K_0402_1%
1 2
<92,93> CORE_V3N

<91,92,93>
ISUMP_VCORE

<91,92,93>
ISUMN_VCORE

<92,93>
CORE_V5N
PCI73
PRI107
+5VS
1 2 1 2
@ PRI108 0_0402_5% 1_0402_5%
PWM6_IA 1 2 1U_0402_6.3V6K

10K_0402_1%
2

2
1_0402_5%

@ PRI111 0_0402_5%
FCCM_VCORE 1 2
PRI109

PRI110
3
PCI74 PUI06 3

1U_0402_6.3V6K 1 28
2 PWM CGND 27
1

1
1 2 3 ZCD_EN# GL 26
PCI75 4 VCIN DSBL# 25
1 2 5 CGND THWn 24
6 BOOT VDRV 23 PLI06
0.22U_0603_16V7K
Use 0603 size 1 2 7 NC PGND 22 0.22UH_MMD-06DZIR22MEM2L__32A_20%
PRI112 8 PHASE GL 21 VCC_CORE_PH6 1 4
2.2_0603_1% 9 VIN SW 20
10 VIN SW 19 CORE_V6P 2 3

@EMI@ PRI113
11 PGND SW 18
SW SW

1
12 17

10_1206_5%
13 SW SW 16 PRI114 PRI115
14 SW SW 15 7.5K_0603_1% 200K_0402_1%
10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

1000P_0402_50V7K
1U_0402_25V6K
2200P_0402_50V7K

SW SW 1 2 1 2
EMI@ PCI79
0.1U_0402_25V6
1

1
PCI76

PCI77

PCI78

EMI@ PCI81

EMI@ PCI82
PCI145

EMI@ PCI80

SIC632CDT1GE3_POWERPAK31_5X5

2
ISEN3_VCORE
2

@EMI@ PCI83
33P_0603_50V8J
1

ISUMP_VCORE

2
PRI117

10_0402_1%
200K_0402_1%

PRI116
2
1 2
<92,93> CORE_V2N

1
PRI118
200K_0402_1%
1 2

ISUMN_VCORE
<92,93> CORE_V4N

<92,93>
CORE_V6N
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/05/16 2018/12/31
PWR_+VCC_CORE
Issued Date Title
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 94 of 101
A B C D
A B C D

+VCCGT
TDC PL2 :30A
PCG02
PRG02
+5VS Peak Current 45A
1 2 1 2

OCP Current
@ PRG01 0_0402_5% 1_0402_5%
1 2 1U_0402_6.3V6K
<91> PWM1_GT
DCR 0.67mohm +/-5%

10K_0402_1%
2

2
1_0402_5%
@ PRG05 0_0402_5%
<91> FCCM_GT 1 2
Load Line 3.1mV/A

PRG03

PRG04
PUG01
PCG01
1U_0402_6.3V6K 1 28
2 PWM CGND 27
+VCCGT

1
1 2 3 ZCD_EN# GL 26
1 1

4 VCIN DSBL# 25
CPU_B+
PCG03
1 2 5 CGND THWn 24
6 BOOT VDRV 23 PLG01
0.22U_0603_16V7K
Use 0603 size 1 2 7 NC PGND 22 0.15UH_MMD-06DZER15MEM1L_36A_20%
PRG06 8 PHASE GL 21 VCC_GT_PH1 1 4
2.2_0603_1% 9 VIN SW 20
10 VIN SW 19 GT_V1P 2 3
11 PGND SW 18

@EMI@ PRG07

4.7_1206_5%
SW SW

1
12 17
13 SW SW 16 PRG08 PRG09
14 SW SW 15 3.65K_0603_1% 100K_0402_1%
SW SW 1 2 1 2

GT_V1N
10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

1000P_0402_50V7K
1U_0402_25V6K
2200P_0402_50V7K

2
SIC632CDT1GE3_POWERPAK31_5X5

EMI@PCG07
0.1U_0402_25V6
1

1
PCG04

PCG05

PCG06

PCG38

EMI@PCG09

EMI@PCG10
EMI@PCG08

680P_0603_50V7K
<91> ISEN1_GT

1
@EMI@ PCG11

2
10_0402_1%
2

2
PRG12

PRG11
20M_0402_5%
2
100K_0402_1%

PRG10
GT_V2N 1 2
@

1
1

<91>
ISUMP_GT

<91>
ISUMN_GT
PCG12
PRG13
+5VS
1 2 1 2
1_0402_5%
@ PRG14 0_0402_5% 1U_0402_6.3V6K
1 2
2 <91> PWM2_GT 2

10K_0402_1%
2

2
1_0402_5%
@ PRG17 0_0402_5%
FCCM_GT 1 2

PRG15

PRG16
PCG13 PUG02
1U_0402_6.3V6K 1 1 28

1
2 PWM CGND 27
1 2 3 ZCD_EN# GL 26
PCG14 4 VCIN DSBL# 25
1 2 5 CGND THWn 24
6 BOOT VDRV 23 PLG02
0.22U_0603_16V7K
Use 0603 size 1 2 7 NC PGND 22 0.15UH_MMD-06DZER15MEM1L_36A_20%
PRG18 8 PHASE GL 21 VCC_GT_PH2 1 4
2.2_0603_1% 9 VIN SW 20
10 VIN SW 19 GT_V2P 2 3
11 PGND SW 18

@EMI@ PRG19

4.7_1206_5%
SW SW

1
12 17
13 SW SW 16 PRG20 PRG21
14 SW SW 15 3.65K_0603_1% 100K_0402_1%
SW SW 1 2 1 2
10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

1000P_0402_50V7K
1U_0402_25V6K
2200P_0402_50V7K

GT_V2N
EMI@PCG17
0.1U_0402_25V6

SIC632CDT1GE3_POWERPAK31_5X5

1 2
1

1
PCG21

PCG15

PCG16

PCG39

EMI@PCG22

EMI@PCG19
EMI@PCG18

ISUMP_GT
<91> ISEN2_GT

680P_0603_50V7K
@EMI@ PCG20
2

2
10_0402_1%
2
PRG23

PRG22
100K_0402_1%
GT_V1N 1 2

1
ISUMN_GT
3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/05/16 2018/12/31
PWR_VCCGT
Issued Date Title
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 95 of 101
A B C D
A B C D

+VCCSA
TDC 10A
Peak Current 11.1A
OCP Current 13.32A
DCR 6.2mohm +/-5%

1 1

Use 0603 size +PWR_SRC


@PJPA01
2 1
+5VS
2 1
JUMP_43X39

PRA01

1000P_0402_50V7K
EMI@ PCA03
2.2_0402_1%

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

1U_0402_25V6K
2200P_0402_50V7K
2 1

EMI@ PCA01
0.1U_0402_25V6
1

1
PCA25

PCA04

PCA05

PCA06

EMI@ PCA07
EMI@ PCA02
@ PRA23
2 1
<58,78,91> IMVP_VR_ON

2
PVCC_VCCSA
1

1
0_0402_5% PCA08 PCA09

VCC_VCCSA
0.1U_0402_16V7K
4.7U_0402_10V6M 4.7U_0402_10V6M
UG_VCCSA

@ PCA26

AON6962_DFN5X6D-8-7
2

2
1
2
PUA01
ISL95870BHRZ-T_QFN20_3X4

18

17

PQA01
PVCC

VCC

1
EN_VCCSA 13 15 UG_VCCSA PLA01
PRA02 EN UGATE PRA03 PCA10 0.47UH_NA__12.2A_20%

D1

G1
+VCCSA
10K_0402_1% 2.2_0603_1% 0.1U_0603_25V7K

+3VS
2 1 VD1_VCCSA 2 16 BST_VCCSA 2 1BST_VCCSA_R 2 1 7 LX_VCCSA 1 4
VID1 BOOT D2/S1
VD0_VCCSA 3 14 LX_VCCSA 2 3
VID0 PHASE
SREF_VCCSA 4 19 LG_VCCSA

@EMI@ PRA04
G2

4.7_1206_5%
S2

S2

S2
SREF LGATE

OCSET_VCCSA_R

OCSET_VCCSA_C
2 2

6
2
PRA05 10 VO_VCCSA
VO PRA07 PRA08
14K_0402_1%
2K_0402_1% 1.82K_0402_1% LG_VCCSA PRA06 PCA11

2
SET0_VCCSA 5 9 OCSET_VCCSA VCCSA_SENSEP 2 1 2 1 12.1K_0402_1% 6800P_0402_25V7K
SET0 OCSET 2 1OCSET_VCCSA2 1
2 1

1
8 FB_VCCSA
PRA09 FB PRA10 PRA11 PCA14

680P_0603_50V7K
@EMI@ PCA12
13K_0402_1% 2K_0402_1% 1.82K_0402_1% 1000P_0402_50V7K

2
VCCSA_SENSEN 2 1 2 1 2 1
1

PCA13 SET1_VCCSA 6
SET1 1 RTN_VCCSA PRA13
VID1 VID0 Output Voltage
0.01U_0402_25V7K
2 1

RTN @ PRA20 12.1K_0402_1%


2

PRA12 10K_0402_1% VO_VCCSA 2 1


PGOOD_VCCSA 2
0 0 1.206V 12K_0402_1% PGOOD
12 1
+3VS
SET2_VCCSA 7 FSEL_VCCSA @PRA14
0 1 1.154V SET2 FSEL
11 2 1
VCC_VCCSA
2 1

0_0402_5%
1 0 1.101V

PGND
PRA15

PAD
1 1 1.049V 270K_0402_1%

1
@PRA16 Pull to VCC : 1MHz
0_0402_5% Pull down 100K to GND : 600KHz

21

20
Floating : 500KHz
1

Pull to GND : 300KHz

2
PRA17 PRA18
100_0402_1% 10_0402_1%
VCCSA_SENSEP
+VCCSA 2 1 2 1

@ PRA19
3
2 1 3

<9> VCCSA_SENSE
0_0402_5%
@ PRA21
2 1
<9> VSSSAIO_SENSE
0_0402_5%
PRA22
2 1 VCCSA_SENSEN

100_0402_1%

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/05/16 2018/12/31
PWR_VCCSA
Issued Date Title
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 96 of 101
A B C D
4
3
2
1
2 1 2 1 2 1

2
1
PCI129 PCI116 PCI96 +
PCI86
+VCC_CORE

22U_0805_10V6M 47U_0805_6.3V6M 47U_0805_6.3V6M 470U_D2_2VM_R4.5M


2 1 2 1 2 1
2
1
+

PCI130 PCI117 PCI97 PCI87


22U_0805_10V6M 47U_0805_6.3V6M 47U_0805_6.3V6M 470U_D2_2VM_R4.5M
2 1 2 1 2 1

A
A

2
1
+

PCI131 PCI118 PCI98 PCI88


22U_0805_10V6M 47U_0805_6.3V6M 47U_0805_6.3V6M 470U_D2_2VM_R4.5M
2 1 2 1 2 1
2
1
+

PCI132 PCI119 PCI99 PCI89


22U_0805_10V6M 47U_0805_6.3V6M 47U_0805_6.3V6M 470U_D2_2VM_R4.5M
2 1 2 1 2 1
2
1
+

PCI133 PCI120 PCI100 PCI90


22U_0805_10V6M 47U_0805_6.3V6M 47U_0805_6.3V6M 470U_D2_2VM_R4.5M
2 1 2 1 2 1
2
1
+

PCI134 PCI121 PCI101 PCI91


22U_0603_6.3V6M 47U_0805_6.3V6M 47U_0805_6.3V6M 470U_D2_2VM_R4.5M
2 1 2 1 2 1
2
1
+

PCI135 PCI122 PCI102 PCI92


22U_0603_6.3V6M 47U_0805_6.3V6M 47U_0805_6.3V6M 470U_D2_2VM_R4.5M
2 1 2 1 2 1
2
1
+

PCI136 PCI123 PCI103 PCI93


22U_0603_6.3V6M 47U_0805_6.3V6M 47U_0805_6.3V6M 470U_D2_2VM_R4.5M
2 1 2 1 2 1
2
1
+

PCI137 PCI124 PCI104 PCI94


22U_0603_6.3V6M 47U_0805_6.3V6M 47U_0805_6.3V6M 470U_D2_2VM_R4.5M
2 1 2 1 2 1
2
1
+

PCI138 PCI125 PCI105 PCI95


22U_0603_6.3V6M 47U_0805_6.3V6M 47U_0805_6.3V6M 470U_D2_2VM_R4.5M
2 1 2 1

PCI126 PCI106
47U_0805_6.3V6M 47U_0805_6.3V6M
2
1
+

2 1 2 1
470U_D2_2VM_R4.5M
PCI127 PCI107 PCI149
47U_0805_6.3V6M 47U_0805_6.3V6M
2
1
+

2 1 2 1
470U_D2_2VM_R4.5M
PCI128 PCI108 PCI150
47U_0805_6.3V6M 47U_0805_6.3V6M
2 1

PCI109
47U_0805_6.3V6M
2 1

PCI111
47U_0805_6.3V6M
2 1

B
B

PCI110
47U_0805_6.3V6M
2 1

PCI112
47U_0805_6.3V6M
2 1
+VCC_CORE

PCI113
47U_0805_6.3V6M
2 1
470uF_D2 x12

22uF_0603 X 5
22uF_0805 X 5

PCI114
47uF_0805 X 33

47U_0805_6.3V6M
2 1

PCI115
47U_0805_6.3V6M
+VCCGT

2 1
2
1
+

PCG27 PCG23
47U_0805_6.3V6M 470U_D2_2VM_R4.5M
2 1
2
1
+

PCG28 PCG24
47U_0805_6.3V6M 470U_D2_2VM_R4.5M
2 1
2
1
+

PCG29 PCG25
47U_0805_6.3V6M 470U_D2_2VM_R4.5M
2 1
2
1
+

Issued Date
PCG30 PCG26
47U_0805_6.3V6M 470U_D2_2VM_R4.5M
2 1

Security Classification
PCG31
47U_0805_6.3V6M
2 1

PCG32

C
C

47U_0805_6.3V6M
2 1

PCG33
47U_0805_6.3V6M

2018/05/16
2 1

PCG34
47U_0805_6.3V6M
2 1
+VCCGT

PCG35
47U_0805_6.3V6M
2 1

PCG36
47U_0805_6.3V6M
2 1
470uF_D2 x4

PCG37
47U_0805_6.3V6M
Compal Secret Data
47uF_0805 X 11

Deciphered Date

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2018/12/31

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+VCCSA

2 1 2 1

PCA19 PCA15
22U_0603_6.3V6M 47U_0805_6.3V6M
2 1 2 1
Size
Title

Date:

PCA20 PCA16
22U_0603_6.3V6M 47U_0805_6.3V6M
2 1 2 1

PCA21 PCA17
22U_0603_6.3V6M 47U_0805_6.3V6M
2 1 2 1
D
D

PCA22
Document Number

PCA18
22U_0603_6.3V6M 47U_0805_6.3V6M
2 1

PCA23
Tuesday, January 08, 2019

22U_0603_6.3V6M
2 1

PCA24
22U_0603_6.3V6M
Sheet
+VCCSA

97
PWR_CPU DECOUPLING
Compal Electronics, Inc.

of
22uF_0603 X 6
47uF_0805 X 4

101
Rev
1.0
4
3
2
1
5 4 3 2 1

+1.8VSP
Input Current: 0.03A TDC 0.13A
1.8V*0.18A/0.85/3=0.127A Peak Current 0.18A
OCP current 3.5A
D D

+3VS
PR1801
2 1 +1.8VSP_EN
<12,37,58,78,88> PCH_PWR_EN

1
0.1U_0402_16V7K
100K_0402_1% @ PR1803

1M_0402_1%
100K_0402_1%

1
PR1802

PC1805
2

2
PU1801

9
@ PJP1801 +1.8VSP_PGOOD 1 8
2 PGOOD GND 7 +1.8VSP_ADJ
+3VALW

GND
1 2 +1.8VSP_VIN 3 EN ADJ 6
1 2 4 VIN VOUT 5 +1.8VSP
VDD NC
JUMP_43X79 RT9059GSP_SO8

1
1

1
22U_0603_6.3V6M

22U_0603_6.3V6M
PR1804

1
PC1804

PC1802

22P_0402_50V8J
24.9K_0402_1%

1
22U_0603_6.3V6M

22U_0603_6.3V6M
PC1801
2

PC1806

PC1803
2
2

2
PR1806
+5VALW 1 2

1
2.2_0402_1% PR1805 Rdown
Vout=0.8V* (1+Rup/Rdown) 20K_0402_1%

1
2.2U_0402_6.3V6K
PC1807

2
2
PJP1802 @

+1.8VSP 1
1 2
2 +1.8VALW
C C

JUMP_43X79

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


2018/05/16 2018/12/31
PWR_+1.8VSP
Issued Date Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-G881P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 98 of 101

5 4 3 2 1
A B C D

Input Current: 2.26A


12V*0.8A/0.85/5V=2.26A

+1.2VP
TDC 0.56A
Must check PL1201 and PD1201 rating Peak Current 0.8A
for your application. OCP current 3A
1 1

Add a switch circuit to turn off the +12V_VIN if need. FSW=1.2MHz


@EMI@PR1202 @EMI@PC1202 TYP MAX
Choke DCR
4.7_1206_5% 680P_0402_50V7K
1 2+12V_SNUB 1 2

PL1201
PD1201
@ PJP1201 3.3UH_MMD-05CZ-3R3M-M7L_5A_20%
+5VS +12VP
1 2 +12V_VIN 1 2 +12V_LX 2 1
1 2 @ PJP1202

22U_0603_6.3V6M
JUMP_43X39 JUMP_43X39
+12VP +12V_FAN
SX34_SMA2

1
PC1203 1 2

22U_0805_25V6M
1 2

1
PC1201
1U_0402_6.3V6K

105K_0402_1%

22U_0805_25V6M
1

1
1 2

PR1203

PC1205

PC1208
@ PC1204

7
100P_0402_50V8J

LX

LX

2
8 2 +12V_FB

2
Vin FB PC1206
0.01U_0402_50V7K
9 10 +12V_SS1 2
FREQ SS

1
PR1204
Vout=1.24V* (1+Rup/Rdown)
PR1201
12K_0402_1%
+5VS 1 2 +12V_ENA 3 1 +12V_COMP
EN COMP

2
40.2K_0402_1%

1
PR1206

1
@ PR1205 56K_0402_1%

GND

GND
PAD
100K_0402_1%
+12V_COMP_1 If the out put is for I/O port, should be add
protection circuit for I/O short protection.

11

2
2 2

2
PU1201

1
RT9297GQW _W DFN10_3X3 PC1207
330P_0402_50V8J
EN high: > VIN pin* 0.7

2
EN Low: < VIN pin* 0.3

FREQ high : Frequency = 1.2MHz


FREQ low : Frequency = 640KHz

3 3

4 4

Security Classification Compal Secret Data


Issued Date 2018/05/16 Deciphered Date 2018/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+12VP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 08, 2019 Sheet 99 of 101
A B C D

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