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    LA-K321P

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    184 views93 pages

    La K321P

    Uploaded by

    Julian Andres Rozo

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 93

    A B C D E

    1 1

    Compal Confidential
    2
    GLMS1 2

    DIS M/B Schematic Document


    Intel Tiger Lake-UP3 Processor with DDR4 Memory Down
    Touch Screen
    3 3

    2021-08-02
    LA-K321P
    REV：2A

    4 4

    Security Classification
    2019/11/27
    Compal Secret Data
    2020/11/27 Title
    Compal Electronics, Inc.
    Issued Date Deciphered Date
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Cover Page
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K321P
    Date: Monday, August 02, 2021 Sheet 1 of 121
    A B C D E
    A B C D E

    DDR4 3200MHz CH-A on board RAM x4


    NVIDIA N18S-G5 PCIe x4 , Gen4
    VRAM(GDDR6) X2 CH-B on board RAM x4
    2GB TDP18W

    1
    USB2.0 x1, 480Mb/s USB Charger USB2.0 x1, 480Mb/s 1

    TI SN1702001
    eDP x4 , HBR 5.4Gb/s USB Conn.
    eDP Panel eDP x2 , HBR 2.7Gb/s with AOU
    USB3.1 x1, Gen1 5Gb/s USB3 Redriver USB3.1 x1, Gen1 5Gb/s
    FHD LCD
    Parade PS8719

    HDMI Conn.
    2.97GT/s HDMI Level Shifter DDI x4 , 1.65GT/s
    USB3.1 x1, Gen1 5Gb/s USB3 Redriver USB3.1 x1, Gen1 5Gb/s
    Parade PS8407A
    Parade PS8719
    USB Conn.
    USB2.0 x1, 480Mb/s
    Intel TGL - UP3 IO Board

    25mm x 45.5mm
    USB2.0 x1, 480Mb/s FingerPrint
    NGFF (Key M) PCIe x4 , Gen3 8Gb/s
    PCIE/SATA SSD SATA , Gen3 6Gb/s 1449pin BGA
    2242/2280 conn. FP Module Board
    2 2

    USB2.0 x1, 480Mb/s


    PCIe x1 , Gen1 2.5Gb/s Int. Camera
    NGFF (Key E)
    USB2.0 x1, 480Mb/s
    WLAN/BT
    2230 conn. CNVi

    CC/VBUS PD IC
    SN2001024YBGR EEPROM PCIe x1 , Gen1 2.5Gb/s Card Reader SDIO SD Card Conn.
    Realtek RTS5232S
    TCSS x4 Lane IO Board
    Type-C Conn. HP
    USB2.0 x1, 480Mb/s Combo Jack
    USB3.1 Gen1 HDA Audio Codec SPK
    CC Type-C CC OVP Realtek ALC3287 Int. Speaker
    TPD6S300A
    3
    SBU Type-C AUX MUX DP_AUX I2C 3

    TS3DS10224 Touch Panel


    SPI ROM SPI
    16MB I2C
    TouchPad
    SPI ROM SPI
    8MB

    eSPI

    Int. KBD KBC


    ENE KB9052QD
    LED
    4 4

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date Title
    Deciphered Date
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Block Diagram
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 2.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K321P
    Date: Thursday, June 03, 2021 Sheet 2 of 121
    A B C D E
    1 2 3 4 5

    Voltage Rails BOM Structure Table USB 2.0 Port Table TCP Port Table
    +5VS
    Item BOM Structure Item BOM Structure
    Port External USB Port Port Lane
    +3VS
    DIS@ GPU select N18S_G5@
    GPU
    +1.8VS
    UMA@ (include chip and strap RES) 1 USB2/3 Port (IO - 1) 0 TYPE C (PD + CC)
    power Channel B Memory Down CHB@ 2 USB2/3 Port (IO - 2) 1
    plane +0.6VS VRAM select VRAM_M2G@
    +1.05V_VCCST
    SDP@ (include chip and strap RES) 3 USB2/3 Port (Type-C) 2
    Memory Down - SDP Package VRAM_S2G@
    +5VALW +1.2V +1.05VS_VCCSTG
    SDP_CHB@ 4 Touch Screen 3
    +12.6VB +3VALW +2.5V +VCCIN
    DDP@ on board RAM select MD_S4G@ 5
    Memory Down - DDP Package (include chip and strap RES) DDI Port Table
    +1.8VALW +VCCIN_AUX
    DDP_CHB@ MD_H4G@ 6 Camera
    A A
    DCI DCI@ MD_M4G@ 7 Fingrt Print
    +1.8VS_DGPU
    Port Lane
    Intel CNVi WLAN CNVi@ MD_S8G@ 8
    +1.8VS_DGPU_AON Keyboard BackLight KBL@ MD_H8G@ 9 0 EDP
    State +VGA_CORE EMI Category EMI@ MD_M8G@ 10 NGFF WLAN+BT 1 HDMI
    +1.0VS_DGPU ESD Category ESD@ MD_S16G@
    +1.2VS_VRAM RF Category RF@ MD_H16G@ USB 3.0 Port Table PCH PCIE Port Table
    RMT test RMT@ MD_M16G@
    Port Port Lane
    HDMI Level Shifter LS@
    1 USB2/3 Port (IO - 1) 1
    Touch Screen TS@
    2 USB2/3 Port (IO - 2) 2
    S0 O O O O GPU GC6 Mode GC6@
    3 3 3 NGFF WLAN+BT
    NOGC6@
    4 4 4 CardReader
    S3 CPU select i3@
    O O O X 5 0
    i5@
    6 1
    S5 S4/AC
    i7@
    O O X X 7 2
    8 3
    S5 S4/ Battery only
    O X X X SATA Port Table 9 3
    Port 10 2
    S5 S4/AC & Battery SSD
    X X X X 0 11 1
    don't exist
    1 SSD 12 0

    B CPU PCIE Port Table B

    Port Lane
    0 0
    EC SM Bus1 address EC SM Bus2 address 1 1
    Device Address Device Address
    GPU
    2 2
    Smart Battery 0001 011x 16h Thermal Sensor (F75305M) 1001_101xb 9Ah
    3 3
    Charger (ISL88739A) 0001 001x 12h Thermal Sensor (F75397M) 1001_100xb 98h

    PCH SM Bus address GPU SM Bus address ON BOARD RAM PCB PN ON BOARD RAM X76
    Device Address Device Address ZZZ

    Micron Hynix Samsung Samsung Hynix Micron


    DDR_JDIMM1 1010 010x A4h Internal thermal sensor 1001 111x 9Eh
    Touch Pad
    ZZZ ZZZ ZZZ
    4GB(R3)
    UD1 MD_M4G@ UD1 MD_H4G@ UD1 MD_S4G@ PCB GLMS1 LA-K321P
    MT40A512M16TB-062E:J H5AN8G6NCJR-XNC K4A8G165WC-BCWE DAZ37H00102
    SA0000CMS10 SA0000CZ320 SA0000CZ520
    UD2 MD_M4G@ UD2 MD_H4G@ UD2 MD_S4G@
    MT40A512M16TB-062E:J H5AN8G6NCJR-XNC K4A8G165WC-BCWE X76 DRAM 4G SAM SINGELX76 DRAM 4G HYN SINGEL X76 DRAM 4G MIC SINGEL
    SMBUS Control Table
    SA0000CMS10 SA0000CZ320 SA0000CZ520 X7684838LA1 X7684838LA2 X7684838LA3
    UD3 MD_M4G@ UD3 MD_H4G@ UD3 MD_S4G@ X76_S4G_1CH_3200@ X76_H4G_1CH_3200@ X76_M4G_1CH_3200@
    MT40A512M16TB-062E:J
    SA0000CMS10
    H5AN8G6NCJR-XNC
    SA0000CZ320
    K4A8G165WC-BCWE
    SA0000CZ520
    TGL-UP3 CPU ZZZ ZZZ ZZZ
    UD4 MD_M4G@ UD4 MD_H4G@ UD4 MD_S4G@
    Thermal MT40A512M16TB-062E:J H5AN8G6NCJR-XNC K4A8G165WC-BCWE
    SOURCE SOC BATT CHARGER KB9052 PD IC Sensor DGPU SA0000CMS10 SA0000CZ320 SA0000CZ520
    UC1 UC1 UC1

    EC_SMB_CK1 8GB(R3)
    V V
    X76 DRAM 8G SAM DUAL X76 DRAM 8G HYN DUAL X76 DRAM 8G MIC DUAL
    C
    EC_SMB_DA1
    KB9052
    +3VL
    X +3VALW +19V_VIN X X X X UD1 MD_M8G@
    MT40A512M16TB-062E:J
    SA0000CMS10
    UD1 MD_H8G@
    H5AN8G6NCJR-XNC
    SA0000CZ320
    UD1 MD_S8G@
    K4A8G165WC-BCWE
    SA0000CZ520
    X7684838LA4
    X76_S8G_2CH_3200@
    X7684838LA5
    X76_H8G_2CH_3200@
    X7684838LA6
    X76_M8G_2CH_3200@
    C

    i3-1115G4 i5-1135G7 I7-1165G7


    EC_SMB_CK2
    V V V
    UD2 MD_M8G@ UD2 MD_H8G@ UD2 MD_S8G@ ZZZ ZZZ ZZZ

    X X X X
    SA0000DRS50 SA0000DRR50 SA0000DRG60
    KB9052 MT40A512M16TB-062E:J H5AN8G6NCJR-XNC K4A8G165WC-BCWE
    i3@ i5@ i7@
    EC_SMB_DA2 +3VL +3VS +3VS +3VS SA0000CMS10
    UD3 MD_M8G@
    SA0000CZ320
    UD3 MD_H8G@
    SA0000CZ520
    UD3 MD_S8G@
    EC_SMB_CK3 KB9052
    MT40A512M16TB-062E:J H5AN8G6NCJR-XNC K4A8G165WC-BCWE

    EC_SMB_DA3 +3VL
    X X X X V+3VL X X SA0000CMS10
    UD4 MD_M8G@
    MT40A512M16TB-062E:J
    SA0000CZ320
    UD4 MD_H8G@
    H5AN8G6NCJR-XNC
    SA0000CZ520
    UD4 MD_S8G@
    K4A8G165WC-BCWE
    X76 DRAM 16G SAM DUAL X76 DRAM 16G HYN DUAL
    X7684838LA7 X7684838LA8
    X76 DRAM 16G MIC DUAL
    X7684838LA9
    SOC_SMBCLK
    X X X X X X
    SA0000CMS10 SA0000CZ320 SA0000CZ520 X76_S16G_2CH_3200@ X76_H16G_2CH_3200@ X76_M16G_2CH_3200@

    SOC_SMBDATA
    SOC
    +3VS
    X UD5 MD_M8G@
    MT40A512M16TB-062E:J
    SA0000CMS10
    UD5 MD_H8G@
    H5AN8G6NCJR-XNC
    SA0000CZ320
    UD5 MD_S8G@
    K4A8G165WC-BCWE
    SA0000CZ520
    GPU
    SOC_SML0CLK UD6 MD_M8G@ UD6 MD_H8G@ UD6 MD_S8G@

    SOC_SML0DATA
    SOC
    +3VS X X X X X X X MT40A512M16TB-062E:J
    SA0000CMS10
    UD7 MD_M8G@
    H5AN8G6NCJR-XNC
    SA0000CZ320
    UD7 MD_H8G@
    K4A8G165WC-BCWE
    SA0000CZ520
    UD7 MD_S8G@ UV1
    VRAM X76
    MT40A512M16TB-062E:J H5AN8G6NCJR-XNC K4A8G165WC-BCWE SA0000DGW50
    SA0000CMS10 SA0000CZ320 SA0000CZ520 N18S-G5-A1
    UD8 MD_M8G@ UD8 MD_H8G@ UD8 MD_S8G@ N18S_G5@
    MT40A512M16TB-062E:J H5AN8G6NCJR-XNC K4A8G165WC-BCWE
    ZZZ ZZZ
    SA0000CMS10 SA0000CZ320 SA0000CZ520

    16GB(R3)
    UD1 MD_M16G@ UD1 MD_H16G@ UD1 MD_S16G@ UD1 MD_H16G2@
    MT40A1G16KD-062E:E
    SA0000D3U10
    H5ANAG6NCMR-XNC
    SA0000CZ120
    K4AAG165WA-BCWE
    SA0000CZ220
    H5ANAG6NCJR-XNC
    SA0000DYB10
    VRAM X76 VRAM SAM 2G X76 VRAM MIC 2G
    X7684838LAA X7684838LAB
    SIGNAL UD2 MD_M16G@ UD2 MD_H16G@ UD2 MD_S16G@ UD2 MD_H16G2@
    X76_S2G@ X76_M2G@
    STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock MT40A1G16KD-062E:E H5ANAG6NCMR-XNC K4AAG165WA-BCWE H5ANAG6NCJR-XNC
    SA0000D3U10
    UD3 MD_M16G@
    SA0000CZ120
    UD3 MD_H16G@
    SA0000CZ220
    UD3 MD_S16G@
    SA0000DYB10
    UD3 MD_H16G2@
    Samsung Micron Hynix
    UG11 SA0000C6270
    Full ON HIGH HIGH HIGH HIGH ON ON ON ON MT40A1G16KD-062E:E H5ANAG6NCMR-XNC K4AAG165WA-BCWE H5ANAG6NCJR-XNC UG11 SA0000BND70 UG11 SA0000DUW30
    VRAM_S2G@
    SA0000D3U10 SA0000CZ120 SA0000CZ220 SA0000DYB10 VRAM_M2G@ VRAM_H2G@
    K4Z80325BC-HC14
    UD4 MD_M16G@ UD4 MD_H16G@ UD4 MD_S16G@ UD4 MD_H16G2@ MT61K256M32JE-14:A H56C8H24AIR-S2C
    S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW MT40A1G16KD-062E:E H5ANAG6NCMR-XNC K4AAG165WA-BCWE H5ANAG6NCJR-XNC
    UG12 SA0000C6270
    SA0000D3U10 SA0000CZ120 SA0000CZ220 SA0000DYB10 UG12 SA0000BND70 UG12 SA0000DUW30
    UD5 MD_M16G@
    MT40A1G16KD-062E:E
    UD5 MD_H16G@
    H5ANAG6NCMR-XNC
    UD5 MD_S16G@
    K4AAG165WA-BCWE
    UD5 MD_H16G2@
    H5ANAG6NCJR-XNC
    VRAM_S2G@
    K4Z80325BC-HC14
    VRAM_M2G@
    MT61K256M32JE-14:A
    VRAM_H2G@
    H56C8H24AIR-S2C
    X4E
    S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
    SA0000D3U10 SA0000CZ120 SA0000CZ220 SA0000DYB10
    ZZZ ZZZ
    D UD6 MD_M16G@ UD6 MD_H16G@ UD6 MD_S16G@ UD6 MD_H16G2@ D
    S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF MT40A1G16KD-062E:E H5ANAG6NCMR-XNC K4AAG165WA-BCWE H5ANAG6NCJR-XNC
    SA0000D3U10 SA0000CZ120 SA0000CZ220 SA0000DYB10
    UD7 MD_M16G@ UD7 MD_H16G@ UD7 MD_S16G@ UD7 MD_H16G2@
    S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF MT40A1G16KD-062E:E H5ANAG6NCMR-XNC K4AAG165WA-BCWE H5ANAG6NCJR-XNC
    SA0000D3U10 SA0000CZ120 SA0000CZ220 SA0000DYB10
    UD8 MD_M16G@ UD8 MD_H16G@ UD8 MD_S16G@ UD8 MD_H16G2@ SMT EMC DIS SMT EMC UMA
    X4EANN38L01 X4EANN38L02
    MT40A1G16KD-062E:E H5ANAG6NCMR-XNC K4AAG165WA-BCWE H5ANAG6NCJR-XNC
    X4E_DIS@ X4E_UMA@
    SA0000D3U10 SA0000CZ120 SA0000CZ220 SA0000DYB10

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date Title
    Deciphered Date
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Notes List
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 2.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K321P
    Date: Thursday, June 03, 2021 Sheet 3 of 121
    1 2 3 4 5
    5 4 3 2 1

    [FQA01-Power Map_TGL-UP3_DDR4_Volume_S0ix]

    D D

    C C

    B B

    www.teknisi-indonesia.com

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2019/11/27 Deciphered Date 2020/11/27 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Power MAP
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K321P
    Date: Thursday, June 03, 2021 Sheet 4 of 121
    5 4 3 2 1
    5 4 3 2 1

    [ FQA01-PWR Sequence_TGL-UP3_DDR4_Volume_S0iX ]

    G3->S0 S0-> S0iX S0iX ->S0 S0->S5


    +3VL_RTC
    +3VL_RTC
    tPCH01_Min : 9 ms
    SOC_RTCRST#
    SOC_RTCRST#
    tPCH04_Min : 9 ms
    +3VALW_DSW
    +3VALW_DSW/+3VALW tPCH02_Min : 10 ms
    D D
    PCH_DPWROK
    PCH_DPWROK
    tPCH05_Min : 1 us
    PM_BATLOW#
    PM_BATLOW#
    tPCH32_Min : 95 ms
    SLP_SUS#
    SLP_SUS#

    +5VALW
    +5VALW
    EXT_PWR_GATE#
    EXT_PWR_GATE#
    +3V_PRIM
    +3V_PRIM
    tPCH06_Min : 200 us
    +1.8V_PRIM
    +1.8V_PRIM
    +VCCIN_AUX
    +VCCIN_AUX
    +1.05VO_OUT_PCH
    +1.05VO_OUT_PCH
    +1.05VO_VNNBYPASS
    +1.05VO_VNNBYPASS
    +1.05VO_EXTBYPASS
    +1.05VO_EXTBYPASS
    tPCH03_Min : 10 ms
    EC_RSMRST#
    EC_RSMRST# tPCH07_Min : 0 ms
    tPCH18_Min : 95 ms
    ESPI_RST# ESPI_RST#

    SUSCLK
    tPLT02_Max : 90 ms
    tPCH31_Min : 105 ms AC_PRESENT_R
    AC_PRESENT_R
    VCCST_Can_be_On_until_VCCINAUX_goes_LOW
    +1.05V_VCCST +1.05V_VCCST_Must_be_ON_anytime_VCCIN_AUX_is_ON +1.05V_VCCST
    C C

    +1.05VO_VCCPLL +1.05VO_VCCPLL

    PBTN_OUT#
    PBTN_OUT#

    PM_SLP_S5#
    PM_SLP_S5#

    PM_SLP_S4#
    PM_SLP_S4#

    PM_SLP_S3# PM_SLP_S3#

    PM_SLP_S0#
    PM_SLP_S0#

    CPU_C10_GATE#
    CPU_C10_GATE#

    VCCST_OVERRIDE High_in_Sx_if_TCSS_wake_enabled
    VCCST_OVERRIDE
    Min : 0 ms
    +2.5V
    +2.5V
    +1.2V_VDDQ
    tCPU01_Min : 1 ms +1.2V_VDDQ
    +1.2V_VCCPLL_OC
    +1.2V_VCCPLL_OC

    B +1.05VS_VCCSTG B
    +1.05VS_VCCSTG
    VCCST and VCCSTG may remain powered during
    Sx power states for Debug support and platform VR optimization.
    VCCSTPWRGOOD_TGSS
    VCCSTPWRGOOD_TGSS

    EC_VCCST_PG EC_VCCST_PG
    tCPU00_Min : 2 ms

    DDR_PG_CTRL DDR_PG_CTRL

    +0.6VS_VTT +0.6VS_VTT

    VR_ON VR_ON

    +VCCIN +VCCIN

    VR_PWRGD VR_PWRGD

    PCH_PWROK tCPU16_Min : 0 ns PCH_PWROK

    +1.05V_VCCIO_OUT +1.05V_VCCIO_OUT

    PCH_CLK_OUTPUTS Stable PCH_CLK_OUTPUTS

    H_PROCPWRGD H_PROCPWRGD
    A A
    SYS_PWROK SYS_PWROK

    SOC_PLTRST#
    SOC_PLTRST#

    H_THERMTRIP# HONORED HONORED Will_Track_VCCST_Rail


    H_THERMTRIP#

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2019/11/27 Deciphered Date 2020/11/27 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Power Sequence
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
    2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K321P
    Date: Thursday, June 03, 2021 Sheet 5 of 121
    5 4 3 2 1
    A B C D E

    UC1A
    AC2 REV 1.6 AY2
    1 DDIA_TXP_3 TCP0_TXRX_P1 TCP0_TRX_DTX_P2 [42] 1
    AC1 AY1
    DDIA_TXN_3 TCP0_TXRX_N1 TCP0_TRX_DTX_N2 [42]
    AD2 BB1
    DDIA_TXP_2 TCP0_TXRX_P0 TCP0_TRX_DTX_P1 [42]
    AD1 BB2
    DDIA_TXN_2 TCP0_TXRX_N0 TCP0_TRX_DTX_N1 [42]
    <eDP> [38] EDP_TXP1
    AF1
    DDIA_TXP_1 TCP0_TX_P1
    AM5
    TCP0_TTX_DRX_P2 [42]
    AF2 AM7 <TYPE-C> (USB3.1+ DP)
    [38] EDP_TXN1 DDIA_TXN_1 TCP0_TX_N1 TCP0_TTX_DRX_N2 [42]
    AG2 AT7
    [38] EDP_TXP0 DDIA_TXP_0 TCP0_TX_P0 TCP0_TTX_DRX_P1 [42]
    AG1 AT5
    [38] EDP_TXN0 DDIA_TXN_0 TCP0_TX_N0 TCP0_TTX_DRX_N1 [42]
    AP7
    TCP0_AUX_P TCP0_AUX_P [42]
    [38] EDP_AUXP AJ2 AP5
    DDIA_AUX_P TCP0_AUX_N TCP0_AUX_N [42]
    [38] EDP_AUXN AJ1
    DDIA_AUX_N AT2
    T2404TP@ 1 SOC_GPP_E22 DN4 TCP1_TXRX_P1 AT1
    T2405TP@ 1 SOC_GPP_E23 DT6 GPP_E22/DDPA_CTRLCLK/DNX_FORCE_RELOAD TCP1_TXRX_N1 AU1
    GPP_E23/DDPA_CTRLDATA TCP1_TXRX_P0 AU2
    DR5 TCP1_TXRX_N0 AD5
    From eDP [38] EDP_HPD GPP_E14/DDSP_HPDA/DISP_MISCA TCP1_TX_P1 AD7
    T12 TCP1_TX_N1 AH7
    [40] CPU_DP2_P3 DDIB_TXP_3 TCP1_TX_P0
    T11 AH5
    [40] CPU_DP2_N3 DDIB_TXN_3 TCP1_TX_N0
    Y11 AF7
    [40] CPU_DP2_P2 DDIB_TXP_2 TCP1_AUX_P
    Y9 AF5
    [40] CPU_DP2_N2 DDIB_TXN_2 TCP1_AUX_N
    <HDMI> T9
    [40] CPU_DP2_P1 DDIB_TXP_1
    P9 BF1
    [40] CPU_DP2_N1 DDIB_TXN_1 TCP2_TXRX_P1
    V11 BF2
    [40] CPU_DP2_P0 DDIB_TXP_0 TCP2_TXRX_N1
    V9 BE2
    [40] CPU_DP2_N0 DDIB_TXN_0 TCP2_TXRX_P0 BE1
    AB9 TCP2_TXRX_N0 BD7
    AD9 DDIB_AUX_P TCP2_TX_P1 BD5
    DDIB_AUX_N TCP2_TX_N1 AY5
    DM29 TCP2_TX_P0 AY7
    2 [40] CPU_DP2_CTRL_CLK GPP_H16/DDPB_CTRLCLK/PCIE_LNK_DOWN TCP2_TX_N0 2
    HDMI DDC (Port 2) DK27 BB5
    [40] CPU_DP2_CTRL_DATA GPP_H17/DDPB_CTRLDATA TCP2_AUX_P BB7
    DG43 TCP2_AUX_N
    From HDMI [40] CPU_DP2_HPD GPP_A18/DDSP_HPDB/DISP_MISCB/I2S4_RXD BK1
    DG47 TCP3_TXRX_P1 BK2
    DJ47 GPP_A21/DDPC_CTRLCLK/I2S5_TXD TCP3_TXRX_N1 BJ2
    GPP_A22/DDPC_CTRLDATA/I2S5_RXD TCP3_TXRX_P0 BJ1
    DU8 TCP3_TXRX_N0 BM7
    DV8 GPP_E18/DDP1_CTRLCLK/TBT_LSX0_TXD TCP3_TX_P1 BM5
    GPP_E19/DDP1_CTRLDATA/TBT_LSX0_RXD TCP3_TX_N1 BH5
    DF6 TCP3_TX_P0 BH7
    DD6 GPP_E20/DDP2_CTRLCLK/TBT_LSX1_TXD TCP3_TX_N0 BK5
    GPP_E21/DDP2_CTRLDATA/TBT_LSX1_RXD TCP3_AUX_P BK7
    DN23 TCP3_AUX_N
    DM23 GPP_D9/ISH_SPI_CS#/DDP3_CTRLCLK/TBT_LSX2_TXD/GSPI2_CS0# AN2 TC_RCOMP_P RC618 1 2 150_0201_1%
    GPP_D10/ISH_SPI_CLK/DDP3_CTRLDATA/TBT_LSX2_RXD/GSPI2_CLK TC_RCOMP_P AN1 TC_RCOMP_N
    DK23 TC_RCOMP_N
    DN21 GPP_D11/ISH_SPI_MISO/DDP4_CTRLCLK/TBT_LSX3_TXD/GSPI2_MISO M8 DSI_DE_TE_2 RC617 1 2 100K_0201_5%
    GPP_D12/ISH_SPI_MOSI/DDP4_CTRLDATA/TBT_LSX3_RXD/GSPI2_MOSI DSI_DE_TE_2
    DF43 AB1 DDI_RCOMP RC616 1 2 150_0201_1%
    DF45 GPP_A17/DISP_MISCC/I2S4_TXD DDI_RCOMP
    From PD [42] TCP0_PD_HPD GPP_A19/DDSP_HPD1/DISP_MISC1/I2S5_SCLK
    1 SOC_GPP_A20 DF47 CE4 DISP_UTILS 1
    T4 TP@ GPP_A20/DDSP_HPD2/DISP_MISC2/I2S5_SFRM DISP_UTILS/DSI_DE_TE_1 TP@ T5
    USB_OC1# DH52
    [71] USB_OC1# GPP_A14/USB_OC1#/DDSP_HPD3/I2S3_RXD/DISP_MISC3/DMIC_CLK_B1
    USB_OC2# DK45
    GPP_A15/USB_OC2#/DDSP_HPD4/DISP_MISC4/I2S4_SCLK
    PCH_ENVDD DM8
    [38] PCH_ENVDD EDP_VDDEN
    EDP_VDDEN: ENBKL DN8
    [58] ENBKL EDP_BKLTEN
    3 100K PD on load swith side INVPW M DG10 3
    [38] INVPW M EDP_BKLTCTL

    TGL-U_BGA1449
    @

    +3V_PRIM

    RC164 1 2 10K_0201_5% USB_OC1#


    RC165 1 2 10K_0201_5% USB_OC2#
    RC422 1 2 100K_0201_5% ENBKL

    4 4

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2019/11/27 Deciphered Date 2020/11/27 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    TGL-UP3(1/14)DDI,EDP
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 2.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K321P
    Date: Thursday, June 03, 2021 Sheet 6 of 121
    A B C D E
    A B C D E

    +1.05VS_VCCSTG_OUT_LGC

    1
    RC6 +1.05VS_VCCSTG
    1K_0201_5% UC1U
    REV 1.6
    CATERR# M7 K4 SOC_XDP_TRST#

    2
    BK9 CATERR# PROC_TRST# B9 SOC_XDP_TMS

    1
    [58] H_PECI PECI PROC_TMS
    1 H_PROCHOT# 1 2 H_PROCHOT#_R E2 D12 SOC_XDP_TDO 1
    [58] H_PROCHOT# PROCHOT# PROC_TDO RC581
    RC7 499_0201_1% H_THERMTRIP# M5 A12 SOC_XDP_TDI
    THRMTRIP# PROC_TDI SOC_XDP_TCK0 1K_0201_5%
    B6
    PROC_POPIRCOMP CT39 PROC_TCK
    PCH_OPIRCOMP CB9 PROC_POPIRCOMP D8 SOC_XDP_TCK0

    2
    +3V_PRIM PCH_OPIRCOMP PCH_JTAGX
    T6 TP@ 1 SOC_TP_1 CW12 A9 SOC_XDP_TMS
    TP_1 PCH_TMS SOC_EAR
    T7 TP@ 1 SOC_TP_2 CM39 E12 SOC_XDP_TDO
    TP_2 PCH_TDO B12 SOC_XDP_TDI

    1
    XDP_ITP_PMODE DF4 PCH_TDI A7 PCH_JTAG_TCK1

    1
    RC371 DBG_PMODE PCH_TCK SOC_XDP_TRST#
    H4
    100K_0201_5% SOC_GPP_B4 PCH_TRST# RC582
    T2413 TP@ 1 DB42
    GPP_B4/CPU_GP3 XDP_PREQ# 1K_0201_5%
    DB41 C11
    SOC_GPP_E7 GPP_B3/CPU_GP2 PROC_PREQ# XDP_PRDY# @
    DF8 D11

    2
    GPP_E7/CPU_GP1 PROC_PRDY# TP@ T498
    DU5

    2
    DC10 1 2 H_PROCHOT# GPP_E3/CPU_GP0
    [17] VCCIN_AUX_CORE_ALERT#_R G1 SOC_EAR
    RB751V-40_SOD323-2 SOC_GPP_H2 EAR_N/EAR_N_TEST_NCTF
    DF31
    SCS00000Z00 SOC_GPP_H1 GPP_H2 SOC_GPP_F7
    DV32 DT15
    [42] VR_ALERT# RC562 1 @ 2 0_0201_5% SOC_GPP_H0 GPP_H1 GPP_F7 SOC_GPP_F9
    DW32 DR15
    GPP_H0 GPP_F9 DT14 SOC_GPP_F10
    1SOC_GPP_H19 DJ27 GPP_F10
    T2409 TP@ GPP_H19/TIME_SYNC0
    +3V_PRIM
    TGL-U_BGA1449
    @

    1
    +1.05V_VCCST RC38
    2 4.7K_0201_5% 2
    @
    RC11 1 2 1K_0201_5% CATERR#

    2
    RC12 1 2 1K_0201_5% H_THERMTRIP#
    SOC_GPP_F7
    CC2 2 1 0.1U_0201_10V6K

    1
    @ESD@ RC40
    20K_0201_5%
    @
    +3VS

    2
    RC23 1 @ 2 10K_0201_5% SOC_GPP_E7

    +1.05VO_OUT_FET
    RC45 2 1 20K_0201_5% SOC_GPP_F10
    RC625 2 @ 1 75K_0201_5% SOC_GPP_F9
    @ESD@ RC18 1 @ 2 1K_0201_5% XDP_ITP_PMODE
    CC751 1 2 0.1U_0201_10V6K H_PECI
    RC366 1 2 49.9_0201_1% PROC_POPIRCOMP RC19 1 @ 2 1K_0201_5%
    RC365 1 2 49.9_0201_1% PCH_OPIRCOMP

    XDP_ITP_PMODE
    3 DFX TEST MODE 3
    INTERNAL PD 20K
    SOC_GPP_H2 HIGH: DFX TEST MODE DISABLED(DEFAULT)
    BOOT STRAP3 - BIT3 LOW: DFX TES TMODE ENABLED
    This is bit 1 of a total of 4-bit encoded pin straps for
    boot configuration.
    Refer to Boot Strap 0 (on GPP_C5) for the encoding.
    +3V_PRIM INTERNAL PD 20K < PU/PD for DCI Debug > +1.05VS_VCCSTG_OUT_LGC

    SOC_GPP_H1
    BOOT STRAP1 - BIT2 SOC_XDP_TMS RC13 1 @ 2 51_0201_5%
    RC24 1 @ 2 4.7K_0201_5% SOC_GPP_H2 This is bit 1 of a total of 4-bit encoded pin straps for
    RC640 1 @ 2 4.7K_0201_5% SOC_GPP_H1 boot configuration. SOC_XDP_TDI RC14 1 @ 2 51_0201_5%
    RC26 1 @ 2 4.7K_0201_5% SOC_GPP_H0 Refer to Boot Strap 0 (on GPP_C5) for the encoding.
    INTERNAL PD 20K SOC_XDP_TDO RC15 1 DCI@ 2 51_0201_5%

    XDP_PREQ# RC17 1 @ 2 51_0201_5%


    SOC_GPP_H0
    BOOT STRAP1 - BIT1
    This is bit 1 of a total of 4-bit encoded pin straps for SOC_XDP_TCK0 RC20 1 DCI@ 2 51_0201_5%
    boot configuration.
    Refer to Boot Strap 0 (on GPP_C5) for the encoding. PCH_JTAG_TCK1 RC22 1 @ 2 51_0201_5%
    INTERNAL PD 20K
    SOC_XDP_TRST# RC21 1 @ 2 51_0201_5%

    4 4

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2019/11/27 Deciphered Date 2020/11/27 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    TGL-UP3(2/14)DDI,MSIC,XDP
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 2.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K321P
    Date: Thursday, June 03, 2021 Sheet 7 of 121
    A B C D E
    5 4 3 2 1

    Follow Intel DDR4 NIL

    UC1B
    REV 1.6
    UC1C
    REV 1.6
    LP4-LP5(NIL)/DDR4 (NIL)/DDR4
    [23] DDR_A_D[0..7] DDR_A_D7 (IL) DDR4/LP4/LP5/LP5 CMD Flip LP4-LP5(NIL)/DDR4 (NIL)/DDR4 (IL)
    D CP53 BT42 [25] DDR_B_D[0..7] DDR_B_D7 DDR4/LP4/LP5/LP5 CMD Flip D
    DDR_A_D6 DDR0_DQ0_7/DDR0_DQ0_7/DDR0_DQ0_7 DDR0_CLK_P1/DDR3_CLK_P/DDR3_CLK_P/DDR3_CLK_P AL53 R41
    CP52 BT41 DDR_B_D6 DDR4_DQ0_7/DDR1_DQ0_7/DDR0_DQ4_7 DDR1_CLK_P1/DDR7_CLK_P/DDR7_CLK_P/DDR7_CLK_P
    DDR_A_D5 DDR0_CLK_N1 / DDR3_CLK_N / DDR3_CLK_N / DDR3_CLK_N
    DDR0_DQ0_6/DDR0_DQ0_6/DDR0_DQ0_6 AL52 R42
    CP50 BP52 DDR_B_D5 DDR1_CLK_N1 / DDR7_CLK_N / DDR7_CLK_N / DDR7_CLK_N
    DDR4_DQ0_6/DDR1_DQ0_6/DDR0_DQ4_6
    DDR_A_D4 DDR0_DQ0_5/DDR0_DQ0_5/DDR0_DQ0_5 NC/DDR2_CLK_P/DDR2_CLK_P/DDR2_CLK_P AL50 M52
    CP49 BP53 DDR_B_D4 DDR4_DQ0_5/DDR1_DQ0_5/DDR0_DQ4_5 NC/DDR6_CLK_P/DDR6_CLK_P/DDR6_CLK_P
    DDR_A_D3 DDR0_DQ0_4/DDR0_DQ0_4/DDR0_DQ0_4 NC / DDR2_CLK_N / DDR2_CLK_N / DDR2_CLK_N AL49 M53
    CU53 CD42 DDR_B_D3 DDR4_DQ0_4/DDR1_DQ0_4/DDR0_DQ4_4 NC / DDR6_CLK_N / DDR6_CLK_N / DDR6_CLK_N
    DDR_A_D2 DDR0_DQ0_3/DDR0_DQ0_3/DDR0_DQ0_3 NC/DDR1_CLK_P/DDR1_CLK_P/DDR1_CLK_P AP53 AC42
    CU52 CD41 DDR_B_D2 DDR4_DQ0_3/DDR1_DQ0_3/DDR0_DQ4_3 NC/DDR5_CLK_P/DDR5_CLK_P/DDR5_CLK_P
    DDR_A_D1 DDR0_DQ0_2/DDR0_DQ0_2/DDR0_DQ0_2 NC / DDR1_CLK_N / DDR1_CLK_N / DDR1_CLK_N AP52 AC41
    CU50 CC52 DDR_B_D1 DDR4_DQ0_2/DDR1_DQ0_2/DDR0_DQ4_2 NC / DDR5_CLK_N / DDR5_CLK_N / DDR5_CLK_N
    DDR_A_D0 DDR0_DQ0_1/DDR0_DQ0_1/DDR0_DQ0_1 DDR0_CLK_P0/DDR0_CLK_P/DDR0_CLK_P/DDR0_CLK_P DDR_A_CLK0 [23] AP50 Y52
    CU49 CC53 DDR_B_D0 DDR4_DQ0_1/DDR1_DQ0_1/DDR0_DQ4_1 DDR1_CLK_P0/DDR4_CLK_P/DDR4_CLKP/DDR4_CLK_P DDR_B_CLK0 [25]
    [23] DDR_A_D[8..15] DDR_A_D15 DDR0_CLK_N0 / DDR0_CLK_N / DDR0_CLK_N / DDR0_CLK_N
    DDR0_DQ0_0/DDR0_DQ0_0/DDR0_DQ0_0 DDR_A_CLK#0 [23] AP49 Y53
    CH53 [25] DDR_B_D[8..15] DDR_B_D15 DDR1_CLK_N0 / DDR4_CLK_N / DDR4_CLK_N / DDR4_CLK_N
    DDR4_DQ0_0/DDR1_DQ0_0/DDR0_DQ4_0 DDR_B_CLK#0 [25]
    DDR_A_D14 DDR0_DQ1_7/DDR0_DQ1_7/DDR0_DQ1_7 DDR4/LP4/LP5/LP5 CMD AF53
    CH52 BT45 DDR_B_D14 DDR4_DQ1_7/DDR1_DQ1_7/DDR0_DQ5_7 DDR4/LP4/LP5/LP5 CMD Flip
    DDR_A_D13 DDR0_DQ1_6/DDR0_DQ1_6/DDR0_DQ1_6 Flip NC/DDR3_CKE0/DDR3_WCK_P/DDR3_WCK_P AF52 R47
    CH50 BT47 DDR_B_D13 DDR4_DQ1_6/DDR1_DQ1_6/DDR0_DQ5_6 NC/DDR7_CKE0/DDR7_WCK_P/DDR7_WCK_P
    DDR_A_D12 DDR0_DQ1_5/DDR0_DQ1_5/DDR0_DQ1_5 NC / DDR3_CKE1 / DDR3_WCK_N / DDR3_WCK_N AF50 R45
    CH49 BN51 DDR_B_D12 DDR4_DQ1_5/DDR1_DQ1_5/DDR0_DQ5_5 NC / DDR7_CKE1 / DDR7_WCK_N / DDR7_WCK_N
    DDR_A_D11 DDR0_DQ1_4/DDR0_DQ1_4/DDR0_DQ1_4 NC/DDR2_CKE0/DDR2_WCK_P/DDR2_WCK_P AF49 K51
    CL53 BN53 DDR_B_D11 DDR4_DQ1_4/DDR1_DQ1_4/DDR0_DQ5_4 NC/DDR6_CKE0/DDR6_WCK_P/DDR6_WCK_P
    DDR_A_D10 DDR0_DQ1_3/DDR0_DQ1_3/DDR0_DQ1_3 NC / DDR2_CKE1 / DDR2_WCK_N / DDR2_WCK_N AH53 K53
    CL52 CD45 DDR_B_D10 DDR4_DQ1_3/DDR1_DQ1_3/DDR0_DQ5_3 NC / DDR6_CKE1 / DDR6_WCK_N / DDR6_WCK_N
    DDR_A_D9 DDR0_DQ1_2/DDR0_DQ1_2/DDR0_DQ1_2 NC/DDR1_CKE0/DDR1_WCK_P/DDR1_WCK_P AH52 AC47
    CL50 CD47 DDR_B_D9 DDR4_DQ1_2/DDR1_DQ1_2/DDR0_DQ5_2 NC/DDR5_CKE0/DDR5_WCK_P/DDR5_WCK_P
    DDR_A_D8 DDR0_DQ1_1/DDR0_DQ1_1/DDR0_DQ1_1 NC / DDR1_CKE1 / DDR1_WCK_N / DDR1_WCK_N AH50 AC45
    CL49 CA51 DDR_B_D8 DDR4_DQ1_1/DDR1_DQ1_1/DDR0_DQ5_1 NC / DDR5_CKE1 / DDR5_WCK_N / DDR5_WCK_N
    [23] DDR_A_D[16..23] DDR_A_D23 DDR0_DQ1_0/DDR0_DQ1_0/DDR0_DQ1_0 NC/DDR0_CKE0/DDR0_WCK_P/DDR0_WCK_P AH49 W51
    CT47 CA53 [25] DDR_B_D[16..23] DDR_B_D23 DDR4_DQ1_0/DDR1_DQ1_0/DDR0_DQ5_0 NC/DDR4_CKE0/DDR4_WCK_P/DDR4_WCK_P
    DDR_A_D22 DDR1_DQ0_7/DDR0_DQ2_7/DDR1_DQ0_7 NC / DDR0_CKE1 / DDR0_WCK_N / DDR0_WCK_N AR41 W53
    CV47 DDR_B_D22 DDR5_DQ0_7/DDR1_DQ2_7/DDR1_DQ4_7 NC / DDR4_CKE1 / DDR4_WCK_N / DDR4_WCK_N
    DDR_A_D21 DDR1_DQ0_6/DDR0_DQ2_6/DDR1_DQ0_6 DDR4/LP4/LP5/LP5 CMD Flip AV42
    CT45 BU52 DDR_B_D21 DDR5_DQ0_6/DDR1_DQ2_6/DDR1_DQ4_6 DDR4/LP4/LP5/LP5 CMD Flip
    DDR_A_D20 DDR1_DQ0_5/DDR0_DQ2_5/DDR1_DQ0_5 DDR0_CKE1/DDR2_CA4/DDR2_CA5/DDR2_CA1 AR42 P52
    CV45 BL50 DDR_B_D20 DDR5_DQ0_5/DDR1_DQ2_5/DDR1_DQ4_5 DDR1_CKE1/DDR6_CA4/DDR6_CA5/DDR6_CA1
    DDR_A_D19 DDR1_DQ0_4/DDR0_DQ2_4/DDR1_DQ0_4 DDR0_CKE0/DDR2_CA5/DDR2_CA6/DDR2_CA0 DDR_A_CKE0 [23] AV41 J50
    CT42 DDR_B_D19 DDR5_DQ0_4/DDR1_DQ2_4/DDR1_DQ4_4 DDR1_CKE0/DDR6_CA5/DDR6_CA6/DDR6_CA0 DDR_B_CKE0 [25]
    DDR_A_D18 DDR1_DQ0_3/DDR0_DQ2_3/DDR1_DQ0_3 DDR4/LP4/LP5/LP5 CMD Flip AR45
    CV42 CF42 DDR_B_D18 DDR5_DQ0_3/DDR1_DQ2_3/DDR1_DQ4_3 DDR4/LP4/LP5/LP5 CMD Flip
    DDR_A_D17 DDR1_DQ0_2/DDR0_DQ2_2/DDR1_DQ0_2 DDR0_CS1/DDR1_CA1/DDR1_CA1/DDR1_CA5 AV45 AE42
    CT41 CF47 DDR_B_D17 DDR5_DQ0_2/DDR1_DQ2_2/DDR1_DQ4_2 DDR1_CS1 / DDR5_CA1 / DDR5_CA1 / DDR5_CA5
    DDR_A_D16 DDR1_DQ0_1/DDR0_DQ2_1/DDR1_DQ0_1 DDR0_CS0/NC/DDR1_CS1/DDR1_CA4 DDR_A_CS#0 [23] AR47 AE47
    CV41 DDR_B_D16 DDR5_DQ0_1/DDR1_DQ2_1/DDR1_DQ4_1 DDR1_CS0 / NC / DDR5_CS1 / DDR5_CA4 DDR_B_CS#0 [25]
    [23] DDR_A_D[24..31] DDR_A_D31 DDR1_DQ0_0/DDR0_DQ2_0/DDR1_DQ0_0 DDR4/LP4/LP5/LP5 CMD Flip AV47
    CK47 CE53 [25] DDR_B_D[24..31] DDR_B_D31 DDR5_DQ0_0/DDR1_DQ2_0/DDR1_DQ4_0 DDR4/LP4/LP5/LP5 CMD Flip
    DDR_A_D30 DDR1_DQ1_7/DDR0_DQ3_7/DDR1_DQ1_7 NC/DDR0_CA0/DDR0_CA0/DDR0_CA6 AJ41 N42
    CM47 CE50 DDR_B_D30 DDR5_DQ1_7/DDR1_DQ3_7/DDR1_DQ5_7 NC/DDR7_CA5/DDR7_CA6/DDR7_CA0
    DDR_A_D29 DDR1_DQ1_6/DDR0_DQ3_6/DDR1_DQ1_6 NC/DDR0_CA1/DDR0_CA1/DDR0_CA5 AJ42 N45
    CK45 BL53 DDR_B_D29 DDR5_DQ1_6/DDR1_DQ3_6/DDR1_DQ5_6 NC/DDR7_CA4/DDR7_CA5/DDR7_CA1
    DDR_A_D28 DDR1_DQ1_5/DDR0_DQ3_5/DDR1_DQ1_5 NC/DDR2_CS0/DDR2_CA2/DDR2_CA2 AL41 N44
    CM45 BP47 DDR_B_D28 DDR5_DQ1_5/DDR1_DQ3_5/DDR1_DQ5_5 NC/DDR7_CA3/DDR7_CA4/DDR7_CS1
    DDR_A_D27 DDR1_DQ1_4/DDR0_DQ3_4/DDR1_DQ1_4 NC/DDR3_CA5/DDR3_CA6/DDR3_CA0 AL42 N47
    CK42 BP42 DDR_B_D27 DDR5_DQ1_4/DDR1_DQ3_4/DDR1_DQ5_4 NC/DDR7_CA2/DDR7_CA3/DDR7_CS0
    DDR_A_D26 DDR1_DQ1_3/DDR0_DQ3_3/DDR1_DQ1_3 NC/DDR3_CA4/DDR3_CA5/DDR3_CA1 AJ45 J53
    CM42 BP45 DDR_B_D26 DDR5_DQ1_3/DDR1_DQ3_3/DDR1_DQ5_3 NC/DDR6_CS0/DDR6_CA2/DDR6_CA2
    DDR_A_D25 DDR1_DQ1_2/DDR0_DQ3_2/DDR1_DQ1_2 NC/DDR3_CA3/DDR3_CA4/DDR3_CS1 AJ47 AC50
    CM41 BP44 DDR_B_D25 DDR5_DQ1_2/DDR1_DQ3_2/DDR1_DQ5_2 NC/DDR4_CA1/DDR4_CA1/DDR4_CA5
    DDR_A_D24 DDR1_DQ1_1/DDR0_DQ3_1/DDR1_DQ1_1 NC/DDR3_CA2/DDR3_CA3/DDR3_CS0 AL45 AC53
    CK41 DDR_B_D24 DDR5_DQ1_1/DDR1_DQ3_1/DDR1_DQ5_1 NC/DDR4_CA0/DDR4_CA0/DDR4_CA6
    [23] DDR_A_D[32..39] DDR_A_D39 DDR1_DQ1_0/DDR0_DQ3_0/DDR1_DQ1_0 LP4-LP5(NIL)/DDR4 (NIL)/DDR4 (IL) AL47
    BF53 BB44 [25] DDR_B_D[32..39] DDR_B_D39 DDR5_DQ1_0/DDR1_DQ3_0/DDR1_DQ5_0 LP4-LP5(NIL)/DDR4 (NIL)/DDR4 (IL)
    DDR_A_D38 DDR2_DQ0_7/DDR0_DQ4_7/DDR0_DQ2_7 DDR3_DQSP_1/DDR0_DQSP_7/DDR1_DQSP_3 DDR_A_DQS7 [23] A43 K36
    BF52 BD44 DDR_B_D38 DDR6_DQ0_7/DDR1_DQ4_7/DDR0_DQ6_7 DDR7_DQSP_1/DDR1_DQSP_7/DDR1_DQSP_7 DDR_B_DQS7 [25]
    DDR_A_D37 DDR2_DQ0_6/DDR0_DQ4_6/DDR0_DQ2_6 DDR3_DQSN_1/DDR0_DQSN_7/DDR1_DQSN_3 DDR_A_DQS#7 [23] B43 K38
    BF50 BK44 DDR_B_D37 DDR6_DQ0_6/DDR1_DQ4_6/DDR0_DQ6_6 DDR7_DQSN_1/DDR1_DQSN_7/DDR1_DQSN_7 DDR_B_DQS#7 [25]
    DDR_A_D36 DDR2_DQ0_5/DDR0_DQ4_5/DDR0_DQ2_5 DDR3_DQSP_0/DDR0_DQSP_6/DDR1_DQSP_2 DDR_A_DQS6 [23] D43 G44
    BF49 BH44 DDR_B_D36 DDR6_DQ0_5/DDR1_DQ4_5/DDR0_DQ6_5 DDR7_DQSP_0/DDR1_DQSP_6/DDR1_DQSP_6 DDR_B_DQS6 [25]
    DDR_A_D35 DDR2_DQ0_4/DDR0_DQ4_4/DDR0_DQ2_4 DDR3_DQSN_0/DDR0_DQSN_6/DDR1_DQSN_2 DDR_A_DQS#6 [23] E44 J44
    BH53 BA51 DDR_B_D35 DDR6_DQ0_4/DDR1_DQ4_4/DDR0_DQ6_4 DDR7_DQSN_0/DDR1_DQSN_6/DDR1_DQSN_6 DDR_B_DQS#6 [25]
    DDR_A_D34 DDR2_DQ0_3/DDR0_DQ4_3/DDR0_DQ2_3 DDR2_DQSP_1/DDR0_DQSP_5/DDR0_DQSP_3 DDR_A_DQS5 [23] A46 D39
    BH52 BA50 DDR_B_D34 DDR6_DQ0_3/DDR1_DQ4_3/DDR0_DQ6_3 DDR6_DQSP_1/DDR1_DQSP_5/DDR0_DQSP_7 DDR_B_DQS5 [25]
    DDR_A_D33 DDR2_DQ0_2/DDR0_DQ4_2/DDR0_DQ2_2 DDR2_DQSN_1/DDR0_DQSN_5/DDR0_DQSN_3 DDR_A_DQS#5 [23] B46 C39
    BH50 BG51 DDR_B_D33 DDR6_DQ0_2/DDR1_DQ4_2/DDR0_DQ6_2 DDR6_DQSN_1/DDR1_DQSN_5/DDR0_DQSN_7 DDR_B_DQS#5 [25]
    DDR_A_D32 DDR2_DQ0_1/DDR0_DQ4_1/DDR0_DQ2_1 DDR2_DQSP_0/DDR0_DQSP_4/DDR0_DQSP_2 DDR_A_DQS4 [23] D46 C45
    BH49 BG50 DDR_B_D32 DDR6_DQ0_1/DDR1_DQ4_1/DDR0_DQ6_1 DDR6_DQSP_0/DDR1_DQSP_4/DDR0_DQSP_6 DDR_B_DQS4 [25]
    [23] DDR_A_D[40..47] DDR_A_D47 DDR2_DQ0_0/DDR0_DQ4_0/DDR0_DQ2_0 DDR2_DQSN_0/DDR0_DQSN_4/DDR0_DQSN_2 DDR_A_DQS#4 [23] E47 D45
    AY53 CK44 [25] DDR_B_D[40..47] DDR_B_D47 DDR6_DQ0_0/DDR1_DQ4_0/DDR0_DQ6_0 DDR6_DQSN_0/DDR1_DQSN_4/DDR0_DQSN_6 DDR_B_DQS#4 [25]
    DDR_A_D46 DDR2_DQ1_7/DDR0_DQ5_7/DDR0_DQ3_7 DDR1_DQSP_1/DDR0_DQSP_3/DDR1_DQSP_1 DDR_A_DQS3 [23] E38 AJ44
    AY52 CM44 DDR_B_D46 DDR6_DQ1_7/DDR1_DQ5_7/DDR0_DQ7_7 DDR5_DQSP_1/DDR1_DQSP_3/DDR1_DQSP_5 DDR_B_DQS3 [25]
    DDR_A_D45 DDR2_DQ1_6/DDR0_DQ5_6/DDR0_DQ3_6 DDR1_DQSN_1/DDR0_DQSN_3/DDR1_DQSN_1 DDR_A_DQS#3 [23] D38 AL44
    C AY50 CT44 DDR_B_D45 DDR6_DQ1_6/DDR1_DQ5_6/DDR0_DQ7_6 DDR5_DQSN_1/DDR1_DQSN_3/DDR1_DQSN_5 DDR_B_DQS#3 [25] C
    DDR_A_D44 DDR2_DQ1_5/DDR0_DQ5_5/DDR0_DQ3_5 DDR1_DQSP_0/DDR0_DQSP_2/DDR1_DQSP_0 DDR_A_DQS2 [23] B38 AV44
    AY49 CV44 DDR_B_D44 DDR6_DQ1_5/DDR1_DQ5_5/DDR0_DQ7_5 DDR5_DQSP_0/DDR1_DQSP_2/DDR1_DQSP_4 DDR_B_DQS2 [25]
    DDR_A_D43 DDR2_DQ1_4/DDR0_DQ5_4/DDR0_DQ3_4 DDR1_DQSN_0/DDR0_DQSN_2/DDR1_DQSN_0 DDR_A_DQS#2 [23] A38 AR44
    BC53 CK51 DDR_B_D43 DDR6_DQ1_4/DDR1_DQ5_4/DDR0_DQ7_4 DDR5_DQSN_0/DDR1_DQSN_2/DDR1_DQSN_4 DDR_B_DQS#2 [25]
    DDR_A_D42 DDR2_DQ1_3/DDR0_DQ5_3/DDR0_DQ3_3 DDR0_DQSP_1/DDR0_DQSP_1/DDR0_DQSP_1 DDR_A_DQS1 [23] E41 AG51
    BC52 CK50 DDR_B_D42 DDR6_DQ1_3/DDR1_DQ5_3/DDR0_DQ7_3 DDR4_DQSP_1/DDR1_DQSP_1/DDR0_DQSP_5 DDR_B_DQS1 [25]
    DDR_A_D41 DDR2_DQ1_2/DDR0_DQ5_2/DDR0_DQ3_2 DDR0_DQSN_1/DDR0_DQSN_1/DDR0_DQSN_1 DDR_A_DQS#1 [23] D40 AG50
    BC50 CR51 DDR_B_D41 DDR6_DQ1_2/DDR1_DQ5_2/DDR0_DQ7_2 DDR4_DQSN_1/DDR1_DQSN_1/DDR0_DQSN_5 DDR_B_DQS#1 [25]
    DDR_A_D40 DDR2_DQ1_1/DDR0_DQ5_1/DDR0_DQ3_1 DDR0_DQSP_0/DDR0_DQSP_0/DDR0_DQSP_0 DDR_A_DQS0 [23] B40 AN51
    BC49 CR50 DDR_B_D40 DDR6_DQ1_1/DDR1_DQ5_1/DDR0_DQ7_1 DDR4_DQSP_0/DDR1_DQSP_0/DDR0_DQSP_4 DDR_B_DQS0 [25]
    [23] DDR_A_D[48..55] DDR_A_D55 DDR2_DQ1_0/DDR0_DQ5_0/DDR0_DQ3_0 DDR0_DQSN_0/DDR0_DQSN_0/DDR0_DQSN_0 DDR_A_DQS#0 [23] A40 AN50
    BK47 [25] DDR_B_D[48..55] DDR_B_D55 DDR6_DQ1_0/DDR1_DQ5_0/DDR0_DQ7_0 DDR4_DQSN_0/DDR1_DQSN_0/DDR0_DQSN_4 DDR_B_DQS#0 [25]
    DDR_A_D54 DDR3_DQ0_7/DDR0_DQ6_7/DDR1_DQ2_7 DDR4/LP4/LP5/LP5 CMD Flip G42
    BK45 CF44 DDR_B_D54 DDR7_DQ0_7/DDR1_DQ6_7/DDR1_DQ6_7 DDR4/LP4/LP5/LP5 CMD Flip
    DDR_A_D53 DDR3_DQ0_6/DDR0_DQ6_6/DDR1_DQ2_6 DDR0_ODT1/DDR1_CA0/DDR1_CA0/DDR1_CA6 G41 AE44
    BH47 CF45 DDR_B_D53 DDR7_DQ0_6/DDR1_DQ6_6/DDR1_DQ6_6 DDR1_ODT1/DDR5_CA0/DDR5_CA0/DDR5_CA6
    DDR_A_D52 DDR3_DQ0_5/DDR0_DQ6_5/DDR1_DQ2_5 DDR0_ODT0 / DDR1_CS0 / DDR1_CA2 / DDR1_CA2 DDR_A_ODT0 [23] J41 AE45
    BH45 DDR_B_D52 DDR7_DQ0_5/DDR1_DQ6_5/DDR1_DQ6_5 DDR1_ODT0/DDR5_CS0/DDR5_CA2/DDR5_CA2 DDR_B_ODT0 [25]
    DDR_A_D51 DDR3_DQ0_4/DDR0_DQ6_4/DDR1_DQ2_4 DDR4/LP4/LP5/LP5 CMD Flip J42
    BH42 CB47 DDR_B_D51 DDR7_DQ0_4/DDR1_DQ6_4/DDR1_DQ6_4 DDR4/LP4/LP5/LP5 CMD Flip
    DDR_A_D50 DDR3_DQ0_3/DDR0_DQ6_3/DDR1_DQ2_3 DDR0_MA16/DDR1_CA4/DDR1_CA5/DDR1_CA1 DDR_A_MA16_RAS# [23] G45 AA47
    BK42 CB44 DDR_B_D50 DDR7_DQ0_3/DDR1_DQ6_3/DDR1_DQ6_3 DDR1_MA16/DDR5_CA4/DDR5_CA5/DDR5_CA1 DDR_B_MA16_RAS# [25]
    DDR_A_D49 DDR3_DQ0_2/DDR0_DQ6_2/DDR1_DQ2_2 DDR0_MA15/DDR1_CA3/DDR1_CA4/DDR1_CS1 DDR_A_MA15_CAS# [23] J45 AA44
    BK41 CB45 DDR_B_D49 DDR7_DQ0_2/DDR1_DQ6_2/DDR1_DQ6_2 DDR1_MA15/DDR5_CA3/DDR5_CA4/DDR5_CS1 DDR_B_MA15_CAS# [25]
    DDR_A_D48 DDR3_DQ0_1/DDR0_DQ6_1/DDR1_DQ2_1 DDR0_MA14/DDR1_CA2/DDR1_CA3/DDR1_CS0 DDR_A_MA14_WE# [23] G47 AA45
    BH41 CF41 DDR_B_D48 DDR7_DQ0_1/DDR1_DQ6_1/DDR1_DQ6_1 DDR1_MA14/DDR5_CA2/DDR5_CA3/DDR5_CS0 DDR_B_MA14_WE# [25]
    [23] DDR_A_D[56..63] DDR_A_D63 DDR3_DQ0_0/DDR0_DQ6_0/DDR1_DQ2_0 DDR0_MA13/DDR1_CS1/DDR1_CS0/DDR1_CA3 DDR_A_MA13 [23] J47 AE41
    BD47 BU53 [25] DDR_B_D[56..63] DDR_B_D63 DDR7_DQ0_0/DDR1_DQ6_0/DDR1_DQ6_0 DDR1_MA13/DDR5_CS1/DDR5_CS0/DDR5_CA3 DDR_B_MA13 [25]
    DDR_A_D62 DDR3_DQ1_7/DDR0_DQ7_7/DDR1_DQ3_7 DDR0_MA12/DDR2_CA1/DDR2_CA1/DDR2_CA5 DDR_A_MA12 [23] G38 P53
    BB47 BT51 DDR_B_D62 DDR7_DQ1_7/DDR1_DQ7_7/DDR1_DQ7_7 DDR1_MA12/DDR6_CA1/DDR6_CA1/DDR6_CA5 DDR_B_MA12 [25]
    DDR_A_D61 DDR3_DQ1_6/DDR0_DQ7_6/DDR1_DQ3_6 DDR0_MA11/NC/DDR2_CS1/DDR2_CA4 DDR_A_MA11 [23] G36 N51
    BD45 BV42 DDR_B_D61 DDR7_DQ1_6/DDR1_DQ7_6/DDR1_DQ7_6 DDR1_MA11/NC/DDR6_CS1/DDR6_CA4 DDR_B_MA11 [25]
    DDR_A_D60 DDR3_DQ1_5/DDR0_DQ7_5/DDR1_DQ3_5 DDR0_MA10/DDR3_CA1/DDR3_CA1/DDR3_CA5 DDR_A_MA10 [23] H36 U42
    BB45 BU50 DDR_B_D60 DDR7_DQ1_5/DDR1_DQ7_5/DDR1_DQ7_5 DDR1_MA10/DDR7_CA1/DDR7_CA1/DDR7_CA5 DDR_B_MA10 [25]
    DDR_A_D59 DDR3_DQ1_4/DDR0_DQ7_4/DDR1_DQ3_4 DDR0_MA9/DDR2_CA0/DDR2_CA0/DDR2_CA6 DDR_A_MA9 [23] H38 P50
    BB42 BY53 DDR_B_D59 DDR7_DQ1_4/DDR1_DQ7_4/DDR1_DQ7_4 DDR1_MA9/DDR6_CA0/DDR6_CA0/DDR6_CA6 DDR_B_MA9 [25]
    DDR_A_D58 DDR3_DQ1_3/DDR0_DQ7_3/DDR1_DQ3_3 DDR0_MA8/DDR0_CA2/DDR0_CA3/DDR0_CS0 DDR_A_MA8 [23] N36 U53
    BB41 CA50 DDR_B_D58 DDR7_DQ1_3/DDR1_DQ7_3/DDR1_DQ7_3 DDR1_MA8/DDR4_CA2/DDR4_CA3/DDR4_CS0 DDR_B_MA8 [25]
    DDR_A_D57 DDR3_DQ1_2/DDR0_DQ7_2/DDR1_DQ3_2 DDR0_MA7/DDR0_CA4/DDR0_CA5/DDR0_CA1 DDR_A_MA7 [23] L36 W50
    BD42 BY52 DDR_B_D57 DDR7_DQ1_2/DDR1_DQ7_2/DDR1_DQ7_2 DDR1_MA7/DDR4_CA4/DDR4_CA5/DDR4_CA1 DDR_B_MA7 [25]
    DDR_A_D56 DDR3_DQ1_1/DDR0_DQ7_1/DDR1_DQ3_1 DDR0_MA6/DDR0_CA3/DDR0_CA4/DDR0_CS1 DDR_A_MA6 [23] L38 U52
    BD41 BY50 DDR_B_D56 DDR7_DQ1_1/DDR1_DQ7_1/DDR1_DQ7_1 DDR1_MA6/DDR4_CA3/DDR4_CA4/DDR4_CS1 DDR_B_MA6 [25]
    DDR3_DQ1_0/DDR0_DQ7_0/DDR1_DQ3_0 DDR0_MA5/DDR0_CA5/DDR0_CA6/DDR0_CA0 DDR_A_MA5 [23] N38 U50
    CD51 DDR7_DQ1_0/DDR1_DQ7_0/DDR1_DQ7_0 DDR1_MA5/DDR4_CA5/DDR4_CA6/DDR4_CA0 DDR_B_MA5 [25]
    DDR0_MA4/DDR0_CS0/DDR0_CA2/DDR0_CA2 DDR_A_MA4 [23] AA51
    CD53 DDR1_MA4/DDR4_CS0/DDR4_CA2/DDR4_CA2 DDR_B_MA4 [25]
    DDR0_MA3/DDR0_CS1/DDR0_CS0/DDR0_CA3 DDR_A_MA3 [23] AA53
    BV47 DDR1_MA3/DDR4_CS1/DDR4_CS0/DDR4_CA3 DDR_B_MA3 [25]
    DDR0_MA2/DDR3_CS0/DDR3_CA2/DDR3_CA2 DDR_A_MA2 [23] U47
    CE52 DDR1_MA2/DDR7_CS0/DDR7_CA2/DDR7_CA2 DDR_B_MA2 [25]
    DDR0_MA1/NC/DDR0_CS1/DDR0_CA4 DDR_A_MA1 [23] AC52
    BV41 DDR1_MA1/NC/DDR4_CS1/DDR4_CA4 DDR_B_MA1 [25]
    DDR0_MA0/NC/DDR3_CS1/DDR3_CA4 DDR_A_MA0 [23] U41
    DDR1_MA0/NC/DDR7_CS1/DDR7_CA4 DDR_B_MA0 [25]
    DDR4/LP4/LP5/LP5 CMD Flip
    BN50 DDR4/LP4/LP5/LP5 CMD Flip
    DDR0_BG1/DDR2_CA2/DDR2_CA3/DDR2_CS0 DDR_A_BG1 [23] K50
    BL52 DDR1_BG1/DDR6_CA2/DDR6_CA3/DDR6_CS0 DDR_B_BG1 [25]
    DDR0_BG0/DDR2_CA3/DDR2_CA4/DDR2_CS1 DDR_A_BG0 [23] J52
    DDR1_BG0/DDR6_CA3/DDR6_CA4/DDR6_CS1 DDR_B_BG0 [25]
    DDR4/LP4/LP5/LP5 CMD Flip
    CB42 DDR_A_BA1 [23] DDR4/LP4/LP5/LP5 CMD Flip
    DDR0_BA1/DDR1_CA5/DDR1_CA6/DDR1_CA0 AA42
    BV44 DDR1_BA1/DDR5_CA5/DDR5_CA6/DDR5_CA0 DDR_B_BA1 [25]
    DDR0_BA0/DDR3_CA0/DDR3_CA0/DDR3_CA6 DDR_A_BA0 [23] U44
    DDR1_BA0/DDR7_CA0/DDR7_CA0/DDR7_CA6 DDR_B_BA0 [25]
    DDR4/LP4/LP5/LP5 CMD Flip BT53
    DDR0_ACT#/DDR2_CS1/DDR2_CS0/DDR2_CA3 DDR_A_ACT# [23] N53
    DDR1_ACT#/DDR6_CS1/DDR6_CS0/DDR6_CA3 DDR_B_ACT# [25]
    DDR4/LP4/LP5/LP5 CMD Flip BV45
    DDR0_PAR/DDR3_CS1/DDR3_CS0/DDR3_CA3 DDR_A_PAR [23] U45
    DDR1_PAR/DDR7_CS1/DDR7_CS0/DDR7_CA3 DDR_B_PAR [25]
    AU50
    DDR0_ALERT# DDR_A_ALERT# [23] AU53
    AU49 DDR1_ALERT# DDR_B_ALERT# [25]
    DDR0_VREF_CA +0.6V_A_VREFCA [23] AU52
    DDR1_VREF_CA +0.6V_B_VREFCA [25]
    DDR_PG_CTRL Trace width/Spacing >= 20mils
    E52 Trace width/Spacing >= 20mils
    B DDR_VTT_CTL DV47 DDR_DRAMRST# B
    DRAM_RESET# SM_RCOMP0 TGL-U_BGA1449
    C49 RC25 1 2 100_0201_1%
    DDR_RCOMP @

    TGL-U_BGA1449
    @

    +1.2V

    1
    Buffer with Open Drain Output RC30
    470_0201_5%
    For VTT power control UC1D
    +1.2V +3VS
    REV 1.6

    2
    CC6 2 1 0.1U_0201_10V6K DDR_DRAMRST# RC31 1 @ 2 0_0201_5%
    DDR_DRAMRST#_R [23]
    1

    DV24
    UC3 RC28 1 RSVD_2
    DW47
    1 5 100K_0201_5% CC9 RSVD_3
    NC VCC DW49
    100P_0201_50V8J RSVD_4
    DDR_PG_CTRL A48
    2 ESD@ RSVD_5
    2

    A 4 2
    3 Y DDR_VTT_PG_CTRL [89]
    GND TGL-U_BGA1449
    @
    74AUP1G07GW_TSSOP5
    SA00005U600
    ESD

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2019/11/27 Deciphered Date 2020/11/27 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    TGL-UP3(3/14)DDR4
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K321P
    Date: Monday, August 02, 2021 Sheet 8 of 121
    5 4 3 2 1
    5 4 3 2 1

    SOC_SPI_0_D0
    BOOT HALT
    NO INTERNAL PU/PD GPP_C2
    HIGH: ENABLED TLS CONFIDENTIALITY
    INTERNAL PD 20K +1.8V_PRIM
    +3VALW LOW: DISABLED
    HIGH: TLS CONFIDENTIALITY ENABLE
    LOW: TLS CONFIDENTIALITY DISABLE SOC_GPP_C2 4.7K_0201_5% 1 2 RC86
    SOC_SPI_0_D2 SOC_SML0ALERT#
    RC631 1 2 4.7K_0201_5% SOC_SPI_0_D0 External pull-up is required. Recommend 100K if pulled ESPI OR EC LESS
    RC632 1 2 100K_0201_5% SOC_SPI_0_D2 up to 3.3V or 75K if pulled up to 1.8V. INTERNAL PD 20K
    SOC_SPI_0_D3 NO INTERNAL PU/PD HIGH: ESPI DISABLE
    RC630 1 2 100K_0201_5% LOW: ESPI ENABLE (Default)
    +3V_PRIM
    SOC_SPI_0_D3
    D
    External pull-up is required. Recommend 100K if pulled D
    up to 3.3V or 75K if pulled up to 1.8V. SOC_SML0ALERT#
    NO INTERNAL PU/PD ESPI OR EC LESS SOC_SML0ALERT# 4.7K_0201_5% 1 @ 2 RC610
    INTERNAL PD 20K
    HIGH: ESPI DISABLE 20K_0201_5% 1 @ 2 RC609
    LOW: ESPI ENABLE
    UC1E This strap is used in conjunction with Boot
    REV 1.6 Strap 1,2,3, (on GPP_H0, GPP_H1, GPP_H2 respectively).
    +3V_PRIM

    SOC_SPI_0_CLK DJ37 DK21 SOC_SMBCLK


    SOC_SPI_0_D3 DG35 SPI0_CLK GPP_C0/SMBCLK DM19 SOC_SMBDATA

    1
    +1.8V_PRIM SPI0_IO3 GPP_C1/SMBDATA SOC_GPP_B23
    SOC_SPI_0_D2 DJ39 DN19 SOC_GPP_C2 CPUNSSC CLOCK FREQ
    SOC_SPI_0_D1 SPI0_IO2 GPP_C2/SMBALERT# RC81
    DJ33 INTERNAL PD 20K
    SPI0_MISO 4.7K_0201_5%
    SPI ROM SOC_SPI_0_D0 DJ35
    SPI0_MOSI GPP_C3/SML0CLK
    DK19 SOC_SML0CLK HIGH: 19.2 MHz (form internal divider)
    @
    1
    100K_0201_5%
    RC648

    SOC_SPI_0_CS#1 DF35 DM17 SOC_SML0DATA LOW: 38.4 MHz (direct form crystal) (Default)
    SOC_SPI_0_CS#0 DG37 SPI0_CS1# GPP_C4/SML0DATA DN17 SOC_SML0ALERT#

    2
    TP@ 1 SOC_SPI_0_CS#2 DF39 SPI0_CS0# GPP_C5/SML0ALERT#
    T11 SPI0_CS2# PD_SMB_CK
    DK17 SOC_GPP_B23
    GPP_C6/SML1CLK PD_SMB_DA PD_SMB_CK [42]
    DJ6 DJ17
    PD_SMB_DA [42]
    2

    DN5 GPP_E11 / THC0_SPI1_CLK GPP_C7/SML1DATA CY50 SOC_GPP_B23


    DR9 GPP_E2 / THC0_SPI1_IO3 GPP_B23/SML1ALERT#/PCHHOT#/GSPI1_CS1#
    DM6 GPP_E1 / THC0_SPI1_IO2 DN53 ESPI_CLK RC34 1 EMI@ 2 49.9_0201_1%
    SOC_THC_0_RST# GPP_E12 / THC0_SPI1_IO1 GPP_A5/ESPI_CLK ESPI_IO3 ESPI_CLK_R [58]
    DK6 DJ53 RC36 1 2 15_0201_1%
    GPP_E13 / THC0_SPI1_IO0 GPP_A3/ESPI_IO3/SUSACK# ESPI_IO2 ESPI_IO3_R [58]
    DK8 DH50 RC35 1 2 15_0201_1%
    GPP_E10 / THC0_SPI1_CS# GPP_A2/ESPI_IO2/SUSWARN#_SUSPWRDNACK ESPI_IO1 ESPI_IO2_R [58]
    DV11 DP50 RC33 1 2 15_0201_1% To EC
    GPP_E8 / SATA_LED# GPP_A1/ESPI_IO1 ESPI_IO1_R [58]
    1
    4.7K_0201_5%
    RC649

    DW9 DP52 ESPI_IO0 RC32 1 2 15_0201_1%


    SOC_THC_0_RST# GPP_E17/THC0_SPI1_INT# GPP_A0/ESPI_IO0 ESPI_CS# ESPI_IO0_R [58]
    DT8 DK52
    GPP_E6/THC0_SPI1_RST# GPP_A4/ESPI_CS# ESPI_RST# ESPI_CS# [58]
    @ DL50
    GPP_A6/ESPI_RESET# ESPI_RST# [58]
    SOC_THC_0_RST# DN15
    C DK13 GPP_F11/THC1_SPI2_CLK C
    JTAG ODT DISABLE
    2

    DM13 GPP_F15/GSXSRESET#/THC1_SPI2_IO3 +3V_PRIM


    NO INTERNAL PU/PD
    HIGH: JTAG ODT ENABLED DN13 GPP_F14/GSXDIN/THC1_SPI2_IO2
    LOW: JTAG ODT DISABLED DJ15 GPP_F13/GSXSLOAD/THC1_SPI2_IO1
    GPP_F12/GSXDOUT/THC1_SPI2_IO0 SOC_SMBCLK RC558 1 2 1K_0201_5%
    DK15 SOC_SMBDATA
    GPP_F16/GSXCLK/THC1_SPI2_CS# RC559 1 2 1K_0201_5%
    DN10 SOC_SML0CLK
    GPP_F18/THC1_SPI2_INT# RC316 1 2 499_0201_1%
    DV14 SOC_SML0DATA
    GPP_F17/THC1_SPI2_RST# RC315 1 2 499_0201_1%
    DH3
    DH4 CL_CLK
    CC152 2 1 10P_0201_50V8J SOC_SPI_0_CLK CL_DATA
    DF2
    CL_RST# ESPI_CS# 75K_0201_5% 1 @ 2 RC444
    @EMI@ SOC_SPI_0_CLK 100K_0201_5% 1 2 RC441
    TGL-U_BGA1449 ESPI_RST# 75K_0201_5% 1 2 RC443
    EMC Suggestion @

    Follow 607872_TGL_UY_PDG for Glitch


    teknisi-indonesia.com
    < SPI ROM - 16+8M (Support ISH) >
    close to SPI ROM
    B +3VALW B
    16M SPI ROM
    SOC_SPI_0_D1_R RC82 1 2 56_0201_5% SOC_SPI_0_D1_R1 UC2 CC10 1 2 0.1U_0201_10V6K
    SOC_SPI_0_D0_R RC83 1 2 56_0201_5% SOC_SPI_0_D0_R1 SOC_SPI_0_CS#1 1 8
    SOC_SPI_0_CLK_R RC84 1 2 56_0201_5% SOC_SPI_0_CLK_R1 SOC_SPI_0_D1_R1 2 /CS VCC 7 SOC_SPI_0_D3_R1
    SOC_SPI_0_D3_R EMI@ SOC_SPI_0_D3_R1 SOC_SPI_0_D2_R1 DO(IO1) /HOLD(IO3) SOC_SPI_0_CLK_R1
    To SPI ROM RC85 1 2 56_0201_5% 3 6 1 2
    SOC_SPI_0_D2_R RC650 1 2 56_0201_5% SOC_SPI_0_D2_R1 4 /WP(IO2) CLK 5 SOC_SPI_0_D0_R1 CC11
    GND DI(IO0) 10P_0201_50V8J
    W 25Q128JVSIQ @EMI@
    SA00005VV20
    SOC_SPI_0_D1 RC594 1 2 5.1_0201_1% SOC_SPI_0_D1_R
    SOC_SPI_0_D0 RC595 1 2 5.1_0201_1% SOC_SPI_0_D0_R
    SOC_SPI_0_CLK RC596 1 2 5.1_0201_1% SOC_SPI_0_CLK_R
    SOC_SPI_0_D3 RC597 1 2 5.1_0201_1% SOC_SPI_0_D3_R
    SOC_SPI_0_D2 RC598 1 2 5.1_0201_1% SOC_SPI_0_D2_R
    +3VALW
    8M SPI ROM(RPMC)
    UC4 CC757 1 2 0.1U_0201_10V6K
    SOC_SPI_0_D1_R RC652 1 2 56_0201_5% SOC_SPI_0_D1_R2 SOC_SPI_0_CS#0 1 8
    SOC_SPI_0_D0_R RC651 1 2 56_0201_5% SOC_SPI_0_D0_R2 SOC_SPI_0_D1_R2 2 /CS VCC 7 SOC_SPI_0_D3_R2
    SOC_SPI_0_CLK_R RC572 1 2 56_0201_5% SOC_SPI_0_CLK_R2 SOC_SPI_0_D2_R2 3 DO(IO1) /HOLD(IO3) 6 SOC_SPI_0_CLK_R2 1 2
    SOC_SPI_0_D3_R EMI@ SOC_SPI_0_D3_R2 /WP(IO2) CLK SOC_SPI_0_D0_R2
    To SPI ROM RC653 1 2 56_0201_5% 4 5 CC756
    SOC_SPI_0_D2_R RC654 1 2 56_0201_5% SOC_SPI_0_D2_R2 GND DI(IO0) 10P_0201_50V8J
    W 25R64JVSSIQ @EMI@
    SA0000DAO00

    A Follow 607872_TGL_UY_PDG A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2019/11/27 Deciphered Date 2020/11/27 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    TGL-UP3(4/14)SPI,ESPI,SMB,LPC
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 2.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K321P
    Date: Thursday, June 03, 2021 Sheet 9 of 121
    5 4 3 2 1
    5 4 3 2 1

    UC1G
    REV 1.6

    D D
    DW15 DR38 HDA_BIT_CLK
    DW24 GPP_F8/I2S_MCLK2_INOUT GPP_R0/HDA_BCLK/I2S0_SCLK DU37 HDA_SYNC
    GPP_D19/I2S_MCLK1 GPP_R1/HDA_SYNC/I2S0_SFRM DT37 HDA_SDOUT
    DG41 GPP_R2/HDA_SDO/I2S0_TXD DV37 HDA_SDIN0
    GPP_A23/I2S1_SCLK GPP_R3/HDA_SDI0/I2S0_RXD HDA_SDIN0 [56]
    DT38
    DV38 GPP_R7/I2S1_SFRM DV41 HDA_RST#
    HDA_SDIN1 DW38 GPP_R6/I2S1_TXD GPP_R4/HDA_RST# DL53
    GPP_R5/HDA_SDI1/I2S1_RXD GPP_A7/I2S2_SCLK/DMIC_CLK_A0 DG51 CNV_RF_RESET#
    SOC_DMIC_R_CLK0 GPP_A8/I2S2_SFRM/CNV_RF_RESET#/DMIC_DATA_0 CNV_RF_RESET# [52]
    DN31 DG50
    SOC_DMIC_R_DAT0 DM31 GPP_S6/SNDW3_CLK/DMIC_CLK_A0 GPP_A10/I2S2_RXD/DMIC_DATA1
    GPP_S7/SNDW3_DATA/DMIC_DATA0 DL49 CLKREQ_CNV#
    GPP_A9/I2S2_TXD/MODEM_CLKREQ/CRF_XTAL_CLKREQ/DMIC_CLK_A1 CLKREQ_CNV# [52]
    DK33 DL52
    DK31 GPP_S4/SNDW2_CLK/DMIC_CLK_A1 GPP_A11/PMC_I2C_SDA/I2S3_SCLK
    GPP_S5/SNDW2_DATA/DMIC_DATA1 DH49 WLBT_OFF#_R RC571 1 @ 2 0_0201_5%
    GPP_A13/PMC_I2C_SCL/I2S3_TXD/DMIC_CLK_B0 WLBT_OFF# [52]
    DW35
    DV35 GPP_S2/SNDW1_CLK/DMIC_CLK_B0 DF33 SNDW_RCOMP RC359 1 2 200_0201_1%
    GPP_S3/SNDW1_DATA/DMIC_CLK_B1 SNDW_RCOMP
    DT32
    DR35 GPP_S0/SNDW0_CLK
    GPP_S1/SNDW0_DATA

    TGL-U_BGA1449
    @

    C C
    75K_0201_5% 1 2 RC307 CNV_RF_RESET#
    100K_0201_5% 1 2 RC448 HDA_BIT_CLK
    33K_0201_5% 1 2 RC449 HDA_RST#
    33K_0201_5% 1 @ 2 RC450 HDA_SDIN1

    < HD AUDIO >


    RC46 1 EMI@ 2 33_0201_5% HDA_BIT_CLK
    [56] HDA_BIT_CLK_R Follow
    [56] HDA_SYNC_R RC48 1 2 33_0201_5% HDA_SYNC 607872_TGL_UY_PDG for Glitch
    RC47 1 2 33_0201_5% HDA_SDOUT
    [56] HDA_SDOUT_R

    +1.8VS +1.8VS +3VS

    1
    RC575 RC576 RC573 RC574
    2.2K_0402_5% 3.3K_0402_5% 3.3K_0402_5% 470_0402_1%
    < To Enable ME Override >

    2
    B B

    2
    G
    SOC_DMIC_R_CLK0 1 6
    HDA_SDOUT SOC_DMIC_CLK0 [38]

    D
    [58] ME_EN RC51 1 @ 2 0_0201_5%
    QC4B
    PJT138KA_SOT363-6

    5
    G
    SOC_DMIC_R_DAT0 4 3
    SOC_DMIC_DAT0 [38]

    D
    QC4A
    PJT138KA_SOT363-6

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2019/11/27 Deciphered Date 2020/11/27 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    TGL-UP3(5/14)HDA,SD
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 2.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K321P
    Date: Thursday, June 03, 2021 Sheet 10 of 121
    5 4 3 2 1
    5 4 3 2 1

    +3VS

    Follow CLKREQ_PEG#0 10K_0201_5% 1 DIS@ 2 RC523


    607872_TGL_UY_PDG_Rev0p5 for Glitch CLKREQ_PCIE#2 10K_0201_5% 1 2 RC353
    UC1K CLKREQ_PCIE#4 10K_0201_5% 1 2 RC64
    +3VALW REV 1.6 CLKREQ_PCIE#5 10K_0201_5% 1 2 RC352
    BW1 DU14 CPU_C10_GATE#
    CLKOUT_PCIE_P6 GPP_F19/SRCCLKREQ6# CLKREQ_PCIE#5 100K_0201_5% 1 @ 2 RC122
    BW2 DF23
    RC553 1 2 100K_0201_5% PM_SLP_S0# CLKOUT_PCIE_N6 GPP_H11/SRCCLKREQ5# CLKREQ_PCIE#4 CLKREQ_PCIE#5 [68] 100K_0201_5% 1 2 RC656
    DG25
    GPP_H10/SRCCLKREQ4# CLKREQ_PCIE#4 [71]
    PM_SLP_LAN# CB2 DT24 CLKREQ_PEG#0
    RC655 1 2 100K_0201_5% [68] CLK_PCIE_P5 CLKOUT_PCIE_P5 GPP_D8/SRCCLKREQ3# CLKREQ_PCIE#2 10K_0201_5% 1 @ 2 RC524
    SLP_SUS# SSD CB1 DT30 CLKREQ_PCIE#2 [52] CLKREQ_PCIE#4
    RC394 1 2 100K_0201_5% [68] CLK_PCIE_N5 CLKOUT_PCIE_N5 GPP_D7/SRCCLKREQ2# 10K_0201_5% 1 @ 2 RC68
    PM_SLP_S5# DV30
    RC395 1 2 100K_0201_5% GPP_D6/SRCCLKREQ1# CLKREQ_PEG#0
    PM_SLP_S4# DW30
    RC396 1 2 100K_0201_5% GPP_D5/SRCCLKREQ0# CLKREQ_PEG#0 [27]
    PM_SLP_S3# BW4
    RC397 1 2 100K_0201_5% [71] CLK_PCIE_P4 CLKOUT_PCIE_P4 SOC_XTAL38.4_OUT
    PM_SLP_A# Card Reader BW5 DM1
    D RC398 1 2 100K_0201_5% [71] CLK_PCIE_N4 CLKOUT_PCIE_N4 XTAL_OUT SOC_XTAL38.4_IN D
    PM_SLP_WLAN# DL1
    RC400 1 2 100K_0201_5% XTAL_IN +3VALW
    CL7
    CL8 CLKOUT_PCIE_P3 DW41 SUSCLK RC376 1 @ 2 0_0201_5%
    CLKOUT_PCIE_N3 GPD8/SUSCLK SUSCLK_R [52]
    CB4 DT47 SOC_RTCX2
    [52] CLK_PCIE_P2 CB5 CLKOUT_PCIE_P2 RTCX2 DR47 SOC_RTCX1
    WLAN [52] CLK_PCIE_N2 CLKOUT_PCIE_N2 RTCX1 PM_BATLOW# 8.2K_0201_5% 2 1 RC69
    BY4 DN37 SOC_RTCRST# WAKE# 8.2K_0201_5% 2 1 RC451
    +3VALW CLKOUT_PCIE_P1 RTCRST#
    BY3 DK37 SOC_SRTCRST# LAN_WAKE# 10K_0201_5% 2 1 RC452
    CLKOUT_PCIE_N1 SRTCRST# SPIVCCIOSEL 4.7K_0201_5% 2 @ 1 RC456
    RC428 1 2 10K_0201_5% SYS_RESET#
    CN7
    [27] CLK_PEG_P0 CN8 CLKOUT_PCIE_P0
    DGPU 4.7K_0201_5% 2 1 RC457
    [27] CLK_PEG_N0 CLKOUT_PCIE_N0
    RC59 2 1 60.4_0402_1% XCLK_BIASREF DJ5
    @ESD@ CC20 2 1 100P_0201_25V8J XCLK_BIASREF PMCALERT#_R 75K_0201_5% 2 @ 1 RC118
    EC_RSMRST# TGL-U_BGA1449 SUSCLK 10K_0201_5% 2 @ 1 RC375
    @ESD@ CC21 2 1 100P_0201_25V8J
    @
    ESD@ CC22 2 1 100P_0201_25V8J SYS_PWROK UC1L
    SLP_SUS# DV49 REV 1.6 BM9 H_PROCPWRGD
    SOC_PLTRST# [90] SLP_SUS# SLP_SUS# PROCPWRGD PBTN_OUT# TP@ T503 Follow
    ESD@ CC23 2 1 100P_0201_25V8J DK41
    PM_SLP_S5# DM43 GPD3/PWRBTN# DN41 PM_BATLOW# PBTN_OUT# [58] 609003_TGL_U_DDR4_SODIMM_RVP_SCH
    ESD@ CC758 2 1 100P_0201_25V8J EC_RSMRST#_R PM_SLP_S4# DJ41 GPD10/SLP_S5# GPD0/BATLOW# DK43 AC_PRESENT_R RC66 1 @ 2 0_0201_5%
    [58,89] PM_SLP_S4# PM_SLP_S3# GPD5/SLP_S4# GPD1/ACPRESENT AC_PRESENT [30,58]
    DJ43
    [16,58,66] PM_SLP_S3# PM_SLP_A# GPD4/SLP_S3#
    DR41 CW40 PMCALERT#_R RC5631 @ 2 0_0201_5% PMCALERT# [42] ORB not im-plement, CRB have implement
    PM_SLP_WLAN# DT44 GPD6/SLP_A# GPP_B11/PMCALERT# DN27 CPU_C10_GATE#
    ESD GPD9/SPL_WLAN# GPP_H18/CPU_C10_GATE#
    GPP_H3/SX_EXIT_HOLDOFF#
    DG31
    CPU_C10_GATE# [16]
    KBL_ID [63] SOC_GPP_F21 100K_0201_5% 1 @ 2 RC137
    PM_SLP_S0# DD42
    PM_SLP_LAN# DN39 GPP_B12/SLP_S0# DK39 WAKE#
    SLP_LAN# WAKE# EC_VCCST_PG 0.1U_0201_10V6K 1 2 CC752
    EC_RSMRST#_R DM35 DM41 LAN_WAKE#
    SYS_RESET# RSMRST# GPD2/LAN_WAKE# ESD@
    DD10 DT41
    SOC_PLTRST# SYS_RESET# GPD11/LANPHYPC/DSWLDO_MON ESD Suggestion
    DD41
    GPP_B13/PLTRST# DN43 GPD7
    GPD7 TP@ T501 SOC_RTCX2
    PCH_DPWROK_R DK35 1 @ 2 SOC_RTCX2_R 1 2
    SYS_PWROK DF10 DSW_PWROK CE5 VCCSTPWRGOOD_TCSS RC453 1 @ 2 0_0201_5% RC633 0_0201_5%
    C CC18 C
    [58] SYS_PWROK PCH_PWROK DN35 SYS_PWROK VCCSTPWRGOOD_TCSS BP8 EC_VCCST_PG
    [58] PCH_PWROK PCH_PWROK VCCST_PWRGD VCCST_OVERRIDE VCCST_OVERRIDE_R 8.2P_0201_50V8B
    +3VL_RTC BP9 RC388 1 @ 2 0_0201_5%
    SM_INTRUDER# DM37 VCCST_OVERRIDE

    2
    SPIVCCIOSEL DT49 INTRUDER# DR12
    SPIVCCIOSEL GPP_F20/EXT_PWR_GATE# DW12 SOC_GPP_F21 RC62 YC1
    RC56 1 2 20K_0201_5% SOC_SRTCRST# GPP_F21/EXT_PWR_GATE2# 10M_0201_5% 32.768KHZ_12.5PF_9H03200042
    SJ10000PW00
    1 2 1U_0201_6.3V6M

    1
    CC13
    TGL-U_BGA1449

    2
    @ CC17
    @ CLRP1 1 2 SHORT PADS CLR ME 8.2P_0201_50V8B
    footprint coated with solder mask! SOC_RTCX1 1 @ 2 SOC_RTCX1_R 1 2
    @
    RC665 1 2 0_0201_5% RC155 0_0201_5%
    RC58 1 2 20K_0201_5% SOC_RTCRST# RC72 1 @ 2 0_0402_5%
    EC_CLEAR_CMOS# [58]
    +3VALW
    CC14 1 2 1U_0201_6.3V6M

    @ CLRP2 1 2 SHORT PADS CLR CMOS


    UC32 Co-lay 32.768KHZ

    5
    RC377 1 2 1M_0201_5% SM_INTRUDER#
    EC_RSMRST# 1

    P
    [58] EC_RSMRST# B 4 EC_RSMRST#_R SOC_RTCX1_R 1 2 SOC_RTCX2_R
    CC319 1 @ 2 0.1U_0201_10V6K Y
    3V/5VALW_PG 2
    [58,87,90] 3V/5VALW_PG A

    G
    RC427 1 @ 2 1M_0201_5% MC74VHC1G08EDFT2G_SC70-5 YC3 @
    32.768KHZ_12.5_X1A000171000118

    1
    SA0000BJI00

    10K_0201_5%

    10K_0201_5%
    RC78 1 2 100K_0201_5% PCH_PWROK

    3
    SJ100015U00

    RC4057

    RC111
    DC4 @
    VR_ON 2 1 PM_SLP_S3#
    [58,97] VR_ON

    2
    RB751S40T1G_SOD523-2

    2
    tPLT17 DC6
    SOC_XTAL38.4_IN
    RB751V-40_SOD323-2 @
    B
    From EC (Open-Drain) +1.05V_VCCST RC664 1 2 0_0201_5%
    B

    1 +3VALW SOC_XTAL38.4_OUT RC57 1 2 200K _0201_1%


    1

    RC76

    1
    1
    1K_0201_5% RC55 RC54
    UC23

    5
    33_0201_5% 33_0201_5%
    2

    PCH_DPWROK 1 EMI@ EMI@

    P
    [58] PCH_DPWROK B PCH_DPWROK_R
    VCCST_PWRGD RC77 1 2 60.4_0402_1% EC_VCCST_PG 4

    2
    2
    [58] VCCST_PWRGD 3V/5VALW_PG Y

    SOC_XTAL38.4_OUT_R

    SOC_XTAL38.4_IN_R
    2
    A

    G
    MC74VHC1G08EDFT2G_SC70-5
    SA0000BJI00

    3
    1
    10K_0201_5%

    1
    10K_0201_5%
    RC4056

    RC4060
    2

    2
    YC2
    VCCST_EN 1
    1
    2
    3
    4 1

    +3V_PRIM CC26 38.4MHZ_10PF_8Y38420005 CC27


    10P_0201_50V8J 10P_0201_50V8J
    To EC 2 2
    RC417 1 2 100K_0201_5% VCCST_OVERRIDE_LS VCCST_PWRGD
    RC418 1 2 100K_0201_5% VCCST_OVERRIDE_N
    RC419 1 2 100K_0201_5% VCCST_OVERRIDE_R
    VCCST_OVERRIDE_LS [16] PCH PLTRST
    +3VALW
    3
    6

    SOC_PLTRST# RC63 1 @ 2 0_0402_5% PCI_RST#


    D PCI_RST# [27,52,58,68,71]
    RC568 1 2 VCCST_PWRGD# 2 G
    D
    QC1B
    S PJT138KA_SOT363-6
    100K_0201_5%
    VCCST_OVERRIDE_N 5

    1
    1

    G
    RC312
    100K_0201_5%
    6 QC2B
    3

    A D S PJT7838_SOT363-6 A
    PM_SLP_S3#
    D
    4 SB00001EJ00 5 G QC1A

    2
    VGS(Max) : 1 V S PJT138KA_SOT363-6
    VCCST_OVERRIDE_R 2 For Glitch
    4

    G
    stuff for CNVI check list
    QC2A
    S PJT7838_SOT363-6
    1 SB00001EJ00
    VGS(Max) : 1 V
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2019/11/27 Deciphered Date 2020/11/27 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    TGL-UP3(6/14)CLK,GPIO
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K321P
    Date: Friday, July 30, 2021 Sheet 11 of 121
    5 4 3 2 1
    5 4 3 2 1

    F
    n
    ti
    o

    M
    D
    L
    S
    T
    IN
    G
    O

    0
    E

    ED
    u

    T
    c
    n
    _

    G
    P
    P

    0 1
    +3VS
    ( _ )

    T
    u
    h u
    o
    c T
    RC459 1 2 49.9K_0402_1% UART_2_CRXD_DTXD
    RC460 1 2 49.9K_0402_1% UART_2_CTXD_DRXD

    0
    N
    n

    h
    RC106 1 2 1K_0402_5% I2C_0_SDA

    o
    -

    c
    RC105 1 2 1K_0402_5% I2C_0_SCL
    RC520 1 DIS@ 2 10K_0201_5% DGPU_PWR_EN

    UC1F
    REV 1.6

    RC518 1 @ 2 10K_0201_5% DGPU_HOLD_RST# +3VS


    RC519 1 DIS@ 2 10K_0201_5% GPU_EVENT#_1V8 DC53 DR27
    [30] GPU_EVENT#_1V8 SOC_GPP_B18 DA51 GPP_B16/GSPI0_CLK GPP_D14/ISH_UART0_TXD DW27 MODEL_SETTING0
    RC98 1 TS@ 2 10K_0201_5%
    OBRAM_ID4 DC49 GPP_B18/GSPI0_MOSI GPP_D13/ISH_UART0_RXD DV25
    D GPP_B17/GSPI0_MISO GPP_D16/ISH_UART0_CTS# RC99 1 2 10K_0201_5% D
    HDA_SPKR DC50 DT25
    [56,58] HDA_SPKR WL_OFF#_R GPP_B14/SPKR/TIME_SYNC1/GSPI0_CS1#GPP_D15/ISH_UART0_RTS#/GSPI2_CS1#/IMGCLKOUT5 NTS@
    RC570 1 @ 2 0_0201_5% DC52
    [52] WL_OFF# GPP_B15/GSPI0_CS0# DB45
    OBRAM_ID1 CY49 GPP_B6/ISH_I2C0_SCL DB44
    OBRAM_ID3 CY53 GPP_B20/GSPI1_CLK GPP_B5/ISH_I2C0_SDA
    OBRAM_ID2 CY52 GPP_B22/GSPI1_MOSI CY39

    D
    P

    e
    e
    t
    G
    U

    l
    c
    GPP_B21/GSPI1_MISO GPP_B8/ISH_I2C1_SCL

    S
    OBRAM_ID0 DA50 DB47
    GPP_B19/GSPI1_CS0# GPP_B7/ISH_I2C1_SDA
    DGPU_HOLD_RST# DV21 DD47
    [27] DGPU_HOLD_RST# DGPU_PWR_EN DT21 GPP_C9/UART0_TXD GPP_B10/I2C5_SCL/ISH_I2C2_SCL DD44 +3VS
    [37,58] DGPU_PWR_EN DGPU_ALL_PGOOD DR21 GPP_C8/UART0_RXD GPP_B9/I2C5_SDA/ISH_I2C2_SDA
    [37] DGPU_ALL_PGOOD GPP_C11/UART0_CTS#
    DW21 DJ8 RC115 1 DIS@ 2 10K_0402_5% DGPU_PRSNT
    GPP_C10/UART0_RTS# GPP_E16/ISH_GP7 DR7 DGPU_PRSNT
    GPP_E15/ISH_GP6 RC116 1 2 10K_0402_5%
    RC4063 1 @ 2 0_0201_5% TS_I2C_RST#_R DV19 DR24 UMA@
    [38,58] TS_I2C_RST# GPP_C13/UART1_TXD/ISH_UART1_TXD GPP_D18/ISH_GP5
    RC514 1 @ 2 0_0201_5% SOC_TS_EN# DT19 DU25 GPIO_Reserve
    [38,58] TS_EN# 2 0_0201_5% BKOFF#_R GPP_C12/UART1_RXD/ISH_UART1_RXD GPP_D17/ISH_GP4
    RC516 1 @ DR18 DV31
    [38,58] BKOFF# GC6_FB_EN1V8 DU19 GPP_C15/UART1_CTS#/ISH_UART1_CTS# GPP_D3/ISH_GP3/BK3/SBK3 DU31
    [30,31] GC6_FB_EN1V8 GPP_C14/UART1_RTS#/ISH_UART1_RTS# GPP_D2/ISH_GP2/BK2/SBK2 DT27 DGPU_SEL0
    UART_2_CTXD_DRXD DJ21 GPP_D1/ISH_GP1/BK1/SBK1 DV27 MODEL_SETTING0

    D
    P

    S
    L
    [52] UART_2_CTXD_DRXD GPP_C21/UART2_TXD GPP_D0/ISH_GP0/BK0/SBK0

    G
    UART_2_CRXD_DTXD

    ED
    F
    n
    ti -G
    o
    DG23

    0
    u N
    [52] UART_2_CRXD_DTXD
    _

    c 8
    n
    GPP_C20/UART2_RXD

    G
    P 01
    2 0_0201_5% TS_DISABLE#_R GPP_RCOMP

    P
    1 DJ19 DR51 RC178 1 2 200_0201_1%

    1
    RC515 @
    [38,58] TS_DISABLE# DF21 GPP_C23/UART2_CTS#
    GPP_C22/UART2_RTS#
    GPP_RCOMP
    ( _ )
    SOC_GPP_T3

    5
    DN33 1

    1
    S
    I2C_0_SCL GPP_T3 SOC_GPP_T2 TP@ T42
    DV18 DT35 1 TP@ T43
    [63] I2C_0_SCL I2C_0_SDA GPP_C17/I2C0_SCL GPP_T2
    DW18
    Touch Pad [63] I2C_0_SDA GPP_C16/I2C0_SDA DG17 FP_RST
    DJ23 GPP_U5 DG19 TP_INT# FP_RST [66]
    DT18 GPP_C19/I2C1_SCL GPP_U4 TP_INT# [58,63]
    GPP_C18/I2C1_SDA
    DJ29 RC160
    DJ31 GPP_H5/I2C2_SCL
    GPP_H4/I2C2_SDA N18S_G5@
    10K_0201_5%
    I2C_3_SCL DF29
    [38] I2C_3_SCL I2C_3_SDA GPP_H7/I2C3_SCL +3VS
    DG29
    Touch Screen [38] I2C_3_SDA GPP_H6/I2C3_SDA
    C DF25 C
    DF27 GPP_H9/I2C4_SCL/CNV_MFUART2_TXD DGPU_SEL0
    GPP_H8/I2C4_SDA/CNV_MFUART2_RXD RC159 1 @ 2 10K_0201_5%
    RC160 1 @ 2 10K_0201_5%

    TGL-U_BGA1449
    @

    Strap Pin

    G
    IO

    e
    e
    v
    P

    s
    r
    e
    R
    +3VS
    +3VS

    RC527 1 @ 2 10K_0201_5% GPIO_Reserve

    1
    4.7K_0201_5%
    RC278

    4.7K_0201_5%
    RC277
    RC528 1 @ 2 10K_0201_5%

    @ @

    2
    SOC_GPP_B18

    HDA_SPKR

    1
    20K_0201_5%
    RC281

    20K_0201_5%
    RC282
    @ @

    2
    B B

    +3VS +3VS +3VS +3VS +3VS


    RC567 MD_S4G@ RC561 MD_S4G@ RC93 MD_S4G@ RC95 MD_S4G@ RC94 MD_S4G@
    10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
    1

    RC567 MD_H4G@ RC561 MD_H4G@ RC93 MD_H4G@ RC95 MD_H4G@ RC91 MD_H4G@
    RC566 RC560 RC93 RC92 RC91 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
    10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% GPP_B18
    @ @ @ @ @ RC567 MD_M4G@ RC561 MD_M4G@ RC93 MD_M4G@ RC92 MD_M4G@ RC94 MD_M4G@ No Reboot
    10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% INTERNAL PD 20K
    2
    2

    OBRAM_ID4 OBRAM_ID3 OBRAM_ID2 OBRAM_ID1 OBRAM_ID0 HIGH: No Reboot


    LOW: Reboot Enable (Default)
    1

    1
    1

    RC567 RC561 RC96 RC95 RC94 RC566 MD_S8G@ RC561 MD_S8G@ RC93 MD_S8G@ RC95 MD_S8G@ RC94 MD_S8G@
    10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% SPKR
    10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% TOP SWAP OVERRIDE
    @ @ @ @ @ INTERNAL PD 20K
    RC566 MD_H8G@ RC561 MD_H8G@ RC93 MD_H8G@ RC95 MD_H8G@ RC91 MD_H8G@
    HIGH: Top swap enable
    2

    10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%


    LOW: Disable (Default)
    RC566 MD_M8G@ RC561 MD_M8G@ RC93 MD_M8G@ RC92 MD_M8G@ RC94 MD_M8G@
    10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%

    RC566 MD_S16G@ RC561 MD_S16G@ RC93 MD_S16G@ RC92 MD_S16G@ RC91 MD_S16G@
    10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%

    RC566 MD_H16G@ RC560 MD_H16G@ RC96 MD_H16G@ RC95 MD_H16G@ RC94 MD_H16G@
    10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%

    RC566 MD_M16G@ RC560 MD_M16G@ RC96 MD_M16G@ RC92 MD_M16G@ RC94 MD_M16G@
    10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%

    RC566 MD_H16G2@ RC560 MD_H16G2@ RC96 MD_H16G2@ RC92 MD_H16G2@ RC91 MD_H16G2@
    10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2019/11/27 Deciphered Date 2020/11/27 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    TGL-UP3(7/14)GPIO
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K321P
    Date: Thursday, June 03, 2021 Sheet 12 of 121
    5 4 3 2 1
    5 4 3 2 1

    UC1I
    BT7 REV 1.6 CV4
    [68] PCIE_CTX_DRX_P12 PCIE12_TXP/SATA1_TXP USB2P_10 USB20_P10 [52]
    BT8 CY3 NGFF WLAN+BT
    [68] PCIE_CTX_DRX_N12 PCIE12_TXN/SATA1_TXN USB2N_10 USB20_N10 [52]
    [68] PCIE_CRX_DTX_P12 CE2
    SATA SSD PCIE12_RXP/SATA1_RXP
    [68] PCIE_CRX_DTX_N12 CE1 DD5
    PCIE12_RXN/SATA1_RXN USB2P_9 DD4
    BT9 USB2N_9
    [68] PCIE_CTX_DRX_P11 PCIE11_TXP/SATA0_TXP
    BV9 CW9
    [68] PCIE_CTX_DRX_N11 PCIE11_TXN/SATA0_TXN USB2P_8
    [68] PCIE_CRX_DTX_P11 CF4 DA9
    CF3 PCIE11_RXP/SATA0_RXP USB2N_8
    [68] PCIE_CRX_DTX_N11 PCIE11_RXN/SATA0_RXN DD1
    SSD USB2P_7 USB20_P7 [66]
    [68] PCIE_CTX_DRX_P10 BV7 DD2 FingerPrint
    D PCIE10_TXP USB2N_7 USB20_N7 [66] D
    [68] PCIE_CTX_DRX_N10 BV8
    CG2 PCIE10_TXN DA1
    [68] PCIE_CRX_DTX_P10 PCIE10_RXP USB2P_6 USB20_P6 [38]
    [68] PCIE_CRX_DTX_N10 CG1 DA2 Camera
    PCIE10_RXN USB2N_6 USB20_N6 [38]
    BY7 DA12
    [68] PCIE_CTX_DRX_P9 PCIE9_TXP USB2P_5
    BY8 DA11
    [68] PCIE_CTX_DRX_N9 PCIE9_TXN USB2N_5
    [68] PCIE_CRX_DTX_P9 CG5
    CG4 PCIE9_RXP DC8
    [68] PCIE_CRX_DTX_N9 PCIE9_RXN USB2P_4 DC7
    CB8 USB2N_4
    CB7 PCIE8_TXP DB4
    PCIE8_TXN USB2P_3 USB20_P3 [42]
    CK5 DB3 USB2.0 / 3.0 Port (Type-C)
    PCIE8_RXP USB2N_3 USB20_N3 [42]
    CK4
    PCIE8_RXN DA5
    USB2P_2 USB20_P2 [71]
    CD9 DA4 USB2.0 / 3.0 Port (MB - 2)
    PCIE7_TXP USB2N_2 USB20_N2 [71]
    CD8
    CK1 PCIE7_TXN DC11
    PCIE7_RXP USB2P_1 USB20_P1 [71]
    CK2 DC9 USB2.0 / 3.0 Port (MB - 1)
    PCIE7_RXN USB2N_1 USB20_N1 [71]
    CG8 DP4
    CG7 PCIE6_TXP GPP_E0/SATAXPCIE0/SATAGP0 DF41 NGFF_SSD_PEDET
    PCIE6_TXN GPP_A12/SATAXPCIE1/SATAGP1/I2S3_SFRM NGFF_SSD_PEDET [68]
    CL4
    CL3 PCIE6_RXP DD8 USB_OC0#
    PCIE6_RXN GPP_E9/USB_OC0# USB_OC3# USB_OC0# [71]
    DJ45
    CJ8 GPP_A16/USB_OC3#/I2S4_SFRM
    CJ7 PCIE5_TXP DN6
    PCIE5_TXN GPP_E5/DEVSLP1 DEVSLP2 [68]
    CN2 DG8
    CN1 PCIE5_RXP GPP_E4/DEVSLP0
    PCIE5_RXN DN29
    C GPP_H15/M2_SKT2_CFG3 C
    [71] PCIE_CTX_DRX_P4 CR8 DK29
    CR7 PCIE4_TXP/USB31_4_TXP GPP_H14/M2_SKT2_CFG2 DT31
    [71] PCIE_CTX_DRX_N4 PCIE4_TXN/USB31_4_TXN GPP_H13/M2_SKT2_CFG1 TS_INT# [38]
    Card Reader [71] PCIE_CRX_DTX_P4 CN5 DR32
    CN4 PCIE4_RXP/USB31_4_RXP GPP_H12/M2_SKT2_CFG0
    [71] PCIE_CRX_DTX_N4 PCIE4_RXN/USB31_4_RXN DV9 PCIE_RCOMPP RC100 1 2 100_0201_1%
    CU8 PCIE_RCOMP_P DT9 PCIE_RCOMPN
    [52] PCIE_CTX_DRX_P3 PCIE3_TXP/USB31_3_TXP PCIE_RCOMP_N
    [52] PCIE_CTX_DRX_N3 CU7
    NGFF WLAN+BT CT2 PCIE3_TXN/USB31_3_TXN DC12 USB2_VBUSSENSE RC354 1 2 10K_0201_1%
    [52] PCIE_CRX_DTX_P3 PCIE3_RXP/USB31_3_RXP USB_VBUSSENSE
    CT1 DF1 USB2_ID RC355 1 2 10K_0201_1%
    [52] PCIE_CRX_DTX_N3 PCIE3_RXN/USB31_3_RXN USB_ID DE1 USB2_COMP RC356 1 2 113_0201_1%
    CW8 USB2_COMP
    [71] USB3_CTX_DRX_P2 PCIE2_TXP/USB31_2_TXP
    CW7 E3 RSVD_BDCAN 1 T328
    [71] USB3_CTX_DRX_N2 PCIE2_TXN/USB31_2_TXN RSVD_BSCAN TP@
    USB2.0 / 3.0 Port (IO - 2) [71] USB3_CRX_DTX_P2 CU3
    CT4 PCIE2_RXP/USB31_2_RXP
    [71] USB3_CRX_DTX_N2 PCIE2_RXN/USB31_2_RXN +3VALW
    DA8 USB_OC0# Strap refer RVP
    [71] USB3_CTX_DRX_P1 PCIE1_TXP/USB31_1_TXP
    DA7 USB_OC0# RC401 1 2 10K_0201_5%
    [71] USB3_CTX_DRX_N1 PCIE1_TXN/USB31_1_TXN
    USB2.0 / 3.0 Port (IO - 1) [71] USB3_CRX_DTX_P1 CV2 USB_OC3# RC403 1 2 10K_0201_5%
    CV1 PCIE1_RXP/USB31_1_RXP
    [71] USB3_CRX_DTX_N1 PCIE1_RXN/USB31_1_RXN
    TGL-U_BGA1449 check list needs stuff even un-use
    @ +3VS

    NGFF_SSD_PEDET RC534 1 @ 2 10K_0201_5%

    B B

    UC1H
    P5 REV 1.6 V5
    [27] PCIE4_CTX_DRX_P3 PCIE4_TX_P_3 PCIE4_TX_P_1 PCIE4_CTX_DRX_P1 [27]
    P7 V7
    [27] PCIE4_CTX_DRX_N3 PCIE4_TX_N_3 PCIE4_TX_N_1 PCIE4_CTX_DRX_N1 [27]
    N1 T1
    [27] PCIE4_CRX_DTX_P3 PCIE4_RX_P_3 PCIE4_RX_P_1 PCIE4_CRX_DTX_P1 [27]
    N2 T2
    [27] PCIE4_CRX_DTX_N3 PCIE4_RX_N_3 PCIE4_RX_N_1 PCIE4_CRX_DTX_N1 [27]

    GPU T5 Y5 GPU
    [27] PCIE4_CTX_DRX_P2 PCIE4_TX_P_2 PCIE4_TX_P_0 PCIE4_CTX_DRX_P0 [27]
    T7 Y7
    [27] PCIE4_CTX_DRX_N2 PCIE4_TX_N_2 PCIE4_TX_N_0 PCIE4_CTX_DRX_N0 [27]
    R1 V1
    [27] PCIE4_CRX_DTX_P2 PCIE4_RX_P_2 PCIE4_RX_P_0 PCIE4_CRX_DTX_P0 [27]
    R2 V2
    [27] PCIE4_CRX_DTX_N2 PCIE4_RX_N_2 PCIE4_RX_N_0 PCIE4_CRX_DTX_N0 [27]
    Y12 PCIE4_RCOMPP RC188 1 2 2.2K_0201_1%
    PCIE4_RCOMP_P V12 PCIE4_RCOMPN
    PCIE4_RCOMP_N
    TGL-U_BGA1449
    @

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2019/11/27 Deciphered Date 2020/11/27 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    TGL-UP3(8/14)PCIE,USB,SATA
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 2.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K321P
    Date: Thursday, June 03, 2021 Sheet 13 of 121
    5 4 3 2 1
    5 4 3 2 1

    UC1J
    REV 1.6
    D22 DK47 CNV_CTX_DRX_P1 [52]
    B22 CSI_F_DP_1 CNVI_WT_D1P DM47
    CSI_F_DN_1 CNVI_WT_D1N CNV_CTX_DRX_N1 [52]
    E22 DN49 CNV_CTX_DRX_P0 [52]
    D20 CSI_F_DP_0 CNVI_WT_D0P DR49
    CSI_F_DN_0 CNVI_WT_D0N CNV_CTX_DRX_N0 [52]
    A20 DN45 CLK_CNV_CTX_DRX_P [52]
    B20 CSI_F_CLK_P CNVI_WT_CLKP DN47
    CSI_F_CLK_N CNVI_WT_CLKN CLK_CNV_CTX_DRX_N [52]
    B18 DU43
    CSI_E_DP_1/CSI_F_DP_2 CNVI_WR_D1P CNV_CRX_DTX_P1 [52]
    D A18 DV43 D
    CSI_E_DN_1/CSI_F_DN_2 CNVI_WR_D1N CNV_CRX_DTX_N1 [52]
    D18 DR44
    CSI_E_DP_0/CSI_F_DP_3 CNVI_WR_D0P CNV_CRX_DTX_P0 [52]
    E18 DT43
    CSI_E_DN_0/CSI_F_DN_3 CNVI_WR_D0N CNV_CRX_DTX_N0 [52]
    C16 DV44
    CSI_E_CLK_P CNVI_WR_CLKP CLK_CNV_CRX_DTX_P [52]
    D16 DW44
    CSI_E_CLK_N CNVI_WR_CLKN CLK_CNV_CRX_DTX_N [52]
    D15 DN51 CNV_WT_RCOMP RC109 1 2 150_0201_1%
    E15 CSI_C_DP_2 CNVI_WT_RCOMP
    A15 CSI_C_DN_2 DJ13
    CSI_C_DP_3 GPP_F3/CNV_RGI_RSP/UART0_CTS# CNV_RGI_CRX_DTX [52]
    B15 DG13 CNV_RGI_CTX_DRX [52]
    CSI_C_DN_3 GPP_F2/CNV_RGI_DT/UART0_TXD DF15
    GPP_F1/CNV_BRI_RSP/UART0_RXD CNV_BRI_CRX_DTX [52]
    L18 DF17 CNV_BRI_CTX_DRX [52]
    N18 CSI_C_DP_1 GPP_F0/CNV_BRI_DT/UART0_RTS#
    L20 CSI_C_DN_1 DJ10 SOC_GPP_F5 1
    CSI_C_DP_0 GPP_F5/MODEM_CLKREQ/CRF_XTAL_CLKREQ TP@ T53
    N20 DV15
    G20 CSI_C_DN_0 GPP_F6/CNV_PA_BLANKING DK10 SOC_GPP_F4
    H20 CSI_C_CLK_P GPP_F4/CNV_RF_RESET#
    CSI_C_CLK_N
    +1.8V_PRIM
    H16
    G16 CSI_B_DP_1
    G18 CSI_B_DN_1
    H18 CSI_B_DP_0 CNV_BRI_CRX_DTX RC181 1 @ 2 20K_0201_5%
    L16 CSI_B_DN_0
    CSI_B_CLK_P CNV_RGI_CRX_DTX RC182 1 @ 2 20K_0201_5%
    N16 Follow check list reserve
    CSI_B_CLK_N
    G14 CNV_RGI_CTX_DRX RC645 2 RMT@ 1 100K_0201_5%
    C
    H14 CSI_B_DP_2 C
    L14 CSI_B_DN_2
    N14 CSI_B_DP_3 +1.8V_PRIM
    CSI_B_DN_3
    RC357 1 2 150_0201_1% CSI_RCOMP K14
    CSI_RCOMP
    DK25
    CNV_RGI_CTX_DRX (M.2 CNVI MODES)
    GPP_H23/IMGCLKOUT4

    1
    DM25
    DN25 GPP_H22/IMGCLKOUT3 0 = Integrated CNVi enable. RC227
    DJ25 GPP_H21/IMGCLKOUT2 4.7K_0201_5%
    DR30 GPP_H20/IMGCLKOUT1 1 = Integrated CNVi disable. @
    GPP_D4/IMGCLKOUT_0/BK4/SBK4

    2
    NO INTERNAL PU/PD
    TGL-U_BGA1449
    @ CNV_BRI_CTX_DRX

    CNV_BRI_CTX_DRX (XTAL SEL)

    1
    RC644
    0 = 38.4/19.2MHZ (DEFAULT) 20K_0201_5%
    1 = 24MHZ (25 MHZ WHEN XTAL FREQ DIVIDER NON ZERO) @

    2
    WEAK INTERNAL PD 20K
    B B
    SOC_GPP_F4

    1
    RC627
    75K_0201_5%
    @

    2
    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2019/11/27 Deciphered Date 2020/11/27 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    TGL-UP3(9/14)CSI,CNV
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 2.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K321P
    Date: Thursday, June 03, 2021 Sheet 14 of 121
    5 4 3 2 1
    5 4 3 2 1

    +VCCIN +VCCIN

    D UC1M EMC CAPS-PLACE D


    REV 1.6
    A24
    VCCIN_1 VCCIN_66
    G32 < 5mm from SOC VCCIN
    A26 H24 +VCCIN
    A29 VCCIN_2 VCCIN_67 H26
    A30 VCCIN_3 VCCIN_68 H30
    A33 VCCIN_4 VCCIN_69 H32
    VCCIN_5 VCCIN_70

    0.1U_0201_10V6K
    CC375

    12P_0201_50V8J
    CC376

    100P_0201_50V8J
    CC377

    2.2P_0201_50V8C
    CC378
    A35 J1 1 1 1 1
    AY39 VCCIN_6 VCCIN_71 J2
    B24 VCCIN_7 VCCIN_72 K1
    B26 VCCIN_8 VCCIN_73 K2
    VCCIN_9 VCCIN_74 2 2 2 2

    EMI@

    EMI@

    EMI@
    B29 K24
    VCCIN_10 VCCIN_75 @
    B30 K26
    B33 VCCIN_11 VCCIN_76 K30
    B35 VCCIN_12 VCCIN_77 K32
    BA10 VCCIN_13 VCCIN_78 L24
    BA40 VCCIN_14 VCCIN_79 L26
    BB39 VCCIN_15 VCCIN_80 L30
    BB9 VCCIN_16 VCCIN_81 L32
    BC10 VCCIN_17 VCCIN_82 N24
    BC40 VCCIN_18 VCCIN_83 N26
    BD39 VCCIN_19 VCCIN_84 N30
    BD9 VCCIN_20 VCCIN_85 N32
    BE10 VCCIN_21 VCCIN_86 P24 +1.05V_VCCST
    BE40 VCCIN_22 VCCIN_87 P26
    BF9 VCCIN_23 VCCIN_88 P28
    VCCIN_24 VCCIN_89

    1
    C C
    BG10 P30
    BG40 VCCIN_25 VCCIN_90 P32 RC148
    BH12 VCCIN_26
    VCCIN_27
    VCCIN_91
    VCCIN_92
    T21 SVID DATA 100_0201_1%
    BH39 T23
    BH9 VCCIN_28 VCCIN_93 T25

    2
    BJ10 VCCIN_29 VCCIN_94 T27
    BJ40 VCCIN_30 VCCIN_95 T31 SOC_SVID_DAT RC362 1 @ 2 0_0201_5% SOC_SVID_DAT_R
    VCCIN_31 VCCIN_96 SOC_SVID_DAT_R [97]
    BK39 U23
    BL10 VCCIN_32 VCCIN_97 U27
    BL40 VCCIN_33 VCCIN_98 U29
    BM39 VCCIN_34 VCCIN_99 U31 +1.05V_VCCST
    BN40 VCCIN_35 VCCIN_100 U33
    BP12 VCCIN_36 VCCIN_101 V23
    VCCIN_37 VCCIN_102

    1
    BP39 V25
    BR10 VCCIN_38 VCCIN_103 V27 RC146
    BR40 VCCIN_39
    VCCIN_40
    VCCIN_104
    VCCIN_105
    V29 SVID ALERT 56_0201_1%
    BT12 V31
    BT39 VCCIN_41 VCCIN_106 V33

    2
    BU10 VCCIN_42 VCCIN_107 W22
    BU40 VCCIN_43 VCCIN_108 W24 SOC_SVID_ALERT# RC363 1 @ 2 0_0201_5% SOC_SVID_ALERT#_R
    VCCIN_44 VCCIN_109 SOC_SVID_ALERT#_R [97]
    BV12 W28
    BY12 VCCIN_45 VCCIN_110 W32
    CA10 VCCIN_46 VCCIN_111
    CB12 VCCIN_47 R38
    VCCIN_48 VCCIN_SENSE VCCIN_VCCSENSE [97] +1.05V_VCCST
    D24 R37
    VCCIN_49 VSSIN_SENSE VCCIN_VSSSENSE [97]
    B D26 B
    D29 VCCIN_50 M12 SOC_SVID_DAT
    D30 VCCIN_51 VIDSOUT M11 SOC_SVID_CLK
    VCCIN_52 VIDSCK

    1
    D33 P12 SOC_SVID_ALERT#
    D35 VCCIN_53
    VCCIN_54
    VIDALERT# SVID CLOCK RC147
    E24 100_0201_1%
    E26 VCCIN_55 @
    E27 VCCIN_56

    2
    E29 VCCIN_57
    E30 VCCIN_58 SOC_SVID_CLK RC364 1 @ 2 0_0201_5% SOC_SVID_CLK_R
    VCCIN_59 SOC_SVID_CLK_R [97]
    E32
    E33 VCCIN_60
    G2 VCCIN_61
    G24 VCCIN_62
    G26 VCCIN_63
    G30 VCCIN_64
    VCCIN_65

    www.teknisi-indonesia.com
    TGL-U_BGA1449
    @

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2019/11/27 Deciphered Date 2020/11/27 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    TGL-UP3(10/14)Power, SVID
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 2.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K321P
    Date: Thursday, June 03, 2021 Sheet 15 of 121
    5 4 3 2 1
    5 4 3 2 1

    +1.05VS_VCCSTG_OUT_FUSE
    EMC CAPS-PLACE +1.2V UC1O
    REV 1.6 +1.05VS_VCCSTG_FUSE
    < 4mm from SOC VDDQ AF9
    +1.05VS_VCCSTG_OUT_FUSE +1.05VS_VCCSTG_FUSE
    +1.2V +1.2V +1.2V VCCSTG_OUT_1
    with each pair < 12mm Apart AA39
    AB40 VDD2_1 VCCSTG_1
    AF12
    AD12 +VCCFPGM
    VDD2_2 VCCSTG_2 RC239 1 @ 2 0_0402_5%
    12pF* 3 (EMI@) AC39
    AD40 VDD2_3 AN10 +VCCFPGM

    2.2P_0201_50V8C
    CC218

    12P_0201_50V8J
    CC219

    2.2P_0201_50V8C
    CC220

    12P_0201_50V8J
    CC221

    2.2P_0201_50V8C
    CC222

    12P_0201_50V8J
    CC223
    VDD2_4 VCCSTG_OUT_2
    2.2pF* 3 (EMI@) AD51
    AD52 VDD2_5 VCCSTG_OUT_3
    AM9
    AG10 +1.05V_VCCIO_OUT
    1 1 1 1 1 1 VDD2_6 VCCSTG_OUT_4 RC240 1 @ 2 0_0402_5%
    AE39 +1.05VS_VCCSTG_OUT_LGC
    AF40 VDD2_7 V15 1
    VDD2_8 VCCIO_OUT TP@ T60
    AG39

    EMI@

    EMI@

    EMI@

    EMI@

    EMI@

    EMI@
    2 2 2 2 2 2 AH40 VDD2_9 M9 +1.05V_VCCST
    D D
    AJ39 VDD2_10 VCCSTG_OUT_LGC
    VDD2_11
    AK40
    AK51 VDD2_12 VCCST_1
    BT2
    BT1 +1.8VALW TO +1.8V_PRIM
    AK52 VDD2_13 VCCST_2 BT4 +1.05VS_VCCSTG
    AL39 VDD2_14 VCCST_3
    AM40 VDD2_15 BP2
    VDD2_16 VCCSTG_3 +1.8VALW +1.8V_PRIM
    AN39 BP1
    AP40 VDD2_17 VCCSTG_4 BP4
    VDD2_18 VCCSTG_5 RC243 1 @ 2 0_0603_5%
    AR39
    AT52 VDD2_19
    AU40 VDD2_20 1
    AW40 VDD2_21 CC753
    VDD2_22 4.7U_0402_6.3V6M
    AW51
    AW52 VDD2_23
    VDD2_24 2
    BD51
    BD52 VDD2_25
    BK51 VDD2_26
    BK52 VDD2_27
    BV51 VDD2_28
    BV52 VDD2_29
    CA40 VDD2_30
    CC40 VDD2_31
    +1.05VO_OUT_FET +1.05V_VCCST VDD2_32
    CC49
    CC50 VDD2_33
    CE40 VDD2_34
    +1.05V_VCCST_R RC622 1 @ 2 0_0402_5% VDD2_35 +1.05V_VCCST +1.05VS_VCCSTG +1.05VS_VCCSTG_OUT_FUSE +1.05VS_VCCSTG_FUSE +VCCFPGM
    CG40
    CH39 VDD2_36
    1U_0201_6.3V6M
    CC750

    Imax : 0.445 A 1 Imax : 0.445 A 1 CJ40 VDD2_37


    CC60 VDD2_38
    VCCST CL40

    1U_0201_6.3V6M
    CC52

    1U_0201_6.3V6M
    CC53

    1U_0201_6.3V6M
    CC54

    1U_0201_6.3V6M
    CC55

    1U_0201_6.3V6M
    CC29

    1U_0201_6.3V6M
    CC56

    1U_0201_6.3V6M
    CC57
    0.1U_0201_10V6K VDD2_39 1 1 1 1 1 1 1
    CN40
    CP47 VDD2_40
    2 2 VDD2_41
    +5VALW CR40
    UC5 VDD2_42
    D50 2 @2 2 @2 @ 2 @2 @2
    1 10 0 for 65us VDD2_43
    IN1 OUT1 E51
    CC58 F49 VDD2_44
    0.1U_0201_10V6K VCCST_EN_LS 2 9 CC62 1 @ 2 1000P_0402_50V7K VDD2_45
    EN1 CT1 +1.05VS_VCCSTG T51
    2 1 @ 3 8 VDD2_46
    VCCSTG_EN_LS VBIAS GND T52
    4 7 CC63 1 @ 2 1000P_0402_50V7K VDD2_47
    EN2 CT2
    C C
    5 6 +1.05VS_VCCSTG_R RC619 1 @ 2 0_0402_5%
    IN2 OUT2 TGL-U_BGA1449
    11 @
    Imax : 0.119 A 1
    +1.05VO_OUT_FET GND PAD CC61
    0.1U_0201_10V6K
    G2894KD1U TDFN2X3_14
    2
    SA0000D5C00
    1U_0201_6.3V6M
    CC59

    VCCSTG
    2
    RDS(on) = 20mΩ at VIN = 1.05V (VBIAS = 5V)
    10μs <= EN asserted to VOUT stable <= 65μs Place on CPU Side
    CPU_C10_GATE# stable to +1.05VS_VCCSTG <= 65us (tCPU26)
    +1.2V +1.2V +1.2V

    Close to UC5

    1U_0201_6.3V6M
    CC70

    1U_0201_6.3V6M
    CC401

    10U_0402_6.3V6M

    10U_0402_6.3V6M

    10U_0402_6.3V6M
    1U_0201_6.3V6M
    CC68

    1U_0201_6.3V6M
    CC69

    1U_0201_6.3V6M
    CC71

    10U_0402_6.3V6M

    10U_0402_6.3V6M

    10U_0402_6.3V6M

    10U_0402_6.3V6M

    10U_0402_6.3V6M

    10U_0402_6.3V6M

    10U_0402_6.3V6M

    10U_0402_6.3V6M

    10U_0402_6.3V6M
    1U_0201_6.3V6M
    CC67

    1U_0201_6.3V6M
    CC72

    1U_0201_6.3V6M
    CC73

    1U_0201_6.3V6M
    CC74

    1U_0201_6.3V6M
    CC75

    10U_0402_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M
    1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
    +1.05V_VCCST +1.05VS_VCCSTG

    CC403

    CC404

    CC405
    CC77

    CC79

    CC80

    CC81

    CC409

    CC410

    CC411

    CC402

    CC92
    CC408

    CC78

    CC407

    CC93

    CC94
    1 1 @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @
    CC754 CC755 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
    0.1U_0201_10V6K 0.1U_0201_10V6K
    @RF@ @RF@
    2 2

    B
    VCCST/VCCSTG Enable B

    PM_SLP_S3# RC304 1 2 0_0201_5%


    [11,58,66] PM_SLP_S3#
    DC7
    SUSP# RC303 1 @ 2 0_0201_5% 2
    [58,78,111] SUSP# 1 VCCST_EN_LS
    3

    LRB715FT1G_SOT323-3

    VCCST_OVERRIDE_LS RC340 1 @ 2 0_0201_5%


    [11] VCCST_OVERRIDE_LS

    DC8
    2
    1 VCCSTG_EN_LS
    CPU_C10_GATE# RC331 1 @ 2 0_0201_5% 3
    [11] CPU_C10_GATE#
    LRB715FT1G_SOT323-3

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2019/11/27 Deciphered Date 2020/11/27 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    TGL-UP3(11/14)Power
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 2.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K321P
    Date: Thursday, June 03, 2021 Sheet 16 of 121
    5 4 3 2 1
    5 4 3 2 1

    Package size?
    +3VALW +3VALW_DSW +3VALW TO +3V_PRIM +3V_PRIM +3V_PRIM_SOC +3V_PRIM +3.3V_VCCPGPPR EMC CAPS-PLACE
    RC217 1 @ 2 0_0402_5% RC608 1 @ 2 0_0402_5%
    < 5mm from SOC VCCIN_AUX
    RC216 1 @ 2 0_0402_5% +3VALW +3V_PRIM
    1354mA +VCCIN_AUX
    RC643 1 @ 2 0_0402_5% 1
    +1.8V_PRIM +1.8V_PRIM_MCP CC168
    1 4.7U_0402_6.3V6M

    0.1U_0201_10V6K
    CC99

    12P_0201_50V8J
    CC98

    100P_0201_50V8J
    CC100

    2.2P_0201_50V8C
    CC97
    2 1 1 1 1
    CC101
    D
    RC219 1 @ 2 0_0402_5% 4.7U_0402_6.3V6M D
    2
    2 2 2 2

    EMI@

    EMI@

    EMI@
    @

    +1.8V_PRIM_MCP +1.8V_VCCA_CLKLDO

    RC218 1 @ 2 0_0402_5%
    CC741
    22U_0603_6.3V6K

    CC246
    22U_0603_6.3V6K

    1 1
    +VCCIN_AUX +1.8V_PRIM_MCP
    UC1N
    @ REV 1.6
    2 2
    AB12 CY18
    AC10 VCCIN_AUX_1 VCCPRIM_1P8_1 CY20
    AE10 VCCIN_AUX_2 VCCPRIM_1P8_2 CY24
    AK2 VCCIN_AUX_3 VCCPRIM_1P8_3 CY26
    AR10 VCCIN_AUX_4 VCCPRIM_1P8_4 DA18
    AT12 VCCIN_AUX_5 VCCPRIM_1P8_5 DA20
    AU10 VCCIN_AUX_6 VCCPRIM_1P8_6 DA22
    AW10 VCCIN_AUX_7 VCCPRIM_1P8_7 DA24
    BV1 VCCIN_AUX_8 VCCPRIM_1P8_8 DA26
    BV39 VCCIN_AUX_9 VCCPRIM_1P8_9 DC18
    BW40 VCCIN_AUX_10 VCCPRIM_1P8_10 DC20
    BY39 VCCIN_AUX_11 VCCPRIM_1P8_11 DC22
    CC1 VCCIN_AUX_12 VCCPRIM_1P8_12 DC24
    CD12 VCCIN_AUX_13 VCCPRIM_1P8_13 DC26
    CF10 VCCIN_AUX_14 VCCPRIM_1P8_14 DD20
    CG12 VCCIN_AUX_15 VCCPRIM_1P8_15 DD22
    +1.05VO_VNNBYPASS CH10 VCCIN_AUX_16 VCCPRIM_1P8_16 DV22 +3V_PRIM_SOC
    CJ1 VCCIN_AUX_17 VCCPRIM_1P8_17
    CJ12 VCCIN_AUX_18 DA35 +VO_VCCDCPRTC
    C C
    CK10 VCCIN_AUX_19 VCCPRIM_3P3_1 DC28
    +1.05VO_EXTBYPASS CL12 VCCIN_AUX_20 VCCPRIM_3P3_2 DC30
    VCCIN_AUX_21 VCCPRIM_3P3_3

    RC601
    100K_0201_5%
    CM10 DD30
    VCCIN_AUX_22 VCCPRIM_3P3_4
    1
    CP1 +0.85VO_VCCLDOSTD
    CP10 VCCIN_AUX_23 DV34
    CR12 VCCIN_AUX_24 DCPRTC
    @ CT10 VCCIN_AUX_25 DV46 +1.8V_VCCA_CLKLDO
    VCCIN_AUX_26 VCCLDOSTD_0P85
    RC600
    100K_0201_5%

    CU12
    2

    VCCIN_AUX_27
    1

    CY1 DV16 +1.24VO_VCCDPHY


    AK1 VCCIN_AUX_28 VCCA_CLKLDO_1P8_1 DC15
    VCCIN_AUX_29 VCCA_CLKLDO_1P8_2 +1.05VO_VCCDSW
    @ AV9 DV28
    [95] VCCIN_AUX_VSSSENSE AT9 VCCIN_AUX_VSSSENSE VCCDPHY_1P24
    [95] VCCIN_AUX_VCCSENSE
    2

    VCCIN_AUX_VCCSENSE DD38 +1.05VO_OUT_FET


    DD17 VCCDSW_1P05
    DD18 VCC_VNNEXT_1P05_1 BR3
    VCC_VNNEXT_1P05_2 VCC1P05_OUT_FET BR4
    DA15 VCC1P05_OUT_FET BT5 +1.05VO_OUT_PCH
    DA17 VCC_V1P05EXT_1P05_1 VCC1P05_OUT_FET
    VCC_V1P05EXT_1P05_2 DA31 +3VL_RTC
    RC222 1 @ 2 0_0201_5% VCCIN_AUX_CORE_ALERT# DB39 VCCPRIM_1P05_1 DC33
    [7] VCCIN_AUX_CORE_ALERT#_R VNN_CTRL GPP_B2/VRALERT# VCCPRIM_1P05_2
    1 DV12 DC31 +3VALW_DSW
    T194 TP@ 1 V1.05P_CTRL DT12 GPP_F22/VNN_CTRL VCCPRIM_1P05_3
    T195 TP@ GPP_F23/V1P05_CTRL DC35 +3.3V_VCCPGPPR
    RC223 1 @ 2 0_0201_5% VCCIN_AUX_CORE_VID0 DB37 VCCRTC DD37
    [95] VCCIN_AUX_CORE_VID0_R GPP_B0/CORE_VID0 VCCDSW_3P3
    [95] VCCIN_AUX_CORE_VID1_R RC224 1 @ 2 0_0201_5% VCCIN_AUX_CORE_VID1 DB38 DA28 +3V_PRIM_SOC
    GPP_B1/CORE_VID1 VCCPGPPR ?
    CY31
    ? +1.8V_PRIM_MCP
    VCCPRIM_3P3_5 CY33
    VCCPRIM_3P3_6 CV39 +VCCANA_EHV
    VCCPRIM_1P8_18
    AP12 1 TP@T84
    RSVD_1
    TGL-U_BGA1449
    B
    @ B

    NOTE:
    576591-tgl-pch-lp-eds-vol1of2-rev0p5
    VCCPGPPR: Audio Power 3.3V, 1.8V, or 1.5V
    Need to sync with codec VDDIO.
    607872_TGL_UY_PDG_Rev0p5
    When configured as 3.3V or 1.8V, VCCPGPPR can be merged directly with
    either VCCPRIM_1P8 or VCCPRIM_3P3 depending on their operating voltage.

    +3VALW_DSW +1.05VO_VCCDSW +0.85VO_VCCLDOSTD +1.8V_PRIM_MCP +3V_PRIM_SOC +1.24VO_VCCDPHY +VO_VCCDCPRTC


    +RTCBATT +3VL_RTC
    W=20mils
    1U_0201_6.3V6M
    CC742

    1U_0201_6.3V6M
    CC745

    1U_0201_6.3V6M
    CC743

    0.1U_0201_10V6K
    CC749
    2.2U_0402_6.3V6M
    CC747

    1 1 1
    4.7U_0402_6.3V6M
    CC746
    1

    1U_0201_6.3V6M
    CC744
    0.1U_0201_10V6K
    CC748

    1
    1

    RC141 2 @ 1 0_0402_5%
    2

    2 2 2

    1U_0201_6.3V6M
    CC258

    0.1U_0201_10V6K
    CC129
    1 1
    2

    @ 2
    @

    2 2

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2019/11/27 Deciphered Date 2020/11/27 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    TGL-UP3(12/14)Power
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K321P
    Date: Thursday, June 03, 2021 Sheet 17 of 121
    5 4 3 2 1
    5 4 3 2 1

    UC1R
    UC1P
    REV 1.6
    UC1Q REV 1.6
    REV 1.6 DP53 K34
    A27 B19 VSS_2 VSS_46
    VSS_223 VSS_289 BY44 CY44 DR11 K48
    A32 B2 VSS_109 VSS_169 VSS_3 VSS_47
    D VSS_224 VSS_290 BY45 CY45 DR16 K5 D
    A45 B23 VSS_110 VSS_170 VSS_4 VSS_48
    VSS_225 VSS_291 BY47 CY47 DR22 L22
    A49 B27 VSS_111 VSS_171 VSS_5 VSS_49
    VSS_226 VSS_292 BY49 CY5 DR28 L28
    AA41 B32 VSS_112 VSS_172 VSS_6 VSS_50
    VSS_227 VSS_293 BY9 D27 DR34 L34
    AA48 B36 VSS_113 VSS_173 VSS_7 VSS_51
    VSS_228 VSS_294 C13 D32 DR40 L39
    AB5 B39 VSS_114 VSS_174 VSS_8 VSS_52
    VSS_229 VSS_295 C19 D36 DR46 L41
    AB7 B42 VSS_115 VSS_175 VSS_9 VSS_53
    VSS_230 VSS_296 C23 D42 DT4 L42
    AB8 B48 VSS_116 VSS_176 VSS_10 VSS_54
    VSS_231 VSS_297 CA48 D49 DT50 L44
    AC44 B52 VSS_117 VSS_177 VSS_11 VSS_55
    VSS_232 VSS_298 CB41 D5 DU11 L45
    AC49 B8 VSS_118 VSS_178 VSS_12 VSS_56
    VSS_233 VSS_299 CC10 DA30 DU16 L47
    AD4 BA48 VSS_119 VSS_179 VSS_13 VSS_57
    VSS_234 VSS_300 CC3 DA33 DU22 L49
    AD48 BA53 VSS_120 VSS_180 VSS_14 VSS_58
    VSS_235 VSS_301 CC5 DA53 DU28 M1
    AD8 BB4 VSS_121 VSS_181 VSS_15 VSS_59
    VSS_236 VSS_302 CD44 DC17 DU34 M2
    AF4 BB8 VSS_122 VSS_182 VSS_16 VSS_60
    VSS_237 VSS_303 CD48 DD15 DU40 M50
    AF8 BC1 VSS_123 VSS_183 VSS_17 VSS_61
    VSS_238 VSS_304 CD7 DD24 DU46 N22
    AG41 BC2 VSS_124 VSS_184 VSS_18 VSS_62
    VSS_239 VSS_305 CE49 DD26 DV1 N28
    AG42 BD12 VSS_125 VSS_185 VSS_19 VSS_63
    VSS_240 VSS_306 CG48 DD28 DV40 N34
    AG44 BD4 VSS_126 VSS_186 VSS_20 VSS_64
    VSS_241 VSS_307 CG51 DD31 DV52 N39
    AG45 BD48 VSS_127 VSS_187 VSS_21 VSS_65
    VSS_242 VSS_308 CG52 DD33 DW51 N41
    AG47 BD8 VSS_128 VSS_188 VSS_22 VSS_66
    VSS_243 VSS_309 CG9 DD35 E13 N48
    AG48 BF39 VSS_129 VSS_189 VSS_23 VSS_67
    VSS_244 VSS_310 CH41 DD39 E19 P11
    AG53 BF4 VSS_130 VSS_190 VSS_24 VSS_68
    VSS_245 VSS_311 CH42 DD45 E35 P14
    AH4 BF41 VSS_131 VSS_191 VSS_25 VSS_69
    VSS_246 VSS_312 CH44 DD51 E48 P16
    AH8 BF42 VSS_132 VSS_192 VSS_26 VSS_70
    VSS_247 VSS_313 CH45 DD52 G22 P18
    AK12 BF44 VSS_133 VSS_193 VSS_27 VSS_71
    VSS_248 VSS_314 CH47 DE3 G28 P20
    AK4 BF45 VSS_134 VSS_194 VSS_28 VSS_72
    VSS_249 VSS_315 CJ3 DE5 G34 P22
    AK48 BF47 VSS_135 VSS_195 VSS_29 VSS_73
    VSS_250 VSS_316 CJ5 DF19 G39 P33
    AK5 BF5 VSS_136 VSS_196 VSS_30 VSS_74
    VSS_251 VSS_317 CJ9 DF37 G48 P35
    AK7 BF7 VSS_137 VSS_197 VSS_31 VSS_75
    VSS_252 VSS_318 CK39 DG15 G51 P4
    AK8 BF8 VSS_138 VSS_198 VSS_32 VSS_76
    C VSS_253 VSS_319 CK48 DG21 G52 P49 C
    AM1 BG48 VSS_139 VSS_199 VSS_33 VSS_77
    VSS_254 VSS_320 CK53 DG27 H12 P8
    AM2 BG53 VSS_140 VSS_200 VSS_34 VSS_78
    VSS_255 VSS_321 CL9 DG33 H22 R39
    AM4 BH1 VSS_141 VSS_201 VSS_35 VSS_79
    VSS_256 VSS_322 CN12 DG39 H28 R44
    AM8 BH2 VSS_142 VSS_202 VSS_36 VSS_80
    VSS_257 VSS_323 CN48 DG45 H34 T19
    AN41 BH4 VSS_143 VSS_203 VSS_37 VSS_81
    VSS_258 VSS_324 CN51 DG5 H8 T29
    AN42 BH8 VSS_144 VSS_204 VSS_38 VSS_82
    VSS_259 VSS_325 CN52 DG53 J39 T33
    AN44 BK12 VSS_145 VSS_205 VSS_39 VSS_83
    VSS_260 VSS_326 CN9 DG6 J49 T4
    AN45 BK4 VSS_146 VSS_206 VSS_40 VSS_84
    VSS_261 VSS_327 CP3 DJ1 K16 T48
    AN47 BK48 VSS_147 VSS_207 VSS_41 VSS_85
    VSS_262 VSS_328 CP41 DJ2 K18 T8
    AN48 BK8 VSS_148 VSS_208 VSS_42 VSS_86
    VSS_263 VSS_329 CP42 DJ4 K20 U19
    AN53 BL49 VSS_149 VSS_209 VSS_43 VSS_87
    VSS_264 VSS_330 CP44 DK51 K22 U25
    AP4 BM1 VSS_150 VSS_210 VSS_44 VSS_88
    VSS_265 VSS_331 CP45 DL3 K28 U39
    AP8 BM4 VSS_151 VSS_211 VSS_45 VSS_89
    VSS_266 VSS_332 CP5 DL5 U49
    AT4 BM41 VSS_152 VSS_212 VSS_90
    VSS_267 VSS_333 CR48 DM10 V19
    Follow AT48 BM42 VSS_153 VSS_213 VSS_91
    VSS_268 VSS_334 CR53 DM15 V4
    612304_TGL_UP3_LPDDR4x_RVP_TDK_Rev0p7 AT51 BM44 VSS_154 VSS_214 VSS_92
    VSS_269 VSS_335 CR9 DM21 V8
    AT8 BM45 VSS_155 VSS_215 VSS_93
    VSS_270 VSS_336 CT5 DM27 W1
    T85 TP@ 1 AV12 BM47 VSS_156 VSS_216 VSS_94
    VSS_271 VSS_337 CU4 DM33 W16
    AV39 BM8 VSS_157 VSS_217 VSS_95
    VSS_272 VSS_338 CU9 DM39 W26
    AV4 BN48 VSS_158 VSS_218 VSS_96
    VSS_273 VSS_339 CV10 DM4 W30
    AV5 BP41 VSS_159 VSS_219 VSS_97
    VSS_274 VSS_340 CV48 DM45 W39
    AV7 BP49 VSS_160 VSS_220 VSS_98
    VSS_275 VSS_341 CV5 DN1 W41
    AV8 BP5 VSS_161 VSS_221 VSS_99
    VSS_276 VSS_342 CV51 DN2 W42
    AW1 BP50 VSS_162 VSS_222 VSS_100
    VSS_277 VSS_343 CV52 W44
    AW2 BP7 VSS_163 VSS_101
    VSS_278 VSS_344 CY17 W45
    AW48 BT44 VSS_164 VSS_102
    VSS_279 VSS_345 CY22 W47
    AY4 BT48 VSS_165 VSS_103
    VSS_280 VSS_346 CY35 W48
    AY41 BU49 VSS_166 VSS_104
    VSS_281 VSS_347 CY41 Y4
    B AY42 BV3 VSS_167 VSS_105 B
    VSS_282 VSS_348 CY42 Y49
    AY44 BV48 VSS_168 VSS_106
    VSS_283 VSS_349 Y50
    AY45 BV5 VSS_107
    VSS_284 VSS_350 Y8
    AY47 BW10 VSS_108
    VSS_285 VSS_351 TGL-U_BGA1449
    AY8 BY41
    VSS_286 VSS_352 @
    AY9 BY42
    VSS_287 VSS_353 TGL-U_BGA1449
    B13
    VSS_288 @

    TGL-U_BGA1449
    @

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2019/11/27 Deciphered Date 2020/11/27 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    TGL-UP3(13/14)GND
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 2.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K321P
    Date: Thursday, June 03, 2021 Sheet 18 of 121
    5 4 3 2 1
    5 4 3 2 1

    UC1T
    REV 1.6
    T15 A51
    CFG14 V17 CFG_15 RSVD_TP_7 B51
    U15 CFG_14 RSVD_TP_8
    D K11 CFG_13 C1 D
    CFG11 K12 CFG_12 RSVD_TP_9 D2
    CFG10 K9 CFG_11 RSVD_TP_10
    CFG9 T17 CFG_10 CP39
    K7 CFG_9 RSVD_TP_11 CU40
    CFG7 H7 CFG_8 RSVD_TP_12 AK9
    K8 CFG_7 RSVD_12
    H9 CFG_6 AH9
    CFG Signals CFG_5 RSVD_13
    CFG4 E6
    (For Strap & XDP) CFG3 H5 CFG_4 DW6
    CFG2 E9 CFG_3 RSVD_14 DV6
    CFG1 D9 CFG_2 RSVD_15
    E7 CFG_1 DV4
    +1.05V_VCCIO_OUT CFG_0 RSVD_TP_13 DW3
    CFG_RCOMP B5 RSVD_TP_14
    CFG_RCOMP DU1
    RSVD_TP_15

    1
    RC229 1 @ 2 10K_0201_5% BPM#0 U17 DT2
    RC230 1 @ 2 10K_0201_5% BPM#1 RC228 H11 CFG_17 RSVD_TP_16
    RC231 1 @ 2 10K_0201_5% BPM#2 49.9_0201_1% CFG_16 DW2
    RC232 1 @ 2 10K_0201_5% BPM#3 BPM#3 Y1 RSVD_TP_17 DV2
    BPM#2 M4 BPM#_3 RSVD_TP_18

    2
    BPM#1 AB4 BPM#_2 E1
    RC233 1 2 1K_0201_5% CFG4 BPM#0 Y2 BPM#_1 RSVD_TP_19 F1
    BPM#_0 RSVD_TP_20
    A3 AB2
    B3 RSVD_6 RSVD_16
    CFG4 RSVD_7
    Display port presence strap DR1
    TCSS_RCOMP AR2 RSVD_TP_21 DR2
    LOW : Enable TCP0_MBIAS_RCOMP RSVD_TP_22
    An external display port device is connected to AL10
    C RSVD_TP_2 C

    1
    AM12 DR53
    the embedded displayport RC335 AH12 RSVD_TP_3 RSVD_TP_23 DW5
    HIGH : Disable AJ10 RSVD_TP_4 RSVD_TP_24
    2.2K_0201_1% RSVD_TP_5
    No physical display port attached to embedded display port AR1 DV51
    RSVD_TP_6 VSS_1 DW52

    2
    BN10 TP_3 DV53
    BM12 RSVD_8 TP_4 W34
    DD13 RSVD_9 RSVD_17 V35
    DF13 RSVD_10 RSVD_18
    +1.05V_VCCIO_OUT RSVD_11 D52 SKTOCC# 1
    SKTOCC# TP@ T112

    RC250 1 2 1K_0201_5% CFG1 TGL-U_BGA1449


    RC251 1 2 1K_0201_5% CFG2 @
    RC252 1 2 1K_0201_5% CFG3
    RC259 1 @ 2 10K_0201_5% CFG7
    RC262 1 2 1K_0201_5% CFG9
    RC264 1 2 1K_0201_5% CFG10
    UC1S
    RC266 1 2 1K_0201_5% CFG11 REV 1.6
    RC271 1 @ 2 10K_0201_5% CFG14
    DF53 C53
    RSVD_19 RSVD_23 T35
    RC642 1 @ 2 10K_0201_5% CFG7 DF52 RSVD_24 E53
    RC647 1 @ 2 10K_0201_5% CFG14 RSVD_20 RSVD_25 CF39
    DT52 RSVD_26 U35

    www.teknisi-indonesia.com
    DU53 PCH_IST_TP_1 RSVD_27 F53
    PCH_IST_TP_0 RSVD_28 B53
    DF50 RSVD_29 AP9
    DF49 RSVD_21 RSVD_30 A52
    B RSVD_22 RSVD_31 B
    CY30 BF12
    1 +1.8V_PRIM_FIVR1 CY15 RSVD_TP_25 RSVD_TP_28 V21
    T466 TP@ RSVD_TP_26 RSVD_TP_29 W20
    D4 RSVD_TP_30 U37
    RSVD_TP_27 RSVD_TP_31 CD39
    A6 RSVD_TP_32 U21
    A4 IST_TP_1 RSVD_TP_33 CB39
    IST_TP_0 RSVD_32 BB12
    RSVD_TP_34 W37
    RSVD_TP_35 AY12
    RSVD_TP_36 W38
    RSVD_TP_37 U38
    RSVD_TP_38 CY28 +1.8V_PRIM_FIVR2 1
    RSVD_TP_39 TP@ T465

    TGL-U_BGA1449
    @

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2019/11/27 Deciphered Date 2020/11/27 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    TGL-UP3(14/14)RSVD,CFG
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 2.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K321P
    Date: Thursday, June 03, 2021 Sheet 19 of 121
    5 4 3 2 1
    5 4 3 2 1

    D D

    C C

    B B

    A A

    Security Classification
    2019/11/27
    Compal Secret Data
    2020/11/27 Title
    Compal Electronics, Inc.
    Issued Date Deciphered Date
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Reserve
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 2.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K321P
    Date: Thursday, June 03, 2021 Sheet 20 of 121
    5 4 3 2 1
    5 4 3 2 1

    D D

    C C

    B B

    A A

    Security Classification
    2019/11/27
    Compal Secret Data
    2020/11/27 Title
    Compal Electronics, Inc.
    Issued Date Deciphered Date
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Reserve
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 2.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K321P
    Date: Thursday, June 03, 2021 Sheet 21 of 121
    5 4 3 2 1
    5 4 3 2 1

    D D

    C C

    B B

    A A

    Security Classification
    2019/11/27
    Compal Secret Data
    2020/11/27 Title
    Compal Electronics, Inc.
    Issued Date Deciphered Date
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Reserve
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 2.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K321P
    Date: Thursday, June 03, 2021 Sheet 22 of 121
    5 4 3 2 1
    5 4 3 2 1

    +DDR_VREF_CA +DDR_VREF_CA +DDR_VREF_CA +DDR_VREF_CA

    UD1 UD2 UD3 UD4

    M1 G2 DDR_A_D21 M1 G2 DDR_A_D5 M1 G2 DDR_A_D38 M1 G2 DDR_A_D60


    VREFCA DQL0 F7 DDR_A_D20 VREFCA DQL0 F7 DDR_A_D3 VREFCA DQL0 F7 DDR_A_D36 VREFCA DQL0 F7 DDR_A_D56
    DQL1 H3 DDR_A_D23 DQL1 H3 DDR_A_D6 DQL1 H3 DDR_A_D33 DQL1 H3 DDR_A_D62
    DQL2 DQL2 DQL2 DQL2
    .047U_0402_16V7K

    DDR_A_MA0 DDR_A_D16

    .047U_0402_16V7K
    DDR_A_MA0 DDR_A_D1

    .047U_0402_16V7K
    DDR_A_MA0 DDR_A_D32

    .047U_0402_16V7K
    P3 H7 P3 H7 P3 H7 DDR_A_MA0 P3 H7 DDR_A_D61
    1 A0 DQL3 1 A0 DQL3 1 A0 DQL3 1 A0 DQL3
    DDR_A_MA1 DDR_A_D17 DDR_A_MA1 DDR_A_D7 DDR_A_MA1 DDR_A_D39 DDR_A_MA1 DDR_A_D59
    CD1

    CD2

    CD3

    CD4
    P7 H2 P7 H2 P7 H2 P7 H2
    DDR_A_MA2 R3 A1 DQL4 H8 DDR_A_D18 DDR_A_MA2 R3 A1 DQL4 H8 DDR_A_D0 DDR_A_MA2 R3 A1 DQL4 H8 DDR_A_D34 DDR_A_MA2 R3 A1 DQL4 H8 DDR_A_D57
    DDR_A_MA3 N7 A2 DQL5 J3 DDR_A_D19 DDR_A_MA3 N7 A2 DQL5 J3 DDR_A_D4 DDR_A_MA3 N7 A2 DQL5 J3 DDR_A_D37 DDR_A_MA3 N7 A2 DQL5 J3 DDR_A_D58
    2 DDR_A_MA4 N3 A3 DQL6 J7 DDR_A_D22 2 DDR_A_MA4 N3 A3 DQL6 J7 DDR_A_D2 2 DDR_A_MA4 N3 A3 DQL6 J7 DDR_A_D35 2 DDR_A_MA4 N3 A3 DQL6 J7 DDR_A_D63
    D DDR_A_MA5 P8 A4 DQL7 DDR_A_MA5 P8 A4 DQL7 DDR_A_MA5 P8 A4 DQL7 DDR_A_MA5 P8 A4 DQL7 D
    DDR_A_MA6 P2 A5 DDR_A_MA6 P2 A5 DDR_A_MA6 P2 A5 DDR_A_MA6 P2 A5
    DDR_A_MA7 R8 A6 A3 DDR_A_D27 DDR_A_MA7 R8 A6 A3 DDR_A_D14 DDR_A_MA7 R8 A6 A3 DDR_A_D51 DDR_A_MA7 R8 A6 A3 DDR_A_D46
    DDR_A_MA8 R2 A7 DQU0 B8 DDR_A_D28 DDR_A_MA8 R2 A7 DQU0 B8 DDR_A_D10 DDR_A_MA8 R2 A7 DQU0 B8 DDR_A_D50 DDR_A_MA8 R2 A7 DQU0 B8 DDR_A_D42
    DDR_A_MA9 R7 A8 DQU1 C3 DDR_A_D31 DDR_A_MA9 R7 A8 DQU1 C3 DDR_A_D13 DDR_A_MA9 R7 A8 DQU1 C3 DDR_A_D52 DDR_A_MA9 R7 A8 DQU1 C3 DDR_A_D45
    DDR_A_MA10 M3 A9 DQU2 C7 DDR_A_D26 DDR_A_MA10 M3 A9 DQU2 C7 DDR_A_D8 DDR_A_MA10 M3 A9 DQU2 C7 DDR_A_D55 DDR_A_MA10 M3 A9 DQU2 C7 DDR_A_D41
    DDR_A_MA11 T2 A10/AP DQU3 C2 DDR_A_D24 DDR_A_MA11 T2 A10/AP DQU3 C2 DDR_A_D12 DDR_A_MA11 T2 A10/AP DQU3 C2 DDR_A_D48 DDR_A_MA11 T2 A10/AP DQU3 C2 DDR_A_D44
    DDR_A_MA12 M7 A11 DQU4 C8 DDR_A_D25 DDR_A_MA12 M7 A11 DQU4 C8 DDR_A_D9 DDR_A_MA12 M7 A11 DQU4 C8 DDR_A_D49 DDR_A_MA12 M7 A11 DQU4 C8 DDR_A_D43
    DDR_A_MA13 T8 A12/BC DQU5 D3 DDR_A_D29 DDR_A_MA13 T8 A12/BC DQU5 D3 DDR_A_D15 DDR_A_MA13 T8 A12/BC DQU5 D3 DDR_A_D53 DDR_A_MA13 T8 A12/BC DQU5 D3 DDR_A_D47
    DDR_A_MA14_W E# L2 A13 DQU6 D7 DDR_A_D30 DDR_A_MA14_W E# L2 A13 DQU6 D7 DDR_A_D11 DDR_A_MA14_W E# L2 A13 DQU6 D7 DDR_A_D54 DDR_A_MA14_W E# L2 A13 DQU6 D7 DDR_A_D40
    [8] DDR_A_MA14_W E# A14/WE DQU7 A14/WE DQU7 A14/WE DQU7 A14/WE DQU7
    DDR_A_BA0 N2 DDR_A_BA0 N2 DDR_A_BA0 N2 DDR_A_BA0 N2
    [8] DDR_A_BA0 DDR_A_BA1 BA0 DDR_A_BA1 BA0 DDR_A_BA1 BA0 DDR_A_BA1 BA0
    N8 B3 N8 B3 N8 B3 N8 B3
    [8] DDR_A_BA1 BA1 VDD1 +1.2V BA1 VDD1 +1.2V BA1 VDD1 +1.2V BA1 VDD1 +1.2V
    B9 B9 B9 B9
    E2 VDD2 D1 E2 VDD2 D1 E2 VDD2 D1 E2 VDD2 D1
    +1.2V DMU/DBIU VDD3 +1.2V DMU/DBIU VDD3 +1.2V DMU/DBIU VDD3 +1.2V DMU/DBIU VDD3
    E7 G7 E7 G7 E7 G7 E7 G7
    DML/DBIL VDD4 J1 DML/DBIL VDD4 J1 DML/DBIL VDD4 J1 DML/DBIL VDD4 J1
    VDD5 J9 VDD5 J9 VDD5 J9 VDD5 J9
    VDD6 L1 VDD6 L1 VDD6 L1 VDD6 L1
    DDR_A_CLK0 K7 VDD7 L9 DDR_A_CLK0 K7 VDD7 L9 DDR_A_CLK0 K7 VDD7 L9 DDR_A_CLK0 K7 VDD7 L9
    [8] DDR_A_CLK0 DDR_A_CLK#0 CK_t VDD8 DDR_A_CLK#0 CK_t VDD8 DDR_A_CLK#0 CK_t VDD8 DDR_A_CLK#0 CK_t VDD8
    K8 R1 K8 R1 K8 R1 K8 R1
    [8] DDR_A_CLK#0 DDR_A_CKE0 CK_c VDD9 DDR_A_CKE0 CK_c VDD9 DDR_A_CKE0 CK_c VDD9 DDR_A_CKE0 CK_c VDD9
    K2 T9 K2 T9 K2 T9 K2 T9
    [8] DDR_A_CKE0 CKE VDD10 CKE VDD10 CKE VDD10 CKE VDD10

    A1 A1 A1 A1
    VDDQ1 A9 VDDQ1 A9 VDDQ1 A9 VDDQ1 A9
    VDDQ2 C1 VDDQ2 C1 VDDQ2 C1 VDDQ2 C1
    VDDQ3 D9 VDDQ3 D9 VDDQ3 D9 VDDQ3 D9
    VDDQ4 F2 VDDQ4 F2 VDDQ4 F2 VDDQ4 F2
    VDDQ5 F8 VDDQ5 F8 VDDQ5 F8 VDDQ5 F8
    DDR_A_ODT0 K3 VDDQ6 G1 DDR_A_ODT0 K3 VDDQ6 G1 DDR_A_ODT0 K3 VDDQ6 G1 DDR_A_ODT0 K3 VDDQ6 G1
    [8] DDR_A_ODT0 DDR_A_CS#0 ODT VDDQ7 DDR_A_CS#0 ODT VDDQ7 DDR_A_CS#0 ODT VDDQ7 DDR_A_CS#0 ODT VDDQ7
    L7 G9 L7 G9 L7 G9 L7 G9
    [8] DDR_A_CS#0 DDR_A_MA16_RAS# CS VDDQ8 DDR_A_MA16_RAS# CS VDDQ8 DDR_A_MA16_RAS# CS VDDQ8 DDR_A_MA16_RAS# CS VDDQ8
    L8 J2 L8 J2 L8 J2 L8 J2
    [8] DDR_A_MA16_RAS# DDR_A_MA15_CAS# A16/RAS VDDQ9 DDR_A_MA15_CAS# A16/RAS VDDQ9 DDR_A_MA15_CAS# A16/RAS VDDQ9 DDR_A_MA15_CAS# A16/RAS VDDQ9
    M8 J8 M8 J8 M8 J8 M8 J8
    [8] DDR_A_MA15_CAS# A15/CAS VDDQ10 A15/CAS VDDQ10 A15/CAS VDDQ10 A15/CAS VDDQ10
    B2 Replace with 240 Ohm to Support DDP@ B2 Replace with 240 Ohm to Support DDP@ B2 Replace with 240 Ohm to Support DDP@ B2 Replace with 240 Ohm to Support DDP@
    VSS1 E1 VSS1 E1 DDP@ VSS1 E1 VSS1 E1
    VSS2 E9 RD1 1 DDP@ 2 240_0402_1% VSS2 E9 RD2 1 2 240_0402_1% VSS2 E9 RD3 1 DDP@ 2 240_0402_1% VSS2 E9 RD4 1 DDP@ 2 240_0402_1%
    VSS3 G8 VSS3 G8 VSS3 G8 VSS3 G8
    DDR_A_DQS#3 A7 VSS4 K1 DDR_A_DQS#1 A7 VSS4 K1 DDR_A_DQS#6 A7 VSS4 K1 DDR_A_DQS#5 A7 VSS4 K1
    DDR_A_DQS3 B7 DQSU_c VSS5 K9 DDR_A_DQS1 B7 DQSU_c VSS5 K9 DDR_A_DQS6 B7 DQSU_c VSS5 K9 DDR_A_DQS5 B7 DQSU_c VSS5 K9
    DDR_A_DQS#2 F3 DQSU_t VSS6 M9 DDR_A_BG1_R DDR_A_DQS#0 F3 DQSU_t VSS6 M9 DDR_A_BG1_R DDR_A_DQS#4 F3 DQSU_t VSS6 M9 DDR_A_BG1_R DDR_A_DQS#7 F3 DQSU_t VSS6 M9 DDR_A_BG1_R
    C DDR_A_DQS2 DQSL_c VSS7 DDR_A_DQS0 DQSL_c VSS7 DDR_A_DQS4 DQSL_c VSS7 DDR_A_DQS7 DQSL_c VSS7 C
    G3 N1 G3 N1 G3 N1 G3 N1
    DQSL_t VSS8 T1 DQSL_t VSS8 T1 DQSL_t VSS8 T1 DQSL_t VSS8 T1
    MEMRST# P1 VSS9 MEMRST# P1 VSS9 MEMRST# P1 VSS9 MEMRST# P1 VSS9
    RESET RESET RESET RESET
    RU1 1 2 240_0402_1% F9 RU2 1 2 240_0402_1% F9 RU3 1 2 240_0402_1% F9 RU4 1 2 240_0402_1% F9
    ZQ ZQ ZQ ZQ

    DDR_A_ACT# L3 A2 DDR_A_ACT# L3 A2 DDR_A_ACT# L3 A2 DDR_A_ACT# L3 A2


    [8] DDR_A_ACT# DDR_A_BG0 ACT VSSQ1 DDR_A_BG0 ACT VSSQ1 DDR_A_BG0 ACT VSSQ1 DDR_A_BG0 ACT VSSQ1
    [8] DDR_A_BG0
    M2 A8 M2 A8 M2 A8 M2 A8
    N9 BG0 VSSQ2 C9 N9 BG0 VSSQ2 C9 N9 BG0 VSSQ2 C9 N9 BG0 VSSQ2 C9
    DDR_A_ALERT# P9 TEN VSSQ3 D2 DDR_A_ALERT# P9 TEN VSSQ3 D2 DDR_A_ALERT# P9 TEN VSSQ3 D2 DDR_A_ALERT# P9 TEN VSSQ3 D2
    [8] DDR_A_ALERT# DDR_A_PAR ALERT VSSQ4 DDR_A_PAR ALERT VSSQ4 DDR_A_PAR ALERT VSSQ4 DDR_A_PAR ALERT VSSQ4
    T3 D8 T3 D8 T3 D8 T3 D8
    [8] DDR_A_PAR PAR VSSQ5 PAR VSSQ5 PAR VSSQ5 PAR VSSQ5
    E3 E3 E3 E3
    T7 VSSQ6 E8 T7 VSSQ6 E8 T7 VSSQ6 E8 T7 VSSQ6 E8
    B1 NC VSSQ7 F1 B1 NC VSSQ7 F1 B1 NC VSSQ7 F1 B1 NC VSSQ7 F1
    +2.5V VPP1 VSSQ8 +2.5V VPP1 VSSQ8 +2.5V VPP1 VSSQ8 +2.5V VPP1 VSSQ8
    R9 H1 R9 H1 R9 H1 R9 H1
    VPP2 VSSQ9 H9 VPP2 VSSQ9 H9 VPP2 VSSQ9 H9 VPP2 VSSQ9 H9
    96-BALL VSSQ10 96-BALL VSSQ10 96-BALL VSSQ10 96-BALL VSSQ10
    SDRAM DDR4 SDRAM DDR4 SDRAM DDR4 SDRAM DDR4
    K4AAG165W A-BCW E_FBGA96 K4AAG165W A-BCW E_FBGA96 K4AAG165W A-BCW E_FBGA96 K4AAG165W A-BCW E_FBGA96
    K4AAG165W A-BCW E_FBGA_96P_A39 K4AAG165W A-BCW E_FBGA_96P_A39 K4AAG165W A-BCW E_FBGA_96P_A39 K4AAG165W A-BCW E_FBGA_96P_A39
    @ @ @ @
    C
    -l
    a
    o
    D

    e
    o
    y
    D
    E
    o

    I
    y
    r

    m
    r
    f
    S

    /
    D

    M
    [8] DDR_A_MA[0..13]

    C
    O
    K
    T
    R
    IN
    A
    IO
    N
    C
    L

    T
    E
    [8] DDR_A_DQS#[0..7]

    [8] DDR_A_DQS[0..7]

    [8] DDR_A_D[0..63] +1.2V +0.6VS


    RD1
    0_0402_5%
    SDP@
    DDR_A_CLK0 RU5 1 2 39_0201_1% CU25 1 2 0.01U_0402_16V7K DDR_A_MA0 RD53 1 2 39_0201_1%
    B B
    RD2 DDR_A_CLK#0 RU6 1 2 39_0201_1% DDR_A_MA1 RD48 1 2 39_0201_1%
    0_0402_5% DDR_A_MA2 RD30 1 2 39_0201_1%
    DDR_A_BG1_R RD7 1 DDP@ 2 0_0402_5% SDP@ DDR_A_MA3 RD34 1 2 39_0201_1%
    DDR_A_BG1 [8] DDR_A_MA4 RD31 1 2 39_0201_1%
    RD3 DDR_A_MA5 RD51 1 2 39_0201_1%
    0_0402_5% DDR_A_MA6 RD52 1 2 39_0201_1%
    SDP@ DDR_A_MA7 RD50 1 2 39_0201_1%
    RD9 1 SDP@ 2 0_0402_5% DDR_A_MA8 RD45 1 2 39_0201_1%
    RD4 DDR_A_MA9 RD29 1 2 39_0201_1%
    0_0402_5% DDR_A_MA10 RD33 1 2 39_0201_1%
    SDP@ DDR_A_MA11 RD47 1 2 39_0201_1%
    +1.2V DDR_A_MA12 RD35 1 2 39_0201_1%
    DDR_A_MA13 RD44 1 2 39_0201_1%

    DDR_A_MA14_W E# RD43 1 2 39_0201_1%


    DDR_A_ALERT# RD11 2 1 49.9_0402_1% DDR_A_MA15_CAS# RD40 1 2 39_0201_1%
    DDR_A_MA16_RAS# RD37 1 2 39_0201_1%

    DDR_A_ACT# RD38 1 2 39_0201_1%

    +1.2V DDR_A_PAR RD46 1 2 39_0201_1%


    2

    RD12 DDR_A_CS#0 RD39 1 2 39_0201_1%


    1.8K_0402_1%
    +DDR_VREF_CA DDR_A_CKE0 RD41 1 2 39_0201_1%
    RD13
    1

    2.7_0402_1% DDR_A_ODT0 RD42 1 2 39_0201_1%


    RD14 1 @ 2 0_0402_5% MEMRST# 2 1
    [8] DDR_DRAMRST#_R MEMRST# [25] [8] +0.6V_A_VREFCA
    DDR_A_BA0 RD49 1 2 39_0201_1%
    DDR_A_BA1 RD32 1 2 39_0201_1%
    1 1
    CD7 CD6
    100P_0402_50V8J 0.022U_0402_16V7K
    @ DDR_A_BG0 RD36 1 2 39_0201_1%
    2 2
    1

    A DDR_A_BG1_R RD54 1 DDP@ 2 39_0201_1% A


    RD15 RD16
    24.9_0402_1% 1.8K_0402_1%
    2

    Security Classification
    2019/11/27
    Compal Secret Data
    2020/11/27 Title
    Compal Electronics, Inc.
    Issued Date Deciphered Date
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    DDR4 ON BOARD RAM CHIPS
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K321P
    Date: Thursday, June 03, 2021 Sheet 23 of 121
    5 4 3 2 1
    5 4 3 2 1

    +1.2V

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M
    D D

    1
    CU1 @

    CU2

    CU3

    CU4

    CU5 @

    CU6

    CU7

    CD34

    CD35 @

    CD36

    CD37

    CD38

    CD39

    CD40 @

    CD41

    CD42 @
    @
    @ @

    2
    CD43 10U_0402_6.3V6M 4 as near each on board RAM device as possible

    CD44 10U_0402_6.3V6M

    CD45 10U_0402_6.3V6M

    CD46 10U_0402_6.3V6M

    CD47 10U_0402_6.3V6M
    1 1 1 1 1

    @
    2 2 2 2 2

    C C

    +0.6VS
    +2.5V

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M
    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1
    CU17

    CU18

    CU19

    CU20

    CU21

    CU22

    CU23

    CU24
    1

    1
    CU9 @

    CU10

    CU11 @

    CU12

    CU13 @

    CU14 @

    CU15

    CU16

    2
    2
    2

    @
    2 as near each on board RAM device as possible 2 as near each on board RAM device as possible

    CD53 10U_0402_6.3V6M

    CD54 10U_0402_6.3V6M
    CD48 10U_0402_6.3V6M

    CD49 10U_0402_6.3V6M

    CD50 10U_0402_6.3V6M

    CD51 10U_0402_6.3V6M

    CD52 10U_0402_6.3V6M

    1 1
    B
    1 1 1 1 1 B

    @
    2 2
    @

    2 2 2 2 2

    A A

    Security Classification
    2019/11/27
    Compal Secret Data
    2020/11/27 Title
    Compal Electronics, Inc.
    Issued Date Deciphered Date
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    DDR4 ON BOARD RAM Decoupling
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 2.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K321P
    Date: Thursday, June 03, 2021 Sheet 24 of 121
    5 4 3 2 1
    5 4 3 2 1

    +DDR1_VREF_CA +DDR1_VREF_CA +DDR1_VREF_CA +DDR1_VREF_CA

    UD5 UD6 UD8 UD7

    M1 G2 DDR_B_D7 M1 G2 DDR_B_D19 M1 G2 DDR_B_D49 M1 G2 DDR_B_D46


    VREFCA DQL0 F7 DDR_B_D1 VREFCA DQL0 F7 DDR_B_D20 VREFCA DQL0 F7 DDR_B_D53 VREFCA DQL0 F7 DDR_B_D42
    DQL1 H3 DDR_B_D6 DQL1 H3 DDR_B_D17 DQL1 H3 DDR_B_D55 DQL1 H3 DDR_B_D47
    DQL2 DQL2 DQL2 DQL2
    .047U_0402_16V7K

    DDR_B_MA0 DDR_B_D4

    .047U_0402_16V7K
    DDR_B_MA0 DDR_B_D18

    .047U_0402_16V7K
    DDR_B_MA0 DDR_B_D50

    .047U_0402_16V7K
    P3 H7 P3 H7 P3 H7 DDR_B_MA0 P3 H7 DDR_B_D45
    1 A0 DQL3 1 A0 DQL3 1 A0 DQL3 1 A0 DQL3
    CD55
    CHB@
    DDR_B_MA1 DDR_B_D0

    CD56
    CHB@
    DDR_B_MA1 DDR_B_D21

    CD57
    CHB@
    DDR_B_MA1 DDR_B_D51

    CD58
    CHB@
    P7 H2 P7 H2 P7 H2 DDR_B_MA1 P7 H2 DDR_B_D43
    DDR_B_MA2 R3 A1 DQL4 H8 DDR_B_D2 DDR_B_MA2 R3 A1 DQL4 H8 DDR_B_D22 DDR_B_MA2 R3 A1 DQL4 H8 DDR_B_D52 DDR_B_MA2 R3 A1 DQL4 H8 DDR_B_D41
    DDR_B_MA3 N7 A2 DQL5 J3 DDR_B_D5 DDR_B_MA3 N7 A2 DQL5 J3 DDR_B_D23 DDR_B_MA3 N7 A2 DQL5 J3 DDR_B_D54 DDR_B_MA3 N7 A2 DQL5 J3 DDR_B_D44
    2 DDR_B_MA4 N3 A3 DQL6 J7 DDR_B_D3 2 DDR_B_MA4 N3 A3 DQL6 J7 DDR_B_D16 2 DDR_B_MA4 N3 A3 DQL6 J7 DDR_B_D48 2 DDR_B_MA4 N3 A3 DQL6 J7 DDR_B_D40
    DDR_B_MA5 P8 A4 DQL7 DDR_B_MA5 P8 A4 DQL7 DDR_B_MA5 P8 A4 DQL7 DDR_B_MA5 P8 A4 DQL7
    DDR_B_MA6 P2 A5 DDR_B_MA6 P2 A5 DDR_B_MA6 P2 A5 DDR_B_MA6 P2 A5
    D DDR_B_MA7 R8 A6 A3 DDR_B_D14 DDR_B_MA7 R8 A6 A3 DDR_B_D26 DDR_B_MA7 R8 A6 A3 DDR_B_D60 DDR_B_MA7 R8 A6 A3 DDR_B_D34 D
    DDR_B_MA8 R2 A7 DQU0 B8 DDR_B_D10 DDR_B_MA8 R2 A7 DQU0 B8 DDR_B_D29 DDR_B_MA8 R2 A7 DQU0 B8 DDR_B_D61 DDR_B_MA8 R2 A7 DQU0 B8 DDR_B_D37
    DDR_B_MA9 R7 A8 DQU1 C3 DDR_B_D15 DDR_B_MA9 R7 A8 DQU1 C3 DDR_B_D27 DDR_B_MA9 R7 A8 DQU1 C3 DDR_B_D57 DDR_B_MA9 R7 A8 DQU1 C3 DDR_B_D33
    DDR_B_MA10 M3 A9 DQU2 C7 DDR_B_D12 DDR_B_MA10 M3 A9 DQU2 C7 DDR_B_D24 DDR_B_MA10 M3 A9 DQU2 C7 DDR_B_D59 DDR_B_MA10 M3 A9 DQU2 C7 DDR_B_D32
    DDR_B_MA11 T2 A10/AP DQU3 C2 DDR_B_D8 DDR_B_MA11 T2 A10/AP DQU3 C2 DDR_B_D30 DDR_B_MA11 T2 A10/AP DQU3 C2 DDR_B_D63 DDR_B_MA11 T2 A10/AP DQU3 C2 DDR_B_D38
    DDR_B_MA12 M7 A11 DQU4 C8 DDR_B_D9 DDR_B_MA12 M7 A11 DQU4 C8 DDR_B_D28 DDR_B_MA12 M7 A11 DQU4 C8 DDR_B_D62 DDR_B_MA12 M7 A11 DQU4 C8 DDR_B_D36
    DDR_B_MA13 T8 A12/BC DQU5 D3 DDR_B_D13 DDR_B_MA13 T8 A12/BC DQU5 D3 DDR_B_D31 DDR_B_MA13 T8 A12/BC DQU5 D3 DDR_B_D56 DDR_B_MA13 T8 A12/BC DQU5 D3 DDR_B_D35
    DDR_B_MA14_W E# L2 A13 DQU6 D7 DDR_B_D11 DDR_B_MA14_W E# L2 A13 DQU6 D7 DDR_B_D25 DDR_B_MA14_W E# L2 A13 DQU6 D7 DDR_B_D58 DDR_B_MA14_W E# L2 A13 DQU6 D7 DDR_B_D39
    [8] DDR_B_MA14_W E# A14/WE DQU7 A14/WE DQU7 A14/WE DQU7 A14/WE DQU7
    DDR_B_BA0 N2 DDR_B_BA0 N2 DDR_B_BA0 N2 DDR_B_BA0 N2
    [8] DDR_B_BA0 DDR_B_BA1 BA0 DDR_B_BA1 BA0 DDR_B_BA1 BA0 DDR_B_BA1 BA0
    N8 B3 +1.2V
    N8 B3 +1.2V
    N8 B3 +1.2V N8 B3 +1.2V
    [8] DDR_B_BA1 BA1 VDD1 BA1 VDD1 BA1 VDD1 BA1 VDD1
    B9 B9 B9 B9
    E2 VDD2 D1 E2 VDD2 D1 E2 VDD2 D1 E2 VDD2 D1
    +1.2V DMU/DBIU VDD3 +1.2V DMU/DBIU VDD3 +1.2V DMU/DBIU VDD3 +1.2V DMU/DBIU VDD3
    E7 G7 E7 G7 E7 G7 E7 G7
    DML/DBIL VDD4 J1 DML/DBIL VDD4 J1 DML/DBIL VDD4 J1 DML/DBIL VDD4 J1
    VDD5 J9 VDD5 J9 VDD5 J9 VDD5 J9
    VDD6 L1 VDD6 L1 VDD6 L1 VDD6 L1
    DDR_B_CLK0 K7 VDD7 L9 DDR_B_CLK0 K7 VDD7 L9 DDR_B_CLK0 K7 VDD7 L9 DDR_B_CLK0 K7 VDD7 L9
    [8] DDR_B_CLK0 DDR_B_CLK#0 CK_t VDD8 DDR_B_CLK#0 CK_t VDD8 DDR_B_CLK#0 CK_t VDD8 DDR_B_CLK#0 CK_t VDD8
    K8 R1 K8 R1 K8 R1 K8 R1
    [8] DDR_B_CLK#0 DDR_B_CKE0 CK_c VDD9 DDR_B_CKE0 CK_c VDD9 DDR_B_CKE0 CK_c VDD9 DDR_B_CKE0 CK_c VDD9
    K2 T9 K2 T9 K2 T9 K2 T9
    [8] DDR_B_CKE0 CKE VDD10 CKE VDD10 CKE VDD10 CKE VDD10

    A1 A1 A1 A1
    VDDQ1 A9 VDDQ1 A9 VDDQ1 A9 VDDQ1 A9
    VDDQ2 C1 VDDQ2 C1 VDDQ2 C1 VDDQ2 C1
    VDDQ3 D9 VDDQ3 D9 VDDQ3 D9 VDDQ3 D9
    VDDQ4 F2 VDDQ4 F2 VDDQ4 F2 VDDQ4 F2
    VDDQ5 F8 VDDQ5 F8 VDDQ5 F8 VDDQ5 F8
    DDR_B_ODT0 K3 VDDQ6 G1 DDR_B_ODT0 K3 VDDQ6 G1 DDR_B_ODT0 K3 VDDQ6 G1 DDR_B_ODT0 K3 VDDQ6 G1
    [8] DDR_B_ODT0 DDR_B_CS#0 ODT VDDQ7 DDR_B_CS#0 ODT VDDQ7 DDR_B_CS#0 ODT VDDQ7 DDR_B_CS#0 ODT VDDQ7
    L7 G9 L7 G9 L7 G9 L7 G9
    [8] DDR_B_CS#0 DDR_B_MA16_RAS# CS VDDQ8 DDR_B_MA16_RAS# CS VDDQ8 DDR_B_MA16_RAS# CS VDDQ8 DDR_B_MA16_RAS# CS VDDQ8
    L8 J2 L8 J2 L8 J2 L8 J2
    [8] DDR_B_MA16_RAS# DDR_B_MA15_CAS# A16/RAS VDDQ9 DDR_B_MA15_CAS# A16/RAS VDDQ9 DDR_B_MA15_CAS# A16/RAS VDDQ9 DDR_B_MA15_CAS# A16/RAS VDDQ9
    M8 J8 M8 J8 M8 J8 M8 J8
    [8] DDR_B_MA15_CAS# A15/CAS VDDQ10 A15/CAS VDDQ10 A15/CAS VDDQ10 A15/CAS VDDQ10
    B2 Replace with 240 Ohm to Support DDP@ B2 Replace with 240 Ohm to Support DDP@ B2 Replace with 240 Ohm to Support DDP@ B2 Replace with 240 Ohm to Support DDP@
    VSS1 E1 DDP_CHB@ VSS1 E1 DDP_CHB@ VSS1 E1 DDP_CHB@ VSS1 E1 DDP_CHB@
    VSS2 E9 RD55 1 2 240_0402_1% VSS2 E9 RD56 1 2 240_0402_1% VSS2 E9 RD57 1 2 240_0402_1% VSS2 E9 RD58 1 2 240_0402_1%
    VSS3 G8 VSS3 G8 VSS3 G8 VSS3 G8
    DDR_B_DQS#1 A7 VSS4 K1 DDR_B_DQS#3 A7 VSS4 K1 DDR_B_DQS#7 A7 VSS4 K1 DDR_B_DQS#4 A7 VSS4 K1
    DDR_B_DQS1 B7 DQSU_c VSS5 K9 DDR_B_DQS3 B7 DQSU_c VSS5 K9 DDR_B_DQS7 B7 DQSU_c VSS5 K9 DDR_B_DQS4 B7 DQSU_c VSS5 K9
    DDR_B_DQS#0 F3 DQSU_t VSS6 M9 DDR_B_BG1_R DDR_B_DQS#2 F3 DQSU_t VSS6 M9 DDR_B_BG1_R DDR_B_DQS#6 F3 DQSU_t VSS6 M9 DDR_B_BG1_R DDR_B_DQS#5 F3 DQSU_t VSS6 M9 DDR_B_BG1_R
    DDR_B_DQS0 G3 DQSL_c VSS7 N1 DDR_B_DQS2 G3 DQSL_c VSS7 N1 DDR_B_DQS6 G3 DQSL_c VSS7 N1 DDR_B_DQS5 G3 DQSL_c VSS7 N1
    DQSL_t VSS8 T1 DQSL_t VSS8 T1 DQSL_t VSS8 T1 DQSL_t VSS8 T1
    C VSS9 VSS9 VSS9 VSS9 C
    MEMRST# P1 MEMRST# P1 MEMRST# P1 MEMRST# P1
    [23] MEMRST# RESET RESET RESET RESET
    RU7 1 CHB@ 2 240_0402_1% F9 RU8 1 CHB@ 2 240_0402_1% F9 RU9 1 CHB@ 2 240_0402_1% F9 RU10 1 CHB@ 2 240_0402_1% F9
    ZQ ZQ ZQ ZQ

    DDR_B_ACT# L3 A2 DDR_B_ACT# L3 A2 DDR_B_ACT# L3 A2 DDR_B_ACT# L3 A2


    [8] DDR_B_ACT# DDR_B_BG0 ACT VSSQ1 DDR_B_BG0 ACT VSSQ1 DDR_B_BG0 ACT VSSQ1 DDR_B_BG0 ACT VSSQ1
    M2 A8 M2 A8 M2 A8 M2 A8
    [8] DDR_B_BG0 BG0 VSSQ2 BG0 VSSQ2 BG0 VSSQ2 BG0 VSSQ2
    N9 C9 N9 C9 N9 C9 N9 C9
    DDR_B_ALERT# P9 TEN VSSQ3 D2 DDR_B_ALERT# P9 TEN VSSQ3 D2 DDR_B_ALERT# P9 TEN VSSQ3 D2 DDR_B_ALERT# P9 TEN VSSQ3 D2
    [8] DDR_B_ALERT# DDR_B_PAR ALERT VSSQ4 DDR_B_PAR ALERT VSSQ4 DDR_B_PAR ALERT VSSQ4 DDR_B_PAR ALERT VSSQ4
    T3 D8 T3 D8 T3 D8 T3 D8
    [8] DDR_B_PAR PAR VSSQ5 PAR VSSQ5 PAR VSSQ5 PAR VSSQ5
    E3 E3 E3 E3
    T7 VSSQ6 E8 T7 VSSQ6 E8 T7 VSSQ6 E8 T7 VSSQ6 E8
    B1 NC VSSQ7 F1 B1 NC VSSQ7 F1 B1 NC VSSQ7 F1 B1 NC VSSQ7 F1
    +2.5V VPP1 VSSQ8 +2.5V VPP1 VSSQ8 +2.5V VPP1 VSSQ8 +2.5V VPP1 VSSQ8
    R9 H1 R9 H1 R9 H1 R9 H1
    VPP2 VSSQ9 H9 VPP2 VSSQ9 H9 VPP2 VSSQ9 H9 VPP2 VSSQ9 H9
    96-BALL VSSQ10 96-BALL VSSQ10 96-BALL VSSQ10 96-BALL VSSQ10
    SDRAM DDR4 SDRAM DDR4 SDRAM DDR4 SDRAM DDR4
    K4AAG165W A-BCW E_FBGA96 K4AAG165W A-BCW E_FBGA96 K4AAG165W A-BCW E_FBGA96 K4AAG165W A-BCW E_FBGA96
    K4AAG165W A-BCW E_FBGA_96P_A39 K4AAG165W A-BCW E_FBGA_96P_A39 K4AAG165W A-BCW E_FBGA_96P_A39 K4AAG165W A-BCW E_FBGA_96P_A39
    @ @ @ @
    C
    -l
    a
    o
    D

    e
    o
    y
    D
    E
    o

    I
    y
    r

    m
    r
    f
    S

    /
    D

    M
    [8] DDR_B_MA[0..13]

    C
    O
    K
    T
    R
    IN
    A
    IO
    N
    C
    L

    T
    E
    [8] DDR_B_DQS#[0..7]

    [8] DDR_B_DQS[0..7]

    [8] DDR_B_D[0..63] +1.2V +0.6VS


    RD55
    0_0402_5%
    SDP_CHB@
    DDR_B_CLK0 RU11 1 CHB@ 2 39_0201_1% CU26 1 2 0.01U_0402_16V7K DDR_B_MA0 RD60 1 CHB@ 2 39_0201_1%
    RD56 DDR_B_CLK#0 DDR_B_MA1
    RU12 1 CHB@ 2 39_0201_1% RD62 1 CHB@ 2 39_0201_1%
    0_0402_5% DDR_B_MA2
    B DDP_CHB@ CHB@ RD63 1 CHB@ 2 39_0201_1% B
    DDR_B_BG1_R SDP_CHB@ DDR_B_MA3
    RD64 1 2 0_0402_5% RD65 1 CHB@ 2 39_0201_1%
    DDR_B_BG1 [8] DDR_B_MA4 RD66 1 CHB@ 2 39_0201_1%
    RD57 DDR_B_MA5 RD68 1 CHB@ 2 39_0201_1%
    0_0402_5% DDR_B_MA6 RD69 1 CHB@ 2 39_0201_1%
    SDP_CHB@ DDR_B_MA7
    SDP_CHB@ RD70 1 CHB@ 2 39_0201_1%
    RD71 1 2 0_0402_5% DDR_B_MA8 RD72 1 CHB@ 2 39_0201_1%
    RD58 DDR_B_MA9 RD74 1 CHB@ 2 39_0201_1%
    0_0402_5% DDR_B_MA10 RD75 1 CHB@ 2 39_0201_1%
    SDP_CHB@ DDR_B_MA11 RD76 1 CHB@ 2 39_0201_1%
    +1.2V DDR_B_MA12 RD77 1 CHB@ 2 39_0201_1%
    DDR_B_MA13 RD78 1 CHB@ 2 39_0201_1%

    DDR_B_MA14_W E# RD79 1 CHB@ 2 39_0201_1%


    DDR_B_ALERT# RD80 2 CHB@ 1 49.9_0402_1% DDR_B_MA15_CAS# RD81 1 CHB@ 2 39_0201_1%
    DDR_B_MA16_RAS# RD82 1 CHB@ 2 39_0201_1%

    DDR_B_ACT# RD83 1 CHB@ 2 39_0201_1%

    +1.2V DDR_B_PAR RD84 1 CHB@ 2 39_0201_1%


    2

    CHB@
    RD85 DDR_B_CS#0 RD86 1 CHB@ 2 39_0201_1%
    1.8K_0402_1%
    CHB@ +DDR1_VREF_CA DDR_B_CKE0 RD87 1 CHB@ 2 39_0201_1%
    RD89 +DDR1_VREF_CA +DDR_VREF_CA
    1

    2.7_0402_1% DDR_B_ODT0 RD88 1 CHB@ 2 39_0201_1%


    2 1
    [8] +0.6V_B_VREFCA
    RD96 1 @ 2 0_0402_5%
    DDR_B_BA0 RD90 1 CHB@ 2 39_0201_1%
    CHB@ DDR_B_BA1 RD91 1 CHB@ 2 39_0201_1%
    1
    CD59
    0.022U_0402_16V7K
    DDR_B_BG0 RD92 1 CHB@ 2 39_0201_1%
    2
    1

    CHB@ CHB@ DDR_B_BG1_R RD95 1 2 39_0201_1%


    RD93 RD94 DDP_CHB@
    A 24.9_0402_1% 1.8K_0402_1% A
    2

    Security Classification
    2019/11/27
    Compal Secret Data
    2020/11/27 Title
    Compal Electronics, Inc.
    Issued Date Deciphered Date
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    DDR4 ON BOARD RAM CHIPS
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K321P
    Date: Thursday, June 03, 2021 Sheet 25 of 121
    5 4 3 2 1
    D

    2.0
    Rev
    DDR4 ON BOARD RAM Decoupling

    121
    of
    Compal Electronics, Inc.

    26
    Sheet
    1

    1
    Thursday, June 03, 2021

    CU49 @
    1U_0201_6.3V6M
    LA-K321P

    1 2
    Document Number

    CHB@
    CU48
    1U_0201_6.3V6M
    2 as near each on board RAM device as possible

    1 2
    CU47 @
    Date:
    Title

    Size

    1U_0201_6.3V6M
    1 2
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

    CD68 @ CU46 @
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

    1U_0201_6.3V6M 1U_0201_6.3V6M
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

    1 2 1 2
    CHB@
    2020/11/27

    CD67 @ CU45
    1U_0201_6.3V6M 1U_0201_6.3V6M
    2

    2
    1 2 1 2
    CD66 @ CU44 @
    1U_0201_6.3V6M 1U_0201_6.3V6M
    1 2 1 2

    Deciphered Date
    CHB@

    Compal Secret Data


    CD65 CU43 @
    1U_0201_6.3V6M 1U_0201_6.3V6M CD80 10U_0402_6.3V6M
    1

    1 2 1 2
    @
    CHB@ CHB@
    CD64 CU42 CHB@
    1U_0201_6.3V6M 1U_0201_6.3V6M CD79 10U_0402_6.3V6M
    1

    2
    4 as near each on board RAM device as possible

    1 2 1 2
    CHB@
    CD63
    1U_0201_6.3V6M
    www.teknisi-indonesia.com

    1 2

    2019/11/27
    CD62 @
    +0.6VS

    1U_0201_6.3V6M
    1 2
    3

    3
    CD61 @
    1U_0201_6.3V6M

    Security Classification
    1 2
    CHB@ CHB@
    CD60 CU41

    Issued Date
    1U_0201_6.3V6M 1U_0201_6.3V6M
    1 2 1 2
    CHB@ CHB@
    CU33 CU40
    1U_0201_6.3V6M 1U_0201_6.3V6M
    2 as near each on board RAM device as possible
    1 2 1 2
    CHB@
    CU32 CU39 @
    1U_0201_6.3V6M 1U_0201_6.3V6M
    1 2 1 2
    CU31 @ CHB@ CU38 @
    1U_0201_6.3V6M CD73 10U_0402_6.3V6M 1U_0201_6.3V6M CD78 10U_0402_6.3V6M

    2
    1

    1 2 1 2
    @
    CHB@
    CU30 CU37 @ CHB@
    4

    4
    1U_0201_6.3V6M CD72 10U_0402_6.3V6M 1U_0201_6.3V6M CD77 10U_0402_6.3V6M
    1

    2
    1 2 @ 1 2
    CHB@ CHB@
    CU29 CHB@ CU36
    1U_0201_6.3V6M CD71 10U_0402_6.3V6M 1U_0201_6.3V6M CD76 10U_0402_6.3V6M
    1

    2
    1 2 1 2
    @
    CHB@
    CU28 @ CHB@ CU35
    1U_0201_6.3V6M CD70 10U_0402_6.3V6M 1U_0201_6.3V6M CD75 10U_0402_6.3V6M

    2
    1 2 1 2
    @
    CU27 @ CU34 @
    1U_0201_6.3V6M CD69 10U_0402_6.3V6M 1U_0201_6.3V6M CD74 10U_0402_6.3V6M

    2
    1 2 @ 1 2
    @
    +1.2V

    +2.5V
    5

    5
    D

    A
    1 2 3 4 5

    UV1A
    1/14 PCI_EXPRESS

    Place under GPU Place close to BGA +1.0VS_DGPU

    AA14 PEX_WAKE# PEX_CVDD AA22

    4.7U_0402_6.3V6M
    CV160

    4.7U_0402_6.3V6M
    CV159

    4.7U_0402_6.3V6M
    CV158

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M
    PLT_RST_VGA#

    22U_0603_6.3V6M

    22U_0402_6.3V6M
    AC7 AB23 1 1 1 1 1 1 1 1 1 1 1 1 1 1

    10U_0402_6.3V6M
    CV161

    10U_0402_6.3V6M
    CV162

    10U_0402_6.3V6M
    CV163
    PEX_RST# PEX_DVDD

    CV157

    CV156

    CV155

    CV154

    CV153

    CV152

    CV165

    CV164
    AC24
    CLKREQ_PEG#0_R PEX_DVDD
    AC6 AD25
    PEX_CLKREQ# PEX_DVDD
    AE26

    @DIS@

    @DIS@

    DIS@

    @DIS@

    DIS@

    DIS@

    @DIS@

    DIS@

    @DIS@
    PEX_DVDD 2 2 2 2 2 2 2 2 2 2 2 2 2 2

    @DIS@

    DIS@

    DIS@

    DIS@

    @DIS@
    AE8 AE27
    [11] CLK_PEG_P0 AD8 PEX_REFCLK PEX_DVDD
    PCIE CLK [11] CLK_PEG_N0 PEX_REFCLK#
    PCIE4_CRX_DTX_P0 CV14 DIS@ 1 2 0.22U_0201_6.3V6M PCIE4_CRX_C_DTX_P0 AC9
    A [13] PCIE4_CRX_DTX_P0 PCIE4_CRX_DTX_N0 2 0.22U_0201_6.3V6M PCIE4_CRX_C_DTX_N0 PEX_TX0 A
    CV15 DIS@ 1 AB9
    [13] PCIE4_CRX_DTX_N0 PEX_TX0#
    PCIE4_CTX_DRX_P0 CV67 DIS@ 1 2 0.22U_0201_6.3V6M PCIE4_CTX_C_DRX_P0 AG6
    [13] PCIE4_CTX_DRX_P0 PCIE4_CTX_DRX_N0 2 0.22U_0201_6.3V6M PCIE4_CTX_C_DRX_N0 PEX_RX0
    CV68 DIS@ 1 AG7 PEX_HVDD
    AA10
    [13] PCIE4_CTX_DRX_N0 PEX_RX0# +1.8VS_DGPU
    PEX_HVDD AA12
    PCIE4_CRX_DTX_P1 CV69 DIS@ 1 2 0.22U_0201_6.3V6M PCIE4_CRX_C_DTX_P1 AB10 AA13 Place under GPU
    [13] PCIE4_CRX_DTX_P1 PEX_TX1 PEX_HVDD Place close to BGA
    PCIE4_CRX_DTX_N1 CV70 DIS@ 1 2 0.22U_0201_6.3V6M PCIE4_CRX_C_DTX_N1 AC10 AA16
    [13] PCIE4_CRX_DTX_N1 PEX_TX1# PEX_HVDD
    PEX_HVDD
    AA18
    PCIE4_CTX_DRX_P1 CV71 DIS@ 1 2 0.22U_0201_6.3V6M PCIE4_CTX_C_DRX_P1 AF7 AA19

    4.7U_0402_6.3V6M
    CV146

    4.7U_0402_6.3V6M
    CV145

    1U_0201_6.3V6M
    4.7U_0402_6.3V6M
    CV144

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M
    1U_0201_6.3V6M

    1U_0201_6.3V6M
    [13] PCIE4_CTX_DRX_P1 PEX_RX1 PEX_HVDD

    22U_0603_6.3V6M

    22U_0603_6.3V6M
    PCIE4_CTX_DRX_N1 CV72 DIS@ 1 2 0.22U_0201_6.3V6M PCIE4_CTX_C_DRX_N1 AE7 AA20 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

    10U_0402_6.3V6M
    CV148

    10U_0402_6.3V6M
    CV149
    10U_0402_6.3V6M
    CV147
    [13] PCIE4_CTX_DRX_N1 PEX_RX1# PEX_HVDD
    PCIE X4 Bus

    CV142

    CV138

    CV137
    CV141

    CV140

    CV139

    CV136

    CV151

    CV150
    PEX_HVDD AA21
    PCIE4_CRX_DTX_P2 CV73 DIS@ 1 2 0.22U_0201_6.3V6M PCIE4_CRX_C_DTX_P2 AD11 AB22
    [13] PCIE4_CRX_DTX_P2 PEX_TX2 PEX_HVDD
    PCIE4_CRX_DTX_N2 CV76 DIS@ 1 2 0.22U_0201_6.3V6M PCIE4_CRX_C_DTX_N2 AC11 AC23

    @DIS@

    @DIS@

    DIS@

    @DIS@

    @DIS@

    DIS@
    DIS@

    @DIS@

    DIS@

    DIS@
    [13] PCIE4_CRX_DTX_N2 PEX_TX2# PEX_HVDD 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

    @DIS@

    DIS@
    DIS@

    @DIS@

    DIS@
    PEX_HVDD
    AD24
    PCIE4_CTX_DRX_P2 CV77 DIS@ 1 2 0.22U_0201_6.3V6M PCIE4_CTX_C_DRX_P2 AE9 AE25
    [13] PCIE4_CTX_DRX_P2 PEX_RX2 PEX_HVDD
    PCIE4_CTX_DRX_N2 CV78 DIS@ 1 2 0.22U_0201_6.3V6M PCIE4_CTX_C_DRX_N2 AF9 AF26
    [13] PCIE4_CTX_DRX_N2 PEX_RX2# PEX_HVDD
    PEX_HVDD AF27
    PCIE4_CRX_DTX_P3 CV79 DIS@ 1 2 0.22U_0201_6.3V6M PCIE4_CRX_C_DTX_P3 AC12
    [13] PCIE4_CRX_DTX_P3 PCIE4_CRX_DTX_N3 PEX_TX3
    CV80 DIS@ 1 2 0.22U_0201_6.3V6M PCIE4_CRX_C_DTX_N3 AB12
    [13] PCIE4_CRX_DTX_N3 PEX_TX3#
    PCIE4_CTX_DRX_P3 CV81 DIS@ 1 2 0.22U_0201_6.3V6M PCIE4_CTX_C_DRX_P3 AG9
    [13] PCIE4_CTX_DRX_P3 PEX_RX3
    PCIE4_CTX_DRX_N3 CV82 DIS@ 1 2 0.22U_0201_6.3V6M PCIE4_CTX_C_DRX_N3 AG10
    [13] PCIE4_CTX_DRX_N3 PEX_RX3#
    AB13
    Near UV1 AC13
    PEX_TX4
    PEX_TX4#

    AF10 PEX_RX4 +1.8VS_DGPU


    AE10 PEX_RX4#

    AD14 PEX_TX5
    Place under GPU
    AC14 PEX_TX5# PEX_PLL_HVDD AA8
    PEX_PLL_HVDD AA9
    AE12 PEX_RX5

    1U_0201_6.3V6M
    AF12 PEX_RX5# 1

    CV182 DIS@
    B AC15 B
    PEX_TX6
    AB15 PEX_TX6#
    2
    AG12 PEX_RX6
    AG13 PEX_RX6#

    AB16 PEX_TX7
    AC16 PEX_TX7#

    AF13 PEX_RX7
    AE13 PEX_RX7#
    AD17
    PEX_TX8
    AC17
    PEX_TX8#
    AE15 PEX_RX8
    AF15 PEX_RX8#
    AC18
    Reset Control +1.8VS_DGPU_AON AB18
    PEX_TX9
    PEX_TX9#
    AG15 PEX_RX9
    UV6 AG16
    PEX_RX9#
    5

    PEX LANES 15 - 4 ARE DEFEATURED


    MC74VHC1G08DFT2G_SC70-5
    AB19
    VCC

    PEX_TX10
    (From PCH) 1 AC19 PEX_TX10#
    [11,52,58,68,71] PCI_RST# IN1 4 PLT_RST_VGA#
    2 OUT AF16
    GND

    [12] DGPU_HOLD_RST# IN2 PEX_RX10


    AE16
    PEX_RX10#
    1

    DIS@ RV2 AD20 PEX_TX11


    3

    100K_0201_5% AC20 PEX_TX11#


    DIS@
    AE18
    PEX_RX11
    2

    AF18 PEX_RX11#
    C C
    AC21 PEX_TX12
    AB21
    PEX_TX12#
    AG18 PEX_RX12
    AG19 PEX_RX12#
    +1.8VS_DGPU AD23
    CLK_REQ AE23
    PEX_TX13
    PEX_TX13#
    AF19 PEX_RX13
    1

    AE19 PEX_RX13#
    RV5
    10K_0402_5% AF24 PEX_TX14
    DIS@ AE24 PEX_TX14#
    @DIS@
    2

    AE21 PEX_RX14
    RV6 1 2 0_0402_5% AF21
    [31,103] DGPU_PWROK PEX_RX14#
    1U_0201_6.3V6M

    AG24 PEX_TX15
    CV29

    AG25 PEX_TX15#
    1

    +1.8VS_DGPU_AON AG21
    PEX_RX15
    AG22
    PEX_RX15#
    2

    @DIS@
    1

    PEX_TERMP AF25
    PEX_TERMP
    RV7
    10K_0402_5% QV150
    DIS@ DIS@

    1
    N18S-G5_FCBGA603
    2
    G

    BSS138W-7-F_SOT323-3
    RV8
    2

    @
    CLKREQ_PEG#0_R 3 1 2.49K_0402_1%
    CLKREQ_PEG#0 [11] DIS@
    S

    2
    (To SOC)
    D VGS(Max) : 1.5 V D
    @DIS@
    RV10 1 2 0_0402_5%

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2019/11/27 Deciphered Date 2020/11/27 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    NV(1/5)-PCIE
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K321P
    Date: Thursday, June 03, 2021 Sheet 27 of 121
    1 2 3 4 5
    1 2 3 4 5

    UV1J
    4/14 IFPAB
    +VGA_CORE +VGA_CORE
    DVI HDMI DP UV1G
    SL/DL 6/14 XVDD

    AC4
    IFPA_L3#
    AC3
    A TXC/TXC IFPA_L3 G1 XVDD XVDD N4 A
    G2 XVDD XVDD N5
    AA6 IFPAB_RSET G3 XVDD XVDD N7
    Y3
    TXD0/0 IFPA_L2# G4 XVDD XVDD P3
    Y4
    IFPA_L2 G5 XVDD XVDD P4
    G6 XVDD XVDD P6
    G7 XVDD XVDD R1
    AA2
    TXD1/1 IFPA_L1# H3 XVDD XVDD R2
    W7 IFPAB_PLLVDD AA3
    IFPA_L1 H4 XVDD XVDD R3
    H6 XVDD XVDD R4
    J1 XVDD XVDD R5
    AA1
    TXD2/2 IFPA_L0# J2 XVDD XVDD R6
    AB1
    IFPA_L0 J3 XVDD XVDD R7
    J4 XVDD XVDD T1
    J5 XVDD XVDD T2
    IFPA_AUX_SDA# AA5
    J6 XVDD XVDD T3
    IFPA_AUX_SCL AA4
    J7 XVDD XVDD T4
    K1 XVDD XVDD T5
    K2 XVDD XVDD T6
    AB4
    IFPB_L3# K3 XVDD XVDD T7
    TXC AB5
    IFPB_L3 K4 XVDD XVDD U3
    K5 XVDD XVDD U4
    K6 XVDD XVDD U6
    W6 IFP_IOVDD TXD0/3 IFPB_L2#
    AB2
    K7 XVDD XVDD V1
    IFPB_L2
    AB3
    L3 XVDD XVDD V2
    Y6 IFP_IOVDD L4 XVDD XVDD V3
    M1 XVDD GM108 XVDD V4
    TXD1/4 AD2
    IFPB_L1# M2 XVDD XVDD V5
    AD3
    IFPB_L1 M3 XVDD XVDD V6
    M4 XVDD XVDD V7
    M5 XVDD RSVD XVDD W1
    TXD2/5 AD1
    IFPB_L0# M7 XVDD XVDD W2
    AE1
    IFPB_L0 N1 XVDD XVDD W3
    N2 XVDD XVDD W4
    N3 XVDD
    IFPB_AUX_SDA# AD5
    B AD4 B
    IFPB_AUX_SCL

    N18S-G5_FCBGA603
    IFPAB (DEFEATURED 0N GM108)
    @

    N18S-G5_FCBGA603
    @

    +1.8VS_DGPU
    Close to L6 M6 F11 N6 Under L6 M6 F11 N6
    DIS@
    L14 1 2 HCB1005KF-300T25_2P VID_PLLVDD
    SM01000NV00
    X'TAL
    22U_0603_6.3V6M
    CV116
    4.7U_0402_6.3V6M
    CV117

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M
    1 1 1 1 1 1
    CV113

    CV112

    CV114

    CV115 UV1L
    9/14 XTAL_PLL
    DIS@

    @DIS@

    @DIS@

    DIS@

    DIS@
    DIS@

    2 2 2 2 2 2 L6 XS_PLLVDD +1.8VS_DGPU_AON
    M6 SP_PLLVDD
    F11 GPCPLL_AVDD RV11 @DIS@
    N6 VID_PLLVDD 10K_0402_1%
    1 2

    RV12 DIS@ RV13 DIS@


    10K_0402_1% 100K_0402_5%
    2 1 A10 XTALSSIN XTALOUTBUFF C10 XTAL_OUTBUFF 1 2
    C C

    C11 XTALIN XTALOUT B10

    N18S-G5_FCBGA603
    @
    90-OHM DIFF Impedance for XTALIN & XTALOUT.

    2
    YV1 RV14
    27MHZ_10PF_XRCGB27M000F2P18R0 1.5K_0402_1%
    SJ10000UI00 DIS@

    1
    1 3
    1 3
    NC NC
    1 1
    DIS@
    CV37 2 4 CV38
    15P_0402_50V8J 15P_0402_50V8J
    2 DIS@ 2 DIS@

    D D

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2019/11/27 Deciphered Date 2020/11/27 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    NV(2/5)-IABCDEF_DAC_XTAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K321P
    Date: Thursday, June 03, 2021 Sheet 28 of 121
    1 2 3 4 5
    1 2 3 4 5

    +1.2VS_VRAM +1.2VS_GPU
    J3 JUMP@
    2 1
    2 1
    JUMP_43X79

    +VGA_CORE
    +VGA_CORE UV1H
    UV1C
    A
    +1.2VS_GPU UV1D UV1F 13/14 GND A
    11/14 NVVDD
    Place under GPU 12/14 FBVDDQ
    K10 7/14 VDDS
    VDD A2 GND GND K11
    K12
    B26 VDD AB17 GND GND K13
    FBVDDQ K14
    C25 VDD L11 AB20 GND GND K15
    FBVDDQ K16 VDDS
    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    10U_0402_6.3V6M

    10U_0402_6.3V6M
    E23 VDD L17 AB24 GND GND K17
    FBVDDQ K18 VDDS

    CV175

    CV174
    1 1 1 1 1 1 1 1 1 1 E26 VDD M14 AC2 GND GND L10
    CV800

    CV801

    CV799

    CV802

    CV797

    CV798

    CV40

    CV41
    FBVDDQ L13 VDDS
    F14 VDD P10 AC22 GND GND L12
    FBVDDQ L15 VDDS
    F21 VDD P12 AC26 GND GND L14
    FBVDDQ M10 VDDS
    G13 VDD P16 AC5 L16
    DIS@

    @DIS@

    @DIS@

    DIS@

    @DIS@

    DIS@

    DIS@

    DIS@

    DIS@
    DIS@
    FBVDDQ M12 VDDS GND GND
    2 2 2 2 2 2 2 2 2 2 G14 VDD P18 AC8 L18
    FBVDDQ M16 VDDS GND GND
    G15 VDD T14 AD12 GND GND L5
    FBVDDQ M18 VDDS
    G16 VDD U11 AD13 GND GND M11
    FBVDDQ N11 VDDS
    G18 VDD U17 A26 GND GND M13
    FBVDDQ N13 VDDS
    G19 VDD AD15 GND GND M15
    FBVDDQ N15
    G20 VDD AD16 GND GND M17
    FBVDDQ N17
    G21 VDD AD18 GND GND N10
    FBVDDQ P14
    L22 VDD AD19 GND GND N12
    FBVDDQ R11
    L24 VDD AD21 GND GND N14
    FBVDDQ R13
    L26 VDD AD22 GND GND N16
    FBVDDQ R15
    M21 VDD AE11 GND GND N18
    FBVDDQ R17
    N21 VDD AE14 GND GND P11
    FBVDDQ T10
    R21 VDD AE17 GND GND P13
    FBVDDQ T12
    T21 VDD AE20 GND GND P15
    FBVDDQ T16
    Place near GPU V21 VDD AB11 GND GND P17
    FBVDDQ T18
    W21 VDD N18S-G5_FCBGA603 AF1 GND GND P23
    FBVDDQ U13
    H24 VDD @ AF11 GND GND P26
    FBVDDQ U15
    H26 VDD AF14 GND GND R10
    FBVDDQ V10
    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    10U_0402_6.3V6M
    J21 VDD AF17 GND GND R12
    FBVDDQ V12
    CV45

    CV107

    CV803

    CV46
    1 1 1 1 K21 VDD AF20 GND GND R14
    FBVDDQ V14
    VDD AF23 GND GND R16
    V16
    VDD AF5 GND GND R18
    V18
    VDD AF8 GND GND T11
    2 2 2 2
    DIS@

    DIS@

    DIS@

    DIS@

    AG2 GND GND T13


    AG26 GND GND T15
    B VDD_SENSE_GPU AB14 GND GND T17 B
    F2
    VDD_SENSE GND_SENSE_GPU VDD_SENSE_GPU [103] B1 GND GND U10
    F1
    GND_SENSE GND_SENSE_GPU [103] B11 GND GND U12
    B14 GND GND U14
    B17 GND GND U16
    B20 GND GND U18
    B23 GND GND U23
    N18S-G5_FCBGA603
    To POWER B27 GND GND U26
    @ B5 V11
    GND GND
    trace width: 16mils B8 GND GND V13
    differential voltage sensing. E11 GND GND V15
    differential signal routing. E14 GND GND V17
    E17 GND GND Y2
    E2 GND GND Y23
    E20 GND GND Y26
    E22 GND GND Y5
    E25 GND GND AA7
    Near Ball +1.2VS_GPU E5 GND GND AB7
    E8 GND

    FB_CAL_PD_VDDQ D22 RV15 1 DIS@ 2 40.2_0402_1%

    FB_CAL_PU_GND C24 RV16 2 DIS@ 1 40.2_0402_1% OPTIONAL GND:

    XVDD AREA
    FB_CALTERM_GND B25 RV17 2 DIS@ 1 40.2_0402_1%
    H2 GND_OPT GND_OPT P2
    H5 GND_OPT GND_OPT P5
    L2 GND_OPT GND_OPT U2
    N18S-G5_FCBGA603 GND_OPT U5
    @
    PCB ADR/CMD
    PWR REFERENCE

    C C
    H23 GND_OPT GND_OPT L23
    H25 GND_OPT GND_OPT L25

    N18S-G5_FCBGA603
    UV1E @
    14/14 VDD18
    +1.8VS_DGPU
    @DIS@ +1.8VS_DGPU_AON
    VDD18_NC G8 RV2493 1 2 0_0402_5%
    VDD18_NC G9 Under GPU Close to GPU
    1V8_AON G10
    1V8_AON G12
    1U_0201_6.3V6M
    CV177

    1U_0201_6.3V6M
    CV171

    1U_0201_6.3V6M
    CV170
    1U_0201_6.3V6M
    CV176

    1U_0201_6.3V6M
    CV169

    4.7U_0402_6.3V6M
    CV168

    4.7U_0402_6.3V6M
    CV167

    4.7U_0402_6.3V6M
    CV166
    1 1 1 1 1 1 1 1
    DIS@

    @DIS@

    DIS@
    @DIS@

    DIS@

    DIS@

    @DIS@

    DIS@
    2 2 2 2 2 2 2 2

    FP_FUSE_SRC AB6 FP_FUSE_GPU


    FP_FUSE_GPU [30]

    N18S-G5_FCBGA603
    @

    D D

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2019/11/27 Deciphered Date 2020/11/27 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    NV(3/5)-POWER
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K321P
    Date: Thursday, June 03, 2021 Sheet 29 of 121
    1 2 3 4 5
    1 2 3 4 5

    UV1I
    I2CS SMBUS: 5/14 NC
    +1.8VS_DGPU_AON
    0x96 and 0x9E(Default) +1.8VS_DGPU_AON

    I2CS_SCL RV19 1 DIS@ 2 2.2K_0402_5% AA15 DGPU_MAIN_EN RV20 1 DIS@ 2 10K_0201_5%


    NC
    UV1M I2CS_SDA RV21 1 DIS@ 2 2.2K_0402_5% AB8 PSI RV22 1 DIS@ 2 10K_0201_5%
    NC
    8/14 MISC1 I2CC_SCL RV2477 2 DIS@ 1 2.2K_0402_5% AD10 VGA_AC_DET RV23 1 DIS@ 2 10K_0201_5%
    +1.8VS_DGPU_AON NC
    I2CC_SDA RV2478 2 DIS@ 1 2.2K_0402_5% AD7 NC GPU_EVENT#_D RV26 1 GC6@ 2 10K_0201_5%
    I2CB_SCL RV2479 2 DIS@ 1 2.2K_0402_5% AE22 NC
    I2CB_SDA RV2480 2 DIS@ 1 2.2K_0402_5% AE3 NC GPIO8_OVERT# RV27 1 DIS@ 2 100K_0201_5%
    1 @ 2 TS_AVDD F10 TS_AVDD AE4 NC GPIO9_ALERT# RV28 1 DIS@ 2 10K_0201_5%
    AF2
    RV2472 0_0402_5% I2CS_SCL Pull up is recommended to avoide NVIDIA diagnostic error. NC RV2506 1 @DIS@ 2 10K_0201_5%
    I2CS_SCL D9 AF22 NC
    I2CS_SDA D8 I2CS_SDA AF3 NC
    GPIO8_OVERT# A6 OVERT AF4
    +1.8VS_DGPU_AON NC
    AE2 TS_VREF I2CC_SCL A9 I2CC_SCL AG3 MEM_VDD_CTL RV2492 1 DIS@ 2 10K_0201_5%
    NC
    I2CC_SDA B9 I2CC_SDA D10 GPU_JTAG_TRST# RV30 1 DIS@ 2 10K_0201_5%
    NC
    E10 GPU_BUFRST RV2491 1 @DIS@ 2 10K_0201_5%
    A
    @DIS@ NC
    GPU_TESTMODE A
    RV49 1 2 0_0402_5% STRAPREF0 F6 NC RV37 1 DIS@ 2 10K_0201_5%
    E12 W5 MEM_VREF RV38 1 DIS@ 2 100K_0201_5%
    1 THERMDN NC
    CV172 I2CB_SCL C9 I2CB_SCL F5 NC
    1U_0201_6.3V6M F12 THERMDP I2CB_SDA C8 I2CB_SDA GC6_FB_EN1V8 RV40 1 GC6@ 2 10K_0201_5%
    DIS@
    2
    +1.8VS_DGPU_AON

    UV31
    N18S-G5_FCBGA603 FP_FUSE_GPU
    GPU_VID0 6 1
    F3 ADC_IN GPIO0 C6 To DGPU VR @ VIN1 VOUT1 FP_FUSE_GPU [29]
    GPIO0_GC6_FB_EN GPU_VID0 [103] 5 2
    F4 ADC_IN# GPIO1 B2 RV29 1 @ 2 0_0402_5% VIN2 VOUT2
    GPU_EVENT#_D GC6_FB_EN1V8 [12,31] 1
    D6 2 1

    1
    GPIO2 GPU_EVENT#_1V8 [12] UV1N 4 3 GPIO18_FP_FUSE
    C7 DV1 @DIS@ RB751V-40_SOD323-2 CV201 VSS EN 1
    GPIO3 3/14 JTAG
    F9 DGPU_MAIN_EN 2.2U_0402_6.3V6M CV202 RV457

    2
    GPIO4 DGPU_MAIN_EN [37,103] GS7616SC-R_SOT363-6
    GPIO5 A3 DIS@ 2 2.2U_0402_6.3V6M 2.21K_0201_1%
    DIS@ RV117
    GPIO6 A4 PSI GPU_JTAG_TCK DIS@ 2 DIS@
    PSI [103] T231 TP@ AE5 10K_0201_5%
    B6 JTAG_TCK

    2
    GPIO7 GPU_JTAG_TDI AE6 DIS@
    GPIO8 E9 MEM_VDD_CTL T242 TP@ JTAG_TDI
    GPU_JTAG_TDO AF6
    F8 GPIO9_ALERT# RV4050 2 DIS@ 1 0_0402_5% T243 TP@ JTAG_TDO

    1
    GPIO9 GPU_ALERT# [58] GPU_JTAG_TMS AD6
    GPIO10 C5 MEM_VREF T232 TP@ JTAG_TMS
    MEM_VREF [35] GPU_JTAG_TRST# AG4
    GPIO11 E7 GPU_TESTMODE JTAG_TRST#
    VGA_AC_DET AD9
    GPIO12 D7 2 1 NVJTAG_SEL
    GPU_PROHOT# [58]
    GPIO13 B4 DV2 DIS@ RB751V-40_SOD323-2
    GPIO14 B3
    GPIO15 C3 +1.8VS_DGPU_AON
    GPIO16 D5
    GPIO17
    D4
    C2 GPIO18_FP_FUSE
    GPIO18
    GPIO19
    F7 Link to PCH SML1
    GPIO20
    E6
    GPIO21
    C4 PU @ PCH SIDE

    2
    A7 ADC_MUX_SEL
    GPIO22 TP@ T82
    B7

    G
    GPIO23
    I2CS_SCL 1 6
    EC_SMB_CK2 [58,66]

    D
    N18S-G5_FCBGA603
    N18S-G5_FCBGA603 QV147B
    @ PJT138KA_SOT363-6
    @
    +1.8VS_DGPU_AON DIS@ VGS(Max) : 1.1 V

    5
    UV1K

    G
    10/14 MISC2
    I2CS_SDA 4 3
    EC_SMB_DA2 [58,66]

    D
    QV147A
    PJT138KA_SOT363-6
    B ROM_CS# D12 ROM_CS# DIS@ B
    +3VS

    1
    B12 ROM_SI
    ROM_SI
    ROM_SO
    Internal Thermal Sensor
    ROM_SO A12 RV2494 +1.8VS_DGPU_AON
    STRAP0 D1 C12 ROM_SCLK 10K_0201_5%

    2
    STRAP0 ROM_SCLK
    STRAP1 D2 STRAP1 DIS@
    UV23 RV60 @DIS@
    STRAP2 E4 ROM_CS# DIS@
    STRAP2 RV120 1 2 33_0201_5% ROM_CS#_R 1 8 10K_0402_5%

    2
    STRAP3 E3 STRAP3 ROM_SO CS# VCC
    2 7 1
    STRAP4 D3 STRAP4 DO(IO1) HOLD#(IO3) ROM_SCLK
    3 6 RV119 1 DIS@ 2 33_0201_5% CV173 DV3 @DIS@
    STRAP5 C1

    1
    STRAP5 4 WP#(IO2) CLK 5 RV121 1 DIS@ 2 33_0201_5% ROM_SI 0.1U_0201_10V6K RB751V-40_SOD323-2
    GND DI(IO0) 9 DIS@ VGA_AC_DET 2 1
    GND 2 AC_PRESENT [11,58]

    GPU_BUFRST W25Q80EWZPIG_WSON8_6X5
    BUFRST# D11
    DIS@
    @DIS@
    RV61 1 2 0_0402_5%

    N18S-G5_FCBGA603
    @

    N18S -G5 Strap STRAP N18S -G5 VRAM Strap


    +1.8VS_DGPU_AON
    +1.8VS_DGPU_AON
    ROM_SO ROM_SI ROM_SCLK STRAP3 STRAP4 STRAP5 RAM_CFG STRAP2 STRAP1 STRAP0
    1
    1

    10K_0402_1%
    100K_0402_5%

    100K_0402_5%

    1
    100K_0402_5%

    100K_0402_5%

    100K_0402_5%

    100K_0402_5%

    100K_0402_5%

    100K_0402_5%
    RV115 RV113 RV114 RV2500 RV2499 RV2505 0x1(LLH)
    RV124
    RV123

    RV126

    RV2501 RV2502 RV116


    RV2504

    RV2495

    RV2496

    RV2497

    RV2498

    RV116
    DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
    100K_0402_5% 100K_0402_5% 100K_0402_5%
    10K_0402_5% 100K_0402_5% 100K_0402_5% 100K_0402_5% 100K_0402_5% 100K_0402_5% @ @ @ @ @ @
    VRAM_M2G@ VRAM_M2G@ VRAM_M2G@
    M2G
    2
    2

    2
    @ @ @
    C STRAP0 C
    ROM_SO STRAP1 0x0(LLL) RV2501 RV2502 RV2503
    ROM_SI STRAP2 100K_0402_5% 100K_0402_5% 100K_0402_5%
    ROM_SCLK STRAP3 VRAM_S2G@ VRAM_S2G@ VRAM_S2G@
    STRAP4 S2G
    STRAP5
    1

    1
    100K_0402_5%

    100K_0402_5%

    10K_0402_1%
    RV114

    RV113

    RV115

    1
    1

    1
    100K_0402_5%

    100K_0402_5%
    100K_0402_5%

    100K_0402_5%

    100K_0402_5%

    100K_0402_5%
    RV2499

    RV2500
    RV2505

    RV2501

    RV2502

    RV2503

    @ @ @ @ @ @
    2

    2
    2

    @ @ @
    2

    2
    2

    D D

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2019/11/27 Deciphered Date 2020/11/27 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    NV(4/5)-GPIO/Strap
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 2.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K321P
    Date: Thursday, June 03, 2021 Sheet 30 of 121
    1 2 3 4 5
    1 2 3 4 5

    UV1B
    2/14 FBA
    [35] FB_A_D[0..31] FB_A_D0 E18
    FB_A_D1
    FB_A_D2
    F18
    E16
    FBA_D0
    FBA_D1 For GC6 Normal:1.8V
    GC6:1.3V
    FB_A_D3 FBA_D2
    F17
    FB_A_D4 D20
    FBA_D3 SC600000B00 (Main) : VIH(min) = 1.0V
    FB_A_D5 D21
    FBA_D4 SC600001Q00 (2nd) : VIH(min) = 1.0V
    FB_A_D6 FBA_D5
    F20
    FB_A_D7 FBA_D6
    E21
    FB_A_D8 FBA_D7
    E15
    FB_A_D9 FBA_D8
    D15
    FB_A_D10 FBA_D9
    F15 DV6 GC6@
    FB_A_D11 FBA_D10 GC6_FB_EN1V8
    F13 2
    FB_A_D12 FBA_D11 [12,30] GC6_FB_EN1V8
    C13 1
    FB_A_D13 B13
    FBA_D12
    1 2 3 1.35V_PWR_EN [108]
    @
    FB_A_D14 E13
    FBA_D13 [27,103] DGPU_PWROK
    A RV2507 0_0402_5% A
    FBA_D14

    1
    FB_A_D15 D13 BAV70W_SOT323-3
    FB_A_D16 B15
    FBA_D15 @DIS@ 2
    RV2508 1 0_0402_5% SC600000B00 RV2462
    FB_A_D17 C16
    FBA_D16 [37,110] 1.0VSDGPU_PG
    16.5K_0402_5%
    FB_A_D18 FBA_D17
    A13 RV68 1 2 0_0402_5% DIS@
    FB_A_D19 FBA_D18
    A15 NOGC6@

    2
    FB_A_D20 FBA_D19
    B18
    FB_A_D21 FBA_D20
    A18 Stuff RV68 if not support GC6
    FB_A_D22 FBA_D21
    A19
    FB_A_D23 FBA_D22
    C19
    FB_A_D24 FBA_D23
    B24
    FB_A_D25 FBA_D24
    C23
    FB_A_D26 FBA_D25
    A25
    FB_A_D27 FBA_D26
    A24
    FB_A_D28 FBA_D27
    A21
    FB_A_D29 FBA_D28
    B21
    FB_A_D30 C20
    FBA_D29 FB_A_CMD[0..33] [35]
    FB_A_D31 FBA_D30
    C21
    [35] FB_A_D[32..63] FB_A_D32 R22
    FBA_D31
    FB_A_D33 FBA_D32 FB_A_CMD0
    R24 C27
    FB_A_D34 FBA_D33 FBA_CMD0 FB_A_CMD1
    T22 C26
    FB_A_D35 FBA_D34 FBA_CMD1 FB_A_CMD2
    R23 E24
    FB_A_D36 FBA_D35 FBA_CMD2 FB_A_CMD3
    N25 F24
    FB_A_D37 FBA_D36 FBA_CMD3 FB_A_CMD4
    N26 D27
    FB_A_D38 FBA_D37 FBA_CMD4 FB_A_CMD5
    N23 D26
    FB_A_D39 FBA_D38 FBA_CMD5 FB_A_CMD6
    N24 F25
    FB_A_D40 FBA_D39 FBA_CMD6 FB_A_CMD7
    V23 F26
    FB_A_D41 V22
    FBA_D40 FBA_CMD7
    F23 FB_A_CMD8 +1.2VS_VRAM
    FB_A_D42 FBA_D41 FBA_CMD8 FB_A_CMD9
    T23 G22
    FB_A_D43 FBA_D42 FBA_CMD9 FB_A_CMD10
    U22 G23
    FB_A_D44 FBA_D43 FBA_CMD10 FB_A_CMD11 FB_A_CMD10
    Y24 G24 FBA_CKE_L RV69 1 DIS@ 2 10K_0201_1%
    FB_A_D45 FBA_D44 FBA_CMD11 FB_A_CMD12 FB_A_CMD26
    AA24 F27 FBA_CKE_H RV70 1 DIS@ 2 10K_0201_1%
    FB_A_D46 FBA_D45 FBA_CMD12 FB_A_CMD13
    Y22 G25
    FB_A_D47 FBA_D46 FBA_CMD13 FB_A_CMD14
    AA23 G27
    FB_A_D48 FBA_D47 FBA_CMD14 FB_A_CMD15 FB_A_CMD2
    AD27 G26 FBA_RST_L RV71 1 DIS@ 2 10K_0201_1%
    FB_A_D49 FBA_D48 FBA_CMD15 FB_A_CMD16 FB_A_CMD18
    AB25 M24 FBA_RST_H RV72 1 DIS@ 2 10K_0201_1%
    FB_A_D50 FBA_D49 FBA_CMD16 FB_A_CMD17
    AD26 M23
    FB_A_D51 FBA_D50 FBA_CMD17 FB_A_CMD18
    AC25 K24
    FB_A_D52 FBA_D51 FBA_CMD18 FB_A_CMD19
    AA27 K23
    B FB_A_D53 FBA_D52 FBA_CMD19 FB_A_CMD20 B
    AA26 M27
    FB_A_D54 FBA_D53 FBA_CMD20 FB_A_CMD21
    W26 M26
    FB_A_D55 FBA_D54 FBA_CMD21 FB_A_CMD22
    Y25 M25
    FB_A_D56 FBA_D55 FBA_CMD22 FB_A_CMD23
    R26 K26
    FB_A_D57 FBA_D56 FBA_CMD23 FB_A_CMD24
    T25 K22
    FB_A_D58 FBA_D57 FBA_CMD24 FB_A_CMD25
    N27 J23
    FB_A_D59 FBA_D58 FBA_CMD25 FB_A_CMD26
    R27 J25
    FB_A_D60 FBA_D59 FBA_CMD26 FB_A_CMD27
    V26 J24
    FB_A_D61 FBA_D60 FBA_CMD27 FB_A_CMD28
    V27 K27
    FB_A_D62 FBA_D61 FBA_CMD28 FB_A_CMD29
    W27 K25
    FB_A_D63 FBA_D62 FBA_CMD29 FB_A_CMD30
    W25 J27
    FBA_D63 FBA_CMD30 FB_A_CMD31
    J26
    FBA_CMD31 FB_A_CMD32 +1.2VS_GPU
    B19
    [35] FB_A_DBI[3..0] FB_A_DBI0 D19
    FBA_CMD32
    F22 FB_A_CMD33
    FBA_DQM0 @DIS@
    FB_A_DBI1 FBA_CMD34 FB_A_DEBUG1
    D14 FBA_DQM1
    J22 R463 1 2 60.4_0402_1%
    FB_A_DBI2 FBA_CMD35
    C17 FBA_DQM2
    FB_A_DBI3 C22
    [35] FB_A_DBI[7..4] FBA_DQM3
    FB_A_DBI4 P24 FBA_DQM4
    FB_A_DBI5 W24 FBA_DQM5
    FB_A_DBI6 AA25 FBA_DQM6
    FB_A_DBI7 U25 FBA_DQM7

    [35] FB_A_EDC[3..0] FB_A_EDC0 E19 FBA_DQS_WP0


    FB_A_EDC1 C15 FBA_DQS_WP1
    FB_A_EDC2 B16 D24
    FBA_DQS_WP2 FBA_CLK0 FB_A_CLK0 [35]
    FB_A_EDC3 B22 D25
    [35] FB_A_EDC[7..4] FBA_DQS_WP3 FBA_CLK0# FB_A_CLK#0 [35]
    FB_A_EDC4 R25 N22
    FBA_DQS_WP4 FBA_CLK1 FB_A_CLK1 [35]
    FB_A_EDC5 W23 M22
    FBA_DQS_WP5 FBA_CLK1# FB_A_CLK#1 [35]
    FB_A_EDC6 AB26 FBA_DQS_WP6
    FB_A_EDC7 T26 FBA_WCK01 D18
    FBA_DQS_WP7 FB_A_WCK01 [35]
    FBA_WCK01# C18 FB_A_WCK#01 [35]
    FBA_WCKB01 A17
    FB_A_WCKB01 [35]
    F19 FBA_DQS_RN0 FBA_WCKB01# A14 FB_A_WCKB#01 [35]
    C14 FBA_DQS_RN1
    A16 FBA_DQS_RN2
    FBA_WCK23 D17
    A22 FBA_WCK23# D16 FB_A_WCK23 [35]
    FBA_DQS_RN3 FB_A_WCK#23 [35]
    P25 FBA_DQS_RN4
    FBA_WCKB23 A23
    W22 FBA_WCKB23# A20 FB_A_WCKB23 [35]
    C FBA_DQS_RN5 C
    AB27 FB_A_WCKB#23 [35]
    FBA_DQS_RN6
    T27 FBA_DQS_RN7 FBA_WCK45 T24
    U24 FB_A_WCK45 [35]
    FBA_WCK45# FB_A_WCK#45 [35]
    FBA_WCKB45 AC27
    Y27 FB_A_WCKB45 [35]
    FBA_WCKB45# FB_A_WCKB#45 [35]
    FBA_WCK67 V24
    FBA_WCK67# V25
    FB_A_WCK67 [35]
    FBA_WCKB67 U27
    FB_A_WCK#67 [35]
    FBA_WCKB67# P27
    FB_A_WCKB67 [35]
    FB_A_WCKB#67 [35]

    FB_PLL_AVDD F16 +1.8VS_DGPU


    PLLAVDD PLLAVDD
    FB_PLL_AVDD P22 Under F16 P22
    DIS@
    FB_REFPLL_AVDD H22 1 2
    DIS@ 2 FB_VREF
    R460 1 49.9_0402_1% D23 LV3
    1U_0201_6.3V6M
    CV181

    1U_0201_6.3V6M
    CV179

    1U_0201_6.3V6M
    CV180

    FB_VREF
    1 1 1 HCB1005KF-300T25_2P
    DIS@ SM01000NV00
    C203 1 2 3.9P_0402_50V8C N18S-G5_FCBGA603
    @
    DIS@

    DIS@

    DIS@

    2 2 2
    22U_0603_6.3V6M
    CV795 DIS@
    4.7U_0402_6.3V6M
    CV111 DIS@

    4.7U_0402_6.3V6M
    CV796 DIS@

    1 1 1
    Near F16 P22 H22

    2 2 2
    D D

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2019/11/27 Deciphered Date 2020/11/27 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    NV(5/5)-MEMORY FBA
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 2.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K321P
    Date: Thursday, June 03, 2021 Sheet 31 of 121
    1 2 3 4 5
    5 4 3 2 1

    D D

    C C

    B B

    A A

    Security Classification
    2019/11/27
    Compal Secret Data
    2020/11/27 Title
    Compal Electronics, Inc.
    Issued Date Deciphered Date
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Reserve
    Size
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
    Custom 2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K321P
    Date: Thursday, June 03, 2021 Sheet 32 of 121
    5 4 3 2 1
    5 4 3 2 1

    D D

    C C

    B B

    A A

    Security Classification
    2019/11/27
    Compal Secret Data
    2020/11/27 Title
    Compal Electronics, Inc.
    Issued Date Deciphered Date
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Reserve
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 2.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K321P
    Date: Thursday, June 03, 2021 Sheet 33 of 121
    5 4 3 2 1
    5 4 3 2 1

    D D

    C C

    B B

    A A

    Security Classification
    2019/11/27
    Compal Secret Data
    2020/11/27 Title
    Compal Electronics, Inc.
    Issued Date Deciphered Date
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Reserve
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 2.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K321P
    Date: Thursday, June 03, 2021 Sheet 34 of 121
    5 4 3 2 1
    5 4 3 2 1

    VRAM A UG11 @ UG12 @

    C2 B4 C2 B4
    [31] FB_A_EDC0 EDC0_A DQ0_A FB_A_D4 [31] [31] FB_A_EDC4 EDC0_A DQ0_A FB_A_D38 [31]
    C13 A3 C13 A3
    GDDR6 CMD Mapping x16 Mode [31] FB_A_EDC1 EDC1_A DQ1_A FB_A_D5 [31] [31] FB_A_EDC5 EDC1_A DQ1_A FB_A_D39 [31]
    T2 B3 T2 B3
    Lower 0..31 Upper 32..63 [31] FB_A_EDC3 EDC0_B DQ2_A FB_A_D7 [31] [31] FB_A_EDC7 EDC0_B DQ2_A FB_A_D36 [31]
    T13 B2 T13 B2
    DRAM1 DRAM2 [31] FB_A_EDC2 EDC1_B DQ3_A FB_A_D6 [31] [31] FB_A_EDC6 EDC1_B DQ3_A FB_A_D37 [31]
    E3 E3
    CHA-Byte 0,1 CHA-Byte 4,5 DQ4_A FB_A_D0 [31] DQ4_A FB_A_D32 [31]
    E2 E2
    DQ5_A FB_A_D1 [31] DQ5_A FB_A_D35 [31]
    D2 F2 D2 F2
    CA0_A CMD0 CMD20 [31] FB_A_DBI0 DBI0#_A DQ6_A FB_A_D2 [31] [31] FB_A_DBI4 DBI0#_A DQ6_A FB_A_D33 [31]
    D13 G2 D13 G2
    CA1_A CMD9 CMD28 [31] FB_A_DBI1 DBI1#_A DQ7_A FB_A_D3 [31] [31] FB_A_DBI5 DBI1#_A DQ7_A FB_A_D34 [31]
    R2 B11 R2 B11
    CA2_A CMD8 CMD21 [31] FB_A_DBI3 DBI0#_B DQ8_A FB_A_D9 [31] [31] FB_A_DBI7 DBI0#_B DQ8_A FB_A_D41 [31]
    R13 A12 R13 A12
    CA3_A CMD32 CMD29 [31] FB_A_DBI2 DBI1#_B DQ9_A FB_A_D13 [31] [31] FB_A_DBI6 DBI1#_B DQ9_A FB_A_D46 [31]
    B12 B12
    CA4_A CMD7 CMD23 DQ10_A FB_A_D8 [31] DQ10_A FB_A_D45 [31]
    B13 B13
    CA5_A CMD11 CMD27 DQ11_A FB_A_D12 [31] DQ11_A FB_A_D47 [31]
    J10 E12 J10 E12
    CA6_A CMD15 CMD30 [31] FB_A_CLK0 CK_T DQ12_A FB_A_D14 [31] [31] FB_A_CLK1 CK_T DQ12_A FB_A_D42 [31]
    K10 E13 K10 E13
    CA7_A CMD14 CMD31 [31] FB_A_CLK#0 CK_C DQ13_A FB_A_D15 [31] [31] FB_A_CLK#1 CK_C DQ13_A FB_A_D43 [31]
    D G10 F13 G10 F13 D
    CA8_A CMD3 CMD19 [31] FB_A_CMD10 CKE#_A DQ14_A FB_A_D10 [31] [31] FB_A_CMD26 CKE#_A DQ14_A FB_A_D40 [31]
    M10 G13 M10 G13
    CA9_A CMD1 CMD17 CKE#_B DQ15_A FB_A_D11 [31] CKE#_B DQ15_A FB_A_D44 [31]
    CABI_A CMD6 CMD22
    U4 U4
    CKE_A CMD10 CMD26 DQ0_B FB_A_D25 [31] DQ0_B FB_A_D63 [31]
    V3 V3
    DQ1_B FB_A_D27 [31] DQ1_B FB_A_D61 [31]
    U3 U3
    CHB-Byte 2,3 CHB-Byte 6,7 DQ2_B FB_A_D24 [31] DQ2_B FB_A_D62 [31]
    J5 U2 J5 U2
    CA0_B CMD4 CMD16 [31] FB_A_CMD6 CABI#_A DQ3_B FB_A_D26 [31] [31] FB_A_CMD22 CABI#_A DQ3_B FB_A_D60 [31]
    K5 P3 K5 P3
    CA1_B CMD12 CMD25 CABI#_B DQ4_B FB_A_D28 [31] CABI#_B DQ4_B FB_A_D59 [31]
    P2 P2
    CA2_B CMD5 CMD24 DQ5_B FB_A_D31 [31] DQ5_B FB_A_D57 [31]
    N2 N2
    CA3_B CMD13 CMD33 DQ6_B FB_A_D30 [31] DQ6_B FB_A_D56 [31]
    M2 M2
    CA4_B CMD7 CMD23 DQ7_B FB_A_D29 [31] DQ7_B FB_A_D58 [31]
    U11 U11
    CA5_B CMD11 CMD27 DQ8_B FB_A_D18 [31] DQ8_B FB_A_D55 [31]
    V12 V12
    CA6_B CMD15 CMD30 DQ9_B FB_A_D16 [31] DQ9_B FB_A_D53 [31]
    RG85 2 DIS@ 1 121_0402_1% J14 U12 RG83 2 DIS@ 1 121_0402_1% J14 U12
    CA7_B CMD14 CMD31 ZQ_A DQ10_B FB_A_D17 [31] ZQ_A DQ10_B FB_A_D54 [31]
    RG84 2 DIS@ 1 121_0402_1% K14 U13 RG86 2 DIS@ 1 121_0402_1% K14 U13
    CA8_B CMD3 CMD19 ZQ_B DQ11_B FB_A_D19 [31] ZQ_B DQ11_B FB_A_D52 [31]
    P12 P12
    CA9_B CMD1 CMD17 DQ12_B FB_A_D23 [31] DQ12_B FB_A_D48 [31]
    P13 P13
    CABI_B CMD6 CMD22 DQ13_B FB_A_D21 [31] DQ13_B FB_A_D50 [31]
    N13 N13
    CKE_B CMD10 CMD26 DQ14_B FB_A_D22 [31] DQ14_B FB_A_D49 [31]
    M13 M13
    DQ15_B FB_A_D20 [31] DQ15_B FB_A_D51 [31]
    RESET* CMD2 CMD18

    N5 H3 N5 H3
    TCK CA0_A FB_A_CMD0 [31] TCK CA0_A FB_A_CMD20 [31]
    F10 G11 F10 G11
    TDI CA1_A FB_A_CMD9 [31] TDI CA1_A FB_A_CMD28 [31]
    N10 G4 N10 G4
    TDO CA2_A FB_A_CMD8 [31] TDO CA2_A FB_A_CMD21 [31]
    F5 H12 F5 H12
    TMS CA3_A FB_A_CMD32 [31] TMS CA3_A FB_A_CMD29 [31]
    H5 H5
    CA4_A FB_A_CMD7 [31] CA4_A FB_A_CMD23 [31]
    H10 H10
    CA5_A FB_A_CMD11 [31] CA5_A FB_A_CMD27 [31]
    J12 J12
    CA6_A FB_A_CMD15 [31] CA6_A FB_A_CMD30 [31]
    D4 J11 D4 J11
    [31] FB_A_W CK01 WCK0_T_A CA7_A FB_A_CMD14 [31] [31] FB_A_W CK45 WCK0_T_A CA7_A FB_A_CMD31 [31]
    D5 J4 D5 J4
    [31] FB_A_W CK#01 WCK0_C_A CA8_A FB_A_CMD3 [31] [31] FB_A_W CK#45 WCK0_C_A CA8_A FB_A_CMD19 [31]
    D11 J3 D11 J3
    [31] FB_A_W CKB01 WCK1_T_A CA9_A FB_A_CMD1 [31] [31] FB_A_W CKB45 WCK1_T_A CA9_A FB_A_CMD17 [31]
    D10 D10
    [31] FB_A_W CKB#01 WCK1_C_A [31] FB_A_W CKB#45 WCK1_C_A
    L3 L3
    CA0_B FB_A_CMD4 [31] CA0_B FB_A_CMD16 [31]
    M11 M11
    CA1_B FB_A_CMD12 [31] CA1_B FB_A_CMD25 [31]
    R4 M4 R4 M4
    [31] FB_A_W CKB23 WCK0_T_B CA2_B FB_A_CMD5 [31] [31] FB_A_W CKB67 WCK0_T_B CA2_B FB_A_CMD24 [31]
    R5 L12 R5 L12
    [31] FB_A_W CKB#23 WCK0_C_B CA3_B FB_A_CMD7 FB_A_CMD13 [31] [31] FB_A_W CKB#67 WCK0_C_B CA3_B FB_A_CMD23 FB_A_CMD33 [31]
    R11 L5 R11 L5
    [31] FB_A_W CK23 WCK1_T_B CA4_B FB_A_CMD11 [31] FB_A_W CK67 WCK1_T_B CA4_B FB_A_CMD27
    R10 L10 R10 L10
    [31] FB_A_W CK#23 WCK1_C_B CA5_B FB_A_CMD15 [31] FB_A_W CK#67 WCK1_C_B CA5_B FB_A_CMD30
    K12 K12
    CA6_B K11 FB_A_CMD14 CA6_B K11 FB_A_CMD31
    CA7_B K4 FB_A_CMD3 CA7_B K4 FB_A_CMD19
    CA8_B K3 FB_A_CMD1 CA8_B K3 FB_A_CMD17
    C +FBA_VREFC K1 CA9_B +1.2VS_VRAM +FBA_VREFC K1 CA9_B +1.2VS_VRAM C
    VREFC VREFC
    C1 C1
    J1 VDDQ1 E1 J1 VDDQ1 E1
    [31] FB_A_CMD2 RESET# VDDQ2 [31] FB_A_CMD18 RESET# VDDQ2
    H1 H1
    VDDQ3 L1 VDDQ3 L1
    B1 VDDQ4 P1 B1 VDDQ4 P1
    D1 VSS1 VDDQ5 T1 D1 VSS1 VDDQ5 T1
    F1 VSS2 VDDQ6 J2 F1 VSS2 VDDQ6 J2
    G1 VSS3 VDDQ7 K2 G1 VSS3 VDDQ7 K2
    M1 VSS4 VDDQ8 C4 M1 VSS4 VDDQ8 C4
    N1 VSS5 VDDQ9 F4 N1 VSS5 VDDQ9 F4
    R1 VSS6 VDDQ10 N4 R1 VSS6 VDDQ10 N4
    U1 VSS7 VDDQ11 T4 U1 VSS7 VDDQ11 T4
    A2 VSS8 VDDQ12 B5
    10UF_0603 X 4 pcs +1.2VS_VRAM A2 VSS8 VDDQ12 B5
    10UF_0603 X 4 pcs +1.2VS_VRAM
    V2
    C3
    VSS9
    VSS10
    VDDQ13
    VDDQ14
    U5
    B10 Close to GDDR6 UG11 V2
    C3
    VSS9
    VSS10
    VDDQ13
    VDDQ14
    U5
    B10 Close to GDDR6 UG12
    teknisi-indonesia.com
    D3 VSS11 VDDQ15 U10 D3 VSS11 VDDQ15 U10

    10U_0402_6.3V6M

    10U_0402_6.3V6M

    10U_0402_6.3V6M

    10U_0402_6.3V6M

    10U_0402_6.3V6M

    10U_0402_6.3V6M

    10U_0402_6.3V6M

    10U_0402_6.3V6M
    F3 VSS12 VDDQ16 C11 F3 VSS12 VDDQ16 C11
    2 2 2 2 2 2 2 2

    CG5

    CG6

    CG7

    CG8
    G3 VSS13 VDDQ17 F11 G3 VSS13 VDDQ17 F11
    M3 VSS14 VDDQ18 N11 M3 VSS14 VDDQ18 N11

    CG1

    CG2

    CG3

    CG4
    N3 VSS15 VDDQ19 T11 N3 VSS15 VDDQ19 T11
    R3 VSS16 VDDQ20 J13 1 1 1 1 R3 VSS16 VDDQ20 J13 1 1 1 1
    T3 VSS17 VDDQ21 K13 T3 VSS17 VDDQ21 K13
    A4 VSS18 VDDQ22 C14 DIS@ DIS@ DIS@ @DIS@ A4 VSS18 VDDQ22 C14 DIS@ @DIS@ DIS@ DIS@
    E4 VSS19 VDDQ23 E14 E4 VSS19 VDDQ23 E14
    H4 VSS20 VDDQ24 H14 H4 VSS20 VDDQ24 H14
    L4 VSS21 VDDQ25 L14 L4 VSS21 VDDQ25 L14
    P4 VSS22 VDDQ26 P14 P4 VSS22 VDDQ26 P14 10UF_0603 X 2 pcs
    VSS23 VDDQ27 10UF_0603 X 2 pcs V4 VSS23 VDDQ27 T14
    V4
    VSS24 VDDQ28
    T14
    22UF_0603 X 6 pcs VSS24 VDDQ28 +1.2VS_VRAM
    22UF_0603 X 6 pcs +1.2VS_VRAM
    C5 C5
    T5
    C10
    VSS25
    VSS26 A1
    +1.2VS_VRAM
    Around GDDR6 UG11
    +1.2VS_VRAM
    T5
    C10
    VSS25
    VSS26 A1
    Around GDDR6 UG12
    T10 VSS27 VDD1 V1 T10 VSS27 VDD1 V1

    CG13

    CG14
    CG12

    CG16
    CG11

    CG15
    A11 VSS28 VDD2 H2 A11 VSS28 VDD2 H2

    CG21

    CG23
    CG22
    CG20
    CG19

    CG24
    VSS29 VDD3

    10U_0402_6.3V6M

    10U_0402_6.3V6M
    E11 VSS29 VDD3 L2 E11 L2 2 2 1 1 1 1 1 1
    2 2 1 1 1 1 1 1

    CG9

    CG10
    10U_0402_6.3V6M

    10U_0402_6.3V6M
    H11 VSS30 VDD4 E5 H11 VSS30 VDD4 E5
    L11 VSS31 VDD5 P5 L11 VSS31 VDD5 P5

    CG17

    CG18
    +1.2VS_VRAM P11 VSS32 VDD6 E10 P11 VSS32 VDD6 E10 1 1 2 2 2 2 2 2

    22U_0603_6.3V6M

    22U_0603_6.3V6M
    22U_0603_6.3V6M

    22U_0603_6.3V6M
    VSS33 VDD7

    22U_0603_6.3V6M

    22U_0603_6.3V6M
    V11 VSS33 VDD7 P10 1 1 2 2 2 2 2 2 V11 P10

    22U_0603_6.3V6M

    22U_0603_6.3V6M
    22U_0603_6.3V6M
    22U_0603_6.3V6M
    22U_0603_6.3V6M

    22U_0603_6.3V6M
    C12 VSS34 VDD8 H13 C12 VSS34 VDD8 H13

    @DIS@
    @DIS@
    VSS35 VDD9 VSS35 VDD9
    1

    @DIS@ D12 L13 D12 L13

    @DIS@
    @DIS@

    @DIS@
    B RG87 F12 VSS36 VDD10 A14 F12 VSS36 VDD10 A14 B
    549_0402_1% G12 VSS37 VDD11 V14 G12 VSS37 VDD11 V14
    M12 VSS38 VDD12 +1.8VS_DGPU_AON M12 VSS38 VDD12 +1.8VS_DGPU_AON
    VSS39 VSS39
    W=16mils N12 N12
    2

    RG88 R12 VSS40 A5 R12 VSS40 A5


    +FBA_VREFC VSS41 VPP1 VSS41 VPP1 @DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
    1 2 T12 V5 @DIS@ DIS@ DIS@ DIS@ DIS@ T12 V5
    @DIS@ A13 VSS42 VPP2 A10 A13 VSS42 VPP2 A10
    VSS43 VPP3
    1

    V13 VSS43 VPP3 V10 V13 V10


    DIS@ RG89

    @DIS@ CG25
    1K_0402_1%

    931_0402_1%
    820P_0402_25V7

    1 VSS44 VPP4 VSS44 VPP4


    B14 B14
    D14 VSS45 D14 VSS45
    1

    D F14 VSS46 G5 F14 VSS46 G5


    2 QG13 2 G14 VSS47 NC1 M5 G14 VSS47 NC1 M5
    2

    [30] MEM_VREF VSS48 NC2 VSS48 NC2


    G BSS138W _SOT323-3 M14 M14
    N14 VSS49 N14 VSS49
    S
    3

    @DIS@ R14 VSS50 R14 VSS50


    U14 VSS51 180-BALL U14 VSS51 180-BALL
    VSS52 SGRAM GDDR6 VSS52 SGRAM GDDR6

    MT61K256M32JE-13-A_FBGA180~D MT61K256M32JE-13-A_FBGA180~D

    4.7UF_0402 X 1 pcs 4.7UF_0402 X 1 pcs


    0.47UF_0201 X 4 pcs 0.47UF_0201 X 4 pcs

    1uF_0201 X 18 pcs Close to +1.8VS_DGPU_AON 1uF_0201 X 18 pcs


    Close to +1.8VS_DGPU_AON
    Close to GDDR6 UG11 +1.2VS_VRAM +1.8VS_DGPU_AON
    Close to GDDR6 UG12 +1.2VS_VRAM
    +1.8VS_DGPU_AON
    CG61

    CG62

    CG43

    CG70

    CG71

    CG72
    CG57

    CG58

    CG59

    CG60

    CG47

    CG48

    CG67

    CG68

    CG69
    CG44

    CG45

    CG46

    CG75

    CG29

    CG30

    CG31

    CG32

    CG51

    CG52

    CG53

    CG66
    CG38

    CG76

    CG28

    CG33

    CG49

    CG50

    CG80
    CG64

    CG65

    CG77

    CG78

    CG79
    CG73

    CG74

    CG63
    CG54

    CG55

    CG56

    CG27
    1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
    1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M
    1U_0201_6.3V6M

    1U_0201_6.3V6M
    4.7U_0402_6.3V6M

    4.7U_0402_6.3V6M
    2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M
    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M
    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M
    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    2 1U_0201_6.3V6M 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M
    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M
    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M
    @DIS@

    @DIS@
    @DIS@

    @DIS@

    @DIS@
    @DIS@

    @DIS@

    @DIS@

    @DIS@
    @DIS@

    @DIS@

    @DIS@

    @DIS@
    A A

    DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@


    DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
    DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2019/11/27 Deciphered Date 2020/11/27 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    N18S_GDDR6_A
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K321P
    Date: Thursday, June 03, 2021 Sheet 35 of 121
    5 4 3 2 1
    5 4 3 2 1

    D D

    C C

    B B

    A A

    Security Classification
    2019/11/27
    Compal Secret Data
    2020/11/27 Title
    Compal Electronics, Inc.
    Issued Date Deciphered Date
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Reserve
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 2.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K321P
    Date: Thursday, June 03, 2021 Sheet 36 of 121
    5 4 3 2 1
    5 4 3 2 1

    +1.8VALW
    QV4 DIS@
    ME2301DC-G_SOT23-3
    +1.8VALW to +1.8VS_DGPU 3
    Discharger

    D
    1

    G
    2
    +5VALW +1.8VALW +1.8VS_DGPU
    QV3 DIS@
    ME2301DC-G_SOT23-3

    2
    +5VALW +1.0VS_DGPU +5VALW
    3

    D
    RV75 1
    47K_0402_5%

    1
    D DIS@ D

    1
    4.7U_0402_6.3V6M
    CV60

    4.7U_0402_6.3V6M
    CV61

    0.1U_0201_10V K X5R
    CV736

    0.1U_0201_10V K X5R
    CV737
    RV76

    G
    1 1 1 1

    2
    DIS@ 47_0603_5% RV78 RV79
    DGPU_MAIN_EN# 1 2 DGPU_MAIN_EN#_GATE DIS@ 100K_0402_1% 22_0603_1% RV80
    DIS@ DIS@ 47K_0402_5%

    2
    RV77 2 2 2 2 DIS@
    1

    2
    @DIS@

    @DIS@
    RV81 4.7K_0402_5%

    1
    0.1U_0201_10V K X5R
    CV59

    DIS@

    DIS@
    0_0402_5%

    6
    D DIS@ D QV5A @DIS@

    1
    DGPU_MAIN_EN 1 @ 2 2 QV148 2 D 1.0VS_DGPU_EN# 2 2N7002KDW_SOT363-6 DGPU_MAIN_EN 1 2
    [30,103] DGPU_MAIN_EN DGPU_MAIN_EN#
    G BSS138W-7-F_SOT323-3 2 G DIS@ RV82 0_0402_5%

    DIS@
    S G

    3
    1U_0201_6.3V6M
    CV62
    S D QV5B S

    1
    1
    QV25 1.0VS_DGPU_EN 5 2N7002KDW_SOT363-6

    3
    2N7002K_SOT23-3 G DIS@
    DIS@ DGPU_MAIN_EN# 5 G
    D
    QV6A

    @DIS@
    S S 2N7002KDW_SOT363-6

    4
    DIS@

    4
    +1.8VALW to +1.8VS_DGPU_AON
    +1.8VS_DGPU_AON
    +5VALW
    +1.8VALW
    QV7 DIS@
    ME2301DC-G_SOT23-3
    2

    D
    1
    RV83
    47K_0402_5%

    1
    DIS@

    G
    2
    1

    4.7U_0402_6.3V6M
    CV64

    1U_0201_6.3V6M
    CV65

    0.1U_0201_10V K X5R
    CV738

    0.1U_0201_10V K X5R
    CV739
    1 1 1 RV84
    +3VALW

    1
    DIS@ 470_0603_5%
    DGPU_PWR_EN# DGPU_PWR_EN#_GATE @DIS@ +3VALW +3VS 1 @ 2
    RV2509 0_0402_5%

    2
    2 2 2

    0.1U_0201_10V K X5R
    CV63
    RV85
    +3VS
    10K_0402_5% 1 @DIS@

    1
    1
    @DIS@

    @DIS@

    DIS@

    DIS@
    1 2
    D
    G 2 DGPU_PWR_EN# RV106 RV108 RV2510 0_0402_5%
    RV86 1 @ 2 0_0402_5% S 100K_0402_5% 10K_0402_5%
    2 QV6B DIS@ DIS@ DIS@
    C Output 3.3V C

    5
    DIS@
    DV8 @ 2N7002KDW_SOT363-6 UV10
    SA00009WE00 (Main) : VIH(min) = 1.2V

    2
    2
    1

    DGPU_PWR_EN 2 D DIS@ DV4 @DIS@

    VCC
    [12,58] DGPU_PWR_EN 1.8VSDGPU_MAIN
    1 2 QV149 1 @ 2 1 RB751S-40_SOD523-2
    +1.35VGS_PGOOD IN B GPUCORE_EN VGA_CORE_EN
    R4044 1 @ 2 220K_0402_5% 3 G BSS138W-7-F_SOT323-3
    RV451 0_0402_5%
    4 1 2
    VGA_CORE_EN [103]
    OUT Y
    1U_0201_6.3V6M
    CV66 @DIS@

    S DIS@ 2

    GND
    3

    IN A
    1

    3
    BAV70W_SOT323-3
    5 1 DIS@ 2
    D
    SC600000B00 1
    G

    1 S QV152A NL17SZ08DFT2G_SC70-5 CV197


    CV741
    2

    3
    PJT138KA_SOT363-6 RV105 0.1U_0201_10V6K
    0.1U_0201_10V6K

    4
    DIS@ 30K_0402_1% @DIS@
    @ 2
    2

    6
    DGPU_MAIN_EN 2
    D
    QV152B DGPU_PWR_EN
    +3VS
    G
    Output 2.6V
    PJT138KA_SOT363-6
    SA0000ACG00(Main) : VIH(min) = 1.6V
    S

    DIS@ DV5 DIS@

    1
    RB751S-40 SOD-523

    2
    1 2 1.0VS_DGPU_EN
    1.0VS_DGPU_EN [110]
    RV256
    2

    100K_0402_5%
    RG82
    @DIS@ 1 DIS@ 2
    10K_0402_5%
    1

    1
    DIS@ RV103 CV196
    DIS@ 100K_0402_1% 0.1U_0201_10V6K
    1

    DG2 1 2 RB751V-40_SOD323-2 DIS@


    [31,110] 1.0VSDGPU_PG 2
    +1.35VGS_PGOOD RG2 1 @ 2 0_0402_5%
    [108] +1.35VGS_PGOOD DGPU_ALL_PGOOD [12]

    B B

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2019/11/27 Deciphered Date 2020/11/27 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    DGPU_DC/DC Interface
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
    2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K321P
    Date: Thursday, June 03, 2021 Sheet 37 of 121
    5 4 3 2 1
    5 4 3 2 1

    LCD POWER SWITCH CAMERA POWER CIRCUIT


    +3VS +3VS_CMOS

    +3VS +LCDVDD_CONN
    W=60mils W=60mils
    D
    U5 W=20mils W=20mils D
    5 1 +LCDVDD R2 1 @ 2 0_0805_5% R3 1 @ 2 0_0603_5%
    IN OUT
    1 1
    2 1 C5 C6
    GND 0.1U_0201_10V6K 10U_0402_6.3V6M
    1

    C4 4 3 C3 @
    1U_0201_6.3V6M EN OC 4.7U_0402_6.3V6M 2 2
    EM5203AJ-20 SOT23 5P 2
    2

    SA00008R900
    [6] PCH_ENVDD

    1
    R4
    100K_0402_5%
    +3VS_IR

    IR POWER +3VS
    W=40mils

    2
    R364 1 @ 2 0_0603_5%

    DISPLAY OFF HOT PLUG DETECT


    C C

    R5 1 @ 2 0_0402_5% DISPOFF# EDP_HPD


    Through EC [12,58] BKOFF# [6] EDP_HPD

    1
    2
    R8
    R7
    100K_0402_5%

    C
    os
    e
    co
    nn
    100K_0402_5%

    l
    2
    1
    eDP CONNECTOR +12.6VB

    R9 1 @ 2 0_0805_5%
    +LEDVDD

    1
    JEDP1
    Touch Screen POWER CIRCUIT
    2 1
    1 2
    3 +3VS +3VS_TS
    C7 @ 4 3
    10U_0603_25V6M EDP_HPD 5 4
    2 6 5
    [6] INVPWM 6
    DISPOFF# 7
    B 8 7 B
    +LCDVDD_CONN W=60mils 9 8
    10 9 W=20mils R337 1 TS@ 2 0_0603_5%
    W=20mils
    11 10
    +3VS_TS 11 1 1
    [13] TS_INT#
    12 C230 C231
    13 12 +3VALW 0.1U_0201_10V6K 10U_0402_6.3V6M
    eDP [12,58] TS_I2C_RST# 14 13 TS@ @
    C12 1 2 0.1U_0201_10V6K EDP_TXN1_C 15 14 2 2
    [6] EDP_TXN1 15

    1
    1 2 EDP_TXP1_C 16 3 1

    D
    10K_0201_5%
    C13 0.1U_0201_10V6K
    [6] EDP_TXP1 EDP_TXN0_C 16
    C11 1 2 0.1U_0201_10V6K 17

    RC4062
    [6] EDP_TXN0 17 @ Q201
    C10 1 2 0.1U_0201_10V6K EDP_TXP0_C 18 @
    [6] EDP_TXP0 1 2 EDP_AUXP_C 19 18 ME2301DC-G_SOT23-3
    C9 0.1U_0201_10V6K

    G
    [6] EDP_AUXP

    2
    C8 1 2 0.1U_0201_10V6K EDP_AUXN_C 20 19 SB000013I00
    [6] EDP_AUXN

    2
    RC4061 1 2 0_0201_5% LCD_SELF_TEST 21 20
    @ 22 21
    23 22 R201 1 @ 2 150K_0402_5% TS_EN#_R
    I2C_3_SCL 24 23 [12,58] TS_EN#
    Touch Screen [12] I2C_3_SCL I2C_3_SDA 25 24
    [12] I2C_3_SDA 25 1
    26
    [12,58] TS_DISABLE# 26 C204
    100P_0201_50V8J 27
    1 1 100P_0201_50V8J 28 27 @ 0.1U_0201_10V6K
    CTS11 CTS12 28 2
    TS@ [13] USB20_P6
    29
    TS@ 30 29
    [13] USB20_N6 31 30
    2 2 Camera +3VS_CMOS
    32 31
    W=20mils +3VS_IR 33 32
    34 33
    R360 1 @ 2 0_0402_5% +3V_DMIC 35 34
    +3VS SOC_DMIC_CLK0_R 35
    R358 1 EMI@ 2 HCB1005KF-221T15 36 41
    C
    os
    e
    co
    nn

    [10] SOC_DMIC_CLK0 36 GND


    l

    SM01000Q500 SOC_DMIC_DAT0 37 42
    DMIC from CPU [10] SOC_DMIC_DAT0 38 37 GND 43
    39 38 GND 44
    40 39 GND 45
    40 GND
    1 ACES 50398-04041-001
    A C249 SP010013I00 A
    C
    os
    e
    co
    nn
    l

    27P_0201_25V8 @EMI@ ME@


    +3VS_TS
    2
    D6 @ESD@ RC674 1 TS@ 2 10K_0201_5% TS_INT#
    I2C_3_SCL 3 6 SOC_DMIC_DAT0 RC675 1 @ 2 4.7K_0402_5% TS_I2C_RST#
    I/O2 I/O4 RC662 1 @ 2 1K_0402_5% TS_DISABLE#

    +3VS_TS
    2 5
    GND VDD 2 TS@
    RC678
    1 +3VS_TS_P
    0_0402_5%
    Security Classification
    2019/11/27
    Compal Secret Data
    2020/11/27 Title
    Compal Electronics, Inc.
    +3VS Issued Date Deciphered Date
    SOC_DMIC_CLK0_R 1
    I/O1 I/O3
    4 I2C_3_SDA RC676 1 TS@ 2 1K_0402_5% I2C_3_SDA
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    eDP / Camera / Touch
    2 @ 1 RC677 1 TS@ 2 1K_0402_5% I2C_3_SCL Size Document Number Rev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    CEST236LC5VU-M SOT23-6 RC679 0_0402_5% DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 2.0
    SC300006010 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K321P
    Date: Monday, August 02, 2021 Sheet 38 of 121
    5 4 3 2 1
    5 4 3 2 1

    HDMI +5VS +5V_Display

    UH1

    3
    W=40mils
    OUT
    +1.2V_HDMI 1
    Near Pin20 Near Pin12 Near Pin40 Near Pin31 Near Pin19 IN 1
    CH5
    1
    D
    @ 2 0.1U_0201_10V K X5R D
    +1.2V +1.2V_HDMI CH6 GND
    0.1U_0201_10V K X5R 2
    2
    0.01U_0402_16V7K
    CLS228

    0.01U_0402_16V7K
    CLS225

    0.1U_0201_10V6K
    CLS226

    0.1U_0201_10V6K
    CLS229

    0.1U_0201_10V6K
    CLS222

    0.1U_0201_10V6K
    CLS223
    W = 40mils S IC AP2330W-7 SC59 3P PWR SW
    2 2 2 2 2 2 SA00004ZA00
    RLS3 1 @ 2 0_0603_5%

    1 1 1 1 1 1
    LS@

    LS@

    LS@

    LS@

    LS@

    LS@
    +3VS

    ULS1 LS@
    Near Pin11 Near Pin37
    19 11
    20 VDDTA VDD33 37
    31 VDDTX VDD33
    VDDTX

    0.01U_0402_16V7K
    CLS224

    0.1U_0201_10V6K
    CLS227
    12
    40 VDDRX 30 HDMI_RD_TX_P2 +5V_Display
    VDDRX OUT_D2p 2 2
    29 HDMI_RD_TX_N2
    Near ULS1 OUT_D2n
    CLS9 LS@ 1 2 0.1U_0201_10V6K HDMI_TX_P2 1 27 HDMI_RD_TX_P1 HDMI_CTRL_DAT RH252 2 1 2.2K_0402_5%
    [6] CPU_DP2_P0 HDMI_TX_N2 IN_D2p OUT_D1p HDMI_RD_TX_N1 1 1

    LS@

    LS@
    CLS10 LS@ 1 2 0.1U_0201_10V6K 2 26
    [6] CPU_DP2_N0 IN_D2n OUT_D1n HDMI_CTRL_CLK 2 1 2.2K_0402_5%
    To HDMI RH253
    CLS11 LS@ 1 2 0.1U_0201_10V6K HDMI_TX_P1 4 25 HDMI_RD_TX_P0
    [6] CPU_DP2_P1 HDMI_TX_N1 IN_D1p OUT_D0p HDMI_RD_TX_N0
    CLS12 LS@ 1 2 0.1U_0201_10V6K 5 24
    [6] CPU_DP2_N1 IN_D1n OUT_D0n
    From CPU CLS13 LS@ 1 2 0.1U_0201_10V6K HDMI_TX_P0 6 22 HDMI_RD_CLKP
    [6] CPU_DP2_P2 HDMI_TX_N0 IN_D0p OUT_CKp HDMI_RD_CLKN
    CLS14 LS@ 1 2 0.1U_0201_10V6K 7 21
    [6] CPU_DP2_N2 IN_D0n OUT_CKn
    CLS15 LS@ 1 2 0.1U_0201_10V6K HDMI_CLKP 9 39 CPU_DP2_CTRL_DATA
    CPU_DP2_CTRL_DATA [6]
    [6]
    [6]
    CPU_DP2_P3
    CPU_DP2_N3
    CLS16 LS@ 1 2 0.1U_0201_10V6K HDMI_CLKN 10 IN_CKp
    IN_CKn
    SDA_SRC
    SCL_SRC
    SDA_SNK
    38
    33
    32
    CPU_DP2_CTRL_CLK
    HDMI_CTRL_DAT
    HDMI_CTRL_CLK
    CPU_DP2_CTRL_CLK [6]
    From CPU
    EMI Near JHDMI1
    SCL_SNK To HDMI
    +3VS
    DDCBUF 14 For HDMI
    C
    RLS247 1 @ 2 4.7K_0402_5% 13 DDCBUF/SDA_CTL 3 CPU_DP2_HPD C
    EQ 17 DCIN_EN/SCL_CTL HPD_SRC 34 ISET
    CPU_DP2_HPD [6] TO CPU HDMI_RD_CLKP RH10 1 EMI@ 2 2_0402_1% HDMI_L_CLKP
    I2C_CTL_EN_LS 8 EQ/I2C_ADDR0 ISET 28 HDMI_HPD HDMI_RD_CLKN RH11 1 EMI@ 2 2_0402_1% HDMI_L_CLKN
    I2C_CTL_EN HPD_SNK From HDMI

    RLS249 1 LS@ 2 4.99K_0402_1% 18 HDMI_RD_TX_P0 RH12 1 EMI@ 2 2_0402_1% HDMI_L_TX_P0


    36 REXT HDMI_RD_TX_N0 RH13 1 EMI@ 2 2_0402_1% HDMI_L_TX_N0
    RLS251 1 @ 2 4.7K_0402_5% 23 PD# 15
    From HDMI Re-driver
    PRE 16 CFG / I2C_ADDR1 GND 35
    PRE GND 41 HDMI_RD_TX_P1 RH14 1 EMI@ 2 2_0402_1% HDMI_L_TX_P1
    EPAD HDMI_RD_TX_N1 RH15 1 EMI@ 2 2_0402_1% HDMI_L_TX_N1
    PS8407ATQFN40GTR2A1_TQFN40_5X5

    HDMI_RD_TX_P2 RH16 1 EMI@ 2 2_0402_1% HDMI_L_TX_P2


    HDMI_RD_TX_N2 RH17 1 EMI@ 2 2_0402_1% HDMI_L_TX_N2

    +3VS +3VS +3VS +3VS +3VS


    1
    1

    1
    HDMI_L_CLKP RH2 1 EMI@ 2 150_0402_5% HDMI_L_CLKN
    RLS257 RLS254 RLS255 RLS258 RLS256
    LS@ 4.7K_0402_5% LS@ 4.7K_0402_5% @ 4.7K_0402_5% @ 4.7K_0402_5% 4.7K_0402_5%
    HDMI_L_TX_P0 RH4 1 EMI@ 2 150_0402_5% HDMI_L_TX_N0
    2
    2

    2
    2

    DDCBUF EQ I2C_CTL_EN_LS PRE ISET


    HDMI_L_TX_P1 RH5 1 EMI@ 2 150_0402_5% HDMI_L_TX_N1
    1

    1
    1

    RLS262 RLS307 RLS260 RLS263 RLS261


    @ 4.7K_0402_5% @ 4.7K_0402_5% @ 4.7K_0402_5% @ 4.7K_0402_5% @ 4.7K_0402_5% HDMI_L_TX_P2 RH6 1 EMI@ 2 150_0402_5% HDMI_L_TX_N2
    2

    2
    2

    B B

    +5V_Display

    JHDMI1
    HDMI_HPD 19
    18 HP_DET
    DH1 @ESD@ DH2 @ESD@ DH3 @ESD@ 17 +5V
    HDMI_CTRL_CLK 9 10 1 HDMI_CTRL_CLK HDMI_L_TX_N1 9 10 1 HDMI_L_TX_N1 HDMI_L_CLKN 9 10 1 HDMI_L_CLKN HDMI_CTRL_DAT 16 DDC/CEC_GND
    1 1 1
    HDMI_CTRL_CLK 15 SDA
    HDMI_CTRL_DAT 8 2 HDMI_CTRL_DAT HDMI_L_TX_P1 8 2 HDMI_L_TX_P1 HDMI_L_CLKP 8 2 HDMI_L_CLKP 14 SCL
    9 2 9 2 9 2
    13 Reserved
    HDMI_HPD 7 4 HDMI_HPD HDMI_L_TX_N2 7 4 HDMI_L_TX_N2 HDMI_L_TX_N0 7 4 HDMI_L_TX_N0 HDMI_L_CLKN 12 CEC
    7 4 7 4 7 4
    11 CK- 23
    +5V_Display 6 5 +5V_Display HDMI_L_TX_P2 6 5 HDMI_L_TX_P2 HDMI_L_TX_P0 6 5 HDMI_L_TX_P0 HDMI_L_CLKP 10 CK_shield GND 22
    6 5 6 5 6 5
    HDMI_L_TX_N0 9 CK+ GND 21
    3 3 3 8 D0- GND 20
    3 3 3
    HDMI_L_TX_P0 7 D0_shield GND
    8 8 8 HDMI_L_TX_N1 6 D0+
    5 D1-
    L05ESDL5V0NA-4 SLP2510P8 ESD L05ESDL5V0NA-4 SLP2510P8 ESD L05ESDL5V0NA-4 SLP2510P8 ESD HDMI_L_TX_P1 4 D1_shield
    HDMI_L_TX_N2 3 D1+
    2 D2-
    HDMI_L_TX_P2 1 D2_shield
    D2+
    HEFENG HHF-14A000-2DB
    A DC232007C00 A
    ME@

    Compal Electronics, Inc.

    H
    M
    Security Classification Compal Secret Data

    I
    D
    Issued Date 2019/11/27 Deciphered Date 2020/11/27 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K321P
    Date: Thursday, June 03, 2021 Sheet 40 of 121
    5 4 3 2 1
    5 4 3 2 1

    +5VALW
    +3V_PD_LDO
    1 +3V_PD_LDO

    22U_0603_6.3V6K

    22U_0603_6.3V6K

    22U_0603_6.3V6K
    R374 R412 1 1 1

    CT50

    CT51

    CT52
    4.7K_0201_1% 100K_0201_1%

    teknisi-indonesia.com
    @
    UT1
    2

    2
    2 2 2
    ADCIN1 ADCIN2 A7 G5 TCP0_CC1
    B7 PP5V_1 PA_CC1 H5 TCP0_CC2
    1

    1
    C7 PP5V_2 PA_CC2
    R376 R378 D7 PP5V_3 H8 +TCP0_VBUS
    100K_0201_1% 100K_0201_1% E7 PP5V_4 PA_VBUS_1 G8
    F7 PP5V_5 PA_VBUS_2 F8
    +3VL +3VL_PD
    G7 PP5V_6 PA_VBUS_3 USB TYPE-C ESD Prorector
    2

    2 @ 1 H7 PP5V_7 E8 PA_GATE_VBUS
    D D
    PP5V_8 PA_GATE_VBUS PA_GATE_VBUS [82]
    +3VALW RT64 0_0402_5%
    A4 PA_GATE_SYS VIN_MUX
    2 1 H4 PA_GATE_VSYS PA_GATE_SYS [82]
    @
    RT65 0_0402_5% VIN_3V3 A3 UT2
    1 2 ADCIN1 G4 VSYS
    CT62 10U_0402_6.3V6M ADCIN2 G3 ADCIN_1 B4 TCP0_SBU1 15 1 TCP0_SBU1_CONN

    System Side
    ADCIN_2 PB_GATE_VSYS SBU1 C_SBU1

    Connector Side
    TCP0_SBU2 14 2 TCP0_SBU2_CONN
    C1 D8 SBU2 C_SBU2
    TCP0_PD_HPD G1 GPIO0 PB_GATE_VBUS 7
    [6] TCP0_PD_HPD TCP0_POL A6 GPIO1 TCP0_CC1 12 RPD_G1 4 TCP0_CC1_CONN
    H6 GPIO2 A8 TCP0_CC2 11 CC1 C_CC1 5 TCP0_CC2_CONN
    B3 GPIO3 PB_VBUS_1 B8 +3V_PD_LDO CC2 C_CC2 6
    C2 GPIO4 PB_VBUS_2 C8 RPD_G2
    TCP0_DP_MODE F6 GPIO5 PB_VBUS_3 RT39 1 2 100K_0201_5% +FLT1 9 20
    G6 GPIO6 B5 10 FLT D1 19
    B6 GPIO7 PB_CC1 A5 3 VPWR D2 17
    VR_ALERT# C6 GPIO8 PB_CC2 VBIAS N.C. 16
    [7] VR_ALERT# GPIO9 18 N.C.
    1 GND

    1
    8
    PD_I2C_CK1 E1 CT58 CT59 13 GND
    PD_I2C_DA1 F1 I2C_EC_SCL 0.1U_0201_10V6K 0.1U_0402_50V6K 21 GND

    2
    EC_PD_INT D1 I2C_EC_SDA 2 THERMAL_PAD
    [58] EC_PD_INT I2C_EC_IRQ# SN1710033RUKR WQFN 20P TYPE-C PROTE
    PD_SMB_CK E2 +3V_PD_LDO SA0000CG500
    [9] PD_SMB_CK PD_SMB_DA D2 I2C2s_SCL
    [9] PD_SMB_DA F2 I2C2s_SDA H3
    PMCALERT#
    [11] PMCALERT# I2C2s_IRQ# LDO_3V3 +1.5V_LDO
    H1
    PD0_I2C_RT_SCL_R A2 LDO_1V5_A G2
    PD0_I2C_RT_SDA_R A1 I2C3m_SCL LDO_1V5_B
    I2C3m_SDA_1 2 2
    B2 CT61 CT60
    B1 I2C3m_SDA_2 H2 10U_0402_6.3V6M 10U_0402_6.3V6M
    [58] EC_SMB_CK3
    RT304 1 @ 2 0_0201_5% I2C MAP I2C3m_IRQ# GND
    RT305 1 2 0_0201_5% PD_I2C_CK1 1 1
    [58,83,85] EC_SMB_CK1
    @
    1 EC SN2001024YBGR DSBGA
    [58] EC_SMB_DA3
    RT306 1 @ 2 0_0201_5%
    2 SOC SA0000DOI00
    [58,83,85] EC_SMB_DA1
    RT307 1 @ 2 0_0201_5% PD_I2C_DA1
    3 ROM Close JUSBC2
    C C
    DT7

    TCP0_TTX_C_DRX_P1 1 10 TCP0_TTX_C_DRX_P1
    9 TCP0_TTX_C_DRX_N1
    DT16 ESD@ TCP0_TTX_C_DRX_N1 TCP0_TRX_C_DTX_N2
    TCP0_SBU2_CONN TCP0_CC1_CONN 2 7
    +3V_PD_LDO 3 6 TCP0_TRX_C_DTX_P2
    I/O2 I/O4 6
    +3V_PD_LDO UT3
    Pull high at EC side PD0_I2C_RT_SCL_R 6 8
    PD0_I2C_RT_SDA_R 5 SCL VCC TCP0_TRX_C_DTX_N2 4 8
    SDA 1 2 5
    RT76 1 @ 2 2.2K_0201_5% PD_I2C_CK1 4 CT63 CT212 GND VDD 3
    RT77 1 @ 2 2.2K_0201_5% PD_I2C_DA1 1 VSS 0.1U_0201_25V6K 270P_0402_50V7K TCP0_TRX_C_DTX_P2 5
    RT116 1 @ 2 10K_0201_5% EC_PD_INT 2 A0 TGL_C@
    RT86 1 2 2.2K_0201_5% PD0_I2C_RT_SCL_R 3 A1 7 2
    A2 WP CT213 TCP0_CC2_CONN 1 4 TCP0_SBU1_CONN
    RT87 1 2 2.2K_0201_5% PD0_I2C_RT_SDA_R I/O1 I/O3 CESD2510UC3V3U DFN2510
    1

    1
    1

    CAT24C256WI-GT3_SO8 270P_0402_50V7K
    TGL_C@ CEST236LC5VU-M SOT23-6 ESD@
    +3VALW RT120 RT121 RT80 RT81
    SC300006010 DT8
    10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5% TCP0_CC1 TGL_U@ CT212 1 2 220P_0402_50V7K
    RT302 1 @ 2 0_0201_5%
    DT1 ESD@ TCP0_TTX_C_DRX_P2 TCP0_TTX_C_DRX_P2
    TCP0_CC2 USB20_P3_R 1 10
    TGL_U@ CT213 1 2 220P_0402_50V7K 3 6
    2

    2
    2

    RT83 1 2 2.2K_0201_5% PD_SMB_CK I/O2 I/O4 9 TCP0_TTX_C_DRX_N2


    +3V_PD_LDO
    RT84 1 2 2.2K_0201_5% PD_SMB_DA TCP0_TTX_C_DRX_N2 2 7 TCP0_TRX_C_DTX_N1
    RT303 1 @ 2 0_0201_5% RT117 1 2 10K_0201_5% PMCALERT# 6 TCP0_TRX_C_DTX_P1
    TCP0_PD_HPD RT29 1 2 20K_0402_5%
    TCP0_POL 2 5
    RT299 1 @ 2 1M_0201_5% GND VDD
    TCP0_DP_MODE RT300 1 @ 2 1M_0201_5% TCP0_TRX_C_DTX_N1 4 8
    VR_ALERT# RT301 1 2 1M_0201_5% 3
    TCP0_TRX_C_DTX_P1 5
    1 4 USB20_N3_R
    +3VALW I/O1 I/O3
    CEST236LC5VU-M SOT23-6
    CESD2510UC3V3U DFN2510
    SC300006010
    1

    ESD@
    RT26
    100K_0402_5%
    +3VALW
    UT4
    13 20 TCP0_C_AUX_N CT36 1 2 0.1U_0201_10V6K
    2

    VCC A1_OUTp TCP0_AUX_N [6]


    1 TCP0_SBU1 1 A1_OUTn
    19 TCP0_C_AUX_P CT35 1 2 0.1U_0201_10V6K
    TCP0_AUX_P [6] +TCP0_VBUS
    A_INp
    1

    B TCP0_SBU2 2 18 B
    C99 A_INn A0_OUTp 17 RT25
    0.1U_0201_10V6K A0_OUTn
    R124 1 @ 2 0_0201_5% 14 100K_0402_5%

    10U_0603_25V6M

    0.1U_0201_25V6K

    0.1U_0201_25V6K
    2

    0.1U_0201_25V6K

    0.1U_0201_25V6K
    TCP0_DP_MODE 16 SAI 15 TCP0_POL

    2
    EN_A SAO
    DT6 1 1 1 1 1
    2

    CEST23NC24VU SOT23

    CT70

    CT71
    CT68

    CT53

    CT69
    3 6
    B_INp B1_OUTp ESD@
    4 7 @
    B_INn B1_OUTn 2 2 2 2 2
    R399 1 @ 2 0_0201_5% 12 8 ESD

    1
    10 SBI B0_OUTp 9
    EN_B B0_OUTn
    5 11 Near Pin A4,A9,B4,B9

    USB2.0
    21 GND SBO
    Thermal pad JUSBC2
    A1 B12
    TS3DS10224RUKR_WQFN20_3X3 GND GND
    TCP0_TTX_C_DRX_P1 A2 B11 TCP0_TRX_C_DTX_P1
    TCP0_TTX_C_DRX_N1 A3 SSTXP1 SSRXP1 B10 TCP0_TRX_C_DTX_N1
    LT1 EMI@ SSTXN1 SSRXN1
    1 2 USB20_N3_R A4 B9
    [13] USB20_N3 1 2 VBUS VBUS
    TCP0_CC1_CONN A5 B8 TCP0_SBU2_CONN
    4 3 USB20_P3_R CC1 SBU2
    [13] USB20_P3 4 3 USB20_P3_R A6 B7 USB20_N3_R
    DLM0NSN900HY2D_4P USB20_N3_R A7 DP1 DN2 B6 USB20_P3_R
    DN1 DP2
    SM070005U00
    TCP0_SBU1_CONN A8 B5 TCP0_CC2_CONN
    SBU1 CC2
    A9 B4
    intel SPEC VBUS VBUS
    TCP0_TRX_C_DTX_N2 A10 B3 TCP0_TTX_C_DRX_N2
    [6] TCP0_TTX_DRX_P1
    TCP0_TTX_DRX_P1
    TCP0_TTX_DRX_N1
    CT39 1
    CT40 1
    2 0.22U_0201_25V6K
    2 0.22U_0201_25V6K
    TCP0_TTX_C_DRX_P1
    TCP0_TTX_C_DRX_N1
    Close JUSBC2 TCP0_TRX_C_DTX_P2 A11 SSRXN2
    SSRXP2
    SSTXN2
    SSTXP2
    B2 TCP0_TTX_C_DRX_P2
    [6] TCP0_TTX_DRX_N1
    A12 B1
    GND GND
    TCP0_TTX_DRX_N2 CT41 1 2 0.22U_0201_25V6K TCP0_TTX_C_DRX_N2
    [6] TCP0_TTX_DRX_N2 TCP0_TTX_DRX_P2 TCP0_TTX_C_DRX_P2 TCP0_TRX_C_DTX_N2
    [6] TCP0_TTX_DRX_P2 CT42 1 2 0.22U_0201_25V6K RT31 1 2 220K_0201_5% 1 4
    TCP0_TRX_C_DTX_P2 RT32 1 2 220K_0201_5% 2 GND GND 5
    3 GND GND 6
    A A
    From CPU [6] TCP0_TRX_DTX_N1
    TCP0_TRX_DTX_N1 CT43 1 2 0.33U_0201_25V6K TCP0_TRX_C_DTX_N1 TCP0_TRX_C_DTX_P1 RT33 1 2 220K_0201_5% GND GND
    TCP0_TRX_DTX_P1 CT44 1 2 0.33U_0201_25V6K TCP0_TRX_C_DTX_P1 TCP0_TRX_C_DTX_N1 RT34 1 2 220K_0201_5%
    [6] TCP0_TRX_DTX_P1
    HIGHSTAR UB11249-B200G-1H
    TCP0_TRX_DTX_N2 CT45 1 2 0.33U_0201_25V6K TCP0_TRX_C_DTX_N2
    [6] TCP0_TRX_DTX_N2 SP06000BWB0
    TCP0_TRX_DTX_P2 CT49 1 2 0.33U_0201_25V6K TCP0_TRX_C_DTX_P2
    [6] TCP0_TRX_DTX_P2 ME@

    Security Classification
    2019/11/27
    Compal Secret Data
    2020/11/27 Title
    Compal Electronics, Inc.
    Issued Date Deciphered Date
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    TYPE-C PD TPS65994
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 2.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K321P
    Date: Thursday, June 03, 2021 Sheet 42 of 121
    5 4 3 2 1
    5 4 3 2 1

    D D

    C C

    B B

    A A

    Security Classification
    2019/11/27
    Compal Secret Data
    2020/11/27 Title
    Compal Electronics, Inc.
    Issued Date Deciphered Date
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Reserve
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 2.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K321P
    Date: Thursday, June 03, 2021 Sheet 43 of 121
    5 4 3 2 1
    A B C D E

    NGFF WLAN / BT (Key E) NGFF Wireless LAN / BT (Key E) [PCIE+USB/CNVi]

    +3VS_W LAN +3VALW +3VS_W LAN

    1 Imax : 2.0 A Imax : 2.0 A 1

    1
    1 1 1 CW 61
    CW 1 CW 2 CW 3 1U_0201_6.3V6M
    10U_0402_6.3V6M 0.1U_0201_10V6K 0.01U_0402_16V7K CNVi@

    2
    CNVi@ CNVi@ CNVi@ UW 1 CNVi@
    2 2 2 5 1
    IN OUT
    2
    Close to KEY E pin72,74 GND
    RW 41 1 @ 2 0_0402_5% CNVi_PW R_EN#_R 4 3
    [58] CNVi_PW R_EN# EN(EN#) OC#
    G524B2T11U_SOT23-5
    +3VS_W LAN +3VS_W LAN SA00007BW 00
    1
    CW 9
    1U_0201_6.3V6M
    CNVi@ I (Max) : 2.0 A(+3VS_WLAN)
    2
    1 1 1 RDS(Typ) : 70 mohm
    CW 4 CW 5 CW 6 1
    10U_0402_6.3V6M 0.1U_0201_10V6K 0.01U_0402_16V7K CW 82 @RF@
    V drop : 0.14 V
    CNVi@ CNVi@ CNVi@ 10P_0402_50V8J
    2 2 2
    2 Jefferson Peak:1360mA@peak current
    Thunder_Peak_2:1100mA@peak current
    Close to KEY E pin2,4
    RF
    2 2

    +3VS_W LAN
    CNVi Module PIN Define
    JW LAN1
    GND 1 2 +3P3A
    GND_1 3.3VAUX_2
    [13] USB20_P10 USB_D+ 3 USB_D+ 3.3VAUX_4
    4 +3P3A
    BT [13] USB20_N10 USB_D- 5 USB_D- LED1#
    6 LED#1
    GND 7 8 PCM_CLK
    GND_7 PCM_CLK
    [14] CNV_CRX_DTX_N1 WGR_D1N 9 SDIO_CLK PCM_SYNC
    10 RF_RESET_B CNV_RF_RESET#_R RW 4 1 CNVi@ 2 33_0402_5% CNV_RF_RESET# [10]
    [14] CNV_CRX_DTX_P1 WGR_D1P 11 SDIO_CMD PCM_OUT
    12 PCM_IN
    GND 13 14 CLKREQ0 CLKREQ_CNV#_R RW 6 1 CNVi@ 2 33_0402_5%
    SDIO_DAT0 PCM_IN CLKREQ_CNV# [10]
    [14] CNV_CRX_DTX_N0 WGR_D0N 15 SDIO_DAT1 LED2#
    16 LED2#
    [14] CNV_CRX_DTX_P0 WGR_D0P 17 SDIO_DAT2 GND_18
    18 GND/LNA_EN
    GND 19 SDIO_DAT3 UART_WAKE
    20 UART WAKE#
    WGR_CLKN 21 22 BRI_RSP CNV_BRI_CRX_R_DTX RW 11 1 CNVi@ 2 49.9_0402_1%
    [14] CLK_CNV_CRX_DTX_N SDIO_WAKE UART_TX CNV_BRI_CRX_DTX [14]
    [14] CLK_CNV_CRX_DTX_P WGR_CLKP 23 SDIO_RST
    RW 9 1 RMT@ 2 0_0402_5%
    UART_2_CRXD_DTXD [12]
    RW 13 1 RMT@ 2 0_0402_5%
    Near JWLAN1 24 RGI_DT CNV_RGI_CTX_R_DRX RW 14 1 CNVi@ 2 0_0402_5%
    UART_2_CTXD_DRXD [12]
    CNV_RGI_CTX_DRX [14]
    UART_RX CNV_RGI_CRX_R_DTX
    GND 25 GND_33 UART_RTS
    26 RGI_RSP RW 15 1 CNVi@ 2 49.9_0402_1%
    CNV_RGI_CRX_DTX [14]
    CC82 1 2 0.1U_0201_10V6K PCIE_CTX_C_DRX_P3 PETp0 27 28 BRI_DT CNV_BRI_CTX_R_DRX RW 16 1 CNVi@ 2 0_0402_5% CNV_BRI_CTX_DRX [14]
    [13] PCIE_CTX_DRX_P3 PET_RX_P0 UART_CTS
    CC83 1 2 0.1U_0201_10V6K PCIE_CTX_C_DRX_N3 PETn0 29 30 Clink RESET RW14 & RW16 close to CPU
    [13] PCIE_CTX_DRX_N3 PET_RX_N0 CLink_RST EC_TX [58]
    GND 31 GND_39 CLink_DATA
    32 Clink DATA EC_RX [58]
    [13] PCIE_CRX_DTX_P3 PERp0 33 PER_TX_P0 CLink_CLK
    34 Clink CLK
    WLAN [13] PCIE_CRX_DTX_N3 PERn0 35 PER_TX_N0 COEX3
    36 COEX3
    GND 37 GND_45 COEX2
    38 COEX_RXD PCH EDS : M.2 CNV Mode Select
    [11] CLK_PCIE_P2 REFCLKP039 REFCLK_P0 COEX1
    40 COEX_TXD
    [11] CLK_PCIE_N2 REFCLKN041 REFCLK_N0 SUSCLK(32KHz)
    42 C_P32K SUSCLK_R [11] GPP_F2/CNV_RGI_DT
    3
    GND 43 GND_51 PERST0#
    44 PERST0# PCI_RST# [11,27,58,68,71] 3
    RW L1 1 @ 2 0_0402_5% CLKREQ_PCIE#2_R CLKREQ0#45 46 W_DISABLE2# W LBT_OFF# 0 = Integrated CNVi enable.
    [11] CLKREQ_PCIE#2 CLKREQ0# W_DISABLE2# W LBT_OFF# [10] +1.8VALW
    RW L2 1 @ 2 0_0402_5% W AKE#_R PEWake0#47 48 W_DISABLE1# W L_OFF#
    [58] PCIE_W AKE# PEWAKE0# W_DISABLE1# W L_OFF# [12]
    GND 49 GND_57 I2C_DAT
    50 A4WP_I2C_DATA 1 = Integrated CNVi disable.
    [14] CNV_CTX_DRX_N1 WT_D1N 51 RSVD/PCIE_RX_P1 I2C_CLK
    52 A4WP_I2C_CLK
    [14] CNV_CTX_DRX_P1 WT_D1P 53 RSVD/PCIE_RX_N1 I2C_IRQ
    54 A4WP_IRQ#
    GND 55 56 REFCLK0 REFCLK_CNV_R 1 T464 CNV_RGI_CTX_R_DRX RW 156 1 CNVi@ 2 100K_0402_5%
    GND_63 RSVD_64
    [14] CNV_CTX_DRX_N0 WT_D0N 57 RSVD/PCIE_TX_P1 RSVD_66
    58 PERST1# TP@
    WT_D0P 59 60 CLKREQ1# CNV_BRI_CTX_R_DRX RW 157 1 @ 2 20K_0402_5%
    [14] CNV_CTX_DRX_P0 RSVD/PCIE_TX_N1 RSVD_68 follow ORB
    GND 61 GND_69 RSVD_70
    62 PEWake1#
    [14] CLK_CNV_CTX_DRX_N WT_CLKN63 RSVD_71 3.3VAUX_72
    64 +3P3A
    [14] CLK_CNV_CTX_DRX_P WT_CLKP 65 RSVD_73 3.3VAUX_74
    66 +3P3A
    GND 67 GND_75 68 GND
    69 GND1 EC_TX RW 26 1 2 100K_0402_5%
    GND GND2
    BELLW _80152-3221 CLKREQ_CNV# RW 27 2 CNVi@ 1 10K_0402_5%
    SP070013E00
    ME@

    +3VS_W LAN
    Note: The real behavior of BT_DISABLE are
    BT_DISABLE=LOW, BT=OFF W LBT_OFF# RW 58 2 @ 1 10K_0402_5%
    BT_DISABLE=HIGH, BT=ON
    W L_OFF# RW 59 2 @ 1 10K_0402_5%
    4 4
    CLKREQ_PCIE#2_R RW 61 2 @ 1 10K_0402_5%

    Security Classification
    2019/11/27
    Compal Secret Data
    2020/11/27 Title
    Compal Electronics, Inc.
    Issued Date Deciphered Date
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    NGFF WLAN / BT
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 2.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K321P
    Date: Thursday, June 03, 2021 Sheet 52 of 121
    A B C D E
    A B C D E

    RF
    HDA_SYNC_R
    HDA_BIT_CLK_R
    @RF@
    @RF@
    CA30
    CA31
    1
    1
    2
    2
    2.2P_0402_50V8C
    2.2P_0402_50V8C Speaker
    ALC3287 HDA_SDOUT_R
    HDA_SDIN0
    @RF@
    @RF@
    CA32
    CA33
    1
    1
    2
    2
    2.2P_0402_50V8C
    2.2P_0402_50V8C

    UA1
    EMI
    34 PC_BEEP SPEAK 4 ohm : 40MIL
    6 PCBEEP SPEAK 8 ohm : 20MIL
    I2C_DATA 30 EXT_MIC_RING2 JSPK1
    7 MIC2-L/RING2 SPK_L1- RA5 1 @EMI@ 2 0_0603_5% SPK_L1-_CONN 1
    I2C_CLK 31 EXT_MIC_SLEEVE SPK_L2+ RA6 1 @EMI@ 2 0_0603_5% SPK_L2+_CONN 2 1
    HDA_SYNC_R 15 MIC2-R/SLEEVE SPK_R1- RA1 1 @EMI@ 2 0_0603_5% SPK_R1-_CONN 3 2
    [10] HDA_SYNC_R SYNC SPK_R2+ SPK_R2+_CONN 3
    1
    36 RA3 1 @EMI@ 2 0_0603_5% 4 1
    HDA_BIT_CLK_R 14 LINE2-L 4
    [10] HDA_BIT_CLK_R BCLK

    1000P_0402_50V7K

    1000P_0402_50V7K

    1000P_0402_50V7K

    1000P_0402_50V7K
    35 5
    HDA_SDOUT_R LINE2-R GND1

    CA2

    CA3

    CA4

    CA5
    17 6
    [10] HDA_SDOUT_R SDATA-OUT SPK_L2+ GND2
    42 1 1 1 1
    13 SPK-OUT-L+ ACES_50271-0040N-001
    DC_DET/EPAD SPK_L1-

    EMI@

    EMI@

    EMI@

    EMI@
    RA2 43 SP02000TS00
    HDA_SDIN0 1 2 HDA_SDIN0_R 16 SPK-OUT-L-
    [10] HDA_SDIN0
    33_0402_5% SDATA-IN 44 SPK_R1- Speaker 2 2 2 2 ME@
    11 SPK-OUT-R- Speaker Connector PN
    NC 45 SPK_R2+ SP02000RR00
    10 SPK-OUT-R+
    EMI NC
    HPOUT-L
    27 HP_OUTL

    CA1 @EMI@ RA4 @EMI@ 9 26 HP_OUTR Headphone +5VS


    2 1 HDA_BIT_CLK_R NC HPOUT-R
    12 DA2 @ESD@
    22P_0402_50V8J 33_0402_5% NC SPK_R1-_CONN 6 3 SPK_L2+_CONN
    8 I/O4 I/O2
    NC
    1
    SPDIF-OUT/GPIO2/DMIC-DATA34/DMIC-CLK-IN 5 2
    4 VDD GND
    GPIO0/DMIC-DATA12
    5
    GPIO1/DMIC-CLK SPK_R2+_CONN 4 1 SPK_L1-_CONN
    RA8 1 @ 2 0_0402_5% PDB 2 I/O3 I/O1
    [58] EC_MUTE# PDB AZC099-04S.R7G_SOT23-6
    PLUG_IN_R 48
    JD1 SC300001G00
    47
    JD2

    +5VDDA_CODEC
    ESD
    GNDA

    CA7 1 2 2.2U_0402_6.3V6M VREF 38


    VREF
    2
    EMI 2
    GNDA

    CA8 1 2 2.2U_0402_6.3V6M LDO1 39


    LDO1-CAP
    GNDA

    CA9 1 2 2.2U_0402_6.3V6M 32 33 RA9 1 2 10K_0402_5% SM010009U00


    MIC2-CAP 5VSTB SM010009U00
    40 EXT_MIC_SLEEVE EMI@ RA14 2 1 BLM15BD121SN1D_2P HGNDB
    EXT_MIC_SLEEVE AVDD1 W=40mils EXT_MIC_RING2
    RA10 1 2 2.2K_0402_5% 29 W=40mils EMI@ RA13 2 1 BLM15BD121SN1D_2P HGNDA
    MIC2-VREFO-R 20 HP_OUTL RA15 1 EMI@ 2 47_0402_5% HPOUT_L
    wide 40MIL EXT_MIC_RING2 RA11 1 2 2.2K_0402_5% 28
    MIC2-VREFO-L
    CPVDD/AVDD2
    3
    +1.8VDD_CODEC HP_OUTR RA16 1 EMI@ 2 47_0402_5% HPOUT_R

    DVDD +3VDD_CODEC +5VS


    18 +IOVDD_CODEC
    DVDD-IO

    10K_0402_5%

    10K_0402_5%

    1000P_0402_50V7K
    CA16 EMI@

    1000P_0402_50V7K
    CA17 EMI@

    220P_0402_50V7K
    CA18 EMI@

    220P_0402_50V7K
    CA19 EMI@
    2

    2
    +5VS_PVDD

    RA17 @

    RA18 @
    GNDA

    CA10 1 2 1U_0201_6.3V6M 25 41 RA12 1 @ 2 0_0805_5% 1 1


    CPVEE PVDD1

    2
    24 46
    CBN PVDD2

    4.7U_0402_6.3V6M

    0.1U_0201_10V6K
    1 1

    1
    CA11 1 2 1U_0402_6.3V6K 23 49 CA12 CA13 2 2

    1
    CBP Thermal_Pad
    GNDA

    CA14 1 2 2.2U_0402_6.3V6M LDO2 21 37


    LDO2-CAP AVSS1 2 2 GNDA GNDA GNDA GNDA GNDA GNDA
    CA15 1 2 2.2U_0402_6.3V6M LDO3 19 22
    LDO3-CAP AVSS2
    Follow LAH101P un-stuff CA16, stuff CA35

    ALC3287-CG_MQFN48_6X6
    Close Audio codec

    GNDA +3VS

    1
    ESD@
    Combo Jack
    RT75
    100K_0402_1%
    (Normal Open)
    Follow ELZ02 pin number

    2
    3 +5VS --> +5VDDA_CODEC +3VS --> +IOVDD_CODEC +3VS --> +3VDD_CODEC HGNDA / HGNDB , W=60mils
    PLUG_IN_R RA33 1 2 200K_0402_1% PLUG_IN
    JP3 3

    HGNDA 2
    +5VS +5VDDA_CODEC +3VS +IOVDD_CODEC +3VS +3VDD_CODEC HPOUT_R 3
    PLUG_IN 6

    RA19 1 @ 2 0_0603_5% RA20 1 @ 2 0_0603_5% RA21 1 @ 2 0_0402_5% 5


    0.1U_0201_10V6K

    1
    0.1U_0201_10V6K

    2.2U_0402_6.3V6M

    CA20
    1 1 0.1U_0201_10V6K 1
    CA21 CA28 CA22 HPOUT_L 4
    2
    2 2 2 HGNDB 1

    YUQIU_1603046-01611

    2
    3

    CEST23LC5VB C/A SOT-23


    DA4 @ESD@
    CEST23LC5VB C/A SOT-23
    DA3 ESD@
    DC23000H100

    SCA00004300
    SCA00004300

    1
    ME@
    Place near Pin40 Place near Pin18 Place near Pin3 RA24
    2 33K_0402_5%
    CA35 @ESD@
    GNDA 2200P_0402_25V7K

    2
    ESD@
    1 RA34 1 @ 2 0_0402_5%

    1
    1
    +1.8VS --> +1.8VDD_CODEC PC Beep RA35 1 @ 2 0_0402_5%

    GNDA GNDA
    RA31 1 @ 2 0_0402_5%
    +1.8VS +1.8VDD_CODEC

    RA25 1 @ 2 0_0402_5%
    [58] BEEP# RA27 1 2 4.7K_0402_5% CA25 1 2 0.1U_0201_10V6K PC_BEEP ESD RA26 1 @ 2 0_0402_5%

    4 [12,58] HDA_SPKR RA29 1 2 4.7K_0402_5% 4


    1
    0.1U_0201_10V6K

    2.2U_0402_6.3V6M

    1 1 Place near Pin34 RA28 1 @ 2 0_0402_5%

    CA24 CA6 RA30


    0_0402_5% RA32 1 @ 2 0_0402_5%
    2 2 @
    2

    GND GNDA
    Security Classification
    2019/11/27
    Compal Secret Data
    2020/11/27 Title
    Compal Electronics, Inc.
    Place near Pin20 Issued Date Deciphered Date
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Audio Codec_Realtek ALC3287
    GNDA AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K321P
    Date: Thursday, June 03, 2021 Sheet 56 of 121
    A B C D E
    5 4 3 2 1

    +3VALW +3VL +3VL_EC_VCC0

    R3991 1 @ 2 0_0402_5% R3992 1 @ 2 0_0402_5%


    +VTT_EC +1.05V_VCCST
    +3VL +3VL_EC +EC_VCCA

    +3VS +3VALW +1.8VALW


    R3985 1 @ 2 0_0603_5% L17 1 2 BLM15AX601SN1D _2P

    2.2K_0402_5%

    2.2K_0402_5%
    SM01000KL00 1 remove R-short for reduce net without test point

    1
    +1.8VALW_ESPI

    R3988

    R3989
    +1.8VALW

    0.1U_0201_10V6K

    0.1U_0201_10V6K
    1 1 1 C234
    +3VL_EC_VCC0

    C237

    C236
    Q5A TS@ 0.1U_0201_10V6K
    2N7002KDW 2N SC88-6 R3984 1 @ 2 0_0402_5% C235 2

    2
    @

    @
    D
    SB00000EO00 0.1U_0201_10V6K Vendor suggest D

    2
    +1.8VALW 2 2 +VTT_EC 2
    TS_EN# 6 1 EC_TS_EN#
    [12,38] TS_EN#

    5
    1 ECAGND
    C238

    111

    117

    124
    PCIE_WAKE# 3 4 EC_PCIE_WAKE# 1U_0201_6.3V6M

    22
    33
    96

    67
    [52] PCIE_WAKE# U11

    9
    Q5B TS@ 2

    PECI_VTT
    VCC
    VCC
    VCC

    AVCC
    VCC_ESPI

    VCC0

    VCC_IO2
    2N7002KDW 2N SC88-6
    SB00000EO00 1.8V
    EC_TS_EN#
    eSPI & MISC VCCST_PWRGD
    1 21
    1ESPI_ALERT# 2 GA20/GPIO00 PWM0/GPIO0F 23 VCCST_PWRGD [11]
    T135 TP@ GPU_ALERT# ESPI_ALERT#/GPIO01 PWM1/GPIO10 BEEP# [56]
    3 PWM Output 26
    [30] GPU_ALERT# GPIO02 FANPWM0/GPIO12 EC_FAN_PWM1 [77]
    4 27
    [9] ESPI_CS# 5 ESPI_CS# FANPWM1/GPIO13 MUTE_LED# [63]
    [9] ESPI_IO3_R 7 ESPI_IO3
    [9] ESPI_IO2_R 8 ESPI_IO2 63 VCIN1_BATT_TEMP
    [9] ESPI_IO1_R 10 ESPI_IO1 AD0/GPIO38 64 VCIN1_BATT_TEMP [83]
    [9] ESPI_IO0_R ESPI_IO0 AD1/GPIO39 EN_5VALW [87]
    65
    ESPI_CLK_R 12 AD2/GPIO3A 66 ADP_I [85]
    AD Input
    2
    C240
    @EMI@
    1 2
    @EMI@

    R3972
    1 ESPI_CLK_R EMI [9] ESPI_CLK_R
    EC_RST#
    13
    37
    20
    ESPICLK
    GPIO05
    ECRST#
    AD3/GPIO3B
    AD4/GPIO42
    AD5/GPIO43
    75
    76
    PCI_RST# CUST_TEMP1 [66]
    PCI_RST# [11,27,52,68,71]
    AC_IN_TYPE [85]
    [66] EC_FP_RST GPIO0E
    22P_0201_50V8J 33_0201_5% 38
    [71] USB_CHG_CTL3 14 GPIO1D
    [9] ESPI_RST# ESPI_RST#/GPIO07
    Close EC
    68
    1 @ 2 SYS_PWROK DA0/GPIO3C 70 OPMODE VCCST_PWRGD C253 1 2 100P_0402_50V8J
    DA Output DA1/GPIO3D PM_SLP_S3#
    R3874 10K_0402_5% KSI0 55 71
    KSI0/GPIO30 DA2/GPIO3E USB_EN# PM_SLP_S3# [11,16,66]
    KSI1 56 72 @ESD@
    57 KSI1/GPIO31 DA3/GPIO3F USB_EN# [71] PCI_RST# 1 2
    KSI2 C250 100P_0402_50V8J
    KSI3 58 KSI2/GPIO32 83 I2C_2_SCL
    59 KSI3/GPIO33 SCL2/GPIO4A 84 FP_EN# I2C_2_SCL [66]
    Reserved R3874,R3917 as Schematic checklist requirement, KSI4 ESD@
    60 KSI4/GPIO34 SDA2/GPIO4B 85 FP_EN# [66]
    R3917 resistor value is follow RVP. KSI5
    KSI5/GPIO35 SCL3/GPIO4C EC_SMB_CK3 [42] +3VS
    (This two resistor wait for verification) KSI6 61 86
    C KSO[0..15] 62 KSI6/GPIO36 SDA3/GPIO4D 87 EC_SMB_DA3 [42] C
    KSI7
    [63] KSO[0..15] 39 KSI7/GPIO37 PSCLK3/GPIO4E 88 EC_CLEAR_CMOS# [11] I2C_2_SCL 1 2 2.7K_0402_5%
    KSO0 PS2 Interface R361 @
    KSI[0..7] 40 KSO0/GPIO20 PSDAT3/GPIO4F TP_INT# [12,63]
    KSO1
    [63] KSI[0..7] KSO2 41 KSO1/GPIO21
    KSO2/GPIO22 +3VL
    KSO3 42 97
    43 KSO3/GPIO23 SHICS#/GPIO60 98 SYS_PWROK ENBKL [6]
    KSO4
    1 2 0.1U_0201_10V6K EC_RST# 44 KSO4/GPIO24 SHICLK/GPIO61 99 GPU_PROHOT# SYS_PWROK [11]
    C239 KSO5 Int. K/B GPIO EC_SMB_CK3
    KSO5/GPIO25 SHIDO/GPIO62 GPU_PROHOT# [30] R4002 1 2 2.2K_0402_5%
    KSO6 45 109
    KSO7 46 KSO6/GPIO26 Matrix VCIN0/GPIO78 VCIN0_PH1 [83] EC_SMB_DA3 R4003 1 2 2.2K_0402_5%
    KSO8 47 KSO7/GPIO27
    KSO9 48 KSO8/GPIO28 119 +3VALW
    49 KSO9/GPIO29 MISO_SHR_ROM/GPIO5B 120 TS_I2C_RST# [12,38]
    KSO10
    50 KSO10/GPIO2A MOSI_SHR_ROM/GPIO5C 126 DGPU_PWR_EN TS_DISABLE# [12,38] EC_PCIE_WAKE# 1 2 4.7K_0402_5%
    KSO11 SPI ROM R3980 @
    1 2 4.7K_0402_5% 51 KSO11/GPIO2B SPICLK_SHR_ROM/GPIO58 128 DGPU_PWR_EN [12,37]
    R3973 @ OPMODE KSO12
    KSO12/GPIO2C SPICS#_SHR_ROM/GPIO5A PWR_LED_AMBER# [71] EC_MUTE#
    KSO13 52 R3961 1 @ 2 10K_0402_5%
    KSO14 53 KSO13/GPIO2D
    KSO15 54 KSO14/GPIO2E 73 LID_SW# R3969 1 @ 2 100K_0402_5%
    81 KSO15/GPIO2F AD6/GPIO40 74 PTM_EN# [85]
    [66] FP_GPIO_AL0 82 KSO16/GPIO48 AD7/GPIO41 89 EC_MUTE# VCC_AUX_PWRGD [95]
    SELF_HEALING KSO17/GPIO49 LOCK#/GPIO50 EC_MUTE# [56]
    OPMODE (Internal Pull High) : 1 @ 2 90
    [12,56] HDA_SPKR GPIO52 91 BATT_CHG_LED# [63]
    R4000 0_0402_5%
    EC_SMB_CK1 77 CAPSLED#/GPIO53 92 CAPS_LED# [63] VCIN1_AC_IN 1 2
    GPIO C243 100P_0402_50V8J
    Pull Up : Intel eSPI Master Attached Flash Sharing Topology [42,83,85] EC_SMB_CK1 EC_SMB_DA1 78 SCL0/GPIO44 WDT_LED/GPIO54 93 PWR_LED# [63,71]
    [42,83,85] EC_SMB_DA1 SDA0/GPIO45 SCROLED#/GPIO55 BATT_LOW_LED# [63]
    --> For KB9042 / KB9052 [30,66] EC_SMB_CK2
    79 95
    SYSON [89]
    R3964 1 @ 2 4.7K_0402_5%
    80 SCL1_BT/GPIO46 GPIO56 121
    [30,66] EC_SMB_DA2 15 SDA1_BT/GPIO47 GPIO57 127 VR_ON [11,97]
    Pull Down : Intel Legacy Wire-OR share ROM. [11,87,90] 3V/5VALW_PG SCL4/GPIO08 SMBUS GPIO59 ME_EN [10]
    19
    --> For KB9022/9042 Use [11,30] AC_PRESENT 17 SDA4/GPIO0D SUSP# R3965 1 @ 2 100K_0402_5%
    [71] USB_CHG_EN 18 SCL5/GPIO0B 100
    [11] PCH_DPWROK SDA5/GPIO0C FANFB2/GPIO63 EC_RSMRST# [11]
    101 USB_CHG_CTL1 [71]
    FANFB3/GPIO64 102 FN_LED#
    +3VL VCIN1/GPIO65 103 VCOUT1_PROCHOT# FN_LED# [63]
    GPIO VCOUT1/GPIO66 104
    1 2 2.2K_0402_5% EC_SMB_CK1 6 VCOUT0/GPIO67 105 VCOUT0_MAIN_PWR_ON [87]
    R3970 +5VALW
    EC_SMB_DA1 [82] AC_OFF GPIO04 GPIO68 EC_PCIE_WAKE# BKOFF# [12,38]
    R3971 1 2 2.2K_0402_5% 16 106
    B
    [63] TP_DISABLE# KB_BL_PWM 25 OWM/GPIO0A GPIO69 107 B
    [63] KB_BL_PWM EC_FAN_SPEED1 PWM2/GPIO11 GPIO6A CNVi_PWR_EN# [52] USB_EN#
    28 108 R3967 1 2 10K_0402_5%
    1 2 10K_0402_5% EC_PD_INT [77] EC_FAN_SPEED1 29 FANFB0/GPIO14 GWG/GPIO6B USB_CHG_STATUS# [71]
    R369
    [42] EC_PD_INT 30 FANFB1/GPIO15
    [52] EC_TX TXD/GPIO16 GPIO VCIN1_AC_IN
    31 110
    [52] EC_RX PCH_PWROK 32 RXD/GPIO17 AC_IN/GPIO79 112 VCIN1_AC_IN [85]
    [11] PCH_PWROK POWER_FAIL1/GPIO18 GPXIOD02/GPIO7A EC_ON [87]
    34 114 ON/OFF# ON/OFF# [71,77]
    +3VS [63] MIC_LED# 36 PWM3/GPIO19 GPIO7B 115 LID_SW#
    [97] VR_PWRGD NUMLED#/GPIO1A GPIO GPXIOD04/GPIO7C LID_SW# [71]
    116 SUSP#
    GPIO7D SUSP# [16,78,111] +3VL
    R3998 1 2 2.2K_0402_5% EC_SMB_CK2 118 PECI R3966 1 2 43_0402_1%
    1 2 2.2K_0402_5% EC_SMB_DA2 122 PECI/GPIO7F H_PECI [7]
    R3999
    [11] PBTN_OUT# 123 XCLKI/GPIO5D LID_SW# 1 2 100K_0402_5%
    [11,89] PM_SLP_S4# R4001
    GPIO5E NOVO# R3977 1 2 100K_0402_5%
    125 NOVO# ON/OFF# R3976 1 2 100K_0402_5%
    GPIO7E NOVO# [77]

    AGND
    GND
    GND
    GND
    GND
    GND

    KB9052Q-C_LQFP128_14X14
    94
    113

    69
    11
    24
    35

    +3VS SA0000BCG30 SYSON C251 1 2 0.1U_0201_10V6K


    20mil
    ECAGND

    @ESD@
    R3974 1 2 10K_0402_5% EC_FAN_SPEED1 1 2 VCIN1_BATT_TEMP

    R3975 2 @ 1 10K_0402_5% KB_BL_PWM ESD C244


    1
    100P_0201_50V8J
    2
    L16 BLM15AX601SN1D _2P
    [85] VCOUT1_PROCHOT#
    VCOUT1_PROCHOT# R3963 1 @ 2 0_0402_5%

    PCH_PWROK SM01000KL00
    R3962 1 @ 2 0_0402_5% H_PROCHOT# [7]
    [97] VR_HOT#
    +3VS ECAGND
    2 1
    C241
    DIS@ 100P_0201_50V8J C242
    R39 1 2 10K_0402_5% GPU_PROHOT# ESD@ 100P_0402_50V8J
    1
    ESD 2 ESD@

    A A
    C252 1 2 100P_0201_50V8J VR_PWRGD

    @ESD@

    Security Classification
    2019/11/27
    Compal Secret Data
    2020/11/27 Title
    Compal Electronics, Inc.
    Issued Date Deciphered Date
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    EC_ENE KB9052QD
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K321P
    Date: Thursday, June 03, 2021 Sheet 58 of 121
    5 4 3 2 1
    1 2 3 4 5 6 7 8

    Touch Pad Keyboard

    A A
    +5VS

    2
    RTP4
    +3VS +3VS 0_0402_5%
    RTP1 @
    1 @ 2

    1
    JKB2
    0_0402_5% +5VS_KB 1
    CTP1 R265 2 1 866_0402_1% CAPS_LED#_R 2 1
    [58] CAPS_LED# 2

    1
    0.1U_0201_10V6K KSO15 3
    RTP2 @ KSO10 4 3
    KSO11 5 4
    4.7K_0402_5% 5
    1 KSO14 6
    C229 KSO13 7 6

    2
    JTP1 0.1U_0201_10V6K KSO12 8 7
    +TP_VCC 8 ESD@ KSO3 9 8
    7 8 10 2 KSO6 10 9
    [12] I2C_0_SCL 6 7 G2 9 KSI[0..7] 11 10
    KSO8
    [12] I2C_0_SDA 5 6 G1 KSI[0..7] [58] 12 11
    KSO7
    4 5 KSO[0..15] KSO4 13 12
    4 KSO[0..15] [58] 13
    3 KSO2 14
    2 3 KSI0 15 14
    [12,58]
    [58]
    TP_INT#
    TP_DISABLE# RTP3 1 @ 2 0_0402_5% TP_DISABLE#_R 1 2
    1
    ACES_51522-00801-001
    ESD KSO1
    KSO5
    KSI3
    16
    17
    18
    15
    16
    17
    18
    100P_0402_50V8J

    100P_0402_50V8J
    1 1 SP01001AE00 KSI2 19
    19
    CTP2

    CTP3
    ME@ KSO0 20
    20

    2
    KSI5 21
    KSI4 22 21
    2 2 DTP1 @ESD@ KSO9 23 22
    CEST23LC5VB C/A SOT-23 KSI6 24 23
    B
    SCA00004300 KSI7 25 24 B
    KSI1 26 25

    1
    27 26
    28 27
    29 28
    30 29

    ESD [58] FN_LED#


    R266
    R371
    1
    1 @
    2
    2
    866_0402_1%
    866_0402_1%
    +5VS_KB
    FN_LED#_R
    MUTE_LED#_R
    31
    32
    33
    30
    31
    32
    [58] MUTE_LED# MIC_LED#_R 33
    R372 1 2 866_0402_1% 34
    [58] MIC_LED# 34
    35
    GND 36
    GND
    ACES_51612-0340M-P01
    SP011907021
    ME@

    C
    Keyboard Backlight BATT LED C

    +5VALW +5VS +5VS_KBL


    Keyboard BackLight_SELECT LED2

    RS3 1 2 866_0402_1% BATT_CHG_LED#_R2 1 2


    [58] BATT_CHG_LED# +5VL
    Function KBL_ID
    1

    KBL LTW-C193TS5-C_WHITE
    0 SC50000BB10
    3
    S

    RKBL1 1
    10K_0402_5%
    NO KBL 1 LED3
    10U_0402_6.3V6M

    0.1U_0201_10V6K

    KBL@ QKBL1 KBL@


    2

    BATT_LOW_LED#_R2 1
    CKBL1 @

    CKBL2 KBL@

    ME2301DC-G_SOT23-3 RS4 1 2 523_0402_1% 2


    G

    1 2 [58] BATT_LOW_LED#
    2

    RKBL2 SB000013I00 A
    1 2
    [58] KB_BL_PWM
    30K_0402_1% LTST-C191KFKT-2CA_ORANGE
    KBL@ 2 1 SC500005930
    1
    CKBL3
    0.01U_0402_16V7K
    KBL@
    2

    +3VALW
    Status LED
    2

    RKBL3
    100K_0402_5%

    3
    LED4
    JKBL1 RKBL4
    1

    6 KBL_ID_R 1 2 RS5 1 2 866_0402_1% PWR_LED#_R 1 2


    GND KBL_ID [11] [58,71] PWR_LED# +5VL
    D 5 D
    GND 330_0402_5%
    2

    +5VS_KBL 4 LTW-S110DC2-C WHITE


    3 4 RKBL5
    KBL_ID_R 2 3 0_0201_5%
    1 2 PWR_LED#_R [77]
    @
    1
    1

    JXT FP202DH-004G10M
    SP01001YQ00
    ME@
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2019/11/27 Deciphered Date 2020/11/27 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    KB / TP / LED
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 2.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K321P
    Date: Thursday, June 03, 2021 Sheet 63 of 121
    1 2 3 4 5 6 7 8
    5 4 3 2 1

    Finger Printer +3VL +3V_FP FP_RST From PCH Thermal Sensor


    FP_GPIO_AL0 to EC
    +3VS +3VS
    RFP2 1 2 0_0402_5%

    QFP1

    1
    ME2301DC-G_SOT23-3
    +3V_FP
    Close to SSD (JSSD1) RTS7
    UTS1 10K_0402_5%

    D
    3 1
    FP_GPIO_AL0 @
    RFP3 1 @ 2 10K_0201_5%
    D @ FP_DELINK D
    RFP4 1 @ 2 10K_0201_5%

    2
    1 10 EC_SMB_CK2
    VCC SCL EC_SMB_CK2 [30,58]

    G
    2
    RFP11 1 @ 2 4.7K_0201_5% FP_RST RFP5 1 2 100K_0201_5%
    [58] FP_EN# REMOTE1+ 2 9 EC_SMB_DA2
    1 DP1 SDA EC_SMB_DA2 [30,58]
    1
    CTS5 REMOTE- 3 8
    CFP2 DN ALERT#
    0.1U_0201_10V6K
    @ 0.1U_0201_10V K X5R
    2 REMOTE2+ 4 7
    2 DP2 THERM#
    REMOTE3+ 5 6 REMOTE3-
    DN3 GND/DN3

    F75305M_MSOP10
    Address 1001_101xb

    [58] I2C_2_SCL
    RFP10 1 @ 2 0_0201_5% 1 TFP2 TP@
    PAD~D JFP1
    Close to UTS1 Close to BATT Charger (JBATT1)
    RFP9 1 @ 2 0_0201_5% FP_GPIO_SCL 8
    [58] EC_FP_RST FP_RST_R 8 REMOTE1+
    RFP7 1 2 0_0201_5% 7 10
    [12] FP_RST 7 G2
    6 9 REMOTE1+

    1
    [58] FP_GPIO_AL0 6 G1 C
    RFP8 1 @ 2 0_0201_5% FP_DELINK 5 1
    [11,16,58] PM_SLP_S3# 5 CTS1 2 QTS1
    +3V_FP 4 B
    4 2200P_0402_25V7K MMST3904-7-F_SOT323-3
    3 CTS3

    2
    [13] USB20_P7 3 @ E
    2 2200P_0402_25V7K

    3
    [13] USB20_N7 +3V_FP 2 2 REMOTE-
    1 REMOTE-
    1

    C
    ACES_51522-00801-001 C
    SP01001AE00
    ME@
    Close to +5VALW (PL501)
    CFP1
    REMOTE2+ REMOTE2+
    0.1U_0201_10V K X5R
    1

    1
    C
    CTS4 CTS2 2 QTS2
    2200P_0402_25V7K 2200P_0402_25V7K B MMST3904-7-F_SOT323-3
    3

    2
    2 REMOTE- @ E

    3
    REMOTE-
    DFP1 ESD@
    CEST23LC5VB C/A SOT-23
    SCA00004300
    Close to CPU Chip (UC1)
    1

    REMOTE3+
    1 REMOTE3+

    1
    CTS6 C
    2200P_0402_25V7K CTS7 2 QTS3
    2 REMOTE3- 2200P_0402_25V7K B MMST3904-7-F_SOT323-3

    2
    @ E

    3
    REMOTE3-

    REMOTE1,2,3 (+/-) :
    B
    Trace width/space:10/10 mil B

    Under thermal pipe Trace length:<8"


    +EC_VCCA
    +3VS
    1

    RTS1 1
    @ 16.5K_0402_1% CTH1
    Close to VRAM IC (UV22) Close to UTH1 0.1U_0201_10V6K
    DIS@
    2

    2
    +3VS
    [58] CUST_TEMP1 1

    1
    QTH1 C
    Close to GPU (UV1)

    1
    LMBT3904W T1G_SC70-3 2 CTH2 CTH3
    1

    DIS@ B 2200P_0402_25V7K 2200P_0402_25V7K UTH1 DIS@


    RTH2

    2
    RTS4 E @ DIS@ 2 REMOTE4+ 2 1 @

    3
    @ 100K +-1% 0402 B25/50 4250K D+ VCC 10K_0402_5%
    REMOTE4- 3 6

    2
    D- ALERT#
    2

    EC_SMB_CK2 8 4
    SCL THERM#
    EC_SMB_DA2 7 5
    ECAGND SDA GND

    F75397M_MSOP8
    A
    REMOTE4(+/-) : SA00007W P00 A
    Trace width/space:10/10 mil
    Trace length:<8" Address 1001_100xb

    Security Classification
    2019/11/27
    Compal Secret Data
    2020/11/27 Title
    Compal Electronics, Inc.
    Issued Date Deciphered Date
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Finger Printer/ Thermal
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 2.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K321P
    Date: Thursday, June 03, 2021 Sheet 66 of 121
    5 4 3 2 1
    5 4 3 2 1

    SSD (TYPE M) +3VS_SSD

    D D
    +3VS_SSD

    0.01U_0402_16V7K

    0.1U_0201_10V6K

    10U_0402_6.3V6M

    10U_0402_6.3V6M
    1 1 1 1

    C18

    C19

    C20

    C21 @
    2 2 2 2

    2
    can remove it, ialready have RC534
    R12
    +3VS +3VS_SSD 10K_0402_5%

    1
    R10 1 @ 2 0_0805_5% NGFF_SSD_PEDET
    NGFF_SSD_PEDET [13]

    JSSD1
    1 2 For RF team cross mote
    3 GND 3P3VAUX 4
    5 GND 3P3VAUX 6
    [13] PCIE_CRX_DTX_N9 PERn3 NC
    7 8
    [13] PCIE_CRX_DTX_P9 PERp3 NC
    9 10
    C155 1 2 0.22U_0201_6.3V6M PCIE_CTX_C_DRX_N9 11 GND DAS/DSS# 12 +3VS
    [13] PCIE_CTX_DRX_N9 PCIE_CTX_C_DRX_P9 PETn3 3P3VAUX
    C156 1 2 0.22U_0201_6.3V6M 13 14 +VCCIN
    [13] PCIE_CTX_DRX_P9 PETp3 3P3VAUX
    15 16
    17 GND 3P3VAUX 18 CC399 1 2 0.1U_0201_10V6K
    [13] PCIE_CRX_DTX_N10 PERn2 3P3VAUX
    19 20
    [13] PCIE_CRX_DTX_P10 PERp2 NC
    21 22 RF@ +5VALW
    C157 1 2 0.22U_0201_6.3V6M PCIE_CTX_C_DRX_N10 23 GND NC 24
    [13] PCIE_CTX_DRX_N10 PCIE_CTX_C_DRX_P10 PETn2 NC
    C C158 1 2 0.22U_0201_6.3V6M 25 26 CC400 1 2 0.1U_0201_10V6K C
    [13] PCIE_CTX_DRX_P10 PETp2 NC
    27 28
    29 GND NC 30 RF@
    [13] PCIE_CRX_DTX_N11 PERn1 NC
    SSD PCIE [13] PCIE_CRX_DTX_P11 31
    PERp1 NC
    32
    33 34
    C159 1 2 0.22U_0201_6.3V6M PCIE_CTX_C_DRX_N11 35 GND NC 36
    [13] PCIE_CTX_DRX_N11 PETn1 NC
    C160 1 2 0.22U_0201_6.3V6M PCIE_CTX_C_DRX_P11 37 38
    [13] PCIE_CTX_DRX_P11 PETp1 DEVSLP DEVSLP2 [13]
    39 40
    41 GND NC 42
    [13] PCIE_CRX_DTX_P12 PERn0/SATA-B+ NC
    43 44
    [13] PCIE_CRX_DTX_N12 PERp0/SATA-B- NC
    45 46
    C161 1 2 0.22U_0201_6.3V6M PCIE_CTX_C_DRX_N12 47 GND NC 48
    [13] PCIE_CTX_DRX_N12 PETn0/SATA-A- NC
    [13] PCIE_CTX_DRX_P12 C162 1 2 0.22U_0201_6.3V6M PCIE_CTX_C_DRX_P12 49 50
    PETp0/SATA-A+ PERST# PCI_RST# [11,27,52,58,71]
    51 52
    GND CLKREQ# CLKREQ_PCIE#5 [11]
    53 54
    [11] CLK_PCIE_N5 REFCLKN PEWake#
    55 56
    [11] CLK_PCIE_P5 REFCLKP NC
    57 58
    GND NC

    59 60
    NGFF_SSD_PEDET 61 NC SUSCLK(32kHz) 62
    63 PEDET(NC-PCIE/GND-SATA) 3P3VAUX 64
    65 GND 3P3VAUX 66
    67 GND 3P3VAUX
    GND 68
    GND1 69
    GND2
    B BELLW _80159-3221 B
    SP070018L00
    ME@

    www.teknisi-indonesia.com

    A A

    Security Classification
    2019/11/27
    Compal Secret Data
    2020/11/27 Title
    Compal Electronics, Inc.
    Issued Date Deciphered Date
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    NGFF SSD
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 2.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K321P
    Date: Thursday, June 03, 2021 Sheet 68 of 121
    5 4 3 2 1
    1 2 3 4 5 6 7 8

    USB3.0_Port (AOU_Port)
    +5VALW_CHG +5VALW

    +3VL
    +5VALW_USB1
    R335 1 @ 2 0_0805_5%

    1
    10K_0402_5%
    80mil 80mil

    1
    R110

    10K_0402_5%
    A A

    R108
    U7

    2
    1 12

    2
    9 IN OUT 10 CHR_USB20_P1
    [58] USB_CHG_STATUS# USB_OC0#_R STATUS# DP_IN CHR_USB20_N1
    R112 2 @ 1 0_0402_5% 13 11
    [13] USB_OC0# USB_CHG_ILIM_SEL 4 FAULT# DM_IN 2 USB20_N1
    5 ILIM_SEL DM_OUT 3 USB20_P1 USB20_N1 [13]
    [58] USB_CHG_EN EN DP_OUT USB20_P1 [13]
    6 15 R113 1 2 2.7M_0402_1%
    [58] USB_CHG_CTL1 USB_CHG_CTL2 CTL1 ILIM_LO
    +3VL
    1 2 7 16 R114 1 2 24.9K_0402_1%
    R3997 10K_0402_5% 8 CTL2 ILIM_HI 14
    [58] USB_CHG_CTL3 CTL3 GND 17
    T-PAD
    SN1702001RTER_QFN16_3X3
    SA0000B0V00
    1
    10K_0402_5%

    22U_0603_6.3V6K

    10U_0402_6.3V6M
    1 1
    R117

    C49

    C50
    @
    2 2
    2

    EMI
    CHR_USB20_P1 R119 1 @EMI@ 2 0_0402_5% CHR_USB20_P1_R
    B B

    CHR_USB20_N1 R120 1 @EMI@ 2 0_0402_5% CHR_USB20_N1_R

    USB3.0_Port (Non-AOU_Port) I/O CONN [58] LID_SW#


    1
    JIO1

    CHR_USB20_N1_R 2 1 41
    CHR_USB20_P1_R 3 2 G1 42
    4 3 G2
    5 4
    [13] USB3_CTX_DRX_N1 5
    [13] USB3_CTX_DRX_P1
    6
    7 6
    8 7
    [13] USB3_CRX_DTX_N1 9 8
    [13] USB3_CRX_DTX_P1 9
    10
    11 10
    [58,77] ON/OFF# 11
    +5VALW_USB1
    12
    13 12
    14 13
    15 14
    C 16 15 C
    [58] PWR_LED_AMBER# 16
    +5VALW_USB2
    17
    18 17
    19 18
    20 19
    +5VL 20
    [58,63] PWR_LED#
    21
    22 21
    40mil 40mil +3VALW
    +3VS
    23 22
    24 23
    +5VALW +5VALW_USB2 25 24
    [11,27,52,58,68] PCI_RST# 2 0.1U_0201_10V6K PCIE_CTX_C_DRX_P4 25
    C232 1 26
    [13] PCIE_CTX_DRX_P4 2 0.1U_0201_10V6K PCIE_CTX_C_DRX_N4 26
    U9 C233 1 27
    1 [13] PCIE_CTX_DRX_N4 28 27
    5 OUT 29 28
    IN
    GND
    2 Card Reader [13] PCIE_CRX_DTX_P4
    [13] PCIE_CRX_DTX_N4
    30 29
    30
    [58] USB_EN# 4 31
    EN 3 [11] CLK_PCIE_P4 32 31
    R334 2 @ 1 0_0402_5%
    OCB USB_OC1# [6] [11] CLK_PCIE_N4 33 32
    [11] CLKREQ_PCIE#4 33
    G524B2T11U_SOT23-5 34
    [13] USB3_CTX_DRX_P2 34
    1 SA00007BW00 [13] USB3_CTX_DRX_N2
    35
    C66 36 35
    +3VL 36
    0.1U_0201_10V6K 37
    [13] USB3_CRX_DTX_P2 38 37
    2 [13] USB3_CRX_DTX_N2 USB20_N2 39 38
    2A/Active Low [13] USB20_N2 USB20_P2 39
    40
    [13] USB20_P2 40
    TWVM FPC0518-40RC-TAGHT 40P P.5
    SP01002UH00
    ME@

    D D

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2019/11/27 Deciphered Date 2020/11/27 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    USB3 / IO board Conn.
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 2.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K321P
    Date: Thursday, June 03, 2021 Sheet 71 of 121
    1 2 3 4 5 6 7 8
    A B C D E

    NOVO Button
    SCREW
    LASER BARCODE
    SW 1
    TBF313KQR_5P
    CPU GPU WLAN SSD
    1 3 1 CODE1 @ SN CODE2 @ Version 1
    [58] NOVO#
    4 2 H1 H2 H3 H4 H6 H5 H7
    HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
    FD1 FD2

    5
    [63] PW R_LED#_R

    1
    BARCODE_6X6 BARCODE_12X4

    1
    MAC
    3

    2
    H_3P3 H_3P3 H_3P3 H_3P3 H_3P3 H_3P2 H_3P2 CODE3 @ CODE4 @
    D33
    FD3 FD4
    ESD@
    SCA00004300
    CEST23LC5VB C/A SOT-23
    H11 H12 H10 H15 H13 H16 H14 H8 H17

    1
    HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
    1

    BARCODE_20X4 BARCODE_8X8
    ESD

    1
    H_3P3 H_3P5 H_2P3 H_2P3 H_2P3 H_2P8 H_3P1X2P1N H_3P1X2P1N H_2P1N

    ON/OFF# SHORT PAD


    2 2
    @

    +12V FAN TOP side


    JP1 2

    SHORT PADS
    1 ON/OFF#
    ON/OFF# [58,71]

    +12V
    @
    JFAN1 JP2 2 1 ON/OFF#
    RF1 2 @ 1 0_0603_5% +12V_FAN 1
    EC_FAN_SPEED1 2 1 SHORT PADS
    [58]
    [58]
    EC_FAN_SPEED1
    EC_FAN_PW M1
    EC_FAN_PW M1 3
    4
    2
    3 BOT side
    4
    1
    5
    CF5 6 GND1
    10U_0603_25V6M GND2
    2 DIS@ ACES_50271-0040N-001
    SP02000TS00
    ME@
    RF moat Caps
    +1.2V +VCCIN +1.2VS_VRAM
    +5VALW +5VS +1.8VALW +1.0VS_DGPU

    3 +5V FAN C758 1 2 0.1U_0201_10V6K C767 1 2 0.1U_0201_10V6K


    1
    C761
    1
    C762
    1
    C763
    3

    0.1U_0201_10V6K 0.1U_0201_10V6K 0.1U_0201_10V6K


    RF@ RF@
    2 RF@ 2 RF@ 2 @RF@
    +3VS +1.8VALW
    +3VALW +3VS
    +5VS
    JFAN2
    +5VS_FAN C759 1 2 0.1U_0201_10V6K C768 1 2 0.1U_0201_10V6K
    RF2 2 @ 1 0_0603_5% 1
    EC_FAN_SPEED1 2 1
    EC_FAN_PW M1 2 RF@ RF@ +1.2VS_VRAM +1.2VS_VRAM +1.8VALW
    2 3
    4 3 +VCCIN_AUX
    4 +3VALW
    CF6
    10U_0402_6.3V6M 5 1 1 1
    1 UMA@ 6 GND1
    GND2 C760 1 2 0.1U_0201_10V6K C764 C765 C769
    0.1U_0201_10V6K 0.1U_0201_10V6K 0.1U_0201_10V6K
    HEFENG AW B03-S04C1A-HF
    RF@ 2 @RF@ 2 @RF@ 2 @RF@
    SP02001NN00 +1.8VALW +3VS
    ME@

    C766 1 2 0.1U_0201_10V6K

    RF@

    RF
    +5VS EC_FAN_SPEED1 EC_FAN_PW M1

    4 4
    1 1 1
    CF2 CF3 CF4
    6.8P_0402_50V8B 6.8P_0402_50V8B 6.8P_0402_50V8B
    2 @RF@ 2 @RF@ 2 @RF@
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2019/11/27 Deciphered Date 2020/11/27 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    NOVO / SCREW / FAN
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 2.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K321P
    Date: Thursday, June 03, 2021 Sheet 77 of 121
    A B C D E
    A B C D E

    DC to DC
    1 1

    +3VALW +3VS
    J1 JUMP@
    2 1
    +5VL 2 1

    0.1U_0201_10V6K

    10U_0402_6.3V6M
    JUMP_43X79

    10U_0402_6.3V6M

    0.1U_0201_10V6K
    1 1 1 1
    +3VALW to +3VS

    C71

    C72

    C73

    C74
    @ @ @
    2 2 2 2
    U10
    1 14 +3VALW _3VS
    2 VIN1 VOUT1 13
    VIN1 VOUT1
    3 12 C75 1 2 1000P_0402_50V7K
    ON1 CT1
    4 11
    [16,58,111] SUSP# VBIAS GND +5VS
    5 10 C76 1 2 2200P_0402_25V7K
    +5VALW ON2 CT2 J2 JUMP@
    6 9 +5VALW _5VS 2 1
    7 VIN2 VOUT2 8 2 1
    VIN2 VOUT2

    10U_0402_6.3V6M

    0.1U_0201_10V6K
    JUMP_43X79 1 1
    0.1U_0201_10V6K

    10U_0402_6.3V6M

    C79

    C80
    1 1 15
    GPAD
    C77

    C78
    2 G2898KD1U_TDFN14_2X3 @ 2
    @ SA0000BEL00 2@ 2
    2 2

    +5VALW to +5VS

    +1.8VALW
    +1.8VALW TO +1.8VS
    1
    C389
    1U_0201_6.3V6M U13 +1.8VS
    1
    2 2 VIN1
    +5VALW VIN2
    C391 @ 7 6
    0.1U_0201_16V6K VIN thermal VOUT
    3 2 1 3 3
    VBIAS 1
    C392
    SUSP# 4 5 0.1U_0201_10V6K
    ON GND
    2
    1
    @ C394 EM5201V_DFN8_3X3
    1U_0201_6.3V6M
    2
    RDS(Typ) : 3.5 mohm
    V drop : 0.0004V

    4 4

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2019/11/27 Deciphered Date 2020/11/27 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    DC to DC
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 2.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K321P
    Date: Thursday, June 03, 2021 Sheet 78 of 121
    A B C D E
    5 4 3 2 1

    D D

    C C

    B B

    A A

    Security Classification
    2019/11/27
    Compal Secret Data
    2020/11/27 Title
    Compal Electronics, Inc.
    Issued Date Deciphered Date
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Reserve
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 2.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K321P
    Date: Thursday, June 03, 2021 Sheet 79 of 121
    5 4 3 2 1
    5 4 3 2 1

    D D

    C C

    B B

    A A

    Security Classification
    2019/11/27
    Compal Secret Data
    2020/11/27 Title
    Compal Electronics, Inc.
    Issued Date Deciphered Date
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Reserve
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 2.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K321P
    Date: Thursday, June 03, 2021 Sheet 80 of 121
    5 4 3 2 1
    5 4 3 2 1

    D D

    C C

    B B

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2019/05/23 Deciphered Date 2021/05/31 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    PWR- Reserve
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LAK321P
    Date: Friday, May 07, 2021 Sheet 81 of 121
    5 4 3 2 1
    5 4 3 2 1

    +TCP0_VBUS +20V_TBT_VBUS_L VIN_MUX


    TYPEC_VIN

    PFS1 PQS1 PQS12


    7A_24V_F1206HI7000V024TM AON7506_DFN3X3-8-5 AON7380_DFN3X3-8-5
    1 1
    1 2 2 2
    D
    3 5 5 3 D

    2200P_0402_25V7K
    2200P_0402_25V7K

    1
    1

    PCS2
    PCS1

    2
    2
    @
    @

    1
    PRS3

    1
    0_0402_5%
    PRS2
    0_0402_5%

    2
    2
    [42] PA_GATE_VBUS

    [42] PA_GATE_SYS

    C C

    +19V_VIN PQD11 +19V_VIN_P1 PQD12


    ACES_50278-00401-001 AONR21357_P_DFN33-8-5 AONR21357_P_DFN33-8-5
    6 EMI@ PLD11 1 1
    G2 PFD1
    5 5A_Z80_0805_2P 2 2
    G1 4 ADPIN 1 2 +19V_ADPIN 1 2 3 5 5 3
    4

    1
    3

    2200P_0402_25V7K
    3

    1
    2 7A_24V_F1206HI7000V024TM PDD1

    499K_0402_1%
    4700P_0402_50V7K

    1
    1 BZT52-B5V1S_SOD323-2
    1000P_0402_50V7K

    1000P_0402_50V7K
    100P_0402_50V8J

    100P_0402_50V8J

    4
    1

    1
    D

    PCD5

    PRD1
    1

    JDCIN1 2
    EMI@ PCD7

    ideal_1

    2
    1

    1
    1

    CONN@
    @EMI@ PCD1

    EMI@ PCD4
    EMI@ PCD2

    EMI@ PCD3

    2
    S PQD4
    2

    3
    WPM5001-3-TR_SOT23-3
    2

    2
    2

    470K_0402_1%
    1

    PRD9
    PRD2
    49.9K_0402_1% PQD5A PQD5B
    METR3906KW-G_SOT363-6 METR3906KW-G_SOT363-6

    2
    1

    4
    2
    2 5
    +19V_VIN

    3
    B B
    1

    PRD6
    154K_0402_1%

    1
    PRD3 PRD5
    2

    47K_0402_1% PRD4 47K_0402_1%

    6
    PQD3A D 470K_0402_1%
    2

    2
    G
    2N7002KDW_SOT363-6
    S
    1
    3

    PQD3B D
    5 PCD6 PRD7
    [58] AC_OFF G 0.1U_0402_25V6 24K_0402_1%
    2
    1

    2N7002KDW_SOT363-6
    PRD8 S
    4

    100K_0402_5%
    2

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Title
    Issued Date 2019/05/23 Deciphered Date 2021/05/31
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    PWR- DC Conn/Type-C PD in
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LAK321P
    Date: Friday, May 07, 2021 Sheet 82 of 121
    5 4 3 2 1
    5 4 3 2 1

    EMI@ PL3
    M_BATA M_VMB 5A_Z80_0805_2P
    Conn@
    PF2
    1 2 BATT+
    JBATT1
    1 1 2
    1 2 EMI@ PL4
    2 3 EC_SMCA 5A_Z80_0805_2P
    D D
    3 4 EC_SMDA 12A_24V_F1206HB12V024TM 1 2
    4 5 BATT_TEMP
    5 6
    6 7
    7 8

    1
    8 9 PC10 EMI@ PC11 EMI@
    G1 10

    1
    1000P_0402_50V7K 0.01U_0402_25V7K

    2
    G2 11
    PH201 under CPU botten side :

    100_0402_1%

    100_0402_1%
    G3 12
    G4
    CPU thermal protection at 93 +-3 degree C

    PR11

    PR12
    2

    2
    ACES_60757-00802-001 Recovery at 56 +-3 degree C

    EC_SMB_CK1 [42,58,85]

    EC_SMB_DA1 [42,58,85]
    +EC_VCCA
    1 2

    16.5K_0402_1%
    +3VL

    1
    PR14 200K_0402_1%

    PR13
    1 2
    VCIN1_BATT_TEMP [58]
    PR15

    2
    C 10K_0402_5% [58] VCIN0_PH1
    C

    +RTCBATT

    1
    PH1
    100K +-1% 0402 B25/50 4250K

    2
    +RTCBATT ECAGND
    +CHGRTC +3VL

    PD2
    @0@ PR8
    1 2 1 2

    30MA_30V_0.5UA_0.4V_SOD323-2 0_0603_5%
    1

    @ PR9
    45.3K_0603_1%
    B B
    2

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Title
    Issued Date 2019/05/23 Deciphered Date 2021/05/31
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    PWR- BATTERY CONN/OTP/RTC
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LAK321P
    Date: Friday, May 07, 2021 Sheet 83 of 121
    5 4 3 2 1
    5 4 3 2 1

    D D

    C C

    B B

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2019/12/09 Deciphered Date 2021/05/31 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    PWR- Reserve
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LAK321P
    Date: Friday, May 07, 2021 Sheet 84 of 121
    5 4 3 2 1
    A B C D

    +12.6VB

    VIN_MUX VIN_CHG

    10U_0603_25V6M

    10U_0603_25V6M

    10U_0603_25V6M

    10U_0603_25V6M

    10U_0603_25V6M

    10U_0603_25V6M
    1

    1
    PCB27

    PCB26

    PCB14

    PCB13

    PCB17

    PCB10
    PRB1

    2
    1 4

    10U_0603_25V6M 2 3

    10U_0603_25V6M

    10U_0603_25V6M

    2200P_0402_25V7K
    1 1
    10U_0603_25V6M

    HG1_CHG

    HG2_CHG
    0.1U_0402_25V6
    0.01_1206_1%
    1

    1
    PCB3

    PCB4

    PCB5

    PCB6

    1
    @EMI@ PCB1

    EMI@ PCB2
    ACP ACN
    2

    1
    +12.6V_BATT+

    2
    PRB2 PRB3 PQB2
    4.99_0402_1% 4.99_0402_1% AON6994_DFN5X6D-8-7 PQB13 BATT+
    PQB1 AONR21357_P_DFN33-8-5 PRB9

    1
    AON6962_DFN5X6D-8-7 1 0.01_1206_1%

    2
    2

    D1

    G1

    D1

    G1
    PLB1 3 5 1 4
    1 2 2.2UH_MMD-10CZ-2R2M-X2L_13A_20%

    1
    7 LX1_CHG 1 2 LX2_CHG 7 2 3

    10U_0603_25V6M
    PCB7 D2/S1 D2/S1

    4
    1

    PCB35
    0.1U_0402_25V6 PCB34

    0.047U_0402_25V7K

    0.047U_0402_25V7K

    2
    PCB8 PCB9 1U_0402_25V6K

    G2

    G2
    S2

    S2

    S2

    S2

    S2

    S2
    1

    1
    0.033U_0402_25V7K 0.033U_0402_25V7K SRP SRN

    PCB11

    PCB19

    4.7_1206_5%
    2

    2
    1

    @EMI@ PRB15
    4.7_1206_5%
    3

    3
    1
    PCB23

    2
    +19V_VIN

    PRB14

    BST1_CHG_R

    BST2_CHG_R
    1 2

    1SNUB_CHG2 2

    1
    1SNUB_CHG1 2
    0.1U_0402_25V6

    @EMI@
    PCB22 PCB24
    0.1U_0402_25V6 0.1U_0402_25V6

    2
    3

    1
    1
    @0@ @0@
    PDB1 PRB4 PRB11

    680P_0402_50V7K
    680P_0402_50V7K
    BAT54CW_SOT323-3 0_0402_5% 0_0402_5%

    PCB21
    PUB1

    2
    2

    1
    PCB20
    1

    2
    BST1_CHG 30 25 BST2_CHG PRB18 PRB19

    2
    BTST1 BTST2

    @EMI@
    10_0402_1% 10_0402_1%

    @EMI@
    32 23
    SW1 SW2

    2
    LG1_CHG 29 26 LG2_CHG
    LODRV1 LODRV2
    REGN PRB8 HG1_CHG 31 24 HG2_CHG
    2 VDDA 1_0805_5% HIDRV1 HIDRV2 PRB32 0_0402_5% 2

    1 2 1 22 VSYS 1 2
    VBUS VSYS
    ACN_CHG 2 21 BGATE
    ACN BATDRV
    ACP_CHG 3 20 SRP_CHG
    ACP SRP
    2 1 7 19 SRN_CHG
    PRB6 VDDA SRN
    REGN
    1

    1
    10_0402_1% PCB15
    0.47U_0402_25V6K HIZ_CHG 6
    ILIM_HIZ
    1

    PCB16 28
    VDDA
    2

    2
    1U_0402_25V6K PRB25 REGN
    PRB21

    1
    165K_0402_1% COMP1_CHG 16
    COMP1 17 COMP2_CHG 1 2 PCB18
    COMP2 COMP2_CHG_R 2.2U_0402_25V6M
    2

    2
    1
    1

    1
    PROCHOT_CHG 11 10K_0402_1%
    PROCHOT
    3.16A PCB29 PCB28 PRB23
    15P_0402_50V8J 680P_0402_50V7K 82K_0402_1%

    2
    2
    PRB26 18
    40.2K_0402_1% SCL_CHG 13 CELL_BATPRESZ

    2
    2 1 SCL
    SDA_CHG 12 8 BATGONE
    1800P_0402_50V7K

    33P_0402_50V8J

    SDA IADPT
    1

    COMP1_CHG_R For 3S battery


    ADP_I [58]
    1

    4 9 IBAT_CHG
    PCB30

    PCB31

    PRB24
    CHRG_OK IBAT

    1
    100K_0402_1%

    1
    5 10 PRB22
    2

    ENZ_OTG PSYS

    1
    100K_0402_1%
    2

    AC_IN_TYPE 15 27 PRB20 PCB25


    CMPOUT PGND

    1
    137K_0402_1% 100P_0402_50V8J

    2
    CMPIN_25710 14 33 PCB32
    REGN

    2
    CMPIN PAD 100P_0402_50V8J

    2
    PRB131 2 0_0402_5%
    [58] VCOUT1_PROCHOT# BQ25710RSNR_QFN32_4X4
    1

    PRB121 2 0_0402_5%
    PRB16 [42,58,83] EC_SMB_CK1 PSYS_MON [97]
    100K_0402_5% PRB101 2 0_0402_5%
    3
    [42,58,83] EC_SMB_DA1 3
    2

    +19V_VIN
    [58] VCIN1_AC_IN +3VL
    REGN
    1

    PRB17
    HIZ_CHG

    100K_0402_5%
    100K_0402_5%

    1
    100K_0402_5%
    PRB31

    PRB29
    2

    1
    @ PQB3
    PRB5 LSK3541G1ET2L_VMT3

    1
    511K_0402_1%
    VDDA

    2
    1

    @
    PRB34
    @

    2
    100K_0402_5% 2.3V 2
    1

    @
    PRB27 CMPIN_25710 @ PQB4
    2

    100K_0402_5% LSK3541G1ET2L_VMT3

    1
    AC_IN_TYPE
    [58] AC_IN_TYPE

    3
    0.1U_0402_25V6
    2

    1
    2 @
    1

    1
    [58] PTM_EN#

    PCB12
    PRB33 PRB7 PCB33
    PRB28 100K_0402_5% 0.1U_0402_6.3V7K

    2
    100K_0402_5% 75K_0402_1%

    2
    2

    3
    0X30 bit6 = 1
    2

    LOW = below threshold


    HIGH = above threshold @0@ PRB30
    0_0402_5%
    1 2

    4 4

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Title
    Issued Date 2019/05/23 Deciphered Date 2021/05/31
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    PWR- CHARGER
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 2.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LAK321P
    Date: Friday, May 07, 2021 Sheet 85 of 121
    A B C D
    5 4 3 2 1

    D D

    C C

    B B

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2019/12/09 Deciphered Date 2021/05/31 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    PWR- Reserve
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LAK321P
    Date: Friday, May 07, 2021 Sheet 86 of 121
    5 4 3 2 1
    A B C D E

    @0@
    @ PR301 PC301
    +12.6VB PJ301 0_0402_5% 0.1U_0402_25V6
    1 2 +12.6VB_3V BST_3V 1 2 BST_3V_R 1 2
    1 2
    JUMP_43X79

    2200P_0402_50V7K
    1 1

    PC302

    EMI@ PC303

    10U_0603_25V6M

    10U_0603_25V6M
    0.1U_0402_25V6
    1

    1
    keep short pad,

    PC304

    PC305

    BS
    IN3

    IN2

    IN1
    snubber is for EMI only.

    2
    @EMI@
    LX_3V 5 17 PL301
    LX EP 1.5UH_6A_20%_5X5X3_M
    PU301
    SY8386BRHC_QFN16_2P5X2P5 16 LX_3V 1 4
    6 LX2 +3VALWP
    +3VL GND 2 3
    15

    4.7_1206_5%

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M
    LX1

    1
    Check pull up resistor of SPOK at HW side

    RF@
    PR302
    7

    PC306

    PC307

    PC308

    PC309
    PG

    1
    14

    2
    GND1
    PR303

    3V_SN2
    100K_0402_5% 8 13
    EN2 LDO +3VLP

    4.7U_0402_6.3V6M
    2

    TEST

    680P_0402_50V7K
    OUT
    EN1

    1
    PC310
    FF

    1
    PC311
    [11,58,90] 3V/5VALW_PG 4.7U_0402_6.3V6M
    Vout is 3.234V~3.366V

    10

    11

    12

    2
    @

    PC312
    RF@

    2
    Iocp=8A
    TDC=6A
    ENLDO_3V5V
    3.3V LDO 150mA~300mA

    5V_3V_EN @
    PJ302
    Fsw : 600K Hz PC313 PR304 1 2
    EN1 and EN2 dont't be floating. 1000P_0402_50V7K 1K_0402_1% +3VALWP 1 2 +3VALW
    3V_FB 1 2 3V_FB_1 1 2
    EN :H>1V ; L<0.4V JUMP_43X118
    2 2
    @
    PJ303
    JUMP_43X39
    1 2
    2 Cell battery : Cin=10uF*2pcs keep short pad, +3VLP 1 2 +3VL
    3 Cell ~ 4 Cell battery : Cin=10uF*1pcs snubber is for EMI only.

    @ @0@ PR501 PC501


    PJ501 0_0402_5% 0.1U_0402_25V6
    1 2 +12.6VB_5V BST_5V1 2 BST_5V_R 1 2
    +12.6VB 1 2
    JUMP_43X118 PU501

    13
    1
    SY8270CTMC_QFN13_3X4
    PL501

    BS
    IN
    1.5UH_9A_20%_7X7X3_M
    10U_0603_25V6M

    10U_0603_25V6M

    10U_0603_25V6M
    10U_0603_25V6M

    2200P_0402_50V7K

    0.1U_0402_25V6

    LX_5V 2 12 LX_5V LX_5V 1 4


    LX1 LX2 +5VALWP
    1

    1
    1

    1
    1
    PC502

    PC503

    PC505
    PC504

    @EMI@ PC507
    EMI@ PC506

    2 3
    3 11

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M
    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M
    2

    2
    2

    2
    2

    GND1 GND2

    1
    1

    1
    1

    1
    1

    PC513

    PC514
    PR502

    PC512
    PC509

    PC510

    PC511

    PC515

    PC516
    4.7_0805_5%
    4 10 VCC_5V 1 2

    RF@

    2
    2

    2
    PG VCC
    OUT PC508
    LDO
    EN2

    EN1

    3V/5VALW_PG 4.7U_0402_6.3V6M
    FF

    2
    5V LDO 150mA~300mA
    5

    15V_SN
    4.7U_0402_6.3V6M

    +5VLP

    680P_0402_50V7K
    RF@
    Vout is 4.998V~5.202V

    PC517
    1

    3 3

    2
    PC518

    ENLDO_3V5V
    TDC=10A Iocp=12A
    2

    5V_3V_EN 1 2 5V_EN
    @ PR503 0_0402_5%

    PR504
    499K_0402_1%
    PC519 PR505

    www.teknisi-indonesia.com
    1 2 ENLDO_3V5V
    +12.6VB 1000P_0402_25V8J 1K_0402_1%
    5V_FB 1 2 5V_FB_1 1 2
    1

    PR506
    150K_0402_1% PC520
    1U_0201_6.3V6M
    +3VLP EN1 and EN2 dont't be floating.
    2
    2

    EN :H>0.8V ; L<0.4V
    1

    PR507
    100K_0402_5% Fsw : 600K Hz @
    PR508 PJ502
    0_0402_5% 1 2
    +5VALWP 1 2 +5VALW
    2

    1 2 5V_EN
    2.2K_0402_5% [58] EN_5VALW JUMP_43X118
    PR509
    1 2
    1

    [58] EC_ON @
    4.7U_0402_6.3V6M

    0_0402_5% PR511 @ PJ503


    1

    PR510 1 JUMP_43X39
    PC521

    2 100K_0402_5%
    [58] VCOUT0_MAIN_PWR_ON 1 2
    +5VLP 1 2 +5VL
    2

    5V_3V_EN @
    4.7U_0402_6.3V6M
    1

    1M_0402_1%
    PR512

    PC522

    4 4
    2

    EN1 and EN2 dont't be floating.


    2

    EN :H>1V ; L<0.4V
    Fsw : 600K Hz

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2019/05/23 Deciphered Date 2021/05/31 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    PWR- 3/5VALWP
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LAK321P
    Date: Friday, May 07, 2021 Sheet 87 of 121
    A B C D E
    5 4 3 2 1

    D D

    C C

    B B

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2019/12/09 Deciphered Date 2021/05/31 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    PWR- Reserve
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LAK321P
    Date: Friday, May 07, 2021 Sheet 88 of 121
    5 4 3 2 1
    5 4 3 2 1

    Pin19 need pull separate from +1.35VP.


    +12.6VB @ If you have +1.35V and +0.675V sequence question, 0.675Volt +/- 5%
    you can change from +1.35VP to +1.35VS. TDC 0.7A
    PJM1
    1 2 +12.6VB_DDR PRM11 Peak Current 1A
    1 2 2.2_0603_5%
    BST_DDR_R 1 2 BST_DDR

    10U_0603_25V6M

    10U_0603_25V6M
    2200P_0402_50V7K
    0.1U_0402_25V6
    JUMP_43X79 +1.2VP

    1
    @EMI@ PCM4

    PCM9

    PCM7
    EMI@ PCM12
    UG_DDR +0.6VSP

    2
    D D

    LX_DDR

    PCM18
    22U_0603_6.3V6M
    1

    1
    PCM14

    5
    0.1U_0402_25V6

    16

    17

    18

    19

    20
    2
    PUM1

    2
    PQM1

    BOOT

    VTT
    PHASE

    UGATE

    VLDOIN
    21
    AON7408L_DFN8-5 PAD
    4 LG_DDR 15 1
    LGATE VTTGND

    PLM1 14 2
    1UH_6.6A_20%_5X5X3_M PRM5 PGND VTTSNS

    1
    2
    3
    20K_0402_1%
    1 4 1 2 CS_DDR 13 3
    +1.2VP PCM10 CS RT8207PGQW_WQFN20_3X3 GND

    1
    2 3 1U_0402_6.3V6K

    5
    1 2 12 4 VTTREF_DDR
    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M
    RF@ PRM1 30MA_30V_0.5UA_0.4V_SOD323-2 PDM1 VDDP VTTREF
    1

    1
    PCM3

    PCM8

    PCM6

    PCM1
    2 1
    PCM16

    PCM15

    4.7_1206_5% PRM6
    5.1_0603_5% 11 5
    +1.2VP

    1 2
    VDD VDDQ

    1
    VDD_DDR

    PGOOD
    1 2
    +5VALW
    2

    4 PCM17
    +5VALW PRM8

    TON
    1
    RF@ PCM11 0.033U_0402_16V7K

    FB
    S5

    S3

    2
    680P_0402_50V7K PQM2 PCM5 1 2

    2
    1U_0402_6.3V6K 2.2_0603_5%

    10

    6
    2
    1
    2
    3
    AON7506_DFN3X3-8-5

    EN_DDR

    FB_DDR
    EN_0.675VSP
    TON_DDR
    PRM2
    470K_0402_1% 1 2 +1.2VP
    PRM10
    +12.6VB_DDR1 2
    C 7.68K_0402_1% C
    Vout = 0.75 X [1+(7.68k/12k)]=1.23

    1
    PRM3 0_0402_5%
    Rds-on=13mohm(Typ), 15.8mohm(Max) [58] SYSON
    1 2 PRM9
    12K_0402_1%
    Switching Frequency:530kHz

    2
    1
    Mode Level +0.675VSP VTTREF_1.35V Iocp~A
    @ PCM13 @
    0.1U_0402_10V7K PJM2
    S5 L off off OVP: 113%~120% 1 2
    +1.2VP +1.2V

    2
    S3 L off on 1 2
    VFB=0.75V, Vout=1.203V
    S0 H on on JUMP_43X118

    Note: S3 - sleep ; S5 - power off @


    PJM3
    PRM4 0_0402_5% 1 2
    1 2 +0.6VSP 1 2 +0.6VS
    [8] DDR_VTT_PG_CTRL JUMP_43X39

    1
    @ PCM2
    0.1U_0402_10V7K

    2
    +3VALW +5VALW
    1

    2
    1

    PC251
    JUMP_43X79
    2.2U_0402_16V6K Vout=0.8V* (1+Rup/Rdown)
    1

    PJ251
    2

    B @ B
    2

    PU251 @
    10 1 PJ252
    2.5V_VIN 9 VDD
    VIN
    VOUT
    VOUT
    2 +2.5VP +2.5VP
    1
    1 2
    2
    +2.5V
    1
    8 3

    43K_0402_1%
    7 VIN VOUT 4 2.5V_FB
    10U_0603_6.3V6M

    VIN ADJ/NC JUMP_43X79


    1

    2.5V_EN 6 5
    PC253

    PR252
    Rup

    10U_0603_6.3V6M
    EN PGOOD

    1
    11
    2

    PAD

    PC256
    2
    RT9059GQW_WDFN10_3X3
    1

    20K_0402_1%

    PR251
    PR254

    1 2
    Rdown
    [11,58] PM_SLP_S4#
    2

    0_0402_5%
    1

    0.1U_0402_16V7K
    PC255
    2

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Title
    Issued Date 2019/05/23 Deciphered Date 2021/05/31
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    PWR- DDR
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LAK321P
    Date: Friday, May 07, 2021 Sheet 89 of 121
    5 4 3 2 1
    A B C D E

    +3VALW
    PR1804 0_0402_5%
    +1.8VSP_ON 1 2
    3V/5VALW_PG [11,58,87]

    1
    @ PR1807 0_0402_5%

    0.1U_0402_16V7K

    1
    PR1801 1 2

    PC1805
    SLP_SUS# [11]

    1
    100K_0402_5% PR1805
    1M_0402_5%

    2
    1 @ 1
    [95] 1.8V_PGOOD PU1801

    2
    9
    1 PGND 8
    FB SGND Note:Iload(max)=2.5A
    @ 2 7 PL1801
    PJ1801 PG EN 1UH_MLV-YT12N1R0M-C1L__4A_20%
    +3VALW 1 2 3 6 LX_1.8V 1 2
    1 2 IN LX +1.8VALWP

    1
    4 5

    68P_0402_50V8J
    JUMP_43X79 PC1801 PGND NC

    1
    4.7_0603_5%

    1
    @

    RF@ PR1802

    PC1802
    22U_0603_6.3V6M
    +1.8VALW

    1
    PR1803 1 2
    Rup

    22U_0603_6.3V6M

    22U_0603_6.3V6M
    SY8003ADFC_DFN8_2X2 22.1K_0402_1% +1.8VALWP 1 2

    PC1803

    PC1804
    2
    2

    2
    PJ1802
    FB_1.8V JUMP_43X79

    1
    1
    FB=0.6V

    680P_0402_50V7K
    Note:Iload(max)=3A PR1806
    Rdown

    RF@ PC1806
    11K_0402_1%

    2
    2 2
    Note:
    When design Vin=5V, please stuff snubber
    to prevent Vin damage
    Vout=0.6V* (1+Rup/Rdown)

    3 3

    4 4

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Title
    Issued Date 2019/05/23 Deciphered Date 2021/05/31
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    PWR- 1.8VALWP
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LAK321P
    Date: Friday, May 07, 2021 Sheet 90 of 121
    A B C D E
    5 4 3 2 1

    D D

    C C

    B B

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2019/12/09 Deciphered Date 2021/05/31 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    PWR- Reserve
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LAK321P
    Date: Friday, May 07, 2021 Sheet 91 of 121
    5 4 3 2 1
    5 4 3 2 1

    D D

    C C

    B B

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2019/12/09 Deciphered Date 2021/05/31 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    PWR- Reserve
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LAK321P
    Date: Friday, May 07, 2021 Sheet 92 of 121
    5 4 3 2 1
    5 4 3 2 1

    D D

    C C

    B B

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2019/12/09 Deciphered Date 2021/05/31 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    PWR- Reserve
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LAK321P
    Date: Friday, May 07, 2021 Sheet 93 of 121
    5 4 3 2 1
    5 4 3 2 1

    D D

    C C

    B B

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2019/12/09 Deciphered Date 2021/05/31 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    PWR- Reserve
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LAK321P
    Date: Friday, May 07, 2021 Sheet 94 of 121
    5 4 3 2 1
    5 4 3 2 1

    CPU PWR controller(36.1), Driver MOS(36.2), Support component(36.3) Module model information
    MP2941_V1.mdd
    VCCIN_AUX (Base on PDG rev 0.71)
    Peak Current 26A (ICCmax)
    TDC :10A
    DC Load line :TBD mV/A
    D D
    AC Load line :TBD mV/A
    OCP Current 32A
    ES need to change to SA0000BJK10 Fsw=700kHz

    PRG106 PCG113

    1
    5.1_0402_1% 1U_0402_6.3V6K

    150K_0402_1%
    1 2 1 2

    PRG107
    +3VALW
    +12.6VB PRG113 PCG115
    +12.6VB_VINAUX

    2
    EMI@ 2.2_0603_5% 1U_0402_25V6K
    PLG11 3V3_AUX FS_AUX BST1_AUX 1 2 BST1_AUX_R 1 2
    5A_Z80_0805_2P PCG108must close IC pin2
    1 2

    18

    19

    13
    7
    3V3

    PGND_4

    BST1
    FS
    PLG1

    EMI@ PCG111

    @EMI@ PCG112
    10U_0603_25V6M

    10U_0603_25V6M

    10U_0603_25V6M

    10U_0603_25V6M

    10U_0603_25V6M

    1U_0402_25V6K

    2200P_0402_25V7K

    0.1U_0402_25V6
    1

    1
    2 12 LX1_AUX 1 4
    PCG277

    PCG101

    PCG104

    PCG102

    PCG103

    PCG108
    VIN SW1 +VCCIN_AUX
    2 3
    2

    2
    1 11
    C @ PGND_1 SW2 PRG111 C
    PRG114 PCG116 0.15UH_NA__35A_20%
    2.2_0603_5% 1U_0402_25V6K 100_0402_1%
    3 10 BST2_AUX 1 2BST2_AUX_R1 2
    PGND_2 BST2

    1
    PUG101 PRG109 0_0402_5%
    4 MP2941BGL-Z_QFN19_3X4 16 VCCIN_AUX_VCCSENSE_VR 1 2
    PGND_3 VOUT VCCIN_AUX_VCCSENSE [17]

    PRG116 0_0402_5% PRG110 0_0402_5%


    1 2 5 17 VCCIN_AUX_VSSSENSE_VR 1 2
    [17] VCCIN_AUX_CORE_VID1_R VID1 RGND VCCIN_AUX_VSSSENSE [17]
    +3VALW PRG117 0_0402_5% PRG108

    2
    1 2 6 9 1 2
    [17] VCCIN_AUX_CORE_VID0_R VID0 PG +3VALW PRG112 PRG111 and PRG112 close CPU.

    MODE
    100K_0402_1% 100_0402_1%

    CLM
    EN
    VCC_AUX_PW RGD [58]

    1
    PRG101

    14

    1 MODE_AUX 15
    1

    LX1_AUX
    100K_0402_5%

    100K_0402_5%

    0_0402_5%
    PRG118

    PRG119

    CLM_AUX
    1 2 EN_AUX

    1
    [90] 1.8V_PGOOD

    4.7_1206_5%
    PRG115
    2

    EN: high > 1.3V


    0.1U_0402_25V6

    1M_0402_5%
    1

    PRG103
    @ PCG114

    150K_0402_1%
    1

    2
    RF@
    PRG104

    @ PRG105
    150K_0402_1%
    2

    VCCIN_AUX_CORE_VID1_R
    2

    @
    SNB1_AUX
    2

    2
    B VCCIN_AUX_CORE_VID0_R B

    RF@ PCG117
    @

    680P_0402_50V7K
    2 1
    TBD under checking with MPS
    Table---1:VID control Bit logics Table---2:CLM Select Table---3:MODE Select Table---4:FS Select

    VID1 VID0 VOUT(V) State CLM Resistor to GND State Interleaving VID Down option Resistor to GND State Fs(kHz) Resistor to GND

    0 0 0 M1 7A 0 M1 N Slew down 0 M1 500 0

    0 1 1.1 M2 10A 90k M2 Y Slew down 90k M2 700 90k

    1 0 1.65 M3 13A 150k M3 Y Decay 150k M3 1000 150k

    1 1 1.8 M4 17A >230k or float M4 N Decay >230k or float M4 1200 >230k or float

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2019/05/23 Deciphered Date 2021/05/31 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    PWR- VCCIN_AUX(MP2941)
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LAK321P
    Date: Friday, May 07, 2021 Sheet 95 of 121
    5 4 3 2 1
    A
    B
    C
    D

    5
    5

    2
    1
    +

    PCG201
    330U_D2_2.5VY_R9M
    2
    1
    +
    +VCCIN_AUX

    PCG202
    220U_D7_2VM_R4.5M

    2 1 2 1

    PCG261 PCG251 2 1
    10U_0402_6.3V6M 10U_0402_6.3V6M
    +VCCIN_AUX

    2 1 2 1 PCG211
    22U_0603_6.3V6M
    PCG262 PCG252 2 1
    10U_0402_6.3V6M 10U_0402_6.3V6M

    4
    4

    2 1 2 1 PCG212
    22U_0603_6.3V6M
    PCG263 PCG253 2 1
    10U_0402_6.3V6M 10U_0402_6.3V6M
    2 1 2 1 PCG213
    22U_0603_6.3V6M
    PCG264 PCG254 2 1
    10U_0402_6.3V6M 10U_0402_6.3V6M
    2 1 2 1 PCG214
    22U_0603_6.3V6M
    PCG265 PCG255 2 1
    10U_0402_6.3V6M 10U_0402_6.3V6M
    2 1 PCG215
    22U_0603_6.3V6M
    PCG256 2 1
    22uF*6

    2 1 10U_0402_6.3V6M
    10uF*15
    330uF*1

    2 1 PCG216
    @

    PCG266 22U_0603_6.3V6M
    10U_0402_6.3V6M PCG257
    VCCIN_AUX

    2 1 10U_0402_6.3V6M
    @

    2 1 2 1
    @

    PCG267
    @

    10U_0402_6.3V6M PCG258 PCG217


    2 1 10U_0402_6.3V6M 22U_0603_6.3V6M

    Issued Date
    @

    2 1 2 1
    PCG268
    10U_0402_6.3V6M PCG259 PCG218

    Security Classification
    2 1 10U_0402_6.3V6M 22U_0603_6.3V6M
    @

    2 1 2 1
    @

    PCG269
    10U_0402_6.3V6M PCG260 PCG219
    2 1 10U_0402_6.3V6M 22U_0603_6.3V6M

    3
    3

    2 1
    @

    PCG270
    10U_0402_6.3V6M PCG220
    22U_0603_6.3V6M

    2019/12/09
    2 1

    RF@ PCG271
    12P_0402_50V8J

    2 1
    +VCCIN_AUX

    RF@ PCG272
    100P_0402_50V8J

    Compal Secret Data


    Deciphered Date
    2 1

    RF@ PCG273
    0.1U_0402_50V7K

    2 1

    @RF@ PCG274
    <5 mm from SoC

    12P_0402_50V8J

    2
    2

    2 1
    2021/05/31

    @RF@ PCG275
    100P_0402_50V8J
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

    2 1
    12P_0402*6

    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

    @RF@ PCG276
    0.1U_0402_50V7K
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Size
    Title
    VCCIN_AUX RF@

    Date:
    Custom
    close to PLG1

    Document Number

    LAK321P
    Friday, May 07, 2021
    1
    1

    Sheet
    96
    PWR- VCORE Cap
    Compal Electronics, Inc.

    of
    121
    Rev
    2.0
    A
    B
    C
    D
    5 4 3 2 1

    Module model information


    MP2940_V1A.mdd for IC portion
    MP2940_V1B.mdd for SW portion

    Rpsys=0.8/PWR_in_MAX*Isys
    =0.8/160uA
    D D
    =5k ohm @0@
    PRZ2
    0_0402_5%
    Where:
    PWR_in_Max is the maximum input power, with the unit of W. 1 2 VRACPU_VTEMP [98]

    @ PRZ3 PCZ1
    0_0402_5% 2.2U_0402_6.3V6M
    1 2 1 2
    [85] PSYS_MON

    RPSYS 1 2
    PRZ5
    2M_0402_1% PRZ6 PRZ4
    1 2 4.99K_0402_1% 49.9K_0402_1%
    +12.6VB_CPU 1 2

    PRZ7
    133K_0402_1% PCZ2

    1
    1 2 1000P_0402_25V8J PCZ3
    1 2 4.7U_0402_6.3V6M
    PE pin can be always pull high to 3.3V

    2
    PRZ8 4.7_0603_5%
    1 2 VINSENSE_MP2940 VDD33_MP2940 1 2 The leakage is 3.3V/100Kohm=0.033mA.
    +3VALW
    PCZ4 0.1U_0402_25V6 PWM1_MP2940 1 @0@ 2 PRZ9 0_0402_5%
    PWM_CORE1 [98]

    TEMP_MP2940
    PSYS_MP2940
    PWM2_MP2940 1 @0@ 2 PRZ10 0_0402_5%
    PWM_CORE2 [98]
    @0@ PRZ45 0_0402_5%
    1 2 CS3_MP2940 PWM3_MP2940 1 @0@ 2 PRZ44 0_0402_5%
    [98] CS_CORE3 PWM_CORE3 [98]
    @0@ PRZ14 0_0402_5%
    H>0.8 L<0.4
    1 2 CS2_MP2940 @0@ 1 2
    [98] CS_CORE2 VR_ON [11,58]
    PRZ13 0_0402_5%

    28

    27

    26

    25

    24

    23

    22
    +3VALW

    0.1U_0402_25V6
    C C
    @0@ PRZ15 0_0402_5%

    1
    1 2 CS1_MP2940

    PCZ5
    +3VALW

    PSYS

    TEMP
    VIN_SEN

    VDD33

    PWM1

    PWM2

    PWM3
    [98] CS_CORE1

    1
    PRZ16 @
    U42@ PRZ53 100K_0402_1%

    2
    1.5K_0402_1% @
    1 2 1 21 EN_MP2940
    CS3 EN

    1
    Vcs=(10uA*Io)*Rcs+1.23 PRZ18 100K_0402_1%

    2
    1 2 PRZ17 1.5K_0402_1% 2 U42@ PUZ1 20 PE_MP2940 1 2 @ PRZ19 @ PRZ20
    CSSUM_MP2940 CS2 MP2940AGRT-0151 PE 10K_0402_1% 10K_0402_1%
    1 2 PRZ21 1.5K_0402_1% 3 SA0000CRW10 19 STB_MP2940 1 2
    CS1 STB SYNC [98]
    @0@ PRZ22 0_0402_5%

    2
    @ PCZ6 @ PRZ26 1 2 VDIFF_MP2940 4 18 SCL_P_MP2940
    390P_0402_50V7K 4.99K_0402_1% PRZ24
    806_0402_1% VDIFF U22@ PUZ1 SCL_P
    PRZ23 1 2 1 2 1 2 5 MP2940AGRT-025E 17 SDA_P_MP2940
    100_0402_1% @ PCZ10 150P_0402_50V8J VFB SA0000DPY10 SDA_P
    1 2 6 16 VR_HOT#_R_MP2940 PRZ30
    +VCCIN VFB_MP2940 VOSEN VRHOT# 10K_0402_1%
    7 15 VRRDY_MP2940 1 2
    VORTN VRRDY +3VS

    SCLK/VID0

    SDIO/VID1
    PRZ28 1 2 0_0402_5% VOSEN_MP2940
    [15] VCCIN_VCCSENSE
    @0@ @0@ 1 2

    CSSUM

    VDD18
    VR_PWRGD [58]

    AGND
    VORTN_MP2940

    IMON
    @0@ Close1 to 20_0402_5%
    IC PRZ31 0_0402_5%

    ALT#
    IREF
    [15] VCCIN_VSSSENSE
    PRZ29
    +1.05V_VCCST
    Static Load Line Setting

    10

    VDD18_MP2940 11

    12

    13

    14

    29
    1 2

    Rdroop=RLL/2*10uA*(4/8*1/8)*1000

    1 IREF_MP2940
    PRZ32

    SVID_CLK_MP2940

    SVID_ALERT#_MP2940
    100_0402_1% CSSUM_MP2940

    SVID_DAT_MP2940
    =2m/2*10uA*(4/8*1/8)*1000

    2.2U_0402_6.3V6M

    PRZ33

    10K_0402_1%
    110_0402_1%

    100_0402_1%

    45.3_0402_1%

    0.1U_0402_25V6
    =1.6k

    1
    1

    1
    Close to CPU

    1
    IMON_MP2940

    PRZ34

    PRZ36

    PCZ7
    RIMON

    PRZ35
    @
    61.9K_0402_1%

    2
    330P_0402_50V8J

    2
    2

    2
    1

    1 @
    PRZ38
    1

    B B
    RIMON=32*(1.6*8/11)/(ICCMAX*10uA)*1000 U42@ @0@ PRZ39 1 2 0_0402_5%
    =32*(1.6*8/11)/(33*10uA)*1000 SOC_SVID_ALERT#_R [15]
    2

    PRZ37
    PCZ8

    PCZ9
    2

    =113k 57.6K_0402_1% @0@ PRZ41 1 2 0_0402_5%


    SOC_SVID_DAT_R [15]
    2

    @0@ PRZ43 1 2 0_0402_5%


    SOC_SVID_CLK_R [15]

    PRZ37=57.6k ohm for TGL-U42 ICCMAX=65A. U22@ PRZ37


    69.8K_0402_1%
    PRZ37=69.8k ohm for TGL-U22 ICCMAX=55A VR_HOT#_R_MP2940 1 2
    VR_HOT# [58]
    SD034698280 PRZ52 75_0402_5%

    1.8V LDO output for current sense

    A A

    Function Field :
    PWR.Plane.Regulator_MP2940:36.1
    Rest of support elements:36.3

    Security Classification Compal Secret Data Compal Electronics, Inc.


    2019/05/23 2021/05/31 Title
    Issued Date Deciphered Date PWR- VCORE(MP2940)
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LAK321P
    Date: Friday, May 07, 2021 Sheet 97 of 121
    5 4 3 2 1
    5 4 3 2 1

    +12.6VB_CPU
    +12.6VB EMI@ PLZ1
    5A_Z80_0805_2P
    1 2

    EMI@ PLZ2
    5A_Z80_0805_2P

    33U_25V_NC_6.3X4.5

    33U_25V_NC_6.3X4.5

    33U_25V_NC_6.3X4.5
    D
    1 2 PUZ2 D
    @0@ PRZ46

    10U_0603_25V6M

    10U_0603_25V6M

    2200P_0402_50V7K
    0_0402_5%

    PCZ13

    PCZ17
    1 1 1

    1U_0402_25V6K

    0.1U_0402_25V6
    1

    1
    1 2 14 1

    PCZ55

    PCZ56

    PCZ64

    PCZ15

    PCZ12
    + + + +3VALW VCC VIN 8 BST can't add boost resistance

    PCZ16
    VIN

    1
    2

    2
    @ PCZ34 PCZ18
    2 2 2

    EMI@
    @EMI@
    1U_0402_25V6K 0.22U_0402_25V6K

    2
    BST_VCC
    13
    AGND BST
    15 1 2 +VCCIN
    PLZ3
    2 LX_VCC 1 4
    9 SW 3
    [97] PWM_CORE1 PWM SW
    close to PUZ2 PIN1 4 2 3

    RF@ PRZ47

    4.7_1206_5%
    SW

    1
    [97] VRACPU_VTEMP 11
    VTEMP/FLT
    10 5 0.15UH_NA__35A_20%
    [97,98] SYNC SYNC PGND 6 Rdc=0.9 mohm +-5%
    12 PGND 7
    [97] CS_CORE1

    2
    CS PGND

    1SNUB_VCC
    reference GND and keep out >=20mil with MP86901-CGLT-Z_TQFN21_3X4
    other phase PWM

    680P_0402_50V7K
    +12.6VB_CPU

    RF@ PCZ21
    2
    PUZ3
    10U_0603_25V6M @0@ PRZ48

    10U_0603_25V6M

    2200P_0402_50V7K
    C C
    0_0402_5%

    PCZ24

    PCZ25
    1U_0402_25V6K

    0.1U_0402_25V6
    1

    1
    1 2 14 1
    PCZ27

    PCZ28 +3VALW VCC VIN 8

    PCZ23
    VIN BST can't add boost resistance

    1
    2

    2
    2

    2
    PCZ35 PCZ29

    EMI@
    @EMI@
    1U_0402_25V6K 0.22U_0402_25V6K

    2
    BST_VCC2
    13
    AGND BST
    15 1 2 +VCCIN
    PLZ4
    2 LX_VCC2 1 4
    9 SW 3
    [97] PWM_CORE2

    4.7_1206_5%
    PWM SW

    1
    close to PUZ3 PIN1 4 2 3

    RF@ PRZ49
    VRACPU_VTEMP 11 SW
    VTEMP/FLT
    10 5 0.15UH_NA__35A_20%
    [97,98] SYNC SYNC PGND 6 Rdc=0.9 mohm +-5%

    2
    12 PGND 7
    [97] CS_CORE2 CS PGND

    reference GND and keep out >=20mil with

    SNUB_VCC2
    MP86901-CGLT-Z_TQFN21_3X4
    other phase PWM

    +12.6VB_CPU

    680P_0402_50V7K
    1
    RF@ PCZ33
    2
    U42@
    PUZ4
    B @0@ PRZ51 B
    10U_0603_25V6M

    10U_0603_25V6M

    2200P_0402_50V7K

    0_0402_5%
    PCZ63

    PCZ57
    1U_0402_25V6K

    0.1U_0402_25V6
    1

    1
    1

    1 2 14 1
    U42@ PCZ61

    U42@ PCZ60
    U42@ PCZ59

    +3VALW VCC VIN 8 BST can't add boost resistance


    VIN
    1
    2

    2
    2

    U42@ PCZ36 U42@ PCZ62


    U42EMI@
    @U42EMI@

    1U_0402_25V6K 0.22U_0402_25V6K
    2

    BST_VCC3
    13
    AGND BST
    15 1 2
    U42@
    +VCCIN
    PLZ5
    2 LX_VCC3 1 4
    9 SW 3
    [97] PWM_CORE3

    4.7_1206_5%
    PWM SW

    1
    4 2 3

    U42RF@ PRZ50
    close to PUZ4 PIN1 VRACPU_VTEMP 11 SW
    VTEMP/FLT
    10 5 0.15UH_NA__35A_20%
    [97,98] SYNC SYNC PGND 6 Rdc=0.9 mohm +-5%

    2
    12 PGND 7
    [97] CS_CORE3 CS PGND

    reference GND and keep out >=20mil with

    SNUB_VCC3
    MP86901-CGLT-Z_TQFN21_3X4
    other phase PWM

    680P_0402_50V7K
    1
    U42RF@ PCZ58
    2
    A A
    Function Field :
    Drivers:36.2
    Rest of support elements:36.3
    CPU_Core output CAP (Including MLCC):36.4

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2019/05/23 Deciphered Date 2021/05/31 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    PWR- VCORE_SW
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LAK321P
    Date: Friday, May 07, 2021 Sheet 98 of 121
    5 4 3 2 1
    5 4 3 2 1

    D D

    C C

    B B

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2019/05/23 Deciphered Date 2021/05/31 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    PWR- Reserve
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LAK321P
    Date: Friday, May 07, 2021 Sheet 99 of 121
    5 4 3 2 1
    5 4 3 2 1

    D D

    C C

    B B

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2019/05/23 Deciphered Date 2021/05/31 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    PWR- Reserve
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LAK321P
    Date: Friday, May 07, 2021 Sheet 100 of 121
    5 4 3 2 1
    A
    B
    C
    D

    5
    5

    +VCCIN

    2 1 2 1 2 1 2 1
    2
    1
    +

    PCZ171 PCZ161 PCZ151 PCZ111 PCZ101


    10U_0402_6.3V6M 10U_0402_6.3V6M 10U_0402_6.3V6M 22U_0603_6.3V6M 330U_D2_2.5VY_R9M
    2 1 2 1 2 1 2 1
    2
    1
    +

    PCZ172 PCZ162 PCZ152 PCZ112


    10U_0402_6.3V6M 10U_0402_6.3V6M 10U_0402_6.3V6M 22U_0603_6.3V6M PCZ102
    2 1 2 1 2 1 2 1 330U_D2_2.5VY_R9M

    PCZ173 PCZ163 PCZ153 PCZ113


    10U_0402_6.3V6M 10U_0402_6.3V6M 10U_0402_6.3V6M 22U_0603_6.3V6M
    2 1 2 1 2 1 2 1

    PCZ174 PCZ164 PCZ154 PCZ114


    10U_0402_6.3V6M 10U_0402_6.3V6M 10U_0402_6.3V6M 22U_0603_6.3V6M
    2 1 2 1

    4
    4

    2 1 PCZ165 PCZ155 2 1
    10U_0402_6.3V6M 10U_0402_6.3V6M

    @
    PCZ175 2 1 2 1 PCZ115
    10U_0402_6.3V6M 22U_0603_6.3V6M

    @
    @

    2 1 PCZ166 PCZ156 2 1
    10U_0402_6.3V6M 10U_0402_6.3V6M

    @
    PCZ176 2 1 2 1 PCZ116
    10U_0402_6.3V6M 22U_0603_6.3V6M
    @

    2 1 PCZ167 PCZ157 2 1
    VCCIN

    10U_0402_6.3V6M 10U_0402_6.3V6M
    22uF*4

    @
    PCZ177 2 1 2 1 PCZ117
    10uF*24
    330uF*1

    10U_0402_6.3V6M 22U_0603_6.3V6M
    @

    2 1 PCZ168 PCZ158 2 1
    10U_0402_6.3V6M 10U_0402_6.3V6M

    @
    PCZ178 2 1 2 1 PCZ118
    10U_0402_6.3V6M 22U_0603_6.3V6M
    @

    2 1 PCZ169 PCZ159 2 1
    10U_0402_6.3V6M 10U_0402_6.3V6M

    @
    PCZ179 2 1 2 1 PCZ119
    10U_0402_6.3V6M 22U_0603_6.3V6M
    @

    2 1 PCZ170 PCZ160 2 1
    10U_0402_6.3V6M 10U_0402_6.3V6M

    @
    PCZ180 PCZ120

    Issued Date
    10U_0402_6.3V6M 22U_0603_6.3V6M

    Security Classification

    3
    3

    2 1

    RF@ PCZ181
    +VCCIN

    12P_0402_50V8J

    2019/05/23
    2 1

    RF@ PCZ182
    100P_0402_50V8J

    2 1
    <5 mm from SoC

    RF@ PCZ183
    0.1U_0402_50V7K

    2 1

    @RF@ PCZ184
    12P_0402_50V8J

    Compal Secret Data


    Deciphered Date
    2 1
    12P_0402*6

    @RF@ PCZ185
    VCCIN RF@

    100P_0402_50V8J

    2 1
    close to PLZ3

    @RF@ PCZ186

    2
    2

    0.1U_0402_50V7K
    2021/05/31

    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Size
    Title

    Date:
    Custom
    Document Number

    LAK321P
    Friday, May 07, 2021
    1
    1

    Sheet
    101
    PWR- VCORE Cap
    Compal Electronics, Inc.

    of
    121
    Rev
    2.0
    A
    B
    C
    D
    5 4 3 2 1

    D D

    C C

    B B

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2019/12/09 Deciphered Date 2021/05/31 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    PWR- Reserve
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LAK321P
    Date: Friday, May 07, 2021 Sheet 102 of 121
    5 4 3 2 1
    5 4 3 2 1

    D D

    +5VALW

    2
    VGA@
    VGA@ PCV45 PRV26
    2.2U_0402_25V6M 2.2_0603_5%
    2 1

    1
    VGA@ PRV113
    2.2_0402_1%

    1
    2 1 NVVDD_VIN_R VGA@
    +12.6VB_VGA PCV8
    2.2U_0402_16V6K

    2
    VGA@ PRV118
    10K_0402_5%
    1 2 fS=300k Hz VGA@
    +3VS PUV1
    VGA@ PRV117 NVVDD_VCC 17
    High: >0.7V @VGA@ [27,31] DGPU_PWROK VCC 20 NVVDD_PWM1
    332K_0402_1% NVVDD_PWM1 [104]
    Low: <0.3V PRV31 2 1 NVVDD_VIN 8 PWM1
    0_0402_5% VIN
    [30,37] DGPU_MAIN_EN 2 1 NVVDD_EN_R

    1 19 NVVDD_PWM2

    VGA@ PCV20
    NVVDD_PWM2 [104]

    0.1U_0402_25V6
    PGOOD PWM2

    1
    PRV10 0_0402_5% 2
    2 1 +1.8VS_DGPU_AON NVVDD_PSI_R 3 EN
    [37] VGA_CORE_EN PSI
    NVVDD_VID_R 4

    2
    NVVDD_VREF 7 PWMVID 18
    C C
    VREF PWM3

    2
    @VGA@

    100K_0201_1%
    VGA@
    NVVDD_REFADJ 5

    PRV119
    REFADJ PRV23
    PRV32
    NVVDD_REFIN 6 16 NVVDD_ISEN1 NVVDD_ISEN1 [104] 10_0402_1%
    PRV116 0_0201_5%
    0_0201_5% 2 1 REFIN ISEN1 2 1
    [30] GPU_VID0
    +VGA_CORE

    1
    1 2 NVVDD_PSI_R 15 NVVDD_ISEN2 NVVDD_ISEN2 [104] +5VALW
    [30] PSI ISEN2

    49.9K_0201_1%
    VGA@ PRV104 14 NVVDD_ISEN3 1 2 PRV13
    PRV120 10.5K_0402_1% ISEN3 VGA@ PRV27 10K_0402_1% 0_0402_5%
    2 1 NVVDD_PINSET1 11 2 1
    PINSET1 13 NVVDD_CSN VDD_SENSE_GPU [29]
    PRV42 CSN

    NVVDD_PINSET1_R
    @VGA@ NVVDD_CSN [104]
    1

    1
    1 2 2 1 12 VGA@ @VGA@ PCV3
    NVVDD_VREF 0_0402_5% PINSET2 PCV10 0.01U_0402_16V7K

    NVVDD_PINSET2
    RREF1 PHV1 0.01UF_0402_25V7K 1 2

    2
    1

    10K_0402_1%_B25/50 3370K 10 NVVDD_VSEN


    VSEN
    1

    VGA@ VGA@ PCV14 VGA@ 21


    PRV1 1U_0402_6.3V6K GND 9 NVVDD_FBRTN 2 1
    R2
    2

    20.5K_0402_1% FBRTN VGA@ PRV24


    RREFADJ RT8843AGQW_WQFN20_3X3
    R1 10_0402_1%

    1
    2

    1 2 NVVDD_REFADJ PRV124 VGA@


    RBOOT PRV106 VGA@ 825_0402_1% 2 1
    4700P_0402_50V7K

    1
    VGA@ PRV3 16.5K_0402_1% GND_SENSE_GPU [29]
    C
    1

    6.19K_0402_1% PRV15
    VGA@ PCV2

    2
    1

    VGA@ VGA@ PRV45 VGA@ PRV115 0_0402_5%


    R3 PRV2 3K_0402_1% 240_0402_1% PCV4 @VGA@
    2

    1
    4.32K_0402_1% VGA@ 0.01U_0402_16V7K

    2
    VGA@ PRV122 PRV127 2
    1.1K_0402_1% 825_0402_1%
    2

    1
    2

    2
    NVVDD_REFIN VGA@ PRV125 VGA@ PRV121
    NVVDD_VREF

    2.43K_0402_1% 470_0402_1%
    RREF2

    2
    VGA@
    16.5K_0402_1%
    1

    NVVDD_VCC
    B B
    PRV4

    R4
    1

    VGA@
    1 2

    PCV16
    4700P_0402_50V7K
    309_0402_1%

    2
    PRV5

    VGA@
    2

    R5

    R1//(R3+R4+R5) = 4.787k
    R1//R2=4.754K

    Vboot = Vref X [Ref2/(Ref1+Rboot+Ref2)]


    Vboot=2*[(R4+R5) / (R2+R3+R4+R5)]
    Vboot=2*[(16.5k+309) / (20.5k+4.32k+16.5k+309)] = 0.8076

    Vmin=Vvref X [Rref2/(Rref2+Rboot)]X[(Rrefadj//(Rboot+Rref2))/(Rref1+(Rrefadj//(Rboot+Rref2)))]
    Vmin=2 X [(R4+R5)/((R4+R5)+R3)]X[(R1//(R3+(R4+R5)))/(R2+(R1//(R3+(R4+R5))))]

    Vmax=Vvref X [Rref2/((Rref1//Rrefadj)+Rboot+Rref2)]
    Vmax=2 X [(R4+R5)/(R2//R1)+R3+(R4+R5))]

    Vmin=2 X [(R4+R5)/((R4+R5)+R3)]X[(R1//(R3+(R4+R5)))/(R2+(R1//(R3+(R4+R5))))] =0.3V

    A Vmax=2 X [(R4+R5)/(R2//R1)+R3+(R4+R5))] =1.3 A

    Security Classification Compal Secret Data


    Title
    Compal Electronics, Inc.
    Issued Date 2019/12/09 Deciphered Date 2021/05/31
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    PWR- GPU_CORE
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 2.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LAK321P
    Date: Friday, May 07, 2021 Sheet 103 of 121
    5 4 3 2 1
    5 4 3 2 1

    +VGA_CORE
    EDP-Continuous 35A
    EDP-Peak 75A
    OCP > Need larger than (A)
    Please base on GPU spec to calculate.
    D D

    VGA@
    PUV2
    +12.6VB_VGA +12.6VB
    11 10
    12 VSWH1 PGND 9 VGA@ VGA_EMI@ PLV3 5A_Z80_0805_2P
    VSWH2 VIN1 PCV28
    13 8 1 2
    VGA@ GL VIN 0.1U_0402_25V6
    +5VALW PRV101 14 7 1 2 BST1_R_NVVDD

    2200P_0402_50V7K
    1 2 15 PGND1 VSWH 6

    PCV29

    PCV30

    10U_0603_25V6M

    10U_0603_25V6M

    10U_0603_25V6M

    10U_0603_25V6M
    0.1U_0402_25V6
    PVCC NC1

    VGA@ PCV146

    VGA@ PCV149

    VGA@ PCV150
    1

    1
    BST1_NVVDD

    VGA@ PCV23
    5.1_0402_1% 16 5 2 1
    17 NC2 BOOT 4
    VGA@ NC3 NC

    VGA_EMI@
    @VGA_EMI@
    PRV105 2.2_0603_5%

    2
    3
    PCV21 VCC 2 VGA@
    1U_0402_10V6K 18 FCCM 1

    2
    AGND PWM

    AOZ5038QI-05_QFN31_5X5
    Rdc=0.9m ohm±5%
    NVVDD_PWM1 VGA@ 0.15UH_NA__35A_20% +VGA_CORE
    +5VALW [103] NVVDD_PWM1 PLV1
    LX1_NVVDD 1 4

    1 2 FCCM_NVVDD 2 3 NVVDD_CSN1

    VGA_EMI@ PRV114
    4.7_1206_5%
    1
    PRV128 10K_0402_5%

    1
    NVVDD_ISEN1_R
    VGA@
    VGA@ PRV82
    1_0402_1%

    2
    @VGA@ +5VALW VGA@

    1SNUB1_NVVDD 2
    PRV129 PCV38

    2
    1 2
    100K_0402_5% 0.1U_0402_25V6K
    1 2 1 2 1 2
    PRV88 5.1_0402_1%

    1
    VGA@ PRV79 VGA@ PRV81 VGA@ @VGA@ PRV84

    1
    VGA@
    825_0402_1% 825_0402_1% 560_0402_1%
    PCV50 1 2
    1U_0402_10V6K

    2
    C PCV42 VGA_EMI@ C
    680P_0402_50V7K

    2
    NVVDD_CSN
    NVVDD_CSN [103]

    NVVDD_ISEN1
    NVVDD_ISEN1 [103]

    PUV3
    11 10
    12 VSWH1 PGND 9 +12.6VB_VGA
    VSWH2 VIN1 VGA@ PCV41
    13 8
    VGA@ GL VIN 0.1U_0402_25V6
    +5VALW PRV107 14 7 1 2 BST2_R_NVVDD

    PCV31

    10U_0603_25V6M

    10U_0603_25V6M

    10U_0603_25V6M

    10U_0603_25V6M
    2200P_0402_50V7K
    1 2 15 PGND1 VSWH 6

    PCV32

    VGA@ PCV36

    VGA@ PCV35

    VGA@ PCV151

    VGA@ PCV152
    0.1U_0402_25V6

    1
    PVCC NC1

    1
    5.1_0402_1% 16 5 BST2_NVVDD 2 1
    17 NC2 BOOT 4

    2
    VGA@ NC3 NC

    VGA_EMI@
    @VGA_EMI@
    1

    PRV112 2.2_0603_5%

    2
    3
    PCV33 VCC 2 VGA@
    1U_0402_10V6K 18 FCCM 1
    2

    AGND PWM

    B AOZ5038QI-05_QFN31_5X5 Rdc=0.9m ohm±5% B


    VGA@
    NVVDD_PWM2 VGA@ PLV2 +VGA_CORE
    [103] NVVDD_PWM2 0.15UH_NA__35A_20%
    LX2_NVVDD 1 4

    VGA_EMI@ PRV111 2 3 NVVDD_CSN2


    4.7_1206_5%
    FCCM_NVVDD 1

    1
    FBVDD_ISEN2_R
    VGA@
    PRV94
    1_0402_1%
    +5VALW VGA@
    2

    PCV25

    2
    1 2
    1VRAM2_SNUB

    0.1U_0402_25V6K
    1 2 1 2 1 2
    VGA@ PRV110
    5.1_0402_1% VGA@ PRV95 VGA@ PRV93 VGA@ @VGA@ PRV97
    1

    825_0402_1% 825_0402_1% 560_0402_1%


    PCV34 1 2
    1U_0402_10V6K
    2

    PCV40 VGA_EMI@
    680P_0402_50V7K
    2

    NVVDD_CSN
    NVVDD_ISEN2

    [103] NVVDD_ISEN2

    A A

    Security Classification Compal Secret Data


    Title
    Compal Electronics, Inc.
    Issued Date 2019/12/09 Deciphered Date 2021/05/31
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    PWR- GPU_CORE_SW
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    D 2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LAK321P
    Friday, May 07, 2021
    Date: Sheet 104 of 121
    5 4 3 2 1
    5 4 3 2 1

    D D

    C C

    B B

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2019/12/09 Deciphered Date 2021/05/31 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    PWR- Reserve
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LAK321P
    Date: Friday, May 07, 2021 Sheet 105 of 121
    5 4 3 2 1
    5 4 3 2 1

    D D

    C C

    B B

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2019/12/09 Deciphered Date 2021/05/31 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    PWR- Reserve
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LAK321P
    Date: Friday, May 07, 2021 Sheet 106 of 121
    5 4 3 2 1
    A
    B
    C
    D

    1
    1

    +VGA_CORE
    2 1

    2 1 2 1 VGA@ PCV65
    22U_0603_6.3V6M
    VGA@ PCV79 @VGA@ PCV63 2 1
    22U_0603_6.3V6M 22U_0603_6.3V6M
    2 1 2 1 VGA@ PCV66
    22U_0603_6.3V6M
    VGA@ PCV85 @VGA@ PCV61
    22U_0603_6.3V6M 22U_0603_6.3V6M
    2 1 2 1
    +VGA_CORE

    VGA@ PCV84 @VGA@ PCV62


    22U_0603_6.3V6M 22U_0603_6.3V6M
    2 1 2 1
    2
    1
    +

    @VGA@ PCV74 @VGA@ PCV64 VGA@ PCV121


    D7

    22U_0603_6.3V6M 22U_0603_6.3V6M 220U_D7_2VM_R4.5M


    2 1

    VGA@ PCV111
    22U_0603_6.3V6M
    2 1
    2
    1
    +

    VGA@ PCV112 2 1 VGA@ PCV122


    B2

    22U_0603_6.3V6M 330U_B2_2.5VM_R9M
    VGA@ PCV91
    2
    1
    +

    22U_0603_6.3V6M
    2 1 VGA@ PCV123

    2
    2

    330U_B2_2.5VM_R9M
    VGA@ PCV92
    22U_0603_6.3V6M
    2
    1
    +

    2 1
    VGA@ PCV90
    @VGA@ PCV93 330U_B2_2.5VM_R9M
    22U_0603_6.3V6M
    2 1
    VGA@ PCV94
    22U_0603_6.3V6M
    1uF 0201 *5

    4.7uF 0402 *4
    10uF 0402 *12

    22uF 0603 * 10(+6)


    VGA_CORE output cap

    10uF 0805 * 0 (11) x

    Issued Date
    2 1

    Security Classification
    VGA@ PCV71
    10U_0402_6.3V6M
    2 1 2 1
    +VGA_CORE

    VGA@ PCV72
    VGA@ PCV53

    3
    3

    10U_0402_6.3V6M 1U_0201_6.3V6M
    2 1 2 1

    VGA@ PCV80
    VGA@ PCV55
    10U_0402_6.3V6M 1U_0201_6.3V6M
    2 1 2 1

    2019/12/09
    VGA@ PCV78
    VGA@ PCV51
    10U_0402_6.3V6M 1U_0201_6.3V6M
    2 1 2 1

    VGA@ PCV83
    VGA@ PCV54
    10U_0402_6.3V6M 1U_0201_6.3V6M
    2 1 2 1

    VGA@ VGA@ PCV52


    PCV81
    10U_0402_6.3V6M 1U_0201_6.3V6M
    2 1
    VGA@ PCV86
    10U_0402_6.3V6M
    2 1

    Compal Secret Data


    Deciphered Date
    VGA@ PCV82
    10U_0402_6.3V6M
    2 1
    VGA@ PCV77
    10U_0402_6.3V6M
    2 1
    GB4-128 package

    VGA@ PCV73

    4
    4

    10U_0402_6.3V6M
    2 1
    2021/05/31

    VGA@ PCV75
    10U_0402_6.3V6M
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

    2 1

    VGA@ PCV76
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

    10U_0402_6.3V6M 2 1
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

    @VGA_RF@ PCV147
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

    0.1U_0402_50V7K

    2 1
    Size
    Title

    Date:
    Custom

    @VGA_RF@ PCV148
    +VGA_CORE

    0.1U_0402_50V7K
    Document Number

    LAK321P
    Friday, May 07, 2021
    5
    5

    Sheet
    close to PLV1

    PWR- GPU_CORE Cap

    107
    Compal Electronics, Inc.

    of
    22U_0603_6.3V

    1U_0402_16V 5pcs

    121
    330U_B2_2.5V 3pcs

    10U_0603_6.3V 13pcs
    4pcs
    VGA_CORE output cap

    Rev
    2.0
    A
    B
    C
    D
    5 4 3 2 1

    +5VALW

    2
    VGA@
    PCW1 VGA@ PRW1
    2.2U_0402_25V6M 2.2_0603_5%
    2 1

    1
    VGA@ PRW2
    2.2_0402_1%

    1
    2 1 FBVDD_VIN_R VGA@
    +12.6VB_FBVDDQ PCW2
    D D
    2.2U_0402_16V6K

    2
    @VGA@ PRW3
    10K_0402_5%
    @VGA@ PDW1 1 2 fS=300k Hz VGA@
    30MA_30V_0.5UA_0.4V_SOD323-2 +3VS PUW1
    1 2 VGA@ PRW4 FBVDD_VCC 17
    [37] +1.35VGS_PGOOD VCC 20 FBVDD_PWM1
    332K_0402_1%
    2 1 FBVDD_VIN 8 PWM1
    PRW6 0_0402_5% VIN
    [31] 1.35V_PWR_EN 2 1 FBVDD_EN_R

    1 19

    VGA@ PCW3
    0.1U_0402_25V6
    PGOOD PWM2

    1
    High: >0.7V 2
    +1.8VS_DGPU_AON FBVDD_PSI_R 3 EN
    Low: <0.3V @VGA@ FBVDD_VID_R 4 PSI

    2
    PRW9 FBVDD_VREF 7 PWMVID 18
    VREF PWM3

    2
    For DR.MOS @VGA@ 0_0402_5%
    PRW40 2 1 FBVDD_REFADJ 5
    REFADJ
    10K_0402_1%
    FBVDD_REFIN 6 16 FBVDD_ISEN1 +5VALW
    FBVDD_VREF REFIN ISEN1

    1
    RREF1 FBVDD_PSI_R 15 FBVDD_ISEN2 1 2
    ISEN2
    1

    VGA@ PRW39 10K_0402_1%


    1

    2
    VGA@ VGA@ PCW6 VGA@ PRW13 14 FBVDD_ISEN3 1 2
    PRW16 1U_0402_6.3V6K VGA@ 2.74K_0402_1% ISEN3 VGA@ PRW12 10K_0402_1%
    R2
    2

    10K_0402_1% PRW11 2 1 FBVDD_PINSET1 11


    RREFADJ 10K_0402_1% PINSET1 13 FBVDD_CSN
    R1 CSN

    FBVDD_PINSET1_R
    PRW15
    2

    1
    @VGA@ 1 2 FBVDD_REFADJ 1 2 2 1 12 VGA@ PCW5 PRW10
    RBOOT 0_0402_5% PINSET2 1 2 0_0402_5%
    4700P_0402_50V7K

    FBVDD_PINSET2
    @VGA@ PRW18 PHW1
    1

    6.19K_0402_1% 10K_0402_1%_B25/50 3370K 10 0.01UF_0402_25V7K 2 1


    PCW7

    VGA@ 21 VSEN +1.2VS_VRAM


    GND 9
    R3
    2

    FBRTN @VGA@ PCW4


    C RT8843AGQW_WQFN20_3X3 0.01U_0402_16V7K

    1
    1
    FBVDD_VSEN 1 2
    C VGA@ PRW20 VGA@ C
    N18S-G5 GDDR6 VRAM, 1.2V only PRW19 9.09K_0402_1%

    1
    FBVDD_REFIN 97.6K_0402_1% PRW17
    VGA@ FBVDD_FBRTN 2 1

    2
    2
    RREF2 Vboot=2*[(R4+R5) / (R2+R3+R4+R5)] VGA@ PRW23 PRW24
    3K_0402_1% 3K_0402_1% 1 0_0402_5%
    15.4K_0402_1%
    1

    1
    Vboot=2*[(16K) / (10K+16K)] =1.23V

    2
    R4 PRW25 PRW26 PCW8 @VGA@
    PRW29

    0_0402_5% 0_0402_5% 0.01U_0402_16V7K

    1
    2

    teknisi-indonesia.com
    VGA@
    1
    2

    2
    @VGA@ PCW9 VGA@ PRW27 VGA@ PRW28
    0.1U_0402_25V6 23.7K_0402_1% 470_0402_1%

    FBVDD_VREF
    2

    2
    FBVDD_VCC
    R5

    VGA@
    PUW2
    11
    VSWH1 PGND
    10 +12.6VB_FBVDDQ
    12 9 VGA@ VGA_EMI@ PLW1
    VSWH2 VIN1 PCW10 5A_Z80_0805_2P
    +5VALW 13 8 +12.6VB_FBVDDQ 2 1
    VGA@ GL VIN 0.1U_0402_25V6 +12.6VB
    PRW31 14 7 VSWH_FBVDD 1 2 BST1_R_FBVDD
    2200P_0402_50V7K

    1 2 FBVDD_MOS_PVCC 15 PGND1 VSWH 6

    10U_0603_25V6M

    10U_0603_25V6M

    10U_0603_25V6M

    10U_0603_25V6M
    VGA_EMI@ PCW15
    @VGA_EMI@ PCW14
    0.1U_0402_25V6

    B PVCC NC1 B

    VGA@ PCW17

    VGA@ PCW18

    VGA@ PCW19
    1

    1
    1

    1
    BST1_FBVDD
    VGA@ PCW16
    5.1_0402_1% 16 5 2 1
    17 NC2 BOOT 4
    VGA@ NC3 NC
    PRW32 2.2_0603_5%
    1

    2
    2

    2
    3
    PCW20 VCC 2 VGA@
    1U_0402_10V6K 18 FCCM 1
    2

    AGND PWM

    AOZ5038QI-05_QFN31_5X5
    Rdc=6.2m ohm±5% Iout: 11A(EDP-continue)
    VGA@
    FBVDD_PWM1 PLW2 0.47UH_NA__12.2A_20% +1.2VS_VRAM Ipeak:11A
    +5VALW Iocp=A
    LX1_FBVDD 1 4 OVP: ~155%
    1 2 FCCM_FBVDD
    2 3 FBVDD_CSN1_R
    VGA_EMI@ PRW33
    4.7_1206_5%

    330U_B2_2.5VM_R9M
    1

    VGA@ PRW41 1

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M
    22U_0603_6.3V6M
    22U_0603_6.3V6M

    0.1U_0402_50V7K
    2

    1
    SW1_FBVDDQ_R

    10K_0402_5% @VGA@ VGA@ 1 1 1 1 1 1 1


    +5VALW

    VGA@ PCW21
    PRW42 PRW34 +

    PCW22

    PCW24

    PCW25

    PCW27
    PCW26
    PCW23

    @VGA_RF@ PCW28
    100K_0402_5% 1_0402_1%
    1 2 FBVDD_MOS_VCC VGA@
    1SNUB1_FBVDD 2

    PCW29 2 2 2 2 2 2 2 2
    VGA@

    VGA@
    VGA@
    1

    5.1_0402_1% VGA@ VGA@ 0.1U_0402_25V6K

    VGA@

    VGA@

    VGA@
    PRW35

    VGA@
    1 2 1 2 1 2

    PRW36 PRW37 VGA@ PRW38


    1

    PCW30 VGA@ 1.18K_0402_1% 1.18K_0402_1% 1.1K_0402_1%


    1 2
    1U_0402_10V6K
    close to PLW2
    2

    PCW31 VGA_EMI@
    680P_0402_50V7K
    2

    FBVDD_ISEN1 FBVDD_CSN

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2019/12/09 Deciphered Date 2021/05/31 Title
    PWR- GPU_VRAM
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 2.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LAK321P
    Date: Friday, May 07, 2021 Sheet 108 of 121
    5 4 3 2 1
    5 4 3 2 1

    D D

    C C

    B B

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2019/12/09 Deciphered Date 2021/05/31 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    PWR- Reserve
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LAK321P
    Date: Friday, May 07, 2021 Sheet 109 of 121
    5 4 3 2 1
    5 4 3 2 1

    D D

    Imax= 2A, Ipeak= 3A


    VGA@ PCE1 FB=0.6V
    +3VALW 22U_0603_6.3V6M
    +3VS VOUT=0.6×(1+RH/RL)
    1 2
    1
    VGA@
    PRE6
    10K_0402_5% @ VGA@
    PJE1
    PUE1
    1 2 VGA@ PLE1
    2

    1 2
    4 3 LX_1.0VS 1 2
    JUMP_43X39 IN LX +1.0VS
    5 2 1UH_MLV-YT12N1R0M-C1L__4A_20%

    68P_0402_50V8J
    [31,37] 1.0VSDGPU_PG PG GND @

    1
    6 1

    VGA@ PCE3

    22U_0603_6.3V6M

    22U_0603_6.3V6M
    FB EN PJE2

    1
    RFVGA@

    VGA@ PCE4

    VGA@ PCE6
    1
    PRE5 1 2
    +1.0VS +1.0VS_DGPU

    2
    SY8032IABC_SOT23-6 VGA@ PRE3 1 2

    2
    PRE1 0_0402_5% 4.7_0603_5% 10K_0402_1%
    1 2 EN_1.0VS JUMP_43X39
    [37] 1.0VS_DGPU_EN

    2
    Rup

    2
    0.1U_0402_16V7K
    1

    @VGA@ PCE2
    VGA@ PRE2 1 FB_1.0VS
    C 1M_0402_1% C
    2

    1
    EN :H>1.2V ; L<0.4V RFVGA@
    2

    PCE5
    680P_0402_50V7K VGA@ PRE4

    2
    EN pin don't floating 15K_0402_1%
    Rdown

    2
    Note:
    When design Vin=5V, please stuff snubber
    to prevent Vin damage
    Vout = 0.6*(1+ 10k / 15k ) = 1

    B B

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2019/05/23 Deciphered Date 2021/05/31 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    PWR- GPU_1.0V
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LAK321P
    Date: Friday, May 07, 2021 Sheet 110 of 121
    5 4 3 2 1
    A B C D

    Module model information


    1
    RT9297_V1.mdd 1

    Must check PL501 and PD501 rating


    for your application.
    Add a switch circuit to turn off the +12V_VIN if need.
    RFVGA@ PR1201 RFVGA@ PC1201
    VGA@ PQ1201 4.7_1206_5% 680P_0402_50V7K
    AONR21321_DFN 3X3 EP 1 2+12V_SNUB 1 2
    @ 1
    PJ1201 2 @VGA@ VGA@ PL1201 VGA@
    1 2 3 PC1207 2.2UH_MMD-04BZ-2R2M-X2_3A_20% PD1201
    +5VALW 1 2 5 1500P_0402_50V7K +12V_VIN 1 2 +12V_LX 2 1
    +12VP

    22U_0603_6.3V6M
    JUMP_43X39
    1

    1
    VGA@
    SX34F_SMAF2

    PC1202
    2 2

    1
    VGA@ PC1204
    1

    1
    VGA@ VGA@ 1U_0402_6.3V6K @VGA@ VGA@ VGA@

    7
    PR1202 PC1203 1 2 PC1205 PR1203 PC1206

    2
    100K_0402_1% 0.022U_0402_25V7K 100P_0402_50V8J 105K_0402_1% 22U_0805_25V6M

    LX

    LX
    2

    2
    2
    8 2 +12V_FB
    +5VALW Vin FB VGA@ PC1208
    0.01U_0402_50V7K

    1
    9 10 +12V_SS1 2 VGA@
    FREQ SS PR1204
    1

    VGA@ PR1209 0_0402_5%


    PR1205 1 2 +12V_EN 3 1 +12V_COMP
    12K_0402_1% Vout=1.24V* (1+Rup/Rdown)
    10K_0402_1% EN COMP

    2
    1
    VGA@

    1
    @VGA@ PR1208

    GND

    GND
    PAD
    2

    PR1207 56K_0402_1%
    100K_0402_1%

    11

    2
    +12V_COMP_1

    2
    VGA@

    1
    PU1201 VGA@
    RT9297GQW _W DFN10_3X3 PC1209
    330P_0402_50V8J

    2
    PR1210
    0_0402_5%
    EN high: > VIN pin* 0.7
    D
    1

    VGA@ EN Low: < VIN pin* 0.3


    1 2 2 PQ1202
    58,78] SUSP#
    3 G L2N7002W T1G_SC70-3 3

    S
    3

    FREQ high : Frequency = 1.2MHz


    FREQ low : Frequency = 640KHz
    1

    @VGA@
    PC1210
    1500P_0402_50V7K
    2

    If the out put is for I/O port, should be add


    protection circuit for I/O short protection.
    @
    PJ1202
    JUMP_43X39
    1 2
    +12VP 1 2 +12V

    4 4

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2019/05/23 Deciphered Date 2021/05/31 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    PWR- 12V
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LAK321P
    Date: Friday, May 07, 2021 Sheet 111 of 121
    A B C D
    5 4 3 2 1

    D D

    C C

    B B

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2019/12/09 Deciphered Date 2021/05/31 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    PWR- Reserve
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LAK321P
    Date: Friday, May 07, 2021 Sheet 112 of 121
    5 4 3 2 1
    5 4 3 2 1

    D D

    C C

    B B

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2019/12/09 Deciphered Date 2021/05/31 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    PWR- Reserve
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LAK321P
    Date: Friday, May 07, 2021 Sheet 113 of 121
    5 4 3 2 1
    5 4 3 2 1

    D D

    C C

    B B

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2019/12/09 Deciphered Date 2021/05/31 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    PWR- Reserve
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LAK321P
    Date: Friday, May 07, 2021 Sheet 114 of 121
    5 4 3 2 1
    5 4 3 2 1

    D D

    C C

    B B

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2019/12/09 Deciphered Date 2021/05/31 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    PWR- Reserve
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LAK321P
    Date: Friday, May 07, 2021 Sheet 115 of 121
    5 4 3 2 1
    5 4 3 2 1

    D D

    C C

    B B

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2019/12/09 Deciphered Date 2021/05/31 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    PWR- Reserve
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LAK321P
    Date: Friday, May 07, 2021 Sheet 116 of 121
    5 4 3 2 1
    5 4 3 2 1

    D D

    C C

    B B

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2019/12/09 Deciphered Date 2021/05/31 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    PWR- Reserve
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LAK321P
    Date: Friday, May 07, 2021 Sheet 117 of 121
    5 4 3 2 1
    5 4 3 2 1

    D D

    C C

    B B

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2019/12/09 Deciphered Date 2021/05/31 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    PWR- Reserve
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LAK321P
    Date: Friday, May 07, 2021 Sheet 118 of 121
    5 4 3 2 1
    5 4 3 2 1

    Version change list (P.I.R. List) Page 1 of 2 for


    PWR
    Item Reason for change PG# Modify List Date Phase

    1 For Voltage deviation 103,108 Mount PCV14 & PCW6 (1U_0402_6.3V6K) 4/1 SDV2
    2 Dr.Mos FCC pin Voltage insufficient 104,108 PRW41 & PRV128 From 100K_0402 change to 10K_0402 4/1 SDV2
    3 Part count reduce 108 Remove PRW22 & PRW30 4/1 SDV2
    D
    4 Adjust VRAM voltage 108 PRW29 from 15K change to 15.4k 4/1 SDV2 D

    5 Fix VRAM cannot Power on PRW37 From 374 change to 806_0402 , Mount PRW38 (1.1K_0402_1% ) SDV2
    Change DCR sense R & C Parameter setting. 108 PRW19 From 182K change to 118K_0402 , PRW20 From 169K change to 11K_0402 4/1
    PRW25 & PRW26 change to R-short
    6 Change component size 103 PRV23 , PRV13 , PRV24 , PRV15 ,PRV31 & PRV10 from 0201 change to 0402 4/7 SDV2
    7 Change component size 103,108 PRV27 ,PRW39 & PRW12 from 0201 change to 0402 4/8 SDV2
    8 Adjustment MLCC mount location 96 Mount PCG268 , UnmountPCG258 4/9 SDV2
    9 For ACFET rating, Size from 3x3 change to 5x6 82 PQS12 From AON7380_DFN3X3-8-5 change to EMB04N03H_EDFN5X6-8-5 4/13 SDV2
    10 RF demand 96,101 Mount PCG271,PCG272,PCG273,PCZ181,PCZ182,PCZ183 4/14 SDV2
    11 HW Suggest 108 Unmount PDW1 4/14 SDV2
    Change VRAM OCP setting from 14A to 16A 108 PRW19 From 118k change to 97.6k.PRW20 From 11k change to 9.09k.
    12 PRW36 From 806 change to 1.18k.PRW37 From 374 change to 1.18k. 4/14 SDV2
    PRW27 From 2.43k change to 23.7kPRW24 From 240 change to 3k
    13 Repeat pull-height 108 Unmount PRW3 4/20 SDV2
    14 HW Suggest 89 PRM2 from 6.04k change to 7.68k 4/23 SDV2
    Adjustment DDR Voltage from 1.2v to 1.23v PRM9 from 10k change to 12k
    15 Unified P/N 104 PLV1 & PLV2 From SH00001DC00 change to SH00001EF00(Common part ) 4/24 SDV2
    16 Fix NVVDD Overshoot/undershoot issue 103 Mount PCV16 (SE074472K80, S CER CAP 4700P 50V K X7R 0402) 4/30 SDV2
    17 For cost 82 PQS12 From EMB04N03H_EDFN5X6-8-5 change to AON7380_DFN3X3-8-5 5/4 SIT
    C
    18 Part count reduce PR508 ,PR510, PRM3 , PRM4 , PR251 ,PR1804 , PRG116 , PR117 , PRG109 , PRG110 5/8 SIT C
    PRV10 , PRW6 , PRE1 , PR1210 , PR1209 , PRV116 , PRV32 , PRV42 , PRW15 , PRV42
    PRB32 from 0 ohm change to R- short
    19 Unified P/N 106 PCG201 Form SGA00002680 Change to SGA0000E800 (Common part) 5/13 SIT
    20 Part count reduce 95 PRG101 From 0 ohm change to R-short 5/14 SIT

    B B

    21

    22

    A
    23 A

    24

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2019/05/23 Deciphered Date 2021/05/31 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    PWR- PIR (1/2)
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LAK321P
    Date: Friday, May 07, 2021 Sheet 119 of 121
    5 4 3 2 1
    5 4 3 2 1

    Version change list (P.I.R. List) Page 2 of 2 for


    PWR
    Item Reason for change PG# Modify List Date Phase

    EX XX EX XX XX
    25

    D D

    C C

    B B

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2019/05/23 Deciphered Date 2021/05/31 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    PWR- PIR (2/2)
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LAK321P
    Date: Friday, May 07, 2021 Sheet 120 of 121
    5 4 3 2 1
    5 4 3 2 1

    Version change list Page 1 of 1 for


    (P.I.R. List) HW
    Item Reason for change PG# Modify List Date Phase

    1 For fixing headset auto swap issue 56 RA33 change from 0 ohm to 200K ohm 2020/3/30 SDV->SIT
    D D
    2 For GPU Power Bead source supply 28 L14 change footprint from 0603 to 0402 2020/4/15 SDV->SIT

    3 For better power shape 29 RV462 change from 0805 0 ohm to J3 43x79 Jump 2020/5/04 SDV->SIT

    4 For Thermal GPU Prochot require 30 change GPU GPIO 9 to GPIO 12 2020/6/15 SIT->SIT-R

    5 For TGL common design 11 Combine 2 SOT323 package (QC2 & QC3) into 1 SOT363 package 2020/6/15 SIT->SIT-R

    6 For Sequence design reserve 11/90 Reserve SLP_SUS# to +1.8VSP_ON circuit 2020/6/15 SIT->SIT-R

    7 For Finger Print power switch design reserve 58/66 Add QFP1 & CFP2 & RFP11 2020/7/16 SIT->SIT-R

    8
    9
    C
    10 C

    11

    12
    13
    14
    15
    16

    17

    B 18 B

    19
    20
    21
    22
    23

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2019/11/27 Deciphered Date 2020/11/27 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    PIR (HW)
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 2.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K321P
    Date: Thursday, June 03, 2021 Sheet 121 of 121
    5 4 3 2 1

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