A B C D E

LCFC Confidential
1 1

CG411/CG511 MB Schematics Document

Intel Skylake-U22/Kabylake-U22 with DDR4 + Nvidia N16S-GTR/N16V-GMR1 GPU
2 2

2016-01-09
REV:1.0

3 3

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 Cover Page
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG411
Date: Thursday, January 14, 2016 Sheet 1 of 60
A B C D E
 A B C D E

LCFC confidential
NV N16S-GTR/N16V-GMR1
DDR4 SO-DIMM x1
Page 18
Package: GB2B-64
Page 19~24 PCIe Port 9~12
PCI-Express Memory Bus (Dual Channel)
VRAM: 256*16 4x Gen3 1.2V DDR4 2133MT/s DDR4 Memory Down
DDR3L*8/*4: 4GB/2GB 4pcs x16 Page 17
1 Page 25~29 1

USB3.0 x1 USB3.0 Left Conn

HDMI Conn. HDMI (DDI 1) USB2.0 x1 USB3.0 Port1
USB2.0 Port1 Page 41
Page 34

DP to VGA USB3.0 x1 3D Camera (Optional)

VGA Conn. DP x2 Lane (DDI 2)
ITE IT6516BFN USB3.0 Port3 Page 31
Page 36
Page 35

eDP x2 Lane
eDP Conn USB3.0 x1 USB3.0 Right Conn 1 (Optional)
USB2.0 x1
Intel MCP USB3.0 Port2 Page 45
Int. Camera Conn.
USB2.0 Port4
USB2.0 x1 USB2.0 Right Conn 1
Int. MIC Conn. SKL-U22 15W USB2.0 Port3 Page 45

Page 33 KBL-U22 15W USB2.0 x1 USB2.0 Right Conn 2

2 2

USB2.0 Port2 Page 45

USB Board
SATA HDD SATA Gen3 x1
Page 42 SATA Port0
BGA-1356 USB2.0 x1 Touch Screen (Optional)
SATA Gen1 x1
42mm*24mm USB2.0 Port6 Page 33
SATA ODD
Page 42 SATA Port1A

USB2.0 x1 Card Reader SD/MMC Conn.

LAN Chip Realtek RTS5170
RJ45 Conn. PCIe Gen1 x1 USB2.0 Port5 Page 30
Page 38
Realtek_RTL8111GUL
Realtek_RTL8111H_CG
Page 37 PCIe Port5 PCIe Gen1 x1 NGFF WLAN&BT
USB2.0 x1 PCIe Port6
HD Audio
USB2.0 Port7 Page 40

Codec SPI SPI ROM (8MB)

3 SPK Conn. W25Q64FVSSIQ 3
Conexant_CX11802_33Z Page 43 Page 07
Page 43

Page 3~16
HP&Mic Combo Conn. SPI ROM (4MB) (Reserved)
Page 43 W25Q32FVSSIQ
LPC Page 07

Sub-board( for 14")

USB BOARD
EC TPM (Reserved)
ITE IT8586E-LQFP Z32H320TC
Page 44 Page 32
TP BOARD

Sub-board( for 15")

Touch Pad Int.KBD Thermal Sensor (Reserved)
NCT7718W USB BOARD
Page 45 Page 45 Page 39

4 TP BOARD 4

ODD  BOARD

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 Block Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG411
WWW.AliSaler.Com
A B C D
Date: Thursday, January 14, 2016
E
Sheet 2 of 60
 A B C D E

Voltage Rails ( O --> Means ON , X --> Means OFF )

SIGNAL
STATE SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

Power Plane Full ON HIGH HIGH HIGH ON ON ON ON

+3VALW +5VS S3 (Suspend to RAM) LOW HIGH HIGH ON ON OFF OFF

+5VALW +1.2V +3VS

S4 (Suspend to Disk) LOW LOW LOW ON OFF OFF OFF
1 +VCCIO 1

V20B+ +3VALW_PCH +2.5V_DDR +VCCSTG S5 (Soft OFF) LOW LOW LOW ON OFF OFF OFF
+VCCSA
+1.8VALW +VCCST +VCC_GT
+1.0VALW +CPU_CORE
State +0.6VS
HSIO PORT Function BOM Structure BTO Item
1 USB3.0 Conn Left @ Not stuff
2 USB3.0 Conn Right(optional) 14@ For 14" part
3 3D Camera(optional) 15@ For 15" part
USB3.0 4 NC For 14" or 15" part
14or15@
S0 O O O O 5 NC 14or17@ For 14" or 17" part
6 NC
1 USB3.0 Conn Left
S3 O O O X 2 USB2.0 Conn1 Right Cannonlake@ For Cannonlake part
3 USB2.0 Conn2 Right CD@ For C cost down
4 Camera DUALMIC@ For Dual MIC part
S3
2
Battery only O O O X USB2.0 5 Cardreader EMC@ For EMC part 2

6 Touch Panel EMC_15@ For EMC 15" part

7 Bluetooth EMC_NS@ For EMC nu-stuff part
S5 S4
AC Only O O X X 8 NC EMC_PX@ For EMC PX part
9 NC EMC_PXNS@ For EMC PX nu-stuff part
10 NC ES@ For ES CPU
S5 S4
Battery only O X X X 1 NC EXO@ For EXO GPU
2 NC
3 NC ME@ For ME part
S5 S4
4 NC NTS@ For nu-touch part
AC & Battery X X X X 5 LAN
don't exist
PCIE 6 WLAN
7 used as SATA
SMBUS Control Table 8 used as SATA PX@ For PX part
RANKA@ For VRAM rank A part
SOURCE BATT Charger DGPU IT8586E Memory PCH PMIC SODIMM Thermal WLAN RANKB@ For VRAM rank B part
Down Sensor WiMAX 9~12 DGPU
Realtek_SD@ For Realtek SD part
X4 PCIE
SINGLEMIC@ For single MIC part
3 3
EC_SMB_CK1 IT8586E 0 HDD SINGLERANK@ For single VRAN rank part
V V X V X X X X X X
EC_SMB_DA1 +3VL_EC +3VL_EC 1A ODD DUALRANK@ For dual VRAN rank part
SATA 1B used as PCIE For touch screen part
TS@
EC_SMB_CK2 IT8586E 2 used as PCIE TPM@ For TPM part
X X V V X V X X V X
EC_SMB_DA2 +3VS +3VG_AON +3VS +3VALW_PCH UMA@ For UMA part

EC_SMB_CK3 IT8586E
X X X V X X V X X X
EC_SMB_DA3 +3VL_EC +3VL_EC

PCH_SMB_CLK PCH
X X X X X V X V X V
PCH_SMB_DATA +3VALW_PCH +3VALW_PCH +3VS +3VS

EC SMBus1 address EC SMBus2 address EC SMBus3 address PCH SM Bus address

Device Address Device Address Device Address Device Address
Smart Battery need to update Thermal Sensor(NCT7718W) 1001_100xb PMIC need to update DDR4 SODIMM need to update
4 4
Charger 0001 0010 b PCH need to update Wlan Reserved
DGPU need to update

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG411
Date: Thursday, January 14, 2016 Sheet 3 of 60
A B C D E
 5 4 3 2 1

SKL_ULT ?
UC1A

HDMI_TX2- E55 C47 CPU_EDP_TX0-

34 HDMI_TX2- HDMI_TX2+ DDI1_TXN[0] EDP_TXN[0] CPU_EDP_TX0+ CPU_EDP_TX0- 33
HDMI D2 F55 C46 confirmed with ITE, the HPD
D 34 HDMI_TX2+ HDMI_TX1- DDI1_TXP[0] EDP_TXP[0] CPU_EDP_TX1- CPU_EDP_TX0+ 33 D
E58 D46 pull down resistor should follow
34 HDMI_TX1- HDMI_TX1+ DDI1_TXN[1] EDP_TXN[1] CPU_EDP_TX1+ CPU_EDP_TX1- 33
HDMI D1 F58 C45
34 HDMI_TX1+ HDMI_TX0- F53 DDI1_TXP[1] EDP_TXP[1] A45
CPU_EDP_TX1+ 33 ITE recommended resistor 4.7k~10Kohm
34 HDMI_TX0- HDMI_TX0+ DDI1_TXN[2] EDP_TXN[2]
HDMI D0 G53 B45
34 HDMI_TX0+ HDMI_CLK- DDI1_TXP[2] EDP_TXP[2]
F56 A47
34 HDMI_CLK- HDMI_CLK+ DDI1_TXN[3] EDP_TXN[3]
HDMI CLK G56 B47
34 HDMI_CLK+ DDI1_TXP[3] EDP_TXP[3] +3VS
VGA_TX0- C50 E45 CPU_EDP_AUX#
35 VGA_TX0- VGA_TX0+ DDI2_TXN[0] DDI EDP EDP_AUXN CPU_EDP_AUX CPU_EDP_AUX# 33
D50 F45
35 VGA_TX0+ VGA_TX1- DDI2_TXP[0] EDP_AUXP CPU_EDP_AUX 33
DP TO VGA Converter C52
35 VGA_TX1- VGA_TX1+ DDI2_TXN[1] GPP_E15
D52 B52 RC1601 1 @ 2 10K_0402_5%
35 VGA_TX1+ DDI2_TXP[1] EDP_DISP_UTIL
A50
B50 DDI2_TXN[2] G50
D51 DDI2_TXP[2] DDI1_AUXN F50
DDI2_TXN[3] DDI1_AUXP

2
C51 E48 VGA_AUX#
DDI2_TXP[3] DDI2_AUXN VGA_AUX VGA_AUX# 35
F48 RC37
DDI2_AUXP G46 VGA_AUX 35
DDI3_AUXN 4.7K_0402_5%
DISPLAY SIDEBANDS F46
DDPB_CLK L13 DDI3_AUXP

1
34 DDPB_CLK DDPB_DATA L12 GPP_E18/DDPB_CTRLCLK L9 HDMI_HPD
34 DDPB_DATA GPP_E19/DDPB_CTRLDATA GPP_E13/DDPB_HPD0 DP_VGA_HPD HDMI_HPD 34
L7
DDPC_CLK GPP_E14/DDPC_HPD1 GPP_E15 DP_VGA_HPD 35
N7 L6 RC181 1 @ 2 0_0402_5%
DDPC_DATA GPP_E20/DDPC_CTRLCLK GPP_E15/DDPD_HPD2 EC_SCI# 44
N8 N9
GPP_E21/DDPC_CTRLDATA GPP_E16/DDPE_HPD3 L10 CPU_EDP_HPD
GPP_E17/EDP_HPD CPU_EDP_HPD 33
N11
GPP_E22/DDPD_CTRLCLK

1
+VCCIO N12 R12 PCH_ENBKL
GPP_E23/DDPD_CTRLDATA EDP_BKLTEN PCH_EDP_PWM PCH_ENBKL 33
R11 RC13
RC4 2 1 24.9_0402_1% EDP_COMP E52 EDP_BKLTCTL U13 PCH_ENVDD PCH_EDP_PWM 33 100K_0402_5%
EDP_RCOMP EDP_VDDEN PCH_ENVDD 33
1 OF 20
+VCCIO&EDP_COMP : SKYLAKE-U_BGA1356

2
Trace Width: 20mil REV = 1 ?
+VCCST_CPU
C
Isolation Spacing: 25mil @
C
Max length: 100mil

1
+VCCSTG
RC1625
@ 49.9_0402_1%
1

RC19 UC1D SKL_ULT ?

2
1K_0402_5% XDP_TCK RC1546 1 @ 2 0_0402_5% JTAGX RC1551 1 2 51_0402_5%
check PROCHOT# circuit with PWR CATERR# D63
H_PECI A54 CATERR# XDP_TDO RC1547 1 @ 2 0_0402_5% PCH_JTAG_TDO RC1543 1 2 51_0402_5%
44 H_PECI +VCCSTG
2

RC20 1 2 499 +-1% 0402 H_PROCHOT#_R C65 PECI

44,55 H_PROCHOT# PROCHOT# JTAG
H_THRMTRIP# C63
A65 THERMTRIP# B61 XDP_TCK 1 PAD @ XDP_TDI RC1548 1 @ 2 0_0402_5% PCH_JTAG_TDI
SKTOCC# PROC_TCK XDP_TDI TC15
CPU MISC D60 1 PAD @
PROC_TDI TC16
1

PAD @ TC11 1 XDP_BPM0# C55 A61 XDP_TDO 1 PAD @ XDP_TMS RC1549 1 @ 2 0_0402_5% PCH_JTAG_TMS
XDP_BPM1# BPM#[0] PROC_TDO XDP_TMS TC17
RC143 PAD @ TC12 1 D55 C60 1 PAD @
XDP_BPM2# BPM#[1] PROC_TMS XDP_TRST# TC18 XDP_TRST# PCH_JTAG_TRST#
1K_0402_5% PAD @ TC13 1 B54 B59 1 PAD @ RC1550 1 @ 2 0_0402_5%
XDP_BPM3# BPM#[2] PROC_TRST# TC27
PAD @ TC14 1 C56
BPM#[3] B56 PCH_JTAG_TCK 1 PAD @
TC29
2

PAD @ TC162 1 GPP_E3 A6 PCH_JTAG_TCK D59 PCH_JTAG_TDI 1 PAD @

GPP_E3/CPU_GP0 PCH_JTAG_TDI TC31 check JTAG circuit?
+VCCST_CPU PAD @ TC163 1 GPP_E7 A7 A56 PCH_JTAG_TDO 1 PAD @
GPP_E7/CPU_GP1 PCH_JTAG_TDO PCH_JTAG_TMS TC35
BA5 C59 1 PAD @
GPP_B3/CPU_GP2 PCH_JTAG_TMS PCH_JTAG_TRST# TC36
check H_THRMTRIP# if need to connector to EC AY5 C61 1 PAD @
GPP_B4/CPU_GP3 PCH_TRST# TC42
A59 JTAGX 1 PAD @
PROC_OPI_RCOMP JTAGX TC43
RC155 1 2 49.9_0402_1% AT16
RC156 1 2 49.9_0402_1% PCH_OPI_RCOMP AU16 PROC_POPIRCOMP
U23E@ RC157 1 2 49.9_0402_1% EDRAM_OPIO_RCOMP H66 PCH_OPIRCOMP
U23E@ RC170 1 2 49.9_0402_1% EOPIO_RCOMP H65 OPCE_RCOMP
OPC_RCOMP

SKYLAKE-U_BGA1356 1 OF 20
REV = 1 ?
B @ B

check DDPC_CLK pull high or not?

+3VS

RPC19
8 1 DDPC_CLK
7 2 DDPC_DATA
6 3 DDPB_CLK
5 4 DDPB_DATA

2.2K_0804_8P4R_5%

DDP*_CTRLDATA strapping sampled on the rising edge of PWROK

Port Strap Enable Disable

Pull up to 3.3 V
Port 1 DDPB_CTRLDATA with 2.2Kohm NC
Pull up to 3.3 V
Port 2 DDPC_CTRLDATA with 2.2Kohm NC

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (DDI,EDP)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG411
Date: Thursday, January 14, 2016 Sheet 4 of 60
5 4 3 2 1

WWW.AliSaler.Com
 5 4 3 2 1

?
SKL_ULT
UC1B

AU53
17 DDRA_DQ[0..63] DDRA_DQ0 DDR0_CKN[0] DDRA_CLK0# 17
AL71 AT53
DDRA_DQ1 DDR0_DQ[0] DDR0_CKP[0] DDRA_CLK0 17
AL68 AU55
DDRA_DQ2 AN68 DDR0_DQ[1] DDR0_CKN[1] AT55
DDRA_DQ3 AN69 DDR0_DQ[2] DDR0_CKP[1]
DDRA_DQ4 AL70 DDR0_DQ[3] BA56
DDRA_DQ5 DDR0_DQ[4] DDR0_CKE[0] DDRA_CKE0 17
AL69 BB56
DDRA_DQ6 AN70 DDR0_DQ[5] DDR0_CKE[1] AW56
DDRA_DQ7 AN71 DDR0_DQ[6] DDR0_CKE[2] AY56
DDRA_DQ8 AR70 DDR0_DQ[7] DDR0_CKE[3]
D DDRA_DQ9 AR68 DDR0_DQ[8] AU45 D
DDRA_DQ10 DDR0_DQ[9] DDR0_CS#[0] DDRA_CS0# 17
AU71 AU43
DDRA_DQ11 AU68 DDR0_DQ[10] DDR0_CS#[1] AT45
DDRA_DQ12 DDR0_DQ[11] DDR0_ODT[0] DDRA_ODT0 17
AR71 AT43
DDRA_DQ13 AR69 DDR0_DQ[12] DDR0_ODT[1]
DDRA_DQ14 AU70 DDR0_DQ[13] BA51
DDRA_DQ15 DDR0_DQ[14] DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] DDRA_MA5 17
AU69 BB54
DDRA_DQ16 DDR0_DQ[15] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] DDRA_MA9 17
BB65 BA52
DDRA_DQ17 DDR0_DQ[16]/DDR0_DQ[32] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] DDRA_MA6 17
AW65 AY52
DDRA_DQ18 DDR0_DQ[17]/DDR0_DQ[33] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] DDRA_MA8 17
AW63 AW52
DDRA_DQ19 DDR0_DQ[18]/DDR0_DQ[34] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] DDRA_MA7 17
AY63 AY55
DDRA_DQ20 DDR0_DQ[19]/DDR0_DQ[35] DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] DDRA_BG0 17
BA65 AW54
DDRA_DQ21 DDR0_DQ[20]/DDR0_DQ[36] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] DDRA_MA12 17
AY65 BA54
DDRA_DQ22 DDR0_DQ[21]/DDR0_DQ[37] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] DDRA_MA11 17
BA63 BA55
DDRA_DQ23 DDR0_DQ[22]/DDR0_DQ[38] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# DDRA_ACT# 17
BB63 AY54
DDRA_DQ24 BA61 DDR0_DQ[23]/DDR0_DQ[39] DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]
DDRA_DQ25 AW61 DDR0_DQ[24]/DDR0_DQ[40] AU46
DDRA_DQ26 DDR0_DQ[25]/DDR0_DQ[41] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] DDRA_MA13 17
BB59 AU48
DDRA_DQ27 DDR0_DQ[26]/DDR0_DQ[42] DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15] DDRA_MA15_CAS# 17
AW59 AT46
DDRA_DQ28 DDR0_DQ[27]/DDR0_DQ[43] DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14] DDRA_MA14_WE# 17
BB61 AU50
DDRA_DQ29 DDR0_DQ[28]/DDR0_DQ[44] DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16] DDRA_MA16_RAS# 17
AY61 AU52
DDRA_DQ30 DDR0_DQ[29]/DDR0_DQ[45] DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] DDRA_BS0# 17
BA59 AY51
DDRA_DQ31 DDR0_DQ[30]/DDR0_DQ[46] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] DDRA_MA2 17
AY59 AT48
DDRA_DQ32 DDR0_DQ[31]/DDR0_DQ[47] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] DDRA_BS1# 17
AY39 AT50
DDRA_DQ33 DDR0_DQ[32]/DDR1_DQ[0] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] DDRA_MA10 17
AW39 BB50
DDRA_DQ34 DDR0_DQ[33]/DDR1_DQ[1] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] DDRA_MA1 17
AY37 AY50
DDRA_DQ35 DDR0_DQ[34]/DDR1_DQ[2] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] DDRA_MA0 17
AW37 BA50
DDRA_DQ36 DDR0_DQ[35]/DDR1_DQ[3] DDR0_MA[3] DDRA_MA3 17
BB39 BB52
DDRA_DQ37 DDR0_DQ[36]/DDR1_DQ[4] DDR0_MA[4] DDRA_MA4 17
BA39
DDRA_DQ38 BA37 DDR0_DQ[37]/DDR1_DQ[5] AM70 DDRA_DQS#0
DDRA_DQ39 BB37 DDR0_DQ[38]/DDR1_DQ[6] DDR0_DQSN[0] AM69 DDRA_DQS0
DDRA_DQ40 AY35 DDR0_DQ[39]/DDR1_DQ[7] DDR0_DQSP[0] AT69 DDRA_DQS#1
C DDRA_DQ41 AW35 DDR0_DQ[40]/DDR1_DQ[8] DDR0_DQSN[1] AT70 DDRA_DQS1 C
DDRA_DQ42 AY33 DDR0_DQ[41]/DDR1_DQ[9] DDR0_DQSP[1] BA64 DDRA_DQS#2
DDRA_DQ43 AW33 DDR0_DQ[42]/DDR1_DQ[10] DDR0_DQSN[2]/DDR0_DQSN[4] AY64 DDRA_DQS2 DDRA_DQS#[0..7]
DDRA_DQ44 DDR0_DQ[43]/DDR1_DQ[11] DDR0_DQSP[2]/DDR0_DQSP[4] DDRA_DQS#3 DDRA_DQS#[0..7] 17
BB35 AY60
DDRA_DQ45 BA35 DDR0_DQ[44]/DDR1_DQ[12] DDR0_DQSN[3]/DDR0_DQSN[5] BA60 DDRA_DQS3 DDRA_DQS[0..7]
DDRA_DQ46 DDR0_DQ[45]/DDR1_DQ[13] DDR0_DQSP[3]/DDR0_DQSP[5] DDRA_DQS#4 DDRA_DQS[0..7] 17
BA33 BA38
DDRA_DQ47 BB33 DDR0_DQ[46]/DDR1_DQ[14] DDR0_DQSN[4]/DDR1_DQSN[0] AY38 DDRA_DQS4
DDRA_DQ48 AY31 DDR0_DQ[47]/DDR1_DQ[15] DDR0_DQSP[4]/DDR1_DQSP[0] AY34 DDRA_DQS#5
DDRA_DQ49 AW31 DDR0_DQ[48]/DDR1_DQ[32] DDR0_DQSN[5]/DDR1_DQSN[1] BA34 DDRA_DQS5
DDRA_DQ50 AY29 DDR0_DQ[49]/DDR1_DQ[33] DDR0_DQSP[5]/DDR1_DQSP[1] BA30 DDRA_DQS#6
DDRA_DQ51 AW29 DDR0_DQ[50]/DDR1_DQ[34] DDR0_DQSN[6]/DDR1_DQSN[4] AY30 DDRA_DQS6
DDRA_DQ52 BB31 DDR0_DQ[51]/DDR1_DQ[35] DDR0_DQSP[6]/DDR1_DQSP[4] AY26 DDRA_DQS#7
DDRA_DQ53 BA31 DDR0_DQ[52]/DDR1_DQ[36] DDR0_DQSN[7]/DDR1_DQSN[5] BA26 DDRA_DQS7
DDRA_DQ54 BA29 DDR0_DQ[53]/DDR1_DQ[37] DDR0_DQSP[7]/DDR1_DQSP[5]
DDRA_DQ55 BB29 DDR0_DQ[54]/DDR1_DQ[38] AW50
DDRA_DQ56 DDR0_DQ[55]/DDR1_DQ[39] DDR0_ALERT# DDRA_ALERT# 17
AY27 AT52
DDRA_DQ57 DDR0_DQ[56]/DDR1_DQ[40] DDR0_PAR DDRA_PAR 17
AW27 SMVREF
DDRA_DQ58 AY25 DDR0_DQ[57]/DDR1_DQ[41] AY67
DDR0_DQ[58]/DDR1_DQ[42] DDR_VREF_CA DDR_SA_VREFCA 17 WIDTH:20MIL
DDRA_DQ59 AW25 AY68 SPACING: 20MIL
DDRA_DQ60 BB27 DDR0_DQ[59]/DDR1_DQ[43] DDR CH - A
DDR0_VREF_DQ BA67
DDRA_DQ61 DDR0_DQ[60]/DDR1_DQ[44] DDR1_VREF_DQ DDR_SB_VREFCA 18
BA27
DDRA_DQ62 BA25 DDR0_DQ[61]/DDR1_DQ[45] AW67 DDR_VTT_CNTL
DDRA_DQ63 BB25 DDR0_DQ[62]/DDR1_DQ[46] DDR_VTT_CNTL
DDR0_DQ[63]/DDR1_DQ[47]
1 OF 20
SKYLAKE-U_BGA1356
REV = 1 ?
@

B B

+3VALW

RC30
100K_0402_5%
2

CPU_DRAMPG_CNTL 55
+1.2V
1

C
RC3 1 2 2 QC18
1K_0402_5% B
E
3

MMBT3904WH_SOT323-3

DDR_VTT_CNTL
2

RC29
10K_0402_5%
@
1

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (DDR4)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG411
Date: Thursday, January 14, 2016 Sheet 5 of 60
5 4 3 2 1
 5 4 3 2 1

?
SKL_ULT
UC1C
18 DDRB_DQ[0..63]

DDRB_DQ0 AF65 AN45

DDRB_DQ1 DDR1_DQ[0]/DDR0_DQ[16] DDR1_CKN[0] DDRB_CLK0# 18
AF64 AN46
DDRB_DQ2 DDR1_DQ[1]/DDR0_DQ[17] DDR1_CKN[1] DDRB_CLK1# 18
AK65 AP45
DDRB_DQ3 DDR1_DQ[2]/DDR0_DQ[18] DDR1_CKP[0] DDRB_CLK0 18
AK64 AP46
DDRB_DQ4 DDR1_DQ[3]/DDR0_DQ[19] DDR1_CKP[1] DDRB_CLK1 18
AF66
D DDRB_DQ5 AF67 DDR1_DQ[4]/DDR0_DQ[20] AN56 D
DDRB_DQ6 DDR1_DQ[5]/DDR0_DQ[21] DDR1_CKE[0] DDRB_CKE0 18
AK67 AP55
DDRB_DQ7 DDR1_DQ[6]/DDR0_DQ[22] DDR1_CKE[1] DDRB_CKE1 18
AK66 AN55
DDRB_DQ8 AF70 DDR1_DQ[7]/DDR0_DQ[23] DDR1_CKE[2] AP53
DDRB_DQ9 AF68 DDR1_DQ[8]/DDR0_DQ[24] DDR1_CKE[3]
DDRB_DQ10 AH71 DDR1_DQ[9]/DDR0_DQ[25] BB42
DDRB_DQ11 DDR1_DQ[10]/DDR0_DQ[26] DDR1_CS#[0] DDRB_CS0# 18
AH68 AY42
DDRB_DQ12 DDR1_DQ[11]/DDR0_DQ[27] DDR1_CS#[1] DDRB_CS1# 18
AF71 BA42
DDRB_DQ13 DDR1_DQ[12]/DDR0_DQ[28] DDR1_ODT[0] DDRB_ODT0 18
AF69 AW42
DDRB_DQ14 DDR1_DQ[13]/DDR0_DQ[29] DDR1_ODT[1] DDRB_ODT1 18
AH70
DDRB_DQ15 AH69 DDR1_DQ[14]/DDR0_DQ[30] AY48
DDRB_DQ16 DDR1_DQ[15]/DDR0_DQ[31] DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] DDRB_MA5 18
AT66 AP50
DDRB_DQ17 DDR1_DQ[16]/DDR0_DQ[48] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] DDRB_MA9 18
AU66 BA48
DDRB_DQ18 DDR1_DQ[17]/DDR0_DQ[49] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] DDRB_MA6 18
AP65 BB48
DDRB_DQ19 DDR1_DQ[18]/DDR0_DQ[50] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] DDRB_MA8 18
AN65 AP48
DDRB_DQ20 DDR1_DQ[19]/DDR0_DQ[51] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] DDRB_MA7 18
AN66 AP52
DDRB_DQ21 DDR1_DQ[20]/DDR0_DQ[52] DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] DDRB_BG0 18
AP66 AN50
DDRB_DQ22 DDR1_DQ[21]/DDR0_DQ[53] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] DDRB_MA12 18
AT65 AN48
DDRB_DQ23 DDR1_DQ[22]/DDR0_DQ[54] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] DDRB_MA11 18
AU65 AN53
DDRB_DQ24 DDR1_DQ[23]/DDR0_DQ[55] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# DDRB_ACT# 18
AT61 AN52
DDRB_DQ25 DDR1_DQ[24]/DDR0_DQ[56] DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1] DDRB_BG1 18
AU61
DDRB_DQ26 AP60 DDR1_DQ[25]/DDR0_DQ[57] BA43
DDRB_DQ27 DDR1_DQ[26]/DDR0_DQ[58] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13] DDRB_MA13 18
AN60 AY43
DDRB_DQ28 DDR1_DQ[27]/DDR0_DQ[59] DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15] DDRB_MA15_CAS# 18
AN61 AY44
DDRB_DQ29 DDR1_DQ[28]/DDR0_DQ[60] DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14] DDRB_MA14_WE# 18
AP61 AW44
DDRB_DQ30 DDR1_DQ[29]/DDR0_DQ[61] DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16] DDRB_MA16_RAS# 18
AT60 BB44
DDRB_DQ31 DDR1_DQ[30]/DDR0_DQ[62] DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] DDRB_BS0# 18
AU60 AY47
DDRB_DQ32 DDR1_DQ[31]/DDR0_DQ[63] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2] DDRB_MA2 18
AU40 BA44
DDRB_DQ33 DDR1_DQ[32]/DDR1_DQ[16] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] DDRB_BS1# 18
AT40 AW46
DDRB_DQ34 DDR1_DQ[33]/DDR1_DQ[17] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] DDRB_MA10 18
AT37 AY46
DDRB_DQ35 DDR1_DQ[34]/DDR1_DQ[18] DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] DDRB_MA1 18
AU37 BA46
DDRB_DQ36 DDR1_DQ[35]/DDR1_DQ[19] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0] DDRB_MA0 18
AR40 BB46
C DDRB_DQ37 DDR1_DQ[36]/DDR1_DQ[20] DDR1_MA[3] DDRB_MA3 18 C
AP40 BA47
DDRB_DQ38 DDR1_DQ[37]/DDR1_DQ[21] DDR1_MA[4] DDRB_MA4 18
AP37
DDRB_DQ39 AR37 DDR1_DQ[38]/DDR1_DQ[22] AH66 DDRB_DQS#0
DDRB_DQ40 AT33 DDR1_DQ[39]/DDR1_DQ[23] DDR1_DQSN[0]/DDR0_DQSN[2] AH65 DDRB_DQS0
DDRB_DQ41 AU33 DDR1_DQ[40]/DDR1_DQ[24] DDR1_DQSP[0]/DDR0_DQSP[2] AG69 DDRB_DQS#1
DDRB_DQ42 AU30 DDR1_DQ[41]/DDR1_DQ[25] DDR1_DQSN[1]/DDR0_DQSN[3] AG70 DDRB_DQS1
DDRB_DQ43 AT30 DDR1_DQ[42]/DDR1_DQ[26] DDR1_DQSP[1]/DDR0_DQSP[3] AR66 DDRB_DQS#2
DDRB_DQ44 AR33 DDR1_DQ[43]/DDR1_DQ[27] DDR1_DQSN[2]/DDR0_DQSN[6] AR65 DDRB_DQS2
DDRB_DQ45 AP33 DDR1_DQ[44]/DDR1_DQ[28] DDR1_DQSP[2]/DDR0_DQSP[6] AR61 DDRB_DQS#3 DDRB_DQS#[0..7]
DDRB_DQ46 DDR1_DQ[45]/DDR1_DQ[29] DDR1_DQSN[3]/DDR0_DQSN[7] DDRB_DQS3 DDRB_DQS#[0..7] 18
AR30 AR60
DDRB_DQ47 AP30 DDR1_DQ[46]/DDR1_DQ[30] DDR1_DQSP[3]/DDR0_DQSP[7] AT38 DDRB_DQS#4 DDRB_DQS[0..7]
DDRB_DQ48 DDR1_DQ[47]/DDR1_DQ[31] DDR1_DQSN[4]/DDR1_DQSN[2] DDRB_DQS4 DDRB_DQS[0..7] 18
AU27 AR38
DDRB_DQ49 AT27 DDR1_DQ[48] DDR1_DQSP[4]/DDR1_DQSP[2] AT32 DDRB_DQS#5
DDRB_DQ50 AT25 DDR1_DQ[49] DDR1_DQSN[5]/DDR1_DQSN[3] AR32 DDRB_DQS5
DDRB_DQ51 AU25 DDR1_DQ[50] DDR1_DQSP[5]/DDR1_DQSP[3] AR25 DDRB_DQS#6
DDRB_DQ52 AP27 DDR1_DQ[51] DDR1_DQSN[6] AR27 DDRB_DQS6
DDRB_DQ53 AN27 DDR1_DQ[52] DDR1_DQSP[6] AR22 DDRB_DQS#7
DDRB_DQ54 AN25 DDR1_DQ[53] DDR1_DQSN[7] AR21 DDRB_DQS7
DDRB_DQ55 AP25 DDR1_DQ[54] DDR1_DQSP[7]
DDRB_DQ56 AT22 DDR1_DQ[55] AN43
DDRB_DQ57 DDR1_DQ[56] DDR1_ALERT# DDRB_ALERT# 18
AU22 AP43
DDRB_DQ58 DDR1_DQ[57] DDR1_PAR CPU_DRAMRST#_R DDRB_PAR 18
AU21 AT13
DDRB_DQ59 AT21 DDR1_DQ[58] DRAM_RESET# AR18 SM_RCOMP_0 RC24 1 2 121_0402_1%
DDRB_DQ60 AN22 DDR1_DQ[59] DDR_RCOMP[0] AT18 SM_RCOMP_1 RC25 1 2 80.6_0402_1%
DDRB_DQ61 AP22 DDR1_DQ[60] DDR_RCOMP[1] AU18 SM_RCOMP_2 RC26 1 2 100_0402_1%
DDRB_DQ62 AP21 DDR1_DQ[61] DDR_RCOMP[2]
DDRB_DQ63 AN21 DDR1_DQ[62] DDR CH - B
DDR1_DQ[63]

SKYLAKE-U_BGA1356 1 OF 20
REV = 1 ?
B @ B

+1.2V

1
RC22
2 470_0402_5%

RC23 1 @ 2 0_0402_5% CPU_DRAMRST#_R

17,18 CPU_DRAMRST#
1
CC1
0.01U_0201_25V6-K
EMC_NS@
2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (DDR4)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG411
WWW.AliSaler.Com
5 4 3 2
Date: Thursday, January 14, 2016
1
Sheet 6 of 60
 5 4 3 2 1

?
SKL_ULT
UC1E
+3VALW_PCH +3VS +3VS
SPI - FLASH
SMBUS, SMLINK
SPI_CLK RC1539 1 2 15_0402_5% SPI_CLK_R SPI_CLK_R AV2 R7 PCH_SMB_CLK
44 SPI_CLK SPI_CLK_1 SPI_SO_R SPI0_CLK GPP_C0/SMBCLK PCH_SMB_DATA
RC1538 1 @ 2 33_0402_5% AW3 R8 DIMM, NGFF
SPI_SI_R AV3 SPI0_MISO GPP_C1/SMBDATA R10 SMB_ALERT#
SPI0_MOSI GPP_C2/SMBALERT#

3
4

4
3
SPI_WP#_R AW2
SPI_SO RC53 1 2 15_0402_5% SPI_SO_R SPI_HOLD#_R AU4 SPI0_IO2 R9 SML0_CLK RPC20 RPC24
44 SPI_SO SPI0_IO3 GPP_C3/SML0CLK

2
SPI_SO_1 RC177 1 @ 2 33_0402_5% SPI_CS0#_R AU3 W2 SML0_DATA 2.2K_0404_4P2R_5% 2.2K_0404_4P2R_5%

G
D SPI_CS1#_R AU2 SPI0_CS0# GPP_C4/SML0DATA W1 SML0_ALERT# D
AU1 SPI0_CS1# GPP_C5/SML0ALERT#

2
1

1
2
SPI0_CS2# W3 PCH_SML1_CLK
SPI_SI RC52 1 2 15_0402_5% SPI_SI_R GPP_C6/SML1CLK V3 PCH_SML1_DAT PCH_SMB_CLK QC2A 6 1
GPU, EC, Thermal Sensor

S
44 SPI_SI SPI_SI_1 SPI - TOUCH GPP_C7/SML1DATA SML1_ALERT# SMB_CLK_S3 18,40
RC175 1 @ 2 33_0402_5% AM7

D
M2 GPP_B23/SML1ALERT#/PCHHOT# 2N7002KDWH_SOT363-6
GPP_D1/SPI1_CLK

5
M3

G
J4 GPP_D2/SPI1_MISO
SPI_CS0# RC51 1 @ 2 0_0402_5% SPI_CS0#_R V1 GPP_D3/SPI1_MOSI
44 SPI_CS0# SPI_CS1# SPI_CS1#_R GPP_D21/SPI1_IO2
RC174 1 @ 2 0_0402_5% V2
BOARD_ID4 M1 GPP_D22/SPI1_IO3 AY13 PCH_SMB_DATA QC2B 3 4
LPC

S
8 BOARD_ID4 GPP_D0/SPI1_CS# GPP_A1/LAD0/ESPI_IO0 LPC_AD0 32,44 SMB_DATA_S3 18,40
BA13

D
GPP_A2/LAD1/ESPI_IO1 LPC_AD1 32,44
BB13 2N7002KDWH_SOT363-6
C LINK GPP_A3/LAD2/ESPI_IO2 LPC_AD2 32,44
AY12
GPP_A4/LAD3/ESPI_IO3 LPC_AD3 32,44
G3 BA12
CL_CLK GPP_A5/LFRAME#/ESPI_CS# SUS_STAT# LPC_FRAME# 32,44
G2 BA11 1
G1 CL_DATA GPP_A14/SUS_STAT#/ESPI_RESET# TC81@
CL_RST#
AW9 CLK_PCI_EC_R RC173 2 1 22_0402_5%
+3V_SPI GPP_A9/CLKOUT_LPC0/ESPI_CLK CLK_PCI_TPM_R CLK_PCI_EC 44
KBRST# AW13 AY9 RC1541 2 TPM@ 1 22_0402_5%
44 KBRST# GPP_A0/RCIN# GPP_A10/CLKOUT_LPC1 PM_CLKRUN# CLK_PCI_TPM 32
AW11
GPP_A8/CLKRUN# PM_CLKRUN# 32 +3VALW_PCH
SERIRQ AY11
32,44 SERIRQ GPP_A6/SERIRQ

1 OF 20
1

SMB_ALERT# 2 1 RC1562
SKYLAKE-U_BGA1356
RC60 RC61 REV = 1 2.2K_0402_5%
?
1K_0402_5% 1K_0402_5%
Check with BIOS, SPI is Dual mode or quad mode @
2

SPI_WP#_R RC54 1 @ 2 15_0402_5% SPI_WP#

+3VALW_PCH
C +3V_SPI check CLKRUN# / SUS_STAT# signal if need to connect +3VS C
SPI_HOLD#_R RC55 1 @ 2 15_0402_5% SPI_HOLD# RPC23
+3VS +3VALW_PCH SML0_CLK 4 1
SML0_DATA 3 2
RC171 1 @ 2 0_0402_5% PM_CLKRUN# RC11 1 2 8.2K_0402_5%
2.2K_0404_4P2R_5%
RC172 1 @ 2 0_0402_5%
SERIRQ RC12 1 2 10K_0402_5%
+3V_SPI +3V_SPI
* +3VALW_PCH
1. If support DS3, connect to +3VS and don't support EC mirror code; KBRST# RC10 1 2 10K_0402_5%
2. If don't support DS3, connect to +3VALW_PCH and support EC mirror code.
1

SML0_ALERT# RC1564 2 @ 1 2.2K_0402_5%

RC179 RC180
1K_0402_5% 1K_0402_5% KBRST# CC1255 1 2 1000P_0201_50V7-K
@ @ This signal has a weak internal pull-down.
EMC_NS@ 0 = LPC Is selected for EC. (Default)
2

SPI_WP#_R RC176 1 @ 2 33_0402_5% SPI_WP#_1 1 = eSPI Is selected for EC.

Notes:
1. The internal pull-down is disabled after RSMRST#
SPI_HOLD#_R RC178 1 @ 2 33_0402_5% SPI_HOLD#_1 de-asserts.
2. This signal is in the primary wel
+3V_SPI Rising edge of RSMRST#
+3VALW_PCH
UC3
SPI_CS0# 1 8
CS# VCC SML1_ALERT# RC1569 1 2 150K_0402_5%
SPI_SO 2 7 SPI_HOLD# 1
DO HOLD# CC8
+3VALW_PCH Follow CRB, need to check the strap ? SPI_WP# 3 6 SPI_CLK 0.1u_0201_10V6K
B WP# CLK B
4 5 SPI_SI 2
RC1568 2 @ 1 20K_0402_5% SPI_SO_R GND DI +3VALW_PCH +3VS To enable Direct Connect Interface (DCI), a 150K pull up resistor will need to be
added to PCHHOT# pin. This pin must be low during the rising edge of RSMRST#.
RC1565 2 @ 1 20K_0402_5% SPI_SI_R W25Q64FVSSIQ_SO8 (Refer to WW52_MOW)
RC1578 2 @ 1 20K_0402_5% SPI_WP#_R

4
3
RC1580 2 @ 1 20K_0402_5% SPI_HOLD#_R RPC25

2
+3V_SPI 2.2K_0404_4P2R_5%

G
UC6

1
2
SPI_CS1# 1 8
SPI_SO_1 2 CS# VCC 7 SPI_HOLD#_1 PCH_SML1_CLK QC10A 6 1 @

S
SPI_WP#_1 DO HOLD# SPI_CLK_1 EC_SMB_CK2 20,39,44
3 6

D
WP# CLK 1
Follow CRB, need to check the strap ? 4 5 SPI_SI_1 CC97 2N7002KDWH_SOT363-6
GND DI

5
0.1u_0201_10V6K

G
W25Q32FVSSIQ_SO8 @
RC1567 2 @ 1 4.7K_0402_5% SPI_SO_R @ 2

RC1566 2 @ 1 4.7K_0402_5% SPI_SI_R PCH_SML1_DAT QC10B 3 4 @

S
EC_SMB_DA2 20,39,44

D
RC1581 2 @ 1 4.7K_0402_5% SPI_WP#_R 2N7002KDWH_SOT363-6

RC64 1 ES@ 2 1K_0402_5% SPI_HOLD#_R

Based on WW36 SKL U&Y WOM, RC64 populated,

and RC61 de-populated for SKL U ES sample.
In this case, customers must ensure that the
A SPI flash device on the platform A
has HOLD functionality disabled by default.

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (MISC,JTAG,SPI,LPC,SMB)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG411
Date: Thursday, January 14, 2016 Sheet 7 of 60
5 4 3 2 1
 5 4 3 2 1

+3VS

+3VS

DUALRANK@ DUALMIC@
PXS_PWREN_R SKL_ULT ?
RC1559 2 OPT@ 1 10K_0402_5% UC1F

1 RC1615 2

1 RC1613 2

1 RC1611 2

1 RC1609 2

1 RC1606 2
10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%
17@ 15@ TS@ OPT@
PXS_RST#_R LPSS ISH

RC1608
RC1641 1 @ 2 10K_0402_5%

Reserve for GPU sequence AN8 P2 BOARD_ID0

AP7 GPP_B15/GSPI0_CS# GPP_D9 P3 BOARD_ID1

1
RC1629 1 @ 2 10K_0402_5% FB_GC6_EN_R AP8 GPP_B16/GSPI0_CLK GPP_D10 P4
RC1561 1 @ 2 2.2K_0402_5% GPP_B18 AR7 GPP_B17/GSPI0_MISO GPP_D11 P1 BOARD_ID3 BOARD_ID0
+3VS GPP_B18/GSPI0_MOSI GPP_D12
RC1630 1 GC6@ 2 10K_0402_5% GPU_EVENT# BOARD_ID1
AM5 M4 BOARD_ID6 BOARD_ID2
D
PCH_CMOS_ON# AN7 GPP_B19/GSPI1_CS# GPP_D5/ISH_I2C0_SDA BOARD_ID5 9 BOARD_ID2 BOARD_ID3 D
N3
33 PCH_CMOS_ON# GPP_B20/GSPI1_CLK GPP_D6/ISH_I2C0_SCL BOARD_ID4
AP5
FB_GC6_EN_R GPP_B22 GPP_B21/GSPI1_MISO BOARD_ID7 7 BOARD_ID4 BOARD_ID5
RC1637 1 OPT@ 2 10K_0402_5% RC1563 1 @ 2 2.2K_0402_5% AN5 N1
GPP_B22/GSPI1_MOSI GPP_D7/ISH_I2C1_SDA N2 BOARD_ID8
RC1638 1 @ 2 10K_0402_5% GPU_EVENT# AB1 GPP_D8/ISH_I2C1_SCL
40 UART_RX_DEBUG GPP_C8/UART0_RXD

10K_0402_5%
AB2 AD11 SINGLERANK@
SINGLEMIC@
40 UART_TX_DEBUG GPP_C9/UART0_TXD GPP_F10/I2C5_SDA/ISH_I2C2_SDA

1 RC1616 2

1 RC1614 2

1 RC1612 2

1 RC1610 2

1 RC1607 2

1 RC123 2
Reserve for NV GPU

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%
W4 AD12 14or15@ 14or17@ NTS@ UMA@
AB3 GPP_C10/UART0_RTS# GPP_F11/I2C5_SCL/ISH_I2C2_SCL
RC1557 1 OPT@ 2 10K_0402_5% PXS_RST#_R GPP_C11/UART0_CTS#
RC7 1 OPT@ 2 1K_0402_5% PXS_PWREN_R AD1 U1
DGPU_PWROK 22,58 PXS_PWREN PXS_RST#_R GPP_C20/UART2_RXD GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA
RC1558 1 UMA@ 2 10K_0402_5% RC8 1 @ 2 0_0402_5% AD2 U2
20 PXS_RST# DGPU_PWROK GPP_C21/UART2_TXD GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL
AD3 U3
PXS_RST# 24,57,58 DGPU_PWROK FB_GC6_EN_R GPP_C22/UART2_RTS# GPP_D15/ISH_UART0_RTS#
CC1259 1 2 0.01U_0201_10V6K AD4 U4
20 FB_GC6_EN_R GPP_C23/UART2_CTS# GPP_D16/ISH_UART0_CTS#/SML0BALERT#
AC1
U7 GPP_C12/UART1_RXD/ISH_UART1_RXD AC2
3D_FR U6 GPP_C16/I2C0_SDA GPP_C13/UART1_TXD/ISH_UART1_TXD AC3 GPU_EVENT#
31 3D_FR GPP_C17/I2C0_SCL GPP_C14/UART1_RTS#/ISH_UART1_RTS# GPU_EVENT# 20
AB4
PCH_WLAN_OFF# U8 GPP_C15/UART1_CTS#/ISH_UART1_CTS#
40 PCH_WLAN_OFF# PCH_BT_OFF# GPP_C18/I2C1_SDA
U9 AY8
40 PCH_BT_OFF# GPP_C19/I2C1_SCL GPP_A18/ISH_GP0 BA8 Board ID Description Stuff R
AH9 GPP_A19/ISH_GP1 BB7
AH10 GPP_F4/I2C2_SDA GPP_A20/ISH_GP2 BA7
GPP_F5/I2C2_SCL GPP_A21/ISH_GP3
00 14" RC1616 RC1614
AY7
AH11 GPP_A22/ISH_GP4 AW7
GPP_F6/I2C3_SDA GPP_A23/ISH_GP5
Board_ID[0:1] 01 15" RC1616 RC1613
+3VS AH12 AP13
GPP_F7/I2C3_SCL GPP_A12/BM_BUSY#/ISH_GP6
10 17" RC1615 RC1614
AF11
AF12 GPP_F8/I2C4_SDA
GPP_F9/I2C4_SCL
11 Reserved

1 OF 20
Board_ID2 0 Non-touch RC1612
RC1595 2 @ 1 10K_0402_5% PCH_CMOS_ON# SKYLAKE-U_BGA1356
RC1596 2 1 10K_0402_5% PCH_WLAN_OFF# REV = 1 ? 1 Touch RC1611
C RC1597 2 1 10K_0402_5% PCH_BT_OFF# @ C
UC1G SKL_ULT ? Board_ID3 0 UMA RC1610
double check if need the pull up resisor
AUDIO 1 DIS RC1609
RC43 1 2 33_0402_5% HDA_SYNC BA22 Board_ID4 0 SingleRankRC1607
43 HDA_SYNC_AUDIO HDA_BCLK HDA_SYNC/I2S0_SFRM
RC42 1 2 33_0402_5% AY22
+3VALW_PCH +3VS 43 HDA_BITCLK_AUDIO HDA_SDOUT HDA_BLK/I2S0_SCLK
BB22 SDIO/SDXC 1 DualRank RC1608
HDA_SDIN0 BA21 HDA_SDO/I2S0_TXD
43 HDA_SDIN0 HDA_SDI0/I2S0_RXD
RC1600 1 @ 2 1K_0402_5% AY21 AB11 Board_ID5 0 SingleMIC RC123
RC44 1 2 33_0402_5% HDA_RST# AW22 HDA_SDI1/I2S1_RXD GPP_G0/SD_CMD AB13
HDA_SDOUT 43 HDA_RST_AUDIO# HDA_RST#/I2S1_SCLK GPP_G1/SD_DATA0
RC47 1 @ 2 1K_0402_5% J5 AB12 1 DualMIC RC1606
AY20 GPP_D23/I2S_MCLK GPP_G2/SD_DATA1 W12
* AW20 I2S1_SFRM
I2S1_TXD
GPP_G3/SD_DATA2
GPP_G4/SD_DATA3
W11
HDA_SDO This signal has a weak internal pull-down. W10 +3VS
AK7 GPP_G5/SD_CD# W8
0 = Enable security measures defined in the Flash Descriptor. GPP_F1/I2S2_SFRM GPP_G6/SD_CLK
AK6 W7
1 = Disable Flash Descriptor Security(override). This strap AK9 GPP_F0/I2S2_SCLK GPP_G7/SD_WP
should only be asserted high during external pull-up in AK10 GPP_F2/I2S2_TXD BA9
manufacturing/debug environments ONLY. GPP_F3/I2S2_RXD GPP_A17/SD_PWR_EN#/ISH_GP7 BB9 510Z@
GPP_A16/SD_1P8_SEL

2 RC1631 1

2 RC1632 1

2 RC1633 1

2 RC1639 1
10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%
H5 AB7 SD_RCOMP
BOARD_ID9 D7 GPP_D19/DMIC_CLK0 SD_RCOMP @ @ @
GPP_D20/DMIC_DATA0

1
For EMI D8 AF13
HDA_SDIN0 C8 GPP_D17/DMIC_CLK1 GPP_F23 RC49
GPP_D18/DMIC_DATA1 200_0402_1% BOARD_ID6
PCH_BEEP AW5 BOARD_ID7
43 PCH_BEEP GPP_B14/SPKR BOARD_ID8
1

2
CC7 BOARD_ID9
10P_0201_50V8F
EMC_NS@ SKYLAKE-U_BGA1356 1 OF 20 310G@

2 RC1634 1

2 RC1635 1

2 RC1636 1

2 RC1640 1
2

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%
REV = 1 ?
B @ B
@ @ @

+3VS
RC45 1 2 33_0402_5% HDA_SDOUT
43 HDA_SDOUT_AUDIO
RC46 1 @ 2 0_0402_5%
44 ME_FLASH PCH_BEEP
RC14 1 @ 2 2.2K_0402_5%

Board ID Description Stuff R

Default When 00 Samsung 8Gb RC1634 RC1635

Pin Name Strap Description Configuration Value Sampled
Internal PD 01 Hynix 8Gb RC1634 RC1632
0 = Disable “ Top Swap” Board_ID[6:7]
SPKR / Top Swap 0 Rising edge
GPP_B14 Override
mode. (Default)
1 = Enable “ Top Swap”
* of PCH_PWROK 10 Micron 8Gb RC1631 RC1635
mode.
11 Reserved RC1631 RC1632
Internal PD
0 = Disable “ No Reboot”
GSPI0_MOSINo Reboot 0 310G RC1636
/GPP_B18
mode. (Default) *
1 = Enable “ No Reboot” 0 Rising edge Board_ID8
mode of PCH_PWROK
1 510Z RC1633
A A
0 Reserved
Internal PD BOARD_ID9
0 = SPI (Default)
GSPI1_MOSIBoot BIOS Rising edge 1 Reserved
/GPP_B22 Strap Bit
1 = LPC * 0 of PCH_PWROK
BBS
Security Classification LC Future Center Secret Data Title
Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (LPSS,ISH,AUDIO,SDIO)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG411
Date: Thursday, January 14, 2016 Sheet 8 of 60
5 4 3 2 1

WWW.AliSaler.Com
 5 4 3 2 1

D D

SKL_ULT
?
UC1H

SSIC / USB3
PCIE/USB3/SATA
H8 USB30_RX_N1
USB3_1_RXN USB30_RX_P1 USB30_RX_N1 41
G8
H13 USB3_1_RXP C13 USB30_TX_N1 USB30_RX_P1 41 LEFT USB (3.0)
PCIE1_RXN/USB3_5_RXN USB3_1_TXN USB30_TX_P1 USB30_TX_N1 41
G13 D13
PCIE1_RXP/USB3_5_RXP USB3_1_TXP USB30_TX_P1 41
B17
A17 PCIE1_TXN/USB3_5_TXN J6 USB30_RX_N2
PCIE1_TXP/USB3_5_TXP USB3_2_RXN/SSIC_1_RXN USB30_RX_P2 USB30_RX_N2 45
H6
G11 USB3_2_RXP/SSIC_1_RXP B13 USB30_TX_N2 USB30_RX_P2 45 Right USB (3.0) (Optional)
PCIE2_RXN/USB3_6_RXN USB3_2_TXN/SSIC_1_TXN USB30_TX_P2 USB30_TX_N2 45
F11 A13
PCIE2_RXP/USB3_6_RXP USB3_2_TXP/SSIC_1_TXP USB30_TX_P2 45
D16
C16 PCIE2_TXN/USB3_6_TXN J10 USB30_RX_N3
PCIE2_TXP/USB3_6_TXP USB3_3_RXN/SSIC_2_RXN USB30_RX_P3 USB30_RX_N3 31
H10
H16 USB3_3_RXP/SSIC_2_RXP B15 USB30_TX_N3 USB30_RX_P3 31 3D Camera (Optional)
PCIE3_RXN USB3_3_TXN/SSIC_2_TXN USB30_TX_P3 USB30_TX_N3 31
G16 A15
PCIE3_RXP USB3_3_TXP/SSIC_2_TXP USB30_TX_P3 31
D17
C17 PCIE3_TXN E10
PCIE3_TXP USB3_4_RXN F10
G15 USB3_4_RXP C15
F15 PCIE4_RXN USB3_4_TXN D15
B19 PCIE4_RXP USB3_4_TXP
A19 PCIE4_TXN AB9 USB20_N1
PCIE4_TXP USB2N_1 USB20_P1 USB20_N1 41
AB10
PCIE_PRX_DTX_N5 F16 USB2P_1 USB20_P1 41 LEFT USB (3.0)
37 PCIE_PRX_DTX_N5 PCIE5_RXN
PCIE_PRX_DTX_P5 E16 AD6 USB20_N2
37 PCIE_PRX_DTX_P5 PCIE5_RXP USB2N_2 USB20_N2 45
LAN CC22 1 2 0.1u_0201_10V6K PCIE_PTX_DRX_N5 C19 AD7 USB20_P2
37 PCIE_PTX_C_DRX_N5
CC23 1 2 0.1u_0201_10V6K PCIE_PTX_DRX_P5 D19 PCIE5_TXN USB2P_2 USB20_P2 45 RIGHT USB (2.0)
C 37 PCIE_PTX_C_DRX_P5 PCIE5_TXP USB20_N3 C
AH3
PCIE_PRX_DTX_N6 USB2N_3 USB20_P3 USB20_N3 45
G18 AJ3
40 PCIE_PRX_DTX_N6
PCIE_PRX_DTX_P6 F18 PCIE6_RXN USB2P_3 USB20_P3 45 RIGHT USB (2.0)
40 PCIE_PRX_DTX_P6 PCIE6_RXP
WLAN CC24 1 2 0.1u_0201_10V6K PCIE_PTX_DRX_N6 D20 AD9 USB20_N4
40 PCIE_PTX_C_DRX_N6 PCIE6_TXN USB2N_4 USB20_N4 33
CC25 1 2 0.1u_0201_10V6K PCIE_PTX_DRX_P6 C20 AD10 USB20_P4
40 PCIE_PTX_C_DRX_P6 PCIE6_TXP USB2P_4 USB20_P4 33 Camera
SATA_PRX_DTX_N0 F20 AJ1 USB20_N5
42 SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 PCIE7_RXN/SATA0_RXN USB2N_5 USB20_P5 USB20_N5 30
E20 AJ2
SATA HDD 42 SATA_PRX_DTX_P0 SATA_PTX_DRX_N0 B21 PCIE7_RXP/SATA0_RXP
USB2
USB2P_5 USB20_P5 30 Card reader
42 SATA_PTX_DRX_N0 SATA_PTX_DRX_P0 A21 PCIE7_TXN/SATA0_TXN AF6 USB20_N6
42 SATA_PTX_DRX_P0 PCIE7_TXP/SATA0_TXP USB2N_6 USB20_P6 USB20_N6 33
AF7
SATA_PRX_DTX_N1 G21 USB2P_6 USB20_P6 33 Touch panel
42 SATA_PRX_DTX_N1 SATA_PRX_DTX_P1 F21 PCIE8_RXN/SATA1A_RXN AH1 USB20_N7
42 SATA_PRX_DTX_P1 SATA_PTX_DRX_N1 PCIE8_RXP/SATA1A_RXP USB2N_7 USB20_P7 USB20_N7 40
SATA ODD D21 AH2
42 SATA_PTX_DRX_N1 SATA_PTX_DRX_P1 C21 PCIE8_TXN/SATA1A_TXN USB2P_7 USB20_P7 40 BT
42 SATA_PTX_DRX_P1 PCIE8_TXP/SATA1A_TXP AF8
PCIE_CRX_GTX_N0 E22 USB2N_8 AF9
PCIE_CRX_GTX_P0 E23 PCIE9_RXN USB2P_8
PCIE_CTX_C_GRX_N0 0.22U_0201_6.3V6-K OPT@1 2 CC16 PCIE_CTX_GRX_N0 B23 PCIE9_RXP AG1
PCIE_CTX_C_GRX_P0 0.22U_0201_6.3V6-K OPT@1 2 CC14 PCIE_CTX_GRX_P0 A23 PCIE9_TXN USB2N_9 AG2
PCIE9_TXP USB2P_9
PCIE_CRX_GTX_N1 F25 AH7
PCIE_CRX_GTX_P1 E25 PCIE10_RXN USB2N_10 AH8
PCIE_CTX_C_GRX_N1 0.22U_0201_6.3V6-K OPT@1 2 CC15 PCIE_CTX_GRX_N1 D23 PCIE10_RXP USB2P_10
PCIE_CTX_C_GRX_P1 0.22U_0201_6.3V6-K OPT@1 2 CC17 PCIE_CTX_GRX_P1 C23 PCIE10_TXN AB6 USB2_COMP RC118 2 1 113_0402_1%
PCIE10_TXP USB2_COMP USBRBIAS
AG3 USB2_ID RC1626 1 @ 2 0_0402_5% Width 20Mil
RC119 1 2 100_0402_1% PCIE_RCOMPN F5 USB2_ID AG4 USB2_VBUSSENSE RC1627 1 2 1K_0402_5%
PCIE_RCOMPN USB2_VBUSSENSE Space 15Mil
PCIE_RCOMPP E5
PCIE_RCOMPP A9 USB_OC0#
Length 500Mil
PCIE_RCOMPN and PCIE_RCOMPP PAD @ TC20 1 XDP_PRDY# D56 GPP_E9/USB2_OC0# C9 USB_OC1#
Trace Width: 12-15mil XDP_PREQ# PROC_PRDY# GPP_E10/USB2_OC1# USB_OC2# USB_OC1# 41
DGPU PAD @ TC19 1 D61 D9
Differential between RCOMPP/RCOMPN PROC_PREQ# GPP_E11/USB2_OC2# USB_OC3# USB_OC2# 45
PIRQA# BB11 B9
B GPP_A7/PIRQA# GPP_E12/USB2_OC3# B
PCIE_CRX_GTX_N2 E28 J1 GPP_E4 RC1628 1 @ 2 0_0402_5%
PCIE_CRX_GTX_P2 PCIE11_RXN/SATA1B_RXN GPP_E4/DEVSLP0 GPP_E5 EC_SMI# 44
E27 J2 1
PCIE_CTX_C_GRX_N2 0.22U_0201_6.3V6-K OPT@1 2 CC18 PCIE_CTX_GRX_N2 D24 PCIE11_RXP/SATA1B_RXP GPP_E5/DEVSLP1 J3 @ PAD TC202
PCIE_CTX_C_GRX_P2 0.22U_0201_6.3V6-K OPT@1 2 CC19 PCIE_CTX_GRX_P2 C24 PCIE11_TXN/SATA1B_TXN GPP_E6/DEVSLP2
PCIE_CRX_GTX_N3 E30 PCIE11_TXP/SATA1B_TXP H2 SATA0GP
PCIE_CRX_GTX_P3 F30 PCIE12_RXN/SATA2_RXN GPP_E0/SATAXPCIE0/SATAGP0 H3 ODD_DETECT#
PCIE_CTX_C_GRX_N3 0.22U_0201_6.3V6-K OPT@1 2 CC20 PCIE_CTX_GRX_N3 A25 PCIE12_RXP/SATA2_RXP GPP_E1/SATAXPCIE1/SATAGP1 G4 SATA2GP
PCIE_CTX_C_GRX_P3 0.22U_0201_6.3V6-K OPT@1 2 CC21 PCIE_CTX_GRX_P3 B25 PCIE12_TXN/SATA2_TXN GPP_E2/SATAXPCIE2/SATAGP2
PCIE12_TXP/SATA2_TXP H1 BOARD_ID2
GPP_E8/SATALED# BOARD_ID2 8

SKYLAKE-U_BGA1356 1 OF 20 +3VS
REV = 1 ?
@

GPP_E4 RC1617 2 @ 1 10K_0402_5%

+3VALW_PCH

20 PCIE_CRX_GTX_N[0..3] +3VS
RPC2 RPC17
1 8 ODD_DETECT# USB_OC0# 8 1
20 PCIE_CRX_GTX_P[0..3]
2 7 SATA0GP USB_OC1# 7 2
3 6 SATA2GP USB_OC3# 6 3
20 PCIE_CTX_C_GRX_N[0..3] USB_OC2#
4 5 PIRQA# 5 4
20 PCIE_CTX_C_GRX_P[0..3]
10K_0804_8P4R_5% 10K_0804_8P4R_5%

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (PCIE,SATA,USB3,USB2)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG411
Date: Thursday, January 14, 2016 Sheet 9 of 60
5 4 3 2 1
 5 4 3 2 1

UC1I
SKL_ULT ?

CSI-2

A36 C37
B36 CSI2_DN0 CSI2_CLKN0 D37
C38 CSI2_DP0 CSI2_CLKP0 C32
D38 CSI2_DN1 CSI2_CLKN1 D32
C36 CSI2_DP1 CSI2_CLKP1 C29
D D36 CSI2_DN2 CSI2_CLKN2 D29 D
A38 CSI2_DP2 CSI2_CLKP2 B26
B38 CSI2_DN3 CSI2_CLKN3 A26
CSI2_DP3 CSI2_CLKP3
C31 E13 CSI2_COMP RC73 1 2 100_0402_1%
D31 CSI2_DN4 CSI2_COMP B7
C33 CSI2_DP4 GPP_D4/FLASHTRIG
D33 CSI2_DN5
A31 CSI2_DP5 EMMC

B31 CSI2_DN6 AP2

A33 CSI2_DP6 GPP_F13/EMMC_DATA0 AP1
B33 CSI2_DN7 GPP_F14/EMMC_DATA1 AP3
CSI2_DP7 GPP_F15/EMMC_DATA2 AN3
A29 GPP_F16/EMMC_DATA3 AN1
B29 CSI2_DN8 GPP_F17/EMMC_DATA4 AN2
check the Pull up resistor CSI2_DP8 GPP_F18/EMMC_DATA5
C28 AM4
D28 CSI2_DN9 GPP_F19/EMMC_DATA6 AM1
+3VS A27 CSI2_DP9 GPP_F20/EMMC_DATA7
B27 CSI2_DN10 AM2
C27 CSI2_DP10 GPP_F21/EMMC_RCLK AM3
RPC4 D27 CSI2_DN11 GPP_F22/EMMC_CLK AP4
1 8 GPU_CLKREQ# CSI2_DP11 GPP_F12/EMMC_CMD
2 7 LAN_CLKREQ# AT1 EMMC_RCOMP RC50 1 2 200_0402_1%
3 6 EMMC_RCOMP
4 5 WLAN_CLKREQ# SKYLAKE-U_BGA1356 1 OF 20
REV = 1 ?
10K_0804_8P4R_5% @

UC1J SKL_ULT ?

C CLOCK SIGNALS C

CLK_PCIE_GPU# D42
20 CLK_PCIE_GPU# CLK_PCIE_GPU CLKOUT_PCIE_N0
PCIE CLK0 DGPU C42
20 CLK_PCIE_GPU GPU_CLKREQ# CLKOUT_PCIE_P0
AR10
20 GPU_CLKREQ# GPP_B5/SRCCLKREQ0#
B42
A42 CLKOUT_PCIE_N1 F43 CLK_PCIE_XDP# 1 TC85 @
AT7 CLKOUT_PCIE_P1 CLKOUT_ITPXDP_N E43 CLK_PCIE_XDP 1 TC87 @ SUSCLK RC95 1 @ 2 1K_0402_5%
GPP_B6/SRCCLKREQ1# CLKOUT_ITPXDP_P
D41 BA17 SUSCLK
CLKOUT_PCIE_N2 GPD8/SUSCLK SUSCLK 40 DIFFCLK_BIASREF RC1555 1
C41 2 60.4_0402_1%
AT8 CLKOUT_PCIE_P2 E37 XTAL24_IN Cannonlake@
GPP_B7/SRCCLKREQ2# XTAL24_IN E35 XTAL24_OUT +VCCCLK5
D40 XTAL24_OUT
C40 CLKOUT_PCIE_N3 E42 DIFFCLK_BIASREF RC72 1 2 2.7K_0402_1%
AT10 CLKOUT_PCIE_P3 XCLK_BIASREF
GPP_B8/SRCCLKREQ3# AM18 RTC_X1
CLK_PCIE_LAN# B40 RTCX1 AM20 RTC_X2
37 CLK_PCIE_LAN# CLK_PCIE_LAN CLKOUT_PCIE_N4 RTCX2
PCIE CLK4 LAN A40
37 CLK_PCIE_LAN LAN_CLKREQ# CLKOUT_PCIE_P4 SRTC_RST#
AU8 AN18
37 LAN_CLKREQ# GPP_B9/SRCCLKREQ4# SRTCRST# RTC_RST#
AM16
CLK_PCIE_WLAN# E40 RTCRST#
40 CLK_PCIE_WLAN# CLK_PCIE_WLAN CLKOUT_PCIE_N5
PCIE CLK5 WLAN E38
40 CLK_PCIE_WLAN WLAN_CLKREQ# CLKOUT_PCIE_P5
AU7
40 WLAN_CLKREQ# GPP_B10/SRCCLKREQ5#
1
CC3
VCCRTC 1U_0402_6.3V6K
SKYLAKE-U_BGA1356 1 OF 20
REV = 1 ? 2
@ RC33 1 2 20K_0402_1% SRTC_RST#
B RC34 1 2 20K_0402_1% RTC_RST# RC1624 1 @ 2 0_0402_5% B
EC_RTC_RST# 44
1

1
CC6 JCMOS1
1U_0402_6.3V6K SHORT PADS
@

2
2

RC71 2 1 1M_0402_5% RTC_X1

YC2
RC32 2 1 10M_0402_5% RTC_X2
2 3 XTAL24_OUT
GND1 OSC2 YC1
XTAL24_IN 1 4 1 2
OSC1 GND2
2 32.768KHZ_9PF_X1A0001410002 2
1 24MHZ_6PF_7V24000032 1
CC12 CC11 CC4 CC5
3.3P_0402_50V8-C 3.3P_0402_50V8-C 7P_0402_50V8J 7P_0402_50V8J
1 1
2 2 when single end external clock generator used,
this pin should be grounded

need to use 38.4MHz (30ohm) for Cannonlake-u

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (CSI2,EMMC,CLOCK)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG411
WWW.AliSaler.Com 5 4 3 2
Date: Thursday, January 14, 2016
1
Sheet 10 of 60
 5 4 3 2 1

SKL_ULT
?
UC1K
SYSTEM POWER MANAGEMENT
AT11
GPP_B12/SLP_S0# AP15 PM_SLP_S3#_R RC96 1 @ 2 0_0402_5%
PLT_RST#_R GPD4/SLP_S3# PM_SLP_S4#_R PM_SLP_S3# 13,44
RC84 1 @ 2 0_0402_5% AN10 BA16 RC97 1 @ 2 0_0402_5%
20,32,37,40,44 PLT_RST# SYS_RESET# GPP_B13/PLTRST# GPD5/SLP_S4# PM_SLP_S4# 44
B5 AY16
D RC85 1 @ 2 0_0402_5% PCH_RSMRST#_R AY17 SYS_RESET# GPD10/SLP_S5# D
44 EC_RSMRST# RSMRST# PM_SLP_SUS#_R
PAD @ TC21 AN15 RC89 1 @ 2 0_0402_5%
CPU_PROCPWRGD SLP_SUS# PM_SLP_SUS# 44
1 A68 AW15
VCCST_PWRGD_R RC93 1 2 60.4_0402_1% VCCST_PWRGD B65 PROCPWRGD SLP_LAN# BB17 Reserve for DS3
VCCST_PWRGD GPD9/SLP_WLAN# AN16
RC139 1 @ 2 0_0402_5% SYS_PWROK_R B6 GPD6/SLP_A#
44 SYS_PWROK PCH_PWROK_R SYS_PWROK PBTN_OUT#_R PBTN_OUT# 44
RC126 1 @ 2 0_0402_5% BA20 BA15 RC87 1 @ 2 0_0402_5%
44 PCH_PWROK PCH_DPWROK_R PCH_PWROK GPD3/PWRBTN# AC_PRESENT_R
BB20 AY15
DSW_PWROK GPD1/ACPRESENT AU13 BATLOW#
RC86 1 @ 2 0_0402_5% SUSWARN#_R AR13 GPD0/BATLOW#
44 SUSWARN# SUSACK#_R GPP_A13/SUSWARN#/SUSPWRDNACK
RC79 1 @ 2 0_0402_5% AP11 VCCRTC
44 SUSACK# GPP_A15/SUSACK#
Reserve for DS3 AU11 PME# @1 TC89
RC91 1 @ 2 0_0402_5% WAKE# BB15 GPP_A11/PME# AP16 INTVRMEN RC41 2 1 330K_0402_5%
37,40,44 PCIE_WAKE# PCH_LAN_WAKE# AM15 WAKE# INTRUDER#
AW17 GPD2/LAN_WAKE# AM10
AT15 GPD11/LANPHYPC GPP_B11/EXT_PWR_GATE# AM11
GPD7/RSVD GPP_B2/VRALERT#

SKYLAKE-U_BGA1356 1 OF 20
REV = 1 ?
@

+3VALW

RC74 1 2 10K_0402_5% AC_PRESENT_R

RC88 1 @ 2 0_0402_5% AC_PRESENT_R
44 AC_PRESENT
RC75 1 2 8.2K_0402_5% BATLOW#

RC76 2 1 1K_0402_5% WAKE# Follow CRB change to 1kohm

1
RC90 1 2 10K_0402_5% PCH_LAN_WAKE# D
C 2 QC8 C
44 ACIN# G 2N7002KW_SOT323-3
@
+3VALW_PCH S

3
RC78 1 @ 2 10K_0402_5% SUSWARN#_R
+VCCST_CPU +VCCSTG

+3VS

2
+3VALW RC137 RC1554
RC80 1 2 10K_0402_5% SYS_RESET# 1K_0402_5% 1K_0402_5%
@

1
RC136
10K_0402_5% VCCST_PWRGD_R
@

3
1000P_0201_50V7-K 1 2 CC1254 PCH_RSMRST#_R D

1
EMC_NS@ 5 QC6B 2
Stuff to fix Reset&PWRGD test fail issue G 2N7002KDWH_SOT363-6 CC140
0.01U_0201_10V6K 1 2 CC104 PCH_PWROK @ 1000P_0201_50V7-K

6
D S EMC_NS@

4
RC138 1 @ 2 0_0402_5% 2 QC6A 1
PCH_DPWROK_R 44 EC_VCCST_PWRGD
1000P_0201_50V7-K 1 2 CC103 G 2N7002KDWH_SOT363-6
EMC_NS@ 1 @
CC46 S

1
47P_0201_25V8-J 1 2 CC101 SYS_PWROK 0.01U_0201_25V6-K
EMC_NS@
2
B 0.01U_0201_10V6K 1 2 CC1260 EC_RSMRST# B

Add to fix Reset&PWRGD test fail issue

RPC21 RC1599 1 @ 2 0_0402_5%

1 8 PCH_RSMRST#_R
2 7 PCH_PWROK
3 6 SYS_PWROK
4 5 PM_SLP_S3# DC4 1 2 @

10K_0804_8P4R_5% RB751V-40_SOD323-2

RC182 1 @ 2 0_0402_5% EC_RSMRST#

100K_0402_5% 2 1 RC92 PLT_RST#_R

100K_0402_1% 2 @ 1 RC94 PCH_DPWROK_R PCH_DPWROK_R RC81 1 @ 2 0_0402_5% DPWROK_EC 44

Reserve for DS3

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (SYSTEM PWR MANAGEMENT)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG411
Date: Thursday, January 14, 2016 Sheet 11 of 60
5 4 3 2 1
 5 4 3 2 1

+CPU_CORE ? +CPU_CORE +CPU_CORE +VCC_GT +VCC_GT

SKL_ULT SKL_ULT ?
UC1L +VCC_GT UC1M
CPU POWER 1 OF 4
VCORE_VCC_SEN RC77 1 2 100_0402_1% VCCGT_VCC_SEN RC83 1 2 100_0402_1% CPU POWER 2 OF 4
A30 G32 N70
A34 VCC_A30 VCC_G32 G33 A48 VCCGT_N70 N71
A39 VCC_A34 VCC_G33 G35 VCORE_VSS_SEN RC82 1 2 100_0402_1% VCCGT_VSS_SEN RC98 1 2 100_0402_1% A53 VCCGT_A48 VCCGT_N71 R63
A44 VCC_A39 VCC_G35 G37 A58 VCCGT_A53 VCCGT_R63 R64
AK33 VCC_A44 VCC_G37 G38 A62 VCCGT_A58 VCCGT_R64 R65
AK35 VCC_AK33 VCC_G38 G40 A66 VCCGT_A62 VCCGT_R65 R66
AK37 VCC_AK35 VCC_G40 G42 AA63 VCCGT_A66 VCCGT_R66 R67
AK38 VCC_AK37 VCC_G42 J30 AA64 VCCGT_AA63 VCCGT_R67 R68
AK40 VCC_AK38 VCC_J30 J33 AA66 VCCGT_AA64 VCCGT_R68 R69
AL33 VCC_AK40 VCC_J33 J37 AA67 VCCGT_AA66 VCCGT_R69 R70
AL37 VCC_AL33 VCC_J37 J40 AA69 VCCGT_AA67 VCCGT_R70 R71
AL40 VCC_AL37 VCC_J40 K33 AA70 VCCGT_AA69 VCCGT_R71 T62
D VCC_AL40 VCC_K33 VCCGT_AA70 VCCGT_T62 D
AM32 K35 SVID +VCCST_CPU AA71 U65
AM33 VCC_AM32 VCC_K35 K37 AC64 VCCGT_AA71 VCCGT_U65 U68
AM35 VCC_AM33 VCC_K37 K38 AC65 VCCGT_AC64 VCCGT_U68 U71
AM37 VCC_AM35 VCC_K38 K40 AC66 VCCGT_AC65 VCCGT_U71 W63
AM38 VCC_AM37 VCC_K40 K42 AC67 VCCGT_AC66 VCCGT_W63 W64
G30 VCC_AM38 VCC_K42 K43 AC68 VCCGT_AC67 VCCGT_W64 W65
VCC_G30 VCC_K43 AC69 VCCGT_AC68 VCCGT_W65 W66
1 VCCGT_AC69 VCCGT_W66
@ TC90 1 K32 E32 VCORE_VCC_SEN CC42 AC70 W67
RSVD_K32 VCC_SENSE VCORE_VSS_SEN VCORE_VCC_SEN 59 0.1u_0201_10V6K VCCGT_AC70 VCCGT_W67
E33 AC71 W68
VSS_SENSE VCORE_VSS_SEN 59 VCCGT_AC71 VCCGT_W68

1
56_0402_5%

100_0402_1%

100_0402_1%
AK32 @ J43 W69
RSVD_AK32 CPU_SVID_ALERT#_R 2 VCCGT_J43 VCCGT_W69

RC131

RC1544

RC132
B63 J45 W70
AB62 VIDALERT# A63 CPU_SVID_CLK_R J46 VCCGT_J45 VCCGT_W70 W71
P62 VCCOPC_AB62 VIDSCK D64 CPU_SVID_DAT_R J48 VCCGT_J46 VCCGT_W71 Y62
@ TC92 1 +V_EDRAM_VR V62 VCCOPC_P62 VIDSOUT J50 VCCGT_J48 VCCGT_Y62

2
VCCOPC_V62 G20 J52 VCCGT_J50
VCCSTG_G20 +VCCSTG VCCGT_J52
H63 @ J53 AK42 1 TC135 @
VCC_OPC_1P8_H63 J55 VCCGT_J53 VCCGTX_AK42 AK43
@ TC94 1 +V1.8S_EDRAM G61 J56 VCCGT_J55 VCCGTX_AK43 AK45
VCC_OPC_1P8_G61 RC133 1 2 220_0402_1% CPU_SVID_ALERT#_R J58 VCCGT_J56 VCCGTX_AK45 AK46
59 VR_SVID_ALRT# VCCGT_J58 VCCGTX_AK46
@ TC95 1 AC63 J60 AK48
@ TC97 1 AE63 VCCOPC_SENSE K48 VCCGT_J60 VCCGTX_AK48 AK50
VSSOPC_SENSE RC134 1 @ 2 0_0402_5% CPU_SVID_CLK_R K50 VCCGT_K48 VCCGTX_AK50 AK52
59 VR_SVID_CLK VCCGT_K50 VCCGTX_AK52
AE62 K52 AK53
@ TC99 1 +VCCEOPIO AG62 VCCEOPIO_AE62 K53 VCCGT_K52 VCCGTX_AK53 AK55
VCCEOPIO_AG62 RC1545 1 @ 2 0_0402_5% CPU_SVID_DAT_R K55 VCCGT_K53 VCCGTX_AK55 AK56
59 VR_SVID_DAT VCCGT_K55 VCCGTX_AK56
@ TC100 1 AL63 K56 AK58
@ TC101 1 AJ62 VCCEOPIO_SENSE K58 VCCGT_K56 VCCGTX_AK58 AK60
VSSEOPIO_SENSE
1, Alert# Route Between CLK and Data VCCGT_K58 VCCGTX_AK60
K60 AK70
L62 VCCGT_K60 VCCGTX_AK70 AL43
SKYLAKE-U_BGA1356 1 OF 20 L63 VCCGT_L62 VCCGTX_AL43 AL46
REV = 1 ? L64 VCCGT_L63 VCCGTX_AL46 AL50
@ L65 VCCGT_L64 VCCGTX_AL50 AL53
L66 VCCGT_L65 VCCGTX_AL53 AL56
L67 VCCGT_L66 VCCGTX_AL56 AL60
L68 VCCGT_L67 VCCGTX_AL60 AM48
+CPU_CORE L69 VCCGT_L68 VCCGTX_AM48 AM50
+VCC_GT L70 VCCGT_L69 VCCGTX_AM50 AM52
C Backside Cap 8x10uF 0402, SIT update VCCGT_L70 VCCGTX_AM52 C
13x10uF 0402, SIT update to 0603 package L71 AM53
M62 VCCGT_L71 VCCGTX_AM53 AM56
N63 VCCGT_M62 VCCGTX_AM56 AM58
VCCGT_N63 VCCGTX_AM58
10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
N64 AU58
N66 VCCGT_N64 VCCGTX_AU58 AU63
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VCCGT_N66 VCCGTX_AU63
CC1086

CC1085

CC1080

CC1236

CC1237

CC1093

CC1092

CC1091

CC1089

CC1238

CC1122

CC1123

CC1124

CC1125

CC1126

CC1127

CC1128

CC1129
N67 BB57
N69 VCCGT_N67 VCCGTX_BB57 BB66
VCCGT_N69 VCCGTX_BB66
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 VCCGT_VCC_SEN J70 AK62 VCCGTX_SENSE 1 TC133 @
59 VCCGT_VCC_SEN VCCGT_VSS_SEN VCCGT_SENSE VCCGTX_SENSE VSSGTX_SENSE
J69 AL61 1 TC134 @
59 VCCGT_VSS_SEN VSSGT_SENSE VSSGTX_SENSE
@ CD@ @ @ @ @ CD@ CD@

SKYLAKE-U_BGA1356 1 OF 20
REV = 1 ?
@

+CPU_CORE +VCC_GT
15x1uF 0201, SIT update to 0402 package Backside Cap 12x1uF 0201, SIT update
1U_0201_6.3V6-M

1U_0201_6.3V6-M
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CC1095

CC1096

CC1097

CC1098

CC1099

CC1100

CC1101

CC1102

CC1104

CC1105

CC1108

CC1109

CC1111

CC1114

CC1115

CC1116

CC1118

CC1119

CC1240

CC1241
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

@ @

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (CPU PWR1)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG411
Date: Thursday, January 14, 2016 Sheet 12 of 60
5 4 3 2 1

WWW.AliSaler.Com
 5 4 3 2 1

+VCCIO
3.1A 2x10uF, 4x1uF

10U_0402_6.3V6M

10U_0402_6.3V6M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
+VCCIO 1 1 1 1 1 1 1 1 1 1

CC1152

CC1153

CC1158

CC1159

CC1160

CC1161

CC1218

CC1230

CC1231

CC1232
+1.2V
?
UC1N SKL_ULT

CPU POWER 3 OF 4 2 2 2 2 2 2 2 2 2 2
AU23 AK28
AU28 VDDQ_AU23 VCCIO_AK28 AK30
AU35 VDDQ_AU28 VCCIO_AK30 AL30 @ @ @ @ @
AU42 VDDQ_AU35 VCCIO_AL30 AL42
+1.2V BB23 VDDQ_AU42 VCCIO_AL42 AM28
2A , 3x22uF, 6x10uF, 4x1uF, SIT update VDDQ_BB23 VCCIO_AM28
BB32 AM30 +VCCSA
BB41 VDDQ_BB32 VCCIO_AM30 AM42
BB47 VDDQ_BB41 VCCIO_AM42
D VDDQ_BB47 D

10U_0603_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M
BB51 AK23 +VCCSA
VDDQ_BB51 VCCSA_AK23 AK25
1 1 1 1 1 1 1 1 1 1 1 1 1 1 VCCSA_AK25
CC1256

CC1257

CC1258

CC1168

CC1169

CC1171

CC1222

CC1223

CC1243

CC1244

CC1224

CC1225

CC1226

CC1227
G23 4.5A 10x10uF, 7x1uF, SIT update
AM40 VCCSA_G23 G25
+VDDQ_CPU_CLK VDDQC VCCSA_G25 G27
2 2 2 2 2 2 2 2 2 2 2 2 2 2 VCCSA_G27

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
+VCCST_CPU A18 G28
VCCST VCCSA_G28 J22
VCCSA_J22 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

CC1133

CC1134

CC1135

CC1136

CC1137

CC1251

CC1252

CC1253

CC1139

CC1140

CC1142

CC1145

CC1141

CC1143

CC1144
CD@ CD@ @ @ CD@ @ CD@ @ +VCCSTG A22 J23
VCCSTG_A22 VCCSA_J23

CC1132
J27
AL23 VCCSA_J27 K23
+VCCSFR_OC VCCPLL_OC VCCSA_K23 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
K25
K20 VCCSA_K25 K27
K21 VCCPLL_K20 VCCSA_K27 K28
+VCCPLL_CPU VCCPLL_K21 VCCSA_K28 K30 @ @ @ @ CD@ CD@ CD@
+VCCSTG +VCCST_CPU VCCSA_K30
+VDDQ_CPU_CLK AM23 VCCIO_SENSE 1 TC136 @
VCCIO_SENSE AM22 VSSIO_SENSE 1 TC137 @
120mA VSSIO_SENSE
VCCSA_VSS_SEN

1U_0402_6.3V6K
+1.2V RC1497 1 @ 2 0_0402_5% +VCCIO RC103 1 2 0_0402_5% H21
VSSSA_SENSE VCCSA_VSS_SEN 59
10U_0402_6.3V6M
1U_0201_6.3V6-M

1 H20 VCCSA_VCC_SEN
VCCSA_SENSE VCCSA_VCC_SEN 59

1U_0402_6.3V6K

CC86
1 1 +VCCST_CPU RC1604 1 @ 2 0_0402_5%
CC1229

CC1228

1
SKYLAKE-U_BGA13561 OF 20

CC87
2 REV = 1 ?
2 2 Reserved for VCCST/VCCSTG/VCCPLL @
@ power optimized 2 +VCCSA

+VCCSFR_OC
VCCSA_VCC_SEN RC101 1 2 100_0402_1%
+VCCPLL_CPU
RC104 1 @ 2 0_0402_5%
1U_0201_6.3V6-M

VCCSA_VSS_SEN RC102 1 2 100_0402_1%

1 120mA
CC85

C +VCCST_CPU RC105 1 2 0_0402_5% C

0.1u_0201_10V6K

1U_0402_6.3V6K
2 1 1

CC1249

CC84
2 2

+1.0VALW +VCCST_CPU

RC1605 1 @ 2 0_0402_5%

Reserved for VCCST/VCCSTG/VCCPLL power optimized

+1.0VALW +VCCST_CPU
QC19
AO3402_SOT-23-3
B B

+1.0VALW AON7408L_DFN8-5 +VCCIO 1 3

D S
QC11

10U_0603_6.3V6M

10U_0603_6.3V6M
G

1
1 1

CC79

CC80
1 RC135

2
5 S1 2 470_0603_5%
D S2
22U_0603_6.3V6-M

10U_0603_6.3V6M

3 @
S3 2 2
10U_0603_6.3V6M

22U_0603_6.3V6-M

1 1

2
G
CC71

CC72

1 1 @

1
CC1250

C1102
4

RC124
2 2 470_0603_5%

1
2 2 @ D
@ @ V20B+ VCCST_EN# 2 QC14

2
G 2N7002KW_SOT323-3
@
V20B+ RC142 1 2 S

3
+3VALW

0.01U_0201_25V6-K
100K_0402_5%

1
+3VALW D

2
RC1621 2 1 100K_0402_5% VCCIO_EN# 2 QC13 1

CC81
G 2N7002KW_SOT323-3 D RC1584
VCCST_EN#
0.01U_0201_25V6-K

@ RC1411 2 2 QC16A 120K_0402_5%

1

S 47K_0402_5% G 2N7002KDWH_SOT363-6
1
3
6

2
CC77

D RC125

1
RC128 1 2 VCCIO_EN# 2 QC12A 470K_0402_5% S

1
47K_0402_5% G 2N7002KDWH_SOT363-6
2

2
2

3
RC1575 S D
1

47K_0402_5% EC_VCCST_EN 5 QC16B

44 EC_VCCST_EN G
@ 2N7002KDWH_SOT363-6
1

4
+VCCST_CPU switch
3

D
RC1577 1 @ 2 0_0402_5% VCCIO_EN 5 QC12B
44 EC_VCCIO_EN G
A 2N7002KDWH_SOT363-6 A
DC1 1 2 @
11,44 PM_SLP_S3# S
4

RB751V-40_SOD323-2

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (CPU PWR2)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG411
Date: Thursday, January 14, 2016 Sheet 13 of 60
5 4 3 2 1
 5 4 3 2 1

+3VALW_PCH +VCCPGPPG

+1.0VALW RC1503 1 @ 2 0_0603_5% +VCCAMPHY

RC1622 1 @ 2 0_0402_5%
+1.0VALW RC1504 1 2 0_0603_5% +VCCAPLL_1P0

D +VCCHDA D

+3VS RC1585 1 @ 2 0_0402_5%

+3VALW_PCH RC1586 1 2 0_0603_5%

RC1620 1 @ 2 0_0402_5% VCCMPHYON_1P0_L1

+1.0VALW

1U_0402_6.3V6K
1

CC144
2

+3VALW_PCH

0.696A
+1.0VALW

1U_0402_6.3V6K
Near AB19

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1

CC141
1 1 1 1 1
+VCCPGPPG

CC156

CC164

CC172

CC173

CC174
22mA 2.574A
+1.0VALW +1.0VALW ?

22U_0603_6.3V6-M

1U_0402_6.3V6K
1 1 2 SKL_ULT

CC158
UC1O
2 2 2 2 2

CC153
@
CPU POWER 4 OF 4

1U_0402_6.3V6K
+VCCDSW_1P0 @ @ @ @
2 2

1U_0402_6.3V6K
AB19 1
VCCPRIM_1P0_AB19

CC175
@ AB20 AK15 20mA Near Y15
1 VCCPRIM_1P0_AB20 VCCPGPPA +3VALW_PCH

1U_0402_6.3V6K
CC145
P18 AG15 4mA
1.5A VCCPRIM_1P0_P18 VCCPGPPB Y16 6mA
+1.0VALW Near AF18 VCCPGPPC 2 1

CC176
AF18 Y15 8mA
2 AF19 VCCPRIM_CORE_AF18 VCCPGPPD T16 6mA @
VCCPRIM_CORE_AF19 VCCPGPPE +1.8VALW
47U_0805_4V6-M

1U_0201_6.3V6-M

1U_0402_6.3V6K
C V20 AF16 161mA C
VCCPRIM_CORE_V20 VCCPGPPF +1.8VALW 2
PCH Internal VRM V21 AD15 61mA
1 1 VCCPRIM_CORE_V21 VCCPGPPG 1
CC148

CC147

CC142
@ +3VALW_PCH

0.1u_0201_10V6K

1U_0402_6.3V6K
Near N15 AL1 V19
DCPDSW_1P0 VCCPRIM_3P3_V19
2 2 2 1 1

CC149

CC143
K17 T1 +1.0VALW
88mA VCCMPHYON_1P0_L1 L1 VCCMPHYAON_1P0_K17 VCCPRIM_1P0_T1
+VCCAMPHY VCCMPHYAON_1P0_L1
22U_0603_6.3V6-M

1U_0402_6.3V6K

@ AA1 6mA
N15 VCCATS_1P8 2 2
1 1 VCCMPHYGT_1P0_N15
C1096

CC151

N16 AK17 1mA

N17 VCCMPHYGT_1P0_N16 VCCRTCPRIM_3P3
P15 VCCMPHYGT_1P0_N17 AK19 1mA
2 2 VCCMPHYGT_1P0_P15 VCCRTC_AK19 VCCRTC

0.1u_0201_10V6K

1U_0402_6.3V6K
Near K15 P16 BB14
@ VCCMPHYGT_1P0_P16 VCCRTC_BB14
1 1

CC146

CC1242
K15 BB10 VCCRTCEXT
L15 VCCAMPHYPLL_1P0_K15 DCPRTC
VCCAMPHYPLL_1P0_L15

0.1u_0201_10V6K
A14 35mA
VCCCLK1 +1.0VALW 2 2
+VCCAPLL_1P0
22mA V15 1
VCCAPLL_1P0
0.1u_0201_10V6K

1U_0402_6.3V6K

CC55
K19 29mA 0_0603_5% 1 @ 2 RC1587 +1.0VALW
VCCCLK2

1U_0402_6.3V6K
1 1 +1.0VALW AB17
VCCPRIM_1P0_AB17

22U_0603_6.3V6-M
C1097

CC154

Y18 L21 24mA

VCCPRIM_1P0_Y18 VCCCLK3 +1.0VALW 1 1 2

C1098
CC56
+VCCHDA
0.1u_0201_10V6K

+3VALW
0.118A AD17 N20 33mA
+VCCCLK4
2 2 AD18 VCCDSW_3P3_AD17 VCCCLK4
1 VCCDSW_3P3_AD18 2 2
CC165

AJ17 L19 4mA

+VCCCLK5
VCCDSW_3P3_AJ17 VCCCLK5 @
68mA AJ19 A10 10mA
2 VCCHDA VCCCLK6 +1.0VALW

1U_0402_6.3V6K
11mA AJ16 AN11
+3VALW_PCH VCCSPI GPP_B0/CORE_VID0 1

CC57
AN13
0.642A AF20 GPP_B1/CORE_VID1
+1.0VALW VCCSRAM_1P0_AF20
1U_0402_6.3V6K

AF21
T19 VCCSRAM_1P0_AF21 2
1 Near AF20 VCCSRAM_1P0_T19
CC159

T20
VCCSRAM_1P0_T20
75mA AJ21
2 +3VALW_PCH VCCPRIM_3P3_AJ21
1U_0402_6.3V6K

CD@ 1 +1.0VALW AK20

VCCPRIM_1P0_AK20
CC171

+1.0VALW
33mA N18 +VCCCLK4 0_0603_5% 1 @ 2 RC1588 +1.0VALW
B VCCAPLLEBB B

22U_0603_6.3V6-M
2
1U_0402_6.3V6K

1
1 OF 20

C1099
1 SKYLAKE-U_BGA1356
CC169

CD@ REV = 1
?
@
2
2 @

+VCCCLK5 0_0603_5% 1 @ 2 RC1589 +1.0VALW

22U_0603_6.3V6-M
Near A18
1

C1100
2
@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (PCH PWR)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

WWW.AliSaler.Com
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG411
Date: Thursday, January 14, 2016 Sheet 14 of 60
5 4 3 2 1
 5 4 3 2 1

SKL_ULT
UC1Q ?
SKL_ULT
UC1P ?
SKL_ULT ?
GND 2 OF 3 UC1R
GND 1 OF 3
AT63 BA49 GND 3 OF 3
A5 AL65 AT68 VSS_AT63 VSS_BA49 BA53 F8 L18
A67 VSS_A5 VSS_AL65 AL66 AT71 VSS_AT68 VSS_BA53 BA57 G10 VSS_F8 VSS_L18 L2
A70 VSS_A67 VSS_AL66 AM13 AU10 VSS_AT71 VSS_BA57 BA6 G22 VSS_G10 VSS_L2 L20
D AA2 VSS_A70 VSS_AM13 AM21 AU15 VSS_AU10 VSS_BA6 BA62 G43 VSS_G22 VSS_L20 L4 D
AA4 VSS_AA2 VSS_AM21 AM25 AU20 VSS_AU15 VSS_BA62 BA66 G45 VSS_G43 VSS_L4 L8
AA65 VSS_AA4 VSS_AM25 AM27 AU32 VSS_AU20 VSS_BA66 BA71 G48 VSS_G45 VSS_L8 N10
AA68 VSS_AA65 VSS_AM27 AM43 AU38 VSS_AU32 VSS_BA71 BB18 G5 VSS_G48 VSS_N10 N13
AB15 VSS_AA68 VSS_AM43 AM45 AV1 VSS_AU38 VSS_BB18 BB26 G52 VSS_G5 VSS_N13 N19
AB16 VSS_AB15 VSS_AM45 AM46 AV68 VSS_AV1 VSS_BB26 BB30 G55 VSS_G52 VSS_N19 N21
AB18 VSS_AB16 VSS_AM46 AM55 AV69 VSS_AV68 VSS_BB30 BB34 G58 VSS_G55 VSS_N21 N6
AB21 VSS_AB18 VSS_AM55 AM60 AV70 VSS_AV69 VSS_BB34 BB38 G6 VSS_G58 VSS_N6 N65
AB8 VSS_AB21 VSS_AM60 AM61 AV71 VSS_AV70 VSS_BB38 BB43 G60 VSS_G6 VSS_N65 N68
AD13 VSS_AB8 VSS_AM61 AM68 AW10 VSS_AV71 VSS_BB43 BB55 G63 VSS_G60 VSS_N68 P17
AD16 VSS_AD13 VSS_AM68 AM71 AW12 VSS_AW10 VSS_BB55 BB6 G66 VSS_G63 VSS_P17 P19
AD19 VSS_AD16 VSS_AM71 AM8 AW14 VSS_AW12 VSS_BB6 BB60 H15 VSS_G66 VSS_P19 P20
AD20 VSS_AD19 VSS_AM8 AN20 AW16 VSS_AW14 VSS_BB60 BB64 H18 VSS_H15 VSS_P20 P21
AD21 VSS_AD20 VSS_AN20 AN23 AW18 VSS_AW16 VSS_BB64 BB67 H71 VSS_H18 VSS_P21 R13
AD62 VSS_AD21 VSS_AN23 AN28 AW21 VSS_AW18 VSS_BB67 BB70 J11 VSS_H71 VSS_R13 R6
AD8 VSS_AD62 VSS_AN28 AN30 AW23 VSS_AW21 VSS_BB70 C1 J13 VSS_J11 VSS_R6 T15
AE64 VSS_AD8 VSS_AN30 AN32 AW26 VSS_AW23 VSS_C1 C25 J25 VSS_J13 VSS_T15 T17
AE65 VSS_AE64 VSS_AN32 AN33 AW28 VSS_AW26 VSS_C25 C5 J28 VSS_J25 VSS_T17 T18
AE66 VSS_AE65 VSS_AN33 AN35 AW30 VSS_AW28 VSS_C5 D10 J32 VSS_J28 VSS_T18 T2
AE67 VSS_AE66 VSS_AN35 AN37 AW32 VSS_AW30 VSS_D10 D11 J35 VSS_J32 VSS_T2 T21
AE68 VSS_AE67 VSS_AN37 AN38 AW34 VSS_AW32 VSS_D11 D14 J38 VSS_J35 VSS_T21 T4
AE69 VSS_AE68 VSS_AN38 AN40 AW36 VSS_AW34 VSS_D14 D18 J42 VSS_J38 VSS_T4 U10
AF1 VSS_AE69 VSS_AN40 AN42 AW38 VSS_AW36 VSS_D18 D22 J8 VSS_J42 VSS_U10 U63
AF10 VSS_AF1 VSS_AN42 AN58 AW41 VSS_AW38 VSS_D22 D25 K16 VSS_J8 VSS_U63 U64
AF15 VSS_AF10 VSS_AN58 AN63 AW43 VSS_AW41 VSS_D25 D26 K18 VSS_K16 VSS_U64 U66
AF17 VSS_AF15 VSS_AN63 AP10 AW45 VSS_AW43 VSS_D26 D30 K22 VSS_K18 VSS_U66 U67
AF2 VSS_AF17 VSS_AP10 AP18 AW47 VSS_AW45 VSS_D30 D34 K61 VSS_K22 VSS_U67 U69
AF4 VSS_AF2 VSS_AP18 AP20 AW49 VSS_AW47 VSS_D34 D39 K63 VSS_K61 VSS_U69 U70
AF63 VSS_AF4 VSS_AP20 AP23 AW51 VSS_AW49 VSS_D39 D44 K64 VSS_K63 VSS_U70 V16
AG16 VSS_AF63 VSS_AP23 AP28 AW53 VSS_AW51 VSS_D44 D45 K65 VSS_K64 VSS_V16 V17
AG17 VSS_AG16 VSS_AP28 AP32 AW55 VSS_AW53 VSS_D45 D47 K66 VSS_K65 VSS_V17 V18
AG18 VSS_AG17 VSS_AP32 AP35 AW57 VSS_AW55 VSS_D47 D48 K67 VSS_K66 VSS_V18 W13
C AG19 VSS_AG18 VSS_AP35 AP38 AW6 VSS_AW57 VSS_D48 D53 K68 VSS_K67 VSS_W13 W6 C
AG20 VSS_AG19 VSS_AP38 AP42 AW60 VSS_AW6 VSS_D53 D58 K70 VSS_K68 VSS_W6 W9
AG21 VSS_AG20 VSS_AP42 AP58 AW62 VSS_AW60 VSS_D58 D6 K71 VSS_K70 VSS_W9 Y17
AG71 VSS_AG21 VSS_AP58 AP63 AW64 VSS_AW62 VSS_D6 D62 L11 VSS_K71 VSS_Y17 Y19
AH13 VSS_AG71 VSS_AP63 AP68 AW66 VSS_AW64 VSS_D62 D66 L16 VSS_L11 VSS_Y19 Y20
AH6 VSS_AH13 VSS_AP68 AP70 AW8 VSS_AW66 VSS_D66 D69 L17 VSS_L16 VSS_Y20 Y21
AH63 VSS_AH6 VSS_AP70 AR11 AY66 VSS_AW8 VSS_D69 E11 VSS_L17 VSS_Y21
AH64 VSS_AH63 VSS_AR11 AR15 B10 VSS_AY66 VSS_E11 E15
AH67 VSS_AH64 VSS_AR15 AR16 B14 VSS_B10 VSS_E15 E18
AJ15 VSS_AH67 VSS_AR16 AR20 B18 VSS_B14 VSS_E18 E21
AJ18 VSS_AJ15 VSS_AR20 AR23 B22 VSS_B18 VSS_E21 E46 1 OF 20
SKYLAKE-U_BGA1356
AJ20 VSS_AJ18 VSS_AR23 AR28 B30 VSS_B22 VSS_E46 E50 REV = 1
VSS_AJ20 VSS_AR28 VSS_B30 VSS_E50 ?
AJ4 AR35 B34 E53 @
AK11 VSS_AJ4 VSS_AR35 AR42 B39 VSS_B34 VSS_E53 E56
AK16 VSS_AK11 VSS_AR42 AR43 B44 VSS_B39 VSS_E56 E6
AK18 VSS_AK16 VSS_AR43 AR45 B48 VSS_B44 VSS_E6 E65
AK21 VSS_AK18 VSS_AR45 AR46 B53 VSS_B48 VSS_E65 E71
AK22 VSS_AK21 VSS_AR46 AR48 B58 VSS_B53 VSS_E71 F1
AK27 VSS_AK22 VSS_AR48 AR5 B62 VSS_B58 VSS_F1 F13
AK63 VSS_AK27 VSS_AR5 AR50 B66 VSS_B62 VSS_F13 F2
AK68 VSS_AK63 VSS_AR50 AR52 B71 VSS_B66 VSS_F2 F22
AK69 VSS_AK68 VSS_AR52 AR53 BA1 VSS_B71 VSS_F22 F23
AK8 VSS_AK69 VSS_AR53 AR55 BA10 VSS_BA1 VSS_F23 F27
AL2 VSS_AK8 VSS_AR55 AR58 BA14 VSS_BA10 VSS_F27 F28
AL28 VSS_AL2 VSS_AR58 AR63 BA18 VSS_BA14 VSS_F28 F32
AL32 VSS_AL28 VSS_AR63 AR8 BA2 VSS_BA18 VSS_F32 F33
AL35 VSS_AL32 VSS_AR8 AT2 BA23 VSS_BA2 VSS_F33 F35
AL38 VSS_AL35 VSS_AT2 AT20 BA28 VSS_BA23 VSS_F35 F37
AL4 VSS_AL38 VSS_AT20 AT23 BA32 VSS_BA28 VSS_F37 F38
AL45 VSS_AL4 VSS_AT23 AT28 BA36 VSS_BA32 VSS_F38 F4
AL48 VSS_AL45 VSS_AT28 AT35 F68 VSS_BA36 VSS_F4 F40
AL52 VSS_AL48 VSS_AT35 AT4 BA45 VSS_F68 VSS_F40 F42
B AL55 VSS_AL52 VSS_AT4 AT42 VSS_BA45 VSS_F42 BA41 B
AL58 VSS_AL55 VSS_AT42 AT56 VSS_BA41
AL64 VSS_AL58 VSS_AT56 AT58
VSS_AL64 VSS_AT58
1 OF 20
SKYLAKE-U_BGA1356
1 OF 20
SKYLAKE-U_BGA1356 REV = 1 ?
REV = 1 ? @
@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (VSS)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG411
Date: Thursday, January 14, 2016 Sheet 15 of 60
5 4 3 2 1
 5 4 3 2 1

?
SKL_ULT
UC1S

RESERVED SIGNALS-1

CPU_CFG0 E68 BB68 1 TC173 @ PAD

D PAD @ TC142 1 CPU_CFG1 B67 CFG[0] RSVD_TP_BB68 BB69 1 TC174 @ PAD D
PAD @ TC143 1 CPU_CFG2 D65 CFG[1] RSVD_TP_BB69
PAD @ TC144 1 XDP_CPU_CFG3 D67 CFG[2] AK13 1 TC175 @ PAD
CFG[3] RSVD_TP_AK13
2

CPU_CFG4 E70 AK12 1 TC176 @ PAD

RC1618 PAD @ TC146 1 CPU_CFG5 C68 CFG[4] RSVD_TP_AK12 +VCCST_CPU
1K_0402_5% PAD @ TC147 1 CPU_CFG6 D68 CFG[5] BB2 UC1T SKL_ULT ?
@ PAD @ TC148 1 CPU_CFG7 C67 CFG[6] RSVD_BB2 BA3
CFG[7] RSVD_BA3

2
PAD @ TC153 1 CPU_CFG8 F71 SPARE
1

RC106 PAD @ TC150 1 CPU_CFG9 G69 CFG[8] +1.8VALW

CFG[9]

1
1K_0402_5% PAD @ TC151 1 CPU_CFG10 F70 AU5 AW69 F6
PAD @ TC152 1 CPU_CFG11 G68 CFG[10] TP5 AT5 AW68 RSVD_AW69 RSVD_F6 E3 RC1619
PAD @ TC157 1 CPU_CFG12 H70 CFG[11] TP6 AU56 RSVD_AW68 RSVD_E3 C11 150_0402_5%
1

PAD @ TC154 1 CPU_CFG13 G71 CFG[12] AW48 RSVD_AU56 RSVD_C11 B11 @

PAD @ TC155 1 CPU_CFG14 H69 CFG[13] D5 Cannonlake@ C7 RSVD_AW48 RSVD_B11 A11

2
PAD @ TC156 1 CPU_CFG15 G70 CFG[14] RSVD_D5 D4 RC1582 2 1 0_0402_5% RSVD_U12 U12 RSVD_C7 RSVD_A11 D12
CFG[15] RSVD_D4 B2 1 TC183 @ PAD RC1583 2 1 0_0402_5% RSVD_U11 U11 RSVD_U12 RSVD_D12 C12
PAD @ TC159 1 CPU_CFG16 E63 RSVD_B2 C2 1 TC185 @ PAD Cannonlake@ H11 RSVD_U11 RSVD_C12 F52 RSVD_F52
PAD @ TC158 1 CPU_CFG17 F63 CFG[16] RSVD_C2 RSVD_H11 RSVD_F52
CFG[17] B3 1 TC184 @ PAD
PAD @ TC161 1 CPU_CFG18 E66 RSVD_B3 A3 1 TC181 @ PAD
CFG[18] RSVD_A3 1 OF 20
PAD @ TC160 1 CPU_CFG19 F66 SKYLAKE-U_BGA1356
CFG[19] AW1 REV = 1 ?
C CFG_RCOMP E60 RSVD_AW1 @ C
CFG_RCOMP E1 1 TC187 @ PAD
PAD @ TC166 1 XDP_ITP_PMODE E8 RSVD_E1 E2
ITP_PMODE RSVD_E2
2

RC162 AY2 BA4

AY1 RSVD_AY2 RSVD_BA4 BB4
49.9_0402_1% RSVD_AY1 RSVD_BB4
PAD @ TC186 1 D1 A4 1 TC182 @ PAD
1

D3 RSVD_D1 RSVD_A4 C4
RSVD_D3 RSVD_C4
K46 BB5
K45 RSVD_K46 TP4
RSVD_K45 A69 1 TC188 @ PAD
AL25 RSVD_A69 B69 1 TC193 @ PAD
AL27 RSVD_AL25 RSVD_B69
RSVD_AL27 AY3 RSVD_AY3 need to check with Intel
PAD @ TC189 1 C71 RSVD_AY3
RSVD_C71

2
PAD @ TC191 1 B70 D71 1 TC190 @ PAD
RSVD_B70 RSVD_D71 C70 1 TC192 @ PAD RC107
F60 RSVD_C70
RSVD_F60 0_0402_5%
C54
A52 RSVD_C54 D54

1
B RSVD_A52 RSVD_D54 B
PAD @ TC171 1 BA70 AY4
PAD @ TC172 1 BA68 RSVD_TP_BA70 TP1 BB3
RSVD_TP_BA68 TP2
J71 AY71 VSS_AY71 need to check with Intel
J68 RSVD_J71 VSS_AY71 AR56 1 TC167 @ PAD
RSVD_J68 ZVM#

2
PAD @ TC169 1 F65 AW71 1 TC177 @ PAD
PAD @ TC170 1 G65 VSS_F65 RSVD_TP_AW71 AW70 1 TC178 @ PAD RC108
VSS_G65 RSVD_TP_AW70
0_0402_5%
F61 AP56 1 TC168 @ PAD
E61 RSVD_F61 MSM# C64 PROC_SELECT# 1 2 +VCCST_CPU

1
RSVD_E61 PROC_SELECT# 100K_0402_5% Cannonlake@ R22

1 OF 20
SKYLAKE-U_BGA1356
REV = 1 ?
@
Default
Pin Name Strap Description Configuration Value

A A
CFG[4] Display Port — 1 = eDP Disabled 1
Presence strap — 0 = eDP Enabled Title
* Security Classification LC Future Center Secret Data
Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (CFG,RESERVED)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG411
Date: Thursday, January 14, 2016 Sheet 16 of 60
5 4 3 2 1

WWW.AliSaler.Com
 5 4 3 2 1

DDRA_DQ[0..63]
DDRA_DQ[0..63] 5
UD1 @ UD2 @ DDRA_DQS#[0..7]
DDRA_DQS#[0..7] 5
DDRA_MA0 P3 G2 DDRA_DQ2 DDRA_MA0 P3 G2 DDRA_DQ18 +1.2V DDRA_DQS[0..7]
DDRA_MA1 A0 DQ0 DDRA_DQ3 DDRA_MA1 A0 DQ0 DDRA_DQ19 DDRA_DQS[0..7] 5
P7 F7 P7 F7
DDRA_MA2 R3 A1 DQ1 H3 DDRA_DQ7 DDRA_MA2 R3 A1 DQ1 H3 DDRA_DQ16 DDRA_MA[0..13]
DDRA_MA3 A2 DQ2 DDRA_DQ1 DDRA_MA3 A2 DQ2 DDRA_DQ21 DDRA_MA[0..13] 5
N7 H7 N7 H7
DDRA_MA4 N3 A3 DQ3 H2 DDRA_DQ4 DDRA_MA4 N3 A3 DQ3 H2 DDRA_DQ22
A4 DQ4 A4 DQ4 1

1
DDRA_MA5 P8 H8 DDRA_DQ0 DDRA_MA5 P8 H8 DDRA_DQ17 +0.6VS
DDRA_MA6 P2 A5 DQ5 J3 DDRA_DQ6 DDRA_MA6 P2 A5 DQ5 J3 DDRA_DQ23 CD119 RD45
DDRA_MA7 R8 A6 DQ6 J7 DDRA_DQ5 DDRA_MA7 R8 A6 DQ6 J7 DDRA_DQ20 0.1u_0201_10V6K 1.8K_0402_1%
DDRA_MA8 R2 A7 DQ7 A3 DDRA_DQ11 DDRA_MA8 R2 A7 DQ7 A3 DDRA_DQ30 2 DDRA_CLK0# RD49 1 2 36_0402_1%
DDRA_MA9 R7 A8 DQ8 B8 DDRA_DQ8 DDRA_MA9 R7 A8 DQ8 B8 DDRA_DQ28 DDRA_CLK0 RD50 1 2 36_0402_1%

2
DDRA_MA10 M3 A9 DQ9 C3 DDRA_DQ14 DDRA_MA10 M3 A9 DQ9 C3 DDRA_DQ26
DDRA_MA11 T2 A10/AP DQ10 C7 DDRA_DQ13 DDRA_MA11 T2 A10/AP DQ10 C7 DDRA_DQ25 DDRA_CS0# RD51 1 2 34.8_0402_1%
DDRA_MA12 M7 A11 DQ11 C2 DDRA_DQ15 DDRA_MA12 M7 A11 DQ11 C2 DDRA_DQ31 RD46 1 2 +VREF_CA_MD DDRA_ODT0 RD52 1 2 34.8_0402_1%
DDRA_MA13 A12/BC_N DQ12 DDRA_DQ12 DDRA_MA13 A12/BC_N DQ12 DDRA_DQ29 5 DDR_SA_VREFCA
T8 C8 T8 C8 2.7_0402_1%
A13 DQ13 D3 DDRA_DQ10 A13 DQ13 D3 DDRA_DQ27 DDRA_CKE0 RD53 1 2 34.8_0402_1%
DQ14 DQ14 1

1
D DDRA_MA14_WE# L2 D7 DDRA_DQ9 DDRA_MA14_WE# L2 D7 DDRA_DQ24 D
5 DDRA_MA14_WE# WE_N/A14 DQ15 WE_N/A14 DQ15 1
DDRA_MA15_CAS# M8 DDRA_MA15_CAS# M8 CD111 RD47 DDRA_MA0 RD54 1 2 34.8_0402_1%
5 DDRA_MA15_CAS# DDRA_MA16_RAS# CAS_N/A15 +1.2V DDRA_MA16_RAS# CAS_N/A15 +1.2V DDRA_MA1
L8 L8 0.022U_0201_6.3V6-K 1.8K_0402_1% CD112 RD55 1 2 34.8_0402_1%
5 DDRA_MA16_RAS# RAS_N/A16 RAS_N/A16 2 DDRA_MA2
D1 D1 0.1u_0201_10V6K RD56 1 2 34.8_0402_1%
DDRA_CLK0# K8 VDD1 J1 DDRA_CLK0# K8 VDD1 J1 2 DDRA_MA3 RD57 1 2 34.8_0402_1%
5 DDRA_CLK0#

2
CK_C VDD2 CK_C VDD2

1
DDRA_CLK0 K7 L1 DDRA_CLK0 K7 L1
5 DDRA_CLK0 CK_T VDD3 CK_T VDD3
R1 R1 RD48 DDRA_MA4 RD58 1 2 34.8_0402_1%
DDRA_CKE0 K2 VDD4 B3 DDRA_CKE0 K2 VDD4 B3 24.9_0402_1% DDRA_MA5 RD59 1 2 34.8_0402_1%
5 DDRA_CKE0 CKE VDD5 CKE VDD5
G7 G7 DDRA_MA6 RD60 1 2 34.8_0402_1%
DDRA_DQS#0 F3 VDD6 B9 DDRA_DQS#2 F3 VDD6 B9 DDRA_MA7 RD61 1 2 34.8_0402_1%

2
DDRA_DQS0 G3 LDQS_C VDD7 J9 DDRA_DQS2 G3 LDQS_C VDD7 J9
DDRA_DQS#1 A7 LDQS_T VDD8 L9 DDRA_DQS#3 A7 LDQS_T VDD8 L9 DDRA_MA8 RD62 1 2 34.8_0402_1%
+1.2V DDRA_DQS1 B7 UDQS_C VDD9 T9 +1.2V DDRA_DQS3 B7 UDQS_C VDD9 T9 DDRA_MA9 RD63 1 2 34.8_0402_1%
UDQS_T VDD10 UDQS_T VDD10 DDRA_MA10 RD64 1 2 34.8_0402_1%
RD65 1 @ 2 0_0402_5% DDRA_DM1 E2 A1 RD66 1 @ 2 0_0402_5% DDRA_DM3 E2 A1 DDRA_MA11 RD67 1 2 34.8_0402_1%
RD68 1 @ 2 0_0402_5% DDRA_DM0 E7 NF/UDM_N/UDBI_N VDDQ1 C1 RD69 1 @ 2 0_0402_5% DDRA_DM2 E7 NF/UDM_N/UDBI_N VDDQ1 C1
NF/LDM_N/LDBI_N VDDQ2 G1 NF/LDM_N/LDBI_N VDDQ2 G1 DDRA_MA12 RD70 1 2 34.8_0402_1%
DDRA_BS0# N2 VDDQ3 F2 DDRA_BS0# N2 VDDQ3 F2 DDRA_MA13 RD71 1 2 34.8_0402_1%
5 DDRA_BS0# BA0 VDDQ4 BA0 VDDQ4
DDRA_BS1# N8 J2 DDRA_BS1# N8 J2 DDRA_MA14_WE#RD72 1 2 34.8_0402_1%
5 DDRA_BS1# BA1 VDDQ5 BA1 VDDQ5
F8 F8 DDRA_MA15_CAS#RD73 1 2 34.8_0402_1%
DDRA_ACT# L3 VDDQ6 J8 DDRA_ACT# L3 VDDQ6 J8
5 DDRA_ACT# ACT_N VDDQ7 ACT_N VDDQ7
DDRA_CS0# L7 A9 DDRA_CS0# L7 A9
5 DDRA_CS0# DDRA_ALERT# CS_N VDDQ8 DDRA_ALERT# CS_N VDDQ8 DDRA_MA16_RAS#RD74
P9 D9 P9 D9 1 2 34.8_0402_1%
5 DDRA_ALERT# ALERT_N VDDQ9 +2.5V_DDR ALERT_N VDDQ9 +2.5V_DDR DDRA_BG0
G9 G9 RD75 1 2 34.8_0402_1%
DDRA_BG0 M2 VDDQ10 DDRA_BG0 M2 VDDQ10 DDRA_BS0# RD76 1 2 34.8_0402_1%
5 DDRA_BG0 BG0 BG0
B1 B1 DDRA_BS1# RD77 1 2 34.8_0402_1%
DDRA_ODT0 K3 VPP1 R9 DDRA_ODT0 K3 VPP1 R9
5 DDRA_ODT0 ODT VPP2 ODT VPP2 DDRA_ACT# RD78 1 2 34.8_0402_1%
DDRA_PAR +VREF_CA_MD DDRA_PAR +VREF_CA_MD DDRA_PAR

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
T3 M1 T3 M1 RD79 1 2 34.8_0402_1%
5 DDRA_PAR PAR VREFCA PAR VREFCA
1 1 1 1
2 10K_0402_5% TEN_UD1 2 10K_0402_5% TEN_UD2

0.1u_0201_10V6K

0.1u_0201_10V6K
RD94 1 N9 E1 RD95 1 N9 E1

.047U_0201_6.3V6K

.047U_0201_6.3V6K
TEN VSS1 K1 TEN VSS1 K1
VSS2 1 1 VSS2 1 1
CPU_DRAMRST# P1 N1 CPU_DRAMRST# P1 N1
6,18 CPU_DRAMRST# RESET_N VSS3 2 2 RESET_N VSS3 2 2
T1 T1
VSS4 VSS4
0.1u_0201_10V6K

0.1u_0201_10V6K
CD121

CD123

CD124

CD125
@ F1 B2 @ F1 B2
H1 VSSQ1 VSS5 G8 2 2 H1 VSSQ1 VSS5 G8 2 2
1 VSSQ2 VSS6 1 VSSQ2 VSS6 +1.2V

CD113

CD120

CD114

CD122
A2 E9 A2 E9
D2 VSSQ3 VSS7 K9 D2 VSSQ3 VSS7 K9
E3 VSSQ4 VSS8 M9 E3 VSSQ4 VSS8 M9
2 VSSQ5 VSS9 2 VSSQ5 VSS9 DDRA_ALERT#
CD47

CD48
A8 A8 RD86 1 2 49.9_0402_1%
D8 VSSQ6 T7 D8 VSSQ6 T7
E8 VSSQ7 NC E8 VSSQ7 NC
C9 VSSQ8 C9 VSSQ8
H9 VSSQ9 H9 VSSQ9
VSSQ10 VSSQ10
C C
F9 F9
ZQ ZQ
1

1
RD39 MT40A512M16HA083EA_FBGA96 RD40 MT40A512M16HA083EA_FBGA96
240_0402_1% 240_0402_1%
2

2
+1.2V
(1uF_0402_6.3V) *16
Place 4 near each DRAM

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
UD3 @ 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
UD4 @
DDRA_MA0 P3 G2 DDRA_DQ43
DDRA_MA1 P7 A0 DQ0 F7 DDRA_DQ44 DDRA_MA0 P3 G2 DDRA_DQ59
DDRA_MA2 R3 A1 DQ1 H3 DDRA_DQ46 DDRA_MA1 P7 A0 DQ0 F7 DDRA_DQ60 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
DDRA_MA3 A2 DQ2 DDRA_DQ40 DDRA_MA2 A1 DQ1 DDRA_DQ62

CD126

CD127

CD128

CD129

CD130

CD131

CD132

CD133

CD134

CD135

CD136

CD137

CD138

CD139

CD140

CD141
N7 H7 R3 H3
DDRA_MA4 N3 A3 DQ3 H2 DDRA_DQ47 DDRA_MA3 N7 A2 DQ2 H7 DDRA_DQ56
DDRA_MA5 P8 A4 DQ4 H8 DDRA_DQ45 DDRA_MA4 N3 A3 DQ3 H2 DDRA_DQ63 CD@ CD@ CD@ CD@
DDRA_MA6 P2 A5 DQ5 J3 DDRA_DQ42 DDRA_MA5 P8 A4 DQ4 H8 DDRA_DQ61
DDRA_MA7 R8 A6 DQ6 J7 DDRA_DQ41 DDRA_MA6 P2 A5 DQ5 J3 DDRA_DQ58
DDRA_MA8 R2 A7 DQ7 A3 DDRA_DQ34 DDRA_MA7 R8 A6 DQ6 J7 DDRA_DQ57
DDRA_MA9 R7 A8 DQ8 B8 DDRA_DQ37 DDRA_MA8 R2 A7 DQ7 A3 DDRA_DQ54
DDRA_MA10 M3 A9 DQ9 C3 DDRA_DQ39 DDRA_MA9 R7 A8 DQ8 B8 DDRA_DQ52
DDRA_MA11 T2 A10/AP DQ10 C7 DDRA_DQ32 DDRA_MA10 M3 A9 DQ9 C3 DDRA_DQ51
DDRA_MA12 M7 A11 DQ11 C2 DDRA_DQ35 DDRA_MA11 T2 A10/AP DQ10 C7 DDRA_DQ49 +1.2V +1.2V
A12/BC_N DQ12 A11 DQ11 (1OuF_0603_6.3V) *5
DDRA_MA13 T8 C8 DDRA_DQ33 DDRA_MA12 M7 C2 DDRA_DQ50
A13 DQ13 DDRA_DQ38 DDRA_MA13 A12/BC_N DQ12 DDRA_DQ53
Place around the DRAMs
D3 T8 C8
DDRA_MA14_WE# L2 DQ14 D7 DDRA_DQ36 A13 DQ13 D3 DDRA_DQ55
DDRA_MA15_CAS# M8 WE_N/A14 DQ15 DDRA_MA14_WE# L2 DQ14 D7 DDRA_DQ48
DDRA_MA16_RAS# L8 CAS_N/A15 +1.2V DDRA_MA15_CAS# M8 WE_N/A14 DQ15
RAS_N/A16 D1 DDRA_MA16_RAS# L8 CAS_N/A15 +1.2V
DDRA_CLK0# VDD1 RAS_N/A16

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
K8 J1 D1
DDRA_CLK0 K7 CK_C VDD2 L1 DDRA_CLK0# K8 VDD1 J1
CK_T VDD3 CK_C VDD2 1 1 1 1 1 1 1
B R1 DDRA_CLK0 K7 L1 CD109 CD110 B
DDRA_CKE0 K2 VDD4 B3 CK_T VDD3 R1 22P_0402_50V8-J 22P_0402_50V8-J
CKE VDD5 G7 DDRA_CKE0 K2 VDD4 B3 RF@ RF@
DDRA_DQS#5 F3 VDD6 B9 CKE VDD5 G7 2 2 2 2 2 2 2
DDRA_DQS5 LDQS_C VDD7 DDRA_DQS#7 VDD6

CD142

CD143

CD144

CD145

CD146
G3 J9 F3 B9
DDRA_DQS#4 A7 LDQS_T VDD8 L9 DDRA_DQS7 G3 LDQS_C VDD7 J9
+1.2V DDRA_DQS4 B7 UDQS_C VDD9 T9 DDRA_DQS#6 A7 LDQS_T VDD8 L9 CD@
UDQS_T VDD10 +1.2V DDRA_DQS6 B7 UDQS_C VDD9 T9
RD87 1 @ 2 0_0402_5% DDRA_DM4 E2 A1 UDQS_T VDD10
RD88 1 @ 2 0_0402_5% DDRA_DM5 E7 NF/UDM_N/UDBI_N VDDQ1 C1 RD89 1 @ 2 0_0402_5% DDRA_DM6 E2 A1
NF/LDM_N/LDBI_N VDDQ2 G1 RD90 1 @ 2 0_0402_5% DDRA_DM7 E7 NF/UDM_N/UDBI_N VDDQ1 C1
DDRA_BS0# N2 VDDQ3 F2 NF/LDM_N/LDBI_N VDDQ2 G1
DDRA_BS1# N8 BA0 VDDQ4 J2 DDRA_BS0# N2 VDDQ3 F2
BA1 VDDQ5 F8 DDRA_BS1# N8 BA0 VDDQ4 J2
DDRA_ACT# L3 VDDQ6 J8 BA1 VDDQ5 F8
DDRA_CS0# L7 ACT_N VDDQ7 A9 DDRA_ACT# L3 VDDQ6 J8
CS_N VDDQ8 ACT_N VDDQ7 +2.5V_DDR
(1OuF_0603_6.3V) *3 +2.5V_DDR
DDRA_ALERT# P9 D9 DDRA_CS0# L7 A9
ALERT_N VDDQ9 +2.5V_DDR DDRA_ALERT# CS_N VDDQ8 Place around the DRAMs
G9 P9 D9
DDRA_BG0 M2 VDDQ10 ALERT_N VDDQ9 G9 +2.5V_DDR
BG0 B1 DDRA_BG0 M2 VDDQ10
DDRA_ODT0 K3 VPP1 R9 BG0 B1
ODT VPP2 DDRA_ODT0 VPP1

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
K3 R9
DDRA_PAR +VREF_CA_MD ODT VPP2
1U_0402_6.3V6K

1U_0402_6.3V6K

T3 M1 1 1 1 1 1
PAR VREFCA DDRA_PAR +VREF_CA_MD

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 T3 M1 CD157 CD148
2 10K_0402_5% TEN_UD3 PAR VREFCA
0.1u_0201_10V6K

RD96 1 N9 E1 22P_0402_50V8-J 22P_0402_50V8-J

.047U_0201_6.3V6K

TEN VSS1 1 1
2 10K_0402_5% TEN_UD4

0.1u_0201_10V6K
K1 RD97 1 N9 E1 RF@ RF@

.047U_0201_6.3V6K
VSS2 1 1 TEN VSS1 2 2 2 2 2
CPU_DRAMRST# P1 N1 K1
RESET_N VSS3 2 2 VSS2 1 1
CPU_DRAMRST#

CD152

CD156

CD147
T1 P1 N1
VSS4 RESET_N VSS3 2 2
0.1u_0201_10V6K

CD150

CD151

@ F1 B2 T1
VSSQ1 VSS5 2 2 VSS4
0.1u_0201_10V6K

CD154

CD155
1 H1 G8 @ F1 B2
VSSQ2 VSS6 VSSQ1 VSS5 2 2
CD115

CD149

A2 E9 CD@ 1 H1 G8
VSSQ3 VSS7 VSSQ2 VSS6

CD116

CD153
D2 K9 A2 E9 CD@
E3 VSSQ4 VSS8 M9 D2 VSSQ3 VSS7 K9
2 VSSQ5 VSS9 VSSQ4 VSS8
CD107

A8 E3 M9
VSSQ6 2 VSSQ5 VSS9
CD108

D8 T7 A8
E8 VSSQ7 NC D8 VSSQ6 T7
C9 VSSQ8 E8 VSSQ7 NC
H9 VSSQ9 C9 VSSQ8 +0.6VS +0.6VS
VSSQ10 VSSQ9 (1uF_0402_6.3V) *8 (1OuF_0603_6.3V) *2
H9 Place 2 near each DRAM Place around the DRAMs
F9 VSSQ10
ZQ F9
ZQ
1

10U_0603_6.3V6M

10U_0603_6.3V6M
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
RD43 MT40A512M16HA083EA_FBGA96
240_0402_1% RD44 MT40A512M16HA083EA_FBGA96 1 1 1 1 1 1 1 1 1 1 1 1
240_0402_1% CD168 CD169
A A
22P_0402_50V8-J 22P_0402_50V8-J
2

RF@ RF@
2

2 2 2 2 2 2 2 2 2 2 2 2

CD158

CD159

CD160

CD161

CD162

CD163

CD164

CD165

CD166

CD167
CD@ CD@ CD@

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 DDR4 Memory Down
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG411
Date: Thursday, January 14, 2016 Sheet 17 of 60
5 4 3 2 1
 5 4 3 2 1

+1.2V

DDR4 SO-DIMM DDRB_DQ[0..63]

DDRB_DQ[0..63] 6

1
DDRB_DQS#[0..7] RD91
DDRB_DQS#[0..7] 6
+1.2V +1.2V +1.2V +1.2V +1.2V +1.2V +1.2V +1.2V 240_0402_1%
JDDR1A DDRB_DQS[0..7] JDDR1B @
DDRB_DQS[0..7] 6

2
1 2 DDRB_MA3 131 132 DDRB_MA2
DDRB_DQ12 VSS_1 VSS_2 DDRB_DQ9 6 DDRB_MA3 DDRB_MA1 A3 A2 DDRB_EVENT# DDRB_MA2 6
3 4 133 134
DQ5 DQ4 6 DDRB_MA1 A1 EVENT_n
5 6 135 136
DDRB_DQ13 7 VSS_3 VSS_4 8 DDRB_DQ8 DDRB_CLK0 137 VDD_9 VDD_10 138 DDRB_CLK1
DQ1 DQ0 6 DDRB_CLK0 DDRB_CLK0# CK0_t CK1_t DDRB_CLK1# DDRB_CLK1 6
9 10 139 140
DDRB_DQS#1 VSS_5 VSS_6 6 DDRB_CLK0# CK0_c CK1_c DDRB_CLK1# 6
11 12 141 142
DDRB_DQS1 13 DQS0_C DM0_n/DBIO_n/NC 14 DDRB_PAR 143 VDD_11 VDD_12 144 DDRB_MA0
DQS0_t VSS_7 DDRB_DQ11 6 DDRB_PAR Parity A0 DDRB_MA0 6
15 16
DDRB_DQ10 17 VSS_8 DQ6 18
19 DQ7 VSS_9 20 DDRB_DQ15 DDRB_BS1# 145 146 DDRB_MA10
D D
DDRB_DQ14 VSS_10 DQ2 6 DDRB_BS1# BA1 A10/AP DDRB_MA10 6
21 22 147 148
23 DQ3 VSS_11 24 DDRB_DQ5 DDRB_CS0# 149 VDD_13 VDD_14 150 DDRB_BS0#
DDRB_DQ0 VSS_12 DQ12 6 DDRB_CS0# DDRB_MA14_WE# CS0_n BA0 DDRB_MA16_RAS# DDRB_BS0# 6
25 26 151 152
DQ13 VSS_13 DDRB_DQ4 6 DDRB_MA14_WE# WE_n/A14 RAS_n/A16 DDRB_MA16_RAS# 6
27 28 153 154
DDRB_DQ6 29 VSS_14 DQ8 30 DDRB_ODT0 155 VDD_15 VDD_16 156 DDRB_MA15_CAS#
DQ9 VSS_15 DDRB_DQS#0 6 DDRB_ODT0 DDRB_CS1# ODT0 CAS_n/A15 DDRB_MA13 DDRB_MA15_CAS# 6
31 32 157 158
VSS_16 DQS1_c DDRB_DQS0 6 DDRB_CS1# CS1_n A13 DDRB_MA13 6
33 34 159 160
35 DM1_n/DBl1_n/NC DQS1_t 36 DDRB_ODT1 161 VDD_17 VDD_18 162
DDRB_DQ7 VSS_17 VSS_18 DDRB_DQ1 6 DDRB_ODT1 ODT1 C0/CS2_n/NC +VREF_CA_DIMM
37 38 163 164
39 DQ15 DQ14 40 165 VDD_19 VREFCA 166 DDRB_SA2
VSS_19 VSS_20 C1/CS3_n/NC SA2

0.1u_0201_10V6K
DDRB_DQ3 DDRB_DQ2

2.2U_0402_6.3V6M
41 42 167 168 @
43 DQ10 DQ11 44 DDRB_DQ32 169 VSS_53 VSS_54 170 DDRB_DQ36
VSS_21 VSS_22 DQ37 DQ36 1 1
DDRB_DQ18 45 46 DDRB_DQ20 171 172
47 DQ21 DQ20 48 DDRB_DQ33 173 VSS_55 VSS_56 174 DDRB_DQ37
DDRB_DQ16 49 VSS_23 VSS_24 50 DDRB_DQ21 175 DQ33 DQ32 176
51 DQ17 DQ16 52 DDRB_DQS#4 177 VSS_57 VSS_58 178 2 2
DDRB_DQS#2 VSS_25 VSS_26 DDRB_DQS4 DQS4_c DM4_n/DBl4_n/NC

CD1

CD2
53 54 179 180
DDRB_DQS2 55 DQS2_c DM2_n/DBl2_n/NC 56 181 DQS4_t VSS_59 182 DDRB_DQ34
57 DQS2_t VSS_27 58 DDRB_DQ17 DDRB_DQ39 183 VSS_60 DQ39 184
DDRB_DQ22 59 VSS_28 DQ22 60 185 DQ38 VSS_61 186 DDRB_DQ35
61 DQ23 VSS_29 62 DDRB_DQ19 DDRB_DQ38 187 VSS_62 DQ35 188
DDRB_DQ23 63 VSS_30 DQ18 64 189 DQ34 VSS_63 190 DDRB_DQ45
65 DQ19 VSS_31 66 DDRB_DQ24 DDRB_DQ41 191 VSS_64 DQ45 192
DDRB_DQ27 67 VSS_32 DQ28 68 193 DQ44 VSS_65 194 DDRB_DQ44
69 DQ29 VSS_33 70 DDRB_DQ29 DDRB_DQ40 195 VSS_66 DQ41 196
DDRB_DQ28 71 VSS_34 DQ24 72 197 DQ40 VSS_67 198 DDRB_DQS#5
73 DQ25 VSS_35 74 DDRB_DQS#3 199 VSS_68 DQS5_c 200 DDRB_DQS5
+1.2V 75 VSS_36 DQS3_c 76 DDRB_DQS3 201 DM5_n/DBl5_n/NC DQS5_t 202
77 DM3_n/DBl3_n/NC DQS3_t 78 DDRB_DQ47 203 VSS_69 VSS_70 204 DDRB_DQ46
DDRB_DQ25 79 VSS_37 VSS_38 80 DDRB_DQ26 205 DQ46 DQ47 206
81 DQ30 DQ31 82 DDRB_DQ43 207 VSS_71 VSS_72 208 DDRB_DQ42
DDRB_DQ30 83 VSS_39 VSS_40 84 DDRB_DQ31 209 DQ42 DQ43 210
DQ26 DQ27 VSS_73 VSS_74
1

85 86 DDRB_DQ53 211 212 DDRB_DQ52

RD92 RD93 87 VSS_41 VSS_42 88 213 DQ52 DQ53 214
240_0402_1% 240_0402_1% 89 CB5/NC CB4/NC 90 DDRB_DQ48 215 VSS_75 VSS_76 216 DDRB_DQ49
91 VSS_43 VSS_44 92 217 DQ49 DQ48 218
93 CB1/NC CB0/NC 94 DDRB_DQS#6 219 VSS_77 VSS_78 220
2

DDRB_DQS#8 95 VSS_45 VSS_46 96 DDRB_DQS6 221 DQS6_c DM6_n/DBl6_n/NC 222

DDRB_DQS8 97 DQS8_c DM8_n/DBI8_n/NC 98 223 DQS6_t VSS_79 224 DDRB_DQ55
99 DQS8_t VSS_47 100 DDRB_DQ54 225 VSS_80 DQ54 226
C
101 VSS_48 CB6/NC 102 227 DQ55 VSS_81 228 DDRB_DQ51 C
103 CB2/NC VSS_49 104 DDRB_DQ50 229 VSS_82 DQ50 230
105 VSS_50 CB7/NC 106 231 DQ51 VSS_83 232 DDRB_DQ56
107 CB3/NC VSS_51 108 CPU_DRAMRST# DDRB_DQ60 233 VSS_84 DQ60 234
DDRB_CKE0 VSS_52 RESET_n DDRB_CKE1 CPU_DRAMRST# 6,17 DQ61 VSS_85 DDRB_DQ61
109 110 235 236
6 DDRB_CKE0 CKE0 CKE1 DDRB_CKE1 6 DDRB_DQ57 VSS_86 DQ57
111 112 1 237 238
DDRB_BG1 113 VDD_1 VDD_2 114 DDRB_ACT# CD3 239 DQ56 VSS_87 240 DDRB_DQS#7
6 DDRB_BG1 DDRB_BG0 BG1 ACT_n DDRB_ALERT# DDRB_ACT# 6 VSS_88 DQS7_c DDRB_DQS7
115 116 0.1u_0201_10V6K 241 242
6 DDRB_BG0 BG0 ALERT_n DDRB_ALERT# 6 DM7_n/DBl7_n/NC DQS7_t
117 118 @ 243 244
DDRB_MA12 119 VDD_3 VDD_4 120 DDRB_MA11 2 DDRB_DQ59 245 VSS_89 VSS_90 246 DDRB_DQ62
6 DDRB_MA12 DDRB_MA9 A12 A11 DDRB_MA7 DDRB_MA11 6 DQ62 DQ63
121 122 247 248
6 DDRB_MA9 A9 A7 DDRB_MA7 6 DDRB_DQ58 VSS_91 VSS_92 DDRB_DQ63
123 124 249 250
DDRB_MA8 125 VDD_5 VDD_6 126 DDRB_MA5 251 DQ58 DQ59 252
6 DDRB_MA8 DDRB_MA6 A8 A5 DDRB_MA4 DDRB_MA5 6 SMB_CLK_S3 VSS_93 VSS_94 SMB_DATA_S3
127 128 253 254
6 DDRB_MA6 A6 A4 DDRB_MA4 6 7,40 SMB_CLK_S3 +VDD_SPD SCL SDA DDRB_SA0 SMB_DATA_S3 7,40
129 130 +3VS RD1 1 @ 2 255 256
VDD_7 VDD_8 0_0603_5% 257 VDDSPD SA0 258
VPP_1 Vtt +0.6VS
1 1 259 260 DDRB_SA1
VPP_2 SA1
ARGOS_D4AS0-26001-1P60 CD4 CD5 261 262
2.2U_0402_6.3V6M 0.1u_0201_10V6K GND_1 GND_2
ME@ 2 2 ARGOS_D4AS0-26001-1P60
ME@

+2.5V_DDR RD2 1 @ 2 +VPP

0_0603_5%

+1.2V

1
CD117 Note:
1

0.1u_0201_10V6K +0.6VS +2.5V_DDR

2 VREF trace width:20 mils at least Layout Note:
RD3
1K_0402_1% Spacing:20mils to other signal/planes Place near DIMM
Place near DIMM scoket
@
2

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
B 1 1 1 1 1 1 1 1 B
RD4 1 2 +VREF_CA_DIMM
5 DDR_SB_VREFCA
2_0402_5%
1 2 2 2 2 2 2 2 2

CD118
1
1

CD6

CD7

CD8

CD9

CD10

CD11

CD12
CD13
0.022U_0201_6.3V6-K RD5 CD14
2 1K_0402_1% 0.1u_0201_10V6K CD@ CD@
2
1

RD6
24.9_0402_1%

+1.2V
2

@
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1

220U_6.3V_M
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
+

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
CD19

CD20

CD21

CD22

CD23

CD24

CD25

CD26

CD27

CD28

CD29

CD30

CD31

CD32

CD33

CD34

CD35
CD@ CD@ CD@ CD@

+3VS +3VS +3VS

+1.2V
1

RD7 RD8 RD9

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

0_0402_5% 0_0402_5% 0_0402_5%

RF@

RF@

@ @ @
0.1u_0201_10V6K

0.1u_0201_10V6K

33P_0402_50V8J

33P_0402_50V8J
4.7U_0402_6.3V6M

4.7U_0402_6.3V6M
2

1 1 1 1 1 1
DDRB_SA0 DDRB_SA1 DDRB_SA2
A A
2 2 2 2 2 2
CD15

CD16

CD17

CD18

CD36

CD37
1

RD10 RD11 RD12

0_0402_5% 0_0402_5% 0_0402_5%
@ @ @
For EMC
Near JDDRL1
2

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 DDR4 SO-DIMM
SPD Address = 2H THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev

WWW.AliSaler.Com DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG411
Date: Thursday, January 14, 2016 Sheet 18 of 60
5 4 3 2 1
 5 4 3 2 1

N15x GPIO
Performance Mode P0 TDP at Tj = 102 C* (DDR3)
GPIO I/O ACTIVE Function Description
FBVDDQ PCI Express I/O and Other
GPU Mem NVCLK FBVDD (GPU+Mem) (1.05V) PLLVDD
GPIO0 OUT - FB Enable for GC6 2.0 (4) (1,5) /MCLK NVVDD (1.35V) (1.35V) (6) (1.05V) (3.3V)
Products (W) (W) (MHz) (V) (A) (W) (A) (W) (A) (W) (mA) (W) (mA) (W) (mA) (W)
D GPIO1 OUT N/A D

N14X
GPIO2 OUT N/A 128bit TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
2GB
DDR3
GPIO3 OUT N/A

GPIO4 OUT N/A

GPIO5 OUT N/A GPU power sequencing---3V3_MAIN_EN

GPIO6 IN - GPU wake signal for GC6 2.0

GPIO7 OUT N/A

GPIO8 I/O - System side PCIe reset Monitor

GPIO9 I/O N/A 2.2K Pull-up

N15x Multi-level Straps
GPIO10 OUT N/A

GPIO11 OUT - GPU Core VDD PWM control signal

GPIO12 IN AC Power Detect Input (10K pull High)

Physical Logical Logical Logical Logical
GPIO13 OUT - Phase Shedding Strapping pin Power Rail Strapping Bit3 Strapping Bit2 Strapping Bit1 Strapping Bit0
C ROM_SCLK +3VGS SOR3_EXPOSED SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED C
GPIO14 IN N/A
ROM_SI +3VGS RAM_CFG[3] RAM_CFG[2] RAM_CFG[1] RAM_CFG[0]
GPIO15 IN N/A ROM_SO +3VGS DEVID_SEL PCIE_CFG SMB_ALT_ADDR VGA_DEVICE
STRAP0 +3VGS Reserved(keep pull-up and pull-down footprint and stuff 50Kohm pull-up)
GPIO16 N/A
STRAP1 +3VGS
GPIO17 IN N/A STRAP2 +3VGS
Reserved(keep pull-up and pull-down footprint and not stuff by default)
STRAP3 +3VGS
GPIO18 IN N/A
STRAP4 +3VGS
GPIO19 IN N/A

GPIO20 N/A SMBUS_ALT_ADDR

GPIO21 OUT GPU PCIe self-reset control 0 0x9E (Default)

OVERT OUT Active Low Thermal Catastrophic Over Temperature 1 0x9C (Multi-GPU usage)

N15V-GM Power Sequence

B
N15x Binary Straps B

+3VG_AON Other Power rail

+VGA_CORE
+3VG_AON
tNVVDD >0
Physical
Strapping pin Power Rail Strap Mapping
+1.35VGS Tpower-off <10ms ROM_SCLK +3VGS SMB_ALT_ADDR
tFBVDDQ >0
ROM_SI +3VGS SUB_VENDOR
+1.05VS_VGA
ROM_SO +3VGS VGA_DEVICE
tPEX_VDD >0
STRAP0 +3VGS RAM_CFG[0]
1.all GPU power rails should be turned off within 10ms STRAP1 +3VGS RAM_CFG[1]
1. all power rail ramp up time should be larger than 40us 2. Optimus system VDD33 avoids drop down earlier than NVDD and FBVDDQ
STRAP2 +3VGS RAM_CFG[2]
STRAP3 +3VGS RAM_CFG[3]
STRAP4 +3VGS PCIE_MAX_SPEED
N15S-GT Power Sequence

+3VG_AON

+VGA_CORE
A A

tNVVDD >0
+1.05VS_VGA

+1.35VGS
tPEX_VDD >0

Security Classification LC Future Center Secret Data Title

1. all power rail ramp up time should be larger than 40us Issued Date 2015/08/20 Deciphered Date 2016/08/20 VGA Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG411
Date: Thursday, January 14, 2016 Sheet 19 of 60
5 4 3 2 1
 5 4 3 2 1

+3VG_AON
9 PCIE_CRX_GTX_N[0..3]

9 PCIE_CRX_GTX_P[0..3]

2
RV41
9 PCIE_CTX_C_GRX_N[0..3]
10K_0402_5%
@
9 PCIE_CTX_C_GRX_P[0..3]
+3VG_AON

1
1
CV24

2
UV1A 0.1u_0201_10V6K
RV45 @

2
Part 1 of 6 10K_0402_5% 2

G
PCIE_CTX_C_GRX_P0 AG6 C6 FB_GC6_EN @
D PCIE_CTX_C_GRX_N0 PEX_RX0 GPIO0 FB_GC6_EN 24 D
AG7 B2

1
PCIE_CTX_C_GRX_P1 AF7 PEX_RX0_N GPIO1 D6
+3VG_AON +3VG_AON PCIE_CTX_C_GRX_N1 AE7 PEX_RX1 GPIO2 C7 FB_GC6_EN 3 1 FB_GC6_EN_R
PEX_RX1_N GPIO3 FB_GC6_EN_R 8

D
PCIE_CTX_C_GRX_P2 AE9 F9
PCIE_CTX_C_GRX_N2 AF9 PEX_RX2 GPIO4 A3 3VGS_PWR_EN QV6
PEX_RX2_N GPIO5 3VGS_PWR_EN 22,58

2
PCIE_CTX_C_GRX_P3 AG9 A4 GPU_EVENT#_R 2N7002KW_SOT323-3
PEX_RX3 GPIO6
2

PCIE_CTX_C_GRX_N3 AG10 B6 RV47 @

RV3 RV5 AF10 PEX_RX3_N GPIO7 E9 SYS_PEX_RST_MON# 10K_0402_5%
NC81 GPIO8
2.2K_0402_5% 2.2K_0402_5% 5 AE10 F8 VGA_ALERT# @
G
@ @ QV1B AE12 NC82 GPIO9 C5 RV49 2 GC6@ 1 0_0402_5%

1
2N7002KDWH_SOT363-6 AF12 NC83 GPIO10 E7 NVVDD_PWM_VID RB751V-40_SOD323-2
NVVDD_PWM_VID 58
1

@ AG12 NC84 GPIO11 D7 VGA_AC_DET_R 2 1

VGA_SMB_CK2 NC85 GPIO12 PSI_VGA_R VGA_AC_DET 44
4 3 AG13 B4 DV1 @
S

GPIO
EC_SMB_CK2 7,39,44 NC86 GPIO13
D

AF13 B3
AE13 NC87 GPIO14 C3 RV6 1 @ 2 0_0402_5%
NC88 GPIO15 PSI_VGA 58
AE15 D5
RV7 2 OPT@ 1 0_0402_5% AF15 NC1 GPIO16 D4
NC2 GPIO17
2

AG15 C2
G

QV1A AG16 NC3 GPIO18 F7 +3VG_AON +3VG_AON

2N7002KDWH_SOT363-6 AF16 NC4 GPIO19 E6
@ AE16 NC5 GPIO20 C4 GPU_PEX_RST_HOLD#
VGA_SMB_DA2 1 6 AE18 NC6 GPIO21
S

EC_SMB_DA2 7,39,44 NC7

2
D

AF18 A6 OVERT# 1
AG18 NC8 OVERT AB6 RV13 CV12
AG19 NC9 NC33 10K_0402_5% 0.1u_0201_10V6K
NC10

2
RV9 2 OPT@ 1 0_0402_5% AF19 @ @

G
AE19 NC11 2
PU AT EC SIDE, +3VS AND 4.7K

1
AE21 NC12 AG3
AF21 NC13 NC97 AF4
AG21 NC14 NC98 AF3 GPU_EVENT#_R 3 1 GPU_EVENT#
NC15 NC99 GPU_EVENT# 8

D
AG22
NC16 QV4
2N7002KW_SOT323-3
PCIE_CRX_GTX_P0 OPT@ CV10 1 2 0.22U_0201_6.3V6-K PCIE_CRX_C_GTX_P0 AC9 AE3 @
PEX_TX0 NC100

DACs
+3VS PCIE_CRX_GTX_N0 OPT@ CV13 1 2 0.22U_0201_6.3V6-K PCIE_CRX_C_GTX_N0 AB9 AE4
PCIE_CRX_GTX_P1 OPT@ CV8 1 2 0.22U_0201_6.3V6-K PCIE_CRX_C_GTX_P1 AB10 PEX_TX0_N NC101
RV10 2 @ 1 PCIE_CRX_GTX_N1 OPT@ CV9 1 2 0.22U_0201_6.3V6-K PCIE_CRX_C_GTX_N1 AC10 PEX_TX1 RV15 1 GC6@ 2 0_0402_5%
PCIE_CRX_GTX_P2 PCIE_CRX_C_GTX_P2 PEX_TX1_N

PCI EXPRESS
C 0_0402_5% OPT@ CV6 1 2 0.22U_0201_6.3V6-K AD11 C
+3VG_AON PCIE_CRX_GTX_N2 OPT@ CV7 1 2 0.22U_0201_6.3V6-K PCIE_CRX_C_GTX_N2 AC11 PEX_TX2 W5
PCIE_CRX_GTX_P3 OPT@ CV4 1 2 0.22U_0201_6.3V6-K PCIE_CRX_C_GTX_P3 AC12 PEX_TX2_N NC102 AE2
+3VGARST RV12 1 @ 2 PCIE_CRX_GTX_N3 OPT@ CV5 1 2 0.22U_0201_6.3V6-K PCIE_CRX_C_GTX_N3 AB12 PEX_TX3 NC103 AF2
0_0402_5% AB13 PEX_TX3_N NC104
AC13 NC89
1 NC90
CV11 AD14 PLT_RST_VGA# RV174 1 @ 2
0.1u_0201_10V6K AC14 NC91 1K_0402_5%
NC92 1
UV2 OPT@ AC15 CV218
2 AB15 NC93 0.1u_0201_10V6K
NC94

2
PLT_RST# 1 5 AB16 B7 VGA_CRT_CLK @

G
11,32,37,40,44 PLT_RST# A VCC NC95 I2CA_SCL 2
AC16 A7 VGA_CRT_DATA
2 AD17 NC96 I2CA_SDA
8 PXS_RST# B NC17 I2CB_SCL
I2C,if not use, can be soft grounded
AC17 C9
3 4 SYS_PEX_RST_MON# AC18 NC18 I2CB_SCL C8 I2CB_SDA and delete pull up resistor OVERT# 3 1
GND Y NC19 I2CB_SDA ---colin WRST# 44

I2C

D
AB18
AB19 NC20 A9 I2CC_SCL QV23
NC21 I2CC_SCL 1
74LVC1G08SE-7_SOT353-5 AC19 B9 I2CC_SDA CV221 2N7002KW_SOT323-3
OPT@ AD20 NC22 I2CC_SDA 0.01U_0201_10V6K @
AC20 NC23 D9 VGA_SMB_CK2 @
RV14 2 OPT@ 1 10K_0402_5% AC21 NC24 I2CS_SCL D8 VGA_SMB_DA2 2
NC25 I2CS_SDA Internal Thermal Sensor
AB21
AD23 NC26
RV16 1 @ 2 0_0402_5% AE23 NC27
AF24 NC28 60mA
AE24 NC29 L6 +PLLVDD
AG24 NC30 CORE_PLLVDD M6 +3VG_AON +3VG_AON
AG25 NC31 SP_PLLVDD
NC32 N6
45mA RV24 1 @ 2 0_0402_5% +SP_PLLVDD
+3VGS +3VG_AON VID_PLLVDD
45mA VGA_CRT_DATA RV17 1 @ 2 2.2K_0402_5% 3VGS_PWR_EN RV18 2 OPT@ 1 10K_0402_5%
CLK_PCIE_GPU AE8
10 CLK_PCIE_GPU CLK_PCIE_GPU# PEX_REFCLK VGA_CRT_CLK
AD8 RV19 1 @ 2 2.2K_0402_5% OVERT# RV20 1 OPT@ 2 10K_0402_5%
10 CLK_PCIE_GPU# PEX_REFCLK_N
2

CLK_REQ_GPU# AC6
RV180 RV37 PEX_CLKREQ_N I2CB_SCL RV22 1 @ 2 2.2K_0402_5% VGA_ALERT# RV23 1 OPT@ 2 10K_0402_5%
2.2K_0402_5% 10K_0402_5% 1 @ 2 RV32 PEX_TSTCLK_OUT AF22

CLK
GC6@ @ 200_0402_1% PEX_TSTCLK_OUT# AE22 PEX_TSTCLK C11 XTAL_IN I2CB_SDA RV25 1 @ 2 2.2K_0402_5% VGA_AC_DET_R RV26 1 OPT@ 2 100K_0402_5%
Differential signal PEX_TSTCLK_N XTAL_IN B10 XTAL_OUT
1

B XTAL_OUT I2CC_SCL RV28 1 @ 2 2.2K_0402_5% PSI_VGA RV29 1 OPT@ 2 10K_0402_5% B

DV6 PLT_RST_VGA# AC7 A10 XTALSSIN 1 OPT@ 2 RV34 10K_0402_5%
GPU_PEX_RST_HOLD# 2 RV35 1 OPT@ 2 PEX_TERMP AF25 PEX_RST_N XTAL_SSIN C10 XTALOUT 1 OPT@ 2 RV36 10K_0402_5% I2CC_SDA RV30 1 @ 2 2.2K_0402_5% GPU_PEX_RST_HOLD# RV31 1 OPT@ 2 10K_0402_5%
1 PLT_RST_VGA# 2.49K_0402_1% PEX_TERMP XTAL_OUTBUFF
SYS_PEX_RST_MON# 3
N15S-GT-S-A2_FCBGA595 XTALOUT RV33 1 @ 2 10K_0402_5%
BAT54AW_SOT323-3 @
GC6@

RV39 1 NGC6@ 2 0_0402_5%

Under GPU(below 150mils)

180ohms (ESR=0.2) Bead
+SP_PLLVDD 1 @ 2 LV1 +1.05VGS
0_0603_5%

OPT@

OPT@

OPT@

OPT@
RV38 1 OPT@ 2 10M_0402_5%

0.1u_0201_10V6K

0.1u_0201_10V6K

22U_0603_6.3V6-M
4.7U_0402_6.3V6M
150mA
1 1 1 1
+3VG_AON YV1

XTAL_IN 2 2 2 2

CV15

CV16

CV17

CV18
1 4
OSC1 GND2
2

RV40 2 3 XTAL_OUT
10K_0402_5% GND1 OSC2
@ 1 1
CV19 27MHZ_10PF_7V27000050 CV20
1

10P_0201_25V8G OPT@ 10P_0201_25V8G

+3VG_AON OPT@ OPT@ Under GPU Near GPU 30ohms (ESR=0.05) Bead
2 2
1
CV23 +PLLVDD 1 @ 2 LV2 +1.05VGS
2

0.1u_0201_10V6K 0_0603_5%

OPT@

OPT@
@ RV44

0.1u_0201_10V6K

22U_0603_6.3V6-M
2

2 10K_0402_5% 1 1
G

@
1

A A
CLK_REQ_GPU# 2 2

CV21

CV22
10 GPU_CLKREQ# 1 3
D

QV5
2

2N7002KW_SOT323-3
@ RV46
10K_0402_5%
@
RV48 1 OPT@ 2
1

0_0402_5%
Security Classification LC Future Center Secret Data Title
Issued Date 2015/08/20 Deciphered Date 2016/08/20 N16X_PCIE/ DAC/ GPIO
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG411
Date: Thursday, January 14, 2016 Sheet 20 of 60
5 4 3 2 1

WWW.AliSaler.Com
 5 4 3 2 1

D D
UV1C

Part 3 of 6 F11
AC3 NC50 AD10
AC4 NC105 NC51 AD7
Y4 NC106 NC52
Y3 NC107 V5
AA3 NC108 FERMI_RSVD1 V6
AA2 NC109 FERMI_RSVD2 G1
AB1 NC110 NC56 G2
NC111 NC57

NC
AA1 G3
AA4 NC112 NC58 G4
AA5 NC113 NC59 G5
NC114 NC60 G6
NC61 G7
AB5 NC62 V1
AB4 NC115 NC63 V2
AB3 NC116 NC64 W1
AB2 NC117 NC65 W2
AD3 NC118 NC66 W3
AD2 NC119 NC67 W4
AE1 NC120 NC68
AD1 NC121
AD4 NC122
AD5 NC123
NC124 D11 RV50 2 @ 1 10K_0402_5%
BUFRST_N

LVDS/TMDS
T2
T3 NC125 D10
T1 NC126 PGOOD
R1 NC127 E10
NC128 NC71

GENERAL
R2
R3 NC129 F10
N2 NC130 NC72
N3 NC131 +3VG_AON
NC132 D1 STRAP0
STRAP0 STRAP0 29
C D2 STRAP1 C
STRAP1 STRAP1 29

1
V3 E4 STRAP2
NC133 STRAP2 STRAP2 29
V4 E3 STRAP3 RV181
NC134 STRAP3 STRAP3 29
U3 D3 STRAP4 10K_0402_5%
NC135 STRAP4 STRAP4 29
U4 C1 @
T4 NC136 NC73

2
T5 NC137
R4 NC138 F6 MULTI_STRAP_REF0_GND
R5 NC139 MULTI_STRAP_REF0_GND F4
NC140 MULTI_STRAP_REF1_GNDMLS_REF1 F5
MULTI_STRAP_REF2_GND

1
N1 RV51
M1 NC34 40.2K_0402_1%
M2 NC35 F12 OPT@
M3 NC36 THERMDP

2
K2 NC37 E12
K3 NC38 THERMDN
K1 NC39
J1 NC40
NC41

M4 F2 VCCSENSE_VGA
NC42 VDD_SENSE VCCSENSE_VGA 58
M5
L3 NC43
NC44 trace width: 16mils
L4 differential voltage sensing.
K4 NC45
NC46 differential signal routing.
K5
J4 NC47 F1 VSSSENSE_VGA
NC48 GND_SENSE VSSSENSE_VGA 58

J5
N4 NC49
N5 NC141 TEST
NC142
P3 AD9 TESTMODE RV52 1 OPT@ 2 10K_0402_5%
P4 NC143 TESTMODE AE5 @ 1
B NC144 JTAG_TCK TV1 B
AE6 @ 1
JTAG_TDI TV2
AF6 @ 1
JTAG_TDO TV3
J2 AD6 @ 1
NC145 JTAG_TMS TV4
J3 AG4 RV53 1 OPT@ 2 10K_0402_5%
NC146 JTAG_TRST_N

H3
H4 NC147
NC148 SERIAL
D12 @ 1
ROM_CS_N ROM_SI TV5
B12
ROM_SI ROM_SO ROM_SI 29
A12
ROM_SO ROM_SCLK ROM_SO 29
C12
ROM_SCLK ROM_SCLK 29

N15S-GT-S-A2_FCBGA595
@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 N16X_LVDS/ HDMI/ THERM
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG411
Date: Thursday, January 14, 2016 Sheet 21 of 60
5 4 3 2 1
 5 4 3 2 1

PEX_IOVVDD/Q Decouling

UV1D Under GPU Near GPU

MLCC Q'ty
+1.35VGS Near GPU Under GPU(below 150mils)
2000mA (below 150mils) +1.05VGS
3.5A Part 4 of 6
B26 AA10
1.0uF 1
FBVDDQ_01 PEX_IOVDDQ_1

10U_0603_6.3V6M
C25 AA12

RF_NS@
1U_0402_6.3V6K

4.7U_0402_6.3V6M
FBVDDQ_02 PEX_IOVDDQ_2

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
CD@
22U_0603_6.3V6-M

10U_0603_6.3V6M
E23 AA13

33P_0402_50V8J
4.7U_0402_6.3V6M

4.7U_0402_6.3V6M
FBVDDQ_03 PEX_IOVDDQ_3 4.7uF 1

CD@

0.1u_0201_10V6K

0.1u_0201_10V6K
E26 AA16

1U_0402_6.3V6K

1U_0402_6.3V6K
FBVDDQ_04 PEX_IOVDDQ_4 1 1 2 1
1 2 1 1 1 1 1 1 F14 AA18
F21 FBVDDQ_05 PEX_IOVDDQ_5 AA19
FBVDDQ_06 PEX_IOVDDQ_6 For RF 10uF 1

CV33

CV37

CV39

CV215
G13 AA20
G14 FBVDDQ_07 PEX_IOVDDQ_7 AA21 2 2 1 2
2 1 2 2 2 2 2 2 FBVDDQ_08 PEX_IOVDDQ_8

CV25

CV26

CV27

CV28

CV29

CV30

CV31

CV32
G15 AB22
G16 FBVDDQ_09 PEX_IOVDDQ_9 AC23
22uF 1
D
G18 FBVDDQ_10 PEX_IOVDDQ_10 AD24 D
G19 FBVDDQ_11 PEX_IOVDDQ_11 AE25
FBVDDQ_12 PEX_IOVDDQ_12 +1.05VGS
G20 AF26

22U_0603_6.3V6-M
+3VG_AON
G21 FBVDDQ_13 PEX_IOVDDQ_13 AF27
FBVDDQ_14 PEX_IOVDDQ_14 Under Near

OPT@
L22
L24 FBVDDQ_19

4.7U_0402_6.3V6M
FBVDDQ_20 1

OPT@

OPT@

OPT@
0.1u_0201_10V6K
L26 AA22

1U_0402_6.3V6K
M21 FBVDDQ_21 PEX_IOVDD_1 AB23
FBVDDQ_22 PEX_IOVDD_2 1 1 1

CV43
N21 AC24
R21 FBVDDQ_23 PEX_IOVDD_3 AD25 2

POWER
FBVDDQ_24 PEX_IOVDD_4

CV47

CV48

CV49
T21 AE26
V21 FBVDDQ_25 PEX_IOVDD_5 AE27 2 2 2
W21 FBVDDQ_26 PEX_IOVDD_6
FBVDDQ_27

H24
H26 FBVDDQ_AON_1
J21 FBVDDQ_AON_2 G10
FBVDDQ_AON_3 3V3_AON_1 +3VG_AON
K21 G12 Near balls
FBVDDQ_AON_4 3V3_AON_2
(Under GPU) Near GPU
V7 G8 +VDD33 RV54 1 @ 2 0_0402_5% +3VGS
NC149 3V3_MAIN_1 G9
3V3_MAIN_2

OPT@

OPT@

OPT@

OPT@
0.1u_0201_10V6K

0.1u_0201_10V6K
+1.35VGS

1U_0402_6.3V6K

4.7U_0402_6.3V6M
W7 1 1 1 1
AA6 NC150
W6 NC151 D22 RV55 1 OPT@ 2 40.2_0402_1%
Y6 NC152 FB_CAL_VDDQ
NC153 2 2 2 2

CV50

CV51

CV52

CV53
C24 RV56 1 OPT@ 2 42.2_0402_1%
CALIBRATION PIN DDR3
FB_CAL_GND

M7 B25 RV57 1 OPT@ 2 51.1_0402_1%

FB_CAL_x_PD_VDDQ 40.2Ohm
N7 NC154 FB_CAL_TERM
T6 NC155
NC156 Place near balls FB_CAL_x_PU_GND 42.2Ohm
P6
NC157
C
Under GPU(below 150mils)
FB_CAL_xTERM_GND 51.1Ohm C

T7 +3VG_AON
NC158

0.1u_0201_10V6K
R7

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M
NC159

OPT@

OPT@

OPT@
U6
R6 NC160 AA8
NC161 PEX_PLL_HVDD_1 1 1 1
AA9
PEX_PLL_HVDD_2

CV55

CV56

CV57
AB8
PEX_SVDD_3V3 2 2 2

J7 120ohm (ESR=0.18) Bead

K7 NC76 120mA
K6 NC77 AA14 +PEX_PLLVDD @ 2 1 LV3
NC78 PEX_PLLVDD_1 +1.05VGS

0.1u_0201_10V6K
H6 AA15 HCB1608KF-121T30_0603

1U_0402_6.3V6K

4.7U_0402_6.3V6M
NC79 PEX_PLLVDD_2

OPT@

OPT@

OPT@
J6
NC80
1 1 1
RV62 1 @ 2 0_0603_5%

CV58

CV59

CV60
2 2 2
N15S-GT-S-A2_FCBGA595
@

Near balls

+3.3VS TO +3VG_AON
+1.35VGS
+3VS +3VG_AON

LP2301ALT1G_SOT23-3 +5VALW
+5VALW

1
S

3 1
QV11 OPT@ RV67
1

1
470_0603_5%
1

B B
RV63 RV69 @
G

1 1 1
2

47K_0402_5% CV61 CV62 RV64 CV63 47K_0402_5%

2
OPT@ 0.1u_0201_10V6K 0.01U_0201_10V6K 470_0603_5% 10U_0603_6.3V6M @
@ @ @ OPT@
2

1
2 2 2 D
2

PXS_PWREN# OPT@ 1 2 RV65 FBVDDQ_PWR_EN# 2 QV15

10K_0402_5% G 2N7002KW_SOT323-3
1 @
1

D CV64 S

3
1

1
2 QV12 0.1u_0201_10V6K D D
8,58 PXS_PWREN G PXS_PWREN#
2N7002KW_SOT323-3 OPT@ 2 QV13 2 QV18
2 G 24,57 FBVDDQ_PWR_EN G
OPT@ 2N7002KW_SOT323-3 2N7002KW_SOT323-3
1

S @ @
3

RV66 S S
3

3
100K_0402_5%
OPT@
2

+1.05VGS

+5VALW
+3VG_AON +3VGS
+3.3VS TO +3VGS

1
RV59

1
RV171 1 2 NGC6@ 470_0603_5%
0_0603_5% RV60 @
47K_0402_5%

2
@
LP2301ALT1G_SOT23-3

2
+5VALW

1
S

QV16 3 1 GC6@ D
1.05VGS_EN# 2 QV10
1

G 2N7002KW_SOT323-3
1

RV71 @
G

1 1 1
2

1
47K_0402_5% CV72 CV73 RV72 CV74 D S

3
A GC6@ 0.1u_0201_10V6K 0.01U_0201_10V6K 470_0603_5% 10U_0603_6.3V6M 2 QV9 A
23,57,58 EN_VGA G
@ GC6@ @ GC6@ 2N7002KW_SOT323-3
2

2 2 2 @
2

DGPU_PWR_EN# GC6@ 1 2 RV73 S

3
4.7K_0402_5%
1
1

D CV75
1

2 QV19 0.1u_0201_10V6K D
20,58 3VGS_PWR_EN G DGPU_PWR_EN#
2N7002KW_SOT323-3 GC6@ 2 QV20
GC6@ 2 G 2N7002KW_SOT323-3
1

S @
Security Classification LC Future Center Secret Data Title
3

RV74 S
3

100K_0402_5%
GC6@
Issued Date 2015/08/20 Deciphered Date 2016/08/20 N16X_Power
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG411
WWW.AliSaler.Com 5 4 3 2
Date: Thursday, January 14, 2016
1
Sheet 22 of 60
 5 4 3 2 1

D D

UV1E
UV1F
A2 Part 5 of 6 K11 +VGA_CORE +VGA_CORE
A26 GND_001 GND_057 K13 Part 6 of 6
AB11 GND_002 GND_058 K15
AB14 GND_003 GND_059 K17 K10 V18
AB17 GND_004 GND_060 L10 K12 VDD_001 VDD_041 V16
AB20 GND_005 GND_061 L12 +VGA_CORE K14 VDD_002 VDD_040 V14
AB24 GND_006 GND_062 L14 K16 VDD_003 VDD_039 V12
GND_007 GND_063 Under GPU VDD_004 VDD_038
AC2 L16 K18 V10
AC22 GND_008 GND_064 L18 L11 VDD_005 VDD_037 U17

POWER
AC26 GND_009 GND_065 L2 L13 VDD_006 VDD_036 U15
GND_010 GND_066 VDD_007 VDD_035

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

@
CD@
AC5 L23 L15 U13

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M
AC8 GND_011 GND_067 L25 L17 VDD_008 VDD_034 U11
GND_012 GND_068 1 1 1 1 1 1 1 1 1 1 1 1 1 VDD_009 VDD_033
AD12 L5 M10 T18
AD13 GND_013 GND_069 M11 M12 VDD_010 VDD_032 T16
AD15 GND_014 GND_070 M13 M14 VDD_011 VDD_031 T14
GND_015 GND_071 2 2 2 2 2 2 2 2 2 2 2 2 2 VDD_012 VDD_030

CV76

CV77

CV78

CV79

CV80

CV81

CV82

CV83

CV84

CV85

CV86

CV87

CV88
AD16 M15 M16 T12
AD18 GND_016 GND_072 M17 M18 VDD_013 VDD_029 T10
AD19 GND_017 GND_073 N10 N11 VDD_014 VDD_028 R17
AD21 GND_018 GND_074 N12 N13 VDD_015 VDD_027 R15
AD22 GND_019 GND_075 N14 N15 VDD_016 VDD_026 R13
AE11 GND_020 GND_076 N16 N17 VDD_017 VDD_025 R11
GND_021 GND_077 VDD_018 VDD_024

OPT@

OPT@

OPT@

OPT@
AE14 N18 P10 P18

RF_NS@
AE17 GND_022 GND_078 P11 P12 VDD_019 VDD_023 P16

33P_0402_50V8J
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
AE20 GND_023 GND_079 P13 VDD_020 VDD_022 P14
GND_024 GND_080 1 1 1 1 1 VDD_021
AF1 P15
GND_025 GND_081
GND

AF11 P17 For RF

AF14 GND_026 GND_082 P2
GND_027 GND_083 2 2 2 2 2

CV89

CV90

CV91

CV92

CV213
AF17 P23
AF20 GND_028 GND_084 P26
C C
AF23 GND_029 GND_085 P5
AF5 GND_030 GND_086 R10
AF8 GND_031 GND_087 R12
AG2 GND_032 GND_088 R14
AG26 GND_033 GND_089 R16 N15S-GT-S-A2_FCBGA595
B1 GND_034 GND_090 R18
GND_035 GND_091 @
B11 T11
GND_036 GND_092

OPT@

OPT@

OPT@

@
CD@

CD@
B14 T13

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M
B17 GND_037 GND_093 T15
GND_038 GND_094 1 1 1 1 1 1 1 1 1 1
B20 T17
B23 GND_039 GND_095 U10
B27 GND_040 GND_096 U12
GND_041 GND_097 2 2 2 2 2 2 2 2 2 2

CV93

CV94

CV95

CV96

CV97

CV98

CV99

CV100

CV101

CV102
B5 U14
B8 GND_042 GND_098 U16
E11 GND_043 GND_099 U18
E14 GND_044 GND_100 U2
E17 GND_045 GND_101 U23
E2 GND_046 GND_102 U26
GND_047 GND_103
OPT@

OPT@

CD@
E20 U5

RF_NS@
E22 GND_048 GND_104 V11
22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

33P_0402_50V8J
E25 GND_049 GND_105 V13
GND_050 GND_106 1 1 1 1
E5 V15
E8 GND_051 GND_107 V17
GND_052 GND_108 For RF
H2 Y2
GND_053 GND_109 2 2 2 2
CV103

CV104

CV105

CV214
H23 Y23
H25 GND_054 GND_110 Y26
H5 GND_055 GND_111 Y5
GND_056 GND_112

AA7
GND_113 AB7
GND_114 Near GPU

N15S-GT-S-A2_FCBGA595
B B
@

+VGA_CORE

+5VALW
1
RV173
2

470_0603_5%
RV172 @
47K_0402_5%
2

@
1

D
2 QV22
G 2N7002KW_SOT323-3
1

D @
2 QV21 S
22,57,58 EN_VGA
3

G 2N7002KW_SOT323-3
@
S
3

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 N16X_+VGA CORE, GND
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG411
Date: Thursday, January 14, 2016 Sheet 23 of 60
5 4 3 2 1
 5 4 3 2 1

FBA_D[0..63]
25,26,27,28 FBA_D[0..63]

25,26,27,28 FBA_DQM[7..0]
25,26,27,28 FBA_DQS[7..0]
25,26,27,28 FBA_DQS#[7..0]

25,26,27,28 FBA_CMD[30..0]

UV1B
D D

Part 2 of 6

FBA_D0 E18 C27 FBA_ODT_L +1.35VGS

FBA_D1 FBA_D00 FBA_CMD00 FBA_CS1#_L FBA_ODT_L 25,27
F18 C26
FBA_D2 FBA_D01 FBA_CMD01 FBA_CS0#_L FBA_CS1#_L 27
E16 E24
FBA_D3 FBA_D02 FBA_CMD02 FBA_CKE_L FBA_CS0#_L 25
F17 F24
FBA_D4 FBA_D03 FBA_CMD03 FBA_CMD4 FBA_CKE_L 25,27
D20 D27
FBA_D5 D21 FBA_D04
FBA_D05
FBA_CMD04
FBA_CMD05
D26 FBA_CMD5 CMD mapping mod Mode E
FBA_D6 FBA_CMD6 FBA_CMD4

0.1u_0201_10V6K
F20 F25 RV75 1 OPT@ 2 100_0402_5% @
FBA_D7 E21 FBA_D06 FBA_CMD06 F26 FBA_CMD7 RV76 1 OPT@ 2 100_0402_5%
FBA_D07 FBA_CMD07 1 Rank0 Rank1
FBA_D8 E15 F23 FBA_CMD8
FBA_D9 D15 FBA_D08 FBA_CMD08 G22 FBA_CMD9 FBA_CMD5 RV77 1 OPT@ 2 100_0402_5%
FBA_D09 FBA_CMD09
Address 0..31 32..63 0..31 32..63
FBA_D10 F15 G23 FBA_CMD10 RV78 1 OPT@ 2 100_0402_5%
FBA_D11 FBA_D10 FBA_CMD10 FBA_RAS# 2

CV106
F13 G24 FBx_CMD0 ODT_L ODT_L
FBA_D12 FBA_D11 FBA_CMD11 FBA_CMD12 FBA_RAS# 25,26,27,28 FBA_CMD6
C13 F27 RV79 1 OPT@ 2 100_0402_5%
FBA_D13 B13 FBA_D12 FBA_CMD12 G25 FBA_CMD13 RV80 1 OPT@ 2 100_0402_5%
FBA_D13 FBA_CMD13 FBx_CMD1 CS1#_L
FBA_D14 E13 G27 FBA_CMD14
FBA_D15 D13 FBA_D14 FBA_CMD14 G26 FBA_CAS# FBA_CMD7 RV81 1 OPT@ 2 100_0402_5%
FBA_D15 FBA_CMD15 FBA_CAS# 25,26,27,28 FBx_CMD2 CS0#_L
FBA_D16 FBA_ODT_H

0.1u_0201_10V6K
B15 M24 RV82 1 OPT@ 2 100_0402_5% @
FBA_D17 FBA_D16 FBA_CMD16 FBA_CS1#_H FBA_ODT_H 26,28
C16 M23 1 FBx_CMD3 CKE_L CKE_L
FBA_D18 FBA_D17 FBA_CMD17 FBA_CS0#_H FBA_CS1#_H 28 FBA_CMD8
A13 K24 RV83 1 OPT@ 2 100_0402_5%
FBA_D19 FBA_D18 FBA_CMD18 FBA_CKE_H FBA_CS0#_H 26
A15 K23 RV84 1 OPT@ 2 100_0402_5% FBx_CMD4 A9 A9 A11 A11
FBA_D20 FBA_D19 FBA_CMD19 FBA_RST# FBA_CKE_H 26,28
B18 M27
FBA_D21 FBA_D20 FBA_CMD20 FBA_CMD21 FBA_RST# 25,26,27,28 FBA_CMD9 2

CV107
A18 M26 RV85 1 OPT@ 2 100_0402_5% FBx_CMD5 A6 A6 A7 A7
FBA_D22 A19 FBA_D21 FBA_CMD21 M25 FBA_CMD22 RV86 1 OPT@ 2 100_0402_5%
FBA_D23 C19 FBA_D22 FBA_CMD22 K26 FBA_CMD23
FBA_D23 FBA_CMD23 FBx_CMD6 A3 A3 BA1 BA1
FBA_D24 B24 K22 FBA_CMD24 FBA_CMD10 RV87 1 OPT@ 2 100_0402_5%
FBA_D25 C23 FBA_D24 FBA_CMD24 J23 FBA_CMD25 RV88 1 OPT@ 2 100_0402_5%
FBA_D25 FBA_CMD25 FBx_CMD7 A0 A0 A12 A12
FBA_D26 A25 J25 FBA_CMD26
FBA_D27 A24 FBA_D26 FBA_CMD26 J24 FBA_CMD27 FBA_RAS# RV89 1 OPT@ 2 100_0402_5%
FBA_D27 FBA_CMD27 FBx_CMD8 A8 A8 A8 A8
FBA_D28 FBA_CMD28

0.1u_0201_10V6K
A21 K27 RV90 1 OPT@ 2 100_0402_5% @
FBA_D29 B21 FBA_D28 FBA_CMD28 K25 FBA_CMD29
FBA_D29 FBA_CMD29 1 FBx_CMD9 A12 A12 A0 A0
FBA_D30 C20 J27 FBA_CMD30 FBA_CMD12 RV91 1 OPT@ 2 100_0402_5%
FBA_D31 C21 FBA_D30 FBA_CMD30 J26 RV92 1 OPT@ 2 100_0402_5%
FBA_D31 FBA_CMD31 +1.35VGS
FBx_CMD10 A1 A1 A2 A2
FBA_D32 R22 B19
FBA_D33 FBA_D32 FBA_CMD32 FBA_CMD13 2

CV108
C R24 RV93 1 OPT@ 2 100_0402_5% FBx_CMD11 RAS# RAS# RAS# RAS# C
FBA_D33

INTERFACE A
FBA_D34 T22 F22 RV121 2 @ 1 60.4_0402_1% RV94 1 OPT@ 2 100_0402_5%
FBA_D35 R23 FBA_D34 FBA_CMD34 J22 RV122 2 @ 1 60.4_0402_1%
FBA_D35 FBA_CMD35 FBx_CMD12 A13 A13 A14 A14
FBA_D36 N25 FBA_CMD14 RV95 1 OPT@ 2 100_0402_5%
FBA_D37 N26 FBA_D36 D19 FBA_DQM0 RV96 1 OPT@ 2 100_0402_5% FBx_CMD13 BA1 BA1 A3 A3

MEMORY
FBA_D38 N23 FBA_D37 FBA_DQM0 D14 FBA_DQM1
FBA_D39 N24 FBA_D38 FBA_DQM1 C17 FBA_DQM2 FBA_CAS# RV97 1 OPT@ 2 100_0402_5%
FBA_D39 FBA_DQM2 FBx_CMD14 A14 A14 A13 A13
FBA_D40 FBA_DQM3

0.1u_0201_10V6K
30ohms (ESR=0.01) Bead V23 C22 RV98 1 OPT@ 2 100_0402_5% @
FBA_D41 V22 FBA_D40 FBA_DQM3 P24 FBA_DQM4
+1.05VGS +FB_PLLAVDD FBA_D41 FBA_DQM4 1 FBx_CMD15 CAS# CAS# CAS# CAS#
FBA_D42 T23 W24 FBA_DQM5 FBA_CMD21 RV99 1 OPT@ 2 100_0402_5%
FBA_D43 U22 FBA_D42 FBA_DQM5 AA25 FBA_DQM6 RV100 1 OPT@ 2 100_0402_5%
FBA_D43 FBA_DQM6 FBx_CMD16 ODT_H ODT_H
FBA_D44 Y24 U25 FBA_DQM7
FBA_D45 FBA_D44 FBA_DQM7 FBA_CMD22 2

CV109
LV4 1 2 OPT@ 200mA AA24 RV101 1 OPT@ 2 100_0402_5% FBx_CMD17 CS1#_H
HCB1608KF-300T60_2P FBA_D46 Y22 FBA_D45 F19 FBA_DQS#0 RV102 1 OPT@ 2 100_0402_5%
FBA_D47 AA23 FBA_D46 FBA_DQS_RN0 C14 FBA_DQS#1
FBA_D47 FBA_DQS_RN1 FBx_CMD18 CS0#_H
Place close to BGA FBA_D48 AD27 A16 FBA_DQS#2 FBA_CMD23 RV103 1 OPT@ 2 100_0402_5%
FBA_D49 AB25 FBA_D48 FBA_DQS_RN2 A22 FBA_DQS#3 RV104 1 OPT@ 2 100_0402_5%
FBA_D49 FBA_DQS_RN3 FBx_CMD19 CKE_H CKE_H
FBA_D50 AD26 P25 FBA_DQS#4
FBA_D51 AC25 FBA_D50 FBA_DQS_RN4 W22 FBA_DQS#5 FBA_CMD24 RV105 1 OPT@ 2 100_0402_5%
FBA_D51 FBA_DQS_RN5 FBx_CMD20 RST RST RST RST
FBA_D52 FBA_DQS#6

0.1u_0201_10V6K
AA27 AB27 RV106 1 OPT@ 2 100_0402_5% @
FBA_D53 AA26 FBA_D52 FBA_DQS_RN6 T27 FBA_DQS#7
Place close to BGA Place close to ball FBA_D53 FBA_DQS_RN7 1 FBx_CMD21 A7 A7 A6 A6
FBA_D54 W26 FBA_CMD25 RV107 1 OPT@ 2 100_0402_5%
FBA_D55 Y25 FBA_D54 E19 FBA_DQS0 RV108 1 OPT@ 2 100_0402_5%
+FB_PLLAVDD FBA_D55 FBA_DQS_WP0 FBx_CMD22 A4 A4 A5 A5
FBA_D56 R26 C15 FBA_DQS1
FBA_D56 FBA_DQS_WP1 2
OPT@

OPT@

OPT@

FBA_D57 FBA_DQS2 FBA_CMD26

CV110
0.1u_0201_10V6K

T25 B16 RV109 1 OPT@ 2 100_0402_5%

22U_0603_6.3V6-M

1U_0402_6.3V6K

FBA_D57 FBA_DQS_WP2 FBx_CMD23 A11 A11 A9 A9

1 1 1 FBA_D58 N27 B22 FBA_DQS3 RV110 1 OPT@ 2 100_0402_5%
FBA_D59 R27 FBA_D58 FBA_DQS_WP3 R25 FBA_DQS4
FBA_D59 FBA_DQS_WP4 FBx_CMD24 A2 A2 A1 A1
FBA_D60 V26 W23 FBA_DQS5 FBA_CMD27 RV111 1 OPT@ 2 100_0402_5%
FBA_D61 V27 FBA_D60 FBA_DQS_WP5 AB26 FBA_DQS6 RV112 1 OPT@ 2 100_0402_5%
2 2 2 FBA_D61 FBA_DQS_WP6 FBx_CMD25 A10 A10 WE# WE#
FBA_D62 FBA_DQS7
CV111

CV112

CV113

W27 T26
FBA_D63 W25 FBA_D62 FBA_DQS_WP7 FBA_CMD28 RV113 1 OPT@ 2 100_0402_5%
FBA_D63 FBx_CMD26 A5 A5 A4 A4
FBA_CLK0

0.1u_0201_10V6K
D24 RV114 1 OPT@ 2 100_0402_5% @
FBA_CLK0 FBA_CLK0# FBA_CLK0 25,27
F16 D25 1 FBx_CMD27 BA2 BA2
FB_PLLAVDD_1 FBA_CLK0_N FBA_CLK0# 25,27 FBA_CMD29
P22 RV115 1 OPT@ 2 100_0402_5%
FB_PLLAVDD_2 N22 FBA_CLK1 RV116 1 OPT@ 2 100_0402_5%
FBA_CLK1 FBA_CLK1 26,28 FBx_CMD28 WE# WE# A10 A10
D23 M22 FBA_CLK1#
FB_VREF FBA_CLK1_N FBA_CLK1# 26,28 FBA_CMD30 2

CV114
+FB_PLLAVDD RV117 1 OPT@ 2 100_0402_5% FBx_CMD29 BA0 BA0 BA0 BA0
Place close to ball D18 RV118 1 OPT@ 2 100_0402_5%
B
OPT@ 1 2 CV115 H22 FBA_WCK01 C18 B
FB_DLLAVDD FBA_WCK01_N FBx_CMD30 BA2 BA2
0.1u_0201_10V6K D17
FB_GC6_EN RV119 1 @ 2 0_0402_5% FB_CLAMP F3 FBA_WCK23 D16
RV120 1 OPT@ 2 10K_0402_5% FB_CLAMP FBA_WCK23_N T24
FBA_WCK45 U24
FBA_WCK45_N V24
FBA_WCK67 V25
FBA_WCK67_N

N15S-GT-S-A2_FCBGA595
@

DV4 GC6@
FB_GC6_EN 1 @ 2 RV123 GC6_EN 2
20 FB_GC6_EN
0_0402_5% 1
FBVDDQ_PWR_EN 22,57
3
1

+3VGS RV124 1 2 @ BAV70W-7-F_SOT323-3

10K_0402_5% RV125
200K_0402_5%
RV126 1 2 NGC6@ GC6@
8,57,58 DGPU_PWROK
0_0402_5%
2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 N16X_MEM Interface
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG411
WWW.AliSaler.Com 5 4 3 2
Date: Thursday, January 14, 2016
1
Sheet 24 of 60
 5 4 3 2 1

at least 16 mils width(optimal)

20 mils spacing to other signals /planes FBA_D[0..63] 24,26,27,28
+1.35VGS
D FBA_CMD[30..0] 24,26,27,28 D
1

RANKA@
FBA_DQM[7..0] 24,26,27,28
RV128
1.33K_0402_1% UV6 UV5
FBA_DQS[7..0] 24,26,27,28
2

+FBA_VREFCA0 +FBA_VREFCA0 M8 E3 FBA_D5 +FBA_VREFCA0 M8 E3 FBA_D11

+FBA_VREFCA0 27 +FBA_VREFDQ0 VREFCA DQL0 FBA_D1 +FBA_VREFDQ0 VREFCA DQL0 FBA_D13 FBA_DQS#[7..0] 24,26,27,28
H1 F7 H1 F7
VREFDQ DQL1 VREFDQ DQL1
1

1 F2 FBA_D7 F2 FBA_D8
RANKA@ CV116 FBA_CMD7 N3 DQL2 F8 FBA_D0 FBA_CMD7 N3 DQL2 F8 FBA_D15
RV127 0.01U_0201_10V6K FBA_CMD10 P7 A0
A1
DQL3
DQL4
H3 FBA_D4 Group0 FBA_CMD10 P7 A0
A1
DQL3
DQL4
H3 FBA_D10 Group1 CMD mapping mod Mode E
1.33K_0402_1% RANKA@ FBA_CMD24 P3 H8 FBA_D3 FBA_CMD24 P3 H8 FBA_D14
2 FBA_CMD6 N2 A2 DQL5 G2 FBA_D6 FBA_CMD6 N2 A2 DQL5 G2 FBA_D9 Rank0 Rank1
2

FBA_CMD22 P8 A3 DQL6 H7 FBA_D2 FBA_CMD22 P8 A3 DQL6 H7 FBA_D12

FBA_CMD26 P2 A4 DQL7 FBA_CMD26 P2 A4 DQL7
A5 A5
Address 0..31 32..63 0..31 32..63
FBA_CMD5 R8 FBA_CMD5 R8
FBA_CMD21 R2 A6 D7 FBA_D31 FBA_CMD21 R2 A6 D7 FBA_D17
A7 DQU0 A7 DQU0 FBx_CMD0 ODT_L ODT_L
FBA_CMD8 T8 C3 FBA_D25 FBA_CMD8 T8 C3 FBA_D22
FBA_CMD4 R3 A8 DQU1 C8 FBA_D30 FBA_CMD4 R3 A8 DQU1 C8 FBA_D16
A9 DQU2 A9 DQU2 FBx_CMD1 CS1#_L
FBA_CMD25 L7 C2 FBA_D24 FBA_CMD25 L7 C2 FBA_D23 Group2
+1.35VGS FBA_CMD23 R7 A10/AP DQU3 A7 FBA_D29 FBA_CMD23 R7 A10/AP DQU3 A7 FBA_D19
A11 DQU4 Group3 A11 DQU4 FBx_CMD2 CS0#_L
FBA_CMD9 N7 A2 FBA_D27 FBA_CMD9 N7 A2 FBA_D21
FBA_CMD12 T3 A12/BC DQU5 B8 FBA_D28 FBA_CMD12 T3 A12/BC DQU5 B8 FBA_D18
A13 DQU6 A13 DQU6 FBx_CMD3 CKE_L CKE_L
1

FBA_CMD14 T7 A3 FBA_D26 FBA_CMD14 T7 A3 FBA_D20

RANKA@ A14 DQU7 A14 DQU7
FBx_CMD4 A9 A9 A11 A11
RV167 +1.35VGS +1.35VGS
1.33K_0402_1% FBx_CMD5 A6 A6 A7 A7
FBA_CMD29 M2 B2 FBA_CMD29 M2 B2
2

+FBA_VREFDQ0 FBA_CMD13 N8 BA0 VDD_1 D9 FBA_CMD13 N8 BA0 VDD_1 D9

+FBA_VREFDQ0 27 BA1 VDD_2 BA1 VDD_2 FBx_CMD6 A3 A3 BA1 BA1
FBA_CMD27 M3 G7 FBA_CMD27 M3 G7
BA2 VDD_3 BA2 VDD_3
1

1 K2 K2 FBx_CMD7 A0 A0 A12 A12

RANKA@ CV216 VDD_4 K8 VDD_4 K8
RV168 0.01U_0201_10V6K VDD_5 N1 VDD_5 N1
VDD_6 VDD_6 FBx_CMD8 A8 A8 A8 A8
1.33K_0402_1% RANKA@ FBA_CLK0 J7 N9 FBA_CLK0 J7 N9
2 24,27 FBA_CLK0 FBA_CLK0# CK VDD_7 FBA_CLK0# CK VDD_7
K7 R1 K7 R1 FBx_CMD9 A12 A12 A0 A0
24,27 FBA_CLK0#
2

FBA_CKE_L K9 CK VDD_8 R9 FBA_CKE_L K9 CK VDD_8 R9

24,27 FBA_CKE_L CKE VDD_9 CKE VDD_9
FBx_CMD10 A1 A1 A2 A2
C C
FBA_ODT_L K1 A1 FBA_ODT_L K1 A1 FBx_CMD11 RAS# RAS# RAS# RAS#
24,27 FBA_ODT_L FBA_CS0#_L ODT VDDQ_1 FBA_CS0#_L ODT VDDQ_1
L2 A8 L2 A8
24 FBA_CS0#_L FBA_RAS# CS VDDQ_2 FBA_RAS# CS VDDQ_2
J3 C1 J3 C1 FBx_CMD12 A13 A13 A14 A14
24,26,27,28 FBA_RAS# FBA_CAS# RAS VDDQ_3 FBA_CAS# RAS VDDQ_3
K3 C9 K3 C9
24,26,27,28 FBA_CAS# FBA_CMD28 CAS VDDQ_4 FBA_CMD28 CAS VDDQ_4
L3 D2 L3 D2 FBx_CMD13 BA1 BA1 A3 A3
WE VDDQ_5 E9 WE VDDQ_5 E9
VDDQ_6 F1 VDDQ_6 F1
VDDQ_7 VDDQ_7 FBx_CMD14 A14 A14 A13 A13
FBA_DQS0 F3 H2 FBA_DQS1 F3 H2
FBA_CLK0 FBA_DQS3 C7 DQSL VDDQ_8 H9 FBA_DQS2 C7 DQSL VDDQ_8 H9
DQSU VDDQ_9 DQSU VDDQ_9 FBx_CMD15 CAS# CAS# CAS# CAS#
FBx_CMD16 ODT_H ODT_H
1

FBA_DQM0 E7 A9 FBA_DQM1 E7 A9
RV129 FBA_DQM3 D3 DML VSS_1 B3 FBA_DQM2 D3 DML VSS_1 B3
DMU VSS_2 DMU VSS_2 FBx_CMD17 CS1#_H
162_0402_1% E1 E1
RANKA@ VSS_3 G8 VSS_3 G8
VSS_4 VSS_4 FBx_CMD18 CS0#_H
FBA_DQS#0 G3 J2 FBA_DQS#1 G3 J2
2

FBA_DQS#3 B7 DQSL VSS_5 J8 FBA_DQS#2 B7 DQSL VSS_5 J8

DQSU VSS_6 DQSU VSS_6 FBx_CMD19 CKE_H CKE_H
FBA_CLK0# M1 M1
VSS_7 M9 VSS_7 M9
VSS_8 VSS_8 FBx_CMD20 RST RST RST RST
P1 P1
FBA_RST# T2 VSS_9 P9 FBA_RST# T2 VSS_9 P9
24,26,27,28 FBA_RST# RESET VSS_10 RESET VSS_10 FBx_CMD21 A7 A7 A6 A6
T1 T1
1 2 RV130 L8 VSS_11 T9 L8 VSS_11 T9
ZQ VSS_12 ZQ VSS_12 FBx_CMD22 A4 A4 A5 A5
243_0402_1%
RANKA@ FBx_CMD23 A11 A11 A9 A9

1
J1 B1 J1 B1
NC1 VSSQ_1 NC1 VSSQ_1
1

L1 B9 RV132 L1 B9 FBx_CMD24 A2 A2 A1 A1
RV131 J9 NC2 VSSQ_2 D1 243_0402_1% J9 NC2 VSSQ_2 D1
FBA_ODT_L 10K_0402_5% L9 NC3 VSSQ_3 D8 RANKA@ L9 NC3 VSSQ_3 D8
NC4 VSSQ_4 NC4 VSSQ_4 FBx_CMD25 A10 A10 WE# WE#
RANKA@ M7 E2 M7 E2

2
NC5 VSSQ_5 E8 NC5 VSSQ_5 E8 FBx_CMD26 A5 A5 A4 A4
2

FBA_CKE_L VSSQ_6 F9 VSSQ_6 F9

VSSQ_7 G1 VSSQ_7 G1
VSSQ_8 VSSQ_8 FBx_CMD27 BA2 BA2
G9 G9
VSSQ_9 VSSQ_9
1

FBx_CMD28 WE# WE# A10 A10

RV133 RV134 96-BALL 96-BALL
10K_0402_5% 10K_0402_5% SDRAM DDR3 SDRAM DDR3 FBx_CMD29 BA0 BA0 BA0 BA0
B B
RANKA@ RANKA@ K4W4G1646B-HC11_FBGA96 K4W4G1646B-HC11_FBGA96
@ @ FBx_CMD30 BA2 BA2
2

+1.35VGS UV6 SIDE +1.35VGS +1.35VGS UV5 SIDE +1.35VGS

For RF
CD@

CD@
RANKA@

RANKA@

RANKA@

RANKA@

RANKA@

RANKA@

RANKA@

RANKA@

RANKA@

RANKA@
RF_NS@

RF_NS@
33P_0402_50V8J

33P_0402_50V8J
0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 For RF 2 2 2 2 2 2 2 2
CV117

CV118

CV119

CV120

CV121

CV122

CV127

CV129

CV130

CV131

CV132

CV133

CV134

CV139
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 N16X_DDR3_Rank0_[31:0]
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG411
Date: Thursday, January 14, 2016 Sheet 25 of 60
5 4 3 2 1
 5 4 3 2 1

at least 16 mils width(optimal)

20 mils spacing to other signals /planes

+1.35VGS
1

D FBA_D[0..63] 24,25,27,28 D
RANKA@
RV135
1.33K_0402_1%
FBA_CMD[30..0] 24,25,27,28
UV8 UV7
2

+FBA_VREFCA1
+FBA_VREFCA1 28 +FBA_VREFCA1 FBA_D34 +FBA_VREFCA1 FBA_D44 FBA_DQM[7..0] 24,25,27,28
M8 E3 M8 E3
VREFCA DQL0 VREFCA DQL0
1

1 +FBA_VREFDQ1 H1 F7 FBA_D38 +FBA_VREFDQ1 H1 F7 FBA_D43

VREFDQ DQL1 FBA_D35 VREFDQ DQL1 FBA_D45 FBA_DQS[7..0] 24,25,27,28
RANKA@ CV141 F2 F2
RV136 0.01U_0201_10V6K FBA_CMD7 N3 DQL2 F8 FBA_D39 FBA_CMD7 N3 DQL2 F8 FBA_D40
FBA_CMD10 A0 DQL3 FBA_D32 FBA_CMD10 A0 DQL3 FBA_D47
Group5 FBA_DQS#[7..0] 24,25,27,28
1.33K_0402_1% RANKA@ P7 H3 Group4 P7 H3
2 FBA_CMD24 P3 A1 DQL4 H8 FBA_D36 FBA_CMD24 P3 A1 DQL4 H8 FBA_D42
2

FBA_CMD6 N2 A2 DQL5 G2 FBA_D33 FBA_CMD6 N2 A2 DQL5 G2 FBA_D46

FBA_CMD22 P8 A3 DQL6 H7 FBA_D37 FBA_CMD22 P8 A3 DQL6 H7 FBA_D41
FBA_CMD26 P2 A4 DQL7 FBA_CMD26 P2 A4 DQL7
FBA_CMD5 R8 A5 FBA_CMD5 R8 A5
FBA_CMD21 R2 A6 D7 FBA_D59 FBA_CMD21 R2 A6 D7 FBA_D52
FBA_CMD8 T8 A7
A8
DQU0
DQU1
C3 FBA_D62 FBA_CMD8 T8 A7
A8
DQU0
DQU1
C3 FBA_D50 CMD mapping mod Mode E
FBA_CMD4 R3 C8 FBA_D58 FBA_CMD4 R3 C8 FBA_D55
+1.35VGS FBA_CMD25 L7 A9 DQU2 C2 FBA_D63 FBA_CMD25 L7 A9 DQU2 C2 FBA_D51
A10/AP DQU3 A10/AP DQU3 Rank0 Rank1
FBA_CMD23 R7 A7 FBA_D57 Group7 FBA_CMD23 R7 A7 FBA_D53 Group6
FBA_CMD9 N7 A11 DQU4 A2 FBA_D60 FBA_CMD9 N7 A11 DQU4 A2 FBA_D48
A12/BC DQU5 A12/BC DQU5
Address 0..31 32..63 0..31 32..63
1

FBA_CMD12 T3 B8 FBA_D56 FBA_CMD12 T3 B8 FBA_D54

RANKA@ FBA_CMD14 T7 A13 DQU6 A3 FBA_D61 FBA_CMD14 T7 A13 DQU6 A3 FBA_D49
A14 DQU7 A14 DQU7 FBx_CMD0 ODT_L ODT_L
RV169
1.33K_0402_1% +1.35VGS +1.35VGS FBx_CMD1 CS1#_L
2

+FBA_VREFDQ1 FBA_CMD29 M2 B2 FBA_CMD29 M2 B2 FBx_CMD2 CS0#_L

+FBA_VREFDQ1 28 FBA_CMD13 BA0 VDD_1 FBA_CMD13 BA0 VDD_1
N8 D9 N8 D9
BA1 VDD_2 BA1 VDD_2
1

1 FBA_CMD27 M3 G7 FBA_CMD27 M3 G7 FBx_CMD3 CKE_L CKE_L

RANKA@ CV217 BA2 VDD_3 K2 BA2 VDD_3 K2
RV170 0.01U_0201_10V6K VDD_4 K8 VDD_4 K8
VDD_5 VDD_5 FBx_CMD4 A9 A9 A11 A11
1.33K_0402_1% RANKA@ N1 N1
2 FBA_CLK1 J7 VDD_6 N9 FBA_CLK1 J7 VDD_6 N9
24,28 FBA_CLK1 FBx_CMD5 A6 A6 A7 A7
2

FBA_CLK1# K7 CK VDD_7 R1 FBA_CLK1# K7 CK VDD_7 R1

24,28 FBA_CLK1# FBA_CKE_H CK VDD_8 FBA_CKE_H K9 CK VDD_8
K9 R9 R9 FBx_CMD6 A3 A3 BA1 BA1
24,28 FBA_CKE_H CKE VDD_9 CKE VDD_9
FBx_CMD7 A0 A0 A12 A12
C FBA_ODT_H K1 A1 FBA_ODT_H K1 A1 C
24,28 FBA_ODT_H FBA_CS0#_H ODT VDDQ_1 FBA_CS0#_H ODT VDDQ_1
L2 A8 L2 A8 FBx_CMD8 A8 A8 A8 A8
24 FBA_CS0#_H FBA_RAS# CS VDDQ_2 FBA_RAS# CS VDDQ_2
J3 C1 J3 C1
24,25,27,28 FBA_RAS# FBA_CAS# RAS VDDQ_3 FBA_CAS# RAS VDDQ_3
K3 C9 K3 C9 FBx_CMD9 A12 A12 A0 A0
24,25,27,28 FBA_CAS# FBA_CMD28 CAS VDDQ_4 FBA_CMD28 CAS VDDQ_4
L3 D2 L3 D2
FBA_CLK1 WE VDDQ_5 E9 WE VDDQ_5 E9
VDDQ_6 VDDQ_6 FBx_CMD10 A1 A1 A2 A2
F1 F1
FBA_DQS4 F3 VDDQ_7 H2 FBA_DQS5 F3 VDDQ_7 H2
DQSL VDDQ_8 DQSL VDDQ_8 FBx_CMD11 RAS# RAS# RAS# RAS#
1

FBA_DQS7 C7 H9 FBA_DQS6 C7 H9
RV137 DQSU VDDQ_9 DQSU VDDQ_9
FBx_CMD12 A13 A13 A14 A14
162_0402_1%
FBA_DQM4 E7 A9 FBA_DQM5 E7 A9 FBx_CMD13 BA1 BA1 A3 A3
RANKA@ FBA_DQM7 D3 DML VSS_1 B3 FBA_DQM6 D3 DML VSS_1 B3
2

DMU VSS_2 E1 DMU VSS_2 E1

VSS_3 VSS_3 FBx_CMD14 A14 A14 A13 A13
FBA_CLK1# G8 G8
FBA_DQS#4 G3 VSS_4 J2 FBA_DQS#5 G3 VSS_4 J2
DQSL VSS_5 DQSL VSS_5 FBx_CMD15 CAS# CAS# CAS# CAS#
FBA_DQS#7 B7 J8 FBA_DQS#6 B7 J8
DQSU VSS_6 M1 DQSU VSS_6 M1
VSS_7 VSS_7 FBx_CMD16 ODT_H ODT_H
M9 M9
VSS_8 P1 VSS_8 P1
VSS_9 VSS_9 FBx_CMD17 CS1#_H
FBA_RST# T2 P9 FBA_RST# T2 P9
24,25,27,28 FBA_RST# RESET VSS_10 RESET VSS_10
T1 T1 FBx_CMD18 CS0#_H
L8 VSS_11 T9 L8 VSS_11 T9
FBA_CKE_H ZQ VSS_12 ZQ VSS_12
FBx_CMD19 CKE_H CKE_H

1
J1 B1 J1 B1 FBx_CMD20 RST RST RST RST
NC1 VSSQ_1 NC1 VSSQ_1
1

FBA_ODT_H L1 B9 RV141 L1 B9
RV140 J9 NC2 VSSQ_2 D1 243_0402_1% J9 NC2 VSSQ_2 D1
NC3 VSSQ_3 NC3 VSSQ_3 FBx_CMD21 A7 A7 A6 A6
243_0402_1% L9 D8 RANKA@ L9 D8
RANKA@ M7 NC4 VSSQ_4 E2 M7 NC4 VSSQ_4 E2 FBx_CMD22 A4 A4 A5 A5

2
NC5 VSSQ_5 NC5 VSSQ_5
1

E8 E8
2

RV138 RV139 VSSQ_6 F9 VSSQ_6 F9

VSSQ_7 VSSQ_7 FBx_CMD23 A11 A11 A9 A9
10K_0402_5% 10K_0402_5% G1 G1
RANKA@ RANKA@ VSSQ_8 G9 VSSQ_8 G9
VSSQ_9 VSSQ_9 FBx_CMD24 A2 A2 A1 A1
2

96-BALL 96-BALL FBx_CMD25 A10 A10 WE# WE#

SDRAM DDR3 SDRAM DDR3
K4W4G1646B-HC11_FBGA96 K4W4G1646B-HC11_FBGA96 FBx_CMD26 A5 A5 A4 A4
B B
@ @
FBx_CMD27 BA2 BA2
FBx_CMD28 WE# WE# A10 A10
FBx_CMD29 BA0 BA0 BA0 BA0
FBx_CMD30 BA2 BA2

+1.35VGS UV8 SIDE +1.35VGS +1.35VGS UV7 SIDE +1.35VGS

For RF For RF
CD@

CD@
RANKA@

RANKA@

RANKA@

RANKA@

RANKA@

RANKA@

RANKA@

RANKA@

RANKA@

RANKA@
RF_NS@

RF_NS@
33P_0402_50V8J

33P_0402_50V8J
0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2 2
CV142

CV143

CV144

CV145

CV146

CV147

CV152

CV154

CV155

CV156

CV157

CV158

CV159

CV164
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 N16X_DDR3_Rank0_[64:32]
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG411
WWW.AliSaler.Com 5 4 3 2
Date: Thursday, January 14, 2016
1
Sheet 26 of 60
 5 4 3 2 1

FBA_D[0..63] 24,25,26,28

FBA_CMD[30..0] 24,25,26,28

FBA_DQM[7..0] 24,25,26,28

FBA_DQS[7..0] 24,25,26,28

D FBA_DQS#[7..0] 24,25,26,28 D

UV9 UV10

+FBA_VREFCA0 M8 E3 FBA_D1 +FBA_VREFCA0 M8 E3 FBA_D13

25 +FBA_VREFCA0 +FBA_VREFDQ0 VREFCA DQL0 FBA_D5 +FBA_VREFDQ0 VREFCA DQL0 FBA_D11
H1 F7 H1 F7
25 +FBA_VREFDQ0 VREFDQ DQL1 FBA_D0 VREFDQ DQL1 FBA_D15
at least 16 mils width(optimal) F2 F2
FBA_CMD9 N3 DQL2 F8 FBA_D7 FBA_CMD9 N3 DQL2 F8 FBA_D8
20 mils spacing to other signals /planes FBA_CMD24 A0 DQL3 FBA_D2 FBA_CMD24 A0 DQL3 FBA_D12
Group1
P7 H3 Group0 P7 H3
FBA_CMD10 P3 A1 DQL4 H8 FBA_D6 FBA_CMD10 P3 A1 DQL4 H8 FBA_D9
FBA_CMD13 N2 A2 DQL5 G2 FBA_D3 FBA_CMD13 N2 A2 DQL5 G2 FBA_D14
FBA_CMD26 P8 A3 DQL6 H7 FBA_D4 FBA_CMD26 P8 A3 DQL6 H7 FBA_D10
FBA_CMD22 P2 A4 DQL7 FBA_CMD22 P2 A4 DQL7
FBA_CMD21 R8 A5 FBA_CMD21 R8 A5
FBA_CMD5 R2 A6 D7 FBA_D25 FBA_CMD5 R2 A6 D7 FBA_D22
FBA_CMD8 T8 A7 DQU0 C3 FBA_D31 FBA_CMD8 T8 A7 DQU0 C3 FBA_D17
FBA_CMD23 R3 A8 DQU1 C8 FBA_D24 FBA_CMD23 R3 A8 DQU1 C8 FBA_D23
FBA_CMD28 L7 A9 DQU2 C2 FBA_D30 FBA_CMD28 L7 A9 DQU2 C2 FBA_D16
FBA_CMD4 A10/AP DQU3 FBA_D26 FBA_CMD4 A10/AP DQU3 FBA_D20
Group2
R7 A7 Group3 R7 A7
FBA_CMD7 N7 A11 DQU4 A2 FBA_D28 FBA_CMD7 N7 A11 DQU4 A2 FBA_D18
FBA_CMD14 T3 A12/BC DQU5 B8 FBA_D27 FBA_CMD14 T3 A12/BC DQU5 B8 FBA_D21
FBA_CMD12 T7 A13 DQU6 A3 FBA_D29 FBA_CMD12 T7 A13 DQU6 A3 FBA_D19
A14 DQU7 A14 DQU7 CMD mapping mod Mode E
+1.35VGS +1.35VGS
Rank0 Rank1
FBA_CMD29 M2 B2 FBA_CMD29 M2 B2
FBA_CMD6 N8 BA0 VDD_1 D9 FBA_CMD6 N8 BA0 VDD_1 D9
BA1 VDD_2 BA1 VDD_2
Address 0..31 32..63 0..31 32..63
FBA_CMD30 M3 G7 FBA_CMD30 M3 G7
BA2 VDD_3 K2 BA2 VDD_3 K2
VDD_4 VDD_4 FBx_CMD0 ODT_L ODT_L
K8 K8
VDD_5 N1 VDD_5 N1
VDD_6 VDD_6 FBx_CMD1 CS1#_L
FBA_CLK0 J7 N9 FBA_CLK0 J7 N9
24,25 FBA_CLK0 FBA_CLK0# CK VDD_7 FBA_CLK0# CK VDD_7
K7 R1 K7 R1 FBx_CMD2 CS0#_L
24,25 FBA_CLK0# FBA_CKE_L CK VDD_8 FBA_CKE_L CK VDD_8
K9 R9 K9 R9
24,25 FBA_CKE_L CKE VDD_9 CKE VDD_9
FBx_CMD3 CKE_L CKE_L
C FBA_ODT_L K1 A1 FBA_ODT_L K1 A1 FBx_CMD4 A9 A9 A11 A11 C
24,25 FBA_ODT_L FBA_CS1#_L ODT VDDQ_1 FBA_CS1#_L ODT VDDQ_1
L2 A8 L2 A8
24 FBA_CS1#_L FBA_RAS# CS VDDQ_2 FBA_RAS# CS VDDQ_2
J3 C1 J3 C1 FBx_CMD5 A6 A6 A7 A7
24,25,26,28 FBA_RAS# FBA_CAS# RAS VDDQ_3 FBA_CAS# RAS VDDQ_3
K3 C9 K3 C9
24,25,26,28 FBA_CAS# FBA_CMD25 CAS VDDQ_4 FBA_CMD25 CAS VDDQ_4
L3 D2 L3 D2 FBx_CMD6 A3 A3 BA1 BA1
WE VDDQ_5 E9 WE VDDQ_5 E9
VDDQ_6 F1 VDDQ_6 F1
VDDQ_7 VDDQ_7 FBx_CMD7 A0 A0 A12 A12
FBA_DQS0 F3 H2 FBA_DQS1 F3 H2
FBA_DQS3 C7 DQSL VDDQ_8 H9 FBA_DQS2 C7 DQSL VDDQ_8 H9
DQSU VDDQ_9 DQSU VDDQ_9 FBx_CMD8 A8 A8 A8 A8
FBx_CMD9 A12 A12 A0 A0
FBA_DQM0 E7 A9 FBA_DQM1 E7 A9
FBA_DQM3 D3 DML VSS_1 B3 FBA_DQM2 D3 DML VSS_1 B3
DMU VSS_2 DMU VSS_2 FBx_CMD10 A1 A1 A2 A2
E1 E1
VSS_3 G8 VSS_3 G8
VSS_4 VSS_4 FBx_CMD11 RAS# RAS# RAS# RAS#
FBA_DQS#0 G3 J2 FBA_DQS#1 G3 J2
FBA_DQS#3 B7 DQSL VSS_5 J8 FBA_DQS#2 B7 DQSL VSS_5 J8
DQSU VSS_6 DQSU VSS_6 FBx_CMD12 A13 A13 A14 A14
M1 M1
VSS_7 M9 VSS_7 M9
VSS_8 VSS_8 FBx_CMD13 BA1 BA1 A3 A3
P1 P1
FBA_RST# T2 VSS_9 P9 FBA_RST# T2 VSS_9 P9
24,25,26,28 FBA_RST# RESET VSS_10 RESET VSS_10 FBx_CMD14 A14 A14 A13 A13
T1 T1
1 2 RV142 L8 VSS_11 T9 L8 VSS_11 T9
ZQ VSS_12 ZQ VSS_12 FBx_CMD15 CAS# CAS# CAS# CAS#
243_0402_1%
RANKB@ FBx_CMD16 ODT_H ODT_H

1
J1 B1 J1 B1
L1 NC1 VSSQ_1 B9 RV143 L1 NC1 VSSQ_1 B9
NC2 VSSQ_2 NC2 VSSQ_2 FBx_CMD17 CS1#_H
J9 D1 243_0402_1% J9 D1
L9 NC3 VSSQ_3 D8 RANKB@ L9 NC3 VSSQ_3 D8
NC4 VSSQ_4 NC4 VSSQ_4 FBx_CMD18 CS0#_H
M7 E2 M7 E2

2
NC5 VSSQ_5 E8 NC5 VSSQ_5 E8
VSSQ_6 VSSQ_6 FBx_CMD19 CKE_H CKE_H
F9 F9
VSSQ_7 G1 VSSQ_7 G1
VSSQ_8 VSSQ_8 FBx_CMD20 RST RST RST RST
G9 G9
VSSQ_9 VSSQ_9
FBx_CMD21 A7 A7 A6 A6
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 FBx_CMD22 A4 A4 A5 A5
K4W4G1646B-HC11_FBGA96 K4W4G1646B-HC11_FBGA96
B B
@ @ FBx_CMD23 A11 A11 A9 A9
FBx_CMD24 A2 A2 A1 A1
FBx_CMD25 A10 A10 WE# WE#
FBx_CMD26 A5 A5 A4 A4
FBx_CMD27 BA2 BA2
FBx_CMD28 WE# WE# A10 A10
FBx_CMD29 BA0 BA0 BA0 BA0
FBx_CMD30 BA2 BA2

+1.35VGS UV4 SIDE +1.35VGS +1.35VGS UV3 SIDE +1.35VGS

For RF For RF
CD@

CD@
RANKB@

RANKB@

RANKB@

RANKB@

RANKB@

RANKB@

RANKB@

RANKB@

RANKB@

RANKB@
RF_NS@

RF_NS@
0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K
33P_0402_50V8J

33P_0402_50V8J
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2 2
CV166

CV167

CV168

CV169

CV170

CV171

CV176

CV178

CV179

CV180

CV181

CV182

CV183

CV188
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 N16X_DDR3_Rank1_[31:0]
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG411
Date: Thursday, January 14, 2016 Sheet 27 of 60
5 4 3 2 1
 5 4 3 2 1

FBA_D[0..63] 24,25,26,27

FBA_CMD[30..0] 24,25,26,27

FBA_DQM[7..0] 24,25,26,27

FBA_DQS[7..0] 24,25,26,27
D D
FBA_DQS#[7..0] 24,25,26,27
UV11 UV12

+FBA_VREFCA1 M8 E3 FBA_D38 +FBA_VREFCA1 M8 E3 FBA_D43

26 +FBA_VREFCA1 +FBA_VREFDQ1 VREFCA DQL0 FBA_D34 +FBA_VREFDQ1 VREFCA DQL0 FBA_D44
at least 16 mils width(optimal) H1 F7 H1 F7
26 +FBA_VREFDQ1 VREFDQ DQL1 FBA_D39 VREFDQ DQL1 FBA_D40
20 mils spacing to other signals /planes F2 F2
FBA_CMD9 N3 DQL2 F8 FBA_D35 FBA_CMD9 N3 DQL2 F8 FBA_D45
FBA_CMD24 P7 A0 DQL3 H3 FBA_D37 FBA_CMD24 P7 A0 DQL3 H3 FBA_D41
FBA_CMD10 A1 DQL4 FBA_D33
Group4 FBA_CMD10 A1 DQL4 FBA_D46
Group5
P3 H8 P3 H8
FBA_CMD13 N2 A2 DQL5 G2 FBA_D36 FBA_CMD13 N2 A2 DQL5 G2 FBA_D42
FBA_CMD26 P8 A3 DQL6 H7 FBA_D32 FBA_CMD26 P8 A3 DQL6 H7 FBA_D47
FBA_CMD22 P2 A4 DQL7 FBA_CMD22 P2 A4 DQL7
FBA_CMD21 R8 A5 FBA_CMD21 R8 A5
FBA_CMD5 R2 A6 D7 FBA_D62 FBA_CMD5 R2 A6 D7 FBA_D50
FBA_CMD8 T8 A7 DQU0 C3 FBA_D59 FBA_CMD8 T8 A7 DQU0 C3 FBA_D52
FBA_CMD23 R3 A8 DQU1 C8 FBA_D63 FBA_CMD23 R3 A8 DQU1 C8 FBA_D51
FBA_CMD28 L7 A9 DQU2 C2 FBA_D58 FBA_CMD28 L7 A9 DQU2 C2 FBA_D55
FBA_CMD4 A10/AP DQU3 FBA_D61
Group7 FBA_CMD4 A10/AP DQU3 FBA_D49
R7 A7 R7 A7 Group6
FBA_CMD7 N7 A11 DQU4 A2 FBA_D56 FBA_CMD7 N7 A11 DQU4 A2 FBA_D54
FBA_CMD14 T3 A12/BC
A13
DQU5
DQU6
B8 FBA_D60 FBA_CMD14 T3 A12/BC
A13
DQU5
DQU6
B8 FBA_D48 CMD mapping mod Mode E
FBA_CMD12 T7 A3 FBA_D57 FBA_CMD12 T7 A3 FBA_D53
A14 DQU7 A14 DQU7
Rank0 Rank1
+1.35VGS +1.35VGS
Address 0..31 32..63 0..31 32..63
FBA_CMD29 M2 B2 FBA_CMD29 M2 B2
FBA_CMD6 N8 BA0 VDD_1 D9 FBA_CMD6 N8 BA0 VDD_1 D9
BA1 VDD_2 BA1 VDD_2 FBx_CMD0 ODT_L ODT_L
FBA_CMD30 M3 G7 FBA_CMD30 M3 G7
BA2 VDD_3 K2 BA2 VDD_3 K2
VDD_4 VDD_4 FBx_CMD1 CS1#_L
K8 K8
VDD_5 N1 VDD_5 N1
VDD_6 VDD_6 FBx_CMD2 CS0#_L
FBA_CLK1 J7 N9 FBA_CLK1 J7 N9
24,26 FBA_CLK1 FBA_CLK1# CK VDD_7 FBA_CLK1# K7 CK VDD_7
K7 R1 R1 FBx_CMD3 CKE_L CKE_L
24,26 FBA_CLK1# FBA_CKE_H CK VDD_8 FBA_CKE_H K9 CK VDD_8
K9 R9 R9
24,26 FBA_CKE_H CKE VDD_9 CKE VDD_9
FBx_CMD4 A9 A9 A11 A11
FBA_ODT_H K1 A1 FBA_ODT_H K1 A1 FBx_CMD5 A6 A6 A7 A7
24,26 FBA_ODT_H FBA_CS1#_H ODT VDDQ_1 FBA_CS1#_H ODT VDDQ_1
C L2 A8 L2 A8 C
24 FBA_CS1#_H FBA_RAS# CS VDDQ_2 FBA_RAS# CS VDDQ_2
J3 C1 J3 C1 FBx_CMD6 A3 A3 BA1 BA1
24,25,26,27 FBA_RAS# FBA_CAS# RAS VDDQ_3 FBA_CAS# RAS VDDQ_3
K3 C9 K3 C9
24,25,26,27 FBA_CAS# FBA_CMD25 CAS VDDQ_4 FBA_CMD25 CAS VDDQ_4
L3 D2 L3 D2 FBx_CMD7 A0 A0 A12 A12
WE VDDQ_5 E9 WE VDDQ_5 E9
VDDQ_6 F1 VDDQ_6 F1
VDDQ_7 VDDQ_7 FBx_CMD8 A8 A8 A8 A8
FBA_DQS4 F3 H2 FBA_DQS5 F3 H2
FBA_DQS7 C7 DQSL VDDQ_8 H9 FBA_DQS6 C7 DQSL VDDQ_8 H9
DQSU VDDQ_9 DQSU VDDQ_9 FBx_CMD9 A12 A12 A0 A0
FBx_CMD10 A1 A1 A2 A2
FBA_DQM4 E7 A9 FBA_DQM5 E7 A9
FBA_DQM7 D3 DML VSS_1 B3 FBA_DQM6 D3 DML VSS_1 B3
DMU VSS_2 DMU VSS_2 FBx_CMD11 RAS# RAS# RAS# RAS#
E1 E1
VSS_3 G8 VSS_3 G8
VSS_4 VSS_4 FBx_CMD12 A13 A13 A14 A14
FBA_DQS#4 G3 J2 FBA_DQS#5 G3 J2
FBA_DQS#7 B7 DQSL VSS_5 J8 FBA_DQS#6 B7 DQSL VSS_5 J8
DQSU VSS_6 DQSU VSS_6 FBx_CMD13 BA1 BA1 A3 A3
M1 M1
VSS_7 M9 VSS_7 M9
VSS_8 VSS_8 FBx_CMD14 A14 A14 A13 A13
P1 P1
FBA_RST# T2 VSS_9 P9 FBA_RST# T2 VSS_9 P9
24,25,26,27 FBA_RST# RESET VSS_10 RESET VSS_10 FBx_CMD15 CAS# CAS# CAS# CAS#
T1 T1
L8 VSS_11 T9 L8 VSS_11 T9
ZQ VSS_12 ZQ VSS_12 FBx_CMD16 ODT_H ODT_H
FBx_CMD17 CS1#_H

1
J1 B1 J1 B1
NC1 VSSQ_1 NC1 VSSQ_1
1

L1 B9 RV145 L1 B9 FBx_CMD18 CS0#_H

RV144 J9 NC2 VSSQ_2 D1 243_0402_1% J9 NC2 VSSQ_2 D1
243_0402_1% L9 NC3 VSSQ_3 D8 RANKB@ L9 NC3 VSSQ_3 D8
NC4 VSSQ_4 NC4 VSSQ_4 FBx_CMD19 CKE_H CKE_H
RANKB@ M7 E2 M7 E2

2
NC5 VSSQ_5 E8 NC5 VSSQ_5 E8 FBx_CMD20 RST RST RST RST
2

VSSQ_6 F9 VSSQ_6 F9
VSSQ_7 G1 VSSQ_7 G1
VSSQ_8 VSSQ_8 FBx_CMD21 A7 A7 A6 A6
G9 G9
VSSQ_9 VSSQ_9
FBx_CMD22 A4 A4 A5 A5
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 FBx_CMD23 A11 A11 A9 A9
K4W4G1646B-HC11_FBGA96 K4W4G1646B-HC11_FBGA96
B @ @ FBx_CMD24 A2 A2 A1 A1 B

FBx_CMD25 A10 A10 WE# WE#

FBx_CMD26 A5 A5 A4 A4
FBx_CMD27 BA2 BA2
FBx_CMD28 WE# WE# A10 A10
FBx_CMD29 BA0 BA0 BA0 BA0
FBx_CMD30 BA2 BA2

+1.35VGS UV6 SIDE +1.35VGS +1.35VGS UV5 SIDE +1.35VGS

For RF For RF
CD@

CD@
RANKB@

RANKB@

RANKB@

RANKB@

RANKB@

RANKB@

RANKB@

RANKB@

RANKB@

RANKB@
RF_NS@

RF_NS@
0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K
33P_0402_50V8J

33P_0402_50V8J
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2 2
CV190

CV191

CV192

CV193

CV194

CV195

CV200

CV202

CV203

CV204

CV205

CV206

CV207

CV212
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 N16X_DDR3_Rank1_[64:32]
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG411
WWW.AliSaler.Com 5 4 3 2
Date: Thursday, January 14, 2016
1
Sheet 28 of 60
 5 4 3 2 1

Physical Logical Logical Logical Logical

Strapping pin Power Rail Strapping Bit3 Strapping Bit2 Strapping Bit1 Strapping Bit0
+3VG_AON
D D
ROM_SCLK +3VGS SOR3_EXPOSED SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED
ROM_SI +3VGS RAM_CFG[3] RAM_CFG[2] RAM_CFG[1] RAM_CFG[0]
ROM_SO +3VGS DEVID_SEL PCIE_CFG SMB_ALT_ADDR VGA_DEVICE

2
RV146 RV147 RV148 RV149 RV150 STRAP0 +3VGS Reserved(keep pull-up and pull-down footprint and stuff 50Kohm pull-up)
49.9K_0402_1% 4.99K_0402_1% 24.9K_0402_1% 4.99K_0402_1% 45.3K_0402_1%
OPT@ @ @ @ @ STRAP1 +3VGS

1
STRAP2 +3VGS
21 STRAP0 STRAP0 Reserved(keep pull-up and pull-down footprint and not stuff by default)
21 STRAP1 STRAP1 STRAP3 +3VGS
21 STRAP2 STRAP2
21 STRAP3 STRAP3 STRAP4 +3VGS
21 STRAP4 STRAP4

DEVID_SEL
2

2
Pull-up to
RV151 RV152 RV153 RV154 RV155 Resistor Values Pull-down to Gnd
45.3K_0402_1% 4.99K_0402_1% 15K_0402_1% 4.99K_0402_1% 45.3K_0402_1%
+3VGS
0 (Default)
@ @ @ @ @ 4.99K 1000 0000
1

1
10K 1001 0001 1
15K 1010 0010
20K 1011 0011 PCIE_CFG
24.9K 1100 0100
0 (Default)
30.1K 1101 0101
34.8K 1110 0110 1
+3VGS 45.3K 1111 0111
C C

SMBUS_ALT_ADDR
X76 0 0x9E (Default)
2

2
RV156 RV157 RV158
4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 1 0x9C (Multi-GPU usage)
@ @ @
1

VGA_DEVICE
ROM_SI
21 ROM_SI
ROM_SO 0 3D Device (Class Code 302h)
21 ROM_SO
ROM_SCLK
21 ROM_SCLK

1 VGA Device (Default)

2

RV159 RV160 RV161

20K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
@ OPT@ OPT@
1

B B
GPU Configuration FB Memory (DDR3L) ROM_SI ROM_SO ROM_SCLK STRAP0 STRAP1 STRAP2 STRAP3 STRAP4 VRAM X76 P/N VRAM Q'ty VRAM P/N
K4W4G1646E-BC1A 0x1
Samsung X7610212201 4
900MHz 256M x 16 PD 10K Samsung SA000063F20
H5TC4G63CFR-N0C 0x2 X7610212001 8
Single-Rank Hynix
900MHz 256M x 16 PD 15K
X7610212202 4
MT41J256M16LY-091G:N 0x6 Hynix SA00007DU10
Micron
900MHz 256M x 16 PD 34.8K X7610212101 8
N16S-GTR PD 4.99K PD 4.99K PU 49.9K Un-stuff Un-stuff Un-stuff Un-stuff
N16V-GMR1 K4W4G1646E-BC1A 0xF
Samsung X7610212203 4
900MHz 256M x 16 PU 45.3K Micron SA00007QJ00
H5TC4G63CFR-N0C 0xE N/A 8
Dual-Rank Hynix
900MHz 256M x 16 PU 34.8K
MT41J256M16LY-091G:N 0xA
Micron
900MHz 256M x 16 PU 15K

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 N16X_MISC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG411
Date: Thursday, January 14, 2016 Sheet 29 of 60
5 4 3 2 1
 5 4 3 2 1

UW1

RW2 1 2 6.2K_0402_1% RREF 1 24 VDD18 1U_0402_6.3V6K 2 1 CW1

USB20_N5 RW9 1 @ 2 0_0402_5% USB20_N5_R 2 RREF V18 23
9 USB20_N5 USB20_P5 USB20_P5_R DM XD_D7
RW10 1 @ 2 0_0402_5% 3 22
9 USB20_P5 DP SP14 SD_D2_R
+3VS 4 21
CARD_3V3 5 3V3_IN SP13 20 SD_D3_R
SDREG 6 CARD_3V3 SP12 19
7 SDREG SP11 18 SD_CMD_R
D 1 1 D
CW2 CW3 SD_WP 8 XD_CD# SP10 17
4.7U_0402_6.3V6M 0.1u_0201_10V6K 9 SP1 GPIO0 16
SD_D1_R 10 SP2 SP9 15 SD_CLK_R
2 2 1 SP3 SP8
LW1 CW4 SD_D0_R 11 14
USB20_N5 1 2 USB20_N5_R 1U_0402_6.3V6K 12 SP4 SP7 13 SD_CD#
1 2 SP5 SP6
2 25
USB20_P5 4 3 USB20_P5_R GND
4 3
EXC24CH900U_4P RTS5170-GRT_QFN24_4X4
EMC_NS@
FOR EMI

SD_D0_R RW3 1 @ 2 0_0402_5% SD_D0

C C
CW5 1 2 5.6P_0402_50V8-D
SD / MMC
EMC@
CARD_3V3
SD_D1_R RW4 1 @ 2 0_0402_5% SD_D1 JREAD1
CW6 1 2 5.6P_0402_50V8-D 4
VDD

0.1u_0201_10V6K
4.7U_0402_6.3V6M
EMC@ 1 1 SD_D0 7
SD_D1 8 DAT0
CW9 CW17 SD_D2 9 DAT1
SD_D2_R RW5 1 @ 2 0_0402_5% SD_D2 SD_D3 1 DAT2
CW7 1 2 5.6P_0402_50V8-D 2 2 CD/DAT3
SD_CD# 11
SD_WP 10 C/D
EMC@
W/P
Close to Connector SD_CMD 2
SD_D3_R RW6 1 @ 2 0_0402_5% SD_D3 SD_CLK 5 CMD
CW8 1 2 5.6P_0402_50V8-D CLK
3 12
6 VSS1 GND_1 13
EMC@
VSS2 GND_2
DEREN_404232501111RHF_NR
SD_CMD_R RW7 1 @ 2 0_0402_5% SD_CMD ME@
B CW11 1 2 5.6P_0402_50V8-D B

EMC@

SD_CLK_R RW8 1 2 0_0402_5% SD_CLK Close to Connector

CW12 1 2 5.6P_0402_50V8-D

EMC@
CARD_3V3

AZ5123-01F.R7GR_DFN1006P2X2

1
DW1

1
2
EMC_NS@

2
FOR ESD
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 Cardreader
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG411
Date: Thursday, January 14, 2016 Sheet 30 of 60
5 4 3 2 1

WWW.AliSaler.Com
 5 4 3 2 1

+5VS +5VS_CMOS_R

R271 1 @ 2 0_0603_5%

1
C1111
+5VS_CMOS
D 1U_0402_10V6K
3D@
2.285W, 0.457A D
2 U15 3D@
5 1 R282 1 3D@ 2 0_0603_5%
IN OUT
2 @

RF_NS@

RF_NS@
GND

2200P_0402_50V7K

47P_0402_50V8J
4.7U_0603_10V6-K
4 3 1 1 1
33 CMOS_ON# ENB OCB
SY6288D20AAC_SOT23-5

1
R273 2 2 2

C1112

C1113

C1114
100K_0402_5%
@

2 3D Camera DB Connector
For RF

+5VS_CMOS
C J3D C
1
+3VS 2 1
3 2
4 3
5 4
5
Prevent damage CPU from LAN surge 6
7 6
8 3D_FR 7
8
USB30_TX_P3 R293 1 3D@ 2 0_0402_5% USB30_TX_P3_R 3D@ C1115 1 2 0.1u_0201_10V6K USB30_TX_C_P3 R274 1 3D@ 2 0_0402_5% USB30_TX_R_P3 9 8
9 USB30_TX_P3 USB30_TX_N3 USB30_TX_N3_R USB30_TX_C_N3 USB30_TX_R_N3 9
R294 1 3D@ 2 0_0402_5% 3D@ C1116 1 2 0.1u_0201_10V6K R275 1 3D@ 2 0_0402_5% 10
9 USB30_TX_N3 10
11
USB30_RX_P3 R276 1 3D@ 2 0_0402_5% USB30_RX_R_P3 12 11
9 USB30_RX_P3 USB30_RX_N3 USB30_RX_R_N3 12
R277 1 3D@ 2 0_0402_5% 13
9 USB30_RX_N3 13
14
15 14
33,43 DMIC_CLK 15
33,43 DMIC_DATA 16
17 16
18 17
19 18 21
20 19 GND1 22
20 GND2
B B
L18 EMC_NS@
USB30_TX_C_P3 1 2 USB30_TX_R_P3 I-PEX_20374-020E-31
1 2
ME@
USB30_TX_C_N3 4 3 USB30_TX_R_N3
4 3
EXC24CH900U_4P
08/29: Double confirm if can
change to 18pin
L19 EMC_NS@
USB30_RX_P3 1 2 USB30_RX_R_P3
1 2

USB30_RX_N3 4 3 USB30_RX_R_N3
4 3
EXC24CH900U_4P

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 3D Camera
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG411
Date: Thursday, January 14, 2016 Sheet 31 of 60
5 4 3 2 1
 5 4 3 2 1

+3VS +3VS_TPM

RTPM1 1 TPM@ 2 0_0603_5% 1A

D D
1 1
1 CTPM3
CTPM4 CTPM1 0.1u_0201_10V6K
0.1u_0201_10V6K 10U_0603_6.3V6M TPM@
TPM@ 2 TPM@ 2
2

TPM
+3VS_TPM
UTPM1 TPM@
1 24
2 NC_1 VDD3 10
C 3 NC_2 VDD1 C
NC_3 Reserve for Nationz TPM
RTPM12 1 TPM@ 2 7 28 RTPM2 1 TPM@ 2 4.7K_0402_5%
0_0402_5% PP LPCPD# 27 SERIRQ_TPM RTPM5 1 TPM@ 2 0_0402_5%
SERIRQ LPC_AD0_TPM SERIRQ 7,44
6 26 RTPM6 1 TPM@ 2 0_0402_5%
NC_4 LAD0 LPC_AD1_TPM LPC_AD0 7,44
Reserve for Nationz TPM 9 23 RTPM7 1 TPM@ 2 0_0402_5%
NC_7 LAD1 LPC_FRAME#_TPM LPC_AD1 7,44
22 RTPM8 1 TPM@ 2 0_0402_5%
LFRAME# LPC_AD2_TPM LPC_FRAME# 7,44
4 20 RTPM9 1 TPM@ 2 0_0402_5%
GND_1 LAD2 LPC_AD3_TPM LPC_AD2 7,44
11 17 RTPM10 1 TPM@ 2 0_0402_5%
+3VALW GND_2 LAD3 LPC_AD3 7,44
18
GND_3 25 +3VS_TPM
RTPM11 1 TPM@ 2 5 GND_4 21
NC_5 LCLK CLK_PCI_TPM 7
0_0603_5% 8 19
12 NC_6 VDD2 15 TPM_CLKRUN# RTPM13 1 @ 2
NC_8 CLK_RUN# PM_CLKRUN# 7
Add for Nuvoton TPM 13 0_0402_5%
14 NC_9 16
NC_10 LRESET# PLT_RST# 11,20,37,40,44
Reserve for Nuvoton TPM

1
Z32H320TC-LPC-T28-LT1_TSSOP28 RTPM4
0_0402_5%
TPM@

2
B B

Nationz TPM Nuvoton TPM

RTPM2 Stuff NC

RTPM12 Stuff NC

RTPM11 NC Stuff

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 TPM
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG411
Date: Thursday, January 14, 2016 Sheet 32 of 60
5 4 3 2 1

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 5 4 3 2 1

LCD POWER CIRCUIT CMOS Camera

+3VS +3VS Need  short +3VS_CMOS_R
+LCDVDD +LCDVDD_CON J1 @
1 2
U5 1 2
5 1 R263 1 @ 2 W=60mils W=40 mils JUMP_43X39
IN OUT

RF_NS@
1 2 0_0805_5% +3VS_CMOS
GND @ LP2301ALT1G_SOT23-3

0.1u_0201_10V6K

33P_0402_50V8J
4.7U_0402_6.3V6M
C1 PCH_ENVDD 4 3 1 1 1 W=40mils
EN OCB

D
0.1u_0201_10V6K Q7 3 1 @ R3 1 @ 2
2 SY6288C20AAC_SOT23-5 0_0603_5%

0.01U_0201_10V6K
D D

@
2 2 2 1 1 1 1
C5 C3 C4

G
2
U5 EN PIN VIH MIN 1.5V

C121

C122

C123
0.1u_0201_10V6K 0.1u_0201_10V6K 10U_0603_6.3V6M
@ CD@ @
2 2 2 2

C6
CMOS_ON# R5 1 @ 2
100K_0402_5%
PCH_ENVDD For RF 1 1
4 PCH_ENVDD
C9 C10

1
0.01U_0201_25V6-K 0.1u_0201_10V6K
R1 EMC_NS@ @
100K_0402_5% 2 2
For EMI
Close to R5
2

R296 1 @ 2 0_0402_5% CMOS_ON# +3VS

8 PCH_CMOS_ON# CMOS_ON# 31

+3VS R297 1 @ 2 0_0402_5%

44 EC_CMOS_ON# EMI request

2
R8 R9
2

100K_0402_1% 100K_0402_1% DMIC_CLK DISPOFF# INVT_PWM

R10
PCH_ENBKL 1 2

470P_0201_50V7-K

470P_0201_50V7-K
R11 @ 4.7K_0402_5% @ @

100P_0201_25V8J
1

EMC_NS@

EMC_NS@
0_0402_5% @ 1 1 1

EMC@
1

EDP_AUX
R12 1 @ 2 0_0402_5% DISPOFF# V20B+ +LEDVDD EDP_AUX#
44 BKOFF# 2 2 2

C11

C12

C13
2A 80 mil 2A 80 mil

2
R14 1 @ 2 0_0402_5% ENBKL R17 1 @ 2 0_0805_5%
4 PCH_ENBKL ENBKL 44
R13 R15
1

C C

EMC@
CD@
100K_0402_1% 100K_0402_1%

4.7U_0805_25V6-K

0.1U_0201_25V6-K
R16 1 1
100K_0402_5% @ @

1
2

2 2 JEDP1

C14

C15
+LEDVDD 1
2 1
3 2
+3VS 4 3
CPU_EDP_TX0+ C19 1 2 0.1u_0201_10V6K EDP_TX0+ 5 4
EMI Request 4 CPU_EDP_TX0+ CPU_EDP_TX0- EDP_TX0- 5
C16 1 2 0.1u_0201_10V6K 6
4 CPU_EDP_TX0- 6
2

7
R18 CPU_EDP_TX1+ C17 1 2 0.1u_0201_10V6K EDP_TX1+ 8 7
4 CPU_EDP_TX1+ CPU_EDP_TX1- EDP_TX1- 8
1K_0402_5% C18 1 2 0.1u_0201_10V6K 9
4 CPU_EDP_TX1- 9
@ 10
CPU_EDP_AUX C20 1 2 0.1u_0201_10V6K EDP_AUX 11 10
4 CPU_EDP_AUX
1

CPU_EDP_AUX# C21 1 2 0.1u_0201_10V6K EDP_AUX# 12 11

INVT_PWM 4 CPU_EDP_AUX# 12
R19 1 @ 2 0_0402_5% 13
4 PCH_EDP_PWM 13
DISPOFF# 14
15 14
15
1

INVT_PWM 16
R20 17 16
100K_0402_5% +3VS 18 17
19 18
4 CPU_EDP_HPD 19
R21 1 @ 2 20
2

0_0402_5% 21 20
1 +LCDVDD_CON 21
W=60mils 22
EMC_NS@ C22 23 22
+3VS 23
680P_0402_50V7K 31,43 DMIC_DATA 24
2 25 24
31,43 DMIC_CLK 25
26
27 26
R182 1 2 0_0402_5% USB20_P4_R 28 27
9 USB20_P4 28
B R183 1 2 0_0402_5% USB20_N4_R 29 B
9 USB20_N4 29
+3VS_CMOS 30
31 30
W=40mils
Touch Screen C24
1 32 G1
G2
.047U_0201_6.3V6K DRAPH_FC5AF301-3181H
EMC_NS@ ME@
2
+5VS +5VS_TS

R26 1 TS@ 2 0_0402_5% EMI request

JTS1
1
C25 1
0.1u_0201_10V6K 2 1 7
TS@ R28 2 TS@ 1 0_0402_5% TS_RS 3 2 GND1
2 44 EC_TS_ON 3
4 8
R23 1 TS@ 2 0_0402_5% USB20_N6_CONN 5 4 GND2
9 USB20_N6 USB20_P6_CONN 5
R24 1 TS@ 2 0_0402_5% 6
9 USB20_P6 6
CVILU_CI1806M2HR0-NH For EMI
ME@ L12 EMC_NS@
USB20_N4 1 2 USB20_N4_R
1 2
Touch Screen
USB20_P4 4 3 USB20_P4_R
4 3
EXC24CH900U_4P
USB20_P6_CONN

USB20_N6_CONN
3

L15 +5VS_TS
USB20_P6 1 2 USB20_P6_CONN
1 2
1

A A
D2
USB20_N6 4 3 USB20_N6_CONN
1

4 3
EXC24CH900U_4P
EMC_NS@ D1
AZC199-02S.R7G_SOT23-3
2

EMC_NS@
AZ5725-01F.R7GR_DFN1006P2X2
2

EMC_NS@
For EMI Security Classification LC Future Center Secret Data Title
1

For EMI Issued Date 2015/08/20 Deciphered Date 2016/08/20 eDP/CMOS/Touch screen

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG411
Date: Thursday, January 14, 2016 Sheet 33 of 60
5 4 3 2 1
 5 4 3 2 1

L2 EMC@ EMC_NS@
HDMI_CLK-_C 1 2 HDMI_CLK-_CON 1 2
1 2 C26 3.3P_0402_50V8-C
EMC_NS@
HDMI_CLK+_C 4 3 HDMI_CLK+_CON 1 2
4 3 C27 3.3P_0402_50V8-C
EXC24CH900U_4P
+3VS
D L3 EMC@ EMC_NS@ D
HDMI_TX0-_C 1 2 HDMI_TX0-_CON 1 2
1 2 C28 3.3P_0402_50V8-C
EMC_NS@
HDMI_TX0+_C 4 3 HDMI_TX0+_CON 1 2
4 3 C29 3.3P_0402_50V8-C

5
EXC24CH900U_4P

G
Q1B D3
L4 EMC@ EMC_NS@ HDMI_DET 1 1 10 9 HDMI_DET
HDMI_TX1-_C 1 2 HDMI_TX1-_CON 1 2
1 2 C30 3.3P_0402_50V8-C 4 3 HDMICLK_R HDMIDAT_R 2 2 9 8 HDMIDAT_R

S
4 DDPB_CLK

D
EMC_NS@
HDMI_TX1+_C 4 3 HDMI_TX1+_CON 1 2 2N7002KDWH_SOT363-6 HDMICLK_R 4 4 7 7 HDMICLK_R
4 3

2
C31 3.3P_0402_50V8-C

G
EXC24CH900U_4P Q1A +5VS_HDMI 5 5 6 6 +5VS_HDMI

L5 EMC@ EMC_NS@ 3 3
HDMI_TX2-_C 1 2 HDMI_TX2-_CON 1 2 1 6 HDMIDAT_R

S
1 2 4 DDPB_DATA

D
C32 3.3P_0402_50V8-C 8
EMC_NS@ 2N7002KDWH_SOT363-6
HDMI_TX2+_C 4 3 HDMI_TX2+_CON 1 2
4 3 C33 3.3P_0402_50V8-C AZ1045-04F_DFN2510P10E-10-9
EXC24CH900U_4P EMC_NS@

For EMC
For EMC

C C
HDMI_CLK-_C R29 1 2 470_0402_5% +5VS +5VS_HDMI_F +5VS_HDMI
D5
HDMI_CLK+_C R30 1 2 470_0402_5% +5VS 2 F1
+3VS 1 1 2
HDMI_TX0-_C R31 1 2 470_0402_5% 3

2
D4 RB491D_SOT23-3 0.5A_6V_1206L050YRHF
HDMI_TX0+_C R32 1 2 470_0402_5% @

HDMI_TX1-_C R33 1 2 470_0402_5% @ LP2301ALT1G_SOT23-3

2
HDMI_TX1+_C R34 1 2 470_0402_5% BAT54S-7-F_SOT23-3 1 3 Q22

S
R35 1

1
2
Q12 D4 C34

G
1M_0402_5%
HDMI_TX2-_C R37 1 2 470_0402_5% 0.1u_0201_10V6K

G
1

2
HDMI_TX2+_C R38 1 2 470_0402_5% 2

2
3 1
4 HDMI_HPD 46 SUSP

D
R39 R40
1

D Q13 2N7002KW_SOT323-3 2.2K_0402_5% 2.2K_0402_5%

2
+3VS 2
G 2N7002KW_SOT323-3 R41

1
20K_0402_5%
S JHDMI1
3

HDMI_DET 19

1
R42 1 @ 2 18 HP_DET
17 +5V
100K_0402_5% HDMIDAT_R 16 DDC/CEC_GND
HDMICLK_R 15 SDA
14 SCL
13 Reserved
HDMI_CLK- C35 2 1 0.1u_0201_10V6K HDMI_CLK-_C R43 2 @ 1 0_0402_5% HDMI_CLK-_CON 12 CEC 20
4 HDMI_CLK- CK- GND1
11 21
B HDMI_CLK+ C36 2 1 0.1u_0201_10V6K HDMI_CLK+_C R44 2 @ 1 0_0402_5% HDMI_CLK+_CON 10 CK_shield GND2 22 B
4 HDMI_CLK+ CK+ GND3
HDMI_TX0- C37 2 1 0.1u_0201_10V6K HDMI_TX0-_C R45 2 @ 1 0_0402_5% HDMI_TX0-_CON 9 23
4 HDMI_TX0- D0- GND4
8
HDMI_TX0+ C38 2 1 0.1u_0201_10V6K HDMI_TX0+_C R46 2 @ 1 0_0402_5% HDMI_TX0+_CON 7 D0_shield
4 HDMI_TX0+ D0+
HDMI_TX1- C39 2 1 0.1u_0201_10V6K HDMI_TX1-_C R47 2 @ 1 0_0402_5% HDMI_TX1-_CON 6
4 HDMI_TX1- D1-
5
HDMI_TX1+ C40 2 1 0.1u_0201_10V6K HDMI_TX1+_C R48 2 @ 1 0_0402_5% HDMI_TX1+_CON 4 D1_shield
4 HDMI_TX1+ D1+
HDMI_TX2- C41 2 1 0.1u_0201_10V6K HDMI_TX2-_C R49 2 @ 1 0_0402_5% HDMI_TX2-_CON 3
4 HDMI_TX2- D2-
2
HDMI_TX2+ C42 2 1 0.1u_0201_10V6K HDMI_TX2+_C R50 2 @ 1 0_0402_5% HDMI_TX2+_CON 1 D2_shield
4 HDMI_TX2+ D2+
SINGA_2HE3Y37-000111F
ME@

Close to JHDMI1
D6 D7
HDMI_CLK+_CON 1 1 10 9 HDMI_CLK+_CON HDMI_TX1-_CON 1 1 10 9 HDMI_TX1-_CON

HDMI_CLK-_CON 2 2 9 8 HDMI_CLK-_CON HDMI_TX1+_CON 2 2 9 8 HDMI_TX1+_CON

HDMI_TX0+_CON 4 4 7 7 HDMI_TX0+_CON HDMI_TX2-_CON 4 4 7 7 HDMI_TX2-_CON

HDMI_TX0-_CON 5 5 6 6 HDMI_TX0-_CON HDMI_TX2+_CON 5 5 6 6 HDMI_TX2+_CON

A A
3 3 3 3

8 8

AZ1045-04F_DFN2510P10E-10-9 For EMC AZ1045-04F_DFN2510P10E-10-9

EMC_NS@ EMC_NS@ Security Classification LC Future Center Secret Data Title
Issued Date 2015/08/20 Deciphered Date 2016/08/20 HDMI_CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG411
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Date: Thursday, January 14, 2016
1
Sheet 34 of 60
 5 4 3 2 1

+IVDDO +RX_AVCC
+3VS +DP_3V3

LVG2 1 @ 2 0_0402_5%
RVG16 1 @ 2 0_0603_5%
1 1
1 CVG10 CVG15
10U_0603_6.3V6M 0.1u_0201_10V6K
CVG8 +DP_3V3 +DP_3V3 +IVDDO +RX_IVDD
10U_0603_6.3V6M 2 2
D 2 D

32

23

25

16
30
31
8

9
UVG1

OVDD1
OVDD2

IVDD33

IVDD1
IVDD2
IVDD3
IVDD4
IVDDO
DP_VGA_HPD 26 +IVDDO +RX_IVDD
4 DP_VGA_HPD HPD

CVG3 1 2 0.1u_0201_10V6K DRX0P 18 27 1 TVG1 @ RVG19 1 @ 2 0_0603_5%

4 VGA_TX0+ RX0P NC
CVG2 1 2 0.1u_0201_10V6K DRX0N 19
4 VGA_TX0- RX0N
1
CVG4 1 2 0.1u_0201_10V6K DRX1P 20 CVG16
4 VGA_TX1+ RX1P
CVG5 1 2 0.1u_0201_10V6K DRX1N 21 0.1u_0201_10V6K
4 VGA_TX1- RX1N
2

10
ISPSCL 11
CVG6 1 2 0.1u_0201_10V6K AUXP 15 ISPSDA
4 VGA_AUX RXAUXP
CVG7 1 2 0.1u_0201_10V6K AUXN 14 13
4 VGA_AUX# RXAUXN VGADDCCLK CRT_DDC_CLK 36
12
VGADDCSDA CRT_DDC_DAT 36
1 VGA_VS +IVDDO +DAC_VDDC
VSYNC VGA_HS VGA_VS 36
2
HSYNC VGA_HS 36
LVG4 1 @ 2 0_0402_5%
+DAC_VDDC

+RX_AVCC
1 1
C 4 CVG17 CVG11 C
17
22 AVCC
ASPVCC
IT6516BFN VDDAC 0.1u_0201_10V6K
2 2
4.7U_0402_6.3V6M

7 CRT_R
IORP CRT_R 36

@ TVG3 1 29 6 CRT_G
PCSDA IOGP CRT_G 36
@ TVG4 1 28
PCSCL
5 CRT_B
IOBP CRT_B 36

3 RVG3 1 2 200_0402_1%
RSET
RVG3 closed to pin3
@ TVG2 1 24
URDBG

GND
IT6516BFN-BX-0061_QFN32_4X4 CRT_R

33
B B

CRT_G

CRT_B

1
RVG25 RVG26 RVG27
75_0402_1% 75_0402_1% 75_0402_1%

2
CLOSE TO UVG1

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 DP to VGA (IT6516BFN)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG411
Date: Thursday, January 14, 2016 Sheet 35 of 60
5 4 3 2 1
 5 4 3 2 1

+CRT_VCC_CON
CRT Connector

2
1
+CRT_VCC_CON +5VS_HDMI
RPVG3
+5VS @
2.2K_0404_4P2R_5% +CRT_VCC RVG39 1 2 0_0603_5%
DVG1

3
4
@ 2 FVG1
CRT_DDC_DAT RVG4 1 2 22_0402_5% CRT_DDC_DAT_R 1 1 2 @ +CRT_VCC_CON
35 CRT_DDC_DAT
3 1
D CRT_DDC_CLK RVG5 1 2 22_0402_5% CRT_DDC_CLK_R RB491D_SOT23-3 0.5A_6V_1206L050YRHF CVG34 D
35 CRT_DDC_CLK

1
0.1u_0201_10V6K
CD@ DVG2
1 1 W=40mils

1
CVG43 CVG44 2 AZ5725-01F.R7GR_DFN1006P2X2
100P_0201_25V8J 68P_0201_50V8-J EMC_NS@
@ @
2 2

2
2
JCRT1
6
11
LVG6 1 2 EMC@ CRT_R_CON 1
35 CRT_R
BLM15BA220SN1D_2P 7 For EMC
CRT_DDC_DAT_R 12
LVG7 1 2 EMC@ CRT_G_CON 2
35 CRT_G
BLM15BA220SN1D_2P 8
HSYNC_CON 13
LVG8 1 2 EMC@ CRT_B_CON 3
35 CRT_B
BLM15BA220SN1D_2P 9
VSYNC_CON 14

15P_0402_50V8J
CVG35

15P_0402_50V8J
CVG36

15P_0402_50V8J
CVG37

15P_0402_50V8J
CVG38

15P_0402_50V8J
CVG39

15P_0402_50V8J
CVG40
1 1 1 1 1 1 4
10 G 16
CRT_DDC_CLK_R 15 G 17
5
2 2 2 2 2 2
1
CVG41 SUYIN_070546HR015M25KZR
100P_0201_25V8J ME@
EMC@ EMC@ EMC@ EMC@ EMC@ EMC@ @
2

C C

VGA_HS RVG32 1 @ 2 0_0402_5% HSYNC_CON

35 VGA_HS

1
CVG42
10P_0201_50V8F
2

VGA_VS RVG33 1 @ 2 0_0402_5% VSYNC_CON

35 VGA_VS

1
CVG45
10P_0201_50V8F
2

B B

DVG3 DVG4
CRT_B_CON 1 1 10 9 CRT_B_CON VSYNC_CON 1 1 10 9 VSYNC_CON

CRT_G_CON 2 2 9 8 CRT_G_CON HSYNC_CON 2 2 9 8 HSYNC_CON

CRT_R_CON 4 4 7 7 CRT_R_CON CRT_DDC_CLK_R 4 4 7 7 CRT_DDC_CLK_R

5 5 6 6 CRT_DDC_DAT_R 5 5 6 6 CRT_DDC_DAT_R

3 3 3 3

8 8

AZ1045-04F_DFN2510P10E-10-9 AZ1045-04F_DFN2510P10E-10-9
EMC_NS@ EMC_NS@
A A
For EMC

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 CRT_CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG411
WWW.AliSaler.Com 5 4 3 2
Date: Thursday, January 14, 2016
1
Sheet 36 of 60
 5 4 3 2 1

+3VALW  TO  +3VALW_LAN

+3VALW_LAN  rising  t i me ( 10 %~90 %): 
+3VALW +3VALW_LAN
0.5ms＜s pec＜ 10 0m s +3VALW_LAN +LAN_VDDREG
Need  short
RL1 @
JL1 1 2 @ width : 40 mils 1 2
1 2
JUMP_43X79 0_0603_5%
D D
1 1
+3VALW

0.1u_0201_10V6K

0.1u_0201_10V6K
LP2301ALT1G_SOT23-3 CL4 CL5 CL1 CL2

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M
1 1 CL6 1 CL7 1 4.7U_0402_6.3V6M 0.1u_0201_10V6K

D
Q14 3 1 @ @ CD@

0.01U_0201_10V6K
1
2 2

0.1u_0201_10V6K
RL2 1 CL8 CL9 1
100K_0402_5% 2 2 2 2

G
2
@
@ @
2

2 2
RL3 1 @ 2 @ @
44 LAN_PWR_ON#
47K_0402_5%
Close to Pin11 Close to Pin32 Close to Pin11 Close to Pin32
+3VALW_LAN +3VS

+3VALW_LAN

2
@

2
RL4

G
2
10K_0402_5% QL1
RL5 manual change the Codec PN to RTL8111GUL-CG
10K_0402_5% UL1

1
@ LAN_CLKREQ#_R 1 3 @
LAN_CLKREQ# 10

S
1
2N7002KW_SOT323-3
RL7 1 @ 2 0_0402_5% PCIE_WAKE#_R
11,40,44 PCIE_WAKE#
40,44 LAN_WAKE# RL6 1 @ 2 0_0402_5%
33 RL18 1 @ 2 0_0402_5%
32 +3VALW_LAN GND 16 CLK_PCIE_LAN#
C C
AVDD33_2 REFCLK_N CLK_PCIE_LAN CLK_PCIE_LAN# 10
RL8 1 2 31 RSET 15
+LAN_VDD10 RSET REFCLK_P PCIE_PTX_C_DRX_N5 CLK_PCIE_LAN 10
2.49K_0402_1% 30 14
LAN_XTALO AVDD10 HSIN PCIE_PTX_C_DRX_P5 PCIE_PTX_C_DRX_N5 9
29 13
LAN_XTALI CKXTAL2 HSIP LAN_CLKREQ#_R PCIE_PTX_C_DRX_P5 9
28 12
+3VS TL3 @ 1 27 CKXTAL1 CLKREQB 11 +3VALW_LAN
LAN_PWR_ON# @ LAN_DISABLE# LED0 AVDD33_1 LAN_MDI3-
RL121 2 26 10
LED1/GPIO MDIN3 LAN_MDI3+ LAN_MDI3- 38
0_0402_5% TL4 @ 1 25 9
LED2 MDIP3 LAN_MDI3+ 38
1

+LAN_REGOUT 24 8 +LAN_VDD10
RL9 +LAN_VDDREG 23 REGOUT AVDD10_2 7 LAN_MDI2-
+LAN_VDD10 VDDREG MDIN2 LAN_MDI2+ LAN_MDI2- 38
1K_0402_1% 22 6
PCIE_WAKE#_R DVDD10 MDIP2 LAN_MDI1- LAN_MDI2+ 38
21 5
LANWAKEB MDIN1 LAN_MDI1+ LAN_MDI1- 38
ISOLATE# 20 4
LAN_MDI1+ 38
2

PLT_RST# 19 ISOLATEB MDIP1 3 +LAN_VDD10

11,20,32,40,44 PLT_RST# PERSTB AVDD10_1
9 PCIE_PRX_DTX_N5 CL10 1 2 0.1u_0201_10V6K PCIE_PRX_C_DTX_N5 18 2 LAN_MDI0-
LAN_PWR_ON# HSON MDIN0 LAN_MDI0- 38
ISOLATE# RL10 1 @ 2 9 PCIE_PRX_DTX_P5 CL11 1 2 0.1u_0201_10V6K PCIE_PRX_C_DTX_P5 17 1 LAN_MDI0+
HSOP MDIP0 LAN_MDI0+ 38
0_0402_5% CL10 close to Pin18
1

RL11 CL11 close to Pin17
15K_0402_5%
@
2

RTL8111GUL-CG QFN 32P

8111GUL@

B B

LAN_XTALI
For  RTL8111GUL(SWR  mode,  reserved)
LAN_XTALO_R 1 2 LAN_XTALO For RTL8111H (LDO mode)
RL21 1K_0402_5% +LAN_VDD10
YL1 LL1 1 2 8111GUL@
2.2UH_NLC252018T-2R2J-N_5%
1 4
OSC1 GND2 +LAN_REGOUT RL20 1 2 8111H@
2 3 0_0805_5%
GND1 OSC2
1 1 1 1 1 1 1 1
1 1
CL12 25MHZ_10PF_7V25000014 CL13 CL15 CL16 CL17 CL18 CL19 CL20 CL21 CL22
12P_0402_50V8-J 15P_0402_50V8J 4.7U_0402_6.3V6M 0.1u_0201_10V6K 0.1u_0201_10V6K 0.1u_0201_10V6K 0.1u_0201_10V6K 0.1u_0201_10V6K 1U_0402_6.3V6K 0.1u_0201_10V6K
2 2 2 CD@ 2 2 2 2 2
2 2

Close to Pin3, 8, 22, 30 Close  to  Pin22(Reserved)

Layout Note: LL1 must be
within  200mil  to  Pin24,
CL15,CL16 must  be  within
200mil  to  LL1
+LAN_REGOUT: Width =60mil
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 LAN_RTL8111H_CG
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG411
Date: Thursday, January 14, 2016 Sheet 37 of 60
5 4 3 2 1
 5 4 3 2 1

DL1/DL2
1'S PN:SC300003M00
TL1
24 1 MCT
D MCT1 TCT1 D
LAN_MDI0+ 23 2 LAN_MDO0+
37 LAN_MDI0+ MX1+ TD1+
DL1
LAN_MDI2+ 1 10 LAN_MDI2+ LAN_MDI0- 22 3 LAN_MDO0-
LINE1IN LINE1OUT 37 LAN_MDI0- MX1- TD1-

1
EMC@
LAN_MDI2- 2 9 LAN_MDI2- 21 4 MCT RL17
LINE2IN LINE2OUT MCT2 TCT2 20_0603_5%

1
3 8 LAN_MDI1+ 20 5 LAN_MDO1+
GND1 GND2 37 LAN_MDI1+ MX2+ TD2+ DL3

1
2
LAN_MDI3+ 4 7 LAN_MDI3+ LAN_MDI1- 19 6 LAN_MDO1- PDT5061_DO-214AA
LINE3IN LINE3OUT 37 LAN_MDI1- MX2- TD2- EMC@

2
LAN_MDI3- 5 6 LAN_MDI3- 18 7 MCT EMC
LINE4IN LINE4OUT MCT3 TCT3

2
11 13 LAN_MDI2+ 17 8 LAN_MDO2+
GND3 GND5 37 LAN_MDI2+ MX3+ TD3+
12 LAN_MDI2- 16 9 LAN_MDO2-
GND4 37 LAN_MDI2- MX3- TD3-
AZ3133-08F.R7G_DFN3020P10E10 15 10 MCT
EMC_NS@ MCT4 TCT4
1 1
LAN_MDI3+ 14 11 LAN_MDO3+ CL32 CL25
37 LAN_MDI3+ MX4+ TD4+ 0.022U_0603_50V7K 1000P_1206_2KV7-K
LAN_MDI3- 13 12 LAN_MDO3- EMC@ EMC@
37 LAN_MDI3- MX4- TD4- 2 2
1 EMC
DL2 CL24
C C
LAN_MDI1- 1 10 LAN_MDI1- 0.01U_0201_25V6-K BOTH_GST5009 LF
LINE1IN LINE1OUT EMC@
LAN_MDI1+ 2 9 LAN_MDI1+ 2
LINE2IN LINE2OUT
3 8 EMC
GND1 GND2
LAN_MDI0- 4 7 LAN_MDI0- CHASSIS1_GND
LINE3IN LINE3OUT
LAN_MDI0+ 5 6 LAN_MDI0+
LINE4IN LINE4OUT
11 13
GND3 GND5
12
GND4
AZ3133-08F.R7G_DFN3020P10E10
EMC_NS@
JRJ1 ME@
12
GND_4
Place Close to TL1
11
GND_3
EMC
10
LAN_MDO0+ 1 GND_2
PR1+ 9
B B
LAN_MDO0- 2 GND_1
PR1-
LAN_MDO1+ 3
PR2+ CHASSIS1_GND
LAN_MDO2+ 4
PR3+
LAN_MDO2- 5
PR3-
RL14 1 @ 2 0_0603_5% LAN_MDO1- 6
PR2-
RL15 1 @ 2 0_0603_5% LAN_MDO3+ 7
PR4+
RL16 1 @ 2 0_0603_5% LAN_MDO3- 8
PR4-
EMC
SANTA_130460-3

CHASSIS1_GND

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 LAN_Transformer
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG411
Date: Thursday, January 14, 2016 Sheet 38 of 60
5 4 3 2 1

WWW.AliSaler.Com
 5 4 3 2 1

R175 1 @ 2 0_0402_5% REMOTE1+

Close to U1 REMOTE2+
REMOTE+_R R176 1 @ 2 0_0402_5% REMOTE2+ REMOTE1+
Near GPU&VRAM 1
Near CPU core

1
REMOTE+_R 1 C46 C

1
1 C45 C 100P_0201_25V8J 2 Q16
C44 REMOTE-_R R177 1 @ 2 0_0402_5% REMOTE2- 100P_0201_25V8J 2 Q15 @ B MMBT3904WH_SOT323-3
2200P_0201_25V7-K @ B MMBT3904WH_SOT323-3 2 E @

3
@ 2 E @ REMOTE2-

3
2 REMOTE-_R R178 1 @ 2 0_0402_5% REMOTE1- REMOTE1-

+3VALW
D REMOTE+/-_R, REMOTE1+/-, REMOTE2+/-: +3VALW D

Trace width/space:10/10 mil Near CPU

Trace length:<8"

1
R36
13.7K_0402_1% R25
13.7K_0402_1%

2
NTC_V1

2
NTC_V2
SMSC thermal sensor

1
R287
placed near DIMM 100K_0402_1%_NCP15WF104F03RC
OPT@
R288
100K_0402_1%_NCP15WF104F03RC
+3VS

2
U1 @

2
1 8 EC_SMB_CK2
VDD SCL EC_SMB_CK2 7,20,44

2
1 REMOTE+_R 2 7 EC_SMB_DA2 R184 R185
D+ SDA EC_SMB_DA2 7,20,44
C47 0_0402_5% 0_0402_5%
0.1u_0201_10V6K REMOTE-_R 3 6 OPT@ @
@ D- ALERT#

1
2 R51 2 @ 1 4 5
+3VS T_CRIT# GND
10K_0402_5%
NCT7718W_MSOP8
EC_AGND
Address 1001_101xb for layout optimized, change the EC_AGND to GND

C C

+5VLP +5VLP
+5VLP

HW thermal sensor
2

2
1 R252 R253
C7 21.5K_0402_1% 21.5K_0402_1%
0.1u_0201_10V6K @ @
@
1

1
2
U4 @
1 8 TMSNS1 R196 1 @ 2 0_0402_5% NTC_V1
VCC TMSNS1 NTC_V1 44
2 7 PHYST1 R6 1 @ 2 10K_0402_5%
GND RHYST1
3 6 TMSNS2 R197 1 @ 2 0_0402_5% NTC_V2
44,54,55 EC_ON OT1 TMSNS2 NTC_V2 44
4 5 PHYST2 R7 1 @ 2 10K_0402_5%
OT2 RHYST2
G718TM1U_SOT23-8

B over temperature threshold: B

RSET=3*RTMH
92+/-30C
Hysteresis temperature threshold.
RHYST=(RSET*RTML)/(3*RTML-RSET)
56+/-30C

FAN Conn
+5VS

JFAN1
R52 1 @ 2 0_0603_5% +5VS_FAN 1
2 1
44 EC_FAN_SPEED 2

0.1u_0201_10V6K
@ 3
4 3
1 1 44 EC_FAN_ANTI 4
C49 44 EC_FAN_PWM 5
10U_0805_10V6K 6 5
7 GND1
2 2 GND2

C50
ACES_50273-0050N-001
ME@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 Thermal sensor/FAN CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG411
Date: Thursday, January 14, 2016 Sheet 39 of 60
5 4 3 2 1
 A B C D E

Mini-Express Card(WLAN/WiMAX)
+3VS
+3VS_WLAN

+3VS +3VS_WLAN
Need  short
J2 @ JWLAN1
1 1

1
1 2 1 2
1 2 3 GND1 3.3VAUX1 4 R258 R259
9 USB20_P7 USB_D+ 3.3VAUX2
JUMP_43X79 1 5 6 1 @ T2 49.9K_0402_1% 49.9K_0402_1%
9 USB20_N7 USB_D- LED#1
C53 7 8
0.1u_0201_10V6K 9 GND2 PCM_CLK 10

2
@ 11 SDIO_CLK PCM_SYNC 12
2 13 SDIO_CMD PCM_IN 14
15 SDIO_DAT0 PCM_OUT 16 1 @ T3
17 SDIO_DAT1 LED#2 18
19 SDIO_DAT2 GND11 20
21 SDIO_DAT3 UART_WAKE 22 UART_RX_DEBUG_R R256 1 @ 2 0_0402_5%
SDIO_WAKE UART_RX UART_RX_DEBUG 8
23
SDIO_RESET

KEY E
25 PIN24~PIN31 NC PIN 24
27 26
29 28
31 30

33 32 UART_TX_DEBUG_R R257 1 @ 2 0_0402_5%

GND3 UART_TX UART_TX_DEBUG 8
35 34
9 PCIE_PTX_C_DRX_P6 PETP0 UART_CTS
37 36
9 PCIE_PTX_C_DRX_N6 PETN0 UART_RTS EC_TX_RSVD
39 38 R62 1 @ 2 0_0402_5%
41 GND4 RSRVD10 40 EC_RX_RSVD R63 1 @ 2 0_0402_5%
9 PCIE_PRX_DTX_P6 PERP0 RSRVD11
43 42
9 PCIE_PRX_DTX_N6 PERN0 RSRVD9
45 44 R88 1 @ 2 0_0402_5%
GND5 COEX3 EC_RX 44
47 46
10 CLK_PCIE_WLAN REFCLKP0 COEX2
49 48
10 CLK_PCIE_WLAN# REFCLKN0 COEX1 SUSCLK_R
2 51 50 R55 1 @ 2 0_0402_5% 2
WLAN_CLKREQ_Q# GND6 SUSCLK PLT_RST# SUSCLK 10
10 WLAN_CLKREQ# R61 1 @ 2 0_0402_5% 53 52
PCIE_WAKE#_WLAN CLKEQ0# PERSTO# BT_OFF# PLT_RST# 11,20,32,37,44
R262 1 @ 2 0_0402_5% 55 54 R53 1 2 1K_0402_5%
11,37,44 PCIE_WAKE# PEWAKE0# RSRVD/W_DISABLE#2 WLAN_OFF# PCH_BT_OFF# 8
57 56 R56 1 @ 2 0_0402_5%
GND7 W_DISABLE#1 PCH_WLAN_OFF# 8
R57 1 @ 2 0_0402_5%
37,44 LAN_WAKE#
59 58 WLAN_SMB_DATA R58 1 @ 2 0_0402_5%
RSRVD/PETP1 I2C_DATA WLAN_SMB_CLK SMB_DATA_S3 7,18
61 60 R59 1 @ 2 0_0402_5%
RSRVD/PETN1 I2C_CLK SMB_CLK_S3 7,18
63 62
65 GND8 ALERT 64 EC_TX_R R89 1 @ 2 0_0402_5%
RSRVD/PERP1 RSRVD6 EC_TX 44
67 66
69 RERVD/PERN1 RSRVD7 68 +3VS_WLAN
GND9 RSRVD8

1
71 70
73 RSRVD1 RSRVD12 72 R186
75 RSRVD2 3.3VAUX3 74 100K_0402_5%
GND10 3.3VAUX4
77 76

2
GND15 GND14

LCN_DAN05-67406-0102
ME@

3 3

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 NGFF WLAN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
CG411
WWW.AliSaler.Com
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Thursday, January 14, 2016 Sheet 40 of 60
A B C D E
 A B C D E

+USB_VCCA

C55 1 2

+
220U_6.3V_M

C1117 1 2
@ 47U_0805_6.3V6-M

C125 1 2
@ 1U_0402_10V6K

1 LEFT SIDE USB3.0 PORT x1 C127

@
1 2
1U_0402_10V6K
1

JUSB1 ME@
USB30_TX_P1 C126 1 2 0.1u_0201_10V6K USB30_TX_C_P1 R95 1 @ 2 0_0402_5% USB30_TX_R_P1 9
9 USB30_TX_P1 StdA_SSTX+
1
+5VALW +USB_VCCA USB30_TX_N1 C124 1 2 0.1u_0201_10V6K USB30_TX_C_N1 R96 1 @ 2 0_0402_5% USB30_TX_R_N1 8 VBUS
9 USB30_TX_N1 USB20_P1 USB20_P1_R StdA_SSTX-
U2 R97 1 @ 2 0_0402_5% 3
9 USB20_P1 D+
5 1 7
IN OUT USB20_N1 R93 1 @ 2 0_0402_5% USB20_N1_R 2 GND_DRAIN 10
1 9 USB20_N1 D- GND_1
C128 2 USB30_RX_P1 R94 1 @ 2 0_0402_5% USB30_RX_R_P1 6 11
1U_0402_6.3V6K GND 9 USB30_RX_P1 StdA_SSRX+ GND_2
4 12
4 3 USB_OC1# USB30_RX_N1 R98 1 @ 2 0_0402_5% USB30_RX_R_N1 5 GND_5 GND_3 13
2 44,45 USB_ON# ENB OCB USB_OC1# 9 9 USB30_RX_N1 StdA_SSRX- GND_4
SY6288D20AAC_SOT23-5 1 SUYIN_020053GR009M2736L
C140
1000P_0201_50V7-K
Low Active 2A EMC_NS@
2

2 2

L13 EMC@
USB30_RX_P1 1 2 USB30_RX_R_P1
1 2

USB30_RX_N1 4 3 USB30_RX_R_N1
4 3
EXC24CH900U_4P
+USB_VCCA D12 EMC_NS@ USB20_P1_R
L16 EMC@ USB30_RX_R_N1 9 10 1 1USB30_RX_R_N1
USB30_TX_C_P1 1 2 USB30_TX_R_P1 USB20_N1_R

AZ5725-01F.R7GR_DFN1006P2X2
1 2 USB30_RX_R_P1 8 9 2 2 USB30_RX_R_P1

1
D11

2
USB30_TX_C_N1 4 3 USB30_TX_R_N1 USB30_TX_R_N1 7 7 4 4USB30_TX_R_N1

1
4 3 D13
EXC24CH900U_4P USB30_TX_R_P1 6 6 5 5 USB30_TX_R_P1 AZC199-02S.R7G_SOT23-3
EMC_NS@
L8 EMC@ 3 3

2
USB20_P1 1 2 USB20_P1_R
1 2 EMC_NS@ 8

2
USB20_N1 4 3 USB20_N1_R AZ1045-04F_DFN2510P10E-10-9
3 4 3 3
EXC24CH900U_4P

1
EMC EMC

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 USB3.0 PORT (LEFT)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG411
Date: Thursday, January 14, 2016 Sheet 41 of 60
A B C D E
 A B C D E F G H

SATA HDD Conn.

FOR 14"
JHDD1

10
SATA ODD Conn.
SATA_PTX_DRX_P0 C66 1 2 0.01U_0201_10V6K SATA_PTX_C_DRX_P0 9 10
9 SATA_PTX_DRX_P0 9
SATA_PTX_DRX_N0 C67 1 2 0.01U_0201_10V6K SATA_PTX_C_DRX_N0 8
9 SATA_PTX_DRX_N0 8
7 12
1 SATA_PRX_DTX_N0 C68 1 2 0.01U_0201_10V6K SATA_PRX_C_DTX_N0 6 7 GND2 1
9 SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 C69 1 2 0.01U_0201_10V6K SATA_PRX_C_DTX_P0 5 6 JODD1
9 SATA_PRX_DTX_P0 4 5 1
3 4 11 SATA_PTX_DRX_P1 14@ C70 1 2 0.01U_0201_10V6K SATA_PTX_C_DRX_P1_14 2 GND_1
3 GND1 9 SATA_PTX_DRX_P1 RX+
2 SATA_PTX_DRX_N1 14@ C71 1 2 0.01U_0201_10V6K SATA_PTX_C_DRX_N1_14 3
2 9 SATA_PTX_DRX_N1 RX-
1 4
+5VS +5VS_HDD 1 SATA_PRX_DTX_N1 14@ C72 1 2 0.01U_0201_10V6K SATA_PRX_C_DTX_N1_14 5 GND_2
Need  short ELCO_006809610010846 9 SATA_PRX_DTX_N1 SATA_PRX_DTX_P1 14@ C73 1 2 0.01U_0201_10V6K SATA_PRX_C_DTX_P1_14 6 TX-
9 SATA_PRX_DTX_P1 7 TX+
ME@ GND_3
J3 1 2 @
1 2 8
JUMP_43X79 9 DP
+5V_ODD 10 +5V_1
11 +5V_2 14
12 MD GND1 15
13 GND_4 GND2
GND_5
+5VS_HDD SUYIN_127382FB013S255ZL
ME@

1 1 1 1 1
C74 C76 C75 C77 C78
33P_0201_50V8-J 33P_0201_50V8-J 0.1u_0201_10V6K 10U_0805_10V6K 10U_0805_10V6K
@ @ @
2 2 2 2 2

FOR 15"
2 2

For EMC SATA ODD FFC Conn

JODD2
1
SATA_PTX_DRX_P1 15@ C79 1 2 0.01U_0201_10V6K SATA_PTX_C_DRX_P1_15 2 1
SATA_PTX_DRX_N1 15@ C80 1 2 0.01U_0201_10V6K SATA_PTX_C_DRX_N1_15 3 2
4 3
SATA_PRX_DTX_N1 15@ C81 1 2 0.01U_0201_10V6K SATA_PRX_C_DTX_N1_15 5 4
SATA_PRX_DTX_P1 15@ C82 1 2 0.01U_0201_10V6K SATA_PRX_C_DTX_P1_15 6 5
7 6 9
+5V_ODD 8 7 GND1 10
8 GND2
HIGHS_FC1AF081-1151H
ME@

+5VS +5V_ODD
3
Need  Short 3
J4 @
1 2
1 2
10U_0805_10V6K

0.1u_0201_10V6K
JUMP_43X79
1 1

2 2
C85

C86

CD@

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 HDD/ODD CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG411
Date: Thursday, January 14, 2016 Sheet 42 of 60
A B C D E F G H

WWW.AliSaler.Com
 5 4 3 2 1

+3VS

+3VS +3VALW_PCH RA3 1 @ 2 0_0603_5%

+3VALW +5VA AVDD_HP
RA2 1 @ 2 0_0603_5% +3.3VD RA44 1 @ 2 0_0402_5%

0.1u_0201_10V6K

0.1u_0201_10V6K
+3VS RA5 1 @ 2 0_0603_5% AVDD_HP 2 2
+3VL
RA11 1 @ 2 0_0402_5% DVDD_IO
RA43 1 @ 2 0_0603_5%
+5VS 1 1

CA11

CA12
0.1u_0201_10V6K
CA1 2
RA7 1 @ 2 0_0603_5% +5VA

RA10 1 @ 2 0_0603_5% +5VD 1 Close to Pin28 Close to Pin24

D Close to Pin3 D

Close to Pin7
DA1
44 BEEP# 2
0.1u_0201_10V6K CA16 close to Pin18

0.1u_0201_10V6K

4.7U_0402_6.3V6M
1 PC_BEEP1 CA2 1 2 PC_BEEP 2 1 CA17 close to Pin2
Close to Pin27

1
8 PCH_BEEP 3
RA14
1 2

CD@
BAT54CW_SOT323-3 10K_0402_5%

0.1u_0201_10V6K

1U_0402_6.3V6K
change the Codec PN to CX11802-33Z,, symbol check ok

CA3

CA4
2 1
UA1

0.1u_0201_10V6K

2.2U_0402_6.3V6M
2

2 1
HDA_RST_AUDIO# 9 3 FILT_1.8V
8 HDA_RST_AUDIO# RESET# FILT_1.8V 7 DVDD_IO 1 2
VDD_IO

CA7

CA8
2
HDA_BITCLK_AUDIO VDDO_3.3 1 2

CA5

CA6
5 18 +3.3VD
8 HDA_BITCLK_AUDIO BIT_CLK DVDD_3.3
HDA_SYNC_AUDIO 8 27 AVDD_3.3
8 HDA_SYNC_AUDIO SYNC AVDD_3.3 29 VREF_1.65V
33_0402_5% 1 RA16 2 SDATA_IN 6 VREF_1.65V 28 +5VA
8 HDA_SDIN0 HDA_SDOUT_AUDIO SDATA_IN AVDD_5V
4

0.1u_0201_10V6K

1U_0402_6.3V6K
8 HDA_SDOUT_AUDIO SDATA_OUT MICBIASB
CX20751-11Z
+3.3VD

2 1
PC_BEEP 10 12 SPK_L+
SPKR_MUTE# 39 PC_BEEP LEFT+ 14 SPK_L-
SPKR_MUTE# LEFT- DA2

4LINE_B_R
3LINE_B_L
SPK_R+ 1 2

CA9

CA10
JSENSE 38 17 BAT54AW_SOT323-3
JSENSE RIGHT+
2

1
37 15 SPK_R- @
GPIO1/PORTC_R_MIC RIGHT-

1
RA15
5.11K_0402_1% 36 35 RA42 RA41
33_0402_5% 1 RA18 2 DMIC_CLK_R 40 MUSIC_REQ/GPIO0/PORTC_L_MIC MICBIASC 34 MICBIASB 0_0402_5% 0_0402_5%
31,33 DMIC_CLK DMIC_CLK/MUSIC_REQ/GPIO0 MICBIASB
Close to Pin29
0_0402_5% 1 @ 2 DMIC_DATA_R 1 @ @ RPA2
31,33 DMIC_DATA
1

RA19 DMIC_DAT/GPIO1 33 LINE_B_R 100_0404_4P2R_1%

2
PLUG_IN RA17 1 2 JSENSE 0.1u_0201_10V6K PORTB_R_LINE 32 LINE_B_L
39.2K_0402_1% +5VD 1 2 11 PORTB_L_LINE

1
2
CA13 CLASS-D_REF 30 PORTD_A_MIC
C PORTD_A_MIC C
RA36 1 2 13 31 PORTD_B_MIC
20K_0402_1% 16 LPWR_5.0 PORTD_B_MIC
RPWR_5.0

1
3K_0402_1%

3K_0402_1%
25 RING2_CONN 1 1
HGNDA

RA37

RA38
CA14 1 2 1U_0402_6.3V6K 19 26 RING3_CONN
20 FLY_P HGNDB CA35 CA36
FLY_N 24 AVDD_HP 4.7U_0603_10V6-K 4.7U_0603_10V6-K
CA17 1 2 2.2U_0402_6.3V6M 21 AVDD_HP 2 2 RPA3

2
AVEE 23 HPOUT_R 1 4 HP_OUTR
41 PORTA_R 22 HPOUT_L 2 3 HP_OUTL
GND PORTA_L
82.5_0404_4P2R_1%

+5VD CX11802-33Z QFN LOW POWER CODEC

CD@

CD@

RPA1
PORTD_A_MIC 2 3 CA39 1 2 2.2U_0402_6.3V6M RING3_CONN
PORTD_B_MIC 1 4 CA40 1 2 2.2U_0402_6.3V6M RING2_CONN
0.1u_0201_10V6K

0.1u_0201_10V6K
4.7U_0603_10V6-K

4.7U_0603_10V6-K

1 1 2 2 RA1 1 @ 2 0_0402_5%
100_0404_4P2R_1%
RA4 1 EMC@ 2 0_0402_5%
2 2 1 1
CA15

RA6 1 @ 2 0_0402_5%
CA16

CA18

CA19

RA9 1 EMC@ 2 0_0402_5%

JSPK1
RA12 1 @ 2 0_0402_5% 15_0402_5% 1 CD@ 2 RA25 SPK_R+ RA26 EMC@1 2 PBY160808T-221Y-N_2P SPK_R+_CONN 1
15_0402_5% 1 CD@ 2 RA29 SPK_R- RA31 EMC@1 2 PBY160808T-221Y-N_2P SPK_R-_CONN 2 1
RA13 1 @ 2 0_0402_5% 15_0402_5% 1 CD@ 2 RA32 SPK_L+ RA30 EMC@1 2 PBY160808T-221Y-N_2P SPK_L+_CONN 3 2
15_0402_5% 1 CD@ 2 RA33 SPK_L- RA34 EMC@1 2 PBY160808T-221Y-N_2P SPK_L-_CONN 4 3
Close to Pin11,13,16 4
5
GND1

EMC@

EMC@

EMC@

EMC@
CD@

CD@

CD@

CD@
GND GNDA 6
GND2

220P_0201_25V7-K

220P_0201_25V7-K

220P_0201_25V7-K

220P_0201_25V7-K

470P_0201_50V7-K

470P_0201_50V7-K

470P_0201_50V7-K

470P_0201_50V7-K
+3.3VD

Use 250mils wide trace bridging 2 2 2 2 1 1 1 1 ACES_88231-04001

AGND and DGND at codec ME@

1 1 1 1 2 2 2 2

CA31

CA32

CA33

CA34
B RA24 1 @ 2 B
1

CA27

CA28

CA29

CA30
0_0402_5%
RA28
47K_0402_5%
RB751V-40_SOD323-2 @
HDA_RST_AUDIO# DA3 1 2 @
2

SPKR_MUTE#
RB751V-40_SOD323-2
EC_MUTE# DA4 1 2 @
44 EC_MUTE#

Audio Jack HP_OUTR

HP_OUTL
RA45 1
RA46 1
@
@
2 0_0402_5%
2 0_0402_5%
HP_OUTR_R
HP_OUTL_R
RA35 1 @ 2
0_0402_5% RING3_CONN

RING2_CONN JHP1
RING2_CONN 3
HP_OUTL_R G/M
RA47 1 @ 2 @ 1 2 CA41 HP_OUTL_R 1
HP_OUTR_R 0_0402_5% L/R
470P_0201_50V7-K PLUG_IN 5
PLUG_IN 6 5
6
RA48 1 @ 2 @ 1 2 CA42 HP_OUTR_R 2
AZ5123-01F.R7GR_DFN1006P2X2

AZ5725-01F.R7GR_DFN1006P2X2

AZ5725-01F.R7GR_DFN1006P2X2

AZ5725-01F.R7GR_DFN1006P2X2

AZ5725-01F.R7GR_DFN1006P2X2
0_0402_5% R/L
470P_0201_50V7-K
1

1
DA5 DA6 DA7 DA8 DA9 RING3_CONN 4
DMIC_CLK HDA_RST_AUDIO# M/G
1
1

1
CA43 7

100P_0201_25V8J

100P_0201_25V8J
HDA_SYNC_AUDIO 1000P_0402_50V7K MS
1 1
DMIC_DATA EMC@ SINGA_2SJ3095-091111F
HDA_SDOUT_AUDIO 2
EMC_NS@

EMC_NS@

ME@
2

HDA_BITCLK_AUDIO 2 2

CA45

CA44
RA27 1 EMC@ 2
100P_0201_25V8J

100P_0201_25V8J

1 1 27_0402_5%
A
HDA_SDIN0 A
EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@ EMC_NS@ EMC_NS@ EMC_NS@ EMC_NS@

2 2
EMC@

EMC@
CA37

CA38

22P_0201_25V8

22P_0201_25V8
68P_0402_50V8J

FOR ESD Close to Connector

33P_0201_50V8-J

33P_0201_50V8-J

1 1 1 1 1

2 2 2 2 2
CA22

CA23

CA24

CA25

CA26

For EMI
Security Classification LC Future Center Secret Data Title
For EMI Issued Date 2015/08/20 Deciphered Date 2016/08/20 Codec_CX11802 & Audio jack
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG411
Date: Thursday, January 14, 2016 Sheet 43 of 60
5 4 3 2 1
 5 4 3 2 1

For EMI RE1 1 @ 2 0_0603_5%

For ESD +3VL V20B+
PLT_RST# CLK_PCI_EC RE2 1 2 10_0402_5%
EMC@

1
RE3 1 @ 2 0_0603_5%
1
CE1 CE2
1 Close  EC +3VALW
RE261
220P_0201_25V7-K 10P_0201_50V8F 470K_0402_5%
+3VL_EC +3VL_EC +3VL_EC_R
EMC@ EMC@ @
2 2 CE3 1 2 VCOREVCC

2
LE1 1 @ 2 0_0603_5% B+_Track
0.1u_0201_10V6K +3VL_EC All capacitors close to EC

1
CD@

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K
1 1
1 1 1 @1 1 @1 CE4 CE5 +3VL_EC R260
0.1u_0201_10V6K 1000P_0201_50V7-K 47K_0402_5%
+3VS +3VL_EC_R @
2 2

2
1
D 2 2 2 2 2 2 EC_AGND D

CE10

CE11
Change RE6 to 0ohm jump LE2 1 @ 2 0_0603_5%

CE6

CE7

CE8

CE9
RE5
RE6 1 @ 2 0_0402_5% 10K_0402_5%
EC_AGND

2
LAN_WAKE#
minimum trace width 12 mil LAN_WAKE# 37,40

114
121
127
12

11

26
50
92

74
3
UE1
+3VS

VCORE

VSTBY1
VSTBY2
VSTBY3
VSTBY4
VSTBY5
VSTBY(PLL)
VBAT

VCC

AVCC
EC_FAN_SPEED RE10 1 2 10K_0402_5%

EC_FAN_PWM RE11 1 @ 2 10K_0402_5%

20 WRST#
RE56 2 @ 1 0_0402_5% 4 24 PWR_LED#
7 KBRST# KBRST#/GPB6 PWM0/GPA0 PWR_LED# 45 LPC_FRAME#
RE59 2 @ 1 0_0402_5% 5 25 RE7 1 @ 2 10K_0402_5%
+3VL_EC 7,32 SERIRQ LPC_FRAME#_EC6 SERIRQ/GPM6 PWM1/GPA1 BATT_CHG_LED# 45
RE60 1 @ 2 0_0402_5% 28
7,32 LPC_FRAME# LPC_AD3_EC LFRAME#/GPM5 PWM2/GPA2 EC_VCCST_PWRGD BATT_LOW_LED# 45
RE61 1 @ 2 0_0402_5% 7 29 ENBKL RE9 1 @ 2 100K_0402_5%
7,32 LPC_AD3 LPC_AD2_EC LAD3/GPM3 PWM3/GPA3 EC_VCCST_PWRGD 11
DE1 1 2 @ RE62 1 @ 2 0_0402_5% 8 PWM 30
7,32 LPC_AD2 LPC_AD1_EC LAD2/GPM2 PWM4/GPA4 EC_FAN_PWM SYS_PWROK 11 CPU_VR_READY
RE63 1 @ 2 0_0402_5% 9 31 RE270 1 2 10K_0402_5%
7,32 LPC_AD1 LPC_AD0_EC LAD1/GPM1 PWM5/GPA5 EC_FAN_PWM 39
RB751V-40_SOD323-2 RE64 1 @ 2 0_0402_5% 10 32
7,32 LPC_AD0 CLK_PCI_EC LAD0/GPM0 PWM6/SSCK/GPA6 EC_VCCST_EN_R BEEP# 43 EC_VCCST_EN EC_CMOS_ON#
13 LPC 34 RE54 1 @ 2 RE275 1 @ 2 10K_0402_5%
7 CLK_PCI_EC LPCCLK/GPM4 PWM7/RIG1#/GPA7 LAN_WAKE# EC_VCCST_EN 13
1 2 WRST# 14 120 0_0402_5%
RE8 15 WRST# TMRI0/GPC4 124 SUSP#
1 9 EC_SMI# ECSMI#/GPD4 TMRI1/GPC6 SUSP# 46
100K_0402_5% EC_RX 16
CE12 40 EC_RX EC_TX PWUREQ#/BBO/SMCLK2ALT/GPC7 +5VS +3VS
17 66 NTC_V1 39
1U_0402_6.3V6K 40 EC_TX PLT_RST# LPCPD#/GPE6 ADC0/GPI0
22 67 NTC_V2 39
2 11,20,32,37,40 PLT_RST# LPCRST#/GPD2 ADC1/GPI1 BATT_TEMP
23 68
4 EC_SCI# ECSCI#/GPD3 ADC2/GPI2 BATT_TEMP 52,53

2
EC_RTCRST#_ON 126 ADC 69
GA20/GPB5 ADC3/GPI3 PM_SLP_SUS# 11
70 RE52 RE51
IT8586E/AX ADC4/GPI4
ADC5/DCD1#/GPI5
71
72 B+_Track
CPU_VR_READY 59
ADP_I 53
+3VL_EC
0_0402_5%
@
0_0402_5%
ADC6/DSR1#/GPI6
LQFP-128L 73 1 TE1 @

1
KSI[0..7] KSI0 58 ADC7/CTS1#/GPI7
45 KSI[0..7] KSI0/STB#

1
KSI1 59 78 SUSWARN# 11
KSO[0..17] KSI2 60 KSI1/AFD# DAC2/TACH0B/GPJ2 79 RE65 TP_CLK RE12 2 1 4.7K_0402_5%
45 KSO[0..17] KSI2/INIT# DAC3/TACH1B/GPJ3 H_PROCHOT#_EC SUSACK# 11
C KSI3 61 DAC 80 100K_0402_5% C
KSI4 62 KSI3/SLIN# DAC4/DCD0#/GPJ4 81 TP_DATA RE13 2 1 4.7K_0402_5%
KSI4 DAC5/RIG0#/GPJ5 ENBKL 33
KSI5 63

2
+3VL_EC KSI6 64 KSI5 85 EC_ON_GPIO 0_0402_5% 1 @ 2 RE57
KSI6 PS2CLK0/TMB0/CEC/GPF0 EC_ON 39,54,55
KSI7 65 86 +5VALW
KSI7 PS2DAT0/TMB1/GPF1 EC_SMB_CK3 PBTN_OUT# 11
KSO0 36 87
EC_SMB_CK1 KSO0/PD0 GPF2 EC_SMB_DA3 EC_SMB_CK3 55
RPE2 PAD 1 @ KSO1 37 Int. K/B PS2 88
EC_SMB_DA1 EC_SMB_DA1 IT1 KSO1/PD1 GPF3 TP_CLK EC_SMB_DA3 55 USB_ON#
2 3 PAD 1 @ KSO2 38 Matrix 89 RE15 1 2 100K_0402_5%
EC_SMB_CK1 IT2 KSO2/PD2 PS2CLK2/GPF4 TP_DATA TP_CLK 45 +3VALW +3VL_EC
1 4 PAD 1 @ KSO3 39 90 For PMIC
IT3 KSO3/PD3 PS2DAT2/GPF5 TP_DATA 45
PAD 1 @ KSO4 40
IT4 KSO4/PD4
2.2K_0404_4P2R_5% PAD 1 @ KSO5 41 EXTERNAL SERIAL FLASH 96 +3VL_EC
IT5 KSO5/PD5 GPH3/ID3 CAPS_LED# 45

1
KSO6 42 97
KSO6/PD6 GPH4/ID4 PCH_PWR_EN 46,55
KSO7 43 98 RE273 RE274
KSO7/PD7 GPH5/ID5 EC_BKL_EN 45
KSO8 44 99 0_0402_5% 0_0402_5%
+3VS KSO8/ACK# GPH6/ID6 PCH_PWROK 11
KSI7 PAD 1 @ KSO9 45 @ SUSP# RE18 1 @ 2 100K_0402_5%
IT6 KSO9/BUSY EC_SPI_CS0#
KSI6 PAD 1 @ KSO10 46 101
IT7

2
RPE3 WRST# PAD 1 @ KSO11 51 KSO10/PE NC1 102 EC_SPI_SI SUSP# RE19 1 2 100K_0402_5%
EC_SMB_CK2 IT8 KSO11/ERR# NC2 EC_SPI_SO
1 4 KSO12 52 SPI Flash ROM 103 RPE4
2 3 EC_SMB_DA2 KSO13 53 KSO12/SLCT NC3 105 EC_SPI_CLK EC_SMB_DA3 1 4 SYSON_R RE21 1 2 100K_0402_5%
KSO14 54 KSO13 NC4 EC_SMB_CK3 2 3
For factory EC flash KSO14
2.2K_0404_4P2R_5% KSO15 55 EC_VCCST_EN RE269 1 @ 2 100K_0402_5%
KSO16 56 KSO15 108 ACIN# 2.2K_0404_4P2R_5%
KSO17 57 KSO16/SMOSI/GPC3 AC_IN# 109 LID_SW# EC_VCCIO_EN RE268 1 @ 2 100K_0402_5%
KSO17/SMISO/GPC5 UART LID_SW# LID_SW# 45

ON/OFF 110 82 EC_FAN_ANTI_R RE53 1 @ 2 0_0402_5% EC_FAN_ANTI 39

45 ON/OFF PWRSW# EGAD/GPE1
EC_ON RE58 2 @ 1 0_0402_5% 111 SM Bus 83 VDDQ_PGOOD 55
EC_SMB_CK1 115 XLP_OUT EGCS#/GPE2 84 EC_VPP_PWREN Add to fix Reset&PWRGD test fail issue
52,53 EC_SMB_CK1 EC_SMB_DA1 SMCLK1/GPC1 EGCLK/GPE3 EC_VPP_PWREN 55
116
52,53 EC_SMB_DA1 PECI_EC SMDAT1/GPC2 VDDQ_PGOOD CE51 1
4 H_PECI RE24 1 2 43_0402_5% 117 GPIO 77 2 0.01U_0201_10V6K
SMCLK2/PECI/GPF6 GPJ1 EC_CMOS_ON# 33
118 100 GPG2
37 LAN_PWR_ON# EC_SMB_CK2 SMDAT2/PECIRQT#/GPF7 SSCE0#/GPG2
94 106
7,20,39 EC_SMB_CK2 EC_SMB_DA2 CRX1/SIN1/SMCLK3/GPH1/ID1 SSCE1#/GPG0 EC_MUTE# 43 PM_SLP_S4#
95 104 CE50 1 2 EMC_NS@ 1000P_0201_50V7-K
+3VL 7,20,39 EC_SMB_DA2 CTX1/SOUT1/GPH2/SMDAT3/ID2 DSR0#/GPG6 SYSON_R ME_FLASH 8
107 RE271 1 @ 2 0_0402_5% SYSON
DTR1#/SBUSY/GPG1/ID7 SYSON 55
119 BKOFF#
CRX0/GPC0 BKOFF# 33 EC_VCCIO_EN PM_SLP_S3#
123 RE55 2 @ 1 0_0402_5% CE21 1 2 EMC_NS@ 1000P_0201_50V7-K
CTX0/TMA0/GPB2 EC_VCCIO_EN 13
RE27 1 @ 2 0_0402_5% 112 18
VSTBY0 RI1#/GPD0 PM_SLP_S3# 11,13
RE272 1 @ 2 0_0402_5% 125 21 PM_SLP_S4# 11
B 59 EC_VR_ON GPE4 RI2#/GPD1 B
WAKE UP 76 NOVO# 45 SYSON CE13 1 2 EMC_NS@ 1000P_0201_50V7-K
PM_SLP_S3# DE2 1 2 TACH2/GPJ0 48
TACH1A/TMA1/GPD7 EC_FAN_SPEED EC_TS_ON 33
@ RB751V-40_SOD323-2 47 EC_FAN_SPEED 39
USB_ON# 33 TACH0A/GPD6 19 VGA_AC_DET
41,45 USB_ON# GINT/CTS0#/GPD5 L80HLAT/BAO/GPE0 VGA_AC_DET 20 EMC Request

2
35 GPIO 20
11 DPWROK_EC RTS1#/GPE5 L80LLAT/GPE7 NUM_LED# 45
93
11 EC_RSMRST# CLKRUN#/GPH0/ID0 Reserve for VGA_AC_DET 
PCIE_WAKE# 2 DE3
11,37,40 PCIE_WAKE#

1
128 CK32KE/GPJ7 RB751V-40_SOD323-2
+3VL 11 AC_PRESENT CK32K/GPJ6 Clock
@
PM_SLP_S4#

RE34 1 @ 2 H_PROCHOT# 4,55

53,59 VR_HOT#
AVSS

RE35 1 @ 2 10K_0402_5% ON/OFF 0_0402_5%

VSS1

VSS2
VSS3
VSS4
VSS5
VSS6

EC_RTC_RST# 10

1
RE36 1 @ 2 10K_0402_5% BKOFF# 1
IT8586E-AX_LQFP128_14X14 RE267 CE14
1

27
49
91
113
122

75

RE38 2 1 100K_0402_5% LID_SW# 100_0402_5% 47P_0201_25V8-J

EMC_NS@

1
2 QE3 D

1 2
EC_RTCRST#_ON 2
RE40 1 2 10K_0402_5% BKOFF# QE1 D G
EC_AGND H_PROCHOT#_EC 2 +3VL
G @ S 2N7002KW_SOT323-3

3
1
2N7002KW_SOT323-3 S RE50
for EC version update to EX,  manual modify PN to FX

2
100K_0402_5%
RE42 @
100K_0402_5%

2
1
+3VL +3VS ACIN# RE262 1 @ 2 0_0402_5%
PECI_EC 11 ACIN#
EMC_NS@ CE15 1 2 47P_0201_25V8-J
+3VL_EC

1
BATT_TEMP EMC_NS@ CE16 1 2 100P_0201_25V8J 1
D QE2
A GPG2 RE43 2 @ 1 10K_0402_5% CE19 2 A
G ACIN 53
ACIN# EMC_NS@ CE17 1 2 100P_0201_25V8J 0.1u_0201_10V6K
GPG2 RE44 2 1 10K_0402_5% EC_SPI_CS0# RE45 2 @ 1 0_0402_5% SPI_CS0#
SPI_CS0# 7 NOVO# ON/OFF @ CE18 1 2 1U_0402_6.3V6K 2 S 2N7002KW_SOT323-3

3
GPG2 RE46 2 @ 1 10K_0402_5% @
EC_SPI_SI RE47 2 @ 1 0_0402_5% SPI_SI
SPI_SI 7
when mirror, GPG2  pull high
when no mirror, GPG2 pull  low EC_SPI_SO RE48 2 @ 1 0_0402_5% SPI_SO
SPI_SO 7 1
CE48
0.01U_0201_10V6K Title
EC_SPI_CLK RE49 2 @ 1 0_0402_5% SPI_CLK EMC_NS@ Security Classification LC Future Center Secret Data
SPI_CLK 7 2
Issued Date 2015/08/20 Deciphered Date 2016/08/20 EC ITE8586LQFP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG411
WWW.AliSaler.Com 5 4 3 2
Date: Thursday, January 14, 2016
1
Sheet 44 of 60
 5 4 3 2 1

ON/OFF switch Novo button

+3VL +3VALW NOVO_BTN#

ON/OFFBTN#

2
AZ5123-01F.R7GR_DFN1006P2X2

1
R82 R83

3
100K_0402_5% 100K_0402_5% SW2 D24

1
1
@ D25 AZ5123-01F.R7GR_DFN1006P2X2
R261 1 @ 2 EVQP7L01K SPST EMC@

1
1

1
0_0402_5% SW1
SKRBAAE010_4P

2
14@

2
2
NOVO# D15 2
44 NOVO#

4
EMC_14@

2
1 NOVO_BTN#

ON/OFF R85 1 @ 2 0_0402_5% 3 @

D D
BAT54CW_SOT323-3

+3VALW +3VL
LID switch
ON/OFFBTN#

AZ5123-01F.R7GR_DFN1006P2X2
2

3
R111 R114

1
100K_0402_5% 100K_0402_5% D26
@ 1

1
SW3 C1104
1

1
SKRBAAE010_4P U14 100P_0201_25V8J
ON/OFFBTN# R119 1 @ 2 0_0402_5% ON/OFF 15@ 1
ON/OFF 44 GND 2
1

2
C1105 3 LID_SW#
LID_SW# 44

4
J5 1 2 @ EMC_15@ 0.01U_0201_10V6K OUTPUT

2
SHORT PADS R264 1 @ 2 2 +VCC_LID 2
+3VL VCC
0_0402_5%
J6 1 2 @ AH9247-W-7_SC59-3

SHORT PADS

K/B Connector KSI[0..7]

KSI[0..7] 44
JKB1
KB Backlight Connector
KSO[0..17]
KSO[0..17] 44 KB_P32 32 33
32 GND1 +5VS
KB_P31 31 34
R279 1 15@ 2 0_0402_5% NUM_LED#_R 30 31 GND2
44 NUM_LED# 30 +5VALW
R90 1 15@ 2 300_0402_5% PWR_NUM_LED 29 +VCC_KB_LED
EMC_NS@ +3VS
KSO17_R 29
PWR_CAPS_LED C133 1 2 100P_0201_25V8J KSO17 R281 1 15@ 2 0_0402_5% 28 Q31
KSO16 R280 1 15@ 2 0_0402_5% KSO16_R 27 28

1
27 R265 LP2301ALT1G_SOT23-3
PWR_NUM_LED C134 1 2 100P_0201_25V8J KSI1 26 10K_0402_5% KBL@
KSI7 25 26

D
25 KBL@ 3 1
EMC_NS@ KSI6 24
KSO9 23 24
23 1 1

2
KSI4 22 R266 C1106 C1107

G
22

2
KSI5 21 1 2 10U_0603_6.3V6M 0.1u_0201_10V6K
KSO0 20 21
KSO12 R291 1 14@ 2 0_0402_5% KB_P32 20 KBL@ KBL@
EMC@ KSI2 19 100K_0402_5% 2 2
KSI3 18 19 1
CAPS_LED# C117 1 2 100P_0201_25V8J KSO14 R292 1 15@ 2 0_0402_5% 18 KBL@ C1108
KSO5 17 0.01U_0201_10V6K
KSO1 16 17
C NUM_LED#_R C118 1 2 100P_0201_25V8J 16 KBL@ C
KSI0 15 2
KSO2 14 15
EMC_15@ 14
KSI2 R289 1 14@ 2 0_0402_5% KB_P31 KSO4 13
KSO7 12 13
KSO8 11 12

1
KSI5 R290 1 15@ 2 0_0402_5% 11 D
KSO6 10 EC_BKL_EN 2 Q32
KSO3 9 10 44 EC_BKL_EN
CAPS_LED# NUM_LED#_R 9 G 2N7002KW_SOT323-3
KSO12 8 KBL@
KSO13 7 8
7 S
1

3
KSO14 6 C1109
KSO11 5 6
5 0.1u_0201_10V6K
KSO10 4
1

4 KBL@
D22 D23 KSO15 3 2 JKBL1
3
1

CAPS_LED# 2 +VCC_KB_LED
AZ5123-01F.R7GR_DFN1006P2X2 AZ5123-01F.R7GR_DFN1006P2X2 44 CAPS_LED# 2 1
R84 1 2 PWR_CAPS_LED 1 1
EMC@ EMC_15@ +3VS 1 2
300_0402_5% 3 2
CVILU_CF32321D0RONH 4 3
4
2

ME@ 1
C1110 5
2

0.1u_0201_10V6K 6 GND1
@ GND2
2 HIGHS_FC1AF040-1201H
For EMC
ME@

+USB_VCCB JUSB3
USB DB Connector TP/B Connector
12
11 12 14
10 11 GND2 +5VS TP_PWR
Right Side USB2.0 Port X 2 (USB/B) R67 1 @ 2 0_0402_5% USB20_P2_CONN
9
8
10
9 GND1
13
R160 1 @ 2
9 USB20_P2 8 +3VS
R66 1 @ 2 0_0402_5% USB20_N2_CONN 7 0_0402_5%
+5VALW +USB_VCCB 9 USB20_N2 7
6 JTP1
U3 R254 1 @ 2 0_0402_5% USB20_P3_CONN 5 6 R141 1 2 1
9 USB20_P3 5 1
5 1 R255 1 @ 2 0_0402_5% USB20_N3_CONN 4 0_0402_5% TP_CLK 2
IN OUT 9 USB20_N3 4 44 TP_CLK TP_DATA 2
3 3

0.1u_0201_10V6K
1 3 44 TP_DATA 3
C141 2 PWR_LED# 2 4

100P_0201_25V8J

100P_0201_25V8J
GND 44 PWR_LED# 2 1 4
1U_0402_6.3V6K 1

EMC_NS@

EMC_NS@
+5VALW 1 1 1
4 3 USB_OC2# 5
2 41,44 USB_ON# ENB OCB USB_OC2# 9 GND1
ACES_50506-01201-AT1 6
TP_CLK 2 GND2

C114
SY6288D20AAC_SOT23-5 1 ME@
TP_DATA 2 2

C115

C116
C142 HIGHS_FC1AF040-1201H
1000P_0201_50V7-K ME@
Low Active 2A

2
EMC_NS@
B 2 B
DT1

EMC_NS@

L14 EMC_NS@ JUSB4

USB20_P2 1 2 USB20_P2_CONN 22
1 2 21 GND2
R284 1 510Z@ 2 0_0402_5% USB30_RX_R_P2 20 GND1
USB20_N2 USB20_N2_CONN 9 USB30_RX_P2 20
4 3 R283 1 510Z@ 2 0_0402_5% USB30_RX_R_N2 19
4 3 9 USB30_RX_N2 19
18 AZC199-02S.R7G_SOT23-3

1
EXC24CH900U_4P R285 1 510Z@ 2 0_0402_5% USB30_TX_R_P2 17 18
9 USB30_TX_P2 17 For EMC
R286 1 510Z@ 2 0_0402_5% USB30_TX_R_N2 16
9 USB30_TX_N2 16
+3VS_DB 15
L17 EMC_NS@ 14 15
+USB_VCCB 14
USB20_P3 1 2 USB20_P3_CONN 13
1 2 12 13
11 12
USB20_N3 4 3 USB20_N3_CONN 10 11
4 3 9 10
EXC24CH900U_4P USB20_P2_CONN 8 9
USB20_N2_CONN 7 8
6 7
L20 EMC_NS@ USB20_P3_CONN 5 6
USB30_RX_P2 1 2 USB30_RX_R_P2 USB20_N3_CONN 4 5
1 2 3 4
PWR_LED# 2 3
USB30_RX_N2 4 3 USB30_RX_R_N2 1 2
4 3 +5VALW 1
EXC24CH900U_4P HIGHS_FC5AF201-1151H
ME@

L21 EMC_NS@
USB30_TX_N2 1 2 USB30_TX_R_N2 +3VS +3VS_DB
1 2
R295 1 510Z@ 2 0_0402_5%
USB30_TX_P2 4 3 USB30_TX_R_P2
4 3
EXC24CH900U_4P

BATT_LOW_LED# LED2 1 2 R143 1 2 470_0402_5%

44 BATT_LOW_LED# +3VALW
L-C192JFCT-LCFC_SUPER_AMBER
1

D18
1

A AZ5123-01F.R7GR_DFN1006P2X2 A
EMC_NS@
2
2

BATT_CHG_LED# LED3 1 2 R144 1 2 1.5K_0402_5%

44 BATT_CHG_LED# +5VALW
L-C192WDT-LCFC_WHITE
1

D19
1

AZ5725-01F.R7GR_DFN1006P2X2
EMC_NS@ Title
Security Classification LC Future Center Secret Data
Issued Date 2015/08/20 Deciphered Date 2016/08/20 KBD/PWR/IO/LED/TP Conn.
2
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG411
Date: Thursday, January 14, 2016 Sheet 45 of 60
5 4 3 2 1
 A B C D E

Load Switch
+5VALW To +5VS +3VS, C173 ‐‐> 2.74ms
+3VALW To +3VS +5VS, C176 ‐‐> 2.03ms
R64 1 @ 2 0_0402_5% 3VSON
VIN 5V and 3.3V (VBIAS=5V), IMAX(per channel)=6A, Rds=16mohm Need Short
+5VALW U13 +5VS
1 14 J12 @
2 IN1_1 OUT1_2 13 +5VS_LS 1 2
1 IN1_2 OUT1_1 1 2 1

1 5VSON 3 12 C176 1 2 1000P_0201_50V7-K JUMP_43X118 1

SUSP# R27 1 @ 2 0_0402_5% 5VSON EN1 CT1 C174
C177 4 11 0.1u_0201_10V6K
+5VALW VBIAS GND
1U_0402_6.3V6K @
+3VALW 2 3VSON 5 10 C173 1 2 2200P_0402_25V7-K 2 +3VS
1 1 EN2 CT2 J11 @
C180 C179 6 9 +3VS_LS 1 2
1U_0402_6.3V6K 1U_0402_6.3V6K 7 IN2_1 OUT2_2 8 1 2
2 2 IN2_2 OUT2_1 JUMP_43X118
1 1
15 C175
C178 GPAD 0.1u_0201_10V6K
1U_0402_6.3V6K
Need Short
G5016KD1U_TDFN14_2X3 @
2 @ 2
Change the main source to SA000067600 (GMT) 7/16

2 2
+3VALW Need  short +3VALW_PCH
+5VALW
J7 @
1 2
1 2
1

JUMP_43X79
R155 1
100K_0402_5% C1103
@ 22U_0603_6.3V6-M LP2301ALT1G_SOT23-3 Id=3.2A
2

@
PCH_PWR_EN#_R 2 100K_0402_5% PCH_PWR_EN# 2

D
R158 1 @ Q29 3 1 @

1
1

Q30 D C130

G
2
PCH_PWR_EN 2 0.01U_0201_10V6K
44,55 PCH_PWR_EN
G @
2
@ S 2N7002KW_SOT323-3
3
1

PCH_PWR_EN#_R

R162 1
100K_0402_5% C131
@ 0.1u_0201_10V6K
2

@
1

2
R87
100K_0402_5%
@
2

3 3

+5VLP +5VALW
For DisCharge
1

R156 R157 +0.6VS +2.5V_DDR

100K_0402_5% 100K_0402_5%
@
1

1
2

R159 R278
SUSP 47_0603_5% 200_0402_5%
34 SUSP
@ @
2

2
1

1
Q10 D D Q11 D Q33
2 2 SUSP 2 SUSP
44 SUSP# G G G

S 2N7002KW_SOT323-3 S 2N7002KW_SOT323-3 S 2N7002KW_SOT323-3

3

3
@ @

4 4
08/29: Need double check enable signal and the resistance

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 DC V TO VS INTERFACE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG411
WWW.AliSaler.Com A B C D
Date: Thursday, January 14, 2016
E
Sheet 46 of 60
 5 4 3 2 1

B2 A2
D
+3VLP PCH_PWR_EN# 2 D

Q25,+3V_PCH

V
V
AC A1
MODE VIN

V V
A2 A4 B5
3 +3V_PCH

V
PU301 PU904

V
B+
+3VALW
BATT BATT V 1
DPWROK_EC
V
MODE

V V V
B1
4
PCH_RSMRST#
EC 14
PM_DRAM_PWRGD
5 PBTN_OUT#

V
EC_ON PM_SLP_S3# PCH 15
PM_SLP_S4# H_CPUPWRGD CPU

V V
A3 B4 PM_SLP_S5#
PM_SLP_SUS# 6

V
CPU_PLTRST# 16
12
PCH_PWROK

V V
C C

B3 13
SYS_PWROK

V
ON/OFF V
NOVO

NVDD_PWR_EN
(DIS)
Vb
+VGA_CORE

V
11 VR_REDY SYSON 7 +1.35V
PU801

V
PU501
DGPU_PWROK
DGPU_PWR_EN
10
Va (DIS)

V
PU901 VR_ON +1.5VS_VGA

V
Q31
V

PU601

V
+CPU_CORE
+5VS

B B

V
Q32 +1.05VSP_VGA

V
SUSP#,SUSP 9 +3VS PU702

V
VGA

V
PU602
+1.5VS +3VS_VGA

V
Q27

V
PU502
+0.675V
8
SUS_VCCP PU701
V
+1.05VS

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 Power sequence block
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG411
Date: Thursday, January 14, 2016 Sheet 47 of 60
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 Virtual symbol
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG411
WWW.AliSaler.Com
5 4 3 2
Date: Thursday, January 14, 2016
1
Sheet 48 of 60
 5 4 3 2 1

PCB Fedical Mark PAD

FD1 FD2 FD3 FD4 FD5 FD6
NH1 NH2 NH3
HOLEA HOLEA HOLEA

1
D D
1

1
PAD_O2P6X2P5D2P6X2P5N PAD_O2P5X3P0D2P5X3P0N PAD_O2P5X2P9D2P5X2P9N

H1 H3 H4 H5 H6 H7 H10
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
1

1
CHASSIS1_GND
PAD_D3P4 PAD_CT7P0B9P0D3P0 PAD_C7P0D3P3 PAD_C8P0 PAD_C5P0 PAD_C7P0D3P0 PAD_C7P0D3P3

H11 H12 H13 H14 H15 H16 H17 H18 H19 H20
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
C C
1

1
PAD_CT7P0B9P0D3P0 pad_ct6p0b7p0d4p0 pad_ct6p0b7p0d4p0 pad_ct6p0b7p0d4p0 pad_ct6p0b7p0d4p0 PAD_ShapeT9P0X8P0CB9P0D3P0 PAD_ShapeT7P5X8P0D3P4 PAD_CT7P0B6P0D3P3 PAD_C3P0D3P0N PAD_C6P0D2P5

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 Hole
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG411
Date: Thursday, January 14, 2016 Sheet 49 of 60
5 4 3 2 1
 5 4 3 2 1

D D

PCH_PWR_EN EN
Silergy
+5VLP/ 100mA LV5075AGQV
V20B+
Silergy VQFN40_5X5 +1.0VALW/6A
SY8288CRAC Converter
QFN20_3X3 +5VALW/6A FOR PCH PGOOD NA

Adaptor 45W/65W Converter

EC_ON EN FOR SYSTEM PGOOD NA

ANPEC GMT
+3VLP/ 100mA LV5075AGQV G971LADJF11U
Silergy +1.8VALW/1A +1.05VGS/1.5A
SY8286BRAC VQFN40_5X5 SO8
Converter LDO
QFN20_3X3 +3VALW/ 5A PCH_PWR_EN EN
For GPU EN_VGA EN FOR GPU
PGOOD NA PGOOD NA
Converter
C EC_ON EN FOR SYSTEM PGOOD ALW_PWRGD C

Richtek
LV5075AGQV +2.5V/1A
Richtek +1.2V/7A VQFN40_5X5
LV5075AGQV LDO
EC_VPP_PWREN EN PGOOD NA
SYSON S5 VQFN40_5X5 For DDR4
TI CPU_DRAMPG_CNTL S3 Switch Mode +0.6VS/2A
FOR DDR4
BQ24780SRUYR PGOOD VDDQ_PGOOD

Battery Charger
Switch Mode
Richtek +1.35V/8A
NB685GQ-Z
QFN16_3X3
FBVDDQ_PWR_EN EN Switch Mode
SMBus FOR VRAM
B
PGOOD NA B

Intersil
RT8812AGQW
Battery WQFN20_3X3 +VGA_CORE/31A
VID
polymer Switch Mode
PXS_PWREN EN FOR GPU VDDC PGOOD DGPU_PWROK
2S1P

CPU Core/23A
Onsemi
NCP81206MNR2G VCCGT/25A
QFN60_7X7
VID Switch Mode VCCSA/7A
EC_VR_ON EN FOR CPU Core
PGOOD CPU_VR_READY

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 PWR-Power Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG411
Date: Thursday, January 14, 2016 Sheet 50 of 60
5 4 3 2 1

WWW.AliSaler.Com
 5 4 3 2 1

VIN
7A_24VDC_429007.WRML EMC@
HCB2012KF-121T50_0805
JDCIN1 PF101 PL101
1 ADPIN 1 2 APDIN_F 1 2
1 2
GND1 3 EMC@
GND2

1000P_0201_50V7-K
4 HCB2012KF-121T50_0805
GND3

PC104 EMC@
470P_0201_50V7-K

470P_0201_50V7-K
1000P_0201_50V7-K
5 PL102
GND4

EMC@ PC101

PC102

EMC@ PC103
6 1 2
GND5

2
D 7 D
GND6
EMC@

1
HIGHS_PJSS0026-8B01H
ME@

+3VL

1
PR1015
1.5K_0402_1%

2
C VCCRTC C

1
PR1016
45.3K_0402_1%
PD101
RTC_VCC

2
2

1 RTC_VCC 20MIL
JRTC1 +3VL 20MIL
3 2 PR101 1 1
2 1 VCCRTC 20MIL
1K_0603_5% 3 2
G1 No charge RTC
2

@ BAT54CW_SOT323-3 4
PC105 G2
1U_0402_6.3V6K ACES_50273-0020N-001
1

ME@

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 PWR-DCIN / RTC charger
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG411
Date: Thursday, January 14, 2016 Sheet 51 of 60
5 4 3 2 1
 5 4 3 2 1

VBAT_F
SUYIN_125022HB008M202ZL VBAT
PF201 EMC@
D JBATT1 D
12A_24V_F1206HB12V024T/M HCB2012KF-121T50_0805
1 PL201
1
2
2
EC_SMCA
1 2 1 2 BATT+ 2S1P BAT +6V
9
10 GND1 3
3
4 EC_SMDA
PR202 1
1
2100_0402_1%
2
EC_SMB_CK1 44,53
1 2
~ 8.4 V
GND2 4 EC_SMB_DA1 44,53
5 PR201 100_0402_1%
5 6 PL202
6 7 HCB2012KF-121T50_0805
7

2
8 EMC@
8

1
ME@ PC201 PC202
1000P_0201_50V7-K 0.01U_0201_25V6-K

2
EMC@ EMC@
Reverse PD201 PD202
For EMI request
PD201

EMC_NS@

AZC199-02S.R7G_SOT23-3

1 PR209
1 2 +3VALW
100K_0402_1%

PR213
C BATT_TEMP_IN 1 2 C
10K_0402_5%
BATT_TEMP 44,53 A/D
1

PD202
1

EMC_NS@
AZ5215-01F_DFN1006P2E2
2
2

VBAT
SUYIN_125022HB008M202ZL
JBATT2
1
1 2
9 2 3 EC_SMCA
B 10 GND1 3 4 EC_SMDA B
GND2 4 5 BATT_TEMP_IN
5 6
6 7
7 8
8
ME@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 PWR-BATTERY CONN/OTP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG411
WWW.AliSaler.Com 5 4 3 2
Date: Thursday, January 14, 2016
1
Sheet 52 of 60
 5 4 3 2 1

AON6414AL_DFN8-5
PQ311 PQ312
AON7408L_DFN8-5 N2
VIN N1 @ PR301
1 1 PJ301 0.01_1206_1%
2 2 JUMP_43X118
5 3 3 5 1 2 1 4
1 2 V20B+

0.1U_0201_25V6-K

1000P_0201_50V7-K
2 3
D D

10U_0603_25V6-M

10U_0603_25V6-M
470P_0201_50V7-K

0.022U_0402_25V7K
4

2
PC301

PC312

PC331
1

2
EMC_NS@

EMC_NS@
PC303

PC304
1000P_0201_50V7-K

1000P_0201_50V7-K

1000P_0201_50V7-K

1000P_0201_50V7-K
1

1
PC329

PC330

EMC_NS@ PC317

PC332

PC302

1
PR302

1
4.7_0603_5% EMC_NS@
2

5
EMC_NS@

EMC_NS@

EMC_NS@ 0.1U_0201_25V6-K

2
EMC_NS@ PQ314
PC305
AON6414AL_DFN8-5
1 2

BQ24780_BATDRV 4

2
PC306
PC307 0.1U_0201_25V6-K

1
1U_0603_25V6K

3
2
1
2
PR303
499K_0402_1% PC308
0.01U_0201_25V6-K

1
VIN BATT+

2
432K and 64.9k change

BAT54CW_SOT323-3
to 43k and 6.49k.0.1u

PD302
change to 0.01u

3
decrease ACDET V20B+
deassert time

2200P_0201_25V7-K

10U_0805_25V6K

10U_0805_25V6K
VIN

1
1

2
PC310

PC313
4.02K_0603_1%

4.02K_0603_1%

ACN
ACP
PR310

PR311

PC314
1

1
2
EMC@

5
PR314 BQ24780_VDD
2

1
C PR313 10_1206_5% C
6.49K_0402_1% 1U_0603_25V6K

ACP

ACN
1 2 43K_0402_1% PC315

1
PR315 2 1 780_VCC 28 24 1 2 PQ316

2
VCC REGN 2.2U_0603_10V6-K PC316 4
2 1 ACDET 6 AON7408L_DFN8-5
PC309 ACDET PR316 PC318
25 BST_CHG
1 2 2 1
0.01U_0201_25V6-K BTST 2.2_0603_5% PR317

3
2
1
BQ24780SRUYR_QFN24_4X4 0.047U_0603_16V7K 4.7UH_PCMB063T-4R7MS_5.5A_20% 0.01_1206_1%
3 26 DH_CHG PL302
0.5C charge
CMSRC HIDRV 1 2 CHG 1 4 BATT+
@ 2 PR339 1 20K_0402_1% 4
ACDRV 2 3

1
100K_0402_1% 2 PR324 1 @ 27 LX_CHG
BQ24780_VDD PHASE

10U_0805_25V6K

10U_0805_25V6K
PR321

2
ACIN_R 4.7_0603_5%

PC319
0_0402_5%1 2 PR325 @ 5
44 ACIN ACOK

PC320
EMC@
0_0402_5%1 2 PR320 @ EC_SMB_DA1_R 11

1
44,52 EC_SMB_DA1 SDA PU301 23 DL_CHG PQ317 4
LODRV

1
0_0402_5%1 2 PR322 @ EC_SMB_CK1_R 12 22 AON7408L_DFN8-5
44,52 EC_SMB_CK1 SCL GND PC321
2200P_0201_25V7-K

3
2
1

2
0_0402_5%1 2 PR323 @ ADP_I_R 7 29 EMC@

0.1U_0201_25V6-K

0.1U_0201_25V6-K
44 ADP_I IADP PAD

2
BQ24780_BATDRV

PC322

PC323
IDCHG 8 18
IDCHG BATDRV
9 PR338 10_0603_5%

1
59 Psys PMON 17 2 1
BATSRC
100P_0201_25V8J

100P_0201_25V8J
2

20 SRP_R 2 1 SRP

0.1U_0201_25V6-K
10 SRP PR328 10_0603_5%
44,59 VR_HOT# PROCHOT#

2
PC324

PC325

PC327
100P_0201_25V8J
1

13
CMPIN

1
BATPRES#
PC1108

TB_STAT#
14
1

CMPOUT 19 SRN_R 2 1 SRN

B
ILIM 21 SRN PR329 10_0603_5% B
ILIM
2

0_0402_5%

@
@
PR330

16

15
1

1 2 ILIM_R 1 2 TB_STAT#
+3VALW BATT_TEMP 44,52
PR331 14.7K_0402_1%
316K_0402_1% PR332
0.1U_0201_25V6-K
1
2

PC328

PR333
100K_0402_1%
need config special
1

appliction

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 PWR-CHARGER
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG411
Date: Thursday, January 14, 2016 Sheet 53 of 60
5 4 3 2 1
 5 4 3 2 1

+3VALW

2
PR407
100K_0402_5%
@
V20B+ @

1
PJ401 PU401
2 1
1.5A +3V_VIN 5 9 +3V_PWRGD TDC-5A OCP-12A OVP-120%
2 1 4 IN1 PG

10U_0805_25V6K

10U_0805_25V6K
1 +3VBS 1 2

0.1U_0201_25V6-K
3 IN2 BS

1
PC403

SY8286BRAC_QFN20_3X3
2 IN3 +3VALW

PC401

PC402

PC452
JUMP_43X79 0.1U_0603_25V7-M
IN4 6 @

2
7 LX1 19 PL401 PJ402
8 GND1 LX2 20 +3VLX 1 2 +3VALW_P 2 1
GND2 LX3 2 1

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
18 2.2UH_PCMB063T-2R2MS_8A_20%
D
21 GND3 D
GND4

1
PR414 @ EMC@ JUMP_43X79
EC_ON_R +3VALW_EN 12 +3VALW_P

PC434

PC432

PC431

PC435
1 2 2 1 14 PR403
39,44,55 EC_ON 0_0402_5% +3V_VIN 11 EN1 OUT 2.2_0805_5%

2
0_0402_5% PR415 EN2 13 +3VALW_FB EMC_NS@
10 FF

2
15 NC1
NC2 100mA +3VLP

1M_0402_5%
16 17

0.1U_0201_25V6-K
NC3 LDO

1
PR401
1

PC408
PC410

4.7U_0603_6.3V6K
1
@ 1200P_0201_25V7-K

2
PC409
EMC_NS@

2
PC411
PR405
1 2 1 2

1K_0402_1%
+3VL 1000P_0201_25V7K
+3VLP @
PJ404
2 1
2 1

JUMP_43X39

+3VALW

2
C C
PR406
100K_0402_5%

V20B+

1
@
PJ405
PU402 @ TDC-6A OCP-14A OVP-120%
2 1
2.5A +5V_VIN 5 9 ALW_PWRGD PC415
2 1 IN1 PG ALW_PWRGD 55

10U_0805_25V6K

10U_0805_25V6K
4 1 +5VBS 1 2

0.1U_0201_25V6-K
1
IN2 BS +5VALW

1
PC413

PC414
3 improve Vin PL402
6V， transient performance
IN3
JUMP_43X79 PC412 2 0.1U_0603_25V7-M PJ406
IN4 6 +5VLX 1 2 +5VALW_P 2 1
2

2
LX1 2 1

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
7 19 2.2UH_PCMB063T-2R2MS_8A_20%
8 GND1 LX2 20
GND2 LX3

1
18 JUMP_43X79
GND3

PC417

PC418

PC419

PC420
21 PR410 @ PR411
PR409 GND4 14 +5VALW_OUT 1 2 +5VALW_P 2.2_0805_5% @
EMC@

2
EC_ON_R 1 2 +5VALW_EN 12 OUT EMC_NS@
+5V_VIN 11 EN1 13 0_0402_5%

2
0_0402_5% EN2 FF
15
LDO +5VLP

1
10
NC1
1M_0402_5%

16 17 2
+5VVCC 1 PC423
0.1U_0201_25V6-K

4.7U_0603_6.3V6K
NC2 VCC 100mA
1

1
PC416 1200P_0201_25V7-K

2
1

PC421

PR412

PC422
EMC_NS@
@ SY8288CRAC_QFN20_3X3 1U_0603_25V6M

2
2

PC424
PR413
+5VFB 1 2 1 2

1K_0402_1%
1000P_0201_25V7K

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 PWR_3VALW/5VALW
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
6800pf soft start 2ms AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
47nf soft start 7ms MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG411
WWW.AliSaler.Com
5 4 3 2
Date: Thursday, January 14, 2016
1
Sheet 54 of 60
 5 4 3 2 1

PR500 @
0_0402_5%
1 2 PMIC_VCC

@
PMIC_VCC PR521 1 2 0_0402_5%
EC_ON 39,44,54

PR522
0_0402_5%
D 1 2 D
ALW_PWRGD 54
+5VALW @

+5VLP PR502 @ PR523

1 2 0_0402_5%
10_0603_5% 1 2 PCH_PWR_EN
PR501 @ 1 2 0_0402_5% VDDQ_EN PR520 @

PMIC_EN
44 SYSON 1 2
10_0603_5%
PR503 @ 1 2 0_0402_5% VTT_EN PC500
5 CPU_DRAMPG_CNTL 1 2
PR505
PR504 2 1 1M_0402_5% +1.8VALW_L_EN VDDQ_P 1 2 2.2U_0603_6.3V6K

VSYS_PMIC
2
10_0402_5%
PR506 @ 1 2 0_0402_5% +1.0VALW_EN PC502
44,46 PCH_PWR_EN 0.1u_0201_10V6K

1
PR507 @ 1 2 +1.8VALW_B_EN

0_0402_5%

28

27

41
PU500

9
EC_VPP_PWREN PR508 @ 1 2 +2.5V_DDR_EN
44 EC_VPP_PWREN

VSYS

VCC

PMIC_EN

GND
0_0402_5% @

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K
+2.5V_DDR_EN 29 25 PMIC_SMB_DAT1 PR510 1 2 0_0402_5%
EN_LDO1 SDA EC_SMB_DA3 44

2
PC504

PC505

PC506

PC503

PC508
@
+1.8VALW_L_EN 1 26 PMIC_SMB_CLK1 PR511 1 2 0_0402_5%
EN_LDO2 SCL EC_SMB_CK3 44

1
+1.0VALW_EN 11 24 PMIC_ALERT# PR512 2 1 @ 0_0402_5%
EN_V1P0A T_ALERT_B H_PROCHOT# 4,44
@ @ @ @ @
+1.8VALW_B_EN 16 22 +1.0VALW_PG 1 PAD @ PTC501
EN_V1P8A POK_V1P0A
VDDQ_EN 31 21 +1.8VALW_B_PG 1 PAD @ PTC502
EN_VDDQ POK_V1P8A
+3VALW
2A VTT_EN 36 23 VDDQ_PGOOD
EN_VTT POK_VDDQ
+5VALW TDC-6A OCP-10A OVP-135%
PJ500 @ 12 0.47UH_PCMB063T-R47MS_18A_20% PJ501 @

22U_0603_6.3V6-M
2 1 +1.0VALW_B_VIN 7 LX_V1P0A_12 13 LX_1P0 1 2 +1.0VALW_FB 2 1

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
LV5075AGQV_VQFN40_5X5
2 1 8 VIN_V1P0A_7
VIN_V1P0A_8
LX_V1P0A_13
LX_V1P0A_14
14 PL500 2 1 +1.0VALW

1
100K_0402_5%
15 JUMP_43X79
JUMP_43X39 LX_V1P0A_15

PC509

PC511

PC512

PC513

PC514

PC515

PC516
PC510

1
+1.0VALW_FB

PR513
R_0402
0.1u_0201_10V6K 10

2
EMC_NS@ VO_V1P0A
PL502
@ @ PJ509 @
TDC-2A OCP-6A OVP-135%
PJ508 @ 17 LX_1P8 1 2 +1.8VALW_FB 2 1

22U_0603_6.3V6-M
2 1 +1.8VALW_B_VIN 19 LX_V1P8A_17 18 2 1 +1.8VALW
+3VALW

2
2 1 VIN_V1P8A_19 LX_V1P8A_18 1UH_PH041H-1R0MS_3.8A_20% JUMP_43X79

22U_0603_6.3V6-M

22U_0603_6.3V6-M
obligation

1
20 +1.8VALW_FB

LX_1P0

LX_1P8
JUMP_43X39 VO_V1P8A_20

1
PC534

PC535

PC536
C C

2
33 UG_VDDQ

2
38 UGATE_VDDQ PR1031 PC518
PC517 1 2 10U_0603_10V6K +1.2V_P VIN_VTT 32 BST_VDDQ 1 2 2 1
BOOT_VDDQ

1
PJ504 @
2 1 39 0_0603_5% 0.1U_0603_25V7-M PR1029 PR1030
+0.6VS 2 1 VTT 34 LX_VDDQ 4.7_0603_5% 4.7_0603_5%

22U_0603_6.3V6-M
VDDQ_PGOOD 44 PHASE_VDDQ

1
EMC@ EMC@
2A JUMP_43X39 LG_VDDQ

PC519
40 35

2
VSNS_VTT LGATE_VDDQ

2
PR515 @ 37 +1.2V_P
VSNS_VDDQ

1
1 2 30
33K_0402_1% CS_VDDQ PC1109 PC1110

1A 600mA 2200P_0201_25V7-K 2200P_0201_25V7-K

2
PJ502 @ PJ503 @ EMC@ EMC@
2 1 +2.5V_DDR_VIN 5 6 +2.5V_P 2 1
+3VALW 2 1 VIN_LDO1 LDO1 2 1 +2.5V_DDR
PC521
1 2
JUMP_43X39 1 2 JUMP_43X39 6mA
PC520 22U_0603_6.3V6-M
10U_0603_10V6K 3
4 LDO2
VIN_LDO2 2
FB_LDO2

VDDQ_P
2A PJ506
2 1
2 1 V20B+

0.1U_0201_25V6-K
5

10U_0805_25V6K

10U_0805_25V6K
JUMP_43X39

EMC@ PC524
@

1
PC525

PC526
PQ500

2
UG_VDDQ 4
AON7408L_DFN8-5
TDC-6A OCP-10A OVP-120%

3
2
1
0.68UH_PCMB063T-R68MS_16A_+-20%
PJ507
PL501
LX_VDDQ 1 2 +1.2V_P 2 1
2 1 +1.2V

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
JUMP_43X79

2
AON7506_DFN @

0.1U_0402_25V6
1

1
4.7_0805_5% @

1
PC527

PC528

PC529

PC530

PC531

PC532
PC1113
B PR518 B
PQ501 EMC_NS@

2
1

2
LG_VDDQ 4

1
PC533
68P_0402_50V8J EMC_NS@
EMC_NS@

3
2
1

2
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 PWR PMIC-DDR4/1.0ALW/1.8ALW
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS D 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG411
Date: Thursday, January 14, 2016 Sheet 55 of 60
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 PWR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG411
Date: Thursday, January 14, 2016 Sheet 56 of 60
5 4 3 2 1

WWW.AliSaler.Com
 5 4 3 2 1

+5VALW
D D

obligation 2A

1
PC702
1U_0402_6.3V6K TP Pin connect to GND +1.05VSP_VGA +1.05VGS

2
500mA OPT@
PU701
PJ701 6 PJ702
2 1 +1.05VGS_VIN 5 VPP 3 2 1
+1.8VALW 2 1 9 VIN VO1 4 2 1
TP OPT@VO2

22U_0603_6.3V6-M

22U_0603_6.3V6-M
JUMP_43X39 JUMP_43X39

1
2 1 +1.05VGS_EN 8
VEN

1
22,23,58 EN_VGA +1.05VGS_FB

PC703

PC704
@ 0_0402_5% 7 2 PR706 PC708 @ @

GND
PC701 PR705 POK ADJ

.1U_0402_10V6-K
220P_0201_25V7-K

2
22U_0603_6.3V6-M @ 22.6K_0402_1% @

PC706
@ G971MF11U _SO8
OPT@

2
100K_0402_5%
OPT@

1
2

PR702
OPT@

1
PR1032 @ PR707

2
1 2 71.5K_0402_1%
8,24,58 DGPU_PWROK
0_0402_5% +3VALW

2
OPT@

C C

V20B+
@ 2A
PJ703
2 1 1.35V_B+
2 1
10U_0805_25V6K

10U_0805_25V6K
0.1U_0201_25V6-K
1

1
PC1087

PC1090

PC1088

JUMP_43X79 @
2

0.1U_0603_25V7-M
PU702
BST_1.35V
0_0603_5% PC1086 TDC-8A OCP-14A OVP-120%
1 10 1 PR1022 2 2 1 0.68UH_PCMB063T-R68MS_16A_+-20% @
VIN BST PL702 PJ704
OPT@ LX_1.35V 1.35V_L
EMC@ PR1017 100K_0402_1% 9 OPT@ OPT@ 1 2 2 1
1 2 S3_1.35V 16 SW 2 1
+1.35VGS

NB685GQ-Z_QFN16_3X3
EN1

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
PR1021 OPT@ JUMP_43X118
S5_1.35V 1.35V_FB

EMC_OPTNS@

2.2_0805_5%
OPT@ 1 2 15 13 @ PC1091
22,24 FBVDDQ_PWR_EN EN2 FB

1
PC1094

PC1082

PC1083

PC1097

PC1089
10K_0402_1% 2 1 1 2

PR1026
OPT@ 1M_0402_5%
1.35V_L
0.1u_0201_10V6K

2 1 12 6 PR1024 220P_0201_25V7-K

2
PR1019 100K_0402_1% PG OPT@ VDDQ
@
2

DDR_3V3 @
PC1084

OPT@ 3

2
3V3

1
499_0402_1%

41.2K_0402_1%
5
1U_0402_6.3V6K

1.35V_SN
VTT

PR1023

PR1020
OPT@ OPT@ OPT@ OPT@ OPT@
1

2
@
PC1085
4.7_0402_5%

4
AGND
1 PR1018 2

8
2 VTTS
2

2
PGND

1200P_0201_25V7-K
7

22U_0603_6.3V6-M
VTTREF
VTTREF

EMC_OPTNS@

1
1

1
PC1093
OPT@ Mode 14 11
MODE OTW# OPT@

PC1092
1U_0402_6.3V6K
B OPT@ 1.35V_FB B

2
2

PC1095
1.35V_GND
PR1027 @
+3VALW

1
0_0402_5%

2
OPT@ PR1028
32.4K_0402_1%
1

OPT@
1.35V_GND

2
1.35V_GND
OPT@

1.35V_GND

PJ705
1 2

JUMPER
@

1.35V_GND

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 PWR-+1.05VGS/+1.35V_VRAM
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG411
Date: Thursday, January 14, 2016 Sheet 57 of 60
5 4 3 2 1
 5 4 3 2 1

NVVDD_PWM_VID
20 NVVDD_PWM_VID

20 PSI_VGA PSI_VGA

VSSSENSE_VGA
21 VSSSENSE_VGA
D VCCSENSE_VGA D
21 VCCSENSE_VGA +VGA_B+
8,24,57 DGPU_PWROK DGPU_PWROK V20B+
@
PJ801
1.5A 2
2 1
1

JUMP_43X118

10U_0805_25V6K

10U_0805_25V6K
0.1U_0201_25V6-K
1

1
+3VGS

PC801

PC802

PC803
5
pr9446 OPT@

2
2

PQ801

NVVDD_PWM_VID
PR835 @ PR811 AON6372_DFN8-5 EMC_OPT@
1 2 10K_0402_5% OPT@
8,22 PXS_PWREN
@ PD801 OPT@ OPT@
0_0402_5% RB751V-40_SOD323-2 VGA_UGATE1 4
1

OPT@
2 1 1 2 EN_VGA EN_VGA 22,23,57
20,22 3VGS_PWR_EN
PR841 OPT@
1

1
0_0402_5% PC812 0.22UH_PCMB063T-R22MS_23A_20%
+VGA_CORE

3
2
1
@ PR814 PR817 @ 0.1u_0201_10V6K PL801
100K_0402_5% 1 2 OPT@ VGA_PHASE1 1 2

1200P_0201_25V7-K 2.2_0805_5%
@

EMC_OPTNS@ EMC_OPTNS@
0_0402_5% PQ802
2

PR808
reserve PR807 PC806 AON6764_DFN8-5

2
VGA_BOOT1 1 2 1 2
PR826 @

OPT@

330U_2.0V_M

330U_2.0V_M
0_0402_5% 0_0603_5% 0.22U_0603_16V7K 1 1

2
OPT@ OPT@
VGA_LGATE1 + +

PC808

PC807
4

PC809
PC816 OPT@ 2 2

2
10P_0201_25V8G
1 2 OPT@ OPT@

3
2
1
1

VGA_UGATE1
C C

VGA_BOOT1
PC821
2700P_0402_50V7-K

GPU_VID

PSI_VGA
@

EN_VGA
2
PR804
VREF_VGA 1 2
1

20K_0402_1% OPT@ PR803

20K_0402_1%

1
OPT@
PR818 @ PR801 OPT@ PR802

UGATE1

BOOT1
VID

PSI

EN
2

1 2 1 2 1 2
18K_0402_1% PC810
0_0402_5% 2K_0402_1% OPT@ 6 20 VGA_PHASE1 4.7U_0603_6.3V6K
REFADJ PHASE1

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
PC805
1 2 REFIN 7 19 VGA_LGATE1 1 2 OPT@
REFIN LGATE1

1
PC832
PC804
2 VREF_VGA PVCC_VGA

PC829

PC830

PC831

PC833

PC834
2700P_0402_50V7-K 1 8 OPT@ 18 1 2 +5VS
PR839 OPT@ VREF PVCC
OPT@ PR830

2
+VGA_B+ 1 2 1 2 0.1U_0603_25V7K 9 17 VGA_LGATE2 0_0402_5%
2.2_0603_5% 430K_0402_1% TON LGATE2 PR815 @
PC826 OPT@ OPT@ VSS_SEN 10 16 VGA_PHASE2
RGND PHASE2
UGATE2
2 1 OPT@ @ OPT@ OPT@ OPT@ @
PGOOD

BOOT2
VSNS
GND

0.1U_0201_25V6-K frequency change to 300K SIT

SS

OPT@ PU801
21

11

12

13

14

15

RT8812AGQW_WQFN20_3X3
+VGA_B+
VCC_SEN

VGA_UGATE2

1.5A
VGA_BOOT2

PR831
2 1
1000P_0201_25V7K

10U_0805_25V6K
100_0402_5%
PC824

10U_0805_25V6K
0.1U_0201_25V6-K
1

OPT@

1
PC813

PC814

PC815
PR836 @
DGPU_PWROK

B VSSSENSE_VGA VSS_SEN B
1 2 PQ803
2
OPT@

PR822 AON6372_DFN8-5

2
0_0402_5% PC842 10K_0402_1% OPT@
1

EMC_OPT@
1000P_0201_25V7K OPT@ VGA_UGATE2 4 OPT@
1

@ OPT@
2

PR837 @
VCCSENSE_VGA 1 2 VCC_SEN
+3VGS OPT@
TDC-31A

3
2
1
0_0402_5% 0.22UH_PCMB063T-R22MS_23A_20%
+VGA_CORE

PL802
PR832
VGA_PHASE2 1 2 +VGA_CORE

2.2_0805_5%
1

EMC_OPTNS@
1 2 PQ804

PR824
PR823 PC817 OPT@ AON6764_DFN8-5
VGA_BOOT2 1 2 1 2
100_0402_5%

OPT@
OPT@

330U_2.0V_M

330U_2.0V_M
0_0603_5% 0.22U_0603_16V7K 1 1

1 2
OPT@
VGA_LGATE2 + +

PC820

PC818

PC819
1200P_0201_25V7-K
4

EMC_OPTNS@
2
2 2
OPT@ OPT@

3
2
1

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 PWR-VGA_CORE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG411
WWW.AliSaler.Com 5 4 3 2
Date: Thursday, January 14, 2016
1
Sheet 58 of 60
 5 4 3 2 1

+VCCST_CPU
+5VS +5VS
V20B+

2
2.2_0603_5% 2.2_0603_5%

1
PR922 PR926
+VCCST_CPU

1
1K_0402_1%

75_0402_1%

100_0402_1%
45.3_0402_1%
PC918
D D

PR923

PR933

PR943

PR932
1U_0402_6.3V6K

2
@

2.2U_0603_10V7K

2.2U_0603_10V7K
2

2
53 Psys

PC912

PC916

VR_VCC

VR_VRMP
VR_PVCC
1

1
PC920

1
0.01U_0201_25V6-K

1K_0402_1%

1K_0402_1%
@

2
PR945

PR946
PR944 PR936
54.9_0402_1% @ @ 10_0402_1%
VR_SVID_DAT_1 2 1

18

13

12
VR_SVID_DAT 12
20K_0402_1% PU901 NCP81206MNTXG_QFN52_6X6 PR937

2
1 PR940 2 50 36 VR_SVID_DAT_1 0_0402_5%

VRMP
PVCC

VCC
PSYS SDIO 38 VR_SVID_CLK_1 VR_SVID_ALRT#_1 2 1
SCLK 37 VR_SVID_ALRT#_1 VR_SVID_ALRT# 12
PR916 @ PR938
1 2 VR_EN 41 ALERT# 49.9_0402_1%
44 EC_VR_ON EN VR_SVID_CLK_1 2 1
VR_SVID_CLK 12
0_0402_5% 39
42 DRON
44 CPU_VR_READY VR_RDY
35
44,53 VR_HOT# VRHOT# PR919 PC910
26 Vcore_BST1 2 1 2
BST3 23.2K_0402_1%
2.7K_0402_1% 1500P_0402_50V6-K
VCORE  PORTION 2.2_0603_5% 0.22U_0603_16V7K 1 PR947 2
Vcore_COMP Vcore_PH 60
1 PR903 2 2 1 PC902 30 25
COMP_1a HG3 Vcore_HG 60
20K_0402_1%
1 2 2 PR901 1Vcore_ILIM 31
ILIM_1a
22K_0402_1% PH905 +CPU_CORE
PC901 15P_0402_50V8J 1 2 24 Vcore_PH 1 PR948 2 1 2
1.58K_0402_1% 1000P_0402_50V7K PC909 SW3
1 PR913 2 Vcore_VSP 28 100K_0402_1%_NCP15WF104F03RC
12 VCORE_VCC_SEN VSP_1a
1 2 1 2 23
LG3/ICCMAX_1b Vcore_LG 60
2

PC913 PR910 PC904 1000P_0402_50V7K 1K_0402_1% 11K_0402_1% 1 2

1000P_0402_50V7K 1.58K_0402_1% 1 PR911 2 Vcore_VSN 29 1 PR941 2 PC942 3300P_0402_50V7-K
470P_0402_50V7K VSN_1a
1

1 2 2 1 Vcore_IOUT 34 33 Vcore_CSP 1 2
12 VCORE_VSS_SEN IOUT_1a CSP_1a
C 330P_0402_50V7K PC906 PC911 PC922 2200P_0402_50V7K C
2 1 27 32
PR917 TSENSE_1ph CSN_1a
45.3K_0402_1%
Vcore_TSENSE
PR949
VCCGT PORTION
1

7 GT_CSSUM 1 2
CSSUM_2ph GT_PH 60
PR942
MOSFET

0_0402_5% 6 GT_CSCOMP PR950 1 2 180K_0402_1% 1 2 PR904 105K_0402_1%

470P_0402_50V7K CSCOMP_2ph 110K_0402_1%
100K_0402_1%_NCP15WF104F03RC

2 1 1 2
2

PC930 PH901 1 2 PC925

GT_IOUT PR951 220P_0402_50V7K
2 1 1 220K_0402_5%_ERTJ0EV224J
IOUT_2ph
1

GT_ILIM
8.25K_0402_1%

25.5K_0402_1% 100K_0402_1% 5 1 2 2 1
.1U_0402_10V6-K

ILIM_2ph +VCC_GT
1
Place close to

PH902

PR931

PC924

PR959 PR902 12.7K_0402_1% PC914 330P_0402_50V7K 10_0402_1%

2 1 8 GT_CSREF 1 PR924 2
CSREF_2ph

0.22U_0603_16V7K
2

GT_DIFFOUT 2 14 GT_BST1 1 2

0.01U_0402_25V7K
2

DIFFOUT_2ph/ICCMAX_2ph BST1

PC915
470P_0402_50V7K PR934 2200P_0402_50V7K PR925 2.2_0603_5%
2 GT_COMP 4

PC917
1 PR914 2 1 2 1 2 1
COMP_2ph

1
49.9_0402_1%PC907 13.7K_0402_1% PC908 15
HG1 GT_HG 60
1 2 1 2

1
PR918 PC932 10P_0402_50V8J 0.047U_0402_16V7K

2
1K_0402_1% GT_FB 3 16 GT_PH PC926
FB_2ph SW1

2
17
LG1/ROSC GT_LG 60
PR954
2 1
51 14K_0402_1%
12 VCCGT_VCC_SEN VSP_2ph GT_CSP1 GT_PH
10 1 2
CSP1_2ph
2

1.5K_0402_1% PR953
GT_VSN 52 PR952
PC931 1 PR964 2 1.8K_0402_1%
1000P_0402_50V7K VSN_2ph 9 GT_CSP2 2 1
+5VS
1

1 2 CSP2_2ph
12 VCCGT_VSS_SEN
PC933 2200P_0402_50V7K 1 2
22.1K_0402_1% 0_0402_5%
B B
PR927
GT_TSENSE 11 40
TSENSE_2ph PWM/ADDR_VBOOT

1.5K_0402_1% 0.015U_0402_25V7-K DIS GT one phase

0.22U_0603_16V7K
1 PR965 2 2 1 PC936 SA_COMP 47 22 SA_BST 1 2
COMP_1b BST2
1

PC989
PR989 2.2_0603_5% 13K_0402_1%
PR960 1 2 PR912 VCCSA PORTION 1 PR956 2
SA_PH 60

2
0_0402_5% PC935 15P_0402_50V8J 2 1 SA_ILIM 46 21
ILIM_1b HG2 SA_HG 60
30.9K_0402_1%
100K_0402_1%_NCP15WF104F03RC

1 2 22K_0402_1% PH904 +VCCSA

2

1
1000P_0402_50V7K PC940 20 SA_PH 1 PR957 2 1 2
3.16K_0402_1% SW2 22.6K_0402_1%
1

SA_VSP 49
8.25K_0402_1%

1 PR966 2 19 1 PR955 2 100K_0402_1%_NCP15WF104F03RC

.1U_0402_10V6-K

13 VCCSA_VCC_SEN VSP_1b LG2/ICCMAX_1a

1
PH903

PR963

PC934

3.16K_0402_1%
2

1 PR907 2 1 2 1K_0402_1% 1 2
SA_VSN 48 SA_LG 60
PC937 PC938 1000P_0402_50V7K 1 PR970 2 PC941 6800P_0402_25V7-K
2

VSN_1b
IOUT_1b

1000P_0402_50V7K 44 SA_CSP 1 2
2

CSP_1b
EPAD

1 2 PC927 5600P_0402_25V7-K
13 VCCSA_VSS_SEN
220P_0402_50V7K PC939 45
CSN_1b
43

53

SA_Iout
1
1

PC929 PR958
121K_0402_1%
470P_0402_50V7K
2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 PWR_CPU_CORE1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG411
Date: Thursday, January 14, 2016 Sheet 59 of 60
5 4 3 2 1
 A
B
C
D

59 GT_LG
59 GT_PH
59 GT_HG
59 Vcore_PH

59 Vcore_LG
59 Vcore_HG

4
4

5
5

4
4

3 5 3 5
2 2
1 1 3 5 3 5
2 2
1 1

PQ1006
PQ1005
PQ1002
PQ1001

AON6764_DFN8-5
AON6372_DFN8-5
AON6764_DFN8-5
AON6372_DFN8-5

2 1 2 1

WWW.AliSaler.Com
2 1 2 1
EMC@

PC1047
PR1008
PR1002

EMC_NS@
PC1001
PC1026

EMC_NS@
EMC_NS@

0.1U_0201_25V6-K

2.2_0805_5%
2.2_0805_5%

EMC_NS@

2 1

EMC@

1200P_0201_25V7-K
PC1032
1000P_0201_25V7K

0.1U_0201_25V6-K PC1002
2 1 10U_0805_25V6K
2 1
1

1
PC1033 PC1003
10U_0805_25V6K 10U_0805_25V6K
2 1 2 1
PL1001

PL1003
2

4
4

PC1031

2
10U_0805_25V6K
Vcore_PH

2 1
CPU_VIN

GT_PH
0.15UH_PCMB063T-R15MS_30A_20%

0.15UH_PCMB063T-R15MS_30A_20%
2

+VCC_GT
+CPU_CORE
2

@
PJ1001

CPU_VIN
1
1

JUMP_43X79

2
1
+

2
1
1

+
+

2 3

330U_2.0V_M
PC1045 PC1015
PC1004

220U_D2_2VM_R6M
68U_25V_M

1
+

2 3
EMC@

PC1066 PC1078
@

220U_D2_2VM_R6M 0.1U_0201_25V6-K
2
1
+

2 1
EMC_NS@
PC1080
0.1U_0402_25V7-K
2 1 PC1079
PC1107

2200P_0201_25V7-K
68U_25V_M

2 1
59 SA_LG

PC1081
59 SA_PH
59 SA_HG

2200P_0201_25V7-K
V20B+

2 1
EMC_NS@
+CPU_CORE

EMC_NS@

3
3

+VCC_GT

2 1 2 1
@

PC1067 PC1052
22U_0603_6.3V6-M 22U_0603_6.3V6-M
2 1 2 1
@
@

PC1068 PC1053
22U_0603_6.3V6-M 22U_0603_6.3V6-M
2 1 2 1

Issued Date
PC1069 PC1054
22U_0603_6.3V6-M 22U_0603_6.3V6-M

Security Classification
2 1 2 1

PC1070 PC1055
22U_0603_6.3V6-M 22U_0603_6.3V6-M
4
4

2 1 2 1

PC1071 PC1056 3 5 3 5
22U_0603_6.3V6-M 22U_0603_6.3V6-M 2 2
2 1 2 1 1 1

PC1072 PC1057

2015/08/20
22U_0603_6.3V6-M 22U_0603_6.3V6-M
2 1 2 1
@

2 1 2 1
PQ1004
PQ1003

PC1073 PC1058
AON7506_DFN

22U_0603_6.3V6-M 22U_0603_6.3V6-M PC1022 PC1005

2 1 2 1 22U_0603_6.3V6-M 22U_0603_6.3V6-M
2 1 2 1 2 1 2 1
@
@

AON7408L_DFN8-5

PC1074 PC1059 PC1016 PC1006

22U_0603_6.3V6-M 22U_0603_6.3V6-M 22U_0603_6.3V6-M 22U_0603_6.3V6-M
EMC@

2 1 2 1 2 1
PC1046
PR1006

2 1 PC1027
EMC_NS@
EMC_NS@

PC1075 0.1U_0201_25V6-K PC1023 PC1007

2
2

2.2_0805_5%

22U_0603_6.3V6-M PC1060 2 1 22U_0603_6.3V6-M 22U_0603_6.3V6-M

2 1 22U_0603_6.3V6-M 2 1 2 1
1200P_0201_25V7-K

2 1
Deciphered Date PC1076 PC1017 PC1008
1

22U_0603_6.3V6-M PC1061 PC1028 22U_0603_6.3V6-M 22U_0603_6.3V6-M

2 1 22U_0603_6.3V6-M 10U_0805_25V6K
2 1 2 1 2 1 2 1
@

PC1077
LC Future Center Secret Data

22U_0603_6.3V6-M PC1062 PC1029 PC1025 PC1009

PL1002

22U_0603_6.3V6-M 10U_0805_25V6K 22U_0603_6.3V6-M 22U_0603_6.3V6-M

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2 1 2 1 2 1
2 1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

PC1063 PC1018
@

22U_0603_6.3V6-M 2 1 22U_0603_6.3V6-M PC1013

SA_PH
0.47UH_PCMB063T-R47MS_18A_20%

2 1 22U_0603_6.3V6-M
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
2016/08/20
+VCCSA
@

2 1 PC1112 2 1
@

47U_0603_4V6-M PC1024
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

PC1064 22U_0603_6.3V6-M PC1010

@

22U_0603_6.3V6-M 2 1 2 1 22U_0603_6.3V6-M
2 1
PC1111 PC1019
2

47U_0603_4V6-M 22U_0603_6.3V6-M PC1011

2 1
2

22U_0603_6.3V6-M
@

2 1 2 1
+VCC_GT

PC1020
PJ1002
1

PC1036 22U_0603_6.3V6-M PC1014

Size

Date:

22U_0603_6.3V6-M 22U_0603_6.3V6-M
Title
1

JUMP_43X79

2 1
2 1 2 1
PC1021
PC1037 22U_0603_6.3V6-M PC1012
22U_0603_6.3V6-M 22U_0603_6.3V6-M

2 1
Document Number

PC1038
V20B+

22U_0603_6.3V6-M
2 1
+CPU_CORE

PC1039
1
1

22U_0603_6.3V6-M
PWR_CPU_CORE2

2 1
Thursday, January 14, 2016
CG411

PC1040
22U_0603_6.3V6-M
2 1
Sheet

PC1041
22U_0603_6.3V6-M
60
@

2 1
of

PC1042
22U_0603_6.3V6-M
+VCCSA

60
Rev
1.0
A
B
C
D