Professional Documents
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Preface
Notebook Computer
NL40CU / NL41CU
Service Manual
Preface
I
Preface
Notice
The company reserves the right to revise this publication or to change its contents without notice. Information contained
herein is for reference only and does not constitute a commitment on the part of the manufacturer or any subsequent ven-
dor. They assume no responsibility or liability for any errors or inaccuracies that may appear in this publication nor are
they in anyway responsible for any loss or damage resulting from the use (or misuse) of this publication.
This publication and any accompanying software may not, in whole or in part, be reproduced, translated, transmitted or
reduced to any machine readable form without prior consent from the vendor, manufacturer or creators of this publica-
tion, except for copies kept by the user for backup purposes.
Brand and product names mentioned in this publication may or may not be copyrights and/or registered trademarks of
their respective companies. They are mentioned for identification purposes only and are not intended as an endorsement
of that product or its manufacturer.
Preface
Version 1.0
November 2019
Trademarks
Pentium and Celeron are trademarks of Intel Corporation.
Windows® is a registered trademark of Microsoft Corporation.
Other brand and product names are trademarks and /or registered trademarks of their respective companies.
II
Preface
It is organized to allow you to look up basic information for servicing and/or upgrading components of the NL40CU /
NL41CU series notebook PC.
Chapter 1, Introduction, provides general information about the location of system elements and their specifications.
Chapter 2, Disassembly, provides step-by-step instructions for disassembling parts and subsystems and how to upgrade
elements of the system.
Preface
Appendix B, Schematic Diagrams
III
Preface
1. Do not use this product near water, for example near a bath tub, wash bowl, kitchen sink or laundry tub, in a wet
basement or near a swimming pool.
2. Avoid using a telephone (other than a cordless type) during an electrical storm. There may be a remote risk of elec-
trical shock from lightning.
3. Do not use the telephone to report a gas leak in the vicinity of the leak.
4. Use only the power cord and batteries indicated in this manual. Do not dispose of batteries in a fire. They may
explode. Check with local codes for possible special disposal instructions.
5. This product is intended to be supplied by a Listed Power Unit with an AC Input of 100 - 240V, 50 - 60Hz, DC Output
of 19V, 2.1A (40 Watts) minimum AC/DC Adapter.
Preface
FCC Statement
This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions:
This device may not cause harmful interference.
This device must accept any interference received, including interference that may cause undesired operation.
IV
Preface
1. Don’t drop it, or expose it to shock. If the computer falls, the case and the components could be damaged.
Do not expose the computer Do not place it on an unstable Do not place anything heavy
to any shock or vibration. surface. on the computer.
2. Keep it dry, and don’t overheat it. Keep the computer and power supply away from any kind of heating element. This
is an electrical appliance. If water or any other liquid gets into it, the computer could be badly damaged.
Do not expose it to excessive Do not leave it in a place Don’t use or store the com- Do not place the computer on
Preface
heat or direct sunlight. where foreign matter or mois- puter in a humid environment. any surface which will block
ture may affect the system. the vents.
3. Follow the proper working procedures for the computer. Shut the computer down properly and don’t forget to save
your work. Remember to periodically save your data as data may be lost if the battery is depleted.
Do not turn off the power Do not turn off any peripheral Do not disassemble the com- Perform routine maintenance
until you properly shut down devices when the computer is puter by yourself. on your computer.
all programs. on.
V
Preface
4. Avoid interference. Keep the computer away from high capacity transformers, electric motors, and other strong mag-
netic fields. These can hinder proper performance and damage your data.
5. Take care when using peripheral devices.
Power Safety
Preface
VI
Preface
Battery Precautions
• Only use batteries designed for this computer. The wrong battery type may explode, leak or damage the computer.
• Do not continue to use a battery that has been dropped, or that appears damaged (e.g. bent or twisted) in any way. Even if the
computer continues to work with a damaged battery in place, it may cause circuit damage, which may possibly result in fire.
• Recharge the batteries using the notebook’s system. Incorrect recharging may make the battery explode.
• Do not try to repair a battery pack. Refer any battery pack repair or replacement to your service representative or qualified service
personnel.
• Keep children away from, and promptly dispose of a damaged battery. Always dispose of batteries carefully. Batteries may explode
or leak if exposed to fire, or improperly handled or discarded.
• Keep the battery away from metal appliances.
• Affix tape to the battery contacts before disposing of the battery.
• Do not touch the battery contacts with your hands or metal objects.
Battery Guidelines
The following can also apply to any backup batteries you may have.
Preface
• If you do not use the battery for an extended period, then remove the battery from the computer for storage.
• Before removing the battery for storage charge it to 60% - 70%.
• Check stored batteries at least every 3 months and charge them to 60% - 70%.
Battery Disposal
The product that you have purchased contains a rechargeable battery. The battery is recyclable. At the end of its useful life, under var-
ious state and local laws, it may be illegal to dispose of this battery into the municipal waste stream. Check with your local solid waste
officials for details in your area for recycling options or proper disposal.
Caution
Danger of explosion if battery is incorrectly replaced. Replace only with the same or equivalent type recommended by the manufacturer.
Discard used battery according to the manufacturer’s instructions.
Battery Level
Click the battery icon in the taskbar to see the current battery level and charge status. A battery that drops below a level of 10%
will not allow the computer to boot up. Make sure that any battery that drops below 10% is recharged within one week.
VII
Preface
Related Documents
You may also need to consult the following manual for additional information:
System Startup
180°
1. Remove all packing materials.
2. Place the computer on a stable surface.
3. Insert the battery and make sure it is locked in position.
4. Securely attach any peripherals you want to use with the
computer (e.g. keyboard and mouse) to their ports.
Preface
Powering the
• Attach the AC/DC adapter cord to the DC-In jack on the
Computer On right of the computer, then plug the AC power cord into
an outlet, and connect the AC power cord to the AC/DC
After every disassem-
bly, make sure that the
adapter. The battery will now be unlocked.
6. Use one hand to raise the lid/LCD to a comfortable viewing Shut Down
bottom case’s screws
angle (do not exceed 180 degrees); use the other hand (as
are all inserted and Note that you should always shut your computer down by choosing the
tightened before turn-
illustrated in Figure 1) to support the base of the computer Shut down command in Windows (see below). This will help prevent
ing the computer on. (Note: Never lift the computer by the lid/LCD). hard disk or system problems.
7. Press the power button on the left side of the computer to
Click Settings in the Charms Bar (use the Windows Logo Key
turn the computer “on” (note that the lid/LCD must be open
+ C key combination to access the Charms Bar) and choose Shut
for the power button to function). down from the Power menu.
Or
Choose Shut down or sign out > Shut down from the context menu
(use the Windows Logo Key + X key combination to access the
context menu).
VIII
Preface
Contents
Introduction ..............................................1-1 Schematic Diagrams................................. B-1
Overview .........................................................................................1-1 System Block Diagram ...................................................................B-2
Specifications ..................................................................................1-2 Processor 1/12 .................................................................................B-3
External Locator - Top View with LCD Panel Open ......................1-4 Processor 2/12 .................................................................................B-4
External Locator - Front & Right Side Views .................................1-5 Processor 3/12 .................................................................................B-5
External Locator - Left Side & Rear View .....................................1-6 Processor 4/12 .................................................................................B-6
External Locator - Bottom View .....................................................1-7 Processor 5/12 .................................................................................B-7
Mainboard Overview - Top (Key Parts) .........................................1-8 Processor 6/12 .................................................................................B-8
Mainboard Overview - Bottom (Key Parts) ....................................1-9 Processor 7/12 .................................................................................B-9
Mainboard Overview - Top (Connectors) .....................................1-10 Processor 8/12 ...............................................................................B-10
Mainboard Overview - Bottom (Connectors) ...............................1-11 Processor 9/12 ...............................................................................B-11
Disassembly ...............................................2-1 Processor 10/12 .............................................................................B-12
Preface
Processor 11/12 .............................................................................B-13
Overview .........................................................................................2-1 Processor 12/12 .............................................................................B-14
Maintenance Tools ..........................................................................2-2 DDR4 SO-DIMM_0 .....................................................................B-15
Connections .....................................................................................2-2
DDR4 SO-DIMM_1 .....................................................................B-16
Maintenance Precautions .................................................................2-3 HDMI ............................................................................................B-17
Disassembly Steps ...........................................................................2-4 Panel .............................................................................................B-18
Removing the Battery ......................................................................2-5
USB / DP MUX ANX7440 ..........................................................B-19
Removing the System Memory (RAM) ..........................................2-7 ANX7411, Type-C .......................................................................B-20
Removing the Wireless LAN Module .............................................2-9
ASM1543 ......................................................................................B-21
Wireless LAN, and Combo Module Cables ..................................2-10 LED KB, LED ..............................................................................B-22
Removing and Installing the M.2 SSD Module ............................2-11 SATA HDD, TPM ........................................................................B-23
Removing the CCD .......................................................................2-12
Audio Codec .................................................................................B-24
Part Lists ..................................................A-1 KBC ITE IT5570 ..........................................................................B-25
Part List Illustration Location ........................................................ A-2 WLAN ..........................................................................................B-26
Top ................................................................................................. A-3 M Key PCIE SSD .........................................................................B-27
Bottom ............................................................................................ A-4 3G/LTE .........................................................................................B-28
LCD ................................................................................................ A-5 USB Type-A .................................................................................B-29
MB .................................................................................................. A-6 Conn, CCD, Fan, TP .....................................................................B-30
IX
Preface
X
Introduction
Chapter 1: Introduction
Overview
This manual covers the information you need to service or upgrade the NL40CU / NL41CU series notebook computer.
Information about operating the computer (e.g. getting started, and the Setup utility) is in the User’s Manual. Information
about dri-vers (e.g. VGA & audio) is also found in the User’s Manual. The manual is shipped with the computer.
Operating systems (e.g. Window 10, etc.) have their own manuals as do application softwares (e.g. word processing and
database programs). If you have questions about those programs, you should consult those manuals.
The NL40CU / NL41CU series notebook is designed to be upgradeable. See Disassembly on page 2 - 1 for a detailed
1.Introduction
description of the upgrade procedures for each specific component. Please take note of the warning and safety informa-
tion indicated by the “” symbol.
The balance of this chapter reviews the computer’s technical specifications and features.
Overview 1 - 1
Introduction
Intel® Core™ i7 Processor Built-In Click Pad (with Microsoft PTP Multi Gesture & Scroll-
i7-10510U (1.80GHz) ing Functionality)
8MB Smart Cache, 14nm, DDR4-2666MHz, TDP 15W
Intel® Core™ i5 Processor
Keyboard
Latest Specification Information i5-10210U (1.60GHz) Multi languages A4-size isolated Keyboard
The specifications listed here are correct at the 6MB Smart Cache, 14nm, DDR4-2666MHz, TDP 15W
Intel® Core™ i3 Processor Audio
time of sending them to the press. Certain items
(particularly processor types/speeds) may be i3-10110U (2.10GHz) High Definition Audio Compliant Interface
changed, delayed or updated due to the manu- 4MB Smart Cache, 14nm, DDR4-2666MHz, TDP 15W 2 * Built-In Speakers
facturer's release schedule. Check with your
service center for more details. BIOS Built-In Array Microphone
(Factory Option) Built-In Microphone
128Mb SPI Flash ROM
Security
1.Introduction
Insyde BIOS
Video Adapter
1 - 2 Specifications
Introduction
Communication Power
1.Introduction
One USB 3.1 Gen 2 Type-C Port* Dimensions & Weight
*The maximum amount of current supplied by USB Type-C
ports is 500mA (USB 2.0)/1500mA (USB 3.1). 324.9mm (w) * 219.5mm (d) * 18.95mm (h)
1.29kg (Barebone with 36WH Battery)
One USB 3.1 Gen 2 Type-A Port
One HDMI-Out Port
One 2-In-1 Audio Jack (Headphone and Microphone)
One DC-in Jack
One RJ-45 LAN Jack
One USB 2.0 Port
USB 3.1 Gen 2
Note that when a single USB device is plugged
in to a USB 3.1 Gen 2 port the data transfer
speed will be 10Gbps, however when two devic-
es are plugged in to both USB 3.1 Gen 2 ports,
this bandwidth will be shared between the ports.
Specifications 1 - 3
Introduction
Figure 1
External Locator - Top View with LCD Panel Open
Top View
1. PC Camera
2. *PC Camera LED
*When the PC
camera is in use,
3 2 1 3
the LED will be
illuminated in
white.
3. Built-In 4
Microphone
1.Introduction
4. LCD
5. Vent
6. LED Indicators
7. Keyboard
8. Touchpad &
Buttons 5
6
FRONT VIEW
1.Introduction
Figure 3
Right Side View
1. Speaker
2. USB 3.1 Gen 2
Type-C Port
3. USB 3.1 Gen 2
RIGHT SIDE VIEW Type-A Port
4. HDMI-Out Port
5. Battery Power LED
Indicator
6. DC-In Jack
1 2 3 4 5 6
7. Speaker
1 1 1
1.Introduction
3 3 Overheating
1. KBC-ITE IT5570
1.Introduction
1. CPU
2. Memory Slots
DDR4 SO-DIMM
1.Introduction
2
1
1. DC-In Jack
2. HDMI-Out Port
3. USB 3.1 Gen 2
Type-A Port
4. USB 3.1 Gen 2
Type-C Port
1
1.Introduction
2
11
1. CCD Cable
Connector
2. Fan Connector
3. M.2 Card
Connector
4. Speaker Connecto
11
5. Battery Connector
12 6. Keyboard
1 Connector
1.Introduction
10 7. Touchpad
Connector
8. USB Board
Connector
9. CMOS Battery
2 Connector
9
10. LAN Board
8 Connector
11. WLAN/BT
6 4
5 Connector
7
3 12. LCD Cable
Connector
4
1 - 12
Disassembly
Chapter 2: Disassembly
Overview
This chapter provides step-by-step instructions for disassembling the NL40CU / NL41CU series notebook’s parts and
subsystems. When it comes to reassembly, reverse the procedures (unless otherwise indicated).
We suggest you completely review any procedure before you take the computer apart.
Procedures such as upgrading/replacing the RAM, optical device and hard disk are included in the User’s Manual but are
repeated here for your convenience.
2.Disassembly
To make the disassembly process easier each section may have a box in the page margin. Information contained under
the figure # will give a synopsis of the sequence of procedures involved in the disassembly procedure. A box with a
lists the relevant parts you will have after the disassembly process is complete. Note: The parts listed will be for the dis-
Information
assembly procedure listed ONLY, and not any previous disassembly step(s) required. Refer to the part list for the previ-
ous disassembly procedure. The amount of screws you should be left with will be listed here also.
A box with a will also provide any possible helpful information. A box with a contains warnings.
Overview 2 - 1
Disassembly
NOTE: All disassembly procedures assume that the system is turned OFF, and disconnected from any power supply (the
battery is removed too).
Maintenance Tools
The following tools are recommended when working on the notebook PC:
• M3 Philips-head screwdriver
• M2.5 Philips-head screwdriver (magnetized)
• M2 Philips-head screwdriver
• Small flat-head screwdriver
• Pair of needle-nose pliers
• Anti-static wrist-strap
2.Disassembly
Connections
Connections within the computer are one of four types:
Locking collar sockets for ribbon connectors To release these connectors, use a small flat-head screwdriver to
gently pry the locking collar away from its base. When replac-
ing the connection, make sure the connector is oriented in the
same way. The pin1 side is usually not indicated.
Pressure sockets for multi-wire connectors To release this connector type, grasp it at its head and gently
rock it from side to side as you pull it out. Do not pull on the
wires themselves. When replacing the connection, do not try to
force it. The socket only fits one way.
Pressure sockets for ribbon connectors To release these connectors, use a small pair of needle-nose pli-
ers to gently lift the connector away from its socket. When re-
placing the connection, make sure the connector is oriented in
the same way. The pin1 side is usually not indicated.
Board-to-board or multi-pin sockets To separate the boards, gently rock them from side to side as
you pull them apart. If the connection is very tight, use a small
flat-head screwdriver - use just enough force to start.
2 - 2 Overview
Disassembly
Maintenance Precautions
The following precautions are a reminder. To avoid personal injury or damage to the computer while performing a removal and/or
replacement job, take the following precautions: Power Safety
1. Don't drop it. Perform your repairs and/or upgrades on a stable surface. If the computer falls, the case and other components Warning
could be damaged.
2. Don't overheat it. Note the proximity of any heating elements. Keep the computer out of direct sunlight. Before you undertake
3. Avoid interference. Note the proximity of any high capacity transformers, electric motors, and other strong magnetic fields. any upgrade proce-
These can hinder proper performance and damage components and/or data. You should also monitor the position of magnet- dures, make sure that
you have turned off the
ized tools (i.e. screwdrivers).
power, and discon-
4. Keep it dry. This is an electrical appliance. If water or any other liquid gets into it, the computer could be badly damaged.
nected all peripherals
5. Be careful with power. Avoid accidental shocks, discharges or explosions. and cables (including
• Before removing or servicing any part from the computer, turn the computer off and detach any power supplies. telephone lines and
• When you want to unplug the power cord or any cable/wire, be sure to disconnect it by the plug head. Do not pull on the wire. power cord). It is advis-
6. Peripherals – Turn off and detach any peripherals. able to also remove
2.Disassembly
7. Beware of static discharge. ICs, such as the CPU and main support chips, are vulnerable to static electricity. Before han- your battery in order to
dling any part in the computer, discharge any static electricity inside the computer. When handling a printed circuit board, do prevent accidentally
not use gloves or other materials which allow static electricity buildup. We suggest that you use an anti-static wrist strap turning the machine
instead. on.
8. Beware of corrosion. As you perform your job, avoid touching any connector leads. Even the cleanest hands produce oils
which can attract corrosive elements.
9. Keep your work environment clean. Tobacco smoke, dust or other air-born particulate matter is often attracted to charged
surfaces, reducing performance.
10. Keep track of the components. When removing or replacing any part, be careful not to leave small parts, such as screws,
loose inside the computer.
Cleaning
Do not apply cleaner directly to the computer, use a soft clean cloth.
Do not use volatile (petroleum distillates) or abrasive cleaners on any part of the computer.
(For Computer Models Supplied with Light Blue Cleaning Cloth) Some computer models in this series come supplied with a
light blue cleaning cloth. To clean the computer case with this cloth follow the instructions below.
• Power off the computer and peripherals.
• Disconnect the AC/DC adapter from the computer.
• Use a little water to dampen the cloth slightly.
• Clean the computer case with the cloth.
• Dry the computer with a dry cloth, or allow it time to dry before turning on.
• Reconnect the AC/DC adapter and turn the computer on.
Overview 2 - 3
Disassembly
Disassembly Steps
The following table lists the disassembly steps, and on which page to find the related information. PLEASE PERFORM
THE DISASSEMBLY STEPS IN THE ORDER INDICATED.
2 - 4 Disassembly Steps
Disassembly
a. c.
1 2 3 4
2.Disassembly
12
10 5
11 13
9 8 7 6
b.
12. Bottom Case
• 11 Screws
9 8 7 6
18 17
Powering the
Computer On 20
e.
After every disassem-
bly, make sure that the
bottom case’s screws
are all inserted and
tightened before turn-
ing the computer on.
20
19
19. Battery
• 4 Screws
2.Disassembly
a. b. c.
Contact Warning
2 2 Be careful not to touch
1
the metal pins on the
4 module’s connecting
edge. Even the cleanest
hands have oils which
can attract particles, and
3 degrade the module’s
3 performance.
Single Memory Module Installation
4. RAM Module
If your computer has a single memory
module, then insert the module into the
Channel 0 (JDIMM1 / RAM1) socket.
2.Disassembly
cable to the “1 + 2”
socket (Figure 4b).
b.
5
4
2
3
5.Wireless LAN Module
• 1 Screw
Cable 1 is usually connected to antenna 1 (Main) on the module, and cable 2 to antenna 2 (Aux).
a. c.
2.Disassembly
1
3
b.
2
Thermal Pad
3.M2 SATA Module
Make sure to place the thermal pad’s adhesive side down on the
module’s surface as illustrated. Insert the module with the thermal
pad facing the mainboard. • 1 Screw
2 2
b.
5. LCD Front Cover
4 4
d.
6
2.Disassembly
7. CCD Module
2 - 14
Appendix A:Part Lists
This appendix breaks down the NL40CU / NL41CU series notebook’s construction into a series of illustrations. The
component part numbers are indicated in the tables opposite the drawings.
Note: This section indicates the manufacturer’s part numbers. Your organization may use a different system, so be sure
to cross-check any relevant documentation.
Note: Some assemblies may have parts in common (especially screws). However, the part lists DO NOT indicate the
total number of duplicated parts used.
Note: Be sure to check any update notices. The parts shown in these illustrations are appropriate for the system at the
A.Part Lists
time of publication. Over the product life, some parts may be improved or re-configured, resulting in new part numbers.
A - 1
Part List Illustration Location
The following table indicates where to find the appropriate part list illustration.
Table A - 1
Part List Illustration
Part
Location
Top page A - 3
Bottom page A - 4
LCD page A - 5
MB page A - 6
A.Part Lists
A - 2
Top
Figure A - 1
A.Part Lists
Top
Top A - 3
Bottom
Figure A - 2
A.Part Lists
Bottom
A - 4 Bottom
LCD
Figure A - 3
LCD
A.Part Lists
LCD A - 5
MB
Figure A - 4
A.Part Lists
MB
A - 6 MB
Schematic Diagrams
B.Schematic Diagrams
Processor 3/12 - Page B - 5 ASM1543 - Page B - 21 VCCIN, VCCGT, VCCSA - Page B - 37
Processor 4/12 - Page B - 6 LED KB, LED - Page B - 22 VCCIO, 2.5V - Page B - 38
Processor 5/12 - Page B - 7 SATA HDD, TPM - Page B - 23 Charger, AC IN - Page B - 39
Processor 6/12 - Page B - 8 Audio Codec - Page B - 24 RTL8411B - Page B - 40
Processor 7/12 - Page B - 9 KBC ITE IT5570 - Page B - 25 14” I/O Board - Page B - 41
Processor 8/12 - Page B - 10 WLAN - Page B - 26 15” I/O Board-1 - Page B - 42 Version Note
Processor 9/12 - Page B - 11 M Key PCIE SSD - Page B - 27 15” I/O Board-2 - Page B - 43 The schematic dia-
grams in this chapter
Processor 10/12 - Page B - 12 3G/LTE - Page B - 28 Power Button Board - Page B - 44
are based upon ver-
Processor 11/12 - Page B - 13 USB Type-A - Page B - 29 sion 6-7P-NL4C5-002.
If your mainboard (or
Processor 12/12 - Page B - 14 Conn, CCD, Fan, TP - Page B - 30
other boards) are a lat-
DDR4 SO-DIMM_0 - Page B - 15 3V, 5V, 3VS, 5VS, 1.8V, 1.5VS - Page B - 31 er version, please
check with the Service
DDR4 SO-DIMM_1 - Page B - 16 VDD3, VDD5 - Page B - 32
Center for updated di-
HDMI - Page B - 17 1.05VA, VCCST, VCCSTG - Page B - 33 agrams (if required).
B - 1
Schematic Diagrams
5 4 3 2 1
5 IN 1 6-7P-NL4C5-002
MAIN BOARD
SHEET 2~38 6-71-NL4C0-D02
NL40CU Comet LAKE U62 (HDCP2.2) System Block Diagram
LAN BOARD 1866/ 2133 MHz 5V,5VS,3.3VA,3.3V
6-71-NL4CZ-D02
SHEET 39
DDI2 DDR4 DDR4 3.3VS,1.8V,1.5VSSHEET 30
D
14" I/O BOARD 6-71-NL4C1-D02 HDMI SHEET 16
SYSTEM SMBUS SO-DIMM A D
SHEET 40 SHEET 14
ANX7440 DDI1 1866/ 2133 MHz VDD3,VDD5
15" I/O BOARD SHEET 31
6-71-NL5C1-D02 SHEET 18 DDR4
SHEET 41~42 DDR4
15" PWR BTN BOARD ANX7411
SYSTEM SMBUS SO-DIMM B 1.05VA/VCCST/VCCSTG
SHEET 43 6-71-NL5CS-D02 SHEET 19 SHEET 15 VCCSFR_OC SHEET 32
B.Schematic Diagrams
Type-C VDDQ,VDDQ_VTT,1.8VA
SHEET 19
Comet Lake
SHEET 33
eDP SHEET 17 PROCESSOR I/O BOARD
USB 2.0 TYPE A DC-JACK, PWR PD
SHEET 34
BIOS SPI rPGA1528 46x24mm USB2.0 port3
SENTELIC SHEET 5 SHEET 40,42 SHEET 43
VCORE MP2979A
Sheet 1 of 43 TOUCH PAD
SHEET 29
TPM
USB 2.0 TYPE A
SHEET 35
C C
ANX7440 ASM1543
7IN1
SHEET 18 SHEET 20 M.2 3G/LTE M.2 CNVI M.2 SSD SOCKET
USB 3.1 Gen2 TYPE A USB3.1 port4 PCIE10 PCIE13~16
HDD W/O DP SHEET 39 LAN BOARD
USB3.1 port1 USB 3.1 Gen2 TYPE C USB2.0 port4 SHEET 25 SATA 2
SATA 0 SHEET 27 SHEET 26
USB2.0 port1 ANX7411 Colay USB3.1 port2
SHEET 28 SHEET 19 USB2.0 port2
SHEET 22 SHEET 19
A
W/ DP A
SIM Socket
CCD+INT MIC SHEET 42
USB2.0 port7 15" I/O BOARD ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
RGBIR CMR Title
SHEET 29 [01] BLOCK DIAGRAM
Size Document Number Rev
A3 NL40CU 6-7P-NL4C5-002 D02
Processor 1/12
5 4 3 2 1
U1A
TYPE C+DP PORT 18 MDP_D#0
AL5
DDI1_TXN_0 EDP_TXN_0
AG4
EDP_TXN_0 17 eDP PANEL
AL6 AG3
18 MDP_D0 DDI1_TXP_0 EDP_TXP_0 EDP_TXP_0 17
D AJ5 AG2 D
18 MDP_D#1 DDI1_TXN_1 EDP_TXN_1 EDP_TXN_1 17
AJ6 AG1
18 MDP_D1 DDI1_TXP_1 EDP_TXP_1 EDP_TXP_1 17
DIFF=85ohm AF6 AJ4
18 MDP_D#2 DDI1_TXN_2 EDP_TXN_2 EDP_TXN_2 17
Length <6000 mils AF5 AJ3
18 MDP_D2 DDI1_TXP_2 EDP_TXP_2 EDP_TXP_2 17
AE5 AJ2
18 MDP_D#3 DDI1_TXN_3 EDP_TXN_3 EDP_TXN_3 17 DIFF=85ohm
AE6 AJ1
18 MDP_D3 DDI1_TXP_3 EDP_TXP_3 EDP_TXP_3 17
AC4
16 HDMI_DATA0N DDI2_TXN_0
HDMI PORT 16 HDMI_DATA0P
AC3
DDI2_TXP_0 EDP_AUX
AH4
EDP_AUXN 17
16 HDMI_DATA1N AC1 AH3
DDI2_TXN_1 EDP_AUX_P EDP_AUXP 17
16 HDMI_DATA1P AC2
AE4 DDI2_TXP_1 AM7 EDP_DISP_UTIL
16 HDMI_DATA2N DDI2_TXN_2 DISP_UTILS T13
DIFF=85ohm AE3
B.Schematic Diagrams
16 HDMI_DATA2P DDI2_TXP_2
16 HDMI_CLOCKN AE1 AC7
AE2 DDI2_TXN_3 DDI1_AUX AC6 MDP_AUX# 18
16 HDMI_CLOCKP DDI2_TXP_3 DDI1_AUX_P MDP_AUX 18
AD4 T54
DDI2_AUX AD3
DDI2_AUX_P T55
AG7 T10
DDI3_AUX AG6
DDI3_AUX_P T11
3.3VS
DIFF=85ohm
EDP_BKLTCTL
CH11
HDMI eDP
EDP_BRIGHTNESS 17 Analog Thermal Sensor
6-17-10400-730 EWTF02-104F4F-N
C
Sheet 2 of 43
W=5mil, SPACE=25mil , Max < 600mil
R218
R217
2.2K_04
2.2K_04
DPPB_CTRLCLK
DPPB_CTRLDATA
VCCIO
R61 24.9_1%_04 EDP_RCOMP
DPPB_CTRLCLK CC8
AM6
DISP_RCOMP
R180
*20K_04
R197
*100K_04
3.3V TH1
1 2
100k_1%_0402_NTC
EW TF02-104F4F-N
Processor 1/12
DPPB_CTRLDATA CC9 GPP_E18/DPPB_CTRLCLK/CNV_BT_HOST_WAKE# THERM_VOLT 24
Enable DP setting
GPP_E19/DPPB_CTRLDATA
1:2 (4mils:8mils)
HDMI_CTRLCLK CH4 R440
R405 2.2K_04 HDMI_CTRLCLK 16 HDMI_CTRLCLK GPP_E20/DPPC_CTRLCLK
HDMI_CTRLDATA CH3
R404 2.2K_04 HDMI_CTRLDATA 16 HDMI_CTRLDATA GPP_E21/DPPC_CTRLDATA 20K_1%_04
㓦 伖 ⎴朊
Intel XDP Debug JTAG Pins
B XDP_TDI B
XDP_TDO T48 PCB Footprint = TC20-50
XDP_TMS T8 PCB Footprint = TC20-50
T52 U1D
XDP_TRST# T6 PCB Footprint = TC20-50
XDP_TCLK T9 PCB Footprint = TC20-50
H_CATERR# XDP_TCLK PCH_JTAG_TCK T45 PCB Footprint = TC20-50
VCCST R38 49.9_1%_04 AA4 T6
H_PECI_ISO CATERR# PROC_TCK XDP_TDI XDP_PREQ# T49 PCB Footprint = TC20-50
VCCSTG R388 *0402_short AR1 U6
24 H_PECI H_PROCHOT# R367 H_PROCHOT#_D PECI PROC_TDI XDP_TDO XDP_PRDY# T53 PCB Footprint = TC20-50
499_1%_04 Y4 Y5
THRMTRIP_R_N PROCHOT# PROC_TDO XDP_TMS T7 PCB Footprint = TC20-50
VCCST R83 1K_04 BJ1 T5
THRMTRIP# PROC_TMS AB6 XDP_TRST#
R365 U1 PROC_TRST#
U2 BPM#_0 W6 PCH_JTAG_TCK R355 *51_04
1K_04 U3 BPM#_1 PCH_TCK U5 XDP_TDI
Form power LENGTH <500MILS U4 BPM#_2 PCH_TDI W5 XDP_TDO
BPM#_3 PCH_TDO P5 XDP_TMS PU/PD for JTAG signals
H_PROCHOT# PCH_TMS
35 H_PROCHOT# Y6 XDP_TRST#
PCH_TRST# P6 XDP_TCLK XDP_TCLK R347 51_04
C376 PCH_JTAGX
D
6,9,17,18,19,20,22,26,27,29,30,33,35,36,37 3.3V
5,6,7,8,9,14,15,16,17,21,23,24,26,29,30,35,37 3.3VS
10,11,32 VCCSTG
4,11,37 VCCIO
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Title
9,10,11,32,35 VCCST
[02] CML A,D/20 DDI,MISC,JAG
Size Document Number Rev
A3 NL40CU 6-71-NL4C0-D02 D02
Date: Friday, August 16, 2019 Sheet 2 of 44
5 4 3 2 1
Processor 1/12 B - 3
Schematic Diagrams
Processor 2/12
5 4 3 2 1
14 M_A_DQ[63:0]
U1B 15 M_B_DQ[63:0]
LP3 / DDR4 U1C
DDR4 (IL) / LP3 - DDR4 (NIL) V32
M_A_DQ0 DDR0_CKN_0/DDR0_CKN_0 M_A_CLK_DDR#0 14 LP3 / DDR4 AF28
A26 V31 M_B_DQ0 DDR4 (IL) / LP3 - DDR4 (NIL) DDR1_CKN_0/DDR1_CKN_0 M_B_CLK_DDR#0 15
M_A_DQ1 DDR0_DQ_0/DDR0_DQ_0 DDR0_CKP_0/DDR0_CKP_0 M_A_CLK_DDR0 14 J22 AF29
D26 T32 M_B_DQ1 DDR1_DQ_0/DDR0_DQ_16 DDR1_CKP_0/DDR1_CKP_0 M_B_CLK_DDR0 15
M_A_DQ2 DDR0_DQ_1/DDR0_DQ_1 DDR0_CKN_1/DDR0_CKN_1 M_A_CLK_DDR#1 14 H25 AE28
D28 T31 M_B_DQ2 DDR1_DQ_1/DDR0_DQ_17 DDR1_CKN_1/DDR1_CKN_1 M_B_CLK_DDR#1 15
M_A_DQ3 DDR0_DQ_2/DDR0_DQ_2 DDR0_CKP_1/DDR0_CKP_1 M_A_CLK_DDR1 14 G22 AE29
C28 M_B_DQ3 DDR1_DQ_2/DDR0_DQ_18 DDR1_CKP_1/DDR1_CKP_1 M_B_CLK_DDR1 15
M_A_DQ4 DDR0_DQ_3/DDR0_DQ_3 LP3 / DDR4 H22
B26 U36 M_A_CKE0 14 M_B_DQ4 DDR1_DQ_3/DDR0_DQ_19 LP3 / DDR4
M_A_DQ5 DDR0_DQ_4/DDR0_DQ_4 DDR0_CKE_0/DDR0_CKE_0 F25 T28 M_B_CKE0 15
C26 U37 M_A_CKE1 14 M_B_DQ5 DDR1_DQ_4/DDR0_DQ_20 DDR1_CKE_0/DDR1_CKE_0
M_A_DQ6 DDR0_DQ_5/DDR0_DQ_5 DDR0_CKE_1/DDR0_CKE_1 J25 T29 M_B_CKE1 15
B28 U34 M_B_DQ6 DDR1_DQ_5/DDR0_DQ_21 DDR1_CKE_1/DDR1_CKE_1
M_A_DQ7 DDR0_DQ_6/DDR0_DQ_6 DDR0_CKE_2/NC G25 V28
B.Schematic Diagrams
Sheet 3 of 43 M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
H37
H34
K34
K35
DDR0_DQ_16/DDR0_DQ_32
DDR0_DQ_17/DDR0_DQ_33
DDR0_DQ_18/DDR0_DQ_34
DDR0_CAB_5/DDR0_MA_2
NC/DDR0_MA_3
NC/DDR0_MA_4
AC34
AC35
AA35
AB35
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_B_DQ16
M_B_DQ17
M_B_DQ18
G31
G32
H29
DDR1_DQ_15/DDR0_DQ_31
DDR1_DQ_16/DDR0_DQ_48
DDR1_DQ_17/DDR0_DQ_49
DDR1_CAB_8/DDR1_MA_1
DDR1_CAB_5/DDR1_MA_2
NC/DDR1_MA_3
AF34
AG37
AE35
M_B_A2
M_B_A3
M_B_A4
M_B_DQ19 H28 DDR1_DQ_18/DDR0_DQ_50 NC/DDR1_MA_4 AF35 M_B_A5
R107
R105
R106
3 of 20
CML_U_IP_CCG
CML_U_IP_CCG 2 OF 20
100_1%_04
80.6_1%_04
121_1%_04
A A
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Title
[03] CML U B,C/20 DDR4 interleave
Size Document Number Rev
A3 NL40CU 6-71-NL4C0-D02 D02
Date: Friday, August 16, 2019 Sheet 3 of 44
5 4 3 2 1
B - 4 Processor 2/12
Schematic Diagrams
Processor 3/12
5 4 3 2 1
U1Q
CFG0 T4 F37
CFG_0 RSVD_TP_1 F34
R4 RSVD_TP_2
CFG_1 CP36
1K_04 R358
T51
CFG3
CFG4
T3
R3
J4
CFG_2
CFG_3
CFG_4
IST_TRIG
RSVD_TP_3
CN36
Comet Lake U Q/20 CFG
*1K_04 R361 CFG5 M4 BJ36
*1K_04 R357 CFG6 J3 CFG_5 RSVD_5 BJ34
CFG7 M3 CFG_6 RSVD_6
D
T50 R2 CFG_7
CFG_8 TP_3
BK34 Ʉ CFG[0]: Stall reset sequence after PCU PLL D
N2 BR18
VCCIO R1 CFG_9 TP_4 lock until de-asserted:
CFG_10
N1
J2 CFG_11 — 1 = (Default) Normal Operation; No
L2 CFG_12
CFG_13 RSVD_16
BT9 stall.
R48 J1 BT8 — 0 = Stall.
*150_04 L1 CFG_14 RSVD_17
CFG_15
RSVD_18
BP8 Ʉ CFG[1]: Reserved configuration lane.
L3 BP9
N3 CFG_16 RSVD_19 Ʉ CFG[2]: PCI Express* Static x16 Lane
*1K_04 R43 CFG0 CFG_18
L4 RSVD_26
CR4 Numbering Reversal.
CFG_17
N4
CFG_19 — 1 = Normal operation
CFG_RCOMP AB5 — 0 = Lane numbers reversed.
B.Schematic Diagrams
R44 49.9_1%_04 CP3
CFG_RCOMP RSVD_27
RSVD_28
CR3 Ʉ CFG[3]: Reserved configuration lane.
R366 1.5K_04 W4
1.05VA ITP_PMODE Ʉ CFG[4]: eDP enable:
CG2
RSVD_20 — 1 = Disabled.
CG1
RSVD_21 — 0 = Enabled.
Ʉ CFG[6:5]: PCI Express* Bifurcation
RSVD_30
AT3 — 00 = 1 x8, 2 x4 PCI Express*
H4 AU3
H3 RSVD_22 RSVD_1 — 01 = reserved
RSVD_23
— 10 = 2 x8 PCI Express*
C
BV24
BV25 RSVD_24
RSVD_25 RSVD_3
AN1
AN2
— 11 = 1 x16 PCI Express*
Ʉ CFG[7]: PEG Training:
C Sheet 4 of 43
RSVD_4
RSVD_14
RSVD_15
AN4
AN3
— 1 = (default) PEG Train immediately
following RESET# de assertion.
Processor 3/12
RSVD_8
AL2 — 0 = PEG Wait for BIOS for training.
AL1
RSVD_9 Ʉ CFG[19:8]: Reserved configuration lanes.
AL4
BK36 RSVD_10 AL3
BK35 RSVD_31 RSVD_11
RSVD_29
W3
AM4 RSVD_12
TP_2
VSS_1
BP34
BP36
BP35
According to CML-U DCL
AM3
RSVD_13 TP_1
611481-qs-cml-qsbf-qsbg-qsbj-dcl-ww17-2019.pdf
RSVD_7
CR35
RSVD_2 T63
SKTOCC# R356 10K_04 3.3VA
E1
SKTOCC#
B B
20 of 20
CML_U_IP_CCG
2,11,37 VCCIO
5,6,7,8,9,12,22,23,30,33 3.3VA
12,32 1.05VA
A A
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Title
[04] CML U D,Q/20 CFG
Size Document Number Rev
A3 NL40CU 6-71-NL4C0-D02 D02
Date: Friday, August 16, 2019 Sheet 4 of 44
5 4 3 2 1
Processor 3/12 B - 5
Schematic Diagrams
Processor 4/12
5 4 3 2 1
D U1E D
Sheet 5 of 43 MB_DET
25
25
25
CL_CLK
CL_DATA1
CL_RST#1
CH7
CH8
CH9
CL_CLK
CL_DATA
CL_RST#
GPP_A14/SUS_STAT#/ESPI_RESET#
GPP_A9/CLKOUT_LPC0/ESPI_CLK
CA27
BV32
BV30
PCLK_KBC_R R231 22_04 PCLK_KBC 24
HIGH = 14" GPP_A10/CLKOUT_LPC1
Processor 4/12 GPP_D2 R171 *10K_04 D02 unstuff BY30 PM_CLKRUN# R214 8.2K_04
3.3VS GPP_A8/CLKRUN# 3.3VS
BV29 C263
24 SB_KBCRST# GPP_A0/RCIN#/TIME_SYNC1
3.3VS R170 *10K_04 SERIRQ BV28 *27p_25V_NPO_02
LOW = 15" GPP_A6/SERIRQ
PM_CLKRUN# 24
C 5 of 20 C
24 SERIRQ CML_U_IP_CCG
3.3VS R429 10K_04 FOR 14"
R428 10K_04 FOR 15" MB_DET
U33
W/O TPM
8 5 SPI_SI R505 49.9_1%_04 SPI_SI_R R500 0_04 W /O_TPM
VDD SI EC_SPI_SI 24
B R496 2 SPI_SO R495 49.9_1%_04 SPI_SO_R R493 0_04 W /O_TPM B
SO EC_SPI_SO 24
1K_1%_04
SPI_W P#_0 3 1 SPI_CS0# R486 0_04 SPI_CS_0# R485 0_04 W /O_TPM
WP# CE# EC_SPI_CS0# 24
R488 6 SPI_SCLK R498 49.9_1%_04 SPI_SCLK_R R491 0_04 W /O_TPM
SCK EC_SPI_SCLK 24
1K_1%_04
SPI_HOLD#_07 4
HOLD# VSS
GD25B127DSIGR Close to BIOS ROM
PCB Footprint = M-SOP8B
128M-bit/16M-byte
GD 6-04-25127-470 GD25B127DSIGR
MXIC 6-04-25128-A77 MX25L12872FM2I-10G
XMC 6-04-25128-A78 XM25QH128A
H15 H14 H5 H4
*C111D111N *C111D111N *C111D111N *C111D111N
CPU NUT, BOT M.2 SSD NUT, BOT C111D111N C111D111N C111D111N C111D111N
H_CPU1 H_CPU2 H_CPU3 H_SSD1
6-34-W 54CS-010 6-34-W 54CS-010 6-34-W 54CS-010 6-34-L140S-010
H1 H2 H11 H13
H7_0B6_0D3_7 H7_0B6_0D3_7 H7_0B6_0D3_7 H7_0B6_0D3_7
2 4 2 4 2 4 2 4
M7 M4 M5 M1
3 1 5 3 1 5 3 1 5 3 1 5 *M-MARK *M-MARK *M-MARK *M-MARK
B - 6 Processor 4/12
Schematic Diagrams
Processor 5/12
5 4 3 2 1
B.Schematic Diagrams
VDD3 25 CNVI_BRI_RSP GPP_F5/CNV_BRI_RSP GPP_H10/I2C5_SDA/ISH_I2C2_SDA
For BIOS Debug 25 CNVI_RGI_DT CG19 CJ29
CJ20 GPP_F6/CNV_RGI_DT GPP_H11/I2C5_SCL/ISH_I2C2_SCL
25 CNVI_BRI_DT GPP_F4/CNV_BRI_DT
CH19 CM24
25 CNVI_RGI_RSP GPP_F7/CNV_RGI_RSP GPP_D13/ISH_UART0_RXD
R413 *10K_04 UART2_RXD R426 *0_06 CN23
R414 *10K_04 UART2_TXD GPP_D14/ISH_UART0_TXD CM23
UART2_RXD CR12 GPP_D15/ISH_UART0_RTS#/GSPI2_CS1# CR24
UART2_TXD GPP_C20/UART2_RXD GPP_D16/ISH_UART0_CTS#/SML0BALERT#
㓦伖 B OT 朊 ㉮味⎗㉱䶂⛘ 㕡 CP12
CN12 GPP_C21/UART2_TXD CG12 GPP_C12_RTD3 26
R415 0_04 CM12 GPP_C22/UART2_RTS# GPP_C12/UART1_RXD/ISH_UART1_RXD CH12
29 TP_ATTN# GPP_C23/UART2_CTS# GPP_C13/UART1_TXD/ISH_UART1_TXD SSD1_PW R_DN# 26
CF12
CM11 GPP_C14/UART1_RTS#/ISH_UART1_RTS# CG14
I2C Address: 0x2C 29 I2C_SDA_TP GPP_C16/I2C0_SDA GPP_C15/UART1_CTS#/ISH_UART1_CTS# SATA_PW R_EN FROM PCH R155
29 I2C_SCL_TP CN11 *1K_04 3.3VS
GPP_C17/I2C0_SCL
19
19
I2C1_SDA
I2C1_SCL
I2C1_SDA
I2C1_SCL
CK12
CJ12 GPP_C18/I2C1_SDA
GPP_C19/I2C1_SCL
GPP_A18/ISH_GP0
GPP_A19/ISH_GP1
GPP_A20/ISH_GP2
BW35
BW34
CA37
CA36
T61
R154 *0_04
SATA_PW R_EN FROM PCH
ANX7411_TEST_R 19
22 Sheet 6 of 43
GPP_A21/ISH_GP3 ASM1543_I_SEL0 20
C
3.3V R530
R531
2.2K_04
2.2K_04
D02 add
T35
T27
CF27
CF29
CH27
GPP_H4/I2C2_SDA
GPP_H5/I2C2_SCL
GPP_A22/ISH_GP4
GPP_A23/ISH_GP5
GPP_A12/ISH_GP6/BM_BUSY#/SX_EXIT_HOLDOFF#
CA35
CA34
BW37
R152
PCH_GPP_A12
*0_04
R151 *10K_04
ASM1543_I_SEL1 20
3.3VA
C Processor 5/12
T28 GPP_H6/I2C3_SDA
T26 CH28
GPP_H7/I2C3_SCL
STRAP PIN CJ30
CJ31 GPP_H8/I2C4_SDA
Flash Descriptor Security Overide GPP_H9/I2C4_SCL
Low = Enable security measures defined in the Flash Descriptor.
(Default)
High = Disable Flash Descriptor Security (override) CML_U_IP_CCG 6 of 20
D15 RB751S-40C2
24 ME_W E R135 1K_04 A C
20190708
HDA_SDO/HDA_SYNNC/HDA_BCLK/HDA_RST#
CAP should be close PCH
Trace Length <1"
U1G
R243 33_04 HDA_SYNC#L BN34
C272 23 HDA_SYNC HDA_BITCLK#L HDA_SYNC/I2S0_SFRM
R242 33_04 BN37
23 HDA_BITCLK HDA_SDOUT#L HDA_BCLK/I2S0_SCLK
R394 33_04 BN36 CH36
*22p_25V_NPO_02 23 HDA_SDOUT HDA_SDO/I2S0_TXD GPP_G0/SD_CMD
BN35 CL35
20190605 EMI 23 HDA_SDIN0 HDA_SDI0/I2S0_RXD GPP_G1/SD_DATA0
BL36 CL36
R395 33_04 HDA_RST#1 BL35 HDA_SDI1/I2S1_RXD/SNDW1_DATA GPP_G2/SD_DATA1 CM35
B 23 AZ_RST#_R HDA_RST#/I2S1_SCLK/SNDW1_CLK GPP_G3/SD_DATA2 B
C390 T29 CK23 CN35
*2p_25V_NPO_02 GPP_D23/I2S_MCLK GPP_G4/SD_DATA3 CH35 BOARD_ID
BL37 GPP_G5/SD_CD# CK36
BL34 I2S1_SFRM/SNDW2_CLK GPP_G6/SD_CLK CK34
I2S1_TXD/SNDW2_DATA GPP_G7/SD_WP 20190708 Modify
3.3VS
CJ32
25 CNVI_RST# GPP_H1/I2S2_SFRM/CNV_BT_I2S_BCLK/CNV_RF_RESET#
CH32 R157 10K_04 FOR CML
CH29 GPP_H0/I2S2_SCLK/CNV_BT_I2S_SCLK
25 CNVI_CLKREQ GPP_H2/I2S2_TXD/CNV_BT_I2S_SDI/MODEM_CLKREQ BOARD_ID
CH30 R160 10K_04 FOR WHL
GPP_H3/I2S2_RXD/CNV_BT_I2S_SDO BW36
GPP_A17/SD_VDD1_PWR_EN#/ISH_GP7 T59
T72 CP24 BY31
CN24 GPP_D19/DMIC_CLK0/SNDW4_CLK GPP_A16/SD_1P8_SEL
T69 GPP_D20/DMIC_DATA0/SNDW4_DATA CK33 SD_RCOMP BOARD ID
CK25 SD_1P8_RCOMP CM34 R172 200_1%_04
CJ25 GPP_D17/DMIC_CLK1/SNDW3_CLK SD_3P3_RCOMP
GPP_D18/DMIC_DATA1/SNDW3_DATA
HIGH = CML-U
GPP_G5
R244 *0402_short PCH_HDA_SPKR CF35
23 PCH_SPKR GPP_B14/SPKR
LOW = WHL-U
7 of 20
CML_U_IP_CCG
STRAP PIN
Top Swap Override
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Title
[06] CML U F,G/20 GPIO/HDA
5,8,9,12,21,22,23,24,25,26,29,30,31,32,33,35,37,38 VDD3 Size Document Number Rev
2,5,7,8,9,14,15,16,17,21,23,24,26,29,30,35,37
4,5,7,8,9,12,22,23,30,33
3.3VS
3.3VA A3 NL40CU 6-71-NL4C0-D02 D02
2,9,17,18,19,20,22,26,27,29,30,33,35,36,37 3.3V Date: Friday, August 16, 2019 Sheet 6 of 44
5 4 3 2 1
Processor 5/12 B - 7
Schematic Diagrams
Processor 6/12
5 4 3 2 1
BU1 BY3
PCIE7_TXP PCIE3_TXP/USB31_3_TXP USB3_3TXP 29
BU9 BW6
PCIE8_RXN PCIE4_RXN/USB31_4_RXN USB3_4RXN 27
BU8 BW5
PCIE8_RXP PCIE4_RXP/USB31_4_RXP USB3_4RXP 27
BT4 BW2 3G/LTE
PCIE8_TXN PCIE4_TXN/USB31_4_TXN USB3_4TXN 27
BT3 BW1
PCIE8_TXP PCIE4_TXP/USB31_4_TXP USB3_4TXP 27
BP5 CE3 USB_PN1 28 M/B USB port1 (2.0+3.1)
29 PCIE_RXN9_GLAN PCIE9_RXN USB2N_1
BP6 CE4
29 PCIE_RXP9_GLAN PCIE9_RXP USB2P_1 USB_PP1 28 USB3.1 GEN2 Type-A
Sheet 7 of 43 LAN 29
29
PCIE_TXN9_GLAN
PCIE_TXP9_GLAN
C392
C391
0.1u_10V_X5R_04
0.1u_10V_X5R_04
PCIE9_TXN
PCIE9_TXP
BR2
BR1
BN6
PCIE9_TXN
PCIE9_TXP USB2N_2
USB2P_2
CE1
CE2
USB_PN2
USB_PP2
19
19
M/B USB port2 (2.0+3.1)
USB3.1 Colay Type C
25 PCIE_RXN10_W LAN
CML_U_IP_CCG
8 of 20
A A
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
5,6,8,9,12,21,22,23,24,25,26,29,30,31,32,33,35,37,38 VDD3 Title
2,5,6,8,9,14,15,16,17,21,23,24,26,29,30,35,37
4,5,6,8,9,12,22,23,30,33
3.3VS
3.3VA
[07] CML U H/20 PCIE/SATA
Size Document Number Rev
A3 NL40CU 6-71-NL4C0-D02 D02
Date: Friday, August 16, 2019 Sheet 7 of 44
5 4 3 2 1
B - 8 Processor 6/12
Schematic Diagrams
Processor 7/12
5 4 3 2 1
CNVi U1I
Comet Lake U I,J/20 CNVI/CLK 3.3VS
CR30
25 CNVI_W R_D0N CP30 CNV_WR_D0N CN27 CPU_C10_GATE# CPU_C10_GATE# R418 *100K_04
25 CNVI_W R_D0P CNV_WR_D0P GPP_H18/CPU_C10_GATE# CPU_C10_GATE# 24,32,37 D02 unstuff
CM30 CM27
25 CNVI_W R_D1N CN30 CNV_WR_D1N GPP_H19/TIMESYNC_0 3.3VA
25 CNVI_W R_D1P CNV_WR_D1P CF25 GPPC_H21
CN32 GPP_H21/XTAL_FREQ_SELECT CN26 GPPC_H21 R156 4.7K_04
25 CNVI_W T_D0N CNV_WT_D0N GPP_H22
CM32 CM26
25 CNVI_W T_D0P CNV_WT_D0P GPP_H23 CK17 R137 *20K_04
CP33 GPP_F10
D 25 CNVI_W T_D1N D
CN33 CNV_WT_D1N LOW:38.4/19.2M
25 CNVI_W T_D1P CNV_WT_D1P HI:24M
BV35 GPD_7 R109 100K_04
GPD7 VDD3
CN31 CN20
25 CNVI_W R_CLKN CP31 CNV_WR_CLKN GPP_F3
25 CNVI_W R_CLKP CNV_WR_CLKP CG25
CP34 GPP_D4/IMGCLKOUT0/BK4/SBK4 CH25
25 CNVI_W T_CLKN CNV_WT_CLKN GPP_H20/IMGCLKOUT1
25 CNVI_W T_CLKP CN34
CNV_WT_CLKP CR20
R173 150_1%_04 CNVI_W T_RCOMP CP32 GPP_F12/EMMC_DATA0 CM20
CR32 CNV_WT_RCOMP_1 GPP_F13/EMMC_DATA1 CN19
CP20 CNV_WT_RCOMP_2 GPP_F14/EMMC_DATA2 CM19
25 CNVI_GNSS_PA_BLANKING GPP_F0/CNV_PA_BLANKING GPP_F15/EMMC_DATA3
CK19 CN18
CG17 GPP_F1 GPP_F16/EMMC_DATA4 CR18
GPP_F2 GPP_F17/EMMC_DATA5 CP18
CR14 GPP_F18/EMMC_DATA6 CM18
CP14 GPP_C8/UART0_RXD GPP_F19/EMMC_DATA7
CN14 GPP_C9/UART0_TXD CM16
GPP_C10/UART0_RTS# GPP_F20/EMMC_RCLK
B.Schematic Diagrams
CM14 CP16
GPP_C11/UART0_CTS# GPP_F21/EMMC_CLK CR16
CJ17 GPP_F11/EMMC_CMD CN16
25 CNVI_MFUART2_RXD GPP_F8/CNV_MFUART2_RXD GPP_F22/EMMC_RESET#
CH17 D02 change footprint and value
25 CNVI_MFUART2_TXD GPP_F9/CNV_MFUART2_TXD CK15 EMMC_RCOMP R175 200_1%_04 PDA bug
R163 100K_04 A4W P_PRESENT CF17 EMMC_RCOMP C403 12p_50V_NPO_04
GPP_F23/A4WP_PRESENT
CML_U_IP_CCG 9 of 20
X3 Sheet 8 of 43
2
C U1J R410 19001-X-015-3 D02 Main vs 2nd change C
CLKOUT_ITPXDP_N
Processor 7/12
AW2 AU1 T56 6-22-24R00-1BB
CLKOUT_PCIE_N0 CLKOUT_ITPXDP CLKOUT_ITPXDP_P
1
AY3 AU2 T57 200K_1%_04 Use a shielded crystal GND and
CF32 CLKOUT_PCIE_P0 CLKOUT_ITPXDP_P isolation external GND
GPP_B5/SRCCLKREQ0# BT32 SUSCLK_R R189 0_04
GPD8/SUSCLK SUS_CLK 25
BC1 D02 change footprint and value
BC2 CLKOUT_PCIE_N1 CK3 XTAL24_IN
CLKOUT_PCIE_P1 XTAL_IN PDA bug
SRCCLKREQ1# CE32 CK2 XTAL24_OUT C404 12p_50V_NPO_04
GPP_B6/SRCCLKREQ1# XTAL_OUT
BD3 CJ1 XCLK_BIASREF R408 60.4_1%_04 CRB
25 CLK_PCIE_W LAN# CLKOUT_PCIE_N2 XCLK_BIASREF
BC3 CM3 L4 FCM1005KF-121T03
25 CLK_PCIE_W LAN W LAN_CLKREQ2# CLKOUT_PCIE_P2 CLKIN_XTAL CLKIN_XTAL_LCP 25
CF30 R411 10K_04 FOR WHL
25 W LAN_CLKREQ2# GPP_B7/SRCCLKREQ2# RTC_X1
BN31
RTCX1 RTC_X2 C201 FOR WHL
BH3 BN32
29 CLK_PCIE_GLAN# CLKOUT_PCIE_N3 RTCX2 5p_50V_NPO_04
BH4
29 CLK_PCIE_GLAN LAN_CLKREQ3# CLKOUT_PCIE_P3
CE31 BR37 SRTCRST# C180 18p_25V_NPO_02 20190627 Add for WHL
29 LAN_CLKREQ3# GPP_B8/SRCCLKREQ3# SRTCRST# BR34 RTCRST# CML-U:NC
RTCRST#
1
BA1 WHL-U:stuff
BA2 CLKOUT_PCIE_N4 R136 X1
SRCCLKREQ4# CE30 CLKOUT_PCIE_P4 10M_06 XTL721-S999-328
32.768KHz
GPP_B9/SRCCLKREQ4# 6-22-32R76-0BM
2
BE1
26 CLK_PCIE_SSD1# CLKOUT_PCIE_N5
BE2 C179 18p_25V_NPO_02
26 CLK_PCIE_SSD1 SSD1_CLKREQ5# CLKOUT_PCIE_P5
CF31
26 SSD1_CLKREQ5# GPP_B10/SRCCLKREQ5#
CML_U_IP_CCG 10 of 20
B B
VCC_RTC VDD3
Processor Pullups/Pull downs
3.3VS
C189 0.1u_6.3V_X5R_02
ijıŮŪŭŴ R533
R169 10K_04 SRCCLKREQ1# 0_04
R188 330K_04 D02 add
R159 10K_04 W LAN_CLKREQ2# 9 SM_INTRUDER_N
LAN_CLKREQ3#
R139 10K_04 A 1 ijıŮŪŭŴ R534 *45.3K_1%_04 D02 EMI add J_RTC1
SRTCRST# R168 20K_1%_04 3 C
R140 10K_04 SRCCLKREQ4# R186 EMR3 0_04
A 2 RTC_VBAT_1 RTC_VBAT_CON_A
2
R158 10K_04 SSD1_CLKREQ5# C190 ijıŮŪŭŴ 1K_04 1
1u_6.3V_X5R_02 D21
BAT54CW G
WLAN_CLKREQ# PU 10K_04 IN PCH SIDE 50271-0020N-001
D02 Main vs 2nd change P/N = 6-20-43130-102
PCB Footprint = 85204-02L 20190618 swap pin1
RTCRST# R187 20K_1%_04
C196
BOTTOM
1
RTC CLEAR
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Title
[08] CML U I,J/20 CNVI/CLK
Size Document Number Rev
A3 NL40CU 6-71-NL4C0-D02 D02
Date: Monday, August 19, 2019 Sheet 8 of 44
5 4 3 2 1
Processor 7/12 B - 9
Schematic Diagrams
Processor 8/12
5 4 3 2 1
VCCST
3.3V
R253
1K_04
Comet Lake U K/20 POWER CONTROL
H_VCCST_PW RGD
R252
D 1M_04 D
6
D Q16A
MTDK3S6R
2 G D02 modify U1K
SLP_S0# 24,35
Q16B S
1
24 RSMRST#
3
MTDK3S6R D PLT_RST# BJ35 BJ37 SLP_S0# R392 *100K_04
D02 modify SYS_RESET# CN10 GPP_B13/PLTRST# GPP_B12/SLP_S0# BU36 SUSB#_PCH
ALL_SYS_PW RGD 5 G SYS_RESET# GPD4/SLP_S3# SUSC#_PCH SUSB#_PCH 24
C273 D02 stuff RSMRST# BR36 BU27
RSMRST# GPD5/SLP_S4# SLP_S5# SUSC#_PCH 24
S *0.01u_50V_X7R_04 PDA bug BT29 T21
4
R387 1K_04 PROCPW RGD AR2 GPD10/SLP_S5#
D02 unstuff R391 60.4_1%_04 VCCST_PW RGD BJ2 PROCPWRGD BU29 SLP_SUS#_R R153 *0_04
VCCST_PWRGOOD SLP_SUS# SLP_LAN# SLP_SUS# 24
PDA bug BT31
B.Schematic Diagrams
SLP_LAN# T20
PCH_PW ROK_EC R425 *0402_short SYS_PW ROK CR10 BT30 SLP_W LAN#
24 PCH_PW ROK_EC SYS_PWROK GPD9/SPL_WLAN# T17
PCH_PW ROK BP31 BU37 SLP_A#
PCH_PWROK GPD6/SLP_A# T58
RSMRST# R103 0_04 PCH_DPW ROK BP30
R101 *0_04 DSW_PWROK BU28 PW R_BTN# PW R_BTN# R110 *100K_04
24 EC_PCH_DPW ROK GPD3/PWRBTN# PW R_BTN# 24 VDD3
R119 0_04 SUSW ARN#_R BV34 BU35 AC_PRESENT AC_PRESENT R397 100K_04
24 SUSW ARN# SUSW ARN#_R SUS_PW R_ACK_RBY32 GPP_A13/SUSWARN#/SUSPWRDACK GPD1/ACPRESENT PM_BATLOW # AC_PRESENT 24,38 PM_BATLOW #
R398 0_04 BV36 R399 8.2K_04
GPP_A15/SUSACK# GPD0/BATLOW#
PCIE_W AKE# BU30
29 PCIE_W AKE# PCIE_SSD_WAKEUP# WAKE#
BU32 BR35
Sheet 9 of 43 26 PCIE_SSD_WAKEUP#
BU34 GPD2/LAN_WAKE#
GPD11/LANPHYPC
INTRUDER#
GPP_B11/EXT_PWR_GATE#
CC37
CC36
EXT_PW R_GATE#
SM_INTRUDER_N
CNVI_W AKE# 25
8
GPP_B2/VRALERT#
3V SELECT STRAP
R111 4.7K_04
14
14
9 TO VR_ON & EC
37 VCCIO_PW RGD ALL_SYS_PW RGD
4 8
PCH_PW ROK_EC 9,17,28,30,32 SUSB# ALL_SYS_PW RGD 17,24,35
C411 0.1u_6.3V_X5R_02 6 10
R439 *100K_04 SYS_PW ROK 5 EC Sequence:
PCH_PW ROK 32,33 VDDQ_PW RGD
R90 10K_04 U31C ALL_SYS_PWRGD → delay 100ms = PM_PWROK
7
R102 100K_04 PCH_DPW ROK U31B 74LVC08APW PM_PWROK → delay 5ms = PCH_PWROK_EC
7
R104 10K_04 RSMRST# 74LVC08APW VCCIO_EN 37
14
R125 10K_04 PCIE_W AKE#
VDD3
14
PCIE_SSD_WAKEUP# 1 PLT_RST# to Buffer
R124 *10K_04
35 H_VR_READY 12 3
PCH_PW ROK PLT_RST# BUF_PLT_RST# 22,24,25,26,29
11 2
B 13 B
24 PM_PW ROK
7
U31D R454
7
74LVC08APW 61.9K_1%_04
EC U8
VDD3
5
U74AHC1G08G-AL5-R
1
24 EC_EN
4
SUSC#_PCH SUSC# 32,33,37
2
3
VDD3
U7
5
U74AHC1G08G-AL5-R
1
4
SUSB#_PCH 2 SUSB# 9,17,28,30,32
3
A A
2,6,17,18,19,20,22,26,27,29,30,33,35,36,37 3.3V
5,6,8,12,21,22,23,24,25,26,29,30,31,32,33,35,37,38
2,5,6,7,8,14,15,16,17,21,23,24,26,29,30,35,37
VDD3
3.3VS ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
4,5,6,7,8,12,22,23,30,33 3.3VA Title
2,10,11,32,35 VCCST
[09] CML U K POWER CONTROL
Size Document Number Rev
A3 NL40CU 6-71-NL4C0-D02 D02
Date: Friday, August 16, 2019 Sheet 9 of 44
5 4 3 2 1
B - 10 Processor 8/12
Schematic Diagrams
Processor 9/12
5 4 3 2 1
VCC_CORE
U1L
VCORE SVID 70A
PLACE IN CPU BACK SIDE
VCC_CORE
Comet Lake U L,M/20 VCC,VCCGT
AN9 AW24
AN10 VCCCORE_28 VCCCORE_67 AW25 VCCGT
AN24 VCCCORE_29 VCCCORE_68 AW26 C370
VCCCORE_30 VCCCORE_69 C104 C126 C115 C114 VCCGT SVID 31A VCCGT
AN26 AW27 + U1M
AN27 VCCCORE_31 VCCCORE_70 AY24
VCCCORE_32 VCCCORE_71 PLACE IN CPU BACK SIDE
PSLB30E227M
PCB Footprint = M-B3528
22u_6.3V_X5R_06
22u_6.3V_X5R_06
22u_6.3V_X5R_06
22u_6.3V_X5R_06
AP2 AY26 A5 H12
AP9 VCCCORE_33 VCCCORE_72 BA5 A6 VCCGT_1 VCCGT_60 H14
VCCCORE_34 VCCCORE_73 VCCGT_2 VCCGT_61 C9 C18 C12 C6 C42 C31 C30
AP24 BA7 A8 H15 + C345
AP26 VCCCORE_35 VCCCORE_74 BA8 A11 VCCGT_3 VCCGT_62 H17
*PSLB30E227M
22u_6.3V_X5R_06
22u_6.3V_X5R_06
22u_6.3V_X5R_06
22u_6.3V_X5R_06
22u_6.3V_X5R_06
22u_6.3V_X5R_06
22u_6.3V_X5R_06
D AR5 BA25 A12 H18 D
VCCCORE_37 VCCCORE_76 VCCGT_5 VCCGT_64
20190613
AR6 BA27 A14 H20
AR7 VCCCORE_38 VCCCORE_77 BB2 A15 VCCGT_6 VCCGT_65 J7
AR8 VCCCORE_39 VCCCORE_78 BB26 A17 VCCGT_7 VCCGT_66 J8
AR10 VCCCORE_40 VCCCORE_79 BC5 A18 VCCGT_8 VCCGT_67 J11
20190613
AR25 VCCCORE_41 VCCCORE_80 BC6 A20 VCCGT_9 VCCGT_68 J14
AR27 VCCCORE_42 VCCCORE_81 BC7 B3 VCCGT_10 VCCGT_69 J17
AT9 VCCCORE_43 VCCCORE_82 BC9 B4 VCCGT_11 VCCGT_70 J20
AT24 VCCCORE_44 VCCCORE_83 BC10 B6 VCCGT_12 VCCGT_71 K2
AT26 VCCCORE_45 VCCCORE_84 BC26 VCC_CORE B8 VCCGT_13 VCCGT_72 K11
AU5 VCCCORE_46 VCCCORE_85 BC27 B11 VCCGT_14 VCCGT_73 L7 VCCGT
AU6 VCCCORE_47 VCCCORE_86 BD5 PLACE IN CPU BACK SIDE B14 VCCGT_15 VCCGT_74 L8
AU7 VCCCORE_48 VCCCORE_87 BD8 B17 VCCGT_16 VCCGT_75 L10 PLACE IN CPU BACK SIDE
VCCCORE_49 VCCCORE_88 C84 C116 C80 C123 C122 C113 C112 C111 C95 VCCGT_17 VCCGT_76
B.Schematic Diagrams
AU8 BD10 B20 M9
AU9 VCCCORE_50 VCCCORE_89 BD25 C2 VCCGT_18 VCCGT_77 N7 C46 C36 C47 C38 C37 C35 C27 C34 C25 C24 C33
VCCCORE_51 VCCCORE_90 VCCGT_19 VCCGT_78
1u_6.3V_X6S_04
1u_6.3V_X6S_04
1u_6.3V_X6S_04
1u_6.3V_X6S_04
1u_6.3V_X6S_04
1u_6.3V_X6S_04
1u_6.3V_X6S_04
1u_6.3V_X6S_04
1u_6.3V_X6S_04
AU24 BD27 C3 N8
VCCCORE_52 VCCCORE_91 VCCGT_20 VCCGT_79
10u_6.3V_X5R_04
10u_6.3V_X5R_04
10u_6.3V_X5R_04
10u_6.3V_X5R_04
10u_6.3V_X5R_04
10u_6.3V_X5R_04
10u_6.3V_X5R_04
10u_6.3V_X5R_04
10u_6.3V_X5R_04
10u_6.3V_X5R_04
10u_6.3V_X5R_04
AU25 BE9 C6 N9
AU26 VCCCORE_53 VCCCORE_92 BE24 C7 VCCGT_21 VCCGT_80 N10
AU27 VCCCORE_54 VCCCORE_93 BE25 C8 VCCGT_22 VCCGT_81 P2
AV2 VCCCORE_55 VCCCORE_94 BE26 C11 VCCGT_23 VCCGT_82 P8
AV5 VCCCORE_56 VCCCORE_95 BE27 C12 VCCGT_24 VCCGT_83 R9
VCCCORE_57 VCCCORE_96 VCCGT_25 VCCGT_84
AV7
AV10
AV27
AW5
VCCCORE_58
VCCCORE_59
VCCCORE_60
VCCCORE_97
VCCCORE_98
VCCCORE_99
BF2
BF9
BF24
BF26
C14
C15
C17
C18
VCCGT_26
VCCGT_27
VCCGT_28
VCCGT_85
VCCGT_86
VCCGT_87
T8
T9
T10
U8
Sheet 10 of 43
VCCCORE_61 VCCCORE_100 VCCGT_29 VCCGT_88
AW6
AW7
AW8
AW9
VCCCORE_62
VCCCORE_63
VCCCORE_64
VCCCORE_101
VCC_SENSE
BG27
AN6
AN5
VCC_SENSE_R
VSS_SENSE_R
C20
D4
D7
D11
VCCGT_30
VCCGT_31
VCCGT_32
VCCGT_89
VCCGT_90
VCCGT_91
U10
V9
W8
W9
VCC_CORE Processor 9/12
C AW10 VCCCORE_65 VSS_SENSE D12 VCCGT_33 VCCGT_92 AA9 C
VCCCORE_66 AA3 H_CPU_SVIDALRT#_R R37 220_04 H_CPU_SVIDALRT# D14 VCCGT_34 VCCCORE_1 AB2
VIDALERT# H_CPU_SVIDALRT# 35 VCCGT_35 VCCCORE_2
BB9 D15 AB8
BC24 RSVD_74 AA1 H_CPU_SVIDCLK_R R32 *0402_short D17 VCCGT_36 VCCCORE_3 AB9
RSVD_75 VIDSCK H_CPU_SVIDCLK 35 VCCGT_37 VCCCORE_4
AY9 D18 AB10
BB24 RSVD_76 AA2 H_CPU_SVIDDAT_R R29 *0402_short D20 VCCGT_38 VCCCORE_5 AC8
RSVD_77 VIDSOUT H_CPU_SVIDDAT 35 VCCGT_39 VCCCORE_6
E4 AD9
Y3 F5 VCCGT_40 VCCCORE_7 AE8
RSVD_78 F6 VCCGT_41 VCCCORE_8 AE9
BG3 F7 VCCGT_42 VCCCORE_9 AE10
VCCSTG_3 VCCSTG VCCGT_43 VCCCORE_10
F8 AF2
F11 VCCGT_44 VCCCORE_11 AF8
F14 VCCGT_45 VCCCORE_12 AF10
12 of 20 VCCGT_46 VCCCORE_13
F17 AG8
F20 VCCGT_47 VCCCORE_14 AG9
VCC_CORE G11 VCCGT_48 VCCCORE_15 AH9
VCCST SVID Signals G12 VCCGT_49 VCCCORE_16 AJ8
PLACE IN CPU BACK SIDE G14 VCCGT_50 VCCCORE_17 AJ10
R33 56_1%_04 H_CPU_SVIDALRT# G15 VCCGT_51 VCCCORE_18 AK2
G17 VCCGT_52 VCCCORE_19 AK9 VCCGT
C97 C83 C68 C67 C66 C60 R34 100_1%_04 H_CPU_SVIDDAT_R G18 VCCGT_53 VCCCORE_20 AL8
G20 VCCGT_54 VCCCORE_21 AL9
VCCGT_55 VCCCORE_22
10u_6.3V_X5R_04
10u_6.3V_X5R_04
10u_6.3V_X5R_04
10u_6.3V_X5R_04
10u_6.3V_X5R_04
10u_6.3V_X5R_04
1u_6.3V_X6S_04
1u_6.3V_X6S_04
1u_6.3V_X6S_04
1u_6.3V_X6S_04
1u_6.3V_X6S_04
1u_6.3V_X6S_04
1u_6.3V_X6S_04
1u_6.3V_X6S_04
1u_6.3V_X6S_04
1u_6.3V_X6S_04
1u_6.3V_X6S_04
1u_6.3V_X6S_04
1u_6.3V_X6S_04
1u_6.3V_X6S_04
1u_6.3V_X6S_04
R342
100_1%_04 VCC_CORE VCC_CORE
PLACE IN CPU BACK SIDE PLACE IN CPU BACK SIDE
C82 C85 C77 C99 C128 C127 C117 C56 C62 C61
1u_6.3V_X6S_04
1u_6.3V_X6S_04
1u_6.3V_X6S_04
10u_6.3V_X5R_04
10u_6.3V_X5R_04
10u_6.3V_X5R_04
10u_6.3V_X5R_04
*22u_6.3V_X5R_06
*22u_6.3V_X5R_06
*22u_6.3V_X5R_06
VCCGT
VCC_CORE
PLACE IN CPU BACK SIDE
PLACE IN CPU BACK SIDE
A C101 C65 C64 C124 C96 C125 C26 C19 C54 C23 C43 C44 C39 C53 C55 C51 C52 A
*22u_6.3V_X5R_06
*22u_6.3V_X5R_06
*22u_6.3V_X5R_06
*22u_6.3V_X5R_06
*22u_6.3V_X5R_06
47u_6.3V_X5R_08
10u_6.3V_X5R_04
10u_6.3V_X5R_04
10u_6.3V_X5R_04
22u_6.3V_X5R_06
22u_6.3V_X5R_06
22u_6.3V_X5R_06
22u_6.3V_X5R_06
10u_6.3V_X5R_04
22u_6.3V_X5R_06
22u_6.3V_X5R_06
22u_6.3V_X5R_06
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
35,36 VCC_CORE Title
35,36 VCCGT
2,9,11,32,35 VCCST
[10] CML U L,M/20 VCC,VCCGT
2,11,32 VCCSTG Size Document Number Rev
A3 NL40CU 6-71-NL4C0-D02 D02
Date: Friday, August 16, 2019 Sheet 10 of 44
5 4 3 2 1
Processor 9/12 B - 11
Schematic Diagrams
Processor 10/12
5 4 3 2 1
D D
VDDQ FIX 3.3A 1.2V+5%
VCCIO FIX 0.95V 4A VCCIO
VDDQ U1N
AK24
4A PLACE IN CPU BACK SIDE
PLACE IN CPU BACK SIDE 2.8A VCCIO_OUT_1
AD36 AK26
AH32 VDDQ_1 VCCIO_OUT_2 AL24 C76 C154 C78 C134 C135
C57 C121 C75 C110 C58 C109 AH36 VDDQ_2 VCCIO_OUT_3 AL25
VDDQ_3 VCCIO_OUT_4
*10u_6.3V_X5R_04
AM36 AL26
1u_6.3V_X6S_04
1u_6.3V_X6S_04
10u_6.3V_X5R_04
10u_6.3V_X5R_04
VDDQ_4 VCCIO_OUT_5
1u_6.3V_X6S_04
10u_6.3V_X5R_04
10u_6.3V_X5R_04
22u_6.3V_X5R_06
*22u_6.3V_X5R_06
AN32 AL27
1u_6.3V_X6S_04
AW32 VDDQ_5 VCCIO_OUT_6 AM25
VDDQ_6 VCCIO_OUT_7
B.Schematic Diagrams
AY36 AM27
BE32 VDDQ_7 VCCIO_OUT_8 BH24
BH36 VDDQ_8 VCCIO_OUT_9 BH25
R32 VDDQ_9 VCCIO_OUT_10 BH26
Y36 VDDQ_10 VCCIO_OUT_11 BH27
VDDQ_11 VCCIO_OUT_12 BJ24
VCCIO_OUT_13 BJ26
VCCIO_OUT_14 BP16
VCCST BC28 VCCIO_OUT_15 BP18
VCCSA SVID 6A VCCSA
RSVD_73 VCCIO_OUT_16
Sheet 11 of 43 VCCSTG
VCCST FIX 60mA 1.05V BP11
BP2 VCCST_2
VCCST_1
VCCSA_1
VCCSA_2
BG8
BG10
BH9 C137
PLACE IN CPU BACK SIDE
C151 C136 C155 C156 C138
VCCSA_3
10u_6.3V_X5R_04
10u_6.3V_X5R_04
10u_6.3V_X5R_04
10u_6.3V_X5R_04
22u_6.3V_X5R_06
10u_6.3V_X5R_04
VCCSTG_1 VCCSA_5
1u_6.3V_X6S_04
BG2 BJ10
VDDQ R82 VCCSFR_OC VCCSTG_2 VCCSA_6 BK8
VCCPLL _OC FIX 120mA VDDQ VCCSA_7
C *0_04 FOR C10 BL27 BK25 C
BM26 VCCPLL_OC_1 VCCSA_8 BK27
VCCPLL_OC_2 VCCSA_9 BL8
VCCPLL FIX 130mA 1.05V VCCSA_10
VCCST BR11 BL9
C139 C148 C133 BT11 VCCPLL_1 VCCSA_11 BL10
VCCPLL_2 VCCSA_12 BL24
VCCSA_13
1u_6.3V_X6S_04
1u_6.3V_X6S_04
*10u_6.3V_X5R_04
C157 C165 BL26
VCCSA_14 BM24
VCCSA_15
1u_6.3V_X6S_04
0.1u_6.3V_X5R_02
BN25
VCCSA_16
BP28
VCCIO_SENSE VCCIO_SENSE 37
BP29
VSSIO_SENSE VSSIO_SENSE 37
BE7 VSSSA_SENSE_R
VSSSA_SENSE BG7 VCCSA_SENSE_R
VCCSA_SENSE VCCSA
14 of 20
CML_U_IP_CCG
R74
100_04
A CML_U_IP_CCG A
32 VCCSFR_OC ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
2,9,10,32,35 VCCST Title
2,10,32 VCCSTG
14,15,32,33 VDDQ
[11] CML U N,O/20 VDDQ,VCCIO
2,4,37 VCCIO Size Document Number Rev
35,36 VCCSA
A3 NL40CU 6-71-NL4C0-D02 D02
Date: Friday, August 16, 2019 Sheet 11 of 44
5 4 3 2 1
B - 12 Processor 10/12
Schematic Diagrams
Processor 11/12
5 4 3 2 1
U1P
D D
1.05VA
1.625A BP20
BW16 VCCPRIM_1P05_5 CB16 199mA
VCCPRIM_1P05_6 VCCPRIM_3P3_3 3.3VA
C164 1u_6.3V_X6S_04 BW18
BW19 VCCPRIM_1P05_7 VCC_RTC
BY16 VCCPRIM_1P05_8
CA14 VCCPRIM_1P05_9 BR23 2mA C149 1u_6.3V_X6S_04
VCCPRIM_1P05_10 VCCRTC C150 0.1u_6.3V_X5R_02
1.8VA
696mA CC15 BY20 1.625A
1.05VA
CD15 VCCPRIM_1P8_6 VCCPRIM_1P05_3 BP24 C169 *0.1u_6.3V_X6S_04
C193 1u_6.3V_X6S_04 CD16 VCCPRIM_1P8_7 DCPRTC
CP17 VCCPRIM_1P8_8
VCCPRIM_1P8_9 BR20 1.625A
B.Schematic Diagrams
VCCPRIM_1P05_4 1.05VA
3.3VA
199mA CB22
CB23 VCCPRIM_3P3_4 BT12 102mA
C171 1u_6.3V_X6S_04 CC22 VCCPRIM_3P3_5 VCCAPLL_1P05_1
CC23 VCCPRIM_3P3_6 BP14 9mA
C181 0.1u_6.3V_X5R_02 CD22 VCCPRIM_3P3_7 VCCA_BCLK_1P05
CD23 VCCPRIM_3P3_8 BR14 102mA
CP29 VCCPRIM_3P3_9 VCCAPLL_1P05_2
VCCPRIM_3P3_10 1.05VA
1.05VA
C183
4.26A
1u_6.3V_X6S_04
BU15
BU22
BV15
VCCPRIM_CORE_1
VCCPRIM_CORE_2
VCCPRIM_CORE_3
VCCA_SRC_1P05
VCCA_XTAL_1P05
BU12
CP5
42mA
2mA C170 1u_6.3V_X6S_04 Sheet 12 of 43
BV16 BY24 610mA
C152
C172
10u_6.3V_X5R_04
22u_6.3V_X5R_06
BV18
BV19
BV20
VCCPRIM_CORE_4
VCCPRIM_CORE_5
VCCPRIM_CORE_6
VCCDPHY_1P24_3
VCCDPHY_1P24_4
CA24
BY23
VCCDPHY_1.24V
Processor 11/12
BV22 VCCPRIM_CORE_7 VCCDPHY_1P24_1 CA23
C BW20 VCCPRIM_CORE_8 VCCDPHY_1P24_2 CP25 VCCDPHY_EC_1P24 C191 4.7u_6.3V_X5R_04 C
BW22 VCCPRIM_CORE_9 VCCDPHY_EC_1P24
CA12 VCCPRIM_CORE_10 BT23 1mA
VCCPRIM_CORE_11 VCCDSW_3P3_2 VDD3
CA16
CA18 VCCPRIM_CORE_12
CA19 VCCPRIM_CORE_13 BR12 27mA
VCCPRIM_CORE_14 VCCA_19P2_1P05 1.05VA
CA20
CB12 VCCPRIM_CORE_15
CB14 VCCPRIM_CORE_16
CB15 VCCPRIM_CORE_17 CC18 696mA
VCCPDSW _1P05 24mA VCCPRIM_CORE_18 VCCPRIM_1P8_1 1.8VA
C163 1u_6.3V_X6S_04 BT24 CC19
VCCDSW_1P05 VCCPRIM_1P8_2 CD18
102mA BU14 VCCPRIM_1P8_3 CD19 C192 1u_6.3V_X6S_04
1.05VA VCCPRIM_1P05_15 VCCPRIM_1P8_4 CP23
BV12 VCCPRIM_1P8_5
1.05VA VCCPRIM_MPHY_1P05_2
BW12 BW23 199mA
3.3VA
C182 22u_6.3V_X5R_06 BW14 VCCPRIM_MPHY_1P05_3 VCCPRIM_3P3_2
BY12 VCCPRIM_MPHY_1P05_4
BY14 VCCPRIM_MPHY_1P05_5
152mA VCCPRIM_MPHY_1P05_6
1.05VA
BV2 BP23 199mA
3.3VA
C173 1u_6.3V_X6S_04 VCCAMPHYPLL_1P05 VCCPRIM_3P3_1
C153 C184 1.05VA
102mA BR15 CB36 R122 *100K_04 3.3VA
VCCAPLL_1P05_3 GPP_B0/CORE_VID0 CB35 R123 *10K_04
22u_6.3V_X5R_06 22u_6.3V_X5R_06 GPP_B1/CORE_VID1
1.05VA
280mA CC12
VCCDUSB_1P05
VDD3
1mA BR24 R121 *100K_04 3.3VA
C147 1u_6.3V_X6S_04 VCCDSW_3P3_1 R138 *10K_04
3.3VA
6mA BT20
B VCCHDA B
CML_U_IP_CCG 16 of 20
A A
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Title
4,32 1.05VA
5,6,8,9,21,22,23,24,25,26,29,30,31,32,33,35,37,38 VDD3 [12] CML U P/20 POWER
25,30,33 1.8VA
Size Document Number Rev
4,5,6,7,8,9,22,23,30,33 3.3VA
8 VCC_RTC A3 NL40CU 6-71-NL4C0-D02 D02
5 SPI_3.3V
Date: Friday, August 16, 2019 Sheet 12 of 44
5 4 3 2 1
Processor 11/12 B - 13
Schematic Diagrams
Processor 12/12
5 4 3 2 1
㬌 枩 㷔 溆 悥⛐ 側 朊
U1R U1S U1T
T65
D BT35 BY25 D
CR34 BL7 D6 VSS_277 VSS_180 J18 N6 CF23
BT5 VSS_342 VSS_330 AE25 AL32 VSS_290 VSS_183 AU32 B37 VSS_66 VSS_99 V4
BY5 VSS_351 VSS_337 BM33 BT36 VSS_156 VSS_186 BY28 CB3 VSS_73 VSS_106 BE30
CP35 VSS_361 VSS_345 CM5 D8 VSS_165 VSS_245 J21 P10 VSS_79 VSS_115 CF28
CM37 VSS_371 VSS_354 AE27 AL7 VSS_172 VSS_257 AV25 B5 VSS_84 VSS_126 W10
CK37 VSS_381 VSS_364 BM35 D9 VSS_208 VSS_270 BY33 CB33 VSS_89 VSS_139 BE31
AW1 VSS_391 VSS_374 CM9 AM10 VSS_217 VSS_284 J24 P3 VSS_95 VSS_8 CF3
CM1 VSS_401 VSS_384 AE30 BU11 VSS_227 VSS_151 AV28 B7 VSS_102 VSS_19 W27
BD6 VSS_411 VSS_302 BM36 E23 VSS_238 VSS_161 BY35 CB4 VSS_110 VSS_29 CF4
AY4 VSS_421 VSS_308 CN13 AM28 VSS_250 VSS_169 J33 P33 VSS_120 VSS_83 W30
B34 VSS_360 VSS_315 AE7 E27 VSS_263 VSS_175 AV3 B9 VSS_132 VSS_87 BF3
E35 VSS_370 VSS_322 BM9 AM33 VSS_276 VSS_179 BY36 CB7 VSS_145 VSS_92 CG33
A4 VSS_380 VSS_329 CN17 BU23 VSS_289 VSS_182 J36 P36 VSS_14 VSS_98 W7
AE24 VSS_390 VSS_336 AF27 E29 VSS_155 VSS_233 AV33 BA10 VSS_25 VSS_105 BF33
AE26 VSS_400 VSS_344 BN30 AM35 VSS_164 VSS_244 J6 CC11 VSS_35 VSS_114 CG7
VSS_410 VSS_353 VSS_200 VSS_256 VSS_44 VSS_125
B.Schematic Diagrams
Sheet 13 of 43 T66
B2
B36
C36
VSS_350
VSS_359
VSS_369
VSS_379
VSS_307
VSS_314
VSS_321
VSS_328
CN29
AF33
BP15
BU7
E9
AN28
VSS_249
VSS_262
VSS_275
VSS_288
VSS_168
VSS_174
VSS_178
VSS_222
K22
AV6
C25
R27
BB3
CC25
VSS_78
VSS_131
VSS_144
VSS_13
VSS_82
VSS_86
VSS_91
VSS_97
BG25
Y30
BG28
C37 AF36 BV11 K24 R28 CJ11
17 of 20 18 of 20 19 of 20
CML_U_IP_CCG
CML_U_IP_CCG CML_U_IP_CCG
A A
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Title
[13] CML U R,S,T/20 VSS
Size Document Number Rev
A3 NL40CU 6-71-NL4C0-D02 D02
Date: Friday, August 16, 2019 Sheet 13 of 44
5 4 3 2 1
B - 14 Processor 12/12
Schematic Diagrams
DDR4 SO-DIMM_0
5 4 3 2 1
VDDQ_VTT
J_DIMMAA VDDQ J_DIMMAB
M_A_DQ2 M_A_DQ[63:0] 3
137 8 163 258
3 M_A_CLK_DDR0 CK0_T DQ0 M_A_DQ0 VDD19 VTT 2.5V
139 7 160
3 M_A_CLK_DDR#0 CK0_C DQ1 M_A_DQ1 VDD18
138 20 159
3 M_A_CLK_DDR1 CK1_T DQ2 M_A_DQ3 VDD17
140 21 154 259
3 M_A_CLK_DDR#1 CK1_C DQ3 M_A_DQ5 VDD16 VPP2
4 153 257
109 DQ4 3 M_A_DQ4 VDDQ 148 VDD15 VPP1
3
3
M_A_CKE0
M_A_CKE1
110 CKE0
CKE1
DQ5
DQ6
16 M_A_DQ6
M_A_DQ7
PLACE CLOSE TO SODIMM 147 VDD14
VDD13 3.3VS
17 142
149 DQ7 28 M_A_DQ13 DIMM0_CHA_EVENT# R69 240_1%_04 141 VDD12
3 M_A_CS#0 S0* DQ8 M_A_DQ12 VDD11
D 157 29 136 255 D
3 M_A_CS#1 S1* DQ9 M_A_DQ11 VDD10 VDDSPD
41 135
155 DQ10 42 M_A_DQ15 130 VDD9
3 M_A_ODT0 ODT0 DQ11 M_A_DQ9 VDD8
161 24 129 C232 C233
3 M_A_ODT1 ODT1 DQ12 M_A_DQ8 VDD7
25 124
DQ13 M_A_DQ10 VDD6
3
3
3
3
3
M_A_BG0
M_A_BG1
M_A_BA0
M_A_BA1
M_A_A[16:0]
115
113
150
145
BG0
BG1
BA0
BA1
DQ14
DQ15
DQ16
DQ17
38
37
50
49
62
M_A_DQ14
M_A_DQ16
M_A_DQ20
M_A_DQ23
SO-DIMM A 123
118
117
112
111
VDD5
VDD4
VDD3
VDD2
0.1u_10V_X5R_04
VDDQ
M_A_A6
126
127 A5 DQ24
70
71 M_A_DQ29
251
247 VSS VSS
252
248 PLACE CLOSE TO SODIMM
B.Schematic Diagrams
M_A_A7 122 A6 DQ25 83 M_A_DQ31 243 VSS VSS 244
M_A_A8 125 A7 DQ26 84 M_A_DQ30 239 VSS VSS 238
M_A_A9 121 A8 DQ27 66 M_A_DQ24 235 VSS VSS 234
M_A_A10 146 A9 DQ28 67 M_A_DQ25 231 VSS VSS 230 C132 C131 C92
M_A_A11
M_A_A12
M_A_A13
120
119
158
A10_AP
A11
A12
DQ29
DQ30
DQ31
79
80
174
M_A_DQ26
M_A_DQ27
M_A_DQ36
227
223
217
VSS
VSS
VSS
VSS
VSS
VSS
226
222
218
10u_6.3V_X5R_04 10u_6.3V_X5R_04 10u_6.3V_X5R_04 Sheet 14 of 43
M_A_A14 A13 DQ32 M_A_DQ33 VSS VSS
DDR4 SO-DIMM_0
151 173 213 214
M_A_A15 156 A14_WE* DQ33 187 M_A_DQ34 209 VSS VSS 210
M_A_A16 152 A15_CAS* DQ34 186 M_A_DQ35 205 VSS VSS 206
A16_RAS* DQ35 170 M_A_DQ32 201 VSS VSS 202
DQ36 169 M_A_DQ37 197 VSS VSS 196 C50 C212 C93
C 114 DQ37 183 M_A_DQ39 VREFCA_CHA_DIMM PLACE THE CAP CLOSE TO SODIMM 193 VSS VSS 192 C
3 M_A_ACT# ACT* DQ38 M_A_DQ38 VSS VSS
182 189 188 10u_6.3V_X5R_04 10u_6.3V_X5R_04 *10u_6.3V_X5R_04
143 DQ39 195 M_A_DQ40 185 VSS VSS 184
3 DDR0_A_PARITY PARITY DQ40 M_A_DQ41 VSS VSS
116 194 181 180
3 DDR0_A_ALERT# DIMM0_CHA_EVENT# 134 ALERT* DQ41 M_A_DQ42 VSS VSS
207 C145 175 176
CPUDRAMRST# 108 EVENT* DQ42 208 M_A_DQ43 *0.1u_10V_X7R_04 171 VSS VSS 172 VDDQ
3,15 CPUDRAMRST# RESET* DQ43 M_A_DQ44 VSS VSS
191 167 168
VREFCA_CHA_DIMM 164 DQ44 190 M_A_DQ45 107 VSS VSS 106
VREFCA DQ45 203 M_A_DQ46 103 VSS VSS 102
254 DQ46 204 M_A_DQ47 99 VSS VSS 98 C17 C8
5,15 SMB_DAT_DDR SDA DQ47 M_A_DQ52 VSS VSS
253 216 93 94
5,15 SMB_CLK_DDR SCL DQ48 M_A_DQ49 VSS VSS
215 89 90 1u_6.3V_X5R_02 1u_6.3V_X5R_02
166 DQ49 228 M_A_DQ51 85 VSS VSS 86
260 SA2 DQ50 229 M_A_DQ50 81 VSS VSS 82
256 SA1 DQ51 211 M_A_DQ48 77 VSS VSS 78 VDDQ
SA0 DQ52 212 M_A_DQ53 73 VSS VSS 72
PLACE THE CAP CLOSE TO DQ53 224 M_A_DQ55 69 VSS VSS 68
SODIMM DQ54 225 M_A_DQ54 65 VSS VSS 64
VDDQ DQ55 VSS VSS
92 237 M_A_DQ56 61 60 C74 C195 C178 C22
91 CB0_NC DQ56 236 M_A_DQ57 57 VSS VSS 56
101 CB1_NC DQ57 249 M_A_DQ63 51 VSS VSS 52 1u_6.3V_X5R_02 1u_6.3V_X5R_02 1u_6.3V_X5R_02 *1u_6.3V_X5R_04
R54 CB2_NC DQ58 M_A_DQ60 VSS VSS
105 250 47 48
88 CB3_NC DQ59 232 M_A_DQ58 43 VSS VSS 44
470_04 CB4_NC DQ60 M_A_DQ59 VSS VSS
87 233 39 40
100 CB5_NC DQ61 245 M_A_DQ62 35 VSS VSS 36
CPUDRAMRST# 104 CB6_NC DQ62 246 M_A_DQ61 31 VSS VSS 30
VDDQ CB7_NC DQ63 VSS VSS
27 26 2.5V
M_A_DQS0 M_A_DQS[7:0] 3 VSS VSS
C73 12 13 23 22
33 DM0*/DBI0* DQS0_T 34 M_A_DQS1 19 VSS VSS 18
B *0.1u_10V_X7R_04 54 DM1*/DBI1* DQS1_T 55 M_A_DQS2 15 VSS VSS 14 B
75 DM2*/DBI2* DQS2_T 76 M_A_DQS3 9 VSS VSS 10 C261 C262
178 DM3*/DBI3* DQS3_T 179 M_A_DQS4 5 VSS VSS 6 10u_6.3V_X5R_04 1u_6.3V_X5R_02
199 DM4*/DBI4* DQS4_T 200 M_A_DQS5 1 VSS VSS 2
220 DM5*/DBI5* DQS5_T 221 M_A_DQS6 VSS VSS
241 DM6*/DBI6* DQS6_T 242 M_A_DQS7
96 DM7*/DBI7* DQS7_T 97
DM8*/DBI8* DQS8_T D4AR0-26001-1P40
M_A_DQS#0 M_A_DQS#[7:0] 3 VDDQ_VTT
11 PCB Footprint = ddr4_260p_rvs_h40_d4arx
DQS0_C 32 M_A_DQS#1 DIMM ASSY BOM
DQS1_C 53 M_A_DQS#2
DQS2_C 74 M_A_DQS#3
DQS3_C 177 M_A_DQS#4
DQS4_C 198 M_A_DQS#5 C229 C230 C231
DQS5_C 219 M_A_DQS#6 10u_6.3V_X5R_04 1u_6.3V_X5R_02 1u_6.3V_X5R_02
DQS6_C 240 M_A_DQS#7
DQS7_C 95
162 DQS8_C
165 S2*/C0
S3*/C1
VDDQ
D4AR0-26001-1P40
PCB Footprint = ddr4_260p_rvs_h40_d4arx
DIMM ASSY BOM
6-86-24260-000 PLACE CLOSE TO CHA R88
1K_1%_04
11,15,32,33 VDDQ
R99 2_1%_04 R100 *0402_short VREFCA_CHA_DIMM 15,33 VDDQ_VTT
A 3 DDR_VREF_CA A
15,37 2.5V
C162
0.022u_25V_X7R_04 C146
TO CHA J_DIMMA 2,5,6,7,8,9,15,16,17,21,23,24,26,29,30,35,37 3.3VS
DDR4 SO-DIMM_0 B - 15
Schematic Diagrams
DDR4 SO-DIMM_1
5 4 3 2 1
M_B_DQ11 M_B_DQ[63:0] 3
137 8 163 258
3 M_B_CLK_DDR0 CK0_T DQ0 M_B_DQ13 VDD19 VTT 2.5V
139 7 160
3 M_B_CLK_DDR#0 CK0_C DQ1 M_B_DQ10 VDD18
3
3
M_B_CLK_DDR1
M_B_CLK_DDR#1
3
3
M_B_CKE0
M_B_CKE1
138
140
109
110
CK1_T
CK1_C
CKE0
DQ2
DQ3
DQ4
DQ5
20
21
4
3
16
M_B_DQ9
M_B_DQ8
M_B_DQ12
M_B_DQ15
SO-DIMM B 159
154
153
148
147
VDD17
VDD16
VDD15
VDD14
VPP2
VPP1
259
257
D
3
3
3
M_B_CS#0
M_B_CS#1
M_B_ODT0
149
157
155
S0*
S1*
DQ7
DQ8
DQ9
DQ10
17
28
29
41
42
M_B_DQ5
M_B_DQ1
M_B_DQ2
M_B_DQ3
RAM2 142
141
136
135
130
VDD12
VDD11
VDD10
VDD9
VDDSPD
255
3.3VS
C225 C228
D
132 45 GND2
M_B_A3 131 A2 DQ21 58 M_B_DQ23 MT2 VDDQ
M_B_A4 A3 DQ22 M_B_DQ22 DIMM1_CHB_EVENT#
M_B_A5
128
126 A4 DQ23
59
70 M_B_DQ24
R68 240_1%_04
251 252 PLACE CLOSE TO SODIMM
M_B_A6 127 A5 DQ24 71 M_B_DQ25 247 VSS VSS 248
M_B_A7 122 A6 DQ25 83 M_B_DQ26 243 VSS VSS 244
M_B_A8 125 A7 DQ26 84 M_B_DQ27 239 VSS VSS 238
M_B_A9 121 A8 DQ27 66 M_B_DQ29 235 VSS VSS 234 C72 C16 C168
M_B_A10 146 A9 DQ28 67 M_B_DQ28 231 VSS VSS 230
M_B_A11 A10_AP DQ29 M_B_DQ30 PLACE THE CAP CLOSE TO SODIMM VSS VSS
Sheet 15 of 43 M_B_A12
M_B_A13
M_B_A14
120
119
158
151
A11
A12
A13
DQ30
DQ31
DQ32
79
80
174
173
M_B_DQ31
M_B_DQ37
M_B_DQ36
VREFCA_CHB_DIMM
C143
227
223
217
213
VSS
VSS
VSS
VSS
VSS
VSS
226
222
218
214
10u_6.3V_X5R_04 10u_6.3V_X5R_04 10u_6.3V_X5R_04
D4AS0-26001-1P40 VDDQ
PCB Footprint = ddr4_260p_std_h40_d4asx
DIMM ASSY BOM
6-86-24260-002 PLACE CLOSE TO CHB R81
1K_1%_04
11,14,32,33 VDDQ
A 14,33 VDDQ_VTT A
R76 2_1%_04 R79 *0402_short VREFCA_CHB_DIMM
3 DDR1_VREF_DQ 14,37 2.5V
C120
C144 R80
TO CHB J_DIMMB 2,5,6,7,8,9,14,16,17,21,23,24,26,29,30,35,37 3.3VS
0.022u_25V_X7R_04 1K_1%_04
D02 common design 16V to 25V *0.1u_10V_X7R_04 ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
R71 Title
24.9_1%_04
[15] DDR4 SO-DIMM_1
Size Document Number Rev
A3 NL40CU 6-71-NL4C0-D02 D02
Date: Friday, August 16, 2019 Sheet 15 of 44
5 4 3 2 1
B - 16 DDR4 SO-DIMM_1
Schematic Diagrams
HDMI
5 4 3 2 1
HDMI_5VS
5VS
U27
VOUT
2 HDMI CONNECTOR HDMI_5VS
For ESD
3 C383 C382 J_HDMI1 C128G1-K1909-L
VIN 1 PCB Footprint = C12826-119A8L
A
C384 GND 22u_6.3V_X5R_06 22u_6.3V_X5R_06 P/N = 6-21-14A70-019
*10u_6.3V_X5R_06 D33
APL3517A
D
RB751S-40C2 D
20190708
C
A
A
19 HDMI_HPD-C
18 HOT PLUG DETECT
TMDS_CLOCK +5V 17
HDMI_SDA-C 16 DDC/CEC GND R390 R389 D32 D31 D34
AC
AC
AC
SDA HDMI_SCL-C
BAV99 RECTIFIER
BAV99 RECTIFIER
BAV99 RECTIFIER
15
C377 R376 14 SCL 2.2K_04 2.2K_04
RESERVED 13 HDMI_CEC
B.Schematic Diagrams
TMDS_CLOCK TMDS_CLOCK#J CEC T12 HDMI_SCL-C
*1.5p_50V_04 100_1%_04 12
TMDS CLOCK- 11
TMDS_CLOCK# TMDS_CLOCK# TMDS_CLOCKJ 10 CLK SHIELD HDMI_SDA-C
TMDS CLOCK+ 9 TMDS_DATA0#J
8 TMDS DATA0- HDMI_HPD-C
20190605 EMI SHIELD0
TMDS_DATA1 TMDS_DATA1 TMDS_DATA1#J 6
TMDS DATA1-
TMDS DATA0+
7 TMDS_DATA0J
Sheet 16 of 43
5
R362 TMDS_DATA1#
TMDS_DATA1J 4
TMDS DATA1+
SHIELD1
TMDS DATA2-
3 TMDS_DATA2#J HDMI
2 TMDS_DATA0
C
100_1%_04 SHIELD2 1 TMDS_DATA2J C
TMDS DATA2+
TMDS_DATA1# R381
TMDS_DATA0
GND
GND
GND
GND
100_1%_04
TMDS_DATA0# TMDS_DATA0#
GND1
GND2
GND3
GND4
E M I 㒢㓦 20190605 EMI
2
B 2 HDMI_CLOCKP
C379 0.1u_10V_X5R_04 TMDS_CLOCK# TMDS_DATA0 R380 470_04 B
G
2 HDMI_CLOCKN TMDS_DATA2#
HDMI_SDA-C R371 470_04
1 6 TMDS_DATA2
2 HDMI_CTRLDATA R370 470_04
S
D
Zdiff=85Ω TMDS_CLOCK# R379 470_04
5
MTDK5S6R TMDS_DATA1#
HDMI ESD W/O LEVELSHIFT 暨
ᶲ , NET HDMI_SCL-C R364 470_04
4 3 TMDS_DATA1
⎗S W A P 2 HDMI_CTRLCLK R363 470_04
S
D30
Q29B
TMDS_DATA0# TMDS_DATA0#J MTDK5S6R GND_HDMI 5VS
6 5
TMDS_DATA0 7 4 TMDS_DATA0J 3.3VS
D
8 3
TMDS_CLOCK# 9 2 TMDS_CLOCK#J
TMDS_CLOCK TMDS_CLOCKJ G
10 1
S
R396 Q30 Q28
20190619 layout swap 2SK3018S3 2SK3018S3
G
ESD73034D 1M_04
PCB Footprint = dfn10-2_5x1mm-short 20190708 20190708
D29 HDMI_HPD-C
S D
2 HDMI_HPD
TMDS_DATA2# 6 5 TMDS_DATA2#J
A A
TMDS_DATA2 TMDS_DATA2J
TMDS_DATA1#
7
8
9
4
3
2 TMDS_DATA1#J
R393
20K_04
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
TMDS_DATA1 10 1 TMDS_DATA1J Title
[16] HDMI
20190619 layout swap
ESD73034D Size Document Number Rev
PCB Footprint = dfn10-2_5x1mm-short
21,22,23,29,30
2,5,6,7,8,9,14,15,17,21,23,24,26,29,30,35,37
5VS
3.3VS
A4 NL40CU 6-71-NL4C0-D02 D02
Date: Friday, August 16, 2019 Sheet 16 of 44
5 4 3 2 1
HDMI B - 17
Schematic Diagrams
Panel
5 4 3 2 1
PLVDD
2A
PANEL POWER
J_LCD1 ℙ䓐䶂 嶗
DEFAULT SHORT
C352 1
2 1 PJ2 2 1 2mm
1u_6.3V_X5R_02 3 2 VIN VLED
4 3 *AO3415 Q1
5 4 S D
6 5
7 6 C48
C356 0.1u_10V_X5R_04 EDP_TXN0 8 7 *0.1u_50V_X5V_04 C11
2 EDP_TXN_0
G
D C357 0.1u_10V_X5R_04 EDP_TXP0 9 8 *0.22u_25V_X7R_06 D
2 EDP_TXP_0 9 6-15-35726-7B0
10
C358 0.1u_10V_X5R_04 EDP_TXN1 11 10 3.3V R36
2 EDP_TXN_1 EDP_TXP1 11
C359 0.1u_10V_X5R_04 12 *4.7K_06
2 EDP_TXP_1 12
13 8/14 R40
C360 0.1u_10V_X5R_04 EDP_TXN2 14 13 GND1 *150K_1%_04
2 EDP_TXN_2 EDP_TXP2 14 GND1
C361 0.1u_10V_X5R_04 15 GND2 R35
2 EDP_TXP_2 15 GND2
16 GND3 *100K_04 R39 *19.1K_04 R45
C365 0.1u_10V_X5R_04 EDP_TXN3 17 16 GND3 GND4
D
2 EDP_TXN_3 EDP_TXP3 17 GND4
C364 0.1u_10V_X5R_04 18 GND5 *10K_04
2 EDP_TXP_3 18 GND5
6
3.3VS R345 *100K_04 19 D
C366 0.1u_10V_X5R_04 EDP_AUX# 20 19 PANEL_VCC_EN G Q2A
2 EDP_AUXN EDP_AUX 20
C369 0.1u_10V_X5R_04 21 R41 *0_04 2G *MTD5S6R
2 EDP_AUXP
S
22 21 S
9,28,30,32 SUSB# Q3
1
R346 *100K_04 23 22 R42 *0_04 *2SK3018S3
B.Schematic Diagrams
23
3
EDP_BRIGHTNESS
INV_BLON
24
25 24 枸 䔁 婧㔜Q PXFS!TFRV
F
O D
F D
Q2B
EDP_HPD_L 26 25 5G *MTD5S6R
27 26 S
4
VLED_L 28 27
L1 29 28
2A 29
VLED . 30
30
HCB1608KF-121T30 lvdfh-03008-tp00+
Sheet 17 of 43 C41
0.1u_50V_X5R_04
C40
*0.01u_50V_X7R_04
PCB Footprint = LVDFH-03008-TP00
P/N = 6-21-44K00-030
Panel C C
R352 *10K_04
PANEL POWER
PLVDD
Entire trace of Panel VCC should be wider than 120-mil
EDP_BRIGHTNESS
2 EDP_BRIGHTNESS
3.3VS
>120mil
3.3VS
EM5290
PCBfootprint:
C
C348
A
D9 U22 EM5209
TDFN14-2X3MM-A
BAV99 RECTIFIER 0.1u_6.3V_X5R_02
1 6
PLVDD 2 IN1 IN2 7 PLVDD
AC
R26 1K_04 EDP_HPD_L IN1 IN2
2 EDP_HPD >120mil >120mil
PLVDD 13 8
C21 OUT1 OUT2
14 9
R28 OUT1 OUT2
C355 C349
G5016_CT1 12 10 G5016_CT1
*220p_50V_NPO_04 100K_04 CT1 CT2
*10u_6.3V_X5R_04 0.1u_6.3V_X5R_02
VBIAS
GND
GND
EN1
EN2
C351
1000p_50V_X7R_04
ὅ őŢůŦŭġųŪŴŦġŵŪ ŮŦġ 婧 㔜 ℞ῤ
15
11
3
5
B B
5V
R337
PANEL_VCC_EN C350 PANEL_VCC_EN
2 NB_ENAVDD
1u_6.3V_X5R_02
*0402_short
R336 100K_04
R333 R338
10K_04 100_04
3.3V
24 BKL_EN
6
3.3V D
U25A
14
74LVC08APW U25B 2G
14
2 BLON
1 74LVC08APW S
1
Q26A
3
3 BLON1 4 D
R384 100K_04 BLON 2 6 BLON2 Q26B MTDK3S6R
5 3.3V PANEL_VCC_EN 5G MTDK3S6R
S
7
4
R385 *100K_04 U25C
14
7
74LVC08APW
SB_BLON 9
6 SB_BLON INV_BLON
8
3.3V 10
A A
B - 18 Panel
Schematic Diagrams
Layout rules:
ANX7440 PWR ON SEQ 1. Place ANX7440/30/90/96 and USB Type-C/Type-A connector in an open area for
easier routing.
2. High-speed trace should be routed with high-priority.
VDD_IO/VDD33
VDD18
t 0 ʁ0 m s
t 1 ʁ0 m s
USB3.1/DP MUX ANX7440 3. If using internal DC/DC, create a dedicated DC/DC VGND
4. High-speed trace must keep distance from DC/DC and other noise source. RX
to TX spacing should be >20mils.
5. High-speed trace must be continuous and without stub, especially to RX
POWER_EN Ferrite Beads choose low DCR parts. traces.
t2>12ms might choose, but not limited to:
6. Ground void should be applied to wide pad along the high-speed traces.
FLIP/OP_MODE VALID VDD0.9_LEX BKP1608HS600-T 220ohm,
7. ESD ground should be wide.
BLM18SG221TN1 2.5A,
BLM18SG121TN1 DCR=0.04ohm D02 common design 16V to 25V 8. Every AVDD09 pin must have a 0.01uF decoupling capacitor that is very
D close. D
L11 HCB1608KF-300T60 9. AVDD09 power delivery must be wide and away from noisy signal.
P/N = 6-19-31001-275
DCR = 0.04ohm
W/_TYPE_C+DP
C303
Impedance = 125ohm
Rated Current = 3A C323 C324 C312
4.7u_6.3V_X5R_04
4.7u_6.3V_X5R_04 1000p_50V_X7R_04 0.01u_25V_X7R_04 W/_TYPE_C+DP
W/_TYPE_C+DP W/_TYPE_C+DP W/_TYPE_C+DP
Note: close to pin51 1.8V
1. These capacitors are used to reduce the slew rate of AUX CH to close to pin1 close to pin21
meet the DP V1.4 AUX CH requirement.
2. These capacitors are mandatory for HBR3 application, for HBR2
and lower, the caps are optional. VDD0.9_LEX
1.8V C316 C298 C292
3. Both the upstream and downstream port need to add the
capacitor for HBR3 application.
1000p_50V_X7R_04
W/_TYPE_C+DP
0.1u_6.3V_X5R_02
W/_TYPE_C+DP
1u_6.3V_X5R_02
W/_TYPE_C+DP
MDP_AUX SBU1_J L7 HCB1608KF-300T60 C290 0.1u_6.3V_X5R_02
W/_TYPE_C+DP
B.Schematic Diagrams
P/N = 6-19-31001-275 C289 3.3V
DCR = 0.04ohm C330
C332 C422 Impedance = 125ohm
Rated Current = 3A
18p_25V_NPO_02 18p_25V_NPO_02 W/_TYPE_C+DP 1u_6.3V_X5R_02 1000p_50V_X7R_04 C335 1u_6.3V_X5R_02
W/_TYPE_C+DP W/_TYPE_C+DP
MDP_AUX# SBU2_J W/_TYPE_C+DP W/_TYPE_C+DP W/_TYPE_C+DP
C309 1000p_50V_X7R_04
W/_TYPE_C+DP
20190617 Analogix recommend
10
41
21
51
22
32
48
60
11
39
54
MDP_AUX
R316 1M_1%_04
Sheet 18 of 43
1
3.3V U18
W/_TYPE_C+DP Note:
DVDD09_10
DVDD09_41
AVDD09_21
AVDD09_51
AVDD09_1
VDD18_22
VDD18_32
VDD18_48
VDD18_60
VDD_IO_11
VDD_IO_39
VDD33
MDP_AUX# AC capacitors for DP max=
R317 1M_1%_04
W/_TYPE_C+DP
main link should be put 0.0096mA
C
From
2
2
MDP_D0
MDP_D#0
close to DP source
C310
C311
0.1u_10V_X7R_04
0.1u_10V_X7R_04
W/_TYPE_C+DP
W/_TYPE_C+DP
55
56 ML0P
ML0N
max=
509mA max=
TX1P
TX1N
19
20
TX_1_P 20
TX_1_N 20
TX1
C
USB / DP MUX
C314 0.1u_10V_X7R_04 W/_TYPE_C+DP 58 16
ANX7440
2 MDP_D1 1.1mA RX_1_N 20
INTEL C315 0.1u_10V_X7R_04 W/_TYPE_C+DP 59 ML1P RX1N 17 RX1
2 MDP_D#1 ML1N RX1P RX_1_P 20
C325 0.1u_10V_X7R_04 W/_TYPE_C+DP 2 Analogix Semi
DIFF=85ohm, L<6" 2 MDP_D2 ML2P
C326 0.1u_10V_X7R_04 W/_TYPE_C+DP 3
2 MDP_D#2 ML2N
C327 0.1u_10V_X7R_04 W/_TYPE_C+DP 5 PWR Rail= 24 TX_2_P 20
2 MDP_D3 ML3P TX2P TX2
C328 0.1u_10V_X7R_04 W/_TYPE_C+DP 6 AVDD09 23 TX_2_N 20
2 MDP_D#3 ML3N TX2N
W/_TYPE_C+DP
PWR Rail= 26 RX_2_N 20 D02 common design 0402 to 0201
MDP_AUX C329 0.1u_10V_X7R_04 MDP_AUX_L 8 RX2N 27
From INTEL 2 MDP_AUX MDP_AUX# MDP_AUX_L# 9 AUXP
AVDD09
RX2P RX_2_P 20 RX2
C331 0.1u_10V_X7R_04
DIFF=90ohm, L<6" 2 MDP_AUX# AUXN SBU1_J
W/_TYPE_C+DP 34 W/_TYPE_C+DP C291 0.1u_6.3V_X5R_02 SBU1_J 19
SBU1 33 W/_TYPE_C+DP C288 0.1u_6.3V_X5R_02 SBU2_J
SBU2 SBU2_J 19
52
From RX
20 USB3_2RXN_R
53 SSTXN 1.8V
20 USB3_2RXP_R SSTXP
INTEL 20 USB3_2TXN_R
49
SSRXN PWR Rail= PULL_1
45 W/_TYPE_C+DP R272 100K_04
TX 50 VDD33 44 W/_TYPE_C+DP R273 100K_04
DIFF=85ohm, L<5" 20 USB3_2TXP_R SSRXP PULL_2
600ohm,
7 1.3A,
1.8V 1.8V 19 ANX7440_POW ER_EN POWER_EN PWR Rail= D02 common design 0603 to 0201
28 DCR=0.15ohm
TEST_R VDD_IO 14 L13 HCB1005KF-121T20
VIN
MSTR_SDA_744038 C337 C338 C333 C336 P/N = 6-19-31001-275
DCR = 0.1ohm
R267 R266 19 MSTR_SDA_7440 MSTR_SCL_744037 SDA Compatible w/3.3V input Impedance = 120ohm W/_TYPE_C+DP
Rated Current = 2A
19 MSTR_SCL_7440 SCL 1000p_50V_X7R_04 0.1u_6.3V_X5R_02 10u_6.3V_X5R_06 22u_6.3V_X5R_06
*4.7K_04 4.7K_04 W/_TYPE_C+DP W/_TYPE_C+DP W/_TYPE_C+DP W/_TYPE_C+DP
B OP_MODE_1/O MODE ANX7440_OP_MODE_0 B
W/_TYPE_C+DP W/_TYPE_C+DP 43 W/_TYPE_C+DP ESR<20mOhm.
00 Disabled ANX7440_OP_MODE_1 42 OP_MODE_0 Internal DC-DC 0.9v 13 Output L12 ahp252012ra-xxxm VDD0.9_LEX
01 USB3(default) OP_MODE_1 output: Maximum 500mA VX AHP252012RA-3R3M GND_DCDC
10 DP ANX7440_FLIP 29 15 P/N = 6-19-41001-049
11 USB3 + DP FLIP PWR Rail= VFB
R275 R274 Internal 45K ohm pull-down. VDD_IO Chock chooses 3.3uH;
ANX7440_I2C_ADR_SEL0 36 >500mA
ANX7440_I2C_ADR_SEL1 I2C_ADR_SEL0 C334
4.7K_04 *4.7K_04 35 DCR<100mOhm. C317
I2C_ADR_SEL1 12 0.1u_6.3V_X5R_02 22u_6.3V_X5R_06
W/_TYPE_C+DP W/_TYPE_C+DP VGND W/_TYPE_C+DP W/_TYPE_C+DP
W/_TYPE_C+DP
40
R269 R270 TEST_EN Signal GND and
3
2
AVSS_18
AVSS_25
AVSS_57
AVSS_4
*4.7K_04 *4.7K_04
R283 X2 GND_DCDC must be
DVSS
W/_TYPE_C+DP
19001-X-015-3 D02 Main vs 2nd change separated. They
1M_04 W/_TYPE_C+DP
ANX7440_I2C_ADR_SEL0 are connected at
1.8V W/_TYPE_C+DP 6-22-24R00-1BB
ANX7440_I2C_ADR_SEL1
a single point.
W/_TYPE_C+DP
W/_TYPE_C+DP ANX7440QN-CB-R
18
25
57
61
4
4
1
PCB Footprint = qfn60-7x7mmb-1 20190617 R309 0_06
R277 R278 C299 15p_50V_NPO_04
R293 W/_TYPE_C+DP
W/_TYPE_C+DP
FLIP: R314 0_06
4.7K_04 4.7K_04
W/_TYPE_C+DP
USB Typc-C Orientation: *4.7K_04 W/_TYPE_C+DP
0=normal, 1=flipped W/_TYPE_C+DP
A ANX7440_FLIP GND_DCDC A
CC1 detection is normal
or
CC2 detection is flipped R292
ANX7411, Type-C
5 4 3 2 1
20190617 Analogix recommend
7411_AVDD33
W/_TYPE_C+DP
DVDD_IO L10 HCB1005KF-121T20
P/N = 6-19-31001-275
20190617 Analogix recommend
DVDD_IO TYPE-C (USB3.1 Gen2+DP)
DCR = 0.1ohm C320 C318 C319
Impedance = 120ohm C300 C305 C294
Rated Current = 2A
5V
close to connector TYPE-C_VBUS
1u_6.3V_X5R_02 0.1u_6.3V_X5R_02 1000p_50V_X7R_04
W/_TYPE_C+DP W/_TYPE_C+DP W/_TYPE_C+DP
1u_6.3V_X5R_02 0.1u_6.3V_X5R_02 1000p_50V_X7R_04
U32
W/_TYPE_C+DP W/_TYPE_C+DP W/_TYPE_C+DP
5
VIN VOUT
1 3A
15
24
19
U19
7
C443 C438
3.3V W /_TYPE_C+DP DVDD_IO 2
AVDD33
AVDD33
DVDD_IO
DVDD_IO
0.1u_25V_X7R_06
10u_6.3V_X5R_06 GND
D
VBUS_LDO3.3V D26 A C SS1040WG 20190708 D
4 3
D25 A C SS1040WG 20190708 R483 *10K_04 EN OC#
7mA 5V VCONN_POWER is the power source for VCONN: 3.3V
374uA 1) VCONN Voltage range [3.6V, 5.5V]. SY6861A1AAC
W /O_TYPE_C+DP
W /_TYPE_C+DP 2) Internal VCONN Switch: Iout Max 400mA, PCB Footprint = M-SOT23-5
Rdson Max 1.2 ohm. 5V/3A/50m ohm
3) VCONN Minimum power is 1W. R473 0_04
20 ASM1543_PW R_EN W /_TYPE_C+DP=6-02-68611-9C0, W /O=6-02-62881-9C0
W/_TYPE_C+DP If DP Alternate Mode is supported,
VCONN power is up to 1.5W. W /O_TYPE_C+DP
R297 100K_04 8 TYPEC_SOURCE_CTRL
AUXP R481 0_04
9
AUXN W/_TYPE_C+DP
21 11 D02 modify
2 ANX7411_HPD HPD Int. PD 100K SBU1
B.Schematic Diagrams
PWR Rail=DVDD_IO 10
SBU2 C321 C313 C322
PD Function ᶲ SY6861A1AAC 6-02-68611-9C0
R296 0_04 7411_TEST_R 14 TYPEC_CC1
6 ANX7411_TEST_R
W/_TYPE_C+DP CC1 1000p_50V_X7R_04 0.1u_6.3V_X5R_02 10u_6.3V_X5R_06 䃉 PD ᶲ SY6288E1AA C 6-02-62881-9C
0
W/_TYPE_C+DP W/_TYPE_C+DP W/_TYPE_C+DP
16
DVDD_IO VCONN_POWER
2
TEST_R
CC2
13 TYPEC_CC2
DVDD_IO
USB+DP TYPE C Connector
Sheet 19 of 43 R287 R286
PWR Rail=DVDD_IO
TYPE-C_VBUS
C410
22u_25V_X5R_08
22u_25V_X5R_08
26
C M_SDA R280 *0402_short INTP_OUT 6 C
PWR Rail=DVDD_IO W/_TYPE_C+DP J_TYPEC+DP1
SMB_DATA_7411 MSTR_SCL_7440 TYPE-C_VBUS A1 B12
22 27 GND GND
TYPE-C_VBUS SMB_CLK_7411 23 CFG_SDA PWR Rail=DVDD_IO M_SCL
CFG_SCL PWR Rail=DVDD_IO TYPEC_TX1+_J A2 B11 TYPEC_RX1+_J
TYPEC_TX1-_J A3 TX0_P RX0_P B10 TYPEC_RX1-_J
D02 modify 28 25 INTP_OUT_R TX0_N RX0_N
34 SINK_CTRL TYPEC_SOURCE_CTRL SINK_CTRL Int. PD 100K INTP_OUT
4 R299
SOURCE_CTRL PWR Rail=DVDD_IO C406 1u_25V_X5R_06 A4 B9 C405 1u_25V_X5R_06
R310 PWR Rail=DVDD_IO 348K_1%_06 VBUS VBUS
10K_06 6-13-34831-28C TYPEC_CC1_J A5 B8 TYPEC_SBU2_J
W/_TYPE_C+DP W/_TYPE_C+DP CC1 SBU2
3 5 TYPEC_U2D+ TYPEC_U2D-
TEST_EN VBUS_SENSE A6 B7
TYPEC_U2D- A7 USB2_P_T USB2_N_B B6 TYPEC_U2D+
D
CGND
CGND
CGND
CGND
7411_AVDD33
1 6 20190612 A12 B1
VSS
I2C_ADR_1 NC 17
PWR Rail=DVDD_IO DVDD_IO GND GND
NC
ANX7411QN-AC-R
GND1
GND2
GND3
GND4
R301
29
UCF3T-21S01-0P01
PCB Footprint = qfn28-4x4mmc-1
PCB Footprint = ucf3t-21xxx-xxx1
4.7K_04 W/_TYPE_C+DP
ROLE_SELECT pin:
W/_TYPE_C+DP
P/N = 6-21-B4D00-024
Logic 1: DRP Mode.
Logic 0: DFP Mode. R276 R268
R294 0_04
NC: UFP Mode. ANX7440_POW ER_EN 18 1.8K_1%_04 1.8K_1%_04
B W/_TYPE_C+DP W/_TYPE_C+DP W/_TYPE_C+DP B
I2C_ADR_1 pin: Connected to AP or EC as UART TXD:
R295 1. Don't care before internal reset released.
R302
2. Used to config the I2C address as reset is released. MSTR_SDA_7440
*4.7K_04 4.7K_04 3. Can be configured to UART output. MSTR_SDA_7440 18
W/_TYPE_C+DP W/_TYPE_C+DP 4. Can be configured to GPIO. MSTR_SCL_7440
MSTR_SCL_7440 18
R204 220K_1%_04
R198 220K_1%_04 D22
D02 modify
24 SMD_PD74XX_EC
R281
R282
0_04
0_04
W/_TYPE_C+DP
W/_TYPE_C+DP
USB2.0 RX2
20
20
TYPEC_RX2+
TYPEC_RX2-
1
2
3
10
9
8
TYPEC_RX2+_J
TYPEC_RX2-_J
24 SMC_PD74XX_EC 4 7 TYPEC_TX1-_J
20 TYPEC_TX1- 5 6 TYPEC_TX1+_J
USB2.0 from PCH D37 TX1 20 TYPEC_TX1+
DIFF= 85ohm, L=3"~12"
10 1 TYPEC_U2D- ESD73034D
7 USB_PN2 TYPEC_U2D+
3.3V R526 10K_04 W/_TYPE_C+DP
7 USB_PP2 9 2 PCB Footprint = dfn10-2_5x1mm-short
8 3
TYPEC_CC1_J R471 220K_1%_04
20 ASM1543_CC1 7 4
24 EC_SMD_EN# 6 5 TYPEC_CC2_J R468 220K_1%_04 D39
20 ASM1543_CC2
ESD73034D 1 10 TYPEC_RX1-_J
G 2
20 TYPEC_RX1- TYPEC_RX1+_J
RX1 2 9
G
20 TYPEC_RX1+
3 8
6 I2C1_SDA
SMB_DATA_7411
ESD 20 TYPEC_TX2-
4 7 TYPEC_TX2-_J
TYPEC_TX2+_J
6
D40 TX2 5 6
TYPEC_CC1 TYPEC_CC1_J 20 TYPEC_TX2+
S
A 6 5 A
D
5
G
34 TYPE-C_VBUS
S
D
D
Q44A MTDK3S6R Q44B MTDK3S6R 24,34 VBUS_LDO3.3V Size Document Number Rev
W/_TYPE_C+DP W/_TYPE_C+DP 17,20,29,30,32,33,37
2,6,9,17,18,20,22,26,27,29,30,33,35,36,37
5V
3.3V A3 NL40CU 6-71-NL4C0-D02 D02
B - 20 ANX7411, Type-C
Schematic Diagrams
ASM1543
5 4 3 2 1
D D
B.Schematic Diagrams
ASM1543 TYPEC CON
PCH
Colay Colay
Sheet 20 of 43
ASM_3.3V 3.3V
C
ANX7440 USB3.1 Gen2 Port2 TYPE-C L22 . HCB1608KF-121T30
W /O_TYPE_C+DP
C
ASM1543
ASM_5V 5V
ASM_3.3V
ASM_3.3V ASM_5V L20 . HCB1608KF-121T30
W /O_TYPE_C+DP
VCC2
MODE_SEL
CC_RDY#
HC_RDY#
MC_RDY#
GNDA3
GND
VCONN_EN
PCH PWR_EN
DIFF= 80ohm, L<5" 1 24 A_URXN_SW 1 W /O_TYPE_C+DP R470 0_04
USB3_RX2_NJ I_SEL0/MUX_EN# DA_a1 A_URXP_SW 1 TYPEC_RX1- 19 RX1
R477 0_04 W /O_TYPE_C+DP 2 23 W /O_TYPE_C+DP R469 0_04
7 USB3_2RXN USB3_RX2_PJ DA_a DA_b1 A_UTXN_SW 1 TYPEC_RX1+ 19
RX R461 0_04 W /O_TYPE_C+DP 3 22 W /O_TYPE_C+DP C430 0.22u_10V_X5R_04
7 USB3_2RXP DA_b DB_a1 A_UTXP_SW 1 TYPEC_TX1- 19
4 21 W /O_TYPE_C+DP C426 0.22u_10V_X5R_04 TX1
5 GNDA1 DB_b1 20 A_URXN_SW 2 W /O_TYPE_C+DP R445 0_04 TYPEC_TX1+ 19
USB3_TX2_NJ VCC1 DA_a2 A_URXP_SW 2 TYPEC_RX2- 19
7 USB3_2TXN R449 0_04 W /O_TYPE_C+DP 6 19 W /O_TYPE_C+DP R444 0_04 RX2
B TX USB3_TX2_PJ DB_a DA_b2 A_UTXN_SW 2 TYPEC_RX2+ 19 B
7 USB3_2TXP R448 0_04 W /O_TYPE_C+DP 7 18 W /O_TYPE_C+DP C416 0.22u_10V_X5R_04
8 DB_b DB_a2 17 A_UTXP_SW 2 W /O_TYPE_C+DP C415 0.22u_10V_X5R_04 TYPEC_TX2- 19
TX2
ROLE_SEL
DFP_CC1
VCONN
GNDA2
CC1
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Title
ASM1543 / ANX CO-LAY
Size Document Number Rev
A3 NL40CU 6-71-NL4C0-D02 D02
Date: Friday, August 16, 2019 Sheet 20 of 44
5 4 3 2 1
ASM1543 B - 21
Schematic Diagrams
D
FOR 15" C308
2A
R288
S
Q21
D 2A
R289 D
G
1K_04 AO3415 4.7K_04
4.7u_6.3V_X5R_04 FOR 15" FOR 15" FOR 15"
FOR 15"
R307
2.7K_04
FOR 15"
RGBKBSW _R R517 0_06 KBZONE_R
D
FOR 15"
Q40 Q20
G MTA90N03ZN3 G 2SK3018S3
24 EC_PW M_LEDKB_R 24 EC_PW M_LEDKB_P
B.Schematic Diagrams
S
RGBKBSW _G R516 0_06 KBZONE_G
D
FOR 15"
VDD3
Q39
G MTA90N03ZN3
24 EC_PW M_LEDKB_G
FOR 15" J_RGB1
S
RGBKBSW _B R518 0_06 KBZONE_B
R117
1
Sheet 21 of 43
D
FOR 15"
*100K_04 2
FOR 15"
Q41 FOR 15" 3
R290 1K_04 LED_KB_PIN4
G MTA90N03ZN3 4
24 EC_PW M_LEDKB_B R291 100_04 RGBKB-DET#_R
FOR 15" 24 RGBKB-DET# KBZONE_B 5
S
C
FOR 15" KBZONE_R 6 C
KBZONE_G 7
8
FP225H-008S11M
fp225h-008gxxxm_r
P/N = 6-20-94K30-108
FOR 15"
LED
D02 change to H active
BAT LED
FOR 14" 3.3VS 3.3VS
LED_BAT_CHG_R
24,29 LED_PW R NUM
CAPS
POWER ON LOCK
1
LOCK LED_BAT_FULL_R
R1 R2 R3 LED
LOCK LED LED
D4 2.7K_04 D02 BCN update 2.7K_04 D02 BCN update 2.7K_04 D02 BCN update
*AVL18S02015 FOR 14"
B FOR 14" B
R31 R30
2
D1 D2 D3
330_04 330_04
A C A C A C
1
P/N = 6-52-57301-022 P/N = 6-52-57301-022 P/N = 6-52-57301-022 D10
PCB Footprint = RY-SP190YG34-5M PCB Footprint = RY-SP190YG34-5M PCB Footprint = RY-SP190YG34-5M RY-SP155HYYG4-1
SG
LED COLOR = W HITE LED COLOR = W HITE LED COLOR = W HITE PCB Footprint = 15-22SURSYGC_TR8A
Y
FOR 14" FOR 14" FOR 14" P/N = 6-52-55002-04E
LED COLOR = GREEN/YELLOW
D7 D8
2
A C A C
*ESD73034D
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Title
[21] LED KB / LED
5,6,8,9,12,22,23,24,25,26,29,30,31,32,33,35,37,38 VDD3 Size Document Number Rev
2,5,6,7,8,9,14,15,16,17,23,24,26,29,30,35,37 3.3VS
16,22,23,29,30 5VS A3 NL40CU 6-71-NL4C0-D02 D02
Date: Monday, September 23, 2019 Sheet 21 of 44
5 4 3 2 1
D
FOR 15" HDD RTD3 POWER FOR 15" HDD CON D
J_HDD1
PJ45 1 2 3mm
FOR 15" HDD_W /O_RTD3 1 SATA_TXP0 C450 0.01u_16V_X7R_04 FOR 15"
2 SATA_TXN0 SATATXP0 7 SATA_5VS
C451 0.01u_16V_X7R_04 FOR 15" SATATXN0 7
3
5VS SATA_5VS 4 SATA_RXN0 C453 0.01u_16V_X7R_04 FOR 15"
5 SATA_RXP0 SATARXN0 7
2.5A U34 C452 0.01u_16V_X7R_04 FOR 15" SATARXP0 7
5 1 2.5A 6
IN OUT 7 R514
8 SATA_5VS
C449 2
GND C458 9 C454 C455 C457 C456 220_06
10u_6.3V_X5R_04 4 3 10 FOR 15"
B.Schematic Diagrams
EN OCB 0.1u_6.3V_X5R_02
FOR 15" HDD_W /_RTD3
FOR 15" HDD_W /_RTD3
0.1u_6.3V_X5R_02 1u_6.3V_X5R_02 22u_6.3V_X5R_06 22u_6.3V_X5R_06 B Y ἧ䓐䘬廠↢暣 ⡻ 婧㔜 ,
SY6288E1AAC FP225H-010S10M
FOR 15" FOR 15" FOR 15" FOR 15" ὅ≇ 䌯 ( 旣 ῤ& ⊭ 墅⣏⮷ )
R519 5V/3A/50m ohm PCB Footprint = FP225H-010-xxxM
D
3.3V FOR 15" HDD_W /_RTD3 P/N = 6-20-94K10-010 Q42
FOR 15"
4.7K_04
G
FOR 15" HDD_W /_RTD3 30,33 SUSB
2SK3018S3
Sheet 22 of 43
S
FOR 15"
6 SATA_PW R_EN FROM PCH
U11
W /_TPM R203 4.7K_04 TPM_GPIO 6 1
GPIO0 VDD 8
W /_TPM R213 4.7K_04 TPM_PP 7 VDD 22 C199 C240 C200
PP VDD
B TPM_RST# 17 23 C239 0.1u_6.3V_X5R_02 0.1u_6.3V_X5R_02 1u_6.3V_X5R_02 B
RST# VSS_3 W /_TPM W /_TPM W /_TPM
TPM
6 TPM_PIRQ# 18 3 0.1u_6.3V_X5R_02
PIRQ# NC_1 4
NC_2 W /_TPM
5 TPM_SPI_CLK R210 49.9_1%_04 W /_TPM 19 5
SPI_CLK NC_3 10
20 NC_4 11
5 TPM_SPI_CS2# SPI_CS# NC_5 12
R212 NC_6
49.9_1%_04 W /_TPM 21 13
5 TPM_SPI_MOSI SPI_MOSI NC_7 14 VDD_TPM
R229 NC_8
5 TPM_SPI_MISO 49.9_1%_04 W /_TPM 24 15
SPI_MISO NC_9 16
NC_A 25
NC_B C238
R211 20K_04 W /_TPM 26
NC_C 27 0.1u_6.3V_X5R_02
R202 10K_04 W /_TPM 2 NC_D 28 W /_TPM
VDD_TPM VSS_1 NC_E
9 29
32 VSS_2 NC_F 30
33 VSS_4 NC_G 31
GND NC_H
SLB9670VQ F/W 7.85 W /_TPM
D02 BCN update
VDD_TPM
5
A A
1
9,24,25,26,29 BUF_PLT_RST# 4 TPM_RST#
2
U9
*TC7SZ08FU
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
3
W /_TPM
5,6,8,9,12,21,23,24,25,26,29,30,31,32,33,35,37,38 VDD3
4,5,6,7,8,9,12,23,30,33 3.3VA Title
R201 0_04 W /_TPM 16,21,23,29,30 5VS [22] SATA HDD ,TPM
2,6,9,17,18,19,20,26,27,29,30,33,35,36,37 3.3V
Size Document Number Rev
A3 NL40CU 6-71-NL4C0-D02 D02
Date: Thursday, September 05, 2019 Sheet 22 of 44
5 4 3 2 1
Audio Codec
5 4 3 2 1
PC BEEP MIC1_VREFO_L
1u_6.3V_X5R_02
1u_6.3V_X5R_02
2.2u_6.3V_X5R_04
R409 *4.7K_04 ANALOG DIGITAL
D38 C249 SLEEVE
BAT54CS3 FOR VOLUMN RING2 Layout trace > 40 mil , 5VS_AUD L6 5VS
ADJUST
24 KBC_BEEP
R419 0_04 BEEP 1 A
C 3 BEEP_A R222 4.53K_1%_04 BEEP_C
0.1u_6.3V_X5R_02
C250
suggest to implement shapes. HCB1005KF-121T20
1 2
D 2 A D
6 PCH_SPKR D02 change AUDG
*100p_25V_NPO_02
C245
1
C277
C276
6-06-00543-021 PDA bug C246 C244 C243 D24
R462
C275
C248
4.7K_04
2.2u_6.3V_X5R_04 0.1u_6.3V_X5R_02 2.2u_6.3V_X5R_04 10u_6.3V_X5R_06 15KV/0.2PF CESD0201UC5VB-M
100p_25V_NPO_02 Pin27 Pin27
36
35
34
33
32
31
30
29
28
27
26
25
3.3VS U15
Moat
2
3.3VS
LINE1-L/RING2
HPOUT-L
AVSS1
AVDD1
HP-OUT-R
MIC1-VREFO
CBP
CBN
CPVEE
VREF
MIC-CAP
LINE1-R/SLEEVE
AUDG
C282 C283
0.1u_6.3V_X5R_02 AUDG 37
AVSS2 I2S_DIN
24 R463 Codec AVDD ( Placement near Audio Codec)
4.7u_6.3V_X5R_04 0_06
COMMON NA 38 23 LINE1-VREFO
B.Schematic Diagrams
HVDD(3.3V) LINE1-VREFO
C441 2.2u_6.3V_X5R_04 39 22 C215 2.2u_6.3V_X5R_04
5/8 follow design common AVDD2 LDO2-CAP AUX mode/LINE1 JD AUDG
1.5VS
AUDG AUDG R503 0_04 40 21 R221 100K_04
C445 AVDD2 LDO1-CAP
ALC293D-CG
2.2u_6.3V_X5R_04
41 20 C216 4.7u_6.3V_X5R_04 HEADPHONE_R
5VS PVDD1 MIC1-R
C286 C440 42
SPKOUTL+ 19 C217 4.7u_6.3V_X5R_04 HEADPHONE_L
3.3VS SPK-OUT-L+ MIC1-L
Sheet 23 of 43 㬌 䳬 䶂 嶗 㙓㗪 䓐 ᶵ ᶲ ĭ 㓭⃰ὅ䄏⺈⓮㊯䣢㍍
⛘
R509
2.2u_6.3V_X5R_04 0.1u_6.3V_X5R_02 SPKOUTL-43
44
SPKOUTR-
SPK-OUT-L-
SPK-OUT-R-
QFN 6x6 I2S_LRCK
I2S_DOUT
18
17
LINE1-VREFO R465
R464
2.2K_04
2.2K_04
D41 (Include Thermal pad)
Audio Codec C AZ_RST#_R
R501
0_04
BAT54AS3
2
A
3
10K_04
R262 0_04
45
SPKOUTR+
46
SPK-OUT-R+ I2S_SCLK
16
15
SLEEVE
RING2
R249
R248
0_04
0_04 SLEEVE_CONN 29
C
GPIO1/DMIC-DATA12
5VS PVDD2 I2S_MCLK RING2_CON 29
1
C
24 KBC_MUTE#
GPIO0/DMIC-CLK
47 14
A
0.1u_6.3V_X5R_02 C287
SPDIFO I2S_IN/I2S_OUT JD
DMIC-DATA34/GPIO2 Layout trace > 40 mil ,
D
CODEC_PD# 48 13
SDATA-OUT
Q36
EAPD+PD HP/MIC1 JD suggest to implement shapes.
LDO3-CAP
SDATA-IN
*2SK3018S3
DVDD-IO
PCBEEP
RESET#
BIT-CLK
R479 *100K_04 G 49
I2S OE
3.3VS R261 GND
DVDD
SYNC
C247 R457
D
S
*0_04
200K_1%_04
Q37 *0.1u_6.3V_X5R_02
AZ_RST#_R G *BSS138
10
11
12
1
9
S
HDA_BITCLK_R
Via hole.
HDA_SDIN0_R
BEEP_R
R456
Grounding circuit for Combo Jack 29 MIC_CLK2
29 MIC_DATA2 100K_1%_04
while system entry into S3 / S4 /S5 3.3VS
C284 AZ_RST#_R 6,23
VDD3 3.3VS *10p_25V_NPO_02
3.3VS
HDA_SYNC 6
R250 22_04 HDA_SDIN0 6
SLEEVE C278
C279 R255 22_04 HDA_SDOUT 6
R511 R512 2.2u_6.3V_X5R_04 0.1u_6.3V_X5R_02 HDA_BITCLK 6
Closed to ALC269VC2 Pins.
6
D
100K_04 *100K_04 C197 0.1u_25V_X5R_04
B Q38A
SPKOUTL- SPKOUTL-_L 40 mil B
2 G MTDK3S6R C267 C280 4R: 40mils
C442 0.1u_25V_X5R_04
S 2.2u_6.3V_X5R_04
8R: 20mils
1
22p_25V_NPO_02 L9 C302
R492 0_04 HCB1608KF-121T30
20190605 EMI D02 change *180p_50V_NPO_04 J_SPKL1
3
D
Q38B D23 PDA bug
AUDG
5 G AUDG 2
6,23 AZ_RST#_R
S
MTDK3S6R
MIC1_VREFO_L
A 1 R206 4.7K_04 HEADPHONE_L SPKOUTL+ SPKOUTL+_L 40 mil 1
3 C
4
S
HEADPHONE_L 1 6 3 4
Q33A Q33B HEADPHONE_L_DEPOP 29
reserve for RC delay to mute pop. SPKOUTR+ SPKOUTR+_R 40 mil 2
MTDK3S6R MTDK3S6R 1
3.3VS 3.3VA
5G
2
MUTE_POP# L24 C468
R443 0_04 50271-0020N-001
HCB1608KF-800T30
Q34A Q34B P/N = 6-20-43130-102
*180p_50V_NPO_04
G5
MTDK3S6R MTDK3S6R PCB Footprint = 85204-02L
G
A R442 R455 C421 A
10K_04 10K_04 HEADPHONE_R 1 6 3 4 EMI Require
HEADPHONE_R_DEPOP 29
6
D
Q32A
S
D42 2G MTDK3S6R R459 *0_04
BAT54AS3 S
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
1
3
D
30 1.5VS
24 EC_CODEC_PD# R510 0_04 2
4,5,6,7,8,9,12,22,30,33 3.3VA Title
3 5G
A
CODEC_PD# R502 0_04 1
C S 2,5,6,7,8,9,14,15,16,17,21,24,26,29,30,35,37 3.3VS
[23] AUDIO CODEC_ALC293D
4
A 16,21,22,29,30 5VS
Q32B
17,24,31,32,33,35,36,37,38 VIN Size Document Number Rev
MTDK3S6R Close to the CODEC 5,6,8,9,12,21,22,24,25,26,29,30,31,32,33,35,37,38 VDD3
A3 NL40CU 6-71-NL4C0-D02 D02
Date: Friday, August 16, 2019 Sheet 23 of 44
5 4 3 2 1
B - 24 Audio Codec
Schematic Diagrams
VDD3 EC_VDD3
VBUS_LDO3.3V R67
EC_VDD3 U4B 10K_04
D20 A C SS1040WG 20190708 EC_VDD3
LED_CAP# 21
C188 C87 C130 C176 OPTION
D19 A C *SS1040WG 20190708 (⎗ ẍ嬲 ≽ ὅE C ㍸ ὃ 䘬 EXE CL 堐
)
㛒⛐ E X E CL堐ᷕ䘬≇傥⎗ẍ 冒埴 ␥ ⎵
10u_6.3V_X5R_06 0.1u_6.3V_X5R_02 0.1u_6.3V_X5R_02 0.1u_6.3V_X5R_02 䚖⇵䓐䵈刚⫿ 橼 ẋ 堐⎗OP TI O N
KBC_AVDD D02 BCN update 100 AUTO_LOAD_PWR
L3 KBC_MUTE# 77 SSCE0#/GPG2
23 KBC_MUTE# TACH2B/GPJ1(3)
C141 . EC_VDD3 1 26
J_KB1 21 OPTION
0.1u_6.3V_X5R_02
HCB1005KF-121T20 29 CCD_EN
78 RI2#/GPD1 IT5570 OPTION 80
19 EC_SMD_EN# DAC2/TACH0B/GPJ2(3) DAC4/DCD0#/GPJ4(3) VA_EC_EN 30,32,33
R84 0_04 C160 68
3.3VS D02 modify OPTION ADC2/GPI2(3) ME_WE 6
0.1u_6.3V_X5R_02
20190624 Follow Jun. common design
A
14" K/B 15" K/B
A
114
121
127
KBC_AGND SOC_TYPE 71
11
26
50
92
74
J_14KB1 ADC5/DCD1#/GPI5(3) OPTION
3
U4A J_15KB1 72 96
21 RGBKB-DET# ADC6/DSR1#/GPI6(3) OPTION OPTION ID3/GPH3 3G_EN 27
D02 swap 76 97
VSTBY
VSTBY
VSTBY
VSTBY
VSTBY
VCC
AVCC
GPH7
VSTBY(PLL)
21 LED_BAT_FULL TACH2A/GPJ0(3) OPTION OPTION ID4/GPH4 3G_PWR_EN 27
10 58 KB-SI0 4 KB-SI0 4 98
5 LPC_AD0 EIO0/LAD0/GPM0(3) KSI0/STB# OPTION ID5/GPH5 LED_BAT_CHG 21
9 59 KB-SI1 5 KB-SI1 5 D02 modify
5 LPC_AD1 EIO1/LAD1/GPM1(3) KSI1/AFD#
8 60 KB-SI2 6 KB-SI2 6
5 LPC_AD2 EIO2/LAD2/GPM2(3) KSI2/INIT# SMC_PD74XX_EC
7 61 KB-SI3 8 KB-SI3 8 115
5 LPC_AD3 EIO3/LAD3/GPM3(3) KSI3/SLIN# SMD_PD74XX_EC SMCLK1/GPC1 OPTION
13 62 KB-SI4 11 KB-SI4 11 116 56 KB-SO16
5 PCLK_KBC ESCK/LPCCLK/GPM4(3) KSI4 SMDAT1/GPC2 KSO16/SMOSI/GPC3(3)
6 63 KB-SI5 12 KB-SI5 12 118 57 KB-SO17
5 LPC_FRAME# ECS#/LFRAME#/GPM5(3) KSI5 9 SLP_SUS# SMDAT2/PECIRQT#/GPF7(3) KSO17/SMISO/GPC5(3)
5 LPC 64 KB-SI6 14 KB-SI6 14
5 SERIRQ ALERT#/SERIRQ/GPM6(3) KSI6 OPTION OPTION
22 65 KB-SI7 15 KB-SI7 15 79
9,22,25,26,29 BUF_PLT_RST# ERST#/LPCRST#/GPD2 KSI7 OPTION DAC3/TACH1B/GPJ3(3) SLP_S0# 9,35
K/B MATRIX 24
KBC_WRESET# 21 EC_PWM_LEDKB_P PWM0/GPA0 OPTION
D12 C A 14 36 1 1 31
P/N = 6-20-94K00-024
9,38 AC_PRESENT RXD/SIN0/PWUREQ#/BBO/SMCLK2ALT/GPC7(3) KSO4/PD4 EC_PCH_DPWROK 9
18 41 KB-SO5 10 KB-SO5 10 2
38 AC_IN# RI1#/GPD0(3) KSO5/PD5 GPJ7 EC_CODEC_PD# 23
GPIO 42 KB-SO6 13 KB-SO6 13 128 EC_GPIO 35
8,32,37 CPU_C10_GATE# KSO6/PD6 GPJ6
43 KB-SO7 16 KB-SO7 16 28
P/N = 6-21-94200-026
B.Schematic Diagrams
21,29 LED_PWR KSO7/PD7 29 CPU_FANPWM PWM2/GPA2
15 44 KB-SO8 17 KB-SO8 17 29 R63 *10K_04
2 SMI# ECSMI#/GPD4(3) KSO8/ACK# 25 WLAN_PWR_EN PWM3/GPA3 OPTION
23 45 KB-SO9 18 KB-SO9 18 30
2 SCI# ECSCI#/GPD3 KSO9/BUSY 9 PCH_PWROK_EC SMCLK5/PWM4/GPA4
46 KB-SO10 19 KB-SO10 19
D02 modify IT5570 KSO10/PE
KSO11/ERR#
51 KB-SO11 20 KB-SO11 20
52 KB-SO12 21 KB-SO12 21 IT5570E-128/CX
KSO12/SLCT 53 KB-SO13 22 KB-SO13 22 PIN128劍ᶵ㗗ἧ䓐 ⢾ 悐 c r ys t
al ,
KSO13 54 KB-SO14 23 KB-SO14 23 1. 劍
ᶵ䓐 䨢P
I N 炻 暨 PUL L D O
WN ,
KSO14 55 KB-SO15 24 KB-SO15 24 2. 劍
䁢GPI O PI 暨 ὅ
N ≇傥 PU LL UP OR O
W
DN.
KSO15 KB-SO16 25
24,38 BAT_DET
24,38 BAT_VOLT
2 THERM_VOLT
BAT_DET
BAT_VOLT
THERM_VOLT
TOTAL_CUR
66
67
69
70
ADC0/GPI0(3)
ADC1/GPI1(3)
ADC3/GPI3(3)
ADC FSPI_3.3V
FP266H-024S10M
FOR 14"
KB-SO17 26
FP226H-026S10M
FOR 15"
DEFAULT㓡
ᶲẞ ,(⤪
㰺 㚱 ᶲẞ
, RT C便 暣 忶
⣏) Sheet 24 of 43
B 38 TOTAL_CUR ADC4/GPI4(3) EC_VDD3 B
妶
婾㗗⏎婳 EC 㓡 L o 䁢enab le 112 0.1u_6.3V_X5R_02
84 VSTBY0 107 EC ROM
VCORE
W/_TPM
34 SINK_CTRL_EC XLP_OUT 31 1Mbit
VSS
VSS
VSS
VSS
1
27
49
91
113
122
75
SI VDD
R96 ALSPI_MSO R373 33_04 W/_TPM EC_SO 2 R368
SO 3.3K_1%_04
ALSPI_CE# R374 0_04 W/_TPM EC_CE# 1 3 FDIO2
Detect USB CHARGE Function C142 CE# WP#
*20mil short-p W/_TPM
H: W/O CHAR 0.1u_6.3V_X5R_02 KBC_AGND ALSPI_SCLK R377 33_04 W/_TPM EC_SCK 6 R382
L: W/ CHAR EC_VDD3 SCK 3.3K_1%_04
4 7 FDIO3
WLAN_EN 25 Co-LAY VSS HOLD# W/_TPM
ALL_SYS_PWRGD 9,17,35
GD25D10BTIGR W/_TPM
PCB Footprint = M-SO8
R97
10K_04
W/O_CHAR D02 common design add
VDD3
KBC_MUTE# 19 SMD_PD74XX_EC
19 SMC_PD74XX_EC
VDD3 (BOT SIDE)
R185 VDD3
R87 for EC debug use J_80DEBUG1
10K_04
VDD3 őŪůġķķſĸĴ䔞 㓡ŨűŪŰ ġ ⎒傥Ūůű Ŷ ŵ ġ 䃉㱽Ű ŶűŶŵġᶼ
47K_04 U6 J_DEBUG1 ⢾ 悐 天űŶŭ ŭġ ũŪŨũ į
W/_CHAR 4
5
D18
C A R184 90.9K_1%_04 B Q8
VIN
ZD5231BS2
BTN3904
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
E
R183
2,5,6,7,8,9,14,15,16,17,21,23,26,29,30,35,37 3.3VS Title
C194 20K_1%_04
*0.1u_16V_X5R_02
EC_RSMRST#
19,34 VBUS_LDO3.3V
5,6,8,9,12,21,22,23,25,26,29,30,31,32,33,35,37,38 VDD3
[24] IT5570
30,31,38 VREG3 Size Document Number Rev
17,23,31,32,33,35,36,37,38 VIN
Custom NL40CU
6-71-NL4C0-D02 D02
WLAN
1
W LAN_3.3V
>40 mil
0.1u_6.3V_X5R_02
PIN 72, 74
C2
22u_6.3V_X5R_06
PIN 72, 74
20190528 update by common design
About REFCLK_0 38.4MHz TO PCH
CML U ES & WHL U need to connect REFCLK (38.4MHz)
75 74 CML U QS can not connect REFCLK (38.4MHz)
73 GND13 3.3V3 72
8 CNVI_W T_CLKP WT_CLKP 3.3V2 CML-U QS:*0_04
71 70
8 CNVI_W T_CLKN WT_CLKN PEWAKE1_N CML-U ES:0_04
69 68
67 GND12 CLKREQ1_N 66 WHL-U:0_04
CNVi 8 CNVI_W T_D0P
65 WT_D0P PERST1_N 64 R7 0_04 FOR WHL
8 CNVI_W T_D0N WT_D0N REFCLK0 CLKIN_XTAL_LCP 8
63 62
61 GND11 NEW PART IRQ_N(I) 60
8 CNVI_W T_D1P WT_D1P I2C CLK(O) D02 add for BT RTD3
59 58
8 CNVI_W T_D1N WT_D1N I2C DATA(IO) W LAN_EN_R
57 56 R4 0_04 W LAN_EN R528 *0_04
B.Schematic Diagrams
Sheet 25 of 43 7
7
PCIE_TXN10_W LAN
PCIE_TXP10_W LAN
C353
C354
0.1u_10V_X7R_04 PCIE_TXN10_W LAN_R
0.1u_10V_X7R_04 PCIE_TXP10_W LAN_R
37
35
33
GND7
PETN0
PETP0
CLINK_RESET
UART_RTS/BRI_DT
UART_CTS/RGI_RSP
36
34
32
CNVI_BRI_DT_R
CNVI_RGI_RSP_R
CNVI_RGI_DT_R
R16 22_04
CL_RST#1 5
CNVI_RGI_RSP
R15
6
R18
22_04 CML=22Ω, W HL=6-14-3303B-11B
WLAN
PCIE TX AC CAP NEAR PCH R17 20K_04 1.8VA CML-U:22Ω
VDD3 CLOSE TO M.2 WHL-U:33Ω
E KEY
23 22 CNVI_BRI_RSP_R R22 22_04
8 CNVI_W R_CLKP WGR_CLKP UART_RX/BRI_RSP CNVI_BRI_RSP 6
8 CNVI_W R_CLKN 21 20
R25 WGR_CLKN UART_WAKE_N CNVI_W AKE# 9
19 18
10K_04 GND5 GND4
L: CNVi 8 CNVI_W R_D0P 17 16 R21 10K_04 W LAN_3.3V
15 WGR_D0P LED2_N(OD) 14
H: W/O CNVi 8 CNVI_W R_D0N WGR_D0N PCM_OUT/CLKREQ0 CNVI_CLKREQ 6
CNVI_DET# 13 12
24 CNVI_DET# GND3 PCM_IN
8 CNVI_W R_D1P 11 10
WGR_D1P PCM_SYNC/LCP_RSTN CNVI_RST# 6
8 CNVI_W R_D1N 9 8
7 WGR_D1N PCM_CLK 6
5 GND2 LED1_N(OD) 4
7 USB_PN10 USB_DN 3.3V1 >40 mil
BLUETOOTH 3 2 R24 R27
7 USB_PP10 USB_DP 3.3V0 W LAN_3.3V
CNVi M.2 A+E KEY BT㍍USB 2. 0 P ORT 1 71.5K_1%_04 FOR WHL 75K_04
PCH-LP USB2.0 PORT-10 GND1 C15 C10
Hybrid M.2 KEY-E 2230 CML-U:NC CLOSE TO PCH
A PCH-H USB2.0 PORT-14 WHL-U:71.5K_04 A
CLOSE TO PCH
PIN 2, 4
22u_6.3V_X5R_06
PIN 2, 4
0.1u_6.3V_X5R_02
USB 暨婳 BI O S姕 ⭂ 䁢XHCI NASE0-S6701-TSH4 CNVI_RGI_RSP_R R19 *20K_04 1.8VA
ᶵ
⎗䓐 USB3 . 0 po
rt妲
嘇 㚫 忈 ㆸ B T Power Man agement Isu
e. P/N = 6-21-84300-075
PCB Footprint = nxse0-s67xx-xx64x
HEIGHT = 3mm
W LAN_EN W LAN_3.3V
The Hybrid M.2 E-Key is used for: BT_EN T2
T3 CLOSE TO M.2
1. CNVi RF(Jefferson Peak) W LAN_PW R_EN W LAN_EN R9 *10K_04
W LAN_3.3V T4 BT_EN
2. Discrete WiFi (PCIe v2.1 Gen1) T1 R8 *10K_04
3. Discrete WiGig (PCIe v2.1 Gen2) These TEST PAD put together in BOT side
CLOSE TO CONN.
4. CNVi+WiGig combo(Cedar Peak) BUF_PLT_RST# R5 100K_04
5. Qualcomm WiGig/WLAN/BT CLOSE TO M.2
combo(Sparrow) on Cannon Lake, Coffee
Lake, and Gemini Lake platform. 1.8VA
1u_6.3V_X5R_02 3 2
EN GND
UP7553PMA5-25
AP2821KTR-G1
P/N = 6-02-02821-9C0
24 W LAN_PW R_EN
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Title
[25] WLAN ( B, E KEY )
5,6,8,9,12,21,22,23,24,26,29,30,31,32,33,35,37,38 VDD3 Size Document Number Rev
12,30,33 1.8VA
A3 NL40CU 6-71-NL4C0-D02 D02
Date: Friday, August 16, 2019 Sheet 25 of 44
1
B - 26 WLAN
Schematic Diagrams
>120 mil
D R325 SSD_3.3VS D
SATAGP2 J_SSD1
L: SATA 10K_04 C339 C295 C301
H: PCIe 75 22u_6.3V_X5R_06
73 GND13 74 0.1u_6.3V_X5R_02 0.1u_6.3V_X5R_02
71 GND12 3.3V8 72 FOR OPTANE SUPPORT
R515 1K_04 PCIE_SATA 69 GND11 3.3V7 70
7 SATAGP2 PEDET(NC-PCIe/GND-SATA) 3.3V6
67 68 GND GND GND
NC18 SUSCLK(32Khz)(O) SSD_3.3VS
B.Schematic Diagrams
55 56
8 CLK_PCIE_SSD1 REFCLKP NC16
53 54 R311 0_04
8 CLK_PCIE_SSD1# REFCLKN PEWake#(IO) PCIE_SSD_WAKEUP# 9
51 52
PCIE_TXP16_SSD_C GND9 CLKREQ#(IO) PLTRST_SSD1# SSD1_CLKREQ5# 8
C459 0.22u_10V_X5R_02 49 50
7 PCIE_TXP16_SSD PCIE_TXN16_SSD_C PETp0/SATA-A+ PERST#(O)
C460 0.22u_10V_X5R_02 47 48 SSD_CLKREQ# PU 10K_04 IN PCH SIDE
7 PCIE_TXN16_SSD PETn0/SATA-A- NC15
45 46
GND8 NC14
PCIE/SATA PORT 7 PCIE_RXN16_SSD
7 PCIE_RXP16_SSD
43
41 PERp0/SATA-B- NC13
44
42
PERn0/SATA-B+ NC12
7 PCIE_TXP15_SSD
7 PCIE_TXN15_SSD
C461
C462
0.22u_10V_X5R_02
0.22u_10V_X5R_02
PCIE_TXP15_SSD_C
PCIE_TXN15_SSD_C
39
37
35
33
GND7
PETp1
PETn1
NC11
DEVSLP(O)
NC10
40
38
36
34
R313
R315
R320
*0_04
0_04
0_04
DEVSLP2 7
VDD3
Sheet 26 of 43
GND6 NC9 3IN1 24
7 PCIE_RXP15_SSD
7 PCIE_RXN15_SSD
C463 0.22u_10V_X5R_02 PCIE_TXP14_SSD_C
31
29
27
25
PERp1
PERn1
GND5
NC8
NC7
NC6
32
30
28
26
R321 0_04
80CLK 24
M Key PCIE SSD
7 PCIE_TXP14_SSD PCIE_TXN14_SSD_C PETp2 NC5
C C464 0.22u_10V_X5R_02 23 24 C
7 PCIE_TXN14_SSD PETn2 NC4
21 22
19 GND4 NC3 20
7 PCIE_RXP14_SSD
17 PERp2 NC2 18 >120 mil
7 PCIE_RXN14_SSD PERn2 3.3V5 SSD_3.3VS
15 16
C465 0.22u_10V_X5R_02 PCIE_TXP13_SSD_C 13 GND3 3.3V4 14 C341
7 PCIE_TXP13_SSD PCIE_TXN13_SSD_C PETp3 3.3V3
C466 0.22u_10V_X5R_02 11 12
7 PCIE_TXN13_SSD PETn3 3.3V2 M2M_SSD1_LED#
9 10 0.1u_6.3V_X5R_02
GND2 DAS/DSS#(I)(OD) T42
7 8
7 PCIE_RXP13_SSD PERp3 NC1
5 6 80 mils
7 PCIE_RXN13_SSD PERn3 NC0
3 4 GND SSD_3.3VS
1 GND1 3.3V1 2
GND0 3.3V0
C343
22u_6.3V_X5R_06
GND NASM0-S6701-TSH4 C296 C342
P/N = 6-21-84KW 0-075 0.1u_6.3V_X5R_02
PCB Footprint = 213maaa32xa 0.1u_6.3V_X5R_02 FOR OPTANE SUPPORT
HEIGHT = 3mm
PCB Footprint婳
䡢
娵㨇
㥳 ἧ 䓐 䘬 Co n n e c
tor
GND GND GND
B B
C344
M.2_SSD_W /_RTD3
6 GPP_C12_RTD3 1 C304 C340
PLTRST_SSD1# 0.1u_6.3V_X5R_02
4 5 1
IN OUT 0.1u_6.3V_X5R_02 0.1u_6.3V_X5R_02
2
9,22,24,25,29 BUF_PLT_RST# M.2_SSD_W /_RTD3 M.2_SSD_W /_RTD3 M.2_SSD_W /_RTD3
2
GND
3
A
3.3V R318 10K_04 4 3 A
EN OCB 5,6,8,9,12,21,22,23,24,25,29,30,31,32,33,35,37,38 VDD3
R322
M.2_SSD_W /_RTD3 2,5,6,7,8,9,14,15,16,17,21,23,24,29,30,35,37 3.3VS
U21 3A
1M_04 2,6,9,17,18,19,20,22,27,29,30,33,35,36,37 3.3V
R323 0_04 SY6288E1AAC
M.2_SSD_W /_RTD3
M.2_SSD_W /O_RTD3 R319 0_04 M.2_SSD_W /_RTD3
6 SSD1_PW R_DN#
M.2_SSD_W /_RTD3 ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Title
[26] SSD PCIE ( M KEY )
Size Document Number Rev
A3 NL40CU 6-71-NL4C0-D02 D02
3G/LTE
5 4 3 2 1
220u,6.3V,ESR=15mΩ,H=1.9mm
80 mils
J_3G1 C387 EEFCX0J221YR
+
3G/LTE 3G/LTE
3G_PW R_EN
75 74 C105 0.1u_6.3V_X5R_02 3G/LTE
73 CONFIG_2 3.3V4 72
D D
71 GND10 3.3V3 70 C86 0.1u_6.3V_X5R_02 3G/LTE
GND9 3.3V2 R112
69 68
CONFIG_1 SUSCLK(32Khz)(O) M2_SIM_DET *100_06
67 66 pin66 H= USIM present
Reset#(O)1.8V SIM Detect(O) 3G/LTE
65 64 pin66 L= USIM absent
63 ANTCTL3(I)1.8V COEX1(I/O)1.8V 62
ANTCTL2(I)1.8V COEX2(I/O)1.8V C119 PW R_ON_OFF
61 60
ANTCTL1(I)1.8V COEX3(I/O)1.8V 470p_50V_X7R_04
59 58
ANTCTL0(I)1.8V NC1 3G/LTE
57 56
GND8 NC0 M.2 3G/4G-LTE module SIM Detect Pin 66炻 R130
55 54
REFCLKP PEWake#(IO) internal 1.8V with Pull-up *12K_06
53 52 GND
REFCLKN CLKREQ#(IO) 3G/LTE
51 50
49 GND7 PERST#(O) 48
47 PETp0/SATA-A+ GPIO_4(IO)1.8V 46
45 PETn0/SATA-A- GPIO_3(IO)1.8V 44
L2 3G/LTE 43 GND6 GPIO_2(IO)1.8V 42
PERp0/SATA-B- GPIO_1(IO)1.8V
B.Schematic Diagrams
*WCM2012F2S-SHORT 41 40
3G/LTE 1 2 39 PERn0/SATA-B+ GPIO_0(IO)1.8V 38 3G_3.3V
C174 0.1u_10V_X7R_04 USB3_4TXP_C USB3_4TXP_L 37 GND5 DEVSLP(O) 36 UIM_PW R
7 USB3_4TXP USB3_4TXN_C 4 PETp1/USB3.0-Tx+/SSIC-TxP UIM_PWR(I) UIM_PW R 29
7 USB3_4TXN C175 0.1u_10V_X7R_04 3 USB3_4TXN_L 35 34 UIM_DATA
PETn1/USB3.0-Tx-/SSIC-TxN UIM_DATA(IO) UIM_CLK UIM_DATA 29
3G/LTE 1 2 33 32 C140
20190619 layout swap USB3_4RXP_L GND4 UIM_CLK(I) UIM_RST UIM_CLK 29 M2_SIM_DET
31 30
7 USB3_4RXP PERp1/USB3.0-Rx+/SSIC-RxP UIM_RESET(I) UIM_RST 29 R70
4 3 USB3_4RXN_L 29 28 0.1u_6.3V_X5R_02
7 USB3_4RXN PERn1/USB3.0-Rx-/SSIC-RxN GPIO_8(IO)1.8V *100K_04 D02 unstuff
27 26
D
L18 *W CM2012F2S-SHORT R113 *0603_short 3G/LTE
BODYSAR_N GND3 GPIO_10(IO)1.8V 3G/LTE
R400 *0_04 3G/LTE 3G/LTE 25 24 3G/LTE
S
暨冯 M .2⎴朊 *2SK3018S3 D02 unstuff
3G/LTE C
3G/LTE C
B KEY 3G/LTE
3G_EN 24
20190619 layout swap 11 10
USB_PN4_L GND2 GPIO_9/DAS/DSS#(I)(OD) R75 0_04
1 2 9 8
7 USB_PN4 USB_PP4_L USB_D- W_DISABLE#1(O) PW R_ON_OFF R131 3G/LTE
7 6 10K_04 3G/LTE
7 USB_PP4 USB_D+ Full_Card_Power_Off#(O)1.8V D02 stuff
4 3 5 4
3 GND1 3.3V1 2 80 mils
L19 3G/LTE GND0 3.3V0 3G_3.3V
1 NGFF_B
*WCM2012F2S-SHORT CONFIG_3
PCB Footprint = W CM2012F2S-short + C398 C186 C185
NASB0-S6701-TSH4 10u_6.3V_X5R_04 0.1u_6.3V_X5R_02
4G-LTE module䘬 USB 3.0 interface ㍍⇘ ㊯⭂
天
⭂
ᶨ
婳 䁢USB 3.0䘬 S IC
Por
t. EEFCX0J221YR
PCB Footprint = 213baaa32xa 3G/LTE 3G/LTE
SKYLAKE㚨
㕘
䘬 H 䲣↿ 䘬 EDS & D esign guide 䴻㰺 㚱 ⭂佑
(Rev
)
0
.
1 SSI
C 3G/LTE
port炻
ỮSKYLAK E Y 婳 U㍍⇘US B3.0 POR T.
2 P/N = 6-21-84KY0-075
䔞
ἧ
䓐 䘬 SKYLAK E-H pltafrm㗪 炻 4 G
o - LTE 䘬US
B3.
0 HEIGHT = 3mm
interface⎗ ẍ
冒埴
⭂佑 忋 ㍍ ⇘ Skylak e - H ả ỽ 䘬ᶨ ᾳUSB3.0 䘬 P o r t ⯙⎗ẍḮ ˤ
220u,6.3V,ESR=15mΩ,H=1.9mm
3G POWER
3G_3.3V
Q6
>120 mil AO3415 >120 mil
S D
3.3V
3G/LTE
B B
C69
C106
G
1u_6.3V_X5R_02
3G/LTE
C70 1u_6.3V_X5R_02 0.1u_6.3V_X5R_02
3G/LTE
3G/LTE
R62
R57
10_06
20K_1%_04
3G/LTE
3G/LTE
R56 100K_04
3
3G/LTE D
6
D Q5B
Q5A 5G MTDK5S6R
R55 0_04 2G MTDK5S6R S 3G/LTE
24 3G_PW R_EN
4
S 3G/LTE
1
3G/LTE
ADD R386,Q23 Solution For
PDA
BUG-When Battery discharge
to
shutdown, the CMOS
sometimes
loss.
A A
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Title
[27] 3G/LTE ( B KEY )
Size Document Number Rev
2,6,9,17,18,19,20,22,26,29,30,33,35,36,37 3.3V
A3 NL40CU 6-71-NL4C0-D02 D02
Date: Friday, August 16, 2019 Sheet 27 of 44
5 4 3 2 1
B - 28 3G/LTE
Schematic Diagrams
USB Type-A
5 4 3 2 1
D D
B.Schematic Diagrams
Sheet 28 of 43
C C
USB Type-A
5
U28
80 mil
1
VIN VOUT
C400 2
CB Smart CDP 10u_6.3V_X5R_04 GND C402
pin8 pin4 Function 4
EN# OC#
3 0.1u_6.3V_X5R_02
SY6288D20AAC
0 X DCP autodetect with USB_DD_ON#
2A/90mohm
mouse/keyboard wake up USB3.1 Max Trace length SY6288D20AAC: 6-02-62882-9C0
Follow Design Guide uP7549UMA5-20: 6-02-75495-9C0
1 0 S0 Charging with SDP
USB PORT Charge
VDD5
1 1 S0 Charging with CDP D02 modify
B B
If select CB pin contact to SUSB#, you can Support 80 MIL
C166 22u_6.3V_X5R_06
DCP mode and Apple-compliant devices charge in 1 2 USBVCC_CH
C167 22u_6.3V_X5R_06
S3 status. D47 15KV/0.2PF CESD0201UC5VB-M
1 2 6-24-40001-018
J_USB3_1
R166 FROM PCH D46 15KV/0.2PF CESD0201UC5VB-M
1
10K_04 USB3_1TXPC 6-24-40001-018 VBUS
9,17,30,32 SUSB# R128 *0_04 7 USB3_1TXP C394 0.1u_6.3V_X5R_02 9 GND1
W /_CHAR USB3_1TXNC SSTX+ SHIELD
W /_CHAR U5 TX C393 0.1u_6.3V_X5R_02 8 GND3
Standard-A
USB_DD_ON# 7 USB3_1TXN SSTX- SHIELD
24,30,31 DD_ON R129 0_04 8 1 D36
W /_CHAR CB PRE# USB3_1RXP 6
USB_PN1 7 2 USB_PN1_R 6 5 USB3_1RXN 5 SSRX+
7 USB_PN1 TDM DM SSRX-
7 4 7
USB_PP1 6 3 USB_PP1_R R406 USB_PN1_R 1 2 USB_PN1R 8 3 GND_D
7 USB_PP1 TDP DP 100K_04 9 2 GND4
GND
D45
2
D02 Modify
15KV/0.2PF CESD0201UC5VB-M
15KV/0.2PF CESD0201UC5VB-M
6-24-40001-018
6-24-40001-018
A A
W/O USB CHARGER
1
R407
W /O_CHAR
0_04
0_04
USB_PP1_R
USB_DD_ON#
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
24,29 USB_PW R_EN# Title
W /O_CHAR [28] USB TYPE-A(1)(CHARGER)
30,31 VDD5 Size Document Number Rev
A3
6-71-NL4C0-D02 D02
Date: Friday, August 16, 2019 Sheet 28 of 44
5 4 3 2 1
USB Type-A B - 29
Schematic Diagrams
TP_VCC
TP_VCC
Touch PAD CONN CPU FAN CONN
R508 *20mil short-p 3.3VS
R305 R306 5VS
C446 1u_6.3V_X5R_02 J_FAN1
1K_04 1K_04 J_FAN1
C447 0.1u_6.3V_X5R_02 1 4
J_TP1 I2C_SCL_TP 2
I2C_SDA_TP I2C_SCL_TP 6 C397 C395 C396
I2C_SDA_TP 6 3
1 TP_I2C_DAT_CON 1 10 I2C_SDA_TP TP_VCC
1u_6.3V_X5R_02 *4.7u_6.3V_X5R_06 10u_6.3V_X5R_04 4 1
2 TP_I2C_CLK_CON 2 9 I2C_SCL_TP
D 3 3 8 50281-00401-001 D
4 4 7 TP_DATA PCB Footprint = 88266-04_L
5 TP_DATA_CON 5 6 TP_CLK P/N = 6-20-63120-104
6 TP_CLK_CON R303 R304
7 10K_04 R507 D27 C409 100p_25V_NPO_02
8 3.3VS
D43 20190708 *ESD73034D 10K_04 10K_04 24 CPU_FANPW M
FP225H-008S11M RB751S-40C2 PCB Footprint = dfn10-2_5x1mm-short C448 C401 100p_25V_NPO_02
1
PCB Footprint = fp225h-008gxxxm_r TP_CLK 24 CPU_FANSEN
LID_SW # 24 TP_CLK TP_DATA
P/N = 6-20-94K30-108 A C *10u_6.3V_X5R_06
24 TP_DATA
D44
3.3VS R403 4.7K_04
*V15AVLC0402 TP_ATTN# 6
C306 C307
20190619 swap pin1 10K_04 R513 3.3VS 47p_25V_NPO_02 47p_25V_NPO_02
2
15" SIM CARD
B.Schematic Diagrams
Sheet 29 of 43 1
U2
VCC OUT
2 LID_SW #
LID_SW # 17,24 3.3VS
3
4
5
SIM_DET 27
UIM_CLK 27
3G_SIM
GND
C C
2
0701 J_BTN1 6 UIM_DATA 27
3
0.1u_6.3V_X5R_02 P/N = 6-02-08251-LC0 *100p_50V_NPO_02 *V15AVLC0402 NC1 2 M_BTN#
2 NC2 3
4 GND
1
FP225H-008S11M
1 3 GND
fp225h-008gxxxm 20190610 swap pin1
GND GND GND FP226H-004S10M GND
P/N = 6-20-94K30-108
GND P/N = 6-20-94A40-004 3G/LTE
䡢娵ᶲẞỵ伖 PCB Footprint = fp226H-004xxxm_r 20190612 swap pin1
FOR 15"
47p_25V_NPO_02
47p_25V_NPO_02
FP225H-02261BM 25 USB3_3RXP 7 50208-01201-001
GND
26 USB_PP5_L 1 2
Colay USB_PP5 7
R353
*100K_04
PCB Footprint = 50208-012xx-xxx_r
P/N = 6-21-64D00-112
27 PCB Footprint = W CM-2012
PCB Footprint = FP225-022-L 28 L21
USB_PN5_L 4 3 *WCM2012F2S-161T03 D28
P/N = 6-20-94K10-022 29 USB_PN5 7
30 R466 0_04 USB_PN7_C 5 6 USB_PN7_J
31 USB_PW R_EN# 24,28 USB_PP7_C 4 7 USB_PP7_J
32 3 8
33 MIC_DATA2_L 2 9 MIC_DATA2_R
34 RING2_CON 23 MIC_CLK2_L 1
SLEEVE_CONN 23 10 MIC_CLK2_R
A 35 A
36 HPOUT-JD 23
20190619 layout swap
37 *ESD73034D
38 HEADPHONE_L_DEPOP 23
HEADPHONE_R_DEPOP 23 PCB Footprint = dfn10-2_5x1mm-short
39
40
FP201H-040S10M
HEAD-PHONE ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Title
P/N = 6-20-94K20-140 AUDG GND 2,6,9,17,18,19,20,22,26,27,30,33,35,36,37 3.3V
PCB Footprint = FP201-040X1-0M
5,6,8,9,12,21,22,23,24,25,26,30,31,32,33,35,37,38 VDD3 [29] CONN,CCD&IR,FAN,T/P
2,5,6,7,8,9,14,15,16,17,21,23,24,26,30,35,37 3.3VS Size Document Number Rev
17,19,20,30,32,33,37
16,21,22,23,30 5VS
5V
A3 NL40CU 6-71-NL4C0-D02 D02
B - 30
Schematic Diagrams
5 4 3 2 1
VREG3
R236
R220 R59 PW R_SW # 24
100K_04 VREG3 6
200K_04
10K_04 D
SUSB Q4A
DD_ON# SUSB 22,33
Q15 2 G
D
D Q14 2SK3018S3 S MTDK3S6R D
D
1
2SK3018S3 R53 3 1
G PJ4 C213 47K_04 D R58
9,17,28,32 SUSB#
G DEL J9 C214 Q4B
24,28,31 DD_ON 1M_04
S
*CV-40mil *30p_50V_NPO_04 R60 5 G
2
29 M_BTN#
S
B.Schematic Diagrams
2nd source G5016
R207
VDD5
C220 U12 EM5209
EM5290
PCBfootprint:
TDFN14-2X3MM-A
C218
VDD5
R208
*100_04 5V 1.5VS
5VS *100_04
0.1u_6.3V_X5R_02 1 6 0.1u_6.3V_X5R_02 Q11 VDD3 1A V1.5 DEFAULT
1.5VS
D
IN1 IN2 SHORT
Sheet 30 of 43
Q10 2 7 U16 30mils
D
SUSB
*2SK3018S3
G
5VS 6A 13
14 OUT1 OUT2
8
9
6A 5V G DD_ON# 2 IN
GND
VOUT
R1
S
OUT1 OUT2
VBIAS
C265 NCT3705U-A
GND
GND
EN1
EN2
C204
1.8V, 1.5VS
C C203 C
1u_6.3V_X5R_04
470p_50V_X7R_04 220p_50V_NPO_04 20190611 C
R256 10K_04 VDD3_R 1 2 2 1 VDD3_R C281 R2 VOUT=1.25(1+R1/R2)
VDD3
3
5
R254
15
11
ON
3.3V
3.3V 6A
7
8
IN2
OUT2 OUT1
IN1
2
13 6A 3.3VS 3.3VS
3.3VA 2A
2
13
IN1
IN1
IN2
IN2
7
8 1A
1.8V
9 14 3.3VA OUT1 OUT2 1.8V
OUT2 OUT1 C269 14 9
C255 OUT1 OUT2
C222 C206
B 10 12 B
CT2 CT1 0.1u_6.3V_X5R_02 12 10
0.1u_6.3V_X5R_02 CT1 CT2
R264 0.1u_6.3V_X5R_02 0.1u_10V_X5R_04
VBIAS
VBIAS
GND
GND
EN2
EN1
GND
GND
R199 C254 C268 200_06
EN1
EN2
C221 C205
220p_50V_NPO_04 220p_50V_NPO_04
100_04 220p_50V_NPO_04 220p_50V_NPO_04
D
11
15
5
Q17
15
11
3
5
Q12 2SK3018S3
DD_ON_EN
D
DD_ON# G DD_ON_EN
VDD3
24,32,33 VA_EC_EN VDD3
C256
S
C257
1u_6.3V_X5R_02 C224 C208 C209
1u_6.3V_X5R_04
*0.1u_6.3V_X5R_02
*0.1u_10V_X7R_04 *0.1u_10V_X7R_04
R239 *10K_04
1.05VA_PW RGD 32
SUSB#_EN_R R240 10K_04 SUSB#_EN
C271
*0.1u_6.3V_X5R_02
23 1.5VS
24,31,38 VREG3
A A
5,6,8,9,12,21,22,23,24,25,26,29,31,32,33,35,37,38 VDD3
2,6,9,17,18,19,20,22,26,27,29,33,35,36,37 3.3V
2,5,6,7,8,9,14,15,16,17,21,23,24,26,29,35,37 3.3VS
4,5,6,7,8,9,12,22,23,33
28,31
3.3VA
VDD5
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
17,19,20,29,32,33,37 5V Title
16,21,22,23,29 5VS [30] 3V,5V,3VS,5VS, 1.8V,1.5VS
12,25,33 1.8VA Size Document Number Rev
18 1.8V A3 NL40CU 6-71-NL4C0-D02 D02
VDD3, VDD5
5 4 3 2 1
PR27 PR26
68K_1%_04 75K_1%_04
PJ44
D D
1 2 EN_3V EN_5V
PC181
*CV-40mil VIN
1000p_50V_X7R_04
20
3A
2
VREG3 PU13
2.5A
EN2
VFB2
CS2
CS1
VFB1
EN1
VIN PC186 PC33 PC187
1
4.7u_25V_X5R_08
PC152 PC81
0.1u_25V_X7R_06
4.7u_25V_X5R_08
PC185 PC34 PC29 PC159 14 + +
VDD3 1u_6.3V_X5R_04
VO1
0.1u_25V_X7R_06
4.7u_25V_X5R_08
*T55D107M025C0060
20190606 PWR
*T55D107M025C0060
4.7u_25V_X5R_08
2
3 7
PQ13 VREG3 PGOOD
PDC3908Z
PC177
PW R ASSY BOM
B.Schematic Diagrams
5
5
5
5
5
5
5
5
PC168 0.1u_10V_X7R_04
0.1u_10V_X7R_04 PQ14 8A
VDD3
6A SYS3V PL12
4 PR31 0_06 10
DRVH2 DRVH1
16 PR30 0_06 4 PDC3908Z
PW R ASSY BOM PL13 SYS5V
VDD5
3
2
1
1
2
3
BCIHP0730-4R7M BCIHP0730-2R2M
PJ11 2 1 5mm 2 1 8 18 2 1 PJ41 1 2 5mm
SW2 SW1
PC26 PC167 PQ10 PQ11 DEFAULT SHORT
DEFAULT SHORT EMC3 R1
C
5
5
5
5
5
5
5
5
+
Sheet 31 of 43
PC19
PDC3906Z 11 15 PDC3906Z EMC4 PC178 PC161
GND PAD
R1 DRVL2 DRVL1
0.1u_10V_X5R_04
220u_6.3V_6.3*4.4
220u_6.3V_6.3*4.4
*1000p_50V_X7R_04
C
PW R ASSY BOM PW R ASSY BOM PD13 *1000p_50V_X7R_04 PR160
0.1u_10V_X5R_04
VREG5
PD12 +
VCLK
PR18 4 4 30K_1%_06
VIN
PC160
CSOD140BSH
13K_1%_06
3
2
1
1
2
3
VDD3, VDD5
*100p_25V_NPO_02
*1000p_50V_X7R_04
CSOD140BSH
C EMR1 C
21
12
13
19
EMR2
A
*5.1_06
R2 TPS51275B-1RUKR *5.1_06
R2
PR165
PR28
20K_1%_06 18.7K_1%_06
PR25
200K_04
VREG5 VDD5_LDO5
VREG5
Qpxfs! po
WEE40WEE6! QXN
R258
VREG5
200K_04
D02 Modify
R263
B EN_3V5V EN_5V B
R257
6 *0402_short
200K_04 D
D02 Modify
Q19A
DD_ON_EN_VDD 2 G
Q19B 3 S MTDK3S6R
MTDK3S6R D 1
1
5 G PJ10 R265
24,28,30 DD_ON S *CV-40mil
4 1M_04
2
D02 Modify
D
CV Test
G
24 USB_CHARGE_EN
Q18
S
2SK3018S3
33 VDD5_LDO5
DMFWP!DP/!!ᙔ Ϻ ႝတ
Title
28,30
5,6,8,9,12,21,22,23,24,25,26,29,30,32,33,35,37,38
VDD5
VDD3
[31] VDD3 / VDD5
Size Document Number Rev
17,23,24,32,33,35,36,37,38 VIN
A3 6-71-NL4C0-D02 D02
24,30,38 VREG3 Date: Friday, August 16, 2019 Sheet 31 of 44
5 4 3 2 1
B - 32 VDD3, VDD5
Schematic Diagrams
VIN VDD3
0.1u_25V_X7R_06
10u_25V_X5R_08
10u_25V_X5R_08
PC141
PC142
PC153
PR146
47K_1%_04
2 9
3 IN PG 1.05VA_PW RGD 30
4 IN
IN BS
1 PR145 0_04 8A
D For CV test 5
IN
PC143 0.1u_10V_X7R_04 PL10
BCIHP-0735-0R68M-NL
V1.05 DEFAULT SHORT 1.05VA 1.05V D
PR153 V1.05_LX
10 6 1 2 PJ40 1 2 6mm
PR151 100K_04 PJ39 1 2 *CV-40mil *0_04 12 NC LX 19 PCB Footprint = BCIHP0735A
VDD3 NC LX
PU12 20
PR152
SY8288RAC LX
PC164
PC163
PC145
PC144
D02 modify
22u_6.3V_X5R_06
22u_6.3V_X5R_06
22u_6.3V_X5R_06
22u_6.3V_X5R_06
PJ37 1 2 *1mm 0_04 11
33 1.8VA_PGD EN 14
FB Vout=0.6(1+R1/R2)
VDD3
PR157 0_04 PJ42 1 2 1mm 13 20190625
24,30,33 VA_EC_EN ILMT 17 PWR MODIFY PR1 : 22.6K = 1.05V
DEFAULT 15 VCC PR1 : 17.8K = 0.95V
SHORT BYP 16 PR122.6K_1%_04
NC PR21
GND
GND
GND
PAD
PR20 PC157
B.Schematic Diagrams
*100K_04
4.7u_6.3V_X5R_06
PC156
18
21
0.1u_10V_X5R_04 Floating O.C.P 12A
PR2 PR19 PC25
PC158 PR155 *1K_1%_04 *330p_50V_NPO_04
4.7u_6.3V_X5R_06 30K_1%_04
20190625
PR154 PWR MODIFY
*100K_04
Sheet 32 of 43
C C
1.05VA, VCCST,
VCCST 1.05VA
VCCSTG VCCSTG VCCSTG
60mA+150mA(VCCPLL) = 210mA VCCST
U26 DEFAULT
1.05VA SHORT
U29 DEFAULT 20mA
2 4 VCCSTG_OUT PJ29 1 2 1mm
SHORT VIN VOUT
2 4 VCCST_OUT PJ35 1 2 1mm
VIN VOUT C388 C389 C386
*10u_6.3V_X5R_06 1u_6.3V_X5R_02 0.1u_6.3V_X5R_02
C433 C428 C420
*10u_6.3V_X5R_06 1u_6.3V_X5R_02 0.1u_6.3V_X5R_02 R436
VDD3
*33_04
R438 VDD3
*33_04
R435
Q31A *100K_04
R450
6
D *MTDK3S6R
Q35A *100K_04 VDD3
6
D *MTDK3S6R G2
VDD3
SUSB#_C10# R451 200_1%_04 1.05V_VCCSTG_EN 6 5 S
G2
1
ON VBIAS Q31B
R453 *0_04 1.05V_VCCST_EN 6 5 S
3
9,33,37 SUSC#
1
4
S
4
B B
1 3
GND NC
1 3
GND NC
FA7609A6
FA7609A6
VCCPLL_OC
VDDQ VCCSFR_OC
U46
1 6
130mA
VIN VOUT
2
C234 C235 VIN C198 17,23,24,31,33,35,36,37,38 VIN
10u_6.3V_X5R_04 *10u_6.3V_X5R_04 9 *10u_6.3V_X5R_04 VDD3 R200
VIN *33_04 4,12 1.05VA
2,10,11 VCCSTG
2,9,10,11,35 VCCST
5V 3 R227
VDD3 VBIAS *100K_04 Q13A
C236 6
D
17,19,20,29,30,33,37 5V
1u_6.3V_X5R_02 *MTDK3S6R
11,14,15,33 VDDQ
A U14 2G A
11 VCCSFR_OC
5
SN74LV1T08DCKR R241 S
1
5,6,8,9,12,21,22,23,24,25,26,29,30,31,33,35,37,38 VDD3
1 0_04
9,17,28,30,32 SUSB#
3
4 SUSB#_C10# VCCPLL_OC_EN 4 5 D
2 ON GND
8,24,37 CPU_C10_GATE# VCCPLL_OC_EN
1.8V 5G Q13B
C237 EM5201V S *MTDK3S6R ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
3
R251 *0.1u_16V_X5R_02
Title
*0_04
[32] 1.05VA/VCCST/VCCSTG
Size Document Number Rev
A3 6-71-NL4C0-D02 D02
Date: Friday, August 16, 2019 Sheet 32 of 44
5 4 3 2 1
1 2 3 4 5
VIN
0.1u_25V_X7R_06
4.7u_25V_X5R_08
4.7u_25V_X5R_08
PD7
*RB0540S2
C
G5616BRZ1U
4/12 power change , layout 㓦
ᶵ
ᶳ
PQ6 VDDQ(1.2V)
5
5
5
5
A PDC3908Z A
VDDQ_VBST PC2
DEFAULT PC70 10u_6.3V_X5R_04 19 18 PW R ASSY BOM
VDDQ_VTT VLDOIN VBST PR82 VDDQ_DRVH_R
SHORT 4
0.1u_10V_X7R_04
DEFAULT
2A
1
2
3
PJ21 2 1 2mm VTT_MEM_R 20 17 VDDQ_DRVH 0_04
VTT DRVH SHORT VDDQ
PR66
D02 pwr common design PL4
BCIHP0730-1R0M
VDDQ_R
9A PJ1 5mm
*20mil short-p 1 16 VDDQ_L 1 2 2 1
PC61 PC60 VTTGND LL
PC62
B.Schematic Diagrams
C
VTTSNS DRVL
5
5
5
5
PDC3906Z 330U_2V_D2_D
PD1
PW R ASSY BOM PC77 COMMON
0.1u_10V_X5R_04
3 14 4 20%
GND PGND *1000p_50V_X7R_04 2V
1
2
3
CSOD140BSH AL POLYMER
PR1
A
PR81 560K_1%_04 VTT_TON 9 13 VDDQ_CS 5V 3.0A@105C
VIN TON CS 0.009R
10K_1%_06 SMD_7343
*5.1_06
H=1.9mm
3.3V
1u_6.3V_X5R_04
1u_6.3V_X5R_04
VDDQ_SNS 5 8 VDDQ_S5
VDDQSNS S5 R334
1.8VA B
VDDQSET 6
VDDQSET S3
7 VTTEN
10K_04
PR68
*20mil short-p
B
PGOOD
GND
VDDQ_PW RGD 9,32
21
PR67 6.04K_1%_04
6
D
5V C347
Q25A
R328 100K_04 SUSC#_G5616 2G MTDK3S6R *0.1u_16V_X5R_02
S
1
3
1
R326 10K_04 D
5V PJ23
Q23 Q25B
5G
D
R330 2SK3018S3 MTDK3S6R *CV-40mil
9,32,37 SUSC#
10K_04 S
2
C346
R329 *0_04 G
22,30 SUSB *0.1u_6.3V_X5R_02
S
For CV test
R332
C
R327
2
*100K_04 ON
VDD3
1A
PC149
1.8VA
VDD5_LDO5
PC148 0.1u_10V_X5R_04
10u_6.3V_X5R_06 PR156 PC150
82p_50V_NPO_04
10u_6.3V_X5R_06
10u_6.3V_X5R_06
0.1u_10V_X5R_04
PC155 8 7 12.7K_1%_04 5,6,8,9,12,21,22,23,24,25,26,29,30,31,32,35,37,38 VDD3
9 GND VFB
GND
*1u_6.3V_X5R_04
24,30,32 VA_EC_EN
PR149 10K_04
PR148
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Title
Rb [33] VDDQ,VDDQ_VTT,1.8VA
10K_1%_04
Power PD Function
5 4 3 2 1
D W /O_TYPE_C+DP D
VA1
JDC_AC
J_DC_JACK1
1
3.5A PD19 A C SK540SB
2
W /_TYPE_C+DP
GND1 PC189
GND2
B.Schematic Diagrams
10u_25V_X5R_08
*10u_25V_X5R_08
D02 change
TYPE-C_VBUS
PQ16 PQ17
3.5A 7
AONS21321
8 W /_TYPE_C+DP
3
AONS21321
W /_TYPE_C+DP
3
8
7 Sheet 34 of 43
6 2 2 6
5 1 1 5
TYPEC-IN
EMC17
PR176 PC191 Power PD Function
4
0.1u_25V_X7R_06
W/_TYPE_C+DP
200K_04 *0.1u_25V_X7R_06
C C
W /_TYPE_C+DP W /_TYPE_C+DP
PR177
100K_04
W /_TYPE_C+DP
D
PQ18
G 2SK3018S3
W /_TYPE_C+DP
S
PD14
C A PR174 20K_04 G PQ19
2SK3018S3
W /_TYPE_C+DP
S
ZD5245BS2 W /_TYPE_C+DP
W /_TYPE_C+DP PR173
100K_04
W /_TYPE_C+DP
B B
19 SINK_CTRL SINK_CTRL_EC 24
PR175 10K_04 PR179 0_04
W /_TYPE_C+DP W /_TYPE_C+DP
PR178
100K_04
R279
2K_04
W /_TYPE_C+DP
38 VA1
19 TYPE-C_VBUS
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
19,24 VBUS_LDO3.3V Title
[34] PWR_PD FUNCTION
Size Document Number Rev
A3 NL40CU D02
6-71-NL4C0-D02
Date: W ednesday, August 21, 2019 Sheet 34 of 44
5 4 3 2 1
Power PD Function B - 35
Schematic Diagrams
VCore
5 4 3 2 1
VIN
PR110
VDD3
VRACPU_PWM1
VRACPU_PWM1 36
VR_VDD18
VR_EN VRACPU_PWM2
PR118
VDD3 PR113 10K_04 PJ25 2 1 *CV-40mil
3.3V VRACPU_PWM2 36
PC85 *0.1u_16V_X7R_04 VRACPU_PWM3
DEFAULT SHORT
VRACPU_PWM3 36
2M_1%_04 PR117
PJ27 1 2 1mm
9,17,24 ALL_SYS_PWRGD
PC63
PJ26
4.7_1%_06
*1mm VRAGT_PWM1
PR108 *0_04 VRAGT_PWM1 36
1
24 VR_ON PJ28 1 2 *1mm
PD8 VRASA_PWM1
VRACPU_PE VRASA_PWM1 36
PC89
1u_16V_X7R_06
PC86
A C
24 EC_GPIO
VRACPU_VINSEN
RB751S-40C2
D D
20190708
VRA_STB
133K_1%_06
0.01u_50V_X7R_04
4.7u_6.3V_X6S_06
PC92 PR112 3.3V
VRA_STB 36
100K_04
*0.1u_16V_X7R_04 VCCST
VRACPU_CS1
VRACPU_CS1 36
VRACPU_CS2
VRACPU_CS2 36
VRACPU_CS3
VRACPU_CS3 36
GND_SIGNAL
PR92
PR84
PR98 PR99 PR100
49
47
26
44
43
42
41
40
39
38
VRAGT_CS1 36
45.3_1%_04 VRASA_CS1
0.1u_10V_X7R_04
VDD18
VDD33
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
AGND
VIN_SEN
VRASA_CS1 36
*1K_1%_04
100_04
37
EN 34
PR103 0_04 35 STB
9,24 SLP_S0#
B.Schematic Diagrams
SLP_S0# VRACPU_CSUMA
PMBUS address 24,38 SMC_BAT PR102 0_04 SMC_BAT_VR 33
SCL_P
CS1
5
4
PR105
PR106
1.5K_1%_04
1.5K_1%_04
PR101 0_04 SMD_BAT_VR 32 CS2 PWR_3PH=1.5K, 2PH=1.5K, 1PH=NC
2 H_PROCHOT# 24,38 SMD_BAT SDA_P
VR_VDD18 3 PR104 1.5K_1%_04
PR94 *100_1%_04 VR_VRHOT# 31 CS3 PWR_3PH=1.5K, 2PH=NC, 1PH=NC
VRHOT# 2
9 H_VR_READY PR91 10K_1%_04 PR93 0_04 VR_VRRDY 30 CS4
3.3VS VRRDY VRAGT_CSUMB
1 PR73 1.5K_1%_04
PR70 10 H_CPU_SVIDALRT# PR86 0_04 VR_ALT# 29 CS5
ALT# 48 PR72 1.5K_1%_04 VRASA_CSUMC
30K_1%_04 VR_DSIO CS6
10 H_CPU_SVIDDAT PR87 10_1%_04 28
PWR_3PH=30K, 2PH=62K, 1PH=NC SDIO VRACPU_VDIFF
Sheet 35 of 43
PU5 6 PR96 1.47K_1%_04
10 H_CPU_SVIDCLK PR85 49.9_1%_04 VR_SCLK 27 VDIFFA
SCLK MP2979AGQKT-0020-Z
ADDRP 25
ADDR_P 7 VRACPU_VFB PR107 *0_04 PC82 *470p_50V_X7R_04
PSYS PR116 0_04 46 VFBA
VCore
38 PSYS PSYS PR95 *100_04 VCC_CORE
PR115 18.2K_1%_04 VRACPU_PE 36 8 VRACPU_VOSEN PJ24 1 2 *1mm VCC_SENSE 10
C PR69 PE VOSENA C
PC88 *0.01u_50V_X7R_04 9 VRACPU_VORTN PJ22 1 2 *1mm VSS_SENSE 10
10K_04 Psys setting base on charger spec: VRACPU_IREF VORTNA
PR71 61.9K_1%_04 24
PWR_3PH=10K, 2PH=10K, 1PH=0Ω 1. 1uA/W information IREF 10 VRAGT_VDIFF PR88 2.49K_1%_04 PR89 *100_04
2. Pmax 44W VRACPU_CSUMA 18 VDIFFB
CSSUMA
VRAGT_CSUMB 19
CSSUMB 11 VRAGT_VFB PR78 *0_04 PC67 *470p_50V_X7R_04
IMON 53.6K_1%_04: 6-13-53621-28C
107K_1%_04: 6-13-10731-28C
VRASA_CSUMC
VRACPU_IMON
20
CSSUMC
VFBB
VORTNC
VOSENC
VRASA_IMON 23 VORTNB
VDIFFC
PR61 120K_1%_04
IMONC
TEMP
VFBC
PR79 *100_04
PC65 180p_50V_NPO_04
PR60 620K_1%_04
45
14
15
17
16
PC64 33p_50V_NPO_04
VRASA_VORTN
PR75 *100_04 VCCSA
PJ17 1
PJ16 1
2 *1mm
2 *1mm
VCCSA_SENSE
VSSSA_SENSE
11
11
PR59 0_06
A A
10,36 VCC_CORE
2,9,10,11,32 VCCST
17,23,24,31,32,33,36,37,38 VIN ᙔ ! Ϻ !ႝ !တ!!DMFWP! D P
/
10,36 VCCGT Title
5,6,8,9,12,21,22,23,24,25,26,29,30,31,32,33,37,38 VDD3
11,36 VCCSA
[35]VCORE MP2979A
2,5,6,7,8,9,14,15,16,17,21,23,24,26,29,30,37 3.3VS Size Document Number Rev
2,6,9,17,18,19,20,22,26,27,29,30,33,36,37 3.3V A2 6-71-NL4C0-D02 D02
B - 36
Schematic Diagrams
E-CAP
VIN
100u_25V
1
PC138 PC162 PC52
+ + +
2
*T55D107M025C0060
T55D107M025C0060
*T55D107M025C0060
D02 stuff
VIN
Co-lay
D
2A D
1u_25V_X7R_06
10u_25V_X6S_08
10u_25V_X6S_08
3.3V
PU6 MP86903-CGLT-Z
20
VCC VIN1
1
14
85A
PC94 1u_10V_X7R_06 VIN2 0V~1.52V
19 21 BST_PWM1
AGND BST VCC_CORE
B.Schematic Diagrams
35,36 VRA_STB SYNC PGND9 12 20190626
PGND8 11 PR111 PWR MODIFY
PGND1
PGND2
PGND3
PGND4
PGND5
18 PGND7 10
35 VRACPU_CS1 CS PGND6 2.2_06
PC93 PC104
330uF_2V_5*5*4.2
330uF_2V_5*5*4.2
PC113 PC100 PC112 PC114 PC111 + +
5
6
7
8
9
PC84
22u_6.3V_X6S_08
22u_6.3V_X6S_08
22u_6.3V_X6S_08
*22u_6.3V_X6S_08
*22u_6.3V_X6S_08
2200p_50V_X7R_04
Sheet 36 of 43
Stuff For 2 phase and 3 phase. VIN
VCCGT & VCCSA OUTPUT STAGE VCCIN, VCCGT,
Co-lay
C (Base U 4+2, 6+2) 2A 2A VIN C
10u_25V_X6S_08
10u_25V_X6S_08
PWR_2_PHASE
PWR_2_PHASE
PWR_2_PHASE
PC57
PC68 PC69
1u_25V_X7R_06
10u_25V_X6S_08
10u_25V_X6S_08
3.3V
PC102 1u_10V_X7R_06
20
VCC VIN1
VIN2
1
14
20
PU3 MP86903-CGLT-Z
PCB Footprint = tqfn21-3x4mm
1
VCCGT
PWR_2_PHASE 19
AGND BST
21 BST_PWM2
PC103
PC58 1u_10V_X7R_06
19
VCC
AGND
VIN1
VIN2
BST
14
21 BST_GT
35A
PR122 0_04 15 2 1u_16V_X7R_06
35 VRACPU_PWM2 PWR_2_PHASE PWM SW1 3 PWR_2_PHASE PL6 PC56
PR123 0_04 17 SW2 4 SW_PWM2 2 1 PR64 0_04 15 2 1u_16V_X7R_06 VCCGT
35,36 VRA_VTEMP VTEP/FLT SW3 35 VRAGT_PWM1 PWM SW1
PWR_2_PHASE CCCA-0630-R15-MR 3 PL3
16 13 PWR_2_PHASE PR63 0_04 17 SW2 4 SW_GT 2 1
35,36 VRA_STB SYNC PGND9 35,36 VRA_VTEMP VTEP/FLT SW3
12 20190626 CCCA-0630-R15-MR
PGND8 11 PR121 16 13
PWR MODIFY
PGND1
PGND2
PGND3
PGND4
PGND5
PGND1
PGND2
PGND3
PGND4
PGND5
2.2_06
PGND7
APXF2R5ARA331MF45G
PR97
PWR_2_PHASE 18 10 + PC75 PC74 PC53 PC54 PC55
PWR_2_PHASE
35 VRAGT_CS1 CS PGND6
5
6
7
8
9
22u_6.3V_X6S_08
22u_6.3V_X6S_08
22u_6.3V_X6S_08
*22u_6.3V_X6S_08
*22u_6.3V_X6S_08
PC97
HEIGHT = 4.4mm
20190606 PWR
5
6
7
8
9
2200p_50V_X7R_04
PWR_2_PHASE PC76
2200p_50V_X7R_04
VIN VIN
(Performance U 4+2, 6+2) 2A Co-lay 1.5A Co-lay
PC108 PC107 PC106
PC123
PC122 PC121
1u_25V_X7R_06
10u_25V_X6S_08
10u_25V_X6S_08
PWR_3_PHASE
PWR_3_PHASE
PWR_3_PHASE
1u_25V_X7R_06
10u_25V_X6S_08
10u_25V_X6S_08
3.3V
PU8 MP86903-CGLT-Z
PC109 1u_10V_X7R_06
20
VCC VIN1
VIN2
1
14
3.3V
12
PU9
MP86901-AGQT-Z 1
VCCSA 6A
19 21 BST_PWM3 VCC VIN1 6
PWR_3_PHASE
AGND BST PC126 1u_10V_X7R_06 VIN2
11 13 BST_SA
15 2 PC110 AGND BST
35 VRACPU_PWM3 PR125 0_04 PC127
PWR_3_PHASE PWM SW1 3 1u_16V_X7R_06 VCCSA
PWR_3_PHASE PL7 1u_16V_X7R_06
PR126 0_04 17 SW2 4 SW_PWM3 2 1 PR129 0_04 7 2 PL8
35,36 VRA_VTEMP VTEP/FLT SW3 35 VRASA_PWM1 PWM SW1
PWR_3_PHASE
CCCA-0630-R15-MR 3 BCIHP0730-R47M
16 13 PWR_3_PHASE PR130 0_04 9 SW2 SW_SA 1 2
35,36 VRA_STB SYNC PGND9 35,36 VRA_VTEMP VTEP/FLT
12 20190626
PGND8 11 PR124 8
PWR MODIFY
PGND1
PGND2
PGND3
PGND4
PGND5
2.2_06
18 10
35 VRACPU_CS3 CS PGND6 2.2_06
PR127
PWR_3_PHASE
4
10 PGND1 5 PC118 PC117 PC120 PC115 PC116
PWR_3_PHASE
35 VRASA_CS1 CS PGND2
5
6
7
8
9
2200p_50V_X7R_04
A A
10,35 VCC_CORE
2,6,9,17,18,19,20,22,26,27,29,30,33,35,37 3.3V
10,35 VCCGT
17,23,24,31,32,33,35,37,38 VIN
11,35 VCCSA
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Title
[36] VCCIN & VCCGT& VCCSA
Size Document Number Rev
A2 NL40CU D02
6-71-NL4C0-D02
Date: Friday, August 16, 2019 Sheet 36 of 44
5 4 3 2 1
VCCIO, 2.5V
5 4 3 2 1
PR133
3.3_06
PR142
0_04
PR141 0_04
PART NUMBER !LPM C1 C0 VOUT (V) 8,24,32 CPU_C10_GATE#
0 X X 0(LPM)
PC133
0.22u_10V_X5R_04 VCCIO
9
VIN PU10
1 0 0 0.85V PL9 8A DEFAULT
VCCIO
LP#
SHORT
MODE
BST
D BCIHP-0735-0R68M-NL PC134 PC125 PC136 PC124 PC137 PC128 D
VCCIO 1 0 1 0.875V 1 8 VCCIO_OUT PJ32 1 2 6mm
VIN SW PCB Footprint = BCIHP0735A
0.95V
*330U_2V_D2_D
22u_6.3V_X5R_06
22u_6.3V_X5R_06
22u_6.3V_X5R_06
0.1u_10V_X5R_04
0.1u_10V_X5R_04
1 1 0 PC130 PC131 PC132 +
4.7u_25V_X5R_08 4.7u_25V_X5R_08 0.1u_25V_X7R_06
1 1 1 0.975V PR132
12 100_04
VOUT
3.3VS
GND
VDD3 PR143 100K_04 PJ34 1 2 *CV-40mil CPU_VCCIO_PWR_GATEB 5
EN
NB681GD-Z PJ30 1 2 1mm
B.Schematic Diagrams
DEFAULT VCCIO_SENSE 11
SHORT
PJ33 1 2 1mm
9 VCCIO_EN PJ31 1 2 1mm
VSSIO_SENSE 11
PR136 PR139
2 DEFAULT
0_04 0_04 PC135 PGND
*0.01u_50V_X7R_04 SHORT
VCCIOGND
PR134
PR138 C1_VCCIO_VR
Sheet 37 of 43 10K_04
C1_VCCIO_VR
3
C1
AGND
11
0_04 PR144
100_04
C0_VCCIO_VR
VCCIO, 2.5V
C0_VCCIO_VR 4
C0
PR140
3V3
PG
PR135 PR137 10K_04
VCCIOGND
C
*20K_04 *20K_04 C
13
10
3.3V 3.3V
PR128
5.1_1%_04
PR131
VCCIOGND
10K_04
PC129
1u_6.3V_X5R_04
9 VCCIO_PWRGD
VCCIOGND
B B
3.3V
3A
2.5V_LDO
5V
PC166
PC27 PC174 PR166
10u_6.3V_X5R_06 0.1u_10V_X5R_04 PU14 1u_6.3V_X5R_04
*47K_04 G9661-25ADJF11U
3 4 V2.5_LDO DEFAULT 2.5V
VIN VCNTL SHORT
D02 add 33 2.5V_PW RGD 3A
2.5V_PG 1 6 3A PJ12 1 2 2mm
DEFAULT POK VOUT
SHORT PR167 5
PJ14 1 2 1mm 2 NC PR161 PC173 PC24 PC165
9,32,33 SUSC# EN
Ra
82p_50V_NPO_04
22u_6.3V_X5R_06
0.1u_10V_X5R_04
0_04 8 7 21.5K_1%_04
PR29 9 GND VFB
PJ13 1 2 *CV-40mil GND
VDD3
100K_04
For CV test PC175 PR162
Rb
0.1u_10V_X5R_04 10K_1%_04
A A
Vout = 0.8V ( 1 + Ra / Rb )
5,6,8,9,12,21,22,23,24,25,26,29,30,31,32,33,35,38 VDD3
2,6,9,17,18,19,20,22,26,27,29,30,33,35,36
2,5,6,7,8,9,14,15,16,17,21,23,24,26,29,30,35
3.3V
3.3VS ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
17,23,24,31,32,33,35,36,38 VIN Title
17,19,20,29,30,32,33 5V [37] VCCIO/2.5V
14,15 2.5V
2,4,11 VCCIO Size Document Number Rev
A3 NL40CU 6-71-NL4C0-D02 D02
B - 38 VCCIO, 2.5V
Schematic Diagrams
Charger, AC IN
5 4 3 2 1
A
PD5 PD4
MDL914S2 MDL914S2
VDD3
VIN
C
PR32
D 287K_1%_04 D
3A PQ2
PDC3906Z VA
PQ1
PDC3906Z
PR33
VA1 ILIM
5 5
L5 5 3 3 5 PRS1 45.3K_1%_04
HCB2012KF-800T80 5
5
2
1
2
1
5
5
0.01_1%_32 D02 pwr common design 5A 5A
PC5
PC9
PC169 PC30 PC28 PC184 PC183 PC179 PC182
4
1000p_50V_X7R_04
0.047u_25V_X7R_06
1000p_50V_X7R_04
4.7u_25V_X5R_08
4.7u_25V_X5R_08
*4.7u_25V_X5R_08
*4.7u_25V_X5R_08
PC15 PC13 PR46 PC44
0.1u_25V_X7R_06
C
1500p_50V_04
PR172 PR171 10_1%_06 1u_25V_X5R_06
0.1u_25V_X7R_06
10u_25V_X5R_08
4.7_04
0.1u_25V_X7R_06
5
5
5
5
0.1u_25V_X7R_06
0.1u_25V_X7R_06
SMAJ20A 4.02K_1%_04
PQ8
PC45
A
BATDRV 4 PDC3906Z
0.1u_25V_X7R_06 PC40 PWR ASSY BOM
1
2
3
PC47 2.2u_16V_X5R_06
PC190 PC48
PC37
0.1u_25V_X7R_06
PR48 PR47
0.1u_25V_X7R_06
2.2u_25V_X5R_08 REGN PQ9 0.01u_25V_X7R_04 J_BAT1
B.Schematic Diagrams
4.02K_1%_04 4.02K_1%_04 PR41 PDC3908Z 50458-00801-002
5
5
5
5
BTST 0_06 PWR ASSY BOM PCB Footprint = 50458-008L
PL11 PRS2 P/N = 6-21-63900-108
29
28
27
26
25
24
23
22
PR45 4
D02 modify PU2 HIDRV BCIHP0730-4R7M 0.01_1%_32
0_06 2 1 V_BAT 5A 1
GND_2
LODRV
GND_1
PHASE
HIDRV
VCC
BTST
REGN
5 1
5 2
5 3
PC41 PQ12 2
PL2 3
5
SMC_BAT
PR159
PC170
PC171
PC172
0.047u_25V_X7R_06 PDC3906Z HCB1005KF-121T20
EMC1
EMC2
PR52 1 21 Phase PWR ASSY BOM SMD_BAT HCB1005KF-121T20 4
20190605 EMI
ACP 2 ACN ILIM 20 LODRV 4 PR158 PL1 5
470K_04 CMSRC 3 ACP BQ24780SRUYR SRP 19 6
*20mil short-p
1
2
3
CMSRC SRN 7
0.1u_25V_X7R_06
0.1u_25V_X7R_06
ACDRV 4 18 PR34
ACDRV BATDRV 24 BAT_DET 8
Sheet 38 of 43
PC39
PC38
PC35
PR49 *0_04 ACPRES 5 17 SRP 10_04
9,24 AC_PRESENT 6 ACOK BATSRC 16
ACDET SRN
10u_25V_X5R_08
10u_25V_X5R_08
*10u_25V_X5R_08
*20mil short-p
PROCHOT#
C
IOUT 7 ACDET TB_STAT# 15 PR35 10_04
CMPOUT
IADP BATPRES# PC36 PD3 PD2
IDCHG
CMPIN
PMON
C C
30p_50V_NPO_04
30p_50V_NPO_04
30p_50V_NPO_04
PC49 PR37 10_04 0.1u_25V_X7R_06
SDA
SCL
SS1040WG
SS1040WG
Charger, AC IN
PR51
SMC_BAT 24,35
0.1u_25V_X7R_06
A
76.8K_1%_04 TB_STAT
T41 IDCHG T40
8
9
10
11
12
13
14
SMD_BAT 24,35
D02 modify PC43 PC32 PC31
100p_50V_NPO_04
0.1u_25V_X7R_06
0.1u_25V_X7R_06
PR39 PR38 PR170
10K_1%_04 *10K_1%_04 2.2_06
PC188
VDD3
PR44
PC42 4700p_50V_X7R_04
35 PSYS
100p_50V_NPO_04 PQ3 PR55
0_04
MTE1K0P15KN3 300K_1%_04
V_BAT S D BATVLT
PR43 BAT_VOLT 24
10K_1%_04
PR53
G
100K_04
PC50
VDD3 PR56
VREG3 0.1u_10V_X5R_04
60.4K_1%_04
SMD_BAT BATGS
PR42 0_04
D
PR54 SMC_BAT PR40 0_04
G PQ4
100K_04 VDD3
2SK3018S3
S
AC_IN# 24
PR50 0_04
C
PD6 TOTAL_CUR 24
C A PR57 10K_04 B PQ5
B VA B
BTN3904 PC46
ZD5245BS2
E
100p_50V_NPO_04
PR58
10K_04
VIN
D02 EMI add
A A
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Title
5,6,8,9,12,21,22,23,24,25,26,29,30,31,32,33,35,37
17,23,24,31,32,33,35,36,37
VDD3
VIN
[38] CHARGER,AC IN
Size Document Number Rev
34
24,30,31
VA1
VREG3
Custom NL40CU 6-71-NL4C0-D02 D02
Charger, AC IN B - 39
Schematic Diagrams
RTL8411B
5 4 3 2 1
ZVDD10
ZVDD33
FOR S5 WAKE UP ON LAN Z_REGOUT ZR19 *28mil_short_06 (>20mil) Z_SD_D3/MS_D3_R 2 DATA2
TO SB PCH WAKE#. CD/DATA3
C A LAN_BD Z_PCIE_WAKE# LAN_BD 4
ZVCC_CARD Z_SD_CLK/MS_D0_R VDD
ZD1 RB751S-40C2 20190708 5
D ZC4 ZC3 Z_SD_CMD/MS_D2_R 3 CLK D
Z_SD_CD#
Z_SD_CD# CMD
LAN_BD
0.1u_6.3V_X5R_02
LAN_BD
*0.1u_10V_X7R_04
10
MEP!Npefਔ ;!Mb-Db-Dc
Z_XTAL2
Z_XTAL1
TO EC5570 PIN123 LAN_WAKEUP#
Z_EECS
9 CD# GND1
Z_LAN_W AKEUP# COMMON GND
ό ҹ- S b ҹ 6
VSS GND
GND2
ZGND ZGND
慷䓊䡢娵 ⼴ 暣 旣 ,㓡SHORT 暞 ẞ W Q21823-DES1-7F ZGND
ZGND PCB Footprint = wq2182x-des1-7x
48
47
46
45
44
43
42
41
40
39
38
37
ZU1 BIOS pulls high or low to GPO pin, P/N = 6-21-K4Y10-008
Pkease refer to LAN/PHY Disable
MS_CD#
LED0
LED2
CKXTAL2
CKXTAL1
SD_CD#
LAN_BD
RSET
LV_CEN
LED_CR
LANWAKEB
LED1/GPO
HV_GIGA
Application Note.
49 Remind that RA using the
ZVCC_CARD
E_PAD main power (S0 power).
ZR21 RA 1K_04 Z3.3VS
B.Schematic Diagrams
LAN_BD
ZGND
ZR23
ZC2 ZC5 ࡑ FNJ ዴ ᇡ ֹ-ׯT I PS U
15K_04 D02 change to short
Z_LAN_MDIP0 Z_REGOUT 0.1u_6.3V_X5R_02 22u_6.3V_X5R_06
1 36 Z_REGOUT LAN_BD
Z_LAN_MDIN0 MDIP0 REG_OUT LAN_BD LAN_BD 崘ℏ Ⰼ .
2 35 ZD3V3 Z_SD_CMD/MS_D2 Z_SD_CMD/MS_D2_R
MDIN0 VDDREG Z_ENSW REG ZR4 *0402_short LAN_BD
ZVDD10 3 34 Z_SD_D0/MS_D1 Z_SD_D0/MS_D1_R
Z_LAN_MDIP1 AVDD10 ENSWREG ZGND ZR9 *0402_short LAN_BD
4 33 ZVDD10 ZGND Z_SD_D1 Z_SD_D1_R
Z_LAN_MDIN1 MDIP1 VDD1 Near Cardreader CONN ZR10 *0402_short LAN_BD
5 32 ZVDD33 Z_SD_D2/MS_CLK Z_SD_D2/MS_CLK_R
MDIN1 VD33 ZR1 *0402_short LAN_BD
Sheet 39 of 43
Z_LAN_MDIP2 6 31 Z_ISOLATEB
MDIP2 ISOLATEBPIN Z_SD_CLK/MS_D0 ZR6 *0402_short LAN_BD Z_SD_CLK/MS_D0_R
Z_LAN_MDIN2 7 30 ZR13 *0402_short Z_BUF_PLT_RST# LAN_BD
8 MDIN2 RTL8411B PERSTBPIN 29 Z_CLKREQB LAN_BD ZR12 *0402_short Z_LAN_CLKREQ3#
Z_SD_D3/MS_D3 ZR3 *0402_short LAN_BD Z_SD_D3/MS_D3_R
ZVDD10 Z_LAN_MDIP3 AVDD10 CLKREQBPIN Z_MS_BS/SD_W P#
9 28
MDIP3 QFN48 MS_BS/SD_WP# ZT1 LAN_BD MBO`DMLSFR$ӵ ό ٬ Ҕ ё ᘐ໒ - ܭQDI ᆄޔௗ
M M
V
Q ! E
O
X
P ZC6 ZC1
RTL8411B Z_LAN_MDIN3 10
11 MDIN3 DV33_18
27
26 Z_RTL8411B_HSON
ZVDD33/18
ZC21 0.1u_10V_X7R_04 LAN_BD Z_PCIE_RXN9_GLAN
*5p_50V_NPO_04
LAN_BD
ZVDD33 HV_GIGA HSON *5p_50V_NPO_04
Z3.3VS 12 25 Z_RTL8411B_HSOP ZC22 0.1u_10V_X7R_04 LAN_BD Z_PCIE_RXP9_GLAN Close to chip
C VDD3 HSOP LAN_BD C
SD_CMD/MS_D2
SD_CLK/MS_D0
SD_D2/MS_CLK
ZC18
SD_D0/MS_D1
SD_D3/MS_D3
ZR25 ZGND ZGND
1K_04
REFCLK_N
D02 Add
REFCLK_P
CARD_3V3
0.1u_6.3V_X5R_02 CR can't write LAN_BD
VDDTX
SD_D1
LAN_BD
Crystal VDD3 meet rising time
HSIN
HSIP
ZVDD33
ZGND ZGND
㓡
䓐 HSX32 1S(3. 2X2 . 5 X0 . 65) >1ms ZR22
RTL8411B meet realtek Freq tolerance 50ppm ZVDD3 60 mil LAN_BD
Z_XTAL1
13
14
15
16
17
18
19
20
21
22
23
24
LAN_BD
6-03-08411-032 *28mil_short_06
ZC17 ZC12 ZC10
Z_SD_CMD/MS_D2
LAN_BD
Z_SD_CLK/MS_D0
Z_SD_D2/MS_CLK
Z_CLK_PCIE_GLAN# ZH5 LAN_BD ZH1 LAN_BD
Z_XTAL2
Z_SD_D0/MS_D1
Z_SD_D3/MS_D3
ZCARD_3V3 Z_CLK_PCIE_GLAN ZR18 1M_04 0.1u_6.3V_X5R_02 0.1u_6.3V_X5R_02 0.1u_6.3V_X5R_02
*H5_0D2_3 *O248X268D85
LAN_BD LAN_BD LAN_BD
1 2 H5_0D2_3 O248X268D85
ZEVDD10
Z_PCIE_TXN9_GLAN ZGND PIN11 PIN32 PIN48
Z_SD_D1 Z_PCIE_TXP9_GLAN 4 3
PCBfootprint: ZGND ZGND ZGND
ZGND HSX321G
ZX1
FSX3L 25MHZ ZD3V3
ZC11 LAN_BD ZC13 ZR20
ZJ_14MB1 ZJ_15MB1
ZL1
LAN POART ZJ_RJ1
ZGND ZGND
1 1 4 3 ZL2 LAN_BD
2 2 Z_LAN_MDIP0 12 13 Z_LMX1+ *WCM2012F2S-161T03-short Z_DLMX1+ 1 GND1 ZCARD_3V3 ZR7 0.2R_5%_06
Z_LAN_MDIN0 TD4+ MX4+ Z_LMX1- Z_DLMX1- 2 DA+ shield ZVCC_CARD
3 3 11 14 1 2 GND2 0.2_06 LAN_BD
Z3.3VS Z3.3VS Z_LAN_MDIP1 TD4- MX4- Z_LMX2+ Z_DLMX2+ 3 DA- shield
4 4 9 16 4 3 ZL3 LAN_BD 6-14-0R23F-01B-1
Z_LAN_MDIN1 TD3+ MX3+ Z_LMX2- Z_DLMX2- 6 DB+
5 5 8
MX3-
17 *WCM2012F2S-161T03-short ᜢ ഈip t uႝ ྍ 0!DB
SE
TD3- 1 2 DB- ZGND
6 6 ܘ ක ਔ - W D D ` D BSE
7 7 4 3 ZL4 LAN_BD
Z_LAN_MDIP2 6 19 Z_LMX3+ Z_DLMX3+ 4 ႝ ᓸ ᔈ ե ܭ1/ 6 ҷ -ന ሡ ा2ntය໔
Ͽ
NC1 8 Z_PCIE_TXN9_GLAN NC1 8 Z_PCIE_TXN9_GLAN *WCM2012F2S-161T03-short
Z_LAN_MDIN2 TD2+ MX2+ Z_LMX3- Z_DLMX3- 5 DC+
NC2 9 Z_PCIE_TXP9_GLAN NC2 9 Z_PCIE_TXP9_GLAN 5 20 1 2
Z_LAN_MDIP3 TD2- MX2- Z_LMX4+ Z_DLMX4+ 7 DC-
10 10 3 TD1+ 22 4 3 ZL5 LAN_BD
MX1+ DD+
ZGND 11 Z_PCIE_RXN9_GLAN
ZGND
11 Z_PCIE_RXN9_GLAN
Z_LAN_MDIN3 2 TD1- MX1- 23 Z_LMX4-
1 2
*WCM2012F2S-161T03-short Z_DLMX4- 8
DD- PULL LOW: LDO Mode
12 Z_PCIE_RXP9_GLAN 12 Z_PCIE_RXP9_GLAN
13 13 Z_NTCT 10 15 Z_NMCT_4 C100LE-108H9-L D02 change footprint
40 mil 7 TCT4 MCT4 18 Z_NMCT_3 PCB Footprint = c100le-108h9-l-1 Z_ENSW REG ZR16 *28mil short-p
14 Z_CLK_PCIE_GLAN 14 Z_CLK_PCIE_GLAN
4 TCT3 MCT3 21 Z_NMCT_2 PN = 6-21-B40G0-008
15 Z_CLK_PCIE_GLAN# 15 Z_CLK_PCIE_GLAN# LAN_BD
1 TCT2 MCT2 24 Z_NMCT_1 LAN_BD
16 16
TCT1 MCT1
17 17 ໆ ౢ ዴᇡ MEP!N
E F
P ZGND
18 Z_LAN_CLKREQ3# 18 Z_LAN_CLKREQ3# GST5009 LF
ZC7 LAN_BD PLࡕ -
19 Z_BUF_PLT_RST# 19 Z_BUF_PLT_RST# D02 change
A 20 Z_LAN_W AKEUP# 20 Z_LAN_W AKEUP# ZH3 LAN_BD
ׯTIPSU ႟ҹ A
21 Z_PCIE_WAKE# 21 Z_PCIE_WAKE# 0.01u_16V_X7R_04
LAN_BD *O134X154B251X271D95X106
22 22 LAN_BD ZR2 75_1%_04 Z_NMCT_R O134X154B251X271D95X106
FP225H-02261BM ZGND FP225H-02261BM ZGND ZR5 75_1%_04 LAN_BD
P/N = 6-20-94K10-022 P/N = 6-20-94K10-022 ZGND ZR8 75_1%_04 LAN_BD
PCB Footprint = FP225-022-R 20190610 swap pin1 PCB Footprint = FP225-022-R ZR11 75_1%_04 LAN_BD
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
ZC8 Title
1ZR1 0_04 4ZR1 *0_04
LAN_BD_FOR_15" LAN_BD
100PF 2KV 1206
ZGND [39] LAN_BD_Z
2ZR1 *0_04 5ZR1 *0_04
LAN_BD Size Document Number Rev
LAN_BD LAN_BD
3ZR1
LAN_BD
*0_04 6ZR1
LAN_BD
*0_04
P/N = 6-07-1012C-HB0
ZGND A3 6-71-NL4CZ-D02 D02
B - 40 RTL8411B
Schematic Diagrams
5 4 3 2 1
HP-L
GND
A_SLEEVE_CONN AR2 0_04 A_SLEEVE_CON_R AL1 FCM1005MF-300T03 14"_IO_BD
A_AUDG 1
AD5
2
AVLC5S02100
14"_IO_BD
COMBO JACK
3 * R / L 䶂⮔ 14"_IO_BD
HP-R AC8 D02 change
GND 100p_50V_NPO_04
14"_IO_BD A_AUDG AR5 *0402_short
Layout note:
D A_AUDG AJ_COMBO1 D
14"_IO_BD A_SLEEVE_CON 1
Headphone妲 嘇
䶂 ⮔ > 10 m
is
l A_HEADPHONE_L_DEPOP AR4 82_04 A_EARPHONE_L AL3 FCM1005KF-121T03 14"_IO_BD A_HPOL_CON 4
嶅暊 p h o n e j a ck崲怈 D02 BCN update 5
䶂⼹⯙⽭枰崲 ⮔ 14"_IO_BD A_HPOUT-JD 6
R / L ⽭枰⊭ 央 GNDᶼ 攻嶅䁢 3* 䶂 ⮔ A_HEADPHONE_R_DEPOP AR3 82_04 A_EARPHONE_R AL2
A_RING2_CONN AL4
FCM1005KF-121T03 14"_IO_BD A_HPOR_CON
A_RING2_CON
3
FCM1005MF-300T03 14"_IO_BD 2
AC5 AC6 AC7
2SJ3127-000111F
1
0_04 D02 BCN update
100p_50V_NPO_04
100p_50V_NPO_04
D02 change AD2 AD3 AD4 PCB Footprint = 2sj3127-000111f
AJ_MB1 D02 change P/N = 6-20-B28X0-006
AC13 0.1u_25V_X5R_04 14"_IO_BD
14"_IO_BD
14"_IO_BD
14"_IO_BD
14"_IO_BD
*AVLC5S02100
*AVLC5S02100
*AVLC5S02100
40 A5V
Layout trace > 40 mil ,
B.Schematic Diagrams
AC12 0.1u_25V_X5R_04 14"_IO_BD
14"_IO_BD
39
14"_IO_BD
14"_IO_BD
Footprint=FP201-040X1-0M pin1 fix
2
37 AC2 0.1u_25V_X5R_04 14"_IO_BD
36
35 AR1 *0_04 14"_IO_BD
34
33
32
Sheet 40 of 43
A3.3V A_AUDG AGND
31 A_AUDG A_AUDG
30 A3.3VS
29
28 A_M_BTN# POWER SW
27
26
25 POWER BUTTON 14” I/O Board
C
24
23
22
21
20
19
14" I/O BOARD S1
G1
AJ_SW 1
S1 S2 S2 A_M_BTN#
C
GND
G2 GND
18
1
GND
17 AD1 AC4
16 TCD-C2KQR
G3
*AVL18S02015
15 PCB Footprint = TCD-C2KQR
14"_IO_BD 0.1u_50V_X5R_04
14 A_USB_PP5 P/N = 6-53-31500-041
VARISTOR 14"_IO_BD
13 A_USB_PN5 AH4 AH3 AH5 AH2 14"_IO_BD
*H6_0D2_3 *H6_5B3_0D2_3 *H4_8b3_0d2_4 *H9_5D5_5 6-24-30003-006
2
12 USB2.0
11 A_USB_PW R_EN# H6_0D2_3 H6_5B3_0D2_3 H4_8b3_0d2_4 H9_5D5_5
10
9 AGND
AGND
8 A_RING2_CONN
7 A_SLEEVE_CONN
GND2 6 A_HPOUT-JD
GND1 5
HEAD-PHONE
AGND AGND AGND AGND ĕ÷ýõýĆöñå 㛔 幓㚫䅺 㭨ñ
4 A_HEADPHONE_L_DEPOP 14"_IO_BD 14"_IO_BD 14"_IO_BD 14"_IO_BD
3 A_HEADPHONE_R_DEPOP ĕ÷ýõýĆö
AGND 2 䫾 å ĉ÷ û å IJĴĺijĹ Ī ĩ å ěĆėĎ Ę ęĔė
⮵ ó
1 1AR1 *0_04 4AR1 *0_04
14"_IO_BD 14"_IO_BD
FP201H-040S10M
2AR1 *0_04 5AR1 *0_04
P/N = 6-20-94K20-140 A_AUDGAGND
14"_IO_BD 14"_IO_BD
PCB Footprint = FP201-040X1-0M
3AR1 *0_04 6AR1 *0_04
14"_IO_BD
14"_IO_BD 14"_IO_BD
B B
A_USBVCC2.0 60 mil
A5V 5
AU1
VIN VOUT
1 60 MIL USB2.0 PORT_5 A_USBVCC2.0 AC10
AC11
22u_6.3V_X5R_06
14"_IO_BD
22u_6.3V_X5R_06
AGND
AGND
14"_IO_BD
2
GND AC1
AC9
4 3
EN# OC# 0.1u_6.3V_X5R_02
10u_6.3V_X5R_06 AD6
AJ_USB1
SY6288D20AAC 14"_IO_BD
14"_IO_BD AR7 *0_04 14"_IO_BD 6 5 1
2A/90mohm 7 4 V+ 0.5A GND2
AGND 14"_IO_BD A_USB_PN5_C GND2
D02 EMI Change to SHORT 8 3 2 GND1
SY6288D20AAC: 6-02-62882-9C0
AGND A_USB_PN5 1 2 A_USB2_PN5AGND 9 2
AGND DATA_L GND1
uP7549UMA5-20: 6-02-75495-9C0
*WCM2012F2S-161T03 A_USB2_PP5 10 1 A_USB_PP5_C 3
A_USB_PW R_EN# AL5 PCB Footprint = WCM2012F2S-SHORT DATA_H
A_USB_PP5 4 3 GND3
14"_IO_BD 4 AGND GND4
AR8 *0_04 14"_IO_BD ESD73034D GND AGND
14"_IO_BD
AGND C147S3-10439-L
A
Colay 䔲 㓦 20190620 layout swap PCB Footprint = c147s3-10439-l-1 AGND
P/N = 6-21-B4920-004 D02 change footprint
A
14"_IO_BD
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
FOR USB2.0 PORT ONLY, EMI暨
㯪, Title
⤪㚱ⷞ 䶂 M/B䪗冯⮷ ⌉ 䪗 悥暨枸䔁 , 嬻 E M I䡢娵 ⒒䪗ᶲ ẞ [40] NL40CU I/O BOARD_A
Size Document Number Rev
A3 6-71-NL4C1-D02 D02
Date: Monday, September 23, 2019 Sheet 40 of 44
5 4 3 2 1
W UDG 1 2
D
HP-L
GND
W _SLEEVE_CONN W R11
3 * R / L 䶂⮔
0_04 W _SLEEVE_CON_R W L1
15"_IO_BD
FCM1005MF-300T03 15"_IO_BD
W D4 AVLC5S02100
15"_IO_BD COMBO JACK D
HP-R W C6
GND 100p_50V_NPO_04
15"_IO_BD W UDG W R10 *0402_short
Layout note:
W UDG D02 change W J_COMBO1
15"_IO_BD W _SLEEVE_CON 1
Headphone妲 嘇
䶂 ⮔ > 10 m
i ls W _HEADPHONE_L_DEPOP W R13 82_04 W _EARPHONE_L W L3 FCM1005KF-121T03 15"_IO_BD W _HPOL_CON 4
嶅暊 p h o n e j a ck崲怈 D02 BCN update 5
䶂⼹⯙⽭枰崲 ⮔ 15"_IO_BD W _HPOUT-JD 6
R / L ⽭枰⊭ 央 GNDᶼ 攻嶅䁢 3* 䶂 ⮔ W _HEADPHONE_R_DEPOP W R12 82_04 W _EARPHONE_R W L2
W _RING2_CONN
FCM1005KF-121T03 15"_IO_BD W _HPOR_CON
W _RING2_CON
3
W L4 FCM1005MF-300T03 15"_IO_BD 2
W C2 W C3 W C4
2SJ3127-000111F
1
0_04 D02 BCN update
W D1 W D2 W D3
100p_50V_NPO_04
100p_50V_NPO_04
D02 change PCB Footprint = 2sj3127-000111f
D02 change
B.Schematic Diagrams
15"_IO_BD
15"_IO_BD
15"_IO_BD
*AVLC5S02100
*AVLC5S02100
*AVLC5S02100
W C1 0.1u_25V_X5R_04 15"_IO_BD
Layout trace > 40 mil ,
15"_IO_BD
15"_IO_BD
15"_IO_BD
W C7 0.1u_25V_X5R_04 15"_IO_BD
suggest to implement shapes.
2
W R9 *0_04 15"_IO_BD
W GND
Sheet 41 of 43 W UDG
W UDG W UDG
W J_MB1
W 5V
38
37
36
35
34
33
32
31 W 3.3V
30 W 3.3VS
29
28
27
26
25 W R15 *4.7K_04 15"_IO_BD_3G
24 W J_SIM1
23 W _USB_PN3 42 D02 rename 21-6012-01 15"_IO_BD_3G
W _USB_PP3 42
USB2.0 15"_IO_BD_3G PCB Footprint = 21-6012-0x
22
21 W GND W C11 0.01u_16V_X7R_04 P/N = 6-86-2B010-007
W J_MB2
20 W _UIM_PWR (TOP VIEW)
19 1 W _SIM_DET SW1 C8
18 20190703 DEL USB3 2 C4 DETECT_SW UIM_MCMD C7 W _UIM_DATA
W _UIM_CLK C3 UIM_DATA UIM_I/O C6 W _UIM_VPP
B 17 3 W _SIM_DET W T1 B
W _UIM_RST C2 UIM_CLK UIM_VPP C5
16 4 W _UIM_CLK
W _UIM_PWR UIM_RST UIM_GND
GND1
GND2
GND3
GND4
15 5 W _UIM_DATA C1 15"_IO_BD_3G
UIM_PWR
14 6 W _UIM_RST
13 W _USB_PP5 42 7
12 W _USB_PN5 42 USB2.0 8
GND1
GND2
GND3
GND4
11 W C5 W C8
10 W _USB_PW R_EN# 42
W GND
9 *0.1u_6.3V_X5R_02 22p_50V_NPO_04
FP225H-008S11M
8 W _RING2_CONN 15"_IO_BD_3G 15"_IO_BD_3G
PCB Footprint = fp225h-008gxxxm_r 20190619 swap pin1
7 W _SLEEVE_CONN P/N = 6-20-94K30-108
GND2 6 W _HPOUT-JD W GND W GND 20190626 W GND
15"_IO_BD_3G RF stuff
GND1 5
4 W _HEADPHONE_L_DEPOP HEAD-PHONE
3 W _HEADPHONE_R_DEPOP
2
W GND 1
FP201H-040S10M
P/N = 6-20-94K20-140 W UDG W GND
PCB Footprint = FP201-040X1-0M
15"_IO_BD
D02 add
A A
W H2 W H3 W H5
W H1 W H4
2 4 2 4 *H4_0D2_3
*H3_9D2_3 *H7_0D5_8
H4_0D2_3
H3_9D2_3 H7_0D5_8 1W R1 *0_04 4W R1 0_04
3 1 5 3 1 5
15"_IO_BD 15"_IO_BD_W /O_3G
*MTH7_0D2_3 *MTH7_0D2_3
2W R1
15"_IO_BD
*0_04 5W R1 *0_04
15"_IO_BD ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
MTH7_0D2_3 MTH7_0D2_3 3W R1 *0_04 6W R1 *0_04 Title
W GND
15"_IO_BD
W GND
15"_IO_BD
W GND
W GND W GND
15"_IO_BD 15"_IO_BD
W GND
15"_IO_BD
[41] NL50CU I/O BOARD_1_W
15"_IO_BD 15"_IO_BD Size Document Number Rev
42 W 5V
A3 6-71-NL5C1-D02 D02
D D
B.Schematic Diagrams
W _USBVCC
W U3
5 1
W 5V VIN VOUT
W C9 2 W C28
10u_6.3V_X5R_06 GND 0.1u_6.3V_X5R_02
4 3 15"_IO_BD
15"_IO_BD EN# OC#
W GND SY6288D20AAC
2A/90mohm
15"_IO_BD W GND
Sheet 42 of 43
C
20190702 Modify from USB3.1 to USB2.0
41 W _USB_PW R_EN#
W _USB_PW R_EN# SY6288D20AAC: 6-02-62882-9C0
uP7549UMA5-20: 6-02-75495-9C0
C 15” I/O Board-2
W C27 22u_6.3V_X5R_06
15"_IO_BD
W _USBVCC W C26 22u_6.3V_X5R_06 W GND
15"_IO_BD
15"_IO_BD
PCB Footprint = dfn10-2_5x1mm-short
ESD73034D
W J_USB2
W R22 *0_04 15"_IO_BD 6 5
1
7 4 V+
D02 EMI Change to SHORT GND2
W _USB_PN3_R W GND 8 3 W GND W _USB_PN3_RJ GND2
1 2 W L6 15"_IO_BD 2 GND1
41 W _USB_PN3 9 2 DATA_L GND1
*WCM2012F2S-161T03-short
10 1
4 3 PCB Footprint = W CM2012F2S-SHORT W _USB_PP3_R W _USB_PP3_RJ 3
41 W _USB_PP3 DATA_H GND3
W R23 *0_04 15"_IO_BD 4 AGND GND4
W D7 GND AGND
Colay C147S3-10439-L
6-21-B4910-004
W GND
B W GND PCB Footprint = c147s3-10439-l-1 B
15"_IO_BD D02 change footprint
P/N = 6-21-B4920-004
60 mil
W C12 22u_6.3V_X5R_06
W _USBVCC2.0
USB2.0 PORT_5 TYPE-A W _USBVCC2.0
W C10
15"_IO_BD
22u_6.3V_X5R_06
15"_IO_BD
W GND
W GND
W U1 W J_USB1
5 1 60 MIL 1
W 5V VIN VOUT W R21 *0_04 15"_IO_BD 15"_IO_BD V+ 0.5A GND2
ESD73034D W _USB_PN5_C GND2
2 D02 EMI Change to SHORT 2 GND1
GND W C13 W _USB2_PN5 DATA_L GND1
W C29 1 2 6 5
41 W _USB_PN5 W _USB2_PP5 W _USB_PP5_C
4 3 W L5 *WCM2012F2S-161T03 7 4 3
EN# OC# 0.1u_6.3V_X5R_02 DATA_H
10u_6.3V_X5R_06 4 3 PCB Footprint = WCM2012F2S-SHORT W GND 8 3 W GND GND3
41 W _USB_PP5 15"_IO_BD AGND
SY6288D20AAC 15"_IO_BD 9 2 4 GND4
15"_IO_BD GND AGND
2A/90mohm W R16 *0_04 15"_IO_BD 10 1
W GND 15"_IO_BD
SY6288D20AAC: 6-02-62882-9C0 W GND C147S3-10439-L
A W _USB_PW R_EN#
uP7549UMA5-20: 6-02-75495-9C0 W GND
Colay W D5 6-21-B4910-004
PCB Footprint = c147s3-10439-l-1
W GND A
20190627 layout swap
15"_IO_BD D02 change footprint
P/N = 6-21-B4920-004
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
FOR USB2.0 PORT ONLY, EMI暨
㯪, Title
⤪㚱ⷞ 䶂 M/B䪗冯⮷ ⌉ 䪗 悥暨枸䔁 , 嬻 E M I䡢娵 ⒒䪗ᶲ ẞ [42] NL50CU I/O BOARD_2_W
Size Document Number Rev
41 W 5V
A3 6-71-NL5C1-D02 D02
Date: Friday, August 16, 2019 Sheet 42 of 43
5 4 3 2 1
D D
Sheet 43 of 43
POWER BUTTON
Power Button C
D02 change to H active 1
B_SW1
2
C
BM_BTN#
Board BJ_BTN1
B3.3VS
BLED_PWR_R POWER ON
LOCK LED
3
T4BJB10BQR
4
BT1
PCB Footprint = T4BJB16-Q
1
1
BLED_PWR P/N = 6-53-31500-B41
NC1 2 BM_BTN# BR1
BD2 BC1
NC2 3
4 2.7K_04 D02 BCN update
BGND 0.1u_6.3V_X5R_02
15"_PWR_BD
BGND *AVL18S02015 15"_PWR_BD
FP226H-004S10M BGND VARISTOR
BD3
2
P/N = 6-20-94A40-004 P/N: 6-24-30003-006
PCB Footprint = fp226H-004xxxm_r D02 change to _r A C BGND 15"_PWR_BD
15"_PWR_BD
BGND
RY-SP190DBW71-5A
PCB Footprint = RY-SP190YG34-5M
P/N = 6-52-57301-022 THE VARISTOR FOR
15"_PWR_BD P2808A1 BURN SOLUTION
B LED COLOR = WHITE B