Professional Documents
Culture Documents
Preface
Notebook Computer
Service Manual
Preface
I
Preface
Notice
The company reserves the right to revise this publication or to change its contents without notice. Information contained
herein is for reference only and does not constitute a commitment on the part of the manufacturer or any subsequent ven-
dor. They assume no responsibility or liability for any errors or inaccuracies that may appear in this publication nor are
they in anyway responsible for any loss or damage resulting from the use (or misuse) of this publication.
This publication and any accompanying software may not, in whole or in part, be reproduced, translated, transmitted or
reduced to any machine readable form without prior consent from the vendor, manufacturer or creators of this publica-
tion, except for copies kept by the user for backup purposes.
Brand and product names mentioned in this publication may or may not be copyrights and/or registered trademarks of
their respective companies. They are mentioned for identification purposes only and are not intended as an endorsement
of that product or its manufacturer.
Preface
Version 1.0
September 2021
Trademarks
Pentium and Celeron are trademarks of Intel Corporation.
Windows® is a registered trademark of Microsoft Corporation.
Other brand and product names are trademarks and /or registered trademarks of their respective companies.
II
Preface
It is organized to allow you to look up basic information for servicing and/or upgrading components of the NL50MU /
NL51MU / NL52MU series notebook PC.
Chapter 1, Introduction, provides general information about the location of system elements and their specifications.
Chapter 2, Disassembly, provides step-by-step instructions for disassembling parts and subsystems and how to upgrade
elements of the system.
Preface
Appendix B, Schematic Diagrams
III
Preface
1. Do not use this product near water, for example near a bath tub, wash bowl, kitchen sink or laundry tub, in a wet
basement or near a swimming pool.
2. Avoid using a telephone (other than a cordless type) during an electrical storm. There may be a remote risk of elec-
trical shock from lightning.
3. Do not use the telephone to report a gas leak in the vicinity of the leak.
4. Use only the power cord and batteries indicated in this manual. Do not dispose of batteries in a fire. They may
explode. Check with local codes for possible special disposal instructions.
5. This product is intended to be supplied by a Listed Power Unit with an AC Input of 100 - 240V, 50 - 60Hz, DC Output
of 19V, 2.37A (45 Watts) minimum AC/DC Adapter.
Preface
FCC Statement
This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions:
This device may not cause harmful interference.
This device must accept any interference received, including interference that may cause undesired operation.
IV
Preface
1. Don’t drop it, or expose it to shock. If the computer falls, the case and the components could be damaged.
Do not expose the computer Do not place it on an unstable Do not place anything heavy
to any shock or vibration. surface. on the computer.
2. Keep it dry, and don’t overheat it. Keep the computer and power supply away from any kind of heating element. This
is an electrical appliance. If water or any other liquid gets into it, the computer could be badly damaged.
Do not expose it to excessive Do not leave it in a place Don’t use or store the com- Do not place the computer on
Preface
heat or direct sunlight. where foreign matter or mois- puter in a humid environment. any surface which will block
ture may affect the system. the vents.
3. Follow the proper working procedures for the computer. Shut the computer down properly and don’t forget to save
your work. Remember to periodically save your data as data may be lost if the battery is depleted.
Do not turn off the power Do not turn off any peripheral Do not disassemble the com- Perform routine maintenance
until you properly shut down devices when the computer is puter by yourself. on your computer.
all programs. on.
V
Preface
4. Avoid interference. Keep the computer away from high capacity transformers, electric motors, and other strong mag-
netic fields. These can hinder proper performance and damage your data.
5. Take care when using peripheral devices.
Power Safety
Preface
VI
Preface
Battery Precautions
• Only use batteries designed for this computer. The wrong battery type may explode, leak or damage the computer.
• Do not continue to use a battery that has been dropped, or that appears damaged (e.g. bent or twisted) in any way. Even if the
computer continues to work with a damaged battery in place, it may cause circuit damage, which may possibly result in fire.
• Recharge the batteries using the notebook’s system. Incorrect recharging may make the battery explode.
• Do not try to repair a battery pack. Refer any battery pack repair or replacement to your service representative or qualified service
personnel.
• Keep children away from, and promptly dispose of a damaged battery. Always dispose of batteries carefully. Batteries may explode
or leak if exposed to fire, or improperly handled or discarded.
• Keep the battery away from metal appliances.
• Affix tape to the battery contacts before disposing of the battery.
• Do not touch the battery contacts with your hands or metal objects.
Battery Guidelines
The following can also apply to any backup batteries you may have.
Preface
• If you do not use the battery for an extended period, then remove the battery from the computer for storage.
• Before removing the battery for storage charge it to 60% - 70%.
• Check stored batteries at least every 3 months and charge them to 60% - 70%.
Battery Disposal
The product that you have purchased contains a rechargeable battery. The battery is recyclable. At the end of its useful life, under var-
ious state and local laws, it may be illegal to dispose of this battery into the municipal waste stream. Check with your local solid waste
officials for details in your area for recycling options or proper disposal.
Caution
Danger of explosion if battery is incorrectly replaced. Replace only with the same or equivalent type recommended by the manufacturer.
Discard used battery according to the manufacturer’s instructions.
Battery Level
Click the battery icon in the taskbar to see the current battery level and charge status. A battery that drops below a level of 10%
will not allow the computer to boot up. Make sure that any battery that drops below 10% is recharged within one week.
VII
Preface
Related Documents
You may also need to consult the following manual for additional information:
System Startup
1. Remove all packing materials.
2. Place the computer on a stable surface.
3. Insert the battery and make sure it is locked in position.
4. Securely attach any peripherals you want to use with the
computer (e.g. keyboard and mouse) to their ports.
Powering the
Preface
Computer On 5. When first setting up the computer use the following pro-
cedure (as to safeguard the computer during shipping, the
After every disassem- battery will be locked to not power the system until first con-
bly, make sure that the nected to the AC/DC adapter and initially set up as below):
bottom case’s screws • Attach the AC/DC adapter cord to the DC-In jack on the 180°
are all inserted and
right of the computer, then plug the AC power cord into an
tightened before turn-
ing the computer on.
outlet, and connect the AC power cord to the AC/DC
adapter. The battery will now be unlocked. Figure 1
Opening the Lid/LCD/
6. Use one hand to raise the lid/LCD to a comfortable viewing
Computer with AC/DC
angle (do not exceed 180 degrees); use the other hand (as
Adapter Plugged-In
illustrated in Figure 1) to support the base of the computer Shut Down
(Note: Never lift the computer by the lid/LCD).
7. Press the power button on the left side of the computer to Note that you should always
turn the computer “on” (note that the lid/LCD must be open shut your computer down by
for the power button to function). choosing Shut Down command
in Windows.
This will help prevent hard disk
or system problems.
VIII
Preface
Contents
Introduction ..............................................1-1 Bottom ........................................................................................... A-4
LCD ............................................................................................... A-5
Overview .........................................................................................1-1 HDD ............................................................................................... A-6
Specifications ..................................................................................1-2 MB ................................................................................................ A-7
External Locator - Top View with LCD Panel Open ......................1-4
External Locator - Front & Right Side Views .................................1-5 Schematic Diagrams................................. B-1
External Locator - Left Side & Rear View .....................................1-6 System Block Diagram ...................................................................B-2
External Locator - Bottom View .....................................................1-7 Processor 1/12 .................................................................................B-3
Mainboard Overview - Top (Key Parts) .........................................1-8 Processor 2/12 .................................................................................B-4
Mainboard Overview - Bottom (Key Parts) ....................................1-9 Processor 3/12 .................................................................................B-5
Mainboard Overview - Top (Connectors) .....................................1-10 Processor 4/12 .................................................................................B-6
Mainboard Overview - Bottom (Connectors) ...............................1-11 Processor 5/12 .................................................................................B-7
Disassembly ...............................................2-1 Processor 6/12 .................................................................................B-8
Preface
Processor 7/12 .................................................................................B-9
Overview .........................................................................................2-1
Processor 8/12 ...............................................................................B-10
Maintenance Tools ..........................................................................2-2 Processor 9/12 ...............................................................................B-11
Connections .....................................................................................2-2
Processor 10/12 .............................................................................B-12
Maintenance Precautions .................................................................2-3
Processor 11/12 .............................................................................B-13
Disassembly Steps ...........................................................................2-4 Processor 12/12 .............................................................................B-14
Removing the Battery ......................................................................2-5
DDR4 SO-DIMM_A ....................................................................B-15
Removing the Hard Disk Drive .......................................................2-9
DDR4 SO-DIMM_B ....................................................................B-16
Removing the System Memory (RAM) ........................................2-11
HDMI ............................................................................................B-17
Removing the Keyboard ................................................................2-13
Panel .............................................................................................B-18
Removing the Wireless LAN Module ...........................................2-14
USB Type-C ANX7443 ................................................................B-19
Wireless LAN, and Combo Module Cables ..................................2-15
ANX7411, Type-C .......................................................................B-20
Removing the 4G Module .............................................................2-16
ASM1543 ......................................................................................B-21
Removing the M.2 SSD Module ...................................................2-17 LED KB, LED ..............................................................................B-22
Removing the CCD .......................................................................2-18
SATA HDD, TPM ........................................................................B-23
Part Lists ..................................................A-1 Audio Codec .................................................................................B-24
Part List Illustration Location ........................................................ A-2 KBC ITE IT5570 ..........................................................................B-25
Top ................................................................................................. A-3 WLAN ..........................................................................................B-26
IX
Preface
X
Introduction
Chapter 1: Introduction
Overview
This manual covers the information you need to service or upgrade the NL50MU / NL51MU / NL52MU series notebook
computer. Information about operating the computer (e.g. getting started, and the Setup utility) is in the User’s Manual.
Information about dri-vers (e.g. VGA & audio) is also found in the User’s Manual. The manual is shipped with the com-
puter.
Operating systems (e.g. Window 10, etc.) have their own manuals as do application softwares (e.g. word processing and
database programs). If you have questions about those programs, you should consult those manuals.
1.Introduction
The NL50MU / NL51MU / NL52MU series notebook is designed to be upgradeable. See Disassembly on page 2 - 1 for
a detailed description of the upgrade procedures for each specific component. Please take note of the warning and safety
information indicated by the “” symbol.
The balance of this chapter reviews the computer’s technical specifications and features.
Overview 1 - 1
Introduction
1 - 2 Specifications
Introduction
Slot 1 for WLAN and Bluetooth Combo Module Full Range AC/DC Adapter
Slot 2 for PCIe Gen4 x4 SSD AC Input: 100 - 240V, 50 - 60Hz
(Factory Option) Slot 3 for 4G Module DC Output: 19V, 2.37A (45W)
1.Introduction
Wireless LAN + Bluetooth
Operating: 20% - 80%
(Factory Option) Intel® Dual Band Wi-Fi 5 Wireless-AC
9462, 1x1 AC Wireless LAN + Bluetooth Non-Operating: 10% - 90%
(Factory Option) Intel® Dual Band Wi-Fi 5 Wireless-AC Dimensions & Weight
9560, 2x2 AC Wireless LAN + Bluetooth
360.4mm (w) * 239.3mm (d) * 19.7mm (h)
Interface 1.59kg (Barebone with 36WH Battery)
One USB 3.2 Gen 2 Type-C Port*
Or
(Factory Option) One USB 3.2 Gen 2 Type-C Port with Dis-
playPort and Power Delivery (DC-In)
*The maximum amount of current supplied by USB Type-C
ports is 500mA (USB 2.0)/900mA (USB3.2).
One USB 3.2 Gen 2 Type-A Port
Or
(Factory Option) One Powered USB 3.2 Gen 2 Type-A Port
One HDMI-Out Port
One 2-In-1 Audio Jack (Headphone / Microphone)
One RJ-45 LAN Jack
One DC-in Jack
Two USB 2.0 Ports
Specifications 1 - 3
Introduction
Figure 1
External Locator - Top View with LCD Panel Open
Top View
1. Webcam
2. *Camera LED
*When the PC 3 2 1 3
camera is in use,
the LED will be
illuminated in
white.
3. Built-In Array
4
Microphone
1.Introduction
4. Display
5. Vent
6. Power Button
7. LED Indicators
8. Keyboard
5
9. Touchpad &
Buttons 6 7
FRONT VIEW
Figure 3
Right Side View
1. Speaker
1.Introduction
2. USB 3.2 Gen 2
Type-C Port
Or
(Factory
Option) USB 3.2
Gen 2 Type-C
Port with
DisplayPort and
RIGHT SIDE VIEW Power Delivery
(DC-In)
3. USB 3.2 Gen 2
Type-A Port
2 Or
1 3 4 5 6 (Factory Option)
Powered USB
3.2 Gen 2 Type-A
Port
4. HDMI-Out Port
5. Battery Power
LED Indicator
6. DC-In Jack
Microphone)
7. Speaker
2
1
1.Introduction
3 3 Overheating
1. KBC-ITE IT5570
1.Introduction
3
2 1
1. CPU
2. Memory Slots
DDR4 SO-DIMM
1.Introduction
2
1
1. DC-In Jack
2. HDMI-Out Port
3. USB 3.2 Gen 2
Type-A Port
4. USB 3.2 Gen 2
Type-C Port
5. LED Keyboard 1
Connector
1.Introduction
6. Keyboard Cable 7
Connector 2
7. Power BTN
Connector
3
6 5
1. CCD Cable
Connector
2. Fan Connector
3. M.2 Card
Connector
4. Speaker Connecto
13
5. HDD Connector
14 6. Battery Connector
1
1.Introduction
12 7. Touchpad
Connector
8. SIM Connector
11 9. USB Board
10
Connector
2 10.CMOS Battery
Connector
9 11. LTE Connector
4 12.LAN Board
6 7
8 Connector
3 5
13.WLAN/BT
4 Connector
14.LCD Cable
Connector
1 - 12
Disassembly
Chapter 2: Disassembly
Overview
This chapter provides step-by-step instructions for disassembling the NL50MU / NL51MU / NL52MU series notebook’s
parts and subsystems. When it comes to reassembly, reverse the procedures (unless otherwise indicated).
We suggest you completely review any procedure before you take the computer apart.
Procedures such as upgrading/replacing the RAM, optical device and hard disk are included in the User’s Manual but are
repeated here for your convenience.
2.Disassembly
To make the disassembly process easier each section may have a box in the page margin. Information contained under
the figure # will give a synopsis of the sequence of procedures involved in the disassembly procedure. A box with a
lists the relevant parts you will have after the disassembly process is complete. Note: The parts listed will be for the dis-
Information
assembly procedure listed ONLY, and not any previous disassembly step(s) required. Refer to the part list for the previ-
ous disassembly procedure. The amount of screws you should be left with will be listed here also.
A box with a will also provide any possible helpful information. A box with a contains warnings.
Overview 2 - 1
Disassembly
NOTE: All disassembly procedures assume that the system is turned OFF, and disconnected from any power supply (the
battery is removed too).
Maintenance Tools
The following tools are recommended when working on the notebook PC:
• M3 Philips-head screwdriver
• M2.5 Philips-head screwdriver (magnetized)
• M2 Philips-head screwdriver
• Small flat-head screwdriver
• Pair of needle-nose pliers
• Anti-static wrist-strap
2.Disassembly
Connections
Connections within the computer are one of four types:
Locking collar sockets for ribbon connectors To release these connectors, use a small flat-head screwdriver to
gently pry the locking collar away from its base. When replac-
ing the connection, make sure the connector is oriented in the
same way. The pin1 side is usually not indicated.
Pressure sockets for multi-wire connectors To release this connector type, grasp it at its head and gently
rock it from side to side as you pull it out. Do not pull on the
wires themselves. When replacing the connection, do not try to
force it. The socket only fits one way.
Pressure sockets for ribbon connectors To release these connectors, use a small pair of needle-nose pli-
ers to gently lift the connector away from its socket. When re-
placing the connection, make sure the connector is oriented in
the same way. The pin1 side is usually not indicated.
Board-to-board or multi-pin sockets To separate the boards, gently rock them from side to side as
you pull them apart. If the connection is very tight, use a small
flat-head screwdriver - use just enough force to start.
2 - 2 Overview
Disassembly
Maintenance Precautions
The following precautions are a reminder. To avoid personal injury or damage to the computer while performing a removal and/or
replacement job, take the following precautions: Power Safety
1. Don't drop it. Perform your repairs and/or upgrades on a stable surface. If the computer falls, the case and other components Warning
could be damaged.
2. Don't overheat it. Note the proximity of any heating elements. Keep the computer out of direct sunlight. Before you undertake
3. Avoid interference. Note the proximity of any high capacity transformers, electric motors, and other strong magnetic fields. any upgrade proce-
These can hinder proper performance and damage components and/or data. You should also monitor the position of magnet- dures, make sure that
you have turned off the
ized tools (i.e. screwdrivers).
power, and discon-
4. Keep it dry. This is an electrical appliance. If water or any other liquid gets into it, the computer could be badly damaged.
nected all peripherals
5. Be careful with power. Avoid accidental shocks, discharges or explosions. and cables (including
•Before removing or servicing any part from the computer, turn the computer off and detach any power supplies. telephone lines and
•When you want to unplug the power cord or any cable/wire, be sure to disconnect it by the plug head. Do not pull on the wire. power cord). It is advis-
6. Peripherals – Turn off and detach any peripherals. able to also remove
2.Disassembly
7. Beware of static discharge. ICs, such as the CPU and main support chips, are vulnerable to static electricity. Before han- your battery in order to
dling any part in the computer, discharge any static electricity inside the computer. When handling a printed circuit board, do prevent accidentally
not use gloves or other materials which allow static electricity buildup. We suggest that you use an anti-static wrist strap turning the machine
instead. on.
8. Beware of corrosion. As you perform your job, avoid touching any connector leads. Even the cleanest hands produce oils
which can attract corrosive elements.
9. Keep your work environment clean. Tobacco smoke, dust or other air-born particulate matter is often attracted to charged
surfaces, reducing performance.
10. Keep track of the components. When removing or replacing any part, be careful not to leave small parts, such as screws,
loose inside the computer.
Cleaning
Do not apply cleaner directly to the computer, use a soft clean cloth.
Do not use volatile (petroleum distillates) or abrasive cleaners on any part of the computer.
(For Computer Models Supplied with Light Blue Cleaning Cloth) Some computer models in this series come supplied with a
light blue cleaning cloth. To clean the computer case with this cloth follow the instructions below.
• Power off the computer and peripherals.
• Disconnect the AC/DC adapter from the computer.
• Use a little water to dampen the cloth slightly.
• Clean the computer case with the cloth.
• Dry the computer with a dry cloth, or allow it time to dry before turning on.
• Reconnect the AC/DC adapter and turn the computer on.
Overview 2 - 3
Disassembly
Disassembly Steps
The following table lists the disassembly steps, and on which page to find the related information. PLEASE PERFORM
THE DISASSEMBLY STEPS IN THE ORDER INDICATED.
2 - 4 Disassembly Steps
Disassembly
2.Disassembly
a. b.
1 2 3 4
10 5
11 12
13
9 8 7 6
9 8 7 6
c.
13. Bottom Case
13
• 12 Screws
14
19 18
2.Disassembly
21
Powering the
Computer On e.
20
20. Battery
• 4 Screws
a. c.
1 2 3 4
2.Disassembly
13
10 5
11 12 14
9 8 7 6
b.
Hard Disk
13
13. Bottom Case
9 8 7 6 • 12 Screws
18
19
2.Disassembly
21
Powering the
Computer On e.
20
20. Battery
• 4 Screws
2.Disassembly
Powering the
a. c. Computer On
b. 4
4. HDD Assembly
3
2
• 1 Screw
5. Remove screws 6 - 7 and bracket 8 from the hard disk 9 (Figure 6d).
Figure 6 6. Reverse the process to install a new hard disk (do not forget to replace the screws).
HDD Assembly
Removal (cont’d.)
d.
d. Remove the screws and 6
bracket from the HDD. HDD System Warning
programs.
6. Bracket
7. HDD
• 2 Screws
2.Disassembly
a. b. c.
Contact Warning
2 2 Be careful not to touch
1
the metal pins on the
4 module’s connecting
edge. Even the cleanest
hands have oils which
can attract particles, and
degrade the module’s
3 3 performance.
Single Memory Module Installation
4. RAM Module
If your computer has a single memory mod-
ule, then insert the module into the Channel
0 (JDIMM1 / RAM1) socket.
a. c.
2.Disassembly
6
1 7
2 8
c.
b.
5
6 4. Eject Stick
3
3 6. Keyboard
cable to the “1 + 2”
socket (Figure 9b).
b.
5
4
2
3
5.Wireless LAN Module
• 1 Screw
2.Disassembly
LTE Broadband
LTE 2 Black Blue
Cable 1 is usually connected to antenna 1 (Main) on the module, and cable 2 to antenna 2 (Aux).
1
5
2.Disassembly
b.
2
5
3
5.4G Module
• 1 Screw
2.Disassembly
1
b.
2 3
3.M2 SATA Module
• 1 Screw
2 2
b.
4. LCD Front Cover
4 4
2 - 18
Disassembly
c. Disconnect
c. d. Remove the
ule.
d.
6
2.Disassembly
6. CCD Modu
2.Disassembly
Removing the CCD 2 - 21
Disassembly
2.Disassembly
Note: This section indicates the manufacturer’s part numbers. Your organization may use a different system, so be sure
to cross-check any relevant documentation.
Note: Some assemblies may have parts in common (especially screws). However, the part lists DO NOT indicate the
total number of duplicated parts used.
Note: Be sure to check any update notices. The parts shown in these illustrations are appropriate for the system at the
A.Part Lists
time of publication. Over the product life, some parts may be improved or re-configured, resulting in new part numbers.
A - 1
Part List Illustration Location
The following table indicates where to find the appropriate part list illustration.
Table A - 1
Part List Illustration
Part
Location
Top page A - 3
Bottom page A - 4
LCD page A - 5
HDD page A - 6
A.Part Lists
MB page A - 7
A - 2
Top
Figure A - 1
A.Part Lists
Top
Top A - 3
Bottom
Figure A - 2
Bottom
A.Part Lists
A - 4 Bottom
LCD
Figure A - 3
LCD
A.Part Lists
LCD A - 5
HDD
Figure A - 4
A.Part Lists
HDD
A - 6 HDD
MB
Figure A - 5
MB
A.Part Lists
MB A - 7
A.Part Lists
A - 8
Schematic Diagrams
B.Schematic Diagrams
Processor 3/12 - Page B - 5 ASM1543 - Page B - 21 3.3V, 5V, 3VS, 5VS, CTL - Page B - 37
Processor 4/12 - Page B - 6 LED KB, LED - Page B - 22 Charger, AC IN - Page B - 38
Processor 5/12 - Page B - 7 SATA HDD, TPM - Page B - 23 VCCIN - Page B - 39
Processor 6/12 - Page B - 8 Audio Codec - Page B - 24 RTL8411B - Page B - 40
Processor 7/12 - Page B - 9 KBC ITE IT5570 - Page B - 25 Multi Board RTS5227S / OZ711 - Page B - 41
Processor 8/12 - Page B - 10 WLAN - Page B - 26 LAN Transformer - Page B - 42 Version Note
Processor 9/12 - Page B - 11 M Key PCIE SSD - Page B - 27 LAN Board Connector - Page B - 43 The schematic dia-
grams in this chapter
Processor 10/12 - Page B - 12 3G/LTE - Page B - 28 14” I/O Board - Page B - 44
are based upon ver-
Processor 11/12 - Page B - 13 USB Type-A - Page B - 29 15” I/O Board 1 - Page B - 45 sion 6-7P-NL4M5-002.
If your mainboard (or
Processor 12/12 - Page B - 14 Conn, CCD, Fan, TP - Page B - 30 15” I/O Board 2 - Page B - 46
other boards) are a lat-
DDR4 SO-DIMM_A - Page B - 15 VDD3, VDD5 - Page B - 31 PWR Button Board - Page B - 47 er version, please
check with the Service
DDR4 SO-DIMM_B - Page B - 16 VDDQ, VDDQ_VTT, 1.8VA - Page B - 32 Power Sequence - Page B - 48
Center for updated di-
HDMI - Page B - 17 3.3VA, 1.8V - Page B - 33 agrams (if required).
B - 1
Schematic Diagrams
5 4 3 2 1
5 IN 1 6-7P-NL4M5-002
MAIN BOARD
SHEET 2~38 6-71-NL4M0-D02
NLx0MU Tiger LAKE UP3 System Block Diagram
LAN BOARD 3200MHz VDD3,VDD5
SHEET 39~42 6-71-NL4MZ-D02
DDIB DDR4 DDR4 SHEET 30
14" I/O BOARD 6-71-NL4M1-D01 HDMI 1.4SHEET 16
SYSTEM SMBUS SO-DIMM A
D
SHEET 43 SHEET 14 VDDQ,VDDQ_VTT D
Type-C 2.5V/VCCST/VCCSTG
SHEET 19
Tiger Lake
I/O BOARD SHEET 33
USB 2.0 TYPE A
eDP SHEET 17
DDIA PROCESSOR SHEET 43,44 USB2.0 port5 14"
SHEET 43
PWR_PD FUNCTION
SHEET 34
BIOS SPI RPGA1528 46x24mm HP USB 2.0 TYPE A
SENTELIC SHEET 5 MIC
Sheet 1 of 47 TOUCH PAD
SHEET 29
TPM
USB2.0 port3
USB2.0 port5
15"
SHEET 44,45
VCCIN_AUX
SHEET 35
System Block
C C
SHEET 22
3.3V,5V,3VS,5VS,CTL
Diagram I2C SHEET 36
EC Azalia Codec
ITE5570
ESPI HP AMP CM6542 SPK AMP CHARGER,AC IN
128pins LQFP 24MHz SA8908 SHEET 37
USB2.0 port6 TPA2008D2
14*14*1.6mm
SHEET 23
SHEET 24 VCCIN
SHEET 38
INT SPKER-R
INT. K/B EC SMBUS USB2.0 480Mbps
INT SPKER-L
D02 modify
SHEET 23
SHEET 24
THERMAL SMART SMART
SENSOR FAN BATTERY
AC-IN 32.768KHz 100 MHz
KB LED PCIE
B SHEET 2 SHEET 29 SHEET 37 SHEET 2~13 B
SHEET 21
24 MHz
SATA LAN Board
connector
SHEET 42
USB3.1
USB2.0 480Mbps
Colay INTEL LAN OZ711 /SD
non-VPRO:i219-V
ANX7443 ASM1543 VPRO:Intel i219-LM SHEET 40
SHEET 18 SHEET 20 M.2 3G/LTE WLAN M.2 SSD PCIe7
USB 3.1 Gen2 TYPE A USB3.1 port4 M.2 CNVI PCIE 4
SHEET 39
HDD W/O DP PCIE10 CPU
USB3.1 port1 USB 3.1 Gen2 TYPE C USB2.0 port4 SHEET 26
SHEET 22
USB2.0 port1 Colay USB3.1 port2 SHEET 27 SHEET 25
ANX7411
SHEET 28 SHEET 19 USB2.0 port2 LAN Transformer
SHEET 19
A
W/ DP SHEET 41 A
SIM Socket
CCD+INT MIC SHEET 44
USB2.0 port7 15" I/O BOARD ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
RGBIR CMR Title
SHEET 29 [01] BLOCK DIAGRAM
Size Document Number Rev
A3 NLx0MU 6-71-NLx0MU-D02 D02
Vinafix.com
Schematic Diagrams
Processor 1/12
5 4 3 2 1
U21A
B.Schematic Diagrams
HDMI PORT [16]
[16]
HDMI_DATA2P
HDMI_DATA2N Y9 DDIB_TXP_2 TCP1_AUX_P AF5
T9 DDIB_TXN_2 TCP1_AUX
[16] HDMI_DATA1P DDIB_TXP_1
DIFF=85ohm [16] HDMI_DATA1N P9 BF1
V11 DDIB_TXN_1 TCP2_TXRX_P1 BF2
[16] HDMI_DATA0P DDIB_TXP_0 TCP2_TXRX_N1
[16] HDMI_DATA0N V9 BE2
DDIB_TXN_0 TCP2_TXRX_P0 BE1
AB9 TCP2_TXRX_N0 BD7
3.3VS AD9 DDIB_AUX_P TCP2_TX_P1 BD5
DDIB_AUX TCP2_TX_N1 AY5
R260 2.2K_04 HDMI_CTRLCLK HDMI_CTRLCLK DM29 TCP2_TX_P0 AY7
[16] HDMI_CTRLCLK HDMI_CTRLDATA GPP_H16/DDPB_CTRLCLK/PCIE_LNK_DOWN TCP2_TX_N0
[16] HDMI_CTRLDATA DK27 BB5
R261 2.2K_04 HDMI_CTRLDATA GPP_H17/DDPB_CTRLDATA TCP2_AUX_P BB7
DG43 TCP2_AUX
Enable HDMI setting [16] HDMI_HPD GPP_A18/DDSP_HPDB/DISP_MISCB/I2S4_RXD BK1
DG47 TCP3_TXRX_P1 BK2
DJ47 GPP_A21/DDPC_CTRLCLK/I2S5_TXD TCP3_TXRX_N1 BJ2
Sheet 2 of 47
[19] ANX7411_TEST_R GPP_A22/DDPC_CTRLDATA/I2S5_RXD TCP3_TXRX_P0
C BJ1 C
DU8 TCP3_TXRX_N0 BM7
GPP_E19 DV8 GPP_E18/DDP1_CTRLCLK/TBT_LSX0_TXD TCP3_TX_P1 BM5
GPP_E19/DDP1_CTRLDATA/TBT_LSX0_RXD TCP3_TX_N1 BH5
Processor 1/12
DF6 TCP3_TX_P0 BH7
GPP_E21 DD6 GPP_E20/DDP2_CTRLCLK/TBT_LSX1_TXD TCP3_TX_N0 BK5
GPP_E21/DDP2_CTRLDATA/TBT_LSX1_RXD TCP3_AUX_P BK7
DN23 TCP3_AUX
T15 GPP_D10 GPP_D9/ISH_SPI_CS#/DDP3_CTRLCLK/TBT_LSX2_TXD/GSPI2_CS0# TC_RCOMP_P
3.3VS R256 10K_04 DM23 AN2 R430 150_1%_04
NL40MU GPP_D10/ISH_SPI_CLK/DDP3_CTRLDATA/TBT_LSX2_RXD/GSPI2_CLK TC_RCOMP_P AN1 TC_RCOMP_N
R144 10K_04 BOARD_ID DK23 TC_RCOMP
NL50MU GPP_D12 DN21 GPP_D11/ISH_SPI_MISO/DDP4_CTRLCLK/TBT_LSX3_TXD/GSPI2_MISO M8 DSI_DE_TE_2 R45 100K_04
GPP_D12/ISH_SPI_MOSI/DDP4_CTRLDATA/TBT_LSX3_RXD/GSPI2_MOSI DSI_DE_TE_2
DF43 AB1 DP_RCOMP R50 150_1%_04
DF45 GPP_A17/DISP_MISCC/I2S4_TXD DDI_RCOMP
[19] ANX7411_HPD GPP_A19/DDSP_HPD1/DISP_MISC1/I2S5_SCLK EDP_DISP_UTIL
DF47 CE4 T36
GPP_A20/DDSP_HPD2/DISP_MISC2/I2S5_SFRM DISP_UTILS/DSI_DE_TE_1
R170 100K_04 USB_OC1# DH52
R172 100K_04 USB_OC2# DK45 GPP_A14/USB_OC1#/DDSP_HPD3/I2S3_RXD/DISP_MISC3/DMIC_CLK_B1
BOARD ID 3.3VA GPP_A15/USB_OC2#/DDSP_HPD4/DISP_MISC4/I2S4_SCLK
DM8
HIGH = NL40MU [17] NB_ENAVDD
DN8 EDP_VDDEN
[17] BLON EDP_BKLTEN
GPP_D11 [17] EDP_BRIGHTNESS
DG10
EDP_BKLTCTL
LOW = NL50MU
TGL_U_IP_EXT
B B
3.3VA 3.3VA
BOARD ID
20K_1%_04 *0.1u_10V_X5R_04
0 = DDP3 I2C / TBT_LSX2 pin at 1.8V 0 = DDP2 I2C / TBT_LSX1 pins at 1.8V
1 = DDP3 I2C / TBT_LSX2 pin at 3.3V
(internal PD 20K)
1 = DDP2 I2C / TBT_LSX1 pins at 3.3V
(internal PD 20K) ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Title
[02] TGL U -A / DDI,TCP
Size Document Number Rev
A3 6-71-NLx0MU-D02
A0
D02
Processor 1/12 B - 3
Schematic Diagrams
Processor 2/12
5 4 3 2 1
U21B
[14]
[14]
M_A_DQ_0_7
M_A_DQ_0_6
CP53
CP52 DDR0_DQ0_7/DDR0_DQ0_7/DDR0_DQ0_7
DDR0_DQ0_6/DDR0_DQ0_6/DDR0_DQ0_6
DDR0_CLK_P1/DDR3_CLK_P/DDR3_CLK_P/DDR3_CLK_P
DDR0_CLK_N1/DDR3_CLK_N/DDR3_CLK_N/DDR3_CLK
BT42
BT41
M_A_CLK_DDR1 [14]
M_A_CLK_DDR#1 [14]
CLOCK
[14] M_A_DQ_0_5 CP50 BP52
CP49 DDR0_DQ0_5/DDR0_DQ0_5/DDR0_DQ0_5 NC/DDR2_CLK_P/DDR2_CLK_P/DDR2_CLK_P BP53
[14] M_A_DQ_0_4 DDR0_DQ0_4/DDR0_DQ0_4/DDR0_DQ0_4 NC/DDR2_CLK_N/DDR2_CLK_N/DDR2_CLK
D [14] M_A_DQ_0_3 CU53 CD42 D
CU52 DDR0_DQ0_3/DDR0_DQ0_3/DDR0_DQ0_3 NC/DDR1_CLK_P/DDR1_CLK_P/DDR1_CLK_P CD41
[14] M_A_DQ_0_2 DIFF=85ohm
CU50 DDR0_DQ0_2/DDR0_DQ0_2/DDR0_DQ0_2 NC/DDR1_CLK_N/DDR1_CLK_N/DDR1_CLK CC52
[14] M_A_DQ_0_1 DDR0_DQ0_1/DDR0_DQ0_1/DDR0_DQ0_1 DDR0_CLK_P0/DDR0_CLK_P/DDR0_CLK_P/DDR0_CLK_P M_A_CLK_DDR0 [14]
[14] M_A_DQ_0_0 CU49 CC53 M_A_CLK_DDR#0 [14]
CH53 DDR0_DQ0_0/DDR0_DQ0_0/DDR0_DQ0_0 DDR0_CLK_N0/DDR0_CLK_N/DDR0_CLK_N/DDR0_CLK
[14] M_A_DQ_1_7 DDR0_DQ1_7/DDR0_DQ1_7/DDR0_DQ1_7 DDR4/LP4/LP5/LP5 CMD Flip
[14] M_A_DQ_1_6 CH52 BT45
CH50 DDR0_DQ1_6/DDR0_DQ1_6/DDR0_DQ1_6 NC/DDR3_CKE0/DDR3_WCK_P/DDR3_WCK_P BT47
[14] M_A_DQ_1_5 DDR0_DQ1_5/DDR0_DQ1_5/DDR0_DQ1_5 NC/DDR3_CKE1/DDR3_WCK_N/DDR3_WCK
[14] M_A_DQ_1_4 CH49 BN51
CL53 DDR0_DQ1_4/DDR0_DQ1_4/DDR0_DQ1_4 NC/DDR2_CKE0/DDR2_WCK_P/DDR2_WCK_P BN53
[14] M_A_DQ_1_3 DDR0_DQ1_3/DDR0_DQ1_3/DDR0_DQ1_3 NC/DDR2_CKE1/DDR2_WCK_N/DDR2_WCK
[14] M_A_DQ_1_2 CL52 CD45
CL50 DDR0_DQ1_2/DDR0_DQ1_2/DDR0_DQ1_2 NC/DDR1_CKE0/DDR1_WCK_P/DDR1_WCK_P CD47
[14] M_A_DQ_1_1 DDR0_DQ1_1/DDR0_DQ1_1/DDR0_DQ1_1 NC/DDR1_CKE1/DDR1_WCK_N/DDR1_WCK
[14] M_A_DQ_1_0 CL49 CA51
CT47 DDR0_DQ1_0/DDR0_DQ1_0/DDR0_DQ1_0 NC/DDR0_CKE0/DDR0_WCK_P/DDR0_WCK_P CA53
[14] M_A_DQ_2_7 DDR1_DQ0_7/DDR0_DQ2_7/DDR1_DQ0_7 NC/DDR0_CKE1/DDR0_WCK_N/DDR0_WCK
[14] M_A_DQ_2_6 CV47 DDR4/LP4/LP5/LP5 CMD Flip
CT45 DDR1_DQ0_6/DDR0_DQ2_6/DDR1_DQ0_6 BU52
B.Schematic Diagrams
[14]
[14]
[14]
M_A_DQ_2_5
M_A_DQ_2_4
M_A_DQ_2_3
CV45
CT42
DDR1_DQ0_5/DDR0_DQ2_5/DDR1_DQ0_5
DDR1_DQ0_4/DDR0_DQ2_4/DDR1_DQ0_4
DDR1_DQ0_3/DDR0_DQ2_3/DDR1_DQ0_3
DDR0_CKE1/DDR2_CA4/DDR2_CA5/DDR2_CA1
DDR0_CKE0/DDR2_CA5/DDR2_CA6/DDR2_CA0
DDR4/LP4/LP5/LP5 CMD Flip
BL50
M_A_CKE1
M_A_CKE0
[14]
[14] CTRL
[14] M_A_DQ_2_2 CV42 CF42 M_A_CS#1 [14]
CT41 DDR1_DQ0_2/DDR0_DQ2_2/DDR1_DQ0_2 DDR0_CS1/DDR1_CA1/DDR1_CA1/DDR1_CA5 CF47
[14] M_A_DQ_2_1 M_A_CS#0 [14] SINGLE=45ohm
CV41 DDR1_DQ0_1/DDR0_DQ2_1/DDR1_DQ0_1 DDR0_CS0/NC/DDR1_CS1/DDR1_CA4
DATA [14] M_A_DQ_2_0
CK47 DDR1_DQ0_0/DDR0_DQ2_0/DDR1_DQ0_0 DDR4/LP4/LP5/LP5 CMD Flip
CE53
[14] M_A_DQ_3_7 DDR1_DQ1_7/DDR0_DQ3_7/DDR1_DQ1_7 NC/DDR0_CA0/DDR0_CA0/DDR0_CA6
[14] M_A_DQ_3_6 CM47 CE50
CK45 DDR1_DQ1_6/DDR0_DQ3_6/DDR1_DQ1_6 NC/DDR0_CA1/DDR0_CA1/DDR0_CA5 BL53
SINGLE=50ohm [14] M_A_DQ_3_5
Sheet 3 of 47
CM45 DDR1_DQ1_5/DDR0_DQ3_5/DDR1_DQ1_5 NC/DDR2_CS0/DDR2_CA2/DDR2_CA2 BP47
[14] M_A_DQ_3_4 DDR1_DQ1_4/DDR0_DQ3_4/DDR1_DQ1_4 NC/DDR3_CA5/DDR3_CA6/DDR3_CA0
[14] M_A_DQ_3_3 CK42 BP42
CM42 DDR1_DQ1_3/DDR0_DQ3_3/DDR1_DQ1_3 NC/DDR3_CA4/DDR3_CA5/DDR3_CA1 BP45
[14] M_A_DQ_3_2 DDR1_DQ1_2/DDR0_DQ3_2/DDR1_DQ1_2 NC/DDR3_CA3/DDR3_CA4/DDR3_CS1
CM41 BP44
Processor 2/12
[14] M_A_DQ_3_1 DDR1_DQ1_1/DDR0_DQ3_1/DDR1_DQ1_1 NC/DDR3_CA2/DDR3_CA3/DDR3_CS0 M_A_DQS[7:0] [14]
[14] M_A_DQ_3_0 CK41 LP4-LP5(NIL)/DDR4 (NIL)/DDR4 (IL)
BF53 DDR1_DQ1_0/DDR0_DQ3_0/DDR1_DQ1_0 BB44 M_A_DQS7
C
[14]
[14]
[14]
M_A_DQ_4_7
M_A_DQ_4_6
M_A_DQ_4_5
BF52
BF50
DDR2_DQ0_7/DDR0_DQ4_7/DDR0_DQ2_7
DDR2_DQ0_6/DDR0_DQ4_6/DDR0_DQ2_6
DDR2_DQ0_5/DDR0_DQ4_5/DDR0_DQ2_5
DDR3_DQSP_1/DDR0_DQSP_7/DDR1_DQSP_3
DDR3_DQSN_1/DDR0_DQSN_7/DDR1_DQSN_3
DDR3_DQSP_0/DDR0_DQSP_6/DDR1_DQSP_2
BD44
BK44
M_A_DQS#7
M_A_DQS6
M_A_DQS#[7:0] [14]
STROBE C
R21
TGL_U_IP_EXT
A 100_1%_04 A
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Title
[03] TGL U -B / DDR CHA
Size Document Number Rev
A3 6-71-NLx0MU-D02
A0
D02
B - 4 Processor 2/12
Schematic Diagrams
Processor 3/12
5 4 3 2 1
U21C
D
[15]
[15]
M_B_DQ_0_7
M_B_DQ_0_6
AL53
AL52 DDR4_DQ0_7/DDR1_DQ0_7/DDR0_DQ4_7
DDR4_DQ0_6/DDR1_DQ0_6/DDR0_DQ4_6
DDR1_CLK_P1/DDR7_CLK_P/DDR7_CLK_P/DDR7_CLK_P
DDR1_CLK_N1/DDR7_CLK_N/DDR7_CLK_N/DDR7_CLK
R41
R42
M_B_CLK_DDR1 [15]
M_B_CLK_DDR#1 [15]
CLOCK D
[15] M_B_DQ_0_5 AL50 M52
AL49 DDR4_DQ0_5/DDR1_DQ0_5/DDR0_DQ4_5 NC/DDR6_CLK_P/DDR6_CLK_P/DDR6_CLK_P M53
[15] M_B_DQ_0_4 DDR4_DQ0_4/DDR1_DQ0_4/DDR0_DQ4_4 NC/DDR6_CLK_N/DDR6_CLK_N/DDR6_CLK
[15] M_B_DQ_0_3 AP53 AC42
AP52 DDR4_DQ0_3/DDR1_DQ0_3/DDR0_DQ4_3 NC/DDR5_CLK_P/DDR5_CLK_P/DDR5_CLK_P AC41
[15] M_B_DQ_0_2 DIFF=85ohm
AP50 DDR4_DQ0_2/DDR1_DQ0_2/DDR0_DQ4_2 NC/DDR5_CLK_N/DDR5_CLK_N/DDR5_CLK Y52
[15] M_B_DQ_0_1 DDR4_DQ0_1/DDR1_DQ0_1/DDR0_DQ4_1 DDR1_CLK_P0/DDR4_CLK_P/DDR4_CLKP/DDR4_CLK_P M_B_CLK_DDR0 [15]
[15] M_B_DQ_0_0 AP49 Y53 M_B_CLK_DDR#0 [15]
AF53 DDR4_DQ0_0/DDR1_DQ0_0/DDR0_DQ4_0 DDR1_CLK_N0/DDR4_CLK_N/DDR4_CLK_N/DDR4_CLK
[15] M_B_DQ_1_7 DDR4_DQ1_7/DDR1_DQ1_7/DDR0_DQ5_7 DDR4/LP4/LP5/LP5 CMD Flip
[15] M_B_DQ_1_6 AF52 R47
AF50 DDR4_DQ1_6/DDR1_DQ1_6/DDR0_DQ5_6 NC/DDR7_CKE0/DDR7_WCK_P/DDR7_WCK_P R45
[15] M_B_DQ_1_5 DDR4_DQ1_5/DDR1_DQ1_5/DDR0_DQ5_5 NC/DDR7_CKE1/DDR7_WCK_N/DDR7_WCK
[15] M_B_DQ_1_4 AF49 K51
AH53 DDR4_DQ1_4/DDR1_DQ1_4/DDR0_DQ5_4 NC/DDR6_CKE0/DDR6_WCK_P/DDR6_WCK_P K53
[15] M_B_DQ_1_3 DDR4_DQ1_3/DDR1_DQ1_3/DDR0_DQ5_3 NC/DDR6_CKE1/DDR6_WCK_N/DDR6_WCK
[15] M_B_DQ_1_2 AH52 AC47
AH50 DDR4_DQ1_2/DDR1_DQ1_2/DDR0_DQ5_2 NC/DDR5_CKE0/DDR5_WCK_P/DDR5_WCK_P AC45
[15] M_B_DQ_1_1 DDR4_DQ1_1/DDR1_DQ1_1/DDR0_DQ5_1 NC/DDR5_CKE1/DDR5_WCK_N/DDR5_WCK
[15] M_B_DQ_1_0 AH49 W51
DDR4_DQ1_0/DDR1_DQ1_0/DDR0_DQ5_0 NC/DDR4_CKE0/DDR4_WCK_P/DDR4_WCK_P
B.Schematic Diagrams
[15] M_B_DQ_2_7 AR41 W53
AV42 DDR5_DQ0_7/DDR1_DQ2_7/DDR1_DQ4_7 NC/DDR4_CKE1/DDR4_WCK_N/DDR4_WCK
[15] M_B_DQ_2_6 DDR5_DQ0_6/DDR1_DQ2_6/DDR1_DQ4_6 DDR4/LP4/LP5/LP5 CMD Flip
AR42 P52
[15]
[15]
[15]
M_B_DQ_2_5
M_B_DQ_2_4
M_B_DQ_2_3
AV41
AR45
DDR5_DQ0_5/DDR1_DQ2_5/DDR1_DQ4_5
DDR5_DQ0_4/DDR1_DQ2_4/DDR1_DQ4_4
DDR5_DQ0_3/DDR1_DQ2_3/DDR1_DQ4_3
DDR1_CKE1/DDR6_CA4/DDR6_CA5/DDR6_CA1
DDR1_CKE0/DDR6_CA5/DDR6_CA6/DDR6_CA0
DDR4/LP4/LP5/LP5 CMD Flip
J50
M_B_CKE1
M_B_CKE0
[15]
[15] CTRL
[15] M_B_DQ_2_2 AV45 AE42 M_B_CS#1 [15]
AR47 DDR5_DQ0_2/DDR1_DQ2_2/DDR1_DQ4_2 DDR1_CS1/DDR5_CA1/DDR4_CA1/DDR4_CA5 AE47
[15] M_B_DQ_2_1 M_B_CS#0 [15] SINGLE=45ohm
AV47 DDR5_DQ0_1/DDR1_DQ2_1/DDR1_DQ4_1 DDR1_CS0/NC/DDR4_CS1/DDR4_CA4
[15] M_B_DQ_2_0 DDR5_DQ0_0/DDR1_DQ2_0/DDR1_DQ4_0 DDR4/LP4/LP5/LP5 CMD Flip
[15] M_B_DQ_3_7 AJ41 N42
AJ42 DDR5_DQ1_7/DDR1_DQ3_7/DDR1_DQ5_7 NC/DDR7_CA5/DDR7_CA6/DDR7_CA0 N45
[15] M_B_DQ_3_6 DDR5_DQ1_6/DDR1_DQ3_6/DDR1_DQ5_6 NC/DDR7_CA4/DDR7_CA5/DDR7_CA1
AL41 N44
DATA [15] M_B_DQ_3_5
AL42 DDR5_DQ1_5/DDR1_DQ3_5/DDR1_DQ5_5 NC/DDR7_CA3/DDR7_CA4/DDR7_CS1 N47
[15] M_B_DQ_3_4
Sheet 4 of 47
AJ45 DDR5_DQ1_4/DDR1_DQ3_4/DDR1_DQ5_4 NC/DDR7_CA2/DDR7_CA3/DDR7_CS0 J53
[15] M_B_DQ_3_3 DDR5_DQ1_3/DDR1_DQ3_3/DDR1_DQ5_3 NC/DDR6_CS0/DDR6_CA2/DDR6_CA2
SINGLE=50ohm [15] M_B_DQ_3_2 AJ47 AC50
C AL45 DDR5_DQ1_2/DDR1_DQ3_2/DDR1_DQ5_2 NC/DDR4_CA1/DDR4_CA1/DDR4_CA5 AC53 C
[15] M_B_DQ_3_1 DDR5_DQ1_1/DDR1_DQ3_1/DDR1_DQ5_1 NC/DDR4_CA0/DDR4_CA0/DDR4_CA6 M_B_DQS[7:0] [15]
AL47
Processor 3/12
[15] M_B_DQ_3_0 DDR5_DQ1_0/DDR1_DQ3_0/DDR1_DQ5_0 LP4-LP5(NIL)/DDR4 (NIL)/DDR4 (IL) M_B_DQS7
A43 K36
[15]
[15]
[15]
M_B_DQ_4_7
M_B_DQ_4_6
M_B_DQ_4_5
B43
D43
DDR6_DQ0_7/DDR1_DQ4_7/DDR0_DQ6_7
DDR6_DQ0_6/DDR1_DQ4_6/DDR0_DQ6_6
DDR6_DQ0_5/DDR1_DQ4_5/DDR0_DQ6_5
DDR7_DQSP_1/DDR1_DQSP_7/DDR1_DQSP_7
DDR7_DQSN_1/DDR1_DQSN_7/DDR1_DQSN_7
DDR7_DQSP_0/DDR1_DQSP_6/DDR1_DQSP_6
K38
G44
M_B_DQS#7
M_B_DQS6 M_B_DQS#[7:0] [15] STROBE
E44 J44 M_B_DQS#6 M_B_DQS#0
[15] M_B_DQ_4_4 DDR6_DQ0_4/DDR1_DQ4_4/DDR0_DQ6_4 DDR7_DQSN_0/DDR1_DQSN_6/DDR1_DQSN_6 M_B_DQS5 M_B_DQS#1
[15] M_B_DQ_4_3 A46 D39
B46 DDR6_DQ0_3/DDR1_DQ4_3/DDR0_DQ6_3 DDR6_DQSP_1/DDR1_DQSP_5/DDR0_DQSP_7 C39 M_B_DQS#5 M_B_DQS#2
[15] M_B_DQ_4_2 DIFF=90ohm
D46 DDR6_DQ0_2/DDR1_DQ4_2/DDR0_DQ6_2 DDR6_DQSN_1/DDR1_DQSN_5/DDR0_DQSN_7 C45 M_B_DQS4 M_B_DQS#3
[15] M_B_DQ_4_1 DDR6_DQ0_1/DDR1_DQ4_1/DDR0_DQ6_1 DDR6_DQSP_0/DDR1_DQSP_4/DDR0_DQSP_6 M_B_DQS#4 M_B_DQS#4
[15] M_B_DQ_4_0 E47 D45
E38 DDR6_DQ0_0/DDR1_DQ4_0/DDR0_DQ6_0 DDR6_DQSN_0/DDR1_DQSN_4/DDR0_DQSN_6 AJ44 M_B_DQS3 M_B_DQS#5
[15] M_B_DQ_5_7 DDR6_DQ1_7/DDR1_DQ5_7/DDR0_DQ7_7 DDR5_DQSP_1/DDR1_DQSP_3/DDR1_DQSP_5 M_B_DQS#3 M_B_DQS#6
[15] M_B_DQ_5_6 D38 AL44
B38 DDR6_DQ1_6/DDR1_DQ5_6/DDR0_DQ7_6 DDR5_DQSN_1/DDR1_DQSN_3/DDR1_DQSN_5 AV44 M_B_DQS2 M_B_DQS#7
[15] M_B_DQ_5_5 DDR6_DQ1_5/DDR1_DQ5_5/DDR0_DQ7_5 DDR5_DQSP_0/DDR1_DQSP_2/DDR1_DQSP_4 M_B_DQS#2
[15] M_B_DQ_5_4 A38 AR44
E41 DDR6_DQ1_4/DDR1_DQ5_4/DDR0_DQ7_4 DDR5_DQSN_0/DDR1_DQSN_2/DDR1_DQSN_4 AG51 M_B_DQS1
[15] M_B_DQ_5_3 DDR6_DQ1_3/DDR1_DQ5_3/DDR0_DQ7_3 DDR4_DQSP_1/DDR1_DQSP_1/DDR0_DQSP_5 M_B_DQS#1
[15] M_B_DQ_5_2 D40 AG50
B40 DDR6_DQ1_2/DDR1_DQ5_2/DDR0_DQ7_2 DDR4_DQSN_1/DDR1_DQSN_1/DDR0_DQSN_5 AN51 M_B_DQS0
[15] M_B_DQ_5_1 DDR6_DQ1_1/DDR1_DQ5_1/DDR0_DQ7_1 DDR4_DQSP_0/DDR1_DQSP_0/DDR0_DQSP_4 M_B_DQS#0
[15] M_B_DQ_5_0 A40 AN50
G42 DDR6_DQ1_0/DDR1_DQ5_0/DDR0_DQ7_0 DDR4_DQSN_0/DDR1_DQSN_0/DDR0_DQSN_4
[15] M_B_DQ_6_7 DDR7_DQ0_7/DDR1_DQ6_7/DDR1_DQ6_7 DDR4/LP4/LP5/LP5 CMD Flip
G41 AE44
[15]
[15]
[15]
M_B_DQ_6_6
M_B_DQ_6_5
M_B_DQ_6_4
J41
J42
DDR7_DQ0_6/DDR1_DQ6_6/DDR1_DQ6_6
DDR7_DQ0_5/DDR1_DQ6_5/DDR1_DQ6_5
DDR7_DQ0_4/DDR1_DQ6_4/DDR1_DQ6_4
DDR1_ODT1/DDR5_CA0/DDR5_CA0/DDR5_CA6
DDR1_ODT0/DDR5_CS0/DDR5_CA2/DDR5_CA2
DDR4/LP4/LP5/LP5 CMD Flip
AE45
M_B_ODT1
M_B_ODT0
[15]
[15] CTRL
M_B_A[16:0] [15] SINGLE=45ohm
G45 AA47 M_B_A16
[15] M_B_DQ_6_3 DDR7_DQ0_3/DDR1_DQ6_3/DDR1_DQ6_3 DDR1_MA16/DDR5_CA4/DDR5_CA5/DDR5_CA1 M_B_A15
[15] M_B_DQ_6_2 J45 AA44
G47 DDR7_DQ0_2/DDR1_DQ6_2/DDR1_DQ6_2 DDR1_MA15/DDR5_CA3/DDR5_CA4/DDR5_CS1 AA45 M_B_A14
[15] M_B_DQ_6_1 DDR7_DQ0_1/DDR1_DQ6_1/DDR1_DQ6_1 DDR1_MA14/DDR5_CA2/DDR5_CA3/DDR5_CS0 M_B_A13
[15] M_B_DQ_6_0 J47 AE41
G38 DDR7_DQ0_0/DDR1_DQ6_0/DDR1_DQ6_0 DDR1_MA13/DDR5_CS1/DDR5_CS0/DDR5_CA3 P53 M_B_A12
B
[15]
[15]
[15]
M_B_DQ_7_7
M_B_DQ_7_6
M_B_DQ_7_5
G36
H36
DDR7_DQ1_7/DDR1_DQ7_7/DDR1_DQ7_7
DDR7_DQ1_6/DDR1_DQ7_6/DDR1_DQ7_6
DDR7_DQ1_5/DDR1_DQ7_5/DDR1_DQ7_5
DDR1_MA12/DDR6_CA1/DDR6_CA1/DDR6_CA5
DDR1_MA11/NC/DDR6_CS1/DDR6_CA4
DDR1_MA10/DDR7_CA1/DDR7_CA1/DDR7_CA5
N51
U42
M_B_A11
M_B_A10 CMD B
H38 P50 M_B_A9
[15] M_B_DQ_7_4 DDR7_DQ1_4/DDR1_DQ7_4/DDR1_DQ7_4 DDR1_MA9/DDR6_CA0/DDR6_CA0/DDR6_CA6 M_B_A8
[15] M_B_DQ_7_3 N36 U53 SINGLE=45ohm
L36 DDR7_DQ1_3/DDR1_DQ7_3/DDR1_DQ7_3 DDR1_MA8/DDR4_CA2/DDR4_CA3/DDR4_CS0 W50 M_B_A7
[15] M_B_DQ_7_2 DDR7_DQ1_2/DDR1_DQ7_2/DDR1_DQ7_2 DDR1_MA7/DDR4_CA4/DDR4_CA5/DDR4_CA1 M_B_A6
[15] M_B_DQ_7_1 L38 U52
N38 DDR7_DQ1_1/DDR1_DQ7_1/DDR1_DQ7_1 DDR1_MA6/DDR4_CA3/DDR4_CA4/DDR4_CS1 U50 M_B_A5
[15] M_B_DQ_7_0 DDR7_DQ1_0/DDR1_DQ7_0/DDR1_DQ7_0 DDR1_MA5/DDR4_CA5/DDR4_CA6/DDR4_CA0 M_B_A4
AA51
DDR1_MA4/DDR4_CS0/DDR4_CA2/DDR4_CA2 AA53 M_B_A3
DDR1_MA3/DDR4_CS1/DDR4_CS0/DDR4_CA3 U47 M_B_A2
DDR1_MA2/DDR7_CS0/DDR7_CA2/DDR7_CA2 AC52 M_B_A1
DDR1_MA1/NC/DDR4_CS1/DDR4_CA4 U41 M_B_A0
DDR1_MA0/NC/DDR7_CS1/DDR7_CA4
DDR4/LP4/LP5/LP5 CMD Flip
K50 M_B_BG1 [15]
DDR1_BG1/DDR6_CA2/DDR6_CA3/DDR6_CS0 J52
DDR1_BG0/DDR6_CA3/DDR6_CA4/DDR6_CS1 M_B_BG0 [15]
DDR4/LP4/LP5/LP5 CMD Flip
AA42 M_B_BA1 [15]
DDR1_BA1/DDR5_CA5/DDR5_CA6/DDR5_CA0 U44
DDR1_BA0/DDR7_CA0/DDR7_CA0/DDR7_CA6 M_B_BA0 [15]
N53 M_B_ACT# [15]
DDR1_ACT#/DDR6_CS1/DDR6_CS0/DDR6_CA3
U45
DDR1_PAR/DDR7_CS1/DDR7_CS0/DDR7_CA3 DDR1_B_PARITY [15]
AU53
DDR1_ALERT# DDR1_B_ALERT# [15]
AU52
DDR1_VREF_CA DDR1_VREF_CA [15]
SINGLE=50ohm
TGL_U_IP_EXT
A A
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Title
[04] TGL U -C / DDR CHB
Size Document Number Rev
A3 6-71-NLx0MU-D02
A0
D02
Processor 3/12 B - 5
Schematic Diagrams
Processor 4/12
5 4 3 2 1
U21E
Sheet 5 of 47
PCH_GPP_E6 DN15 GPP_A6/ESPI_RESET# ESPI_RESET_N [24]
PCH_GPP_E10 DK13 GPP_F11/THC1_SPI2_CLK
PCH_GPP_E11 DM13 GPP_F15/GSXSRESET#/THC1_SPI2_IO3
GPP_C5 [22] SATA_PWR_EN FROM PCH GPP_F14/GSXDIN/THC1_SPI2_IO2
DN13
GPP_F13/GSXSLOAD/THC1_SPI2_IO1
Processor 4/12
DJ15
DK15 GPP_F12/GSXDOUT/THC1_SPI2_IO0
C R498 TPM 10K_04 DN10 GPP_F16/GSXCLK/THC1_SPI2_CS# C
3.3VS TPM_DET# GPP_F18/THC1_SPI2_INT#
R184 R174 R161 R481 W/O_TPM10K_04 DV14
GPP_F17/THC1_SPI2_RST#
*4.7K_04 *20K_04 *20K_04 DH3
DH4 CL_CLK
DF2 CL_DATA
CL_RST#
CPUNSSC CLOCK FREQ
HIGH: 19.2MHZ CLOCK FROM DIVIDER
TPM Type Detect (DERIVED FROM 38.4MHZ CRYSTAL)
TGL_U_IP_EXT LOW: 38.4MHZ CLOCK FROM DIRECT
CRYSTAL (DEFAULT)
PCH_GPP_F17 HIGH = TPM WEAK INTERNAL PD 20K
SAMPLING - RSMRSTB
Default
SPI_3.3V
BIOS+ME ROM R160
R299 0_04 R302 R303 R301
SPI_* = 1.5"~6.5" *4.7K_04
VDD3 C467 4.7K_04 100K_1%_04 100K_1%_04
0.1u_6.3V_X5R_02
R553 0_04 SPI_SI_R PCH_SPI_DQ2 PCH_SPI_DQ3 GPP_B23
U35
SPI_3.3V 8 5 SPI_SI
VDD SI
R309 RVP PULL20K 2 SPI_SO
1K_1%_04 SO
SPI_3.3V SPI_WP#_0 SPI_CS_0#
3 1
WP# CE#
B
R305 6 SPI_SCLK B
SPI0_CS2# 1K_1%_04 SCK
R300 *100K_04 SPI_HOLD#_0 7 4
HOLD# VSS
GD25B127DSIGR
PCB Footprint = M-SOP8B
256M-bit
GD 6-04-25127-470 GD25B127DSIGR
MXIC 6-04-25128-A77 MX25L12872FM2I-10G
XMC 6-04-25128-A78 XM25QH128A
U21D
2/11 short ↮
ⰼ⼴
枰䫱攟
, ᶼ 攟 ⹎ 旸 ⇞ <1"
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Title
[05] TGL U -D E / SPI,SMB,ESPI
Size Document Number Rev
Custom 6-71-NLx0MU-D02 D02
B - 6 Processor 4/12
Schematic Diagrams
Processor 5/12
5 4 3 2 1
STRAP PIN
1.8VA
0=>Disable “ No Reboot” mode. (Default)
Top Swap Override 1=>Enable “ No Reboot” mode (PCH will
disable the TCO Timer
LOW = Disable (Default) system reboot feature). This function is
D STP_A16OVR D
HIGH =Enable Top Swap mode R123 useful when running ITP/XDP.
*4.7K_04
R130 *4.7K_04 PCH_HDA_SPKR
3.3VS
PCH_GPP_B18
U21F
B.Schematic Diagrams
R191 0_04 PCH_GPP_B16 DC53 DR27
[26] SSD1_PW R_DN# GPP_B16/GSPI0_CLK GPP_D14/ISH_UART0_TXD
PCH_GPP_B18 DA51 DW27
DC49 GPP_B18/GSPI0_MOSI GPP_D13/ISH_UART0_RXD DV25
PCH_HDA_SPKR DC50 GPP_B17/GSPI0_MISO GPP_D16/ISH_UART0_CTS# DT25
DC52 GPP_B14/SPKR/TIME_SYNC1/GSPI0_CS1# GPP_D15/ISH_UART0_RTS#/GSPI2_CS1#/IMGCLKOUT5
GPP_B15/GSPI0_CS0# DB45 PCH_GPP_B6 R132 *2.2K_04
GPP_B6/ISH_I2C0_SCL PCH_GPP_B5 R131 3.3VS
For BIOS Debug CY49 DB44 *2.2K_04
VDD3 R121 *20K_04 PCH_GPP_B22 CY53 GPP_B20/GSPI1_CLK GPP_B5/ISH_I2C0_SDA
CY52 GPP_B22/GSPI1_MOSI CY39
R483 *10K_04 UART2_RXD R490 *0_06 DA50 GPP_B21/GSPI1_MISO GPP_B8/ISH_I2C1_SCL DB47 SB_BLON [17]
Sheet 6 of 47
GPP_B19/GSPI1_CS0# GPP_B7/ISH_I2C1_SDA
R499 *10K_04 UART2_TXD DV21 DD47
T17 GPP_C9/UART0_TXD GPP_B10/I2C5_SCL/ISH_I2C2_SCL
DT21 DD44 R205 10K_04 3.3VS
DR21 GPP_C8/UART0_RXD GPP_B9/I2C5_SDA/ISH_I2C2_SDA
Processor 5/12
GPP_C11/UART0_CTS# SB_KBCRST# [24]
㓦伖 B OT 朊 ㉮味⎗
㉱ 䶂 ⛘
㕡 DW21
GPP_C10/UART0_RTS# GPP_E16/ISH_GP7
DJ8
DR7 GPP_E15
R189
R198
*0_04
*10K_04
ALERT# [24]
GPP_E15/ISH_GP6 GPP_D18 3.3VS
C DV19 DR24 R255 *100K_04 3.3VS
C
DT19 GPP_C13/UART1_TXD/ISH_UART1_TXD GPP_D18/ISH_GP5 DU25
DR18 GPP_C12/UART1_RXD/ISH_UART1_RXD GPP_D17/ISH_GP4 DV31
GPP_C15/UART1_CTS#/ISH_UART1_CTS# GPP_D3/ISH_GP3/BK3/SBK3 GPP_D3_RTD3 [26]
3.3VS R503 10K_04 DU19 DU31
GPP_C14/UART1_RTS#/ISH_UART1_RTS# GPP_D2/ISH_GP2/BK2/SBK2 DT27 GPP_D1 R257 *100K_04
[22] TPM_PIRQ# UART2_TXD GPP_D1/ISH_GP1/BK1/SBK1 3.3VS
DJ21 DV27
R248 *100K_04 UART2_RXD DG23 GPP_C21/UART2_TXD GPP_D0/ISH_GP0/BK0/SBK0
3.3VA GPP_C20/UART2_RXD SD_RCOMP
[25] W LAN_W AKEUP# R247 *0_04 DJ19 DR51 R182 200_1%_04
DF21 GPP_C23/UART2_CTS# GPP_RCOMP
GPP_C22/UART2_RTS# DN33
GPP_T3 LAN_ID [29]
I2C_SCL_TP DV18 DT35
[29] I2C_SCL_TP GPP_C17/I2C0_SCL GPP_T2 LAN_RTD3_REL [29]
R230 2.2K_04 I2C_SDA_TP DW18
3.3V [29] I2C_SDA_TP GPP_C16/I2C0_SDA
R229 2.2K_04 DG17
DJ23 GPP_U5 DG19
[19] I2C1_SCL GPP_C19/I2C1_SCL GPP_U4 SDCARD_W AKE# [29]
DT18
[19] I2C1_SDA GPP_C18/I2C1_SDA
DJ29
DJ31 GPP_H5/I2C2_SCL
GPP_H4/I2C2_SDA
DF29
R471 *0_04 GPP_H7 DG29 GPP_H7/I2C3_SCL
[5,24] SW I# GPP_H6/I2C3_SDA
3.3VA R469 *10K_04
DF25
[25] CNVI_MFUART2_TXD GPP_H9/I2C4_SCL/CNV_MFUART2_TXD
DF27
[25] CNVI_MFUART2_RXD GPP_H8/I2C4_SDA/CNV_MFUART2_RXD
TGL_U_IP_EXT
B B
A A
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Title
[06] TGL U -F / GPIO,I2C,UART
Size Document Number Rev
A3 6-71-NLx0MU-D02
A0
D02
5 4 3 2 1
Processor 5/12 B - 7
Schematic Diagrams
Processor 6/12
5 4 3 2 1
STRAP PIN
Flash Descriptor Security Overide
1.8V/3.3V:GPIO_A B C D E F H R T U Low = Enable security measures defined in the Flash Descriptor.
(Default)
1.8V:GPIO_S High = Disable Flash Descriptor Security (override)
D 3.3V:GPD RB751S-40H
C
D38
A R536 1K_04
D
ME_W E [24]
20191111(D02B)
U21G
DG41 DV37
DT38 GPP_A23/I2S1_SCLK GPP_R3/HDA_SDI0/I2S0_RXD
DV38 GPP_R7/I2S1_SFRM DV41 HDA_RST#1
DW38 GPP_R6/I2S1_TXD GPP_R4/HDA_RST# DL53
GPP_R5/HDA_SDI1/I2S1_RXD GPP_A7/I2S2_SCLK/DMIC_CLK_A0 DG51
GPP_A8/I2S2_SFRM/CNV_RF_RESET#/DMIC_DATA_0 CNVI_RST# [25]
DN31 DG50
DM31 GPP_S6/SNDW3_CLK/DMIC_CLK_A0 GPP_A10/I2S2_RXD/DMIC_DATA1
GPP_S7/SNDW3_DATA/DMIC_DATA0 DL49
GPP_A9/I2S2_TXD/MODEM_CLKREQ/CRF_XTAL_CLKREQ/DMIC_CLK_A1 CNVI_CLKREQ [25]
DK33 DL52
Sheet 7 of 47
GPP_S4/SNDW2_CLK/DMIC_CLK_A1 GPP_A11/PMC_I2C_SDA/I2S3_SCLK INTP_OUT [19]
DK31
GPP_S5/SNDW2_DATA/DMIC_DATA1 DH49
GPP_A13/PMC_I2C_SCL/I2S3_TXD/DMIC_CLK_B0 PCH_BT_EN [25]
DW35
GPP_S2/SNDW1_CLK/DMIC_CLK_B0 SNDW _RCOMP
Processor 6/12
DV35 DF33 R137 200_1%_04
GPP_S3/SNDW1_DATA/DMIC_CLK_B1 SNDW_RCOMP
DT32
DR35 GPP_S0/SNDW0_CLK
U21S GPP_S1/SNDW0_DATA
C
⺈
⓮⺢ 嬘 3 /1 5 C
TGL_U_IP_EXT
R492 *0_02 HDA_SYNC#L
DF53 C53
RSVD_19 RSVD_23 R484 *0_02 HDA_BITCLK#L
T35 0=>Enable security measures defined
DF52 RSVD_24 E53 R488 *0_02 HDA_SDIN0
RSVD_20 RSVD_25 in the Flash Descriptor.(Default)
RSVD_26
CF39
1=>Disable Flash Descriptor R477 *0_02 HDA_RST#1
PCH_TP1 DT52 U35
T40 PCH_TP0 PCH_IST_TP_1 RSVD_27 Security (override).
T44 DU53 F53
PCH_IST_TP_0 RSVD_28 B53
DF50 RSVD_29 AP9 HDA_SDOUT_R R491 *2.2K_04
RSVD_21 RSVD_30 3.3VA
DF49 A52
RSVD_22 RSVD_31
CY30 BF12 U21T
CY15 RSVD_TP_25 RSVD_TP_28 V21
RSVD_TP_26 RSVD_TP_29 W20
D4 RSVD_TP_30 U37
RSVD_TP_27 RSVD_TP_31 CD39 T15 A51 NCTF_A51
IST_TP1 RSVD_TP_32 CFG_15 RSVD_TP_7 NCTF_B51 T33
T32 A6 U21 R49 *1K_04 CFG14 V17 B51 T34
IST_TP0 A4 IST_TP_1 RSVD_TP_33 CB39 U15 CFG_14 RSVD_TP_8
T28 IST_TP_0 RSVD_32 CFG_13 NCTF_C1
BB12 K11 C1 T26
RSVD_TP_34 W37 K12 CFG_12 RSVD_TP_9 D2 NCTF_D2
RSVD_TP_35 CFG_11 RSVD_TP_10 T27
AY12 K9
RSVD_TP_36 W38 T17 CFG_10 CP39
RSVD_TP_37 U38 K7 CFG_9 RSVD_TP_11 CU40
RSVD_TP_38 CY28 CFG7 H7 CFG_8 RSVD_TP_12 AK9
RSVD_TP_39 *1K_04 R44 T7 CFG6 K8 CFG_7 RSVD_12
*1K_04 R37 CFG5 H9 CFG_6 AH9
1K_04 R40 CFG4 E6 CFG_5 RSVD_13
TGL_U_IP_EXT CFG_4
CFG3 H5 DW6
B T8 CFG_3 RSVD_14 B
Ʉ CFG[0]: Stall reset sequence after E9
D9 CFG_2 RSVD_15
DV6
CFG_1
PCU PLL T6
CFG0 E7
CFG_0 RSVD_TP_13
DV4
NCTF_DW 3
DW3
lock until de-asserted: R416 49.9_1%_04 CFG_RCOMP B5 RSVD_TP_14 T37
CFG_RCOMP
— 1 = (Default) Normal Operation; No U17 RSVD_TP_15
DU1
DT2
stall. H11 CFG_17
CFG_16
RSVD_TP_16
DW2 NCTF_DW 2
— 0 = Stall. Y1 RSVD_TP_17 DV2 NCTF_DV2 T38
T16
Ʉ CFG[1]: Reserved configuration lane. M4 BPM#_3
BPM#_2
RSVD_TP_18
NCTF_E1
AB4 E1
Ʉ CFG[2]: PCI Express* Static x16 Lane T35 BPM#0 Y2 BPM#_1 RSVD_TP_19 F1 NCTF_F1 T31
T30
BPM#_0 RSVD_TP_20
Numbering Reversal. A3 AB2
— 1 = Normal operation B3 RSVD_6
RSVD_7
RSVD_16
DR1
— 0 = Lane numbers reversed. R436 2.2K_1%_04 MBIAS_RCOMP AR2 RSVD_TP_21 DR2
Ʉ CFG[3]: Reserved configuration lane. AL10 TCP0_MBIAS_RCOMP
RSVD_TP_2
RSVD_TP_22
AM12 DR53
Ʉ CFG[4]: eDP enable: AH12 RSVD_TP_3 RSVD_TP_23 DW5
RSVD_TP_4 RSVD_TP_24
— 1 = Disabled. AJ10
AR1 RSVD_TP_5 DV51
— 0 = Enabled. RSVD_TP_6 VSS_1
TP_3
DW52 NCTF_DW 52
T41
NCTF_DV53
Ʉ CFG[6:5]: PCI Express* Bifurcation BN10
BM12 RSVD_8 TP_4
DV53
W34
T43
— 00 = 1 x8, 2 x4 PCI Express* DD13 RSVD_9 RSVD_17 V35
DF13 RSVD_10 RSVD_18
A
— 01 = reserved RSVD_11 D52 SKTOCC# R29 10K_04 3.3VA A
SKTOCC#
— 10 = 2 x8 PCI Express*
— 11 = 1 x16 PCI Express* TGL_U_IP_EXT
Ʉ CFG[7]: PEG Training:
— 1 = (default) PEG Train immediately ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
following RESET# de assertion. Title
— 0 = PEG Wait for BIOS for training. [07] TGL U -G,S,T / SPI,SMB,ESPI
Ʉ CFG[19:8]: Reserved configuration Size Document Number Rev
lanes. A3 6-71-NLx0MU-D02
A0
D02
B - 8 Processor 6/12
Schematic Diagrams
Processor 7/12
5 4 3 2 1
B.Schematic Diagrams
CG5
CG4 PCIE9_RXP DC8
PCIE9_RXN USB2P_4 USB_PP4 [27]
DC7 USB_PN4 [27] 3G/LTE
CB8 USB2N_4
CB7 PCIE8_TXP DB4
PCIE8_TXN USB2P_3 USB_PP3 [29] USB B'd
CK5 DB3
CK4 PCIE8_RXP USB2N_3 USB_PN3 [29] USB port3 2.0 DIFF=85ohm
PCIE8_RXN DA5 M/B USB port2 (2.0+3.1)
Sheet 8 of 47
USB2P_2 USB_PP2 [19]
GLAN CD9 DA4
[29] PCIE_TXP7_GLAN
CD8 PCIE7_TXP USB2N_2 USB_PN2 [19] USB3.1 Colay Type C
GEN 2 [29] PCIE_TXN7_GLAN
CK1 PCIE7_TXN DC11
[29] PCIE_RXP7_GLAN PCIE7_RXP USB2P_1 USB_PP1 [28] M/B USB port1 (2.0+3.1)
C DIFF=85ohm CK2 DC9 C
Processor 7/12
[29] PCIE_RXN7_GLAN PCIE7_RXN USB2N_1 USB_PN1 [28] USB3.1 GEN2 Type-A
TGL_U_IP_EXT
U21H
P5 V5 PCIE4_TXP1_SSD [26]
[26] PCIE4_TXP3_SSD PCIE4_TX_P_3 PCIE4_TX_P_1
P7 V7 PCIE4_TXN1_SSD [26]
[26] PCIE4_TXN3_SSD PCIE4_TX_N_3 PCIE4_TX_N_1
N1 T1
[26] PCIE4_RXP3_SSD
N2 PCIE4_RX_P_3 PCIE4_RX_P_1 T2
PCIE4_RXP1_SSD [26] M.2 PCIE SSD X4
M.2 PCIE SSD X4 [26] PCIE4_RXN3_SSD PCIE4_RX_N_3 PCIE4_RX_N_1 PCIE4_RXN1_SSD [26]
GEN4
GEN4 [26] PCIE4_TXP2_SSD
T5
PCIE4_TX_P_2 PCIE4_TX_P_0
Y5
PCIE4_TXP0_SSD [26]
T7 Y7
[26] PCIE4_TXN2_SSD PCIE4_TX_N_2 PCIE4_TX_N_0 PCIE4_TXN0_SSD [26]
R1 V1
[26] PCIE4_RXP2_SSD PCIE4_RX_P_2 PCIE4_RX_P_0 PCIE4_RXP0_SSD [26]
R2 V2
[26] PCIE4_RXN2_SSD PCIE4_RX_N_2 PCIE4_RX_N_0 PCIE4_RXN0_SSD [26]
Y12 PCIE4_RCOMP_P R46 2.2K_1%_04
PCIE4_RCOMP_P V12 PCIE4_RCOMP_N
PCIE4_RCOMP V12
TGL_U_IP_EXT
A A
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Title
[08] TGL U -H,I / PCIE,USB
Size Document Number Rev
A3 NLx0MU 6-71-NLx0MU-D02
A0
D02
Date: W ednesday, August 18, 2021 Sheet 8 of 47
5 4 3 2 1
Processor 7/12 B - 9
Schematic Diagrams
Processor 8/12
5 4 3 2 1
U21J 1.8VA
Sheet 9 of 47
L16 CSI_B_DN_0
N16 CSI_B_CLK_P VCC_RTC
CSI_B_CLK
G14
Processor 8/12
H14 CSI_B_DP_2 C427 0.1u_6.3V_X5R_02
L14 CSI_B_DN_2
N14 CSI_B_DP_3
CSI_B_DN_3
CSI_RCOMP [10] SM_INTRUDER#
R287 1M_04 ijıŮ ŪŭŴ
R39 150_1%_04 K14
CSI_RCOMP
C C
DK25 C254
DM25 GPP_H23/IMGCLKOUT4 R296
GPP_H22/IMGCLKOUT3 0.1u_6.3V_X5R_02
DN25
PM_CLKRUN# DJ25 GPP_H21/IMGCLKOUT2 *1M_04
3.3VS R258 8.2K_04
GPP_H20/IMGCLKOUT1 VDD3
DR30
GPP_D4/IMGCLKOUT_0/BK4/SBK4 ijıŮ ŪŭŴ
A 1
[24] PM_CLKRUN# 3 C
SRTCRST# R285 20K_1%_04
TGL_U_IP_EXT A 2 RTC_VBAT_1
3.3VS
C244 ijıŮ ŪŭŴ
D37
1u_6.3V_X5R_04 BAT54CW H R539
CARD_CLKREQ# 1K_04
M.2 PCIE GEN4 X4 CLKPUT_PCIE0 CLKREQ0 R213 10K_04
WLAN CLKPUT_PCIE1 CLKREQ1
GLAN_CLKREQ# R221 10K_04 RTCRST# R286 20K_1%_04 J_RTC1
SDCARD CLKPUT_PCIE2 CLKREQ2
RTC_VBAT
LAN CLKPUT_PCIE3 CLKREQ3 SSD1_CLKREQ# 1
M.2 PCIE GEN3X4 / SATA CLKPUT_PCIE4 CLKREQ4 R274 10K_04 C248
2
1
1u_6.3V_X5R_04
W LAN_CLKREQ# R204 10K_04 JOPEN1 50271-0020N-001
*OPEN_10mil-1MM 85204-02R
6-20-43130-102
2
RTC CLEAR
WLAN_CLKREQ# PU 10K_04 IN PCH SIDE
U21K
Processor Pullups/Pull downs
BOTTOM
C397 10p_50V_NPO_04
BW1 DU14
BW2 CLKOUT_PCIE_P6 GPP_F19/SRCCLKREQ6# DF23
CLKOUT_PCIE_N6 GPP_H11/SRCCLKREQ5# DG25
B GPP_H10/SRCCLKREQ4# B
CB2 DT24 GLAN_CLKREQ#
CLKOUT_PCIE_P5 GPP_D8/SRCCLKREQ3# W LAN_CLKREQ# GLAN_CLKREQ# [29]
CB1 DT30 R461 X1
2
CLKOUT_PCIE_N5 GPP_D7/SRCCLKREQ2# CARD_CLKREQ# W LAN_CLKREQ# [25]
DV30 XTAL19001-X-022-3
GPP_D6/SRCCLKREQ1# SSD1_CLKREQ# CARD_CLKREQ# [29]
DW30
GPP_D5/SRCCLKREQ0# SSD1_CLKREQ# [26] 200K_1%_04
1
BW4 38.4Mhz
BW5 CLKOUT_PCIE_P4 DM1 XTAL38.4_OUT Use a shielded crystal GND and
CLKOUT_PCIE_N4 XTAL_OUT DL1 XTAL38.4_IN isolation external GND
CL7 XTAL_IN
[29] CLK_PCIE_GLAN CL8 CLKOUT_PCIE_P3 DW41 SUSCLK_R R504 33_04 C389 10p_50V_NPO_04
[29] CLK_PCIE_GLAN# CLKOUT_PCIE_N3 GPD8/SUSCLK SUS_CLK [25]
CB4 DT47 R507 *0_02 C439 *12p_50V_NPO_04
[25] CLK_PCIE_W LAN CB5 CLKOUT_PCIE_P2 RTCX2 DR47 R508 *0_02
[25] CLK_PCIE_W LAN# CLKOUT_PCIE_N2 RTCX1
2
BY4 DN37 RTCRST# R524 OSCAR 08_11_2020
[29] CLK_PCIE_CARD BY3 CLKOUT_PCIE_P1 RTCRST# DK37 *XDMCZLNDDD-0.032768MHz
SRTCRST# R509
[29] CLK_PCIE_CARD# CLKOUT_PCIE_N1 SRTCRST# X3
0_02 *10M_06 32.768KHz
CN7 6-22-32R76-0BN
1
[26] CLK_PCIE_SSD1 CN8 CLKOUT_PCIE_P0
[26] CLK_PCIE_SSD1# CLKOUT_PCIE_N0
PCIE GEN4 only use C440 *12p_50V_NPO_04
XCLK_BIASREF DJ5 GCLK_32K_RTC
XCLK_BIASREF
R152
TGL_U_IP_EXT GREEN CLOCK
60.4_1%_04 C435 0.1u_16V_X5R_02
C436 0.1u_16V_X5R_02
C451 0.1u_16V_X5R_02
C426 0.1u_16V_X5R_02
U28
15
VDD3 V3.3A GCLK_32K_RTC
A 2 9 R527 0_04 A
VDD3 VDD 32.768K
8 6
3 VIOE_19.2M 19.2M 4
VDD3 VIO_25M 25M
C419 15p_50V_NPO_04 12
NC 10 R528 330_04 RTC_VBAT
VRTC RTC_VBAT
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
4
1
16 C438 22u_6.3V_X5R_06
1 X2-OUT 11
GND
GND
GND
PAD
X2 X1-IN NC 14 R489 *0_04 Title
VOUT C425 2.2u_6.3V_X5R_04
VCC_RTC
[09] TGL U -J,K / CNVI,CLK,CSI
19001-X-016-3 SLG3NB3426VTR
5
7
13
17
6-22-25R00-1B6 Size Document Number R ev
6-71-NLx0MU-D02
3
2
5 4 3 2 1
B - 10 Processor 8/12
Schematic Diagrams
Processor 9/12
5 4 3 2 1
D
C420 0.1u_6.3V_X5R_02 SLP_SUS# R188 *10K_04 100K_1%_04
G Q26
2SK3018S3
S
C
U21L 100K_04
VCCST_OVERRIDE R446 B
Power sequence tCPU08 Q27
B.Schematic Diagrams
MMBT3904H
E
R485 0_04 SLP_SUS#_R DV49 BM9 PROCPW RGD R86 *1K_04 R449
[24,31] SLP_SUS# SLP_SUS# PROCPWRGD PW R_BTN#
DK41 100K_04
SLP_S5# GPD3/PWRBTN# PM_BATLOW # PW R_BTN# [24]
T13 DM43 DN41
SUSC#_PCH DJ41 GPD10/SLP_S5# GPD0/BATLOW# DK43 AC_PRESENT
[24] SUSC#_PCH SUSB#_PCH GPD5/SLP_S4# GPD1/ACPRESENT AC_PRESENT [24]
DJ43
[24] SUSB#_PCH SLP_A# GPD4/SLP_S3#
T42 DR41 CW40
T39 SLP_W LAN# DT44 GPD6/SLP_A# GPP_B11/PMCALERT# DN27 CPU_C10_GATE#
D02 modify Modern Standby
Sheet 10 of 47
GPD9/SPL_WLAN# GPP_H18/CPU_C10_GATE# CPU_C10_GATE# [24,33]
[24,33] SLP_S0# DG31 3.3VS
20210617 R142 100K_04 SLP_S0# DD42 GPP_H3/SX_EXIT_HOLDOFF# R259 *100K_04
DN39 GPP_B12/SLP_S0# DK39 VCCST
[29] PM_SLP_LAN# SLP_LAN# WAKE# PCIE_W AKE# [26]
Processor 9/12
EC_PCIE_WAKE# [24,25,29]
Modern Standby RSMRST# DM35 DM41 R220 *0_04
[10,24] RSMRST# SYS_RESET# RSMRST# GPD2/LAN_WAKE# LAN_DISABLE# LAN_W AKEUP# [29]
DD10 DT41
PLT_RST# SYS_RESET# GPD11/LANPHYPC/DSWLDO_MON LAN_DISABLE# [29] 3.3V
DD41 R88
GPP_B13/PLTRST# DN43 GPD7_REST
C PCH_DPW ROK_EC R196 *14mil_02 PCH_DPW ROK DK35 GPD7 1K_04 C
[24] PCH_DPW ROK_EC PCH_PW ROK_EC SYS_PW ROK DF10 DSW_PWROK VCCST_OVERRIDE
[24] PCH_PW ROK_EC R127 *14mil_02 CE5 R450 0_04
PCH_PW ROK DN35 SYS_PWROK VCCSTPWRGOOD_TCSS BP8 VCCST_PW RGD R87 60.4_1%_04 H_VCCST_PW RGD R91
PCH_PWROK VCCST_PWRGD BP9 R90 0_04 VCCST_OVERRIDE
VCCST_OVERRIDE
6
[9] SM_INTRUDER# DM37 Q7A D 1M_04
R208 4.7K_04 SPIVCCIOSEL DT49 INTRUDER# DR12 EXT_PW R_GATE# oscar 07_08_2020 MTDK3S6R
SPIVCCIOSEL GPP_F20/EXT_PWR_GATE# DW12 EXT_PW R_GATE2# R480 100K_04 G 2 VCCST_PG#
GPP_F21/EXT_PWR_GATE2# S Q7B
3
D MTDK3S6R
R497 *100K_04 3.3VS
TGL_U_IP_EXT ALL_SYS_PW RGD
C116 G 5
3.3V *0.01u_50V_X7R_04 S
4
3.3V
U29D
14
74LVC08APW U29A
14
R535
3.3V
3.3V 61.9K_1%_04 3.3V
U29C
14
U29B 74LVC08APW
14
5
7
3
7
R141
100K_04
3.3V
5
1
4
SUSB#_PCH SUSB# [10,17,23,28,33,36]
2 U6
74AHC1G08GW
3
R151
100K_04
A A
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Title
[10] TGL UP3 L POWER CONTROL
Size Document Number Rev
A3 NLx0MU 6-71-NLx0MU-D02
A0
D02
Date: W ednesday, August 18, 2021 Sheet 10 of 47
5 4 3 2 1
Processor 9/12 B - 11
Schematic Diagrams
Processor 10/12
5 4 3 2 1
U21M U21N
VCC_IN
36A 36A
A24
A26 VCCIN_1 VCCIN_66
G32
H24
VCORE SVID 36A AB12
AC10 VCCIN_AUX_1 VCCPRIM_1P8_1
CY18
CY20
A29
A30
VCCIN_2
VCCIN_3
VCCIN_67
VCCIN_68
H26
H30 VCC_IN
AE10
AK2
VCCIN_AUX_2
VCCIN_AUX_3
VCCPRIM_1P8_2
VCCPRIM_1P8_3
CY24
CY26
1.3A
A33
A35
VCCIN_4
VCCIN_5
VCCIN_6
VCCIN_69
VCCIN_70
VCCIN_71
H32
J1 㓦
伖 cp u側 朊 (T O
P朊) 14A AR10
AT12
VCCIN_AUX_4
VCCIN_AUX_5
VCCIN_AUX_6
VCCPRIM_1P8_4
VCCPRIM_1P8_5
VCCPRIM_1P8_6
DA18
DA20
1.8VA 1.8VA
AY39 J2 VCCIN_AUX AU10 DA22
B24 VCCIN_7 VCCIN_72 K1 AW10 VCCIN_AUX_7 VCCPRIM_1P8_7 DA24
B26 VCCIN_8 VCCIN_73 K2 C350 BV1 VCCIN_AUX_8 VCCPRIM_1P8_8 DA26 C187
VCCIN_9 VCCIN_74 C340 C119 C69 C99 C338 C84 C342 VCCIN_AUX_9 VCCPRIM_1P8_9
B29 K24 BV39 DC18 VDPHY_1P24 LDO_OUT_0P85
VCCIN_10 VCCIN_75 + VCCIN_AUX_10 VCCPRIM_1P8_10
10u_6.3V_X5R_04
B30 K26 BW40 DC20
VCCIN_11 VCCIN_76 VCCIN_AUX_11 VCCPRIM_1P8_11
PSLB30E227M
*22u_6.3V_X5R_06
*22u_6.3V_X5R_06
*22u_6.3V_X5R_06
22u_6.3V_X5R_06
22u_6.3V_X5R_06
22u_6.3V_X5R_06
22u_6.3V_X5R_06
B33 K30 BY39 DC22 C414 C416
B35 VCCIN_12 VCCIN_77 K32 CC1 VCCIN_AUX_12 VCCPRIM_1P8_12 DC24
VCCIN_13 VCCIN_78 VCCIN_AUX_13 VCCPRIM_1P8_13
4.7u_6.3V_X5R_04
2.2u_6.3V_X5R_04
BA10 L24 CD12 DC26
BA40 VCCIN_14 VCCIN_79 L26 CF10 VCCIN_AUX_14 VCCPRIM_1P8_14 DD20
D D
BB39 VCCIN_15 VCCIN_80 L30 CG12 VCCIN_AUX_15 VCCPRIM_1P8_15 DD22
BB9 VCCIN_16 VCCIN_81 L32 CH10 VCCIN_AUX_16 VCCPRIM_1P8_16 DV22
BC10 VCCIN_17 VCCIN_82 N24 CJ1 VCCIN_AUX_17 VCCPRIM_1P8_17
BC40 VCCIN_18 VCCIN_83 N26 CJ12 VCCIN_AUX_18 DA35 0.2A
VCCIN_19 VCCIN_84 VCCIN_AUX VCCIN_AUX_19 VCCPRIM_3P3_1 3.3VA
BD39 N30 CK10 DC28
BD9 VCCIN_20 VCCIN_85 N32 CL12 VCCIN_AUX_20 VCCPRIM_3P3_2 DC30
BE10 VCCIN_21 VCCIN_86 P24 CM10 VCCIN_AUX_21 VCCPRIM_3P3_3 DD30
BE40 VCCIN_22 VCCIN_87 P26 CP1 VCCIN_AUX_22 VCCPRIM_3P3_4
BF9 VCCIN_23 VCCIN_88 P28 VCC_IN PR27 CP10 VCCIN_AUX_23 DV34
VCCIN_24 VCCIN_89 VCCIN_AUX_24 DCPRTC VRTCEXT VCCA_LDO_1P8
BG10
BG40 VCCIN_25 VCCIN_90
P30
P32 㓦
伖 cp u側 朊 (T O
P朊) *100_04 CR12
CT10 VCCIN_AUX_25 DV46 LDO_OUT_0P85
BH12 VCCIN_26 VCCIN_91 T21 CU12 VCCIN_AUX_26 VCCLDOSTD_0P85
BH39 VCCIN_27 VCCIN_92 T23 C65 C98 C64 C77 C92 C37 C19 C118 C76 R70 *20mil_short_04 CY1 VCCIN_AUX_27 DV16 R197 0_06
VCCIN_28 VCCIN_93 [35] AUX_VCC_SENSE VCCIN_AUX_28 VCCA_CLKLDO_1P8_1 1.8VA
BH9 T25 AK1 DC15
VCCIN_29 VCCIN_94 VCCIN_AUX_29 VCCA_CLKLDO_1P8_2 C199 C190
1u_6.3V_X6S_04
1u_6.3V_X6S_04
1u_6.3V_X6S_04
1u_6.3V_X6S_04
1u_6.3V_X6S_04
1u_6.3V_X6S_04
1u_6.3V_X6S_04
1u_6.3V_X6S_04
1u_6.3V_X6S_04
BJ10 T27
BJ40 VCCIN_30 VCCIN_95 T31 R74 *20mil_short_04 AUX_VSS_SENSE_R AV9 DV28
VCCIN_31 VCCIN_96 [35] AUX_VSS_SENSE AUX_VCC_SENSE_R VCCIN_AUX_VSSSENSE VCCDPHY_1P24 VDPHY_1P24
22u_6.3V_X5R_06
22u_6.3V_X5R_06
BK39 U23 AT9
BL10 VCCIN_32 VCCIN_97 U27 VCCIN_AUX_VCCSENSE DD38
BL40 VCCIN_33 VCCIN_98 U29 R75 Sense Only 0.2A DD17 VCCDSW_1P05 VDSW_1P05
VCCIN_34 VCCIN_99 VNNEXT_1P05 VCC_VNNEXT_1P05_1
BM39 U31 *100_1%_04 DD18 BR3
BN40 VCCIN_35 VCCIN_100 U33 VCC_VNNEXT_1P05_2 VCC1P05_OUT_FET_1 BR4
BP12 VCCIN_36 VCCIN_101 V23 Sense Only 0.2A DA15 VCC1P05_OUT_FET_2 BT5
V1P05_OUT_FET
VCCIN_37 VCCIN_102 V1P05EXT VCC_V1P05EXT_1P05_1 VCC1P05_OUT_FET_3
BP39 V25 DA17
BR10 VCCIN_38 VCCIN_103 V27 VCC_V1P05EXT_1P05_2 DA31
B.Schematic Diagrams
Sheet 11 of 47
D33 P12 R24 220_04 H_CPU_SVIDALRT# [38] 100_1%_04
D35 VCCIN_53 VIDALERT# VRTCEXT VCC_RTC 3.3VA VDSW_1P05
VCCIN_54 TGL_U_IP_EXT
E24
C E26 VCCIN_55 R25 56_1%_04 C
VCCIN_56 VCCST
E27 OSCAR 07_24_2020
E29 VCCIN_57 R23 100_1%_04 C412 C189 C185 C186 C191
E30 VCCIN_58
CAD Note: the PU resistors close to CPU
Processor 10/12
VCCIN_59
0.1u_6.3V_X5R_02
0.1u_6.3V_X5R_02
1u_6.3V_X6S_04
0.1u_6.3V_X5R_02
1u_6.3V_X6S_04
E32
E33 VCCIN_60
G2 VCCIN_61 SVID Signals
G24 VCCIN_62
G26 VCCIN_63
G30 VCCIN_64
VCCIN_65
TGL_U_IP_EXT
C61 C78 C45 C91 C87 C142 C18 C140 C24 C58 C130 C53 C44 C14 C51 C86 C105 C48 C93 C28 C88 C36 C13 C122 C141 C17 C55 C367 C132 C156 C179 C157 C365 C361 C176 C155 C146 C67 C175 C59 C180 C178 C136 C158 C150 C54 C154 C376 C177 C167 C166 C358
10u_6.3V_X5R_04
10u_6.3V_X5R_04
10u_6.3V_X5R_04
10u_6.3V_X5R_04
10u_6.3V_X5R_04
10u_6.3V_X5R_04
*10u_6.3V_X5R_04
*10u_6.3V_X5R_04
*10u_6.3V_X5R_04
*10u_6.3V_X5R_04
*10u_6.3V_X5R_04
1u_6.3V_X6S_04
1u_6.3V_X6S_04
1u_6.3V_X6S_04
10u_6.3V_X5R_04
10u_6.3V_X5R_04
10u_6.3V_X5R_04
10u_6.3V_X5R_04
1u_6.3V_X6S_04
1u_6.3V_X6S_04
1u_6.3V_X6S_04
1u_6.3V_X6S_04
1u_6.3V_X6S_04
1u_6.3V_X6S_04
1u_6.3V_X6S_04
1u_6.3V_X6S_04
1u_6.3V_X6S_04
47u_6.3V_X5R_08
22u_6.3V_X5R_06
22u_6.3V_X5R_06
22u_6.3V_X5R_06
22u_6.3V_X5R_06
47u_6.3V_X5R_08
*47u_6.3V_X5R_08
22u_6.3V_X5R_06
22u_6.3V_X5R_06
22u_6.3V_X5R_06
22u_6.3V_X5R_06
22u_6.3V_X5R_06
22u_6.3V_X5R_06
22u_6.3V_X5R_06
22u_6.3V_X5R_06
10u_6.3V_X5R_04
10u_6.3V_X5R_04
10u_6.3V_X5R_04
10u_6.3V_X5R_04
10u_6.3V_X5R_04
10u_6.3V_X5R_04
10u_6.3V_X5R_04
10u_6.3V_X5R_04
10u_6.3V_X5R_04
10u_6.3V_X5R_04
B B
㓦
伖 cp u側 朊 (T O
P朊) 㓦
伖 cp u側 朊 (T O
P朊) 㓦
伖 cp u側 朊 (T O
P朊) 㓦
伖 cp u側 朊 (T O
P朊)
C343 C52 C25 C27 C39 C120 C73 C100 C102 C104 C21 C29 C57 C103 C121 C66 C355 C34 C128 C80 C79 C181 C135 C374
*22u_6.3V_X5R_06
*22u_6.3V_X5R_06
*22u_6.3V_X5R_06
22u_6.3V_X5R_06
22u_6.3V_X5R_06
22u_6.3V_X5R_06
*22u_6.3V_X5R_06
*22u_6.3V_X5R_06
*22u_6.3V_X5R_06
22u_6.3V_X5R_06
22u_6.3V_X5R_06
22u_6.3V_X5R_06
22u_6.3V_X5R_06
22u_6.3V_X5R_06
22u_6.3V_X5R_06
22u_6.3V_X5R_06
22u_6.3V_X5R_06
22u_6.3V_X5R_06
22u_6.3V_X5R_06
10u_6.3V_X5R_04
10u_6.3V_X5R_04
10u_6.3V_X5R_04
10u_6.3V_X5R_04
10u_6.3V_X5R_04
A A
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Title
[11] TGL U -M,N
Size Document Number Rev
Custom NLx0MU 6-71-NLx0MU-D02 D02
Date: Wednesday, August 18, 2021 Sheet 11 of 47
5 4 3 2 1
B - 12 Processor 10/12
Schematic Diagrams
Processor 11/12
5 4 3 2 1
VDDQ
1.5A AA39
VDD2_1 VCCSTG_OUT_1
AF9 A27
VSS_223 VSS_289
B19 BY44
VSS_109 VSS_169
CY44 DP53
VSS_2 VSS_46
K34
AB40 AF12 VCCSTG_OUT A32 B2 BY45 CY45 DR11 K48
AC39 VDD2_2 VCCSTG_1 AD12 A45 VSS_224 VSS_290 B23 BY47 VSS_110 VSS_170 CY47 DR16 VSS_3 VSS_47 K5
AD40 VDD2_3 VCCSTG_2 A49 VSS_225 VSS_291 B27 BY49 VSS_111 VSS_171 CY5 DR22 VSS_4 VSS_48 L22
AD51 VDD2_4 AN10 AA41 VSS_226 VSS_292 B32 BY9 VSS_112 VSS_172 D27 DR28 VSS_5 VSS_49 L28
AD52 VDD2_5 VCCSTG_OUT_2 AM9 AA48 VSS_227 VSS_293 B36 C13 VSS_113 VSS_173 D32 DR34 VSS_6 VSS_50 L34
D D
AE39 VDD2_6 VCCSTG_OUT_3 AG10 AB5 VSS_228 VSS_294 B39 C19 VSS_114 VSS_174 D36 DR40 VSS_7 VSS_51 L39
AF40 VDD2_7 VCCSTG_OUT_4 VCCIO_OUT AB7 VSS_229 VSS_295 B42 C23 VSS_115 VSS_175 D42 DR46 VSS_8 VSS_52 L41
AG39 VDD2_8 V15 AB8 VSS_230 VSS_296 B48 CA48 VSS_116 VSS_176 D49 DT4 VSS_9 VSS_53 L42
VDD2_9 VCCION_OUT VCCIO_OUT VSS_231 VSS_297 VSS_117 VSS_177 VSS_10 VSS_54
AH40 AC44 B52 CB41 D5 DT50 L44
AJ39 VDD2_10 M9 0.3A PC12 AC49 VSS_232 VSS_298 B8 CC10 VSS_118 VSS_178 DA30 DU11 VSS_11 VSS_55 L45
VDD2_11 VCCSTG_OUT_LGC VCCSTG_OUT_LGC VSS_233 VSS_299 VSS_119 VSS_179 VSS_12 VSS_56
AK40 0.1u_10V_X5R_04 AD4 BA48 CC3 DA33 DU16 L47
AK51 VDD2_12 BT2 0.5A AD48 VSS_234 VSS_300 BA53 CC5 VSS_120 VSS_180 DA53 DU22 VSS_13 VSS_57 L49
VDD2_13 VCCST_1 VCCST VSS_235 VSS_301 VSS_121 VSS_181 VSS_14 VSS_58
AK52 BT1 AD8 BB4 CD44 DC17 DU28 M1
AL39 VDD2_14 VCCST_2 BT4 AF4 VSS_236 VSS_302 BB8 CD48 VSS_122 VSS_182 DD15 DU34 VSS_15 VSS_59 M2
AM40 VDD2_15 VCCST_3 AF8 VSS_237 VSS_303 BC1 CD7 VSS_123 VSS_183 DD24 DU40 VSS_16 VSS_60 M50
AN39 VDD2_16 BP2 0.3A AG41 VSS_238 VSS_304 BC2 CE49 VSS_124 VSS_184 DD26 DU46 VSS_17 VSS_61 N22
VDD2_17 VCCSTG_3 VCCSTG VSS_239 VSS_305 VSS_125 VSS_185 VSS_18 VSS_62
AP40 BP1 AG42 BD12 CG48 DD28 DV1 N28
B.Schematic Diagrams
AR39 VDD2_18 VCCSTG_4 BP4 AG44 VSS_240 VSS_306 BD4 CG51 VSS_126 VSS_186 DD31 DV40 VSS_19 VSS_63 N34
AT52 VDD2_19 VCCSTG_5 AG45 VSS_241 VSS_307 BD48 CG52 VSS_127 VSS_187 DD33 DV52 VSS_20 VSS_64 N39
AU40 VDD2_20 AG47 VSS_242 VSS_308 BD8 CG9 VSS_128 VSS_188 DD35 DW51 VSS_21 VSS_65 N41
AW40 VDD2_21 VCCST VCCSTG AG48 VSS_243 VSS_309 BF39 CH41 VSS_129 VSS_189 DD39 E13 VSS_22 VSS_66 N48
AW51 VDD2_22 AG53 VSS_244 VSS_310 BF4 CH42 VSS_130 VSS_190 DD45 E19 VSS_23 VSS_67 P11
AW52 VDD2_23 AH4 VSS_245 VSS_311 BF41 CH44 VSS_131 VSS_191 DD51 E35 VSS_24 VSS_68 P14
BD51 VDD2_24 C372 C369 AH8 VSS_246 VSS_312 BF42 CH45 VSS_132 VSS_192 DD52 E48 VSS_25 VSS_69 P16
Sheet 12 of 47
BD52 VDD2_25 AK12 VSS_247 VSS_313 BF44 CH47 VSS_133 VSS_193 DE3 G22 VSS_26 VSS_70 P18
VDD2_26 VSS_248 VSS_314 VSS_134 VSS_194 VSS_27 VSS_71
1u_6.3V_X6S_04
1u_6.3V_X6S_04
BK51 AK4 BF45 CJ3 DE5 G28 P20
BK52 VDD2_27 AK48 VSS_249 VSS_315 BF47 CJ5 VSS_135 VSS_195 DF19 G34 VSS_28 VSS_72 P22
BV51 VDD2_28 AK5 VSS_250 VSS_316 BF5 CJ9 VSS_136 VSS_196 DF37 G39 VSS_29 VSS_73 P33
Processor 11/12
BV52 VDD2_29 AK7 VSS_251 VSS_317 BF7 CK39 VSS_137 VSS_197 DG15 G48 VSS_30 VSS_74 P35
CA40 VDD2_30 AK8 VSS_252 VSS_318 BF8 CK48 VSS_138 VSS_198 DG21 G51 VSS_31 VSS_75 P4
CC40 VDD2_31 AM1 VSS_253 VSS_319 BG48 CK53 VSS_139 VSS_199 DG27 G52 VSS_32 VSS_76 P49
CC49 VDD2_32 AM2 VSS_254 VSS_320 BG53 CL9 VSS_140 VSS_200 DG33 H12 VSS_33 VSS_77 P8
CC50 VDD2_33 AM4 VSS_255 VSS_321 BH1 CN12 VSS_141 VSS_201 DG39 H22 VSS_34 VSS_78 R39
C CE40 VDD2_34 AM8 VSS_256 VSS_322 BH2 CN48 VSS_142 VSS_202 DG45 H28 VSS_35 VSS_79 R44 C
CG40 VDD2_35 AN41 VSS_257 VSS_323 BH4 CN51 VSS_143 VSS_203 DG5 H34 VSS_36 VSS_80 T19
CH39 VDD2_36 AN42 VSS_258 VSS_324 BH8 CN52 VSS_144 VSS_204 DG53 H8 VSS_37 VSS_81 T29
CJ40 VDD2_37 AN44 VSS_259 VSS_325 BK12 CN9 VSS_145 VSS_205 DG6 J39 VSS_38 VSS_82 T33
CL40 VDD2_38 AN45 VSS_260 VSS_326 BK4 CP3 VSS_146 VSS_206 DJ1 J49 VSS_39 VSS_83 T4
CN40 VDD2_39 AN47 VSS_261 VSS_327 BK48 CP41 VSS_147 VSS_207 DJ2 K16 VSS_40 VSS_84 T48
CP47 VDD2_40 AN48 VSS_262 VSS_328 BK8 CP42 VSS_148 VSS_208 DJ4 K18 VSS_41 VSS_85 T8
CR40 VDD2_41 AN53 VSS_263 VSS_329 BL49 CP44 VSS_149 VSS_209 DK51 K20 VSS_42 VSS_86 U19
D50 VDD2_42 AP4 VSS_264 VSS_330 BM1 CP45 VSS_150 VSS_210 DL3 K22 VSS_43 VSS_87 U25
E51 VDD2_43 AP8 VSS_265 VSS_331 BM4 CP5 VSS_151 VSS_211 DL5 K28 VSS_44 VSS_88 U39
F49 VDD2_44 AT4 VSS_266 VSS_332 BM41 CR48 VSS_152 VSS_212 DM10 VSS_45 VSS_89 U49
T51 VDD2_45 AT48 VSS_267 VSS_333 BM42 CR53 VSS_153 VSS_213 DM15 VSS_90 V19
T52 VDD2_46 AT51 VSS_268 VSS_334 BM44 CR9 VSS_154 VSS_214 DM21 VSS_91 V4
VDD2_47 AT8 VSS_269 VSS_335 BM45 CT5 VSS_155 VSS_215 DM27 VSS_92 V8
VSS_271 AV12 VSS_270 VSS_336 BM47 CU4 VSS_156 VSS_216 DM33 VSS_93 W1
AV39 VSS_271 VSS_337 BM8 CU9 VSS_157 VSS_217 DM39 VSS_94 W16
TGL_U_IP_EXT VSS_272 VSS_338 VSS_158 VSS_218 VSS_95
AV4 BN48 CV10 DM4 W26
VDDQ R67 AV5 VSS_273 VSS_339 BP41 CV48 VSS_159 VSS_219 DM45 VSS_96 W30
*0201_short AV7 VSS_274 VSS_340 BP49 CV5 VSS_160 VSS_220 DN1 VSS_97 W39
AV8 VSS_275 VSS_341 BP5 CV51 VSS_161 VSS_221 DN2 VSS_98 W41
AW1 VSS_276 VSS_342 BP50 CV52 VSS_162 VSS_222 VSS_99 W42
AW2 VSS_277 VSS_343 BP7 CY17 VSS_163 VSS_100 W44
C171 C115 C153 C144 C174 C42 C22 C145 C131 C96 C83 C50 C134 C162 C172 C49 AW48 VSS_278 VSS_344 BT44 CY22 VSS_164 VSS_101 W45
AY4 VSS_279 VSS_345 BT48 CY35 VSS_165 VSS_102 W47
VSS_280 VSS_346 VSS_166 VSS_103
1u_6.3V_X6S_04
1u_6.3V_X6S_04
1u_6.3V_X6S_04
1u_6.3V_X6S_04
1u_6.3V_X6S_04
1u_6.3V_X6S_04
1u_6.3V_X6S_04
1u_6.3V_X6S_04
1u_6.3V_X6S_04
1u_6.3V_X6S_04
1u_6.3V_X6S_04
1u_6.3V_X6S_04
1u_6.3V_X6S_04
1u_6.3V_X6S_04
1u_6.3V_X6S_04
1u_6.3V_X6S_04
TGL_U_IP_EXT
VDDQ VDDQ
VDDQ
C71 C149 C60 C47 C41 C33 C82 C46 C68 C43 C72 C23 C63 C31 C152 C95
10u_6.3V_X5R_04
10u_6.3V_X5R_04
10u_6.3V_X5R_04
10u_6.3V_X5R_04
10u_6.3V_X5R_04
10u_6.3V_X5R_04
10u_6.3V_X5R_04
10u_6.3V_X5R_04
10u_6.3V_X5R_04
10u_6.3V_X5R_04
10u_6.3V_X5R_04
10u_6.3V_X5R_04
22u_6.3V_X5R_06
22u_6.3V_X5R_06
22u_6.3V_X5R_06
22u_6.3V_X5R_06
A A
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Title
[12] TGL U O,P,Q,R POWER CONTROL
Size Document Number Rev
A3 NLx0MU 6-71-NLx0MU-D02
A0
D02
Date: W ednesday, August 18, 2021 Sheet 12 of 47
5 4 3 2 1
Processor 11/12 B - 13
Schematic Diagrams
Processor 12/12
5 4 3 2 1
3.3VA
3.3VS
R35
100K_04
R199 10K_04 SCI#
PU/PD for JTAG signals
VCCSTG_OUT_LGC VCCSTG XDP_TCLK R417 51_04
R206 10K_04 SMI# XDP_TRST# R415 *51_04
U21U CPU_EAR R31 *1K_04
D11
R41 R34
D R38 0_04 C A D
[11] VRALERT#_PD
1K_04 *1K_04 H_CATERR# XDP_TRST#
RB751S-40H VCCST R48 1K_04 M7 K4
R78 *14mil_02 H_PECI_ISO BK9 CATERR# PROC_TRST# B9 XDP_TMS
H_PROCHOT# [24] H_PECI
R410 499_1%_04 H_PROCHOT#_D E2 PECI PROC_TMS D12 XDP_TDO
Form power [38] H_PROCHOT# PROCHOT# PROC_TDO XDP_TDI
LENGTH <500MILS VCCST R47 1K_04 THERMTRIP# M5 A12
R32 *200K_04 C335 THRMTRIP# PROC_TDI B6 XDP_TCLK VCCSTG
3.3VA PROC_TCK
6
D R110 49.9_1%_04 CPU_POPIRCOMP CT39
C A *47p_25V_NPO_02 R95 49.9_1%_04 PCH_OPI_RCOMP CB9 PROC_POPIRCOMP D8 XDP_TCLK R411 *1K_04
[24,37] AC_IN# PCH_OPIRCOMP PCH_JTAGX XDP_TMS
D8 *RB751S-40H 2G CW12 A9 R412 51_04
S Q23A CM39 TP_1 PCH_TMS E12 XDP_TDO R413 51_04
1
TP_2 PCH_TDO
3
R408 D MTDK3S6R B12 XDP_TDI R414 51_04
0_02 R153 *1K_04 DBG_PMODE DF4 PCH_TDI A7 PCH_JTAG_TCK R418 *51_04
Form EC R409 DBG_PMODE PCH_TCK XDP_TRST#
[24] H_PROCHOT_EC 5G Q23B H4
S MTDK3S6R DB42 PCH_TRST#
*0_04
4
R116 0_04 TP_ATTN#_R DB41 GPP_B4/CPU_GP3 C11 XDP_PREQ#
[29] TP_ATTN# GPP_B3/CPU_GP2 PROC_PREQ# T29
B.Schematic Diagrams
Sheet 13 of 47
GPP_H1 DV32 DT15
GPP_H0_RTD3 DW32 GPP_H1 GPP_F7 DR15
GPP_H0 GPP_F9 DT14 GPP_F10
CNVI_W AKE# DJ27 GPP_F10
[25] CNVI_W AKE#
Processor 12/12
GPP_H19/TIME_SYNC0
TGL_U_IP_EXT
C C
This is bit 1 of a total of 4-bit This is bit 2 of a total of This is bit 3 of a total of
3.3VA 3.3VA 3.3VA 3.3VA This strap should sample LOW.
encoded pin 4-bit encoded pin straps for 4-bit encoded pin straps for
straps for boot configuration. boot boot There should NOT be any onboard
Refer to Boot Strap 0 (on GPP_C5) configuration. configuration. R226
device driving it to opposite direction
R487 for the encoding. R486 Refer to Boot Strap 0 (on R143 Refer to Boot Strap 0 (on during strap sampling.
(internal PD 20K) GPP_C5) for the encoding. GPP_C5) for the encoding. (internal PD 20K)
*4.7K_04 *4.7K_04 *4.7K_04 *4.7K_04
(internal PD 20K) (internal PD 20K)
GPP_H0_RTD3 GPP_H1 GPP_H2 GPP_F10
H10 H2 H1 H9
*C111D111N *C111D111N *C111D111N *C111D111N
㰺
㚱 V A L UE⎒ 㚱P /
N
CPU NUT, BOT 㰺
㚱 V A L UE⎒ 㚱P /
N M.2 SSD NUT, BOT C111D111N C111D111N C111D111N C111D111N
H_CPU1 H_CPU2 H_CPU3 H_SSD1
6-34-W 54CS-010 6-34-W 54CS-010 6-34-W 54CS-010 6-34-L140S-010
H5 H12 H11 H14
H7_0B6_0D3_7 H7_0B6_0D3_7 H7_0B6_0D3_7 H7_0B6_0D3_7
2 4 2 4 2 4 2 4
M5 M2 M6 M1
3 1 5 3 1 5 3 1 5 3 1 5 㰺
㚱 V A L UE⎒ 㚱P /
N *M-MARK *M-MARK *M-MARK *M-MARK
A H6 H7 H13 A
H3 H8 H4
2 4 2 4 2 4
*H5_0B4_0D2_0 *O197X216B157X177D77 *O197X216B157X177D77
D02A Del H12
M4 M3 M8 M7
H5_0B4_0D2_0 O197X216B157X177D77 O197X216B157X177D77
3 1 5 3 1 5 3 1 5 *M-MARK *M-MARK *M-MARK *M-MARK
5 4 3 2 1
B - 14 Processor 12/12
Schematic Diagrams
DDR4 SO-DIMM_A
5 4 3 2 1
137
J_DIMMAA SO-DIMM A8
VDDQ
3.5A 163
J_DIMMAB
258
1A VDDQ_VTT
CLOCK [3]
[3]
[3]
M_A_CLK_DDR0
M_A_CLK_DDR#0
M_A_CLK_DDR1
139
138
CK0_T
CK0_C
CK1_T
DQ0
DQ1
DQ2
7
20
M_A_DQ_7_2
M_A_DQ_7_4
M_A_DQ_7_5
[3]
[3]
[3]
160
159
VDD19
VDD18
VDD17
VTT 2.5V
[3]
M_A_CKE1
M_A_CS#0
149
CKE1
S0*
DQ6
DQ7
DQ8
17
28
M_A_DQ_7_7
M_A_DQ_7_1
M_A_DQ_6_3
[3]
[3]
[3]
142
141
VDD13
VDD12
VDD11
3.3VS
B.Schematic Diagrams
M_A_A7 A6 DQ25 M_A_DQ_4_6 [3] VSS VSS
122 83 M_A_DQ_4_1 [3] 243 244
M_A_A8 125 A7 DQ26 84 239 VSS VSS 238
SINGLE=45ohm M_A_DQ_4_3 [3]
M_A_A9 121 A8 DQ27 66 235 VSS VSS 234 C38 C148 C26 C56
Sheet 14 of 47
M_A_A10 A9 DQ28 M_A_DQ_4_7 [3] VSS VSS
146 67 M_A_DQ_4_5 [3] 231 230
M_A_A11 120 A10_AP DQ29 79 227 VSS VSS 226 10u_6.3V_X5R_04 10u_6.3V_X5R_04 10u_6.3V_X5R_04 *10u_6.3V_X5R_04
M_A_A12 A11 DQ30 M_A_DQ_4_2 [3] VSS VSS
119 80 M_A_DQ_4_0 [3] 223 222
M_A_A13 158 A12 DQ31 174 217 VSS VSS 218
DDR4 SO-DIMM_A
M_A_A14 A13 DQ32 M_A_DQ_1_3 [3] VSS VSS VDDQ
151 173 M_A_DQ_1_2 [3] 213 214
M_A_A15 156 A14_WE* DQ33 187 209 VSS VSS 210
M_A_A16 A15_CAS* DQ34 M_A_DQ_1_6 [3] VSS VSS
152 186 M_A_DQ_1_0 [3] 205 206
A16_RAS* DQ35 170 201 VSS VSS 202
DQ36 M_A_DQ_1_4 [3] VSS VSS C161 C207 C127 C139
169 M_A_DQ_1_1 [3] 197 196
114 DQ37 183 193 VSS VSS 192
C SINGLE=50ohm [3] M_A_ACT# M_A_DQ_1_7 [3]
C
ACT* DQ38 182 189 VSS VSS 188 10u_6.3V_X5R_04 10u_6.3V_X5R_04 *10u_6.3V_X5R_04 *10u_6.3V_X5R_04
DQ39 M_A_DQ_1_5 [3] VSS VSS
143 195 M_A_DQ_0_5 [3] 185 184
[3] DDR0_A_PARITY PARITY DQ40 VSS VSS
SINGLE=45ohm [3] 116 194 M_A_DQ_0_7 [3] 181 180
DDR0_A_ALERT# DIMM0_CHA_EVENT# ALERT* DQ41 VSS VSS VDDQ
134 207 M_A_DQ_0_0 [3] 175 176
CPUDRAMRST# 108 EVENT* DQ42 208 171 VSS VSS 172
[3,15] CPUDRAMRST# RESET* DQ43 M_A_DQ_0_2 [3] VSS VSS
SINGLE=50ohm 191 M_A_DQ_0_6 [3] 167 168
VREFCA_CHA_DIMM 164 DQ44 190 107 VSS VSS 106
VREFCA DQ45 M_A_DQ_0_4 [3] VSS VSS
203 M_A_DQ_0_3 [3] 103 102 C16 C40 C75 C90
254 DQ46 204 99 VSS VSS 98
[5,15] SMB_DAT_DDR SDA DQ47 M_A_DQ_0_1 [3] VSS VSS
253 216 M_A_DQ_3_7 [3] 93 94 1u_6.3V_X5R_04 1u_6.3V_X5R_04 *1u_6.3V_X5R_04 1u_6.3V_X5R_04
[5,15] SMB_CLK_DDR SCL DQ48 VSS VSS
215 M_A_DQ_3_0 [3] 89 90
R102 *10mil_Short_04 SA2_CHA_DIM0 166 DQ49 228 85 VSS VSS 86
SA1_CHA_DIM0 SA2 DQ50 M_A_DQ_3_2 [3] VSS VSS VDDQ
R293 *10mil_Short_04 260 229 M_A_DQ_3_6 [3] 81 82
R292 *10mil_Short_04 SA0_CHA_DIM0 256 SA1 DQ51 211 77 VSS VSS 78
SA0 DQ52 M_A_DQ_3_3 [3] VSS VSS
212 M_A_DQ_3_5 [3] 73 72
DQ53 224 69 VSS VSS 68
DQ54 M_A_DQ_3_1 [3] VSS VSS
225 M_A_DQ_3_4 [3] 65 64 C126 C151 C101 C201
92 DQ55 237 61 VSS VSS 60
CB0_NC DQ56 M_A_DQ_2_1 [3] VSS VSS
91 236 M_A_DQ_2_7 [3] 57 56 1u_6.3V_X5R_04 1u_6.3V_X5R_04 *1u_6.3V_X5R_04 *1u_6.3V_X5R_04
VDDQ 101 CB1_NC DQ57 249 51 VSS VSS 52
PLACE CLOSE TO SODIMM 105 CB2_NC
CB3_NC
DQ58
DQ59
250
M_A_DQ_2_4
M_A_DQ_2_2
[3]
[3] 47 VSS
VSS
VSS
VSS
48
2.5V
88 232 M_A_DQ_2_5 [3] 43 44
DIMM0_CHA_EVENT# R81 240_1%_04 87 CB4_NC DQ60 233 39 VSS VSS 40
CB5_NC DQ61 M_A_DQ_2_3 [3] VSS VSS
100 245 M_A_DQ_2_6 [3] 35 36 6/24/2016
VDDQ 104 CB6_NC DQ62 246 31 VSS VSS 30
CB7_NC DQ63 M_A_DQ_2_0 [3] VSS VSS C235
27 26 C236
M_A_DQS7 M_A_DQS[7:0] [3] VSS VSS
12 13 23 22
33 DM0*/DBI0* DQS0_T 34 M_A_DQS6 19 VSS VSS 18 10u_6.3V_X5R_04 1u_6.3V_X5R_04
B 54 DM1*/DBI1* DQS1_T 55 M_A_DQS5 15 VSS VSS 14 B
75
178
DM2*/DBI2*
DM3*/DBI3*
DM4*/DBI4*
DQS2_T
DQS3_T
DQS4_T
76
179
M_A_DQS4
M_A_DQS1 STROBE 9
5
VSS
VSS
VSS
VSS
VSS
VSS
10
6 VDDQ_VTT
199 200 M_A_DQS0 1 2
220 DM5*/DBI5* DQS5_T 221 M_A_DQS3 VSS VSS
DIFF=90ohm
241 DM6*/DBI6* DQS6_T 242 M_A_DQS2
96 DM7*/DBI7* DQS7_T 97 M_A_DQS8 R61 240_1%_04
DM8*/DBI8* DQS8_T VDDQ C222
D4AR0-26001-1P40 C223 C224
M_A_DQS#7 M_A_DQS#[7:0] [3]
11 PCB Footprint = ddr4_260p_rvs_h40_d4arx
DQS0_C 32 M_A_DQS#6 <FUNCTION> 10u_6.3V_X5R_04 1u_6.3V_X5R_04 1u_6.3V_X5R_04
DQS1_C 53 M_A_DQS#5
DQS2_C 74 M_A_DQS#4
DQS3_C 177 M_A_DQS#1
DQS4_C 198 M_A_DQS#0
DQS5_C 219 M_A_DQS#3
DQS6_C 240 M_A_DQS#2
DQS7_C 95 M_A_DQS#8 R58 240_1%_04
DQS8_C VDDQ
162
165 S2*/C0
S3*/C1
VDDQ
D4AR0-26001-1P40
VDDQ PCB Footprint = ddr4_260p_rvs_h40_d4arx
<FUNCTION>
R103
TO CHA J_DIMMAA
R63
PLACE CLOSE TO CHA 1K_1%_04
DDR4 SO-DIMM_A B - 15
Schematic Diagrams
DDR4 SO-DIMM_B
5 4 3 2 1
137
J_DIMMBA SO-DIMM B 8
VDDQ
3.5A 163
J_DIMMBB
258
1A
VDDQ_VTT
CLOCK [4]
[4]
[4]
M_B_CLK_DDR0
M_B_CLK_DDR#0
M_B_CLK_DDR1
139
138
CK0_T
CK0_C
CK1_T
DQ0
DQ1
DQ2
7
20
M_B_DQ_5_5
M_B_DQ_5_7
M_B_DQ_5_0
[4]
[4]
[4]
160
159
VDD19
VDD18
VDD17
VTT 2.5V
[4]
M_B_CKE1
M_B_CS#0
149
CKE1
S0*
DQ6
DQ7
DQ8
17
28
M_B_DQ_5_3
M_B_DQ_5_1
M_B_DQ_4_4
[4]
[4]
[4]
142
141
VDD13
VDD12
VDD11
3.3VS
PLACE CLOSE TO PIN
D SINGLE=45ohm 157 29 M_B_DQ_4_7 [4] 136 255 D
[4] M_B_CS#1 S1* DQ9 VDD10 VDDSPD
41 M_B_DQ_4_1 [4] 135
155 DQ10 42 130 VDD9
[4] M_B_ODT0 ODT0 DQ11 M_B_DQ_4_3 [4] VDD8
161 24 M_B_DQ_4_5 [4] 129 C246 C247
[4] M_B_ODT1 ODT1 DQ12 VDD7
25 M_B_DQ_4_6 [4] 124
115 DQ13 38 123 VDD6 0.1u_10V_X5R_04 2.2u_6.3V_X5R_04
[4] M_B_BG0 BG0 DQ14 M_B_DQ_4_0 [4] VDD5
113 37 M_B_DQ_4_2 [4] 118
[4] M_B_BG1 BG1 DQ15 VDD4
150 50 M_B_DQ_7_2 [4] 117
[4] M_B_BA0 BA0 DQ16 VDD3
145 49 M_B_DQ_7_6 [4] 112
[4] M_B_BA1 BA1 DQ17 VDD2
62 M_B_DQ_7_4 [4] 111
[4] M_B_A[16:0] M_B_A0 DQ18 M_B_CLK_DDR0 VDD1
144 63 M_B_DQ_7_1 [4]
M_B_A1 133 A0 DQ19 46 GND1
M_B_A2 A1 DQ20 M_B_DQ_7_3 [4] MT1
B.Schematic Diagrams
Sheet 15 of 47
M_B_A11 A10_AP DQ29 M_B_DQ_6_3 [4] VSS VSS
120 79 M_B_DQ_6_5 [4] *3p_25V_NPO_02 227 226
M_B_A12 119 A11 DQ30 80 M_B_CLK_DDR#1 223 VSS VSS 222
M_B_A13 A12 DQ31 M_B_DQ_6_0 [4] VSS VSS VDDQ
158 174 M_B_DQ_1_0 [4] 217 218
M_B_A14 151 A13 DQ32 173 213 VSS VSS 214
DDR4 SO-DIMM_B
M_B_A15 A14_WE* DQ33 M_B_DQ_1_5 [4] VSS VSS
156 187 M_B_DQ_1_2 [4] 209 210
M_B_A16 152 A15_CAS* DQ34 186 205 VSS VSS 206
A16_RAS* DQ35 M_B_DQ_1_4 [4] VSS VSS C8 C165 C137 C7
170 M_B_DQ_1_7 [4]
Oscar 09_25_2020 201 202
DQ36 169 Oscar 09_28_2020 197 VSS VSS 196
DQ37 M_B_DQ_1_6 [4] Oscar 11_26_2020 VSS VSS
C SINGLE=50ohm 114 183 M_B_DQ_1_1 [4] 193 192 10u_6.3V_X5R_04 10u_6.3V_X5R_04 10u_6.3V_X5R_04 *10u_6.3V_X5R_04 C
[4] M_B_ACT# ACT* DQ38 VSS VSS
182 M_B_DQ_1_3 [4] 189 188
143 DQ39 195 185 VSS VSS 184
[4] DDR1_B_PARITY PARITY DQ40 M_B_DQ_0_7 [4] VSS VSS VDDQ
SINGLE=45ohm 116 194 M_B_DQ_0_0 [4] 181 180
[4] DDR1_B_ALERT#
DIMM1_CHB_EVENT# ALERT* DQ41 VSS VSS
134 207 M_B_DQ_0_2 [4] 175 176
108 EVENT* DQ42 208 171 VSS VSS 172
[3,14] CPUDRAMRST# RESET* DQ43 M_B_DQ_0_3 [4] VSS VSS
191 M_B_DQ_0_6 [4] 167 168
VREFCA_CHB_DIMM 164 DQ44 190 107 VSS VSS 106 C124 C81 C112 C74
SINGLE=50ohm M_B_DQ_0_5 [4]
VREFCA DQ45 203 103 VSS VSS 102
DQ46 M_B_DQ_0_1 [4] VSS VSS
254 204 M_B_DQ_0_4 [4] 99 98 1u_6.3V_X5R_04 1u_6.3V_X5R_04 1u_6.3V_X5R_04 *1u_6.3V_X5R_04
[5,14] SMB_DAT_DDR SDA DQ47 VSS VSS
253 216 M_B_DQ_3_6 [4] 93 94
[5,14] SMB_CLK_DDR SCL DQ48 VSS VSS
215 M_B_DQ_3_2 [4] 89 90
R115 *10mil_Short_04 SA2_CHB_DIM0 166 DQ49 228 85 VSS VSS 86 VDDQ
SA1_CHB_DIM0 SA2 DQ50 M_B_DQ_3_5 [4] VSS VSS
3.3VS R280 *10mil_Short_04 260 229 M_B_DQ_3_1 [4] 81 82
R275 *10mil_Short_04 SA0_CHB_DIM0 256 SA1 DQ51 211 77 VSS VSS 78
SA0 DQ52 M_B_DQ_3_3 [4] VSS VSS
212 M_B_DQ_3_7 [4] 73 72
DQ53 224 69 VSS VSS 68 C12 C117 C97 C62
DQ54 M_B_DQ_3_4 [4] VSS VSS
225 M_B_DQ_3_0 [4] 65 64
92 DQ55 237 61 VSS VSS 60 1u_6.3V_X5R_04 1u_6.3V_X5R_04 *1u_6.3V_X5R_04 *1u_6.3V_X5R_04
CB0_NC DQ56 M_B_DQ_2_5 [4] VSS VSS
91 236 M_B_DQ_2_1 [4] 57 56
101 CB1_NC DQ57 249 51 VSS VSS 52
CB2_NC DQ58 M_B_DQ_2_0 [4] VSS VSS 2.5V
105 250 M_B_DQ_2_4 [4] 47 48
88 CB3_NC DQ59 232 43 VSS VSS 44
CB4_NC DQ60 M_B_DQ_2_3 [4] VSS VSS
87 233 M_B_DQ_2_7 [4] 39 40
100 CB5_NC DQ61 245 35 VSS VSS 36
VDDQ CB6_NC DQ62 M_B_DQ_2_2 [4] VSS VSS C249
104 246 M_B_DQ_2_6 [4] 31 30 C250
CB7_NC DQ63 27 VSS VSS 26
M_B_DQS5 M_B_DQS[7:0] [4] VSS VSS
12 13 23 22 10u_6.3V_X5R_04 1u_6.3V_X5R_04
33 DM0*/DBI0* DQS0_T 34 M_B_DQS4 19 VSS VSS 18
B 54 DM1*/DBI1* DQS1_T 55 M_B_DQS7 15 VSS VSS 14 B
75
178
DM2*/DBI2*
DM3*/DBI3*
DM4*/DBI4*
DQS2_T
DQS3_T
DQS4_T
76
179
M_B_DQS6
M_B_DQS1 STROBE 9
5
VSS
VSS
VSS
VSS
VSS
VSS
10
6
199 200 M_B_DQS0 1 2 VDDQ_VTT
220 DM5*/DBI5* DQS5_T 221 M_B_DQS3 VSS VSS
DIFF=90ohm
241 DM6*/DBI6* DQS6_T 242 M_B_DQS2
96 DM7*/DBI7* DQS7_T 97 M_B_DQS8 R60 240_1%_04
DM8*/DBI8* DQS8_T VDDQ
D4AS0-26001-1P40
M_B_DQS#5 M_B_DQS#[7:0] [4] C227
11 PCB Footprint = ddr4_260p_std_h40_d4asx C229 C221
DQS0_C 32 M_B_DQS#4 <FUNCTION>
DQS1_C 53 M_B_DQS#7 10u_6.3V_X5R_04 1u_6.3V_X5R_04 1u_6.3V_X5R_04
DQS2_C 74 M_B_DQS#6
DQS3_C 177 M_B_DQS#1
DQS4_C 198 M_B_DQS#0
DQS5_C 219 M_B_DQS#3
DQS6_C 240 M_B_DQS#2
DQS7_C 95 M_B_DQS#8 R57 240_1%_04
DQS8_C VDDQ VDDQ
162
165 S2*/C0
S3*/C1
D4AS0-26001-1P40 R98
PCB Footprint = ddr4_260p_std_h40_d4asx
<FUNCTION> PLACE CLOSE TO CHB 1K_1%_04 TO CHB J_DIMMBA
R97 2_1%_04 VREFCA_CHB_DIMM
[4] DDR1_VREF_CA
C133
A R101 A
0.022u_25V_X7R_04 C163
VREFCA_CHB_DIMM PLACE THE CAP CLOSE TO SODIMM 1K_1%_04
*0.1u_10V_X7R_04
R94
VDDQ
C170 24.9_1%_04
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
PLACE CLOSE TO SODIMM *0.1u_10V_X5R_04
Title
[15] DDR4 SO-DIMM_B
DIMM1_CHB_EVENT# R85 240_1%_04
Size Document Number Rev
A3 NLx0MU 6-71-NLx0MU-D02A0 D02
Date: W ednesday, August 18, 2021 Sheet 15 of 47
5 4 3 2 1
B - 16 DDR4 SO-DIMM_B
Schematic Diagrams
HDMI
5 4 3 2 1
D02 modify
HDMI_5VS
20210617
U22 HDMI_5VS
HDMI CONNECTOR D18 劍 㛒
㺷
暣
SMBUS 炻⇯⎗ S ho rt .
A
5VS 2 BY platform 婧
㔜
℞ῤ
VOUT D29
3 C371 C370 C373 J_HDMI1 C128G1-K1909-L RB751S-40H
VIN 1 PCB Footprint = C12826-119A8L
C375 GND
D 1u_6.3V_X5R_04 0.1u_6.3V_X5R_02 *22u_6.3V_X5R_06 P/N = 6-21-14A70-019 D
C
*10u_6.3V_X5R_06
APL3517A
19 HDMI_HPD-C
HOT PLUG DETECT R442 R444
20210812 delete 18
TMDS_CLOCK +5V 17
HDMI_SDA-C DDC/CEC GND 4.7K_04 4.7K_04
for eye pattern pass 16
SDA 15 HDMI_SCL-C
C363 R435 14 SCL
RESERVED HDMI_CEC D28
13
B.Schematic Diagrams
TMDS_CLOCK TMDS_CLOCK#J CEC T9
*1.5p_50V_04 *100_1%_04 12 HDMI_SCL-C HDMI_SCL-C-R
TMDS CLOCK- 5 6
11 HDMI_SDA-C HDMI_SDA-C-R
TMDS_CLOCK# TMDS_CLOCK# TMDS_CLOCKJ CLK SHIELD 4 7
10
TMDS CLOCK+ TMDS_DATA0#J 3 8
9 HDMI_HPD-C HDMI_HPD-C-R
TMDS DATA0- 2 9
8
SHIELD0 TMDS_DATA0J 1 10
7
Sheet 16 of 47
20210812 delete TMDS DATA0+
TMDS_DATA1 TMDS_DATA1 TMDS_DATA1#J 6
TMDS DATA1- 5
for eye pattern pass SHIELD1 ESD73034D
TMDS_DATA1J 4
HDMI
R424 TMDS_DATA1# TMDS DATA1+ 3 TMDS_DATA2#J
C TMDS DATA2- 20210812 delete C
2 TMDS_DATA0
*100_1%_04 SHIELD2 1 TMDS_DATA2J
TMDS DATA2+ for eye pattern pass
TMDS_DATA1# R441
TMDS_DATA0
GND
GND
GND
GND
*100_1%_04
TMDS_DATA0# TMDS_DATA0#
GND1
GND2
GND3
GND4
E M I 㒢㓦
20210812 delete
C359 0.1u_10V_X5R_04 TMDS_DATA2 TMDS_DATA2 TMDS_DATA2
[2] HDMI_DATA0P
C360 0.1u_10V_X5R_04 TMDS_DATA2#
[2] HDMI_DATA0N
R428
C356 0.1u_10V_X5R_04 TMDS_DATA1 TMDS_DATA2#
[2] HDMI_DATA1P
C357 0.1u_10V_X5R_04 TMDS_DATA1# *100_1%_04
[2] HDMI_DATA1N TMDS_DATA2#
3.3VS
C366 0.1u_10V_X5R_04 TMDS_DATA0 for eye pattern pass
[2] HDMI_DATA2P
C368 0.1u_10V_X5R_04 TMDS_DATA0#
[2] HDMI_DATA2N
C362 0.1u_10V_X5R_04 TMDS_CLOCK TMDS_DATA0# R443 470_04
2
[2] HDMI_CLOCKP
C364 0.1u_10V_X5R_04 TMDS_CLOCK# TMDS_DATA0 R440 470_04
G
B [2] HDMI_CLOCKN TMDS_DATA2# B
HDMI_SDA-C-R R431 470_04
1 6 TMDS_DATA2
[2] HDMI_CTRLDATA R427 470_04
D
Zdiff=85Ω 5
G Q25A
MTDK5S6R
TMDS_CLOCK#
TMDS_CLOCK
R438
R433
470_04
470_04
TMDS_DATA1# R425 470_04
HDMI ESD W/O LEVELSHIFT 暨
ᶲ , NET 4 3 HDMI_SCL-C-R
[2] HDMI_CTRLCLK TMDS_DATA1 R423 470_04
⎗S W A P
S
D
D27
Q25B
TMDS_DATA0# TMDS_DATA0#J MTDK5S6R GND_HDMI 5VS
6 5
TMDS_DATA0 7 4 TMDS_DATA0J 3.3VS
D
8 3
TMDS_CLOCK# 9 2 TMDS_CLOCK#J
TMDS_CLOCK TMDS_CLOCKJ G
10 1
S
R451 Q28 Q24
20190619 layout swap 2SK3018S3 2SK3018S3
G
ESD73034D 1M_04
PCB Footprint = dfn10-2_5x1mm-short 20190708 20190708
D26 HDMI_HPD-C-R
S D
[2] HDMI_HPD
TMDS_DATA1# 6 5 TMDS_DATA1#J
TMDS_DATA1 7 4 TMDS_DATA1J
R445
8 3
TMDS_DATA2# 9 2 TMDS_DATA2#J 20K_04
A A
TMDS_DATA2 10 1 TMDS_DATA2J
ESD73034D
20190619 layout swap ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Title
PCB Footprint = dfn10-2_5x1mm-short
[16] HDMI
Size Document Number Re v
Custom NLx0MU 6-71-NLx0MU-D02 D02
Date: Wednesday, August 18, 2021 Sheet 16 of 47
5 4 3 2 1
HDMI B - 17
Schematic Diagrams
Panel
5 4 3 2 1
PLVDD
2A
PANEL POWER
J_LCD1 ℙ 䓐 䶂嶗
DEFAULT SHORT
C334 1
2 1 PJ4 2 1 2mm
1u_6.3V_X5R_02 3 2 VIN VLED
4 3 *AO3415 Q1
5 4 S D
6 5
7 6 C32
C336 0.1u_10V_X5R_04 EDP_TXN0 8 7 *0.1u_50V_X5V_04 C11
[2] EDP_TXN_0
G
D C337 0.1u_10V_X5R_04 EDP_TXP0 9 8 *0.22u_25V_X7R_06 D
[2] EDP_TXP_0 9 6-15-35726-7B0
10
C339 0.1u_10V_X5R_04 EDP_TXN1 11 10 3.3V R52
[2] EDP_TXN_1 EDP_TXP1 11
C341 0.1u_10V_X5R_04 12 *4.7K_06
[2] EDP_TXP_1 12
13 8/14 R54
C344 0.1u_10V_X5R_04 EDP_TXN2 14 13 GND1 *150K_1%_04
[2] EDP_TXN_2 EDP_TXP2 14 GND1
C346 0.1u_10V_X5R_04 15 GND2 R51
[2] EDP_TXP_2 15 GND2
16 GND3 *100K_04 R53 *19.1K_04 R59
C347 0.1u_10V_X5R_04 EDP_TXN3 17 16 GND3 GND4
D
[2] EDP_TXN_3 EDP_TXP3 17 GND4
C349 0.1u_10V_X5R_04 18 GND5 *10K_04
[2] EDP_TXP_3 18 GND5
6
3.3VS R419 *100K_04 19 D
C352 0.1u_10V_X5R_04 EDP_AUX# 20 19 PANEL_VCC_EN G Q2A
[2] EDP_AUXN EDP_AUX 20
C353 0.1u_10V_X5R_04 21 R55 *0_04 2G *MTD5S6R
[2] EDP_AUXP
S
22 21 S
[10,23,28,33,36] SUSB# Q3
1
R420 *100K_04 23 22 R56 *0_04 *2SK3018S3
B.Schematic Diagrams
23
3
EDP_BRIGHTNESS
INV_BLON
24
25 24 枸 䔁 婧㔜Q PXFS!TFRV O
F DF D
Q2B
EDP_HPD_L 26 25 5G *MTD5S6R
27 26 S
4
VLED_L 28 27
L1 29 28
2A 29
VLED . 30
30
Sheet 17 of 47
HCB1608KF-121T30 lvdfh-03008-tp00+
C30 C35 PCB Footprint = LVDFH-03008-TP00
P/N = 6-21-44K00-030
0.1u_50V_X5R_04 *0.01u_50V_X7R_04
Panel C C
R422 *10K_04
PANEL POWER
PLVDD
Entire trace of Panel VCC should be wider than 120-mil
EDP_BRIGHTNESS
[2] EDP_BRIGHTNESS
3.3VS
>120mil
2nd source G5016
3.3VS
EM5290
PCBfootprint:
C
C327
A
D7 U18 G2898KD1U
TDFN14-2X3MM-A
BAV99 RECTIFIER 0.1u_6.3V_X5R_02
1 6
PLVDD 2 IN1 IN2 7 PLVDD
AC
R36 1K_04 EDP_HPD_L IN1 IN2
[2] EDP_HPD >120mil >120mil
PLVDD 13 8
C20 OUT1 OUT2
14 9
R33 OUT1 OUT2
C333 C328
G5016_CT1 12 10 G5016_CT1
*220p_50V_NPO_04 100K_04 CT1 CT2
*10u_6.3V_X5R_04 0.1u_6.3V_X5R_02
VBIAS
GND
GND
EN1
EN2
C329
1000p_50V_X7R_04
ὅ őŢůŦŭġųŪŴŦġŵŪ ŮŦġ 婧 㔜 ℞ῤ
15
11
3
5
B B
5V
R405
PANEL_VCC_EN C330 PANEL_VCC_EN
[2] NB_ENAVDD
1u_6.3V_X5R_02
*0402_short
R403 100K_04
R401 R404
10K_04 100_04
3.3V
[24] BKL_EN
6
3.3V D
U30A
14
74LVC08APW U30B 2G
14
[2] BLON
1 74LVC08APW S
1
Q22A
3
3 BLON1 4 D
R542 100K_04 BLON 2 6 BLON2 Q22B *MTDK3S6R
5 3.3V PANEL_VCC_EN 5G *MTDK3S6R
S
7
4
R521 *100K_04 U30C
14
7
74LVC08APW
SB_BLON 9
[6] SB_BLON INV_BLON
8
3.3V 10
A A
B - 18 Panel
Schematic Diagrams
MDP_AUX SBU1_J ⃰
䓐 1.8 V ⤪㰺 㚱1. 8 V 㗪 䓐 1.8V A 暨婧
㔜冯3.3V䘬㗪
⸷
1RWH
USB TYPE-C_ANX7443_Retimer 7KHVHFDSDFLWRUVDUHXVHGWRUHGXFHWKHVOHZUDWHRI$8;&+WRPHHWWKH'3
9$8;&+UHTXLUHPHQW C319 C316
1.8V
ANX7443_1.8V
7KHVHFDSDFLWRUVDUHPDQGDWRU\IRU+%5DSSOLFDWLRQIRU+%5DQGORZHUWKH *18p_25V_NPO_02 *18p_25V_NPO_02
FDSVDUHRSWLRQDO MDP_AUX# SBU2_J
%RWKWKHXSVWUHDPDQGGRZQVWUHDPSRUWQHHGWRDGGWKHFDSDFLWRUIRU+%5
D01, Ku , ⺈
⓮
⺢嬘 DSSOLFDWLRQ L5 HCB1005KF-121T20
3.3V 3.3V
D ANX7443_1.8V ANX7443_1.8V D
R390 D01, Ku , ⺈
⓮
⺢嬘
R391 R377
D01, Ku , ⺈
⓮
⺢嬘
*1M_1%_04 1M_1%_04 *1M_1%_04 C304 C265 C281 C293 C277 C312
near
MDP_AUX_L DVDD09
0.1u_10V_X5R_04 0.1u_10V_X5R_04 1u_6.3V_X5R_04 0.1u_10V_X5R_04 0.1u_10V_X5R_04 0.1u_10V_X5R_04
[2] MDP_AUX
C318 0.1u_10V_X5R_04
C288 C270 C287 C262
W/_TYPE_C+DP MDP_AUX#_L# 0.1u_10V_X5R_04
[2] MDP_AUX# 4.7u_6.3V_X5R_04
C317 0.1u_10V_X5R_04 0.1u_10V_X5R_04 0.01u_25V_X7R_04 CAP shall be respectively placed
ANX7443_1.8V
W/_TYPE_C+DP close to PIN5, PIN12, PIN27, PIN33, PIN39 and PIN45
R389 R376
25
21
56
12
27
33
39
45
9
5
Note:
U14
V09_OUT
VDD18_3
VDD18_8
VDD18_1
VDD18_2
VDD18_4
VDD18_5
VDD18_6
VDD18_7
DVDD09
AC capacitors for DP
main link should be put
close to DP source
6
DTX1P TX_1_P [20] TX1
C280 0.1u_6.3V_X5R_02 34 (dp2) 7
[2] MDP_D0 ML0P (DFP1P) DTX1N TX_1_N [20]
C283 0.1u_6.3V_X5R_02 35
From [2] MDP_D#0
C285 0.1u_6.3V_X5R_02 37 ML0N (DFP1N) 4
[2] MDP_D1 ML1P (DFP0P) RX_1_N [20] RX1
INTEL C289 0.1u_6.3V_X5R_02 38 (dp3)DRX1N 3
[2] MDP_D#1 ML1N(DFP0N) DRX1P RX_1_P [20]
C290 0.1u_6.3V_X5R_02 40
[2] MDP_D2 ML2P (DFP3P)
B.Schematic Diagrams
DIFF=85ohm, L<6" C291 0.1u_6.3V_X5R_02 41
[2] MDP_D#2 43 ML2N (DFP3N) 11
C294 0.1u_6.3V_X5R_02 Analogix Semi TX_2_P [20]
[2] MDP_D3 44 ML3P (DFP2P) (dp1) DTX2P 10 TX2
C296 0.1u_6.3V_X5R_02 TX_2_N [20]
[2] MDP_D#3 ML3N (DFP2N) DTX2N
13
MDP_AUX_L DRX2N RX_2_N [20]
51 (dp0) 14 RX2
MDP_AUX#_L# AUXP DRX2P RX_2_P [20]
50
C D01, Ku , ⺈
⓮
⺢嬘 AUXN 52 W/_TYPE_C+DP C314 0.1u_6.3V_X5R_02 SBU1_J C
DSBU1 SBU2_J SBU1_J [19]
53 W/_TYPE_C+DP C315 0.1u_6.3V_X5R_02
DSBU2 SBU2_J [19]
C273 0.22u_10V_X5R_02 31
[20] USB3_2RXN_R SSTXN
RX C275 0.22u_10V_X5R_02 32 16 W/_TYPE_C+DP R349 100K_04
86%*(1
Sheet 18 of 47
[20] USB3_2RXP_R SSTXP PULL1
C264 0.22u_10V_X5R_02 28 17 W/_TYPE_C+DP R386 100K_04
[20] USB3_2TXN_R C263 0.22u_10V_X5R_02 29 SSRXN PULL2
',)) RKP/ TX [20] USB3_2TXP_R SSRXP Close to
USB TYPE-C Conn.
59 T22
USB Type-C
HPD_IN
D01, Ku , ⺈
⓮
⺢嬘
1
ANX7443_1.8V ANX7443_1.8V V18_IN ANX7443_1.8V
If ANX7443 is on host motherboard, then C307 C272
SSTXP/N connect to chipset SSRXP/N, Two power options:
0.1u_10V_X5R_04 10u_6.3V_X5R_06 1) Use 7443 internal 1.2V LDO, pin V18_IN and V12_OUT
SSRXP/N connect to chipset SSTXP/N
ANX7443
are connected as reference design.
D02 modify R345 R346 The capacitors for TX should be placed
near SSTx pins. 2) System provides AVDD12, 7443 internal 1.2V LDO is
GND_DCDC
*1.8K_1%_04 60 not used, keep pin V18_IN and V12_OUT floating.
*1.8K_1%_04 V12_OUT ANX7443_1.2V Remove C21, C22 and C23.
ANX7433_SDA D01, Ku , ⺈
⓮
⺢嬘
R337 0_04 ANX7433_SDA 22
ANX7433_SCL [19] MSTR_SDA_7443
R336 0_04 ANX7433_SCL 23 CSDA C313
[19] MSTR_SCL_7443 CSCL
4.7u_6.3V_X5R_04
6LJQDO*1'DQG*1'B'&'&
FLIP:
USB Typc-C Orientation: PXVWEHVHSDUDWHG7KH\DUH
GND_DCDC
ANX7443_1.8V ANX7443_1.8V 0=normal, 1=flipped ANX7443_FLIP 54 2
FRQQHFWHGDW DVLQJOHSRLQW
R378 4.7K_04
Internal 45K ohm pull-down. FLIP AVDD12_1 15
CC1 detection is normal
AVDD12_2 26
D02 modify or
ANX7433_I2C_ADR_SEL020 AVDD12_3
CC2 detection is flipped 49
R388 R387 20210628 ANX7433_I2C_ADR_SEL119 ADDR0 AVDD12_4 R381 *0402_short
ADDR1 47
*4.7K_04 *4.7K_04 NC_47 46 C301 C311 C310 C266 R375 *0402_short
OP_MODE_1/O MODE [19] ANX7443_POWER_EN NC_46 48
W/_TYPE_C+DP W/_TYPE_C+DP 0.1u_10V_X5R_04
B 55 NC_48 0.1u_10V_X5R_04 0.1u_10V_X5R_04 B
00 Disabled USB_EN 0.1u_10V_X5R_04 GND_DCDC
TEST_EN
DP_PWR
01 USB3(default)
AVSS_1
AVSS_2
AVSS_3
10 DP 57
SWAP
DP_EN
DVSS
AVSS
11 USB3 + DP GND_DCDC shall be respectively placed
ANX7443_1.8V ANX7443_1.8V
close to PIN2, PIN15, PIN26 and PIN49.
R380 R379 ANX7443_1.2V
58
24
30
36
42
8
18
EPAD
ANX7443
4.7K_04 *4.7K_04 R339 R340 3.3V
W/_TYPE_C+DP
W/_TYPE_C+DP
*4.7K_04 *4.7K_04 D01, Ku , ⺈
⓮
⺢嬘
C267 C300 C276
ANX7433_I2C_ADR_SEL0
ANX7433_I2C_ADR_SEL1
0.01u_50V_X7R_04
0.01u_50V_X7R_04
0.1u_10V_X5R_04
shall be respectively placed
close to PIN2, PIN15.
,&0RGH Note:
$''[ : [ 5 SWAP connects to GND
for host side
R347 R348 application.
Or, SWAP connects to
4.7K_04 4.7K_04 VDD18 for device side VDD33 is for
application. source
detection in GND_DCDC
AUX CH.
A A
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Title
[18] USB TYPE-C_ANX7443_Retimer
Size Document Number R ev
Custom NLx0MU 6-71-NLx0MU-D02 D02
ANX7411, Type-C
5 4 3 2 1
7411_AVDD33
W/_TYPE_C+DP
DVDD_IO L8
P/N = 6-19-31001-275
HCB1005KF-121T20 DVDD_IO TYPE-C (USB3.1 Gen2+DP)
DCR = 0.1ohm C297 C295 C302
Impedance = 120ohm C274 C286 C284 close to connector
Rated Current = 2A
5V TYPE-C_VBUS
1u_6.3V_X5R_02 0.1u_6.3V_X5R_02 1000p_50V_X7R_04
1u_6.3V_X5R_02 0.1u_6.3V_X5R_02 1000p_50V_X7R_04
W/_TYPE_C+DP W/_TYPE_C+DP W/_TYPE_C+DP
W/_TYPE_C+DP W/_TYPE_C+DP W/_TYPE_C+DP
5
U36
1 3A
VIN VOUT
15
24
19
U15
7
C484 C478
3.3V W /_TYPE_C+DP DVDD_IO 2
0.1u_25V_X5R_04
AVDD33
AVDD33
DVDD_IO
DVDD_IO
10u_6.3V_X5R_06 GND
D D
VBUS_LDO3.3V D20 A C SS14W S
4 3
D19 A C SS14W S R567 4.7K_04 EN OC#
7mA 5V VCONN_POWER is the power source for VCONN: 3.3V
374uA 1) VCONN Voltage range [3.6V, 5.5V]. W /O_TYPE_C+DP SY6861A1AAC
W /_TYPE_C+DP 2) Internal VCONN Switch: Iout Max 400mA, PCB Footprint = M-SOT23-5
Rdson Max 1.2 ohm. R557 0_04 5V/3A/50m ohm
3) VCONN Minimum power is 1W. [20] ASM1543_PW R_EN
20210812 add for 攳㨇忶ㄊ⮵ 䫾 If DP Alternate Mode is supported, W /O_TYPE_C+DP W /_TYPE_C+DP=6-02-68611-9C0, W /O=6-02-62881-9C0
VCONN power is up to 1.5W.
R356 100K_04 8 TYPEC_SOURCE_CTRL R566 0_04 W/_TYPE_C+DP W PD FUNCTION
9 AUXP 6-07-10422-2A0 0.1u_25V_X5R_04
AUXN W/_TYPE_C+DP W/O_TYPE_C+DP W/O PD FUNCTION
6-07-1042L-2A0 0.1u_10V_X5R_04
B.Schematic Diagrams
21 11
[2] ANX7411_HPD HPD Int. PD 100K SBU1
PWR Rail=DVDD_IO 10 D02 modify D02 modify
SBU2 C299 C298 C303
R361 0_04 7411_TEST_R 14 TYPEC_CC1
PD Function ᶲ SY6861A1AAC 6-02-68611-9C0 ℙ 䓐 䶂嶗
[2] ANX7411_TEST_R W/_TYPE_C+DP CC1 1000p_50V_X7R_04 0.1u_6.3V_X5R_02 10u_6.3V_X5R_06
W/_TYPE_C+DP W/_TYPE_C+DP W/_TYPE_C+DP
䃉 PD ᶲ SY6288E1AA C 6-02-62881-9C
0
16
DVDD_IO VCONN_POWER
13 TYPEC_CC2
USB+DP TYPE C Connector
Sheet 19 of 47 2 CC2 DVDD_IO
TEST_R
PWR Rail=DVDD_IO
ANX7411, Type-C
TYPE-C_VBUS
R354 R353
R352
1.8K_1%_04 1.8K_1%_04 C429 22u_25V_X5R_08
W/_TYPE_C+DP W/_TYPE_C+DP
4.7K_04
W/_TYPE_C+DP C423 22u_25V_X5R_08
MSTR_SDA_7443 Connect to PCH GPP_A11
C 26 C
M_SDA R350 0_04
PWR Rail=DVDD_IO INTP_OUT [7] J_TYPEC+DP1
W/_TYPE_C+DPTYPE-C_VBUS A1 B12
SMB_DATA_7411 22 27 MSTR_SCL_7443 GND GND
TYPE-C_VBUS SMB_CLK_7411 23 CFG_SDA PWR Rail=DVDD_IO M_SCL TYPEC_TX1+_J TYPEC_RX1+_J
CFG_SCL PWR Rail=DVDD_IO A2 B11
TYPEC_TX1-_J A3 TX0_P RX0_P B10 TYPEC_RX1-_J
28 25 INTP_OUT_R TX0_N RX0_N
[34] SINK_CTRL TYPEC_SOURCE_CTRL SINK_CTRL Int. PD 100K INTP_OUT
4 PWR Rail=DVDD_IO R367 C413 1u_25V_X5R_06 A4 B9 C410 1u_25V_X5R_06
SOURCE_CTRL VBUS VBUS
R373 PWR Rail=DVDD_IO 348K_1%_04
TYPEC_CC1_J A5 B8 TYPEC_SBU2_J
10K_06 6-13-34831-28C CC1 SBU2
W/_TYPE_C+DP W/_TYPE_C+DP
3 5 TYPEC_U2D+ A6 B7 TYPEC_U2D-
TEST_EN VBUS_SENSE TYPEC_U2D- USB2_P_T USB2_N_B TYPEC_U2D+
A7 B6
D
CGND
CGND
CGND
CGND
7411_AVDD33
1 6 A12 B1
VSS
I2C_ADR_1 NC 17 GND GND
PWR Rail=DVDD_IO NC DVDD_IO
GND1
GND2
GND3
GND4
ANX7411QN-AC-R UCF3T-21S01-0P01
R364
29
PCB Footprint = qfn28-4x4mmc-1 PCB Footprint = ucf3t-21xxx-xxx1
ROLE_SELECT pin: 4.7K_04 W/_TYPE_C+DP P/N = 6-21-B4D00-024
Logic 1: DRP Mode. W/_TYPE_C+DP
Logic 0: DFP Mode. R338 R335
B R358 0_04 B
NC: UFP Mode. ANX7443_POW ER_EN [18] 1.8K_1%_04 1.8K_1%_04
W/_TYPE_C+DP W/_TYPE_C+DP W/_TYPE_C+DP
I2C_ADR_1 pin: Connected to AP or EC as UART TXD:
R359 D02 modify 1. Don't care before internal reset released.
R365
2. Used to config the I2C address as reset is released. MSTR_SDA_7443
*4.7K_04 *4.7K_04 20210628 3. Can be configured to UART output. MSTR_SDA_7443 [18]
W/_TYPE_C+DP W/_TYPE_C+DP 4. Can be configured to GPIO. MSTR_SCL_7443
MSTR_SCL_7443 [18]
Q40A Q40B
USB2.0 & 3.0 Type-C
G
4 7 TYPEC_TX1-_J
S
D
D
[20] ASM1543_CC2
S
R333 *0_04
D
S
D
[6] I2C1_SDA
MTDK3S6R
W/_TYPE_C+DP
MTDK3S6R
W/_TYPE_C+DP SMB_DATA_7411 [18] SBU2_J
SBU2_J 10 1 TYPEC_SBU2_J
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
6
Title
[19] ANX7411 / TYPE C CON
S
ESD73034D
D
S
G 2
MTDK3S6R
W/_TYPE_C+DP
MTDK3S6R
W/_TYPE_C+DP SMB_CLK_7411
A3 NLx0MU 6-71-NLx0MU-D02 D02
[6] I2C1_SCL
6
D
D
5 4 3 2 1
B - 20 ANX7411, Type-C
Schematic Diagrams
ASM1543
5 4 3 2 1
D D
ASM_3.3V 3.3V
B.Schematic Diagrams
ASM_3.3V ASM_5V
W /O_TYPE_C+DP
C
0 0 X
C
ASM1543
33
32
31
30
29
28
27
26
25
ASM1543_I_SEL0 U31
ASM1543_I_SEL1 ASM_3.3V
USB3.1 Gen2 from back to back co-lay To TYPE-C CON
HC_RDY#
GNDA3
MODE_SEL
VCC2
CC_RDY#
MC_RDY#
GND
PWR_EN
VCONN_EN
PCH
DIFF= 80ohm, L<5" 1 24 A_URXN_SW 1 W /O_TYPE_C+DP R544 0_04
USB3_RX2_NJ I_SEL0/MUX_EN# DA_a1 A_URXP_SW 1 TYPEC_RX1- [19] RX1
R546 0_02 W /O_TYPE_C+DP 2 23 W /O_TYPE_C+DP R543 0_04
[8] USB3_2RXN USB3_RX2_PJ DA_a DA_b1 A_UTXN_SW 1 TYPEC_RX1+ [19]
RX [8] R538 0_02 W /O_TYPE_C+DP 3 22 W /O_TYPE_C+DP C464 0.22u_10V_X5R_04
USB3_2RXP DA_b DB_a1 A_UTXP_SW 1 TYPEC_TX1- [19]
4 21 W /O_TYPE_C+DP C458 0.22u_10V_X5R_04 TX1
5 GNDA1 DB_b1 20 A_URXN_SW 2 W /O_TYPE_C+DP R529 0_04 TYPEC_TX1+ [19]
USB3_TX2_NJ VCC1 DA_a2 A_URXP_SW 2 TYPEC_RX2- [19]
R533 0_02 W /O_TYPE_C+DP 6 19 W /O_TYPE_C+DP R522 0_04 RX2
TX [8] USB3_2TXN
R526 0_02 W /O_TYPE_C+DP USB3_TX2_PJ 7 DB_a DA_b2 18 A_UTXN_SW 2 W /O_TYPE_C+DP C442 0.22u_10V_X5R_04
TYPEC_RX2+ [19]
[8] USB3_2TXP DB_b DB_a2 A_UTXP_SW 2 TYPEC_TX2- [19]
8 17 W /O_TYPE_C+DP C431 0.22u_10V_X5R_04
TX2
ROLE_SEL
I_SEL1/MUX_SEL DB_b2 TYPEC_TX2+ [19]
DFP_CC2
DFP_CC1
VCONN
GNDA2
C231 0.22u_10V_X5R_02 W /_TYPE_C+DP
REXT
USB3_2TXP_R [18] TX W /_TYPE_C+DP C476 0.33u_6.3V_X5R_04
CC2
CC1
C237 0.22u_10V_X5R_02 W /_TYPE_C+DP [18] RX_1_N
USB3_2TXN_R [18] RX1 W /_TYPE_C+DP C475 0.33u_6.3V_X5R_04
C256 0.22u_10V_X5R_02 W /_TYPE_C+DP [18] RX_1_P
C255 0.22u_10V_X5R_02 W /_TYPE_C+DP USB3_2RXN_R [18]
USB3_2RXP_R [18] RX ASM1543 W /O_TYPE_C+DP W /_TYPE_C+DP C463 0.22u_10V_X5R_04
10
11
12
13
14
15
16
9
[18] TX_1_N W /_TYPE_C+DP C457 0.22u_10V_X5R_04
back to back co-lay TX1 [18] TX_1_P
To ANX7443 ASM1543_REXT W /_TYPE_C+DP C453 0.33u_6.3V_X5R_04
[18] RX_2_N
RX2 W /_TYPE_C+DP C449 0.33u_6.3V_X5R_04
ASM_3.3V [18] RX_2_P
ASM_5V
W /_TYPE_C+DP C441 0.22u_10V_X5R_04
R551 2.2K_04 ASM1543_VCONN_EN W /O_TYPE_C+DP [18] TX_2_N W /_TYPE_C+DP C430 0.22u_10V_X5R_04
ASM1543_MODE_SEL
TX2 [18] TX_2_P
R559 2.2K_04 W /O_TYPE_C+DP
R511 2.2K_04 ASM1543_ROLE_SEL W /O_TYPE_C+DP pin1 ASM1543_ROLE_SEL
R548 10K_04 ASM1543_I_SEL0 W /O_TYPE_C+DP
From ANX7443 Close to
B R520 10K_04 ASM1543_I_SEL1 W /O_TYPE_C+DP
ROLE_SEL: B
A A
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Title
ASM1543 / ANX CO-LAY
Size Document Number Rev
A3 NLx0MU 6-71-NLx0MU-D02 D02
Date: W ednesday, August 18, 2021 Sheet 20 of 47
5 4 3 2 1
ASM1543 B - 21
Schematic Diagrams
D
5VS
FOR 14"
L21 . *HCB1608KF-121T30
C497
KB_LED_PW R FOR 15" C292
2A
R360
S
Q19
D 2A
R366 D
G
1K_04 SM3415KIDSH 4.7K_04
10u_6.3V_X5R_06
4.7u_6.3V_X5R_04 FOR 15" FOR 15" FOR 15"
FOR 14"
FOR 15"
5VS
C499
T48
KB_LED_PW R
FON-KB 1
2
3
4
U38
FON
VIN
VOUT
GND
GND
GND
8
7
6
5
FOR 14" R368
2.7K_04
FOR 15"
VSET GND
RGBKBSW _R R355 0_06 KBZONE_R
0.1u_6.3V_X5R_02 NCT3940S-A
D
FOR 14" FOR 14" FOR 15"
Q17 Q43
KBLIGHT_ADJ [24] G MTA90N03ZN3 G 2SK3018S3
[24] EC_PW M_LEDKB_R [24] EC_PW M_LEDKB_P
B.Schematic Diagrams
S
RGBKBSW _G R343 0_06 KBZONE_G
KB_LED_PW R
D
FOR 15"
J_W HITE1 VDD3
Q16
6 G MTA90N03ZN3
D02 modify VDD3 R582 [24] EC_PW M_LEDKB_G
5 FOR 15" J_RGB1
*10K_04
S
4 NC2 RGBKBSW _B R357 0_06 KBZONE_B
20210617 FOR 14" R136
Sheet 21 of 47
3 NC1 1
D
FOR 15"
[24] W HITE_LEDKB_DET# 2 *100K_04 2
FOR 15"
1 Q18 FOR 15" 3
R331 1K_04 LED_KB_PIN4
G MTA90N03ZN3 4
FP225H-006S10M [24] EC_PW M_LEDKB_B R362 100_04 RGBKB-DET#_R
S
FOR 15" KBZONE_R 6
C P/N = 6-20-94K00-006 C
FOR 14" KBZONE_G 7
8
CVM19C3***J430 WHITE LED KB FP225H-008S11M
VCC: 5V fp225h-008gxxxm_r
P/N = 6-20-94K30-108
LED Vf: 2.7~3.4V FOR 15"
Current: 296~520mA
LED
BAT LED
FOR 14" 3.3VS 3.3VS
LED_BAT_CHG_R
[24,29] LED_PW R CAPS NUM
POWER ON LOCK LOCK
1
LED_BAT_FULL_R
R398 LOCK LED R8 LED R1 LED
D21 2.7K_04 2.7K_04 2.7K_04
*AVL18S02015 FOR 14" 20210706 D02 modify
B FOR 14" B
R43 R42
2
D1 D2 D3 20210628
120_04 120_04
A C A C A C
1
P/N = 6-52-57301-022 P/N = 6-52-57301-022 P/N = 6-52-57301-022 D10
PCB Footprint = RY-SP190YG34-5M PCB Footprint = RY-SP190YG34-5M PCB Footprint = RY-SP190YG34-5M RY-SP155HYYG4-1
SG
LED COLOR = W HITE LED COLOR = W HITE LED COLOR = W HITE PCB Footprint = 15-22SURSYGC_TR8A
Y
FOR 14" FOR 14" FOR 14" P/N = 6-52-55002-04E
LED COLOR = GREEN/YELLOW
D5 D6
2
A C A C
*ESD73034D
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Title
[21] LED KB / LED
Size Document Number Rev
A3 NLx0MU 6-71-NLx0MU-D02 D02
Date: W ednesday, August 18, 2021 Sheet 21 of 47
5 4 3 2 1
D
FOR 15" HDD RTD3 POWER FOR 15" HDD CON D
J_HDD1
PJ8 1 2 3mm
FOR 15" HDD_W /O_RTD3 1 SATA_TXP0 C491 0.01u_16V_X7R_04 FOR 15"
2 SATA_TXN0 SATATXP0 [8] SATA_5VS
C492 0.01u_16V_X7R_04 FOR 15" SATATXN0 [8]
3
5VS SATA_5VS 4 SATA_RXN0 C493 0.01u_16V_X7R_04 FOR 15"
5 SATA_RXP0 SATARXN0 [8]
2.5A U37 C494 0.01u_16V_X7R_04 FOR 15" SATARXP0 [8]
5 1 2.5A 6
IN OUT 7 R576
8 SATA_5VS
C490 2
GND C495 9 C309 C308 C305 C306 220_06
10u_6.3V_X5R_04 4 3 10 FOR 15"
B.Schematic Diagrams
EN OCB 0.1u_6.3V_X5R_02
FOR 15" HDD_W /_RTD3 0.1u_6.3V_X5R_02 1u_6.3V_X5R_02 22u_6.3V_X5R_06 22u_6.3V_X5R_06
FOR 15" HDD_W /_RTD3
FOR 15" FOR 15" FOR 15" FOR 15"
B Y ἧ䓐䘬廠↢暣⡻ 婧㔜 ,
SY6288E1AAC FP225H-010S10M ὅ≇䌯 ( 旣ῤ& ⊭墅⣏⮷ )
R575 5V/3A/50m ohm PCB Footprint = FP225H-010-xxxM
D
3.3V FOR 15" HDD_W /_RTD3 P/N = 6-20-94K10-010 Q38
FOR 15"
4.7K_04
G
FOR 15" HDD_W /_RTD3 [31,36] SUSB
Sheet 22 of 47
2SK3018S3
S
FOR 15"
[5] SATA_PW R_EN FROM PCH
U9
W /_TPM R268 4.7K_04 TPM_GPIO 6 1
GPIO0 VDD 8
W /_TPM R254 4.7K_04 TPM_PP 7 VDD 22 C205 C230 C208
PP VDD
B TPM_RST# 17 23 C243 0.1u_6.3V_X5R_02 0.1u_6.3V_X5R_02 1u_6.3V_X5R_02 B
RST# VSS_3 W /_TPM W /_TPM W /_TPM
TPM
[6] TPM_PIRQ# 18 3 0.1u_6.3V_X5R_02
PIRQ# NC_1 4
NC_2 W /_TPM
[5] TPM_SPI_CLK R253 49.9_1%_04 W /_TPM 19 5
SPI_CLK NC_3 10
20 NC_4 11
[5] TPM_SPI_CS2# SPI_CS# NC_5 12
R273 NC_6
49.9_1%_04 W /_TPM 21 13
[5] TPM_SPI_MOSI SPI_MOSI NC_7 14 VDD_TPM
R290 NC_8
[5] TPM_SPI_MISO 49.9_1%_04 W /_TPM 24 15
SPI_MISO NC_9 16
NC_A 25
NC_B C242
R264 20K_04 W /_TPM 26
NC_C 27 0.1u_6.3V_X5R_02
R246 10K_04 W /_TPM 2 NC_D 28 W /_TPM
VDD_TPM VSS_1 NC_E
9 29
32 VSS_2 NC_F 30
33 VSS_4 NC_G 31
GND NC_H
SLB9670VQ F/W 7.85 W /_TPM
VDD_TPM
5
A A
1
[10,24,25,26,29] BUF_PLT_RST# 4 TPM_RST#
2
U8
*TC7SZ08FU
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
3
W /_TPM
Title
R231 0_04 W /_TPM [22] SATA HDD ,TPM
Size Document Number Rev
A3 NLx0MU 6-71-NLx0MU-D02 D02
Date: W ednesday, August 18, 2021 Sheet 22 of 47
5 4 3 2 1
Audio Codec
5 4 3 2 1
V4V3
U12 PD8
40 MIL HPOUT_L
5 1 A C HPOUT_R HPOUT_L [23]
5V VIN VOUT
HPOUT_R [23]
D 2 C446 C452 D
C259 GND 1N914BWS [29] SLEEVE_CONN VNEG_NEG C225 10u_6.3V_X5R_04
4 3 0.1u_6.3V_X5R_02 2.2u_6.3V_X5R_04 [29] RING2_CON
EN# OC# DVDD33
JD MODE
10u_6.3V_X5R_04
SY6288D20AAC [29] MIC_DATA2 AUDG
[29] MIC_CLK2
SY6288D20AAC: 6-02-62882-9C0 C226
uP7549UMA5-20: 6-02-75495-9C0 ADD D-MIC 3/10
[24,28,29] USB_PWR_EN# 0.47u_6.3V_X5R_04 R249
R328 0_04 C257
[24] EC_CODEC_PD# *10p_25V_NPO_02
220K_1%_04
48
47
46
45
44
43
42
41
40
39
38
37
36
35
Del SPDIF 3/9
R329 *0_04
AGND
HPOUT_R
SLEEVE
SPDIF_O
GPIO_8
GPIO_9
VNEG_NEG
CHP_N_NEG
GPIO_10
GPIO_11
RING2
AVDD18
HPOUT_L
CHP_P_NEG
GPIO_7 R510 0_04
HPOUT-JD [29]
PC BEEP
FOR VOLUMN
ADJUST 1 34 D1V8_NEG R267 0_04
GPIO_5 D1V8_NEG BULK_1V8
GPIO_4 GPIO_4 2 33 VREF_PAD C210 10u_6.3V_X5R_04 C209
R327 *4.53K_1%_04 AUDG
[24] KBC_BEEP GPIO_4 VREF_PAD
GPIO_3 3 32 10u_6.3V_X5R_04
6-06-00543-021 GPIO_3 AGND AUDG
R321 GPIO_7 4 31 VRP_PAD C211 10u_6.3V_X5R_04 MIC_BIAS
*4.7K_04 GPIO_7 VRP_PAD AUDG
ADD PC BEEP 3/16 5
CM6542 30 AVDD33 C212 10u_6.3V_X5R_04
GPIO_6 AVDD33 AUDG
B.Schematic Diagrams
CHP_N_BULK
CHP_P_BULK
[8] USB_PP6 DGND ⺈
⓮
⺢ 嬘
DVDD50 A5V
USB_DM DEL ESD 3/10 ADD 3/
18
[8] USB_PN6 R306 22_04
BULK_1V8
I2C_SDAT
I2C_SCLK
C C
USB_DM
USB_DP
PD_R5V
GPIO_1
GPIO_0
Sheet 23 of 47
PDSW
DVDD33
TEST
VSS
SLEEVE_CONN R262 *0_04
C261 C260 AUDG
C219 0.1u_25V_X5R_04 RING2_CON
100p_50V_NPO_04
100p_50V_NPO_04
R270 0_04
11
12
13
14
15
16
17
18
19
20
21
22
23
24
PD_R5V R271 10K_04
Audio Codec
R313 R311
C204 0.1u_25V_X5R_04
2.2K_04 2.2K_04
V4V3
TEST
BULK_1V8 R278 0_04
I2C_SCLK BULK_1V8
I2C_SDAT R215 0_04
USB_DM C240 C239
USB_DP AUDG
2.2u_6.3V_X5R_04 10u_6.3V_X5R_04 Analog_ground Digital_ground
Tied at one point only under
R319 10K_04 TEST Codec or near the Codec
AMP_5VS
6-19-31001-275
L17
HCB1608KF-121T30
D
[10,17,28,33,36] SUSB# [23] HPOUT_R RINN ROUTN R476
D17 RB751S-40H C411
C461 0.1u_25V_X5R_04 23 16 20 Mil J_SPKR1 10u_6.3V_X5R_04 0.1u_6.3V_X5R_02
MODIFY 3/9 AMPGND RINP PVDDR2 200K_04 GPIO_7
D02 modify C508 Connect VAULE FOR 0.1u_6.3V_X5R_02 G
5
6 18 1000p_50V_X7R_04 REFERENCE
PCB FootprintBY
= 85204-02L
6-01-07408-Q71 Q32
S
GPIO_3 C A 20210702 1 PGNDL1 PGNDR1 PROJECT
AUDG AUDG AUDG
P/N = 6-20-43130-102
16
15
14
13
AMP_EN_SPK 2SK3018S3
D40 RB751S-40H 4 7 19 50271-0020N-001 U25
2 20 Mil PGNDL2 PGNDR2 20 Mil AUDG AUDG
U34
SGND
VDD
EN
OUTL
[23,24] KBC_MUTE# GPIO_2
74AHC1G08GW C483 0.1u_25V_X5R_04 1 5 LOUTP L6 . HCB1005KF-121T20 LOUT+ C447
[23] HPOUT_L LINN LOUTP 1
Low mute! 10u_6.3V_X5R_06
4 Ohm Speaker R556 *0_04
3
3.3VS Va u l e ⎗
婧㔜 C487 0.1u_25V_X5R_04 2 9 2 HPOUT_L HPOUT_L_IN 1 12
AMPGND LINP PVDDL1 [23] HPOUT_L INL- PVDD
C448 2 11
R531 10.2K_1%_04 14 4 J_SPKL1 10u_6.3V_X5R_06 3 INL+ CP 10 C400
On 5VS VOLUME PVDDL2 HPOUT_R HPOUT_R_IN INR+ PGND
4 SGND 9 KBC_MUTE# [23,24]
[23] HPOUT_R INR- CN R186 *0_04
R554
AMPGND
R534 15.8K_1%_04 15
NC VDD
13 ⮵ ⛘ 暣⭡ , 2.2u_6.3V_X5R_04
OUTR
PVSS
20 Mil C401
D02 modify *330K_04 B Y ⮎㷔婧 㔜 ,
GO
10 8 LOUTN L7 HCB1005KF-121T20 LOUT- 17 4.7u_6.3V_X5R_04
G1
. ⎗ ᶲ ⎗ᶵ ᶲ
D
TH_PAD
R237 AUDG
11 12 R519 R518 0_04 0_04 SA8908
5
6
7
8
HP_EN_SPK_EN R555 0_04 G ROSC AGND C279 C282 AUDG 3.3V
Gain G0 G1
Q36 1000p_50V_X7R_04 1000p_50V_X7R_04 100K_04 100K_04
S
劍
䃉H P AM Eᾉ
P MUT嘇⎗ᶵ枸 䔁 2015/12/8 R577 TPA2008D2 R209 10K_04
2SK3018S3 -6db LOW LOW
25
C488 AMPGND C422
220p_50V_NPO_04 120K_04 4.7u_6.3V_X5R_04 R243 *10K_04 0db HIGH LOW
6-02-20082-AL0 G1_SV3H706
AMPGND AMPGND R218 *10K_04 3db LOW HIGH
R312 *20mil short-p
AMPGND AMPGND AUDG G0_SV3H706 R233 10K_04
The volume control.the gain range is from 6db HIGH HIGH
-80db(Vvolume=5V) to +20db(Vvolume=0V) with
64 steps precise control. AMPGND AUDG
HEADPHONE_R_DEPOP [29]
A A
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Title
[23] AUDIO CODEC_CM6542
Size Document Number Rev
Custom NLx0MU 6-71-NLx0MU-D02 D02
Date: Wednesday, August 18, 2021 Sheet 23 of 47
5 4 3 2 1
B - 24 Audio Codec
Schematic Diagrams
114
121
127
KBC_AGND 71
11
26
50
92
74
PCH_DPWROK_EC ADC5/DCD1#/GPI5(3) OPTION
3
U3A J_14KB1 J_15KB1 72 96
[34] SINK_CTRL_EC ADC6/DSR1#/GPI6(3) OPTION OPTION ID3/GPH3 3G_EN [27]
76 97
VSTBY
VSTBY
VSTBY
VSTBY
VSTBY
VCC
AVCC
GPH7
VSTBY(PLL)
[21] LED_BAT_FULL TACH2A/GPJ0(3) OPTION OPTION ID4/GPH4 3G_PWR_EN [27]
10 58 KB-SI0 4 KB-SI0 4 98
[5] ESPI_IO0_EC EIO0/LAD0/GPM0(3) KSI0/STB# OPTION ID5/GPH5 LED_BAT_CHG [21]
9 59 KB-SI1 5 KB-SI1 5
[5] ESPI_IO1_EC EIO1/LAD1/GPM1(3) KSI1/AFD#
8 60 KB-SI2 6 KB-SI2 6
[5] ESPI_IO2_EC EIO2/LAD2/GPM2(3) KSI2/INIT# SMC_PD74XX_EC
7 61 KB-SI3 8 KB-SI3 8 115
[5] ESPI_IO3_EC EIO3/LAD3/GPM3(3) KSI3/SLIN# SMD_PD74XX_EC SMCLK1/GPC1 OPTION
13 62 KB-SI4 11 KB-SI4 11 116 56 KB-SO16
[5] ESPI_CLK_EC ESCK/LPCCLK/GPM4(3) KSI4 SMDAT1/GPC2 KSO16/SMOSI/GPC3(3)
6 63 KB-SI5 12 KB-SI5 12 118 57 KB-SO17
[5] ESPI_CS_EC# ECS#/LFRAME#/GPM5(3) KSI5 [10,24,31] SLP_SUS# SMDAT2/PECIRQT#/GPF7(3) KSO17/SMISO/GPC5(3)
5 LPC 64 KB-SI6 14 KB-SI6 14
EC_ERST# [6] ALERT# ALERT#/SERIRQ/GPM6(3) KSI6 OPTION OPTION
22 65 KB-SI7 15 KB-SI7 15 79
ERST#/LPCRST#/GPD2 KSI7 OPTION DAC3/TACH1B/GPJ3(3) SLP_S0# [10,33]
K/B MATRIX 24
[21] EC_PWM_LEDKB_P PWM0/GPA0 OPTION
100K_04 KBC_WRESET# 14 36 1 1 31
P/N = 6-20-94K00-024
[10] AC_PRESENT RXD/SIN0/PWUREQ#/BBO/SMCLK2ALT/GPC7(3) KSO4/PD4
B.Schematic Diagrams
18 41 KB-SO5 10 KB-SO5 10 2
[13,37] AC_IN# RI1#/GPD0(3) KSO5/PD5 GPJ7 WHITE_LEDKB_DET# [21]
GPIO 42 KB-SO6 13 KB-SO6 13 128 R82 *10K_04
[17] BKL_EN KSO6/PD6 GPJ6
43 KB-SO7 16 KB-SO7 16 28
P/N = 6-21-94200-026
[21,29] LED_PWR KSO7/PD7 [29] CPU_FANPWM PWM2/GPA2 D02 modify
15 44 KB-SO8 17 KB-SO8 17 29
[13] SMI# ECSMI#/GPD4(3) KSO8/ACK# [25] WLAN_PWR_EN PWM3/GPA3 OPTION
23 45 KB-SO9 18 KB-SO9 18 30
[10,33] CPU_C10_GATE# ECSCI#/GPD3 KSO9/BUSY [10] PCH_PWROK_EC SMCLK5/PWM4/GPA4
46 KB-SO10 19 KB-SO10 19
IT5570 KSO10/PE
KSO11/ERR#
51 KB-SO11 20 KB-SO11 20
52 KB-SO12 21 KB-SO12 21 IT5570E-128/CX
KSO12/SLCT
Sheet 24 of 47
53 KB-SO13 22 KB-SO13 22 PIN128劍
ᶵ㗗ἧ䓐 ⢾ 悐 c ry s t a l ,
KSO13 54 KB-SO14 23 KB-SO14 23 1. 䓐䨢
ᶵ
劍 IN炻暨 PULL D OW N,
P
KSO14 55 KB-SO15 24 KB-SO15 24 2. 劍䁢GPI O PI 暨
ὅ
N ≇傥 PU LL UP OR D
W.
O N
KSO15 KB-SO16 25
BAT_DET 66 FP266H-024S10M KB-SO17 26 DEFAULT㓡
ᶲẞ ,(⤪
㰺 㚱 ᶲẞ
, RT C便 暣 忶
⣏)
KBC ITE IT5570
[24,37] BAT_DET BAT_VOLT ADC0/GPI0(3)
67 FOR 14"
[37] BAT_VOLT THERM_VOLT ADC1/GPI1(3)
69 ADC FSPI_3.3V FP226H-026S10M
[2] THERM_VOLT TOTAL_CUR ADC3/GPI3(3)
70 FOR 15"
B [37] TOTAL_CUR ADC4/GPI4(3) VDD3 B
106 R80 0_04 VDD3
MODEL_ID 73 VSTBY_FSPI
ADC7/CTS1#/GPI7(3) MODEL_ID RA RB Voltage
C
125 3.3V AC
SSCE1#/GPG0 LED_NUM# [21] NL40CU 10K_04 X [24,37] SMC_BAT
SMBUS D13 A
GPG0 DEFAULT GPO HIGH ἧ 暨
䓐䡢娵
R120 47_04 19 BAV99 RECTIFIER
[24,37] SMC_BAT SMCLK4/L80HLAT/BAO/GPE0 NL50CU X 10K_04 0V
R124 47_04 20 95 T49 C
[24,37] SMD_BAT SMDAT4/L80LLAT/GPE7 CTX1/SOUT1/GPH2/SMDAT3/ID2 AC
EC_PECI117 NL40CU CM6542 22.1K_1%_04 34K_1%_04 2V [24,37] SMD_BAT
R73 43_1%_04 D12 A
[13] H_PECI PECI/SMCLK2/GPF6(3) EC_RSMRST#
35 BAV99 RECTIFIER
C108 *5p_25V_NPO_04 RTS1#/GPE5 17 VDD3 NL50CU CM6542 8.45K_1%_043.65K_1%_04 1V C
TXD/SOUT0/LPCPD#/GPE6 SB_KBCRST# [6]
AC
[24,37] BAT_DET
47 VDD3 D14 A
TACH0A/GPD6(3) CPU_FANSEN [29]
25 BAV99 RECTIFIER
[23] KBC_BEEP PWM1/GPA1 MODEL_ID RA 10K_04 FOR 14"
120 R129
OPTION TMRI0/GPC4(3) CNVI_DET# [25]
124 R77
TMRI1/GPC6(3) PM_PWROK [10] RB 10K_04 FOR 15"
10K_04 R125
123
OPTION CTX0/TMA0/GPB2(3) EC_PCIE_WAKE# [10,25,29]
80CLK 85
[26] 80CLK PS2CLK0/CEC/TMB0/GPF0
3IN1 87
[26] 3IN1 SMCLK0/GPF2 SLP_SUS#
126 R79 *100K_04
GA20/GPB5(3) SWI# [5,6]
86
[30] USB_CHARGE_EN PS2DAT0/TMB1/GPF1 OPTION CCD_EN
88 R128 *100K_04
[25] EC_BT_EN SMDAT0/GPF3 OPTION
89 93 EC_CLKRUN# R93 *0_04 WLAN_PWR_EN R158 *100K_04
[29] TP_CLK PS2CLK2/GPF4 OPTION CLKRUN#/ID0/GPH0 PM_CLKRUN# [9]
90 PS/2
[29] TP_DATA PS2DAT2/GPF5 EC_RSMRST#
99 R177 10K_04
ID6/GPH6 SUSB#_PCH [10]
94
CRX1/SIN1/SMCLK3/GPH1/ID1 SUSC#_PCH [10] AC_IN#
110 C110 0.1u_16V_X5R_02
OPTION
妶
婾㗗⏎婳 EC 㓡 L o 䁢 en a
bl e 112 0.1u_6.3V_X5R_02
84 VSTBY0 107 EC ROM
VCORE
W/_TPM
D02 modify [21] RGBKB-DET# XLP_OUT [30] 1Mbit
VSS
VSS
VSS
VSS
1
27
49
91
113
122
75
SI VDD
R117 ALSPI_MSO R429 33_04 W/_TPM EC_SO 2 R426
SO 3.3K_1%_04
ALSPI_CE# R432 0_04 W/_TPM EC_CE# 1 3 FDIO2
Detect USB CHARGE Function C169 CE# WP#
*20mil short-p W/_TPM
H: W/O CHAR 0.1u_6.3V_X5R_02 KBC_AGND ALSPI_SCLK R434 33_04 W/_TPM EC_SCK 6 R439
L: W/ CHAR VDD3 SCK 3.3K_1%_04
4 7 FDIO3
WLAN_EN [25] Co-LAY VSS HOLD# W/_TPM
ALL_SYS_PWRGD [10,17,38]
GD25D10CTIGR W/_TPM
PCB Footprint = M-SO8
R108
10K_04
W/O_CHAR
VDD3 㕘⡆
KBC_MUTE# R169 0_04 [19] SMD_PD74XX_EC
SLP_SUS# [10,24,31]
[19] SMC_PD74XX_EC
VDD3 (BOT SIDE)
R202 VDD3
R114 for EC debug use
10K_04
VDD3 őŪůġ ķķſĸĴ䔞 㓡ŨűŪ Ű ġ ⎒傥Ūůű Ŷ ŵ ġ 䃉㱽Ű Ŷ Ŷŵġűᶼ
*47K_04 ⢾ 悐 天űŶ ŭ ŭġ ũŪŨũį R372 *0_06
W/_CHAR
5
100K_04
C
D15
C A R167 90.9K_1%_04 B Q10
VIN
ZD5231BS2
MMBT3904H
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
E
R166
C200 20K_1%_04 Title
*0.1u_16V_X5R_02
EC_RSMRST#
[24] IT5570
Size Document Number Rev
Custom NLx0MU
6-71-NLx0MU-D02 D02
WLAN
1
WLAN/CNVi
W LAN_3.3V
>40 mil
VDD3 R402 *10K_04
75 74
73 GND13 3.3V3 72
[9] CNVI_W T_CLKP WT_CLKP 3.3V2
71 70
[9] CNVI_W T_CLKN WT_CLKN PEWAKE1_N
69 68
67 GND12 CLKREQ1_N 66
CNVi [9] CNVI_W T_D0P
65 WT_D0P PERST1_N 64
[9] CNVI_W T_D0N WT_D0N REFCLK0 T1
63 62
61 GND11 NEW PART IRQ_N(I) 60
[9] CNVI_W T_D1P WT_D1P I2C CLK(O)
59 58
[9] CNVI_W T_D1N WT_D1N I2C DATA(IO) W LAN_EN_R
57 56 R2 0_04 W LAN_EN R96 0_04
GND10 W_DISABLE1_N(O) W LAN_EN [24] PCH_BT_EN [7]
B.Schematic Diagrams
Sheet 25 of 47
39 38
C331 0.1u_10V_X7R_04 PCIE_TXN10_W LAN_R 37 GND7 CLINK_RESET 36 CNVI_BRI_DT_R R228 0_04
[8] PCIE_TXN10_W LAN PETN0 UART_RTS/BRI_DT CNVI_BRI_DT [9]
C332 0.1u_10V_X7R_04 PCIE_TXP10_W LAN_R 35 34 CNVI_RGI_RSP_R R11 49.9_1%_04
[8] PCIE_TXP10_W LAN PETP0 UART_CTS/RGI_RSP CNVI_RGI_DT_R CNVI_RGI_RSP [9]
33 32 R179 0_04
GND6 UART_TX/RGI_DT CNVI_RGI_DT [9]
WLAN
PCIE TX AC CAP NEAR PCH R10 47K_04 CML-U:22Ω
1.8VA
WHL-U:33Ω
VDD3 CLOSE TO M.2
E KEY TGL-UP3:0Ω
23 22 CNVI_BRI_RSP_R R17 49.9_1%_04
[9] CNVI_W R_CLKP WGR_CLKP UART_RX/BRI_RSP CNVI_BRI_RSP [9]
D02 modify [9] CNVI_W R_CLKN 21 20
R14 WGR_CLKN UART_WAKE_N CNVI_W AKE# [13]
19 18
ℙ 䓐 䶂嶗 100K_04 GND5 GND4
L: CNVi [9] CNVI_W R_D0P 17 16 R19 10K_04 W LAN_3.3V
15 WGR_D0P LED2_N(OD) 14
H: W/O CNVi [9] CNVI_W R_D0N WGR_D0N PCM_OUT/CLKREQ0 CNVI_CLKREQ [7]
CNVI_DET# 13 12
[24] CNVI_DET# GND3 PCM_IN
[9] CNVI_W R_D1P 11 10
WGR_D1P PCM_SYNC/LCP_RSTN CNVI_RST# [7]
[9] CNVI_W R_D1N 9 8
7 WGR_D1N PCM_CLK 6 W LAN_3.3V
GND2 LED1_N(OD) >40 mil
5 4
[8] USB_PN10 USB_DN 3.3V1
BLUETOOTH 3 2 R26 R28
[8] USB_PP10 USB_DP 3.3V0
CNVi M.2 A+E KEY BT㍍USB 2. 0 P ORT 1 *71.5K_1%_04 75K_04
PCH-LP USB2.0 PORT-10 GND1 C15 C9 C4
Hybrid M.2 KEY-E 2230 CML-U:NC CLOSE TO PCH
PCH-H USB2.0 PORT-14 WHL-U:71.5K_04
A CLOSE TO PCH A
PIN 2, 4
22u_6.3V_X5R_06
PIN 2, 4
0.1u_6.3V_X5R_02
0.01u_16V_X7R_04
RF_ 05_04_2021
USB 暨
婳 BI O S姕 ⭂ 䁢 XH C
I NASE0-S6701-TSH4 TGL-U:NC CNVI_RGI_RSP_R R12 *20K_04 1.8VA
ᶵ
⎗䓐 USB3 . 0 po
rt妲
嘇 㚫 忈 ㆸ B T Power Man agement Isu
e. P/N = 6-21-84300-075
PCB Footprint = nxse0-s67xx-xx64x
HEIGHT = 3mm
W LAN_EN W LAN_3.3V
The Hybrid M.2 E-Key is used for: BT_EN T2
T10 CLOSE TO M.2
1. CNVi RF(Jefferson Peak) W LAN_PW R_EN W LAN_EN R3 *10K_04
W LAN_3.3V T3 BT_EN
2. Discrete WiFi (PCIe v2.1 Gen1) T4 R6 *10K_04
3. Discrete WiGig (PCIe v2.1 Gen2) These TEST PAD put together in BOT side
CLOSE TO CONN.
4. CNVi+WiGig combo(Cedar Peak) BUF_PLT_RST# R4 100K_04
5. Qualcomm WiGig/WLAN/BT CLOSE TO M.2
combo(Sparrow) on Cannon Lake, Coffee
Lake, and Gemini Lake platform. 1.8VA
1u_6.3V_X5R_02 3 2
EN GND
AP2821KTR-G1
AP2821KTR-G1
P/N = 6-02-02821-9C0
[24] W LAN_PW R_EN
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Title
[25] WLAN ( B, E KEY )
Size Document Number Rev
B - 26 WLAN
Schematic Diagrams
D02 modify
ℙ 䓐 䶂嶗 >120 mil
D R396 SSD_3.3VS D
SATAGP2 J_SSD1
L: SATA 100K_04 C320 C268 C271
H: PCIe 75 22u_6.3V_X5R_06
73 GND13 74 0.1u_6.3V_X5R_02 0.1u_6.3V_X5R_02
⚈S S D㰺
㚱㓗 ㎜SATA≇
傥炻 㓭
ᶵ暨天 㬌 P in炻 Ữ
ḇ姙暨
天 pull h i g h 71 GND12 3.3V8 72 FOR OPTANE SUPPORT
PCIE_SATA 69 GND11 3.3V7 70
67 PEDET(NC-PCIe/GND-SATA) 3.3V6 68 GND GND GND
NC18 SUSCLK(32Khz)(O) SSD_3.3VS
B.Schematic Diagrams
55 56
[9] CLK_PCIE_SSD1 REFCLKP NC16
53 54 R370 0_04
[9] CLK_PCIE_SSD1# REFCLKN PEWake#(IO) PCIE_W AKE# [10]
51 52
PCIE4_TXP0_SSD_C GND9 CLKREQ#(IO) PLTRST_SSD1# SSD1_CLKREQ# [9]
C500 0.22u_10V_X5R_02 49 50
[8] PCIE4_TXP0_SSD PCIE4_TXN0_SSD_C PETp0/SATA-A+ PERST#(O)
C501 0.22u_10V_X5R_02 47 48 SSD_CLKREQ# PU 10K_04 IN PCH SIDE
[8] PCIE4_TXN0_SSD PETn0/SATA-A- NC15
45 46
43 GND8 NC14 44
[8] PCIE4_RXP0_SSD PERp0/SATA-B- NC13
41 42
Sheet 26 of 47
[8] PCIE4_RXN0_SSD PERn0/SATA-B+ NC12
39 40
C502 0.22u_10V_X5R_02 PCIE4_TXP1_SSD_C 37 GND7 NC11 38 R382 0_04
[8] PCIE4_TXP1_SSD PCIE4_TXN1_SSD_C PETp1 DEVSLP(O) DEVSLP0 [8]
C503 0.22u_10V_X5R_02 35 36 R383 0_04
[8] PCIE4_TXN1_SSD PETn1 NC10 VDD3
33 34 R385 0_04
B B
C325
[6] GPP_D3_RTD3 1 C278 C321
PLTRST_SSD1# 0.1u_6.3V_X5R_02
4 5 1
IN OUT 0.1u_6.3V_X5R_02 0.1u_6.3V_X5R_02
2 U17
[10,22,24,25,29] BUF_PLT_RST# M.2_SSD_W /_RTD3 M.2_SSD_W /_RTD3 M.2_SSD_W /_RTD3
74AHC1G08GW 2
GND
M.2_SSD_W /_RTD3
3
A
3.3V R393 10K_04 4 3 A
R395 EN OCB
M.2_SSD_W /_RTD3
U16 3A
1M_04
R392 0_04 SY6288E1AAC
M.2_SSD_W /_RTD3
M.2_SSD_W /O_RTD3 R394 0_04 M.2_SSD_W /_RTD3
[6] SSD1_PW R_DN#
M.2_SSD_W /_RTD3 ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Title
[26] SSD PCIE ( M KEY )
Size Document Number Rev
A3 NLx0MU 6-71-NLx0MU-D02 D02
3G/LTE
5 4 3 2 1
220u,6.3V,ESR=15mΩ,H=1.9mm
80 mils
J_3G1 C377 EEFCX0J221YR For 15" LTE
+
3G_PW R_EN
75 74 C113 0.1u_6.3V_X5R_02 For 15" LTE
73 CONFIG_2 3.3V4 72
D D
71 GND10 3.3V3 70 C106 0.1u_6.3V_X5R_02 For 15" LTE
GND9 3.3V2 R138
69 68
CONFIG_1 SUSCLK(32Khz)(O) M2_SIM_DET *100_06
67 66 pin66 H= USIM present
65 Reset#(O)1.8V SIM Detect(O) 64
ANTCTL3(I)1.8V COEX1(I/O)1.8V pin66 L= USIM absent
63 62 PW R_ON_OFF
ANTCTL2(I)1.8V COEX2(I/O)1.8V C129
61 60 For 15" LTE
ANTCTL1(I)1.8V COEX3(I/O)1.8V 470p_50V_X7R_04
59 58
57 ANTCTL0(I)1.8V NC1 56 For 15" LTE
GND8 NC0 M.2 3G/4G-LTE module SIM Detect Pin 66炻 R147
55 54
REFCLKP PEWake#(IO) internal 1.8V with Pull-up *12K_06
53 52 GND
51 REFCLKN CLKREQ#(IO) 50
49 GND7 PERST#(O) 48
47 PETp0/SATA-A+ GPIO_4(IO)1.8V 46 For 15" LTE
45 PETn0/SATA-A- GPIO_3(IO)1.8V 44
43 GND6 GPIO_2(IO)1.8V 42
PERp0/SATA-B- GPIO_1(IO)1.8V
B.Schematic Diagrams
L12 *W CM2012F2S-SHORT 41 40
1 For 15" LTE2 39 PERn0/SATA-B+ GPIO_0(IO)1.8V 38 3G_3.3V
C378 0.1u_16V_X7R_04 USB3_4TXP_C USB3_4TXP_L 37 GND5 DEVSLP(O) 36 UIM_PW R
[8] USB3_4TXP USB3_4TXN_C PETp1/USB3.0-Tx+/SSIC-TxP UIM_PWR(I) UIM_PW R [29]
[8] USB3_4TXN C379 0.1u_16V_X7R_04 4 3 USB3_4TXN_L 35 34 UIM_DATA
PETn1/USB3.0-Tx-/SSIC-TxN UIM_DATA(IO) UIM_CLK UIM_DATA [29]
For 15" LTE 1 2
For 15" LTE 33 32 C168
USB3_4RXP_L GND4 UIM_CLK(I) UIM_RST UIM_CLK [29] M2_SIM_DET
For 15" LTE 31 30 For 15" LTE For 15" LTE
[8] USB3_4RXP PERp1/USB3.0-Rx+/SSIC-RxP UIM_RESET(I) UIM_RST [29] R89
4 3 USB3_4RXN_L 29 28 0.1u_6.3V_X5R_02
[8] USB3_4RXN PERn1/USB3.0-Rx-/SSIC-RxN GPIO_8(IO)1.8V *100K_04
27 26
D
L15 *W CM2012F2S-SHORT R122 *0603_short
BODYSAR_N GND3 GPIO_10(IO)1.8V
Sheet 27 of 47
R119 *0_04 25 24
For 15" LTE T11 3G_W AKE# 23 GPIO_12(IO)1.8V GPIO_7(IO)1.8V 22 For 15" LTE G SIM_DET
GPIO_11(IO)1.8V GPIO_6(IO)1.8V ᶵ㓗 ㎜ GP S ≇ 傥 ẍ PULL DOWN
8/12 RF⡆
≈ 21
CONFIG_0 GPIO_5(IO)1.8V
20
Q8
SIM_DET [29]
For 15" LTE
S
暨冯 M .2⎴ 朊 For 15" LTE *2SK3018S3
3G/LTE C
USB_PN4_L
11
GND2
B KEY
GPIO_9/DAS/DSS#(I)(OD)
10
For 15" LTE T12
3G_EN [24]
R92 0_04
C
1 2 9 8
[8] USB_PN4 USB_PP4_L USB_D- W_DISABLE#1(O) PW R_ON_OFF R157
7 6 10K_04
[8] USB_PP4 USB_D+ Full_Card_Power_Off#(O)1.8V For 15" LTE
4 3 5 4
3 GND1 3.3V1 2 For 15" LTE 80 mils
L14 For 15" LTE GND0 3.3V0 3G_3.3V
1 NGFF_B
*WCM2012F2S-SHORT CONFIG_3
PCB Footprint = W CM2012F2S-short + C384 For 15" LTE C196 C195
NASB0-S6701-TSH4 10u_6.3V_X5R_04 0.1u_6.3V_X5R_02
4G-LTE module䘬 USB 3.0 interface婳
ᶨ
⭂
天
㍍ ⇘ ㊯⭂䁢 USB 3.0 䘬S I
C
Por
.
t EEFCX0J221YR
PCB Footprint = 213baaa32xa For 15" LTE For 15" LTE
SKYLAKE㚨
㕘
䘬 H 䲣↿ 䘬 EDS & D esign guide 䴻㰺 㚱 ⭂佑
(Rev
)
0
.
1 SS
C
I
port炻
ỮSKYLAK E Y 婳 U㍍⇘US B3.0 POR T.
2 P/N = 6-21-84KY0-075
䔞
ἧ
䓐 䘬 SKYLAK E-H pltaf
rm㗪 炻 4 G
o - LTE 䘬US
B3.
0 HEIGHT = 3mm
interface⎗ ẍ冒
埴⭂佑 忋 ㍍ ⇘ Skylak e - H ả ỽ 䘬ᶨ ᾳUSB3.0 䘬 P o rt⯙⎗ ẍḮ ˤ
For 15" LTE
220u,6.3V,ESR=15mΩ,H=1.9mm
3G POWER
3G_3.3V
Q6
>120 mil SM3415KIDSH >120 mil
S D
3.3V
B B
C94
C123
G
For 15" LTE For 15" LTE
1u_6.3V_X5R_02
C85 1u_6.3V_X5R_02 For 15" LTE 0.1u_6.3V_X5R_02
For 15" LTE
R76
R66
10_06
20K_1%_04
3
6
D Q5B
Q5A 5G MTDK5S6R
For 15" LTE
R68 0_04 2G MTDK5S6R S
[24] 3G_PW R_EN
4
S For 15" LTE
1
For 15" LTE
ADD R386,Q23 Solution For
PDA
BUG-When Battery discharge
to
shutdown, the CMOS
sometimes
loss.
A A
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Title
[27] 3G/LTE ( B KEY )
Size Document Number Rev
B - 28 3G/LTE
Schematic Diagrams
USB Type-A
5 4 3 2 1
D D
B.Schematic Diagrams
Sheet 28 of 47
C C
USB Type-A
5
U23
80 mil
1
VIN VOUT
C395 2
CB Smart CDP 10u_6.3V_X5R_04 GND C398
pin8 pin4 Function 4
EN# OC#
3 0.1u_6.3V_X5R_02
SY6288D20AAC
0 X DCP autodetect with USB_DD_ON#
2A/90mohm
mouse/keyboard wake up USB3.1 Max Trace length SY6288D20AAC: 6-02-62882-9C0
Follow Design Guide uP7549UMA5-20: 6-02-75495-9C0
1 0 S0 Charging with SDP
USB PORT Charge
VDD5
1 1 S0 Charging with CDP
B B
If select CB pin contact to SUSB#, you can Support 80 MIL
C182 22u_6.3V_X5R_06
DCP mode and Apple-compliant devices charge in 1 2 USBVCC_CH
C183 22u_6.3V_X5R_06
S3 status. D33 15KV/0.2PF CESD0201UC5VB-M
1 2 6-24-40001-018
J_USB3_1
R176 FROM PCH D34 15KV/0.2PF CESD0201UC5VB-M
1
10K_04 USB3_1TXPC 6-24-40001-018 VBUS
[10,17,23,33,36] SUSB# R135 *0_04 [8] USB3_1TXP C381 0.1u_6.3V_X5R_02 9 GND1
W /_CHAR USB3_1TXNC SSTX+ SHIELD
W /_CHAR U4 TX C380 0.1u_6.3V_X5R_02 8 GND3
Standard-A
USB_DD_ON# [8] USB3_1TXN SSTX- SHIELD
[24,30,36] DD_ON R140 0_04 8 1 D32
W /_CHAR CB PRE# USB3_1RXP6
USB_PN1 7 2 USB_PN1_R 6 5 USB3_1RXN5 SSRX+
[8] USB_PN1 TDM DM SSRX-
7 4 7
USB_PP1 6 3 USB_PP1_R R465 USB_PN1_R 1 2 USB_PN1R 8 3 GND_D
[8] USB_PP1 TDP DP 100K_04 9 2 GND4
GND
D31
2
2
15KV/0.2PF CESD0201UC5VB-M
15KV/0.2PF CESD0201UC5VB-M
6-24-40001-018
6-24-40001-018
A A
W/O USB CHARGER
1
R472
W /O_CHAR
0_04
0_04
USB_PP1_R
USB_DD_ON#
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
[23,24,29] USB_PW R_EN# Title
W /O_CHAR [28] USB TYPE-A(1)(CHARGER)
Size Document Number Rev
A3
6-71-NLx0MU-D02 D02
Date: W ednesday, August 18, 2021 Sheet 28 of 47
5 4 3 2 1
USB Type-A B - 29
Schematic Diagrams
TP_VCC
1
PCB Footprint = fp225h-008gxxxm_r TP_CLK [24] CPU_FANSEN
LID_SW # [24] TP_CLK TP_DATA
P/N = 6-20-94K30-108 A C *10u_6.3V_X5R_06
[24] TP_DATA
D43
3.3VS R454 4.7K_04
*V15AVLC0402 TP_ATTN# [13]
C485 C486
10K_04 R580 3.3VS 47p_25V_NPO_02 47p_25V_NPO_02
2
B.Schematic Diagrams
D24 C A
RB751S-40H
EC_PCIE_WAKE# [10,24,25]
15" SIM CARD
[29] LAN_W AKEUP#_R
D25 C A
LAN_W AKEUP# [10]
VDD3
LID SWITCH IC 15" PWR SW BOARD
RB751S-40H
暞
ẞ㔠 ÿ ÷ å ĵ Ĩĸ
Sheet 29 of 47
J_SIM1
3.3VS 1 UIM_PW R [27]
U1
LID_SW # J_BTN1 2
C 1 2 C
GND
4 SIM_DET [27]
3G_SIM
2
0701 NC1 2 M_BTN# LED_PW R [21,24]
5 UIM_CLK [27]
C5 C3 NC2 3
6 UIM_DATA [27]
YB8251ST23 D4 4 UIM_RST [27]
3
0.1u_6.3V_X5R_02 P/N = 6-02-08251-LC0 *100p_50V_NPO_02 *V15AVLC0402 7
2 GND 8
FP226H-004S10M GND
1
P/N = 6-20-94A40-004
1 3 GND
PCB Footprint = fp226H-004xxxm_r
GND GND GND FP225H-008S11M
䡢娵ᶲẞỵ 伖 For 15" PW R
GND fp225h-008gxxxm
P/N = 6-20-94K30-108
For 15" LTE
LAN BOARD CONN VDD3 I/O BOARD CONN CCD+ DIGITAL MIC
J_14MB CCD_PW R
U19
1 J_IO1 1A 4 1
1A
2 3.3VS VIN VOUT
1 5V 5
3 3.3VS VIN
2 C348 C345
4
LAN_RTD3_REL [6] 3
GND1 5 1u_6.3V_X5R_02 3 2 2.2u_6.3V_X5R_04
PM_SLP_LAN# [10] 4
GND2 6 EN GND
GLAN_CLKREQ# [9] GND1 5
7 AP2821KTR-G1
CARD_CLKREQ# [9] GND2 6
B GND 8 B
LAN_W AKEUP#_R [29] 7 㬌㕁嘇 䁢 3 A ,
9
8 CCD_EN
Footprint=FP201-040X1-0M pin1 fix
10 SDCARD_W AKE# [6]
9 [24] CCD_EN ⤪
䓐 2n d s o u r ce 㗪 5VS
11 LAN_DISABLE# [10] 3.3V 天 㲐 シㅱ 䓐
GND 10 J_CCD1
12 LAN_ID [6] 3.3VS From EC default HI
11
50208-01201-001 12 POWER SW R564 0_04 USB2.0 1
PCB Footprint = 50208-012xx-xxx_r
P/N = 6-21-64D00-112
13
14
M_BTN#
M_BTN# [36] 1 2
Colay USB_PN3 [8] [8] USB_PN7
1 2 USB_PN7_J 2
PCB Footprint = W CM-2012 3
15
16 USB_TYPE [7]
L20
4 3 *WCM2012F2S-161T03 CCD 4 3 USB_PP7_J USB_PN7_C 4
USB_PP3 [8] [8] USB_PP7 USB_PP7_C 5 GND1
17 L9
R563 0_04 *WCM2012F2S-161T03-short 6 GND2
18
J_LAN1 7
19
3.3VS MIC_DATA2_L 8
SML0_CLK [5] 20 L10 1 2 FCM1005KF-241T03 MIC_DATA2_R
1 USB3_3TXP [8] [23] MIC_DATA2 MIC_CLK2_L 9 GND
SML0_DATA [5] 21 L11 1 2 FCM1005KF-241T03 MIC_CLK2_R
2 USB3_3TXN [8] [23] MIC_CLK2 10
22
3 USB 3.1 11
PCIE_RXP6_CARD [8] 23 C351 C354
4 USB3_3RXN [8] 12
PCIE_RXN6_CARD [8] 24 R541 0_04
5 USB2.0
*47p_25V_NPO_02
*47p_25V_NPO_02
25 USB3_3RXP [8] 50208-01201-001
6
7 CLK_PCIE_CARD [9] 26 USB_PP5_L 1 2
Colay USB_PP5 [8]
R421
*100K_04
PCB Footprint = 50208-012xx-xxx_r
P/N = 6-21-64D00-112
CLK_PCIE_CARD# [9] 27 PCB Footprint = W CM-2012
NC1 8 L18
28 USB_PN5_L 4 3 *WCM2012F2S-161T03 D23
NC2 9 USB_PN5 [8]
PCIE_TXP7_GLAN [8] 29
10
PCIE_TXN7_GLAN [8] 30 R540 0_04 USB_PN7_C 5 6 USB_PN7_J
GND 11 USB_PW R_EN# [23,24,28]
31 USB_PP7_C 4 7 USB_PP7_J
12
PCIE_RXP7_GLAN [8] 32 3 8
13
PCIE_RXN7_GLAN [8] 33 MIC_DATA2_L 2 9 MIC_DATA2_R
14 RING2_CON [23]
34 MIC_CLK2_L 1 10 MIC_CLK2_R
15 SLEEVE_CONN [23]
A CLK_PCIE_GLAN [9] 35 A
16 HPOUT-JD [23] HEAD-PHONE
CLK_PCIE_GLAN# [9] 36
17
37 *ESD73034D
18 HEADPHONE_L_DEPOP [23]
PCIE_TXP6_CARD [8] 38 PCB Footprint = dfn10-2_5x1mm-short
19 HEADPHONE_R_DEPOP [23]
PCIE_TXN6_CARD [8] 39
20
40
21
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
2
22 BUF_PLT_RST# [10,22,24,25,26]
FP201H-040S10M EMD1
FP225H-02261BM *15KV/0.2PF CESD0201UC5VB-M Title
P/N = 6-20-94K20-140 AUDG GND
PCB Footprint = FP225-022-L
P/N = 6-20-94K10-022 PCB Footprint = FP201-040X1-0M
[29] CONN,CCD&IR,FAN,T/P
ADD for EMI NICK 3/18
GND Size Document Number Rev
6-71-NLx0MU-D02
1
A3 NLx0MU D02
AUDG
Date: W ednesday, August 18, 2021 Sheet 29 of 47
5 4 3 2 1
B - 30
Schematic Diagrams
VDD3, VDD5
5 4 3 2 1
VREG5
Qpxfs! po
WEE40WEE6! QXN
R322
VREG5
470K_04
R325
EN_3V5V EN_5V
D R316 D
6 *0402_short
470K_04 D
Q13A
DD_ON_EN_VDD 2 G
Q13B 3 S MTDK3S6R
MTDK3S6R D 1
1
5 G PJ5 R330
[24,28,36] DD_ON S *CV-40mil
4 2M_1%_04
2
D
CV Test
B.Schematic Diagrams
G
[24] USB_CHARGE_EN
Q15
S
2SK3018S3
Sheet 30 of 47
D18
*RB751S-40H PR34 68K_1%_04 OCP Design 8.9A
VBUS_LDO3.3V A C
PR37 75K_1%_04
VDD3, VDD5
PR145 0_04 EN_3V VIN
[24] XLP_OUT
C D02 modify C
1
PC134
20210622 +
VREG3
*T55D107M025C0060
PJ17
2
PC24 VIN
1000p_50V_X7R_04
*CV-40mil
20
VIN PC146
2
PU9 PC151
1u_6.3V_X5R_04
1
PC30 PC177 PC176 PC29 PC178 PC31 PC166
EN2
VFB2
CS2
CS1
VFB1
EN1
+
*25TQC15MYFB
+
0.1u_25V_X7R_06
4.7u_25V_X5R_08
0.1u_25V_X7R_06
4.7u_25V_X5R_08
4.7u_25V_X5R_08
4.7u_25V_X5R_08
*T55D107M025C0060
14
2
VO1
PR142
*20mil short-p
VDD3 PQ19
PDC3908Z Ken 11/21
3
VREG3 PGOOD
7
PC168 VDD5
<FUNCTION>
PR154 0_06 9 17 PR153 0_06 0.1u_10V_X5R_04
8A VBST2 VBST1
5
5
5
5
5
5
5
5
SYS3V PC170 0.1u_10V_X5R_04
VDD3 PQ20 VDD5
PJ18 PL9 4 PR40 0_06 VDD3_DH2 10
DRVH2 DRVH1
16 VDD5_DH1 PR39 0_06 4 PDC3908Z PL8 SYS5V 8A
BCIHP0730SC-4R7M-X <FUNCTION> BCIHP0730SC-4R7M-X
3
2
1
1
2
3
2 1 2 1 2 1 PJ16 1 2 5mm
PQ17 VDD3_SW 2 8 18 VDD5_SW 1 PQ16
7.0*7.7*3mmEMC8 7.0*7.7*3mm
5
5
5
5
SW2 SW1
5
5
5
5
5mm DEFAULT SHORT
C
SHORT PC25 PC155 <FUNCTION> <FUNCTION> EMC9 PC148
R1
1000p_50V_X7R_04
+ VDD3_DL2 VDD5_DL1
PC23
PDC3906Z
4 11 GND PAD 15 4 PD14 1000p_50V_X7R_04
B R1 DRVL2 DRVL1 B
0.1u_10V_X5R_04
220u_6.3V_6.3*4.4
VREG5
C
3
2
1
1
2
3
PDC3906Z
*1000p_50V_X7R_04
VCLK
PD16 30K_1%_06
0.1u_10V_X5R_04
PR33 +
VIN
EMR2
SS1040G
13K_1%_06
A
*100p_25V_NPO_02
220u_6.3V_6.3*4.4
EMR1
21
12
13
19
SS1040G
5.1_06
A
TPS51275B-1RUKR
5.1_06
R2 R2
PR36 PR146
PR35
19.1K_1%_06 200K_04 18.7K_1%_06
6-13-18721-28B
A A
DMFWP!DP/!!ᙔ Ϻ ႝ
တ
Title
[30] VDD3 / VDD5
Size Document Number Rev
Custom 6-71-NLx0MU-D02 D02
Date: W ednesday, August 18, 2021 Sheet 30 of 47
5 4 3 2 1
VDD3, VDD5 B - 31
Schematic Diagrams
DDR4 PD7
2A
A C
1.2V/0.6VS 5V
*RB0540S2
VIN
<Function>
PC1 PC70
+
PC69
+
VDDQ(1.2V)
4.7u_25V_X5R_08
4.7u_25V_X5R_08
PU2
VTT_MEM(0.675V)
0.1u_25V_X7R_06
G5616BRZ1U
VDDQ_R
5
5
5
5
PDC3908Z
1
PJ13
2
1.5A VTT_MEM_R 20 17 VDDQ_DRVH PR4
<FUNCTION>
0_04 DRVH_R 4 PL3
VDDQ_R
13A
VDDQ_VTT VTT DRVH BCIHP0730SC-1R0M-X PJ1
1
2
3
2mm 1 2 2 1
PC59 VDDQ_L VDDQ
PC64 PR71 1 16 PQ8
VTTGND LL
5
5
5
5
*15mil_short PDC3906Z 7.0*7.7*3mm OPEN-5mm
22u_6.3V_X5R_06 *10u_6.3V_X5R_06
VTT_SNS 2 15 VDDQ_DRVL 4 PC73 PC60 DEFAULT
VTTSNS DRVL PC81 330U_2V_D2_D SHORT
C
1
2
3
0.1u_16V_X7R_04
PD1 COMMON
3 14 2200p_50V_X7R_04 20%
GND PGND 1A
OCP 16A 5V SS1040G
2V
AL POLYMER
VTT_TON VDDQ_CS PR7 3.0A@105C
B.Schematic Diagrams
A
TON CS 0.009R
SMD_7343
12 2.2_06
PC62 0.1u_6.3V_X5R_02 VTT_REF 4 PVCC5 11 VDDQ_VCC5 PR10 2.2_06
VTTREF VCC5
PC79 PC75
10 PGOOD
PGOOD 3.3V 3.3VS
1u_6.3V_X5R_02
1u_6.3V_X5R_02
Sheet 31 of 47 VDDQ_SNS 5
VDDQSNS S5
8
PR83
PR89
10K_04
PR95
*15mil_short
VDDQ, VDDQ_VTT,
VDDQSET 6 7
VDDQSET S3 *10K_04
B B
GND
PR88 0_04
VDDQ_PW RGD [10]
1.8VA
Vout
=0.75*(1+R1/R2)
21
<Function> =0.75*(1+4.99K/7.68K)
=1.237V
D
PC68
PQ5 PC71
VTT_EN# [33] 2.5V_PG
[22,36] SUSB PR76 *0_04 G *0.1u_6.3V_X5R_02
*0.22u_10V_X5R_04
2SK3018S3
S
5V
R399
ON
10K_04
R400 ON
C
1K_04
1
DDR_VTT_CTRL_R B Q21
C [3] DDR_VTT_CTRL C
MMBT3904H PJ10
C326 *CV-40mil
E
2
0.01u_16V_X7R_04
VDD3
1.5A
PC139
PC140
10u_6.3V_X5R_06
0.1u_10V_X5R_04 VDD3
1.8VA PC137
VREG5
10u_6.3V_X5R_06
10u_6.3V_X5R_06
0.1u_10V_X5R_04
R288 *10K_04 8 7 12.7K_1%_04
[10,24] SLP_SUS# PC16 GND VFB
9
GND PU11_VFB
0.1u_10V_X5R_04
Vout=0.8V*(1+Ra/Rb) PR127
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Title
Vout=0.8V*(1+1.27)=1.816V Rb [31] VDDQ,VDDQ_VTT,1.8VA
10K_1%_04
3.3VA, 1.8V
5 4 3 2 1
W/ TPM W/O TPM W/ USB CHARGER 3.1 TYPEA W/O USB CHARGER 3.1 TYPEA
B.Schematic Diagrams
R132 10_04 6-14-1003B-01B
R143 10_04 6-14-1003B-01B J_USB3_1 2UB3M04-023201F 6-21-B4M00-009
R155 10_04 6-14-1003B-01B L9 WCM2012F2S-900T04 6-19-41001-287
R156 10_04 6-14-1003B-01B C150 0.22u_10V_X5R_04 6-07-2242L-2A0
R157 10_04 6-14-1003B-01B C151 0.22u_10V_X5R_04 6-07-2242L-2A0
Sheet 32 of 47
R446 10_04 6-14-1003B-01B C488 0.33u_6.3V_X5R_04 6-07-33421-2A0
C309 1u_6.3V_X5R_02 6-07-10511-2K0 C489 0.33u_6.3V_X5R_04 6-07-33421-2A0
3.3VA, 1.8V
R389 4.7K_04 6-14-4723B-11B
U10 SLB9670VQ 6-03-09670-030
C C
R255 3.3K_1%_04 6-13-33011-28B
R274 3.3K_1%_04 6-13-33011-28B
R254 33_04 6-14-3303B-11B
R272 33_04 6-14-3303B-11B
R273 33_04 6-14-3303B-11B
U25 GD25D10BTIGR 6-04-02510-A91
R390 4.7K_04 6-14-4723B-11B
1.8V 3.3VA
⹎旸⇞
檀
㥳
㨇 ,10u c han ge to 0 4 2nd source G5016
EM5290
1A
PCBfootprint: VDD3
1.8VA 1A U27
TDFN14-2X3MM-A
G2898KD1U
C450
1A 8
9 OUT2 OUT1
13
14
1A 3.3VA
OUT2 OUT1
10 12
C415 CT2 CT1
VBIAS
R502 C437
GND
GND
EN2
EN1
*100_04 C445
0.1u_6.3V_X5R_02
100p_50V_NPO_04
100p_50V_NPO_04
3
11
15
D
Q34
*2SK3018S3
G VDD3
[36] DD_ON#
S
C434
1u_6.3V_X5R_02
*0.1u_6.3V_X5R_02
A A
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Title
[32]3.3VA,1.8V
Size Document Number Rev
A3 NLx0MU 6-71-NLx0MU-D02 D02
3.3VA, 1.8V B - 33
Schematic Diagrams
5 4 3 2 1
VCCST
60mA+150mA(VCCPLL) = 210mA VCCST VCCST
V1P05_OUT_FET
PU6
C393
D 2 4 VCCST D
VIN VOUT
1u_6.3V_X6S_04
C408 C405 C388
*10u_6.3V_X5R_06 1u_6.3V_X5R_02
0.1u_6.3V_X5R_02
R458 VDD3
*33_04
VDD3 R457
B.Schematic Diagrams
Q29B *100K_04
3
R506 0_04 D *MTDK3S6R
[10,24] SLP_S0#
5
U24
R494 *0_04 1 PJ15 OPEN-1mm G5
[10,33] 3.3_VCCST_OVERRIDE VCCST_EN 1.05V_VCCST_EN
4 1 2 6 5 S
4
2 ON VBIAS Q29A
[10,17,23,28,36] SUSB#
6
DEFAULT C392 C399 D *MTDK3S6R
SHORT *0.1u_10V_X5R_04
3
74LVC1G32
Sheet 33 of 47
0.1u_6.3V_X5R_02 G2 1.05V_VCCST_EN
S
1
2.5V, VCCST, 3.3V
1A
2.5V_LDO R456 *0_04 VDD3
VCCSTG
R455 0_04 3.3VA
5V
PC149 PC152 PR130 PC156 1 3
C 10u_6.3V_X5R_06 0.1u_10V_X5R_04 GND NC C
*47K_04 PU8 1u_6.3V_X5R_04 2.5V
G9661MF11U FA7609A6
3 4
[31] 2.5V_PG
2.5V_PG 1
VIN VCNTL
6
1A
DEFAULT POK VOUT
SHORT 5
PJ7 1 2 1mm 2.5V_EN 2 NC PR133 PC144 PC153 PC154
[10] SUSC# EN
Ra
82p_50V_NPO_04
22u_6.3V_X5R_06
0.1u_10V_X5R_04
8 7 21.5K_1%_04
PR38 9 GND VFB
PJ6 1 2 *CV-40mil GND VFB
VDD3
PC145
100K_04
For CV test 0.1u_10V_X5R_04
Rb
PR132
10K_1%_04
VCCSTG
V1P05_OUT_FET VCCSTG VCCSTG
PU5
EN LP# OUTPUT PG 20mA C387
Vout = 0.8V ( 1 + Ra / Rb ) 2 4 VCCSTG
VIN VOUT
1u_6.3V_X6S_04
0 0 0 V, Off LOW C407 C406 C386
*10u_6.3V_X5R_06 1u_6.3V_X5R_02 0.1u_6.3V_X5R_02
6
PG + 1 ms and remains high SLP_S0# R505 *0_04 D *MTDK3S6R
5
during LP# = 0 U26
R493 0_04 1 G2
[10,33] 3.3_VCCST_OVERRIDE VCCSTG_EN 1.05V_VCCSTG_EN 6
1 1 HIGH Remains asserted 4 R462 120_04 5 S
1
2 ON VBIAS Q30B
after SS [10,24] CPU_C10_GATE#
3
C391 C396 D *MTDK3S6R
3
74LVC1G32 0.1u_6.3V_X5R_02 G5 1.05V_VCCSTG_EN
0.1u_6.3V_X5R_02
S
4
Modern Standby
R466 *0_04 VDD3
R467 0_04 3.3VA
1 3
GND NC
FA7609A6
A A
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Title
[33]2.5V/VCCST/VCCSTG
Size Document Number Rev
A3 NLx0MU 6-71-NLx0MU-D02 D02
Power PD Function
5 4 3 2 1
W/O_TYPE_C+DP
PRS2
0.01_1%_32
D W /O_TYPE_C+DP D
VA1
JDC_AC
J_DC_JACK1
1
3.5A PD10 A C SK54B
2
PC97 W /_TYPE_C+DP
GND1
GND2 PCB Footprint = do-214aa
2DC3206-001111F
P/N = 6-20-B3210-003
PC94 PC90 0.1u_25V_X7R_06
PR124
100K_1%_06 W/_TYPE_C+DP D02A Change footprint
B.Schematic Diagrams
W /_TYPE_C+DP
10u_25V_X5R_08
*10u_25V_X5R_08
TYPE-C_VBUS
PQ10
Sheet 34 of 47
PD11 MTD13P03H8
3.5A A
SK54B
C
W /_TYPE_C+DP 8
3
2
7
6
Power PD Function
W /_TYPE_C+DP 1 5
EMC7 PR143 PCB Footprint = do-214aa
TYPEC-IN 100K_1%_06
PR137 PC147
4
0.1u_25V_X7R_06
W/_TYPE_C+DP
W /_TYPE_C+DP *0.1u_25V_X7R_06
C
200K_04 C
W /_TYPE_C+DP W /_TYPE_C+DP
PR148
100K_04
W /_TYPE_C+DP
D
PQ13
G 2SK3018S3
W /_TYPE_C+DP
S
PD13
C A PR140 20K_04 G PQ11
PR134
2SK3018S3
W /_TYPE_C+DP
S
MM3Z15V W /_TYPE_C+DP
*100K_04
W /_TYPE_C+DP PR141
W /_TYPE_C+DP
100K_04
W /_TYPE_C+DP
B B
W /_TYPE_C+DP=6-13-30031-28C, W /O=6-14-1043B-11B
resolve DC mode 㛒
攳
㨇 㗪,
䃉
P
D 㱽⃭暣 i
sue
For Dead Battery
VBUS_LDO3.3V
TYPE-C_VBUS
U13
1 5
VIN VOUT
D02 modify
2
C480 GND R351
R341 0_04
10u_6.3V_X5R_06 3 4 3.48K_1%_04
W /_TYPE_C+DP EN ADJ W /_TYPE_C+DP
A W /_TYPE_C+DP A
AP2204K-ADJTRG1
W /_TYPE_C+DP
R342
2K_04
W /_TYPE_C+DP
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Title
[34] PWR_PD FUNCTION
Size Document Number Rev
A3 NLx0MU D02
6-71-NLx0MU-D02
Date: W ednesday, August 18, 2021 Sheet 34 of 47
5 4 3 2 1
Power PD Function B - 35
Schematic Diagrams
NCP81269
5 4 3 2 1
D D
VIN
Co-lay
B.Schematic Diagrams
0.01u_50V_X7R_04
1u_25V_X7R_06
10u_25V_X6S_08
10u_25V_X6S_08
*25TQC15MYFB
+
VCCIN_AUX_VID0
[11] VCCIN_AUX_VID0
AOZ2264VQI_BST_1
PU4
VCCIN_AUX_VID1
AOZ2264VQI_BST
1 7
[11] VCCIN_AUX_VID1 VID0 IN#1 22
IN#2 9
Sheet 35 of 47
PR113 PR116 IN#3 24
23 IN#4 8
*100K_04 *100K_04 VID1 IN#5 4 AOZ2264VQI_VFB
VOUT PR111 PC121
2.2_06 0.1u_25V_X7R_06
20 PR117 PR121
NCP81269
BST
*10K_1%_04 *100K_1%_04
*PSLB30E227M
PC127
2R0AVEC331M0545E09
LX#3 18 PR110
LX#4 + +
4.7u_6.3V_X6S_06 2 11
AGND LX#5 25 *2.2_06
LX#6
6
PGOOD PC117
*1000p_50V_X7R_04
PR123 0_04
AUX_VSS_SENSE [11]
VCCIN_AUX
B B
0.1u_25V_X7R_06
0.1u_25V_X7R_06
22u_6.3V_X6S_08
22u_6.3V_X6S_08
22u_6.3V_X6S_08
22u_6.3V_X6S_08
22u_6.3V_X6S_08
22u_6.3V_X6S_08
A A
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Title
[35] NCP81269
Size Document Number Rev
A2 NLx0MU 6-71-NLx0MU-D02 D02
Date: Wednesday, August 18, 2021 Sheet 35 of 47
5 4 3 2 1
B - 36 NCP81269
Schematic Diagrams
R291
R266
100K_04
10K_04
SUSB
DD_ON# SUSB [22,31]
Q12
D
DD_ON# [32]
D Q11 2SK3018S3 D
D
1
2SK3018S3
G J1 C245
[10,17,23,28,33] SUSB#
G DEL J9 C218
[24,28,30] DD_ON
S
*CV-40mil *30p_25V_NPO_02
2
S
ON ON
ON ON VIN C258 1000p_50V_X7R_04
B.Schematic Diagrams
VIN C479 *1000p_50V_X7R_04
Sheet 36 of 47
VREG3
0901 5V, 5VS 婧
⮵2nd source
EM5290
G5016
Qpxfs! po
VDD5 VDD5
C233 U10 G2898KD1U
PCBfootprint:
TDFN14-2X3MM-A
C232
R250
*100_04 5V WEE40WEE6! QXN
5VS R245 *100_04 0.1u_6.3V_X5R_02 1 6 0.1u_6.3V_X5R_02 Q35 VREG3
R62
47K_04 3.3V, 5V, 3VS, 5VS,
D
Q31 2 IN1 IN2 7
D
IN1 IN2
CTL
C *2SK3018S3 C
*2SK3018S3
SUSB G
5VS 6A 13
14 OUT1 OUT2
8
9
6A 5V G DD_ON#
R72
PW R_SW #
PW R_SW # [24]
S
C215 OUT1 OUT2 C228 VREG3 3
S
C216 M_BTN 5 G
GND
GND
EN1
EN2
C217 R64 S MTDK3S6R
470p_50V_X7R_04 220p_50V_NPO_04 47K_04 6 4
VDD3_R J3 *CV-40mil VDD3_R
VDD3 R314 10K_04 1 2 2 1 D R69
3
5
15
11
J5 *CV-40mil Q4A
JUMP-1MM JUMP-1MM R65 1K_04 2 G 1M_04
[29] M_BTN#
R298 0905 change footprint S MTDK3S6R
2
C252 10K_04 1
SUSB# 1 2 SUSB#_EN R297 10K_04 5VS_EN1 5V_EN2 DD_ON_EN 2 1 DD_ON
VDD5
ED1
J2 1u_6.3V_X5R_02 C253 J4 *V15AVLC0402
OPEN-1mm OPEN-1mm
SHORT SHORT
C251 *0.1u_6.3V_X5R_02
1
ON *0.1u_6.3V_X5R_02
DD_ON_EN [32]
B B
3.3V
3.3V 6A 13
14
IN1
OUT1
IN2
OUT2
8
9
6A 3.3VS 3.3VS
OUT1 OUT2 C465
C481 3.3V_CT2 12 10 3.3VS_CT1
0.1u_6.3V_X5R_02 CT1 CT2 0.1u_6.3V_X5R_02 R332
VBIAS
R244
GND
GND
EN1
EN2
11
3
Q33 SUSB G
R561
S
C470 ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
*0.1u_6.3V_X5R_02 Title
[36] 3.3V,5V,3VS,5VS,CTL
Size Document Number Rev
A3 NLx0MU 6-71-NLx0MU-D02 D02
Charger, AC IN
5 4 3 2 1
A
W/_TYPE_C+DP
PD6 PD5 PD4
1N914BWS 1N914BWS 1N914BWS
W/_TYPE_C+DP
C
26786_VAC_R
D 3.5A D
VA1 PQ2
PQ1 VIN
L4
AC Detect 17.2V MDU1517
ULTRASO-8 VA PDC3906Z PRS1
HCB2012KF-800T80 WMCSL0612R020FETA PQ14
D S 5 5 PDC3906Z
PR31
3 5 5 3
PC158
PR45
PR30
2 5 PC157 PC28 PC27 PC159 PC173 PC174 PC175 5 2
PC22
1500p_50V_04
0.1u_25V_X7R_06
1000p_50V_X7R_04
4.7u_25V_X7R_08
4.7u_25V_X7R_08
4.7u_25V_X7R_08
4.7u_25V_X7R_08
PC17 PC20 PC21 1 5 5 1
C
PR126 PR125 PC15 close to Rsense
G
0.1u_25V_X7R_06
0.1u_25V_X7R_06
10u_25V_X5R_08
PC143 PC19 PC18
0.1u_25V_X5R_04
PD12 PC160
4.7_06 4.7_06
4
*0.1u_25V_X7R_06
*10mil_short
10u_25V_X5R_08
0.1u_25V_X7R_06
0.1u_25V_X7R_06
750K_1%_04
*0.01u_50V_X7R_04
*10mil_short
SMAJ20A PR150
26786_PB
*2200p_50V_X7R_04
A
PR32
0_04
PC142
B.Schematic Diagrams
26786_PA
4.02K_1%_04
2.2u_25V_X5R_08 PC49 *0.1u_25V_X7R_06
PR46
PC40
PC52 *0.1u_25V_X7R_06
PC51
Power 8/4
26786_ADDIV
165K_1%_04
0.22u_25V_X7R_06
close to IC
*0.1u_25V_X7R_06
PC36 0.47uF_25V_X5R_04
26786_IACM
26786_IACP
26786_VAC
26786_PB
PR49 0_04 26786_PSYS
[38] PSYS
Sheet 37 of 47
26786_VAC_R PR43 3.3_06
PC41
22
24
13
14
15
100p_50V_NPO_04
1
Charger, AC IN
PR50 0_04 26786_BATTON# PQ15
ADDIV
PA
PB
IACP
VAC
VAD
IACM
C PR56 10K_1%_04 11 12 PDC3908Z J_BAT1 C
VDD3 BATTON# VSYS
5
5
5
5
<FUNCTION> PC163 50458-00801-002
PR55 100K_1%_0426786_CEN 28 0.01u_25V_X7R_04 PCB Footprint = 50458-008L
CEN 17 26786_HDR 4 PL7 PRS3 P/N = 6-21-63900-108
connect to IMVP PSYS function 26786_PSYS 25 HDR PC26 1000p_50V_X7R_04 BCIHP0730SC-4R7M-X WMCSL0612R020FETA
5A
1
2
3
PSYS 16 26786_LX 2 1 V_BAT 1
26786_Prochot# LX 2
PC161
PC162
PR152
PC164
PC165
PR151
PR51 10k_04 10 PQ18
PC167
VDD3 Prochot# PL2 3
5
5
5
5
PR47 *100K_1%_04 26786LN 18 26786_BSTPR42 3.3_06 PC32 0.47uF_25V_X5R_04 PDC3906Z SMC_BAT HCB1005KF-121T20
VDD3 BST SMD_BAT 4
<FUNCTION> HCB1005KF-121T20
PC38 1000p_25V_X7R_0226786_ACAV 23 20 26786_LDR 4 PR41 PL1 5
ACAV LDR 6
10u_25V_X5R_08
10u_25V_X5R_08
*10u_25V_X5R_08
*10u_25V_X5R_08
0.1u_25V_X5R_04
PU1 *2.2_06
1
2
3
300_1%_04 26786_IAD 47p_50V_NPO_04 26786_IBATT 26786_VDDP 7
*10mil_short
*10mil_short
PR60 PC47 3 21 A
PD15 C 1N914BWS PC179
[24] TOTAL_CUR IBATT VDDP [24] BAT_DET 8
PC39
PC37
PC34
1000p_50V_X7R_04
PC14 PC48 47p_50V_NPO_04 26786_IAD 4 26 PC33 PC35
C
IAD ICHP 4.7u_25V_X5R_06 *2200p_50V_X7R_04
COMP
GNDA
GNDP
CNFB
PD3 PD2
SDA
SCL
CNI
2200p_50V_X7R_04
47p_25V_NPO_02
47p_25V_NPO_02
47p_25V_NPO_02
27
ICHM
SS14WS
SS14WS
SMC_BAT [24]
29
19
A
CLOSE TO EC 26786_ICHP
SMD_BAT [24]
26786_SDA
26786_SCL
PC43
PR44 26786_ICHM
*0.1u_25V_X7R_06
PR57
PR58
26786_COMP
26786_CNFB
26786_CNI
PR59
PR52
0_04 PC44
*0.1u_25V_X7R_06 PC42
*0.1u_25V_X7R_06
15K_1%_04 PC50
499_1%_04 PC45
100_1%_04
100_1%_04
PC46
PR54
33p_25V_NPO_02
60.4K_1%_04
SMC_BAT
SMD_BAT
B B
1200p_50V_X7R_04
82p_50V_NPO_04
PR129 *0_04 26786_ACAV
VREG3
PR144
47K_04
㍉
岤 7 / 29 PQ3 PR61
MTE1K0P15KN3 300K_1%_04
AC_IN# [13,24]
C
G
100K_04
PC53
㍉
岤 7 / 29 PR63
VIN 0.1u_10V_X5R_04
60.4K_1%_04
BATGS
PR138
D
10K_04
A G PQ4 A
EMC4 EMC5 EMC1 EMC6 VDD3
2SK3018S3
S
0.1u_25V_X7R_06 0.1u_25V_X7R_06 0.1u_25V_X7R_06 0.1u_25V_X7R_06
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Title
[37] CHARGER,AC IN
Size Document Number Rev
Custom NLx0MU 6-71-NLx0MU-D02 D02
B - 38 Charger, AC IN
Schematic Diagrams
VCCIN
5 4 3 2 1
T55D107M025C0060
*T55D107M025C0060
*T55D107M025C0060
*75_04 *100_04 100_04
45.3_1%_04
PR90 *100_04
H_PROCHOT# [13]
D PR93 PR86 0_04 D
H_CPU_SVIDCLK [11]
1K_1%_04 PR81 0_04
H_CPU_SVIDALRT# [11]
PR79 0_04
H_CPU_SVIDDAT [11]
PR1 2_06 5V
[10] H_VR_READY
Place close to
CPU pins Place close to U8514 VIN VIN VIN
VCC_IN PR107 *100_04 Adjust PsysPmax to 49.5W problem PC67
20210818 1u_16V_X7R_06 VIN
PSYS MAX 45W EMC2 EMC3 Co-lay
0.01u_50V_X7R_04
0.01u_50V_X7R_04
PR101 0_04 PR16 PU4_VRMP PR73 1K_04 PC104 PC105 PC107 PC109 PC108
[11] VCC_SENSE
40.2K_1%_04 PC101
10u_25V_X6S_08
10u_25V_X6S_08
1u_25V_X7R_06
PR13
B.Schematic Diagrams
*25TQC15MYFB
+
0.01u_50V_X7R_04
*0.1u_16V_X7R_04
118K_1%_04 PC63
PC85 PSYS [37] Fsw~ 500KHZ 0.01u_50V_X7R_04
1000p_50V_X7R_04 PC86 2200p_50V_X7R_04
4
3
10
PR21 *1K_1%_04 5V
D1
PR102 0_04 VSN PR96 1K_1%_04 PW M2 T24
[11] VSS_SENSE
PQ9
Sheet 38 of 47
41
40
39
38
37
36
35
34
33
32
31
PR106 *100_04 PR104 0_04 1 G1 AOE6932
Closed to NMOS
VR_HOT#
ALERT#
PWM2
SDIO
PAD
EN
VR_RDY
SCLK
ROSC
VCC
VRMP
PC55 SW 5 PL5
PU4_SW 3
VCCIN
PR68 2.2_06 0.22u_16V_X7R_06 2 S1 6 2 1
D02 modify 7
PC95
CMME063T-R24MS1R197
PR109
VCC_IN
36A
C PC88 47p_50V_NPO_04 PR99 PC92 470p_50V_X7R_04 20210624 PWR 1 30 PU4_BST3 *20mil short-p C
303_VSP PSYS BST3 PU4_HG3
1000p_50V_X7R_04
49.9_1%_04 PR103 30K_1%_04 2 PU3 29 CSN3
303_VSN 3 VSP HG3 28 PU4_SW 3
PR100 PC87 470p_50V_X7R_04 4 VSN NCP81303MNTXG SW3 27 PU4_LG3 PR105 0_04 8 G2 2020/6/19 OSCAR
PC91 4.3K_1%_04 PR97 910_04 DIFFOUT 5 IOUT LG3 26 PR98 PR108
DIFFOUT PGND
2.2_04
2200p_50V_X7R_04 FB 6 25 PR69 1_06 5V
S2 *20mil short-p
COMP 7 FB PVCC 24 PU4_LG1 SW N3
9
PR17 17.8K_1%_04 PU4_ILIM 8 COMP LG1 23 PU4_SW 1 PC56
D02 modify ILIM SW1
20210624 PWR NILIM PR25 220K_1%_04 CSCOMP 9 22 PU4_HG1 4.7u_6.3V_X6S_06
PR19 CSSUM 10 CSCOMP HG1 21 VIN
Place close to CSSUM BST1
phase 1 Inductor 160K_1%_04 PR20 75K_1%_04
VBOOT/SR
Co-lay
TSENSE
ICCMAX
SW N1 PR8 120K_1%_06 PC8 220p_50V_NPO_04 CSREF PC57 0.22u_16V_X7R_06
DRON
CSP3
CSP2
CSP1
PR70 2.2_06 PC2 PC4 PC65 PC58
GND
ADD
PC7 820p_50V_X7R_04 PC61 PC3
1u_25V_X7R_06
10u_25V_X6S_08
10u_25V_X6S_08
+
0.01u_50V_X7R_04
*25TQC15MYFB
*0.1u_16V_X7R_04
SW N3 PR24 120K_1%_06
11
12
13
14
15
16
17
18
19
20
CSREF
4
3
303_CSP3 PU4_ICCMAX
10
SW N3 PR18 10K_1%_04
PU4_ADD D1
5V
PC82 PU4_VBOOT PQ7
AOE6932
*100K_1%_04
0.01u_50V_X7R_04
PR64
PR3
PR94 CV TEST 1.8V PR87 0_04 1 G1
2
2
PC80
Closed to NMOS
DEFAULT SHORT
B 303_CSP2 B
10K_1%_04
51K_1%_04
PR65
PR82
1000p_50V_X7R_04
*20mil short-p
SW N1 PR85 10K_1%_04 303_CSP1 CSN1
TSENSE
PR11 0_04 8 G2 PR67 2020/6/19 OSCAR
*100K_1%_04
118K_1%_04
PR66
2.2_04
PR84 PR75
PC76 PR77 S2 *20mil short-p
0.022u_25V_X7R_04 0_04 SW N1
9
PC72
CSREF
26.1K_1%_04
0.1u_16V_X7R_04
PNTC1
1
VCC_IN
*EWTF02-103F3I-N
PR78
53.6K_1%_04 22uF_0603_X5R_4V
2
DRON PC114 PC93 PC99 PC111 PC112 PC100 PC115 PC116 PC103 PC102 PC10 PC9 PC110 PC98
T25
VCC_IN
0.1u_25V_X7R_06
0.1u_25V_X7R_06
0.1u_25V_X7R_06
0.1u_25V_X7R_06
22u_6.3V_X6S_08
22u_6.3V_X6S_08
22u_6.3V_X6S_08
22u_6.3V_X5R_06
22u_6.3V_X5R_06
22u_6.3V_X5R_06
*22u_6.3V_X5R_06
22u_6.3V_X5R_06
22u_6.3V_X5R_06
*22u_6.3V_X5R_06
PC96 PC89 PC83 PC106
PR92 10_04 CSN1
*PSLB30E227M
PSLB30E227M
2R0AVEC331M0545E09
2R0AVEC331M0545E09
+ + + +
A Place close to A
phase 1 MOSFET
ICCMAX 55A// DCLL 2m ohm /OCP:72A
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Title
[38] VCCIN
Size Document Number Rev
A3 NLx0MU 6-71-NLx0MU-D02 D02
VCCIN B - 39
Schematic Diagrams
RTL8411B
5 4 3 2 1
U_VDD3
The 10Kohm pull-up resistor of CLK_REQ_N is required
to either 3.3V Suspend (5, 6, 7) or Core (2) rail,
depending on the power well of PCH's input PCIECLKRQx#
CLK_PCIE_C_GLAN buffer. See Platform Design Guide for more details
LAN_BD_FOR_14" YR3 0_02 ZR20
[42] Y_CLK_PCIE_GLAN CLK_PCIE_C_GLAN#
LAN_BD_FOR_14" YR4 0_02 10K_04
[42] Y_CLK_PCIE_GLAN# PCIE_RXP7_C_GLAN
LAN_BD_FOR_14" YUC5 0.1u_6.3V_X5R_02
[42] Y_PCIE_RXP7_GLAN PCIE_RXN7_C_GLAN
LAN_BD_FOR_14" YUC6 0.1u_6.3V_X5R_02
[42] Y_PCIE_RXN7_GLAN PCIE_TXP7_C_GLAN
LAN_BD_FOR_14" YUC7 0.1u_6.3V_X5R_02 ZZ1
[42] Y_PCIE_TXP7_GLAN PCIE_TXN7_C_GLAN
LAN_BD_FOR_14" YUC8 0.1u_6.3V_X5R_02
[42] Y_PCIE_TXN7_GLAN Z_LAN_MDIP0
48 13
[42] Z_GLAN_CLKREQ# CLK_REQ_N MDI_PLUS0 Z_LAN_MDIN0 Z_LAN_MDIP0 [41]
36 14
[40,42] Z_BUF_PLT_RST# PE_RST_N MDI_MINUS0 Z_LAN_MDIN0 [41]
ZR22 0_02 LAN_BD_FOR_15" CLK_PCIE_C_GLAN 44 17 Z_LAN_MDIP1
[42] Z_CLK_PCIE_GLAN CLK_PCIE_C_GLAN# PE_CLKP MDI_PLUS1 Z_LAN_MDIN1 Z_LAN_MDIP1 [41]
ZR23 0_02 LAN_BD_FOR_15" 45 18
[42] Z_CLK_PCIE_GLAN# PE_CLKN MDI_MINUS1 Z_LAN_MDIN1 [41]
B.Schematic Diagrams
PCIE
MDI
SMBUS PULL-UP OPTIONS ZC13 0.1u_6.3V_X5R_02 LAN_BD_FOR_15" PCIE_RXP7_C_GLAN 38 20 Z_LAN_MDIP2
[42] Z_PCIE_RXP7_GLAN PCIE_RXN7_C_GLAN PETp MDI_PLUS2 Z_LAN_MDIN2 Z_LAN_MDIP2 [41]
SMBUS SPEED ZC14 0.1u_6.3V_X5R_02 LAN_BD_FOR_15" 39 21
1MHz(Defaul setting) 499ohm [42] Z_PCIE_RXN7_GLAN PETn MDI_MINUS2 Z_LAN_MDIN2 [41]
100KHz/400KHz 2.2Kohm ZC15 0.1u_6.3V_X5R_02 LAN_BD_FOR_15" PCIE_TXP7_C_GLAN 41 23 Z_LAN_MDIP3 3.3V_LAN
[42] Z_PCIE_TXP7_GLAN PCIE_TXN7_C_GLAN PERp MDI_PLUS3 Z_LAN_MDIN3 Z_LAN_MDIP3 [41]
ZC16 0.1u_6.3V_X5R_02 LAN_BD_FOR_15" 42 24
[42] Z_PCIE_TXN7_GLAN PERn MDI_MINUS3 Z_LAN_MDIN3 [41]
ZR12 *499_1%_04
U_VDD3 ZR9 *499_1%_04 SVR_EN_N ZR14 0_04
28 6 ZR15 *4.7K_04 ZC8 ZC9
NOTE: Default SMBus [42] Z_SML0_CLK SMB_CLK SVR_EN_N
SMBUS
Address is 0xC8 31
Sheet 39 of 47
[42] Z_SML0_DATA SMB_DATA
0.1u_6.3V_X5R_02
0.1u_6.3V_X5R_02
C ZR26 4.7K_04 1 ZR21 4.7K_04 3.3V_LAN C
U_VDD3 RSVD_VCC3P3
ZR25 0_04 LAN_WAKE_N 2
[42] Z_LAN_WAKEUP#_R LANWAKE_N
NOTE: LANWAKE_N must be ZR18 *10K_04 LAN_DISABLE_N 3 5 ZC10 1u_6.3V_X5R_02
LAN I219-LM
connected to PCH's GPIO27. 3.3V_LAN LAN_DISABLE_N VDD3P3_5
ZR19 0_04 4
ZR16 *10K_04 VDD3P3_4 15
26 VDD3P3_15 19
[42] Z_LAN_DISABLE# LED0 VDD3P3_19
27 29
25 LED1 VDD3P3_29
LED
NOTE: LAN_DISABLE_N must be connected
to PCH's GPIO12/LAN_PHY_PWR_CTRL. ZR17 *10K_04 LED2
This GPIO12 pin must be set as 3.3V_LAN ZR13 *10K_04 8 0.9V_LAN_M
"LAN_PHY_PC" function through FITC VDD0P9_8
tool. 11
DESIGN NOTE: PCH's LANPHYPC output ZT1 LAN_JTAG_TDI 32 VDD0P9_11 16 LAYOUT NOTE: Place L, C*3 and R close to PHY
does not require pull-up. Resistors are no-stuff (for testing ZT2 LAN_JTAG_TDO 34 JTAG_TDI VDD0P9_16 NOTE: Total requirement Cout>=20uF. ESR<50mohm.
purpose only). LAN_JTAG_TMS JTAG_TDO
JTAG
ZT3 33 22
ZT4 LAN_JTAG_TCK 35 JTAG_TMS VDD0P9_22
JTAG_TCK 37
Crystal 䓐 503 2 SI Z
㓡 E VDD0P9_37 Keep
ZR11 0_04 LAN_XTAL_OUT 9 40 short
LAN_XTAL_IN 10 XTAL_OUT VDD0P9_40 43
and wide
XTAL_IN VDD0P9_43 46 modify,0510 max
VDD0P9_46 47
ZX1 LAN_TEST_EN VDD0P9_47
30
TEST_EN ZL6
DESIGN NOTE: C7 & C8 value may vary depending on the 1 2 RES_BIAS 12 7 CTRL_0P9
actual Cstray of the board. Cstray is varied because RBIAS CTRL_0P9
.
specific board stack-up, layout, etc. For examples: 4 3
10p_50V_NPO_04
10p_50V_NPO_04
Using Cload=18pF Crystal part, if Cstray=7pF then 49 SWF2520CF-4R7M-M ZC2 ZC4 ZC5
ZC12 ZC11 GND_EPAD
C7=C8=22pF and if Cstray=6pF then C7=C8=24pF.
B 19001-X-016-3 B
0.1u_6.3V_X5R_02
*10u_6.3V_X5R_06
22u_6.3V_X5R_06
Cload=[(C7*C8)/(C7+C8)] + Cstray. ZR10 ZR7 I219V MP
Each design should measure the crystal’ s ppm to make
sure it is within the I217 Specification. 1K_04 3.01K_1%_04
暣⭡ῤ BY⮎ 㷔
B - 40 RTL8411B
Schematic Diagrams
5 4 3 2 1
U_VDD3 U_3V3AUX
U_3V3AUX
ZUR10 *0201_short U_SD_W P# ZUR12 *0_04 LAN_BD 40 mil
ZGND U_VDD3
ZUR9 U_CR1_LEDN ZUR8 LAN_BD
10K_04
10K_04 ZUR14 0_04 LAN_BD 40 mil
LAN_BD U_SD_CD#
U_MS_INS#
U_3.3VS
NEW Part
ZUT1
⤪
ᶵ supp o r t R T D3⎗
ᶵ㍍ ZUC7 ZUC5
ZR8 *0_04 LAN_BD LAN_BD ZUJ_SD1
[42] Z_SDCARD_W AKE#
10u_6.3V_X5R_06 0.1u_6.3V_X5R_02
B.Schematic Diagrams
LAN_BD U_SD_D0 7
U_SD_D1 8 DATA0
32
31
30
29
28
27
26
25
ZUU1 ZGND U_SD_D2 1 DATA1
ZGND U_SD_D3 2 DATA2
WAKE#
MS_INS#
SD_CD#
SP7
3V3aux
GPIO
NC
NC
CD/DATA3
U_VCC_CARD 4
U_SD_CLK 5 VDD
U_SD_CMD CLK
Sheet 40 of 47
LAN_BD 3
1 24 ZUC9 1u_6.3V_X5R_02 ZUC3 ZUC1 U_SD_CD# 10 CMD
[39,42] Z_BUF_PLT_RST# PERST# NC ZGND CD#
2 23 LAN_BD 9 GND1
*10u_6.3V_X5R_06
[42] Z_CARD_CLKREQ# U_RTS5227_HSIP CLKREQ# NC COMMON GND
0.1u_6.3V_X5R_02
LAN_BD_FOR_15" ZUC6 0.1u_6.3V_X5R_02 3 22 6 GND2
[42] Z_PCIE_TXP6_CARD U_RTS5227_HSIN HSIP RTS5227S NC U_SP6 ZUR1 LAN_BD U_SD_D2 VSS GND
Multi Board
LAN_BD_FOR_15" ZUC8 0.1u_6.3V_X5R_02 4 21 33_04 ZUC10 *5P_50V_NPO_04
[42] Z_PCIE_TXN6_CARD U_RTS5227_CLKP HSIN SP6 U_SP5 ZUR2 LAN_BD U_SD_D3 ZGND
LAN_BD_FOR_15" ZR5 0_02 5 20 33_04
[42] Z_CLK_PCIE_CARD
LAN_BD_FOR_15" ZR6 0_02 U_RTS5227_CLKN 6 REFCLKP QFN32 SP5 19 U_SP4 ZUR3 LAN_BD 33_04 U_SD_CMD W Q21823-DES1-7F
[42] Z_CLK_PCIE_CARD# U_RTS5227_HSOP REFCLKN SP4 U_DV33_18 ZUC12 1u_6.3V_X5R_04
LAN_BD_FOR_15" ZUC11 0.1u_6.3V_X5R_02 7 18 20 mil
ZGND PCB Footprint = wq2182x-des1-7x
[42] Z_PCIE_RXP6_CARD HSOP DV33_18
RTS5227S / OZ711
LAN_BD_FOR_15" ZUC14 0.1u_6.3V_X5R_02 U_RTS5227_HSON 8 17 LAN_BD ZGND P/N = 6-21-K4Y10-008
[42] Z_PCIE_RXN6_CARD HSON SP3 U_SP3 U_SD_CLK
C ZUR4 LAN_BD 33_04 ZGND ZGND LAN_BD ZGND C
CARD_3V3
LAN_BD_FOR_14" YUC1 0.1u_6.3V_X5R_02 U_RTS5227_HSIP ZUC13 LAN_BD
3V3_IN
DV12S
[42] Y_PCIE_TXP6_CARD U_RTS5227_HSIN
RREF
LAN_BD_FOR_14" YUC2 0.1u_6.3V_X5R_02 33
AV12
[42] Y_PCIE_TXN6_CARD
SP1
SP2
U_RTS5227_CLKP GND
NC
LAN_BD_FOR_14" YR1 0_02 5/21 update PCB Footprint *0.1u_6.3V_X5R_02
[42] Y_CLK_PCIE_CARD U_RTS5227_CLKN
LAN_BD_FOR_14" YR2 0_02
[42] Y_CLK_PCIE_CARD# U_RTS5227_HSOP
LAN_BD_FOR_14" YUC3 0.1u_6.3V_X5R_02 OZ711LV2 0618 VALUE UPDATE
[42] Y_PCIE_RXP6_CARD
10
11
12
13
14
15
16
LAN_BD_FOR_14" YUC4 0.1u_6.3V_X5R_02 U_RTS5227_HSON ZGND 9 LAN_BD ZGND
[42] Y_PCIE_RXN6_CARD
U_SP2 ZUR5 LAN_BD 33_04 U_SD_D0 100ohm +/- 15% U_VCC_CARD
U_SP1 ZUR6 LAN_BD 33_04 U_SD_D1
ZUR7 6.2K_1%_04 12 mil U_CR_RREF
ZGND
LAN_BD
20 mil
U_DV12_S
L<200mils
U_AV12 ZUC2 ZUC4
ZUC20 ZUC17
LAN_BD LAN_BD
LAN_BD LAN_BD
20 mil 0.1u_6.3V_X5R_02 22u_6.3V_X5R_06
U_DV12_S ZUR16 0_04 4.7u_6.3V_X5R_04 0.1u_6.3V_X5R_02
LAN_BD
ZUC19 ZUC15
LAN_BD LAN_BD ZGND ZGND
60 mil *4.7u_6.3V_X5R_04 0.1u_6.3V_X5R_02 ZGND
U_VDD3 ZUR13 *0_06 U_CARD_3V3 Near Cardreader CONN
60 mil LAN_BD
ZUR15 0_06 ZGND 60 milZGND 1.2A U_CARD_3V3 ZUR11 0.2R_5%_06 40 mil Near Cardreader CONN
U_3.3VS U_VCC_CARD
LAN_BD LAN_BD
ZUC16 ZUC21 ZUC18
LAN_BD LAN_BD LAN_BD
0.1u_6.3V_X5R_02 10u_6.3V_X5R_06 0.1u_6.3V_X5R_02
B B
NEAR PIN11 SD Card Remove Fall time less than 1 ms
ZGND ZGND ZGND
when SD card remove.
GPIO_SDCARD_PWR_RTD3
3.3V_AUX
GPIO_SDCARD_PLT_RST#
A A
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Title
[40] Multi board RTS5227S/OZ711
Size Document Number Rev
A3 6-71-NLx0MU-D02 D02
LAN Transformer
5 4 3 2 1
D D
LMX1+ 1 ZL1 2
Sheet 41 of 47 LMX1- 4 3
*WCM2012F2S-161T03-short
1 ZL2 ZJ_RJ45_1
LAN Transformer
ZL5 LMX2+ 2
C 11 14 LMX4+ DLMX1+ 1 GND1 C
[39] Z_LAN_MDIP3 TD4+ MX4+ DA+ shield
12 13 LMX4- LMX2- 4 3 DLMX1- 2 GND2
[39] Z_LAN_MDIN3 TD4- MX4- DA- shield
8 17 LMX3+ *WCM2012F2S-161T03-short DLMX2+ 3 GND3
[39] Z_LAN_MDIP2 TD3+ MX3+ DB+ shield
9 16 LMX3- DLMX2- 6 GND4
[39] Z_LAN_MDIN2 TD3- MX3- DB- shield
LMX3+ 1 ZL3 2
5 20 LMX2+ DLMX3+ 4
[39] Z_LAN_MDIP1 TD2+ MX2+ DC+
6 19 LMX2- LMX3- 4 3 DLMX3- 5 ZGND
[39] Z_LAN_MDIN1 TD2- MX2- DC-
2 23 LMX1+ *WCM2012F2S-161T03-short DLMX4+ 7
[39] Z_LAN_MDIP0 TD1+ MX1+ DD+
3 22 LMX1- DLMX4- 8
[39] Z_LAN_MDIN0 TD1- MX1- DD-
LMX4+ 1 ZL4 2
10 15 RJ08J46BAA413
7 TCT4 MCT4 18 LMX4- 4 3 PCB Footprint = c100le-108h9-l-1
ZC3 4 TCT3 MCT3 21 PN = 6-21-B40L0-008
*WCM2012F2S-161T03-short
1 TCT2 MCT2 24 LAN_BD
0.01u_16V_X7R_04 TCT1 MCT1 NMCT_1 ZR2 75_1%_04 NMCT_R
GST5009 LF NMCT_2 ZR4 75_1%_04
LG-2413S NMCT_3 ZR3 75_1%_04
ZGND 6-19-41001-239 NMCT_4 ZR1 75_1%_04
Main : 6-07-1003C-1B0
EMI Require
ZGND
B B
A A
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Title
[41] LAN TRANSFORMER
Size Document Number Rev
A3 6-71-NLx0MU-D02 D02
B - 42 LAN Transformer
Schematic Diagrams
D
LAN & SD Card connector for Sub Board D
B.Schematic Diagrams
FOR 15"
ZJ_14MB2
ZPJ1
1
2
3
Z_SML0_CLK [39,42]
Z_SML0_DATA [39,42] 3.3V_LAN 1 2
*OPEN-8mil
Sheet 42 of 47
4 Z_PCIE_RXP6_CARD [40] 3.3V_LAN
5 Z_PCIE_RXN6_CARD [40] ON
6 U_VDD3
7 Z_CLK_PCIE_CARD [40] ZQ1 SM3415KIDSH
LAN Board
NC1 8 Z_CLK_PCIE_CARD# [40] S D
NC2 9
C 10 Z_PCIE_TXP7_GLAN [39] C
11 Z_PCIE_TXN7_GLAN [39] value,0517 max
G
Connector
12 ZC6 ZC7 ZC17
ZGND
13 Z_PCIE_RXP7_GLAN [39]
14 Z_PCIE_RXN7_GLAN [39]
0.1u_6.3V_X5R_02
0.1u_6.3V_X5R_02
15 value,0529 max 0.1u_6.3V_X5R_02
16 Z_CLK_PCIE_GLAN [39] ZR28
17 Z_CLK_PCIE_GLAN# [39]
18 1M_04
19 Z_PCIE_TXP6_CARD [40] ZR27 100K_04
20 Z_PCIE_TXN6_CARD [40]
D
21 ZQ2
22 Z_BUF_PLT_RST# [39,40,42]
FP225H-02261BM G ZR24 0_04
Z_PM_SLP_LAN# [42]
P/N = 6-20-94K10-022
S
PCB Footprint = FP225-022-R 2SK3018S3
ZGND
U_VDD3
ZH3 LAN_BD
*H5_0D2_3
ZH4 LAN_BD
*O248X268D85
FOR 14" ZJ_14MB1
H5_0D2_3 O248X268D85 1
ZJ_14MB3 2
3 U_3.3VS
T14
B 1 Z_SML0_CLK [39,42] 4 Z_LAN_RTD3_REL U_VDD3 B
2 Z_SML0_DATA [39,42] GND1 5
3 GND2 6 Z_PM_SLP_LAN# [42]
ZGND ZGND 4 Y_PCIE_RXP6_CARD [40] 7 Z_GLAN_CLKREQ# [39]
ZR156
5 Y_PCIE_RXN6_CARD [40] 8 Z_CARD_CLKREQ# [40]
ZH1 ZH5 6 9 Z_LAN_W AKEUP#_R [39] *10K_02
ZGND
2 4 2 4 7 Y_CLK_PCIE_CARD [40] 10 Z_SDCARD_W AKE# [40]
NC1 8 Y_CLK_PCIE_CARD# [40] 11 Z_LAN_DISABLE# [39] Z_LAN_ID
3 1 5 3 1 5 NC2 9 12
10 Y_PCIE_TXP7_GLAN [39]
50208-01201-001
11 Y_PCIE_TXN7_GLAN [39]
*MTH9_5D2_3 *MTH9_5D2_3 ZGND PCB Footprint = 50208-012xx-xxx_r ZR163
12 P/N = 6-21-64D00-112
MTH9_5D2_3 MTH9_5D2_3 13 Y_PCIE_RXP7_GLAN [39] 10K_02
LAN_BD LAN_BD 14 Y_PCIE_RXN7_GLAN [39]
ZGND ZGND ZGND 15
16 Y_CLK_PCIE_GLAN [39]
ZGND
17 Y_CLK_PCIE_GLAN# [39]
18
19 Y_PCIE_TXP6_CARD [40]
ZH2 LAN_BD
20 Y_PCIE_TXN6_CARD [40]
*O134X154B251X271D95X106
O134X154B251X271D95X106 21
22 Z_BUF_PLT_RST# [39,40,42]
FP225H-02261BM
P/N = 6-20-94K10-022 ZGND
PCB Footprint = FP225-022-R
ZGND
A A
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Title
[42] LAN Board connector
Size Document Number Rev
A3 6-71-NLx0MU-D02 D02
14"_IO_BD 0201
1 2
AD4 *PESD5V0R1BSF
HP-L
GND
A_SLEEVE_CONN AR4 0_04 A_SLEEVE_CON_R AL4
A_AUDG
FCM1005MF-300T03 14"_IO_BD
1
AD6
2
3.3V 14"_IO_BD COMBO JACK
3 * R / L 䶂⮔ 14"_IO_BD
HP-R AC7
GND 100p_50V_NPO_04
14"_IO_BD A_AUDG AR5 *0402_short
Layout note:
D A_AUDG AJ_COMBO1 D
14"_IO_BD A_SLEEVE_CON 1
Headphone妲嘇
䶂 ⮔ > 10mi l s A_HEADPHONE_L_DEPOP AR2 82_04 A_EARPHONE_L AL2 FCM1005KF-121T03 14"_IO_BD A_HPOL_CON 4
嶅暊 p h o n e j a ck崲
怈 5
䶂⼹⯙⽭枰崲⮔ 14"_IO_BD A_HPOUT-JD 6
R / L ⽭枰⊭ 央 GNDᶼ 攻嶅 䁢 3 * 䶂 ⮔ A_HEADPHONE_R_DEPOP AR1 82_04 A_EARPHONE_R AL1
A_RING2_CONN AL5
FCM1005KF-121T03 14"_IO_BD A_HPOR_CON
A_RING2_CON
3
FCM1005MF-300T03 14"_IO_BD 2
AC8 AC5 AC6
2SJ3127-000111F
1
0_04
100p_50V_NPO_04
100p_50V_NPO_04
AD1 AD2 AD5 PCB Footprint = 2sj3127-000111f
AJ_MB1
P/N = 6-20-B28X0-006
A5V AC10 0.1u_25V_X5R_04 14"_IO_BD
40 14"_IO_BD
14"_IO_BD
14"_IO_BD
14"_IO_BD
*AVLC5S02100
*AVLC5S02100
*AVLC5S02100
39 AC2 0.1u_25V_X5R_04 14"_IO_BD Layout trace > 40 mil ,
14"_IO_BD
Footprint=FP201-040X1-0M pin1 fix
14"_IO_BD
14"_IO_BD
38 AC3 0.1u_25V_X5R_04 14"_IO_BD suggest to implement shapes.
2
37
36 AC1 0.1u_25V_X5R_04 14"_IO_BD
B.Schematic Diagrams
35
34 AR3 *0_04 14"_IO_BD
33
32
31 A3.3V A_AUDG AGND
A3.3VS A_AUDG A_AUDG
30
29
28 A_M_BTN# POWER SW
Sheet 43 of 47
27
S1 S2 S2
POWER BUTTON
A_M_BTN#
C
GND
20 12/27 Add FP conn for POSTIVO (D03) G2 GND
1
19 GND
18 AD3 AC4
TCD-C2KQR
G3
17 *AVL18S02015
PCB Footprint = TCD-C2KQR
16 14"_IO_BD 0.1u_50V_X5R_04
P/N = 6-53-31500-041
15 VARISTOR 14"_IO_BD
14 14"_IO_BD 6-24-30003-006
A_USB_PP5
2
13 A_USB_PN5
12 USB2.0
11 A_USB_PW R_EN# AGND
10 AGND
9
8 A_RING2_CONN
FP CONN 12/27 Add FP conn for POSTIVO (D03)
7 A_SLEEVE_CONN
ĕ÷ýõýĆöñå 㛔 幓㚫䅺 㭨ñ
GND2 6 A_HPOUT-JD AJ_FP1 >30mil AL3 ĕ÷ýõýĆö
GND1 5
4 A_HEADPHONE_L_DEPOP HEAD-PHONE 1
FCM1005KF-121T03
A3.3VS 䫾 å ĉ÷ û å IJĴĺijĹ Ī ĩ å ěĆėĎ Ę ęĔėó
⮵
3 A_HEADPHONE_R_DEPOP 2
AGND 2 NC1 3 AGND
1 NC2 4 A_USB_PN3 AH3 AH2 AH4 AH1
5 A_USB_PP3 *H6_0D2_3 *H6_5B3_0D2_3 *H4_8b3_0d2_4 *H9_5D5_5
1AR1 *0_02 4AR1 *0_02 H6_0D2_3 H6_5B3_0D2_3 H4_8b3_0d2_4 H9_5D5_5
FP201H-040S10M 6
AGND 14"_IO_BD 14"_IO_BD
P/N = 6-20-94K20-140 A_AUDGAGND
FP225H-006S10M 2AR1 *0_02 5AR1 *0_02
PCB Footprint = FP201-040X1-0M
P/N = 6-20-94K00-006 AD8 1 2 AVL18S02015 AGND 14"_IO_BD 14"_IO_BD
14"_IO_BD
PCB Footprint = fp225h-006xxxm_R AD7 1 2 AVL18S02015 AGND 3AR1 *0_02 6AR1 *0_02
14"_IO_BD 14"_IO_BD
B 7AR1 *0_02 8AR1 *0_02 B
AGND AGND AGND AGND
14"_IO_BD 14"_IO_BD 14"_IO_BD 14"_IO_BD 14"_IO_BD 14"_IO_BD
A_USBVCC2.0
60 mil
A5V 5
AU1
VIN VOUT
1 60 MIL USB2.0 PORT_5 A_USBVCC2.0 AC12
AC13
22u_6.3V_X5R_06
14"_IO_BD
22u_6.3V_X5R_06
AGND
AGND
14"_IO_BD
2
GND AC9
AC11
4 3
EN# OC# 0.1u_6.3V_X5R_02
10u_6.3V_X5R_06 AD9
AJ_USB1
SY6288D20AAC 14"_IO_BD
14"_IO_BD AR6 *0_04 14"_IO_BD 6 5 1
2A/90mohm 7 4 V+ 0.5A GND2
AGND 14"_IO_BD A_USB_PN5_C GND2
8 3 2 GND1
SY6288D20AAC: 6-02-62882-9C0
AGND A_USB_PN5 1 2 A_USB2_PN5AGND 9 2
AGND DATA_L GND1
uP7549UMA5-20: 6-02-75495-9C0
*WCM2012F2S-161T03 A_USB2_PP5 10 1 A_USB_PP5_C 3
A_USB_PW R_EN# AL6 PCB Footprint = WCM2012F2S-SHORT DATA_H
A_USB_PP5 4 3 GND3
14"_IO_BD 4 AGND GND4
AR7 *0_04 14"_IO_BD ESD73034D GND AGND
14"_IO_BD
AGND C147S3-10439-L
A
Colay 䔲㓦 20190620 layout swap PCB Footprint = c147s3-10439-l-1
P/N = 6-21-B4920-004
AGND
A
14"_IO_BD
15"_IO_BD 0201
1 2
W D5 *PESD5V0R1BSF
W UDG 1 2
D
HP-L
GND
W _SLEEVE_CONN W R3
3 * R / L 䶂⮔
0_04 W _SLEEVE_CON_R W L1
15"_IO_BD
FCM1005MF-300T03 15"_IO_BD
W D4 3.3V
15"_IO_BD COMBO JACK D
HP-R W C6
GND 100p_50V_NPO_04
15"_IO_BD W UDG W R2 *0402_short
Layout note:
W UDG W J_COMBO1
15"_IO_BD W _SLEEVE_CON 1
Headphone妲嘇
䶂 ⮔ > 10mi l s W _HEADPHONE_L_DEPOP W R5 82_04 W _EARPHONE_L W L3 FCM1005KF-121T03 15"_IO_BD W _HPOL_CON 4
嶅暊 p h o n e j a ck崲
怈 5
䶂⼹⯙⽭枰崲⮔ 15"_IO_BD W _HPOUT-JD 6
R / L ⽭枰⊭ 央 GNDᶼ 攻嶅 䁢 3 * 䶂 ⮔ W _HEADPHONE_R_DEPOP W R4 82_04 W _EARPHONE_R W L2
W _RING2_CONN
FCM1005KF-121T03 15"_IO_BD W _HPOR_CON
W _RING2_CON
3
W L4 FCM1005MF-300T03 15"_IO_BD 2
W C2 W C3 W C4
2SJ3127-000111F
1
0_04
W D1 W D2 W D3
100p_50V_NPO_04
100p_50V_NPO_04
PCB Footprint = 2sj3127-000111f
W C10 0.1u_25V_X5R_04 15"_IO_BD P/N = 6-20-B28X0-006
B.Schematic Diagrams
15"_IO_BD
15"_IO_BD
15"_IO_BD
15"_IO_BD
*AVLC5S02100
*AVLC5S02100
*AVLC5S02100
W C1 0.1u_25V_X5R_04 15"_IO_BD
Layout trace > 40 mil ,
15"_IO_BD
15"_IO_BD
15"_IO_BD
suggest to implement shapes.
W C7 0.1u_25V_X5R_04 15"_IO_BD
2
W R1 *0_04 15"_IO_BD
W UDG
W GND
W UDG W UDG
Sheet 44 of 47
C C
15” I/O Board 1
W J_MB1
40
39
W 5V FOR 15" I/O BOARD
Footprint=FP201-040X1-0M pin1 fix
38
37
36
35
34
33
32
31 W 3.3V
30 W 3.3VS
29
28
27
26
25 W R6 *4.7K_04 15"_IO_BD_LTE
24 W J_SIM1
23 W _USB_PN3 [45] USB2.0 21-6012-01 15"_IO_BD_LTE
22 W _USB_PP3 [45] 15"_IO_BD_LTE PCB Footprint = 21-6012-0x
21 W GND W C9 0.01u_16V_X7R_04 P/N = 6-86-2B010-007
W J_MB2
20 W _UIM_PWR (TOP VIEW)
19 1 W _SIM_DET SW1 C8
C4 DETECT_SW UIM_MCMD C7 W _UIM_DATA
18 2
W _UIM_CLK C3 UIM_DATA UIM_I/O C6 W _UIM_VPP
B 17 3 W _SIM_DET W T1 B
W _UIM_RST C2 UIM_CLK UIM_VPP C5
16 4 W _UIM_CLK
W _UIM_PWR UIM_RST UIM_GND
GND1
GND2
GND3
GND4
15 5 W _UIM_DATA C1 15"_IO_BD_LTE
UIM_PWR
14 6 W _UIM_RST
13 W _USB_PP5 [45] 7
12 W _USB_PN5 [45] USB2.0 8
GND1
GND2
GND3
GND4
11 W C5 W C8
10 W _USB_PW R_EN# [45]
W GND
9 *0.1u_6.3V_X5R_02 22p_50V_NPO_04
FP225H-008S11M
8 W _RING2_CONN 15"_IO_BD_LTE 15"_IO_BD_LTE
PCB Footprint = fp225h-008gxxxm_r
7 W _SLEEVE_CONN P/N = 6-20-94K30-108
GND2 6 W _HPOUT-JD W GND W GND W GND
15"_IO_BD_LTE
GND1 5
4 W _HEADPHONE_L_DEPOP HEAD-PHONE
3 W _HEADPHONE_R_DEPOP
2
W GND 1
FP201H-040S10M
P/N = 6-20-94K20-140 W UDG W GND
PCB Footprint = FP201-040X1-0M
15"_IO_BD
A A
W H2 W H4 W H3
W H1 W H5
2 4 2 4 *H4_0D2_3
*H3_9D2_3 *H7_0D5_8
1W R1 *0_02 4W R1 *0_02 H4_0D2_3
H3_9D2_3 H7_0D5_8
3 1 5 3 1 5 15"_IO_BD 15"_IO_BD
2W R1 *0_02 5W R1 *0_02
*MTH7_0D2_3 *MTH7_0D2_3
15"_IO_BD
3W R1 *0_02
15"_IO_BD
6W R1 *0_02
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
MTH7_0D2_3 MTH7_0D2_3 15"_IO_BD 15"_IO_BD Title
<FUNCTION> <FUNCTION> W GND W GND
7W R1 *0_02 8W R1 *0_02 W GND [44] NL50MU I/O BOARD_1_W
W GND W GND W GND 15"_IO_BD 15"_IO_BD <FUNCTION>
<FUNCTION> <FUNCTION> Size Document Number Rev
[45] W 5V
A3 6-71-NLx0MU-D02 D01
D D
W _USBVCC
W U2
5 1
W 5V VIN VOUT
W C12 2 W C17
10u_6.3V_X5R_06 GND 0.1u_6.3V_X5R_02
4 3 15"_IO_BD
15"_IO_BD EN# OC#
Sheet 45 of 47
W GND SY6288D20AAC
2A/90mohm
15"_IO_BD W GND
W _USB_PW R_EN# SY6288D20AAC: 6-02-62882-9C0
W C18 22u_6.3V_X5R_06
15"_IO_BD
W _USBVCC W C16 22u_6.3V_X5R_06 W GND
15"_IO_BD
15"_IO_BD
PCB Footprint = dfn10-2_5x1mm-short
ESD73034D
W J_USB2
W R10 *0_04 15"_IO_BD 6 5
1
7 4 V+ GND2
W _USB_PN3_R W GND 8 3 W GND W _USB_PN3_RJ GND2
1 2 W L6 15"_IO_BD 2 GND1
[44] W _USB_PN3 9 2 DATA_L GND1
*WCM2012F2S-161T03-short
10 1
4 3 PCB Footprint = W CM2012F2S-SHORT W _USB_PP3_R W _USB_PP3_RJ 3
[44] W _USB_PP3 DATA_H GND3
W R9 *0_04 15"_IO_BD 4 AGND GND4
W D7 GND AGND
Colay C147S3-10439-L
6-21-B4910-004
W GND
B W GND PCB Footprint = c147s3-10439-l-1 B
15"_IO_BD
P/N = 6-21-B4920-004
60 mil
W C14 22u_6.3V_X5R_06
W _USBVCC2.0
USB2.0 PORT_5 TYPE-A W _USBVCC2.0
W C11
15"_IO_BD
22u_6.3V_X5R_06
15"_IO_BD
W GND
W GND
W U1 W J_USB1
5 1 60 MIL 1
W 5V VIN VOUT W R8 *0_04 15"_IO_BD 15"_IO_BD V+ 0.5A GND2
ESD73034D W _USB_PN5_C GND2
2 2 GND1
GND W C13 W _USB2_PN5 DATA_L GND1
W C15 1 2 6 5
[44] W _USB_PN5 W _USB2_PP5 W _USB_PP5_C
4 3 W L5 *WCM2012F2S-161T03 7 4 3
EN# OC# 0.1u_6.3V_X5R_02 DATA_H
10u_6.3V_X5R_06 4 3 PCB Footprint = WCM2012F2S-SHORT W GND 8 3 W GND GND3
[44] W _USB_PP5 15"_IO_BD AGND
SY6288D20AAC 15"_IO_BD 9 2 4 GND4
15"_IO_BD GND AGND
2A/90mohm W R7 *0_04 15"_IO_BD 10 1
W GND 15"_IO_BD
SY6288D20AAC: 6-02-62882-9C0 W GND C147S3-10439-L
A W _USB_PW R_EN#
uP7549UMA5-20: 6-02-75495-9C0 W GND
Colay W D6 6-21-B4910-004
PCB Footprint = c147s3-10439-l-1
W GND A
15"_IO_BD
P/N = 6-21-B4920-004
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
FOR USB2.0 PORT ONLY, EMI暨
㯪, Title
⤪㚱ⷞ 䶂 M/B䪗冯⮷ ⌉ 䪗 悥暨枸䔁 , 嬻 E M I 䡢娵 ⒒䪗ᶲ ẞ [45] NL50MU I/O BOARD_2_W
Size Document Number Rev
[44] W 5V
A3 6-71-NLx0MU-D02 D01
Date: W ednesday, August 18, 2021 Sheet 45 of 47
5 4 3 2 1
D D
B.Schematic Diagrams
POWER BUTTON Sheet 46 of 47
PWR Button Board
C C
B_SW1
1 2
POWER ON 3 4 BM_BTN#
BLED_PWR_R
B3.3VS
BJ_BTN1 LOCK LED T4BJB10BQR2
BT1
PCB Footprint = T4BJB16-Q
1 D02 modify
1
BLED_PWR P/N = 6-53-31500-B41
NC1 2 BM_BTN# BR1
15"_PWR_BD BD2 BC1
NC2 3
4 390_04
BGND 0.1u_6.3V_X5R_02
15"_PWR_BD
BGND *AVL18S02015 15"_PWR_BD
FP226H-004S10M BGND VARISTOR
BD3
2
P/N = 6-20-94A40-004 P/N: 6-24-30003-006
PCB Footprint = fp226H-004xxxm_r A C BGND 15"_PWR_BD
15"_PWR_BD
BGND
RY-SP190DBW71-5A
PCB Footprint = RY-SP190YG34-5M
P/N = 6-52-57301-022 THE VARISTOR FOR
15"_PWR_BD P2808A1 BURN SOLUTION
B LED COLOR = WHITE B
Power Sequence
5 4 3 2 1
VCCRTC
13.813ms
RTCRST#
PWR_SW#
VDD3 1.523ms
DSW_PWROK(PCH_DPWROK) 77.274ms
SLP_SUS# 95.9ms
B.Schematic Diagrams
VA_EC_EN 124.778ms
3.3VA 253.456us
1.8VA 1.4792ms
Sheet 47 of 47 DD_ON
3.3V
9.195ms
384.852us
Power Sequence C
VDD5 1.484ms
C
5V 326.108us
VCCIN_AUX 1.4169ms
RSMRST# 125.977ms
ESPI_RESET_N 2.554ms
SUSC# 157.8432ms
SUSB# 28.232us
3.3VS 370.299us
CPU_C10_GATE# 637.1661us
VCCSTG 19.8879us
5VS 155.128us
2.5V 835.007us
B B
VDDQ 2.3533ms
VCCIO_EN 2.313ms
VDDQ_PWRGD 1.0027us
VDDQ_VTT 32.1535us
H_VR_READY 1.6322ms
PCH_PWROK 219.565ms
SYS_PWROK;PCH_PWROK_EC 50.4659us
PLT_RST# 74.6829ms
A A
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Title
[47] Power Sequence
Size Document Number Re v
Custom 6-71-NLx0MU-D02 D02
Date: Wednesday, August 18, 2021 Sheet 47 of 47
5 4 3 2 1
B - 48 Power Sequence