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NH55RCQ / NH58RCQ

Preface

Notebook Computer

NH55RCQ / NH58RCQ

Service Manual

Preface
I
Preface

Notice
The company reserves the right to revise this publication or to change its contents without notice. Information contained
herein is for reference only and does not constitute a commitment on the part of the manufacturer or any subsequent ven-
dor. They assume no responsibility or liability for any errors or inaccuracies that may appear in this publication nor are
they in anyway responsible for any loss or damage resulting from the use (or misuse) of this publication.

This publication and any accompanying software may not, in whole or in part, be reproduced, translated, transmitted or
reduced to any machine readable form without prior consent from the vendor, manufacturer or creators of this publica-
tion, except for copies kept by the user for backup purposes.

Brand and product names mentioned in this publication may or may not be copyrights and/or registered trademarks of
their respective companies. They are mentioned for identification purposes only and are not intended as an endorsement
of that product or its manufacturer.
Preface

Version 1.0
April 2019

Trademarks
Intel and Intel Core are trademarks of Intel Corporation.
Windows® is a registered trademark of Microsoft Corporation.
Other brand and product names are trademarks and /or registered trademarks of their respective companies.

II
Preface

About this Manual


This manual is intended for service personnel who have completed sufficient training to undertake the maintenance and
inspection of personal computers.

It is organized to allow you to look up basic information for servicing and/or upgrading components of the NH55RCQ /
NH58RCQ series notebook PC.

The following information is included:

Chapter 1, Introduction, provides general information about the location of system elements and their specifications.
Chapter 2, Disassembly, provides step-by-step instructions for disassembling parts and subsystems and how to upgrade
elements of the system.

Appendix A, Part Lists

Preface
Appendix B, Schematic Diagrams

III
Preface

IMPORTANT SAFETY INSTRUCTIONS


Follow basic safety precautions, including those listed below, to reduce the risk of fire, electric shock and injury to per-
sons when using any electrical equipment:

1. Do not use this product near water, for example near a bath tub, wash bowl, kitchen sink or laundry tub, in a wet
basement or near a swimming pool.
2. Avoid using a telephone (other than a cordless type) during an electrical storm. There may be a remote risk of elec-
trical shock from lightning.
3. Do not use the telephone to report a gas leak in the vicinity of the leak.
4. Use only the power cord and batteries indicated in this manual. Do not dispose of batteries in a fire. They may
explode. Check with local codes for possible special disposal instructions.
5. This product is intended to be supplied by a Listed Power Unit as follows:
• AC Input of 100 - 240V, 50 - 60Hz, DC Output of 19.5V, 9.23A (180 Watts) minimum AC/DC Adapter.
Preface

FCC Statement
This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions:
This device may not cause harmful interference.
This device must accept any interference received, including interference that may cause undesired operation.

IV
Preface

Instructions for Care and Operation


The notebook computer is quite rugged, but it can be damaged. To prevent this, follow these suggestions:

1. Don’t drop it, or expose it to shock. If the computer falls, the case and the components could be damaged.
Do not expose the computer Do not place it on an unstable Do not place anything heavy
to any shock or vibration. surface. on the computer.

2. Keep it dry, and don’t overheat it. Keep the computer and power supply away from any kind of heating element. This
is an electrical appliance. If water or any other liquid gets into it, the computer could be badly damaged.
Do not expose it to excessive Do not leave it in a place Don’t use or store the com- Do not place the computer on

Preface
heat or direct sunlight. where foreign matter or mois- puter in a humid environment. any surface which will block
ture may affect the system. the vents.

3. Follow the proper working procedures for the computer. Shut the computer down properly and don’t forget to save
your work. Remember to periodically save your data as data may be lost if the battery is depleted.
Do not turn off the power Do not turn off any peripheral Do not disassemble the com- Perform routine maintenance
until you properly shut down devices when the computer is puter by yourself. on your computer.
all programs. on.

V
Preface

4. Avoid interference. Keep the computer away from high capacity transformers, electric motors, and other strong mag-
netic fields. These can hinder proper performance and damage your data.
5. Take care when using peripheral devices.

Use only approved brands of Unplug the power cord before


peripherals. attaching peripheral devices.

Power Safety
Preface

The computer has specific power requirements:


• Only use a power adapter approved for use with this computer.
• Your AC adapter may be designed for international travel but it still requires a steady, uninterrupted power supply. If you are
 unsure of your local power specifications, consult your service representative or local power company.
Power Safety • The power adapter may have either a 2-prong or a 3-prong grounded plug. The third prong is an important safety feature; do
Warning not defeat its purpose. If you do not have access to a compatible outlet, have a qualified electrician install one.
Before you undertake • When you want to unplug the power cord, be sure to disconnect it by the plug head, not by its wire.
any upgrade proce- • Make sure the socket and any extension cord(s) you use can support the total current load of all the connected devices.
dures, make sure that • Before cleaning the computer, make sure it is disconnected from any external power supplies.
you have turned off the
power, and discon-
nected all peripherals Do not plug in the power Do not use the power cord if Do not place heavy objects
and cables (including cord if you are wet. it is broken. on the power cord.
telephone lines and
power cord). It is advis-
able to also remove
your battery in order to
prevent accidentally
turning the machine
on.

VI
Preface

Battery Precautions
• Only use batteries designed for this computer. The wrong battery type may explode, leak or damage the computer.
• Do not continue to use a battery that has been dropped, or that appears damaged (e.g. bent or twisted) in any way. Even if the
computer continues to work with a damaged battery in place, it may cause circuit damage, which may possibly result in fire.
• Recharge the batteries using the notebook’s system. Incorrect recharging may make the battery explode.
• Do not try to repair a battery pack. Refer any battery pack repair or replacement to your service representative or qualified service
personnel.
• Keep children away from, and promptly dispose of a damaged battery. Always dispose of batteries carefully. Batteries may explode
or leak if exposed to fire, or improperly handled or discarded.
• Keep the battery away from metal appliances.
• Affix tape to the battery contacts before disposing of the battery.
• Do not touch the battery contacts with your hands or metal objects.

Battery Guidelines
The following can also apply to any backup batteries you may have.

Preface
• If you do not use the battery for an extended period, then remove the battery from the computer for storage.
• Before removing the battery for storage charge it to 60% - 70%.
• Check stored batteries at least every 3 months and charge them to 60% - 70%.


Battery Disposal
The product that you have purchased contains a rechargeable battery. The battery is recyclable. At the end of its useful life, under var-
ious state and local laws, it may be illegal to dispose of this battery into the municipal waste stream. Check with your local solid waste
officials for details in your area for recycling options or proper disposal.

Caution
Danger of explosion if battery is incorrectly replaced. Replace only with the same or equivalent type recommended by the manufacturer.
Discard used battery according to the manufacturer’s instructions.

Battery Level
Click the battery icon in the taskbar to see the current battery level and charge status. A battery that drops below a level of 10%
will not allow the computer to boot up. Make sure that any battery that drops below 10% is recharged within one week.

VII
Preface

Related Documents
You may also need to consult the following manual for additional information:

User’s Manual on CD/DVD


This describes the notebook PC’s features and the procedures for operating the computer and its ROM-based setup pro-
gram. It also describes the installation and operation of the utility programs provided with the notebook PC.

System Startup
1. Remove all packing materials.
2. Place the computer on a stable surface.
3. Insert the battery and make sure it is locked in position.
4. Securely attach any peripherals you want to use with the
computer (e.g. keyboard and mouse) to their ports.
Preface

5. When first setting up the computer use the follow- 130°


ing procedure (as to safeguard the computer during Figure 1
shipping, the battery will be locked to not power the sys- Opening the Lid/LCD/
tem until first connected to the AC/DC adapter and ini- Computer with AC/DC
tially set up as below): Adapter Plugged-In
• Attach the AC/DC adapter cord to the DC-In jack on the rear
of the computer, then plug the AC power cord into an outlet,
and connect the AC power cord to the AC/DC adapter and
leave it there for 6 seconds or longer.

• Remove the adapter cord from the computer’s DC-In jack,
Shut Down
and then plug it back in again; the battery will now be
unlocked. Note that you should always shut your computer down by
choosing the Shut down command in Windows (see be-
6. Use one hand to raise the lid/LCD to a comfortable viewing low). This will help prevent hard disk or system problems.
angle (do not exceed 130 degrees); use the other hand (as
illustrated in Figure 1) to support the base of the computer Click the icon in the Start Screen and
(Note: Never lift the computer by the lid/LCD). choose Shut down from the menu.

7. Press the power button to turn the computer “on”. Or


Right-click the Start button at the bottom of the Start
Screen or the Desktop and choose Shut down or sign out
> Shut down from the context menu.

VIII
Preface

Contents
Introduction ..............................................1-1 Bottom ........................................................................................... A-5
Main Board ................................................................................... A-6
Overview .........................................................................................1-1 HDD .............................................................................................. A-7
Specifications ..................................................................................1-2 LCD (NH55RCQ) .......................................................................... A-8
External Locator - Top View with LCD Panel Open ......................1-4 LCD (NH58RCQ) .......................................................................... A-9
External Locator - Front & Right Side Views .................................1-5
External Locator - Left Side & Rear View .....................................1-6 Schematic Diagrams................................. B-1
External Locator - Bottom View .....................................................1-7 System Block Diagram ...................................................................B-2
Mainboard Overview - Top (Key Parts) .........................................1-8 Processor 1/6 ...................................................................................B-3
Mainboard Overview - Bottom (Key Parts) ....................................1-9 Processor 2/6 ...................................................................................B-4
Mainboard Overview - Top (Connectors) .....................................1-10 Processor 3/6 ...................................................................................B-5
Mainboard Overview - Bottom (Connectors) ...............................1-11 Processor 4/6 ...................................................................................B-6
Disassembly ...............................................2-1 Processor 5/6 ...................................................................................B-7

Preface
Processor 6/6 ...................................................................................B-8
Overview .........................................................................................2-1 DDR4 CHA SO-DIMM ..................................................................B-9
Maintenance Tools ..........................................................................2-2 DDR4 CHB SO-DIMM ................................................................B-10
Connections .....................................................................................2-2 VGA PCI Express .........................................................................B-11
Maintenance Precautions .................................................................2-3 GPU Frame Buffer Partition .........................................................B-12
Disassembly Steps ...........................................................................2-4 Frame Buffer A .............................................................................B-13
Removing the Battery ......................................................................2-5 Frame Buffer A .............................................................................B-14
Removing the Keyboard ..................................................................2-6 Frame Buffer B .............................................................................B-15
Removing the Hard Disk Drive .......................................................2-7 Frame Buffer B .............................................................................B-16
Removing the System Memory (RAM) ..........................................2-9 Frame Buffer C/D .........................................................................B-17
Removing the M.2 SSD Module ...................................................2-10 Frame Buffer C .............................................................................B-18
Removing the Wireless LAN Module ...........................................2-11 Frame Buffer C .............................................................................B-19
Wireless LAN, Combo Module Cables .........................................2-12 GPU Decoupling 1 ........................................................................B-20
Removing the CCD .......................................................................2-13 GPU Decoupling 2 ........................................................................B-21
Part Lists ..................................................A-1 Straps and XTAL ..........................................................................B-22
Part List Illustration Location ........................................................ A-2 IFP I/O Interface ...........................................................................B-23
Top ................................................................................................. A-3 Misc - GPIO, I2C and ROM .........................................................B-24
Top without FP ............................................................................... A-4 NVIDIA Power Sequence .............................................................B-25

IX
Preface

GPU NVVDD, FBVDDQ ............................................................ B-26 AC_In, Charger .............................................................................B-58


GPU GND .................................................................................... B-27 NVVDD1 ......................................................................................B-59
mDP .............................................................................................. B-28 NVVDD2 ......................................................................................B-60
mDP .............................................................................................. B-29 PEX_VDD ....................................................................................B-61
Panel, Inverter .............................................................................. B-30 FBVDDQ ......................................................................................B-62
HDMI ........................................................................................... B-31 1V8_RUN/AON ...........................................................................B-63
PCH 1/9 ........................................................................................ B-32 Audio Board ..................................................................................B-64
PCH 2/9 ........................................................................................ B-33 NH50 PW Board ...........................................................................B-65
PCH 3/9 ........................................................................................ B-34 Hall Sensor Board .........................................................................B-66
PCH 4/9 ........................................................................................ B-35 Click Board ...................................................................................B-67
PCH 5/9 ........................................................................................ B-36 LED Board ....................................................................................B-68
PCH 6/9 ........................................................................................ B-37 NH70 PW Board ...........................................................................B-69
PCH 7/9 ........................................................................................ B-38 Power Sequence ............................................................................B-70
PCH 8/9 ........................................................................................ B-39 USB Type-C .................................................................................B-71
Preface

PCH 9/9 ........................................................................................ B-40 PD Controller ANX7411 ..............................................................B-72


M.2 Card ....................................................................................... B-41 PER KEY Board ...........................................................................B-73
M.2 WLAN+BT ........................................................................... B-42 DGPU Power Measurement ..........................................................B-74
USB Charger ................................................................................ B-43
Card Reader / LAN RTL8411B ................................................... B-44
HDD, Click TP, Audio, Hall Con. ............................................... B-45
LED, CCD, TPM, Power SW Con. .............................................. B-46
Audio Codec ................................................................................. B-47
KBC-ITE IT8587 ......................................................................... B-48
RGB KB Only .............................................................................. B-49
5V, 5VS, 3.3V, 3.3VS .................................................................. B-50
VDD1.05V, VCCIO ..................................................................... B-51
VDD3, VDD5 ............................................................................... B-52
DDR 1.2V / 0.6VS, 2.5V ............................................................. B-53
VCore Output Stage ..................................................................... B-54
VCC_Core & VCCGT ................................................................. B-55
1.05DX_VCCSTG/VCCSFR_OC ............................................... B-56
VCCGT & VCCSA Output Stage ................................................ B-57

X
Introduction

Chapter 1: Introduction
Overview
This manual covers the information you need to service or upgrade the NH55RCQ / NH58RCQ series notebook com-
puter. Information about operating the computer (e.g. getting started, and the Setup utility) is in the User’s Manual. In-
formation about dri-vers (e.g. VGA & audio) is also found in the User’s Manual. The manual is shipped with the
computer.

Operating systems (e.g. Windows 10, etc.) have their own manuals as do application softwares (e.g. word processing and
database programs). If you have questions about those programs, you should consult those manuals.

1.Introduction
The NH55RCQ / NH58RCQ series notebook is designed to be upgradeable. See Disassembly on page 2 - 1 for a detailed
description of the upgrade procedures for each specific component. Please take note of the warning and safety informa-
tion indicated by the “” symbol.

The balance of this chapter reviews the computer’s technical specifications and features.

Overview 1 - 1
Introduction

Specifications Processor Options Audio

Intel® Core™ i7 Processor High Definition Audio Compliant Interface


i7-9750H (2.60GHz) Sound Blaster™ Cinema 5
12MB Smart Cache, 14nm, DDR4-2666MHz, TDP 45W Built-In Array Microphone
 Intel® Core™ i5 Processor Two Speakers
Latest Specification Information i5-9300H (2.40GHz)
LCD Options
The specifications listed here are correct at the 8MB Smart Cache, 14nm, DDR4-2666MHz, TDP 45W
time of sending them to the press. Certain items 15.6" (39.62cm), 16:9, FHD (1920x1080)
(particularly processor types/speeds) may be Core Logic
changed, delayed or updated due to the manu- Video Adapter
Mobile Intel® HM370 Express Chipset
facturer's release schedule. Check with your
service center for more details. Intel® Integrated GPU and NVIDIA® Discrete GPU
BIOS
Supports Microsoft Hybrid Graphics
128Mb SPI Flash ROM
1.Introduction

INSYDE BIOS Intel Integrated GPU


Intel® UHD Graphics 630
Memory Dynamic Frequency
 Dual Channel DDR4 Intel Dynamic Video Memory Technology
CPU Two 260 Pin SO-DIMM Sockets Microsoft DirectX®12 Compatible
The CPU is not a user serviceable part. Ac- Supporting DDR4 2666MHz Memory Modules NVIDIA® Discrete GPU
cessing the CPU in any way may violate your Memory Expandable from 8GB (minimum) up to 64GB NVIDIA® GeForce GTX 1660Ti
warranty. (maximum)
6GB GDDR6 Video RAM on board
Compatible with 4GB, 8GB, 16GB or 32GB Modules
Microsoft DirectX® 12 Compatible
(The real memory operating frequency depends on the FSB
of the processor.) Security

Storage Security (Kensington® Type) Lock Slot


BIOS Password
One changeable 2.5" 7.0mm (h) SATA (Serial) Hard Disk Intel® PTT for Systems Without TPM Hardware
Drive/Solid State Drive (SSD)
(Factory Option) TPM 2.0
(Factory Option) One M.2 2280 SATA Solid State Drive
(SSD) Keyboard
Or
(Factory Option) Two PCIe Gen3 x4 M.2 2280 SSDs sup- Full-size Multi-Color LED Keyboard (with Numeric Keypad)
porting RAID level 0/1 Or
(Factory Option) Full Size Full Color “Per Key” LED Key-
board (with Numeric Keypad)

1 - 2 Specifications
Introduction

Pointing Device Communication

Built-in Touchpad (with Microsoft PTP Multi Gesture & Scroll- Built-In 10/100/1000Mb Base-TX Ethernet LAN
ing Functionality) 1.0M HD PC Camera Module

Card Reader WLAN/ Bluetooth M.2 Modules:


Embedded Multi-In-1 Card Reader (Factory Option) Intel® Dual Band Wireless-AC 9260 Wire-
less LAN (802.11ac) + Bluetooth
MMC (MultiMedia Card) / RS MMC
(Factory Option) Intel® Dual Band Wireless-AC 9560 Wire-
SD (Secure Digital) / Mini SD / SDHC/ SDXC
less LAN (802.11ac) + Bluetooth
M.2 Slots (Factory Option) Intel® Dual Band Wireless-AC 9462 Wire-
less LAN (802.11ac) + Bluetooth
Slot 1 for Combo WLAN and Bluetooth Module (Factory Option) Qualcomm® Atheros Killer™ Wireless-AC
Slot 2 for SATA or PCIe Gen3 x4 SSD 1550i Wireless LAN (802.11ac) + Bluetooth
Slot 3 for PCIe Gen3 x4 SSD
Environmental Spec

1.Introduction
Interface
Temperature
One DisplayPort 1.3 over USB 3.1 Gen 2 Type-C Port Operating: 5°C - 35°C
One USB 3.1 Gen 2 Type-A Port Non-Operating: -20°C - 60°C
One USB 3.0 (USB 3.1 Gen 1) Type-A Port Relative Humidity
One USB 2.0 Port Operating: 20% - 80%
One Mini DisplayPort 1.2 Non-Operating: 10% - 90%
One HDMI-Out Port
One Microphone-In Jack
Power
One 2- In-1 Audio Jack (Headphone and Microphone) Removable 4 Cell Smart Lithium-Ion Battery Pack, 48.96WH
One RJ-45 LAN Jack
One DC-In Jack Full Range AC/DC Adapter
AC Input: 100 - 240V, 50 - 60Hz
DC Output: 19.5V, 9.23A (180W)

 Dimensions & Weight


USB 3.1 Gen 2
361mm (w) * 258mm (d) * 27.9mm (h)
Note that when a single USB device is plugged 2.2kg (Barebone with 48.96WH Battery)
in to a USB 3.1 Gen 2 port the data transfer
speed will be 10Gbps, however when two devic-
es are plugged in to both USB 3.1 Gen 2 ports,
this bandwidth will be shared between the ports.

Specifications 1 - 3
Introduction

Figure 1
External Locator - Top View with LCD Panel Open
Top View

1. PC Camera
2. *PC Camera LED
*When the PC 3 2 1 3 3 2 1 3
camera is in use,
the LED will be
illuminated.
3. Built-In Array
Microphone
4. LCD
1.Introduction

5. Power Button 4 4
6. Keyboard
7. Touchpad &
Buttons

5 5

6
6

7
7

1 - 4 External Locator - Top View with LCD Panel Open


Introduction

External Locator - Front & Right Side Views Figure 2


Front View
1. LED Indicator

FRONT VIEW

1.Introduction
Figure 3
Right Side View
1. USB 3.1 Gen 2
RIGHT SIDE VIEW Type-A Port
2. Mini Display Port
1.2
3. Multi-in-1 Card
3 Reader
1 2 4
4. Vent

External Locator - Front & Right Side Views 1 - 5


Introduction

External Locator - Left Side & Rear View


Figure 4
Left Side View
1. Security Lock Slot
2. Vent /
3. USB 3.0 (USB 3.1 LEFT SIDE VIEW
Gen 1) Type-A
Port
4. USB 2.0 Port
5. Microphone-In 1 3 4 5 6
2
Jack
6. 2-In-1 Audio Jack
(Headphone and
1.Introduction

Microphone)

REAR VIEW

Figure 5
Rear View 1
1. Vent 2 3 4 5
2. DisplayPort 1.3
over USB 3.1 Gen
2 Type-C Port
3. HDMI-Out Port
4. RJ-45 LAN Jack
5. DC-In Jack

1 - 6 External Locator - Left Side & Rear View


Introduction

External Locator - Bottom View Figure 6


Bottom View
1. Battery
2. Vent
3. Speakers

1.Introduction
2 2

2 2

2 Overheating

To prevent your com-


puter from overhea-
3 3 ting, make sure no-
thing blocks any vent
while the computer is
in use.

External Locator - Bottom View 1 - 7


Introduction

Figure 7 Mainboard Overview - Top (Key Parts)


Mainboard Top
Key Parts

1. KBC-ITE IT8587
1.Introduction

1 - 8 Mainboard Overview - Top (Key Parts)


Introduction

Mainboard Overview - Bottom (Key Parts) Figure 8


Mainboard Bottom
Key Parts

1. Mini-Card
Connector (WLAN
Module)
2. PCH
3. GPU
4. CPU
5. Memory Slots
DDR4 SO-DIMM
6. M.2-Card

1.Introduction
Connector (SSD
Module)
3
4

1
2

6
5

Mainboard Overview - Bottom (Key Parts) 1 - 9


Introduction

Figure 9 Mainboard Overview - Top (Connectors)


Mainboard Top
Connectors

1. USB Connector
2. Keyboard Cable
Connector
3. KB LED
Connector
4. Multi-in-1 Card
Reader
5. Mini Display Port
6. USB 3.1 Gen 2
1.Introduction

Type-A Port

2 3
5

10 6
1

1 - 10 Mainboard Overview - Top (Connectors)


Introduction

Mainboard Overview - Bottom (Connectors) Figure 10


Mainboard Bottom
Connectors
11 10 9 8
1. Fan Connector
2. HDD Connector
3. Speaker Connector
4. LED Connector
5. Touchpad
7 Connector
6. LCD Connector
6 7. Battery Connector
8. DC-In Jack

1.Introduction
9. RJ-45 LAN Jack
10. HDMI-Out Port
1 11. DisplayPort 1.3
1
over USB 3.1 Gen
2 Type-C Port

3 3
4 5

Mainboard Overview - Bottom (Connectors) 1 - 11


Introduction
1.Introduction

1 - 12
Disassembly

Chapter 2: Disassembly
Overview
This chapter provides step-by-step instructions for disassembling the NH55RCQ / NH58RCQ series notebook’s parts
and subsystems. When it comes to reassembly, reverse the procedures (unless otherwise indicated).

We suggest you completely review any procedure before you take the computer apart.

Procedures such as upgrading/replacing the RAM, optical device and hard disk are included in the User’s Manual but are
repeated here for your convenience.

2.Disassembly
To make the disassembly process easier each section may have a box in the page margin. Information contained under
the figure # will give a synopsis of the sequence of procedures involved in the disassembly procedure. A box with a  
lists the relevant parts you will have after the disassembly process is complete. Note: The parts listed will be for the dis-
Information
assembly procedure listed ONLY, and not any previous disassembly step(s) required. Refer to the part list for the previ-
ous disassembly procedure. The amount of screws you should be left with will be listed here also.

A box with a  will also provide any possible helpful information. A box with a  contains warnings.

An example of these types of boxes are shown in the sidebar.



Warning

Overview 2 - 1
Disassembly

NOTE: All disassembly procedures assume that the system is turned OFF, and disconnected from any power supply (the
battery is removed too).

Maintenance Tools
The following tools are recommended when working on the notebook PC:

• M3 Philips-head screwdriver
• M2.5 Philips-head screwdriver (magnetized)
• M2 Philips-head screwdriver
• Small flat-head screwdriver
• Pair of needle-nose pliers
• Anti-static wrist-strap
2.Disassembly

Connections
Connections within the computer are one of four types:

Locking collar sockets for ribbon connectors To release these connectors, use a small flat-head screwdriver to
gently pry the locking collar away from its base. When replac-
ing the connection, make sure the connector is oriented in the
same way. The pin1 side is usually not indicated.
Pressure sockets for multi-wire connectors To release this connector type, grasp it at its head and gently
rock it from side to side as you pull it out. Do not pull on the
wires themselves. When replacing the connection, do not try to
force it. The socket only fits one way.
Pressure sockets for ribbon connectors To release these connectors, use a small pair of needle-nose pli-
ers to gently lift the connector away from its socket. When re-
placing the connection, make sure the connector is oriented in
the same way. The pin1 side is usually not indicated.
Board-to-board or multi-pin sockets To separate the boards, gently rock them from side to side as
you pull them apart. If the connection is very tight, use a small
flat-head screwdriver - use just enough force to start.

2 - 2 Overview
Disassembly

Maintenance Precautions
The following precautions are a reminder. To avoid personal injury or damage to the computer while performing a removal and/or 
replacement job, take the following precautions: Power Safety
1. Don't drop it. Perform your repairs and/or upgrades on a stable surface. If the computer falls, the case and other components Warning
could be damaged.
2. Don't overheat it. Note the proximity of any heating elements. Keep the computer out of direct sunlight. Before you undertake
3. Avoid interference. Note the proximity of any high capacity transformers, electric motors, and other strong magnetic fields. any upgrade proce-
These can hinder proper performance and damage components and/or data. You should also monitor the position of magnet- dures, make sure that
you have turned off the
ized tools (i.e. screwdrivers).
power, and discon-
4. Keep it dry. This is an electrical appliance. If water or any other liquid gets into it, the computer could be badly damaged.
nected all peripherals
5. Be careful with power. Avoid accidental shocks, discharges or explosions. and cables (including
•Before removing or servicing any part from the computer, turn the computer off and detach any power supplies. telephone lines and
•When you want to unplug the power cord or any cable/wire, be sure to disconnect it by the plug head. Do not pull on the wire. power cord). It is advis-
6. Peripherals – Turn off and detach any peripherals. able to also remove

2.Disassembly
7. Beware of static discharge. ICs, such as the CPU and main support chips, are vulnerable to static electricity. Before han- your battery in order to
dling any part in the computer, discharge any static electricity inside the computer. When handling a printed circuit board, do prevent accidentally
not use gloves or other materials which allow static electricity buildup. We suggest that you use an anti-static wrist strap turning the machine
instead. on.
8. Beware of corrosion. As you perform your job, avoid touching any connector leads. Even the cleanest hands produce oils
which can attract corrosive elements.
9. Keep your work environment clean. Tobacco smoke, dust or other air-born particulate matter is often attracted to charged
surfaces, reducing performance.
10. Keep track of the components. When removing or replacing any part, be careful not to leave small parts, such as screws,
loose inside the computer.

Cleaning
Do not apply cleaner directly to the computer, use a soft clean cloth.
Do not use volatile (petroleum distillates) or abrasive cleaners on any part of the computer.
(For Computer Models Supplied with Light Blue Cleaning Cloth) Some computer models in this series come supplied with a
light blue cleaning cloth. To clean the computer case with this cloth follow the instructions below.
• Power off the computer and peripherals.
• Disconnect the AC/DC adapter from the computer.
• Use a little water to dampen the cloth slightly.
• Clean the computer case with the cloth.
• Dry the computer with a dry cloth, or allow it time to dry before turning on.
• Reconnect the AC/DC adapter and turn the computer on.

Overview 2 - 3
Disassembly

Disassembly Steps
The following table lists the disassembly steps, and on which page to find the related information. PLEASE PERFORM
THE DISASSEMBLY STEPS IN THE ORDER INDICATED.

To remove the Battery: To remove the CCD Module:


1. Remove the battery page 2 - 5 1. Remove the battery page 2 - 5
2. Remove the HDD page 2 - 7
To remove the Keyboard: 3. Remove the CCD module page 2 - 13
1. Remove the keyboard page 2 - 6
To remove the HDD:
2.Disassembly

1. Remove the battery page 2 - 5


2. Remove the HDD page 2 - 7
To remove the System Memory:
1. Remove the battery page 2 - 5
2. Remove the HDD page 2 - 7
3. Remove the system memory page 2 - 9
To remove the M.2 SSD:
1. Remove the battery page 2 - 5
2. Remove the HDD page 2 - 7
3. Remove the SSD page 2 - 10
To remove the Wireless LAN Module:
1. Remove the battery page 2 - 5
2. Remove the HDD page 2 - 7
3. Remove the WLAN page 2 - 11

2 - 4 Disassembly Steps
Disassembly

Removing the Battery Figure 1


1. Turn the computer off, and turn it over. Battery Removal
2. Slide the latch 1 in the direction of the arrow (Figure 1a).
a. Slide the latch 1 in the
3. Slide the latch 2 in the direction of the arrow. direction of the arrow.
4. While holding the latch 2 , lift the battery 3 (Figure 1b) out of the compartment (Figure 1c). and slide the latch 2 in
the direction of the arrow.
b. Lift the battery.
a. b.
c. Remove the battery.

2.Disassembly
3
2 1

c.


3. Battery

Removing the Battery 2 - 5


Disassembly

Figure 2 Removing the Keyboard


Keyboard Removal 1. Turn off the computer, turn it over.
2. Remove screws 1 - 2 from the bottom of the computer.
a. Remove the screws from 3. Open it up with the LCD on a flat surface before pressing at point 3 to release the keyboard module (use the spe-
the bottom of the compu-
cial eject stick 4 to do this) while releasing the keyboard in the direction of the arrow 5 as shown (Figure 2a).
ter and then eject the
keyboard using a special 4. Carefully lift the keyboard 6 up, being careful not to bend the keyboard ribbon cable 7 . Disconnect the key-
eject stick to push the board ribbon cable 7 from the locking collar socket by using a flat-head screwdriver to pry the locking collar pins
keyboard out while re- 8 away from the base (Figure 2b).
leasing the keyboard as 5. Carefully lift the keyboard 6 off the computer (Figure 2c).
shown.
b. Lift the keyboard up and
disconnect the keyboard a. b.
ribbon cable from the
2.Disassembly

locking collar socket. 2 6


c. Remove the keyboard.
1
7

 8 7 8
Re-inserting the Key-
board

When re-inserting the


keyboard firstly, align the
keyboard tabs at the bot-
tom of the keyboard with
c.
the slots in the case.

5
 3
4. Eject Stick 6
6. Keyboard 4

• 2 Screws

2 - 6 Removing the Keyboard


Disassembly

Removing the Hard Disk Drive


Figure 3
The hard disk drive can be taken out to accommodate other 2.5" serial (SATA) hard disk drives with a height of 7mm HDD Assembly
(h). Follow your operating system’s installation instructions, and install all necessary drivers and utilities (as outlined in Removal
Chapter 4 of the User’s Manual) when setting up a new hard disk.
a. Remove the SD card
Hard Disk Disassembly Process cover and screws.
b. Remove the bottom
1. Turn off the computer, and remove the battery (page 2 - 5). case.
2. Remove the SD card cover 16 and screws 2 - 14 (Figure 3a). c. Locate the HDD.
3. Carefully lift the bottom case 15 up from point 16 and remove it (Figure 3b).
4. The HDD will be visible at point 17 on the mainboard (Figure 3c).

a. b.

2.Disassembly
4 6
2 3 5 7

15 16
1
14
13 8

12 11 10 9

c. 
15. Bottom Case

15 • 13 Screws
17

Removing the Hard Disk Drive 2 - 7


Disassembly

5. Remove screws 18 from the HDD assembly (Figure 4b).


Figure 4 6. Slightly lift and pull the hard disk assembly in the direction of arrow 19 (Figure 4c).
HDD Assembly 7. Lift the hard disk assembly 20 out of the bay 21 (Figure 4d).
Removal (cont’d.)
8. Remove screws 22 - 23 and bracket 24 from the hard disk 25 (Figure 4e).
9. Reverse the process to install a new hard disk (replace the bottom case by inserting at point 1 first as shown in
d. Remove the screws.
Figure 3b, do not forget to replace the screws).
e. Slightly lift and pull the
HDD in the direction of
d. e. f.
the arrow.
f. Lift the HDD assembly
out of the bay.
g. Remove the screws and
bracket from the HDD. 19
21
18
2.Disassembly

g.
 20
HDD System Warning
22
New HDD’s are blank. Before you begin
make sure:
24
You have backed up any data you want to
keep from your old HDD.
23

 25
You have all the CD-ROMs and FDDs re-
quired to install your operating system and
20. HDD Assembly programs.
24. Bracket
If you have access to the internet, down-
25. HDD
load the latest application and hardware
driver updates for the operating system you
• 3 Screws plan to install. Copy these to a removable
medium.

2 - 8 Removing the Hard Disk Drive


Disassembly

Removing the System Memory (RAM)


Figure 5
The computer has two memory sockets for 260 pin Small Outline Dual In-line Memory Modules (SO-DIMM) supporting RAM Module
DDR4 up to 2400 MHz. The main memory can be expanded up to 16GB. The total memory size is automatically detected Removal
by the POST routine once you turn on your computer.
Memory Upgrade Process a. The RAM modules
will be visible at point
1. Turn off the computer, turn it over, remove the battery (page 2 - 5). 1 on the main-
2. The RAM modules will be visible at point 1 on the mainboard (Figure 5a). board.
3. Gently pull the two release latches ( 2 & 3 ) on the sides of the memory socket in the direction indicated by the b. Pull the release lat-
arrows (Figure 5b). The RAM module 4 will pop-up (Figure 5c), and you can then remove it. ches.
c. Remove the module.
4. Pull the latches to release the second module if necessary.
5. Insert a new module (for single module only - make sure to install it in the top slot “J_DIMMB_1” as shown in Fig-

2.Disassembly
ure 5c) by holding it at about a 30° angle and fit the connectors firmly into the memory slot.
6. The module will only fit one way as defined by its pin alignment. Make sure the module is seated as far into the slot 
as it will go. DO NOT FORCE IT; it should fit without much pressure. Contact Warning
7. Press the module in and down towards the mainboard until the slot levers click into place to secure the module.
8. Replace the bottom cover and the screws (see page 2 - 7). Be careful not to touch
the metal pins on the
9. Restart the computer to allow the BIOS to register the new memory configuration as it starts up.
module’s connecting
edge. Even the clean-
a. b. c. est hands have oils
which can attract parti-
cles, and degrade the
module’s performance.

2 3

1 
4. RAM Module

Removing the System Memory (RAM) 2 - 9


Disassembly

Figure 6 Removing the M.2 SSD Module


M.2 SSD Module
Removal
M.2 SSD Module Removal Procedure
1. Turn off the computer, turn it over, remove the battery (page 2 - 5).
a. Locate the M.2 SSD. 2. The M.2 SSD module will be visible at point 1 on the mainboard (Figure 6a).
b. Remove the screw. 3. Remove the screw 2 (Figure 6b)
c. The M.2 SSD module 4. The M.2 SSD module 3 (Figure 6c) will pop-up, and you can remove it from the computer.
will pop up.
a. c.

3
2.Disassembly

3
b.

 2
3
3.M2 SSD Module

3
• 1 Screw

2 - 10 Removing the M.2 SSD Module


Disassembly

Removing the Wireless LAN Module Figure 7


Wireless LAN
1. Turn off the computer, turn it over, remove the battery (page 2 - 5).
Module Removal
2. The Wireless LAN module will be visible at point 1 on the mainboard (Figure 7a).
3. Remove the mylar cover 2 (Figure 7b).
a. Locate the WLAN.
4. Carefully disconnect the cables 3 & 4 , and then remove the screw 5 (Figure 7c) b. Remove the mylar cov-
5. The Wireless LAN module 6 (Figure 7d) will pop-up, and you can remove it from the computer. er.
6. Reverse the process to install a new module (do not forget to replace the mylar and screws while making sure the c. Disconnect the cables
wire are properly placed). and remove the screw.
d. The WLAN module will
pop up.
a. b. c.

Note: Make sure you

2.Disassembly
reconnect the antenna
3
cable to the “1 + 2”
2 4 socket (Figure 7b).
1 5

d.


6 6 2.Mylar Cover
6.Wireless LAN Module

• 1 Screw

Removing the Wireless LAN Module 2 - 11


Disassembly

Wireless LAN, Combo Module Cables


Note that the cables for connecting to the antennae on WLAN, WLAN & Bluetooth Combo modules are not labelled.
The cables/covers (each cable will have either a black or transparent cable cover) are color coded for identification as
outlined in the table below.

Antenna Cable Cover


Module Type Cable Color
Type Type

WLAN/WLAN & Bluetooth WM 1 Black Transparent


Combo WM 2 Black White
2.Disassembly

Cable 1 is usually connected to antenna 1 on the module, and cable 2 to antenna 2.

2 - 12 Wireless LAN, Combo Module Cables


Disassembly

Removing the CCD Figure 8


CCD Removal
1. Turn off the computer, turn it over to remove the battery (page 2 - 5).
2. Lay the computer down on a flat surface with the top case up forming a 90 degree angle.
a. Carefully release the in-
3. Carefully run your fingers around the inner frame of the LCD panel to lift at points 1 - 4 as indicated by the ner frame of the LCD
arrows (Figure 8a). panel at the points indi-
4. Remove the LCD front cover 5 (Figure 8b). cated by the arrows.
b. Remove the LCD front
a. cover.

2.Disassembly
2 3

b.


5. LCD Front Cover

Removing the CCD 2 - 13


Disassembly

Figure 9 5. Disconnect the cable 6 from the locking collar socket by using a flat-head screwdriver to pry the locking collar
CCD Removal pins 7 away from the base (Figure 9c).
(cont’d) 6. Remove the CCD module 8 (Figure 9d).
7. Reverse the process to install a new CCD module.
c. Disconnect the cable
from the locking collar c.
socket.
d. Remove the CCD mod-
ule.
6

7
2.Disassembly

d.
8


8. CCD Module

2 - 14 Removing the CCD


Appendix A:Part Lists
This appendix breaks down the NH55RCQ / NH58RCQ series notebook’s construction into a series of illustrations. The
component part numbers are indicated in the tables opposite the drawings.

Note: This section indicates the manufacturer’s part numbers. Your organization may use a different system, so be sure
to cross-check any relevant documentation.

Note: Some assemblies may have parts in common (especially screws). However, the part lists DO NOT indicate the
total number of duplicated parts used.

Note: Be sure to check any update notices. The parts shown in these illustrations are appropriate for the system at the

A.Part Lists
time of publication. Over the product life, some parts may be improved or re-configured, resulting in new part numbers.

A - 1
Part List Illustration Location
The following table indicates where to find the appropriate part list illustration.
Table A - 1
Part List Illustration
Part NH55RCQ NH58RCQ
Location
Top page A - 3
Top without FP page A - 4
Bottom page A - 5
Main Board page A - 6
HDD page A - 7
A.Part Lists

LCD page A - 8 page A - 9

A - 2
Top

Figure A - 1

A.Part Lists
Top

Top A - 3
Top without FP

Figure 2
A.Part Lists

Top without FP

A - 4 Top without FP
Bottom

Figure A - 3
Bottom

A.Part Lists
Bottom A - 5
Main Board

Figure A - 4
Main Board
A.Part Lists

A - 6 Main Board
HDD

Figure A - 5
HDD

A.Part Lists
HDD A - 7
LCD (NH55RCQ)

Figure A - 6
A.Part Lists

LCD (NH55RCQ)

A - 8 LCD (NH55RCQ)
LCD (NH58RCQ)

Figure A - 7
LCD (NH58RCQ)

A.Part Lists
LCD (NH58RCQ) A - 9
A.Part Lists

A - 10
Schematic Diagrams

Appendix B: Schematic Diagrams


This appendix has circuit diagrams of the NH55RCQ / NH58RCQ notebook’s PCB’s. The following table indicates
where to find the appropriate schematic diagram.

Diagram - Page Diagram - Page Diagram - Page


System Block Diagram - Page B - 2 GPU NVVDD, FBVDDQ - Page B - 26 5V, 5VS, 3.3V, 3.3VS - Page B - 50 Table B - 1
Processor 1/6 - Page B - 3 GPU GND - Page B - 27 VDD1.05V, VCCIO - Page B - 51 SCHEMATIC
Processor 2/6 - Page B - 4 mDP - Page B - 28 VDD3, VDD5 - Page B - 52 DIAGRAMS

B.Schematic Diagrams
Processor 3/6 - Page B - 5 mDP - Page B - 29 DDR 1.2V / 0.6VS, 2.5V - Page B - 53

Processor 4/6 - Page B - 6 Panel, Inverter - Page B - 30 VCore Output Stage - Page B - 54

Processor 5/6 - Page B - 7 HDMI - Page B - 31 VCC_Core & VCCGT - Page B - 55

Processor 6/6 - Page B - 8 PCH 1/9 - Page B - 32 1.05DX_VCCSTG/VCCSFR_OC - Page B - 56

DDR4 CHA SO-DIMM - Page B - 9 PCH 2/9 - Page B - 33 VCCGT & VCCSA Output Stage - Page B - 57

DDR4 CHB SO-DIMM - Page B - 10 PCH 3/9 - Page B - 34 AC_In, Charger - Page B - 58 
VGA PCI Express - Page B - 11 PCH 4/9 - Page B - 35 NVVDD1 - Page B - 59
Version Note
GPU Frame Buffer Partition - Page B - 12 PCH 5/9 - Page B - 36 NVVDD2 - Page B - 60
The schematic dia-
Frame Buffer A - Page B - 13 PCH 6/9 - Page B - 37 PEX_VDD - Page B - 61
grams in this chapter
Frame Buffer A - Page B - 14 PCH 7/9 - Page B - 38 FBVDDQ - Page B - 62 are based upon ver-
Frame Buffer B - Page B - 15 PCH 8/9 - Page B - 39 1V8_RUN/AON - Page B - 63 sion 6-7P-NH506-003.
Frame Buffer B - Page B - 16 PCH 9/9 - Page B - 40 Audio Board - Page B - 64 If your mainboard (or
other boards) are a lat-
Frame Buffer C/D - Page B - 17 M.2 Card - Page B - 41 NH50 PW Board - Page B - 65
er version, please
Frame Buffer C - Page B - 18 M.2 WLAN+BT - Page B - 42 Hall Sensor Board - Page B - 66 check with the Service
Frame Buffer C - Page B - 19 USB Charger - Page B - 43 Click Board - Page B - 67 Center for updated di-
GPU Decoupling 1 - Page B - 20 Card Reader / LAN RTL8411B - Page B - 44 LED Board - Page B - 68
agrams (if required).
GPU Decoupling 2 - Page B - 21 HDD, Click TP, Audio, Hall Con. - Page B - 45 NH70 PW Board - Page B - 69

Straps and XTAL - Page B - 22 LED, CCD, TPM, Power SW Con. - Page B - 46 Power Sequence - Page B - 70

IFP I/O Interface - Page B - 23 Audio Codec - Page B - 47 USB Type-C - Page B - 71

Misc - GPIO, I2C and ROM - Page B - 24 KBC-ITE IT8587 - Page B - 48 PD Controller ANX7411 - Page B - 72

NVIDIA Power Sequence - Page B - 25 RGB KB Only - Page B - 49 PER KEY Board - Page B - 73

B - 1
Schematic Diagrams

System Block Diagram


5 4 3 2 1

VDD3,VDD5
SHEET 51 NH50ED System Block Diagram (Coffee lake)
GPU NVVDD
nVIDIA
Nvidia
N18E-G1 -RAM SIZE 6GB DDR6 2 VIA:3"~8"
SHEET 58,59
PCIE*16
4 VIA:3"~9" Coffee Lake-H
D
5V,3.3V,5VS,3.3VS
SHEET 49
SHEET 10,11,12, CFL-H 62 45W D
13,14,15,16,17,18,19,20,21,22,23,24,25,26 PANEL Connector
1 vias <5"
2152 Balls SHEET 29
1.05V, VCCIO
SHEET 50
Mini DP(iGPU) <10" (4 VIA) BGA1440
PS8330 28x42mm 2133 MHz
VCCGT/VCORE Output stage SHEET 27 SHEET 2,3,4,5,6,7
DDR4 /1.2 DDR4
VCC_CORE & VCCGT Power: 1.05V.1.5V, <4.7"
SHEET 53,54 HDMI(dGPU)
<6.5" (3 VIA)
3.3V,VCORE(VR12.5)
B.Schematic Diagrams

SHEET 30
VDDQ(1.2V),VTT_MEM(0.6V) SYSTEM SMBUS 1866/2133 MHz
SHEET 52 GEN 3 DMI*4 0.1"~13 DDR4 / 1.2V
DP_E ANX7440 2 vias 1" ~ 7" DDR4 DDR4
USB3.1 GEN2 SO-DIMMA SO-DIMMB
1.05DX_VCCSTG USB2.0 PORT3 SHEET 27
SHEET 8 SHEET 9
SHEET 55
(USB3.1 PORT3,4)

Sheet 1 of 73 SHEET 42 ANX7411 H Platform


VCCSA TYPE-C
C
SHEET 56
USB3.1 GEN2 SHEET 30 Controller C

System Block SMB BUS Hub (CNL-H)


3.3VA/VCCSFR_OC/VCCST TOUCH PAD HM370
Diagram SHEET 50
CLICK BOARD SPI
AUDIO BOARD
USB3.0 USB2.0
SHEET 44
AC_IN Charger SHEET 31
TPM 2.0 25x24mm USB2.0 PORT5
SHEET 57 Optional USB2.0 PORT6
SHEET 44
874 Ball FCBGA MIC
IN
HP
OUT
(USB3.0 PORT5)
32.768 KHz
NH50ED 5IN1 6-7P-xxxxxxx
EC
SHEET 63

MAIN BOARD (NH50) LPC SHEET 31,32,33,34,35,36,37,38,39


ITE 8587
6-71-xxxxxxx 0.5"~11" 33 MHz
SHEET 2~61 128pins LQFP
BOM: xxx Azalia Codec
14*14*1.6mm EC
BIOS ALC293D SPK-L & SPK-R
AUDIO BOARD SHEET 47 SPI
SHEET 44 SPI SHEET 77 SHEET 77
PHONE JACK x2;USB2.0 x1;USB3.0 x1 SHEET 30 <14"
6-71-xxxxxxxx EC SMBUS AZALIA LINK 24 MHz
B BOM:xxx SHEET 62 INT. K/B B

SHEET 47
NH50 POWER SWITCH BOARD THERMAL SMART SMART PCIE 100 MHz
6-71-xxxxxxxx SENSOR FAN BATTERY Tx 3VIA 4VIA
BOM:xxx AC-IN
CNVI Rx 2VIA
SHEET 63 2.5"~8"
2.5"~9"
PER-KEY
IT8295 32.768KHz

480 Mbps
SHEET 2 SHEET 47 SHEET 57 NGFF E Key REALTEK
NH50 LED BOARD

10 Gbps
USB2.0

USB3.1 GEN2
SHEET 74 25
6-71-xxxxxxxx M.2 WLAN+BT RTL8411B MHz
SHEET 66 USB2.0 USB2.0 PORT14 LAN CARD READER
BOM:xxx SATA I/II/III 6.0Gb/s 2 vias 3"~7.5"
PCIE PORT 14 PCIE PORT 15
SHEET 41
NH50 CLICK BOARD 3VIA SHEET 43
6-71-xxxxxxxx 3" ~ 12" 3VIA
SHEET 65 SATA SATA
BOM:xxx 5"
NGFF M Key NGFF M Key
3VIA 2VIA PCIE 4X SSD PCIE 4X SSD RJ-45 6IN1
3" ~ 12" 3"~7" PCIE PCIE SHEET 43 SOCKET
(Optional charger) PORT PORT SHEET 43
A 17,18,19,20 9,10,11,12 A
SATA HDD CCD +D-Mic USB2.0 PORT1 SHEET 39 SHEET 40
SATA III PORT4 USB2.0 PORT8 (USB3.1 PORT1)
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
SHEET 42
SHEET 44 SHEET 44 TYPE-A
Title
USB3.1 GEN2 [01]BLOCK DIAGRAM
Size Document Number Rev
A3 SCHEMATIC1 6-7P-NH506-002 D02

Date: W ednesday, December 05, 2018 Sheet 1 of 78


5 4 3 2 1

B - 2 System Block Diagram


Schematic Diagrams

Processor 1/6
5 4 3 2 1

?
?
U32C
? PEG_TX_0
10 PEG_RX0 E25 B25 C996 0.22u_10V_X5R_04
PEG_RXP_0 PEG_TXP_0 PEG_TX#_0 PEG_TX0 10
10 PEG_RX#0 D25 A25 C995 0.22u_10V_X5R_04
PEG_RXN_0 PEG_TXN_0 PEG_TX#0 10
E24 B24 PEG_TX_1 C994 0.22u_10V_X5R_04
10 PEG_RX1
F24 PEG_RXP_1 PEG_TXP_1 C24 PEG_TX#_1 C1001 0.22u_10V_X5R_04
PEG_TX1 10 6-36-00180-250
10 PEG_RX#1 PEG_RXN_1 PEG_TXN_1 PEG_TX#1 10
E23 B23 PEG_TX_2 C1006 0.22u_10V_X5R_04
CPU HOLD
10 PEG_RX2 PEG_RXP_2 PEG_TXP_2 PEG_TX#_2 PEG_TX2 10
10 PEG_RX#2 D23 A23 C1005 0.22u_10V_X5R_04
PEG_RXN_2 PEG_TXN_2 PEG_TX#2 10
D E22 B22 PEG_TX_3 C1002 0.22u_10V_X5R_04 H3 H1 H2 H6 D
10 PEG_RX3 PEG_RXP_3 PEG_TXP_3 PEG_TX#_3 PEG_TX3 10
10 PEG_RX#3 F22 C22 C1003 0.22u_10V_X5R_04 H5_7D3_7 H5_7D3_7 H5_7D3_7 H5_7D3_7
PEG_RXN_3 PEG_TXN_3 PEG_TX#3 10
E21 B21 PEG_TX_4 C1008 0.22u_10V_X5R_04
10 PEG_RX4 PEG_RXP_4 PEG_TXP_4 PEG_TX#_4 PEG_TX4 10
10 PEG_RX#4 D21 A21 C1007 0.22u_10V_X5R_04
PEG_RXN_4 PEG_TXN_4 PEG_TX#4 10
E20 B20 PEG_TX_5 C1004 0.22u_10V_X5R_04
10 PEG_RX5 PEG_RXP_5 PEG_TXP_5 PEG_TX#_5 PEG_TX5 10
10 PEG_RX#5 F20 C20 C1020 0.22u_10V_X5R_04
PEG_RXN_5 PEG_TXN_5 PEG_TX#5 10
E19 B19 PEG_TX_6 C1025 0.22u_10V_X5R_04
10 PEG_RX6 PEG_RXP_6 PEG_TXP_6 PEG_TX#_6 PEG_TX6 10
10 PEG_RX#6 D19 A19 C1024 0.22u_10V_X5R_04
PEG_RXN_6 PEG_TXN_6 PEG_TX#6 10
E18 B18 PEG_TX_7 C1021 0.22u_10V_X5R_04
10 PEG_RX7 PEG_RXP_7 PEG_TXP_7 PEG_TX#_7 PEG_TX7 10
10 PEG_RX#7 F18 C18 C1022 0.22u_10V_X5R_04
PEG_RXN_7 PEG_TXN_7 PEG_TX#7 10
D17 A17
E17 PEG_RXP_8 PEG_TXP_8 B17
PEG_RXN_8 PEG_TXN_8

B.Schematic Diagrams
F16 C16
E16 PEG_RXP_9 PEG_TXP_9 B16
PEG_RXN_9 PEG_TXN_9
D15 A15
E15 PEG_RXP_10 PEG_TXP_10 B15
PEG_RXN_10 PEG_TXN_10
F14 C14
E14 PEG_RXP_11 PEG_TXP_11 B14 3.3V
PEG_RXN_11 PEG_TXN_11
D13
E13 PEG_RXP_12
PEG_RXN_12
PEG_TXP_12
PEG_TXN_12
A13
B13
PLACE NEAR CPU
C C

2
F12 C12
E12 PEG_RXP_13 PEG_TXP_13 B12 RT1
PEG_RXN_13 PEG_TXN_13
EW TF02-104F4F-N
D11 A11

1
E11 PEG_RXP_14 PEG_TXP_14 B11

F10
E10
PEG_RXN_14

PEG_RXP_15
PEG_TXN_14

PEG_TXP_15
C10
B10 R162
THERM_VOLT 47
Sheet 2 of 73
PEG_RXN_15 PEG_TXN_15

VCCIO
R241
PEG_COMP G2
PEG_RCOMP
20K_1%_04
Processor 1/6
24.9_1%_04

D8 B8
32 DMI_IT_MR_0_DP DMI_RXP_0 DMI_TXP_0 DMI_MT_IR_0_DP 32
E8 A8
32 DMI_IT_MR_0_DN DMI_RXN_0 DMI_TXN_0 DMI_MT_IR_0_DN 32
E6 C6
32 DMI_IT_MR_1_DP DMI_RXP_1 DMI_TXP_1 DMI_MT_IR_1_DP 32
F6 B6
32 DMI_IT_MR_1_DN DMI_RXN_1 DMI_TXN_1 DMI_MT_IR_1_DN 32
D5 B5
32 DMI_IT_MR_2_DP DMI_RXP_2 DMI_TXP_2 DMI_MT_IR_2_DP 32
E5 A5
32 DMI_IT_MR_2_DN DMI_RXN_2 DMI_TXN_2 DMI_MT_IR_2_DN 32
J8 D4
32 DMI_IT_MR_3_DP DMI_RXP_3 DMI_TXP_3 DMI_MT_IR_3_DP 32
32 DMI_IT_MR_3_DN ? J9 B4
DMI_MT_IR_3_DN 32
? DMI_RXN_3 DMI_TXN_3

B CFL_H_62_INT_IP_CRB_CFLH/BGA B
U32D 3 OF 13 ?
?

K36 D29
27 IGPU_LANE0P DDI1_TXP_0 EDP_TXP_0 EDP_TXP_0 29
K37 E29
27 IGPU_LANE0N DDI1_TXN_0 EDP_TXN_0 EDP_TXN_0 29
J35 F28
27 IGPU_LANE1P DDI1_TXP_1 EDP_TXP_1 EDP_TXP_1 29
J34 E28
27 IGPU_LANE1N
H37 DDI1_TXN_1 EDP_TXN_1 A29
EDP_TXN_1 29 EDP to Panel
27 IGPU_LANE2P DDI1_TXP_2 EDP_TXP_2 EDP_TXP_2 29
ŅŅŊġ ŕŐġ ŮŅő 27 IGPU_LANE2N
H36
J37 DDI1_TXN_2 EDP_TXN_2
B29
C28
EDP_TXN_2 29 (support 4K Panel)
27 IGPU_LANE3P DDI1_TXP_3 EDP_TXP_3 EDP_TXP_3 29
J38 B28
27 IGPU_LANE3N DDI1_TXN_3 EDP_TXN_3 EDP_TXN_3 29
D27 C26
27 IGPU_AUX_CH_P DDI1_AUXP EDP_AUXP EDP_AUXP 29
E27 B26
27 IGPU_AUX_CH_N DDI1_AUXN EDP_AUXN EDP_AUXN 29 EDP
H34
DDI2_TXP_0
ʼnŅŎŊġ IJįĵţ H33
F37 DDI2_TXN_0 A33 EDP_DISP_UTIL
G38 DDI2_TXP_1 EDP_DISP_UTIL
F34 DDI2_TXN_1
F35 DDI2_TXP_2 D37 EDP_RCOMP R531 24.9_1%_04
DDI2_TXN_2 DISP_RCOMP VCCIO
E37
DDI2_TXP_3
Width = 12mil CLOSE TO CPU
E36 Space = 25mil
DDI2_TXN_3
lengh = 100mil(max)
F26
E26 DDI2_AUXP
DDI2_AUXN
A
C34 A
D34 DDI3_TXP_0
B36 DDI3_TXN_0
DDI3_TXP_1 3.3V 24,29,42,44,49,50,52,53,56,59,60,61,72,73
B34
DDI3_TXN_1 VCCIO 6,50
F33

ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
E33 DDI3_TXP_2
C33 DDI3_TXN_2
B33 DDI3_TXP_3
DDI3_TXN_3 G27 Title
A27
DDI3_AUXP
PROC_AUDIO_CLK
PROC_AUDIO_SDI
G25
AUD_AZACPU_SCLK
AUD_AZACPU_SDO_R
34
34
[02] Processor 1/7-DMI/PEG/DISPLAY
B27 G29 PROC_AUDIO_SDO R530 20_1%_04
DDI3_AUXN PROC_AUDIO_SDO AUD_AZACPU_SDI 34 Size Document Number Rev
4 of 13
CLOSE TO CPU A3 SCHEMATIC1 6-71-NH500-D02 D02
CFL_H_62_INT_IP_CRB_CFLH/BGA Date: W ednesday, December 05, 2018 Sheet 2 of 78
5 4 ? 3 2 1

Processor 1/6 B - 3
Schematic Diagrams

Processor 2/6
5 4 3 2 1

? ?
? ?
8 M_A_DQ[63:0] 9 M_B_DQ[63:0]
U32A U32B
M_A_DQ0 ? M_B_DQ0 ?
BR6 AG1 BT11 AM9
M_A_DQ1 DDR0_DQ_0/DDR0_DQ_0 DDR0_CKP_0/DDR0_CKP_0 M_A_CLK_DDR0 8 M_B_DQ1 DDR1_DQ_0/DDR0_DQ_16 DDR1_CKP_0/DDR1_CKP_0 M_B_CLK_DDR0 9
BT6 AG2 BR11 AN9
M_A_DQ2 DDR0_DQ_1/DDR0_DQ_1 DDR0_CKN_0/DDR0_CKN_0 M_A_CLK_DDR#0 8 M_B_DQ2 DDR1_DQ_1/DDR0_DQ_17 DDR1_CKN_0/DDR1_CKN_0 M_B_CLK_DDR#0 9
BP3 AK2 BT9 AM7
M_A_DQ3 DDR0_DQ_2/DDR0_DQ_2 DDR0_CKP_1/DDR0_CKP_1 M_A_CLK_DDR1 8 M_B_DQ3 DDR1_DQ_2/DDR0_DQ_18 DDR1_CKP_1/DDR1_CKP_1 M_B_CLK_DDR1 9
BR3 AK1 BR8 AM8
M_A_DQ4 DDR0_DQ_3/DDR0_DQ_3 DDR0_CKN_1/DDR0_CKN_1 M_A_CLK_DDR#1 8 M_B_DQ4 DDR1_DQ_3/DDR0_DQ_19 DDR1_CKN_1/DDR1_CKN_1 M_B_CLK_DDR#1 9
D BN5 AL3 BP11 AM11 D
M_A_DQ5 BP6 DDR0_DQ_4/DDR0_DQ_4 NC/DDR0_CKP_2 AK3 M_B_DQ5 BN11 DDR1_DQ_4/DDR0_DQ_20 NC/DDR1_CKP_2 AM10
M_A_DQ6 BP2 DDR0_DQ_5/DDR0_DQ_5 NC/DDR0_CKN_2 AL2 M_B_DQ6 BP8 DDR1_DQ_5/DDR0_DQ_21 NC/DDR1_CKN_2 AJ10
M_A_DQ7 BN3 DDR0_DQ_6/DDR0_DQ_6 NC/DDR0_CKP_3 AL1 M_B_DQ7 BN8 DDR1_DQ_6/DDR0_DQ_22 NC/DDR1_CKP_3 AJ11
M_A_DQ8 BL4 DDR0_DQ_7/DDR0_DQ_7 NC/DDR0_CKN_3 M_B_DQ8 BL12 DDR1_DQ_7/DDR0_DQ_23 NC/DDR1_CKN_3
M_A_DQ9 BL5 DDR0_DQ_8/DDR0_DQ_8 AT1 M_B_DQ9 BL11 DDR1_DQ_8/DDR0_DQ_24 AT8
M_A_DQ10 DDR0_DQ_9/DDR0_DQ_9 DDR0_CKE_0/DDR0_CKE_0 M_A_CKE0 8 M_B_DQ10 DDR1_DQ_9/DDR0_DQ_25 DDR1_CKE_0/DDR1_CKE_0 M_B_CKE0 9
BL2 AT2 BL8 AT10
M_A_DQ11 DDR0_DQ_10/DDR0_DQ_10 DDR0_CKE_1/DDR0_CKE_1 M_A_CKE1 8 M_B_DQ11 DDR1_DQ_10/DDR0_DQ_26 DDR1_CKE_1/DDR1_CKE_1 M_B_CKE1 9
BM1 AT3 BJ8 AT7
M_A_DQ12 BK4 DDR0_DQ_11/DDR0_DQ_11 DDR0_CKE_2/DDR0_CKE_2 AT5 M_B_DQ12 BJ11 DDR1_DQ_11/DDR0_DQ_27 DDR1_CKE_2/DDR1_CKE_2 AT11
M_A_DQ13 BK5 DDR0_DQ_12/DDR0_DQ_12 DDR0_CKE_3/DDR0_CKE_3 M_B_DQ13 BJ10 DDR1_DQ_12/DDR0_DQ_28 DDR1_CKE_3/DDR1_CKE_3
M_A_DQ14 BK1 DDR0_DQ_13/DDR0_DQ_13 AD5 M_B_DQ14 BL7 DDR1_DQ_13/DDR0_DQ_29 AF11
M_A_DQ15 DDR0_DQ_14/DDR0_DQ_14 DDR0_CS#_0/DDR0_CS#_0 M_A_CS#0 8 M_B_DQ15 DDR1_DQ_14/DDR0_DQ_30 DDR1_CS#_0/DDR1_CS#_0 M_B_CS#0 9
BK2 AE2 BJ7 AE7
M_A_DQ16 DDR0_DQ_15/DDR0_DQ_15 DDR0_CS#_1/DDR0_CS#_1 M_A_CS#1 8 M_B_DQ16 DDR1_DQ_15/DDR0_DQ_31 DDR1_CS#_1/DDR1_CS#_1 M_B_CS#1 9
BG4 AD2 BG11 AF10
M_A_DQ17 BG5 DDR0_DQ_16/DDR0_DQ_32 NC/DDR0_CS#_2 AE5 M_B_DQ17 BG10 DDR1_DQ_16/DDR0_DQ_48 NC/DDR1_CS#_2 AE10
M_A_DQ18 BF4 DDR0_DQ_17/DDR0_DQ_33 NC/DDR0_CS#_3 M_B_DQ18 BG8 DDR1_DQ_17/DDR0_DQ_49 NC/DDR1_CS#_3
M_A_DQ19 BF5 DDR0_DQ_18/DDR0_DQ_34 AD3 M_B_DQ19 BF8 DDR1_DQ_18/DDR0_DQ_50 AF7
M_A_DQ20 DDR0_DQ_19/DDR0_DQ_35 DDR0_ODT_0/DDR0_ODT_0 M_A_ODT0 8 M_B_DQ20 DDR1_DQ_19/DDR0_DQ_51 DDR1_ODT_0/DDR1_ODT_0 M_B_ODT0 9
B.Schematic Diagrams

BG2 AE4 BF11 AE8


M_A_DQ21 DDR0_DQ_20/DDR0_DQ_36 NC/DDR0_ODT_1 M_A_ODT1 8 M_B_DQ21 DDR1_DQ_20/DDR0_DQ_52 NC/DDR1_ODT_1 M_B_ODT1 9
BG1 AE1 BF10 AE9
M_A_DQ22 BF1 DDR0_DQ_21/DDR0_DQ_37 NC/DDR0_ODT_2 AD4 M_B_DQ22 BG7 DDR1_DQ_21/DDR0_DQ_53 NC/DDR1_ODT_2 AE11
M_A_DQ23 BF2 DDR0_DQ_22/DDR0_DQ_38 NC/DDR0_ODT_3 M_B_DQ23 BF7 DDR1_DQ_22/DDR0_DQ_54 NC/DDR1_ODT_3
M_A_DQ24 BD2 DDR0_DQ_23/DDR0_DQ_39 AH5 M_B_DQ24 BB11 DDR1_DQ_23/DDR0_DQ_55 AH10
M_A_DQ25 DDR0_DQ_24/DDR0_DQ_40 DDR0_CAB_4/DDR0_BA_0 M_A_BA0 8 M_B_DQ25 DDR1_DQ_24/DDR0_DQ_56 DDR1_CAB_3/DDR1_MA_16 M_B_RAS# 9
BD1 AH1 BC11 AH11
M_A_DQ26 DDR0_DQ_25/DDR0_DQ_41 DDR0_CAB_6/DDR0_BA_1 M_A_BA1 8 M_B_DQ26 DDR1_DQ_25/DDR0_DQ_57 DDR1_CAB_2/DDR1_MA_14 M_B_W E# 9
BC4 AU1 BB8 AF8
M_A_DQ27 DDR0_DQ_26/DDR0_DQ_42 DDR0_CAA_5/DDR0_BG_0 M_A_BG0 8 M_B_DQ27 DDR1_DQ_26/DDR0_DQ_58 DDR1_CAB_1/DDR1_MA_15 M_B_CAS# 9
BC5 BC8
M_A_DQ28 BD5 DDR0_DQ_27/DDR0_DQ_43 AH4 M_B_DQ28 BC10 DDR1_DQ_27/DDR0_DQ_59 AH8
DDR0_DQ_28/DDR0_DQ_44 DDR0_CAB_3/DDR0_MA_16 M_A_RAS# 8 DDR1_DQ_28/DDR0_DQ_60 DDR1_CAB_4/DDR1_BA_0 M_B_BA0 9

Sheet 3 of 73 M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
BD4
BC1
BC2
AB1
DDR0_DQ_29/DDR0_DQ_45
DDR0_DQ_30/DDR0_DQ_46
DDR0_DQ_31/DDR0_DQ_47
DDR0_CAB_2/DDR0_MA_14
DDR0_CAB_1/DDR0_MA_15
AG4
AD1

AH3
M_A_W E#
M_A_CAS#
8
8
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
BB10
BC7
BB7
AA11
DDR1_DQ_29/DDR0_DQ_61
DDR1_DQ_30/DDR0_DQ_62
DDR1_DQ_31/DDR0_DQ_63
DDR1_CAB_6/DDR1_BA_1
DDR1_CAA_5/DDR1_BG_0
AH9
AR9

AJ9
M_B_BA1
M_B_BG0
9
9

M_A_A0 8 M_B_A0 9
Processor 2/6 C M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
AB2
AA4
AA5
DDR0_DQ_32/DDR1_DQ_0
DDR0_DQ_33/DDR1_DQ_1
DDR0_DQ_34/DDR1_DQ_2
DDR0_DQ_35/DDR1_DQ_3
DDR0_CAB_9/DDR0_MA_0
DDR0_CAB_8/DDR0_MA_1
DDR0_CAB_5/DDR0_MA_2
NC/DDR0_MA_3
AP4
AN4
AP5
M_A_A1
M_A_A2
M_A_A3
8
8
8
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
AA10
AC11
AC10
DDR1_DQ_32/DDR1_DQ_16
DDR1_DQ_33/DDR1_DQ_17
DDR1_DQ_34/DDR1_DQ_18
DDR1_DQ_35/DDR1_DQ_19
DDR1_CAB_9/DDR1_MA_0
DDR1_CAB_8/DDR1_MA_1
DDR1_CAB_5/DDR1_MA_2
NC/DDR1_MA_3
AK6
AK5
AL5
M_B_A1
M_B_A2
M_B_A3
9
9
9
C

AB5 AP2 AA7 AL6


M_A_DQ37 DDR0_DQ_36/DDR1_DQ_4 NC/DDR0_MA_4 M_A_A4 8 M_B_DQ37 DDR1_DQ_36/DDR1_DQ_20 NC/DDR1_MA_4 M_B_A4 9
AB4 AP1 AA8 AM6
M_A_DQ38 DDR0_DQ_37/DDR1_DQ_5 DDR0_CAA_0/DDR0_MA_5 M_A_A5 8 M_B_DQ38 DDR1_DQ_37/DDR1_DQ_21 DDR1_CAA_0/DDR1_MA_5 M_B_A5 9
AA2 AP3 AC8 AN7
M_A_DQ39 DDR0_DQ_38/DDR1_DQ_6 DDR0_CAA_2/DDR0_MA_6 M_A_A6 8 M_B_DQ39 DDR1_DQ_38/DDR1_DQ_22 DDR1_CAA_2/DDR1_MA_6 M_B_A6 9
AA1 AN1 AC7 AN10
M_A_DQ40 DDR0_DQ_39/DDR1_DQ_7 DDR0_CAA_4/DDR0_MA_7 M_A_A7 8 DDR1_DQ_39/DDR1_DQ_23 DDR1_CAA_4/DDR1_MA_7 M_B_A7 9
V5 AN3
M_A_DQ41 DDR0_DQ_40/DDR1_DQ_8 DDR0_CAA_3/DDR0_MA_8 M_A_A8 8 M_B_DQ40
V2 AT4 W8 AN8
M_A_DQ42 DDR0_DQ_41/DDR1_DQ_9 DDR0_CAA_1/DDR0_MA_9 M_A_A9 8 M_B_DQ41 DDR1_DQ_40/DDR1_DQ_24 DDR1_CAA_3/DDR1_MA_8 M_B_A8 9
U1 AH2 W7 AR11
M_A_DQ43 DDR0_DQ_42/DDR1_DQ_10 DDR0_CAB_7/DDR0_MA_10 M_A_A10 8 M_B_DQ42 DDR1_DQ_41/DDR1_DQ_25 DDR1_CAA_1/DDR1_MA_9 M_B_A9 9
U2 AN2 V10 AH7
M_A_DQ44 DDR0_DQ_43/DDR1_DQ_11 DDR0_CAA_7/DDR0_MA_11 M_A_A11 8 M_B_DQ43 DDR1_DQ_42/DDR1_DQ_26 DDR1_CAB_7/DDR1_MA_10 M_B_A10 9
V1 AU4 V11 AN11
M_A_DQ45 DDR0_DQ_44/DDR1_DQ_12 DDR0_CAA_6/DDR0_MA_12 M_A_A12 8 M_B_DQ44 DDR1_DQ_43/DDR1_DQ_27 DDR1_CAA_7/DDR1_MA_11 M_B_A11 9
V4 AE3 W11 AR10
M_A_DQ46 DDR0_DQ_45/DDR1_DQ_13 DDR0_CAB_0/DDR0_MA_13 M_A_A13 8 M_B_DQ45 DDR1_DQ_44/DDR1_DQ_28 DDR1_CAA_6/DDR1_MA_12 M_B_A12 9
U5 AU2 W10 AF9
M_A_DQ47 DDR0_DQ_46/DDR1_DQ_14 DDR0_CAA_9/DDR0_BG_1 M_A_BG1 8 M_B_DQ46 DDR1_DQ_45/DDR1_DQ_29 DDR1_CAB_0/DDR1_MA_13 M_B_A13 9
U4 AU3 V7 AR7
M_A_DQ48 DDR0_DQ_47/DDR1_DQ_15 DDR0_CAA_8/DDR0_ACT# M_A_ACT# 8 M_B_DQ47 DDR1_DQ_46/DDR1_DQ_30 DDR1_CAA_9/DDR1_BG_1 M_B_BG1 9
R2 V8 AT9
M_A_DQ49 DDR0_DQ_48/DDR1_DQ_32 M_B_DQ48 DDR1_DQ_47/DDR1_DQ_31 DDR1_CAA_8/DDR1_ACT# M_B_ACT# 9
P5 AG3 R11
M_A_DQ50 DDR0_DQ_49/DDR1_DQ_33 NC/DDR0_PAR DDR0_A_PARITY 8 M_B_DQ49 DDR1_DQ_48/DDR1_DQ_48
R4 AU5 P11 AJ7
M_A_DQ51 DDR0_DQ_50/DDR1_DQ_34 NC/DDR0_ALERT# DDR0_A_ALERT# 8 M_B_DQ50 DDR1_DQ_49/DDR1_DQ_49 NC/DDR1_PAR DDR1_B_PARITY 9
P4 P7 AR8
M_A_DQ52 DDR0_DQ_51/DDR1_DQ_35 M_B_DQ51 DDR1_DQ_50/DDR1_DQ_50 NC/DDR1_ALERT# DDR1_B_ALERT# 9
R5 R8
M_A_DQ53 DDR0_DQ_52/DDR1_DQ_36 M_A_DQS#[3:0] 8 DDR1_DQ_51/DDR1_DQ_51
P2 BR5 M_A_DQS#0 M_B_DQ52 R10
M_A_DQ54 DDR0_DQ_53/DDR1_DQ_37DDR0_DQSN_0/DDR0_DQSN_0 DDR1_DQ_52/DDR1_DQ_52 M_B_DQS#[3:0] 9
R1 BL3 M_A_DQS#1 M_B_DQ53 P10 BN9 M_B_DQS#0
M_A_DQ55 P1 DDR0_DQ_54/DDR1_DQ_38DDR0_DQSN_1/DDR0_DQSN_1 BG3 M_A_DQS#2 M_B_DQ54 R7 DDR1_DQ_53/DDR1_DQ_53DDR1_DQSN_0/DDR0_DQSN_2 BL9 M_B_DQS#1
M_A_DQ56 M4 DDR0_DQ_55/DDR1_DQ_39DDR0_DQSN_2/DDR0_DQSN_4 BD3 M_A_DQS#3 M_B_DQ55 P8 DDR1_DQ_54/DDR1_DQ_54DDR1_DQSN_1/DDR0_DQSN_3 BG9 M_B_DQS#2
M_A_DQ57 DDR0_DQ_56/DDR1_DQ_40DDR0_DQSN_3/DDR0_DQSN_5 M_A_DQS#[7:4] 8 DDR1_DQ_55/DDR1_DQ_55DDR1_DQSN_2/DDR0_DQSN_6
M1 AA3 M_A_DQS#4 M_B_DQ56 L11 BC9 M_B_DQS#3
M_A_DQ58 DDR0_DQ_57/DDR1_DQ_41DDR0_DQSN_4/DDR1_DQSN_0 DDR1_DQ_56/DDR1_DQ_56DDR1_DQSN_3/DDR0_DQSN_7 M_B_DQS#[7:4] 9
L4 U3 M_A_DQS#5 M_B_DQ57 M11 AC9 M_B_DQS#4
M_A_DQ59 L2 DDR0_DQ_58/DDR1_DQ_42DDR0_DQSN_5/DDR1_DQSN_1 P3 M_A_DQS#6 M_B_DQ58 L7 DDR1_DQ_57/DDR1_DQ_57DDR1_DQSN_4/DDR1_DQSN_2 W9 M_B_DQS#5
M_A_DQ60 M5 DDR0_DQ_59/DDR1_DQ_43DDR0_DQSN_6/DDR1_DQSN_4 L3 M_A_DQS#7 M_B_DQ59 M8 DDR1_DQ_58/DDR1_DQ_58DDR1_DQSN_5/DDR1_DQSN_3 R9 M_B_DQS#6
M_A_DQ61 M2 DDR0_DQ_60/DDR1_DQ_44DDR0_DQSN_7/DDR1_DQSN_5 M_B_DQ60 L10 DDR1_DQ_59/DDR1_DQ_59DDR1_DQSN_6/DDR1_DQSN_6 M9 M_B_DQS#7
B M_A_DQ62 DDR0_DQ_61/DDR1_DQ_45 M_A_DQS[3:0] 8 DDR1_DQ_60/DDR1_DQ_60DDR1_DQSN_7/DDR1_DQSN_7 B
L5 BP5 M_A_DQS0 M_B_DQ61 M10
M_A_DQ63 DDR0_DQ_62/DDR1_DQ_46DDR0_DQSP_0/DDR0_DQSP_0 DDR1_DQ_61/DDR1_DQ_61 M_B_DQS[3:0] 9
L1 BK3 M_A_DQS1 M_B_DQ62 M7 BP9 M_B_DQS0
DDR0_DQ_63/DDR1_DQ_47DDR0_DQSP_1/DDR0_DQSP_1 BF3 M_A_DQS2 M_B_DQ63 L8 DDR1_DQ_62/DDR1_DQ_62DDR1_DQSP_0/DDR0_DQSP_2 BJ9 M_B_DQS1
BA2 DDR0_DQSP_2/DDR0_DQSP_4 BC3 M_A_DQS3 DDR1_DQ_63/DDR1_DQ_63DDR1_DQSP_1/DDR0_DQSP_3 BF9 M_B_DQS2
NC/DDR0_ECC_0 DDR0_DQSP_3/DDR0_DQSP_5 M_A_DQS[7:4] 8 DDR1_DQSP_2/DDR0_DQSP_6
BA1 AB3 M_A_DQS4 AW11 BB9 M_B_DQS3
NC/DDR0_ECC_1 DDR0_DQSP_4/DDR1_DQSP_0 NC/DDR1_ECC_0 DDR1_DQSP_3/DDR0_DQSP_7 M_B_DQS[7:4] 9
AY4 V3 M_A_DQS5 AY11 AA9 M_B_DQS4
AY5 NC/DDR0_ECC_2 DDR0_DQSP_5/DDR1_DQSP_1 R3 M_A_DQS6 AY8 NC/DDR1_ECC_1 DDR1_DQSP_4/DDR1_DQSP_2 V9 M_B_DQS5
BA5 NC/DDR0_ECC_3 DDR0_DQSP_6/DDR1_DQSP_4 M3 M_A_DQS7 AW8 NC/DDR1_ECC_2 DDR1_DQSP_5/DDR1_DQSP_3 P9 M_B_DQS6
BA4 NC/DDR0_ECC_4 DDR0_DQSP_7/DDR1_DQSP_5 AY10 NC/DDR1_ECC_3 DDR1_DQSP_6/DDR1_DQSP_6 L9 M_B_DQS7
AY1 NC/DDR0_ECC_5 AY3 AW10 NC/DDR1_ECC_4 DDR1_DQSP_7/DDR1_DQSP_7
AY2 NC/DDR0_ECC_6 DDR0_DQSP_8/DDR0_DQSP_8 BA3 AY7 NC/DDR1_ECC_5 AW9
1 OF 13
NC/DDR0_ECC_7 DDR0_DQSN_8/DDR0_DQSN_8 AW7 NC/DDR1_ECC_6 DDR1_DQSP_8/DDR1_DQSP_8 AY9
NC/DDR1_ECC_7 DDR1_DQSN_8/DDR1_DQSN_8
DDR CHANNEL A

? CFL_H_62_INT_IP_CRB_CFLH/BGA
CLOSE TO CPU
R757 121_1%_04 DDR_RCOMP0 G1 BN13
DDR_RCOMP1 H1 DDR_RCOMP_0 DDR_VREF_CA DIMM_CA_CPU_VREF_A 8
R758 75_1%_04 BP13 DIMM_DQ_CPU_VREF_A
R759 100_1%_04 DDR_RCOMP2 J2 DDR_RCOMP_1 DDR0_VREF_DQ BR13
2 OF 13 DIMM_DQ_CPU_VREF_B 9
DDR_RCOMP_2 DDR1_VREF_DQ
DDR CHANNEL B

? CFL_H_62_INT_IP_CRB_CFLH/BGA

A A

ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Title
[03] Processor 3/7-DDR4
Size Document Number Rev
A3 SCHEMATIC1 6-71-NH500-D02 D02

Date: W ednesday, December 05, 2018 Sheet 3 of 78


5 4 3 2 1

B - 4 Processor 2/6
Schematic Diagrams

Processor 3/6
5 4 3 2 1

Configuration Signals: The CFG signals have a


NEAR CPU default value of '1' if not terminated on the board.
Refer to the appropriate platform design guide for
1.05V_VCCST pull-down recommendations when a logic low is
? desired.
? Ʉ CFG[0]: Stall reset sequence after PCU PLL
U32E lock until de-asserted:
— 1 = (Default) Normal Operation; No
? stall.
R122 R490 36 PCH_CPU_BCLK_R_DP B31 BN25 CFG0 T22
A32 BCLKP CFG_0 BN27 CFG_1 — 0 = Stall.
100_04 56.2_1%_04 36 PCH_CPU_BCLK_R_DN BCLKN CFG_1 BN26
T20 Ʉ CFG[1]: Reserved configuration lane.
D35 CFG_2 BN28 CFG3 Ʉ CFG[2]: PCI Express* Static x16 Lane
36 PCH_CPU_PCIBCLK_R_DP PCI_BCLKP CFG_3 T21
D C36 BR20 CFG4 R576 1K_04 Numbering Reversal. D
36 PCH_CPU_PCIBCLK_R_DN PCI_BCLKN CFG_4 BM20 CFG5 T24
— 1 = Normal operation
54 H_CPU_SVIDDAT CFG_5
54 H_CPU_SVIDALRT# 36 CPU_24MHZ_R_DP E31 BT20 CFG6 T112 — 0 = Lane numbers reversed.
CLK24P CFG_6
54 H_CPU_SVIDCLK 36 CPU_24MHZ_R_DN D31
CLK24N CFG_7
BP20 CFG7 T23 Ʉ CFG[3]: Reserved configuration lane.
CFG_8
BR23 CFG8 T110 Ʉ CFG[4]: eDP enable:
R123 BR22 CFG9 R558 *1K_04 — 1 = Disabled.
CFG_9 BT23
220_04 CFG_10 — 0 = Enabled.
BT22 CFG11
CFG_11 BM19
T111 Ʉ CFG[6:5]: PCI Express* Bifurcation
CFG_12 BR19
— 00 = 1 x8, 2 x4 PCI Express*
CFG_13 BP19 CFG14 — 01 = reserved
CFG_14 T114 — 10 = 2 x8 PCI Express*
VIDALERT# BH31 BT19 CFG15 T113
BH32 VIDALERT# CFG_15 — 11 = 1 x16 PCI Express*
BH29 VIDSCK BN23 Ʉ CFG[7]: PEG Training:
H_PROCHOT# R764 499_1%_04 PROCHOT# BR30 VIDSOUT CFG_17 BP23 — 1 = (default) PEG Train immediately
54 H_PROCHOT# PROCHOT# CFG_16 BP22 following RESET# de assertion.
BT13 CFG_19 BN22
52 DDR_VTT_PG_CTRL DDR_VTT_CNTL CFG_18 — 0 = PEG Wait for BIOS for training.
Ʉ CFG[19:8]: Reserved configuration lanes.

B.Schematic Diagrams
BR27
BPM#_0 BT27
BPM#_1 BM31
VCCST_PW RGD R555 60.4_1%_04 VCCST_PW RGD_CPU H13 BPM#_2 BT30
VCCST_PWRGD BPM#_3
R578 20_1%_04 34 H_PW RGD BT31
33 H_PM_DOW N PROCPWRGD H_TDO
33 PLTRST_CPU_N BP35 BT28 H_TDO 34
TO PCH-H R771 *12.1_1%_04 BM34 RESET# PROC_TDO BL32 H_TDI 1.05DX_VCCSTG
33 PCH_PECI 33 H_PM_SYNC PM_DOW N PM_SYNC PROC_TDI H_TMS H_TDI 34
BP31 BP28 H_TMS 34
TO EC
R775 *0402_short PECI BT34 PM_DOWN PROC_TMS BR28 H_TCK H_TMS R767 51_04
47 H_PECI PECI PROC_TCK H_TCK 34 H_TDI
C
33 PCH_THERMTRIP# J31 R121 51_04 C

35,39 H_SKTOCC_N
H_SKTOCC_N BR33
BN1
THERMTRIP#

SKTOCC#
PROC_SELECT#
PROC_TRST#
PROC_PREQ#
PROC_PRDY#
BP30
BL30
BP27
H_TRST#
H_PREQ#
H_PRDY#
H_TRST#
H_PREQ#
H_PRDY#
39
39
39
H_TDO

H_TCK
R539

R765
100_04

51_04
Sheet 4 of 73
C284
*0.1u_10V_X7R_04 BM30

AT13
CATERR#

ZVM#
CFG_RCOMP
BT25 CFG_RCOMP Processor 3/6
AW13 3.3VA
MSM# R136
AU13
AY13 RSVD1 49.9_1%_04 H_SKTOCC_N R577 100K_04
RSVD2
5 OF 13

CFL_H_62_INT_IP_CRB_CFLH/BGA
?

PCI EXPRESS STATIC LANE REVERSAL FOR ALL PEG PORTS


1.05V_VCCST
1: (DEFAULT)NORMAL OPERATION;
VCCST_PWRGD VDD3
R556 CFG2
LANE# DEFINITION MATCHES
SOCKET PIN MAP DEFINITION
0: LANE REVERSAL
1K_04
B R553 VCCST_PW RGD B

100K_04 DISPLAY PORT PRESENCE STRAP


6

SYS_PW RGD# 2 G C1019 1: DISABLED;


S Q56A *0.1u_10V_X7R_04 NO PHYSICAL DISPLAY PORT ATTACHED
1
3

D MTDK3S6R TO EMBEDDED DISPLAY PORT


29,32,47,54 ALL_SYS_PW RGD
R575 20K_04 5 G
S Q56B
CFG4 0: ENABLED;
AN EXTERNAL DISPLAY PORT DEVICE
4

MTDK3S6R IS CONNECTED TO THE EMBEDDED


C1035
DISPLAY PORT
*0.1u_10V_X7R_04
PCIE PORT BIFURCATION STRAPS

11: (Default) x16 - Device 1 functions 1 and 2 disabled


10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled
1.05DX_VCCSTG CFG[6:5] 01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
H_PROCHOT# R768 1K_04

DEFENSIVE PULL DOWN SITE


D

Q57
C1167
G 1: (Default) PEG Train immediately following xxRESETB de assertion
A
47 H_PROCHOT_EC
2SK3018S3 47p_25V_NPO_02 CFG7 0: PEG Wait for BIOS for training A
S

R579

100K_04
CAD Note: Capacitor need to be placed
close to buffer output pin ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
VCCIO 2,6,50 Title
3.3VA 31,32,33,34,37,39,45,50,55
1.05DX_VCCSTG 6,34,55
[04]Processor 4/7-CLK/JTAG/MISC
1.05V_VCCST 6,33,50,54 Size Document Number Rev
VDD3 23,24,31,32,34,37,40,41,43,45,47,48,49,50,51,54,55,57,58,59,60,61,62,65,74,77,78
A3 SCHEMATIC1 6-71-NH500-D02 D02

Date: W ednesday, December 05, 2018 Sheet 4 of 78


5 4 3 2 1

Processor 3/6 B - 5
Schematic Diagrams

Processor 4/6
5 4 3 2 1

VCORE

C460 C376 C375 C372 C373 C457 C458 C272 C371 VCORE VCORE
?
?

10u_4V_X6S_06

10u_4V_X6S_06

10u_4V_X6S_06

10u_4V_X6S_06

10u_4V_X6S_06

10u_4V_X6S_06

10u_4V_X6S_06

10u_4V_X6S_06

10u_4V_X6S_06
?
D
128A U32I
?
128A VCORE ? VCORE
D

AA13 AH13 U32J


AA31 VCC1 VCC64 AH14 128A ? 128A
AA32 VCC2 VCC65 AH29 K14 W35
AA33 VCC3 VCC66 AH30 L13 VCC1 VCC64 W36
AA34 VCC4 VCC67 AH31 L14 VCC2 VCC65 W37
AA35 VCC5 VCC68 AH32 N13 VCC3 VCC66 W38
AA36 VCC6 VCC69 AJ14 N14 VCC4 VCC67 Y29
AA37 VCC7 VCC70 AJ29 N30 VCC5 VCC68 Y30
AA38 VCC8 VCC71 AJ30 N31 VCC6 VCC69 Y31
AB29 VCC9 VCC72 AJ31 N32 VCC7 VCC70 Y32
AB30 VCC10 VCC73 AJ32 N35 VCC8 VCC71 Y33
C456 C368 C370 C455 C369 VCC11 VCC74 VCC9 VCC72
AB31 AJ33 N36 Y34
AB32 VCC12 VCC75 AJ34 N37 VCC10 VCC73 Y35

10u_4V_X6S_06

10u_4V_X6S_06

10u_4V_X6S_06

10u_4V_X6S_06
*10u_4V_X6S_06
AB35 VCC13 VCC76 AJ35 N38 VCC11 VCC74 Y36
AB36 VCC14 VCC77 AJ36 P13 VCC12 VCC75
B.Schematic Diagrams

AB37 VCC15 VCC78 AK31 P14 VCC13


AB38 VCC16 VCC79 AK32 P29 VCC14
AC13 VCC17 VCC80 AK33 P30 VCC15
AC14 VCC18 VCC81 AK34 P31 VCC16
AC29 VCC19 VCC82 AK35 P32 VCC17
AC30 VCC20 VCC83 AK36 P33 VCC18
AC31 VCC21 VCC84 AK37 P34 VCC19
AC32 VCC22 VCC85 AK38 P35 VCC20
VCC23 VCC86 VCC21

Sheet 5 of 73
AC33 AL13 P36
AC34 VCC24 VCC87 AL29 R13 VCC22
AC35 VCC25 VCC88 AL30 R31 VCC23
AC36 VCC26 VCC89 AL31 R32 VCC24
VCC27 VCC90 VCC25

Processor 4/6 C AD13


AD14
AD31
AD32
VCC28
VCC29
VCC30
VCC91
VCC92
VCC93
AL32
AL35
AL36
AL37
R33
R34
R35
R36
VCC26
VCC27
VCC28
C

AD33 VCC31 VCC94 AL38 R37 VCC29


AD34 VCC32 VCC95 AM13 R38 VCC30
AD35 VCC33 VCC96 AM14 T29 VCC31
AD36 VCC34 VCC97 AM29 T30 VCC32
AD37 VCC35 VCC98 AM30 T31 VCC33
VCORE AD38 VCC36 VCC99 AM31 T32 VCC34
AE13 VCC37 VCC100 AM32 T35 VCC35
AE14 VCC38 VCC101 AM33 T36 VCC36
AE30 VCC39 VCC102 AM34 T37 VCC37
AE31 VCC40 VCC103 AM35 T38 VCC38
C278 C274 C185 C280 C279 C275 C273 C276 C538 C539 VCC41 VCC104 VCC39
AE32 AM36 U29
AE35 VCC42 VCC105 AN13 U30 VCC40
1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04
AE36 VCC43 VCC106 AN14 U31 VCC41
AE37 VCC44 VCC107 AN31 U32 VCC42
AE38 VCC45 VCC108 AN32 U33 VCC43
AF29 VCC46 VCC109 AN33 U34 VCC44
AF30 VCC47 VCC110 AN34 U35 VCC45
AF31 VCC48 VCC111 AN35 U36 VCC46
AF32 VCC49 VCC112 AN36 V13 VCC47
AF33 VCC50 VCC113 AN37 V14 VCC48
AF34 VCC51 VCC114 AN38 V31 VCC49
AF35 VCC52 VCC115 AP13 V32 VCC50
AF36 VCC53 VCC116 AP30 V33 VCC51
AF37 VCC54 VCC117 AP31 V34 VCC52
AF38 VCC55 VCC118 AP32 V35 VCC53
B C277 C377 C186 C184 C540 VCC56 VCC119 VCC54 B
AG14 AP35 V36
AG31 VCC57 VCC120 AP36 V37 VCC55
1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04
*1u_6.3V_X6S_04

AG32 VCC58 VCC121 AP37 V38 VCC56


AG33 VCC59 VCC122 AP38 W13 VCC57
AG34 VCC60 VCC123 K13 W14 VCC58
AG35 VCC61 VCC124 W29 VCC59
AG36 VCC62 W30 VCC60
VCC63 W31 VCC61
W32 VCC62
VCC63
AG37 10 OF 13
VCC_SENSE VCC_VCORE_SENSE 54
AG38
VSS_SENSE VSS_VCORE_SENSE 54
? CFL_H_62_INT_IP_CRB_CFLH/BGA
9 OF 13

? CFL_H_62_INT_IP_CRB_CFLH/BGA

VCC_VCORE_SENSE R522 VSS_VCORE_SENSE


*49.9_1%_04

A A
VCORE 53,54

ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Title
[05] Processor 5/7-POWER1
Size Document Number Rev
A3 SCHEMATIC1 6-71-NH500-D02 D02

Date: W ednesday, December 05, 2018 Sheet 5 of 78


5 4 3 2 1

B - 6 Processor 4/6
Schematic Diagrams

Processor 5/6

5 4 3 2 1

PLACE CAP BACKSIDE


1.05V_VCCST 1.05V_VCCST
? C282 C281
VCCSA ? VDDQ

1u_6.3V_X5R_02

1u_6.3V_X5R_02
U32L
11.1A ? ?
D J30 3.3A
AA6
?
D
K29 VCCSA1 VDDQ1 AE12 U32M
VCCSA2 VDDQ2 ?
K30 AF5 place to angle
K31 VCCSA3 VDDQ3 AF6
K32 VCCSA4 VDDQ4 AG5 RSVD_TP[5] E2
K33 VCCSA5 VDDQ5 AG9 IST_TRIG E3 RSVD_TP5
K34 VCCSA6 VDDQ6 AJ12 RSVD_TP[4] E1 IST_TRIG
K35 VCCSA7 VDDQ7 AL11 RSVD_TP[3] D1 RSVD_TP4
L31 VCCSA8 VDDQ8 AP6 1.05DX_VCCSTG VCCSFR_OC RSVD_TP3
L32 VCCSA9 VDDQ9 AP7 RSVD_TP[1] BR1 BK28
L35 VCCSA10 VDDQ10 AR12 RSVD_TP[2] BT2 RSVD_TP1 RSVD11 BJ28
L36 VCCSA11 VDDQ11 AR6 RSVD_TP2 RSVD10
VCCSA12 VDDQ12 C285 C283 C535 C534
L37 AT12 BN35
L38 VCCSA13 VDDQ13 AW6 RSVD15

1u_6.3V_X6S_04
1u_6.3V_X5R_02

1u_6.3V_X5R_02
*1u_6.3V_X5R_02

B.Schematic Diagrams
M29 VCCSA14 VDDQ14 AY6 J24
M30 VCCSA15 VDDQ15 J5 H24 RSVD28
M31 VCCSA16 VDDQ16 J6 BN33 RSVD27
M32 VCCSA17 VDDQ17 K12 BL34 RSVD14
M33 VCCSA18 VDDQ18 K6 RSVD13
M34 VCCSA19 VDDQ19 L12 N29
M35 VCCSA20 VDDQ20 L6 R14 RSVD30
M36 VCCSA21 VDDQ21 R6 AE29 RSVD31
VCCIO VCCSA22 VDDQ22 T6 AA14 RSVD2
VDDQ23 W6 AP29 RSVD1
VDDQ24 Y12 AP14 RSVD5
6.4A AG12 VDDQ25 VCCSFR_OC A36 RSVD4
VCCIO1 VSS_A36

Sheet 6 of 73
G15
G17 VCCIO2 A37
G19 VCCIO3 BH13 0.13A VSS_A37
C G21 VCCIO4 VCCPLL_OC1 BJ13 H23 C
VCCIO5 VCCPLL_OC2 39 PCH_2_CPU_TRIGGER PROC_TRIGOUT PROC_TRIGIN
H15 G11 J23
Processor 5/6
R137 30.1_1%_04
VCCIO6 VCCPLL_OC3 1.05DX_VCCSTG VCCFUSEPRG 39 CPU_2_PCH_TRIGGER PROC_TRIGOUT
H16
H17 VCCIO7 H30 0.06A1.05V_VCCST F30
H19 VCCIO8 VCCST RSVD24
H20 VCCIO9 H29 R124 *28mil short-p
H21 VCCIO10 VCCSTG2 E30
H26 VCCIO11 G30 0.02A NEAR TO CPU PIN RSVD23
H27 VCCIO12 VCCSTG1
J15 VCCIO13 H28 0.15A B30 BL31
J16 VCCIO14 VCCPLL1 J28 C30 RSVD7 RSVD12 AJ8
VCCIO15 VCCPLL2 1.05V_VCCST RSVD21 RSVD3 TP_SKL_G13
J17 G13
J19 VCCIO16 RSVD25
J20 VCCIO17 M38 G3
VCCIO18 VCCSA_SENSE VCCSA_SENSE 54Raven modfiy 0726 RSVD26 TP_SKL_C38
J21 M37 J3 C38
VCCIO19 VSSSA_SENSE VSSSA_SENSE 54 RSVD29 RSVD22 TP_SKL_C1
J26 C1
J27 VCCIO20 H14 VCCIO_SENSE RSVD20 BR2 TP_SKL_BR2
VCCIO21 VCCIO_SENSE VSSIO_SENSE VCCIO_SENSE 50 TP_SKL_BR35 RSVD17 TP_SKL_BP1
J14 BR35 BP1
VSSIO_SENSE VSSIO_SENSE 50 TP_SKL_BR31 RSVD19 RSVD16 TP_SKL_B38
BR31 B38
TP_SKL_BH30 BH30 RSVD18 RSVD8 B2 TP_SKL_B2
RSVD9 RSVD6
12 OF 13
13 OF 13
? CFL_H_62_INT_IP_CRB_CFLH/BGA
CFL_H_62_INT_IP_CRB_CFLH/BGA AROUND_CPU
?

B B

PLACE CAP IN BACK SIDE


PLACE CAP BACKSIDE CPU_BACK_VCCSA
VDDQ VCCIO

VDDQ VCCSA VCCSA

C584 C581 C583 C582 C463 C464 C379


C187 C136 C188 C189 C135 C134
*22u_6.3V_X5R_06

22u_6.3V_X6S_08

*22u_6.3V_X5R_06

*22u_6.3V_X5R_06

10u_4V_X6S_06

22u_4V_X6S_06

*10u_6.3V_X5R_04
C586 C589 C580 C585 C587 C588

10u_4V_X6S_06

10u_4V_X6S_06

10u_4V_X6S_06

*10u_4V_X6S_06

1u_6.3V_X6S_04

1u_6.3V_X5R_04
10u_4V_X6S_06

10u_6.3V_X5R_06

*10u_6.3V_X5R_04

10u_6.3V_X5R_06

10u_4V_X6S_06

10u_4V_X6S_06

D02_1029_Alex
A A

8,9,34,50,52 VDDQ
2,50
54,56
VCCIO
VCCSA ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
4,34,55 1.05DX_VCCSTG Title
4,33,50,54
50 VCCSFR_OC
1.05V_VCCST
[06] Processor 6/7-POWER2
Size Document Number Rev
A3 SCHEMATIC1 6-71-NH500-D02 D02
Date: W ednesday, December 05, 2018 Sheet 6 of 78
5 4 3 2 1

Processor 5/6 B - 7
Schematic Diagrams

Processor 6/6

5 4 3 2 1

?
? ?
? ? U32H
? VCCGT VCCGT
? U32G BN4 F15
AW5 ? BJ15 BN7 VSS_325 VSS_409 F17
U32F
? VSS_163
VSS_244 VSS_326 VSS_410
A10 AK4 AY12 BJ18 BP12 F19 ?
A12 VSS_1
VSS_82 AL10 AY33 VSS_164
VSS_245 BJ22 BP14 VSS_327 VSS_411 F2 ?
A16 VSS_2
VSS_83 AL12 AY34 VSS_165
VSS_246 BJ25 BP18 VSS_328 VSS_412 F21 32A U32K
?
32A
A18 VSS_3
VSS_84 AL14 B9 VSS_166
VSS_247 BJ29 BP21 VSS_329 VSS_413 F23 AT14 BD35
A20 VSS_4
VSS_85 AL33 BA10 VSS_167
VSS_248 BJ30 BP24 VSS_330 VSS_414 F25 AT31 VCCGT1 VCCGT80 BD36
A22 VSS_5
VSS_86 AL34 BA11 VSS_168
VSS_249 BJ31 BP25 VSS_331 VSS_415 F27 AT32 VCCGT2 VCCGT81 BE31
A24 VSS_6
VSS_87 AL4 BA12 VSS_169
VSS_250 BJ32 BP26 VSS_332 VSS_416 F29 AT33 VCCGT3 VCCGT82 BE32
A26 VSS_7
VSS_88 AL7 BA37 VSS_170
VSS_251 BJ33 BP29 VSS_333 VSS_417 F3 AT34 VCCGT4 VCCGT83 BE33
A28 VSS_8
VSS_89 AL8 BA38 VSS_171
VSS_252 BJ34 BP33 VSS_334 VSS_418 F31 AT35 VCCGT5 VCCGT84 BE34
A30 VSS_9
VSS_90 AL9 BA6 VSS_172
VSS_253 BJ35 BP34 VSS_335 VSS_419 F36 AT36 VCCGT6 VCCGT85 BE35
A6 VSS_10
VSS_91 AM1 BA7 VSS_173
VSS_254 BJ36 BP7 VSS_336 VSS_420 F4 AT37 VCCGT7 VCCGT86 BE36
D VSS_11
VSS_92 VSS_174
VSS_255 VSS_337 VSS_421 VCCGT8 VCCGT87 D
A9 AM12 BA8 BK13 BR12 F5 AT38 BE37
AA12 VSS_12
VSS_93 AM2 BA9 VSS_175
VSS_256 BK14 BR14 VSS_338 VSS_422 F8 AU14 VCCGT9 VCCGT88 BE38
AA29 VSS_13
VSS_94 AM3 BB1 VSS_176
VSS_257 BK15 BR18 VSS_339 VSS_423 F9 AU29 VCCGT10 VCCGT89 BF13
AA30 VSS_14
VSS_95 AM37 BB12 VSS_177
VSS_258 BK18 BR21 VSS_340 VSS_424 G10 AU30 VCCGT11 VCCGT90 BF14
AB33 VSS_15
VSS_96 AM38 BB2 VSS_178
VSS_259 BK22 BR24 VSS_341 VSS_425 G12 AU31 VCCGT12 VCCGT91 BF29
AB34 VSS_16
VSS_97 AM4 BB29 VSS_179
VSS_260 BK25 BR25 VSS_342 VSS_426 G14 AU32 VCCGT13 VCCGT92 BF30
AB6 VSS_17
VSS_98 AM5 BB3 VSS_180
VSS_261 BK29 BR26 VSS_343 VSS_427 G16 AU35 VCCGT14 VCCGT93 BF31
AC1 VSS_18
VSS_99 AN12 BB30 VSS_181
VSS_262 BK6 BR29 VSS_344 VSS_428 G18 AU36 VCCGT15 VCCGT94 BF32
AC12 VSS_19
VSS_100 AN29 BB4 VSS_182
VSS_263 BL13 BR34 VSS_345 VSS_429 G20 AU37 VCCGT16 VCCGT95 BF35
AC2 VSS_20
VSS_101 AN30 BB5 VSS_183
VSS_264 BL14 BR36 VSS_346 VSS_430 G22 AU38 VCCGT17 VCCGT96 BF36
AC3 VSS_21
VSS_102 AN5 BB6 VSS_184
VSS_265 BL18 BR7 VSS_347 VSS_431 G23 AV29 VCCGT18 VCCGT97 BF37
AC37 VSS_22
VSS_103 AN6 BC12 VSS_185
VSS_266 BL19 BT12 VSS_348 VSS_432 G24 AV30 VCCGT19 VCCGT98 BF38
AC38 VSS_23
VSS_104 AP10 BC13 VSS_186
VSS_267 BL20 BT14 VSS_349 VSS_433 G26 AV31 VCCGT20 VCCGT99 BG29
AC4 VSS_24
VSS_105 AP11 BC14 VSS_187
VSS_268 BL21 BT18 VSS_350 VSS_434 G28 AV32 VCCGT21 VCCGT100 BG30
B.Schematic Diagrams

AC5 VSS_25
VSS_106 AP12 BC33 VSS_188
VSS_269 BL22 BT21 VSS_351 VSS_435 G4 AV33 VCCGT22 VCCGT101 BG31
AC6 VSS_26
VSS_107 AP33 BC34 VSS_189
VSS_270 BL29 BT24 VSS_352 VSS_436 G5 AV34 VCCGT23 VCCGT102 BG32
AD10 VSS_27
VSS_108 AP34 BC6 VSS_190
VSS_271 BL33 BT26 VSS_353 VSS_437 G6 AV35 VCCGT24 VCCGT103 BG33
AD11 VSS_28
VSS_109 AP8 BD10 VSS_191
VSS_272 BL35 BT29 VSS_354 VSS_438 G8 AV36 VCCGT25 VCCGT104 BG34
AD12 VSS_29
VSS_110 AP9 BD11 VSS_192
VSS_273 BL38 BT32 VSS_355 VSS_439 G9 AW14 VCCGT26 VCCGT105 BG35
AD29 VSS_30
VSS_111 AR1 BD12 VSS_193
VSS_274 BL6 BT5 VSS_356 VSS_440 H11 AW31 VCCGT27 VCCGT106 BG36
AD30 VSS_31
VSS_112 AR13 BD37 VSS_194
VSS_275 BM11 C11 VSS_357 VSS_441 H12 AW32 VCCGT28 VCCGT107 BH33
AD6 VSS_32
VSS_113 AR14 BD6 VSS_195
VSS_276 BM12 C13 VSS_358 VSS_442 H18 AW33 VCCGT29 VCCGT108 BH34
AD8 VSS_33
VSS_114 AR2 BD7 VSS_196
VSS_277 BM13 C15 VSS_359 VSS_443 H22 AW34 VCCGT30 VCCGT109 BH35
AD9 VSS_34
VSS_115 AR29 BD8 VSS_197
VSS_278 BM14 C17 VSS_360 VSS_444 H25 AW35 VCCGT31 VCCGT110 BH36
AE33 VSS_35
VSS_116 AR3 BD9 VSS_198
VSS_279 BM18 C19 VSS_361 VSS_445 H32 AW36 VCCGT32 VCCGT111 BH37
AE34 VSS_36
VSS_117 AR30 BE1 VSS_199
VSS_280 BM2 C21 VSS_362 VSS_446 H35 AW37 VCCGT33 VCCGT112 BH38
AE6 VSS_37
VSS_118 AR31 BE2 VSS_200
VSS_281 BM21 C23 VSS_363 VSS_447 J10 AW38 VCCGT34 VCCGT113 BJ16
AF1 VSS_38
VSS_119 AR32 BE29 VSS_201
VSS_282 BM22 C25 VSS_364 VSS_448 J18 AY29 VCCGT35 VCCGT114 BJ17
AF12 VSS_39
VSS_120 AR33 BE3 VSS_202
VSS_283 BM23 C27 VSS_365 VSS_449 J22 AY30 VCCGT36 VCCGT115 BJ19
AF13 VSS_40
VSS_121 AR34 BE30 VSS_203
VSS_284 BM24 C29 VSS_366 VSS_450 J25 AY31 VCCGT37 VCCGT116 BJ20
AF14 VSS_41
VSS_122 AR35 BE4 VSS_204
VSS_285 BM25 C31 VSS_367 VSS_451 J32 AY32 VCCGT38 VCCGT117 BJ21

Sheet 7 of 73 AF2
AF3
AF4
AG10
VSS_42
VSS_123
VSS_43
VSS_124
VSS_44
VSS_125
VSS_45
VSS_126
VSS_46
VSS_127
AR36
AR37
AR38
AR4
BE5
BE6
BF12
BF33
VSS_205
VSS_286
VSS_206
VSS_287
VSS_207
VSS_288
VSS_208
VSS_289
VSS_209
VSS_290
BM26
BM27
BM28
BM29
C37
C5
C8
C9
VSS_368
VSS_369
VSS_370
VSS_371
VSS_372
VSS_452
VSS_453
VSS_454
VSS_455
VSS_456
J33
J36
J4
J7
AY35
AY36
AY37
AY38
VCCGT39
VCCGT40
VCCGT41
VCCGT42
VCCGT43
VCCGT118
VCCGT119
VCCGT120
VCCGT121
VCCGT122
BJ23
BJ24
BJ26
BJ27
AG11 AR5 BF34 BM3 D10 K1 BA13 BJ37

Processor 6/6 C
AG13
AG29
AG30
AG6
VSS_47
VSS_128
VSS_48
VSS_129
VSS_49
VSS_130
VSS_50
VSS_131
VSS_51
VSS_132
AT29
AT30
AT6
AU10
BF6
BG12
BG13
BG14
VSS_210
VSS_291
VSS_211
VSS_292
VSS_212
VSS_293
VSS_213
VSS_294
VSS_214
VSS_295
BM33
BM35
BM38
BM5
D12
D14
D16
D18
VSS_373
VSS_374
VSS_375
VSS_376
VSS_377
VSS_457
VSS_458
VSS_459
VSS_460
VSS_461
K10
K11
K2
K3
BA14
BA29
BA30
BA31
VCCGT44
VCCGT45
VCCGT46
VCCGT47
VCCGT48
VCCGT123
VCCGT124
VCCGT125
VCCGT126
VCCGT127
BJ38
BK16
BK17
BK19
C

AG7 AU11 BG37 BM6 D20 K38 BA32 BK20


AG8 VSS_52
VSS_133 AU12 BG38 VSS_215
VSS_296 BM7 D22 VSS_378 VSS_462 K4 BA33 VCCGT49 VCCGT128 BK21
AH12 VSS_53
VSS_134 AU33 BG6 VSS_216
VSS_297 BM8 D24 VSS_379 VSS_463 K5 BA34 VCCGT50 VCCGT129 BK23
AH33 VSS_54
VSS_135 AU34 BH1 VSS_217
VSS_298 BM9 D26 VSS_380 VSS_464 K7 BA35 VCCGT51 VCCGT130 BK24
AH34 VSS_55
VSS_136 AU6 BH10 VSS_218
VSS_299 BN12 D28 VSS_381 VSS_465 K8 BA36 VCCGT52 VCCGT131 BK26
AH35 VSS_56
VSS_137 AU7 BH11 VSS_219
VSS_300 BN14 D3 VSS_382 VSS_466 K9 BB13 VCCGT53 VCCGT132 BK27
AH36 VSS_57
VSS_138 AU8 BH12 VSS_220
VSS_301 BN18 D30 VSS_383 VSS_467 L29 BB14 VCCGT54 VCCGT133 BL15
AH6 VSS_58
VSS_139 AU9 BH14 VSS_221
VSS_302 BN19 D33 VSS_384 VSS_468 L30 BB31 VCCGT55 VCCGT134 BL16
AJ1 VSS_59
VSS_140 AV37 BH2 VSS_222
VSS_303 BN2 D6 VSS_385 VSS_469 L33 BB32 VCCGT56 VCCGT135 BL17
AJ13 VSS_60
VSS_141 AV38 BH3 VSS_223
VSS_304 BN20 D9 VSS_386 VSS_470 L34 BB33 VCCGT57 VCCGT136 BL23
AJ2 VSS_61
VSS_142 AW1 BH4 VSS_224
VSS_305 BN21 E34 VSS_387 VSS_471 M12 BB34 VCCGT58 VCCGT137 BL24
AJ3 VSS_62
VSS_143 AW12 BH5 VSS_225
VSS_306 BN24 E35 VSS_388 VSS_472 M13 BB35 VCCGT59 VCCGT138 BL25
AJ37 VSS_63
VSS_144 AW2 BH6 VSS_226
VSS_307 BN29 E38 VSS_389 VSS_473 N10 BB36 VCCGT60 VCCGT139 BL26
AJ38 VSS_64
VSS_145 AW29 BH7 VSS_227
VSS_308 BN30 E4 VSS_390 VSS_474 N11 BB37 VCCGT61 VCCGT140 BL27
AJ4 VSS_65
VSS_146 AW3 BH8 VSS_228
VSS_309 BN31 E9 VSS_391 VSS_475 N12 BB38 VCCGT62 VCCGT141 BL28
AJ5 VSS_66
VSS_147 AW30 BH9 VSS_229
VSS_310 BN34 N3 VSS_392 VSS_476 N2 BC29 VCCGT63 VCCGT142 BL36
AJ6 VSS_67
VSS_148 AW4 T2 VSS_230
VSS_311 P38 N33 VSS_393 VSS_477 BT8 BC30 VCCGT64 VCCGT143 BL37
W4 VSS_68
VSS_149 U6 T3 VSS_231
VSS_312 P6 N34 VSS_394 VSS_478 BR9 BC31 VCCGT65 VCCGT144 BM15
W5 VSS_69
VSS_150 V12 T33 VSS_232
VSS_313 R12 N4 VSS_395 VSS_479 BC32 VCCGT66 VCCGT145 BM16
Y10 VSS_70
VSS_151 V29 T34 VSS_233
VSS_314 R29 N5 VSS_396 A3 BC35 VCCGT67 VCCGT146 BM17
Y11 VSS_71
VSS_152 V30 T4 VSS_234
VSS_315 AY14 N6 VSS_397 VSS_A3 A34 BC36 VCCGT68 VCCGT147 BM36
Y13 VSS_72
VSS_153 A14 T5 VSS_235
VSS_316 BD38 N7 VSS_398 VSS_A34 A4 BC37 VCCGT69 VCCGT148 BM37
Y14 VSS_73
VSS_154 AD7 T7 VSS_236
VSS_317 R30 N8 VSS_399 VSS_A4 B3 BC38 VCCGT70 VCCGT149 BN15
Y37 VSS_74
VSS_155 V6 T8 VSS_237
VSS_318 T1 N9 VSS_400 VSS_B3 B37 BD13 VCCGT71 VCCGT150 BN16
Y38 VSS_75
VSS_156 W1 T9 VSS_238
VSS_319 T10 P12 VSS_401 VSS_B37 BR38 BD14 VCCGT72 VCCGT151 BN17
Y7 VSS_76
VSS_157 W12 U37 VSS_239
VSS_320 T11 P37 VSS_402 VSS_BR38 BT3 BD29 VCCGT73 VCCGT152 BN36
Y8 VSS_77
VSS_158 W2 U38 VSS_240
VSS_321 T12 M14 VSS_403 VSS_BT3 BT35 BD30 VCCGT74 VCCGT153 BN37
Y9 VSS_78
VSS_159 W3 BJ12 VSS_241
VSS_322 T13 M6 VSS_404 VSS_BT35 BT36 BD31 VCCGT75 VCCGT154 BN38
AK29 VSS_79
VSS_160 W33 BJ14 VSS_242
VSS_323 T14 N1 VSS_405 VSS_BT36 BT4 BD32 VCCGT76 VCCGT155 BP15
AK30 VSS_80
VSS_161 W34 VSS_243
VSS_324 F11 VSS_406 VSS_BT4 C2 BD33 VCCGT77 VCCGT156 BP16
VSS_81
VSS_162 F13 VSS_407 VSS_C2 D38 BD34 VCCGT78 VCCGT157 BP17
7 OF 13
CFL_H_62_INT_IP_CRB_CFLH/BGA VSS_408 VSS_D38 BP37 VCCGT79 VCCGT158 BR37
6 OF 13
CFL_H_62_INT_IP_CRB_CFLH/BGA ? BP38 VCCGT159 VCCGT164 BT15
? 8 OF 13 BR15 VCCGT160 VCCGT165 BT16
? CFL_H_62_INT_IP_CRB_CFLH/BGA BR16 VCCGT161 VCCGT166 BT17
B B
BR17 VCCGT162 VCCGT167 BT37
VCCGT163 VCCGT168

AH37
VSSGT_SENSE VSSGT_SENSE 54
AH38
VCCGT_SENSE VCCGT_SENSE 54
11 OF 13
CFL_H_62_INT_IP_CRB_CFLH/BGA
?

PLACE CAP IN BACK SIDE


VCCGT
CPU_BACK_VCCGT

C271 C269 C367 C268 C366 C270

10u_4V_X6S_06

10u_4V_X6S_06
*10u_4V_X6S_06

*10u_4V_X6S_06

*10u_4V_X6S_06

*10u_4V_X6S_06
VCCGT

C363 C453 C183 C958 C953 C364 C954 C955 C956 C536 C533 C537 C957 C454 C365 C959
A A
1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04
*1u_6.3V_X6S_04

*1u_6.3V_X6S_04

*1u_6.3V_X6S_04

*1u_6.3V_X6S_04

*1u_6.3V_X6S_04

*1u_6.3V_X6S_04
VCCGT 54,56

ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Title
[07] Processor 7/7-POWER/GND
Size Document Number Rev
Custom SCHEMATIC1 6-71-NH500-D02 D02

Date: Wednesday, December 05, 2018 Sheet 7 of 78


5 4 3 2 1

B - 8 Processor 6/6
Schematic Diagrams

DDR4 CHA SO-DIMM


5 4 3 2 1

VTT_MEM

Channel A SO-DIMM 0[RAM1] RVS TYPE


H=5.2mm
VDDQ
J_DIMMA_1B
2.5V

Samuel change RVS H=4MM DIMM 137


J_DIMMA_1A

8 M_A_DQ1
M_A_DQ[63:0] 3
163
160
159
VDD19
VDD18
VTT
258

3 M_A_CLK_DDR0 CK0_T DQ0 M_A_DQ0 VDD17


139 7 154 259
3 M_A_CLK_DDR#0 CK0_C DQ1 M_A_DQ3 VDD16 VPP2
138 20 153 257
3 M_A_CLK_DDR1 CK1_T DQ2 M_A_DQ2 VDD15 VPP1
140 21 148
3 M_A_CLK_DDR#1 CK1_C DQ3 M_A_DQ4 VDD14
4 147
109 DQ4 3 M_A_DQ5 142 VDD13 3.3VS
3 M_A_CKE0 CKE0 DQ5 M_A_DQ7 VDD12
D 110 16 141 D
PLACE THE CAP WITHIN 200 MILS FROM THE SODIMM 3 M_A_CKE1 CKE1 DQ6 M_A_DQ6 VDD11
17 136 255
DDR4_DRAMRST# 149 DQ7 28 M_A_DQ9 135 VDD10 VDDSPD
9,34 DDR4_DRAMRST# 3 M_A_CS#0 S0* DQ8 M_A_DQ13 VDD9
157 29 130
3 M_A_CS#1 S1* DQ9 M_A_DQ11 VDD8
41 129 C681 C680
155 DQ10 42 M_A_DQ15 124 VDD7
3 M_A_ODT0 ODT0 DQ11 M_A_DQ8 VDD6
161 24 123 0.1u_10V_X7R_04 2.2u_6.3V_X5R_04
3 M_A_ODT1 ODT1 DQ12 M_A_DQ12 VDD5
25 118
115 DQ13 38 M_A_DQ14 117 VDD4
PLACE THE CAP CLOSE TO SODIMM 3 M_A_BG0 BG0 DQ14 VDD3
113 37 M_A_DQ10 112
DDR_VREFCA_CHA_DIMM 3 M_A_BG1 BG1 DQ15 M_A_DQ16 VDD2
150 50 111
3 M_A_BA0 BA0 DQ16 M_A_DQ21 VDD1
145 49
3 M_A_BA1 BA1 DQ17 M_A_DQ23
62 GND1
C667 DQ18 M_A_DQ22 MT1
144 63 GND2
3 M_A_A0 A0 DQ19 M_A_DQ20 MT2

B.Schematic Diagrams
133 46
*0.1u_10V_X7R_04 3 M_A_A1 A1 DQ20 M_A_DQ17 PLACE NEAR TO PIN
132 45
3 M_A_A2 A2 DQ21 M_A_DQ19
131 58 251 252
3 M_A_A3 A3 DQ22 M_A_DQ18 VSS VSS
128 59 247 248
3 M_A_A4 A4 DQ23 M_A_DQ25 VSS VSS
126 70 243 244
3 M_A_A5 A5 DQ24 M_A_DQ29 VSS VSS
127 71 239 238
3 M_A_A6 A6 DQ25 M_A_DQ31 VSS VSS
122 83 235 234
3 M_A_A7 A7 DQ26 M_A_DQ26 VSS VSS
125 84 231 230
3 M_A_A8 A8 DQ27 M_A_DQ24 VSS VSS

3
3
3 M_A_A9
M_A_A10
M_A_A11
121
146
120
119
A9
A10_AP
A11
DQ28
DQ29
DQ30
66
67
79
80
M_A_DQ28
M_A_DQ30
M_A_DQ27
227
223
217
213
VSS
VSS
VSS
VSS
VSS
VSS
226
222
218
214
Sheet 8 of 73
3 M_A_A12 A12 DQ31 VSS VSS

DDR4 CHA SO-


VDDQ 158 174 M_A_DQ32 209 210
3 M_A_A13 A13 DQ32 M_A_DQ37 VSS VSS
151 173 205 206
3 M_A_W E# A14_WE* DQ33 M_A_DQ39 VSS VSS
156 187 201 202
3 M_A_CAS# A15_CAS* DQ34 M_A_DQ34 VSS VSS
C 152 186 197 196 C
3 M_A_RAS# A16_RAS* DQ35 VSS VSS
R235
240_1%_04
3 M_A_ACT#
114
ACT*
DQ36
DQ37
DQ38
170
169
183
182
M_A_DQ36
M_A_DQ33
M_A_DQ38
M_A_DQ35
193
189
185
181
VSS
VSS
VSS
VSS
VSS
VSS
192
188
184
180
DIMM
143 DQ39 195 M_A_DQ44 175 VSS VSS 176
3 DDR0_A_PARITY PARITY DQ40 M_A_DQ40 VSS VSS
116 194 171 172
3 DDR0_A_ALERT# DIMM0_CHA_EVENT# ALERT* DQ41 M_A_DQ42 VSS VSS
134 207 167 168
DDR4_DRAMRST# 108 EVENT* DQ42 208 M_A_DQ43 107 VSS VSS 106
RESET* DQ43 191 M_A_DQ41 103 VSS VSS 102
DDR_VREFCA_CHA_DIMM 164 DQ44 190 M_A_DQ45 99 VSS VSS 98
VREFCA DQ45 203 M_A_DQ47 93 VSS VSS 94
254 DQ46 204 M_A_DQ46 89 VSS VSS 90
9,32 SMB_DATA_MAIN_DDR4 SDA DQ47 M_A_DQ48 VSS VSS
253 216 85 86
9,32 SMB_CLK_MAIN_DDR4 SCL DQ48 M_A_DQ49 VSS VSS
215 81 82
000 166
SA2
DQ49
DQ50
228 M_A_DQ54 77 VSS
VSS
VSS
VSS
78
260 229 M_A_DQ53 73 72
256 SA1 DQ51 211 M_A_DQ50 69 VSS VSS 68
SA0 DQ52 212 M_A_DQ52 65 VSS VSS 64
DQ53 224 M_A_DQ55 61 VSS VSS 60
CHA_DIMM0=000 DQ54
DQ55
225 M_A_DQ51 57 VSS
VSS
VSS
VSS
56
92 237 M_A_DQ56 51 52
CHA_DIMM1=001 91 CB0_NC DQ56 236 M_A_DQ60 47 VSS VSS 48
CB1_NC DQ57 VSS VSS
CHB_DIMM0=010 101
CB2_NC DQ58
249 M_A_DQ63
M_A_DQ62
43
VSS VSS
44
105 250 39 40
CHB_DIMM1=011 88 CB3_NC DQ59 232 M_A_DQ57 35 VSS VSS 36
87 CB4_NC DQ60 233 M_A_DQ61 31 VSS VSS 30
2.5V 100 CB5_NC DQ61 245 M_A_DQ59 27 VSS VSS 26
104 CB6_NC DQ62 246 M_A_DQ58 23 VSS VSS 22
B CB7_NC DQ63 19 VSS VSS 18 B
M_A_DQS0 M_A_DQS[3:0] 3 VSS VSS
VDDQ 12 13 15 14
C696 33 DM0*/DBI0* DQS0_T 34 M_A_DQS1 9 VSS VSS 10
54 DM1*/DBI1* DQS1_T 55 M_A_DQS2 5 VSS VSS 6
10u_6.3V_X5R_06 75 DM2*/DBI2* DQS2_T 76 M_A_DQS3 1 VSS VSS 2
DM3*/DBI3* DQS3_T M_A_DQS4 M_A_DQS[7:4] 3 VSS VSS
178 179
199 DM4*/DBI4* DQS4_T 200 M_A_DQS5
220 DM5*/DBI5* DQS5_T 221 M_A_DQS6
VTT_MEM 241 DM6*/DBI6* DQS6_T 242 M_A_DQS7 D4AR0-26001-1P40
96 DM7*/DBI7* DQS7_T 97
DM8*/DBI8* DQS8_T
M_A_DQS#[3:0] 3 VDDQ
11 M_A_DQS#0
C690 DQS0_C 32 M_A_DQS#1
DQS1_C 53 M_A_DQS#2
1u_6.3V_X5R_02 DQS2_C 74 M_A_DQS#3
DQS3_C M_A_DQS#[7:4] 3
月D I M M䪗㒢 㓦
177 M_A_DQS#4 R238
DQS4_C 198 M_A_DQS#5
DQS5_C 219 M_A_DQS#6 1K_1%_04
DQS6_C 240 M_A_DQS#7
DQS7_C 95 DDR_VREFCA_CHA_DIMM
162 DQS8_C
VDDQ 165 S2*/C0
S3*/C1 C668
R244
*0.1u_10V_X7R_04
D4AR0-26001-1P40
1K_1%_04
C651 C657 C662

10u_6.3V_X5R_06 10u_6.3V_X5R_06 10u_6.3V_X5R_06


6,9,34,50,52 VDDQ
A R242 2_1%_04 A
3 DIMM_CA_CPU_VREF_A 9,52 VTT_MEM
VDDQ 9,52 2.5V
9,23,24,27,29,30,31,32,33,34,35,36,39,40,41,43,44,45,47,49,50,54,61,74,77 3.3VS
C664

C654 C656 C650 C663 D02_1107_Alex


0.022u_25V_X7R_04
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
R239 Title
1u_6.3V_X5R_02 1u_6.3V_X5R_02 1u_6.3V_X5R_02 1u_6.3V_X5R_02
24.9_1%_04
[08] DDR4 CHA SO-DIMM_0
Size Document Number Rev
A3 SCHEMATIC1 6-71-NH500-D02 D02

Date: W ednesday, December 05, 2018 Sheet 8 of 78


5 4 3 2 1

DDR4 CHA SO-DIMM B - 9


Schematic Diagrams

DDR4 CHB SO-DIMM


5 4 3 2 1

J_DIMMB_1B VTT_MEM
STD TYPE VDDQ

Channel B SO-DIMM 0[RAM2] H=5.2mm 163


160
159
VDD19
VDD18
VTT
258
2.5V

J_DIMMB_1A 154 VDD17 259


153 VDD16 VPP2 257
PLACE THE CAP WITHIN 200 MILS FROM THE SODIMM M_B_DQ5 M_B_DQ[63:0] 3 VDD15 VPP1
137 8 148
DDR4_DRAMRST# 3 M_B_CLK_DDR0 CK0_T DQ0 M_B_DQ1 VDD14
139 7 147 3.3VS
8,34 DDR4_DRAMRST# 3 M_B_CLK_DDR#0 CK0_C DQ1 M_B_DQ7 VDD13
138 20 142
3 M_B_CLK_DDR1 CK1_T DQ2 M_B_DQ2 VDD12
140 21 141
3 M_B_CLK_DDR#1 CK1_C DQ3 M_B_DQ4 VDD11
4 136 255
109 DQ4 3 M_B_DQ0 135 VDD10 VDDSPD
D
Samuel change RVS H=8MM DIMM 3
3
M_B_CKE0
M_B_CKE1
110 CKE0
CKE1
DQ5
DQ6
DQ7
16
17
M_B_DQ6
M_B_DQ3
130
129
VDD9
VDD8
VDD7
C686 C687
D

149 28 M_B_DQ10 124


3 M_B_CS#0 S0* DQ8 M_B_DQ14 VDD6
157 29 123 0.1u_10V_X7R_04 2.2u_6.3V_X5R_04
3 M_B_CS#1 S1* DQ9 M_B_DQ12 VDD5
41 118
155 DQ10 42 M_B_DQ15 117 VDD4
3 M_B_ODT0 ODT0 DQ11 M_B_DQ8 VDD3
161 24 112
PLACE THE CAP CLOSE TO SODIMM 3 M_B_ODT1 ODT1 DQ12 M_B_DQ9 VDD2
25 111
DDR_VREFCA_CHB_DIMM 115 DQ13 38 M_B_DQ11 VDD1
3 M_B_BG0 BG0 DQ14 M_B_DQ13
113 37 GND1
3 M_B_BG1 BG1 DQ15 M_B_DQ22 MT1
150 50 GND2
3 M_B_BA0 BA0 DQ16 M_B_DQ17 MT2
B.Schematic Diagrams

C665 145 49 PLACE NEAR TO PIN


3 M_B_BA1 BA1 DQ17 M_B_DQ20
62
*0.1u_10V_X7R_04 144 DQ18 63 M_B_DQ19 251 252
3 M_B_A0 A0 DQ19 M_B_DQ18 VSS VSS
133 46 247 248
3 M_B_A1 A1 DQ20 M_B_DQ16 VSS VSS
132 45 243 244
3 M_B_A2 A2 DQ21 M_B_DQ21 VSS VSS
131 58 239 238
3 M_B_A3 A3 DQ22 M_B_DQ23 VSS VSS
128 59 235 234
3 M_B_A4 A4 DQ23 M_B_DQ30 VSS VSS
126 70 231 230
2.5V 3 M_B_A5 A5 DQ24 M_B_DQ28 VSS VSS
127 71 227 226
3 M_B_A6 A6 DQ25 VSS VSS

Sheet 9 of 73 122 83 M_B_DQ31 223 222


3 M_B_A7 A7 DQ26 M_B_DQ29 VSS VSS
125 84 217 218
3 M_B_A8 A8 DQ27 M_B_DQ27 VSS VSS
121 66 213 214
3 M_B_A9 A9 DQ28 M_B_DQ25 VSS VSS
146 67 209 210
3 M_B_A10 A10_AP DQ29 VSS VSS
DDR4 CHB SO- C684

1u_6.3V_X5R_02 VDDQ
3
3
3
M_B_A11
M_B_A12
M_B_A13
120
119
158
151
A11
A12
A13
DQ30
DQ31
DQ32
79
80
174
173
M_B_DQ24
M_B_DQ26
M_B_DQ35
M_B_DQ38
205
201
197
193
VSS
VSS
VSS
VSS
VSS
VSS
206
202
196
192
3 M_B_W E#

DIMM C 156 A14_WE* DQ33 187 M_B_DQ37 189 VSS VSS 188 C
3 M_B_CAS# A15_CAS* DQ34 M_B_DQ36 VSS VSS
152 186 185 184
3 M_B_RAS# A16_RAS* DQ35 M_B_DQ34 VSS VSS
R234 170 181 180
DQ36 169 M_B_DQ39 175 VSS VSS 176
240_1%_04 DQ37 M_B_DQ33 VSS VSS
114 183 171 172
3 M_B_ACT# ACT* DQ38 M_B_DQ32 VSS VSS
182 167 168
VTT_MEM 143 DQ39 195 M_B_DQ45 107 VSS VSS 106
3 DDR1_B_PARITY PARITY DQ40 M_B_DQ41 VSS VSS
116 194 103 102
3 DDR1_B_ALERT# DIMM0_CHB_EVENT# ALERT* DQ41 M_B_DQ46 VSS VSS
134 207 99 98
DDR4_DRAMRST# 108 EVENT* DQ42 208 M_B_DQ43 93 VSS VSS 94
C688 RESET* DQ43 191 M_B_DQ44 89 VSS VSS 90
DDR_VREFCA_CHB_DIMM 164 DQ44 190 M_B_DQ40 85 VSS VSS 86
1u_6.3V_X5R_02 VREFCA DQ45 203 M_B_DQ47 81 VSS VSS 82
254 DQ46 204 M_B_DQ42 77 VSS VSS 78
8,32 SMB_DATA_MAIN_DDR4 SDA DQ47 M_B_DQ54 VSS VSS
253 216 73 72
8,32 SMB_CLK_MAIN_DDR4 SCL DQ48 M_B_DQ48 VSS VSS
215 69 68
010 166
SA2
DQ49
DQ50
228 M_B_DQ49 65 VSS
VSS
VSS
VSS
64
260 229 M_B_DQ55 61 60
3.3VS SA1 DQ51 M_B_DQ52 VSS VSS
256 211 57 56
SA0 DQ52 212 M_B_DQ51 51 VSS VSS 52
DQ53 224 M_B_DQ53 47 VSS VSS 48
CHA_DIMM0=000 DQ54 225 M_B_DQ50 43 VSS VSS 44
CHA_DIMM1=001 92 DQ55 237 M_B_DQ57 39 VSS VSS 40
91 CB0_NC DQ56 236 M_B_DQ62 35 VSS VSS 36
CHB_DIMM0=010 101 CB1_NC DQ57 249 M_B_DQ56 31 VSS VSS 30
CB2_NC DQ58 M_B_DQ63 VSS VSS
CHB_DIMM1=011 105
88 CB3_NC DQ59
250
232 M_B_DQ59
27
23 VSS VSS
26
22
87 CB4_NC DQ60 233 M_B_DQ61 19 VSS VSS 18
100 CB5_NC DQ61 245 M_B_DQ60 15 VSS VSS 14
B 104 CB6_NC DQ62 246 M_B_DQ58 9 VSS VSS 10 B
CB7_NC DQ63 5 VSS VSS 6
M_B_DQS0 M_B_DQS[3:0] 3 VSS VSS
VDDQ 12 13 1 2
33 DM0*/DBI0* DQS0_T 34 M_B_DQS1 VSS VSS
54 DM1*/DBI1* DQS1_T 55 M_B_DQS2
75 DM2*/DBI2* DQS2_T 76 M_B_DQS3
DM3*/DBI3* DQS3_T M_B_DQS4 M_B_DQS[7:4] 3
178 179 D4AR0-26001-1P80
199 DM4*/DBI4* DQS4_T 200 M_B_DQS5
220 DM5*/DBI5* DQS5_T 221 M_B_DQS6
DM6*/DBI6* DQS6_T VDDQ
241 242 M_B_DQS7
96 DM7*/DBI7* DQS7_T 97
DM8*/DBI8* DQS8_T
M_B_DQS#0 M_B_DQS#[3:0] 3
11
DQS0_C
DQS1_C
32
53
M_B_DQS#1
M_B_DQS#2
R246
1K_1%_04
月D I M M䪗㒢 㓦
DQS2_C 74 M_B_DQS#3
DQS3_C M_B_DQS#4 M_B_DQS#[7:4] 3 DDR_VREFCA_CHB_DIMM
177
DQS4_C 198 M_B_DQS#5
DQS5_C M_B_DQS#6 C666
219
DQS6_C 240 M_B_DQS#7 R247
DQS7_C *0.1u_10V_X7R_04
VDDQ 95
DQS8_C 1K_1%_04
162
165 S2*/C0
S3*/C1
R248 2_1%_04
3 DIMM_DQ_CPU_VREF_B
C642 C644 C648 C661 C652 C658 D4AR0-26001-1P80
_ C669
10u_6.3V_X5R_06 10u_6.3V_X5R_06 10u_6.3V_X5R_06 *10u_6.3V_X5R_06 10u_6.3V_X5R_06 10u_6.3V_X5R_06
0.022u_25V_X7R_04 D02_1107_Alex
A A

VDDQ R252
24.9_1%_04

C647 C660 C649 C659 C653 C655


ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Title
1u_6.3V_X5R_02 *1u_6.3V_X5R_02 1u_6.3V_X5R_02 1u_6.3V_X5R_02 1u_6.3V_X5R_02 1u_6.3V_X5R_02
8,23,24,27,29,30,31,32,33,34,35,36,39,40,41,43,44,45,47,49,50,54,61,74,77
8,52 2.5V
3.3VS
[09] DDR4 CHB SO-DIMM_0
27,30,32,44,45,47,48,49,74,77,78 5VS Size Document Number Rev
4,31,32,33,34,37,39,45,50,55
6,8,34,50,52
3.3VA
VDDQ A3 SCHEMATIC1 6-71-NH500-D02 D02
8,52 VTT_MEM Date: W ednesday, December 05, 2018 Sheet 9 of 78
5 4 3 2 1

B - 10 DDR4 CHB SO-DIMM


Schematic Diagrams

VGA PCI Express


1 2 3 4 5

NV3V3 1V8_AON

24,58 NVVDD_PWRGD
R58

10K_04
R60

*10K_04
NV PCI EXPRESS

G
Q12
D S 2SK3018S3
36 PEG_CLKREQ#

R57

*10K_04 G1A
A
1/22 PCI_EXPRESS Place between A

Place Under GPU


BK44 PEX_WAKE GPU and PS PEX_VDD
PEX_DVDD BB35
BK26 PEX_RST PEX_DVDD BB36
23,24 GPU_PEX_RST#
PEX_DVDD BC35 C242 C243 C249 C157 C212 C149 C148 C36 C35 C921 C34 C946
PEX_CLKREQ# BL26 BC36
PEX_CLKREQ PEX_DVDD

1u_4V_X6S_02

*0.47U_4V_X6S_02

1u_4V_X6S_02

*0.47u_4V_X6S_02

1u_4V_X6S_02

*0.47u_4V_X6S_02

1u_4V_X6S_02

4.7u_6.3V_X6S_06

4.7u_6.3V_X6S_06

10U_4V_X6S_06

10U_4V_X6S_06

10U_4V_X6S_06
PEX_DVDD BD33

NV_0201_LARGE

NV_0201_LARGE

NV_0201_LARGE

NV_0201_LARGE

NV_0201_LARGE

NV_0201_LARGE

NV_0201_LARGE

NV_0603

NV_0603 

NV_0603

NV_0603

NV_0603
VGA_PEXCLK BM26 BD36
36 VGA_PEXCLK PEX_REFCLK PEX_DVDD
VGA_PEXCLK# BM27
36 VGA_PEXCLK# PEX_REFCLK
PEX_CVDD BB33
PEX_RX0 BG26
2 PEG_RX0
C68 0.22u_10V_X5R_04 PEX_TX0 PEX_CVDD BC33
C69 0.22u_10V_X5R_04 PEX_RX0# BH26
2 PEG_RX#0 PEX_TX0

BL27 PEX_RX0
2 PEG_TX0 BK27 PEX_RX0
2 PEG_TX#0
C105 0.22u_10V_X5R_04 PEX_RX1 BF26
2 PEG_RX1 PEX_TX1
C108 0.22u_10V_X5R_04 PEX_RX1# BE26 BB26 C143 C213 C144 C253 C146 C239 C154 C247 C922 C931 C930
2 PEG_RX#1 PEX_TX1 PEX_HVDD
PEX_HVDD BB27

0.47U_4V_X6S_02

*0.47u_4V_X6S_02

1u_4V_X6S_02

*0.47U_4V_X6S_02

*0.47u_4V_X6S_02

1u_4V_X6S_02

1u_4V_X6S_02

1u_4V_X6S_02

4.7u_6.3V_X6S_06

22u_4V_X6S_06

22u_6.3V_X6S_08
BK29 PEX_RX1 PEX_HVDD BB29

NV_0201_LARGE

NV_0201_LARGE

NV_0201_LARGE

NV_0201_LARGE

NV_0201_LARGE

NV_0201_LARGE

NV_0201_LARGE

NV_0201_LARGE

NV_0603 

NV_0603

M-C0805
2 PEG_TX1 BL29 BB32
2 PEG_TX#1 PEX_RX1 PEX_HVDD
PEX_HVDD BC26
C70 0.22u_10V_X5R_04 PEX_RX2 BF27 BC27
2 PEG_RX2 PEX_TX2 PEX_HVDD
C71 0.22u_10V_X5R_04 PEX_RX2# BG27 BC29

B.Schematic Diagrams
2 PEG_RX#2 PEX_TX2 PEX_HVDD
PEX_HVDD BC30
BM29 PEX_RX2 PEX_HVDD BC32
2 PEG_TX2 BM30 BD27
2 PEG_TX#2 PEX_RX2 PEX_HVDD
PEX_HVDD BD30
C110 0.22u_10V_X5R_04 PEX_RX3 BG29
2 PEG_RX3 PEX_TX3
C109 0.22u_10V_X5R_04 PEX_RX3# BH29 1V8_RUN
PEX_TX3
2 PEG_RX#3
BL30 PEX_RX3
2 PEG_TX3
BK30 PEX_RX3
2 PEG_TX#3 C238 C234 C225 C155 C150 C290 C382 C384 C289 C288
PEX_RX4

Sheet 10 of 73
C72 0.22u_10V_X5R_04 BF29 PEX_TX4

1u_4V_X6S_02

1u_4V_X6S_02

*0.47u_4V_X6S_02

*0.47u_4V_X6S_02

1u_4V_X6S_02

4.7u_6.3V_X6S_06

4.7u_6.3V_X6S_06

10U_4V_X6S_06

10U_4V_X6S_06

10U_4V_X6S_06
2 PEG_RX4 PEX_RX4#

NV_0201_LARGE

NV_0201_LARGE

NV_0201_LARGE

NV_0201_LARGE

NV_0201_LARGE

NV_0603

NV_0603

NV_0603

NV_0603

NV_0603
C73 0.22u_10V_X5R_04 BE29 PEX_TX4
2 PEG_RX#4
B BK32 PEX_RX4 B
2 PEG_TX4
BL32 PEX_RX4
2 PEG_TX#4

2
2

2
PEG_RX5
PEG_RX#5

PEG_TX5
C74
C75
0.22u_10V_X5R_04
0.22u_10V_X5R_04
PEX_RX5
PEX_RX5#
BF30
BG30

BM32
BM33
PEX_TX5
PEX_TX5

PEX_RX5
PEX_PLL_HVDD BB30
VGA PCI Express
PEX_RX5
2 PEG_TX#5
PEX_RX6 BG32 C292 C228 C222 C151 C293 C169 C170 C287 C291 C286
C76 0.22u_10V_X5R_04 PEX_TX6
2 PEG_RX6 PEX_RX6# BH32
C77 0.22u_10V_X5R_04 PEX_TX6

1u_4V_X6S_02

1u_4V_X6S_02

1u_4V_X6S_02

*0.47U_4V_X6S_02

*0.47u_4V_X6S_02

*0.47u_4V_X6S_02

1U_4V_X6S_02

4.7u_6.3V_X6S_06

22u_4V_X6S_06

22u_4V_X6S_06
2 PEG_RX#6

NV_0201_LARGE

NV_0201_LARGE

NV_0201_LARGE

NV_0201_LARGE

NV_0201_LARGE

NV_0201_LARGE

NV_0201_LARGE

NV_0603

NV_0603

NV_0603
BL33 PEX_RX6
2 PEG_TX6 BK33
2 PEG_TX#6 PEX_RX6

C79 0.22u_10V_X5R_04 PEX_RX7 BF32


2 PEG_RX7 PEX_TX7
C78 0.22u_10V_X5R_04 PEX_RX7# BE32
2 PEG_RX#7 PEX_TX7

BK35 PEX_RX7
2 PEG_TX7 BL35
2 PEG_TX#7 PEX_RX7

BF33 PEX_TX8
BG33 PEX_TX8

BM35 1V8_RUN
PEX_RX8
BM36 PEX_RX8
PEX_PLL_HVDD R112 0_04
BG35 PEX_TX9 NV_0402
BH35 PEX_TX9 C231 C294 C218
BL36 PEX_RX9
6-34-T80VS-023

*0.47u_4V_X6S_02

*0.47u_4V_X6S_02

4.7u_6.3V_X6S_06
NV_0201_LARGE

NV_0201_LARGE

NV_0603 
BK36 PEX_RX9

BF35 PEX_TX10
BE35 PEX_TX10

BK38 PEX_RX10
BL38 PEX_RX10

C BF36 PEX_TX11 C
BG36 PEX_TX11

BM38 PEX_RX11
BM39 PEX_RX11

BG38 PEX_TX12
BH38 PEX_TX12
H8 H5 H4 H7
BL39 PEX_RX12 H5_7D3_7 H5_7D3_7 H5_7D3_7 H5_7D3_7
BK39 PEX_RX12

BF38 PEX_TX13
BE38 PEX_TX13

BK41 PEX_RX13
BL41 PEX_RX13

BF39 PEX_TX14
BG39 PEX_TX14

BM41 PEX_RX14
BM42 PEX_RX14

BH41 PEX_TX15
BG41 PEX_TX15

BL42 PEX_TERMP
PEX_RX15 PEX_TERMP BL44 R491 2.49K_1%_04
BK42 PEX_RX15

GND

COMMON
BGA2228
?

D D

22,60 PEX_VDD

2,24,29,42,44,49,50,52,53,56,59,60,61,72,73 3.3V
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Title
23,30,58,61,62,78 NV3V3 [10] VGA PCI Express
12,13,14,15,17,18,20,21,22,23,24,25,58,61,62,78 1V8_AON Size Document Number Rev
11,21,23,62 1V8_RUN Custom SCHEMATIC1 6-71-NH500-D02 D02

Date: Wednesday, December 05, 2018 Sheet 10 of 78


1 2 3 4 5

VGA PCI Express B - 11


Schematic Diagrams

GPU Frame Buffer Partition


1 2 3 4 5 6 7 8

G1C
G1B

PAGE3: GPU FRAME BUFFER PARTITION A/B


?
BGA2228
?
COMMON
BGA2228
COMMON
3/22 FBB
2/22 FBA
FBB_D0 H32 B35 FBB_CMD0
FBA_DBI[7..0] FBB_DBI[7..0] FBB_D0 FBB_CMD0
A
FBA_D0 U51 Y51 FBA_CMD0 FBB_D1 D32 A35 FBB_CMD1 A
FBA_D0 FBA_CMD0 FBA_DBI[7..0] 12,13 FBB_DBI[7..0] 14,15 FBB_D1 FBB_CMD1
FBA_D1 U48 Y52 FBA_CMD1 FBB_D2 A33 D35 FBB_CMD2
FBA_D1 FBA_CMD1 FBA_EDC[7..0] FBB_EDC[7..0] FBB_D2 FBB_CMD2
FBA_D2 U50 Y49 FBA_CMD2 FBB_D3 B32 A36 FBB_CMD3
FBA_D2 FBA_CMD2 FBA_EDC[7..0] 12,13 FBB_EDC[7..0] 14,15 FBB_D3 FBB_CMD3
FBA_D3 U49 AA52 FBA_CMD3 FBB_D4 E32 B36 FBB_CMD4
FBA_D3 FBA_CMD3 FBA_CMD[33..0] FBB_CMD[33..0] FBB_D4 FBB_CMD4
FBA_D4 R51 AA51 FBA_CMD4 FBB_D5 G32 C36 FBB_CMD5
FBA_D4 FBA_CMD4 FBA_CMD[33..0] 12,13 FBB_CMD[33..0] 14,15 FBB_D5 FBB_CMD5
FBA_D5 R50 AA50 FBA_CMD5 FBB_D6 J30 C38 FBB_CMD6
FBA_D5 FBA_CMD5 FBA_D[63..0] FBB_D[63..0] FBB_D6 FBB_CMD6
FBA_D6 R47 AC50 FBA_CMD6 FBB_D7 F32 B38 FBB_CMD7
FBA_D6 FBA_CMD6 FBA_D[63..0] 12,13 FBB_D[63..0] 14,15 FBB_D7 FBB_CMD7
FBA_D7 U46 AC51 FBA_CMD7 FBB_D8 H36 A38 FBB_CMD8
FBA_D7 FBA_CMD7 FBB_D8 FBB_CMD8
FBA_D8 V46 AC52 FBA_CMD8 FBB_D9 G36 D38 FBB_CMD9
FBA_D8 FBA_CMD8 FBB_D9 FBB_CMD9
FBA_D9 Y45 AC49 FBA_CMD9 FBB_D10 J36 A39 FBB_CMD10
FBA_D9 FBA_CMD9 FBB_D10 FBB_CMD10
FBA_D10 Y47 AD52 FBA_CMD10 FBB_D11 F36 B39 FBB_CMD11
FBA_D10 FBA_CMD10 FBB_D11 FBB_CMD11
FBA_D11 Y46 AD51 FBA_CMD11 FBB_D12 F33 C39 FBB_CMD12
FBA_D11 FBA_CMD11 FBB_D12 FBB_CMD12
FBA_D12 V50 AD50 FBA_CMD12 FBB_D13 D33 C41 FBB_CMD13
FBA_D12 FBA_CMD12 FBB_D13 FBB_CMD13
FBA_D13 V47 AF50 FBA_CMD13 FBB_D14 J32 B41 FBB_CMD14
FBA_D13 FBA_CMD13 FBB_D14 FBB_CMD14
FBA_D14 U52 AF51 FBA_CMD14 FBB_D15 G33 A41 FBB_CMD15
FBA_D15
FBA_D16
V51
FBA_D14
FBA_D15
FBA_CMD14
FBA_CMD15 AF52 FBA_CMD15
FBA_CMD16
GDDR5 Mode F Mapping FBB_D16
FBB_D17
E45
FBB_D15
FBB_D16
FBB_CMD15
FBB_CMD16 B49 FBB_CMD16
FBB_CMD17
AJ44 FBA_D16 FBA_CMD16 AN50 D45 FBB_D17 FBB_CMD17 A49
FBA_D17 AG48 AN51 FBA_CMD17 FBB_D18 F45 A48 FBB_CMD18
FBA_D18 AJ45
FBA_D17 FBA_CMD17
AN52 FBA_CMD18 GB3B-256 ch0 0..31 ch1 32..63 FBB_D19 G45
FBB_D18 FBB_CMD18
D47 FBB_CMD19
B.Schematic Diagrams

FBA_D18 FBA_CMD18 FBB_D19 FBB_CMD19


FBA_D19 AG49 AM49 FBA_CMD19 FBB_D20 D42 A47 FBB_CMD20
FBA_D20 AF46
FBA_D19 FBA_CMD19
AM52 FBA_CMD20 CMD0 CAS* FBB_D21 E42
FBB_D20 FBB_CMD20
B47 FBB_CMD21
FBA_D20 FBA_CMD20 FBB_D21 FBB_CMD21
FBA_D21 AF47 AM51 FBA_CMD21 FBB_D22 F42 C47 FBB_CMD22
FBA_D22 AF48
FBA_D21 FBA_CMD21
AM50 FBA_CMD22 1.55V CMD1 CKE* FBB_D23 H41
FBB_D22 FBB_CMD22
C45 FBB_CMD23 1.55V
FBA_D22 FBA_CMD22 FBVDDQ FBB_D23 FBB_CMD23
FBA_D23 AD47 AK50 FBA_CMD23 FBB_D24 E41 B45 FBB_CMD24
FBA_D24
FBA_D23 FBA_CMD23
FBA_CMD24 CMD2 RST* FBB_D25
FBB_D24 FBB_CMD24
FBB_CMD25
FBVDDQ
AD49 FBA_D24 FBA_CMD24 AK51 F39 FBB_D25 FBB_CMD25 A45
FBA_D25 AD48 AK52 FBA_CMD25 FBB_D26 E39 D44 FBB_CMD26
FBA_D26 AC46
FBA_D25 FBA_CMD25
AJ49 FBA_CMD26 CMD3 RAS* FBB_D27 D39
FBB_D26 FBB_CMD26
A44 FBB_CMD27
FBA_D26 FBA_CMD26 FBB_D27 FBB_CMD27
FBA_D27 AC47 AJ52 FBA_CMD27 FBB_D28 F38 B44 FBB_CMD28
FBA_D28 AA47
FBA_D27 FBA_CMD27
AJ51 FBA_CMD28 CMD4 A1_A9 FBB_D29 E38
FBB_D28 FBB_CMD28
C44 FBB_CMD29
FBA_D28 FBA_CMD28 FBB_D29 FBB_CMD29
FBA_D29 AA46 AJ50 FBA_CMD29 R155 R512 FBB_D30 D36 C42 FBB_CMD30 R322 R327
FBA_D30
FBA_D29 FBA_CMD29
FBA_CMD30 CMD5 A0_A10 FBB_D31
FBB_D30 FBB_CMD30
FBB_CMD31

Sheet 11 of 73
AA45 FBA_D30 FBA_CMD30 AG50 60.4_1%_04 60.4_1%_04 E36 FBB_D31 FBB_CMD31 B42 60.4_1%_04 60.4_1%_04
FBA_D31 Y44 AG51 FBA_CMD31 FBB_D32 M50 D41 FBB_CMD32
FBA_D32 AW51
FBA_D31 FBA_CMD31
AF49 FBA_CMD32 CMD6 A12_RFU FBB_D33 P48
FBB_D32 FBB_CMD32
A42 FBB_CMD33
FBA_D32 FBA_CMD32 FBB_D33 FBB_CMD33
FBA_D33 BA52 AG52 FBA_CMD33 FBB_D34 M51 C35 FBB_DEBUG0
FBA_D34 AW50
FBA_D33 FBA_CMD33
Y50 FBA_DEBUG0 CMD7 ABI* FBB_D35 M49
FBB_D34 FBB_CMD34
B50 FBB_DEBUG1
FBA_D34 FBA_CMD34 FBB_D35 FBB_CMD35
B FBA_D35 FBA_DEBUG1 FBB_D36 B

GPU Frame Buffer


BA51 FBA_D35 FBA_CMD35 AR50 CMD8 A6_A11 P47 FBB_D36
FBA_D36 BA50 FBB_D37 P52
FBA_D36 FBB_D37
FBA_D37 BB50 FBB_D38 R46
FBA_D38 BA49
FBA_D37 CMD9 A7_A8 FBB_D39 P46
FBB_D38
J35
FBA_D38 FBB_D39 FBB_DBG_RFU1
FBA_D39 AW49 AA44 FBB_D40 L50 J41
FBA_D40
FBA_D39 FBA_DBG_RFU1 CMD10 WE* FBB_D41
FBB_D40 FBB_DBG_RFU2

Partition
AV48 FBA_D40 FBA_DBG_RFU2 AN44 L51 FBB_D41
FBA_D41 AT49 FBB_D42 L52
FBA_D42 AT47
FBA_D41 CMD11 A5_BA1 FBB_D43 L49
FBB_D42
FBA_D42 FBB_D43
FBA_D43 AT48 FBB_D44 M46 H42 FBB_CLK0
FBA_D44 AT46
FBA_D43
AG45 FBA_CLK0 FB_CLK
CMD12 A4_BA2 FBB_D45 L47
FBB_D44 FBB_CLK0
G42 FBB_CLK0#
DP_FBB_CLK0 FB_CLK FBB_CLK0 14
FBA_D44 FBA_CLK0 DP_FBA_CLK0 FBA_CLK0 12 FBB_D45 FBB_CLK0 DP_FBB_CLK0 FB_CLK FBB_CLK0* 14
FBA_D45 AV51 AG46 FBA_CLK0# FB_CLK FBB_D46 M48 F47 FBB_CLK1
FBA_D46 AV52
FBA_D45 FBA_CLK0
AK46 FBA_CLK1
DP_FBA_CLK0
FB_CLK
FBA_CLK0* 12 CMD13 A2_BA0 FBB_D47 M47
FBB_D46 FBB_CLK1
E47 FBB_CLK1#
DP_FBB_CLK1 FB_CLK FBB_CLK1 15
FBA_D46 FBA_CLK1 DP_FBA_CLK1 FBA_CLK1 13 FBB_D47 FBB_CLK1 DP_FBB_CLK1 FB_CLK FBB_CLK1* 15
FBA_D47 AV49 AK45 FBA_CLK1# FB_CLK FBB_D48 D48
FBA_D48 AJ48
FBA_D47 FBA_CLK1 DP_FBA_CLK1 FBA_CLK1* 13 CMD14 A3_BA3 FBB_D49 C50
FBB_D48
FBA_D48 FBB_D49
FBA_D49 AJ46 FBB_D50 C48
FBA_D50 AJ47
FBA_D49 CMD15 CS* FBB_D51 C49
FBB_D50
FBA_D50 FBB_D51
FBA_D51 AK49 FBB_D52 E49
FBA_D52 AM47
FBA_D51 CMD16 CAS* FBB_D53 E50
FBB_D52
FBA_D52 FBB_D53
FBA_D53 AM46 FBB_D54 F49
FBA_D54 AN48
FBA_D53 CMD17 CKE* FBB_D55 F48
FBB_D54
FBA_D54 FBB_D55 FBB_WCK01
FBA_D55 AN49 FBB_D56 F50 J33
FBA_D56
FBA_D55 FBA_WCK01 CMD18 RST* FBB_D57
FBB_D56 FBB_WCK01 FBB_WCK01#
FBB_WCK01 80DIFF_NETCLASS1
FBB_WCK01 14
AM44 FBA_D56 FBA_WCK01 U45 FBA_WCK01 80DIFF_NETCLASS1 FBA_WCK01 12 D52 FBB_D57 FBB_WCK01 H33 FBB_WCK01 80DIFF_NETCLASS1
FBB_WCK01* 14
FBA_D57 FBA_WCK01# FBB_D58 FBB_WCKB01
AM45 FBA_D57 FBA_WCK01 U44 FBA_WCK01 80DIFF_NETCLASS1 CMD19 RAS* J50 FBB_D58 FBB_WCKB01 G35 FBB_WCKB01 80DIFF_NETCLASS1
FBA_D58 FBA_WCKB01 FBA_WCK01* 12 FBB_D59 FBB_WCKB01# FBB_WCKB01 14
AN45 FBA_D58 FBA_WCKB01 V45 FBA_WCKB01 80DIFF_NETCLASS1 H48 FBB_D59 FBB_WCKB01 H35 FBB_WCKB01 80DIFF_NETCLASS1
FBA_D59 FBA_WCKB01# FBA_WCKB01 12 FBB_D60 FBB_WCK23 FBB_WCKB01* 14
AN46 FBA_D59 FBA_WCKB01 V44 FBA_WCKB01 80DIFF_NETCLASS1 FBA_WCKB01* CMD20
12 A1_A9 H51 FBB_D60 FBB_WCK23 J39 FBB_WCK23 80DIFF_NETCLASS1
FBB_WCK23 14
FBA_D60 FBA_WCK23 FBB_D61 FBB_WCK23#
AR48 FBA_D60 FBA_WCK23 AC45 FBA_WCK23 80DIFF_NETCLASS1 J51 FBB_D61 FBB_WCK23 H39 FBB_WCK23 80DIFF_NETCLASS1
FBA_D61 FBA_WCK23# FBA_WCK23 12 FBB_D62 FBB_WCKB23 FBB_WCK23* 14
AN47 FBA_D61 FBA_WCK23 AC44 FBA_WCK23 80DIFF_NETCLASS1 FBA_WCK23* CMD21
12 A0_A10 H49 FBB_D62 FBB_WCKB23 F41 FBB_WCKB23 80DIFF_NETCLASS1
FBB_WCKB23 14
FBA_D62 FBA_WCKB23 FBB_D63 FBB_WCKB23#
AR47 FBA_D62 FBA_WCKB23 AD46 FBA_WCKB23 80DIFF_NETCLASS1 H52 FBB_D63 FBB_WCKB23 G41 FBB_WCKB23 80DIFF_NETCLASS1
FBA_D63 FBA_WCKB23# FBA_WCKB23 12 FBB_WCK45 FBB_WCKB23* 14
AR46 FBA_D63 FBA_WCKB23 AD45 FBA_WCKB23 80DIFF_NETCLASS1 CMD22 A12_RFU FBB_WCK45 L46 FBB_WCK45 80DIFF_NETCLASS1
FBA_WCK45 FBA_WCKB23* 12 FBB_WCK45# FBB_WCK45 15
FBA_WCK45 AV47 FBA_WCK45 80DIFF_NETCLASS1 FBA_WCK45 13 FBB_WCK45 L45 FBB_WCK45 80DIFF_NETCLASS1
FBB_WCK45* 15
FBA_WCK45# FBB_DBI0 FBB_WCKB45
FBA_WCK45 AV46 FBA_WCK45 80DIFF_NETCLASS1 CMD23 ABI* C32 FBB_DQM0 FBB_WCKB45 M44 FBB_WCKB45 80DIFF_NETCLASS1
FBA_DBI0 FBA_WCKB45 FBA_WCK45* 13 FBB_DBI1 FBB_WCKB45# FBB_WCKB45 15
U47 FBA_DQM0 FBA_WCKB45 AW48 FBA_WCKB45 80DIFF_NETCLASS1 FBA_WCKB45 13 E33 FBB_DQM1 FBB_WCKB45 M45 FBB_WCKB45 80DIFF_NETCLASS1
FBB_WCKB45* 15
FBA_DBI1 FBA_WCKB45# FBB_DBI2 FBB_WCK67
Y48 FBA_DQM1 FBA_WCKB45 AW47 FBA_WCKB45 80DIFF_NETCLASS1 CMD24 A6_A11 E44 FBB_DQM2 FBB_WCK67 H47 FBB_WCK67 80DIFF_NETCLASS1
FBA_DBI2 FBA_WCK67 FBA_WCKB45* 13 FBB_DBI3 FBB_WCK67# FBB_WCK67 15
AG47 FBA_DQM2 FBA_WCK67 AR45 FBA_WCK67 80DIFF_NETCLASS1 G39 FBB_DQM3 FBB_WCK67 H46 FBB_WCK67 80DIFF_NETCLASS1
FBA_DBI3 FBA_WCK67# FBA_WCK67 13 FBB_DBI4 FBB_WCKB67 FBB_WCK67* 15
C AC48 FBA_DQM3 FBA_WCK67 AR44 FBA_WCK67 80DIFF_NETCLASS1 FBA_WCK67* CMD25
13 A7_A8 P49 FBB_DQM4 FBB_WCKB67 J47 FBB_WCKB67 80DIFF_NETCLASS1
FBB_WCKB67 15 C
FBA_DBI4 FBA_WCKB67 FBB_DBI5 FBB_WCKB67#
BB51 FBA_DQM4 FBA_WCKB67 AT45 FBA_WCKB67 80DIFF_NETCLASS1 L48 FBB_DQM5 FBB_WCKB67 J46 FBB_WCKB67 80DIFF_NETCLASS1
FBA_DBI5 FBA_WCKB67# FBA_WCKB67 13 FBB_DBI6 FBB_WCKB67* 15
AV50 FBA_DQM5 FBA_WCKB67 AT44 FBA_WCKB67 80DIFF_NETCLASS1 FBA_WCKB67* CMD26
13 WE* D50 FBB_DQM6
FBA_DBI6 AM48 FBB_DBI7 H50
FBA_DQM6 FBB_DQM7
FBA_DBI7 AR49 FBA_DQM7 CMD27 A5_BA1
FBB_EDC0 B33
FBA_EDC0 R48
CMD28 A4_BA2 FBB_EDC1 E35
FBB_DQS_WP0
FBA_DQS_WP0 FBB_DQS_WP1
FBA_EDC1 V48 FBB_EDC2 G44
FBA_EDC2 AF44
FBA_DQS_WP1 CMD29 A2_BA0 FBB_EDC3 H38
FBB_DQS_WP2
FBA_DQS_WP2 FBB_DQS_WP3
FBA_EDC3 AA48 FBB_EDC4 P50
FBA_EDC4 BB52
FBA_DQS_WP3 CMD30 A3_BA3 FBB_EDC5 J48
FBB_DQS_WP4
FBA_DQS_WP4 FBB_DQS_WP5 PLACE AT BALLS
FBA_EDC5 AT50 PLACE AT BALLS L4 FBB_EDC6 D51
FBA_EDC6 AK48
FBA_DQS_WP5 CMD31 CS* FBB_EDC7 F51
FBB_DQS_WP6
L38 FB_PLL_AVDD
FBA_DQS_WP6 HCB1608KF-300T60 FBB_DQS_WP7 FBB_PLL_AVDD FB_PLL_AVDD 16
FBA_EDC7 AR51 AN42 FB_PLL_AVDD
FBA_DQS_WP7 FBA_PLL_AVDD 1V8_RUN
C347 C385 C386 C465 Y16 GND
W45 GND Y17 GND C547
1u_4V_X6S_02

4.7U_6.3V_X6S_06

4.7U_6.3V_X6S_06

22u_4V_X6S_06

W47 GND Y18 GND


NV_0201_LARGE

NV_0603

NV_0603

NV_0603

W49 GND Y19 GND *0.47u_4V_X6S_02


NV_0201_LARGE
W51 GND Y20 GND
W6 GND Y21 GND
W8 GND Y22 GND
Y14 GND Y23 GND GND
Y15 GND
FBVDDQ FBVDDQ
GND
GND
FB_PLL_AVDD AF42 Place near GPU
FB_REFPLL_AVDD0
L29 FB_REFPLL_AVDD1

R169 R131 R323 R335


10K_04 10K_04 10K_04 10K_04

D
C559 C497 FBA_CMD10 FBB_CMD10 D
FBA_CMD26 FBB_CMD26
*0.47u_4V_X6S_02

*0.47u_4V_X6S_02
NV_0201_LARGE

NV_0201_LARGE

FBA_CMD2 FBB_CMD2 10,21,23,62 1V8_RUN


FBA_CMD18 FBB_CMD18 12,13,14,15,16,17,18,19,25,61 FBVDDQ

ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
R99 R707 R704 R313
10K_04 10K_04 10K_04 10K_04

GND Title
[11] GPU Frame Buffer Partition
ɈP6 x x RA A, Bᶵ
ᶲẞ 枩␐怲 暞ẞ
ᶵᶲẞ )
Size Document Number Rev

GND GND
Fr a me (㔜 Custom SCHEMATIC1 6-71-NH500-D02 D02

Date: Wednesday, December 05, 2018 Sheet 11 of 78


1 2 3 4 5 6 7 8

B - 12 GPU Frame Buffer Partition


Schematic Diagrams

Frame Buffer A
5 4 3 2 1

FBA_W CK01
FRAME BUFFER PARTITION A 31..0 11
11
11
FBA_W CK01
FBA_W CK01*
FBA_W CK23
FBA_W CK01*
FBA_W CK23
11 FBA_DBI[3..0]
FBA_DBI[3..0]

FBA_EDC[3..0]
M8D FBVDDQ

VRAM=K4G80325FB-HC03, HC28 11 FBA_W CK23*


FBA_W CK23* 11 FBA_EDC[3..0]
FBA_CMD[15..0]
FBA_W CKB01 11 FBA_CMD[15..0]
11 FBA_W CKB01 FBA_W CKB01* FBA_CMD32
M8A M8B A11 VSS VDD A1
11 FBA_W CKB01* FBA_W CKB23 11 FBA_CMD32
FBA_D[31..0] A13 VSS VDD A14
11 FBA_W CKB23 FBA_W CKB23* 11 FBA_D[31..0] A2 VSS VDD E10
NORMAL NORMAL 11 FBA_W CKB23*
A4 VSS VDD E5
FBA_D4 B1 VSS VDD H13
B4 x16 x8 M8C
FBA_D7 DQ0_A FBA_D30 B14 VSS VDD H2
D A3 U4 DQ0_B NC D
FBA_D1 DQ1_A FBA_D29 C10 VSS VDD L13
B3 V3 DQ1_B NC
FBA_D5 DQ2_A FBA_D28 C12 VSS VDD L2
B2 U3 DQ2_B NC FBA_CMD0 FBA_VREFC
FBA_D3 DQ3_A FBA_D31 H3 CA0_A VREFC K1 C3 VSS VDD P10
E3 U2 DQ3_B NC FBA_CMD9
FBA_D6 DQ4_A FBA_D25 G11 CA1_A C5 VSS VDD P5
E2 P3 DQ4_B NC FBA_CMD8
FBA_D2 DQ5_A FBA_D27 G4 CA2_A D1 VSS VDD V1
F2 P2 DQ5_B NC FBA_CMD32
FBA_D0 DQ6_A FBA_D24 H12 CA3_A D12 VSS VDD V14
G2 N2 DQ6_B NC FBA_CMD7
DQ7_A FBA_D26 H5 CA4_A D14 VSS
M2 DQ7_B NC FBA_CMD11
FBA_EDC0 H10 CA5_A D3 VSS
C2 EDC0_A FBA_CMD15
FBA_DBI0 FBA_EDC3 J12 CA6_A E11 VSS
D2 DBI0_A T2 EDC0_B GND FBA_CMD14 FBVDDQ
FBA_DBI3 J11 CA7_A E4 VSS
R2 DBI0_B NC FBA_CMD3
FBA_W CK01 J4 CA8_A F1 VSS
D4 WCK0_t_A FBA_CMD1
FBA_W CK01* FBA_W CKB23 J3 CA9_A F12 VSS
D5 WCK0_c_A R4 WCK0_t_B NC FBA_CMD6
FBA_W CKB23* J5 CABI_A F14 VSS VDDQ B10
R5 WCK0_c_B NC FBA_CMD10 G10 CKE_A F3 VSS VDDQ B5
G1 C1

B.Schematic Diagrams
x16 x8 FBA_D23 U11 VSS VDDQ
DQ8_B N5 SNN_FBAL_TCK_M G12 C11
FBA_D8 B11 FBA_D22 V12 TCK T30 VSS VDDQ
DQ8_A
NC DQ9_B F10 SNN_FBAL_TDI_M G14 C14
FBA_D15 A12 FBA_D20 U12 TDI T27 VSS VDDQ
DQ9_A NC DQ10_B N10 SNN_FBAL_TDO_M G3 C4
FBA_D13 B12 FBA_D17 U13 TDO T26 VSS VDDQ
DQ10_A NC DQ11_B F5 SNN_FBAL_TMS_M H11 E1
FBA_D14 B13 FBA_D21 P12 TMS T33 VSS VDDQ
DQ11_A NC DQ12_B H4 E14
FBA_D12 E12 FBA_D16 P13 VSS VDDQ
DQ12_A NC DQ13_B L11 F11
FBA_D10 E13 FBA_D19 N13 VSS VDDQ
DQ13_A NC DQ14_B FBA_CMD4 L3 L4 F4
FBA_D11 F13 FBA_D18 M13 CA0_B VSS VDDQ
DQ14_A NC DQ15_B FBA_CMD12 M11 M1 H1

Sheet 12 of 73
FBA_D9 G13 CA1_B VSS VDDQ
DQ15_A NC FBA_CMD5 M4 M12 H14
FBA_EDC2 T13 CA2_B VSS VDDQ
EDC1_B FBA_CMD13 L12 M14 J13
FBA_EDC1 C13 FBA_DBI2 R13 CA3_B VSS VDDQ
EDC1_A GND DBI1_B FBA_CMD7 L5 M3 J2
FBA_DBI1 D13 CA4_B VSS VDDQ
DBI1_A FBA_CMD11 L10 N1 K13

Frame Buffer A
NC FBA_W CK23 R11 CA5_B VSS VDDQ
WCK1_t_B FBA_CMD15 K12 N12 K2
FBA_W CKB01 D11 FBA_W CK23* R10 CA6_B VSS VDDQ
WCK1_t_A NC WCK1_c_B FBA_CMD14 K11 N14 L1
C FBA_W CKB01* D10 CA7_B VSS VDDQ C
WCK1_c_A NC FBA_CMD3 K4 N3 L14
CA8_B VSS VDDQ
FBA_CMD1 K3 P11 N11
CA9_B VSS VDDQ
FBA_CMD6 K5 P4 N4
U_MEM_SG_GDDR6 U_MEM_SG_GDDR6 CABI_B VSS VDDQ
FBA_CMD10 M10 R1 P1
P/N = P/N = CKE_B VSS VDDQ
ZQ_A J14 FBA_ZQ_1_A R12 VSS VDDQ P14
Close to DRAM FBVDDQ K14 FBA_ZQ_1_B R14 T1
ZQ_B VSS VDDQ
FBVDDQ FBVDDQ R3 VSS VDDQ T11
T10 VSS VDDQ T14
R534 R142 T12 VSS VDDQ T4
FBA_CMD2 J1 T3 U10
RESET VSS VDDQ
C820 C817 C816 C815 C814 C813 121_1%_04 121_1%_04 T5 VSS VDDQ U5
U1 VSS
10u_4V_X6S_06

10u_4V_X6S_06

10u_4V_X6S_06

10u_4V_X6S_06

10u_4V_X6S_06

U14 VSS
10u_4V_X6S_06

K10 CLK_c V11 VSS


11 FBA_CLK0*
J10 CLK_t V13 VSS
11 FBA_CLK0 1V8_AON
V2 VSS
V4 VSS
G5 SNN_FBAL_RFU_A_M
RFU_A T32
M5 SNN_FBAL_RFU_B_M A10
RFU_B T31 VPP
VPP A5
VPP V10
VPP V5
Around DRAM Around DRAM
FBVDDQ
FBVDDQ
U_MEM_SG_GDDR6
U_MEM_SG_GDDR6 P/N =
P/N =
C819 C818 C812 C811 C808 C807
B B
22u_4V_X6S_06

22u_4V_X6S_06

22u_6.3V_X6S_08

22u_6.3V_X6S_08

22u_4V_X6S_06

22u_6.3V_X6S_08

FBVDDQ

R101

*549_1%_04

FBA_VREFC
FBA_VREFC 13
FBVDDQ FBVDDQ
C976 C975 C973 C974 C972 C977 C989 C991 C990 C983 C982 C981 R102 C176
Right under DRAM Right under DRAM R100
1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04

*931_1%_04 *820p_50V_X7R_04
1K_1%_04

D
Q51
G *MTN2002ZS3
14,17,23 GPIO10_FBVREF_SEL
OPTION, Under DRAM

S
1V8_AON
FBVDDQ FBVDDQ C987 C965 C964 C963
A C980 C979 C978 C950 C988 C971 C970 C969 C968 C967 C966 C962 A
Close to DRAM Close to DRAM
1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04

10,13,14,15,17,18,20,21,22,23,24,25,58,61,62,78 1V8_AON
1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04

C354
11,13,14,15,16,17,18,19,25,61 FBVDDQ
4.7u_6.3V_X6S_06

ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Title
[12]MEMORY FBA 31..0
Size Document Number Rev
D02
A3 SCHEMATIC1
6-71-NH500-D02
Date: W ednesday, December 05, 2018 Sheet 12 of 78
5 4 3 2 1

Frame Buffer A B - 13
Schematic Diagrams

Frame Buffer A
5 4 3 2 1

FBA_W CK45
FRAME BUFFER PARTITION A 63..32 11
11
11
FBA_W CK45
FBA_W CK45*
FBA_W CK67
FBA_W CK45*
FBA_W CK67
11 FBA_DBI[7..4]
FBA_DBI[7..4]

FBA_EDC[7..4]
M7D FBVDDQ

VRAM=K4G80325FB-HC03, HC28 11 FBA_W CK67*


FBA_W CK67* 11 FBA_EDC[7..4]
FBA_CMD[31..16]
FBA_W CKB45 11 FBA_CMD[31..16]
11 FBA_W CKB45 FBA_W CKB45* FBA_CMD33
M7A M7B A11 VSS VDD A1
11 FBA_W CKB45* FBA_W CKB67 11 FBA_CMD33
A13 VSS VDD A14
11 FBA_W CKB67 FBA_W CKB67* FBA_D[63..32] A2 VSS VDD E10
NORMAL NORMAL 11 FBA_W CKB67* 11 FBA_D[63..32]
A4 VSS VDD E5
FBA_D39 B1 VSS VDD H13
B4 x16 x8 M7C
FBA_D35 DQ0_A FBA_D57 B14 VSS VDD H2
D A3 U4 DQ0_B NC D
FBA_D32 DQ1_A FBA_D56 C10 VSS VDD L13
B3 V3 DQ1_B NC
FBA_D38 DQ2_A FBA_D59 C12 VSS VDD L2
B2 U3 DQ2_B NC FBA_CMD20
FBA_D34 DQ3_A FBA_D58 H3 CA0_A VREFC K1 C3 VSS VDD P10
E3 U2 DQ3_B NC FBA_CMD28 FBA_VREFC 12
FBA_D33 DQ4_A FBA_D61 G11 CA1_A C5 VSS VDD P5
E2 P3 DQ4_B NC FBA_CMD21
FBA_D37 DQ5_A FBA_D60 G4 CA2_A D1 VSS VDD V1
F2 P2 DQ5_B NC FBA_CMD29
FBA_D36 DQ6_A FBA_D63 H12 CA3_A D12 VSS VDD V14
G2 N2 DQ6_B NC FBA_CMD23
DQ7_A FBA_D62 H5 CA4_A D14 VSS
M2 DQ7_B NC FBA_CMD27
FBA_EDC4 H10 CA5_A D3 VSS
C2 EDC0_A FBA_CMD30
FBA_DBI4 FBA_EDC7 J12 CA6_A E11 VSS
D2 DBI0_A T2 EDC0_B GND FBA_CMD31 FBVDDQ
FBA_DBI7 J11 CA7_A E4 VSS
R2 DBI0_B NC FBA_CMD19
FBA_W CK45 J4 CA8_A F1 VSS
D4 WCK0_t_A FBA_CMD17
FBA_W CK45* FBA_W CKB67 J3 CA9_A F12 VSS
D5 WCK0_c_A R4 WCK0_t_B NC FBA_CMD22
FBA_W CKB67* J5 CABI_A F14 VSS VDDQ B10
R5 WCK0_c_B NC FBA_CMD26 G10 CKE_A F3 VSS VDDQ B5
B.Schematic Diagrams

FBA_D49 G1 VSS VDDQ C1


x16 x8 U11 DQ8_B SNN_FBAU_TCK_M
FBA_D43 FBA_D50 TCK N5 G12 VSS VDDQ C11
B11 NC V12 DQ9_B SNN_FBAU_TDI_M T13
FBA_D46 DQ8_A FBA_D53 TDI F10 G14 VSS VDDQ C14
A12 NC U12 DQ10_B SNN_FBAU_TDO_M T18
FBA_D44 DQ9_A FBA_D48 TDO N10 G3 VSS VDDQ C4
B12 NC U13 DQ11_B SNN_FBAU_TMS_M T19
FBA_D42 DQ10_A FBA_D52 TMS F5 H11 VSS VDDQ E1

Sheet 13 of 73 FBA_D45
FBA_D40
FBA_D41
B13
E12
E13
F13
DQ11_A
DQ12_A
DQ13_A
NC
NC
NC
FBA_D51
FBA_D54
FBA_D55
P12
P13
N13
M13
DQ12_B
DQ13_B
DQ14_B FBA_CMD16 L3 CA0_B
T11
H4
L11
L4
VSS
VSS
VSS
VDDQ
VDDQ
VDDQ
E14
F11
F4
DQ14_A NC DQ15_B FBA_CMD25 M11 M1 H1

Frame Buffer A
FBA_D47 G13 CA1_B VSS VDDQ
DQ15_A NC FBA_CMD24 M4 M12 H14
FBA_EDC6 T13 CA2_B VSS VDDQ
EDC1_B FBA_CMD33 L12 M14 J13
FBA_EDC5 C13 FBA_DBI6 R13 CA3_B VSS VDDQ
EDC1_A GND DBI1_B FBA_CMD23 L5 M3 J2
FBA_DBI5 D13 CA4_B VSS VDDQ
DBI1_A FBA_CMD27 L10 N1 K13
NC FBA_W CK67 R11 CA5_B VSS VDDQ
WCK1_t_B FBA_CMD30 K12 N12 K2
FBA_W CKB45 D11 FBA_W CK67* R10 CA6_B VSS VDDQ
WCK1_t_A NC WCK1_c_B FBA_CMD31 K11 N14 L1
C FBA_W CKB45* D10 CA7_B VSS VDDQ C
WCK1_c_A NC FBA_CMD19 K4 N3 L14
CA8_B VSS VDDQ
FBA_CMD17 K3 P11 N11
CA9_B VSS VDDQ
FBA_CMD22 K5 P4 N4
U_MEM_SG_GDDR6 U_MEM_SG_GDDR6 CABI_B VSS VDDQ
FBA_CMD26 M10 R1 P1
P/N = P/N = CKE_B VSS VDDQ
ZQ_A J14 FBA_ZQ_2_A R12 VSS VDDQ P14
ZQ_B K14 FBA_ZQ_2_B R14 VSS VDDQ T1
R3 VSS VDDQ T11
T10 VSS VDDQ T14
R141 R140 T12 VSS VDDQ T4
FBA_CMD18 J1 T3 U10
RESET VSS VDDQ
121_1%_04 121_1%_04 T5 VSS VDDQ U5
U1 VSS
U14 VSS
K10 CLK_c V11 VSS
11 FBA_CLK1*
J10 CLK_t V13 VSS
11 FBA_CLK1 1V8_AON
V2 VSS
V4 VSS
G5 SNN_FBAU_RFU_A
RFU_A T10
M5 SNN_FBAU_RFU_B A10
RFU_B T12 VPP
VPP A5
VPP V10
VPP V5

U_MEM_SG_GDDR6
U_MEM_SG_GDDR6 P/N =
P/N =

B B

A A
10,12,14,15,17,18,20,21,22,23,24,25,58,61,62,78 1V8_AON
11,12,14,15,16,17,18,19,25,61 FBVDDQ

ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Title
[13]MEMORY FBA 63..32
Size Document Number Rev
R9.1
A3 SCHEMATIC1
6-71-NH500-D02
Date: W ednesday, December 05, 2018 Sheet 13 of 78
5 4 3 2 1

B - 14 Frame Buffer A
Schematic Diagrams

Frame Buffer B

5 4 3 2 1

FBB_W CK01
FRAME BUFFER PARTITION B 31..0 11
11
11
FBB_W CK01
FBB_W CK01*
FBB_W CK23
FBB_W CK01*
FBB_W CK23
11 FBB_DBI[3..0]
FBB_DBI[3..0]

FBB_EDC[3..0]
M10D FBVDDQ

VRAM=K4G80325FB-HC03, HC28 11 FBB_W CK23*


FBB_W CK23* 11 FBB_EDC[3..0]
FBB_CMD[15..0]
FBB_W CKB01 11 FBB_CMD[15..0]
11 FBB_W CKB01 FBB_W CKB01* FBB_CMD32
M10A M10B A11 VSS VDD A1
11 FBB_W CKB01* FBB_W CKB23 11 FBB_CMD32
FBB_D[31..0] A13 VSS VDD A14
11 FBB_W CKB23 FBB_W CKB23* 11 FBB_D[31..0] A2 VSS VDD E10
NORMAL NORMAL 11 FBB_W CKB23*
A4 VSS VDD E5
FBB_D1 B1 VSS VDD H13
B4 x16 x8 M10C
FBB_D6 DQ0_A FBB_D24 B14 VSS VDD H2
D A3 U4 DQ0_B NC D
FBB_D2 DQ1_A FBB_D30 C10 VSS VDD L13
B3 V3 DQ1_B NC
FBB_D4 DQ2_A FBB_D29 C12 VSS VDD L2
B2 U3 DQ2_B NC FBB_CMD0 FBB_VREFC
FBB_D5 DQ3_A FBB_D31 H3 CA0_A VREFC K1 C3 VSS VDD P10
E3 U2 DQ3_B NC FBB_CMD9
FBB_D3 DQ4_A FBB_D25 G11 CA1_A C5 VSS VDD P5
E2 P3 DQ4_B NC FBB_CMD8
FBB_D0 DQ5_A FBB_D26 G4 CA2_A D1 VSS VDD V1
F2 P2 DQ5_B NC FBB_CMD32
FBB_D7 DQ6_A FBB_D27 H12 CA3_A D12 VSS VDD V14
G2 N2 DQ6_B NC FBB_CMD7
DQ7_A FBB_D28 H5 CA4_A D14 VSS
M2 DQ7_B NC FBB_CMD11
FBB_EDC0 H10 CA5_A D3 VSS
C2 EDC0_A FBB_CMD15
FBB_DBI0 FBB_EDC3 J12 CA6_A E11 VSS
D2 DBI0_A T2 EDC0_B GND FBB_CMD14 FBVDDQ
FBB_DBI3 J11 CA7_A E4 VSS
R2 DBI0_B NC FBB_CMD3
FBB_W CK01 J4 CA8_A F1 VSS
D4 WCK0_t_A FBB_CMD1
FBB_W CK01* FBB_W CKB23 J3 CA9_A F12 VSS
D5 WCK0_c_A R4 WCK0_t_B NC FBB_CMD6 J5 F14 B10

B.Schematic Diagrams
FBB_W CKB23* R5 CABI_A VSS VDDQ
WCK0_c_B NC FBB_CMD10 G10 F3 B5
CKE_A VSS VDDQ
FBB_D21 G1 VSS VDDQ C1
x16 x8 U11 DQ8_B SNN_FBBL_TCK_M
FBB_D13 FBB_D16 TCK N5 G12 VSS VDDQ C11
B11 NC V12 DQ9_B SNN_FBBL_TDI_M T56
FBB_D14 DQ8_A FBB_D20 TDI F10 G14 VSS VDDQ C14
A12 NC U12 DQ10_B SNN_FBBL_TDO_M T60
FBB_D12 DQ9_A FBB_D17 TDO N10 G3 VSS VDDQ C4
B12 NC U13 DQ11_B SNN_FBBL_TMS_M T59
FBB_D11 DQ10_A FBB_D18 TMS F5 H11 VSS VDDQ E1
B13 NC P12 DQ12_B T58
FBB_D15 DQ11_A FBB_D22 H4 VSS VDDQ E14
E12 NC P13 DQ13_B
DQ12_A L11 F11
FBB_D8 FBB_D23
Sheet 14 of 73
E13 N13 VSS VDDQ
DQ13_A NC DQ14_B FBB_CMD4 L3 L4 F4
FBB_D9 F13 FBB_D19 M13 CA0_B VSS VDDQ
DQ14_A NC DQ15_B FBB_CMD12 M11 M1 H1
FBB_D10 G13 CA1_B VSS VDDQ
DQ15_A NC FBB_CMD5 M4 M12 H14
FBB_EDC2 T13 CA2_B VSS VDDQ
EDC1_B FBB_CMD13 L12 M14 J13
FBB_EDC1
FBB_DBI1

FBB_W CKB01
C13
D13

D11
EDC1_A
DBI1_A
GND

NC
FBB_DBI2

FBB_W CK23
FBB_W CK23*
R13

R11
R10
DBI1_B

WCK1_t_B
FBB_CMD7
FBB_CMD11
FBB_CMD15
L5
L10
K12
CA3_B
CA4_B
CA5_B
CA6_B
M3
N1
N12
VSS
VSS
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
J2
K13
K2
Frame Buffer B
WCK1_t_A NC WCK1_c_B FBB_CMD14 K11 N14 L1
C FBB_W CKB01* D10 CA7_B VSS VDDQ C
WCK1_c_A NC FBB_CMD3 K4 N3 L14
CA8_B VSS VDDQ
FBB_CMD1 K3 P11 N11
CA9_B VSS VDDQ
FBB_CMD6 K5 P4 N4
U_MEM_SG_GDDR6 U_MEM_SG_GDDR6 CABI_B VSS VDDQ
FBB_CMD10 M10 R1 P1
P/N = P/N = CKE_B VSS VDDQ
ZQ_A J14 FBB_ZQ_1_A R12 VSS VDDQ P14
Close to DRAM FBVDDQ K14 FBB_ZQ_1_B R14 T1
FBVDDQ FBVDDQ ZQ_B VSS VDDQ
R3 VSS VDDQ T11
T10 VSS VDDQ T14
R326 R325 T12 VSS VDDQ T4
FBB_CMD2 J1 T3 U10
RESET VSS VDDQ
C526 C525 C445 C753 C774 C782 121_1%_04 121_1%_04 T5 VSS VDDQ U5
U1 VSS
10u_4V_X6S_06

10u_4V_X6S_06

10u_4V_X6S_06

10u_4V_X6S_06

10u_4V_X6S_06

U14
10u_4V_X6S_06

VSS
K10 CLK_c V11 VSS
11 FBB_CLK0*
J10 CLK_t V13 VSS
11 FBB_CLK0 1V8_AON
V2 VSS
V4 VSS
G5 SNN_FBBL_RFU_A_M
RFU_A T57
M5 SNN_FBBL_RFU_B_M A10
RFU_B T55 VPP
VPP A5
VPP V10
VPP V5
Around DRAM Around DRAM
FBVDDQ
FBVDDQ
U_MEM_SG_GDDR6
U_MEM_SG_GDDR6 P/N =
P/N =
C780 C754 C705 C805 C362 C741
B B
22u_6.3V_X6S_08

22u_4V_X6S_06

22u_6.3V_X6S_08

22u_6.3V_X6S_08

22u_6.3V_X6S_08

22u_6.3V_X6S_08

FBVDDQ

R710

*549_1%_04

FBB_VREFC
FBB_VREFC 15
FBVDDQ FBVDDQ
C751 C712 C721 C785 C452 C792 C796 C567 C447 C264 C449 C356 R711 C1137
Right under DRAM Right under DRAM R318
1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04

*931_1%_04 *820p_50V_X7R_04
1K_1%_04

D
Q67
G *MTN2002ZS3
OPTION, Under DRAM 12,17,23 GPIO10_FBVREF_SEL

S
1V8_AON
FBVDDQ FBVDDQ C760 C761 C762 C763
C448 C565 C726 C566 C446 C357 C263 C360 C359 C179 C358 C755
1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04

A Close to DRAM Close to DRAM A


C769 10,12,13,15,17,18,20,21,22,23,24,25,58,61,62,78 1V8_AON
1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04

11,12,13,15,16,17,18,19,25,61 FBVDDQ
4.7u_6.3V_X6S_06

ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Title
[14]MEMORY FBB 31..0
Size Document Number Rev
R9.1
A3 SCHEMATIC1
6-71-NH500-D02
Date: W ednesday, December 05, 2018 Sheet 14 of 78
5 4 3 2 1

Frame Buffer B B - 15
Schematic Diagrams

Frame Buffer B
5 4 3 2 1

FBB_W CK45
FRAME BUFFER PARTITION B 63..32 11
11
11
FBB_W CK45
FBB_W CK45*
FBB_W CK67
FBB_W CK45*
FBB_W CK67
11 FBB_DBI[7..4]
FBB_DBI[7..4]

FBB_EDC[7..4]
M9D FBVDDQ

VRAM=K4G80325FB-HC03, HC28 11 FBB_W CK67*


FBB_W CK67* 11 FBB_EDC[7..4]
FBB_CMD[31..16]
FBB_W CKB45 11 FBB_CMD[31..16]
11 FBB_W CKB45 FBB_W CKB45* FBB_CMD33
M9A M9B A11 VSS VDD A1
11 FBB_W CKB45* FBB_W CKB67 11 FBB_CMD33
A13 VSS VDD A14
11 FBB_W CKB67 FBB_W CKB67* FBB_D[63..32] A2 VSS VDD E10
NORMAL NORMAL 11 FBB_W CKB67* 11 FBB_D[63..32]
A4 VSS VDD E5
FBB_D35 B1 VSS VDD H13
B4 x16 x8 M9C
D FBB_D33 DQ0_A FBB_D62 B14 VSS VDD H2 D
A3 U4 DQ0_B NC
FBB_D32 DQ1_A FBB_D59 C10 VSS VDD L13
B3 V3 DQ1_B NC
FBB_D36 DQ2_A FBB_D57 C12 VSS VDD L2
B2 U3 DQ2_B NC FBB_CMD20
FBB_D39 DQ3_A FBB_D63 H3 CA0_A VREFC K1 C3 VSS VDD P10
E3 U2 DQ3_B NC FBB_CMD28 FBB_VREFC 14
FBB_D34 DQ4_A FBB_D56 G11 CA1_A C5 VSS VDD P5
E2 P3 DQ4_B NC FBB_CMD21
FBB_D37 DQ5_A FBB_D61 G4 CA2_A D1 VSS VDD V1
F2 P2 DQ5_B NC FBB_CMD29
FBB_D38 DQ6_A FBB_D60 H12 CA3_A D12 VSS VDD V14
G2 N2 DQ6_B NC FBB_CMD23
DQ7_A FBB_D58 H5 CA4_A D14 VSS
M2 DQ7_B NC FBB_CMD27
FBB_EDC4 H10 CA5_A D3 VSS
C2 EDC0_A FBB_CMD30
FBB_DBI4 FBB_EDC7 J12 CA6_A E11 VSS
D2 DBI0_A T2 EDC0_B GND FBB_CMD31 FBVDDQ
FBB_DBI7 J11 CA7_A E4 VSS
R2 DBI0_B NC FBB_CMD19
FBB_W CK45 J4 CA8_A F1 VSS
D4 WCK0_t_A FBB_CMD17
FBB_W CK45* FBB_W CKB67 J3 CA9_A F12 VSS
D5 WCK0_c_A R4 WCK0_t_B NC FBB_CMD22
FBB_W CKB67* J5 CABI_A F14 VSS VDDQ B10
R5 WCK0_c_B NC FBB_CMD26 G10 CKE_A F3 VSS VDDQ B5
FBB_D55 G1 VSS VDDQ C1
B.Schematic Diagrams

x16 x8 U11 DQ8_B SNN_FBBU_TCK_M


FBB_D42 FBB_D48 TCK N5 G12 VSS VDDQ C11
B11 NC V12 DQ9_B SNN_FBBU_TDI_M T65
FBB_D43 DQ8_A FBB_D52 TDI F10 G14 VSS VDDQ C14
A12 NC U12 DQ10_B SNN_FBBU_TDO_M T62
FBB_D40 DQ9_A FBB_D50 TDO N10 G3 VSS VDDQ C4
B12 NC U13 DQ11_B SNN_FBBU_TMS_M T66
FBB_D45 DQ10_A FBB_D49 TMS F5 H11 VSS VDDQ E1
B13 NC P12 DQ12_B T61
DQ11_A H4 E14

Sheet 15 of 73 FBB_D41
FBB_D44
FBB_D46
FBB_D47
E12
E13
F13
DQ12_A
DQ13_A
DQ14_A
NC
NC
NC
FBB_D51
FBB_D53
FBB_D54
P13
N13
M13
DQ13_B
DQ14_B
DQ15_B
FBB_CMD16
FBB_CMD25
L3
M11
CA0_B
CA1_B
L11
L4
M1
VSS
VSS
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
F11
F4
H1
G13 NC FBB_CMD24 M4 M12 H14
Frame Buffer B
DQ15_A FBB_EDC6 CA2_B VSS VDDQ
T13 EDC1_B FBB_CMD33
FBB_EDC5 FBB_DBI6 L12 CA3_B M14 VSS VDDQ J13
C13 EDC1_A GND R13 DBI1_B FBB_CMD23
FBB_DBI5 L5 CA4_B M3 VSS VDDQ J2
D13 DBI1_A FBB_CMD27
NC FBB_W CK67 L10 CA5_B N1 VSS VDDQ K13
R11 WCK1_t_B FBB_CMD30
FBB_W CKB45 FBB_W CK67* K12 CA6_B N12 VSS VDDQ K2
D11 WCK1_t_A NC R10 WCK1_c_B FBB_CMD31
C FBB_W CKB45* K11 CA7_B N14 VSS VDDQ L1 C
D10 WCK1_c_A NC FBB_CMD19 K4 CA8_B N3 VSS VDDQ L14
FBB_CMD17 K3 P11 N11
CA9_B VSS VDDQ
FBB_CMD22 K5 P4 N4
U_MEM_SG_GDDR6 U_MEM_SG_GDDR6 CABI_B VSS VDDQ
FBB_CMD26 M10 R1 P1
P/N = P/N = CKE_B VSS VDDQ
ZQ_A J14 FBB_ZQ_2_A R12 VSS VDDQ P14
ZQ_B K14 FBB_ZQ_2_B R14 VSS VDDQ T1
R3 VSS VDDQ T11
T10 VSS VDDQ T14
R334 R333 T12 VSS VDDQ T4
FBB_CMD18 J1 T3 U10
RESET VSS VDDQ
121_1%_04 121_1%_04 T5 VSS VDDQ U5
U1 VSS
U14 VSS
K10 CLK_c V11 VSS
11 FBB_CLK1*
J10 CLK_t V13 VSS
11 FBB_CLK1 1V8_AON
V2 VSS
V4 VSS
G5 SNN_FBBU_RFU_A
RFU_A T63
M5 SNN_FBBU_RFU_B A10
RFU_B T64 VPP
VPP A5
VPP V10
VPP V5

U_MEM_SG_GDDR6
U_MEM_SG_GDDR6 P/N =
P/N =
B B

A A

10,12,13,14,17,18,20,21,22,23,24,25,58,61,62,78 1V8_AON
11,12,13,14,16,17,18,19,25,61 FBVDDQ

ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Title
[15]MEMORY FBB 63..32
Size Document Number Rev
R9.1
A3 SCHEMATIC1
6-71-NH500-D02
Date: W ednesday, December 05, 2018 Sheet 15 of 78
5 4 3 2 1

B - 16 Frame Buffer B
Schematic Diagrams

Frame Buffer C/D


1 2 3 4 5 6 7 8

GPU FRAME BUFFER PARTITION C/D FBC_DBI[7..0]


FBC_DBI[7..0] 17,18
FBC_EDC[7..0]

ɈP6xx RE Fr a me ᶲ

D ẞ
G1D FBC_EDC[7..0] 17,18 G1E
? ?
BGA2228 FBC_CMD[33..0] BGA2228
COMMON FBC_CMD[33..0] 17,18 COMMON
FBC_D[63..0]
4/22 FBC 5/22 FBD
FBC_D[63..0] 17,18
FBC_D0 C6 C11 FBC_CMD0 FBVDDQ AK8 AD2
FBC_D0 FBC_CMD0 FBD_D0 FBD_CMD0
FBC_D1 D6 B11 FBC_CMD1 AK4 AD1
FBC_D1 FBC_CMD1 FBD_D1 FBD_CMD1
FBC_D2 A6 A11 FBC_CMD2 AK2 AD4
FBC_D2 FBC_CMD2 FBD_D2 FBD_CMD2
A
FBC_D3 B6 D11 FBC_CMD3 AK3 AC1 A
FBC_D3 FBC_CMD3 FBD_D3 FBD_CMD3
FBC_D4 B4 A12 FBC_CMD4 AK5 AC2
FBC_D4 FBC_CMD4 FBD_D4 FBD_CMD4
FBC_D5 A4 B12 FBC_CMD5 AK6 AC3
FBC_D5 FBC_CMD5 FBD_D5 FBD_CMD5
FBC_D6 B3 C12 FBC_CMD6 R300 R298 AK9 AA3
FBC_D6 FBC_CMD6 FBD_D6 FBD_CMD6
FBC_D7 C4 C14 FBC_CMD7 10K_04 10K_04 AK7 AA2
FBC_D7 FBC_CMD7 FBD_D7 FBD_CMD7
FBC_D8 D9 B14 FBC_CMD8 AG4 AA1
FBC_D8 FBC_CMD8 FBD_D8 FBD_CMD8
FBC_D9 C9 A14 FBC_CMD9 AF9 AA4
FBC_D9 FBC_CMD9 FBD_D9 FBD_CMD9
FBC_D10 E9 D14 FBC_CMD10 FBC_CMD10 AG6 Y1
FBC_D10 FBC_CMD10 FBD_D10 FBD_CMD10
FBC_D11 B9 A15 FBC_CMD11 FBC_CMD26 AG7 Y2
FBC_D11 FBC_CMD11 FBD_D11 FBD_CMD11
FBC_D12 B8 B15 FBC_CMD12 AJ4 Y3
FBC_D12 FBC_CMD12 FBD_D12 FBD_CMD12
FBC_D13 A8 C15 FBC_CMD13 FBC_CMD2 AJ5 V3
FBC_D13 FBC_CMD13 FBD_D13 FBD_CMD13
FBC_D14 F6 C17 FBC_CMD14 FBC_CMD18 AJ6 V2
FBC_D14 FBC_CMD14 FBD_D14 FBD_CMD14
FBC_D15 E6 B17 FBC_CMD15 AG5 V1
FBC_D15 FBC_CMD15 FBD_D15 FBD_CMD15
FBC_D16 F18 B24 FBC_CMD16 Y6 L3
FBC_D16 FBC_CMD16 FBD_D16 FBD_CMD16
FBC_D17 G18 A24 FBC_CMD17 R312 R307 Y5 L2
FBC_D17 FBC_CMD17 FBD_D17 FBD_CMD17
FBC_D18 E18 D23 FBC_CMD18 10K_04 10K_04 V5 L1
FBC_D18 FBC_CMD18 FBD_D18 FBD_CMD18
FBC_D19 FBC_CMD19

B.Schematic Diagrams
H18 FBC_D19 FBC_CMD19 A23 Y4 FBD_D19 FBD_CMD19 M4
FBC_D20 D15 B23 FBC_CMD20 AA6 M1
FBC_D20 FBC_CMD20 FBD_D20 FBD_CMD20
FBC_D21 E15 C23 FBC_CMD21 AA5 M2
FBC_D21 FBC_CMD21 FBD_D21 FBD_CMD21
FBC_D22 G17 C21 FBC_CMD22 AC5 M3
FBC_D22 FBC_CMD22 FBD_D22 FBD_CMD22
FBC_D23
FBC_D24
FBC_D25
FBC_D26
H17
J15
H15
FBC_D23
FBC_D24
FBC_D25
FBC_CMD23
FBC_CMD24
FBC_CMD25
B21
A21
D20
FBC_CMD23
FBC_CMD24
FBC_CMD25
FBC_CMD26
FBVDDQ GND
AC4
AD7
AC6
FBD_D23
FBD_D24
FBD_D25
FBD_CMD23
FBD_CMD24
FBD_CMD25
P3
P2
P1
Sheet 16 of 73
E14 FBC_D26 FBC_CMD26 A20 AF6 FBD_D26 FBD_CMD26 R4
FBC_D27
FBC_D28
FBC_D29
F14
H11
G11
FBC_D27
FBC_D28
FBC_D29
FBC_CMD27
FBC_CMD28
FBC_CMD29
B20
C20
C18
FBC_CMD27
FBC_CMD28
FBC_CMD29
AD6
AF7
AF8
FBD_D27
FBD_D28
FBD_D29
FBD_CMD27
FBD_CMD28
FBD_CMD29
R1
R2
R3
Frame Buffer C/D
FBC_D30 F11 B18 FBC_CMD30 R291 R315 AF2 U3
FBC_D30 FBC_CMD30 FBD_D30 FBD_CMD30
FBC_D31 E11 A18 FBC_CMD31 AF3 U2
FBC_D31 FBC_CMD31 FBD_D31 FBD_CMD31
B FBC_D32 J29 A17 FBC_CMD32 60.4_1%_04 60.4_1%_04 F4 V4 B
FBC_D32 FBC_CMD32 FBD_D32 FBD_CMD32
FBC_D33 F30 D17 FBC_CMD33 E1 U1
FBC_D33 FBC_CMD33 FBD_D33 FBD_CMD33
FBC_D34 H29 A9 FBC_DEBUG0 F3 AD3
FBC_D34 FBC_CMD34 FBD_D34 FBD_CMD34
FBC_D35 G30 C24 FBC_DEBUG1 F5 J3
FBC_D35 FBC_CMD35 FBD_D35 FBD_CMD35
FBC_D36 B30 D2
FBC_D36 FBD_D36
FBC_D37 A30 D1
FBC_D37 FBD_D37
FBC_D38 H30 C3
FBC_D38 FBD_D38
FBC_D39 C30 J14 C2 AC9
FBC_D39 FBC_DBG_RFU1 FBD_D39 FBD_DBG_RFU1
FBC_D40 D27 J23 J5 P9
FBC_D40 FBC_DBG_RFU2 FBD_D40 FBD_DBG_RFU2
FBC_D41 J26 J4
FBC_D41 FBD_D41
FBC_D42 F27 L8
FBC_D42 FBD_D42
FBC_D43 G27 J2
FBC_D43 FBD_D43
FBC_D44 C27 G15 FBC_CLK0 F1 Y8
FBC_D44 FBC_CLK0 DP_FBC_CLK0 FB_CLK FBC_CLK0 17 FBD_D44 FBD_CLK0
FBC_D45 B27 F15 FBC_CLK0# F2 Y7
FBC_D45 FBC_CLK0 DP_FBC_CLK0 FB_CLK FBC_CLK0* 17 FBD_D45 FBD_CLK0
FBC_D46 A27 H21 FBC_CLK1 H4 R8
FBC_D46 FBC_CLK1 DP_FBC_CLK1 FB_CLK FBC_CLK1 18 FBD_D46 FBD_CLK1
FBC_D47 G29 J21 FBC_CLK1# H5 R7
FBC_D47 FBC_CLK1 DP_FBC_CLK1 FB_CLK FBC_CLK1* 18 FBD_D47 FBD_CLK1
FBC_D48 H20 V7
FBC_D48 FBD_D48
FBC_D49 D18 V8
FBC_D49 FBD_D49
FBC_D50 G20 V6
FBC_D50 FBD_D50
FBC_D51 E20 V9
FBC_D51 FBD_D51
FBC_D52 F23 U4
FBC_D52 FBD_D52
FBC_D53 E21 R5
FBC_D53 FBD_D53
FBC_D54 D21 R6
FBC_D54 FBD_D54
FBC_D55 E23 U8
FBC_D55 FBC_WCK01 FBD_D55
FBC_D56 G24 F8 P6 AJ8
FBC_D56 FBC_WCK01 FBC_WCK01#
FBC_WCK01 80DIFF_NETCLASS1 FBC_W CK01 17 FBD_D56 FBD_WCK01
FBC_D57 H26 G8 R9 AJ7
FBC_D57 FBC_WCK01 FBC_WCKB01
FBC_WCK01 80DIFF_NETCLASS1 FBC_W CK01* 17 FBD_D57 FBD_WCK01
FBC_D58 F24 G9 P4 AG8
FBC_D58 FBC_WCKB01 FBC_WCKB01#
FBC_WCKB01 80DIFF_NETCLASS1 FBC_W CKB01 17 FBD_D58 FBD_WCKB01
FBC_D59 G26 F9 P5 AG9
FBC_D59 FBC_WCKB01 FBC_WCK23
FBC_WCKB01 80DIFF_NETCLASS1 FBC_W CKB01* 17 FBD_D59 FBD_WCKB01
FBC_D60 F26 H12 L7 AD8
FBC_D60 FBC_WCK23 FBC_WCK23#
FBC_WCK23 80DIFF_NETCLASS1 FBC_W CK23 17 FBD_D60 FBD_WCK23
C FBC_D61 D26 G12 L6 AD9 C
FBC_D61 FBC_WCK23 FBC_WCKB23
FBC_WCK23 80DIFF_NETCLASS1 FBC_W CK23* 17 FBD_D61 FBD_WCK23
FBC_D62 B26 G14 L4 AC7
FBC_D62 FBC_WCKB23 FBC_WCKB23#
FBC_WCKB23 80DIFF_NETCLASS1 FBC_W CKB23 17 FBD_D62 FBD_WCKB23
FBC_D63 C26 H14 L5 AC8
FBC_D63 FBC_WCKB23 FBC_WCK45
FBC_WCKB23 80DIFF_NETCLASS1 FBC_W CKB23* 17 FBD_D63 FBD_WCKB23
FBC_WCK45 J27 FBC_WCK45 80DIFF_NETCLASS1 FBC_W CK45 18 FBD_WCK45 J6
FBC_WCK45#
FBC_WCK45 H27 FBC_WCK45 80DIFF_NETCLASS1 FBC_W CK45* 18 FBD_WCK45 J7
FBC_DBI0 FBC_WCKB45
A5 FBC_DQM0 FBC_WCKB45 E29 FBC_WCKB45 80DIFF_NETCLASS1 FBC_W CKB45 18 AJ1 FBD_DQM0 FBD_WCKB45 H7
FBC_DBI1 FBC_WCKB45#
C8 FBC_DQM1 FBC_WCKB45 F29 FBC_WCKB45 80DIFF_NETCLASS1 FBC_W CKB45* 18 AG1 FBD_DQM1 FBD_WCKB45 H6
FBC_DBI2 FBC_WCK67
J18 FBC_DQM2 FBC_WCK67 G23 FBC_WCK67 80DIFF_NETCLASS1 FBC_W CK67 18 AA7 FBD_DQM2 FBD_WCK67 P8
FBC_DBI3 FBC_WCK67#
F12 FBC_DQM3 FBC_WCK67 H23 FBC_WCK67 80DIFF_NETCLASS1 FBC_W CK67* 18 AD5 FBD_DQM3 FBD_WCK67 P7
FBC_DBI4 FBC_WCKB67
D29 FBC_DQM4 FBC_WCKB67 H24 FBC_WCKB67 80DIFF_NETCLASS1 FBC_W CKB67 18 D3 FBD_DQM4 FBD_WCKB67 M7
FBC_DBI5 FBC_WCKB67#
E27 FBC_DQM5 FBC_WCKB67 J24 FBC_WCKB67 80DIFF_NETCLASS1 FBC_W CKB67* 18 H3 FBD_DQM5 FBD_WCKB67 M8
FBC_DBI6 F20 U5
FBC_DQM6 FBD_DQM6
FBC_DBI7 E26 M9
FBC_DQM7 FBD_DQM7 C252

FBC_EDC0 0.47U_4V_X6S_02
D5 FBC_DQS_WP0 AJ3 FBD_DQS_WP0 NV_0201_LARGE
FBC_EDC1 D8 AG2
FBC_DQS_WP1 FBD_DQS_WP1
FBC_EDC2 E17 AA9
FBC_DQS_WP2 FBD_DQS_WP2
FBC_EDC3 E12 AF4
FBC_DQS_WP3 FBD_DQS_WP3
FBC_EDC4 E30 E3 GND
FBC_DQS_WP4 FBD_DQS_WP4
FBC_EDC5 B29 H2
FBC_DQS_WP5 FBD_DQS_WP5
FBC_EDC6 G21 U6
FBC_DQS_WP6 FBD_DQS_WP6 R152 0_04
FBC_EDC7 E24 L17 M5 V11
FBC_DQS_WP7 FBC_PLL_AVDD FB_PLL_AVDD 11,16 FBD_DQS_WP7 FBD_PLL_AVDD FB_PLL_AVDD 11,16

Y24 GND Y32 GND


Y25 GND C383 Y33 GND
Y26 GND Y34 GND
D
Y27 GND 0.47U_4V_X6S_02 Y35 GND D
NV_0201_LARGE
Y28 GND Y36 GND
Y29 GND Y37 GND
Y30 GND Y38 GND
Y31 GND GND Y39 GND

N18E-G3
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
GND GND Title
[16] GPU Frame Buffer Partition
FBD N/A Size Document Number Rev
11,12,13,14,15,17,18,19,25,61 FBVDDQ
A3 SCHEMATIC1 6-71-NH500-D02 D02

Date: W ednesday, December 05, 2018 Sheet 16 of 78


1 2 3 4 5 6 7 8

Frame Buffer C/D B - 17


Schematic Diagrams

Frame Buffer C

5 4 3 2 1

FBC_W CK01
FRAME BUFFER PARTITION C 31..0 16
16
16
FBC_W CK01
FBC_W CK01*
FBC_W CK23
FBC_W CK01*
FBC_W CK23
16 FBC_DBI[3..0]
FBC_DBI[3..0]

FBC_EDC[3..0]
M12D FBVDDQ

VRAM=K4G80325FB-HC03, HC28 16 FBC_W CK23*


FBC_W CK23* 16 FBC_EDC[3..0]
FBC_CMD[15..0]
FBC_W CKB01 16 FBC_CMD[15..0]
16 FBC_W CKB01 FBC_W CKB01* FBC_CMD32
M12A M12B A11 VSS VDD A1
16 FBC_W CKB01* FBC_W CKB23 16 FBC_CMD32
FBC_D[31..0] A13 VSS VDD A14
16 FBC_W CKB23 FBC_W CKB23* 16 FBC_D[31..0] A2 VSS VDD E10
NORMAL NORMAL 16 FBC_W CKB23*
A4 VSS VDD E5
FBC_D1 B1 VSS VDD H13
B4 x16 x8 M12C
FBC_D7 DQ0_A FBC_D25 B14 VSS VDD H2
D A3 U4 DQ0_B NC D
FBC_D5 DQ1_A FBC_D29 C10 VSS VDD L13
B3 V3 DQ1_B NC
FBC_D4 DQ2_A FBC_D28 C12 VSS VDD L2
B2 U3 DQ2_B NC FBC_CMD0 FBC_VREFC
FBC_D6 DQ3_A FBC_D31 H3 CA0_A VREFC K1 C3 VSS VDD P10
E3 U2 DQ3_B NC FBC_CMD9
FBC_D3 DQ4_A FBC_D26 G11 CA1_A C5 VSS VDD P5
E2 P3 DQ4_B NC FBC_CMD8
FBC_D0 DQ5_A FBC_D24 G4 CA2_A D1 VSS VDD V1
F2 P2 DQ5_B NC FBC_CMD32
FBC_D2 DQ6_A FBC_D30 H12 CA3_A D12 VSS VDD V14
G2 N2 DQ6_B NC FBC_CMD7
DQ7_A FBC_D27 H5 CA4_A D14 VSS
M2 DQ7_B NC FBC_CMD11
FBC_EDC0 H10 CA5_A D3 VSS
C2 EDC0_A FBC_CMD15
FBC_DBI0 FBC_EDC3 J12 CA6_A E11 VSS
D2 DBI0_A T2 EDC0_B GND FBC_CMD14 FBVDDQ
FBC_DBI3 J11 CA7_A E4 VSS
R2
B.Schematic Diagrams

DBI0_B NC FBC_CMD3 J4 F1
FBC_W CK01 D4 CA8_A VSS
WCK0_t_A FBC_CMD1 J3 F12
FBC_W CK01* D5 FBC_W CKB23 R4 CA9_A VSS
WCK0_c_A WCK0_t_B NC FBC_CMD6 J5 F14 B10
FBC_W CKB23* R5 CABI_A VSS VDDQ
WCK0_c_B NC FBC_CMD10 G10 F3 B5
CKE_A VSS VDDQ
G1 C1

Sheet 17 of 73 FBC_D14
FBC_D15
FBC_D8
B11
A12
B12
DQ8_A
DQ9_A
x16 x8
NC
NC
FBC_D23
FBC_D20
FBC_D22
FBC_D21
U11
V12
U12
U13
DQ8_B
DQ9_B
DQ10_B
TCK
TDI
TDO
N5
F10
N10
SNN_FBCL_TCK_M
SNN_FBCL_TDI_M
SNN_FBCL_TDO_M
T39
T40
T41
G12
G14
G3
VSS
VSS
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
C11
C14
C4
DQ10_A NC DQ11_B F5 SNN_FBCL_TMS_M H11 E1
Frame Buffer C FBC_D12
FBC_D13
FBC_D9
FBC_D11
B13
E12
E13
DQ11_A
DQ12_A
DQ13_A
NC
NC
NC
FBC_D18
FBC_D19
FBC_D17
FBC_D16
P12
P13
N13
DQ12_B
DQ13_B
DQ14_B FBC_CMD4 L3 CA0_B
TMS T37
H4
L11
L4
VSS
VSS
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
E14
F11
F4
F13 NC M13 DQ15_B FBC_CMD12
FBC_D10 DQ14_A M11 CA1_B M1 VSS VDDQ H1
G13 NC FBC_CMD5
DQ15_A FBC_EDC2 M4 CA2_B M12 VSS VDDQ H14
T13 EDC1_B FBC_CMD13
FBC_EDC1 FBC_DBI2 L12 CA3_B M14 VSS VDDQ J13
C13 EDC1_A GND R13 DBI1_B FBC_CMD7
FBC_DBI1 L5 CA4_B M3 VSS VDDQ J2
D13 DBI1_A FBC_CMD11
NC FBC_W CK23 L10 CA5_B N1 VSS VDDQ K13
R11 WCK1_t_B FBC_CMD15
FBC_W CKB01 FBC_W CK23* K12 CA6_B N12 VSS VDDQ K2
D11 WCK1_t_A NC R10 WCK1_c_B FBC_CMD14
FBC_W CKB01* K11 CA7_B N14 VSS VDDQ L1
C D10 WCK1_c_A NC FBC_CMD3 C
K4 CA8_B N3 VSS VDDQ L14
FBC_CMD1 K3 P11 N11
CA9_B VSS VDDQ
FBC_CMD6 K5 P4 N4
U_MEM_SG_GDDR6 U_MEM_SG_GDDR6 CABI_B VSS VDDQ
FBC_CMD10 M10 R1 P1
P/N = P/N = CKE_B VSS VDDQ
ZQ_A J14 FBC_ZQ_1_A R12 VSS VDDQ P14
Close to DRAM FBVDDQ ZQ_B K14 FBC_ZQ_1_B R14 VSS VDDQ T1
FBVDDQ FBVDDQ R3 VSS VDDQ T11
T10 VSS VDDQ T14
R279 R278 T12 VSS VDDQ T4
FBC_CMD2 J1 T3 U10
RESET VSS VDDQ
121_1%_04 121_1%_04 T5 VSS VDDQ U5
C568 C450 C781 C793 C784 C451
U1 VSS
U14 VSS
10u_4V_X6S_06

10u_4V_X6S_06

10u_4V_X6S_06

10u_4V_X6S_06

10u_4V_X6S_06

10u_4V_X6S_06
K10 CLK_c V11 VSS
16 FBC_CLK0*
J10 CLK_t V13 VSS
16 FBC_CLK0 1V8_AON
V2 VSS
V4 VSS
G5 SNN_FBCL_RFU_A_M
RFU_A T35
M5 SNN_FBCL_RFU_B_M A10
RFU_B T38 VPP
VPP A5
VPP V10
VPP V5
Around DRAM OPTION, Under DRAM
Around DRAM FBVDDQ 1V8_AON
FBVDDQ U_MEM_SG_GDDR6
C768 C767 C766 C765
U_MEM_SG_GDDR6 P/N =
P/N =

1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04
C711
B C757 C702 C800 C675 C673 C739 B

4.7u_6.3V_X6S_06
FBVDDQ
22u_6.3V_X6S_08

22u_6.3V_X6S_08

22u_6.3V_X6S_08

22u_6.3V_X6S_08

22u_4V_X6S_06

22u_6.3V_X6S_08

R755

*549_1%_04

FBC_VREFC
FBC_VREFC 18
FBVDDQ FBVDDQ
R756 C674
C717 C720 C703 C794 C783 C756 C744 C698 C799 C795 C802 C178 R311
Right under DRAM Right under DRAM
*931_1%_04 *820p_50V_X7R_04
1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04

1K_1%_04

D
Q68
G *MTN2002ZS3
12,14,23 GPIO10_FBVREF_SEL

S
FBVDDQ FBVDDQ
A C177 C174 C171 C168 C685 C779 C725 C791 C804 C798 C797 C710 A
Close to DRAM Close to DRAM 10,12,13,14,15,18,20,21,22,23,24,25,58,61,62,78 1V8_AON
11,12,13,14,15,16,18,19,25,61 FBVDDQ
1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04

1u_6.3V_X6S_04

ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Title
[17]MEMORY FBC 31..0
Size Document Number Rev
R9.1
A3 SCHEMATIC1
6-71-NH500-D02
Date: W ednesday, December 05, 2018 Sheet 17 of 78
5 4 3 2 1

B - 18 Frame Buffer C
Schematic Diagrams

Frame Buffer C
5 4 3 2 1

FBC_W CK45
FRAME BUFFER PARTITION C 63..32 16
16
16
FBC_W CK45
FBC_W CK45*
FBC_W CK67
FBC_W CK45*
FBC_W CK67
16 FBC_DBI[7..4]
FBC_DBI[7..4]

FBC_EDC[7..4]
M11D FBVDDQ

VRAM=K4G80325FB-HC03, HC28 16 FBC_W CK67*


FBC_W CK67* 16 FBC_EDC[7..4]
FBC_CMD[31..16]
FBC_W CKB45 16 FBC_CMD[31..16]
16 FBC_W CKB45 FBC_W CKB45* FBC_CMD33
M11A M11B A11 VSS VDD A1
16 FBC_W CKB45* FBC_W CKB67 16 FBC_CMD33
A13 VSS VDD A14
16 FBC_W CKB67 FBC_W CKB67* FBC_D[63..32] A2 VSS VDD E10
NORMAL NORMAL 16 FBC_W CKB67* 16 FBC_D[63..32]
A4 VSS VDD E5
FBC_D38 B1 VSS VDD H13
B4 x16 x8 M11C
FBC_D34 DQ0_A FBC_D56 B14 VSS VDD H2
A3 U4 DQ0_B NC
D FBC_D36 DQ1_A FBC_D57 C10 VSS VDD L13 D
B3 V3 DQ1_B NC
FBC_D39 DQ2_A FBC_D58 C12 VSS VDD L2
B2 U3 DQ2_B NC FBC_CMD20
FBC_D35 DQ3_A FBC_D59 H3 CA0_A VREFC K1 C3 VSS VDD P10
E3 U2 DQ3_B NC FBC_CMD28 FBC_VREFC 17
FBC_D32 DQ4_A FBC_D60 G11 CA1_A C5 VSS VDD P5
E2 P3 DQ4_B NC FBC_CMD21
FBC_D33 DQ5_A FBC_D61 G4 CA2_A D1 VSS VDD V1
F2 P2 DQ5_B NC FBC_CMD29
FBC_D37 DQ6_A FBC_D62 H12 CA3_A D12 VSS VDD V14
G2 N2 DQ6_B NC FBC_CMD23
DQ7_A FBC_D63 H5 CA4_A D14 VSS
M2 DQ7_B NC FBC_CMD27
FBC_EDC4 H10 CA5_A D3 VSS
C2 EDC0_A FBC_CMD30
FBC_DBI4 FBC_EDC7 J12 CA6_A E11 VSS
D2 DBI0_A T2 EDC0_B GND FBC_CMD31 FBVDDQ
FBC_DBI7 J11 CA7_A E4 VSS
R2 DBI0_B NC FBC_CMD19
FBC_W CK45 J4 CA8_A F1 VSS
D4 WCK0_t_A FBC_CMD17
FBC_W CK45* FBC_W CKB67 J3 CA9_A F12 VSS
D5 WCK0_c_A R4 WCK0_t_B NC FBC_CMD22
FBC_W CKB67* J5 CABI_A F14 VSS VDDQ B10
R5 WCK0_c_B NC FBC_CMD26 G10 CKE_A F3 VSS VDDQ B5
G1 C1

B.Schematic Diagrams
x16 x8 FBC_D51 U11 VSS VDDQ
DQ8_B N5 SNN_FBCU_TCK_M G12 C11
FBC_D40 B11 FBC_D50 V12 TCK T53 VSS VDDQ
DQ8_A
NC DQ9_B F10 SNN_FBCU_TDI_M G14 C14
FBC_D43 A12 FBC_D48 U12 TDI T47 VSS VDDQ
DQ9_A NC DQ10_B N10 SNN_FBCU_TDO_M G3 C4
FBC_D46 B12 FBC_D49 U13 TDO T46 VSS VDDQ
NC DQ11_B SNN_FBCU_TMS_M
F5 H11 E1
Sheet 18 of 73
FBC_D42 DQ10_A FBC_D53 TMS VSS VDDQ
B13 NC P12 DQ12_B T51
FBC_D44 DQ11_A FBC_D52 H4 VSS VDDQ E14
E12 NC P13 DQ13_B
FBC_D45 DQ12_A FBC_D55 L11 VSS VDDQ F11
E13 NC N13 DQ14_B FBC_CMD16
FBC_D47 DQ13_A FBC_D54 L3 CA0_B L4 VSS VDDQ F4
F13 M13

Frame Buffer C
DQ14_A NC DQ15_B FBC_CMD25 M11 M1 H1
FBC_D41 G13 CA1_B VSS VDDQ
DQ15_A NC FBC_CMD24 M4 M12 H14
FBC_EDC6 T13 CA2_B VSS VDDQ
EDC1_B FBC_CMD33 L12 M14 J13
FBC_EDC5 C13 FBC_DBI6 R13 CA3_B VSS VDDQ
EDC1_A GND DBI1_B FBC_CMD23 L5 M3 J2
FBC_DBI5 D13 CA4_B VSS VDDQ
DBI1_A FBC_CMD27 L10 N1 K13
NC FBC_W CK67 R11 CA5_B VSS VDDQ
WCK1_t_B FBC_CMD30 K12 N12 K2
FBC_W CKB45 D11 FBC_W CK67* R10 CA6_B VSS VDDQ
WCK1_t_A NC WCK1_c_B FBC_CMD31 K11 N14 L1
FBC_W CKB45* D10 CA7_B VSS VDDQ
C WCK1_c_A NC FBC_CMD19 K4 N3 L14 C
CA8_B VSS VDDQ
FBC_CMD17 K3 P11 N11
CA9_B VSS VDDQ
FBC_CMD22 K5 P4 N4
U_MEM_SG_GDDR6 U_MEM_SG_GDDR6 CABI_B VSS VDDQ
FBC_CMD26 M10 R1 P1
P/N = P/N = CKE_B VSS VDDQ
ZQ_A J14 FBC_ZQ_2_A R12 VSS VDDQ P14
ZQ_B K14 FBC_ZQ_2_B R14 VSS VDDQ T1
R3 VSS VDDQ T11
T10 VSS VDDQ T14
R285 R286 T12 VSS VDDQ T4
FBC_CMD18 J1 T3 U10
RESET VSS VDDQ
121_1%_04 121_1%_04 T5 VSS VDDQ U5
U1 VSS
U14 VSS
K10 CLK_c V11 VSS
16 FBC_CLK1*
J10 CLK_t V13 VSS
16 FBC_CLK1 1V8_AON
V2 VSS
V4 VSS
G5 SNN_FBCU_RFU_A
RFU_A T54
M5 SNN_FBCU_RFU_B A10
RFU_B T50 VPP
VPP A5
VPP V10
VPP V5

U_MEM_SG_GDDR6
U_MEM_SG_GDDR6 P/N =
P/N =

B B

A A
10,12,13,14,15,17,20,21,22,23,24,25,58,61,62,78 1V8_AON
11,12,13,14,15,16,17,19,25,61 FBVDDQ

ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Title
[18]MEMORY FBC 63..32
Size Document Number Rev
R9.1
A3 SCHEMATIC1
6-71-NH500-D02
Date: W ednesday, December 05, 2018 Sheet 18 of 78
5 4 3 2 1

Frame Buffer C B - 19
C

D
A

R9.1
R ev

78
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
C209

C412

C202

C321

*0.47u_4V_X6S_02 *0.47u_4V_X6S_02 *0.47u_4V_X6S_02 *0.47u_4V_X6S_02


of
GND

GND
GND

GND

19
6-71-NH500-D02
C219

C201

C203

C517

[19] GPU Decoupling1

*0.47u_4V_X6S_02 *0.47u_4V_X6S_02 *0.47u_4V_X6S_02 *0.47u_4V_X6S_02


Sheet
8

8
C423
C489

C313

C438

Wednesday, December 05, 2018

*0.47u_4V_X6S_02
*0.47u_4V_X6S_02 *0.47u_4V_X6S_02 1u_4V_X6S_02
C494

C436

C402

C241

Document Number

1u_4V_X6S_02 *0.47u_4V_X6S_02 *0.47u_4V_X6S_02 1u_4V_X6S_02


SCHEMATIC1
C511

C424

C233

C236

*0.47u_4V_X6S_02 1u_4V_X6S_02 *0.47u_4V_X6S_02 *0.47u_4V_X6S_02


Date:
Title

Size
C513

A2
C431

C317

C339

C432

*0.47u_4V_X6S_02
*0.47u_4V_X6S_02 *0.47u_4V_X6S_02 *0.47u_4V_X6S_02 1u_4V_X6S_02
GND
C396

C434

C516
C331

C490
7

7
1V8_AON

1u_4V_X6S_02 1u_4V_X6S_02 1u_4V_X6S_02


FBVDDQ
NVVDD

*0.47u_4V_X6S_02 *0.47u_4V_X6S_02
under GPU

NVVDD
C514

C324

C246

C492

C405

19,20,25,58,59
11,12,13,14,15,16,17,18,25,61

*0.47u_4V_X6S_02 *0.47u_4V_X6S_02 *0.47u_4V_X6S_02 *0.47u_4V_X6S_02 *0.47u_4V_X6S_02


10,12,13,14,15,17,18,20,21,22,23,24,25,58,61,62,78
X)  

NVVDD

19,20,25,58,59
C210

C408

C491

C197

C208

C205

C214

C220

C519

C164

1u_4V_X6S_02 1u_4V_X6S_02 *0.47u_4V_X6S_02 1u_4V_X6S_02 1u_4V_X6S_02 1u_4V_X6S_02 *0.47u_4V_X6S_02 *0.47u_4V_X6S_02 1u_4V_X6S_02 1u_4V_X6S_02
GND

GND

GND

GND

GND

GND

GND

GND

GND

GND
C400

C500

C481

C486

C418

C401

C406

C165

C420
C397

*0.47u_4V_X6S_02 *0.47u_4V_X6S_02 *0.47u_4V_X6S_02 1u_4V_X6S_02 1u_4V_X6S_02 *0.47u_4V_X6S_02 *0.47u_4V_X6S_02 *0.47u_4V_X6S_02 *0.47u_4V_X6S_02


*0.47u_4V_X6S_02
6

6
C415

C211

C327

C307

C304

C198

C302
C325

C518

C318

*0.47u_4V_X6S_02 *0.47u_4V_X6S_02 1u_4V_X6S_02 1u_4V_X6S_02 *0.47u_4V_X6S_02 *0.47u_4V_X6S_02 *0.47u_4V_X6S_02


*0.47u_4V_X6S_02 *0.47u_4V_X6S_02 *0.47u_4V_X6S_02
C326

C316

C207

C206

C215

C217

C487
C328

C435

C413

*0.47u_4V_X6S_02 *0.47u_4V_X6S_02 1u_4V_X6S_02 *0.47u_4V_X6S_02 *0.47u_4V_X6S_02 1u_4V_X6S_02 *0.47u_4V_X6S_02


*0.47u_4V_X6S_02 *0.47u_4V_X6S_02 1u_4V_X6S_02
C226

C336

C488

C485

C428

C502

C335
C493

C478

C499

*0.47u_4V_X6S_02 1u_4V_X6S_02 *0.47u_4V_X6S_02 *0.47u_4V_X6S_02 *0.47u_4V_X6S_02 *0.47u_4V_X6S_02 *0.47u_4V_X6S_02


1u_4V_X6S_02 *0.47u_4V_X6S_02 *0.47u_4V_X6S_02
C305

C311

C251

C340

C323

C322

C484

C409

C482

C425

1u_4V_X6S_02 *0.47u_4V_X6S_02 1u_4V_X6S_02 *0.47u_4V_X6S_02 *0.47u_4V_X6S_02 1u_4V_X6S_02 *0.47u_4V_X6S_02 *0.47u_4V_X6S_02 *0.47u_4V_X6S_02 *0.47u_4V_X6S_02
C512

C474

C308

C495

C332

C245

C476

C199

C250

C422

*0.47u_4V_X6S_02 *0.47u_4V_X6S_02 *0.47u_4V_X6S_02 *0.47u_4V_X6S_02 *0.47u_4V_X6S_02 1u_4V_X6S_02 1u_4V_X6S_02 1u_4V_X6S_02 *0.47u_4V_X6S_02 *0.47u_4V_X6S_02
5

5
C160

C329

C399

C224

C330

C200

C404

C240

C343

C421

*0.47u_4V_X6S_02
1u_4V_X6S_02 1u_4V_X6S_02 1u_4V_X6S_02 *0.47u_4V_X6S_02 1u_4V_X6S_02 1u_4V_X6S_02 *0.47u_4V_X6S_02 1u_4V_X6S_02 *0.47u_4V_X6S_02
C237

C319

C407

C341

C204

C337

C310

C254

C257

C419

*0.47u_4V_X6S_02 *0.47u_4V_X6S_02 *0.47u_4V_X6S_02 *0.47u_4V_X6S_02 *0.47u_4V_X6S_02 1u_4V_X6S_02 *0.47u_4V_X6S_02 *0.47u_4V_X6S_02 1u_4V_X6S_02 1u_4V_X6S_02
C216

C320

C411

C483

C338

C437

C315

C235

C221

C416

1u_4V_X6S_02 1u_4V_X6S_02
1u_4V_X6S_02 *0.47u_4V_X6S_02 1u_4V_X6S_02 1u_4V_X6S_02 1u_4V_X6S_02 *0.47u_4V_X6S_02 1u_4V_X6S_02 *0.47u_4V_X6S_02
C334

C473

C501

C496

C521

C427

C232

C248

C342

*0.47u_4V_X6S_02 *0.47u_4V_X6S_02 1u_4V_X6S_02 *0.47u_4V_X6S_02 1u_4V_X6S_02 *0.47u_4V_X6S_02 *0.47u_4V_X6S_02 1u_4V_X6S_02 1u_4V_X6S_02 C417
*0.47u_4V_X6S_02
4

4
C227

C471

C223

C507

C515

C314

C229

C472

C115

C163
1u_4V_X6S_02 1u_4V_X6S_02
*0.47u_4V_X6S_02 *0.47u_4V_X6S_02 *0.47u_4V_X6S_02 *0.47u_4V_X6S_02 *0.47u_4V_X6S_02 *0.47u_4V_X6S_02 1u_4V_X6S_02 1u_4V_X6S_02
C477

C510

C426

C403

C504

C414

C306

C479

C475

C244
*0.47u_4V_X6S_02 *0.47u_4V_X6S_02 1u_4V_X6S_02 *0.47u_4V_X6S_02 *0.47u_4V_X6S_02 1u_4V_X6S_02 *0.47u_4V_X6S_02 *0.47u_4V_X6S_02 *0.47u_4V_X6S_02 1u_4V_X6S_02
C480

C429

C508

C410

C503

C162

C261

C506

C509

C230
1u_4V_X6S_02 *0.47u_4V_X6S_02
1u_4V_X6S_02 *0.47u_4V_X6S_02 1u_4V_X6S_02 1u_4V_X6S_02 1u_4V_X6S_02 *0.47u_4V_X6S_02 *0.47u_4V_X6S_02 *0.47u_4V_X6S_02
under GPU

C309

C498

C312

C333

C398

C430

C260

C433

C505

C394
X)  

*0.47u_4V_X6S_02 *0.47u_4V_X6S_02 1u_4V_X6S_02 *0.47u_4V_X6S_02 *0.47u_4V_X6S_02 1u_4V_X6S_02 *0.47u_4V_X6S_02 *0.47u_4V_X6S_02 *0.47u_4V_X6S_02 1u_4V_X6S_02
NVVDD

NVVDD
3

3
C676

C789

C788

C786

10u_4V_X6S_06 10u_4V_X6S_06 10u_4V_X6S_06 10u_4V_X6S_06


GND

GND

GND

GND

C469
GPU Decoupling 1

22u_6.3V_X6S_08
C543

C787

C790

C803

GND
10u_4V_X6S_06 10u_4V_X6S_06 10u_4V_X6S_06 10u_4V_X6S_06

C387
22u_6.3V_X6S_08
C562

C297

C442

C391

C552

C298

C544

C553
1u_4V_X6S_02 1u_4V_X6S_02 1u_4V_X6S_02 *0.47u_4V_X6S_02 *0.47u_4V_X6S_02 *0.47u_4V_X6S_02 1u_4V_X6S_02 1u_4V_X6S_02

C1132
GND

GND

GND

GND
22u_6.3V_X6S_08
C344

C353

C551

C258

C349

C259

C345

C545

C468
*0.47u_4V_X6S_02 0.47u_4V_X6S_02 1u_4V_X6S_02 1u_4V_X6S_02 *0.47u_4V_X6S_02 *0.47u_4V_X6S_02 *0.47u_4V_X6S_02 1u_4V_X6S_02
2

2
22u_6.3V_X6S_08
C441

C546

C443

C555

C352

C550

C549
C393

C466
*0.47u_4V_X6S_02 1u_4V_X6S_02 1u_4V_X6S_02 *0.47u_4V_X6S_02 0.47u_4V_X6S_02 1u_4V_X6S_02 1u_4V_X6S_02 22u_6.3V_X6S_08
1u_4V_X6S_02
6x 1uF and 2x 10uF

6x 1uF and 2x 10uF

6x 1uF and 2x 10uF

6x 1uF and 2x 10uF

C775

C388
C390

C300

C351

C301

C554

C395

C470
10u_4V_X6S_06 22u_6.3V_X6S_08

C440

GND
1u_4V_X6S_02 1u_4V_X6S_02 0.47u_4V_X6S_02 1u_4V_X6S_02 *0.47u_4V_X6S_02 *0.47u_4V_X6S_02 1u_4V_X6S_02
1u_4V_X6S_02

C718

C296
10u_4V_X6S_06 22u_6.3V_X6S_08

Place Close to GPU


Place Close to GPU
C392

C548

C346

C520

C556

C467

C389
C561

C758
0.47u_4V_X6S_02 1u_4V_X6S_02 *0.47u_4V_X6S_02 1u_4V_X6S_02 1u_4V_X6S_02 1u_4V_X6S_02 *0.47u_4V_X6S_02
FBVDDQ_GPU

C542
*0.47u_4V_X6S_02
10u_4V_X6S_06 22u_6.3V_X6S_08
Partition A

Partition B

Partition C

Partition D
1

1
C439

C560

C348

C558

C350

C557

C303

C295
C444

C699
1u_4V_X6S_02 *0.47u_4V_X6S_02 1u_4V_X6S_02 1u_4V_X6S_02 1u_4V_X6S_02 *0.47u_4V_X6S_02 *0.47u_4V_X6S_02 10u_4V_X6S_06 22u_6.3V_X6S_08
*0.47U_4V_X6S_02
FBVDDQ

B - 20 GPU Decoupling 1
C

D
A

B
Schematic Diagrams

GPU Decoupling 1
Sheet 19 of 73
B.Schematic Diagrams
B.Schematic Diagrams
GPU Decoupling 2 B - 21
Schematic Diagrams

GPU Decoupling 2
Sheet 20 of 73

D
A

R9.1
R ev

78
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/

of
20
6-71-NH500-D02
[20] GPU Decoupling2

Sheet
8

8
Wednesday, December 05, 2018
C123

C527

1u_4V_X6S_02
0.47u_4V_X6S_02
GND

Document Number
C801

SCHEMATIC1

1u_4V_X6S_02
C361

0.47u_4V_X6S_02
C689

C122

Date:
Title

Size

0.47u_4V_X6S_02
A2

*0.47u_4V_X6S_02
C262
GND

0.47u_4V_X6S_02
C679

C736

0.47u_4V_X6S_02
C265

C708

0.47u_4V_X6S_02
7

7
1V8_RUN
1V8_AON

0.47u_4V_X6S_02 0.47u_4V_X6S_02
FBVDDQ
C764

GND

GND
C1136
Under the GPU

*0.47U_4V_X6S_02
0.47u_4V_X6S_02
NVVDD
C1135
C524

10,11,21,23,62

11,12,13,14,15,16,17,18,19,25,61
C355

10,12,13,14,15,17,18,21,22,23,24,25,58,61,62,78
C777

0.47u_4V_X6S_02 0.47u_4V_X6S_02
1u_4V_X6S_02
1u_4V_X6S_02
19,25,58,59
C569

C759

C750
C714

4.7u_6.3V_X6S_06 *0.47U_4V_X6S_02 0.47u_4V_X6S_02


0.47u_4V_X6S_02
C1148
C563

C984

C564

4.7u_6.3V_X6S_06 0.47u_4V_X6S_02 4.7u_6.3V_X6S_06 0.47u_4V_X6S_02


1V8_AON

C1149

C1138
C951

C776
Near the GPU

Near the GPU

4.7u_6.3V_X6S_06 0.47u_4V_X6S_02 4.7u_6.3V_X6S_06 4.7u_6.3V_X6S_06


1V8_AON

1V8_AON
6

6
1V8_AON

1V8_AON
C37

C92

10u_4V_X6S_06 10u_4V_X6S_06
C48

C59

10u_4V_X6S_06 10u_4V_X6S_06
5

5
C93

C38

10u_4V_X6S_06 10u_4V_X6S_06
C94

C61

10u_4V_X6S_06 10u_4V_X6S_06
10u_4V_X6S_06
C95

C40

10u_4V_X6S_06

Raven modfiy 0919


10u_4V_X6S_06
C45

C41

10u_4V_X6S_06
10u_4V_X6S_06
C58

C39

10u_4V_X6S_06
C945

10u_4V_X6S_06
4

4
10u_4V_X6S_06
C46

C42

10u_4V_X6S_06

PC284
470u_2V_SMD-V
C43

NVVDD
10u_4V_X6S_06

GND
10u_4V_X6S_06
C47

C62

10u_4V_X6S_06
C936

C166

10u_4V_X6S_06
Near the GPU

C60

Near the GPU


10u_4V_X6S_06 10u_4V_X6S_06
GND

GND

GND
NVVDD
X) 

X) 
3

3
GPU Decoupling 2
2

2
C937
22u_6.3V_X6S_08
GPU DECOUPLING

C167
47u_2.5V_X6S_08

C49
22u_4V_X6S_06

C929
47u_2.5V_X6S_08

C935
22u_4V_X6S_06

Near the GPU

Near the GPU


C938
47u_2.5V_X6S_08
1

1
GND

C44
22u_4V_X6S_06

NVVDD

GND
X) 
NVVDD
X) 

D
A

B
Schematic Diagrams

Straps and XTAL


1 2 3 4 5

22 GPU_PLLVDD
G1V
?
XTAL
BGA2228
COMMON
30ohm ESR 10mohm bead
13/22 XTAL/PLL

GPU_PLLVDD
1V8_RUN L3 . HCB1608KF-300T60 40mil BD12 SP_PLLVDD

Near to GPU
C192 C193
20mil BC12 VID_PLLVDD

0.47u_4V_X6S_02

0.47u_4V_X6S_02
A 22u_6.3V_X6S_08 4.7u_6.3V_X6S_06 C140 C141 A

GND
GND
Strap 2 Strap 1 Strap 0 RAMCFG[4:0] GPU under GPU near 40mil U42 GPCPLL_AVDD0
0 0 0 0 (0x0000)
AF11 GPCPLL_AVDD1
0 0 1 1 (0x0001)

0.47u_4V_X6S_02

*0.47u_4V_X6S_02

0.47u_4V_X6S_02
0 1 0 2 (0x0002) C139 C522 C299 BB24 XSN_PLLVDD
B.Schematic Diagrams

1V8_AON
0 1 1 3 (0x0003)
1 0 0 4 (0x0004) 1V8_RUN
1 0 1 5 (0x0005)
1 1 0 6 (0x0006) R70
100K_04
1 1 1 7 (0x0007) R86
0 0 M 8 (0x0008) *100K_1%_04

Sheet 21 of 73 0
0
M
M
0
1
9 (0x0009)
10 (0x000A)
GPU under
GND
XTALSSIN

R90
BJ6

BL6
EXT_REFCLK_FL

XTALIN
XTALOUTBUFF BK6

XTALOUT BM6
XTALOUTBUFF

0 1 R73

Straps and XTAL M


M
0
0
M
0
1
11 (0x000B)
12 (0x000C)
13 (0x000D)
10K_04

Co-Lay
X3 fsx3m
XTALOUT
100K_04

B
4 3 B
GND
M 1 0 14 (0x000E) XTALIN 1 2
GND
M 1 1 15 (0x000F)

10p_50V_NPO_04
GND
C948

C947
U83-076_27MHZ 6-22-27R00-1BG GND
1 0 M 16 (0x0010) 6-22-27R00-1BH
10p_50V_NPO_04
1 M 0 17 (0x0011)
1
1
M
1
1
M
18 (0x0012)
19 (0x0013) D03 Raven modfiy 0417
XTAL
GND GND
0 M M 20 (0x0014) 1 = HIGH : Tied to 1.8V
M 0 M 21 (0x0015) M = Middle : Tied to 0.9V
M M 0 22 (0x0016) 0 = Low : Tied to 0V
M M 1 23 (0x0017)
M 1 M 24 (0x0018)
1
M
M
M
M
M
25 (0x0019)
26 (0x001A) 1:Enable 0:Disable MULTI-LEVEL STRAPS
Strap 2 Strap 1 Strap 0 RAMCFG[4:0] SOR 0/1/2/3 ENABLE
1V8_AON
0 0 0 00000
0 1 0 00010
0 1 1 00011 R506 R505 R504 R495 R494 R507
1 1 0 00110

*100K_04

*100K_04

*100K_04

100K_04

*100K_04

*100K_04
1 1 1 00111 1= SMB_ALT_ADDR Enable 1V8_AON
C C
0= SMB_ALT_ADDR Disable
ROM_SO ROM_SI ROM_SCLK SOR_EXPOSED[3:0] Setting RAM type
23 STRAP0
0 0 0 1111 1= DEVID_SEL Rebrand 23 STRAP1
0 0 1 1110 0= DEVID_SEL Orignal Strap5
R508 R71 R89 23 STRAP2
0 1 0 1101 *100K_1%_04 *100K_1%_04 *100K_1%_04 eDP = L
23 STRAP3
0 1 1 1100 1= PCIE_CFG Low Power Rc Re Gsync= H
23 STRAP4
1 0 0 1011 0= PCIE_CFG High Power
23 VGA_ROM_SI 23 STRAP5
1 0 1 1010 1= VGA_DEVICE Enable 23 VGA_ROM_SO
1 1 1 1000 R502 R501 R500 R492 R493 R503
0= VGA_DEVICE Disable 23 VGA_ROM_SCLK
1 1 M 0000

100K_04

100K_04

100K_04

*100K_04

100K_04

100K_04
Strap 5 Strap 4 Strap 3 SMB_ALT_ADDR DEVID_SEL PCIE_CFG VGA_DEVICE R499 R72 R91
100K_1%_04 100K_1%_04 100K_1%_04
0 0 0 0 0 0 0
0 0 1 eDP ID 0 0 0 1 Rd Rf
0 1 0 0 0 1 0
0 1 1 0 1 0 0 GND
1 0 0 0 0 1 1 GND DG P.65 recommend strap resistor 5%
1 0 1 0 1 0 0 or better , voltage use 1V8_AON
GSYNC ID DG P.73 recommend Pull down resistor 100k
1 1 0 0 1 0 1 10,12,13,14,15,17,18,20,22,23,24,25,58,61,62,78 1V8_AON

1 1 1 0 1 1 0
D 1 1 1 0 1 1 1 D

0 0 M 1 0 0 0 10,11,23,62 1V8_RUN
0 M 0 1 0 0 1
0 1 1 0 1 Setting RAM type
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
M 0 Strap
0 1 M 1 0 1 1 default Samsung K4G41325FE-HC25 E-die 0 X 7 4000MHz 128Mx32
M 0 0 1 1 0 0 Title
M 0 1 1 1 0 1 [21] STRAPS and XTAL
M 1 0 1 1 1 0 Size Document Number Rev
M 1 1 1 1 1 1 A3 SCHEMATIC1 6-71-NH500-D02 D02

Date: W ednesday, December 05, 2018 Sheet 21 of 78


1 2 3 4 5

B - 22 Straps and XTAL


Schematic Diagrams

IFP I/O Interface


1 2 3 4 5

?
G1S

IFP I/O INTERFACE BGA2228


11/22 NVHS
COMMON

G1N NVHS_RX0 AM1


? NVHS_RX0 AN1
BGA2228
COMMON
NVHS_RX1 AN2
NVHS_RX1 AN3
7/22 IFPAB
NVHS_RX2 AR3
modification 0507 Biaggi DL-DVI DVI/HDMI DP NVHS_RX2 AR2

NVHS_RX3 AR1
IFPA_AUX BH11 NVHS_RX3 AT1
SDA SDA
IFPA_AUX BG11 R114
SCL SCL
A
AT10 NVHS_DVDD NVHS_RX4 AT2 A
10K_04 AT9 NVHS_DVDD NVHS_RX4 AT3
IFPA_L3 BF21 AV10 NVHS_DVDD
R98 1K_1%_04 BD23 T XC T XC BG21 PEX_VDD
GND
IFPAB_RSET T XC T XC
IFPA_L3 AV11 NVHS_DVDD NVHS_RX5 AV3
R116 NVHS_RX5 AV2

IFPA_L2 BG23
Need check NV USB3.1 OUTPUT 0_04
AR10
AT11
NVHS_CVDD
AV1
T XD 0 T XD 0 NVHS_CVDD NVHS_RX6
IF_PLLVDD
PLACE AT BALLS
BD21 IFPAB_PLLVDD
T XD 0 T XD 0 IFPA_L2 BH23 -0517 Biaggi C1205 C1206 NVHS_RX6 AW1

1u_6.3V_X6S_04

1u_6.3V_X6S_04
NVHS_RX7 AW2
C107 C104 C100 C106 BF23
T XD 1 T XD 1
IFPA_L1 NVHS_RX7 AW3
IFPA_L1 BE23
1u_4V_X6S_02

1u_4V_X6S_02

1u_4V_X6S_02

*0.47u_4V_X6S_02

T XD 1 T XD 1
NVHS_TX0 AM7
NVHS_TX0 AM8
T XD 2 T XD 2 IFPA_L0 BF24
GND T XD 2 T XD 2 IFPA_L0 BG24 NVHS_TX1 AN7
NVHS_TX1 AN6
R130
AM10 NVHS_HVDD NVHS_TX2 AR6
Raven 0628 10K_04 AM11 AR5
NVHS_HVDD NVHS_TX2
AN10 NVHS_HVDD
AN11 NVHS_HVDD NVHS_TX3 AR7

B.Schematic Diagrams
IFPB_AUX BG12 AR11 NVHS_HVDD AR8
SDA
BH12 NVHS_TX3
SCL IFPB_AUX R129
Raven del 0628 AN9 AT7
NVHS_PLL_HVDD NVHS_TX4
Raven del 0628 10K_04 NVHS_TX4
AT6
IFPB_L3 BL18
BB18 T XC BK18
IFP_IOVDD T XC
IFPB_L3
NVHS_TX5
AV6
BB17 IFP_IOVDD AV5
NVHS_TX5
G1O
BB20
BB21
IFP_IOVDD
IFP_IOVDD
T XD 3
T XD 3
T XD 0
T XD 0
IFPB_L2
IFPB_L2
BK20
BL20
?
BGA2228
COMMON
HDMI NVHS_TX6
NVHS_TX6
AV7
AV8

8/22 IFPC NVHS_TX7 AW7


IFPB_L1 BM20 AW6

Sheet 22 of 73
T XD 4 T XD 1 NVHS_TX7
IFPB_L1 BM21 R96 1K_1%_04 BD20 IFPCD_RSET
T XD 4 T XD 1 GND
DVI/HDMI DP

BL21 40 mil PLACE AT BALLS


ʼnŅŎŊ R524 2.49K_1%_04 NVHS00_TERMP
AM3 NVHS_TERMP AM6
T XD 5 T XD 2 IFPB_L0 IF_PLLVDD NVHS_REFCLK
T XD 5 T XD 2 IFPB_L0 BK21 21 GPU_PLLVDD
L2 . HCB1608KF-300T60 BD18 IFPCD_PLLVDD SDA IFPC_AUX BL9
BK9
HDMI_CTRLDATA 30 NVHS_REFCLK AM5
IFPC_AUX

IFP I/O Interface


SCL HDMI_CTRLCLK 30
IFPAB C145 C103 C101 C142
EXT_REFCLK_SLI
AM2
PEX_VDD IFPC_L3 BF17
B TXC HDMI_CLOCKN 30

0.47u_4V_X6S_02

*0.47u_4V_X6S_02

1u_4V_X6S_02

0.47u_4V_X6S_02
B
PLACE Under GPU IFPC_L3 BE17
HDMI_CLOCKP 30
40 mil TXC

IFPC_L2 BF18 N18E-G3


TXD0 HDMI_DATA0N 30
BG18
4.7u_6.3V_X6S_06

*0.47u_4V_X6S_02

1u_4V_X6S_02

1u_4V_X6S_02

0.47u_4V_X6S_02

TXD0 IFPC_L2 HDMI_DATA0P 30 NVHS RX/TX N/A


C916 C29 C161 C255 C156 GND IFPC IFPC_L1 BG20
TXD1 HDMI_DATA1N 30
TXD1 IFPC_L1 BH20
HDMI_DATA1P 30
IFPC_L0 BF20
TXD2 HDMI_DATA2N 30
PLACE Under GPU PLACE Near GPU IFPC_L0 BE20
TXD2 HDMI_DATA2P 30

GND
BB23 IFP_IOVDD
BC17 IFP_IOVDD
C31 C917
C159
*0.47U_4V_X6S_02 4.7u_6.3V_X6S_06
G1Q
?
BGA2228
DP *0.47u_4V_X6S_02
COMMON modification 0517 Biaggi
10/22 IFPE
RAVEN modfiy 0816

DVI/HDMI DP G1P

R95 1K_1%_04 BD17 IFPE_RSET IFPE_AUX BL8


GND GND
eDP ?
BGA2228
COMMON
GND SDA DP_E_AUX# 72
SCL IFPE_AUX BK8 DP_E_AUX 72 9/22 IFPD

20 mil
PLACE AT BALLS IFPE_L3 BG14 DVI/HDMI DP
IF_PLLVDD TXC DP_E#3 72
BD15 IFPE_PLLVDD IFPE_L3 BH14
TXC DP_E3 72

C147 IFPE_L2 BF14 IFPD_AUX BF11


C102 TXD0 DP_E#2 72 SDA
TXD0 IFPE_L2 BE14 IFPD_AUX BE11
DP_E2 72 SCL
0.47U_4V_X6S_02

0.1u_10V_X7R_04
NV_0201_LARGE

TXD1 IFPE_L1 BF15


DP_E#1 72
TXD1 IFPE_L1 BG15 TXC IFPD_L3 BM14
DP_E1 72
IFPE TXC IFPD_L3 BM15
GND GND BG17
TXD2 IFPE_L0 DP_E#0 72
TXD2 IFPE_L0 BH17 IFPD_L2 BL15
DP_E0 72 TXD0
IFPD_L2 BK15
TXD0

PLACE Near GPU PLACE close GPU IFPD IFPD_L1 BK17


TXD1
BC21 BL17
C
PEX_VDD
40 mil BC23
IFP_IOVDD
IFP_IOVDD
TXD1 IFPD_L1 C

IFPD_L0 BM17
TXD2
C914 C152 C153 C158 IFPD_L0 BM18
TXD2
*0.47u_4V_X6S_02

*0.47u_4V_X6S_02

1u_4V_X6S_02

PLACE Near GPU PLACE under GPU


4.7u_6.3V_X6S_06

DP PEX_VDD
BC18
BC20
IFP_IOVDD
IFP_IOVDD

G1R C915 C256 C30

1u_4V_X6S_02

1u_4V_X6S_02
GND GND ?
BGA2228
COMMON 4.7u_6.3V_X6S_06
6/22 IFPF/USB-C

USB-C DP
GND
R118
BB15 USB_DVDD IFPF_AUX BM9
SBU2
10K_04 BC15 USB_DVDD IFPF_AUX BM8
SBU1

RX1 IFPF_L3 BK11


RX1 IFPF_L3 BL11

TX1 IFPF_L2 BM11


TX1 IFPF_L2 BM12

TX2 IFPF_L1 BL12


R115 IFPF_L1 BK12
TX2
AW10 USB_HVDD
1V8_AON 10K_04 AW11 BK14
ŮŪůŪġ ġ ŅőŠŇ
USB_HVDD RX2 IFPF_L0
Near the GPU
R128 Under the GPU IFPF_L0 BL14
RX2
AW9 USB_PLL_HVDD
0_04
1u_4V_X6S_02

*0.47u_4V_X6S_02

C196 C194 C195 USB_L0 BA1


USB_L0 BA2
22u_4V_X6S_06
USB_L1 BA7
USB_L1 BA8
R92
BE12 USB_VDDP
D GND GND GND 10K_04 D

USB_SCL BB8
USB_SDA BB7

R76 2.49K_1%_04 BG6


ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
USB_TERMP0

R77 2.49K_1%_04 BH6 USB_TERMP1


Title
R93 1K_1%_04 BA6 USB_RBIAS [22] IFP I/O Interface
IFPF/USB-C 10,12,13,14,15,17,18,20,21,23,24,25,58,61,62,78 1V8_AON Size Document Number Re v
4,23,24,31,32,34,37,40,41,43,45,47,48,49,50,51,54,55,57,58,59,60,61,62,65,74,77,78
10,60 PEX_VDD
VDD3 Custom SCHEMATIC1 6-71-NH500-D02 D02
GND
Date: Wednesday, December 05, 2018 Sheet 22 of 78
1 2 3 4 5

IFP I/O Interface B - 23


Schematic Diagrams

Misc - GPIO, I2C and ROM


1 2 3 4 5 6 7 8

G1U
?
1V8_AON MISC: GPIO, I2C, and ROM
BGA2228
COMMON

14/22 MISC 2
R518 1V8_AON VBIOS ROM 1M
ROM_CS BJ4 VGA_ROM_CS# 10K_04 (OPTIMUS)
BK2 VGA_ROM_SI 1V8_AON
ROM_SI VGA_ROM_SI 21 DP_E INS28107254
ROM_SO BK4 VGA_ROM_SO SO8
BL3 BK3 VGA_ROM_SCLK VGA_ROM_SO 21 R520 SO8 U28
GPIO18_IFPE_HPD_R
21
21
STRAP0
STRAP1
BL4
STRAP0
STRAP1
ROM_SCLK VGA_ROM_SCLK 21 Zdiff=50ȍ 10K_04 7
COMMON
8
BM4 STRAP2 HOLD VCC
21 STRAP2 3

C
BM5 STRAP3 WP
21 STRAP3 VGA_ROM_CS# R519 IVGA_ROM_CS#_R 1
33.2_1%_04
BK5 STRAP4 B R510 100K_04 CS
21 STRAP4
21 STRAP5
BJ5 STRAP5 Q79
MDP_E_HPD 35,73  
 VGA_ROM_SI IVGA_ROM_SI 5
C949
R497 33.2_1%_04
  

A SI 0.1u_6.3V_X5R_02 A

R509

C952
BTN3904 VGA_ROM_SO R521 0_04 IVGA_ROM_SO_R 2

E
M-SOT23-CBE SO
VGA_ROM_SCLK R496 IVGA_ROM_SCLK 6
33.2_1%_04 4
SCK GND
BUFRST BF9 GPU_BUFRST#
W25Q80EWSNIG

220p_50V_NPO_04
NV3V3 1V8_RUN NV3V3

100K_04
R787 R134
*10K_04 10K_04

R145 R143
1V8_RUN 10K_04 10K_04
1V8_AON
B.Schematic Diagrams

*0.1u_10V_X7R_04 C190
GND
R108 Q25A
R109

2
0_04 R103 *10K_04 MTDK3S6R

G
*0_04 NV3V3
24,35 DGPU_RST#_PCH I2CC_SCL I2CC_SCL_P
The GPU does not support multiple 1 6
I2CC_SCL_P 24
G1T Q22A masters on its I2C Buses.
R104 4.75K_1%_04

2
MTDK3S6R

D
G
?
Q25B

5
BGA2228 R105 4.75K_1%_04

G
COMMON
1 6 SMC_VGA_THERM MTDK3S6R
SMC_VGA_THERM 47,74 I2CC_SDA I2CC_SDA_P
12/22 MISC 1 4 3
I2CC_SDA_P 24

D
slave Q22B

D
G
Sheet 23 of 73 24 OVERT#
OVERT#

TS_VREF
BG5 OVERT I2CS_SCL BJ8 SMC_VGA_THERM1 R782
I2CS_SDA BH8
SMD_VGA_THERM1 R781
33.2_1%_04
4
33.2_1%_04
MTDK3S6R
3 SMD_VGA_THERM
SMD_VGA_THERM 47,74

D
BF12 TS_VREF
I2CC_SCL BG9 R74 33.2_1%_04 I2CC_SCL 1V8_AON

Misc - GPIO, I2C B


I2CC_SDA BH9

I2CB_SCL BG8
R75

R783
33.2_1%_04 I2CC_SDA

33.2_1%_04 I2CB_SCL
33.2_1%_04 I2CB_SDA
master

C1000
FP_FUSE_GPU 25

B
I2CB_SDA BF8 R784

2.2u_6.3V_X5R_04
C191 R536

and ROM BJ1

BJ2
THERMDN

THERMDP
1V8_AON
Raven modfiy 0726

R515
R526
2.2u_6.3V_X5R_04

2
U30
4
2.2K_04

10K_04 VIN VOUT


10K_04 3 5
NC VBIAS 3.3VS
GPIO26_FP_FUSE
GPIO0 BD6 6 1 C999
BB5 GPIO1_GC6_FB_EN GPIO0_NVVDD_PWM_VID 58 ON GND
GPIO1 R527 0_04
GPIO2_GPU_EVENT# GPIO1_GC6_FB_EN_R 24
GPIO2 BD1 FA7609A6 0.1u_6.3V_X5R_02
BJ9 ADC_IN GPIO3 BE4 D42 A C RB751V-40(lision) R535 P/N = 6-15-76096-7E0
78 ADC_IN_P BJ11 BE1 GPIO4_1V8_MAIN_EN GPU_EVENT# 35
78 ADC_IN_N ADC_IN GPIO4 GPIO4_1V8_MAIN_EN 24
BG2 GPIO5_FRAME_LOCK#
GPIO5 The error was caused by PB50EF_D01_20180521A.DSN 10K_04
BD2 GPIO6_NVVDD_PSI# 0606 Biaggi
GPIO6
BD7 GPIO7_BL_PWM_GPU
GPIO7
BH4 GPIO8_MEM_VDD_CTL 1V8_AON
GPIO8 GPIO8_MEM_VDD_CTL 61 Raven modfiy 0726
BJ3 GPIO9_THERM_ALERT#
GPIO9
BD3 GPIO10_ALT_MEM_VREF
GPIO10
GPIO10_FBVREF_SEL 12,14,17 R107 10K_04 GPIO12_AC_DETECT_R
BK24 BH3 GPIO11_PPEN
JTAG_TCK GPIO11
BL23 BE6 GPIO12_AC_DETECT_R
JTAG_TMS GPIO12 GPU_PEX_RST# R514 10K_04 GPIO4_1V8_MAIN_EN
BM23 BB1
JTAG_TDI GPIO13 R513 10K_04 GPIO5_FRAME_LOCK#
BM24 BG4
JTAG_TRST
JTAG_TDO GPIO14 R537 10K_04 GPIO9_THERM_ALERT#
BL24 JTAG_TRST GPIO15 BG1
BE2 GPIO16_FAN_A_PWM Q54A R538 10K_04 OVERT#

2
GPIO16 *MTDK3S6R R517 10K_04 GPIO16_FAN_A_PWM

G
GPIO17 BH1
R489 BE3 GPIO18_IFPE_HPD_R
GPIO18 GPIO9_THERM_ALERT# 1 6
10K_04 BK23 NVJTAG_SEL GPIO19 BD4 The error was caused by PB50EF_D01_20180521A.DSN d_GPIO9_ALERT_FAN 47
BE5 GPIO20_FL_SYNC_GPU_FGC6 0606 Biaggi
GPIO20

D
BA5 GPIO21_RASTER_SYNC0
GPIO21
R97 GPIO22 BB6
R557 0_04
10K_04 GPIO23 BG3
R554 *10K_04 VDD3
GPIO24 BD5

D
BB2 GPIO25_FBVDD_PSI#
GND GPIO25 OVERT# 4 3
BE7 GPIO26_FP_FUSE dGPU_GPIO8_OVERT 47 1V8_AON
GPIO26
BA4 GPIO27_IFPC_HPD_R
GPIO27
BB4 GPIO28_OC_WARN# *MTDK3S6R
GPIO28 1.5K_1%_04 I2CB_SCL

G
GND
BA3 GPIO29_IDLE_IN_SW GPIO28_OC_WARN# 78 Q54B R785

5
C GPIO29 R786 1.5K_1%_04 I2CB_SDA C
GPIO30 BB3 GPU_PEX_RST#
DG P.279 Note: GPIO can 3V3 input ,
1V8_RUNDG P.261 use 2.2k pull-up
and can not drive a 3V3 levelin push-pull mode.
on both I2C_SDA/SCL
GPU_PEX_RST# 10,24 R133 1.5K_1%_04 I2CC_SCL
R132 1.5K_1%_04 I2CC_SDA
1V8_AON

19 UHVHUYH 1V8_AON


C67 *470p_50V_X7R_04
C66 *470p_50V_X7R_04
R149 R166
10K_1%_04 *10K_1%_04 R167 *300K_1%_04 GPIO25_FBVDD_PSI#_R 61
R151 *300K_1%_04 1V8_AON
GPIO6_NVVDD_PSI#_R 58
U9 GPIO20_FL_SYNC_GPU_FGC6 R106 10K_04

C
SN74LV1T32DCKR

5
GPIO25_FBVDD_PSI#
C

R275 *10K_1%_04 B Q36 1


GPIO6_NVVDD_PSI# *BTN3904 GPIO12_AC_DETECT_R 4 VBATT_BOOST# 47
R163 *10K_1%_04 B Q26 GPIO29_IDLE_IN_SW
R148 2 R126 10K_04
*BTN3904 AC/BATL# 57

E
0_04
GPIO6_NVVDD_PSI# GPIO6_NVVDD_PSI#_R
E

R165 C683

3
R150 C541 *10K_1%_04 *0.1u_6.3V_X5R_04 GPIO7_BL_PWM_GPU
R164 R125 100K_04
10K_1%_04 *0.1u_6.3V_X5R_04 GPIO10_ALT_MEM_VREF R498 100K_04
0_04
GPIO25_FBVDD_PSI# GPIO25_FBVDD_PSI#_R GPIO11_PPEN R516 100K_04
GPIO8_MEM_VDD_CTL R111 *10K_04
GPIO21_RASTER_SYNC0 R113 100K_04

NV ⺢嬘 HDMI
HDMI
GPIO27_IFPC_HPD_R

R127 10K_04 1V8_AON


D Q23 D
BTN3904
C

M-SOT23-CBE
B R147 100K_04
HDMI_HPD 30,35
R146 100K_04
E

C380 220p_50V_NPO_04
C381 *220p_50V_NPO_04

10,30,58,61,62,78
4,24,31,32,34,37,40,41,43,45,47,48,49,50,51,54,55,57,58,59,60,61,62,65,74,77,78
NV3V3
VDD3
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Title
10,11,21,62
2,24,29,42,44,49,50,52,53,56,59,60,61,72,73
1V8_RUN
3.3V
[23] Misc-GPIO_I2C_ROM
10,12,13,14,15,17,18,20,21,22,24,25,58,61,62,78 1V8_AON Size Document Number Rev
8,9,24,27,29,30,31,32,33,34,35,36,39,40,41,43,44,45,47,49,50,54,61,74,77 3.3VS Custom SCHEMATIC1 6-71-NH500-D02 D02

Date: Wednesday, December 05, 2018 Sheet 23 of 78


1 2 3 4 5 6 7 8

B - 24 Misc - GPIO, I2C and ROM


Schematic Diagrams

NVIDIA Power Sequence


1 2 3 4 5 6 7 8

VDD3
U10
24,47,54,57,58
23
SMC_BAT
I2CC_SCL_P
2
11 0B0
1B0
VCC
12
DEFAULT HW POWER SEQUENCE
1
DGPU_PWR_EN A0 I2CC_SCL_PP 58,61
R144 *0_04 10 3
S0 GND
5 9
24,47,54,57,58 SMD_BAT 0B1 VCC 3.3V U5
8 Raven add 0809
23 I2CC_SDA_P 1B1 4
A1 I2CC_SDA_PP 58,61
7 6 1 20
S1 GND VDD FBVDDQ_EN NV_FBVDDQ_EN 61
*PI5A3158BZAE 2 19
24,34 NV_EN_DOWN VIN_DOWN PEX_VDD_EN NV_PEXVDD_EN 60
A 3 18 NV_NVVDDS_EN Raven modfiy 0726 A
23 OVERT# OVERT# NVVDDS_EN
4 17
62 1V8_AON_PWRGD SUSB# NVVDD_EN NV_NVVDD_EN 58,59
NVVDDS_PWRGD 5 16
The error was caused by PB50EF_D01_20180521A.DSN NVVDDS_PWRGD 3V3_SYS_EN NV_NV3V3_EN 62
R839 *0_04 VDD3 0606 Biaggi
D02 0919 Add for EC flash PWR IC 6 15
DGPU_PWR_EN 23 GPIO1_GC6_FB_EN_R GC6_FB_EN 1V8_MAIN_EN NV_1V8RUN_EN 59,62
R838 *0_04
PU28 7 14
VDD3 FA8202AOTR From EC 35,47 GC6_FB_EN_PCH GC6_FB_EN_PCH 1V8_AON_EN NV_1V8AON_EN 62
1 8 R837 0_04 8 13
GND EN EC_GPIO 47,54,58,61 31,32,45 PLT_RST# PLT_RST# GPIO4_1V8_MAIN_EN GPIO4_1V8_MAIN_EN 23,24
㍍ EC SM_BUS PULL 䘬 2 7 9 12
暣 㸸 VREF1 VREF2 VDD3 23,35 DGPU_RST#_PCH dGPU_RST#_PCH dGPU_PWR_EN DGPU_PWR_EN 35,47
㍍ GPU SM_BUS PULL 䘬
暣 㸸 ?? 10 11 1V8_AON
SMC_BAT I2CC_SCL_PP 10,23 GPU_PEX_RST# GPU_PEX_RST# GND
3 6
24,47,54,57,58 SMC_BAT A1 B1 GPU_PEX_RST# R50 10K_04
GND

B.Schematic Diagrams
SMD_BAT 4 5 I2CC_SDA_PP SLG4U41681_new
24,47,54,57,58 SMD_BAT A2 B2 GPU_PEX_RST# R49 *100K_04
EC SM_BUS GPU SM_BUS
9

DGPU_PWR_EN R51 100K_04


C A NVVDDS_PWRGD
10,58 NVVDD_PWRGD GC6_FB_EN_PCH
D13 RB751V-40(lision) R47 *100K_04

The error was caused by PB50EF_D01_20180521A.DSN DGPU_RST#_PCH R48 100K_04


0606 Biaggi

Sheet 24 of 73
NVIDIA Power
B
HW POWER DOWN SEQUENCE B

NVIDIA GPIO LEVEL SHIFT NV_1V8RUN_EN


NV_NV3V3_EN
NV_NVVDD_EN
Sequence

D
D

D
NV_EN_DOWN Q13
G
NV_EN_DOWN Q14 *2SK3018S3
24,34 NV_EN_DOWN G

S
*2SK3018S3 NV_EN_DOWN Q11
3.3VS G

S
3.3VS 2SK3018S3
C33

S
3.3VS C50 *0.1u_10V_X7R_04
3.3VS *0.1u_10V_X7R_04 C63
R533 *0.1u_10V_X7R_04
R551
100K_04
100K_04
R550
R532 NV_NVVDDS_EN
Q53A 100K_04 NV_FBVDDQ_EN
35 DGPU_PWRGD_R Q55A 100K_04 NV_PEXVDD_EN
MTDK3S6R 39 GPIO4_1V8_MAIN_EN_R
6

D MTDK3S6R
6

D
D
G2
G2
S NV_EN_DOWN Q9 NV_EN_DOWN Q8
Q53B S Q10 G G
1

Q55B NV_EN_DOWN G
1
3

D MTDK3S6R *2SK3018S3 2SK3018S3


3

D MTDK3S6R *2SK3018S3

S
S
G5
DGPU_PWRGD 61 G5 C52 C51
S GPIO4_1V8_MAIN_EN 23,24 C64
S
4

*0.1u_10V_X7R_04 *0.1u_10V_X7R_04
4

*0.1u_10V_X7R_04

Raven 0628
C C

D D

ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
8,9,23,27,29,30,31,32,33,34,35,36,39,40,41,43,44,45,47,49,50,54,61,74,77 3.3VS
2,29,42,44,49,50,52,53,56,59,60,61,72,73 3.3V
4,23,31,32,34,37,40,41,43,45,47,48,49,50,51,54,55,57,58,59,60,61,62,65,74,77,78 VDD3
10,23,30,58,61,62,78 NV3V3 Title
10,11,21,23,62
10,12,13,14,15,17,18,20,21,22,23,25,58,61,62,78
1V8_RUN
1V8_AON
[24] NVIDIA POWER SEQUENCE
Size Document Number Rev
Custom SCHEMATIC1 6-71-NH500-D02 D02

Date: Wednesday, December 05, 2018 Sheet 24 of 78


1 2 3 4 5 6 7 8

NVIDIA Power Sequence B - 25


Schematic Diagrams

GPU NVVDD, FBVDDQ


1 2 3 4 5 6 7 8

G1I G1J G1L

NVVDD
?
BGA2228
COMMON
NVVDD
NVVDD
?
BGA2228
COMMON
FBVDDQ
NVVDD
?
BGA2228
COMMON
FBVDDQ GPU NVVDD, FBVDDQ
17/22 VDD_1/3 18/22 VDD_2/3 19/22 FBVDDQ

AA13 VDD VDD AE28 AH39 VDD VDD AP23 AA10 FBVDDQ FBVDDQ AT43 G1M
AA14 VDD VDD AE29 AH40 VDD VDD AP24 AA11 FBVDDQ FBVDDQ K12 ?
AA15 VDD VDD AE30 AJ13 VDD VDD AP25 AA42 FBVDDQ FBVDDQ K14 BGA2228
COMMON
AA16 VDD VDD AE31 AJ40 VDD VDD AP26 AA43 FBVDDQ FBVDDQ K15
AA17 VDD VDD AE32 AK13 VDD VDD AP27 AC10 FBVDDQ FBVDDQ K17 NVVDD 22/22 VDD_3/3
NVVDD
AA18 VDD VDD AE33 AK14 VDD VDD AP28 AC11 FBVDDQ FBVDDQ K18
AA19 VDD VDD AE34 AK15 VDD VDD AP29 AC42 FBVDDQ FBVDDQ K20
AA20 VDD VDD AE35 AK16 VDD VDD AP30 AC43 FBVDDQ FBVDDQ K21 BG45 VDD VDD R23
AA21 VDD VDD AE36 AK17 VDD VDD AP31 AD10 FBVDDQ FBVDDQ K23 BG46 VDD VDD R24
A AA22 VDD VDD AE37 AK18 VDD VDD AP32 AD11 FBVDDQ FBVDDQ K24 BG47 VDD VDD R25 A
AA23 VDD VDD AE38 AK19 VDD VDD AP33 AD42 FBVDDQ FBVDDQ K26 BG48 VDD VDD R26
AA24 VDD VDD AE39 AK20 VDD VDD AP34 AD43 FBVDDQ FBVDDQ K27 BG49 VDD VDD R27
AA25 VDD VDD AE40 AK21 VDD VDD AP35 AF10 FBVDDQ FBVDDQ K29 BG50 VDD VDD R28
AA26 VDD VDD AF13 AK22 VDD VDD AP36 AF43 FBVDDQ FBVDDQ K30 BG51 VDD VDD R29
AA27 VDD VDD AF14 AK23 VDD VDD AP37 AG10 FBVDDQ FBVDDQ K32 BG52 VDD VDD R30
AA28 VDD VDD AF15 AK24 VDD VDD AP38 AG11 FBVDDQ FBVDDQ K33 BH44 VDD VDD R31
AA29 VDD VDD AF16 AK25 VDD VDD AP39 AG42 FBVDDQ FBVDDQ K35 BH45 VDD VDD R32
AA30 VDD VDD AF17 AK26 VDD VDD AP40 AG43 FBVDDQ FBVDDQ K36 BH47 VDD VDD R33
AA31 VDD VDD AF18 AK27 VDD VDD AR13 AJ10 FBVDDQ FBVDDQ K38 BH48 VDD VDD R34
AA32 VDD VDD AF24 AK28 VDD VDD AR40 AJ11 FBVDDQ FBVDDQ K39 BH49 VDD VDD R35
AA33 VDD VDD AF25 AK29 VDD VDD AT13 AJ42 FBVDDQ FBVDDQ K41 BH50 VDD VDD R36
AA34 VDD VDD AF26 AK30 VDD VDD AT14 AJ43 FBVDDQ FBVDDQ L14 BH51 VDD VDD R37
AA35 VDD VDD AF30 AK31 VDD VDD AT15 AK10 FBVDDQ FBVDDQ L15 BH52 VDD VDD R38
AA36 VDD VDD AF31 AK32 VDD VDD AT16 AK11 FBVDDQ FBVDDQ L18 BJ44 VDD VDD R39
AA37 AF32 AK33 AT17 AK42 L20 BJ45 R40
B.Schematic Diagrams

VDD VDD VDD VDD FBVDDQ FBVDDQ VDD VDD


AA38 VDD VDD AF33 AK34 VDD VDD AT18 AK43 FBVDDQ FBVDDQ L21 BJ46 VDD VDD T13
AA39 VDD VDD AF34 AK35 VDD VDD AT19 AM42 FBVDDQ FBVDDQ L23 BJ47 VDD VDD T40
AA40 VDD VDD AF40 AK36 VDD VDD AT20 AM43 FBVDDQ FBVDDQ L24 BJ48 VDD VDD U13
AB13 VDD VDD AG13 AK37 VDD VDD AT21 AN43 FBVDDQ FBVDDQ L26 BJ49 VDD VDD U14
AB40 VDD VDD AG19 AK38 VDD VDD AT22 AR42 FBVDDQ FBVDDQ L27 BJ50 VDD VDD U15
AC13 VDD VDD AG20 AK39 VDD VDD AT23 AR43 FBVDDQ FBVDDQ L30 BJ51 VDD VDD U16
AC14 VDD VDD AG21 AK40 VDD VDD AT24 R42 FBVDDQ FBVDDQ L32 BJ52 VDD VDD U17
AC15 VDD VDD AG22 AL13 VDD VDD AT25 R43 FBVDDQ FBVDDQ L33 BK47 VDD VDD U18
AC16 VDD VDD AG23 AL40 VDD VDD AT26 U10 FBVDDQ FBVDDQ L35 BK48 VDD VDD U19
AC17 VDD VDD AG27 AM13 VDD VDD AT27 U11 FBVDDQ FBVDDQ L36 BK49 VDD VDD U20

Sheet 25 of 73 AC18
AC19
AC20
AC21
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
AG28
AG29
AG35
AG36
AM14
AM15
AM16
AM17
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
AT28
AT29
AY26
AY27
U43
V10
V42
V43
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
L39
M10
M43
P10
BK50
BK51
BK52
BL46
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
U21
U22
U23
U24
AC22 AG37 AM18 AY28 Y10 P11 BL47 U25

GPU NVVDD,
VDD VDD VDD VDD FBVDDQ FBVDDQ VDD VDD
AC23 VDD VDD AG38 AM19 VDD VDD AY29 Y11 FBVDDQ FBVDDQ P42 BL48 VDD VDD U26
AC24 VDD VDD AG39 AM20 VDD VDD AY30 Y42 FBVDDQ FBVDDQ P43 BL49 VDD VDD U27
AC25 VDD VDD AG40 AM21 VDD VDD AY31 Y43 FBVDDQ FBVDDQ R10 PLACE WEST EDGE OF FBD BL50 VDD VDD U28
AC26 VDD VDD AH13 AM22 VDD VDD AY32 FBVDDQ R11 BL51 VDD VDD U29
B B

FBVDDQ
AC27 VDD VDD AH14 AM23 VDD VDD AY33 R329 *2.2_04 BL52 VDD VDD U30
FBVDDQ
AC28 VDD VDD AH15 AM24 VDD VDD AY34 BM47 VDD VDD U31
AC29 VDD VDD AH16 AM25 VDD VDD AY35 BM48 VDD VDD U32
AC30 VDD VDD AH17 AM26 VDD VDD AY36 BM49 VDD VDD U33
AC31 AH18 AM27 AY37 FBVDDQ_SENSE_R49 FBVDDQ_SENSE
VDD VDD VDD VDD FBVDDQ_SENSE E52 R328 2.2_04
FBVDDQ_SENSE 61
BM50 VDD VDD U34
AC32 VDD VDD AH19 AM28 VDD VDD AY38 BM51 VDD VDD U35
AC33 AH20 AM29 AY39 R552 2.2_04 FBVDDQ_SENSE_RTN N13 U36
VDD VDD VDD VDD GND FBVDDQ_SENSE_RTN 61 VDD VDD
AC34 VDD VDD AH21 AM30 VDD VDD AY40 N14 VDD VDD U37
AC35 AH22 AM31 AY43 P45 FB_VREF_PROBE PLACE NEAR G1 PIN E52 N15 U38
VDD VDD VDD VDD FB_VREF VDD VDD
AC36 VDD VDD AH23 AM32 VDD VDD AY45 C523 *3.9pF_50V_02 N16 VDD VDD U39
AC37 VDD VDD AH24 AM33 VDD VDD BA43 FBVDDQ N17 VDD VDD U40
AC38 VDD VDD AH25 AM34 VDD VDD BA44 R168 49.9_1%_04 N18 VDD VDD V13
AC39 VDD VDD AH26 AM35 VDD VDD BA45 N19 VDD VDD V40
AC40 VDD VDD AH27 AM36 VDD VDD BA46 N20 VDD VDD W13
AD13 AH28 AM37 BA47 FB_CAL_PD_VDDQ
VDD VDD VDD VDD FB_CAL_PD_VDDQ R44 R153 40.2_1%_04 N21 VDD VDD W14
AD40 VDD VDD AH29 AM38 VDD VDD BB38 N22 VDD VDD W15
AE13 AH30 AM39 BB39 FB_CAL_PU_GND
VDD VDD VDD VDD FB_CAL_PU_GND P44 R154 40.2_1%_04 N23 VDD VDD W16
AE14 VDD VDD AH31 AM40 VDD VDD BB45 N24 VDD VDD W17
AE15 AH32 AN13 BB46 FB_CAL_TERM_GND
VDD VDD VDD VDD FB_CALTERM_GND R45 R139 40.2_1%_04 N25 VDD VDD W18
AE16 VDD VDD AH33 AN40 VDD VDD BB47 N26 VDD VDD W19
AE17 VDD VDD AH34 AP13 VDD VDD BB48 N27 VDD VDD W20
AE18 VDD VDD AH35 AP14 VDD VDD BC38 N28 VDD VDD W21
AE19 VDD VDD AH36 AP15 VDD VDD BC39 GND N29 VDD VDD W22
AE20 VDD VDD AH37 AP16 VDD VDD BC40 N30 VDD VDD W23
AE21 VDD VDD AH38 AP17 VDD VDD BC41 N31 VDD VDD W24
AE22 VDD VDD AV28 AP18 VDD VDD BC45 N32 VDD VDD W25
AE23 VDD VDD AV29 AP19 VDD VDD BC47 N33 VDD VDD W26
AE24 VDD VDD AV30 AP20 VDD VDD BC49 N34 VDD VDD W27
AE25 VDD VDD AV31 AP21 VDD VDD BD39 N35 VDD VDD W28
AE26 VDD VDD AV32 AP22 VDD VDD BE48 N36 VDD VDD W29
AE27 VDD VDD AV33 BD41 VDD VDD BE49 N37 VDD VDD W30
AT30 VDD VDD AV34 BD46 VDD VDD BE50 N38 VDD VDD W31
AT31 VDD VDD AV35 BD47 VDD VDD BE51 N39 VDD VDD W32
AT32 VDD VDD AV36 BD48 VDD VDD BE52 N40 VDD VDD W33
C AT33 VDD VDD AV37 BD49 VDD VDD BF42 P13 VDD VDD W34 C
AT34 VDD VDD AV38 BD50 VDD VDD BF44 P40 VDD VDD W35
AT35 VDD VDD AV39 BD51 VDD VDD BF45 R13 VDD VDD W36
AT36 VDD VDD AV40 BE41 VDD VDD BF47 R14 VDD VDD W37
AT37 VDD VDD AV42 BE42 VDD VDD BF49 R15 VDD VDD W38
AT38 VDD VDD AV43 BE43 VDD VDD BF51 R16 VDD VDD W39
AT39 VDD VDD AV44 BE46 VDD VDD BG43 R17 VDD VDD W40
AT40 VDD VDD AW13 BE47 VDD VDD BG44 R18 VDD VDD Y13
AT42 VDD VDD AW40 R19 VDD VDD Y40
AU13 VDD VDD AW42 R20 VDD
AU40 VDD VDD AW43 NVVDD_SENSE BK45 R21 VDD
GPU_NVVDD_SENSE 58
AU43 VDD VDD AW44 GND_SENSE BL45 R22 VDD
GPU_GND_SENSE 58
AV13 VDD VDD AW45
AV14 VDD VDD AY13
AV15 VDD VDD AY14
AV16 VDD VDD AY15
AV17 VDD VDD AY16 G1K
AV18 VDD VDD AY17 ?
AV19 AY18 BGA2228 1V8_AON
VDD VDD
COMMON
AV20 VDD VDD AY19
AV21 VDD VDD AY20 20/22 NC/1V8
AV22 VDD VDD AY21
AV23 VDD VDD AY22 1V8_AON BA10
AV24 VDD VDD AY23 1V8_AON BB14
AV25 VDD VDD AY24 1V8_AON BC14
AV26 VDD VDD AY25
AV27 VDD

BD14 NC BD24
23 FP_FUSE_GPU FP_FUSE_SRC
NC BM44
NC BM45

D D

10,12,13,14,15,17,18,20,21,22,23,24,58,61,62,78
11,12,13,14,15,16,17,18,19,61
1V8_AON
FBVDDQ
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
19,20,58,59 NVVDD Title
[25] GPU NVVDD, FBVDDQ
Size Document Number Rev
Custom SCHEMATIC1 6-71-NH500-D02 D02

Date: Wednesday, December 05, 2018 Sheet 25 of 78


1 2 3 4 5 6 7 8

B - 26 GPU NVVDD, FBVDDQ


Schematic Diagrams

GPU GND
1 2 3 4 5 6 7 8

G1F G1G G1H


?
BGA2228
COMMON
?
BGA2228
COMMON
?
BGA2228
COMMON
GPU GND
15/22 GND_1/3 16/22 GND_2/3 21/22 GND_3/3

A2 GND GND AH6 AR20 GND GND B52 BL40 GND GND N51
A26 GND GND AH8 AR21 GND GND B7 BL43 GND GND N6
A29 GND GND AJ14 AR22 GND GND BA48 BL5 GND GND N8
A3 GND GND AJ15 AR23 GND GND BA9 BL7 GND GND P14
A32 GND GND AJ16 AR24 GND GND BB49 BM2 GND GND P15
A50 GND GND AJ17 AR25 GND GND BC13 BM3 GND GND P16
A51 GND GND AJ18 AR26 GND GND BC16 C1 GND GND P17
AA49 GND GND AJ19 AR27 GND GND BC19 C29 GND GND P18
AA8 GND GND AJ2 AR28 GND GND BC2 C33 GND GND P19
A A
AB10 GND GND AJ20 AR29 GND GND BC22 C5 GND GND P20
AB14 GND GND AJ21 AR30 GND GND BC25 C51 GND GND P21
AB15 GND GND AJ22 AR31 GND GND BC28 C52 GND GND P22
AB16 GND GND AJ23 AR32 GND GND BC31 D10 GND GND P23
AB17 GND GND AJ24 AR33 GND GND BC34 D12 GND GND P24
AB18 GND GND AJ25 AR34 GND GND BC37 D13 GND GND P25
AB19 GND GND AJ26 AR35 GND GND BC4 D16 GND GND P26
AB2 GND GND AJ27 AR36 GND GND BC51 D19 GND GND P27
AB20 GND GND AJ28 AR37 GND GND BC6 D22 GND GND P28
AB21 GND GND AJ29 AR38 GND GND BC8 D24 GND GND P29
AB22 GND GND AJ30 AR39 GND GND BD26 D25 GND GND P30
AB23 GND GND AJ31 AR4 GND GND BD29 D28 GND GND P31
AB24 GND GND AJ32 AR52 GND GND BD32 D30 GND GND P32
AB25 GND GND AJ33 AR9 GND GND BD35 D31 GND GND P33
AB26 GND GND AJ34 AT4 GND GND BD38 D34 GND GND P34
AB27 AJ35 AT5 BD52 D37 P35

B.Schematic Diagrams
GND GND GND GND GND GND
AB28 GND GND AJ36 AT51 GND GND BE10 D4 GND GND P36
AB29 GND GND AJ37 AT52 GND GND BE13 D40 GND GND P37
AB30 GND GND AJ38 AT8 GND GND BE15 D43 GND GND P38
AB31 GND GND AJ39 AU10 GND GND BE16 D46 GND GND P39
AB32 GND GND AJ9 AU14 GND GND BE18 D49 GND GND P51
AB33 GND GND AK1 AU15 GND GND BE19 D7 GND GND R49
AB34 GND GND AK44 AU16 GND GND BE21 E2 GND GND R52
AB35 GND GND AK47 AU17 GND GND BE22 E4 GND GND T10
AB36 GND GND AL10 AU18 GND GND BE24 E48 GND GND T14

Sheet 26 of 73
AB37 GND GND AL14 AU19 GND GND BE25 E5 GND GND T15
AB38 GND GND AL15 AU2 GND GND BE27 E51 GND GND T16
AB39 GND GND AL16 AU20 GND GND BE28 E8 GND GND T17
AB4 GND GND AL17 AU21 GND GND BE30 F10 GND GND T18
AB43 GND GND AL18 AU22 GND GND BE31 F13 GND GND T19
AB45
AB47
AB49
AB51
GND
GND
GND
GND
GND
GND
GND
GND
AL19
AL2
AL20
AL21
AU23
AU24
AU25
AU26
GND
GND
GND
GND
GND
GND
GND
GND
BE33
BE34
BE36
BE37
F16
F17
F19
F21
GND
GND
GND
GND
GND
GND
GND
GND
T2
T20
T21
T22
GPU GND
B AB6 GND GND AL22 AU27 GND GND BE39 F22 GND GND T23 B
AB8 GND GND AL23 AU28 GND GND BE40 F25 GND GND T24
AD14 GND GND AL24 AU29 GND GND BF2 F28 GND GND T25
AD15 GND GND AL25 AU30 GND GND BF4 F31 GND GND T26
AD16 GND GND AL26 AU31 GND GND BF41 F34 GND GND T27
AD17 GND GND AL27 AU32 GND GND BF6 F35 GND GND T28
AD18 GND GND AL28 AU33 GND GND BG10 F37 GND GND T29
AD19 GND GND AL29 AU34 GND GND BG13 F40 GND GND T30
AD20 GND GND AL30 AU35 GND GND BG16 F43 GND GND T31
AD21 GND GND AL31 AU36 GND GND BG19 F44 GND GND T32
AD22 GND GND AL32 AU37 GND GND BG22 F46 GND GND T33
AD23 GND GND AL33 AU38 GND GND BG25 F52 GND GND T34
AD24 GND GND AL34 AU39 GND GND BG28 F7 GND GND T35
AD25 GND GND AL35 AU4 GND GND BG31 G2 GND GND T36
AD26 GND GND AL36 AU45 GND GND BG34 G38 GND GND T37
AD27 GND GND AL37 AU47 GND GND BG37 G4 GND GND T38
AD28 GND GND AL38 AU49 GND GND BG40 G47 GND GND T39
AD29 GND GND AL39 AU51 GND GND BG42 G49 GND GND T4
AD30 GND GND AL4 AU6 GND GND BG7 G51 GND GND T43
AD31 GND GND AL43 AU8 GND GND BH15 G6 GND GND T45
AD32 GND GND AL45 AV4 GND GND BH18 H1 GND GND T47
AD33 GND GND AL47 AV45 GND GND BH2 H10 GND GND T49
AD34 GND GND AL49 AV9 GND GND BH21 H13 GND GND T51
AD35 GND GND AL51 AW14 GND GND BH24 H16 GND GND T6
AD36 GND GND AL6 AW15 GND GND BH27 H19 GND GND T8
AD37 GND GND AL8 AW16 GND GND BH30 H22 GND GND U7
AD38 GND GND AM4 AW17 GND GND BH33 H25 GND GND U9
AD39 GND GND AM9 AW18 GND GND BH36 H28 GND GND V14
AD44 GND GND AN14 AW19 GND GND BH39 H31 GND GND V15
AE10 GND GND AN15 AW20 GND GND BH42 H34 GND GND V16
AE2 GND GND AN16 AW21 GND GND BH5 H37 GND GND V17
AE4 GND GND AN17 AW22 GND GND BJ10 H40 GND GND V18
AE43 GND GND AN18 AW23 GND GND BJ12 H43 GND GND V19
AE45 GND GND AN19 AW24 GND GND BJ13 J1 GND GND V20
AE47 GND GND AN20 AW25 GND GND BJ14 J12 GND GND V21
C AE49 AN21 AW26 BJ15 J17 V22 C
GND GND GND GND GND GND
AE51 GND GND AN22 AW27 GND GND BJ16 J20 GND GND V23
AE6 GND GND AN23 AW28 GND GND BJ17 J38 GND GND V24
AE8 GND GND AN24 AW29 GND GND BJ18 J49 GND GND V25
AF1 GND GND AN25 AW30 GND GND BJ19 J52 GND GND V26
AF19 GND GND AN26 AW31 GND GND BJ20 K13 GND GND V27
AF20 GND GND AN27 AW32 GND GND BJ21 K16 GND GND V28
AF21 GND GND AN28 AW33 GND GND BJ22 K19 GND GND V29
AF22 GND GND AN29 AW34 GND GND BJ23 K2 GND GND V30
AF23 GND GND AN30 AW35 GND GND BJ24 K22 GND GND V31
AF27 GND GND AN31 AW36 GND GND BJ25 K25 GND GND V32
AF28 GND GND AN32 AW37 GND GND BJ26 K28 GND GND V33
AF29 GND GND AN33 AW38 GND GND BJ27 K31 GND GND V34
AF35 GND GND AN34 AW39 GND GND BJ28 K34 GND GND V35
AF36 GND GND AN35 AW4 GND GND BJ29 K37 GND GND V36
AF37 GND GND AN36 AW46 GND GND BJ30 K4 GND GND V37
AF38 GND GND AN37 AW5 GND GND BJ31 K40 GND GND V38
AF39 GND GND AN38 AW52 GND GND BJ32 K45 GND GND V39
AF45 GND GND AN39 AW8 GND GND BJ33 K47 GND GND V49
AF5 GND GND AN4 AY10 GND GND BJ34 K49 GND GND V52
AG14 GND GND AN5 AY2 GND GND BJ35 K51 GND GND W10
AG15 GND GND AN8 AY4 GND GND BJ36 K6 GND GND W2
AG16 GND GND AP10 AY47 GND GND BJ37 K8 GND GND W4
AG17 GND GND AP2 AY49 GND GND BJ38 M52 GND GND W43
AG18 GND GND AP4 AY51 GND GND BJ39 M6 GND GND Y9
AG24 GND GND AP43 AY6 GND GND BJ40 N10 GND
AG25 GND GND AP45 AY8 GND GND BJ41 N2 GND
AG26 GND GND AP47 B1 GND GND BJ42 N4 GND GND
AG3 GND GND AP49 B10 GND GND BJ43 N43 GND
AG30 GND GND AP51 B13 GND GND BJ7 N45 GND
AG31 GND GND AP6 B16 GND GND BK1 N47 GND
AG32 GND GND AP8 B19 GND GND BL1 N49 GND
AG33 GND GND AR14 B2 GND GND BL10 BL37 GND
AG34 GND GND AR15 B22 GND GND BL13
D AG44 GND GND AR16 B25 GND GND BL16 D
AH10 GND GND AR17 B28 GND GND BL19
AH2 GND GND AR18 B31 GND GND BL2 GND
AH4 GND GND AR19 B34 GND GND BL22
AH43 GND GND BL34 B37 GND GND BL25
AH45 GND GND BC24 B40 GND GND BL28
AH47 GND B43 GND GND BL31
AH49 B46 B5

ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
GND GND GND
AH51 GND B48 GND GND B51

Title
GND GND GND GND [26] GPU GND
Size Document Number Rev
Custom SCHEMATIC1 6-71-NH500-D02 D02

Date: Wednesday, December 05, 2018 Sheet 26 of 78


1 2 3 4 5 6 7 8

GPU GND B - 27
Schematic Diagrams

mDP
5 4 3 2 1

3.3VS
Footprint 㓡
M-SOT23-5ᾖ䁢M-SOT23-
5A
6/14 Tim MDP_I_PWR
COMMON SHIELD6 GND4 D31 *4.7K_04 R583 PS8330B_CFG0
MDP_I_PWR SHIELD5 GND3
For Safety LPS. I_MDP_D3 6 5 I_MDP_D3J *4.7K_04 R584
3.3VS
I_MDP_D#3 7 4 I_MDP_D#3J
U35
3 1 8 3
OC# VOUT PWR 20 I_MDP_D2 9 2 I_MDP_D2J 3.3VS
20
GND 19 I_MDP_D#2 10 1 I_MDP_D#2J
5 19
VIN I_MDP_AUX#_R 18 AUX_CHN *4.7K_04 R594 PS8330B_CFG1
C862 18
C1066 4 2 17
EN# GND I_MDP_D#2J 17 LANE_2N AUX_CHP 16 I_MDP_AUX_R *TVUDF1004AD0 *4.7K_04 R593
10u_6.3V_X5R_06 10u_6.3V_X5R_06 16
I_MDP_D2J 15 LANE_2P
D SY6288D20AAC 15 D
PCB Footprint = M-SOT23-5A 3.3VS GND 14 D32
14
GND 13 3.3VS
13
I_MDP_D#3J 12 LANE_3N I_MDP_D0 6 5 I_MDP_D0J
12
30,44,49 SUSB I_MDP_D3J 10 LANE_3P LANE_1N 11 I_MDP_D#1J I_MDP_D#0 7 4 I_MDP_D#0J *4.7K_04 R581 PS8330B_PEQ
11
R441 10
8 3
I_MDP_D1J 9 LANE_1P
I_MDP_D1 9 2 I_MDP_D1J *4.7K_04 R582
9
*100K_04 7 GND GND 8 I_MDP_D#1 10 1 I_MDP_D#1J
8

7 5VS
I_MDPC_CEC 6 CONFIG2
6
I_MDP_MODE 4 CONFIG1 LANE_0N 5 I_MDP_D#0J *TVUDF1004AD0

MINI DISPLAY PORT A(PS8330B) I_MDP_D0J 4


5

G
3 LANE_0P
3
1 GND HPD 2 I_MDP_HPD_R
2
R587 1 S D R807 1K_04 I_MDP_HPD_R
J_MDP1 35 I_MDP_HPD
3.3VS
1M_04 C17737-120A9-L

AC
11/24/2017
P/N = 6-21-11Y20-020 Q74
3.3VS R806

220p_50V_NPO_04
SHIELD2 GND2 2SK3018S3 D53
PCB Footprint = c-909jd20fstc6-1 SHIELD1 GND1
C1079 C1072 BAV99 RECTIFIER

10K_04

C1194
C
A
100K_04
0.1u_6.3V_X5R_02 0.01u_16V_X7R_04
B.Schematic Diagrams

PDB PIN:
4/2/2018 L:Chip power down

R599
MDP_I_PWR
H:Normal operation(default)

C1077 2.2u_6.3V_X5R_04 3.3VS 3.3VS


C C

3.3VS 3.3VS 3.3VS

Sheet 27 of 73 R808 R812

5
U34 *100K_1%_04 100K_1%_04

G
36

35

34

33

32

31

30

29

28

27

26

25
PS8330B
I_MDP_AUX#_R

mDP C1203 0.1u_10V_X7R_04 4 3


2 IGPU_AUX_CH_N

VDD33

RST#

SDA_DDC

SCL_DDC

VDD33

GND

AUX_SRCp

AUX_SRCn

AUX_SNKp

AUX_SNKn

PD#

VDD33

D
Q76B
Modify,3/19 Tim MTDK3S6R

月P S 8 3 3 0 B 月
Mini DP Conn
37 24
NC GND

2
G
C1074 0.1u_10V_X7R_04 IN0P_R 38 23 C1069 0.1u_10V_X7R_04 I_MDP_D0
2 IGPU_LANE0P IN0p OUT0p
C1204 0.1u_10V_X7R_04 1 6 I_MDP_AUX_R
C1070 0.1u_10V_X7R_04 IN0N_R 39 22 C1067 0.1u_10V_X7R_04 I_MDP_D#0 2 IGPU_AUX_CH_P
2 IGPU_LANE0N IN0n OUT0n

D
PS8330B_CFG1 40 21 Q76A
CFG1 NC R809 R810
MTDK3S6R
C1061 0.1u_10V_X7R_04 IN1P_R 41 20 C1065 0.1u_10V_X7R_04 I_MDP_D1
2 IGPU_LANE1P IN1p OUT1p *100K_1%_04 100K_1%_04
C1057 0.1u_10V_X7R_04 IN1N_R 42 19 C1058 0.1u_10V_X7R_04 I_MDP_D#1
2 IGPU_LANE1N IN1n OUT1n 5VS

2 IGPU_LANE2P C1055 0.1u_10V_X7R_04 IN2P_R


43

44
NC PS8330B GND
18

17 C1056 0.1u_10V_X7R_04 I_MDP_D2


5VS
IN2p OOUT2p R813
IN2N_R 45 16 I_MDP_D#2

5
2 IGPU_LANE2N C1053 0.1u_10V_X7R_04 C1054 0.1u_10V_X7R_04 100K_04

G
B IN2n OUT2n B
46 15 4 3 I_MDP_AUX#_R
NC NC R811
35 I_MDP_DATA
IN3P_R 47 14 I_MDP_D3

6
C1051 0.1u_10V_X7R_04 C1052 0.1u_10V_X7R_04

D
2 IGPU_LANE3P IN3p OUT3p D 100K_04
Q75B
C1049 0.1u_10V_X7R_04 IN3N_R 48 13 C1050 0.1u_10V_X7R_04 I_MDP_D#3
2 IGPU_LANE3N IN3n OUT3n MTDK3S6R Q78A G2
S

SDA_CLTCFG0

3
MTDK3S6R D

SCL_CTLPEQ
Q78B

I2C_ADDR
49 I_MDP_MODE

CAD_SRC

HPD_SRC

CAD_SNK

HPD_SNK
EPAD MTDK3S6R G5
0715 0715

G2
S
VDD33

VDD33

VDD33
CEXT

REXT

4
6 1 I_MDP_AUX_R
35 I_MDP_CLK

S
1

10

11

12
Q75A
MTDK3S6R
2.2u_6.3V_X5R_04

PS8330B_PEQ

PS8330B_CFG0

IN_CAD_SRC
4.99K_1%_04

I_MDP_HPD_R
DESIGN NOTE:CFG0

I_MDP_MODE
30,32,44,45,47,48,49,74,77,78 5VS
3.3VS
8,9,23,24,29,30,31,32,33,34,35,36,39,40,41,43,44,45,47,49,50,54,61,74,77 3.3VS
3.3VS 3.3VS Configuration pin for automatic EQ and
Aux interception; Internal pull down at
~150Kohm,3.3V I/O
L: default, automatic EQ enable and Aux interception enable DESIGN NOTE:PEQ
H: automatic EQ disable and AUX interception enable
C1048

R585

Programmalbe input equalization levels;internal pull


M: automatic EQ disable and AUX interception down at~150k ,3.3v I/O
disable,no pre-emphasis, 600mVpp swing L: default, LEQ, compensate channel loss up to 12dB at
HBR2
A DESIGN NOTE:CFG1 A

Configuration pin for auto test and input offset H: HEQ, compensate channel loss up to 15dB at HBR2
Raven add 0809
cancellation,3.3V IO, internal pull up at~150K M:LLEQ, compensate channel loss up to 5dB at HBR2
H: default, auto test disable and input offset cancellation
enable
L: auto test enable and input offset cancellation enable ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
M: auto test disable and input offset cancellation disable Title
[27] mDP (iGPU)
Size Document Number Rev
Custom SCHEMATIC1 6-71-NH500-D02 D02

Date: Wednesday, December 05, 2018 Sheet 27 of 78


5 4 3 2 1

B - 28 mDP
Schematic Diagrams

mDP
5 4 3 2 1

AUX interception disable for Port y (y = 1, 2). Internal pull down at ~150K㫉 , 
L: AUX interception enable, driver configuration is set by link training (default)
mini-Display Port E (LEFT)
H: AUX interception disable, driver output with fixed 800mV and 0dB
M: AUX interception disable, driver output with fixed 400mV and 0dB

Output swing adjustment for Port y (y = 1, 2). Internal pull down at ~150K㫉,  
L: default
H: +20%
M: -16.7%

DESIGN NOTE:CFG0
Configuration pin for automatic EQ and
Aux interception; Internal pull down at
D ~150Kohm,3.3V I/O D
L: default, automatic EQ enable and Aux interception enable
H: automatic EQ disable and AUX interception enable
M: automatic EQ disable and AUX interception
disable,no pre-emphasis, 600mVpp swing

DESIGN NOTE:CFG1
Configuration pin for auto test and input offset
cancellation,3.3V IO, internal pull up at~150K
H: default, auto test disable and input offset cancellation
enable
L: auto test enable and input offset cancellation enable
M: auto test disable and input offset cancellation disable

B.Schematic Diagrams
DESIGN NOTE:PEQ
Programmalbe input equalization levels;internal pull
down at~150k ,3.3v I/O
L: default, LEQ, compensate channel loss up to 12dB at
HBR2
H: HEQ, compensate channel loss up to 15dB at HBR2 Raven del 0628
M:LLEQ, compensate channel loss up to 5dB at HBR2

Sheet 28 of 73
mDP
C
DEL PS8460B Repeter C

B B

Raven del 0628

A A

ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Title
[28] mDP (dGPU)
Size Document Number R ev
Custom SCHEMATIC1 6-71-NH500-D02 D02

Date: Wednesday, December 05, 2018 Sheet 28 of 78

5 4 3 2 1

mDP B - 29
Schematic Diagrams

Panel, Inverter
5 4 3 2 1

PANEL POWER
PANEL CONNECTOR VIN
SHORT
PJ25 VLED

OPEN_2A
LED PANEL (EDP Channel). 2 1

PLVDD
J_LCD1 VIN Q15
*MTP3403N3
D 2A 1 S D
D

C181 2 1
3 2 C942 C943 D02A
3 modidication 0604 biaggi
4
C99

G
4

*0.1u_50V_X5R_04

*0.1u_50V_X5R_04
1u_6.3V_X5R_02 5
6 5
7 6 3.3V R69
C918 0.1u_10V_X7R_04 8 7 *0.22u_50V_X7R_04
2 EDP_TXN_0 8
C919 0.1u_10V_X7R_04 9 R66 *4.7K_06
2 EDP_TXP_0 9
10 D02_1107_Alex R82
C920 0.1u_10V_X7R_04 11 10 GND5 *150K_04 6
2 EDP_TXN_1 11 GND5
C923 0.1u_10V_X7R_04 12 GND4 *10K_04 D Q21A
2 EDP_TXP_1 12 GND4
13 GND3 R67 *100K_04
C924 0.1u_10V_X7R_04 14 13 GND3 GND2 LVDD_EN#1 2 G *MTDK5S6R
B.Schematic Diagrams

2 EDP_TXN_2 14 GND2
C925 0.1u_10V_X7R_04 15 GND1 R68 3 S
2 EDP_TXP_2 15 GND1
16 D 1
C926 0.1u_10V_X7R_04 17 16 *100K_04 Q21B
2 EDP_TXN_3 17
C927 0.1u_10V_X7R_04 18 5 G
Raven del 0712 2 EDP_TXP_3 18

Sheet 29 of 73
19 S *MTDK5S6R
C932 0.1u_10V_X7R_04 20 19 modidication 0604 biaggi 4

D
2 EDP_AUXN 20
C933 0.1u_10V_X7R_04 21
2 EDP_AUXP 21
22
22 NB_ENAVDD

Panel, Inverter Raven del 0712 BRIGHTNESS_R


23
24 23
R84 *0_04 G

S
INV_BLON 25 24 Q20
eDPHPD 26 25 *UK3018
27 26 R83 *0_04
2A 28 27 32,34,42,47,49,50,52,55,62 SUSB# LVDD_EN
VLED 28

C944

C934
C 29 C
30 29
30
LVDFH-03008-TP00+

0.01u_50V_X7R_04

*0.1u_50V_X5R_04
PCB Footprint = lvdfh-030xx-tx00
current = 0.3A
INV_BLON
3.3V
3.3V

3.3V

U14A

14
74LVC08APW U14B

14
R198 *0402_short 1 74LVC08APW
47 BKL_EN
3BLON14
2 6BLON2
33 BLON
PANEL POWER 6-06-75140-068 R201 100K_04
5

7
U14C

14
7
74LVC08APW
9
R202 *100K_04 3.3V 8 INV_BLON
10
SB_BLON U14D

14
B 39 SB_BLON B
74LVC08APW R161

7
12 C532
44,47,65 LID_SW #
11 LID_SW #1 100K_04
3.3VS Entire trace of Panel VCC should be wider than 80-mil4,32,47,54 13 0.1u_10V_X7R_04
ALL_SYS_PW RGD
U8 G5016 C182

7
1 6 1u_6.3V_X5R_02
2 IN1 IN2 7
IN1 IN2

PLVDD 13
14 OUT1 OUT2
8
9
PLVDD 3.3V 3A PLVDD 3.3VS

C
A
OUT1 OUT2

*22u_6.3V_X5R_06
G5016_CT1 12 10 G5016_CT1 C131 C132 D14
CT1 CT2

C130
BAV99 RECTIFIER
VBIAS

*1u_6.3V_X5R_02

*22u_6.3V_X5R_06
GND

GND

AC
EN1

EN2

C180
680p_50V_X7R_04 eDPHPD R135 1K_04
EDP_HPD 35
3

15

11

R119 C266
100K_04
*220p_50V_X7R_04
NB_ENAVDD
5V NB_ENAVDD 33,47
C267
1u_6.3V_X5R_02 R53 *10K_04
PLVDD
R120
100K_04 BRIGHTNESS_R R54 *0402_short
A EDP_BRIGHTNESS 33 A

ON R52 100K_04
BRIGHTNESS
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Title
42,44,49,50,52,55,60,73
34,49,50,51,52,53,54,55,56,57,59,78
5V
VIN
[29] PANEL,INVERTER
27,30,32,44,45,47,48,49,74,77,78 5VS Size Document Number Rev
2,24,42,44,49,50,52,53,56,59,60,61,72,73
8,9,23,24,27,30,31,32,33,34,35,36,39,40,41,43,44,45,47,49,50,54,61,74,77
3.3V
3.3VS A3 SCHEMATIC1 6-71-NH500-D02 D02

Date: W ednesday, December 05, 2018 Sheet 29 of 78


5 4 3 2 1

B - 30 Panel, Inverter
Schematic Diagrams

HDMI
5 4 3 2 1

HDMI_5VS

HDMI CONNECTOR HDMI ESD W/O LEVELSHIFT 暨


ᶲ , NE T⎗SW
P
A

A
R3 D7
D40
*0_04 RB551V-30S2 TMDS_CLOCK# 6 5 TMDS_CLOCK#J
TMDS_CLOCK 7 4 TMDS_CLOCKJ

C
D8 *RB551V-30S2
A C R11 *0.5_1%_04 For ESD TMDS_DATA0#
8
9
3
2 TMDS_DATA0#J
R10 *0.5_1%_04 TMDS_DATA0 TMDS_DATA0J
10 1

C
A

A
ESDPSA2510V05
D 5VS modidication 0604 biaggi HDMI_5VS D
U2 R5 R4
5 1 J_HDMI1 D39
VIN VOUT 2K_04 2K_04 D11 D10 D9

AC

AC

AC
TMDS_DATA1# TMDS_DATA1#J

22u_6.3V_X5R_06

22u_6.3V_X5R_06
C7 6 5
2 C8 BAV99 RECTIFIER BAV99 RECTIFIER BAV99 RECTIFIER TMDS_DATA1 TMDS_DATA1J
GND 7 4
R2 *0_04 8 3
4 3 HDMI_SCL-C TMDS_DATA2# TMDS_DATA2#J
27,44,49 SUSB EN# OC# HDMI_HPD-C 9 2
19 TMDS_DATA2 TMDS_DATA2J
HOT PLUG DETECT 10 1
*uP7549UMA5-20 18 HDMI_SDA-C
+5V 17
D02_1112_Alex 6-02-75495-9C0 HDMI_SDA-C DDC/CEC GND HDMI_HPD-C
only uP7549UMA-20 16
SDA HDMI_SCL-C ESDPSA2510V05
15
14 SCL
RESERVED 13 HDMI_CEC
U47 TMDS_CLOCK#J 12 CEC
TMDS CLOCK- 11
2
VOUT TMDS_CLOCKJ 10 CLK SHIELD
TMDS CLOCK+ 9 TMDS_DATA0#J
3
VIN 8 TMDS DATA0-
1
GND SHIELD0 7 TMDS_DATA0J
TMDS_DATA1#J 6 TMDS DATA0+

B.Schematic Diagrams
TMDS DATA1- 5
NV3V3 3.3VS APL3517A
TMDS_DATA1J 4 SHIELD1
TMDS DATA1+ 3 TMDS_DATA2#J
TMDS DATA2- 旣
暣ῤ m婧 㔜
by platfo
r
R55 *0_06 2 11/9/2017
SHIELD2 1 TMDS_DATA2J

R56 0_06
TMDS DATA2+ TMDS_CLOCK#_R

TMDS_CLOCK_R
R474 499_1%_04
TMDS_CLOCK#_R

TMDS_CLOCK_R
R473
6.04_1%_04
R471
TMDS_CLOCK#

TMDS_CLOCK
Sheet 30 of 73

GND
GND
GND
GND
R470 499_1%_04 R472 6.04_1%_04

R78 R79
116E-1C001-20Y R464 499_1%_04
*180_1%_04
HDMI

GND1
GND2
GND3
GND4
C TMDS_DATA1#_R TMDS_DATA1#_R R463 TMDS_DATA1# C
47K_04 47K_04 P/N = 6-21-13K20-019 6.04_1%_04
PIN GND1~4=GND TMDS_DATA1_R
R460 499_1%_04
22,30 HDMI_CTRLDATA TMDS_DATA1_R R461 TMDS_DATA1
22,30 HDMI_CTRLCLK
SCL/SDA 暨PULL HIGH (CHECK 䪗)
PCH Rd R462
*180_1%_04
6.04_1%_04

GND_HDMI
䓐COMMO
ᶵ 䚜㍍SHORT,mod
Output from PS8409.
N CHOK E ify net a
nme

D
Connect to 1.2V power IC for 1.2V power cut down if desired 5VS
EMI 3/7/2016
G
0701 䁢COMMO N CHOK E SHOR
㓡 暞 ẞ
T
TMDS_DATA2#_R
枸䔁暣 旣 嶐 -+ ℑ䪗

S
C886 0.1u_10V_X7R_04 Q2
22 HDMI_DATA2N TMDS_DATA2_R D02_102518_Alex_HDMI bug
C887 0.1u_10V_X7R_04 UK3018 2.5V drive
22 HDMI_DATA2P
C884 0.1u_10V_X7R_04 TMDS_DATA1_R
22 HDMI_DATA1P TMDS_DATA1#_R
22 HDMI_DATA1N C885 0.1u_10V_X7R_04

C882 0.1u_10V_X7R_04 TMDS_DATA0#_R


22 HDMI_DATA0N TMDS_DATA0_R D02_102518_Alex_HDMI bug
22 HDMI_DATA0P C883 0.1u_10V_X7R_04

C888 0.1u_10V_X7R_04 TMDS_CLOCK_R


22 HDMI_CLOCKP TMDS_CLOCK#_R
C889 0.1u_10V_X7R_04 3.3VS
22 HDMI_CLOCKN

暣ῤ m婧 㔜
by platfo
r
3.3VS EMI 11/9/2017
䁢COMMO N CHOK E SHOR
㓡 暞
T ẞ

2
枸䔁暣 旣 嶐 -+ ℑ䪗
G 䓐COMMO
ᶵ 䚜㍍SHORT,mod
HDMI_SDA-C
22,30 HDMI_CTRLDATA
1
S
6 N CHOK E ify net a
nme
D
B R22 B
5

3/7/2016
Q16A
G

1M_04
G

4 3 MTDK5S6R HDMI_SCL-C R465 499_1%_04


22,30 HDMI_CTRLCLK TMDS_DATA0#_R TMDS_DATA0#_R R466 TMDS_DATA0#
S

S D HDMI_HPD-C MTDK5S6R 6.04_1%_04


23,35 HDMI_HPD TMDS_DATA0_R TMDS_DATA0_R R468 TMDS_DATA0
Q16B
Q1 R467 R469 499_1%_04 6.04_1%_04
UK3018 2.5V drive *180_1%_04
R18 R455 499_1%_04
TMDS_DATA2#_R TMDS_DATA2#_R R456 TMDS_DATA2#
0701 20K_04 6.04_1%_04
TMDS_DATA2_R TMDS_DATA2_R R458 TMDS_DATA2

⛘旣ῤ B Y P L A T FRO M ᾖ㬋 R459 499_1%_04 6.04_1%_04

9/23/2014
R457
*180_1%_04
Rd Raven add 0809
GND_HDMI

A A

10,23,58,61,62,78 NV3V3
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Title
2,24,29,42,44,49,50,52,53,56,59,60,61,72,73
29,42,44,49,50,52,55,60,73
3.3V
5V [30] HDMI 2.0
8,9,23,24,27,29,31,32,33,34,35,36,39,40,41,43,44,45,47,49,50,54,61,74,77 3.3VS
27,32,44,45,47,48,49,74,77,78 5VS Size Document Number Rev
Custom SCHEMATIC1 6-71-NH500-D02 D02

Date: Wednesday, December 05, 2018 Sheet 30 of 78


5 4 3 2 1

HDMI B - 31
Schematic Diagrams

PCH 1/9
5 4 3 2 1
BOOT HALT JTAG ODT
ENABLED IF LOW DISABLE:LOW
PCH HAS (INTERNAL WEAK PU)
INTERNAL WEAK
PU
SPI_3.3V SPI_3.3V

D02_102518_Alex_MOW ?
R848 R849
?
100K_04 100K_04
U40A
SPI_SI_R SPI_SO_R ?
R627 *0_04 LAN_W UP# BE36 AV29 PLT_RST# 24,32,45
34,43,47 LAN_W AKEUP# GPP_A11/PME#/SD_VDD2_PWR_EN# GPP_B13/PLTRST#
D GPP_K_14_GSXDIN: D
R15 DMI AC COUPLING FULL VOLTAGE MODE
RSVD2 Y47 T67
R734 R751 R13 GPP_K16/GSXCLK WHEN SAMPLED LOW
RSVD1 Y46 T70
*4.7K_04 *4.7K_04 GPP_K12/GSXDOUT Y48
GPP_K13/GSXSLOAD W46 GPP_K14_TEST_R
GPP_K14/GSXDIN GPP_K14_TEST_R 73
AA45
AL37 GPP_K15/GSXSRESET# 3.3VS
AN35 VSS_AL37
T80 TP
AL47 EXTTS_SNI_DRV0 R666 10K_04
CONSENT STRAP IS PESONALITY STRAP SPI_SI_R R712 5.1_1%_04 AU41 GPP_E3/CPU_GP0
45 SPI_SI_R SPI_SO_R SPI0_MOSI AM45 TP_ATTN# 44
ENABLED IF LOW IS ENABLED IF LOW 45 SPI_SO_R R709 5.1_1%_04 BA45 GPP_E7/CPU_GP1
SPI_CS_0# SPI0_MISO BF32
PCH HAS NO PCH HAS NO AY47 GPP_B3/CPU_GP2 EXTTS_SNI_DRV1
SPI_SCLK_R SPI0_CS0# BC33 R398 *10K_04
INTERNAL INTERNAL 45 SPI_SCLK_R R724 5.1_1%_04 AW47 GPP_B4/CPU_GP3
AW48 SPI0_CLK
TERMINATION TERMINATION SPI0_CS1# AE44 SML4ALERT# T74
SPI_W P# R747 33_04 SPI_IO2 AY48 GPP_H18/SML4ALERT# AJ46 SML4DATA
SPI0_IO2 GPP_H17/SML4DATA T75
B.Schematic Diagrams

SPI_3.3V SPI_3.3V SPI_HOLD# R722 33_04 SPI_IO3 BA46 AE43 SML4CLK


SPI0_IO3 GPP_H16/SML4CLK T73
AT40 AC47 SML3ALERT#
45 SPI0_CS2# SPI0_CS2# GPP_H15/SML3ALERT# AD48 SML3DATA T133
BE19 GPP_H14/SML3DATA
GPP_D1/SPI1_CLK/SBK1/BK1 AF47 SML3CLK
R749 R723 BF19 GPP_H13/SML3CLK GPP_H_12
GPP_D0/SPI1_CS#/SBK0/BK0 AB47

Sheet 31 of 73
BF18 GPP_H12/SML2ALERT#
100K_04 100K_04 GPP_D3/SPI1_MOSI/SBK3/BK3 AD47 SML2DATA T72
BE18 GPP_H11/SML2DATA
GPP_D2/SPI1_MISO/SBK2/BK2 AE48 SML2CLK T132
BC17 GPP_H10/SML2CLK
SPI_IO2 SPI_IO3 BD17 GPP_D22/SPI1_IO3 BB44 INTRUDER# R403 330K_04
GPP_D21/SPI1_IO2 INTRUDER# VCC_RTC

PCH 1/9 R748 R625


?
HM370_MP 1 OF 13

*4.7K_04 *1K_04
C C

ESPI FLASH SHARING MODE


MASTER ATTACHED FLASH SHARING:LOW
SLAVE ATTACEHD FLASH SHARING:HIGH
(INTERNAL WEAK PD)

3.3VA 3.3VA

SML3CLK R675 100K_04


SML3ALERT# R681 20K_04
R684
SML3ALERT# R683 *20K_04
*4.7K_04

GPP_H_12
GPP_H15
JTAG ODT IS DISABLED IF LOW
PCH HAS INTERNAL WEAK PU

B B

For ITE IT8587B CO-LAY


W /O TPM 天
ᶲẞ
ALSPI_MSI R850 0_04 SPI_SI_R
47 ALSPI_MSI ALSPI_MSO R851 0_04 SPI_SO_R W/O TPM
47 ALSPI_MSO ALSPI_SCLK R852 0_04 SPI_SCLK_R W/O TPM
47 ALSPI_SCLK ALSPI_CE# R853 0_04 SPI_CS_0# W/O TPM
47 ALSPI_CE# W/O TPM

SPI_3.3V
SHORT SPI_* = 1"~6.5"
2 1
VDD3
PJ40 OPEN_1mm ME+BIOS ROM 16MB
RTC Wake UP
U43
8 5 SPI_SI_M R730 33_04 SPI_SI_R
VDD SI
A A
C1143 2 SPI_SO_M R750 33_04 SPI_SO_R
SO
0.1u_6.3V_X5R_02 R746 20K_04 SPI_W P# 3 1 SPI_CS_0#
WP# CE#

ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
6 SPI_SCLK_M R732 33_04 SPI_SCLK_R
SCK 3.3VA 4,32,33,34,37,39,45,50,55
SPI_HOLD# SPI_3.3V 37
R736 20K_04 7 4
HOLD# VSS VCC_RTC 34,37 Title
R731
GD25B127DSIGR 100K_04
3.3VS
VDD3
8,9,23,24,27,29,30,32,33,34,35,36,39,40,41,43,44,45,47,49,50,54,61,74,77
4,23,24,32,34,37,40,41,43,45,47,48,49,50,51,54,55,57,58,59,60,61,62,65,74,77,78
[31] PCH 1/12-SPI/SMBUS
Size Document Number Rev
A3 SCHEMATIC1 6-71-NH500-D02 D02

Date: W ednesday, December 05, 2018 Sheet 31 of 78


5 4 3 2 1

B - 32 PCH 1/9
Schematic Diagrams

PCH 2/9
5 4 3 2 1

?
?
U40B
?
K34 J3
2
2
DMI_MT_IR_0_DN
DMI_MT_IR_0_DP
J35 DMI0_RXN USB2N_1 J2
USB_PN1
USB_PP1
42
42
1- USB3 Port 1 Charger
C33 DMI0_RXP USB2P_1 N13 USB_PN2 44
2
2
DMI_IT_MR_0_DN
DMI_IT_MR_0_DP
B33 DMI0_TXN
DMI0_TXP
USB2N_2
USB2P_2
N15 USB_PP2 44 2- Audio USB3.0 Con.
G33 K4 USB_PN3 42
2
2
DMI_MT_IR_1_DN
DMI_MT_IR_1_DP
F34 DMI1_RXN
DMI1_RXP
USB2N_3
USB2P_3
K3 USB_PP3 42 3. Type-C CON. D03 Raven modfiy 0417
C32 M10
2 DMI_IT_MR_1_DN DMI1_TXN USB2N_4
B32 L9
2 DMI_IT_MR_1_DP DMI1_TXP USB2P_4 Raven modfiy 0628
K32 M1
2 DMI_MT_IR_2_DN DMI2_RXN USB2N_5
D J32 L2 D
2 DMI_MT_IR_2_DP DMI2_RXP USB2P_5
C31 K7
2 DMI_IT_MR_2_DN
B31 DMI2_TXN USB2N_6 K6
USB_PN6
USB_PP6
44
44
6- Audio USB2.0 Con.
2 DMI_IT_MR_2_DP DMI2_TXP USB2P_6
G30 L4
2 DMI_MT_IR_3_DN DMI3_RXN USB2N_7
F30 L3 Raven DEL 3G 0629
2 DMI_MT_IR_3_DP DMI3_RXP USB2P_7
C29 G4 USB_PN8 45
2 DMI_IT_MR_3_DN DMI3_TXN USB2N_8
B29 G5
2 DMI_IT_MR_3_DP
A25 DMI3_TXP USB2P_8 M6
USB_PP8 45 8- CCD
RSVD_A25 USB2N_9 USB_P9# 74
B25 N8 Raven modfiy 0628
P24 RSVD_B25 USB2P_9 H3
USB_P9 74 9- Perkey
RSVD_P24 USB2N_10 USB_PN10 44
R24 H2
C26 RSVD_R24 USB2P_10 R10
USB_PP10 44 10- Finger printer
B26 RSVD_C26 USB2N_11 P9 Raven add 0628
F26 RSVD_B26 USB2P_11 G1
G26 RSVD_F26 USB2N_12 G2
B27 RSVD_G26 USB2P_12 N3
C27 RSVD_B27 USB2N_13 N2

B.Schematic Diagrams
L26 RSVD_C27 USB2P_13 E5 3.3VA
RSVD_L26 USB2N_14 USB_PN14 41
M26 F6
D29 RSVD_M26 USB2P_14 USB_PP14 41 14- BT
E28 RSVD_D29 AH36 USB_OC0# USB_OC2# 1 8
DEL ASM x142 USB3.1 K29
M29
RSVD_E28
RSVD_K29
RSVD_M29
GPP_E9/USB2_OC0#
GPP_E10/USB2_OC1#
GPP_E11/USB2_OC2#
AL40
AJ44
AL41
USB_OC1#
USB_OC2#
VISACH2_D3
VISACH2_D3
USB_OC1#
USB_OC0#
RN4 2
3
4
7 *10K_8P4R_04
6
5
Sheet 32 of 73
GPP_E12/USB2_OC3# USB_OC4# USB_OC4#

7-3G NGFF M.2 B Key


G17
F16
A17
B17
PCIE1_RXN/USB31_7_RXN GPP_F15/USB2_OC4#
PCIE1_RXP/USB31_7_RXP GPP_F16/USB2_OC5#
PCIE1_TXN/USB31_7_TXN GPP_F17/USB2_OC6#
AV47
AR35
AR37
AV43
USB_OC5#
USB_OC6#
USB_OC7#
USB_OC7#
USB_OC6#
USB_OC5# RN5
4
3
2
1
5
6
7
8
PCH 2/9
R21 PCIE1_TXP/USB31_7_TXP GPP_F18/USB2_OC7#
C P21 PCIE2_RXN/USB31_8_RXN F4 USB2_COMP R698 113_1%_04 *10K_8P4R_04 C
Raven DEL 3G 0629 B18 PCIE2_RXP/USB31_8_RXP USB2_COMP F3 USB2_VBUSSENSE R699 *1K_04
C18 PCIE2_TXN/USB31_8_TXN USB2_VBUSSENSE U13 TP_PCH_U13 DESIGN NOTE:
USB2 COMP RES: PLACE WITHIN 1 INCH
K18 PCIE2_TXP/USB31_8_TXP RSVD1 G3 USB2_ID R696 *1K_04 VDD3
J18 PCIE3_RXN/USB31_9_RXN USB2_ID
B19 PCIE3_RXP/USB31_9_RXP BE41 GPD_7
C19 PCIE3_TXN/USB31_9_TXN GPD7 GPD_7 R626 10K_04
N18 PCIE3_TXP/USB31_9_TXP G45 PCIE24_TXP C1211 0.22u_10V_X5R_04
PCIE4_RXN/USB31_10_RXN PCIE24_TXP PCIE24_TXN C1212 PCIE_TXP24_SSD 40
R18 G46 0.22u_10V_X5R_04 D02_1109_Alex
PCIE4_RXP/USB31_10_RXP PCIE24_TXN PCIE_TXN24_SSD 40
D20 Y41
PCIE4_TXN/USB31_10_TXN PCIE24_RXP PCIE_RXP24_SSD 40
C20 Y40
PCIE4_TXP/USB31_10_TXP PCIE24_RXN PCIE23_TXP C1209 PCIE_RXN24_SSD 40
F20 G48 0.22u_10V_X5R_04 XTAL INPUT
PCIE5_RXN PCIE23_TXP PCIE23_TXN C1210 PCIE_TXP23_SSD 40
G20 G49 0.22u_10V_X5R_04 HIGH -> DIFFERENTIAL
PCIE5_RXP PCIE23_TXN PCIE_TXN23_SSD 40
B21 W44 LOW -> SINGLE ENDED
PCIE5_TXN PCIE23_RXP PCIE_RXP23_SSD 40
A22 W43
PCIE5_TXP PCIE23_RXN PCIE22_TXP C1214 PCIE_RXN23_SSD 40
K21 H48 0.22u_10V_X5R_04
PCIE6_RXN PCIE22_TXP PCIE22_TXN C1213 PCIE_TXP22_SSD 40
J21 H47 0.22u_10V_X5R_04 USB TABLE
PCIE6_RXP PCIE22_TXN PCIE_TXN22_SSD 40
D21 U41
PCIE6_TXN PCIE22_RXP PCIE_RXP22_SSD 40
C21 U40
WLAN B23
C23
PCIE6_TXP
PCIE7_TXP
PCIE22_RXN
PCIE21_TXP
F46
G47
PCIE21_TXP C1215
PCIE21_TXN C1216
0.22u_10V_X5R_04
0.22u_10V_X5R_04
PCIE_RXN22_SSD
PCIE_TXP21_SSD
40USB2.0
40
USB3.0 DEVICE

J24 PCIE7_TXN PCIE21_TXN R44


PCIE_TXN21_SSD 40 1 1 Charger, PORT 1
PCIE7_RXP PCIE21_RXP PCIE_RXP21_SSD 40
L24 T43
F24 PCIE7_RXN PCIE21_RXN PCIE_RXN21_SSD 40 3 3,4
raven add 0629
Type-C
G24 PCIE8_RXN
BUF_PLT_RST# Audio USB3.0 Con.
VDD3 B24
C24
PCIE8_RXP
PCIE8_TXN
M2. PCIE (21~24) J_SSD2
D02_102518_Alex_M.2
5 5
PCIE8_TXP 6 Audio USB2.0 Con.
U20B HM370_MP
14

B 74LVC08APW
2 OF 13 VDD3 7 7 3G/LTE B
4 ? VDD3 CCD
24,31,45 PLT_RST#
6
8
BUF_PLT_RST# 40,41,43,47 EC DELAY 99ms(UP)
5 U20D BT

14
U20C 74LVC08APW
14

14
R308 74LVC08APW 12
7

47 PM_PW ROK SYS_PW ROK_R


9 11 R288 1K_04
54 VCORE_PG SYS_PW ROK 34
100K_04 8 13
ALL_SYS_PW RGD 10

7
R287
7

R289
*10K_04
*10K_04

PM_PCH_PW ROK 32,34


SMB_DATA 34,52
DESIGN
SM BUS
NOTE: 5VS VDD3
㚫㚱⸚㒦䘬 ⓷ 柴婳 ㉱ GND⊭ 央 Q66A
6

⣏VI A㗪
␐怕婳 怈暊 2 0 mil D
3.3VA MTDK3S6R
U20A

14
1/10 R705 2G 74LVC08APW
S 1 TO VR_ON & EC
1

50 VCCIO_PW RGD ALL_SYS_PW RGD


1K_04 3
ALL_SYS_PW RGD 4,29,47,54
R708 R742 1K_04 3.3VS 2
29,34,42,47,49,50,52,55,62 SUSB#
C1134 *1u_6.3V_X5R_02
1K_04

7
3

D 1 2 R309 C716
SMB_DATA_MAIN_DDR4 8,9 34 PCH_DPW ROK
A PJ13 *1mm A
SMB_CLK 34,52
Q65A 5G 10K_04 *0.1u_10V_X7R_04
MTDK3S6R S
4
6

D Q66B
3

MTDK3S6R D

ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
2G
32,34 PM_PCH_PW ROK S 5G ON
1

S
4

Q65B Title
MTDK3S6R R706 1K_04 3.3VS 8,9,23,24,27,29,30,31,33,34,35,36,39,40,41,43,44,45,47,49,50,54,61,74,77 3.3VS
[32] PCH 2/12-DMI/PCIE/USB2.0
C1133 *1u_6.3V_X5R_02
27,30,44,45,47,48,49,74,77,78 5VS Size Document Number Rev
SMB_CLK_MAIN_DDR4 8,9
4,31,33,34,37,39,45,50,55
4,23,24,31,34,37,40,41,43,45,47,48,49,50,51,54,55,57,58,59,60,61,62,65,74,77,78
3.3VA
VDD3 A3 SCHEMATIC1 6-71-NH500-D02 D02

Date: W ednesday, December 05, 2018 Sheet 32 of 78


5 4 3 2 1

PCH 2/9 B - 33
Schematic Diagrams

PCH 3/9
5 4 3 2 1

BIOS RECOVERY
ENABLE :LOW PCH_RSVD MFG_MODE
3.3VS 3.3VS 3.3VS SATAGP0 1 8 3.3VS
SATAGP3 RN3 2 7 10K_8P4R_04
SATAGP2 3 6
4 5
R367 R656 R653
SCI#_R R689 10K_04 D02_1107_Alex
100K_04 10K_04 *10K_04
SATA_LED# R671 10K_04
BIOS_REC PCH_RSVD MFG_MODE ? SW I#_R R693 10K_04
? 3.3VA
U40C
AR2 ?
D 41 CLINK_CLK G36 D
AT5 CL_CLK PCIE_RXN9_SSD 41
41 CLINK_DATA PCIE9_RXN F36
3.3VS AU4 CL_DATA
GFX SELECT TABLE 41 CLINK_RESET CL_RST#
PCIE9_RXP C34 PCIE9_TXN C1124 0.22u_10V_X5R_04
PCIE_RXP9_SSD 41
NORMAL GFX:LOW PCIE9_TXN PCIE9_TXP PCIE_TXN9_SSD 41
D34 C1123 0.22u_10V_X5R_04
CUSTOMER GFX:HIGH P48 PCIE9_TXP PCIE_TXP9_SSD 41

R651
40
40
SATA_M2_PW R_EN1
SATA_M2_PW R_EN2 PCH_GPPK10_PCH_NVVDD_EN V47
V48
GPP_K8
GPP_K9 K37
M2. PCIE/SATA
*10K_04
PCH_GPPK11_PCH_NVVDDS_EN W47 GPP_K10
GPP_K11
PCIE10_RXN
PCIE10_RXP
J37
C35 PCIE10_TXN C1113 0.22u_10V_X5R_04
PCIE_RXN10_SSD
PCIE_RXP10_SSD
41
41 (9~12)
PCIE10_TXN PCIE10_TXP PCIE_TXN10_SSD 41
PCH_GPPK0_PCH_PEXVDD_EN B35 C1112 0.22u_10V_X5R_04
GP39_GFX_CRB_DETECT raven add 0918 L47 PCIE10_TXP PCIE_TXP10_SSD 41
PCH_GPPK1_PCH_FBVDDQ_EN L46 GPP_K0
PCH_GPPK2_PCH_1V8RUN_EN GPP_K1 F44
U48 PCIE15_RXN/SATA2_RXN PCIE_RXN15_GLAN 43
SCI#_R GPP_K2 E45
47 SCI# R687 *10mil_short U47 PCIE15_RXP/SATA2_RXP PCIE15_TXN PCIE_RXP15_GLAN 43
R649 GPP_K3 B40 C1114 0.1u_10V_X7R_04
嶇 BIOS 䡢 娵
N48
N47 GPP_K4
PCIE15_TXN/SATA2_TXN C40 PCIE15_TXP C1115 0.1u_10V_X7R_04
PCIE_TXN15_GLAN 43
RTL8411 GLAN
B.Schematic Diagrams

10K_04 PCIE15_TXP/SATA2_TXP PCIE_TXP15_GLAN 43


R694 *10mil_short SW I#_R P47 GPP_K5
47 SW I# GPP_K6 L41
R46 PCIE16_RXN/SATA3_RXN
GPP_K7 M40
PCIE16_RXP/SATA3_RXP B41
C1125 0.22u_10V_X5R_04 PCIE11_TXP C36 PCIE16_TXN/SATA3_TXN
41 PCIE_TXP11_SSD PCIE11_TXP/SATA0A_TXP C41

Sheet 33 of 73 M2. PCIE/SATA 414141 PCIE_TXN11_SSD


PCIE_RXP11_SSD
PCIE_RXN11_SSD
C1126 0.22u_10V_X5R_04 PCIE11_TXN B36
F39
G38
PCIE11_TXN/SATA0A_TXN
PCIE11_RXP/SATA0A_RXP
PCIE11_RXN/SATA0A_RXN
PCIE16_TXP/SATA3_TXP

PCIE17_RXN/SATA4_RXN
K43
K44
D02_102518_Alex_2.5" SATA issue
SATA_RXN4 44
raven add 0918

(9~12) PCIE17_RXP/SATA4_RXP A42


SATA_RXP4 44

PCH 3/9 BIOS_REC


PCH_RSVD
GP39_GFX_CRB_DETECT
MFG_MODE
AR42
AR48
AU47
GPP_F10/SATA_SCLOCK
GPP_F11/SATA_SLOAD
GPP_F13/SATA_SDATAOUT0
PCIE17_TXN/SATA4_TXN
PCIE17_TXP/SATA4_TXP
B42

P41
SATA_TXN4
SATA_TXP4
44
44 Main HDD
AU46 PCIE18_RXN/SATA5_RXN
GPP_F12/SATA_SDATAOUT1 R40

C
41 PCIE_TXN14_W LAN
C1128
C1127
0.1u_10V_X7R_04
0.1u_10V_X7R_04
PCIE14_TXN
PCIE14_TXP
C39
D39 PCIE14_TXN/SATA1B_TXN
PCIE18_RXP/SATA5_RXP
PCIE18_TXN/SATA5_TXN
C42
D42
SSD2 PCIE lan port change raven add 0629 C
WLAN 41
41
PCIE_TXP14_W LAN
PCIE_RXN14_W LAN
D46
C47
PCIE14_TXP/SATA1B_TXP
PCIE14_RXN/SATA1B_RXN
PCIE18_TXP/SATA5_TXP
AK48 SATA_LED#
41 PCIE_RXP14_W LAN PCIE14_RXP/SATA1B_RXP GPP_E8/SATALED# SATA_LED# 45 SATAGP0 & SATAGP1
AH41 SATAGP0 T79 L: SATA
B38 GPP_E0/SATAXPCIE0/SATAGP0
PCIE13_TXN/SATA0B_TXN AJ43 SATAGP1 SATAGP1 41 H: PCIe
C38 GPP_E1/SATAXPCIE1/SATAGP1
PCIE13_TXP/SATA0B_TXP AK47 SATAGP2
C45 GPP_E2/SATAXPCIE2/SATAGP2
PCIE13_RXN/SATA0B_RXN AN47 SATAGP3
C46 GPP_F0/SATAXPCIE3/SATAGP3
PCIE13_RXP/SATA0B_RXP AM46 1.05V_VCCST
GPP_F1/SATAXPCIE4/SATAGP4 AM43 ODD_DA#_R
C1110 0.22u_10V_X5R_04 PCIE12_TXP E37 GPP_F2/SATAXPCIE5/SATAGP5 T81
41 PCIE_TXP12_SSD AM47
C1111 0.22u_10V_X5R_04 PCIE12_TXN D38 PCIE12_TXP/SATA1A_TXP GPP_F3/SATAXPCIE6/SATAGP6 T131
M2. PCIE/SATA4141 PCIE_TXN12_SSD
PCIE_RXP12_SSD
J41 PCIE12_TXN/SATA1A_TXN GPP_F4/SATAXPCIE7/SATAGP7
H42 PCIE12_RXP/SATA_1A_RXP
AM48
raven add 0629
(9~12) 41 PCIE_RXN12_SSD
B44
PCIE12_RXN/SATA1A_RXN
GPP_F21/EDP_BKLTCTL
AU48
AV46
EDP_BRIGHTNESS
BLON 29
29 R679
1K_04
A44 PCIE20_TXP/SATA7_TXP GPP_F20/EDP_BKLTEN AV44 NB_ENAVDD 29,47
R37 PCIE20_TXN/SATA7_TXN GPP_F19/EDP_VDDEN
R35 PCIE20_RXP/SATA7_RXP AD3 PCH_THERMTRIP#_R R680 30.1_1%_04 PCH_THERMTRIP#
PCH_THERMTRIP# 4
D43 PCIE20_RXN/SATA7_RXN THRMTRIP# AF2 PCH_PECI
SSD2 PCIE lan port change C44 PCIE19_TXP/SATA6_TXP PECI AF3 H_PM_SYNC_R R676 30.1_1%_04 H_PM_SYNC 4
PCH_PECI 4
N42 PCIE19_TXN/SATA6_TXN PM_SYNC AG5 PLTRST_CPU_N 4
M44 PCIE19_RXP/SATA6_RXP PLTRST_CPU# AE2 H_PM_DOW N 4 R677
PCIE19_RXN/SATA6_RXN PM_DOWN
HM370_MP *10K_04
3 OF 13

B B

A A

ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Title
[33] PCH 3/12-PCIE/SATA/HOST
4,31,32,34,37,39,45,50,55 3.3VA
8,9,23,24,27,29,30,31,32,34,35,36,39,40,41,43,44,45,47,49,50,54,61,74,77 3.3VS Size Document Number Rev
4,6,50,54 1.05V_VCCST A3 SCHEMATIC1 6-71-NH500-D02 D02

Date: W ednesday, December 05, 2018 Sheet 33 of 78


5 4 3 2 1

B - 34 PCH 3/9
Schematic Diagrams

PCH 4/9

5 4 3 2 1

VDD3 R448 300_1%_04 R446 45.3K_1%_04 SUS_PW R_ACK#_R


? SUSW ARN#
D02_102518_Alex_HDA ?
U40D ?
R841 33_04 BD11 BF36 ISH_GP_6_R
RTC3.2V 77 HDA_BITCLK HDA_BCLK/I2S0_SCLK GPP_A12/BM_BUSY#/ISH_GP6/SX_EXIT_HOLDOFF# PM_CLKRUN#
R842 33_04 BE11 AV32
77 HDA_SDIN0 HDA_SDI0/I2S0_RXD GPP_A8/CLKRUN#
R843 33_04 BF12
6-06-00054-06F 34,77 HDA_SDOUT HDA_SDO/I2S0_TXD LAN_DISABLE_N D02_1115_Alex
R844 33_04 BG13 BF41
77 HDA_SYNC HDA_SYNC/I2S0_SFRM GPD11/LANPHYPC
ijıŮŪŭŴ D34 VCC_RTC
R845 33_04 BE10 BD42 PCH_SLP_W LAN#
77 HDA_RST# HDA_RST#/I2S1_SCLK GPD9/SLP_WLAN#
BF10
1 A ijıŮŪŭŴ BE12 HDA_SDI1/I2S1_RXD BB46 DDR4_DRAMRST#
C 3 I2S1_TXD/SNDW2_DATA DRAM_RESET#
BD12 BE32 VRALERTB#
2 A I2S1_SFRM/SNDW2_CLK GPP_B2/VRALERT# GPP_B1
D CLOSE TO PCH BF33 D
R444 GPP_B1/GSPI1_CS1#/TIME_SYNC1 TPM_PIRQ#
BE29 TPM_PIRQ# 45
BAT54CS3 C863 R445 20K_1%_04 AUD_AZACPU_SDO GPP_B0/GSPI0_CS1# DDR GPIO OUTPUT VOLTAGE SELECT
R665 30.1_1%_04 AM2 R47
20K_1%_04 2 AUD_AZACPU_SDO_R HDACPU_SDO GPP_K17/ADR_COMPLETE
AN3 AP29
10u_6.3V_X5R_06 2 AUD_AZACPU_SDI AUD_AZACPU_SCLK_R AM3 HDACPU_SDI GPP_B11/I2S_MCLK D02_1109_Alex
R662 30.1_1%_04 AU3 SYS_PW ROK 32
2 AUD_AZACPU_SCLK HDACPU_SCLK SYS_PWROK
BB47 PCIE_W AKE#
AV18 WAKE# PCIE_W AKE# 43
IJıŮŪŭŴ GPP_D8/I2S2_SCLK BE40 SLP_A#
RTC_VBAT_1

C842 AW18 GPD6/SLP_A# PM_SLP_LAN#


GPP_D7/I2S2_RXD BF40
1

BA17 SLP_LAN#
41 XTAL_CLKREQ GPP_D6/I2S2_TXD/MODEM_CLKREQ BC28
1u_6.3V_X5R_02 JOPEN1 BE16 GPP_B12/SLP_S0# SLP_S0# 50,54
41 CNVI_RF_RST# GPP_D5/I2S2_SFRM/CNV_RF_RESET# BF42
*OPEN_10mil-1MM BF15 GPD4/SLP_S3# SUSB# 29,32,42,47,49,50,52,55,62
GPP_D20/DMIC_DATA0/SNDW4_DATA BE42 SUSC# 47,50,52
BD16 GPD5/SLP_S4# BC42
2

D02_1109_Alex GPP_D19/DMIC_CLK0/SNDW4_CLK R419 100K_04


AV16

B.Schematic Diagrams
GPD10/SLP_S5#
*100K_04 R385 AW15 GPP_D18/DMIC_DATA1/SNDW3_DATA
GPP_D17/DMIC_CLK1/SNDW3_CLK BE45 SUS_CLK_R R424 33_04
GPD8/SUSCLK SUS_CLK 41
R447
GPD0/BATLOW#
BF44
BE35
PM_BATLOW #
SUS_PW R_ACK#_R R414 DSX*0_04
1K_04
C841
RTC_RST#
SRTC_RST#
BE47
BD46 RTCRST#
SRTCRST#
GPP_A15/SUSACK#
GPP_A13/SUSWARN#/SUSPWRDNACK
BC37 SUSW ARN# R418

R415
*0_04

*1K_04
SUS_PW R_ACK#
SUS_W ARN# 47
47
Sheet 34 of 73
1u_6.3V_X5R_02 AY42 BG44 LAN_W AKEUP#
RTC_VBAT

32 PM_PCH_PW ROK

PCH_DPW ROK
RSMRST#

AW41
BA47 PCH_PWROK
RSMRST#
GPD2/LAN_WAKE#
GPD1/ACPRESENT
SLP_SUS#
BG42
BD39
BE46
AC_PRESENT
SLP_SUS#_R
PW R_BTN#
LAN_W AKEUP#
AC_PRESENT

PW R_BTN# 47
31,43,47
47
PCH 4/9
32 PCH_DPW ROK GPD3/PWRBTN# AU2 SYS_RESET#
D03 Raven modfiy 0417 SKIN_THRM_SNSR_ALERT_N BE25 DSW_PWROK
41 SKIN_THRM_SNSR_ALERT_N SYS_RESET# AW29 SPKR_SMC_EXTSMI R390 *10mil_short
SMB_CLK BE26 GPP_C2/SMBALERT# PCH_SPKR 77
32,52 SMB_CLK GPP_B14/SPKR AE3
SMB_DATA BF26 GPP_C0/SMBCLK H_PW RGD 4
32,52 SMB_DATA CPUPWRGD
GPP_C5 BF24 GPP_C1/SMBDATA
GPP_C5/SML0ALERT# AL3 ITP_PMODE 1.05DX_VCCSTG
SML0_CLK
1
2

BF25 ITP_PMODE
C SML0_DATA GPP_C3/SML0CLK AH4 H_TCK 4
C
BE24 PCH_JTAGX H_TDO
PCH_HOT_GNSS_DISABLE GPP_C4/SML0DATA AJ4 H_TMS 4 R674 100_04
J_RTC1 BD33 PCH_JTAG_TMS
SMC_CPU_THERM GPP_B23/SML1ALERT#/PCHHOT# AH3 H_TDO 4
50271-0020N-001 BF27 PCH_JTAG_TDO
D02_102518_Alex_Typec DP issue SMD_CPU_THERM GPP_C6/SML1CLK AH2 H_TDI 4
BE27 PCH_JTAG_TDI PCH_JTAG_TCK
PCB Footprint = 85204-02R GPP_C7/SML1DATA AJ3 R372 51_04
PCH_JTAG_TCK
P/N = 6-20-43130-102 4 OF 13
HM370_MP
?

VDD3
VDDQ
VDD3
3.3VA
DRAM_RST#
R432 VDD3
R230 SMC_CPU_THERM 1 8
470_04 47K_04 SMD_CPU_THERMRN6
U24 2 7 1K_8P4R_04
R425

5
TC7SZ08FU SMB_CLK 3 6
1 SMB_DATA 4 5
DDR4_DRAMRST# 47K_04
DDR4_DRAMRST# 8,9 4 RSMRST#
2

D
C640
SML0_CLK R639 1K_04
R428 0_04 G Q47

3
*0.1u_10V_X7R_04 24 NV_EN_DOW N SML0_DATA R401 1K_04
2SK3018S3

S
C
D30 SUSW ARN# R417 1K_04
VIN C A R427 90.9K_1%_04 B Q46
B B
ZD5231BS2 E MMBT3904H
C850 R426

Flash Descriptor Security Overide VDD3


20K_1%_04
*0.1u_25V_X5R_04.

Low = Disabled-(Default) D02_1108_Alex


High = Enabled PCIE_W AKE# R636 1K_04
47 EC_RSMRST# PW R_BTN# R628 *100K_04
R645 1K_04
ME_W E 47
D47 PM_BATLOW # 1 8
AC_PRESENT RN7 2 7 10K_8P4R_04
A C HDA_SDOUT 3.3VS
HDA_SDOUT 34,77 3 6
SYS_RESET# 4 5
RB751S-40H
PM_CLKRUN# R386 8.2K_04
VCC_3P3DSW_PWRGD Design Note:
ESPI/LPC SELECT STRAP TOP SWAP OVERRIDE STRAP DCI BSSB MODE PCH_DPWROK > 10ms Delay
PCH HAS INTERNAL WEAK PD
IF SAMPLED HIGH, ESPI HIGH:TOP SWAP ENABLED TLS CONFIDENTIALITY ENABLED
IS SELECTED ELSE LPC LOW:TOP SWAP DISABLED(DEFAULT) PCH_DPW ROK RSMRST# R433 100K_04
PCH HAS INTERNAL WEAK PCH HAS INTERNAL WEAK PD IF SAMPLED HIGH(DEFAULT) R396 *20mil short-p RSMRST#
PD
3.3VS 3.3VA
PCH HAS INTERNAL WEAK PD

SUS_CLK R423 *1.5K_04


R638 4.7K_04 SKIN_THRM_SNSR_ALERT_N
3.3VA
R391 R402
A

    
A

150K_1%_04 *4.7K_04    


SPKR_SMC_EXTSMI PCH_HOT_GNSS_DISABLE

VIN
3.3VA
29,49,50,51,52,53,54,55,56,57,59,78
4,31,32,33,37,39,45,50,55
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
1.05DX_VCCSTG 4,6,55 Title
VCC_RTC 31,37 [34] PCH 4/12-HDA/SMBUS/RTC
VDDQ 6,8,9,50,52
3.3VS Size
8,9,23,24,27,29,30,31,32,33,35,36,39,40,41,43,44,45,47,49,50,54,61,74,77 Document Number Rev
VDD3 4,23,24,31,32,37,40,41,43,45,47,48,49,50,51,54,55,57,58,59,60,61,62,65,74,77,78
A3 SCHEMATIC1 6-71-NH500-D02 D02

Date: W ednesday, December 05, 2018 Sheet 34 of 78


5 4 3 2 1

PCH 4/9 B - 35
Schematic Diagrams

PCH 5/9
5 4 3 2 1

3.3VS

modification 0507 Biaggi

R346 R345
?
?
*100K_04 *100K_04
U40E
?
AL13 I_MDP_CLK
GPP_I5/DDPB_CTRLCLK I_MDP_DATA I_MDP_CLK 27
MDP OUT (B) (iGPU) 27 I_MDP_HPD AT6 AR8
GPP_I0/DDPB_HPD0/DISP_MISC0 GPP_I6/DDPB_CTRLDATA I_MDP_DATA 27
HDMI OUT(C) AN10 AN13
23,30 HDMI_HPD R340 *1K_04 AP9 GPP_I1/DDPC_HPD1/DISP_MISC1 GPP_I7/DDPC_CTRLCLK AL10
D D
R343 1K_04 AL15 GPP_I2/DDPD_HPD2/DISP_MISC2 GPP_I8/DDPC_CTRLDATA AL9
DP OUT(E port) (dGPU)
23,73 MDP_E_HPD GPP_I3/DDPF_HPD3/DISP_MISC3 GPP_I9/DDPD_CTRLCLK AR3
GPP_I10/DDPD_CTRLDATA AN40 DGPU_PW R_EN
Biaggi 0507 GPP_F23/DDPF_CTRLDATA DGPU_PW R_EN 24,47
raven del 0731 AT49 DGPU_RST#_PCH
GPP_F22/DDPF_CTRLCLK DGPU_RST#_PCH 23,24
R586 R339 R375
100K_04 100K_04 100K_04 AP41 R369 10K_04 H_SKTOCC_N 4,39
AN6 GPP_F14/PS_ON#
29 EDP_HPD GPP_I4/EDP_HPD/DISP_MISC4
M45 DGPU_PRSNT#
GPP_K23/IMGCLKOUT1 L48 DGPU_PW RGD_R
GPP_K22/IMGCLKOUT0 GC6_FB_EN_PCH DGPU_PW RGD_R 24
R374 T45
GPP_K21 GPU_EVENT# GC6_FB_EN_PCH 24,47
T46
100K_04 GPP_K20 DGPU_SELECT# GPU_EVENT# 23
B.Schematic Diagrams

AJ47
GPP_H23/TIME_SYNC0
HM370_MP 5 OF 13 嶇 BIOS 䡢 娵
?

Sheet 35 of 73 RN36
2.2K_8P4R_04 3.3VS

PCH 5/9 I_MDP_CLK

I_MDP_DATA
1
2
3
8
7
6
4 5
DGPU_SELECT# R673 *10K_04
DGPU_PRSNT# R695 10K_04
? SERIRQ R422 10K_04
?
C U40F DGPU_PW R_EN R357 *10K_04 C
?
F9
42 USB3_TXN1 USB31_1_TXN BB39 R410 15_1%_04
F7 GPP_A1/LAD0/ESPI_IO0 LPC_AD0 47
1-USB3.1(II) Port 1 Charger
42 USB3_TXP1
D11 USB31_1_TXP
GPP_A2/LAD1/ESPI_IO1
AW37 R413 15_1%_04
LPC_AD1 47
42 USB3_RXN1 USB31_1_RXN AV37 R407 15_1%_04
C11 GPP_A3/LAD2/ESPI_IO2 LPC_AD2 47
42 USB3_RXP1 USB31_1_RXP BA38 R416 15_1%_04
GPP_A4/LAD3/ESPI_IO3 LPC_AD3 47
C3
44 USB3_TXN2 USB31_2_TXN
D4
2-USB3.0 Port2(Audio B'd)
44
44
USB3_TXP2
USB3_RXN2
B9 USB31_2_TXP
USB31_2_RXN
GPP_A5/LFRAME#/ESPI_CS0#
BE38
AW35 SERIRQ
LPC_FRAME# 47
C9 GPP_A6/SERIRQ/ESPI_CS1# INTP_OUT SERIRQ 47
44 USB3_RXP2 USB31_2_RXP BA36 INTP_OUT 73
C17 GPP_A7/PIRQA#/ESPI_ALERT0# BE39 SB_KBCRST#
USB31_6_TXN GPP_A0/RCIN#/ESPI_ALERT1# S4_STATE# SB_KBCRST# 47
C16 BF38
G14 USB31_6_TXP GPP_A14/SUS_STAT#/ESPI_RESET#
D03 Raven modfiy 0417 USB31_6_RXN
F14 3.3VS
USB31_6_RXP BB36 CLK_PCI_KBC_R R404 22_04
GPP_A9/CLKOUT_LPC0/ESPI_CLK PCLK_KBC 47
C15 BB34 24 Mhz S4_STATE#
USB31_5_TXN GPP_A10/CLKOUT_LPC1 R630 *10K_04
B15 SMI#_RR
USB31_5_TXP SMI#_RR raven del 0731 1 8
J13 T48 R691 *10mil_short SMI# 47 GPP_F9
USB31_5_RXN GPP_K19/SMI# 2 7
K13 T47 GPP_F8
USB31_5_RXP GPP_K18/NMI# 3 6
SB_KBCRST# 4 5
G12
USB3.1 G2 Port3 to ANX7440 72 ANX7440_SSTXP
F11 USB31_3_TXP AH40 PCH_MUTE#
72 ANX7440_SSTXN USB31_3_TXN GPP_E6/SATA_DEVSLP2 T76 RN1
modfication 0517 Biaggi C10 AH35 R371 *0_04 DEVSLP1 40
72 ANX7440_SSRXP USB31_3_RXP GPP_E5/SATA_DEVSLP1 10K_8P4R_04
B10 AL48 R663 *0_04 DEVSLP0 41 raven add 0629
72 ANX7440_SSRXN USB31_3_RXN GPP_E4/SATA_DEVSLP0 AP47 GPP_F9
C14 GPP_F9/SATA_DEVSLP7 AN37 GPP_F8
B14 USB31_4_TXP GPP_F8/SATA_DEVSLP6 AN46
J15 USB31_4_TXN GPP_F7/SATA_DEVSLP5 AR47 LIGHT_KB_DET#
Remove Biaggi 0507 K16 USB31_4_RXP GPP_F6/SATA_DEVSLP4 AP48 KBLED_DET LIGHT_KB_DET# 47
USB31_4_RXN GPP_F5/SATA_DEVSLP3
B B
HM370_MP 6 OF 13

H: R154--N870RC L: R177--N850RC

USB TABLE H: R154--N870RN L: R177--N850RN

USB2.0 USB3.0 DEVICE


1 1 Charger, PORT 1 3.3VS
3 3,4 GPIO
Type-C H: W/KBLED
Audio USB3.0 Con. L: W/O KBLED
5 5 R659
Audio USB2.0 Con. *10K_04
6
嶇 BIOS 䡢 娵
7 7 3G/LTE KBLED_DET
8 CCD
BT R661
14 *10K_04

A A

ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Title
10,12,13,14,15,17,18,20,21,22,23,24,25,58,61,62,78
4,31,32,33,34,37,39,45,50,55
1V8_AON
3.3VA
[35] PCH 5_6/12-DPP/ESPI/USB3.0
8,9,23,24,27,29,30,31,32,33,34,36,39,40,41,43,44,45,47,49,50,54,61,74,77 3.3VS Size Document Number Rev
27,30,32,44,45,47,48,49,74,77,78 5VS
A3 SCHEMATIC1 6-71-NH500-D02 D02

Date: W ednesday, December 05, 2018 Sheet 35 of 78


5 4 3 2 1

B - 36 PCH 5/9
Schematic Diagrams

PCH 6/9
5 4 3 2 1

D03 Raven modfiy 0417


C1105 15p_50V_NPO_04 0_04 R688 PCI-E CLK Usage

1 ASM x142 USB 3.1

1
4
6-07-18034-1A0 5 GLAN
X4 R686 6 WLAN
FSX3M_24MHZ
1M_1%_04 8 PEG(NV)
SPEC: 20PPM 9 SSD (X 4 LANE)

2
3
D D
R685 0_04 ?
C1104 15p_50V_NPO_04 ?
U40G
?
BE33
GPP_A16/CLKOUT_48
24 MHz Y3 PCH_XDP_CLK_DN
2015.9.11 D7 CLKOUT_ITPXDP PCH_XDP_CLK_DP
4 CPU_24MHZ_R_DP CLKOUT_CPUNSSC_P Y4
4 CPU_24MHZ_R_DN C6 CLKOUT_ITPXDP_P 100 MHz
CLKOUT_CPUNSSC B6
100 MHz CLKOUT_CPUPCIBCLK PCH_CPU_PCIBCLK_R_DN 4
B8 A6
4 PCH_CPU_BCLK_R_DP CLKOUT_CPUBCLK_PCLKOUT_CPUPCIBCLK_P PCH_CPU_PCIBCLK_R_DP 4
C1096 15p_50V_NPO_04 R623 0_04 4 PCH_CPU_BCLK_R_DN C8
CLKOUT_CPUBCLK
XTAL ᶳ

ᶵ⎗㚱P OWE R
O ᾉ 嘇 XTAL24_O AJ6
U9 CLKOUT_PCIE_N0 AJ7

B.Schematic Diagrams
XTAL_OUT

2
1
32.768KHz ␴
暨 朊ᶵ ⎗ ㇻ V I A


PC
H X5 R622 XTAL24_IN U10 CLKOUT_PCIE_P0
XTAL_IN
XCLK_RBIAS AH9
10M_06 R690 60.4_1%_04 T3 CLKOUT_PCIE_N1
32.768KHZ XCLK_BIASREF AH10
CM200C_32.768KHZ CLKOUT_PCIE_P1

Sheet 36 of 73
3
4
6-22-32R76-0B2 CM200S RTC_X1 BA49 CLK_SRC1_ASM_100_DN/P
6-22-32R76-0BJ RTC_X2 RTCX1 AE14
BA48 CLKOUT_PCIE_N2
RTCX2 AE15
C1097 15p_50V_NPO_04 CLKOUT_PCIE_P2
BF31

RTC(10M RES): DON'T CHANGE TO 0402


CLK_REQ1_ASM_CLKREQ_N BE31
AR32
BB30
GPP_B5/SRCCLKREQ0#
GPP_B6/SRCCLKREQ1#
GPP_B7/SRCCLKREQ2#
GPP_B8/SRCCLKREQ3#
CLKOUT_PCIE_N3
CLKOUT_PCIE_P3
AE6
AE7

AC2
PCH 6/9
BA30 CLKOUT_PCIE_N4
LAN_CLKREQ# GPP_B9/SRCCLKREQ4# AC3
AN29 CLKOUT_PCIE_P4
43 LAN_CLKREQ# W LAN_CLKREQ# GPP_B10/SRCCLKREQ5# 100 MHz
AE47
41 W LAN_CLKREQ# GPP_H0/SRCCLKREQ6# AB2
AC48 CLKOUT_PCIE_N5 CLK_PCIE_GLAN# 43
PEG_CLKREQ# GPP_H1/SRCCLKREQ7# AB3
AE41 CLKOUT_PCIE_P5 CLK_PCIE_GLAN 43
10 PEG_CLKREQ# GPP_H2/SRCCLKREQ8#
C AF48 100 MHz C
3.3VS SSD_CLKREQ# GPP_H3/SRCCLKREQ9# W4
AC41 CLKOUT_PCIE_N6 CLK_PCIE_MINI# 41
41 SSD_CLKREQ# SSD2_CLKREQ# GPP_H4/SRCCLKREQ10# W3
AC39 CLKOUT_PCIE_P6 CLK_PCIE_MINI 41
40 SSD2_CLKREQ# GPP_H5/SRCCLKREQ11#
AE39
GPP_H6/SRCCLKREQ12# W7
AB48 CLKOUT_PCIE_N7
PEG_CLKREQ# GPP_H7/SRCCLKREQ13# W6
1 8 AC44 CLKOUT_PCIE_P7
RN2 2 7 10K_8P4R_04 W LAN_CLKREQ# raven modfiy 0918 AC43 GPP_H8/SRCCLKREQ14#
LAN_CLKREQ# GPP_H9/SRCCLKREQ15# AC14 VGA_PEXCLK# 10
3 6 CLKOUT_PCIE_N8
SSD_CLKREQ# AC15 VGA_PEXCLK 10
4 5 V2 CLKOUT_PCIE_P8
V3 CLKOUT_PCIE_N15
PCIe* 100 MHz CLKOUT_PCIE_P15
CLKOUT_PCIE_N9
U2
U3
T2 CLKOUT_PCIE_P9
T1 CLKOUT_PCIE_N14
CLKOUT_PCIE_P14 AC9 100 MHz
VDD1.05 R692 *2.7K_1%_04 XCLK_RBIAS CLKOUT_PCIE_N10 CLK_PCIE_SSD# 41
AC11
AA1 CLKOUT_PCIE_P10 CLK_PCIE_SSD 41
Y2 CLKOUT_PCIE_N13
CLKOUT_PCIE_P13 AE9 100 MHz
CLKOUT_PCIE_N11 CLK_PCIE_SSD2# 40 raven add 0629
3.3VS AE11
AC7 CLKOUT_PCIE_P11 CLK_PCIE_SSD2 40
R814 AC6 CLKOUT_PCIE_N12 L8
SSD2_CLKREQ# CLKOUT_PCIE_P12 R6
CLKIN_XTAL CLKIN_XTAL_LCP 41
HM370_MP 7 OF 13 FCM1005KF-121T03
10K_04 R356
?

C827
5p_50V_NPO_04
10K_04

B B

D03 Raven modfiy 0417

A A

1V8_AON 10,12,13,14,15,17,18,20,21,22,23,24,25,58,61,62,78
VCC_RTC
VDD3
31,34,37
4,23,24,31,32,34,37,40,41,43,45,47,48,49,50,51,54,55,57,58,59,60,61,62,65,74,77,78 ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
3.3VS 8,9,23,24,27,29,30,31,32,33,34,35,39,40,41,43,44,45,47,49,50,54,61,74,77Title
VDD1.05 37,50,55
[36] PCH 7/12-CLKOUT
Size Document Number Rev
A3 SCHEMATIC1 6-71-NH500-D02 D02

Date: W ednesday, December 05, 2018 Sheet 36 of 78


5 4 3 2 1

PCH 6/9 B - 37
Schematic Diagrams

PCH 7/9
5 4 3 2 1

?
?
U40H
5.95A ?
VDD1.05 AA22 AW9 0.182A R400 *20mil_04 3.3VA
AA23 VCCPRIM_1P051 VCCPRIM_3P32
AB20 VCCPRIM_1P052 BF47 VCC_RTCEXT_CAP
C834 C825 AB22 VCCPRIM_1P053 DCPRTC1 BG47
1u_6.3V_X5R_02 AB23 VCCPRIM_1P054 DCPRTC2 C1098
22u_6.3V_X5R_08 VCCPRIM_1P055
AB27 V23 0.095A R363 *20mil_04 3.3VA
VCCPRIM_1P056 VCCPRIM_3P35 *0.1u_10V_X7R_04
AB28
VCCPRIM_1P057 AN44 0.05A
D03 Raven modfiy 0417 AB30 VCCSPI
AD20 VCCPRIM_1P058
D BC49 0.000416A VCCPRTC3P3 D
AD23 VCCPRIM_1P059
VCCRTC1 BD49 V3.3A_V1.8A_VCCPSPI R745 *20mil_04
AD27 VCCPRIM_1P0510 SPI_3.3V
VCCRTC2
AD28 VCCPRIM_1P0511 AN21 0.145A
AD30 VCCPRIM_1P0512 VCCPGPPG_3P3 R408 *20mil_04
VCCPRIM_1P0513 AY8 0.97A VCC_RTC
AF23 VCCPRIM_3P33
VCCPRIM_1P0516 BB7
AF27 VCCPRIM_3P34
AF30 VCCPRIM_1P0517 AC35 0.262A C844 C843
CLOSE TO PCH VCCPRIM_1P0518 VCCPGPPHK1 AC36 V3.3A_VCCPGPPHK 1u_6.3V_X5R_02 *1u_6.3V_X5R_02
6.66A U26 D03 Raven modfiy 0417
VDD1.05 VCCPGPPHK2
U29 VCCPRIM_1P0523 AE350.174A
VCCPRIM_1P0524 VCCPGPPEF1 R383 *20mil_04 3.3VA
C830 V25 AE36
C832 V27 VCCPRIM_1P0525 VCCPGPPEF2
*1u_6.3V_X5R_02 VCCPRIM_1P0526 AN24 0.14A
B.Schematic Diagrams

22u_6.3V_X5R_06 V28 VCCPGPPD


V30 VCCPRIM_1P0527 AN26 0.343A
D03 Raven modfiy 0417 VCCPRIM_1P0528 VCCPGPPBC1 R387 *20mil_04 3.3VA
V31 AP26
VCCPRIM_1P0529 VCCPGPPBC2
VDD1.05 R366 *20mil_04 0.0012AAD31 AN320.101A
VCCPRIM_1P0514 VCCPGPPA C838 C840

Sheet 37 of 73 VDD1.05 R358 *20mil_04


0.2A
0.42A
AE17
W22
W23
VCCPRIM_1P0515
VCCDUSB_1P051
VCCPRIM_3P31
AT44 0.106A
BE48 0.113A
1u_6.3V_X5R_02

CLOSE TO PCH
*1u_6.3V_X5R_02

R361
D03 Raven modfiy 0417
*20mil_04
C1100 VCCDSW_3P31 BE49 (1-3 mm) 3.3VA

PCH 7/9 C829 VCCDUSB_1P052


VCCDSW_3P32
VCCDSW _1P05 BG45 BB140.00767A C831
*0.1u_10V_X7R_04 BG46 VCCDSW_1P051 VCCHDA *0.1u_10V_X7R_04
VCCDSW_1P052 AG190.766A eSPI:1.8V
0.109A W31 VCCPRIM_1P81 AG20 CLOSE TO PCH LPC:3.3V
1u_6.3V_X5R_02
VCCPRIM_MPHY_1P05 VCCPRIM_1P82 AN15 (1-3 mm)
R362 *20mil_04 0.015A D1 VCCPRIM_1P83 V3.3A_VCCPGPPEF R365 *20mil_04
VDD1.05 VCCPRIM_1P0521 AR15 3.3VA
E1 VCCPRIM_1P84
VCCPRIM_1P0522 BB11
VCCPRIM_1P85 C835
C833 0.213A C49
C VCCAMPHYPLL_1P051 AF190.882A *0.1u_10V_X7R_04 C
*1u_6.3V_X5R_02 D49 VCCPHVLDO_1P81
VCCAMPHYPLL_1P052 AF20
E49 VCCPHVLDO_1P82
VCCAMPHYPLL_1P053
D03 Raven modfiy 0417 0.00428A P2 AG310.193A
P3 VCCA_XTAL_1P051 VCCPRIM_1P0520 AF310.0859A R377 *20mil_04
VCCA_XTAL_1P052 VCCPRIM_1P0519 VDD1.05 1.8VA
VDD1.05 R701 *20mil_04 0.169A W19 AK22
W20 VCCA_SRC_1P051 VCCDPHY_1P243 AK23
VCCA_SRC_1P052 VCCDPHY_1P244 R381 *20mil_04 3.3VA
C1107 0.0198A C1 AJ22
1u_6.3V_X5R_02 C2 VCCAPLL_1P054 VCCDPHY_1P241 AJ23 R355 R378 *20mil_04
VCCAPLL_1P055 VCCDPHY_1P242 3.3VA
0.0085A BG5
V19 VCCDPHY_1P245
VCCA_BCLK_1P05 100_04 R380 *20mil_04 3.3VA
0.021A B1 K47
VDD1.05 R353 *20mil_04 B2 VCCAPLL_1P051 VCCMPHY_SENSE K46 R629 *20mil_04
VCCAPLL_1P052 VSSMPHY_SENSE VDD3
B3
VCCAPLL_1P053 C1101
C1131
C1120 C1109 HM370_MP 8 OF 13 R700 *0.1u_10V_X7R_04
1u_6.3V_X5R_02
22u_6.3V_X5R_08 22u_6.3V_X5R_08
? 100_04
R393 *20mil_04 3.3VA
D03 Raven modfiy 0417
C839
VDD1.05 R697 *20mil_04 0.1u_10V_X7R_04 PCH1.8VA
CLOSE TO PCH
(1-3 mm)

VSSMPHY_SENSE
VCCMPHY_SENSE

50
50
C1106 PCH1.8VA R379 0_06 1.8VA
*22u_6.3V_X5R_08
C1102 R373 *0_06 1P8_LDO
B C836 C837 B
R360 *20mil_04 *1u_6.3V_X5R_02
VDD1.05 4.7u_6.3V_X5R_06 4.7u_6.3V_X5R_06
D03 Raven modfiy 0417

VDD1.05 R703 *20mil_04 R368 *20mil_04 1P8_LDO


R370 *20mil_04 VDD1.05

C1108
1u_6.3V_X5R_02

VDD1.05 R359 *20mil_04

C828
*0.1u_10V_X7R_04

VDD1.05 R350 *20mil_04

C826
1u_6.3V_X5R_02

A A

39
55,62,72
PCH1.8VA
1.8VA ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
4,31,32,33,34,39,45,50,55 3.3VA Title
31
36,50,55
SPI_3.3V
VDD1.05
[37] PCH 8/12-POWER
4,23,24,31,32,34,40,41,43,45,47,48,49,50,51,54,55,57,58,59,60,61,62,65,74,77,78 VDD3 Size Document Number Rev
8,9,23,24,27,29,30,31,32,33,34,35,36,39,40,41,43,44,45,47,49,50,54,61,74,77
31,34
3.3VS
VCC_RTC A3 SCHEMATIC1 6-71-NH500-D02 D02

Date: W ednesday, December 05, 2018 Sheet 37 of 78


5 4 3 2 1

B - 38 PCH 7/9
Schematic Diagrams

PCH 8/9

5 4 3 2 1

?
? ?
?
U40I
?
A2 AL12 U40L
VSS_1 VSS_73 ?
D A28
A3 VSS_2 VSS_74
AL17
AL21
BG3
VSS_145 VSS_196
M24 M5 M14 M4 D
VSS_3 VSS_75 BG33 M32 M-MARK M-MARK M-MARK
A33 AL24 VSS_146 VSS_197
VSS_4 VSS_76 BG37 M34
A37 AL26 VSS_147 VSS_198
VSS_5 VSS_77 BG4 M49
A4 AL29 VSS_148 VSS_199
VSS_6 VSS_78 BG48 M5
A45 AL33 VSS_149 VSS_200
VSS_7 VSS_79 C12 N12
A46 AL38 VSS_150 VSS_201
VSS_8 VSS_80 C25 N16
A47 AM1 VSS_151 VSS_202
VSS_9 VSS_81 C30 N34
A48 AM18 VSS_152 VSS_203
VSS_10 VSS_82 C4 N35
A5 AM32 VSS_153 VSS_204 M17 M3 M1
VSS_11 VSS_83 C48 N37
A8 AM49 VSS_154 VSS_205 M-MARK M-MARK M-MARK
VSS_12 VSS_84 C5 N38
AA19 AN12 VSS_155 VSS_206
VSS_13 VSS_85 D12 P26

B.Schematic Diagrams
AA20 AN16 VSS_156 VSS_207
VSS_14 VSS_86 D16 P29
AA25 AN34 VSS_157 VSS_208
VSS_15 VSS_87 D17 P4
AA27 AN38 VSS_158 VSS_209
VSS_16 VSS_88 D30 P46
AA28 AP4 VSS_159 VSS_210
VSS_17 VSS_89 D33 R12
AA30
AA31
AA49
AA5
VSS_18
VSS_19
VSS_20
VSS_90
VSS_91
VSS_92
AP46
AR12
AR16
AR34
D8
E10
E13
VSS_160
VSS_161
VSS_162
VSS_163
VSS_211
VSS_212
VSS_213
VSS_214
R16
R26
R29
M18
M-MARK
M19
M-MARK Sheet 38 of 73
VSS_21 VSS_93 E15 R3
AB19
AB25
AB31
AC12
VSS_22
VSS_23
VSS_24
VSS_94
VSS_95
VSS_96
AR38
AT1
AT16
AT18
E17
E19
E22
VSS_164
VSS_165
VSS_166
VSS_167
VSS_215
VSS_216
VSS_217
VSS_218
R34
R38
R4
PCH 8/9
VSS_25 VSS_97 E24 T17
AC17 AT21 VSS_168 VSS_219
VSS_26 VSS_98 E26 T18
AC33 AT24 VSS_169 VSS_220
VSS_27 VSS_99 E31 T32
AC38 AT26 VSS_170 VSS_221
VSS_28 VSS_100 E33 T4
AC4 AT29 VSS_171 VSS_222
VSS_29 VSS_101 E35 T49
AC46 AT32 VSS_172 VSS_223
VSS_30 VSS_102 E40 T5
C AD1
AD19 VSS_31 VSS_103
AT34
AT45
E42 VSS_173
VSS_174
VSS_224
VSS_225
T7 C
VSS_32 VSS_104 E8 U12 H25 H19 H12
AD2 AV11 VSS_175 VSS_226
VSS_33 VSS_105 F41 U15 C111D111N C111D111N C111D111N
AD22 AV39 VSS_176 VSS_227
VSS_34 VSS_106 F43 U17
AD25 AW10 VSS_177 VSS_228
VSS_35 VSS_107 F47 U21
AD49 AW4 VSS_178 VSS_229
VSS_36 VSS_108 G44 U24
AE12 AW40 VSS_179 VSS_230 H28
VSS_37 VSS_109 G6 U33
AE33 AW46 VSS_180 VSS_231 2 4
VSS_38 VSS_110 H8 U38
AE38 B47 VSS_181 VSS_232
VSS_39 VSS_111 J10 V20
AE4 B48 VSS_182 VSS_233 3 1 5
VSS_40 VSS_112 J26 V22
AE46 B49 VSS_183 VSS_234
VSS_41 VSS_113 J29 V4
AF22 BA12 VSS_184 VSS_235
VSS_42 VSS_114 J4 V46
AF25 BA14 VSS_185 VSS_236 MTH7_0D2_8
VSS_43 VSS_115 J40 W25
AF28 BA44 VSS_186 VSS_237 GND GND
AG1 VSS_44
VSS_45
VSS_116
VSS_117
BA5
J46
J47 VSS_187 VSS_238
W27
W28
M/B PCH
AG22 BA6 VSS_188 VSS_239
VSS_46 VSS_118 J48 W30 H27 H23 H18 H20 H29 H30 H31
AG23 BB41 VSS_189 VSS_240
VSS_47 VSS_119 J9 Y10 2 4 2 4 2 4 2 4 2 42 42 4
AG25 BB43 VSS_190 VSS_241
VSS_48 VSS_120 K11 Y12
AG27 BB9 VSS_191 VSS_242
VSS_49 VSS_121 K39 Y17 3 1 5 3 1 5 3 1 5 3 1 5 3 1 53 1 53 1 5
AG28 BC10 VSS_192 VSS_243
VSS_50 VSS_122 M16 Y33
AG30 BC13 VSS_193 VSS_244
VSS_51 VSS_123 M18 Y38
AG49 BC15 VSS_194 VSS_245
VSS_52 VSS_124 M21 Y9 MTH7_0D2_8 MTH7_0D2_8 MTH7_0D2_8 MTH7_0D2_8 MTH7_0D2_8 MTH7_0D2_8 MTH7_0D2_8
AH12 BC19 VSS_195 VSS_246
AH17 VSS_53 VSS_125 BC24 12 OF 13 GND GND GND GND GND GND GND GND
AH33 VSS_54 VSS_126 BC26
AH38 VSS_55 VSS_127 BC31 ? HM370_MP
AJ19 VSS_56 VSS_128 BC35
AJ20 VSS_57 VSS_129 BC40
VSS_58 VSS_130 H22
AJ25 BC45 H10
AJ27 VSS_59 VSS_131 BC8 H8_5D6_5 H11
B AJ28 VSS_60
VSS_61
VSS_132
VSS_133
BD43
2
H26
4
H6_0D3_7 2 4 B
AJ30 BE44
AJ31 VSS_62 VSS_134 BF1 3 1 5
VSS_63 VSS_135 3 1 5
AK19 BF2
AK20 VSS_64 VSS_136 BF3
AK25 VSS_65 VSS_137 BF48 MTH7_0D2_8
VSS_66 VSS_138 MTH7_0D2_8
AK27 BF49
AK28 VSS_67 VSS_139 BG17 GND GND GND
VSS_68 VSS_140 GND GND GND
AK30 BG2
AK31 VSS_69 VSS_141 BG22
AK4 VSS_70 VSS_142 BG25 H14
VSS_71 VSS_143 H21
AK46 BG28 H8_5D6_5 H8_5D6_5
VSS_72 VSS_144 H17
9 OF 13 H38 2 4
HM370_MP nh_C111D111N
? 3 1 5

MTH7_0D2_8

GND GND GND

H35 H36 H37


H40 h2_8d1_8
h2_8d1_8 h2_8d1_8 h2_8d1_8

A A

ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Title
[38] PCH 9_12/12-VSS,Holes
Size Document Number Rev
A3 SCHEMATIC1 6-71-NH500-D02 D02

Date: W ednesday, December 05, 2018 Sheet 38 of 78

5 4 3 2 1

PCH 8/9 B - 39
Schematic Diagrams

PCH 9/9

5
NO REBOOThis signal has an integrated weak BOOT STARP 4 3 2 1
pull-down resistor (20 K
nominal) to This signal has an integrated weak
disable the no reboot strap functionality pull-down resistor (20 K
nominal)
by default. to default boot from SPI.

To enable no reboot on TCO Timer To enable boot to LPC, this signal


expiration, this signal should be should be pulled up to V3.3S through
pulled-up to V3.3S through a 1k to 2.2 K
a 1k to 2.2 K
± 5% resistor. ?
± 5% resistor. 3.3VA ?
3.3VS U40J
? Y14
RSVD7 Y15
R388 RSVD8
U37
D R642
*4.7K_04
RSVD6
RSVD5
U35 D
*4.7K_04 N32
LPSS_GSPI1_MOSI RSVD3 R32
LPSS_GSPI0_MOSI RSVD4
AH15
RSVD2 AH14
RSVD1
3.3VS

GPIO AL2 H_PREQ# 4


H: W / TPM PREQ# AM5
PRDY# H_PRDY# 4
L: W/O TPM R397 AM4
B.Schematic Diagrams

CPU_TRST# H_TRST# 4
10K_04 AK3 PCH_2_CPU_TRIGGER_R R670 30.1_1%_04 PCH_2_CPU_TRIGGER 6
TRIGGER_OUT
嶇 BIOS 䡢 娵 TPM
TRIGGER_IN
AK2 CPU_2_PCH_TRIGGER 6
TPM_DET 10 OF 13
HM370_MP
?
R406
100K_04

Sheet 39 of 73 W /O TPM ?
?
U40K ?
LPSS_GSPI1_MOSI BA26
GPP_B22/GSPI1_MOSI BA20

PCH 9/9
BD30 GPP_D9/ISH_SPI_CS#/GSPI2_CS0#
GPP_B21/GSPI1_MISO BB20
AU26 GPP_D10/ISH_SPI_CLK/GSPI2_CLK
GPP_B20/GSPI1_CLK BB16
AW26 GPP_D11/ISH_SPI_MISO/GP_BSSB_CLK/GSPI2_MISO
3.3VS GPP_B19/GSPI1_CS0# AN18
LPSS_GSPI0_MOSI BE30 GPP_D12/ISH_SPI_MOSI/GP_BSSB_DI/GSPI2_MOSI
C Leakage BD29 GPP_B18/GSPI0_MOSI BF14 C
BF29 GPP_B17/GSPI0_MISO GPP_D16/ISH_UART0_CTS#/CNV_WCEN AR18
*10K_04 R647 SMI#_R
BB26 GPP_B16/GSPI0_CLK GPP_D15/ISH_UART0_RTS#/GSPI2_CS1#/CNV_WFEN BF17
GPP_B15/GSPI0_CS0# GPP_D14/ISH_UART0_TXD/I2C2_SCL BE17
D02_1109_Alex GPP_D13/ISH_UART0_RXD/I2C2_SDA
BB24
BE23 GPP_C9/UART0A_TXD
AP24 GPP_C8/UART0A_RXD
BA24 GPP_C11/UART0A_CTS#
GPP_C10/UART0A_RTS#
PCH1.8VA BD21 AG45
AW24 GPP_C15/UART1_CTS#/ISH_UART1_CTS# GPP_H20/ISH_I2C0_SCL AH46
AP21 GPP_C14/UART1_RTS#/ISH_UART1_RTS# GPP_H19/ISH_I2C0_SDA
AU24 GPP_C13/UART1_TXD/ISH_UART1_TXD AH47
GPP_C12/UART1_RXD/ISH_UART1_RXD GPP_H22/ISH_I2C1_SCL AH48
R655 GPP_H21/ISH_I2C1_SDA
DEL ASM_SMI# AV21
DEBUG AW21 GPP_C23/UART2_CTS#
10K_04 TX -> D+ GPP_C22/UART2_RTS#
R411 *0_06 UART2_TXD BE20
RX -> D- R420 *0_06 UART2_RXD BD20 GPP_C21/UART2_TXD AV34 DGPU_PW M_SELECT#
D02_102518_Alex_Typec DP issue GPP_C20/UART2_RXD GPP_A23/ISH_GP5 T83
GPP_J1 AW32
R421 *0402_short SMC_7411_I2C GPP_A22/ISH_GP4 3G_CONFIG2 SATA_PW R_EN 44
BE21 BA33 T85
73 SMC_7411 R412 *0402_short SMD_7411_I2C GPP_C19/I2C1_SCL GPP_A21/ISH_GP3
BF21 BE34
73 SMD_7411 GPP_C18/I2C1_SDA GPP_A20/ISH_GP2
BC22 BD34
BF23 GPP_C17/I2C0_SCL GPP_A19/ISH_GP1 BF35 SB_BLON
R4894 *0402_short Raven add 0731
GPP_C16/I2C0_SDA GPP_A18/ISH_GP0 SB_BLON 29
44 I2C_SCL_TP R4895 *0402_short BD38
BE15 GPP_A17/SD_VDD1_PWR_EN#/ISH_GP7
PCH1.8VA 44 I2C_SDA_TP GPP_D4/ISH_I2C2_SDA/I2C3_SDA/SBK4/BK4
BE14
GPP_D23/ISH_I2C2_SCL/I2C3_SCL
XTAL SELECT-1
D02_102518_Alex_Typec DP/TP issue
嶇 BIOS 䡢 娵
HIGH -> 24 MHZ HM370_MP
? 11 OF 13
LOW -> 38.4 MHZ ?
R395 ?
B U40M
B
10K_04 3.3VS *10K_04 R394
嶇 BIOS 䡢 娵 ?
BD4
BOARD_ID1 CNV_WR_CLKN CNVI_W GR_CLKN 41
NH70 10K_04 R389 AW13 BE3 㴰 SB_BLO
D02_1109_Alex_⍾ N pul 枸

l Hig
h
CNVI_BRI_DT BOARD_ID2 GPP_G0/SD_CMD CNV_WR_CLKP CNVI_W GR_CLKP 41
3.3VS *10K_04 R634 BE9
D01A for CNVI samuel TPM_DET BF8 GPP_G1/SD_DATA0 BB3
GPP_G2/SD_DATA1 CNV_WR_D0N CNVI_W GR_D0N 41
10K_04 R635 BF9 BB4
R392 24 GPIO4_1V8_MAIN_EN_R GPP_G3/SD_DATA2 CNV_WR_D0P CNVI_W GR_D0P 41
BG8 BA3
SMI#_R GPP_G4/SD_DATA3 CNV_WR_D1N CNVI_W GR_D1N 41
BE8 BA2
GPP_G5/SD_CD# CNV_WR_D1P CNVI_W GR_D1P 41
*10K_04 BD8
AV13 GPP_G6/SD_CLK BC5
GPP_G7/SD_WP CNV_WT_CLKN CNVI_W T_CLKN 41
BB6
CNV_WT_CLKP CNVI_W T_CLKP 41
4,35 H_SKTOCC_N 10K_04 R376 AP3
AP2 GPP_I11/M2_SKT2_CFG0 BE6
GPP_I12/M2_SKT2_CFG1 CNV_WT_D0N CNVI_W T_D0N 41
AN4 BD7
GPP_I13/M2_SKT2_CFG2 CNV_WT_D0P CNVI_W T_D0P 41
AM7 BG6
PCH1.8VA PCH1.8VA GPP_I14/M2_SKT2_CFG3 CNV_WT_D1N CNVI_W T_D1N 41
BF6
CNV_WT_D1P CNV_W T_RCOMP CNVI_W T_D1P 41
AV6 BA1 150_1%_04 R652
41 CNVI_GNSS_PA_BLANKING GPP_J0/CNV_PA_BLANKING CNV_WT_RCOMP
AY3 Differential between RCOMPN/RCOMPP.
50,55 GPP_J1 GPP_J1/CPU_C10_GATE# PCIECOMP_N
100K_04 R384 AR13 B12 100_1%_04 R702
M.2 CNVI STRAP PCH1.8VA R654 R660 AV7 GPP_J11/A4WP_PRESENT PCIE_RCOMPN A13 PCIECOMP_P Length matched to less than 1% trace.
HIGH -> DISABLE 100K_04 R657 AW3 GPP_J10 PCIE_RCOMPP BE5 SD3_RCOMP_1P8 200_1%_04 R633
LOW -> ENABLE
20K_04 20K_04 100K_04 R382 AT10 GPP_J2 SD_1P8_RCOMP BE4 SD3_RCOMP_3P3 200_1%_04 R405
33_04 R658 AV4 GPP_J3 SD_3P3_RCOMP BD1 GPPJ_RCOMP_1P8
41 CNVI_BRI_DT GPP_J4/CNV_BRI_DT/UART0B_RTS# GPPJ_RCOMP_1P81
R399 AY2 BE1
41 CNVI_BRI_RSP GPP_J5/CNV_BRI_RSP/UART0B_RXD GPPJ_RCOMP_1P82
33_04 R650 BA4 BE2 200_1%_04 R648
41 CNVI_RGI_DT GPP_J6/CNV_RGI_DT/UART0B_TXD GPPJ_RCOMP_1P83
20K_04 AV3
41 CNVI_RGI_RSP GPP_J7/CNV_RGI_RSP/UART0B_CTS#
AW2 Y35
41 CNVI_MFUART2_RXD GPP_J8/CNV_MFUART2_RXD RSVD2
AU9 Y36
A CNVI_RGI_DT 41 CNVI_MFUART2_TXD GPP_J9/CNV_MFUART2_TXD RSVD3 A
BC1
RSVD1 AL35
TP T78
R409 13 OF 13

*100K_04
D01A for CNVI samuel
HM370_MP ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
?
Title
[39] PCH 10_11/12-UART/I2C/GPIO
4,31,32,33,34,37,45,50,55 3.3VA
4,23,24,31,32,34,37,40,41,43,45,47,48,49,50,51,54,55,57,58,59,60,61,62,65,74,77,78 VDD3 Size Document Number Rev
8,9,23,24,27,29,30,31,32,33,34,35,36,40,41,43,44,45,47,49,50,54,61,74,77
37
3.3VS
PCH1.8VA
A3 SCHEMATIC1 6-71-NH500-D02 D02

Date: W ednesday, December 05, 2018 Sheet 39 of 78

5 4 3 2 1

B - 40 PCH 9/9
Schematic Diagrams

M.2 Card
5 4 3 2 1

NGFF_M (M2) SSD (PCIE 4X)


3.3VS
D >120 mil D
M2_SSD2_3.3VS
J_SSD2
R840 C598 C601 C604
H: PCIe 75
10K_04 73 GND13 74 *0.1u_10V_X7R_04 0.1u_10V_X7R_04
GND12 3.3V8 22u_6.3V_X5R_06
71 72
69 GND11 3.3V7 70
67 PEDET(NC-PCIe/GND-SATA) 3.3V6 68 GND GND
NC18 SUSCLK(32Khz)(O) GND

M KEY
57 58
55 GND10 NC17 56
36 CLK_PCIE_SSD2 REFCLKP NC16
53 54 SSD_CLKREQ# Pu 10K near to PCH-H.

B.Schematic Diagrams
36 CLK_PCIE_SSD2# REFCLKN PEWake#(IO)
51 52
GND9 CLKREQ#(IO) SSD2_CLKREQ# 36
49 50
32 PCIE_TXP21_SSD PETp0/SATA-A+ PERST#(O) BUF_PLT_RST# 32,41,43,47
47 48
32 PCIE_TXN21_SSD PETn0/SATA-A- NC15
45 46
R769 *10mil_short 43 GND8 NC14 44
32 PCIE_RXP21_SSD PERp0/SATA-B- NC13
R770 *10mil_short 41 42
32 PCIE_RXN21_SSD PERn0/SATA-B+ NC12
Reserved 39 40
37 GND7 NC11 38
32
32

32
PCIE_TXP22_SSD
PCIE_TXN22_SSD

PCIE_RXP22_SSD
35
33
31
PETp1
PETn1
GND6
PERp1
DEVSLP(O)
NC10
NC9
NC8
36
34
32
DEVSLP1 35

DEBUG PORT Sheet 40 of 73


29 30

C M2. PCIE change(21~24)


32

32
32
PCIE_RXN22_SSD

PCIE_TXP23_SSD
PCIE_TXN23_SSD
27
25
23
PERn1
GND5
PETp2
PETn2
NC7
NC6
NC5
NC4
28
26
24
M2_SSD2_3.3VS

C602
raven Del 0629
C M.2 Card
21 22
GND4 NC3 0.1u_6.3V_X5R_02
19 20 3.3VS
32 PCIE_RXP23_SSD PERp2 NC2
17 18
32 PCIE_RXN23_SSD PERn2 3.3V5 R4939 10K_04
15 16
13 GND3 3.3V4 14
32 PCIE_TXP24_SSD PETp3 3.3V3 GND
11 12
32 PCIE_TXN24_SSD PETn3 3.3V2
9 10
GND2 DAS/DSS#(I)(OD) M2M_SSD2_LED# 45
7 8
32 PCIE_RXP24_SSD PERp3 NC1
5 6 80 mils
32 PCIE_RXN24_SSD PERn3 NC0
3 4 M2_SSD2_3.3VS
1 GND1 3.3V1 2
GND0 3.3V0
C596 C599
NFSM0-S6701-TP40 0.1u_10V_X7R_04 *0.1u_10V_X7R_04
P/N = 6-21-84KE0-075
GND PCB Footprint = NXSM0-S67XX-XX40
PCB Footprint婳
䡢娵
㨇㥳 ἧ 䓐 䘬 C o n ne ctor
GND GND
RTD3 POWER >120 mil
C597 C600 C603

*0.1u_10V_X7R_04 0.1u_10V_X7R_04
22u_6.3V_X5R_06

GND GND GND


B B

3.3VS 3.3VS
C1250 U52 *G5016 C1253

*0.1u_6.3V_X5R_02 1 6 *0.1u_6.3V_X5R_02
2 IN1 IN2 7
M2_SSD2_3.3VS IN1 IN2
6A 13
14 OUT1 OUT2
8
9
6A M2_SSD1_3.3VS
C1249 OUT1 OUT2 C1246
M2_SSD2_3.3VS
3.3VS 12 10
*0.1u_6.3V_X5R_02 CT1 CT2 *0.1u_6.3V_X5R_02
VBIAS

R4911 0_06
GND

GND
EN1

EN2

C1248 C1252
R4910 0_06 *470p_50V_X7R_04 *470p_50V_X7R_04
3.3VS
3

15

11

R4909 *10K_04 3.3VS


D02_1101_Alex
R4908
*10K_04 VDD3 SATA_M2_PW R_EN1 33
C1245 C1255
C1254
*1u_6.3V_X5R_02
33 SATA_M2_PW R_EN2 *0.1u_6.3V_X5R_02
*0.1u_6.3V_X5R_02
A A

ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Title
M2_SSD1_3.3VS 41 [40] M.2 3G Card
3.3V 2,24,29,42,44,49,50,52,53,56,59,60,61,72,73
3.3VS Size
8,9,23,24,27,29,30,31,32,33,34,35,36,39,41,43,44,45,47,49,50,54,61,74,77 Document Number Rev
VDD3 4,23,24,31,32,34,37,41,43,45,47,48,49,50,51,54,55,57,58,59,60,61,62,65,74,77,78
A3 SCHEMATIC1 6-71-NH500-D02 D02
5V 29,42,44,49,50,52,55,60,73
Date: W ednesday, December 05, 2018 Sheet 40 of 78

5 4 3 2 1

M.2 Card B - 41
Schematic Diagrams

M.2 WLAN+BT
5 4 3 2 1

J_WLAN1

39
WLAN+BT
CNVI_WT_CLKP
75
73
71
GND13
WT_CLKP
3.3V3
3.3V2
74
72
70
40 mil

C1093 C1092 C1094


WLAN_3.3V

39 CNVI_WT_CLKN WT_CLKN PEWAKE1_N


69 68
67 GND12 CLKREQ1_N 66 22u_6.3V_X5R_06 22u_6.3V_X5R_06 *0.1u_6.3V_X5R_02
39 CNVI_WT_D0P WT_D0P PERST1_N
65 64
39 CNVI_WT_D0N WT_D0N REFCLK0 CLKIN_XTAL_LCP 36 VDD3
63 62
61 GND11 IRQ_N(I) 60 R621 10K_04
39 CNVI_WT_D1P WT_D1P I2C CLK(O) WLAN_3.3V WLAN_3.3V
59 58 R436 10K_04
39 CNVI_WT_D1N WT_D1N I2C DATA(IO)
57 56 R619 0_04
GND10 W_DISABLE1_N(O) WLAN_EN 47 U39
D D02_1109_Alex 55 54 >120 mil >120 mil D
PEWAKE0_N W_DISABLE2_N(O) BT_EN 47
53 52 5 1
36 WLAN_CLKREQ# CLKREQ0_N PERST0_N(O) BUF_PLT_RST# 32,40,41,43,47 VIN VOUT
3.3VS R678 *10K_04 51 50
GND9 SUSCLK(32Khz)(O) SUS_CLK 34
49 48 R618 *33_04 C1084 4 C1095
36 CLK_PCIE_MINI# REFCLKN0 COEX1_TXD(I/O)1.8V CNVI_MFUART2_RXD 39 VIN/SS
47 46 R617 *33_04
36 CLK_PCIE_MINI REFCLKP0 COEX2_RXD(I/O)1.8V CNVI_MFUART2_TXD 39
45 44 R616 *33_04 1u_6.3V_X5R_02 3 2 0.1u_6.3V_X5R_02
GND8 COEX3(I/O)1.8V CL_CLK CNVI_GNSS_PA_BLANKING 39 EN GND
43 42 R615 *0_04
33 PCIE_RXN14_WLAN PERN0 CLINK_CLK CL_DATA CLINK_CLK 33 Follow
41 40 R614 *0_04 UP7553PMA5-25
33 PCIE_RXP14_WLAN PERP0 CLINK_DATA CL_RST# CLINK_DATA 33 07 PCH _ 07-03-2 M.2 WLAN+BT,CN.pdf
39 38 R613 *0_04 Biaggi 0514
GND7 CLINK_RESET CLINK_RESET 33
37 36 M: NCT3522U -- 6-02-03522-9C0
33 PCIE_TXN14_WLAN PETN0 UART_RTS/BRI_DT CNVI_BRI_DT 39
35 34 R620 22_04 S: AP2821KTR-G1 6-02-02821-9C0
33 PCIE_TXP14_WLAN PETP0 UART_CTS/RGI_RSP CNVI_RGI_RSP 39
33 32
GND6 UART_TX/RGI_DT CNVI_RGI_DT 39 47 WLAN_PWR_EN
Remove 0 ohm R598 0_04
VDD3 Biaggi 0514 ㍍⇘ E C ,枰 冯EC䡢娵
E KEY D02 for CNVI samuel 47,50,55,78 SLP_SUS# R597 *0_04
23 22 R612 22_04
39 CNVI_WGR_CLKP WGR_CLKP UART_RX/BRI_RSP CNVI_WAKE# CNVI_BRI_RSP 39
B.Schematic Diagrams

R604 21 20 R611 0_04


39 CNVI_WGR_CLKN WGR_CLKN UART_WAKE_N SKIN_THRM_SNSR_ALERT_N 34
19 18
10K_04 17 GND5 GND4 16 ADD Biaggi 0514 D01A for CNVI samuel
39 CNVI_WGR_D0P WGR_D0P LED2_N(OD)
15 14
39 CNVI_WGR_D0N WGR_D0N PCM_OUT/CLKREQ0 XTAL_CLKREQ 34
13 12
47 CNVI_DET# GND3 PCM_IN
11 10

Sheet 41 of 73
39 CNVI_WGR_D1P WGR_D1P PCM_SYNC/LCP_RSTN CNVI_RF_RST# 34
L: CNVi
39 CNVI_WGR_D1N
9 8 普ᷕ㷔 溆
H: W/O CNVi 7 WGR_D1N PCM_CLK 6 D02 for CNVI samuel
5 GND2 LED1_N(OD) 4 R606 WLAN_EN
32 USB_PN14 USB_DN 3.3V1 40 mil
3 2 R610
32 USB_PP14 USB_DP 3.3V0 WLAN_3.3V BT_EN
1

M.2 WLAN+BT
75K_1%_04
GND1 C1091 71.5K_1%_04
C WLAN_PWR_EN C
NFSE0-S6701-AP64
22u_6.3V_X5R_06 WLAN_3.3V
P/N = 6-21-84K03-075
PCB Footprint = argosy_nfse0-s6701-tp64
PCB Footprint婳
䡢娵㨇
㥳 ἧ 䓐 䘬 C o n ne ctor

NGFF_M (M2) SSD (PCIE 4X) M2_SSD1_3.3VS


3.3VS

R194 0_06

R195 0_06
3A
3.3VS
>120 mil
M2_SSD1_3.3VS
J_SSD1
D02_1105_Alex
R774 C591 C594 C610
SATAGP1 75
10K_04 73 GND13 74 *0.1u_10V_X7R_04 0.1u_10V_X7R_04
H: PCIe GND12 3.3V8 22u_6.3V_X5R_06
L: SATA 71 72
69 GND11 3.3V7 70
33 SATAGP1 PEDET(NC-PCIe/GND-SATA) 3.3V6
67 68 GND GND
NC18 SUSCLK(32Khz)(O) GND

B
M KEY B
57 58
55 GND10 NC17 56
36 CLK_PCIE_SSD REFCLKP NC16
53 54 SSD_CLKREQ# Pu 10K near to PCH-H.
36 CLK_PCIE_SSD# REFCLKN PEWake#(IO)
51 52
GND9 CLKREQ#(IO) SSD_CLKREQ# 36
49 50
33 PCIE_TXP12_SSD PETp0/SATA-A+ PERST#(O) BUF_PLT_RST# 32,40,41,43,47
47 48
33 PCIE_TXN12_SSD PETn0/SATA-A- NC15
45 46
R772 *10mil_short SATA0_RXN_SSD 43 GND8 NC14 44
33 PCIE_RXN12_SSD PERp0/SATA-B- NC13
R773 *10mil_short SATA0_RXP_SSD 41 42 D02_1112_Alex
33 PCIE_RXP12_SSD PERn0/SATA-B+ NC12
Reserved 39 40
37 GND7 NC11 38
33 PCIE_TXP11_SSD PETp1 DEVSLP(O) DEVSLP0 35
35 36 R776 *10mil_short VDD3
33 PCIE_TXN11_SSD PETn1 NC10
33 34 R777 *10mil_short 3IN1
33 PCIE_RXP11_SSD
31 GND6
PERp1
NC9
NC8
32 R778 *10mil_short 80CLK
3IN1
80CLK
47
47
DEBUG PORT
29 30
33 PCIE_RXN11_SSD PERn1 NC7
27 28 M2_SSD1_3.3VS
25 GND5 NC6 26
33 PCIE_TXP10_SSD PETp2 NC5
23 24
33 PCIE_TXN10_SSD PETn2 NC4
21 22 C607
19 GND4 NC3 20 0.1u_6.3V_X5R_02
33 PCIE_RXP10_SSD PERp2 NC2
17 18
33 PCIE_RXN10_SSD PERn2 3.3V5
15 16
13 GND3 3.3V4 14
33 PCIE_TXP9_SSD PETp3 3.3V3
11 12 GND
33 PCIE_TXN9_SSD PETn3 3.3V2
9 10
GND2 DAS/DSS#(I)(OD) M2M_SSD1_LED# 45
7 8
33 PCIE_RXP9_SSD PERp3 NC1
5 6 80 mils
33 PCIE_RXN9_SSD PERn3 NC0
3 4 M2_SSD1_3.3VS
A
1 GND1 3.3V1 2 A
GND0 3.3V0
D02_102518_Alex_M.2 C590 C593 >120 mil
NFSM0-S6701-TP40 0.1u_10V_X7R_04 *0.1u_10V_X7R_04
C592 C595 C611

ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
P/N = 6-21-84KE0-075
GND PCB Footprint = NXSM0-S67XX-XX40
Footprint婳 *0.1u_10V_X7R_04 0.1u_10V_X7R_04
PCB 䡢娵㨇
㥳 ἧ 䓐 䘬 C o n ne ctor 22u_6.3V_X5R_06
GND GND Title
GND GND GND
[41] M.2 WLAN+BT, PCIE4X SSD
3.3V 2,24,29,42,44,49,50,52,53,56,59,60,61,72,73 M2_SSD1_3.3VS 40 Size Document Number Rev
3.3VS
VDD3
8,9,23,24,27,29,30,31,32,33,34,35,36,39,40,43,44,45,47,49,50,54,61,74,77
4,23,24,31,32,34,37,40,43,45,47,48,49,50,51,54,55,57,58,59,60,61,62,65,74,77,78
5V 29,42,44,49,50,52,55,60,73 Custom SCHEMATIC1 6-71-NH500-D02 D02

Date: Wednesday, December 05, 2018 Sheet 41 of 78


5 4 3 2 1

B - 42 M.2 WLAN+BT
Schematic Diagrams

USB Charger
5 4 3 2 1

USB3.1 PORT(PORT3,4) USB3.1 PORT(PORT1) 6-02-75495-9C0


VDD5 USBVCC_CH
W/O USB CHARGER
80 mil U25
80 mil
5 1
C856 VIN VOUT DD_ON# R437 0_04 USB_DD_ON#
49,52 DD_ON#
Remove 3831 CC lOGIC IC_0507 Biaggi 10u_6.3V_X5R_06 2 C857 C858 W/O CHARGER
GND
暞ẞ伖㕤妲嘇 ↮㓗嗽
R439 100K_04 4 3 *0.1u_6.3V_X5R_02
R442 *0_04 CHARGER EN# OC# 0.1u_6.3V_X5R_02
29,32,34,47,49,50,52,55,62 SUSB#
U36
Default Low USB_PN1 R438 0_04 B_UDN
CHARGER uP7549UMA5-20
R443 0_04 8 1 USB_DD_ON#
47,49,51,78 DD_ON CB PRE# W/O CHARGER
CHARGER
USB_PN1 7 2 B_UDN
32 USB_PN1 TDM DM USB_PP1 B_UDP
R440 0_04
USB_PP1 6 3 B_UDP
32 USB_PP1 TDP DP W/O CHARGER

GND
VDD5
5 4 CDP VDD5
D VCC CDP D
暞ẞ伖㕤妲嘇 ↮㓗嗽
C855 SLG55593VTR R590

9
TDFN8-2X2MM R592 10K_04
0.1u_6.3V_X5R_02 CHARGER W/O CHARGER 㗪 W/USB3.1 R2201 STUFF
*10K_04 CB Smart CDP
CHARGER
pin8 pin4 Function W/O CHARGER 㗪 W/USB3.0 R381 STUFF
SLG55583VTR : 6-02-55583-9D0 P2P
SLG55593VTR : 6-02-55593-9D0 DCP autodetect with
0 X mouse/keyboard wake up

1 0 S0 Charging with SDP

1 1 S0 Charging with CDP

B.Schematic Diagrams
Sheet 42 of 73
Remove ASM1562 0522 Biaggi
USB Charger
C
5V

5
U1
1
100 MIL
USBVCC3.1_1
TYPE-C USBVCC3.1_1
A1
J_TYPEC1
UCF3T-21S01-0P11
Y
B12
USBVCC3.1_1 C

C6 IN OUT C4 C5 GND GND


2 NV_TX_1_P_J A2 B11 NV_RX_1_P_J
10u_6.3V_X5R_06 GND *0.1u_6.3V_X5R_02 *0.1u_6.3V_X5R_02 NV_TX_1_N_J A3 TX0_P RX0_P B10 NV_RX_1_N_J
4 3 TX0_N RX0_N
EN OCB C864 1u_6.3V_X5R_02 A4 B9 C870 1u_6.3V_X5R_02
SY6288E1AAC VBUS VBUS
R488 *10K_04 6-02-62881-9C0 R1 0_04 3831_CC1_J A5 B8 TYPEC_SBU2
3.3V T1
CC1 SBU2
Raven Add VBUS 0629 TYPEC_UDP_J A6 B7 TYPEC_UDN_J
TYPEC_UDN_J A7 USB2_P_T USB2_N_B B6 TYPEC_UDP_J
R487 0_04 USB2_N_T USB2_P_B
73 SOURCE_CTRL TYPEC_SBU1 3831_CC2_J
A8 B5
SBU1 CC2
VBUS_USB_TYPE_C C867 1u_6.3V_X5R_02 A9 B4 C869 1u_6.3V_X5R_02
VBUS VBUS
NV_RX_2_N_J A10 B3 NV_TX_2_N_J
Modification 0516 Biaggi
NV_RX_2_P_J A11 RX1_N TX1_N B2 NV_TX_2_P_J
USBVCC3.1_1 VBUS_USB_TYPE_C RX1_P TX1_P
R30 A12 B1
D02_1110_Alex *100_04 GND GND
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8

C865 C866 C868


Remove 0507 Biaggi
10u_25V_X6S_08

1u_25V_X5R_06

0.1u_25V_X5R_04
D

GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8

Q3
_
73 DISCHARGE_CTRL
G
*2SK3018S3 MAIN 6-21-B4K30-024
S

modification 0517 Biaggi


Close to Connector
Remove CC to EC 0507 Biaggi D3

1 10
D4 2 9
To Con. 1 2 3 8
3831_CC1_J 32 USB_PN3 TYPEC_UDN_J
B 1 10 4 7 B
73 CCG2_CC1 3831_CC2_J 4 3 5 6 TYPEC_UDP_J
2 9
73 CCG2_CC2 32 USB_PP3
3 8 L1
4 7 TYPEC_SBU1 *WCM2012F2S-161T03-short DT1140-04LP-7
72 NV_SBU1_J TYPEC_SBU2
5 6
72 NV_SBU2_J
DT1140-04LP-7 close to connector
modification 0507 Biaggi close to connector Raven modfiy 0628
To Con.
To Con.

modification 0509 Biaggi


R449 220K_1%_04 R451 220K_1%_04
R450 220K_1%_04 R454 220K_1%_04
USBVCC_CH C860 *22u_6.3V_X5R_06
GND
NV_RX_1_P_J NV_RX_2_P_J USB3_RXP1 C859 0.1u_10V_X7R_04
72
72
NV_RX_1_P_J
NV_RX_1_N_J
NV_RX_1_N_J 72
72
NV_RX_2_P_J
NV_RX_2_N_J
NV_RX_2_N_J 35
35
USB3_RXP1
USB3_RXN1
USB3_RXN1
USB3.0/3.1 PORT(PORT3) C861 22u_6.3V_X5R_06
GND

GND
1

J_USB1
1

D35 D36
ESDPSA0402V12 D1 D2 D43 D45 D33
ESDPSA0402V12 ESDPSA0402V12 ESDPSA0402V12 USB3_TXP1_RJ 9 GND1
SSTX+ SHIELD

Standard-A
ESDPSA0402V12 ESDPSA0402V12 10 1 1
9 2 USB3_TXN1_RJ 8 VBUS GND3
2

B_UDP 4 3 8 3 2 SSTX- SHIELD


2

_ _
2

L9 USB_PP1R 7 4 USB_PP1RJ 4 D-
_ _ _ _ B_UDN USB_PN1R USB_PN1RJ GND
Raven modfiy 0824 Raven modfiy 0824 1 2 6 5 3
Raven modfiy 0824 D+
*WCM2012F2S-161T03-short 6 GND4
7 SSRX+ SHIELD
TVUDF1004AD0 5 GND_D GND2
C1059 0.22u_10V_X5R_04 USB3_TXP1_RJ USB3_RXP1 SSRX- SHIELD
NV_TX_1_P_J NV_TX_2_P_J 35 USB3_TXP1 C1060 0.22u_10V_X5R_04 USB3_TXN1_RJ USB3_RXN1
72 NV_TX_1_P_J NV_TX_1_N_J 72 NV_TX_2_P_J NV_TX_2_N_J 35 USB3_TXN1 C107NC-90939-L GND
A A
72 NV_TX_1_N_J 72 NV_TX_2_N_J
1
1
1

1
1

D6 D5 D38 D37 D46 D44 GND


ESDPSA0402V12 ESDPSA0402V12 ESDPSA0402V12
ESDPSA0402V12 ESDPSA0402V12 ESDPSA0402V12
2
2
2

2
2

ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Raven modfiy 0824 _
_ _ _ _ _ 73 VBUS_USB_TYPE_C
Raven modfiy 0824 37,55,62,72 1.8VA
Raven modfiy 0824 Title
D03 Raven modfiy 0417
2,24,29,44,49,50,52,53,56,59,60,61,72,73 3.3V
[42] USB3.0/3.1 CON,USB CHARGER
29,44,49,50,52,55,60,73 5V
Size Document Number Rev
8,9,23,24,27,29,30,31,32,33,34,35,36,39,40,41,43,44,45,47,49,50,54,61,74,77
49,51
3.3VS
VDD5 Custom
SCHEMATIC1 6-71-NH500-D02 D02

Date: Wednesday, December 05, 2018 Sheet 42 of 78

5 4 3 2 1

USB Charger B - 43
Schematic Diagrams

Card Reader / LAN RTL8411B

5 4 3 2 1

Crystal 䓐 HSX32 1S(3. 2X2. 5X0. 65)



meet realtek Freq tolerance 50ppm
LAN (RTL8411B) 6 IN 1 SOCKET - MMC / RSMMC
- SD / mini SD / SDHC / SDXC
Co-Lay J_CARD-REV2
RSET R159 2.49K_1%_04 Switching Regulator close to PIN48 SD_D2/MS_CLK_R P9
D03 Raven modfiy 0417 SD_DATA2
R174 *1K_04 SD_D3/MS_D3_R
0_04 R173 XTAL1 P1
Gary_For common design SD_DATA3
R175 10K_04 (>20mil) VDD10
AVDD33 SD_CMD/MS_D2_R P2
Ra SD_CMD

AVDD33
R176 *10mil_short FOR S5 WAKE UP ON LAN REGOUT R573 *15mil_short_06VDD10

VDD10
R160 1M_04 XTAL2 P3
TO SB PCH WAKE#. (>20mil) SD_VSS1
D C A Ca Cb D
PCIE_W AKE# 34 P4
D15 *RB751S-40H VCC_CARD SD_VDD
1 2 LAN_W AKEUP# TO EC8587 PIN123 LAN_WAKEUP# LDO Mode㗪
: La, Ca, Cb ᶵ
ᶲẞ,R a ᶲ ẞ SD_CLK/MS_D0_R P5
SD_CLK

SD_CD#
LAN_W AKEUP# 31,34,47 C854 C852

XTAL2
XTAL1
慷䓊䡢娵 ⼴ 暣 旣 ,㓡 S H O RT暞 ẞ

EECS
4 3 P6

*0.1u_16V_X7R_04

*0.1u_10V_X7R_04
6-06-75140-068 SD_VSS2
X1 FSX3L 25MHZ SD_D0/MS_D1_R
PCBfootprint: P7
C571 C570 SD_DATA0
HSX321G
SD_D1_R P8
5p_50V_NPO_04 SD_DATA1

48
47
46
45
44
43
42
41
40
39
38
37
5p_50V_NPO_04 GND1
6-07-5R074-1A0 U11 BIOS pulls high or low to GPO pin, MS_BS/SD_W P# GND1
Pkease refer to LAN/PHY Disable P10 GND2
SD_WP GND2
B.Schematic Diagrams

CKXTAL2
CKXTAL1
MS_CD#
SD_CD#
LED0

LED2
LED1/GPO
LV_CEN
HV_GIGA

LED_CR
RSET

LANWAKEB
Application Note. GND3
SPEC:30PPM 49 SD_CD# GND3
E_PAD P11 GND4
SD_C/D GND4
R348 1K_04 3.3VS CM2S-061-H-N
PCB Footprint = SD-10395-001-3

Sheet 43 of 73 LAN_MDIP0 1 36 REGOUT


R347
15K_04
⼭E M I䡢
娵⬴ , 㓡 SH O R T
6-21-A4450-111
LAN_MDIN0 MDIP0 REG_OUT REGOUT
崘ℏ Ⰼ.
Card Reader / 2 35 Remind that R109 using the
MDIN0 VDDREG D3V3 main power (S0 power). SD_CMD/MS_D2 SD_CMD/MS_D2_R
VDD10 3 34 ENSW REG R170 33_04
LAN_MDIP1 4 AVDD10 ENSWREG 33 SD_D0/MS_D1 R157 33_04 SD_D0/MS_D1_R
LAN_MDIN1 MDIP1 VDD1 VDD10 SD_D1 SD_D1_R
5 32 AVDD33 R156 33_04
LAN_MDIP2 MDIN1 VD33 SD_D2/MS_CLK SD_D2/MS_CLK_R
LAN RTL8411B VDD10
LAN_MDIN2

LAN_MDIP3
6
7
8
MDIP2
MDIN2
AVDD10
RTL8411B
ISOLATEBPIN
PERSTBPIN
CLKREQBPIN
31
30
29
ISOLATEB
PERSTB
CLKREQB
MS_BS/SD_W P#
R344 *10mil_short
BUF_PLT_RST# 32,40,41,47
R341 0_04 LAN_CLKREQ# 36
SD_CLK/MS_D0
SD_D3/MS_D3
R172
R158
R171
33_04
33_04
33_04
SD_CLK/MS_D0_R
SD_D3/MS_D3_R

C528
9 28
LAN_MDIN3 10 MDIP3 QFN48 MS_BS/SD_WP# 27 VDD33/18
LAN_CLKREQ#⤪
ᶵἧ䓐⎗㕟 攳
,㕤 P C H 䪗 䚜 ㍍
PUL LD O WN
C
11 MDIN3 DV33_18 26 RTL8411B_HSON C822 0.1u_10V_X7R_04 C
AVDD33 HV_GIGA HSON RTL8411B_HSOP PCIE_RXN15_GLAN 33

*5p_50V_NPO_04
3.3VS 12 25 C821 0.1u_10V_X7R_04
VDD3 HSOP PCIE_RXP15_GLAN 33

SD_CMD/MS_D2
SD_CLK/MS_D0

SD_D2/MS_CLK
D02_1107_Alex
C1016

SD_D0/MS_D1

SD_D3/MS_D3
Close to chip

REFCLK_N
REFCLK_P
CARD_3V3
*0.1u_6.3V_X5R_02

VDDTX
SD_D1
PIN12

HSIN
HSIP
D02_1114_Alex

RTL8411B AVDD33

13
14
15
16
17
18
19
20
21
22
23
24
6-03-08411-032 R354 R352

SD_CMD/MS_D2
SD_CLK/MS_D0

SD_D2/MS_CLK
VDD3

SD_D0/MS_D1

SD_D3/MS_D3
CARD_3V3 CLK_PCIE_GLAN# 36 *28mil short-p *28mil short-p
C1015 C824 C530
CLK_PCIE_GLAN 36

EVDD10
SD_D1

VCC_CARD 0.1u_10V_X5R_02 0.1u_10V_X5R_020.1u_6.3V_X5R_02


PCIE_TXN15_GLAN 33
PCIE_TXP15_GLAN 33 PULL HIGH: SWR Mode
60 mil PIN11 PIN32 PIN48
D02_1107_Alex
D3V3
C853 C851 R349
VDD33/18 ENSW REG *20mil_04 R351
VDD10 VDD10 VDD10 VDD10 CARD_3V3
*0.1u_25V_X5R_04 22u_6.3V_X5R_06
PULL LOW: LDO Mode *28mil short-p LDO Mode
C1014 C1013 C1034 C531 C823 C529


䡢 娵 LDO M ODE O K ⼴,
B 0.1u_25V_X5R_04 0.1u_25V_X5R_04 0.1u_25V_X5R_04 0.1u_25V_X5R_04 0.1u_25V_X5R_04 0.1u_25V_X5R_04 Near Cardreader CONN 㓡S H O R T暞 ẞ B
EVDD10
PIN3 PIN8 PIN32 PIN46 PIN27 PIN13 R574
VDD10

斄攱 ho
t暣 㸸 /
s D㉼ ㍺㗪 , V CC_ C
C
A
R AR
D *20mil_04 C1018 C1017

GIGA LAN (RTL8411) L15


暣⡻ㅱ Ỷ 㕤0.5ặ䈡 , 㚨⮹暨 天 1 ms 㛇 攻 VDD3 meet rising time
>1ms 0.1u_25V_X5R_02 1u_6.3V_X5R_02

1 2 J_RJ_1 PIN20 PIN20


LAN_MDIP0 12 13 LMX1+ *W CM2012F2S-161T03-short DLMX1+ 1 GND1
LAN_MDIN0 TD4+ MX4+ DA+ shield
11 14 LMX1- 4 3 L13 DLMX1- 2 GND2 D02_1107_Alex
LAN_MDIP1 TD4- MX4- DA- shield
9 16 LMX2+ 1 2 DLMX2+ 3
LAN_MDIN1 TD3+ MX3+ *W CM2012F2S-161T03-short DB+
8 17 LMX2- DLMX2- 6
TD3- MX3- DB-
4 3 L12 LAN_GND 0.2_06
1 2
LAN_MDIP2
LAN_MDIN2
LAN_MDIP3
LAN_MDIN3
6
5
3
TD2+
TD2-
TD1+
MX2+
MX2-
MX1+
19
20
22
LMX3+
LMX3-
LMX4+
4
1 2
*W CM2012F2S-161T03-short
3 L11

*W CM2012F2S-161T03-short
DLMX3+
DLMX3-
DLMX4+
4
5
7
DC+
DC-
DD+
LAN POART CARD_3V3 R430

6-14-0R23F-01B-1
0.2R_5%_06
VCC_CARD

2 TD1- MX1- 23 LMX4- DLMX4- 8


4 3 L10 DD-
10 15 NMCT_4 C10217-10839
40 mil 7 TCT4 MCT4 18 NMCT_3
4 TCT3 MCT3 21 NMCT_2 6-21-B40A0-008
1 TCT2 MCT2 24 NMCT_1
TCT1 MCT1
GST5009 LF
EMI ER4
*10mil_short
C24 㓦伖 T OP朊
A ER3 A
*10mil_short
0.1u_6.3V_X5R_02
R12 75_04 NMCT_R
R13 75_04 ER1
*10mil_short

ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
R14 75_04 4,23,24,31,32,34,37,40,41,45,47,48,49,50,51,54,55,57,58,59,60,61,62,65,74,77,78 VDD3
R15 75_04 㓦伖 B OT朊 2,24,29,42,44,49,50,52,53,56,59,60,61,72,73 3.3V
ER2
*10mil_short 8,9,23,24,27,29,30,31,32,33,34,35,36,39,40,41,44,45,47,49,50,54,61,74,77 3.3VS
C15 Title
1013 100PF 2KV 1206
[43] CARD READER/ LAN RTL8411B
modify ℙ
䓐䶂嶗
Size Document Number Rev

LAN_GND LAN_GND
A3 6-71-NH500-D02 D02

Date: W ednesday, December 05, 2018 Sheet 43 of 78


5 4 3 2 1

B - 44 Card Reader / LAN RTL8411B


Schematic Diagrams

HDD, Click TP, Audio, Hall Con.


5 4 3 2 1

FOR SUPPORT OPTANE project, SATA HDD≈


POWER 暣
GATEING 嶗 HDD CONNECT1 (MASTER)

change to SY6288E1AAC SATA_5VS 6-21-C4790-122


J_HDD1
(7.0mm HDD)
Gen3
S1
S2 JHDD_SATA_TXP4 C748 0.01u_50V_X7R_04
JHDD_SATA_TXN4 SATA_TXP4 33
D S3 C747 0.01u_50V_X7R_04 SATA_TXN4 33 D
PJ531 2 *OPEN-3mm S4
SATA_5VS S5 JHDD_SATA_RXN4 C746 0.01u_50V_X7R_04
5VS SATA_5VS JHDD_SATA_RXP4 SATA_RXN4 33
S6 C745 0.01u_50V_X7R_04 SATA_RXP4 33
2.5A U21 2.5A S7
5 1 3.3VS
IN OUT
C1217 2 P1
GND C1218 R324 P2
10u_6.3V_X5R_06 4 3 P3
EN OCB 0.1u_6.3V_X5R_02 *220_06 P4
SY6288E1AAC P5
6-02-62881-9C0 B Y ἧ䓐䘬廠↢暣 ⡻   婧㔜 , P6
3.3V R4893 4.7K_04 ὅ≇䌯 ( 旣ῤ& ⊭ 墅 ⣏ ⮷ ) P7
3A P8
39 SATA_PW R_EN P9 SATA_5VS

B.Schematic Diagrams
D02_Gary Q44 P10
P11 C743 C749 C735 C740
SUSB G P12
27,30,49 SUSB
*2SK3018S3 P13

0.1u_10V_X7R_04

*1u_6.3V_X5R_02

10u_6.3V_X5R_06

22u_6.3V_X5R_06
P14 R4949
RTD3 POWER P15
*0_04
AT22J36BAA207
D02_102518_Alex

D02A_1205_Alex
Sheet 44 of 73
C
㓦暣徜 嶗 枸䔁 ᶵᶲ
C HDD, Click TP,
ON
Audio, Hall Con.
L19
Tommy 0419FCM1005KF-121T03
.
J_FP1
30mil
C1168
1u_6.3V_X5R_02
3.3VS
FOR AUDIO BOARD
1
2 GND
3
4 5V
5 USB_PN10 32 J_AUD1
6 USB_PP10 32

GND1
D50 D51 1
1

FP225H-006S10M 2
3
*TEA10402V15A0

*TEA10402V15A0

4
6-20-94A40-004 5
6
7
2

8 5V
Raven HALL CHANGE FINGER 0731 9
10
PCB Footprint = fp225h-006xxxm 11
B 12 USB_PP2 32 B
13 USB_PN2 32
C1088
TP_VCC 14
USB3_RXP2 35 0.1u_10V_X7R_04

CLICK PAD R331

*0603_short
3.3VS
15
16
17
18
USB3_RXN2

USB3_TXN2
35

35
19 USB3_TXP2 35
C778 1u_6.3V_X5R_02 20
FP225H-008S11M 21 USB_PP6 32
fp225h-008gxxxm_L C773 0.1u_6.3V_X5R_02 22 USB_PN6 32
23
1 TP_CLK_CON 1 10 TP_CLK 24
2 TP_DATA_CON TP_DATA TP_CLK 47
2 9 25
3 TP_DATA 47
3 8 26
4 TP_I2C_CLK_CON 4 7 I2C_SCL_TP 27 SPDIFO 77
5 TP_I2C_DAT_CON I2C_SDA_TP I2C_SCL_TP 39 AUDG
5 6 28
PCB Footprint = FP201-040X1-0M

6 LID_SW #_L I2C_SDA_TP 39 SLEEVE_CON 77


29
7 TP_ATTN# D27 30
8 TP_ATTN# 31
1

*DT1140-04LP-7 31 HP_SENSE 77
J_TP1 TP_VCC 32 MIC_SENSE 77
D28 10K_04 R337 33 MIC1_L 77
3.3VS Raven modfiy 0629
*ESDPSA0402V12 34 MIC1_R 77
FP201H-040S10M

MAIN 6-20-94K00-006 35 HEADPHONE_L_DEPOP 77


36 HEADPHONE_R_DEPOP 77
2

R817 R818 R330 R332 C771 37


38
GND2

3.3VS 10K_04 10K_04 10K_04 10K_04 *10u_6.3V_X5R_06 39


TP_CLK 40 AUDG
A TP_DATA A
Raven modfiy AUDG 0716
I2C_SCL_TP
R336 I2C_SDA_TP _

10K_04 C770 C772


ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
C1208 C1207 AUDG modification 0508
D29 47p_25V_NPO_02 47p_25V_NPO_02 Biaggi
*47p_25V_NPO_02 *47p_25V_NPO_02
LID_SW #_L A C
LID_SW # 29,47,65 29,42,49,50,52,55,60,73 5V Title

RB751S-40C2
27,30,32,45,47,48,49,74,77,78
4,23,24,31,32,34,37,40,41,43,45,47,48,49,50,51,54,55,57,58,59,60,61,62,65,74,77,78
5VS
VDD3
[44]HDD,CLICK TP,AUDIO,HALL CON
2,24,29,42,49,50,52,53,56,59,60,61,72,73 3.3V Size Document Number Rev
8,9,23,24,27,29,30,31,32,33,34,35,36,39,40,41,43,45,47,49,50,54,61,74,77 3.3VS A3 SCHEMATIC1 6-71-NH500-D02 D02

Date: W ednesday, December 05, 2018 Sheet 44 of 78


5 4 3 2 1

HDD, Click TP, Audio, Hall Con. B - 45


Schematic Diagrams

LED, CCD, TPM, Power SW Con.


5 4 3 2 1

NGFF B & M KEY


LED ⤪PCIE SSD LED
L E D ≽ἄ㗪炻婳䓐㬌 䶂 嶗

佑⎴S
A
T A
WLAN ON
WLAN LED


婳EC 復
↢ầ S S D
PIN24
L E D ≽ἄ䘬㊯䣢 炻德 忶 A P忂䞍 B IOS ⛐ ⏲ 䞍EC   ↢ ≽ ἄ Windows 7
WLAN OFF ᶵṖ VDD_TPM R716 TPM 0_04 3.3VA
3.3VS Airplane ON Ṗ R735
R721 *0_04 VDD3
Windows 8
TC7SZ08FU *4.7K_04

5
D Airplane OFF ᶵṖ D
1
LED_HDD# M2M_SSD2_LED# 40 U41
4
2 TPM_GPIO 6 1
SATA_LED# 33 GPIO0 VDD 8 C1140 C1146
A C D25 R737 *4.7K_04 TPM_PP 7 VDD 22 VDD_TPM C1142
M2M_SSD1_LED# 41 PP VDD

3
U18 RB751S-40H 0.1u_6.3V_X5R_02 0.1u_6.3V_X5R_02 *1u_6.3V_X5R_02
6-52-55001-021 24,31,32 PLT_RST#
17 23 C1139 DEL R713
RST#
TPM VSS_3 TPM TPM
D02_1029_Alex 34 TPM_PIRQ# 18 3 0.1u_6.3V_X5R_02 D02_102518_Alex
PIRQ# NC_1 4
R725 TPM33_04 19 NC_2 5 TPM
31 SPI_SCLK_R SPI_CLK NC_3 10
R718 TPM0_04 20 NC_4 11
31 SPI0_CS2# SPI_CS# NC_5 12 DEL R740
R715 TPM33_04 21 NC_6 13 D02_102518_Alex
31 SPI_SI_R SPI_MOSI NC_7 VDD_TPM
14
R714 TPM33_04 24 NC_8 15
31 SPI_SO_R SPI_MISO NC_9 16 C1147
B.Schematic Diagrams

NC_A 25
NC_B 26 0.1u_6.3V_X5R_02
NC_C 27
VDD_TPM R717 *20K_04 2 NC_D 28 TPM
9 VSS_1 NC_E 29
32 VSS_2 NC_F 30
47 AIRPLAN_LED# AIRPLAN_LED# VSS_4 NC_G
R727 10K_04 33 31
GND NC_H
LED_BAT_CHG SLB9670VQ
47 LED_BAT_CHG TPM TPM_W

Sheet 45 of 73 C

47 LED_BAT_FULL
LED_BAT_FULL Raven Del 0820
TPM
C

LED, CCD, TPM, LED_ACIN

Power SW Con. 47 LED_ACIN

LED_PWR
Raven change 0731

47 LED_PWR

CCD+DMIC ⤪C C D _ 5 V 2 A⎗
M: G5243A ----
䓐ẍ ᶳ 㕁
6-02-05243-9C0
S: AP2821KTR-G1 6-02-02821-9C0
POWER SWITCH BOARD
3.3VS 3.3VS
U27 CCD_PWR
1A 1A 48 mil
4 1

C881

1u_6.3V_X5R_02
5

3
VIN
VIN
VOUT

2
C896

2.2u_6.3V_X5R_04
NHx0 LED BOARD C56

*0.01u_50V_X7R_04
C57

*0.01u_50V_X7R_04
B EN GND B

UP7553PMA5-25 5VS
47 CCD_EN

㕁嘇 䁢3A , ⤪ 䓐 2nd source㗪 天 㲐 シㅱ䓐
GND GND
J_LED2
LED_HDD#
EVTᶲ
ẞ炻 DVT⼴ 㓡 䁢 S H ORT 0616
12 AIRPLAN_LED# 1
USB_PN8_J 11 LED_BAT_FULL 2
4 L18 3
32 USB_PN8 10 LED_BAT_CHG 3 *AVL18S02015
USB_PP8_J USB_PN8_C 9 LED_PWR 4 D12 2 1 FP226H-004S10M
1 2 5
32 USB_PP8 USB_PP8_C 8 LED_ACIN
*WCM2012F2S-161T03-short 6 3.3VS 1
7 NC2 R46 *1K_04
MIC_DATA_R 6 7 2
L17 . FCM1005KF-121T03
77 MIC_DATA MIC_CLK_R 3.3VSMIC_DATA_L 5 8 NC1 M_BTN# 3
L16 . FCM1005KF-121T03 49 M_BTN#
77 MIC_CLK MIC_CLK_L 4 9 4
GND 10 J_SW1
3
10/5/2017 2 11 C54 C55
C895 C894 3.3VS
1 12
47p_25V_NPO_02 47p_25V_NPO_02 FP225H-012S10M 0.01u_50V_X7R_04 *0.01u_50V_X7R_04
J_CCD1
50207-01271-001
6-21-62D00-112
⤪A U D I O 3.3VS D02_1109_Alex
GND GND
SOURCE⶙ 㚱㬌 L C ( E M I
Solution)⇯ ⎗ᶵ≈
炻ᾉ嘇䚜㍍ ⇘ ⇘ CO N N E C T
EMC7
A A
0.01u_50V_X7R_04
D41
USB_PN8_J 5 6 USB_PN8_C
USB_PP8_J 4 USB_PP8_C EMI, Close to connector

ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
7
GND
3 8
MIC_DATA_R 2 9 MIC_DATA_L
MIC_CLK_R 1 10 MIC_CLK_L Title
29,42,44,49,50,52,55,60,73
27,30,32,44,47,48,49,74,77,78
5V
5VS
[45]LED,CCD,TPM,POWER SW CON.
*TVUDF1004AD0 4,23,24,31,32,34,37,40,41,43,47,48,49,50,51,54,55,57,58,59,60,61,62,65,74,77,78 VDD3 Size Document Number Rev
2,24,29,42,44,49,50,52,53,56,59,60,61,72,73
8,9,23,24,27,29,30,31,32,33,34,35,36,39,40,41,43,44,47,49,50,54,61,74,77
3.3V
3.3VS 4,31,32,33,34,37,39,50,55 3.3VA
Custom SCHEMATIC1 6-71-NH500-D02 D02

Date: Wednesday, December 05, 2018 Sheet 45 of 78


5 4 3 2 1

B - 46 LED, CCD, TPM, Power SW Con.


Schematic Diagrams

Audio Codec
5 4 3 2 1

AUDIO CODEC ALC293D  


  
L5 1

C577

C575
2 *HCB1005KF-121T20

0.1u_25V_X5R_04

0.1u_25V_X5R_04
     R209 0_04
HEADPHONE_R
HEADPHONE_L
AUDG AUDG
BEEP_R
CLOSE TO CODEC

2.2u_6.3V_X5R_04
PC D18
BEEP MIC1_VREFO_L
#$% !%

1u_6.3V_X5R_02

1u_6.3V_X5R_02
C578
FOR VOLUMN SLEEVE 5VS_AUD L6 5VS
R192 4.7K_04 BAT54CS3
R193 3.9K_04 BEEP 1 A ADJUST 0.1u_6.3V_X5R_02 AUDG HCB1005KF-121T20
47 KBC_BEEP BEEP_A
D C 3 R188 6.2K_1%_04 BEEP_C C631 1 2 D
2 A

R210
34 PCH_SPKR AUDG
*100p_25V_NPO_02 C626 2018/7/2

1
6-06-00543-021 R187 C579 C622 C625 C623 D48

C627

C624
34 C1164
4.7K_04 100p_25V_NPO_02 2.2u_6.3V_X5R_04

0_04
0.1u_6.3V_X5R_02 2.2u_6.3V_X5R_04 10u_6.3V_X5R_06
Pin27 Pin27

36

35

33

32

31

30

29

28

27

26

25
U15 *15KV/0.2PF CESD0201UC5VB-M
Moat

2
3.3VS 3.3VS

CBP

CPVEE

HPOUT-L

MIC-CAP

MIC1-VREFO

LINE1-R/SLEEVE

LINE1-L/RING2

AVDD1

AVSS1
CBN

HP-OUT-R

VREF
AUDG

C1163 C1160 AUDG


37
AVSS2 I2S_DIN
24 R762 
 !!"
   

0.1u_6.3V_X5R_02 0_06
4.7u_6.3V_X5R_04 38 23 LINE1-VREFO
HVDD(3.3V) LINE1-VREFO
C1165 2.2u_6.3V_X5R_04 39 22 C628 2.2u_6.3V_X5R_04
AVDD2 LDO2-CAP AUX mode/LINE1 JD AUDG
5/8 follow design common 1.5VS
AUDG AUDG R215 0_04 40 21 R214 100K_04
AVDD2 LDO1-CAP

ALC293D-CG
C1166 2.2u_6.3V_X5R_04
D02_102518_Alex_HDA 41 20 C629 4.7u_6.3V_X5R_04
5VS MIC1_R 44,77

B.Schematic Diagrams
PVDD1 MIC1-R
C1162 C1161 SPKOUTL+ 42 19 C630 4.7u_6.3V_X5R_04
SPK-OUT-L+ MIC1-L MIC1_L 44,77
3.3VS
㬌 䳬 䶂 嶗 㙓 㗪 䓐 ᶵ ᶲ ĭ 㓭⃰ ὅ䄏⺈⓮㊯䣢
㍍ ⛘ SPKOUTL- 43 18
SPK-OUT-L- I2S_LRCK
4.7u_6.3V_X5R_04 0.1u_6.3V_X5R_02
SPKOUTR- 44
QFN 6x6 17
SPK-OUT-R- I2S_DOUT 3.3VS
R224 
  
D17 0.1u_6.3V_X5R_02 C1159 SPKOUTR+ 45 16
R220 SPK-OUT-R+ I2S_SCLK
BAT54AS3 10K_04
HDA_RST# 0_04 2 46 15

GPIO1/DMIC-DATA12
5VS PVDD2 I2S_MCLK
A
3 R223 0_04 R761

GPIO0/DMIC-CLK
Sheet 46 of 73
1 C
47 14 100K_1%_04
D

47 KBC_MUTE# A 44 SPDIFO SPDIFO I2S_IN/I2S_OUT JD


DMIC-DATA34/GPIO2
CODEC_PD# 48

SDATA-OUT
Q31 13
EAPD+PD HP/MIC1 JD

LDO3-CAP
G

SDATA-IN
R225 100K_04 2SK3018S3

DVDD-IO
3.3VS

PCBEEP
RESET#
BIT-CLK
49

I2S OE
D

GND

DVDD
R218

SYNC
C1156 R216

Audio Codec
R217
Q30
HDA_RST# G BSS138 *0_04 200K_1%_04
C 100K_1%_04 C
S

10

11

12
Thermal Pad place 49 *0.1u_6.3V_X5R_02

3.3VS
HP_SENSE 44
BEEP_R
Via hole.
Grounding circuit for Combo Jack R221 220_04
MIC_SENSE 44
45 MIC_CLK
while system entry into S3 / S4 /S5 45 MIC_DATA
R219 0_04
3.3VS 3.3VS
HDA_RST# 34,77
VDD3 HDA_SYNC 34
C633 HDA_SDIN0 34
SLEEVE
10p_25V_NPO_02 C1158 C1157
R191 R190 HDA_SDOUT 34
HDA_BITCLK 34
2.2u_6.3V_X5R_04 0.1u_6.3V_X5R_02
3

D
100K_04 *100K_04
Q29B
5 G MTDK3S6R
S C1155 C632
4

2.2u_6.3V_X5R_04
6

D 22p_25V_NPO_02
Q29A LINE1-VREFO R213 2.2K_04
2 G MTDK3S6R AUDG
34,77 HDA_RST# S
1

SLEEVE R211 0_04 SLEEVE_CON


SLEEVE_CON 44

D49
A 1 4.7K_04 R763 MIC1_R
MIC1_VREFO_L 3 C MIC1_R 44,77
A 2 4.7K_04 R766 MIC1_L
MIC1_L 44,77

BAT54AS3

B B
R212 0_04

HEADPHONE_L

HEADPHONE_L_DEPOP
D02_1114_Alex HEADPHONE_L_DEPOP 44

HEADPHONE_R HEADPHONE_R_DEPOP
HEADPHONE_R_DEPOP 44

R208 0_04

Close to the CODEC

J_SPK1
2 1
6-19-31001-274
SPKOUTL+ R296 0_06 SPKOUTL+_L

C709
85204-0200N
C707
180p_50V_NPO_04 2 NC1
*1u_6.3V_X5R_02 1 NC2
J_SPKL1
SPKOUTL- R293 0_06 SPKOUTL-_L
6-20-43130-102
C706
A 6-19-31001-274 A
180p_50V_NPO_04

SPKOUTR+ R227 HCB1608KF-800T30 SPKOUTR+_R

85204-0200N
C636
C635 2 NC1
180p_50V_NPO_04
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
1 NC2
*1u_6.3V_X5R_02
J_SPKR1
SPKOUTR- SPKOUTR-_R
R226 HCB1608KF-800T30
Title
29,34,49,50,51,52,53,54,55,56,57,59,78 VIN
4,31,32,33,34,37,39,45,50,55 3.3VA
[77]AUDIO CODEC ALC293D RTD3
C634
4,23,24,31,32,34,37,40,41,43,45,47,48,49,50,51,54,55,57,58,59,60,61,62,65,74,78 VDD3 Size Document Number R ev
180p_50V_NPO_04 27,30,32,44,45,47,48,49,74,78 5VS R9.1
8,9,23,24,27,29,30,31,32,33,34,35,36,39,40,41,43,44,45,47,49,50,54,61,74 3.3VS
A2 SCHEMATIC1
6-71-NH500-D02
Date: Wednesday, December 05, 2018 Sheet 77 of 78
5 4 3 2 1

Audio Codec B - 47
Schematic Diagrams

KBC-ITE IT8587
5 4 3 2 1

KBC_AVDD L7 VDD3
HCB1005KF-121T20
VDD3 VDD3 PERKB-DET#_R R836 10K_04
. VDD3
C670 C678 C682 C691 KB-DET R257 100K_04
C671 SMC_BAT R245 1.5K_04
10u_6.3V_X5R_06 *0.1u_6.3V_X5R_02 0.1u_6.3V_X5R_02 0.1u_6.3V_X5R_02 SMD_BAT R249 1.5K_04
R277 0.1u_6.3V_X5R_02 BAT_DET
J_KB2 NH50 KB VBATT_BOOST#
R253 10K_1%_04
R260 10K_04
100K_04 C695 KB-SI0 4
D02_1114_Alex
KB-SI1 5
FOR 50 AC
C
KBC_WRESET# 0.1u_10V_X7R_04 KBC_AGND 24,47,54,57,58 SMD_BAT
KB-SI2 6 D21 A
3.3VS KB-SI3 8 BAV99 RECTIFIER

114
121
127
11

26
50
92

74
KB-SI4 11 C

3
C692 U17 J_KB1 NH70 KB KB-SI5 12 Gary_Add N870 White LED Keyboard AC
0.1u_10V_X7R_04 FOR 70 47,57 BAT_DET

VBAT
VSTBY
VSTBY
VSTBY
VSTBY
VSTBY
VSTBY
VCC

AVCC
D
KB-SI6 14 D23 A D
10 58 KB-SI0 4 KB-SI7 15
35LPC_AD0 LAD0 KSI0/STB# BAV99 RECTIFIER
9 59 KB-SI1 5
35LPC_AD1 LAD1 KSI1/AFD# C
8 60 KB-SI2 6 KB-SO0 1
35LPC_AD2 LAD2 KSI2/INIT# AC
7 61 KB-SI3 8 KB-SO1 2 24,47,54,57,58 SMC_BAT
35LPC_AD3 LAD3 KSI3/SLIN# D22 A
13 62 KB-SI4 11 KB-SO2 3
35 PCLK_KBC LPCCLK KSI4 BAV99 RECTIFIER
6 63 KB-SI5 12 KB-SO3 7 CPU_FANSEN C960
35 LPC_FRAME# LFRAME# KSI5 100p_25V_NPO_02
5 LPC K/B MATRIX 64 KB-SI6 14 KB-SO4 9 AC_IN#
35 SERIRQ SERIRQ KSI6 C694 *0.1u_10V_X7R_04
22 65 KB-SI7 15 KB-SO5 10 BAT_VOLT VDD3
32,40,41,43 BUF_PLT_RST# LPCRST#/WUI4/GPD2( PU ) KSI7 C672 1u_6.3V_X5R_02
KB-SO6 13 CPU_FAN C961 100p_25V_NPO_02
KBC_WRESET# 14 36 KB-SO0 1
WRST# KSO0/PD0 KB-SO7 16 C677 *5p_50V_NPO_04
37 KB-SO1 2 KB-SO8 17  
126 KSO1/PD1 38 KB-SO2 3
GA20/GPB5 KSO2/PD2 KB-SO9 18
4 39 KB-SO3 7 KB-SO10 19 EC_PECI
57 AC_IN# KBRST#/GPB6( PU ) KSO3/PD3 R272 33_04
16 40 KB-SO4 9 KB-SO11 20 H_PECI 4
45 LED_ACIN PWUREQ#/GPC7( PU ) KSO4/PD4
20 41 KB-SO5 10 KB-SO12 21
34 AC_PRESENT L80LLAT/GPE7( PU ) KSO5/PD5 42 KB-SO6 13 KB-SO13 22

R269

R271
23 KSO6/PD6 43 KB-SO7 16
35 SMI# ECSCI#/GPD3( PU ) KSO7/PD7 KB-SO14 23
15 44 KB-SO8 17
B.Schematic Diagrams

33 SCI# ECSMI#/GPD4( PU ) KSO8/ACK# KB-SO15 24


45 KB-SO9 18 KB-SO16 25

4.7K_04

4.7K_04
KSO9/BUSY 46 KB-SO10 19
DAC KSO10/PE KB-SO17 26
34 SUS_PWR_ACK#
R255 *10mil_short
KBC_MUTE#
76
77 GPJ0 KSO11/ERR#
51
52
KB-SO11 20
21 6-20-94AF0-124 6-20-94AF0-124
KB-SO12 SMC_VGA_THERM
77 KBC_MUTE# GPJ1 KSO12/SLCT FP226H-026S10M
78 53 KB-SO13 22
34 ME_WE DAC2/GPJ2 KSO13
79 54 KB-SO14 23 SMD_VGA_THERM
24,54,58,61 EC_GPIO DAC3/GPJ3 KSO14
R4904 *10mil_short 80 55 KB-SO15 24
24,35
23
DGPU_PWR_EN
dGPU_GPIO8_OVERT
R4905 *10mil_short 81 DAC4/GPJ4
DAC5/GPJ5
IT8587 KSO15 KB-SO16 25
26
D02_1029_Alex KB-SO17
BAT_DET ADC FLASH R265 10K_04
100 AUTO_LOAD_PWR

Sheet 47 of 73
66 FP226H-026S10M VDD3
47,57 BAT_DET BAT_VOLT ADC0/GPI0 FLFRAME#/GPG2
67 101 ALSPI_CE#_L R854 0_04 ALSPI_CE# 31
57 BAT_VOLT ADC1/GPI1 FLAD0/SCE# W/O TPM
R259 0_04 68 102 ALSPI_MSI_L R855 0_04
24,35
2
GC6_FB_EN_PCH
THERM_VOLT
69
70
ADC2/GPI2
ADC3/GPI3
FLAD1/SI
FLAD2/SO
103 ALSPI_MSO_L R856
104
0_04
ALSPI_MSI
ALSPI_MSO
31
31
W/O TPM
W/O TPM
3.3VS
Debug Port
KBC-ITE IT8587
57 TOTAL_CUR VBATT_BOOST# ADC4/GPI4 FLAD3/GPG6 AIRPLAN_LED# 45
71 105 ALSPI_SCLK_L R857 0_04 LIGHT_KB_DET#
23 VBATT_BOOST# LIGHT_KB_DET# ADC5/GPI5 FLCLK/SCK ALSPI_SCLK 31W/O TPM R261 10K_04
72 106
C 35 LIGHT_KB_DET# MODEL_ID ADC6/GPI6 ( PD )FLRST#/WUI7/GPG0/TM CCD_EN 45 C
73
R266 47_04 ADC7/GPI7
24,47,54,57,58 SMC_BAT GPIO Raven modfiy 0628 VGA_FAN OPTION (⎗
ẍ怠
㑯㗗⏎ 枸
䔁 )
R267 47_04 SMBUS 56 KB-SO16 C993 100p_25V_NPO_02
24,47,54,57,58 SMD_BAT ( PD )KSO16/GPC3 VGA_FANSEN C992 100p_25V_NPO_02
Raven DEL 0731 110 57 KB-SO17 VDD3
111 SMCLK0/GPB3
SMDAT0/GPB4
( PD )KSO17/GPC5 midification 0517 Biaggi DEBUG PORT
R268 *10mil_short 115 93
23,74 SMC_VGA_THERM SMCLK1/GPC1 ( PD )GPH0/ID0 PERKB_ID2#_R 74
R270 *10mil_short 116 94 3IN1 4
23,74 SMD_VGA_THERM EC_PECI SMDAT1/GPC2 ( PD )GPH1/ID1 SUSC# 34,50,52 41 3IN1
117 95 D02_1029_Alex 80CLK 3
SMCLK2/GPF6( PU ) ( PD )GPH2/ID2 BKL_EN 29 41 80CLK
118 96 2
23 d_GPIO9_ALERT_FAN SMDAT2/GPF7( PU ) ( PD )GPH3/ID3 97
LED_BAT_CHG 45 NET ℐ ⼑ 䘥 ⃱ 䃉 䘤 ⃱ 1
( PD )GPH4/ID4 LED_BAT_FULL 45
D02_1029_Alex PWM 98 LED_PWR 45
( PD )GPH5/ID5 LIGHT_KB_DET# H L H J_80DEBUG1
48 EC_PWM_PIN_24 24 99 85205-04001
PWM0/GPA0( PU ) ( PD )GPH6/ID6 SUSB# 29,32,34,42,49,50,52,55,62
25 107
77 KBC_BEEP CPU_FAN PWM1/GPA1( PU ) ( PD )GPG1/ID7 KB-DET L H H
midification 0517 Biaggi
28 PCB Footprint = 85205-0400M
29 PWM2/GPA2( PU )
74 PERKB_ID1#_R VGA_FAN PWM3/GPA3( PU ) EXT GPIO 80DEBUG1
30 82
PWM4/GPA4( PU ) ( PD )EGAD/GPE1 SUS_WARN# 34
31 83 KB-DET
48 EC_PWM_LEDKB_R PWM5/GPA5( PU ) ( PD )EGCS#/GPE2 RGBKB-DET# 48
32 84 R258 *10mil_short
48 EC_PWM_LEDKB_G PWM6/GPA6( PU ) ( PD )EGCLK/GPE3 CNVI_DET# 41
34
48 EC_PWM_LEDKB_B
D02_1029_Alex
PWM7/GPA7( PU )
WAKE UP
D02_1112_Alex

35
R754 10K_04 EC ROM
PS/2 ( PD )WUI5/GPE5 EC_RSMRST# 34
80CLK 85 17
PS2CLK0/GPF0( PU ) ( PD )LPCPD#/WUI6/GPE6 SB_KBCRST# 35
86
49,51 USB_CHARGE_EN PS2DAT0/GPF1( PU ) ALSPI_* = 1.5"~5.8" C1178 VDD3
3IN1 87 PWM/COUNTER
88 PS2CLK1/GPF2( PU ) 47 CPU_FANSEN 0.1u_6.3V_X5R_02
41 BT_EN PS2DAT1/GPF3( PU ) ( PD )TACH0/GPD6
89 48 VGA_FANSEN
44 TP_CLK PS2CLK2/GPF4( PU ) ( PD )TACH1/GPD7
44 TP_DATA
90
PS2DAT2/GPF5( PU )
midification 0517 Biaggi 1Mbit
( PD )TMRI0/WUI2/GPC4
120
PERKB-DET#_R 48,74 U45
TPM
124
125
WAKE UP ( PD )TMRI1/WUI3/GPC6 PM_PWROK 32 ALSPI_MSI_L R792 TPM 33_04 5 8
42,49,51,78 DD_ON PWRSW/GPE4( PU ) SI VDD
CIR R274 0_04 ALSPI_MSO_L R793 TPM 33_04
ALL_SYS_PWRGD 4,29,32,54 2 R789
18 119 R273 *0_04 SO
49 PWR_SW# RI1#/WUI0/GPD0( PU ) ( PD )CRX/GPC0 NB_ENAVDD 29,33 3.3K_1%_04
21 123 ALSPI_CE#_L R791 TPM 0_04
29,44,65 LID_SW# RI2#/WUI1/GPD1( PU ) ( PD )CTX/GPB2 LAN_WAKEUP# 31,34,43 1 3 FDIO2
ECṢ
⒉㬌 PIN暨姕 ⭂ 䁢 H igh CE# WP#
B
GP INTERRUPT LPC/WAKE UP ALSPI_SCLK_L R790 TPM 33_04 6 R788 TPM B
33 19 SCK
34 PWR_BTN# GINT/GPD5( PU ) ( PD )L80HLAT/GPE0 SWI# 33 3.3K_1%_04
112 4 7 FDIO3
( PD )RING#/PWRFAIL#/LPCRST#/GPB7 EC_CODEC_PD# VSS HOLD#
108
UART Raven change 0703 GD25D10BTIGR TPM
41 WLAN_PWR_EN RXD/GPB0( PU )
AVSS
CLOCK D02_1029_Alex PCB Footprint = M-SO8
109 2
4 H_PROCHOT_EC WLAN_EN 41
VSS
VSS
VSS
VSS
VSS
VSS
VSS

TXD/GPB1( PU ) CK32KE
CK32K
128
SLP_SUS# 41,50,55,78 TPM
VDD3 IT8587E/FX
R276 10K_04
1
12
27
49
91
113
122

75

KBC_AGND
R254 *10mil_short KBC_AGND
R251
10K_04

KBC_MUTE#
W/O CHARGER C693
6-03-08587-FX
0.1u_6.3V_X5R_02
VGA FAN CONTROL
R256
10K_04
㕟 &
  ≇ 傥 

" ' 㗪
 㚱       
㗪㰺 㚱
CPU FAN CONTROL 5VS VGA_FAN
J_FAN2
J_FAN2
VGA_FAN 1 4
2
CHARGER CPU_FAN C998 C997
3 1
5VS ὅℙ䓐䶂 嶗 ᾖ 㓡 *1u_6.3V_X5R_02 10u_6.3V_X5R_06 4
MODEL_ID RA RB Voltage J_FAN1
J_FAN1 85205-04001
_
NH50ED R250 NC 3.3V CPU_FAN 1 4 PCB Footprint = 85205-0400M
2 VGA_FANSEN
C986 C985
NH70ED NC R262 0V 3
1
*1u_6.3V_X5R_02 4 R523 4.7K_04
10u_6.3V_X5R_06 3.3VS
A
xxxxx 6.49K_1% 10K_1% 2V 85205-04001 6-20-41120-104 A
PCB Footprint = 85205-0400M
CPU_FANSEN
xxxxxx 12K_1% 10K_1% 1.5V 6-20-43130-104
R511 4.7K_04
3.3VS
VDD3
NH50ED
R250 RA 10K_04
MODEL_ID
R262 10K_04
29,34,49,50,51,52,53,54,55,56,57,59,78
27,30,32,44,45,48,49,74,77,78
VIN
5VS ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
NH70ED 4,23,24,31,32,34,37,40,41,43,45,48,49,50,51,54,55,57,58,59,60,61,62,65,74,77,78 VDD3 Title
RB 8,9,23,24,27,29,30,31,32,33,34,35,36,39,40,41,43,44,45,49,50,54,61,74,77 3.3VS [47] KBC-ITE IT8587
Size Document Number Rev

Custom SCHEMATIC1 6-71-NH500-D02 D02

Date: Wednesday, December 05, 2018 Sheet 47 of 78


5 4 3 2 1

B - 48
Schematic Diagrams

RGB KB Only
5 4 3 2 1

RGB KB Only N 8 5 ᶲẞ D02_102618_Alex_Common design

RGBKB_PWR VDD3
J_KBLED1
C719 4.7u_6.3V_X5R_04 R303
1 NH50_RGB
D *100K_04 D
2
3 R310 1K_04 NH50_RGB
4 NH50_RGB 1K_04
5 KBZONE_B R304
6 KBZONE_R NH50_RGB
7 KBZONE_G
8
FP225H-008S11M 2018/6/28
fp225h-008gxxxm_r
P/N = 6-20-94K30-108
NH50_RGB

2018/6/29

B.Schematic Diagrams
C
KB_5VS/3A N 8 7 ᶲẞ D02_102618_Alex_Common design C
5VS
RGBKB_PWR RGBKB_PWR
Sheet 48 of 73
J_KBLED2

1
PJ14
2 1
2
C697 4.7u_6.3V_X5R_04
NH70_RGB
RGB KB Only
OPEN_2mm 3 R280 1K_04
4 NH70_RGB 1K_04
KB-LED-RGB 5 KBZONE_B R281
5VS RGBKB_PWR 6 KBZONE_R NH70_RGB
7 KBZONE_G
2A S D 2A 47,74 PERKB-DET#_R
R4896 *1K_04 8
FP225H-008S11M 2018/6/28
R833 0_06 fp225h-008gxxxm_r
RGBKBSW_R KBZONE_R P/N = 6-20-94K30-108

D
C1244 R4897 Q82 R4899
G

1K_04 AO3415 4.7K_04 NH70_RGB


4.7u_6.3V_X5R_04 KB-LED-RGB KB-LED-RGB KB-LED-RGB
Q81 KB-LED-RGB
G MTNK8N3
47 EC_PWM_LEDKB_R
KB-LED-RGB KB-LED-RGB

S
2018/6/29
R834 0_06
RGBKBSW_G KBZONE_G

D
B B
R4898
2.7K_04
Q80 KB-LED-RGB
G MTNK8N3
KB-LED-RGB 47 EC_PWM_LEDKB_G
D02_102618_Alex_Common design KB-LED-RGB      

S
R835 0_06
RGBKBSW_B KBZONE_B
D

D
Q83 Q69 KB-LED-RGB
G 2SK3018S3 G MTNK8N3
47 EC_PWM_PIN_24 47 EC_PWM_LEDKB_B RGBKB-DET# 47
KB-LED-RGB
KB-LED-RGB
S

A A

ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Title
29,34,49,50,51,52,53,54,55,56,57,59,78 VIN [48] RGB KB
27,30,32,44,45,47,49,74,77,78 5VS
2,24,29,42,44,49,50,52,53,56,59,60,61,72,73 3.3V Size Document Number Rev
4,23,24,31,32,34,37,40,41,43,45,47,49,50,51,54,55,57,58,59,60,61,62,65,74,77,78
8,9,23,24,27,29,30,31,32,33,34,35,36,39,40,41,43,44,45,47,49,50,54,61,74,77
VDD3
3.3VS
SCHEMATIC1
Custom 6-71-NH500-D02 D02

Date: Wednesday, December 05, 2018 Sheet 48 of 78

5 4 3 2 1

RGB KB Only B - 49
Schematic Diagrams

5V, 5VS, 3.3V, 3.3VS


1 2 3 4 5

VDD3 EMI EMI


DD_ON# SUSB
VDD3

VIN
VIN VIN VIN

PR111 PR290
C1046 C1044 C1045
10K_04 100K_04 VIN VA VIN1
C1047
DD_ON# SUSB

0.1u_50V_X5R_04

0.1u_50V_X5R_04

0.1u_50V_X5R_04
DD_ON# 42,52 SUSB 27,30,44
C25 C28 C27

1000p_50V_X7R_04
D

D
PQ6 PQ19
PC271
0.1u_50V_X5R_04 0.1u_50V_X5R_04 0.1u_50V_X5R_04
A42,47,51,78 G 2SK3018S3 PC85 G 2SK3018S3 A
DD_ON 29,32,34,42,47,50,52,55,62 SUSB# *0.1u_6.3V_X5R_02

S
*0.1u_6.3V_X5R_02
PR110 PR289 Clost to P2808B0
100K_04 100K_04

VIN1
U4
R28 10K_04 1 8
VA VA VIN1
DDON_LATCH DD_ON
B.Schematic Diagrams

R29 1_1%_06 2 7 R26 100K_04


VIN VIN DD_ON_LATCH
R27 10K_04 3 6 R25 10K_04 VDD3
45 M_BTN# M_BTN# PWR_SW#
R44 *100K_04 4 5 R24 1K_1%_04
INSTANT-ON GND PW R_SW # 47
USB_CHARGE_EN R43 1K_1%_04 P2808B0
47,51 USB_CHARGE_EN

Sheet 49 of 73
VDD5 VDD5

5V, 5VS, 3.3V, B C1177 U44 G5016 C1176 B

0.1u_6.3V_X5R_02 1 6 0.1u_6.3V_X5R_02

3.3VS 5V 6A
2

13
IN1
IN1
IN2
IN2
7

8 6A
5VS
5V OUT1 OUT2 5VS
14 9
C1175 OUT1 OUT2 C1170
12 10
0.1u_6.3V_X5R_02 CT1 CT2 0.1u_6.3V_X5R_02

VBIAS
GND

GND
EN1

EN2
C1174 C1171
220p_50V_NPO_04 470p_50V_X7R_04
PR291 10K_04 VDD3_R 1 2 2 1 VDD3_R
VDD3

15

11

5
PJ46 *CV-40mil PJ45 *CV-40mil
R780 R779
SHORT 10K_04 10K_04 SHORT
DD_ON 1 2 DD_ON_EN SUSB#_EN 2 1 SUSB#
VDD5
PJ47 OPEN_1mm C1173 C1169 C1172 PJ44 OPEN_1mm
1u_6.3V_X5R_02
DD_ON_EN *0.1u_10V_X7R_04 *0.1u_10V_X7R_04
ON
SUSB#_EN 50
ON

C C

VDD3 VDD3
C722 U29 G5016 C737

0.1u_6.3V_X5R_02 1 6 0.1u_6.3V_X5R_02
2 IN1 IN2 7

3.3V 3.3V 6A 13
IN1

OUT1
IN2

OUT2
8 6A 3.3VS 3.3VS
14 9
C724 OUT1 OUT2 C734
12 10
CT1 CT2 R314
0.1u_6.3V_X5R_02 0.1u_6.3V_X5R_02

VBIAS
47_04

GND

GND
EN1

EN2
C729 C733
D02_1107_Alex 220p_50V_NPO_04 330p_50V_NPO_04

15

11

5
Q39

D
2SK3018S3
R317
G SUSB
10K_04
DD_ON_EN R321 10K_04 SUSB#_EN

S
VDD3
C727 C730 C732
1u_6.3V_X5R_02
0.22u_10V_X5R_02 *0.1u_10V_X7R_04

D D

51 VIN1
57 VA
29,34,50,51,52,53,54,55,56,57,59,78
6,8,9,34,50,52
VIN
VDDQ ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
42,51 VDD5 Title
4,23,24,31,32,34,37,40,41,43,45,47,48,50,51,54,55,57,58,59,60,61,62,65,74,77,78
29,42,44,50,52,55,60,73
VDD3
5V
[49] 5V,5VS,3.3V,3.3VS
27,30,32,44,45,47,48,74,77,78 5VS Size Document Number Rev
2,24,29,42,44,50,52,53,56,59,60,61,72,73
8,9,23,24,27,29,30,31,32,33,34,35,36,39,40,41,43,44,45,47,50,54,61,74,77
3.3V
3.3VS A3 SCHEMATIC1 6-71-NH500-D02 D02

Date: W ednesday, December 05, 2018 Sheet 49 of 78


1 2 3 4 5

B - 50 5V, 5VS, 3.3V, 3.3VS


Schematic Diagrams

VDD1.05V, VCCIO
1 2 3 4 5

VDD3

PR296
VDD1.05
VIN
47K_1%_04
1V/8A
2 9

10u_25V_X5R_08

10u_25V_X5R_08
3 IN PG

0.1u_25V_X7R_06
IN
4 1 PR300 10A

PC276

PC279

PC274
0_04
5 IN BS V1.0A
PC278 0.1u_16V_X7R_04 PL23 VDD1.05
IN BCIHP0730-1R0M PJ30
10 6 1 2 1 2
12 NC LX 19 PCB Footprint = BCIHP0735A
VTT_SELECT VTT VR Output Voltages NC PU18 LX 20 OPEN_8mm
low 1.1 V JW5068AUQFNF LX

PC273

PC272

PC282

PC280
PR297

22u_6.3V_X6S_08

22u_6.3V_X6S_08

22u_6.3V_X6S_08

22u_6.3V_X6S_08
A high (V1.1S_VTT) 1.05 V VDD3
PR295 100K_04
PJ50
1 2
*CV-40mil
11 qfn20-3x3mmc
EN 6-02-05068-4Q0 14
100_04 6+257 A
VDD3 FB
13
1 2 ILMT 17
41,47,50,55,78 SLP_SUS# VCC
PJ51 1mm 15
20180502 Follow common design BYP 16 PR293 22.6K_1%_04
PR299 NC
6+257

GND

GND

GND

PAD
*100K_04
1 2 PR254
55 1.8VA_PGD
PJ52 *OPEN_40mil PR253 *1K_1%_04 PC283 PJ48 1mm

18

21
PC277 30K_1%_04 *330p_50V_NPO_04 1 2
VCCMPHY_SENSE 37
PC275 PC281
*0.01u_25V_X7R_04 4.7u_6.3V_X6S_06 4.7u_6.3V_X6S_06
PR298
*100K_04
Floating O.C.P 12A PJ49 1mm
6+257
1 2
VSSMPHY_SENSE 37

PR294 6+257

B.Schematic Diagrams
100_04

PR220
3.3_06
Sheet 50 of 73
B
39,55 GPP_J1
PR219
0_04

PC189 VCCIO
B VDD1.05V, VCCIO
PU16 0.22u_16V_X7R_06

9
PL14 SHORT VCCIO
6A

LP#

MODE

BST
BCIHP-0735-0R68M-NL PC61 PC59 PC60 PC58 PC55 PJ8 *6mm
PC39 PC38 PC37 1 8 VCCIO_R 1 2
VIN VIN SW

*330U_2V_D2_D

22u_6.3V_X5R_06

22u_6.3V_X5R_06

22u_6.3V_X5R_06
PCB Footprint = BCIHP0735A

10u_25V_X5R_08

10u_25V_X5R_08

0.1u_25V_X7R_06
+ PC54

0.1u_10V_X7R_04

0.1u_10V_X7R_04
12 PR74
NB681GD-Z VOUT 100_04
GND
PR223 0_04 5 SHORT
EN PJ5 *1mm
VDD3 1 2
VCCIO_SENSE 6
PC188 PART NUMBER !LPM C1 C0 VOUT (V)
*0.1u_10V_X7R_04 PC56 PR75
*0.01u_50V_X7R_04 100_1%_04 PJ6 *1mm
PU2 SHORT 3.3VS 1 2
VSSIO_SENSE 6
0 X X 0(LPM)
5

TC7SZ08FU 2
1
PJ7 PJ26 PR224 PGND 1 0 0 0.85V
52 DDR 1.35V_PWRGD 100K_04
4 2 1 2 1 VCCIOGND
2 VDD3 VCCIO 1 0 1 0.875V
29,32,34,42,47,49,52,55,62 SUSB# OPEN C1_VCCIO_VR PR62
1mm *CV-40mil 3
*0_04 PR78 C1 11 0_04 1 1 0 0.95V
34,54 SLP_S0#
3

AGND

C0_VCCIO_VR 4 1 1 1 0.975V
C0 PR77 PR76

3V3
PG
0_04 *0_04
VCCIOGND
13

10
3.3V 3.3V 10K_04 PR68 C1_VCCIO_VR

PR63
10K_04 PR66 C0_VCCIO_VR
5.1_1%_04

C PR64 C
10K_04
PC49 PR67 PR65
20K_04 20K_04
32 VCCIO_PWRGD 1u_6.3V_X5R_04

VCCIOGND VCCIOGND

SHORT
1.05V VCCSFR_OC 3.3VA
VDD1.05
VCCST 1

PJ36
2

OPEN_1mm
1.05V_VCCST
VDDQ VDD3

U38
1.05V_VCCST C1083

C1090

C1089
10u_6.3V_X5R_06

10u_6.3V_X5R_06
*1u_6.3V_X5R_02
2 4 2A C1062 C1064 C1063
C1029 C1099 VIN VOUT
10u_6.3V_X5R_06
*1u_6.3V_X5R_02

*10u_6.3V_X5R_06

C1086 G5016 U37


1u_6.3V_X5R_02

*10u_6.3V_X5R_06

*0.1u_10V_X7R_04

VDD3 R605 6 1
SHORT 7 IN2 IN1 2 SHORT
*100_04 IN2 IN1

VCCSFR_OC
2 1 1A 8
OUT2 OUT1
13 3A 1 2
3.3VA
R179 9 14
OPEN_1mm PJ35 C1068 OUT2 OUT1 C1081 PJ37 OPEN_3mm
D

*100K_04 Q50 10 12
CT2 CT1
10u_6.3V_X5R_06

220p_50V_NPO_04

VBIAS

10u_6.3V_X5R_06
R609 G C1073 C1076 NOTE:
GND

GND
EN2

EN1

0_04 *2SK3018S3 VCCSFR_OC 6


3.3VA Ton need <65us
S

VCCST_EN
220p_50V_NPO_04

6 5 R591 VDDQ 6,8,9,34,52


5V
D

34,47,52 SUSC# ON VBIAS M5938 TURON-ON TIME=60us 3.3VA 4,31,32,33,34,37,39,45,55


Q27
5

11

15

*100_04 R603 VDD1.05 36,37,55


VCCST_EN G VCCIO 2,6
D VDD3 4,23,24,31,32,34,37,40,41,43,45,47,48,49,51,54,55,57,58,59,60,61,62,65,74,77,78 D
*0.1u_10V_X7R_04C1085

*2SK3018S3 100_04 VDD3


S

VDD3 R596 0_04 VIN 29,34,49,51,52,53,54,55,56,57,59,78


49 SUSB#_EN VDD5 42,49,51
C1087 R595 *0_04 1.05V_VCCST 4,6,33,54
55 VCCSTG_EN VREG5 51,55
*0.1u_10V_X7R_04 C1071

R588
0.1u_10V_X7R_04

R589 5V 29,42,44,49,52,55,60,73
D

VDD3 3.3VA_ON 3.3V 2,24,29,42,44,49,52,53,56,59,60,61,72,73


Q61 100K_04
SLP_SUS# 41,47,50,55,78 3.3VS 8,9,23,24,27,29,30,31,32,33,34,35,36,39,40,41,43,44,45,47,49,54,61,74,77
*100K_04 C1082 10K_04 R600
D

G 1u_6.3V_X5R_02 Q59
*2SK3018S3
S

1 3 G
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
C1078
GND NC 2SK3018S3
D

D
S

Q62 *0.1u_10V_X7R_04 Q60


FA7609A6 Title
SUSB#_EN G G 3.3VA_ON
*2SK3018S3 2SK3018S3 [50] VDD1.05V,VCCIO,3.3VA,VCCST
S

Size Document Number R ev


A2 SCHEMATIC1 6-71-NH500-D02 D02

Date: Wednesday, December 05, 2018 Sheet 50 of 78


1 2 3 4 5

VDD1.05V, VCCIO B - 51
Schematic Diagrams

VDD3, VDD5
5 4 3 2 1

PR92 D02_1115_Power PR93

34.8K_1%_04 34.8K_1%_04

EN_5V
PC72
D VIN D
1000p_50V_X7R_04

20
2.5A

2
PU23

2.5A VREG3

EN2

VFB2

CS2

CS1

VFB1

EN1
VIN PC267 PC268 PC269

1
PC261 PC270

0.1u_25V_X7R_06

4.7u_25V_X5R_08

*4.7u_25V_X5R_08
PC260 PC259 PC258 14 + +

VDD3 VO1

*EEEFZ1E101P

*EEEFZ1E101P
*4.7u_25V_X5R_08

4.7u_25V_X5R_08

0.1u_25V_X7R_06
PC74

2
1u_6.3V_X5R_04 3 7
VREG3 PGOOD
PC264 PC263
PR286
0.1u_10V_X7R_04
0_06 9
VBST2 VBST1
17 PR285 0_06
VDD5

4
3
2

2
3
4
B.Schematic Diagrams

0.1u_10V_X7R_04
1 PR288 0_06 10
DRVH2 DRVH1
16 PR287 0_06 1 SHORT
VDD3
SHORT SYS3V PL21 PL22 SYS5V
PJ43
VDD5

2
PJ42
1
14A BCIHP0730-4R7M
2 1
9
8 18
9 BCIHP0730-2R2M
2 1
8A 1 2
8 SW2 SW1 8
5mm PC77 PC257 *5mm
R1

C
+

PC262
11 15 EMC5 PC266

GND PAD
C
DRVL2 DRVL1

0.1u_10V_X7R_04

220u_6.3V_6.3*4.4

220u_6.3V_6.3*4.4
PD9 PD8 1000p_50V_X7R_04 PR95

7
6
5

5
6
7
R1

VREG5
Sheet 51 of 73 +

VCLK
PC76 30K_1%_06 PC75

VIN
PR283 PQ17 PQ18 *1000p_50V_X7R_04 0.1u_10V_X7R_04

CSOD140BSH
*100p_50V_NPO_04
14K_1%_06 AON6992 AON6992 for EMI

CSOD140BSH

A
EMR2

VDD3, VDD5

21

12

13

19
A
5.1_06
C TPS51275B-1RUKR R2 C
R2 PR96
PR94 PR284 19.1K_1%_06
200K_04
20K_1%_06
D03 Raven modfiy 0417
VDD5_LDO5
PR91
Vout=2*(1+R1/R2)
Vout=2*(1+R1/R2)
=2*(1+14K/20K) VIN1 VREG5

=3.4V PD7
PC73
PR89 0_06 =2*(1+30K/19.1K)
2.2_06
VIN C A
PC265 1u_6.3V_X5R_04
=5.1927
4.7u_25V_X5R_08
RB751S-40H

VREG5
Qpxfs! po! WEE40WEE6! QXN

R237
VREG5 S478-S744! Opu! Tuvgg...Wqsp-! BD! JO! WEE4-WEE6! Bmxbzt! PO/
10K_04

EN_3V5V EN_5V
S478! Opu! Tuvgg! -! S744! Tuvgg....Opo.Wqsp-! BD! JO! WEE4! Bmxbzt! PO/
B R236 B
6 R240
10K_04 D *10mil_short
Q35A
DD_ON_EN_VDD 2 G
Q35B 3 S MTDK3S6R
MTDK3S6R D 1
1

5 G PJ10 R243
42,47,49,78 DD_ON S *CV-40mil
4 100K_04
2
D

G CV Test
47,49 USB_CHARGE_EN
Q34
S

2SK3018S3

A A

4,23,24,31,32,34,37,40,41,43,45,47,48,49,50,54,55,57,58,59,60,61,62,65,74,77,78
42,49
VDD3
VDD5 ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
49 VIN1
Title
29,34,49,50,52,53,54,55,56,57,59,78
55
VIN
VREG5 [51] VDD3,VDD5
Size Document Number Rev
A3 SCHEMATIC1 6-71-NH500-D02 D02

Date: W ednesday, December 05, 2018 Sheet 51 of 78


5 4 3 2 1

B - 52 VDD3, VDD5
Schematic Diagrams

DDR 1.2V / 0.6VS, 2.5V


5 4 3 2 1

DDR4 5V A
PD10
C 2A VIN

1.2V/0.6VS VDDQ_R
PU3
G5616BRZ1U RB0540S2
PC248 PC252

4.7u_25V_X7R_08

4.7u_25V_X7R_08
PC246

VTT_MEM(0.6V)

0.1u_25V_X7R_06
SHORT
PC255
19
VLDOIN VBST
18
PC81
1.2V
10u_6.3V_X5R_06 0.1u_25V_X7R_06
EMR4
13A

2
3
4
D
VTT_MEM
2 1 2A 20
VTT DRVH
17
1 PL20
VDDQ_R
SHORT D
0_06
PJ11 OPEN_2mm BCIHP0730-1R0M PJ41 *6mm
1 16 9 1 2 1 2
PC79 VTTGND LL VDDQ
PR99 PCB Footprint = BCIHP0735A
*15mil_short 8
22u_6.3V_X5R_06 2 15 EMC6 PC254
VTTSNS DRVL ERM1 0_06
+

C
PD11 CSOD140BSH
PC80

5
6
7
3 14 220p_50V_NPO_04 390uF_2.5V_10m_6.3*6 0.1u_10V_X7R_04
GND PGND PQ16
AON6992 EMR3
PR102 560K_1%_04 9 13 PR103 4.7K_1%_04 5V
VIN

A
TON CS
PR104
12
PC78 0.1u_10V_X7R_04 4 PVCC5 11 5.1_06
VTTREF VCC5

B.Schematic Diagrams
2.2_1%_06
10 PC256 PC82
PGOOD 3.3V

1u_6.3V_X6S_04

1u_6.3V_X6S_04
5 8
VDDQSNS S5 PR98
R294 *15mil_short
6 7 10K_04
VDDQSET S3
Sheet 52 of 73

GND
VDDQSET
R290 *10mil_short
DDR 1.35V_PW RGD 50

DDR 1.2V / 0.6VS,

21
C C

PR100 8.06K_1%_06 PR108 5.1K_1%_04 2.5V


PC84 *100p_50V_NPO_04
R283 47K_04

D
5V

D
Q42 Q40
R282 10K_04 R316 100K_04 G 2SK3018S3 *2SK3018S3
5V ⮔⹎≈⣏ 䁢 8m il G

S
D

S
1
Q38 C700

D
R297 10K_04 G PJ16
5V
2SK3018S3 *0.1u_6.3V_X5R_02 Q43 *CV-40mil C701
S
1

G CV Test
34,47,50,52 SUSC#

2
PJ12 2SK3018S3
C

S
*CV-40mil *0.22u_10V_X5R_02
42,49 DD_ON#
R292 *10K_04 B Q37 CV Test
29,32,34,42,47,49,50,55,62 SUSB#
2

R295 1K_04 MMBT3904H


4 DDR_VTT_PG_CTRL
E

C704

0.01u_16V_X7R_04 暣⡻ 堐
ON DDR GPIO OUTPUT VOLTAGE SELECT
B GPIO DDR Vout B

Lo 1.2V
Hi 1.35V

5V D02_1106_Alex
Modify, Ivy 03/01
DEL R1058

Layout trace 2A after jumper R743


10_04
5V

3.3V
PC250 2.5V 1
U42
8 VDDQSET
3A 3
PU22
4
1u_6.3V_X5R_04
2.5V
2
3
VCC
BUS_SEL
OUT
NC
7
6 C1141

PC249 PC245 PR280 47K_04 2.5V_PG 1


VIN VCNTL
6

月 P I N4 儛 3A C1145
R738 R1 4 GND
SDA
NC
SCL
5 *1u_6.3V X5R_04
POK VOUT 1u_6.3V_X5R_02 10K_04 UP1804AMA8
10u_6.3V_X5R_06 0.1u_10V_X7R_04 5 PC253 R720 *10mil_short SMB_CLK 32,34
2 NC PR282 PC247 PC251
EN *10u_6.3V_X5R_06 R719 *10mil_short SMB_DATA 32,34
8 7 Ra 21.5K_1%_04 82p_25V_NPO_02
SHORT 9 GND VFB 22u_6.3V_X5R_06
R744 D02_1112_Alex
1 2 GND R2
34,47,50,52 SUSC# *0_04
A G9661-25ADJF11U A
PJ38 OPEN_1mm

PR281
R741 10K_04 1 2 Rb Vout = 0.8V ( 1 + Ra / Rb )
3.3V 8,9 2.5V
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
10K_1%_04
10,22,60 PEX_VDD
PJ39 *CV-40mil C1144
8,9 VTT_MEM
0.1u_6.3V_X7R_02
2.52V = 0.8V ( 1 + 21.5/ 10 ) 29,42,44,49,50,55,60,73 5V Title
For CV test 29,34,49,50,51,53,54,55,56,57,59,78 VIN
[52] DDR 1.2V/0.6VS,2.5V
6,8,9,34,50 VDDQ
D02_1107_Alex 2,24,29,42,44,49,50,53,56,59,60,61,72,73 3.3V Size Document Number Rev
27,30,32,44,45,47,48,49,74,77,78
8,9,23,24,27,29,30,31,32,33,34,35,36,39,40,41,43,44,45,47,49,50,54,61,74,77
5VS
3.3VS A3 SCHEMATIC1 6-71-NH500-D02 D02
4,23,24,31,32,34,37,40,41,43,45,47,48,49,50,51,54,55,57,58,59,60,61,62,65,74,77,78 VDD3 Date: W ednesday, December 05, 2018 Sheet 52 of 78
5 4 3 2 1

DDR 1.2V / 0.6VS, 2.5V B - 53


Schematic Diagrams

VCore Output Stage


5 4 3 2 1

VCORE OUTPUT STAGE VIN VCORE 4Phase


5.5A Co-lay
3.3V PC173 PC150 PC137
PC136

1u_25V_X7R_06

10u_25V_X6S_08

10u_25V_X6S_08
PU11 MP86941GQVT-Z

*25TQC15MYFB
+
20 1
PC149 VCC VIN1 14
D D
1u_6.3V_X6S_04 VIN2
19 21 BST_PWM1
AGND BST VIN

54 VRACPU_PWM1 PR193 0_04 15 2 PC172


PWM SW1 3 1u_16V_X7R_06 PL10
PR194 0_04 17 SW2 4 SW_PWM1 2 1
53,54,56 VRA_VTEMP VTEP/FLT SW3
CMME063T-R15MS0R907
16 13 C1264 C1265
53,54,56 VRA_STB SYNC PGND9 12

2.2_06

0.01u_50V_X7R_04

0.01u_50V_X7R_04
PGND8 D02_1115_EMI
11 DIPLF! DNNF174U.S26NT1S:18

PR200
PGND1
PGND2
PGND3
PGND4
PGND5
18 PGND7 10
54 VRACPU_CS1 CS PGND6 Jsnt>49B! Jtbu>56B! EDS>1/:1nS

5
6
7
8
9
PC151

2200p_50V_X7R_04
B.Schematic Diagrams

VIN
Co-lay
5.5A
PC175 PC138 PC153 PC139

1u_25V_X7R_06

10u_25V_X6S_08

10u_25V_X6S_08

*25TQC15MYFB
+

3.3V

PU12 MP86941GQVT-Z

Sheet 53 of 73 PC152
1u_6.3V_X6S_04
20

19
VCC VIN1
VIN2
1
14

21 BST_PWM2
AGND BST

VCore Output
VCORE

C
54 VRACPU_PWM2
PR39

PR40
0_04

0_04
15

17
PWM SW1
SW2
2
3
4 SW_PWM2
PC174
1u_16V_X7R_06
2
PL11
1
128A C

53,54,56 VRA_VTEMP VTEP/FLT SW3


CMME063T-R15MS0R907

Stage 53,54,56 VRA_STB


16
SYNC PGND9
13
12 DIPLF! DNNF174U.S26NT1S:18

2.2_06
PGND8 11

PR201
+ PC286 + PC285 + PC57 + PC53

PGND1
PGND2
PGND3
PGND4
PGND5
18 PGND7 10 Jsnt>49B! Jtbu>56B! EDS>1/:1nS
54 VRACPU_CS2 CS PGND6
330U_2V_D2_D 330U_2V_D2_D 330U_2V_D2_D 330U_2V_D2_D

5
6
7
8
9
PC176

2200p_50V_X7R_04

D02_102518_Power

VIN

5.5A Co-lay

3.3V PC106 PC178 PC141 PC155


PC140

*EEEFZ1E101P

1u_25V_X7R_06

10u_25V_X6S_08

10u_25V_X6S_08
PU13 MP86941GQVT-Z D02_1115_Power +

*25TQC15MYFB
+
20 1
PC154 VCC VIN1 14
1u_6.3V_X6S_04 VIN2
19 21 BST_PWM3
AGND BST
B B

54 VRACPU_PWM3 PR37 0_04 15 2 PC177


PWM SW1 3 1u_16V_X7R_06 PL12
PR38 0_04 17 SW2 4 SW_PWM3 2 1
53,54,56 VRA_VTEMP VTEP/FLT SW3
CMME063T-R15MS0R907
16 13 C374 C459 C461 C941 C378 C940
53,54,56 VRA_STB SYNC PGND9 5,53,54 VCORE
12 DIPLF! DNNF174U.S26NT1S:18

2.2_06
PGND8 11

PR202

22u_4V_X6S_06
PGND1
PGND2
PGND3
PGND4
PGND5

22u_6.3V_X6S_08

22u_6.3V_X6S_08

22u_6.3V_X6S_08

22u_6.3V_X6S_08

22u_6.3V_X6S_06
18 PGND7 10 Jsnt>49B! Jtbu>56B! EDS>1/:1nS
54 VRACPU_CS3 CS PGND6
5
6
7
8
9

PC156

2200p_50V_X7R_04

5,53,54 VCORE C138 C137 C939 C462 C133 C53


VIN
Co-lay
5.5A

*22u_4V_X6S_06

*22u_4V_X6S_06

*22u_4V_X6S_06

*22u_4V_X6S_06

PSLB30E227M

PSLB30E227M
+ +
PC180 PC158 PC143 PC142

*1u_25V_X7R_06

*10uF_25V_X6S_08

*10uF_25V_X6S_08

*25TQC15MYFB
+

3.3V

PU14 *MP86941-GLT-Z

20 1
PC157 VCC VIN1 14
1u_6.3V_X6S_04 VIN2
19 21 BST_PWM4
AGND BST

PR195 0_04 15 2 PC179


54 VRACPU_PWM4 PWM SW1 3 1u_16V_X7R_06 PL13
PR36 0_04 17 SW2 4 SW_PWM4 2 1
53,54,56 VRA_VTEMP VTEP/FLT SW3
A
*CMME063T-R15MS0R907 A
16 13
53,54,56 VRA_STB SYNC PGND9 12 DIPLF! DNNF174U.S26NT1S:18
2.2_06

PGND8 11
PR203
PGND1
PGND2
PGND3
PGND4
PGND5

18 PGND7 10 Jsnt>49B! Jtbu>56B! EDS>1/:1nS


54 VRACPU_CS4 CS PGND6
5
6
7
8
9

PC159

2200p_50V_X7R_04

ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Title
[53] VCORE OUTPUT STAGE
Size Document Number R ev

2,24,29,42,44,49,50,52,56,59,60,61,72,73 3.3V
A2 SCHEMATIC1 6-71-NH500-D02 D02

29,34,49,50,51,52,54,55,56,57,59,78 VIN Date: Wednesday, December 05, 2018 Sheet 53 of 78


5 4 3 2 1

B - 54 VCore Output Stage


Schematic Diagrams

VCC_Core & VCCGT


5 4 3 2 1

VIN

PR42
VDD3
VRACPU_PWM1
VRACPU_PWM1 53
VR_VDD18
VR_EN VRACPU_PWM2

PR199
PR71 10K_04 2 1
VDD3 VRACPU_PWM2 53
PJ4 *CV-40mil VRACPU_PWM3
PC41 0.1u_16V_X7R_04 VRACPU_PWM3 53
4,29,32,47 ALL_SYS_PWRGD VRACPU_PWM4

2M_1%_04 PR43
PR311 20K_04 1 2 GND_SIGNAL
D02_1102_Alex VRACPU_PWM4 53

PC52

4.7_1%_06
D PJ3 OPEN_4mil D
D02_1102_Alex VRAGT_PWM1
6+257 VRAGT_PWM1 56
VRASA_PWM1
VRASA_PWM1 56

PC31

1u_16V_X7R_06

PC147
VRACPU_VINSEN
VRA_STB

133K_1%_06

0.01u_50V_X7R_04

4.7u_6.3V_X5R_04
VDD3
VRA_STB 53,56
1.05V_VCCST
VRACPU_CS1
VRACPU_CS1 53
VRACPU_CS2
VRACPU_CS2 53
GND_SIGNAL VRACPU_CS3
VRACPU_CS3 53
GND_SIGNAL VRACPU_CS4

B.Schematic Diagrams
VRACPU_CS4 53

PR213

PR209

PR207
PR215 PR217 PR222 GND_SIGNAL

PC51 *10K_1%_04 *10K_1%_04 10K_1%_04 VRAGT_CS1

49

47

26

44

43

42

41

40

39

38
VRAGT_CS1 56
0.1u_16V_X7R_04 VRASA_CS1

VDD18

VDD33

PWM1

PWM2

PWM3

PWM4

PWM5

PWM6
AGND

VIN_SEN
*1K_1%_04 VRASA_CS1 56

100_04

45.3_1%_04
37
EN 34
PR221 *0_04 35 STB
34,50 SLP_S0# SLP_S0# 5 VRACPU_CSUMA
PR177 1.5K_1%_04
24,47,57,58 SMC_BAT PR218 0_04 SMC_BAT_VR 33 CS1
SCL_P

Sheet 54 of 73
GND_SIGNAL 4 PR178 1.5K_1%_04
24,47,57,58 SMD_BAT PR216 0_04 SMD_BAT_VR 32 CS2
VR_VDD18 4 H_PROCHOT# SDA_P 3 PR179 1.5K_1%_04
PR214 *100_1%_04 VR_VRHOT# 31 CS3
VRHOT# 2 PR180 *1.5K_1%_04
32 VCORE_PG PR211 10K_1%_04 PR212 0_04 VR_VRRDY 30 CS4 PR292 0_04

VCC_Core &
3.3VS VRRDY VRAGT_CSUMB
1 PR181 1.5K_1%_04
4 H_CPU_SVIDALRT# PR210 0_04 VR_ALT# 29 CS5 GND_SIGNAL
PR198 ALT# 48 PR182 1.5K_1%_04 VRASA_CSUMC
4 H_CPU_SVIDDAT PR208 10_1%_04 VR_DSIO 28 CS6
3.32K_1%_04 SDIO VRACPU_VDIFFPR176
PU15 6 1.47K_1%_04
VR_SCLK VDIFFA

VCCGT
C D02_102518_Power 4 H_CPU_SVIDCLK PR206 49.9_1%_04 27 C
SCLK MP2979AGQKT-0020-Z
ADDRP 25
ADDR_P 7 VRACPU_VFB PR175 *0_04 PC135 *470p_50V_X7R_04
PSYS PR192 0_04 46 VFBA
57 PSYS PSYS
D02_1030_Power PR174 *100_04 VCORE GND_SIGNAL
PR191 10K_1%_04 VRACPU_PE 36 8 VRACPU_VOSEN VCCSENSE_J PJ24 1 2 1mm VCC_VCORE_SENSE 5
PR205 PE VOSENA
9 VRACPU_VORTN VSSSENSE_J PJ23 1 2 1mm VSS_VCORE_SENSE 5
1.47K_1%_04 Psys setting base on charger spec:
GND_SIGNAL
PC148 0.01u_50V_X7R_04
VRACPU_IREF VORTNA
PR197 61.9K_1%_04 24 PR173 *100_04
1. 1uA/W information IREF 10 VRAGT_VDIFF PR172 2.1K_1%_04
2. Pmax 65W VRACPU_CSUMA 18 VDIFFB
CSSUMA
VRAGT_CSUMB 19
CSSUMB 11 VRAGT_VFB PR170 *0_04 PC134 *470p_50V_X7R_04
GND_SIGNAL VRASA_CSUMC 20 VFBB
CSSUMC
PR56 28.7K_1%_04 VRACPU_IMON 21 PR171 *100_04
IMONA VRAGT_VOSEN VGT_VCCSENSE_J VCCGT VCCGT_SENSE 7
12 PJ22 1 2 1mm
GND_SIGNAL PC170 680p_50V_X7R_04 VRAGT_IMON 22 VOSENB
IMONB 13 VRAGT_VORTN VGT_VSSSENSE_J PJ21 1 2 1mm VSSGT_SENSE 7

VORTNC

VOSENC
VRASA_IMON VORTNB

VDIFFC
PR57 118K_1%_04 23 PR190 *100_04
IMONC

TEMP

VFBC
GND_SIGNAL PC171 180p_50V_NPO_04

PR58 332K_1%_04

45

14

15

17

16
GND_SIGNAL PC42 68p_50V_NPO_04

Iccmax setting: PR44 *100_04


VRA_VTEMP VRASA_VOSEN VCCSA_VCCSENSE_J VCCSA
Vcore: 128A 53,56 VRA_VTEMP PR41 0_04 PJ1 1 2 1mm VCCSA_SENSE 6

VGT:32A
VSA: 11.1A PC40 PR54
TDC setting: 1u_16V_X7R_06 49.9K_1%_04
VRASA_VORTN VCCSA_VSSSENSE_J PJ2 1 2 1mm VSSSA_SENSE 6
Vcore: 80A PR55 *100_04
B VGT:14A B

AC/DC LLsetting:
VRASA_VFB
6+257
Vcore: 1.8m PR189 *0_04 PC146 *470p_50V_X7R_04

VGT:2.7m GND_SIGNAL
VSA: 10.3m VRASA_VDIFF PR188 8.2K_1%_04
GND_SIGNAL

VDD3

PR69
PR310 *0_04 *10K_1%_04

PD17
A C VRACPU_PE
24,47,58,61 EC_GPIO

RB751S-40H
D02 POWER ISSUE
PC50 PR70
100K_04
*0.1u_16V_X7R_04 D02_102518_Power

GND_SIGNAL

A A

PR196 0_06

GND_SIGNAL

4,6,33,50 1.05V_VCCST
6,56 VCCSA
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
8,9,23,24,27,29,30,31,32,33,34,35,36,39,40,41,43,44,45,47,49,50,61,74,77 3.3VS Title
5,53 VCORE [54] VCC_CORE & VCCGT &VCCSA
29,34,49,50,51,52,53,55,56,57,59,78 VIN
Size Document Number R ev
4,23,24,31,32,34,37,40,41,43,45,47,48,49,50,51,55,57,58,59,60,61,62,65,74,77,78 VDD3
7,56 VCCGT A2 SCHEMATIC1 6-71-NH500-D02 D02

Date: Wednesday, December 05, 2018 Sheet 54 of 78


5 4 3 2 1

VCC_Core & VCCGT B - 55


Schematic Diagrams

1.05DX_VCCSTG/VCCSFR_OC
5 4 3 2 1

NOTE:
1.05DX_VCCSTG Ton need <65us
M5938 TURON-ON TIME=60us
SHORT
PJ20 1mm

VDD1.05
1.05DX_VCCSTG 1 2 1.05DX_VCCSTG

U23

2 4 1A VOUT1_U140
VIN VOUT C846
D D
C845 C847

*0.1u_10V_X7R_04
1u_6.3V_X5R_02

*10u_6.3V_X5R_06
R431

VDD3 VDD3 *100_04


*0.1u_10V_X7R_04 PC88

U22 R435 VCCSFR_OC Combine with

5
TC7SZ08FU

D
39,50 GPP_J1
R434 20K_1%_04 1
4 VCCSTG_EN 6
ON VBIAS
5 5V
*100K_04 Q48
3.3VA(U16)
B.Schematic Diagrams

2 G
*2SK3018S3

S
D
3
Q49

180p_50V_NPO_04 C849
C848
R429 *0_04 VCCSTG_EN G

0.1u_10V_X7R_04
*2SK3018S3

S
Sheet 55 of 73
1.05DX_VCCSTG/ 1
GND NC
3

50
C C

VCCSTG_EN
29,32,34,42,47,49,50,52,62 SUSB#
FA7609A6

VCCSFR_OC
6+257
1.8VA PU20
PJ33
1
*1mm
2
PWR_SRC_NV_FB
AOZ2261NQI-11 PJ34 *1mm
VREG5 1 2 VIN
3.3VA VIN 7
21 VCC VIN 8 PC206 PC224 PC223
VIN 9

0.1u_25V_X7R_06

4.7u_25V_X7R_08

4.7u_25V_X7R_08
VIN 22 D02_1115_Power
VIN 24 + +
PC207
PR248 1u_16V_X7R_06 TON 6 PR269 180K_1%_04
10K_1%_04

BST 20 PR249 0_04 PC209


0.1u_16V_X7R_04

1.8VA_PGD 1
50 1.8VA_PGD PGOOD

B PR265 *10K_1%_04 B
VREG5
SW 10
PS_1V8_PFM
3 11 1.8VA
PFM* SW
SW 16
PR267 17

SHORT
SW
SW 18 PL17 8A
10K_1%_04 SW 25 2 1
BCIHP5420HC-1ROM
3.3VA PR247 100K_04 PJ311 2 *CV-40mil 2 EN/DSG PC225 PC227 PC226 PC229 PC228
ISET 19 PR251 *6.8K_1%_04
1.8VA

22u_6.3V_X5R_06

22u_6.3V_X5R_06

22u_6.3V_X5R_06

22u_6.3V_X5R_06

*22u_6.3V_X5R_06
PC208 100p_50V_NPO_04
PC221
PR250 15K_1%_04 ?
PJ32 *1mm 23 SS FB 5 680p_50V_X7R_04
1 2
41,47,50,78 SLP_SUS#
PC205 PR266
PR270
PC222 2200p_50V_X7R_04 PGND 12 10K_1%_04
4 AGND PGND 13
D02_102718_Alex 0.1u_16V_X7R_04 *10K_1%_04 PGND 14
PGND 15

PR268

4.99K_1%_04
Raven Modfiy 0726

A A
60,61,78 PW R_SRC_NV_FB
29,34,49,50,51,52,53,54,56,57,59,78 VIN
51 VREG5
8,9,23,24,27,29,30,31,32,33,34,35,36,39,40,41,43,44,45,47,49,50,54,61,74,77
37,62,72
3.3VS
1.8VA ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
4,31,32,33,34,37,39,45,50 3.3VA
Title
4,23,24,31,32,34,37,40,41,43,45,47,48,49,50,51,54,57,58,59,60,61,62,65,74,77,78
42,49,51
VDD3
VDD5
[55]1.05DX_VCCSTG/VCCSFR_OC/1.8
6,8,9,34,50,52 VDDQ
Size Document Number Rev
29,42,44,49,50,52,60,73
4,6,34
5V
1.05DX_VCCSTG A3 SCHEMATIC1 6-71-NH500-D02 D02
36,37,50 VDD1.05
Date: W ednesday, December 05, 2018 Sheet 55 of 78
2,24,29,42,44,49,50,52,53,56,59,60,61,72,73 3.3V
5 4 3 2 1

B - 56 1.05DX_VCCSTG/VCCSFR_OC
Schematic Diagrams

VCCGT & VCCSA Output Stage


5 4 3 2 1

VIN

D
2.5A Co-lay
D

PC194 PC219 PC203

1u_25V_X7R_06

10u_25V_X6S_08

10u_25V_X6S_08
VCCGT1Phase
3.3V

PU17 MP86901-CGLT-Z

PC195
1u_6.3V_X6S_04
20
VCC VIN1
VIN2
1
14 D02_1030_Power
%

B.Schematic Diagrams
D02_1030_Power
19 21 BST_GT
AGND BST

54 VRAGT_PW M1 PR246 0_04 15 2 PC196


PWM SW1 3 1u_25V_X6S_04 PL15
PR245 0_04 17 SW2 4 SW _GT 2 1
53,54,56 VRA_VTEMP VTEP/FLT SW3 VCCGT
CMME063T-R15MS0R907
16 13 0V~1.5V
53,54,56 VRA_STB SYNC PGND9 12 DIPLF! DNNF174U.S26NT1S:18 + PC62
Sheet 56 of 73

2.2_06
PGND8 11

PR228
PGND1
PGND2
PGND3
PGND4
PGND5

54 VRAGT_CS1 18 PGND7 10 Jsnt>49B! Jtbu>56B! EDS>1/:1nS PC288 PC287 PC289


CS PGND6 330U_2V_D2_D
+
VCCGT & VCCSA

22u_6.3V_X5R_06

22u_6.3V_X5R_06

PSLB30E227M
5
6
7
8
9

C PC193 C

2200p_50V_X7R_04
Output Stage
D02_102518_Power

Near CPU side

VIN

1.5A Co-lay

PC132 PC111 PC112 PC113

1u_25V_X7R_06

10u_25V_X6S_08

10u_25V_X6S_08

*25TQC15MYFB
+
VCCSA1Phase
3.3V

(
PU9
B MP86901-AGQT-Z B
12 1
PC129 VCC VIN1 6
1u_6.3V_X6S_04
11
VIN2
13 BST_SA
11.1A
AGND BST VCCSA
PC131 PL8
54 VRASA_PW M1 PR154 0_04 7 2 1u_16V_X7R_06 BCIHP0730-R47M
PWM SW1 3 SW _SA 1 2
PR152 0_04 9 SW2
53,54,56 VRA_VTEMP VTEP/FLT
53,54,56 VRA_STB 8
SYNC
2.2_06

4 PC187 PC186 PC185 PC184


PR169

10 PGND1 5
54 VRASA_CS1 CS PGND2 +

22u_6.3V_X5R_06

22u_6.3V_X5R_06

22u_6.3V_X5R_06
*PSLB30E227M
PC133

2200p_50V_X7R_04

D02_1107_Power

A A

ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Title
[56] VCCGT & VCCSA OUTPUT STAGE
2,24,29,42,44,49,50,52,53,59,60,61,72,73 3.3V Size Document Number Rev
6,54
7,54
VCCSA
VCCGT
A3 SCHEMATIC1 6-71-NH500-D02 D02

29,34,49,50,51,52,53,54,55,57,59,78 VIN Date: W ednesday, December 05, 2018 Sheet 56 of 78


5 4 3 2 1

VCCGT & VCCSA Output Stage B - 57


Schematic Diagrams

AC_In, Charger

1 2 3 4 5

SMART CHARGER

A
VIN A

A
PD14 PD13
Samuel ADD PC362, PC422 12/20 MDL914S2 MDL914S2

J_DC_JACK1
Gary_EMI TEST
EML2

C
HCB2012KF-800T80
JDC_AC EML1

4
1 HCB2012KF-800T80
3 2
3 PC1

5
PC2 PC3 PC5 VDD3
2DC3003-002211

0.1u_25V_X7R_06
0.1u_25V_X7R_06

*10u_25V_X5R_08
10u_25V_X5R_08
VA1

PR48
180K_1%_04
B.Schematic Diagrams

PR47
VA
ILIM
PQ1 PQ2
6-20-B3810-003 QM3116M6 QM3116M6
P/N = PRS1 45.3K_1%_04
PCB Footprint = TDC-099DHSR2-L-005-J-1 WMCSL0612R005FETA D01A
_ D S S D Battery Voltage:

PD12
PC6 PC70 PC220 PC71 PC66 PC67 PC69 PC68
12V~16.8V

1000p_50V_X7R_04
PC8 PR52 PR61 PR60

0.1u_25V_X7R_06

4.7u_25V_X7R_08

4.7u_25V_X7R_08

4.7u_25V_X7R_08

4.7u_25V_X7R_08
PC9 D02_1115_EMI

1500p_50V_04
0.047u_25V_X7R_06
PC4 PR2 PR1 *0402_short *0402_short 10_1%_06 Gary_Add N870 BAT. CON.

G
PC46

0.1u_25V_X7R_06
SMAJ20A

1000p_50V_X7R_04
ULTRASO-8ULTRASO-8

10u_25V_X5R_08
PC48

Sheet 57 of 73
PR4

D
4.7_06
4.7_06 PR49

A
1u_25V_X7R_06 4.02K_1%_04 PQ12 C1268
4.7_04 C1269     
PC47 BATDRV G QM3116M6
PC7

0.01u_50V_X7R_04

0.01u_50V_X7R_04
0.1u_25V_X7R_06 0.1u_25V_X7R_06 N87

S
PC36 PC34

2.2u_25V_X5R_08
ULTRASO-8

AC_In, Charger
2.2u_16V_X5R_06 PC23
0.1u_25V_X7R_06 REGN
0.01u_25V_X7R_04
PR5 PR3

2
3
4
BTST PR51 0_06
4.02K_1%_04 4.02K_1%_04 PL9 PRS2 V_BAT

29

28
27
26
25
24
23
22
PU1 HIDRV 1 BCIHP0730-4R7M WMCSL0612R005FETA J_BAT1
2 1 V_BAT

GND_2

PHASE
HIDRV

LODRV
GND_1
VCC

BTST
REGN
B PC35 9 5 B
0.047u_25V_X7R_06 SMC_BAT PL1 HCB1005KF-121T20
1 21 8 SMD_BAT 4

PC30

PC28

PC29
ACN Phase

PC160
PR34 HCB1005KF-121T20 N85
ACN ILIM PC45 3

PR22 *0402_short

PR45 *0402_short
ACP 2 20 LODRV PR35 PL2
470K_04 CMSRC 3 ACP BQ24780SRUYR SRP 19 *100p_50V_NPO_04 2
CMSRC SRN 1

5
6
7
ACDRV 4 18
ACDRV BATDRV 47 BAT_DET

EMC1

EMC2

EMC3
ACPRES 5 17 SRP

10u_25V_X6S_08

10u_25V_X6S_08
10_04 PR46 *20K_04 BA05N16BA0075

*10u_25V_X6S_08

*10u_25V_X6S_08
ACDET 6 ACOK BATSRC 16 SRN PQ11

PROCHOT#

C
IOUT 7 ACDET TB_STAT# 15 10_04 PR50 AON6992

CMPOUT
IADP BATPRES# PD5 PD3 PD6 PD4

IDCHG

CMPIN
PMON

30p_50V_NPO_04

30p_50V_NPO_04

30p_50V_NPO_04
PC27
6-21-D34H0-105

SDA
SCL
PR31 0.1u_25V_X7R_06 10_04 PR25 PC33

SS1040WG

SS1040WG
*MMSZ5232BS

*MMSZ5232BS
SMC_BAT 24,47,54,58
0.1u_25V_X7R_06

A
75K_1%_04 IDCHG TB_STAT PC44
SMD_BAT 24,47,54,58

8
9
10
11
12
13
14
0.1u_25V_X7R_06
PC25
PC32
100p_50V_NPO_04 PR23 0.1u_25V_X7R_06 D01A_0214
10K_1%_04 PR24 PR204
*10K_1%_04 2.2_06

100p_50V_NPO_04
PR32 *0_04 PC190
23,57 AC/BATL#
PC24 PR21 VDD3
*10K_1%_04 4700p_50V_X7R_04
PR20 0_04 PR28
54 PSYS
10K_1%_04

VDD3
SMD_BAT PR27 0_04

SMC_BAT PR26 0_04

C C

PR29 0_04
TOTAL_CUR 47

PC26
PR30 PC22

100p_50V_NPO_04
*24K_1%_04 *1u_25V_X5R_06

Option close to EC
VDD3

PR33
Battery Voltage:
10K_04

VDD3
12V~16.8VAC/BATL# 23,57
D

PQ3
G
PR53 2SK3018S3
S

PQ13 PR225
47K_04 MTE1K0P15KN3 300K_1%_04
V_BAT S D BATVLT
BAT_VOLT 47

AC_IN# 47
PR227
6-21-D34J0-105

G
PR72 PR226 PC192
C

PD1 10K_04 100K_04


C A B PQ4 60.4K_1%_04 0.1u_16V_X7R_04
VA
BATGS
ZD5245BS2 BTN3904

D
E

PR73

10K_04 G PQ14
VDD3
2SK3018S3
S

D D
4,6,34,55 1.05DX_VCCSTG
AC_IN 49 VA
4,23,24,31,32,34,37,40,41,43,45,47,48,49,50,51,54,55,58,59,60,61,62,65,74,77,78 VDD3
29,34,49,50,51,52,53,54,55,56,59,78 VIN

ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Title
[57] AC_IN,CHARGER
Size Document Number R ev
A2 SCHEMATIC1 6-71-NH500-D02 D02

Date: Wednesday, December 05, 2018 Sheet 57 of 78


1 2 3 4 5

B - 58 AC_In, Charger
Schematic Diagrams

NVVDD1
8 7 6 5 4 3 2 1

PD15
C A
EC_GPIO 24,47,54,61

MDL914S2

+,- 0 VDD3 1V8_AON NV3V3


D D
1- 2 /
PR155 *0_04
 %&'() * +, *
#")#"** . 24,47,54,57 SMD_BAT
PR157 PR160 PR144

*10K_1%_04

10K_1%_04

10K_1%_04
PR156 *0_04
24,47,54,57 SMC_BAT 1V8_AON
#. 
PR142 0_04
! !#) " 24,61 I2CC_SDA_PP

%& " #' 2 PR143 0_04


24,61 I2CC_SCL_PP
PR141 100_04
' '#) "

1
PR158 0_04 NTC1 PR17
PC21
24,59 NV_NVVDD_EN

100k_1%_04_NTC
0.01u_50V_X7R_04
AGND_MP2886A PC115 *1uF_25V_X7R_04 4.99K_1%_04

2
PR161 0_04 PR18 0_04
23 GPIO6_NVVDD_PSI#_R
AGND_MP2886A
GPU_GND_SENSE 25
PR159
*100_04 PR19 0_04
10,24 NVVDD_PWRGD
GPU_NVVDD_SENSE 25
PR164 0_04 AGND_MP2886A MP2886A_PWMVID

B.Schematic Diagrams
23 GPIO0_NVVDD_PWM_VID
NVVDD

MP2886A_VOSEN
MP2886A_VORTN
MP2886A_VDD18
PR162 PR163 *0_04


MP2886A_TSNS
MP2886A_SDA
MP2886A_SCL
MP2886A_PSI
*100_04 PR138 100_04

MP2886A_EN
PR146 0_04 MP2886A_VTEMP   ! "   #$
59 NVVDD_DRMOS_VTEMP
AGND_MP2886A
PR145 PC116
10K_04 0.01u_50V_X7R_04
#$

"
NV3V3 PU4

41

40

39

38

37

36

35

34

33

32

31
!

%&

AGND_MP2886A

Sheet 58 of 73

VTEMP

SCL

SDA
AGND

PWMVID

PGOOD

PSI

EN

TSNS/BOOT

VORTN

VOSEN
PR147 AGND_MP2886A
*10K_04
'
(
NVVDD_TALERT# 1 30
C C
TALERT# T5

2
T1 VFB
29 MP2886A_VFB

MP2886A_VDIFF
PR139 150_1%_04
PR140 *0_04
NVVDD1
3 28 PC114
T2 VDIFF
*1000p_50V_X7R_04
4 27
T3 T4 AGND_MP2886A
PR132 61.9K_1%_04 PC107 1000p_50V_X7R_04
5 26 MP2886A_IREF
NC
MP2884AGU-1311-Z IREF
PR128 PR129 549_1%_04
6 25 MP2886A_IMON AGND_MP2886A
NC IMON 8.45K_1%_04
PR131 3.32K_1%_04
7 24 MP2886A_VDD18
NC ADDR AGND_MP2886A
PR135 0_04
MP2886A_PWM4 8 23 MP2886A_VDD18
59 NVVDD_PHASE4_PWM PWM4 VDD18 PR130 D02_102518_Power
PR134 0_04 2.94K_1%_04
MP2886A_PWM3 9 22 PC14
59 NVVDD_PHASE3_PWM PWM3 VINSEN
1u_16V_X7R_06
PR133 0_04
MP2886A_PWM2 10 21
59 NVVDD_PHASE2_PWM PWM2 CSSUM PWR_SRC_NV
AGND_MP2886A AGND_MP2886A
PR127 0_04 PR119 1.5M_1%_04

VDD33
PWM1
MP2886A_PWM1 MP2886A_VINSEN PWR_SRC_NV

CS4

CS3

CS2

CS1
59 NVVDD_PHASE1_PWM

1000p_50V_X7R_04
NC

NC

NC

NC
PC108 PR120
100K_1%_04 D02_102518_Power
11

12

13

14

15

16

17

18

19

20
MP2886A_VDD33

AGND_MP2886A
MP2886A_CSSUM
VDD3
B PR125 0_04 B
PR121 PR122 PR123 PR124
1K_1%_04 1K_1%_04 1K_1%_04 1K_1%_04

PC90
PR126 0_04 1u_16V_X7R_06

AGND_MP2886A




 
  59 NVVDD_PHASE4_CS

59 NVVDD_PHASE3_CS

 
59 NVVDD_PHASE2_CS

  59 NVVDD_PHASE1_CS

A A

ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
29,34,49,50,51,52,53,54,55,56,57,59,78 VIN
4,23,24,31,32,34,37,40,41,43,45,47,48,49,50,51,54,55,57,59,60,61,62,65,74,77,78 VDD3
10,12,13,14,15,17,18,20,21,22,23,24,25,61,62,78 1V8_AON
10,11,21,23,62 1V8_RUN Title
8,9,23,24,27,29,30,31,32,33,34,35,36,39,40,41,43,44,45,47,49,50,54,61,74,77
27,30,32,44,45,47,48,49,74,77,78 5VS
3.3VS [58] NVVDD1
Size Document Number R ev
19,20,25,59
10,23,30,61,62,78
NVVDD
NV3V3
A2 SCHEMATIC1 6-71-NH500-D02 D01

Date: Wednesday, December 05, 2018 Sheet 58 of 78


8 7 6 5 4 3 2 1

NVVDD1 B - 59
Schematic Diagrams

NVVDD2

5 4 3 2 1

D02_1115_EMI

C1266 C1267

0.01u_50V_X7R_04

0.01u_50V_X7R_04
VIN

PC103 PC105 PC104


PWR_SRC_NV

*EEEFZ1E101P

*EEEFZ1E101P

*EEEFZ1E101P
D02_102518_Power PWR_SRC_NV + + +
D02_102518_Power

PC101 PC102

10u_25V_X6S_08

10u_25V_X6S_08
D PC100 PC124 PC93 PC91 D
+

*25TQC15MYFB

10u_25V_X6S_08

10u_25V_X6S_08
1u_25V_X7R_06 PC92 PC118
+

*25TQC15MYFB
M-C0603 1u_25V_X7R_06
M-C0603

14

1
PU8

14

1
3.3V PC123 1u_25V_X7R_06 PU5

VIN2

VIN1
21 PC117 1u_25V_X7R_06

VIN2

VIN1
BST 21
PR16 0_06 NVVDD_DRMOS_VCC 20 M-C0603 BST
VCC 2
D02_1114_Power
NVVDD NVVDD_DRMOS_VCC 20 M-C0603
PC10 SW VCC 2 NVVDD
3 PL6 PC13 SW
1u_6.3V_X6S_04 SW BCIH11740HC-R22M 3 PL3
D02_102518_Power 4 2 1 D02_102518_Power
1u_6.3V_X6S_04 SW BCIH11740HC-R22M
SW
PR6 19
AGND MP86941GQVT-Z <Function>
SW
4 2 1
2K_04
16 17
PR9 19 MP86941GQVT-Z
AGND
<Function>

2.2_06
2K_04 D02_1114_Power
SYNC VTEMP/FLT NVVDD_DRMOS_VTEMP 58,59 16 17

PR12

2.2_06
15 18 SYNC VTEMP/FLT NVVDD_DRMOS_VTEMP 58,59

PR15
58 NVVDD_PHASE1_PW M PWM CS NVVDD_PHASE1_CS 58
B.Schematic Diagrams

15 18
58 NVVDD_PHASE4_PW M PWM CS NVVDD_PHASE4_CS 58

PGND

PGND

PGND

PGND

PGND

PGND

PGND

PGND

PGND

PGND

PGND

PGND

PGND

PGND

PGND

PGND

PGND

PGND
PC17
PC20
2200p_50V_X7R_04

10

11

12

13
2200p_50V_X7R_04

10

11

12

13
PWR_SRC_NV D02_102518_Power

Sheet 59 of 73 PC94 PC95

10u_25V_X6S_08

10u_25V_X6S_08
PC97 PC122
+

*25TQC15MYFB
1u_25V_X7R_06
M-C0603

14
NVVDD2

1
PU7
PC121 1u_25V_X7R_06

VIN2

VIN1
C 21 C
BST
NVVDD_DRMOS_VCC 20 M-C0603
VCC 2 D02_1114_Power NVVDD
SW
PC11
3 PL5
SW BCIH11740HC-R22M
1u_6.3V_X6S_04
4 2 1
PR7
2K_04
19
AGND MP86941GQVT-Z SW <Function>

16 17

2.2_06
SYNC VTEMP/FLT NVVDD_DRMOS_VTEMP 58,59

PR13
15 18
58 NVVDD_PHASE2_PW M PWM CS NVVDD_PHASE2_CS 58

PGND

PGND

PGND

PGND

PGND

PGND

PGND

PGND

PGND
PC18

2200p_50V_X7R_04

10

11

12

13
PWR_SRC_NV
D02_102518_Power

PC98 PC99
10u_25V_X6S_08

10u_25V_X6S_08

PC96 PC120
+
*25TQC15MYFB

1u_25V_X7R_06
M-C0603

14

1
PU6
PC119 1u_25V_X7R_06

VIN2

VIN1
21
BST
NVVDD_DRMOS_VCC 20 M-C0603
VCC 2 D02_1114_Power NVVDD
PC12 SW
3 PL4
B
1u_6.3V_X6S_04 SW BCIH11740HC-R22M
B
4 2 1
SW
AGND MP86941GQVT-Z
PR8 19 <Function>
2K_04
16 17

2.2_06
SYNC VTEMP/FLT NVVDD_DRMOS_VTEMP 58,59

PR14
15 18
58 NVVDD_PHASE3_PW M PWM CS NVVDD_PHASE3_CS 58
PGND

PGND

PGND

PGND

PGND

PGND

PGND

PGND

PGND PC19

2200p_50V_X7R_04
5

10

11

12

13

GPU DECOUPLING
85A NVVDD

330uF_2V_5*5*4.2 x 6 pcs
NVVDD ONLY G2 STUFF

VDD3 PR187 PR186 PR185 PR165


PC181 PC191 PC161 PC167 PC163 PC166 PC165 PC162 PC164
15_1%_06 15_1%_06 15_1%_06 15_1%_06
*330U_2V_D2_D

*330U_2V_D2_D

*330U_2V_D2_D

*330uF_2V_5*5*4.2

330uF_2V_5*5*4.2

330uF_2V_5*5*4.2

330uF_2V_5*5*4.2

*330uF_2V_5*5*4.2

330uF_2V_5*5*4.2

+ + + + + + + + + *10u_6.3V_X5R_06 PC144

㚱0
⎒ 㰺㚱08s
<FUNCTION>

<FUNCTION>

15R 6 i z e
PR183

5
5
5
5
2K_04
枸䔁㰺 SLG 㓦暣
4 PQ10
D02_1107_Power D02_1107_Power PR184 *0_04
24,62 NV_1V8RUN_EN PDC3906Z

1
2
3
CLOSE TO CHOCK

D
A PQ9 A
2SK3018S3
PR137 *0402_short G PC145
24,58 NV_NVVDD_EN
*10u_6.3V_X5R_06

ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Title
2,24,29,42,44,49,50,52,53,56,60,61,72,73
4,23,24,31,32,34,37,40,41,43,45,47,48,49,50,51,54,55,57,58,60,61,62,65,74,77,78
3.3V
VDD3
[59] NVVDD2
29,34,49,50,51,52,53,54,55,56,57,78 VIN Size Document Number Rev
10,23,30,58,61,62,78
19,20,25,58
NV3V3
NVVDD A2 SCHEMATIC1 6-71-NH500-D02 D01

Date: W ednesday, December 05, 2018 Sheet 59 of 78


5 4 3 2 1

B - 60 NVVDD2
Schematic Diagrams

PEX_VDD
8 7 6 5 4 3 2 1

PEX_VDD PWR_SRC_NV_FB
PU10

AOZ2261NQI-11
5V

VIN 7
3.3V 21 VIN 8 PC110 PC109 PC127
VCC
VIN 9

0.1u_25V_X7R_06

4.7u_25V_X7R_08

4.7u_25V_X7R_08
D VIN 22 D02_1115_Power D
PC16 VIN 24 + +
1u_16V_X7R_06
PR11 TON 6 PR168 100K_1%_04
*10K_1%_04

BST 20 PR10 0_04 PC15


0.1u_16V_X7R_04
PEX_VDD_PWRGD 1 PGOOD

5V PR150 *10K_1%_04
SW 10
3 PFM* SW 11 PEX_VDD
SW 16
PR151 17
SW
SW 18
25 2
PL7
1
8A
10K_1%_04 SW
BCIHP5420HC-1ROM PEX_VDD
PS_1V8_EN_R
PR148 0_04 2 EN/DSG PR136 *6.8K_1%_04 PC43 PC169 PC182 PC168 PC183
24 NV_PEXVDD_EN
ISET 19 PC128 100p_50V_NPO_04

22u_6.3V_X5R_06

22u_6.3V_X5R_06

22u_6.3V_X5R_06

22u_6.3V_X5R_06

*22u_6.3V_X5R_06
PR153 15K_1%_04

B.Schematic Diagrams
?
23 5 D02_Gary
SS FB
VDD3 PR307 PR301 PR305 PR304
PC125 PR149 PC126
1.5_1%_06 1.5_1%_06 1.5_1%_06 1.5_1%_06
*0.1u_16V_X7R_04 2200p_50V_X7R_04 PGND 12
*10K_1%_04 4 AGND PGND 13
PGND 14 *10u_6.3V_X5R_06 PC290
PGND 15
PC130
PR167
100p_50V_NPO_04 PR302
10K_1%_04
Sheet 60 of 73

5
5
5
5
2K_04

4 PQ20
PDC3906Z

1
2
3
PEX_VDD

D
PQ21
C PR166 C
2SK3018S3
NV_PEXVDD_EN G PC291
14.7K_1%_04
*10u_6.3V_X5R_06

S
Cold boot/Optimus: 1V8_AONĺ 1 V8_ RUN ĺ NVVD Dĺ NVVDD S ĺ PEX_ VDDĺ F V Q
D
B
GC6 2.1 Exit: 1V8_RUNĺ NVVDD_L ĺ NVVDD_ Sĺ PEX_ VDDor 1V8 _ R UNĺ NVVD D_ L ĺ NVVDD_ S & PEX_V DD

B B

A A

ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
10,22 PEX_VDD
Title
29,42,44,49,50,52,55,73
4,23,24,31,32,34,37,40,41,43,45,47,48,49,50,51,54,55,57,58,59,61,62,65,74,77,78
5V
VDD3
[60] PEX_VDD
2,24,29,42,44,49,50,52,53,56,59,61,72,73 3.3V Size Document Number R ev
29,34,49,50,51,52,53,54,55,56,57,59,78
55,61,78
VIN
PWR_SRC_NV_FB A2 SCHEMATIC1 6-71-NH500-D02 D01

Date: Wednesday, December 05, 2018 Sheet 60 of 78


8 7 6 5 4 3 2 1

PEX_VDD B - 61
Schematic Diagrams

FBVDDQ
8 7 6 5 4 3 2 1

PD16
C A
EC_GPIO 24,47,54,58

MDL914S2
D D

FBVDDQ
NV3V3 D02_1107_MF
1V8_AON VDD3
3.3VS
+,- 0
 %&'() * +, * PWR_SRC_NV_FB
PR83 PR79
1- 2 / *10K_1%_04 *10K_04 PR239 D02_102518_Power
4.99K_1%_04 1V8_AON
#")#"** . B2 冯 2PCS 0805 CO-LAY
PR234 PR235 PR236 PC201 PC215 PC200
#.  *10K_1%_04 10K_1%_04 4.99K_1%_04 PR238 0_04

*25TQC15MYFB

10u_25V_X6S_08

10u_25V_X6S_08
! !#) " 24,58 I2CC_SDA_PP PC232
1u_25V_X7R_06
+ + +
PR237 0_04
%& " #' 2 100K_1%_04_NTC
24,58 I2CC_SCL_PP
B.Schematic Diagrams

' '#) "

1
PR80 0_04 NTC2 PR240 PC202 100_04 PR241
24 NV_FBVDDQ_EN

0.01u_50V_X7R_04
4.99k_1%_04

14
PR81 0_04 3.3V

1
2
PR242 0_04 PU19 MP86901-CGLT-Z PC231 1u_25V_X7R_06
23 GPIO25_FBVDD_PSI#_R 21
AGND_MP2884A

VIN1
VIN2
FBVDDQ_SENSE_RTN 25 BST
PR82
*R_04 24 DGPU_PWRGD PR243 0_04 PR255 0_06 FBVDD_DRMOS_VCC 20 M-C0603 FBVDDQ
PC214 VCC 2
FBVDDQ_SENSE 25 SW1 3
PR232 0_04 D02_102518_Power PL18
MP2884A_PWMVID_1 1u_6.3V_X6S_04 SW2 4
AGND_MP2884A BCIH11740HC-R22M

MP2884A_VOSEN_1
23 GPIO8_MEM_VDD_CTL

MP2884A_VORTN_1
19 SW3 2 1
FBVDDQ PR256

MP2884A_TSNS_1
Sheet 61 of 73
AGND

MP2884A_SDA_1
MP2884A_SCL_1


MP2884A_PSI_1
PR233 2K_1%_04 <Function>

MP2884A_EN_1
*R_04 PR257 0_04 D02_1114_Power
MP2884A_VTEMP_1   ! "   #$ 16

2.2_06
100_04 PR244
61 FBVDD_DRMOS_VTEMP SYNC

PR272
AGND_MP2884A 17
VTEP/FLT FBVDD_DRMOS_VTEMP 61

FBVDDQ PR258 PC216 15 18


61 FBVDD_PHASE1_PWM PWM CS FBVDD_PHASE1_CS 61

PGND1
PGND2
PGND3
PGND4
PGND5
PGND6
PGND7
PGND8
PGND9
10K_1%_04 0.1u_16V_X7R_04
#$

"
C C
3.3VS U33 PC234

41

40

39

38

37

36

35

34

33

32

31
!

AGND_MP2884A 2200p_50V_X7R_04
%&


VTEMP

SCL

SDA
AGND

PWMVID

PGOOD

PSI

EN

TSNS/BOOT

VORTN

VOSEN

5
6
7
8
9
10
11
12
13
PR260 AGND_MP2884A
10K_1%_04
'
( PWR_SRC_NV_FB
FBVDD_TALERT# 1 30
TALERT# T5 D02_102518_Power

B2 冯 2PCS 0805 CO-LAY


2 29 MP2884A_VFB_1 PR261 *R_04
T1 VFB PC243 PC244 PC242

10u_25V_X6S_08

10u_25V_X6S_08
PC218 PC239
MP2884A_VDIFF_1 150_04

*25TQC15MYFB
3 28 PR262 *C_04 1u_25V_X7R_06
(4
 T2 VDIFF + + +

4 27
 3 T3 T4 AGND_MP2884A
PR263 61.9K_1%_04 PC217 1000p_50V_X7R_04
5 26 MP2884A_IREF_1

14
 %%%%% NC IREF

1
PU21 MP86901-CGLT-Z PC240 1u_25V_X7R_06
MP2884AGU-1311-Z PR264 PR275 294_1%_04 21

VIN1
VIN2
6 25 MP2884A_IMON_1 AGND_MP2884A BST

 %%%%% NC IMON 18.2K_1%_04 FBVDD_DRMOS_VCC 20
VCC
M-C0603 FBVDDQ
PC86 2
7 24 PR86 MP2884A_VDD18_1
3.32K_1%_04 SW1 3
  NC ADDR AGND_MP2884A D02_102518_Power 1u_6.3V_X6S_04 SW2
SW3
4 PL19
BCIH11740HC-R22M D02_1114_Power
19
8 23 MP2884A_VDD18_1 AGND 2 1
PWM4 VDD18 PR279
PR85 2K_1%_04 <Function>
C806 430_1%_04 16
9 22 SYNC

2.2_06
PWM3 VINSEN

PR278
1u_16V_X7R_06 17
PR259 0_04 15 VTEP/FLT 18 FBVDD_DRMOS_VTEMP 61
MP2884A_PWM2_1 10 21 61 FBVDD_PHASE2_PWM PWM CS FBVDD_PHASE2_CS 61

PGND1
PGND2
PGND3
PGND4
PGND5
PGND6
PGND7
PGND8
PGND9
61 FBVDD_PHASE2_PWM PWM2 CSSUM AGND_MP2884A
AGND_MP2884A
PR273 0_04 PR277 1.5M_1%_04

VDD33
PWM1
MP2884A_PWM1_1 MP2884A_VINSEN_1 PC241

CS4

CS3

CS2

CS1
61 FBVDD_PHASE1_PWM PWR_SRC_NV_FB 55,60,61,78

NC

NC

NC

NC

5
6
7
8
9
10
11
12
13
PR276 2200p_50V_X7R_04
100K_1%_04 D02_102518_Power_lot3

11

MP2884A_VDD33_1 12

13

14

15

16

17

18

19

20
B PC238 B
1000p_50V_X7R_04

FBVDDQ FBVDDQ
AGND_MP2884A
MP2884A_CSSUM_1
VDD3
PR274 0_04 AGND_MP2884A PR112 PR113

1K_1%_04
PR118 PR117 PR116 PR115 PR87 PC87 PC237 PC236 PC233 PC230

1K_1%_04

*1K_1%_04

0.1u_16V_X7R_04

330uF_2V_5*5*4.2

330uF_2V_5*5*4.2

330uF_2V_5*5*4.2

*330uF_2V_5*5*4.2
VDD3 15_1%_06 15_1%_06 15_1%_06 15_1%_06
PC235 + + + +
1u_16V_X7R_06
PR114 0_04

R338
C809 2K_04 PR88
5
5
5
5

*10u_6.3V_X5R_06 AGND_MP2884A *R_04


PQ8
4 EMB09N03V 61 FBVDD_PHASE2_CS
1
2
3

61 FBVDD_PHASE1_CS
D

AGND_MP2884A
NV_FBVDDQ_EN G C810
*10u_6.3V_X5R_06
S

PQ7
2SK3018S3

A A

ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
10,23,30,58,62,78 NV3V3
10,12,13,14,15,17,18,20,21,22,23,24,25,58,62,78 1V8_AON
8,9,23,24,27,29,30,31,32,33,34,35,36,39,40,41,43,44,45,47,49,50,54,74,77 3.3VS
4,23,24,31,32,34,37,40,41,43,45,47,48,49,50,51,54,55,57,58,59,60,62,65,74,77,78 VDD3 Title
10,11,21,23,62
2,24,29,42,44,49,50,52,53,56,59,60,72,73
1V8_RUN
3.3V
[61] FBVDDQ
55,60,61,78 PWR_SRC_NV_FB Size Document Number R ev
29,42,44,49,50,52,55,60,73
11,12,13,14,15,16,17,18,19,25
5V
FBVDDQ
A2 SCHEMATIC1 6-71-NH500-D02 D01

Date: Wednesday, December 05, 2018 Sheet 61 of 78


8 7 6 5 4 3 2 1

B - 62 FBVDDQ
Schematic Diagrams

1V8_RUN/AON
1 2 3 4 5 6 7 8

1.8VA 1.8VA
C124 C118 C117
U6 G5016
10u_6.3V_X5R_06 10u_6.3V_X5R_06 *10u_6.3V_X5R_06
A 1 6 A

1V8_AON 2A 13
2 IN1
IN1
IN2
IN2
7

8 2A
1V8_RUN
1V8_AON OUT1 OUT2 1V8_RUN
14 9
PR59 C175 OUT1 OUT2
10K_04 12 10
0.1u_10V_X7R_04 CT1 CT2 VDD3 1V8_RUN
24 1V8_AON_PWRGD

VBIAS
C173 C172

GND

GND
D02_1109_Alex

EN1

EN2
*100p_50V_NPO_04 330p_50V_NPO_04
R59 R80

15

11

5
VDD3 1V8_AON 100K_04 10_06
R81 0_04 1V8_AON_ON 1V8_RUN_ON R62 0_04
24 NV_1V8AON_EN VDD3 NV_1V8RUN_EN 24,59
C121 C120 C119

3
R61 R63 1u_6.3V_X5R_02 D D
*0.1u_10V_X7R_04 *0.1u_10V_X7R_04
100K_04 10_06 1V8_RUN_ON 2 G 5 G
S Q18A S Q18B

4
MTDK3S6R
MTDK3S6R
6

D D

B.Schematic Diagrams
1V8_AON_ON 2 G 5 G
S Q19A S Q19B
1

MTDK3S6R
MTDK3S6R

Sheet 62 of 73
B

VDD3
C97 C96
VDD3
B

1V8_RUN/AON
U7 G5016
0.1u_6.3V_X5R_02 10u_6.3V_X5R_06

NV3V3 MLCC Comm part 1


2 IN1
IN1
IN2
IN2
6
7

NV3V3
1A 13
OUT1 OUT2
8
14 9
C129 OUT1 OUT2 C126
12 10
0.1u_6.3V_X5R_02 CT1 CT2 0.1u_6.3V_X5R_02
VBIAS

MLCC Comm part C128 MLCC Comm part


GND

GND

C127
EN1

EN2

100p_25V_NPO_02 220p_50V_NPO_04
3

15

11

R65 0_04 NV3V3_EN


24 NV_NV3V3_EN VDD3
C98 C125 R64
1u_6.3V_X5R_02
*C_04 10K_04

C C
VDD3
1A

C646 C645
1.5VS
VDD5_LDO5
10u_6.3V_X5R_06_E 0.1u_10V_X7R_04
R231 C641
DEFAULT
*47K_04 U16 1u_6.3V_X5R_02 SHORT
G9661-25ADJF11U close pin 4
3 4 V1.5 PJ54 1.5VS
VIN VCNTL
1.5VS_PWRGD 1A OPEN-2mm
1 6 2 1
POK VOUT
5
R233 10K_04 PJ9 1 2 *CV-40mil 2 NC R228 C637 C638 C639
VDD3 EN
Ra
82p_50V_NPO_04

JUMP-1MM 8 7 8.87K_1%_04 22u_6.3V_X5R_06_E 0.1u_10V_X7R_04


9 GND VFB
R232 10K_04 GND
29,32,34,42,47,49,50,52,55 SUSB#
C643

*1u_6.3V_X5R_02 R229
Rb
10K_1%_04

D D

ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
4,23,24,31,32,34,37,40,41,43,45,47,48,49,50,51,54,55,57,58,59,60,61,65,74,77,78 VDD3
10,22,60 PEX_VDD
29,42,44,49,50,52,55,60,73 5V
10,12,13,14,15,17,18,20,21,22,23,24,25,58,61,78 1V8_AON Title
10,11,21,23 1V8_RUN [62] 1V8_RUN, 1V8_AON , NV3V3
10,23,30,58,61,78 NV3V3 Size Document Number R ev
8,9,23,24,27,29,30,31,32,33,34,35,36,39,40,41,43,44,45,47,49,50,54,61,74,77
37,55,72
3.3VS
1.8VA
A2 SCHEMATIC1 6-71-NH500-D02 D02

Date: Wednesday, December 05, 2018 Sheet 62 of 78


1 2 3 4 5 6 7 8

1V8_RUN/AON B - 63
Schematic Diagrams

Audio Board
5 4 3 2 1

1AR1 *0_04 4AR1 *0_04

6-71-NH508-D02 2AR1

3AR1
*0_04

*0_04
5AR1

6AR1
*0_04

*0_04 A_5V
USB PORT(PORT9) USB2.0 CON AC1 *22u_6.3V_X5R_06 AGND

A_USBVCC2
60 mil
A_USBVCC2 AC2 0.1u_10V_X7R_04 AGND
AU1
60 mil 60 mil
Ἕㆸ慵䔲 5 1
AUDIO BOARD Connector AC4
VIN VOUT

GND
2 AC5 AC6 AC7 CLOSE TO CONNECTOR
AC3 22u_6.3V_X5R_06 AGND

0.1u_10V_X7R_04

*0.1u_6.3V_X5R_02

10u_6.3V_X5R_06
4
10u_6.3V_X5R_06 3 AJ_USB1
EN# OC# AD1 1
AGND V+
D SY6288D20AAC GND2 D
AGND AGND AGND DT1140-04LP-7 2 GND2 GND1
_ AUSB2_PN9 6 5 AUSB_PN9_C DATA_L GND1
A_5V 6-02-62882-9C0 AGND AGND AUSB2_PP9 7 4 AUSB_PP9_C 3
AGND 8 3 DATA_H GND3
AGND AGND AGND

PCB Footprint = FP201-040X1-0M


GND2
40 9 2 4 GND4
10 1 GND AGND
39
38 AUSB_PN9 1 2 AUSB2_PN9
37 C107BF-10405-L
36 AUSB_PP9 4 3 AL1 AUSB2_PP9 AGND AGND

FP201H-040S10M
35 *WCM2012F2S-161T03-short
34
33
32
31
USB3.0 CON 60 mil
AC8 *22u_6.3V_X5R_06 AGND
30 AUSB_PP8 AGND AC9 22u_6.3V_X5R_06
A_USBVCC1 AGND
B.Schematic Diagrams

29 AUSB_PN8
28 AC10 0.1u_10V_X7R_04 AGND
27 AUSB3_RX8P AGND
AUSB_PN8 4 3 AUSB2_PN8

+
26 AUSB3_RX8N AC11 *100u_6.3V_B_A AGND
25 AUSB_PP8
24 AGND 1 2 AL11 AUSB2_PP8 CLOSE TO CONNECTOR
AUSB3_TX8N AJ_USB2
23 *WCM2012F2S-161T03-short
AUSB3_TX8P
22 AD2
21 AGND AUSB3_TX8_P_C 9 GND1
AUSB_PP9 D02_1115_Alex SSTX+ SHIELD

Standard-A
20 AUSB_PN9 1 10 1
AUSB3_TX8_N_C VBUS

Sheet 63 of 73 19 2 9 8
AGND 3 8 AUSB_PN8_C 2 SSTX- GND3
18 AGND AGND
AUSB3_TX8P AC27 0.1u_10V_X7R_04 4 7 AUSB3_TX8_P_C 4 D- SHIELD
17
AUSB3_TX8N AC28 0.1u_10V_X7R_04 5 6 AUSB3_TX8_N_C AUSB_PP8_C 3 GND GND4
16
AUSB3_RX8_P_C 6 D+ SHIELD
15

Audio Board 14
13
12
ASPDIFO
ASLEEVE_CON A_AUDG
AUSB2_PN8
AUSB2_PP8
5
4
DT1140-04LP-7
AD3
6
7
AUSB_PN8_C
AUSB_PP8_C
AUSB3_RX8_N_C
7
5
SSRX+
GND_D
SSRX- SHIELD
GND2

C 11 AHP_SENSE C
10 AMIC_SENSE AGND 3 8 AGND AGND C19007-90905-L NEW AGND
9 AUSB3_RX8N 2 9 AUSB3_RX8_N_C
AMIC1_L
8 AUSB3_RX8P 1 10 AUSB3_RX8_P_C
AMIC1_R
7 AHEADPHONE_L_DEPOP
6 AHEADPHONE_R_DEPOP A_5V A_USBVCC1
5 60 mil AU2 60 mil DT1140-04LP-7
4 5 1
VIN VOUT
3
GND1

2 AC12 2 AC13 AC14 AC15


A_AUDG GND
1

*0.1u_10V_X7R_04

*0.1u_6.3V_X5R_02

10u_6.3V_X5R_06
4
10u_6.3V_X5R_06 3
EN# OC#
AJ_AUD1
modification 0508 SY6288D20AAC
Biaggi AGND
AGND AGND
A_AUDG
6-02-62882-9C0 AGND AGND AGND

TOJ-0015STR2-2-H4-PA9T-J
AJ_SPDIF1
6-19-31001-004
AUDIO JACK AMIC1_R
AMIC1_L
AL4
AL5
FCM1005KF-121T03
FCM1005KF-121T03
A_AUDG
1
3
2
4
AC16 *0.1u_10V_X7R_04 AMIC_SENSE 5

AC18 *0.1u_10V_X7R_04 AC22 AC23 A


AGND
100p_50V_NPO_04 100p_50V_NPO_04 B DRIVE
AC20 0.1u_10V_X7R_04 A_5V C
Headphone IC
TX
AC21 0.1u_10V_X7R_04 AC26 0.1u_6.3V_X5R_02

GND1
GND2
B L L L A_AUDG
B
AGND A_AUDG AGND ASPDIFO_R
ASPDIFO AL13 FCM1005KF-121T03
A_AUDG
AH1 AH2
R R R
2 4 H2_8D1_8 MIC SPOIF COMBO JACK
M G AR2 AC19
BLACK
3 1 5
G 220_04 *100p_50V_NPO_04
G M modification 0508
Biaggi
MTH7_0D2_3 OMTP CTIA normal AGND 20180409 Update lib
AGND

A_AUDG A_AUDG

2
AH3
4
W/O Plug W/ Plug ㍍ 㱽(CTIA )

3 1 5
MIC 7 Resistor 32 or 33_04
AH4
H2_8D1_8 meet WLK Test
GND 1
MTH7_0D2_8 A_AUDG AR4 0_04
L 2
Short Open *15KV/0.2PF CESD0201UC5VB-M1 2 AEMD1
6 A_AUDG
AGND AGND X VT1802P 6-19-31001-245
6-19-31001-004 AJ_HP_COMBO1
6-19-31001-271 3
R 3 75_04 82_04
AHEADPHONE_L_DEPOP
AR3 EARPHONE_L AL6 FCM1005KF-121T03 EARPHONE_L_L 1
D02_1101_ME
A_AUDG Sense 4 HP_DET 5
Open Short 6-19-31001-004 AHP_SENSE 6
GND 5 AHEADPHONE_R_DEPOP
AR6 82_04 EARPHONE_R AL7 FCM1005KF-121T03 EARPHONE_R_R 2
ASLEEVE_CON AL12 AINT_MIC_OUT_R
FCM1005KF-121T03 4

2SJ3072-112111F
AC17 AC24 AC25

A modification 0508 A
Biaggi 100p_50V_NPO_04 100p_50V_NPO_04 100p_50V_NPO_04
HEADPHONE COMBO JACK

A_AUDG
AR1
A_AUDG BLACK modification 0508
Biaggi
A_COMBOJACK

AC29 22K_04 ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/


10u_6.3V_X5R_06 Title
[63]AUDIO BOARD
A_AUDG Size Document Number Rev
Custom 6-71-NH508-D03 D01

Date: Wednesday, December 05, 2018 Sheet 63 of 78


5 4 3 2 1

B - 64 Audio Board
Schematic Diagrams

NH50 PW Board
5 4 3 2 1

1BR1 *0_04 4BR1 *0_04

POWER SW BOARD 6-71-NH50S-D02 2BR1

3BR1
*0_04

*0_04
5BR1

6BR1
*0_04

*0_04
D

Ἕㆸ慵䔲

B.Schematic Diagrams
Sheet 64 of 73
C
BH_3.3VS
C
NH50 PW Board
POWER
POWER BUTTON
BOTTOM
LED
6-53-31500-B41 BR2
390_06
BSW 1
For N850 T4BJB10BQR
BJ_SW 1 1 2
6-13-82001-2AB
BH_3.3VS 3 4 BPW RBTN#
1
2
3 BDGND PCBfootprint:
BPW RBTN# TJE-53X-Q
4 BSW1

A
FP226H-004S10M BDGND 5
1 2 BD1
3 4
6 WHITE

C
RY-SP190DBW 71-5A
6-52-57301-022
BDGND

B B

BH3 D02_1101_ME
H3_0D1_8

C_GND

BH1 BH2
2 4 2 4 BH6
H2_8D1_8
3 1 5 3 1 5

A MTH7_0D2_3 MTH7_0D2_3 A

BDGND BDGND BDGND BDGND

ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Title
[64]NH50 PW BOARD
Size Document Number Rev
A3 6-71-NH50S-D03 D01

Date: W ednesday, December 05, 2018 Sheet 64 of 78


5 4 3 2 1

NH50 PW Board B - 65
Schematic Diagrams

Hall Sensor Board

5 4 3 2 1

HALL Sensor

D D
B.Schematic Diagrams

Sheet 65 of 73 VDD3 6-02-09249-LC0 OLD Value MH248-ALFA-ESO

Hall Sensor Board R794 *100K_04


6-02-00248-LC2

U46
C 1 2 LIDSW# R795 LID_SW# C
VCC OUT

GND
*10mil_short  

2
C1179 C1180
YB8251 D52

3
0.1u_6.3V_X5R_02
*100p_50V_NPO_04 *V15AVLC0402

1
LID_SW#
29,44,47 LID_SW#

B B

ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
A A

Title
[65]HALL SENSOR BOARD
Size Document Number Rev
A4 6-71-NH500-D02 D01
4,23,24,31,32,34,37,40,41,43,45,47,48,49,50,51,54,55,57,58,59,60,61,62,74,77,78 VDD3
Date: Wednesday, December 05, 2018 Sheet 65 of 78
5 4 3 2 1

B - 66 Hall Sensor Board


Schematic Diagrams

Click Board
5 4 3 2 1

1CR1 *0_04 4CR1 *0_04

6-71-NH502-D02 2CR1

3CR1
*0_04

*0_04
5CR1

6CR1
*0_04

*0_04

Ἕㆸ慵䔲
D D

B.Schematic Diagrams
FP226H-004S10M
C_GND
C_CTPBUTTON_L 1
2
C_CTPBUTTON_R 3
4
CJ_TP1
D02_1101_ME
Sheet 66 of 73
C C
Click Board

B B

LEFT RIGHT
KEY KEY
6-53-31500-B41
CSW 1 CSW 2
T4BJB10BQR T4BJB10BQR
1 2 C_CTPBUTTON_L 1 2 C_CTPBUTTON_R
3 4 3 4

6-53-31500-B40 6-53-31500-B40

C_GND C_GND

A A

D02_1101_ME CH2 CH6


CH8 CH9 2 4 2 4

ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
H2_8D1_8 H3_0D1_8
3 1 5 3 1 5

Title
MTH7_0D2_3 MTH7_0D2_3 [66]CLICK BOARD
Size Document Number Rev

AGND C_GND
C_GND C_GND C_GND C_GND A3 6-71-NH502-D03 D01

Date: W ednesday, December 05, 2018 Sheet 66 of 78


5 4 3 2 1

Click Board B - 67
Schematic Diagrams

LED Board
5 4 3 2 1

1LR1 *0_04 4LR1 *0_04

6-71-N87P4-D61 2LR1 *0_04 5LR1 *0_04

LED 3LR1 *0_04 6LR1 *0_04

D
Ἕㆸ慵䔲 D

6-52-55001-021
GREEN YELLOW LD1
L_3.3VS
LR1 220_04 A C L_LED_HDD#
HDD LED WLAN LED

RY-SP190YG34-5M WLAN ON Ṗ
GREEN YELLOW LD2
Windows 7
L_3.3VS
LR2 220_04 A

RY-SP190YG34-5M
C L_AIRPLAN_LED#
Airplane mode WLAN OFF ᶵṖ


B.Schematic Diagrams

Airplane ON
6-52-55001-021 Windows 8
Airplane OFF ᶵṖ

4
WLAN/BLUETOOTH LED

2
LD3 GREEN/YELLOW
Sheet 67 of 73 LR3 220_04 1
Y
2 L_GND

LED Board
*TVUDF1004AD0
LR4 220_04 3
SG
4 L_GND
BAT LED LJ_LED1
for 50
L_LED_PW R 1 10
C L_LED_ACIN RY-SP155HYYG4-1 L_LED_HDD# C
2 9 L_AIRPLAN_LED# 1
L_GND
L_LED_BAT_FULL
3 8 L_GND 6-52-55002-04E L_LED_BAT_FULL 2
4 7 LD5 L_LED_BAT_CHG 3
L_LED_BAT_CHG 5 6
LR5 220_04 1 2
GREEN/YELLOW L_LED_PW R 4
L_GND L_LED_ACIN 5
Y
LD4

LR6 220_04 3
SG
4 L_GND
POWER ON LED 6
7
8
9
NC2

NC1
L_GND 10
RY-SP155HYYG4-1
11
L_3.3VS 12
FP225H-012S10M

NH50

LJ_LED2
L_LED_HDD#
L_AIRPLAN_LED#
L_LED_BAT_FULL
1
2
3
for 70
L_LED_BAT_CHG
L_LED_PW R 4
L_LED_ACIN 5
6 NC2
7
8 NC1
B
9 B
L_GND 10
11
L_3.3VS 12
FP225H-012S10M

NH70

H32 H33 LH1 LH2


H3_0D2_0 H3_0D2_0 H6_0D2_3 H6_0D2_3

L_GND L_GND L_GND L_GND

A A

ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Title
[67]NHx0 LED BOARD
Size Document Number Rev
A3 6-71-NH504-D03 D61

Date: W ednesday, December 05, 2018 Sheet 67 of 78


5 4 3 2 1

B - 68 LED Board
Schematic Diagrams

NH70 PW Board
5 4 3 2 1

1B2R2 *0_04 4B2R2 *0_04

6-71-NH70S-D01 2B2R2

3B2R2
*0_04

*0_04
5B2R2

6B2R2
*0_04

*0_04

D D

Ἕㆸ慵䔲

B2H_3.3VS
POWER
POWER BUTTON
BOTTOM
LED
6-53-31500-B41 B2R4

B.Schematic Diagrams
390_04
B2SW 1
For NH70 T4BJB10BQR
B2J_SW 1 1 2
6-13-82001-2AB
B2H_3.3VS 3 4 B2PW RBTN#
1
2
3 B2DGND PCBfootprint:
B2PW RBTN# TJE-53X-Q
4

Sheet 68 of 73
BSW1

A
FP226H-004S10M B2DGND 5
1 2 B2D4
3 4
6 WHITE
NH70 PW Board

C
C C
RY-SP190DBW 71-5A
6-52-57301-022
B2DGND

B2H8
H2_8D1_8

B B

B2H9 B2H10
2 4 2 4 B2H7
H2_8D1_8
3 1 5 3 1 5

MTH7_0D2_3 MTH7_0D2_3

B2DGND B2DGND B2DGND B2DGND

A A

ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Title
[68]NH70 PW BOARD
Size Document Number Rev
A3 
6-71-NH70S-D01 D01

Date: W ednesday, December 05, 2018 Sheet 68 of 78


5 4 3 2 1

NH70 PW Board B - 69
Schematic Diagrams

Power Sequence
5 4 3 2 1

W650RN POWER ON SEQUENCE

VDD3

D 3.372v D
DD_ON
595.47us 3.367V
3.3V
1.398ms 5.19V
VDD5
1.963ms 5.18V
5V
30.459ms 3.348V
SLP_SUS#
31.018ms 3.371V
3.3VA
31.333ms 1.054V
VDD1.05
81.21963ms 3.368V
RSMRST
182.725ms 3.369V
PWR_BTN
B.Schematic Diagrams

178.754ms 3.372V
SUSC#
33.405us 3.372V
SUSB#
98.1771.214V
VDDQ
255.43us 3.3V
DDR1.35V_PWRGD

Sheet 69 of 73 1.05V_VCCST

VCCIO
691.20us 1.032V

703us 1.006V
C C

Power Sequence 3.3VS

5VS
767us 3.372V

790us 5.18V

1.234ms 1.033V
1.05DX_VCCSTG
1.248ms 1.213V
VCCSFR_OC
2.573ms 3.3V
VCCIO_PWRGD
2.578ms 3.367V
ALL_SYS_PWRGD
3.062ms 1.17V
DDR_VTT_PG_CTRL
3.072ms 0.603V
VTT_MEM
3.097ms 1.026V
VCCST_PWRGD
4.736ms 3.368V
VCORE_PG
4.789ms 3.371V
DELAY_PWRGD
4.801ms 3.367V
PM_PCH_PWROK
4.823ms 1.05V
VCCSA
4.865ms 3.3V
VCCGT_PG
B 404.918ms3.371V B
SYS_PWROK
407.281ms 3.371V
PLT_RST#
410ms 1.213V
VCORE
429.802ms 3.371V
PM_PWROK

A A

啵 ⣑ 暣 儎 CLEVO
Title
[71]Power Sequencing
Size Document Number Rev
A3 004
6-71-NH500-D02
Date: W ednesday, December 05, 2018 Sheet 71 of 78
5 4 3 2 1

B - 70 Power Sequence
Schematic Diagrams

USB Type-C
5 4 3 2 1

Ferrite Beads choose low DCR parts.


might choose, but not limited to:
BKP1608HS600-T
BLM18SG221TN1
BLM18SG121TN1
Note:
VDD0.9_LEX
1. These capacitors are used to reduce the slew rate of AUX CH to
Remove 0601 biaggi
meet the DP V1.4 AUX CH requirement.
PUT C1895
near Pin21 2. These capacitors are mandatory for HBR3 application, for HBR2
and lower, the caps are optional.
L24 FCM1608KF-301T05
3. Both the upstream and downstream port need to add the
D D
capacitor for HBR3 application.
1.8VA
C11 C19 C16 DP_E_AUX
L25

1000p_50V_X7R_04

4.7u_25V_X5R_06
0.01u_50V_X7R_04
1.8VA C1103
FCM1608KF-301T05 18p_25V_NPO_02
L26
FCM1608KF-301T05 DP_E_AUX#
C875
0.1u_25V_X5R_04 C20 C14 C13
VDD0.9_LEX NV_SBU1_J

1000p_50V_X7R_04

0.1u_25V_X5R_04

1u_25V_X5R_06
P1.8V C1
L27 FCM1608KF-301T05 18p_25V_NPO_02
3.3V NV_SBU2_J
C17 1u_25V_X5R_06

B.Schematic Diagrams
C21 C12
D02_1112_Alex

1u_25V_X5R_06

1000p_50V_X7R_04
Note: C18 1000p_50V_X7R_04
AC capacitors for DP main

10

41

21
51

22
32
48
60

11
39

54
link should be

1
U26
Close to
put close to DP source
Sheet 70 of 73

DVDD09_10

DVDD09_41
AVDD09_1
AVDD09_21
AVDD09_51

VDD18_22
VDD18_32
VDD18_48
VDD18_60

VDD_IO_11
VDD_IO_39

VDD33
USB TYPE-C Conn.
19 NV_TX_1_P C3 0.22u_10V_X5R_04 NV_TX_1_P_J
TX1P NV_TX_1_P_J 42
C Note:
Connect
Both SSTx and SSRx between USB
22
22
22
DP_E0
DP_E#0
DP_E1
DP_E0
DP_E#0
DP_E1
DP_E#1
C901
C902
C903
C904
0.22u_10V_X5R_04
0.22u_10V_X5R_04
0.22u_10V_X5R_04
0.22u_10V_X5R_04
55
56
58
59
ML0P
ML0N
ML1P
TX1N

RX1N
20

16
17
NV_TX_1_N

NV_RX_1_N
NV_RX_1_P
C2

C1260
C1261
0.22u_10V_X5R_04

0.33u_6.3V_X5R_04
0.33u_6.3V_X5R_04
NV_TX_1_N_J
D02_1112_Alex
NV_TX_1_N_J

NV_RX_1_N_J
42

42
C
USB Type-C
host and ANX7440 need AC to DP 22 DP_E#1 DP_E2 C906 0.22u_10V_X5R_04 2 ML1N RX1P NV_RX_1_P_J 42
capacitors. Source 22 DP_E2 DP_E#2 C905 0.22u_10V_X5R_04 3 ML2P Analogix Semi
22 DP_E#2 DP_E3 ML2N NV_TX_2_P NV_TX_2_P_J
USB host SSTx connects to 22 DP_E3 C891 0.22u_10V_X5R_04 5 24 C872 0.22u_10V_X5R_04 NV_TX_2_P_J 42
DP_E#3 C890 0.22u_10V_X5R_04 6 ML3P TX2P 23 NV_TX_2_N C871 0.22u_10V_X5R_04 NV_TX_2_N_J
ANX7440 SSRx. 22 DP_E#3 ML3N TX2N
D02_1112_Alex
NV_TX_2_N_J 42
USB host SSRx connects to 26 NV_RX_2_N C1262 0.33u_6.3V_X5R_04 NV_RX_2_N_J 42
DP_E_AUX C892 DP_E_AUX_L RX2N NV_RX_2_P
ANX7440 SSTx. 22 DP_E_AUX DP_E_AUX# C893
0.1u_25V_X5R_04
DP_E_AUX_L#
8
AUXP RX2P
27 C1263 0.33u_6.3V_X5R_04 NV_RX_2_P_J 42
The capacitors should be 22 DP_E_AUX# 0.1u_25V_X5R_04 9
AUXN 34 C877 0.1u_25V_X5R_04 NV_SBU1_J
placed modidication 0517 biaggi SBU1 NV_SBU2_J NV_SBU1_J 42
33 C876 0.1u_25V_X5R_04 NV_SBU2_J 42
near SSTx pin. C899 0.22u_10V_X5R_04 52 SBU2
Check? USB3.1 35 ANX7440_SSRXN SSTXN
C900 0.22u_10V_X5R_04 53
Connect 35 ANX7440_SSRXP
C897 0.22u_10V_X5R_04 49 SSTXP 45 R480 100K_04
to USB 35 ANX7440_SSTXN C898 0.22u_10V_X5R_04 50 SSRXN PULL_1 44 R479 100K_04
35 ANX7440_SSTXP SSRXP PULL_2
Source
Check ANX7440_POW ER_EN 7 P1.8V
73 ?
Need Save Power ANX7440_POW ER_EN POWER_EN
28
TEST_R 14 L28 FCM1005KF-601T03
VIN
D02_1114_Alex R482 0_04 ANX7440_SDA 38
73 MSTR_SDA_7440 ANX7440_SCL SDA
R478 0_04 37 C878 C879 PC89 C880
73 MSTR_SCL_7440 SCL 1000p_50V_X7R_04 0.1u_25V_X5R_04 10u_25V_X6S_08 22u_6.3V_X5R_06

P1.8V 43 L14
42 OP_MODE_0 13 AHP252012RA-3R3M VDD0.9_LEX
B OP_MODE_1 VX PCB Footprint = bcmpc252012a-xxxm GND_DCDC B
R481 4.7K_04 D02_1120_Alex
ANX7440_FLIP 29 15 P/N = 6-19-41001-019
R4940 Internal 45K ohm pull-down. FLIP VFB
L1 chooses 3.3uH; >500mA,
D02_1115_Alex 4.7K_04 ANX7440_I2C_ADR_SEL0 36 DCR<100 mOhm.
ANX7440_I2C_ADR_SEL1 35 I2C_ADR_SEL0 C10 C9
I2C_ADR_SEL1 C23 ESR< 20mOhm.
12 0.1u_25V_X5R_04 22u_6.3V_X5R_06
VGND
DP_E_AUX#
3.3V
GND_DCDC
I2C Mode 31 GND_DCDC
Internal DC-DC 0.9v
R486 XTAL_O
ADD:0x20(W),0x21 (R) 47
DCI_CLK C873
output: Maximum
R483 46
499K_1%_04
DCI debug interface DCI_DAT 30 500mA
P1.8V P1.8V P1.8V 100K_1%_04 XTAL_I
40
TEST_EN 15p_50V_NPO_04

3
2
DP_E_AUX_L#
AVSS_18
AVSS_25
AVSS_57

DP_E_AUX
AVSS_4

DP_E_AUX_L R477 X2 SPEC: 20PPM


DVSS

R453 R476 R475 1M_1%_04 FSX3M_24MHZ Signal GND and


*4.7K_04 *4.7K_04 *4.7K_04 GND_DCDC must be
R485 ANX7440QN-CB-R 6-07-18034-1A0
R484
separated. They
4
18
25
57
61

4
1
ANX7440_I2C_ADR_SEL0 C874
499K_1%_04 are connected at
ANX7440_I2C_ADR_SEL1
ANX7440_FLIP
100K_1%_04 a single point.
ANX7440_POW ER_EN R6 0_06
15p_50V_NPO_04
R7 0_06
R452 R9 R8
C26 FLIP: OP_MODE_1/O  MODE
A USB Typc-C Orientation: A
1u_6.3V_X5R_04

4.7K_04 0_04 0_04 GND_DCDC


0=normal, 1=flipped 00  Disabled
01  USB3
CC1 detection is normal 10  DP
or 11  USB3 + DP

ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
CC2 detection is flipped
2,24,29,42,44,49,50,52,53,56,59,60,61,73 3.3V
Compatible with 3.3V input. 37,55,62 1.8VA
Add 0521 Biaggi 10,23,30,58,61,62,78 NV3V3 Title
Add 0601 Biaggi
[72]USB TYPE-C_ANX7440_Retimer
Size Document Number Rev
A3 SCHEMATIC1 6-71-NH500-D02 D04

Date: W ednesday, December 05, 2018 Sheet 72 of 78


5 4 3 2 1

USB Type-C B - 71
Schematic Diagrams

PD Controller ANX7411
5 4 3 2 1

ANX7411

3.3V The DVDD_IO can be power supplied by 1.8V ~ 3.3V:


3.3V If AP or EC's IO type is 1.8V, select 1.8V power for DVDD_IO.
If AP or EC's IO type is 3.3V, select 3.3V power for DVDD_IO.

C23 C907 C22


1u_6.3V_X5R_02 0.1u_6.3V_X5R_02 1000p_50V_X7R_04 C908 C912
1u_6.3V_X5R_02 0.1u_6.3V_X5R_02 C913
D 1000p_50V_X7R_04 D

D02_1112_Alex

15

24

19
7
U3

AVDD33
AVDD33

DVDD_IO

DVDD_IO
To EC
VCONN_POWER is the power source for VCONN:
1) VCONN Voltage range [3.6V, 5.5V].
2) Internal VCONN Switch: Iout Max 400mA,Rdson Max 1.2 ohm.
2) VCONN Minimum power is 1W. If DP Alternate
Mode is supported, VCONN power is up to 1.5W.
D02_1113_Alex
B.Schematic Diagrams

8
9 AUXP
AUXN
R4937 0_04
21 11
23,35 MDP_E_HPD HPD SBU1 10
SBU2
14
R32 CC1 CCG2_CC1 42 5V
*100K_04
D02_1112_Alex C909 C911

Sheet 71 of 73 R4903
TEST_R 2
VCONN_POWER

CC2
16

13
CCG2_CC2
3.3V
42
10u_6.3V_X5R_06 0.1u_6.3V_X5R_02 C910
1000p_50V_X7R_04

31 GPP_K14_TEST_R TEST_R

PD Controller C
0_04
D02_1112_Alex
3.3V
ANX7411QN-AC-R
D02_1114_Alex
C

R35 R36

ANX7411 D02_1113_Alex R33


1.8K_1%_04 R31 26
1.8K_1%_04 1.8K_1%_04

MSTR_SDA_7440 72
INTP_OUT pin: interrupt output, active low.
1.8K_1%_04 M_SDA 3.3V Connect to AP or EC.
R4935 0_04
CFG_SDA 22 27
39 SMD_7411 CFG_SCL CFG_SDA M_SCL MSTR_SCL_7440 72 VBUS_USB_TYPE_C
39 SMC_7411 23
CFG_SCL
R4936 0_04
28 25 R34
4 SINK_CTRL INTP_OUT 4.7K_04
42 SOURCE_CTRL SOURCE_CTRL R41
INTP_OUT
INTP_OUT 35 348K_1%_04
3.3V 3 5
ROLE_SELECT pin: TEST_EN VBUS_SENSE
Logic 1: DRP Mode. R21
Logic 0: DFP Mode. 12 49.9K_1%_04
NC: UFP Mode. R19 20 VBUS_OCP
42 DISCHARGE_CTRL DISCHARGE_CTRL
4.7K_04

18
ROLE_SELECT
3.3V
1 6

VSS
R20 I2C_ADR_1 NC 17
B
*4.7K_04 NC B

R39

29
*4.7K_04

R40

72 ANX7440_POW ER_EN

0_04 I2C_ADR_1 pin: Connected to AP or EC as UART TXD:


1. Don点 t care before internal reset released.
R38 2. Used to config the I2C address as reset is released.
4.7K_04 3. Can be configured to UART output.
4. Can be configured to GPIO.

I2C_ADR_1pin:
1. The I2C address is determined approximately 300ns after internal RESET_N turns from 0 to 1,
this pin's input should be kept at a stable value during this period. Vout =50*Ibus*R28=0.5*Ibus
2. There are internal pull-down resistors on I2C_ADR_1 pin. 1. 0A<=Ibus<=5A
3. If external pull-up resistor is not populated, the I2C_ADR_1 is logic 0. 2. Vout[0V,2.5V]
4. If external pull-up is populated, the I2C_ADR_1 is logic 1.

I2C Address Selection:

A A
I2C_ADR_1 TCPC Address SPI Address EMTB Address EMRB Address Debug Address_1 Debug Address_2
(Wakeup address)

ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Logic 0(R19=DNP) 0x58 0x7E 0x7A 0x84 0x72 0x70

Logic 1(R19=4.7K) 0x54 0x64 0x68 0x6C 0x5C 0x70


Title
VBUS_USB_TYPE_C 42 [73] PD Controller ANX7411
1.8VA 37,55,62,72 Size Document Number Rev
5V
3.3V
29,42,44,49,50,52,55,60
2,24,29,42,44,49,50,52,53,56,59,60,61,72
Custom SCHEMATIC1 6-71-NH500-D02 D04

Date: W ednesday, December 05, 2018 Sheet 73 of 78

5 4 3 2 1

B - 72 PD Controller ANX7411
Schematic Diagrams

PER KEY Board

5 4 3 2 1

for 70 for 50

RGSW7
RGSW6
RGSW5
RGSW4
RGSW3
RGSW2
RGSW1
RGSW0
5VS

PER KEY LED RN8


100K_8P4R_04
8
7
6
1
2
3
ROUTR0
ROUTR1
ROUTR2
4
3
2
5
6
7
RN9
22_8P4R_04
RLED_R0
RLED_R1
RLED_R2
J_PERKB3
1
2
RLED_R0
RLED_R1
J_PERKB4
1
3.3VS RLED_R3 3 RLED_R2 2
PER KEY 5 4 ROUTR3 1 8 PER KEY
C1181 C1182 C1183 RLED_R4 4 RLED_R3 3
8 1 ROUTR4 4 5
RLED_R5 5 RLED_R4 4

10u_6.3V_X5R_06

0.1u_6.3V_X5R_02
MLCC Comm part

0.1u_6.3V_X5R_02
MLCC Comm part
RN11 7 2 ROUTR5 3 6 RN12

49
48
47
46
45
44
43
42
41
40
39
38
37
RLED_R6 6 RLED_R5 5
U48 100K_8P4R_04 6 3 ROUTR6 2 7 22_8P4R_04
RLED_R7 7 RLED_R6 6

PER KEY

PER KEY

PER KEY
PER KEY 5 4 ROUTR7 1 8 PER KEY

VSS
PWM15/GSW7/TACH1/GPB7
PWM14/GSW6/TACH0/GPB6
PWM13/GSW5/GPB5
PWM12/GSW4/GPB4
PWM11/GSW3/GPB3
PWM10/GSW2/GPB2
PWM9/GSW1/GPB1
PWM8/GSW0/GPB0
VSTBY33
VSS
SSCE1#/PWM7/GPA7
PGND
D RLED_R8 8 GND1 RLED_R7 7 D
8 1 ROUTR8 4 5
RLED_R9 9 GND2 RLED_R8 8 GND1
RN13 7 2 ROUTR9 3 6 RN14
6 3 2 7 RLED_R10 10 RLED_R9 9 GND2
100K_8P4R_04 ROUTR10 22_8P4R_04
5 4 1 8 RLED_R11 11 RLED_R10 10
PER KEY ROUTR11 PER KEY GND
1 36 8 1 ROUTR12 4 5 RLED_R12 12 RLED_R11 11 GND
SMCLK0/GPC0 SMOSI1/PWM6/GPA6 RLED_R13 13 RLED_R12 12
2 35 RN15 7 2 ROUTR13 3 6 RN10
SMDAT0/GPC1 SSCK1/PWM5/GPA5 RLED_R14 14 RLED_R13 13
GND GND GND 3 34 100K_8P4R_04 6 3 ROUTR14 2 7 22_8P4R_04
23,47 SMC_VGA_THERM RSMC_VGA_THERM 4 SMCLK1/GPC2 GLK1/SMISO1/PWM4/GPA4 33 RLE_MBI 5 4 1 8 RLED_R15 15 RLED_R14 14
PER KEY ROUTR15 PER KEY
23,47 SMD_VGA_THERM RSMD_VGA_THERM SMDAT1/GPC3 SSCE0#/PWM3/GPA3 RSDI0_MBI 16 RLED_R15 15
5 32
6 TXD/GPC4 SMOSI0/PWM2/GPA2 31 RDCLK_MBI 8 1 ROUTG0 4 5 RLED_G0 17 16
RXD/GPC5 SSCK0/PWM1/GPA1 RGCLK_MBI RLED_G1 18 RLED_G0 17
7 30 RN16 7 2 ROUTG1 3 6 RN17
VSTBY33 GLK0/SMISO0/PWM0/GPA0 22_8P4R_04 RLED_G2 19 RLED_G1 18
RVCOREB2 8 29 3.3VS 100K_8P4R_04 6 3 ROUTG2 2 7
9 VCOREB2 VSTBY33 28 RLED_G3 20 RLED_G2 19
RWRST#
10 WRST# IT8295FN GPD0 27
PER KEY 58 4
1
ROUTG3 1
4
8
5
PER KEY RLED_G4 21 RLED_G3 20
ROUTG4
VSS VSTBY33 RLED_G5 22 RLED_G4 21
C1184 R796 C1185 11
GPE0 QFN-48 GPG0
26 RN18 7 2 ROUTG5 3 6 RN19
RLED_G6 23 RLED_G5 22
12 25 100K_8P4R_04 6 3 ROUTG6 2 7 22_8P4R_04
GPE1 GPF7 C1186 C1187 RLED_G7 24 RLED_G6 23
PER KEY 85 4 ROUTG7 1 8 PER KEY

0.1u_6.3V_X5R_02
MLCC Comm part

10K_04

0.1u_6.3V_X5R_02
MLCC Comm part
RLED_G7 24

PER KEY

PER KEY
RLED_G8 25
PER KEY
1 ROUTG8 4 5

0.1u_6.3V_X5R_02
MLCC Comm part

0.1u_6.3V_X5R_02
MLCC Comm part
VSTBY33
PER KEY
PER KEY RLED_G8 25

VCOREB
RN20 7 2 ROUTG9 3 6 RN21 RLED_G9 26

B.Schematic Diagrams
22_8P4R_04 RLED_G10 27 RLED_G9 26
100K_8P4R_04 6 3 ROUTG10 2 7

GPE2
GPE3
GPE4
GPE5
GPF4

GPF5
GPF6
RLED_G10 27

VSS
RLED_G11 28
PER KEY 5 4 1 8

DM
ROUTG11 PER KEY

DP
RLED_G12 29 RLED_G11 28
8 1 ROUTG12 4 5
RLED_G13 30 RLED_G12 29
PER KEY IT8295FN-56A/BX RN22 7 2 ROUTG13 3 6 RN23
30

13
14
15
16
17
18
19
20
21
22
23
24
RLED_G14 31 RLED_G13
100K_8P4R_04 6 3 ROUTG14 2 7 22_8P4R_04
RLED_G15 32 RLED_G14 31
Thermal Pad must PER KEY 5 4 ROUTG15 1 8 PER KEY 33 RLED_G15 32
GND 3.3VS GND has 9 vias
RPERKB_ID1#_R 20180502 34 33
GND GND Follow common design
RPERKB_ID2#_R 35 34
GND
36 35
37 36

Sheet 72 of 73
20180419 Delete MCU pin USB_P9 32 38 37
USB_P9# 32 2A 39 38
RVCOREB USB2.0 PORT8 5VS 40 2A 39
5VS 40
C C1189 FP201H-040S10M C
C1188 PCB Footprint = FP201-040X1-0M C1190 FP201H-040S10M
4.7u_6.3V_X5R_04

PER KEY Board


MLCC Comm part P/N = 6-20-94K20-140 PCB Footprint = FP201-040X1-0M
0.1u_6.3V_X5R_02 NH70 PER KEY 4.7u_6.3V_X5R_04
RGSW5_R NH70 PER KEY P/N = 6-20-94K20-140
PER KEY RGSW1_R
RGSW4_R
MLCC Comm part NH50 PERKEY
MLCC Comm part NH50 PERKEY
RGSW0_R GND
GND GND

3
D

3
D
5VS
RGSW4 5G Q71B
RGSW0 5G Q70B J_PERKB1
S MTDK3S6R RLED_B0
S MTDK3S6R 8 1 ROUTB0 4 5 J_PERKB2

4
6
4
D
PER KEY 1 RLED_B0

6
D RN24 7 2 ROUTB1 3 6 RN25 RLED_B1
PER KEY 2 RLED_B1 1
2G 100K_8P4R_04 6 3 ROUTB2 2 7 22_8P4R_04 RLED_B2
RGSW5 RLED_B3 3 RLED_B2 2
RGSW1 2G PER KEY 85 4 ROUTB3 1 8 PER KEY RLED_B4
Q71A S GND 4 RLED_B3 3
S 1 ROUTB4 4 5

1
Q70A 1 GND
MTDK3S6R RLED_B5 5 RLED_B4 4
MTDK3S6R RN26 7 2 ROUTB5 3 6 RN27
PER KEY 6 RLED_B5 5
3.3VS PER KEY 100K_8P4R_04 6 3 ROUTB6 2 7 22_8P4R_04 RLED_B6
RLED_B7 7 RLED_B6 6
GND PER KEY 58 4
1
ROUTB7 1
4
8
5
PER KEY RLED_B8 8 NC1 RLED_B7 7
GND RGSW7_R ROUTB8
RGSW3_R RLED_B9 9 NC2 RLED_B8 8 NC1
RSDI1_MBI RGSW6_R RN28 7 2 ROUTB9 3 6 RN29
R797 12K_04 PER KEY RGSW2_R 10 RLED_B9 9 NC2
RSDI2_MBI 100K_8P4R_04 6 3 ROUTB10 2 7 22_8P4R_04 RLED_B10
R798 12K_04 PER KEY RLED_B11 11 RLED_B10 10
RGCLK_MBI R799 PER KEY 5 4 ROUTB11 1 8 PER KEY RLED_B12 12
GND
RLED_B11 11 GND
1.5K_04 PER KEY 8 1 ROUTB12 4 5

3
D 13 RLED_B12 12
3

RDCLK_MBI R800 1.5K_04 D RN30 7 2 ROUTB13 3 6 RN31 RLED_B13


RSDI0_MBI R801 PER KEY 14 RLED_B13 13
1.5K_04 PER KEY 5G 100K_8P4R_04 6 3 ROUTB14 2 7 22_8P4R_04 RLED_B14
RLE_MBI RGSW6 Q73B RLED_B15 15 RLED_B14 14
R802 1.5K_04 PER KEY RGSW2 5G Q72B PER KEY 5 4 ROUTB15 1 8 PER KEY
S MTDK3S6R
S MTDK3S6R 16 RLED_B15 15

4
6
4

20180502 Follow common design D


PER KEY 20180502 17 16
6

D RGSW0_R
PER KEY Follow common design
RGSW1_R 18 RGSW0_R 17
RGSW7 2G RGSW2_R 19 RGSW1_R 18
RGSW3 2G
S Q73A S GND RGSW3_R 20 RGSW2_R 19

1
Q72A GND
20
1

MTDK3S6R RGSW4_R 21 RGSW3_R


MTDK3S6R
PER KEY RGSW5_R 22 RGSW4_R 21
2018/1/18_for white light adjust, PER KEY RGSW6_R 23 RGSW5_R 22
3.3VS
B R857 change to 1K GND RGSW7_R 24 RGSW6_R 23 B
R857 change to 806_1%_04 GND
25 RGSW7_R 24
GCLK length < 2 inch 25
RDCLK_MBI 47,74 PERKB_ID1#_R RPERKB_ID1#_R 8 RN32 1 RPERKB_ID1# 26
RGCLK_MBI 47,74 PERKB_ID2#_R RPERKB_ID2#_R 7 2 RPERKB_ID2# 27 47,74 PERKB_ID1#_R RPERKB_ID1#_R 8 RN33 1 RPERKB_ID1# 26
RLE_MBI 47,48,74 PERKB-DET#_R RPERKB-DET#_R 6 3 28 47,74 PERKB_ID2#_R RPERKB_ID2#_R 7 2 RPERKB_ID2# 27
RPERKB-DET#
RSDI0_MBI RSDI1_MBI RSDI2_MBI RR-EXT2_MBI 29 47,48,74 PERKB-DET#_R RPERKB-DET#_R 28

GND
5 4 6 3 RPERKB-DET#
RR-EXT0_MBI RR-EXT1_MBI 30 29

GND
5 4
100_8P4R_04 30
VDD3 FP225H-030S10M 100_8P4R_04
R805 NH70 PER KEY VDD3 FP225H-030S10M
C1192 C1193 P/N = 6-20-94K20-130
C1191 R803
MLCC Comm part
R804
MLCC Comm part PCB Footprint = fp225h-030gxxm NH50 PERKEY P/N = 6-20-94K20-130
680_1%_04
24
23
22
21
20
19

MLCC Comm part 0.1u_6.3V_X5R_02 0.1u_6.3V_X5R_02 PCB Footprint = fp225h-030gxxm


8 RN34 1 NH70 PER KEY
24
23
22
21
20
19

24
23
22
21
20
19

0.1u_6.3V_X5R_02 1K_1%_04 806_1%_04 PER KEY


PER KEY PER KEY 7 2 8 RN35 1 NH50 PERKEY
PER KEY PER KEY PER KEY
DCLK

GCLK
SDO
SDI
VDD
R-EXT
DCLK

GCLK
SDO

DCLK

GCLK
SDO
SDI
VDD
R-EXT

SDI
VDD
R-EXT

6 3 7 2
GND GND 5 4 6 3
GND GND GND GND 1 18 5 4
ROUTB15
1 18 ROUTR15 1 18 ROUTG15 LE OUT15
LE OUT15 LE OUT15 ROUTB0 2 17 ROUTB14 *100K_8P4R_04
ROUTR0 2 17 ROUTR14 ROUTG0 2 17 ROUTG14 OUT0 OUT14
OUT0 OUT14 OUT0 OUT14 ROUTB1 3 MBIA045OUT13 16 ROUTB13 NH70 PER KEY *100K_8P4R_04
ROUTR1 3 MBIA045OUT13 16 ROUTR13 ROUTG1 3 MBIA045OUT13 16 ROUTG13 OUT1
OUT1 OUT1 ROUTB2 4 15 ROUTB12 NH50 PERKEY
ROUTR2 4
OUT2 QFN-24 OUT12 15 ROUTR12 ROUTG2 4
OUT2 QFN-24 OUT12 15 ROUTG12
ROUTB3 5 OUT2 QFN-24 OUT12 14 ROUTB11
ROUTR3 5 14 ROUTR11 ROUTG3 5 14 ROUTG11 OUT3 OUT11
OUT3 OUT11 OUT3 OUT11 ROUTB4 6 13 ROUTB10
ROUTR4 6 13 ROUTR10 ROUTG4 6 13 ROUTG10 OUT4 OUT10
OUT4 OUT10 OUT4 OUT10
PGND
OUT5
OUT6
OUT7

OUT8
OUT9
PGND

PGND

GND
OUT5
OUT6
OUT7

OUT8
OUT9

OUT5
OUT6
OUT7

OUT8
OUT9
GND

GND

U51
7
8
9
10
25
11
12

U49 U50
7
8
9
10
25
11
12

7
8
9
10
25
11
12

MBIA045GFN-A
MBIA045GFN-A MBIA045GFN-A
PER KEY PER KEY PER KEY
Thermal Pad must Thermal Pad must
Thermal Pad must has 5 vias
ROUTG5
ROUTG6
ROUTG7

ROUTG8
ROUTG9
ROUTR5
ROUTR6
ROUTR7

ROUTR8
ROUTR9

ROUTB5
ROUTB6
ROUTB7

ROUTB8
ROUTB9

has 5 vias has 5 vias


GND GND GND

A A

ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Title
[74] PER KEY BOARD_R
Size Document Number Rev
4,23,24,31,32,34,37,40,41,43,45,47,48,49,50,51,54,55,57,58,59,60,61,62,65,77,78 VDD3
27,30,32,44,45,47,48,49,77,78 5VS
SCHEMATIC1
Custom 6-71-NH500-D02 D01
8,9,23,24,27,29,30,31,32,33,34,35,36,39,40,41,43,44,45,47,49,50,54,61,77 3.3VS Date: Wednesday, December 05, 2018 Sheet 74 of 78
5 4 3 2 1

PER KEY Board B - 73


Schematic Diagrams

DGPU Power Measurement

5 4 3 2 1

VIN VIN_45491 Output power MEASUREMENT


PJ55
2 1 5A
5A
5mm
C1271
*0.01u_50V_X7R_04 C1272 C1273
D D

10u_25V_X6S_08
8

10u_25V_X6S_08
3 7
R559 2 6
100K_04 1 5 D02A_1130_Alex
R4941
20K_04 Q87

4
MEP4435Q8

R4942 0_04

D
41,47,50,55 SLP_SUS#
R4943 Q84
*0_04 G
42,47,49,51,78 DD_ON 2SK3018S3 NV3V3 VDD3

S
B.Schematic Diagrams

R669
0_04
R4938 Total Power
*0_04

D02_102618_Alex_NV OVR-M VIN_45491


U31 PWR_SRC_NV_FB
NVVDD
Sheet 73 of 73
QFN32 0.400
C1031 RS2
COMMON D02_1110_Alex
1u_6.3V_X6S_04 1 4
PWR_SRC_VINP_R R570 75K_1%_04 PFM_CH1_BS_IN1 3 27 U812_VCC 2 3
BS_IN1 VCC
RL1632T4F-B-R005-FNH
COMMON PWR_SRC_NV_FB PWR_SRC_NV

GND
C1033 1000p_50V_X7R_02 R547 649_1%_04

DGPU Power
C1257 47p_25V_NPO_02
1206 1%
GND RS1
PWR_SRC_NV_VINP_R R549 75K_1%_04 PFM_CH1_BS_IN2 6 2 PFM_CH1_SH_IN_P1 R571 100_1%_04 PWR_SRC_VINP_R 1 4
BS_IN2 SH_P1
C 2 3 C

Measurement PFM_CH1_SH_IN_N1 PWR_SRC_VINN_R

GND
C1011 1000p_50V_X7R_02 R548 649_1%_04 SH_N1 1 R572 0_04 RL1632T4F-B-R005-FNH
COMMON
1% 1206

11 5 PFM_CH1_SH_IN_P2 R545 100_1%_04 PWR_SRC_NV_VINP_R <Function>


BS_IN3 SH_P2

4 PFM_CH1_SH_IN_N2 R546 0_04 PWR_SRC_NV_VINN_R


SH_N2
D02_102618_Alex_NV OVR-M
U812_VCC
R4944 0_04 C1259 47p_25V_NPO_02
14 BS_IN4 SH_P3 12

13 D02_1110_Alex
SH_N3
D02_102618_Alex_NV OVR-M

R543 *0_04 PFM_FILTER_GND_FET 9 15


GND_FET SH_P4

R682 287_1%_04 32 SH_O1 SH_N4 16


U812_VCC
GND PFM_FILTER_SH_O1 ADC_IN_P 23
C1032 15000p_50V_X7R_06
ADC_IN_N 23
1V8_AON 5VS GND R544 287_1%_04 7 20 ADC_IN_P R541 0_04 PFM_ADC_IN_P_RC C1009 47p_25V_NPO_02
SH_O2 DIFF_P GND
R568
C1012 15000p_50V_X7R_06 PFM_FILTER_SH_O2 19 ADC_IN_N R542 0_04 PFM_ADC_IN_N_RC C1010 47p_25V_NPO_02
DIFF_N GND 10K_1%_04

R672 R664 10 SH_O3


10K_1%_04 1K_1%_04 30 PFM_PF_BSOK_R
BS_OK

17 SH_O4 NC 8

NC
18
B B
R569
21 49.9K_1%_04
NC

R567 0_04 PFM_ADC_MUX_SEL_R 29 31 Apply P/N


23 GPIO28_OC_WARN# MUX_SEL NC
VIN R4948 0_04 OVRM_EN 28 EN

PFM_PF_BSOK_RC
23 PFM_BG_REF_OUT R564 243K_1%_04
BG_REF_OUT
PFM_SKIP_R 25 SKIP
24 PFM_BS_REF
BS_REF
R4945 R178 365K_1%_04
PFM_ADC_FILTER_MODE 26 22 PFM_CM_REF_IN R562
MODE CM_REF_IN
470K_04 90.9K_1%_04
R4947 R565 R177 R563 C574
10K_1%_04 *10K_1%_04 680K_1%_04 10K_1%_04 *1000p_50V_X7R_04
GND 33
R4946

C
D02_102718_Alex Q45
2
C

D55
BTN3904 B
D54 GND
100K_04 M-SOT23-CBE
*V15AVLC0402 GND NCP45491XMNTWG
D

E
ZD5231BS2

C572 C573 C1030


Q88
A

G
1

1000p_50V_X7R_04

1000p_50V_X7R_04

1000p_50V_X7R_04
2SK3018S3 DD_ON 42,47,49,51,78
S

GND
GND 4,23,24,31,32,34,37,40,41,43,45,47,48,49,50,51,54,55,57,58,59,60,61,62,65,74,77 VDD3
GND
GND 29,42,44,49,50,52,55,60,73 5V
27,30,32,44,45,47,48,49,74,77 5VS
55,60,61 PWR_SRC_NV_FB
GND 29,34,49,50,51,52,53,54,55,56,57,59 VIN
A A
10,23,30,58,61,62 NV3V3
10,12,13,14,15,17,18,20,21,22,23,24,25,58,61,62 1V8_AON
GND

ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
D02A_1130_Alex Title
[78] DGPU Power Measurement
Size Document Number R ev
Custom SCHEMATIC1 6-71-NH500-D02 D02

Date: Wednesday, December 05, 2018 Sheet 78 of 78

5 4 3 2 1

B - 74 DGPU Power Measurement

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