NM A161

A B C D E
1 1
NM-A161 Rev1.0 Schematic 2
Intel Haswell Processor with DDRIII + Lynx point PCH

nVIDIA N14P-GV2/ N14M-GL
2013-07-11 Rev 1.0
3 3
4 4
A
Dr-Bios.com
B
Security Classification
Issued Date 2012/12/05
LC Future Center Secret Data
Deciphered Date 2014/12/05
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C D
Title
Date:
Cover Page
Size Document Number

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
!"#$%&'()*+*
Thursday, July 11, 2013
E
Sheet 1 of 57
Rev
1.0
A B C D E
N14P-GV2 2G
N14M-GL 1G PCI-Express 16X Gen3 Intel CPU
VRAM 128M*16 *4
VRAM 256M*16 *4
PEG 0~7 Haswell Memory BUS (DDRIII) DDR3-SO-DIMM X2
Page 23,24,25,26,27,28,29,30,31,32,33
Dual Channel BANK 0, 1, 2, 3
1
rPGA-989 1
1.35V DDRIIIL 1066/1333/1600 MT/s

HDMI Conn. HDMI 37.5mm*37.5mm UP TO 16G
1.65GT/s
HDMI1.4b Page 36
Page 5,6,7,8,9,10,11
eDP DP
eDP Conn. 3.3V 5.4GT/s Docking Conn
Page 35 USB 3.0 Port 1
Page 51
DMI *4 FDI *2
5GT/s 5GT/s
CRT Conn. CRT USB 3.0 USB Left

USB 3.0 Port 2
Page 35
5V 500MB/S USB 3.0 Port 5
Small Board
Page 50
2 Realtek RTL8111G JRJ45 Conn. PCIe Gen1

1.5V 2.5GT/s
Intel PCH 2
LAN Board PCIe port 4 Page 42

Lynx point USB 2.0 Touch panel USB Right Int. Camera
USB 2.0 Port 5
Realtek RTS5227 JUCR Conn. PCIe Gen1 5V 60MB/S USB 2.0 Port 4 USB 2.0 Port 13
USB Charge Port 1.5V 2.5GT/S Page 51 Sub Board Page 50 Page 34
Card Reader Board PCIe port 3 Page 43
ODD Board For 15" SATA ODD For 15" SATA Gen1 Port2 695 ball FCBGA
Card Reader Board
SATA Port 2
Page 44
5V 3GHz(150MB/s) 20mm*20mm USB 2.0
PCIeMini Card mSATA SSD
5V 60MB/S
WLAN SATA Port 0
PCIe Port 5
SATA ODD For 14" PCIe Gen1 USB 2.0 Port 10 Page 37
SATA Port 2 5V 2.5GT/S Page 37 PCIeMini Card
Page 45
WWAN
SATA Gen3 USB 2.0 Port 11
SATA HDD 5V 6GHz(600MB/s) Page 38
SATA Port 1
SATA Gen3 Port 0
Page 44 5V 6GHz(600MB/s)
3 3
SPK Conn.
HD Audio Codec Page 46
SPI ROM 3.3V 24MHz
Power Circuit DC/DC SPI BUS Page 14,15,16,17,18,19,20,21,22 COX 20751
Page 52,53,54,55,56,57,
(4MB+8MB) 3.3V 33MHz SMBus Page 45 Int. Comb Conn.
58,59,60,61,62 Page 17 (Ext MIC & HP)
LPC BUS Page 34
3.3V 33MHz
DC/DC Interface CKT.
Page 51
Debug Port EC
Finger Print Conn Page 45 PS2 Click Pad Track Point
Page 56 ITE IT8586E-CX SMBus
Page 47 SMBus Port3
Page 47 Page 48
POWER/B Conn.
Page 40 ADC Int. K/B
SMBus
Thermal Sensor Security EEPROM
4
ODD/B Conn. G-Sensor EMC SMBus
1403Port3 4
page 41 SMBus Port3
Int.KBD Page 40 Page 41
LIS34ALTR
Dr-Bios.com
Page 47 Page 46
Touch Pad Conn SIM Conn
Page 56 Page 54
Security Classification LC Future Center Secret Data Title
Block Diagram
Issued Date 2012/12/05 Deciphered Date 2014/12/05
Click Pad Conn Track Point Conn THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
Page 55 Page 53 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
!"#$%&'()*+*
Date: Thursday, July 11, 2013 Sheet 2 of 57
A B C D E
A B C D E
Voltage Rails ( O --> Means ON , X --> Means OFF )

SIGNAL
+5VS STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
+3VS
Power Plane Full ON HIGH HIGH HIGH HIGH ON ON ON ON
+1.5VS
+VCCSA S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
1
+V1.5S_VCCP 1
S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
+CPU_CORE
+3VALW
+VGA_CORE S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
B+ +1.5V
+GFX_CORE
S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+5VALW +1.8VS
+1.05VS
State +0.75VS
+3.3VS_VGA
+1.5VS_VGA
+1.05VS_VGA
USB Port Table BOM Structure Table
4 External BOM Structure BTO Item
USB 2.0 USB 3.0 Port
USB Port HDMI part
HDMI@
S0 O O O O Camera USB charger part
0 CHG@
1
XHCI NOCHG@ No USB charger part
1 USB Port (Right Side)
2 CMOS@ NV noCamera
CMOS CG6 support
part part
S3 O O O X EHCI1
2 USB Port (Left Side) 8171@ QCA8171 LAN part
3
2 3 8171S@ QCA8171 LAN surge part 2
4 SURGE@ QCA8171&8172 LAN surge part
S5 S4/AC Only O O X X 4 X76@ X76 Level part for VRAM
5 USB Port (Right Side) GC6@ NV CG6 support part
6
S5 S4 NOGC6@
Battery only O X X X 7 AOAC@ AOAC support part
EHCI2 8 KBL@ K/B Light part

9 ME@ ME part
S5 S4 10 Mini Card(WLAN) SLI@ For SLI function part
AC & Battery X X X X 11 DS3@ Deep S3 support part
don't exist 12 S3@ For S3 function part
13 Blue Tooth
GT@ NV chip part
@ Unpop
EDP@ Support EDP panel function
SMBUS Control Table PCIE PORT LIST daul@ Support daul channel panel function
Main 2nd WLAN Thermal PCH CP Port Device

3
SOURCE VGA VGA BATT IT8580E SODIMM WiMAX Sensor Module 3
1 LAN
EC_SMB_CK1 IT8580E 2 WLAN
EC_SMB_DA1 +3VALW X X V X X X X X X 3
+3VALW 4 Card Reader
EC_SMB_CK2 IT8580E 5
EC_SMB_DA2 +3VS
V V X X X X V V X 6
+3VS +3VS +3VS +3V_PCH
7
PM_SMBCLK PCH 8
PM_SMBDATA +3V_PCH
X X X X V V X V V
+3VS +3VS +3V_PCH +3VS
Address
EC SM Bus1 address EC SM Bus2 address PCH SM Bus address ZZZ1
4 4
Device Device Address Device Address
Dr-Bios.com
Smart Battery 0001 011X b Thermal Sensor EMC1403-2 1001_101xb DDR DIMM0 1001 000Xb
DA80000TX00
Master VGA 0x9E DDR DIMM2 1001 010Xb
Slave VGA 0x9C
Notes List
Rev
Custom 1.0
!"#$%&'()*+*
A B C D E
5 4 3 2 1
Hot plug detect for IFP link E

Performance Mode P0 TDP at Tj = 102 C* (GDDR5)
FBVDDQ PCI Express I/O and I/O and Other
VGA and GDDR5 Voltage Rails (N13Px GPIO) GPU Mem NVCLK FBVDD (GPU+Mem) (1.05V) PLLVDD PLLVDD
(4) (1,5) /MCLK NVVDD (1.35V) (1.35V) (6) (1.8V) (1.05V) (3.3V)
GPIO I/O ACTIVE Function Description Products (W) (W) (MHz) (V) (A) (W) (A) (W) (A) (W) (mA) (W) (mA) (W) (mA) (W) (mA) (W)
GPIO0 OUT - GPU VID4 N13X

128bit TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
D
1GB D
GPIO1 OUT - GPU VID3 GDDR5
GPIO2 OUT - VGA_BL_PWM

Physical Logical Logical Logical Logical
Strapping pin Power Rail Strapping Bit3 Strapping Bit2 Strapping Bit1 Strapping Bit0
GPIO3 OUT - VGA_ENVDD ROM_SCLK +3VS_VGA PCI_DEVID[4] SUB_VENDOR SLOT_CLK_CFG PEX_PLL_EN_TERM
GPIO4 OUT - VGA_ENBKL ROM_SI +3VS_VGA RAM_CFG[3] RAM_CFG[2] RAM_CFG[1] RAM_CFG[0]
ROM_SO +3VS_VGA FB[1] FB[0] SMB_ALT_ADDR VGA_DEVICE
GPIO5 OUT - GPU VID1
STRAP0 +3VS_VGA USER[3] USER[2] USER[1] USER[0]
GPIO6 OUT - GPU VID2 STRAP1 +3VS_VGA 3GIO_PAD_CFG_ADR[3] 3GIO_PAD_CFG_ADR[2] 3GIO_PAD_CFG_ADR[1] 3GIO_PAD_CFG_ADR[0]
STRAP2 +3VS_VGA PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0]
GPIO7 OUT - DPRSLPVR_VGA
STRAP3 +3VS_VGA SOR3_EXPOSED SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED
GPIO8 I/O - Thermal Catastrophic Over Temperature STRAP4 +3VS_VGA RESERVED PCIE_SPEED_ PCIE_MAX_SPEED DP_PLL_VDD33V
CHANGE_GEN3
GPIO9 OUT - GPIO9
Device ID setting I2C Slave addrees ID
GPIO10 OUT - Memory VREF Control N13P-GT SMB_ALT_ADDR
(28nm) 0x0FDB 0 0x9E
(ROM_SO Bit 1)
C C
1 0x9C
GPIO12 IN AC Power Detect Input (10K pull High)
GPIO14 OUT - FB_CLAMP_TOGGLE_REQ#

GPU ROM_SO ROM_SCLK STRAP0 STRAP1 STRAP2 STRAP3 STRAP4
GPIO15 IN N/A (100K pull low)
PU 10K PU 25K PU 45K PD 35K PD 10K PU 5K PD 10K Master
GPIO16 OUT - FRMLCK# N13P-GT1
28nm PU 20K PU 25K PU 45K PD 35K PD 10K PD 5K PD 10K Slave
GPIO17 IN N/A
GPIO18 IN - dGPU_HDMI_HPD
GPIO19 IN - HPD_IRQ
GPU N13P-GT
FB Memory (GDDR5) ROM_SI
Samsung K4G10325FG-HC04
B
+3VS_VGA 2500MHz B
32Mx32 PD 45K
+VGA_CORE
Hynix H5GQ1H24BFR-T2C
tNVVDD >0 2500MHz
+1.5VS_VGA 32Mx32 PD 35K
tFBVDDQ >0
Samsung K4G20325FD-FC04
+1.05VS_VGA 2500MHz
tPEX_VDD >0 64Mx32 PD 30K
1. all power rail ramp up time should be larger than 40us

Hynix H5GQ2H24MFR-T2C
2500MHz
64Mx32 PD 25K
Other Power rail
+3VS_VGA
A A
Tpower-off <10ms
5
Dr-Bios.com
1.all GPU power rails should be turned off within 10ms
2. Optimus system VDD33 avoids drop down earlier than NVDD and FBVDDQ
4
3 2
Custom
Date:
Title
VGA Notes List

!"#$%&'()*+*
1
Sheet 4 of 57
Rev
1.0
CAD Note:
Trace width=12 mils ,Spacing=15mils
Max length= 400 mils.
JCPU1A ME@Haswell rPGA EDS
PCIE_CRX_GTX_N[7:0] <23>
E23 PEG_COMP
<15> DMI_CRX_PTX_N[3:0] PEG_RCOMP M29 PCIE_CRX_GTX_N0
DMI_CRX_PTX_N0 D21 PEG_RXN_0 K28 PCIE_CRX_GTX_N1
DMI_CRX_PTX_N1 C21 DMI_RXN_0 PEG_RXN_1 M31 PCIE_CRX_GTX_N2
DMI_CRX_PTX_N2 B21 DMI_RXN_1 PEG_RXN_2 L30 PCIE_CRX_GTX_N3
DMI_CRX_PTX_N3 A21 DMI_RXN_2 PEG_RXN_3 M33 PCIE_CRX_GTX_N4
<15> DMI_CRX_PTX_P[3:0] DMI_RXN_3 PEG_RXN_4 L32 PCIE_CRX_GTX_N5
DMI_CRX_PTX_P0 D20 PEG_RXN_5 M35 PCIE_CRX_GTX_N6
PEG
DMI_CRX_PTX_P1 C20 DMI_RXP_0 PEG_RXN_6 L34 PCIE_CRX_GTX_N7
DMI_CRX_PTX_P2 B20 DMI_RXP_1 PEG_RXN_7 E29
DMI_CRX_PTX_P3 A20 DMI_RXP_2 PEG_RXN_8 D28
<15> DMI_CTX_PRX_N[3:0]
DMI
DMI_RXP_3 PEG_RXN_9 E31
DMI_CTX_PRX_N0 D18 PEG_RXN_10 D30
DMI_CTX_PRX_N1 C17 DMI_TXN_0 PEG_RXN_11 E35
DMI_CTX_PRX_N2 B17 DMI_TXN_1 PEG_RXN_12 D34
DMI_CTX_PRX_N3 A17 DMI_TXN_2 PEG_RXN_13 E33
<15> DMI_CTX_PRX_P[3:0] DMI_TXN_3 PEG_RXN_14 PCIE_CRX_GTX_P[7:0] <23>
E32
DMI_CTX_PRX_P0 D17 PEG_RXN_15 L29 PCIE_CRX_GTX_P0
DMI_CTX_PRX_P1 C18 DMI_TXP_0 PEG_RXP_0 L28 PCIE_CRX_GTX_P1
DMI_CTX_PRX_P2 B18 DMI_TXP_1 PEG_RXP_1 L31 PCIE_CRX_GTX_P2
DMI_CTX_PRX_P3 A18 DMI_TXP_2 PEG_RXP_2 K30 PCIE_CRX_GTX_P3
DMI_TXP_3 PEG_RXP_3 L33 PCIE_CRX_GTX_P4
PEG_RXP_4 K32 PCIE_CRX_GTX_P5
PEG_RXP_5 L35 PCIE_CRX_GTX_P6
PEG_RXP_6 K34 PCIE_CRX_GTX_P7
PEG_RXP_7 F29
FDI_CSYNC H29 PEG_RXP_8 E28
<15> FDI_CSYNC
FDI
FDI_INT J29 FDI_CSYNC PEG_RXP_9 F31
<15> FDI_INT DISP_INT PEG_RXP_10 E30
PEG_RXP_11 F35
PEG_RXP_12 E34
PEG_RXP_13 F33
PEG_RXP_14 PCIE_CTX_C_GRX_N[7:0] <23>
D32
PEG_RXP_15 H35 PCIE_CTX_GRX_N0 CC1 DIS@ 0.22U_0402_10V6-K PCIE_CTX_C_GRX_N0
1 2
PEG_TXN_0 H34 PCIE_CTX_GRX_N1 CC2 DIS@ 1 2 0.22U_0402_10V6-K PCIE_CTX_C_GRX_N1
PEG_TXN_1 J33 PCIE_CTX_GRX_N2 CC3 DIS@ 0.22U_0402_10V6-K PCIE_CTX_C_GRX_N2
1 2
PEG_TXN_2 H32 PCIE_CTX_GRX_N3 CC4 DIS@ 1 2 0.22U_0402_10V6-K PCIE_CTX_C_GRX_N3
PEG_TXN_3 J31 PCIE_CTX_GRX_N4 CC5 DIS@ 1 2 0.22U_0402_10V6-K PCIE_CTX_C_GRX_N4
PEG_TXN_4 G30 PCIE_CTX_GRX_N5 CC6 DIS@ 1 2 0.22U_0402_10V6-K PCIE_CTX_C_GRX_N5
PEG_TXN_5 C33 PCIE_CTX_GRX_N6 CC7 DIS@ 1 2 0.22U_0402_10V6-K PCIE_CTX_C_GRX_N6
PEG_TXN_6 B32 PCIE_CTX_GRX_N7 CC8 DIS@ 1 2 0.22U_0402_10V6-K PCIE_CTX_C_GRX_N7
PEG_TXN_7 B31
PEG_TXN_8 A30
PEG_TXN_9 B29
PEG_TXN_10 A28
PEG_TXN_11 B27
PEG_TXN_12 A26
PEG_TXN_13 B25
PEG_TXN_14 PCIE_CTX_C_GRX_P[7:0] <23>
A24
PEG_TXN_15 J35 PCIE_CTX_GRX_P0 CC9 DIS@ 1 2 0.22U_0402_10V6-K PCIE_CTX_C_GRX_P0
PEG_TXP_0 G34 PCIE_CTX_GRX_P1 CC10 DIS@ 1 2 0.22U_0402_10V6-K PCIE_CTX_C_GRX_P1
PEG_TXP_1 H33 PCIE_CTX_GRX_P2 CC11 DIS@ 1 2 0.22U_0402_10V6-K PCIE_CTX_C_GRX_P2
PEG_TXP_2 G32 PCIE_CTX_GRX_P3 CC12 DIS@ 1 2 0.22U_0402_10V6-K PCIE_CTX_C_GRX_P3
PEG_TXP_3 H31 PCIE_CTX_GRX_P4 CC13 DIS@ 1 2 0.22U_0402_10V6-K PCIE_CTX_C_GRX_P4
PEG_TXP_4 H30 PCIE_CTX_GRX_P5 CC14 DIS@ 0.22U_0402_10V6-K PCIE_CTX_C_GRX_P5
1 2
PEG_TXP_5 B33 PCIE_CTX_GRX_P6 CC15 DIS@ 1 2 0.22U_0402_10V6-K PCIE_CTX_C_GRX_P6
PEG_TXP_6 A32 PCIE_CTX_GRX_P7 CC16 DIS@ 0.22U_0402_10V6-K PCIE_CTX_C_GRX_P7
1 2
PEG_TXP_7 C31
PEG_TXP_8 B30
PEG_TXP_9 C29
PEG_TXP_10 B28
PEG_TXP_11 C27
PEG_TXP_12 B26
PEG_TXP_13 C25
PEG_TXP_14 B24
PEG_TXP_15
Dr-Bios.com
5 4 3 2 1
D D
Reserve for VCCST
+1.05VS_PCH_VPROC
+VCCIO_OUT DDR3 COMPENSATION SIGNALS

1
RC3 1 2 62_0402_5% H_PROCHOT# @ CC41 CAD Note: Trace width=12~15 mil, Spcing=20 mils
Haswell rPGA EDS
0.1U_0402_25V6-K JCPU1B ME@ Max trace length= 500 mil
2
RC7 1 2 10K_0402_5% H_CPUPWRGD_R AP32 MISC AP3 SM_RCOMP0 RC2 1 2 100_0402_1%
SKTOCC SM_RCOMP_0 AR3 SM_RCOMP1 RC4 1 2 75_0402_1%
SM_RCOMP_1
DDR3
THERMAL
1 AN32 AP2 SM_RCOMP2 RC5 1 2 100_0402_1%
T1 CATERR SM_RCOMP_2
H_PECI AR27 AN3 H_DRAMRST# RC6 1 2 0_0402_5% DDR3_DRAMRST#
<48> H_PECI PECI SM_DRAMRST DDR3_DRAMRST# <11,12>
AK31
RC8 1 2 56_0402_5% H_PROCHOT#_R AM30 FC_AK31 AR29 XDP_PRDY# 1
<48> H_PROCHOT# PROCHOT PRDY T3 @ 1
H_THERMTRIP# AM35 AT29 XDP_PREQ# 1
<19> H_THERMTRIP# THERMTRIP PREQ T4 @
AM34 XDP_TCLK CC43
TCK AN33 XDP_TMS 1 330P_0402_50V7-K
TMS T5 @ 2
AM33 XDP_TRST#
JTAG
H_PM_SYNC AT28 TRST AM31 XDP_TDI 1
<15> H_PM_SYNC T6 @
PWR
RC10 1 2 0_0402_5% H_CPUPWRGD_R AL34 PM_SYNC TDI AL33 XDP_TDO
<19> H_CPUPWRGD
SM_DRAMPWROK AC10 PWRGOOD TDO AP33 XDP_DBRESET#
ESD
RC11 1 2 0_0402_5% CPU_PLTRSTIN# AT26 SM_DRAMPWROK DBR
Buffered Reset to CPU, 1.5V <19> PLTRST_PROC# PLTRSTIN AR30 TP closer to CPU
BPM_N_0 AN31
RC12 1 2 0_0402_5% CPU_DPLL# G28 BPM_N_1 AN29 XDP Connector reserve test point
<16> CLK_CPU_DPLL# DPLL_REF_CLKN BPM_N_2
CLOCK
C RC13 1 2 0_0402_5% CPU_DPLL H28 AP31 C
<16> CLK_CPU_DPLL DPLL_REF_CLKP BPM_N_3 +1.05VS
135MHz <16> CLK_CPU_SSC_DPLL# RC14 1 2 0_0402_5% CPU_SSC_DPLL# F27 AP30
RC15 1 2 0_0402_5% CPU_SSC_DPLL E27 SSC_DPLL_REF_CLKN BPM_N_4 AN28
<16> CLK_CPU_SSC_DPLL SSC_DPLL_REF_CLKP BPM_N_5
<16> CLK_CPU_DMI# CLK_CPU_DMI# D26 AP29 XDP_TDO RC16 1 2 51_0402_1%
CLK_CPU_DMI E26 BCLKN BPM_N_6 AP28
100 MHz PCIe 3.0 <16> CLK_CPU_DMI BCLKP BPM_N_7
INTEL_HASWELL_HASWELL 2 OF 9 XDP_TCLK RC17 1 2 51_0402_1%
XDP_TRST# RC18 1 2 51_0402_1%
+3VS
XDP_DBRESET# RC9 1 2 1K_0402_1%
PU/PD for JTAG signals

Place R closer to CPU
B B
SM_DRAMPWROK Topology for platforms supporting Deep S3

+3V_PCH +3V_PCH +3V_PCH +1.35V
1
1
@
RC19 RC20 CC17 RC21
200_0402_1% 100K_0402_5% 0.1U_0402_25V6-K 1.8K_0402_1%
2 Close to JCPU. AC10
2
2
5
1
P
B 4 DRAMPWROK_AND RC22 1 2 0_0402_5% SM_DRAMPWROK

2 O SM_DRAMPWROK
<15> DRAMPWROK A
G
SM_DRAMPWROK rise and fall time must be < 50ns

1
UC1 1
measured between VDDQ *0.15 and VDDQ *0.47.
3
74AHC1G09GW_TSSOP5
RC23 CC44
3.3K_0402_1% 330P_0402_50V7-K
A RC24 1 @ 2 0_0402_5% 2 A
2
ESD
5
Dr-Bios.com 4
Deciphered Date
3 2
Date:
2014/12/05

Custom

Title
CPU_JTAG/XDP/CLK
!##$%&'()*"*
1
Sheet 6 of 57
Rev
1.0
5 4 3 2 1
D D
Haswell rPGA EDS
JCPU1C ME@
<11> DDRA_DQ[0..63]
Haswell rPGA EDS
DDRA_DQ0 AR15 AC7 JCPU1D ME@
SA_DQ_0 RSVD_1 <12> DDRB_DQ[0..63]
DDRA_DQ1 AT14 U4 DDRA_CLK0#
SA_DQ_1 SA_CK_N_0 DDRA_CLK0# <11>
DDRA_DQ2 AM14 V4 DDRA_CLK0 DDRB_DQ0 AR18 AG8
SA_DQ_2 SA_CK_P_0 DDRA_CLK0 <11> SB_DQ_0 RSVD_2
DDRA_DQ3 AN14 AD9 DDRA_CKE0 DDRB_DQ1 AT18 Y4 DDRB_CLK0#
SA_DQ_3 SA_CKE_0 DDRA_CKE0 <11> SB_DQ_1 SB_CKN0 DDRB_CLK0# <12>
DDRA_DQ4 AT15 U3 DDRA_CLK1# DDRB_DQ2 AM17 AA4 DDRB_CLK0
SA_DQ_4 SA_CK_N_1 DDRA_CLK1# <11> SB_DQ_2 SB_CK0 DDRB_CLK0 <12>
DDRA_DQ5 AR14 V3 DDRA_CLK1 DDRB_DQ3 AM18 AF10 DDRB_CKE0
SA_DQ_5 SA_CK_P_1 DDRA_CLK1 <11> SB_DQ_3 SB_CKE_0 DDRB_CKE0 <12>
DDRA_DQ6 AN15 AC9 DDRA_CKE1 DDRB_DQ4 AR17 Y3 DDRB_CLK1#
SA_DQ_6 SA_CKE_1 DDRA_CKE1 <11> SB_DQ_4 SB_CKN1 DDRB_CLK1# <12>
DDRA_DQ7 AM15 U2 DDRB_DQ5 AT17 AA3 DDRB_CLK1
SA_DQ_7 SA_CK_N_2 SB_DQ_5 SB_CK1 DDRB_CLK1 <12>
DDRA_DQ8 AM9 V2 DDRB_DQ6 AN17 AG10 DDRB_CKE1
SA_DQ_8 SA_CK_P_2 SB_DQ_6 SB_CKE_1 DDRB_CKE1 <12>
DDRA_DQ9 AN9 AD8 DDRB_DQ7 AN18 Y2
DDRA_DQ10 AM8 SA_DQ_9 SA_CKE_2 U1 DDRB_DQ8 AT12 SB_DQ_7 SB_CKN2 AA2
DDRA_DQ11 AN8 SA_DQ_10 SA_CK_N_3 V1 DDRB_DQ9 AR12 SB_DQ_8 SB_CK2 AG9
DDRA_DQ12 AR9 SA_DQ_11 SA_CK_P_3 AC8 DDRB_DQ10 AN12 SB_DQ_9 SB_CKE_2 Y1
DDRA_DQ13 AT9 SA_DQ_12 SA_CKE_3 DDRB_DQ11 AM11 SB_DQ_10 SB_CKN3 AA1
DDRA_DQ14 AR8 SA_DQ_13 M7 DDRA_CS0# DDRB_DQ12 AT11 SB_DQ_11 SB_CK3 AF9
SA_DQ_14 SA_CS_N_0 DDRA_CS0# <11> SB_DQ_12 SB_CKE_3
DDRA_DQ15 AT8 L9 DDRA_CS1# DDRB_DQ13 AR11
SA_DQ_15 SA_CS_N_1 DDRA_CS1# <11> SB_DQ_13
DDRA_DQ16 AJ9 M9 DDRB_DQ14 AM12 P4 DDRB_CS0#
SA_DQ_16 SA_CS_N_2 SB_DQ_14 SB_CS_N_0 DDRB_CS0# <12>
DDRA_DQ17 AK9 M10 DDRB_DQ15 AN11 R2 DDRB_CS1#
SA_DQ_17 SA_CS_N_3 SB_DQ_15 SB_CS_N_1 DDRB_CS1# <12>
DDRA_DQ18 AJ6 M8 DDRA_ODT0 DDRB_DQ16 AR5 P3
SA_DQ_18 SA_ODT_0 DDRA_ODT0 <11> SB_DQ_16 SB_CS_N_2
DDRA_DQ19 AK6 L7 DDRA_ODT1 DDRB_DQ17 AR6 P1
SA_DQ_19 SA_ODT_1 DDRA_ODT1 <11> SB_DQ_17 SB_CS_N_3
DDRA_DQ20 AJ10 L8 DDRB_DQ18 AM5
DDRA_DQ21 AK10 SA_DQ_20 SA_ODT_2 L10 DDRB_DQ19 AM6 SB_DQ_18 R4 DDRB_ODT0
SA_DQ_21 SA_ODT_3 SB_DQ_19 SB_ODT_0 DDRB_ODT0 <12>
DDRA_DQ22 AJ7 V5 DDRA_BS0# DDRB_DQ20 AT5 R3 DDRB_ODT1
SA_DQ_22 SA_BS_0 DDRA_BS0# <11> SB_DQ_20 SB_ODT_1 DDRB_ODT1 <12>
DDRA_DQ23 AK7 U5 DDRA_BS1# DDRB_DQ21 AT6 R1
SA_DQ_23 SA_BS_1 DDRA_BS1# <11> SB_DQ_21 SB_ODT_2
DDRA_DQ24 AF4 AD1 DDRA_BS2# DDRB_DQ22 AN5 P2
SA_DQ_24 SA_BS_2 DDRA_BS2# <11> SB_DQ_22 SB_ODT_3
DDRA_DQ25 AF5 DDRB_DQ23 AN6 R7 DDRB_BS0#
SA_DQ_25 SB_DQ_23 SB_BS_0 DDRB_BS0# <12>
DDRA_DQ26 AF1 V10 DDRB_DQ24 AJ4 P8 DDRB_BS1#
SA_DQ_26 VSS_1 SB_DQ_24 SB_BS_1 DDRB_BS1# <12>
DDRA_DQ27 AF2 U6 DDRA_RAS# DDRB_DQ25 AK4 AA9 DDRB_BS2#
C SA_DQ_27 SA_RAS DDRA_RAS# <11> SB_DQ_25 SB_BS_2 DDRB_BS2# <12> C
DDRA_DQ28 AG4 U7 DDRA_WE# DDRB_DQ26 AJ1
SA_DQ_28 SA_WE DDRA_WE# <11> SB_DQ_26
DDRA_DQ29 AG5 U8 DDRA_CAS# DDRB_DQ27 AJ2 R10
SA_DQ_29 SA_CAS DDRA_CAS# <11> SB_DQ_27 VSS_2
DDRA_DQ30 AG1 DDRB_DQ28 AM1 R6 DDRB_RAS#
SA_DQ_30 DDRA_MA[0..15] <11> SB_DQ_28 SB_RAS DDRB_RAS# <12>
DDRA_DQ31 AG2 V8 DDRA_MA0 DDRB_DQ29 AN1 P6 DDRB_WE#
SA_DQ_31 SA_MA_0 SB_DQ_29 SB_WE DDRB_WE# <12>
DDRA_DQ32 J1 AC6 DDRA_MA1 DDRB_DQ30 AK2 P7 DDRB_CAS#
SA_DQ_32 SA_MA_1 SB_DQ_30 SB_CAS DDRB_CAS# <12>
DDRA_DQ33 J2 V9 DDRA_MA2 DDRB_DQ31 AK1
SA_DQ_33 SA_MA_2 SB_DQ_31 DDRB_MA[0..15] <12>
DDRA_DQ34 J5 U9 DDRA_MA3 DDRB_DQ32 L2 R8 DDRB_MA0
DDRA_DQ35 H5 SA_DQ_34 SA_MA_3 AC5 DDRA_MA4 DDRB_DQ33 M2 SB_DQ_32 SB_MA_0 Y5 DDRB_MA1
DDRA_DQ36 H2 SA_DQ_35 SA_MA_4 AC4 DDRA_MA5 DDRB_DQ34 L4 SB_DQ_33 SB_MA_1 Y10 DDRB_MA2
DDRA_DQ37 H1 SA_DQ_36 SA_MA_5 AD6 DDRA_MA6 DDRB_DQ35 M4 SB_DQ_34 SB_MA_2 AA5 DDRB_MA3
DDRA_DQ38 J4 SA_DQ_37 SA_MA_6 AC3 DDRA_MA7 DDRB_DQ36 L1 SB_DQ_35 SB_MA_3 Y7 DDRB_MA4
DDRA_DQ39 H4 SA_DQ_38 SA_MA_7 AD5 DDRA_MA8 DDRB_DQ37 M1 SB_DQ_36 SB_MA_4 AA6 DDRB_MA5
DDRA_DQ40 F2 SA_DQ_39 SA_MA_8 AC2 DDRA_MA9 DDRB_DQ38 L5 SB_DQ_37 SB_MA_5 Y6 DDRB_MA6
DDRA_DQ41 F1 SA_DQ_40 SA_MA_9 V6 DDRA_MA10 DDRB_DQ39 M5 SB_DQ_38 SB_MA_6 AA7 DDRB_MA7
DDRA_DQ42 D2 SA_DQ_41 SA_MA_10 AC1 DDRA_MA11 DDRB_DQ40 G7 SB_DQ_39 SB_MA_7 Y8 DDRB_MA8
DDRA_DQ43 D3 SA_DQ_42 SA_MA_11 AD4 DDRA_MA12 DDRB_DQ41 J8 SB_DQ_40 SB_MA_8 AA10 DDRB_MA9
DDRA_DQ44 D1 SA_DQ_43 SA_MA_12 V7 DDRA_MA13 DDRB_DQ42 G8 SB_DQ_41 SB_MA_9 R9 DDRB_MA10
DDRA_DQ45 F3 SA_DQ_44 SA_MA_13 AD3 DDRA_MA14 DDRB_DQ43 G9 SB_DQ_42 SB_MA_10 Y9 DDRB_MA11
DDRA_DQ46 C3 SA_DQ_45 SA_MA_14 AD2 DDRA_MA15 DDRB_DQ44 J7 SB_DQ_43 SB_MA_11 AF7 DDRB_MA12
DDRA_DQ47 B3 SA_DQ_46 SA_MA_15 DDRB_DQ45 J9 SB_DQ_44 SB_MA_12 P9 DDRB_MA13
DDRA_DQ48 B5 SA_DQ_47 DDRB_DQ46 G10 SB_DQ_45 SB_MA_13 AA8 DDRB_MA14
SA_DQ_48 DDRA_DQS#[0..7] <11> SB_DQ_46 SB_MA_14
DDRA_DQ49 E6 AP15 DDRA_DQS#0 DDRB_DQ47 J10 AG7 DDRB_MA15
DDRA_DQ50 A5 SA_DQ_49 SA_DQS_N_0 AP8 DDRA_DQS#1 DDRB_DQ48 A8 SB_DQ_47 SB_MA_15
DDRA_DQ51 D6 SA_DQ_50 SA_DQS_N_1 AJ8 DDRA_DQS#2 DDRB_DQ49 B8 SB_DQ_48
SA_DQ_51 SA_DQS_N_2 SB_DQ_49 DDRB_DQS#[0..7] <12>
DDRA_DQ52 D5 AF3 DDRA_DQS#3 DDRB_DQ50 A9 AP18 DDRB_DQS#0
DDRA_DQ53 E5 SA_DQ_52 SA_DQS_N_3 J3 DDRA_DQS#4 DDRB_DQ51 B9 SB_DQ_50 SB_DQS_N_0 AP11 DDRB_DQS#1
DDRA_DQ54 B6 SA_DQ_53 SA_DQS_N_4 E2 DDRA_DQS#5 DDRB_DQ52 D8 SB_DQ_51 SB_DQS_N_1 AP5 DDRB_DQS#2
DDRA_DQ55 A6 SA_DQ_54 SA_DQS_N_5 C5 DDRA_DQS#6 DDRB_DQ53 E8 SB_DQ_52 SB_DQS_N_2 AJ3 DDRB_DQS#3
DDRA_DQ56 E12 SA_DQ_55 SA_DQS_N_6 C11 DDRA_DQS#7 DDRB_DQ54 D9 SB_DQ_53 SB_DQS_N_3 L3 DDRB_DQS#4
SA_DQ_56 SA_DQS_N_7 DDRA_DQS[0..7] <11> SB_DQ_54 SB_DQS_N_4
DDRA_DQ57 D12 AP14 DDRA_DQS0 DDRB_DQ55 E9 H9 DDRB_DQS#5
DDRA_DQ58 B11 SA_DQ_57 SA_DQS_P_0 AP9 DDRA_DQS1 DDRB_DQ56 E15 SB_DQ_55 SB_DQS_N_5 C8 DDRB_DQS#6
DDRA_DQ59 A11 SA_DQ_58 SA_DQS_P_1 AK8 DDRA_DQS2 DDRB_DQ57 D15 SB_DQ_56 SB_DQS_N_6 C14 DDRB_DQS#7
B SA_DQ_59 SA_DQS_P_2 SB_DQ_57 SB_DQS_N_7 DDRB_DQS[0..7] <12> B
DDRA_DQ60 E11 AG3 DDRA_DQS3 DDRB_DQ58 A15 AP17 DDRB_DQS0
DDRA_DQ61 D11 SA_DQ_60 SA_DQS_P_3 H3 DDRA_DQS4 DDRB_DQ59 B15 SB_DQ_58 SB_DQS_P_0 AP12 DDRB_DQS1
DDRA_DQ62 B12 SA_DQ_61 SA_DQS_P_4 E3 DDRA_DQS5 DDRB_DQ60 E14 SB_DQ_59 SB_DQS_P_1 AP6 DDRB_DQS2
DDRA_DQ63 A12 SA_DQ_62 SA_DQS_P_5 C6 DDRA_DQS6 DDRB_DQ61 D14 SB_DQ_60 SB_DQS_P_2 AK3 DDRB_DQS3
AM3 SA_DQ_63 SA_DQS_P_6 C12 DDRA_DQS7 DDRB_DQ62 A14 SB_DQ_61 SB_DQS_P_3 M3 DDRB_DQS4
+V_SM_VREF SM_VREF SA_DQS_P_7 SB_DQ_62 SB_DQS_P_4
+VREF_DQA_M3 F16 DDRB_DQ63 B14 H8 DDRB_DQS5
F13 SA_DIMM_VREFDQ SB_DQ_63 SB_DQS_P_5 C9 DDRB_DQS6
+VREF_DQB_M3 SB_DIMM_VREFDQ SB_DQS_P_6 C15 DDRB_DQS7
SB_DQS_P_7
INTEL_HASWELL_HASWELL 3 OF 9 INTEL_HASWELL_HASWELL 4 OF 9
A A
Dr-Bios.com
+VREF_DQA_M3 +VREF_DQB_M3
1 1
CC45 CC46
0.1U_0402_25V6-K 0.1U_0402_25V6-K
2 2 Issued Date 2012/12/05 Deciphered Date 2014/12/05 CPU_DDR3 INTERFACE
Rev
Custom 1.0
ESD DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
!##$%&'()*"*
5 4 3 2 1
5 4 3 2 1
JCPU1H ME@Haswell rPGA EDS HPD INVERSION FOR EDP

To HDMI
CPU_HDMI_TX2- T28 M27 CPU_EDP_AUX# +VCCIO_OUT
<34> CPU_HDMI_TX2- DDIB_TXBN_0 EDP_AUXN CPU_EDP_AUX# <36>
<34> CPU_HDMI_TX2+ CPU_HDMI_TX2+ U28 N27 CPU_EDP_AUX
DDIB_TXBP_0 EDP_AUXP CPU_EDP_AUX <36>
<34> CPU_HDMI_TX1- CPU_HDMI_TX1- T30 P27 EDP_HPD_IN#
DDIB_TXBN_1 EDP_HPD
1
D CPU_HDMI_TX1+ U30 eDP E24 EDP_COMP RC25 1 2 24.9_0402_1% D
<34> CPU_HDMI_TX1+ DDIB_TXBP_1 EDP_RCOMP +VCCIOA_OUT
<34> CPU_HDMI_TX0- CPU_HDMI_TX0- U29 R27 1 Pull up resistor on DP_HPD
DDIB_TXBN_2 EDP_DISP_UTIL T10 @
<34> CPU_HDMI_TX0+ CPU_HDMI_TX0+ V29 RC26
CPU_HDMI_CLK- U31 DDIB_TXBP_2 10K_0402_5% modified to 10kOhms from
<34> CPU_HDMI_CLK- DDIB_TXBN_3
<34> CPU_HDMI_CLK+ CPU_HDMI_CLK+ V31 1kOhms .
2
DDIB_TXBP_3 P35 CPU_EDP_TX0-
EDP_TXN_0 CPU_EDP_TX0- <36>
<42> CPU_DOCK_TX0- CPU_DOCK_TX0- T34 R35 CPU_EDP_TX0+
DDIC_TXCN_0 EDP_TXP_0 CPU_EDP_TX0+ <36>
CPU_DOCK_TX0+ U34 N34 CPU_EDP_TX1- EDP_HPD_IN#
<42>
<42>
CPU_DOCK_TX0+
CPU_DOCK_TX1- CPU_DOCK_TX1- U35 DDIC_TXCP_0 EDP_TXN_1 P34 CPU_EDP_TX1+
CPU_EDP_TX1-
CPU_EDP_TX1+
<36>
<36>
To eDP Panel
CPU_DOCK_TX1+ V35 DDIC_TXCN_1 EDP_TXP_1 P33 FDI_CTX_PRX_N0
<42> CPU_DOCK_TX1+ DDIC_TXCP_1 FDI_TXN_0 FDI_CTX_PRX_N0 <15>
1
U32 R33 FDI_CTX_PRX_P0 D
DDIC_TXCN_2 FDI_TXP_0 FDI_CTX_PRX_P0 <15>
T32 N32 FDI_CTX_PRX_N1 CPU_EDP_HPD 2 QC1
Docking DP U33 DDIC_TXCP_2 FDI_TXN_1 P32 FDI_CTX_PRX_P1
FDI_CTX_PRX_N1
FDI_CTX_PRX_P1
<15>
<15>
<36> CPU_EDP_HPD G BSS138_NL_SOT23-3
V33 DDIC_TXCN_3 FDI_TXP_1
S SB50138002J
3
DDIC_TXCP_3
1
P29
DDID_TXDN_0 COMPENSATION PU FOR eDP 2nd --> SB50138000T
R29 RC27
N28 DDID_TXDP_0 CAD Note:Trace width=20 mils, Spacing=25mil, 100K_0402_5%
P28 DDID_TXDN_1 DDI
Max length=100 mils.
2
P31 DDID_TXDP_1
DDID_TXDN_2 It is an output from eDP sink device and it is a active high
R31
N30 DDID_TXDP_2 signal. However, the HPD processor input is a low voltage
P30 DDID_TXDN_3 active low signal.
DDID_TXDP_3
INTEL_HASWELL_HASWELL 8 OF 9
C C
CFG STRAPS For CPU

Haswell rPGA EDS (CFG[17:0] internal pull high 5!
!15K to VCCIO)
JCPU1I ME@
AT1 PEG Static Lane Reversal - CFG2 is for the 16x CFG2 RC28 1 @ 2 1K_0402_1%
AT2 RSVD_TP_5 C23
AD10 RSVD_TP_6 RSVD_TP_16 B23
RSVD_17 RSVD_TP_17
RSVD_TP_18
D24 * 1: (Default) Normal Operation;
A34 D23 RC35
A35 RSVD_TP_7 RSVD_TP_19 CPU_CFG_RCOMP 2 1 CFG2 Lane# definition matches socket pin map definition
RSVD_TP_8
W29 49.9_0402_1% 0: Lane Reversed
RC33 W28 RSVD_TP_9 AT31
1 2 CPU_TESTLO_G26 G26 RSVD_TP_10 CFG_RCOMP AR21 PCH_PWROK
TESTLO_G26 CFG_16 PCH_PWROK <15,48>
W33 AR23
RSVD_18 CFG_18
1
49.9_0402_1% AL30 AP21

AL29 RSVD_19 CFG_17 AP23
+VCC_CORE +VCC_CORE F25 RSVD_20 CFG_19 @ RC44 Display Port Presence Strap CFG4 RC29 1 2 1K_0402_1%
VCC 2K_0402_1%
C35 AR33
1 : Disabled
2
B35 RSVD_TP_11 RSVD_21 G6

B RSVD_TP_12 FC_G6 AM27 B
RSVD_22 No Physical Display Port attached to Embedded Display Port
1
AL25 AM26
RSVD_TP_13 RSVD_23 F5
W30
RSVD_TP_14
RSVD_24
RSVD_25
AM2 @ RC45 CFG4 * 0 : Enabled;
RC34 W31 K6 1K_0402_1%
1 2 CPU_TESTLO_W34 W34 RSVD_TP_15 RSVD_26 An external Display Port device is connected to the
2
TESTLO E18
49.9_0402_1% AT20 RSVD_27 Embedded Display Port
AR20 CFG_0 U10
CFG2 AP20 CFG_1 RSVD_28 P10
1 CFG3 AP22 CFG_2 RSVD_29
@ T34
@T34 CFG_3
CFG4 AT22 B1
CFG5 AN22 CFG_4 NC A2
CFG6 AT25 CFG_5 RSVD_30 AR1 PCIE Port Bifurcation Straps CFG5 RC30 1 @ 2 1K_0402_1%
CFG7 AN23 CFG_6 RSVD_TP_20
AR24 CFG_7 E21 CFG6 RC31 1 @ 2 1K_0402_1%
@ T41
@T41
1 CFG9 AT23 CFG_8 RSVD_TP_21 E20 11 : Func 1 Disabled, Func 2 Disabled (x16,---,---)
AN20 CFG_9 RSVD_TP_22
AP24 CFG_10
CFG_11 RSVD_31
AP27
CFG[6:5] * 10 : Func 1 Enabled, Func 2 Disabled (x8,x8,---)
AP26 AR26
AN25 CFG_12 RSVD_32 01 : Func 1 Disabled, Func 2 Enabled
AN26 CFG_13 AL31
AP25 CFG_14 VSS_342 AL32 00 : Func 1 Enabled, Func 2 Enabled (x8,x4,x4)
CFG_15 VSS_343
PEG DEFER TRAINING CFG7 RC32 1 @ 2 1K_0402_1%
A
* 1: (Default)
A
CFG7 PEG Train Immediately Following XXRESETB Deassertion
0 : PEG Wait for BIOS for Training
5
Dr-Bios.com 4
3 2
Title
CPU_eDP/DDI/RSVD/CFG
Custom
Date: Thursday, July 11, 2013

!##$%&'()*"*
1
Sheet 8 of 57
Rev
1.0
5 4 3 2 1
Haswell rPGA EDS +VCC_CORE

JCPU1E ME@
CPU VDDQ DECOUPLING
AA26
VCC_13 AA28
D K27
57W, 95A VCC_14 AA34 D
L27 RSVD_3 47W, 85A VCC_15 AA30
+1.35V T27 RSVD_4 VCC_16 AA32
V27 RSVD_5 37W, 55A VCC_17 AB26
RSVD_6 VCC_18 AB29
CC18 CC19 CC20 CC21 CC22 CC23 CC24 CC25 CC26 CC27 VCC_19 AB25
+1.35V VCC_20 AB27
VCC_21 AB28
VCC_22
10U_0603_6.3V6-M
10U_0603_6.3V6-M
10U_0603_6.3V6-M
10U_0603_6.3V6-M
10U_0603_6.3V6-M
10U_0603_6.3V6-M
10U_0603_6.3V6-M
10U_0603_6.3V6-M
10U_0603_6.3V6-M
10U_0603_6.3V6-M
1 1 1 1 1 1 1 1 1 1 AB11 4.2A AB30
AB2 VDDQ_1 VCC_23 AB31
2 2 2 2 2 2 2 2 2 2 AE11 VDDQ_4 VCC_26 AB32
AE2 VDDQ_5 VCC_27 AC26
AE5 VDDQ_6 VCC_28 AB35
AE8 VDDQ_7 VCC_29 AC28
AH11 VDDQ_8 VCC_30 AD25
K11 VDDQ_9 VCC_31 AC30
N11 VDDQ_10 VCC_32 AD28
N8 VDDQ_11 VCC_33 AC32
CC28 CC29 CC30 CC31 CC32 CC33 CC34 CC35 CC36 CC37 CC38 CC39 CC40 T11 VDDQ_12 VCC_34 AD31
T2 VDDQ_13 VCC_35 AC34
T5 VDDQ_14 VCC_36 AD34
VDDQ_15 VCC_37
22U_0805_6.3V6-M
22U_0805_6.3V6-M
22U_0805_6.3V6-M
22U_0805_6.3V6-M
22U_0805_6.3V6-M
22U_0805_6.3V6-M
22U_0805_6.3V6-M
22U_0805_6.3V6-M
22U_0805_6.3V6-M
22U_0805_6.3V6-M
22U_0805_6.3V6-M
330U_D2_2VM_R6M
330U_D2_2VM_R6M
1 1 1 1 1 1 1 1 1 1 1 1 1 T8 AD26
W11 VDDQ_16 VCC_38 AD27
+ @ + W2 VDDQ_17 VCC_39 AD29
W5 VDDQ_18 VCC_40 AD30
2 2 2 2 2 2 2 2 2 2 2 W8 VDDQ_19 VCC_41 AD32
2 2 VDDQ_20 VCC_42 AD33
N26 VCC_43 AD35
K26 RSVD_7 VCC_44 AE26
+VCC_CORE VCC_1 VCC_45
AL27 AE32
C AK27 RSVD_8 VCC_46 AE28 C
RSVD_9 VCC_47 AE30
VDDQ Decoupling : VCC_48 AG28
VCC_49 AG34
1. MB Bottom Socket Edge --> 2* 330uf, 6mΩ VCC_50 AE34
VCC_51 AF25
2. 6x MB Bottom Socket Cavity --> 11* 22 μF (0805), 3mΩ Reserve for VCCST VCC_52 AF26
+1.05VS_PCH_VPROC VCCSENSE AL35 VCC_53 AF27
5x MB Top Socket Cavity E17 VCC_SENSE VCC_54 AF28
AN35 RSVD_10 VCC_55 AF29
3. 5x MB Bottom Socket Cavity --> 10 x 10 μF (0805), 3mΩ RC43 1 @ 2 0_0402_5%
+VCCIO_OUT
+VCCST_A23 A23 VCCIO_OUT 300mA VCC_56 AF30
RSVD_11 VCC_57
5x MB Top Socket Cavity 1 +VCCIOA_OUT F22
W32 VCOMP_OUT 300mA VCC_58
AF31
AF32
@ CC42 AL16 RSVD_12 VCC_59 AF33
4.7U_0603_6.3V6K J27 RSVD_13 VCC_60 AF34
2 AL13 RSVD_14 VCC_61 AF35
RSVD_15 VCC_62 AG26
VCC_63 AH26
RC36 1 2 43_0402_1% H_CPU_SVIDALRT# AM28 VCC_64 AH29
<64> VR_SVID_ALRT# VIDALERT VCC_65
RC37 1 2 0_0402_5% H_CPU_SVIDCLK AM29 AG30
<64> VR_SVID_CLK VIDSCLK VCC_66
RC38 1 2 0_0402_5% H_CPU_SVIDDAT AL28 AG32
<64> VR_SVID_DAT VIDSOUT VCC_67 AH32
AP35 VCC_68 AH35
Pull high resistor on VR side RC42 1 2 130_0402_1% 1 H27 VSS_3 VCC_69 AH25
+VCCIO_OUT @ T54 PWR_DEBUG VCC_70
AP34 AH27
AT35 VSS_4 VCC_71 AH28
VCC/VSS SENSE AR35 RSVD_TP_1
RSVD_TP_2
VCC_72
VCC_73
AH30
AR32 AH31
AL26 RSVD_TP_3 VCC_74 AH33
+VCC_CORE AT34 RSVD_TP_4 VCC_75 AH34
AL22 VSS_5 VCC_76 AJ25
AT33 VSS_6 VCC_77 AJ26
B +1.05VS +VCCIO_OUT AM21 VSS_7 VCC_78 AJ27 B
VSS_8 VCC_79
1
AM25 AJ28
AM22 VSS_9 VCC_80 AJ29
RC39
Reserve 0-Ohm on Power Side RC40 AM20 VSS_10 VCC_81 AJ30
100_0402_1% 1 @ 2 AM24 VSS_11 VCC_82 AJ31
AL19 VSS_12 VCC_83 AJ32
2
0_0603_5% AM23 VSS_13 VCC_84 AJ33

AT32 VSS_14 VCC_85 AJ34
VCCSENSE VSS_15 VCC_86 AJ35
<64> VCCSENSE RESISTOR STUFFING OPTIONS ARE VCC_87 G25
PROVIDED FOR TESTING PURPOSES VCC_88 H25
VCC_89 J25
VCC_90 K25
VCC_91 L25
VSSSENSE +VCC_CORE VCC_92 M25
<10,64> VSSSENSE VCC_93
Y25 N25
Y26 VCC_2 VCC_94 P25
VCC_3 VCC_95
1
Y27 R25
Y28 VCC_4 VCC_96 T25
RC41 Y29 VCC_5 VCC_97
100_0402_1% Y30 VCC_6 U25
Y31 VCC_7 VCC_98 U26
2
Y32 VCC_8 VCC_99 V25

Y33 VCC_9 VCC_100 V26
Close to CPU Y34 VCC_10 VCC_101
Y35 VCC_11 W26
VCC_12 VCC_102 W27
VCC_103
A A
5
Dr-Bios.com 4
3 2
Custom
Date:
Title
CPU_POWER

!##$%&'()*"*
1
Sheet 9 of 57
Rev
1.0
5 4 3 2 1
D JCPU1F Haswell rPGA EDSME@ Haswell rPGA EDSME@

JCPU1G D
A10 AK34 B34 K10

A13 VSS_16 VSS_106 AK5 B4 VSS_185 VSS_266 K2
A16 VSS_17 VSS_107 AL1 B7 VSS_186 VSS_267 K29
A19 VSS_18 VSS_108 AL10 C1 VSS_187 VSS_268 K3
A7 VSS_27 VSS_117 AL21 C28 VSS_196 VSS_277 L11
AA11 VSS_28 VSS_118 AL23 C30 VSS_197 VSS_278 L26
AA25 VSS_29 VSS_119 E22 C32 VSS_198 VSS_279 L6
AA27 VSS_30 VSS_120 AL3 C34 VSS_199 VSS_280 M11
AB1 VSS_33 VSS_123 AL6 D10 VSS_202 VSS_283 M30
AB10 VSS_34 VSS_124 AL7 D13 VSS_203 VSS_284 M32
AA33 VSS_35 VSS_125 AL8 D16 VSS_204 VSS_285 M34
AA35 VSS_36 VSS_126 AL9 D19 VSS_205 VSS_286 M6
AB3 VSS_37 VSS_127 AM10 D22 VSS_206 VSS_287 N1
AC25 VSS_38 VSS_128 AM13 D25 VSS_207 VSS_288 N10
AB6 VSS_41 VSS_131 E25 D31 VSS_210 VSS_291 N3
C AD11 VSS_45 VSS_135 AN10 D7 VSS_214 VSS_295 N4 C
AC29 VSS_46 VSS_136 AN13 E1 VSS_215 VSS_296 N5
AD7 VSS_50 VSS_140 AN21 E4 VSS_219 VSS_300 P11
AE1 VSS_51 VSS_141 AN24 E7 VSS_220 VSS_301 P26
AE10 VSS_52 VSS_142 AN27 F10 VSS_221 VSS_302 P5
AE25 VSS_53 VSS_143 AN30 F11 VSS_222 VSS_303 R11
AE35 VSS_57 VSS_147 AP1 F17 VSS_226 VSS_307 R32
AE7 VSS_70 VSS_150 AP16 F21 VSS_229 VSS_310 T1
AE9 VSS_71 VSS_151 AP19 F23 VSS_230 VSS_311 T10
AF11 VSS_72 VSS_152 AP4 F24 VSS_231 VSS_312 T29
AF6 VSS_73 VSS_153 AP7 F26 VSS_232 VSS_313 T3
AF8 VSS_74 VSS_154 W25 F28 VSS_233 VSS_314 T31
AG11 VSS_75 VSS_155 AR10 F30 VSS_234 VSS_315 T33
AE31 VSS_77 VSS_157 AR16 F34 VSS_236 VSS_317 T4
AE33 VSS_79 VSS_159 AR2 F6 VSS_238 VSS_319 T7
AH1 VSS_81 VSS_161 AR25 F8 VSS_240 VSS_321 U11
AH10 VSS_82 VSS_162 AR28 F9 VSS_241 VSS_322 U27
AH2 VSS_83 VSS_163 AR31 G1 VSS_242 VSS_323 V11
AG27 VSS_84 VSS_164 AR34 G11 VSS_243 VSS_324 V28
AG29 VSS_85 VSS_165 AR4 G2 VSS_244 VSS_325 V30
AH3 VSS_86 VSS_166 AR7 G27 VSS_245 VSS_326 V32
B AG33 VSS_87 VSS_167 AT10 G29 VSS_246 VSS_327 V34 B
AG35 VSS_88 VSS_168 AT13 G3 VSS_247 VSS_328 W1
AH4 VSS_89 VSS_169 AT16 G31 VSS_248 VSS_329 W10
AH9 VSS_94 VSS_174 AT3 H10 VSS_253 VSS_334 W7
AJ11 VSS_95 VSS_175 AT30 H26 VSS_254 VSS_335 W9
AJ5 VSS_96 VSS_176 AT4 H6 VSS_255 VSS_336 Y11
AK11 VSS_97 VSS_177 AT7 H7 VSS_256 VSS_337 H11
AK25 VSS_98 VSS_178 B10 J11 VSS_257 VSS_338 AL24
AK26 VSS_99 VSS_179 B13 J26 VSS_258 VSS_339 F19
AK28 VSS_100 VSS_180 B16 J28 VSS_259 VSS_340 T26
AK29 VSS_101 VSS_181 B19 J30 VSS_260 VSS_341 AK35 VSSSENSE
VSS_102 VSS_182 VSS_261 VSS_SENSE VSSSENSE <64,9>
AK30 B2 J32 AK33
AK32 VSS_103 VSS_183 B22 J34 VSS_262 RSVD_17
E19 VSS_104 VSS_184 J6 VSS_263
VSS_105 K1 VSS_264
VSS_265
INTEL_HASWELL_HASWELL6 OF 9 INTEL_HASWELL_HASWELL 7 OF 9
A A
5
Dr-Bios.com 4
3 2
Title
Date:
CPU_GND
Custom
!"#$%&'()*+*
1
Sheet 10 of 57
Rev
1.0
5 4 3 2 1
DDRA_DQ[0..63] <7>
DDR3 SO-DIMM A DDRA_DQS[0..7] <7>
DDRA_DQS#[0..7] <7>
DDRA_MA[0..15] <7>
+1.35V +1.35V
3A@1.5V
JDIMM1 ME@
+VREF_DQA 1 2
3 VREF_DQ VSS1 4 DDRA_DQ4
D DDRA_DQ0 5 VSS2 DQ4 6 DDRA_DQ5 D
DDRA_DQ1 7 DQ0 DQ5 8
1 0.1U_0402_10V7-K 1 DQ1 VSS3
2.2U_0402_6.3V6-M
CD1 CD2 9 10 DDRA_DQS#0
11 VSS4 DQS#0 12 DDRA_DQS0
13 DM0 DQS0 14
2 2 DDRA_DQ2 15 VSS5 VSS6 16 DDRA_DQ6
DDRA_DQ3 17 DQ2 DQ6 18 DDRA_DQ7
19 DQ3 DQ7 20
DDRA_DQ8 21 VSS7 VSS8 22 DDRA_DQ12
25 DQ9 DQ13 26
DDRA_DQS#1 27 VSS9 VSS10 28
Close to JDDR3H.1 DDRA_DQS1 29
31
DQS#1
DQS1
DM1
RESET#
30
32
DDR3_DRAMRST#
DDR3_DRAMRST# <12,6> DDR Decoupling
DDRA_DQ11 35 DQ10 DQ14 36 DDRA_DQ15 +1.35V
DDRA_DQ16
37
39
DQ11
VSS13
DQ15
VSS14
38
40 DDRA_DQ20
1uF *4, 10uF *7, 330uF *1
DDRA_DQ17 41 DQ16 DQ20 42 DDRA_DQ21 CD3 CD4 CD5 CD6
43 DQ17 DQ21 44
DDRA_DQS#2 45 VSS15
DQS#2
VSS16
DM2
46 Layout Note :
1U_0402_6.3V6-K
1U_0402_6.3V6-K
1U_0402_6.3V6-K
1U_0402_6.3V6-K
DDRA_DQS2 47 48 1 1 1 1
DQS2 VSS17
DDRA_DQ18
49
51 VSS18
DQ18
DQ22
DQ23
50
52
DDRA_DQ22
DDRA_DQ23 1. Placed near JDDR3L
DDRA_DQ19 53 54
DDRA_DQ24
55
57
DQ19
VSS20
VSS19
DQ28
56
58
DDRA_DQ28
DDRA_DQ29
2 2 2 2
2. Place these 4 Caps near Command
DQ24 DQ29
DDRA_DQ25 59
61 DQ25
VSS22
VSS21
DQS#3
60
62 DDRA_DQS#3 and Control signals of DIMMA
63 64 DDRA_DQS3
65 DM3 DQS3 66
C DDRA_DQ27 69 DQ26 DQ30 70 DDRA_DQ31 C
71 DQ27 DQ31 72
VSS25 VSS26
CD7 CD8 CD9 CD10 CD11 CD12 CD13 CD14 CD15
<7> DDRA_CKE0 DDRA_CKE0 73 74 DDRA_CKE1 1

CKE0 CKE1 DDRA_CKE1 <7>
10U_0603_6.3V6-M
10U_0603_6.3V6-M
10U_0603_6.3V6-M
10U_0603_6.3V6-M
10U_0603_6.3V6-M
10U_0603_6.3V6-M
10U_0603_6.3V6-M
10U_0603_6.3V6-M
330U_D2_2VM_R9M
75 76 1 1 1 1 1 1 1 1
77 VDD1 VDD2 78 DDRA_MA15 +
DDRA_BS2# 79 NC1 A15 80 DDRA_MA14
<7> DDRA_BS2# BA2 A14
81 82
DDRA_MA12 83 VDD3 VDD4 84 DDRA_MA11 2 2 2 2 2 2 2 2 2
DDRA_MA9 85 A12/BC# A11 86 DDRA_MA7
87 A9 A7 88
DDRA_MA8 89 VDD5 VDD6 90 DDRA_MA6
DDRA_MA5 91 A8 A6 92 DDRA_MA4
93 A5 A4 94
DDRA_MA3 95 VDD7 VDD8 96 DDRA_MA2
DDRA_MA1 97 A3 A2 98 DDRA_MA0
99 A1 A0 100
DDRA_CLK0 101 VDD9 VDD10 102 DDRA_CLK1
<7> DDRA_CLK0 CK0 CK1 DDRA_CLK1 <7> +0.675VS
<7> DDRA_CLK0# DDRA_CLK0# 103 104 DDRA_CLK1#
CK0# CK1# DDRA_CLK1# <7>
105 106
DDRA_MA10 107 VDD11 VDD12 108 DDRA_BS1#
A10/AP BA1 DDRA_BS1# <7>
DDRA_BS0# 109 110 DDRA_RAS# CD16 CD17 CD18 CD19
<7> DDRA_BS0#
DDRA_WE#
111
113
BA0
VDD13
RAS#
VDD14
112
114 DDRA_CS0#
DDRA_RAS# <7>
Layout Note : Placed near
<7> DDRA_WE# WE# S0# DDRA_CS0# <7>
JDDR3L1.Pin203, 204
1U_0402_6.3V6-K
1U_0402_6.3V6-K
1U_0402_6.3V6-K
1U_0402_6.3V6-K
<7> DDRA_CAS# DDRA_CAS# 115 116 DDRA_ODT0 1 1 1 1
CAS# ODT0 DDRA_ODT0 <7>
117 118
DDRA_MA13 119 VDD15 VDD16 120 DDRA_ODT1
A13 ODT1 DDRA_ODT1 <7>
<7> DDRA_CS1# DDRA_CS1# 121 122
123 S1# NC2 124 2 2 2 2
125 VDD17 VDD18 126
B NCTEST VREF_CA +V_SM_VREF_CNT B
127 128
DQ33 DQ37 1 1
0.1U_0402_10V7-K
133 134 CD20 CD21 2.2U_0402_6.3V6-M

DDRA_DQS4 137 DQS#4 DM4 138
139 DQS4 VSS31 140 DDRA_DQ38 2 2
DDRA_DQ34 141 VSS32 DQ38 142 DDRA_DQ39
DDRA_DQ35 143 DQ34 DQ39 144
145 DQ35 VSS33 146 DDRA_DQ44
DDRA_DQ41 149 DQ40 DQ45 150
151 DQ41 VSS35 152 DDRA_DQS#5
155 DM5 DQS5 156
close to JDDR3L.126
161 DQ43 DQ47 162
167 DQ49 DQ53 168
DDRA_DQS6 171 DQS#6 DM6 172
173 DQS6 VSS43 174 DDRA_DQ54
DDRA_DQ51 177 DQ50 DQ55 178
179 DQ51 VSS45 180 DDRA_DQ60
DDRA_DQ57 183 DQ56 DQ61 184
185 DQ57 VSS47 186 DDRA_DQS#7
SPD setting (SA0, SA1) DM7 DQS7
189 190
A PU/PD by Channel A/B DDRA_DQ58 191 VSS49 VSS50 192 DDRA_DQ62 A
->Channel A 00 DDRA_DQ59 193 DQ58 DQ62 194 DDRA_DQ63
195 DQ59 DQ63 196
->Channel B 01
Dr-Bios.com
RD1 VSS51 VSS52
1 2 197 198
10K_0402_5% 199 SA0 EVENT# 200 PM_SMBDATA
+3VS VDDSPD SDA PM_SMBDATA <12,17,39,43>
201 202 PM_SMBCLK
SA1 SCL PM_SMBCLK <12,17,39,43>
1
1 1 203 204 +0.675VS

VTT1 VTT2
!"#$%&!"'$( Security Classification LC Future Center Secret Data Title
CD22 CD23 RD2 205 206
2.2U_0603_6.3V6-K 0.1U_0402_10V6-K 10K_0402_5% G1 G2
2 2 TYCO_2-2013287-1
Issued Date 2012/12/05 Deciphered Date 2014/12/05 DDR3 SO-DIMMA/1
2
Rev
Custom 1.0
!##$%&'()*"*
5 4 3 2 1
5 4 3 2 1
DDR3 SO-DIMM B DDRB_DQ[0..63] <7>
DDRB_DQS[0..7] <7>
+1.35V +1.35V DDRB_DQS#[0..7] <7>

3A@1.5V DDRB_MA[0..15] <7>
JDIMM2 ME@
+VREF_DQB 1 2
3 VREF_DQ VSS1 4 DDRB_DQ4
DDRB_DQ0 5 VSS2 DQ4 6 DDRB_DQ5
DDRB_DQ1 7 DQ0 DQ5 8
1 1 DQ1 VSS3
DDR Decoupling
0.1U_0402_10V7-K
2.2U_0402_6.3V6-M
D CD25 CD24 9 10 DDRB_DQS#0 D
11 VSS4 DQS#0 12 DDRB_DQS0
13 DM0 DQS0 14
2 2 DDRB_DQ2 15 VSS5 VSS6 16 DDRB_DQ6 +1.35V
DDRB_DQ3 17
19
DQ2
DQ3
DQ6
DQ7
18
20
DDRB_DQ7 1uF *4, 10uF *7, 330uF *1
DDRB_DQ8 21 VSS7 VSS8 22 DDRB_DQ12 CD26 CD27 CD28 CD29
DDRB_DQ9 23 DQ8 DQ12 24 DDRB_DQ13
25 DQ9
VSS9
DQ13
VSS10
26 Layout Note :
1U_0402_6.3V6-K
1U_0402_6.3V6-K
1U_0402_6.3V6-K
1U_0402_6.3V6-K
DDRB_DQS#1 27 28 1 1 1 1
DQS#1 DM1
Close to JDDR3L.1 DDRB_DQS1 29
31 DQS1
VSS11
RESET#
VSS12
30
32
DDR3_DRAMRST#
DDR3_DRAMRST# <11,6> 1. Placed near JDDR3H
DDRB_DQ10 33 34 DDRB_DQ14
DDRB_DQ11 35
37
DQ10
DQ11
DQ14
DQ15
36
38
DDRB_DQ15 2 2 2 2
2. Place these 4 Caps near Command
VSS13 VSS14
DDRB_DQ16
DDRB_DQ17
39
41 DQ16
DQ17
DQ20
DQ21
40
42
DDRB_DQ20
DDRB_DQ21 and Control signals of DIMMA
43 44
DDRB_DQS#2 45 VSS15 VSS16 46
DDRB_DQS2 47 DQS#2 DM2 48
49 DQS2 VSS17 50 DDRB_DQ22
55 DQ19 VSS19 56 DDRB_DQ28 CD30 CD31 CD32 CD33 CD34 CD35 CD36 CD37 CD38
DQ25 VSS21 1
10U_0603_6.3V6-M
10U_0603_6.3V6-M
10U_0603_6.3V6-M
10U_0603_6.3V6-M
10U_0603_6.3V6-M
10U_0603_6.3V6-M
10U_0603_6.3V6-M
10U_0603_6.3V6-M
330U_D2_2VM_R9M
61 62 DDRB_DQS#3 1 1 1 1 1 1 1 1
63 VSS22 DQS#3 64 DDRB_DQS3 +
65 DM3 DQS3 66
DDRB_DQ26 67 VSS23 VSS24 68 DDRB_DQ30
DDRB_DQ27 69 DQ26 DQ30 70 DDRB_DQ31 2 2 2 2 2 2 2 2 2
71 DQ27 DQ31 72
C VSS25 VSS26 C
<7> DDRB_CKE0 DDRB_CKE0 73 74 DDRB_CKE1

CKE0 CKE1 DDRB_CKE1 <7>
75 76
77 VDD1 VDD2 78 DDRB_MA15
DDRB_BS2# 79 NC1 A15 80 DDRB_MA14
<7> DDRB_BS2# BA2 A14 +0.675VS
81 82
DDRB_MA12 83 VDD3 VDD4 84 DDRB_MA11
DDRB_MA9 85 A12/BC# A11 86 DDRB_MA7
87 A9 A7 88 CD39 CD40 CD41 CD42
DDRB_MA8
DDRB_MA5
89
91
VDD5
A8
VDD6
A6
90
92
DDRB_MA6
DDRB_MA4
Layout Note : Placed near
A5 A4
JDDR3H.Pin203, 204
1U_0402_6.3V6-K
1U_0402_6.3V6-K
1U_0402_6.3V6-K
1U_0402_6.3V6-K
93 94 1 1 1 1
DDRB_MA3 95 VDD7 VDD8 96 DDRB_MA2
DDRB_MA1 97 A3 A2 98 DDRB_MA0
99 A1 A0 100
DDRB_CLK0 101 VDD9 VDD10 102 DDRB_CLK1 2 2 2 2
<7> DDRB_CLK0 CK0 CK1 DDRB_CLK1 <7>
<7> DDRB_CLK0# DDRB_CLK0# 103 104 DDRB_CLK1#
CK0# CK1# DDRB_CLK1# <7>
105 106
DDRB_MA10 107 VDD11 VDD12 108 DDRB_BS1#
A10/AP BA1 DDRB_BS1# <7>
<7> DDRB_BS0# DDRB_BS0# 109 110 DDRB_RAS#
BA0 RAS# DDRB_RAS# <7>
111 112
DDRB_WE# 113 VDD13 VDD14 114 DDRB_CS0#
<7> DDRB_WE# WE# S0# DDRB_CS0# <7>
<7> DDRB_CAS# DDRB_CAS# 115 116 DDRB_ODT0
CAS# ODT0 DDRB_ODT0 <7>
117 118
DDRB_MA13 119 VDD15 VDD16 120 DDRB_ODT1
A13 ODT1 DDRB_ODT1 <7>
<7> DDRB_CS1# DDRB_CS1# 121 122
123 S1# NC2 124
125 VDD17 VDD18 126
NCTEST VREF_CA +V_SM_VREF_CNT
127 128
B DDRB_DQ33 131 DQ32 DQ36 132 DDRB_DQ37 B
DQ33 DQ37 1 1
0.1U_0402_10V7-K
2.2U_0402_6.3V6-M
133 134 CD43 CD44

DDRB_DQS#4 135 VSS29 VSS30 136
139 DQS4 VSS31 140 DDRB_DQ38 2 2
DDRB_DQ35 143 DQ34 DQ39 144
145 DQ35 VSS33 146 DDRB_DQ44
DDRB_DQ41 149 DQ40 DQ45 150 All VREF traces should have 20 mil trace width
151 DQ41 VSS35 152 DDRB_DQS#5
153 VSS36 DQS#5 154 DDRB_DQS5
155 DM5 DQS5 156
Close to JDDR3H.126
161 DQ43 DQ47 162
DDRB_DQ48 163 VSS39 VSS40 164 DDRB_DQ52 +1.35V +VREF_DQA +1.35V +VREF_DQB +1.35V +V_SM_VREF_CNT
167 DQ49 DQ53 168
VSS41 VSS42 1
1
DDRB_DQS#6 169 170
173 DQS6 VSS43 174 DDRB_DQ54 +VREF_DQA_M3 RD3 +VREF_DQB_M3 RD4 +V_SM_VREF RD5
DDRB_DQ50 175 VSS44 DQ54 176 DDRB_DQ55 1K_0402_0.5% 1K_0402_0.5% 1K_0402_0.5%
DDRB_DQ51 177 DQ50 DQ55 178
2
2
179 DQ51 VSS45 180 DDRB_DQ60
VSS46 DQ60 RD6 RD7 RD8
DDRB_DQ56 181 182 DDRB_DQ61 1 2 1 2 1 2
DDRB_DQ57 183 DQ56 DQ61 184
DQ57 VSS47 1 2_0402_1% 1 2_0402_1% 1 2_0402_1%
185 186 DDRB_DQS#7
VSS48 DQS#7
1
1
187 188 DDRB_DQS7 CD45 CD46 CD47
189 DM7 DQS7 190 0.022U_0402_25V7-K 0.022U_0402_25V7-K 0.022U_0402_25V7-K
SPD setting (SA0, SA1) VSS49 VSS50 2 2 2
DDRB_DQ58 191 192 DDRB_DQ62 RD9 RD10 RD11
PU/PD by Channel A/B DQ58 DQ62
1
1
DDRB_DQ59 193 194 DDRB_DQ63 1K_0402_0.5% 1K_0402_0.5% 1K_0402_0.5%
A ->Channel A 00 195 DQ59 DQ63 196 A
2
2
1 RD14 2 197 VSS51 VSS52 198 RD15 RD12 RD13
->Channel B 01 SA0 EVENT#
10K_0402_5% 199 200 PM_SMBDATA 24.9_0402_1% 24.9_0402_1% 24.9_0402_1%
Dr-Bios.com
VDDSPD SDA PM_SMBDATA <11,17,39,43>
1 RD16 2 201 202 PM_SMBCLK
+3VS PM_SMBCLK <11,17,39,43>
2
2
10K_0402_5% 203 SA1 SCL 204
VTT1 VTT2 +0.675VS
1 1
205
G1 G2
206 !"#$%&!"'$(
CD48 CD49 Title
2.2U_0603_6.3V6-K 0.1U_0402_10V6-K LCN_DAN06-K4806-0103 Security Classification LC Future Center Secret Data
2 2
Issued Date 2012/12/05 Deciphered Date 2014/12/05 DDR3 SO-DIMMB/2
Rev
Custom 1.0
!##$%&'()*"*
5 4 3 2 1
5 4 3 2 1
JCMOS, JME Setting, Need Under DDR Door

+RTCVCC JCMOS1 @ 1. INTVRMEN, should always be pull high
RH1
1 2 PCH_RTCRST# 1 2
20K_0402_5%
* !Integrated VRM enable (Default)
H!
CH1 1 2 1U_0603_10V6-K !Integrated VRM disable
L!
LPT_PCH_M_EDS
2. Internal Voltage Regulator Enable: UH1A
JME1 @ This signal enables the internal 1.05 V regulators. BC8 SATA_PRX_DTX_N0
RH4 REV = 5 SATA_RXN_0 SATA_PRX_DTX_N0 <38>
1 2 PCH_SRTCRST# 1 2 PCH_RTCX1 B5 BE8 SATA_PRX_DTX_P0 SATA_PRX_DTX_P0 <38>
D RTCX1 SATA_RXP_0 D
20K_0402_5% HDD
CH2 1 2 1U_0603_10V6-K PCH_RTCX2 B4 AW8 SATA_PTX_DRX_N0 SATA_PTX_DRX_N0 <38>
RTCX2 SATA_TXN_0 AY8 SATA_PTX_DRX_P0 SATA_PTX_DRX_P0 <38>
RTC
+RTCVCC PCH_SRTCRST# B9 SATA_TXP_0
SRTCRST# BC10 SATA_PRX_DTX_N1
SATA_RXN_1 SATA_PRX_DTX_N1 <40>
RH5 1 2 1M_0402_5% SM_INTRUDER# A8 BE10 SATA_PRX_DTX_P1 SATA_PRX_DTX_P1 <40>
INTRUDER# SATA_RXP_1
SSD(NGFF)
RH2 1 2 330K_0402_5% PCH_INTVRMEN G10 AV10 SATA_PTX_DRX_N1
INTVRMEN SATA_TXN_1 SATA_PTX_DRX_N1 <40>
PCH_RTCX1 AW10 SATA_PTX_DRX_P1
SATA_TXP_1 SATA_PTX_DRX_P1 <40>
PCH_RTCRST# D9
RH3 RTCRST#
SATA
1 2 PCH_RTCX2 BB9 SATA_PRX_DTX_N2 SATA_PRX_DTX_N2 <38>
SATA_RXN_2 BD9 SATA_PRX_DTX_P2
10M_0402_5% SATA_RXP_2 SATA_PRX_DTX_P2 <38>
HDA_BCLK B25 ODD
HDA_BCLK AY13 SATA_PTX_DRX_N2
SATA_TXN_2 SATA_PTX_DRX_N2 <38>
YH1 HDA_SYNC A22 AW13 SATA_PTX_DRX_P2
HDA_SYNC SATA_TXP_2 SATA_PTX_DRX_P2 <38>
1 2
<47> HDA_SPKR HDA_SPKR AL10 BC12
32.768KHZ_12.5PF_9H03200019 SPKR SATA_RXN_3 BE12
SJ10000DM0J HDA_RST# C24 SATA_RXP_3
1 1 HDA_RST#
Y_CM31532768DZFT_2P AR13
SATA_TXN_3
AZALIA
CH9 CH10 HDA_SDIN0 L22 AT13
<46> HDA_SDIN0 HDA_SDI0 SATA_TXP_3
18P_0402_50V8-J 18P_0402_50V8-J
2 2 K22
HDA_SDI1 BD13
G22 SATA_RXN4/PERN1 BB13
HDA_SDI2 SATA_RXP4/PERP1
F22 AV15
HDA_SDI3 SATA_TXN4/PETN1 AW15
ME_FLASH RH6 1 2 0_0402_5% HDA_SDOUT A24 SATA_TXP4/PETP1
<48> ME_FLASH HDA_SDO BC14
B17 SATA_RXN5/PERN2 BE14
DOCKEN#/GPIO33 SATA_RXP5/PERP2
SATA Impedance Compensation :
C RH7 1 2 10K_0402_5% EC_WAKE# C22 AP15 C
+3V_PCH HDA_DOCK_RST#/GPIO13 SATA_TXN5/PETN2 --> Place the resistor within 500 mils of the PCH.
AR15
SATA_TXP5/PETP2 Avoid routing next to clock pins.
<48> EC_WAKE#
AY5 SATA_RCOMP RH8 1 2 7.5K_0402_1% +1.5VS
SATA_RCOMP
AP3 SATALED# RH9 1 2 10K_0402_5% +3VS
SATALED#
1 PCH_JTAG_TCK AB3 AT1 PCH_GPIO21 RH10 1 2 10K_0402_5%
@ T64
@T64 JTAG_TCK SATA0GP/GPIO21
During Reset", Immediately after Reset and S3/S4/S5 1 PCH_JTAG_TMS AD1 AU2 PCH_GPIO19 RH12 1 2 10K_0402_5%
@ T65
@T65 JTAG_TMS SATA1GP/GPIO19
1. JTAG_TDI, JTAG_TMS --> Int. PU 20K
1 PCH_JTAG_TDI AE2 BD4 +1.5VS 1. "#$%&'RH12(
()
JTAG
2. JTAG_TCK --> Int. PD 20K @ T66
@T66 JTAG_TDI SATA_IREF +1.5VS
3. JTAG_TDO --> High-Z @ T67
@T67
1 PCH_JTAG_TDO AD3
JTAG_TDO TP9
BA2
F8 BB2
TP25 TP8
C26
TP22
AB6
TP20
LYNX-POINT-DH82LPMS_BGA695 1 OF 11
SA00005U820
B B
HDA AUDIO SIGNAL
HDA AUDIO For Codec HDA STRAP

RTCVCC Circuit
HDA_BCLK RH21 1 2 33_0402_5% +RTCBATT +RTCVCC
HDA_BITCLK_AUDIO <46> +3VS +3V_PCH
HDA_RST# RH24 1 2 33_0402_5% HDA_RST_AUDIO# <46>
HDA_SDOUT RH25 1 2 33_0402_5% HDA_SDOUT_AUDIO <46> RH20 1 2 1K_0402_5%
RH22 1 @ 2 1K_0402_5% HDA_SPKR RH23 1 @ 2 1K_0402_5% HDA_SDOUT 1
+RTCBATT, +RTCVCC CH11
HIGH= Enable ( No Reboot ) Low = Disabled (Default)
+5VS * LOW= Disable (Default)
* High = Enabled Trace width = 20mils
2
1U_0603_10V6-K
Isolation 1. The internal pull-down is disabled after PLTRST# deasserts. [Flash Descriptor Security Overide]
QH4 @ 2. When Sampled : Rising edge of PWROK RTC External SRTCRST# Circuit
2
BSS138_NL_SOT23-3
G
RH26
HDA_SYNC 1 3 HDA_SYNC_R 1 2 HDA_SYNC_AUDIO <46>
D
33_0402_5% +3V_PCH
A RH128 1 2 0_0402_5% @ R422 RH27 1 @ 2 1K_0402_5% HDA_SYNC A

1M_0402_5%
1. This signal has a weak internal pull-down 15K
Dr-Bios.com
2
2. The internal pull-down on AZA_SYNC and AZA_SDO are enabled during reset.
Issued Date 2012/12/05 Deciphered Date 2014/12/05 PCH_RTC/HDA/SATA

Rev
Custom 1.0
!##$%&'()*"*
5 4 3 2 1
5 4 3 2 1
+3VS
PCH_HDMI_CLK RH28 1 2 2.2K_0402_5%

PCH_HDMI_DATA RH29 1 2 2.2K_0402_5%
PCH_DOCK_CLK RH136 1 2 2.2K_0402_5%

PCH_DOCK_DATA RH138 1 2 2.2K_0402_5%
D D
+3VS
1 2 LPT_PCH_M_EV
RH32 2.2K_0402_5% PCH_CRT_DDC_CLK UH1E
RH33 1 2 2.2K_0402_5% PCH_CRT_DDC_DAT
PCH_CRT_B T45 R40 PCH_HDMI_CLK
<35> PCH_CRT_B VGA_BLUE REV = 5 DDPB_CTRLCLK PCH_HDMI_CLK <34>
RH34 1 2 150_0402_1% PCH_CRT_B
RH35 1 2 150_0402_1% PCH_CRT_G PCH_CRT_G U44 R39 PCH_HDMI_DATA
<35> PCH_CRT_G VGA_GREEN DDPB_CTRLDATA PCH_HDMI_DATA <34>
RH36 1 2 150_0402_1% PCH_CRT_R
PCH_CRT_R V45 R35 PCH_DOCK_CLK
<35> PCH_CRT_R VGA_RED DDPC_CTRLCLK
PCH_CRT_DDC_CLK M43 R36 PCH_DOCK_DATA
<35> PCH_CRT_DDC_CLK VGA_DDC_CLK DDPC_CTRLDATA
PCH_CRT_DDC_DAT M45 N40
CRT
<35> PCH_CRT_DDC_DAT VGA_DDC_DATA DDPD_CTRLCLK
PCH_CRT_HSYNC N42 N38
<35> PCH_CRT_HSYNC VGA_HSYNC DDPD_CTRLDATA
+3VS PCH_CRT_VSYNC N44
<35> PCH_CRT_VSYNC VGA_VSYNC H45
CRT_IREF U40 DDPB_AUXN
DAC_IREF K43 PCH_DOCK_AUX#
DDPC_AUXN PCH_DOCK_AUX# <42>
U39
DISPLAY
RH37 1 2 10K_0402_5% DGPU_RST# VGA_IRTN J42
DDPD_AUXN
RH38 1 2 10K_0402_5% NVDD_PWR_EN PCH_EDP_PWM N36 H43
<36> PCH_EDP_PWM EDP_BKLTCTL DDPB_AUXP
LVDS
RH39 1 2 10K_0402_5% DGPU_PWR_EN PCH_ENBKL K36 K45 PCH_DOCK_AUX
<48> PCH_ENBKL EDP_BKLTEN DDPC_AUXP PCH_DOCK_AUX <42>
RH40 1 2 10K_0402_5% PCH_GPIO51 PCH_ENVDD G36 J44
C <36> PCH_ENVDD EDP_VDDEN DDPD_AUXP C
RH41 1 @ 2 10K_0402_5% PCH_GPIO55 K40 PCH_HDMI_HPD
DDPB_HPD PCH_HDMI_HPD <34>
Only for 15" TPANEL H20
<44> TPANEL PIRQA#
RH42 1 2 10K_0402_5% TPANEL K38 PCH_DOCK_HPD
DDPC_HPD PCH_DOCK_HPD <42>
RH43 1 2 10K_0402_5% PCI_PIRQB# PCI_PIRQB# L20
RH44 1 2 10K_0402_5% PCI_PIRQC# PIRQB# H39
RH45 1 2 10K_0402_5% PCI_PIRQD# PCI_PIRQC# K17 DDPD_HPD
PIRQC#
RH46 1 2 100K_0402_5% PCH_GS_ON# PCI_PIRQD# M20
PIRQD# PCI G17 ODD_DETECT#_DP_R
PIRQE#/GPIO2 ODD_DETECT#_DP_R <38>
RH47 1 2 10K_0402_5% PCH_ODD_DA# DGPU_RST# A12
GPIO50 F17 PCH_ODD_DA#
PIRQF#/GPIO3 PCH_ODD_DA# <38>
RH48 1 2 10K_0402_5% ODD_DETECT#_DP_R +VGA_CORE NVDD_PWR_EN B13
<63> NVDD_PWR_EN GPIO52 L15 SATA1_DEVSLP# To JIMIN1.Pin38
PIRQG#/GPIO4 SATA1_DEVSLP# <40>
RH49 1 2 10K_0402_5% SATA1_DEVSLP# +3VS_VGA DGPU_PWR_EN C12
<23,54> DGPU_PWR_EN GPIO54 M15 PCH_GS_ON#
PIRQH#/GPIO5 PCH_GS_ON# <33>
RH50 1 @ 2 10K_0402_5% DGPU_GC6_EN PCH_GPIO51 C10
GPIO51 AD10 PCI_PME#
DGPU_GC6_EN A10 PME# PCI_PME# <42> Integrated Pull-Up 20K
<27> DGPU_GC6_EN GPIO53 Y11 PLT_RST#
PLTRST# PLT_RST# <17,39,41,42,44,48>
PCH_GPIO55 AL6
GPIO55
1
RH51 1 2 649_0402_1% CRT_IREF
RH52 1 2 100K_0402_5% PCH_ENBKL SA00005U830 RH53
100K_0402_5%
RH54 1 @ 2 1K_0402_5% DGPU_PWR_EN +3VS
2
RH55 1 @ 2 10K_0402_5% DGPU_GC6_EN
5
RH56 1 @ 2 10K_0402_5% DGPU_RST#
PLT_RST# 2
P
B B 4 B
Y PLTRST_VGA# <23>
DGPU_RST# 1
A
G
UH2 DIS@
NC7SZ08P5X_NL_SC70-5
A16 swap overide Strap/Top-Block For ESD

Swap Override jumper
Boot BIOS Straps (BBS)
PCH_ODD_DA#
BBS_BIT1 BBS_BIT0 1
Low = A16 swap Boot BIOS Location
(GPIO51) (GPIO19) @ CH12
override/Top-Block 220P_0402_50V8-J
2
PCI_GNT3# Swap Override enabled 0 0 LPC
A **High=Default 0 1 Reserved (NAND) A
*
Dr-Bios.com
1 0 PCI
1. The signal has a weak internal pull-up,
which is disabled after PLTRST# deasserts.
1 1 SPI *
2. When sampled : Rising edge of PWROK Security Classification LC Future Center Secret Data Title
1. GPIO51/19 has weak internal pull-up via 20kohm Issued Date 2012/12/05 Deciphered Date 2014/12/05 PCH_CRT/EDP/DDP
2. The internal pull-up is disabled after PLTRST# deasserts. THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
3. GPIO51 (bit 11) at the rising edge of PWROK AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
SATA1GP/GPIO19 (bit 10) at the rising edge of PWROK.
!"#$%&'()*+*
5 4 3 2 1
5 4 3 2 1
+3V_PCH +3VS
RH57 1 2 10K_0402_5% SUSWARN#_R
1
+3VALW
CH13
D RH58 1 2 200K_0402_5% AC_PRESENT .1U_0402_16V4-Z D
2
5
RH59 1 2 10K_0402_5% EC_RSMRST# DPWROK RH60 1 2 100K_0402_5%
VGATE 2
P
<64> VGATE B 4 SYS_PWROK
PCH_PWROK 1 Y
A
100 kOhms ±1% pull-down to GND
1
1
UH3
3
SUSACK#_R RH61 1 @ 2 0_0402_5% SUSWARN#_R MC74VHC1G08DFT2G SC70 5P @ R1
RH62 100K_0402_5%
Stuff RH289 if EC does not want to 10K_0402_5%
2
involve in the handshake mechanism
2
for the DeepSX state entry and exit
LPT_PCH_M_EDS
<5> DMI_CTX_PRX_N[3:0] UH1B
DMI_CTX_PRX_N0 AW22
DMI_RXN_0 REV = 5
DMI_CTX_PRX_N1 AR20
DMI_RXN_1 AJ35 FDI_CTX_PRX_N0
FDI_RXN_0 FDI_CTX_PRX_N0 <8>
DMI_CTX_PRX_N2 AP17
DMI_CTX_PRX_N3 AV20 DMI_RXN_2 AL35 FDI_CTX_PRX_N1
<5> DMI_CTX_PRX_P[3:0] DMI_RXN_3 FDI_RXN_1 FDI_CTX_PRX_N1 <8>
C DMI_CTX_PRX_P0 AY22 AJ36 FDI_CTX_PRX_P0 C
DMI_RXP_0 FDI_RXP_0 FDI_CTX_PRX_P0 <8>
DMI_CTX_PRX_P1 AP20
DMI_RXP_1 FDI AL36 FDI_CTX_PRX_P1
FDI_RXP_1 FDI_CTX_PRX_P1 <8>
DMI_CTX_PRX_P2 AR17
DMI_CTX_PRX_P3 AW20 DMI_RXP_2 AV43
DMI
<5> DMI_CRX_PTX_N[3:0] DMI_RXP_3 TP16
DMI_CRX_PTX_N0 BD21 AY45
DMI_CRX_PTX_N1 BE20 DMI_TXN_0 TP5
DMI_TXN_1 AV45
DMI_CRX_PTX_N2 BD17 TP15
DMI_CRX_PTX_N3 BE18 DMI_TXN_2 AW44
<5> DMI_CRX_PTX_P[3:0] DMI_TXN_3 TP10
DMI_CRX_PTX_P0 BB21 AL39 FDI_CSYNC
DMI_TXP_0 FDI_CSYNC FDI_CSYNC <5>
DMI_CRX_PTX_P1 BC20
DMI_TXP_1 AL40 FDI_INT
FDI_INT FDI_INT <5>
DMI_CRX_PTX_P2 BB17
DMI_CRX_PTX_P3 BC18 DMI_TXP_2 AT45 FDI_IREF RH65 1 2 0_0402_5%
DMI_TXP_3 FDI_IREF +1.5VS
+1.5VS BE16 AU42

DMI_IREF TP17
AW17 AU44
TP12 TP13
DSWVREN must be always pulled high to +RTCVCC
AV17 AR44 FDI_RCOMP RH66 1 2 7.5K_0402_1% +1.5VS DSWVREN - Internal Deep Sleep 1.05V regulator
TP7 FDI_RCOMP
+1.5VS RH67 1 2 7.5K_0402_1% DMI_RCOMP AY17
DMI_RCOMP
***H!
L!
!Enable
!Disable
!
EC to PCH <48> SUSACK# RH68 1 2 0_0402_5% SUSACK#_R R6 C8 DSWVRMEN RH69 1 2 330K_0402_5% +RTCVCC
SUSACK# DSWVRMEN
1 2 AM1 System Power L13 1 2
+3VS RH70 10K_0402_5% SYS_RESET# DPWROK RH71 0_0402_5% EC_DPWROK EC_DPWROK <48> For Deep S3
SYS_RESET# Management DPWROK
B SYS_PWROK AD7 K3 WAKE# RH72 1 @ 2 0_0402_5% WLAN_WAKE# B
SYS_PWROK WAKE# WLAN_WAKE# <39> For WLAN WAKE# (Disable)
APWROK may come <48,8> PCH_PWROK RH73 1 2 0_0402_5% PWROK F10 AN7 PM_CLKRUN#
PWROK CLKRUN# PM_CLKRUN# <44>
up earlier than +3VALW
<48> PCH_APWROK RH74 1 2 0_0402_5% APWROK AB7 U7 SUS_STAT# 1
PWROK but no APWROK SUS_STAT#/GPIO61 T72 @
later DRAMPWROK H3 Y6 SUSCLK 1 WAKE# RH63 1 2 10K_0402_5%
<6> DRAMPWROK DRAMPWROK SUSCLK/GPIO62 T73 @
EC_RSMRST# J2 Y7 PM_SLP_S5#
<48> EC_RSMRST# RSMRST# SLP_S5#/GPIO63 PM_SLP_S5# <48> +3VS
PCH to EC RH75 1 2 0_0402_5% SUSWARN#_R J4 C6 PM_SLP_S4#
<48> SUSWARN# SUSWARN#/SUSPWRNACK/GPIO30 SLP_S4# PM_SLP_S4# <48>
PM_CLKRUN# RH64 1 2 10K_0402_5%
PBTN_OUT# K1 H1 PM_SLP_S3#
<48> PBTN_OUT# PWRBTN# SLP_S3# PM_SLP_S3# <48>
AC_PRESENT E6 F3 PM_SLP_A#
<48> AC_PRESENT ACPRESENT/GPIO31 SLP_A# PM_SLP_A# <48>
RH76 1 2 10K_0402_5% PCH_BATLOW# K7 F1 PM_SLP_SUS#_R RH77 1 2 0_0402_5% PM_SLP_SUS#
For Deep S3
+3VALW BATLOW#/GPIO72 SLP_SUS# PM_SLP_SUS# <48,55>
+3V_PCH RH78 1 2 10K_0402_5% RI# N4 AY3 H_PM_SYNC Can be left NC when IAMT is
RI# PMSYNCH H_PM_SYNC <6>
not support on the platfrom
AB10 G5 PCH_SLPLAN# 1
TP21 SLP_LAN# T74 @
D2 Can be left NC if no use integrated LAN.
SLP_WLAN#/GPIO29
10/06 Test point request
SUSCLK/GPIO62
SA00005U830 This signal has a weak internal pull-up.
APWROK only for A phase 0 = Disable PLL On-Die voltage regulator.
* 1 = Enable PLL On-Die voltage regulator.
NOTES:
A PWROK RH13 1 @ 2 0_0402_5% APWROK A
1. The internal pull-up is disabled after RSMRST#
deasserts.
Dr-Bios.com
2. This signal is in the Suspend well.
Issued Date 2012/12/05 Deciphered Date 2014/12/05 PCH_DMI/FDI/PM

Rev
Custom 1.0
!##$%&'()*"*
5 4 3 2 1
5 4 3 2 1
LPT_PCH_M_EDS
UH1C
REV = 5 +3V_PCH
Y43 AB35 CLK_PCIE_VGA#
D CLKOUT_PCIE_N_0 CLKOUT_PEG_A_N CLK_PCIE_VGA# <23> D
Y45 AB36 CLK_PCIE_VGA CLK_REQ_GPU#_R RH79 1 2 10K_0402_5%
CLKOUT_PCIE_P_0 CLKOUT_PEG_A_P CLK_PCIE_VGA <23>
+3V_PCH RH80 1 2 10K_0402_5% PCH_GPIO73 AB1 AF6 CLK_REQ_GPU#_R CLK_REQ_GPU#_R <23> PCH_GPIO56 RH81 1 2 10K_0402_5%
PCIECLKRQ0#/GPIO73 PEG_A_CLKRQ#/GPIO47
AA44 Y39
AA42 CLKOUT_PCIE_N_1 CLKOUT_PEG_B_N
1. No use Native function CLKOUT_PCIE_P_1 Y38
2. When configured as GPIO, default direction is Output (GPO). AF1 CLKOUT_PEG_B_P
PCIECLKRQ1#/GPIO18 U4 PCH_GPIO56
CLK_PCIE_CR# AB43 PEG_B_CLKRQ#/GPIO56
<41> CLK_PCIE_CR# CLKOUT_PCIE_N_2 AF39 CLK_CPU_DMI#
CLKOUT_DMI_N CLK_CPU_DMI# <6>
CardReader, Core CLK_PCIE_CR AB45
<41> CLK_PCIE_CR CLKOUT_PCIE_P_2 AF40 CLK_CPU_DMI
CLKOUT_DMI_P CLK_CPU_DMI <6>
<41> CLKREQ_CR# CLKREQ_CR# AF3
PCIECLKRQ2#/GPIO20/SMI# AJ40 CLK_CPU_SSC_DPLL#
CLKOUT_DP_N CLK_CPU_SSC_DPLL# <6>
CLK_PCIE_LAN# AD43 AJ39 CLK_CPU_SSC_DPLL
<42> CLK_PCIE_LAN# CLKOUT_PCIE_N_3 CLKOUT_DP_P CLK_CPU_SSC_DPLL <6>
LAN, Suspend CLK_PCIE_LAN AD45
<42> CLK_PCIE_LAN CLKOUT_PCIE_P_3
<42> CLKREQ_LAN# CLKREQ_LAN# T3 AF35 CLK_CPU_DPLL#
PCIECLKRQ3#/GPIO25 CLKOUT_DPNS_N CLK_CPU_DPLL# <6>
AF36 CLK_CPU_DPLL
CLKOUT_DPNS_P CLK_CPU_DPLL <6>
CLK_PCIE_WLAN# AF43
<39> CLK_PCIE_WLAN# CLKOUT_PCIE_N_4
WLAN, Suspend CLK_PCIE_WLAN AF45 AY24 CLK_BUF_CPU_DMI# RH83 1 2 10K_0402_5%
<39> CLK_PCIE_WLAN CLKOUT_PCIE_P_4 CLKIN_DMI_N
<39> CLKREQ_WLAN# CLKREQ_WLAN# V3 AW24 CLK_BUF_CPU_DMI RH84 1 2 10K_0402_5%
PCIECLKRQ4#/GPIO26 CLKIN_DMI_P
AE44 AR24 CLKIN_BUF_DMI2# RH85 1 2 10K_0402_5%
AE42 CLKOUT_PCIE_N5 CLKIN_GND_N AT24 CLKIN_BUF_DMI2 RH86 1 2 10K_0402_5%
RH87 1 2 10K_0402_5% PCH_GPIO44 AA2 CLKOUT_PCIE_P_5 CLKIN_GND_P
+3V_PCH PCIECLKRQ5#/GPIO44 H33 CLK_BUF_DREF_96M# RH88 1 2 10K_0402_5%
AB40 CLKIN_DOT96N G33 CLK_BUF_DREF_96M RH89 1 2 10K_0402_5%
AB39 CLKOUT_PCIE_N_6 CLKIN_DOT96P
RH90 1 2 10K_0402_5% PCH_GPIO45 AE4 CLKOUT_PCIE_P_6 BE6 CLK_BUF_PCIE_SATA# RH91 1 2 10K_0402_5%
+3V_PCH PCIECLKRQ6#/GPIO45 CLKIN_SATA_N BC6 CLK_BUF_PCIE_SATA RH92 1 2 10K_0402_5%
C AJ44 CLKIN_SATA_P C
CLKOUT_PCIE_N_7 F45 CLK_BUF_ICH_14M RH93 1 2 10K_0402_5%
AJ42 REFCLK14IN D17 CLK_PCI_LOOPBACK
CLKOUT_PCIE_P_7 CLKIN_33MHZLOOPBACK
+3V_PCH RH94 1 2 10K_0402_5% PCH_GPIO46 Y3 AM43 PCH_XTAL25_IN

PCIECLKRQ7#/GPIO46 XTAL25_IN AL44 PCH_XTAL25_OUT
AH43 XTAL25_OUT
When configured as GPIO, default direction is CLKOUT_ITPXDP_N C40 PCH_GPIO64
!"#$%RH87, 90 and 94&
Input (GPI).! &' AH45 CLKOUTFLEX0/GPIO64
Remove TP CLKOUT_ITPXDP_P F38 PCH_GPIO65
D44 CLKOUTFLEX1/GPIO65
CLKOUT_33MHZ0 F36 LAN_25M RH95 1 @ 2 0_0402_5%
CLKOUTFLEX2/GPIO66 PCH_LAN_25M <42>
RH96 1 2 22_0402_5% CLK_PCI_EC_R E44
<48> CLK_PCI_EC CLKOUT_33MHZ1 F39 PCH_GPIO67 Reseve for SKU ID
CLKOUTFLEX3/GPIO67 PCH_GPIO67 <19>
RH97 1 @ 2 22_0402_5% PCH_CLK_PCI_DB B42
<39> CLK_PCI_DB CLKOUT_33MHZ2 AM45 +1.5VS +1.5VS
RH98 1 TPM@ 2 22_0402_5% CLK_PCI_TPM_R F41 ICLK_IREF
<44> CLK_PCI_TPM CLKOUT_33MHZ3 AD39
RH99 1 2 22_0402_5% PCI_LOOPBACKOUT A40 TP19 AD38
CLKOUT_33MHZ4 TP18
CLK_PCI_LOOPBACK AN44 PCH_CLK_BIASREF RH100 1 2 7.5K_0402_1% +1.05VS_+1.5VS_RUN +1.5VS
DIFFCLK_BIASREF
CLOCK SIGNAL
SA00005U830
B B
+3V_PCH PCH Crystal Project Phase ID

+3VS
RH101 1 2 10K_0402_5% CLKREQ_LAN# PCH_XTAL25_IN

Project Phase PCH_GPIO64 PCH_GPIO65
RH31 1 2 10K_0402_5% PCH_GPIO64
RH103 1 2 10K_0402_5% CLKREQ_WLAN# PCH_XTAL25_OUT RH104 1 2 1M_0402_5% SDV, FVT 0 0 RH82 1 2 10K_0402_5% PCH_GPIO65
YH2 SIT2 (R 0.5)

+3VS 0 1
1 4 RH152 1 @ 2 10K_0402_5% PCH_GPIO64
RH105 1 2 10K_0402_5% CLKREQ_CR# OSC1 GND2
2 3
SIT (R 0.4) 1 0 RH162 1 @ 2 10K_0402_5% PCH_GPIO65
GND1 OSC2
1
25MHZ_10PF_7V25000014
1 * SVT 1 1
Reserve for EMI please close to PCH CH15 CH16
12P_0402_50V8-J 12P_0402_50V8-J
A 2 2 A
RH102 CH14
CLK_PCI_LOOPBACK 1 @ 2 1 @ 2
Dr-Bios.com
33_0402_5% 22P_0402_50V8-J
Change to 7V25000014 (TXC),. Cap 15pF*2
Issued Date 2012/12/05 Deciphered Date 2014/12/05 PCH_PCIE/CLK

Rev
Custom 1.0
!##$%&'()*"*
5 4 3 2 1
5 4 3 2 1
LPT_PCH_M_EDS
UH1D
+3V_PCH
EC, MINI CARD and TPM Module debug port
REV = 5
<39,44,48> LPC_AD[3:0]
N7 PCH_SMBALERT# PCH_SMBALERT# RH106 1 2 10K_0402_5%
LPC_AD0 A20 SMBALERT#/GPIO11
LAD_0 R10 PCH_SMBCLK PCH_GPIO60 RH107 1 2 1K_0402_5%
SMBus
LPC_AD1 C20 SMBCLK
LAD_1 U11 PCH_SMBDATA PCH_GPIO74 RH108 1 2 10K_0402_5%
LPC_AD2 A18 SMBDATA
LPC
LAD_2 N8 PCH_GPIO60
LPC_AD3 C18 SML0ALERT#/GPIO60 PCH_TD_IREF RH109 1 2 8.2K_0402_1%
LAD_3 U8 PCH_SML0CLK
D LPC_FRAME# B21 SML0CLK D
<39,44,48> LPC_FRAME# LFRAME# R7 PCH_SML0DATA
Touch Panel
+3VS D21 SML0DATA
LDRQ0# H6 PCH_GPIO74
RH110 1 2 10K_0402_5% SERIRQ PCH_GPIO23 G20 SML1ALERT#/PCHHOT#/GPIO74
LDRQ1#/GPIO23 K6 PCH_SML1CLK
RH119 1 2 10K_0402_5% PCH_GPIO23 SERIRQ AL11 SML1CLK/GPIO58 RPH3 +3V_PCH
<44,48> SERIRQ SERIRQ N11 PCH_SML1DATA PCH_SML1CLK 1 8
SML1DATA/GPIO75 PCH_SML1DATA 2 7
PCH_SMBDATA 3 6
SPI_CLK_8MB RH111 1 2 33_0402_5% AF11 PCH_SMBCLK 4 5
SPI_CLK_4MB RH112 1 2 33_0402_5% SPI_CLK AJ11 CL_CLK
SPI
SPI_CLK AF10 2.2K_0804_5%
SPI_CS0#_8MB RH113 1 2 0_0402_5% SPI_CS0# AJ7 C-Link CL_DATA SD30922010T
SPI_CS0# AF7
SPI_CS1#_4MB RH114 1 2 0_0402_5% SPI_CS1# AL7 CL_RST# RPH4 +3V_PCH
SPI_CS1# PCH_SML0CLK 1 8
AJ10 PCH_SML0DATA 2 7
SPI_SI_8MB RH115 1 2 33_0402_5% SPI_CS2# BA45 3 6
SPI_SI_4MB RH116 1 2 33_0402_5% SPI_SI AH1 TP1 4 5
SPI_MOSI BC45
SPI_SO_8MB RH117 1 2 33_0402_5% SPI_SO AH3 Thermal TP2 2.2K_0804_5%
SPI_SO_4MB RH118 1 2 33_0402_5% SPI_MISO BE43 SD30922010T
AJ4 TP4
SPI_IO2_8MB RH129 1 2 33_0402_5% SPI_IO2 SPI_IO2 BE44
SPI_IO2_4MB RH130 1 2 33_0402_5% AJ2 TP3
SPI_IO3 AY43 PCH_TD_IREF
SPI_IO3_8MB RH131 1 2 33_0402_5% SPI_IO3 TD_IREF
SPI_IO3_4MB RH132 1 2 33_0402_5%
Near U4M1 and U8M1 LYNX-POINT-DH82LPMS_BGA695 3 OF 11

C +3V_SPI SA00005U830 C
RH16 1 2 1K_0402_5% SPI_IO2

RH17 1 2 1K_0402_5% SPI_IO3 SM Bus
Near U4M1 DIMM1, DIMM2, WLAN(@), CP, Security EEPROM
+3VS +3VS
RH121 1 2 4.7K_0402_5%
2
8MB + 4MB SPI ROM, 5MB ME(SBA), Security EEPROM
G
RH123 1 2 4.7K_0402_5%
PCH_SMBCLK 6 1 PM_SMBCLK
Security EEPROM
S
+3VS PM_SMBCLK <11,12,39,43>
RH124
D
5
1 @ 2 USROM1 QH1A
G
+3VS
1 8 2N7002KDWH_SOT363-6
0_0402_5% NC_1 VCC
2 7 1 SB00000YR00
PLT_RST# 3 NC_2 WP 6 PM_SMBCLK
<14,39,41,42,44,48> PLT_RST# PROT# SCL
4 5 PM_SMBDATA C1 PCH_SMBDATA 3 4 PM_SMBDATA
S
GND SDA PM_SMBDATA <11,12,39,43>
0.1U_0402_16V4Z
D
PCA24S08AD_SO8 2 QH1B
SA00004MK00/SA00004ML00 2N7002KDWH_SOT363-6
SB00000YR00
+3V_SPI +3VS GPU, EC, Thermal Sensor

SBA Fun. Power rail
+3VS RH125 1 @ 2 0_0402_5% +3V_SPI
B B
2N7002KDWH
2
0.085 A
G
+3VM RH127 1 2 0_0402_5% Vth= min 1V, max 2.5V
ESD 2KV
PCH_SML1CLK 6 1 EC_SMB_CK3
S
EC_SMB_CK3 <23,32,48>
D
5
QH2A
8MB(64Mb) 4MB(32Mb)
G
2N7002KDWH_SOT363-6
SB00000YR00
PCH_SML1DATA 3 4 EC_SMB_DA3
S
EC_SMB_DA3 <23,32,48>
D
QH2B
2N7002KDWH_SOT363-6
SB00000YR00
RH133 CH17 For EMI RH134 CH18 For EMI Touch Panel
SPI_CLK_8MB 1 @ 2 1 @ 2 SPI_CLK_4MB 1 @ 2 1 @ 2
+3VS +3VS
10_0402_5% 10P_0402_50V8-J 10_0402_5% 10P_0402_50V8-J
RH135 1 2 2.2K_0402_5%
2
G
+3V_SPI +3V_SPI RH137 1 2 2.2K_0402_5%
U8M1 U4M1
SPI_CS0#_8MB 1 8 2 SPI_CS1#_4MB 1 8 2
CS# VCC SPI_SO_4MB 2 CS# VCC 7 SPI_IO3_4MB PCH_SML0CLK 6 1 SMB_CLK_TPANEL
S
DO HOLD# SMB_CLK_TPANEL <44>
SPI_SO_8MB 2 7 SPI_IO3_8MB CH19 SPI_IO2_4MB 3 6 SPI_CLK_4MB CH20
D
DO HOLD# WP# CLK
5
0.1U_0402_10V7-K 4 5 SPI_SI_4MB 0.1U_0402_10V7-K QH3A
G
SPI_IO2_8MB 3 6 SPI_CLK_8MB 1 GND DI 1 2N7002KDWH_SOT363-6
A WP# CLK W25Q32FVSSIQ_SO8 SB00000YR00 A
4 5 SPI_SI_8MB SA00005P500
GND DI PCH_SML0DATA 3 4 SMB_DATA_TPANEL
Dr-Bios.com
S
SMB_DATA_TPANEL <44>
D
W25Q64FVSSIG_SO8
SA00005P500 QH3B
SA000039A2J SA00003K80J --> EOL 2N7002KDWH_SOT363-6
SB00000YR00
Issued Date 2012/12/05 Deciphered Date 2014/12/05 PCH_LPC/SPI/SM BUS

Rev
Custom 1.0
!##$%&'()*"*
5 4 3 2 1
5 4 3 2 1
D D
LPT_PCH_M_EDS
UH1I
AW31 B37 USB20_N0

PERN1/USB3RN3 REV = 5 USB2N0 USB20_N0 <37>
AY31 D37 USB20_P0 LEFT USB20 (Front)
PERP1/USB3RP3 USB2P0 USB20_P0 <37>
A38 USB20_N1
USB2N1 USB20_N1 <37>
BE32 C38 USB20_P1 LEFT USB20 (Back)
PETN1/USB3TN3 USB2P1 USB20_P1 <37>
BC32 A36
PETP1/USB3TP3 USB2N2 C36
AT31 USB2P2 A34 USB20_N3
PERN2/USB3RN4 USB2N3 USB20_N3 <42>
AR31 C34 USB20_P3 Docking USB3.0
PERP2/USB3RP4 USB2P3 USB20_P3 <42>
B33 USB20_N4
BD33 D33 USB20_P4 Touch Panel
PETN2/USB3TN4 USB2P4 USB20_P4 <44>
BB33 F31 USB20_N5 1
PETP2/USB3TP4 USB2N5 T77 @
G31 USB20_P5 1
USB2P5 T78 @
K31
PCIE_PRX_DTX_N3 AW33 USB2N6 L31
<41> PCIE_PRX_DTX_N3 PERN_3 USB2P6
Some PCH config not support USB port 6 & 7.
<41> PCIE_PRX_DTX_P3 PCIE_PRX_DTX_P3 AY33 G29
PERP_3 USB2N7 H29
CH21 1 2 0.1U_0402_10V7-K PCIE_PTX_DRX_N3 BE34 USB2P7 A32
CardReader <41> PCIE_PTX_C_DRX_N3 PETN_3 USB2N8
CH22 1 2 0.1U_0402_10V7-K PCIE_PTX_DRX_P3 BC34 C32
<41> PCIE_PTX_C_DRX_P3 PETP_3 USB2P8 A30 USB20_N9
<42> PCIE_PRX_DTX_N4 PCIE_PRX_DTX_N4 AT33 C30 USB20_P9 RIGHT USB20 Sleep&charge (S/B), Debug port,
PERN_4 USB2P9 USB20_P9 <41>
<42> PCIE_PRX_DTX_P4 PCIE_PRX_DTX_P4 AR33 B29 USB20_N10
C PERP_4 USB2N10 USB20_N10 <39> C
LAN D29 USB20_P10 WLAN
USB2P10 USB20_P10 <39>
CH23 1 2 0.1U_0402_10V7-K PCIE_PTX_DRX_N4 BE36 A28 USB20_N11
<42> PCIE_PTX_C_DRX_N4 PETN_4 USB2N11 USB20_N11 <40>
CH24 1 2 0.1U_0402_10V7-K PCIE_PTX_DRX_P4 BC36 C28 USB20_P11 WWAN
<42> PCIE_PTX_C_DRX_P4 PETP_4 USB2P11 USB20_P11 <40>
G26 USB20_N12
USB20_N12 <44>
PCIe
PCIE_PRX_DTX_N5 AW36 USB2N12 F26 USB20_P12
<39> PCIE_PRX_DTX_N5 FingerPrint (S/B)
USB
PERN_5 USB2P12 USB20_P12 <44>
WLAN <39> PCIE_PRX_DTX_P5 PCIE_PRX_DTX_P5 AV36 F24 USB20_N13
PERP_5 USB2N13 USB20_N13 <36>
G24 USB20_P13 CAMERA
USB2P13 USB20_P13 <36>
CH25 1 2 0.1U_0402_10V7-K PCIE_PTX_DRX_N5 BD37
<39> PCIE_PTX_C_DRX_N5 PETN_5
CH26 1 2 0.1U_0402_10V7-K PCIE_PTX_DRX_P5 BB37
<39> PCIE_PTX_C_DRX_P5 PETP_5 AR26 USB30_RX_N1
USB3RN1 USB30_RX_N1 <42>
AY38 AP26 USB30_RX_P1 RIGHT Docking
PERN_6 USB3RP1 USB30_RX_P1 <42>
AW38 BE24 USB30_TX_N1
PERP_6 USB3TN1 USB30_TX_N1 <42>
BD23 USB30_TX_P1
USB3TP1 USB30_TX_P1 <42>
BC38 AW26 USB30_RX_N2
PETN_6 USB3RN2 USB30_RX_N2 <37>
BE38 AV26 USB30_RX_P2 LEFT USB30 (Front)
PETP_6 USB3RP2 USB30_RX_P2 <37>
BD25 USB30_TX_N2
USB3TN2 USB30_TX_N2 <37>
AT40 BC24 USB30_TX_P2
PERN_7 USB3TP2 USB30_TX_P2 <37>
AT39 AW29 USB30_RX_N5
PERP_7 USB3RN5 USB30_RX_N5 <37>
AV29 USB30_RX_P5 LEFT USB30 (Back)
USB3RP5 USB30_RX_P5 <37>
BE40 BE26 USB30_TX_N5
PETN_7 USB3TN5 USB30_TX_N5 <37>
BC40 BC26 USB30_TX_P5
PETP_7 USB3TP5 USB30_TX_P5 <37>
AR29
AN38 USB3RN6 AP29
AN39 PERN_8 USB3RP6 BD27 +3V_PCH
PERP_8 USB3TN6 BE28
BD42 USB3TP6 RPH1
BD41 PETN_8 K24 USBRBIAS RH1391 2 22.6_0402_1% USB_OC1# 1 8
PETP_8 USBRBIAS# K26 USB_OC2# 2 7
USBRBIAS Within 500 mils USB_OC5# 3 6
+1.5VS BE30 M33 USB_OC0# 4 5
PCIE_IREF TP24 L33
TP23 10K_0804_8P4R_5%
B BC30 P3 USB_OC0# SD300002P0T B
TP11 OC0#/GPIO59 V1 USB_OC1#
USB_OC0# <37> USB Port0, 1 (LEFT USB)
OC1#/GPIO40 U2 USB_OC2#
BB29 OC2#/GPIO41 P1 USB_OC3# RPH2
TP6 OC3#/GPIO42 M3 USB_OC4# USB_OC3# 1 8
R2 OC4#/GPIO43 T1 USB_OC5# PCH_3G_DET# 2 7
OC5#/GPIO9 USB_OC5# <41> USB Port5 (Sleep&Charge)
+1.5VS 1 2 PCIE_RCOMP BD29 N2 PCH_3G_DET# USB_OC7# 3 6
PCIE_RCOMP OC6#/GPIO10 PCH_3G_DET# <40>
M1 USB_OC7# USB_OC4# 4 5
7.5K_0402_1% OC7#/GPIO14
10K_0804_8P4R_5%
LYNX-POINT-DH82LPMS_BGA695 9 OF 11 SD300002P0T
SA00005U830
USB2.0 : USB3.0 USB2.0 OC# Note

OC#0-3 --> Port 0-7
OC#4-7 --> Port 8-13 Port1 Port3 X Docking (Right)
Port2 Port0 OC0# LEFT USB (Front)

A OC[3:0]# should be connected with USB 2.0 ports 0 - 7 and any 4 A
of USB 3.0 ports 1 - 6. Port5 Port1 OC0# LEFT USB (Back)
Dr-Bios.com
X Port9 OC5# Sleep&Charge (Right)
Issued Date 2012/12/05 Deciphered Date 2014/12/05 PCH_PCIE/USB/OC#

Rev
Custom 1.0
!##$%&'()*"*
5 4 3 2 1
5 4 3 2 1
LPT_PCH_M_EDS
UH1F
+3VS <23,48> GC6_EVENT# RH194 1 @ 2 0_0402_5% GC6_EVENT#_R AT8

BMBUSY#/GPIO0 REV = 5
RH140 1 2 0_0402_5% FN_LED#_R F13
<45> FN_LED# TACH1/GPIO1
RH141 1 2 10K_0402_5% FN_LED#_R
RH142 1 2 0_0402_5% F1_LED#_R A14
<45> F1_LED# TACH2/GPIO6
RH143 1 2 10K_0402_5% F1_LED#_R
D G15 CPU/Misc D
<48> EC_SCI# EC_SCI#
RH144 1 2 10K_0402_5% F4_LED#_R TACH3/GPIO7
<42> DOCK_DETECT# DOCK_DETECT# Y1

RH145 1 2 10K_0402_5% GC6_EVENT#_R GPIO8
K13
RH146 1 2 10K_0402_5% EC_SCI# LAN_PHY_PWR_CTRL/GPIO12 AN10 GATEA20
TP14 GATEA20 <48>
WWAN_ON AB11
<39> WWAN_ON GPIO15
RH147 1 2 10K_0402_5% PCH_BT_DISABLE# AY1
PCH_GPIO16 AN2 PECI
RH148 1 2 10K_0402_5% BT_DET# SATA4GP/GPIO16 AT6 KBRST#
GPIO RCIN# KBRST# <48>
<27,54,62,63> DGPU_PWROK DGPU_PWROK C14
RH149 1 2 10K_0402_5% 3G_OFF# TACH0/GPIO17 AV3 H_CPUPWRGD
PROCPWRGD H_CPUPWRGD <6>
PCH_BT_DISABLE# BB4
<39> PCH_BT_DISABLE# SCLOCK/GPIO22
RH150 1 2 10K_0402_5% GPS_OFF# AV1 PCH_THERMTRIP#
ODD_EN Y10 THRMTRIP#
<38> ODD_EN GPIO24 AU4 PLTRST_PROC#
PLTRST_PROC# PLTRST_PROC# <6>
RH151 1 2 200K_0402_5% ODD_DETECT# For tempo detect PCH_MSATA_DET R11
GPIO27 N10
RH153 1 @ 2 10K_0402_5% ODD_DETECT#_R TRACKP_ON AD11 VSS_N10
<43> TRACKP_ON GPIO28
RH18 1 @ 2 0_0402_5% ODD_DETECT#_R AN6
RH154 1 2 10K_0402_5% PCH_GPIO35
<39> PCH_BT_ON# GPIO34 Output
PCH_GPIO35 AP1
RH155 1 2 10K_0402_5% CMOS_ON# GPIO35/NMI# PCH_THERMTRIP# RH156 1 2 390_0402_5% H_THERMTRIP# <6>
<38> ODD_DETECT#_DP RH19 1 @ 2 0_0402_5% ODD_DETECT# AT3 Input
RH157 1 2 10K_0402_5% GATEA20 SATA2GP/GPIO36 RH11 1 @ 2 0_0402_5% VGA_THERMTRIP# <23>
PCH_GPIO37 AK1
RH158 1 2 10K_0402_5% KBRST# SATA3GP/GPIO37
PCH_GPIO38 AT7
RH15 1 2 10K_0402_5% PCH_GPIO37 SLOAD/GPIO38
3G_OFF# AM3 A2
<40> 3G_OFF# SDATAOUT0/GPIO39 VSS_NCTF_5 A41
C GPS_OFF# AN4 VSS_NCTF_6 A43 C
<40> GPS_OFF# SDATAOUT1/GPIO48 VSS_NCTF_7 A44
+3V_PCH PCH_GPIO49 AK3 VSS_NCTF_8 B1
SATA5GP/GPIO49 VSS_NCTF_9 B2
RH159 1 @ 2 10K_0402_5% WWAN_ON PCH_GPIO57 U12 VSS_NCTF_10 B44
GPIO57 VSS_NCTF_11 B45
RH160 1 2 10K_0402_5% DOCK_DETECT# CMOS_ON# C16 VSS_NCTF_12 BA1
<36> CMOS_ON# TACH4/GPIO68 VSS_NCTF_13 BC1
RH163 1 2 10K_0402_5% PCH_GPIO57 RH164 1 2 0_0402_5% F4_LED#_R D13 VSS_NCTF_14 BD1
<45> F4_LED# TACH5/GPIO69 VSS_NCTF_15 BD2
PCH_GPIO70 G13 VSS_NCTF_16 BD44
Reseve for SKU ID TACH6/GPIO70 VSS_NCTF_17 BD45
+3VALW BT_DET# H15 VSS_NCTF_18 BE2
<39> BT_DET# TACH7/GPIO71 VSS_NCTF_19 BE3
RH177 1 2 10K_0402_5% PCH_MSATA_DET VSS_NCTF_20 D1
BE41 VSS_NCTF_21 E1
BE5 VSS_NCTF_1 NCTF VSS_NCTF_22 E45
C45 VSS_NCTF_2 VSS_NCTF_23 A4
A5 VSS_NCTF_3 VSS_NCTF_24
RH161 1 2 10K_0402_5% WWAN_ON VSS_NCTF_4
RH14 1 2 10K_0402_5% TRACKP_ON LYNX-POINT-DH82LPMS_BGA695 6 OF 11

SA00005U830
RH165 1 @ 2 10K_0402_5% PCH_GPIO37 ODD_DETECT#_R RH30 1 2 0_0402_5% ODD_DETECT#
B B
PCH_MSATA_DET
1
D
<40> PCH_MSATA_DET# 2 QH5
G 2N7002KW_SOT323-3
S
3
+3VS
CONFIG GPIO16, 49 RH167 1 2 10K_0402_5% PCH_GPIO16

RH169 1 2 10K_0402_5% PCH_GPIO49
* USB X4,PCIEX8,SATAX6 11
USB X6,PCIEX8,SATAX4 01 No use Flexible I/O pin, delete RH172, RH174
SKU ID
Function PCH_GPIO38 PCH_GPIO67 PCH_GPIO70 +3VS
* Optimus RH166 1 UMA@ 2 10K_0402_5% PCH_GPIO38

0 0
RH168 1 UMA@ 2 10K_0402_5% PCH_GPIO67
PCH_GPIO67 <16>
Reserve 0 1 RH170 1 NM15@ 2 10K_0402_5% PCH_GPIO70
A A
DIS 1 0
RH171 1 DIS@ 2 10K_0402_5% PCH_GPIO38
Dr-Bios.com
* UMA 1 1 RH173 1 DIS@ 2 10K_0402_5% PCH_GPIO67
RH175 1 NM14@ 2 10K_0402_5% PCH_GPIO70

* 14" 0 Title
Security Classification LC Future Center Secret Data
* 15" 1 Issued Date 2012/12/05 Deciphered Date 2014/12/05 PCH_GPIO/CPU-MISC
Rev
Custom 1.0
!##$%&'()*"*
5 4 3 2 1
5 4 3 2 1
+1.5VS
RH178 LH1
+1.5VS_VCCADAC CH27 CH28 CH29 1 2 1 2
1 1 1 0_0603_5% BLM18PG181SN1D_2P
.01U_0402_16V7-K
0.1U_0402_10V7-K
10U_0603_6.3V6-M
D D
UH1G LPT_PCH_M_EDS 2 2 2
+1.05VS P45
REV = 5 0.07 A VCCADAC1_5
CH30 CH31 CH32 CH33 +1.05VS AA24 P43
AA26 VCC[1] CRT DAC VSSADAC +3VS
VCC[2] 1.312 A
10U_0603_6.3V6-M
1U_0402_6.3V6-K
1U_0402_6.3V6-K
1U_0402_6.3V6-K
AD20 M31 +3VS
1 1 1 1
AD22 VCC[3] 0.0133 A VCCADACBG3_3 +1.05VS_+1.5VS_RUN
AD24 VCC[4]
AD26 VCC[5] BB44 +1.05VS_+1.5VS_RUN
2 2 2 2 AD28 VCC[6] 0.183 A VCCVRM[1]
1
AE18 VCC[7] FDI AN34 +1.05VS
AE20 VCC[8] VCCIO[1] @ CH34
AE22 VCC[9] AN35 +1.05VS 10U_0603_6.3V6-M
AE24 VCC[10] VCCIO[2] 2
VCC[11] 1
AE26 R30 +3VS
AG18 VCC[12] HVCMOS 0.133 A VCC3_3_R30 R32 +3VS CH35
AG20 VCC[13] VCC3_3_R32 1U_0402_6.3V6-K
Layout note: AG22 VCC[14] Y12 +1.05VM_PCH_DCPSUS1
1 2
AG24 VCC[15] DCPSUS1 CH36
Fanout : 5mil Y26 VCC[16] AJ30 0.1U_0402_10V7-K
VCC[17] VCCSUS3_3_AJ30 2
Core
AJ32 +3V_PCH
Breakout : 10mil 0.261 A VCCSUS3_3_AJ32 +3V_PCH
+1.05VM_PCH_VCCASW AJ26
+PCH_VCCDSW U14 USB3 DCPSUS3_AJ26 AJ28 +1.05VM_PCH_DCPSUS3
CH38 CH39 CH40 +1.05VM_PCH_VCCASW AA18 DCPSUSBYP DCPSUS3_AJ28 AK20 +1.05VS +1.05VS_+1.5VS_RUN
VCCASW[1] VCCIO[3] +1.05VS
U18 AK26
VCCASW[2] 0.67 A VCCVRM[2]
22U_0805_6.3V6-M
1U_0402_6.3V6-K
1U_0402_6.3V6-K
1 1 1 U20 AK28 +1.05VS_+1.5VS_RUN

U22 VCCASW[3] VCCVRM[3] +1.05VS_+1.5VS_RUN
VCCASW[4] 1
C U24 BE22 +1.05VS_+1.5VS_RUN C
V18 VCCASW[5] VCCVRM[4] @ CH37
PCIe/DMI 1
2 2 2 V20 VCCASW[6] AK18 +1.05VS 10U_0603_6.3V6-M
VCCASW[7] VCCIO[4] +1.05VS 2
V22 +1.05VS_+1.5VS_RUN @ CH41
V24 VCCASW[8] AN11 +1.05VS_+1.5VS_RUN 10U_0603_6.3V6-M
Y18 VCCASW[9] VCCVRM[5] 2
VCCASW[10] SATA 1
Y20 AK22
Y22 VCCASW[11] VCCIO[5] @ CH42
VCCASW[12] AM18 10U_0603_6.3V6-M
VCCIO[6] AM20 2
3.269 A VCCIO[7] AM22
VCCMPHY VCCIO[8] AP22
+PCH_VCCDSW VCCIO[9] AR22 +1.05VS
VCCIO[10] AT22 +1.05VS CH43 CH44 CH45 CH46 CH47
VCCIO[11]
1U_0402_6.3V6-K
1U_0402_6.3V6-K
1U_0402_6.3V6-K
1U_0402_6.3V6-K
10U_0603_6.3V6-M
1 1 1 1 1
1
SA00005U830
RH179
5.11_0402_1% 2 2 2 2 2
2
1 PCH Power Rail Table (EDS Rev1.0)

CH48
1U_0402_6.3V6-K
2
Voltage Rail Voltage S0 Iccmax Current (A)
VCC 1.05V 1.312 A
B B
VCCIO 1.05V 3.629 A
VCCADAC1_5 1.5V 0.07 A
VCCADAC3_3 3.3V 0.0133 A
VCCCLK 1.05V 0.306 A
VCCCLK3_3 3.3V 0.055 A
+1.05VS_PCH_VCC VCCVRM 1.5V 0.183 A

+1.05VS_PCH_VCCIO
+1.05VM_PCH_VCCASW VCC3_3 3.3V 0.133 A
RH180
+1.05VM_PCH_DCPSUS1 1 @ 2
1 VCCASW 1.05V 0.67 A
0_0402_5%
@ CH49
1U_0402_6.3V6-K VCCSUSHDA 3.3V 0.01 A
+1.05VM_PCH_VCCASW +1.05VS_+1.5VS_RUN 2
VCCSPI 3.3V 0.022 A

+1.05VS +1.05VM_PCH_VCCASW +1.5VS +1.05VS_+1.5VS_RUN +1.05VM_PCH_VCCASW
RH183
RH181 1 @ 2 0_0603_5% 0.67 A RH182 1 2 0_0603_5% 0.183 A +1.05VM_PCH_DCPSUS3 1 @ 2 VCCSUS3_3 3.3V 0.261 A
1 1
A 0_0402_5% A
+1.05VM +1.05VS @ CH50 @ CH51 VCCDSW3_3 3.3V 0.015 A
0.1U_0402_10V7-K 10U_0603_6.3V6-M
Dr-Bios.com
RH184 1 2 0_0603_5% RH185 1 @ 2 0_0603_5% 2 2
V_PROC_IO 1.05V 0.004 A
Issued Date 2012/12/05 Deciphered Date 2014/12/05 PCH_POWER-1

Rev
Custom 1.0
!##$%&'()*"*
5 4 3 2 1
5 4 3 2 1
+3V_PCH RH186 1 2 0_0402_5% +3VALW

LPT_PCH_M_EDS 1 2 0_0402_5%
UH1H +3V_PCH RH187 @ +3V_PCH
1 1
+3V_PCH
D REV = 5 D
CH52 CH53
CH54 +3V_PCH R24 R20 0.1U_0402_10V7-K 0.1U_0402_10V7-K
R26 VCCSUS3_3_R24 VCCSUS3_3_R20 R22 2 2
VCCSUS3_3_R26 0.261 A VCCSUS3_3_R22
0.1U_0402_10V7-K
1 R28
+1.05VS U26 VCCSUS3_3_R28 GPIO/LPC
VCCSUS3_3_U26 A16 +3VALW_VCCDSW3_3
CH56 +1.05VS M24 0.015 A VCCDSW3_3
2 VSS_USB AA14 CH55 1 2 0.1U_0402_10V7-K
0.1U_0402_10V7-K +3VS U35 DCPSST
1 VCCUSBPLL AE14 +3VS
USB
VCC3_3_AE14 +3VS
CH57 +3VS L24 AF12 1
VCC3_3_L24 VCC3_3_AF12 AG14
2 VCC3_3_AG14
0.1U_0402_10V7-K
1 U30 CH58
+1.05VS V28 VCCIO[12] 0.1U_0402_10V7-K
V30 VCCIO[13] U36 +1.05VS 2
VCCIO[14] VCCIO[16] +1.05VS
CH59 +1.05VS Y30
2 VCCIO[15] +3V_PCH
1U_0402_6.3V6-K
1 +1.05VS_+1.5VS_RUN +1.05VM_PCH_DCPSUS2 Y35 Azalia
DCPSUS2 A26 +3V_PCH
CH61 AF34 0.01 A VCCSUSHDA
1
VCCVRM[6] +3V_PCH
2
10U_0603_6.3V6-M
1 +PCH_VCC +PCH_VCC AP45 K8 +3V_PCH CH60
VCC[18] VCCSUS3_3_K8 0.1U_0402_10V7-K
1 2
+PCH_VCCCLK Y32 A6 +RTCVCC CH64 CH65 CH66
+PCH_VCCCLK VCCCLK[1] 0.306 A VCCRTC +RTCVCC
CH62
2 RTC
0.1U_0402_10V7-K
0.1U_0402_10V7-K
1U_0402_6.3V6-K
+PCH_VCCCLK3_3 +PCH_VCCCLK3_3 M29 P14 1 1 1 1U_0402_6.3V6-K
VCCCLK3_3[1] DCPRTC[1] P16 CH63 1 2 0.1U_0402_10V7-K 2
L29 0.055 A DCPRTC[2]
VCCCLK3_3[2]
L26 AJ12 +1.05VS_PCH_VPROC 2 2 2
M26 VCCCLK3_3[3] V_PROC_IO[1] AJ14
VCCCLK3_3[4]
CPU
0.004 A V_PROC_IO[2]
C U32 C
VCCCLK3_3[5]
ICC
V32 AD12 +3VM_VCCSPI
VCCCLK3_3[6] SPI 0.022 A VCCSPI
1
+PCH_VCCCLK +PCH_VCCCLK AD34
VCCCLK[2] P18 +PCH_VCCCFUSE CH67 +3VS
AA30 0.306 A VCC[19] P20 1U_0402_6.3V6-K
AA32 VCCCLK[3] VCC[20] 2 +3VM_VCCSPI RH122 1 @ 2 0_0402_5%
VCCCLK[4] L17
AD35 Fuse VCCASW[13] +3VM
VCCCLK[5] R18 +1.05VM_PCH_VCCASW
VCCASW[14] +1.05VM_PCH_VCCASW
AG30 RH126 1 2 0_0402_5%
AG32 VCCCLK[6]
VCCCLK[7] AW40 +1.05VS_+1.5VS_RUN
VCCVRM[7] +1.05VS_+1.5VS_RUN
AD36
VCCCLK[8] AK30 +3VS
AE30 VCC3_3_AK30
Thermal
AE32 VCCCLK[9] AK32
VCCCLK[10] VCC3_3_AK32
1
LYNX-POINT-DH82LPMS_BGA695 8 OF 11 CH68
SA00005U830 0.1U_0402_10V7-K
2
+1.05VM_PCH_DCPSUS2 +PCH_VCCCLK +V_VPROC

B B
+1.05VM +1.05VS
RH189 +1.05VS_PCH_VPROC +1.05VS
RH188 1 @ 2 0_0402_5% +1.05VM_PCH_DCPSUS2 1 2 CH70 CH71 CH72 CH73 CH74 +PCH_VCCCLK RH190
+1.05VS_PCH_VPROC CH75 CH76 CH77 1 2
1U_0402_6.3V6-K
1U_0402_6.3V6-K
1U_0402_6.3V6-K
1U_0402_6.3V6-K
1U_0402_6.3V6-K
0_0805_5% 1 1 1 1 1
0.1U_0402_10V7-K
0.1U_0402_10V7-K
1U_0402_6.3V6-K
+1.05VS 1 1 1 1 0_0805_5%
RH120 1 @ 2 0_0402_5% @ CH69

1U_0402_6.3V6-K 2 2 2 2 2
2 2 2 2
Place near pin Place near pin Place near pin Place near pin
Y32,AA30,AA32AD34 AD35,AD36 AG30,AG32,AE30,AE32
+PCH_VCC +PCH_VCCCLK3_3 +PCH_VCCCFUSE

+1.05VS +3VS RH191 1 @ 2 0_0805_5% +3VS
LH2 RH192
2 1 CH78 CH79 +PCH_VCC 1 2 CH80 CH81 CH82 CH83 CH84 +PCH_VCCCLK3_3 +PCH_VCCCFUSE CH85 RH193 1 2 0_0805_5% +1.05VS
4.7UH_LQM18FN4R7M00D_20%
10U_0603_6.3V6-M
1U_0402_6.3V6-K
1U_0402_6.3V6-K
1U_0402_6.3V6-K
1U_0402_6.3V6-K
1U_0402_6.3V6-K
1U_0402_6.3V6-K
1U_0402_6.3V6-K
1 1 0_0805_5% 1 1 1 1 1 1 20130125 --> Need connect to +1.05VS
2 2 2 2 2 2 2 2
A A
Dr-Bios.com
Place near pin Place near pin Place near Place near pin
M29 L29 pin L26,M26 U32,V32
Issued Date 2012/12/05 Deciphered Date 2014/12/05 PCH_POWER-2

Rev
Custom 1.0
!##$%&'()*"*
5 4 3 2 1
5 4 3 2 1
D D
LPT_PCH_M_EDS LPT_PCH_M_EDS
UH1J UH1K
AL34 K39 AA16 REV = 5 B19

AL38 VSS[1] REV = 5 VSS[48] L2 AA20 VSS[93] VSS[138] B23
AL8 VSS[2] VSS[49] L44 AA22 VSS[94] VSS[139] B27
AM14 VSS[3] VSS[50] M17 AA28 VSS[95] VSS[140] B31
AM24 VSS[4] VSS[51] M22 AA4 VSS[96] VSS[141] B35
AM26 VSS[5] VSS[52] N12 AB12 VSS[97] VSS[142] B39
AM28 VSS[6] VSS[53] N35 AB34 VSS[98] VSS[143] B7
AM30 VSS[7] VSS[54] N39 AB38 VSS[99] VSS[144] BA40
AM32 VSS[8] VSS[55] N6 AB8 VSS[100] VSS[145] BD11
AM16 VSS[9] VSS[56] P22 AC2 VSS[101] VSS[146] BD15
AN36 VSS[10] VSS[57] P24 AC44 VSS[102] VSS[147] BD19
AN40 VSS[11] VSS[58] P26 AD14 VSS[103] VSS[148] AY36
AN42 VSS[12] VSS[59] P28 AD16 VSS[104] VSS[149] AT43
AN8 VSS[13] VSS[60] P30 AD18 VSS[105] VSS[150] BD31
AP13 VSS[14] VSS[61] P32 AD30 VSS[106] VSS[151] BD35
C AP24 VSS[15] VSS[62] R12 AD32 VSS[107] VSS[152] BD39 C
AP31 VSS[16] VSS[63] R14 AD40 VSS[108] VSS[153] BD7
AP43 VSS[17] VSS[64] R16 AD6 VSS[109] VSS[154] D25
AR2 VSS[18] VSS[65] R2 AD8 VSS[110] VSS[155] AV7
AK16 VSS[19] VSS[66] R34 AE16 VSS[111] VSS[156] F15
AT10 VSS[20] VSS[67] R38 AE28 VSS[112] VSS[157] F20
AT15 VSS[21] VSS[68] R44 AF38 VSS[113] VSS[158] F29
AT17 VSS[22] VSS[69] R8 AF8 VSS[114] VSS[159] F33
AT20 VSS[23] VSS[70] T43 AG16 VSS[115] VSS[160] BC16
AT26 VSS[24] VSS[71] U10 AG2 VSS[116] VSS[161] D4
AT29 VSS[25] VSS[72] U16 AG26 VSS[117] VSS[162] G2
D42 VSS[28] VSS[75] U38 AJ16 VSS[120] VSS[165] G8
AV13 VSS[29] VSS[76] U42 AJ18 VSS[121] VSS[166] H10
AV22 VSS[30] VSS[77] U6 AJ20 VSS[122] VSS[167] H13
AV24 VSS[31] VSS[78] V14 AJ22 VSS[123] VSS[168] H17
BB25 VSS[34] VSS[81] V43 AJ38 VSS[126] VSS[171] H26
AV40 VSS[35] VSS[82] W2 AJ6 VSS[127] VSS[172] H31
AV6 VSS[36] VSS[83] W44 AJ8 VSS[128] VSS[173] H36
AW2 VSS[37] VSS[84] Y14 AK14 VSS[129 VSS[174] H40
F43 VSS[38] VSS[85] Y16 AK24 VSS[130] VSS[175] H7
AY10 VSS[39] VSS[86] Y24 AK43 VSS[131] VSS[176] K10
AY15 VSS[40] VSS[87] Y28 AK45 VSS[132] VSS[177] K15
AY20 VSS[41] VSS[88] Y34 AL12 VSS[133] VSS[178] K20
AY26 VSS[42] VSS[89] Y36 AL2 VSS[134] VSS[179] K29
AY29 VSS[43] VSS[90] Y40 BC22 VSS[135] VSS[180] K33
AY7 VSS[44] VSS[91] Y8 BB42 VSS[136] VSS[181] BC28
B11 VSS[45] VSS[92] VSS[137] VSS[182]
B15 VSS[46]
B VSS[47] B
SA00005U830
SA00005U830
A A
5
Dr-Bios.com
4
3 2
Title
Date:
PCH_GND
Custom
!"#$%&'()*+*
1
Sheet 22 of 57
Rev
1.0
5 4 3 2 1
VGA_THERMTRIP#
+3VS_VGA
+3VS_VGA VGA_THERMTRIP# <19>
UV1A
1
Part 1 of 6
6
PCIE_CTX_C_GRX_N[0..7] PCIE_CTX_C_GRX_P0 AG6 C6 FB_CLAMP_MON DPRSLPVR_VGA RV3 1 DIS@ 2 10K_0402_5% DIS@ RV10
<5> PCIE_CTX_C_GRX_N[0..7] PEX_RX0 GPIO0
PCIE_CTX_C_GRX_N0 AG7 B2 10K_0402_5%
PCIE_CTX_C_GRX_P[0..7] PCIE_CTX_C_GRX_P1 AF7 PEX_RX0_N GPIO1 D6 OVERT# RV6 1 DIS@ 2 100K_0402_5% QV1A DIS@
<5> PCIE_CTX_C_GRX_P[0..7]
2
PCIE_CTX_C_GRX_N1 AE7 PEX_RX1 GPIO2 C7 2 2N7002KDWH_SOT363-6
PCIE_CRX_GTX_N[0..7] PCIE_CTX_C_GRX_P2 AE9 PEX_RX1_N GPIO3 F9 THERM#_VGA RV8 1 DIS@ 2 100K_0402_5%
<5> PCIE_CRX_GTX_N[0..7] PEX_RX2 GPIO4
3
PCIE_CTX_C_GRX_N2 AF9 A3
1
PCIE_CRX_GTX_P[0..7] PCIE_CTX_C_GRX_P3 AG9 PEX_RX2_N GPIO5 A4 FB_CLAMP_TGL_REQ# VGA_AC_DET_R RV9 1 DIS@ 2 100K_0402_5%
D <5> PCIE_CRX_GTX_P[0..7] PEX_RX3 GPIO6 D
PCIE_CTX_C_GRX_N3 AG10 B6 QV1B DIS@
PCIE_CTX_C_GRX_P4 AF10 PEX_RX3_N GPIO7 A6 OVERT# OVERT# 5 2N7002KDWH_SOT363-6
PCIE_CTX_C_GRX_N4 AE10 PEX_RX4 GPIO8 F8 THERM#_VGA
PCIE_CTX_C_GRX_P5 AE12 PEX_RX4_N GPIO9 C5
4
PCIE_CTX_C_GRX_N5 AF12 PEX_RX5 GPIO10 E7 NVVDD_PWM_VID DIS@
PEX_RX5_N GPIO11 NVVDD_PWM_VID <63>
PCIE_CTX_C_GRX_P6 AG12 D7 VGA_AC_DET_R 2 1 VGA_AC_DET
PEX_RX6 GPIO12 VGA_AC_DET <48>
1
PCIE_CTX_C_GRX_N6 AG13 B4 DPRSLPVR_VGA D
GPIO
PEX_RX6_N GPIO13 DPRSLPVR_VGA <63>
PCIE_CTX_C_GRX_P7 AF13 B3 DV1 RB751V-40_SOD323-2 PLTRST_VGA# 2 QV2 DIS@
PCIE_CTX_C_GRX_N7 AE13 PEX_RX7 GPIO14 C3 SCS00006S00 G 2N7002KW_SOT323-3
AE15 PEX_RX7_N GPIO15 D5 For GC6 (FB_CLAMP_TGL_REQ#, GC6_EVEVT#), just for N14P S
3
AF15 NC1 GPIO16 D4
AG15 NC2 GPIO17 C2
AG16 NC3 GPIO18 F7 +3VS_VGA
NC4 GPIO19 1 1
AF16 E6 RV93 RV94
AE16 NC5 GPIO20 C4 1 @ 2 1 @ 2 DGPU_PWR_EN @ CV117 @ CV118
NC6 GPIO21 DGPU_PWR_EN <14,54>
AE18 0.1U_0402_10V7K 0.1U_0402_10V7K
NC7 0_0402_5% 2 2
AF18 AB6 0_0402_5%
AG18 NC8 NC33 N14PGV2@
AG19 NC9 RV95 1 2 10K_0402_5% PLTRST_VGA#
AF19 NC10
NC11 1
2
AE19
AE21 NC12 AG3 CV116 N14PGV2@
AF21 NC13 DACA_RED AF4 N14PGV2@ RV12 0.1U_0402_10V7K
AG21 NC14 DACA_GREEN AF3 100K_0402_5% 2 27MHz X'TAL
NC15 DACA_BLUE
2
G
AG22
1
NC16 RV30 1 DIS@ 2 10M_0402_5%
FB_CLAMP_TGL_REQ# 3 1
To EC
GC6_EVENT# <19,48>
PCIE_CRX_GTX_P0 CV1 DIS@ 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_P0 AC9 AE3
D
PEX_TX0 DACA_HSYNC GPIO 6 of GPU connect to EC GPIO
DACs
PCIE_CRX_GTX_N0 CV2 DIS@ 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_N0 AB9 AE4 QV3 N14PGV2@ YV1 DIS@
PCIE_CRX_GTX_P1 CV3 DIS@ 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_P1 AB10 PEX_TX0_N DACA_VSYNC 2N7002KW_SOT323-3 Crystal
PCIE_CRX_GTX_N1 CV4 DIS@ 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_N1 AC10 PEX_TX1 4 3XTAL_OUT
PEX_TX1_N GND OUT
PCI EXPRESS
PCIE_CRX_GTX_P2 CV5 DIS@ 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_P2 AD11
C PCIE_CRX_GTX_N2 CV6 DIS@ 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_N2 AC11 PEX_TX2 W5 RV13 1 @ 2 10K_0402_5% XTALIN 1 2 C
PCIE_CRX_GTX_P3 CV7 DIS@ 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_P3 AC12 PEX_TX2_N DACA_VDD AE2 IN GND
PCIE_CRX_GTX_N3 CV8 DIS@ 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_N3 AB12 PEX_TX3 DACA_VREF AF2
PEX_TX3_N DACA_RSET 2 2
PCIE_CRX_GTX_P4 CV9 DIS@ 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_P4 AB13 27MHZ_10PF_7V27000050
PCIE_CRX_GTX_N4 CV10 DIS@ 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_N4 AC13 PEX_TX4 CV17 DIS@ SJ10000G700 CV18 DIS@
PCIE_CRX_GTX_P5 CV11 DIS@ 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_P5 AD14 PEX_TX4_N 10P_0402_50V8-J 10P_0402_50V8-J
PCIE_CRX_GTX_N5 CV12 DIS@ 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_N5 AC14 PEX_TX5 +3VS_VGA 1 1
PCIE_CRX_GTX_P6 CV13 DIS@ 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_P6 AC15 PEX_TX5_N
PCIE_CRX_GTX_N6 CV14 DIS@ 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_N6 AB15 PEX_TX6
PCIE_CRX_GTX_P7 CV15 DIS@ 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_P7 AB16 PEX_TX6_N B7 I2CA_SCL RV14 1 DIS@ 2 2.2K_0402_5%
PCIE_CRX_GTX_N7 CV16 DIS@ 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_N7 AC16 PEX_TX7 I2CA_SCL A7 I2CA_SDA RV15 1 DIS@ 2 2.2K_0402_5%
AD17 PEX_TX7_N I2CA_SDA LV1 DIS@
AC17 NC17 C9 I2CB_SCL RV16 1 DIS@ 2 2.2K_0402_5% CV19 CV20 1 2
NC18 I2CB_SCL +1.05VS_VGA
AC18 C8 I2CB_SDA RV17 1 DIS@ 2 2.2K_0402_5% BLM18PG181SN1D_2P
NC19 I2CB_SDA
I2C
0.1U_0402_10V7K
22U_0805_6.3V6M
AB18 30 ohms @100MHz (ESR=0.05)
AB19 NC20 A9 I2CC_SCL RV18 1 DIS@ 2 2.2K_0402_5%
NC21 I2CC_SCL 1 1
AC19 B9 I2CC_SDA RV19 1 DIS@ 2 2.2K_0402_5% DIS@ DIS@
AD20 NC22 I2CC_SDA
AC20 NC23 D9 I2CS_SCL RV21 1 DIS@ 2 2.2K_0402_5%
AC21 NC24 I2CS_SCL D8 I2CS_SDA RV22 1 DIS@ 2 2.2K_0402_5% 2 2
AB21 NC25 I2CS_SDA
AD23 NC26
AE23 NC27 Under GPU Near GPU
AF24 NC28
AE24 NC29 L6 +PLLVDD
NC30 52mACORE_PLLVDD
AG24 M6
AG25 NC31 SP_PLLVDD LV2 DIS@
NC32 71mA N6 +SP_PLLVDD CV23 CV24 CV25 CV26
150mA 1 2
VID_PLLVDD +1.05VS_VGA
41mA BLM18PG330SN1_2P
22U_0805_6.3V6M
4.7U_0402_6.3V6M
0.1U_0402_10V7K
0.1U_0402_10V7K
RV23 180ohms (ESR=0.2) Bead
CLK_PCIE_VGA AE8 +PLLVDD 1 @ 2 +SP_PLLVDD 1 1 1 1
<16> CLK_PCIE_VGA PEX_REFCLK
CLK_PCIE_VGA# AD8 DIS@ DIS@ DIS@ DIS@
B <16> CLK_PCIE_VGA# PEX_REFCLK_N B
CLK_REQ_GPU# AC6 0_0402_5%
PEX_CLKREQ_N
Differential signal 2 2 2 2
RV25 1 @ 2 200_0402_1% PEX_TSTCLK_OUT AF22
CLK
PEX_TSTCLK_OUT# AE22 PEX_TSTCLK_OUT C11 XTALIN

PEX_TSTCLK_OUT_N XTAL_IN B10 XTAL_OUT
XTAL_OUT
PLTRST_VGA# AC7 A10 XTALSSIN RV26 1 DIS@ 2 10K_0402_5%
Under GPU(below 150mils)
<14> PLTRST_VGA# PEX_RST_N XTAL_SSIN
PEX_TERMP AF25 C10 XTALOUT RV29 1 DIS@ 2 10K_0402_5%
PEX_TERMP XTAL_OUTBUFF
1
DIS@ RV97 DIS@ RV28 N14M-LP-S-A2_FCBGA595

Internal Thermal Sensor For GC6 (FB_CLAMP_MON, FB_CLAMP)
10K_0402_5% 2.49K_0402_1% N14PGV2@
SA00005NC10 FB_CLAMP_MON
2
+3VS
2
To PCH
1
N14PGV2@ RV27
+3VS_VGA 0_0402_5%
N14PGV2@ RV31
1
10K_0402_5% N14PGV2@
For GPU CLKREQU# RV32 1 2 10K_0402_5%
2
2
QV4A DIS@
1
2N7002KDWH_SOT363-6
I2CS_SCL 1 6 N14PGV2@
+3VS_VGA EC_SMB_CK3 <17,32,48>
RV2 QV5 N14PGV2@
1 2 CV115 2 AP2301GN-HF_SOT23-3
RV33 RV96 RV20 1 @ 2 0_0402_5% SB00000YL00
0.1U_0402_10V7K
DGPU_PWR_EN 1 @ 2 CV21 1 DIS@ 2 1K_0402_5% 1 From EC
3
1
D
FB_CLAMP <27,48>
0.1U_0402_16V4Z
10K_0402_5% 1 0_0402_5% DGPU_PWR_EN 2 N14PGV2@

1
1
QV4B DIS@ G
@ 2N7002KDWH_SOT363-6 S QV6 N14PGV2@ 2
3
A DIS@ RV34 I2CS_SDA 4 3 2N7002KW_SOT323-3 DIS@ RV35 A
2 EC_SMB_DA3 <17,32,48>
10K_0402_5% 10K_0402_5%
2
G
!"#$%UV1
Load BOM! PU +3VS AT EC SIDE, +3VS AND 4.7K
Dr-Bios.com
2
2
QV7 DIS@ RV24 1 @ 2 0_0402_5%
CV22 1 3 2N7002KW_SOT323-3 CLK_REQ_GPU# NV recommend add RV2 1KOhm to avoid giltich issue
<16> CLK_REQ_GPU#_R
D
1
0.1U_0402_16V4Z
To PCH 1
RV37 1 @ 2 0_0402_5%
@ @ RV36 UV1
10K_0402_5%
2 Issued Date 2012/12/05 Deciphered Date 2014/12/05 N14P_PCIe/GPIO/I2C
2
N14M-GL-S-A2_FCBGA595 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
N14MGL@ Size Document Number
Rev
SA00005N900 Custom 1.0
!##$%&'()*"*
5 4 3 2 1
5 4 3 2 1
UV1C
Part 3 of 6 F11
AC3 NC50 AD10
AC4 IFPA_TXC NC51 AD7
Y4 IFPA_TXC_N NC52 B19
Y3 IFPA_TXD0 NC53 V5
AA3 IFPA_TXD0_N NC54 V6
AA2 IFPA_TXD1 NC55 G1
D AB1 IFPA_TXD1_N NC56 G2 D
IFPA_TXD2 NC57
NC
AA1 G3
AA4 IFPA_TXD2_N NC58 G4
AA5 IFPA_TXD3 NC59 G5
IFPA_TXD3_N NC60 G6
NC61 G7
AB5 NC62 V1
AB4 IFPB_TXC NC63 V2
AB3 IFPB_TXC_N NC64 W1
AB2 IFPB_TXD4 NC65 W2
AD3 IFPB_TXD4_N NC66 W3
AD2 IFPB_TXD5 NC67 W4
AE1 IFPB_TXD5_N NC68
AD1 IFPB_TXD6
AD4 IFPB_TXD6_N
AD5 IFPB_TXD7 D11 RV38 1 DIS@ 2 10K_0402_5%
IFPB_TXD7_N BUFRST_N
D10
T2 NC69
T3 IFPC_L0 E9
T1 IFPC_L0_N NC70
R1 IFPC_L1 E10
R2 IFPC_L1_N NC71
GENERAL
IFPC_L2
LVDS/TMDS
R3 F10
N2 IFPC_L2_N NC72
N3 IFPC_L3
IFPC_L3_N D1 STRAP0
STRAP0 STRAP0 <30>
D2 STRAP1
STRAP1 STRAP1 <30>
V3 E4 STRAP2
IFPD_L0 STRAP2 STRAP2 <30>
V4 E3 STRAP3
IFPD_L0_N STRAP3 STRAP3 <30>
U3 D3 STRAP4
IFPD_L1 STRAP4 STRAP4 <30>
U4 C1
C T4 IFPD_L1_N NC73 C
T5 IFPD_L2 N14PGV2@
R4 IFPD_L2_N F6 RV39 1 2 40.2K_0402_1%
R5 IFPD_L3 MULTI_STRAP_REF0_GND F4
IFPD_L3_N NC74 F5
NC75
N1
M1 NC34
M2 NC35 F12
M3 NC36 THERMDP
K2 NC37 E12
K3 NC38 THERMDN
K1 NC39
J1 NC40
NC41
M4 F2 VCCSENSE_VGA
NC42 VDD_SENSE VCCSENSE_VGA <63>
M5
L3 NC43
L4 NC44 trace width: 16mils
K4 NC45 differential voltage sensing.
NC46
K5 differential signal routing.
J4 NC47 F1 VSSSENSE_VGA
NC48 GND_SENSE VSSSENSE_VGA <63>
J5
N4 NC49
N5 IFPC_AUX_I2CW_SCL TEST
IFPC_AUX_I2CW_SDA_N
P3 AD9 TESTMODE RV40 1 DIS@ 2 10K_0402_5%
B P4 IFPD_AUX_I2CX_SCL TESTMODE AE5 1 B
IFPD_AUX_I2CX_SDA_N JTAG_TCK TV1
AE6 1
JTAG_TDI TV2
AF6 1
JTAG_TDO TV3
J2 AD6 1
IFPE_AUX_I2CY_SCL JTAG_TMS TV4
J3 AG4 RV41 1 DIS@ 2 10K_0402_5%
IFPE_AUX_I2CY_SDA_N JTAG_TRST_N
H3
H4 IFPF_AUX_I2CZ_SCL
IFPF_AUX_I2CZ_SDA_N SERIAL +3VS_VGA
D12 ROM_CS# RV42 1 DIS@ 2 10K_0402_5%
ROM_CS_N B12 ROM_SI
ROM_SI ROM_SI <30>
A12 ROM_SO
ROM_SO ROM_SO <30>
C12 ROM_SCLK
ROM_SCLK ROM_SCLK <30>
N14M-LP-S-A2_FCBGA595
N14PGV2@
SA00005NC10
A A
5
Dr-Bios.com
4
3 2
Title
N14P_SPI ROM/SENSE
Custom
Date:
!##$%&'()*"*
1
Sheet 24 of 57
Rev
1.0
5 4 3 2 1
D +1.5VS_VGA UV1D D
+1.05VS_VGA
3.5A Part 4 of 6 2000mA
CV36 CV27 CV28 CV37 CV29 CV30 CV31 CV38 CV32 CV39 CV33 CV40 CV41 CV34 CV35 CV42 B26 AA10 CV43 CV44 CV45 CV46 CV47 CV48 CV49 CV50 CV51 CV52 CV53 CV54 CV55 CV56
C25 FBVDDQ_01 PEX_IOVDDQ_1 AA12
FBVDDQ_02 PEX_IOVDDQ_2
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
1U_0603_10V6K
1U_0603_10V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
22U_0805_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
E23 AA13
FBVDDQ_03 PEX_IOVDDQ_3
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 E26 AA16 1 1 1 1 1 1 1 1 1 1 1 1 1 1
F14 FBVDDQ_04 PEX_IOVDDQ_4 AA18
F21 FBVDDQ_05 PEX_IOVDDQ_5 AA19
G13 FBVDDQ_06 PEX_IOVDDQ_6 AA20
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 G14 FBVDDQ_07 PEX_IOVDDQ_7 AA21 2 2 2 2 2 2 2 2 2 2 2 2 2 2
G15 FBVDDQ_08 PEX_IOVDDQ_8 AB22
G16 FBVDDQ_09 PEX_IOVDDQ_9 AC23
G18 FBVDDQ_10 PEX_IOVDDQ_10 AD24
G19 FBVDDQ_11 PEX_IOVDDQ_11 AE25
Under GPU(below 150mils) Near GPU G20 FBVDDQ_12 PEX_IOVDDQ_12 AF26 Under GPU(below 150mils) Near GPU
G21 FBVDDQ_13 PEX_IOVDDQ_13 AF27
rise 1.5v system source voltage to 1.55-1.57V H24 FBVDDQ_14
FBVDDQ_15
PEX_IOVDDQ_14
Cost Down Plan H26

J21 FBVDDQ_16 AA22
K21 FBVDDQ_17 PEX_IOVDD_1 AB23
L22 FBVDDQ_18 PEX_IOVDD_2 AC24
L24 FBVDDQ_19 PEX_IOVDD_3 AD25
L26 FBVDDQ_20 PEX_IOVDD_4 AE26
M21 FBVDDQ_21 PEX_IOVDD_5 AE27
N21 FBVDDQ_22 PEX_IOVDD_6
R21 FBVDDQ_23
T21 FBVDDQ_24
V21 FBVDDQ_25 +3VS_VGA
W21 FBVDDQ_26
FBVDDQ_27 G10 +VDD33 CV57 CV58 CV59 CV60 CV61 CV62 RV43 1 2 0_0603_5%
VDD33_1 G12
VDD33_2
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
1U_0402_6.3V6K
4.7U_0603_6.3V6K
C G8 C
VDD33_3
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
G9 1 1 1 1 1 1
VDD33_4
+1.5VS_VGA
RV44 2 @ 1 10K_0402_5% +IFPAB_PLLVDD V7
W7 IFPAB_PLLVDD_1 2 2 2 2 2 2
AA6 IFPAB_PLLVDD_2
RV45 2 @ 1 10K_0402_5% +IFPAB_IOVDD W6 IFPAB_RSET D22 RV46 1 DIS@ 2 40.2_0402_1%
Y6 IFPA_IOVDD FB_CAL_PD_VDDQ
IFPB_IOVDD
C24 RV47 1 DIS@ 2 42.2_0402_1%
FB_CAL_PU_GND
Under GPU Near GPU
RV48 2 @ 1 10K_0402_5% +IFPC_PLLVDD M7 B25 RV49 1 DIS@ 2 51.1_0402_1%
N7 IFPC_PLLVDD_1 FB_CAL_TERM_GND
T6 IFPC_PLLVDD_2
RV50 2 @ 1 10K_0402_5% +IFPC_IOVDD P6 IFPC_RSET Place near balls
IFPC_IOVDD
RV51 2 @ 1 10K_0402_5% +IFPD_PLLVDD T7

R7 IFPD_PLLVDD_2
U6 IFPD_PLLVDD_1 +3VS_VGA
RV52 2 @ 1 10K_0402_5% +IFPD_IOVDD R6 IFPD_RSET AA8
IFPD_IOVDD PEX_PLL_HVDD_1 AA9 +PEX_PLLHVDD RV53 1 2 0_0402_5%
PEX_PLL_HVDD_2
CV63
0.1U_0402_10V7K
CV64
4.7U_0603_6.3V6K
CV65
4.7U_0603_6.3V6K
AB8
PEX_SVDD_3V3
1 1 1
J7 +1.05VS_VGA
NC76
DIS@
DIS@
DIS@
K7
K6 NC77 AA14 120mA N14MGL@ 2 2 2
B H6 NC78 PEX_PLLVDD_1 AA15 +PEX_PLLVDD LV3 1 2 BLM18PG121SN1D_0603 B
J6 NC79 PEX_PLLVDD_2
NC80
CV66
0.1U_0402_10V7K
CV67
1U_0603_10V6K
CV68
4.7U_0805_10V4Z
120ohms @100MHz (ESR=0.18)
1 1 1
N14PGV2@
DIS@
DIS@
DIS@
RV54 1 2 0_0603_5%
N14M-LP-S-A2_FCBGA595 2 2 2 Near GPU(below 150mils)
N14PGV2@
SA00005NC10
Under GPU Near GPU
CALIBRATION PIN DDR3

FB_CAL_x_PD_VDDQ 40.2Ohm
A A
FB_CAL_x_PU_GND 42.2Ohm
Dr-Bios.com
FB_CAL_xTERM_GND 51.1Ohm
Issued Date 2012/12/05 Deciphered Date 2014/12/05 N14P_POWER

Rev
Custom 1.0
!##$%&'()*"*
5 4 3 2 1
5 4 3 2 1
UV1E
A2 Part 5 of 6 K11 +VGA_CORE +VGA_CORE

A26 GND_001 GND_057 K13 UV1F
AB11 GND_002 GND_058 K15
AB14 GND_003 GND_059 K17 Part 6 of 6
AB17 GND_004 GND_060 L10
AB20 GND_005 GND_061 L12 K10 V18
AB24 GND_006 GND_062 L14 K12 VDD_001 VDD_041 V16
D AC2 GND_007 GND_063 L16 K14 VDD_002 VDD_040 V14 D
GND_008 GND_064 VDD_003 VDD_039 1
AC22 L18 K16 V12
AC26 GND_009 GND_065 L2 K18 VDD_004 VDD_038 V10 CV69 DIS@
AC5 GND_010 GND_066 L23 L11 VDD_005 VDD_037 U17 47U_0805_4V6
AC8 GND_011 GND_067 L25 L13 VDD_006 VDD_036 U15 2
AD12 GND_012 GND_068 L5 L15 VDD_007 VDD_035 U13
AD13 GND_013 GND_069 M11 L17 VDD_008 VDD_034 U11
Place near balls
AD15 GND_014 GND_070 M13 M10 VDD_009 VDD_033 T18
AD19 GND_017 GND_073 N10 M16 VDD_012 VDD_030 T12
AD21 GND_018 GND_074 N12 M18 VDD_013 VDD_029 T10
AD22 GND_019 GND_075 N14 N11 VDD_014 VDD_028 R17
AE11 GND_020 GND_076 N16 N13 VDD_015 VDD_027 R15
AE14 GND_021 GND_077 N18 N15 VDD_016 VDD_026 R13
AE17 GND_022 GND_078 P11 N17 VDD_017 VDD_025 R11
AE20 GND_023 GND_079 P13 P10 VDD_018 VDD_024 P18
AF1 GND_024 GND_080 P15 P12 VDD_019 VDD_023 P16
AF11 GND_025 GND_081 P17 VDD_020 VDD_022 P14
AF14 GND_026 GND_082 P2 VDD_021
AF17 GND_027 GND_083 P23
AF20 GND_028 GND_084 P26
AF23 GND_029 GND_085 P5
AF5 GND_030 GND_086 R10
AF8 GND_031 GND_087 R12
AG2 GND_032 GND_088 R14
AG26 GND_033 GND_089 R16
B1 GND_034 GND_090 R18
B11 GND_035 GND_091 T11 N14M-LP-S-A2_FCBGA595
B14 GND_036 GND_092 T13
B17 GND_037 GND_093 T15 N14PGV2@
B20 GND_038 GND_094 T17 SA00005NC10
C B23 GND_039 GND_095 U10 C
B27 GND_040 GND_096 U12
B5 GND_041 GND_097 U14
B8 GND_042 GND_098 U16
E11 GND_043 GND_099 U18
E14 GND_044 GND_100 U2
E17 GND_045 GND_101 U23
E2 GND_046 GND_102 U26
E20 GND_047 GND_103 U5
E22 GND_048 GND_104 V11
E25 GND_049 GND_105 V13
E5 GND_050 GND_106 V15
E8 GND_051 GND_107 V17
H2 GND_052 GND_108 Y2
H23 GND_053 GND_109 Y23
H25 GND_054 GND_110 Y26
H5 GND_055 GND_111 Y5
GND_056 GND_112
AA7
GND_113 AB7
GND_114 VDD33 (+3VS_VGA)
tIFPx_IOVDD
IFPx_IOVDD
N14PGV2@
SA00005NC10
B
tNVVDD B
NVVDD (+VGA_CORE)
tFBVDDQ
FBVDDQ (+1.5VS_VGA)
tPEX_VDD
PEX_VDD (+1.05VS_VGA)
tIFPy_IOVDD
IFPy_IOVDD
NV Recommended Power On Sequencing Order

A
X=A and B A
Y=C,D,E and F
5
Dr-Bios.com
4
3 2
Date:
Title
N14P_VDD/GND
Custom
!"#$%&'()*+*
1
Sheet 26 of 57
Rev
1.0
5 4 3 2 1
UV1B
Part 2 of 6
FBA_D[0..63]
<28,29> FBA_D[0..63]
FBA_D0 E18 C27 FBA_CS0#_L
<28,29> FBA_DQM[7..0]
FBA_DQM[7..0] FBA_D1 F18 FBA_D00
FBA_D01
FBA_CMD0
FBA_CMD1
C26
FBA_CS0#_L <28> Mode D - Mirror Mode Mapping
FBA_D2 E16 E24 FBA_ODT_L
FBA_DQS[7..0] FBA_D02 FBA_CMD2 FBA_ODT_L <28>
FBA_D3 F17 F24 FBA_CKE_L DATA Bus
<28,29> FBA_DQS[7..0] FBA_D03 FBA_CMD3 FBA_CKE_L <28>
FBA_D4 D20 D27 FBA_MA14
FBA_DQS#[7..0] FBA_D5 D21 FBA_D04 FBA_CMD4 D26 FBA_RST#
<28,29> FBA_DQS#[7..0] FBA_D05 FBA_CMD5 FBA_RST# <28,29> Address 0..31 32..63
FBA_D6 F20 F25 FBA_MA9
D FBA_D7 E21 FBA_D06 FBA_CMD6 F26 FBA_MA7 D
FBA_D07 FBA_CMD7 FBx_CMD0 CS0#_L
FBA_D8 E15 F23 FBA_MA2
FBA_MA[15..0] FBA_D9 D15 FBA_D08 FBA_CMD8 G22 FBA_MA0
FBA_MA[15..0] <28,29> FBA_D09 FBA_CMD9 FBx_CMD1
FBA_D10 F15 G23 FBA_MA4
FBA_BA[2..0] FBA_D11 F13 FBA_D10 FBA_CMD10 G24 FBA_MA1
FBA_BA[2..0] <28,29> FBA_D11 FBA_CMD11 FBx_CMD2 ODT_L
FBA_D12 C13 F27 FBA_BA0
FBA_D13 B13 FBA_D12 FBA_CMD12 G25 FBA_WE#
FBA_D13 FBA_CMD13 FBA_WE# <28,29> FBx_CMD3 CKE_L
FBA_D14 E13 G27 FBA_MA15
FBA_D15 D13 FBA_D14 FBA_CMD14 G26 FBA_CAS#
FBA_D15 FBA_CMD15 FBA_CAS# <28,29> FBx_CMD4 A14 A14
FBA_D16 B15 M24 FBA_CS0#_H
FBA_D16 FBA_CMD16 FBA_CS0#_H <29>
FBA_D17 C16 M23 FBx_CMD5 RST RST
FBA_D18 A13 FBA_D17 FBA_CMD17 K24 FBA_ODT_H
FBA_D18 FBA_CMD18 FBA_ODT_H <29>
FBA_D19 A15 K23 FBA_CKE_H FBx_CMD6 A9 A9
FBA_D19 FBA_CMD19 FBA_CKE_H <29>
FBA_D20 B18 M27 FBA_MA13
FBA_D21 A18 FBA_D20 FBA_CMD20 M26 FBA_MA8
FBA_D21 FBA_CMD21 FBx_CMD7 A7 A7
FBA_D22 A19 M25 FBA_MA6
FBA_D23 C19 FBA_D22 FBA_CMD22 K26 FBA_MA11
FBA_D24 B24 K22 FBA_MA5
FBA_D25 C23 FBA_D24 FBA_CMD24 J23 FBA_MA3
FBA_D26 A25 J25 FBA_BA2
FBA_D27 A24 FBA_D26 FBA_CMD26 J24 FBA_BA1
FBA_D28 A21 K27 FBA_MA12
FBA_D29 B21 FBA_D28 FBA_CMD28 K25 FBA_MA10
FBA_D30 C20 J27 FBA_RAS#
FBA_D30 FBA_CMD30 FBA_RAS# <28,29>
FBA_D31 C21 J26 FBx_CMD12 BA0 BA0
FBA_D32 R22 FBA_D31 FBA_CMD31
FBA_D33 R24 FBA_D32 D19 FBA_DQM0 FBx_CMD13 WE# WE#
INTERFACE A
FBA_D34 T22 FBA_D33 FBA_DQM0 D14 FBA_DQM1
FBA_D35 R23 FBA_D34 FBA_DQM1 C17 FBA_DQM2
FBA_D35 FBA_DQM2 FBx_CMD14 A15 A15
FBA_D36 N25 C22 FBA_DQM3
FBA_D37 N26 FBA_D36 FBA_DQM3 P24 FBA_DQM4 FBx_CMD15 CAS# CAS#
MEMORY
FBA_D38 N23 FBA_D37 FBA_DQM4 W24 FBA_DQM5
C FBA_D39 N24 FBA_D38 FBA_DQM5 AA25 FBA_DQM6 C
FBA_D39 FBA_DQM6 FBx_CMD16 CS0#_H
FBA_D40 V23 U25 FBA_DQM7
FBA_D41 V22 FBA_D40 FBA_DQM7
+1.05VS_VGA
1. 30ohms (ESR=0.01) Bead
+FB_PLLAVDD FBA_D41 FBx_CMD17
FBA_D42 T23 F19 FBA_DQS#0
2. Place close to BGA FBA_D43 U22 FBA_D42 FBA_DQS_RN0 C14 FBA_DQS#1
DIS@
600mA FBA_D44 Y24 FBA_D43 FBA_DQS_RN1 A16 FBA_DQS#2
FBx_CMD18 ODT_H
LV4 1 2 MPZ1608S300AT_2P~D +FB_PLLAVDD FBA_D45 AA24 FBA_D44 FBA_DQS_RN2 A22 FBA_DQS#3
FBA_D45 FBA_DQS_RN3 FBx_CMD19 CKE_H
FBA_D46 Y22 P25 FBA_DQS#4
FBA_D47 AA23 FBA_D46 FBA_DQS_RN4 W22 FBA_DQS#5
SM01003110J FBA_D47 FBA_DQS_RN5 FBx_CMD20 A13 A13
FBA_D48 AD27 AB27 FBA_DQS#6
FBA_D49 AB25 FBA_D48 FBA_DQS_RN6 T27 FBA_DQS#7
FBA_D49 FBA_DQS_RN7 FBx_CMD21 A8 A8
FBA_D50 AD26
FBA_D51 AC25 FBA_D50 E19 FBA_DQS0
+FB_PLLAVDD FBA_D51 FBA_DQS_WP0 FBx_CMD22 A6 A6
FBA_D52 AA27 C15 FBA_DQS1
FBA_D52 FBA_DQS_WP1
CV70
0.1U_0402_10V7K
CV71
1U_0402_6.3V6K
CV72
22U_0805_6.3V6M
FBA_D53 AA26 B16 FBA_DQS2 FBx_CMD23 A11 A11

FBA_D54 W26 FBA_D53 FBA_DQS_WP2 B22 FBA_DQS3
1 1 1 FBA_D54 FBA_DQS_WP3
FBA_D55 Y25 R25 FBA_DQS4 FBx_CMD24 A5 A5
FBA_D56 R26 FBA_D55 FBA_DQS_WP4 W23 FBA_DQS5
FBA_D56 FBA_DQS_WP5
DIS@
DIS@
DIS@
FBA_D57 T25 AB26 FBA_DQS6 FBx_CMD25 A3 A3

2 2 2 FBA_D58 N27 FBA_D57 FBA_DQS_WP6 T26 FBA_DQS7
FBA_D59 R27 FBA_D58 FBA_DQS_WP7
FBA_D59 FBx_CMD26 BA2 BA2
FBA_D60 V26
FBA_D61 V27 FBA_D60
FBA_D61 FBx_CMD27 BA1 BA1
Under GPU Near GPU FBA_D62 W27
FBA_D63 W25 FBA_D62
FBA_D63 FBx_CMD28 A12 A12
D24 FBA_CLK0
FBA_CLK0 FBA_CLK0 <28>
F16 D25 FBA_CLK0# FBx_CMD29 A10 A10
FB_PLLAVDD_1 FBA_CLK0_N FBA_CLK0# <28>
Under GPU P22
FB_PLLAVDD_2 N22 FBA_CLK1
FBA_CLK1 FBA_CLK1 <29> FBx_CMD30 RAS# RAS#
+FB_PLLAVDD D23 M22 FBA_CLK1#
FB_VREF_PROBE FBA_CLK1_N FBA_CLK1# <29>
0.1U_0402_10V7K DIS@ 2 1 CV73 D18
B H22 FBA_WCK01 C18 B
FB_DLLAVDD FBA_WCK01_N D17
FB_CLAMP F3 FBA_WCK23 D16
+1.5VS_VGA For GC6 <23,48> FB_CLAMP FB_CLAMP FBA_WCK23_N T24
FBA_WCK45 U24
RV55 1 @ 2 60.4_0402_1% F22 FBA_WCK45_N V24
+1.5VS_VGA FBA_DEBUG0 FBA_WCK67
RV56 1 @ 2 60.4_0402_1% J22 V25
FBA_DEBUG1 FBA_WCK67_N
N14PGV2@ SA00005NC10
For GC6 (+1.5VS_VGA)
+3VS
1
From PCH <14> DGPU_GC6_EN 2 QV8 @

DGPU_GC6_EN
G 2N7002KW_SOT323-3
S
3
RV57 1 @ 2 0_0402_5%
DV2 DIS@
From EC FB_CLAMP RV58 1 2 0_0402_5% GC6_EN 2 +1.5VS_VGA
1 FBVDDQ_PWR_EN
FBVDDQ_PWR_EN <54>
DGPU_PWROK 3
1
DAN202UT106_SOT323-3
@ RV59 SC600001U00 DIS@ RV60
A 10K_0402_5% 200K_0402_5% A
RV61 1 @ 2 0_0402_5%
<19,54,62,63> DGPU_PWROK
2
Dr-Bios.com
From +VGA_CORE IC (follow +3VS)
Issued Date 2012/12/05 Deciphered Date 2014/12/05 N14P_MEM IF/FB CLAMP

Rev
Custom 1.0
!##$%&'()*"*
5 4 3 2 1
5 4 3 2 1
Memory Partition A - Lower 32 bits

UV3 X76@
UV2 X76@
+FBA_VREF0 M8 E3 FBA_D19
+1.5VS_VGA +FBA_VREF0 M8 E3 FBA_D4 H1 VREFCA DQL0 F7 FBA_D20
VREFCA DQL0 VREFDQ DQL1 FBA_MA[15..0] <27,29>
H1 F7 FBA_D1 F2 FBA_D17
VREFDQ DQL1 F2 FBA_D7 FBA_MA0 N3 DQL2 F8 FBA_D21
DQL2 A0 DQL3 Group2 (IN1) FBA_BA[2..0] <27,29>
1
D FBA_MA0 N3 F8 FBA_D0 FBA_MA1 P7 H3 FBA_D16 D

RV62 FBA_MA1 P7 A0 DQL3 H3 FBA_D6 FBA_MA2 P3 A1 DQL4 H8 FBA_D23
A1 DQL4 Group0 (IN3) A2 DQL5
1.1K_0402_1% FBA_MA2 P3 H8 FBA_D3 FBA_MA3 N2 G2 FBA_D18
A2 DQL5 A3 DQL6 FBA_D[0..63] <27,29>
DIS@ FBA_MA3 N2 G2 FBA_D5 FBA_MA4 P8 H7 FBA_D22
FBA_MA4 P8 A3 DQL6 H7 FBA_D2 FBA_MA5 P2 A4 DQL7
FBA_DQM[7..0] <27,29>
2
+FBA_VREF0 FBA_MA5 P2 A4 DQL7 FBA_MA6 R8 A5

FBA_MA6 R8 A5 FBA_MA7 R2 A6 D7 FBA_D10
A6 A7 DQU0 FBA_DQS[7..0] <27,29>
CV74
0.01U_0402_16V7K
FBA_MA7 R2 D7 FBA_D29 FBA_MA8 T8 C3 FBA_D15

A7 DQU0 A8 DQU1
1
1 FBA_MA8 T8 C3 FBA_D25 FBA_MA9 R3 C8 FBA_D8

A8 DQU1 A9 DQU2 FBA_DQS#[7..0] <27,29>
RV63 FBA_MA9 R3 C8 FBA_D30 FBA_MA10 L7 C2 FBA_D13 Group1 (TOP)
1.1K_0402_1% FBA_MA10 L7 A9 DQU2 C2 FBA_D26 FBA_MA11 R7 A10/AP DQU3 A7 FBA_D9
A10/AP DQU3 A11 DQU4
DIS@
DIS@ FBA_MA11 R7 A7 FBA_D28 Group3 (BOT) FBA_MA12 N7 A2 FBA_D12

2 FBA_MA12 N7 A11 DQU4 A2 FBA_D24 FBA_MA13 T3 A12 DQU5 B8 FBA_D11
2
FBA_MA13 T3 A12 DQU5 B8 FBA_D31 FBA_MA14 T7 A13 DQU6 A3 FBA_D14

FBA_MA14 T7 A13 DQU6 A3 FBA_D27 FBA_MA15 M7 A14 DQU7
FBA_MA15 M7 A14 DQU7 A15/BA3
A15/BA3 +1.5VS_VGA
+1.5VS_VGA FBA_BA0 M2
BA0 VDD1
B2 Mode D - Mirror Mode Mapping
FBA_BA0 M2 B2 FBA_BA1 N8 D9
FBA_BA1 N8 BA0 VDD1 D9 FBA_BA2 M3 BA1 VDD2 G7
FBA_BA2 M3 BA1 VDD2 G7 BA2 VDD3 K2
BA2 VDD3 VDD4 DATA Bus
K2 K8
VDD4 K8 VDD5 N1
VDD5 VDD6
Address 0..31 32..63
N1 FBA_CLK0 J7 N9
FBA_CLK0 FBA_CLK0 J7 VDD6 N9 FBA_CLK0# K7 CK VDD7 R1
<27> FBA_CLK0 CK VDD7 CK VDD8 FBx_CMD0 CS0#_L
FBA_CLK0# K7 R1 FBA_CKE_L K9 R9 FBA_ODT_L
<27> FBA_CLK0# CK VDD8 CKE/CKE0 VDD9
FBA_CKE_L K9 R9 FBx_CMD1
<27> FBA_CKE_L CKE/CKE0 VDD9
1
RV64 FBA_ODT_L K1 A1 FBA_CKE_L FBx_CMD2 ODT_L

160_0402_1% FBA_ODT_L K1 A1 FBA_CS0#_L L2 ODT/ODT0 VDDQ1 A8
<27> FBA_ODT_L ODT/ODT0 VDDQ1 CS/CS0 VDDQ2
DIS@ FBA_CS0#_L L2 A8 FBA_RAS# J3 C1 FBx_CMD3 CKE_L
<27> FBA_CS0#_L CS/CS0 VDDQ2 RAS VDDQ3
1
FBA_RAS# J3 C1 FBA_CAS# K3 C9
<27,29> FBA_RAS#
2
C FBA_CAS# K3 RAS VDDQ3 C9 FBA_WE# L3 CAS VDDQ4 D2 RV65 RV66 C

<27,29> FBA_CAS# CAS VDDQ4 WE VDDQ5 FBx_CMD4 A14 A14
FBA_CLK0# FBA_WE# L3 D2 E9 10K_0402_5% 10K_0402_5%
<27,29> FBA_WE# WE VDDQ5 VDDQ6
E9 F1 DIS@ DIS@ FBx_CMD5 RST RST
VDDQ6 F1 FBA_DQS2 F3 VDDQ7 H2
2
FBA_DQS0 F3 VDDQ7 H2 FBA_DQS1 C7 DQSL VDDQ8 H9
DQSL VDDQ8 DQSU VDDQ9 FBx_CMD6 A9 A9
FBA_DQS3 C7 H9
DQSU VDDQ9
FBx_CMD7 A7 A7
FBA_DQM2 E7 A9
FBA_DQM0 E7 A9 FBA_DQM1 D3 DML VSS1 B3
DML VSS1 DMU VSS2 FBx_CMD8 A2 A2
FBA_DQM3 D3 B3 E1
DMU VSS2 E1 VSS3 G8
VSS3 VSS4 FBx_CMD9 A0 A0
G8 FBA_DQS#2 G3 J2
FBA_DQS#0 G3 VSS4 J2 FBA_DQS#1 B7 DQSL VSS5 J8
DQSL VSS5 DQSU VSS6 FBx_CMD10 A4 A4
FBA_DQS#3 B7 J8 M1
DQSU VSS6 M1 VSS7 M9
M9 P1
VSS8 P1 FBA_RST# T2 VSS9 P9
VSS9 RESET VSS10 FBx_CMD12 BA0 BA0
FBA_RST# T2 P9 T1
<27,29> FBA_RST# RESET VSS10 VSS11
T1 L8 T9 FBx_CMD13 WE# WE#
L8 VSS11 T9 ZQ/ZQ0 VSS12
ZQ/ZQ0 VSS12
FBx_CMD14 A15 A15
1
J1 B1
NC/ODT1 VSSQ1
1
J1 B1 RV69 L1 B9 FBx_CMD15 CAS# CAS#

RV67 RV68 L1 NC/ODT1 VSSQ1 B9 243_0402_1% J9 NC/CS1 VSSQ2 D1
10K_0402_5% 243_0402_1% J9 NC/CS1 VSSQ2 D1 DIS@ L9 NC/CE1 VSSQ3 D8
NC/CE1 VSSQ3 NCZQ1 VSSQ4 FBx_CMD16 CS0#_H
DIS@ DIS@ L9 D8 E2
2
NCZQ1 VSSQ4 E2 VSSQ5 E8 FBx_CMD17
2
VSSQ5 E8 VSSQ6 F9
VSSQ6 F9 VSSQ7 G1
VSSQ7 VSSQ8 FBx_CMD18 ODT_H
G1 G9
VSSQ8 G9 VSSQ10
VSSQ10 FBx_CMD19 CKE_H
96-BALL
B 96-BALL SDRAM DDR3 B
FBx_CMD20 A13 A13
SDRAM DDR3 K4W4G1646B-HC11_FBGA96
K4W4G1646B-HC11_FBGA96 FBx_CMD21 A8 A8
FBx_CMD22 A6 A6
FBx_CMD23 A11 A11
FBx_CMD24 A5 A5
FBx_CMD25 A3 A3
FBx_CMD26 BA2 BA2
+1.5VS_VGA +1.5VS_VGA
U1406 SIDE U1407 SIDE FBx_CMD27 BA1 BA1
FBx_CMD28 A12 A12
CV75
0.1U_0402_10V7K
CV76
0.1U_0402_10V7K
CV77
0.1U_0402_10V7K
CV78
0.1U_0402_10V7K
CV79
0.1U_0402_10V7K
CV80
1U_0402_6.3V6K
CV81
1U_0402_6.3V6K
CV82
1U_0402_6.3V6K
CV83
1U_0402_6.3V6K
CV84
1U_0402_6.3V6K
CV85
0.1U_0402_10V7K
CV86
0.1U_0402_10V7K
CV87
0.1U_0402_10V7K
CV88
0.1U_0402_10V7K
CV89
0.1U_0402_10V7K
CV90
1U_0402_6.3V6K
CV91
1U_0402_6.3V6K
CV92
1U_0402_6.3V6K
CV93
1U_0402_6.3V6K
CV94
1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FBx_CMD29 A10 A10
FBx_CMD30 RAS# RAS#
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
@ @
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
A A
5
Dr-Bios.com 4
Issued Date
3
Date:
2012/12/05

Custom

Deciphered Date
2
2014/12/05
Title
N14P_DDR3-A LOWER
!##$%&'()*"*
1
Sheet 28 of 57
Rev
1.0
5 4 3 2 1
Memory Partition A - Upper 32 bits

UV4 X76@ UV5 X76@
+1.5VS_VGA
+FBA_VREF1 M8 E3 FBA_D36 +FBA_VREF1 M8 E3 FBA_D63
H1 VREFCA DQL0 F7 FBA_D34 H1 VREFCA DQL0 F7 FBA_D58
VREFDQ DQL1 VREFDQ DQL1
1
D F2 FBA_D37 F2 FBA_D60 D
DQL2 DQL2 FBA_D[0..63] <27,28>
RV70 FBA_MA0 N3 F8 FBA_D35 FBA_MA0 N3 F8 FBA_D59
1.1K_0402_1% FBA_MA1 P7 A0 DQL3 H3 FBA_D39 FBA_MA1 P7 A0 DQL3 H3 FBA_D61
A1 DQL4 Group4 (IN1) A1 DQL4 Group7 (IN3) FBA_MA[15..0] <27,28>
DIS@ FBA_MA2 P3 H8 FBA_D32 FBA_MA2 P3 H8 FBA_D56
FBA_MA3 N2 A2 DQL5 G2 FBA_D38 FBA_MA3 N2 A2 DQL5 G2 FBA_D62
FBA_BA[2..0] <27,28>
2
+FBA_VREF1 FBA_MA4 P8 A3 DQL6 H7 FBA_D33 FBA_MA4 P8 A3 DQL6 H7 FBA_D57

FBA_MA5 P2 A4 DQL7 FBA_MA5 P2 A4 DQL7
A5 A5 FBA_DQM[7..0] <27,28>
CV95
0.01U_0402_16V7K
FBA_MA6 R8 FBA_MA6 R8
A6 A6
1
1 FBA_MA7 R2 D7 FBA_D44 FBA_MA7 R2 D7 FBA_D55

A7 DQU0 A7 DQU0 FBA_DQS[7..0] <27,28>
RV71 FBA_MA8 T8 C3 FBA_D42 FBA_MA8 T8 C3 FBA_D51
1.1K_0402_1% FBA_MA9 R3 A8 DQU1 C8 FBA_D46 FBA_MA9 R3 A8 DQU1 C8 FBA_D54
A9 DQU2 A9 DQU2 FBA_DQS#[7..0] <27,28>
DIS@
DIS@ FBA_MA10 L7 C2 FBA_D41 FBA_MA10 L7 C2 FBA_D49

2 FBA_MA11 R7 A10/AP DQU3 A7 FBA_D47 FBA_MA11 R7 A10/AP DQU3 A7 FBA_D52
Group5 (TOP) Group6 (BOT)
2
FBA_MA12 N7 A11 DQU4 A2 FBA_D43 FBA_MA12 N7 A11 DQU4 A2 FBA_D50

FBA_MA13 T3 A12 DQU5 B8 FBA_D45 FBA_MA13 T3 A12 DQU5 B8 FBA_D53
FBA_MA14 T7 A13 DQU6 A3 FBA_D40 FBA_MA14 T7 A13 DQU6 A3 FBA_D48
FBA_MA15 M7 A14 DQU7 FBA_MA15 M7 A14 DQU7
A15/BA3 +1.5VS_VGA A15/BA3 +1.5VS_VGA
FBA_BA0 M2 B2 FBA_BA0 M2 B2
FBA_BA1 N8 BA0 VDD1 D9 FBA_BA1 N8 BA0 VDD1 D9
FBA_CLK1 FBA_BA2 M3 BA1
BA2
VDD2
VDD3
G7 FBA_BA2 M3 BA1
BA2
VDD2
VDD3
G7 Mode D - Mirror Mode Mapping
K2 K2
VDD4 K8 VDD4 K8
VDD5 VDD5
1
N1 N1 DATA Bus
RV72 FBA_CLK1 J7 VDD6 N9 FBA_CLK1 J7 VDD6 N9
<27> FBA_CLK1 CK VDD7 CK VDD7
160_0402_1% FBA_CLK1# K7 R1 FBA_CLK1# K7 R1 Address 0..31 32..63
<27> FBA_CLK1# CK VDD8 CK VDD8
DIS@ FBA_CKE_H K9 R9 FBA_CKE_H K9 R9
<27> FBA_CKE_H CKE/CKE0 VDD9 CKE/CKE0 VDD9
FBx_CMD0 CS0#_L
2
FBA_CLK1# FBA_ODT_H K1 A1 FBA_ODT_H K1 A1 FBx_CMD1

<27> FBA_ODT_H ODT/ODT0 VDDQ1 ODT/ODT0 VDDQ1
FBA_CS0#_H L2 A8 FBA_CS0#_H L2 A8
C <27> FBA_CS0#_H CS/CS0 VDDQ2 CS/CS0 VDDQ2 C
FBA_RAS# J3 C1 FBA_RAS# J3 C1 FBx_CMD2 ODT_L
<27,28> FBA_RAS# RAS VDDQ3 RAS VDDQ3
FBA_CAS# K3 C9 FBA_CAS# K3 C9
<27,28> FBA_CAS# CAS VDDQ4 CAS VDDQ4
FBA_WE# L3 D2 FBA_WE# L3 D2 FBx_CMD3 CKE_L
<27,28> FBA_WE# WE VDDQ5 WE VDDQ5
E9 E9
VDDQ6 F1 VDDQ6 F1
VDDQ7 VDDQ7 FBx_CMD4 A14 A14
FBA_DQS4 F3 H2 FBA_DQS7 F3 H2
FBA_DQS5 C7 DQSL VDDQ8 H9 FBA_DQS6 C7 DQSL VDDQ8 H9
DQSU VDDQ9 DQSU VDDQ9 FBx_CMD5 RST RST
FBx_CMD6 A9 A9
FBA_DQM4 E7 A9 FBA_DQM7 E7 A9
FBA_DQM5 D3 DML VSS1 B3 FBA_DQM6 D3 DML VSS1 B3
DMU VSS2 DMU VSS2 FBx_CMD7 A7 A7
E1 E1
VSS3 G8 VSS3 G8
FBA_DQS#4 G3 J2 FBA_DQS#7 G3 J2
FBA_DQS#5 B7 DQSL VSS5 J8 FBA_DQS#6 B7 DQSL VSS5 J8
DQSU VSS6 DQSU VSS6 FBx_CMD9 A0 A0
M1 M1
FBA_CKE_H VSS7 M9 VSS7 M9
P1 P1
FBA_RST# T2 VSS9 P9 FBA_RST# T2 VSS9 P9
<27,28> FBA_RST# RESET VSS10 RESET VSS10 FBx_CMD11 A1 A1
FBA_ODT_H T1 T1
L8 VSS11 T9 L8 VSS11 T9
ZQ/ZQ0 VSS12 ZQ/ZQ0 VSS12 FBx_CMD12 BA0 BA0
FBx_CMD13 WE# WE#
1
1
J1 B1 J1 B1
RV73 RV74 RV75 L1 NC/ODT1 VSSQ1 B9 RV76 L1 NC/ODT1 VSSQ1 B9
NC/CS1 VSSQ2 NC/CS1 VSSQ2 FBx_CMD14 A15 A15
10K_0402_5% 10K_0402_5% 243_0402_1% J9 D1 243_0402_1% J9 D1
DIS@ DIS@ DIS@ L9 NC/CE1 VSSQ3 D8 DIS@ L9 NC/CE1 VSSQ3 D8
NCZQ1 VSSQ4 NCZQ1 VSSQ4 FBx_CMD15 CAS# CAS#
E2 E2
2
2
VSSQ5 E8 VSSQ5 E8
VSSQ6 VSSQ6 FBx_CMD16 CS0#_H
F9 F9
VSSQ7 G1 VSSQ7 G1
VSSQ8 VSSQ8 FBx_CMD17
G9 G9
B VSSQ10 VSSQ10 B
FBx_CMD18 ODT_H
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 FBx_CMD19 CKE_H
K4W4G1646B-HC11_FBGA96 K4W4G1646B-HC11_FBGA96
FBx_CMD20 A13 A13
FBx_CMD21 A8 A8
FBx_CMD22 A6 A6
FBx_CMD23 A11 A11
FBx_CMD24 A5 A5
FBx_CMD25 A3 A3
FBx_CMD26 BA2 BA2
FBx_CMD27 BA1 BA1
FBx_CMD28 A12 A12
+1.5VS_VGA +1.5VS_VGA U1408 SIDE
U1409 SIDE FBx_CMD29 A10 A10
FBx_CMD30 RAS# RAS#
CV96
0.1U_0402_10V7K
CV97
0.1U_0402_10V7K
CV98
0.1U_0402_10V7K
CV99
0.1U_0402_10V7K
CV100
0.1U_0402_10V7K
CV101
1U_0402_6.3V6K
CV102
1U_0402_6.3V6K
CV103
1U_0402_6.3V6K
CV104
1U_0402_6.3V6K
CV105
1U_0402_6.3V6K
CV106
0.1U_0402_10V7K
CV107
0.1U_0402_10V7K
CV108
0.1U_0402_10V7K
CV109
0.1U_0402_10V7K
UV6
0.1U_0402_10V7K
CV110
1U_0402_6.3V6K
CV111
1U_0402_6.3V6K
CV112
1U_0402_6.3V6K
CV113
1U_0402_6.3V6K
CV114
1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
@ @ @ @ @ @ @
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
A A
5
Dr-Bios.com 4
Issued Date
3
Date:
2012/12/05

Custom

Deciphered Date
2
2014/12/05
Title
N14P_DDR3-A UPPER
!##$%&'()*"*
1
Sheet 29 of 57
Rev
1.0
5 4 3 2 1
+3VS_VGA
Physical Logical Logical Logical Logical
Strapping pin Power Rail Strapping Bit3 Strapping Bit2 Strapping Bit1 Strapping Bit0
D D
ROM_SCLK +3VS_VGA PCI_DEVID[4] SUB_VENDOR PCI_DEVID[5] PEX_PLL_EN_TERM

ROM_SI +3VS_VGA RAM_CFG[3] RAM_CFG[2] RAM_CFG[1] RAM_CFG[0]
1
RV77 RV78 RV79 RV80 RV81 ROM_SO +3VS_VGA FB[1] FB[0] SMB_ALT_ADDR VGA_DEVICE
45.3K_0402_1% 10K_0402_5% 29.4K_0402_1% 10K_0402_5% 10K_0402_5%
N14PGV2@ X76@ X76@ X76@ @ STRAP0 +3VS_VGA USER[3] USER[2] USER[1] USER[0]
2
N14M @ STRAP1 +3VS_VGA 3GIO_PADCFG[3] 3GIO_PADCFG[2] 3GIO_PADCFG[1] 3GIO_PADCFG[0]
STRAP0
<24> STRAP0
STRAP1 N14P @
<24> STRAP1 STRAP2 +3VS_VGA PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0]
STRAP2
<24> STRAP2
STRAP3 STRAP3 +3VS_VGA SOR3_EXPOSED SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED
<24> STRAP3
STRAP4
<24> STRAP4
STRAP4 +3VS_VGA RESERVED PCIE_SPEED_ PCIE_MAX_SPEED DP_PLL_VDD33V
CHANGE_GEN3
1
1
RV82 RV83 RV84 RV85 RV86
10K_0402_5% 10K_0402_5% 10K_0402_5% 4.99K_0402_1% 10K_0402_5%
@ X76@ X76@ X76@ N14MGL@
N14M @
2
2
N14P @
Pull-up to
Resistor Values +3VS_VGA Pull-down to Gnd
5K 1000 0000
10K 1001 0001
C
15K 1010 0010 C
+3VS_VGA
20K 1011 0011
25K 1100 0100
30K 1101 0101
1
1
35K 1110 0110
RV87 RV88 RV89
10K_0402_5% 4.99K_0402_1% 4.99K_0402_1% 45K 1111 0111
@ N14PGV2@ N14PGV2@
2
ROM_SI
<24> ROM_SI
ROM_SO
<24> ROM_SO
ROM_SCLK SUB_VENDOR 3GIO_PADCFG[3:0]
<24> ROM_SCLK
0 No VBIOS ROM 0110 Gen1/Gen2 support only
1
N14M @ RV90 RV91 RV92 1 BIOS ROM is present (Default) 0000 Gen3 support
10K_0402_5% 10K_0402_5% 10K_0402_5%
N14P @ X76@ N14MGL@ N14MGL@
2
FB[1:0] SMBUS_ALT_ADDR VGA_DEVICE

B B
0 Reserved 0 0x9E (Default) 0 3D Device (Class Code 302h)

ZZZ2 ZZZ3 ZZZ4 ZZZ5
For N14P-GV2 QS Sample 1
ROM_SO change from PU 10K to PU 5K 1 Reserved 1 0x9C (Multi-GPU usage) VGA Device (Default)
ROM_SCLK change from PD 15K to PU 5K
STRAP1 change from PD 5K to PD 45K 2 256MB (Default)
MT41J128M16JT K4W2G1646E K4W4G1646B MT41K256M16HA STRAP2 change from PU 30K to PD 15K PCIE_MAX_SPEED PEX_PLL_EN_TERM
M1G@ S1G@ S2G@ M2G@
SA00005M110 SA00005SH20 SA00005OM00 SA00005ON00 STRAP4 change from PD 5K to PD 45K 3 Reserved
0 Limit booting to PCIE Gen1 0 Disable (Default)
USER Straps 1 Allow booting to PCIE Gen 2/3 1 Enable
RV77 RV86 User[3:0]
10K_0402_5% 45.3K_0402_1% 1000-1100 Customer defined

PCIE_SPEED_CHANGE_GEN3 DP_PLL_VDD33V
N14MGL@ N14PGV2@ !"#$%RV86,
Load BOM!
SD02810028T SD03445328T 0 Disable PCIE Gen3 operation 0 Reserved
RV77
1 Enable PCIE Gen3 operation 1 Default
ZZZ6 ZZZ7 ZZZ8 ZZZ9
A Micron Samsung Micron Samsung A

M1G@ S2G@ M2G@ S1G@
X7600108001 X7600108004 X7600108005 X7600108002
5
Dr-Bios.com 4
3 2
Title
Date:
N14P_MISC(1/2)
Custom
!"#$%&'()*+*
1
Sheet 30 of 57
Rev
1.0
5 4 3 2 1
D D
X76 PU, RV78 PU, RV79 PU, RV80

RV90 RV77 PD, RV83 PD, RV84 PD, RV85 PD, RV86
GPU FB Memory GDDR3 ROM_SO ROM_SCLK ROM_SI STRAP0 STRAP1 STRAP2 STRAP3 STRAP4
Samsung K4W2G1646E-BC1A
PD 45K
1000MHz
128Mx16
Micron MT41J128M16JT-093G
PD 30K
1000MHz PD 45.3K
N14P-GV2
128Mx16 PU 5K PU 45.3K PD 45.3K PD 15K PD 5K
S2G, X76~04 *
Samsung K4W4G1646B-HC11
PD 20K
SA00005OM00 900MHz
256Mx16
M2G, X76~05 *
Micron MT41K256M16HA-107G
PD 10K
C SA00005ON00 900MHz C
256Mx16
PU, RV78 PU, RV79 PU, RV80

RV77 PD, RV83 PD, RV84 PD, RV85 PD, RV86
GPU FB Memory GDDR3 ROM_SO ROM_SCLK ROM_SI STRAP0 STRAP1 STRAP2 STRAP3 STRAP4
S1G, X76~02 *
Samsung K4W2G1646E-BC1A
PU 10K PD 10K PU 10K PD 10K
SA00005SH20 1000MHz
128Mx16
Hynix H5TQ2G63DFR-N0C
PD 10K PU 10K PU 10K PD 10K
1000MHz
128Mx16
M1G, X76~01 *
Micron MT41J128M16JT-093G
PU 10K PD 10K PD 10K PD 10K PD 10K
B SA00005M110 1000MHz
128Mx16
PD 10K B
N14M-GL
Samsung K4W4G1646B-HC11
PU 10K PU 10K PU 10K PU 10K
900MHz
256Mx16
Hynix H5TQ4G63MFR-11C
PU 10K PU 10K PD 10K PD 10K
900MHz
256Mx16
Micron MT41K256M16HA-107G
PD 10K PD 10K PU 10K PU 10K
900MHz
256Mx16
A A
5
Dr-Bios.com
4
3 2
Title
Date:
N14P_MISC(2/2)
Custom
!"#$%&'()*+*
1
Sheet 31 of 57
Rev
1.0
A B C D E
1 1
Thermal Sensor
Thermal Sensor
placed near by VRAM
U1
+3VS
1 10 EC_SMB_CK3
VDD SMCLK EC_SMB_CK3 <17,23,48>
REMOTE1+ 2 9 EC_SMB_DA3
DP1 SMDATA EC_SMB_DA3 <17,23,48>
1
2 REMOTE1- 3 8 2
C2 DN1 ALERT#
.1U_0402_16V4-Z REMOTE2+ 4 7 R3 1 @ 2 10K_0402_5% +3VS
2 DP2/DN3 THERM#
REMOTE2- 5 6
DN2/DP3 GND
F75303M_MSOP10
Address 1001_101xb
Internal pull up 1.2K to 1.5V
R for initial thermal shutdown temp
Close to U2 Close to BOTTOM DDR3 Close to +CPU_CORE

REMOTE1+ REMOTE2+ REMOTE2+/-:
REMOTE1+ REMOTE2+
1 1 1 1
Trace width/space:10/10 mil
1
C C
C3 C4 C5 @ 2 Q1 C6 @ 2 Q2 Trace length:<8"
2200P_0402_50V7-K 2200P_0402_50V7-K 100P_0402_50V8-J B MMST3904-7-F_SOT323-3 100P_0402_50V8-J B MMST3904-7-F_SOT323-3
2 2 2 E SB000010U00 2 E SB000010U00
3
REMOTE1- REMOTE2-
REMOTE1- REMOTE2-
3 3
4 4
A
Dr-Bios.com B
Deciphered Date
C D
2014/12/05
Custom
Date:
Title

THERMAL SENSOR
!##$%&'()*"*
E
Sheet 32 of 57
Rev
1.0
5 4 3 2 1
D D
APS G-Sensor
+3VALW_GS +3V_GS
R84 1 @ 2 0_0402_5%
W=40 mils
+3VALW R4 1 2 0_0402_5% +3VALW_GS 3 1 +3V_GS
1 1 1
+3VS R73 1 @ 2 0_0402_5%
C7 Q3 C8 @ C9
2
.1U_0402_16V4-Z AP2301GN-HF_SOT23-3 .01U_0402_16V7-K 10U_0603_6.3V6M
2 SB00000YL00 2 2
R7
R85 1 @ 2 0_0402_5% 1 2
C <14> PCH_GS_ON# C
1
100K_0402_5%
R90 1 2 0_0402_5% @ C10
<48> EC_GS_ON#
0.01U_0402_16V7K
2
R8 1 2 100K_0402_5% UGSEN1
GS_SELFTEST 2 12 VOUTX R9 1 2 56K_0402_5% GS_VOUTX

<48> GS_SELFTEST ST VoutX GS_VOUTX <48>
10 VOUTY R10 1 2 56K_0402_5% GS_VOUTY
VoutY GS_VOUTY <48>
8
+3V_GS VoutZ
1 1 1 1
14
15 VDD_1 C11 C12 C13 C14
VDD_2 .1U_0402_16V7K .1U_0402_16V7K .1U_0402_16V7K .1U_0402_16V7K
1 1 2 2 2 2
1
C15 C16 NC1 4
10U_0603_6.3V6M .1U_0402_16V7K 3 NC2 9
2 2 5 GND1 NC3 11
6 GND2 NC4 13
7 GND3 NC5 16 APS_GND
GND4 NC6
B B
APS_GND LIS34ALTR_LGA16_4X4
SA000037F0J
JAPS1 @
1 2
2MM
APS_GND
A A
5
Dr-Bios.com 4
Deciphered Date
3 2
2014/12/05

Custom

Title
APS G-SENSOR
!##$%&'()*"*
1
Sheet 33 of 57
Rev
1.0
5 4 3 2 1
+3VS +5VS_HDMI +3VS
1
2
R11 R12 R13
G
2.2K_0402_5% 2.2K_0402_5% 1M_0402_5% Q5
2
G
D 2N7002KW_SOT323-3 D
2
PCH_HDMI_CLK 1 6 HDMI_CLK_CON PCH_HDMI_HPD 3 1 HDMI_DET_CON
S
<14> PCH_HDMI_CLK <14> PCH_HDMI_HPD
D
5
1
Q4A
G
2N7002KDWH_SOT363-6
SB00000YR00 R15
20K_0402_5%
PCH_HDMI_DATA 4 3 HDMI_DAT_CON
S
<14> PCH_HDMI_DATA
2
D
Q4B
2N7002KDWH_SOT363-6
SB00000YR00
<8> CPU_HDMI_CLK+ CPU_HDMI_CLK+ C17 1 2 0.1U_0402_10V7-K HDMI_CLK+_C R17 1 @ 2 0_0402_5% HDMI_CLK+_CON
1 2
1 2 +5VS U2 +5VS_HDMI
L1 WCM-2012-900T_4P
4 3 SM070003100 3 1
4 3 VOUT
<8> CPU_HDMI_CLK- CPU_HDMI_CLK- C18 1 2 0.1U_0402_10V7-K HDMI_CLK-_C R18 1 @ 2 0_0402_5% HDMI_CLK-_CON 1 C19
VIN SA00004ZB0J 0.1U_0402_10V7-K
2 2
GND
<8> CPU_HDMI_TX0+ CPU_HDMI_TX0+ C20 1 2 0.1U_0402_10V7-K HDMI_TX0+_C R19 1 @ 2 0_0402_5% HDMI_TX0+_CON 1 1
APL3517AI-TRG_SOT23-3
1 2 C21 C22
1 2 2200P_0402_50V7-K 0.1U_0402_10V7-K
C L2 WCM-2012-900T_4P 2 2 C
4 3 SM070003100
4 3
<8> CPU_HDMI_TX0- CPU_HDMI_TX0- C23 1 2 0.1U_0402_10V7-K HDMI_TX0-_C R20 1 @ 2 0_0402_5% HDMI_TX0-_CON
CPU_HDMI_TX1+ C24 1 2 0.1U_0402_10V7-K HDMI_TX1+_C R21 1 @ 2 0_0402_5% HDMI_TX1+_CON

<8> CPU_HDMI_TX1+
HDMI CONN.
1 2
1 2 JHDMI1 ME@
L3 WCM-2012-900T_4P HDMI_DET_CON 19
4 3 SM070003100 18 HP_DET
4 3 +5VS_HDMI +5V
17
CPU_HDMI_TX1- C25 1 2 0.1U_0402_10V7-K HDMI_TX1-_C R22 1 @ 2 0_0402_5% HDMI_TX1-_CON HDMI_DAT_CON 16 DDC/CEC_GND
<8> CPU_HDMI_TX1- SDA
HDMI_CLK_CON 15
14 SCL
CPU_HDMI_TX2+ C26 1 2 0.1U_0402_10V7-K HDMI_TX2+_C R23 1 @ 2 0_0402_5% HDMI_TX2+_CON 13 Reserved
<8> CPU_HDMI_TX2+ CEC
HDMI_CLK-_CON 12 20
1 2 11 CK- GND1 21
1 2 HDMI_CLK+_CON 10 CK_shield GND2 22
L4 WCM-2012-900T_4P HDMI_TX0-_CON 9 CK+ GND3 23
4 3 SM070003100 8 D0- GND4
4 3 HDMI_TX0+_CON 7 D0_shield
CPU_HDMI_TX2- C27 1 2 0.1U_0402_10V7-K HDMI_TX2-_C R24 1 @ 2 0_0402_5% HDMI_TX2-_CON HDMI_TX1-_CON 6 D0+
<8> CPU_HDMI_TX2- D1-
5
HDMI_TX1+_CON 4 D1_shield
HDMI_TX2-_CON 3 D1+
2 D2-
HDMI_TX2+_CON 1 D2_shield
D2+
CONCR_099ATAC19NBLCNF
B B
For ESD
D1 D2 D3
RP1 +5VS_HDMI 1 1 10 9 +5VS_HDMI HDMI_CLK-_CON 1 1 10 9 HDMI_CLK-_CON HDMI_TX1-_CON 1 1 10 9 HDMI_TX1-_CON
HDMI_CLK-_CON 1 8 HDMI_GND
HDMI_CLK+_CON 2 7 HDMI_DET_CON 2 2 9 8 HDMI_DET_CON HDMI_CLK+_CON 2 2 9 8 HDMI_CLK+_CON HDMI_TX1+_CON 2 2 9 8 HDMI_TX1+_CON
HDMI_TX0-_CON 3 6
HDMI_TX0+_CON 4 5 HDMI_DAT_CON 4 4 7 7 HDMI_DAT_CON HDMI_TX0-_CON 4 4 7 7 HDMI_TX0-_CON HDMI_TX2-_CON 4 4 7 7 HDMI_TX2-_CON
470_0804_8P4R_5% HDMI_CLK_CON 5 5 6 6 HDMI_CLK_CON HDMI_TX0+_CON 5 5 6 6 HDMI_TX0+_CON HDMI_TX2+_CON 5 5 6 6 HDMI_TX2+_CON

SD300002O0T
3 3 3 3 3 3
RP2
HDMI_TX1-_CON 1 8 8 8 8
HDMI_TX1+_CON 2 7
HDMI_TX2-_CON 3 6 AZ1045-04F_DFN2510P10E-10-9 AZ1045-04F_DFN2510P10E-10-9 AZ1045-04F_DFN2510P10E-10-9
HDMI_TX2+_CON 4 5
470_0804_8P4R_5%
SD300002O0T
1
A D A
+3VS 2 Q6
G 2N7002KW_SOT323-3
Dr-Bios.com
S
3
Issued Date 2012/12/05 Deciphered Date 2014/12/05 HDMI CONN.

Rev
Custom 1.0
!##$%&'()*"*
5 4 3 2 1
5 4 3 2 1
+5VS +CRT_VCC
U8
D4 D5 W=40mils
CRT_B_CON 3 6 CRT_R_CON VSYNC_CON 3 6 HSYNC_CON 3
I/O2 I/O4 I/O2 I/O4 W=40mils VOUT 1
1 C28
VIN SA00004ZB0J 0.1U_0402_10V7-K
2 5 2 5 2 2
GND VDD +CRT_VCC GND VDD +CRT_VCC GND
1 1
D D
C157 C82 APL3517AI-TRG_SOT23-3
1 4 CRT_G_CON CRT_DDC_CLK_CON 1 4 CRT_DDC_DAT_CON 2200P_0402_50V7-K 0.1U_0402_10V7-K
I/O1 I/O3 I/O1 I/O3 2 2
AZC099-04S.R7G_SOT23-6 AZC099-04S.R7G_SOT23-6
closer to JCRT
CRT Connector
JCRT1 ME@
From PCH 6
L5 SM01000MC00 1 11
@ T79
@T79
PCH_CRT_R 1 2 CRT_R_CON 1
<14> PCH_CRT_R
NBQ100505T-800Y-N_2P 7
L6 SM01000MC00 CRT_DDC_DAT_CON 12
PCH_CRT_G 1 2 CRT_G_CON 2
<14> PCH_CRT_G
NBQ100505T-800Y-N_2P 8
L7 SM01000MC00 HSYNC_CON 13
PCH_CRT_B 1 2 CRT_B_CON 3
<14> PCH_CRT_B
NBQ100505T-800Y-N_2P +CRT_VCC 9
10P_0402_50V8-J
10P_0402_50V8-J
10P_0402_50V8-J
10P_0402_50V8-J
10P_0402_50V8-J
10P_0402_50V8-J
1 1 1 1 1 1 VSYNC_CON 14 16
1
150_0402_1%
150_0402_1%
150_0402_1%
4 17
C29
C30
C31
C32
C33
C34
10
R33 R34 R35 CRT_DDC_CLK_CON 15
2 2 2 2 2 2 5
C C
2
2
SUYIN_070546HR015S21BZR
Only for 15'

closer to JCRT
+CRT_VCC
C35 1 2 0.1U_0402_16V7-K OE# R36 1 2 1K_0402_5%

5
From PCH L8 SM01000MC00

OE#
P
PCH_CRT_HSYNC 2 4 CRT_HSYNC_1 R37 1 2 33_0603_5% CRT_HSYNC_2 1 2 HSYNC_CON

<14> PCH_CRT_HSYNC A Y NBQ100505T-800Y-N_2P 1
G
U3
SN74AHCT1G125DCKR_SC70-5 @ C36
3
10P_0402_50V8-J
2
+CRT_VCC
C37 1 2 0.1U_0402_16V7-K
B B
5
L9 SM01000MC00
OE#
P
PCH_CRT_VSYNC 2 4 CRT_VSYNC_1 R38 1 2 33_0603_5% CRT_VSYNC_2 1 2 VSYNC_CON

<14> PCH_CRT_VSYNC A Y NBQ100505T-800Y-N_2P 1
G
U4
SN74AHCT1G125DCKR_SC70-5 For CostDown @ C38
3
10P_0402_50V8-J
2
+3VS +CRT_VCC
1
2
G
R39 R40
4.7K_0402_5% 4.7K_0402_5%
From PCH
2
2
PCH_CRT_DDC_DAT R41 1 2 0_0402_5% DDC_DAT_R 1 6 CRT_DDC_DAT_CON
<14> PCH_CRT_DDC_DAT
D
S
Q7A
5
G
2N7002KDWH_SOT363-6
SB00000YR00
PCH_CRT_DDC_CLK R42 1 2 0_0402_5% DDC_CLK_R 4 3 CRT_DDC_CLK_CON

<14> PCH_CRT_DDC_CLK
D
S
1 1
Q7B
2N7002KDWH_SOT363-6 @ C39 @ C40
SB00000YR00 100P_0402_50V8-J 100P_0402_50V8-J
A 2 2 A
5
Dr-Bios.com 4
3
Date:
Deciphered Date

Custom

2
2014/12/05
Title
CRT CONN.
!"#$%&'()*+*
1
Sheet 35 of 57
Rev
1.0
5 4 3 2 1
LCDVDD Circuit CMOS Camera
+3VS +LCDVDD_CON
U5
5 1 +LCDVDD_CON Q8 +3VS_CMOS
IN2 OUT AO3413_SOT23-3
1 2 1 W=40 mils W=40mils
GND
D
+3VS 3 1
D C41 4 3 LCD_ENVDD C42 D
1U_0402_6.3V6-K IN1 EN 4.7U_0603_6.3V6-K
2 2 1 1 1 1
G5243AT11U_SOT23-5
G
2
SA00005XJ00 @ C43 @ C44 C45 @ C46
.1U_0402_16V4-Z .01U_0402_16V7-K .1U_0402_16V4-Z 10U_0603_6.3V6-M
2 2 2 2
R44
1 2
<19> CMOS_ON#
100K_0402_5%
1
From PCH R45 1 2 0_0402_5% LCD_ENVDD
<14> PCH_ENVDD
C47
.1U_0402_16V4-Z
1
2
R46
100K_0402_5%
2
C CMOS USB Port10 C
<18> USB20_N13 USB20_N13 R47 1 @ 2 0_0402_5% USB20_N13_CMOS
1 2
1 2
L10 WCM-2012-900T_4P
4 3 SM070003100 JLCD1 ME@
4 3 1
+LEDVDD W= 80 mil 1
<18> USB20_P13 USB20_P13 R48 1 @ 2 0_0402_5% USB20_P13_CMOS 2
R49 1 2 100K_0402_5% 3 2
4 3
W= 40 mil 4
+3VS R158 1 2 0_0402_5% 5
6 5
+3VS_CMOS W= 20 mil 6
+LCDVDD_CON W= 60 mil 7
8 7
+3VALW_LOGO 9 8
LOGO_LED# 10 9
11 10
USB20_N13_CMOS 12 11
USB20_P13_CMOS 13 12
14 13
B+ DMIC_DATA 15 14
<46> DMIC_DATA 15
2A 80 mil 2A 80 mil DMIC_CLK 16
<46> DMIC_CLK 16
R50 1 2 0_0805_5% +LEDVDD 17
CPU_EDP_AUX# C48 1 2 0.1U_0402_25V7-K CPU_EDP_AUX#_CON 18 17
1 <8> CPU_EDP_AUX# 18
CPU_EDP_AUX C49 1 2 0.1U_0402_25V7-K CPU_EDP_AUX_CON 19
<8> CPU_EDP_AUX 19
C50 20
4.7U_0805_25V6-K CPU_EDP_TX0+ C51 1 2 0.1U_0402_25V7-K CPU_EDP_TX0+_CON 21 20
2 <8> CPU_EDP_TX0+ 21
CPU_EDP_TX0- C52 1 2 0.1U_0402_25V7-K CPU_EDP_TX0-_CON 22
B <8> CPU_EDP_TX0- 22 B
23
CPU_EDP_TX1+ C53 1 2 0.1U_0402_25V7-K CPU_EDP_TX1+_CON 24 23
+3VALW <8> CPU_EDP_TX1+ 24
CPU_EDP_TX1- C54 1 2 0.1U_0402_25V7-K CPU_EDP_TX1-_CON 25
<8> CPU_EDP_TX1- 25
26
R51 1 2 4.99K_0402_1% +3VALW_LOGO CPU_EDP_HPD 27 26
<8> CPU_EDP_HPD 27
28 31
PCH_EDP_PWM 29 28 G1 32
<14> PCH_EDP_PWM 29 G2
<48> BKOFF# BKOFF# 30
LOGO_LED# 30
LOGO_LED# <41>
I-PEX_20374-030E-31
1
1
D
LOGO_LED 2 Q9 R53
<48> LOGO_LED
G 2N7002KW_SOT323-3 100K_0402_5%
S
3
2
ESD request EMI
+3VALW_LOGO +LEDVDD +3VALW_LOGO
A A
LOGO_LED#
Dr-Bios.com
1 1 1 1
3
D6 C174 C175 C176 C177

PESD5V0U2BT_SOT23-3 47P_0402_50V8-J 2200P_0402_50V7-K 47P_0402_50V8-J 2200P_0402_50V7-K
2 2 2 2
Issued Date 2012/12/05 Deciphered Date 2014/12/05 LCD/CMOS CONN.

1
Location : -4495,-1075 (BOT) Location : -4833,-1502 (BOT) Size Document Number
Rev
Custom 1.0
!##$%&'()*"*
5 4 3 2 1
A B C D E
+5VALW +USB_VCCA
W=80mils W=80mils
U6 For EMI
1 8 C55 1 @ 2 1000P_0402_50V7-K
2 GND Vout1 7
3 VIN1 Vout2 6
USB_ON# 4 VIN2 Vout3 5 USB_OC0#
1 <48> USB_ON# EN FLG USB_OC0# <18> 1
1 1
G547I2P81U_MSOP8
C56 @ C57
0.1U_0402_16V7-K Low Active 2.5A 1000P_0402_50V7-K
2 2
USB30 Front
L11 L12 L13 D9 D10

USB20_P0 2 1 USB20_P0_C USB3TXDP2 3 4 USB3_TX2_C_P USB30_RX_P2 3 4 USB3_RX2_C_P USB20_P0_C 1 6 USB20_N0_C USB3_TX2_C_P 1 1 10 9 USB3_TX2_C_P
2 1 3 4 3 4 V_I/O1 V_I/O4
2 5 USB3_TX2_C_N 2 2 9 8 USB3_TX2_C_N
USB20_N0 3 4 USB20_N0_C USB3TXDN2 2 1 USB3_TX2_C_N USB30_RX_N2 2 1 USB3_RX2_C_N Ground VBUS +USB_VCCA
3 4 2 1 2 1 USB3_RX2_C_P 4 4
3
V_I/O2 V_I/O3
4 7 7 USB3_RX2_C_P
WCM-2012-900T_4P WCM-2012HS-900T_4P WCM-2012HS-900T_4P
SM070003100 SM070003100 SM070003100 IP4223CZ6_SO6-6 USB3_RX2_C_N 5 5 6 6 USB3_RX2_C_N
3 3
AZ1045-04F_DFN2510P10E-10-9
2 +USB_VCCA +USB_VCCA 2
JUSB3 ME@
USB30_TX_P2 C58 1 2 0.1U_0402_10V6-K USB3TXDP2 R54 1 @ 2 0_0402_5% USB3_TX2_C_P 9 1
<18> USB30_TX_P2 StdA_SSTX+
1 1 1
USB30_TX_N2 C59 1 2 0.1U_0402_10V6-K USB3TXDN2 R55 1 @ 2 0_0402_5% USB3_TX2_C_N 8 VBUS +
<18> USB30_TX_N2 StdA_SSTX-
USB20_P0 R56 1 @ 2 0_0402_5% USB20_P0_C 3 C60 C61 C62
<18> USB20_P0 D+
7 150U_B2_6.3VM_R35M 470P_0402_50V7K 0.1U_0402_16V4Z
USB20_N0 R57 1 @ 2 0_0402_5% USB20_N0_C 2 GND_DRAIN 10 2 2 2
<18> USB20_N0 D- GND_1
USB30_RX_P2 R58 1 @ 2 0_0402_5% USB3_RX2_C_P 6 11 For ESD, Close to JUSB1
<18> USB30_RX_P2 StdA_SSRX+ GND_2
4 12
USB30_RX_N2 R59 1 @ 2 0_0402_5% USB3_RX2_C_N 5 GND_5 GND_3 13
<18> USB30_RX_N2 StdA_SSRX- GND_4
TAITW_PUBAU1-09FNLSCNN4H0
USB30 Back
L14 L15 L16 D11 D12

3 USB20_P1 2 1 USB20_P1_C USB3TXDP5 3 4 USB3_TX5_C_P USB30_RX_P5 3 4 USB3_RX5_C_P USB20_P1_C 1 6 USB20_N1_C USB3_TX5_C_P 1 1 10 9 USB3_TX5_C_P 3
2 1 3 4 3 4 V_I/O1 V_I/O4
2 5 USB3_TX5_C_N 2 2 9 8 USB3_TX5_C_N
USB20_N1 3 4 USB20_N1_C USB3TXDN5 2 1 USB3_TX5_C_N USB30_RX_N5 2 1 USB3_RX5_C_N Ground VBUS +USB_VCCA
3 4 2 1 2 1 USB3_RX5_C_P 4 4
3
V_I/O2 V_I/O3
4 7 7 USB3_RX5_C_P
WCM-2012-900T_4P WCM-2012HS-900T_4P WCM-2012HS-900T_4P
SM070003100 SM070003100 SM070003100 IP4223CZ6_SO6-6 USB3_RX5_C_N 5 5 6 6 USB3_RX5_C_N
3 3
AZ1045-04F_DFN2510P10E-10-9
+USB_VCCA +USB_VCCA
JUSB2 ME@
USB30_TX_P5 C63 1 2 0.1U_0402_10V6-K USB3TXDP5 R60 1 @ 2 0_0402_5% USB3_TX5_C_P 9
<18> USB30_TX_P5 StdA_SSTX+
1 1
USB30_TX_N5 C65 1 2 0.1U_0402_10V6-K USB3TXDN5 R62 1 @ 2 0_0402_5% USB3_TX5_C_N 8 VBUS
<18> USB30_TX_N5 StdA_SSTX-
USB20_P1 R61 1 @ 2 0_0402_5% USB20_P1_C 3 C64
<18> USB20_P1 D+
7 0.1U_0402_16V4Z
USB20_N1 R63 1 @ 2 0_0402_5% USB20_N1_C 2 GND_DRAIN 10 2
<18> USB20_N1 D- GND_1
USB30_RX_P5 R64 1 @ 2 0_0402_5% USB3_RX5_C_P 6 11 For ESD, Close to JUSB2
<18> USB30_RX_P5 StdA_SSRX+ GND_2
4 12
USB30_RX_N5 R65 1 @ 2 0_0402_5% USB3_RX5_C_N 5 GND_5 GND_3 13
<18> USB30_RX_N5 StdA_SSRX- GND_4
TAITW_PUBAU1-09FNLSCNN4H0
4 4
A
Dr-Bios.com B
C D
Date:
Title

Custom
USB30 PORT CONN.

!##$%&'()*"*
E
Sheet 37 of 57
Rev
1.0
5 4 3 2 1
SATA HDD CONN.
+5VS
D D
1 1 1 1 1 PJ1 @
1 2
+5VS 1 2 +5VS_HDD
C66 C67 C68 C69 C70
10U_0805_10V6-K 10U_0805_10V6-K 1U_0603_10V6-K 0.1U_0402_25V7-K 1000P_0402_50V7-K JUMP_43X79
2 2 2 2 2
JHDD1 ME@
1
SATA_PTX_DRX_P0 C138 1 2 .01U_0402_16V7-K SATA_PTX_C_DRX_P0 2 GND1
<13> SATA_PTX_DRX_P0 A+
<13> SATA_PTX_DRX_N0 SATA_PTX_DRX_N0 C147 1 2 .01U_0402_16V7-K SATA_PTX_C_DRX_N0 3
4 A-
SATA_PRX_DTX_N0 C71 1 2 .01U_0402_16V7-K SATA_PRX_C_DTX_N0 5 GND2
<13> SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 C72 1 2 .01U_0402_16V7-K SATA_PRX_C_DTX_P0 6 B-
<13> SATA_PRX_DTX_P0 7 B+
GND3
8
+3VS V33_1
9
10 V33_2
11 V33_3
HDD_DETECT# 12 GND4
<48> HDD_DETECT# 13 GND5
14 GND6
+5VS_HDD V5_1
15
16 V5_2
17 V5_3
18 GND7
Pin18 connect to GND for SATA Gen3 19 Reserved 23
C 20 GND8 GND9 24 C
21 V12_1 GND10
22 V12_2
V12_3
SANTA_198003-1
SATA ODD CONN & ODD Power Control +5VS TO +5VS_ODD
R68 1 @ 2 0_0805_5%
JODD2 ME@
SATA_PTX_DRX_P2 C164 1 2 .01U_0402_16V7-K SATA_PTX_C_DRX_P2 1 +5VS +5VS_ODD
<13> SATA_PTX_DRX_P2 1
<13> SATA_PTX_DRX_N2 SATA_PTX_DRX_N2 C165 1 2 .01U_0402_16V7-K SATA_PTX_C_DRX_N2 2 80 mils U11 80 mils
3 2 5 1 +5VS_ODD
B SATA_PRX_DTX_N2 C76 1 2 .01U_0402_16V7-K SATA_PRX_C_DTX_N2 4 3 IN2 OUT B
<13> SATA_PRX_DTX_N2 SATA_PRX_DTX_P2 C78 1 2 .01U_0402_16V7-K SATA_PRX_C_DTX_P2 5 4 2
<13> SATA_PRX_DTX_P2 5 1 GND 1
6 From PCH
ODD_DETECT#_DP 7 6 C73 4 3 ODD_EN C74
<19> ODD_DETECT#_DP 7 IN1 EN ODD_EN <19>
<14> ODD_DETECT#_DP_R ODD_DETECT#_DP_R R93 1 2 0_0402_5% 8 1U_0402_6.3V6-K 4.7U_0603_6.3V6-K
+5VS_ODD 8 2 2
9 G5243AT11U_SOT23-5
9
1
To PCH <14> PCH_ODD_DA# R69 1 2 0_0402_5% ODD_DA# 10 SA00005XJ00
11 10
1 R70 1 @ 2 0_0402_5% 12 GND1 R66
T2 GND2 100K_0402_5%
ACES_88514-104N
2
Only for 15"
A A
Dr-Bios.com
+5VS_ODD
1 Security Classification LC Future Center Secret Data Title

@ C185 SATA HDD/ODD CONN.
47P_0402_50V8-J
2
Rev
Custom 1.0
RF DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
!"#$%&'()*+*
5 4 3 2 1
2 1
Mini-Express Card(WLAN/WiMAX)
+3V_WLAN
+3VALW R27 1 @ 2 0_0805_5% +3V_WLAN

1
+3VS R28 1 @ 2 0_0805_5%
+3VALW R124 1 2 10K_0402_5% C80
10U_0805_10V6-K
R125 1 @ 2 10K_0402_5% 2
+3V_WLAN
+3V_WLAN
To PCH (X) <15> WLAN_WAKE#
JMINI2 ME@
R126 1 2 0_0402_5% WLAN_WAKE# 1 2 +1.5VS
BT_CTRL R74 1 2 0_0402_5% BT_CTRL_R
To EC <48> WLAN_WAKE#_EC
3 1 2 4
B BT_CTRL_R 5 3 4 6 +1.5VS B
CLKREQ_WLAN# 7 5 6 8 LPC_FRAME#_R
<16> CLKREQ_WLAN# 7 8 1
R76 1 2 1K_0402_5% BT_DISABLE# 9 10 LPC_AD3_R
11 9 10 12 LPC_AD2_R C81
<16> CLK_PCIE_WLAN# 11 12
13 14 LPC_AD1_R 0.1U_0402_25V7-K
<16> CLK_PCIE_WLAN 13 14 2
For isolate Intel Rainbow Peak and 15 16 LPC_AD0_R
PCI_RST#_R 17 15 16 18
Compal debug card. R80 1 2 1K_0402_5% CLK_PCI_DB_R 19 17 18 20 BTRF_OFF#
<19> BT_DET# 19 20 BTRF_OFF# <48>
21 22 PLT_RST#
21 22 PLT_RST# <14,17,41,42,44,48>
PCIE_PRX_DTX_N5 23 24
<18> PCIE_PRX_DTX_N5 23 24
PCIE_PRX_DTX_P5 25 26
<18> PCIE_PRX_DTX_P5 25 26
27 28
29 27 28 30 PM_SMBCLK_R R77 1 @ 2 0_0402_5%
For EMI PCIE_PTX_C_DRX_N5 31 29 30 32 PM_SMBDATA_R R78 1 @ 2 0_0402_5%
PM_SMBCLK <11,12,17,43>
R79 <18> PCIE_PTX_C_DRX_N5 31 32 PM_SMBDATA <11,12,17,43>
CLK_PCI_DB_R 1 @ 2 PCIE_PTX_C_DRX_P5 33 34
<18> PCIE_PTX_C_DRX_P5 33 34
1 35 36 USB20_N10
10_0402_5% 35 36 USB20_N10 <18>
37 38 USB20_P10
37 38 USB20_P10 <18>
@ C83 39 40
10P_0402_50V8-J +3V_WLAN 41 39 40 42
2 +3V_WLAN 41 42
43 44
45 43 44 46
47 45 46 48
R81 1 2 100_0402_1% 49 47 48 50
<48> EC_TX 49 50
R107 1 2 100_0402_1% BT_DISABLE# 51 52
<48> EC_RX 51 52
53 54
GND1 GND2
1
BELLW_80003-3041
R82
100K_0402_5%
R83 For EC to detect
2
<19> PCH_BT_DISABLE# 1 2 BT_CTRL
debug card insert.
0_0402_5%
6
Q12A D @ D Q12B @
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
<19> PCH_BT_ON# 2 5
G G SUSP <55,60,63>
SB00000YR00 S S SB00000YR00
WLAN&BT Combo module circuits
1
+1.5VS
BT on module BT on module
1 Enable Disable
@ C186
2
47P_0402_50V8-J * PCH_BT_DISABLE# H L
RF PCH_BT_ON# L H
Load Switch
+3VALW To +3V_WLAN 1. softstart (RC) will check on EVT PCB
2. if AOAC enable +3V_WLAN always ON
+3VALW To +3V_WWAN if AOAC disable +3V_WLAN is same as +3VS
A A
+3VALW VIN 5V and 3.3V (VBIAS=5V), IMAX(per channel)=6A, Rds=18mohm +3V_WLAN
U10 PJ10 @
1 14 +3V_WLAN_LS 1 2
2 VIN1_1 VOUT1_2 13 1 2
VIN1_2 VOUT1_1 JUMP_43X79
1 1
AOAC_ON 3 12 C84 1 2 1000P_0402_25V7-K
<48> AOAC_ON ON1 CT1
@ C150 @ C152
1U_0402_6.3V6-K +5VALW 4 11 0.1U_0402_10V7-K Reserve for SW mini-pcie debug card.
2 VBIAS GND 2
WWAN_ON_R 5 10 C85 1 2 2200P_0402_25V7-K Series resistors closed to KBC side.
+3VALW ON2 CT2 +3V_WWAN
6 9 PJ11 @
7 VIN2_1 VOUT2_2 8 +3V_WWAN_LS 1 2 LPC_FRAME#_R R86 1 @ 2 0_0402_5% LPC_FRAME#
VIN2_2 VOUT2_1 1 2 LPC_FRAME# <17,44,48>
LPC_AD3_R R87 1 @ 2 0_0402_5% LPC_AD3
LPC_AD3 <17,44,48>
1 15 JUMP_43X79 1 LPC_AD2_R R88 1 @ 2 0_0402_5% LPC_AD2
GPAD LPC_AD2 <17,44,48>
LPC_AD1_R R89 1 @ 2 0_0402_5% LPC_AD1
LPC_AD1 <17,44,48>
@ C151 TPS22966DPUR_WSON14_2X3 @ C153 LPC_AD0_R R91 1 @ 2 0_0402_5% LPC_AD0
LPC_AD0 <17,44,48>
1U_0402_6.3V6-K 0.1U_0402_10V7-K PCI_RST#_R R92 1 @ 2 0_0402_5% PLT_RST#
Dr-Bios.com
2 2 CLK_PCI_DB_R R106 1 @ 2 0_0402_5% CLK_PCI_DB
+3V_WLAN, C165 --> 1.5ms CLK_PCI_DB <16>
+3V_WWAN, C163 --> 2.5ms
SUSP# R29 1 @ 2 0_0402_5%
<48,55,61,62> SUSP#
WWAN_ON R30 1 2 0_0402_5% WWAN_ON_R
Issued Date 2012/12/05 Deciphered Date 2014/12/05 PCIe-WLAN SLOT
<19> WWAN_ON
Rev
Custom 1.0
!##$%&'()*"*
2 1
5 4 3 2 1
NGFF(SSD) & SIM CARD CONN.
D D
+3V_WWAN
PJ8 @
+3VALW 1 2 +3V_WWAN SSD Active:4.5W(1.5A)
1 2
JUMP_43X118 2 1 1 1
PJ9 @ C86 C87 C89 @ C88
+3VALW +3VS 1 2 .01U_0402_16V7-K 0.1U_0402_25V7-K 10U_0805_10V6-K 10U_0805_10V6-K
1 2 1 2 2 2
JUMP_43X118
1
R145
10K_0402_5%
+3V_WWAN
2
JMINI1 ME@
<19> PCH_MSATA_DET# PCH_MSATA_DET# R94 1 2 0_0402_5% MSATA_DET# 1 2
1 R95 1 @ 2 0_0402_5% 3 CONFIG_3 3.3VAUX1 4
T8 GND1 3.3VAUX2
5 6 R97 1 3G@ 2 10K_0402_5% +3V_WWAN
USB20_P11 7 GND2 FULL_CARD_POWER_OFF# 8 3G_OFF#
<18> USB20_P11 USB_D+ W_DISABLE# 3G_OFF# <19>
USB20_N11 9 10 +3VS
<18> USB20_N11 USBD- LED#
11 12 D13 @
GND3 NC
13 NC 14 40mil 3
NC
15 NC NC 16 +UIM_PWR 1
17 NC NC 18 2
<18> PCH_3G_DET# PCH_3G_DET# R98 1 2 0_0402_5% 19 NC 20 1 1
EC_3G_DET# R96 1 @ 2 0_0402_5% 3G_DET# 21 GPIO_5 22 DAN217T146_SC59-3
<48> EC_3G_DET# CONFIG_0 GPIO_6
23 24 3G@ C91 3G@ C92
R99 1 3G@ 2 10K_0402_5% 25 WAKE_ON_WWAN# GPIO_7 26 GPS_OFF# 0.1U_0402_25V7-K 4.7U_0603_6.3V6K
DPR W_DISABLE2# GPS_OFF# <19> 2 2
27 28
C 29 GND4 UIM-RFU 30 UIM_RST C
31 USB3.0-TX-(Device) UIM-RESET 32 UIM_CLK
33 USB3.0-TX+(Device) UIM-CLK 34 UIM_DATA R100 1 3G@ 2 20K_0402_5%
35 GND5 UIM-DATA 36 +UIM_PWR
37 USB3.0-RX-(Device) UIM-PWR 38 SATA1_DEVSLP#_R R52 1 @ 2 0_0402_5% SATA1_DEVSLP#
USB3.0-RX+(Device) DEVSLP SATA1_DEVSLP# <14>
39 40
SATA_PRX_DTX_P1 C90 1 2 .01U_0402_16V7-K SATA_PRX_C_DTX_P1 41 GND6 GPIO_0 42
<13> SATA_PRX_DTX_P1 SATA_PRX_DTX_N1 C93 1 2 .01U_0402_16V7-K SATA_PRX_C_DTX_N1 43 SATA-B+/HRX+ GPIO_1 44
<13> SATA_PRX_DTX_N1 45 SATA-B-/HRX- GPIO_2 46
SATA_PTX_DRX_N1 C149 1 2 .01U_0402_16V7-K SATA_PTX_C_DRX_N1 47 GND7 GPIO_3 48
<13> SATA_PTX_DRX_N1 SATA-A-/HTX- GPIO_4 +1.8VS
<13> SATA_PTX_DRX_P1 SATA_PTX_DRX_P1 C163 1 2 .01U_0402_16V7-K SATA_PTX_C_DRX_P1 49 50
51 SATA-A+/HTX+ RESERVED3 52
53 GND8 RESERVED4 54
RESERVED1 RESERVED5
1
55 56
57 RESERVED2 RESERVED6 58
59 GND9 RESERVED7 60 3G@ R101
61 ANTCTRL0 COEX3 62 10K_0402_5%
63 ANTCTRL1 COEX2 64
2
65 ANTCTRL2 COEX1 66 UIM_DET
67 ANTCTRL3 SIM_DETECT 68
RESET# SUSCLK
1
R102 1 3G@ 2 10K_0402_5% 69 70
71 CONFIG_1 3.3VAUX3 72
73 GND10 3.3VAUX4 74 3G@ R103
R104 1 3G@ 2 10K_0402_5% 75 GND11 3.3VAUX5 10K_0402_5%
CONFIG_2
2
76 77
PEG1 PEG2
FOX_AS0BC21-S30BB-7H
+UIM_VPP R105 1 @ 2 10K_0402_5% +UIM_PWR
B B
Only for 15" D14 @
JSIM1 ME@
UIM_DATA 1 4 UIM_CLK UIM_DET 1

I/O1 I/O3 +UIM_PWR 2 CD
3 C1
1. PCH_MSATA_DET# --> +3V_PCH UIM_RST 4 C5
EC_MSATA_DET# --> +3VL 2 5 +UIM_VPP 5 C2
GND VDD +3VS C6
UIM_CLK 6
2. PCH_3G_DET# --> +3VS UIM_DATA 7 C3
C7
EC_3G_DET# --> +3VL 1
+UIM_VPP 3 6 UIM_RST 8
!"#EC$ $%&PCH I/O2 I/O4 3G@ C94 9 GND1
AZC099-04S.R7G_SOT23-6 0.1U_0402_25V7-K GND2
3. EC don't have GPIO pin for DET# pin as below 2
a. PCH_3G_DET# PLAST_CE1S-148-H-N_7P-T
b. PCH_MSATA_DET#
NGFF Detect Desc.

A A
MSATA_DET# 3G_DET#
Dr-Bios.com
No Card 1 1
WWAN CARD 1 0 Security Classification LC Future Center Secret Data Title
Issued Date 2012/12/05 Deciphered Date 2014/12/05 PCIe-WWAN/SIM SLOT

SSD CARD 0 0 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Rev
Custom 1.0
!##$%&'()*"*
5 4 3 2 1
A B C D E F G H
1 1
USB2.0, CR & LOGO Board

JUCR ME@
+5VALW 1
2 1
3 2
4 3
2 5 4 2
+3VALW 5
+3VS 6
7 6
AOU_DET# 8 7
<48> AOU_DET# 8
LOGO_LED# 9
<36> LOGO_LED# 9
USB_OC5# 10
<18> USB_OC5# 10
AOU_EN 11
<48> AOU_EN 11
AOU_CTL1 12
<48> AOU_CTL1 12
AOU_CTL3 13
<48> AOU_CTL3 13
14
USB20_N9 15 14
<18> USB20_N9 15
USB20_P9 16
<18> USB20_P9 16
17
PCIE_PRX_DTX_P3 18 17
<18> PCIE_PRX_DTX_P3 18
PCIE_PRX_DTX_N3 19
<18> PCIE_PRX_DTX_N3 19
20
PCIE_PTX_C_DRX_P3 21 20
<18> PCIE_PTX_C_DRX_P3 21
PCIE_PTX_C_DRX_N3 22
<18> PCIE_PTX_C_DRX_N3 22
23
CLK_PCIE_CR 24 23
<16> CLK_PCIE_CR 24
CLK_PCIE_CR# 25
<16> CLK_PCIE_CR# 25
26
CLKREQ_CR# 27 26
<16> CLKREQ_CR# 27
PLT_RST# 28
<14,17,39,42,44,48> PLT_RST# 28
29
30 GND1
GND2
ACES_88194-2841
3 3
4 4
A B
Dr-Bios.com
C D
E F
Title
PCIe-CR/USB-Charge CONN.
Custom
Date:
G
!##$%&'()*"*
Thursday, July 11, 2013 Sheet
H
41 of 57
Rev
1.0
5 4 3 2 1
LAN (Port4)
USB3.0/2.0 (Port1/3)
DP(DDIC) LAN CONN. (FFC)
JRJ45 ME@
D 1 D
+3VALW 1
2
3 2
+3VS 3
+RTCBATT 4
5 4
+5VALW 5
6
PCIE_PRX_DTX_N4 7 6
<18> PCIE_PRX_DTX_N4 7
PCIE_PRX_DTX_P4 8
<18> PCIE_PRX_DTX_P4 8
9
PCIE_PTX_C_DRX_N4 10 9
<18> PCIE_PTX_C_DRX_N4 10
PCIE_PTX_C_DRX_P4 11
<18> PCIE_PTX_C_DRX_P4 11
12
CLK_PCIE_LAN# 13 12
<16> CLK_PCIE_LAN# 13
CLK_PCIE_LAN 14
<16> CLK_PCIE_LAN 14
CLKREQ_LAN# 15
<16> CLKREQ_LAN# 15
PLT_RST# 16
<14,17,39,41,44,48> PLT_RST# 16
17
LAN_WAKE# 18 17
To PCH <48> LAN_WAKE#
PCH_LAN_25M 19 18
<16> PCH_LAN_25M 19
20
21 20
PCI_PME# 0_0402_5% 2 @ 1 R108 22 GND1
<14> PCI_PME# GND2
ACES_88194-2041
C C
DCIN CONN. (Coaxial)

JDCIN2 ME@
USB30_TX_P1 1
<18> USB30_TX_P1 1
USB30_TX_N1 2
+5VS <18> USB30_TX_N1 2
3
USB3.0 Port1 <18> USB30_RX_P1
USB30_RX_P1 4 3
DOCK_HPD R109 1 2 1K_0402_5% DOCK_HPD_CONN USB30_RX_N1 5 4
<18> USB30_RX_N1 5
1 6
CPU_DOCK_TX0+ R110 1 2 0_0402_5% CPU_DOCK_TX0+_CON 7 6
<8> CPU_DOCK_TX0+ 7
1
C95 1 CPU_DOCK_TX0- R111 1 2 0_0402_5% CPU_DOCK_TX0-_CON 8

<8> CPU_DOCK_TX0- 8
5
0.1U_0402_10V7-K CPU_DOCK_TX1+ R113 1 2 0_0402_5% CPU_DOCK_TX1+_CON 9

2 <8> CPU_DOCK_TX1+ 9
C96 R112 CPU_DOCK_TX1- R114 1 2 0_0402_5% CPU_DOCK_TX1-_CON 10
OE#
P
<8> CPU_DOCK_TX1- 10
2 4 PCH_DOCK_HPD 0.1U_0402_10V7-K 100K_0402_5% 11
A Y PCH_DOCK_HPD <14> 2 11
USB20_P3 12
USB2.0 Port3 <18> USB20_P3
2
12
G
U7 USB20_N3 13
<18> USB20_N3 13
74AHCT1G125GW_SOT353-5 14
3
B C79 1 2 0.1U_0402_10V7-K PCH_DOCK_AUX_CONN 15 14 B

<14> PCH_DOCK_AUX 15
C148 1 2 0.1U_0402_10V7-K PCH_DOCK_AUX#_CONN 16
<14> PCH_DOCK_AUX# 16
DOCK_DETECT# R43 1 2 0_0402_5% DOCK_DETECT#_CONN 17
<19> DOCK_DETECT# 17
DOCK_CONSUMP 18
<58> DOCK_CONSUMP 18
DOCK_HPD_CONN 19
ON/OFFBTN# 20 19
<45,48> ON/OFFBTN# 20
21
+3VS 22 G1
R115 1 2 2.2K_0402_5% PCH_DOCK_HPD 23 G2
24 G3
G4
ACES_50406-02071-001
+3VS
PCH_DOCK_AUX#_CONN R16 1 2 100K_0402_5%
PCH_DOCK_AUX_CONN R14 1 2 100K_0402_5%
A A
5
Dr-Bios.com 4
3 2
Date:
Title
PCIe-RJ45/RTC/Docking CONN.
Custom

!##$%&'()*"*
1
Sheet 42 of 57
Rev
1.0
5 4 3 2 1
Click Pad Track point

D D
+5VS
JCP1 ME@ +5VS JTP1 ME@
1 R118 TP_DATA2 1
PM_SMBCLK 2 1 1 2 TP_RESET 2 1
<11,12,17,39> PM_SMBCLK 2 2
3 3
TP_DATA2 4 3 4.7K_0402_5% 4 3
TP_CLK2 5 4 5 4
PM_SMBDATA 6 5 +5VS_TRACKP TP_CLK2 6 5
<11,12,17,39> PM_SMBDATA 6 6
7 7
CP_RESET# 8 7 8 7
<48> CP_RESET# 8 8
TP_CLK 9 1 9
<48> TP_CLK 9 9
TP_DATA 10 10
<48> TP_DATA 10 10
TP4RST 11 13 C97 11 13
<48> TP4RST 11 GND1 11 GND1
BYPASS_PAD 12 14 0.1U_0402_16V4Z 12 14
12 GND2 2 12 GND2
1 1
2
ACES_51522-01201-001
R123 C98 @ @ C99 JAE_FL10S012HA1
4.7K_0402_5% 100P_0402_50V8J 100P_0402_50V8J
2 2
Only for 15"
1
C R5 1 2 0_0603_5% C
+5VS
+5VS +5VS_TRACKP
80 mils U12 @ 80 mils
5 1 +5VS_TRACKP
R116 1 2 4.7K_0402_5% TP_CLK2 TP4RST R75 1 2 0_0402_5% TP_RESET IN2 OUT
1 2 1
R117 1 2 4.7K_0402_5% TP_DATA2 GND
R71 1 @ 2 0_0402_5% BYPASS_PAD C75 4 3 TRACKP_ON
From PCH C77
IN1 EN TRACKP_ON <19>
1U_0402_6.3V6-K 4.7U_0603_6.3V6-K
2 G5243AT11U_SOT23-5 2
1
SA00005XJ00
R119 1 2 100K_0402_5% CP_RESET# TP_CLK TP_DATA2
TP_DATA TP_CLK2 @ R67
100K_0402_5%
3
2
D15 D16
PESD5V0U2BT_SOT23-3 PESD5V0U2BT_SOT23-3
1
B
FAN CONN. B
R120 1 2 0_0603_5% +VCC_FAN1

40mil
+5VS
1
@ C100
1U_0402_6.3V6K
2
JFAN1 ME@
1
<48> EC_FAN_PWM 1
2
3 2
<48> EC_FAN_SPEED 3
4 6
5 4 G1 7
<48> FAN_ID 5 G2
1 ACES_85205-05001
C101
1000P_0402_50V7K
@
2
A A
5
Dr-Bios.com 4
Deciphered Date
3 2
2014/12/05
Custom
Date:
Title
CP/TP/FAN CONN.

!"#$%&'()*+*
1
Sheet 43 of 57
Rev
1.0
5 4 3 2 1
D D
TPM IC
+3VS
UTPM1
1 24
2 NC_1 VPS_1 10
NC_2 VPS_2 1 1
3 R32 1 TPM@ 2 10K_0402_5% TPM@ TPM@
7 NC_3 28 C102 C103
PP LPCPD# 27 SERIRQ .1U_0402_16V4-Z 10U_0603_6.3V6-M
SERIRQ SERIRQ <17,48> 2 2
6 26 LPC_AD0
NC_4 LAD0 LPC_AD0 <17,39,48>
9 23 LPC_AD1
VNC_1 LAD1 LPC_AD1 <17,39,48>
22 LPC_FRAME#
LFRAME# LPC_FRAME# <17,39,48>
4 20 LPC_AD2
GND_1 LAD2 LPC_AD2 <17,39,48>
11 17 LPC_AD3
GND_2 LAD3 LPC_AD3 <17,39,48>
18
GND_3 25
5 NC_11 21 CLK_PCI_TPM
NC_5 LCLK CLK_PCI_TPM <16>
8 19
12 VNC_2 NC_10 15 PM_CLKRUN#
NC_6 NC_9 PM_CLKRUN# <15>
13
14 NC_7 16 PLT_RST#
NC_8 LRESET# PLT_RST# <14,17,39,41,42,48>
ST33ZP24AR28PVSP_TSSOP28
SA00005C010
TPM@
C C
FingerPrint CONN. Touch Panel CONN.

+3VS
JTOUCH ME@
+3VS 1
JFPB1 ME@ PLT_RST# R26 1 @ 2 0_0402_5% 2 1
1 3 2
USB20_P12 2 1 SMB_DATA_TPANEL 4 3
<18> USB20_P12 2 <17> SMB_DATA_TPANEL 4
USB20_N12 3 SMB_CLK_TPANEL 5
<18> USB20_N12 3 <17> SMB_CLK_TPANEL 5
4 6
4 6
3
1 5 USB20_N4 7
5 <18> USB20_N4 7
6 USB20_P4 8
3
6 <18> USB20_P4 8
D17 C104 <14> TPANEL R6 1 @ 2 0_0402_5% 9
AZC199-02SPR7G_SOT23-3 0.1U_0402_10V6-K 7 10 9
2 GND1 10
1
8
B GND2 11 B
1 1
1
ACES_88514-0060N-071 12 GND1
C146 C105 GND2
0.1U_0402_10V6-K 0.1U_0402_10V6-K ACES_50463-0104A-P01
Only for 15" 2 2
Only for 15"
A A
5
Dr-Bios.com 4
3 2
Date:
Title
TPM/TPanel/FP CONN.

Custom

!"#$%&'()*+*
1
Sheet 44 of 57
Rev
1.0
5 4 3 2 1
PWR BTN/LID SW CONN.
D 1. Power Button/B link to Function/B Conn. 10pin D
2. Lid Switch
ON/OFF switch
+3VL
SW1 @
1 3
1
Power Button 2 4 +3VL
TOP Side
SMT1-05_4P R121 JPWR1 ME@
6
5
100K_0402_5% 1
ON/OFFBTN# 2 1
2
3 2
J3 3
LID_SW# 4
<48> LID_SW# 4
Bottom Side 1 2 ON/OFFBTN#
ON/OFFBTN# <42,48>
5
SHORT PADS 6 GND1
@ GND2
ACES_88514-0401
C C
KeyBoard CONN.(14")
KSI[0..7] KSI[0..7] <48>

KSO[0..17]
KSO[0..17] <48>
JKB1 ME@
KSI1 32 34
KSI0 C108 1 @ 2 100P_0402_50V8J KSO0 C109 1 @ 2 100P_0402_50V8J KSI7 31 32 GND2 33
KSI6 30 31 GND1
KSI1 C110 1 @ 2 100P_0402_50V8J KSO1 C111 1 @ 2 100P_0402_50V8J KSO9 29 30
KSI4 28 29
KSI2 C106 1 @ 2 100P_0402_50V8J KSO2 C112 1 @ 2 100P_0402_50V8J KSI5 27 28
B KSO0 26 27 B
KSI3 24 25
KSO1 22 23
KSO2 20 21
KSO7 18 19
KSO6 16 17
KSO8 C122 1 @ 2 100P_0402_50V8J KSO3 15 16
KSO12 14 15
KSO9 C123 1 @ 2 100P_0402_50V8J KSO13 13 14
Fn_LED# C124 1 @ 2 100P_0402_50V8J KSO14 12 13
KSO10 C125 1 @ 2 100P_0402_50V8J KSO11 11 12
F1_LED# C126 1 @ 2 100P_0402_50V8J KSO10 10 11
KSO11 C127 1 @ 2 100P_0402_50V8J KSO15 9 10
F4_LED# C128 1 @ 2 100P_0402_50V8J R122 1 2 300_0402_5% 8 9
+3VS 8
KSO12 C129 1 @ 2 100P_0402_50V8J Fn_LED# 7
<19> FN_LED# 7
KB_FN C130 1 @ 2 100P_0402_50V8J F1_LED# 6
<19> F1_LED# 6
KSO13 C131 1 @ 2 100P_0402_50V8J F4_LED# 5
<19> F4_LED# 5
KB_FN 4
<48> KB_FN 4
KSO14 C132 1 @ 2 100P_0402_50V8J 3
KSO16 2 3
CONN PIN define need double check KSO15 C133 1 @ 2 100P_0402_50V8J KSO17 1 2
1
KSO16 C134 1 @ 2 100P_0402_50V8J JAE_FL10S032HA1
KSO17 C135 1 @ 2 100P_0402_50V8J
A A
5
Dr-Bios.com
4
3 2
Date:
Title
KB/PWR BTN CONN.

Custom
!"#$%&'()*+*
1
Sheet 45 of 57
Rev
1.0
A B C D E F G H
+3VS
+5VS +1.8V_LDO LDO 1V8 +1.65V_LDO VREF 1V65 +3V_LDO LDO 3V3 1
CA1
RA1 0.1U_0402_10V7-K
C3505 close Pin7
1 2 CA2 CA3 CA4 CA5 +5VS_CLASSD
2
CA6
CA7
CA8
CA9
CA10
CA11
0_0805_5%
4.7U_0603_10V6-K
4.7U_0603_10V6-K
0.1U_0402_10V7-K
0.1U_0402_10V7-K
1 1 1 1 2 2 1 1 1 2
@
0.1U_0402_10V7-K
4.7U_0402_6.3V6-M
0.1U_0402_10V7-K
1U_0402_6.3V6-K
0.1U_0402_10V7-K
2.2U_0603_6.3V6-K
1 2 2 2 2 1 1 2 2 2 1 +3VS 1
RA28 1 2 0_0402_5% +3VS_VDDO

X5R CAP X5R CAP X5R CAP 1
CA12
0.1U_0402_10V7-K
2 CA12 close Pin2
Close to Pin13,16
+3VALW
+3V_AVDD_HP RA2 2 1 0_0805_5%
12/3 For PH noise
+3VS
1
RA3 2 @ 1 0_0805_5%
CA13
1U_0402_6.3V6-K
2
C3537 close Pin24
+3VS_DVDD +3VS
RA4 2 1 0_0805_5%
UA1
X5R CAP, Please Close Pin18
2 2
HDA_RST_AUDIO# 9 3 +1.8V_LDO 1
<13> HDA_RST_AUDIO# RESET# FILT_1.8V 7 +3VS_VDDIO
VDD_IO 2 CA14
VDDO_3.3 +3VS_VDDO
HDA_BITCLK_AUDIO 5 18 +3VS_DVDD 1U_0402_6.3V6-K
<13> HDA_BITCLK_AUDIO BIT_CLK DVDD_3.3 2
HDA_SYNC_AUDIO 8 27 +3V_LDO
<13> HDA_SYNC_AUDIO SYNC AVDD_3.3 29 +1.65V_LDO
HDA_SDIN0 RA5 1 2 33_0402_5% HDA_SDIN0_AUDIO 6 VREF_1.65V 28
<13> HDA_SDIN0 SDATA_IN AVDD_5V +5VS_AVDD
HDA_SDOUT_AUDIO 4
<13> HDA_SDOUT_AUDIO SDATA_OUT
<47> PC_BEEP
PC_BEEP 10
PC_BEEP
CX20751-11Z LEFT+
12 SPK_L2+
SPK_L2+ <47>
EC_MUTE# 39 14 SPK_L1- +5VS_AVDD +5VS
<48> EC_MUTE# SPKR_MUTE# LEFT- SPK_L1- <47>
JSENSE 38 17 SPK_R2+ RA6 2 1 0_0805_5%
<47> JSENSE JSENSE RIGHT+ SPK_R2+ <47>
37 15 SPK_R1-
GPIO1/PORTC_R_MIC RIGHT- SPK_R1- <47>
36 35 1
DMIC_CLK RA7 1 2 33_0402_5% DMIC_CLK_R 40 MUSIC_REQ/GPIO0/PORTC_L_MIC MICBIASC 34
<36> DMIC_CLK DMIC_CLK/MUSIC_REQ/GPIO0 MICBIASB +MICBIASB
DMIC_DATA 1 CA15
<36> DMIC_DATA DMIC_DAT/GPIO1 33 PORTB_R 1U_0402_6.3V6-K
PORTB_R_LINE PORTB_R <47> 2
32 PORTB_L
PORTB_L_LINE PORTB_L <47>
+5VS_CLASSD CA16 1 2 0.1U_0402_10V7-K 11
CLASS-D_REF 30 EXT_MIC_A
13 PORTD_A_MIC 31 EXT_MIC_B
EXT_MIC_A <47> Apple --> EXT_MIC_A, HGNDB Please Close Pin28
LPWR_5.0 PORTD_B_MIC EXT_MIC_B <47>
W= 80mils 16
RPWR_5.0 25 HGNDA Nokia --> EXT_MIC_B, HGNDA
HGNDA HGNDA <47>
CA17 1 2 1U_0402_6.3V6-K 19 26 HGNDB
FLY_P HGNDB HGNDB <47>
20
FLY_N 24
AVDD_HP +3V_AVDD_HP
+AVEE +AVEE 21
AVEE 23 HP_OUTR +3VS_VDDIO
3 PORTA_R HP_OUTR <47> 3
HP indicate 1 41 22 HP_OUTL +3VS RA25 1 @ 2 0_0402_5%
GND PORTA_L HP_OUTL <47>
CA18 Should be +3V_PCH RA27 1 2 0_0402_5% +3VS_VDDIO
2.2U_0603_6.3V6-K
2 connect to CX20751-11Z_QFN40_5X5 CX20751-21Z 1
GNDA SA00005ZT0J CA42
GND 4.7U_0402_6.3V6-M
2
CA42 close Pin7
EMI, close to UA1 RF, close to RA7

RA26
W= 300mils
HDA_BITCLK_AUDIO_C 1 @ 2 HDA_BITCLK_AUDIO DMIC_CLK CA19 1 @ 2 0.1U_0402_10V7-K
1 1
33_0402_5% CA20 1 @ 2 0.1U_0402_10V7-K
@ CA41 @ CA40
4 22P_0402_50V8-J 47P_0402_50V8-J CA21 1 @ 2 0.1U_0402_10V7-K 4
2 2
Dr-Bios.com
HDA_RST_AUDIO# HDA_SYNC_AUDIO HDA_SDOUT_AUDIO DMIC_DATA
GND GNDA
1
1 1 1 Security Classification LC Future Center Secret Data Title
@ CA43
@ CA37 @ CA38 @ CA39 47P_0402_50V8-J
22P_0402_50V8-J 22P_0402_50V8-J 22P_0402_50V8-J 2 Issued Date 2012/12/05 Deciphered Date 2014/12/05 HDA-CX20751-CX
2 2 2
Rev
Custom 1.0
!##$%&'()*"*
A B C D E F G H
5 4 3 2 1
PC Beep Speaker OUT SPK CONN.

D D
EC Beep SCS00006S00 JSPK2

DA1 2 1 RB751V-40_SOD323-2 SPK_L1- RA8 1 2 0_0603_5% SPK_L1-_CON SPK_R1-_CON 1
<48> BEEP# <46> SPK_L1- 1
SPK_R2+_CON 2
SPK_L2+ RA9 1 2 0_0603_5% SPK_L2+_CON SPK_L1-_CON 3 2
<46> SPK_L2+ 3
CA22 1 @ 2 0.1U_0402_10V7-K SPK_L2+_CON 4
SPK_R1- RA10 1 2 0_0603_5% SPK_R1-_CON 5 4
<46> SPK_R1- GND1
6
CA24 SPK_R2+ RA12 1 2 0_0603_5% SPK_R2+_CON GND2
PCH Beep CA23 1 @ 2 0.1U_0402_10V7-K 1
RA11
2 1 2 PC_BEEP
<46> SPK_R2+
ACES_87302-0401-003
<13> HDA_SPKR PC_BEEP <46>
33_0402_5% ME@
0.1U_0402_10V7-K
DA2 2 1 RB751V-40_SOD323-2
Only for 15"
SCS00006S00 CA25 1 @ 2 1000P_0402_50V7-K SPK_L1-_CON
1
CA26 1 @ 2 1000P_0402_50V7-K SPK_L2+_CON
RA13
10K_0402_5% CA27 1 @ 2 1000P_0402_50V7-K SPK_R1-_CON
2
CA28 1 @ 2 1000P_0402_50V7-K SPK_R2+_CON
C C
Apple --> EXT_MIC_A, HGNDB

EXT. MIC/LINE IN Nokia --> EXT_MIC_B, HGNDA
Audio Jack
+3VS
JAUHP ME@
1
HGNDB 3
<46> HGNDB
HGNDA 6
<46> HGNDA
RA18
EXT_MIC_A RA14 1 2 100_0402_5% CA29 1 2 2.2U_0402_6.3V6-K HGNDB 5.11K_0402_1% HP_OUTL_CON 1
<46> EXT_MIC_A
2
HP_OUTR_CON 2
EXT_MIC_B RA15 1 2 100_0402_5% CA30 1 2 2.2U_0402_6.3V6-K HGNDA JSENSE RA20 2 1 20K_0402_1% JSENSE_CON 4
<46> EXT_MIC_B <46> JSENSE
RA21 2 1 39.2K_0402_1% 5
Changed CA29 & CA30 from 1uF to 2.2uF/X5R
SINGA_2SJ2326-001111
B to meet Port-D(headset-Mic) THD+N <= -65 dB GNDA B
HeadPhone/LINE OUT
RA16 1 2 2.2K_0402_5%
ESD Diode, close to JAUHP
+MICBIASB
DA3 DA4 DA5
<46> HP_OUTL HP_OUTL RA17 1 2 5.1_0402_1% HP_OUTL_CON 2 HGNDB 2 HP_OUTL_CON 2 JSENSE_CON
1 1 1
CA31 3 HGNDA 3 HP_OUTR_CON 3
RA19
<46> PORTB_L PORTB_L 1 2 1 2
PESD5V0U2BT_SOT23-3 PESD5V0U2BT_SOT23-3 PESD5V0U2BT_SOT23-3
100_0402_5%
4.7U_0402_6.3V6-M
RA22 1 2 2.2K_0402_5% +MICBIASB EMI, close to JAUHP
<46> HP_OUTR HP_OUTR RA23 1 2 5.1_0402_1% HP_OUTR_CON HGNDB HGNDA HP_OUTL_CON HP_OUTR_CON
CA32 1 1 1 1
RA24
<46> PORTB_R PORTB_R 1 2 1 2
CA33 CA34 CA35 CA36
100_0402_5% 220P_0402_50V8-J 220P_0402_50V8-J 220P_0402_50V8-J 220P_0402_50V8-J
4.7U_0402_6.3V6-M
2 2 2 2
CA31, CA32 change to 4.7U for Quality requirement
A A
5
Dr-Bios.com 4
Deciphered Date
3 2
2014/12/05

Custom
Date:
Title

HDA-HP/EXT MIC/SPK CONN.
!"#$%&'()*+*
1
Sheet 47 of 57
Rev
1.0
5 4 3 2 1
+3VL +3VL +3VL_AVCC

All capacitors close to EC LE1
1 2 +3VL_AVCC
+3VL CE3 CE4 CE5 CE6 CE7 CE8 BLM18PG181SN1D_0603
0.1U_0402_25V7-K
0.1U_0402_25V7-K
0.1U_0402_25V7-K
0.1U_0402_25V7-K
0.1U_0402_25V7-K
0.1U_0402_25V7-K
1 1
1 1 1 1 1 1
CE9 CE10
Close to EC +3VS +3VL_AVCC 0.1U_0402_25V7-K 1000P_0402_50V7-K
CE1 2 2
1 2 +VCOREVCC 2 2 2 2 2 2 LE2
D D
EC_AGND 1 2
0.1U_0402_25V7-K BLM18PG181SN1D_0603
114
121
127
12
11
26
50
92
74
minimum trace width 12 mil
3
UE1
VBAT
VCORE
VSTBY1
VSTBY2
VSTBY3
VSTBY4
VSTBY5
VCC
VSTBY(PLL)
AVCC
KBRST# 4 24 LOGO_LED
<19> KBRST# KBRST#/GPB6 PWM0/GPA0 LOGO_LED <36>
SERIRQ 5 25 AOU_DET# AOU_DET# <41> +5VALW
<17,44> SERIRQ SERIRQ/GPM6 PWM1/GPA1
LPC_FRAME# 6 28 CP_RESET#
<17,39,44> LPC_FRAME# LFRAME#/GPM5 PWM2/GPA2 CP_RESET# <43>
LPC_AD3 7 29 LAN_WAKE# LAN_WAKE# <42> USB_ON# RE12 1 2 10K_0402_5%
<17,39,44> LPC_AD3 LAD3/GPM3 PWM3/GPA3
LPC_AD2 8 PWM 30 GS_SELFTEST
+3VL <17,39,44> LPC_AD2 LAD2/GPM2 PWM4/GPA4 GS_SELFTEST <33>
LPC_AD1 9 31 EC_FAN_PWM
<17,39,44> LPC_AD1 LAD1/GPM1 PWM5/GPA5 EC_FAN_PWM <43>
LPC_AD0 10 32 BEEP#
<17,39,44> LPC_AD0 LAD0/GPM0 PWM6/SSCK/GPA6 BEEP# <47> +5VS
CLK_PCI_EC 13 LPC 34 VDDQ_PGOOD VDDQ_PGOOD <60>
RE4 <16> CLK_PCI_EC LPCCLK/GPM4 PWM7/RIG1#/GPA7
1 2 WRST# WRST# 14 120 BATT_LEN#
WRST# TMRI0/GPC4 BATT_LEN# <57>
1 HDD_DETECT# 15 124 SUSP# TP_CLK RE2 1 2 4.7K_0402_5%
100K_0402_5% <38> HDD_DETECT# ECSMI#/GPD4 TMRI1/GPC6 SUSP# <39,55,61,62>
EC_RX 16 TP_DATA RE3 1 2 4.7K_0402_5%
<39> EC_RX PWUREQ#/BBO/SMCLK2ALT/GPC7
CE12 EC_TX 17 66 GS_VOUTX GS_VOUTX <33>
<39> EC_TX LPCPD#/GPE6 ADC0/GPI0
1U_0603_10V6-K PLT_RST# 22 67 GS_VOUTY GS_VOUTY <33>
2 <14,17,39,41,42,44> PLT_RST# LPCRST#/GPD2 ADC1/GPI1
EC_SCI# 23 68 BATT_TEMP BATT_TEMP <56,57> +3VS
<19> EC_SCI# ECSCI#/GPD3 ADC2/GPI2
GATEA20 126 ADC 69 IMVP_IMON IMVP_IMON <64>
<19> GATEA20 GA20/GPB5 ADC3/GPI3 70 EC_ON EC_FAN_PWM RE5 1 @ 2 10K_0402_5%
IT8586E/AX ADC4/GPI4
ADC5/DCD1#/GPI5
71
72
ADP_I
FAN_ID
EC_ON
ADP_I
FAN_ID
<59>
<57,58>
<43> EC_FAN_SPEED RE6 1 2 10K_0402_5%
ADC6/DSR1#/GPI6
+3VL <45> KSI[0..7]

KSI[0..7] KSI0
KSI1
58
59 KSI0/STB#
LQFP-128L ADC7/CTS1#/GPI7
73
78
ADP_ID
SUSWARN#
ADP_ID <56>
GC6_EVENT# RE39 1 @ 2 10K_0402_5%
KSO[0..17] KSI1/AFD# DAC2/TACH0B/GPJ2 SUSWARN# <15>

<45> KSO[0..17] KSI2 60 79 MAINPWON
KSI2/INIT# DAC3/TACH1B/GPJ3 MAINPWON <56,57,59>
RE10 1 2 2.2K_0402_5% EC_SMB_CK1 KSI3 61 DAC 80 H_PROCHOT_EC
RE11 1 2 2.2K_0402_5% EC_SMB_DA1 KSI4 62 KSI3/SLIN# DAC4/DCD0#/GPJ4 81 PCH_ENBKL +3VL
KSI4 DAC5/RIG0#/GPJ5 PCH_ENBKL <14>
KSI5 63
KSI6 64 KSI5 85 AOU_EN LID_SW# RE22 1 2 10K_0402_5%
C C
+3VALW KSI6 PS2CLK0/TMB0/CEC/GPF0 AOU_EN <41>
KSI7 65 86 PBTN_OUT#
KSI7 PS2DAT0/TMB1/GPF1 PBTN_OUT# <15>
KSO0 36 87 PM_SLP_SUS# PM_SLP_SUS# <15,55> GC6_EVENT# RE40 1 2 10K_0402_5%
KSO1 37 KSO0/PD0 GPF2 88 SUSACK#
KSO1/PD1 Int. K/B PS2 GPF3 SUSACK# <15>
RE18 1 2 10K_0402_5% KSO1 KSO2 38 89 TP_CLK
RE19 1 2 10K_0402_5% KSO2 KSO3 39 KSO2/PD2 Matrix PS2CLK2/GPF4 90 TP_DATA
TP_CLK <43>
KSO3/PD3 PS2DAT2/GPF5 TP_DATA <43>
KSO4 40
RE38 1 2 100K_0402_5% HDD_DETECT# KSO5 41 KSO4/PD4 96 PCH_APWROK +3VALW
KSO5/PD5 EXTERNAL SERIAL FLASH GPH3/ID3 PCH_APWROK <15>
KSO6 42 97 PCH_PWR_EN
KSO6/PD6 GPH4/ID4 PCH_PWR_EN <55>
RE16 1 2 10K_0402_5% KB_FN KSO7 43 98 ACOFF ACOFF <58>
KSO8 44 KSO7/PD7 GPH5/ID5 99 PCH_PWROK AOU_DET# RE15 1 2 10K_0402_5%
KSO8/ACK# GPH6/ID6 PCH_PWROK <15,8>
KSO9 45
+3VS KSO10 46 KSO9/BUSY 101 BTRF_OFF# FAN_ID RE17 1 2 10K_0402_5%
KSO10/PE NC1 BTRF_OFF# <39>
KSO11 51 102 EC_GS_ON#
KSO11/ERR# NC2 EC_GS_ON# <33>
RE13 1 2 2.2K_0402_5% EC_SMB_CK3 KSO12 52 SPI Flash ROM 103 EC_3G_DET# EC_3G_DET# <40> LAN_WAKE# RE36 1 2 10K_0402_5%
RE14 1 2 2.2K_0402_5% EC_SMB_DA3 KSO13 53 KSO12/SLCT NC3 105 VM_PWRON
KSO13 NC4 VM_PWRON <53,67>
KSO14 54
RE7 1 2 10K_0402_5% LPC_FRAME# KSO15 55 KSO14
KSO16 56 KSO15 108 AC_IN#
KSO17 57 KSO16/SMOSI/GPC3 AC_IN# 109 LID_SW# AOAC_ON RE31 1 2 100K_0402_5%
KSO17/SMISO/GPC5 UART LID_SW# LID_SW# <45>
<42,45> ON/OFFBTN# ON/OFFBTN# 110 82 FB_CLAMP

PWRSW# EGAD/GPE1 FB_CLAMP <23,27>
111 SM Bus 83 GC6_EVENT# GC6_EVENT# <19,23>
EC_SMB_CK1 115 XLP_OUT EGCS#/GPE2 84 AOU_CTL1
<57,58> EC_SMB_CK1 SMCLK1/GPC1 EGCLK/GPE3 AOU_CTL1 <41>
EC_SMB_DA1 116
RE37 <57,58> EC_SMB_DA1 SMDAT1/GPC2
1 2 H_PECI_R 117 GPIO 77 PM_SLP_S5# PM_SLP_S5# <15>
<6> H_PECI SMCLK2/PECI/GPF6 GPJ1
ADP_PROTECT 118 100 EC_MUTE#
43_0402_5% <57> ADP_PROTECT SMDAT2/PECIRQT#/GPF7 SSCE0#/GPG2 EC_MUTE# <46>
EC_SMB_CK3 94 106 TP4RST
<17,23,32> EC_SMB_CK3 CRX1/SIN1/SMCLK3/GPH1/ID1 SSCE1#/GPG0 TP4RST <43>
EC_SMB_DA3 95 104 ME_FLASH
<17,23,32> EC_SMB_DA3 CTX1/SOUT1/GPH2/SMDAT3/ID2 DSR0#/GPG6 ME_FLASH <13> +3VALW
107 SYSON
DTR1#/SBUSY/GPG1/ID7 SYSON <60>
119 BKOFF#
CRX0/GPC0 BKOFF# <36>
123 AOAC_ON
CTX0/TMA0/GPB2 AOAC_ON <39>
+3VL RE20 1 2 0_0402_5% +3VL_VSTBY0 112 18 PM_SLP_S3# PM_SLP_S3# <15> EC_MUTE# RE35 1 @ 2 10K_0402_5%
VR_ON 125 VSTBY0 RI1#/GPD0 21 PM_SLP_S4#
<64> VR_ON GPE4 RI2#/GPD1 PM_SLP_S4# <15>
WAKE UP 76 PM_SLP_A# PM_SLP_A# <15> RE41 1 2 10K_0402_5%
TACH2/GPJ0 48 AOU_CTL3
TACH1A/TMA1/GPD7 AOU_CTL3 <41>
47 EC_FAN_SPEED EC_FAN_SPEED <43>
B
USB_ON# 33 TACH0A/GPD6 19 WLAN_WAKE#_EC B
<37>
<15>
USB_ON#
EC_DPWROK
EC_DPWROK 35 GINT/CTS0#/GPD5
GPIO
L80HLAT/BAO/GPE0 20 KB_FN
WLAN_WAKE#_EC
KB_FN <45>
<39> 1. Version CX : Don't Support Mirror Code
EC_RSMRST# 93 RTS1#/GPE5 L80LLAT/GPE7
<15> EC_RSMRST# CLKRUN#/GPH0/ID0 Version DX/EX/FX : Support Mirror Code
EC_WAKE# 2
Please don't place any PU Resistor on GPG[7:2] 2. For Mirror Code
<13> EC_WAKE# CK32KE/GPJ7
128
CK32K/GPJ6 Clock (Reserve hardware strapping) "H" --> Enable
<15> AC_PRESENT
AC_PRESENT RE25 1 2 0_0402_5% AC_PRESENT_R * "L" --> Disable (Default)
VGA_AC_DET RE26 1 2 0_0402_5%
<23> VGA_AC_DET
AVSS
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
AC IN
IT8586E-AX_LQFP128_14X14 +3VL
IT8586E/FX LQFP
1
27
49
91
113
122
75
SA00005W940
AC_IN# RE21 1 2 10K_0402_5%
RE23 1 2 0_0402_5%
ACPRN <58>
EC_AGND
DV3 @ 2 1 RB751V-40_SOD323-2
CE15 1 2 100P_0402_50V8-J
SYSON, SUSP#
For factory EC flash
EC_SMB_CK1
IT0 PAD
EC_SMB_DA1
PROCHOT# IT1
IT2
PAD
PAD
SUSP# RE29 1 2 100K_0402_5%
A
(EC asserts PROCHOT# signal by driving high, IT3 PAD
A
IT4 PAD
the level shifter must invert it and drive the processor side PROCHOT# low.)
Dr-Bios.com
For ESD SYSON RE30 1 2 100K_0402_5%
CE2 1 @ 2 220P_0402_50V7-K PLT_RST# KSI7
IT5 PAD
KSI6 CE16 1 @ 2 0.1U_0402_25V7-K
IT6 PAD
For EMI RE1 RE27 1 2 0_0402_5% H_PROCHOT# H_PROCHOT# <6> WRST#
<56,57,64> VR_HOT# IT7 PAD
CE11 1 @ 2 10P_0402_50V8-J 1 @ 2 CLK_PCI_EC For EMC
1
D
1
10_0402_5% H_PROCHOT_EC 2
CE14 2 1 100P_0402_50V8-J BATT_TEMP G CE13 Title
QE1 S 47P_0402_50V8-J Security Classification LC Future Center Secret Data
3
2N7002KW_SOT323-3 2
!"#EC$
BATT_TEMP! $ADC pin Issued Date 2012/12/05 Deciphered Date 2014/12/05 EC_IT8586E-CX LQFP_128P
Size
Document Number Rev
RE8 1 @ 2 0_0402_5% C 1.0
PROCHOT <57> DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
!""#$%&'()*)
5 4 3 2 1
5 4 3 2 1
JDB1 ME@
1
2 1
3 2
D 4 3 D
5 4
6 5
7 6
8 7
9 8
10 9
11 10 13
12 11 GND1 14
12 GND2
ACES_85201-1205N
C C
B B
A A
5
Dr-Bios.com
4
3 2
Title
Date:
BLANK
Custom
!##$%&'()*"*
1
Sheet 49 of 57
Rev
1.0
A B C D E
+3VALW +3VALW +3VALW +3VALW
1 1 1 1
C166 C167 C168 C169
0.1U_0402_10V7-K 0.1U_0402_10V7-K 0.1U_0402_10V7-K 0.1U_0402_10V7-K
1 2 2 2 2 1
Location : 560.00 -6055.00 Location :1010.00 -130.00 Location : -2490.00 -5940.00 Location : -1880.00 142.00
+0.675VS +0.675VS
1 1 1 1
C170 C171 C172 C173
47P_0402_50V8-J 2200P_0402_50V7-K 47P_0402_50V8-J 2200P_0402_50V7-K
2 2 2 2
close to JDDR3L and Pin .203/.204 close to JDDR3H and Pin .203/.204
1. 47P --> Location : -3885,-5914 (BOT) 1. 47P --> Location : -4198,-5416 (TOP)
2 2. 2200P --> Location : -3885,-5877 (BOT) 2. 2200P --> Location : -4204,-5384 (Top) 2
3 3
4 4
A
Dr-Bios.com B
C D
Title
Date:
BLANK
Custom
!##$%&'()*"*
E
Sheet 50 of 57
Rev
1.0
5 4 3 2 1
D D
C C
B B
A A
5
Dr-Bios.com
4
3 2
Title
Date:
BLANK

Custom
!"#$%&'()*+*
1
Sheet 51 of 57
Rev
1.0
Screw Hole
H19 H18
H5 H6 H_2P5 H_2P5N
H_3P8 H_3P8
@ @
1
@ @
1
H17
GPU Screw H_2P5
H7 H8
H_3P8 H_3P3 @
1
H26 @ @
1
H_2P5 H1 H2
H_3P8 H_3P8
@ H25
1
@ @ H_6P6N
1
@
1
H24 H9
H_6P6N CPU Screw H_2P5
@ H4 H3 @
1
1
H_3P8 H_3P8
@ @
1
H20
H_2P5
@
1
H23
H_2P6X3P1N
H15
H_2P5
@
1
H12
H_2P5 H13 @
1
H_2P5 H14
H_2P5
@
1
@
1
LED3
POWER
LED2
BATTERY
Dr-Bios.com
LED1
T/P
LED4
CapsLK
PCB Fedical Mark PAD
FD1 FD2 FD3 FD4
Title
PLM/SCREW HOLE
Rev
1
Custom 1.0
!"#$%&'()*+*
+3VALW to +3VM
FOR SBA Function POWER(always mount)
+3VALW +3VM
U14
5 1 +3VM
IN2 OUT
1 2 1
GND
C136 4 3 VM_PWRON_R C137
1U_0402_6.3V6-K IN1 EN 4.7U_0603_6.3V6-K
2 G5243AT11U_SOT23-5 2
SA00005XJ00
From EC R25 1 2 0_0402_5% VM_PWRON_R

<48,67> VM_PWRON
1
R31
100K_0402_5%
2
already have 1M PD to GND on Power side
Dr-Bios.com Security Classification

Title
ONOFF SW/ PWR-B CONN/ ISPD

Custom
Date:
!"#$%&'()*+*
JITR1_LA-4141P
Thursday, July 11, 2013 Sheet 53 of 57
Rev
1.0
+1.5V to +1.5VS_VGA
+1.5VS +1.5VS_VGA
J4 @
1 2
1 2
JUMP_43X79
+5VALW
+1.5VS +1.5VS_VGA
Q18 DIS@
1
AO4430L_SO8
8 1 C139 C140 C141
+VSB 7 2 DIS@ R127
10U_0603_6.3V6M
10U_0603_6.3V6M
0.1U_0402_10V7K
6 3 100K_0402_5%
5 1 1 1
2
1
@ DIS@ DIS@
FBVDDQ_PWR_EN#
1
DIS@ R128
From GPU
1
100K_0402_5% 2 2 2 R130 D
DIS@ R129 1 DIS@ 2 2 Q19 DIS@
<27> FBVDDQ_PWR_EN
2 R131 150_0603_1% G 2N7002KW_SOT323-3
+1.5VS_VGA_GATE 1 DIS@ 2 10K_0402_5% S
3
1
0_0402_5%
3
D D R134 @ R133
FBVDDQ_PWR_EN# R132 1 2 0_0402_5% 2 DIS@ C142 5 1 2 FBVDDQ_PWR_EN# 100K_0402_5%
G 0.01U_0603_50V7K G
2
1
0_0402_5%
1S S
4
@ R135 Q20A DIS@ Q20B DIS@
100K_0402_5% 2N7002KDWH_SOT363-6 2N7002KDWH_SOT363-6
SB00000YR00 SB00000YR00
2
1. Mount 470 ohm of R129 (Speed up discharge electric time by 1.5VS_VGA).
+3VS to +3VS_VGA
+3VS +3VS_VGA
J5 @
1 2
1 2
JUMP_43X79
+5VALW +3VS +3VS_VGA +5VALW

1
3 1
1
1
DIS@ R139 Q22 DIS@
1
20K_0402_5% AO3413_SOT23-3 C143 DIS@ DIS@ R136

G
2
10U_0603_6.3V6M 100K_0402_5%
2
R141 DIS@ R140 2
2
DGPU_PWR_EN# 1 DIS@ 2 150_0603_1% DGPU_PWROK#
DGPU_PWROK# <63>
From GPU
3 2
10K_0402_5%
From +VGA_CORE IC
6
1
D D R143 DIS@ R137 D
R142 1 DIS@ 2 0_0402_5% 2 DIS@ C144 5 1 2 DGPU_PWR_EN# 1 DIS@ 2 2 Q21 DIS@
<14,23> DGPU_PWR_EN G G <19,27,62,63> DGPU_PWROK
0.01U_0402_16V7K G 2N7002KW_SOT323-3
1
10K_0402_5% 10K_0402_5% S
3
1
1
S Q23B DIS@ S 1
1
Q23A DIS@ 2N7002KDWH_SOT363-6

DIS@ R144 2N7002KDWH_SOT363-6 SB00000YR00 DIS@ C145 @ R138
100K_0402_5% SB00000YR00 0.1U_0402_10V7K 100K_0402_5%
2
2
2
1. R140 from 470 change to 150 (Speed up discharge electric time by 3VS_VGA).
2. R139 form 100K change to 20K (Let fall time rapider for 3VS_VGA).
Power Up -->
+3VS_VGA (En:DGPU_PWR_EN)
Dr-Bios.com
+VGA_CORE (En:NVDD_PWR_EN, POK:DGPU_PWROK) Title
Security Classification LC Future Center Secret Data
+1.5VS_VGA (En:FBVDDQ_PWR_EN# = FB_CLAMP and DGPU_PWROK) Issued Date 2012/12/05 Deciphered Date 2014/12/05 DOCKING USB30/DP
+1.05VS_VGA (En:DGPU_PWROK#) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Custom
Rev
1.0
!##$%&'()*"*
A B C D E
Load Switch
+5VALW To +5VS +5VALW VIN 5V and 3.3V (VBIAS=5V), IMAX(per channel)=6A, Rds=18mohm +5VS
+3VALW To +3VS 1
U9
14 +5VS_LS 1
PJ6 @
2
1 2 VIN1_1 VOUT1_2 13 1 2 1
VIN1_2 VOUT1_1 JUMP_43X118
1 1
SUSP# 3 12 C159 1 2 1000P_0402_25V7-K
@ C161 ON1 CT1 @ C156
1U_0402_6.3V6-K +5VALW 4 11 0.1U_0402_10V7-K
2 VBIAS GND 2
SUSP# 5 10 C160 1 2 2200P_0402_25V7-K
+3VALW ON2 CT2 +3VS
6 9 PJ7 @
7 VIN2_1 VOUT2_2 8 +3VS_LS 1 2
VIN2_2 VOUT2_1 1 2
1 15 JUMP_43X118 1
GPAD
@ C162 TPS22966DPUR_WSON14_2X3 @ C158
1U_0402_6.3V6-K 0.1U_0402_10V7-K
2 2
+5VALW
+5VS, C159 --> 1.5ms
+5VS
+3VS, C160 --> 2.5ms
1 1 1
1 1 1 1
C178 C179 C180
0.1U_0402_25V7-K 0.1U_0402_25V7-K 0.1U_0402_25V7-K C181 C182 C183 C184
2 2 2 0.1U_0402_25V7-K 0.1U_0402_25V7-K 33P_0402_50V8-J 33P_0402_50V8-J
2 2 2 2
ESD
ESD
2 2
+3VALW To +3V_PCH
R72 1 @ 2 0_0805_5%
+3VALW +3V_PCH
U13
0.271 A
From EC PCH_PWR_EN R152 1 2 0_0402_5% PCH_PWR_EN_R
80 mils 5 1 +3V_PCH
80 mils
<48> PCH_PWR_EN IN2 OUT
1 2 1
PM_SLP_SUS# R153 1 @ 2 0_0402_5% GND
<15,48> PM_SLP_SUS#
C154 4 3 PCH_PWR_EN_R C155
1U_0402_6.3V6-K IN1 EN 4.7U_0603_6.3V6-K
From PCH 2 G5243AT11U_SOT23-5 2
1
SA00005XJ00
R154
100K_0402_5%
2
3 3
For DisCharge
+5VALW +0.675VS
1
R156 R157
100K_0402_5% 22_0805_5%
2
SUSP
<39,60,63> SUSP
6
Q30A D D Q30B
SUSP# 2 5 SUSP
<39,48,61,62> SUSP# G G
2N7002KDWH_SOT363-6 S S 2N7002KDWH_SOT363-6
1
4 SB00000YR00 SB00000YR00 4
A
Dr-Bios.com B
Deciphered Date
C D
2014/12/05
Custom

Title
DC V TO V/VS INTERFACE
!##$%&'()*"*
E
Sheet 55 of 57
Rev
1.0
5 4 3 2 1
ADP_ID
PR101
750_0402_1% AC Adapter 90W 65W
680P_0603_50V7K
1 2
+3VALW ADP_ID <48> R(K ohm) open 10
0.1U_0402_6.3V7-K
A/D ADP_ID(V) 3.3 1.65 VL
1
+5VALW
PC101
PC102
Detection voltage >2.64 1.32~1.98 2013-05-21
VL
100K_0402_1%
100K_0402_1%
1
1
+5VALW
PR1209
PR1214
VL
PJDCIN VIN
D 1 D
540_0402NEW_30%_PRF15BB541NB6RC
540_0402NEW_30%_PRF15BB541NB6RC
540_0402NEW_30%_PRF15BB541NB6RC
1
1
2 APDIN @
PF1
2
2
10K_0402_5%
3 1 2 APDIN1 1 2 PC1226
3
10K_0402_5%
4 1U_0603_10V6K
2
4
100K_0402_1%
PR1215
5 7A_32V_0437007.WR PL101
5
1000P_0402_50V7-K
PR1208
PR1210
8 6 SMB3025500YA_2P
GND1 6
1000P_0402_50V7-K
100P_0402_50V8J
100P_0402_50V8-J
9 7 @
GND2 7 PU1203
2
1
1
ACES_50271-00701-001 1
2
IN+
RT2
RT3
RT4
@ 5
2 VCC+ PR1211
2
GND
PC103
PC104
PC105
PC106
4 1 2
OUT MAINPWON <48,57,59>
3
2
IN- 0_0402_5%
LMV331IDCKRG4_SC70-5
540_0402NEW_30%_PRF15BB541NB6RC
540_0402NEW_30%_PRF15BB541NB6RC
540_0402NEW_30%_PRF15BB541NB6RC
1
1
RT5
RT7
RT8
Thermal protect
2
RT2 place to closed PQ401 with PU401
C RT5 place to closed PQ312 with PU301 C

2013-04-18 +5VS
+3VALW
VR_HOT#
1
VIN PR104
47K_0402_1% PR103
10K_0402_1%
8
2
2
1
D PC108 3
2
PD104 PQ103 2 1 2 1 + BATT_TEMP <48,57>
LL4148_LL34-2 O 2
2013-04-18 G
-
G
@ @ 2N7002BKW_SOT323-3 S 0.022U_0402_25V7-K PU101A
100P_0402_50V8-J
PD105 LM393DMR2G MICRO8 8P
1
4
1
1
LL4148_LL34-2 51ON-1 1
1
BATT+ 2 1 PD102 PR106 2013-04-25
1
LL4148_LL-34-2 1.5M_0402_5%
PC107
PR102
@ PR123 PR124 100K_0402_1%
B PQ101 68_1206_5% 68_1206_5% 2 B
2
TP0610K-T1-GE3_SOT23-3 @ @ +5VS
2
2
2013-04-18
51ON-2 3 1
VS
1
0.22U_0603_25V7K
<48,57,64> VR_HOT# PR105

1
2013-05-17 @ 47K_0402_1%
2
1
PC114
PR128 PC115
8
100K_0402_1% @ 0.1U_0603_25V7K
2
1
@ D PC109 5
P
1
PQ102 2 1 2 7 +
2013-04-18
2
G O 6
-
G
51ON-3 2N7002BKW_SOT323-3 S 0.022U_0402_25V7-K PU101B PACIN <58>
1
LM393DMR2G MICRO8 8P
4
1
PD101
LL4148_LL-34-2 PR107 2013-04-25
1.5M_0402_5%
2
RTCVREF
2
+CHGRTC
PR132 PR133
PD106
@ 560_0603_5% 560_0603_5% 3.3V
+RTCBATT 1 2 1 2 1 2
@ @
RB751V-40_SOD323-2
1
PC116
PD107 10U_0603_6.3V6M
2
1 2 @
A +3VLP A
RB751V-40_SOD323-2
Dr-Bios.com
2013-05-14
Issued Date 2012/07/01 Deciphered Date 2014/07/01 PWR-DCIN / Vin Detector

RTC Battery THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Custom 1.0
!##$%&'()*"*
5 4 3 2 1
5 4 3 2 1
PH1 under CPU botten side :

CPU thermal protection at 93 +-3 degree C
Recovery at 56 +-3 degree C
VMB2 VMB PR223
PF201 PL201 0.01_1206_1% VL
JBATT1 12A_65V_451012MRL SMB3025500YA_2P 2013-04-18 +3VLP
1 1 2 1 2 1 4 1 2
1 BATT+ <48,58> ADP_I
30K_0402_1%
2 PR227 PQ206
2
1
4.42K_0402_1%
12.7K_0402_1%
3 EC_SMCA 2 3 2.1K_0402_1% 2N7002BKW_SOT323-3
3
1
D
PR207
4 EC_SMDA
4
PR205
PR206
.01U_0402_25V7-K
5 2
5
1
DCN
DCP
D 6 G ADP_PROTECT <48> D
6 7 PC201 PC203 +3VS S @
2
7
PC202
8 1000P_0402_50V7-K 0.1U_0603_16V7K PU201
2
G1
3
9 1 8 NTC_V_1 2013-05-23
G2 10 VCC TMSNS1
G3 1
100K_0402_1%
11 2 7 OTP_N_002 2 1
G4 PESD5V0U2BT_SOT23-3 GND RHYST1
100_0402_1%
100_0402_1%
PR209
PR208
PD805 3 6 Turbo_V_1 499K_0402_1%
100K_0402_1%_NCP15WF104F03RC
@ <48,56,64> VR_HOT# OT1 TMSNS2
1
@ PR210 PR230
1
PR202
PR201
SUYIN_200082GR007M211ZR 4 5 ADP_OCP_2 1 2 2013-07-08 0_0402_5%
+3VALW
2
1
OT2 RHYST2
1
10K_0402_1%
1
2
D G718TM1U_SOT23-8 27.4K_0402_1% PR228
2011_0823 2013-04-18 2013-07-08
PR211
PH201
change 9P JBATT1 PQ201 2ADP_OCP_1 0_0402_5%
2
OTP_N_003
2N7002BKW_SOT323-3 S
G
@
PR229 +3VLP 2 1
EC_SMB_CK1 <48,58> 2013-07-08
2
1 2 1 2 PR232
1
PR212 @ PR213 47K_0402_1%
0_0402_5% 0_0402_5% PR231
EC_SMB_DA1 <48,58> <48> PROCHOT 0_0402_5%
PR203 1 2 2 1 47K_0402_1%
MAINPWON <48,56,59>
100K_0402_1% @
2 1 +3VALW
1 2
A/D
PR204
BATT_TEMP <48,56>
PR248
@ T135
1 Turbo_V
750_0402_5% 0_0402_5%
2
<BOM Structure> VCP 1 2

@ T136
1 NTC_V
PESD5V0U2BT_SOT23-3
C PD806 PR247 PR246 C
PU102 @ @
@ 1 6 1 2 2 1
1
VMB REF OUT +5VS

2 5 DCN 150K_0402_1% 100K_0402_1%
GND IN-
221K_0402_1%
3 4 DCP
V+ IN+
1
+3VS
PR234
INA199A1DCKR_SC70-6 PR233
+1.05VS 0_0402_5%
2011_0731 add circuit for battery learning function 1 2 VR_HOT#
1
2011_1119 change circuit to unmount from mount PR235
2
2
PR249 2013-05-15 1 2
PR237
DCP
10K_0402_1%
DCN
@ PC214 @ 100K_0402_1% PR236 1.78M_0402_1% 2013-04-18
8
P2 0.1U_0402_25V6 @ PC212 PC213 @ 20K_0402_1%
1
+1.05VS 2 1 1 2 1 2 VCP 1 2 3 D
P
1
+3VLP +3VALW + 1 2 PQ207
0.1U_0402_25V6 0.1U_0402_25V6 2 O G 2N7002BKW_SOT323-3
-
G
+5VALW
220P_0402_50V7-K
.01U_0402_25V7-K
@ PR250 PU1204A S
3
2
100P_0402_50V8-J
1 2 LM393DMR2G MICRO8 8P
4
VMB2
2
1
PC208
1K_0402_1% @
1
PC207
PC209
PR222 PR220 @ PC215 PR238
1
1
100K_0402_1% 100K_0402_1% 1 PR251 2 0.1U_0402_25V6 100K_0402_1% 2013-04-25
2
PR224 PR218 1K_0402_1% PR256
2
2
4
255K_0402_1% 10M_0402_5% 2.2_0402_5%
1
1
1 2 10 1 @
PG
BATT_OUT <58> PVIN2 LX1
PR219 PR255
2
10K_0402_1% VR_HOT# 2 1 9 2
@ 0_0402_5% PVIN1 LX2
8
1 2 @
Battery Protection Circuit for Turbo Mode
1
3 D MAINPWON 2 1 8 3 1 PR257 2
P
+ SVIN1 LX3 +3VALW

1 2
O
1
0.1U_0402_25V6
PR221 2 G PR254 @ 0_0402_5% PR260 13K_0402_1% @
-
G
2
1
B
150K_0402_1%<BOM Structure> PU202A PQ204 S +5VS B
3
20K_0402_1%
PC218
2N7002BKW_SOT323-3 5 6
GND
4
2
LM393DMR2G MICRO8 8P EN FB @
NC
2013-04-18
1
+3VLP
374K_0402_1%
221K_0402_1%
2013-04-25
1
PR261
PU203 +3VS
1
11
2
1
PR242
RT9553 PR241
2 PQ205 @ 0_0402_5%
2
G @ @ PR252 1 2 VR_HOT#
2
+3VLP PR226 S 2N7002BKW_SOT323-3 1 2 Turbo_V_1 PR239

+3VALW
3
2
2
100K_0402_1% 10K_0402_1% 1 2
2 1 @ PR253 PR243
1 2 150K_0402_1% PR240 1.78M_0402_1% 2013-04-18
1
8
PR225 10K_0402_1% 20K_0402_1%
1
1
10K_0402_1% 1 2 5 D
P
1
PR259 PR258 + 7 2 PQ208
10K_0402_1% 6 O 2N7002BKW_SOT323-3
2013-04-18 20K_0402_1% -
G
G
220P_0402_50V7-K
@ @ PU1204B S
<48> BATT_LEN#
3
100P_0402_50V8-J
LM393DMR2G MICRO8 8P
2
4
2
1
PC210
PQ202
1
PC211
TP0610K-T1-GE3_SOT23-3 PR244 PR245 2013-04-25
84.5K_0402_1% 10K_0402_1%
2
2
B+ 3 1
+VSBP
2
100K_0402_1%
0.22U_0603_25V7K
2013-07-01
1
VL
1
1
PR214
PC204
PC205
0.1U_0603_25V7K Adaptor Protection Circuit for Turbo Mode
2
2
2
PR216 PR215 PJ201

100K_0402_1% 22K_0402_1% @ JUMP_43X39
A 1 2 1 2 A
+VSBP 1 2 +VSB
1
PR217
Dr-Bios.com
1
1K_0402_5% D
1 2 2 PQ203 2013-04-18
<59> SPOK
G
1U_0402_10V6K
S 2N7002BKW_SOT323-3
3
1
PC206
Issued Date 2012/07/01 Deciphered Date 2014/07/01 PWR-BATTERY CONN/OTP

2
2011_1005 PQ105 change Size Document Number
Rev
Custom 1.0
form SB000006800(2N7002W T/R7 1N SOT-323)
to SB000009Q80( 2N7002KW 1N SOT323-3)
!##$%&'()*"*
5 4 3 2 1
5 4 3 2 1
PQ302
P3
B+ AO4407AL_SO8
2013-07-01
P2 1 8
2 7
PQ301 PQ304 3 6
AO4407AL_SO8 SI4483ADY 1P SO8 5
8 1 1 8 PR302
VIN 7 2 2 7 0.01_1206_1% 2013-05-16 B+
SH00000AA00
4
6 3 3 6
5 5 1 2 1 4
PL301 2 3 VIN
4
1UH_PCMB061H-1R0MS_7A_20% PR305
10U_0805_25V6-K
47K_0402_1%
2200P_0402_25V7-K
10U_0805_25V6-K
47P_0402_50V8-J
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
PQ305 PC310 1 2
D D
47K_0402_5%
68P_0402_50V8-J
1 2 1 1
1
2
200K_0402_1%
PC304
0.1U_0603_25V7K
PRFC32
2 1
PC308
1
PR301
PC303
PC305
PC306
PC307
PRFC33
LTA044EUBFS8TL_UMT3F PC302
2
1U_0603_25V6M
10K_0402_1%
PC301
PR306
PC309
2200P_0402_25V 0.1U_0603_25V7K
1
2 1 2 2
2
PR307
2 PC312
2
2013-07-01 0.1U_0603_25V7K
1DISCHG_G-1
1
2
2ACOFF-1
1SS355_SOD323-2
PR304 PR308
1
10_0402_1%
PR303 200K_0402_1%
0_0402_5%
1
PD302
1
P2-1
2 2013-05-09 DOCK_CONSUMP <42>
PQ307
1
LTC015EUBFS8TL_UMT3F PR331 +3VALWP PR310 2 1 2
20K_0402_1% <48> ACPRN 1 2
2013-04-18
3
2013-07-01 PD303 2013-04-18
100K_0402_1%
2N7002KDW-2N_SOT363-6
1 2 2013-04-18 10_0402_1% 1SS355_SOD323-2
6
@ 10K_0603_1%
0.1U_0603_25V7K
PQ317 PQ308
3
1
6
D
150K_0402_1%
PQ311A
PR337 @
2N7002BKW_SOT323-3 LTC015EUBFS8TL_UMT3F
1
PR309
PR336
PC311
PQ310A 2
BATT_OUT <57> PC110
2 2N7002KDW-2N_SOT363-6 G
S 1 2 2 PACIN
P2
3
2
1
2
VIN PR338 @ PR339 @ @
1
2 1 1 2 100P_0402_50V8-J
2013-04-18 432K_0603_1% 4.7M_0603_1% ACP ACN
1
5
P2-2
10_1206_5%
39.2K_0402_1%
2
C C
PR314
2N7002KDW-2N_SOT363-6
PR317
3
PQ310B
ACOK
CMPIN
CMPOUT
ACP
ACN
PR318 PR319 <48,57> ADP_I
2
47K_0402_1% 64.9K_0603_1% 21 4
PACIN 1
1
2 5 1 2 6 TP
<56> PACIN ACDET PC314
PL302
1 2 PC313 20 BQ24727VCC-1 1 2 PQ312 10UH_PCMB104T-100MS_6A_20% PR320
4
1 2 7 VCC SIS412DN-T1-GE3 0.01_1206_1%
3
2
1
IOUT
PC323 0.1U_0603_25V7K
1U_0603_25V6M
BATT+
1
PQ313 100P_0603_50V8 19 LX_CHG 1 2 CHG 1 4

LTC015EUBFS8TL_UMT3F <48,57> EC_SMB_DA1 8 PU301 PHASE
SDA 2 3
BQ24737RGRR_VQFN20_3P5X3P5
PR321 18 DH_CHG
HIDRV
1
<48,57> EC_SMB_CK1
4.7_1206_5%
1 2ACOFF-12 9
<48> ACOFF SCL SA000051W00
PR322
10K_0402_5% PR324
PR323 3.3_0603_5%
1
10U_0805_25V6-K
10U_0805_25V6-K
PR332 1 2 10 17 BST_CHG 1 2 2 1 SRP SRN
0_0402_5% 316K_0402_1% ILIM BTST
+3VALW PD301
3
2
2013-07-08 PC315
LODRV
2
16 2 1 0.047U_0603_25V7M 4
GND
24727_SN
SRN
SRP
REGN
PC316
PC317
BM
2
RB751V-40_SOD323-2
1
680P_0603_50V7K
11 BQ24737_VDD PQ314
1 12
13
14
15
1
1
D
10_0603_5%
6.8_0603_5%
PR330 SIS412DN-T1-GE3
3
2
1
PR327
BATT_OUT 2 PQ318 1 2 PC318
1
PR326
G 2N7002BKW_SOT323-3 1U_0603_25V6M
2
S 84.5K_0402_1%
3
PC319
2013-04-18
2
2
2013-06-25
2
PR325 PC320 DL_CHG

B 100K_0402_1% 0.1U_0603_25V7K B
2 1
2
CHGVADJ=(Vcell-4)/0.10627
1
Vcell CHGVADJ
1
PC321 <BOM Structure>
4V 0V 0.1U_0603_25V7K PC322
2
2 0.1U_0603_25V7K
4.2V 1.882V
4.35V 3.2935V
BQ24737_VDD
CC=0.25A~3A 2013-05-21
IREF=1.016*Icharge PR334
10K_0402_1%
1
IREF=0.254V~3.048V 1 2 T_ACIN 1
TACIN
@ PR329 @
VCHLIM need over 95mV PR328 10K_0402_1%
47K_0402_1%
2
PACIN
2N7002KDW-2N_SOT363-6
1
3
PQ311B
PR335
ACPRN 5 12K_0402_1%
2
A A
2013-04-18
4
5
Dr-Bios.com For disable pre-charge circuit.
4
3
Custom
Date:

Deciphered Date
2
2014/07/01
Title
PWR-CHARGER-BQ24737
!""#$%&'()*)
1
Sheet 58 of 69
Rev
1.0
5 4 3 2 1
PJ402
+3VALWP 2 1 +3VALW
2 1
@ JUMP_43X118
2013-05-09
PC425
D D
PR402 @ 0.1U_0402_25V6 PJ403
13K_0402_1% +5VALWP 2 1 +5VALW
1 2 1 2 2 1
@ JUMP_43X118
PC411
PR414 71.5K_04021_1%
PR418 147K_0402_1%
@ 0.1U_0402_25V6 PR403
30K_0402_1%
82K_0402_1%
1 2 1 2
1
PR405
PR404 20K_0402_1%
20K_0402_1% 1 2
PR407
1 2
2
TPS51225_B+
3V5V TON
ENTRIP2
ENTRIP1
FB_5V 2013-05-16
TPS51225_B+
PJ401 2013-05-16
2200P_0402_25V7-K
PU401
47P_0402_50V8-J
2 1
B+
2200P_0402_25V7-K
2 1
1
RT8243AZQW_WQFN20_3X3
10U_0805_25V6-K
10U_0805_25V6-K
0.1U_0603_25V7K
0.1U_0603_25V7K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
0.1U_0402_25V6
1
1
47P_0402_50V8-J
PC410
PC409
PC408
PC407
@ JUMP_43X118
PRFC35
FB2
ENTRIP2
TON
ENTRIP1
FB1
PC401
PC403
1 PQ401 21
<57> SPOK GND
1
1
PC405
PC404
PC406
SIS412DN-T1-GE3 6 PQ402
PRFC34
2
PGOOD
5
PC412 PR408 20 SIS412DN-T1-GE3 2

BYP1
5
0.1U_0603_25V7K 2.2_0603_5% PR409 PC413
2
C
2 1 2 1 2 BST_3V 7 2.2_0603_5% 0.1U_0603_25V7K C
BOOT2 19 BST_5V 1 2 1 2
BOOT1
4 UG_3V 8
UGATE2 18 UG_5V 4
UGATE1
LX_3V 9
PHASE2 17 LX_5V
1
2
3
PHASE1
3
2
1
LG_3V 10
LGATE2 16 LG_5V
ENLDO
+3VALWP LGATE1
LDO5
LDO3
PL401
+5VALWP
ENM
PL402
VIN
4.7UH +-20% PCMB063T-4R7MS 5.5A
1 2 PC420 1 2
PQ403 0.1U_0603_25V7K
11
12
13
14
15
SIS412DN-T1-GE3
1
5
680P_0603_50V7K 4.7_1206_5%
1 2 TPS51225_B+ 2.2UH_PCMB063T-2R2MS_8A_20%
1
PR401
680P_0603_50V7K 4.7_1206_5%
1
+3VLP PR419 +3VL 2013-05-09
PR410
1 SNUB_3V
+ PC414 0_0603_5%~D 1
150U_B2_6.3VM_R45M 2 1
2
4 4 + PC415
2013-07-08
2
2 1 2 220U_B2_6.3VM_R25M
TPS51225_B+ PQ404
2
100K_0402_1%
PC416
1U_0603_10V6K
1U_0603_10V5K
1U_0603_10V6K
PR413 SIS472DN-T1-GE3
1
0_0603_5%
PC417
499K_0402_1%
1
2
3
3
2
1
1
1
PR406
PC421
PC419
PR412
PC402
2
2
2
2
1
1
B B
VL
2013-04-18
1 2
<48> EC_ON
PR420
2.2K_0402_1%
2013-05-14
<48,56,57> MAINPWON PD401
1 2
RB751V-40_SOD323-2
1
PC426
1U_0402_6.3V6-K
2
A A
5
Dr-Bios.com 4
Issued Date
3
2012/07/01

Custom

2
Title
PWR-3VALWP/5VALWP
!""#$%&'()*)
1
Sheet 59 of 69
Rev
1.0
A B C D
2013-05-16
PJ501 PC506 PR502
B+ 2 1 B+_1.35V 0.22U_0402_10V6-K 2.2_0603_5%
2200P_0402_25V7-K
2 1 1 2 1 2
47P_0402_50V8-J
68P_0402_50V8J
0.1U_0402_25V6
@ JUMP_43X79
10U_0805_25V6-K
10U_0805_25V6-K
1
1
PC519
PC504
PC505
PC502
PC503
PRFC36
+1.35VP
2
2
+0.675VSP
+0.675VSP
+1.35VP
BST_1.35V
DH_1.35V
LX_1.35V
PJ502
5
1 1
10U_0805_6.3V6-K
10U_0805_6.3V6-K
2 1
2 1
1
PC703
PC704
@ JUMP_43X118
PJ503 +1.35V
16
17
18
19
20
2
4 PU501 +1.35VP 2 1
2 1
PHASE
UGATE
BOOT
VLDOIN
VTT
PQ501 21 @ JUMP_43X118
SIS472DN-T1-GE3 PAD
DL_1.35V 15 1
1
2
3
LGATE VTTGND
1 2 2013-05-09
+1.35VP 14
PGND VTTSNS
2 +0.675VSP
5
PL501 PR503
0.68UH_PCMB063T-R68MS_16A_+-20% 6.19K +-1% 0402
PR504 1 2 CS_1.35V 13 3 PJ504
4.7_1206_5% CS RT8207MZQW_WQFN20_3X3 GND 2 1
+0.675VSP 2 1 +0.675VS
1 +5VALW +5VALW 12
1SNB_1.35V 2
4 4 VTTREF_0.675V
+ PC508 PR701 VDDP VTTREF JUMP_43X39
330U_D2_2V_R9M 5.1_0603_5% @
2
+5VALW 1 2 VDD_1.35V 11
VDD VDDQ
5 +1.35VP +1.35VP
680P_0603_50V7K
PGOOD
PQ502
1
2
3
1
SISA12DN-T1-GE3 +3VALW
TON
PC509
2013-05-09 PC701 PC702 PC507
FB
S5
S3
1U_0603_10V6K 1U_0603_10V6K 0.033U_0402_16V7K
2
2
100K_0402_1%
2
10
6
PR511
TON_1.35V
FB_1.35V
S5_1.35V
S3_1.35V
1
2 2
<48> VDDQ_PGOOD PR507

8.06K_0402_1%
1 2 +1.35VP
2013-07-08 PR506
887K_0402_1%
PC510
PR501 B+_1.35V1 2
0_0402_5% 1 2
1 2
<48> SYSON @
470P_0402_50V7K
2
+5VALW
47K_0402_5%
@
0.1U_0402_16V7-K
1
PC501
2013-04-18
PR505
2
1
2
PR509
100K_0402_5%
1
1
PR508
10K_0402_1%
PR510
2
1
49.9K_0402_1% D
<39,55,63> SUSP 1 2 2
G
PQ503
2N7002BKW_SOT323-3
2013-07-01
0.1U_0402_6.3V7-K
S
3
1
2013-04-18
PC511
3 3
4 4
A
Dr-Bios.com B
Deciphered Date

Custom
Date:
C
2014/07/01
Title
PWR-+1.35VP/+0.675VSP
D
!""#$%&'()*)
Sheet 60 of 69
Rev
1.0
5 4 3 2 1
2013-07-08
D D
PR601
<39,48,55,62> SUSP# 0_0402_5%
1 2
0.1U_0402_16V7-K
1
PR607
PC601
1M_0402_5%
2
1
PU601
SY8208DQNC_QFN10_3X3
PJ601
10U_0805_25V6-K
2 1 8 1 PC602
B+ 2 1 IN EN
0.1U_0402_25V6
0.1U_0603_25V7K
@ JUMP_43X79
BS
6 BST 1.5VS 1 2 +1.5VSP
1
PC606
PC604
9 10 SW 1.5VS 1 2
+3VS GND LX
2
4 PL601
FB
4.7_1206_5%
3 +3VALW 0.68UH_PCMB063T-R68MS_16A_+-20%
ILMT 7
BYP
PR610
PR605
22U_0805_6.3V6-M
22U_0805_6.3V6-M
22U_0805_6.3V6-M
22U_0805_6.3V6-M
2013-05-09 @ 0_0402_5% 2 1 1 1 1
2
PG
1
4.7U_0402_6.3V6-M
1 2 5
LDO
PC610
PC612
PC613
PC614
1
PC607
4.7U_0402_6.3V6-M
C 2 PR608 1 @ C
2
2 2 2 2
1
PC605
100K_0402_5% PC609
2
680P_0603_50V7K
2
PR606
0_0402_5%
@ @
330P_0402_50V7-K
1
30.1K_0402_1%
1
2013-05-09
PC611
PR603
2
2
20K_0402_1%
1
+1.5VSP PJ602 +1.5VS
PR604
2 1
2 1
@ JUMP_43X118
2
B B
A A
5
Dr-Bios.com
4
3
Deciphered Date
Custom
Date:
2014/07/01

2
Title
PWR-+1.5VSP
!""#$%&'()*)
Sheet
1
61 of 69
Rev
1.0
5 4 3 2 1
PR708
<39,48,55,61> SUSP# 0_0402_5%
0.1U_0402_6.3V7-K
1 2
0.1U_0402_16V7-K
PC705
1
2
2013-07-08
+3VS
PC713
2
2
D D
PR704
100K_0402_5%
B+
24
25
26
27
28
29
1
REFIN2
REFIN
VREF
RA
EN
GND2
68U_25V_M_R0.36
1
+5VALW +
PC711
23 1 PGOOD 1.05VS
GSNS PGOOD
22 2
PC706 VSNS LP# 2
PR705 2 1 21 3
0_0402_5% SLEW MODE
1 2 20
.01U_0402_25V7-K 4 PR707 PC712
1 2 TRIP NC 5.1_0603_5% 0.1U_0603_25V7K
@ PR702 19
GND1 BST
5 1
BST 1.05VS 2 1 2 +1.05VS_VCCPP
0_0402_5%
2 1 PC715 18 6 SW 1.05VS 1 2
PJ603 1U_0603_10V6K V5 SW1
2200P_0402_25V7-K
10U_0805_25V6-K
10U_0805_25V6-K
2 1 VIN 1.05VS 17 7 PL701
B+ 2 1 VIN3 SW2
1
68P_0402_50V8J
4.7_1206_5%
0.1U_0402_25V6
0.68UH_PCMB063T-R68MS_16A_+-20%
47P_0402_50V8-J
@ JUMP_43X79 16 8
VIN2 SW3
1
1
PC717
PC710
PC709
PC708
PR710
1
PC707
PRFC37
15 9
VIN1 SW4
22U_0805_6.3V6-M
22U_0805_6.3V6-M
22U_0805_6.3V6-M
PGND1
PGND2
PGND3
PGND4
PGND5
1 1 1
2
2
2
PC719
PC726
PC727
C @ C
TPS51363RVER_QFN28_3P5X4P5 2 2 2
14
13
12
11
10
1
2013-05-16 PU701 PC716
680P_0603_50V7K
2
@
DGPU_PWROK <19,27,54,63>
PR83110K_0402_5%
2 1 +3VS
+1.05VS_VCCPP PJ703 +1.05VS

2 1
2 1
@ JUMP_43X118
B B
PU702 PL702
1UH_PH041H-1R0MS_3.8A_20%
+5VALW 4 3 1.8VSP_LX 1 2
+5VALW IN LX +1.8VSP
1
22U_0805_6.3V6-M
22U_0805_6.3V6-M
4.7_1206_5%
1 1 PJ704
68P_0402_50V8J
PC728
PC720
5 2 +1.8VSP 2 1 +1.8VS
PG GND 2 1
1
PR717
1
PC723
@ 6 1
2 2 FB EN PR718 JUMP_43X39
2
20K_0402_1% @
22U_0805_6.3V6-M
22U_0805_6.3V6-M
SY8032ABC_SOT23-6 1 1
2
1
PC724
PC725
PC722
PR703
0_0402_5% 680P_0603_50V7K
2
SUSP# 1 2 EN_1.8VSP 2 2
0.1U_0402_6.3V7-K
2
2013-07-08
1
PC721
PR716
1
1M_0402_5% @
2
PR719
1
10K_0402_1%
2
A A
5
Dr-Bios.com 4
3
Deciphered Date

Custom

2014/07/01
2
Title
PWR-+1.05VS_VCCPP/+1.8VSP
!""#$%&'()*)
Sheet
1
62 of 69
Rev
1.0
A B C D
NVVDD_PWM_VID <23>
DPRSLPVR_VGA <23>
+VGA_CORE Under VGA Core GB4-128 package NVDD_PWR_EN <14>
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
1
1
+VGA_B+
PC834
PC835
PC836
PC837
PC838
PC839
PC840
PC1209
PC1210
PC1211
PC1212
PC1213
PC1214
PC1215
2013-05-16 PL1202
HCB2012KF-121T50_0805
2
1 2 B+
1
PL1203 1
HCB2012KF-121T50_0805
2200P_0402_25V7-K
RB751V-40_SOD323-2
1 2
10U_0805_25V6-K
10U_0805_25V6-K
27.4K_0402_1%
47P_0402_50V8-J
0.1U_0402_25V6
0.1U_0402_6.3V7-K
0.1U_0402_6.3V7-K
0.1U_0402_6.3V7-K
0.1U_0402_6.3V7-K
0.1U_0402_6.3V7-K
1
2
1
1
1
PC819
PC818
PC817
PC816
PD801
PR864
PC802
PC805
PC806
PC807
PC808
PRFC38
SIR472DP-T1-GE3
PQ804
2
2
2
1
PC2428
470P_0402_50V7K
4
1
+VGA_CORE Near VGA Core @ PR821

0_0603_5%
PC809
0.22U_0603_10V7K
3
2
1
2 2 1BOOT1_2_VGA 1 2
+3VS
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
2013-07-08 +VGA_CORE
2200P_0402_25V7-K
10K_0402_5%
22U_0805_6.3V6-M
47U_0805_6.3V6M
1
1
2013-07-08
PC824
PC825
PC826
PC827
PC1216
PC1217
PC1218
PC1219
PC1220
PC1221
PC1222
PC1223
1 4
BOOT1_VGA
0_0402_5%
0_0402_5%
1
5
PC830
2 3
2
1
2
4.7_1206_5%
@
330U_B2_2.5V_M_R9M
330U_B2_2.5V_M_R9M
PQ805 PL802
PR1212
@ @ @ @ @ @ @
PR836
1 1
PR835
PR837
SIRA06DP-T1-GE3
LGATE1_VGA 4
1SNUB1_VGA 2
+ +
PC811
PC812
N14PGV2@ N14PGV2@
1
PR832 PR833 @
PR833 PR844 2 2
PSI_VGA
20K_0402_1% 20K_0402_1% GPU_VID UGATE1_VGA
EN_VGA
PR812
3
2
1
VREF 2 1 2 1VIDBUF 10K_0402_5%
PR834 PR832 PR846
1
PC1224
2
PHASE1_VGA
PR834 680P_0402_50V7-K
2K_0402_1%
2
6
1
PR844 PR846 N14PGV2@
0_0402_5% 18K_0402_1%
VIDBUF
PSI
HG1
VID
BST1
EN
2
2 3K_0402_1% 39K_0402_1% 30K_0402_1% 3K_0402_1% 24K_0402_1% 2 1 2 1 @ 2
N14MGL@ N14MGL@ N14MGL@ N14MGL@ N14MGL@ N14PGV2@ N14PGV2@

1 2 7 24
PC855 REFIN PH1
PRV11 = 71.5K ==>Fsw = 450KHz PC854 2200P_0402_25V7-K PC815
1 2 VREF 8 PU801 23 4.7U_0603_10V6
PR849 VREF LG1
0.01U_0603_50V7K 2 1 FS 9 NCP81172MNTWG_QFN24_4X4 22 1 2
PR859 0_0402_5% 34K_0402_1% FS PGND
<24> VSSSENSE_VGA 1 2 10 21 PVCC_VGA 1 2 +5VS

FBRTN PVCC
PR852 FB_VGA 11 20 PR843 0_0402_5%
FB LG2
1
PC853 PC863 51_0402_1% PC843 10P_0402_50V8-J +VGA_B+

1000P_0402_50V7-K 1 2FB1_VGA1 2 1 2 COMP_VGA 12 19 2013-07-08 2013-05-16
TALERT#
COMP PH2
PGOOD
2
TSNS
47P_0402_50V8-J
BST2
GND
VCC
HG2
<24> VCCSENSE_VGA 1 2 1 PR854 2 1 2FB2_VGA1 2
2200P_0402_25V7-K
10U_0805_25V6-K
10U_0805_25V6-K
47P_0402_50V8-J
0.1U_0402_25V6
5
PR865 0_0402_5% 10K_0402_1% PC841 PR845 1
25
13
14
15
16
17
18
1
PC858
PC859
PC860
PC861
SIR472DP-T1-GE3
100P_0402_50V8J 82K_0402_1% PQ806
PRFC39
BOOT2_VGA
VCC_VGA
2
2
UGATE2_VGA UGATE2_VGA 4
100K_0402_1%_NCP15WF104F03RC
0.1U_0402_6.3V7-K
DGPU_PWROK <19,27,54,62>
1
1
PC865
PR858 5.9K_0402_1%
PR857 PC862
3
2
1
0_0603_5% 0.22U_0603_10V7K
PH801
2 1 BOOT2_2_VGA 1 2
2
PR853 2.2_0402_5% +VGA_CORE

2 1 +5VS
2
PHASE2_VGA 1 4
2
1U_0402_10V6K
5
2 3
2
1
PC856
4.7_1206_5%
Thermistor near MOSFET
1
330U_B2_2.5V_M_R9M
330U_B2_2.5V_M_R9M
PQ807 @ PL801
trigger point 97 degree C.
PR1207
VREF
1 1
SIRA06DP-T1-GE3
3 LGATE2_VGA 4 3
1SNUB2_VGA 2
+ +
PC866
PC867
N14P-GT 35W N14P-GS 25W 2 2
3
2
1
PR840 10K_0402_5%
Ipeak=50A Ipeak=36A 2 1 +3VS
PC1225
Imax=35A Imax=25A 680P_0402_50V7-K
2
MDU1512, Rdson(max)=5mohm
Iocp=64.8A Iocp=64.8A @
Fsw=450KHz Fsw=450KHz
bulk cap 330uF 9m *4 bulk cap 330uF 9m *3
2011_1007
N13M-GE1 +1.05VS +1.05VS_VGA PJ802
VID: 0110100 2 1
+1.05VS 2 1 +1.05VS_VGA
0.85V +5VALW 8 1
7 2 @ JUMP_43X118
1
2
10U_0805_6.3V6-K
6 3
1
1
PC803
PC801 5 PC810
10U_0805_6.3V6-K PR813 PR813, PQ803 and PR815 --> "Stuff"
2
2
1U_0603_10V6-K
TPC8A03-H_SO8PQ802
TPC8A03-H_SO8PQ802 75_0603_5%
4
PR814 PR815
1
20K_0402_1% 0_0402_5%
PR816 1 2 DGPU_PWROK#
1
100K_0402_5% D PQ803
SUSP
1
1 2 2 1 2
1
PC804 G
PR818 2011_0727 PR816 0.01U_0603_50V7K S PR817 @
3
0_0402_5% modfiy 10K to 100K. 2N7002BKW_SOT323-3 0_0402_5%

2
<54> DGPU_PWROK# 1 2
4 4
1
<39,55,60> SUSP SUSP 1 2 2 PQ808
Dr-Bios.com
G 2N7002BKW_SOT323-3 2013-05-21
PR819 @ S
Confirm with HW
3
0_0402_5%
2013-04-18

Issued Date 2012/07/01 Deciphered Date 2014/07/01 PWR-VGA_COREP-ISL62883
Size
Document Number Rev
C 1.0
!""#$%&'()*)
A B C D
5 4 3 2 1
D D
PR903
162K_0402_1%
1 2 SWN3
PR902
220K_0402_5%_ERTJ0EV224J
165K_0402_1%
1 2
0.047U_0402_25V7-K
CSREF
75K_0402_1%
1200P_0402_50V7-K
470P_0402_50V7-K
20K_0402_1%
PR905
2
162K_0402_1%
1
PH901
PR901
PC901
PC902
PC904
PR907
1 2 SWN1
PR910
2
6.65K_0402_1%
2
1
CSP3 2 1
SWN3 <65>
Place close to
1000P_0402_50V7-K
phase 1 inductir
2
PC903
1
C CSREF <65> C
CSP3
0.047U_0402_25V7-K
CSREF
20K_0402_1%
CSP2
<48>
IMVP_IMON
2
1
PC906
PR909
CSP1
CSSUM
CPU_B+
DRON 1
T138 @
PR913
2
@ 6.65K_0402_1%
1
PR906 CSP1 2 1
SWN1 <65>
43K_0402_1%
2
2013-07-08 CSCOMP 1 2 37W=43K

PR918
1K_0402_1% 47W=66.5K
+5VALW
1
0_0402_5%
81103_PWM
PR952
37W=10K 1 2013-07-08
T137 @
1
47W=15.4K
2
PC914 PC913
1
.01U_0402_25V7-K
390P_0402_50V7-K 10P_0402_50V8-J PR917

2
1 2 1 2 1 2 PR912 10K_0402_1% PR914

1
PC912
PR920 23.7K_0402_1% PU901 PR915 PC907
27
26
25
24
23
22
21
20
19
0_0402_5%
49.9_0402_1% 1 2 NCP81103MNTWG_QFN36_5X5 2.2_0603_5% 0.22U_0402_10V6-K
1
37W=10K 1 2 1 2
CSCOMP
CSSUM
CSREF
CSP3
CSP2
CSP1
DRON
PWM2/IMAX
BST3
2
2
PC911
47W=7.5K 470P_0402_50V7-K CSP2 Mount for 37W
1 2 1 2 2 1 28 18
ILIM HG3 HG3 <65>
PR921 PR919 29 17
IOUT SW3 SW3 <65>
1K_0402_1% 10K_0402_1% 30 16 PC908
VRMP LG3 LG3 <65>
31 15 1 2 PR951 2013-07-08
32 COMP PVCC 14 0_0402_5%
33 FB PGND 13 2.2U_0603_10V7-K 1 2
1 2 VSN_1 1 2 VSN_2 34 DIFFOUT LG1 12
LG1 <65> +5VALW
VSN SW1 SW1 <65>
1000P_0402_50V7-K
PR922 PR924 35 11
VSP HG1 HG1 <65>
B 0_0402_5% 1K_0402_5% 36 10 B
<10,9> VSSSENSE VCC BST1
2
VRHOT#
VR_RDY
INT_SEL
TSENSE
PC915
ALERT#
1 2 PR916 PC909
ROSC
37 2.2_0603_5% 0.22U_0402_10V6-K
SCLK
SDIO
<9> VCCSENSE GND

PC916 1 2 1 2
EN
1
1 2 VSP 2200P_0402_25V7-K
PR923
1
2
3
4
5
6
7
8
9
0_0402_5% PR928
1 2 45.3K_0402_1%
VR_HOT#_1
+5VALW 1 2
TSENSE
VR_SVID_ALRT#_1
2.2U_0603_10V7-K
PR925 PR926
VR_SVID_DAT_1
VR_SVID_CLK_1
2_0603_5% 0_0402_5%
VR_RDY
2
PC917
1 2
<48> VR_ON
TSENSE
2
1 2
1
<48,56,57> VR_HOT# PC910

PR927 0.1U_0402_6.3V7-K
1
0_0402_5%
2
2013-07-08
PR929
52.3K_0402_1%
100K_0402_1%_NCP15WF104F03RC
1
+VCCIO_OUT 15K_0402_1%
2
1
2013-07-08
PR938
1.91K_0402_1%
PH802
1
1
75_0402_1%
130_0402_1%
0_0402_5%
54.9_0402_1%
2
PR931
PR930
2
PR933
PR934
PR932
Place close to
2
phase 2 MOSFET
2
PC918
1
PR935 0.1U_0402_6.3V7-K
1
A A
0_0402_5%
1 2 VR_SVID_DAT_1
Dr-Bios.com
<9> VR_SVID_DAT
+3VS
PR936
0_0402_5%
<15>
VGATE
1 2 VR_SVID_ALRT#_1
<9> VR_SVID_ALRT#
PR937
0_0402_5%
1 2 VR_SVID_CLK_1
<9> VR_SVID_CLK
2013-07-08
CPU_CORE
Rev
Custom 1.0
!""#$%&'()*)
5 4 3 2 1
5 4 3 2 1
D D
2013-05-16 CPU_B+
1 2
B+
2200P_0402_25V7-K
10U_0805_25V6-K
10U_0805_25V6-K
10U_0805_25V6-K
0.1U_0402_25V6-K
PL901
47P_0402_50V8-J
FBMA-L11-453215-800LMA90T_1812
SIR472DP-T1-GE3
PQ1001 1
1
PC920
PC921
PC922
PC923
PC924
PRFC40
PR939
2.2_0603_1%
2
2 1 4 2
<64> HG1
+VCC_CORE
3
2
1
PL902
0.36UH +-20% PCME103T-R36MSR 33A
1 4
<64> SW1
220P_0402_50V7-K
68P_0402_50V8-J
4.7_1206_5%
2 3
5
PC926
PC925
<64> LG1 2013-05-16
1
PR940
PQ1002 V1N_CPU
CPU_B+
2200P_0402_25V7-K
10U_0805_25V6-K
10U_0805_25V6-K
10U_0805_25V6-K
0.1U_0402_25V6-K
5
47P_0402_50V8-J
SIRA06DP-T1-GE3
68U_25V_M_R0.36
68U_25V_M_R0.36
4 2 1
1SNUB_CPU1
CSREF <64> 1 1
SIR472DP-T1-GE3
PQ1003 1
1
+ +
PC927
PC928
PC929
PC930
PC931
PC932
PC933
PR941 @ @
PRFC41
680P_0402_50V7-K
10_0402_1% PR942
2.2_0603_1%
SWN1 <64>
3
2
1
2
2 1 4 2 2 2
<64> HG3
PC919
C C
2
+VCC_CORE
3
2
1
PL903
0.36UH +-20% PCME103T-R36MSR 33A
1 4
<64> SW3
4.7_1206_5%
2 3
PR943
<64> LG3
PQ1004
2
PR944
SIRA06DP-T1-GE3
4 V3N_CPU 2 1 CSREF
SNUB_CPU3
10_0402_1%
SWN3 <64>
3
2
1
680P_0402_50V7-K
1
PC935
2
B B
A A
5
Dr-Bios.com 4 3
Deciphered Date
2
2014/12/05
Size
Title
CPU_CORE
Date:
Document Number

!""#$%&'()*)
1
Sheet 65 of 69
Rev
1.0
5 4 3 2 1
+VCC_CORE
1 1 1 1
D +VCC_CORE + + + +
D
PC1030 PC1031 PC1032 PC1033

330U_D2_2VM_R9M 330U_D2_2VM_R9M 330U_D2_2VM_R9M 330U_D2_2VM_R9M
2 2 @ 2 2
1 1 1 1 1
PC1001 PC1002 PC1003 PC1004 PC1005
10U_0805_6.3V6-K 10U_0805_6.3V6-K 10U_0805_6.3V6-K 10U_0805_6.3V6-K 10U_0805_6.3V6-K

2 2 2 2 2
1 1
+ +
1 1 1 1 1 1 PC1034 PC1035
PC1011 PC1010 PC1009 PC1008 PC1007 PC1006 330U_D2_2VM_R9M 330U_D2_2VM_R9M
2 2 @
10U_0805_6.3V6-K 10U_0805_6.3V6-K 10U_0805_6.3V6-K 10U_0805_6.3V6-K 10U_0805_6.3V6-K 10U_0805_6.3V6-K
2 2 2 2 2 2
+VCC_CORE
1 1 1 1 1
PC1016 PC1015 PC1014 PC1013 PC1012
22U_0805_6.3V6-M 22U_0805_6.3V6-M 22U_0805_6.3V6-M 22U_0805_6.3V6-M 22U_0805_6.3V6-M
2 2 2 2 2
C C
1 1 1 1 1
PC1017 PC1018 PC1019 PC1020 PC1021
2 2 2 2 2
1 1 1 1 1
PC1026 PC1025 PC1024 PC1023 PC1022
2 2 2 2 2
1 1 1 1
PC1027 PC1028 PC1029 PC1036
22U_0805_6.3V6-M 22U_0805_6.3V6-M 22U_0805_6.3V6-M 22U_0805_6.3V6-M
B 2 2 2 2 B
A A
5
Dr-Bios.com 4
3 2
Date:
Title
PWR-PROCESSOR DECOUPLING

Custom

!""#$%&'()*)
Sheet
1
66 of 69
Rev
1.0
A B C D
1 2013-05-16 1
PJ1202
+1.05VMP 2 1 +1.05VM
2 1
JUMP_43X39
@
47P_0402_50V8-J
47P_0402_50V8-J
1.05VMP max current=1A 1 1
PRFC55
PRFC56
2 2
PJ1201
+5VALW 2 1 1.05VMP_VIN
2 1 PU1201 PL1201
22U_0805_6.3V6-M
22U_0805_6.3V6-M
1 1 1UH_PH041H-1R0MS_3.8A_20%
JUMP_43X39 1.05VMP_LX
PC1207
PC1201
4 3 1 2
@ IN LX +1.05VMP
68P_0402_50V8J
@ 5 2
PG GND
1
2 2
680P_0603_50V7K 4.7_1206_5%
1
PC1202
6 1
FB EN
PR1201
PR1202
7.5K_0402_1%
22U_0805_6.3V6-M
22U_0805_6.3V6-M
PR1203 SY8032ABC_SOT23-6 1 1
1 2
PC1204
PC1205
0_0402_5%
1 2 EN_1.05VMP FB=0.6Volt
<48,53> VM_PWRON
PC1203
2 2
0.1U_0402_6.3V7-K
2
2
2013-07-08
1
PR1204 PC1206
2
1M_0402_5% 2
2
1
1.05VMP_FB
1
PR1205
2011_0923 JUMP form 43X79 change to 43X79 10K_0402_1%
2
3 3
4 4
A
Dr-Bios.com B
Deciphered Date
Custom
Date:
C
2014/07/01
Title
PWR-+1.05VMP
D
!""#$%&'()*)
Sheet 67 of 69
Rev
1.0
5 4 3 2 1
POWER PIR (Product Improve Record)

AILE1 NM-A151 SCHEMATIC CHANGE LIST
REVISION CHANGE: 0.1
GERBER-OUT DATE: 2013/01/16
NO DATE PAGE MODIFICATION LIST PURPOSE

---------------------------------------------------------------------------------------------------------------------
D
B+ D
+5VALW/8A RICHTEK +1.8VSP/2A

RICHTEK
Adaptor RT8243AZQW RT8068AZQW
WQFN20_3X3 WDFN10_3X3
+3VALW/6A SUSP#
EN
Switch Mode converter
PGOOD SPOK
EC_ON EN1 PAGE 62 PGOOD
FOR System VREG5 VL
EN2
PAGE 59 VREG3 +3VLP
RICHTEK +1.05VMP/2A
RT8068AZQW
RICHTEK
RT8207MZQW +1.35VP/12A VM_PWRON WDFN10_3X3
EN
WQFN20_3X3 converter
PAGE 67 PGOOD
Switch Mode +0.675VSP/2A
SYSON S5
FOR DDR3/3L
C
SUSP# S3 VDDQ_PGOOD C
PAGE 60 PGOOD
TI
BQ24737RGRR TI
TPS51212DSCR +1.5V/8A
Battery Charger SON10_3X3
Switch Mode Switch Mode
PAGE 58 SUSP# EN FOR FCH PGOOD
PAGE 61
TI
SMBus TPS51212DSCR +1.05VS_VCCPP/10A
SON10_3X3
Switch Mode
SUSP# EN FOR FCH PGOOD
B
PAGE 62 B
Battery ONSEMI
Li-ion NCP81172MNTWG_
QFN24_4X4 +VGA_CORE/40A
NVVDD_PWM_VID VIDs
Switch Mode
NVDD_PWR_EN EN FOR GPU VDDC PGOOD DGPU_PWROK
PAGE 63
ONSEMI
NCP81103MNTWG +CPU_CORE/56A
QFN36_5X5
Switch Mode
VR_ON FOR CPU Core
A
EN PGOOD VGATE A
PAGE 64
5
Dr-Bios.com 4
3 2
Title
Date:
HW-PIR
Custom
!""#$%&'()*)
1
Sheet 68 of 69
Rev
1.0
5 4 3 2 1
HW PIR (Product Improve Record)

AILE1 NM-A151 SCHEMATIC CHANGE LIST
REVISION CHANGE: 0.1
GERBER-OUT DATE: 2013/01/16
NO DATE PAGE MODIFICATION LIST PURPOSE

D
--------------------------------------------------------------------------------------------------------------------- D
01) 03/14 10 R64 Change R64 BOM structure from "@" to "DS3@" For Deep S3 Function
C C
B B
A A
5
Dr-Bios.com
4
Compal Secret Data
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3 2
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Date:
Compal Electronics, Inc.

Custom
PIR (PWR)
Y490-LA8691P
1
Sheet 69 of 69
Rev
1.0

NM A161

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NM A161

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A B C D E

NM-A161 Rev1.0 Schematic 2

Intel Haswell Processor with DDRIII + Lynx point PCH

Size Document Number

1.35V DDRIIIL 1066/1333/1600 MT/s

CRT Conn. CRT USB 3.0 USB Left

2 Realtek RTL8111G JRJ45 Conn. PCIe Gen1

LAN Board PCIe port 4 Page 42

Voltage Rails ( O --> Means ON , X --> Means OFF )

EHCI2 8 KBL@ K/B Light part

Main 2nd WLAN Thermal PCH CP Port Device

Device Device Address Device Address

Hot plug detect for IFP link E

GPIO0 OUT - GPU VID4 N13X

GPIO2 OUT - VGA_BL_PWM

GPIO13 OUT - GPU VID5

GPIO14 OUT - FB_CLAMP_TOGGLE_REQ#

FB Memory (GDDR5) ROM_SI

1. all power rail ramp up time should be larger than 40us

Other Power rail

VGA Notes List

Reserve for VCCST

+VCCIO_OUT DDR3 COMPENSATION SIGNALS

INTEL_HASWELL_HASWELL 2 OF 9 XDP_TCLK RC17 1 2 51_0402_1%

XDP_TRST# RC18 1 2 51_0402_1%

XDP_DBRESET# RC9 1 2 1K_0402_1%

PU/PD for JTAG signals

SM_DRAMPWROK Topology for platforms supporting Deep S3

B 4 DRAMPWROK_AND RC22 1 2 0_0402_5% SM_DRAMPWROK

SM_DRAMPWROK rise and fall time must be < 50ns

Size Document Number

Thursday, July 11, 2013

JCPU1H ME@Haswell rPGA EDS HPD INVERSION FOR EDP

CFG STRAPS For CPU

49.9_0402_1% AL30 AP21

B35 RSVD_TP_11 RSVD_21 G6

PEG DEFER TRAINING CFG7 RC32 1 @ 2 1K_0402_1%

Date: Thursday, July 11, 2013

Haswell rPGA EDS +VCC_CORE

0_0603_5% AM23 VSS_13 VCC_84 AJ33

Y32 VCC_8 VCC_99 V25

Thursday, July 11, 2013

D JCPU1F Haswell rPGA EDSME@ Haswell rPGA EDSME@

A10 AK34 B34 K10

DDR3 SO-DIMM A DDRA_DQS[0..7] <7>

<7> DDRA_CKE0 DDRA_CKE0 73 74 DDRA_CKE1 1

133 134 CD20 CD21 2.2U_0402_6.3V6-M

1 1 203 204 +0.675VS

DDR3 SO-DIMM B DDRB_DQ[0..63] <7>

+1.35V +1.35V DDRB_DQS#[0..7] <7>

<7> DDRB_CKE0 DDRB_CKE0 73 74 DDRB_CKE1

133 134 CD43 CD44

JCMOS, JME Setting, Need Under DDR Door

HDA AUDIO SIGNAL

HDA AUDIO For Codec HDA STRAP

A RH128 1 2 0_0402_5% @ R422 RH27 1 @ 2 1K_0402_5% HDA_SYNC A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/12/05 Deciphered Date 2014/12/05 PCH_RTC/HDA/SATA

PCH_HDMI_CLK RH28 1 2 2.2K_0402_5%

PCH_DOCK_CLK RH136 1 2 2.2K_0402_5%

A16 swap overide Strap/Top-Block For ESD

RH57 1 2 10K_0402_5% SUSWARN#_R

+1.5VS BE16 AU42