LCFC NM-D711 r0.1

A B C D E
1 1
LCFC Confidential
HY568 M/B Schematics Document
2 2
Tiger Lake H-Processor with DDR4 + NV GN20-E GPU
2020-10-10
3
REV:0.1 3
4 4
Security Classification LC Future Center Secret Data Title
Issued Date 2021/04/07 Deciphered Date 2021/04/07 Cover Page
A
Vinafix.com
B
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C D
Date:
Document Number
Custom
HY568
Wednesday, April 07, 2021 Sheet
E
1 of 110
Rev
0.1
A B C D E
VBOIS ROM Memory BUS (DDR4 non-ECC)

2MB
Channel B DDR4-SO-DIMM x1
Page 25 Page 12,13
1.2V DDR4 3200MT/s

UP TO 16G x 1
Memory BUS
nVidia GN20-P0/P1 Channel A
HDMI Conn.
N18P-G61-A
DDR4-SO-DIMM x1
Page 12,13
1
Page 44 PCI-Express 8x Gen4 1.2V DDR4 3200 MT/s 1
GPIO3 MUX_CNTL Intel CPU UP TO 16G x 1

GDDR6*4 6/8GB
Page 33~38
eDP x4 Lane Tiger Lake H 45W PCI-Express 4x Gen4 SSD M.2 Conn. Port1
I2CB
BGA-1787
eDP x4 Lane 50mm*26.5mm
MUX
eDP Conn
eDP x4 Lane PS8461E
PS8361E
for 8.1G
for 5.4G
Page 5~13
FHD Page 60 Burnside Bridge USB2.0 1x
Page 39 TBT Retimer USB-C Port1(Back side) (PCH)
Burnside Bridge USB2.0 1x

TBT Retimer USB-C Port1(Left) (PCH)
2 DMI *8 2
USB 3.1 1x
USB2.0 1x USB-A Right
PCIe 4x Gen3
SSD M.2 Conn. Port2
/Optane Memory USB Back (AOU port x1)
USB3.1 3x
Page 45 PCIe Port 17-20 SATA Gen3 Intel PCH USB3.1 Port1 USB2.0 Port1
USB2.0 3x
USB Back port x2
Card Read conn
USB IO board
for 17"
PCIe 1x
Tiger Lake H USB3.1 Port2 USB2.0 Port2
Page 51 USB2.0 1x
LAN Realtek EC IT8176 int. keyboard
PCIe 1x
RJ45 Conn. RTL8111H-CG
Page 53 PCIe Port14
FCBGA-943
Int. Camera USB2.0 1x 25mm*24mm
Page 39 USB2.0 Port6
USB 2.0 1x
HDD Conn SATA Gen3
3 M.2 Card (WLAN&BT) 3
Page 61 SATA Port0 PCIe 1x PCIe Port13 USB2.0 Port10
USB2.0 1x
Touch Pad CNVio Page 54
IIC M.2 CRF Module
Page 51 HD Audio
Page 14~22
SPI BUS SPI ROM
USB2.0 PORT7 16MB+8MB
Page 18
eSPI
SPK Conn. Codec
Page 56 ALC3306
Page 55
SMBUS EC
int. DMIC conn ITE IT8227-LQFP128
Page 51 Page 50
HP&Mic Combo Conn.

Page 55
Battery Thermal Sensor Thermal Sensor CPU FAN

4 4
F75303M F75303M GPU FAN
Page 67 Page 58 Page 58 Page 58
I2C
Reserved
RGB KB conn
LC Future Center Secret Data Title
for RGB SKU Security Classification
A
Vinafix.com
B
Page 63
C
Issued Date 2021/04/07 Deciphered Date 2021/04/07
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D
Size
C
Date:
Block Diagram
Document Number
HY568
Wednesday, April 07, 2021
E
Sheet 2 of 110
Rev
0.1
5 4 3 2 1
B+ +5VLP/
Richtek
Adaptor RT6585C +5VALW/20A
EC_ON_3VALW_R EN1 Switch Mode
ALW_PWRGD
100W/TYPEC FOR SYS PGOOD
Page 91
D
300W/Wall-Plug D
EC_ON_5VALW_R EN2 +3VL/100mA
+3VALW/8A ANPEC
APL5934 +2.5V/1A
SYSON EN LDO
FOR DDR PGOOD
Richtek Page 93
+1.2V/11.4A
RT8231A
Switch Mode +0.6VS/1.1A
SYSON_VDDQ S5 FOR DDR Richtec
SM_PG_CTRL S3 Page 93 PGOOD +0.95VGS/3.5A
RT8068
0.95V_MAIN_EN EN Converter
FOR GPU PGOOD 0.95VGS_PG
Page 103
TI MPS
B+
BQ24800RUYR MP2950+MP86941 +VCCIN/61A
Switch Mode
Battery Charger FOR CPU Core
CPUCORE_ON EN
Page 95 PGOOD CPU_PWRGD
C
Switch Mode C
Page 89
AOS
AOZ2264VQI VCCIN_AUX/18A
Converter
VCCIN_AUX_EN EN FOR CPU PGOOD
SMBus Page 96
Silergy
SY8288 +1.8VALW/ 8A
Converter
EC_1.8VALW_EN EN FOR PCH PGOOD
Page 97
AOS
AOZ2264 VCCIN_AUX_PCH/10A
Converter
VCCIN_AUX_EN EN FOR PCH PGOOD
Page 99
B B
Battery
Li-ion ON
NCP81610+NCP303150 NVVDD/115A
60Wh/80Wh Switch Mode
NVVDD_EN EN FOR GPU NVVDD PGOOD NVVDD_PWRGD
Page 102
Richtek
RT8816 FBVDDQ/ 36A
Switch Mode
FBVDDQ_PWR_EN EN PGOOD FBVDDQ_PWROK
FOR GPU
Page 107
AOS
AOZ2151 +10V/4A
Converter
SUSP_N EN
A FOR Fan & Audio A
Page 90 PGOOD

Issued Date 2020/09/16 Deciphered Date 2020/09/16 Power Diagram
5
Vinafix.com
4 3
2
Size
Custom
Date:
Document Number
HY568 INTEL
1
Sheet 3 of 110
Rev
0.1
5 4 3 2 1
+3VS
DDR DIMMA
+3VALW_AG
DDR DIMMB
+3VS 2.2K
+3VALW_PCH
AG Controller Thermal Sensor

IT8176 or IT8258 2.2K F75303M 2.2K
UI22 or UI1 2.2K
Dual MOS
U134
+3VALW_SYS
Vcore controller
RGB MP2950GVT PCH_SMBDATA
PCH_SMBCLK 3VALW_TBTA
2.2K
Dual MOS Dual MOS PU2901 JHL8040RSLMNx
D D
UU3 and UU8

2.2K
+1.8VALW
EC_SMB_CK0
EC_SMB_DA0
2.2K
Isolator
+3VALW_R
Change IC
Battery BQ24800RUYR
JBATT1 PU5401
2.2K SML0DATA
SML0CLK
VINA_3V3
SN2001024YGBR
UU125 and UU127
+1.8VS_AON 2.2K
EC EC_SMB_CK1
EC_SMB_DA1 +1.8VALW
2.2K
VGA( UG1 ) 2.2K
Isolator
UE1
IT8227E +3VS
VGA_SMB_CK2
VGA_SMB_DA2
Thermal sensor NVDD controller
F75303M PAC1934T-I
+1.8VS_AON PU7902 NCP81610AMNTXG
Dual MOS Control
US1 PU2007(Reserved) CPU_SMB_CK0
2.2K CPU_SMB_DA0
PCH
+3VS
C
eDP MUX C
EC_SMB_CK2
Elan TP Synaptics TP PWR memory PS8461
EC_SMB_DA2 UH1 PK09000C190 PK09000G920 PU3002 UV12 (Reserve)
+3VALW_R TGL-H 2.2K
PD Controller 1 PD Controller 2
SN2001024YGBR SN2001024YGBR
2.2K
UU125 UU127
PCH_I2C1_SCL
PCH_I2C1_SDA
EC_SMB_CK4
EC_SMB_DA4
Del AMP
SMBUS Control Table
SOURCE VGA BATT IT8226E SODIMM WLAN Thermal PCH TP Charger RGB KB USB-C HiFi Audio Anti-ghost
WiMAX Sensor Module Backlight PD
EC_SMB_CK0 IT8226E V V
EC_SMB_DA0 +3VALW X X X X X X X X X X X PCH_I2C2_CLK
+5VS +3VALW_AG PCH_I2C2_SDA
EC_SMB_CK1 IT8226E X V V X X X X X V X X X X
EC_SMB_DA1 +3VALW_R +3VALW_R +3VALW_R +3VALW_R
EC_SMB_CK2 IT8226E V X V X X V V X X X X X X
+3VS
EC_SMB_DA2 +3VS +1.8VS_VGA +3VS Reserve +3VALW_PCH
PCH_SMBCLK V V
PCH X X X X X X X X X X X
PCH_SMBDATA +3VALW_PCH +3VS +3VS
B
PCH_RGBKB_SCL V B
PCH_RGBKB_SDA X X X X X X X X X X +LDO_3V3 X X X +3VS

EC_SMB_CK0 IT8226E V
+3VALW
EC_SMB_DA0 X X X X X X X X X X +5VS X X
GPU PWR Monitor

2.2K
EC SM Bus1 address EC SM Bus2 address PCH SM Bus address PCH I2C 2 Bus address PU7801
Device Address Device Address
Device Address Device Address
DDR DIMMA 1010 000X b RGB Backlight Need to update
Smart Battery 0X16 Thermal Sensor F75303M 1001_100x b
DDR DIMMB 1010 010X b
Charger 0001 0010 b VGA 0x9E (default)
TP Module Need to update +1.8VS_VGA
PCH Need to update
Wlan Reserved
Thermal Sensor NCT7718W 1001100xb
2.2K
Dual MOS
GPU I2CC_SCL
I2CC_SDA +1.8VS_VGA
EDP 2.2K
UG1
GN20-E3/E5
+1.8VS_VGA
2.2K
Dual MOS
A A
I2CB_SCL
I2CB_SDA
Security Classification
Vinafix.com Issued Date 2021/04/07 Deciphered Date 2021/04/07 Blank4

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
E
HY568 0.1
Date: Wednesday, April 07, 2021 Sheet 4 of 110

5 4 3 2 1
5 4 3 2 1
GN20x-P/N18P-G61-A GPIO H=High: Tied to 1.8V

M=Middle: Tied to 0.9V
GPIO I/O GPIO Name Function Description Net name I/O Termination
L=Low: Tied to 0V FS_OVERT# FUNCTION ENABLE
GPIO0 OUT NVVDD_PWM_VID PWM Output to control NVVDD NVVDD_PWM_VID
STRAP2 STRAP1 STRAP0 RAMCFG[4:0] GN20x-P/N18P-G61-A VRAM ROM_SO ROM_SI ROM_SCLK SOR_EXPOSED[3:0]
GPIO1 OUT GC6:GC6_FB_EN FB Enable for GC6 FB_GC6_EN (10K PD) Samsung
L L L 0 (0x0000) K4Z80325BC-HC14 L L L N18P-G61-A ENABLE OVERT*
GPIO2 IN GC6:GPU_EVENT* Wake the GPU from GC6 state GPU_EVENT#_R (10K PU) Micron
L L H 1 (0x0001) MT61K256M32JE-14:A L L H GN20x-P ENABLE OVERT*
D GPIO3 OUT DISP_MUX_CNTL Display MUX control signal GPU_MUX_CNTL (10K PD) Hynix Only For GN20x-P D
L H L 2 (0x0002) H56C8H24AIR-S2C
MSVDD_EN GN20x-P GPU power sequencing for GC6 ---MSVDD_ENGPIO4_GC6_MSVDD_EN
GPIO4 OUT 1V8_MAIN_EN N18P-G61-A 1V8_MAIN_EN 1V8_MAIN_EN (10K PU)
L H H 3 (0x0003)
GPIO5 OUT FRAME_LOCK* Active low Frame Lock for NVSR panel UNUSED
H L L 4 (0x0004) BOM NOTE:
GPIO6 OUT NVVDD_PSI* Phase Shedding, NVVDD_PSI NVVDD_PSI (10K PU) RSVD
1.BOM Structure：
H L H 5 (0x0005) GN20x-P1/P0-->GN20@
GPIO7 OUT LCD_BL_PWM LCD Panel Backlight PWM GPU_EDP_PWM (100K PD)
H H L 6 (0x0006) N18P-G61-A-->N18P@
GPIO8 OUT MEM_VDD_CTL Memory voltage Control FBVDDQ_SEL (10K PD)
H H H 7 (0x0007) 2.1.0V_GS voltage different：need Power setting
GPIO9 I/O THERM_ALERT* Active Low Thermal Alert VGA_ALERT# (10K PU)
L L M 8 (0x0008) GN20x-P1/P0-->0.95V
GPIO10 OUT MEM_VREF_CTL Memory VREF Control MEM_VREF_CTL (100K PD)
N18P-G61-A-->1.0V
L M L 9 (0x0009)
GPIO11 OUT LCD_VDD LED Panel power enable GPU_EDP_ENVDD (10K PD)
L M H 10 (0x000A) 3.VBIOS ROM partnumber need BOM control
GPIO12 IN PWR_LEVEL AC power detect or power supply overdraw input VGA_AC_DET_R (10K PU)
GN20x-P1/P0-->2MB PN:SA0000AU500
L H M 11 (0x000B) N18P-G61-A-->1MB PN:SA000080E00
GPIO13 IN IGPU_BL_EN Signal indicating when the IGPU has EN the BL iGPU_EDP_ENBKL (100K PU)
M L L 12 (0x000C)
GPIO14 IN HPD_IFPA* Hot Plug Detect for IFPA IFPA_HPD (10K PU)
4.ROM_SO,ROM_SI,ROM_CLK setting
M L H 13 (0x000D) GN20x-P1/P0-->LLH
GPIO15 IN HPD_IFPB* Hot Plug Detect for IFPB IFPB_HPD (10K PU) N18P-G61-A-->LLL
C C
GPIO16 OUT DISP_MUX_PWM_CNTL Allows switching the PWM between IGPU & DGPU PWM_SW_SELECT (10K PD)
5.VRAM_FB(RG702 STUFF package 0402)
GPIO17 IN HPD_IFPD* Hot Plug Detect for IFPD GPU_EDP_HPD (10K PU) BOM Structure Control Table GN20x-P1/P0 :2.49K ohm（PN:SD03424918J）
GPIO18 IN HPD_IFPE* Hot Plug Detect for IFPE UNUSED
BOM Structure BTO Item N18P-G61-A: 49.9 ohm（PN:SD034499A8J）
@ Not stuff
GPIO19 OUT UNUSED OPT@ GN20-P1/P0 N18P-G61 Stuff 6.+FUSE_1V8
GN20@ GN20P1/P0 Stuff GN20x-P1/P0 :RG1200:10K CG1104:1U
GPIO20 OUT UNUSED
N18P@ N18P-G61 Stuff N18P-G61-A: RG1200:2.21K CG1104:2.2U
GPIO21 OUT LCD_BLEN LCD Panel Backlight Enable GPU_EDP_ENBKL (100K PD)
GPIO22 OUT ADC_MUX_SEL OVRM MUX Input SEL ADC_MUX_SEL (2.2K PU)
GPIO23 OUT UNUSED UNUSED test point
GPIO24 IN HPD_IFPF* Hot Plug Detect for IFPF UNUSED
GPIO25 OUT FBVDD_PSI Turns off phases of the Frame buffer power supply FBVDDQ_PSI test point
1:SMB_ALT_ADDR ENABLE
ROM_WP* GN20x-P Connect to WP pin of the GPU EEPROM GPIO26_ROM_WP (10K PD) STRAP5 STRAP4 STRAP3 SMB_ALT_ADDR DEVID_SEL PCIE_CFG VGA_DEVICE
GPIO26 OUT FP_FUSE N18P-G61-A Control FP_FUSE GPIO26_FP_FUSE (10K PD) 0:SMB_ALT_ADDR DISABLE
M H H 1 1 1 1
GPIO27 IN HPD_IFPC* Hot Plug Detect for IFPC IFPC_HPD (10K PU) 1:DEVID_SEL REBRAND
M H L 1 1 1 0 0:DEVID_SEL ORIGNAL
B B
M L H 1 1 0 1 1:PCIE_CFG LOW POWER

GN20x-P/N18P-G61-A Power Sequence 0:PCIE_CFG HIGH POWER
M L L 1 1 0 0
1:VGA_DEVICE ENABLE
L H M 1 0 1 1
0:VGA_DEVICE DISABLE
PLT_RST_VGA_N PLT_RST_VGA_N L M H 1 0 1 0
PXS_PWREN L M L 1 0 0 1
PXS_PWREN For N18P-G61-A
L L M 1 0 0 0
+1.8VS_AON +0.95VGS
H H H 0 1 1 1
+1.8VS_VGA(VPP) NVVDD
H H L 0 1 1 0
NVVDD FBVDDQ
+1.8VS_VGA(VPP) H L H 0 1 0 1
+0.95VGS
VGA_PWRGD H L L 0 1 0 0
FBVDDQ
L H H 0 0 1 1
VGA_PWRGD
L H L 0 0 1 0
1. The ramp time for any rail must be more than 40us 1. For GDDR6, VPP must be equal to or higher than
A and is recommended to be less than 2ms. FBVDD/Q at all times;use gate logic and discharge L L H 0 0 0 1 DEFAULT A
circuit as needed
2. It is recommended that the delay from 1V8 on to
PEXVDD/GPU_PGOOD assertion not exceed 20ms. 2. All 3.3V devices that connect to the GPU must be L L L 0 0 0 0
ramp down before 1V8; GPU can NOT have any 3.3V
3.The ramp-up overshoot should not exceed the silicon leakage path after 1V8 power down.
reliability limit voltage.
3. Power down of PEXVDD must be less than 10% before
4. Power up NVVDD must be 90% before PEXVDD can NVVDD can start ramp-down.
ramp-up.
Security Classification LCFC Highly Confidential Information Title
5. Refer to the JEDEC Memory SPEC for memory-related power sequencing.
Issued Date 2021/04/07 Deciphered Date 2021/04/07 N18E VGA Notes List
7. FBVDD/Q, USB_VDDP and 1V8_AON don't need power cycle for GC6
Vinafix.com
C
HY568 0.1

5 4 3 2 1
A B C D E
Voltage Rails ( O --> Means ON , X --> Means OFF )

SIGNAL
+5VS STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
+3VS
Samsung VRAM
BOARD ID LLL--RG194/RG193/RG192
Power Plane VCCIO
Full ON HIGH HIGH HIGH HIGH ON ON ON ON
UG4 SAM8GbX4@ UG5 SAM8GbX4@ UG6 SAM8GbX4@ UG7 SAM8GbX4@ RG194 SAM8GbX4@ RG193 SAM8GbX4@
VCCSA S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW RH1195 17@ RH1195 HY568P@ RH1196 15@
VCCSTG board ID HY568-15-

S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF GN20P0----001100 ZZZ3 X76SAM8GbX4@
+3VALW HY568-17-
Samsung 8Gb VRAM
SA00009L430
Samsung 8Gb VRAM
SA00009L430
Samsung 8Gb VRAM
SA00009L430
Samsung 8Gb VRAM
SA00009L430
1/20W_100K_1%_0201
SD04110038J
1/20W_100K_1%_0201
SD04110038J
VCCCPUCORE S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
B+ +3VALW_PCH +1.2V VCCGFXCORE
S RES 1/20W 10K +-5% 0201S RES 1/20W 10K +-5% 0201S RES 1/20W 10K +-5% 0201
GN20P0----010100
SD04310028J SD04310028J SD04310028J HY568-15-GN20P1----001101
S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF RG192 SAM8GbX4@
+5VALW +1.8VS_VGA
RH1197 15@ RH1197 HY568P@ RH1198 17@
HY568-17-GN20P1----010101 Samsung 8Gb VRAM
HY568P----GN20P0---011100 X764CU12001
+1.8VGS
HY568P----GN20P1---011101
State BOM Structure Control Table HY568-15-N18P--------001110
NVVDD 1/20W_100K_1%_0201
BOM Structure BTO Item BOM Structure BTO Item HY568-17-N18P--------010110 SD04110038J
+1.0VGS S RES 1/20W 10K +-5% 0201S RES 1/20W 10K +-5% 0201S RES 1/20W 10K +-5% 0201 HY568-15-P0-D---------001111
@ Not stuff MIRROR@ MIRROR
SD04310028J SD04310028J SD04310028J
FBVDDQ 15@ HY568 15'' Stuff N18EG0@N18EG1@ GPU part Hynix VRAM LHL--RG194/RG188/RG192
1 1
17@ 17'' stuff NOMIRROR@ 17'' stuff
RH1201 N18P@ RH1201 GN20P0D@ RH1202 GN20P0@ RH1202 GN20P1@ UG4 H8GbX4@ UG5 H8GbX4@ UG6 H8GbX4@ UG7 H8GbX4@ RG194 H8GbX4@ RG188 H8GbX4@
7000P@ 7000P stuff NPI@ SPI VCC diode stuff
S0 O O O O O 7502M@ 7502 stuff OPT@ For NV GPU part
ZZZ4 X76H8GbX4@
8111GUL@ LAN Chip 8111GUL part OPTANE@ Optane memory support part
S RES 1/20W 10K +-5% 0201S RES 1/20W 10K +-5% 0201S RES 1/20W 10K +-5% 0201S RES 1/20W 10K +-5% 0201 Hynix 8Gb VRAM Hynix 8Gb VRAM Hynix 8Gb VRAM Hynix 8Gb VRAM 1/20W_100K_1%_0201 1/20W_100K_1%_0201
8111H@ LAN Chip 8111H part SA0000B4E10 SA0000B4E10 SA0000B4E10 SA0000B4E10 SD04110038J SD04110038J
S3 O O O O X AG@ Anti-ghost TPM@ For support TPM sku part
SD04310028J SD04310028J SD04310028J SD04310028J
Hynix 8Gb VRAM
AOAC@ AOAC support part X764CU12002 RG192 H8GbX4@
BL@ BL RH1204 GN20P0@ RH1204 N18P@ RH1203 GN20P1@ RH1203 GN20P0D@

S3
Battery only O O O O X CD@ Cost down part UP9632_@ UP9632 part stuff
CNVI@ CNVi support part USB@ USB2.0 port1 for USB Port 1/20W_100K_1%_0201
SD04110038J
DCI@ DCI X76@ VRAM S RES 1/20W 10K +-5% 0201S RES 1/20W 10K +-5% 0201S RES 1/20W 10K +-5% 0201S RES 1/20W 10K +-5% 0201
Debug@ USB2.0 port 1for Debug GS@ Reserved for G-sensor

S5 S4/AC Only O O O X X SD04310028J SD04310028J SD04310028J SD04310028J
Micron VRAM LLH--RG194/RG193/RG187
EMC@ EMC part 15_P@
EMC_8111H@ LAN 8111H EMC Part UG4 M8GbX4@ UG5 M8GbX4@ UG6 M8GbX4@ UG7 M8GbX4@ RG194 M8GbX4@ RG193 M8GbX4@
ZZZ5 X76M8GbX4@
S5 S4 EMC_NS@ EMC not stuff
Battery only O X X X X GC6@
GYSNC@
GC6
GSYNC support part
CPU UC1 11400H@ UC1 11800H@
Micron 8Gb VRAM Micron 8Gb VRAM Micron 8Gb VRAM Micron 8Gb VRAM 1/20W_100K_1%_0201 1/20W_100K_1%_0201
S5 S4 HDMI@ HDMI
Micron 8Gb VRAM
X764CV12001
SA00009L530 SA00009L530 SA00009L530 SA00009L530 SD04110038J SD04110038J
AC & Battery X X X X X i5@i7@i9@ CPU Part S IC FH8069004351613 SRKT1 R0 2.7G CPU S IC FH8069004352018 SRKT3 R0 2.3G CPU
RG187 M8GbX4@
don't exist ME@ ME part(connector, hole) SA0000BVK10 SA0000BVJ10
M6GX6@S6GX6@ VRAM part UC1 11260H@ UC1 11600H@

1/20W_100K_1%_0201
USB2.0 Port table SD04110038J
USB3.0 Port table SATA Port table PCIE Port table
Port Function S IC FH8069004351513 SRKT0 R0 2.6G CPU SIC FH8069004670407 QXJ0 R0 2.9G BGA CPU
Port Function Port Function Port Function SA0000BWP10 SA0000BWQ00
1 Back USB3.0
1 Back USB3.0 0A NA 1:8 NA
2 Left USB3.0 ZZZ10 X76NCP495@ OVRM for GEN2@
2 Right USB3.0 0B HDD Gen3 9 M.2 SSD/Optane
Right USB3.0 HDMI Logo
3
3 Left USB3.0 1A M.2 SSD Gen3 10 M.2 SSD/Optane PCH UH1 B1MP@ ZZZ16 HDMI@
PU7801 GEN2_ON@ PR7837 GEN2_ON@ PR7838 GEN2_ON@
4 Type-C Port OVRM NCP45495X

4 Type-C Port 1B NA 11 M.2 SSD/Optane X764CU12006
5 NA load GEN2_ON@ S IC NCP45495XMNTWG QFN 32P MONITOR S RES 1/16W 0 +-5% 0402 S RES 1/16W 49.9 +-1% 0402
2
5 Back USB3.0 2 NA 12 M.2 SSD/Optane S IC FH82HM570 SRKMA B1 BGA 943P PCH 12! HDMI Logo
RO00000040J
SA0000B1M00 SD02800008J SD034499A8J
2
6 Camera SA0000BVQ20
6 NA 3 NA 14 WLAN Gen1
7 RGBKB PU7801 GEN2_UPI@ PR7837 GEN2_UPI@ PR7838 GEN2_UPI@ PR7816 GEN2_UPI@ PC7804 GEN2_UPI@
4 M.2 SSD Gen3 15 LAN Gen1
9 AG EDP MUX
HY568P@
5 NA 16 for Card Reader 17" UV12 15@ UV12 17@ UV12 ZZZ11 X76US5651@
10
Back USB3.0 S IC US5651AQKI WQFN 32P PREFILTER S RES 1/16W 51 +-5% 0402 S RES 1/16W 51 +-5% 0402S RES 1/16W 51 +-5% 0402 S CER CAP 0.1U 25V K X5R 0201
7 NA 17:20 M.2 SSD SA0000BCA00 SD028510A8J SD028510A8J SD028510A8J SE000018600
11:13
NA PS8361QFN66GTR-A2 PS8361QFN66GTR-A2 S IC PS8461EQFN66GTR-A2 QFN DP SWITCH OVRM US5651A PR7808 GEN2_UPI@ PR7817 GEN2_UPI@ PR7809 GEN2_UPI@ PC7813 GEN2_UPI@ PC7809 GEN2_UPI@
14 BT SA0000BCH00 SA0000BCH00 SA0000AQK10 X764CU12007
load GEN2_UPI@
S RES 1/16W 51 +-5% 0402 S RES 1/16W 51 +-5% 0402 S RES 1/16W 51 +-5% 0402 S CER CAP 0.1U 25V K X5R 0402
S CER CAP 0.1U 25V K X5R 0201
SD028510A8J SD028510A8J SD028510A8J SE00000G88J SE000018600
GN20x-P and N18P-G61-A CO-LAY PWR BTN EMC ZZZ12 X76NCP491@

OVRM for GEN1@
VRAM_FB setting VBIOS ROM PN +FUSE_1V8 DI113 15@ DI113 HY568P@ PU7801 GEN1_ON@ PR7826 GEN1_ON@ PR7811 GEN1_ON@ PR7818 GEN1_ON@ PR7822 GEN1_ON@ PR7835 GEN1_ON@ PR7802 GEN1_ON@
OVRM NCP45491X
X764CU12008
RG702 GN20@ UG15 GN20@ RG1200 GN20@ RG1200 N18P@
AZ5725-01F.R7GR_DFN1006P2X2 AZ5725-01F.R7GR_DFN1006P2X2 load GEN1_ON@ S IC NCP45491XMNTWG QFN 32P MONITOR

SA00009KR00
S RES 1/16W 0 +-5% 0402
SD02800008J
S RES 1/16W 649 +-1% 0402 1/16W 649 +-1% 0402
SD000008O8J SD000008O8J
S RES 1/16W 475 +-1% 0402S RES 1/16W 475 +-1% 0402 S RES 1/16W 243K +-1% 0402
SD03447508J SD03447508J SD000025J00
SC400008K00 SC400008K00
2.49K_0402_1% W25Q16JWSNIQ_SOIC8 10K_0402_1% 1/16W_2.21K_1%_0402 ZZZ13 X76US5650@
SD03424918J SA0000AU500 SD03410028J SD00001KC00
PU7801 GEN1_UPI@ PR7811 GEN1_UPI@ PR7818 GEN1_UPI@ PR7822 GEN1_UPI@ PR7835 GEN1_UPI@ PR7802 GEN1_UPI@
PWR LED OVRM US5650Q

X764CU12009
RG702 N18P@ UG15 N18P@ CG1104 GN20@ CG1104 N18P@ S IC US5650QQKI WQFN 32P PREFILTER S RES 1/16W 487 +-1% 0402S RES 1/16W 487 +-1% 0402S RES 1 /16W 357 +-1% 0402 S RES 1 /16W 357 +-1% 04021/16W_324K_1%_0402
HY568P@ HY568P@ RI408 HY568P@ SA00009YH00 SD00002CE00 SD00002CE00 SD00001DC00 SD00001DC00 SD000021D00
RI406 RI407 load GEN1_UPI@
49.9_0402_1% W25Q80EWSNIG_SO8 1U_6.3V_K_X6S_0402 2.2U_0402_6.3V6M
SD034499A8J SA000080E00 SE00000X300 SE00000888J PR7808 GEN1@ PR7809 GEN1@ PR7816 GEN1@ PR7842 GEN1@ PR7817 GEN1@ PR7824 GEN1@
S RES 1/16W 1.33K +-1% 0402S RES 1/16W 1.69K +-1% 0402
S RES 1/16W 1.1K +-1% 0402
SD00000RF0J SD00000JB8J SD03411018J
for GEN1
15@ 15@ RI408 15@ S RES 1/16W 100 +-1% 0402 S RES 1/16W 75K +-1% 0402 S RES 1/16W 49.9 +-1% 0402S RES 1/16W 49.9 +-1% 0402S RES 1/16W 75K +-1% 0402 S RES 1/16W 0 +-5% 0402
RI406 RI407 SD03410008J SD03475028J SD034499A8J SD034499A8J SD03475028J SD02800008J
GN20P QS2 / N18P-MP sample

3 3
UG1 N18P@ ZZZ7 X76NCP15@
UG1 GN20P0@ UG1 GN20P1@ S RES 1/16W 3.09K +-1% 0402 S RES 1/16W 3.83K +-1% 0402 S RES 1/16W 1.8K +-1% 0402
SD000026300 SD00000LZ0J SD00000R58J
S IC N18P-G61-A-A1 FCBGA 1358 GPU MP 12! GPU DRMOS NCP303150

S IC GN20-P0-A1 FCBGA 1358 GPU MP 12 ! S IC GN20-P1-A1 FCBGA 1358 GPU MP 12 ! SA0000BDF20 X764CU12003
SA0000BTE10 SA0000BTD10
UG1 GN20P0D@
Cover LED load NCP3150@
RV71 15@ RV72 15@ QV8 15@ RV71 HY568P@ RV72 HY568P@ QV8 HY568P@
ZZZ8 X76AOS52@
S IC GN20-P0-D-A1 GB5B 128P GPU MP 12 !
SA0000BWM10 ZZZ9 X76NCP16@
PC2039 AOS5279@ PC2044 AOS5279@ PC2045 AOS5279@ PC2039 NCP3160@ PC2044 NCP3160@ PC2045 NCP3160@
0_0402_5% 100K_0402_5% PJA138K_SOT23-3 0_0402_5% 100K_0402_5% PJA138K_SOT23-3
SD02800008J SD02810038J SB000012X00 SD02800008J SD02810038J SB000012X00 GPU DRMOS AOZ5279QI
X764CU12004
GPU DRMOS NCP303160
load S CER CAP 33P 50V J NPO 0402S CER CAP 33P 50V J NPO 0402 S CER CAP 33P 50V J NPO 0402
SE071330J8J SE071330J8J SE071330J8J
X764CU12005 S CER CAP 100P 50V J NPO 0402
SE071101J8J
S CER CAP 100P 50V J NPO 0402
S CER CAP 100P 50V J NPO 0402
SE071101J8J SE071101J8J
NVVDD AOS5279@ PR2055 AOS5279@ PR2065 AOS5279@ PR2074 AOS5279@

load PR2055 NCP3160@ PR2065 NCP3160@ PR2074 NCP3160@
+0.95VGS
VCCST/VCCSTG Enable P84 NCP3160@
PR2031 N18P@ PR6804 N18P@
ZZZ14 X76G3905@
S RES 1/16W 2K +-5% 0402 S RES 1/16W 2K +-5% 0402 S RES 1/16W 2K +-5% 0402 S RES 1/16W 432 +1% 0402 S RES 1/16W 432 +1% 0402 S RES 1/16W 432 +1% 0402
SD02820018J SD02820018J SD02820018J SD03443208J SD03443208J SD03443208J
S RES 1/16W 4.32K +-1% 0402 S RES 1/16W 26.1K +-1% 0402
load 3905@
SD00000J28J SD03426128J
VCCST G3905 PR2101 AOS5279@ PR2102 AOS5279@ PR2103 AOS5279@ PR2101 NCP3160@ PR2102 NCP3160@ PR2103 NCP3160@
X764CM1200A
PR2034 N18P@
S RES 1/16W 2.61K +-1% 0402 S RES 1/16W 2.61K +-1% 0402 S RES 1/16W 2.61K +-1% 0402 S RES 1/16W 0 +-5% 0402 S RES 1/16W 0 +-5% 0402 S RES 1/16W 0 +-5% 0402
SD000009M8J SD000009M8J SD000009M8J SD02800008J SD02800008J SD02800008J
ZZZ15 X76Discr@
S RES 1/16W 16.5K +-1% 0402
SD03416528J PR2023 AOS5279@ PR2026 AOS5279@ PR2068 AOS5279@ PR2023 NCP3160@ PR2026 NCP3160@ PR2068 NCP3160@
PR2033 N18P@
load Discr@
VCCST dispersion
X764CM1200B
S RES 1/16W 1K +-1% 0402 S RES 1/16W 1K +-1% 0402 S RES 1/16W 1K +-1% 0402 S RES 1/16W 0 +-5% 0402 S RES 1/16W 0 +-5% 0402 S RES 1/16W 0 +-5% 0402
SD03410018J SD03410018J SD03410018J SD02800008J SD02800008J SD02800008J
S RES 1/16W 309 +-1% 0402

SD00001XX00
PU2001 AOS5279@ PU2002 AOS5279@ PU2004 AOS5279@ PU2001 NCP3160@ PU2002 NCP3160@ PU2004 NCP3160@
ZZZ2
PCB@
MB PCB
4 4
S IC AOZ5279QI QFN 39P POWER

S IC AOZ5279QI QFN 39P POWERS IC AOZ5279QI QFN 39P POWER S IC NCP303160MNTWG PQFN 41P PWM
S IC NCP303160MNTWG PQFN 41P PWM
S IC NCP303160MNTWG PQFN 41P PWM
SA0000BJF00 SA0000BJF00 SA0000BJF00 SA0000ANB00 SA0000ANB00 SA0000ANB00
PCB HY563 NM-D741 NSD741/742/743/744/745, A.2 ZZZ17 ZZZ18 ZZZ19 ZZZ20
MB_PCB@ 15_USB_PCB@ 17_USB_PCB@ HY568P_USB_PCB@
DAZ22G00100
PCB 22G NM-D741 REV1 M/B, A.3 PCB 22G NS-D741 REV1 IO-USB/BPCB 22Z NS-D742 REV1 IO-USB/BPCB 22X NS-D743 REV1 IO-USB/B
DAA0000GM10 DAA0000GN10 DAA0000GP10 DAA0000GR10
ZZZ21 ZZZ22
HY568P_MIC_PCB@ 17_PWR_PCB@
Vinafix.com
PCB 22X NS-D744 REV1 IO-MIC/B PCB 22Z NS-D745 REV1 IO-POWER/B
DAA0000GS10 DAA0000GT10
Issued Date 2021/04/07 Deciphered Date 2021/04/07 Notes List
Custom
HY568 0.1

A B C D E
5 4 3 2 1
D D
UC1C
PCIE4_CRX_DTX3_P N29 3 OF 15 E28 PCIE4_CTX_DRX3_P

63 PCIE4_CRX_DTX3_P PCIE4_CRX_DTX3_N PCIE4_RX_P_3 PCIE4_TX_P_3 PCIE4_CTX_DRX3_N PCIE4_CTX_DRX3_P 63
63 PCIE4_CRX_DTX3_N M29 D28 PCIE4_CTX_DRX3_N 63
PCIE4_CRX_DTX2_P PCIE4_RX_N_3 PCIE4_TX_N_3 PCIE4_CTX_DRX2_P
63 PCIE4_CRX_DTX2_P J29 A28 PCIE4_CTX_DRX2_P 63
PCIE4_CRX_DTX2_N PCIE4_RX_P_2 PCIE4_TX_P_2 PCIE4_CTX_DRX2_N
K29 B28
For MAIN SSD1 63
63
PCIE4_CRX_DTX2_N
PCIE4_CRX_DTX1_P
PCIE4_CRX_DTX1_P
PCIE4_CRX_DTX1_N
M31
L31
PCIE4_RX_N_2
PCIE4_RX_P_1
PCIE4_TX_N_2
PCIE4_TX_P_1
F29
E29
PCIE4_CTX_DRX1_P
PCIE4_CTX_DRX1_N
PCIE4_CTX_DRX2_N
PCIE4_CTX_DRX1_P
63
63 For MAIN SSD1
63 PCIE4_CRX_DTX1_N PCIE4_CRX_DTX0_P PCIE4_RX_N_1 PCIE4_TX_N_1 PCIE4_CTX_DRX0_P PCIE4_CTX_DRX1_N 63
63 PCIE4_CRX_DTX0_P H31 B29 PCIE4_CTX_DRX0_P 63
PCIE4_CRX_DTX0_N PCIE4_RX_P_0 PCIE4_TX_P_0 PCIE4_CTX_DRX0_N
63 PCIE4_CRX_DTX0_N J31 C29 PCIE4_CTX_DRX0_N 63
PCIE4_RX_N_0 PCIE4_TX_N_0
PEG_CRX_GTX0_P N15 E16 PEG_CTX_GRX0_P OPT@ CC17 1 2 0.22U_6.3V_K_X5R_0201 PEG_CTX_C_GRX0_P
28 PEG_CRX_GTX0_P PEG_CRX_GTX0_N PCIE16_RX_P_15 PCIE16_TX_P_15 PEG_CTX_GRX0_N PEG_CTX_C_GRX0_N PEG_CTX_C_GRX0_P 28
M15 D16 OPT@ CC1 1 2 0.22U_6.3V_K_X5R_0201
28 PEG_CRX_GTX0_N PEG_CRX_GTX1_P PCIE16_RX_N_15 PCIE16_TX_N_15 PEG_CTX_GRX1_P PEG_CTX_C_GRX1_P PEG_CTX_C_GRX0_N 28
J15 A16 OPT@ CC18 1 2 0.22U_6.3V_K_X5R_0201
K15 B16 OPT@ CC2 1 2 0.22U_6.3V_K_X5R_0201
M17 F17 OPT@ CC19 1 2 0.22U_6.3V_K_X5R_0201
L17 E17 OPT@ CC3 1 2 0.22U_6.3V_K_X5R_0201
H17 B17 OPT@ CC20 1 2 0.22U_6.3V_K_X5R_0201
J17 C17 OPT@ CC4 1 2 0.22U_6.3V_K_X5R_0201
N18 E18 OPT@ CC21 1 2 0.22U_6.3V_K_X5R_0201
M18 D18 OPT@ CC5 1 2 0.22U_6.3V_K_X5R_0201
J18 A18 OPT@ CC22 1 2 0.22U_6.3V_K_X5R_0201
K18 B18 OPT@ CC6 1 2 0.22U_6.3V_K_X5R_0201
M20 F20 OPT@ CC23 1 2 0.22U_6.3V_K_X5R_0201
L20 E20 OPT@ CC7 1 2 0.22U_6.3V_K_X5R_0201
H20 B20 OPT@ CC24 1 2 0.22U_6.3V_K_X5R_0201
J20 C20 OPT@ CC8 1 2 0.22U_6.3V_K_X5R_0201
28 PEG_CRX_GTX7_N PCIE16_RX_N_8 PCIE16_TX_N_8 PEG_CTX_C_GRX7_N 28
N22 E22
PCIE16_RX_P_7 PCIE16_TX_P_7
M22 D22
J22 A22
K22 B22
C M24 F23 C
L24 E23
H24 B23
J24 C23
N26 E25
M26 D25
J26 A25
K26 B25
M28 F27
L28 E27
H28 B27
J28 C27
C41 U11 PEG_RCOMP_P
RSVD_TP_9 PCIE16_COM0_RCOMP_P PEG_RCOMP_N RC1 1 2 1/20W_2.2K_+-1%_0201
D41 R11
RSVD_TP_10 PCIE16_COM0_RCOMP_N
A40
RSVD_TP_11 PCIE4_RCOMP_P
B40 T26
RSVD_TP_12 PCIE4_RCOMP_P PCIE4_RCOMP_N RC858 1 2 1/20W_2.2K_+-1%_0201
R26
RC10 1 2 2.2K_0402_1% DMI_RCOMP_P C4 PCIE4_RCOMP_N
DMI_RCOMP_N C5 DMI_RCOMP_P DMI_CTX_PRX7_P
J13 DMI_CTX_PRX7_P 21
DMI_ RCOMP_N DMI_TX_P_7 DMI_CTX_PRX7_N
H13 DMI_CTX_PRX7_N 21
DMI_CRX_PTX7_P DMI_TX_N_7 DMI_CTX_PRX6_P
21 DMI_CRX_PTX7_P C14 M13 DMI_CTX_PRX6_P 21
DMI_CRX_PTX7_N DMI_RX_P_7 DMI_TX_P_6 DMI_CTX_PRX6_N
21 DMI_CRX_PTX7_N B14 L13 DMI_CTX_PRX6_N 21
DMI_CRX_PTX6_P DMI_RX_N_7 DMI_TX_N_6 DMI_CTX_PRX5_P
21 DMI_CRX_PTX6_P F14 H11 DMI_CTX_PRX5_P 21
21 DMI_CRX_PTX6_N E14 G11 DMI_CTX_PRX5_N 21
21 DMI_CRX_PTX5_P B13 N11 DMI_CTX_PRX4_P 21
21 DMI_CRX_PTX5_N A13 L11 DMI_CTX_PRX4_N 21
21 DMI_CRX_PTX4_P E13 E10 DMI_CTX_PRX3_P 21
21 DMI_CRX_PTX4_N D13 D10 DMI_CTX_PRX3_N 21
21 DMI_CRX_PTX3_P C11 F9 DMI_CTX_PRX2_P 21
21 DMI_CRX_PTX3_N B11 E9 DMI_CTX_PRX2_N 21
21 DMI_CRX_PTX2_P B10 E8 DMI_CTX_PRX1_P 21
21 DMI_CRX_PTX2_N A10 D8 DMI_CTX_PRX1_N 21
21 DMI_CRX_PTX1_P C9 D6 DMI_CTX_PRX0_P 21
21 DMI_CRX_PTX1_N B9 C6 DMI_CTX_PRX0_N 21
DMI_CRX_PTX0_P DMI_RX_N_1 DMI_TX_N_0
21 DMI_CRX_PTX0_P B8
DMI_CRX_PTX0_N DMI_RX_P_0
21 DMI_CRX_PTX0_N A8
DMI_RX_N_0
B B
B3
RSVD_TP_13
B4
RSVD_TP_14
TIGERLAKE-H-CPU_BGA1787
@
A A

X60-TGL-H
Size Document Number Rev
Vinafix.com
C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CPU (1/9) DMI,PEG
5 4 3 2 1
5 4 3 2 1
UC1A DDRA_DQ[0..63] 25
DDR4 / DDR5 DDR4(IL) / DDR4(NIL) / DDR5(IL)
BC3 1 OF 15 G2 DDRA_DQ63
DDR0_CLK_P3/DDR1_CLK_P1 DDR0_DQ7_7/DDR1_DQ5_7/DDR1_DQ3_7 DDRA_DQ62
BC4 H1
DDR0_CLK_N3/DDR1_CLK_N1 DDR0_DQ7_6/DDR1_DQ5_6/DDR1_DQ3_6 DDRA_DQ61
BC1 H3
BC2 H4
25 DDRA_CLK1_P BK3 L1
25 DDRA_CLK1_N BK4 K1
25 DDRA_CLK0_P BK1 L4
25 DDRA_CLK0_N BK2 L3
N2
DDR0_DQ6_7/DDR1_DQ4_7/DDR1_DQ2_7 DDRA_DQ54
BW4 P1
DDR0_CKE3/NC DDR0_DQ6_6/DDR1_DQ4_6/DDR1_DQ2_6 DDRA_DQ53
BW3 P3
D DDR0_CKE2/DDR0_CS1 DDR0_DQ6_5/DDR1_DQ4_5/DDR1_DQ2_5 DDRA_DQ52 D
25 DDRA_CKE1 BN1 P4
DDR0_CKE1/DDR0_CS3 DDR0_DQ6_4/DDR1_DQ4_4/DDR1_DQ2_4 DDRA_DQ51
25 DDRA_CKE0 BW1 U1
DDR0_CKE0/DDR0_CS0 DDR0_DQ6_3/DDR1_DQ4_3/DDR1_DQ2_3 DDRA_DQ50
R1
AR4 U4
DDR0_CS3/DDR1_CS0 DDR0_DQ6_1/DDR1_DQ4_1/DDR1_DQ2_1 DDRA_DQ48
AV1 U3
DDR0_CS2/DDR1_CA5 DDR0_DQ6_0/DDR1_DQ4_0/DDR1_DQ2_0 DDRA_DQ47
25 DDRA_CS1_N AN4 V2
25 DDRA_CS0_N AV3 W1
W3
AN1 W4
DDR0_ODT3/NC DDR0_DQ5_4/DDR1_DQ1_4/DDR1_DQ1_4 DDRA_DQ43
AV4 AB1
DDRA_ODT1 AM3 DDR0_ODT2/DDR1_CA1 DDR0_DQ5_3/DDR1_DQ1_3/DDR1_DQ1_3 DDRA_DQ42
25 DDRA_ODT1 Y1
DDRA_ODT0 AR3 DDR0_ODT1/DDR1_CS1 DDR0_DQ5_2/DDR1_DQ1_2/DDR1_DQ1_2 DDRA_DQ41
25 DDRA_ODT0 AB4
DDR0_ODT0/DDR1_CA3 DDR0_DQ5_1/DDR1_DQ1_1/DDR1_DQ1_1 DDRA_DQ40
AB3
25 DDRA_MA16_RAS_N AY2 AC2
DDR0_MA16/DDR1_CA8 DDR0_DQ4_7/DDR1_DQ0_7/DDR1_DQ0_7 DDRA_DQ38
25 DDRA_MA15_CAS_N AN3 AD1
25 DDRA_MA14_WE_N AR1 AD3
AD4
DDRA_MA13 DDR0_DQ4_4/DDR1_DQ0_4/DDR1_DQ0_4 DDRA_DQ35
25 DDRA_MA13 AM2 AG1
DDRA_MA12 DDR0_MA13/DDR1_CA2 DDR0_DQ4_3/DDR1_DQ0_3/DDR1_DQ0_3 DDRA_DQ34
25 DDRA_MA12 BP4 AF1
25 DDRA_MA11 BP2 AG4
DDRA_MA10_AP DDR0_MA11/DDR0_CA5 DDR0_DQ4_1/DDR1_DQ0_1/DDR1_DQ0_1 DDRA_DQ32
25 DDRA_MA10_AP BD1 AG3
BP3 CE2
BM4 CF1
BV3 CF4
BM1 CF3
BN3 CJ1
BM3 CH1
BM2 CJ4
BG1 CJ3
DDRA_MA1 DDR0_MA2/NC DDR0_DQ3_0/DDR0_DQ5_0/DDR0_DQ3_0 DDRA_DQ23
BH1 CK2
BE4 CM1
25 DDRA_MA[0..9] CM4
DDRA_BG1 DDR0_DQ2_5/DDR0_DQ4_5/DDR0_DQ2_5 DDRA_DQ20
25 DDRA_BG1 BV1 CM3
DDR0_BG1/DDR0_CA2 DDR0_DQ2_4/DDR0_DQ4_4/DDR0_DQ2_4 DDRA_DQ19
25 DDRA_BG0 BP1 CU7
DDR0_BG0/DDR0_CA1 DDR0_DQ2_3/DDR0_DQ4_3/DDR0_DQ2_3 DDRA_DQ18
25 DDRA_BA1 AY3 CR7
DDR0_BA1/DDR1_CA11 DDR0_DQ2_2/DDR0_DQ4_2/DDR0_DQ2_2 DDRA_DQ17
25 DDRA_BA0 AW3 CU8
DDR0_BA0/DDR1_CA9 DDR0_DQ2_1/DDR0_DQ4_1/DDR0_DQ2_1 DDRA_DQ16
CR8
DDRA_ACT_N DDR0_DQ2_0/DDR0_DQ4_0/DDR0_DQ2_0 DDRA_DQ15
C
25 DDRA_ACT_N BW2 CT9 C
DDR0_ACT#/DDR0_CA0 DDR0_DQ1_7/DDR0_DQ1_7/DDR0_DQ1_7 DDRA_DQ14
DDR4(IL) / DDR4(NIL) / DDR5(IL) CU11
DDRA_DQS7_P DDR0_DQ1_6/DDR0_DQ1_6/DDR0_DQ1_6 DDRA_DQ13
25 DDRA_DQS7_P K3 CR11
DDRA_DQS6_P DDR0_DQSP_7/DDR1_DQSP_5/DDR1_DQSP_3 DDR0_DQ1_5/DDR0_DQ1_5/DDR0_DQ1_5 DDRA_DQ12
25 DDRA_DQS6_P R3 CP11
DDRA_DQS5_P DDR0_DQSP_6/DDR1_DQSP_4/DDR1_DQSP_2 DDR0_DQ1_4/DDR0_DQ1_4/DDR0_DQ1_4 DDRA_DQ11
25 DDRA_DQS5_P Y3 CU13
DDRA_DQS4_P AF3 DDR0_DQSP_5/DDR1_DQSP_1/DDR1_DQSP_1 DDR0_DQ1_3/DDR0_DQ1_3/DDR0_DQ1_3 DDRA_DQ10
25 DDRA_DQS4_P CU12
DDRA_DQS3_P CH3 DDR0_DQSP_4/DDR1_DQSP_0/DDR1_DQSP_0 DDR0_DQ1_2/DDR0_DQ1_2/DDR0_DQ1_2 DDRA_DQ9
25 DDRA_DQS3_P CP13
DDRA_DQS2_P CN2 DDR0_DQSP_3/DDR0_DQSP_5/DDR0_DQSP_3 DDR0_DQ1_1/DDR0_DQ1_1/DDR0_DQ1_1 DDRA_DQ8
25 DDRA_DQS2_P CR13
DDRA_DQS1_P CR12 DDR0_DQSP_2/DDR0_DQSP_4/DDR0_DQSP_2 DDR0_DQ1_0/DDR0_DQ1_0/DDR0_DQ1_0 DDRA_DQ7
25 DDRA_DQS1_P CT14
DDRA_DQS0_P CR17 DDR0_DQSP_1/DDR0_DQSP_1/DDR0_DQSP_1 DDR0_DQ0_7/DDR0_DQ0_7/DDR0_DQ0_7 DDRA_DQ6
25 DDRA_DQS0_P CU16
DDR0_DQSP_0/DDR0_DQSP_0/DDR0_DQSP_0 DDR0_DQ0_6/DDR0_DQ0_6/DDR0_DQ0_6 DDRA_DQ5
CR16
DDRA_DQS7_N DDR0_DQ0_5/DDR0_DQ0_5/DDR0_DQ0_5 DDRA_DQ4
25 DDRA_DQS7_N K4 CP16
DDRA_DQS6_N R4 DDR0_DQSN_7/DDR1_DQSN_5/DDR1_DQSN_3 DDR0_DQ0_4/DDR0_DQ0_4/DDR0_DQ0_4 DDRA_DQ3
25 DDRA_DQS6_N CU18
DDRA_DQS5_N Y4 DDR0_DQSN_6/DDR1_DQSN_4/DDR1_DQSN_2 DDR0_DQ0_3/DDR0_DQ0_3/DDR0_DQ0_3 DDRA_DQ2
25 DDRA_DQS5_N CU17
DDRA_DQS4_N AF4 DDR0_DQSN_5/DDR1_DQSN_1/DDR1_DQSN_1 DDR0_DQ0_2/DDR0_DQ0_2/DDR0_DQ0_2 DDRA_DQ1
25 DDRA_DQS4_N CP18
DDRA_DQS3_N CH4 DDR0_DQSN_4/DDR1_DQSN_0/DDR1_DQSN_0 DDR0_DQ0_1/DDR0_DQ0_1/DDR0_DQ0_1 DDRA_DQ0
25 DDRA_DQS3_N CR18
DDRA_DQS2_N CN3 DDR0_DQSN_3/DDR0_DQSN_5/DDR0_DQSN_3 DDR0_DQ0_0/DDR0_DQ0_0/DDR0_DQ0_0
25 DDRA_DQS2_N DDRA_DQS1_N CP12 DDR0_DQSN_2/DDR0_DQSN_4/DDR0_DQSN_2
25 DDRA_DQS1_N BY2
DDRA_DQS0_N CP17 DDR0_DQSN_1/DDR0_DQSN_1/DDR0_DQSN_1 DDR0_DQ8_7/NC/NC
25 DDRA_DQS0_N CA1
DDR0_DQSN_0/DDR0_DQSN_0/DDR0_DQSN_0 DDR0_DQ8_6/NC/NC
DDR4 / DDR5 CA4
+VREF_CA_DIMMA_R DDRA_PARITY BE1 DDR0_DQ8_5/NC/NC
25 DDRA_PARITY CA3
DDRA_ALERT_N D3 DDR0_PAR/NC DDR0_DQ8_4/NC/NC
25 DDRA_ALERT_N CD1
DDR0_ALERT# DDR0_DQ8_3/NC/DDR0_DQ4_3
DDR4 CC1
DDR0_DQ8_2/NC/DDR0_DQ4_2
CP21 CD4 CAD Note:
RC147 1 @ 2 0_0402_5% +V_DDR_REFA_R DDR0_VREF_CA_1 DDR0_DQ8_1/NC/DDR0_DQ4_1
CR21 CD3
DDR0_VREF_CA_0 DDR0_DQ8_0/NC/DDR0_DQ4_0 Trace width=12~15 mil, Spcing=20 mils
DDR0_DQSN_8/NC/DDR0_DQSP_4
CC4 Max trace length= 500 mil
CC3
DDR0_DQSP_8/NC/DDR0_DQSP_4
D2 SM_RCOMP2 RC5 1 2 1/20W_100_1%_0201
DDR_RCOMP
CG12DDR_PG_CTRL
DDR_VTT_CTL
@
B B
+3VALW_SYS +3VS CAD Note:

Trace width= 20 mil, Spcing=20 mils
DDR_VREF_CA : Connected to VREF_CA on DIMM CH-A
2
2
DDR0_VREF_DQ : NC
RC178 DDR1_VREF_CA : Connected to VREF_CA on DIMM CH-B
+1.2V RC177
100K_0402_5%
100K_0402_5%
@
DDR4 COMPENSATION SIGNALS
1
1
1
SM_PG_CTRL
SM_PG_CTRL 93
RC18
1K_0402_5%
1
C
2
DDR_PG_CTRL_EN 2 QC1
B MMBT3904WH_SOT323-3
E
3
DDR_PG_CTRL
2
RC179
10K_0402_5%
@
1
A
Logic Buffer A

X60-TGL-H
C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CPU(2/9):(DDR4-Chanel-A)
Vinafix.com
5 4 3 2 1
5 4 3 2 1
D D
UC1B
DDRB_DQ[0..63] 26
DDR4 / DDR5 DDR4(IL) / DDR4(NIL) / DDR5(IL)
BC8 2 OF 15 G7 DDRB_DQ63
DDR1_CLK_P3/DDR3_CLK_P1 DDR1_DQ7_7/DDR1_DQ7_7/DDR3_DQ3_7 H9 DDRB_DQ62
BC9
DDR1_CLK_N3/DDR3_CLK_N1 DDR1_DQ7_6/DDR1_DQ7_6/DDR3_DQ3_6 L9 DDRB_DQ61
BC6
DDR1_CLK_P2/DDR3_CLK_P0 DDR1_DQ7_5/DDR1_DQ7_5/DDR3_DQ3_5 DDRB_DQ60
BC7 H8
DDR1_CLK_N2/DDR3_CLK_N0 DDR1_DQ7_4/DDR1_DQ7_4/DDR3_DQ3_4 H6 DDRB_DQ59
26 DDRB_CLK1_P BK6
26 DDRB_CLK1_N BK7 L8
DDR1_CLK_N1/DDR2_CLK_N1 DDR1_DQ7_2/DDR1_DQ7_2/DDR3_DQ3_2 DDRB_DQ57
26 DDRB_CLK0_P BK8 L6
26 DDRB_CLK0_N BK9 K6
DDR1_CLK_N0/DDR2_CLK_N0 DDR1_DQ7_0/DDR1_DQ7_0/DDR3_DQ3_0 DDRB_DQ55
N7
DDR1_DQ6_7/DDR1_DQ6_7/DDR3_DQ2_7 DDRB_DQ54
BW9 P9
DDR1_CKE3/NC DDR1_DQ6_6/DDR1_DQ6_6/DDR3_DQ2_6 DDRB_DQ53
BW8 U9
DDR1_CKE2/DDR2_CS1 DDR1_DQ6_5/DDR1_DQ6_5/DDR3_DQ2_5 DDRB_DQ52
26 DDRB_CKE1 BN7 P8
DDR1_CKE1/DDR2_CS3 DDR1_DQ6_4/DDR1_DQ6_4/DDR3_DQ2_4 P6 DDRB_DQ51
26 DDRB_CKE0 BW6
DDR1_CKE0/DDR2_CS0 DDR1_DQ6_3/DDR1_DQ6_3/DDR3_DQ2_3 DDRB_DQ50
U8
AR10 U6
DDR1_CS3/DDR3_CS0 DDR1_DQ6_1/DDR1_DQ6_1/DDR3_DQ2_1 DDRB_DQ48
AV6 R6
DDR1_CS2/DDR3_CA5 DDR1_DQ6_0/DDR1_DQ6_0/DDR3_DQ2_0 DDRB_DQ47
26 DDRB_CS1_N AN9 V7
26 DDRB_CS0_N AV8 W9
AB9
AN6 W8
DDR1_ODT3/NC DDR1_DQ5_4/DDR1_DQ3_4/DDR3_DQ1_4 DDRB_DQ43
AV9 W6
DDRB_ODT1 DDR1_ODT2/DDR3_CA1 DDR1_DQ5_3/DDR1_DQ3_3/DDR3_DQ1_3 DDRB_DQ42
26 DDRB_ODT1 AM9 AB8
DDRB_ODT0 DDR1_ODT1/DDR3_CS1 DDR1_DQ5_2/DDR1_DQ3_2/DDR3_DQ1_2 DDRB_DQ41
26 DDRB_ODT0 AR9 AB6
DDR1_ODT0/DDR3_CA3 DDR1_DQ5_1/DDR1_DQ3_1/DDR3_DQ1_1 DDRB_DQ40
Y6
26 DDRB_MA16_RAS_N AW8 AC7
DDR1_MA16/DDR3_CA8 DDR1_DQ4_7/DDR1_DQ2_7/DDR3_DQ0_7 DDRB_DQ38
26 DDRB_MA15_CAS_N AN8 AD9
26 DDRB_MA14_WE_N AR7 AG9
AD8
DDRB_MA13 DDR1_DQ4_4/DDR1_DQ2_4/DDR3_DQ0_4 DDRB_DQ35
26 DDRB_MA13 AM7 AD6
DDRB_MA12 DDR1_MA13/DDR3_CA2 DDR1_DQ4_3/DDR1_DQ2_3/DDR3_DQ0_3 DDRB_DQ34
26 DDRB_MA12 BP9 AG8
26 DDRB_MA11 BP7 AG6
DDRB_MA10_AP DDR1_MA11/DDR2_CA5 DDR1_DQ4_1/DDR1_DQ2_1/DDR3_DQ0_1 DDRB_DQ32
26 DDRB_MA10_AP AY7 AF6
BP8 CH6
BM9 CJ6
BV8 CJ8
C BN9 CF6 C
BM7 CF8
BM6 CE7
BM8 CF9
BG6 CJ9
DDRB_MA1 DDR1_MA2/NC DDR1_DQ3_0/DDR0_DQ7_0/DDR2_DQ3_0 DDRB_DQ23
BH6 CK7
BE9 CM6
26 DDRB_MA[0..9] CM8
DDRB_BG1 DDR1_DQ2_5/DDR0_DQ6_5/DDR2_DQ2_5 DDRB_DQ20
26 DDRB_BG1 BV7 CN6
DDR1_BG1/DDR2_CA2 DDR1_DQ2_4/DDR0_DQ6_4/DDR2_DQ2_4 DDRB_DQ19
26 DDRB_BG0 BP6 CM12
DDR1_BG0/DDR2_CA1 DDR1_DQ2_3/DDR0_DQ6_3/DDR2_DQ2_3 DDRB_DQ18
26 DDRB_BA1 AY9 CM9
DDR1_BA1/DDR3_CA11 DDR1_DQ2_2/DDR0_DQ6_2/DDR2_DQ2_2 DDRB_DQ17
26 DDRB_BA0 AY8 CJ12
DDR1_BA0/DDR3_CA9 DDR1_DQ2_1/DDR0_DQ6_1/DDR2_DQ2_1 DDRB_DQ16
CK12
DDRB_ACT_N DDR1_DQ2_0/DDR0_DQ6_0/DDR2_DQ2_0 DDRB_DQ15
26 DDRB_ACT_N BW7 CL13
DDR1_ACT#/DDR2_CA0 DDR1_DQ1_7/DDR0_DQ3_7/DDR2_DQ1_7 DDRB_DQ14
DDR4(IL) / DDR4(NIL) / DDR5(IL) CM14
DDRB_DQS7_P DDR1_DQ1_6/DDR0_DQ3_6/DDR2_DQ1_6 DDRB_DQ13
26 DDRB_DQS7_P K8 CK14
DDRB_DQS6_P DDR1_DQSP_7/DDR1_DQSP_7/DDR3_DQSP_3 DDR1_DQ1_5/DDR0_DQ3_5/DDR2_DQ1_5 DDRB_DQ12
26 DDRB_DQS6_P R8 CM16
26 DDRB_DQS5_P Y8 CM17
26 DDRB_DQS4_P AF8 CJ14
26 DDRB_DQS3_P CH8 CJ17
26 DDRB_DQS2_P CN8 CK17
26 DDRB_DQS1_P CK16 CL18
26 DDRB_DQS0_P CK21 CM20
DDR1_DQSP_0/DDR0_DQSP_2/DDR2_DQSP_0 DDR1_DQ0_6/DDR0_DQ2_6/DDR2_DQ0_6 DDRB_DQ5
CK20
DDRB_DQS7_N DDR1_DQ0_5/DDR0_DQ2_5/DDR2_DQ0_5 DDRB_DQ4
26 DDRB_DQS7_N K9 CM21
DDRB_DQS6_N DDR1_DQSN_7/DDR1_DQSN_7/DDR3_DQSN_3 DDR1_DQ0_4/DDR0_DQ2_4/DDR2_DQ0_4 DDRB_DQ3
26 DDRB_DQS6_N R9 CM22
26 DDRB_DQS5_N Y9 CJ20
26 DDRB_DQS4_N AF9 CJ22
26 DDRB_DQS3_N CH9 CK22
DDRB_DQS2_N DDR1_DQSN_3/DDR0_DQSN_7/DDR2_DQSN_3 DDR1_DQ0_0/DDR0_DQ2_0/DDR2_DQ0_0
26 DDRB_DQS2_N CN9
DDRB_DQS1_N DDR1_DQSN_2/DDR0_DQSN_6/DDR2_DQSN_2
26 DDRB_DQS1_N CJ16 CD6
DDRB_DQS0_N DDR1_DQSN_1/DDR0_DQSN_3/DDR2_DQSN_1 DDR1_DQ8_7/NC/NC
26 DDRB_DQS0_N CJ21 CA6
DDR1_DQSN_0/DDR0_DQSN_2/DDR2_DQSN_0 DDR1_DQ8_6/NC/NC
BY7
DDRB_PARITY DDR1_DQ8_5/NC/NC
26 DDRB_PARITY BE6 CC6
+VREF_DQ_DIMMB_R DDRB_ALERT_N DDR1_PAR/NC DDR1_DQ8_4/NC/NC
26 DDRB_ALERT_N E4 CA8
DDR1_ALERT# DDR1_DQ8_3/NC/DDR2_DQ4_3
CD8
DDR4 DDR1_DQ8_2/NC/DDR2_DQ4_2
CT21 CA9
RC37 2 @ 1 0_0402_5% +V_DDR_REFB_R DDR1_VREF_CA_1 DDR1_DQ8_1/NC/DDR2_DQ4_1
CU21 CD9
B DDR1_VREF_CA_0 DDR1_DQ8_0/NC/DDR2_DQ4_0 B
CC9
DDR1_DQSN_8/NC/DDR2_DQSP_4
CC8
DDR1_DQSP_8/NC/DDR2_DQSP4
@
A A

X60-TGL-H
Vinafix.com
C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CPU(3/9):(DDR4-Chanel-B)
5 4 3 2 1
5 4 3 2 1
+VCCST_CPU
+VCCSTG_CPU
CFG Straps for CPU

UC1E Reserved configuration lane
2
1 5 OF 15
RC28 1 @ 2 0_0402_5% CPU_BCLKP C36 CT3
19 PCH_CPU_BCLKP CPU_BCLKN BCLK_P CPU_ID
CC186 @ RC66 @ RC2 RC76 RC7 RC29 1 @ 2 0_0402_5% D36
19 PCH_CPU_BCLKN BCLK_N
0.1u_0201_10V6K 100_0402_1% 100_0402_1% 56.2_0402_1% J40 CFG15 @ PAD 1 N/A
2
1K_0402_5%
RC15 1 @ 2 0_0402_5% CPU_PCIBCLKN C37
CFG_15
L41 CFG14
TC7616 CFG0
1
19 PCH_CPU_PCIBCLKN CPU_PCIBCLKP PCI_BCLKN CFG_14
RC13 1 @ 2 0_0402_5% B37 J41 CFG13 @ PAD 1
19 PCH_CPU_PCIBCLKP PCI_BCLKP CFG_13 TC7617
N41 CFG12 @ PAD 1
CFG_12 TC7618
D32 L40 CFG11 @ PAD 1
95 SVID_DATA VIDSOUT CFG_11 TC7619
E32 N40 CFG10 @ PAD 1 Reserved configuration lane
95 SVID_CLK VIDSCK CFG_10 TC7620
F32 M39 CFG9 @ PAD 1
95 SVID_ALERT_N H_PROCHOT_R_N VIDALERT# CFG_9 TC7621
RC9 1 2 499_0402_1% H35 J37 CFG8 @ PAD 1
D 20,79,95 H_PROCHOT_N PROCHOT# CFG_8 TC7622 D
CC178 1 @ 2.1U_0402_10V6-K M38 CFG7
CLKOUT_CPURTC CFG_7 CFG7 24
RC11 1 2 1K_0402_5% CR22 J38 CFG6 N/A
+VCCST_CPU 19 CLKOUT_CPURTC RTC_CLK CFG_6
J35 CFG5
CFG6 24 CFG1
THRMTRIP_CPU_N CFG_5 CFG5 24
17 THRMTRIP_CPU_N F34 N39 CFG4
CPU_PM_SYNC THERMTRIP# CFG_4 CFG4 24
16 CPU_PM_SYNC CR23 L37 CFG3
CPU_PM_DOWN PM_SYNC CFG_3 CFG3 24
16 PCH_PM_DOWN RC33 1 2 20_0402_5% CR24 M35 CFG2
BUF_CPU_PLTRST_N PM_DOWN CFG_2 CFG2 24
16 CPU_PLTRST_N RC22 1 @ 2 0_0201_5% CR25 M37 CFG1 PCI Express Static x16 Lane Numbering Reversal
CPU_PECI RESET# CFG_1 CFG1 24
16,79 CPU_PECI CP25 N36 CFG0
CPU_PWRGOOD_R PECI CFG_0 CFG0 24
19 CPU_PWRGOOD RC32 1 @ 2 0_0402_5% CT25
PROCPWRGD
H_CATERR# CFG_17
M41 PAD 1 @
TC7624  1 Normal operation
RC174 1 2 1K_0402_5% H36 L39
+VCCST_CPU CATERR# CFG_16 CFG16 24 CFG2
2
PROC_PREQ_N
 0 Lane numbers reversed.
1 1 H39 H34
*
1K_0402_5%
BPM#_3 PROC_PREQ# PROC_PREQ_N 24
.1U_0402_10V6-K
CC177
H40 G36 PROC_PRDY_N
RC12
CC176
PROC_PRDY_N 24
100P_0402_50V8J
@ BPM#_2 PROC_PRDY#
G38
@ @ BPM#_1 CFG_RCOMP
H37 A34 Reserved configuration lane
2 2 BPM#_0 CFG_RCOMP
1
E40 CP23 VCCSTPWRGOOD_TCSS RC19 1 @ 2 0_0201_5%
24 PROC_TRST_N PROC_TRST# VCCSTPWRGOOD_TCSS VCCST_PWRGD VCCST_OVERRIDE 22,84
24 PROC_TMS G41 CP24
PROC_TMS VCCST_PWRGD
24 PROC_TDO G39
PROC_TDO CFG3 N/A
24 PROC_TDI F39 CR3
2
PROC_TDI SKTOCC# CPU_C10_WAKE RC20 1 @ 2 0_0201_5%
24 PROC_TCK G40 CU23 PCH_C10_WAKE 19
PROC_TCK C10_WAKE
F37 RC853
RSVD_1
E37
RSVD_2
49.9_0402_1% eDP enable
1
RC888 1 2 1/20W_150_1%_0201 TC_RCOMP_P BR41
TC_RCOMP_P
TC_RCOMP_N BR40
TC_RCOMP_N  1 Disabled.
RC17 1 @ 2 0_0402_5% CPU_NSSC_CLKP C39
19 PCH_CPU_NSSC_CLKP
RC16 1 @ 2 0_0402_5% CPU_NSSC_CLKN CLK_XTAL_P CFG4  0 Enabled.
19 PCH_CPU_NSSC_CLKN D39
CLK_XTAL_N *
TIGERLAKE-H-CPU_BGA1787 +VCCIO PCI Express Bifurcation
@
 00 1 x8, 2 x4 PCI Express
C C
1
 01 reserved
+VCCST_CPU
RC21 CFG[6:5]  10 2 x8 PCI Express
UC1M 100_0402_1%
2
 11 1 x16 PCI Express

*
2
13 OF 15
1 PAD @ R24 BG33
RC164 TC7626 IST_TRIG RSVD_TP_25 PROC_PRDY_N
P24 BG12
1K_0201_5% RSVD_TP_15 RSVD_TP_26
BE33
RSVD_TP_27
E1 BD12
Reserved configuration lane
1
RSVD_TP_16 RSVD_TP_28
D1 BA33
BA12
VCCST_PWRGD RC158 1 2 RSVD_TP_30 +VCCSTG_CPU
EC_VCCST_PWRGD 79 H41 AY33
RSVD_TP_32
AV12
CFG[13:7] N/A
2 1/20W_60.4_1%_0201 1 PAD @ CR4
TC7627 IST_TP_1
1 PAD @ CP4 BT33
TC7628 IST_TP_0 RSVD_TP_33
EMC_NS@ CC1542 AG11
1
RSVD_TP_34
.1U_0402_10V6-K E3 AM33
1 RSVD_5 RSVD_TP_35
E2 BP11 PCIE4 LANE reversal
RSVD_6 RSVD_TP_36 @ RC57
BR11
CPU_TRIGIN RSVD_TP_37 51_0402_5%
17 CPU_TRIGIN CT23 BR12
PCH_TRIGIN CPU_TRIGOUT PROC_TRIGIN RSVD_TP_38
RC4 1 @ 2 0_0402_5% CT24 BN11
* 1 (default) normal
2
17 PCH_TRIGIN PROC_TRIGOUT RSVD_TP_39 PROC_PREQ_N
BN12
CN24
RSVD_TP_40
AG12 CFG14  0 Reversed
CM25 AF11
R31
RSVD_TP_21 +VCCSTG_CPU
CN25 BM33
RSVD_TP_22 RSVD_7
CM24
RSVD_TP_23 RSVD_8
P31 Reserved configuration lane.
R29 T29
1
RSVD_TP_24 RSVD_9
CP22
RSVD_10
RSVD_11
CU25
CU24 @ RC78
CFG[17:15] N/A
RSVD_12 100_0402_1%
CU22
RSVD_13
R28
2
RSVD_14 PROC_TDO
B @ B
+VCCIO
1
1
RC139 RC140 RC141 RC142 RC143 RC144 RC145
+VCCIO 1K_0402_5% 1K_0402_5% 1K_0402_5% 1K_0402_5% 1K_0402_5% @ 1K_0402_5% 1K_0402_5%
@ @ @
2
2
RPC1 CFG14
CFG7
CFG3 1 8 CFG6
CFG9 2 7 CFG5
CFG10 3 6 CFG4
CFG11 4 5 CFG2
CFG1
1/16W_1K_5%_8P4R_0804
1
1
1
RC56 RC53 RC54 RC52 RC51 RC55 RC58
1K_0402_5% 1K_0402_5% 1K_0402_5% 1K_0402_5% 1K_0402_5% 1K_0402_5% 1K_0402_5%
@ @ @ @
2
2
2
A A

X60-TGL-H
Vinafix.com AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CPU (4/9) PM,XDP,CLK,CFG
5 4 3 2 1
5 4 3 2 1
UC1O
DDR4(IL) / DDR4(NIL) / DDR5(IL)
15 OF 15 CPU_EDP_TX3_P
AL8 AU36 CPU_EDP_TX3_P 45
NC/NC/DDR3_DQSP_4 DDIA_TXP_3 CPU_EDP_TX3_N
AL9 AU37 CPU_EDP_TX3_N 45
NC/NC/DDR3_DQSN_4 DDIA_TXN_3 CPU_EDP_TX2_P
AL3 AV40 CPU_EDP_TX2_P 45
NC/NC/DDR1_DQSP_4 DDIA_TXP_2 CPU_EDP_TX2_N
AL4 AV41 CPU_EDP_TX2_N 45
NC/NC/DDR1_DQSN_4 DDIA_TXN_2 CPU_EDP_TX1_P
AV37 CPU_EDP_TX1_P 45
DDIA_TXP_1 CPU_EDP_TX1_N
AJ8 AV38 CPU_EDP_TX1_N 45
D NC/NC/DDR3_DQ4_3 DDIA_TXN_1 CPU_EDP_TX0_P D
AJ9 AW39 CPU_EDP_TX0_P 45
NC/NC/DDR3_DQ4_2 DDIA_TXP_0 CPU_EDP_TX0_N
AJ6 AW40 CPU_EDP_TX0_N 45
NC/NC/DDR3_DQ4_1 DDIA_TXN_0
AH7
NC/NC/DDR3_DQ4_0 CPU_EDP_AUXP
AJ3 BA40 CPU_EDP_AUXP 45
NC/NC/DDR1_DQ4_3 DDIA_AUX_P CPU_EDP_AUXN
AJ4 BA41 CPU_EDP_AUXN 45
NC/NC/DDR1_DQ4_2 DDIA_AUX_N
AJ1
NC/NC/DDR1_DQ4_1 EDP_RCOMP RC49 1 2 150_0402_1%
AH2 BC38
NC/NC/DDR1_DQ4_0 DDIA_RCOMP
DDR4 / DDR5 BD39
RSVD_4
BT9
NC/DDR2_CLK_N2
BT8 AW36
NC/DDR2_CLK_P2 DDIB_TXP_3
BT4 AW37
NC/DDR0_CLK_N2 DDIB_TXN_3
BT3 BB39
AT2 BB40
AT1 BA37
AT7 BA38
AT6 BB36
BB37
DDIB_TXN_0
BT6
NC/DDR2_CLK_P3
BT7 BC35
NC/DDR2_CLK_N3 DDIB_AUX_P
BT1 BC36
NC/DDR0_CLK_P3 DDIB_AUX_N
BT2
NC/DDR0_CLK_N3
AT3 U39
NC/DDR1_CLK_P3 CSI_A_CLK_P
AT4 U40
NC/DDR1_CLK_N3 CSI_A_CLK_N
AT8 R37
NC/DDR3_CLK_P3 CSI_A_DP_1/CSI_B_DP_2
AT9 R38
NC/DDR3_CLK_N3 CSI_A_DN_1/CSI_B_DN_2
U36
CSI_A_DP_0/CSI_B_DP_3
BH9 U37
NC/NC_1 CSI_A_DN_0/CSI_B_DN_3
BH8
NC/NC_2
BG9 R40
NC/NC_3 CSI_B_CLK_P
BH4 R41
NC/NC_4 CSI_B_CLK_N
BH3 P36
NC/NC_5 CSI_B_DP_1
BG4 P37
NC/NC_6 CSI_B_DN_1
AY1 P39
NC/NC_7 CSI_B_DP_0
AW1 P40
NC/DDR1_CS2 CSI_B_DN_0
BD3 R35 CSI_RCOMP RC884 1 2 1/20W_150_1%_0201
NC/NC_8 CSI_RCOMP
BF2
NC/NC_9
C BE8 C
NC/NC_10
BE3
NC/DDR1_CS3
BG3
NC/DDR0_CS2
BG8
NC/DDR2_CS2
AW7
NC/DDR3_CS2
BD8
NC/NC_11
BF7
NC/NC_12
BD7
NC/DDR3_CS3
C40
NC_1
CR40
NC_2
CR2
NC_3
C2
NC_4
@
B B
A A

X60-TGL-H
C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CPU (5/9) eDP
5
Vinafix.com
4 3 2 1
5 4 3 2 1
UC1D
4 OF 15
TCP0_CTX_DRX1_P BL38 AC40 GPU_IFPA_TX3_C_P CC456 1 2 0.1u_0201_10V6K GPU_IFPA_TX3_P
52 TCP0_CTX_DRX1_P TCP0_CTX_DRX1_N TCP0_TX_P1 DPIP3_RXP_3 GPU_IFPA_TX3_C_N GPU_IFPA_TX3_N GPU_IFPA_TX3_P 29
BL37 AC41 CC455 1 2 0.1u_0201_10V6K
52 TCP0_CTX_DRX1_N TCP0_CTX_DRX0_P TCP0_TX_N1 DPIP3_RXN_3 GPU_IFPA_TX2_C_P GPU_IFPA_TX2_P GPU_IFPA_TX3_N 29
BP37 AD39 CC458 1 2 0.1u_0201_10V6K
52 TCP0_CTX_DRX0_P TCP0_CTX_DRX0_N TCP0_TX_P0 DPIP3_RXP_2 GPU_IFPA_TX2_C_N GPU_IFPA_TX2_N GPU_IFPA_TX2_P 29
BP38 AD40 CC457 1 2 0.1u_0201_10V6K
52 TCP0_CTX_DRX0_N TCP0_CRX_DTX1_P TCP0_TX_N0 DPIP3_RXN_2 GPU_IFPA_TX1_C_P GPU_IFPA_TX1_P GPU_IFPA_TX2_N 29
BK40 AC37 CC460 1 2 0.1u_0201_10V6K
52 TCP0_CRX_DTX1_P TCP0_CRX_DTX1_N TCP0_TXRX_P1 DPIP3_RXP_1 GPU_IFPA_TX1_C_N GPU_IFPA_TX1_N GPU_IFPA_TX1_P 29
TBT port1 BK41 AC38 CC459 1 2 0.1u_0201_10V6K DPIN port1
52 TCP0_CRX_DTX1_N TCP0_CRX_DTX0_P TCP0_TXRX_N1 DPIP3_RXN_1 GPU_IFPA_TX0_C_P GPU_IFPA_TX0_P GPU_IFPA_TX1_N 29
BL41 AD36 CC462 1 2 0.1u_0201_10V6K
52 TCP0_CRX_DTX0_P TCP0_CRX_DTX0_N TCP0_TXRX_P0 DPIP3_RXP_0 GPU_IFPA_TX0_C_N GPU_IFPA_TX0_N GPU_IFPA_TX0_P 29
BL40 AD37 CC461 1 2 0.1u_0201_10V6K
52 TCP0_CRX_DTX0_N TCP0_TXRX_N0 DPIP3_RXN_0 GPU_IFPA_TX0_N 29
TCP0_AUX_P BN37 AN38 GPU_IFPA_C_AUXP CC454 1 2 0.1u_0201_10V6K GPU_IFPA_AUXP
52 TCP0_AUX_P TCP0_AUX_N TCP0_AUX_P DPIP3_AUX_P GPU_IFPA_C_AUXN GPU_IFPA_AUXN GPU_IFPA_AUXP 29
BN38 AN39 CC453 1 2 0.1u_0201_10V6K
52 TCP0_AUX_N TCP0_AUX_N DPIP3_AUX_N GPU_IFPA_AUXN 29 +3VS
BD40 AE40
RSVD_TP_1 DPIP2_RXP_3
BD41 AE41
RSVD_TP_2 DPIP2_RXN_3
1
BD37 AF39 +3VS +3VS
D RSVD_TP_3 DPIP2_RXP_2 RC880 D
BD36 AF40
RSVD_TP_4 DPIP2_RXN_2 @ 1/20W_1M_5%_0201
AF36
DPIP2_RXP_1
1
RC61 1 2 2.2K_0402_1% TCP0_MBIAS_RCOMP BP41 AF37
TCP0_MBIAS_RCOMP DPIP2_RXN_1 RC896 RC898
BP40 AG37
2
RSVD_TP_5 DPIP2_RXP_0 @ @ GPU_IFPA_AUXP
AG38 100K_0201_5% 100K_0201_5%
DPIP2_RXN_0 GPU_IFPA_AUXN
BG38
TCP1_TX_P1
BG37 AR39
2
TCP1_TX_N1 DPIP2_AUX_P
1
BJ37 AR40 GPU_IFPA_C_AUXN GPU_IFPB_C_AUXN
TCP1_TX_P0 DPIP2_AUX_N GPU_IFPA_C_AUXP GPU_IFPB_C_AUXP RC881
BJ38
TCP1_TX_N0 @ 1/20W_1M_5%_0201
BG40 AG40
TCP1_TXRX_P1 DPIP1_RXP_3
1
BG41 AG41
TCP1_TXRX_N1 DPIP1_RXN_3 RC897 RC899
BH41 AJ39
2
TCP1_TXRX_P0 DPIP1_RXP_2 @ @
BH40 AJ40 100K_0201_5% 100K_0201_5%
TCP1_TXRX_N0 DPIP1_RXN_2
AJ36
DPIP1_RXP_1
BH37 AJ37
2
TCP1_AUX_P DPIP1_RXN_1
BH38 AK37
TCP1_AUX_N DPIP1_RXP_0
AK38
TCP2_CTX_DRX1_P DPIP1_RXN_0
55 TCP2_CTX_DRX1_P BW37
TCP2_CTX_DRX1_N TCP2_TX_P1
55 TCP2_CTX_DRX1_N BW38 AR36
TCP2_CTX_DRX0_P TCP2_TX_N1 DPIP1_AUX_P
55 TCP2_CTX_DRX0_P BT38 AR37
TCP2_CTX_DRX0_N TCP2_TX_P0 DPIP1_AUX_N
55 TCP2_CTX_DRX0_N BT37
TCP2_CRX_DTX1_P TCP2_TX_N0 GPU_IFPB_TX3_C_P CC465 1 2 0.1u_0201_10V6K GPU_IFPB_TX3_P
55 TCP2_CRX_DTX1_P BW41 AL36 GPU_IFPB_TX3_P 29
TBT port2 TCP2_CRX_DTX1_N TCP2_TXRX_P1 DPIP0_RXP_3 GPU_IFPB_TX3_C_N CC466 1 2 0.1u_0201_10V6K GPU_IFPB_TX3_N
55 TCP2_CRX_DTX1_N BW40 AL37 GPU_IFPB_TX3_N 29
TCP2_CRX_DTX0_P TCP2_TXRX_N1 DPIP0_RXN_3 GPU_IFPB_TX2_C_P CC468 1 2 0.1u_0201_10V6K GPU_IFPB_TX2_P
55 TCP2_CRX_DTX0_P BU40 AK40 GPU_IFPB_TX2_P 29
TCP2_CRX_DTX0_N TCP2_TXRX_P0 DPIP0_RXP_2 GPU_IFPB_TX2_C_N CC467 1 2 0.1u_0201_10V6K GPU_IFPB_TX2_N
55 TCP2_CRX_DTX0_N BU41 AK41 GPU_IFPB_TX2_N 29
TCP2_TXRX_N0 DPIP0_RXN_2 GPU_IFPB_TX1_C_P CC470 1 2 0.1u_0201_10V6K GPU_IFPB_TX1_P
AL39 GPU_IFPB_TX1_P 29
TCP2_AUX_P DPIP0_RXP_1 GPU_IFPB_TX1_C_N CC469 1 2 0.1u_0201_10V6K GPU_IFPB_TX1_N DPIN port2
55 TCP2_AUX_P BU38 AL40 GPU_IFPB_TX1_N 29
TCP2_AUX_N TCP2_AUX_P DPIP0_RXN_1 GPU_IFPB_TX0_C_P CC472 1 2 0.1u_0201_10V6K GPU_IFPB_TX0_P
55 TCP2_AUX_N BU37 AM37 GPU_IFPB_TX0_P 29
TCP2_AUX_N DPIP0_RXP_0 GPU_IFPB_TX0_C_N CC471 1 2 0.1u_0201_10V6K GPU_IFPB_TX0_N
AM38 GPU_IFPB_TX0_N 29
DPIP0_RXN_0
CD37
TCP3_TX_P1 GPU_IFPB_C_AUXP CC464 1 2 0.1u_0201_10V6K GPU_IFPB_AUXP
CD38 AT37 GPU_IFPB_AUXP 29
TCP3_TX_N1 DPIP0_AUX_P GPU_IFPB_C_AUXN CC463 1 2 0.1u_0201_10V6K GPU_IFPB_AUXN
CB38 AT38 GPU_IFPB_AUXN 29
TCP3_TX_P0 DPIP0_AUX_N +3VS
CB37
TCP3_TX_N0
CC41 AM41
TCP3_TXRX_P1 RSVD_TP_6
CC40 AM40
TCP3_TXRX_N1 RSVD_TP_7
1
CB40 AN41
TCP3_TXRX_P0 RSVD_TP_8 RC882
CB41
TCP3_TXRX_N0 DPIP3_HPD @ 1/20W_1M_5%_0201
C AC35 C
DPIP3_HPD DPIP2_HPD RC878 1 2 100K_0201_5% follow CRB no use port, HPD left un-connector
CC38 AE37
TCP3_AUX_P DPIP2_HPD DPIP1_HPD RC879 1 2 100K_0201_5% PDG 100K pull-down
CC37 AE35
2
TCP3_AUX_N DPIP1_HPD DPIP0_HPD GPU_IFPB_AUXP
AE38
DPIP0_HPD GPU_IFPB_AUXN
D34
RSVD_3 DPIP3_RCOMP RC856 1 2 1/20W_150_1%_0201
E34 AT41
DISP_UTILS DPIP3_RCOMP
1
AU40 DPIP2_RCOMP RC876 1 2 1/20W_150_1%_0201
RC180 2 1 20_0402_5% PROC_AUDIO_SDI_CPU_R DPIP2_RCOMP DPIP1_RCOMP RC877 1 2 1/20W_150_1%_0201 need confirm DP RCOMP if stuff when un-used? RC883
20 PROC_AUDIO_SDI_CPU A32 AU39
PROC_AUDIO_SDO_CPU AUDOUT DPIP1_RCOMP DPIP0_RCOMP RC857 1 2 1/20W_150_1%_0201 @ 1/20W_1M_5%_0201
20 PROC_AUDIO_SDO_CPU A31 AT40
+VCCSTG_CPU PROC_AUDIO_CLK_CPU AUDIN DPIP0_RCOMP
20 PROC_AUDIO_CLK_CPU B32
AUDCLK
2
1
CPU_EAR_N F36
RC762 EAR#
1
@ 1/20W_33_5%_0201
RC31
TIGERLAKE-H-CPU_BGA1787 +1.8VS_VGA
1K_0201_5%
2
@
1
2
@ CC185
1
CPU_EAR_N 10P_50V_G_NPO_0201
2 RC860
10K_0402_5%
1
RC34 Plug in: High
2
1K_0201_5% UC2 IFPA_HPD
PCH_IFPA_HPD PCH_DPIN_HPD IFPA_HPD 31
1 4 QC505
IN B OUT Y PCH_DPIN_HPD 18
2
PCH_IFPB_HPD 2 MMBT3904WH_SOT323-3
2
IN A
1
C RC885
@ DPIP3_HPD DPIP3_HPD_R
3 5 +3VS RC861 1 2 2 100K_0201_5%
GND Vcc
2
1K_0201_5% B
RC891 E
1
2
MC74VHC1G32DFT2G_SC70-5 100K_0201_5% 1
Stall CPU reset sequence until de-asserted CC1538 RC862
@ 220P_0402_50V7K @ 100K_0201_5%
1
2
 1 (Default) Normal Operation;
*
1
CPU_EAR_N No stall.
B B
 0 Stall. +3VS
1
+3VS +1.8VS_VGA
Disabling and Termination Guidelines
RC889
*
1
10K_0201_5%
1
DPIPx_HPD Pull down to ground via 100k resistor
2
RC892 PCH_IFPA_HPD RC864

10K_0201_5% 10K_0402_5%
6
D
2
DPIP3_HPD_L 2 QC507A
2
G LBSS138DW1T1G_SOT363-6 QC506 IFPB_HPD
IFPB_HPD 31
1
S MMBT3904WH_SOT323-3
1
1
QC508 C
LSI1012XT1G_SC-89-3 DPIP0_HPD RC865 1 2 DPIP0_HPD_R 2
2
DPIP3_HPD 2 1K_0201_5% B
2
1 E RC886
3
2
DPIP_HPD Voltage is 0.98V CC1540 RC867 100K_0201_5%

3
RC893 Vgs(th)≤0.9V @ 220P_0402_50V7K @ 100K_0201_5%

100K_0201_5%
1
2
1
+3VS
1
+3VS
RC890
1
10K_0201_5%
2
RC894 PCH_IFPB_HPD
10K_0201_5%
3
D
2
DPIP0_HPD_L 5 QC507B
G LBSS138DW1T1G_SOT363-6
1
S
4
QC509
A LSI1012XT1G_SC-89-3 A
DPIP0_HPD 2
2
DPIP_HPD Voltage is 0.98V

3
RC895
100K_0201_5% Vgs(th)≤0.9V
1

X60-TGL-H
Vinafix.com
C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CPU (6/9) DDI,TBT
5 4 3 2 1
5 4 3 2 1
+VCCIO from PWR +VCCIN +VCCIN

VCCIN_AUX +VCCIN need confirm power side net name UC1J
UC1L UC1K +VCCIN 10 OF 15
+VCCST_CPU
35A 105A 11 OF 15 AB11
VCCIN_140 VCCIN_215
CB30
AA34 12 OF 15 G35 CG16 CN30 AC11 CB31
VCCIN_AUX_1 VCCIO_OUT VCCIN_1 VCCIN_73 VCCIN_141 VCCIN_216
AA36
VCCIN_AUX_2 0.97A CG17
VCCIN_2 VCCIN_74
CN31 AC12
VCCIN_142 VCCIN_217
CB33
AA39 P20 CG18 CN33 AD11 CB34
VCCIN_AUX_3 VCCST_1 VCCIN_3 VCCIN_75 VCCIN_143 VCCIN_218 CRB place to CPU
AB33 R20 CG20 CN34 AD12 CB35
VCCIN_AUX_4 VCCST_2 +VCCSTG_FUSE VCCIN_4 VCCIN_76 VCCIN_144 VCCIN_219
AD34 R22 CG21 CN35 AV33 CC12
VCCIN_AUX_5 VCCST_3 VCCIN_5 VCCIN_77 VCCIN_145 VCCIN_220 VCCIN_AUX
AE33 CG22 CN36 AV34 CC13
VCCIN_AUX_6 +VCCSTG_OUT VCCIN_6 VCCIN_78 VCCIN_146 VCCIN_221
AF33 P17 CG23 CN38 AV35 CC14
VCCIN_AUX_7 VCCSTG_1 VCCIN_7 VCCIN_79 VCCIN_147 VCCIN_222
AF34
AG34
VCCIN_AUX_8
VCCIN_AUX_9
VCCSTG_2
R17
+VCCSTG_FPGM
CG24
CG25
VCCIN_8
VCCIN_9
VCCIN_80
VCCIN_81
CN39
CN40
AW34
BA34
VCCIN_148
VCCIN_149
VCCIN_223
VCCIN_224
CC16
CC17 AUX_CPU_SENSE
1
AG35 T17 CG27 CN41 BA35 CC18 RC59
VCCIN_AUX_10 VCCSTG_OUT_1 VCCIN_10 VCCIN_82 VCCIN_150 VCCIN_225 100_0402_1%
AH33 CG28 CP28 BB34 CC20
D VCCIN_AUX_11 VCCIN_11 VCCIN_83 VCCIN_151 VCCIN_226 D
AJ33 P13 CG30 CP30 BD33 CC21
VCCIN_AUX_12 VCCSTG_OUT_2 VCCIN_12 VCCIN_84 VCCIN_152 VCCIN_227
AJ34 R13 CG31 CP33 BD34 CC22
AK34 T13 CG33 CP34 BE34 CC23
2
BH11 R15 CG34 CP38 BE35 CC24
BK11 T15 CG35 CP39 BG34 CC25
VCCIN_AUX_16 VCCSTG_OUT_6 VCCIN_16 VCCIN_88 VCCIN_156 VCCIN_231 VCCIN_AUX_VCCSEN
BK12 CG36 CP40 BG35 CC27 96 VCCIN_AUX_VCCSEN
VCCIN_AUX_17 VCCIN_17 VCCIN_89 VCCIN_157 VCCIN_232
BL11 B5 CG37 CP41 BH33 CC28
VCCIN_AUX_18 RSVD_15 +VCC1P8A_CPU VCCIN_18 VCCIN_90 VCCIN_158 VCCIN_233
BL12 P28 CG38 CR28 BH34 CC30
VCCIN_AUX_19 RSVD_16 VCCIN_19 VCCIN_91 VCCIN_159 VCCIN_234
BM11 CT4 CG39 CR30 BH35 CC31
VCCIN_AUX_20 RSVD_17 VCCIN_20 VCCIN_92 VCCIN_160 VCCIN_235
U24 CG40 CR31 BJ34 CC33
U28 AM35 CG41 CR32 BJ35 CC34
VCCIN_AUX_22 VCC1P8A_1 VCCIN_22 VCCIN_94 VCCIN_162 VCCIN_237 VCCIN_AUX_VSSSEN
U31 AN33 CH24 CR33 BK34 CC35 96 VCCIN_AUX_VSSSEN
VCCIN_AUX_23 VCC1P8A_2 VCCIN_23 VCCIN_95 VCCIN_163 VCCIN_238
V24
VCCIN_AUX_24 VCC1P8A_3
AN34 0.5A CH27
VCCIN_24 VCCIN_96
CR34 BK35
VCCIN_164 VCCIN_239
CD12
V26 AN35 CH28 CR35 BL33 CD14
1
V28 AP33 CH33 CR36 BL34 CD16
V29 AR34 CH34 CR38 BL35 CD18
VCCIN_AUX_27 VCC1P8A_6 VCCIN_27 VCCIN_99 VCCIN_167 VCCIN_242 RC62
V31 AT33 CH38 CR39 BN34 CD20
VCCIN_AUX_28 VCC1P8A_7 VCCIN_28 VCCIN_100 VCCIN_168 VCCIN_243 100_0402_1%
V33 AT34 CH39 CT28 BN35 CD22
V34 AT35 CJ24 CT30 BP34 CD23
2
VCCIN_AUX_30 VCC1P8A_9 +VCCIN_AUX_FIL VCCIN_30 VCCIN_102 VCCIN_170 VCCIN_245
V35 AU34 CJ27 CT31 BP35 CD25
V38 CJ28 CT32 BR33 CD27
W24 AK35 CJ30 CT33 BR34 CD30
VCCIN_AUX_33 VCCIN_AUX_59 VCCIN_33 VCCIN_105 VCCIN_173 VCCIN_248
W26 AL34 CJ31 CT34 BR35 CD31
VCCIN_AUX_34 VCCIN_AUX_60 +VCCSTG_CPU VCCIN_34 VCCIN_106 VCCIN_174 VCCIN_249
W28 CJ33 CT35 BT11 CD34
W29 L34 CJ34 CT36 BT34 CD35
W31
VCCIN_AUX_37 VCCSTG_4
M34 0.34A CJ35
VCCIN_37 VCCIN_109
CT38 BT35
VCCIN_177 VCCIN_252
CE12
W33 N34 CJ36 CT39 BU34 CE13
W34 P34 CJ38 CT40 BU35 CE14
W35 CJ39 CT41 BV11 CE16
W36 CJ40 CU28 BV12 CE18
W37 CJ41 CU30 BV33 CE20
W38 CK24 CU33 BW11 CE22
W39
VCCIN_AUX_43
CK25
VCCIN_43 VCCIN_115
CU34 BW12
VCCIN_183 VCCIN_258
CE23 CRB place to CPU
CK27 CU38 BW33 CE25
VCCIN_45 VCCIN_117 VCCIN_185 VCCIN_260 +VCCIN
W40 CK28 CU39 BW34 CE27
W41
Y24
VCCIN_AUX_45
VCCIN_AUX_46
VCCIN_AUX_47
CK30
CK31
VCCIN_46
VCCIN_47
VCCIN_48
VCCIN_118
VCCIN_119
VCCIN_120
T18
U18
BW35
BY12
VCCIN_186
VCCIN_187
VCCIN_188
VCCIN_261
VCCIN_262
VCCIN_263
CE30
CE31
VCCIN_SENSE
1
C Y28 CK33 U20 BY34 CE34 RC60 C
VCCIN_AUX_48 VCCIN_49 VCCIN_121 VCCIN_189 VCCIN_264 100_0402_1%
Y29 CK34 V12 BY35 CE35
Y33 CK35 V13 CA14 CF13
Y34 CK36 V15 CA16 CF14
Y35 CL27 V17 CA18 CF16
2
Y36 CL28 V18 CA20 CF17 95 VCCIN_SENSE
Y37 CL33 V20 CA22 CF18
Y38 CL34 W11 CA23 CF20 95 VSSIN_SENSE
Y39 CL38 W13 CA25 CF21
1
Y40 CL39 W15 CA27 CF22
Y41 CL40 W17 CA30 CF23
VCCIN_AUX_58 VCCIN_59 VCCIN_131 VCCIN_199 VCCIN_274 RC63
CL41 W18 CA31 CF24
VCCIN_60 VCCIN_132 VCCIN_200 VCCIN_275 100_0402_1%
CM27 W20 CB12 CF25
VCCIN_61 VCCIN_133 VCCIN_201 VCCIN_276
TIGERLAKE-H-CPU_BGA1787 CM28 Y11 CB13 CF27
2
CM30 Y12 CB14 CF28
@ VCCIN_63 VCCIN_135 VCCIN_203 VCCIN_278
CM31 Y13 CB16 CF30
CM33 Y15 CB17 CF31
CM34 Y18 CB18 CF33
CM35 Y20 CB20 CF34
+VCCSTG_OUT VCCIN_67 VCCIN_139 VCCIN_207 VCCIN_282
CM36 CB21 CF35
+VCCSTG_FUSE VCCIN_68 VSSIN_SENSE VCCIN_208 VCCIN_283
CM38 CE41 CB22 CF36
VCCIN_69 VCCIN_VSS_SENSE VCCIN_SENSE VCCIN_209 VCCIN_284
CM39 CE40 CB23 CF38
LC1 1 @ 2 0_0603_5% VCCIN_70 VCCIN_VCCSENSE VCCIN_210 VCCIN_285
CN27 CB24 CF39
VCCIN_71 VCCIN_AUX_VSSSEN VCCIN_211 VCCIN_286
CN28 U33 CB25 CF40
+VCCSTG_FPGM VCCIN_72VCCIN_AUX_VSS_SENSE VCCIN_AUX_VCCSEN VCCIN_212 VCCIN_287
U34 CB27 CF41
VCCIN_AUX_VCCSENSE VCCIN_213 VCCIN_288
CB28 CG14
LC2 1 2 1/10W_0_5%_0603 VCCIN_214 VCCIN_289
1 TIGERLAKE-H-CPU_BGA1787
@
CC451 @
1U_0402_6.3V6K
2
B from PWR +VCCSTG_CPU +VCCSTG_FPGM B

+1.8VALW +VCC1P8A_CPU need confirm power side net name +VCCST_CPU
LC6 1 @ 2 0_0603_5% VCCIN_AUX +VCCIN_AUX_FIL
1U_0402_6.3V6K
1
+1.8VALW_CPU
1U_0402_6.3V6K
1U_0402_6.3V6K
CC180
1 1
1U_0402_6.3V6K
1U_0402_6.3V6K
CC251
CC252
1 1
CC250
CC253
@
LC7 1 @ 2 1/10W_0_5%_0603 LC3 1 2 1/10W_0_5%_0603 @ 2
2 2
10U 6.3V M X5R 0402 2 2
1 1 1 CC34
@
CC35 CC1541 @
10U 6.3V M X5R 0402
2 2 2
2
2
U
C
_
6.
3
V
C
_
M
C
_
X
5
R
C
_
0
6
0
3
A A

X60-TGL-H
Vinafix.com
C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CPU (7/9) PWR,BYPASS
5 4 3 2 1
5 4 3 2 1
UC1N +1.2V
14 OF 15 4.3A
L15 AH11
VSS_572 VDD2_1
L18 AH12
VSS_573 VDD2_2
L2 AJ11
VSS_574 VDD2_3
L22 AJ12
VSS_575 VDD2_4
L26 AL11
VSS_576 VDD2_5
L29 AM11
VSS_577 VDD2_6
L33 AM12
VSS_578 VDD2_7
L35 AN11
VSS_579 VDD2_8
L36 AN12
VSS_580 VDD2_9
L38 AR11
VSS_581VDD2_10
L5 AR5
D VSS_582VDD2_11 D
L7 AT11
VSS_583VDD2_12
M33 AT12
VSS_584VDD2_13
M36 AT5
VSS_585VDD2_14
M40 AV10
VSS_586VDD2_15
N1 AV11
VSS_587VDD2_16
N10 AW10
VSS_588VDD2_17
N13 AW11
VSS_589VDD2_18
N17 AW12
VSS_590VDD2_19
N20 AW5
VSS_591VDD2_20
N24 AY11
VSS_592VDD2_21
N28 AY5
VSS_593VDD2_22
N3 BA11
VSS_594VDD2_23
N31 BC10
VSS_595VDD2_24
N33 BC11
VSS_596VDD2_25
N35 BC12
VSS_597VDD2_26
N37 BD10
VSS_598VDD2_27
N38 BD11
VSS_599VDD2_28
N4 BD5
VSS_600VDD2_29
N5 BE11
VSS_601VDD2_30
N6 BE5
VSS_602VDD2_31
N8 BF11
VSS_603VDD2_32
N9 BF12
VSS_604VDD2_33
P10 BG10
VSS_605VDD2_34
P11 BG11
VSS_606VDD2_35
P15 BH10
VSS_607VDD2_36
P18 BH5
VSS_608VDD2_37
P2 BK5
VSS_609VDD2_38
P22 BM10
VSS_610VDD2_39
P26 BN10
VSS_611VDD2_40
P29 BN5
VSS_612VDD2_41
P33 BP5
VSS_613VDD2_42
P35 BT10
VSS_614VDD2_43
P38 BV10
VSS_615VDD2_44
P41 BV5
VSS_616VDD2_45
P5 BW5
VSS_617VDD2_46
P7
VSS_618
R10 V37
VSS_619VSS_652
C R18 V39 C
VSS_620VSS_653
R2 V4
VSS_621VSS_654
R33 V40
VSS_622VSS_655
R34 V41
VSS_623VSS_656
R36 V5
VSS_624VSS_657
R39 V6
VSS_625VSS_658
R5 V8
VSS_626VSS_659
R7 V9
VSS_627VSS_660
T20 W10
VSS_628VSS_661
T22 W2
VSS_629VSS_662
T24 W22
VSS_630VSS_663
T28 W5
VSS_631VSS_664
T31 W7
VSS_632VSS_665
U10 Y10
VSS_633VSS_666
U13 Y17
VSS_634VSS_667
U15 Y2
VSS_635VSS_668
U17 Y22
VSS_636VSS_669
U2 Y26
VSS_637VSS_670
U22 Y31
VSS_638VSS_671
U26 Y5
VSS_639VSS_672
U29 Y7
VSS_640VSS_673
U35
VSS_641
U38
VSS_642
U41
VSS_643
U5
VSS_644
U7
VSS_645
V1
VSS_646
V10
VSS_647
V11
VSS_648
V22
VSS_649
V3
VSS_650
V36
VSS_651
@
B B
A A

X60-TGL-H
C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CPU (8/9) PWR,BYPASS
5 4 3 2 1
Vinafix.com
5 4 3 2 1
UC1F UC1G UC1H

6 OF 15 7 OF 15 8 OF 15
D D
A11 AL1 BA3 BN36 CB39 CK5 UC1I
VSS_412VSS_492 VSS_252VSS_332 VSS_92 VSS_172
A14 AL10 BA36 BN39 CC10 CK6 9 OF 15
VSS_413VSS_493 VSS_253VSS_333 VSS_93 VSS_173
A17 AL12 BA39 BN4 CC2 CK8 CU27 G15
VSS_414VSS_494 VSS_254VSS_334 VSS_94 VSS_174 VSS_1 VSS_46
A20 AL2 BA4 BN40 CC36 CK9 CU3 G17
A23 AL33 BA5 BN41 CC39 CL12 CU31 G18
A27 AL35 BA6 BN6 CC5 CL14 CU32 G20
A29 AL38 BA7 BN8 CC7 CL16 CU35 G22
A3 AL41 BA8 BP10 CD10 CL17 CU36 G24
A36 AL5 BA9 BP12 CD13 CL20 CU4 G26
VSS_420VSS_500 VSS_260VSS_340 VSS_100VSS_180 VSS_7 VSS_52
A37 AL6 BB33 BP36 CD17 CL21 CU40 G28
A39 AL7 BB35 BP39 CD2 CL22 CU5 G29
A4 AM1 BB38 BR1 CD21 CL23 CU9 G3
A5 AM10 BB41 BR10 CD24 CL24 D11 G31
A6 AM34 BC34 BR2 CD28 CL25 D14 G33
A9 AM36 BC37 BR3 CD33 CL30 D17 G34
AA12 AM39 BC39 BR36 CD36 CL31 D20 G37
AA35 AM4 BC40 BR37 CD39 CL35 D23 G4
AA37 AM5 BC41 BR38 CD40 CL36 D27 G5
AA38 AM6 BC5 BR39 CD41 CM10 D29 G6
AA40 AM8 BD2 BR4 CD5 CM13 D31 G8
AA41 AN10 BD35 BR5 CD7 CM18 D37 G9
AB10 AN2 BD38 BR6 CE1 CM2 D4 H10
VSS_436VSS_516 VSS_276VSS_356 VSS_116VSS_196 E11 VSS_23 VSS_68
AB7 AN5 BE10 BT12 CE24 CM5 H22
AC1 AN7 BE12 BT36 CE28 CM7 E31 H26
AC10 AR12 BE2 BT39 CE3 CN1 E36 H29
AC33 AR33 BE37 BT41 CE36 CN12 E41 H38
AC36 AR38 BE39 BU33 CE38 CN14 E6 H7
AC39 AR41 BE40 BU36 CE39 CN16 F10 J33
AC4 AR6 BE41 BU39 CE4 CN17 F11 J34
AC5 AR8 BE7 BV2 CE5 CN18 F13 J36
AC6 AT10 BF1 BV4 CE6 CN20 F16 J39
AC8 AT36 BF10 BV6 CE8 CN21 F18 K10
C AC9 AT39 BF3 BV9 CE9 CN22 F22 K11 C
AD10 AU1 BF33 BW10 CF10 CN23 F25 K13
AD2 AU10 BF4 BW36 CF12 CN4 F28 K17
AD35 AU11 BF5 BW39 CF2 CN5 F31 K2
AD38 AU12 BF6 BY1 CF5 CN7 F40 K20
AD41 AU2 BF8 BY10 CF7 CP1 F6 K24
AD5 AU3 BF9 BY3 CG13 CP14 F8 K28
AD7 AU35 BG2 BY36 CH10 CP2 G1 K31
AE34 AU38 BG36 BY37 CH12 CP20 G10 K5
VSS_457VSS_537 VSS_297VSS_377 VSS_137VSS_217 G13 VSS_44 VSS_89
AE36 AU4 BG39 BY38 CH13 CP27 K7
AE39 AU41 BG5 BY39 CH14 CP3 L10
VSS_459VSS_539 VSS_299VSS_379 VSS_139VSS_219 VSS_91
AF10 AU5 BG7 BY4 CH16 CP31
VSS_460VSS_540 VSS_300VSS_380 VSS_140VSS_220
AF12 AU6 BH12 BY40 CH17 CP32
AF2 AU7 BH2 BY41 CH18 CP35 TIGERLAKE-H-CPU_BGA1787
AF41 AV2 BH7 BY8 CH21 CP7
AF5 AV36 BJ36 BY9 CH22 CP8
AF7 AV39 BJ39 C1 CH23 CP9
AG10 AV5 BJ40 C10 CH25 CR1
AG2 AV7 BJ41 C13 CH30 CR14
AG33 AW2 BK10 C16 CH31 CR20
AG36 AW33 BK33 C18 CH35 CR27
AG39 AW35 BK36 C22 CH36 CR41
AH1 AW41 BK39 C3 CH5 CT1
AH10 AW6 BL1 C31 CH7 CT11
AH3 AW9 BL10 C32 CJ10 CT12
AH4 AY10 BL2 C34 CJ13 CT13
AH5 AY12 BL3 C8 CJ18 CT16
AH6 AY4 BL36 CA10 CJ2 CT17
AH8 AY6 BL39 CA12 CJ23 CT18
AH9 B2 BL4 CA13 CJ25 CT2
AJ10 B31 BL5 CA17 CJ5 CT20
AJ2 B34 BL6 CA2 CJ7 CT22
AJ35 B36 BL7 CA21 CK1 CT27
B VSS_486VSS_566 VSS_326VSS_406 VSS_166VSS_246 B
AJ5 B6 BM12 CA33 CK18 CT8
AJ7 BA1 BM5 CA5 CK23 CU14
AK36 BA10 BN2 CA7 CK3 CU2
AK39 BA2 BN33 CB36 CK4 CU20
TIGERLAKE-H-CPU_BGA1787 TIGERLAKE-H-CPU_BGA1787 TIGERLAKE-H-CPU_BGA1787

@ @ @
A A

X60-TGL-H
Vinafix.com
C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CPU (9/9) PWR,VSS
5 4 3 2 1
5 4 3 2 1
UH1E
AF3 5 OF 9 C36 PCIE_SATA_PTX_DRX12_P

24 PCH_PRDY_N PRDY# PCIE12_TXP/SATA1A_TXP PCIE_SATA_PTX_DRX12_N PCIE_SATA_PTX_DRX12_P 63
D36 PCIE_SATA_PTX_DRX12_N 63
PCIE12_TXN/SATA1A_TXN PCIE_SATA_PRX_DTX12_P
24 PCH_PREQ_N AF4
PREQ# PCIE12_RXP/SATA1A_RXP
L36
PCIE_SATA_PRX_DTX12_N PCIE_SATA_PRX_DTX12_P 63 NGFF SSD1
J37 PCIE_SATA_PRX_DTX12_N 63
RH13 2 1 30_0402_1% PCH_PM_SYNC PCIE12_RXN/SATA1A_RXN
10 CPU_PM_SYNC AH4
PM_SYNC PCIE_PTX_DRX11_P
D35 PCIE_PTX_DRX11_P 63
PCH_PM_DOWN PCIE11_TXP/SATA0A_TXP PCIE_PTX_DRX11_N
10 PCH_PM_DOWN AH2 C35 PCIE_PTX_DRX11_N 63
PM_DOWN PCIE11_TXN/SATA0A_TXN PCIE_PRX_DTX11_P
CPU_PLTRST_N PCIE11_RXP/SATA0A_RXP
G36
PCIE_PRX_DTX11_N PCIE_PRX_DTX11_P 63 NGFF SSD1
10 CPU_PLTRST_N AE3 H35
PLTRST_CPU# PCIE11_RXN/SATA0A_RXN PCIE_PRX_DTX11_N 63
R287 1 2 1/16W_13_5%_0402 PCH_PECI AH3 D34 PCIE_PTX_DRX10_P
10,79 CPU_PECI PECI PCIE10_TXP PCIE_PTX_DRX10_N PCIE_PTX_DRX10_P 63
PCIE10_TXN
E34 PCIE_PTX_DRX10_N 63 NGFF SSD1
1
D PCIE_PRX_DTX10_P D
V29 J35 PCIE_PRX_DTX10_P 63
CH280 RH11 RH836 RSVD_10 PCIE10_RXP PCIE_PRX_DTX10_N
V28 L34 PCIE_PRX_DTX10_N 63
@ RSVD_11 PCIE10_RXN
1K_0402_5% @ 1K_0402_5% @ 10K_0201_5%
H45 C33 PCIE_PTX_DRX9_P
PCIE24_TXP PCIE9_TXP PCIE_PTX_DRX9_N PCIE_PTX_DRX9_P 63
G45 B33 PCIE_PTX_DRX9_N 63
1
2
PCIE24_TXN PCIE9_TXN PCIE_PRX_DTX9_P
T42
PCIE24_RXP PCIE9_RXP
G33
PCIE_PRX_DTX9_N PCIE_PRX_DTX9_P 63 NGFF SSD1
T43 H33 PCIE_PRX_DTX9_N 63
PCIE24_RXN PCIE9_RXN
J46 B21
PCIE23_TXP PCIE8_TXP
J47 A22
PCIE23_TXN PCIE8_TXN
P35 F24
P37 H24
G47 C23
F47 D23
R39 P19
P41 R19
E48 E20
E49 D20
N43 J21
N42 L21
B44 D21
PCIE20_TXP/SATA7_TXP PCIE5_TXP
A44 C21
PCIE20_TXN/SATA7_TXN PCIE5_TXN
M37 F20
PCIE20_RXP/SATA7_RXP PCIE5_RXP
M35 H20
PCIE20_RXN/SATA7_RXN PCIE5_RXN
D43 D19
PCIE19_TXP/SATA6_TXP PCIE4_TXP/USB31_10_TXP
C43 C20
PCIE19_TXN/SATA6_TXN PCIE4_TXN/USB31_10_TXN EC_RSMRST_N RH59 2 @ 1 100K_0201_5%
L41 P17
PCIE19_RXP/SATA6_RXP PCIE4_RXP/USB31_10_RXP CH304 2 1 0.1U_25V_K_X5R_0402
N39 R17
PCIE19_RXN/SATA6_RXN PCIE4_RXN/USB31_10_RXN EMC_NS@
C42 E17 PCH_PWROK_R RH54 1 2 10K_0201_5%
B42 D17
PCIE18_TXN/SATA5_TXN PCIE3_TXN/USB31_9_TXN
L42 H17
PCIE18_RXP/SATA5_RXP PCIE3_RXP/USB31_9_RXP
K43 G17
PCIE18_RXN/SATA5_RXN PCIE3_RXN/USB31_9_RXN
C C
E41 C18
D42 D18
PCIE17_TXN/SATA4_TXN PCIE2_TXN/USB31_8_TXN
G43 J18
F44 L19
PCIE_PTX_DRX16_P C40 C17
78 PCIE_PTX_DRX16_P PCIE_PTX_DRX16_N PCIE16_TXP/SATA3_TXP PCIE1_TXP/USB31_7_TXP
78 PCIE_PTX_DRX16_N D40 B17
PCIE_PRX_DTX16_P PCIE16_TXN/SATA3_TXN PCIE1_TXN/USB31_7_TXN
Card Reader 78 PCIE_PRX_DTX16_P PCIE_PRX_DTX16_N
C47
J15
78 PCIE_PRX_DTX16_N D46 L16
PCIE_PTX_DRX15_P D39 AB47 PCH_PWROK_R RH12 2 @ 1 0_0201_5%
73 PCIE_PTX_DRX15_P PCIE_PTX_DRX15_N PCIE15_TXP/SATA2_TXP PCH_PWROK PCH_PWROK 79
73 PCIE_PTX_DRX15_N C39
PCIE_PRX_DTX15_P PCIE15_TXN/SATA2_TXN PCH_RTCRST_N
LAN 73 PCIE_PRX_DTX15_P PCIE_PRX_DTX15_N
C46
PCIE15_RXP/SATA2_RXP RTCRST#
AM45
EC_RSMRST_N PCH_RTCRST_N 16,79
73 PCIE_PRX_DTX15_N D45 AA45 EC_RSMRST_N 21,24,79
PCIE15_RXN/SATA2_RXN RSMRST#
PCIE_PTX_DRX14_P E38 AM48 PCH_RTCX2
71 PCIE_PTX_DRX14_P PCIE_PTX_DRX14_N PCIE14_TXP/SATA1B_TXP RTCX2 PCH_RTCX1
71 PCIE_PTX_DRX14_N D38 AM46
PCIE_PRX_DTX14_P PCIE14_TXN/SATA1B_TXN RTCX1
WLAN 71 PCIE_PRX_DTX14_P PCIE_PRX_DTX14_N
H42
PCIE14_RXP/SATA1B_RXP
71 PCIE_PRX_DTX14_N J41
PCIE14_RXN/SATA1B_RXN
SATA_PTX_DRX13_P B37
61 SATA_PTX_DRX13_P SATA_PTX_DRX13_N PCIE13_TXP/SATA0B_TXP
61 SATA_PTX_DRX13_N C38
SATA_PRX_DTX13_P PCIE13_TXN/SATA0B_TXN
SATA for GN20P 61 SATA_PRX_DTX13_P SATA_PRX_DTX13_N
G39
PCIE13_RXP/SATA0B_RXP Emergency Power Loss Early De-assertion of DSW_PWROK control circuit
61 SATA_PRX_DTX13_N H38
PCIE13_RXN/SATA0B_RXN
DH13 @
RH284 1 @ 2 0_0201_5%ALW_PWRGD_R1 2 EC_RSMRST_N
TIGERLAKE-H-PCH_FCBGA943 91,93 ALW_PWRGD
@ RB751V-40_SOD323-2
DH14 @
1 2
PCH_DPWROK 21,79
RB751V-40_SOD323-2
B B
PCH_RTCX1
CMOS RH1 1 2 10M_0402_5% PCH_RTCX2

PCH_SRTCRST_N
1
CH4
VCCRTC 1U_0402_6.3V6K YH1
1
CH77 1 2
2 1000P_0201_50V7-K
RH3 1 2 20K_0402_5% PCH_SRTCRST_N EMC_NS@ 32.768KHZ_9PF_X1A0001410002
PCH_SRTCRST_N 17 1 1
2
RH4 1 2 20K_0402_5% PCH_RTCRST_N CH2 CH3
PCH_RTCRST_N 16,79 10P_0402_50V8J 10P_0402_50V8J
@ 2 2
1
1
CH5 JCMOS1
1U_0402_6.3V6K SHORT PADS
2
A A

X60-TGL-H
C 0.1
PCH (1/8) PCIe/SATA
5
Vinafix.com
4 3
2
Date: Wednesday, April 07, 2021
1
Sheet 16 of 110
5 4 3 2 1
All processor based platforms are required to provide a 38.4MHz input to

the PCH to enable the PCH to generate all of its internal reference clocks
and all of the single-ended and differential platform clock outputs
XTAL_PCH_38P4M_IN RH30 1 @ 2 0_0402_5% XTAL_PCH_38P4M_IN_R
D D
EXC24CH500U_4P
4 3
4 3
1 2
1 2
LC5 EMC_NS@
XTAL_PCH_38P4M_OUT RH32 1 @ 2 0_0402_5% XTAL_PCH_38P4M_OUT_R
XTAL_PCH_38P4M_IN_R RH92 1 2 200K_0402_1% XTAL_PCH_38P4M_OUT_R
YH2
4 3
NC1 OSC2
1 2
OSC1 NC2
m
1 1 UH1F
PDG_0.71 60Ω±1 %
CRB 60.4Ω±1% XTAL_PCH_38P4M_OUT 6 OF 9 USB30_TX4_P
CH9 38.4MHZ_10PF_7R38400001 CH10 AC6 D14 USB30_TX4_P 24
12P_0402_50V8-J 12P_0402_50V8-J need to confirm XTAL_PCH_38P4M_IN XTAL_OUT USB31_4_TXP USB30_TX4_N
AC8 C14
2 2 XTAL_IN USB31_4_TXN
USB31_4_RXP
C11 USB30_RX4_P USB30_TX4_N
USB30_RX4_P
24
24
SFF debug
RH6 1 2 60.4_0402_1% PCH_CLK_BIASREF P3 D11 USB30_RX4_N
XCLK_BIASREF USB31_4_RXN USB30_RX4_N 24
AC17 M13 USB30_TX3_P
RSVD_1 USB31_3_TXP USB30_TX3_N USB30_TX3_P 59
AC15 M15
RSVD_2 USB31_3_TXN USB30_TX3_N 59 Back USB3.0 charge
co
D12 USB30_RX3_P
WAKE_N USB31_3_RXP USB30_RX3_N USB30_RX3_P 59
73,79 PCIE_WAKE_N RH69 1 @ 2 0_0201_5% AD47 E12 USB30_RX3_N 59
WAKE# USB31_3_RXN
RH758 1 @ 2 0_0201_5% PCH_TRIGOUT AL4 F6 USB30_TX2_P
10 CPU_TRIGIN TRIGGER_OUT USB31_2_TXP USB30_TX2_N USB30_TX2_P 78
C AL3 D5 C
10 PCH_TRIGIN TRIGGER_IN USB31_2_TXN
USB31_2_RXP
E11 USB30_RX2_P USB30_TX2_N
USB30_RX2_P
78
78
Type-C
+3VALW_PCH RH34 2 1 620_0402_5% THRMTRIP_PCH_N AD3 G11 USB30_RX2_N
10 THRMTRIP_CPU_N THRMTRIP# USB31_2_RXN USB30_RX2_N 78
AA15 C3 USB30_TX1_P
WAKE_N RSVD_3 USB31_1_TXP USB30_TX1_N USB30_TX1_P 57
RH80 1 2 10K_0201_5% AA17 D4
RSVD_4 USB31_1_TXN
USB31_1_RXP
C10 USB30_RX1_P USB30_TX1_N
USB30_RX1_P
57
57
Back USB3.0 MID
SYS_RESET_N AP3 D10 USB30_RX1_N
.
24 SYS_RESET_N SYS_PWROK_R SYS_RESET# USB31_1_RXN USB30_RX1_N 57
RH193 2 @ 1 0_0201_5% AN5
RH1213 1 2 100K_0201_5% SLP_SUS_N 79 EC_SYS_PWROK SYS_PWROK USB20_14_P
P13
PCH_SRTCRST_N AM47
USB2P_14
P15 USB20_14_N USB20_14_P 71 BT
ap
SYS_PWROK_R 16 PCH_SRTCRST_N SRTCRST# USB2N_14 USB20_14_N 71
RH660 1 2 100K_0201_5%
remove SPI_CS2# AP41 N3
SPI0_CS2# USB2P_13
N4
PCH_SPI0_SO USB2N_13
27 PCH_SPI0_SO AP37
PCH_SPI0_SI SPI0_MISO
27 PCH_SPI0_SI AP35 G3
SPI0_MOSI USB2P_12
G2
PCH_SPI0_IO3 USB2N_12
AM42
27 PCH_SPI0_IO3 PCH_SPI0_IO2 SPI0_IO3 USB20_11_P
AR43 N8 USB20_11_P 59
24,27 PCH_SPI0_IO2 SPI0_IO2 USB2P_11 USB20_11_N
N7
+3VS
27 PCH_SPI0_CS1_N
PCH_SPI0_CS1_N AM43
USB2N_11 USB20_11_N 59 Back USB3.0 charge
16M PCH_SPI0_CS0_N AR42
SPI0_CS1#
J3 USB20_10_P
8M 27 PCH_SPI0_CS0_N SPI0_CS0# USB2P_10 USB20_10_N USB20_10_P 58
J4
USB2N_10 USB20_10_N 58 Back USB3.0 Right
rL
PCH_SPI0_CLK AN39
SYS_RESET_N 27 PCH_SPI0_CLK SPI0_CLK USB20_9_P
RH67 1 2 10K_0201_5% R11
SNDW_RCOMP USB2P_9 USB20_9_N USB20_9_P 82
RH1131 2 1 200_0402_1% BF21 P9
SNDW_RCOMP USB2N_9 USB20_9_N 82 AG
SLP_SUS_N AD46 G5
79,97 SLP_SUS_N SLP_SUS# USB2P_8
H5
TH2967 PAD @ 1 SLP_LAN_N USB2N_8
AC47
+3VALW_PCH SLP_LAN# USB20_7_P
L3 USB20_7_P 80
RH993 2 1 200_0402_1% RCOMP_1P8 USB2P_7 USB20_7_N
BF8 M4
ai RCOMP_1P8 USB2N_7 USB20_7_N 80 RGB
1/20W_4.7K_5%_0201 2 1 RC68 PCH_SPI0_CS0_N R33 L9 USB20_6_P
RSVD_5 USB2P_6 USB20_6_N USB20_6_P 47
Internal 20K PD @PCH P33 N11
1/20W_150K_5%_0201 2 1 RC74 PCH_SPI0_CS1_N
VIH=0.7VCC @SPI ROM
RSVD_6 USB2N_6 USB20_6_N 47 Camera
RH184 2 1 10K_0201_5% USB2_VBUSSENSE E1 M2
USB_VBUSSENSE USB2P_5
M1
B
1/20W_4.7K_5%_0201 1 2 RC70 PCH_SPI0_SI USB2N_5 B
T13
RSVD_7 USB20_4_P
H7
100K_0201_5% 2 1 RC71 PCH_SPI0_IO2 RH183 2 1 10K_0201_5% USB2_ID F3
USB_ID
USB2P_4
USB2N_4
G7 USB20_4_N USB20_4_P
USB20_4_N
78
78
Right USB3.0(or Type-C)
ep
100K_0201_5% 2 1 RC72 PCH_SPI0_IO3 RH127 2 1 113_0402_1% USB2_COMP E2 L5 USB20_3_P
USB2_COMP USB2P_3
USB2N_3
L4 USB20_3_N USB20_3_P
USB20_3_N
56
56
Left TBT2
SPI0_MOSI(PCH_SPI_SI ): R31
RSVD_8 USB20_2_P
Rising edge of RSMRST# P31 L8
External pull-up is required. Recommend 4.7 kohm pull up.
RSVD_9 USB2P_2
USB2N_2
K7 USB20_2_N USB20_2_P
USB20_2_N
53
53
Back TBT1
This strap should sample HIGH. There should NOT be any onboard E16
USB31_6_TXP USB20_1_P
D16 K4
device driving it to opposite direction during strap sampling. J13
USB31_6_TXN USB2P_1
K3 USB20_1_N USB20_1_P 57
SPI0_IO2 and SPI0_IO3: H12
USB31_6_RXP
USB31_6_RXN
USB2N_1 USB20_1_N 57 Back USB3.0 MID
Rising edge of RSMRST# USB30_TX5_P
External pull-up is required. 58 USB30_TX5_P D15
USB30_TX5_N USB31_5_TXP
C15
Recommend 100K if pulled up to 3.3V or 75K if pulled up to 1.8V. Back USB3.0 Right
R
58 USB30_TX5_N USB30_RX5_P USB31_5_TXN

H15
This strap should sample HIGH. There should NOT be any onboard 58 USB30_RX5_P USB30_RX5_N G14
USB31_5_RXP
device driving it to opposite direction during strap sampling. 58 USB30_RX5_N USB31_5_RXN
20191213 TIGERLAKE-H-PCH_FCBGA943
@
Glitch Free Requirements:

Cap or pull-down resistor is required
100K for 3.3V Signaling Mode
75K for 1.8V Signaling Mode
PCH_SPI0_CLK RC854 1 2 100K_0201_5%
CC452 1 2 5P_50V_B_NPO_0402
A EMC_NS@ A
20191226

X60-TGL-H
5
Vinafix.com
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2
Size
C
Date:
Document Number
PCH (2/8) USB,SPI

1
Sheet 17 of 110
Rev
0.1
5 4 3 2 1
+3VS UH1C
+3VALW_PCH
3 OF 9
AU21 AY12 GPP_H15
1 GPP_S7/SNDW4_DATA/DMIC_DATA0 GPP_H23/TIME_SYNC0
AW21 BD10 JTAG ODT DISABLE
GPP_S6/SNDW4_CLK/DMIC_CLKA0 GPP_H22/ISH_I2C1_SCL
@ AY20 BE10
GPP_S5/SNDW3_DATA/DMIC_DATA1 GPP_H21/ISH_I2C1_SDA LOW: JTAG ODT DISABLED
1
RH924 BB20 BB6
10K_0201_5% GPP_S4/SNDW3_CLK/DMIC_CLKA1 GPP_H20/ISH_I2C0_SCL HIGH: JTAG ODT ENABLED RH811
HDA_SDO This signal has a weak internal pull-down. BC20
GPP_S3/SNDW2_DATA/DMIC_CLKB1 GPP_H19/ISH_I2C0_SDA
BD5
SPI_VCC_SEL
0 = Enable security measures defined in the Flash Descriptor. BD19 BE3 1/20W_4.7K_5%_0201
2
GPP_S2/SNDW2_CLK/DMIC_CLKB0 GPP_H18/SML4ALERT#
LCD_OD_N
LCD over drive control * 1 = Disable Flash Descriptor Security (override). This
strap should only be asserted high using external pull-
BE20
BD18
GPP_S1/SNDW1_DATA GPP_H17/SML4DATA
BD4
BE4
2
GPP_S0/SNDW1_CLK GPP_H16/SML4CLK GPP_H15 GPP_H15
OD: low for OD off( Default) BA11
up in manufacturing/debug environments ONLY. GPP_H15/SML3ALERT#
1
BOARD_ID5 AW47 AY8

High for OD on BOARD_ID4 AY45
GPP_R19/ISH_GP5 GPP_H14/SML3DATA
AW9
GPP_R18/ISH_GP4 GPP_H13/SML3CLK
1
RH923 BOARD_ID3 BA45 BG5 GPP_H12
10K_0201_5% +1.8VALW BOARD_ID2 GPP_R17/ISH_GP3 GPP_H12/SML2ALERT#
BA48 BF6 RH813
D
need confirm HDA LINK power level with CODEC BOARD_ID1 GPP_R16/ISH_GP2 GPP_H11/SML2DATA @ 1/20W_4.7K_5%_0201
D
BA47 BG6
2
BOARD_ID0 GPP_R15/ISH_GP1 GPP_H10/SML2CLK

BB47 BA3
GPP_R14/ISH_GP0 GPP_H9/SRCCLKREQ15#
BC49 BD8
2
GPP_R13/ISH_GP7 GPP_H8/SRCCLKREQ14#
2
BC48 BE8
GPP_R12/CLKOUT_48 GPP_H7/SRCCLKREQ13#
RH25 AV43 BD7
1K_0402_5% GPP_R11/SX_EXIT_HOLDOFF#/ISH_GP6 GPP_H6/SRCCLKREQ12#
AR39 BE7
GPP_R10/ISH_UART0_RTS#/GSPI2_CS1# GPP_H5/SRCCLKREQ11#
AU42 BC1
GPP_R9/PCIE_LNK_DOWN GPP_H4/SRCCLKREQ10# CARD_CLKREQ_N
BD46 BC2 CARD_CLKREQ_N 78
1
GPP_R8/I2S1_SCLK GPP_H3/SRCCLKREQ9# +3VS
BE47 BB3
+3VALW_PCH RH9 1 @ 2 0_0201_5% GPP_R7/I2S1_SFRM GPP_H2/SRCCLKREQ8# SSD_CLKREQ_N SSD PCIE from CPU
79 ME_FLASH AT38 AR11 SSD_CLKREQ_N 63
GPP_R6/I2S1_TXD GPP_H1/SRCCLKREQ7#
BG45 BA7
1 HDA_RST_N GPP_R5/HDA_SDI1/I2S1_RXD GPP_H0/SRCCLKREQ6#
@ PAD TH2976 BF44
RPH1 HDA_SDIN0 GPP_R4/HDA_RST# CARD_CLKREQ_N RH1129 2 1 10K_0201_5%
66 HDA_SDIN0 BG44 U41
5 4 USB_OC4_N RH806 1 2 33_0402_5% HDA_SDOUT GPP_R3/HDA_SDI0/I2S0_RXD/HDACPU_SDI GPP_F23
BE43 V39
6 3 USB_OC5_N 66 HDA_SDOUT_AUDIO HDA_SYNC GPP_R2/HDA_SDO/I2S0_TXD/HDACPU_SDO GPP_F22/VNN_CTRL SSD_CLKREQ_N
RH804 1 2 33_0402_5% BD43 T35 RH917 2 1 10K_0201_5%
7 2 USB_OC6_N 66 HDA_SYNC_AUDIO HDA_BIT_CLK GPP_R1/HDA_SYNC/I2S0_SFRM GPP_F21/EDP_BKLTCTL PCH_EDP_PWM 45,46
RH805 1 2 33_0402_5% BE42 T37
USB_OC7_N 66 HDA_BITCLK_AUDIO GPP_R0/HDA_BCLK/I2S0_SCLK/HDACPU_BCLK GPP_F20/EDP_BKLTEN PCH_EDP_ENBKL 45,46 PCH_EDP_PWM
8 1 V45 RH311 1 2 100K_0201_5%
GPP_F19/EDP_VDDEN PCH_EDP_ENVDD 45,46
AT15 W42
10K_1206_8P4R_5% GPP_K11 GPP_F18/M2_SKT2_CFG3 PCH_EDP_ENBKL RH312 1 2 100K_0201_5%
AR7 Y41
VCCIN_AUX_PCH_VID1 GPP_K10/DDSP_HPDC/DISP_MISCC GPP_F17/M2_SKT2_CFG2
84,96,99 VCCIN_AUX_PCH_VID1 AT4 Y39
VCCIN_AUX_PCH_VID0 GPP_K9/CORE_VID1 GPP_F16/M2_SKT2_CFG1 PCH_EDP_ENVDD RH313 1 2 100K_0201_5%
84,96,99 VCCIN_AUX_PCH_VID0 AN11 V37
RPH2 GPP_K8/CORE_VID0 GPP_F15/M2_SKT2_CFG0
AR8 V35
5 4 USB_OC0_N PCH_EDP_HPD GPP_K7/DDSP_HPDB/DISP_MISCB GPP_F14/PS_ON#
45 PCH_EDP_HPD AT2 R46
6 3 USB_OC3_N GPP_K6/DDSP_HPDA/DISP_MISCA GPP_F13/SATA_SDATAOUT0
AP9 T47
7 2 USB_OC2_N LCD_OD_N GPP_K5/ADR_COMPLETE GPP_F12/SATA_SDATAOUT1
47 LCD_OD_N AT13 T48
8 1 USB_OC1_N +1.8VALW GPP_K4/GSXCLK GPP_F11/SATA_SLOAD
AU5 T46
EC_SCI_K2_R GPP_K3/GSXSRESET# GPP_F10/SATA_SCLOCK
AP15 T45 PCH_PCIE_WAKE_N_WLAN 71
10K_1206_8P4R_5% follow CRB & PDG EMPTY GPP_K2/GSXDIN GPP_F9/SATA_DEVSLP7
AU4 U47
GPP_K1/GSXSLOAD GPP_F8/SATA_DEVSLP6
1
internal pull-up, no need external AU3 U46 SPI select strap
+3VALW_PCH need check CNVIo schme check list GPP_K0/GSXDOUT GPP_F7/SATA_DEVSLP5 +3VALW_PCH
RH831 RH832 V46 low: 3.3V
20K_0402_5% 20K_0402_5% GPP_F6/SATA_DEVSLP4
BA2 W47 high: 1.8V
@ @ GPP_J9 GPP_F5/SATA_DEVSLP3
BA1 W45
GPP_J8 GPP_F4/SATAXPCIE7/SATAGP7
1
RH1157 2 1 10K_0201_5% PCH_PMC_ALERT_PD_N BA5 W46
2
GPP_J7/CNV_MFUART2_TXD GPP_F3/SATAXPCIE6/SATAGP6 RH661
AU9 Y47
RH1155 1 2 100K_0201_5% VCCIN_AUX_PCH_VID1 GPP_J6/CNV_MFUART2_RXD GPP_F2/SATAXPCIE5/SATAGP5 @ 1/20W_4.7K_5%_0201
71 CNVI_RGI_RSP AW4 Y48
RH304 1 @ 2 0_0402_5% GPP_J4 AW3 GPP_J5/CNV_RGI_RSP/UART0_CTS# GPP_F1/SATAXPCIE4/SATAGP4
71 CNVI_RGI_DT Y46
RH1156 1 2 100K_0201_5% VCCIN_AUX_PCH_VID0 GPP_J4/CNV_RGI_DT/UART0_TXD GPP_F0/SATAXPCIE3/SATAGP3
71 CNVI_BRI_RSP AV4
2
RH302 1 @ 2 0_0402_5% GPP_J2 AV3 GPP_J3/CNV_BRI_RSP/UART0_RXD USB_OC3_N SPI_VCC_SEL
C
71 CNVI_BRI_DT K46 C
CPU_C10_GATE_H_N GPP_J2/CNV_BRI_DT/UART0_RTS# GPP_E12/USB_OC3# USB_OC2_N USB_OC3_N 57 back dual port USB
AV7 K47 USB_OC2_N 59 back USB charge port
GPP_J1/CPU_C10_GATE# GPP_E11/USB_OC2# USB_OC1_N
AU8 L45 USB_OC1_N 78 right side USB port IO board typeC
GPP_J0/CNV_PA_BLANKING GPP_E10/USB_OC1#
1
L46 USB_OC0_N
+3VS USB_OC7_N GPP_E9/USB_OC0# SATA_LED_N RH15 1 2 10K_0402_5% RH662
AM7 L47 +3VS
USB_OC6_N GPP_I14/USB_OC7#/I2C5_SCL GPP_E8/SATALED#/SPI1_CS1# @ 100K_0201_5%
AP13 M48
USB_OC5_N GPP_I13/USB_OC6#/I2C5_SDA GPP_E7/CPU_GP1
AK11 M46
TBT port2 54 USB_OC5_N GPP_I12/USB_OC5#/I2C4_SCL GPP_E6/SATA_DEVSLP2
1
USB_OC4_N RH927 1 @ 2 10K_0402_5%

51 USB_OC4_N AM13 M45 DEVSLP 63 +3VS
2
RH1160 TBT port1 GPP_I11/USB_OC4#/I2C4_SDA GPP_E5/SATA_DEVSLP1
AL9 N47
@ 10K_0201_5% GPP_I10 GPP_E4/SATA_DEVSLP0 PCH_SMI_N RH926 1 @ 2 0_0201_5%
63 CPU_SSD_RST_N AM8 N46 EC_SMI_N 79
GPP_I9 GPP_E3/CPU_GP0
AM15 P46
GPP_I8/DDPC_CTRLDATA GPP_E2/SATAXPCIE2/SATAGP2 SSD_DET_N
AJ6 P47
2
GPP_I7/DDPC_CTRLCLK GPP_E1/SATAXPCIE1/SATAGP1 SSD_DET_N 63

AJ8 R45
EC_SCI_N RH1159 1 @ 2 0_0201_5% EC_SCI_K2_R GPP_I6/DDPB_CTRLDATA GPP_E0/SATAXPCIE0/SATAGP0
20,79 EC_SCI_N AH9
RH1219 1 @ 2 0_0201_5% PCH_DPIN_HPD_R GPP_I5/DDPB_CTRLCLK
12 PCH_DPIN_HPD AK15
CNVI_EN_N GPP_I4/DDSP_HPD4/DISP_MISC4 +3VALW_PCH
AK13
71 CNVI_EN_N GPP_I3/DDSP_HPD3/DISP_MISC3
AH11
PCH_HDMI_HPD 1 2 0_0201_5% GPP_I1 GPP_I2/DDSP_HPD2/DISP_MISC2
50 PCH_HDMI_HPD RH26 @ AE8
GPP_I1/DDSP_HPD1/DISP_MISC1
1
+1.8VALW PCH_PMC_ALERT_PD_N AE6
20,51,54 PCH_PMC_ALERT_PD_N GPP_I0/PMCALERT# RH1209
@ 1/20W_4.7K_5%_0201
+3VALW_PCH TIGERLAKE-H-PCH_FCBGA943
1
CH100 @
2
0.1U_6.3V_K_X5R_0201
GPP_H12
2
2
UH8 RH1152 BOARD ID0 BOARD ID1 BOARD ID2 BOARD ID3 BOARD ID4 BOARD ID5
1 6 10K_0201_5% Function
NC1 Vcc GPP_R14 GPP_R15 GPP_R16 GPP_R17 GPP_R18 GPP_R19 This strap has a 20 kOhm ± 30% internal pull-down.
CPU_C10_GATE_H_N 2 5 0 >Master Attached Flash Sharing (MAFS) enabled (Default)
1
A NC2 1 >Slave Attached Flash Sharing (SAFS) enabled.

SKU Size GPU Type Notes: 1. The internal pull-down is disabled after RSMRST#
1
3 4 de-asserts.
GND Y CPU_C10_GATE_N 79,84
RH1207
1/20W_75K_5%_0201
74AUP1G07GS_SOT1202-6
HY568-15-GN20E-E3 0 0 1 0 0 1 2. This signal is in the primary well.
HY568-17-GN20E-E3 0 1 0 0 0 1
2
RH1218 2 @ 1 0_0201_5%
B B
+1.8VALW
HY568-15-GN20E- 0 0 1 0 1 0
E5 HY568P-GN20E- 0 1 1 0 0 1
E3
HY568P-GN20E-E5 0 1 1 0 1 0
1
1
10K_0201_5%
10K_0201_5%
10K_0201_5%
10K_0201_5%
10K_0201_5%
10K_0201_5%
RH1193
@
RH1195
@
RH1197
@
RH1199 RH1201
@
RH1203
@
Y760-GN20E-E3 1 0 0 0 0 1
Y760-GN20E-E5 1 0 0 0 1 0
2
2
BOARD_ID0
BOARD_ID1
BOARD_ID2
BOARD_ID3
BOARD_ID4
Y760-GN20E-E7 1 0 0 0 1 1
BOARD_ID5
HY568-15-GN20P-P0 0 0 1 1 0 0
HY568-17-GN20P-P0 0 1 0 1 0 0
1
1
10K_0201_5%
10K_0201_5%
10K_0201_5%
10K_0201_5%
10K_0201_5%
10K_0201_5%
HY568-15-GN20P-P1
RH1194 RH1196 RH1198 RH1200 RH1202 RH1204
@ @ @ @ @
0 0 1 1 0 1
2
2
HY568-17-GN20P-P1 0 1 0 1 0 1
HY568P-GN20P-P0 0 1 1 1 0 0
HY568P-GN20P-P1 0 1 1 1 0 1
A
HY568-15-N18P-G61 0 0 1 1 1 0 A
HY568-17-N18P-G61 0 1 0 1 1 0
HY568-15-GN20P0-D 0 0 1 1 1 1
X60-TGL-H
Custom
PCH (3/8) HDA 0.1
Vinafix.com
5 4 3 2 1
5 4 3 2 1
UH1A
PCH_C10_WAKE 1 OF 9
10 PCH_C10_WAKE AJ4 T2
C10_WAKE CLKOUT_PCIE_P15
T3
CLKOUT_PCIE_N15
10 PCH_CPU_BCLKP B8
CLKOUT_CPUBCLK_P
10 PCH_CPU_BCLKN A9 AA1
CLKOUT_CPUBCLK_N CLKOUT_PCIE_P14
Y2
D CLKOUT_PCIE_N14 D
C8
10 PCH_CPU_NSSC_CLKP CLKOUT_CPUNSSC_P
10 PCH_CPU_NSSC_CLKN D8 R4
CLKOUT_CPUNSSC_N CLKOUT_PCIE_P13
R5
CLKOUT_PCIE_N13
10 PCH_CPU_PCIBCLKP A6
CLKOUT_CPUPCIBCLK_P
10 PCH_CPU_PCIBCLKN A5 AB4
CLKOUT_CPUPCIBCLK_N CLKOUT_PCIE_P12
AB3
RH20 1 @ 2 0_0402_5% CLKOUT_CPURTC_R CLKOUT_PCIE_N12
10 CLKOUT_CPURTC AD1
CLKOUT_CPURTC
W4
PAD TH2978 @1 CLKOUT_CPUBCLK2_P CLKOUT_PCIE_P11
AC11 W5
PAD TH2979 @1 CLKOUT_CPUBCLK2_N CLKOUT_CPUBCLK2_P CLKOUT_PCIE_N11
AC12
CLKOUT_CPUBCLK2_N
T4
CNVI_WT_D1_P CLKOUT_PCIE_P10
71 CNVI_WT_D1_P AU16 T5
CNVI_WT_D1_N CNV_WT_D1P CLKOUT_PCIE_N10
71 CNVI_WT_D1_N AW15
CNV_WT_D1N CLK_PCIE_CARD_P
W8 CLK_PCIE_CARD_P 78
CNVI_WT_D0_P CLKOUT_PCIE_P9 CLK_PCIE_CARD_N
71 CNVI_WT_D0_P
CNVI_WT_D0_N
AY15
CNV_WT_D0P CLKOUT_PCIE_N9
W6 CLK_PCIE_CARD_N 78 CARD READER
71 CNVI_WT_D0_N BA14
CNV_WT_D0N
W3
CNVI_WT_CLK_P CLKOUT_PCIE_P8
71 CNVI_WT_CLK_P AU14 V4
CNVI_WT_CLK_N CNV_WT_CLKP CLKOUT_PCIE_N8
71 CNVI_WT_CLK_N AW13
CNV_WT_CLKN CLK_PCIE_SSD1_P
T8 CLK_PCIE_SSD1_P 63
CNVI_WR_D1_P CLKOUT_PCIE_P7 CLK_PCIE_SSD1_N
71 CNVI_WR_D1_P CNVI_WR_D1_N
BE11
CNV_WR_D1P CLKOUT_PCIE_N7
T7 CLK_PCIE_SSD1_N 63 M.2 SSD2
71 CNVI_WR_D1_N BD11
CNV_WR_D1N
U4
CNVI_WR_D0_P CLKOUT_PCIE_P6
71 CNVI_WR_D0_P BD13 U3
CNVI_WR_D0_N CNV_WR_D0P CLKOUT_PCIE_N6
71 CNVI_WR_D0_N BC13
CNV_WR_D0N CLK_PCIE_SSD0_P
Y4 CLK_PCIE_SSD0_P 63
CNVI_WR_CLK_P CLKOUT_PCIE_P5 CLK_PCIE_SSD0_N
71 CNVI_WR_CLK_P CNVI_WR_CLK_N
BD12
CNV_WR_CLKP CLKOUT_PCIE_N5
Y3 CLK_PCIE_SSD0_N 63 M.2 SSD1
71 CNVI_WR_CLK_N BC12
CNV_WR_CLKN
V13
RH50 2 CNVI@ 1 150_0402_1% CNV_WT_RCOMP BE12 CLKOUT_PCIE_P4
V15
CNV_WT_RCOMP CLKOUT_PCIE_N4
BE14 U9 CLK_PCIE_LAN_P
RSVD_18 CLKOUT_PCIE_P3 CLK_PCIE_LAN_N CLK_PCIE_LAN_P 73
CLKOUT_PCIE_N3
V11 CLK_PCIE_LAN_N 73 LAN
24 CPU_TRST_N AE4
CPU_TRST# CLK_PCIE_WLAN_P
AG15 CLK_PCIE_WLAN_P 71
CLKOUT_PCIE_P2 CLK_PCIE_WLAN_N
10 CPU_PWRGOOD AC3
PROCPWRGD CLKOUT_PCIE_N2
AG13 CLK_PCIE_WLAN_N 71 WLAN
C AE11 C
CLKOUT_PCIE_P1
AE9
CLKOUT_PCIE_N1
Y9 CLK_PCIE_GPU_P CLK_PCIE_GPU_P 28
CLKOUT_PCIE_P0
Y11 CLK_PCIE_GPU_N CLK_PCIE_GPU_N 28 GPU
CLKOUT_PCIE_N0
TIGERLAKE-H-PCH_FCBGA943
@
B B
A A

X60-TGL-H
Vinafix.com
C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. PCH (4/8) CLOCK,CNVI
5 4 3 2 1
5 4 3 2 1
UH1D
+3VS
4 OF 9
AU29 AW46 +1.8VALW +1.8VALW
WLAN side pull up GPP_D23/UART3_CTS#/THC1_SPI2_INT# GPP_A14/IMGCLKOUT0
AY30 AV46
RH90 1 @ 2 10K_0201_5% WLAN_CLKREQ_N +3VALW_PCH GPP_D22/UART3_RTS#/THC1_SPI2_RST# GPP_A13/ESPI_ALERT3#
AW29 AV47
GPP_D21/UART3_TXD/THC1_SPI2_IO3 GPP_A12/ESPI_ALERT2#
BD30 AU45
GPP_D20/UART3_RXD/THC1_SPI2_IO2 GPP_A11/ESPI_ALERT1#
2
RH89 1 2 10K_0201_5% LAN_CLKREQ_N BD35 AU46 ESPI_ALERT0_N
GPP_D19/GSPI3_MOSI/THC1_SPI2_IO1 GPP_A10/ESPI_ALERT0# ESPI_ALERT0_N 79
1
BD34 AU47 RH1174 RH1173
GPP_D18/GSPI3_MISO/THC1_SPI2_IO0 GPP_A9/ESPI_CS3# @ @
RPH15 BC34 AT48 10K_0201_5% 10K_0201_5%
1 4 SSD_CLKREQ0_N @ RH300 GPP_D17/GSPI3_CLK/THC1_SPI2_CLK GPP_A8/ESPI_CS2#
BE35 AT46 ESPI_CS0_N Internal PU 20K
2 3 GPU_CLKREQ_N GPP_D16/GSPI3_CS0#/THC1_SPI2_CS# GPP_A7/ESPI_CS1# ESPI_RST_N
4.7K_0402_5% SML1DATA BB30 AT45
1
GPP_D15/SML1DATA GPP_A6/ESPI_RESET# ESPI_CLK_R ESPI_RST_N 79 ESPI_CS0_N ESPI_ALERT0_N
PD BC30 AR47 RH84 1 2 33_0402_5%
ESPI_CLK 79
2
10K_0404_4P2R_5% EDP_SW GPP_D14/THC0_SPI1_IO3 GPP_A5/ESPI_CLK ESPI_CS0_N
BE30 AR46 ESPI_CS0_N 79
GPP_D13/THC0_SPI1_IO2 GPP_A4/ESPI_CS0#
1
ESPI_IO3_R RH128 1 2 33_0402_5% ESPI_RST_N
BD31 AP46 ESPI_IO3 79 1
RH852 1 @ 2 10K_0201_5% GPU_CLKREQ_N GPP_D12/ISH_UART0_CTS# GPP_A3/ESPI_IO3/SUSACK# ESPI_IO2_R RH130 1 2 33_0402_5% EMC_NS@ RH1175
BD32 AP47
GPP_D11 GPP_A2/ESPI_IO2/SUSWARN#/SUSPWRDNACK ESPI_IO2 79
1
PCH_SML0_DATABC33 AN45 ESPI_IO1_R RH131 1 2 33_0402_5% CH265 @
D 52,55 PCH_SML0_DATA GPP_D10/SML0DATA GPP_A1/ESPI_IO1 ESPI_IO1 79 1/20W_75K_5%_0201 D
reserved GPU_CLKREQ# PD RH301 TBTB PCH_SML0_CLK BE32 AN46 ESPI_IO0_R RH132 1 2 33_0402_5% 10P_0402_50V8J RH1177
follow Y540 4.7K_0402_5% 52,55 PCH_SML0_CLK GPP_D9/SML0CLK GPP_A0/ESPI_IO0 ESPI_IO0 79 2
BD36 1/20W_75K_5%_0201
2
GPP_D8/I2S2_SCLK/THC0_SPI1_INT# GPP_G15
BE36 AL21
CNVI_MODEM_CLKREQ GPP_D7/I2S2_RXD/THC0_SPI1_RST# GPP_G15/DDP2_CTRLDATA/TBT_LSX1_RXD
AY33 AN21
2
+1.8VALW 71 CNVI_MODEM_CLKREQ CNVI_RF_RESET_N GPP_D6/I2S2_TXD/MODEM_CLKREQ GPP_G14/DDP2_CTRLCLK/TBT_LSX1_TXD TBT0_LSX0_RXD
BA33 AU19
71 CNVI_RF_RESET_N GPP_D5/I2S2_SFRM/CNV_RF_RESET# GPP_G13/DDP1_CTRLDATA/TBT_LSX0_RXD TBT0_LSX0_TXD TBT0_LSX0_RXD 52
RPH10 V0.4 SML1CLK BF33 AW18
PCH_SML0_CLK GPP_D4/SML1CLK GPP_G12/DDP1_CTRLCLK/TBT_LSX0_TXD GPP_G11 TBT0_LSX0_TXD 52
1 4 BD33 AY17
2 3 PCH_SML0_DATA GPP_D3/THC0_SPI1_IO0/SBK3/BK3 GPP_G11/ISH_SPI_MOSI/DDP4_CTRLDATA/GSPI2_MOSI/TBT_LSX3_RXD
BE33 BA17
GPP_D2/THC0_SPI1_IO1/SBK2/BK2 GPP_G10/ISH_SPI_MISO/DDP4_CTRLCLK/GSPI2_MISO/TBT_LSX3_TXD TBT2_LSX1_RXD
AW32 BC17
GPP_D1/THC0_SPI1_CLK/SBK1/BK1 GPP_G9/ISH_SPI_CLK/DDP3_CTRLDATA/GSPI2_CLK/TBT_LSX2_RXD TBT2_LSX1_TXD TBT2_LSX1_RXD 55 +3VALW_PCH +3VALW_PCH +3VALW_PCH +3VALW_PCH
2.2K_0404_4P2R_5% AU31 BE18
GPP_D0/THC0_SPI1_CS#/SBK0/BK0 GPP_G8/ISH_SPI_CS#/DDP3_CTRLCLK/GSPI2_CS0#/TBT_LSX2_TXD TBT2_LSX1_TXD 55
+3VS EDP_SW
45,46 EDP_SW BB26 BF17
RPH14 GPP_C23/UART2_CTS# GPP_G7
AU26 BD17
GPP_C22/UART2_RTS# GPP_G6
1
1 4 PCH_I2C1_SCL PCH_UART2_TXD AW26 BE17 1.8V GPIO
PCH_I2C1_SDA 71 PCH_UART2_TXD PCH_UART2_RXD GPP_C21/UART2_TXD GPP_G5/SLP_DRAM# PXS_RST_R_N
2 3 AY26 BD16 RH315 1 @ 2 0_0201_5% PXS_RST_N 1.8V GPIO RH1136 RH1138 RH1140 RH1141
71 PCH_UART2_RXD PCH_I2C1_SCL RH1205 1 GPP_C20/UART2_RXD GPP_G4 PXS_RST_N 31
@ 2 0_0201_5% PCH_I2C1_SCL_R BD20 BC16 PCH_GPU_EVENT_N
PCH_GPU_EVENT_N 31 @ 1/20W_4.7K_5%_0201 @ 1/20W_4.7K_5%_0201 @ 1/20W_4.7K_5%_0201 @ 1/20W_4.7K_5%_0201
45,83,93 PCH_I2C1_SCL PCH_I2C1_SDA RH1206 1 GPP_C19/I2C1_SCL GPP_G3
2.2K_0404_4P2R_5% Touchpad /OC /eDP MUX @ 2 0_0201_5% PCH_I2C1_SDA_R BE21 BE15
45,83,93 PCH_I2C1_SDA NUM_LED GPP_C18/I2C1_SDA GPP_G2/DNX_FORCE_RELOAD
RH1184 1 @ 2 0_0201_5% NUM_LED_CPH BD21 BD15
79,81 NUM_LED
2
Follow CRB 71.5K PCH_FNLK RH1183 1 @ 2 0_0201_5% PCH_FNLK_R GPP_C17/I2C0_SCL GPP_G1/DDPA_CTRLDATA PXS_PWREN_PCH RH314 1 @ 2 0_0201_5% PXS_PWREN
BC22 BD14
81 PCH_FNLK CAPS_LED GPP_C16/I2C0_SDA GPP_G0/DDPA_CTRLCLK PXS_PWREN 31,34
PDG 75k RH1185 1 @ 2 0_0201_5% CAPS_LED_PCH BE23 GPP_G15 GPP_G11 TBT0_LSX0_RXD TBT2_LSX1_RXD
CNVI@ CNVI_RF_RESET_N 79,81 CAPS_LED GPP_C15/UART1_CTS#/ISH_UART1_CTS# GPPC_RCOMP
RH829 1 2 1/16W_71.5K_1%_0402 BD24 BG13 RH21 1 2 200_0402_1%
RH830 1 @ 2 1/16W_71.5K_1%_0402 CNVI_MODEM_CLKREQ GPP_C14/UART1_RTS#/ISH_UART1_RTS# GPP_RCOMP
28,31 VGA_PWRGD BD23
GPP_C13/UART1_TXD/ISH_UART1_TXD
1
VGA_ALERT_PCH_N PCIE_RCOMP
BC28 B13
PCH_TP_INT_N GPP_C12/UART1_RXD/ISH_UART1_RXD PCIE_RCOMPP PCIE_RCOMN RH741 2 1 100_0402_1% RH1137 RH1139 RH1142 RH1143
BD29 A13
83 PCH_TP_INT_N GPP_C11/UART0_CTS# PCIE_RCOMPN
BF29 @ 1/20W_20K_5%_0201 @ 1/20W_20K_5%_0201 @ 1/20W_20K_5%_0201 @ 1/20W_20K_5%_0201
EC_SCI_N GPP_C10/UART0_RTS#
+3VALW_PCH
18,79 EC_SCI_N RH780 1 @ 2 0_0201_5% EC_SCI_C9_N BE29 AR3
GPP_C9/UART0_TXD CL_RST#
71 PCH_BT_OFF_N BE27
2
RH1163 1 2 100K_0201_5% SLP_S0_N GPP_C8/UART0_RXD
BB24 AR4
GPP_C7/ISH_I2C2_SCL/I2C3_SCL CL_DATA
AY24 AP4
SML0_ALERT_N BD27 GPP_C6/ISH_I2C2_SDA/I2C3_SDA/SBK4/BK4 CL_CLK
GPP_C5/SML0ALERT#
BE25 AM2
+3VALW_PCH GPP_C4/ISH_UART0_TXD/I2C2_SCL PCH_JTAGX JTAGX 24
Smart AMP BE24 AM4 GPP_G9/ISH_SPI_CLK/DDP3_CTRLDATA/GSPI2_CLK/TBT_LSX2_RXD
SMB_ALERT_N GPP_C3/ISH_UART0_RXD/I2C2_SDA PCH_JTAG_TMS PCH_TMS 24
BD26
GPP_C2/SMBALERT# PCH_JTAG_TDO
AM3 PCH_TDO 24 This strap has a 20Kohm ±30% internal pull-down
RH765 1 2 2.2K_0402_5% SMB_ALERT_N RH768 1 @ 2 2.2K_0402_5% PCH_SMBDATA BD25 AN4 0 = DDP3_I2C/TBT_LSX2_BBSB_LS2 pins at 1.8V
GPP_C1/SMBDATA PCH_JTAG_TDI PCH_TDI 24
RH766 1 @ 2 2.2K_0402_5% SML0_ALERT_N RH769 1 @ 2 2.2K_0402_5% PCH_SMBCLK BE26 AM5
1 2 2.2K_0402_5% SML1_ALERT_N RH770 1 2 2.2K_0402_5% GPP_C0/SMBCLK PCH_JTAG_TCK PCH_TCK 24 1 = DDP3_I2C/TBT_LSX2_BBSB_LS2 pins at 3.3V
RH767 @ @ Strap PIN
RH1186 1 @ 2 0_0201_5% SML1_ALERT_N DBG_PMODE notes: 1. the internal pull-down is disabled after RSMRST# de-asserts
18,51,54 PCH_PMC_ALERT_PD_N BD42 AG5 DBG_PMODE 24
C Strap GPP_B22
AW41
GPP_B23/SML1ALERT#/PCHHOT# DBG_PMODE 2. this signal is in the primary well C
PCH_WLAN_OFF_N GPP_B22/GSPI1_MOSI
BE46 AE47 RTC_INTRUDER_N
71 PCH_WLAN_OFF_N PWM_OUT_EN_RR GPP_B21/GSPI1_MISO INTRUDER# GPP_G11/ISH_SPI_MOSI/DDP4_CTRLDATA/GSPI2_MOSI/TBT_LSX3_RXD
RH928 2 @ 1 0_0201_5% BB42
46,79 PWM_OUT_EN GPP_B20/GSPI1_CLK
BD45 AJ5 PROC_AUDIO_SDO_PCH RH754 1 2 30_0402_1% PROC_AUDIO_SDO_CPU 12 This strap has a 20Kohm ±30% internal pull-down
31 PCH_FB_GC6_EN GPP_B18_NO_REBOOT GPP_B19/GSPI1_CS0# HDACPU_SDO
GPP_C2 /SMBALERT# 24 GPP_B18_NO_REBOOT AU36
GPP_B18/GSPI0_MOSI HDACPU_SDI
AK4 PROC_AUDIO_SDI_CPU 12 0 = DDP4_I2C/TBT_LSX3/BBSB_LS3 pins at 1.8V
PROC_AUDIO_CLK_PCH RH755 1 2 30_0402_1%
This signal has a weak internal pull-down. 73 LAN_PWR_ON_N BA36
GPP_B17/GSPI0_MISO HDACPU_BCLK
AJ3 PROC_AUDIO_CLK_CPU 12 1 = DDP4_I2C/TBT_LSX3/BBSB_LS3 pins at 3.3V
0 = Disable Intel ME Crypto Transport Layer Security AY38 notes: 1. the internal pull-down is disabled after RSMRST# de-asserts
GPP_B16/GSPI0_CLK
79 TOP_SWAP_EN RH1165 2 @ 1 0_0201_5% BA39
(TLS) cipher suite (no confidentiality). (Default) GPP_B15/GSPI0_CS0# +VCC1P05_OUT_FET 2. this signal is in the primary well
* 1 = Enable Intel ME Crypto Transport Layer Security
(TLS) cipher suite (with confidentiality). Must be 31,52,55,63,71,73,78,79 PLT_RST_N
66 PCH_BEEP PLT_RST_N
SLP_S0_N
BD40
BD39
GPP_B14/SPKR
GPP_B13/PLTRST# GPP_G13/DDP1_CTRLDATA/TBT_LSX0_RXD
RH1162 1 @ 2 0_0201_5% BE40
pulled up to support Intel AMT with TLS. 79 PM_SLP_S0_N GPP_B12/SLP_S0# This strap has a 20Kohm ±30% internal pull-down
1
1
1 BE39
SSD_CLKREQ0_N GPP_B11/I2S_MCLK 0 = DDP1_I2C/TBT_LSX0/BSSB_LS0 pins at 1.8V
63 SSD_CLKREQ0_N
BD38
GPP_B10/SRCCLKREQ5#
RH663 DBG_PMODE
GPP_C5 /SML0ALERT# CH61 RH43 BE38 @ 1K_0201_5% This strap has a 20kohm±30% internal pull-up 1 = DDP1_I2C/TBT_LSX0/BSSB_LS0 pins at 3.3V
LAN_CLKREQ_N GPP_B9/SRCCLKREQ4#
This signal has a weak internal pull-down. 220P_0201_25V7-K 100K_0201_5% 73 LAN_CLKREQ_N BF37
GPP_B8/SRCCLKREQ3# This strap should sample high. notes: 1. the internal pull-down is disabled after RSMRST# de-asserts
EMC_NS@ 2 WLAN_CLKREQ_N
0 = eSPI Enable (for EC). (Default) 71 WLAN_CLKREQ_N BD37 There should not be any on-board device driving it to 2. this signal is in the primary well
2
2
GPP_B7/SRCCLKREQ2# DBG_PMODE
1 = eSPI Disable (for EC). BC38
GPU_CLKREQ_N BC37
GPP_B6/SRCCLKREQ1# opposite direction during strap sampling.
28 GPU_CLKREQ_N GPP_B5/SRCCLKREQ0# Notes: 1. The internal pull-up is disabled after RSMRST# de-asserts. GPP_G15/DDP2_CTRLDATA/TBT_LSX1_RXD
1
RH1180 1 @ 2 0_0201_5% TBTA_FORCE_PWR_CPU AU34
GPP_B23 /SML1ALERT# /PCHHOT# 51,52 TBTA_FORCE_PWR
RH1181 1 @ 2 0_0201_5% TBTB_FORCE_PWR_CPU GPP_B4/CPU_GP3 RH664 2. This signal is in the primary well. This strap has a 20Kohm ±30% internal pull-down
54,55 TBTB_FORCE_PWR AW35
This strap has a 20 kOhm ± 30% internal pull-down. AY35
GPP_B3/CPU_GP2 @ 1K_0201_5% 0 = DDP2_I2C/TBT_LSX1/BSSB_LS1 pins at 1.8V
0 = 38.4 MHz clock (direct from crystal) (default) 51,54 GPPC_B2_VRALERT_N GPP_B2/VRALERT# 1 = DDP2_I2C/TBT_LSX1/BSSB_LS1 pins at 3.3V
AY42
1 = 19.2 MHz clock (derived from 38.4 MHz crystal) GPP_B1/GSPI1_CS1#/TIME_SYNC1 notes: 1. the internal pull-down is disabled after RSMRST# de-asserts
AW37
2
GPP_B0/GSPI0_CS1#/IMGCLKOUT1
Notes: 1. The internal pull-down is disabled after RSMRST# 2. this signal is in the primary well
de-asserts.
2. When used as PCHHOT# and strap low, a 150K TIGERLAKE-H-PCH_FCBGA943
+3VALW_PCH +VCCPRTC_3P3
pull-up is needed to ensure it does not override @
+3VS
the internal pull-down strap sampling.
+1.8VS_VGA
3. This signal is in the primary well.
2
2
1
RC203
+3VALW_PCH RH1161 RH665
100K_0201_5%
@ 10K_0201_5% RB521CM-30T2R_VMN2M-2 1/20W_1M_5%_0201
2
PCH_BEEP
G
RH1117 1 @ 2 1K_0402_5% @
1
1
2
3 1 VGA_ALERT_PCH_N DC4 2 1 GPPC_B2_VRALERT_N
31 VGA_ALERT_N 10,79,95 H_PROCHOT_N RTC_INTRUDER_N
SPKR / GPP_B14
S
The signal has a weak internal pull-down. 2 1

B B
1U_6.3V_M_X5R_0201
0 = Disable ¨Top Swap〃 mode. (Default) QH23 1
1
CH300
LBSS139WT1G_SC70-3 RC204 1 @ 2 0_0402_5% follow Y550 pull high, PDG/EDS Pull Up
1 = Enable ¨Top Swap〃 mode. This inverts an address CRB SPI select strap
@ RH743
on access to SPI and firmware hub, so the processor
Need confirm GPIO pull level @ 1/20W_1M_5%_0201
believes it fetches the alternate boot block instead of +3V_PD +3VALW 2
0603
the original boot-block. PCH will invert A16 (default)
2
for cycles going to the upper two 64-KB blocks in the
FWH or the appropriate address lines (A16, A17, or
A18) as selected in Top Swap Block size soft strap DIMM1, DIMM2 +3V_PD
RH1220 1 @ 2 0_0402_5%
(handled through FITC). +3VS PD
RPH4 RPH7 RPH8 RPH11
2
+3VALW_PCH 1 4 2N7002KDWH 1 4 1 4 +1.8VALW +3V_PD 1 4

G
+3VALW_PCH Vth= min 1V, max 2.5V +3VS +1.8VALW DH15

2 3 2 3 2 3 2 3 VCC3_LDO_PDA
GPP_B22 ESD 2KV UH3
RH750 1 @ 2 4.7K_0402_5%
2.2K_0404_4P2R_5% 2.2K_0404_4P2R_5% 2.2K_0404_4P2R_5% 1 8 2.2K_0404_4P2R_5% 1 2 GPU, EC, Thermal Sensor,
PCH_SMBCLK 6 1 SMB_CLK_S3 VCCA VCCB
GPP_B22 PCH temp. remove to ESPI read by EC
S
SMB_CLK_S3 25,26 PD_I2C2_SCL

2 7
D
HIGH: LPC SELECTED FOR SYSTEM FLASH SML1CLK 1 2

A0 B0 PD_I2C2_SCL 51,54 0709
5
LOW: SPI SELECTED. (DEFAULT) QH1A L2N7002KDW1T1G_SOT363-6

G
3 6 PD_I2C2_SDA RB521CM-30T2R_VMN2M-2
SML1DATA
BOOT BIOS STRAP (BBS) A1 B1 PD_I2C2_SDA 51,54 @
WEAK INTERNAL PD 4 5 RH1133 1 2 10K_0201_5%
PCH_SMBDATA SMB_DATA_S3 GND OE +3V_PD DH16
3 4 VCC3_LDO_PDB
S
SMB_DATA_S3 25,26
D
QH1B L2N7002KDW1T1G_SOT363-6
FXMA2102UMX_U-MLP8_1P2X1P4
1 2
SML1CLK RH1170 1 @ 2 0_0201_5% PD_I2C2_SCL 1 2

SMBUS/SMLINK需需需需需需 PD_I2C2_SDA RB521CM-30T2R_VMN2M-2
SML1DATA RH1171 1 @ 2 0_0201_5%
GPPD电电1.8V @
SMLINK0是是Burinside bridge re-timer
SMLINK1是是PD
GPU EC thermal等DEVICE换换换SMBUS
A A
Vinafix.com
X60-TGL-H
Custom
PCH (5/8) SMBUS,GPPABCDG 0.1

5 4 3 2 1
5 4 3 2 1
+3VALW_SYS
UH1B
PM_PWRBTN_R_N 2 OF 9 DMI_CRX_PTX7_P
RH17 1 2 10K_0201_5% AL47 C25
PCH_AC_PRESENT_R GPD12 DMI7_TXP DMI_CRX_PTX7_N DMI_CRX_PTX7_P 7
RH58 1 2 100K_0201_5% AK46 A25
BATLOW_N PM_SLP_S5_N GPD11/LANPHYPC DMI7_TXN DMI_CTX_PRX7_P DMI_CRX_PTX7_N 7
RH60 1 2 10K_0201_5% TH2981 PAD @ 1 AJ47 J24
GPD10/SLP_S5# DMI7_RXP DMI_CTX_PRX7_N DMI_CTX_PRX7_P 7
71 PM_SLP_WLAN_N AJ46 L24 DMI_CTX_PRX7_N 7
RH747 1 2 10K_0201_5% PCH_LAN_WAKE_N SUSCLK GPD9/SLP_WLAN# DMI7_RXN
63,71 SUSCLK AJ45
RH1182 2 @ 10_0201_5% GPD7 GPD8/SUSCLK DMI_CRX_PTX6_P
52,55 BB_TBT_PERST_N AL46 D26 DMI_CRX_PTX6_P 7
RH61 1 2 100K_0201_5% PCH_DPWROK @ 1 PAD SLP_A_N GPD7 DMI6_TXP DMI_CRX_PTX6_N
TH2982 AF46 C26 DMI_CRX_PTX6_N 7
follow CRB change to pull up RH71 1 @ 2 0_0201_5% PM_SLP_S4_R_N GPD6/SLP_A# DMI6_TXN DMI_CTX_PRX6_P
51,54,79,84 PM_SLP_S4_N AE46 R22 DMI_CTX_PRX6_P 7
D
RH70 1 @ 2 0_0201_5% PM_SLP_S3_R_N GPD5/SLP_S4# DMI6_RXP DMI_CTX_PRX6_N D
79,84 PM_SLP_S3_N AF47 P22 DMI_CTX_PRX6_N 7
RH75 1 @ 2 0_0201_5% PM_PWRBTN_R_N GPD4/SLP_S3# DMI6_RXN
24,79 PBTN_OUT_N AH47
PCH_LAN_WAKE_N GPD3/PWRBTN# DMI_CRX_PTX5_P
AH48 D27 DMI_CRX_PTX5_P 7
follow PDG pull down RH76 1 @ 2 0_0201_5% PCH_AC_PRESENT_R GPD2/LAN_WAKE# DMI5_TXP DMI_CRX_PTX5_N
79 AC_PRESENT AH46 C27 DMI_CRX_PTX5_N 7
08/05 BATLOW_N GPD1/ACPRESENT DMI5_TXN DMI_CTX_PRX5_P
AG45 P26 DMI_CTX_PRX5_P 7
RH1151 1 2 100K_0201_5% PM_SLP_S4_R_N GPD0/BATLOW# DMI5_RXP DMI_CTX_PRX5_N
R26 DMI_CTX_PRX5_N 7
DMI5_RXN
Y33
RH1150 1 2 100K_0201_5% PM_SLP_S3_R_N VSS_317 DMI_CRX_PTX4_P
E28 DMI_CRX_PTX4_P 7
DMI4_TXP DMI_CRX_PTX4_N
Y35 D29 DMI_CRX_PTX4_N 7
RH1208 1 @ 2 100K_0201_5% PM_SLP_WLAN_N TP_1 DMI4_TXN DMI_CTX_PRX4_P
F26 DMI_CTX_PRX4_P 7
DMI4_RXP DMI_CTX_PRX4_N
V32 H26 DMI_CTX_PRX4_N 7
RH921 1 @ 2 10K_0201_5% PCH_AC_PRESENT_R TP_2 DMI4_RXN
AJ42 C29 DMI_CRX_PTX3_P
RSVD_12 DMI3_TXP DMI_CRX_PTX3_N DMI_CRX_PTX3_P 7
AB20 B29 DMI_CRX_PTX3_N 7
RSVD_TP_1 DMI3_TXN DMI_CTX_PRX3_P
L26 DMI_CTX_PRX3_P 7
CH306 1 2 0.1u_0201_10V6K PM_PWRBTN_R_N DMI3_RXP DMI_CTX_PRX3_N
AJ44 J26 DMI_CTX_PRX3_N 7
RSVD_13 DMI3_RXN
AJ22
EMC_NS@ RSVD_TP_2 DMI_CRX_PTX2_P
E30 DMI_CRX_PTX2_P 7
DMI2_TXP DMI_CRX_PTX2_N
AK39 D30 DMI_CRX_PTX2_N 7
RSVD_14 DMI2_TXN DMI_CTX_PRX2_P
J29 DMI_CTX_PRX2_P 7
DMI2_RXP DMI_CTX_PRX2_N
AL41 L29 DMI_CTX_PRX2_N 7
RSVD_15 DMI2_RXN
+1.2V TH2983 PAD @ 1 PCH_IST_TP1_TP AH37 D31 DMI_CRX_PTX1_P
PCH_IST_TP0_TP PCH_IST_TP1 DMI1_TXP DMI_CRX_PTX1_N DMI_CRX_PTX1_P 7
TH2984 PAD @ 1 AK37 C30
PCH_IST_TP0 DMI1_TXN DMI_CTX_PRX1_P DMI_CRX_PTX1_N 7
F30 DMI_CTX_PRX1_P 7
DMI1_RXP
1
AH17 H30 DMI_CTX_PRX1_N
+3VALW_PCH RSVD_16 DMI1_RXN DMI_CTX_PRX1_N 7
RH1128 AH18
470_0402_5% RSVD_17 DMI_CRX_PTX0_P
D32 DMI_CRX_PTX0_P 7
PCH_DPWROK_R DMI0_TXP DMI_CRX_PTX0_N
AB46 C32 DMI_CRX_PTX0_N 7
DSW_PWROK DMI0_TXN
2
J32 DMI_CTX_PRX0_P
DMI_CTX_PRX0_P 7
2
RH814 RH1212 1 @ 2 0_0201_5% PCH_DRAMRST_R_N DMI0_RXP DMI_CTX_PRX0_N
25,26 PCH_DRAMRST_N AC46 L31 DMI_CTX_PRX0_N 7
@ 100K_0201_5% DRAM_RESET# DMI0_RXN
1
GPD7 @
C C
2
@ RH837
10K_0201_5%
1
This strap has a 20Kohm±30% internal pull-down

This strap should sample LOW. There should DSWROK can be tied to RSMRST# for platforms
not be any on-board device driving it to opposite direction that dose not support the Deep Sx state.
during strap sampling. 2 10_0201_5% PCH_DPWROK_R
NOTES: 1. The internal pull-down is disabled after RH1172 @
16,24,79 EC_RSMRST_N
DSW_PWROK is high.
2. This signal is in the DSW well.
PCH_DPWROK_R RH1153 1 @ 2 0_0201_5% PCH_DPWROK

PCH_DPWROK 16,79
1
1
RH1154
1/20W_1M_5%_0201 CH305
@ 0.1u_0201_10V6K
2
2
delay +3.3V_PCH over 10ms
B B
A A

X60-TGL-H
Vinafix.com
C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. PCH (6/8) DMI,PM
5 4 3 2 1
5 4 3 2 1
+1.8VALW +VCCPRIM_1P8
+3VALW_SYS +3VALW_PCH Need stuff
+VCCPRIM_3P3 @
+VCCLDOSTD_OUT_0P85
1.3A
JH2 1 2 JUMP_43X79
1 1 2
10U 6.3V M X5R 0402

UH1G
1
RH759 RH760 0.2A
1M_0402_5%
7 OF 9 1
@ @ VCCST_OVERRIDE out VCCIN_AUX_PCH
AD4 BF4 GPIO Group Power Supply
RH37
0_0805_5% 0_0805_5% 10,84 VCCST_OVERRIDE VCCST_OVERRIDE VCCLDOSTD_0P85_1
+VCCPGPPBC
CH12
BG3 @ @
VCCLDOSTD_0P85_2 9.646A
V18 BG4
2
2
VCCPRIM_3P3_1 VCCLDOSTD_0P85_3 2
GPP_A Pre-PAD 3.3V or 1.8V
2
D +3VALW_PCH_R RH222 1 @ 2 0_0402_5% +VCCPRTC_3P3 BF46 AA38 D
VCCRTC_1 VCCIN_AUX_1
BG46 AC38
+VCCPGPPEF +VCCPRIM_1P05_OUT VCCRTC_2 VCCIN_AUX_2
BG47
VCCRTC_3 VCCIN_AUX_3
AC39 GPP_B/C 3.3V
AC41
From AK21 In VCCIN_AUX_4 +3VALW_PCH +VCCPRIM_3P3
AK22 AC42
RH223 1 @ 2 0_0402_5% VCCPRIM1P05_OUT_PCH_1 VCCIN_AUX_5 Need stuff
+VCCPRIM_1P8 In VCCIN_AUX_6
AC44
@
GPP_E/F 3.3V
AJ20 AD38 0.202A
+VCCPGPPHK VCCPRIM1P05_OUT_PCH_2 VCCIN_AUX_7 JH4 1 2 JUMP_43X39
AD39
VCCIN_AUX_8 1 2
10U 6.3V M X5R 0402

1.55A AA27
VCCPRIM_1P8_1 VCCIN_AUX_9
AD41 GPP_H/K 3.3V
0.01U_0402_25V7K
AB22 AD42
1M_0402_5%
VCCPRIM_1P8_2 VCCIN_AUX_10 1 1
CH21
RH224 1 @ 2 0_0402_5% AB23 AD44
RH46
CH22
AB25 AE38 @ @ @ GPP_I 3.3V
+VCCPGPPI VCCPRIM_1P8_4 VCCIN_AUX_12
AB27 AE39
VCCPRIM_1P8_5 VCCIN_AUX_13 2 2
AD20 AE41
2
RH225 1 @ 2 0_0402_5%
AD22
AE42 GPP_D 1.8V
AD23 AE44
AD25 AG38
+3VALW_SYS +VCCPDSW_3P3 VCCPRIM_1P8_9 VCCIN_AUX_17
AD27
VCCPRIM_1P8_10 VCC_AUX_PCH_SENSE GPP_R 1.8V
AF20 AH39 VCC_AUX_PCH_SENSE 99
VCCPRIM_1P8_11 VCCIN_AUX_VCCSENSE VSS_AUX_PCH_SENSE
AF22 AH41 VSS_AUX_PCH_SENSE 99
RH205 1 @ 2 0_0402_5% VCCPRIM_1P8_12 VCCIN_AUX_VSSSENSE
AF23
VCCPRIM_1P8_13 need confirm VCCDPHY connect method
GPP_J 1.8V(only)
AF25 BD1 +VCCDPHY_1P24 RVP PWR prvide
VCCPRIM_1P8_14 VCCDPHY_1P24_1
AF27 BD2
VCCPRIM_1P8_15 VCCDPHY_1P24_2 0.1A BEP only out, and 1pcs MLCC only
+3VALW_PCH VCCDPHY_1P24_3
BE1 GPP_S 1.8V(only)
+VCCPGPPI AA18
VCCPGPPI
1U_6.3V_M_X5R_0201
P29 In
VCCA_CLKLDO_1P8_1 +VCCA_CLKLDO_1P8
RH206 1 @ 2 0_0402_5% AP22 R29 GPD 3.3V(only)
+VCCPGPPR VCCPGPPR VCCA_CLKLDO_1P8_2
1 AG18 0.1A trace width need to 40mil
+VCCPGPPHK VCCPGPPHK
CH271
PDG: VCCDSW_3P3 AM37 AK21 out

+VCCPGPPEF VCCPGPPEF VCCPRIM1P05_OUT_PCH_3 +VCCPRIM_1P05_OUT
0.1A
C
Placeholder 1* 0402 capacitor on primary side +VCCPGPPD AU24
VCCPGPPD GPP_G Pre-PAD 3.3V or 1.8V C
as close as possible to the vias. +VCCPRIM_3P3 AP19 W20 +VCC1P05_OUT_FET
2@ VCCPRIM_3P3_2 VCC1P05_OUT_FET_1
+VCCPGPPBC AP24 W22
VCCPGPPBC VCC1P05_OUT_FET_2 1.5A
+VCCPGPPA AP29 W23
VCCPRIM_3P3_3 VCC1P05_OUT_FET_3
W25
VCC1P05_OUT_FET_4 +1.8VALW +VCCA_CLKLDO_1P8
+VCCPRIM_3P3 AT35
VCCRTC +VCCPRTC_3P3 VCCPRIM_3P3_4 0.5A
AN29 +VNN_BYPASS
+VCCPDSW_3P3 +VCCPRIM_1P8 VCC_VNNEXT_1P05 use inside FIVR
Y37 0.165A
RH216 1 @ 2 0_0402_5% VCCPRIM_1P8_16 impact power consumption RH1130 1 @ 2 0_0603_5%
AN28 +V1.05A_BYPASS
VCC_V1P05EXT_1P05 0608
BD48
VCCDSW_3P3_1
1U_0402_6.3V6K
.1U_0402_10V6-K
BD49 0.5A
VCCDSW_3P3_2
1
1
100K_0402_5%
1 1 0.1A BE49 1 2 LH5

VCCDSW_3P3_3
CH245
RH42
RH22
CH244
@ @ @ 0_0402_5%
0.68UH_SDTT25201B-R68MS_3.3A_20%
2 2 TIGERLAKE-H-PCH_FCBGA943
2
2
@ VCCA_CLKLDO_R
47U_6.3V_M_X5R_0805_H1.25
1U_6.3V_M_X5R_0201
1 1
CH14
CH19
+VCCPRIM_1P05_OUT
+VCCPRIM_1P8 +VCCPGPPD
+VCCDPHY_1P24 2 2@
4.7U_0402_6.3V6M
RH791 1 @ 2 0_0402_5% PDG: VCCDPHY_1P24
1M_0402_5%
1
@
RH23
1 4.7u_0402 *1
CH299
@ RC859 Require minimum power plane
1U_6.3V_M_X5R_0201
base on HDA level fine tune 2 width of 3mm from BGA to
Capacitor. Require immediate PDG: VCCA_CLKLDO_1P8
2 2
+3VALW_PCH +VCCPRIM_1P8 +VCCPGPPR GND reference
Inductor by default is a placeholder. If stuffed, the
680nF 1 inductor needs to meet following requirement:
B B
(Placeholder) Rated at least 150mA; DCR = 0.036Ohm +/- 20%
RH790 1 @ 2 0_0402_5%
+VNN_BYPASS +V1.05A_BYPASS
RH1164 1 @ 2 0_0402_5% +VCCLDOSTD_OUT_0P85 Option 1: stuff with 0 ohm if the inductor is not stuffed.
0 ohm_0603 1 Option 2: stuff 100 mohm if the inductor stuffed
trace width >40mil 100 mohm_0603
CV1537 need within 3mm from PCH dege
10U 6.3V M X5R 0402
1
10U 6.3V M X5R 0402
1 2
1
Place the cap near to package pin DR15 and DR12

1 47u_0603 1 right after signal breakout
CH29
RH24 @ @ CV1537
CH30
100K_0201_5% RH27 @ @ 2.2U_0402_6.3V6M

+VCCPRIM_3P3 +VCCPRIM_1P8 +VCCPGPPA 2 100K_0201_5% 1
2
2
2
RH792
1 @ 2 0_0402_5%
RH1144 1 @ 2 0_0402_5%
EXCEL PDG MERGE to 3.3_S5

PDG GPP_A per-pad config power, control by SW,not HW
CRB1 3.3, CRB2 1.8
A A

X60-TGL-H
Vinafix.com
Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. PCH (7/8) PWR
5 4 3 2 1
5 4 3 2 1
UH1H UH1I
8 OF 9 9 OF 9
A17 AJ23 AW25 F42
VSS_163VSS_240 VSS_1 VSS_78
A2 AJ25 AW39 F8
A28 AJ27 AY25 G1
A3 AJ28 AY43 G41
A33 AK12 AY5 G48
A37 AK17 AY7 G49
A4 AK18 B1 G9
A41 AK24 B2 H25
D VSS_170VSS_247 VSS_8 VSS_85 D
A45 AK25 B4 H43
A46 AK26 B46 H8
A47 AK28 B48 J11
A48 AK29 B49 J25
AA12 AK30 B6 J39
AA13 AK32 BA41 J9
AA20 AK33 BA43 K11
AA22 AK35 BA49 K39
AA23 AK38 BA9 K45
AA25 AK45 BB25 K5
AA29 AK5 BB44 L14
AA30 AL19 BB8 L25
AA32 AL22 BC11 M12
AA33 AL24 BC15 M17
AA35 AL25 BC19 M19
AA37 AL26 BC24 M21
AA49 AL28 BC25 M22
AA5 AL29 BC26 M24
AB28 AL31 BC31 M25
AC13 AM1 BC35 M26
AC18 AM12 BC39 M28
AC35 AM17 BC41 M29
AC37 AM33 BC9 M31
AC4 AM35 BF1 M33
AC45 AM38 BF13 M38
AC5 AM49 BF2 M49
AC9 AN17 BF42 M5
AD11 AN19 BF48 P12
AD12 AN22 BF49 P21
AD13 AN24 BG17 P24
AD15 AN25 BG2 P25
AD17 AN26 BG22 P28
AD18 AN31 BG25 P38
AD28 AN33 BG28 P4
AD35 AP12 BG33 P45
AD37 AP17 BG37 P5
AD45 AP21 BG41 R21
C AD49 AP25 BG48 R24 C
AD5 AP26 BG9 R25
AD6 AP28 C1 R28
AD8 AP31 C12 T1
AD9 AP33 C24 T12
AE12 AP38 C4 T15
AE13 AP45 C49 T17
AE15 AP5 C7 T33
AE17 AT1 D1 T38
AE18 AT12 D13 T49
AE35 AT17 D2 U19
AE37 AT19 D24 U21
AE45 AT21 D25 U22
AE5 AT22 D33 U24
AF28 AT24 D37 U25
AG1 AT25 D48 U26
AG12 AT26 D49 U28
AG17 AT28 D7 U29
AG20 AT29 E13 U31
AG22 AT31 E15 V12
AG23 AT33 E19 V17
AG25 AT37 E22 V21
AG27 AT49 E24 V22
AG28 AT5 E25 V24
AG35 AU25 E26 V25
AG37 AU41 E31 V26
AG49 AV11 E33 V33
AH12 AV39 E35 V38
AH13 AV45 E37 V5
AH15 AV5 E39 W27
AH35 AW11 E9 W28
AH38 AW24 F25 W30
W44
VSS_155
Y12
VSS_156
TIGERLAKE-H-PCH_FCBGA943 Y13
VSS_157
Y15
@ VSS_158
Y17
VSS_159
Y18
B VSS_160 B
Y32
VSS_161
Y38
VSS_162
@
A A

X60-TGL-H
C 0.1
PCH (8/8) VSS
5
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2
1
Sheet 23 of 110
5 4 3 2 1
TABLE : CPU ITP DEBUG REPORT +VCCSTG_CPU
Individual DCI 2.0

No use Port w/o connector
2
PDG 51ohm.
RVP 100ohm. RH601 RH600 RH624 GPP_B18_NO_REBOOT
need to confirm 51_0402_1% @ 51_0402_1% @ 51_0402_1% +3VS * 0 = Disable ¨No Reboot〃 mode. (Default)
R591 NO ASM NO ASM ASM 1 = Enable ¨No Reboot〃 mode (PCH will disable the
TCO
1
R593 NO ASM NO ASM ASM Timer system reboot feature). This function is useful
1
PCH_TDO RH612 1 @ 2 0_0201_5% XDP_TDO PAD 1 @ SFF #5
20 PCH_TDO ITH9 when running ITP/XDP.
D R594 NO ASM NO ASM ASM PCH_TDI RH610 1 @ 2 0_0201_5% XDP_TDI PAD 1 @ SFF #8 @ RH607 Place near PCH D
20 PCH_TDI ITH10
1K_0402_5%
R595 NO ASM NO ASM ASM PCH_TMS RH609 1 @ 2 0_0201_5% XDP_TMS PAD 1 @ SFF #6
20 PCH_TMS ITH11
2
R596 NO ASM NO ASM ASM PCH_TCK RH602 1 @ 2 0_0201_5% PCH_TCK1 PAD 1 @ SFF #20 GPP_B18_NO_REBOOT
GPP_B18_NO_REBOOT 20
20 PCH_TCK ITH12
R657 NO ASM NO ASM ASM JTAGX RH608 1 @ 2 0_0201_5% XDP_TCK0 PAD 1 @ SFF #7
20 JTAGX ITH13
R658 NO ASM NO ASM ASM 17,24,27 PCH_SPI0_IO2
2
RH625
1
@ 51_0402_1%
R102 NO ASM ASM NO ASM DEFENSIVE A0 PO BOARDS.
INTERNAL 60 - 100OHM ODT TO GND @ RH613
R597 NO ASM ASM NO ASM
1
1K_0402_1%
R9907 NO ASM ASM ASM
2
RH622 1 @ 2 0_0201_5% XDP_TDO
JXDP1 NO ASM ASM NO ASM 10 PROC_TDO
RH620 1 @ 2 0_0201_5% XDP_TDI
C70 NO ASM ASM NO ASM 10 PROC_TDI
RH619 1 @ 2 0_0201_5% XDP_TMS
R96 NO ASM ASM NO ASM 10 PROC_TMS
RH618 1 @ 2 0_0201_5% XDP_TCK0
R101 NO ASM ASM NO ASM 10 PROC_TCK
2
USB30_TX4_P RH1217 1 NPI@ 2 0_0402_5% PAD 1 @ SFF #1
R9909 NO ASM ASM ASM RH616
17 USB30_TX4_P ITH34
51_0402_1% USB30_TX4_N RH1216 1 NPI@ 2 0_0402_5% PAD 1 @ SFF #2
R9910 NO ASM ASM ASM 17 USB30_TX4_N ITH33
USB30_RX4_P RH1215 1 NPI@ 2 0_0402_5% PAD 1 @ SFF #3
R9916 NO ASM ASM ASM 17 USB30_RX4_P ITH32
1
C USB30_RX4_N RH1214 1 NPI@ 2 0_0402_5% PAD 1 @ SFF #4 C
R99 NO ASM ASM ASM 17 USB30_RX4_N ITH31
R9912 NO ASM ASM ASM +3V_SPI +3VALW_PCH

R9934 NO ASM ASM ASM
2
R9930 NO ASM ASM ASM RH626 RH605
2.2K_0402_5% 1K_0402_5% JSFFD1ME@
R9931 NO ASM ASM ASM @ @ SFF #1 @ 1 PAD SFF1_USB30_TX4_CON_P 1
ITH35 SFF2_USB30_TX4_CON_N 1
SFF #2 @ 1 PAD 2
R9932 NO ASM ASM ASM @ ITH36
1
RH606 1 2 1K_0402_5% PAD 1 @ @ 1 PAD SFF3_USB30_RX4_CON_P 3 2
16,21,79 EC_RSMRST_N ITH14 SFF #3 ITH37 3
PAD 1 @ SFF #4 @ 1 PAD SFF4_USB30_RX4_CON_N 4
R9933 NO ASM ASM ASM 17,24,27 PCH_SPI0_IO2
PAD 1 @
ITH15
SFF #5
ITH38
@ 1 PAD SFF5_XDP_TDO 5 4
20 DBG_PMODE ITH16 ITH39 SFF6_XDP_TMS 5
PAD 1 @ SFF #6 @ 1 PAD 6
21,79 PBTN_OUT_N ITH17 ITH40 SFF7_XDP_TCK0 6
PAD 1 @ SFF #7 @ 1 PAD 7
17 SYS_RESET_N ITH18 ITH41 SFF8_XDP_TDI 7
SFF #8 @ 1 PAD 8
ITH42 SFF9_XDP_TRST# 8
SFF #9 @ 1 PAD 9
ITH43 SFF10_CFG16 9
LOGIC RH623 1 NPI@ 2 0_0402_5% PAD 1 @ SFF #14 SFF #10 @ 1 PAD 10
10 CFG3 ITH19 ITH44 SFF11_CFG0 10
SFF #11 @ 1 PAD 11
ITH45 SFF12_CFG1 11
SFF #12 @ 1 PAD 12
TABLE : PCH ITP DEBUG REPORT SFF #13
ITH46
@ 1 PAD SFF13_CFG2 13 12
ITH47 SFF14_CFG3 13
SFF #14 @ 1 PAD 14
ITH48 SFF15_CFG4 14
SFF #15 @ 1 PAD 15
No use Individual DCI 2.0 SFF #16
ITH49
@ 1 PAD SFF16_CFG5 16 15
ITH50 16
1
Port w/o connector SFF #17 ITH51

@ 1 PAD SFF17_CFG6
SFF18_CFG7
17
17
SFF #18 @ 1 PAD 18
ITH52 18
@ RC887 19
51_0402_5% 1 PAD SFF20_PCH_TCK1 R4 1 2 0_0402_5% PCH_TCK_SSF 20 19
R93 NO ASM ASM NO ASM SFF #20 ITH53 @ @
20
21
2
B RH603 1 @ 2 0_0402_5% RH611 1 @ 2 0_0402_5% XDP_TRST# PAD 1 @ 22 GND1 B

JXDP1 NO ASM ASM NO ASM 19 CPU_TRST_N ITH20 SFF #9 GND2
PCH_PRDY_N RH614 1 @ 2 0_0402_5% XDP_PRDY# PAD 1 @
R9917 NO ASM ASM NO ASM 16 PCH_PRDY_N ITH21
HIGHS_FC5AF201-1151H
PCH_PREQ_N RH615 1 @ 2 0_0402_5% XDP_PREQ# PAD 1 @
R101 NO ASM ASM NO ASM 16 PCH_PREQ_N ITH22
R9908 NO ASM ASM NO ASM PROC_TRST_N

10 PROC_TRST_N
R9911 NO ASM ASM NO ASM RH621 1 @ 2 0_0402_5% PAD 1 @ SFF #10
10 PROC_PRDY_N 10 CFG16 ITH23
R9913 NO ASM ASM NO ASM RH617 1 @ 2 0_0402_5% PAD 1 @ SFF #11
10 PROC_PREQ_N 10 CFG0 ITH24
R9915 NO ASM ASM NO ASM PAD 1 @ SFF #12
10 CFG1 ITH25
PAD 1 @ SFF #13
10 CFG2 ITH26
PAD 1 @ SFF #15
10 CFG4 ITH27
LOGIC
PAD 1 @ SFF #16
10 CFG5 ITH28
TABLE : Functional Strap PAD 1 @
10 CFG6 ITH29 SFF #17
GPP_B18/GSPI0_MOSI (No Reboot) R563 PAD 1 @
10 CFG7 ITH30 SFF #18
HIGH Enable "No Reboot" Mode ASM
LOW Disable "No Reboot" Mode (Default ) NO ASM LOGIC
A A
Issued Date 2021/04/07 Deciphered Date 2021/04/07 XDP
5
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4 3
2
Size Document Number
Custom
Date:
HY568
1
Sheet 24 of 110
Rev
0.1
5 4 3 2 1
DDR4 SO-DIMM A
Follow CRB ball map TOP 9.2 Height CRB 0ohm_0603 to 1.2V+1.2V
+1.2V+1.2V +1.2V+1.2V
+1.2V+1.2V +1.2V+1.2V JDDRL1B
1
RD5
DDRA_MA3
STD DDRA_MA2
5.6A JDDRL1A 240_0402_5% 131 132
8 DDRA_MA3 DDRA_MA1 A3 A2 DDRA_EVENT_N DDRA_MA2 8
133 134
STD 8 DDRA_MA1
135 A1 EVENT_n/NF 136
2
1 2 DDRA_CLK0_P 137 VDD_9 VDD_10 138 DDRA_CLK1_P
DDRA_DQ3 VSS_1 VSS_2 DDRA_DQ0 DDRA_EVENT_N 8 DDRA_CLK0_P DDRA_CLK0_N CK0_t CK1_t/NF DDRA_CLK1_N DDRA_CLK1_P 8
3 4 139 140
8 DDRA_DQ3 DQ5 DQ4 DDRA_DQ0 8 8 DDRA_CLK0_N CK0_c CK1_c/NF DDRA_CLK1_N 8
5 6 141 142
DDRA_DQ1 7 VSS_3 VSS_4 8 DDRA_DQ2 DDRA_PARITY 143 VDD_11 VDD_12 144 DDRA_MA0
8 DDRA_DQ1 DQ1 DQ0 DDRA_DQ2 8 8 DDRA_PARITY Parity A0 DDRA_MA0 8
9 10
DDRA_DQS0_N 11 VSS_5 VSS_6 12
D 8 DDRA_DQS0_N DDRA_DQS0_P DQS0_C DM0_n/DBI0_n/NC DDRA_BA1 DDRA_MA10_AP D
13 14 145 146
8 DDRA_DQS0_P DQS0_t VSS_7 DDRA_DQ6 8 DDRA_BA1 BA1 A10/AP 148 DDRA_MA10_AP 8
15 16 147
DDRA_DQ7 VSS_8 DQ6 DDRA_DQ6 8 DDRA_CS0_N VDD_13 VDD_14 150 DDRA_BA0
17 18 149
8 DDRA_DQ7 DQ7 VSS_9 DDRA_DQ5 8 DDRA_CS0_N DDRA_MA14_WE_N CS0_n BA0 152 DDRA_MA16_RAS_N DDRA_BA0 8
19 20 151
DDRA_DQ4 VSS_10 DQ2 DDRA_DQ5 8 8 DDRA_MA14_WE_N WE_n/A14 RAS_n/A16 154 DDRA_MA16_RAS_N 8
21 22 153
8 DDRA_DQ4 DQ3 VSS_11 DDRA_DQ8 DDRA_ODT0 VDD_15 VDD_16 156 DDRA_MA15_CAS_N
23 24 155
DDRA_DQ9 VSS_12 DQ12 DDRA_DQ8 8 8 DDRA_ODT0 DDRA_CS1_N ODT0 CAS_n/A15 158 DDRA_MA13 DDRA_MA15_CAS_N 8
25 26 157
8 DDRA_DQ9 DQ13 VSS_13 DDRA_DQ10 8 DDRA_CS1_N CS1_n A13 160 DDRA_MA13 8
27 28 159
DDRA_DQ11 VSS_14 DQ8 DDRA_DQ10 8 DDRA_ODT1 VDD_17 VDD_18 162
29 30 161
8 DDRA_DQ11 DQ9 VSS_15 DDRA_DQS1_N 8 DDRA_ODT1 ODT1 C0/CS2_n/NC 164 +VREF_CA_DIMMA
31 32 163
VSS_16 DQS1_c DDRA_DQS1_P DDRA_DQS1_N 8 VDD_19 VREFCA 166 DDRA_SA2
33 34 165
DM1_n/DBl1_n/NC DQS1_t DDRA_DQS1_P 8 C1/CS3_n/NC SA2 168
35 36 167
.1U_0402_10V6-K
VSS_17 VSS_18 VSS_53 VSS_54 170
2.2U_0603_6.3V6K
DDRA_DQ12 37 38 DDRA_DQ14 DDRA_DQ32 169 DDRA_DQ35
8 DDRA_DQ12 DQ15 DQ14 DDRA_DQ14 8 8 DDRA_DQ32 DQ37 DQ36 172 DDRA_DQ35 8 1 1
39 40 171
DDRA_DQ13 41 VSS_19 VSS_20 42 DDRA_DQ15 DDRA_DQ34 173 VSS_55 VSS_56 174 DDRA_DQ33
8 DDRA_DQ13 DQ10 DQ11 DDRA_DQ15 8 8 DDRA_DQ34 DQ33 DQ32 176 DDRA_DQ33 8
43 44 175
DDRA_DQ17 45 VSS_21 VSS_22 46 DDRA_DQ18 DDRA_DQS4_N 177 VSS_57 VSS_58 178 2 2
8 DDRA_DQ17 DQ21 DQ20 DDRA_DQ18 8 8 DDRA_DQS4_N DDRA_DQS4_P DQS4_c DM4_n/DBl4_n/NC 180
47 48 179
CD2
CD3
DDRA_DQ19 VSS_23 VSS_24 DDRA_DQ16 8 DDRA_DQS4_P DQS4_t VSS_59 182 DDRA_DQ36
49 50 181
8 DDRA_DQ19 DQ17 DQ16 DDRA_DQ16 8 DDRA_DQ38 VSS_60 DQ39 184 DDRA_DQ36 8
51 52 183
DDRA_DQS2_N VSS_25 VSS_26 8 DDRA_DQ38 DQ38 VSS_61 186 DDRA_DQ37
53 54 185
8 DDRA_DQS2_N DDRA_DQS2_P DQS2_c DM2_n/DBl2_n/NC DDRA_DQ39 VSS_62 DQ35 188 DDRA_DQ37 8
55 56 187
8 DDRA_DQS2_P DQS2_t VSS_27 DDRA_DQ22 8 DDRA_DQ39 DQ34 VSS_63 190 DDRA_DQ41
57 58 189
DDRA_DQ20 VSS_28 DQ22 DDRA_DQ22 8 DDRA_DQ40 VSS_64 DQ45 192 DDRA_DQ41 8
59 60 191
8 DDRA_DQ20 DQ23 VSS_29 DDRA_DQ23 8 DDRA_DQ40 DQ44 VSS_65 194 DDRA_DQ42
61 62 193
DDRA_DQ21 VSS_30 DQ18 DDRA_DQ23 8 DDRA_DQ43 VSS_66 DQ41 196 DDRA_DQ42 8
63 64 195
8 DDRA_DQ21 DQ19 VSS_31 DDRA_DQ26 8 DDRA_DQ43 DQ40 VSS_67 198 DDRA_DQS5_N
65 66 197
DDRA_DQ24 VSS_32 DQ28 DDRA_DQ26 8 VSS_68 DQS5_c 200 DDRA_DQS5_P DDRA_DQS5_N 8
67 68 199
8 DDRA_DQ24 DQ29 VSS_33 DDRA_DQ25 DM5_n/DBl5_n DQS5_t 202 DDRA_DQS5_P 8
69 70 201
DDRA_DQ27 VSS_34 DQ24 DDRA_DQ25 8 DDRA_DQ44 VSS_69 VSS_70 204 DDRA_DQ45
71 72 203
8 DDRA_DQ27 DQ25 VSS_35 DDRA_DQS3_N 8 DDRA_DQ44 DQ46 DQ47 206 DDRA_DQ45 8
73 74 205
VSS_36 DQS3_c DDRA_DQS3_P DDRA_DQS3_N 8 DDRA_DQ46 VSS_71 VSS_72 208 DDRA_DQ47
75 76 207
DM3_n/DBl3_n/NC DQS3_t DDRA_DQS3_P 8 8 DDRA_DQ46 DQ42 DQ43 210 DDRA_DQ47 8
77 78 209
81 82 213
85 86 217
87 VSS_41 VSS_42 88 DDRA_DQS6_N 219 VSS_77 VSS_78 220
C C
CB5/NC CB4/NC 8 DDRA_DQS6_N DDRA_DQS6_P DQS6_c DM6_n/DBl6_n/NC 222
89 90 221
VSS_43 VSS_44 8 DDRA_DQS6_P DQS6_t VSS_79 224 DDRA_DQ53
91 92 223
CB1/NC CB0/NC DDRA_DQ54 VSS_80 DQ54 226 DDRA_DQ53 8
93 94 225
VSS_45 VSS_46 8 DDRA_DQ54 DQ55 VSS_81 228 DDRA_DQ55
95 96 227
DQS8_c DBI8_n/DBI_n/NC DDRA_DQ52 VSS_82 DQ50 230 DDRA_DQ55 8
97 98 229
DQS8_t VSS_47 8 DDRA_DQ52 DQ51 VSS_83 232 DDRA_DQ58
99 100 231
VSS_48 CB6/NC DDRA_DQ56 VSS_84 DQ60 234 DDRA_DQ58 8
101 102 233
CB2/NC VSS_49 8 DDRA_DQ56 DQ61 VSS_85 236 DDRA_DQ59
103 104 235
VSS_50 CB7/NC DDRA_DQ57 VSS_86 DQ57 238 DDRA_DQ59 8
105 106 237
CB3/NC VSS_51 PCH_DRAMRST_N 8 DDRA_DQ57 DQ56 VSS_87 240 DDRA_DQS7_N
107 108 239
DDRA_CKE0 VSS_52 RESET_n DDRA_CKE1 PCH_DRAMRST_N 21,26 VSS_88 DQS7_c 242 DDRA_DQS7_P DDRA_DQS7_N 8
8 DDRA_CKE0
109 110 241
CKE0 CKE1 DDRA_CKE1 8 DM7_n/DBl7_n/NC DQS7_t 244 DDRA_DQS7_P 8
111 112 243
DDRA_BG1 113 VDD_1 VDD_2 114 DDRA_ACT_N DDRA_DQ60 245 VSS_89 VSS_90 246 DDRA_DQ61
8 DDRA_BG1 BG1 ACT_n DDRA_ACT_N 8 1 8 DDRA_DQ60 DQ62 DQ63 248 DDRA_DQ61 8
DDRA_BG0 115 116 DDRA_ALERT_N 247
8 DDRA_BG0 BG0 ALERT_n DDRA_ALERT_N 8 DDRA_DQ63 VSS_91 VSS_92 250 DDRA_DQ62
117 118 CD69 249
DDRA_MA12 VDD_3 VDD_4 DDRA_MA11 0.1U_0402_10V7K 8 DDRA_DQ63 DQ58 DQ59 252 DDRA_DQ62 8
8 DDRA_MA12
119 120 251
DDRA_MA9 A12 A11 DDRA_MA7 DDRA_MA11 8 2 SMB_CLK_S3 VSS_93 VSS_94 254 SMB_DATA_S3
121 122 20,26 SMB_CLK_S3 253
8 DDRA_MA9 A9 A7 DDRA_MA7 8 @ DDRA_VDDSPD SCL SDA 256 DDRA_SA0 SMB_DATA_S3 20,26
123 124 RD18 1 @ 2 0_0402_5% 255
DDRA_MA8 VDD_5 VDD_6 DDRA_MA5 +3VS VDDSPD SA0 258
8 DDRA_MA8
125 126 257 +0.6VS
DDRA_MA6 A8 A5 DDRA_MA4 DDRA_MA5 8 VPP_1 Vtt 260 DDRA_SA1
127 128 1 1 259 1.1A
8 DDRA_MA6 A6 A4 DDRA_MA4 8 VPP_2 SA1
129 130
VDD_7 VDD_8 CD27 CD28 261 262
2.2U_0603_6.3V6K .1U_0402_10V6-K GND_1 GND_2
2 2 ARGOS_D4AS0-26001-1P52
ARGOS_D4AS0-26001-1P52 ME@
ME@
+2.5V
1A
+3VS +3VS +3VS

+1.2V
+VREF_CA_DIMMA_R
1
Change RD2 to 0ohm jump RD22 RD24 RD26
1
B B
0_0402_5% 0_0402_5% 0_0402_5%
RD1 @ @ @
1K_0402_1%
2
Note:
2
RD2 1 2 2_0402_5% +VREF_CA_DIMMA DDRA_SA0 DDRA_SA1 DDRA_SA2

VREF trace width:20 mils at least
1
Spacing:20mils to other signal/planes

.1U_0402_10V6-K
2
Place near DIMM scoket
1K_0402_1%
1 1
CD21
CD1 RD23 RD25 RD27

RD3
0.022U_0402_16V7-K 0_0402_5% 0_0402_5% 0_0402_5%

2
2 2 1
1
1
@ @ @
RD4
24.9_0402_1%
SPD Address 0H
2
For EMC
A A
Issued Date 2021/04/07 Deciphered Date 2021/04/07 DDRVI SO-DIMM A

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C
HY568 0.3
Vinafix.com
5 4 3 2 1
5 4 3 2 1
DDR4 SO-DIMM B
Follow CRB ball map TOP 5.2 Height
+1.2V +1.2V +1.2V +1.2V
+1.2V
5.6A JDDRH1A +1.2V+1.2V +1.2V+1.2V
1
RVS RD6
1 2 240_0402_5% JDDRH1B
DDRB_DQ0 3 VSS_1 VSS_2 4 DDRB_DQ4
9 DDRB_DQ0
5 DQ5 DQ4 6
DDRB_DQ4 9
RVS
2
DDRB_DQ1 7 VSS_3 VSS_4 8 DDRB_DQ3 DDRB_MA3 131 132 DDRB_MA2
9 DDRB_DQ1 DQ1 DQ0 DDRB_DQ3 9 DDRB_EVENT_N 9 DDRB_MA3 DDRB_MA1 A3 A2 DDRB_EVENT_N DDRB_MA2 9
9 10 133 134
D DDRB_DQS0_N VSS_5 VSS_6 9 DDRB_MA1 A1 EVENT_n/NF D
11 12 135 136
9 DDRB_DQS0_N DDRB_DQS0_P DQS0_C DM0_n/DBI0_n/NC DDRB_CLK0_P VDD_9 VDD_10 DDRB_CLK1_P
13 14 137 138
9 DDRB_DQS0_P DQS0_t VSS_7 DDRB_DQ5 9 DDRB_CLK0_P DDRB_CLK0_N CK0_t CK1_t/NF DDRB_CLK1_N DDRB_CLK1_P 9
15 16 139 140
DDRB_DQ7 VSS_8 DQ6 DDRB_DQ5 9 9 DDRB_CLK0_N CK0_c CK1_c/NF DDRB_CLK1_N 9
17 18 141 142
9 DDRB_DQ7 DQ7 VSS_9 DDRB_DQ2 DDRB_PARITY VDD_11 VDD_12 DDRB_MA0
19 20 143 144
DDRB_DQ6 VSS_10 DQ2 DDRB_DQ2 9 9 DDRB_PARITY Parity A0 DDRB_MA0 9
21 22
9 DDRB_DQ6 DQ3 VSS_11 DDRB_DQ8
23 24
DDRB_DQ11 VSS_12 DQ12 DDRB_DQ8 9 DDRB_BA1 DDRB_MA10_AP
25 26 145 146
9 DDRB_DQ11 DQ13 VSS_13 DDRB_DQ9 9 DDRB_BA1 BA1 A10/AP DDRB_MA10_AP 9
27 28 147 148
DDRB_DQ12 VSS_14 DQ8 DDRB_DQ9 9 DDRB_CS0_N VDD_13 VDD_14 DDRB_BA0
29 30 9 DDRB_CS0_N
149 150
9 DDRB_DQ12 DQ9 VSS_15 DDRB_DQS1_N DDRB_MA14_WE_N CS0_n BA0 DDRB_MA16_RAS_N DDRB_BA0 9
31 32 151 152
VSS_16 DQS1_c DDRB_DQS1_P DDRB_DQS1_N 9 9 DDRB_MA14_WE_N WE_n/A14 RAS_n/A16 DDRB_MA16_RAS_N 9
33 34 153 154
DM1_n/DBl1_n/NC DQS1_t DDRB_DQS1_P 9 DDRB_ODT0 VDD_15 VDD_16 DDRB_MA15_CAS_N
35 36 155 156
DDRB_DQ14 VSS_17 VSS_18 DDRB_DQ13 9 DDRB_ODT0 DDRB_CS1_N ODT0 CAS_n/A15 DDRB_MA13 DDRB_MA15_CAS_N 9
37 38 9 DDRB_CS1_N 157 158
9 DDRB_DQ14 DQ15 DQ14 DDRB_DQ13 9 CS1_n A13 DDRB_MA13 9
39 40 159 160
DDRB_DQ15 41 VSS_19 VSS_20 42 DDRB_DQ10 DDRB_ODT1 161 VDD_17 VDD_18 162
9 DDRB_DQ15 DQ10 DQ11 DDRB_DQ10 9 9 DDRB_ODT1 ODT1 C0/CS2_n/NC +VREF_CA_DIMMB
43 44 163 164
DDRB_DQ20 45 VSS_21 VSS_22 46 DDRB_DQ16 165 VDD_19 VREFCA 166 DDRB_SA2
9 DDRB_DQ20 DQ21 DQ20 DDRB_DQ16 9 C1/CS3_n/NC SA2
47 48 167 168
DDRB_DQ19 49 VSS_23 VSS_24 50 DDRB_DQ17 DDRB_DQ34 169 VSS_53 VSS_54 170 DDRB_DQ33
.1U_0402_10V6-K
9 DDRB_DQ19 DDRB_DQ17 9 9 DDRB_DQ34 DDRB_DQ33 9
2.2U_0603_6.3V6K
51 DQ17 DQ16 52 171 DQ37 DQ36 172 1
VSS_25 VSS_26 VSS_55 VSS_56 1
DDRB_DQS2_N 53 54 DDRB_DQ32 173 174 DDRB_DQ37
9 DDRB_DQS2_N DDRB_DQS2_P DQS2_c DM2_n/DBl2_n/NC 9 DDRB_DQ32 DQ33 DQ32 DDRB_DQ37 9
55 56 175 176
9 DDRB_DQS2_P DQS2_t VSS_27 DDRB_DQ21 DDRB_DQS4_N VSS_57 VSS_58
57 58 177 178
DDRB_DQ18 VSS_28 DQ22 DDRB_DQ21 9 9 DDRB_DQS4_N DDRB_DQS4_P DQS4_c DM4_n/DBl4_n/NC 2 2
59 60 179 180
9 DDRB_DQ18 DQ23 VSS_29 9 DDRB_DQS4_P DQS4_t VSS_59
CD31
61 62 DDRB_DQ23 181 182 DDRB_DQ35
CD30
DDRB_DQ22 VSS_30 DQ18 DDRB_DQ23 9 DDRB_DQ39 VSS_60 DQ39 DDRB_DQ35 9
63 64 183 184
9 DDRB_DQ22 DQ19 VSS_31 DDRB_DQ31 9 DDRB_DQ39 DQ38 VSS_61 DDRB_DQ38
65 66 185 186
67 68 187 188
9 DDRB_DQ30 DQ29 VSS_33 DDRB_DQ29 9 DDRB_DQ36 DQ34 VSS_63 DDRB_DQ45
69 70 189 190
71 72 191 192
9 DDRB_DQ24 DQ25 VSS_35 DDRB_DQS3_N 9 DDRB_DQ41 DQ44 VSS_65 DDRB_DQ42
73 74 193 194
VSS_36 DQS3_c DDRB_DQS3_P DDRB_DQS3_N 9 DDRB_DQ40 VSS_66 DQ41 DDRB_DQ42 9
75 76 195 196
DM3_n/DBl3_n/NC DQS3_t DDRB_DQS3_P 9 9 DDRB_DQ40 DQ40 VSS_67 DDRB_DQS5_N
77 78 197 198
DDRB_DQ28 VSS_37 VSS_38 DDRB_DQ27 VSS_68 DQS5_c DDRB_DQS5_P DDRB_DQS5_N 9
79 80 199 200
9 DDRB_DQ28 DQ30 DQ31 DDRB_DQ27 9 DM5_n/DBl5_n/NC DQS5_t DDRB_DQS5_P 9
81 82 201 202
DDRB_DQ26 83 VSS_39 VSS_40 84 DDRB_DQ25 DDRB_DQ43 203 VSS_69 VSS_70 204 DDRB_DQ46
9 DDRB_DQ26 DQ26 DQ27 DDRB_DQ25 9 9 DDRB_DQ43 DQ46 DQ47 DDRB_DQ46 9
C 85 86 205 206 C
87 VSS_41 VSS_42 88 DDRB_DQ47 207 VSS_71 VSS_72 208 DDRB_DQ44
CB5/NC CB4/NC 9 DDRB_DQ47 DQ42 DQ43 DDRB_DQ44 9
89 90 209 210
CB1/NC CB0/NC 9 DDRB_DQ49 DQ52 DQ53 DDRB_DQ53 9
93 94 213 214
DQS8_c DBI8_n/DBI_n/NC 9 DDRB_DQ50 DQ49 DQ48 DDRB_DQ48 9
97 98 217 218
99 DQS8_t VSS_47 100 DDRB_DQS6_N 219 VSS_77 VSS_78 220
VSS_48 CB6/NC 9 DDRB_DQS6_N DDRB_DQS6_P DQS6_c DM6_n/DBl6_n/NC
101 102 221 222
CB2/NC VSS_49 9 DDRB_DQS6_P DQS6_t VSS_79 DDRB_DQ52
103 104 223 224
VSS_50 CB7/NC DDRB_DQ54 VSS_80 DQ54 DDRB_DQ52 9
105 106 225 226
CB3/NC VSS_51 PCH_DRAMRST_N 9 DDRB_DQ54 DQ55 VSS_81 DDRB_DQ51
107 108 227 228
DDRB_CKE0 VSS_52 RESET_n DDRB_CKE1 PCH_DRAMRST_N 21,25 DDRB_DQ55 VSS_82 DQ50 DDRB_DQ51 9
109 110 229 230
9 DDRB_CKE0 CKE0 CKE1 DDRB_CKE1 9 9 DDRB_DQ55 DQ51 VSS_83 DDRB_DQ56
111 112 231 232
DDRB_BG1 VDD_1 VDD_2 DDRB_ACT_N DDRB_DQ57 VSS_84 DQ60 DDRB_DQ56 9
113 114 233 234
9 DDRB_BG1 DDRB_BG0 BG1 ACT_n DDRB_ALERT_N DDRB_ACT_N 9 9 DDRB_DQ57 DQ61 VSS_85 DDRB_DQ61
115 116 235 236
9 DDRB_BG0 BG0 ALERT_n DDRB_ALERT_N 9 DDRB_DQ58 VSS_86 DQ57 DDRB_DQ61 9
117 118 1 237 238
DDRB_MA12 VDD_3 VDD_4 DDRB_MA11 9 DDRB_DQ58 DQ56 VSS_87 DDRB_DQS7_N
119 120 239 240
9 DDRB_MA12 DDRB_MA9 A12 A11 DDRB_MA7 DDRB_MA11 9 VSS_88 DQS7_c DDRB_DQS7_P DDRB_DQS7_N 9
121 122 @ CD70 241 242
9 DDRB_MA9 A9 A7 DDRB_MA7 9 0.1U_0402_10V7K DM7_n/DBl7_n/NC DQS7_t DDRB_DQS7_P 9
123 124 243 244
DDRB_MA8 125 VDD_5 VDD_6 126 DDRB_MA5 2 DDRB_DQ63 245 VSS_89 VSS_90 246 DDRB_DQ59
9 DDRB_MA8 DDRB_MA6 A8 A5 DDRB_MA4 DDRB_MA5 9 9 DDRB_DQ63 DQ62 DQ63 DDRB_DQ59 9
127 128 247 248
9 DDRB_MA6 A6 A4 DDRB_MA4 9 DDRB_DQ62 VSS_91 VSS_92 DDRB_DQ60
129 130 249 250
VDD_7 VDD_8 9 DDRB_DQ62 DQ58 DQ59 DDRB_DQ60 9
251 252
SMB_CLK_S3 253 VSS_93 VSS_94 254 SMB_DATA_S3
SMB_DATA_S3 20,25
RD19 1 @ 20,25 2 SMB_CLK_S3 DDRB_VDDSPD 255 SCL SDA 256 DDRB_SA0
+3VS VDDSPD SA0
ARGOS_D4AR0-26001-1P52 0_0402_5% 1 1 257 258 +0.6VS
CD53 259 VPP_1 Vtt 260 DDRB_SA1
ME@ VPP_2 SA1 1.1A
2.2U_0603_6.3V6K CD54
.1U_0402_10V6-K 261 262
2 2 GND_1 GND_2
ARGOS_D4AR0-26001-1P52
ME@
+2.5V
1A
B B
+3VS +3VS +3VS +1.2V
+VREF_DQ_DIMMB_R
1
RD28 Change RD12 to 0ohm jump

1
RD30 RD33
@ 0_0402_5% @ @ RD11
0_0402_5% 0_0402_5%
1K_0402_1%
2
DDRB_SA0 DDRB_SA1 DDRB_SA2 RD12 1 2 2_0402_5% +VREF_CA_DIMMB

1
1
2
RD31 1
RD29 RD32 CD29 RD13 CD47
@ @ 0_0402_5% @ 0.022U_0402_16V7-K 1K_0402_1% .1U_0402_10V6-K
0_0402_5% 0_0402_5%
2
2
2
1
RD14
24.9_0402_1%
CAD Note:
Trace width= 20 mil, Spcing=20 mils
2
For EMC
SPD Address 2H
A A
Issued Date 2021/04/07 Deciphered Date 2021/04/07 DDRVI SO-DIMM B
5
Vinafix.com
4 3
2
Size
C
Date:
Document Number
HY568
1
Sheet 26 of 110
Rev
0.1
5 4 3 2 1
+3VALW_SYS +3V_SPI
RB2 1 @ 2 0_0402_5%
RB1 1 @ 2 0_0201_5% SPI_CS1_N

17 PCH_SPI0_CS1_N
RB8 1 @ 2 0_0201_5% SPI_CLK DB1 2 1
17 PCH_SPI0_CLK
+3V_SPI
RB3 1 @ 2 0_0201_5% SPI_SI 2 1
D 17 PCH_SPI0_SI D
RB6 1 @ 2 0_0201_5% SPI_SO RB521CM-30T2R_VMN2M-2
17 PCH_SPI0_SO 1
NPI@
RB4 1 @ 2 0_0201_5% SPI_IO2 CB1
17,24 PCH_SPI0_IO2 0.1U_6.3V_K_X5R_0201
RB5 1 @ 2 0_0201_5% SPI_IO3 UB3 2
17 PCH_SPI0_IO3 SPI_CS1_N SPI_16M_CS1_N
0_0201_5% 1 @ 2 RB14 1 8
/CS VCC
SPI_SO 1/20W_15_5%_0201 1 2 RB15 SPI_16M_SO 2 7 SPI_16M_IO3 RB17 1 2 1/20W_15_5%_0201 SPI_IO3
DO(IO1) /HOLD(IO3)
RB13 1 @ 2 0_0201_5% SPI_CS1_N SPI_IO2 1/20W_15_5%_0201 1 2 RB16 SPI_16M_IO2 3 6 SPI_16M_CLK RB18 1 2 1/20W_15_5%_0201 SPI_CLK
27,79 EC_SPI_CS0_N /WP(IO2) CLK
RB10 1 2 1/20W_100_1%_0201 SPI_CLK 4 5 SPI_16M_SI RB19 1 2 1/20W_15_5%_0201 SPI_SI
79 EC_SPI_CLK GND DI(IO0)
79 EC_SPI_SI RB11 1 2 1/20W_100_1%_0201 SPI_SI
W25Q128JVSIQ_SO8
79 EC_SPI_SO RB12 1 2 1/20W_100_1%_0201 SPI_SO
+3V_SPI
SPI_SO RB7 1 @ 2 100K_0201_5%
C 1 C
CB3
0.1U_6.3V_K_X5R_0201
UB2 2
SPI_CS0_N 0_0201_5% 1 @ 2 RB20 SPI_8M_CS0_N 1 8
RB26 1 @ 2 0_0201_5% SPI_SO 1/20W_15_5%_0201 1 2 RB21 SPI_8M_SO 2 /CS VCC 7 SPI_8M_IO3RB22 1 2 1/20W_15_5%_0201 SPI_IO3
27,79 EC_SPI_CS0_N SPI_IO2 1 2 RB23 SPI_8M_IO2 3 IO1 IO3 6 SPI_8M_CLKRB24 1 2 1/20W_15_5%_0201 SPI_CLK
1/20W_15_5%_0201
4 IO2 CLK 5 SPI_8M_SI RB25 1 2 1/20W_15_5%_0201 SPI_SI
RB9 1 @ 2 0_0201_5% SPI_CS0_N GND IO0
17 PCH_SPI0_CS0_N
W25R64JVSSIQ_SO8
+3V_SPI
UB1 @
1 8
/CS VCC
2 7
DO(IO1) /HOLD(IO3)
3 6
/WP(IO2) CLK
4 5
GND DI(IO0)
B B
W25R256JVEIQ_WSON8_8X6
UB1 ,UB3 co-lay
A A

Common Module
Vinafix.com
B
SPI ROM/TPM 0.1

5 4 3 2 1
5 4 3 2 1
UG1A
1/17 PCI_EXPRESS +1.8VS_VGA

CORE_PLLVDD
2 x 0603 4.7uF 1 x 0603 22uF
4 x 0402 1uF 2 x 0603 10uF +0.95VGS
PEX_WAKE_N Under GPU(below 150mils)
@
TG12 1 AP11 Near GPU
PLT_RST_VGA_N
PEX_WAKE*
PEX_DVDD_1
AL27 1.6A 1 2
MAX:400mA
AN11 AL28 LG1
31 PLT_RST_VGA_N
22U_6.3V_M_X6S_0603
PEX_RST* PEX_DVDD_2 AL29 HCB1608KF-300T60_2P
10U_10V_M_X6S_0603
10U_10V_M_X6S_0603
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
22U_6.3V_M_X6S_0603
4.7U_6.3V_K_X6S_0603
4.7U_6.3V_K_X6S_0603
CLK_REQ_GPU_N AU11 PEX_DVDD_3 AM26 OPT@
1 1 1 1 1 1 1 1
4.7U_6.3V_K_X6S_0603
PEX_CLKREQ* PEX_DVDD_4 AM28
CLK_PCIE_GPU_P PEX_DVDD_5 1 1 1 30ohms (ESR=0.01) Bead
AR12 AM29
19 CLK_PCIE_GPU_P CLK_PCIE_GPU_N AT12 PEX_REFCLK PEX_DVDD_6 AM30 P/N;SM01000M300 Place near GPU
OPT@
OPT@
OPT@
OPT@
OPT@
19 CLK_PCIE_GPU_N PEX_REFCLK* PEX_DVDD_7 2 2 2 2 2 2 N18 change 2 2
AN29
OPT@
OPT@
OPT@
PEG_CRX_GTX0_P 1 2 0.22U_6.3V_K_X5R_0201 OPT@ PEG_CRX_C_GTX0_P AN13 PEX_DVDD_8 AN30 2 2 2
OPT@
OPT@
OPT@
CG8
CG548
CG549
CG11
CG1716
CG1717
CG1718
CG1719
7 PEG_CRX_GTX0_P PEX_TX0 PEX_DVDD_9
CG1977
D PEG_CRX_GTX0_N D
CG9 1 2 0.22U_6.3V_K_X5R_0201 OPT@ PEG_CRX_C_GTX0_N AP13 AP30
CG1639
CG1640
CG1965
7 PEG_CRX_GTX0_N PEX_TX0* PEX_DVDD_10 AR30
PEG_CTX_C_GRX0_P AV13 PEX_DVDD_11 AT30
7 PEG_CTX_C_GRX0_P PEG_CTX_C_GRX0_N PEX_RX0 PEX_DVDD_12
7 PEG_CTX_C_GRX0_N AW13 AU30
PEX_RX0* PEX_DVDD_13 AV30
PEG_CRX_GTX1_P CG13 1 2 0.22U_6.3V_K_X5R_0201 OPT@ PEG_CRX_C_GTX1_P AR14 PEX_DVDD_14 AW30
7 PEG_CRX_GTX1_P PEG_CRX_GTX1_N PEX_TX1 PEX_DVDD_15
7 PEG_CRX_GTX1_N CG15 1 2 0.22U_6.3V_K_X5R_0201 OPT@ PEG_CRX_C_GTX1_N AT14 AY30
PEX_TX1* PEX_DVDD_16
PEG_CTX_C_GRX1_P AW14
7 PEG_CTX_C_GRX1_P PEG_CTX_C_GRX1_N PEX_RX1
7 PEG_CTX_C_GRX1_N AY14
PEX_RX1*
PEG_CRX_GTX2_P CG18 1 2 0.22U_6.3V_K_X5R_0201 OPT@ PEG_CRX_C_GTX2_P AN15
7 PEG_CRX_GTX2_P PEG_CRX_GTX2_N PEX_TX2
7 PEG_CRX_GTX2_N CG19 1 2 0.22U_6.3V_K_X5R_0201 OPT@ PEG_CRX_C_GTX2_N AP15 +3VS
PEX_TX2*
PEG_CTX_C_GRX2_P AV15
7 PEG_CTX_C_GRX2_P PEX_RX2
1
PEG_CTX_C_GRX2_N AW15
7 PEG_CTX_C_GRX2_N PEX_RX2* RG1343
OPT@
PEG_CRX_GTX3_P CG20 1 2 0.22U_6.3V_K_X5R_0201 OPT@ PEG_CRX_C_GTX3_P AR16 AL24 +1.8VS_VGA 10K_0402_5%
7 PEG_CRX_GTX3_P
7 PEG_CRX_GTX3_N
PEG_CRX_GTX3_N CG21 1 2 0.22U_6.3V_K_X5R_0201 OPT@ PEG_CRX_C_GTX3_N AT16 PEX_TX3
PEX_TX3*
PEX_CVDD_1 AL25
PEX_CVDD_2 AL26 Under GPU 2 x 0603 4.7uF
3 x 0402 1uF
Near GPU 1 x 0603 22uF
2 x 0603 10uF
1.7A
FS_OVERT# FUNCTION
2
PEG_CTX_C_GRX3_P AW16 PEX_CVDD_3 AM24 RG1207
7 PEG_CTX_C_GRX3_P PEG_CTX_C_GRX3_N PEX_RX3 PEX_CVDD_4 OVERT_R_N 1
31For OVERT Enable
AY16 @ 2 0_0402_5%
10U_10V_M_X6S_0603
10U_10V_M_X6S_0603
7 PEG_CTX_C_GRX3_N
22U_6.3V_M_X6S_0603
PEX_RX3* +3VS OVERT_N_NVEN
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
PEG_CRX_GTX4_P CG22 1 2 0.22U_6.3V_K_X5R_0201 OPT@ PEG_CRX_C_GTX4_P AN17 AL17
7 PEG_CRX_GTX4_P 1 1 1 1 1 1
4.7U_6.3V_K_X6S_0603
4.7U_6.3V_K_X6S_0603
PEG_CRX_GTX4_N CG23 1 2 0.22U_6.3V_K_X5R_0201 OPT@ PEG_CRX_C_GTX4_N AP17 PEX_TX4 PEX_HVDD_1 AL18
7 PEG_CRX_GTX4_N PEX_TX4* PEX_HVDD_2 1 1
AL19 1 2 For SWG mode
OPT@
OPT@
PEX_HVDD_3 WRST_N_EC 79
1
PEG_CTX_C_GRX4_P AV17 AL20 RG20
OPT@
OPT@
OPT@
OPT@
7 PEG_CTX_C_GRX4_P PEG_CTX_C_GRX4_N PEX_RX4 PEX_HVDD_4 2 2 2 2 2 2
AW17 AL21 RG2 0_0402_5%
OPT@
OPT@
OPT@
7 PEG_CTX_C_GRX4_N PEX_RX4* PEX_HVDD_5 2 2
@
AL22 10K_0402_5%
OPT@
CG1979
CG1980
CG1981
CG1642
CG1643
CG1963
PEG_CRX_GTX5_P CG24 1 2 0.22U_6.3V_K_X5R_0201 OPT@ PEG_CRX_C_GTX5_P AR18 PEX_HVDD_6 AL23
CG532
CG1381
7 PEG_CRX_GTX5_P PEX_TX5 PEX_HVDD_7
3
PEG_CRX_GTX5_N CG25 1 2 0.22U_6.3V_K_X5R_0201 OPT@ PEG_CRX_C_GTX5_N AT18 AM16 D
7 PEG_CRX_GTX5_N
2
PEX_TX5* PEX_HVDD_8 AM18 OVERT_R 5 QG1B
PEG_CTX_C_GRX5_P AW18 PEX_HVDD_9 AM20 LBSS138DW1T1G_SOT363-6
7 PEG_CTX_C_GRX5_P G
PEG_CTX_C_GRX5_N AY18 PEX_RX5 PEX_HVDD_10
OPT@
7 PEG_CTX_C_GRX5_N S
4
PEX_RX5* +1.8VS_VGA
6
PEG_CRX_GTX6_P CG26 1 2 0.22U_6.3V_K_X5R_0201 OPT@ PEG_CRX_C_GTX6_P AN19 D
7 PEG_CRX_GTX6_P PEG_CRX_GTX6_N PEX_TX6
7 PEG_CRX_GTX6_N CG30 1 2 0.22U_6.3V_K_X5R_0201 OPT@ PEG_CRX_C_GTX6_N AP19 AM22 PEX_PLL_HVDD RG7 1 @ 2 0_0402_5%
31 OVERT_N
OVERT_N 2 QG1A
PEX_TX6* PEX_PLL_HVDD LBSS138DW1T1G_SOT363-6 OVERT_RR_N
C G C
PEG_CTX_C_GRX6_P AV19 S
7 PEG_CTX_C_GRX6_P 1
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1
PEG_CTX_C_GRX6_N AW19 PEX_RX6
7 PEG_CTX_C_GRX6_N PEX_RX6* Near GPU 1
OPT@
PEG_CRX_GTX7_P CG31 1 2 0.22U_6.3V_K_X5R_0201 OPT@ PEG_CRX_C_GTX7_P AR20
OPT@
7 PEG_CRX_GTX7_P PEX_TX7
1
PEG_CRX_GTX7_N CG32 1 2 0.22U_6.3V_K_X5R_0201 OPT@ PEG_CRX_C_GTX7_N AT20 2 D
OPT@
7 PEG_CRX_GTX7_N PEX_TX7* PLT_RST_VGA_N PLT_RST_VGA_R_N 2
1 @ 2 2 QG2
CG1985
PEG_CTX_C_GRX7_P AW20 RG3 G LBSS139WT1G_SC70-3
CG2126
7 PEG_CTX_C_GRX7_P PEG_CTX_C_GRX7_N PEX_RX7
7 PEG_CTX_C_GRX7_N AY20 0_0402_5% S
3
PEX_RX7*
1U_6.3V_K_X6S_0402
1
@
2
CG2125
CORE_PLLVDD
UG1Q
11/17 XTAL_PLL
Place Under GPU(1 CAP per pin) +1.8VS_AON
CORE_PLLVDD AJ9
AM9 CORE_PLL_AVDD
AK9 GPCADC_AVDD
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
SP_PLLVDD
1 1 1 1
1
+1.8VS_VGA AJ10
VID_PLLVDD RG1339
100K_0402_1%
OPT@
OPT@
OPT@
OPT@
2
2 2 2 2 @
RG1243 RG29
CG1986
CG1987
CG1988
CG1989
2
1/16W_5.6K_1%_0402 10K_0402_5% Voltage SmartFan PWM %
B B
@
OPT@ XTALSSIN L4 L3 XTALOUT 0 V GPIO DISABLED

EXT_REFCLK_FL XTAL_OUTBUFF 0.9 V 33% PWM
1
VGA_PWRGD_R
@
1 2 1.8 V 66% PWM

20,31 VGA_PWRGD +1.8VS_AON
1 L2 L1
XTAL_IN XTAL_OUT
1
RG8
10K_0402_1%
0_0402_5% CG66 @ GN20-P-FCBGA1358_BGA1358 RG111
10K_0402_5%
2
1
0.1U_10V_K_X5R_0402 100K_0402_1%
RG1335
2
@
@ RG209 OPT@
10K_0402_1%
2 OPT@ 1
1 2
OPT@
RG31
2
2
10M_0402_5%
RG1337
OPT@
1
XTALSSIN_RC 2
1 3 CLK_REQ_GPU_N TG13 YG1
20 GPU_CLKREQ_N PEX_CVDD_SENSE
AU29 1
PEX_CVDD_SENSE XTAL_IN 1 4
QG5 OSC1 GND2
@
LSI1012XT1G_SC-89-3 2 3 XTAL_OUT
18P_0402_50V8J
OPT@ AW29 PEX_TERMP 1 2 GND1 OSC2
PEX_TERMP 1 1 1
@
Vgs(th)≤0.9V CG263
CG1540
RG34 CG262 27MHZ_10PF_7V27000050 8P_0402_50V8J
2.49K_0402_1% 8P_0402_50V8J OPT@
OPT@ 2 2 OPT@ 2 OPT@
@ GN20-P-FCBGA1358_BGA1358
A A

Issued Date 2021/04/07 2021/04/07 N18P_(1/6):PEG I/F
Vinafix.com
Deciphered Date
Custom
HY568 0.1

5 4 3 2 1
5 4 3 2 1
UG1L
5/17 IFPAB
Type-C DP UG1M
DVI DP
6/17 IFPC
SL/DL OPT@
TXC/TXC
AV1 GPU_IFPA_TX3_N RG73 2 1 1K_0402_1% IFPCD_RSET AN7
IFPA_L3* GPU_IFPA_TX3_N 12 IFPCD_RSET
OPT@ TXC/TXC
AV2 GPU_IFPA_TX3_P
IFPAB_RSET IFPA_L3 GPU_IFPA_TX3_P 12
RG68 2 1 1K_0402_1% AP9 HDMI DP
IFPAB_RSET
TXD0/0
AW3 GPU_IFPA_TX2_N AK4 For HDMI
IFPA_L2* GPU_IFPA_TX2_N 12 IFPC_AUX_SDA* HDMI1_DAT 50
CORE_PLLVDD
TXD0/0
AY3 GPU_IFPA_TX2_P AJ4
IFPA_L2 GPU_IFPA_TX2_P 12 CORE_PLLVDD IFPC_AUX_SCL HDMI1_CLK 50
RG69 1 @ 2 0_0402_5% +IFPAB_PLLVDD AN9
IFPAB_PLLVDD AV5 GPU_IFPA_TX1_N AM6 GPU_HDMI_CLK_N
TXD1/1 GPU_IFPA_TX1_N 12 TXC GPU_HDMI_CLK_N 50
D IFPA_L1* AW5 GPU_IFPA_TX1_P RG1327 1 @ 2 0_0402_5% +IFPCD_PLLVDD AN8 IFPC_L3* AM5 GPU_HDMI_CLK_P D
TXD1/1 IFPA_L1 GPU_IFPA_TX1_P 12 IFPCD_PLLVDD TXC IFPC_L3 GPU_HDMI_CLK_P 50 HDMI CLK
1U_6.3V_M_X6S_0201
1
1U_6.3V_M_X6S_0201
AN5 GPU_HDMI_TX0_N
OPT@
1 TXD0 IFPC_L2* GPU_HDMI_TX0_N 50
AY5 GPU_IFPA_TX0_N AN6 GPU_HDMI_TX0_P
OPT@
TXD2/2 IFPA_L0* GPU_IFPA_TX0_N 12 TXD0
IFPC_L2 GPU_HDMI_TX0_P 50 HDMI D0
TXD2/2
AY6 GPU_IFPA_TX0_P
2 IFPA_L0 GPU_IFPA_TX0_P 12
2
IFPC TXD1 IFPC_L1*
AR6 GPU_HDMI_TX1_N
GPU_HDMI_TX1_P GPU_HDMI_TX1_N 50
AR5 HDMI D1
CG1990
TXD1 IFPC_L1 GPU_HDMI_TX1_P 50
AJ6 GPU_IFPA_AUXN
CG1998
IFPA_AUX_SDA* GPU_IFPA_AUXN 12
AK6 GPU_IFPA_AUXP TXD2 AT5 GPU_HDMI_TX2_N
IFPA_AUX_SCL GPU_IFPA_AUXP 12 IFPC_L0* GPU_HDMI_TX2_P GPU_HDMI_TX2_N 50
TXD2 AT6 HDMI D2
IFPC_L0 GPU_HDMI_TX2_P 50
IFPAB
under GPU TXC
AW9 GPU_IFPB_TX3_N
IFPB_L3* GPU_IFPB_TX3_N 12
TXC
AV9 GPU_IFPB_TX3_P
IFPB_L3 GPU_IFPB_TX3_P 12 +0.95VGS under GPU
TXD0/3
AV8 GPU_IFPB_TX2_N RG1328 1 @ 2 0_0402_5% +IFPCD_IOVDD AL13
IFPB_L2* GPU_IFPB_TX2_N 12 IFP_IOVDD_3
TXD0/3
AW8 GPU_IFPB_TX2_P AL14
IFPB_L2 GPU_IFPB_TX2_P 12 IFP_IOVDD_4
1U_6.3V_M_X6S_0201
1U_6.3V_M_X6S_0201
1U_6.3V_M_X6S_0201
AW6 GPU_IFPB_TX1_N
4.7U_6.3V_K_X6S_0603
TXD1/4 1 1 1 1 @ GN20-P-FCBGA1358_BGA1358
IFPB_L1* GPU_IFPB_TX1_N 12
AV6 GPU_IFPB_TX1_P
OPT@
OPT@
OPT@
TXD1/4 IFPB_L1 GPU_IFPB_TX1_P 12
OPT@
AY8 GPU_IFPB_TX0_N 2 2 2 2
TXD2/5 IFPB_L0* GPU_IFPB_TX0_N 12
AY9 GPU_IFPB_TX0_P
CG227
CG1999
CG2000
CG2001
TXD2/5 GPU_IFPB_TX0_P 12
+0.95VGS IFPB_L0
AK7 GPU_IFPB_AUXN
+IFPAB_IOVDD IFPB_AUX_SDA* GPU_IFPB_AUXN 12
RG72 1 @ 2 0_0402_5% AL15 AJ7 GPU_IFPB_AUXP
IFP_IOVDD_5 IFPB_AUX_SCL GPU_IFPB_AUXP 12
AL16
AM11 IFP_IOVDD_6
IFP_IOVDD_7
1U_6.3V_M_X6S_0201
1U_6.3V_M_X6S_0201
1U_6.3V_M_X6S_0201
1 1 1 1 AM12 near GPU

IFP_IOVDD_8
4.7U_6.3V_K_X6S_0603
under GPU
OPT@
OPT@
OPT@
OPT@
2 2 2 2
CG1991
CG1992
CG1993
CG445
C GPU_IFPA_AUXN RG15 1 OPT@ 2 100K_0201_5% C

GPU_IFPA_AUXP RG1292 1 OPT@ 2 100K_0201_5%
GPU_IFPB_AUXN RG232 1 OPT@ 2 100K_0201_5%

GPU_IFPB_AUXP RG233 1 OPT@ 2 100K_0201_5%
near GPU under GPU
1.If an IFP link is unused, The main and AUX links,

IFPxy_RSET can be left unconnected,and IFPxy_PLLVDD
should be 10K PD to GND.
UG1N
7/17 IFPD 2.IFP_IOVDD rail can be left unconnected if no IFP link is

used. If any IFP is used, all IFP_IOVDD balls must be
connected to power rail.
HDMI DP UG1O
AJ5 GPU_EDP_AUXN 8/17 IFPE

IFPD_AUX_SDA* GPU_EDP_AUXN 45
AK5 GPU_EDP_AUXP @
IFPD_AUX_SCL GPU_EDP_AUXP 45 IFPE_RSET
2 1 AM7
RG1140 1K_0402_1% IFPE_RSET
TXC
AN2 GPU_EDP_TX3_N HDMI DP
IFPD TXC
IFPD_L3*
IFPD_L3
AN3 GPU_EDP_TX3_P
GPU_EDP_TX3_N
GPU_EDP_TX3_P
45
45
CORE_PLLVDD
AJ8
AR3 GPU_EDP_TX2_N RG1124 1 @ 2 0_0402_5% +IFPE_PLLVDD AM8 IFPE_AUX_SDA* AK8
TXD0 IFPD_L2* GPU_EDP_TX2_N 45 IFPE_PLLVDD IFPE_AUX_SCL
AR2 GPU_EDP_TX2_P
TXD0 IFPD_L2 GPU_EDP_TX2_P 45
TXD1
AR1 GPU_EDP_TX1_N AJ1
IFPD_L1* GPU_EDP_TX1_N 45 TXC IFPE_L3*
1 GN20@ 2
1U_6.3V_M_X6S_0201
TXD1 AT1 GPU_EDP_TX1_P 1 AJ2
10K_0201_5%
IFPD_L1 GPU_EDP_TX1_P 45 TXC IFPE_L3
RG1344
AT2 GPU_EDP_TX0_N AK1
*
TXD2 GPU_EDP_TX0_N 45 TXD0
IFPD_L0* AT3 GPU_EDP_TX0_P IFPE_L2* AK2
TXD2 GPU_EDP_TX0_P 45 TXD0
B IFPD_L0 2 IFPE_L2 B
AM3
CG1997
TXD1 IFPE_L1*
TXD1
AM2
+IFPCD_IOVDD AM14 IFPE_L1
AN12 IFP_IOVDD_9 AM1
TXD2
IFP_IOVDD_10 IFPE_L0* AN1
TXD2 IFPE_L0
+0.95VGS
1U_6.3V_M_X6S_0201
1U_6.3V_M_X6S_0201
1 1 @ GN20-P-FCBGA1358_BGA1358 under GPU

OPT@
OPT@
RG337 1 @ 2 0_0402_5% +IFPE_IOVDD AL11

GPU_EDP_AUXN RG1293 1 OPT@ 2 100K_0201_5% AL12 IFP_IOVDD_1
2 2 GPU_EDP_AUXP RG1294 1 OPT@ 2 100K_0201_5% IFP_IOVDD_2
CG2002
CG2003
1U_6.3V_M_X6S_0201
1 1 1 1
1U_6.3V_M_X6S_0201
1U_6.3V_M_X6S_0201
OPT@
OPT@
OPT@
4.7U_6.3V_K_X6S_0603
OPT@
2 2 2 2
under GPU
CG1994
CG460
CG1995
CG1996
near GPU under GPU
A A

Issued Date 2021/04/07 Deciphered Date 2021/04/07 N18P_(3/6):VRAM I/F
Custom
HY568 0.1

5 4 3 2 1
Vinafix.com
5 4 3 2 1
UG1C
UG1B
3/17 FBB
2/17 FBA
38,39 FBB_D[0..63]
+FB_PLLAVDD
36,37 FBA_D[0..63] FBB_D21 F1
FBA_D20 C39 K28 FBB_D19 F2 FBB_D0
FBA_D21 C40 FBA_D0 FB_PLLVDD_2 FBB_D17 E1 FBB_D1
FBA_D18 E37 FBA_D1 FBB_D18 D2 FBB_D2
1U_6.3V_K_X6S_0402
FBA_D17 FBA_D2 1 GA1XX GDDR6 CMD Mapping FBB_D22 FBB_D3
D40 B4
FBA_D23 G39 FBA_D3 Lower 0..31 Upper 32..63 FBB_D23 A3 FBB_D4
FBA_D22 H40 FBA_D4 FBB_D20 C5 FBB_D5
OPT@
DRAM1 DRAM2
FBA_D19 J38 FBA_D5 2 CHA-Byte 0,1 CHA-Byte 4,5 FBB_D16 A5 FBB_D6
FBA_D16 J40 FBA_D6 FBB_D11 G2 FBB_D7
CG2122
FBA_D8 E38 FBA_D7 CA0_A CMD1 CMD33 FBB_D8 J4 FBB_D8
Under GPU
FBA_D12 F37 FBA_D8 CA1_A CMD13 CMD45 FBB_D15 H1 FBB_D9
FBA_D11 J34 FBA_D9 CA2_A CMD12 CMD35 FBB_D13 J2 FBB_D10
D FBA_D15 E36 FBA_D10 CA3_A CMD24 CMD46 FBB_D14 J6 FBB_D11 D
FBA_D9 J36 FBA_D11 CA4_A CMD11 CMD36 FBB_D9 D4 FBB_D12
FBA_D10 FBA_D12 FBB_D10 FBB_D13 FBB_CMD[0..24] 38
L35 CA5_A CMD15 CMD43 F5
FBA_D14 FBA_D13 FBA_CMD[0..24] 36 FBB_D12 FBB_D14 FBB_CMD0
K37 CA6_A CMD22 CMD48 H7 D14
FBA_D13 N33 FBA_D14 Y36 FBA_CMD0 CA7_A CMD23 CMD47 FBB_D30 D12 FBB_D15 FBB_CMD0 A17 FBB_CMD1
FBA_D24 U38 FBA_D15 FBA_CMD0 AA39 FBA_CMD1 CA8_A CMD0 CMD34 FBB_D25 A12 FBB_D16 FBB_CMD1 J15 FBB_CMD2
FBA_D31 U40 FBA_D16 FBA_CMD1 AA32 FBA_CMD2 CA9_A CMD2 CMD32 FBB_D29 B12 FBB_D17 FBB_CMD2 E17 FBB_CMD3
FBA_D27 T39 FBA_D17 FBA_CMD2 AC34 FBA_CMD3 CABI_A CMD10 CMD37 FBB_D27 A11 FBB_D18 FBB_CMD3 H15 FBB_CMD4
FBA_D26 R38 FBA_D18 FBA_CMD3 AA33 FBA_CMD4 CKE_A CMD14 CMD44 FBB_D31 A8 FBB_D19 FBB_CMD4 D17 FBB_CMD5
FBA_D30 M40 FBA_D19 FBA_CMD4 Y37 FBA_CMD5 FBB_D26 C8 FBB_D20 FBB_CMD5 E14 FBB_CMD6
FBA_D29 L40 FBA_D20 FBA_CMD5 Y35 FBA_CMD6 CHB-Byte 2,3 CHB-Byte 6,7 FBB_D28 B7 FBB_D21 FBB_CMD6 G15 FBB_CMD7
FBA_D28 L38 FBA_D21 FBA_CMD6 AA35 FBA_CMD7 CA0_B CMD5 CMD29 FBB_D24 A6 FBB_D22 FBB_CMD7 A15 FBB_CMD8
FBA_D25 K39 FBA_D22 FBA_CMD7 Y39 FBA_CMD8 CA1_B CMD18 CMD52 FBB_D6 H10 FBB_D23 FBB_CMD8 B14 FBB_CMD9
FBA_D2 P34 FBA_D23 FBA_CMD8 V40 FBA_CMD9 CA2_B CMD7 CMD40 FBB_D1 H12 FBB_D24 FBB_CMD9 B15 FBB_CMD10
FBA_D5 U33 FBA_D24 FBA_CMD9 Y40 FBA_CMD10 CA3_B CMD20 CMD50 FBB_D4 G11 FBB_D25 FBB_CMD10 A14 FBB_CMD11
FBA_D6 U35 FBA_D25 FBA_CMD10 Y38 FBA_CMD11 CA4_B CMD8 CMD39 FBB_D3 E11 FBB_D26 FBB_CMD11 F17 FBB_CMD12
FBA_D7 U37 FBA_D26 FBA_CMD11 W37 FBA_CMD12 CA5_B CMD16 CMD42 FBB_D2 J8 FBB_D27 FBB_CMD12 B17 FBB_CMD13
FBA_D3 N37 FBA_D27 FBA_CMD12 AA40 FBA_CMD13 CA6_B CMD21 CMD49 FBB_D0 G9 FBB_D28 FBB_CMD13 D15 FBB_CMD14
FBA_D4 R32 FBA_D28 FBA_CMD13 AA38 FBA_CMD14 CA7_B CMD19 CMD51 FBB_D7 E6 FBB_D29 FBB_CMD14 C15 FBB_CMD15
FBA_D0 N35 FBA_D29 FBA_CMD14 V38 FBA_CMD15 CA8_B CMD6 CMD28 FBB_D5 F7 FBB_D30 FBB_CMD15 C14 FBB_CMD16
FBA_D1 M38 FBA_D30 FBA_CMD15 V39 FBA_CMD16 CA9_B CMD4 CMD30 FBB_D49 B39 FBB_D31 FBB_CMD16 E15 FBB_CMD17
FBA_D52 AY35 FBA_D31 FBA_CMD16 AA37 FBA_CMD17 CABI_B CMD9 CMD38 FBB_D54 B38 FBB_D32 FBB_CMD17 C17 FBB_CMD18
FBA_D49 AW35 FBA_D32 FBA_CMD17 AC38 FBA_CMD18 CKE_B CMD17 CMD41 FBB_D52 A38 FBB_D33 FBB_CMD18 J17 FBB_CMD19
FBA_D48 AY36 FBA_D33 FBA_CMD18 AC33 FBA_CMD19 FBB_D50 B37 FBB_D34 FBB_CMD19 D18 FBB_CMD20
FBA_D50 AW37 FBA_D34 FBA_CMD19 AC36 FBA_CMD20 RESET* CMD3 CMD31 FBB_D51 B34 FBB_D35 FBB_CMD20 J14 FBB_CMD21
FBA_D51 AU39 FBA_D35 FBA_CMD20 Y33 FBA_CMD21 FBB_D48 A33 FBB_D36 FBB_CMD21 H14 FBB_CMD22
FBA_D55 AV40 FBA_D36 FBA_CMD21 Y32 FBA_CMD22 FBB_D55 C32 FBB_D37 FBB_CMD22 H17 FBB_CMD23
FBA_D53 AT38 FBA_D37 FBA_CMD22 AC32 FBA_CMD23 FBB_D53 A32 FBB_D38 FBB_CMD23 A18 FBB_CMD24
FBA_D54 AT40 FBA_D38 FBA_CMD23 AC39 FBA_CMD24 FBB_D45 C36 FBB_D39 FBB_CMD24 F13
FBA_D47 AW32 FBA_D39 FBA_CMD24 V34 FBB_D40 D35 FBB_D40 FBB_CMD25_NC G14
FBA_D46 AU32 FBA_D40 FBA_CMD25_NC V36 FBB_D46 D37 FBB_D41 FBB_CMD26_NC H13 FBB_DEBUG0
FBA_D44 FBA_D41 FBA_CMD26_NC FBA_DEBUG0 FBB_D43 FBB_D42 FBB_CMD27 FBB_CMD28 FBB_CMD[28..52] 39
AY33 V32 G32 E18
FBA_D40 FBA_D42 FBA_CMD27 FBA_CMD28 FBA_CMD[28..52] 37 FBB_D41 FBB_D43 FBB_CMD28 FBB_CMD29
AW34 AD35 E32 A23
FBA_D43 AU37 FBA_D43 FBA_CMD28 AG38 FBA_CMD29 FBB_D42 F30 FBB_D44 FBB_CMD29 J18 FBB_CMD30
FBA_D45 AR32 FBA_D44 FBA_CMD29 AD32 FBA_CMD30 FBB_D47 D31 FBB_D45 FBB_CMD30 F20 FBB_CMD31
FBA_D42 AT35 FBA_D45 FBA_CMD30 AG37 FBA_CMD31 FBB_D44 H28 FBB_D46 FBB_CMD31 H18 FBB_CMD32
FBA_D41 AP33 FBA_D46 FBA_CMD31 AD33 FBA_CMD32 FBVDDQ FBVDDQ FBB_D59 C24 FBB_D47 FBB_CMD32 B20 FBB_CMD33
FBA_D60 AJ37 FBA_D47 FBA_CMD32 AD37 FBA_CMD33 FBB_D60 A24 FBB_D48 FBB_CMD33 G18 FBB_CMD34
Foe Partition A CMD Return Path Foe Partition B CMD Return Path
FBA_D61 AJ40 FBA_D48 FBA_CMD33 AD36 FBA_CMD34 FBB_D56 B25 FBB_D49 FBB_CMD34 D22 FBB_CMD35
C
FBA_D57 AJ39 FBA_D49 FBA_CMD34 AC37 FBA_CMD35 FBB_D57 C26 FBB_D50 FBB_CMD35 A20 FBB_CMD36 C
FBA_D59 AK40 FBA_D50 FBA_CMD35 AD40 FBA_CMD36 FBB_D62 A29 FBB_D51 FBB_CMD36 E21 FBB_CMD37
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
FBA_D63 AN40 FBA_D51 FBA_CMD36 AG33 FBA_CMD37 FBB_D58 A30 FBB_D52 FBB_CMD37 F21 FBB_CMD38
FBA_D62 FBA_D52 FBA_CMD37 FBA_CMD38 1 1 1 1 1 1 1 1 FBB_D61 FBB_D53 FBB_CMD38 FBB_CMD39
AN38 AF33 C30 A21
FBA_D58 AP39 FBA_D53 FBA_CMD38 AC40 FBA_CMD39 FBB_D63 B31 FBB_D54 FBB_CMD39 D21 FBB_CMD40
FBA_D56 FBA_D54 FBA_CMD39 FBA_CMD40 FBB_D36 FBB_D55 FBB_CMD40 FBB_CMD41
@
AR40 AF34 G27 B23
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
FBA_D37 AL33 FBA_D55 FBA_CMD40 AG39 FBA_CMD41 2 2 2 2 2 2 2 2 FBB_D37 H24 FBB_D56 FBB_CMD41 C21 FBB_CMD42
FBA_D36 AJ33 FBA_D56 FBA_CMD41 AF38 FBA_CMD42 FBB_D38 F24 FBB_D57 FBB_CMD42 C20 FBB_CMD43
CG2137
CG2138
CG2139
CG2140
CG2141
CG2142
CG2143
CG2144
FBA_D38 AK34 FBA_D57 FBA_CMD42 AF37 FBA_CMD43 FBB_D34 D24 FBB_D58 FBB_CMD43 C23 FBB_CMD44
FBA_D39 AK36 FBA_D58 FBA_CMD43 AG40 FBA_CMD44 FBB_D32 D28 FBB_D59 FBB_CMD44 C18 FBB_CMD45
FBA_D32 AN32 FBA_D59 FBA_CMD44 AD38 FBA_CMD45 FBB_D35 J26 FBB_D60 FBB_CMD45 B18 FBB_CMD46
FBA_D35 AM34 FBA_D60 FBA_CMD45 AF39 FBA_CMD46 FBB_D33 F28 FBB_D61 FBB_CMD46 H20 FBB_CMD47
FBA_D33 AP35 FBA_D61 FBA_CMD46 AF36 FBA_CMD47 FBB_D39 C29 FBB_D62 FBB_CMD47 J20 FBB_CMD48
FBA_D34 AR36 FBA_D62 FBA_CMD47 AF32 FBA_CMD48 FBB_D63 FBB_CMD48 J21 FBB_CMD49
FBA_D63 FBA_CMD48 AG32 FBA_CMD49 FBB_CMD49 B21 FBB_CMD50
FBA_CMD49 AF40 FBA_CMD50 FBB_DBI2_N C3 FBB_CMD50 H21 FBB_CMD51
FBA_DBI2_N F38 FBA_CMD50 AG36 FBA_CMD51 38 FBB_DBI2_N FBB_DBI1_N G4 FBB_DQM0 FBB_CMD51 D20 FBB_CMD52
36 FBA_DBI2_N FBA_DBI1_N L33 FBA_DQM0 FBA_CMD51 AD39 FBA_CMD52 38 FBB_DBI1_N FBB_DBI3_N B10 FBB_DQM1 FBB_CMD52 G23 FBB_DEBUG0 1 @ 2
36 FBA_DBI1_N FBA_DBI3_N FBA_DQM1 FBA_CMD52 38 FBB_DBI3_N FBB_DBI0_N FBB_DQM2 FBB_CMD53_NC FBVDDQ
P40 AH35 F10 E23 RG121
36 FBA_DBI3_N FBA_DBI0_N R35 FBA_DQM2 FBA_CMD53_NC AG34 38 FBB_DBI0_N FBB_DBI6_N C35 FBB_DQM3 FBB_CMD54_NC J23 FBB_DEBUG1 60.4_0402_1%
36 FBA_DBI0_N FBA_DBI6_N AV38 FBA_DQM3 FBA_CMD54_NC AH33 FBA_DEBUG1 FBA_DEBUG0 1 @ 2 39 FBB_DBI6_N FBB_DBI5_N H30 FBB_DQM4 FBB_CMD55 FBB_DEBUG1 1 @ 2
37 FBA_DBI6_N FBA_DBI5_N FBA_DQM4 FBA_CMD55 FBVDDQ 39 FBB_DBI5_N FBB_DBI7_N FBB_DQM5
AU34 RG119 A27 RG122
37 FBA_DBI5_N FBA_DBI7_N AL39 FBA_DQM5 60.4_0402_1% 39 FBB_DBI7_N FBB_DBI4_N F26 FBB_DQM6 60.4_0402_1%
37 FBA_DBI7_N FBA_DBI4_N AL35 FBA_DQM6 FBA_DEBUG1 1 @ 2 39 FBB_DBI4_N FBB_DQM7
37 FBA_DBI4_N FBA_DQM7 RG120
60.4_0402_1% FBB_EDC2 C1
FBA_EDC2 F40 38 FBB_EDC2 FBB_EDC1 H3 FBB_DQS_WP0
36 FBA_EDC2 FBA_EDC1 H35 FBA_DQS_WP0 38 FBB_EDC1 FBB_EDC3 C11 FBB_DQS_WP1 D6 FBB_CLK0_P
36 FBA_EDC1 FBA_EDC3 R40 FBA_DQS_WP1 L37 FBA_CLK0_P 38 FBB_EDC3 FBB_EDC0 D10 FBB_DQS_WP2 FBB_CLK0 C6 FBB_CLK0_N FBB_CLK0_P 38
36 FBA_EDC3 FBA_EDC0 R37 FBA_DQS_WP2 FBA_CLK0 M37 FBA_CLK0_N FBA_CLK0_P 36 38 FBB_EDC0 FBB_EDC6 A35 FBB_DQS_WP3 FBB_CLK0* D29 FBB_CLK1_P FBB_CLK0_N 38
36 FBA_EDC0 FBA_EDC6 AY38 FBA_DQS_WP3 FBA_CLK0* AR38 FBA_CLK1_P FBA_CLK0_N 36 39 FBB_EDC6 FBB_EDC5 F33 FBB_DQS_WP4 FBB_CLK1 D30 FBB_CLK1_N FBB_CLK1_P 39
37 FBA_EDC6 FBA_EDC5 AV33 FBA_DQS_WP4 FBA_CLK1 AR37 FBA_CLK1_N FBA_CLK1_P 37 39 FBB_EDC5 FBB_EDC7 A26 FBB_DQS_WP5 FBB_CLK1* FBB_CLK1_N 39
37 FBA_EDC5 FBA_EDC7 AK38 FBA_DQS_WP5 FBA_CLK1* FBA_CLK1_N 37 39 FBB_EDC7 FBB_EDC4 D26 FBB_DQS_WP6
37 FBA_EDC7 FBA_EDC4 AL37 FBA_DQS_WP6 39 FBB_EDC4 FBB_DQS_WP7
37 FBA_EDC4 FBA_DQS_WP7
B2 FBB_WCK23_P
E39 FBA_WCK23_P FBB_WCK01 B3 FBB_WCK23_N FBB_WCK23_P 38
FBA_WCK01 E40 FBA_WCK23_N FBA_WCK23_P 36 FBB_WCK01* A9 FBB_WCKB23_P FBB_WCK23_N 38
FBA_WCK01* N40 FBA_WCKB23_P FBA_WCK23_N 36 FBB_WCK23 B9 FBB_WCKB23_N FBB_WCKB23_P 38
FBA_WCK23 N39 FBA_WCKB23_N FBA_WCKB23_P 36 FBB_WCK23* B36 FBB_WCK67_P FBB_WCKB23_N 38
B FBA_WCK23* AW39 FBA_WCK67_P FBA_WCKB23_N 36 FBB_WCK45 A36 FBB_WCK67_N FBB_WCK67_P 39 B
FBA_WCK45 AV39 FBA_WCK67_N FBA_WCK67_P 37 FBB_WCK45* A28 FBB_WCKB67_P FBB_WCK67_N 39
FBA_WCK45* AM40 FBA_WCKB67_P FBA_WCK67_N 37 FBB_WCK67 B28 FBB_WCKB67_N FBB_WCKB67_P 39
FBA_WCK67 AM39 FBA_WCKB67_N FBA_WCKB67_P 37 FBB_WCK67* FBB_WCKB67_N 39
FBA_WCK67* FBA_WCKB67_N 37 F3 FBB_WCKB01_P
H37 FBA_WCKB01_P FBVDDQ FBB_WCKB01 E3 FBB_WCKB01_N FBB_WCKB01_P 38
FBA_WCKB01 H38 FBA_WCKB01_N FBA_WCKB01_P 36 FBVDDQ FBB_WCKB01* E8 FBB_WCK01_P FBB_WCKB01_N 38
FBA_WCKB01* P38 FBA_WCK01_P FBA_WCKB01_N 36 FBB_WCKB23 D8 FBB_WCK01_N FBB_WCK01_P 38
FBA_WCKB23 P39 FBA_WCK01_N FBA_WCK01_P 36 FBB_WCKB23* D33 FBB_WCKB45_P FBB_WCK01_N 38
FBA_WCKB23* FBA_WCK01_N 36 FBB_WCKB45 FBB_WCKB45_P 39
1
AV35 FBA_WCKB45_P C33 FBB_WCKB45_N
FBA_WCKB45 FBA_WCKB45_P 37
CKE_A FBB_WCKB45* FBB_WCKB45_N 39
1
AV36 FBA_WCKB45_N C27 FBB_WCK45_P
FBA_WCKB45* FBA_WCKB45_N 37
CKE_A RG1312 RG1313
FBB_WCKB67 FBB_WCK45_P 39 +FB_PLLAVDD
AN36 FBA_WCK45_P RG1286 RG1287 10K_0402_1% 10K_0402_1% B27 FBB_WCK45_N
FBA_WCKB67 AN37 FBA_WCK45_N FBA_WCK45_P 37 +FB_PLLAVDD 10K_0402_1% 10K_0402_1% OPT@ OPT@ FBB_WCKB67* FBB_WCK45_N 39
FBA_WCKB67* FBA_WCK45_N 37 OPT@ OPT@ K13 +FB_PLLAVDD
2
FB_VREF F35 R31 FBB_CMD14 FB_PLLVDD_1
3.9P_50V_B_NPO_0402
2
FB_VREF FB_PLLVDD_3 FBA_CMD14 FBB_CMD44
FBA_CMD44
OPT@
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1
2.49K_0402_1%
1 1 1
@
OPT@
OPT@
2 2 FBVDDQ FBVDDQ 2
CG1522
2
RG702
CG2123
CG2124
*
GN20-P1/P0 stuff 2.49Kohm Under GPU
1
1
CKE_B CKE_B
N18P-G61-A stuff 49.9ohm RG1310 RG1311 RG1288 RG1289
10K_0402_1% 10K_0402_1% 10K_0402_1% 10K_0402_1%
OPT@ OPT@ OPT@ OPT@
Under GPU
2
2
+FB_PLLAVDD FBA_CMD17 FBB_CMD17
FBA_CMD41 FBB_CMD41
30ohms (ESR=0.01) Bead FBB_CMD3

22U_6.3V_M_X6S_0603
4.7U_6.3V_K_X6S_0603
4.7U_6.3V_K_X6S_0603
P/N;SM01000M300 FBA_CMD3 FBB_CMD31

+1.8VS_VGA N18 change +FB_PLLAVDD
1 1 1
FBA_CMD31
1
A A
1
1 2 +FB_PLLAVDD 2 2 2
OPT@
RESET RG87 RG88

OPT@
OPT@
CG1967
CG474
CG562
LG7 RESET RG76 RG80 10K_0402_1% 10K_0402_1%

HCB1608KF-300T60_2P 10K_0402_1% 10K_0402_1% OPT@ OPT@
OPT@ OPT@ OPT@
2
2
Place close to BGA

Near GPU
Vinafix.com
Issued Date 2021/04/07 Deciphered Date 2021/04/07 N18P_(3/6):VRAM I/F
Custom
HY568 0.1

5 4 3 2 1
5 4 3 2 1
+1.8VS_AON
+1.8VS_AON +3VS
UG1K @
GN20-P-FCBGA1358_BGA1358 I2CB_SCL RG22 1 OPT@ 2 2.2K_0402_5%
2
10/17 MISC1
RG214
10K_0402_5%
I2CB_SDA RG25 1 OPT@ 2 2.2K_0402_5% Power on/off sequence +3VALW_SYS RG1129
10K_0402_5%
OPT@ U1 VGA_SMB_CK2 1V8_MAIN_EN RG27 1 OPT@ 2 10K_0201_5% OPT@
I2CS_SCL 1V8_MAIN_EN
2
V1 VGA_SMB_DA2
Internal Thermal Sensor
1
OVERT_N P1 I2CS_SDA NVVDD_PSI RG28 1 @ 2 10K_0201_5% RG1132 1V8_MAIN_EN_R
28 OVERT_N OVERT I2CC_SCL 1V8_MAIN_EN_R 34
U2 10K_0402_5%
TG5 @ 1 TS_VREF AP8 I2CC_SCL V2 I2CC_SDA VGA_ALERT_N RG23 1 OPT@ 2 10K_0201_5% OPT@
TS_VREF I2CC_SDA
3
D
1
M2 U3 I2CB_SCL VGA_AC_DET_R RG26 1 OPT@ 2 10K_0201_5% 1V8_MAIN_EN_N 5 QG32B
THERMDN I2CB_SCL I2CB_SDA I2CB_SCL 46
V3 G LBSS138DW1T1G_SOT363-6
I2CB_SDA I2CB_SDA 46 ADC_MUX_SEL
M1 RG381 1 OPT@ 2 2.2K_0402_5% S OPT@
4
THERMDP
6
P3 NVVDD_PWM_VID D
GPIO0 FB_GC6_EN NVVDD_PWM_VID 102 MEM_VREF_CTL 1V8_MAIN_EN
P7 RG32 1 OPT@ 2 100K_0201_5% 2 QG32A
GPIO1 R4 GPU_EVENT_N G LBSS138DW1T1G_SOT363-6
GPIO2
1
TG1 @ 1 JTAG_TCK AY11 U6 GPU_MUX_CNTL_RC PWM_SW_SELECT RG1302 1 OPT@ 2 10K_0201_5% OPT@
S
1
D TG2 @ 1 JTAG_TMS AV11 JTAG_TCK GPIO3 U7 1V8_MAIN_EN RG1133 D
TG3 @ 1 JTAG_TDI
JTAG_TDO
AW11 JTAG_TMS
JTAG_TDI
GPIO4
GPIO5
V4
NVVDD_PSI_GPU
*
Option Pin
GN20-P1 & P0 NVVDD_EN
N18P-G61-A 1V8_MAIN_EN
iGPU_EDP_ENBKL RG1299 1 @ 2 100K_0201_5% 10K_0402_5% @
RG37 TG4 @ 1 AW12 R7 RG107 1 @ 2 0_0402_5%
JTAG_TRST JTAG_TDO GPIO6 NVVDD_PSI 102
OPT@ 1 2 10K_0402_5% AV12 M6 GPU_EDP_PWM GPU_MUX_CNTL_RC RG1301 1 OPT@ 2 10K_0201_5%
GPU_EDP_PWM 45
2
RG24 1 2 10K_0402_5% NVJTAG_SEL AY12 JTAG_TRST* GPIO7 L8 FBVDDQ_SEL
NVJTAG_SEL GPIO8 FBVDDQ_SEL 107
OPT@ M7 VGA_ALERT_N GPU_EDP_ENBKL RG1305 1 OPT@ 2 100K_0201_5%
RG1228 1 @ 2 0_0402_5% ADC_IN_P_GPU Y3 GPIO9 L5 MEM_VREF_CTL
105 ADC_IN_P ADC_IN GPIO10 MEM_VREF_CTL 36,38,50
RG1229 1 @ 2 0_0402_5% ADC_IN_N_GPUY4 R8 GPU_EDP_ENVDD GPU_EDP_PWM RG1306 1 OPT@ 2 100K_0201_5% 1V8_MAIN_EN RG12311 @ 2 0_0402_5% 1V8_MAIN_EN_R
105 ADC_IN_N ADC_IN* GPIO11 GPU_EDP_ENVDD 45
M3 VGA_AC_DET_R
GPIO12 P6 iGPU_EDP_ENBKL GPU_EDP_ENVDD RG1307 1 OPT@ 2 10K_0201_5%
GPIO13 IFPA_HPD iGPU_EDP_ENBKL 46
P5
GPIO14 IFPB_HPD IFPA_HPD 12 +3VS
P2
GPIO15 IFPB_HPD 12
U4 PWM_SW_SELECT_GPIO16 RG1304 1 @ 2 0_0402_5% +1.8VS_VGA +3VS
GPIO16 GPU_EDP_HPD PWM_SW_SELECT 46
P4
GPIO17 IFPE_HPD GPU_EDP_HPD 45 OPT@
L6 1
PAD TG16 +1.8VS_AON DG10
2
GPIO18 R3 @ OVERT_N_NVEN 1 2
GPIO19 MVVDD_EN 28 OVERT_N_NVEN RG109
1
R5 FBVDDQ_SEL 2 @ 1 10K_0402_5%
GPIO20 GPU_EDP_ENBKL 10K_0402_5%
R2 RG41 RB751V-40_SOD323-2 RG13 RG334
GPIO21 GPU_EDP_ENBKL 45 OPT@
M5 ADC_MUX_SEL_R RG1239 1 @ 2 0_0402_5% OPT@ 0_0402_5% 10K_0402_1%
GPIO22 ADC_MUX_SEL 105
U5 GPU_PEX_RST_HOLD_N_R @ 1 2 1 10K_0402_5% DG9 @
1
GPIO23 PAD OPT@
L7 TG14 RG43
2
GPIO24 R6 FBVDDQ_PSI @ 1 PXS_PWREN RG220 1 @ 2 0_0402_5% NVVDD_EN_CNTH 3 PXS_PWREN
GPIO25 PAD 20,34 PXS_PWREN
M4 GPIO26_FUNC_OPT TG15 1
GPIO26 IFPC_HPD VGA_ALERT_N 20 1V8_MAIN_EN_R NVVDD_EN 31,102
R1 RG1319 1 @ 2 0_0402_5% NVVDD_EN_CNT 2
GPIO27 IFPC_HPD 50 OPT@
1
M8 @
GPIO28 P8 VGA_ALERT_N DG6 2 1 RB751V-40_SOD323-2 BAT54AW_SOT323-3
GPIO29 P9 RG335 RG115
GPIO30 R9 100K_0402_5% 100K_0402_5%
GPIO31 U9 VGA_AC_DET_R 2 1 RB751V-40_SOD323-2 @ @
VGA_AC_DET 79
2
GPIO32 V9 GPIO26_FUNC_OPT RG1323 1 N18P@ 2 0_0402_5% GPIO26_FP_FUSE DG1
GPIO33 GPIO26_FP_FUSE 34
U10
GPIO34 V10 RG1324 1 GN20@ 2 0_0402_5% GPIO26_ROM_WP OPT@
GPIO35 GPIO26_ROM_WP 32
for N18P-G61 GPIO[28..35] NC GPU_MUX_CNTL_RC RG1357 1 @ 2 0_0402_5%

GN20-P1/P0 stuff RG1324
* N18P-G61-A stuff RG1323
GPU_MUX_CNTL 46
1
CG1782 +3VS
+1.8VS_AON
0.1U_25V_K_X5R_0402
@ 0.95V_MAIN_EN
2
OPT@
1
2
PXS_PWREN 1 2 RG331
RG89 1/16W_8.2K_1%_0402
DG8
RB751V-40_SOD323-2 10K_0402_5% OPT@
@
2
DG7
1
+1.8VS_AON +1.8VS_AON +3VS
+3VS 1V8_MAIN_EN_R RG1321 1 @ 2 0_0402_5% 0.95V_MAIN_EN_CNT 2
1 0.95V_MAIN_EN_R RG98 1 @ 2 0_0402_5%
NVVDD_PWRGD 0.95V_MAIN_EN 31
3
50,102 NVVDD_PWRGD
2
1
RG12
2
RG1209 RG1208 +3VALW_SYS 10K_0402_5% OPT@ RG330

C 2.2K_0402_5% 2.2K_0402_5% RG1212 RG1213 OPT@ RG4 1 2 10K_0402_5% BAT54AW_SOT323-3 C
+3VS 10K_0402_5%
OPT@ OPT@ 2.2K_0402_5% 2.2K_0402_5% OPT@ OPT@
5
2
OPT@ OPT@ RG57
1
2
10K_0402_5%
G2
OPT@ FB_GC6_EN_R RG51 1 @ 2 0_0402_5%

I2CC_SCL PCH_FB_GC6_EN 20
4 3
S2 D2 NVDD_SCL 102,105
3
D
QG35B FB_GC6_EN_N 5 QG7B
PJT7838_SOT363-6 G LBSS138DW1T1G_SOT363-6 FBVDDQ_PWR_EN
OPT@ S OPT@ UG12
4
2 1 FB_GC6_EN_R RG110 1 @ 2 0_0402_5% FB_GC6_EN_RR 1 4 FBVDDQ_PWR_EN
0.95VGS_PG 0.95VGS_PG_R IN B OUT Y FBVDDQ_PWR_EN 31,107
RG1211 RG325 1 @ 2 0_0402_5% 2
IN A
2
6
0_0402_5% @ D
FB_GC6_EN 2 QG7A NVVDD_PWRGD 1 2 3 5
G1
GND Vcc +3VS

LBSS138DW1T1G_SOT363-6 RG1341 @ 10K_0402_5%
0.1U_10V_K_X5R_0402
G
I2CC_SDA 1 6 1 OPT@
NVDD_SDA 102,105 S
1
S1 D1 MC74VHC1G32DFT2G_SC70-5
RG313 1 1
Vgs(th)≤1.0V
CG458
10K_0402_5% OPT@
QG35A @ CG1189
OPT@ 0.1U_10V_K_X5R_0402
PJT7838_SOT363-6
OPT@ 2 2 OPT@
2
2 1 RG55 1 @ 2 0_0402_5%
RG1210
0_0402_5% @
+3VS
2
+1.8VS_AON VGA_PWRGD BAT54AW
VF=0.32V @ IF=1mA
RG104
10K_0402_5%
DG3 OPT@
PLT_RST_VGA_N
RG49 1 @ 2 0_0402_5% FBVDDQ_PWROK_R 2
1
107 FBVDDQ_PWROK
1
VGA_PWRGD 20,28
2
+1.8VS_AON +1.8VS_AON RG64 1 @ 2 0_0402_5% 0.95VGS_PG_RR 3

2
103 0.95VGS_PG
RG1241 RG1138 RG1240 +3VS
RG1136
10K_0402_5% @ 0_0402_5% @ 0_0402_5%
+1.8VS_AON 10K_0402_5% BAT54AW_SOT323-3
@
@
1
OPT@
1
RG319 RG59
1
EC_SMB_DA2_PWR @
10K_0402_5% 0_0402_5%
1
OPT@
EC_SMB_CK2_PWR RG320
2
2GPU_EVENT_GATE 1
2
10K_0402_5%
RG5 RG6 OPT@ NVVDD
2.2K_0402_5% 2.2K_0402_5% Discharge +0.95VGS
2
5
OPT@ OPT@
NVVDD Discharge
G2
1
1/8W_15_1%_0805
1/8W_15_1%_0805
+0.95VGS Discharge
2 RG1333 1
2 RG1334 1
B VGA_SMB_CK2 4 3 B
1/8W_15_1%_0805
1/8W_15_1%_0805
S2 D2 EC_SMB_CK2 45,76,79,102
2 RG63 1
2 RG328 1
@
OPT@
OPT@
QG3B +5VALW
PJT7838_SOT363-6 +5VALW
OPT@
1
GPU_EVENT_N 3 1 GPU_EVENT_N_R RG318 1 @ 2 NVVDD_DIS
PCH_GPU_EVENT_N 20
1
2 1 RG60 +0.95VGS_DIS
2
RG1238 0_0402_5% 47K_0402_5% RG1308
1
@
0_0402_5% @ QG8 47K_0402_5%
G1
1
LSI1012XT1G_SC-89-3 OPT@
D
2
VGA_SMB_DA2 1 6 OPT@
D
EC_SMB_DA2 45,76,79,102 Vgs(th)≤0.9V
2
S1 D1 NVVDD_EN_N 2
G 0.95V_MAIN_EN_N 2
Vgs(th)≤1.0V G
QG3A PU AT EC SIDE, +3VS AND 4.7K RG317 1 @ 2 0_0402_5%
LBSS139WT1G_SC70-3
S
PJT7838_SOT363-6 QG11 QG126
LBSS139WT1G_SC70-3
1
D
S
OPT@ QG49 QG12
AO3402_SOT-23-3
1
D
@
2
3
31,102 NVVDD_EN AO3402_SOT-23-3
@
2 1 2
OPT@
G 31,103 0.95V_MAIN_EN
RG1235 S G OPT@
3
0_0402_5% @ S
3
+3VALW_SYS +3VS
FBVDDQ
2
1
RG1358 RG38 FBVDDQ Discharge
@ 0_0402_5% 0_0402_5% RG61
470_0603_5%
@
@
1
+5VALW
FBVDDQ_DIS 2
1
VGA_RST_PWR
+3VS RG48
1 +1.8VS_AON 47K_0402_5%
@
CG58
2
0.1U_10V_K_X5R_0402
2
2
RG216 2 OPT@
3
D QG6B
10K_0402_5% RG50 FBVDDQ_PWR_EN_N 5
@ 10K_0402_5% L2N7002KDW1T1G_SOT363-6
G
OPT@
@
1
6
UG2 D QG6A
1
PLT_RST_N 1 2 S
4
P
20,52,55,63,71,73,78,79 PLT_RST_N B VGA_RST_N PLT_RST_VGA_N 31,107 FBVDDQ_PWR_EN L2N7002KDW1T1G_SOT363-6

4 RG44 1 @ 2 0_0402_5% G
Y PLT_RST_VGA_N 28
@
2
20 PXS_RST_N A
G
1
1
A MC74VHC1G09DFT2G_SC70-5 A
3
OPT@
1
RG217
100K_0402_5% RG324
OPT@ 100K_0402_5%
2
OPT@
2
Issued Date 2021/04/07 Deciphered Date 2021/04/07 N18P_(4/6):GPIO
Vinafix.com
Custom
HY568 0.1

5 4 3 2 1
5 4 3 2 1
UG1P +1.8VS_AON +1.8VS_AON
12/17 MISC2
EEPROM
10U_10V_M_X6S_0603
RG245 RG141
N18P@
1 1
Y8 ROM_CS_N 10K_0402_5%
CG1703
ROM_CS* 0_0402_5%
@
OPT@ CG145
Y7 ROM_SI 0.1U_10V_K_X5R_0402
1
ROM_SI Y9 ROM_SO UG10 2 2 OPT@
STRAP0 V5 ROM_SO Y10 ROM_SCLK ROM_CS_N RG138 2 OPT@ 133_0402_5% ROM_CS_N_R 1 8
STRAP1 V8 STRAP0 ROM_SCLK /CS VCC
STRAP2 Y5 STRAP1 ROM_SO RG137 1 @ 2 0_0402_5% ROM_SO_R 2 7
STRAP3 V7 STRAP2 DO(IO1) /HOLD(IO3)
STRAP4 U8 STRAP3 GPIO26_ROM_WP 3 6 ROM_SCLK_R RG139 2 OPT@ 1 33_0402_5% ROM_SCLK
STRAP4 31 GPIO26_ROM_WP /WP(IO2) CLK
STRAP5 V6
STRAP5
2
D ROM_SI_R ROM_SI D
4 5 RG140 2 OPT@ 1 33_0402_5%
RG249 GND DI(IO0)
GN20@
10K_0402_5%
W25Q16JWSNIQ_SOIC8
@ * BOM Structure controller
1
GPU ROM size ROM Partnumber
GN20x-P 2MB SA0000AU500
N18P-G61-A 1MB SA000080E00
+1.8VS_AON
1
RG197 RG1202 RG199

1/20W_100K_1%_0201 10K_0201_1% 1/20W_100K_1%_0201 1:ENABLE 0:DISABLE
@ @ GN20@ SOR0 DISABLE
SOR1/2/3 ENABLE
2
ROM_SI
GPU ROM_SO ROM_SI ROM_SCLK SOR_EXPOSED[3:0]
ROM_SO
ROM_SCLK
N18P-G61-A L L L ENABLE OVERT*
1
C C
RG200 RG1203 RG202 GN20x-P L L H ENABLE OVERT*
1/20W_100K_1%_0201 10K_0201_1% 1/20W_100K_1%_0201
OPT@ OPT@ N18P@
2
+1.8VS_AON
VRAMCFG
1
RG187 RG188 RG189 GPU VRAM FB Memory (GDDR6) RAMCFG[2:0] STRAP2 STRAP1 STRAP0
1/20W_100K_1%_02011/20W_100K_1%_0201 1/20W_100K_1%_0201
@ @ @
GN20x-P1 Samsung 8Gb K4Z80325BC-HC14 0(0x0000) L L L
2
GN20x-P0
STRAP2 N18P-G61-A Micron 8Gb MT61K256M32JE-14:A 1(0x0001) L L H
4GB
STRAP1
Hynix 8Gb H56C8H24AIR-S2C 2(0x0002) L H L
STRAP0
1
RG192 RG193 RG194

1/20W_100K_1%_02011/20W_100K_1%_0201 1/20W_100K_1%_0201
@ @ @
2
B B
+1.8VS_AON VGA_DEVICE
STRAP5 STRAP4 STRAP3 SMB_ALT_ADDR DEVID_SEL PCIE_CFG VGA_DEVICE
1
L L H 0 0 0 1
RG19 RG21 RG74
1/20W_100K_1%_02011/20W_100K_1%_0201 1/20W_100K_1%_0201
OPT@ @ OPT@
1: SMB_ALT_ADDR ENABLE
*
1:DEVID_SEL for G-SYNC SKU
2
STRAP5 0: SMB_ALT_ADDR DISABLE

STRAP4
1: DEVID_SEL REBRAND
STRAP3
0: DEVID_SEL ORIGNAL
1
RG78 RG75 RG77 1: PCIE_CFG LOW POWER

1/20W_100K_1%_02011/20W_100K_1%_0201 1/20W_100K_1%_0201
@ OPT@ @ 0: PCIE_CFG HIGH POWER
2
1: VGA_DEVICE ENABLE
0: VGA_DEVICE DISABLE
A A
Issued Date 2021/04/07 Deciphered Date 2021/04/07 Blank
Vinafix.com
C
HY568 0.1

5 4 3 2 1
5 4 3 2 1
UG1H
NVVDD NVVDD NVVDD UG1F NVVDD
UNDER GPU NEAR GPU
68A 13/17 VDD
NVVDD NVVDD 9/17 Configurable
AA13 T19 UG1G Power Channels
NVVDD NVVDD
AA14 VDD_01 VDD_71 T20
VDD_02 VDD_72 68A 23*1uF 1 x 330uF
AA15 T21 AA1 AD6
AA16 VDD_03 VDD_73 T22
4/17 VDDMS
AA2 NC_XVDD_1 NC_XVDD_31 AD7
40 x 22uF
AA17 VDD_04 VDD_74 T23 AA12 AJ22 AA3 NC_XVDD_2 NC_XVDD_32 AD8
VDD_05 VDD_75 VDDMS_1 VDDMS_43 NC_XVDD_3 NC_XVDD_33
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
AA18 T24 AA29 AJ23 AA4 AD9 1 1 1 1 1 1 1 1 1 1 1 1
22U_6.3V_M_X6S_0603
22U_6.3V_M_X6S_0603
22U_6.3V_M_X6S_0603
22U_6.3V_M_X6S_0603
22U_6.3V_M_X6S_0603
22U_6.3V_M_X6S_0603
22U_6.3V_M_X6S_0603
22U_6.3V_M_X6S_0603
22U_6.3V_M_X6S_0603
22U_6.3V_M_X6S_0603
330U_B2_2.5VM_R9M
AA19 T25 AB12 AJ24 AA5 AD10 1
D AA20 VDD_07 VDD_77 T26 AB29 VDDMS_3 VDDMS_45 AJ25 AA6 NC_XVDD_5 NC_XVDD_35 AE2 D
VDD_08 VDD_78 VDDMS_4 VDDMS_46 NC_XVDD_6 NC_XVDD_36 1 1 1 1 1 1 1 1 1 1
+
@
AA21 T27 AC12 AJ26 AA7 AE4
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
AA22 VDD_09 VDD_79 T28 AC29 VDDMS_5 VDDMS_47 AJ27 AA8 NC_XVDD_7 NC_XVDD_37 AE6 2 2 2 2 2 2 2 2 2 2 2 2
AA23 VDD_10 VDD_80 V13 AD12 VDDMS_6 VDDMS_48 AJ28 AA9 NC_XVDD_8 NC_XVDD_38 AE8
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
CG2023
CG2024
CG2025
CG2026
CG2027
CG2028
CG2029
CG2030
CG2031
CG2032
CG2033
CG2034
AA24 VDD_11 VDD_81 V14 AD29 VDDMS_7 VDDMS_49 AJ29 AA10 NC_XVDD_9 NC_XVDD_39 AE10 2 2 2 2 2 2 2 2 2 2 2
AA25 VDD_12 VDD_82 V15 AE12 VDDMS_8 VDDMS_50 M12 AB2 NC_XVDD_10 NC_XVDD_40 AF1
CG1577
CG1870
CG1871
CG1872
CG1873
CG1874
CG1875
CG1876
CG1877
CG1878
CG1879
AA26 VDD_13 VDD_83 V16 AE29 VDDMS_9 VDDMS_51 M13 AB4 NC_XVDD_11 NC_XVDD_41 AF2
AA27 VDD_14 VDD_84 V17 AF12 VDDMS_10 VDDMS_52 M14 AB6 NC_XVDD_12 NC_XVDD_42 AF3
AA28 VDD_15 VDD_85 V18 AF29 VDDMS_11 VDDMS_53 M15 AB8 NC_XVDD_13 NC_XVDD_43 AF4 NVVDD
AC13 VDD_16 VDD_86 V19 AG12 VDDMS_12 VDDMS_54 M16 AB10 NC_XVDD_14 NC_XVDD_44 AF5
AC14 VDD_17 VDD_87 V20 AG13 VDDMS_13 VDDMS_55 M17 AC1 NC_XVDD_15 NC_XVDD_45 AF6
AC15 VDD_18 VDD_88 V21 AG14 VDDMS_14 VDDMS_56 M18 AC2 NC_XVDD_16 NC_XVDD_46 AF7 NVVDD
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
AC17 V23 AG16 M20 AC4 AF9 1 1 1 1 1 1 1 1 1 1 1
AC19 VDD_22 VDD_92 V25 AG18 VDDMS_18 VDDMS_60 M22 AC6 NC_XVDD_20 NC_XVDD_50 AG1
22U_6.3V_M_X6S_0603
22U_6.3V_M_X6S_0603
22U_6.3V_M_X6S_0603
22U_6.3V_M_X6S_0603
22U_6.3V_M_X6S_0603
22U_6.3V_M_X6S_0603
22U_6.3V_M_X6S_0603
22U_6.3V_M_X6S_0603
22U_6.3V_M_X6S_0603
22U_6.3V_M_X6S_0603
@
AC20 V26 AG19 M23 AC7 AG2
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
AC21 VDD_24 VDD_94 V27 AG20 VDDMS_20 VDDMS_62 M24 AC8 NC_XVDD_22 NC_XVDD_52 AG3 2 2 2 2 2 2 2 2 2 2 2
AC22 V28 AG21 M25 AC9 AG4
CG2127
CG2128
CG2129
CG2130
CG2131
CG2132
CG2133
CG2134
CG2135
CG2136
CG2022
AC23 VDD_26 VDD_96 W17 AG22 VDDMS_22 VDDMS_64 M26 AC10 NC_XVDD_24 NC_XVDD_54 AG5
@
AC24 W18 AG23 M27 AD1 AG6
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
AC25 VDD_28 VDD_98 W19 AG24 VDDMS_24 VDDMS_66 M28 AD2 NC_XVDD_26 NC_XVDD_56 AG7 2 2 2 2 2 2 2 2 2 2
AC26 VDD_29 VDD_99 W20 AG25 VDDMS_25 VDDMS_67 M29 AD3 NC_XVDD_27 NC_XVDD_57 AG8
CG1881
CG1882
CG1883
CG1884
CG1885
CG1886
CG1887
CG1888
CG1889
CG1890
AC27 VDD_30 VDD_100 W25 AG26 VDDMS_26 VDDMS_68 N12 AD4 NC_XVDD_28 NC_XVDD_58 AG9
AC28 VDD_31 VDD_101 W26 AG27 VDDMS_27 VDDMS_69 N29 AD5 NC_XVDD_29 NC_XVDD_59 AG10 NVVDD
AE13 VDD_32 VDD_102 W27 AG28 VDDMS_28 VDDMS_70 P12 NC_XVDD_30 NC_XVDD_60
AE14 VDD_33 VDD_103 W28 AG29 VDDMS_29 VDDMS_71 P29
VDD_34 VDD_104 VDDMS_30 VDDMS_72 34*10uF
AE15 Y13 AH12 R12 AN21 AN25
AE16 VDD_35 VDD_105 Y14 AH29 VDDMS_31 VDDMS_73 R29 AP21 NC_XVDD_61 NC_XVDD_87 AP25
AE17 VDD_36 VDD_106 Y15 AJ12 VDDMS_32 VDDMS_74 T12 AR21 NC_XVDD_62 NC_XVDD_88 AR25
10U_10V_M_X6S_0603
10U_10V_M_X6S_0603
10U_10V_M_X6S_0603
10U_10V_M_X6S_0603
10U_10V_M_X6S_0603
10U_10V_M_X6S_0603
10U_10V_M_X6S_0603
10U_10V_M_X6S_0603
10U_10V_M_X6S_0603
10U_10V_M_X6S_0603
10U_10V_M_X6S_0603
C AE18 Y16 AJ13 T29 AU21 AU25 1 1 1 1 1 1 1 1 1 1 1 C
AE19 VDD_38 VDD_108 Y21 AJ14 VDDMS_34 VDDMS_76 U12 AV21 NC_XVDD_64 NC_XVDD_90 AV25 NVVDD
AE20 VDD_39 VDD_109 Y22 AJ15 VDDMS_35 VDDMS_77 U29 AW21 NC_XVDD_65 NC_XVDD_91 AW25
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
AE21 VDD_40 VDD_110 Y23 AJ16 VDDMS_36 VDDMS_78 V12 AP22 NC_XVDD_66 NC_XVDD_92 AP26
AE22 VDD_41 VDD_111 Y24 AJ17 VDDMS_37 VDDMS_79 V29 AR22 NC_XVDD_67 NC_XVDD_93 AR26 2 2 2 2 2 2 2 2 2 2 2
AE23 VDD_42 VDD_112 P21 AJ18 VDDMS_38 VDDMS_80 W12 AT22 NC_XVDD_68 NC_XVDD_94 AT26
CG1644
CG1645
CG1646
CG1647
CG1648
CG1649
CG1650
CG1651
CG1652
CG1653
CG1654
22U_6.3V_M_X6S_0603
22U_6.3V_M_X6S_0603
22U_6.3V_M_X6S_0603
22U_6.3V_M_X6S_0603
22U_6.3V_M_X6S_0603
22U_6.3V_M_X6S_0603
22U_6.3V_M_X6S_0603
22U_6.3V_M_X6S_0603
22U_6.3V_M_X6S_0603
22U_6.3V_M_X6S_0603
AE24 P22 AJ19 W29 AU22 AU26
AE25 VDD_44 VDD_58 P23 AJ20 VDDMS_40 VDDMS_82 Y12 AV22 NC_XVDD_70 NC_XVDD_96 AV26
AE26 P24 AJ21 Y29 AW22 AW26
AE27 VDD_46 VDD_60 P25 VDDMS_42 VDDMS_84 AY22 NC_XVDD_72 NC_XVDD_98 AY26
VDD_47 VDD_61 NC_XVDD_73 NC_XVDD_99 NVVDD
@
AE28 P26 AN23 AN27
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
P13 VDD_48 VDD_62 P27 AP23 NC_XVDD_74 NC_XVDD_100 AP27 2 2 2 2 2 2 2 2 2 2
P14 VDD_49 VDD_63 P28 AR23 NC_XVDD_75 NC_XVDD_101 AR27
CG1860
CG1861
CG1862
CG1863
CG1864
CG1865
CG1866
CG1867
CG1868
CG1869
P15 VDD_50 VDD_64 T13 AU23 NC_XVDD_76 NC_XVDD_102 AU27
P16 VDD_51 VDD_65 T14 AV23 NC_XVDD_77 NC_XVDD_103 AV27
P17 VDD_52 VDD_66 T15 AW23 NC_XVDD_78 NC_XVDD_104 AW27
VDD_53 VDD_67 NC_XVDD_79 NC_XVDD_105
10U_10V_M_X6S_0603
10U_10V_M_X6S_0603
10U_10V_M_X6S_0603
10U_10V_M_X6S_0603
10U_10V_M_X6S_0603
10U_10V_M_X6S_0603
10U_10V_M_X6S_0603
10U_10V_M_X6S_0603
10U_10V_M_X6S_0603
10U_10V_M_X6S_0603
10U_10V_M_X6S_0603
P18 T16 AP24 AP28 1 1 1 1 1 1 1 1 1 1 1
VDD_54 VDD_68 NC_XVDD_80 NC_XVDD_106
P19
VDD_55 VDD_69
T17 trace width: 8-10mils AR24
NC_XVDD_81 NC_XVDD_107
AR28
@
P20 T18 M9 AT24 AT28
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
VDD_56 VDD_70 VDDMS_SENSE M10 MSVDD_VDD_SENSE 102 NC_XVDD_82 NC_XVDD_108 NVVDD
AU24 AU28
GNDMS_SENSE MSVDD_VSS_SENSE 102 NC_XVDD_83 NC_XVDD_109 2 2 2 2 2 2 2 2 2 2 2
AV24 AV28
GN20-P-FCBGA1358_BGA1358 AW24 NC_XVDD_84 NC_XVDD_110 AW28
CG1655
CG1656
CG1657
CG1658
CG1659
CG1660
CG1661
CG1662
CG1663
CG1664
CG1665
@ N18P : NC AY24 AY28
GN20 Use merged-rail design : NC
22U_6.3V_M_X6S_0603
22U_6.3V_M_X6S_0603
22U_6.3V_M_X6S_0603
22U_6.3V_M_X6S_0603
22U_6.3V_M_X6S_0603
22U_6.3V_M_X6S_0603
22U_6.3V_M_X6S_0603
22U_6.3V_M_X6S_0603
22U_6.3V_M_X6S_0603
22U_6.3V_M_X6S_0603
GN20-P-FCBGA1358_BGA1358
@ 1 1 1 1 1 1 1 1 1 1
NVVDD
NVVDD
@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
2 2 2 2 2 2 2 2 2 2
B B
CG1905
CG1906
CG1907
CG1908
CG1909
CG1910
CG1911
CG1912
CG1913
CG1914
330U_B2_2.5VM_R9M
1
10U_10V_M_X6S_0603
10U_10V_M_X6S_0603
10U_10V_M_X6S_0603
10U_10V_M_X6S_0603
10U_10V_M_X6S_0603
10U_10V_M_X6S_0603
10U_10V_M_X6S_0603
10U_10V_M_X6S_0603
10U_10V_M_X6S_0603
10U_10V_M_X6S_0603
10U_10V_M_X6S_0603
10U_10V_M_X6S_0603
1 1 1 1 1 1 1 1 1 1 1 1
+
@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
2 2 2 2 2 2 2 2 2 2 2 2 2
L9
CG2145
CG1666
CG1667
CG1668
CG1669
CG1670
CG1671
CG1672
CG1673
CG1674
CG1675
CG1676
CG1677
VDD_SENSE NVVDD_VDD_SENSE 102
L10
GND_SENSE NVVDD_VSS_SENSE 102
trace width: 8-10mils

GN20-P-FCBGA1358_BGA1358
@
A A

Issued Date 2021/04/07 Deciphered Date 2021/04/07 Blank
Custom
HY568 0.1

5
Vinafix.com
4 3 2 1
5 4 3 2 1
FBVDDQ UG1J FBVDDQ
13A 14/17 FBVDDQ

2 x 10uF
AA31
FBVDDQ_01 FBVDDQ_36
F19 FBVDDQ 13A 6 x 1uF UG1I
AA36 F22 Partition A Under GPU +1.8VS_AON
AB33 FBVDDQ_02 FBVDDQ_37 F23 17/17 1V8 / NC
FBVDDQ_03 FBVDDQ_38
AB34 G16 under GPU near GPU
AB35 FBVDDQ_04 FBVDDQ_39 G19 AR8 P10 0.4A
10U_10V_M_X6S_0603
10U_10V_M_X6S_0603
AB36 FBVDDQ_05 FBVDDQ_40 G21 AR9 NC_1 1V8_1 R10
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
AB39 FBVDDQ_06 FBVDDQ_41 H16 AT8 NC_2 1V8_2
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
4.7U_6.3V_K_X6S_0603
4.7U_6.3V_K_X6S_0603
4.7U_6.3V_K_X6S_0603
AC31 FBVDDQ_07 FBVDDQ_42 H19 AT9 NC_3
FBVDDQ_08 FBVDDQ_43 NC_4
OPT@
AC35 H22 AV3
FBVDDQ_09 FBVDDQ_44 NC_5
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
AD31 H23 @ AW2
FBVDDQ_10 FBVDDQ_45 2 2 2 2 2 2 2 2 NC_6 2 2 2 2 2 2 2 2
OPT@
OPT@
OPT@
AE33 K15 Y6
AE34 FBVDDQ_11 FBVDDQ_46 K17 NC_7
CG203
CG207
CG211
CG1633
CG1634
CG2010
CG2011
CG2012
CG2013
CG2014
CG2015
CG2016
CG2017
CG2018
CG2019
CG2020
AE35 FBVDDQ_12 FBVDDQ_47 K18
AF31 FBVDDQ_15 FBVDDQ_50 K23 Y2
D D
AG31 FBVDDQ_16 FBVDDQ_51 K24 FUSE_SRC
AG35 FBVDDQ_17 FBVDDQ_52 K25
AH31 FBVDDQ_18 FBVDDQ_53 K26
AH37 FBVDDQ_19 FBVDDQ_54 K30 FBVDDQ +FUSE_1V8
FBVDDQ_20 FBVDDQ_55 2 x 10uF
AH39 L31 Partition B Under GPU
AJ31 FBVDDQ_21 FBVDDQ_56 M31 6 x 1uF
FBVDDQ_22 FBVDDQ_57 1
1
B13 N31 @ GN20-P-FCBGA1358_BGA1358
B16 FBVDDQ_23 FBVDDQ_58 U31 @ @
10U_10V_M_X6S_0603
10U_10V_M_X6S_0603
B19 FBVDDQ_24 FBVDDQ_59 V31 CG1104 RG1200
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
B22 FBVDDQ_25 FBVDDQ_60 V33 2 1/16W_2.21K_1%_0402
1 1 1 1 1 1 1 1 2.2U_0402_6.3V6M
D13 FBVDDQ_26 FBVDDQ_61 V35
2
FBVDDQ_27 FBVDDQ_62
OPT@
OPT@
D23 V37
FBVDDQ_28 FBVDDQ_63
@
OPT@
OPT@
OPT@
OPT@
OPT@
E16 W33
E19 FBVDDQ_29 FBVDDQ_64 W35 2 2 2 2 2 2 2 2
E20 FBVDDQ_30 FBVDDQ_65 W36
CG1678
CG1679
CG2004
CG2005
CG2006
CG2007
CG2008
CG2009
E22 FBVDDQ_31 FBVDDQ_66 W39
F14 FBVDDQ_32 FBVDDQ_67 Y31
F16 FBVDDQ_33 FBVDDQ_68 Y34 +1.8VS_AON +FUSE_1V8
F18 FBVDDQ_34 FBVDDQ_69
FBVDDQ_35
GN20@
FBVDDQ RG1325 1 2 1/10W_0_5%_0603
5 x 22uF
Near GPU 2 x 10uF
UG11
CG1103 1 2 N18P@ A2 A1 +FUSE_1V8
10U_10V_M_X6S_0603
10U_10V_M_X6S_0603
22U_6.3V_M_X6S_0603
22U_6.3V_M_X6S_0603
22U_6.3V_M_X6S_0603
22U_6.3V_M_X6S_0603
22U_6.3V_M_X6S_0603
2.2U_0402_6.3V6M VIN Vout
1 1 1 1 1 1 1 B1 B2 GPIO26_FP_FUSE
GND ON GPIO26_FP_FUSE 31
OPT@
1
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
AP22913CN4-7_X1-WLB0909-4
2 2 2 2 2 2 2 RG1198
N18P@
10K_0402_5%
CG1968
CG1969
CG1970
CG1971
CG1972
CG1680
CG1681
N18P@
K11FBVDDQ_SENSE_GPU RG90 1 @ 2 0_0402_5%
FBVDDQ_VCC_SENSE 107
2
FBVDDQ_SENSE
H32 FBCAL_VDDQ 1 OPT@ 2 FBVDDQ

FB_CAL_PD_VDDQ RG92 40.2_0402_1%
J32 FBCAL_GND 1 OPT@ 2
FB_CAL_PU_GND RG93 40.2_0402_1%
C FBCAL_TERM C
J33 1 OPT@ 2
FB_CAL_TERM_GND RG94 40.2_0402_1%
Place close to GPU

+1.8VALW +1.8VS_AON
QG4
AON7380_DFN8-5
1
B+ 2 1.7A
5 3
+5VALW
0.1U_25V_K_X5R_0402
2
1
RG1116 CG1117
+1.8VALW to +1.8VS_AON
10U_10V_M_X6S_0603
4
1
1
100K_0402_5% OPT@ @ 0.01U_50V_K_X7R_0402 1
1
RG1342 OPT@ @
CG1118
CG1113
2
OPT@
47K_0402_5% RG1118
2
OPT@ RG1120 1/10W_47_5%_0603
+1.8VS_AON_GATE_EN 1 2 +1.8VS_AON_GATE OPT@ 2
2
1K_0402_5%
0.047U_0402_25V_X7R_0402
+1.8VS_AON_DIS 2
OPT@
3
QG25B D 1
+1.8VS_AON_EN_N
L2N7002KDW1T1G_SOT363-6
OPT@
5
CG1116
G
1
6
QG25A D OPT@ S RG1121 2
4
PXS_PWREN_GATE
RG1117 1 @ 2 0_0402_5% 2 430K_0402_1%

20,31 PXS_PWREN G OPT@ OPT@
DG12
2
1
1
S D
1
1
3 PXS_PWREN_DELAY RG1340 1 @ 2 0_0402_5% CG1115 RG1119 +1.8VS_AON_EN_N 2 QG23

0.1U_25V_K_X5R_0402100K_0402_5% G L2N7002KWT1G_SOT323-3
1 OPT@ @ OPT@
2
59K_0402_1% S
2
3
2 PXS_PWREN_DIS_DELAY RG1123 1 OPT@ 2
B LBAT54SWT1G_SOT323-3 B
OPT@ +1.8VS_AON discharger circuit
+1.8VS_AON +1.8VS_VGA
GN20@
RG1314 1 2 0_0805_5%
GN20@
RG1315 1 2 0_0805_5%
QG16
AON7380_DFN8-5
B+ 1
2 1.7A
+1.8VS_AON to +1.8VS_VGA
10U_10V_M_X6S_0603
5 3
2
CG74
1
1
+5VALW RG42 2 1
100K_0402_5% CG73 RG85
N18P@
4
N18P@ CG72 N18P@ @ 1/10W_47_5%_0603
1
0.1U_25V_K_X5R_0402 0.01U_50V_K_X7R_0402 N18P@ 2

1@
1
RG86 2
2
47K_0402_5% +1.8VS_VGA_GATE_EN 1 2 +1.8VS_VGA_GATE
N18P@ RG83
+1.8VS_VGA_DIS
1K_0402_5%
2
QG9B D N18P@ 2
+1.8VGS_PWR_EN_N
5 RG47
G 430K_0402_1% CG75
N18P@ 0.047U_0402_25V_X7R_0402
N18P@ S 1 N18P@
4
2
6
N18P@ RG1285 N18P@ QG9A D

1V8_MAIN_EN_RR 1V8_MAIN_EN_GATE
RG58 2 1 0_0402_5% 2 1 0_0402_5% 2

31 1V8_MAIN_EN_R
1
G N18P@ D
+1.8VGS_PWR_EN_N 2
0.1U_25V_K_X5R_0402
DG13 0_0402_5% 2 S G QG20

1
3 1V8_MAIN_EN_DELAY RG1114 1 2 @ RG84 2N7002KW_SOT323-3

CG1976
@ 100K_0402_5% S N18P@
3
1 @
0_0402_5% 1
2
A 1V8_MAIN_EN_DIS_DELAY A
2 RG1115 1 2
LBAT54SWT1G_SOT323-3
@ +1.8VS_VGA discharger circuit
@
Issued Date 2021/04/07 Deciphered Date 2021/04/07 N18P_(5/6):PWR

5
Vinafix.com
4
3 2
Custom
Date:
HY568
1
Sheet 34 of 110
0.1
5 4 3 2 1
UG1E
UG1D
16/17 GND_2/2
15/17 GND_1/2
Y1 N27
A10 AN10 E5 GND GND_344 N28
A2 GND_001 GND_121 AN31 E9 GND_240 GND_345 N4
A25 GND_002 GND_122 AN33 F11 GND_241 GND_346 N6
A31 GND_003 GND_123 AN34 F12 GND_242 GND_347 N8
A34 GND_004 GND_124 AN35 F25 GND_243 GND_348 P31
D
A4 GND_007 GND_127 AP12 F31 GND_246 GND_351 P35 D
A7 GND_008 GND_128 AP14 F32 GND_247 GND_352 P36
AB13 GND_009 GND_129 AP16 F34 GND_248 GND_353 P37
AB14 GND_010 GND_130 AP18 F36 GND_249 GND_354 R13
AB20 GND_016 GND_136 AP40 G1 GND_255 GND_360 R19
AB21 GND_017 GND_137 AP6 G12 GND_256 GND_361 R20
AB22 GND_018 GND_138 AR10 G13 GND_257 GND_362 R21
AD13 GND_027 GND_147 AR34 G40 GND_266 GND_371 R34
AD16 GND_030 GND_150 AR4 H11 GND_269 GND_374 T10
AD17 GND_031 GND_151 AR7 H2 GND_270 GND_375 T2
AD18 GND_032 GND_152 AT11 H25 GND_271 GND_376 T31
AD25 GND_039 GND_159 AU10 H36 GND_278 GND_383 T8
AD26 GND_040 GND_160 AU12 H39 GND_279 GND_384 U13
AE31 GND_043 GND_163 AU15 H6 GND_282 GND_387 U16
AE32 GND_044 GND_164 AU16 H8 GND_283 GND_388 U17
C C
AF13 GND_045 GND_165 AU17 H9 GND_284 GND_389 U18
AF14 GND_046 GND_166 AU18 J1 GND_285 GND_390 U19
AF28 GND_060 GND_180 AU9 J39 GND_299 GND_404 W10
AH10 GND_061 GND_181 AV14 J5 GND_300 GND_405 W13
AH15 GND_064 GND_184 AV20 K12 GND_303 GND_408 W16
AH16 GND_065 GND_185 AV32 K14 GND_304 GND_409 W2
AH17 GND_066 GND_186 AW1 K16 GND_305 GND_410 W21
AH2 GND_069 GND_189 E4 K22 GND_308 GND_413 W24
AH26 GND_076 GND_195 AY2 K6 GND_315 GND_420 Y17
AH27 GND_077 GND_196 AY32 K8 GND_316 GND_421 Y18
AH28 GND_078 GND_197 AY34 L32 GND_317 GND_422 Y19
AH36 GND_081 GND_200 B1 L39 GND_320 GND_425 Y26
B
AH4 GND_082 GND_201 B11 M32 GND_321 GND_426 Y27 B
AH6 GND_083 GND_202 B24 M33 GND_322 GND_427 Y28
AH8 GND_084 GND_203 B26 M34 GND_323 GND_428 N18
AJ3 GND_085 GND_204 B29 M35 GND_324 GND_334 N19
AJ35 GND_088 GND_207 B33 N10 GND_327 GND_337 N21
AK10 GND_091 GND_210 B5 N15 GND_330 GND_340 N24
AK32 GND_094 GND_213 C12 GND_333 GND_343
AK33 GND_095 GND_214 C2
AK35 GND_096 GND_215 C38
AK37 GND_097 GND_216 C9
AK39 GND_098 GND_217 D1
AL2 GND_099 GND_218 D11
AL30 GND_100 GND_219 D25
AL4 GND_101 GND_220 D27
AL40 GND_102 GND_221 D32
AL6 GND_103 GND_222 D34
AL8 GND_104 GND_223 D36
AM13 GND_105 GND_224 D39
AM15 GND_106 GND_225 D5
AM17 GND_107 GND_226 D7
AM19 GND_108 GND_227 D9
AM21 GND_109 GND_228 E12 AA34
AM23 GND_110 GND_229 E13 G20 OPT_GND_1
AM25 GND_111 GND_230 E2 AB37 OPT_GND_10
AM27 GND_112 GND_231 E24 AD34 OPT_GND_2
AM32 GND_113 GND_232 E26 AE37 OPT_GND_3
AM33 GND_114 GND_233 E27 AF35 OPT_GND_4
AM35 GND_115 GND_234 E29 D16 OPT_GND_5
AM36 GND_116 GND_235 E30 D19 OPT_GND_6
AM37 GND_117 GND_236 E33 F15 OPT_GND_7
AM38 GND_118 GND_237 E35 G17 OPT_GND_8
AM4 GND_119 GND_238 OPT_GND_9
A A
GND_120
Issued Date 2021/04/07 Deciphered Date 2021/04/07 N18E-G1_POWER VDDQ

C
HY568 0.1

5 4 3 2 1
Vinafix.com
5 4 3 2 1
UG4D
?
? UG4C
COMMON ?
?
FBVDDQ COMMON
30 FBA_CMD[0..24]
RG1345
A11 A1 UG4B FBA_CMD1 H3 K1 +FBA_A_VREFC 1 2 +FBA_VREFC
A13 VSS_1 VDD_1 A14 UG4A FBA_CMD13 G11 CA0_A VREFC 0_0201_5%
A2 VSS_2 VDD_2 E10 FBA_CMD12 G4 CA1_A N18P@
NORMAL
VSS_3 VDD_3 CA2_A
1
A4 E5 FBA_CMD24 H12
VSS_4 VDD_4 30 FBA_D[8..15] NORMAL 30 FBA_D[16..23] CA3_A
B1 H13 x16 x8 FBA_CMD11 H5 RG1346
B14 VSS_5 VDD_5 H2 FBA_D11 G2 FBA_D20 N2 FBA_CMD15 H10 CA4_A 1K_0402_1%
C10 VSS_6 VDD_6 L13 FBA_D10 B3 DQ7_A FBA_D19 P3 DQ6_B FBA_CMD22 J12 CA5_A GN20@
C12 VSS_7 VDD_7 L2 FBA_D8 F2 DQ2_A FBA_D18 M2 DQ4_B FBA_CMD23 J11 CA6_A
2
D
C3 VSS_8 VDD_8 P10 FBA_D12 E3 DQ6_A FBA_D21 P2 DQ7_B FBA_CMD0 J4 CA7_A D
VSS_9 VDD_9 BYTE1 FBA_D9 DQ4_A FBA_D23 DQ5_B FBA_CMD2 CA8_A
C5 P5 B4 BYTE2 U3 J3
D1 VSS_10 VDD_10 V1 FBA_D14 B2 DQ0_A FBA_D22 V3 DQ2_B FBA_CMD10 J5 CA9_A
D12 VSS_11 VDD_11 V14 FBA_D15 E2 DQ3_A FBA_D16 U4 DQ1_B FBA_CMD14 G10 CABI_n_A
D14 VSS_12 VDD_12 FBA_D13 A3 DQ5_A FBA_D17 U2 DQ0_B CKE_n_A
D3 VSS_13 DQ1_A DQ3_B N5
E11 VSS_14 FBA_EDC1 C2 FBA_EDC2 T2 TCK
VSS_15 FBVDDQ 30 FBA_EDC1 FBA_DBI1_N EDC0_A 30 FBA_EDC2 FBA_DBI2_N EDC0_B
E4 D2 R2 F10
VSS_16 30 FBA_DBI1_N DBI0_n_A 30 FBA_DBI2_N DBI0_n_B TDI
F1 N10
F12 VSS_17 FBA_WCKB01_P D4 FBA_WCK23_P R4 TDO
VSS_18 30 FBA_WCKB01_P FBA_WCKB01_N WCK_t_A 30 FBA_WCK23_P FBA_WCK23_N NC3
F14 B10 D5 R5 F5
VSS_19 VDDQ_1 30 FBA_WCKB01_N WCK_c_A 30 FBA_WCK23_N NC4 FBA_CMD5 TMS
F3 B5 L3
VSS_20 VDDQ_2 30 FBA_D[24..31] FBA_D26 FBA_CMD18 CA0_B
G1 C1 P13 M11
VSS_21 VDDQ_3 30 FBA_D[0..7] FBA_D30 DQ13_B FBA_CMD7 CA1_B
G12 C11 x16 x8 U13 M4
G14 VSS_22 VDDQ_4 C14 FBA_D6 B11 FBA_D24 M13 DQ11_B FBA_CMD20 L12 CA2_B
NC
G3 VSS_23 VDDQ_5 C4 FBA_D3 G13 DQ8_A FBA_D31 N13 DQ15_B FBA_CMD8 L5 CA3_B
VSS_24 VDDQ_6 FBA_D2 DQ15_A NC BYTE3 FBA_D28 DQ14_B FBA_CMD16 CA4_B
H11 E1 E13 NC U12 L10
H4 VSS_25 VDDQ_7 E14 FBA_D0 F13 DQ13_A FBA_D27 P12 DQ10_B FBA_CMD21 K12 CA5_B
NC
L11 VSS_26 VDDQ_8 F11 FBA_D1 E12 DQ14_A FBA_D29 V12 DQ12_B FBA_CMD19 K11 CA6_B
VSS_27 VDDQ_9 BYTE0 FBA_D5 DQ12_A NC
FBA_D25 DQ9_B FBA_CMD6 CA7_B
L4 F4 B12 NC U11 K4
M1 VSS_28 VDDQ_10 H1 FBA_D7 B13 DQ10_A DQ8_B FBA_CMD4 K3 CA8_B
NC
M12 VSS_29 VDDQ_11 H14 FBA_D4 A12 DQ11_A FBA_EDC3 T13 FBA_CMD9 K5 CA9_B J14FBA_ZQ_1_A RG1290 1 OPT@ 2 121_0402_1%
NC
VSS_30 VDDQ_12 DQ9_A 30 FBA_EDC3 FBA_DBI3_N EDC1_B FBA_CMD17 CABI_n_B ZQ_A
M14 J13 R13 M10
VSS_31 VDDQ_13 FBA_EDC0 30 FBA_DBI3_N DBI1_n_B CKE_n_B
M3 J2 C13 GND K14FBA_ZQ_1_B RG1122 1 OPT@ 2 121_0402_1%
VSS_32 VDDQ_14 30 FBA_EDC0 FBA_DBI0_N EDC1_A FBA_WCKB23_P R11 ZQ_B
N1 K13 D13
VSS_33 VDDQ_15 30 FBA_DBI0_N DBI1_n_A NC 30 FBA_WCKB23_P FBA_WCKB23_N R10 WCK_t_B
N12 K2
VSS_34 VDDQ_16 FBA_WCK01_P 30 FBA_WCKB23_N WCK_c_B
N14 L1 D11 NC
VSS_35 VDDQ_17 30 FBA_WCK01_P FBA_WCK01_N NC1
N3 L14 D10 NC
VSS_36 VDDQ_18 30 FBA_WCK01_N NC2 FBA_CMD3
P11 N11 J1
VSS_37 VDDQ_19 RESET_n
P4 N4 MT61K256M32JE-14-A_FBGA180
R1 VSS_38 VDDQ_20 P1 MT61K256M32JE-14-A_FBGA180
VSS_39 VDDQ_21 @
R12 P14 @
R14 VSS_40 VDDQ_22 T1 FBA_CLK0_N K10
VSS_41 VDDQ_23 30 FBA_CLK0_N CK_c
R3 T11 FBA_CLK0_P J10
T10
T12
T3
T5
VSS_42
VSS_43
VSS_44
VSS_45
VDDQ_24
VDDQ_25
VDDQ_26
VDDQ_27
T14
T4
U10
U5
follow CRB bit swap 30 FBA_CLK0_P CK_t
NC5
NC6
G5
M5
C C
U1 VSS_46 VDDQ_28
U14 VSS_47
V11 VSS_48
V13 VSS_49 +1.8VS_AON
V4 VSS_51 4 x 0402 1 uF
VSS_52 CLOSE TO DRAM
MT61K256M32JE-14-A_FBGA180
A10
VPP_1 @
A5
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
VPP_2 V10
VPP_3 1 1 1 1
V5
VPP_4
OPT@
OPT@
OPT@
OPT@
2 2 2 2
CG2052
CG2053
CG2054
CG2055
FBVDDQ
1
RG97
1/16W_549_1%_0402
@
1 x POSCAP 330 uF
2
FBVDDQ 6 x 0603 22uF 4 x 0603 10uF +FBA_VREFC_R 1 @ 2 +FBA_VREFC
2 x 0603 10uF +FBA_VREFC 37
AROUND DRAM CLOSE TO DRAM RG1291 16 mil
1
931_0402_1% 1
RG99 CG1521
22U_6.3V_M_X6S_0603
22U_6.3V_M_X6S_0603
22U_6.3V_M_X6S_0603
22U_6.3V_M_X6S_0603
22U_6.3V_M_X6S_0603
22U_6.3V_M_X6S_0603
1 1K_0402_1% 820P_0402_25V7
10U_10V_M_X6S_0603
10U_10V_M_X6S_0603
10U_10V_M_X6S_0603
10U_10V_M_X6S_0603
10U_10V_M_X6S_0603
10U_10V_M_X6S_0603
330U_B2_2.5VM_R9M
1
1 1 1 1 1 1 1 1 1 1 1 1 N18P@ @
+ 2
2
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
@
2
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
QG48
B 2 2 2 2 2 2 2 2 2 2 2 2 2 31,50 MEM_VREF_CTL B
LSI1012XT1G_SC-89-3
@
CG675
CG1939
CG1940
CG1941
CG1942
CG1943
CG1944
CG1699
CG1700
CG1635
CG1636
CG1637
CG1638
3
Vgs(th)≤0.9V VREFC IS NOT USED IN
x16 CONFIGURATION
1K OHM PULL-DOWN IS
IN PLACE OF THE 1.33K
FBVDDQ FOR RV99
CLOSE TO DRAM 18 x 0402 1uF
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
CG2021
CG2035
CG2036
CG2037
CG2038
CG2039
CG2040
CG2041
CG2042
CG2043
CG2044
CG2045
CG2046
CG2047
CG2048
CG2049
CG2050
CG2051
A A
Issued Date 2021/04/07 Deciphered Date 2021/04/07 N18P_GDDR6_A_[31_0]
5 Vinafix.com
4 3
2
Size
C
Date:
Document Number
HY568
1
Sheet 36 of 110
Rev
0.1
5 4 3 2 1
UG5D
? UG5C
? ?
COMMON ?
COMMON
FBVDDQ
30 FBA_CMD[28..52]
UG5A RG1347
UG5B FBA_CMD33 H3 K1 +FBA_B_VREFC 1 2 +FBA_VREFC
FBA_CMD45 CA0_A VREFC +FBA_VREFC 36
A11 A1 NORMAL G11 0_0201_5%
VSS_1 VDD_1 30 FBA_D[32..39] FBA_CMD35 CA1_A
A13 A14 NORMAL G4 N18P@ 1
VSS_2 VDD_2 CA2_A
1
A2 E10 FBA_D36 G2 FBA_CMD46 H12 CG172
VSS_3 VDD_3 FBA_D33 DQ7_A 30 FBA_D[56..63] FBA_CMD36 CA3_A
A4 E5 B3 x16 x8 H5 RG1348 820P_0402_25V7
B1 VSS_4 VDD_4 H13 FBA_D38 F2 DQ2_A FBA_D58 N2 FBA_CMD43 H10 CA4_A 1K_0402_1% @
B14 VSS_5 VDD_5 H2 FBA_D39 E3 DQ6_A FBA_D59 P3 DQ6_B FBA_CMD48 J12 CA5_A GN20@ 2
C10 VSS_6 VDD_6 L13 FBA_D35 B4 DQ4_A FBA_D56 M2 DQ4_B FBA_CMD47 J11 CA6_A
BYTE4
2
C12 VSS_7 VDD_7 L2 FBA_D32 B2 DQ0_A FBA_D62 P2 DQ7_B FBA_CMD34 J4 CA7_A
D VSS_8 VDD_8 FBA_D37 DQ3_A BYTE7 FBA_D60 DQ5_B FBA_CMD32 CA8_A D
C3 P10 E2 U3 J3
C5 VSS_9 VDD_9 P5 FBA_D34 A3 DQ5_A FBA_D61 V3 DQ2_B FBA_CMD37 J5 CA9_A
D1 VSS_10 VDD_10 V1 DQ1_A FBA_D63 U4 DQ1_B FBA_CMD44 G10 CABI_n_A
D12 VSS_11 VDD_11 V14 FBA_EDC4 C2 FBA_D57 U2 DQ0_B CKE_n_A
VSS_12 VDD_12 30 FBA_EDC4 FBA_DBI4_N EDC0_A DQ3_B
D14 D2 N5
VSS_13 30 FBA_DBI4_N DBI0_n_A FBA_EDC7 TCK
D3 T2
VSS_14 FBA_WCK45_P 30 FBA_EDC7 FBA_DBI7_N EDC0_B
E11 D4 R2 F10
E4 VSS_15 FBVDDQ 30 FBA_WCK45_P FBA_WCK45_N D5 WCK_t_A 30 FBA_DBI7_N DBI0_n_B TDI N10
VSS_16 30 FBA_WCK45_N WCK_c_A FBA_WCKB67_P TDO
F1 R4
VSS_17 30 FBA_WCKB67_P FBA_WCKB67_N NC3
F12 R5 F5
VSS_18 30 FBA_D[40..47] 30 FBA_WCKB67_N NC4 FBA_CMD29 TMS
F14 B10 x16 x8 L3
VSS_19 VDDQ_1 FBA_D40 30 FBA_D[48..55] FBA_D50 FBA_CMD52 CA0_B
F3 B5 B11 NC P13 M11
G1 VSS_20 VDDQ_2 C1 FBA_D42 G13 DQ8_A FBA_D55 U13 DQ13_B FBA_CMD40 M4 CA1_B
NC
G12 VSS_21 VDDQ_3 C11 FBA_D45 E13 DQ15_A FBA_D52 M13 DQ11_B FBA_CMD50 L12 CA2_B
NC
G14 VSS_22 VDDQ_4 C14 FBA_D43 F13 DQ13_A FBA_D49 N13 DQ15_B FBA_CMD39 L5 CA3_B
VSS_23 VDDQ_5 BYTE5 FBA_D41 DQ14_A NC BYTE6 FBA_D53 DQ14_B FBA_CMD42 CA4_B
G3 C4 E12 NC U12 L10
H11 VSS_24 VDDQ_6 E1 FBA_D44 B12 DQ12_A FBA_D48 P12 DQ10_B FBA_CMD49 K12 CA5_B
NC
H4 VSS_25 VDDQ_7 E14 FBA_D46 B13 DQ10_A FBA_D51 V12 DQ12_B FBA_CMD51 K11 CA6_B
NC
L11 VSS_26 VDDQ_8 F11 FBA_D47 A12 DQ11_A FBA_D54 U11 DQ9_B FBA_CMD28 K4 CA7_B
NC
L4 VSS_27 VDDQ_9 F4 DQ9_A DQ8_B FBA_CMD30 K3 CA8_B
M1 VSS_28 VDDQ_10 H1 FBA_EDC5 C13 FBA_EDC6 T13 FBA_CMD38 K5 CA9_B J14FBA_ZQ_2_A RG1177 1 OPT@ 2 121_0402_1%
GND
VSS_29 VDDQ_11 30 FBA_EDC5 FBA_DBI5_N EDC1_A 30 FBA_EDC6 FBA_DBI6_N EDC1_B FBA_CMD41 CABI_n_B ZQ_A
M12 H14 D13 R13 M10
VSS_30 VDDQ_12 30 FBA_DBI5_N DBI1_n_A 30 FBA_DBI6_N DBI1_n_B CKE_n_B
M14 J13 NC
K14FBA_ZQ_2_B RG1178 1 OPT@ 2 121_0402_1%
M3 VSS_31 VDDQ_13 J2 FBA_WCKB45_P D11 FBA_WCK67_P R11 ZQ_B
NC
VSS_32 VDDQ_14 30 FBA_WCKB45_P FBA_WCKB45_N D10 NC1 30 FBA_WCK67_P FBA_WCK67_N WCK_t_B
N1 K13 NC R10
VSS_33 VDDQ_15 30 FBA_WCKB45_N NC2 30 FBA_WCK67_N WCK_c_B
N12 K2
N14 VSS_34 VDDQ_16 L1
N3 VSS_35 VDDQ_17 L14 MT61K256M32JE-14-A_FBGA180 FBA_CMD31 J1
P11 N11 @ MT61K256M32JE-14-A_FBGA180
P4 VSS_37 VDDQ_19 N4
VSS_38 VDDQ_20 @
R1 P1
R12 VSS_39 VDDQ_21 P14 FBA_CLK1_N K10
VSS_40 VDDQ_22 30 FBA_CLK1_N CK_c
R14 T1 FBA_CLK1_P J10
R3
T10
T12
T3
VSS_41
VSS_42
VSS_43
VSS_44
VDDQ_23
VDDQ_24
VDDQ_25
VDDQ_26
T11
T14
T4
U10
follow CRB bit swap 30 FBA_CLK1_P CK_t
NC5
NC6
G5
M5
T5 VSS_45 VDDQ_27 U5
C C
U1 VSS_46 VDDQ_28
U14 VSS_47
V11 VSS_48
V4 VSS_51 4 x 0402 1 uF
VSS_52 CLOSE TO DRAM MT61K256M32JE-14-A_FBGA180
@
A10
VPP_1 A5
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
VPP_2 V10
VPP_3 1 1 1 1
V5
VPP_4
OPT@
OPT@
OPT@
OPT@
2 2 2 2
CG2056
CG2057
CG2058
CG2059
1 x POSCAP 330 uF
FBVDDQ 6 x 0603 22uF 4 x 0603 10uF
2 x 0603 10uF
AROUND DRAM CLOSE TO DRAM
22U_6.3V_M_X6S_0603
22U_6.3V_M_X6S_0603
22U_6.3V_M_X6S_0603
22U_6.3V_M_X6S_0603
22U_6.3V_M_X6S_0603
22U_6.3V_M_X6S_0603
1
10U_10V_M_X6S_0603
10U_10V_M_X6S_0603
10U_10V_M_X6S_0603
10U_10V_M_X6S_0603
10U_10V_M_X6S_0603
10U_10V_M_X6S_0603
330U_B2_2.5VM_R9M
1 1 1 1 1 1 1 1 1 1 1 1
+
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
B 2 2 2 2 2 2 2 2 2 2 2 2 2 B
CG1629
CG1945
CG1946
CG1947
CG1948
CG1949
CG1950
CG1695
CG1696
CG1682
CG1683
CG1684
CG1685
FBVDDQ
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
CG2060
CG2061
CG2062
CG2063
CG2064
CG2065
CG2066
CG2067
CG2068
CG2069
CG2070
CG2071
CG2072
CG2073
CG2074
CG2075
CG2076
CG2077
A A
Issued Date 2021/04/07 Deciphered Date 2021/04/07 N18P_GDDR6_A_[63_32]
5 Vinafix.com4 3
2
Size
C
Date:
Document Number
HY568
1
Sheet 37 of 110
Rev
0.1
5 4 3 2 1
UG6D
?
? UG6C
COMMON ?
?
FBVDDQ COMMON
30 FBB_CMD[0..24]
RG1349
A11 A1 UG6B FBB_CMD1 H3 K1 +FBB_A_VREFC 1 2+FBB_VREFC
A13 VSS_1 VDD_1 A14 UG6A FBB_CMD13 G11 CA0_A VREFC 0_0201_5%
A2 VSS_2 VDD_2 E10 NORMAL FBB_CMD12 G4 CA1_A N18P@
VSS_3 VDD_3 CA2_A
1
A4 E5 FBB_CMD24 H12
VSS_4 VDD_4 30 FBB_D[8..15] NORMAL 30 FBB_D[16..23] CA3_A
B1 H13 x16 x8 FBB_CMD11 H5 RG1350
B14 VSS_5 VDD_5 H2 FBB_D10 G2 FBB_D19 N2 FBB_CMD15 H10 CA4_A 1K_0402_1%
C10 VSS_6 VDD_6 L13 FBB_D15 B3 DQ7_A FBB_D17 P3 DQ6_B FBB_CMD22 J12 CA5_A GN20@
D
C12 VSS_7 VDD_7 L2 FBB_D9 F2 DQ2_A FBB_D21 M2 DQ4_B FBB_CMD23 J11 CA6_A D
BYTE1
2
C3 VSS_8 VDD_8 P10 FBB_D12 E3 DQ6_A FBB_D18 P2 DQ7_B FBB_CMD0 J4 CA7_A
VSS_9 VDD_9 FBB_D11 DQ4_A BYTE2 FBB_D20 DQ5_B FBB_CMD2 CA8_A
C5 P5 B4 U3 J3
D1 VSS_10 VDD_10 V1 FBB_D8 B2 DQ0_A FBB_D22 V3 DQ2_B FBB_CMD10 J5 CA9_A
D12 VSS_11 VDD_11 V14 FBB_D14 E2 DQ3_A FBB_D16 U4 DQ1_B FBB_CMD14 G10 CABI_n_A
D14 VSS_12 VDD_12 FBB_D13 A3 DQ5_A FBB_D23 U2 DQ0_B CKE_n_A
D3 VSS_13 DQ1_A DQ3_B N5
E11 VSS_14 FBB_EDC1 C2 FBB_EDC2 T2 TCK
VSS_15 FBVDDQ 30 FBB_EDC1 FBB_DBI1_N EDC0_A 30 FBB_EDC2 FBB_DBI2_N EDC0_B
E4 D2 R2 F10
VSS_16 30 FBB_DBI1_N DBI0_n_A 30 FBB_DBI2_N DBI0_n_B TDI
F1 N10
F12 VSS_17 FBB_WCKB01_P D4 FBB_WCK23_P R4 TDO
VSS_18 30 FBB_WCKB01_P FBB_WCKB01_N WCK_t_A 30 FBB_WCK23_P FBB_WCK23_N NC3
F14 B10 D5 R5 F5
VSS_19 VDDQ_1 30 FBB_WCKB01_N WCK_c_A 30 FBB_WCK23_N NC4 FBB_CMD5 TMS
F3 B5 L3
VSS_20 VDDQ_2 30 FBB_D[24..31] FBB_D26 FBB_CMD18 CA0_B
G1 C1 P13 M11
VSS_21 VDDQ_3 30 FBB_D[0..7] FBB_D29 DQ13_B FBB_CMD7 CA1_B
G12 C11 x16 x8 U13 M4
G14 VSS_22 VDDQ_4 C14 FBB_D0 B11 FBB_D24 M13 DQ11_B FBB_CMD20 L12 CA2_B
VSS_23 VDDQ_5 FBB_D1 DQ8_A NC BYTE3 FBB_D28 DQ15_B FBB_CMD8 CA3_B
G3 C4 G13 NC N13 L5
H11 VSS_24 VDDQ_6 E1 FBB_D6 E13 DQ15_A FBB_D30 U12 DQ14_B FBB_CMD16 L10 CA4_B
NC
H4 VSS_25 VDDQ_7 E14 FBB_D4 F13 DQ13_A FBB_D27 P12 DQ10_B FBB_CMD21 K12 CA5_B
VSS_26 VDDQ_8 BYTE0 FBB_D3 DQ14_A NC
FBB_D25 DQ12_B FBB_CMD19 CA6_B
L11 F11 E12 NC V12 K11
L4 VSS_27 VDDQ_9 F4 FBB_D5 B12 DQ12_A FBB_D31 U11 DQ9_B FBB_CMD6 K4 CA7_B
NC
M1 VSS_28 VDDQ_10 H1 FBB_D2 B13 DQ10_A DQ8_B FBB_CMD4 K3 CA8_B
NC
M12 VSS_29 VDDQ_11 H14 FBB_D7 A12 DQ11_A FBB_EDC3 T13 FBB_CMD9 K5 CA9_B J14FBB_ZQ_1_A RG1179 1 OPT@ 2 121_0402_1%
NC
VSS_30 VDDQ_12 DQ9_A 30 FBB_EDC3 FBB_DBI3_N EDC1_B FBB_CMD17 CABI_n_B ZQ_A
M14 J13 R13 M10
VSS_31 VDDQ_13 FBB_EDC0 30 FBB_DBI3_N DBI1_n_B CKE_n_B
M3 J2 C13 GND K14FBB_ZQ_1_B RG1180 1 OPT@ 2 121_0402_1%
VSS_32 VDDQ_14 30 FBB_EDC0 FBB_DBI0_N EDC1_A FBB_WCKB23_P R11 ZQ_B
N1 K13 D13
VSS_33 VDDQ_15 30 FBB_DBI0_N DBI1_n_A NC 30 FBB_WCKB23_P FBB_WCKB23_N R10 WCK_t_B
N12 K2
VSS_34 VDDQ_16 FBB_WCK01_P 30 FBB_WCKB23_N WCK_c_B
N14 L1 D11 NC
VSS_35 VDDQ_17 30 FBB_WCK01_P FBB_WCK01_N NC1
N3 L14 D10 NC
VSS_36 VDDQ_18 30 FBB_WCK01_N NC2 FBB_CMD3
P11 N11 J1
P4 N4 MT61K256M32JE-14-A_FBGA180
R1 VSS_38 VDDQ_20 P1 MT61K256M32JE-14-A_FBGA180
VSS_39 VDDQ_21 @
R12 P14 @
R14 VSS_40 VDDQ_22 T1 FBB_CLK0_N K10
VSS_41 VDDQ_23 30 FBB_CLK0_N CK_c
R3 T11 FBB_CLK0_P J10
VSS_42 VDDQ_24 30 FBB_CLK0_P CK_t
T10 T14 G5
C
T12
T3
T5
U1
VSS_43
VSS_44
VSS_45
VSS_46
VDDQ_25
VDDQ_26
VDDQ_27
VDDQ_28
T4
U10
U5
follow CRB bit swap NC5
NC6
M5 C
U14 VSS_47
V13 VSS_49
V4 VSS_51 4 x 0402 1 uF
VSS_52 CLOSE TO DRAM
A10
VPP_1 @
A5
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
VPP_2 V10
VPP_3 1 1 1 1
V5
VPP_4
OPT@
OPT@
OPT@
OPT@
2 2 2 2
CG2078
CG2079
CG2080
CG2081
FBVDDQ
1
RG1181
1/16W_549_1%_0402
@
FBVDDQ 1 x POSCAP 330 uF 4 x 0603 10uF
2
6 x 0603 22uF +FBB_VREFC_R 1 2 +FBB_VREFC
AROUND DRAM 2 x 0603 10uF CLOSE TO DRAM +FBB_VREFC 39
RG1182 16 mil
1
931_0402_1% 1
22U_6.3V_M_X6S_0603
22U_6.3V_M_X6S_0603
22U_6.3V_M_X6S_0603
22U_6.3V_M_X6S_0603
22U_6.3V_M_X6S_0603
22U_6.3V_M_X6S_0603
1 @ RG1183 CG1973
10U_10V_M_X6S_0603
10U_10V_M_X6S_0603
10U_10V_M_X6S_0603
10U_10V_M_X6S_0603
10U_10V_M_X6S_0603
10U_10V_M_X6S_0603
330U_B2_2.5VM_R9M
1 1 1 1 1 1 1 1 1 1 1 1 1K_0402_1% 820P_0402_25V7
1
+ N18P@ @
2
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
2
@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
B 2 2 2 2 2 2 2 2 2 2 2 2 2 B
2 QG33
31,50 MEM_VREF_CTL
LSI1012XT1G_SC-89-3
CG676
CG1951
CG1952
CG1953
CG1954
CG1955
CG1956
CG1697
CG1698
CG1686
CG1687
CG1688
CG1689
3
Vgs(th)≤0.9V VREFC IS NOT USED IN
x16 CONFIGURATION
1K OHM PULL-DOWN IS
IN PLACE OF THE 1.33K
FOR RV1183
FBVDDQ
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
CG2082
CG2083
CG2084
CG2085
CG2086
CG2087
CG2088
CG2089
CG2090
CG2091
CG2092
CG2093
CG2094
CG2095
CG2096
CG2097
CG2098
CG2099
A A
Issued Date 2021/04/07 Deciphered Date 2021/04/07 N18P_GDDR6_B_[31_0]
5
Vinafix.com4 3
2
Size
C
Date:
Document Number
HY568
1
Sheet 38 of 110
Rev
0.1
5 4 3 2 1
UG7D UG7C
? ?
? ?
COMMON COMMON
FBVDDQ 30 FBB_CMD[28..52]
RG1351
FBB_CMD33 H3 K1 +FBB_B_VREFC 1 2 +FBB_VREFC
FBB_CMD45 CA0_A VREFC +FBB_VREFC 38
UG7B G11 0_0201_5%
A11 A1 UG7A FBB_CMD35 G4 CA1_A N18P@
VSS_1 VDD_1 CA2_A 1
1
A13 A14 NORMAL FBB_CMD46 H12 CG743
A2 VSS_2 VDD_2 E10 FBB_CMD36 H5 CA3_A RG1352 820P_0402_25V7
VSS_3 VDD_3 30 FBB_D[32..39] NORMAL 30 FBB_D[56..63] CA4_A
A4 E5 x16 x8 FBB_CMD43 H10 1K_0402_1% @
B1 VSS_4 VDD_4 H13 FBB_D32 G2 FBB_D60 N2 FBB_CMD48 J12 CA5_A GN20@ 2
B14 VSS_5 VDD_5 H2 FBB_D37 B3 DQ7_A FBB_D56 P3 DQ6_B FBB_CMD47 J11 CA6_A
2
C10 VSS_6 VDD_6 L13 FBB_D33 F2 DQ2_A FBB_D59 M2 DQ4_B FBB_CMD34 J4 CA7_A
D
C12 VSS_7 VDD_7 L2 FBB_D39 E3 DQ6_A FBB_D57 P2 DQ7_B FBB_CMD32 J3 CA8_A D
VSS_8 VDD_8 BYTE4 FBB_D38 DQ4_A BYTE7 FBB_D61 DQ5_B FBB_CMD37 CA9_A
C3 P10 B4 U3 J5
C5 VSS_9 VDD_9 P5 FBB_D34 B2 DQ0_A FBB_D58 V3 DQ2_B FBB_CMD44 G10 CABI_n_A
D1 VSS_10 VDD_10 V1 FBB_D36 E2 DQ3_A FBB_D63 U4 DQ1_B CKE_n_A
D12 VSS_11 VDD_11 V14 FBB_D35 A3 DQ5_A FBB_D62 U2 DQ0_B N5
D14 VSS_12 VDD_12 DQ1_A DQ3_B TCK
D3 VSS_13 FBB_EDC4 C2 FBB_EDC7 T2 F10
VSS_14 30 FBB_EDC4 FBB_DBI4_N EDC0_A 30 FBB_EDC7 FBB_DBI7_N EDC0_B TDI
E11 D2 R2 N10
VSS_15 FBVDDQ 30 FBB_DBI4_N DBI0_n_A 30 FBB_DBI7_N DBI0_n_B TDO
E4
F1 VSS_16 FBB_WCK45_P D4 FBB_WCKB67_P R4 F5
VSS_17 30 FBB_WCK45_P FBB_WCK45_N WCK_t_A 30 FBB_WCKB67_P FBB_WCKB67_N NC3 FBB_CMD29 TMS
F12 D5 R5 L3
VSS_18 30 FBB_WCK45_N WCK_c_A 30 FBB_WCKB67_N NC4 FBB_CMD52 CA0_B
F14 B10 M11
VSS_19 VDDQ_1 30 FBB_D[48..55] FBB_D52 FBB_CMD40 CA1_B
F3 B5 P13 M4
VSS_20 VDDQ_2 30 FBB_D[40..47] FBB_D50 DQ13_B FBB_CMD50 CA2_B
G1 C1 x16 x8 U13 L12
G12 VSS_21 VDDQ_3 C11 FBB_D41 B11 FBB_D49 M13 DQ11_B FBB_CMD39 L5 CA3_B
NC
G14 VSS_22 VDDQ_4 C14 FBB_D43 G13 DQ8_A FBB_D54 N13 DQ15_B FBB_CMD42 L10 CA4_B
VSS_23 VDDQ_5 FBB_D46 DQ15_A NC BYTE6 FBB_D51 DQ14_B FBB_CMD49 CA5_B
G3 C4 BYTE5 E13 NC U12 K12
H11 VSS_24 VDDQ_6 E1 FBB_D45 F13 DQ13_A FBB_D55 P12 DQ10_B FBB_CMD51 K11 CA6_B
NC
H4 VSS_25 VDDQ_7 E14 FBB_D40 E12 DQ14_A FBB_D48 V12 DQ12_B FBB_CMD28 K4 CA7_B
NC
L11 VSS_26 VDDQ_8 F11 FBB_D42 B12 DQ12_A FBB_D53 U11 DQ9_B FBB_CMD30 K3 CA8_B
NC
L4 VSS_27 VDDQ_9 F4 FBB_D47 B13 DQ10_A DQ8_B FBB_CMD38 K5 CA9_B J14FBB_ZQ_2_A RG1184 1 OPT@ 2 121_0402_1%
NC
M1 VSS_28 VDDQ_10 H1 FBB_D44 A12 DQ11_A FBB_EDC6 T13 FBB_CMD41 M10 CABI_n_B ZQ_A
NC
VSS_29 VDDQ_11 DQ9_A 30 FBB_EDC6 FBB_DBI6_N EDC1_B CKE_n_B
M12 H14 R13 K14FBB_ZQ_2_B RG1185 1 OPT@ 2 121_0402_1%
VSS_30 VDDQ_12 FBB_EDC5 30 FBB_DBI6_N DBI1_n_B ZQ_B
M14 J13 C13 GND
VSS_31 VDDQ_13 30 FBB_EDC5 FBB_DBI5_N EDC1_A FBB_WCK67_P
M3 J2 D13 R11
VSS_32 VDDQ_14 30 FBB_DBI5_N DBI1_n_A NC 30 FBB_WCK67_P FBB_WCK67_N WCK_t_B
N1 K13 R10
VSS_33 VDDQ_15 FBB_WCKB45_P D11 30 FBB_WCK67_N WCK_c_B
N12 K2 NC
VSS_34 VDDQ_16 30 FBB_WCKB45_P FBB_WCKB45_N D10 NC1 FBB_CMD31
N14 L1 NC J1
VSS_35 VDDQ_17 30 FBB_WCKB45_N NC2 RESET_n
N3 L14
P11 VSS_36 VDDQ_18 N11 MT61K256M32JE-14-A_FBGA180
P4 VSS_37 VDDQ_19 N4 MT61K256M32JE-14-A_FBGA180
VSS_38 VDDQ_20 @
R1 P1 FBB_CLK1_N K10
VSS_39 VDDQ_21 @ 30 FBB_CLK1_N CK_c
R12 P14 FBB_CLK1_P J10
VSS_40 VDDQ_22 30 FBB_CLK1_P CK_t
R14 T1 G5
R3
T10
T12
T3
VSS_41
VSS_42
VSS_43
VSS_44
VDDQ_23
VDDQ_24
VDDQ_25
VDDQ_26
T11
T14
T4
U10
follow CRB bit swap NC5
NC6
M5
C C
T5 VSS_45 VDDQ_27 U5
U1 VSS_46 VDDQ_28
U14 VSS_47
V11 VSS_48
VSS_51 MT61K256M32JE-14-A_FBGA180
V4 CLOSE TO DRAM 4 x 0402 1 uF
VSS_52 @
A10
VPP_1 A5
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
VPP_2 V10
VPP_3 1 1 1 1
V5
VPP_4
OPT@
OPT@
OPT@
OPT@
2 2 2 2
CG2100
CG2101
CG2102
CG2103
1 x POSCAP 330 uF
FBVDDQ 6 x 0603 22uF 4 x 0603 10uF
2 x 0603 10uF
AROUND DRAM CLOSE TO DRAM
22U_6.3V_M_X6S_0603
22U_6.3V_M_X6S_0603
22U_6.3V_M_X6S_0603
22U_6.3V_M_X6S_0603
22U_6.3V_M_X6S_0603
22U_6.3V_M_X6S_0603
1
10U_10V_M_X6S_0603
10U_10V_M_X6S_0603
10U_10V_M_X6S_0603
10U_10V_M_X6S_0603
10U_10V_M_X6S_0603
10U_10V_M_X6S_0603
330U_B2_2.5VM_R9M
1 1 1 1 1 1 1 1 1 1 1 1
+
B B
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
2 2 2 2 2 2 2 2 2 2 2 2 2
CG1630
CG1957
CG1958
CG1959
CG1960
CG1961
CG1962
CG1701
CG1702
CG1690
CG1691
CG1692
CG1693
FBVDDQ
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1U_6.3V_K_X6S_0402
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
CG2104
CG2105
CG2106
CG2107
CG2108
CG2109
CG2110
CG2111
CG2112
CG2113
CG2114
CG2115
CG2116
CG2117
CG2118
CG2119
CG2120
CG2121
A A
Issued Date 2021/04/07 Deciphered Date 2021/04/07 N18P_GDDR6_B_[63_32]
5
Vinafix.com
4 3
2
Size
C
Date:
Document Number
HY568
1
Sheet 39 of 110
Rev
0.1
5 4 3 2 1
+1.8VS VDD33
1.2V_MUX VDD12
VDD33 +3VS
2
VDD33
RV852 LV111 1 2 BLM15PX800SN1D_2P
RV121 1 @ 2 0_5%_0603 VDD33 @ RV51 @ 0_0201_5%
0_0201_5%
CV67
CV72
CV68
CV71
0.1u_0201_10V6K
0.01U_0201_10V6K
0.01U_0201_10V6K
1
VDD12
CV200
CV201
CV202
CV203
0.1u_0201_10V6K
0.1u_0201_10V6K
0.01U_0201_10V6K
0.01U_0201_10V6K
VDD33
2 1 1 2
0.1u_0201_10V6K
CPU_EDP_TX0_P CV47 1 2 0.1u_0201_10V6K CPU_EDP_TX0_C_P VDD12
11 CPU_EDP_TX0_P 2 1 1 2
CPU_EDP_TX0_N CV48 1 2 0.1u_0201_10V6K CPU_EDP_TX0_C_N
11 CPU_EDP_TX0_N 1 2 2 1
CPU_EDP_TX1_P CV52 1 2 0.1u_0201_10V6K CPU_EDP_TX1_C_P 1 2 2 1
11 CPU_EDP_TX1_P
eDP MUX
CPU_EDP_TX1_N CV50 1 2 0.1u_0201_10V6K CPU_EDP_TX1_C_N Place near to PIN 60,21,49,26 HY568:SA0000BCH00 (PS8361QFN66GTR) HY568P/
11 CPU_EDP_TX1_N Place near to PIN 60,21,49,26
Y760:SA0000AQK10 (PS8461EQFN66GTR)
32
56
42
55
43
29
24
2
1
D CPU_EDP_TX2_P CPU_EDP_TX2_C_P D
CV55 1 2 0.1u_0201_10V6K UV12
11 CPU_EDP_TX2_P
VDD_DDC
VDD12_1
VDD12_2
VDDTX12_1
VDDTX12_2
VDDA12
VDD33_1
VDD33_2
VDDRX12_1
VDDRX12_2
CPU_EDP_TX2_N CV56 1 2 0.1u_0201_10V6K CPU_EDP_TX2_C_N
11 CPU_EDP_TX2_N
CPU_EDP_TX3_P CV53 1 2 0.1u_0201_10V6K CPU_EDP_TX3_C_P
11 CPU_EDP_TX3_P CPU_EDP_TX0_C_P MUX_EDP_TX0_P
4 54
CPU_EDP_TX3_N CV54 1 2 0.1u_0201_10V6K CPU_EDP_TX3_C_N CPU_EDP_TX0_C_N 5 IN1_D0p OUT_D0p 53 MUX_EDP_TX0_N
11 CPU_EDP_TX3_N CPU_EDP_TX1_C_P IN1_D0n OUT_D0n MUX_EDP_TX1_P
7 51
CPU_EDP_TX1_C_N 8 IN1_D1p OUT_D1p 50 MUX_EDP_TX1_N
CPU_EDP_AUXP CV49 1 2 0.1u_0201_10V6K CPU_EDP_AUX_C_P CPU_EDP_TX2_C_P 10 IN1_D1n OUT_D1n 48 MUX_EDP_TX2_P
11 CPU_EDP_AUXP CPU_EDP_TX2_C_N IN1_D2p OUT_D2p MUX_EDP_TX2_N
11 47
CPU_EDP_AUXN CV51 1 2 0.1u_0201_10V6K CPU_EDP_AUX_C_N CPU_EDP_TX3_C_P 12 IN1_D2n OUT_D2n 45 MUX_EDP_TX3_P
11 CPU_EDP_AUXN CPU_EDP_TX3_C_N IN1_D3p OUT_D3p MUX_EDP_TX3_N
13 44
CPU_EDP_AUX_C_P 62 IN1_D3n OUT_D3n 57 MUX_EDP_AUXN
CPU_EDP_AUX_C_N 61 IN1_AUXp DP_AUXn_SDA 58 MUX_EDP_AUXP
65 IN1_AUXn DP_AUXp_SCL 49 EDP_HPD
IN1_SDA OUT_HPD EDP_MUX_SW EDP_HPD 47,79
66 9
PCH_EDP_HPD RV102 1 @ 2 0_0201_5% IN1_HPD 16 IN1_SCL SW 28 MUX_CFG0
18 PCH_EDP_HPD GPU_EDP_TX0_C_P IN1_HPD CFG0 MUX_CFG1
14 27
GPU_EDP_TX0_P CV57 1 2 0.1u_0201_10V6K GPU_EDP_TX0_C_P GPU_EDP_TX0_C_N 15 IN2_D0p CFG1 26 MUX_CFG2
29 GPU_EDP_TX0_P GPU_EDP_TX1_C_P IN2_D0n CFG2 MUX_CFG3
17 25
GPU_EDP_TX0_N CV58 1 2 0.1u_0201_10V6K GPU_EDP_TX0_C_N GPU_EDP_TX1_C_N 18 IN2_D1p CFG3 46 MUX_CFG4
29 GPU_EDP_TX0_N GPU_EDP_TX2_C_P IN2_D1n CFG4 IN1_EQ1
20 41
GPU_EDP_TX1_P CV59 1 2 0.1u_0201_10V6K GPU_EDP_TX1_C_P GPU_EDP_TX2_C_N 21 IN2_D2p IN1_EQ1 40 IN1_EQ0
29 GPU_EDP_TX1_P GPU_EDP_TX3_C_P IN2_D2n IN1_EQ0 IN2_EQ1
22 39
GPU_EDP_TX1_N CV60 1 2 0.1u_0201_10V6K GPU_EDP_TX1_C_N GPU_EDP_TX3_C_N 23 IN2_D3p IN2_EQ1 38 IN2_EQ0
29 GPU_EDP_TX1_N GPU_EDP_AUX_C_P IN2_D3n IN2_EQ0 I2C_CTL_EN
60 6
GPU_EDP_TX2_P CV61 1 2 0.1u_0201_10V6K GPU_EDP_TX2_C_P GPU_EDP_AUX_C_N 59 IN2_AUXp I2C_ADDR 52 CA_DET RV119 1 2 1M_0402_5%
29 GPU_EDP_TX2_P IN2_AUXn DP_CADET MUX_REXT RV132 2
63 31 11/20W_4.99K_1%_0201
GPU_EDP_TX2_N CV62 1 2 0.1u_0201_10V6K GPU_EDP_TX2_C_N 64 IN2_SDA REXT 30 MUX_PD RV96 2 @ 1 10K_0201_5%
29 GPU_EDP_TX2_N IN2_HPD IN2_SCL PD# VDD33
19 37 RSV0
GPU_EDP_TX3_P CV63 1 2 0.1u_0201_10V6K GPU_EDP_TX3_C_P RV857 1 @ 2 0_0201_5% TV1 33 IN2_HPD RSV0 36
29 GPU_EDP_TX3_P 20,83,93 PCH_I2C1_SDA CSDA RSV1
RV858 1 @ 2 0_0201_5% TV2 34 35
GPU_EDP_TX3_N GPU_EDP_TX3_C_N 20,83,93 PCH_I2C1_SCL CSCL RSV2
EPAD
CV64 1 2 0.1u_0201_10V6K
29 GPU_EDP_TX3_N MUX_EDP_TX0_P
MUX_EDP_TX0_P 47
TV1 1 TV1
GPU_EDP_AUXP CV66 1 2 0.1u_0201_10V6K GPU_EDP_AUX_C_P TV2 1 TV2 PS8461EQFN66GTR-A2_QFN66_5X10 MUX_EDP_TX0_N
29 GPU_EDP_AUXP MUX_EDP_TX0_N 47
67
C @ C
GPU_EDP_AUXN CV65 1 2 0.1u_0201_10V6K GPU_EDP_AUX_C_N MUX_EDP_TX1_P
29 GPU_EDP_AUXN MUX_EDP_TX1_P 47
31,76,79,102 EC_SMB_DA2 RV867 1 @ 2 0_0201_5% TV1
RV868 1 @ 2 0_0201_5% TV2 MUX_EDP_TX1_N
31,76,79,102 EC_SMB_CK2 MUX_EDP_TX1_N 47
Hunk 10/9 : Reserved I2C control EDP MUX MUX_EDP_TX2_P
MUX_EDP_TX2_P 47
MUX_EDP_TX2_N
MUX_EDP_TX2_N 47
+1.8VS_VGA MUX_EDP_TX3_P
MUX_EDP_TX3_P 47
MUX_EDP_TX3_N
PCH_EDP_HPD MUX_EDP_TX3_N 47
RV560 1 2 100K_0402_5%
1
+5VS MUX_EDP_AUXN
MUX_EDP_AUXN 47
RV118
10K_0201_5% MUX_EDP_AUXP
MUX_EDP_AUXP 47
1
MUX_EDP_AUXN RV120 1 2 100K_0201_5% VDD33
2
MUX@ CV259
1U_0402_10V6K MUX_EDP_AUXP RV122 1 2 100K_0201_5%
2 GPU_EDP_HPD
31 GPU_EDP_HPD MUX_CFG1
UV18 MUX@ RV112 1 @ 21/20W_4.7K_5%_0201 VDD33
16
Vcc 4 RV854 1 MUX@ 2 0_0402_5% QV11 MUX_CFG3 RV111 1 @ 21/20W_4.7K_5%_0201
1A MUX_EDP_ENBKL 46,79 VDD33
2 7 RV855 1 MUX@ 2 0_0402_5% MMBT3904WH_SOT323-3
18,46 PCH_EDP_ENBKL 1B1 2A MUX_EDP_ENVDD 46,47
1
GPU_EDP_ENBKL_B 3 9 RV856 1 MUX@ 2 0_0402_5% C GPU_EDP_AUX_C_N RV126 1 @ 2 100K_0201_5%
1B2 3A MUX_INVT_PWM 46,47 IN2_HPD VDD33
5 12 2 RV123 1 2 100K_0201_5% RV124 1 @ 2 0_0201_5%
18,46 PCH_EDP_ENVDD GPU_EDP_ENVDD_B 6 2B1 4A GPU_EDP_AUX_C_P
CV260 B RV127 1 @ 2 100K_0201_5%
2B2
1
11 15 E
18,46 PCH_EDP_PWM
3
3B1 OE
2
GPU_EDP_PWM_B 10 1 EDP_MUX_SW EMC_NS@
3B2 S 1 1
14 RV125 VDD33
2
13 4B1 8 L: B1 470P_0201_25V_X7R_0201 CV74 @ CV75

4B2 GND 100K_0201_5%
17 H:B2 220P_25V_K_X7R_0201 220P_25V_K_X7R_0201
T-PAD 2 2
2
CBT3257ABQ_DHVQFN16_2P5X3P5 RV830
1/20W_4.7K_5%_0201
B B
1
+3VS
RSV0
2
RV831
2
+3VS RV341
MUX@ 1/20W_4.7K_5%_0201
UV15 +3VALW 4.7K_0402_5%
1
1 5 for DDS
1
OE Vcc 08/06
GPU_EDP_PWM 2 EDP_MUX_SW
31 GPU_EDP_PWM IN_A EDP_MUX_SW 46
1
3 4 GPU_EDP_PWM_B RV342
GND OUT_Y GPU_EDP_PWM_B 46 10K_0201_5%
MUX@
3
M74VHC1GT125DF2G_SC70-5 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33

2
1/20W_4.7K_5%_0201
1/20W_4.7K_5%_0201
1/20W_4.7K_5%_0201
1/20W_4.7K_5%_0201
1/20W_4.7K_5%_0201
QV28B
D2
1/20W_4.7K_5%_0201
1/20W_4.7K_5%_0201
1/20W_4.7K_5%_0201
+3VALW_Q 5
RV853
RV116
RV105
RV107
RV109
RV113
RV134
G2 PJT7838_SOT363-6
1
1
1
S2
+3VS @
RV103
UV16 for DDS MUX@ @ @ @ @ @ @ @
4
6
1 5 08/06
2
OE Vcc QV28A
D1
2
GPU_EDP_ENBKL 2 EDP_SW 2 PJT7838_SOT363-6 I2C_CTL_EN MUX_CFG0 MUX_CFG2 MUX_CFG4 IN1_EQ0 IN1_EQ1 IN2_EQ0 IN2_EQ1
31 GPU_EDP_ENBKL IN_A 20,46 EDP_SW G1
RV343
RV108
1/20W_4.7K_5%_0201
3 4 GPU_EDP_ENBKL_B
RV110
RV133
RV135
S1
GND OUT_Y GPU_EDP_ENBKL_B 46
1
1/20W_4.7K_5%_0201
1/20W_4.7K_5%_0201
1/20W_4.7K_5%_0201
1/20W_4.7K_5%_0201
1/20W_4.7K_5%_0201
1/20W_4.7K_5%_0201
RV115
MUX@
RV117
1
M74VHC1GT125DF2G_SC70-5 Vgs(th)≤1.0V @ @ @ @ @ @ @
RV104
1 0_0201_5%
2
+3VS
for DDS
UV17 08/06 RV345 1 @ 2 0_0201_5%
A A
1 5
OE Vcc
GPU_EDP_ENVDD 2
31 GPU_EDP_ENVDD IN_A EDP_SW :Port switching control configuration; Internal pull down
3 4 GPU_EDP_ENVDD_B at ~150KΩ, 3.3V I/O.
GND OUT_Y GPU_EDP_ENVDD_B 46 L: Input Port1 is selected (default)
H: Input Port2 is selected
M74VHC1GT125DF2G_SC70-5
Issued Date 2019/07/02 Deciphered Date 2020/02/24 EDP MUX
5
Vinafix.com
4 3
2
Size
C
Date:
Document Number

HY568
1
Sheet 45 of 110
Rev
1.0
A B C D E
need fine tune RG107 RG108 RG88 BOM structure

new add
+3VS
08/08
08/12 UV7 DDS@
1 5 EDP PWM LOGIC CONTROL
OE Vcc +3VS
PWM_SW_SELECT 2 +3VS
31 PWM_SW_SELECT IN_A
3 4 PWM_SW_SELECT_B
GND OUT_Y 1
DDS@ 1
CV1 CV2
M74VHC1GT125DF2G_SC70-5 1U_0402_10V6K DDS@ 1U_0402_10V6K
UV1 DDS@ 2
1 5 UV2 DDS@ 2
45 GPU_EDP_PWM_B Y1 Vcc EC_EDP_PWM
3 1 5
18,45 PCH_EDP_PWM Y0 EDP_PWM_M 79 EC_EDP_PWM EDP_PWM_M Y1 Vcc
4 3
UV8 DDS@ Z Y0 4 MUX_INVT_PWM_R RV90 1 @ 2 0_0402_5%
1 PWM_SEL PWM_SEL Z MUX_INVT_PWM 45,47 1
1 4 2 6
20,45,46 EDP_SW PWM_SW_SELECT_B IN B OUT Y GND S
2 2 6 PWM_OUT_EN 20,79
IN A 74LVC1G3157GW_SOT363-6 GND S
3 5 +3VS_UV8 RV92 1 @ 2 0_0402_5%
GND Vcc +3VS
S z 74LVC1G3157GW_SOT363-6 VCC: 3V VIH:2V
1 default high
MC74VHC1G32DFT2G_SC70-5 DDS@ H Y1
Discrete mode: EDP_SW 1 CV41 DGPU 08/06
MSHybrid mode: EDP_SW 0 .1U_0402_10V6-K
08/12 2 L Y0
iGPU
+3VS
new add +3VS +3VS
08/12
UV19 DDS@ new add
Co-lay EDP ENVDD LOGIC CONTROL 1
2
1 5 CV43 08/08
OE Vcc @ 1U_0402_10V6K RV84
GPU_MUX_CNTL 2 UV11 @ @ 0_0402_5%
31 GPU_MUX_CNTL IN_A GPU_EDP_ENVDD_B 2
1 5
3 4 GPU_MUX_CNTL_B PCH_EDP_ENVDD 3 Y1 Vcc +3VS
1
GND OUT_Y Y0 4 EDP_ENVDD +3VS
Z
1
2
M74VHC1GT125DF2G_SC70-5 2 6 EDP_MUX_SW DDS@
1
+3VS_UV5
GND S DDS@ CV1542
2
@ CV45 RV85 .1U_0402_10V6-K
2 74LVC1G3157GW_SOT363-6 .1U_0402_10V6-K 10K_0402_5% 2 2
UV10 DDS@ 2 DDS@ RV86
1
1 4 EDP_MUX_SW 10K_0402_5%
20,45,46 EDP_SW IN B OUT Y EDP_MUX_SW 45
5
GPU_MUX_CNTL_B 2 UV5
1
IN A EDP_ENVDD 1
P
3 5 +3VS_UV10RV93 1 @ 2 0_0402_5% B 4 MUX_EDP_ENVDD_R RV87 1 @ 2 0_0402_5%
GND Vcc +3VS Y MUX_EDP_ENVDD 45,47
2
EDP ENVDD LOGIC CONTROL 79 EC_EDP_ENVDD A
G
MC74VHC1G32DFT2G_SC70-5 1 VIH: 2.1V Vil: 0.9V DDS@ MC74VHC1G09DFT2G_SC70-5
3
Voh: 2.9V Vol: 0.1V(Io 50uA)
DDS@ CV42 UV3 DDS@
.1U_0402_10V6-K PCH_EDP_ENVDD 1 4 EDP_ENVDD
18,45 PCH_EDP_ENVDD
2 GPU_EDP_ENVDD_B 2 IN B OUT Y
45 GPU_EDP_ENVDD_B IN A
3 5 +3VS_UV3 RV76 1 @ 2 0_0402_5%
GND Vcc +3VS
MC74VHC1G32DFT2G_SC70-5 1
DDS@ CV3
.1U_0402_10V6-K
2
EDP backlight LOGIC CONTROL

VIH: 2.1V Vil: 0.9V level shift for I2C
Voh: 2.9V Vol: 0.1V(Io 50uA) UV4 DDS@
MC74VHC1G32DFT2G_SC70-5 +1.8VS_VGA +1.8VS_VGA +LCD_VDD
PCH_EDP_ENBKL 1 4 EDP_ENBKL RV346 1 @ 2 0_0402_5%
18,45 PCH_EDP_ENBKL IN B OUT Y MUX_EDP_ENBKL 45,79
2
45 GPU_EDP_ENBKL_B IN A
2
3 +3VS_UV4 3
3 5 RV349 1 @ 2 0_0402_5%
GND Vcc +3VS
1 RV347 RV348
2.2K_0402_5% 2.2K_0402_5%
2
DDS@ CV4 @ @
.1U_0402_10V6-K
G2
G1
1
1
2
I2CB_SCL 4 3 I2CB_SCLA_L 6 1
31 I2CB_SCL S2 D2 D1 S1 GPU_I2CB_SCL 47
+1.8VS_VGA QV37B QV38A

PJT7838_SOT363-6 PJT7838_SOT363-6
+3VS DDS@ DDS@
+1.8VS_VGA
1
5
1
2
DDS@
G1
G2
DDS@ CV5 @ RV80
RV79 .1U_0402_10V6-K 10K_0402_5% I2CB_SDA 1 6 I2CB_SDA_L 3 4
2 31 I2CB_SDA S1 D1 D2 S2 GPU_I2CB_SDA 47
100K_0402_5%
2
2
Vgs(th)≤1.0V
1
QV37A QV38B
PJT7838_SOT363-6 PJT7838_SOT363-6
3 1PCH_ENBKL_R RV350 1 @ 2 0_0402_5% PCH_EDP_ENBKL DDS@ DDS@
31 iGPU_EDP_ENBKL
RV94 1 @ 2 0_0402_5%
QV9
LSI1012XT1G_SC-89-3
DDS@
Vgs(th)≤0.9V
RV95 1 @ 2 0_0402_5%
4 4
Issued Date 2021/04/07 Deciphered Date 2021/04/07 DC V TO VS INTERFACE
A Vinafix.com
B C
D
Custom
Date:
HY568
E
Sheet 46 of 110
Rev
0.1
5 4 3 2 1
+LCD_VDD
LCD POWER CIRCUIT +3VS +3VALW
B+ +LED_VDD +3VS +3VS +3VS_CMOS
W=80mils RV7 1 @ 2 0_0805_5% 2A 80 mil FV3 2A 80 mil

UV9
2
W=80mils 1 2
RV3 1 @ 2 0_0805_5% LCD_VDD_OUT 1 5 LCD_VDD_IN RV4 1 @ 2 0_0805_5% RV789 UV25 Shutter@
OUT IN 4A_32V_ 0497004PKRHF Shutter@ 5 1
1 1 IN OUT
1 1 2 CV14 CV15 100K_0402_5% 2
GND FV3 need changed to SP04000A200 4.7U_0805_25V6K 0.1U_25V_K_X5R_0402 2
1
CV7 CV8 1 @ 2 LCD_VDD_OCB 3 4 CD@ EMC@ GND @ CV543
4.7U_0402_6.3V6M 0.1u_0201_10V6K OCB EN 2 2 4 3 0.047U_0402_16V7K
2 2 78,79 IO_Camera_EN EN OCB 1
RV6 SY6288E1AAC_SOT23-5
D 10K_0402_5% New change D
EMI Request SY6288C20AAC_SOT23-5
45,46 MUX_EDP_ENVDD
1
1
RV1
100K_0402_5% @ CV22
.1U_0402_10V6-K +5VALW JEDP1
2 CVILUX_CF69442D0R0-05-NH
2A 80 mil
2
1
+LED_VDD 1
2
2
1
1A Inrush 2A 3
m
EDP_HPD MUX_INVT_PWM RV70 4 3
+LCD_VDD 4
@ 470_0603_5% 5
6 5
7 6
2
7
1
YLOGO_LED_PWM_CONN EDP_HPD 8
45,79 EDP_HPD BKOFF_N 8
9
QV8 1 79 BKOFF_N MUX_INVT_PWM 9
RV5 RV2 上上 45,46 MUX_INVT_PWM
10
10
100K_0201_5% 100K_0201_5% D LCD_OD_N 11
YLOGO_LED_PWM_R 2 18 LCD_OD_N 11
79 EC_YLOGO_LED_PWM RV71 1 @ 2 @ 12
0.5A
2
12
co
G +3VS_DMIC 13
+3VS_DMIC DMIC_DAT_CON DMIC_DATA_R_CONN 13
0_0402_5% S RV829 1 @ 2 0_0402_5% 14
14
2
PJA138K_SOT23-3 DMIC_CLK_CON RV828 1 @ 2 0_0402_5% DMIC_CLK_R_CONN 15
RV72 3 16 15
@ 100K_0402_5% RV826 1 @ 2 0_0402_5% USB20_6_R_N 17 16
EMI request 17 USB20_6_N
RV827 1 @ 2 0_0402_5% USB20_6_R_P 18 17
17 USB20_6_P 18
0.5A 19
1
C BKOFF_N MUX_INVT_PWM +3VS_CMOS 20 19 C
+3VS_CMOS 20
21
+5VALW_LOGO YLOGO_LED_PWM_CONN 21
22
RV850 1 @ 2 0_0402_5% 23 22
+3VL 23
1
LID_SW_N 24
.
YLOGO_LED_PWM_CONN 78,79,83 LID_SW_N 24
@ CV12 @ CV13 25
470P_0201_25V_X7R_0201 470P_0201_25V_X7R_0201 26 25
2
27 26
ap
46 GPU_I2CB_SDA 27
46 GPU_I2CB_SCL
28
28
1
29
MUX_EDP_AUXN CV1553 1 2 0.1u_0201_10V6K MUX_EDP_AUX_CON_N 30 29
1
45 MUX_EDP_AUXN MUX_EDP_AUXP MUX_EDP_AUX_CON_P 30
1 DV1 CV1554 1 2 0.1u_0201_10V6K 31
45 MUX_EDP_AUXP 31
AZ5725-01F.R7GR_DFN1006P2X2 32
CV102 Cover_LED@ MUX_EDP_TX0_P CV1555 1 2 0.1u_0201_10V6K MUX_EDP_TX0_CON_P 33 32
45 MUX_EDP_TX0_P MUX_EDP_TX0_N MUX_EDP_TX0_CON_N 33
1000P_0402_50V_X7R_0402 CV1556 1 2 0.1u_0201_10V6K 34
DMIC_CLK_R_CONN DMIC_DATA_R_CONN 2 45 MUX_EDP_TX0_N 34
2
Cover_LED@ 35
MUX_EDP_TX1_P CV1557 1 2 0.1u_0201_10V6K MUX_EDP_TX1_CON_P 36 35
45 MUX_EDP_TX1_P
2
MUX_EDP_TX1_N CV1558 1 2 0.1u_0201_10V6K MUX_EDP_TX1_CON_N 37 36
45 MUX_EDP_TX1_N 37
1 1 38
MUX_EDP_TX2_P CV1559 1 2 0.1u_0201_10V6K MUX_EDP_TX2_CON_P 39 38
45 MUX_EDP_TX2_P 39
rL
CV11 CV28 MUX_EDP_TX2_N CV1560 1 2 0.1u_0201_10V6K MUX_EDP_TX2_CON_N 40
100P_50V_J_NPO_0201 10P_50V_D_NPO_0201 45 MUX_EDP_TX2_N 40
41
2 EMC_NS@ 2 EMC_NS@ MUX_EDP_TX3_P CV1561 1 2 0.1u_0201_10V6K MUX_EDP_TX3_CON_P 42 41
45 MUX_EDP_TX3_P MUX_EDP_TX3_N MUX_EDP_TX3_CON_N 42
CV1562 1 2 0.1u_0201_10V6K 43 46
45 MUX_EDP_TX3_N 43 GND2
44 45
44 GND1
ME@
+1.8VS +3VS
ai
B select for LOGO_led PWR +5VALW_LOGO B
06/12 yong
2.2K_0404_4P2R_5%
2.2K_0404_4P2R_5%
100P 25V J NPO 0201
100P 25V J NPO 0201

4
3
4
3
1 1
RV47 1 @ 2 0_0402_5% +3VS +3VS_DMIC +3VS_CMOS
RPV4
CA86
RPV5
+3VALW
CA85
RV48 1 2 1/10W_0_5%_0603
+5VALW 2 2
Cover_LED@
1
2
1
2
RV81 1 @ 2 0_0603_5%
ep RV825 1 17@ 2 1/10W_0_5%_0603
UV201
2
1 8
VCCA VCCB @ CV1552
For EMI CODEC_DMIC_DAT 2 7 DMIC_DAT_CON 0.047U_0402_16V7K
66 CODEC_DMIC_DAT A0 B0 1
EXC24CH900U_4P CODEC_DMIC_CLK 3 6 DMIC_CLK_CON
USB20_6_N USB20_6_R_N 66 CODEC_DMIC_CLK A1 B1
4 3
4 3 4 5 DMIC_OUTPUT_EN RV77 2 @ 1 0_0201_5%
GND OE +1.8VS
USB20_6_P 1 2 USB20_6_R_P
1 2
1
FXMA2102UMX_U-MLP8_1P2X1P4
R
LV1 RV78
EMC@ 100K_0201_5%
2
A A
Issued Date 2019/07/02 Deciphered Date 2020/02/24 eDP/ CMOS/Touch screen
Vinafix.com
Custom
HY568 1.0

5 4 3 2 1
5 4 3 2 1
+5VS_HDMI +1.8VS_VGA
HDMI Power +5VS_HDMI
2
1
1
RV60
10K_0402_5%
+5VS +5VS_HDMI_F +5VS_HDMI RPV501
QV501 2.2K_0404_4P2R_5%
LP2301ALT1G_SOT-23-3 update by bing
FV501
3
4
2
1 3 1 2 JHDMI2 20180316
S
HDMI_DET 19
1 Hot_Plug_Detect IFPC_HPD
1.1A_8V_1206L110THYR 18
+5V_Power 31 IFPC_HPD
CV501 17
Ihold:1.1A,Itrip:2.2A,
G
2
DDPB_DATA_U 16 DDC/CEC_GND
0.1u_0201_10V6K
D
84 SUSP Rmax:0.21ohm 2 DDPB_CLK_U 15 SDA QV4 D
14 SCL MMBT3904WH_SOT323-3
Utility
1
13 20 C
HDMI_CLK_CON_N RV859 1 2 6.8_0201_1% HDMI_CLK_R_CON_N 12 CEC GND1 2 RV58 1 2 100K_0402_5% HDMI_DET
11 TMDS_Clock- 21 B
HDMI_CLK_CON_P RV860 1 2 6.8_0201_1% HDMI_CLK_R_CON_P 10 TMDS_Clock_Shield GND2 E
3
HDMI_TX0_CON_N RV861 1 2 6.8_0201_1% HDMI_TX0_R_CON_N 9 TMDS_Clock+ 22
TMDS_Data0- GND3 1
1
8 CV29
GPU_HDMI_TX0_P CV502 1 2 0.1u_0201_10V6K HDMI_TX0_CON_P HDMI_TX0_CON_P RV862 1 2 6.8_0201_1% HDMI_TX0_R_CON_P 7 TMDS_Data0_Shield 23 RV57 220P_0402_50V7K
29 GPU_HDMI_TX0_P HDMI_TX1_CON_N TMDS_Data0+ GND4
RV863 1 2 6.8_0201_1% HDMI_TX1_R_CON_N 6 100K_0402_5%
GPU_HDMI_TX0_N CV503 1 2 0.1u_0201_10V6K HDMI_TX0_CON_N 5 TMDS_Data1- 2
29 GPU_HDMI_TX0_N HDMI_TX1_CON_P 1 2 6.8_0201_1% HDMI_TX1_R_CON_P 4 TMDS_Data1_Shield
RV864
2
GPU_HDMI_TX1_P CV504 1 2 0.1u_0201_10V6K HDMI_TX1_CON_P HDMI_TX2_CON_N RV865 1 2 6.8_0201_1% HDMI_TX2_R_CON_N 3 TMDS_Data1+
29 GPU_HDMI_TX1_P TMDS_Data2-
2
GPU_HDMI_TX1_N CV505 1 2 0.1u_0201_10V6K HDMI_TX1_CON_N HDMI_TX2_CON_P RV866 1 2 6.8_0201_1% HDMI_TX2_R_CON_P 1 TMDS_Data2_Shield
29 GPU_HDMI_TX1_N TMDS_Data2+
GPU_HDMI_TX2_P CV506 1 2 0.1u_0201_10V6K HDMI_TX2_CON_P ALLTOP-C128DQ-K1939-L
29 GPU_HDMI_TX2_P
ME@
GPU_HDMI_TX2_N CV507 1 2 0.1u_0201_10V6K HDMI_TX2_CON_N
29 GPU_HDMI_TX2_N
GPU_HDMI_CLK_P CV508 1 2 0.1u_0201_10V6K HDMI_CLK_CON_P
29 GPU_HDMI_CLK_P
GPU_HDMI_CLK_N CV509 1 2 0.1u_0201_10V6K HDMI_CLK_CON_N
29 GPU_HDMI_CLK_N
+3VS
HDMI_TX0_CON_P RV504 1 2 1/20W_499_1%_0201 HDMI_TX0_DP_R LV840 1 2 BLM15BD601SN1D_2P
1
HDMI_TX0_CON_N RV505 1 2 1/20W_499_1%_0201 HDMI_TX0_DN_R LV841 1 2 BLM15BD601SN1D_2P
RV666
HDMI_TX1_CON_P RV506 1 2 1/20W_499_1%_0201 HDMI_TX1_DP_R LV842 1 2 BLM15BD601SN1D_2P 1M_0402_5%
HDMI_TX1_CON_N RV507 1 2 1/20W_499_1%_0201 HDMI_TX1_DN_R LV843 1 2 BLM15BD601SN1D_2P
2
HDMI_TX2_CON_P HDMI_TX2_DP_R
G
RV508 1 2 1/20W_499_1%_0201 LV844 1 2 BLM15BD601SN1D_2P
3
HDMI_TX2_CON_N HDMI_TX2_DN_R PCH_HDMI_HPD HDMI_DET
1
RV509 1 2 1/20W_499_1%_0201 LV845 1 2 BLM15BD601SN1D_2P
18 PCH_HDMI_HPD
D
HDMI_CLK_CON_P RV510 1 2 1/20W_499_1%_0201 HDMI_CLK_DP_R LV846 1 2 BLM15BD601SN1D_2P
C HDMI_CLK_CON_N RV511 1 2 1/20W_499_1%_0201 HDMI_CLK_DN_R LV847 1 2 BLM15BD601SN1D_2P QV6 C
1
PJA138K_SOT23-3
1
RV503
RV849 1 @ 2 0_0402_5% QV504 100K_0402_5%
31,102 NVVDD_PWRGD LSI1012XT1G_SC-89-3
RV848 1 @ 2 0_0402_5% 2
31,36,38 MEM_VREF_CTL
2
NV Suggestion RV512 1 @ 2 3 QV504 Max Vgs 0.9V
100K_0402_5%
+1.8VS_VGA +1.8VS_VGA
1
RV42 RV40
@ @
0_0402_5% 0_0402_5%
AUX
2
1
1
NV suggestion
RV56 RV55
10K_0402_5% 10K_0402_5%
2
G1
2
DDPB_DATA_U 6 1
D1 S1 HDMI1_DAT 29
PJT7838_SOT363-6
QV3A
EMC
5
G2
B DDPB_CLK_U 3 4 B
D2 S2 HDMI1_CLK 29
Vgs(th)≤1V PJT7838_SOT363-6
DV501 DV502 QV3B
HDMI_TX1_CON_N 1 10 HDMI_TX1_CON_N HDMI_DET 1 1 10 9 HDMI_DET
Line-1 NC1
HDMI_TX1_CON_P 2 9 HDMI_TX1_CON_P DDPB_CLK_U 2 2 9 8 DDPB_CLK_U
Line-2 NC2
3 8 DDPB_DATA_U 4 4 7 7 DDPB_DATA_U
GND1 GND2
HDMI_TX2_CON_N 4 7 HDMI_TX2_CON_N +5VS_HDMI 5 5 6 6 +5VS_HDMI
Line-3 NC3
HDMI_TX2_CON_P 5 6 HDMI_TX2_CON_P 3 3
Line-4 NC4
EMC_NS@ AZ1023-04F.R7G_DFN2510P10E10 8
EMC_NS@ AZ1045-04F_DFN2510P10E-10-9
DV501 & DV503 Change to SC300005R00
DV503
HDMI_CLK_CON_P 1 10 HDMI_CLK_CON_P
Line-1 NC1
HDMI_CLK_CON_N 2 9 HDMI_CLK_CON_N
Line-2 NC2
3 8
GND1 GND2
HDMI_TX0_CON_P 4 7 HDMI_TX0_CON_P
Line-3 NC3
HDMI_TX0_CON_N 5 6 HDMI_TX0_CON_N
Line-4 NC4
EMC_NS@ AZ1023-04F.R7G_DFN2510P10E10
A A
Issued Date 2019/07/02 Deciphered Date 2020/02/24 HDMI_CONN

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
HY568 1.0
Vinafix.com
5 4 3 2 1
5 4 3 2 1
TBT portA/rear side TABLE I2C Addressing

VCC3_LDO_PDA Master: EC TBTB PORT 0x23
I2C1
Slave: PD TBTC PORT 0x27
1/20W_100K_1%_0201
Master: PMC TBTB PORT 0x23
VBUS_TBTA I2C2
TBTC PORT 0x27
RU3
+3VALW VINA_3V3 Slave: PD
Master: PD TBTB PORT T.B.D.
2
D RU2 1 @ 2 0_5%_0603 I2C3 D
1
TBTC PORT T.B.D.
NSR20F30NXT5G_DSN2-2
2
PDA_ADCIN1 Slave: RT
1
VINA_3V3 VCC3_LDO_PDA CU4
DU1
1/20W_12.1K_1%_0201
4.7U_25V_M_X5R_0402
1
1
2
10U 6.3V M X5R 0402
10U 6.3V M X5R 0402
10U 6.3V M X5R 0402

VCC1V5_LDO_PDA
RU5
2
1 1 1
2
CU1
CU2
CU3
2 2 2
+5VALW
G2
G8
H4
H1
H3
H8
C8
A3
A8
B8
F8
22UC_6.3VC_MC_X5RC_0603
22UC_6.3VC_MC_X5RC_0603
22UC_6.3VC_MC_X5RC_0603
22UC_6.3VC_MC_X5RC_0603
22UC_6.3VC_MC_X5RC_0603
22UC_6.3VC_MC_X5RC_0603
UU125 need verify address
1 1 1 1 1 1
VIN_3V3
LDO_1V5_1
LDO_1V5_2
LDO_3V3
PA_VBUS_1
PA_VBUS_2
PA_VBUS_3
PB_VBUS_1
PB_VBUS_2
PB_VBUS_3
VSYS
CU121
CU122
CU6
CU7
CU8
CU9
A7
2 2 2 2 2 2 B7 PP5V_1 VCC3_LDO_PDA
C7 PP5V_2
PP5V_3 TBTA_CC1 53
D7 EC
PP5V_4 PDA_ADCIN1 TBTA_CC2 53
E7 G4
C F7 PP5V_5 ADCIN1 EC_I2C_INT4_PDA_N RU10 1 @ 2 10K_0201_5% C
PP5V_6
220P_25V_K_X7R_0201
220P_25V_K_X7R_0201
G7
H7 PP5V_7 G3
PP5V_8 ADCIN2 VCC3_LDO_PDA 1 1
@
PD_I2C2_SCL RPU7 1 4 2.2K_0404_4P2R_5%
CU10
CU11
PD_I2C2_SDA 2 3
RU619 1 @ 2 0_0201_5% TBTA_GATE_VSYS_R A4 2 2 PCH
88 TBTA_GATE_VSYS PA_GATE_VSYS TBTA_CC1
E8 G5
PA_GATE_VBUS PA_CC1 H5 TBTA_CC2 PCH_PMC_ALERT_PD_NRU11 1 @ 2 10K_0201_5%
PA_CC2
B5 PD1_B_CC1
B4 PB_CC1 A5 PD1_B_CC2
D8 PB_GATE_VSYS PB_CC2 TBTA_I2C_SCL RPU2 1 4 2.2K_0404_4P2R_5%
PB_GATE_VBUS TBTA_I2C_SDA 2 3
BB Retimer
TBTA_I2C_INT_N RU12 1 2 10K_0201_5%

TBTA_RESET_N RU16 1 @ 2 0_0201_5% PD_TBTA_RESET_N C1 D1 EC_I2C_INT4_N_PDA_R RU15 1 @ 2 0_0201_5% EC_I2C_INT4_PDA_N
52 TBTA_RESET_N GPIO0 I2C_EC_IRQ# EC_I2C_INT4_PDA_N 79
RU622 1 @ 2 0_0201_5% PDA_PM_SLP_S4_N G1 E1 EC_SMB_CK4_PDA_R RU17 1 @ 2 0_0201_5% EC_SMB_CK4_PD EC
21,79 PM_SLP_S4_N GPIO1 I2C_EC_SCL EC_SMB_CK4_PD 79 Slave
F1 EC_SMB_DA4_PDA_R RU18 1 @ 2 0_0201_5% EC_SMB_DA4_PD PD1_B_CC1 RU634 1 @ 2 0_0201_5%
TBTA_PWR_EN PD_TBTA_PWR_EN I2C_EC_SDA EC_SMB_DA4_PD 54,79 PD1_B_CC2
RU23 1 @ 2 0_0201_5% A6 RU635 1 @ 2 0_0201_5%
52 TBTA_PWR_EN GPIO2
RU620 1 @ 2 0_0201_5% PD_ACK_SNK1_R H6
88 PD_ACK_SNK1 GPIO3 PMC_ALERT_PDA_N PCH_PMC_ALERT_PD_N
F2 RU21 1 @ 2 0_0201_5%
USB_OC4_N USB_OC4_R_N I2C2S_IRQ# PCH_PMC_ALERT_PD_N 18,20
18 USB_OC4_N RU26 1 @ 2 0_0201_5% B3
GPIO4 E2 SML1_CLK_R_PDA RU22 1 @ 2 0_0201_5% PD_I2C2_SCL PCH SML1
I2C2S_SCL PD_I2C2_SCL 20 Slave
C2 D2 SML1_DATA_R_PDA RU24 1 @ 2 0_0201_5% PD_I2C2_SDA
GPIO5 I2C2S_SDA PD_I2C2_SDA 20,54
RU28 1 @ 2 0_0201_5% GPPC_B2_VRALERT_A_N F6
B 20 GPPC_B2_VRALERT_N GPIO6 B
G6 B1 TBTA_I2C_INT_R_N RU27 1 @ 2 0_0201_5% TBTA_I2C_INT_N
GPIO7 I2C3M_IRQ# TBTA_I2C_INT_N 52
B6 A2 TBTA_I2C_SCL_R RU29 1 @ 2 0_0201_5% TBTA_I2C_SCL BB retimer
GPIO8 I2C3M_SCL TBTA_I2C_SCL 52 Master
A1 TBTA_I2C_SDA_R RU30 1 @ 2 0_0201_5% TBTA_I2C_SDA
TBTA_FORCE_PWR_R I2C3M_SDA_1 TBTA_I2C_SDA 52
20,52 TBTA_FORCE_PWR RU31 1 @ 2 0_0201_5% C6 B2
GPIO9 I2C3M_SDA_2
GND
SN2001024YGBR_DSBGA50
H2
A A

S540-TGL
Custom 0.1
TYPEC_Controller_PortA
5
Vinafix.com 4 3
2
1
Sheet 51 of 110
5 4 3 2 1
Burnside Bridge Re-Timer UU3D Y
TCP0_CTX_DRX0_P CU802 1 2 0.22U_6.3V_K_X5R_0201 TCP0_CTX_C_DRX0_P J1

TBT PORTS J12 TBTA_RX0_P
VCC3_BB_SPIA
+3VALW
12 TCP0_CTX_DRX0_P TCP0_CTX_DRX0_N TCP0_CTX_C_DRX0_N ASSRXp1 BSSRXp1 TBTA_RX0_N TBTA_RX0_P 53 TBTA_SPI_MISO
CU803 1 2 0.22U_6.3V_K_X5R_0201 J2 J11 RU73 1 2 1/20W_2.2K_5%_0201
12 TCP0_CTX_DRX0_N ASSRXn1 BSSRXn1 TBTA_RX0_N 53 TBTA_SPI_CS_N TBTA_FLASH_BUSY_N
RU74 1 2 1/20W_2.2K_5%_0201 RU44 1 2 10K_0201_5% FLASH_BUSY# should be shared between BBR#1 and
Port B - TypeC Side

TCP0_CRX_DTX0_P CU15 1 2 0.22U_6.3V_K_X5R_0201 TCP0_CRX_C_DTX0_P G1 G12 TBTA_TX0_P TBTA_SPI_WP_N RU75 1 2 1/20W_3.3K_5%_0201 RU45 1 @ 2 10K_0201_5%
12 TCP0_CRX_DTX0_P TBTA_TX0_P 53 BBR#2 with PU to PW_VCC3v3_SX_SYS
Port A - Host Side

TCP0_CRX_DTX0_N CU16 1 2 0.22U_6.3V_K_X5R_0201 TCP0_CRX_C_DTX0_N G2 ASSTXp1 BSSTXp1 G11 TBTA_TX0_N TBTA_SPI_HOLD_N RU77 1 2 1/20W_3.3K_5%_0201
12 TCP0_CRX_DTX0_N ASSTXn1 BSSTXn1 TBTA_TX0_N 53
TCP0_CTX_DRX1_P CU790 1 2 0.22U_6.3V_K_X5R_0201 TCP0_CTX_C_DRX1_P C1 C12 TBTA_RX1_P
12 TCP0_CTX_DRX1_P TCP0_CTX_DRX1_N TCP0_CTX_C_DRX1_N ASSRXp2 BSSRXp2 TBTA_RX1_N TBTA_RX1_P 53
CU791 1 2 0.22U_6.3V_K_X5R_0201 C2 C11
12 TCP0_CTX_DRX1_N ASSRXn2 BSSRXn2 TBTA_RX1_N 53 +3VS
TCP0_CRX_DTX1_P CU17 1 2 0.22U_6.3V_K_X5R_0201 TCP0_CRX_C_DTX1_P E1 E12 TBTA_TX1_P
12 TCP0_CRX_DTX1_P TCP0_CRX_DTX1_N TCP0_CRX_C_DTX1_N ASSTXp2 BSSTXp2 TBTA_TX1_N TBTA_TX1_P 53 BB_TBTA_GPIO_6
POC_GPIO6:
CU18 1 2 0.22U_6.3V_K_X5R_0201 E2 E11 RU47 1 2 10K_0201_5% Indication to S0 state for Re-timer
12 TCP0_CRX_DTX1_N ASSTXn2 BSSTXn2 TBTA_TX1_N 53 +3VALW VCC3_BB_SPIA RU48 1 @ 2 10K_0201_5%
TBT0_LSX0_TXD RU630 1 @ 2 0_0201_5% TBT0_LSX0_TXD_R M7 M10 TBTA_SBU1
20 TBT0_LSX0_TXD TBT0_LSX0_RXD TBT0_LSX0_RXD_R PA_LSTX_SBU1 B_SBU1 TBTA_SBU2 TBTA_SBU1 53
RU631 1 @ 2 0_0201_5% L7 L10 CU19
20 TBT0_LSX0_RXD PA_LSRX_SBU2 B_SBU2 TBTA_SBU2 53
RU57 1 @ 2 0_0402_5% 1 2
D TCP0_AUX_P RU50 1 @ 2 0_0201_5% TCP0_AUX_P_R L8 D
12 TCP0_AUX_P TCP0_AUX_N TCP0_AUX_N_R PA_AUX_P 3VALW_TBTA
RU51 1 @ 2 0_0201_5% M8 0.1U_6.3V_K_X5R_0201
12 TCP0_AUX_N PA_AUX_N
BB_FORCE_PWR:
1/20W_1M_1%_0201
1/20W_1M_1%_0201
TBTA_FORCE_PWR RU52 1 @ 2 10K_0201_5%
AC coupling caps and PU/PD on AUX lines Connect to EC/PCH for FW update
1
are implemented inside Burnside Bridge. UU4 RU55 1 2 10K_0201_5% '0' - by default
TBTA_SPI_CS_N 1 8
RU53
RU54
TBTA_SPI_MISO 2 /CS VCC 7 TBTA_SPI_HOLD_N '1' - for debug only/FW update
TBTA_SPI_WP_N 3 DO(IO1) /HOLD(IO3) 6 TBTA_SPI_CLK
@ @ /WP(IO2) CLK 5 TBTA_SPI_MOSI
2
4 DI(IO0) 9 3VALW_TBTA
GND PAD_GND
W25Q80DVZPIG_WSON8_6X5 BB_TBTA_FLSH_SHARE_EN RU56 1 @ 2 10K_0201_5% FLSH_SHARE_EN (iPU):
RU58 1 2 10K_0201_5% '0' - Flash isn't shared, 1 Flash per Re-timer.
INTEL-RETIMER_BGA105 '1' - Flash is shared between 2 Re-timers
TBT Retime P/N:SA00009QD40
m
3VALW_TBTA
3VALW_TBTA
BB retimer FLSH_MSTR_SLV (iPU):
UU3A Should be used only when DG_FLSH_SHARE_EN is High.
RPU1 BB_TBTA_FLSH_MSTR_SLV RU64 1 @ 2 10K_0201_5%
TBTA_SPI_MOSI 1 2 0_0201_5% BBA_SPI_DI C6 C9 TBTA_I2C_SCL_BB 1 2 0_0201_5% 4 1 1 2 10K_0201_5%
'0' - Set Re-timer to be Slave on shared flash SPI I/F.
RU59 @ RU66 @ RU65 @
TBTA_SPI_MISO RU60 1 @ 2 0_0201_5% BBA_SPI_DO B4 EE_DI I2C_SCL E7 TBTA_I2C_SDA_BB RU61 1 @ 2 0_0201_5%
TBTA_I2C_SCL 51
3 2
'1' - Set Re-timer to be Master on shared flash SPI I/F
FLASH
TBTA_SPI_CS_N RU62 1 @ 2 0_0201_5% BBA_SPI_CS# B6 EE_DO I2C_SDA A10 TBTA_I2C_INT_BB_N RU67 1 @ 2 0_0201_5%
TBTA_I2C_SDA 51 FLSH_MSTR_SLV of BBR#1 (set as Master) should be PU
TBTA_SPI_CLK BBA_SPI_CLK EE_CS_N I2C_INT TBTA_FORCE_PWR_BB TBTA_I2C_INT_N 51 and PD for BBR#2 (set as Slave)
RU68 1 @ 2 0_0201_5% C7 B10 RU69 1 @ 2 0_0201_5% 2.2K_0404_4P2R_5%
EE_CLK FORCE_PWR TBTA_FLASH_BUSY_BB_N TBTA_FLASH_BUSY_N TBTA_FORCE_PWR 20,51 3VALW_TBTA +1.8VALW
A9 RU263 1 @ 2 0_0201_5%
POC GPIO
+VCC3V3_LC_TBTA RU63 FLASH_BUSY_N B9 BB_TBTA_GPIO_5
DEBUG
POC_GPIO_5 UU9
MISC &
A8 BB_TBTA_GPIO_6
1 8 TBTA_TDI A3 POC_GPIO_6 B8 BB_TBTA_PERST_N 8 1
TBTA_TMS TDI PERST_N TBTA_SMBUS_SCL VCCB VCCA RESET# should be output from PD.
2 7 C3 A7 3VALW_TBTA
TBTA_TCK TMS SMBUS_SCL TBTA_SMBUS_SDA TBTA_SMBUS_SCL PCH_SML0_CLK Pull up or Pull down based on USB PD Controller GPIO design.
3 6 B5 B7 7 2
co
4 5 TBTA_TDO C5 TCK JTAG SMBUS_SDA A4 BB_TBTA_FLSH_SHARE_EN B0 A0 TBTA_RESET_N 1 @ 2 100K_0201_5%
Note: If the USB PD Controller has a weak pull up present during its
RU70
TDO POC_GPIO_10 A5 BB_TBTA_FLSH_MSTR_SLV TBTA_SMBUS_SDA 6 3 PCH_SML0_DATA RU71 1 @ 2 100K_0201_5%
boot, a 10K to 100K Ohm pull down resistor is required to keep the
10K_0804_8P4R_5% POC_GPIO_11 A6 BB_TBTA_POC_GPIO12 B1 A1 Burnside Bridge RESET_N low during the VCC_3P3_SX power supply
POC_GPIO_12 L3 POC_GPIO_12 have iPU RU676 1 @ 2 0_0402_5% 5 4 ramp. The USB PD controller must drive RESET_N meeting the Burnside
TBTA_THERMDA NC_L3 3VALW_TBTA OE GND Bridge datasheet timing requirements to take it out of reset. If the USB
@ TP93 1 M11
2
THERMDA PD Controller can hold RESET_N low during the Burnside Bridge
M12 RU677 FXMA2102UMX_U-MLP8_1P2X1P4 VCC_3P3_SX power supply ramp, a 10K to 100K Ohm pull up and
B2 TEST_EDM push/pull GPIO on the USB PD controller is recommended.
FUSE_VQPS_64 Main power reset signal
TBTA_RESET_N
100K_0201_5%
L11
RESET_N TBTA_RESET_N 51
A11
1
C A12 MONDC L9 TBTA_XTAL_25M_IN 3VALW_TBTA C
DEBUG
L12 NC_A12 Main XTAL_25_IN M9 TBTA_XTAL_25M_OUT

MONDC_SVR XTAL_25_OUT RU81 1 @ 2 10K_0201_5%
TBTA_TEST_PWRGD B3 L5 TBTA_RSENSE BB_TBTA_PERST_N RU82 1 @ 2 10K_0201_5%
B11 TEST_PWR_GOOD RSENSE L4 TBTA_RBIAS RU76 1 2 1/20W_4.75K_0.5%_0201
TEST_EN RBIAS
.
A1 TBTA_SMBUS_SCL RU83 1 @ 2 0_0201_5% PCH_SML0_CLK
ATEST_P
Place as close as PCH_SML0_CLK 20,55
A2 possible to pins RU78 1 2 1K_0201_5%
ATEST_N TBTA_SMBUS_SDA PCH_SML0_DATA PLT_RST_N 20,31,63,73,78,79
RU88 1 @ 2 0_0201_5%
PCH_SML0_DATA 20,55
ap
INTEL-RETIMER_BGA105 Y BB_TBTA_PERST_N RU79 1 @ 2 0_0201_5%
BB_TBT_PERST_N 21
UU3C Y
B1 F12 3VALW_TBTA
B12 VSS_ANA_1 VSS_ANA_12 G7
D1 VSS_ANA_2 VSS_ANA_13 H1 BB_TBTA_POC_GPIO12 RU84 1 @ 2 10K_0201_5%
D2 VSS_ANA_3 VSS_ANA_14 H2
D11 VSS_ANA_4 VSS_ANA_15 H11 RU85 1 @ 2 10K_0201_5%
D12
F1
VSS_ANA_5
VSS_ANA_6 GND VSS_ANA_16
VSS_ANA_17
H12
J9 BB_TBTA_GPIO_5 RU86 1 2 10K_0201_5%
F2 VSS_ANA_7 VSS_ANA_18 K1 TBTA_TEST_PWRGD RU87 1 2 1/20W_100_1%_0201
VSS_ANA_8 VSS_ANA_19 0.9v @850mA
F7 K2 For BBR,
F9 VSS_ANA_9 VSS_ANA_20 K11 3VALW_TBTA C3718 +VCC0V9_SVR_TBTA_IND +VCC0V9_SVR_TBTA
VSS_ANA_10 VSS_ANA_21 LU2
F11 K12 can be
VSS_1
VSS_2
VSS_3
VSS_ANA_11 VSS_ANA_22 1 2
removed.
rL
3VALW_TBTA
22UC_6.3VC_MC_X5RC_0603
22UC_6.3VC_MC_X5RC_0603
22UC_6.3VC_MC_X5RC_0603
22UC_6.3VC_MC_X5RC_0603
1 1 0.68UH_DFE201610E-R68M-P2_3.1A_20% 1 1 1 1 1 1 1 @
1
1
TBTA_I2C_SCL
CU39
2.2U_6.3V_M_X5R_0201
CU42
2.2U_6.3V_M_X5R_0201
CU34
2.2U_6.3V_M_X5R_0201
CU35
2.2U_6.3V_M_X5R_0201
CU38
18P_50V_J_NPO_0201
CU40
2.2U_6.3V_M_X5R_0201
CU41
2.2U_6.3V_M_X5R_0201
CU43
2.2U_6.3V_M_X5R_0201
CU44
2.2U_6.3V_M_X5R_0201
RPU3 1 4 2.2K_0404_4P2R_5%
Pin E6
Pin J5
Inductor must be placed on the
Pin M4
Pin M5
F3
F5
G5
TBTA_I2C_SDA
CU32
CU36
CU37
CU33
INTEL-RETIMER_BGA105 same side as BB. No vias allowed 2 3
Pin E3
Pin E9
Pin F6
Pin G6
Pin G3
Pin G9
on VCC0v9_SVR_IND
2
2
2 2 2@ 2 2 2 2 2 2
RU49 1 @ 2 10K_0201_5% TBTA_I2C_INT_N
UU3B
+VCC3V3_ANA_TBTA L2
VCC3P3_ANA VCC3P3_SX
E6
3.3V@ 230mA
3VALW_TBTA IN XTAL
Share Same GND plane and connect to M2 & M3 pins (SVR_VSS) of BB TBTA_XTAL_25M_IN_R TBTA_XTAL_25M_IN
B E5 M4 RU89 1 2 0_0402_5% B
ai
+VCC3V3_LC_TBTA @
VCC3P3_LC VCC3P3_SVR_1 M5
F6 VCC3P3_SVR_2
+VCC0V9_SVR_TBTA VCC0P9_SVR_ANA_1 3.3V@ 50mA
G6 J7 3VA_TBTA IN LU22 EMC_NS@
VCC0P9_SVR_ANA_2 VCC3P3A
Power
4 3
E3 L1 4 3
VCC0P9_SVR_1 SVR_IND_1 +VCC0V9_SVR_TBTA_IND
G3 M1 OUT
VCC0P9_SVR_2 SVR_IND_2 1 2
E9 M2 3VALW_TBTA 3VA_TBTA +VCC3V3_ANA_TBTA +VCC3V3_LC_TBTA +VCC0V9_LC_TBTA +VCC0V9_LVR_TBTA 1 2
G9 VCC0P9_SVR_PB_ANA_1 SVR_VSS_1 M3 EXC24CH500U_4P
VCC0P9_SVR_PB_ANA_2 SVR_VSS_2 RU97 1 @ 2 0_0402_5%
TBTA_XTAL_25M_OUT_R TBTA_XTAL_25M_OUT
10U 6.3V M X5R 0402
10U 6.3V M X5R 0402

+VCC0V9_LC_TBTA J3 RU98 1 @ 2 0_0402_5% 1 1 1 1 1 1 1 1 RU92 1 @ 2 0_0402_5%
VCC0P9_LC
ep
CU45
CU46
2.2U_6.3V_M_X5R_0201
CU47
18P_50V_J_NPO_0201
CU48
2.2U_6.3V_M_X5R_0201
CU50
2.2U_6.3V_M_X5R_0201
CU49
2.2U_6.3V_M_X5R_0201
CU51
CU52
2.2U_6.3V_M_X5R_0201
Pin E5
Pin L2
Pin L6
Pin J7
Pin J7
Pin J3
+VCC0V9_LVR_TBTA L6 J5 RU682 1 @ 2 0_0201_5% 3VALW_TBTA @
M6 VCC0P9_LVR NC_J5 J6 RU683 1 @ 2 0_0201_5% TBTA_XTAL_25M_IN_R
VCC0P9_LVR_SENSE NC_J6 2 2 2 2 2 2 2 2
YU1
INTEL-RETIMER_BGA105 Y 4 3 TBTA_XTAL_25M_OUT_R
Pin J5 should be connected to NC2 3
Place holder for RC filter to reduce
PW_VCC3v3_SX for DBR ripple to VCC3v3A pin
compatibility. for BBR this pin is NC in 1 2
1 NC1
the package.
1 25MHZ_18PF_7R25000007 1
+3VALW CU28 CU29
27P_25V_J_NPO_0201 27P_25V_J_NPO_0201
3VALW_TBTA 2 2
1
CU166
UU5
R
1U_0402_6.3V6K
2
10U 6.3V M X5R 0402
0.1U_6.3V_K_X5R_0201
1 14 +3VTBTA RU680 1 @ 2 0_5%_0603 1 1
2 VIN1_1 VOUT1_2 13
VIN1_2 VOUT1_1
CU167
CU168
CU23
TBTA_PWR_EN 3 12 1 2 1000P_50V_K_X7R_0201
51 TBTA_PWR_EN ON1 CT1 2 2
1/20W_10K_5%_0201
+3VALW
4 11
VBIAS GND
0.01U_0402_25V7K
CU25
1 CU24
1
5 10 1 2 1000P_50V_K_X7R_0201
ON2 CT2
RU95
@
+3VALW
6 9 +3VTBTA
A 2 7 VIN2_1 VOUT2_2 8 A
VIN2_2 VOUT2_1
2
1 15
GPAD
CU169 TPS22976DPUR_WSON_2X3
1U_0402_6.3V6K
2

S540-TGL
Issued Date 2014/07/01
Vinafix.com
2012/07/01 Deciphered Date
Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. TYPEC_MUX_PortA
5 4 3 2 1
5 4 3 2 1
Reduce current surge in a

VBUS-short event. If not AC coupling is recommended for
+3VALW
needed, place 0Ohm VBUS-short protection on SSRX lines. If
resistor instead. not needed, place 0Ohm resistor instead.
2
TBTA_RX0_P RU99 1 2 1/20W_2.2_1%_0201 TBTA_RX0_R_P CU53 1 2 0.33U_25V_K_X5R_0201 TBTA_RX0_CONN_P
52 TBTA_RX0_P TBTA_RX0_N RU100 1 2 1/20W_2.2_1%_0201 TBTA_RX0_R_N CU54 1 2 0.33U_25V_K_X5R_0201 TBTA_RX0_CONN_N RU107
52 TBTA_RX0_N
100K_0201_5%
TBTA_TX0_P RU101 1 2 1/20W_2.2_1%_0201 TBTA_TX0_R_P CU56 1 2 0.22U_25V_K_X5R_0201 TBTA_TX0_CONN_P
52 TBTA_TX0_P TBTA_TX0_N RU102 1 2 1/20W_2.2_1%_0201 TBTA_TX0_R_N CU57 1 2 0.22U_25V_K_X5R_0201 TBTA_TX0_CONN_N
52 TBTA_TX0_N
1
TBT_USB2_ON_N
TBTA_RX1_P TBT_USB2_ON_N 56
RU103 1 2 1/20W_2.2_1%_0201 TBTA_RX1_R_P CU58 1 2 0.33U_25V_K_X5R_0201 TBTA_RX1_CONN_P
52 TBTA_RX1_P TBTA_RX1_N RU104 1 2 1/20W_2.2_1%_0201 TBTA_RX1_R_N CU60 1 2 0.33U_25V_K_X5R_0201 TBTA_RX1_CONN_N
52 TBTA_RX1_N
RU195 1 @ 2 0_0201_5%
79 EC_ON_PCH
3
TBTA_TX1_P RU105 1 2 1/20W_2.2_1%_0201 TBTA_TX1_R_P CU61 1 2 0.22U_25V_K_X5R_0201 TBTA_TX1_CONN_P QU1 D
52 TBTA_TX1_P TBTA_TX1_N RU106 1 2 1/20W_2.2_1%_0201 TBTA_TX1_R_N CU62 1 2 0.22U_25V_K_X5R_0201 TBTA_TX1_CONN_N RU196 1 @ 2 0_0201_5% TBT_USB2_ON 1
52 TBTA_TX1_N 79 EC_ON_USB2 G
D D
1
S L2N7002KN3T5G_SOT883-3
2
@ RU108
100K_0201_5%
DU607 DU5
EMC_NS@ EMC_NS@
2
TBTA_RX0_R_P1 2 2 1 TBTA_RX0_R_N
1 2 2 1
Bleeding SSTX/SSRX resistors
PESD5V0H1BSF_SOD962-2 PESD5V0H1BSF_SOD962-2 must be placed near USBC connector if 330nF cap +3VALW_PCH
DU6 DU7 is being used. Otherwise de-populate.
EMC_NS@ EMC_NS@
TBTA_TX0_R_P 1 2 2 1 TBTA_TX0_R_N RU110 1 2 1/20W_220K_1%_0201TBTA_RX0_CONN_P 1U_6.3V_M_X5R_0201 1 2 CU55

1 2 2 1 UU6
RU111 1 2 1/20W_220K_1%_0201TBTA_RX0_CONN_N
0.1U_6.3V_K_X5R_0201 1 2 CU59 8 7
PESD5V0H1BSF_SOD962-2 PESD5V0H1BSF_SOD962-2 RU112 1 2 1/20W_220K_1%_0201TBTA_RX1_CONN_P VCC NC
DU8 DU9
EMC_NS@ EMC_NS@
RU113 1 2 1/20W_220K_1%_0201TBTA_RX1_CONN_N USB20_2_U_P 2 3 USB20_2_P
TBTA_RX1_R_P1 TBTA_RX1_R_N HSD+ D+ USB20_2_P 17
2 2 1
1 2 2 1 RU114 1 2 1/20W_220K_1%_0201TBTA_TX0_CONN_P USB20_2_U_N 6 5 USB20_2_N
HSD- D- USB20_2_N 17 PCH
RU116 1 2 1/20W_220K_1%_0201TBTA_TX0_CONN_N
m
PESD5V0H1BSF_SOD962-2 PESD5V0H1BSF_SOD962-2 TBT_USB2_ON_N 1 4
DU10 DU11 OE# GND
EMC_NS@ EMC_NS@ RU117 1 2 1/20W_220K_1%_0201TBTA_TX1_CONN_P
TBTA_TX1_R_P 1 2 2 1 TBTA_TX1_R_N RU118 1 2 1/20W_220K_1%_0201TBTA_TX1_CONN_N TS3USB31ERSER_UQFN8_1P5X1P5

1 2 2 1
USB20_2_U_P RU197 2 @ 1 0_0201_5% USB20_2_P

PESD5V0H1BSF_SOD962-2 PESD5V0H1BSF_SOD962-2
USB20_2_U_N RU198 2 @ 1 0_0201_5% USB20_2_N
co
ESD Diodes should be located as close as possible to USBC.
C C
VCC3_LDO_PDA RU109 1 @ 2 0_0402_5%

VCC3_LDO_PDA
CC OVP EMC@
EXC24CH900U_4P
1
USB20_2_U_N 3 4 TBTA_USB2_CONN_N
1
.
RU119
CU63 100K_0201_5%
0.1U_6.3V_K_X5R_0201 USB20_2_U_P 2 1 TBTA_USB2_CONN_P
2
ap
UU7
2
LU3
C4 B4
VPWR FLT RU115 1 @ 2 0_0402_5%
TBTA_SBU1 D1 B1 TBTA_SBU1_CONN
52 TBTA_SBU1 TBTA_SBU2 SBU1 C_SBU1 TBTA_SBU2_CONN
D2 A1
52 TBTA_SBU2 SBU2 C_SBU2
TBTA_CC1 D3 A2 TBTA_CC1_CONN
51 TBTA_CC1
GND4
GND3
GND2
GND1
TBTA_CC2 D4 CC1 C_CC1 B2
51 TBTA_CC2 CC2 RPD_G1
A3 TBTA_CC2_CONN JUSBC1
C_CC2 B3
GND8
GND7
GND6
GND5
RPD_G2 B12 A1
rL
C1 GND4 GND1
GND1 C2 TBTA_RX0_CONN_P B11 A2 TBTA_TX0_CONN_P
CC_A_VBIAS A4 GND2 C3 TBTA_SBU1_CONN RU652 2 @ 1 1/20W_1M_1%_0201 SSRXp1 SSTXp1
VBIAS GND3 TBTA_SBU2_CONN RU653 2 @ 1 1/20W_1M_1%_0201 TBTA_RX0_CONN_N B10 A3 TBTA_TX0_CONN_N
1 SSRXn1 SSTXn1
CU68 VBUS_TBTA
B9 A4 VBUS_TBTA
0.1U_50V_K_X5R_0402 SN1904020YBFR_DSBGA16 Vbus4 Vbus1
2 TBTA_SBU2_CONN B8 A5 TBTA_CC1_CONN
SBU2 CC1
ai TBTA_USB2_CONN_N B7 A6 TBTA_USB2_CONN_P
Dn2 Dp1
TBTA_USB2_CONN_P B6 A7 TBTA_USB2_CONN_N
Dp2 Dn1
DU12 EMC_NS@ DU13 EMC_NS@ TBTA_CC2_CONN B5 A8 TBTA_SBU1_CONN
B CC2 SBU1 B
TBTA_USB2_CONN_N
1 2 2 1 TBTA_USB2_CONN_P B4 A9
1 2 2 1 VBUS_TBTA Vbus3 Vbus2 VBUS_TBTA
TBTA_TX1_CONN_N B3 A10 TBTA_RX1_CONN_N
SSTXn2 SSRXn2
ep
SESD0201X1BN-0010-098_DFN2 SESD0201X1BN-0010-098_DFN2
TBTA_TX1_CONN_P B2 A11 TBTA_RX1_CONN_P
SSTXp2 SSRXp2
DU14 EMC_NS@ DU15 EMC_NS@ B1 A12
GND10
GND3 GND2
GND9
VBUS_TBTA
TBTA_SBU1_CONN 1 2 2 1 TBTA_SBU2_CONN
1 2 2 1 DU608
1 8
GND5
GND6
SESD0201X1BN-0010-098_DFN2 SESD0201X1BN-0010-098_DFN2 2 Vbus GND4 7 HIGHSTAR-UB11249-B200W-1H
Near Near Near NC1 GND3
0.01U_25V_K_X5R_0201
0.01U_25V_K_X5R_0201
0.01U_25V_K_X5R_0201
0.01U_25V_K_X5R_0201
Near Near Near 3 6

DU16 EMC_NS@ DU17 EMC_NS@
PinB9 PinB9 PinB4 4 NC2 GND2 5
PinA9 PinA4 PinA4 NC3 GND1
2 1 1 1 1 2
4.7U_25V_M_X5R_0402
4.7U_25V_M_X5R_0402
TBTA_CC1_CONN TBTA_CC2_CONN
CU804
CU64
CU65
CU66
CU67
EMC_NS@
CU805
1 2 2 1
R
SP1224-01UTG_UDFN-6
1 2 2 1 EMC@
SESD0201X1BN-0010-098_DFN2 SESD0201X1BN-0010-098_DFN2 1 2 2 2 2 1
DU18
EMC_NS@
TVS靠靠Conn Pin出出出出VBUS plane放,
且且4个pin距且距距距距
VBUS_TBTA 1 2
1 2
SPHV24-01ETG-C_SOD882-2
FOR ESD
A A

S540-TGL
5 Vinafix.com
4 3
2
Size
C
Date:
Document Number
TYPEC_CONN_PortA
1
Sheet 53 of 110
Rev
0.1
5 4 3 2 1
VBUS_TBTB
TBT portB/left side TABLE I2C Addressing

Master: EC TBTB PORT 0x23
VCC3_LDO_PDB I2C1
NSR20F30NXT5G_DSN2-2
Slave: PD TBTC PORT 0x22
2
1
Master: PMC TBTB PORT 0x23
1/20W_100K_1%_0201
VINB_3V3 VCC3_LDO_PDB CU152 ADCIN1:3 I2C2
DU47
D
+3VALW VINB_3V3 4.7U_25V_M_X5R_0402 ADCIN2:0
TBTC PORT 0x22 D
1 Slave: PD
RU264
2
RU265 1 @ 2 0_5%_0603 Master: PD TBTB PORT T.B.D.
10U 6.3V M X5R 0402
10U 6.3V M X5R 0402
10U 6.3V M X5R 0402

I2C3
VCC1V5_LDO_PDB
2
2
1 1 1
Slave: RT TBTC PORT T.B.D.
PDB_ADCIN1
CU153
CU154
CU155
1/20W_22K_1%_0201
2 2 2
1
VCC3_LDO_PDB
RU266
EC
+5VALW EC_I2C_INT4_PDB_N RU267 1 @ 2 10K_0201_5%
2
22UC_6.3VC_MC_X5RC_0603
22UC_6.3VC_MC_X5RC_0603
22UC_6.3VC_MC_X5RC_0603
22UC_6.3VC_MC_X5RC_0603
22UC_6.3VC_MC_X5RC_0603
22UC_6.3VC_MC_X5RC_0603
G2
G8
H4
H1
H3
H8
C8
A3
A8
B8
F8
UU127 @
PD_I2C2_SCL RPU9 1 4 2.2K_0404_4P2R_5%
1 1 1 1 1 1
VSYS
PA_VBUS_1
PA_VBUS_2
PA_VBUS_3
VIN_3V3
LDO_1V5_1
LDO_1V5_2
LDO_3V3
PB_VBUS_1
PB_VBUS_2
PB_VBUS_3
PD_I2C2_SDA 2 3
CU160
CU161
CU156
CU157
CU158
CU159
PCH
A7
2 2 2 2 2 2 B7 PP5V_1 PCH_PMC_ALERT_PD_N
RU268 1 @ 2 10K_0201_5%
C7 PP5V_2
PP5V_3 TBTB_CC1 56
D7
PP5V_4 TBTB_CC2 56
E7 G4 PDB_ADCIN1
F7 PP5V_5 ADCIN1 TBTB_I2C_SCL RPU10 1 4 2.2K_0404_4P2R_5%
330P_25V_K_X7R_0201
330P_25V_K_X7R_0201
C PP5V_6 C
G7 TBTB_I2C_SDA 2 3
PP5V_7 BB Retimer
H7 G3 1 1
PP5V_8 ADCIN2
CU164
CU165
TBTB_I2C_INT_N RU269 1 2 10K_0201_5%
A4 2 2
E8 PA_GATE_VSYS G5 TBTB_CC1
PA_GATE_VBUS PA_CC1 H5 TBTB_CC2
PA_CC2
B5 PD2_A_CC1
B4 PB_CC1 A5 PD2_A_CC2 PD2_A_CC1 RU636 1 @ 2 0_0201_5%
D8 PB_GATE_VSYS PB_CC2 PD2_A_CC2 RU637 1 @ 2 0_0201_5%
PB_GATE_VBUS
PH 3.3VALW at EC SIDE
TBTB_RESET_N RU272 1 @ 2 0_0201_5% PD_TBTB_RESET_N C1 D1 EC_I2C_INT4_N_PDB_R RU271 1 @ 2 0_0201_5% EC_I2C_INT4_PDB_N
55 TBTB_RESET_N GPIO0 I2C_EC_IRQ# EC_I2C_INT4_PDB_N 79
RU623 1 @ 2 0_0201_5% PDB_PM_SLP_S4_N G1 E1 EC_SMB_CK4_PDB_R RU273 1 @ 2 0_0201_5% EC_SMB_CK4_PD EC
21,79 PM_SLP_S4_N GPIO1 I2C_EC_SCL EC_SMB_DA4_PDB_R RU274 EC_SMB_DA4_PD EC_SMB_CK4_PD 79 Slave
F1 1 @ 2 0_0201_5%
TBTB_PWR_EN PD_TBTB_PWR_EN I2C_EC_SDA EC_SMB_DA4_PD 51,79
RU276 1 @ 2 0_0201_5% A6
55 TBTB_PWR_EN GPIO2
H6
PH 3.3VALW at PCH SIDE
GPIO3 F2 PMC_ALERT_PDB_N RU277 1 @ 2 0_0201_5% PCH_PMC_ALERT_PD_N
USB_OC5_N USB_OC5_R_N I2C2S_IRQ# PCH_PMC_ALERT_PD_N 18,20
B RU278 1 @ 2 0_0201_5% B3 B
18 USB_OC5_N GPIO4 SML1_CLK_R_PDB PD_I2C2_SCL PCH
E2 RU279 1 @ 2 0_0201_5% Slave
I2C2S_SCL SML1_DATA_R_PDB PD_I2C2_SDA PD_I2C2_SCL 20
C2 D2 RU280 1 @ 2 0_0201_5%
GPIO5 I2C2S_SDA PD_I2C2_SDA 20,51
RU281 1 @ 2 0_0201_5% GPPC_B2_VRALERT_B_N F6
20 GPPC_B2_VRALERT_N GPIO6
G6 B1 TBTB_I2C_INT_PDB_N RU282 1 @ 2 0_0201_5% TBTB_I2C_INT_N
GPIO7 I2C3M_IRQ# TBTB_I2C_INT_N 55
B6 A2 TBTB_I2C_SCL_R RU283 1 @ 2 0_0201_5% TBTB_I2C_SCL BB retimer
GPIO8 I2C3M_SCL TBTB_I2C_SCL 55 Master
A1 TBTB_I2C_SDA_R RU284 1 @ 2 0_0201_5% TBTB_I2C_SDA
TBTB_FORCE_PWR_R I2C3M_SDA_1 TBTB_I2C_SDA 55
RU285 1 @ 2 0_0201_5% C6 B2
20 TBTB_FORCE_PWR GPIO9 I2C3M_SDA_2
GND
SN2001024YGBR_DSBGA50 H2
A A

S540-TGL
Vinafix.com
Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. TYPEC_Controller_PortA
5 4 3 2 1
5 4 3 2 1
VCC3_BB_SPIB
Burnside Bridge Re-Timer UU8D Y
+3VALW
12 TCP2_CTX_DRX0_P
TCP2_CTX_DRX0_P CU794 1 2 0.22U_6.3V_K_X5R_0201 TCP2_CTX_C_DRX0_P J1
TBT PORTS J12 TBTB_RX0_P
TBTB_RX0_P 56
TBTB_SPI_MISO
TBTB_SPI_CS_N
RU625
RU626
1
1
2 1/20W_2.2K_5%_0201
2 1/20W_2.2K_5%_0201 TBTB_FLASH_BUSY_N RU124 1 2 10K_0201_5% FLASH_BUSY# should be shared between BBR#1 and
TCP2_CTX_DRX0_N CU118 1 2 0.22U_6.3V_K_X5R_0201 TCP2_CTX_C_DRX0_N J2 ASSRXp1 BSSRXp1 J11 TBTB_RX0_N TBTB_SPI_WP_N RU627 1 2 1/20W_3.3K_5%_0201 RU125 1 @ 2 10K_0201_5%
12 TCP2_CTX_DRX0_N ASSRXn1 BSSRXn1 TBTB_RX0_N 56 TBTB_SPI_HOLD_N
BBR#2 with PU to PW_VCC3v3_SX_SYS
RU628 1 2 1/20W_3.3K_5%_0201
Port B - TypeC Side

TCP2_CRX_DTX0_P CU69 1 2 0.22U_6.3V_K_X5R_0201 TCP2_CRX_C_DTX0_P G1 G12 TBTB_TX0_P
Port A - Host Side

12 TCP2_CRX_DTX0_P TCP2_CRX_DTX0_N TCP2_CRX_C_DTX0_N ASSTXp1 BSSTXp1 TBTB_TX0_N TBTB_TX0_P 56
CU70 1 2 0.22U_6.3V_K_X5R_0201 G2 G11
12 TCP2_CRX_DTX0_N ASSTXn1 BSSTXn1 TBTB_TX0_N 56
TCP2_CTX_DRX1_P CU119 1 2 0.22U_6.3V_K_X5R_0201 TCP2_CTX_C_DRX1_P C1 C12 TBTB_RX1_P +3VS
12 TCP2_CTX_DRX1_P TCP2_CTX_DRX1_N TCP2_CTX_C_DRX1_N ASSRXp2 BSSRXp2 TBTB_RX1_N TBTB_RX1_P 56
CU120 1 2 0.22U_6.3V_K_X5R_0201 C2 C11 POC_GPIO6:
12 TCP2_CTX_DRX1_N ASSRXn2 BSSRXn2 TBTB_RX1_N 56 BB_TBTB_GPIO_6 1 2 10K_0201_5%
RU126 Indication to S0 state for Re-timer
TCP2_CRX_DTX1_P CU71 1 2 0.22U_6.3V_K_X5R_0201 TCP2_CRX_C_DTX1_P E1 E12 TBTB_TX1_P +3VALW VCC3_BB_SPIB RU127 1 @ 2 10K_0201_5%
12 TCP2_CRX_DTX1_P TCP2_CRX_DTX1_N TCP2_CRX_C_DTX1_N ASSTXp2 BSSTXp2 TBTB_TX1_N TBTB_TX1_P 56
CU72 1 2 0.22U_6.3V_K_X5R_0201 E2 E11
12 TCP2_CRX_DTX1_N ASSTXn2 BSSTXn2 TBTB_TX1_N 56
CU610
TBT2_LSX1_TXD RU632 1 @ 2 0_0201_5% TBT2_LSX1_TXD_R M7 M10 TBTB_SBU1 RU624 1 @ 2 0_0402_5% 1 2
20 TBT2_LSX1_TXD TBT2_LSX1_RXD 1 2 0_0201_5% TBT2_LSX1_RXD_R L7 PA_LSTX_SBU1 B_SBU1 L10 TBTB_SBU2 TBTB_SBU1 56
RU633 @
20 TBT2_LSX1_RXD PA_LSRX_SBU2 B_SBU2 TBTB_SBU2 56 3VALW_TBTB
0.1U_6.3V_K_X5R_0201
D TCP2_AUX_P RU128 1 @ 2 0_0201_5% TCP2_AUX_P_R L8 D
12 TCP2_AUX_P TCP2_AUX_N TCP2_AUX_N_R PA_AUX_P TBTB_FORCE_PWR
BB_FORCE_PWR:
RU129 1 @ 2 0_0201_5% M8 RU660 1 @ 2 10K_0201_5% Connect to EC/PCH for FW update
12 TCP2_AUX_N PA_AUX_N UU602 RU661 1 2 10K_0201_5% '0' - by default
1/20W_1M_1%_0201
1/20W_1M_1%_0201
TBTB_SPI_CS_N 1 8
AC coupling caps and PU/PD on AUX lines /CS VCC '1' - for debug only/FW update
1
1
TBTB_SPI_MISO 2 7 TBTB_SPI_HOLD_N
are implemented inside Burnside Bridge. TBTB_SPI_WP_N DO(IO1) /HOLD(IO3) TBTB_SPI_CLK
3 6
RU674
RU675
/WP(IO2) CLK 5 TBTB_SPI_MOSI
4 DI(IO0) 9 3VALW_TBTB
GND PAD_GND
2
2
@ @ W25Q80DVZPIG_WSON8_6X5 BB_TBTB_FLSH_SHARE_EN RU662 1 @ 2 10K_0201_5% FLSH_SHARE_EN (iPU):
RU663 1 2 10K_0201_5% '0' - Flash isn't shared, 1 Flash per Re-timer.
'1' - Flash is shared between 2 Re-timers
INTEL-RETIMER_BGA105
3VALW_TBTB
BB retimer 3VALW_TBTB FLSH_MSTR_SLV (iPU):
UU8A TBT Retime P/N:SA00009QD40 RPU11
BB_TBTB_FLSH_MSTR_SLV
Should be used only when DG_FLSH_SHARE_EN is High.
4 1 3VALW_TBTB +1.8VALW RU664 1 @ 2 10K_0201_5%
TBTB_SPI_MOSI BBB_SPI_DI TBTB_I2C_SCL_BB '0' - Set Re-timer to be Slave on shared flash SPI I/F.
RU138 1 @ 2 0_0201_5% C6 C9 RU139 1 @ 2 0_0201_5% 3 2 RU665 1 @ 2 10K_0201_5%
TBTB_SPI_MISO 1 2 0_0201_5% BBB_SPI_DO B4 EE_DI I2C_SCL E7 TBTB_I2C_SDA_BB 1 2 0_0201_5%
TBTB_I2C_SCL 54 '1' - Set Re-timer to be Master on shared flash SPI I/F
RU140 @ RU141 @
FLASH
TBTB_SPI_CS_N RU142 1 @ 2 0_0201_5% BBB_SPI_CS# B6 EE_DO I2C_SDA A10 TBTB_I2C_INT_BB_N RU143 1 @ 2 0_0201_5% TBTB_I2C_SDA 54
2.2K_0404_4P2R_5%
FLSH_MSTR_SLV of BBR#1 (set as Master) should be PU
m
TBTB_SPI_CLK RU144 1 @ 2 0_0201_5% BBB_SPI_CLK C7 EE_CS_N I2C_INT B10 TBTB_FORCE_PWR_BB RU145 1 @ 2 0_0201_5% TBTB_I2C_INT_N 54 and PD for BBR#2 (set as Slave)
EE_CLK FORCE_PWR TBTB_FLASH_BUSY_BB_NRU629 TBTB_FORCE_PWR 20
A9 1 @ 2 0_0201_5% TBTB_FLASH_BUSY_N
POC GPIO
+VCC3V3_LC_TBTB RU659 FLASH_BUSY_N B9 BB_TBTB_GPIO_5 UU11
DEBUG
MISC &
POC_GPIO_5 A8 BB_TBTB_GPIO_6 8 1 3VALW_TBTB
1 8 TBTB_TDI A3 POC_GPIO_6 B8 BB_TBTB_PERST_N VCCB VCCA
2 7 TBTB_TMS C3 TDI PERST_N A7 TBTB_SMBUS_SCL TBTB_SMBUS_SCL 7 2 PCH_SML0_CLK TBTB_RESET_N RU666 1 @ 2 100K_0201_5%
3 6 TBTB_TCK B5 TMS SMBUS_SCL B7 TBTB_SMBUS_SDA B0 A0 RU667 1 @ 2 100K_0201_5%
JTAG
4 5 TBTB_TDO C5 TCK SMBUS_SDA A4 BB_TBTB_FLSH_SHARE_EN TBTB_SMBUS_SDA 6 3 PCH_SML0_DATA
TDO POC_GPIO_10 A5 BB_TBTB_FLSH_MSTR_SLV B1 A1
10K_0804_8P4R_5% POC_GPIO_11 A6 BB_TBTB_POC_GPIO12 RU678 1 @ 2 0_0402_5% 5 4
POC_GPIO_12 3VALW_TBTB OE GND
L3 POC_GPIO_12 have iPU RESET# should be output from PD.
NC_L3
2
@ TP94 1 TBTB_THERMDA M11
co
THERMDA Pull up or Pull down based on USB PD Controller GPIO design.
RU679 FXMA2102UMX_U-MLP8_1P2X1P4 Note: If the USB PD Controller has a weak pull up present during its
M12 100K_0201_5%
B2 TEST_EDM boot, a 10K to 100K Ohm pull down resistor is required to keep the
FUSE_VQPS_64 Main power reset signal
TBTB_RESET_N Burnside Bridge RESET_N low during the VCC_3P3_SX power supply
L11
TBTB_RESET_N 54 ramp. The USB PD controller must drive RESET_N meeting the Burnside
1
A11 RESET_N
A12 MONDC L9 TBTB_XTAL_25M_IN Bridge datasheet timing requirements to take it out of reset. If the USB
DEBUG
Main
L12 NC_A12 XTAL_25_IN M9 TBTB_XTAL_25M_OUT PD Controller can hold RESET_N low during the Burnside Bridge
C MONDC_SVR XTAL_25_OUT VCC_3P3_SX power supply ramp, a 10K to 100K Ohm pull up and C
TBTB_TEST_PWRGD B3 L5 TBTB_RSENSE TBTB_SMBUS_SCL RU669 1 @ 2 0_0201_5% PCH_SML0_CLK push/pull GPIO on the USB PD controller is recommended.
TEST_PWR_GOOD RSENSE TBTB_RBIAS PCH_SML0_CLK 20,52 3VALW_TBTB
B11 L4 RU151 1 2 1/20W_4.75K_0.5%_0201
TEST_EN RBIAS TBTB_SMBUS_SDA RU673 1 @ 2 0_0201_5% PCH_SML0_DATA
PCH_SML0_DATA 20,52
A1 Place as close as RU153 1 @ 2 10K_0201_5%
A2 ATEST_P BB_TBTB_PERST_N RU155 1 @ 2 10K_0201_5%
ATEST_N possible to pins
.
INTEL-RETIMER_BGA105 Y
0.9v @850mA
UU8C Y For BBR, RU672 1 @ 2 0_0201_5%
3VALW_TBTB +VCC0V9_SVR_TBTB_IND +VCC0V9_SVR_TBTB PLT_RST_N 20,31,63,73,78,79
C3718
ap
B1 F12 LU5
can be
B12 VSS_ANA_1 VSS_ANA_12 G7 1 2 BB_TBTB_PERST_N RU152 1 @ 2 0_0201_5%
VSS_ANA_2 VSS_ANA_13 removed. BB_TBT_PERST_N 21
22UC_6.3VC_MC_X5RC_0603
22UC_6.3VC_MC_X5RC_0603
22UC_6.3VC_MC_X5RC_0603
22UC_6.3VC_MC_X5RC_0603
D1 H1
D2 VSS_ANA_3 VSS_ANA_14 H2 0.68UH_DFE201610E-R68M-P2_3.1A_20%
VSS_ANA_4 VSS_ANA_15 1 1 1 1 1 1 1 1 1
1
1
CU793
2.2U_6.3V_M_X5R_0201
CU78
2.2U_6.3V_M_X5R_0201
CU81
18P_50V_J_NPO_0201
CU82
2.2U_6.3V_M_X5R_0201
CU83
2.2U_6.3V_M_X5R_0201
CU85
2.2U_6.3V_M_X5R_0201
CU84
2.2U_6.3V_M_X5R_0201
CU87
2.2U_6.3V_M_X5R_0201
CU86
2.2U_6.3V_M_X5R_0201
D11 H11
Pin E6
Pin J5
Pin M4
Pin M5
Inductor must be placed on the
VSS_ANA_5
GND VSS_ANA_16
CU789
CU797
CU798
CU792
D12 H12 same side as BB. No vias allowed
F1 VSS_ANA_6 VSS_ANA_17 J9
Pin E3
Pin E9
Pin G6
Pin G3
Pin G9
Pin F6
on VCC0v9_SVR_IND
2
2
F2 VSS_ANA_7 VSS_ANA_18 K1 2 2 2@ 2 2 2 2 2 2
F7 VSS_ANA_8 VSS_ANA_19 K2 3VALW_TBTB
F9 VSS_ANA_9 VSS_ANA_20 K11
F11 VSS_ANA_10 VSS_ANA_21 K12 BB_TBTB_POC_GPIO12 RU657 1 @ 2 10K_0201_5%
VSS_ANA_11 VSS_ANA_22
VSS_1
VSS_2
VSS_3
RU158 1 @ 2 10K_0201_5%
BB_TBTB_GPIO_5 RU658 1 2 10K_0201_5%
Share Same GND plane and connect to M2 & M3 pins (SVR_VSS) of BB
F3
F5
G5
TBTB_TEST_PWRGD RU656 1 2 1/20W_100_1%_0201
rL
INTEL-RETIMER_BGA105
3VALW_TBTB
@
UU8B RPU5 1 4 2.2K_0404_4P2R_5% TBTB_I2C_SCL
2 3 TBTB_I2C_SDA
3.3V@ 230mA
L2 E6 3VALW_TBTB 3VA_TBTB +VCC3V3_ANA_TBTB +VCC3V3_LC_TBTB +VCC0V9_LC_TBTB +VCC0V9_LVR_TBTB
+VCC3V3_ANA_TBTB VCC3P3_ANA VCC3P3_SX 3VALW_TBTB IN
E5 M4 RU670 1 @ 2 0_0402_5% RU156 1 @ 2 10K_0201_5% TBTB_I2C_INT_N
+VCC3V3_LC_TBTB VCC3P3_LC VCC3P3_SVR_1
10U 6.3V M X5R 0402
10U 6.3V M X5R 0402

M5 RU173 1 @ 2 0_0402_5% 1 1 1 1 1 1 1 1
VCC3P3_SVR_2
Pin E5
CU88
CU89
2.2U_6.3V_M_X5R_0201
CU90
18P_50V_J_NPO_0201
CU91
2.2U_6.3V_M_X5R_0201
CU92
2.2U_6.3V_M_X5R_0201
CU93
2.2U_6.3V_M_X5R_0201
CU94
CU95
2.2U_6.3V_M_X5R_0201
Pin L2
Pin L6
F6
Pin J7
Pin J7
Pin J3
3.3V@ 50mA
+VCC0V9_SVR_TBTB VCC0P9_SVR_ANA_1 XTAL
ai
B G6 J7 @ B
VCC0P9_SVR_ANA_2 VCC3P3A 3VA_TBTB IN
Power
E3 L1 2 2 2 2 2 2 2 2 TBTB_XTAL_25M_IN_R RU668 1 @ 2 0_0402_5% TBTB_XTAL_25M_IN

VCC0P9_SVR_1 SVR_IND_1 +VCC0V9_SVR_TBTB_IND
G3 M1 OUT
VCC0P9_SVR_2 SVR_IND_2
E9 M2 Place holder for RC filter to reduce LU4 EMC_NS@
G9 VCC0P9_SVR_PB_ANA_1 SVR_VSS_1 M3 4 3
VCC0P9_SVR_PB_ANA_2 SVR_VSS_2 ripple to VCC3v3A pin 4 3
J3
+VCC0V9_LC_TBTB VCC0P9_LC 1 2
L6 J5 RU684 1 @ 2 0_0201_5% 1 2
+VCC0V9_LVR_TBTB VCC0P9_LVR NC_J5 3VALW_TBTB
ep
M6 J6 RU685 1 @ 2 0_0201_5% EXC24CH500U_4P
VCC0P9_LVR_SENSE NC_J6
TBTB_XTAL_25M_OUT_R RU671 1 @ 2 0_0402_5% TBTB_XTAL_25M_OUT
INTEL-RETIMER_BGA105 Y
Pin J5 should be connected to
PW_VCC3v3_SX for DBR
compatibility. for BBR this pin is NC in TBTB_XTAL_25M_IN_R
the package.
YU2
4 3 TBTB_XTAL_25M_OUT_R
+3VALW NC2 3
3VALW_TBTB 1 2
1 1 NC1
CU170 1 25MHZ_18PF_7R25000007 1
1U_0402_6.3V6K UU130
R
2
10U 6.3V M X5R 0402
0.1U_6.3V_K_X5R_0201
1 14 +3VTBTB RU681 1 @ 2 0_5%_0603 1 1 CU795 CU799

2 VIN1_1 VOUT1_2 13 27P_25V_J_NPO_0201 27P_25V_J_NPO_0201
VIN1_2 VOUT1_1 2 2
CU171
CU172
CU808
TBTB_PWR_EN 3 12 1 2 1000P_50V_K_X7R_0201
54 TBTB_PWR_EN ON1 CT1 2 2
1/20W_10K_5%_0201
4 11
+3VALW VBIAS GND
0.01U_0402_25V7K
CU174
1 CU809
1
5 10 1 2 1000P_50V_K_X7R_0201
ON2 CT2
RU286
@
6 9 +3VTBTB
2 +3VALW VIN2_1 VOUT2_2
7 8
VIN2_2 VOUT2_1
2
15
A GPAD A
1
TPS22976DPUR_WSON_2X3
CU173
1U_0402_6.3V6K
2

S540-TGL
Vinafix.com
Custom
TYPEC_MUX_PortB 0.1

5 4 3 2 1
5 4 3 2 1
Reduce current surge in a

VBUS-short event. If not AC coupling is recommended for
needed, place 0Ohm VBUS-short protection on SSRX lines. If
resistor instead. not needed, place 0Ohm resistor instead.
TBTB_RX0_P RU174 1 2 1/20W_2.2_1%_0201 TBTB_RX0_R_P CU96 1 2 0.33U_25V_K_X5R_0201 TBTB_RX0_CONN_P
55 TBTB_RX0_P TBTB_RX0_N +3VALW_PCH
RU175 1 2 1/20W_2.2_1%_0201 TBTB_RX0_R_N CU97 1 2 0.33U_25V_K_X5R_0201 TBTB_RX0_CONN_N
55 TBTB_RX0_N
TBTB_TX0_P RU176 1 2 1/20W_2.2_1%_0201 TBTB_TX0_R_P CU99 1 2 0.22U_25V_K_X5R_0201 TBTB_TX0_CONN_P
55 TBTB_TX0_P TBTB_TX0_N RU177 1 2 1/20W_2.2_1%_0201 TBTB_TX0_R_N CU100 1 2 0.22U_25V_K_X5R_0201 TBTB_TX0_CONN_N 1U_6.3V_M_X5R_0201 1 2 CU98
55 TBTB_TX0_N UU10
TBTB_RX1_P RU178 1 2 1/20W_2.2_1%_0201 TBTB_RX1_R_P CU101 1 2 0.33U_25V_K_X5R_0201 TBTB_RX1_CONN_P
55 TBTB_RX1_P TBTB_RX1_N RU179 1 2 1/20W_2.2_1%_0201 TBTB_RX1_R_N CU103 1 2 0.33U_25V_K_X5R_0201 TBTB_RX1_CONN_N 0.1U_6.3V_K_X5R_0201 1 2 CU102 8 7
D 55 TBTB_RX1_N VCC NC D
TBTB_TX1_P RU180 1 2 1/20W_2.2_1%_0201 TBTB_TX1_R_P CU104 1 2 0.22U_25V_K_X5R_0201 TBTB_TX1_CONN_P
55 TBTB_TX1_P TBTB_TX1_N RU181 1 2 1/20W_2.2_1%_0201 TBTB_TX1_R_N CU105 1 2 0.22U_25V_K_X5R_0201 TBTB_TX1_CONN_N USB20_3_U_P 2 3 USB20_3_P
55 TBTB_TX1_N HSD+ D+ USB20_3_P 17
PCH
USB20_3_U_N 6 5 USB20_3_N
HSD- D- USB20_3_N 17
TBT_USB2_ON_N 1 4
DU20 DU21 53 TBT_USB2_ON_N OE# GND
EMC_NS@ EMC_NS@
TBTB_RX0_R_P1 2 2 1 TBTB_RX0_R_N TS3USB31ERSER_UQFN8_1P5X1P5

1 2 2 1
Bleeding SSTX/SSRX resistors
m
PESD5V0H1BSF_SOD962-2 PESD5V0H1BSF_SOD962-2 must be placed near USBC connector if 330nF cap
DU22 DU23 is being used. Otherwise de-populate. USB20_3_P USB20_3_U_P
EMC_NS@ EMC_NS@ RU199 1 @ 2 0_0201_5%
TBTB_TX0_R_P 1 2 2 1 TBTB_TX0_R_N RU185 1 2 1/20W_220K_1%_0201TBTB_RX0_CONN_P USB20_3_N RU200 1 @ 2 0_0201_5% USB20_3_U_N

1 2 2 1
RU186 1 2 1/20W_220K_1%_0201TBTB_RX0_CONN_N
PESD5V0H1BSF_SOD962-2 PESD5V0H1BSF_SOD962-2 RU187 1 2 1/20W_220K_1%_0201TBTB_RX1_CONN_P
DU24 DU25
EMC_NS@ EMC_NS@
co
RU188 1 2 1/20W_220K_1%_0201TBTB_RX1_CONN_N
TBTB_RX1_R_P1 2 2 1 TBTB_RX1_R_N
1 2 2 1 RU189 1 2 1/20W_220K_1%_0201TBTB_TX0_CONN_P RU184 1 @ 2 0_0402_5%
RU191 1 2 1/20W_220K_1%_0201TBTB_TX0_CONN_N EMC@

PESD5V0H1BSF_SOD962-2 PESD5V0H1BSF_SOD962-2 EXC24CH900U_4P
DU26 DU27
EMC_NS@ EMC_NS@ RU192 1 2 1/20W_220K_1%_0201TBTB_TX1_CONN_P USB20_3_U_N 3 4 TBTB_USB2_CONN_N
C C
TBTB_TX1_R_P 1 2 2 1 TBTB_TX1_R_N RU193 1 2 1/20W_220K_1%_0201TBTB_TX1_CONN_N
1 2 2 1 USB20_3_U_P 2 1 TBTB_USB2_CONN_P
.
LU6
PESD5V0H1BSF_SOD962-2 PESD5V0H1BSF_SOD962-2
RU190 1 @ 2 0_0402_5%
ap
ESD Diodes should be located as close as possible to USBC.
Remove CC OVP B12

JUC2
A1
GND4 GND1
TBTB_RX0_CONN_P B11 A2 TBTB_TX0_CONN_P
TBTB_SBU1 RU638 1 @ 2 0_0402_5% TBTB_SBU1_CONN SSRXp1 SSTXp1
55 TBTB_SBU1 TBTB_SBU2 TBTB_SBU2_CONN TBTB_RX0_CONN_N TBTB_TX0_CONN_N
RU639 1 @ 2 0_0402_5% B10 A3
55 TBTB_SBU2 SSRXn1 SSTXn1
rL
TBTB_CC1 RU640 1 @ 2 0_0402_5% TBTB_CC1_CONN B9 A4
54 TBTB_CC1 TBTB_CC2 TBTB_CC2_CONN VBUS_TBTB VBUS4 VBUS1 VBUS_TBTB
RU641 1 @ 2 0_0402_5%
54 TBTB_CC2 TBTB_SBU2_CONN TBTB_CC1_CONN
B8 A5
SBU2 CC1
TBTB_USB2_CONN_N B7 A6 TBTB_USB2_CONN_P
Dn2 Dp1
DU28 EMC_NS@ DU29 EMC_NS@ TBTB_USB2_CONN_P B6 A7 TBTB_USB2_CONN_N
Dp2 Dn1
TBTB_USB2_CONN_N
1 2 2 1 TBTB_USB2_CONN_P TBTB_CC2_CONN B5 A8 TBTB_SBU1_CONN
1 2 2 1 CC2 SBU1
ai
B
VBUS_TBTB
B4 A9 VBUS_TBTB
B
SESD0201X1BN-0010-098_DFN2 SESD0201X1BN-0010-098_DFN2 VBUS3 VBUS2
TBTB_TX1_CONN_N B3 A10 TBTB_RX1_CONN_N
SSTXn2 SSRXn2
DU30 EMC_NS@ DU31 EMC_NS@ TBTB_TX1_CONN_P B2 A11 TBTB_RX1_CONN_P
SSTXp2 SSRXp2
TBTB_SBU1_CONN 1 2 2 1 TBTB_SBU2_CONN VBUS_TBTB B1 A12
1 2 2 1 DU609 GND3 GND2
SESD0201X1BN-0010-098_DFN2 SESD0201X1BN-0010-098_DFN2
ep 1
2 Vbus GND4 7
8
GND1 GND6
Near Near Near NC1 GND3 6 GND5 GND10
0.01U_25V_K_X5R_0201
0.01U_25V_K_X5R_0201
0.01U_25V_K_X5R_0201
0.01U_25V_K_X5R_0201
Near Near Near 3 GND2 GND5
DU32 EMC_NS@ DU33 EMC_NS@
PinB9 PinB9 PinB4 4 NC2 GND2 5 GND3 GND6 GND9 GND4
PinA9 PinA4 PinA4 NC3 GND1 GND7 GND8
2 1 1 1 1 2
4.7U_25V_M_X5R_0402
4.7U_25V_M_X5R_0402
TBTB_CC1_CONN TBTB_CC2_CONN
CU806
CU796
CU800
CU110
CU801
EMC_NS@
CU807
1 2 2 1 SP1224-01UTG_UDFN-6
1 2 2 1 EMC_NS@ HIGHSTAR_UB11249-B200G-1H
ME@
SESD0201X1BN-0010-098_DFN2 SESD0201X1BN-0010-098_DFN2 1 2 2 2 2 1
DU34
EMC_NS@
R
VBUS_TBTB 1 2
1 2
SPHV24-01ETG-C_SOD882-2
FOR ESD
A A

S540-TGL
5
Vinafix.com
4 3
2
Custom
Date:
TYPEC_CONN_PortB
1
Sheet 56 of 110
Rev
0.1
5 4 3 2 1
+USB_VCCB
USB3.1 PORT x2 @
CU74 1 2
+USB_VCCB 1U_0603_25V6M
+5VALW @
Low Active 2.2A CU75 1 2 470P_50V_K_X7R_0201
UU134 CU73 1 2 220U_6.3V_M
+
5 1
D IN OUT D
2 2
CU76 GND JUA1
1U_0402_16V6K 4 3 USB_OC3_N 1
ENB OCB USB_OC3_N 18 USB20_1_CON_N 2 VBUS
1 SY6288D20AAC_SOT23-5 USB20_1_CON_P 3 D-
1 D+
4
@ CU77 USB30_RX1_CON_N 5 GND1
1000P_0402_50V_X7R_0402 USB30_RX1_CON_P 6 SSRX- 10
2 7 SSRX+ GND3 11
USB_ON_N USB30_TX1_CON_N 8 GND2 GND4 12
78,79 USB_ON_N USB30_TX1_CON_P SSTX- GND5
9 13
SSTX+ GND6
m
ALLTO_C107MJ-10939-L
ME@
co
RU133 1 @ 2 0_0402_5%
EMC close to USB Conn
C
LU101 EMC@ C
USB20_1_N 1 2 USB20_1_CON_N
17 USB20_1_N 1 2
DU106
USB20_1_P 4 3 USB20_1_CON_P USB30_RX1_CON_N 10 1 USB30_RX1_CON_N
17 USB20_1_P 4 3 NC1 Line-1
.
EXC24CH900U_4P USB30_RX1_CON_P 9 2 USB30_RX1_CON_P
NC2 Line-2
ap
RU134 1 @ 2 0_0402_5% USB30_TX1_CON_N 7 4 USB30_TX1_CON_N
NC3 Line-3
USB30_TX1_CON_P 6 5 USB30_TX1_CON_P
NC4 Line-4
RU136 1 @ 2 0_0402_5% 3
GND1
8
LU99 EMC_NS@ GND2
USB30_RX1_N 1 2 USB30_RX1_CON_N AZ1143-04F-R7G_DFN2510P10E10
rL
17 USB30_RX1_N 1 2 EMC@
USB30_RX1_P 4 3 USB30_RX1_CON_P
17 USB30_RX1_P 4 3
EXC24CH900U_4P
USB20_1_CON_P
RU135 1 @ 2 0_0402_5% +USB_VCCB
ai
B USB20_1_CON_N B
2
RU132 1 @ 2 0_0402_5%
DU108
1
ep
LU100 EMC_NS@ EMC@ DU107
USB30_TX1_N 1 2 USB30_TX1_C_N 1 2 USB30_TX1_CON_N AZC199-02S.R7G_SOT23-3
17 USB30_TX1_N 1 2
CU80 .1U_0402_10V6-K EMC@
2
USB30_TX1_P 1 2 USB30_TX1_C_P 4 3 USB30_TX1_CON_P
17 USB30_TX1_P
2
CU79 .1U_0402_10V6-K 4 3 AZ5725-01F.R7GR_DFN1006P2X2
EXC24CH900U_4P
RU131 1 @ 2 0_0402_5%
1
R
A A
Issued Date 2021/04/07 Deciphered Date 2021/04/07 USB2.0

B
HY568 0.1
Vinafix.com
5 4 3 2 1
5 4 3 2 1
+USB_VCCB
@
CU111 1 2 1U_0603_25V6M
@
CU112 1 2470P_0402_50V7K
JUA2
1
D USB20_10_CON_N 2 VBUS D
USB20_10_CON_P 3 D-
4 D+
USB30_RX5_CON_N 5 GND1
USB30_RX5_CON_P 6 SSRX- 10
7 SSRX+ GND3 11
USB30_TX5_CON_N 8 GND2 GND4 12
USB30_TX5_CON_P 9 SSTX- GND5 13
SSTX+ GND6
ALLTO_C107MJ-10939-L
ME@
RU150 1 @ 2 0_0402_5% EMC close to USB Conn

LU8 EMC@
USB20_10_N 1 2 USB20_10_CON_N
17 USB20_10_N 1 2 DU241
m
USB30_RX5_CON_N 10 1 USB30_RX5_CON_N
USB20_10_P 4 3 USB20_10_CON_P NC1 Line-1
17 USB20_10_P 4 3 USB30_RX5_CON_P USB30_RX5_CON_P
9 2
EXC24CH900U_4P NC2 Line-2
USB30_TX5_CON_N 7 4 USB30_TX5_CON_N
RU157 1 @ 2 0_0402_5% NC3 Line-3
USB30_TX5_CON_P 6 5 USB30_TX5_CON_P
NC4 Line-4
3
1 2 0_0402_5% GND1
co
RU148 @
8
GND2
C LU15 EMC_NS@ AZ1143-04F-R7G_DFN2510P10E10 C
USB30_RX5_N 1 2 USB30_RX5_CON_N EMC@
17 USB30_RX5_N 1 2
USB30_RX5_P 4 3 USB30_RX5_CON_P
17 USB30_RX5_P 4 3
EXC24CH900U_4P USB20_10_CON_P
+USB_VCCB
RU149 1 @ 2 0_0402_5% USB20_10_CON_N
.
1
ap
RU159 1 @ 2 0_0402_5% DU65
1
DU62
LU16 EMC_NS@ EMC@ AZC199-02S.R7G_SOT23-3
USB30_TX5_N 1 2 USB30_TX5_C_N 1 2 USB30_TX5_CON_N EMC@
17 USB30_TX5_N 1 2
2
CU109 .1U_0402_10V6-K
2
USB30_TX5_P 1 2 USB30_TX5_C_P 4 3 USB30_TX5_CON_P AZ5725-01F.R7GR_DFN1006P2X2
17 USB30_TX5_P 4 3
CU108 .1U_0402_10V6-K
EXC24CH900U_4P
1
RU147 1 @ 2 0_0402_5%
rL
B
ai B
ep
R
A A

Vinafix.com
C
HY568 0.1

5 4 3 2 1
A B C D E
+USB_VCCA
RU169 1 @ 2 0_0402_5%
LU95 EMC@ CU788 1 2 220U_B2_6.3VM_R35M
+
USB20_11_B_N 1 2 USB20_11_CON_N
1 2 @
CU113 1 2
USB20_11_B_P 4 3 USB20_11_CON_P 1U_0603_25V6M
4 3 @
EXC24CH900U_4P CU114 1 2
470P_0402_50V7K
RU170 1 @ 2 0_0402_5%
1 1
JUA3
RU172 1 @ 2 0_0402_5% 1
USB20_11_CON_N 2 VBUS
USB20_11_CON_P 3 D-
LU93 EMC_NS@ 4 D+
USB30_RX3_N 1 2 USB30_RX3_CON_N USB30_RX3_CON_N 5 GND1
17 USB30_RX3_N 1 2 USB30_RX3_CON_P SSRX-
6 10
7 SSRX+ GND3 11
USB30_RX3_P 4 3 USB30_RX3_CON_P USB30_TX3_CON_N 8 GND2 GND4 12
17 USB30_RX3_P 4 3 USB30_TX3_CON_P SSTX- GND5
9 13
EXC24CH900U_4P SSTX+ GND6
RU171 1 @ 2 0_0402_5% ALLTO_C107MJ-10939-L

ME@
RU168 1 @ 2 0_0402_5%
LU94 EMC_NS@
USB30_TX3_N 1 2 USB30_TX3_C_N 1 2 USB30_TX3_CON_N
17 USB30_TX3_N 1 2
CU116 .1U_0402_10V6-K
m
USB30_TX3_P 1 2 USB30_TX3_C_P 4 3 USB30_TX3_CON_P
17 USB30_TX3_P 4 3
CU115 .1U_0402_10V6-K
EXC24CH900U_4P
RU161 1 @ 2 0_0402_5%
co
USB charger
2 2
+5VALW
2.5A
UU133
@
DU4 USB20_11_CON_P CU117 2 1 .1U_0402_16V7K 1 16 ILIM_HI RU162 1 2 18.2K_0402_1%
USB30_RX3_CON_N 10 1 USB30_RX3_CON_N +USB_VCCA IN ILIM_HI
NC1 Line-1 USB20_11_CON_N USB20_11_N 2 15 ILIM_LO RU163 1 @ 2 20K_0402_1%
17 USB20_11_N DM_OUT ILIM_LO
.
USB30_RX3_CON_P 9 2 USB30_RX3_CON_P
NC2 Line-2
3
USB20_11_P 3 14
17 USB20_11_P DP_OUT GND
1
USB30_TX3_CON_N 7 4 USB30_TX3_CON_N DU3
NC3 Line-3
ap
AZC199-02S.R7G_SOT23-3 DU242 ILIM_SEL 4 13
1
USB30_TX3_CON_P 6 5 USB30_TX3_CON_P EMC@ AZ5725-01F.R7GR_DFN1006P2X2 ILIM_SEL FAULT USB_OC2_N 18
NC4 Line-4 EMC@ 5 12
79 USB_CHG_EN EN OUT +USB_VCCA
3
GND1 CHG_MOD1 6 11 USB20_11_B_N
79 CHG_MOD1 CLT1 DM_IN
2
8
GND2 CHG_MOD2 7 10 USB20_11_B_P
2
AZ1143-04F-R7G_DFN2510P10E10 CLT2 DP_IN
E_PAD
CHG_MOD3 8 9 STATUS_N
EMC@ 79 CHG_MOD3 CLT3 STATUS STATUS_N 79
1
SN1702001RTER_WQFN16_3X3
17
rL
+5VALW
3
ai STATUS_N RU164 2 1 10K_0402_5%
for placement optimization

3
[close to EC side]
ep
+5VALW
RU160
ILIM_SEL 2 3
CHG_MOD2 1 4
10K_0404_4P2R_5%
ILIM_SEL RU165 2 @ 1 10K_0402_5%

CLT1 CLT2 CLT3 ILIM_SEL MOD
CHG_MOD2 RU166 2 @ 1 10K_0402_5%
R
USB_CHG_EN RU167 2 1 10K_0402_5% 0 0 0 X DCH OUT held low
* 1 1 1 1 CDP Data Connected and Port Power Mgt. Function Active
* 1 1 1 0 SDP2 Data Connected
* 1 1 0 X SDP1 Data Connected
* 0 1 0 X SDP1 Data Connected
1 0 0 X DCP_Short Device Forced to stay in DCP BC 1.2 charging mode
1 0 1 X DCP_Divider Device Forced to stay in DCP Divider 1 Charging Mode

4 4
* 0 1 1 X DCP_Auto Data Disconnected and Port Power Mgt. Function Active
0 0 1 X DCP_Auto Data Disconnected and Power Wake Function Active
Issued Date 2021/04/07 Deciphered Date 2021/04/07 USB2.0/USB3.0 PORT (LEFT)

Vinafix.com
C
HY568 0.1

A B C D E
A B C D E F G H
1 1
SATA HDD Conn.
JHDD1
RF8 1 @ 2 0_0805_5% 1
+5VS 1
2
3 2
4 3
SATA_PRX_DTX13_P 17@ CF5 1 2 0.01U_0201_10V6K SATA_PRX_C_DTX13_P 5 4
16 SATA_PRX_DTX13_P SATA_PRX_DTX13_N 17@ CF4 1 2 0.01U_0201_10V6K SATA_PRX_C_DTX13_N 6 5
16 SATA_PRX_DTX13_N 7 6
SATA_PTX_DRX13_N 17@ CF3 1 2 0.01U_0201_10V6K SATA_PTX_C_DRX13_N 8 7 12
16 SATA_PTX_DRX13_N SATA_PTX_DRX13_P SATA_PTX_C_DRX13_P 8 GND2
17@ CF2 1 2 0.01U_0201_10V6K 9
16 SATA_PTX_DRX13_P 9
10 11
10 GND1
ME@
2 2
+5VS
22U_10V_M_X5R_0603
22U_10V_M_X5R_0603
33P_50V_J_NPO_0201
33P_50V_J_NPO_0201
0.1U_6.3V_K_X5R_0201
1 1 1 1 1 1 1
10U_0805_10V6K
10U_25V_K_X6S_0805_H1.25
CF30
CF31
CF32
CF33
CF34
CF35
CF6
17@
17@ @ @ @
2 2 2 2 2 2 2
RF_NS@
RF_NS@
3 3
4 4
Issued Date 2021/04/07 Deciphered Date 2021/04/07 HDD/XBOX CONN

HY568
Vinafix.com DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 0.3
A B C D E F G H
A B C D E
M.2 SSD(PCIE GEN4 from CPU)

+3VS +3VS_SSD1
Need short SSD RST +3VS_SSD1
J6 @
2 1 Min 3A +3VS
2 1
0.1U_6.3V_K_X5R_0201
0.1U_6.3V_K_X5R_0201
12P_50V_J_NPO_0201
2.2P_25V_C_COG_0201
JUMP_43X79 1
1
10U 6.3V M X5R 0402
10U 6.3V M X5R 0402

1 1 1 1 1 1 1
CK209
CK210
CK211
CK212
CK218
CK219
@ CK2
+ CK222 RK457 @ 0.1U_6.3V_K_X5R_0201
100U_B2_6.3VM_R35M 10K_0402_5% 2
2 2 2 2 2 2
RF_NS@
RF_NS@
5
@ 2
@
VCC
1
JSSD1
NGFF1 +3VS_SSD1
20,31,52,55,71,73,78,79 PLT_RST_N
PLT_RST_N
CPU_SSD_RST_N
1
2
IN1
OUT
4 SSD_RST_N
1
GND
18 CPU_SSD_RST_N IN2
1
1 2 UK134
3 GND_1 3.3V_1 4 MC74VHC1G08DFT2G_SC70-5 RK458
3
PCIE4_CRX_DTX3_N 5 GND_2 3.3V_2 6 @ 100K_0201_5%
7 PCIE4_CRX_DTX3_N PCIE4_CRX_DTX3_P PERN3 N/C_2 @
7 8
7 PCIE4_CRX_DTX3_P PERP3 N/C_3
9 10
2
PCIE4_CTX_DRX3_N CK17 2 PCIE4_CTX_C_DRX3_N
1 0.22U_6.3V_K_X5R_0201 11 GND_3 DAS/DSS# 12
7 PCIE4_CTX_DRX3_N PCIE4_CTX_DRX3_P PCIE4_CTX_C_DRX3_P PETN3 3.3V_3
CK18 2 1 0.22U_6.3V_K_X5R_0201 13 14
7 PCIE4_CTX_DRX3_P PETP3 3.3V_4
15 16
PCIE4_CRX_DTX2_N 17 GND_4 3.3V_5 18
7 PCIE4_CRX_DTX2_N PCIE4_CRX_DTX2_P PERN2 3.3V_6 PLT_RST_N SSD_RST_N
19 20 RK459 1 @ 2 0_0201_5%
21 22
1 0.22U_6.3V_K_X5R_0201 23 GND_5 N/C_5 24
7 PCIE4_CTX_DRX2_N PCIE4_CTX_DRX2_P PCIE4_CTX_C_DRX2_P PETN2 N/C_6
CK21 2 1 0.22U_6.3V_K_X5R_0201 25 26
7 PCIE4_CTX_DRX2_P PETP2 N/C_7
27 28
PCIE4_CRX_DTX1_N 29 GND_6 N/C_8 30
7 PCIE4_CRX_DTX1_N PCIE4_CRX_DTX1_P PERN1 N/C_9
31 32
33 34
1 0.22U_6.3V_K_X5R_0201 35 GND_7 N/C_11 36
PCIE Gen4 across moat solution
7 PCIE4_CTX_DRX1_N PCIE4_CTX_DRX1_P PCIE4_CTX_C_DRX1_P PETN1 N/C_12
CK14 2 1 0.22U_6.3V_K_X5R_0201 37 38
7 PCIE4_CTX_DRX1_P PETP1 DEVSLP
39 40
PCIE4_CRX_DTX0_N 41 GND_8 N/C_13 42
7 PCIE4_CRX_DTX0_N PCIE4_CRX_DTX0_P PERN0/SATA-B+ N/C_14
43 44 +3VALW VCCIN_AUX
7 PCIE4_CRX_DTX0_P PERP0/SATA-B- N/C_15
45 46 CK223
1 0.22U_6.3V_K_X5R_0201 47 GND_9 N/C_16 48 1 2
7 PCIE4_CTX_DRX0_N PCIE4_CTX_DRX0_P PCIE4_CTX_C_DRX0_P PETN0/SATA-A- N/C_17 SSD1_RST_N SSD_RST_N
CK16 2 1 0.22U_6.3V_K_X5R_0201 49 50 RK460 1 @ 2 0_0201_5% EMC_NS@
7 PCIE4_CTX_DRX0_P PETP0/SATA-A+ PERST# SSD_CLKREQ_N
51 52 1
CLK_PCIE_SSD1_N GND_10 CLKREQ# SSD_CLKREQ_N 18 0.1U_6.3V_K_X5R_0201
53 54 1
19 CLK_PCIE_SSD1_N CLK_PCIE_SSD1_P REFCLKN PEWAKE#
55 56 @ CK41
19 CLK_PCIE_SSD1_P REFCLKP N/C_18
+3VS_SSD1
57 58 TPK2 1000P_0402_50V_X7R_0402
GND_11 N/C_19 2 +5VALW +3VS
1
59 NC NC 60 CK233
RK18 61 NC NC 62 1 2
10K_0201_5% @ 63 NC NC 64 EMC_NS@
65 NC NC 66
67 68 SUSCLK_SSD1 RK22 1 @ 2 0_0201_5% SUSCLK 0.1U_6.3V_K_X5R_0201
SUSCLK 21,63,71
2
PEDET 69 N/C_1 SUSCLK 70

71 PEDET 3.3V_7 72 +3VS_SSD1
73 GND_12 3.3V_8 74 +3VALW +3VALW
Only support PCIE SSD 75 GND_13 3.3V_9
GND_14 1 1 1
1
@
PEDET (PE_DTCT) RK14 77 76 CK42 CK36 CK143 2 2
10K_0201_5% @ PEG1 PEG2
2
SATA Device GND 2 2 2 CK224 CK225
2
EMC_NS@
EMC_NS@
PCIe Device Open
0.01U_0201_10V6K
0.1u_0201_10V6K
22UC_6.3VC_MC_X5RC_0603
ME@
2
1 1
0.1U_6.3V_K_X5R_0201
0.1U_6.3V_K_X5R_0201
DEREN_40-42329-067B3RHF-L
M.2 SSD(SATA/PCIE Gen3 from PCH)

+3VS
+3VS_SSD0
Need short
J7 @
2 1 Min 3A
2 1
2.2P_25V_C_COG_0201
0.1U_6.3V_K_X5R_0201
0.1U_6.3V_K_X5R_0201
12P_50V_J_NPO_0201
JUMP_43X79
10U 6.3V M X5R 0402
10U 6.3V M X5R 0402
1 1 1 1 1 1
CK213
CK214
CK215
CK216
CK220
CK221
RF_NS@
RF_NS@
@ @
2 2 2 2 2 2
NGFF
JSSD0 +3VS_SSD0
3 3
1 2
3 GND_1 3.3V_1 4
PCIE_PRX_DTX9_N 5 GND_2 3.3V_2 6
16 PCIE_PRX_DTX9_N PCIE_PRX_DTX9_P PERN3 N/C_2
7 8
16 PCIE_PRX_DTX9_P PERP3 N/C_3
9 10
PCIE_PTX_DRX9_N CK12 2 PCIE_PTX_C_DRX9_N
1 0.22U_6.3V_K_X5R_0201 11 GND_3 DAS/DSS# 12
16 PCIE_PTX_DRX9_N PCIE_PTX_DRX9_P PCIE_PTX_C_DRX9_P PETN3 3.3V_3
CK13 2 1 0.22U_6.3V_K_X5R_0201 13 14
16 PCIE_PTX_DRX9_P PETP3 3.3V_4
15 16
PCIE_PRX_DTX10_N 17 GND_4 3.3V_5 18 +3VS_SSD0
16 PCIE_PRX_DTX10_N PCIE_PRX_DTX10_P PERN2 3.3V_6
19 20
21 22
1 0.22U_6.3V_K_X5R_0201 23 GND_5 N/C_5 24
16 PCIE_PTX_DRX10_N PETN2 N/C_6
1
PCIE_PTX_DRX10_P CK11 2 PCIE_PTX_C_DRX10_P
1 0.22U_6.3V_K_X5R_0201 25 26
16 PCIE_PTX_DRX10_P PETP2 N/C_7
27 28 RK2
PCIE_PRX_DTX11_N 29 GND_6 N/C_8 30 10K_0201_5% @
16 PCIE_PRX_DTX11_N PCIE_PRX_DTX11_P PERN1 N/C_9
31 32
33 34
DK1
2
1 0.22U_6.3V_K_X5R_0201 35 GND_7 N/C_11 36
16 PCIE_PTX_DRX11_N PCIE_PTX_DRX11_P PCIE_PTX_C_DRX11_P PETN1 N/C_12 DEVSLP_R
CK9 2 1 0.22U_6.3V_K_X5R_0201 37 38 2 1 DEVSLP
16 PCIE_PTX_DRX11_P PETP1 DEVSLP DEVSLP 18
39 40 @
PCIE_SATA_PRX_DTX12_P 41 GND_8 N/C_13 42
16 PCIE_SATA_PRX_DTX12_P PERN0/SATA-B+ N/C_14
1
PCIE_SATA_PRX_DTX12_N 43 44 RB521CM-30T2R_VMN2M-2
16 PCIE_SATA_PRX_DTX12_N PERP0/SATA-B- N/C_15
45 46 RK4
PCIE_SATA_PTX_DRX12_N CK1 2 PCIE_SATA_PTX_C_DRX12_N
1 0.22U_6.3V_K_X5R_0201 47 GND_9 N/C_16 48 10K_0201_5% @
16 PCIE_SATA_PTX_DRX12_N PCIE_SATA_PTX_DRX12_P PCIE_SATA_PTX_C_DRX12_P PETN0/SATA-A- N/C_17 SSD0_RST_N SSD_RST_N
CK7 2 1 0.22U_6.3V_K_X5R_0201 49 50 RK461 1 @ 2 0_0201_5%
16 PCIE_SATA_PTX_DRX12_P PETP0/SATA-A+ PERST# SSD_CLKREQ0_N
51 52
SSD_CLKREQ0_N 20
2
CLK_PCIE_SSD0_N 53 GND_10 CLKREQ# 54 1
19 CLK_PCIE_SSD0_N REFCLKN PEWAKE# 1
CLK_PCIE_SSD0_P 55 56 @ CK124
19 CLK_PCIE_SSD0_P REFCLKP N/C_18
57 58 TPK1 1000P_0402_50V_X7R_0402
+3VS_SSD0 GND_11 N/C_19
59 NC NC 60 2
61 NC NC 62
1
63 NC NC 64
RK6 65 NC NC 66
10K_0201_5% 67 68 SUSCLK_32K_R RK23 1 @ 2 0_0201_5% SUSCLK
SUSCLK 21,63,71
69 N/C_1 SUSCLK 70
SSD_DET_N RK15 1 @ 2 0_5%_0603 SSD_DET_N_R 71 PEDET 3.3V_7 72 +3VS_SSD0
18 SSD_DET_N
2
73 GND_12 3.3V_8 74
75 GND_13 3.3V_9
GND_14
1 1 1
0.01U_0201_10V6K
0.1u_0201_10V6K
22UC_6.3VC_MC_X5RC_0603
77 76
PEG1 PEG2
1
CK28
CK22
CK27
@
PEDET (PE_DTCT) RK7

10K_0201_5% @ 2 2 2
4
SATA Device GND DEREN_40-42329-067B3RHF-L
4
PCIe Device Open ME@

2
SSD_DET#
0 - SATA
1 - PCIE
Issued Date 2021/04/07 Deciphered Date 2021/04/07 NGFF WLAN
A
Vinafix.com
B C
D
Custom
Date:
HY568
E
Sheet 63 of 110
Rev
0.1
5 4 3 2 1
Digital Power for Digital I/O Circuit

+1.8VALW DVDD_IO +3VS
Digital Power for Core DVDD
Digital Power for HDA Link
66,69 CODEC_SPK_LP
RA1 1 @ 2 0_0402_5% RA2 1 @ 2 0_0402_5%
0.1U_6.3V_K_X5R_0201
+1.8VS 66,69 CODEC_SPK_LN
2.2U_0402_6.3V6M
0.1U_6.3V_K_X5R_0201
10U 6.3V M X5R 0402

MIC2_VREFOL
1 2 66,69 CODEC_SPK_RN MIC2_VREFOL 69
CA1
RA3 1 @ 2 0_0402_5% 2 1
470P_0201_25V_X7R_0201
470P_0201_25V_X7R_0201
470P_0201_25V_X7R_0201
470P_0201_25V_X7R_0201
CA2
CA3
CA4
RING2
66,69 CODEC_SPK_RP RING2 69
2 1
CA5
CA6
@ 1 1 1 1
1 2 MIC2_VREFOR
CA401
CA402
CA403
CA404
1 2 MIC2_VREFOR 69
SLEEVE
2 2 2 2 SLEEVE 69
1U_6.3V_M_X5R_0201
0.47U 6.3V K X5R 0201
D 2 1 D
Close to Pin18 CBP1 CA7 1 2 1U_6.3V_M_X5R_0201
CBN1
+5VS LA1 +5VD CBP2 CA8 1 2 1U_6.3V_M_X5R_0201

EMC_NS@ +5VS +5VA
BTL Analog Power
1 2 Analog Power for IO CBN2
MIC2_VREFOR
MIC2_VREFOL
BLM15PD600SN1D_2P
RA4 1 @ 2 0_0402_5%
MIC2_CAP
10U_10V_M_X5R_0402
10U_10V_M_X5R_0402
0.1U_10V_K_X5R_0402
0.1U_10V_K_X5R_0402
HPOUT_R
PC_BEEP
HPOUT_L
HPOUT_L
1U_10V_M_X5R_0201
RA5 1 @ 2 0_0805_5% 1 1 1 1
SLEEVE
HPOUT_L 69
CPVPP
0.1u_0201_10V6K
CA9
CA10
CA11
CA12
RING2
CBN1
CBP1
CBP2
HPOUT_R
CA13
CA14
1 1 HPOUT_R 69
2 2 2 2 @ Vendor update MPN to ALC3306-VA1-CG
2 2 New LCFC PN is SA0000ARR00 AI AI AI AO AO
36
35
34
33
32
31
30
29
28
27
26
25
Use vitural symbol untill new CIS symbol update
UA1
HPOUT-R
MIC2-VREFO-R
PCBEEP
MIC2-CAP
MIC2-R/SLEEVE
CPVPP
HPOUT-L
CBN1
CBP1
CBP2
MIC2-L/RING2
MIC2-VREFO-L
37 24 CBN2
+1.8VS +1.8V_AUDIO AVSS1 CBN2
Analog power for DACs, ADCs CA15 1 2 0.47U 6.3V K X5R 0201 VREF_CAP 38 23 CPVEE CA16 1 2 1U_6.3V_M_X5R_0201
RA6 1 @ 2 0_0402_5% VREF CPVEE
LDO1_CAP
0.1U_6.3V_K_X5R_0201
CA17 1 2 4.7U_0402_6.3V6M 39 22
LDO1-CAP AVSS2
2.2U_0402_6.3V6M
2 2
+1.8VALW LDO2_CAP
CA19
CA20
+5VA
40 21 CA18 1 2 4.7U_0402_6.3V6M
AVDD1 LDO2-CAP
RA7 1 @ 2 0_0402_5% 41 20
1 1 +5VD PVDD1 AVDD2 +1.8V_AUDIO
CODEC_SPK_LP RA408 1 2 0_0603_5% SPK_LP LDO3_CAP
@ AO42 19 CA21 1 2 4.7U_0402_6.3V6M
I2S-EN/SPDIF-OUT/GPIO2/DMIC-DATA34
66,69 CODEC_SPK_LP SPK-OUT-L+ LDO3-CAP
CODEC_SPK_LN RA409 1 2 0_0603_5% SPK_LN
@ AO43 18
C Codec Only 66,69
66,69
CODEC_SPK_LN
CODEC_SPK_RN
CODEC_SPK_RN RA410 1 @ 2 0_0603_5% SPK_RN
AO44
SPK-OUT-L-
SPK-OUT-R-
DVDD-IO
SDATA-OUT
17 DI
DVDD_IO
HDA_SDOUT_AUDIO
HDA_SDOUT_AUDIO 18
C
CODEC_SPK_RP RA411 1 2 0_0603_5% SPK_RP 16 DIO HDA_SDI

66,69 CODEC_SPK_RP
@ AO45 SPK-OUT-R+ SDATA-IN
RA8 1 2 33_0402_5%
HDA_SDIN0 18
46 15 DI HDA_SYNC_AUDIO
+5VD PVDD2 SYNC HDA_SYNC_AUDIO 18
GPIO0/DMIC-DATA12
1 2 0_0201_5% HDA_BITCLK_AUDIO
69 PLUG_IN
RA9 @ JD1 DI 47 JD1 BCLK
14 DI
HDA_BITCLK_AUDIO 18
GPIO1/DMIC-CLK
I2S-MCLK/GPIO3
DI 48 JD2/GPIO4 DC-DET/EAPD
13
DVDD 49
I2C-DATA
I2S-LRCK
I2S-BCLK
Thermal Pad
I2S-OUT
I2C-CLK
internal pull
I2S-IN
DVDD
high to DVDD
PDB
1
@ RA10 ALC3306-VA1-CG_QFN48_6X6
10
11
12
10K_0201_5% DIO DI DIO DIO DODDOD DIDO DIO DIO DIO
DA1
2
1 2 SPK_MUTE_N
79 EC_MUTE_N SPK_MUTE_N
Codec_I2C_DAT
Codec_I2C_CLK
1
LRB751V-40T1G_SOD323-2
DVDD
RA12 1 @ 2 0_0402_5% @ RA11
100K_0201_5% RA13 1 @ 2 0_0201_5% CODEC_DMIC_DAT_R
47 CODEC_DMIC_DAT
2
RA14 1 @ 2 0_0201_5% CODEC_DMIC_CLK_R

47 CODEC_DMIC_CLK
DA2 @ DVDD
2 1PC_BEEP1 RA15 1 2 PC_BEEP_R 0.1U_6.3V_K_X5R_0201 1 2 CA22 PC_BEEP
20 PCH_BEEP DVDD
1K_0201_5%
1
B LRB751V-40T1G_SOD323-2 B
RA16
2
1
10K_0201_5%
RA17 1 @ 2 0_0201_5% RPA3
@ 2.2K_0404_4P2R_5%
2
2
@
G1
3
4
Codec_I2C_DAT 1 6 RA422 1 @ 2 0_0201_5%
S1 D1 RGB_I2C_SDA 80
HDA_BCLK_EMC_RC RA20 1 2 EMC@ HDA_BITCLK_AUDIO

QA1A
1/16W_27_5%_0402 PJT7838_SOT363-6
5
HDA_SYNC_AUDIO CODEC_DMIC_CLK_R @
G2
HDA_SDOUT_AUDIO
HDA_SDIN0 CODEC_DMIC_DAT_R Codec_I2C_CLK 4 3 RA423 1 @ 2 0_0201_5%
S2 D2 RGB_I2C_SCL 80
15P_50V_J_NPO_0201
22P_0201_258J
22P_0201_258J
33P_50V_J_NPO_0201
100P 25V J NPO 0201
100P 25V J NPO 0201

EMC@
EMC@
EMC_NS@
EMC_NS@
EMC_NS@
1 1 1 1 1 1 QA1B
CA23
CA24
CA25
CA79
CA80
CA81
PJT7838_SOT363-6
2 2 2 2 2 2
EMC_NS@
DVDD
RA22 1 @ 2 100K_0201_5% JD1
@
CA84 1 2 0.1U_6.3V_K_X5R_0201 JD1
A RA29 1 @ 2 0_0402_5% A
RA30 1 @ 2 0_0402_5%
RA31 1 @ 2 0_0402_5%
RA210 1 @ 2 0_0402_5%
GND GNDA Security Classification LCFC Highly Confidential Information Title
Issued Date 2019/11/06 Deciphered Date 2019/11/05 Yoga C750-TGL

Vinafix.com
C 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Audio_Codec
5 4 3 2 1
5 4 3 2 1
SPK L+ L- R+ R- trace width

Speaker 4 ohm ==> 40 mils
Speaker 8 ohm ==> 20 mils
Speaker JSPK1
LA6 1 2 PBY160808T-800Y-N_2P SPK_RP_CONN 1

66 CODEC_SPK_RP SPK_RN_CONN 1
LA7 1 2 PBY160808T-800Y-N_2P 2
66 CODEC_SPK_RN SPK_LN_CONN 2
LA8 1 2 PBY160808T-800Y-N_2P 3 5
D 66 CODEC_SPK_LN SPK_LP_CONN 3 GND1 D
LA9 1 2 PBY160808T-800Y-N_2P 4 6
66 CODEC_SPK_LP 4 GND2
ME@
1500P_25V_K_X7R_0201
1500P_25V_K_X7R_0201
1500P_25V_K_X7R_0201
1500P_25V_K_X7R_0201
1 1 1 1
CA571
CA570
CA569
CA568
2 2 2 2
As EMC suggestion to reserve 1500P CAP

Close to CONN
C C
MIC2_VREFOL RA401 2 1 1/20W_2.2K_5%_0201

66 MIC2_VREFOL
RING2
66 RING2
HPOUT_L RA402 1 2 56_0402_1% HPOUT_L_CONN
66 HPOUT_L
HPOUT_R RA403 1 2 56_0402_1% HPOUT_R_CONN
Audio Jack JHP1
66 HPOUT_R
RING2 2
SLEEVE G/M
66 SLEEVE
4
MIC2_VREFOR RA404 2 1 1/20W_2.2K_5%_0201 GND
66 MIC2_VREFOR
PLUG_IN
66 PLUG_IN PLUG_IN 5
DET
SLEEVE RA405 CA407

RING2 0_0402_5% 470P_50V_K_X7R_0201
HPOUT_L_CONN EMC_NS@ 1 2 HP_OUTL_C
1 2 EMC_NS@ HPOUT_L_CONN HPOUT_L_CONN 6
B HPOUT_R_CONN L B
PLUG_IN
HPOUT_R_CONN
DA401
AZ5123-01F.R7GR_DFN1006P2X2
DA402
DA403
DA404
DA405
RA406 CA408 3
0_0402_5% 470P_50V_K_X7R_0201 R
1
HP_OUTR_C HPOUT_R_CONN
47P_25V_J_NPO_0201
EMC_NS@ 1 2 1 2 EMC_NS@
1 SLEEVE 1
1
M/G
CA409
EMC_NS@
EMC_NS@
EMC_NS@
EMC_NS@
EMC@
EMC@
10U 6.3V M X5R 0402
10U 6.3V M X5R 0402

CA410 1 2
CA405
CA406
100P 25V J NPO 0201 RIYUE-3F213-00J02_6P-T
2 2 1 EMC@ SLEEVE
ME@
2
2 1
2
CA411 @ @
100P 25V J NPO 0201
2 1 EMC@ RING2
A A
Issued Date 2019/11/06 Deciphered Date 2019/11/05 Yoga C750-TGL
5
Vinafix.com 4 3
2
C
Size
Date:
Document Number
Audio_SPK/Jack
1
Sheet 69 of 110
Rev
0.2
5 4 3 2 1
Mini-Express Card(WLAN/WiMAX)
+3V_WLAN
JWLAN1 +3VS
1 2
USB20_14_P 3 GND1 3.3VAUX1 4
17 USB20_14_P USB20_14_N USB_D+ 3.3VAUX2
49.9K_0402_1%
D 5 6 D
17 USB20_14_N 7 USB_D- LED1# 8
1
CNVI_WR_D1_N 9 GND2 PCM_CLK/I2S_SCK 10 CNVI_RF_RESET_N_R RN40 1 2 33_0402_5%
19 CNVI_WR_D1_N CNVI_WR_D1_P 11 SDIO_CLK PCM_SYNC/I2S_WS 12 CNVI_RF_RESET_N 20
RN11
19 CNVI_WR_D1_P 13 SDIO_CMD PCM_IN/I2S_SD_IN 14
CNVI_WR_D0_N 15 SDIO_DATA0 PCM_OUT/I2S_SD_OUT 16 CNVI_MODEM_CLKREQ 20
19 CNVI_WR_D0_N CNVI_WR_D0_P 17 SDIO_DATA1 LED#2 18
19 CNVI_WR_D0_P
2
19 SDIO_DATA2 GND11 20
CNVI_WR_CLK_N 21 SDIO_DATA3 UART_WAKE# 22 CNVI_BRI_RSP_R RN13 1 CNVI@ 2 49.9_0402_1%
19 CNVI_WR_CLK_N CNVI_WR_CLK_P 23 SDIO_WAKE# UART_RXD CNVI_BRI_RSP 18 PCH_UART2_RXD 20
19 CNVI_WR_CLK_P SDIO_RESET# +3VS
49.9K_0402_1%
KEY E
1
25 PIN24~PIN31 NC PIN 24
27 26
RN12
29 28
31 30
+3V_WLAN
2
+3VS 33 32
PCIE_PTX_C_DRX14_P GND3 UART_TXD CNVI_RGI_RSP_R CNVI_RGI_DT 18 PCH_UART2_TXD 20
CN8 1 2 0.1u_0201_10V6K 35 34 RN14 1 CNVI@ 2 49.9_0402_1%
2
16 PCIE_PTX_DRX14_P 1 2 0.1u_0201_10V6K PCIE_PTX_C_DRX14_N 37 PETP0 UART_CTS 36 CNVI_RGI_RSP 18
CN9
16 PCIE_PTX_DRX14_N 39 PETN0 UART_RTS 38 CL_RST_N_WLAN EC_TX CNVI_BRI_DT 18
RN6 RN15 1 @ 2 0_0402_5%
41 GND4 VENDOR_DEFINED1 40 CL_DAT_WLAN RN16 1 2 0_0402_5% EC_RX
AOAC Co-Design 10K_0402_5%
16 PCIE_PRX_DTX14_P PERP0 VENDOR_DEFINED2
@
43 42
16 PCIE_PRX_DTX14_N
1
45 PERN0 VENDOR_DEFINED3 44
1
47 GND5 COEX3 46 +3V_WLAN
19 CLK_PCIE_WLAN_P 49 REFCLKP0 COEX2 48 CRB: 33ohm
19 CLK_PCIE_WLAN_N 51 REFCLKN0 COEX1 50 SUSCLK_R RN17 1 2 33_0402_5%
3 WLAN_CLKREQ_CONN_N 53 GND6 SUSCLK 52 WLAN_PERST_N SUSCLK 21,63
20 WLAN_CLKREQ_N 2 RN33 1 @ 2 0_0201_5%
PCIE_WAKE_N_WLAN CLKREQ0# PERST0# BT_OFF_N 2 0_0402_5% PCH_BT_OFF_N PLT_RST_N 20,31,63,73,78,79
D
55 54 RN18 1 @
57 PEWAKE0# W_DISABLE2# 56 WLAN_OFF_N 2 0_0402_5% PCH_WLAN_OFF_N PCH_BT_OFF_N 20 PCH_BT_OFF_N
@ RN19 1 @ RN5 1 2 10K_0201_5%
QN2 GND7 W_DISABLE1# PCH_WLAN_OFF_N 20 PCH_WLAN_OFF_N 1 2 10K_0201_5%
RN4
L2N7002KN3T5G_SOT883-3
CNVI_WT_D1_N 59 58 WLAN_SMB_DATA RN20 1 @ 2 0_0402_5% EC_RX
19 CNVI_WT_D1_N CNVI_WT_D1_P 61 RSRVD/PETP1 I2C_DATA 60 WLAN_SMB_CLK EC_TX EC_RX 79 WLAN_SMB_CLK
If PCH side PU stuff, RN21 1 @ 2 0_0402_5% RN22 1 2 100K_0402_5%
19 CNVI_WT_D1_P 63 RSRVD/PETN1 I2C_CLK 62 EC_TX 79
then NC RN6 and stuff QN2; CNVI_WT_D0_N GND8 ALERT#
If PCH side PU un-stuff, RN7 1 @ 2 0_0402_5% 65 64 REFCLK0 1 TP107
19 CNVI_WT_D0_N CNVI_WT_D0_P 67 RSRVD/PERP1 RSRVD 66
then stuff RN6and NC QN2. Test_Point_12MIL
19 CNVI_WT_D0_P 69 RERVD/PERN1 UIM_SWP/PERST1# 68 +3V_WLAN
+3V_WLAN
CNVI_WT_CLK_N 71 GND9 UIM_POWER_SNK/CLKREQ1# 70
19 CNVI_WT_CLK_N CNVI_WT_CLK_P 73 RSRVD/REFCLKP1 UIM_POWER_SRC/GPIO1/PEWAKE1# 72
19 CNVI_WT_CLK_P 75 RSRVD/REFCLKN1 3.3VAUX3 74
2
GND10 3.3VAUX4
RN8 77 76
CNVI@ GND15 GND14
10K_0201_5%
1 ARGOS_NASE0-S6701-TS40
RN10 1 @ 2 0_0402_5% PCIE_WAKE_N_WLAN
18 PCH_PCIE_WAKE_N_WLAN ME@
C RN35 1 @ 2 0_0402_5% C
79 EC_WLAN_WAKE_N
+1.8VALW
+3VS +3V_WLAN
JN9 Don't short RN38 1 @ 2 10K_0201_5% CNVI_BRI_DT RN39 1 2 10K_0201_5%

1 2
1 2 JUMP_43X79 RN36 1 2 CNVI_RGI_DT RN37 1 @ 2 2.2K_0402_5%
@ 1/20W_20K_5%_0201
+3VALW_SYS
1
JN10Need short
2
PCH Strap Pin
1 2 JUMP_43X79
100U_1206_6.3V6M
10U 6.3V M X5R 0402
0.1U_6.3V_K_X5R_0201
1U_6.3V_M_X5R_0201
10U 6.3V M X5R 0402
0.1U_6.3V_K_X5R_0201
1U_6.3V_M_X5R_0201
@ 1 1 1 1 1 1 1
CN1
CN2
CN3
CN4
CN5
CN6
CN7
+3VALW_SYS CNVI
+3VALW_SYS
2 2 2 2 2 2 2 *
This strap does not have an internal pull-up or
@ @ @
GPP_J4 / pull-down. A weak external pull-up is required.
1
@
UN1
CNV_RGI_DT / 0 >Integrated CNVi enabled.
@ RN29 5 1 RN11 @ 2 1/10W_0_5%_0603 1 >Integrated CNVi disabled.
75K_0402_5% IN OUT UART0_TXD
2
2
GND
WLAN_PWR_EN 1
CN20
0.01U_0402_25V7K
RN27 1 @ 2 0_0402_5% 4 3 This strap has a 20 kohm ± 30% internal pull-down.
71,79,80,93 SUSP_N EN OCB @ Close to Pin2/Pin4 Close to Pin72/Pin74 This strap should not be pulled high since 24 MHz
1 GPP_J2 / crystal is not supported on the PCH.
1
@ D SY6288C20AAC_SOT23-5 2
18 CNVI_EN_N
2
G
QN1
2N7002KW_SOT323-3 @ RN28
CNV_BRI_DT / 0 38.4 MHz (default)
UART0_RTS# 1 24 MHz
1
200K_0402_5%
S Notes: 1. The internal pull-down is disabled
3
2
@ RN30 after RSMRST# de-asserts.
75K_0402_5% 2. This signal is in the primary well.
2
B B
RN31 1 @ 2 0_0402_5%
21 PM_SLP_WLAN_N
RN32 1 @ 2 0_0402_5%
71,79,80,93 SUSP_N
1
@
CN21
0.033U_25V_K_X7R_0402
2
A A
Vinafix.com
Issued Date 2021/04/07 Deciphered Date 2021/04/07 CNVi
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
D
Yx60 0.1

5 4 3 2 1
5 4 3 2 1
+3VALW TO +3VALW_LAN
+3VALW_LAN rising time (10%~90%): +3VALW_LAN +LAN_VDDREG
+3VALW_SYS +3VALW_LAN
0.5ms＜spec＜100ms
Need short RL1 1 21/10W_0_5%_0603
JL1
D
1 2 width : 40 mils D
1 2
1 1
@ JUMP_43X79 CL1 CL2
4.7U_0402_6.3V6M 0.1U_6.3V_K_X5R_0201
+3VALW_SYS
0.1U_6.3V_K_X5R_0201
0.1U_6.3V_K_X5R_0201
QL1 8111GUL@ 8111GUL@
2 2
1 1 1 1
0.1U_6.3V_K_X5R_0201
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
3
D
1 CL4 CL5 CL6 CL7
2
RL2 LP2301ALT1G_SOT-23-3 @ @
100K_0201_5% 1 @ 1
2 2 2 2
0.01U_0201_10V6K
@ CL8 CL9
G
2
@
@
Note: CL1,CL2 can be remove for LDO mode.
1
RL3 2 2
1 @ 2 LAN_PWR_ON_N_R
20 LAN_PWR_ON_N
1/20W_47K_5%_0201
Close to Pin11 Close to Pin32 Close to Pin11 Close to Pin32 +3VALW_LAN +3VS
+3VALW_LAN
2
RL5 RL4 QL2
G
@ 2N7002KW_SOT323-3
10K_0201_5% 10K_0201_5% @
UL1
2
2
RL7 1 @ 2 0_0201_5% PCIE_WAKE_N_R LAN_CLKREQ_N_R 1 3
17,79 PCIE_WAKE_N LAN_CLKREQ_N 20
RL6 1 @ 2 0_0201_5%
S
79 EC_LAN_WAKE_N
RL13 1 @ 2 0_0201_5%
33
+3VALW_LAN 32 GND 16 CLK_PCIE_LAN_N
AVDD33_2 REFCLK_N CLK_PCIE_LAN_P CLK_PCIE_LAN_N 19
RSET RL8 1 2 31 15
+LAN_VDD10 RSET REFCLK_P PCIE_PTX_C_DRX15_N CLK_PCIE_LAN_P 19
2.49K_0402_1% 30 14 CL33 1 2 0.1u_0201_10V6K
LAN_XTALO AVDD10 HSIN PCIE_PTX_C_DRX15_P PCIE_PTX_DRX15_N 16
29 13 CL34 1 2 0.1u_0201_10V6K
LAN_XTALI CKXTAL2 HSIP LAN_CLKREQ_N_R PCIE_PTX_DRX15_P 16
28 12
+3VS @ TL2 1 LAN_LED0 27 CKXTAL1 CLKREQB 11 +3VALW_LAN
C C
LAN_PWR_ON_N RL12 1 @ 2 LAN_DISABLE_N 26 LED0 AVDD33_1 10 LAN_MDI3_N
LAN_LED2 LED1/GPO MDIN3 LAN_MDI3_P LAN_MDI3_N 74
0_0201_5% @ TL3 1 25 9
LED2 MDIP3 LAN_MDI3_P 74
1
+LAN_REGOUT 24 8 +LAN_VDD10
RL9 +LAN_VDDREG 23 REGOUT AVDD10_2 7 LAN_MDI2_N
+LAN_VDD10 VDDREG MDIN2 LAN_MDI2_P LAN_MDI2_N 74
1/20W_1K_1%_0201 22 6
PCIE_WAKE_N_R DVDD10 MDIP2 LAN_MDI1_N LAN_MDI2_P 74
21 5
ISOLATE_N LANWAKEB MDIN1 LAN_MDI1_P LAN_MDI1_N 74
20 4
LAN_MDI1_P 74
2
PLT_RST_N RL27 1 2 1K_0201_5% LAN_RST_N 19 ISOLATEB MDIP1 3 +LAN_VDD10

20,31,52,55,63,71,78,79 PLT_RST_N PCIE_PRX_C_DTX15_N PERSTB AVDD10_1 LAN_MDI0_N
CL10 1 2 0.1u_0201_10V6K 18 2
ISOLATE_N RL10 1 @ 2 LAN_PWR_ON_N 16 PCIE_PRX_DTX15_N
CL11 1 2 0.1u_0201_10V6K PCIE_PRX_C_DTX15_P 17 HSON MDIN0 1 LAN_MDI0_P LAN_MDI0_N 74 2018/01/24: add AZ5815-01F.R7GR for
16 PCIE_PRX_DTX15_P HSOP MDIP0 LAN_MDI0_P 74 RTL8111H Lan Surge issue
0_0201_5%
CL10 close to Pin18
1
+LAN_VDD10
CL11 close to Pin17
@ RL11
1/20W_15K_5%_0201
1
2
1
RTL8111H-CG_QFN32_4X4 DL4
AZ5815-01FPR7GR_DFN1006P2E-2
2
04/03 add AZ5815_bron
@
2
02/19 Update AZ5825 dual dircetion for 8111H
LAN_XTALI
RL25
LAN_XTALO_R 1 2 LAN_XTALO
YL1
1K_0201_5%
1 4
OSC1 GND2
2 3
GND1 OSC2
B B
25MHZ_10PF_7V25000014
1 1 For RTL8111GUL(SWR mode, reserved)
CL12 CL13
15P_0402_50V8J 15P_0402_50V8J For RTL8111H (LDO mode)
2 2 +LAN_VDD10
LL1 1 2 8111GUL@
2.2UH_NLC252018T-2R2J-N_5%
+LAN_REGOUT RL26 1 2 8111H@

0_0805_5%
1 1
0.1U_6.3V_K_X5R_0201
0.1U_6.3V_K_X5R_0201
0.1U_6.3V_K_X5R_0201
0.1U_6.3V_K_X5R_0201
0.1U_6.3V_K_X5R_0201
1 CL14 CL15
CL3 4.7U_0402_6.3V6M 0.1U_6.3V_K_X5R_0201 1 1 1 1 1 1
1U_10V_M_X5R_0201
0.1U_6.3V_K_X5R_0201 8111GUL@ 8111GUL@ CL16 CL17 CL18 CL19 CL20 CL21
8111H@ 2 2
2
2 2 2 2 2 2
Layout Note: LL1 must be

within 200mil to Pin24,
CL15,CL14 must be within
200mil to LL1 Close to Pin3, 8, 22, 30 Close to Pin22(Reserved)
+LAN_REGOUT: Width =60mil
A A
Issued Date 2019/07/02 Deciphered Date 2020/02/24 LAN_RTL8111GUL_H
5
Vinafix.com
4 3
2
C
Size
Date:
Document Number
LAN
1
Sheet 73 of 110
Rev
1.0
5 4 3 2 1
DL1/DL2 TL1
D
1'S PN:SC300008P00 1:1 24 LAN_MDO3_N
D
LAN_MDI3_N T1/B MX1+ LAN_MDO3_N 75

Place Close to TL1 1
73 LAN_MDI3_N TD1+
23 LAN_MDO3_P
MX1- LAN_MDO3_P 75
LAN_MDI3_P 2
73 LAN_MDI3_P TD1-
TDCT 3 22
TCT1 T1/A MCT1
DL1
LAN_MDI3_N 4 3 LAN_MDI2_N 4 21
I/O3 I/O2 TCT2 1:1 MCT2 LAN_MDO2_N
20
5
73 LAN_MDI2_N TD2+
5 2
VDD GND
19 LAN_MDO2_P
LAN_MDI2_P MX2- LAN_MDO2_P 75
6
73 LAN_MDI2_P TD2-
LAN_MTC
LAN_MDI3_P 6 1 LAN_MDI2_P
I/O4 I/O1
AZ1515-04S.R7G SOT23-6L-6 T1/A
EMC_8111H@ 1:1 18 LAN_MDO1_N
7
73 LAN_MDI1_N TD3+
17 LAN_MDO1_P
MX3- LAN_MDO1_P 75
LAN_MDI1_P 8
73 LAN_MDI1_P TD3-
DL2 9 16
LAN_MDI1_N 4 3 LAN_MDI0_N TCT3 T1/A MCT3
I/O3 I/O2
10 15
TCT4 1:1 MCT4 LAN_MDO0_N
T1/B
14
LAN_MDI0_N MX4+ LAN_MDO0_N 75
C 5 2 11 C
VDD GND 73 LAN_MDI0_N TD4+
2
LAN_MDI1_P 6 1 LAN_MDI0_P CL24 13 LAN_MDO0_P
I/O4 I/O1 LAN_MDI0_P MX4- LAN_MDO0_P 75
0.01U_25V_K_X5R_0201 12
1 73 LAN_MDI0_P TD4-
AZ1515-04S.R7G SOT23-6L-6
EMC@
EMC_8111H@
T1/A
BOTH_NA0069R-LF
1
RL17
20_0603_5%
1
EMC_NS@
DL3
1
LAN_MTC_R 2
BS401N-1_1206-2
EMC@
2
SCV00001Y00
2
RL14 1 @ 2 0_0402_5%
1 1
RL15 1 @ 2 0_0402_5% CL32 CL25
68P_0402_50V8J 1000P_1206_2KV7-K
RL16 1 @ 2 0_0402_5% EMC_NS@ EMC_NS@
2 2
RL24 1 @ 2 0_0402_5%
B
Reserve for EMI go rural solution B
CHASSIS1_GND
CHASSIS1_GND
A A

Vinafix.com
C
HY568 1.0

5 4 3 2 1
5 4 3 2 1
JRJ45
LAN_MDO3_N 8
D 74 LAN_MDO3_N BI_DD- D
LAN_MDO3_P 7
74 LAN_MDO3_P BI_DD+
LAN_MDO1_N 6
74 LAN_MDO1_N RX_DB-
LAN_MDO2_N 5
74 LAN_MDO2_N BI_DC-
LAN_MDO2_P 4
74 LAN_MDO2_P BI_DC+
LAN_MDO1_P 3
74 LAN_MDO1_P RX_DB+
LAN_MDO0_N 2
74 LAN_MDO0_N TX_DA-
LAN_MDO0_P 1 9
74 LAN_MDO0_P TX_DA+ GND_1
10
GND_2
ALLTOP_C10289-10839-L
ME@
CHASSIS1_GND
C C
B B
A A
Issued Date 2019/07/02 Deciphered Date 2020/02/24 LAN_Transformer

Vinafix.com HY568
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
5 4 3 2 1
5 4 3 2 1
Remove Force sense
Fintek(1 Local+2 Remote) thermal sensor +3VS +3VS
placed near DIMM

REMOTE+/-_R, REMOTE1+/-, REMOTE2+/-:
Trace width/space:10/10 mil
Trace length:<8"
2
+3VS Near CPU FAN RS17 RS18
US1 4.7K_0402_5% 4.7K_0402_5% REMOTE1+ Near GPU&VRAM REMOTE2+ Near CPU core
@ @ 1 1
1
C C
1
1 10 EC_SMB_CK2 2 2
CS5 QS15 CS6 QS16
VCC SCL EC_SMB_CK2 31,45,79,102
3300P_0402_50V7-K B MMBT3904WH_SOT323-3 3300P_0402_50V7-K B MMBT3904WH_SOT323-3
EC_SMB_DA2
1 REMOTE1+ 2 9 @ 2 E @ 2 E
3
DP1 SDA EC_SMB_DA2 31,45,79,102 REMOTE1- REMOTE2-
3 8 THEM_ALERT_N
CS7 @ REMOTE1- RS13 1 @ 2 0_0402_5%
.1U_0402_10V6-K DN1 ALERT# SMB1_ALERT_N 79
2 REMOTE2+ 4 7 THERM_L
D DP2 THERM# D
REMOTE2- 5 6
DN2 GND
F75303M_MSOP10
Near GPU&VRAM
Near CPU
+3VALW_SYS
+5VLP +5VLP
+5VLP +3VALW_SYS
HW thermal sensor
1
2
RS29 RS36
1
@ CS12 21.5K_0402_1% @ @ 21.5K_0402_1% @ RS19
0.1U_0603_25V7-M 13.7K_0402_1%
1
@ RS21
2
NTC_V1_GPU 13.7K_0402_1%
US18
2
1 8 TMSNS1 RS88 1 @ 2 0_0402_5% NTC_V1_GPU 79 NTC_V1_GPU
1
VCCTMSNS1 NTC_V2_CPU
2 7 1 2 10K_0402_5% 79 NTC_V2_CPU
PHYST1 RS9 @ RTS2
GNDRHYST1
@ 100K_0402_1%_TSM0B104F4251RZ
3 6 NTC_V2_CPU
TMSNS2 RS10 1 @ 2 0_0402_5%
OT1TMSNS2
1
4 5 PHYST2 RS11 1 @ 2 10K_0402_5%
79,91 EC_ON_3VALW_R OT2RHYST2
RTS3
G718TM1U_SOT23-8 @ 100K_0402_1%_TSM0B104F4251RZ
2
@
RS20
2
@ 0_0402_5%
over temperature threshold:
RSET=3*RTMH
1
92+/-30C
Hysteresis temperature threshold.
RHYST=(RSET*RTML)/(3*RTML-RSET)
56+/-30C
for layout optimized, change the EC_AGND to GND
Near DIMM
Nuvoton(1 Local+2 Remote) thermal sensor +3VS +3VS +3VS +3VALW_SYS
1side placed VRAM backside
1
+3VS
2
@ RS22
RS93 RS92 13.7K_0402_1%
2.2K_0402_5% 2.2K_0402_5%
2
2
2
+3VS NTC_V3_DIMM
RS91 RS14
G
Near PCH
1
US134 4.7K_0402_5% @ @ 4.7K_0402_5% 79 NTC_V3_DIMM
1
THM_SMCLK THM_SMCLK EC_SMB_CK0
1
1 10 1 6
S
VCC SCL EC_SMB_CK0 79,80,82
D
RTS4
NT_REMOTE1_P THM_SMDAT
5
2 9 @
G
1 100K_0402_1%_TSM0B104F4251RZ
DP1 SDA QS22A
NT_REMOTE1_N 3 8 SMB1_ALERT_N
CS13 @ RS15 1 @ 2 0_0402_5% 2N7002KDWH_SOT363-6
2
DN1 ALERT#
.1U_0402_10V6-K
2 NT1_REMOTE1_P 4 7 THM_SMDAT 4 3 EC_SMB_DA0
S
DP2 THERM# EC_SMB_DA0 79,80,82
D
NT1_REMOTE1_N 5 6
2
C DN2 GND QS22B C
2N7002KDWH_SOT363-6 RS23 RS12
F75303M_MSOP10 @ 0_0402_5% @ 0_0402_5%
1
EC_AGND
Near VRAM high Temp side
NT_REMOTE1_P
NT_REMOTE1_P 78
NT_REMOTE1_N NT1_REMOTE1_P
NT_REMOTE1_N 78
1
1
C
CS14 2 QS17
Thermal Diode Near GPU FAN(DB) 3300P_0402_50V7-K B MMBT3904WH_SOT323-3
@ 2 E
NT_REMOTE1+/-:
3
NT1_REMOTE1_N
Trace width/space:10/10 mil
Trace length:<8"
Remove TOF senser
B B
A A
Vinafix.com Security Classification LC Future Center Secret Data Title

E
HY568 0.1

5 4 3 2 1
5 4 3 2 1
D D
C C
FAN Conn Right

FAN Conn LEFT
+5VS
+5VS
JFAN1 JFAN2
RF52 1 @ 2 0_5%_0603 +5VS_FAN1 1 RF75 1 @ 2 0_5%_0603 +5VS_FAN2 1
2 1 2 1
79 EC_FAN1_SPEED 2 79 EC_FAN2_SPEED 2
1 79 EC_FAN1_PWM
3 1 79 EC_FAN2_PWM
3
3 3
1
1
4 4
CF8 @ CF9 5 4 CF11 @ CF10 5 4
10U_0805_25V6K 0.1U_25V_K_X5R_0402 6 G1 10U_0805_25V6K 0.1U_25V_K_X5R_0402 6 G1
2
2
2 G2 2 G2
CVILUX_CI4404M1HRT-NH CVILUX_CI4404M1HRT-NH
ME@ ME@
B B
A A
Issued Date 2021/04/07 Deciphered Date 2021/04/07 Thermal sensor/FAN CONN

C
HY568 0.1

5
Vinafix.com
4 3 2 1
5 4 3 2 1
D Right Side USB2.0 Port X 1 (USB/B)

+USB_VCCC
D
for HY568 15" / HY568P USB board HIGHSTAR_FC5AF241-2931H
24
23 24
RI409 1 @ 2 0_0402_5% 22 23 26
21 22 GND2 25
20 21 GND1
LI102 USB20_4_CONN_P 19 20
USB20_4_N 2 1 USB20_4_CONN_N USB20_4_CONN_N 18 19
17 USB20_4_N 2 1 18
17
USB30_RX2_N 16 17
USB20_4_P USB20_4_CONN_P 17,78 USB30_RX2_N USB30_RX2_P 16
3 4 15
17 USB20_4_P 3 4 17,78 USB30_RX2_P 15
14
EXC24CH900U_4P USB30_TX2_N 13 14
17,78 USB30_TX2_N USB30_TX2_P 13
EMC@ 12
17,78 USB30_TX2_P 12
11
RI414 1 @ 2 0_0402_5% SYS_LED_MUX_CONN 10 11
78,80 SYS_LED_MUX_CONN 10
+3VALW_SYS
9
LID_SW_N 8 9
47,78,79,83 LID_SW_N 8
7
6 7
+3VL 6
47,78,79 IO_Camera_EN
5
4 5
NT_REMOTE1_P 3 4
76,78 NT_REMOTE1_P NT_REMOTE1_N 3
2
m
USB3.1 PORT x1 76,78 NT_REMOTE1_N
1 2
1
JIO2 ME@
+5VALW Low Active 1.8A +USB_VCCC
UI138
5 1
IN OUT +USB_VCCC ME@
co
2 ELCO_046809640410846+
GND
2
C C
+USB_VCCC_EN
CI171 4 3 USB_OC1_N for HY568 17" / Y760 USB board

1U_0402_16V6K ENB OCB USB_OC1_N 18 40 42
G517E2T11U_SOT23-5 39 40 GND2 41
1 39 GND1
1 38
@ CI172 37 38
1000P_0402_50V_X7R_0402 36 37
2 USB20_4_CONN_P 35 36
USB_ON_N RI910 1 @ 2 0_0402_5% USB20_4_CONN_N 34 35
57,79 USB_ON_N 34
33
USB30_RX2_N 33
.
32
17,78 USB30_RX2_N USB30_RX2_P 32
31
17,78 USB30_RX2_P 31
30
USB30_TX2_N 29 30
ap
17,78 USB30_TX2_N USB30_TX2_P 29
28
17,78 USB30_TX2_P 28
27
SYS_LED_MUX_CONN 26 27
78,80 SYS_LED_MUX_CONN 26
25
+3VALW_SYS LID_SW_N 24 25
47,78,79,83 LID_SW_N 23 24
22 23
+3VL 22
21
47,78,79 IO_Camera_EN 21
20
NT_REMOTE1_P 19 20
76,78 NT_REMOTE1_P NT_REMOTE1_N 19
18
76,78 NT_REMOTE1_N 18
17
rL
CLK_PCIE_CARD_N 16 17
19 CLK_PCIE_CARD_N CLK_PCIE_CARD_P 16
for CardRead 15
19 CLK_PCIE_CARD_P 15
14
PCIE_PRX_DTX16_N 13 14
16
PCIE_PRX_DTX16_N PCIE_PRX_DTX16_P 13
for CardRead 12
16
PCIE_PRX_DTX16_P 12
17@ 11
PCIE_PTX_DRX16_N CM1 1 20.1U_6.3V_K_X5R_0201 PCIE_PTX_C_DRX16_N 10 11
16 PCIE_PTX_DRX16_N PCIE_PTX_DRX16_P PCIE_PTX_C_DRX16_P 10
CM2 1 20.1U_6.3V_K_X5R_0201 9
16 PCIE_PTX_DRX16_P 9
17@ 8
PLT_RST_N RM1 1 @ 2 0_0402_5% PLT_RST_N_R 7 8
B
ai 20,31,52,55,63,71,73,79
18
PLT_RST_N
CARD_CLKREQ_N
for CardRead
CARD_CLKREQ_N RM2 1 @ 2 0_0402_5%
79 EC_ON_PCH
CARD_CLKREQ_N_R1
EC_ON_PCH
6
5
4
3
2
7
6
5
4
3 B
for CardRead 1 2
+3VS 1
JIO1
ep
R
A A
Issued Date
<Title> Deciphered Date
C <Doc> EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET
DEPARTMENT <RevCode>
NOR THE INFORMATION IT CONTAINS
Vinafix.com
Wednesday, April 07, 2021 78 110 Date: Sheet of
5 4 3 2 1
5 4 3 2 1
RE1 1 @ 2 0_0603_5% +3VL 0.5A

+3VALW_R +VFSPI
+3VS
RE3 1 @ 2 1/10W_0_5%_0603 +3VALW_SYS +3VALW_R RPE1
ESPI_CS0_N +3VALW_R +3VALW_EC EC_FAN2_SPEED
For EMI EMC_NS@ 220P_0402_50V7K 2 1 CE24 +3VALW_SYS RE75 1 @ 2 0_0402_5% 1 4
EC_FAN1_SPEED 2 3
RE2 2 1 33_0402_5% ESPI_CLK EMC_NS@ 220P_0402_50V7K 2 1 CE25 ESPI_IO3 +3VALW_R All capacitors close to EC RE4 1 @ 2 0_0603_5%
1 EMC_NS@ RE97 1 @ 2 0_0402_5% 10K_0404_4P2R_5%
EMC_NS@ 220P_0402_50V7K 2 1 CE26 ESPI_IO2 VCC_LPC_ESPI EC_FAN2_PWM RE65 1 @ 2 10K_0402_5%
.1U_0402_10V6-K
.1U_0402_10V6-K
.1U_0402_10V6-K
.1U_0402_10V6-K
.1U_0402_10V6-K
.1U_0402_10V6-K
CE2 For SPI ROM Mirror +VFSPI
22P_50V_J_NPO_0402 EMC_NS@ 220P_0402_50V7K 2 1 CE27 ESPI_IO1 Close EC 1
CE6
1
CE7
1
CE8
1
CE9
1
CE10
1
CE11
1
CE4
1
CE5 EC_FAN1_PWM RE11 1 @ 2 10K_0402_5%
2 EMC_NS@ +3VALW_EC .1U_0402_10V6-K 1000P_0402_50V_X7R_0402
EMC_NS@ 220P_0402_50V7K 2 1 CE28 ESPI_IO0 +1.8VALW VCC_LPC_ESPI CE3 CD@ @ @ ENBKL RE9 1 @ 2 100K_0402_5%
1 2 VCOREVCC 2 2 2 2 2 2 2 2
D 1 2 0_0603_5% EC_AGND D
RE6 @
ESPI_RST_N RE901 1 @ 2 0_0402_5% .1U_0402_10V6-K +3VL
Reserved Cap HLZ SDV 0616 Project ID Y7 PU, Y5 PD
1
CE1 EC_AGND EC_ON_5VALW_R RE903 2 1 100K_0402_5%
minimum trace width 12 mil
114
121
127
106
1000P_0402_50V_X7R_0402 Board_Project_ID RE885 1 @ 2 100K_0201_5%
12
11
26
50
92
74
2 EMC_NS@ UE1 EC_3V/5V_USM RE889 1 2 100K_0201_5%
EC_ON_3VALW_R RE95 2 1 100K_0402_5%
VCORE
VCC
VSTBY1
VSTBY2
VSTBY3
VSTBY4
VSTBY5
VSTBY6
VFSPI
AVCC
EC 使使使使SA00009CZ10
BKOFF_N RE36 2 @ 1 10K_0402_5%
LID_SW_N RE38 1 2 100K_0402_5%
+3VALW_R ACIN RE42 1 2 100K_0402_5%
+3VALW_R EC_ON_PCH_R RE902 1 2 100K_0402_5%
EC_1.8VALW_EN RE98 1 @ 2 100K_0402_5%
RPE2 EC_ON_PCH RE876 1 @ 2 EC_ON_PCH_R
0_0402_5% 4 24 PWR_LED_PWM_B
28 WRST_N_EC 53,78,84 EC_ON_PCH KBRST#/GPB6 PWM0/GPA0 25 PWR_LED_PWM_B 80
1 4EC_SMB_CK1 ESPI_ALERT0_N RE898 1 @ 2 EC_ESPI_ALERT0_N
0_0402_5% 5 EC_YLOGO_LED_PWM
20 ESPI_ALERT0_N ALERT#/SERIRQ/GPM6 PWM1/GPA1 28 EC_YLOGO_LED_PWM 47
3EC_SMB_DA1 ESPI_CS0_N EC_ESPI_CS0_N PWR_LED_PWM_R EC_RSMRST_R_N
15P_0402_50V8J
15P_0402_50V8J
2 1 1 RE899 1 @ 2 0_0402_5% 6 RE877 2 1 100K_0402_5%

20 ESPI_CS0_N ESPI_IO3 EC_ESPI_IO3 ECS#/LFRAME#/GPM5 PWM2/GPA2 29 PWR_LED_PWM_G PWR_LED_PWM_R 80 BKOFF_N
DE1 @ RE943 1 @ 2 0_0402_5% 7 RE40 2 1 100K_0402_5%
20 ESPI_IO3 ESPI_IO2 EC_ESPI_IO2 EIO3/LAD3/GPM3 PWM3/GPA3 30 EC_FAN2_PWM PWR_LED_PWM_G 80
CE113
CE112
2.2K_0404_4P2R_5% @ @ 1 2 RE944 1 @ 2 0_0402_5% 8 ENBKL RE10 1 2 100K_0402_5%

20 ESPI_IO2 ESPI_IO1 EC_ESPI_IO1 EIO2/LAD2/GPM2 SMCLK5/PWM4/GPA4 31 EC_FAN1_PWM EC_FAN2_PWM 77
RE945 1 @ 2 0_0402_5% 9
2 2 20 ESPI_IO1 ESPI_IO0 EC_ESPI_IO0 EIO1/LAD1/GPM1 SMDAT5/PWM5/GPA5 32 EC_FAN1_PWM 77 Board_Project_ID
RE946 1 @ 2 0_0402_5% 10 GPA6 PAD 1 @ RE886 1 2 100K_0201_5%
RB751V-40_SOD323-2 20 ESPI_IO0 ESPI_CLK EC_ESPI_CLK EIO0/LAD0/GPM0 PWM6/SSCK/GPA6 34 ITE14
RE900 1 @ 2 0_0402_5% 13
+3VS 20 ESPI_CLK WRST_N_EC ESCK/LPCCLK/GPM4 PWM7/RIG1#/GPA7 120 CHG_MOD3 EC_EDP_PWM 46 for DDS 08/06
RE8 1 2 100K_0402_5% 14
2 0_0402_5% EC_PLT_RST_N WRST# GPC4 124 SUSP_N CHG_MOD3 59
RE947 1 @ 15
20,31,52,55,63,71,73,78 PLT_RST_N EC_RX PLTRST#/ECSMI#/GPD4 GPC6 SUSP_N 71,80,84,93
RPE3 1 16 RE106 1 @ 2 0_0402_5% AGKB_INT 82
1 4EC_SMB_CK2 71 EC_RX EC_TX 17 RXD/SIN0/PWUREQ#/BBO/SMCLK2ALT/GPC7 66 NTC_V1_GPU new add for RGB_KB +3VALW_R
71 EC_TX TXD/SOUT0/LPCPD#/GPE6 ADC0/GPI0 NTC_V1_GPU 76
3EC_SMB_DA2 CE12 ESPI_RST_N NTC_V2_CPU
15P_0402_50V8J
15P_0402_50V8J
2 1 1 22 67 NTC_V2_CPU 76 yong 07/16

1U_0402_6.3V6K 20 ESPI_RST_N EC_SCI_N 23 ERST#/LPCRST#/GPD2 ADC1/GPI1 68 BATT_TEMP RE868 1 @ 2 0_0402_5% MIRROR@
2 18,20 EC_SCI_N ECSCI#/GPD3 ADC2/GPI2 DCIN_ATTACHED_EC BATT_TEMP 87,89 RGB_KB_INT 80
CE30
CE117
2.2K_0404_4P2R_5% @ @ RE12 1 @ 2 0_0402_5% ENBKL 126 69

DCIN_ATTACHED_EC 88 GPG2 RE44 2 1 10K_0402_5%
45,46 MUX_EDP_ENBKL GA20/GPB5 ADC3/GPI3 70 GPG2 RE46 2 1 10K_0402_5%
2 2
ITE-IT8227E-192/CX_ ADC4/GPI4
ADC5/DCD1#/GPI5
71
72
ADP_I
EC_SYS_PWROK ADP_I 89
NTC_V3_DIMM_R RE870 2
RE869 1
@
@
1 0_0402_5%
2 0_0402_5%
NTC_V3_DIMM 76 NOMIRROR@
EC_SYS_PWROK 17 ADAPTER_ID 88 when mirror, GPG2 pull high
20 PM_SLP_S0_N
58
KSI0/STB#
LQFP128 ADC6/DSR1#/GPI6
ADC7/CTS1#/GPI7
73 PSYS
BKOFF_N
PSYS 89,95 follow PWR request change to 0ohm
1/14 when no mirror, GPG2 pull low
59 78
84 EC_VCCST_EN KSI1/AFD# DAC2/TACH0B/GPJ2 79 BKOFF_N 47
+3VALW_SYS RE76 1 @ 2 0_0402_5% CAPS_LED_EC 60 ME_FLASH +3VALW_SYS
20,81 CAPS_LED KSI2/INIT# DAC3/TACH1B/GPJ3 80 ME_FLASH 18 OD output
RE77 1 @ 2 0_0402_5% NUM_LED_EC 61 EC_PROCHOT
20,81 NUM_LED EC_ON_USB2 KSI3/SLIN# DAC4/DCD0#/GPJ4 81
RPE4 RE879 1 @ 2 0_0402_5% EC_ON_USB2_R 62 EC_VR_ON
2 3 EC_SMB_CK0 53 EC_ON_USB2 1 PAD EC_KSI5 63 KSI4 DAC5/RIG0#/GPJ5 EC_VR_ON 95 VCCIN_AUX_EN
C @ RE895 1 2 100K_0402_5% C
EC_SMB_DA0 ITE13 EC_KSI6 KSI5 AGKB_PWR_EN_R_N
1 4 81 EC_KSI6 64 85 RE102 1 @ 2 0_0402_5%
EC_KSI7 KSI6 PS2CLK0/TMB0/CEC/GPF086 PBTN_OUT_N AGKB_PWR_EN_N 80,82
81 EC_KSI7 65 +5VALW
USB_CHG_EN KSI7 PS2DAT0/TMB1/GPF1 87 EC_SMB_CK0 PBTN_OUT_N 21,24
2.2K_0404_4P2R_5% 59 USB_CHG_EN 36
EC_+10V_EN KSO0/PD0 SMCLK0/GPF2 88 EC_SMB_DA0 EC_SMB_CK0 76,80,82
@ 1 PAD 37
ITE11 38 KSO1/PD1 SMDAT0/GPF3 89 EC_SMB_DA0 76,80,82 USB_ON_N
16,21 PCH_DPWROK RE15 1 2 100K_0402_5%
KSO2/PD2 PS2CLK2/GPF4 90 EC_I2C_INT4_PDB_N 54
18,84 CPU_C10_GATE_N RE952 1 @ 2 0_0402_5% EC_CPU_C10_GATE_N 39 EC_3V/5V_USM SYSON_VDDQ RE64 1 @ 2 100K_0402_5%
+3VL KSO3/PD3 PS2DAT2/GPF5 EC_3V/5V_USM 91
95 VR_PWRGD 40
RE897 1 @ 2 0_0402_5% EC_SLP_SUS_N 41 KSO4/PD4 96 +3VALW_R
17,97 SLP_SUS_N KSO5/PD5 GPH3/ID3 97 STATUS_N 59
RE951 1 @ 2 0_0402_5% +1.8VALW_PG_R 42 BATT_CHG_LED_N
97 +1.8VALW_PG KSO6/PD6 GPH4/ID4 98 BATT_CHG_LED_N 80
1
43 BATT_LOW_LED_N
RE108
20
84
TOP_SWAP_EN
EC_+1.8VS_EN 44 KSO7/PD7
KSO8/ACK#
SA00009CZ20 GPH5/ID5 99
GPH6/ID6
PCH_PWROK BATT_LOW_LED_N
PCH_PWROK 16
80 EC_LAN_WAKE_N RE5 2 @ 1 10K_0402_5%
@ 100K_0201_5% RE119 1 @ 2 0_0402_5% PWM_OUT_EN_R 45
20,46
46
PWM_OUT_EN
EC_EDP_ENVDD RE118 1 @ 2 0_0402_5% EC_EDP_ENVDD_R
1 0_0402_5% SYS_LED_EC
46 KSO9/BUSY
KSO10/PE
support ECC function 101
FSCE# 102
EC_SPI_CS0_N
EC_SPI_SI EC_SPI_CS0_N 27
SUSP_N RE18 1 @ 2 100K_0402_5%
80 SYS_LED RE883 2 @ 51
EC_SPI_SI 27
2
BoardID_ADP_LIM VCCIN_AUX_EN 52 KSO11/ERR# FMOSI 103 EC_SPI_SO

96,99 VCCIN_AUX_EN KSO12/SLCT FMISO 105 EC_SPI_CLK EC_SPI_SO 27 EC_VCCST_EN
80 PWR_LED_SEL 53 RE896 1 @ 2 100K_0402_5%
KSO13 FSCK EC_SPI_CLK 27
1
54 EC_ON_3VALW_R RE114 1 @ 2 100K_0402_5%

RE109 BoardID_ADP_LIM 55 KSO14 SUSP_N RE19 1 2 100K_0402_5%
100K_0201_5% Board_Project_ID 56 KSO15 108 ACIN SYSON RE21 1 2 100K_0402_5%
2 0_0402_5% SMB1_ALERT#_R KSO16/SMOSI/GPC3 GPB0 LID_SW_N ACIN 89 EC_VR_ON
76 SMB1_ALERT_N RE101 1 @ 57 109 RE14 1 2 100K_0402_5%
KSO17/SMISO/GPC5 GPB1 LID_SW_N 47,78,83
BoardID_ADP_LIM:
2
1: GN20E < 170W adapter not support

0: GN20P < 135W adapter not support ON/OFF 110 82 VGA_AC_DET_EC RE30 1 @ 2 0_0402_5%
80 ON/OFF PWRSW/GPB3 EGAD/GPE1 83 VGA_AC_DET 31
EC request 11/12 RE92 2 @ 1 0_0402_5% EC_ON_3VALW 111 SYSON_VDDQ
76,91 EC_ON_3VALW_R EC_SMB_CK1 115 GPB4 EGCS#/GPE2 84 EC_TP_ON SYSON_VDDQ 93
+3VALW_R
87,89 EC_SMB_CK1 EC_SMB_DA1 SMCLK1/GPC1 EGCLK/GPE3 EC_TP_ON 83
116
87,89 EC_SMB_DA1 SMDAT1/GPC2
RE24 1 2 33_0402_5% EC_PECI 117 77 EC_MUTE_N
EC_SMB_CK1 10,16 CPU_PECI SMCLK2/PECI/GPF6 TACH2B/GPJ1 100 EC_MUTE_N 66
PAD 1 @ 118 GPG2 for PD
EC_SMB_DA1 ITE1 47,78 IO_Camera_EN EC_SMB_CK2 SMDAT2/PECIRQT#/GPF7 SSCE0#/GPG2 125 CHG_MOD1 EC_SMB_CK4_PD
PAD 1 @ 94 RPE5 1 4 2.2K_0404_4P2R_5%
ITE2 31,45,76,102 EC_SMB_CK2 EC_SMB_DA2 CRX1/SIN1/SMCLK3/GPH1/ID1 SSCE1#/GPG0 119 CHG_MOD1 59 EC_SMB_DA4_PD
PAD 1 @ 95 SYSON 2 3
ITE3 31,45,76,102 EC_SMB_DA2 CTX1/SOUT1/SMDAT3/GPH2/ID2 DSR0#/GPG6 122 EC_LAN_WAKE_N SYSON 93
PAD 1 @ EC_LAN_WAKE_N 73
ITE4 DTR1#/SBUSY/GPG1/ID7113 EC_I2C_INT4_PDB_N
PAD 1 @ GPC0 RE941 2 @ 1 0_0402_5% EC_WLAN_WAKE_N 71 RE878 1 2 10K_0201_5%
ITE5 CRX0/GPC0 123 EC_WAKE_R_N EC_I2C_INT4_PDA_N
RE29 1 @ 2 0_0402_5% RE88 1 2 10K_0201_5%
EC_ON_5VALW_R CTX0/TMA0/GPB2 18 PM_SLP_S3_N PCIE_WAKE_N 17,73
112
91 EC_ON_5VALW_R 1 2 0_0402_5% 107 RING#/CK32KOUT/LPCRET#/GPB7 RI1#/GPD0 21 PM_SLP_S4_N PM_SLP_S3_N 21,84
RE948 @
EC_KSI7 45,47 EDP_HPD GPE4 RI2#/GPD1 76 PM_SLP_S4_N 21,51,54,84
PAD 1 @
EC_KSI6 ITE6 TACH2A/GPJ0 48 EC_FAN2_SPEED EC_VCCST_PWRGD 10 OD output ADAPTER_ID
PAD 1 @ Hunk 10/9 : Reserved I2C control EDP MUX CE31 1 2 .1U_0402_10V6-K EMC_NS@
B WRST_N_EC ITE7 TACH1A/TMA1/GPD7 47 EC_FAN1_SPEED EC_FAN2_SPEED 77 B
PAD 1 @
ITE8 TACH0A/GPD6 19 EC_FAN1_SPEED 77
33 SYSON CE13 1 2 .1U_0402_10V6-K EMC_NS@
57,78 USB_ON_N EC_SMI_N 35 GINT/CTS0#/GPD5 SMCLK4/L80HLAT/BAO/GPE020 EC_SMB_CK4_PD 51,54
PD
18 EC_SMI_N EC_RSMRST_R_N RTS1#/GPE5 SMDAT4/L80LLAT/GPE73 EC_SMB_DA4_PD 51,54 EC_PECI
RE848 1 2 1K_0201_5% 93 CE15 1 2 47P_0402_50V8J EMC_NS@
16,21,24 EC_RSMRST_N CLKRUN#/GPH0/ID0 GPH7 EC_I2C_INT4_PDA_N 51
For factory EC flash BATT_TEMP CE16 1 2 100P_0402_50V8J EMC_NS@
EC_1.8VALW_EN 2
EC_SPI_CS0_N CE20 1 97 EC_1.8VALW_EN GPJ7 EC_RTCRST_N_ON
2 .01U_0402_16V7-K @ GPC0 RE942 2 @ 1 0_0402_5% ACIN CE17 1 2 100P_0402_50V8J EMC_NS@
AC_PRESENT 128
EC_SPI_SI 21 AC_PRESENT GPJ6
CE21 1 2 .01U_0402_16V7-K @ ON/OFF CE18 1 2 1U_0402_6.3V6K EMC_NS@
EC_SPI_SO CE22 1 2 .01U_0402_16V7-K @ PM_SLP_S3_N CE29 1 2 .01U_0402_16V7-K EMC_NS@
EC_SPI_CLK PM_SLP_S4_N
AVSS
VSS1
49 VSS2
VSS3
VSS5
CE23 1 2 .01U_0402_16V7-K @ CE135 1 2 .01U_0402_16V7-K EMC_NS@
PCH_RTCRST_N 16
91VSS4
RE34 1 @ 2 0_0402_5% +3VS EC_RSMRST_R_N CE136 1 2 .01U_0402_16V7-K EMC_NS@
89 VR_HOT_N H_PROCHOT_N 10,20,95
1
IT8227E-192CX_LQFP128_14X14 QE3 D
27
104
75
EC_RTCRST_N_ON 2 EC_PLT_RST_N CE137 1 2 .01U_0402_16V7-K EMC_NS@
1
1
CE14 G 1
RE90 @ 47P_0402_50V8J
1/20W_100_5%_0201 S 2N7002KW_SOT323-3 CE19
3
1
2 .1U_0402_10V6-K
RE50 2
1 2
EC_AGND 10K_0402_5%
QE1 D
EC_PROCHOT 2
2
G
2N7002KW_SOT323-3 S
3
A A
Vinafix.com
Issued Date 2021/04/07 Deciphered Date 2021/04/07 ITE8371LQFP
Custom
HY568 0.1

5 4 3 2 1
5 4 3 2 1
for HY568 KB
lighting 04/27
+3VALW_RGB
RI923 1 @ 2 2.2K_0402_5%RGB_I2C_SCL
RI922 1 @ 2 2.2K_0402_5%RGB_I2C_SDA
+5VS +5VS_KLED
RI96 1 2 4.7K_0402_5%RGB_KB_INT
RI286 1 @ 2 2.2K_0402_5%RGB_SMCLK RI888 1 @ 2 0_0603_5% CI70 1 2 22U_10V_M_X5R_0603
RI287 1 @ 2 2.2K_0402_5%RGB_SMDAT CI60 1@ 2
150P_25V_J_COG_0201
150P_25V_J_COG_0201
1U_0603_25V6M
2 2 CI61 1@ 2 +5VS_KLED
470P_0402_50V7K
@
D JRGB1 D
1 1
CI76
CI77
20
19 20
@ 18 19
17 18
16 17 21
15 16 GND1 22
14 15 GND2
13 14
RGB_SMCLK 12 13
RGB_SMDAT 11 12
RGB_KB_INT 10 11
79 RGB_KB_INT 9 10
66 RGB_I2C_SCL 8 9
66 RGB_I2C_SDA 7 8
USB20_RGB_N_CONN 6 7
USB20_RGB_P_CONN 5 6
4 5
3 4
2 3
RI79 1 @ 2 0_0402_5% 1 2
+3VALW_RGB 1
LI96 ME@
USB20_7_N 1 2 USB20_RGB_N_CONN
m
17 USB20_7_N 1 2
USB20_7_P 4 3 USB20_RGB_P_CONN
17 USB20_7_P 4 3
EXC24CH900U_4P
EMC@
RI80 1 @ 2 0_0402_5%
+3VALW_SYS +3VALW_RGB
+3VALW_RGB
co
RI284 1 @ 2 0_0603_5%
10U_25V_M_X5R_0603
2
G
2
CI74
RI285
EC_SMB_CK0 6 1 RGB_SMCLK UI130 @ 100K_0402_5%
S
C 76,79,82 EC_SMB_CK0 5 1 2 C
@ @
D
5
IN OUT
G
1
QI21A 2
2N7002KDWH_SOT363-6 GND
4 3 RGBKB_PWR_OCB
EC_SMB_DA0 RGB_SMDAT 79,82 AGKB_PWR_EN_N ENB OCB
3 4
76,79,82 EC_SMB_DA0
S
0.1U_0402_10V7K
D
CI75
@ SY6288D20AAC_SOT23-5
QI21B 2N7002KDWH
.
@
2N7002KDWH_SOT363-6 Vth= min 1V, max 2.5V
ESD 2KV @ 2
RI326 1 @ 2 0_0402_5%
ap
need confirm if another GPIO
RI327 1 @ 2 0_0402_5%
yong 07/22
system LED
LED310 15@ LED303 HY568P@ +3VALW_SYS
+5VALW
S z
Power button LED Status OE S PWM_B 3 - PWR_LED_PWM_B_OUT RI406 1 @ 21/16W 1.8K +-1% 0402 PWM_B 3 -
Blue L H
B B H Y1 1
1 CI56
2
PWM_G 2 4 PWR_LED_PWM_G_OUT RI407 1 22.2K_0402_5% PWM_G 2 4

RI935 White L L
-
G
+
+5VALW @ -
G
+
+5VALW L Y0 SYS_LED@1U_0402_10V6K
CI164
1U_0402_10V6K @ 0_0603_5% UI4 SYS_LED@ 2
PWR_LED@ 2 OFF H x PWM_R 1 - PWR_LED_PWM_R_OUT RI408 1 @ 2 1K_0402_1% PWM_R 1 - 1 5
79 SYS_LED PWR_LED_PWM_B 3 Y1 Vcc
R R
1
PWR_LED@ UI137 RI406,RI407,RI408 HY568,HY568P需分分分使使使使使使 arthur 20210126 Y0 4 SYS_LED_MUX
rL
PWR LED_VCC
16 LED LTST-C19HEGBW-KN RED/GREEN/BLUE LED LTST-C19HEGBW-KN RED/GREEN/BLUE Z
Vcc 4 PWR_LED_PWM_B_MUX 2 6
1A PWR_LED_PWM_G_MUX GND S SUSP_N 71,79,84,93
2 7
79 PWR_LED_PWM_B 1B1 2A PWR_LED_PWM_R_MUX
3 9 LED310 and LED303 P/N change to SC50000NQ00
5 1B2 3A 12 74LVC1G3157GW_SOT363-6
79 PWR_LED_PWM_G 2B1 4A
6
11 2B2 15
79 PWR_LED_PWM_R 3B1 OE
10 1
3B2 S PWR_LED_SEL 79
14
2
13 4B1 8 只
4B2 GND 17 RI411 +3VALW_SYS
T-PAD 100K_0402_5%
CBT3257ABQ_DHVQFN16_2P5X3P5
PWR_LED@
1
1
RI321
ai
@ 470_0603_5%
B B
PWR_LED_PWM_B RI936 1 @ 2 0_0201_5% PWR_LED_PWM_B_MUX
2
PWR_LED_PWM_G RI937 1 @ 2 0_0201_5% PWR_LED_PWM_G_MUX SYS_LED_MUX_CONN
PWR_LED_PWM_R RI938 1 @ 2 0_0201_5% PWR_LED_PWM_R_MUX SYS_LED_MUX_CONN 78
1
QI22 D
SYS_LED_MUX 2
G
PWR_LED_PWM_R_OUT +5VALW +5VALW +5VALW
2
SYS_LED@S 2N7002KW_SOT323-3
3
PWR_LED_PWM_G_OUT RI322
SYS_LED@ 100K_0402_5%
1
PWR_LED_PWM_B_OUT
ep
RI418 RI419 RI404
1
470_0603_5% @ 470_0603_5% @ 470_0603_5%
@
PWR_LED_PWM_B_OUT PWR_LED_PWM_G_OUT PWR_LED_PWM_R_OUT

1000P_0402_50V_X7R_0402
1000P_0402_50V_X7R_0402
1000P_0402_50V_X7R_0402
2N7002KW_SOT323-3
2N7002KW_SOT323-3
2N7002KW_SOT323-3
1
QI27 D QI28 D 1 QI26 D 1

PWR_LED_PWM_B_MUX PWR_LED_PWM_G_MUX PWR_LED_PWM_R_MUX
EMC_NS@
EMC_NS@
EMC_NS@
EMC_NS@
EMC_NS@
CI170
CI166
2 1 2 2
ON/OFF switch
1
EMC_NS@
DI118
DI119
DI120
CI169
G G G
100K_0402_5%
100K_0402_5%
ON/OFFBTN_N ON/OFFBTN_N
17" Power DB
100K_0402_5%
2 2
RI410
PWR_LED@ S PWR_LED@ S PWR_LED@ S
3
2
RI420
RI421
Conn
1
2
PWR_LED@
PWR_LED@ PWR_LED@ SW8 SW6
1
del LID
2
DI113
1
2
@
2 yong 0619
+5VALW
2
R
Charger LED
2
BATT_LOW_LED 上上
17" Power DB
3
4
+3VALW_SYS BATT_CHG_LED HY568P@ 15@ RI76
LED302
@ 0_0402_5%
Conn
RI394 NTC5033-XKG-C16001_4P NTC5033-XKG-C16001_4P

BATT_LOW_LED 4 3 3VALW_LOW_LED 1 2
del LID
1
1
1/16W_82_1%_0402 DI114 DI115
1
BATT_CHG_LED 1 2 3VALW_CHG_LED 1
RI397
2 1
EMC_NS@ yong 0619 JPWR1
CI157 PWR_LED_PWM_G_OUT RI296 1 @ 2 0_0402_5% PWM_G_OUT 1
1 1 PWR_LED_PWM_B_OUT 1
1/16W_82_1%_0402 .1U_0402_10V6-K RI75 1 @ 2 0_0402_5% PWM_B_OUT 2
PWR_LED_PWM_R_OUT 2 0_0402_5% PWM_R_OUT 3 2
2
CI158 CI159 B2972UDBS05P-000114_AMBER-WHITE @ RI297 1 @

220P_0402_50V7K 2 EMC_NS@ 4 3
220P_0402_50V7K
2
EMC_NS@ 2 2 EMC_NS@ 5 4
ON/OFFBTN_N RI74 1 @ 2 0_0402_5% ON/OFFBTN 6 5
+3VALW_SYS +3VALW_SYS +3VALW_SYS 6
A 7 A
10K_0402_1%
10K_0402_1%
8 GND1
remove NOVO button
10K_0402_1%
+3VALW_SYS GND2
1
RI940
RI942
+3VL HIGHS_FC5AF061-2931H
10K_0402_1%
RI939
@ +3VL @ ME@
1
RI943
1
BATT_CHG_LED BATT_LOW_LED
2
RI941 RI944
6
100K_0402_5% D 100K_0402_5% D
2
2 QV505A 2 QV506A
G G 2N7002KDWH_SOT363-6
2
D D
5 S 5 S JI4 1 2 @ +3VL
79 BATT_CHG_LED_N
1
79 BATT_LOW_LED_N
1
G 2N7002KDWH_SOT363-6 G
QV505B QV506B SHORT PADS
2
S S Title
Security Classification LCFC Highly Confidential Information
4
2N7002KDWH_SOT363-6 2N7002KDWH_SOT363-6 JI5 1 2 @ RI398
Vinafix.com
100K_0402_5% DC V TO VS INTERFACE
SHORT PADS
1
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
ON/OFFBTN_N
RI945 1 @ 2 0_0402_5% RI946 1 @ 2 0_0402_5% RI399 1 @ 2 0_0402_5% ON/OFF
ON/OFF 79 DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
D
HY568 0.1

5 4 3 2 1
5 4 3 2 1
+3VS
DI109 AZ5725-01F.R7GR_DFN1006P2X2
FNlock_R_LED_N
1 2 EMC@ CAPS_LED_CONN CAPS_LED_CONN
JKB2 New Add for EC debug 1 2 NUM_LED_CONN
34 DI110 AZ5725-01F.R7GR_DFN1006P2X2
34 EC_KSI7 79
33
33 FNlock_R_LED_N FNlock_LED_N EC_KSI6 79 NUM_LED_CONN
36 32 RI391 1 @ 2 0_0402_5% 1 2 EMC@
GND1 32 1 2
1000P_0402_50V_X7R_0402
35 31 LED_KB_C
GND2 31
1000P_0402_50V_X7R_0402
1000P_0402_50V_X7R_0402
30
EMC_NS@
EMC_NS@
EMC_NS@
30 1 1 1
29 NUM_R_LED_N RI393 1 @ 2 0_0402_5% NUM_LED_CONN
CI161
CI162
29 28 KSO17 DI112 AZ5725-01F.R7GR_DFN1006P2X2 1
CI160
28 27 KSO16 D
D 27 26 KSI1 1 2 EMC@ FNlock_R_LED_N 2 2 2 2 QI24 D
26 1 2 82 LED_KB_PWM
25 KSI7 G PJA138K_SOT23-3
25 24 KSI6 S
24
2
23 KSO9
23 22 KSI4 3
22 21 KSI5 RI395
21 20 KSO0 100K_0402_5%
20 19 KSI2 KSI[0..7]
KSI[0..7] 82
1
19 18 KSI3
18 17 KSO5 KSO[0..17]
17 KSO[0..17] 82
16 KSO1
16 15 KSI0 KSO16 1 @ TI13
15 14 KSO2
14 13 KSO4
13 12 KSO7
12
11
11
10
KSO8
KSO6
K/B Connector
10 9 KSO3
9 8 KSO12
8 7 KSO13
7 6 KSO14 +5VS
6 5 KSO11
0.5A JKBL2
5 4 KSO10 1
4 3 KSO15 LED_KB_C 2 1
3 2 CAPS_R_LED_N RI401 1 @ 2 0_0402_5% CAPS_LED_CONN RI400 1 @ 2 0_0603_5% LED_Power_C1 3 2
2 1 4 3
1 4 5
0.1U_10V_K_X5R_0402
GND1 6
CI163
HIGHS_FC8AR341-3160-1H 2 GND2
ME@
@ HIGHSTAR_FC1AF041-3152-1H
1
ME@
C C
+3VS +3VS
+3VS
10K_0402_1%
10K_0402_1%
1
10K_0402_1%
1
RI918
RI402
@
RI920
@
2
2
CAPS_LED_CONN FNlock_LED_N
2
NUM_LED_CONN
1
1
QI35 D QI25 D
1
CAPS_LED 2 PCH_FNLK 2 QI36 D
20,79 CAPS_LED G 20 PCH_FNLK G NUM_LED 2
20,79 NUM_LED G
2
S 2N7002KW_SOT323-3 2 S 2N7002KW_SOT323-3
3
2
RI919 RI403 S 2N7002KW_SOT323-3
3
100K_0402_5% 100K_0402_5% RI921
100K_0402_5%
1
1
B B
A A

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C
HY568 0.1
Vinafix.com
5 4 3 2 1
5 4 3 2 1
IT8258 delete for P
D D
+3VALW_SYS
2
RI447
@ 0_0603_5%
1
+3VALW_AG
RI448
+3VALW_IN 1 2
@
1/10W_0_5%_0603
10U_25V_M_X5R_0603
1
2
CI219
RI450
UI142 @ 100K_0402_5%
5 1 2
IN OUT
1
2
GND
4 3 AGKB_PWR_OCB
79,80 AGKB_PWR_EN_N ENB OCB
2
1 SY6288D20AAC_SOT23-5
100K_0402_5%
0.1U_10V_K_X7R_0402
RI913
CI220
2
1
+3VALW_AG
C C
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_25V_M_X5R_0603
10U_25V_M_X5R_0603
10U_25V_M_X5R_0603
10U_25V_M_X5R_0603
0.1U_10V_K_X7R_0402
0.1U_10V_K_X7R_0402
0.1U_10V_K_X7R_0402
0.1U_10V_K_X7R_0402
1 1 1 1 1 1 1 1 1 1 1 1
CI222
CI224
CI225
CI226
CI221
CI227
CI228
CI229
CI223
CI230
CI231
CI232
2 2 2 2 2 2 2 2 2 2 2 2
IT8176
+3VALW_AG AVCC3.3V_AG
+3VALW_AG AVCC3.3V_AG
0.1U_10V_K_X7R_0402
1 1
0.1U_10V_K_X7R_0402
CI13
CI14
+3VALW_AG LI24 1 2 HCB1608KF-181T20
VCOREB2_8177
2 2
1 1
1
+3VALW_AG
0.1U_10V_K_X7R_0402
CI15
CI17
1000P_0402_50V_X7R_0402
RI14
1.5K_0402_5%
@ 2 2
2
VCOREB_8176 AGKB_INT
RI730 1 2 1/20W_2.2K_5%_0201
USB20_9_P 1 2 0_0603_5%
UI22 RI42 @
17
18
32
IT8176FN-56A-BX_QFN48_6X6
7
1.5K Reserve for USB

+3VALW_AG KSI7 PAD 1 @ ITI9
slave mode use
VCOREB2
VSTBY33_1
VSTBY33_2
AVCC33
VCOREB
DI44 AG_AGND KSI6 PAD 1 @ ITI10

1 2 KSO17 1 @ TI15
B RB751V-40_SOD323-2 B
1 GPA0 PAD 1 @
SMCLK0/PWM0/GPA0 2 GPA1 1 TI23 +3VALW_AG
PAD @
2 1 10K_0402_5% AG_WRST SMDAT0/PWM1/GPA1 3 AG_SMCLK TI24
RI15
SMCLK1/PWM2/GPA2 4 AG_SMDAT
SMDAT1/PWM3/GPA3
1
CI18 PAD 1 @ 1 1
TI8
0.1U_10V_K_X7R_0402
0.1U_10V_K_X7R_0402
1U_0402_6.3V6K
CI19
CI20
2
48 2 2
WRST#
5
PWM5/GPA5 47
USB20_9_N USB20_8176_N
IT8176FN-56A/BX PWM4/GPA4 LED_KB_PWM 81
+3VALW_AG +3VALW_AG
17
17
USB20_9_N
USB20_9_P
USB20_9_P
RI16
RI17
1
1
@
@
2 0_0201_5%
2 0_0201_5% USB20_8176_P USB20_8176_N
USB20_8176_P
19
20 DM
DP
QFN48 RI40 1 2
2.2K_0402_5%
AG_SMCLK
1 2 AG_SMDAT
RI41
2
2.2K_0402_5%
G
45
KSI[0..7] TXD/GPA7 46
81 KSI[0..7] 37 RXD/GPA6
KSI0
KSO[0..17] 38 KSI0/ADC16/STB#/GPD0 AG_SMCLK 1 6 EC_SMB_CK0
KSI1
S
81 KSO[0..17] KSI1/ADC17/AFD#/GPD1 EC_SMB_CK0 76,79,80
D
KSI2 39
5
KSI3 40 KSI2/ADC18/INIT#/GPD2
G
KSI4 41 KSI3/ADC19/SLIN#/GPD3 QI20A
42 KSI4/ADC20/GPD4
KSI5 2N7002KDWH_SOT363-6
KSI6 43 KSI5/ADC21/GPD5
KSI7 44 KSI6/ADC22/GPD6 AG_SMDAT 4 3 EC_SMB_DA0
S
KSI7/ADC23/GPD7 EC_SMB_DA0 76,79,80
D
KSI0 KSO0 9 34
10 KSO0/PD0/GPE0 ADC0/GPC0 35 QI20B
KSI1 KSO1 2N7002KDWH
KSI2 KSO2 11 KSO1/PD1/GPE1 ADC1/GPC1 36 2N7002KDWH_SOT363-6 Vth= min 1V, max 2.5V
12 KSO2/PD2/GPE2 ADC2/GPC2 AGKB_INT 79
KSI3 KSO3 ESD 2KV
KSI4 KSO4 13 KSO3/PD3/GPE3
22 KSO7/PD7/GPE7 FW update change part number SA000081L20
KSO8
KSO9 23 KSO8/ACK#/GPF0
1 1 1 1 1 1 1 1
KSO9/BUSY/GPF1
33P_0402_50V8J
33P_0402_50V8J
33P_0402_50V8J
33P_0402_50V8J
33P_0402_50V8J
33P_0402_50V8J
33P_0402_50V8J
33P_0402_50V8J
KSO10 24
CI25
CI26
CI27
CI28
CI29
CI30
CI234
CI233
25 KSO10/PE/GPF2
KSO11
KSO12 26 KSO11/ERR#/GPF3
2 2 2 2 2 2 2 2 27 KSO12/SLCT/GPF4
KSO13
KSO14 28 KSO13/GPF5
KSO15 29 KSO14/GPF6
KSO16 30 KSO15/GPF7
KSO17 31 KSO16/SMCLK2/GPG0
AVSS
KSO17/SMDAT2/GPG1
VSS1
VSS2
PAD
6
21
33
49
AG_AGND
A A
5
Vinafix.com 4 3 2
Security Classification
Issued Date 2019/07/02
LCFC Highly Confidential Information
Deciphered Date 2020/02/24
1
Title
Size
E
Date:
DC V TO VS INTERFACE
Document Number
HY568
Wednesday, April 07, 2021 Sheet 82 of 110
Rev
0.1
5 4 3 2 1
+3VS TP_PWR
RI405 1 @ 2 0_0402_5%
1
CI165
.1U_0402_10V6-K
2
D D
+3VS +3VS
1
PCH_I2C1_SCL
RI51 @ RI417
PCH_I2C1_SDA 10K_0201_5% 10K_0201_5%
TP/B Connector
1
2
1
1
JTP2
DI116 DI117 1
79
EC_TP_ON 1
RI61 1 @ 2 0_0201_5% 2
20 PCH_TP_INT_N LID_SW_N 2
RI78 1 @ 2 0_0402_5% 3
47,78,79 LID_SW_N 3
2
2
+3VL RI77 1 @ 2 0_0402_5% 4
5 4
2
PCH_I2C1_SDA 6 5
EMC_NS@ EMC_NS@ 20,45,93 PCH_I2C1_SDA PCH_I2C1_SCL 6
7
20,45,93 PCH_I2C1_SCL 8 7
For EMC TP_PWR 8
68P_25V_J_NPO_0201
68P_25V_J_NPO_0201
9
10 GND1
GND2
2 2
CI167 CI168 HIGHS_FC5AF081-2931H
1 1 ME@
C C
B B
A A
Issued Date 2021/04/07 Deciphered Date 2021/04/07 KBD/PWR/IO/LED/TP Conn.

Vinafix.com
D
HY568 0.1

5 4 3 2 1
A B C D E
+3VALW
+3/5VALW to +3/5VS +5VLP +5VALW +1.8VALW
+3VALW_SYS
+0.6VS
1
5VS_CT2
+1.8VALW_CPU
CR2 +3VS 1 1
1
UR1
1000P_0402_50V_X7R_0402
1U_0402_10V6K
2 1 14 RR2 RR21 RR1 CR43 @ @ CR44
IN1_1 OUT1_2 1
CR5
Change net to SUSP# for PWR sequence 2 13 1 100K_0402_5% @ 100K_0402_5% @ 47_0603_5% 1U_6.3V_M_X5R_0201 10U 6.3V M X5R 0402
IN1_2 OUT1_1 CR6 2 2
SUSP_N RR3 1 @ 2 0_0402_5% 3 12 3VS_CT1 @ .1U_0402_10V6-K +1.8VALW_CPU
79,80,93 SUSP_N
2
EN1 CT1 2 UR13
4 11 2 SUSP 2 4
VBIAS GND 50 SUSP VIN VOUT
1
D
RR4 1 @ 2 0_0402_5% 5 10 5VS_CT2 +5VS 2 SUSP 5 3
EN2 CT2 @ G QR3 VBIAS NC
1 6 9 3VS_CT1 2N7002KW_SOT323-3 CPU_C10_GATE_N RR42 1 @ 2 0_0201_5% 1.8VALW_CPU_EN 6 1 1
1 1 18,79,84 CPU_C10_GATE_N
1
7 IN2_1 OUT2_2 8 CR7 D S ON GND
3
IN2_2 OUT2_1
2200P_25V_K_X7R_0402
CR3 @ +5VALW @ .1U_0402_10V6-K SUSP_N 2 SUSP_N RR46 1 @ 2 0_0201_5% EM5201BJ-45_SOT23-6
0.01U_50V_K_X7R_0402 15 2 G QR2 @
1
2 Thermal Pad 2
CR4
1 S 2N7002KW_SOT323-3 RR44
G2898KD1U_TDFN14P_2X3
3
@ 200K_0402_5%
CR1 1
1U_0402_16V6K
2
2
+3VALW +3VALW
for Parade 1.2V +5VALW
2
1
+1.8VS_CT2 RX51
1
CR33 100K_0402_5%
1U_0402_10V6K @ +3VALW_SYS 2 CX36 @
2 UR12 JX3 1U_0402_6.3V6K
1
+3VALW_SYS_OUT 2 UR3 MUX_POK
1 14 1 CR41
2 IN1_1 OUT1_2 13 2 1 +3VALW
1 1000P_50V_K_X7R_0201
IN1_2 OUT1_1 CR35 1 10 5 1.2V_MUX
EC_ON_PCH RR39 1 2 0_0402_5% EC_ON_3V3 3 12 3V_SYS__CT1 JUMP_43X39 .1U_0402_10V6-K VCNTL POK
79 EC_ON_PCH
@
EN1 CT1
@ 0.5A @ @
4 11 2 2
JX2
1 MUX_VIN 7 1 MUX_P 2
JX1
1
0.5A
+5VALW VBIAS GND 2 1 VIN1 VOUT1 2 1
1 1
SUSP_N RR40 1 @ 2 0_0402_5% +1.8VS_EN 5 10 +1.8VS_CT2 +1.8VS CX38 8 2
1
EN2 CT2 3V_SYS__CT1 JUMP_43X39 CX37 4.7U_0402_6.3V6M VIN2 VOUT2 RX52 220P_0402_50V_X7R_0402 JUMP_43X39
@
1 1 +1.8VALW 6 9 1 4.7U_0402_6.3V6M 9 3 CX99 @
@ @ 7 IN2_1 OUT2_2 8 CR37 2 2 VIN3 VOUT3
@
CR36
22UC_6.3VC_MC_X5RC_0603
2
1
IN2_2 OUT2_1
0.01U_50V_K_X7R_0402
@ .1U_0402_10V6-K 1/20W_12K_+-1%_0201
CR42
22UC_6.3VC_MC_X5RC_0603
0.01U_50V_K_X7R_0402
2 15 2
CX40
CX41
1 CR40
2
2 2 Thermal Pad 2
CR39
1200P_25V_K_X7R_0201
2
1U_0402_16V6K
1 4 MUX_FB
G2898KD1U_TDFN14P_2X3 FB
2 SUSP_N RX53 1 @ 2 0_0201_5% MUX_EN 6 11
1
EN GND RX54
1
APL5934DQBI-TRG_TDFN10_3X3
CX42 1/20W_24K_1%_0201
2
0.1U_10V_K_X5R_0402
2
RR56 1 @ 2 0_0402_5% +1.8VS_EN
79 EC_+1.8VS_EN
+3VS
VCCSTG
1
RR22 +3VALW_SYS
@ 100K_0201_5%
+3VALW_SYS
+3VALW_SYS
2
SUSP_N RR45 1 @ 2 0_0201_5% 1

VCCST
1
UR4 Discr@
1
RR24 1 @ 2 0_0201_5% PM_SLP_VCCSTG# 1 4 VCCSTG_EN_R CR19 RR16
18,79,84 CPU_C10_GATE_N EC_VCCST_EN 3V3_VCCST_OVERRIDE_R IN B OUT Y 0.1U_6.3V_K_X5R_0201
RR25 1 @ 2 0_0201_5% 2 Discr@ RR29 Discr@ 100K_0201_5%
IN A 2 Discr@ 100K_0201_5%
3V3_VCCST_OVERRIDE RR26 1 @ 2 0_0201_5% 3 5
2
GND Vcc 3V3_VCCST_OVERRIDE +3VALW_SYS
2
MC74VHC1G32DFT2G_SC70-5
3
OR Gate QR6 D 1
VCCST_OVERRIDE_N 1
+3VALW_SYS +VCC1P05_OUT_FET G CR28
3 Discr@ 0.1U_6.3V_K_X5R_0201
Discr@ Discr@ S L2N7002KN3T5G_SOT883-3 2
2
1 1 UR7 Discr@
3 3V3_VCCST_OVERRIDE 1 4 PM_SLP_VCCST_OVRD 3
CR17 CR18 RR28 1 @ 2 0_0201_5% +VCCST_EN 2 IN B OUT Y
1U_6.3V_M_X5R_0201 10U 6.3V M X5R 0402 79 EC_VCCST_EN IN A
QR7
2 2 LSI1012N3T5G_SOT883-3 RR38 1 @ 2 0_0201_5% 3 5
21,79 PM_SLP_S3_N GND Vcc
+VCCSTG_CPU remove to EC control
UR6 150mA VCCST_OVERRIDE 1 2 MC74VHC1G32DFT2G_SC70-5
10,22 VCCST_OVERRIDE
2 4 +VCCSTG_CPU_LS OR Gate
VIN VOUT
1.05V
2
5 3
VBIAS NC RR41
VCCSTG_EN_R RR27 1 @ 2 0_0201_5% VCCSTG_ENABLE 6 1
ON GND 100K_0201_5%
EM5201BJ-45_SOT23-6 +3VALW_SYS +VCC1P05_OUT_FET
1
1
RR14
200K_0402_5% 1 1
CR31 CR32
2
1U_6.3V_M_X5R_0201 10U 6.3V M X5R 0402 +VCCST_CPU

2 2
UR10
2 4 +VCCST_CPU_LS
RR51 1 @ 2 0_0402_5% UR14 3905@ VIN VOUT
+3VALW_SYS
5 3
VBIAS NC
1
3905@ 1 PM_SLP_VCCST_OVRD RR34 1 @ 2 0_0201_5% VCCST_EN 6 1
CR45 VDD ON GND
0.1U_6.3V_K_X5R_0201 RR36 1 @ 2 0_0201_5% EM5201BJ-45_SOT23-6
2 21,79 PM_SLP_S4_N
7
1
GND
RR37
3 200K_0402_5%
XDR_PRESENT 8 VCCST_EN_R RR52 1 @ 2 0_0201_5% VCCST_EN
EC_VCCST_EN RR53 1 @ 2 0_0201_5% VCCST_EN
2
PM_SLP_S3_N RR47 1 @ 2 0_0201_5% G_SLP_S3_N 4
SLP_S3# 9
RR48 1 @ 2 0_0201_5% VCCAUX_VID0 5 NC1
18,96,99 VCCIN_AUX_PCH_VID0 VCCAUX_VID0 11
4 RR49 1 @ 2 0_0201_5% VCCAUX_VID1 6 NC2 4
18,96,99 VCCIN_AUX_PCH_VID1 VCCAUX_VID1
VCCST_OVERRIDE RR50 1 @ 2 0_0201_5% G_VCCST_OVERRIDE 2 10 VCCSTG_ENABLE_R RR54 1 @ 2 0_0201_5% VCCSTG_ENABLE
OVERRIDE VCCSTG_EN
CPU_C10_GATE_N RR55 1 @ 2 0_0201_5% G_C10_GATE_N 12
C10_GATE#
G3905AN1U_AQFN12_1P6X1P6
A
Vinafix.com
B C
Issued Date 2021/04/07 Deciphered Date
D
2021/04/07
Size
Date:
DC V TO VS INTERFACE
Document Number
Custom
HY568
E
Sheet 84 of 110
Rev
0.1
5 4 3 2 1
H1 H2 H3 H4 H5 H6 H10
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
@ @ @ @ @ @ @
1
1
PAD_D2P8 PAD_D2P5 PAD_D2P5 PAD_D2P5 PAD_D2P5 PAD_D2P5 PAD_D2P5
D D
H11 H12 H13 H14 H15 H16 H17 H18
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
@ @ @ @ @ @ @ @
1
1
CHASSIS1_GND PAD_C8P0D3P1 PAD_C8P0D3P1 PAD_C8P0D3P1 PAD_C8P0D3P1 PAD_C8P0D3P1 PAD_C8P0D3P1 PAD_CB6P5D2P5
PAD_CB8P0D2P5
SH9 ME@ SH13 ME@ SH16 ME@
H19 H20 H21 H22 H23 H25
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA 1 1 1
@ @ @ @ @ @ 1 1 1
1
1
SHIELDING_SUL-15A3M_6X1P2_1P SHIELDING_SUL-15A3M_6X1P2_1P SHIELDING_SUL-15A3M_6X1P2_1P
PAD_C2P5D2P5N PAD_C2P5D2P5N PAD_CT6P5D2P5 PAD_CT6P5D2P5 PAD_CT7P0D3P3 PAD_CT7P0B7P5D4P1 SH14 ME@
SH18 ME@
1 SH17 ME@
1 1
H26 1 1
C 1 C
HOLEA H27 H28 H29 H30 H31
@ HOLEA HOLEA HOLEA HOLEA HOLEA SHIELDING_SUL-15A3M_6X1P2_1P
@ @ @ @ @ SHIELDING_SUL-35A2M_9P2X3P3_1P
SHIELDING_SUL-35A2M_9P2X3P3_1P
1
1
SH12 ME@ SH15 ME@
PAD_CT6P0B7P0D3P3
PAD_CT7P0B6P2D3P2 PAD_CB6P0D2P5 PAD_CB7P0D2P5 PAD_CT6P4B7P0D3P4 PAD_D2P8X2P5 1 1
1 1
SHIELDING_SUL-35A2M_9P2X3P3_1P SHIELDING_SUL-35A2M_9P2X3P3_1P
B
SO-DIMM Shielding B
FD1 FD2 FD3 FD4 FD5 FD6

1
SH19
@ @ @ @ @ @
1 2
HHY568_MB_EMC_SMT_GASKET
ME@
EMC GASKET
A A
Issued Date 2021/04/07 Deciphered Date 2021/04/07 Hole

Vinafix.com AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B
HY568 0.1

5 4 3 2 1
5 4 3 2 1
+3VL
ME@
ALLTO_C51126-112Z9-C
JBATT1
VMB BATT+
2
1
1 2 PL101 EMC@ PR101
VCCRTC
2 3 HCB2012KF-121T50_0805 @
3 4 0_0402_5%
1 2
4 5 EC_SMCA RTC_VCC1 PR102 PD102
1
5 6 EC_SMDA
6 7 PL102 EMC@ 1 2 VCCRTC_D1 3
7 8 HCB2012KF-121T50_0805
8 9
1
PC101 1 2 PC102 45.3K_0402_1% 1
9 10 1000P_0402_50V_X7R_0402 0.01U_0402_25V_X7R_0402
D 10 11 @ D
EMC@ PL103 EMC@ EMC@ 1 2 RTC_VCC_R1 2
For 560"
2
11 12 HCB2012KF-121T50_0805
12 13 1 2 PR104
GND1 14 JRTC1 BAT54CW_SOT323-3
1
1K_0603_5%
100_0402_1%
GND2 15 1 RTC@
PR105
GND3 16
1
1 RTC@
2
100_0402_1%
GND4 PR106 2 3
GND1
1
4 PC103
2
GND2
1U_0402_10V6K
@
2
2
PD101 EC_SMB_CK1 79,89
AZC199-02S.R7G_SOT23-3 HIGHS_WS33020-S0351-HF
EMC_NS@ ME@
EC_SMB_DA1 79,89
PR107 1 2 100K_0402_1% +3VALW

For 17"
BATT_TEMP_IN 1 2
BATT_TEMP 79,89 A/D +3VL
PR108
10K_0402_5%
2
PR103
VCCRTC
@ 0_0402_5%
RTC_VCC2 PR130 PD103
1
1 2 VCCRTC_D2 3
C 45.3K_0402_1% 1 C
@
1 2 RTC_VCC_R2 2
For 760"
PR109
JRTC2 BAT54CW_SOT323-3
1K_0603_5%
1 17@
1 2
17@
2 3
GND1
1
4 PC104
GND2
1U_0402_10V6K
@
2
HIGHS_WS33020-S0351-HF
ME@
B B
A A
Issued Date 2021/04/07 Deciphered Date 2021/04/07 PWR_DCIN/RTC
5
Vinafix.com
4 3
2
C
Size
Date:
Document Number
HY568 AMD
1
Sheet 87 of 110
Rev
0.1
5 4 3 2 1
VIN
CHARGER_IN
PL110 EMC@
HCB2012KF-121T50_0805
1 2
PL111 EMC@
HCB2012KF-121T50_0805
230W & 170W adapter 1 2
useSP040006900 24V PQ110 APDIN_2 PQ111
AON6403_DFN8 AON6403_DFN8
D JDCIN1 D
PL112 EMC@ 1 8 8 1
PF110
1 HCB2012KF-121T50_0805 2 7 7 2
GND_1 2 APDIN 1 2 APDIN2 1 2 3 6 6 3
POWER_1 3 5 5
DETECT(ID) 4 25A_24V_F1206HB25V024TM
POWER_2
1000P_0402_50V_X7R_0402
5
402K_0402_1%
4
4
GND_2
1000P_0402_50V_X7R_0402
0.1U_25V_K_X5R_0402
0.1U_25V_K_X5R_0402
6
PC113
402K_0402_1%
EMC_NS@
GND_3
1
1000P_0402_50V_X7R_0402
1000P_0402_50V_X7R_0402
EMC_NS@
PC114 EMC@
PC112 EMC@
7
PR110
PR112
PC115
GND_4
1
PC111
PC110
499K_0402_1%
1
ADAPTER_ID PD_CHG_GATE2
2
HIGHSTAR-PJSSS56-A6000-1H PD_CHG_GATE1
PR111
2
2
ME@
1
PR113 PR114
100K_0402_5% 100K_0402_5%
2
PD_CHG_GATE1_R PD_CHG_GATE2_R
3
D D
2 PQ112A 5 PQ112B
G L2N7002KDW1T1G_SOT363-6 G L2N7002KDW1T1G_SOT363-6
S S
4
+3VALW
1
PR115
PR124
750_0603_1% DCIN_ATTACHED 1 2 DCIN_ATTACHED_R
C C
2
100K_0402_5%
VIN +3VL
1
1
PR116 PC116
ADAPTER_ID 79
PC117 0.1U_25V_K_X5R_0402
680P_0402_50V_X7R_0402
100K_0402_5%
2
1000P_0402_50V_X7R_0402
2
1
1
0.1U_25V_K_X5R_0402
@
1
PR127
1
1
PC120
PC121
PD110 100K_0402_5%
1
@ 499K_0402_1%
AZ5123-01F.R7GR_DFN1006P2X2 PQ113 PR125
2
2
2
PR116 mount for 560 pull L PD_VBUS_C_CTRL1_R 2

SSM3K15AMFV_2-1L1B DCIN_ATTACHED_EC 79
2
1
2
PQ116
3
SSM3K15AMFV_2-1L1B
2
1000P_0402_50V_X7R_0402
3
1
PC122
PR126
1
53.6K_0402_1%
2
VBUS_TBTA VCC3_LDO_PDA
@
PR117 1 2 PR118 1 @ 2 0_0402_5%
10K_0402_5% Follow AMD (For Y760 AC only can not power on issue)0910
2
1
PU110 PD_OVLO PR119
PC118 1/16W_100K_5%_4P2R_0404
1 2 B2 B3
3
4
C2 VBUS1 OVLO A2 PD_ACK_SNK1
VBUS2 ACK PD_ACK_SNK1 51
1U_25V_K_X5R_0402 D2
B
E1 VBUS3 C3 B
CHARGER_IN CHARGER_OUT E2 VBUS4 GND1 D3
4.5A A1
VBUS5 GND2
GND3
E3
B1 VINT1 A3 PD_VBUS_C_CTRL1_EN#
HCB2012KF-121T50_0805 C1 VINT2 EN#
PL113 D1 VINT3
1 2 PQ106 VINT4 2
AONR21357_DFN8
1 8 NX20P5090UK_WLCSP15 PR121
2
HCB2012KF-121T50_0805 2 7 @ 0_0402_5%
PL114 3 6 PC119
1 2 5 1U_25V_K_X5R_0402
1
100K_0402_5%
PD_VBUS_C_CTRL1_R1
PR122
4
1
1
PC123 PR128 1 2
TBTA_GATE_VSYS 51
1
402K_0402_1%
1000P_0402_50V_X7R_0402 PQ114
2
SSM3K15AMFV_2-1L1B
2
2 PD_VBUS_C_CTRL1_R
1M_0402_5%
PR123
3
1
PR129
2
100K_0402_5%
1
PQ115
2
SSM3K15AMFV_2-1L1B
2 DCIN_ATTACHED
1
PQ117
3
SSM3K15AMFV_2-1L1B
2 PD_VBUS_C_CTRL1_R
3
A A
Follow AMD (For IEC62368 Safety testing)0916

PD_VBUS_C_CTRL1 H --> TPYE C 1 Use --> PD_VBUS_C_CTRL1_EN# Low
Issued Date 2021/04/07 Deciphered Date 2021/04/07 PWR_ACIN

HY568 AMD Rev
Vinafix.com
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
5 4 3 2 1
5 4 3 2 1
PQ5401 PQ5402
SMN2R0-30YLE AONS32306_DFN8-5
CHARGER_IN P2 B+
1 1 P3
2 2 PR5401
5 3 3 5 1 4
2 3
EMC_NS@
EMC_NS@
0.01U_0402_25V_X7R_0402
0.01U_0402_25V_X7R_0402
4
4
CHG_ACDRV_R2
1W_0.005_1%_1206
1
PC5403
PC5404
1
1
D D
PC5402
PC5401 0.022U_0402_25V_X7R_0402
2
470P_0402_50V_X7R_0402 PR5402
2
4.7_0603_5% PQ5403
5
AONS32314_DFN8-5
2
1 2
PC5405 CHG_BATDRV 4
1
PC5406 0.1U_25V_K_X5R_0402 PC5407
0.1U_25V_K_X5R_0402 0.1U_25V_K_X5R_0402
1
CHG_ACN
CHARGER_IN BATT+
CHG_ACP
3
2
1
1
PR5403
499K_0402_1% PC5408
CHG_ACDRV_R
0.01U_0402_25V_X7R_0402
2
2
B+
3
PD5401
BAT54CW_SOT323-3
10U_25V_M_X5R_0603
10U_25V_M_X5R_0603
0.1U_25V_K_X5R_0402
2 2
CHARGER_IN
1 CHG_VCC_R 1
EMC@
PC5410
PC5411
ACDET Threshold:min:17.878V
PC5409
2
BAT Max V 17.6V
1
1 1
1/10W_4.02K_1%_0603
1/10W_4.02K_1%_0603
PR5404
PR5405
CHG_VDD
1
1/16W_43.2K_1%_0402
PR5406
PR5407 PU5401
2
1
PR5408 PC5412 10_1206_5% BQ24780SRUYR_QFN28_4X4
6.49K_0402_1%
ACP
ACN
2
5
1 2 1U_25V_K_X5R_0402
5
C 1 2 CHG_VCC 28 24 1 2 PQ5406 C
VCC REGN 2.2U_10V_K_X5R_0402 PC5413 PQ5404
1 2 CHG_ACDET 6 0.047U_0402_16V_X7R_0402 AON6380_DFN8-5
PC5414 ACDET PC5415 AON6380_DFN8-5
need link CIS
0.01U_0402_25V_X7R_0402
BTST
25 CHG_BS1 2 CHG_BS_R 2 1
CHG_HG 4
CHG_HG 4 SH000027A00
PR5409
2.2_0603_5%
CHG_CMSRC 3 26
CMSRC HIDRV 2.2UH_CMME064T-2R2MS_12A_20% PR5410 BATT+
3
2
1
CHG_ACDRV 4 PL5401 0.005_1206_1%
3
2
1
ACDRV @
27 CHG_LX 1 2 1 4
PHASE
1
PR5411 1 @ 2 0_0402_5% CHG_ACOK 5 PQ5407 2 3
ACOK
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
0.1U_25V_K_X5R_0402
79 ACIN PR5412
EMC@
11 AON6324_DFN8-5
10U_0805_25V6K
SDA 1/8W_4.7_5%_0805
2
PC5418
79,87 EC_SMB_DA1 23 EMC_NS@
PC5416
PC5417
PC5443
PC5419
PC5420
PC5441
LODRV
2
12 22 CHG_LG 4
CHG_SN
1
79,87 EC_SMB_CK1 SCL GND
1
7 29
0.1U_25V_K_X5R_0402
0.1U_25V_K_X5R_0402
79 ADP_I IADP PAD
PC5421
3
2
1
1
CHG_BATT_I 8 18 CHG_BATDRV
PC5422
PC5423
1000P_50V_J_COG_0402
2
IDCHG BATDRV
9
2
79,95 PSYS PMON 17 CHG_BATSRC 1 2 CHG_BATSRC_R
BATSRC E
PR5413 10_0603_5% M
20 CHG_SRP 1 2 CHG_SRP_R C
10 SRP _
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
79 VR_HOT_N PR5414 10_0603_5% N

PROCHOT#
1
1
PMON Gain 1uA/W Actucl 0.5uA/W S
1
PR5415 13 PC5426 @
CMPIN
PR5415 15K 0.75V 100W 15K_0402_1% 0.1U_25V_K_X5R_0402
2
BATPRES#
PC5424
PC5427
PC5425
14
TB_STAT#
2
CMPOUT 19 CHG_SRN 1 2 CHG_SRN_R

2
CHG_ILIM 21 SRN PR5416 10_0603_5%

ILIM
2
B B
V charge (MAX):17.6V
CHG_TB# 16
PR5417 15
@ 0_0402_5% I charge (MAX):12A
FSW:800K
1
1 2 CHG_ILIM_R 1 2
+3VALW BATT_TEMP 79,87
PR5418 PR5419
1
105K_0402_1% 32.4K_0402_1%
1
PR5420
PC5428 100K_0402_1%
0.1U_25V_K_X5R_0402
2
IchargeLIM 16.1A
IDischargeLIM 64.4A
B+
0.1U_25V_K_X5R_0402
0.1U_25V_K_X5R_0402
0.1U_25V_K_X5R_0402
0.1U_25V_K_X5R_0402
0.1U_25V_K_X5R_0402
1000P_25V_K_X7R_0402
1000P_25V_K_X7R_0402
1000P_25V_K_X7R_0402
1000P_25V_K_X7R_0402
1000P_25V_K_X7R_0402
1
1
PC5429
PC5430
PC5431
PC5432
PC5433
PC5434
PC5435
PC5436
PC5437
PC5438
2
A A
EMC_NS@
EMC_NS@
EMC_NS@
EMC_NS@
EMC_NS@
EMC_NS@
EMC_NS@
EMC_NS@
EMC_NS@
EMC_NS@

Issued Date 2021/04/07 Deciphered Date 2021/04/07 PWR-charger
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
Document Number
HY568 Rev
0.1
Vinafix.com
5 4 3 2 1
A B C D
PJ6201
2 1
+3VLP 2 1 +3VL
+3V_VIN B+
+5VLP +3VLP JUMP_43X39
1A +5V_VIN JUMP_43X118
@
@
10A 2
PJ6208
1
2 1
1
1U_25V_K_X5R_0402
1U_25V_K_X5R_0402
10U_25V_M_X5R_0603
10U_25V_M_X5R_0603
22U_B2_25VM_R100M
0.1U_25V_K_X5R_0402
PC6201
1 1 1 1 1 1
+3V_VIN
0.1U_25V_K_X5R_0402
PC6240
PC6241
PC6209
PC6211
PC6242
1 1
+
PC6203
PC6204
PC6210
B+
EMC_NS@

LCFC NM-D711 r0.1

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LCFC NM-D711 r0.1

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A B C D E

Tiger Lake H-Processor with DDR4 + NV GN20-E GPU

Security Classification LC Future Center Secret Data Title

Issued Date 2021/04/07 Deciphered Date 2021/04/07 Cover Page

VBOIS ROM Memory BUS (DDR4 non-ECC)

1.2V DDR4 3200MT/s

GPIO3 MUX_CNTL Intel CPU UP TO 16G x 1

Burnside Bridge USB2.0 1x

Page 61 SATA Port0 PCIe 1x PCIe Port13 USB2.0 Port10

HP&Mic Combo Conn.

Battery Thermal Sensor Thermal Sensor CPU FAN

Security Classification LC Future Center Secret Data Title

AG Controller Thermal Sensor

UU3 and UU8

SMBUS Control Table

PCH_RGBKB_SDA X X X X X X X X X X +LDO_3V3 X X X +3VS

GPU PWR Monitor

Vinafix.com Issued Date 2021/04/07 Deciphered Date 2021/04/07 Blank4

Date: Wednesday, April 07, 2021 Sheet 4 of 110

GN20x-P/N18P-G61-A GPIO H=High: Tied to 1.8V

GPIO23 OUT UNUSED UNUSED test point

GPIO24 IN HPD_IFPF* Hot Plug Detect for IFPF UNUSED

M L H 1 1 0 1 1:PCIE_CFG LOW POWER

Date: Wednesday, April 07, 2021 Sheet 5 of 110

Voltage Rails ( O --> Means ON , X --> Means OFF )

VCCSTG board ID HY568-15-

BL@ BL RH1204 GN20P0@ RH1204 N18P@ RH1203 GN20P1@ RH1203 GN20P0D@

Debug@ USB2.0 port 1for Debug GS@ Reserved for G-sensor

M6GX6@S6GX6@ VRAM part UC1 11260H@ UC1 11600H@

4 Type-C Port OVRM NCP45495X

GN20x-P and N18P-G61-A CO-LAY PWR BTN EMC ZZZ12 X76NCP491@

AZ5725-01F.R7GR_DFN1006P2X2 AZ5725-01F.R7GR_DFN1006P2X2 load GEN1_ON@ S IC NCP45491XMNTWG QFN 32P MONITOR

PWR LED OVRM US5650Q

GN20P QS2 / N18P-MP sample

S IC N18P-G61-A-A1 FCBGA 1358 GPU MP 12! GPU DRMOS NCP303150

NVVDD AOS5279@ PR2055 AOS5279@ PR2065 AOS5279@ PR2074 AOS5279@

S RES 1/16W 309 +-1% 0402

S IC AOZ5279QI QFN 39P POWER

Date: Wednesday, April 07, 2021 Sheet 6 of 110

PCIE4_CRX_DTX3_P N29 3 OF 15 E28 PCIE4_CTX_DRX3_P

Security Classification LCFC Highly Confidential Information Title

+3VALW_SYS +3VS CAD Note:

Security Classification LCFC Highly Confidential Information Title

Security Classification LCFC Highly Confidential Information Title

CFG Straps for CPU

 11 1 x16 PCI Express

Security Classification LCFC Highly Confidential Information Title

Security Classification LCFC Highly Confidential Information Title

RC34 Plug in: High

RC892 PCH_IFPA_HPD RC864

DPIP_HPD Voltage is 0.98V CC1540 RC867 100K_0201_5%

RC893 Vgs(th)≤0.9V @ 220P_0402_50V7K @ 100K_0201_5%

DPIP_HPD Voltage is 0.98V

Security Classification LCFC Highly Confidential Information Title

+VCCIO from PWR +VCCIN +VCCIN

B from PWR +VCCSTG_CPU +VCCSTG_FPGM B

LC6 1 @ 2 0_0603_5% VCCIN_AUX +VCCIN_AUX_FIL

Security Classification LCFC Highly Confidential Information Title

Security Classification LCFC Highly Confidential Information Title

UC1F UC1G UC1H

TIGERLAKE-H-CPU_BGA1787 TIGERLAKE-H-CPU_BGA1787 TIGERLAKE-H-CPU_BGA1787

Security Classification LCFC Highly Confidential Information Title

AF3 5 OF 9 C36 PCIE_SATA_PTX_DRX12_P

CMOS RH1 1 2 10M_0402_5% PCH_RTCX2