Inter-Integrated Circuit “I2C”

Introduction (1)
 I²C enables the communication between MCUs and their peripheral devices.

 The communication is done by using two wires SDA and SCL.

 The data transfer rate can be:

 Up to 100 Kbit /s in standard mode.
 Up to 400 Kbit /s in fast mode.
 Up to 3.4 Mbit /s in High-speed mode.

 Each device has a unique address with 7 bits, 10 bits or 16 bits.

 Each device can serve as a transmitter, a receiver, or both.

Introduction (2)
 The master device initializes a data transfer on the bus.

 Then it generates the clocks signals to permit that data transfer.

 Finally, it terminates the transfer.

 The device addressed by the master called slave.

Vcc
Slave Device Slave Device
Address: 1101001 Address: 0100111

Pull-up R1 Pull-up R2

SDA
Master Device SCL
I²C Pins
 The pins connected to SDA and SCL lines should be configured as open-drain.

 In open-drain, the output is in positive voltage if an active high is outputted.

 The output pin is in a high impedance state if a low is outputted.

 Software can configure the SDA and SCL pins as open-drained.

 The pull-up resistor within the processor is too large, in order of 100 kΩ.

 To reduce the rise time of I²C lines, smaller resistors, such as 3 kΩ, are often used.
I²C Protocol (1)
 The communication begins with START bit (S) and terminates with STOP bit (P)

 A START bit is defined as a high-to-low transaction of SDA while SCL is high.

 A STOP bit is defined as a low-to-high transaction of SDA while SCL is high.

 The master generates both START and STOP bits.

 The I²C interfacing HW of all peripherals devices is capable of detecting START and STOP.

 After the START bit, the master begins to send data byte by byte.

 The slave sends an acknowledge bit to the master.

 The transmitter releases the SDA line during the ACK clock period (nineth clock period).
I²C Protocol (2)
 The communication begins with START bit (S) and terminates with STOP bit (P)

 A START bit is defined as a high-to-low transaction of SDA while SCL is high.

 A STOP bit is defined as a low-to-high transaction of SDA while SCL is high.

 The master generates both START and STOP bits.

 The I²C interfacing HW of all peripherals devices is capable of detecting START and STOP.

 After the START bit, the master begins to send data byte by byte.

 The slave sends an acknowledge bit to the master.

 The transmitter releases the SDA line during the ACK clock period (nineth clock period).