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EE6008-Microcontroller Based System Design Department Of EEE 2017-2018

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING

EE6008 - Microcontroller Based System Design

UNIT – III PERIPHERALS AND INTERFACING

PART – A
1. What is an I2C bus?
I2C is a serial protocol for two-wire interface to connect low-speed devices like microcontrollers, EEPROMs,
A/D and D/A converters, I/O interfaces and other similar peripherals in embedded systems. It was invented by
Philips and now it is used by almost all major IC manufacturers. I2C bus is popular because it is simple to
use, there can be more than one master, only upper bus speed is defined and only two wires with pull-up
resistors are needed to connect almost unlimited number of I2C devices. I2C can use even slower
microcontrollers with general-purpose I/O pins since they only need to generate correct Start and Stop
conditions in addition to functions for reading and writing a byte.
2. Draw the Block diagram of I2C bus.

3. What are the modes of operation in I2C bus?

There are three data transfer speeds for the I2C bus: standard, fast-mode, and high-speed mode. Standard
is 100 Kbps. Fast-mode is 400 Kbps, and high-speed mode supports speeds up to 3.4 Mbps. All
are backward compatible. The I2C bus supports 7-bit and 10-bit address space devices and devices that
operate under different voltages.
4. How does PIC write data through I2C bus?
 A peripheral chip address and a read/write bit designating that the peripheral chip is to read successive
bytes.
 A peripheral internal register or address byte.
 Data to write into one or more consecutive internal addresses.
5. How PIC does reads data through I2C bus?
 PIC sends out a peripheral chip address and a read/write bit designating that the peripheral chip is to
send one or more successive bytes beginning at a previously selected internal register or address.
 Reads back one or more bytes of data.
6. Draw the format of I2C bus to read and write from several peripheral interfaces.

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7. Write a note on temperature sensor used for interfacing with I2C bus.
National Semiconductor’s LM 75 chip combines an analog temperature transducer, an analog-to-digital
convertor (9-bit), and an I2C bus interface, all in a tiny S)-8 surface mount package. The temperature range
covered is -25oC to +100oC with ±2oC accuracy. The two’s complement form of the temperature is available
from the 9-bit ADC. The resolution of the ADC is about 0.5oC.

8. What is the function of TRISA pin?

Setting TRISA bit will configure portA as input and resetting will configure as output port.

9. What is synchronous and asynchronous transmission?

Asynchronous – start and stop bit allowed for transmission of data. Synchronous – no start and
stop bit only block header data.
10. What is baud rate in asynchronous mode?
The baud rate in asynchronous mode is given by B.R = Fosc/64.(x+1) for low speed, and Fosc/16(x+1) for
high speed.
11. How data is transmitted serially using UART?
To transmit a byte of data serially from the TX pin, the byte is written to the TXREG register. Assuming there is
not already data in the TSR, the content of TXREG will be automatically transferred to TSR, making TXREG
available for a second byte even as the first byte is being shifted out of the TX pin, framed by START and STOP
bits.
12. What is key debouncing?
Key bouncing may cause multiple entries made for the same key. To overcome this problem after a key
press is sensed the device is made to wait for few milliseconds. Then the key is checked again to
ensure it is still pressed. If it is still pressed it is taken as a valid key press. This process is called
keyboard debouncing.
13. Name any two types of ADCs.
The different types of ADC are successive approximation ADC, Counter type ADC flash type ADC, integrator
converters and voltage to-frequency converters.
14. What is the difference between A/D and D/A converters?
Digital-to-analog conversion is to pull the samples from memory and convert them into an impulse train.
An ADC is attempting to capture and convert a largely unknown signal into a known representation. In
contrast, a DAC is taking a fully known, well-understood representation and "simply" generating an
equivalent analog value. The challenge for an ADC is much greater than it is for a DAC.

15. What is the value to be loaded into SPBRG register if we want 19200 baud rate with 10MHZ clock
source. (Nov/Dec 2016)
01101010 is the value to be loaded into SPBRG register

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EE6008-Microcontroller Based System Design Department Of EEE 2017-2018

UNIT – III PERIPHERALS AND INTERFACING

PART – B
1. What is meant by I2C module? Explain how I2C is interfaced with PIC microcontroller. Nov/Dec 2016

Data bits Acknowledge bit

(driven by transmitter) (driven by receiver)

The clock line, SCL, is driven by the PIC chip, which server as bus master. The open drain feature of every chip’s
bus driver can be used by the receiver to hold the clock line low, there by signalling the transmitter to pause until
the clock line is released by the receiver. The open drain feature is also needed if this PIC will ever become an
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I2C slave to another PIC, in which it must relinquish control of the SCL line.

The previous figure illustrates that the first eight bits on the SDA line are sent by the transmitter whereas the
ninth bit is the acknowledgment bit which is sent by the receiver in response to the byte sent by the
transmitter. For instance, when the PIC sends out a chip address, it is the transmitter,
while every other chip on the I2C bus is a receiver. During the acknowledgment bit time, the addressed chip
is the only one that drives the SDA line, pulling it low in response to the masters pulse on SCL,
acknowledging the reception of its chip address.
When the data transfer direction is reversed that is form a peripheral chip to the PIC, which is the master ,
the peripheral chip drives the eight daa bits in response to the clock pulse from PIC. In this case, the
acknowledge bit is driven in a special way by the PIC, which is serving as receive but also as bus master. If
the peripheral chip is one that can send the contents of successive internal address back to the PIC, then
PIC completes the reception of each byte and signals a request for the next byte by pulling SDA line low in
acknowledgment. After any number of bytes have been received by the master from the peripheral, the PIC
can signal the peripheral to stop any further transfers by not pulling the SDA line low in acknowledgment.

SDA line should be stable during high period of the clock (SCL). When the slave peripheral is driving SDA
line , either as transmiter or acknowledge, it initiates the new bit in response to the falling edge of SCL, after
a specified time. It maintains that bit on SDA line until the next falling edge of SCL, again afte r a specified
hold time.

I2C bus transfers consist of a number of byte transfers framed between a START condition and either
another START condition or a STOP condition. Both SDA and SCL lines are released by all drives and float
high when bus transfers are not taking place. The PIC (I2C bus controller) initiates a transfer with a START
condition by first pulling SDA low and then pulling SCL as shown in the figure.

SDA

SDA

SCL

SCL

START Condition STOP Condition

Similarly, the PIC terminates a multiple byte transfer with the STOP condition. With both SDA and SCL
initially low, it first releases SCL and then SDA. Both then occurrences are easily recognized by I 2C
hardware in each peripheral chip since they both consist of a chage in SDA line which SCL is high, a
condition that never happens in the middle of a byte transfer.
Data Communication protocol
In I2C communication standard, there is one bus master and several slaves. It can be assumed here
that the PIC microcontroller is the bus master and several peripheral devices connected to SDA and
SCL bus are slaves.
Following a start condition, the master sends a 7-bit address of the slave on SDA line. The MSB is sent
first. After sending 7 bit address of the slave peripheral a R/W bit (8th bit) is sent by the master. If R/W bit
is 0 the following byte (after the acknowledgment) is written by the master to the addressed slave
peripheral. If R/W bit is 1, the following byte after the acknowledgment bit has to be read from the slave
by the master. After sending the 7-bit address of the slave, the master sends the address of the internal
register of the salve where from the data has to be used or written to. The subsegment access is
automatically directed to the next address of the internal register.
The following diagrams give the general format to write and read from several peripheral internal
registers
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.
START R/ W = 0
condition 7-bit address for write Internal address N, Data to be written
of peripheral chip in peripheral into address N

A A A
C C C
S WK K K

SDA
Data to be written Data to be written
STOP
into address N+1 into address N+2
condition
A A
C C
K K P

2. Explain with example the concept of I2C subroutine in PIC microcontroller.

I 2 C Subroutine
SDA equ 4
SCL equ 3
The following subroutine DATA_OUT transfers out three bytes, i.e., ADDRDEV, ADDR8, and DATAWRTE
DATA_OUT: call START ; Generate start condition
movf ADDRDEV, W ; Sends 7-bit peripheral address with R/ W=0
call TRBYTE ; Transmit
movf ADDR8, W ; Send 8-bit internal address
call TRBYTE
movf DATAWRTE, W ; Send data to be written
call TRBYTE
call STOP ; Generate Stop condition
return
The DATA_IN subroutine, which is given below transfers out ADDRDEV (with R/ W=0) and ADDR8, restarts
and transfers out ADDRDEV (with R/ W =1) and read one byte back into RAM variable DATARD.
DATA_IN: call START
movf ADDRDEV, W ; Send 7-bit peripheral address R/ W=0
call TRBYTE
movf ADDR8, W ; Send int. address
call TRBYTE
call START1 ; Restart
movf ADDRDEV, W ; Send 7-bit peripheral address R/W=1
call TRBYTE
bsf TRBUF, 7 ; Generate NO ACK
call RCVBYTE
movwf DATARD
call STOP
return
The 'START' subroutine initializes I2C bus and then generates START condition on the I 2C bus. START1 bypasses the
initialization of I 2C.
START: movlw 3BH ;enables I2C master mode by programming SSPCON
movwf SSPCON
bcf PORTC, SDA ; drive SDA low when it is an o/p
movlw TRISC ;set indirect pointer to TRISC
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movwf FSR
START1:
bsf INDF, SDA ; SDA=1
bsf INDF , SCL ; SCL=1
call DELAY ; Generates a suitable delay
bcf INDF, SDA ; SDA=0
call DELAY ; Generate a suitable delay
bcf INDF, SCL ;SCL=0
return
STOP:
bcf INDF, SDA ;SDA=0
bsf INDF, SCL ; SCL=1
call DELAY ; Generate a suitable delay
bsf INDF, SDA ;SDA=1
return
The subroutine 'TRBYTE' send out the byte available in w. It returns with Z=1 if ACK occurs. It returns with Z=0 if NOACK occurs.
TRBUF is an 8-bit RAM variable used for temporary storage. The bits are shifted to carry flag (C) and the carry bit
transmitted successively. Data transfer is complete when all 8-bits are transmitted. Setting C = 1 initially sets an index for 8-bits
to be transferred. C is rotated through TRBUF. After transmitting C, C-bit is cleared. When TRBUF is completely cleared,
all 8-btis are transmitted.
TRBYTE:
movwf TRBUF
bsf STATUS,C
TR_1:

rlf TRBUF, F
movf RBUF,F
btfss STATUS, Z
call out_bit ; Send a bit available in C
btfss STATUS, Z
goto TR_1
call in_bit ; Get the ACK bit in RCBUF<0>
movlw 01H ;
andwf RCBUF, W ; Store the complement of ACK bit in Z flag
return
The RCVBYTE subroutine receives a byte from I2 C into W using a RAM variable RCBUF buffer.
Call RCVBYTE with bit 7 of TRBUF clear for ACK
Call RCVBYTE with bit 7 of TRBUF set for NOACK
RCBUF is an 8-bit RAM variable used for recieving the data. the bit is recieved in the RCBUF<0> and is rotated
successively through RCBUF as shown. The reception ends when all 8-bits are recieved.
RCVBYTE:
movlw 01H
movwf RCBUF ; Keep an index for 8-bits to be recieved.

rlf RCBUF, F
call In_bit
btfss STATUS, C
goto RCV_1
rlf TRBUF, F
call Out_bit
movf RCBUF,w

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return
The out_bit subroutine transmits carry bit, then clears the carry bit.
Out_bit:
bcf INDF, SDA
btfsc STATUS, C
bsf INDF, SDA ; Send carry bit
bsf INDF, SCL
call DELAY
bcf INDF, SCL
bcf STATUS,C ; Clear carry bit
return
The in_bit subroutine receives one bit into bit-0 of RCBUF.
In_bit:
bsf INDF,SDA
bsf INDF, SCL
bcf RCBUF, 0
btfsc PORTC, SDA ; Check SDA line for data bit
bsf RCBUF, 0
bcf INDF, SCL
return

3. Explain in detail the interfacing of temperature sensor using I2C bus.

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4. Explain with neat diagram interfacing of serial EEPROM using I2C bus.

5. Explain with neat diagram the use of UART to interface two PIC resources.

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