Serial Interfaces

Introduction to I2C, SPI & UART

Serial Communication
 The concept of serial communication is the process of
sending data one bit at a time, sequentially, over a
communication channel.
 This is in contrast to parallel communication, where several
bits are sent as a whole, on a link with several parallel
channels.
 Advantages of Serial Communication
– Integrated circuits are more expensive when they have more
pins. To reduce the number of pins in a package, many ICs use
a serial bus to transfer data.
– Serial communication is used for all long-haul communication to
reduce the cost of the cable.

Reference : Serial communication. (2010, July 12). In Wikipedia, The Free Encyclopedia. Retrieved 06:30, July 29, 2010, from
http://en.wikipedia.org/w/index.php?title=Serial_communication&oldid=373069241
Various Serial Communication Examples
 High Speed Serial Communication Examples
– SATA Rev 1.0 with a data rate of 1.5 Gbps.
– SATA Rev 2.0 with a data rate of 3.0 Gbps.
– SATA Rev 3.0 with a data rate of 6.0 Gbps.
– SAS Gen 1 with a data rate of 3.0 Gbps.
– SAS Gen 2 with a data rate of 6.0 Gbps.
– PCI Express 1.0 with a data rate of 2.5 Gbps.
– PCI Express 2.0 with a data rate of 5 Gbps.
– PCI Express 1.0 with a data rate of 8 Gbps.

 Low Speed Serial Communication Examples

– I2C Bus with a data speed spanning from 100 Kbit/s to 3.4 Mbit/s.
– SPI Bus. Standard does not specify maximum data rate. Peripherals available
operating with a maximum of 104 MHz.
– RS-232. Speeds range from 9600 bits/sec to 115200 bits/sec.
I2C Bus – Introduction
 Even amongst seemingly unrelated electronic products, some
similarity in design would often exist. For e.g.
– Some intelligent controller, say a microprocessor or microcontroller.
– General purpose LCD / LED drivers, Real time clocks, A-D Converters &
D-A Converters etc.
– Sensors like Temperature Sensors.

 Some form of communication needs to exist for the coherent

operation of the system.
 Philips Semiconductors (now NXP Semiconductors) developed a
simple bidirectional 2-wire bus for efficient inter-IC control. This bus
is called the Inter IC or I2C-bus.
 All I2C-bus compatible devices incorporate an on-chip interface
which allows them to communicate directly with each other via the
I2C-bus.

Reference : UM10204 - I2C Bus Specification & User Manual from NXP Semiconductors
I2C Bus – Features
 Only two bus lines are required; a serial data line (SDA) and a serial
clock line (SCL).
 Each device connected to the bus is software addressable by a
unique address and simple master/slave relationships exist at all
times; masters can operate as master-transmitters or as master-
receivers.
 It is a true multi-master bus including collision detection and
arbitration to prevent data corruption if two or more masters
simultaneously initiate data transfer.
 Serial, 8-bit oriented, bidirectional data transfers can be made at
– Up to 100 kbit/s in the Standard-mode.
– Up to 400 kbit/s in the Fast-mode.
– Up to 1 Mbit/s in Fast-mode Plus.
– Up to 3.4 Mbit/s in the High-speed mode.

Reference : UM10204 - I2C Bus Specification & User Manual from NXP Semiconductors
I2C Bus – Example LED Driver

Reference : PCA9633 Datasheet from NXP Semiconductors

I2C Bus – Terminology

Reference : UM10204 - I2C Bus Specification & User Manual from NXP Semiconductors
I2C Bus – Signal Lines
 The two signal lines SDA and SCL are bidirectional lines, connected
to a positive supply voltage via a pull-up resistor.
 When the bus is free, both lines are HIGH. The output stages of
devices connected to the bus must have an open-drain or open-
collector to perform the wired-AND function.

 The levels of the logical ‘0’ (LOW) and ‘1’ (HIGH) are set as 30% and
70% of VDD; VIL is 0.3VDD and VIH is 0.7VDD.

Reference : UM10204 - I2C Bus Specification & User Manual from NXP Semiconductors
I2C Bus – Data Validity
 The data on the SDA line must be stable during the HIGH
period of the clock.
 The HIGH or LOW state of the data line can only change
when the clock signal on the SCL line is LOW.
 One clock pulse is generated for each data bit transferred.

Reference : UM10204 - I2C Bus Specification & User Manual from NXP Semiconductors
I2C Bus – START & STOP Condition
 All transactions begin with a START (S) and can be terminated by a
STOP (P).
 A HIGH to LOW transition on the SDA line while SCL is HIGH
defines a START condition.
 A LOW to HIGH transition on the SDA line while SCL is HIGH
defines a STOP condition.
 START and STOP conditions are always generated by the master.

Reference : UM10204 - I2C Bus Specification & User Manual from NXP Semiconductors
I2C Bus – Byte Format
 Every byte put on the SDA line must be 8 bits long.
 The number of bytes that can be transmitted per transfer is
unrestricted.
 Each byte has to be followed by an Acknowledge bit.
 Data is transferred with the Most Significant Bit (MSB) first.

Reference : UM10204 - I2C Bus Specification & User Manual from NXP Semiconductors
I2C Bus – Arbitration
 Arbitration refers to a portion of the protocol required only if more
than one master will be used in the system.
 A master may start a transfer only if the bus is free. Two masters
may generate a valid START condition on the bus.
 Arbitration is then required to determine which master will complete
its transmission.

Reference : UM10204 - I2C Bus Specification & User Manual from NXP Semiconductors
I2C Bus – Data Transfer
 After the START condition (S), a slave address is sent.
 This address is 7 bits long followed by an eighth bit which is a data direction
bit (R/W) — a ‘zero’ indicates a transmission (WRITE), a ‘one’ indicates a
request for data (READ).
 A data transfer is always terminated by a STOP condition (P) generated by
the master.

Reference : UM10204 - I2C Bus Specification & User Manual from NXP Semiconductors
I2C Bus – Possible Data Transfer Formats

Reference : UM10204 - I2C Bus Specification & User Manual from NXP Semiconductors
I2C Bus – Other evolved variants
 SMBus – System Management Bus.
 PMBus – Power Management Bus.
 IPMI – Intelligent Platform Management Interface.

Reference : UM10204 - I2C Bus Specification & User Manual from NXP Semiconductors
I2C Bus – Electrical Specifications

Reference : UM10204 - I2C Bus Specification & User Manual from NXP Semiconductors
SPI Bus – Introduction
 A Serial Peripheral Interface (SPI) system is a Master-Slave
protocol.
 SPI consists of one master device and one or more slave
devices.
 The master is defined as a microcontroller providing the SPI
clock and the slave as any integrated circuit receiving the SPI
clock from the master.
 SPI is also called “four wire” serial bus and operates in full-
duplex mode.
 Standard has been defined by Motorola.

Reference : TN15_SPI_Interface_Specification from VTI Technologies

Reference : Getting started in SPI from Microchip

SPI Bus – Features
 In SPI, data are always transferred in both directions.

 It is up to the master and slave devices to know whether a

received byte is meaningful or not.
 A device must discard the received byte in a “transmit only”
frame or generate a dummy byte for a “receive only” frame.
 SPI does not have an acknowledgement mechanism to
confirm receipt of data.
 SPI is better suited to applications in which devices transfer
data streams such as the communication between a “codec”
(coder-decoder) and a digital signal processor.

Reference : Introduction to Serial Peripheral Interface from Embedded Systems Design

SPI Bus – Example Serial EEPROM

Reference : AT25512 SPI Serial EEPROM from Atmel

SPI Bus – Signal Lines
 CS~ or SS~ : Chip Select or Slave Select
– When this signal goes low, the slave will listen for SPI clock and
data signals.
 SCK : Serial Clock
– It is generated by the master device and controls when data is
sent and when it is read.
– Data is typically output from the transmitter during the falling
edge of SCK.
– Data is typically latched by the receiver during the rising edge of
SCK.

 SDO : Serial Data Output

 SDI : Serial Data Input

Reference : Getting started in SPI from Microchip

SPI Bus – Typical SPI Connection

Reference : AT25512 SPI Serial EEPROM from Atmel

I2C & SPI – A Comparison

Reference : Application Note AN4024 from Maxim

More info on testing I2C & SPI interfaces

 A one hour webinar is available from Agilent

Technologies and it can be viewed at

http://www.home.agilent.com/agilent/eventDetail.jspx?
cc=US&lc=eng&ckey=1450545&nid=-
11143.0.00&id=1450545&pselect=SR.General
UART – Introduction
 A Universal Asynchronous Receiver/Transmitter (UART) is a
type of "asynchronous receiver/transmitter", a piece of
computer hardware that translates data between parallel and
serial forms.
 An example of UART communication is RS-232.
 UARTs are commonly included in microcontrollers.
 A UART is usually used for serial communications over a
computer or peripheral device serial port.
 Serial ports are used as a control console for diagnostics &
configuration.
 Many modern personal computers do not have a serial port
since this legacy port has been superseded by USB now.

Reference : Universal asynchronous receiver/transmitter. (2010, July 28). In Wikipedia, The Free Encyclopedia. Retrieved 15:14,
August 1, 2010, from http://en.wikipedia.org/w/index.php?title=Universal_asynchronous_receiver/transmitter&oldid=375909355
UART – Features
 The Universal Asynchronous Receiver/Transmitter (UART) controller
is the key component of the serial communications subsystem of a
computer.
 The UART takes bytes of data and transmits the individual bits in a
sequential fashion. At the destination, a second UART re-assembles
the bits into complete bytes.
 Serial transmission of digital information (bits) through a single wire
or other medium is much more cost effective than parallel
transmission through multiple wires.
 The UART usually does not directly generate or receive the external
signals used between different items of equipment. Typically,
separate interface devices are used to convert the logic level signals
of the UART to and from the external signaling levels.

Reference : Universal asynchronous receiver/transmitter. (2010, July 28). In Wikipedia, The Free Encyclopedia. Retrieved 15:14,
August 1, 2010, from http://en.wikipedia.org/w/index.php?title=Universal_asynchronous_receiver/transmitter&oldid=375909355
RS-232 – Example Connection
RS-232 – Signal Lines

Reference : http://en.wikipedia.org/w/index.php?title=Serial_port&oldid=375074019
RS-232 – Bus Speeds & Signal Levels
 The typical operational speeds of the RS-232 bus are:
– 9600 bits/sec
– 19200 bits/sec
– 38400 bits/sec
– 57600 bits/sec
– 115200 bits/sec

Reference : RS-232. (2010, July 30). In Wikipedia, The Free Encyclopedia. Retrieved 17:56, August 1, 2010, from
http://en.wikipedia.org/w/index.php?title=RS-232&oldid=376240910
RS-232 – Null Modem
 Null modem is a communication method to connect two DTEs
directly using an RS-232 serial cable.
 The RS-232 standard is asymmetrical as to the definitions of
the two ends of the communications link so it assumes that
one end is a DTE and the other is a DCE e.g. a modem.

Reference : Null modem. (2010, July 16). In Wikipedia, The Free Encyclopedia. Retrieved 18:01, August 1, 2010, from
http://en.wikipedia.org/w/index.php?title=Null_modem&oldid=373861640
RS-232 – Null Modem Connection

Reference : Null modem. (2010, July 16). In Wikipedia, The Free Encyclopedia. Retrieved 18:01, August 1, 2010, from
http://en.wikipedia.org/w/index.php?title=Null_modem&oldid=373861640
Thank You