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A B C D E

MS-1485 Ver : 0B Chief River Platform


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Table of Contents DC JACK
+3V +5V
Page Description &
ATI Thames
Selector
01_Block Diagram TPS51125RGER
02_SMB Topology DDR3 1GB PCI-E x16
DDRIII-SODIMM0
03_CLock Delivery chart (64Mx16bitx8)
04_Power dellivery chart
CPU +1_5VDIMM +0_75VRUN
05_Ivy Bridge (HOST BUS & XDP) Dual Channel DDRIII
06_Ivy Bridge (DDR3) IVY BRIDGE 1066/1333/1600 MHz
TPS51218 APL5331KAC
07_Ivy Bridge (POWER) DDRIII-SODIMM1
08_Ivy Bridge (GRAPHICS POWER) SYS POWER
09_Ivy Bridge (GND) +VTT_CORE(1.05V)
10_Ivy Bridge (RESERVE)
LVDS HDMI CRT
11_DDR3 SODIMM 0 +0.85VRUN
12_DDR3 SODIMM 1
13_Thames GPU(PCIE) GPU_CORE POWER
14_Thames GPU(MEM)
TPS51218
15_Thames GPU(DP)
16_Thames GPU(POWER GND)
17_Thames GPU(VRAM_A)
18_Thames GPU(VRAM_B) FDI Interface DMI Interface
+1_8VRUN
19_Thames GPU(SEQUENCE)
2
+1_8VRUN_GPU 2

20_CRT/LVDS
MP2107ADN
21_HDMI
22_BTB CONN
23_PANTHER POIN (HDA/JTAG/SATA) USB PORT
SATA0 HDD
24_PANTHER POI(PCI-E/SMBUS/CLK) (USB3.0 COMBO)
25_PANTHER POINT (DMI/FDI/GPIO)
CPU POWER
26_PANTHER POINT (LVDS/DDI)
27_PANTHER POIN (PCI/USB/NVRAM) Graphic POWER
28_PANTHER POI (GPIO/NCTF/RSVD) SATA1 ODD
USB PORT
29_PANTHER POINT (POWER) PCH (USB3.0 COMBO) ISL95831
30_PANTHER POINT (POWER)
31_PANTHER POINT (GND) PCI-E LAN USB 3.0
MINI PCIE
32_USB3.0 PANTHER POINT USB 3.0
Conn. X2
33_KBC/EC/uP (KB3930-A1) RTL8111EL Conn. X1
34_GIGA LAN (RTL8111EL) CHARGER

USB 0,1
35_WLAN
MAX8731
36_HDD/ODD/FAN/BT/USB
37_AUDIO(ALC269) USB2 USB PORT
38_M_Battery select PCI-Express
39_M_Charger
40_M_System Power
41_M_DIMM_1.5VRUN AUDIO ALC269 Azalia USB 1.1/2.0 USB3 USB PORT
3 3
42_M_VTT_1.8VRUN
43_M_0.85V SPI Flash
NB-SPI
44 M_CPU 32M
45_GPU POWER USB4 BT/WLAN COMBO
46_EMI/Screw
47_1485A_Cardreader,Audio,USB LPC
LPC BUS
48_1485B_Lauch Board DEBUG
49_1485C_TP,LED Board Earphone USB5 WebCAM
50_Power on Sequency
MIC
51_Power down Sequency Keyboard
52_Power Diagram Internal SPK
53_History USB8 Card Reader
Internal MIC
Touch Pad
KBC
ENE 3930 USB9 BT/WLAN COMBO
LID

Smart Fan LED


USB10 MINI PCIE
CPU & S ystem

4 EC-SPI 4

SPI BIOS

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Title

Block Diagram
Size Document Number Rev
Custom 0B
MS-14851
Date: Friday, December 02, 2011 Sheet 1 of 53
A B C D E

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A B C D E

+3VSUS +3VRUN +3VRUN +3VRUN +3VRUN +VTT_CORE +VTT_CORE


2.2K 2.2K 2.2K 2.2K
54.9R
G DIMM1 DIMM2 130R 130R
G
1 SMBCLK VIDSCLK 1

SUS_SMBCLK SMB_CLK_DIMM VR_SVID_CLK


D S CPU POWER IC
SMBDATA VIDSOUT
SUS_SMBDATA D S SMB_DATA_DIMM VR_SVID_DATA

+3VSUS +3VRUN +3VRUN +3VALW


2.2K 2.2K 2.2K 2.2K
+3VALW
PCH
G 4.7K 4.7K
G
SML1CLK
SML1_CLK SMB_CLK_EC BATCLK_M
D S KBC BATTERY
2
SML1DATA 2
SML1_DATA D S SMB_DATA_EC BATDATA_M

+3VRUN +3VRUN +5VRUN


2.2K 2.2K 4.7K 4.7K
DGPU_PWRGD VDDR3
G
G 2.2K 2.2K
CRT_DDC_CLK
CRT_CLK_UMA DDC_CLK VGA G
S D G
CRT_DDC_DATA Connect
CRT_DATA_UMA DDC_DATA SMB_THRMGPU_CLK
S D D S GPU

3 +3VRUN +3VRUN +5VRUN D S SMB_THRMGPU_DATA 3

2.2K 2.2K 2.2K 2.2K


G
G
DDPD_CTRLCLK
HDMI_SCL SCLDDC HDMI
S D
DDPD_CTRLDATA Connect
HDMI_SDA SDADDC

+3VRUN S D

4 2.2K 4

2.2K
L_DDC_CLK LVDS MICRO-STAR INT'L CO.,LTD.
LVDS_DDC_CLK
Title

Connect SMB Topology


L_DDC_DATA Size Docum ent Num ber Rev
Cus tom 0B
MS-14851

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LVDS_DDC_DATA
Date: Friday, Decem ber 02, 2011 Sheet 2 of 53
A B C D E
A B C D E

4 4

3 3

2 2

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Title

CLock Delivery chart


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Size Document Number Rev
A 0B
MS-14851
Date: Friday, December 02, 2011 Sheet 3 of 53
A B C D E
A B C D E

+3VALW
0
POWER Button
POWER Input +3VALW
0
PWR_SRC
PWR_SW#
1 0 SPI
4
0 GPXIOD4 SPI FLASH 4
ROM
0
+5VALW 5VSUS_EN SUS_ON 2
0 EN1 GPXIOA01 PM_PWRBTN# :
+3VALW Should be over 150msec
TPS51125
Regulator 3VSUS_EN RSMRST# :
MAX17062ETB+T 3 EN2 Asserted <10mses after
Step up +5VSUS
+5VSUS 3 +3VSUSPWROK=High
+12V_FAN DC-DC +3VSUS SUSPWROK 4
CONVERTER PGOOD GPXIOD0 5 RSMRST#
GPXIOA02 RSMRST# & DPWROK
6 PM_PWRBTN#
+5VSUS PWR_SRC PWRBTN#

PM_SLP_S5# 7 SLP_S5# 19
10 DIMM_ON 9 GPXIOD5 DRAMPWRGD SM_DRAMPWRGD
+1_5VDIMM EN GPXIOA03 PM_DRAM_PWRGD
TPS51117 PM_SLP_S4# 8 SLP_S4# (Delay Min:1ms)
GPXIOD1 21 UNCOREPWRGOOD 22
10a
+1_5VDIMM_PWRGD PGOOD1 PM_SLP_S3# 11 SLP_S3# PROCPWRGD H_CPUPWRGD SVID
GPXIOD2
(Delay Min:41ms)
18 RESET#
+5VSUS +3VSUS PWROK
EC_PCH_PWROK APWROK
20
SM_DRAMRST# DRAMRST#
13 D D RUN_ON 24 SYS_PWROK PLTRST# 25
+5VRUN S RUND 12 26
14 G SYS_PWROK PLT_RST# CKE[3:0] CKE[3:0]
+3VRUN S NMOS N-AO4468 GPXIOA04
3 +5VRUN DDR3 3

Sandy Bridge SODIMM


+1_5VDIMM
15 27
VTT APL5930KAI-TRG GPIO54
DGPU_PWR_EN#
15 D 15a EN 29
+1_5VRUN S G +1_8VRUN_PWRGD PGOOD2 GPIO17
NMOS N-AO4468 DGPU_PWROK
30
KBC/EC PEG_A_CLKRQ#
PEG_CLKREQ#
15d +5VRUN
+1_5VRUN_PWGD Logic circuit 31
KB3930QFD2-RH CKOUT_PEG_A
CLK_PEGA_MXM
15 APL5930KAI-TRG
+5VRUN +1_5VDIMM +1_8VRUN 32
GPIO50
EN DGPU_HOLD_RST#
15b
VCNTL VIN 15d +1_8VRUN_PWRGD PGOOD2
+0_75VRUN
16
+1_5VRUN_PWGD
PCH
EN
APL5331KAC-TRL +5VSUS PWR_SRC AND GATE
25 33
NC7S08
PLT_RST# PEG_RST#
15
2 +VTT_CORE TPS51218DSCR 2
+5VSUS PWR_SRC
15c EN
+VTT_CORE_PWRGD PGOOD2
+3VRUN
16 15c
+0.85VRUN TPS51218DSCR
+VTT_CORE_PWRGD 27
16a EN 28 D DGPU_PWR_EN#
+0.85V_PWRGD PGOOD3 11a +3V_MXM S
17 18 NMOS N-NDS351ANG
+1_5VDIMM_PWRGD GPXIOD3 GPXIOA06
EC_ALLSYSPG delay 99ms EC_PCH_PWROK
15a
+5VRUN
+1_8VRUN_PWRGD
AND Circuit
15c
+VTT_CORE_PWRGD 28 D
+5V_MXM SPMOS G
16a P-IRLML6402PBF
+0.85V_PWRGD

PWR_SRC +3V_MXM +5V_MXM


+5VSUS PWR_SRC

31 29
PWRGOOD
1 23-a CLK_PEGA_MXM DGPU_PWROK 1
+VCC_CORE 19
17 30
VR_ON CLKIN_CPU PEX_CLK_REQ#
EC_ALLSYSPG 23-b 18 CLKIN_DMI PEG_CLKREQ#
+VCC_GFXCORE SL28770ELC 33
MAX17039GTN EC_PCH_PWROK CLKIN_GND1
22 CLKIN_DOT PEG_RST#
24

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SVID
PGOOD SYS_PWROK CLKIN_SATA Thames GPU MICRO-STAR INT'L CO.,LTD.
T itle

Power dellivery chart


Size Docum ent Num ber Rev
C 0B
MS-14851
Date: Friday, Decem ber 02, 2011 Sheet 4 of 53
A B C D E
A B C D E

IVY BRIDGE PROCESSOR (HOST) IVY BRIDGE PROCESSOR (CLK,MISC,JTAG)


U21A
J22 PEG_COMP R74 24.9R1%0402 +VTT
PEG_ICOMPI J21
B27 PEG_ICOMPO H22
25 DMI_TXN0 DMI_RX#[0] PEG_RCOMPO
B25
25 DMI_TXN1 DMI_RX#[1]
25 DMI_TXN2 A25 PEG_RXN[15:0] 13
B24 DMI_RX#[2] K33 PEG_RXN0
25 DMI_TXN3 DMI_RX#[3] PEG_RX#[0] M35 PEG_RXN1
PEG_RX#[1]
B28 L34 PEG_RXN2 U21B
25 DMI_TXP0 DMI_RX[0] PEG_RX#[2] PEG_RXN3
B26 J35
25 DMI_TXP1 DMI_RX[1] PEG_RX#[3]
4 A24 J32 PEG_RXN4 4
25 DMI_TXP2 DMI_RX[2] PEG_RX#[4]
B23 H34 PEG_RXN5

DMI
25 DMI_TXP3 DMI_RX[3] PEG_RX#[5] PEG_RXN6
H31 A28

MISC

CLOCKS
PEG_RX#[6] BCLK CLK_EXP 24
G21 G33 PEG_RXN7 C26 A27
25 DMI_RXN0 DMI_TX#[0] PEG_RX#[7] 28 H_SNB_IVB# PROC_SELECT# BCLK# CLK_EXP# 24
E22 G30 PEG_RXN8
25 DMI_RXN1 DMI_TX#[1] PEG_RX#[8]
F21 F35 PEG_RXN9
25 DMI_RXN2 DMI_TX#[2] PEG_RX#[9] PEG_RXN10 SKTOCC#
D21 E34 TPJNC39 AN34
25 DMI_RXN3 DMI_TX#[3] PEG_RX#[10] SKTOCC# 1KR1%0402
E32 PEG_RXN11 A16 R187
PEG_RX#[11] DPLL_REF_CLK 1KR1%0402
G22 D33 PEG_RXN12 A15 R186 +VTT
25 DMI_RXP0 DMI_TX[0] PEG_RX#[12] PEG_RXN13 DPLL_REF_CLK#
25 DMI_RXP1 D22 D31
F20 DMI_TX[1] PEG_RX#[13] B33 PEG_RXN14
25 DMI_RXP2 DMI_TX[2] PEG_RX#[14]
C21 C32 PEG_RXN15 TPJNC34 H_CATERR# AL33
25 DMI_RXP3 DMI_TX[3] PEG_RX#[15] CATERR#

PCI EXPRESS* - GRAPHICS


PEG_RXP0 PEG_RXP[15:0] 13 +VTT
J33

THERMAL
PEG_RX[0] PEG_RXP1
L35
PEG_RX[1] K34 PEG_RXP2 AN33 R8 CPUDRAMRST#
PEG_RX[2] PEG_RXP3 28,33 H_PECI PECI SM_DRAMRST#
A21 H35 R99
25 FDI_TXN0 FDI0_TX#[0] PEG_RX[3]

DDR3
MISC
H19 H32 PEG_RXP4 68R0402
25 FDI_TXN1 FDI0_TX#[1] PEG_RX[4] R284
E19 G34 PEG_RXP5
25 FDI_TXN2 FDI0_TX#[2] PEG_RX[5]
F18 G31 PEG_RXP6 R310 X_0R0402 PROCHOT#_R H_PROCHOT# AL32 AK1 SM_RCOMP0JNC R52 140R1%0402
25 FDI_TXN3 FDI0_TX#[3] PEG_RX[6] 33 EC_PROCHOT# PROCHOT# SM_RCOMP[0]
B21 F33 PEG_RXP7 A5 SM_RCOMP1JNC R181 25.5R1%0402

Intel(R) FDI
25 FDI_TXN4 FDI1_TX#[0] PEG_RX[7] PEG_RXP8 SM_RCOMP[1] SM_RCOMP2JNC R180 200R1%0402
25 FDI_TXN5 C20 F30 A4
D18 FDI1_TX#[1] PEG_RX[8] E35 PEG_RXP9 0R0402 SM_RCOMP[2]
25 FDI_TXN6 FDI1_TX#[2] PEG_RX[9] PEG_RXP10
If use EC_PROCHOT# , R310 need staff, R99 need
E17 E33 AN32
25 FDI_TXN7 FDI1_TX#[3] PEG_RX[10] PEG_RXP11 change to 62ohm, R284 need change to 56ohm; 28 H_THRMTRIP# THERMTRIP#
F32
PEG_RX[11] D34 PEG_RXP12
PEG_RX[12] PEG_RXP13
A22 E31
25 FDI_TXP0 FDI0_TX[0] PEG_RX[13] PEG_RXP14
G19 C33
25 FDI_TXP1 FDI0_TX[1] PEG_RX[14]
E20 B32 PEG_RXP15 AP29
25 FDI_TXP2 FDI0_TX[2] PEG_RX[15] PRDY#
G18 AP27 XDP_PREQ#
25 FDI_TXP3 FDI0_TX[3] PEG_TXN0 PEG_TXN[15:0] 13 PREQ#
B20 M29 [Fuqun] Not need pull high follow DPDG
25 FDI_TXP4 FDI1_TX[0] PEG_TX#[0] PEG_TXN1 XDP_TCLK
C19 M32 AR26

PWR MANAGEMENT
25 FDI_TXP5 FDI1_TX[1] PEG_TX#[1] TCK

JTAG & BPM


D19 M31 PEG_TXN2 AR27 XDP_TMS
25 FDI_TXP6 FDI1_TX[2] PEG_TX#[2] TMS
F17 L32 PEG_TXN3 AM34 AP30 XDP_TRST# +VTT
25 FDI_TXP7 FDI1_TX[3] PEG_TX#[3] 25 H_PM_SYNC PM_SYNC TRST#
L29 PEG_TXN4 RN12
J18 PEG_TX#[4] K31 PEG_TXN5 AR28 XDP_TDI XDP_TDI
25 FDI_FSYNC0 1 2
J17 FDI0_FSYNC PEG_TX#[5] K28 PEG_TXN6 TDI AP26 XDP_TDO XDP_TMS 3 4
25 FDI_FSYNC1 FDI1_FSYNC PEG_TX#[6] PEG_TXN7 TDO XDP_PREQ#
J30 AP33 5 6
PEG_TX#[7] PEG_TXN8 28 H_CPUPWRGD UNCOREPWRGOOD XDP_TCLK
25 FDI_INT H20 J28 7 8
FDI_INT PEG_TX#[8] H29 PEG_TXN9 R225 10KR0402
PEG_TX#[9] PLT_RST#_R set 1v level: R334 1.5K , R3370 649R:
3 J19 G27 PEG_TXN10 AL35 XDP_DBRESET# X_8P4R-51R/4 3
25 FDI_LSYNC0 FDI0_LSYNC PEG_TX#[10] PLT_RST#_R set 1.05v level: R334 1.47K , R3370 681R: DBR#
H17 E29 PEG_TXN11 VDDPWRGOOD_R V8
25 FDI_LSYNC1 FDI1_LSYNC PEG_TX#[11] PEG_TXN12 SM_DRAMPWROK
F27
PEG_TX#[12] D28 PEG_TXN13 AT28
PEG_TX#[13] BPM#[0]
PEG_TXN14
PEG_TX#[14]
F26
E25 PEG_TXN15 1.045V BPM#[1]
AR29
AR30 XDP_TRST# R215 X_51R1%0402
R190 24.9R1%0402 EDP_COMPIO A18 PEG_TX#[15] R124 1.47KR1%0402 PLT_RST#_R AR33 BPM#[2] AT30
+VTT eDP_COMPIO PEG_TXP[15:0] 13 27 BUF_PTL_RST# RESET# BPM#[3]
A17 M28 PEG_TXP0 AP32
eDP_ICOMPO PEG_TX[0] BPM#[4]
TP4 B16 M33 PEG_TXP1 AR31
*eDP_HPD# PEG_TX[1] PEG_TXP2 BPM#[5]
M30 R128 AT31
PEG_TX[2] L31 PEG_TXP3 681R1%0402 BPM#[6] AR32
PEG_TX[3] BPM#[7]
C15 L28 PEG_TXP4 +3VRUN
eDP_AUX PEG_TX[4] PEG_TXP5
D15 K30
eDP_AUX# PEG_TX[5] K27 PEG_TXP6
PEG_TX[6]
J29 PEG_TXP7
eDP

PEG_TX[7] PEG_TXP8 XDP_DBRESET# 1KR1%0402


C17 J27 R236
eDP_TX[0] PEG_TX[8] PEG_TXP9
F16 H28 [Fuqun] Follow MS-16F3 Ivy Bridge_rPGA_2DPC_Rev0p61
C16 eDP_TX[1] PEG_TX[9] G28 PEG_TXP10
eDP_TX[2] PEG_TX[10] +3VRUN
G15 E28 PEG_TXP11
eDP_TX[3] PEG_TX[11] F28 PEG_TXP12 +VTT
C18 PEG_TX[12] D27 PEG_TXP13
eDP_TX#[0] PEG_TX[13] +VTT
E16 E26 PEG_TXP14
eDP_TX#[1] PEG_TX[14] PEG_TXP15
D16 D25
eDP_TX#[2] PEG_TX[15]

X_C0.1u10X0402
F15 XDP_TDO R86 X_51R1%0402

C296
eDP_TX#[3]
R138
Ivy Bridge_rPGA_2DPC_Rev0p61 X_68R0402

5
VCC
1 R139
A Y
4
2
GND U10 X_40.2R1%0402
X_SN74LVC1G07

3
2 2

+1_5VDIMM

R35
200R1%0402 R38
+3VSUS +3VSUS

+1_5VDIMM +3VSUS

R37 +3VSUS 130R1%0402


C80 X_1.5KR5%0402 +1_5VDIMM
X_C0.1u10X0402
5

R34 R33 R53


1.5V
5

VCC
X_10KR0402 X_10KR0402 U5A 1
VCC 25 PM_DRAM_PWRGD 若Q10上件,R62上1K
4 Z0302 VDDPWRGOOD_R R49
Q6
3 A Y
4 2 B X_1KR0402
GND R39 X_1.5KR1%0402 X_N-BSS138_SOT23
C
Z0301 X_NC7WZ14P6X_SC70 R41 R48 D S CPUDRAMRST#
3

11,12 DDR3_DRAMRST#
E Q3 U6 X_1.27KR1%0402
2

X_N-SST3904_SOT23 X_S08P5X_SC70

G
R31 C79
R54 R56
8,24 DRAMRST_CNTRL_PCH
X_4.99KR1%0402
X_20KR1%0402

X_C1u6.3Y0402

C85
R36 X_0R0402 X_C0.047u10X0402

+1_5VRUN_PWGD 41

1 1

MICRO-STAR INT'L CO.,LTD.


Title

Ivy Bridge (HOST BUS & XDP)


Size Document Number Rev
Custom 0B
MS-14851
Date: Friday, December 02, 2011 Sheet 5 of 53
A B C D E

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A B C D E

IVY BRIDGE PROCESSOR (DDR3)


U21D
U21C

12 M_B_DQ[63:0] AE2
4 *SB_CK[0] M_B_CLK_DDR0 12 4
11 M_A_DQ[63:0] AB6 AD2
*SA_CK[0] M_A_CLK_DDR0 11 M_B_DQ0 SB_CLK#[0] M_B_CLK_DDR#0 12
AA6 C9 R9
M_A_DQ0 C5 SA_CLK#[0] V9 M_A_CLK_DDR#0 11 M_B_DQ1 A7 SB_DQ[0] SB_CKE[0] M_B_CKE0 12
M_A_DQ1 SA_DQ[0] SA_CKE[0] M_A_CKE0 11 M_B_DQ2 SB_DQ[1]
D5 D10
M_A_DQ2 SA_DQ[1] M_B_DQ3 SB_DQ[2]
D3 C8
M_A_DQ3 SA_DQ[2] M_B_DQ4 SB_DQ[3]
D2 A9 AE1
M_A_DQ4 SA_DQ[3] M_B_DQ5 SB_DQ[4] *SB_CK[1] M_B_CLK_DDR1 12
D6 AA5 A8 AD1
M_A_DQ5 SA_DQ[4] *SA_CK[1] M_A_CLK_DDR1 11 M_B_DQ6 SB_DQ[5] SB_CLK#[1] M_B_CLK_DDR#1 12
C6 AB5 D9 R10
M_A_DQ6 SA_DQ[5] SA_CLK#[1] M_A_CLK_DDR#1 11 M_B_DQ7 SB_DQ[6] SB_CKE[1] M_B_CKE1 12
C2 V10 D8
M_A_DQ7 SA_DQ[6] SA_CKE[1] M_A_CKE1 11 M_B_DQ8 SB_DQ[7]
C3 G4
M_A_DQ8 SA_DQ[7] M_B_DQ9 SB_DQ[8]
F10 F4
M_A_DQ9 SA_DQ[8] M_B_DQ10 SB_DQ[9]
F8 F1 AB2
M_A_DQ10 SA_DQ[9] M_B_DQ11 SB_DQ[10] *SB_CK[2]
G10 AB4 G1 AA2
M_A_DQ11 SA_DQ[10] *SA_CK[2] M_B_DQ12 SB_DQ[11] *SB_CLK#[2]
G9 AA4 G5 T9
M_A_DQ12 SA_DQ[11] *SA_CLK#[2] M_B_DQ13 SB_DQ[12] *SB_CKE[2]
F9 W9 F5
M_A_DQ13 SA_DQ[12] *SA_CKE[2] M_B_DQ14 SB_DQ[13]
F7 F2
M_A_DQ14 SA_DQ[13] M_B_DQ15 SB_DQ[14]
G8 G2
M_A_DQ15 SA_DQ[14] M_B_DQ16 SB_DQ[15]
G7 J7 AA1
M_A_DQ16 SA_DQ[15] M_B_DQ17 SB_DQ[16] *SB_CK[3]
K4 AB3 J8 AB1
M_A_DQ17 SA_DQ[16] *SA_CK[3] M_B_DQ18 SB_DQ[17] *SB_CLK#[3]
K5 AA3 K10 T10
M_A_DQ18 SA_DQ[17] *SA_CLK#[3] M_B_DQ19 SB_DQ[18] *SB_CKE[3]
K1 W10 K9
M_A_DQ19 SA_DQ[18] *SA_CKE[3] M_B_DQ20 SB_DQ[19]
J1 J9
M_A_DQ20 SA_DQ[19] M_B_DQ21 SB_DQ[20]
J5 J10
M_A_DQ21 SA_DQ[20] M_B_DQ22 SB_DQ[21]
J4 K8 AD3
M_A_DQ22 SA_DQ[21] M_B_DQ23 SB_DQ[22] SB_CS#[0] M_B_CS#0 12
J2 AK3 K7 AE3
M_A_DQ23 SA_DQ[22] SA_CS#[0] M_A_CS#0 11 M_B_DQ24 SB_DQ[23] SB_CS#[1] M_B_CS#1 12
K2 AL3 M5 AD6
M_A_DQ24 SA_DQ[23] SA_CS#[1] M_A_CS#1 11 M_B_DQ25 SB_DQ[24] *SB_CS#[2]
3 M8 AG1 N4 AE6 3
M_A_DQ25 SA_DQ[24] *SA_CS#[2] M_B_DQ26 SB_DQ[25] *SB_CS#[3]
N10 AH1 N2
M_A_DQ26 SA_DQ[25] *SA_CS#[3] M_B_DQ27 SB_DQ[26]
N8 N1
M_A_DQ27 SA_DQ[26] M_B_DQ28 SB_DQ[27]
N7 M4
M_A_DQ28 SA_DQ[27] M_B_DQ29 SB_DQ[28]
M10 N5 AE4
M_A_DQ29 SA_DQ[28] M_B_DQ30 SB_DQ[29] SB_ODT[0] M_B_ODT0 12
M9 AH3 M2 AD4
M_A_DQ30 SA_DQ[29] SA_ODT[0] M_A_ODT0 11 M_B_DQ31 SB_DQ[30] SB_ODT[1] M_B_ODT1 12
N9 AG3 M1 AD5
M_A_DQ31 SA_DQ[30] SA_ODT[1] M_A_ODT1 11 M_B_DQ32 SB_DQ[31] *SB_ODT[2]
M7 AG2 AM5 AE5

DDR SYSTEM MEMORY B


M_A_DQ32 SA_DQ[31] *SA_ODT[2] M_B_DQ33 SB_DQ[32] *SB_ODT[3]
AG6 AH2 AM6
DDR SYSTEM MEMORY A

M_A_DQ33 SA_DQ[32] *SA_ODT[3] M_B_DQ34 SB_DQ[33]


AG5 AR3
M_A_DQ34 SA_DQ[33] M_B_DQ35 SB_DQ[34]
AK6 AP3
M_A_DQ35 SA_DQ[34] M_B_DQ36 SB_DQ[35]
AK5 AN3 M_B_DQS#[7:0] 12
M_A_DQ36 SA_DQ[35] M_B_DQ37 SB_DQ[36] M_B_DQS#0
AH5 M_A_DQS#[7:0] 11 AN2 D7
M_A_DQ37 SA_DQ[36] M_A_DQS#0 M_B_DQ38 SB_DQ[37] SB_DQS#[0] M_B_DQS#1
AH6 C4 AN1 F3
M_A_DQ38 SA_DQ[37] SA_DQS#[0] M_A_DQS#1 M_B_DQ39 SB_DQ[38] SB_DQS#[1] M_B_DQS#2
AJ5 G6 AP2 K6
M_A_DQ39 SA_DQ[38] SA_DQS#[1] M_A_DQS#2 M_B_DQ40 SB_DQ[39] SB_DQS#[2] M_B_DQS#3
AJ6 J3 AP5 N3
M_A_DQ40 AJ8 SA_DQ[39] SA_DQS#[2] M6 M_A_DQS#3 M_B_DQ41 AN9 SB_DQ[40] SB_DQS#[3] AN5 M_B_DQS#4
M_A_DQ41 SA_DQ[40] SA_DQS#[3] M_A_DQS#4 M_B_DQ42 SB_DQ[41] SB_DQS#[4] M_B_DQS#5
AK8 AL6 AT5 AP9
M_A_DQ42 AJ9 SA_DQ[41] SA_DQS#[4] AM8 M_A_DQS#5 M_B_DQ43 AT6 SB_DQ[42] SB_DQS#[5] AK12 M_B_DQS#6
M_A_DQ43 SA_DQ[42] SA_DQS#[5] M_A_DQS#6 M_B_DQ44 SB_DQ[43] SB_DQS#[6] M_B_DQS#7
AK9 AR12 AP6 AP15
M_A_DQ44 AH8 SA_DQ[43] SA_DQS#[6] AM15 M_A_DQS#7 M_B_DQ45 AN8 SB_DQ[44] SB_DQS#[7]
M_A_DQ45 SA_DQ[44] SA_DQS#[7] M_B_DQ46 SB_DQ[45]
AH9 AR6
M_A_DQ46 AL9 SA_DQ[45] M_B_DQ47 AR5 SB_DQ[46]
M_A_DQ47 SA_DQ[46] M_B_DQ48 SB_DQ[47]
AL8 AR9 M_B_DQS[7:0] 12
M_A_DQ48 SA_DQ[47] M_B_DQ49 SB_DQ[48] M_B_DQS0
AP11 M_A_DQS[7:0] 11 AJ11 C7
M_A_DQ49 SA_DQ[48] M_A_DQS0 M_B_DQ50 SB_DQ[49] SB_DQS[0] M_B_DQS1
AN11 D4 AT8 G3
M_A_DQ50 AL12 SA_DQ[49] SA_DQS[0] F6 M_A_DQS1 M_B_DQ51 AT9 SB_DQ[50] SB_DQS[1] J6 M_B_DQS2
2 SA_DQ[50] SA_DQS[1] SB_DQ[51] SB_DQS[2] 2
M_A_DQ51 AM12 K3 M_A_DQS2 M_B_DQ52 AH11 M3 M_B_DQS3
M_A_DQ52 SA_DQ[51] SA_DQS[2] M_A_DQS3 M_B_DQ53 SB_DQ[52] SB_DQS[3] M_B_DQS4
AM11 N6 AR8 AN6
M_A_DQ53 SA_DQ[52] SA_DQS[3] M_A_DQS4 M_B_DQ54 SB_DQ[53] SB_DQS[4] M_B_DQS5
AL11 AL5 AJ12 AP8
M_A_DQ54 SA_DQ[53] SA_DQS[4] M_A_DQS5 M_B_DQ55 SB_DQ[54] SB_DQS[5] M_B_DQS6
AP12 AM9 AH12 AK11
M_A_DQ55 SA_DQ[54] SA_DQS[5] M_A_DQS6 M_B_DQ56 SB_DQ[55] SB_DQS[6] M_B_DQS7
AN12 AR11 AT11 AP14
M_A_DQ56 SA_DQ[55] SA_DQS[6] M_A_DQS7 M_B_DQ57 SB_DQ[56] SB_DQS[7]
AJ14 AM14 AN14
M_A_DQ57 SA_DQ[56] SA_DQS[7] M_B_DQ58 SB_DQ[57]
AH14 AR14
M_A_DQ58 SA_DQ[57] M_B_DQ59 SB_DQ[58]
AL15 AT14
M_A_DQ59 SA_DQ[58] M_B_DQ60 SB_DQ[59]
AK15 AT12 M_B_A[15:0] 12
M_A_DQ60 SA_DQ[59] M_B_DQ61 SB_DQ[60] M_B_A0
AL14 M_A_A[15:0] 11 AN15 AA8
M_A_DQ61 SA_DQ[60] M_A_A0 M_B_DQ62 SB_DQ[61] SB_MA[0] M_B_A1
AK14 AD10 AR15 T7
M_A_DQ62 SA_DQ[61] SA_MA[0] M_A_A1 M_B_DQ63 SB_DQ[62] SB_MA[1] M_B_A2
AJ15 W1 AT15 R7
M_A_DQ63 SA_DQ[62] SA_MA[1] M_A_A2 SB_DQ[63] SB_MA[2] M_B_A3
AH15 W2 T6
SA_DQ[63] SA_MA[2] M_A_A3 SB_MA[3] M_B_A4
W7 T2
SA_MA[3] M_A_A4 SB_MA[4] M_B_A5
V3 T4
SA_MA[4] M_A_A5 SB_MA[5] M_B_A6
V2 T3
SA_MA[5] M_A_A6 SB_MA[6] M_B_A7
W3 AA9 R2
SA_MA[6] M_A_A7 12 M_B_BS0 SB_BS[0] SB_MA[7] M_B_A8
AE10 W6 AA7 T5
11 M_A_BS0 SA_BS[0] SA_MA[7] M_A_A8 12 M_B_BS1 SB_BS[1] SB_MA[8] M_B_A9
AF10 V1 R6 R3
11 M_A_BS1 SA_BS[1] SA_MA[8] M_A_A9 12 M_B_BS2 SB_BS[2] SB_MA[9] M_B_A10
V6 W5 AB7
11 M_A_BS2 SA_BS[2] SA_MA[9] M_A_A10 SB_MA[10] M_B_A11
AD8 R1
SA_MA[10] M_A_A11 SB_MA[11] M_B_A12
V4 T1
SA_MA[11] M_A_A12 SB_MA[12] M_B_A13
W4 AA10 AB10
SA_MA[12] M_A_A13 12 M_B_CAS# SB_CAS# SB_MA[13] M_B_A14
AE8 AF8 AB8 R5
11 M_A_CAS# SA_CAS# SA_MA[13] M_A_A14 12 M_B_RAS# SB_RAS# SB_MA[14] M_B_A15
AD9 V5 AB9 R4
11 M_A_RAS# SA_RAS# SA_MA[14] M_A_A15 12 M_B_WE# SB_WE# Ivy Bridge_rPGA_2DPC_Rev0p61SB_MA[15]
AF9 V7
1 11 M_A_WE# SA_WE# SA_MA[15] 1
Ivy Bridge_rPGA_2DPC_Rev0p61

MICRO-STAR INT'L CO.,LTD.


Title

Ivy Bridge (DDR3)


Size Docum ent Num ber Rev
Cus tom 0B
MS-14851
Date: Friday, Decem ber 02, 2011 Sheet 6 of 53
A B C D E

https://vinafix.com
A B C D E

IVY BRIDGE PROCESSOR (POWER)

[Fuqun] 0.3~1.52V
[Fuqun] 45W----94A
4
35W----52A U21F POWER 4

[Fuqun] 22u*16/10u*10
+VCC_CORE 1.05V
+VCC_CORE

+VT T
52 A
AG35
[Fuqun] 22u*12 8.5 A
AG34 VCC1 AH13
AG33 VCC2 VCCIO1 AH10
AG32 VCC3 VCCIO2 AG10
C116 C252 C415 C411 C412 C410 AG31 VCC4 VCCIO3 AC10 C399 C109 C192 C404 C110 C406 C405
AG30 VCC5 VCCIO4 Y10
VCC6 VCCIO5
C22u6.3X50805

C22u6.3X50805
AG29 U10
VCC7 VCCIO6
C22u6.3X50805

C22u6.3X50805

C22u6.3X50805

C22u6.3X50805

C22u6.3X50805

C22u6.3X50805

C22u6.3X50805

C22u6.3X50805
X_C22u6.3X50805

X_C22u6.3X50805

X_C22u6.3X50805
AG28 P10
AG27 VCC8 VCCIO7 L10
AG26 VCC9 VCCIO8 J14
AF35 VCC10 VCCIO9 J13
AF34 VCC11 VCCIO10 J12
AF33 VCC12 VCCIO11 J11
AF32 VCC13 VCCIO12 H14 +VT T
AF31 VCC14 VCCIO13 H12
AF30 VCC15 VCCIO14 H11
AF29 VCC16 VCCIO15 G14
+VCC_CORE AF28 VCC17 VCCIO16 G13
AF27 VCC18 VCCIO17 G12
VCC19 VCCIO18

PEG AND DDR


AF26 F14 C400 C401 C402 C403 C108
AD35 VCC20 VCCIO19 F13
AD34 VCC21 VCCIO20 F12
VCC22 VCCIO21

C22u6.3X50805

C22u6.3X50805

X_C22u6.3X0805

X_C22u6.3X0805

X_C22u6.3X50805
AD33 F11
C117 C118 C414 C211 C413 C119 AD32 VCC23 VCCIO22 E14
AD31 VCC24 VCCIO23 E12
AD30 VCC25 VCCIO24
VCC26
C22u6.3X0805

C22u6.3X0805
C10u6.3X50805

C10u6.3X50805

C10u6.3X50805

C10u6.3X50805

AD29 E11
AD28 VCC27 VCCIO25 D14
3 VCC28 VCCIO26 3
AD27 D13
AD26 VCC29 VCCIO27 D12
AC35 VCC30 VCCIO28 D11
AC34 VCC31 VCCIO29 C14
AC33 VCC32 VCCIO30 C13
AC32 VCC33 VCCIO31 C12
AC31 VCC34 VCCIO32 C11
AC30 VCC35 VCCIO33 B14
AC29 VCC36 VCCIO34 B12
AC28 VCC37 VCCIO35 A14
AC27 VCC38 VCCIO36 A13
AC26 VCC39 VCCIO37 A12 +VT T
AA35 VCC40 VCCIO38 A11
AA34 VCC41 VCCIO39
AA33 VCC42 J23 JNC13 1 2 X_0402
AA32 VCC43 VCCIO40
AA31 VCC44
AA30 VCC45
AA29 VCC46
AA28 VCC47
AA27 VCC48
AA26 VCC49
Y35 VCC50
VCC51

CORE SUPPLY
Y34
Y33 VCC52 +VT T
Y32 VCC53
Y31 VCC54
Y30 VCC55
Y29 VCC56
Y28 VCC57 R91
Y27 VCC58
75R1%0402
Y26 VCC59
V35 VCC60
V34 VCC61 AJ29 R93 43R5%0402

SVID
VCC62 VIDALERT# VR_SVID_ALERT # 44
2 V33 AJ30 2
VCC63 VIDSCLK VR_SVID_CLK 44
V32 AJ28
V31 VCC64 VIDSOUT
V30 VCC65
V29 VCC66 +VT T
V28 VCC67
V27 VCC68
V26 VCC69
U35 VCC70
U34 VCC71 R90
U33 VCC72
130R1%0402
U32 VCC73
U31 VCC74
U30 VCC75
VCC76 VR_SVID_DAT A 44
U29 Ivy Bridge_rPGA_2DPC_Rev0p61
U28 VCC77
U27 VCC78 Close to CPU
U26 VCC79
R35 VCC80
R34 VCC81 +VCC_CORE
R33 VCC82
R32 VCC83
R31 VCC84
R30 VCC85 R115
R29 VCC86 100R1%0402
R28 VCC87
VCC88
SENSE LINES

R27 AJ35
VCC89 VCC_SENSE VCCSENSE 44
R26 AJ34
VCC90 VSS_SENSE VSSSENSE 44
P35
P34 VCC91
P33 VCC92 R112
P32 VCC93 B10 100R1%0402
VCC94 VCCIO_SENSE VT T _SENSE 42
P31 A10 T P_VSS_SENSE_VT T JNC
P30 VCC95 *VSS_SENSE_VCCIO T P2
P29 VCC96
VCC97
near processor
1 P28 1
P27 VCC98
P26 VCC99
VCC100

MICRO-STAR INT'L CO.,LTD.


T itle

Ivy Bridge (POWER)


Size Docum ent Num ber Rev
Custom 0B
MS-14851
Date: Friday, Decem ber 02, 2011 Sheet 7 of 53

https://vinafix.com
A B C D E
A B C D E

IVY BRIDGE PROCESSOR (GRAPHICS POWER) PPDG Recommend 100R R178 X_0R0402

Q4
1 [Fuqun] 22u*12 [Fuqun] 0V~1.52V 1
+VCC_GFXCORE X_N-BSS138_SOT23
[Fuqun] 45W----46A SA_DIMM_VREFDQ D S
+VCC_GFXCORE
35W----33A POWER M_VREF_DQ_DIMMA 11

G
U21G R218
100R1%0402 R51
46 A 5,24 DRAMRST_CNTRL_PCH
AT24 AK35
VAXG1 VAXG_SENSE VAXG_SENSE 44 C84
AT23 AK34 Change net name after check with power.
VAXG2 VSSAXG_SENSE VSSAXG_SENSE 44

SENSE
LINES
AT21 X_C0.047u10X0402
AT20 VAXG3 ----Dragon 07/27
C101 C103 C102 AT18 VAXG4 R222 +1_5VDIMM
X_C22u6.3X50805-RH X_C22u6.3X50805-RH X_C22u6.3X50805-RH VAXG5 100R1%0402
AT17
AR24 VAXG6
VAXG7 R47 X_0R0402
AR23
AR21 VAXG8 R43
AR20 VAXG9
VAXG10 1KR0402 Q5
AR18
AR17 VAXG11 X_N-BSS138_SOT23
VAXG12

VREF
AP24 AL1 SM_VREF SB_DIMM_VREFDQ D S
VAXG13 SM_VREF M_VREF_DQ_DIMMB 12
AP23
C106 C112 C123 AP21 VAXG14

G
X_C22u6.3X50805 X_C22u6.3X50805-RH C22u6.3X50805-RH VAXG15 SA_DIMM_VREFDQ
AP20 B4
AP18 VAXG16 SA_DIMM_VREFDQ D1 SB_DIMM_VREFDQ C82 R44 R50
VAXG17 SB_DIMM_VREFDQ 5,24 DRAMRST_CNTRL_PCH
AP17 1KR0402
AN24 VAXG18
VAXG19

C0.1u10X0402
AN23 R179 R42 C83
VAXG20 X_1KR0402 X_1KR0402 X_C0.047u10X0402
2 AN21 2
AN20 VAXG21
VAXG22
AN18
AN17 VAXG23
VAXG24

DDR3 -1.5V RAILS


AM24 AF7
C408 C124 C114 VAXG25 VDDQ1
AM23 AF4
VAXG26 VDDQ2

GRAPHICS
C22u6.3X50805-RH X_C22u6.3X50805-RH C22u6.3X50805-RH AM21 AF1 +1_5VDIMM
AM20
VAXG27
VAXG28
VDDQ3
VDDQ4
AC7 5 A
AM18 AC4
AM17 VAXG29 VDDQ5 AC1
VAXG30 VDDQ6
AL24 Y7 [Fuqun] 10u*6

1
AL23 VAXG31 VDDQ7 Y4

+
VAXG32 VDDQ8 C98 C86 C87 C95 C99 C100 C81
AL21 Y1
AL20 VAXG33 VDDQ9 U7 X_C330u2.5V

2
AL18 VAXG34 VDDQ10 U4
VAXG35 VDDQ11

C10u6.3X50805

X_C10u6.3X50805

X_C10u6.3X50805

C10u6.3X50805

X_C10u6.3X50805
C0.1u16Y0402
C115 C407 C113 AL17 U1
C22u6.3X50805-RH C22u6.3X50805-RH C22u6.3X50805-RH AK24 VAXG36 VDDQ12 P7
VAXG37 VDDQ13
AK23 P4
AK21 VAXG38 VDDQ14 P1
AK20 VAXG39 VDDQ15
VAXG40
AK18
AK17 VAXG41
VAXG42 [Fuqun] 0.675V~0.9V
AJ24
AJ23 VAXG43 +0_85VRUN
AJ21 VAXG44
VAXG45
6 A
AJ20
AJ18 VAXG46 Ivy Bridge_rPGA_2DPC_Rev0p61
VAXG47
3
AJ17 [Fuqun] 10u*3 3
AH24 VAXG48
AH23 VAXG49 C416 C122 C120
VAXG50
AH21 M27
SA RAIL

AH20 VAXG51 VCCSA1 M26


VAXG52 VCCSA2

C10u6.3X50805

C10u6.3X50805

X_C10u6.3X50805
AH18 L26
AH17 VAXG53 VCCSA3 J26
VAXG54 VCCSA4 J25
VCCSA5
J24
VCCSA6 H26
VCCSA7
H25
VCCSA8
[Fuqun] 10u*1/1u*2
+1_8VRUN
1.8V RAIL

1.2 A
B6 H23
VCCPLL1 VCCSA_SENSE VCCUSA_SENSE 43
A6 [Fuqun] Add VCCSA_SEL0
VCCPLL2
A2
VCCPLL3
MISC

C387 C391 C388


X_C22u6.3X50805-RH C1u6.3Y0402-RH X_C1u6.3Y0402-RH C22
*VCCSA_VID[0] VCCSA_SEL0 43
C24 Change net name after check with power.
*VCCSA_VID[1] VCCSA_SEL1 43
A19 TPJNC10 ----Dragon 07/27
VCCIO_SEL
The 2012 processor has internally hard-wired the
VCCIO_SEL pin low, so removal of this series resistor
will restore the signal to the “1” level for a 1.05-V selection.
4 4

MICRO-STAR INT'L CO.,LTD.


Title

Ivy Bridge (GRAPHICS POWER)


Size Docum ent Num ber Rev
Cus tom 0B
MS-14851
Date: Friday, Decem ber 02, 2011 Sheet 8 of 53
A B C D E

https://vinafix.com
A B C D E

IVY BRIDGE PROCESSOR (GND)


U21H

AT35 AJ22 U21I


VSS1 VSS81
AT32 AJ19
VSS2 VSS82
AT29 AJ16
VSS3 VSS83
AT27 AJ13
4 VSS4 VSS84 4
AT25 AJ10 T35 F22
VSS5 VSS85 VSS161 VSS234
AT22 AJ7 T34 F19
VSS6 VSS86 VSS162 VSS235
AT19 AJ4 T33 E30
AT16 VSS7 VSS87 AJ3 T32 VSS163 VSS236 E27
VSS8 VSS88 VSS164 VSS237
AT13 AJ2 T31 E24
VSS9 VSS89 VSS165 VSS238
AT10 AJ1 T30 E21
VSS10 VSS90 VSS166 VSS239
AT7 AH35 T29 E18
VSS11 VSS91 VSS167 VSS240
AT4 AH34 T28 E15
VSS12 VSS92 VSS168 VSS241
AT3 AH32 T27 E13
VSS13 VSS93 VSS169 VSS242
AR25 AH30 T26 E10
VSS14 VSS94 VSS170 VSS243
AR22 AH29 P9 E9
VSS15 VSS95 VSS171 VSS244
AR19 AH28 P8 E8
VSS16 VSS96 VSS172 VSS245
AR16 P6 E7
AR13 VSS17 AH25 P5 VSS173 VSS246 E6
VSS18 VSS98 VSS174 VSS247
AR10 AH22 P3 E5
VSS19 VSS99 VSS175 VSS248
AR7 AH19 P2 E4
VSS20 VSS100 VSS176 VSS249
AR4 AH16 N35 E3
VSS21 VSS101 VSS177 VSS250
AR2 AH7 N34 E2
VSS22 VSS102 VSS178 VSS251
AP34 AH4 N33 E1
VSS23 VSS103 VSS179 VSS252
AP31 AG9 N32 D35
VSS24 VSS104 VSS180 VSS253
AP28 AG8 N31 D32
VSS25 VSS105 VSS181 VSS254
AP25 AG4 N30 D29
VSS26 VSS106 VSS182 VSS255
AP22 AF6 N29 D26
VSS27 VSS107 VSS183 VSS256
3 AP19 AF5 N28 D20 3
VSS28 VSS108 VSS184 VSS257
AP16 AF3 N27 D17
VSS29 VSS109 VSS185 VSS258
AP13 AF2 N26 C34
AP10 VSS30 VSS110 AE35 M34 VSS186 VSS259 C31
VSS31 VSS111 VSS187 VSS260
AP7 AE34 L33 C28
VSS32 VSS112 VSS188 VSS261
AP4 AE33 L30 C27
VSS33 VSS113 VSS189 VSS262
AP1 AE32 L27 C25
VSS34 VSS114 VSS190 VSS263
AN30 AE31 L9 C23
VSS35 VSS115 VSS191 VSS264
AN27 AE30 L8 C10
VSS36 VSS116 VSS192 VSS265
AN25 AE29 L6 C1
AN22
AN19
VSS37
VSS38 VSS VSS117
VSS118
AE28
AE27
L5
L4
VSS193
VSS194
VSS266
VSS267
B22
B19
AN16
AN13
VSS39
VSS40
VSS41
VSS119
VSS120
VSS121
AE26
AE9
L3
L2
VSS195
VSS196
VSS197
VSS VSS268
VSS269
VSS270
B17
B15
AN10 AD7 L1 B13
VSS42 VSS122 VSS198 VSS271
AN7 AC9 K35 B11
AN4 VSS43 VSS123 AC8 K32 VSS199 VSS272 B9
VSS44 VSS124 VSS200 VSS273
AM29 AC6 K29 B8
VSS45 VSS125 VSS201 VSS274
AM25 AC5 K26 B7
VSS46 VSS126 VSS202 VSS275
AM22 AC3 J34 B5
VSS47 Ivy Bridge_rPGA_2DPC_Rev0p61 VSS127 VSS203 VSS276
AM19 AC2 J31 B3
VSS48 VSS128 VSS204 VSS277
AM16 AB35 H33 B2
VSS49 VSS129 VSS205 Ivy Bridge_rPGA_2DPC_Rev0p61 VSS278
AM13 AB34 H30 A35
VSS50 VSS130 VSS206 VSS279
AM10 AB33 H27 A32
VSS51 VSS131 VSS207 VSS280
2 AM7 AB32 H24 A29 2
VSS52 VSS132 VSS208 VSS281
AM4 AB31 H21 A26
VSS53 VSS133 VSS209 VSS282
AM3 AB30 H18 A23
VSS54 VSS134 VSS210 VSS283
AM2 AB29 H15 A20
VSS55 VSS135 VSS211 VSS284
AM1 AB28 H13 A3
VSS56 VSS136 VSS212 VSS285
AL34 AB27 H10
VSS57 VSS137 VSS213
AL31 AB26 H9
VSS58 VSS138 VSS214
AL28 Y9 H8
VSS59 VSS139 VSS215
AL25 Y8 H7
VSS60 VSS140 VSS216
AL22 Y6 H6
VSS61 VSS141 VSS217
AL19 Y5 H5
VSS62 VSS142 VSS218
AL16 Y3 H4
VSS63 VSS143 VSS219
AL13 Y2 H3
VSS64 VSS144 VSS220
AL10 W35 H2
VSS65 VSS145 VSS221
AL7 W34 H1
VSS66 VSS146 VSS222
AL4 W33 G35
AL2 VSS67 VSS147 W32 G32 VSS223
VSS68 VSS148 VSS224
AK33 W31 G29
VSS69 VSS149 VSS225
AK30 W30 G26
AK27 VSS70 VSS150 W29 G23 VSS226
VSS71 VSS151 VSS227
AK25 W28 G20
VSS72 VSS152 VSS228
AK22 W27 G17
AK19 VSS73 VSS153 W26 G11 VSS229
VSS74 VSS154 VSS230
AK16 U9 F34
1 VSS75 VSS155 VSS231 1
AK13 U8 F31
VSS76 VSS156 VSS232
AK10 U6 F29
AK7 VSS77 VSS157 U5 VSS233
VSS78 VSS158
AK4
AJ25
VSS79 VSS159
U3
U2
MICRO-STAR INT'L CO.,LTD.
VSS80 VSS160 Title

Ivy Bridge (GND)


Size Document Number Rev
Custom 0B
MS-14851

https://vinafix.com
Date: Friday, December 02, 2011 Sheet 9 of 53
A B C D E
A B C D E

IVY BRIDGE PROCESSOR (RESERVED)


U21E

AH27 TPJNC23
*VCC_DIE_SENSE TPJNC12
AH26
1 *VSS_DIE_SENSE 1
these PINs for debug purpose
AK28
1KR0402 CFG[0] TPJNC8
AK29 L7
R89 CFG2 CFG[1] RSVD28 TPJNC9
AL26 AG7
TPJNC15 CFG3 CFG[2] RSVD29 TPJNC7
AL27 AE7
TPJNC14 CFG4 CFG[3] RSVD30 TPJNC6
AK26 AK2
TPJNC27 CFG5 CFG[4] RSVD31
AL29 W8
TPJNC26 CFG6 CFG[5] RSVD32
AL30
CFG[6]
AM31
CFG[7]
AM32 AT26
CFG[8] RSVD33 CFG2 - PCI-Express Static Lane Reversal
AM30 AM33
CFG[9] RSVD34
AM28 AJ27
CFG[10] RSVD35 1 :Normal Operation
AM26
CFG[11] CFG2 0 :Lane Numbers Reversed
AN28
CFG[12]
AN31 T8 15 -> 0, 14 -> 1, ...
CFG[13] RSVD37
AN26 J16
CFG[14] RSVD38
AM27 H16
CFG[15] RSVD39 CFG4 - Display Port Presence
AK31 G16
CFG[16] RSVD40
AN29
CFG[17] 1:Disabled; No Physical Display Port
attached to Embedded Display Port
CFG4
AR35 0:Enabled; An external Display Port
TPJNC32 *RSVD_NCTF1
2 AJ31 AT34 device is connected to the Embedded 2
TPJNC31 VAXG_VAL_SENSE *RSVD_NCTF2
AH31 AT33 Display Port
TPJNC37 VSSAXG_VAL_SENSE *RSVD_NCTF3
AJ33 AP35
TPJNC36 VCC_VAL_SENSE *RSVD_NCTF4
AH33 AR34
VSS_VAL_SENSE *RSVD_NCTF5
PCI-Express Configuration Select
AJ26
RSVD5 CFG[5:6] 11:Default X16-device 1 functions 1 and 2 disabled
10: X8 X8-device 1 functions 1 enable, function2 disabled
RESERVED
B34
*RSVD_NCTF6 01:Reserved--(device 1 functions 1disabled function2 enable
A33
*RSVD_NCTF7
A34 00: X8 X4 X4-device 1 functions 1 and 2 enable
*RSVD_NCTF8
B35
*RSVD_NCTF9
C35
*RSVD_NCTF10
F25
RSVD8
F24
RSVD9
F23
RSVD10
D24 AJ32
RSVD11 RSVD51
G25 AK32
RSVD12 RSVD52
G24
RSVD13
E23
RSVD14 Ivy Bridge_rPGA_2DPC_Rev0p61
D23
RSVD15
C30
3 RSVD16 3
A31
RSVD17
B30
RSVD18
B29
RSVD19 TPJNC43
D30 AN35
RSVD20 *BCLK_ITP TPJNC42
B31 AM35
RSVD21 *BCLK_ITP#
A30
RSVD22
C29
RSVD23

J20
RSVD24
B18 AT2
RSVD25 *RSVD_NCTF11
AT1
*RSVD_NCTF12
*RSVD_NCTF13
AR1 Vinafix.com
J15

https://vinafix.com
RSVD27

B1 TPJNC5
KEY

4 4

MICRO-STAR INT'L CO.,LTD.


Title

Ivy Bridge (RESERVE)


Size Document Number Rev
Custom 0B
MS-14851
Date: Friday, December 02, 2011 Sheet 10 of 53
A B C D E
A B C D E

+1_5VDIMM

SOCKET3A SOCKET3B
6 M_A_A[15:0] M_A_DQ[63:0] 6
75 44
M_A_A0 M_A_DQ0 VDD VSS
98 5 76 48
M_A_A1 A0 DQ0 M_A_DQ1 VDD VSS
97 7 81 49
M_A_A2 A1 DQ1 M_A_DQ2 VDD VSS
96 15 82 54
M_A_A3 A2 DQ2 M_A_DQ3 VDD VSS
95 17 87 55
M_A_A4 A3 DQ3 M_A_DQ4 VDD VSS
92 4 88 60
M_A_A5 A4 DQ4 M_A_DQ5 VDD VSS
91 6 93 61
4
SODIMM #A0 M_A_A6
M_A_A7
M_A_A8
90
86
89
A5
A6
A7
DQ5
DQ6
DQ7
16
18
21
M_A_DQ6
M_A_DQ7
M_A_DQ8
8 M_VREF_DQ_DIMMA

+1_5VDIMM
94
99
100
VDD
VDD
VDD
VSS
VSS
VSS
65
66
71
4

M_A_A9 A8 DQ8 M_A_DQ9 VDD VSS


85 23 105 72
M_A_A10 107 A9 DQ9 33 M_A_DQ10 106 VDD VSS 127
M_A_A11 A10/AP DQ10 M_A_DQ11 VDD VSS
84 35 111 128
M_A_A12 A11 DQ11 M_A_DQ12 R27 VDD VSS
83 22 112 133
M_A_A13 119 A12/BC# DQ12 24 M_A_DQ13 1KR1%0402 117 VDD VSS 134
M_A_A14 A13 DQ13 M_A_DQ14 VDD VSS
80 34 118 138
M_A_A15 A14 DQ14 M_A_DQ15 M_VREF_DQ_DIMMA VDD VSS
78 36 123 139
A15 DQ15 M_A_DQ16 +3VRUN VDD VSS
39 124 144
DQ16 M_A_DQ17 VDD VSS
6 M_A_BS0
109 41 145
BA0 DQ17 M_A_DQ18 R28 VSS
6 M_A_BS1 108 51 199 150
BA1 DQ18 M_A_DQ19 1KR1%0402 VDDSPD VSS
6 M_A_BS2 79 53 151
BA2 DQ19 M_A_DQ20 C68 C70 VSS
6 M_A_CS#0 114 40 77 155
S0# DQ20 M_A_DQ21 X_C0.1u10X0402 X_C2.2u6.3X0603 122 NC1 VSS
6 M_A_CS#1
121 42 156
S1# DQ21 M_A_DQ22 NC2 VSS
6 M_A_CLK_DDR0 101 50 125 161
CK0 DQ22 M_A_DQ23 NCTEST VSS
6 M_A_CLK_DDR#0 103 52 162
CK0# DQ23 M_A_DQ24 TPJNC59 VSS
6 M_A_CLK_DDR1
102 57 198 167
CK1 DQ24 M_A_DQ25 EVENT# VSS
6 M_A_CLK_DDR#1 104 59 5,12 DDR3_DRAMRST# 30 168
CK1# DQ25 M_A_DQ26 RESET# VSS
6 M_A_CKE0 73 67 172
CKE0 DQ26 M_A_DQ27 VSS
6 M_A_CKE1
74 69 173
CKE1 DQ27 M_A_DQ28 M_VREF_DQ_DIMMA VSS
6 M_A_CAS# 115 56 1 178
CAS# DQ28 M_A_DQ29 +1_5VDIMM VREF_DQ VSS
6 M_A_RAS# 110 58 126 179
RAS# DQ29 M_A_DQ30 VREF_CA VSS
3 6 M_A_WE# 113 68 184 3
JNC10 1 2 X_0402 SA0_DIM0_0 197 WE# DQ30 70 M_A_DQ31 C65 C64 VSS 185
JNC9 1 SA0 DQ31 VSS
2 X_0402 SA1_DIM0_0 201 129 M_A_DQ32 C0.1u10X0402 X_C2.2u6.3X0603 2 189
202 SA1 DQ32 131 M_A_DQ33 R30 3 VSS VSS 190
12,24 SMB_CLK_DIMM SCL DQ33 VSS VSS
200 141 M_A_DQ34 1KR1%0402 8 195
12,24 SMB_DATA_DIMM SDA DQ34 VSS VSS
143 M_A_DQ35 9 196
116 DQ35 130 M_A_DQ36 M_VREF_CA_DIMMA_0 13 VSS VSS
6 M_A_ODT0 ODT0 DQ36 VSS
120 132 M_A_DQ37 14
6 M_A_ODT1 ODT1 DQ37 VSS
140 M_A_DQ38 19 MEC1
DQ38 M_A_DQ39 R29 C72 C75 VSS MEC1 +0_75VRUN
11 142 20
DM0 DQ39 M_A_DQ40 1KR1%0402 C0.1u10X0402 X_C2.2u6.3X0603 VSS
28 147 25 MEC2
DM1 DQ40 M_A_DQ41 VSS MEC2
46 149 26 203
DM2 DQ41 M_A_DQ42 VSS VTT
63 157 31 204
DM3 DQ42 M_A_DQ43 VSS VTT
136 159 32
DM4 DQ43 M_A_DQ44 VSS C44 C73
153 146 37 205
DM5 DQ44 M_A_DQ45 VSS 205
170
DM6 DQ45
148 VERF should have 20mil trace width & 20mil spacing 38
VSS 206
206

X_C1u6.3Y0402-RH

C1u6.3Y0402-RH
187 158 M_A_DQ46 43
DM7 DQ46 M_A_DQ47 VSS
6 M_A_DQS[7:0]
160
M_A_DQS0 DQ47 M_A_DQ48 DDR3SODIMM-204PS_BLACK-RH
12 163
M_A_DQS1 DQS0 DQ48 M_A_DQ49 SODIMM_S204
29 165
M_A_DQS2 DQS1 DQ49 M_A_DQ50 N13-2040060-L41
47 175
M_A_DQS3 64 DQS2 DQ50 177 M_A_DQ51
M_A_DQS4 DQS3 DQ51 M_A_DQ52
137 164
M_A_DQS5 DQS4 DQ52 M_A_DQ53
154 166
M_A_DQS6 171 DQS5 DQ53 174 M_A_DQ54
2 M_A_DQS7 DQS6 DQ54 M_A_DQ55 2
6 M_A_DQS#[7:0] 188 176
M_A_DQS#0 10 DQS7 DQ55 181 M_A_DQ56
M_A_DQS#1 DQS#0 DQ56 M_A_DQ57 +1_5VDIMM
27 183
M_A_DQS#2 DQS#1 DQ57 M_A_DQ58
45 191
M_A_DQS#3 62 DQS#2 DQ58 193 M_A_DQ59
M_A_DQS#4 DQS#3 DQ59 M_A_DQ60
135 180
M_A_DQS#5 DQS#4 DQ60 M_A_DQ61
152 182
M_A_DQS#6 DQS#5 DQ61 M_A_DQ62 C380 C45 C378 C379
169 192
M_A_DQS#7 DQS#6 DQ62 M_A_DQ63 C1u10X50402 X_C1u10X50402 C1u10X50402 C1u10X50402
186 194
DQS#7 DQ63

DDR3SODIMM-204PS_BLACK-RH
SODIMM_S204
N13-2040060-L41
+1_5VDIMM

1 +
C62 C74 C52 C51 C77 C76 C66 C71 C50
C10u6.3X5-RH X_C10u6.3X5-RH X_C10u6.3X5-RH C10u6.3X5-RH X_C10u6.3X5-RH X_C10u6.3X5-RH X_C10u6.3X5-RH X_C10u6.3X5-RH
2

X_C330u2.5pSO

1 1

MICRO-STAR INT'L CO.,LTD.


Title

DDR3 SODIMM A0
Size Document Number Rev
Custom 0B
MS-14851
Date: Friday, December 02, 2011 Sheet 11 of 53
A B C D E

https://vinafix.com
A B C D E

+1_5VDIMM

SOCKET2A SOCKET2B
6 M_B_A[15:0] M_B_DQ[63:0] 6
75 44
M_B_A0 M_B_DQ0 VDD VSS
98 5 76 48
M_B_A1 A0 DQ0 M_B_DQ1 VDD VSS
97 7 81 49
M_B_A2 A1 DQ1 M_B_DQ2 VDD VSS
96 15 82 54
M_B_A3 A2 DQ2 M_B_DQ3 VDD VSS
95 17 87 55
M_B_A4 A3 DQ3 M_B_DQ4 VDD VSS
92 4 88 60

1 SODIMM #B0 M_B_A5


M_B_A6
M_B_A7
91
90
86
A4
A5
A6
DQ4
DQ5
DQ6
6
16
18
M_B_DQ5
M_B_DQ6
M_B_DQ7
8 M_VREF_DQ_DIMMB
93
94
99
VDD
VDD
VDD
VSS
VSS
VSS
61
65
66
1

M_B_A8 A7 DQ7 M_B_DQ8 +1_5VDIMM VDD VSS


89 21 100 71
M_B_A9 A8 DQ8 M_B_DQ9 VDD VSS
85 23 105 72
M_B_A10 107 A9 DQ9 33 M_B_DQ10 106 VDD VSS 127
M_B_A11 A10/AP DQ10 M_B_DQ11 VDD VSS
84 35 111 128
M_B_A12 A11 DQ11 M_B_DQ12 R24 VDD VSS
83 22 112 133
M_B_A13 119 A12/BC# DQ12 24 M_B_DQ13 1KR1%0402 117 VDD VSS 134
M_B_A14 A13 DQ13 M_B_DQ14 VDD VSS
80 34 118 138
M_B_A15 A14 DQ14 M_B_DQ15 M_VREF_DQ_DIMMB VDD VSS
78 36 123 139
A15 DQ15 M_B_DQ16 +3VRUN VDD VSS
39 124 144
DQ16 M_B_DQ17 VDD VSS
6 M_B_BS0
109 41 145
BA0 DQ17 M_B_DQ18 R23 VSS
6 M_B_BS1 108 51 199 150
BA1 DQ18 M_B_DQ19 1KR1%0402 VDDSPD VSS
6 M_B_BS2 79 53 151
BA2 DQ19 M_B_DQ20 C46 C49 VSS
6 M_B_CS#0 114 40 77 155
S0# DQ20 M_B_DQ21 X_C0.1u10X0402 X_C2.2u6.3X0603 NC1 VSS
6 M_B_CS#1
121 42 122 156
S1# DQ21 M_B_DQ22 NC2 VSS
6 M_B_CLK_DDR0 101 50 125 161
CK0 DQ22 M_B_DQ23 NCTEST VSS
6 M_B_CLK_DDR#0 103 52 162
+3VRUN CK0# DQ23 M_B_DQ24 TPJNC58 VSS
6 M_B_CLK_DDR1
102 57 198 167
CK1 DQ24 M_B_DQ25 EVENT# VSS
6 M_B_CLK_DDR#1 104 59 5,11 DDR3_DRAMRST# 30 168
CK1# DQ25 M_B_DQ26 RESET# VSS
6 M_B_CKE0 73 67 172
CKE0 DQ26 M_B_DQ27 VSS
6 M_B_CKE1
74 69 173
R22 CKE1 DQ27 M_B_DQ28 M_VREF_DQ_DIMMB VSS
6 M_B_CAS# 115 56 1 178
10KR0402 CAS# DQ28 M_B_DQ29 +1_5VDIMM VREF_DQ VSS
6 M_B_RAS# 110 58 126 179
RAS# DQ29 M_B_DQ30 VREF_CA VSS
2 6 M_B_WE# 113 68 184 2
JNC8 1 2 X_0402 SA0_DIM1_0 197 WE# DQ30 70 M_B_DQ31 C43 C47 VSS 185
SA1_DIM1_0 SA0 DQ31 M_B_DQ32 C0.1u10X0402 X_C2.2u6.3X0603 VSS
201 129 2 189
202 SA1 DQ32 131 M_B_DQ33 R26 3 VSS VSS 190
11,24 SMB_CLK_DIMM SCL DQ33 VSS VSS
200 141 M_B_DQ34 1KR1%0402 8 195
11,24 SMB_DATA_DIMM SDA DQ34 VSS VSS
143 M_B_DQ35 9 196
116 DQ35 130 M_B_DQ36 M_VREF_CA_DIMMB_0 13 VSS VSS
6 M_B_ODT0 ODT0 DQ36 VSS
120 132 M_B_DQ37 14
6 M_B_ODT1 ODT1 DQ37 VSS
140 M_B_DQ38 19 MEC1
DQ38 M_B_DQ39 R25 C57 C54 VSS MEC1 +0_75VRUN
11 142 20
DM0 DQ39 M_B_DQ40 1KR1%0402 C0.1u10X0402 X_C2.2u6.3X0603 VSS
28 147 25 MEC2
DM1 DQ40 M_B_DQ41 VSS MEC2
46 149 26 203
DM2 DQ41 M_B_DQ42 VSS VTT
63 157 31 204
DM3 DQ42 M_B_DQ43 VSS VTT
136 159 32
DM4 DQ43 M_B_DQ44 VSS C63 C56
153 146 37 205
DM5 DQ44 M_B_DQ45 VSS 205
170
DM6 DQ45
148 VERF should have 20mil trace width & 20mil spacing 38
VSS 206
206

X_C1u6.3Y0402-RH

C1u6.3Y0402-RH
187 158 M_B_DQ46 43
DM7 DQ46 M_B_DQ47 VSS
6 M_B_DQS[7:0]
160
M_B_DQS0 DQ47 M_B_DQ48 DDR3SODIMM-204PS_BLACK-RH
12 163
M_B_DQS1 DQS0 DQ48 M_B_DQ49 SODIMM_S204_1
29 165
M_B_DQS2 DQS1 DQ49 M_B_DQ50 N13-2040080-L41
47 175
M_B_DQS3 64 DQS2 DQ50 177 M_B_DQ51
M_B_DQS4 DQS3 DQ51 M_B_DQ52
137 164
M_B_DQS5 DQS4 DQ52 M_B_DQ53
154 166
M_B_DQS6 171 DQS5 DQ53 174 M_B_DQ54
3 M_B_DQS7 DQS6 DQ54 M_B_DQ55 3
6 M_B_DQS#[7:0] 188 176
M_B_DQS#0 10 DQS7 DQ55 181 M_B_DQ56
M_B_DQS#1 DQS#0 DQ56 M_B_DQ57 +1_5VDIMM
27 183
M_B_DQS#2 DQS#1 DQ57 M_B_DQ58
45 191
M_B_DQS#3 62 DQS#2 DQ58 193 M_B_DQ59
M_B_DQS#4 DQS#3 DQ59 M_B_DQ60
135 180
M_B_DQS#5 DQS#4 DQ60 M_B_DQ61
152 182
M_B_DQS#6 DQS#5 DQ61 M_B_DQ62 C58 C67 C55 C39
169 192
M_B_DQS#7 DQS#6 DQ62 M_B_DQ63 C1u10X50402 X_C1u10X50402 X_C1u10X50402 C1u10X50402
186 194
DQS#7 DQ63

DDR3SODIMM-204PS_BLACK-RH
SODIMM_S204_1
N13-2040080-L41
+1_5VDIMM

1 +
C78 C69 C53 C38 C60 C59 C40 C61 C48
X_C10u6.3X50805 X_C10u6.3X50805 C10u6.3X50805 X_C10u6.3X5-RH C10u6.3X5-RH X_C10u6.3X5-RH X_C10u6.3X5-RH X_C10u6.3X5-RH
2

X_C330u2.5pSO

4 4

MICRO-STAR INT'L CO.,LTD.


Title

DDR3 SODIMM B0
Size Document Number Rev
Custom 0B
MS-14851
Date: Friday, December 02, 2011 Sheet 12 of 53
A B C D E

https://vinafix.com
A B C D E

U24A

PEG_RXN[15:0] 5

PEG_RXP[15:0] 5
PEG_TXP15 C0.22u16X0402 C125 GFX_RXP0 AA38 Y33 GFX_TX0P C134 C0.22u16X0402 PEG_RXP15
PCIE_RX0P PCIE_TX0P PEG_TXN[15:0] 5
PEG_TXN15 C0.22u16X0402 C127 GFX_RXN0 Y37 Y32 GFX_TX0N C130 C0.22u16X0402 PEG_RXN15
PCIE_RX0N PCIE_TX0N
PEG_TXP[15:0] 5
4 PEG_TXP14 C0.22u16X0402 C128 GFX_RXP1 Y35 W33 GFX_TX1P C151 C0.22u16X0402 PEG_RXP14 4
PEG_TXN14 C0.22u16X0402 C133 GFX_RXN1 PCIE_RX1P PCIE_TX1P GFX_TX1N C144 C0.22u16X0402 PEG_RXN14
W36 W32
PCIE_RX1N PCIE_TX1N

PEG_TXP13 C0.22u16X0402 C132 GFX_RXP2 W38 U33 GFX_TX2P C143 C0.22u16X0402 PEG_RXP13
PEG_TXN13 C0.22u16X0402 C139 GFX_RXN2 V37 PCIE_RX2P PCIE_TX2P GFX_TX2N C138 C0.22u16X0402 PEG_RXN13
U32
PCIE_RX2N PCIE_TX2N

PEG_TXP12 C0.22u16X0402 C141 GFX_RXP3 V35 U30 GFX_TX3P C157 C0.22u16X0402 PEG_RXP12
PEG_TXN12 C0.22u16X0402 C147 GFX_RXN3 PCIE_RX3P PCIE_TX3P GFX_TX3N C162 C0.22u16X0402 PEG_RXN12
U36 U29
PCIE_RX3N PCIE_TX3N

PEG_TXP11 C0.22u16X0402 C149 GFX_RXP4 U38 T33 GFX_TX4P C152 C0.22u16X0402 PEG_RXP11
PEG_TXN11 C0.22u16X0402 C156 GFX_RXN4 T37 PCIE_RX4P PCIE_TX4P T32 GFX_TX4N C155 C0.22u16X0402 PEG_RXN11
PCIE_RX4N PCIE_TX4N

PCI EXPRESS INTERFACE


PEG_TXP10 C0.22u16X0402 C159 GFX_RXP5 T35 T30 GFX_TX5P C172 C0.22u16X0402 PEG_RXP10
PEG_TXN10 C0.22u16X0402 C168 GFX_RXN5 R36 PCIE_RX5P PCIE_TX5P GFX_TX5N C182 C0.22u16X0402 PEG_RXN10
T29
PCIE_RX5N PCIE_TX5N

PEG_TXP9 C0.22u16X0402 C167 GFX_RXP6 R38 P33 GFX_TX6P C163 C0.22u16X0402 PEG_RXP9
PEG_TXN9 C0.22u16X0402 C178 GFX_RXN6 PCIE_RX6P PCIE_TX6P GFX_TX6N C171 C0.22u16X0402 PEG_RXN9
P37 P32
PCIE_RX6N PCIE_TX6N

PEG_TXP8 C0.22u16X0402 C179 GFX_RXP7 P35 P30 GFX_TX7P C185 C0.22u16X0402 PEG_RXP8
3
PEG_TXN8 C0.22u16X0402 C188 GFX_RXN7 N36 PCIE_RX7P PCIE_TX7P P29 GFX_TX7N C195 C0.22u16X0402 PEG_RXN8
3
PCIE_RX7N PCIE_TX7N

PEG_TXP7 C0.22u16X0402 C191 GFX_RXP8 N38 N33 GFX_TX8P C183 C0.22u16X0402 PEG_RXP7
PEG_TXN7 C0.22u16X0402 C201 GFX_RXN8 PCIE_RX8P PCIE_TX8P GFX_TX8N C184 C0.22u16X0402 PEG_RXN7
M37 N32
PCIE_RX8N PCIE_TX8N

PEG_TXP6 C0.22u16X0402 C199 GFX_RXP9 M35 N30 GFX_TX9P C203 C0.22u16X0402 PEG_RXP6
PEG_TXN6 C0.22u16X0402 C209 GFX_RXN9 L36 PCIE_RX9P PCIE_TX9P N29 GFX_TX9N C207 C0.22u16X0402 PEG_RXN6
PCIE_RX9N PCIE_TX9N

PEG_TXP5 C0.22u16X0402 C222 GFX_RXP10 L38 L33 GFX_TX10P C194 C0.22u16X0402 PEG_RXP5
PEG_TXN5 C0.22u16X0402 C236 GFX_RXN10 K37 PCIE_RX10P PCIE_TX10P L32 GFX_TX10N C202 C0.22u16X0402 PEG_RXN5
PCIE_RX10N PCIE_TX10N

PEG_TXP4 C0.22u16X0402 C212 GFX_RXP11 K35 L30 GFX_TX11P C219 C0.22u16X0402 PEG_RXP4
PEG_TXN4 C0.22u16X0402 C229 GFX_RXN11 PCIE_RX11P PCIE_TX11P GFX_TX11N C228 C0.22u16X0402 PEG_RXN4
J36 L29
PCIE_RX11N PCIE_TX11N

PEG_TXP3 C0.22u16X0402 C227 GFX_RXP12 J38 K33 GFX_TX12P C208 C0.22u16X0402 PEG_RXP3
PEG_TXN3 C0.22u16X0402 C242 GFX_RXN12 H37 PCIE_RX12P PCIE_TX12P K32 GFX_TX12N C218 C0.22u16X0402 PEG_RXN3
PCIE_RX12N PCIE_TX12N

PEG_TXP2 C0.22u16X0402 C244 GFX_RXP13 H35 J33 GFX_TX13P C238 C0.22u16X0402 PEG_RXP2
PEG_TXN2 C0.22u16X0402 C256 GFX_RXN13 PCIE_RX13P PCIE_TX13P GFX_TX13N C245 C0.22u16X0402 PEG_RXN2
2 G36 J32 2
PCIE_RX13N PCIE_TX13N

PEG_TXP1 C0.22u16X0402 C253 GFX_RXP14 G38 K30 GFX_TX14P C254 C0.22u16X0402 PEG_RXP1
PEG_TXN1 C0.22u16X0402 C266 GFX_RXN14 F37 PCIE_RX14P PCIE_TX14P GFX_TX14N C260 C0.22u16X0402 PEG_RXN1
K29
PCIE_RX14N PCIE_TX14N

PEG_TXP0 C0.22u16X0402 C288 GFX_RXP15 F35 H33 GFX_TX15P C230 C0.22u16X0402 PEG_RXP0
PEG_TXN0 C0.22u16X0402 C281 GFX_RXN15 E37 PCIE_RX15P PCIE_TX15P GFX_TX15N C237 C0.22u16X0402 PEG_RXN0
H32
PCIE_RX15N PCIE_TX15N

CLOCK
24 GFX_REFCLK AB35
AA36 PCIE_REFCLKP
24 GFX_REFCLK# PCIE_REFCLKN
R116 1.27KR1%0402
CALIBRATION
Y30 PCIE_VDDC
PCIE_CALRP
GFX_PWRGD AH16 Y29 R121 2KR1%0402
PWRGOOD PCIE_CALRN
R125
27 PEG_RST# AA30
10KR0402 PERSTB
1 1

THAMES M2 XT
MICRO-STAR INT'L CO.,LTD.
Title

Thames GPU(PCIE)
Vinafix.com
Size Document Number Rev
Custom 0B
MS-14851

https://vinafix.com
Date: Friday, December 02, 2011 Sheet 13 of 53
A B C D E
A B C D E

18 VMB_DQA[63:0]
17 VMA_DQA[63:0]
18 B_MA[13:0] 18 B_QSA[7:0]
17 A_MA[13:0] 17 A_QSA[7:0]
18 B_BA[2:0] 18 B_QSA#[7:0]
17 A_BA[2:0] 17 A_QSA#[7:0]
18 B_DQMA[7:0]
17 A_DQMA[7:0]

4 U24D 4
U24C DDR2 DDR2
DDR2 DDR2 GDDR3/GDDR5 GDDR5/GDDR3
GDDR3/GDDR5 GDDR5/GDDR3 DDR3 DDR3
DDR3 DDR3 VMB_DQA0 C5 P8 B_MA0
VMA_DQA0 C37 G24 A_MA0 VMB_DQA1 C3 DQB0_0/DQB_0 M AB0_0/M AB_0 T9 B_MA1
VMA_DQA1 C35 DQA0_0/DQA_0 M AA0_0/M AA_0 J23 A_MA1 VMB_DQA2 E3 DQB0_1/DQB_1 M AB0_1/M AB_1 P9 B_MA2
VMA_DQA2 A35 DQA0_1/DQA_1 M AA0_1/M AA_1 H24 A_MA2 VMB_DQA3 E1 DQB0_2/DQB_2 M AB0_2/M AB_2 N7 B_MA3
DQA0_2/DQA_2 M AA0_2/M AA_2 DQB0_3/DQB_3 M AB0_3/M AB_3
VMA_DQA3 E34 J24 A_MA3 VMB_DQA4 F1 N8 B_MA4
VMA_DQA4 G32 DQA0_3/DQA_3 M AA0_3/M AA_3 H26 A_MA4 VMB_DQA5 F3 DQB0_4/DQB_4 M AB0_4/M AB_4 N9 B_MA5
VMA_DQA5 D33 DQA0_4/DQA_4 M AA0_4/M AA_4 J26 A_MA5 VMB_DQA6 F5 DQB0_5/DQB_5 M AB0_5/M AB_5 U9 B_MA6
DQA0_5/DQA_5 M AA0_5/M AA_5 DQB0_6/DQB_6 M AB0_6/M AB_6

MEMORY INTERFACE B
VMA_DQA6 F32 H21 A_MA6 VMB_DQA7 G4 U8 B_MA7

MEMORY INTERFACE A
VMA_DQA7 E32 DQA0_6/DQA_6 M AA0_6/M AA_6 G21 A_MA7 VMB_DQA8 H5 DQB0_7/DQB_7 M AB0_7/M AB_7 Y9 B_MA8
VMA_DQA8 D31 DQA0_7/DQA_7 M AA0_7/M AA_7 H19 A_MA8 VMB_DQA9 H6 DQB0_8/DQB_8 M AB1_0/M AB_8 W9 B_MA9
VMA_DQA9 F30 DQA0_8/DQA_8 M AA1_0/M AA_8 H20 A_MA9 VMB_DQA10 J4 DQB0_9/DQB_9 M AB1_1/M AB_9 AC8 B_MA10
VMA_DQA10 C30 DQA0_9/DQA_9 M AA1_1/M AA_9 L13 A_MA10 VMB_DQA11 K6 DQB0_10/DQB_10 M AB1_2/M AB_10 AC9 B_MA11
VMA_DQA11 A30 DQA0_10/DQA_10 M AA1_2/M AA_10 G16 A_MA11 VMB_DQA12 K5 DQB0_11/DQB_11 M AB1_3/M AB_11 AA7 B_MA12
VMA_DQA12 F28 DQA0_11/DQA_11 M AA1_3/M AA_11 J16 A_MA12 VMB_DQA13 L4 DQB0_12/DQB_12 M AB1_4/M AB_12 AA8 B_BA2
DQA0_12/DQA_12 M AA1_4/M AA_12 DQB0_13/DQB_13 M AB1_5/BA2
VMA_DQA13 C28 H16 A_BA2 VMB_DQA14 M6 Y8 B_BA0
VMA_DQA14 A28 DQA0_13/DQA_13 M AA1_5/M AA_13_BA2 J17 A_BA0 VMB_DQA15 M1 DQB0_14/DQB_14 M AB1_6/BA0 AA9 B_BA1
VMA_DQA15 DQA0_14/DQA_14 M AA1_6/M AA_14_BA0 A_BA1 VMB_DQA16 DQB0_15/DQB_15 M AB1_7/BA1
E28 H17 M3
VMA_DQA16 D27 DQA0_15/DQA_15 M AA1_7/M AA_A15_BA1 VMB_DQA17 M5 DQB0_16/DQB_16 H3 B_DQMA0
VMA_DQA17 F26 DQA0_16/DQA_16 A32 A_DQMA0 VMB_DQA18 N4 DQB0_17/DQB_17 WCKB0_0/DQM B_0 H1 B_DQMA1
VMA_DQA18 C26 DQA0_17/DQA_17 WCKA0_0/DQM A_0 C32 A_DQMA1 VMB_DQA19 P6 DQB0_18/DQB_18 WCKB0B_0/DQM B_1 T3 B_DQMA2
VMA_DQA19 A26 DQA0_18/DQA_18 WCKA0B_0/DQM A_1 D23 A_DQMA2 VMB_DQA20 P5 DQB0_19/DQB_19 WCKB0_1/DQM B_2 T5 B_DQMA3
VMA_DQA20 F24 DQA0_19/DQA_19 WCKA0_1/DQM A_2 E22 A_DQMA3 VMB_DQA21 R4 DQB0_20/DQB_20 WCKB0B_1/DQM B_3 AE4 B_DQMA4
VMA_DQA21 C24 DQA0_20/DQA_20 WCKA0B_1/DQM A_3 C14 A_DQMA4 VMB_DQA22 T6 DQB0_21/DQB_21 WCKB1_0/DQM B_4 AF5 B_DQMA5
VMA_DQA22 DQA0_21/DQA_21 WCKA1_0/DQM A_4 A_DQMA5 VMB_DQA23 DQB0_22/DQB_22 WCKB1B_0/DQM B_5 B_DQMA6
A24 A14 T1 AK6
VMA_DQA23
DQA0_22/DQA_22 WCKA1B_0/DQM A_5 A_DQMA6 VMB_DQA24
DQB0_23/DQB_23 WCKB1_1/DQM B_6 B_DQMA7
E24 E10 U4 AK5
VMA_DQA24 DQA0_23/DQA_23 WCKA1_1/DQM A_6 A_DQMA7 VMB_DQA25 DQB0_24/DQB_24 WCKB1B_1/DQM B_7
C22 D9 V6
VMA_DQA25 A22 DQA0_24/DQA_24 WCKA1B_1/DQM A_7 VMB_DQA26 V1 DQB0_25/DQB_25 GDDR5/DDR2/GDDR3
F6 B_QSA0
VMA_DQA26 F22 DQA0_25/DQA_25 GDDR5/DDR2/GDDR3
C34 A_QSA0 VMB_DQA27 V3 DQB0_26/DQB_26 EDCB0_0/QSB_0/RDQSB_0 K3 B_QSA1
VMA_DQA27 D21 DQA0_26/DQA_26 EDCA0_0/QSA_0/RDQSA_0 D29 A_QSA1 VMB_DQA28 Y6 DQB0_27/DQB_27 EDCB0_1/QSB_1/RDQSB_1 P3 B_QSA2
3 DQA0_27/DQA_27 EDCA0_1/QSA_1/RDQSA_1 DQB0_28/DQB_28 EDCB0_2/QSB_2/RDQSB_2 3
VMA_DQA28 A20 D25 A_QSA2 VMB_DQA29 Y1 V5 B_QSA3
VMA_DQA29 F20 DQA0_28/DQA_28 EDCA0_2/QSA_2/RDQSA_2 E20 A_QSA3 VMB_DQA30 Y3 DQB0_29/DQB_29 EDCB0_3/QSB_3/RDQSB_3 AB5 B_QSA4
VMA_DQA30 D19 DQA0_29/DQA_29 EDCA0_3/QSA_3/RDQSA_3 E16 A_QSA4 VMB_DQA31 Y5 DQB0_30/DQB_30 EDCB1_0/QSB_4/RDQSB_4 AH1 B_QSA5
VMA_DQA31 DQA0_30/DQA_30 EDCA1_0/QSA_4/RDQSA_4 A_QSA5 VMB_DQA32 DQB0_31/DQB_31 EDCB1_1/QSB_5/RDQSB_5 B_QSA6
E18 E12 AA4 AJ9
VMA_DQA32 C18 DQA0_31/DQA_31 EDCA1_1/QSA_5/RDQSA_5 J10 A_QSA6 VMB_DQA33 AB6 DQB1_0/DQB_32 EDCB1_2/QSB_6/RDQSB_6 AM 5 B_QSA7
VMA_DQA33
DQA1_0/DQA_32 EDCA1_2/QSA_6/RDQSA_6 A_QSA7 VMB_DQA34
DQB1_1/DQB_33 EDCB1_3/QSB_7/RDQSB_7
A18 D7 AB1
VMA_DQA34 F18 DQA1_1/DQA_33 EDCA1_3/QSA_7/RDQSA_7 VMB_DQA35 AB3 DQB1_2/DQB_34 G7 B_QSA#0
VMA_DQA35 D17 DQA1_2/DQA_34 A34 A_QSA#0 VMB_DQA36 AD6 DQB1_3/DQB_35 DDBIB0_0/QSB_0B/WDQSB_0 K1 B_QSA#1
VMA_DQA36 A16 DQA1_3/DQA_35 DDBIA0_0/QSA_0B/WDQSA_0 E30 A_QSA#1 VMB_DQA37 AD1 DQB1_4/DQB_36 DDBIB0_1/QSB_1B/WDQSB_1 P1 B_QSA#2
VMA_DQA37 F16 DQA1_4/DQA_36 DDBIA0_1/QSA_1B/WDQSA_1 E26 A_QSA#2 VMB_DQA38 AD3 DQB1_5/DQB_37 DDBIB0_2/QSB_2B/WDQSB_2 W4 B_QSA#3
VMA_DQA38 D15 DQA1_5/DQA_37 DDBIA0_2/QSA_2B/WDQSA_2 C20 A_QSA#3 VMB_DQA39 AD5 DQB1_6/DQB_38 DDBIB0_3/QSB_3B/WDQSB_3 AC4 B_QSA#4
VMA_DQA39 E14 DQA1_6/DQA_38 DDBIA0_3/QSA_3B/WDQSA_3 C16 A_QSA#4 VMB_DQA40 AF1 DQB1_7/DQB_39 DDBIB1_0/QSB_4B/WDQSB_4 AH3 B_QSA#5
VMA_DQA40 DQA1_7/DQA_39 DDBIA1_0/QSA_4B/WDQSA_4 A_QSA#5 VMB_DQA41 DQB1_8/DQB_40 DDBIB1_1/QSB_5B/WDQSB_5 B_QSA#6
F14 C12 AF3 AJ8
VMA_DQA41 D13 DQA1_8/DQA_40 DDBIA1_1/QSA_5B/WDQSA_5 J11 A_QSA#6 VMB_DQA42 AF6 DQB1_9/DQB_41 DDBIB1_2/QSB_6B/WDQSB_6 AM 3 B_QSA#7
VMA_DQA42 F12 DQA1_9/DQA_41 DDBIA1_2/QSA_6B/WDQSA_6 F8 A_QSA#7 VMB_DQA43 AG4 DQB1_10/DQB_42 DDBIB1_3/QSB_7B/WDQSB_7
DQA1_10/DQA_42 DDBIA1_3/QSA_7B/WDQSA_7 DQB1_11/DQB_43
VMA_DQA43 A12 VMB_DQA44 AH5 T7
DQA1_11/DQA_43 DQB1_12/DQB_44 ADBIB0/ODT B0 ODTB0 18
VMA_DQA44 D11 J21 VMB_DQA45 AH6 W7
DQA1_12/DQA_44 ADBIA0/ODT A0 ODTA0 17 DQB1_13/DQB_45 ADBIB1/ODT B1 ODTB1 18
VMA_DQA45 F10 G19 VMB_DQA46 AJ4
DQA1_13/DQA_45 ADBIA1/ODT A1 ODTA1 17 DQB1_14/DQB_46
VMA_DQA46 A10 VMB_DQA47 AK3 L9
DQA1_14/DQA_46 DQB1_15/DQB_47 CLKB0 B0_CLK 18
VMA_DQA47 C10 H27 VMB_DQA48 AF8 L8
DQA1_15/DQA_47 CLKA0 A0_CLK 17 DQB1_16/DQB_48 CLKB0B B0_CLK# 18
VMA_DQA48 G13 G27 VMB_DQA49 AF9
VMA_DQA49 DQA1_16/DQA_48 CLKA0B A0_CLK# 17 VMB_DQA50 DQB1_17/DQB_49
H13 AG8 AD8
VMA_DQA50 J13 DQA1_17/DQA_49 J14 VMB_DQA51 AG7 DQB1_18/DQB_50 CLKB1 AD7 B1_CLK 18
VMA_DQA51 H11 DQA1_18/DQA_50 CLKA1 H14 A1_CLK 17 VMB_DQA52 AK9 DQB1_19/DQB_51 CLKB1B B1_CLK# 18
VMA_DQA52 DQA1_19/DQA_51 CLKA1B A1_CLK# 17 VMB_DQA53 DQB1_20/DQB_52
G10 AL7 T 10
VDDQ DQA1_20/DQA_52 DQB1_21/DQB_53 RASB0B B0_RAS# 18
VMA_DQA53 G8 K23 VMB_DQA54 AM 8 Y10
DQA1_21/DQA_53 RASA0B A0_RAS# 17 DQB1_22/DQB_54 RASB1B B1_RAS# 18
VMA_DQA54 K9 K19 VMB_DQA55 AM 7
DQA1_22/DQA_54 RASA1B A1_RAS# 17 DQB1_23/DQB_55
VMA_DQA55 K10 VMB_DQA56 AK1 W10
DQA1_23/DQA_55 VDDQ DQB1_24/DQB_56 CASB0B B0_CAS# 18
VMA_DQA56 G9 K20 VMB_DQA57 AL4 AA10
DQA1_24/DQA_56 CASA0B A0_CAS# 17 DQB1_25/DQB_57 CASB1B B1_CAS# 18
R146 VMA_DQA57 A8 K17 VMB_DQA58 AM 6
DQA1_25/DQA_57 CASA1B A1_CAS# 17 DQB1_26/DQB_58
40.2R_1% VMA_DQA58 C8 VMB_DQA59 AM 1 P10
VMA_DQA59 E8 DQA1_26/DQA_58 K24 VMB_DQA60 AN4 DQB1_27/DQB_59 CSB0B_0 L10 B0_CSB0# 18
2 VMA_DQA60 A6 DQA1_27/DQA_59 CSA0B_0 K27 A0_CSB0# 17 R137 VMB_DQA61 AP3 DQB1_28/DQB_60 CSB0B_1 2
VMA_DQA61 DQA1_28/DQA_60 CSA0B_1 40.2R_1% VMB_DQA62 DQB1_29/DQB_61
C6 AP1 AD10
VMA_DQA62 E6 DQA1_29/DQA_61 M 13 VMB_DQA63 AP5 DQB1_30/DQB_62 CSB1B_0 AC10 B1_CSB0# 18
VMA_DQA63
DQA1_30/DQA_62 CSA1B_0 A1_CSB0# 17 DQB1_31/DQB_63 CSB1B_1
A5 K16
R147 C297 DQA1_31/DQA_63 CSA1B_1 U10
VDDQ CKEB0 B0_CKE 18
100R1%0402 C1u6.3Y 0402-RH L18 K21 Y12 AA11
M VREFDA CKEA0 A0_CKE 17 M VREFDB CKEB1 B1_CKE 18
L20 J20 AA12
M VREFSA CKEA1 A1_CKE 17 M VREFSB
R141 C295 N10
WEB0B B0_WEB# 18
R132 240R1%0402 ATI_MEM_CALRN0 L27 K26 100R1%0402 C1u6.3Y 0402-RH AB11
R149 240R1%0402 ATI_MEM_CALRN1 N12 M EM _CALRN0 WEA0B L15 A0_WEB# 17 WEB1B B1_WEB# 18
VDDQ R131 240R1%0402 ATI_MEM_CALRN2 M EM _CALRN1 WEA1B A1_WEB# 17
AG12
M EM _CALRN2 R110 1KR1%0402 AD28 T8 B_MA13
R153 240R1%0402 ATI_MEM_CALRP1 M 12 H23 A_MA13 T EST EN M AB0_8 W8
M EM _CALRP1 M AA0_8 VDDQ M AB1_8 R143
R129 240R1%0402 ATI_MEM_CALRP0 M 27 J19 AK10
R148 R126 240R1%0402 ATI_MEM_CALRP2 AH12 M EM _CALRP0 M AA1_8 AL10 CLKT EST A AH11 R135 10R0402
M EM _CALRP2 CLKT EST B DRAM _RST GPU_MEM_RST# 17,18
X_40.2R_1%

GDDR5
51R1%0402
R133 R130 C301
GDDR5

X_40.2R_1% 4.99KR1%0402 C120p50N0402

R150 C263 C440 THAMES M2 XT


X_100R1%0402 C308 X_C0.1u16Y 0402 X_C0.1u16Y 0402
X_C1u6.3Y 0402-RH THAMES M2 XT
R134 route 50ohms single-ended/100ohms diff
X_100R1%0402 C287
X_C1u6.3Y 0402-RH and keep short.
R127 R231
X_51.1R0402 X_51.1R0402

1 1

MICRO-STAR INT'L CO.,LTD.


Title

Thames GPU(MEM)
Size Document Number Rev
Custom 0B
MS-14851
Date: Friday , December 02, 2011 Sheet 14 of 53
A B C D E

https://vinafix.com
A B C D E

U24B

+1_8VRUN_GPU
AU24
TXCAP_DPA3P
AV23
TXCAM_DPA3N
AT25 U24G
R239 R237 R238 R235 MUTI GFX TX0P_DPA2P AR24
DPA TX0M_DPA2N
X_10KR0402 X_10KR0402 X_10KR0402 X_10KR0402
AU26
VDDR3 TX1P_DPA1P
AV25 LVDS CONTROL AK27
4 TX1M_DPA1N VARY _BL AJ27 4
DIGON
AR8 AT27
AU8 DVPCNTL_MVP_0 TX2P_DPA0P AR26
DVPCNTL_MVP_1 TX2M_DPA0N
AP8
R118 3KR0402 GPU_GPIO0 AW8 DVPCNTL_0 AR30
DVPCNTL_1 TXCBP_DPB3P
AR3 AT29 AK35
R120 3KR0402 GPU_GPIO1 AR1 DVPCNTL_2 TXCBM_DPB3N TXCLK_UP_DPF3P AL36
MEM_ID0 DVPCLK TXCLK_UN_DPF3N
AU1 AV31
R226 3KR0402 GPU_GPIO2 MEM_ID1 AU3 DVPDATA_0 TX3P_DPB2P AU30 AJ38
MEM_ID2 DVPDATA_1 TX3M_DPB2N TXOUT_U0P_DPF2P
AW3 DPB AK37
R233 X_10KR0402 GPU_GPIO8 MEM_ID3 AP6 DVPDATA_2 AR32 TXOUT_U0N_DPF2N
DVPDATA_3 TX4P_DPB1P
AW5 AT31 AH35
R109 X_10KR0402 GPU_GPIO9 AU5 DVPDATA_4 TX4M_DPB1N TXOUT_U1P_DPF1P AJ36
DVPDATA_5 TXOUT_U1N_DPF1N
AR6 AT33
R107 X_10KR0402 GPU_THERMAL AW6 DVPDATA_6 TX5P_DPB0P AU32 AG38
DVPDATA_7 TX5M_DPB0N TXOUT_U2P_DPF0P
AU6 AH37
AT7 DVPDATA_8 AU14 TXOUT_U2N_DPF0N
DVPDATA_9 TXCCP_DPC3P
AV7 AV13 AF35
AN7 DVPDATA_10 TXCCM_DPC3N TXOUT_U3P AG36
DVPDATA_11 TXOUT_U3N
AV9 AT15
VDDR3VDDR3 AT9 DVPDATA_12 TX0P_DPC2P AR14
DVPDATA_13 TX0M_DPC2N
AR10 LVTMDP
R106 X_10KR0402 GPU_GPIO7 AW10 DVPDATA_14 DPC AU16
DVPDATA_15 TX1P_DPC1P
AU10 AV15 AP34
10KR0402 10KR0402 AP10 DVPDATA_16 TX1M_DPC1N TXCLK_LP_DPE3P AR34
R221 R219 DVPDATA_17 TXCLK_LN_DPE3N
AV11 AT17
AT11 DVPDATA_18 TX2P_DPC0P AR16 AW37
DVPDATA_19 TX2M_DPC0N TXOUT_L0P_DPE2P
AR12 AU35
AW12 DVPDATA_20 AU20 TXOUT_L0N_DPE2N
GPU_SMBCLK DVPDATA_21 TXCDP_DPD3P
33 SMB_THRMGPU_CLK AU12 AT19 AR37
AP12 DVPDATA_22 TXCDM_DPD3N TXOUT_L1P_DPE1P AU39
GPU_SMBDAT DVPDATA_23 TXOUT_L1N_DPE1N
33 SMB_THRMGPU_DATA AT21
AJ21 TX3P_DPD2P AR20 AP35
SWAPLOCKA TX3M_DPD2N TXOUT_L2P_DPE0P
AK21 AR35
SWAPLOCKB DPD AU22 TXOUT_L2N_DPE0N
TX4P_DPD1P
AV21 AN36
TX4M_DPD1N TXOUT_L3P AP37
I2C TXOUT_L3N
AT23
TX5P_DPD0P AR22
TX5M_DPD0N
AK26
VDDR3 AJ26 SCL
SDA
AD39 GPU_R R212 X_75R1%0402
3 R 3
GENERAL PURPOSE I/O AD37 THAMES M2 XT
GPU_GPIO0 AH20 RB
GPU_GPIO1 GPIO_0 GPU_G R207 X_75R1%0402
AH18 AE36
GPU_GPIO2 AN16 GPIO_1 G AD35
GPU_SMBDAT GPIO_2 GB
AH23
GPU_SMBCLK AJ23 GPIO_3_SMBDATA AF37 GPU_B R206 X_75R1%0402
R103 R104 R102 GPIO_4_SMBCLK B
AH17 AE38
X_10KR0402 X_10KR0402 10KR0402 AJ17 GPIO_5_AC_BATT DAC1 BB
GPU_GPIO7 GPIO_6 TPJNC70
AK17 AC36
GPU_GPIO8 AJ13 GPIO_7_BLON HSY NC AC38 TPJNC72
GPIO13 GPIO12 GPIO11 MEMORY SIZE GPU_GPIO9 GPIO_8_ROMSO VSY NC
AH15
AJ16 GPIO_9_ROMSI +1_8VRUN_GPU
GPU_GPIO11 GPIO_10_ROMSCK R210 499R1%0402
AK16 AB34
0 0 0 128 MB GPU_GPIO12 AL16 GPIO_11 RSET
GPU_GPIO13 GPIO_12 +1_8VRUN_GPU
AM16 AD34
0 0 1 256 MB AM14 GPIO_13 AVDD AE34
GPIO_14_HPD2 AVSSQ
AM13
0 1 0 64 MB AK14 GPIO_15_PWRCNTL_0 AC33 RECOMMENDED SETTINGS
GPU_THERMAL AG30
GPIO_16
GPIO_17_THERMAL_INT
VDD1DI
VSS1DI
AC34 CONFIGURATION STRAPS 0= DO NOT INSTALL RESISTOR
AN14 1 = INSTALL 10K RESISTOR
R113 X_0R0402 GPIO_18_HPD3
33 GPU_CTF AM17 ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED, X = DESIGN DEPENDANT
AL13 GPIO_19_CTF AC30
GPIO_20_PWRCNTL_1 R2/NC THEY MUST NOT CONFLICT DURING RESET NA = NOT APPLICABLE
AJ14 AC31
AK13 GPIO_21_BB_EN R2B/NC
PEX_CLKREQ# GPIO_22_ROMCSB
AN13 AD30
AM23 GPIO_23_CLKREQB G2/NC AD31 STRAPS PIN DESCRIPTION OF DEFAULT SETTINGS
JTAG_TRSTB G2B/NC
AN23
AK23 JTAG_TDI AF30
JTAG_TCK B2/NC TPJNC41
AL24 AF31
AM24 JTAG_TMS B2B/NC
+1_8VRUN_GPU JTAG_TDO
AJ19
AK19 GENERICA AC32
GENERICB C/NC
AJ20 AD32
AK20 GENERICC Y /NC AF32
R114 GENERICD COMP/NC TX_PWRS_ENB GPIO0 PCIE FULL TX OUTPUT SWING 1
AJ24
499R1%0402 AH26 GENERICE_HPD4 DAC2
GENERICF_HPD5 TX_DEEMPH_EN GPIO1 PCIE TRANSMITTER DE-EMPHASIS ENABLED 1
AH24 AD29
GENERICG_HPD6 H2SY NC/GENLK_CLK AC29
GPU_VREF V2SY NC/GENLK_VSY NC BIF_GEN2_EN_A GPIO2 PCIE GNE2 ENABLED 1
AK24
HPD1 BIF_CLK_PM_EN GPIO8 BIF_CLK_PM_EN 0
AG31
R117 C255 VDD2DI/NC AG32 BIF_VGA DIS GPIO9 VGA ENABLED 0
2 C0.1u10X0402 VSS2DI/NC BIF_RX_PLL_CALIB_BP GPIO21 BIF_RX_PLL_CALIB_BP 0 2
249R1%0402

AG33 BIOS_ROM_EN GPIO_22_ROMCSB ENABLE EXTERNAL BIOS ROM 1


+1_8VRUN_GPU A2VDD/NC
AD33 ROMIDCFG(2:0) GPIO[13:11] SERIAL ROM TY PE OR MEMORY APERTURE SIZE SELECT X X X
AH13 A2VDDQ/NC
L19 120L600m GPU_DPLL_PVDD VREFG TPJNC38 VIP_DEVICE_STRAP_ENA V2SY NC IGNORE VIP DEVICE STRAPS 0
75mA AF33
A2VSSQ/TSVSSQ
SMS_EN_HARD H2SY NC 0
C409 C418 C154 AA29 CCBY PASS GENERICC 0
X_C22u6.3X50805-RH C1u6.3Y 0402-RH C0.1u10X0402 R2SET/NC AUD[1] HSY NC built-in HDMI connector
AM32 1
AN32 DPLL_PVDD AUD[0] VSY NC Audio f unctiuon present
DPLL_PVSS 1
PCIE_VDDC
DDC/AUX AM26
L5 120L600m GPU_DPLL_VDDC DDC1CLK
125mA AN31 PLL/CLOCK AN26
DPLL_VDDC DDC1DATA
AM27
C126 C129 C140 AV33 AUX1P AL27
X_C22u6.3X50805-RH C1u6.3Y 0402-RH C0.1u10X0402 XTALIN AUX1N
AU34
XTALOUT AM19
DDC2CLK
AL19
C426 C22p50N0402 AW34 DDC2DATA
XO_IN
AN20
C0402 AW35
XO_IN2
AUX2P
AUX2N
AM20 AMD RESERVED CONFIGURATION STRAPS
Y4 R204
27MHZ 1MR0402 AL30 ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED,
TXC7A DDCCLK_AUX3P
AM30
C421 C22p50N0402 DDCDATA_AUX3N THEY MUST NOT CONFLICT DURING RESET
AL29
C0402 AF29 DDCCLK_AUX4P AM29
DPLUS DDCDATA_AUX4N H2SY NC GENERICC
AG29 THERMAL
DMINUS AN21 VDDR3
DDCCLK_AUX5P
AM21
AK32 DDCDATA_AUX5N
TS_FDO PULLUP PADS ARE NOT REQUIRED FOR THESE STRAPS BUT IF THESE GPIOS ARE USED,
AJ30 GPU_RGB_CLK R202 X_2.2KR0402
+1_8VRUN_GPU AL31 DDC6CLK AJ31 GPU_RGB_DA THEY MUST NOT CONFLICT DURING RESET
TS_A/NC DDC6DATA R203 X_2.2KR0402
AK30
28,33,45 DGPU_PWRGD DDCCLK_AUX7P
AJ32 AK29 GPIO_28_TDO GPIO21_BB_EN
AJ33 TSVDD DDCDATA_AUX7N
TSVSS
pull up to +3VSUS on PCH side
VDDR3 R81
1 1
GPU_CLKREQ# 24 THAMES M2 XT

X_10KR0402
D

R87
G
Q12
N-2N7002G_SOT23-1
S
D

PEX_CLKREQ# G

https://vinafix.com
Q13
X_N-2N7002G_SOT23-1
S

MICRO-STAR INT'L CO.,LTD.


Title

Thames GPU(DP)
Size Document Number Rev
Custom 0B
MS-14851
Date: Friday , December 02, 2011 Sheet 15 of 53
A B C D E
A B C D E

BACO enable just close the core pow er


PX_EN=0, for Norm al Operation
PX_EN =1, for BACO MODE
U24H
U24E +1_8VRUN_GPU +1_8VRUN_GPU +1_8VRUN_GPU U24F
VDDQ DP C/D POWER DP A/B POWER
MEM I/O
PCIE L20 AP20 AN24
0.5A PCIE_PVDD DPCD/DPC_VDD18#1 DPAB/DPA_VDD18#1
AC7 AA31 2 1 AP21 AP24 AB39 A3
AD11 VDDR1#1 PCIE_VDDR#1 AA32 X_0603 PCIE_VDDC DPCD/DPC_VDD18#2 DPAB/DPA_VDD18#2 PCIE_VDDC E39 PCIE_VSS#1 GND#1 A37
VDDR1#2 PCIE_VDDR#2 PCIE_VSS#2 GND#2
AF7 AA33 F34 AA16
AG10 VDDR1#3 PCIE_VDDR#3 AA34 F39 PCIE_VSS#3 GND#3 AA18
AJ7 VDDR1#4 PCIE_VDDR#4 V28 AP13 AP31 G33 PCIE_VSS#4 GND#4 AA2
AK8 VDDR1#5 PCIE_VDDR#5 W29 AT13 DPCD/DPC_VDD10#1 DPAB/DPA_VDD10#1 AP32 G34 PCIE_VSS#5 GND#5 AA21
AL9 VDDR1#6 PCIE_VDDR#6 W30 DPCD/DPC_VDD10#2 DPAB/DPA_VDD10#2 H31 PCIE_VSS#6 GND#6 AA23
4
G11 VDDR1#7 PCIE_VDDR#7 Y31 H34 PCIE_VSS#7 GND#7 AA26
4

G14 VDDR1#8 PCIE_VDDR#8 AB37 PCIE_VDDC AN17 AN27 H39 PCIE_VSS#8 GND#8 AA28
G17 VDDR1#9 PCIE_VDDR/PCIE_PVDD AP16 DP/DPC_VSSR#1 DP/DPA_VSSR#1 AP27 J31 PCIE_VSS#9 GND#9 AA6
VDDR1#10 2A DP/DPC_VSSR#2 DP/DPA_VSSR#2 PCIE_VSS#10 GND#10
G20 G30 AP17 AP28 J34 AB12
G23 VDDR1#11 PCIE_VDDC#1 G31 AW14 DP/DPC_VSSR#3 DP/DPA_VSSR#3 AW24 K31 PCIE_VSS#11 GND#11 AB15
G26 VDDR1#12 PCIE_VDDC#2 H29 AW16 DP/DPC_VSSR#4 DP/DPA_VSSR#4 AW26 K34 PCIE_VSS#12 GND#12 AB17
G29 VDDR1#13 PCIE_VDDC#3 H30 +1_8VRUN_GPU DP/DPC_VSSR#5 DP/DPA_VSSR#5 +1_8VRUN_GPU
K39 PCIE_VSS#13 GND#13 AB20
H10 VDDR1#14 PCIE_VDDC#4 J29 L31 PCIE_VSS#14 GND#14 AB22
VDDR1#15 PCIE_VDDC#5 PCIE_VSS#15 GND#15
J7 J30 L34 AB24
J9 VDDR1#16 PCIE_VDDC#6 L28 AP22 AP25 M34 PCIE_VSS#16 GND#16 AB27
K11 VDDR1#17 PCIE_VDDC#7 M28 AP23 DPCD/DPD_VDD18#1 DPAB/DPB_VDD18#1 AP26 M39 PCIE_VSS#17 GND#17 AC11
K13 VDDR1#18 PCIE_VDDC#8 N28 DPCD/DPD_VDD18#2 DPAB/DPB_VDD18#2 N31 PCIE_VSS#18 GND#18 AC13
VDDR1#19 PCIE_VDDC#9 PCIE_VDDC PCIE_VDDC PCIE_VSS#19 GND#19
K8 R28 N34 AC16
VDDR1#20 PCIE_VDDC#10 PCIE_VSS#20 GND#20
L12 T28 P31 AC18
L16 VDDR1#21 PCIE_VDDC#11 U28 AP14 AN33 P34 PCIE_VSS#21 GND#21 AC2
L21 VDDR1#22 PCIE_VDDC#12 GPU_CORE AP15 DPCD/DPD_VDD10#1 DPAB/DPB_VDD10#1 AP33 P39 PCIE_VSS#22 GND#22 AC21
VDDR1#23 DPCD/DPD_VDD10#2 DPAB/DPB_VDD10#2 PCIE_VSS#23 GND#23
L23 R34 AC23
L26 VDDR1#24 AA15 T31 PCIE_VSS#24 GND#24 AC26
VDDR1#25 CORE VDDC#1 PCIE_VSS#25 GND#25
L7 AA17 T34 AC28
M11 VDDR1#26 VDDC#2 AA20 AN19 AN29 T39 PCIE_VSS#26 GND#26 AC6
N11 VDDR1#27 VDDC#3 AA22 AP18 DP/DPD_VSSR#1 DP/DPB_VSSR#1 AP29 U31 PCIE_VSS#27 GND#27 AD15
P7 VDDR1#28 VDDC#4 AA24 AP19 DP/DPD_VSSR#2 DP/DPB_VSSR#2 AP30 U34 PCIE_VSS#28 GND#28 AD17
R11 VDDR1#29 VDDC#5 AA27 AW20 DP/DPD_VSSR#3 DP/DPB_VSSR#3 AW30 V34 PCIE_VSS#29 GND#29 AD20
U11 VDDR1#30 VDDC#6 AB16 AW22 DP/DPD_VSSR#4 DP/DPB_VSSR#4 AW32 V39 PCIE_VSS#30 GND#30 AD22
U7 VDDR1#31 VDDC#7 AB18 DP/DPD_VSSR#5 DP/DPB_VSSR#5 W31 PCIE_VSS#31 GND#31 AD24
Y11 VDDR1#32 VDDC#8 AB21 W34 PCIE_VSS#32 GND#32 AD27
Y7 VDDR1#33 VDDC#9 AB23 Y34 PCIE_VSS#33 GND#33 AD9
VDDR1#34 VDDC#10 AB26 +1_8VRUN_GPU R224 150R1%0402 AW18 AW28 150R1%0402 R208 Y39 PCIE_VSS#34 GND#34 AE2
+1_8VRUN_GPU VDDC#11 AB28 DPCD_CALR DPAB_CALR +1_8VRUN_GPU PCIE_VSS#35 GND#35 AE6
VDDC#12 AC17 GND#36 AF10
L6 VDDC#13 GND#37
110mA AC20 DP E/F POWER DP PLL POWER AF16
2 1 LEVEL VDDC#14 AC22 AH34 AU28 GND#38 AF18
TRANSLATION VDDC#15 AC24 AJ34 DPEF/DPE_VDD18#1 DPAB_VDD18/DPA_PVDD AV27 GND#39 AF21
VDDC#16 PCIE_VDDC DPEF/DPE_VDD18#2 DP_VSSR/DPA_PVSS +1_8VRUN_GPU
GND GND#40

POWER
X_0603 VDD_CT AF26 AC27 AG17
AF27 VDD_CT#1 VDDC#17 AD18 F15 GND#41 AG2
VDDR3 VDD_CT#2 VDDC#18 GND#100 GND#42
AG26 AD21 F17 AG20
VDD_CT#3 VDDC#19 GND#101 GND#43
AG27 AD23 AL33 AV29 F19 AG22
VDD_CT#4 VDDC#20 AD26 AM33 DPEF/DPE_VDD10#1 DPAB_VDD18/DPB_PVDD AR28 F21 GND#102 GND#44 AG6
VDDC#21 AF17 DPEF/DPE_VDD10#2 DP_VSSR/DPB_PVSS +1_8VRUN_GPU F23 GND#103 GND#45 AG9
I/O VDDC#22 GND#104 GND#46
AF20 F25 AH21
VDDR3 VDDC#23 GND#105 GND#47
AF23 AF22 F27 AJ10
AF24 VDDR3#1 VDDC#24 AG16 AN34 AU18 F29 GND#106 GND#48 AJ11
+1_8VRUN_GPU
AG23 VDDR3#2 VDDC#25 AG18 AP39 DP/DPE_VSSR#1 DPCD_VDD18/DPC_PVDD AV17 F31 GND#107 GND#49 AJ2
AG24 VDDR3#3 VDDC#26 AG21 AR39 DP/DPE_VSSR#2 DP_VSSR/DPC_PVSS +1_8VRUN_GPU
F33 GND#108 GND#50 AJ28
L7 VDDR3#4 VDDC#27 AH22 AU37 DP/DPE_VSSR#3 F7 GND#109 GND#51 AJ6
VDDC#28 DP/DPE_VSSR#4 GND#110 GND#52
2 1 AH27 F9 AK11
VDDR4 AF13 VDDC#29 AH28 BINF_VCCD +1_8VRUN_GPU
AV19 G2 GND#111 GND#53 AK31
3 X_0603 AF15 VDDR4#4 VDDC#30 M26 DPCD_VDD18/DPD_PVDD AR18 G6 GND#112 GND#54 AK7 3
AG13 VDDR4#5 VDDC#31 N24 DP_VSSR/DPD_PVSS +1_8VRUN_GPU H9 GND#113 GND#55 AL11
AG15 VDDR4#7 VDDC#32 N27 AF34 J2 GND#114 GND#56 AL14
VDDR4#8 VDDC/BIF_VDDC#33 R18 AG34 DPEF/DPF_VDD18#1 J27 GND#115 GND#57 AL17
VDDC#34 R21 PCIE_VDDC DPEF/DPF_VDD18#2 AM37 J6 GND#116 GND#58 AL2
AD12 VDDC#35 R23 DPEF_VDD18/DPE_PVDD AN38 J8 GND#117 GND#59 AL20
VDDR4#1 VDDC#36 DP_VSSR/DPE_PVSS +1_8VRUN_GPU GND#118 GND#60
AF11 R26 K14 AL21 PX_EN 45
AF12 VDDR4#2 VDDC#37 T17 AK33 K7 GND#119 GND/PX_EN#61 AL23
AG11 VDDR4#3 VDDC#38 T20 AK34 DPEF/DPF_VDD10#1 L11 GND#120 GND#62 AL26
VDDR4#6 VDDC#39 T22 DPEF/DPF_VDD10#2 AL38 L17 GND#121 GND#63 AL32 need a pull down R
VDDC#40 C249 DPEF_VDD18/DPF_PVDD GND#122 GND#64
T24 AM35 L2 AL6
VDDC#41 DP_VSSR/DPF_PVSS GND#123 GND#65 PR47
T27 L22 AL8
VDDC/BIF_VDDC#42 GND#124 GND#66
U16 AF39 L24 AM11 X_100KR0402
M20 VDDC#43 U18 AH39 DP/DPF_VSSR#1 L6 GND#125 GND#67 AM31
NC_VDDRHA VDDC#44 C0.1u10X0402 DP/DPF_VSSR#2 GND#126 GND#68
M21 U21 AK39 M17 AM9
NC_VSSRHA VDDC#45 DP/DPF_VSSR#3 GND#127 GND#69
U23 AL34 M22 AN11
VDDC#46 DP/DPF_VSSR#4 GND#128 GND#70
U26 AM34 M24 AN2
V12 VDDC#47 V17 DP/DPF_VSSR#5 N16 GND#129 GND#71 AN30
U12 NC_VDDRHB VDDC#48 V20 N18 GND#130 GND#72 AN6
NC_VSSRHB VDDC#49 V22 N2 GND#131 GND#73 AN8
+1_8VRUN_GPU VDDC#50 V24 R205 150R1%0402 AM39 N21 GND#132 GND#74 AP11
VDDC#51 V27 DPEF_CALR N23 GND#133 GND#75 AP7
VDDC#52 Y16 N26 GND#134 GND#76 AP9
L21 120L600m MPV18 PLL VDDC#53 GND#135 GND#77
Y18 N6 AR5
VDDC#54 Y21 R15 GND#136 GND#78 B11
VDDC#55 Y23 T HAMES M2 XT R17 GND#137 GND#79 B13
+1_8VRUN_GPU
H7 VDDC#56 Y26 R2 GND#138 GND#80 B15
H8 MPV18#1 VDDC#57 Y28 R20 GND#139 GND#81 B17
L8 120L600m SPV18 MPV18#2 VDDC#58 R22 GND#140 GND#82 B19
GPU_CORE GND#141 GND#83
R24 B21
PCIE_VDDC AM10 R27 GND#142 GND#84 B23
SPV18 T HAMES M2 XT AA13 R6 GND#143 T HAMES M2 XT GND#85 B25
L9 120L600m SPV10 AN9 VDDCI#1 AB13 T11 GND#144 GND#86 B27
SPV10 VDDCI#2 R161 X_0R0603 GND#145 GND#87
AC12 PCIE_VDDC BINF_VCCD T13 B29
AN10 VDDCI#3 AC15 T16 GND#146 GND#88 B31
SPVSS VDDCI#4 GND#147 GND#89
AD13 T18 B33
VDDCI#5 AD16 T21 GND#148 GND#90 B7
VDDCI#6 M15 R155 0R0603 T23 GND#149 GND#91 B9
VDDCI#7 GPU_CORE BINF_VCCD GND#150 GND#92
M16 T26 C1
VOLTAGE VDDCI#8 GND#151 GND#93
M18 U15 C39
SENESE VDDCI#9 M23 U17 GND#153 GND#94 E35
VDDCI#10 N13 U2 GND#154 GND#95 E5
AF28 VDDCI#11 N15 U20 GND#155 GND#96 F11
FB_VDDC VDDCI#12 GND#156 GND#97
N17 U22 F13
VDDCI#13 N20 U24 GND#157 GND#98
AG28 VDDCI#14 N22 U27 GND#158
FB_VDDCI ISOLATED VDDCI#15 GND#159
R12 U6
CORE I/O VDDCI#16 R13 V11 GND#160
2
AH29 VDDCI#17 R16 V16 GND#161 2
FB_GND VDDCI#18 T12 V18 GND#163
VDDCI#19 T15 V21 GND#164
VDDCI#20 V15 V23 GND#165
SPV10 VDDCI#21 GND#166
Y13 V26
VDDCI#22 W2 GND#167
SPV10 W6 GND#168
Y15 GND#169
GND#170
Y17
C262 C275 C278 Y20 GND#171
X_C22u6.3X50805-RH C1u6.3Y0402 C0.1u10X0402 GND#172
Y22 A39
Y24 GND#173 VSS_MECH#1 AW1
Y27 GND#174 VSS_MECH#2 AW39
GND#175 VSS_MECH#3
U13
NC#1
V13
NC#2
VDD_CT VDDR4

VDD_CT VDDR4

C165 C181 C187 C225 C277 C241


X_C22u6.3X50805-RH C1u6.3Y0402 C1u6.3Y0402 X_C22u6.3X50805-RH C1u6.3Y0402 C1u6.3Y0402

VDDR3 PCIE_PVDD

VDDR3 PCIE_PVDD VDDQ

C215 C221 C239 C425 C427 C220


X_C22u6.3X50805-RH C1u6.3Y0402 C1u6.3Y0402 X_C22u6.3X50805-RH C1u6.3Y0402 C1u6.3Y0402
C319 C322 C306 C293 C302
C22u6.3X50805 X_C1u6.3Y0402 C1u6.3Y0402 X_C1u6.3Y0402 X_C1u6.3Y0402

MPV18 SPV18 +1_8VRUN_GPU

MPV18 SPV18

C435 C323 C437 C240 C250 C251 C300 C317 C320 C311 C292 C298 C142 C173 C164 C145 C135 C193
X_C22u6.3X50805-RH C1u6.3Y0402 C0.1u10X0402 X_C22u6.3X50805-RH C1u6.3Y0402 C0.1u10X0402 C1u6.3Y0402 C1u6.3Y0402 X_C1u6.3Y0402 X_C1u6.3Y0402 X_C1u6.3Y0402 X_C1u6.3Y0402 X_C1u6.3Y0402 X_C1u6.3Y0402 X_C1u6.3Y0402 X_C1u6.3Y0402 X_C0.1u10X0402 X_C0.1u10X0402

1 GPU_CORE 1

PCIE_VDDC

C131 C343 C268 C259 C243 C273 C213 C137 C136 C299 C258 C286 C246 C276 C290 C294
X_C22u6.3X50805-RH 4.7uX0402 C1u6.3Y0402 C0.1u10X0402 C22u6.3X50805 C22u6.3X50805 X_C22u6.3X50805 X_C22u6.3X50805 X_C22u6.3X50805 C1u6.3Y0402 C1u6.3Y0402 X_C1u6.3Y0402 X_C1u6.3Y0402 C1u6.3Y0402 X_C1u6.3Y0402 X_C1u6.3Y0402

C284 C291 C285 C233 C267


C0.1u10X0402 C0.1u10X0402 C0.1u10X0402 X_C0.1u10X0402 C0.1u10X0402
MICRO-STAR INT'L CO.,LTD.
T itle

Size
Thames GPU(POWER GND)
Document Number Rev
Custom 0B
MS-14851
Date: Friday, December 02, 2011 Sheet 16 of 53
A B C D E

https://vinafix.com
A B C D E

VDDQ VDDQ

1 +
C442 C356 C333 C466 C326 PEC17 C303 C487 C461
C10u6.3X50805 C0.1u16X50402-1 C0.1u16X50402-1 X_C0.1u16X50402-1 C10u6.3X50805 X_C560u2.5pSO X_C0.1u16X50402-1 C0.1u16X50402-1 X_C0.1u16X50402-1

2
4 4
C352 C481 C468 C353 C328 C477 C443 C332 C324 C307
X_C10u6.3X50805 C0.1u16X50402-1 C0.1u16X50402-1 C0.1u16X50402-1 X_C0.1u16X50402-1 X_C10u6.3X50805 C0.1u16X50402-1 X_C0.1u16X50402-1 C0.1u16X50402-1 X_C0.1u16X50402-1

VDDQ

R158
1KR1%0402
L11 L22 L26 L15
VRAMREF_A 2 1 VRAMREF_A 2 1 VRAMREF_A 2 1 VRAMREF_A 2 1

X_0603 X_0603 X_0603 X_0603

R157 C339 C316 C457 C471


1KR1%0402 C2.2u6.3X5 X_C0.1u16X50402-1 X_C0.1u16X50402-1 X_C0.1u16X50402-1 C335
X_C0.1u16X50402-1

U80 U81 U82 U83

M8 E3 VM A_DQA18 M8 E3 VM A_DQA31 M8 E3 VM A_DQA33 M8 E3 VM A_DQA54


H1 VREFCA DQL0 F7 VM A_DQA22 H1 VREFCA DQL0 F7 VM A_DQA25 H1 VREFCA DQL0 F7 VM A_DQA38 H1 VREFCA DQL0 F7 VM A_DQA51
VREFDQ DQL1 F2 VM A_DQA16 VREFDQ DQL1 F2 VM A_DQA30 VREFDQ DQL1 F2 VM A_DQA32 VREFDQ DQL1 F2 VM A_DQA53
A_M A0 N3 DQL2 F8 VM A_DQA23 A_M A0 N3 DQL2 F8 VM A_DQA24 A_M A0 N3 DQL2 F8 VM A_DQA34 A_M A0 N3 DQL2 F8 VM A_DQA48
A_M A1 P7 A0 DQL3 H3 VM A_DQA19 A_M A1 P7 A0 DQL3 H3 VM A_DQA29 A_M A1 P7 A0 DQL3 H3 VM A_DQA35 A_M A1 P7 A0 DQL3 H3 VM A_DQA52
A_M A2 P3 A1 DQL4 H8 VM A_DQA21 A_M A2 P3 A1 DQL4 H8 VM A_DQA26 A_M A2 P3 A1 DQL4 H8 VM A_DQA39 A_M A2 P3 A1 DQL4 H8 VM A_DQA49
A_M A3 N2 A2 DQL5 G2 VM A_DQA17 A_M A3 N2 A2 DQL5 G2 VM A_DQA28 A_M A3 N2 A2 DQL5 G2 VM A_DQA36 A_M A3 N2 A2 DQL5 G2 VM A_DQA55
A_M A4 P8 A3 DQL6 H7 VM A_DQA20 A_M A4 P8 A3 DQL6 H7 VM A_DQA27 A_M A4 P8 A3 DQL6 H7 VM A_DQA37 A_M A4 P8 A3 DQL6 H7 VM A_DQA50
A_M A5 P2 A4 DQL7 A_M A5 P2 A4 DQL7 A_M A5 P2 A4 DQL7 A_M A5 P2 A4 DQL7
3 A_M A6 R8 A5 A_M A6 R8 A5 A_M A6 R8 A5 A_M A6 R8 A5 3
A_M A7 R2 A6 D7 VM A_DQA15 A_M A7 R2 A6 D7 VM A_DQA1 A_M A7 R2 A6 D7 VM A_DQA45 A_M A7 R2 A6 D7 VM A_DQA62
A_M A8 T8 A7 DQU0 C3 VM A_DQA8 A_M A8 T8 A7 DQU0 C3 VM A_DQA7 A_M A8 T8 A7 DQU0 C3 VM A_DQA44 A_M A8 T8 A7 DQU0 C3 VM A_DQA58
A_M A9 R3 A8 DQU1 C8 VM A_DQA14 A_M A9 R3 A8 DQU1 C8 VM A_DQA0 A_M A9 R3 A8 DQU1 C8 VM A_DQA46 A_M A9 R3 A8 DQU1 C8 VM A_DQA56
A_M A10 L7 A9 DQU2 C2 VM A_DQA11 A_M A10 L7 A9 DQU2 C2 VM A_DQA4 A_M A10 L7 A9 DQU2 C2 VM A_DQA43 A_M A10 L7 A9 DQU2 C2 VM A_DQA60
A_M A11 R7 A10/AP DQU3 A7 VM A_DQA13 A_M A11 R7 A10/AP DQU3 A7 VM A_DQA3 A_M A11 R7 A10/AP DQU3 A7 VM A_DQA42 A_M A11 R7 A10/AP DQU3 A7 VM A_DQA59
A_M A12 N7 A11 DQU4 A2 VM A_DQA9 A_M A12 N7 A11 DQU4 A2 VM A_DQA6 A_M A12 N7 A11 DQU4 A2 VM A_DQA40 A_M A12 N7 A11 DQU4 A2 VM A_DQA63
A_M A13 T3 A12/BC DQU5 B8 VM A_DQA12 A_M A13 T3 A12/BC DQU5 B8 VM A_DQA2 A_M A13 T3 A12/BC DQU5 B8 VM A_DQA47 A_M A13 T3 A12/BC DQU5 B8 VM A_DQA57
T7 A13 DQU6 A3 VM A_DQA10 T7 A13 DQU6 A3 VM A_DQA5 T7 A13 DQU6 A3 VM A_DQA41 T7 A13 DQU6 A3 VM A_DQA61
M7 A14 DQU7 M7 A14 DQU7 M7 A14 DQU7 M7 A14 DQU7
A15 VDDQ A15 VDDQ A15 VDDQ A15 VDDQ

A_BA0 M2 B2 A_BA0 M2 B2 A_BA0 M2 B2 A_BA0 M2 B2


A_BA1 N8 BA0 VDD D9 A_BA1 N8 BA0 VDD D9 A_BA1 N8 BA0 VDD D9 A_BA1 N8 BA0 VDD D9
A_BA2 M3 BA1 VDD G7 A_BA2 M3 BA1 VDD G7 A_BA2 M3 BA1 VDD G7 A_BA2 M3 BA1 VDD G7
BA2 VDD K2 BA2 VDD K2 BA2 VDD K2 BA2 VDD K2
VDD K8 VDD K8 VDD K8 VDD K8
VDD N1 VDD N1 VDD N1 VDD N1
J7 VDD N9 J7 VDD N9 J7 VDD N9 J7 VDD N9
14 A0_CLK CK VDD 14 A0_CLK CK VDD 14 A1_CLK CK VDD 14 A1_CLK CK VDD
14 A0_CLK# K7 R1 14 A0_CLK# K7 R1 14 A1_CLK# K7 R1 14 A1_CLK# K7 R1
K9 CK VDD R9 K9 CK VDD R9 K9 CK VDD R9 K9 CK VDD R9
14 A0_CKE CKE VDD 14 A0_CKE CKE VDD 14 A1_CKE CKE VDD 14 A1_CKE CKE VDD

14 ODT A0 K1 A1 14 ODT A0 K1 A1 14 ODT A1 K1 A1 14 ODT A1 K1 A1


L2 ODT VDDQ A8 L2 ODT VDDQ A8 L2 ODT VDDQ A8 L2 ODT VDDQ A8
14 A0_CSB0# CS VDDQ 14 A0_CSB0# CS VDDQ 14 A1_CSB0# CS VDDQ 14 A1_CSB0# CS VDDQ
14 A0_RAS#
J3 C1 14 A0_RAS#
J3 C1 14 A1_RAS#
J3 C1 14 A1_RAS#
J3 C1
K3 RAS VDDQ C9 K3 RAS VDDQ C9 K3 RAS VDDQ C9 K3 RAS VDDQ C9
14 A0_CAS# CAS VDDQ 14 A0_CAS# CAS VDDQ 14 A1_CAS# CAS VDDQ 14 A1_CAS# CAS VDDQ
14 A0_WEB# L3 D2 14 A0_WEB# L3 D2 14 A1_WEB# L3 D2 14 A1_WEB# L3 D2
WE VDDQ E9 WE VDDQ E9 WE VDDQ E9 WE VDDQ E9
VDDQ F1 VDDQ F1 VDDQ F1 VDDQ F1
A_QSA2 F3 VDDQ H2 A_QSA3 F3 VDDQ H2 A_QSA4 F3 VDDQ H2 A_QSA6 F3 VDDQ H2
A_QSA1 C7 DQSL VDDQ H9 A_QSA0 C7 DQSL VDDQ H9 A_QSA5 C7 DQSL VDDQ H9 A_QSA7 C7 DQSL VDDQ H9
DQSU VDDQ DQSU VDDQ DQSU VDDQ DQSU VDDQ

A_DQM A2 E7 A9 A_DQM A3 E7 A9 A_DQM A4 E7 A9 A_DQM A6 E7 A9


A_DQM A1 D3 DML VSS B3 A_DQM A0 D3 DML VSS B3 A_DQM A5 D3 DML VSS B3 A_DQM A7 D3 DML VSS B3
DMU VSS E1 DMU VSS E1 DMU VSS E1 DMU VSS E1
VSS G8 VSS G8 VSS G8 VSS G8
2
A_QSA#2 G3 VSS J2 A_QSA#3 G3 VSS J2 A_QSA#4 G3 VSS J2 A_QSA#6 G3 VSS J2
2
A_QSA#1 B7 DQSL VSS J8 A_QSA#0 B7 DQSL VSS J8 A_QSA#5 B7 DQSL VSS J8 A_QSA#7 B7 DQSL VSS J8
DQSU VSS M1 DQSU VSS M1 DQSU VSS M1 DQSU VSS M1
VSS M9 VSS M9 VSS M9 VSS M9
VSS P1 VSS P1 VSS P1 VSS P1
T2 VSS P9 GPU_M EM _RST # T2 VSS P9 GPU_M EM _RST # T2 VSS P9 GPU_M EM _RST # T2 VSS P9
14,18 GPU_M EM _RST # RESET VSS RESET VSS RESET VSS RESET VSS
T1 T1 T1 T1
R269 L8 VSS T9 R152 L8 VSS T9 R283 L8 VSS T9 R156 L8 VSS T9
ZQ VSS ZQ VSS ZQ VSS ZQ VSS
243R1%0402 243R1%0402 243R1%0402 243R1%0402
B1 B1 B1 B1
VSSQ B9 VSSQ B9 VSSQ B9 VSSQ B9
VSSQ D1 VSSQ D1 VSSQ D1 VSSQ D1
VSSQ D8 VSSQ D8 VSSQ D8 VSSQ D8
VSSQ E2 VSSQ E2 VSSQ E2 VSSQ E2
J1 VSSQ E8 J1 VSSQ E8 J1 VSSQ E8 J1 VSSQ E8
L1 NC1 VSSQ F9 L1 NC1 VSSQ F9 L1 NC1 VSSQ F9 L1 NC1 VSSQ F9
J9 NC2 VSSQ G1 J9 NC2 VSSQ G1 J9 NC2 VSSQ G1 J9 NC2 VSSQ G1
L9 NC3 VSSQ G9 L9 NC3 VSSQ G9 L9 NC3 VSSQ G9 L9 NC3 VSSQ G9
NC4 VSSQ NC4 VSSQ NC4 VSSQ NC4 VSSQ
INFINEON 96-BALL INFINEON 96-BALL INFINEON 96-BALL INFINEON 96-BALL
SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
SAM SUNG ( K4W2G1646C-HC12 ) SAM SUNG ( K4W2G1646C-HC12 ) SAM SUNG ( K4W2G1646C-HC12 ) SAM SUNG ( K4W2G1646C-HC12 )

A0_CLK R259 56R0402 A1_CLK R278 56R0402


14 VM A_DQA[63:0]
C445 C0.01u16X0402 C483 C0.01u16X0402
14 A_M A[13:0] 14 A_QSA[7:0]
A0_CLK# R261 56R0402 A1_CLK# R280 56R0402
14 A_BA[2:0] 14 A_QSA#[7:0]
1 1
14 A_DQM A[7:0]

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MICRO-STAR INT'L CO.,LTD.
T itle

Thames GPU(VRAM)
Size Docum ent Num ber Rev
C 0B
MS-14851
Date: Friday, Decem ber 02, 2011 Sheet 17 of 53
A B C D E
A B C D E

VDDQ VDDQ

+1
C350 C338 C304 C318 C340 C8 C346 C467 C358
C10u6.3X50805 C0.1u16X50402-1 C0.1u16X50402-1 X_C0.1u16X50402-1 C10u6.3X50805 X_C330u X_C0.1u16X50402-1 C0.1u16X50402-1 X_C0.1u16X50402-1

2
4 4

C321 C470 C329 C486 C469 C330 C327 C463 C347 C325
X_C10u6.3X50805 C0.1u16X50402-1 C0.1u16X50402-1 C0.1u16X50402-1 X_C0.1u16X50402-1 X_C10u6.3X50805 C0.1u16X50402-1 X_C0.1u16X50402-1 C0.1u16X50402-1 X_C0.1u16X50402-1

VDDQ

R275
1KR1%0402
L27 L16 L10 L23
VRAMREF_B 2 1 VRAMREF_B 2 1 VRAMREF_B 2 1 VRAMREF_B 2 1

X_0603 X_0603 X_0603 X_0603

R276 C480 C482 C354 C313


1KR1%0402 C2.2u6.3X5 X_C0.1u16X50402-1 X_C0.1u16X50402-1 X_C0.1u16X50402-1 C455
X_C0.1u16X50402-1

U90 U91 U92 U93

M8 E3 VM B_DQA27 M8 E3 VM B_DQA15 M8 E3 VM B_DQA46 M8 E3 VM B_DQA56


H1 VREFCA DQL0 F7 VM B_DQA29 H1 VREFCA DQL0 F7 VM B_DQA10 H1 VREFCA DQL0 F7 VM B_DQA41 H1 VREFCA DQL0 F7 VM B_DQA61
VREFDQ DQL1 F2 VM B_DQA24 VREFDQ DQL1 F2 VM B_DQA14 VREFDQ DQL1 F2 VM B_DQA47 VREFDQ DQL1 F2 VM B_DQA57
B_M A0 N3 DQL2 F8 VM B_DQA30 B_M A0 N3 DQL2 F8 VM B_DQA8 B_M A0 N3 DQL2 F8 VM B_DQA40 B_M A0 N3 DQL2 F8 VM B_DQA62
B_M A1 P7 A0 DQL3 H3 VM B_DQA26 B_M A1 P7 A0 DQL3 H3 VM B_DQA12 B_M A1 P7 A0 DQL3 H3 VM B_DQA44 B_M A1 P7 A0 DQL3 H3 VM B_DQA60
B_M A2 P3 A1 DQL4 H8 VM B_DQA31 B_M A2 P3 A1 DQL4 H8 VM B_DQA9 B_M A2 P3 A1 DQL4 H8 VM B_DQA42 B_M A2 P3 A1 DQL4 H8 VM B_DQA58
3 B_M A3 N2 A2 DQL5 G2 VM B_DQA25 B_M A3 N2 A2 DQL5 G2 VM B_DQA13 B_M A3 N2 A2 DQL5 G2 VM B_DQA45 B_M A3 N2 A2 DQL5 G2 VM B_DQA59 3
B_M A4 P8 A3 DQL6 H7 VM B_DQA28 B_M A4 P8 A3 DQL6 H7 VM B_DQA11 B_M A4 P8 A3 DQL6 H7 VM B_DQA43 B_M A4 P8 A3 DQL6 H7 VM B_DQA63
B_M A5 P2 A4 DQL7 B_M A5 P2 A4 DQL7 B_M A5 P2 A4 DQL7 B_M A5 P2 A4 DQL7
B_M A6 R8 A5 B_M A6 R8 A5 B_M A6 R8 A5 B_M A6 R8 A5
B_M A7 R2 A6 D7 VM B_DQA22 B_M A7 R2 A6 D7 VM B_DQA1 B_M A7 R2 A6 D7 VM B_DQA33 B_M A7 R2 A6 D7 VM B_DQA54
B_M A8 T8 A7 DQU0 C3 VM B_DQA16 B_M A8 T8 A7 DQU0 C3 VM B_DQA7 B_M A8 T8 A7 DQU0 C3 VM B_DQA38 B_M A8 T8 A7 DQU0 C3 VM B_DQA51
B_M A9 R3 A8 DQU1 C8 VM B_DQA19 B_M A9 R3 A8 DQU1 C8 VM B_DQA0 B_M A9 R3 A8 DQU1 C8 VM B_DQA35 B_M A9 R3 A8 DQU1 C8 VM B_DQA55
B_M A10 L7 A9 DQU2 C2 VM B_DQA17 B_M A10 L7 A9 DQU2 C2 VM B_DQA6 B_M A10 L7 A9 DQU2 C2 VM B_DQA37 B_M A10 L7 A9 DQU2 C2 VM B_DQA50
B_M A11 R7 A10/AP DQU3 A7 VM B_DQA20 B_M A11 R7 A10/AP DQU3 A7 VM B_DQA3 B_M A11 R7 A10/AP DQU3 A7 VM B_DQA34 B_M A11 R7 A10/AP DQU3 A7 VM B_DQA52
B_M A12 N7 A11 DQU4 A2 VM B_DQA21 B_M A12 N7 A11 DQU4 A2 VM B_DQA4 B_M A12 N7 A11 DQU4 A2 VM B_DQA36 B_M A12 N7 A11 DQU4 A2 VM B_DQA48
B_M A13 T3 A12/BC DQU5 B8 VM B_DQA23 B_M A13 T3 A12/BC DQU5 B8 VM B_DQA2 B_M A13 T3 A12/BC DQU5 B8 VM B_DQA32 B_M A13 T3 A12/BC DQU5 B8 VM B_DQA53
T7 A13 DQU6 A3 VM B_DQA18 T7 A13 DQU6 A3 VM B_DQA5 T7 A13 DQU6 A3 VM B_DQA39 T7 A13 DQU6 A3 VM B_DQA49
M7 A14 DQU7 M7 A14 DQU7 M7 A14 DQU7 M7 A14 DQU7
A15 VDDQ A15 VDDQ A15 VDDQ A15 VDDQ

B_BA0 M2 B2 B_BA0 M2 B2 B_BA0 M2 B2 B_BA0 M2 B2


B_BA1 N8 BA0 VDD D9 B_BA1 N8 BA0 VDD D9 B_BA1 N8 BA0 VDD D9 B_BA1 N8 BA0 VDD D9
B_BA2 M3 BA1 VDD G7 B_BA2 M3 BA1 VDD G7 B_BA2 M3 BA1 VDD G7 B_BA2 M3 BA1 VDD G7
BA2 VDD K2 BA2 VDD K2 BA2 VDD K2 BA2 VDD K2
VDD K8 VDD K8 VDD K8 VDD K8
VDD N1 VDD N1 VDD N1 VDD N1
J7 VDD N9 J7 VDD N9 J7 VDD N9 J7 VDD N9
14 B0_CLK CK VDD 14 B0_CLK CK VDD 14 B1_CLK CK VDD 14 B1_CLK CK VDD
14 B0_CLK#
K7 R1 14 B0_CLK#
K7 R1 14 B1_CLK#
K7 R1 14 B1_CLK#
K7 R1
K9 CK VDD R9 K9 CK VDD R9 K9 CK VDD R9 K9 CK VDD R9
14 B0_CKE CKE VDD 14 B0_CKE CKE VDD 14 B1_CKE CKE VDD 14 B1_CKE CKE VDD

14 ODT B0 K1 A1 14 ODT B0 K1 A1 14 ODT B1 K1 A1 14 ODT B1 K1 A1


L2 ODT VDDQ A8 L2 ODT VDDQ A8 L2 ODT VDDQ A8 L2 ODT VDDQ A8
14 B0_CSB0# CS VDDQ 14 B0_CSB0# CS VDDQ 14 B1_CSB0# CS VDDQ 14 B1_CSB0# CS VDDQ
14 B0_RAS# J3 C1 14 B0_RAS# J3 C1 14 B1_RAS# J3 C1 14 B1_RAS# J3 C1
K3 RAS VDDQ C9 K3 RAS VDDQ C9 K3 RAS VDDQ C9 K3 RAS VDDQ C9
14 B0_CAS# CAS VDDQ 14 B0_CAS# CAS VDDQ 14 B1_CAS# CAS VDDQ 14 B1_CAS# CAS VDDQ
14 B0_WEB#
L3 D2 14 B0_WEB#
L3 D2 14 B1_WEB#
L3 D2 14 B1_WEB#
L3 D2
WE VDDQ E9 WE VDDQ E9 WE VDDQ E9 WE VDDQ E9
VDDQ F1 VDDQ F1 VDDQ F1 VDDQ F1
B_QSA3 F3 VDDQ H2 B_QSA1 F3 VDDQ H2 B_QSA5 F3 VDDQ H2 B_QSA7 F3 VDDQ H2
B_QSA2 C7 DQSL VDDQ H9 B_QSA0 C7 DQSL VDDQ H9 B_QSA4 C7 DQSL VDDQ H9 B_QSA6 C7 DQSL VDDQ H9
DQSU VDDQ DQSU VDDQ DQSU VDDQ DQSU VDDQ

B_DQM A3 E7 A9 B_DQM A1 E7 A9 B_DQM A5 E7 A9 B_DQM A7 E7 A9


2
B_DQM A2 D3 DML VSS B3 B_DQM A0 D3 DML VSS B3 B_DQM A4 D3 DML VSS B3 B_DQM A6 D3 DML VSS B3
2
DMU VSS E1 DMU VSS E1 DMU VSS E1 DMU VSS E1
VSS G8 VSS G8 VSS G8 VSS G8
B_QSA#3 G3 VSS J2 B_QSA#1 G3 VSS J2 B_QSA#5 G3 VSS J2 B_QSA#7 G3 VSS J2
B_QSA#2 B7 DQSL VSS J8 B_QSA#0 B7 DQSL VSS J8 B_QSA#4 B7 DQSL VSS J8 B_QSA#6 B7 DQSL VSS J8
DQSU VSS M1 DQSU VSS M1 DQSU VSS M1 DQSU VSS M1
VSS M9 VSS M9 VSS M9 VSS M9
VSS P1 VSS P1 VSS P1 VSS P1
T2 VSS P9 GPU_M EM _RST # T2 VSS P9 GPU_M EM _RST # T2 VSS P9 GPU_M EM _RST # T2 VSS P9
14,17 GPU_M EM _RST # RESET VSS RESET VSS RESET VSS RESET VSS
T1 T1 T1 T1
R271 L8 VSS T9 R163 L8 VSS T9 R154 L8 VSS T9 R263 L8 VSS T9
ZQ VSS ZQ VSS ZQ VSS ZQ VSS
243R1%0402 243R1%0402 243R1%0402 243R1%0402
B1 B1 B1 B1
VSSQ B9 VSSQ B9 VSSQ B9 VSSQ B9
VSSQ D1 VSSQ D1 VSSQ D1 VSSQ D1
VSSQ D8 VSSQ D8 VSSQ D8 VSSQ D8
VSSQ E2 VSSQ E2 VSSQ E2 VSSQ E2
J1 VSSQ E8 J1 VSSQ E8 J1 VSSQ E8 J1 VSSQ E8
L1 NC1 VSSQ F9 L1 NC1 VSSQ F9 L1 NC1 VSSQ F9 L1 NC1 VSSQ F9
J9 NC2 VSSQ G1 J9 NC2 VSSQ G1 J9 NC2 VSSQ G1 J9 NC2 VSSQ G1
L9 NC3 VSSQ G9 L9 NC3 VSSQ G9 L9 NC3 VSSQ G9 L9 NC3 VSSQ G9
NC4 VSSQ NC4 VSSQ NC4 VSSQ NC4 VSSQ
INFINEON 96-BALL INFINEON 96-BALL INFINEON 96-BALL INFINEON 96-BALL
SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
SAM SUNG ( K4W2G1646C-HC12 ) SAM SUNG ( K4W2G1646C-HC12 ) SAM SUNG ( K4W2G1646C-HC12 ) SAM SUNG ( K4W2G1646C-HC12 )

B0_CLK R279 56R0402 B1_CLK R253 56R0402


14 VM B_DQA[63:0]
C484 C0.01u16X0402 C447 C0.01u16X0402
14 B_M A[13:0] 14 B_QSA[7:0]
1 B0_CLK# R281 56R0402 B1_CLK# R260 56R0402 1
14 B_BA[2:0] 14 B_QSA#[7:0]

14 B_DQM A[7:0]

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MICRO-STAR INT'L CO.,LTD.
T itle

Thames GPU(VRAM)
Size Docum ent Num ber Rev
C 0B
MS-14851
Date: Friday, Decem ber 02, 2011 Sheet 18 of 53
A B C D E
A B C D E

4
VDDR3 4

MVDDQ/VDDC/1.0_REG

1.8V_REG

VDDC_PWRG

3 3

BIF_VDDC

20ms max

PCIE_RST#
100ms

PCIE_CLK

2 2

1
MICRO-STAR INT'L CO.,LTD. 1

Title

Thames GPU(SEQUENCE)
https://vinafix.com
Size Document Number Rev
A 0B
MS-14851
Date: Friday, December 02, 2011 Sheet 19 of 53
A B C D E
1 2 3 4 5

CRT

2010/03/29 for EMI suggestion modify bead to indutor 120nH

16
VGA2
6
26 CRT_R_UMA L4 R_DVI 1 11
+5VRUN 0.12u300mA 7
L3 G_DVI 2 12 DDC_DATA
26 CRT_G_UMA
0.12u300mA 8
L2 B_DVI F2 3 13 HSYNC_R
26 CRT_B_UMA
0.12u300mA +5V_CRT 1 2 +5V_CRT_C 9
D2 R71 R70 R68 C111 C105 C96 C97 C104 C107 4 14 VSYNC_R
S-RB551V-30_SOD323 30Mil F-SMD1812P150TF-8-RH 10
1 +3VRUN 5 15 DDC_CLK 1

150R1%0402

150R1%0402

150R1%0402
+5V_CRT

X_C10p25N0402

X_C10p25N0402

X_C10p25N0402

X_C5.6p25N0402

X_C5.6p25N0402

X_C5.6p25N0402
VGAF_BLACK-RH-9

17
R69 R58
Q10 4.7KR0402 4.7KR0402
N-BSS138_SOT23 C386

G
C0.1u16Y0402
S D DDC_DATA
26 CRT_DATA_UMA
S D DDC_CLK
26 CRT_CLK_UMA
Q9 HSYNC_R

G
N-BSS138_SOT23
VSYNC_R

CI16 CI13 CI15 CI14

+3VRUN

X_C10p25N0402

X_C10p25N0402

X_C10p25N0402

X_C10p25N0402
R67 33R0402 CRT_HSYNC
26 CRT_HSYNC_UMA

R64 33R0402 CRT_VSYNC


26 CRT_VSYNC_UMA

2 2

J40

1 21
P1 P21
2 22
3
4
5
P2
P3
P4
P22
P23
P24
23
24
25
LVDSA_DATA2#
LVDSA_DATA2
26
26
LVDS
6 P5 P25 26
7 P6 P26 27
P7 P27 LVDSA_DATA1# 26
+3VRUN 8 28 LVDSA_DATA1 26
+3V_LCD_PANEL +3V_LCD_PANEL 9 P8 P28 29
3 P9 P29 3
10 30
26 LVDSA_CLK# P10 P30 LVDSA_DATA0# 26
U7 11 31
26 LVDSA_CLK P11 P31 LVDSA_DATA0 26
5 1 12 32
2 VIN VOUT 13 P12 P32 33 BL-ON
GND 33 BR-AD-ADJ P13 P33 40Mil +3VRUN
4 3 X_0R0402 R63 +3V_LCD_PANEL 14 34
26 LVDS_VDD_EN EN OCB 26 LVDS_DDC_CLK P14 P34
C90 C89 15 35
26 LVDS_DDC_DATA P15 P35
APL3511ABI 120Mil 16 36 20Mil +3V_CAMERA
P16 P36
X_C0.1u10X0402

C10u6.3X50805-1

SOT23_5_NPC30X 17 37
P17 P37 USB_P5N_C C94
PWR_INVTER 18 38
19 P18 P38 39 USB_P5P_C
P19 P39 C0.1u16Y0402
R66 100KR0402 20 40
PWR_SRC P20 P40
41 42 C397
+3VSUS GNDM1 GNDM2

2
+3VSUS
Hall Switch PWR_INVTER
JNC11
MEC1
MEC1 MEC2
MEC2 0.01U16X0402

X_0805 C384
C395 X_C0.1u16Y0402 R164 X_0.01U16X0402
N32-2200270-A81
1
10KR0402
5

C385 C91
VCC
33 LID# 1 A +3VSUS
Y 4 BL-ON 10U25X51206 C0.1u50Y BH2X20S-1PITCH_WHITE-RH-1
26 BLON 2 B
LID# 33 USB_P5N_C
GND U20 2 3
USB_P5N 27
R182
3

R184 NC7S08P5X_SC70-RH X_100KR0402 USB_P5P_C 1 4


X

USB_P5P 27
100KR0402
+3V_CAMERA +3VRUN L18
VDD

VOUT

X_CMC-L12-9008064-RH
X_C0.1u16Y0402

20Mil 20Mil
C351

GND

U15 D S

U19
Z

C389 C392 P-IRLML6402PBF_SOT23-3-RH


E-CMOS ( EC2648-B3-F ) X_C10u10Y0805 X_C0.1u10X0402
R183 15K 5%0402
CAMERA_ON# 33
4 4

C398

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LVDSA_DATA0 LVDSA_DATA1 LVDSA_DATA2 LVDSA_CLK C0.1u10X0402
X_180R0402

X_180R0402

X_180R0402

X_180R0402

4 1 4 1 4 1 4 1
RI3

RI4

RI5

RI2

3 2 3 2 3 2 3 2

LVDSA_DATA0# LVDSA_DATA1# LVDSA_DATA2# LVDSA_CLK#

LI4
X_CMC-L12-9008084-RH
LI5
X_CMC-L12-9008084-RH
LI6
X_CMC-L12-9008084-RH
LI2
X_CMC-L12-9008084-RH
MICRO-STAR INT'L CO.,LTD.
Title

CRT/LVDS
Size Document Number Rev
Custom 0B
MS-14851
Date: Friday, December 02, 2011 Sheet 20 of 53
1 2 3 4 5
A B C D E

HDMI connector
CN4
20
DPD_LANE2_P SHELL1
26 DPD_LANE2_P 1
R266 680R1%0402 DPD_LANE2_P DPD_LANE2_N D2+
26 DPD_LANE2_N 2 X1
4
R265 680R1%0402 DPD_LANE2_N D2 Shield GND 4
3
DPD_LANE1_P D2-
26 DPD_LANE1_P 4
R264 680R1%0402 DPD_LANE1_P DPD_LANE1_N D1+
26 DPD_LANE1_N 5
R262 680R1%0402 DPD_LANE1_N D1 Shield
6
DPD_LANE0_P D1-
26 DPD_LANE0_P 7
R267 680R1%0402 DPD_LANE0_P DPD_LANE0_N D0+
26 DPD_LANE0_N 8
R268 680R1%0402 DPD_LANE0_N D0 Shield
9
D0-
10
R258 680R1%0402 DPD_LANE3_P DPD_LANE3_P CK+
26 DPD_LANE3_P 11
R249 680R1%0402 DPD_LANE3_N DPD_LANE3_N CK Shield
26 DPD_LANE3_N 12
CK-
13

D
CE Remote
14
Q19 SCLDDC NC
+3VRUN G 15
N-2N7002_SOT23-1 SDADDC DDC CLK
16
F3 DDC DATA
17
S
GND
+5VRUN 1 2 18 X2
+5V GND
19
F-SMD1812P150TF-8-RH HP DET
21
EC40 SHELL2
3 HDMI19PM_BLACK-RH-1 3
X_C0.1u10X0402

R243 10KR0402
26 HDMI_HPD

R242
20K/4

Integrated pull-down resistor on HPD input


guarantees"input low" when no display is
plugged in.

+5VRUN

2 2

Y
D8 D7
Z SCLDDC Z SDADDC

X_BAV99LT1_SOT23 X_BAV99LT1_SOT23
+3VRUN

X
Q17
G

N-BSS138_SOT23
26 HDMI_SCL S D
+3VRUN
RN15
1 2 +5VRUN
3 4
5 6
+3VRUN 7 8

1 Q18 2.2KR 1
G

S
N-BSS138_SOT23
D
SCLDDC
SDADDC
MICRO-STAR INT'L CO.,LTD.
26 HDMI_SDA
Title

HDMI
Size Document Number Rev
Custom 0B
MS-14851
Date: Friday, December 02, 2011 Sheet 21 of 53
A B C D E

https://vinafix.com
A B C D E

34
CON4

18
FPC32P-B-0.5PITCH_WHITE-RH
+3VRUN 32
31 CON3
30 +5VRUN 16 FPC16P-B-0.5PITCH_WHITE-RH
+5VSUS 29 15
+5VSUS
28 14
27 33 TP_DATA TP_DATA 13
1 TP_CLK 1
26 33 TP_CLK 12
25 LED_HDD# 11
23,24 LED_HDD#
GND 24 LED_BATLOW# 10
33 LED_BATLOW#
27 USB_P8P 23 9
CARD READER 22 LED_CAP# 8
27 USB_P8N 33 LED_CAP#
GND 21 LED_WLAN# 7
33 LED_WLAN#
27 USB_P3P 20 33 LED_BLUETOOTH# LED_BLUETOOTH# 6
USB 2.0 PORT 4 19 LED_ACPI# 5
27 USB_P3N 33 LED_ACPI#
GND 18 LED_CHARGE# 4
33 LED_CHARGE#
27 USB_P2P 17 33 LED_NUM# LED_NUM# 3
USB 2.0 PORT 3 27 USB_P2N 16 2
GND 15 1
+5VALW
14
13
GND 12

17
AGND 11
FRONT_JD# 10
37 FRONT_JD# DEPOP_R
37 DEPOP_R 9
DEPOP_L 8
37 DEPOP_L
AGND 7
MIC_JD# 6
37 MIC_JD# MIC1_VREFO_L
37 MIC1_VREFO_L 5
MIC1_VREFO_R 4
37 MIC1_VREFO_R
MIC1_R 3
37 MIC1_R
MIC1_L 2
37 MIC1_L
1 TP_DATA CI11 X_C10p50N0402
AGND
TP_CLK CI12 X_C10p50N0402

LED_HDD# CI9 X_C1000p50N0402

33
2 LED_BLUETOOTH# CI5 X_C1000p50N0402 2

LED_WLAN# CI6 X_C1000p50N0402

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LED_ACPI# CI4 X_C1000p50N0402

LED_BATLOW# CI8 X_C1000p50N0402

LED_CHARGE# CI3 X_C1000p50N0402

LED_CAP# CI7 X_C1000p50N0402

LED_NUM# CI2 X_C1000p50N0402


+3VALW

CON2

R80
10KR0402 16

+3VALW 14
PWR_SW# JNC25 2 1 PWR_SW#JNC 13
33 PWR_SW#
Turbo_SW# JNC24 2 1 Turbo_SW#JNC 12
33 Turbo_SW#
Device key_SW# JNC23 2 1 Device key_SW#JNC 11
33 Device key_SW#
Cinema Pro_SW# JNC22 2 1 Cinema Pro_SW#JNC 10
33 Cinema Pro_SW#
33 Display_SW# Display_SW# JNC20 2 1 Display_SW#JNC 9
ODD_EJECT_SW# JNC21 2 1 ODD_EJECT_SW#JNC 8
33 ODD_EJECT_SW#
PWR_LED#
7
6 +3VRUN
TP-OFF SW &LED
3 33 PWR_LED# 3
33 LED_Device key# 5
LED_Cinema Pro# 4
33 LED_Cinema Pro#
LED_Turbo# 3
33 LED_Turbo#
2
R73 SW2
+5VRUN 1
X_10KR0402 SW-TACTS-RH-2
15 33 TP-OFF_SW# 1 1 3
3

2 2 4
4
FPC14P-T-0.5PITCH_WHITE-RH

5
CI10
X_C1000p50N0402

PWR_SW# CI21 X_C1000p50N0402


Turbo_SW# CI20 X_C1000p50N0402
Device key_SW# CI23 X_C1000p50N0402
Cinema Pro_SW# CI22 X_C1000p50N0402
Display_SW# CI19 X_C1000p50N0402
ODD_EJECT_SW# CI24 X_C1000p50N0402 D3
LED_Cinema Pro# CI29 X_C1000p50N0402 R72 220R 1 2
+5VRUN LED_TP-OFF 33
LED_Turbo# CI28 X_C1000p50N0402

LED04-G-30mA2.4V_20125-RH
orange
Reserve for EMI request

4 4

https://vinafix.com Title

Size
Custom
BTB CONN
Document Number

MS-14851
MICRO-STAR INT'L CO.,LTD.

Rev
0B

Date: Friday, December 02, 2011 Sheet 22 of 53


A B C D E
A B C D E

PANTHER POINT (HDA,JTAG,SATA)


+3VALW

D6
S-BAT54C_SOT23

Y
RTCVCC

Z R105 20KR0402

X_C10u6.3X50805
C489 C428 C170 C436 C22p50N0402 RTCX1JNC

X
C1u6.3Y0402-RH
1 1

C1u6.3Y0402-RH
RTC_P2

2
RTCVCC Y5 R227
32.768KHZ12.5p_S-RH-2 10MR1%0402
R228

1
1KR0402 R108
1MR0402
C433 C22p50N0402 RTCX2JNC U23A
RTC_P3
R119 20KR0402
A20 C38 LAD0 33
RTCX1 FWH0 / LAD0
A38 LAD1 33
C206 FWH1 / LAD1
C20 B37

LPC
RTCX2 FWH2 / LAD2 LAD2 33
1

BAT2 C1u6.3Y0402-RH C37


FWH3 / LAD3 LAD3 33
RTCRST# D20
RTCRST#
MEC1 MEC2 D36
SRTCRST# FWH4 / LFRAME# LPC_FRAME# 33
G22
SRTCRST#
E36 L_LDRQ0# 33
BAT2PS_BLACK-RH-1 SM_INTRUDER# LDRQ0#
K22 K36

RTC
BAT3 N91-02F0060-L06 INTRUDER# LDRQ1# / GPIO23
2

BAT-BCR2032P-RH BATHOLD_S2_2 RTCVCC R223 330KR0402 PCH_INTVRMEN C17 V5


INTVRMEN SERIRQ INT_SERIRQ 24,33
Strap: Integrated 1.05 V VRMs is enabled when high
NOTE: This signal should always be pulled high AM3
SATA0RXN SATA0RXN 36
HDA_BIT_CLK_PCH_R N34 AM1
HDA_BCLK SATA0RXP SATA0RXP 36
AP7 HDD

SATA 6G
HDA_SYNC_PCH_R SATA0TXN SATA0TXN 36
L34 AP5 SATA0TXP 36
HDA_SYNC SATA0TXP
TP3 T10 AM10
SPKR SATA1RXN SATA1RXN 36
SATA1RXP
AM8 SATA1RXP 36 ODD
HDA_RST#_PCH_R K34 AP11
HDA_RST# SATA1TXN SATA1TXN 36
AP10
SATA1TXP SATA1TXP 36
2 RN13 2
37 CODEC_HDA_SDIN0 E34 AD7
HDA_SDIN0 SATA2RXN
1 2 AD5
37 CODEC_HDA_RST# +3VSUS SATA2RXP
3 4 G34 AH5
37 CODEC_HDA_BIT_CLK HDA_SDIN1 SATA2TXN
5 6 AH4
37 CODEC_HDA_SYNC SATA2TXP
7 8 C34
37 CODEC_HDA_SDOUT HDA_SDIN2
AB8
SATA3RXN
X_C10p50N0402

IHDA
8P4R-33R0402 R244 A34 AB10
HDA_SDIN3 SATA3RXP
CI25

X_1KR0402 AF3
SATA3TXN
AF1
HDA_SDOUT_PCH_R A36 SATA3TXP
HDA_SDO
EMI reserved Y7

SATA
R241 1KR0402 SATA4RXN
33 FLASH_SECURITY Y5
HDA_DOCK_EN C36 SATA4RXP AD3
HDA_DOCK_EN# / GPIO33 SATA4TXN
AD1
TPJNC75 N32 SATA4TXP
HDA_DOCK_RST# / GPIO13
Flash Descriptor effect Y3
SATA5RXN
Y1
SATA5RXP AB3
TPJNC63 SATA5TXN
Low = Enable J3 AB1
HDA_SDO JTAG_TCK SATA5TXP +VTT
High = Disable TPJNC18 H7 Y11
JTAG_TMS SATAICOMPO
GPIO28 作为On Die PLL VR的 Enable PIN。

JTAG
+3VSUS SATAICOMP
HDA_SYNC 为电压设定PIN。 TPJNC17 K5
JTAG_TDI SATAICOMPI
Y10 R94 37.4R1%0402

TPJNC60 H1
JTAG_TDO
AB12
R246 SATA3RCOMPO
X_1KR0402 AB13 SATA3COMP R97 49.9R1%0402
SATA3COMPI
HDA_SYNC_PCH_R
SPI_CLK R194 SPI_CLKR T3 AH1 PCH_SATABIAS R193 750R1%0402
SPI_CLK SATA3RBIAS
3 SPI_CS0# 3
Y14
EC39 SPI_CS0#
Checklist Page37: Needs to be pulled high for CR X_C10p50N0402 TPJNC62 T1
SPI_CS1# P3

SPI
SATALED# LED_HDD# 22,24

Low = On Die PLL VR is supplied by 1.8V SPI_MOSI V4 V14 R79 X_10KR0402


SPI_MOSI SATA0GP / GPIO21 +3VRUN
HDA_SYNC High = On Die PLL VR is supplied by 1.5V SPI_MISO U3 P1 BBS_BIT0 R188 X_10KR0402
SPI_MISO SATA1GP / GPIO19 +3VRUN
This signal has a weak internal pull-down.

CPT_PPT_Rev_0p5 R195
X_1KR0402 BBS_BIT0--BIIOS BOOT STRAP BIT0
This Signal has a weak internal pull-up

BIOS1

+3VRUN +3VRUN +3VRUN


X_WINBOND-W25Q32BVSSIG

C417 X_C0.1u16Y0402
R185
3.3KR0402 R192
3.3KR0402

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SPI_CS0# 1 8
SPI_MISO 2 CS VCC 7 SPI_HOLD#_B
DO HLOD SPI_CLK
3 6
4
4 WP CLK 5 SPI_MOSI 4
GND DI

U22
SPI FLASH-8P_BLACK-RH
M31-25Q3203-W03
SIC8_SST_S2A
MICRO-STAR INT'L CO.,LTD.
Title

PANTHER POIN (HDA/JTAG/SATA)


Size Document Number Rev
Custom 0B
MS-14851
Date: Friday, December 02, 2011 Sheet 23 of 53
A B C D E
A B C D E

PANTHER POINT (PCI-E,SMBUS,CLK) +3VSUS

U23B
DRAMRST_CNTRL_PCH R95 1KR1%0402 SUS_SMBCLK
35 PCIE_MINI_RXN BG34
PERN1 PCH_GPIO11 SUS_SMBDATA
35 PCIE_MINI_RXP BJ34 E12
C21 C0.1u10X0402 PETN1 AV32 PERP1 SMBALERT# / GPIO11
1 35 PCIE_MINI_TXN PETN1 1
C25 C0.1u10X0402 PETP1 AU32 H14 SUS_SMBCLK Q14
35 PCIE_MINI_TXP PETP1 SMBCLK RN5 NN-2N7002DW-7-F_SOT363-6-RH

D2

D1
BE34 C9 SUS_SMBDATA SML0_CLK 1 2
BF34 PERN2 SMBDATA SML0_DATA 3 4
BB32 PERP2 SML1_CLK 5 6 +3VRUN
PETN2 SML1_DATA
AY32 7 8

SMBUS
PETP2 A12 DRAMRST_CNTRL_PCH
BG36 SML0ALERT# / GPIO60 DRAMRST_CNTRL_PCH 5,8 8P4R-2.2K0402
PERN3 SML0_CLK
BJ36 C8

G2
S2
G1
S1
AV34 PERP3 SML0CLK
AU34 PETN3 G12 SML0_DATA
PETP3 SML0DATA
SMB_CLK_DIMM 11,12
BF36 SMLINK0 for PHY +3VRUN +3VSUS
34 PCIE_GLAN_RXN PERN4
BE36
34 PCIE_GLAN_RXP PETN4 PERP4 PCH_GPIO74 SMB_DATA_DIMM 11,12
C289 C0.1u10X0402 AY34 C13 RN4
34 PCIE_GLAN_TXN C282 C0.1u10X0402 PETP4 PETN4 SML1ALERT# / PCHHOT# / GPIO74 SMB_CLK_DIMM
BB34 1 2
34 PCIE_GLAN_TXP PETP4 E14 SML1_CLK SMB_DATA_DIMM 3 4

PCI-E*
BG37 SML1CLK / GPIO58 SUS_SMBCLK 5 6
PERN5 SML1_DATA SUS_SMBDATA
BH37 M16 7 8
AY36 PERP5 SML1DATA / GPIO75
BB36 PETN5 8P4R-2.2K0402 SML1_CLK
PETP5
BJ38 SML1_DATA
BG38 PERN6

Controller
AU36 PERP6 M7 Q11
PETN6 CL_CLK1 X_NN-2N7002DW-7-F_SOT363-6-RH
AV36
PETP6

D2

D1
Link
BG40 T11 +3VRUN
PERN7 CL_DATA1 +3VRUN +3VSUS +3VRUN
BJ40
AY40 PERP7
BB40 PETN7 P10
2 PETP7 CL_RST1# 2

BE38 R82 R83

G2
S2
G1
S1
BC38 PERN8 R101 R75 2.2KR0402 2.2KR0402
AW38 PERP8
[Fuqun] CLKREQ#1/2 : RUN PETN8 X_10KR0402 10KR0402
AY38 SMB_CLK_EC 33
Other CLKREQ#: SUS PETP8
M10
PEG_A_CLKRQ# / GPIO47 GPU_CLKREQ# 15 SMB_DATA_EC 33
Y40
35 CLK_PCIE_MINI# Y39 CLKOUT_PCIE0N
35 CLK_PCIE_MINI CLKOUT_PCIE0P AB37
CLKOUT_PEG_A_N GFX_REFCLK# 13

CLOCKS
R199 X_10KR0402 J2 AB38 R84
PCIECLKRQ0# / GPIO73 CLKOUT_PEG_A_P GFX_REFCLK 13
X_10KR0402
AB49 AV22
CLKOUT_PCIE1N CLKOUT_DMI_N CLK_EXP# 5
PCIe devices or addin cards that do NOT support CLKREQ# functionality should not AB47 AU22
CLKOUT_PCIE1P CLKOUT_DMI_P CLK_EXP 5
route this signal to PCH. In this case, Intel recommends terminating PCIECLKRQx#
pin on PCH with 10 k? ±10% external pull-up resistor instead of No Connect. M1
PCIECLKRQ1# / GPIO18
Appropriate Intel ME Fireware controls should be used to disable the CLKREQ# AM12 For designs not using eDP, CLKIN_DP
CLKOUT_DP_N AM13
feature and enable a free-running SRC clock to the PCIe devices or addin cards. CLKOUT_DP_P can leave as No Connect
AA48
(Refer to latest version of Fireware Bring-Up Guide for default AA47 CLKOUT_PCIE2N RN6
settings and details on CLKREQ# registers). CLKOUT_PCIE2P
BF18 2 1
V10 CLKIN_DMI_N BE18 4 3 +3VRUN
PCIECLKRQ2# / GPIO20 CLKIN_DMI_P 6 5
8 7
Y37 BJ30 RN3
34 CLK_PCIE_LAN# Y36 CLKOUT_PCIE3N CLKIN_GND1_N BG30 8P4R-10KR0402 CLKIN_SATA_N 2 1
34 CLK_PCIE_LAN CLKOUT_PCIE3P CLKIN_GND1_P CLKIN_SATA_P 4 3
A8 RN8 +3VSUS 6 5
34 CLK_GLAN_REQ# PCIECLKRQ3# / GPIO25 23,33 INT_SERIRQ
G24 2 1 8 7
CLKIN_DOT_96N 22,23 LED_HDD#
E24 4 3
3 CLKIN_DOT_96P PCH_GPIO74 8P4R-10KR0402 3
Y43 6 5
Y45 CLKOUT_PCIE4N CPT_PPT_Rev_0p5 PCH_GPIO11 8 7
CLKOUT_PCIE4P AK7 CLKIN_SATA_N 8P4R-10KR0402
CLKIN_SATA_N
L12 AK5 CLKIN_SATA_P
PCIECLKRQ4# / GPIO26 CLKIN_SATA_P C451 C18p50N0402

V45 K45 R145 10KR0402


V46 CLKOUT_PCIE5N REFCLK14IN

1
CLKOUT_PCIE5P
L14 H45 R251 X2
PCIECLKRQ5# / GPIO44 CLKIN_PCILOOPBACK CLK_PCI_FB 27
1MR1%0402 25MHZ20p_S-RH-2

2
AB42 V47 XTAL25_IN
CLKOUT_PEG_B_N XTAL25_IN XTAL25_OUT
AB40 V49
CLKOUT_PEG_B_P XTAL25_OUT C452 C18p50N0402
E6
PEG_B_CLKRQ# / GPIO56
Y47 XCLK_RCOMP R250 90.9R1%0402 +VTT
V40 XCLK_RCOMP
V42 CLKOUT_PCIE6N
CLKOUT_PCIE6P
[Fuqun] VccDIFFCLKN power
T13
PCIECLKRQ6# / GPIO45
V38 K43
CLKOUT_PCIE7N CLKOUTFLEX0 / GPIO64
FLEX CLOCKS

V37
CLKOUT_PCIE7P F47 TPJNC76
CLKOUTFLEX1 / GPIO65
K12
PCIECLKRQ7# / GPIO46 H47 TP_CLK_FLEX2JNC TPJNC78
AK14 CLKOUTFLEX2 / GPIO66
AK13 CLKOUT_ITPXDP_N K49
CLKOUT_ITPXDP_P CLKOUTFLEX3 / GPIO67
4 4

Intel Comments:
If CLKREQ# control is not needed, say for a free running clock, DO NOT pull-down signal to GND. This will increase leakage in Sx states.
PCIe devices or addin cards that do NOT support CLKREQ# functionality should not route this signal to PCH.
Intel recommends terminating PCIECLKRQx# pin on PCH with 10 k ∮10% external pull-up resistor instead of MICRO-STAR INT'L CO.,LTD.
No Connect.
Only PCIECLKRQ[2:1]# on PCH are core well powered. All other PCIECLKRQx# are suspend well powered. Title

PANTHER POI(PCI-E/SMBUS/CLK)
Size Document Number Rev
Custom 0B
MS-14851
Date: Friday, December 02, 2011 Sheet 24 of 53
A B C D E

https://vinafix.com
A B C D E

PANTHER POINT (DMI,FDI,GPIO)


U23C
1 1
BC24 BJ14
5 DMI_RXN0 DMI0RXN FDI_RXN0 FDI_TXN0 5
5 DMI_RXN1 BE20 AY14 FDI_TXN1 5
DMI1RXN FDI_RXN1
5 DMI_RXN2 BG18 BE14 FDI_TXN2 5
BG20 DMI2RXN FDI_RXN2 BH13
5 DMI_RXN3 DMI3RXN FDI_RXN3 FDI_TXN3 5
BC12 FDI_TXN4 5
FDI_RXN4
5 DMI_RXP0 BE24 BJ12 FDI_TXN5 5
BC20 DMI0RXP FDI_RXN5 BG10
5 DMI_RXP1 DMI1RXP FDI_RXN6 FDI_TXN6 5
BJ18 BG9
5 DMI_RXP2 DMI2RXP FDI_RXN7 FDI_TXN7 5
5 DMI_RXP3 BJ20
DMI3RXP
BG14 FDI_TXP0 5
FDI_RXP0
5 DMI_TXN0
AW24 BB14 FDI_TXP1 5
DMI0TXN FDI_RXP1
5 DMI_TXN1 AW20 BF14 FDI_TXP2 5
DMI1TXN FDI_RXP2
5 DMI_TXN2 BB18 BG13 FDI_TXP3 5
DMI2TXN FDI_RXP3
AV18 BE12

DMI
FDI
5 DMI_TXN3 DMI3TXN FDI_RXP4 FDI_TXP4 5
BG12 FDI_TXP5 5
+VTT FDI_RXP5
5 DMI_TXP0 AY24 BJ10 FDI_TXP6 5
DMI0TXP FDI_RXP6
5 DMI_TXP1 AY20 BH9 FDI_TXP7 5
DMI1TXP FDI_RXP7
5 DMI_TXP2
AY18
DMI2TXP
5 DMI_TXP3 AU18
DMI3TXP
AW16 FDI_INT 5
R232 FDI_INT
49.9R1%0402 BJ24 AV12
DMI_ZCOMP FDI_FSYNC0 FDI_FSYNC0 5
DMI_COMP_R BG25 BC10
2 DMI_IRCOMP FDI_FSYNC1 FDI_FSYNC1 5 2

BH21 AV14 FDI_LSYNC0 5


R229 750R1%0402 DMI2RBIAS FDI_LSYNC0
BB10 FDI_LSYNC1 5 DSWODVREN - On Die DSW VR Enable
FDI_LSYNC1 RTCVCC
High --- Enable internal 1.05V regulator
A18 DSWVRMEN R220 330KR0402-1 Low --- Disable
DSWVRMEN

System Power Management


TPJNC28 SUSACK# C12 E22 DPWROK
SUSACK# DPWROK RSMRST# 33
Without deep s4/s5 support tied together with RSMRST#
PM_SYSRST# K3 B9
SYS_RESET# WAKE# PCIE_WAKE# 34,35

SYS_PWROK P12 N3 PM_CLKRUN# R189 X_0R0402


44 SYS_PWROK SYS_PWROK CLKRUN# / GPIO32 EC_CLKRUN# 33
R78 X_10KR0402
33,44 EC_PCH_PWROK L22 G8
PWROK SUS_STAT# / GPIO61
For platforms not supporting Intel AMT
it can be connected to PWROK. L10 N14
APWROK SUSCLK / GPIO62 SUSCLK 33
3 3
B13 D10 TPJNC33
5 PM_DRAM_PWRGD DRAMPWROK SLP_S5# / GPIO63

33 RSMRST# C21 H4 PM_SLP_S4# 33


RSMRST# SLP_S4#
+3VSUS
SUSPWRACK K16 F4 check list 1.0 remove SUSPWRACK pull up resistor
33 SUSPWRACK SUSWARN#/SUSPWRDNACK/GPIO30 SLP_S3# PM_SLP_S3# 33
SUSPWRACK R96 X_10KR0402
33 PM_PWRBTN# E20 G10
PWRBTN# SLP_A# AC_PRESENT R100 10KR0402

AC_PRESENT H20 G16 PM_RI# R213 10KR0402


ACPRESENT / GPIO31 SLP_SUS#
PM_BATLOW# R85 8.2KR5%
PM_BATLOW# E10 AP14
BATLOW# / GPIO72 PMSYNCH H_PM_SYNC 5
PCIE_WAKE# R209 1KR0402
CPT_PPT_Rev_0p5
PM_RI# A10 K14 TPJNC29 +3VRUN
RI# SLP_LAN# / GPIO29

PM_CLKRUN# R196 8.2KR0402

PM_SYSRST# R197 10KR0402


4 4

MICRO-STAR INT'L CO.,LTD.


Title

PANTHER POINT (DMI/FDI/GPIO)


Size Document Number Rev
Custom 0B
MS-14851
Date: Friday, December 02, 2011 Sheet 25 of 53
A B C D E

https://vinafix.com
A B C D E

PANTHER POINT (LVDS,DDI)


U23D

20 BLON J47 AP43


L_BKLTEN SDVO_TVCLKINN
1
20 LVDS_VDD_EN M45 AP45 1
L_VDD_EN SDVO_TVCLKINP
TPJNC54 P45 AM42
L_BKLTCTL SDVO_STALLN
AM40
SDVO_STALLP
20 LVDS_DDC_CLK T40
L_DDC_CLK
20 LVDS_DDC_DATA K47 AP39
L_DDC_DATA SDVO_INTN
AP40
TPJNC56 SDVO_INTP
T45
TPJNC53 L_CTRL_CLK
P39
L_CTRL_DATA
TP_LVDS_IBG AF37 P38
LVD_IBG SDVO_CTRLCLK
AF36 M39
LVD_VBG SDVO_CTRLDATA
R136 AE48
LVD_VREFH
2.37KR1%0402-RH AE47 AT49
LVD_VREFL DDPB_AUXN
AT47
DDPB_AUXP
AT40
DDPB_HPD
AK39

LVDS
20 LVDSA_CLK# LVDSA_CLK#
20 LVDSA_CLK AK40 AV42
LVDSA_CLK DDPB_0N
AV40
DDPB_0P
20 LVDSA_DATA0# AN48 AV45
LVDSA_DATA#0 DDPB_1N
20 LVDSA_DATA1# AM47 AV46
LVDSA_DATA#1

Digital Display Interface


DDPB_1P
20 LVDSA_DATA2# AK47 AU48
LVDSA_DATA#2 DDPB_2N
AJ48 AU47
+3VRUN LVDSA_DATA#3 DDPB_2P
AV47
2 DDPB_3N 2
20 LVDSA_DATA0 AN47 AV49
LVDSA_DATA0 DDPB_3P
20 LVDSA_DATA1 AM49
LVDSA_DATA1
20 LVDSA_DATA2 AK49
LVDSA_DATA2
AJ47 P46
RN11 LVDSA_DATA3 DDPC_CTRLCLK
P42
LVDS_DDC_CLK DDPC_CTRLDATA
1 2
3 4 LVDS_DDC_DATA AF40
CRT_CLK_UMA LVDSB_CLK#
5 6 AF39 AP47
CRT_DATA_UMA LVDSB_CLK DDPC_AUXN
7 8 AP49
DDPC_AUXP
AH45 AT38
8P4R-2.2K0402 LVDSB_DATA#0 DDPC_HPD
AH47
LVDSB_DATA#1
AF49 AY47
LVDSB_DATA#2 DDPC_0N
AF45 AY49
LVDSB_DATA#3 DDPC_0P
AY43
DDPC_1N
AH43 AY45
LVDSB_DATA0 DDPC_1P
AH49 BA47
LVDSB_DATA1 DDPC_2N
AF47 BA48
LVDSB_DATA2 DDPC_2P
AF43 BB47
LVDSB_DATA3 DDPC_3N
BB49
DDPC_3P

20 CRT_B_UMA N48 M43 HDMI_SCL 21


CRT_BLUE DDPD_CTRLCLK
20 CRT_G_UMA P49 M36 HDMI_SDA 21
CRT_GREEN DDPD_CTRLDATA
20 CRT_R_UMA T49
3
CRT_RED 3
AT45

CRT
DDPD_AUXN
20 CRT_CLK_UMA T39 AT43
CRT_DDC_CLK DDPD_AUXP
20 CRT_DATA_UMA M40 BH41 HDMI_HPD 21
CRT_DDC_DATA DDPD_HPD
BB43 DPD_LANE0_N_C C0.1u10X0402 C458
DDPD_0N DPD_LANE2_N 21
ER3 HSYNC M47 BB45 DPD_LANE0_P_C C0.1u10X0402 C459 R245
20 CRT_HSYNC_UMA CRT_HSYNC DDPD_0P DPD_LANE2_P 21
ER4 VSYNC M49 BF44 DPD_LANE1_N_C C0.1u10X0402 C453 X_110KR1%0402-RH
20 CRT_VSYNC_UMA CRT_VSYNC DDPD_1N DPD_LANE1_N 21
BE44 DPD_LANE1_P_C C0.1u10X0402 C456
DDPD_1P DPD_LANE1_P 21
BF42 DPD_LANE2_N_C C0.1u10X0402 C462
DDPD_2N DPD_LANE0_N 21
DAC_IREF_R T43 BE42 DPD_LANE2_P_C C0.1u10X0402 C460
DAC_IREF DDPD_2P DPD_LANE0_P 21
T42 BJ42 DPD_LANE3_N_C C0.1u10X0402 C444
CRT_IRTN DDPD_3N DPD_LANE3_N 21
R142 BG42 DPD_LANE3_P_C C0.1u10X0402 C450
DDPD_3P DPD_LANE3_P 21
1KR1%0402

CPT_PPT_Rev_0p5

CRT_B_UMA R256 150R1%0402

CRT_G_UMA R255 150R1%0402

CRT_R_UMA R254 150R1%0402

4 4

MICRO-STAR INT'L CO.,LTD.


Title

PANTHER POINT (LVDS/DDI)


Size Document Number Rev
Custom 0B
MS-14851
Date: Friday, December 02, 2011 Sheet 26 of 53
A B C D E

https://vinafix.com
A B C D E

PANTHER POINT (PCI,USB,NVRAM)


+3VSUS

+3VRUN U23E C92 X_C0.1u10X0402


AY7
RSVD1
AV7

5
1 RN9 BG26 RSVD2 AU3 U8 1
INT_PIRQA# 1 2 BJ26 TP1 RSVD3 BG4 DGPU_HOLD_RST# 1 VCC
A
INT_PIRQD# TP2 RSVD4
3 4 BH25 4 PEG_RST# 13
INT_PIRQB# 5 6 BJ16 TP3 AT10 2
Y
B
INT_PIRQC# TP4 RSVD5
7 8 BG16 BC8 GND
AH38 TP5 RSVD6 S08P5X_SC70

3
8P4R-8.2KR0402 AH37 TP6 AU2
TP7 RSVD7
AK43 AT4
RN10 AK45 TP8 RSVD8 AT3
INT_PIRQH# TP9 RSVD9
1 2 C18 AT1
INT_PIRQE# 3 4 N30 TP10 RSVD10 AY3
ODD_INT_PIRQF# 5 6 H3 TP11 RSVD11 AT5
ODD_PWR_ON# TP12 RSVD12
7 8 AH12 AV3
AM4 TP13 RSVD13 AV1
8P4R-8.2KR0402 TP14 RSVD14
AM5 BB1
RN14 Y13 TP15 RSVD15 BA3 +3VSUS
1 2 K24 TP16 RSVD16 BB5
DGPU_SELECT# TP17 RSVD17 C93 X_C0.1u10X0402
3 4 L24 BB3
DGPU_PWR_EN# 5 6 AB46 TP18 RSVD18 BB7

5
DGPU_HOLD_RST# 7 TP19 RSVD19 U9
8 AB45 BE8
TP20 RSVD20 BD4 PLT_RST# 1 VCC

RSVD
A
8P4R-8.2KR0402 RSVD21 BF6 4 R61
RSVD22 Y WLAN_RST# 35
2 B R59
LPC_RST# 33
B21 AV5 GND R62
TP21 RSVD23 LAN_RST# 34
M20 AV10 X_S08P5X_SC70 R60
BUF_PTL_RST# 5

3
AY16 TP22 RSVD24
BG46 TP23 AT8
TP24 RSVD25
2 AY5 2
RSVD26 R65
BA2
A16 swap override Strap/Top-Block BE28 RSVD27
32 USB3_RX1N *USB3Rn1
Swap Override jumper 32 USB3_RX2N BC30 AT12
*USB3Rn2 RSVD28
BE32 BF3
BJ32 *USB3Rn3 RSVD29
Low = A16 swap *USB3Rn4
32 USB3_RX1P BC28
GNT#3 override/Top-Block BE30 *USB3Rp1
32 USB3_RX2P *USB3Rp2
Swap Override enabled BF32
*USB3Rp3
High = Default BG32 C24 USB_P0N 32
*USB3Rp4 USBP0N
32 USB3_TX1N
AV26
*USB3Tn1 USBP0P
A24 USB_P0P 32 USB 3.0 PORT 1
BB26 C25 USB_P1N 32
32 USB3_TX2N *USB3Tn2 USBP1N
AU28
*USB3Tn3 USBP1P
B25 USB_P1P 32 USB 3.0 PORT 2
Boot BIOS Strap AY30 C26
*USB3Tn4 USBP2N USB_P2N 22
BBS_BIT1 BBS_BIT0
32 USB3_TX1P
AU26 A26 USB_P2P 22
USB 2.0 PORT 3
Boot BIOS Location AY26 *USB3Tp1 USBP2P K28
32 USB3_TX2P *USB3Tp2 USBP3N USB_P3N 22
GPIO51 GPIO19 AV28 H28 USB_P3P 22 USB 2.0 PORT 4
*USB3Tp3 USBP3P
0 0 LPC AW30
*USB3Tp4 USBP4N
E28 USB_P4N 36
USBP4P
D28 USB_P4P 36 3870 BT
0 1 Reserved USBP5N
C28 USB_P5N 20
USBP5P
A28 USB_P5P 20 WEBCAM
1 0 PCI USBP6N
C29
B29
INT_PIRQA# USBP6P
1 1 SPI K40
PIRQA# USBP7N
N28 ports 6&7 are noneffective ports for HM76
INT_PIRQB# K38 M28
INT_PIRQC# H38 PIRQB# USBP7P L30
PCI
PIRQC# USBP8N USB_P8N 22
INT_PIRQD# G38 K30 USB_P8P 22 CardReader
PIRQD# USBP8P G30
3 DGPU_HOLD_RST# USBP9N USB_P9N 36 3
C46
REQ1# / GPIO50 USBP9P
E30 USB_P9P 36 3870 WLAN
DGPU_SELECT# C44 C30
USB
REQ2# / GPIO52 USBP10N USB_P10N 35
45 DGPU_PWR_EN#
E40
REQ3# / GPIO54 USBP10P
A30 USB_P10P 35 MINI PCIE SLOT
L32
BBS_BIT1 D47 USBP11N K32
TPJNC55 DGPU_PWM_SEL E42 GNT1# / GPIO51 USBP11P G32
GNT#3 GNT2# / GPIO53 USBP12N
F46 E32
R247 R248 X_1KR0402 GNT3# / GPIO55 USBP12P C32
USBP13N
X_1KR0402 A32
INT_PIRQE# G42 CPT_PPT_Rev_0p5 USBP13P
G40 PIRQE# / GPIO2
33,36 ODD_INT_PIRQF# ODD_PWR_ON# PIRQF# / GPIO3 USB_BIAS
36 ODD_PWR_ON# C42 C33
INT_PIRQH# D44 PIRQG# / GPIO4 USBRBIAS#
PIRQH# / GPIO5
B33 R240
TPJNC25 PCI_PME#JNC K10 USBRBIAS 22.6R1%0402
PME#
PLT_RST# C6 A14
PLTRST# OC0# / GPIO59
K20
OC1# / GPIO40 B17
H49 OC2# / GPIO41 C16 +3VSUS
R140 22R0402 CLKOUT_PCI1 CLKOUT_PCI0 OC3# / GPIO42
H43 L16
24 CLK_PCI_FB R257 22R0402 CLKOUT_PCI2 CLKOUT_PCI1 OC4# / GPIO43
J48 A16
33 CLK_PCI_KBC CLKOUT_PCI2 OC5# / GPIO9
R252 22R0402 CLKOUT_PCI3 K42 D14
33 CLK_PCIF_PORT80 CLKOUT_PCI3 OC6# / GPIO10 R217 X_10KR0402
H40 C14
CLKOUT_PCI4 OC7# / GPIO14
X_C10p50N0402

X_C10p50N0402

X_C10p50N0402
CI17

CI27

CI26

4 4

MICRO-STAR INT'L CO.,LTD.


EMI reserved Title

PANTHER POIN (PCI/USB/NVRAM)


Size Docum ent Num ber Rev
Cus tom 0B
MS-14851
Date: Friday, Decem ber 02, 2011 Sheet 27 of 53

A B C D E

https://vinafix.com
A B C D E

PANTHER POINT (GPIO,VSS_NCTF,RSVD)


U23F

1 TPJNC16 PCH_GPIO0 T7 C40 1


internal pull up BMBUSY# / GPIO0 TACH4 / GPIO68
A42 B41
33 KBSMI# TACH1 / GPIO1 TACH5 / GPIO69
TPJNC52 PCH_GPIO6 H36 C41
TACH2 / GPIO6 TACH6 / GPIO70
PLL ON DIE VR_ENABLE internal pull up DMI & FDI Termination Voltage
33 KBSCI# E38 A40
TACH3 / GPIO7 TACH7 / GPIO71
Internal pull high (Enable) TPJNC71 ICC_EN# C10 Set to VSS when LOW Sandy Bridge
GPIO8
GPIO28 NV_CLE
TPJNC19 PCH_GPIO12 C4
Low: Disable LAN_PHY_PWR_CTRL / GPIO12 Set to VCC when High Ivy Bridge
R200 X_10KR0402 TLSEN G2 P4
+3VSUS GPIO15 A20GATE H_A20GATE 33
AU16 R98 X_0R0402 [Fuqun] VccDFTERM power
PECI H_PECI 5,33
TPJNC67 JTAG_SATA4GP U2
SATA4GP / GPIO16
P5 KBRST# 33
RCIN# +1_8VRUN
D40 AY11

GPIO
15,33,45 DGPU_PWRGD TACH0 / GPIO17 PROCPWRGD H_CPUPWRGD 5

CPU/MISC
TPJNC13 BIOS_REC T5 AY10 PCH_THRMTRIP#_R R92 390R0402_1%
+3VSUS SCLOCK / GPIO22 THRMTRIP# H_THRMTRIP# 5
R191
TPJNC68 HOST_ALERT#2 E8 T14 2.2KR0402
*GPIO24 INIT3_3V#
R76 TPJNC35 DSW wake up event E16 AY1 NV_CLE R198 1KR0402
2 GPIO27 DF_TVS H_SNB_IVB# 5 2
X_4.7KR0402
R77 X_10KR0402 PLL_ODVR_EN P8
GPIO28 AH8
when use as the chipset test interface,GPIO28 TPJNC69 STP_PCI# K1 TS_VSS1 DF_TVS:
STP_PCI# / GPIO34 JNC14
signal needs to be pulled up to 3.3V_SUS with AK11 Sandy Bridge + Ivy Bridge Compatible:
TPJNC21 EDID_SELECT# K4 TS_VSS2
4.7K resistor to ensure proper strap setting GPIO35 Connect DF_TVS signal of the PCH to PROC_SELECT# of the
AH10
TPJNC20 PCH_GPIO36 V8 TS_VSS3 processor through a 1K±5% series resistor. PROC_SELECT#
SATA2GP / GPIO36 AK10 also needs a 2.2K±5% pull up resistor to PCH VccDFTERM rail.
TPJNC11 PCH_GPIO37 TS_VSS4
M5
SATA3GP / GPIO37
TPJNC61 MFG_MODE N2 P37
SLOAD / GPIO38 NC_1
TPJNC66 CRB_SV_DET M3
SDATAOUT0 / GPIO39
TPJNC24 TEST_SET_UP V13 BG2
SDATAOUT1 / GPIO48 VSS_NCTF_15
TPJNC64 CRIT_TEMP_REP# V3 BG48
R201 X_10KR0402 *SATA5GP / GPIO49 / TEMP_ALERT# VSS_NCTF_16
+3VSUS
33 SCI_WAKE_UP# D6 BH3
GPIO57 VSS_NCTF_17
Wake up device BH47
VSS_NCTF_18
A4 BJ4
3 VSS_NCTF_1 VSS_NCTF_19 3
A44 BJ44
VSS_NCTF_2 VSS_NCTF_20
A45 BJ45
VSS_NCTF_3 VSS_NCTF_21
A46 BJ46

NCTF
VSS_NCTF_4 VSS_NCTF_22
A5 BJ5
VSS_NCTF_5 VSS_NCTF_23
A6 BJ6
VSS_NCTF_6 VSS_NCTF_24
B3 C2
VSS_NCTF_7 VSS_NCTF_25
B47 C48
VSS_NCTF_8 VSS_NCTF_26
BD1 D1
VSS_NCTF_9 VSS_NCTF_27
BD49 CPT_PPT_Rev_0p5 D49
VSS_NCTF_10 VSS_NCTF_28
BE1 E1
VSS_NCTF_11 VSS_NCTF_29
BE49 E49
VSS_NCTF_12 VSS_NCTF_30
BF1 F1
VSS_NCTF_13 VSS_NCTF_31
4 4
BF49 F49
VSS_NCTF_14 VSS_NCTF_32

MICRO-STAR INT'L CO.,LTD.


Title

PANTHER POI (GPIO/NCTF/RSVD)


Size Docum ent Num ber Rev
Cus tom 0B
MS-14851
Date: Friday, Decem ber 02, 2011 Sheet 28 of 53
A B C D E

https://vinafix.com
A B C D E

PANTHER POINT (POWER)


+VTT

U23G POWER VCCA_DAC +3VRUN


1700mA 63mA L12
AA23 U48
VCCCORE[1] VCCADAC
AC23
VCCCORE[2]

CRT
AD21 C315 120L200mA-200
1 VCCCORE[3] C309 X_C10u6.3X50805 1
AD23 U47
VCCCORE[4] VSSADAC

VCC CORE
AF21 C0.1u16Y0402
C190 C234 C176 C197 VCCCORE[5]
AF23
VCCCORE[6] +3VRUN
AG21
VCCCORE[7]

X_C10u6.3X50805
AG23 1mA

X_C1u6.3Y0402

X_C1u6.3Y0402
C1u6.3Y0402
VCCCORE[8]
AG24 AK36
VCCCORE[9] VCCALVDS
AG26
VCCCORE[10]
AG27 AK37
VCCCORE[11] VSSALVDS +1_8VRUN C279
AG29
VCCCORE[12] L14 X_C0.1u16Y0402
AJ23 40mA

LVDS
VCCCORE[13]
AJ26 AM37
VCCCORE[14] VCCTX_LVDS[1]
AJ27
VCCCORE[15] 10u100mA_0805
AJ29 AM38
VCCCORE[16] VCCTX_LVDS[2] C310 C272 C314
AJ31
+VTT VCCCORE[17]

X_C0.01u25X0402

C0.01u25x0402

C22u6.3X50805
AP36
VCCTX_LVDS[3]
AP37
VCCTX_LVDS[4]
AN19
VCCIO[28]
+3VRUN
TPJNC73 VCCAPLLEXP BJ22
VCCAPLLEXP
VCC3_3 228mA
V33

HVCMOS
VCC3_3[6]
AN16
VCCIO[15] C174
AN17 C0.1u16Y0402
+VTT VCCIO[16]
V34
VCC3_3[7]
VCCIO 3711mA +VCCVRM
AN21
2
VCCIO[17] 2
AN26 +VTT
C232 C204 C175 C186 C180 VCCIO[18]
AN27 AT16
VCCIO[19] VCCVRM[3]
C10u6.3X50805

X_C1u6.3Y0402

X_C1u6.3Y0402
C1u6.3Y0402

C1u6.3Y0402

AP21
VCCIO[20]
VCCDMI 47mA
AP23 AT20
VCCIO[21] VCCDMI[1]

X_C1u6.3Y0402
DMI
AP24 +VTT

VCCIO
VCCIO[22] C261
70mA
AP26 AB36
VCCIO[23] VCCCLKDMI
AT24
VCCIO[24] C1u6.3Y0402-RH C265

AN33
VCCIO[25]
+VCCVRM +3VRUN 2mA
AN34 AG16 +1_8VRUN
VCCIO[26] VCCDFTERM[1]

BH29 AG17
DFT / SPI
VCC3_3[3] VCCDFTERM[2] C169
C441 C0.1u16Y0402
X_C0.1u16Y0402 AJ16
VCCDFTERM[3]
AP16
VCCVRM[2]
AJ17
VCCDFTERM[4]
TPJNC22 VCCAFDIPLL BG6
3 VccAFDIPLL 3

+VTT AP17
VCCIO[27] 10mA
FDI

V1 +3VRUN
VCCSPI
+VTT AU20
VCCDMI[2] CPT_PPT_Rev_0p5 C420
C1u6.3Y0402

C1u6.3Y0402
C247

VCCVRM 167mA
+1_8VRUN +VCCVRM

R88
2 1 +VCCVRM GPIO28 作为On Die PLL VR的 Enable PIN。
X_0603 HDA_SYNC 为电压设定PIN。

C150 C153 C449 C148


X_C10u6.3X50805

X_C1u6.3Y0402

X_C1u6.3Y0402
C1u6.3Y0402

https://vinafix.com
4 Checklist Page37: Needs to be pulled high for CR 4
The VCCVRM rail (1.5 V) powers an internal voltage regulator module (VRM) that
regulates clean 1.05-V voltage supply for analog rails (VccAPLLEXP, VccaPLLDMI2, and
VccAPLLSATA). This solution will allow us to remove the LC filter requirements for those Low = On Die PLL VR is supplied by 1.8V
rails, thereby reducing platform BOM cost. VCCVRM is enabled by default via internal HDA_SYNC
pull up to GPIO28, High = On Die PLL VR is supplied by 1.5V
This signal has a weak internal pull-down.
MICRO-STAR INT'L CO.,LTD.
Title

PANTHER POINT (POWER)


Size Document Number Rev
Custom 0B
MS-14851
Date: Friday, December 02, 2011 Sheet 29 of 53
A B C D E
A B C D E

PANTHER POINT (POWER)


+3VSUS
U23J POWER +VTT

JNC12
1mA TPJNC77 VCCACLK AD49 N26
VCCACLK VCCIO[29]
1 VCCDSW3_3 does not support Deep SX VCCIO[30]
P26 1
T16 C217
C121 VCCDSW3_3 C1u6.3Y0402
P28
VCCIO[31]
C0.1u16Y0402
+3VRUN TPJNC30 DCPSUSBYP V12 T27
DCPSUSBYP VCCIO[32]
L13 T29
VCC_CLKF33 VCCIO[33]
T38
VCC3_3[5] +3VSUS
10u100mA_0805 T23 95mA
TPJNC74 VCCAPLLDMI2 VCCSUS3_3[7]
BH23 VCCSUS3_3 97mA
VCCAPLLDMI2 T24
C312 C305 VCCSUS3_3[8]
+VTT AL29
VCCIO[14]
V23
VCCSUS3_3[9] +3VSUS

USB
C205 C196
X_C10u6.3X50805

C1u6.3Y0402

TPJNC48 DCPSUS AL24 V24 C0.1u16Y0402 C0.1u16Y0402


DCPSUS[3] VCCSUS3_3[10]
P24
C210 VCCSUS3_3[6] +VTT
C1u6.3Y0402 AA19 D4
VCCASW[1] S-RB551V-30_SOD323
T26
VCCIO[34]
AA21
VCCASW[2] R123 10R1%0402
1mA V5REF_SUS +3VRUN
AA24 M26 +5VSUS
VCCASW[3] V5REF_SUS
AA26 C200 X_C1u6.3Y0402
VCCASW[4] +3VSUS

Clock and Miscellaneous


AN23
DCPSUS[4] C226
AA27
VCCASW[5] C0.1u16Y0402 D5
AN24
AA29 VCCSUS3_3[1] S-RB551V-30_SOD323
+VTT VCCASW[6]
AA31
VCCASW[7] R151 10R1%0402
903mA 1mA V5REF
AC26 P34 +5VRUN
2 VCCASW[8] V5REF 2

AC27
VCCASW[9] N20 C280
VCCSUS3_3[2] +3VSUS
AC29 C1u6.3Y0402
VCCASW[10]

PCI/GPIO/LPC
N22
AC31 VCCSUS3_3[3] C257
C189 C231 C235 C269 VCCASW[11] C1u6.3Y0402
P20
VCCSUS3_3[4]
AD29
VCCASW[12] P22
X_C22u6.3X50805

C22u6.3X50805

X_C1u6.3Y0402
C1u6.3Y0402

VCCSUS3_3[5] +3VRUN
AD31
VCCASW[13]
VCC3_3 228mA
W21 AA16
VCCASW[14] VCC3_3[1]
W23 W16
VCCASW[15] VCC3_3[8] C271 C248
W24 T34 C0.1u16Y0402 X_C0.1u16Y0402
VCCASW[16] VCC3_3[4]
W26
VCCASW[17]
W29 +3VRUN
VCCASW[18]
+VTT W31 AJ2
VCCASW[19] VCC3_3[2]
W33
L24 10u100mA_0805 VCCASW[20] C419 +VTT
AF13
VCCADPLLA VCCIO[5] C0.1u16Y0402
+VCCVRM +VCCRTCEXT N16
DCPRTC
+1

EC41 C446 C158 C0.1u16Y0402 AH13


VCCIO[12]
X_C100u6.3pSO C1u6.3Y0402 Y49 AH14
2

VCCVRM[4] VCCIO[13] C216


C1u6.3Y0402
L25 10u100mA_0805 80mA AF14
3 VCCADPLLB BD47 VCCIO[6] 3
VCCADPLLA
AK1 VCCAPLLSATA
SATA

80mA
+1

EC42 C448 BF47 VCCAPLLSATA TPJNC65


C1u6.3Y0402 +VTT VCCADPLLB
X_C100u6.3pSO AF11 +VCCVRM
2

JNC15 VCCVRM[1] +VTT


AF17
AF33 VCCIO[7]
+VTT VCCDIFFCLKN[1]
55mA AF34 AC16
C198 C270 C1u6.3Y0402 VCCDIFFCLKN[2] VCCIO[2]
AG34
C1u6.3Y0402 VCCDIFFCLKN[3]
AC17
VCCIO[3] C161
95mA VCCSSC
+VTT R122 AG33 AD17 C1u6.3Y0402
C264 VCCSSC VCCIO[4]
C1u6.3Y0402
DCPSST V16
C166 C0.1u16Y0402 DCPSST +VTT

T17 T21
DCPSUS[1] VCCASW[22]
V19
DCPSUS[2]
MISC

+VTT V21
C177 VCCASW[23]
1mA
CPU

C1u6.3Y0402 BJ8
V_PROC_IO T19
VCCASW[21]
PC114 C160 C146 +3VSUS
C4.7u6.3X0603 C0.1u16Y0402 X_C0.1u16Y0402 10mA
A22 P32
RTC

VCCRTC VCCSUSHDA
HDA

RTCVCC
max 6uA C214
CPT_PPT_Rev_0p5 C0.1u16Y0402

4 C430 C432 C429 4


X_C0.1u16Y0402 C1u6.3Y0402 X_C0.1u16Y0402

MICRO-STAR INT'L CO.,LTD.


Title

PANTHER POINT (POWER)


Size Document Number Rev

https://vinafix.com
Custom 0B
MS-14851
Date: Friday, December 02, 2011 Sheet 30 of 53
A B C D E
A B C D E

PANTHER Point (GND) U23I

AY4 H46
VSS[159] VSS[259]
AY42 K18
AY46 VSS[160] VSS[260] K26
VSS[161] VSS[261]
AY8 K39
B11 VSS[162] VSS[262] K46
1 U23H VSS[163] VSS[263] 1
B15 K7
VSS[164] VSS[264]
H5 B19 L18
VSS[0] B23 VSS[165] VSS[265] L2
VSS[166] VSS[266]
AA17 AK38 B27 L20
AA2 VSS[1] VSS[80] AK4 B31 VSS[167] VSS[267] L26
AA3 VSS[2] VSS[81] AK42 B35 VSS[168] VSS[268] L28
VSS[3] VSS[82] VSS[169] VSS[269]
AA33 AK46 B39 L36
AA34 VSS[4] VSS[83] AK8 B7 VSS[170] VSS[270] L48
VSS[5] VSS[84] VSS[171] VSS[271]
AB11 AL16 F45 M12
AB14 VSS[6] VSS[85] AL17 BB12 VSS[172] VSS[272] P16
AB39 VSS[7] VSS[86] AL19 BB16 VSS[173] VSS[273] M18
VSS[8] VSS[87] VSS[174] VSS[274]
AB4 AL2 BB20 M22
AB43 VSS[9] VSS[88] AL21 BB22 VSS[175] VSS[275] M24
VSS[10] VSS[89] VSS[176] VSS[276]
AB5 AL23 BB24 M30
AB7 VSS[11] VSS[90] AL26 BB28 VSS[177] VSS[277] M32
AC19 VSS[12] VSS[91] AL27 BB30 VSS[178] VSS[278] M34
VSS[13] VSS[92] VSS[179] VSS[279]
AC2 AL31 BB38 M38
AC21 VSS[14] VSS[93] AL33 BB4 VSS[180] VSS[280] M4
VSS[15] VSS[94] VSS[181] VSS[281]
AC24 AL34 BB46 M42
AC33 VSS[16] VSS[95] AL48 BC14 VSS[182] VSS[282] M46
AC34 VSS[17] VSS[96] AM11 BC18 VSS[183] VSS[283] M8
VSS[18] VSS[97] VSS[184] VSS[284]
AC48 AM14 BC2 N18
AD10 VSS[19] VSS[98] AM36 BC22 VSS[185] VSS[285] P30
VSS[20] VSS[99] VSS[186] VSS[286]
AD11 AM39 BC26 N47
AD12 VSS[21] VSS[100] AM43 BC32 VSS[187] VSS[287] P11
AD13 VSS[22] VSS[101] AM45 BC34 VSS[188] VSS[288] P18
VSS[23] VSS[102] VSS[189] VSS[289]
AD19 AM46 BC36 T33
AD24 VSS[24] VSS[103] AM7 BC40 VSS[190] VSS[290] P40
VSS[25] VSS[104] VSS[191] VSS[291]
AD26 AN2 BC42 P43
2 AD27 VSS[26] VSS[105] AN29 BC48 VSS[192] VSS[292] P47 2
AD33 VSS[27] VSS[106] AN3 BD46 VSS[193] VSS[293] P7
VSS[28] VSS[107] VSS[194] VSS[294]
AD34 AN31 BD5 R2
AD36 VSS[29] VSS[108] AP12 BE22 VSS[195] VSS[295] R48
VSS[30] VSS[109] VSS[196] VSS[296]
AD37 AP19 BE26 T12
AD38 VSS[31] VSS[110] AP28 BE40 VSS[197] VSS[297] T31
AD39 VSS[32] VSS[111] AP30 BF10 VSS[198] VSS[298] T37
VSS[33] VSS[112] VSS[199] VSS[299]
AD4 AP32 BF12 T4
AD40 VSS[34] VSS[113] AP38 BF16 VSS[200] VSS[300] W34
VSS[35] VSS[114] VSS[201] VSS[301]
AD42 AP4 BF20 T46
AD43 VSS[36] VSS[115] AP42 BF22 VSS[202] VSS[302] T47
AD45 VSS[37] VSS[116] AP46 BF24 VSS[203] VSS[303] T8
VSS[38] VSS[117] VSS[204] VSS[304]
AD46 AP8 BF26 V11
AD8 VSS[39] VSS[118] AR2 BF28 VSS[205] VSS[305] V17
VSS[40] VSS[119] VSS[206] VSS[306]
AE2 AR48 BD3 V26
AE3 VSS[41] VSS[120] AT11 BF30 VSS[207] VSS[307] V27
AF10 VSS[42] VSS[121] AT13 BF38 VSS[208] VSS[308] V29
VSS[43] VSS[122] VSS[209] VSS[309]
AF12 AT18 BF40 V31
AD14 VSS[44] VSS[123] AT22 BF8 VSS[210] VSS[310] V36
VSS[45] VSS[124] VSS[211] VSS[311]
AD16 AT26 BG17 V39
AF16 VSS[46] VSS[125] AT28 BG21 VSS[212] VSS[312] V43
AF19 VSS[47] VSS[126] AT30 BG33 VSS[213] VSS[313] V7
VSS[48] VSS[127] VSS[214] VSS[314]
AF24 AT32 BG44 W17
AF26 VSS[49] VSS[128] AT34 BG8 VSS[215] VSS[315] W19
VSS[50] VSS[129] VSS[216] VSS[316]
AF27 AT39 BH11 W2
AF29 VSS[51] VSS[130] AT42 BH15 VSS[217] VSS[317] W27
AF31 VSS[52] VSS[131] AT46 BH17 VSS[218] VSS[318] W48
VSS[53] VSS[132] VSS[219] VSS[319]
AF38 AT7 BH19 Y12
AF4 VSS[54] VSS[133] AU24 H10 VSS[220] VSS[320] Y38
VSS[55] VSS[134] VSS[221] VSS[321]
3 AF42 AU30 BH27 Y4 3
AF46 VSS[56] VSS[135] AV16 BH31 VSS[222] VSS[322] Y42
AF5 VSS[57] VSS[136] AV20 BH33 VSS[223] VSS[323] Y46
VSS[58] VSS[137] VSS[224] CPT_PPT_Rev_0p5 VSS[324]
AF7 AV24 BH35 Y8
AF8 VSS[59] VSS[138] AV30 BH39 VSS[225] VSS[325] BG29
VSS[60] VSS[139] VSS[226] VSS[328]
AG19 AV38 BH43 N24
AG2 VSS[61] VSS[140] AV4 BH7 VSS[227] VSS[329] AJ3
AG31 VSS[62] VSS[141] AV43 D3 VSS[228] VSS[330] AD47
VSS[63] VSS[142] VSS[229] VSS[331]
AG48 AV8 D12 B43
AH11 VSS[64] VSS[143] AW14 D16 VSS[230] VSS[333] BE10
VSS[65] CPT_PPT_Rev_0p5 VSS[144] VSS[231] VSS[334]
AH3 AW18 D18 BG41
AH36 VSS[66] VSS[145] AW2 D22 VSS[232] VSS[335] G14
AH39 VSS[67] VSS[146] AW22 D24 VSS[233] VSS[337] H16
VSS[68] VSS[147] VSS[234] VSS[338]
AH40 AW26 D26 T36
AH42 VSS[69] VSS[148] AW28 D30 VSS[235] VSS[340] BG22
VSS[70] VSS[149] VSS[236] VSS[342]
AH46 AW32 D32 BG24
AH7 VSS[71] VSS[150] AW34 D34 VSS[237] VSS[343] C22
AJ19 VSS[72] VSS[151] AW36 D38 VSS[238] VSS[344] AP13
VSS[73] VSS[152] VSS[239] VSS[345]
AJ21 AW40 D42 M14
AJ24 VSS[74] VSS[153] AW48 D8 VSS[240] VSS[346] AP3
VSS[75] VSS[154] VSS[241] VSS[347]
AJ33 AV11 E18 AP1
AJ34 VSS[76] VSS[155] AY12 E26 VSS[242] VSS[348] BE16
AK12 VSS[77] VSS[156] AY22 G18 VSS[243] VSS[349] BC16
VSS[78] VSS[157] VSS[244] VSS[350]
AK3 AY28 G20 BG28
VSS[79] VSS[158] G26 VSS[245] VSS[351] BJ28
VSS[246] VSS[352]
G28
G36 VSS[247]
G48 VSS[248]
VSS[249]
H12
H18 VSS[250]
4 VSS[251] 4
H22
H24 VSS[252]
H26 VSS[253]
VSS[254]
H30
H32 VSS[255]
VSS[256]
H34
VSS[257]
F3
VSS[258] MICRO-STAR INT'L CO.,LTD.
Title

PANTHER POINT (GND)


Size Docum ent Num ber Rev
Cus tom 0B
MS-14851

https://vinafix.com
Date: Friday, Decem ber 02, 2011 Sheet 31 of 53
A B C D E
A B C D E

USB5V_PT1
F4
+5VSUS 1 2
4 4
F-MINISMDC150
C422 C424 C423

X_C220p50N0402

X_C220p50N0402
X_C100u6.3Y1210-RH
USB2
SSTX2P USB5V_PT1
27 USB3_TX2P

C1
C3
SSTX2N USB3
27 USB3_TX2N

SHIELD1
SHIELD3
C331 C0.1u10X0402 SSTX2P_C 9 STDA_SSTX+

RVS Type-A
1 VBUS
C334 C0.1u10X0402 SSTX2N_C 8
3
USBN1_C STDA_SSTX- 3
27 USB_P1N 4 1 2 D-
4
USBP1_C GND
27 USB_P1P 3 2 3
D+
6

SHIELD2
SHIELD4
LI3 STDA_SSRX+
7 GND_DRAIN
X_CMC-L12-9008084-RH 5 STDA_SSRX-

SSRX2P AMP ( 1932295-1 )

C2
C4
27 USB3_RX2P
SSRX2N
27 USB3_RX2N

C344 C337
X_C10p25N0402

X_C10p25N0402

Vinafix.com
2 2

USB1
https://vinafix.com
SSTX1P USB5V_PT1
27 USB3_TX1P
C1
C3

SSTX1N USB2
27 USB3_TX1N
SHIELD1
SHIELD3

C438 C0.1u10X0402 SSTX1P_C 9


STDA_SSTX+
RVS Type-A

1
C439 C0.1u10X0402 SSTX1N_C VBUS
8
USBN0_C STDA_SSTX-
27 USB_P0N 4 1 2
D-
4
USBP0_C GND
27 USB_P0P 3 2 3
D+
6
SHIELD2
SHIELD4

LI7 STDA_SSRX+
7
GND_DRAIN
X_CMC-L12-9008084-RH 5
SSRX1P STDA_SSRX-
27 USB3_RX1P
SSRX1N AMP ( 1932295-1 )
C2
C4

27 USB3_RX1N
X_C10p25N0402

1 1
X_C10p25N0402

C434 C431
MICRO-STAR INT'L CO.,LTD.
Title

USB3.0
Size Document Number Rev
Custom 0B
MS-14851
Date: Friday, December 02, 2011 Sheet 32 of 53
A B C D E
1 2 3 4 5

U4 +3VALW
+3VRUN

26
3 9
23,24 INT _SERIRQ SERIRQ VCC
4 22
23 LPC_FRAM E# LFARAME# VCC
RN7 +3VALW 12 33
27 CLK_PCI_KBC PCICLK VCC
1 2 KBSM I# EC_CLKRUN# 38 96 C17 C27 C34 C11
KBSCI# 25 EC_CLKRUN# CLKRUN#/GPIO1D VCC
3 4 10 LPC I/F 111
23 LAD0 LAD0 VCC
5 6 H_A20GAT E 8 125

C0.1u10X0402

C0.1u10X0402
23 LAD1 LAD1 VCC

C0.1u16Y0402

C0.1u16Y0402
7 8 KBRST # 7 KBOUT 0 1
23 LAD2 LAD2
R16 5 POWER/GROUND 67 KBOUT 1 2
23 LAD3 LAD3 AVCC KBOUT 2
X_8P4R-10KR0402 10KR0402 69 3
AGND KBIN0 4
EC_RST # 37 11 +3VALW KBIN1 5
KBRST # 2 ECRST# GND 24 KBIN2
C37 6
1
R19 100KR0402 EC_CLKRUN# 28 KBRST # KBSCI# KBRST# GND 1
20 35 C0.1u10X0402 KBIN3 7
28 KBSCI# SCI#/GPIO0E GND
H_A20GAT E 1 94 R10 4.7KR0402 KBOUT 3 8
28 H_A20GAT E GA20 GND
R9 100KR0402 ENCHG C33 13 113 R12 4.7KR0402 KBOUT 4 9
27 LPC_RST # PCIRST# GND
X_C1u6.3Y0402-RH KBIN4 10
R4 10KR0402 RSM RST # 21 78 KBIN5 11
38 AC_CT L PWM0/GPIO0F SDA0/GPIO45 BAT DAT A_M 38,39
23 77 KBIN6 12
35,36 BT _PWR_ON PWM1/GPIO10 SCL0/GPIO44 BAT CLK_M 38,39
R8 100KR0402 KBRST # 25 SMBUS 80 KBIN7 13
20 BR-AD-ADJ T P-OFF_SW# GPIO11/PWM2 SDA1/GPIO47 SM B_DAT A_EC 24 KBOUT 5
34 79 14
22 T P-OFF_SW# GPIO19/PWM3 SCL1/GPIO46 SM B_CLK_EC 24
26 FAN&PWM KBOUT 6 15
27 FANPWM0/GPIO12 68 KBOUT 7 16
23 FLASH_SECURIT Y FANPWM1/GPIO13 DA0/GPO3C FAN_DA 36
checklist required 28 70 KBOUT 8 17
36 CPUFAN_FB FANFB0/GPIO14 DA1/GPO3D KBOUT 9
29 71 EC_S3 41 18
27,36 ODD_INT _PIRQF# FANFB1/GPIO15 DA2/GPO3E
72 KBOUT 10 19
DA3/GPO3F DGPU_PWRGD Q2 KBOUT 11
AD/DA AD0/GPI38
63 20
KBOUT 0 39 64 S1 KBOUT 12 21
KBOUT 1 KSO0/GPIO20/TP_TEST AD1/GPI39 M B_ID IOUT 39 SM B_T HRM GPU_DAT A 15 KBOUT 13
40 65 D1 G1 22
KBOUT 2 41 KSO1/GPIO21/TP_PLL AD2/GPI3A 66 S2 KBOUT 14 23
KSO2/GPIO22/TP_ANA_TEST AD3/GPI3B SUSPWRACK 25 SM B_T HRM GPU_CLK 15
KBOUT 3 42 75 D2 G2 KBOUT 15 24
KSO3/GPIO23/TP_ISP AD4/GPI42 AC_OK# 38,39
KBOUT 4 43 76 R13 25
KSO4/GPIO24 AD5/GPI43 BAT _IN# 38 DGPU_PWRGD 15,28,45
+3VALW +3VALW KBOUT 5 44 NN-2N7002DW_SOT 363-RH
KSO5/GPIO25
KBOUT 6 45 97
KBOUT 7 KSO6/GPIO26 GPXIOA00/SDICS#
R11 2.2KR0402 46 SDI 98 C31
KBOUT 8 KSO7/GPIO27 GPXIOA01/SDICLK SUS_ON 40
47 99 X_C0.1u10X0402
KSO8/GPIO28 GPXIOA02/SDIMOSI RSM RST # 25
R7 U2 KBOUT 9 48
EC_CS# KBOUT 10 KSO9/GPIO29 J19
10KR0402 8 1 49 100
SPI_HOLD# VCC CS# EC_RD# KBOUT 11 KSO10/GPIO2A GPXIOA03 DIM M _ON 41
7 2 50 IKB 101

27
EC_SPICLK HOLD# SO KBOUT 12 KSO11/GPIO2B GPXIOA04 RUN_ON 40,41,42,45
6 3 51 102 EC_PCH_PWROK 25,44
EC_WR# 5 SCLK WP# 4 KBOUT 13 52 KSO12/GPIO2C GPXIOA05 103 Cinem a Pro_SW# FPC25P-T -1PIT CH_WHIT E-RH
SI GND KBOUT 14 KSO13/GPIO2D GPXIOA06 Cinem a Pro_SW# 22
53 104 WLAN_PWRON 35,36
M X25L512M C-12G-RH KBOUT 15 54 KSO14/GPIO2E GPXIOA07 105
KSO15/GPIO2F/E51_RXD(ISP) GPXIOA08 LED_ACPI# 22
81 106
KSO16/GPIO48 GPXIOA09 LED_CHARGE# 22
82 107
KSO17/GPIO49 GPXIOA10 LED_BAT LOW# 22
108
GPXIOA11 LED_BLUET OOT H# 22
KBIN0 55 109
KSI0/GPIO30/E51TXD(ISP) GPXIOD0 SUSPWROK 40
ER2 KBIN1 56 110
KSI1/GPIO31 GPXIOD1 PM _SLP_S4# 25
2 EC_SPI_CLK EC_SPICLK KBIN2 57 112 2
KBIN3 KSI2/GPIO32 GPXIOD2 EC_ALLSYSPG PM _SLP_S3# 25
58 114
KBIN4 KSI3/GPIO33 GPXIOD3 PWR_SW#
0R PAD 0402 59 115
EC2 KBIN5 KSI4/GPIO34/EDI_CS GPXIOD4 PWR_SW# 22
60 116
KBIN6 KSI5/GPIO35/EDI_CLK GPXIOD5 SCI_WAKE_UP# 28
C10p50N0402 61 117
KBIN7 KSI6/GPIO3/EDI_DIN GPXIOD6 LID# 20
62 118 R15 43R0402 H_PECI 5,28 EC10
KSI7/GPIO37/EDI_DO GPXIOD7 KBOUT 11
EC6 1 2
17 ESB 6 KBOUT 3 1 2 KBOUT 10 3 4
37 KBC_M UT E# GPIO0B/ESB_CLK GPIO04 EC_DE_POP 37
18 14 Device key_SW# KBOUT 2 3 4 KBOUT 9 5 6
GPIO0C/ESB_DAT_O/ESB_DAT_I GPIO07/i_clk_8051 15 T urbo_SW# Device key_SW# 22 KBOUT 1 5 6 KBOUT 8 7 8
GPIO08/i_clk_peri T urbo_SW# 22
+5VRUN +5VRUN 73 32 KBOUT 0 7 8
22 LED_Device key# GPIO40/CIR_RX GPIO18 KBSM I# 28
5,28 H_PECI R14 X_43R0402
74 89 8p4C-100p50N0402-RH
ODD_EJECT _SW# GPIO41/CIR_RLC_TX GPIO50 PWR_LED# ENCHG 38
16 CIR 90 8p4C-100p50N0402-RH
22 ODD_EJECT _SW# GPIO0A/RLC_RX2 E51CS#/GPIO52 PWR_LED# 22
Display_SW# 19 92 EC5 EC8
22 Display_SW# GPIO0D/RLC_TX2 E51TMR0/GPIO54/WDT_LED# LED_WLAN# 22 KBOUT 7 KBOUT 15
95 1 2 1 2
E51INT1/GPIO56 PM _PWRBT N# 25
EC_RD# 119 121 LED_Cinem a Pro# KBOUT 6 3 4 KBOUT 14 3 4
EC_WR# MISO GPIO57/XCLK32K LED_Cinem a Pro# 22 KBOUT 5 KBOUT 13
R21 R20 120 127 5 6 5 6
EC_SPI_CLK MOSI GPIO59/TEST_CLKSPICLKI CAM ERA_ON# 20 KBOUT 4 KBOUT 12
10KR0402 10KR0402 126 SPI FLASH 7 8 7 8
EC_CS# SPICLK/GPIO58
128
SPICS# 8p4C-100p50N0402-RH 8p4C-100p50N0402-RH
T P_CLK 87
22 T P_CLK PSCLK2/GPIO4E
T P_DAT A 88
22 T P_DAT A PSDAT2/GPIO4F
85 PS2 I/F 36
22 LED_T urbo# PSCLK1/GPIO4C GPIO1A/NUMLED# LED_NUM # 22
LED_T P-OFF 86 91
22 LED_T P-OFF PSDAT1/GPIO4D E51TMR1/GPIO53/CAPSLED# LED_CAP# 22
83 93
5 EC_PROCHOT # PSCLK0/GPIO4A/P80CLK E51INT0/GPIO55/SCROLED# GPU_CT F 15
84
PSDAT0/GPIO4B/P80DAT
T PJNC3 30
放在keyboard connector附件 E51TXD/GPIO16
T PJNC4 31 UART
E51RXD/GPIO17
LED
R2 EC_XIN 122
EC_XOUT 123 XCLKI
25 SUSCLK XCLKO
0R PAD 0402
124
Y2 V18R
3 4 1 3
3 2 C6 KB3930QFB1-B1-HF R5 EC_ALLSYSPG
43 +0.85V_PWRGD EC_ALLSYSPG 44
C4.7u6.3X0603
R3
X_100KR0402 X_32.768KHZ12.5P_S-2 0R PAD 0402

C5 C4
X_C22p50N0402 X_C22p50N0402

15
LPC_FRAM E# 1 +3VALW
LAD3 2
LAD2 3
LAD1 4
LAD0 5
6 PR15
23 L_LDRQ0# X_100KR0402
7
27 CLK_PCIF_PORT 80
INT _SERIRQ 8
LPC_RST # 9 M B_ID
10
+5VRUN
11
+3VRUN R18 C35
12
FWH_ID0 13 X_0R0402 X_C0.1u16Y0402
14 CON5

R168 BH1X14HS-1.25PIT CH_WHIT E-RH


X_10KR0402 16

4 4

MICRO-STAR INT'L CO.,LTD.


Title

KBC/EC/uP (KB3930-A1)
Size Docum ent Num ber Rev
Custom 0B
MS-14851
Date: Friday, Decem ber 02, 2011 Sheet 33 of 53
1 2 3 4 5

https://vinafix.com
1 2 3 4 5

Note: add 0.1u cap at each power pin of LAN, please don't save.
Use External 1.05V Supply When Disable Switch Regulator.
If Using External 1.2V Supply Pls. Contact With FAE.
C373
X_OUT C27p50N0402

2010/01/08 remove it,If used jump write

1
R176 2.49KR1%0402 RSET
Y3
T PJNC2 25M HZ20p_S-RH-2 VDD10

2
CHOKE2
JNC6
1 C372 1
X_IN C27p50N0402 REGOUT 1 2

X_OUT
VDD33
VDD33

VDD10

VDD33
VDD10

VDD33
REGOUT

EESK
GPO
X_IN
CH-4.7u1.24A98m S-RH
X_CP0603 C0.1u16Y0402 C0.1u16Y0402 C0.1u16Y0402
Pls. refer to C375 C374
C4.7u6.3 C0.1u16Y0402 C16 C18 C28 C23 C20 C13 C14
8111E Layout

48
47
46
45
44
43
42
41
40
39
38
37
U16 Guide for L1, C0.1u16Y0402 C0.1u16Y0402 C0.1u16Y0402 C0.1u16Y0402
49 C1, C2

AVDD33
AVDD33

AVDD10
CKXTAL2
CKXTAL1
AVDD33

LED0
DVDD33
RSET

GPO/SMBALERT
DVDD10(NC)

LED1/EESK
GND
selection
AVDD33_REG
criteria.
REGOUT EVDD10
M DI0+ REGOUT JNC3
1
MDIP0 REGOUT
36 Remove For Disable Switch Regulator
M DI0# 2 35 AVDD33_REG
VDD10 MDIN0 VDDREG AVDD33_REG +3VRUN VDD33 (Accept External 1.05V Power Supply )
3 34
M DI1+ 4 AVDD10 VDDREG 33 ENSWREG
M DI1# 5 MDIP1 ENSWREG 32 EEDI X_CP0603
MDIN1 EEDI
VDD10 6 31 EEDO T PJNC57 R172 C9 C369
M DI2+ 7 AVDD10(NC) LED3/EEDO 30 EECS R174 C1u6.3Y0402-RHC0.1u16Y0402
MDIP2(NC) EECS
M DI2# 8 29 VDD10 1KR0402 0R PAD 0402
VDD10 MDIN2(NC) DVDD10
9 28
M DI3+ AVDD10(NC) LANWAKEB VDD33 PCIE_WAKE# 25,35
10 27
MDIP3(NC) DVDD33
M DI3# 11 26 ISOLAT E# ENSWREG
VDD33 12 MDIN3(NC) ISOLATEB 25 LAN_RST #
SMBDATA(NC)

AVDD33(NC) PERSTB LAN_RST # 27


SMBCLK(NC)

R170
REFCLK_N
REFCLK_P
CLKREQB

15KR0402 R173 2010/03/26 modify Xcopper to 0R


DVDD10

EVDD10

X_0R0402 VDD33
HSON
HSOP

+3VSUS
HSIN
HSIP

GND

JNC2
2 1
13
14
15
16
17
18
19
20
21
22
23
24

RT L8111E-VL-CG C0.1u16Y0402 C0.1u16Y0402


X_0805
2 2
+3VSUS R171 10KR0402 EECS C22 C29 C26 C15 C366 C10
SMBDATA

EVDD10

EEDI
VDD10

R169 10KR0402 C0.1u16Y0402 C0.1u16Y0402 C0.1u16Y0402 C0.1u16Y0402


VDD33 power on rise time >1ms
R166 Please close to LAN Chip
10KR0402 C1851 to C1856 Close To LAN chip
24 CLK_GLAN_REQ# HSON C367 C0.1u10X0402
24 PCIE_GLAN_T XP PCIE_GLAN_RXN 24
HSOP C368 C0.1u10X0402
24 PCIE_GLAN_T XN PCIE_GLAN_RXP 24
24 CLK_PCIE_LAN
AVDD33_REG
24 CLK_PCIE_LAN# JNC5
AVDD33_REG

X_CP0603
C19 C371
U17 RN2 C4.7u6.3 C0.1u16Y0402
V_DAC 1 24 M CT 1 M CT 1 1 2
M DI3# 2 TCT1 MCT1 23 T RD3# M CT 2 3 4
M DI3+ TD1+ MX1+ T RD3+ M CT 3
3 22 5 6
V_DAC 4 TD1- MX1- 21 M CT 2 M CT 4 7 8 Remove For Disable
M DI2# 5 TCT2 MCT2 20 T RD2#
M DI2+ 6
TD2+ MX2+
19 T RD2+ 8P4R-75R0402
Switch Regulator
V_DAC 7 TD2- MX2- 18 M CT 3
TCT3 MCT3
M DI1# 8 17 T RD1#
M DI1+ 9 TD3+ MX3+ 16 T RD1+
V_DAC TD3- MX3- M CT 4
10 15 C12 JNC7
TCT4 MCT4
M DI0# 11 14 T RD0# X_C1000p2KX1206 X_R/2
M DI0+ TD4+ MX4+ T RD0+
12 13
TD4- MX4-
GST 5009 LF-RH
C7
C0.01u25X0402
3 3

10
CN3
LAN-RJ45-HF
T RD0+ 1
VDD33 T RD0# 2
T RD1+ 3
EEPROM Select T RD2+ 4
GPO R175 1KR0402 T RD2# 5
T RD1# 6
T RD3+ 7
T RD3# 8
SM BDAT A R165 X_10KR0402

R167 10KR0402

9
N55-08F0491-SH4

4 4

MICRO-STAR INT'L CO.,LTD.


Title

GIGA LAN (RTL8111EL)


Size Docum ent Num ber Rev
Custom 0B
MS-14851
Date: Friday, Decem ber 02, 2011 Sheet 34 of 53
1 2 3 4 5

https://vinafix.com
A B C D E

WLAN
+3VRUN
1 1
C36 C10u10Y0805
R6 X_0R0402 1 2
25,34 PCIE_WAKE# WAKE# +3.3V_1
3 4
BT_DATA GND7
5 6
BT_CHCLK +1.5V_1
7 8
CLKREQ# RSVD13
9 10
GND1 RSVD14
24 CLK_PCIE_MINI# 11 12
REFCLK- RSVD15
24 CLK_PCIE_MINI 13 14
REFCLK+ RSVD16
15 16
GND2 RSVD17

KEY
17 18
RSVD3 GND8
19 20 WLAN_PWRON 33,36
RSVD4 W_DISABLE#
21 22 WLAN_RST# 27
GND3 PERST#
24 PCIE_MINI_RXN 23 24 +3VRUN
PET_N0 +3.3_AUX
24 PCIE_MINI_RXP 25 26
2
PET_P0 GND9 2
27 28
GND4 +1.5V_2
29 30
GND5 RSVD18
24 PCIE_MINI_TXN 31 32
PER_N0 RSVD19
24 PCIE_MINI_TXP 33 34
PER_P0 GND10
35 36 USB_P10N 27
GND6 USB_D-
37 38 USB_P10P 27
RSVD5 USB_D+
+3VRUN 39 40
RSVD6 GND11
41 42
C2 RSVD7 NC
43 44
C3 RSVD8 LED_WLAN#
45 46
X_10u6.3v C0.1u16Y0402 RSVD9 NC
47 48
RSVD10 +1.5V_3
49 50
RSVD11 GND12
51 52 +3VRUN
RSVD12 +3.3V_2
33,36 BT_PWR_ON
53 54 C24
GND17 GND17 X_C0.1u16Y0402
3 3

56
NC
55
NC

CON6
SLOT-MINIPCI52P-0.8PITCH-RH-2
N11-0520020-L41
SLOT_MINIPCIEXP52_H9

4
MICRO-STAR INT'L CO.,LTD. 4

Title

WLAN
https://vinafix.com
Size Document Number Rev
A 0B
MS-14851
Date: Friday, December 02, 2011 Sheet 35 of 53
A B C D E
A B C D E

ODD 1.GND
WLAN/BT (3870)

S8
2.TX
S1
3.TX#
C396 C0.01u25X0402 SATA1TXP_SJNC S2 4.GND
23 SATA1TXP SATA1TXN_SJNC
23 SATA1TXN C394 C0.01u25X0402 S3 5.RX#
S4 6.RX
C393 C0.01u25X0402 SATA1RXN_SJNC S5 +3VRUN
23 SATA1RXN 7.GND
C390 C0.01u25X0402 SATA1RXP_SJNC S6
1 23 SATA1RXP 1
S7 33,35 WLAN_PWRON
1.DP C376 X_C0.1u16Y0402
2.+5V
3.+5V C41
R177 X_10KR0402 P1 4.MD X_C1000p50X0402

12
+5VRUN
P2 5.GND
+5V_ODD P3 6.GND R57 X_0R0805 10 CON7
1

P4 +5V_ODD 9 BH1X10S-1PITCH_WHITE-RH
+

C382 C381 C383 P5 +5VRUN 8


P6 7
2

27 USB_P9N
X_C100u16EL-RH-8 X_C0.1u10X0402C0.1u10X0402 Q7 N-AO3404_SOT23 6
27 USB_P9P
D S 5
4

P7
27,33 ODD_INT_PIRQF# 33,35 BT_PWR_ON
3

G
27 USB_P4N
R55 1MR1%0402 2
27 USB_P4P
1
N5N-13M0010-A81 40 RUND +3VRUN

D
CON8 C42

11
G C377
27 ODD_PWR_ON#
SATA_S13 Q8

X_C1000p50X0402
SATA13PSM_BLACK-RH N-2N7002G_SOT23-1
N32-1100250-A81

X_C0.1u16Y0402
C88
X_C0.1u10X0402

2 2

+5VRUN

Modify fo ANPEC
CPU FAN
U3
C370 C1u6.3Y0402-RH 1 8
FSM# GND
2 7
VIN GND
VCCFAN1 3 6
VOUT GND
SATA HDD 33 FAN_DA
4
VSET GND
5

MEC2 APL5606KI-TRL_SOP8-RH

23
1.GND
2.TX
1
3.TX#
C224 C0.01u25X0402 SATA0TXP_SJNC 2 4.GND
23 SATA0TXP SATA0TXN_SJNC
23 SATA0TXN C223 C0.01u25X0402 3 5.RX#
4 6.RX
3 SATA0RXN_SJNC 3
23 SATA0RXN C274 C0.01u25X0402 5
C283 C0.01u25X0402 SATA0RXP_SJNC 6 7.GND
23 SATA0RXP
7
1.V33 +3VRUN
2.V33
3.V33
4.GND R17
5.GND 10KR0402
6.GND
8 CPUFAN_FB 33
9 7.V5
10 8.V5

5
11 9.V5
12 VCCFAN1 1 J39
10.GND
13 2 BH1X3#_white-1.25pitch
14 11.Reserved 3
+5VRUN 15 12.GND 53398_03
16 13.V12 C30

4
C464 17 X_C10u10Y0805
C0.1u10X0402 18
14.V12
15.V12
N32-1030720-A81
19
1

R270 20
+

C454 X_0R0402 21
X_C100u16EL-RH-8 C465 22
2

X_C0.1u10X0402
MEC1

24

4 4
CN2

SATA22PSF_BLACK-P-RH-1

N5N-22F0160-A81 MICRO-STAR INT'L CO.,LTD.


Title
HDD/ODD/ESATA/FAN/BT/USB
Size Docum ent Num ber Rev
Cus tom 0B
MS-14851
Date: Friday, Decem ber 02, 2011 Sheet 36 of 53
A B C D E

https://vinafix.com
A B C D E

+3VRUN
SPEAKER

Default use 3.3V


FOR ALC269-VB have internal LDO CON10

6
JNC16
AVDD_5V X_CP0603 SPK_OUT_L- 4
1 SPK_OUT_L+ 1
+5VRUN 3

X_10u10X
0.1u16X
80L3A SPK_OUT_R+ 2
AVDD SPK_OUT_R- 1
L17
C365 C363 close to pin 9 C475 C473 C472 C474

5
C348

C349
C361 C476

X_C1000p50X0402

X_C1000p50X0402

X_C1000p50X0402

X_C1000p50X0402
X_10u10X X_0.1u16X 10u10X 0.1u16X GND

BH1X4#S-1.25PITCH_WHITE-RH-3

+3VRUN
GND AGND close to pin 1 GND GND GND GND GND
+5VRUN

JNC18 X_CP_93519 PVDD


AGND
C357 C355
N32-10400N0-A81
0.1u16X X_10u10X

IOVDD
C364 C362 C359 C360

DVDD
C485
X_10u10X X_0.1u16X 10u10X 0.1u16X 2.2u10X
Speaker length < 20MM
close to chip GND
4ohm loading---------20 mil trace width

46
39

38
25

34
8ohm loading---------10 mil trace width

9
1
GND GND U29

PVDD2
PVDD1

AVDD2
AVDD1

DVDD-IO

CPVEE
DVDD
2
23 CODEC_HDA_RST# 11
RESET#
MIC1-L
21 MIC1_L 22 MIC2_VREFO N32-1020730-A81 2
23 CODEC_HDA_SY NC 10 22 MIC1_R 22
SY NC MIC1-R

23 CODEC_HDA_BIT_CLK 6 23 INT MIC

Digital I/O Pins


BCLK LINE1-L C1u10Y 0402-RH R159 2.2KR0402
24

5
5 LINE1-R
23 CODEC_HDA_SDOUT SDATA-OUT MIC2_L C341
8 14
R277 33R1%0402 CODEC_HDA_SDIN0_R SDATA-IN LINE2-L 15 INT_MIC 1
23 CODEC_HDA_SDIN0 LINE2-R
47 MIC2_R C342 2
33 EC_DE_POP EAPD
48 16 MIC2_L
SPDIFO MIC2-L MIC2_R C1u10Y 0402-RH C336 X_C1000p50X0402
TO EC 17
2 MIC2-R

6
GPIO0/DMIC-DATA AGND
3
GPIO1/DMIC-CLK 40 SPK_OUT_L+

Analog I/O Pins


PD# SPK-OUT-L+ SPK_OUT_L- AGND
4 41
PD# SPK-OUT-L- AGND
VLth=2/5*5V 44 SPK_OUT_R- BH1X2#S-1.25PITCH_WHITE-RH-3
SPK-OUT-R- 45 SPK_OUT_R+ CON9
MIC2_VREFO SPK-OUT-R+
29
30 MIC2-VREFO
22 MIC1_VREFO_R OPT1 MIC1-VREFO-R HPOUT_L R160 75R
31 32 DEPOP_L 22
MIC1-VREFO-L HPOUT-L 33 HPOUT_R R162 75R
DEPOP_R 22

Filter/Reference
HPOUT-R
must close to chip C488 2.2u10X 35 R274
CBN MIC_JD# 22
36 13 R273 20KR1%0402
CBP SenseA FRONT_JD# 22
18 39.2KR1%
SenseB
close chip LOW=plug
VREF_AUDIO 27
VREF
12
19 PCBEEP
close to pin 27 AGND R272 20KR1%0402 JDREF JNC17
20
3 MONO-OUT X_CP_93519 3
JNC27
C479 C478 OPT2 28 X_CP_93519
No Co-layout VA
PVSS2
PVSS1

AVSS2
AVSS1
LDO-CAP

DVSS

GND
VB 2.2u10X X_0.1u16X

ALC269Q-VB5-GR-RH simple MUTE AGND GND


43
42

37
26

49
22 MIC1_VREFO_L
JNC28 X_R/2 OPT1 VA=NC

AGND C345 10u10X OPT2 FROM EC 33 KBC_MUTE#


KBC_MUTE# D9 S-BAS40WS PD# R282 10KR0402 AVDD_5V
Tie PGND to DGND
AGND AGND VB=10K

GND GND AGND GND

DEPOP CIRCUIT

4 4

MICRO-STAR INT'L CO.,LTD.


Title

AUDIO(ALC269)
Size Document Number Rev
Custom 0B
MS-14851
Date: Friday , December 02, 2011 Sheet 37 of 53
A B C D E

https://vinafix.com
A B C D E

+3VALW
MEC1

PL3 X_80L6A-30_0805-RH
DC_IN+ +VBATA
PQ21
1 PL4 80L6A-30_0805-RH +DC_IN 1 8 BAT9P_BLACK-RH-8
4 2 2 7 PR2 PC5 C0.1u25X0603 9 X2 4
3 3 6 100KR0402 8 VBATA+GND X1
PC72 PC71 PC70 PC68 PR74 VBATA+GND
4 4 5 7
PC60 PC64 PC63 NC
6

X_C2200p50X0402
NC

C0.1u25X0603
C220p50N0402
C1U25X0805 200KR0402 P-ANPEC0417 5

X_C10u25X51206
X_C0.01u25X0402
MEC2

SMBCLK

C0.1u25X0603
33,39 BATCLK_M
4
PR69 33,39 BATDATA_M SMBDATA
3
150KR0402 33 BAT_IN#
2 BAT_IN#
GND
1
PC2 PC3 PC4 GND

N32-1040B30-A81

X_C10p50N0402

X_C10p50N0402
X_C0.1u16Y0402
CONN2

D Z3102
P-DTA114
PU7
Z3101

G PQ24
33 AC_CTL
N-2N7002_SOT23-1 N91-09M0071-AF2

S
PR76
100KR0402

+3VALW
3 3

X_1uF,10V,X7R,
PR3 SDC_IN+

PC6
100KR0402 PQ18B
P-ANPEC4927

5 3
6

4
D2

D1
PQ3
NN-2N7002DW_SOT363-RH PR5 10KR0402 PR7 100KR0402

G2
S2
G1
S1
2
33,39 AC_OK# 2
PD2 ES3BB-13-F-RH

+VBATA
PQ4B
PQ4A
P-ANPEC4927 P-ANPEC4927 PQ18A
P-ANPEC4927

V_CHG 7 1 3 5 7 1 PWR_SRC
8 6 8
2

2
PC7 C0.1u25X0603

PR4 10KR0402 PR8 100KR0402 PR67


470KR0402
D

CHG_BAT_N
33 ENCHG G
1
PQ2 1
N-2N7002_SOT23-1
S

MICRO-STAR INT'L CO.,LTD.


Title

Battery select
Size Document Number Rev
Custom 0B
MS-14851
Date: Friday, December 02, 2011 Sheet 38 of 53
A B C D E

https://vinafix.com
5 4 3 2 1

Adapter= 90W
SDC_IN+
Adapter input voltage set 19 Voltage
PR68
D DC_IN+ D

0.01R1%XTRA

EMCC2 PC62
X_2200p50X4 10u25X12

PC45 PC50

PR52 0.1u25X0402 0.1u25X0402


412K1%4

PC48

GND_BQ24707 GND_BQ24707 SDC_IN+


0.1u25X0402
+3VALW PC38 DC_IN+

1
PU6
PR64

ACN
ACP
10R0402-1
PR56 X_0.1u25Y4
237K/4 PR54 66.5K1%4 ACIN 6 20 1U25X5 PC54

2200p50X4

10u25X12

10u25X12
C GND_BQ24707 ACDET VCC GND_BQ24707 C

PC40

PC49

X_10u25X12
C0.1u25X5R
PC56

PC57

PC51
10 1U25X5 PC52
ILIM

16 PD3 S-RB751V-40
PR55 REGN PC55
PQ19
127K/4 33,38 BATDATA_M 8 17 C0.047u25X0603
SDA BTST
1 8
33,38 BATCLK_M 9 18 2.2R0603 PR66 PL2
SCL HIDRV V_CHG
PR65
PR58 10K/4 19 2 7 1 2
+3VALW PHASE
GND_BQ24707
PR59 5 15 10u5.5A 0.02R1%XTRA
PR60 33,38 AC_OK# ACOK LODRV
X_10K/4

10u25X12
3 6

PC53

PC43
X_10u25X12

PC46

PC42
X_10K/4 11 14 PR71

10u25X12
0.1u25X5R
IFAULT GND
X_2.7R
4 5 PR63 PR62

PC61

X_2200p
10R1%0603 7.5R1%0603
PR61 3 13
CMPOUT SRP AO4932
X_3M/4
4 12 SOIC8 PC44
CMPIN SRN
B B
PR57
0.1u25X0402
7 PC41

PowerPad
IOUT
0.1u25X0402
X_39.2K1%4 PC47
PR53 0.1u25X0402
X_100K1%4 TI BQ24707RGRR GND_BQ24707
21
PC39 GND_BQ24707
100p16X70402

GND_BQ24707
GND_BQ24707
GND_BQ24707
33 IOUT

JNC19 X_COPPER
NC_93519

A GND_BQ24707 A

MICRO-STAR INT'L CO.,LTD.


Title

Charger
Size Docum ent Num ber Rev
Cus tom 0B
MS-14851
Date: Friday, Decem ber 02, 2011 Sheet 39 of 53
5 4 3 2 1

https://vinafix.com
A B C D E

PQ27
NN-2N7002DW-7-F_SOT 363-6-RH

S1
33 SUS_ON G1 D1 PR89 100KR0402 +5VALW
S2
G2 D2 JNC26 X_R/2

GND_T PS51125
4 4

PR82
C0402
20KR1%0402 1U6.3X

PC83 PR84
20KR1%0402
3VSUS_EN
PR80 0R0402

VREF
3V_FB 5V_FB
PR85 30KR1%0402

PR83
13KR1%0402
GND_T PS51125 GND_T PS51125
PR81 PR88 PWR_SRC
PWR_SRC X_107KR1%0402 97.6KR1%0402-RH

1
+3VALW

ENTRIP2

FB2

TONSEL

FB1

ENTRIP1
REF
PC89 PC88 PC85 PC86
PC78 PC76 PC77
C4.7u6.3X0805 PR86

C0.1u25X0603

C10u25X51206
X_C10u25X51206
X_C2200p50X0402
PC80 3V_OUT 7 24 5V_OUT 10KR0402

C0.1u25X0603

C10u25X51206
VOUT2 VOUT1

X_C2200p50X0402
Current limit at 7A for +3VSUS 8 23
+3VALW VREG3 PGOOD SUSPWROK 33
Imax at 6A PC79 PR79
C0.1u25X0603
4.7R0603
PR87 PC84
4.7R0603 C0.1u25X0603
9 22 Current limit at 8A for +5VSUS
BOOT2 BOOT1 PQ28 NN-AO4932_SOIC8-RH
PQ26 NN-AO4932_SOIC8-RH
1 8
HL3V 10
UGATE2 UGATE1
21
HL5V 8 1
Imax at 7A
2 7 LL3V 11 20 LL5V 7 2
3V_OUT 1 2 5 3 PHASE2 PHASE1 DL5V 3 5 1 2 5V_OUT
+3VSUS +5VSUS
6 4 DL3V 12 19 4 6
PCHOKE3 LGATE2 LGATE1

SKIPSEL
3 PCHOKE4 3

1
VREG5
CH-4.7u10A40m S-RH-2 CH-4.7u10A40m S-RH-2

+
PEC10 PC100

GND
1

VIN
EN

NC
PR78 25 C220u6.3pSO
+

2
PC74 PEC9 X_2.2R0603 GND PR90 C0.1u25X0603
C220u6.3pSO PU8 X_2.2R0603
2

13

14

15

16

17

18
T PS51125RGER_QFN24-RH
C0.1u25X0603

PC75 GND_T PS51125


X_C470p50X0402 PC87
+5VALW
X_C470p50X0402

5
6
7
8
PC82
RUND 4
PQ25 22U10X
N-AO4468_SOIC8-RH VREF C0805_67
8
7
6
5

PWR_SRC

3
2
1
PQ29
4 PR77 10KR0402 RUND N-AO4468_SOIC8-RH

PC81
PC73
1
2
3

C0.1u25X0603
C0.1u25X0603

+5VRUN

+3VRUN
PJNC3 X_COPPER
NC_93519

2 2
GND_T PS51125

PWR_SRC PWR_SRC

PR39 PR38

NN-2N7002DW-7-F_SOT363-6-RH
100KR0402 33KR0402

RUND 36

D1

D2
PC30 PR36
C0.1u25X0603470KR0402

PQ11

S1
G1
S2
G2
33,41,42,45 RUN_ON PR40
100KR0402

PR41
100KR0402

1 1

MICRO-STAR INT'L CO.,LTD.


Title

System Power
Size Docum ent Num ber Rev
Custom 0B
MS-14851
Date: Friday, Decem ber 02, 2011 Sheet 40 of 53
A B C D E

https://vinafix.com
A B C D E

PWR_SRC

4 4

D
PQ20
G PC65 PC66 PC59 PC58

C0.1u25X0603

C10u25X51206

C10u25X51206
C2200p50X0402
PU2 2.2R0603 PC10
Current limit at 18A for +1_5VDIMM
PR16 C0.1u25X0603
1 10 AOL1426_ULTRASO-8-RH
Imax at 15A
PGOOD VBST
PR9 2 9 PCHOKE2
100KR1%0402 TRIP DRVH CH-0.56u25A1.8m S-RH-1 +1_5VDIMM
33 DIMM_ON JNC4 X_R/2 3 8
EN SW
4 7 +5VSUS
VFB V5IN

1
5 6 PR75 PC67

+
GND

D
RF DRVL PQ23 X_2.2R0603 PEC7 PEC8
G

2
TPS51218DSCR_SON10-RH

11

C0.1u25X0603
S

C330u2.5pSO

C330u2.5pSO
PR12 PC9 PC69
464KR1%0402 C1u6.3Y0402-RH X_C470p50X0402

AOL1412_ULTRASO-8-RH
3 3

PR10
13.3KR1%0402

+3VSUS
S0 Mode--EC_S3=Low : 1.5V
PR6
PR11
11.8KR1%0402
X_69.8KR1%0402
PR13
S3 Mode--EC_S3=High: 1.35V
PQ6 X_100KR0402
D

X_N-2N7002_SOT23-1
G
S

C
PC8 PR14 X_10KR0.1%0402-RH
B
EC_S3 33
X_C0.1u25X0603 E
PQ5
X_N-SST3904_SOT23

+1_5VDIMM
2 2

PC15
PC16

+5VSUS +1_5VDIMM
C0.1u25X0603
C4.7u101206

PU3
9
thermal pad(GND) PC12
1 8
PR73 2 VIN NC1 7 PC11
C4.7u10Y0805
X_10KR1%0402 3 GND NC2 6 X_C0.1u25X0603
PR17 VREF VCNTL
4 5
10KR1%0402 VOUT NC3
+5VRUN
APL5331KAC-TRL_SOP8-RH
5 +1_5VRUN_PWGD
D1

D2

PR70 PR18 PC18


X_1KR1%0402 10KR1%0402 C0.1u16Y0402 +0_75VRUN
S1
G1
S2
G2

PR72 X_0R0402 PC14 PC13


33,40,42,45 RUN_ON

1
PQ22
X_NN-2N7002DW-7-F_SOT363-6-RH
PC17
C0.1u16Y0402 2A 1
X_C22u6.3X1206

C22u6.3X1206

MICRO-STAR INT'L CO.,LTD.


Title

DIMM_1.5VRUN
Size Docum ent Num ber Rev
Cus tom 0B
MS-14851
Date: Friday, Decem ber 02, 2011 Sheet 41 of 53
A B C D E

https://vinafix.com
A B C D E

+3VRUN PWR_SRC

D
PQ30 PC90 PC95 PC93 PC94
PR32 G
10KR1%0402

C2200p50X0402

C0.1u25X0603

C10u25X51206

C10u25X51206
S Current limit at 16A for +VTT
4 4
PU4 2.2R0603 PC29 Imax at 13.5A
PR35 C0.1u25X0603
1 10
43 +VTT_PWRGD PR28 PGOOD VBST AOL1426_ULTRASO-8-RH
PR26 2 9 PL5
TRIP DRVH CH-0.56u25A1.8m S-RH-1 +VTT
82.5KR1%0402 3 8 LL_VTTCORE
33,40,41,45 RUN_ON EN SW
4 7 +5VSUS
10KR1%0402 VFB V5IN

1
5 6 PR92 PC106

+
GND

D
RF DRVL PQ34
PC22 X_2.2R0603 PEC13 PEC12
C0.68u10X0603 DL_VTTCORE G

C0.1u25X0603
2

2
TPS51218DSCR_SON10-RH

11

C330u2.5pSO-RH

C330u2.5pSO-RH
S
PR22 PC28 PC98
464KR1%0402 C1u6.3Y0402-RH X_C470p50X0402

AOL1412_ULTRASO-8-RH

PR24 PR23
10KR1%0402
VTT_SENSE 7

X_0R5%
PR25
3 3
20K1%4

+5VSUS
PC110

4.7U10Y
+3VRUN
6

2 PU9 2
PC109
Imax at 2A
VCNTL

5
VIN1
9 4.7U10Y
VIN2 +1_8VRUN
7
POK
4 +1_8VOUT
VOUT1
8
EN
3
VOUT2 PR95 PC113 PC112
22.6K1%4 C0.1u25X0603
2 C22u6.3X1206
FB
GND

PC111
1

APL5912KAC-TRL_SOP8-RH C0.1u25X0603
PR94
18K0402 1%
1

1 1

MICRO-STAR INT'L CO.,LTD.


Title

VTT_1.8VRUN

https://vinafix.com
Size Docum ent Num ber Rev
Cus tom 0B
MS-14851
Date: Friday, Decem ber 02, 2011 Sheet 42 of 53
A B C D E
A B C D E

+5VSUS

PWR_SRC
4 4

PR153
2.2R0603 +5VSUS

PC163 PC160
+3VSUS +3VSUS C0.1u25X50402 C10u25X51206

+3VRUN PC168 PC169


PR166 PR167 C0.1u25X50402 C1u16X5R0402
X_10KR0402 X_10KR0402
PR150
10KR0402 95870B_AGND

17
PU11
3 18

VCC
8 VCCSA_SEL1 VID0 PVCC 2.2R0603 PC165
2 PR149 C0.1u25X0603
8 VCCSA_SEL0 VID1 16
Current limit at 8A for +0.85VRUN
BOOT
PR159 PR160
33 +0.85V_PWRGD
12
PGOOD Imax at 6A
10KR0402 10KR0402 15 DH_0V85
13 UGATE PQ45 NN-AO4932_SOIC8-RH
42 +VT T _PWRGD EN +0_85VRUN
8 1 PL10
14 7 2 CH-1.5u18A15m S-RH-1
VCCUSA_SENSE_FB PR157 357R1%0402 PHASE 3 5
3 3
4 6

PC171 8 19 DL_0V85

1
X_C0.1u25X50402 FB LGATE PC35

+
PR155 PC170 RT N1 1 PR147 PEC16 PC34
1KR1%0402 X_C0.1u25X50402 RTN X_2.2R0603 C10u25X51206

2
9 PR156 14.7KR1%0402
OCSET

C560u2.5pSO
PC172

X_C0.1u25X0603
X_C0.1u25X50402 4 10
SREF VO PC167 PC164 PR158 357R1%0402 RT N1
C6800p25X0402-HF X_C470p50X0402
5 PR154 14.7KR1%0402
6 SET0 11 PR165

PGND
7 SET1 FSEL 1KR1%0402

GND
SET2 PC166
+5VSUS X_C0.1u25X50402
ISL95870BHRZ-T _QFN20

21

20
PR161
PR148
22.6KR1%0402 PR163 PR152 95870B_AGND 95870B_AGND
24.9KR1%0402 X_10KR0402 VCCUSA_SENSE_FB VCCUSA_SENSE 8

X_0R5%
PR162 95870B_AGND
2 30KR1%0402 PR151 2
VID STATE RESULT PC173 X_10KR0402
C0.1u25X50402

VID1 VID0 VSREF Vout


PR164
221KR1%0402
1 1 VSET1 0.675V 95870B_AGND

1 0 VSET2 0.725V
J41 X_COPPER
NC_93519
0 1 VSET3 0.8V

0 0 VSET4 0.9V 95870B_AGND

1 1

MICRO-STAR INT'L CO.,LTD.


T itle

0.8V
Size Docum ent Num ber Rev
Custom 0B
MS-14851
Date: Friday, Decem ber 02, 2011 Sheet 43 of 53
A B C D E

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A B C D E

PWR_SRC

D
PQ41
G
PC152 PC153 PC151 PC155

1
S

+
C0.1u25X0603
C10u25X51206 C10u25X51206 C2200p50X0402 PEC6 PEC15
C100u25EL-RH C100u25EL-RH

2
AOL1426_ULTRASO-8-RH +VCC_CORE
PL8
4 1 2 4
PWR_SRC +5VSUS

D
PQ43 PQ44 CH-0.36u60A1.2mS-RH
G G PR146
PR141 PR140
S S X_2.2R/6 PR145 PR144
+3VRUN PR131 3.65KR1% 10KR1% 1R0402 X_10KR1%
1R0603

+VTT +VTT PC154


Parallel

C330u2-RH-1

C330u2-RH-1
PC150

+1

+1
AOL1412_ULTRASO-8-RH X_AOL1412_ULTRASO-8-RH X_1000pF

PEC4

PEC5
PC135 PC130

C1u10X-RH
R230 R234

2
130R1%0402 PR118 C0.22u25X0603 PC138
C0.22U16X7R0603

ISEN1
VSUM+

VSUM-

ISEN2
54.9R1%0402 PR115 C1u10X-RH

1.91KR0402
1.91KR0402

x_0R0402 PR120

23

31

22
33 EC_ALLSYSPG PC131
PU10 ISL95831
0R PAD 0402 PR117 7 25 C0.22u25X-RH

VCCP
VIN

VDD
25,33 EC_PCH_PWROK VR_ON BOOT1 PWR_SRC
4 PR123

D
7 VR_SVID_DATA SDA PQ42
6 26 2.2R/6
7 VR_SVID_CLK SCLK UGATE1
8 G PC158 PC33 PC156 PC157 Current limit at 65A for +VCC_CORE
25 SYS_PWROK PGOOD
3 27 C0.1u25X0603
PGOODG PHASE1
7 VR_SVID_ALERT# 5
ALERT#
S C10u25X51206 C10u25X51206 C2200p50X0402 Imax at 50A
10
VR_HOT# 29
PC134 LGATE1 +VCC_CORE
1nNPO0402 12 28 PL9
PR124 VW VSSP1 AOL1426_ULTRASO-8-RH 1 2
8.06KR1% 17 ISEN1
PR125 ISEN1 PR122 PR142 CH-0.36u60A1.2mS-RH

D
COMP 13 PQ39 PQ40
X_464KR1%0402-HE PC128
150p PC141 PR129 316KR1%0402 COMP G G PR138 PR139
FB 14 36 C0.22u25X-RH PR143
PC136 C39p50N0402 FB BOOT2 PR112 S S X_2.2R/6 3.65KR1% 10KR1% 1R0402 X_10KR1%
PC147 PR130 35 2.2R/6
PC139 470pX7R 50V0402 499R1%0402 UGATE2
1nNPO0402 3.01KR1%0402 PR132 34
Parallel

C330u2-RH-1

C330u2-RH-1
PC149

+1

+1
3.24KR1%0402 PHASE2 PC132

PEC3
PEC14
PR134 18 AOL1412_ULTRASO-8-RH X_AOL1412_ULTRASO-8-RH X_1000pF
7 VCCSENSE VSEN 32

2
PC137 LGATE2
Rdroop C0.22U16X7R0603

ISEN2
33

VSUM+

VSUM-

ISEN1
C330p16N0402
19 VSSP2
7 VSSSENSE RTN
3 16 ISEN2 3
PC127 ISEN2
PC145 1nNPO0402 1
PR136 PC144 PR113 VWG 30 PR116 X_R/2
PWM3 +5VSUS
PR137 8.06KR1%
PR111 15 COMP
C330p16N0402
C1000p50N0402

ISEN3/FB2
X_10R0402-1

X_464KR1%0402-HE 48 PC140 C10p50N0402


COMPG
X_10R0402-1

150p PC123 PR101 475KR1%0603


47
PC125 C120p50N0402 FBG

PC124 PR108 PC115 C470p50N 0603


PC117
+VCC_CORE 2.26KR1%0402 PR99 422R1%0402
2.1KR1%0402-RH 40 C0.22u25X-RH

Vinafix.com
C1200p50X0402-HF PR107 46 BOOT1G PR109
8 VAXG_SENSE VSENG 39 2.2R/6
UGATE1G
PC126
Rdroop 38
C330p16N0402 45 PHASE1G
8 VSSAXG_SENSE RTNG
37
PC119 21 LGATE1G
C1000p50N0402

PC118 ISUMP
PR103 PR102 C330p16N0402 44
X_10R0402-1 X_10R0402-1 20 ISUMPG
ISUMN 43
IMON 9 ISUMNG
NC
IMONG 2
NC 11
24 NTC
VSUM+ PROG1 42
GND

41 NTCG
PR126 PROG2 PWR_SRC
24.9KR1%
PR100

49
16.5KR1%

PR135
2.61KR1% PC142

1
PR128 X_C330p16N0402 PR127 PQ35

+
11KR1% PC146 1.58KR1%0402 G PC105 PC104 PC162 PC159 PC161
C2200p50X0402 C0.1u25X0603 X_C22u25SO-RH-2

2
PC143 S C10u25X51206 C10u25X51206
PR133
C0.22U25X0603
X_C0.022u16X0402-RH

PR119 X_100R1%0402 +VCC_GFXCORE


10KRT/6 Ri AOL1426_ULTRASO-8-RH PL7
2 2
VSUM- 1 2
IMONG
IMON

CH-0.56u28A1.3mS-RH

D
PQ36 PQ37
PC148 G G PR93
Rntc Ci C0.1U25X0603
S S
X_2.2R/6 Current limit at 38A for +VCC_GFXCORE
Imax at 27A
PC108

C330u2-RH-1

C330u2-RH-1
+1

+1
X_1000pF

PEC2

PEC11
AOL1412_ULTRASO-8-RH X_AOL1412_ULTRASO-8-RH PR97
10KR1%
PR121

PR114

2
26.1KR1%

19.6KR1%

PR98
PC133 PC129 1R0402

C18nF16X0402-RH C22nF16X0402-RH

PR104
7.5KR1%
PR110 PR105
PC122 PC121 PC120
681R1%0402 X_C220p50N0402 11KR1%
C0.1U10X7R0402
C0.068U10X7R0402
PR96
PR106 10KRT/6
X_100R1%0402

PC116

C0.1U10X7R0402 Cn Rntc
Ri

1 1

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MICRO-STAR INT'L CO.,LTD.
Title

CPU
Size Document Number Rev
Custom 0B
MS-14851
Date: Friday, December 02, 2011 Sheet 44 of 53
A B C D E
A B C D E

PWR_SRC

+3VRUN

D
PQ33 PC99 PC101 PC96 PC97 PC91
G 2200p50X 0.1U25Y 10u25X 10u25X X_10u25X
DH_M 92
S
R40
10KR0402 GPU_CORE

PU5
AOL1426_ULT RASO-8-RH
4 DGPU_PWRGD 1 10 PR31 4
15,28,33 DGPU_PWRGD PGOOD VBST
PR33
PL6
DGPU_PWR_EN R46 0R0402 2 9 2.2R PC25
TRIP DRVH C0.1u25X0402-2 output=1.0V Imax= 16A
R45 64.9KR1%04023 8 LL_M 92 1 2
33,40,41,42 RUN_ON EN SW Iocp=20.8A
10KR0402 4 7 PC107
+5VSUS

+1
VFB V5IN PQ31 PQ32

C330u2.5pSO-1
PC26 X_C1u10X50402-RH CH-0.56u25A1.8m S-RH-1 PC21 PC103 PC102

+1

+1
5 6 DL_M 92 G G PR91 PR21

GND
RF DRVL X_2.2R 0.1u10X

2
D
PQ8 S S PC23 C330u X_C330u

X_N-2N7002_SOT23-1

2
16 PX_EN G T PS51218DSCR_SON10-RH X_100p16N 5.6KR1%0402

11
PR37 PC92
X_1000p50X

S
R32 PC27
464KR1%0402 C1u10X50402-RH AOL1412_ULT RA AOL1412_ULT RA
X_100KR0402

PR27
13KR1%0402

+1_5VDIM M

3 3
+3VRUN

5
6
7
8
4

PR34 VDDQ
10KR0402

3
2
1
PQ38
N-AO4468_SOIC8-RH

DGPU_PWR_EN
D

DGPU_PWR_EN# G PQ9
27 DGPU_PWR_EN#
2N7002
S

+1_8VRUN

5
6
7
8
+1_8VRUN +1_8VRUN_GPU
4
+1_8VRUN_GPU
R214 X_0R0603

3
2
1
PQ14
N-AO4468_SOIC8-RH
R216 X_0R0603

2 2

PWR_SRC +VT T

PWR_SRC

PR44

5
6
7
8
33KR0402
+VT T PCIE_VDDC
PR42 DGPU_RUND 4
100KR0402
PCIE_VDDC
R144 X_0R0603

3
2
1
PR45 PC31 PQ15
N-AO4468_SOIC8-RH
D1

D2

470KR0402 C0.1u25Y0402-RH R211 X_0R0603

PQ13

NN-2N7002DW_SOT 363-RH
S1
G1
S2
G2

DGPU_PWRGD
PR43 +3VRUN VDDR3
PR46 100KR0402 +3VRUN VDDR3

PC32 PQ12
C0.1u25Y0402-RH D S R111 X_0R0603
X_100KR0402
N-AO3404_SOT 23
G

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1 1

MICRO-STAR INT'L CO.,LTD.


T itle

GPU POWER
Size Docum ent Num ber Rev
Custom 0B
MS-14851
Date: Friday, Decem ber 02, 2011 Sheet 45 of 53
A B C D E
A B C D E

TOP J17 J8 J30 J16


J21 J14 J12 J10 J27 L1_DIFF_4.5/4/20_80 Ohm+ L1_DIFF_4/4/20_85 Ohm+ L1_DIFF_4/6/20_90 Ohm+ L1_DIFF_4/8/20_100 Ohm+
2 L1_9mil_35_Ohm 2 L1_8mil_37.5_Ohm 2 L1_7mil_40_Ohm 2 L1_5.5mil_45_Ohm 2 L1_4mil_50_Ohm L1_DIFF_4.5/4/20_80 Ohm- L1_DIFF_4/4/20_85 Ohm- L1_DIFF_4/6/20_90 Ohm- L1_DIFF_4/8/20_100 Ohm-
1 1 1 1 1

X_H1X2M_BLACK-RH X_H1X2M_BLACK-RH X_H1X2M_BLACK-RH X_H1X2M_BLACK-RH X_H1X2M_BLACK-RH X_H1X4_black-RH X_H1X4_black-RH X_H1X4_black-RH X_H1X4_black-RH

J28 J13
INT3 J18 J15
L3_DIFF_4/4/20_85 Ohm+ L3_DIFF_4/8/20_100 Ohm+
J22 J29 J20 J9 J11 L3_DIFF_5/4/20_80 Ohm+ L3_DIFF_4/4/20_85 Ohm- L3_DIFF_4.5/6/20_90 Ohm+ L3_DIFF_4/8/20_100 Ohm-
2 L3_10.5mil_35_Ohm 2 L3_9.5mil_37.5_Ohm 2 L3_8mil_40_Ohm 2 L3_6.5mil_45_Ohm 2 L3_5mil_50_Ohm L3_DIFF_5/4/20_80 Ohm- L3_DIFF_4.5/6/20_90 Ohm-
1 1 1 1 1
X_H1X4_black-RH X_H1X4_black-RH
X_H1X2M_BLACK-RH X_H1X2M_BLACK-RH X_H1X2M_BLACK-RH X_H1X2M_BLACK-RH X_H1X2M_BLACK-RH X_H1X4_black-RH X_H1X4_black-RH

INT4
J24 J32 J5 J33
1 J2 J7 J25 J3 J6 L4_DIFF_5/4/20_80 Ohm+ L4_DIFF_4/4/20_85 Ohm+ L4_DIFF_4.5/6/20_90 Ohm+ L4_DIFF_4/8/20_100 Ohm+ 1
2 L4_10.5mil_35_Ohm 2 L4_9.5mil_37.5_Ohm 2 L4_8mil_40_Ohm 2 L4_6.5mil_45_Ohm 2 L4_5mil_50_Ohm L4_DIFF_5/4/20_80 Ohm- L4_DIFF_4/4/20_85 Ohm- L4_DIFF_4.5/6/20_90 Ohm- L4_DIFF_4/8/20_100 Ohm-
1 1 1 1 1

X_H1X2M_BLACK-RH X_H1X2M_BLACK-RH X_H1X2M_BLACK-RH X_H1X2M_BLACK-RH X_H1X2M_BLACK-RH X_H1X4_black-RH X_H1X4_black-RH X_H1X4_black-RH X_H1X4_black-RH

BOTTOM
J36 J35 J4 J31
J38 J34 J37 J23 J26 L6_DIFF_4.5/4/20_80 Ohm+ L6_DIFF_4/4/20_85 Ohm+ L6_DIFF_4/6/20_90 Ohm+ L6_DIFF_4/8/20_100 Ohm+
2 L6_9mil_35_Ohm 2 L6_8mil_37.5_Ohm 2 L6_7mil_40_Ohm 2 L6_5.5mil_45_Ohm 2 L6_4mil_50_Ohm L6_DIFF_4.5/4/20_80 Ohm- L6_DIFF_4/4/20_85 Ohm- L6_DIFF_4/6/20_90 Ohm- L6_DIFF_4/8/20_100 Ohm-
1 1 1 1 1

X_H1X2M_BLACK-RH X_H1X2M_BLACK-RH X_H1X2M_BLACK-RH X_H1X2M_BLACK-RH X_H1X2M_BLACK-RH X_H1X4_black-RH X_H1X4_black-RH X_H1X4_black-RH X_H1X4_black-RH

SDC_IN+ +VBATA PWR_SRC +3VALW +3VRUN +5VRUN +5VSUS USB5V_PT1


X_C0.1u25X5R

X_C0.1u25X5R

X_C0.1u25X5R

X_C0.1u25X5R

X_C0.1u25X5R

X_C0.1u25X5R

X_C0.1u25X5R

X_C0.1u25X5R

X_C0.1u25X5R

X_C0.1u25X5R

X_C0.1u25X5R

X_C0.1u25X5R

X_C0.1u25X5R

X_C0.1u25X5R

X_C0.1u25X5R

X_C0.1u25X5R

X_C0.1u25X5R

X_C0.1u25X5R

X_C0.1u25X5R
EC35

EC36

EC34

EC31

EC37

EC33

EC32

EC28

EC3

EC4

EC44

EC45

EC26

EC38

EC7

EC25

EC30

EC29

EC43
+1_5VDIMM

2 2
X_C0.1u25X5R

X_C0.1u25X5R

X_C0.1u25X5R

X_C0.1u25X5R

X_C0.1u25X5R

X_C0.1u25X5R

X_C0.1u25X5R

X_C0.1u25X5R

X_C0.1u25X5R

X_C0.1u25X5R

X_C0.1u25X5R

X_C0.1u25X5R

X_C0.1u25X5R

X_C0.1u25X5R

X_C0.1u25X5R
EC14

EC19

EC15

EC22

EC24

EC18

EC20

EC21

EC23

EC11

EC9

EC17

EC16

EC13

EC12

HOLES_8X8_D3MM_VIA8 HOLES_8X8_D3MM_VIA5 HOLES_8X8_D3MM HOLES_8X8_D3MM FM13 FM2 FM6 FM16


MH11 X_8x8 MH5 X_8x8 MH9 X_8x8 MH6 X_8x8 1 1 1 1
9 5 2 4
2 6 3 5
3 (NPTH) 7 (NPTH) 6 (PTH) (PTH)
4 8
RACK1 RACK2

FM18 FM15 FM3 FM7


TOP SPRING
1

1 1 1 1

PCIE_H2
PAD3
Spacer
HOLES_8X8_D3MM_VIA5 HOLES_8X8_D3MM_VIA3 HOLES_8X8_D3MM_VIA8 X_RACK X_RACK X_HS-MS1011-RH
Support
MH7 X_8x8 MH3 X_8x8 MH8 X_8x8 FM11 FM4 FM12 E2P-6310611-K23 E2P-6310611-K23
2 4 2 3 9 5 1 1 1 E2B-1634010-RH

1
1
3 5 4 2 6
6 3 7

1
(NPTH) (NPTH) (NPTH)
10 4 8 PCBA1

MY LAR5 MY LAR6
1

3 FM9 FM17 FM14 3


1 1 1
PAD4 PAD2 PCI-E Stand off
X_HS-MS1011-RH X_HS-MS1011-RH

PCB
E2B-1634010-A89 X_MY LAR X_MY LAR

1
E2Y -4811611-Y 40 E2Y -4811611-Y 40

1
FM8 FM5 FM10
1 1 1

MY LAR7 MY LAR8

HOLES_8X8_D3MM HOLES_8X8_D3MM_VIA3 HOLES_8X8_D3MM_VIA3 X_MY LAR X_MY LAR


MH10 X_8x8 MH2 X_8x8 MH4 X_8x8 BRAKET1 E2Y -4820311-Y 40 E2Y -6111911-Y 40
2 3 2 3
4 4
(PTH) (NPTH) (NPTH)
10 10

X_CPU SCREW HOLE X_CPU SCREW HOLE MY LAR9 MY LAR10

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1

PCH X_PCH SCREW HOLE


CPU Braket
E2M-4850111-A89

UME2
X_MY LAR X_MY LAR
1

HOLES_R177D91
CPU_H2 CPU_H3 E2Y -4820311-Y 40 E2P-4811911-G40
1

X_PCH SCREW HOLE E2B-1676010-RH


1

PCH_H2
X_E2B-1676010-RH

MY LAR2 MY LAR4
1

PCH_H3 PCH_H4 MY LAR3


CPU E2B-1634010-A89
1

CPU_H4
X_Stand of f

E2B-1676010-L63 X_MY LAR_DDR


E2P-0112911-G40 X_MY LAR_MIDDLE
X_MY LAR_MIC
E2P-4813211-G40
E2P-4812211-G40

4 4

MICRO-STAR INT'L CO.,LTD.


Title

EMI/Screw
Size Document Number Rev
Custom 0B
MS-14851
Date: Friday , December 02, 2011 Sheet 46 of 53
A B C D E
A B C D E

USB5V_A

USB_A2
USBASM_BLACK-RH-4
+3VRUN_A

Clock R23 R22

MEC2
ECA3 CA21 CA20
X_C10u10Y0805 C0.1u16Y0402 X_C1000p50X0402

5
RA5 XT LO CA14 C18p50N0402 48MHz USB 2.0 PORT 3
X_100K GND_A GND_A GND_A 1
YA2
4
1
3
2 12MHZ16p_S-1
24MHz USB_P0P_A 2 3 2

USB_P0N_A 1 4 3
Reserved
CA13 +3VRUN_A +3VRUN_A 12MHz

X_C10p0402

X_C10p0402
1.0uF LA3 4
RA4 X_10K XT LI CA15 C18p50N0402 X_CMC-L12-9008064-RH

CIA3

CIA2
12MHz

MEC1

6
GND_A CA11 1.0uF RA6 GND_A
GND_A
10K (Crystal) USB5V_A

N53-04M0570-AF2

SD_CD#
GND_A

SD_WP
1 1
GND_A

RREF

XTLO

XTLI
RA3 USB_A3
6.2K 1% USBASM_BLACK-RH-4

1 +
ECA2 CA18 CA23

48

47

46

45

44

43

42

41

40

39

38

37

MEC2
U18 C220u6.3pSO C0.1u16Y0402 X_C1000p50X0402

2
XTLO

GPIO
RREF

NC

XTLI/CLK_IN

CLK_MODE[0]
DV18

RST#

MS_INS#

SD_CD#

SP15

SP14

5
GND_A GND_A GND_A
1
LA4

13
SDCONA2 USB_P1P_A 1 4 2
USB 2.0 PORT 4

GND
SD_D3 1 USB_P1N_A 2 3 3
SD_CMD CD/DAT 3
2
CMD

X_C10p0402

X_C10p0402
USB_P9N_A 1 36 3 4
DM SP13 CARD_3V3 VSS X_CMC-L12-9008064-RH

CIA5

CIA4
4
USB_P9P_A SD_CLK VDD
2 35 5
DP SP12 CLK
6
VSS

MEC1

6
3 34 SD_D0 7
NC SP11 CA10 CA7 SD_D1 DAT 0
8
C10u10Y0805 C0.1u16Y0402 SD_D2 DAT 1
4 33 9
NC SP10 DAT 2
5
NC SP9
32 SD_CD# 10
11
CD SW
GND_A N53-04M0570-AF2
6
NC RTS5139 SP8
31 GND_A GND_A SD_WP 12
CD/WP COM
WP
7 30
NC
LQFP48 SP7
MEC1
MEC1

GND
GND_A 8 29 MEC2
GND SP6 MEC2
+3VRUN_A 9 28
NC SP5 PSDBT 4-09GLAG1N14N1

14
10 27 RA7 10K DV33_18
NC CLK_MODE[1]
11
3V3_IN GND
26 GND_A N5J-09F0110-N40
Card_3V3 12 25 SD_D2
Card_3V3 SD_D2 GND_A +5VSUS_A USB5V_A
CA9 CA8 PCBA2
10uF 0.1uF
FB2
1 2
GND_A GND_A
SD_CMD
DV33_18
XD_CD#

SD_CLK

F-MINISMDC150
PCB
SD_D1

SD_D0

SD_D3
GND

SP1

SP2

SP3

SP4
13

14

15

16

17

18

19

20

21

22

23

24

2 2
PCB_V10
DV33_18

GND_A
SD_CMD
SD_CLK
SD_D1

SD_D0

SD_D3

CA16 CA12
X_4.7uF 0.1uF

GND_A GND_A

MYLARA1 MYLARA2

SCREW HOLES
HOLES_8X8_D3MM_VIA8 HOLES_8X8_D3MM_VIA8
MHA3 X_8x8 MHA2 X_8x8 X_MYLAR_1 X_MYLAR_1
9 5 9 5 X_NPT H63 X_NPT H63 E2P-4811911-G40 E2Y-4811711-Y42
2 6 2 6
3 7 3 7 2010/11/18 add for ME request
4 8 4 8

HA3 HA2
1

3 3

RA2
MIC1_VREFO_L_A 4.7KR0402

MEC2
MEC2

RA8
MIC1_VREFO_R_A 4.7KR0402
FRONT _JD#_A 5
MIC_JD#_A 5 4 +3VRUN_A
4 DEPOP_R_A LA7 300L300mA DEPOP_R_A_L 3
MIC1_R_A CA19 4.7u10X LA5 300L300mA MIC1_R_A_L 3 6

33
6 DEPOP_L_A LA6 300L300mA DEPOP_L_A_L 2 EARPHONE
MIC1_L_A CA4 4.7u10X LA2 300L300mA MIC1_L_A_L 2 1 CA17
1 (BLACK) X_0.1uF
MIC
2

2
LOUT A2 1

MEC1
CA26 CA6
EDA3 EDA2 MICA2 CA24 CA25 CA27 CA28 EDA4 EDA5 2
MEC1

CA5 CA22 ESD ESD ESD ESD GND_A 3


X_C100p16N0402
X_C100p16N0402 X_C680p16X0402-RH X_C100p16N0402 +5VSUS_A +5VSUS_A 4
1

1
X_C680p16X0402-RH X_C680p16X0402-RH X_C100p16N0402 AUDIO_JACK_6P_OB 5
X_C680p16X0402-RH AUDIO_JACK_6P_OB JACK-AUDIOF_PK-SP-RH-1 6
JACK-AUDIOF_PK-SP-RH-1 7

N54-06F0481-A10 N54-06F0481-A10 CA2 CA3


X_0.1uF X_0.1uF GND_A
8
9
AGND_A AGND_A AGND_A AGND_A AGND_A AGND_A AGND_A USB_P9P_A 10
AGND_A
CARD READER USB_P9N_A 11
GND_A GND_A GND_A 12
USB 2.0 PORT 4 USB_P1P_A 13
USB_P1N_A 14
GND_A 15
USB_P0P_A 16
USB 2.0 PORT 3 USB_P0N_A 17
GND_A 18
19
20
GND_A 21
AGND_A 22
FRONT _JD#_A 23
DEPOP_R_A 24
DEPOP_L_A 25
AGND_A 26
MIC_JD#_A 27
MIC1_VREFO_L_A 28
MIC1_VREFO_R_A 29
MIC1_R_A 30
MIC1_L_A 31
4
AGND_A 32 4

34
FPC32P-B-0.5PIT CH_WHIT E-RH
CONA2

GND_A

N5A-32F0030-A81 MICRO-STAR INT'L CO.,LTD.


T itle

Cardreader,Audio,USB
Size Document Number Rev
Custom 0B
MS-14851
Date: Friday, December 02, 2011 Sheet 47 of 53
A B C D E

https://vinafix.com
A B C D E

+3VALW_B

PCBA3

C
DB2 RB2

X_S-RB551V-30_SOD323 X_10KR
PCB

A
1 1
PWR_SW#_B

CB2
PCB_V10
C0.1u10X0402
N5A-14F0090-A81
FPC14P-T-0.5PITCH_WHITE-RH

GND_B 15
SW-TACTB1-6PS-RH-2 SW-TACTB1-6PS-RH-2 SW-TACTB1-6PS-RH-2
N71-0101630-D02 N71-0101630-D02 N71-0101630-D02 +3VALW_B 1
SWTA_S6_5_2X6_3 SWTA_S6_5_2X6_3 SWTA_S6_5_2X6_3 PWR_SW#_B 2
Turbo_SW#_B 3
Display_SW#_B 1 2 ODD_EJECT_SW#_B 1 2 Cinema Pro_SW#_B 1 2 Device key_SW#_B 4
JNCB3 X_0402 A B JNCB2 X_0402 A B JNCB6 X_0402 A B Cinema Pro_SW#_B 5
Display_SW#_B 6
ODD_EJECT_SW#_B 7
E F E F E F 8
LED_PWR#_B 9
LED_Device key#_B 10
LED_Cinema Pro#_B 11
C D C D C D LED_Turbo#_B 12
13
SWB3 SWB2 SWB6 +5VRUN_B 14
CIB3 CIB2 CIB6
2 X_C0.1u16Y0402 X_C0.1u16Y0402 X_C0.1u16Y0402 16 2

GND_B GND_B GND_B GND_B GND_B GND_B CONB2

SW-TACTB1-6PS-RH-2 SW-TACTB1-6PS-RH-2 SW-TACTB1-6PS-RH-2


N71-0101630-D02 N71-0101630-D02 N71-0101630-D02
SWTA_S6_5_2X6_3 SWTA_S6_5_2X6_3 SWTA_S6_5_2X6_3

Turbo_SW#_B 1 2 Device key_SW#_B 1 2 PWR_SW#_B 1 2


JNCB4 X_0402 A B JNCB5 X_0402 A B JNCB7 X_0402 A B

E F E F E F
+5VRUN_B LED
1 2 LED_PWR#_B
C D C D C D DB3 LED04-B-20mA3.8V_3216-RH

SWB4 SWB5 SWB7


CIB4 CIB5 CIB7 RNB2
X_C0.1u16Y0402 X_C0.1u16Y0402 X_C0.1u16Y0402 1 2
3 4 1 2 LED_Turbo#_B
5 6
7 8 DB4 LED04-O-30mA2.0V_320160-HF Stuff orange LED for Discrete
3 GND_B GND_B GND_B GND_B GND_B GND_B 3
8P4R-220R0402

SCREW HOLES
MHB3 MHB2
X_R6.2D2.7 X_R6.2D2.7
holes_r244d106 holes_r244d106
X_NPTH63 X_NPTH63

For EMI
LED_PWR#_B CIB11 X_C100p16N0402
1

HB2 HB3
1

1
LED_Device key#_B CIB9 X_C100p16N0402
GND_B GND_B
LED_Cinema Pro#_B CIB10 X_C100p16N0402
MYLARB1 MYLARB2
LED_Turbo#_B CIB8 X_C100p16N0402

4 +5VRUN_B CIB12 X_C100p16N0402 4

X_MYLAR_Launch X_MYLAR_Launch

E2P-4820111-Y42 E2Y-4820111-Y42 MICRO-STAR INT'L CO.,LTD.


GND_B
Title

Lauch Board
Size Document Number Rev
Custom 0B
MS-14851
Date: Friday, December 02, 2011 Sheet 48 of 53
A B C D E

https://vinafix.com
A B C D E

SWC2 SWC3
SW-TACT-1B SW-TACT-1B
SWTA_S6_5_2X6_3 SWTA_S6_5_2X6_3

18
LEFT_C A B RIGHT_C A B
C D C D CONC2
16 FPC16P-B-0.5PITCH_WHITE-RH
+5VRUN_C
CC2 CC3 15

F
E

E
14
TP_DATA_C 13
X_C0.1u10X0402 X_C0.1u10X0402 TP_CLK_C 12
GND_C CIC2 LED_HDD#_C 11
1 1
GND_C GND_C GND_C LED_BATLOW#_C 10
X_C0.1u10X0402 9
LED_CAP#_C 8
N71-0101630-D02 N71-0101630-D02 GND_C
LED_WLAN#_C
LED_BLUETOOTH#_C
7
6
LED_ACPI#_C 5
LED_CHARGE#_C 4
LED_NUM#_C 3
2
+5VALW_C 1

17
CNC2

13

GND_C GND_C
GND_C
LEFT_C 12
11
10
N5A-16F0110-A81
9
8
RIGHT_C 7
TP_CLK_C 6
TP_DATA_C 5
4
+5VRUN_C
3
2 2 DC4 LED04-B-20mA3.8V_3216-RH 2
1 +5VRUN_C LED
1 2 LED_HDD#_C BLUE D0C-0405230-L05
DC9 LED04-B-20mA3.8V_3216-RH
14
CIC6
X_C0.1u10X0402 RNC2
1 2 LED_BLUETOOTH#_C BLUE D0C-0405230-L05
1 2 DC8 LED04-B-20mA3.8V_3216-RH
FPC12P-B-0.5PITCH_WHITE-RH-3 3 4

GND_C
N5A-12F0200-A81
FPC_S12_3
5
7
6
8
1 2 LED_WLAN#_C BLUE D0C-0405230-L05
DC2
8P4R-220R0402
GND_C 1 2 LED_CAP#_C BLUE D0C-0405230-L05
LED04-B-20mA3.8V_3216-RH
For S8048D-3200 multi finger pin define
MYLARC1 For EMI
2010/03/29 Add TP baord Mylar for ME
LED_HDD#_C CIC11 X_1000P_50V_0402

LED_BLUETOOTH#_C CIC9 X_1000P_50V_0402

X_MYLAR_TP LED_WLAN#_C CIC12 X_1000P_50V_0402

3
E2P-4811811-G40 LED_ACPI#_C CIC14 X_1000P_50V_0402
3
LED_BATLOW#_C CIC8 X_1000P_50V_0402

LED_CHARGE#_C CIC5 X_1000P_50V_0402

DC7 TP_CLK_C CIC3 X_1000P_50V_0402

+5VALW_C
RC5 220R 1 2 LED_ACPI#_C BLUE D0C-0405230-L05 TP_DATA_C CIC4 X_1000P_50V_0402

LED04-B-20mA3.8V_3216-RH LED_CAP#_C CIC10 X_1000P_50V_0402

SCREW HOLES DC6 LED_NUM#_C CIC13 X_1000P_50V_0402


ORANG
PCBA4
MHC2
X_R6.2D2.7
MHC3
X_R6.2D2.7
+5VALW_C
RC4 220R 1 2 LED_BATLOW#_C D0C-0409300-L05 +5VALW_C
CIC7 X_1000P_50V_0402

holes_r244d106 holes_r244d106 X_NPTH63 LED04-O-30mA2.0V_320160-HF

DC5 GND_C
BLUE
PCB +5VALW_C RC3 220R 1 2 LED_CHARGE#_C D0C-0405230-L05
HC2 LED04-B-20mA3.8V_3216-RH
1

DC3

PCB_V10 GND_C GND_C


+5VRUN_C
RC2 220R 1 2 LED_NUM#_C BLUE D0C-0405230-L05
LED04-B-20mA3.8V_3216-RH

4 4

MICRO-STAR INT'L CO.,LTD.


Title

TP,LED Board
Size Document Number Rev
Custom 0B
MS-14851
Date: Friday, December 02, 2011 Sheet 49 of 53
A B C D E

https://vinafix.com
A B C D E

S5-S0 S0-S5
EC programming timing EC programming timing
Intel Huron River timing SPEC Intel Huron River timing SPEC

1 1

DC_IN+ STP_PCI# (From SB)

PWR_SRC
PLTRST# (From SB)
+3VALW+5VALW T1 T1 > 150 us
T0>=150ms
PWR_SW# (To EC) UNCOREPWRGOOD (SB TO CPU)
T2 T2 > 30 us
SUS_ON (From EC)
CLK
+3VSUS/+5VSUS

+3VSUSPWROK (To EC) T3 T3 > 100 us


+VCC_CORE/+VCC_GFXCORE
RSMRST# (EC To SB) T1 T1>10 ms

SLP_S3# (SB to EC)


T0>=16ms T4 T4 > 1 us
PWRBTN# (EC To SB)
SLP_S4# (SB to EC)
T5 T5 > 30 us

SLP_S4# (SB to EC) SLP_S5# (SB to EC)


T6 T6 > 30 us
2 SLP_S3# RUN_ON (From EC) 2

DIMM_ON (From EC) +5VRUN/+3VRUN

+1_5VDIMM +1_8VRUN

RUN_ON (From EC) VTT/+VTT_CORE

+5VRUN/+3VRUN +0_75VRUN

+1_8VRUN EC_ALLSYSPG (To EC)

VTT/+VTT_CORE DIMM_ON (From EC)

+0_75VRUN +1_5VDIMM

EC_ALLSYSPG (To EC) SUS_ON (From EC)

EC_PCH_PWROK (From EC) T4 T4>99 ms +3VSUS/+5VSUS

DRAMPWRGD (SB TO CPU) T5 T5>1 ms (Timing set by PCH) RSMRST#

CLK EC_PCH_PWROK

SYS_PWROK

UNCOREPWRGOOD (SB TO CPU) T6 T6>41 ms (Timing set by PCH)


3
DRAMPWRGD 3
SVID (From CPU to IMVP7)

T7 T7 < 500 us
System State
S0 S3 S4 S5 G3
+VCC_CORE/+VCC_GFXCORE T8 T8 < 50 us

SYS_PWROK (From IMVP7 to SB) T9 T9 < 5 ms

PLTRST# (From SB) T10 T10 > 1 ms (Timing set by PCH)

CKEA[3:0] (From CPU to DDR3 SODIMM)

4 4

MICRO-STAR INT'L CO.,LTD.


Title

Power on Sequency

https://vinafix.com
Size Document Number Rev
Custom 0B
MS-14851
Date: Friday, December 02, 2011 Sheet 50 of 53
A B C D E
A B C D E

Power down Sequence DC mode S0 to G3

1 1

S0-S5
EC programming timing
Intel Huron River timing SPEC

2 STP_PCI# (From SB) 2

PLTRST# (From SB)


T1 T1 > 150 us

UNCOREPWRGOOD (SB TO CPU)


T2 T2 > 30 us

CLK

T3 T3 > 100 us
+VCC_CORE/+VCC_GFXCORE

SLP_S3# (SB to EC)


T4 T4 > 1 us

SLP_S4# (SB to EC)


T5 T5 > 30 us

SLP_S5# (SB to EC)


T6 T6 > 30 us
RUN_ON (From EC)

+5VRUN/+3VRUN
3 3
+1_8VRUN

VTT/+VTT_CORE

+0_75VRUN

EC_ALLSYSPG (To EC)

DIMM_ON (From EC)

+1_5VDIMM

SUS_ON (From EC)

+3VSUS/+5VSUS

RSMRST#

EC_PCH_PWROK

SYS_PWROK

DRAMPWRGD

4 4
System State
S0 S3 S4 S5 G3

MICRO-STAR INT'L CO.,LTD.


Title

Power down Sequency


Size Document Number Rev

https://vinafix.com
Custom 0B
MS-14851
Date: Friday, December 02, 2011 Sheet 51 of 53
A B C D E
5 4 3 2 1

+3VALW
0
POWER Button
POWER Input +3VALW
D D
0
PWR_SRC
PWR_SW#
1 0 SPI
0 GPXIOD4 SPI FLASH
ROM
0
+5VALW 5VSUS_EN SUS_ON 2
0 EN1 GPXIOA01 PM_PWRBTN# :
+3VALW Should be over 150msec
TPS51125
Regulator 3VSUS_EN RSMRST# :
MAX17062ETB+T 3 EN2 Asserted <10mses after
Step up +5VSUS
+5VSUS 3 +3VSUSPWROK=High
+12V_FAN DC-DC +3VSUS SUSPWROK 4
CONVERTER PGOOD GPXIOD0 5 RSMRST#
GPXIOA02 RSMRST# & DPWROK
6 PM_PWRBTN#
+5VSUS PWR_SRC PWRBTN#

PM_SLP_S5# 7 SLP_S5# 19
10 DIMM_ON 9 GPXIOD5 DRAMPWRGD SM_DRAMPWRGD
+1_5VDIMM EN GPXIOA03 PM_DRAM_PWRGD
TPS51117 PM_SLP_S4# 8 SLP_S4# (Delay Min:1ms)
GPXIOD1 21 UNCOREPWRGOOD 22
10a
+1_5VDIMM_PWRGD PGOOD1 PM_SLP_S3# 11 SLP_S3# PROCPWRGD H_CPUPWRGD SVID
GPXIOD2
(Delay Min:41ms)
18 RESET#
+5VSUS +3VSUS PWROK
EC_PCH_PWROK APWROK
20
C SM_DRAMRST# DRAMRST# C
13 D D RUN_ON 24 SYS_PWROK PLTRST# 25
+5VRUN S RUND 12 26
14 G SYS_PWROK PLT_RST# CKE[3:0] CKE[3:0]
+3VRUN S NMOS N-AO4468 GPXIOA04
+5VRUN DDR3
Sandy Bridge SODIMM
+1_5VDIMM
15 27
VTT APL5930KAI-TRG GPIO54
DGPU_PWR_EN#
15 D 15a EN 29
+1_5VRUN S G +1_8VRUN_PWRGD PGOOD2 GPIO17
NMOS N-AO4468 DGPU_PWROK
30
KBC/EC PEG_A_CLKRQ#
PEG_CLKREQ#
15d +5VRUN
+1_5VRUN_PWGD Logic circuit 31
KB3930QFD2-RH CKOUT_PEG_A
CLK_PEGA_MXM
15 APL5930KAI-TRG
+5VRUN +1_5VDIMM +1_8VRUN 32
GPIO50
EN DGPU_HOLD_RST#
15b
VCNTL VIN 15d +1_8VRUN_PWRGD PGOOD2
+0_75VRUN
16
+1_5VRUN_PWGD
PCH
EN
APL5331KAC-TRL +5VSUS PWR_SRC AND GATE
B B
25 33
NC7S08
PLT_RST# PEG_RST#
15
+VTT_CORE TPS51218DSCR
+5VSUS PWR_SRC
15c EN
+VTT_CORE_PWRGD PGOOD2
+3VRUN
16 15c
+0.85VRUN TPS51218DSCR
+VTT_CORE_PWRGD 27
16a EN 28 D DGPU_PWR_EN#
+0.85V_PWRGD PGOOD3 11a +3V_MXM S
17 18 NMOS N-NDS351ANG
+1_5VDIMM_PWRGD GPXIOD3 GPXIOA06
EC_ALLSYSPG delay 99ms EC_PCH_PWROK
15a
+5VRUN
+1_8VRUN_PWRGD
AND Circuit
15c
+VTT_CORE_PWRGD 28 D
+5V_MXM SPMOS G
16a P-IRLML6402PBF
+0.85V_PWRGD

PWR_SRC +3V_MXM +5V_MXM


+5VSUS PWR_SRC
A A

31 29
PWRGOOD
23-a CLK_PEGA_MXM DGPU_PWROK
+VCC_CORE 19
17 30

https://vinafix.com
VR_ON CLKIN_CPU PEX_CLK_REQ#
EC_ALLSYSPG 23-b 18 CLKIN_DMI PEG_CLKREQ#
MAX17039GTN +VCC_GFXCORE SL28770ELC 33 MICRO-STAR INT'L CO.,LTD.
EC_PCH_PWROK CLKIN_GND1
22 CLKIN_DOT PEG_RST# T itle
PGOOD 24
SVID SYS_PWROK CLKIN_SATA MXM 3.0 Power Diagram
Size Docum ent Num ber Rev
C 0B
MS-14851
Date: Friday, Decem ber 02, 2011 Sheet 52 of 53
5 4 3 2 1
A B C D E

0B Modify list
1, Change power net +1_5VRUN to +1_5VDIMM.
2, Co-lay PX4.0 and PX5.0.
4 4

3, Change HDMI CNT footprint to HDMI_D19_11.

3 3

2 2

1
MICRO-STAR INT'L CO.,LTD. 1

Title

History
https://vinafix.com
Size Document Number Rev
A 0B
MS-14851
Date: Friday, December 02, 2011 Sheet 53 of 53
A B C D E

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