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A B C D E

1 1

LCFC Confidential
2 2

VENUS2 M/B Schematics Document


INTEL Ivy Bridge Processor with DDRIII + QS77 PCH

3 2012-12-24 3

REV:0.2

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2012/09/03 Deciphered Date 2012/09/03 Cover Page


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
VENUS2
Date: Saturday, January 26, 2013 Sheet 1 of 46
A B C D E
5 4 3 2 1

D D

DDR3L Channel B Ivy Bridge


SODIMM DDR3L SDP 8W EDP
1333/1600MHz
EDP

FDI DMI
SATA TMDS
mSATA HDMI
USB2.0 X2 HDA HP/MIC COMBO JACK
WiFi/BT Module CX20672-21Z
Panther USB2.0
USB2.0 Point RTS5179-GR CARD READER
USB2.0
SFF QS77 SPI
C

USB3.0 SPI BIOS C

USB3.0
USB2.0
I2C USB2.0 CAMERA
Gyro+G sensor MCU USB2.0
TOUCHPANEL
I2C
e-Compass

I2C
G-Sensor
LPC BUS
ALS I2C
I2C

EC SMBUS B

FAN Battery

PS/2 Thermal sensor


SPI KB LID
ROM TouchPad

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/09/03 Deciphered Date 2012/09/03 Block Diagram


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
VENUS2 0.1

Date: Saturday, January 26, 2013 Sheet 2 of 46


5 4 3 2 1
A B C D E

Voltage Rails ( O --> Means ON , X --> Means OFF )


SIGNAL
+5VS STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
+3VS
Power Plane +1.5VS
Full ON HIGH HIGH HIGH HIGH ON ON ON ON

+VCCSA S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW


+V1.5S_VCCP
S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
+CPU_CORE
1 +3VALW 1

S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF


B+ +1.5V
+GFX_CORE
S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+5VALW +1.8VS
+1.05VS
State +0.75VS
+3.3VS_VGA
+1.5VS_VGA
+1.05VS_VGA
USB Port Table BOM Structure Table
2 External BOM Structure BTO Item
USB 2.0 USB 3.0 Port
USB Port
HDMI@ HDMI part
S0 O O O O 1
0
XHCI CHG@ USB charger part
1
2 NOCHG@ No USB charger part
S3 O O O X EHCI1 3 2 CMOS@ CMOS Camera part
AR8161 LAN part
4 3 USB Port (Left Side)/USB3.0 Port
2
AR8151 LAN part 2
S5 S4/AC Only O O X X 4
5 MCU Sensor Hub
AR8161 LAN surge part
AR8151 LAN surge part
6 WIFI
S5 S4 SURGE@ AR8151&8161 LAN surge part

Battery only O X X X 7 Camera X76 P/N for AR8161


8 X76 P/N for AR8151
EHCI2
9 USB Port (Right Side) X76@ X76 Level part for VRAM
S5 S4 10 Cardreader
GC6@ NV CG6 support part
AC & Battery X X X X 11 Touchpanel
Bluetooth
NOGC6@ NV no CG6 support part
12 AOAC@ AOAC support part
don't exist
13 KBL@ K/B Light part
ME@ ME part
SMBUS Control Table OPT@ For optimus function part

Main WLAN Thermal TP PCIE PORT LIST SLI@ For SLI function part
SOURCE ALS BATT IT8580E SODIMM PCH
VGA WiMAX Sensor Module Port Device DS3@ Deep S3 support part
S3@ For S3 function part

3
1 GT@ NV chip part 3
EC_SMB_CLK IT8519
X V V X X X V X X 2 @ Unpop
EC_SMB_DAT +3VALW_EC +3VS +3VLP +3VS 3
4
EC_SMB_CLK1 IT8519
X X X X X X X V X 5
EC_SMB_DAT1 +3VALW_EC
+3V_PCH 6
7
SMB_CLK PCH
SMB_DATA +3VS
X X X X V X X X V 8
+3VS +3VS +3V_PCH +3VS

Address
EC SM Bus1 address EC SM Bus2 address PCH SM Bus address ZZZ1

4
Device Device Address Device Address 4

Smart Battery 0001 011X b Thermal Sensor EMC1403-2 1001_101xb DDR DIMM0 1001 000Xb
DA80000T10J
Master VGA 0x9E DDR DIMM2 1001 010Xb
Slave VGA 0x9C

Security Classification LC Future Center Secret Data Title

Issued Date 2012/09/03 Deciphered Date 2012/09/03 Notes List


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
VENUS2
Date: Saturday, January 26, 2013 Sheet 3 of 46
A B C D E
5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/09/03 Deciphered Date 2012/09/03 VGA NOTES LIST


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
VENUS2 0.1

Date: Saturday, January 26, 2013 Sheet 4 of 46


5 4 3 2 1
5 4 3 2 1

IVYBRIDGE PROCESSOR(DMI,DP,PEG,FDI)
D D

U1A
G3 PEG_COMP
PEG_ICOMPI G1
M2 PEG_ICOMPO G4
15 DMI_TXN0 DMI_RX#[0] PEG_RCOMPO
15 DMI_TXN1 P6
P1 DMI_RX#[1]
15 DMI_TXN2 DMI_RX#[2]
15 DMI_TXN3 P10 H22
DMI_RX#[3] PEG_RX#[0] J21
N3 PEG_RX#[1] B22
15 DMI_TXP0 DMI_RX[0] PEG_RX#[2]
15 DMI_TXP1 P7 D21
P3 DMI_RX[1] PEG_RX#[3] A19

DMI
15 DMI_TXP2 DMI_RX[2] PEG_RX#[4]
15 DMI_TXP3 P11 D17
DMI_RX[3] PEG_RX#[5] B14
K1 PEG_RX#[6] D13
15 DMI_RXN0 DMI_TX#[0] PEG_RX#[7]
M8 A11
15 DMI_RXN1 DMI_TX#[1] PEG_RX#[8]
N4 B10
15 DMI_RXN2 R2 DMI_TX#[2] PEG_RX#[9] G8
15 DMI_RXN3 DMI_TX#[3] PEG_RX#[10] A8
K3 PEG_RX#[11] B6
15 DMI_RXP0 DMI_TX[0] PEG_RX#[12]
M7 H8
15 DMI_RXP1 DMI_TX[1] PEG_RX#[13]
P4 E5
15 DMI_RXP2 DMI_TX[2] PEG_RX#[14]
T3 K7
15 DMI_RXP3 DMI_TX[3] PEG_RX#[15]
K22
C
PEG_RX[0] K19 C
PEG_RX[1] C21
U7 PEG_RX[2] D19
15 FDI_TXN0 FDI0_TX#[0] PEG_RX[3]
W11 C19
15 FDI_TXN1 FDI0_TX#[1] PEG_RX[4]
W1 D16
15 FDI_TXN2 AA6 FDI0_TX#[2] PEG_RX[5] C13
15 FDI_TXN3 FDI0_TX#[3] PEG_RX[6]
W6 D12
15 FDI_TXN4 V4 FDI1_TX#[0] PEG_RX[7] C11

PCI EXPRESS -- GRAPHICS


15 FDI_TXN5 Y2 FDI1_TX#[1] PEG_RX[8] C9
15 FDI_TXN6 FDI1_TX#[2] PEG_RX[9]
AC9 F8
15 FDI_TXN7 FDI1_TX#[3] PEG_RX[10] C8

Intel(R) FDI
PEG_RX[11] C5
U6 PEG_RX[12] H6
15 FDI_TXP0 FDI0_TX[0] PEG_RX[13]
W10 F6
15 FDI_TXP1 FDI0_TX[1] PEG_RX[14]
W3 K6
15 FDI_TXP2 FDI0_TX[2] PEG_RX[15]
AA7
15 FDI_TXP3 FDI0_TX[3]
W7 G22
15 FDI_TXP4 FDI1_TX[0] PEG_TX#[0]
T4 C23
15 FDI_TXP5 FDI1_TX[1] PEG_TX#[1]
AA3 D23
15 FDI_TXP6 FDI1_TX[2] PEG_TX#[2]
AC8 F21
15 FDI_TXP7 FDI1_TX[3] PEG_TX#[3] H19
AA11 PEG_TX#[4] C17
15 FDI_FSYNC0 FDI0_FSYNC PEG_TX#[5]
15 FDI_FSYNC1 AC12 K15
FDI1_FSYNC PEG_TX#[6] F17
U11 PEG_TX#[7] F14
15 FDI_INT FDI_INT PEG_TX#[8] A15
AA10 PEG_TX#[9] J14
15 FDI_LSYNC0 FDI0_LSYNC PEG_TX#[10]
15 FDI_LSYNC1 AG8 H13
FDI1_LSYNC PEG_TX#[11] M10
PEG_TX#[12] F10
PEG_TX#[13] D9
+1.05VS PEG_TX#[14] J4
DP_COMP AF3 PEG_TX#[15]
AD2 eDP_COMPIO F22
DP_COMP R1 24.9_0402_1% AG11 eDP_ICOMPO PEG_TX[0] A23
22 EDP_HPD eDP_HPD# PEG_TX[1] D24
PEG_COMP R2 24.9_0402_1%
PEG_TX[2] E21
AG4 PEG_TX[3] G19
B 22 EDP_AUX_DN eDP_AUX# PEG_TX[4] B
AF4 B18
22 EDP_AUX_DP eDP_AUX PEG_TX[5] K17
PEG_TX[6] G17
eDP
AC3 PEG_TX[7] E14
22 EDP_TX0_DN AC4 eDP_TX#[0] PEG_TX[8] C15
22 EDP_TX1_DN AE11 eDP_TX#[1] PEG_TX[9] K13
AE7 eDP_TX#[2] PEG_TX[10] G13
eDP_TX#[3] PEG_TX[11] K10
AC1 PEG_TX[12] G10
22 EDP_TX0_DP eDP_TX[0] PEG_TX[13]
AA4 D8
22 EDP_TX1_DP eDP_TX[1] PEG_TX[14]
AE10 K4
AE6 eDP_TX[2] PEG_TX[15]
eDP_TX[3]

AV8063801057404-QC_BGA1023

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/09/03 Deciphered Date 2012/09/03 CPU (1/7) DMI, FDI, PEG
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
VENUS2 0.1

Date: Saturday, January 26, 2013 Sheet 5 of 46


5 4 3 2 1
5 4 3 2 1

IVYBRIDGE PROCESSOR(CLK,MISC,JTAG)

D D

U1B

J3 CLK_EXP_P 14
TP155 BCLK H2
BCLK# CLK_EXP_N 14

MISC

CLOCKS
F49
18 H_SNB_IVB# PROC_SELECT# AG3 CLK_DP_P 14
DPLL_REF_CLK AG1
DPLL_REF_CLK# CLK_DP_N 14
TESTPAD TP19 TP_SKTOCC# C57
PROC_DETECT#

TESTPAD TP2 H_CATERR# C49


CATERR#

THERMAL
A48 AT30
18 H_PECI PECI SM_DRAMRST# CPUDRAMRST# 7

BF44 SM_RCOMP_0

DDR3
MISC
R3 56_0402_5% C45 SM_RCOMP[0] BE43 SM_RCOMP_1
34,43 H_PROCHOT# PROCHOT# SM_RCOMP[1] BG43 SM_RCOMP_2
SM_RCOMP[2]

D45
18 H_THRMTRIP# THERMTRIP#

N53 TP3 TESTPAD


TP83 PRDY# N55 TP4 TESTPAD
TESTPAD PREQ#
L56 TP5 TESTPAD
TCK L55 TP6 TESTPAD
TMS J58

PWR MANAGEMENT
TP7 TESTPAD
TRST#

JTAG & BPM


C 15 H_PM_SYNC C48 M60 TP8 TESTPAD C
PM_SYNC TDI L59 TP9 TESTPAD
TP84 TDO
TESTPAD
18 H_CPUPWRGD B46
UNCOREPWRGOOD K58 TP10 TESTPAD
TP85 DBR#
TESTPAD
VDD_PWRGOOD BE45 G58 TP11 TESTPAD
SM_DRAMPWROK BPM#[0] E55 TP12 TESTPAD
BPM#[1] E59 TP13 TESTPAD
TP86 BPM#[2] G55 TP14 TESTPAD
TESTPAD BPM#[3] G59 TP15 TESTPAD
BUF_CPU_RST# D44 BPM#[4] H60 TP16 TESTPAD
RESET# BPM#[5] J59 TP17 TESTPAD
BPM#[6] J61 TP18 TESTPAD
BPM#[7]

AV8063801057404-QC_BGA1023

+3VS +3V_VCCSUS_PCH +3V_VCCSUS_PCH


+3VS
1

TP166 +1.35V_CPU
R4 TP162 +1.05VS
200_0402_5% R198 C189 1
B B
@ 1K_0402_5%
1

0.1u_0201_10V6K C1
2

U21 R5 U2 0.1U_0402_25V6
1 5 200_0402_5% TP161 3 4 2 R8
15 PM_DRAM_PWRGD A VCC 2A 2Y
75_0402_5%
34,42 ALL_SYS_PWRGD R48 1 2 0_0402_5% 2 TP160 2 5
B GND VCC
2

R132 1 @ 2200_0402_5% 3 4 R6 130_0402_1% VDD_PWRGOOD 17,34 PLT_RST# 1 6 R7 1 2 43_0402_5% BUF_CPU_RST#


2
+3VS GND Y 1A 1Y
2 @
TP168 @ SN74LVC2G07YZPR_WCSP6 C140
SN74AHC1G09DCKR_SC70-5 C139 0.1U_0402_25V6
0.1U_0402_25V6 TP163 1
TP167 TP165 1
DDR3 Compensation Signal
SM_RCOMP_2

SM_RCOMP_1

SM_RCOMP_0
1

R10 R11 R12


Processor Pull-ups
25.5_.402_1%
140_0402_1% 200_0402_1%
2

+1.05VS
H_CPUPWRGD

R9
2

62_0402_1%
R13
A 10K_0402_5% A
1

H_PROCHOT#

Security Classification LC Future Center Secret Data Title

Issued Date 2012/09/03 Deciphered Date 2012/09/03 CPU (2/7) PM, XDP, CLK
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
VENUS2 0.1

Date: Saturday, January 26, 2013 Sheet 6 of 46


5 4 3 2 1
5 4 3 2 1

IVYBRIDGE PROCESSOR(DDR3)

D D

U1C

U1D
12 M_B_DQ[63:0]
AG6
AJ6 SA_DQ[0] AU36
AP11 SA_DQ[1] SA_CK[0] AV36 M_B_DQ0 AL4
AL6 SA_DQ[2] SA_CK#[0] AY26 M_B_DQ1 AL1 SB_DQ[0] BA34
AJ10 SA_DQ[3] SA_CKE[0] AN3 SB_DQ[1] SB_CK[0] AY34 M_CLK_DDR2 12
M_B_DQ2
SA_DQ[4] SB_DQ[2] SB_CK#[0] M_CLK_DDR#2 12
AJ8 M_B_DQ3 AR4 AR22
SA_DQ[5] SB_DQ[3] SB_CKE[0] M_CKE2 12
AL8 M_B_DQ4 AK4
AL7 SA_DQ[6] M_B_DQ5 AK3 SB_DQ[4]
AR11 SA_DQ[7] M_B_DQ6 AN4 SB_DQ[5]
AP6 SA_DQ[8] AT40 M_B_DQ7 AR1 SB_DQ[6]
AU6 SA_DQ[9] SA_CK[1] AU40 M_B_DQ8 AU4 SB_DQ[7]
AV9 SA_DQ[10] SA_CK#[1] BB26 M_B_DQ9 AT2 SB_DQ[8] BA36
SA_DQ[11] SA_CKE[1] SB_DQ[9] SB_CK[1] M_CLK_DDR3 12
AR6 M_B_DQ10 AV4 BB36
SA_DQ[12] SB_DQ[10] SB_CK#[1] M_CLK_DDR#3 12
AP8 M_B_DQ11 BA4 BF27
SA_DQ[13] SB_DQ[11] SB_CKE[1] M_CKE3 12
AT13 M_B_DQ12 AU3
AU13 SA_DQ[14] M_B_DQ13 AR3 SB_DQ[12]
BC7 SA_DQ[15] M_B_DQ14 AY2 SB_DQ[13]
BB7 SA_DQ[16] BB40 M_B_DQ15 BA3 SB_DQ[14]
BA13 SA_DQ[17] SA_CS#[0] BC41 M_B_DQ16 BE9 SB_DQ[15]
BB11 SA_DQ[18] SA_CS#[1] M_B_DQ17 BD9 SB_DQ[16] BE41
SA_DQ[19] SB_DQ[17] SB_CS#[0] M_CS#2 12
BA7 M_B_DQ18 BD13 BE47
SA_DQ[20] SB_DQ[18] SB_CS#[1] M_CS#3 12
BA9 M_B_DQ19 BF12
BB9 SA_DQ[21] M_B_DQ20 BF8 SB_DQ[19]
AY13 SA_DQ[22] M_B_DQ21 BD10 SB_DQ[20]
AV14 SA_DQ[23] AY40 M_B_DQ22 BD14 SB_DQ[21]
AR14 SA_DQ[24] SA_ODT[0] BA41 M_B_DQ23 BE13 SB_DQ[22]
AY17 SA_DQ[25] SA_ODT[1] M_B_DQ24 BF16 SB_DQ[23] AT43
SA_DQ[26] SB_DQ[24] SB_ODT[0] M_ODT2 12
AR19 M_B_DQ25 BE17 BG47
SA_DQ[27] SB_DQ[25] SB_ODT[1] M_ODT3 12
BA14 M_B_DQ26 BE18
AU14 SA_DQ[28] M_B_DQ27 BE21 SB_DQ[26]
BB14 SA_DQ[29] M_B_DQ28 BE14 SB_DQ[27]
BB17 SA_DQ[30] AL11 BG14 SB_DQ[28] M_B_DQS#[7:0] 12
C M_B_DQ29 C
BA45 SA_DQ[31] SA_DQS#[0] AR8 M_B_DQ30 BG18 SB_DQ[29]
AR43 SA_DQ[32] SA_DQS#[1] AV11 M_B_DQ31 BF19 SB_DQ[30] AL3 M_B_DQS#0
AW48 SA_DQ[33] SA_DQS#[2] AT17 M_B_DQ32 BD50 SB_DQ[31] SB_DQS#[0] AV3 M_B_DQS#1
BC48 SA_DQ[34] SA_DQS#[3] AV45 M_B_DQ33 BF48 SB_DQ[32] SB_DQS#[1] BG11 M_B_DQS#2
BC45 SA_DQ[35] SA_DQS#[4] AY51 M_B_DQ34 BD53 SB_DQ[33] SB_DQS#[2] BD17 M_B_DQS#3
AR45 SA_DQ[36] SA_DQS#[5] AT55 M_B_DQ35 BF52 SB_DQ[34] SB_DQS#[3] BG51 M_B_DQS#4
DDR SYSTEM MEMORY A

AT48 SA_DQ[37] SA_DQS#[6] AK55 M_B_DQ36 BD49 SB_DQ[35] SB_DQS#[4] BA59 M_B_DQS#5
AY48 SA_DQ[38] SA_DQS#[7] M_B_DQ37 BE49 SB_DQ[36] SB_DQS#[5] AT60 M_B_DQS#6
SA_DQ[39] SB_DQ[37] SB_DQS#[6]

DDR SYSTEM MEMORY B


BA49 M_B_DQ38 BD54 AK59 M_B_DQS#7
AV49 SA_DQ[40] M_B_DQ39 BE53 SB_DQ[38] SB_DQS#[7]
BB51 SA_DQ[41] M_B_DQ40 BF56 SB_DQ[39]
AY53 SA_DQ[42] M_B_DQ41 BE57 SB_DQ[40]
BB49 SA_DQ[43] M_B_DQ42 BC59 SB_DQ[41]
AU49 SA_DQ[44] AJ11 M_B_DQ43 AY60 SB_DQ[42]
SA_DQ[45] SA_DQS[0] SB_DQ[43] M_B_DQS[7:0] 12
BA53 AR10 M_B_DQ44 BE54
BB55 SA_DQ[46] SA_DQS[1] AY11 M_B_DQ45 BG54 SB_DQ[44]
BA55 SA_DQ[47] SA_DQS[2] AU17 M_B_DQ46 BA58 SB_DQ[45] AM2 M_B_DQS0
AV56 SA_DQ[48] SA_DQS[3] AW45 M_B_DQ47 AW59 SB_DQ[46] SB_DQS[0] AV1 M_B_DQS1
AP50 SA_DQ[49] SA_DQS[4] AV51 M_B_DQ48 AW58 SB_DQ[47] SB_DQS[1] BE11 M_B_DQS2
AP53 SA_DQ[50] SA_DQS[5] AT56 M_B_DQ49 AU58 SB_DQ[48] SB_DQS[2] BD18 M_B_DQS3
AV54 SA_DQ[51] SA_DQS[6] AK54 M_B_DQ50 AN61 SB_DQ[49] SB_DQS[3] BE51 M_B_DQS4
AT54 SA_DQ[52] SA_DQS[7] M_B_DQ51 AN59 SB_DQ[50] SB_DQS[4] BA61 M_B_DQS5
AP56 SA_DQ[53] M_B_DQ52 AU59 SB_DQ[51] SB_DQS[5] AR59 M_B_DQS6
AP52 SA_DQ[54] M_B_DQ53 AU61 SB_DQ[52] SB_DQS[6] AK61 M_B_DQS7
AN57 SA_DQ[55] M_B_DQ54 AN58 SB_DQ[53] SB_DQS[7]
AN53 SA_DQ[56] M_B_DQ55 AR58 SB_DQ[54]
AG56 SA_DQ[57] M_B_DQ56 AK58 SB_DQ[55]
AG53 SA_DQ[58] M_B_DQ57 AL58 SB_DQ[56]
AN55 SA_DQ[59] M_B_DQ58 AG58 SB_DQ[57]
SA_DQ[60] SB_DQ[58] M_B_A[15:0] 12
AN52 BG35 M_B_DQ59 AG59
AG55 SA_DQ[61] SA_MA[0] BB34 M_B_DQ60 AM60 SB_DQ[59]
AK56 SA_DQ[62] SA_MA[1] BE35 M_B_DQ61 AL59 SB_DQ[60] BF32 M_B_A0
SA_DQ[63] SA_MA[2] BD35 M_B_DQ62 AF61 SB_DQ[61] SB_MA[0] BE33 M_B_A1
SA_MA[3] AT34 M_B_DQ63 AH60 SB_DQ[62] SB_MA[1] BD33 M_B_A2
SA_MA[4] AU34 SB_DQ[63] SB_MA[2] AU30 M_B_A3
SA_MA[5] BB32 SB_MA[3] BD30 M_B_A4
BD37 SA_MA[6] AT32 SB_MA[4] AV30 M_B_A5
B
BF36 SA_BS[0] SA_MA[7] AY32 SB_MA[5] BG30 M_B_A6
B
BA28 SA_BS[1] SA_MA[8] AV32 BG39 SB_MA[6] BD29 M_B_A7
SA_BS[2] SA_MA[9] BE37 12 M_B_BS0 BD42 SB_BS[0] SB_MA[7] BE30 M_B_A8
SA_MA[10] 12 M_B_BS1 SB_BS[1] SB_MA[8]
BA30 AT22 BE28 M_B_A9
SA_MA[11] BC30 12 M_B_BS2 SB_BS[2] SB_MA[9] BD43 M_B_A10
BE39 SA_MA[12] AW41 SB_MA[10] AT28 M_B_A11
BD39 SA_CAS# SA_MA[13] AY28 SB_MA[11] AV28 M_B_A12
AT41 SA_RAS# SA_MA[14] AU26 AV43 SB_MA[12] BD46 M_B_A13
SA_WE# SA_MA[15] 12 M_B_CAS# SB_CAS# SB_MA[13]
BF40 AT26 M_B_A14
12 M_B_RAS# SB_RAS# SB_MA[14]
BD45 AU22 M_B_A15
12 M_B_WE# SB_WE# SB_MA[15]

AV8063801057404-QC_BGA1023

AV8063801057404-QC_BGA1023

+1.35V
3

Q1B

R14
5 1K_0402_1%
TP171

AO5800E_SC89-6
4

DDR3_DRAMRST# 12
TP169
6

Q1A

A R16 1 2 0_0402_5% A
10,14 DRAMRST_CNTRL_PCH
DRAMRST_CNTRL 2
R17 1 @ 2 0_0402_5%
34 DRAMRST_CNTRL_EC
2

1 AO5800E_SC89-6
C365 R101
1

10K_0402_5%
10U_0402_6.3V6M R18 1 2 0_0402_5%
2 CPUDRAMRST# 6
1

TP172
R19
4.99K_0402_1% Title
TP170 Security Classification LC Future Center Secret Data
Issued Date 2012/09/03 Deciphered Date 2012/09/03 CPU (3/7) DDRIII
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
VENUS2 0.1

Date: Saturday, January 26, 2013 Sheet 7 of 46


5 4 3 2 1
5 4 3 2 1

IVYBRIDGE PROCESSOR(RESERVED)
D D

U1E

B50 N59
C51 CFG[0] BCLK_ITP N58
B54 CFG[1] BCLK_ITP#
D53 CFG[2]
EN_eDP A51 CFG[3] N42 TP173
CFG[4] RSVD30

2
C53 L42 TP174
C55 CFG[5] RSVD31 L45 TP175
R199 H49 CFG[6] RSVD32 L47
1K_0402_5% A55 CFG[7] RSVD33
H51 CFG[8]
CFG[9]

1
K49 M13
K53 CFG[10] RSVD34 M14
F53 CFG[11] RSVD35 U14
G53 CFG[12] RSVD36 W14
L51 CFG[13] RSVD37 P13
F51 CFG[14] RSVD38
D52 CFG[15]
L53 CFG[16] AT49
CFG[17] RSVD39 K24
RSVD40
TESTPAD TP21 H_CPU_RSVD3 H43

RESERVED
TESTPAD TP22 H_CPU_RSVD4 K43 VCC_VAL_SENSE AH2
VSS_VAL_SENSE RSVD41 AG13
RSVD42 AM14
TESTPAD TP23 H_CPU_RSVD1 H45 RSVD43 AM15
TESTPAD TP24 H_CPU_RSVD2 K45 VAXG_VAL_SENSE RSVD44
VSSAXG_VAL_SENSE
C N50 C
F48 RSVD45
G48 VCC_DIE_SENSE
RSVD47
H48
K48 RSVD6
RSVD7 A4
DC_TEST_A4 C4
BA19 DC_TEST_C4 D3 DC_TEST_C4_D3
AV19 RSVD8 DC_TEST_D3 D1
AT21 RSVD9 DC_TEST_D1 A58
BB21 RSVD10 DC_TEST_A58 A59
BB19 RSVD11 DC_TEST_A59 C59 DC_TEST_A59_C59
AY21 RSVD12 DC_TEST_C59 A61
BA22 RSVD13 DC_TEST_A61 C61 DC_TEST_A61_C61
AY22 RSVD14 DC_TEST_C61 D61
AU19 RSVD15 DC_TEST_D61 BD61
AU21 RSVD16 DC_TEST_BD61 BE61
BD21 RSVD17 DC_TEST_BE61 BE59 DC_TEST_BE59_BE61
BD22 RSVD18 DC_TEST_BE59 BG61
BD25 RSVD19 DC_TEST_BG61 BG59 DC_TEST_BG59_BG61
BD26 RSVD20 DC_TEST_BG59 BG58
BG22 RSVD21 DC_TEST_BG58 BG4
BE22 RSVD22 DC_TEST_BG4 BG3
BG26 RSVD23 DC_TEST_BG3 BE3 DC_TEST_BE3_BG3
BE26 RSVD24 DC_TEST_BE3 BG1
BF23 RSVD25 DC_TEST_BG1 BE1 DC_TEST_BE1_BG1
BE24 RSVD26 DC_TEST_BE1 BD1
RSVD27 DC_TEST_BD1

AV8063801057404-QC_BGA1023

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/09/03 Deciphered Date 2012/09/03 CPU (4/7) RSVD,CFG


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
VENUS2 0.1

Date: Saturday, January 26, 2013 Sheet 8 of 46


5 4 3 2 1
5 4 3 2 1

IVYBRIDGE PROCESSOR(POWER)
POWER
U1F
+1.05VS PROCESSOR UNCORE
CPU_CORE
VCCIO[1]
AF46
RPOWER
AG48
VCCIO[3] AG50
A26 VCCIO[4] AG51
VCC[1] VCCIO[5] 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
A29 AJ17 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17
A31 VCC[2] VCCIO[6] AJ21 @ @ @ @
D 1 1 1 1 1 1 1 1 VCC[3] VCCIO[7] D
C18 C19 C20 C21 C22 C23 C24 C25 A34 AJ25 1U_0402_10V6K
1U_0402_10V6K
1U_0402_10V6K
1U_0402_10V6K
1U_0402_10V6K
1U_0402_10V6K
1U_0402_10V6K
1U_0402_10V6K
1U_0402_10V6K
1U_0402_10V6K
1U_0402_10V6K
1U_0402_10V6K
1U_0402_10V6K
1U_0402_10V6K
1U_0402_10V6K
1U_0402_10V6K
@ A35 VCC[4] VCCIO[8] AJ43 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
2.2U_0402_6.3V6M
33P_0402_50V8J
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M A38 VCC[5] VCCIO[9] AJ47
2 2 2 2 2 2 2 2 A39 VCC[6] VCCIO[10] AK50
A42 VCC[7] VCCIO[11] AK51
C26 VCC[8] VCCIO[12] AL14
C27 VCC[9] VCCIO[13] AL15
C32 VCC[10] VCCIO[14] AL16
C34 VCC[11] VCCIO[15] AL20
C37 VCC[12] VCCIO[16] AL22
1 1 1 1 1 1 1 1 VCC[13] VCCIO[17]
C26 C27 C28 C29 C30 C31 C32 C33 C39 AL26 1
@ C42 VCC[14] VCCIO[18] AL45
VCC[15] VCCIO[19] 1 1 1 1 1 1
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M D27 AL48 C34 C35 C36 C37 C38 C39 + C180
2 2 2 2 2 2 2 2 D32 VCC[16] VCCIO[20] AM16 @
D34 VCC[17] VCCIO[21] AM17

330U_D1_2VM_R6M
33P_0402_50V8J
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
D37 VCC[18] VCCIO[22] AM21 2 2 2 2 2 2 2
D39 VCC[19] VCCIO[23] AM43

PEG IO AND DDR IO


D42 VCC[20] VCCIO[24] AM47
E26 VCC[21] VCCIO[25] AN20
E28 VCC[22] VCCIO[26] AN42
1 1 1 1 1 1 1 1 VCC[23] VCCIO[27]
C40 C41 C42 C43 C44 C45 C46 C47 E32 AN45
@ @ @ @ E34 VCC[24] VCCIO[28] AN48
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M E37 VCC[25] VCCIO[29]
2 2 2 2 2 2 2 2 E38 VCC[26]
F25 VCC[27]

CORE SUPPLY
F26 VCC[28]
F28 VCC[29] +1.05VS
F32 VCC[30]
F34 VCC[31]
F37 VCC[32] AA14
1 1 1 1 1 1 1 1 VCC[33] VCCIO[30]
C48 C49 C50 C51 C52 C53 C54 C55 F38 AA15
@ @ @ F42 VCC[34] VCCIO[31] AB17
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M G42 VCC[35] VCCIO[32] AB20
2 2 2 2 2 2 2 2 VCC[36] VCCIO[33] 1 1 1 1 1 1 1 1 1 1
H25 AC13 C56 C57 C58 C59 C60 C61 C62 C63 C64 C65
H26 VCC[37] VCCIO[34] AD16 @ @ @ @
H28 VCC[38] VCCIO[35] AD18 1U_0402_10V6K
1U_0402_10V6K
1U_0402_10V6K
1U_0402_10V6K
1U_0402_10V6K
1U_0402_10V6K
33P_0402_50V8J
1U_0402_10V6K
1U_0402_10V6K
1U_0402_10V6K
H29 VCC[39] VCCIO[36] AD21 2 2 2 2 2 2 2 2 2 2
C H32 VCC[40] VCCIO[37] AE14 C
H34 VCC[41] VCCIO[38] AE15
H35 VCC[42] VCCIO[39] AF16
1 1 1 1 VCC[43] VCCIO[40]
C66 C67 C68 C69 H37 AF18
@ H38 VCC[44] VCCIO[41] AF20
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
33P_0402_50V8J
2.2U_0402_6.3V6M H40 VCC[45] VCCIO[42] AG15
2 2 2 2 J25 VCC[46] VCCIO[43] AG16
J26 VCC[47] VCCIO[44] AG17
J28 VCC[48] VCCIO[45] AG20
J29 VCC[49] VCCIO[46] AG21
VCC[50] VCCIO[47] 1 1 1 1 1 1
J32 AJ14 C70 C71 C72 C73 C74 C75
J34 VCC[51] VCCIO[48] AJ15
J35 VCC[52] VCCIO[49] 10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
J37 VCC[53] 2 2 2 2 2 2
J38 VCC[54]
J40 VCC[55] +1.05VS
J42 VCC[56]
1 1 1 1 1 1 1 1 VCC[57]
C76 C77 C78 C79 C80 C81 C82 C83 K26 W16
@ @ @ @ K27 VCC[58] VCCIO50 W17
22U_0603_4V6M
22U_0603_4V6M
22U_0603_4V6M
22U_0603_4V6M
22U_0603_4V6M
22U_0603_4V6M
22U_0603_4V6M
22U_0603_4V6M K29 VCC[59] VCCIO51
2 2 2 2 2 2 2 2 K32 VCC[60] +1.05VS
K34 VCC[61]
K35 VCC[62]
VCC[63]

1
K37
K39 VCC[64] R22
K42 VCC[66] BC22 VCCIO_SEL TP35 TESTPAD 75_0402_1%
L25 VCC[67] VCCIO_SEL
L28 VCC[68]
VCC[69]

2
1 1 1 1 1 1 1 1 L33 H_CPU_SVIDALRT# R24 1 2 43_0402_5% R25 1 2 0_0402_5%
VCC[70] VR_SVID_ALERT# 43
C84 C85 C86 C94 C96 C89 C97 C98 L36
@ @ @ L40 VCC[71] +1.05VS
22U_0603_4V6M
22U_0603_4V6M
22U_0603_4V6M
22U_0603_4V6M
22U_0603_4V6M
22U_0603_4V6M
22U_0603_4V6M
22U_0603_4V6M N26 VCC[72]
2 2 2 2 2 2 2 2 N30 VCC[73] AM25
QUIET
RAILS

N34 VCC[74] VCCPQE[1] AN22


N38 VCC[75] VCCPQE[2]
VCC[76] 1
C92

1U_0402_10V6K
B 2 B
H_CPU_SVIDCLK R27 1 2 0_0402_5%
VR_SVID_CLK 43
1 1 1 1 1 1 1 1 +1.05VS
C87 C88 C95 C90 C91 C93 C99 C100 A44 H_CPU_SVIDALRT#
@ @ @ @ @ VIDALERT# B43 H_CPU_SVIDCLK
VIDSCLK C44
SVID

22U_0603_4V6M
22U_0603_4V6M
22U_0603_4V6M
22U_0603_4V6M
22U_0603_4V6M
22U_0603_4V6M
22U_0603_4V6M
22U_0603_4V6M H_CPU_SVIDDAT
2 2 2 2 2 2 2 2 VIDSOUT R28
CPU_CORE 130_0402_1%

H_CPU_SVIDDAT R29 1 2 0_0402_5%


VR_SVID_DATA 43
R30
100_0402_1%

1 1
C101 C102 F43
@ @ VCC_SENSE G43 VCC_SENSE 43
SENSE LINES

22U_0603_4V6M
22U_0603_4V6M VSS_SENSE VSS_SENSE 43
2 2
R31
100_0402_1%
AN16
VCCIO_SENSE AN17 VCCP_SENSE 41
VSS_SENSE_VCCIO VSSP_SENSE 41

AV8063801057404-QC_BGA1023
1 1 1 1
+ CT2 + CT3 + CT4 + C181
330U_B2_2VM_R15M
330U_B2_2VM_R15M 330U_D1_2VM_R6M
330U_B2_2VM_R15M
2 2 2 2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/09/03 Deciphered Date 2012/09/03 CPU (5/7) PWR, BYPASS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
VENUS2 0.1

Date: Saturday, January 26, 2013 Sheet 9 of 46


5 4 3 2 1
5 4 3 2 1

DDR3_VREF SB_DDR_VREFDQ_DIMM 12

Q2 close to MCP AY43 PIN


R2211 2 0_0402_5%

IVYBRIDGE PROCESSOR(GRAPHICS POWER)

4
Q2
1 3 AO6802L_TSOP6 R35 1 2 0_0402_5% MAIND
24,35,36 MAIND
R2181 @ 2 0_0402_5%
D DRAMRST_CNTRL_PCH 14,7D

POWER

2
U1G +V_SM_VREF_CNT SB_DDR_VREFDQ

GFX_CORE +V_SM_VREF_CNT should have 10 mil trace


R32
AY43 +V_SM_VREF_CNT 100K_0402_5%
AA46 SM_VREF

VREF
AB47 VAXG[1]
AB50 VAXG[2] BE7 TP42 TESTPAD
1 1 1 1 1 1 1 1 1 1 1 1 VAXG[3] SA_DIMM_VREFDQ
C103 C104 C105 C106 C107 C108 C109 C110 C111 C112 C113 C114 AB51 BG7 SB_DDR_VREFDQ
AB52 VAXG[4] SB_DIMM_VREFDQ
1U_0402_10V6K
33P_0402_50V8J
1U_0402_10V6K
1U_0402_10V6K
1U_0402_10V6K
1U_0402_10V6K
1U_0402_10V6K
1U_0402_10V6K
1U_0402_10V6K
1U_0402_10V6K
1U_0402_10V6K
1U_0402_10V6K AB53 VAXG[5] +1.35V
2 2 2 2 2 2 2 2 2 2 2 2 AB55 VAXG[6]
VAXG[7] 1
AB56 @
AB58 VAXG[8] + CT10
AB59 VAXG[9] 330U_B2_2VM_R15M
AC61 VAXG[10]
AD47 VAXG[11] 2
AD48 VAXG[12] +1.35V_CPU
AD50 VAXG[13]
AD51 VAXG[14] AJ28
1 1 1 1 1 1 VAXG[15] VDDQ[1]

- 1.5V RAILS
C115 C116 C117 C118 C119 C120 AD52 AJ33
AD53 VAXG[16] VDDQ[2] AJ36
VAXG[17] VDDQ[3] 1 1 1 1 1 1 1 1 1 1
10U_0402_6.3V6M
10U_0402_6.3V6M
33P_0402_50V8J
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M AD55 AJ40 C121 C122 C123 C124 C125 C126 C127 C128 C129 C130
2 2 2 2 2 2 AD56 VAXG[18] VDDQ[4] AL30 @
AD58 VAXG[19] VDDQ[5] AL34 1U_0402_10V6K
1U_0402_10V6K
33P_0402_50V8J
1U_0402_10V6K
1U_0402_10V6K
1U_0402_10V6K
1U_0402_10V6K
1U_0402_10V6K
1U_0402_10V6K
1U_0402_10V6K
AD59 VAXG[20] VDDQ[6] AL38 2 2 2 2 2 2 2 2 2 2
AE46 VAXG[21] VDDQ[7] AL42 +1.35V_CPU +1.35V
N45 VAXG[22] VDDQ[8] AM33
P47 VAXG[23] VDDQ[9] AM36
P48 VAXG[24] VDDQ[10] AM40
P50 VAXG[25] VDDQ[11] AN30
P51 VAXG[26] VDDQ[12] AN34
P52 VAXG[27] VDDQ[13] AN38 C131 0.1u_0201_10V6K
1 1 1 1 1 1 1 1 1 1 VAXG[28] VDDQ[14]
C371 C370 C341 C369 C155 C154 C153 C368 C158 C141 P53 AR26 1 1 1 1 1 1 1 1
VAXG[29] VDDQ[15]

DDR3
C @ @ @ @ P55 AR28 C142 C143 C144 C145 C146 C147 C148 C150 C149 0.1u_0201_10V6K C
VAXG[30] VDDQ[16]

GRAPHICS
22U_0603_4V6M
22U_0603_4V6M
22U_0603_4V6M
22U_0603_4V6M
22U_0603_4V6M
22U_0603_4V6M
22U_0603_4V6M
22U_0603_4V6M
22U_0603_4V6M
22U_0603_4V6M P56 AR30
2 2 2 2 2 2 2 2 2 2 P61 VAXG[31] VDDQ[17] AR32 10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M C172 @ 0.1u_0201_10V6K
T48 VAXG[32] VDDQ[18] AR34 2 2 2 2 2 2 2 2
T58 VAXG[33] VDDQ[19] AR36 C173 @ 0.1u_0201_10V6K
T59 VAXG[34] VDDQ[20] AR40
T61 VAXG[35] VDDQ[21] AV41
U46 VAXG[36] VDDQ[22] AW26
V47 VAXG[37] VDDQ[23] BA40 stitching caps needed only for SODIMM designs.
V48 VAXG[38] VDDQ[24] BB28
1 VAXG[39] VDDQ[25]
1 1 1 1 1 1 1 1 V50 BG33
C372 C374 C363 C364 C366 C375 C376 C367 + CT6 V51 VAXG[40] VDDQ[26]
@ @ @ @ 330U_B2_2VM_R15M V52 VAXG[41] 2012/01/05 SIV2 delete CT7, the power
22U_0603_4V6M
22U_0603_4V6M
22U_0603_4V6M
22U_0603_4V6M
22U_0603_4V6M
22U_0603_4V6M
22U_0603_4V6M
22U_0603_4V6M V53 VAXG[42] side has enough 330uF cap for memeory
2 2 2 2 2 2 2 2 2 V55 VAXG[43]
controllor side.
V56 VAXG[44]
V58 VAXG[45]
V59 VAXG[46]
W50 VAXG[47]
W51 VAXG[48]
W52 VAXG[49]
W53 VAXG[50]
W55 VAXG[51]
W56 VAXG[52]
W61 VAXG[53]
GFX_CORE Y48 VAXG[54]
Y61 VAXG[55]
VAXG[56]
1

R33 +1.35V_CPU
10_0402_1%

AM28 R2081 2 0_0402_5%


QUIET RAILS
VCCDQ[1]
SENSE
LINES
2

F45 AN26 1
43 VCC_AXG_SENSE G45 VAXG_SENSE VCCDQ[2] C159
43 VSS_AXG_SENSE VSSAXG_SENSE
1

R34 1U_0402_10V6K
10_0402_1% 2
B B

+1.35V_CPU
L33
2

1.8V RAIL

1 2 BB3
BC1 VCCPLL[1]
1 VCCPLL[2]
1 1 BC4
BLM15PX121SN1D_2P + CT8 C160 C161 VCCPLL[3]
330U_B2_2VM_R15M
1U_0402_10V6K
1U_0402_10V6K
2 2 2 BC43 TP25 TESTPAD
VDDQ_SENSE BA43 TP26 TESTPAD
VSS_SENSE_VDDQ
SENSE LINES

L17
L21 VCCSA[1]
VCCSA N16 VCCSA[2]
N20 VCCSA[3]
N22 VCCSA[4]
VCCSA[5]
SA RAIL

P17
P20 VCCSA[6] U10
1 1 1 1 1 VCCSA[7] VCCSA_SENSE VCCSA_SENSE 42
C162 C163 C164 C165 C166 R16
@ R18 VCCSA[8] VCCSA_VID0 VCCSA_VID1 VCCSA
1U_0402_10V6K
1U_0402_10V6K
1U_0402_10V6K
1U_0402_10V6K
1U_0402_10V6K R21 VCCSA[9]
VCCSA_P 2 2 2 2 2 U15 VCCSA[10] 0 0 0.9V
VCCSA[11]
VCCSA VID

V16
V17 VCCSA[12] D48 0.85v for ulv&lv
V18 VCCSA[13] VCCSA_VID[0] D49 VCCSA_VID0 42
lines

V21 VCCSA[14] VCCSA_VID[1] VCCSA_VID1 42 0 1


W20 VCCSA[15] 0.8v others
VCCSA[16]
1 1 1 1 1 1
C167 C168 C169 C170 C171
+ CT9 1 0 0.725v
330U_B2_2VM_R15M 10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
2 2 2 2 2 AV8063801057404-QC_BGA1023
2 1 1 0.675v

A A

SIT Phase change back to VCCSA

Security Classification LC Future Center Secret Data Title

Issued Date 2012/09/03 Deciphered Date 2012/09/03 CPU (6/7) PWR


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
VENUS2 0.1

Date: Saturday, January 26, 2013 Sheet 10 of 46


5 4 3 2 1
5 4 3 2 1

IVYBRIDGE PROCESSOR(GND)
D D

U1H

U1I

A13 AM38
A17 VSS[1] VSS[91] AM4
A21 VSS[2] VSS[92] AM42 BG17 M4
A25 VSS[3] VSS[93] AM45 BG21 VSS[181] VSS[250] M58
A28 VSS[4] VSS[94] AM48 BG24 VSS[182] VSS[251] M6
A33 VSS[5] VSS[95] AM58 BG28 VSS[183] VSS[252] N1
A37 VSS[6] VSS[96] AN1 BG37 VSS[184] VSS[253] N17
A40 VSS[7] VSS[97] AN21 BG41 VSS[185] VSS[254] N21
A45 VSS[8] VSS[98] AN25 BG45 VSS[186] VSS[255] N25
A49 VSS[9] VSS[99] AN28 BG49 VSS[187] VSS[256] N28
A53 VSS[10] VSS[100] AN33 BG53 VSS[188] VSS[257] N33
A9 VSS[11] VSS[101] AN36 BG9 VSS[189] VSS[258] N36
AA1 VSS[12] VSS[102] AN40 C29 VSS[190] VSS[259] N40
AA13 VSS[13] VSS[103] AN43 C35 VSS[191] VSS[260] N43
AA50 VSS[14] VSS[104] AN47 C40 VSS[192] VSS[261] N47
AA51 VSS[15] VSS[105] AN50 D10 VSS[193] VSS[262] N48
AA52 VSS[16] VSS[106] AN54 D14 VSS[194] VSS[263] N51
AA53 VSS[17] VSS[107] AP10 D18 VSS[195] VSS[264] N52
AA55 VSS[18] VSS[108] AP51 D22 VSS[196] VSS[265] N56
AA56 VSS[19] VSS[109] AP55 D26 VSS[197] VSS[266] N61
AA8 VSS[20] VSS[110] AP7 D29 VSS[198] VSS[267] P14
AB16 VSS[21] VSS[111] AR13 D35 VSS[199] VSS[268] P16
AB18 VSS[22] VSS[112] AR17 D4 VSS[200] VSS[269] P18
AB21 VSS[23] VSS[113] AR21 D40 VSS[201] VSS[270] P21
AB48 VSS[24] VSS[114] AR41 D43 VSS[202] VSS[271] P58
AB61
AC10
VSS[25]
VSS[26]
VSS[27]
VSS[115]
VSS[116]
VSS[117]
AR48
AR61
D46
D50
VSS[203]
VSS[204]
VSS[205]
VSS VSS[272]
VSS[273]
VSS[274]
P59
P9
AC14 AR7 D54 R17
AC46 VSS[28] VSS[118] AT14 D58 VSS[206] VSS[275] R20
C AC6 VSS[29] VSS[119] AT19 D6 VSS[207] VSS[276] R4 C
AD17 VSS[30] VSS[120] AT36 E25 VSS[208] VSS[277] R46
AD20 VSS[31] VSS[121] AT4 E29 VSS[209] VSS[278] T1
AD4 VSS[32] VSS[122] AT45 E3 VSS[210] VSS[279] T47
AD61
AE13
VSS[33]
VSS[34]
VSS[35]
VSS VSS[123]
VSS[124]
VSS[125]
AT52
AT58
E35
E40
VSS[211]
VSS[212]
VSS[213]
VSS[280]
VSS[281]
VSS[282]
T50
T51
AE8 AU1 F13 T52
AF1 VSS[36] VSS[126] AU11 F15 VSS[214] VSS[283] T53
AF17 VSS[37] VSS[127] AU28 F19 VSS[215] VSS[284] T55
AF21 VSS[38] VSS[128] AU32 F29 VSS[216] VSS[285] T56
AF47 VSS[39] VSS[129] AU51 F35 VSS[217] VSS[286] U13
AF48 VSS[40] VSS[130] AU7 F40 VSS[218] VSS[287] U8
AF50 VSS[41] VSS[131] AV17 F55 VSS[219] VSS[288] V20
AF51 VSS[42] VSS[132] AV21 G51 VSS[220] VSS[289] V61
AF52 VSS[43] VSS[133] AV22 G6 VSS[221] VSS[290] W13
AF53 VSS[44] VSS[134] AV34 G61 VSS[222] VSS[291] W15
AF55 VSS[45] VSS[135] AV40 H10 VSS[223] VSS[292] W18
AF56 VSS[46] VSS[136] AV48 H14 VSS[224] VSS[293] W21
AF58 VSS[47] VSS[137] AV55 H17 VSS[225] VSS[294] W46
AF59 VSS[48] VSS[138] AW13 H21 VSS[226] VSS[295] W8
AG10 VSS[49] VSS[139] AW43 H4 VSS[227] VSS[296] Y4
AG14 VSS[50] VSS[140] AW61 H53 VSS[228] VSS[297] Y47
AG18 VSS[51] VSS[141] AW7 H58 VSS[229] VSS[298] Y58
AG47 VSS[52] VSS[142] AY14 J1 VSS[230] VSS[299] Y59
AG52 VSS[53] VSS[143] AY19 J49 VSS[231] VSS[300]
AG61 VSS[54] VSS[144] AY30 J55 VSS[232]
AG7 VSS[55] VSS[145] AY36 K11 VSS[233]
AH4 VSS[56] VSS[146] AY4 K21 VSS[234]
AH58 VSS[57] VSS[147] AY41 K51 VSS[235]
AJ13 VSS[58] VSS[148] AY45 K8 VSS[236] A5
AJ16 VSS[59] VSS[149] AY49 L16 VSS[237] VSS_NCTF_1 A57
AJ20 VSS[60] VSS[150] AY55 L20 VSS[238] VSS_NCTF_2 BC61
AJ22 VSS[61] VSS[151] AY58 L22 VSS[239] VSS_NCTF_3 BD3
AJ26 VSS[62] VSS[152] AY9 L26 VSS[240] VSS_NCTF_4 BD59
AJ30 VSS[63] VSS[153] BA1 L30 VSS[241] VSS_NCTF_5 BE4
VSS[64] VSS[154] VSS[242] VSS_NCTF_6

NCTF
AJ34 BA11 L34 BE58
AJ38 VSS[65] VSS[155] BA17 L38 VSS[243] VSS_NCTF_7 BG5
AJ42 VSS[66] VSS[156] BA21 L43 VSS[244] VSS_NCTF_8 BG57
B
AJ45 VSS[67] VSS[157] BA26 L48 VSS[245] VSS_NCTF_9 C3 B
AJ48 VSS[68] VSS[158] BA32 L61 VSS[246] VSS_NCTF_10 C58
AJ7 VSS[69] VSS[159] BA48 M11 VSS[247] VSS_NCTF_11 D59
AK1 VSS[70] VSS[160] BA51 M15 VSS[248] VSS_NCTF_12 E1
AK52 VSS[71] VSS[161] BB53 VSS[249] VSS_NCTF_13 E61
AL10 VSS[72] VSS[162] BC13 VSS_NCTF_14
AL13 VSS[73] VSS[163] BC5
AL17 VSS[74] VSS[164] BC57
AL21 VSS[75] VSS[165] BD12
AL25 VSS[76] VSS[166] BD16
AL28 VSS[77] VSS[167] BD19 AV8063801057404-QC_BGA1023
AL33 VSS[78] VSS[168] BD23
AL36 VSS[79] VSS[169] BD27
AL40 VSS[80] VSS[170] BD32
AL43 VSS[81] VSS[171] BD36
AL47 VSS[82] VSS[172] BD40
AL61 VSS[83] VSS[173] BD44
AM13 VSS[84] VSS[174] BD48
AM20 VSS[85] VSS[175] BD52
AM22 VSS[86] VSS[176] BD56
AM26 VSS[87] VSS[177] BD8
AM30 VSS[88] VSS[178] BE5
AM34 VSS[89] VSS[179] BG13
VSS[90] VSS[180]

AV8063801057404-QC_BGA1023

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/09/03 Deciphered Date 2012/09/03 CPU (7/7) VSS


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
VENUS2 0.1

Date: Saturday, January 26, 2013 Sheet 11 of 46


5 4 3 2 1
5 4 3 2 1

D D

JP1009A
7 M_B_A[15:0] M_B_DQ[63:0] 7

M_B_A0 98 5 M_B_DQ0
M_B_A1 97 A0 DQ 0 7 M_B_DQ1
M_B_A2 96 A1 DQ 1 15 M_B_DQ2 +1.35V
M_B_A3 95 A2 DQ 2 17 M_B_DQ3 +1.35V
M_B_A4 92 A3 DQ 3 4 M_B_DQ4 JP1009B
M_B_A5 91 A4 DQ 4 6 M_B_DQ5 75 44
M_B_A6 90 A5 DQ 5 16 M_B_DQ6 76 VDD1 VSS16 48 1 1 1 1 1 1 1 1 1 1 1
M_B_A7 86 A6 DQ 6 18 M_B_DQ7 81 VDD2 VSS17 49 C136 C134 C135 C317 C318 C351 C352 C353 C354 C355 C356
M_B_A8 89 A7 DQ 7 21 M_B_DQ8 82 VDD3 VSS18 54 @ @
M_B_A9 85 A8 DQ 8 23 M_B_DQ9 87 VDD4 VSS19 55 22U_0603_4V6M
22U_0603_4V6M
22U_0603_4V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
33P_0402_50V8J 2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
M_B_A10 107 A9 DQ 9 33 M_B_DQ10 88 VDD5 VSS20 60 2 2 2 2 2 2 2 2 2 2 2
M_B_A11 84 A10/A P DQ 10 35 M_B_DQ11 93 VDD6 VSS21 61
M_B_A12 83 A11 DQ 11 22 M_B_DQ12 94 VDD7 VSS22 65 @
M_B_A13 119 A12/B C# DQ 12 24 M_B_DQ13 99 VDD8 VSS23 66
M_B_A14 80 A13 DQ 13 34 M_B_DQ14 100 VDD9 VSS24 71
M_B_A15 78 A14 DQ 14 36 M_B_DQ15 105 VDD10 VSS25 72
A15 DQ 15 39 M_B_DQ16 106 VDD11 VSS26 127
109 DQ 16 41 M_B_DQ17 111 VDD12 VSS27 128
7 M_B_BS0 108 BA0 DQ 17 51 112 VDD13 VSS28 133
M_B_DQ18
7 M_B_BS1 79 BA1 DQ 18 53 117 VDD14 VSS29 134
M_B_DQ19
7 M_B_BS2 114 BA2 DQ 19 40 118 VDD15 VSS30 138
M_B_DQ20
7 M_CS#2 S0# DQ 20 VDD16 VSS31
121 42 M_B_DQ21 +3VS 123 139
7 M_CS#3 101 S1# DQ 21 50 124 VDD17 VSS32 144
M_B_DQ22
7 M_CLK_DDR 2 103 CK 0 DQ 22 52 VDD18 VSS33 145
M_B_DQ23
7 M_CLK_DDR #2 102 CK 0# DQ 23 57 199 VSS34 150
M_B_DQ24 +0.68VS DD R3_VTT
7 M_CLK_DDR 3 104 CK 1 DQ 24 59 VDDSPD VSS35 151
M_B_DQ25 1
7 M_CLK_DDR #3 CK 1# DQ 25 VSS36 L31
73 67 M_B_DQ26 C359 C333 77 155
7 M_CKE2 74 CK E0 DQ 26 69 122 NC1 VSS37 156 1 2
M_B_DQ27
7 M_CKE3 115 CK E1 DQ 27 56 125 NC2 VSS38 161
M_B_DQ28 2.2U_0402_6.3V6M
0.1u_0201_10V6K
7 M_B_CAS# 110 CA S# DQ 28 58 2 NCT EST VSS39 162
M_B_DQ29 +1.35V 1 1 1 1
C 7 M_B_RAS# 113 RA S# DQ 29 68 198 VSS40 167 BLM15PX121SN1D_2P C
M_B_DQ30 TESTPAD TP71 PM_EXTTS#1 C345 C346 C332 C331 C357 C358 C283 C278
7 M_B_WE# WE # DQ 30 EVENT # VSS41
SA0_DIM1 197 70 M_B_DQ31 R148 2 11K_0402_5% 30 168
201 SA0 DQ 31 129 7 DD R3_DRAMRST# RE SET # VSS42 172
SA1_DIM1 M_B_DQ32 1U_0402_10V6K1U_0402_10V6K
0.1u_0201_10V6K
0.1u_0201_10V6K 2.2U_0402_6.3V6M
2.2U_0402_6.3V6M 0.1u_0201_10V6K
0.1u_0201_10V6K
202 SA1 DQ 32 131 M_B_DQ33 DD R3_VREF VSS43 173 2 2 2 2
14,27 PCH_SMB_CLK 200 SCL DQ 33 141 VSS44
M_B_DQ34 R207 1 2 0_0402_5% VREF_DQ 1 178
14,27 PCH_SMB_DAT SDA DQ 34 143 VRE F_ DQ VSS45
M_B_DQ35 R21 R230 R209 1 2 0_0402_5% VREF_CA 126 179
116 DQ 35 130 M_B_DQ36 1K_0402_1% 1K_0402_1% VRE F_ CA VSS46 184
7 M_ODT2 120 ODT 0 DQ 36 132 VSS47 185
M_B_DQ37 @ @
7 M_ODT3 ODT 1 DQ 37 140 2 VSS48 189
M_B_DQ38
11 DQ 38 142 M_B_DQ39 VREF_DQ VREF_CA 3 VSS1 VSS49 190
28 DM 0 DQ 39 147 M_B_DQ40 8 VSS2 VSS50 195
46 DM 1 DQ 40 149 M_B_DQ41 2 2 1 1 9 VSS3 VSS51 196
63 DM 2 DQ 41 157 M_B_DQ42 @ R26 R231 @ C360 C361 13 VSS4 VSS52
136 DM 3 DQ 42 159 M_B_DQ43 C179 C386 14 VSS5 205 +0.68V DD R3_VREF
153 DM 4 DQ 43 146 M_B_DQ44 @ @ 0.1U_0402_25V6 2.2U_0402_6.3V6M19
2.2U_0402_6.3V6M VSS6 GND1 206
170 DM 5 DQ 44 148 M_B_DQ45 1 1K_0402_1% 1 2 2 20 VSS7 GND2
7 M_B_DQS[7:0] DM 6 DQ 45 VSS8
187 158 M_B_DQ46 0.1U_0402_25V6 1K_0402_1% 25
DM 7 DQ 46 160 M_B_DQ47 26 VSS9
12 DQ 47 163 31 VSS10 L32
M_B_DQS0 M_B_DQ48
M_B_DQS1 29 DQ S0 DQ 48 165 M_B_DQ49 32 VSS11 DD R3_VTT 1 2
M_B_DQS2 47 DQ S1 DQ 49 175 M_B_DQ50 37 VSS12 203
M_B_DQS3 64 DQ S2 DQ 50 177 M_B_DQ51 38 VSS13 VT T 1 204 C274 C210
M_B_DQS4 137 DQ S3 DQ 51 164 M_B_DQ52 43 VSS14 VT T 2 BLM15PX121SN1D_2P
C334
M_B_DQS5 154 DQ S4 DQ 52 166 M_B_DQ53 VSS15 0.1u_0201_10V6K
0.1u_0201_10V6K
M_B_DQS6 171 DQ S5 DQ 53 174 M_B_DQ54 R220 2 @ 10_0402_5% VREF_DQ 0.1u_0201_10V6K
188 DQ S6 DQ 54 176 10 SB_DDR_VREFDQ_DIMM
M_B_DQS7 M_B_DQ55
7 M_B_DQS#[7:0] DQ S7 DQ 55
M_B_DQS#0 10 181 M_B_DQ56 FOX_AS0A621-U4R6-7H
M_B_DQS#1 27 DQ S#0 DQ 56 183 M_B_DQ57
M_B_DQS#2 45 DQ S#1 DQ 57 191 M_B_DQ58
M_B_DQS#3 62 DQ S#2 DQ 58 193 M_B_DQ59
M_B_DQS#4 135 DQ S#3 DQ 59 180 M_B_DQ60
M_B_DQS#5 152 DQ S#4 DQ 60 182 M_B_DQ61
M_B_DQS#6 169 DQ S#5 DQ 61 192 M_B_DQ62
M_B_DQS#7 186 DQ S#6 DQ 62 194 M_B_DQ63
DQ S#7 DQ 63

FOX_AS0A621-U4R6-7H

B B

+3VS SA0_DIM1
2

R153 R152
10K_0402_5% 10K_0402_5%
1

SA1_DIM1

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/09/03 Deciphered Date 2012/09/03 SODIMM DDR3L


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document N umber Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
D
VENUS2 0.1

Date: Saturday, January 26, 2013 Sheet 12 of 46


5 4 3 2 1
5 4 3 2 1

TP112
TESTPAD
+3VLP
D3
2 1
D D
SDM10U45LP-7_DFN1006-2-2 VCCRTC
RTC_VCC D4
R40 2 11K_0402_5%
BAT_D 2 1 TP113 C201 1 218P_0402_50V8J
1 TESTPAD
C217
SDM10U45LP-7_DFN1006-2-2
1U_0402_10V6K
2

2
R74
Y1 10M_0402_5%
R75 1 220K_0402_1% U10A
32.768KHZ_12.5PF_CM8V-T1A
1

1
R76 1 220K_0402_1% C242 RTC_X1 A19 A37
RTCX1 FWH0/LAD0 LPC_AD0 34
1 A39
FWH1/LAD1 LPC_AD1 34
C243 1U_0402_10V6K C202 1 218P_0402_50V8J RTC_X2 C19 C39
2 RTCX2 FWH2/LAD2 LPC_AD2 34
R77 C37
FWH3/LAD3 LPC_AD3 34
1M_0402_5% 1U_0402_10V6K RTC_RST# F19
2 RTCRST# K40
FWH4/LFRAME# LPC_FRAME# 34
SRTC_RST# A23
SRTCRST# H40
LDRQ0#

LPC
RTC
SM_INTRUDER# K22 F37 TP45 TESTPAD
INTRUDER# LDRQ1#/GPIO23
R78 330K_0402_5% C21 Y4
VCCRTC INTVRMEN SERIRQ INT_SERIRQ 18,34

AN3
H35 SATA0RXN AN1 SATA_RXN0 25
HDA_BCLK_24M_R
HDA_BCLK SATA0RXP SATA_RXP0 25
AU3
SATA0TXN SATA_TXN0 25
HDA_SYNC H37 AU1

SATA3
HDA_SYNC SATA0TXP SATA_TXP0 25
HDA AUDIO 28 PCH_BEEP
PCH_BEEP N1
SPKR SATA1RXN
AN6
AN8
HDA_RST#_R F35 SATA1RXP AR3
HDA_RST# SATA1TXN AR1
SATA1TXP
+3V_VCCSUS_PCH HDA_SDIN0 D36 AD4
HDA_SDIN0 SATA2RXN AD2
HDA_SYNC R66 2 11K_0402_5% TESTPAD TP50 B36 SATA2RXP AL3
HDA_SDOUT_R R73 @2 11K_0402_5% HDA_SDIN1 SATA2TXN AL1
C +5VS TESTPAD TP51 C35 SATA2TXP C
HDA_SDIN2

IHDA
AD8
SATA3RXN
2

TESTPAD TP52 A35 AD6


R90 HDA_SDIN3 SATA3RXP AG3
10K_0402_5% SATA3TXN AG1
R2221 @ 2 0_0402_5%
HDA_SDOUT_R K37 SATA3TXP
34 ME_FLASH HDA_SDO

SATA
HDA_SDIN0 AE3
28 HDA_SDIN0 SATA4RXN
21

R79 33_0402_5% HDA_RST#_R AE1


28 HDA_RST# K35 SATA4RXP AH8
R80 33_0402_5% HDA_BCLK_24M_R TESTPAD TP43
28 HDA_BCLK_24M HDA_DOCK_EN#/GPIO33 SATA4TXN
R81 33_0402_5% HDA_SDOUT_R AH6
28 HDA_SDOUT SATA4TXP
R84 33_0402_5% 3 1 HDA_SYNC TESTPAD TP44 M35
28 HDA_SYNC_CODEC HDA_DOCK_RST#/GPIO13 AC3
SATA5RXN AC1
SATA5RXP
1

C206 C239 R45 AJ3


Q25 TESTPAD TP46 M17 SATA5TXN AJ1 +1.05VS
1M_0402_5%
20P_0201_25V8
20P_0201_25V8 DMG1012T-7_SOT523-3 JTAG_TCK SATA5TXP
2

TESTPAD TP47 M15 AB10 R86 37.4_0402_1% 2

JTAG
JTAG_TMS SATAICOMPO
@ TESTPAD TP48 U12 AB12 C251
JTAG_TDI SATAICOMPI
0.01U_0201_10V6K
TESTPAD TP49 M12 1
JTAG_TDO AF10 +1.05VS
SATA3RCOMPO
AF12 R88 49.9_0402_1% 2 +3VS
SATA3COMPI
C252
PCH_SCK AD12 AH4 R89 750_0402_1% 0.01U_0201_10V6K
SPI_CLK SATA3RBIAS 1

2
PCH_SCE0# AB8 R93 R94
SPI_CS0# TP184 10K_0402_5% 10K_0402_5%
TESTPAD TP31 PCH_SCE1# AB6
SPI_CS1#

SPI
W10
SPI ROM SATALED# SATA_LED# 18

1
BOARD_ID0
PCH_SI W8 M2 BOARD_ID0 TP183
SPI_MOSI SATA0GP/GPIO21 18 BOARD_ID1

2
PCH_SO Y2 R1 BBS_BIT0 TP30 TESTPAD
+3VAUX_SPI SPI_MISO SATA1GP/GPIO19 BBS_BIT0 R91 R92
10K_0402_5% 10K_0402_5%
B B
QS77-QPRF-C1_BGA1017 @ @

1
R141
10K_0402_5%
R95 4.7K_0402_5% @

1
C211
U11 R96
PCH_SCE0# 1 8 4.7K_0402_5% 0.1u_0201_10V6K
CS# VCC
PCH_SO R97 100_0402_5% PCH_SO_R 2 7
DO HOLD#
3 6 PCH_SCK_R R98 100_0402_5%
PCH_SCK
WP# CLK
PCH_SPI_GND 4 5 PCH_SI_R R99 PCH_SI
100_0402_5% BOARD_ID1 BOARD_ID0 Description
GND DI
TP186
W25Q64FVSSIG_SO8 0 0 SDV phase, SNB QS+PPT ES1

+3VALW +3VS +3VAUX_S5_S0 0 1 SIV phase, IVB ES2+PPT ES2


L46
1 2 @ 1 0 SIV2/SIT phase, IVB QS+PPT QS
L45
1 2
BLM15BD221SN1D_2P 1 1 TBD
BLM15BD221SN1D_2P

TP99
+5VS +3VAUX_SPI TESTPAD

PCH_SPI_GND
3
A Q41B A
2

6
R61 Q41A R58
1

10K_0402_5% SPI_FLASH_PWREN 5 @ 0_0402_5%


@ R46
SPI_FLASH_PWREN 2 0_0402_5% @
1

AO5804EL_SC89-6
@ @ 4
2

AO5804EL_SC89-6
1
Security Classification LC Future Center Secret Data Title
+3VAUX_S5_S0
Issued Date 2012/09/03 Deciphered Date 2012/09/03 PCH (1/9) SATA,HDA,SPI, LPC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
VENUS2 0.1

Date: Saturday, January 26, 2013 Sheet 13 of 46

5 4 3 2 1
5 4 3 2 1

+3V_VCCSUS_PCH

AO5804EL_SC89-6
Q34A
RP7
SMB_CLK 2 3
SMB_CLK 6 1 SMB_DATA 1 4
PCH_SMB_CLK 12,27
U10B 2.2K_0404_4P2R_5%
+3VS
RP3 RP10 4.7K_0404_4P2R_5%
BJ33 R127 2 2
1 10K_0402_5% 1 4 SML0_CLK 1 4
PERN1 +5VS
BL33 H12 SMB_ALERT# 2 3 SML0_DATA 2 3
BB30 PERP1 SMBALERT#/GPIO11
PETN1 5
AY30 F17 SMB_CLK 10K_0404_4P2R_5%
D PETP1 SMBCLK RP11
D
BJ35 F10 SMB_DATA EC_SMB_CLK1 1 4
BL35 PERN2 SMBDATA SMB_DATA 3 4 EC_SMB_DAT1 2 3
PERP2 PCH_SMB_DAT 12,27
BB33
AY33 PETN2 4.7K_0404_4P2R_5%
PETP2

SMBUS
H22
SML0ALERT#/GPIO60 DRAMRST_CNTRL_PCH 10,7 Q34B
BH36
BK36 PERN3 K12 SML0_CLK AO5804EL_SC89-6 RP17
BF33 PERP3 SML0CLK
BD33 PETN3 A9 SML0_DATA USB_OC#6 1 8
PETP3 SML0DATA 17 USB_OC#6 2 7
PCIECLKREQB#
BJ37 USB_OC#7 3 6
PERN4 17 USB_OC#7
BL37 PCIECLKREQ3# 4 5
BD35 PERP4 C9
PETN4 SML1ALERT#/PCHHOT#/GPIO74 SML1_ALERT# 17
BF35 10K_8P4R_5%
PETP4 D12 R193 1 @ 2 0_0402_5% RP18
SML1CLK/GPIO58 EC_SMB_CLK1 34

PCI-E*
BJ39 R194 1 @ 2 0_0402_5%
PERN5 EC_SMB_DAT1 34
BL39 C11 PCIECLKREQ0# 1 8
AY35 PERP5 SML1DATA/GPIO75 PCIECLKREQA# 2 7
BB35 PETN5 CLK_PCIE_LAN_REQ# 3 6
PETP5 PCIECLKREQ7# 4 5
BH40
BK40 PERN6 10K_8P4R_5%
PERP6

Controller
BD37 L3 RP19
BF37 PETN6 CL_CLK1
PETP6 1 8

Link
BJ41 J1 SMB_ALERT# 2 7
BL41 PERN7 CL_DATA1 PCIECLKREQ5# 3 6
AY37 PERP7 PCIECLKREQ4# 4 5
BB37 PETN7 M8
PETP7 CL_RST1# 10K_8P4R_5%
BJ43
BL43 PERN8
AY40 PERP8 CF change to 1k pull-up (HR 10K) R83 @2
DRAMRST_CNTRL_PCH 11K_0402_5%
BB40 PETN8
PETP8
R8 PCIECLKREQA#
C AD48 PEG_A_CLKRQ#/GPIO47 C
AD50 CLKOUT_PCIE0N
CLKOUT_PCIE0P AF44
M4 CLKOUT_PEG_A_N AF46
CLOCKS

PCIECLKREQ0# +3VS
PCIECLKRQ0#/GPIO73 CLKOUT_PEG_A_P
RP14 RP4
AE49 BB24 1 4 1 4
AE51 CLKOUT_PCIE1N CLKOUT_DMI_N AY24 2 3 CLK_EXP_N 6 18 DGPU_HPD_INTR# 2 3
CLKOUT_PCIE1P CLKOUT_DMI_P CLK_EXP_P 6 18 GPIO17
PCIECLKREQ1# U8 0_0404_4P2R_5%
RP15 10K_0404_4P2R_5%
18 PCIECLKREQ1# PCIECLKRQ1#/GPIO18 AN10 1 4
CLKOUT_DP_N CLK_DP_N 6
AN12 2 3
CLKOUT_DP_P CLK_DP_P 6
AD40
AD42 CLKOUT_PCIE2N 0_0404_4P2R_5%
CLKOUT_PCIE2P BD17 CLK_BUF_DMI_N
PCIECLKREQ2# T4 CLKIN_DMI_N BF17 CLK_BUF_DMI_P
18 PCIECLKREQ2# PCIECLKRQ2#/GPIO20 CLKIN_DMI_P
R103 1M_0402_5%
AA49 BB26 CLK_BUF_BCLK_N
AA51 CLKOUT_PCIE3N CLKIN_GND1_N AY26 CLK_BUF_BCLK_P
CLKOUT_PCIE3P CLKIN_GND1_P
Y2 25MHZ_10PF_8Y25000010
PCIECLKREQ3# B8
PCIECLKRQ3#/GPIO25 M24 CLK_BUF_DOT96_N
CLKIN_DOT_96N K24 CLK_BUF_DOT96_P XTAL25_IN 1 3 XTAL25_OUT
Y48 CLKIN_DOT_96P 1 3
Y50 CLKOUT_PCIE4N GND1 GND2
CLKOUT_PCIE4P AK8
CLKIN_SATA_N
CLK_BUF_SATA_N 1 C240 2 4 1 C241
PCIECLKREQ4# M19 AK6 CLK_BUF_SATA_P
PCIECLKRQ4#/GPIO26 CLKIN_SATA_P
15P_0402_50V8J 12P_0402_50V8-J
AB40 J49 CLK_BUF_REF14 2 2
AB42 CLKOUT_PCIE5N REFCLK14IN
CLKOUT_PCIE5P
PCIECLKREQ5# K8 E51
PCIECLKRQ5#/GPIO44 CLKIN_PCILOOPBACK CLK_PCI_FB 17
RP20

AF40 W49 XTAL25_IN CLK_BUF_DMI_P 1 8


AF42 CLKOUT_PEG_B_N XTAL25_IN W51 XTAL25_OUT CLK_BUF_DMI_N 2 7
B CLKOUT_PEG_B_P XTAL25_OUT CLK_BUF_BCLK_N 3 6 B

PCIECLKREQB# C4 +1.05VS CLK_BUF_BCLK_P 4 5


PEG_B_CLKRQ#/GPIO56
R104 1
AC49 290.9_0402_1% 10K_8P4R_5%
AB44 XCLK_RCOMP
AB46 CLKOUT_PCIE6N RP6
CLKOUT_PCIE6P CLK_BUF_DOT96_N 1 4
CLK_PCIE_LAN_REQ# J3 CLK_BUF_DOT96_P 2 3
PCIECLKRQ6#/GPIO45
W44 H50 TP82 TESTPAD 10K_0404_4P2R_5%
W46 CLKOUT_PCIE7N CLKOUTFLEX0/GPIO64
FLEX CLOCKS

CLKOUT_PCIE7P D48 TP53 TESTPAD RP5


PCIECLKREQ7# H4 CLKOUTFLEX1/GPIO65 CLK_BUF_SATA_P 1 4
PCIECLKRQ7#/GPIO46 G49 TP54 TESTPAD CLK_BUF_SATA_N 2 3
AR12 CLKOUTFLEX2/GPIO66
AR10 CLKOUT_ITPXDP_N J51 TP55 TESTPAD 10K_0404_4P2R_5%
CLKOUT_ITPXDP_P CLKOUTFLEX3/GPIO67

QS77-QPRF-C1_BGA1017
CLK_BUF_REF14 R105 2 1 10K_0402_5%

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/09/03 Deciphered Date 2012/09/03 -PCH (2/9) PCIE, SMBUS, CLK
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
VENUS2 0.1

Date: Saturday, January 26, 2013 Sheet 14 of 46


5 4 3 2 1
5 4 3 2 1

D D

U10C

BL21 BL13
5 DMI_RXN0 DMI0RXN FDI_RXN0 FDI_TXN0 5
BL23 BJ15
5 DMI_RXN1 BJ19 DMI1RXN FDI_RXN1 BD12 FDI_TXN1 5
5 DMI_RXN2 BL17 DMI2RXN FDI_RXN2 BJ11 FDI_TXN2 5
5 DMI_RXN3 DMI3RXN FDI_RXN3 FDI_TXN3 5
AY15
FDI_RXN4 FDI_TXN4 5
BJ21 AY12
5 DMI_RXP0 DMI0RXP FDI_RXN5 FDI_TXN5 5
BJ23 BJ9
5 DMI_RXP1 DMI1RXP FDI_RXN6 FDI_TXN6 5
BL19 BF10
5 DMI_RXP2 DMI2RXP FDI_RXN7 FDI_TXN7 5
BJ17
5 DMI_RXP3 DMI3RXP BJ13
FDI_RXP0 FDI_TXP0 5
BD22 BL15
5 DMI_TXN0 DMI0TXN FDI_RXP1 FDI_TXP1 5
BB22 BF12
5 DMI_TXN1 DMI1TXN FDI_RXP2 FDI_TXP2 5
BB19 BL11
5 DMI_TXN2 DMI2TXN FDI_RXP3 FDI_TXP3 5
BB17 BB15
5 DMI_TXN3 DMI3TXN FDI_RXP4 FDI_TXP4 5

DMI
FDI
BB12
BF22 FDI_RXP5 BL9 FDI_TXP5 5
5 DMI_TXP0 DMI0TXP FDI_RXP6 FDI_TXP6 5
AY22 BD10
5 DMI_TXP1 AY19 DMI1TXP FDI_RXP7 FDI_TXP7 5
5 DMI_TXP2 DMI2TXP
AY17
5 DMI_TXP3 DMI3TXP BB10
FDI_INT FDI_INT 5
R107 1 249.9_0402_1% BF19 BH12
+1.05VS DMI_ZCOMP FDI_FSYNC0 FDI_FSYNC0 5
BD19 BK8
DMI_IRCOMP FDI_FSYNC1 FDI_FSYNC1 5
R110 750_0402_1% BK20 BK12
DMI2RBIAS FDI_LSYNC0 FDI_LSYNC0 5
VCCRTC
BH8
FDI_LSYNC1 FDI_LSYNC1 5

C DSWODVREN R113 330K_0402_5% C


TP330 F22 DSWODVREN
R114 1 @ 2 0_0402_5% DSWVRMEN
34 PCH_SUSACK#

System Power Management


R115 1 @ 2 0_0402_5% PM_RSMRST#
SUS_PWR_ACK R116 1 @ 2 0_0402_5% F15 A21
SUSACK# DPWROK R117 1 @ 2 0_0402_5%
PCH_DPWROK 34
+3VS
+3VS R118 2 1 10K_0402_5%L1 D8 WAKE# RH294 1 @ 2 0_0402_5% PCIE_WAKE#
SYS_RESET# WAKE#
R120
TP88
TESTPAD R119 1 @ 2 0_0402_5%M10 T2 PM_CLKRUN# 1 2
34 SYS_PWROK SYS_PWROK CLKRUN#/GPIO32 PM_CLKRUN# 34
TP89
8.2K_0402_5%
TESTPAD R121 1 @ 2 0_0402_5%M22 G6
34 PM_PCH_PWROK PWROK SUS_STAT#/GPIO61 SUS_STAT# 34 +3V_VCCSUS_PCH

R122 1 @ 2 0_0402_5% G3 D3 TP56 TESTPAD


APWROK SUSCLK/GPIO62 R150
TP90 PM_BATLOW#_R 1 2
TESTPAD R123 1 @ 2 0_0402_5% B12 F6 TP57 TESTPAD
6 PM_DRAM_PWRGD DRAMPWROK SLP_S5#/GPIO63 disable PCIE PCIE_WAKE# R52 2 110K_0402_5%
TP87 8.2K_0402_5%
TESTPAD R124 1 @ 2 0_0402_5% B20 K10 R125 1 @ 2 0_0402_5%
34 PM_RSMRST# RSMRST# SLP_S4# SUSC# 34
TP92
TESTPAD R128 1 @ 2 0_0402_5%C13 D4 R129 1 @ 2 0_0402_5% +3V_VCCSUS_PCH
17,34 SUS_PWR_ACK SUSWARN#/SUSPWRDNACK/GPIO30 SLP_S3# SUSB# 34
TP91 +3VALW
TESTPAD K19 C7 TP58 TESTPAD
34 PCH_PWRBTN# PWRBTN# SLP_A# 2 110K_0402_5% +3VLP
R190 @

R202 1 @ 2 0_0402_5%
AC_PRESENT_R H19 A15 R133 1 @ 2 0_0402_5% AC_PRESENT_R R130 2 @ 110K_0402_5%
34 AC_PRESENT ACPRESENT/GPIO31 SLP_SUS# SLP_SUS# 34,36
D8
R1912 110K_0402_5%
1 2 PM_BATLOW#_R H10 BB8 R135 1 @ 2 0_0402_5%
34 PM_BATLOW# BATLOW#/GPIO72 PMSYNCH H_PM_SYNC 6
@
SDM10U45LP-7_DFN1006-2-2
R136 2 110K_0402_5% F12 A7 TP59 TESTPAD
B +3V_VCCSUS_PCH RI# SLP_LAN#/GPIO29 B
R315 @2 110K_0402_5%
+3VLP
PM_RSMRST# R1342 110K_0402_5%
QS77-QPRF-C1_BGA1017
PCH_DPWROK R2032 110K_0402_5%

PM_PCH_PWROK

1
RH216
10K_0402_5%

2
@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/09/03 Deciphered Date 2012/09/03 PCH (3/9) DMI, FDI, PM
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
VENUS2 0.1

Date: Saturday, January 26, 2013 Sheet 15 of 46


5 4 3 2 1
5 4 3 2 1

D D

U10D

M44 AU40
22 L_BKLT_EN L_BKLTEN SDVO_TVCLKINN
M42 AU42
22 LVDS_VDD_EN L_VDD_EN SDVO_TVCLKINP
L49 AR51
22 L_BKLT_CTRL L_BKLTCTL SDVO_STALLN AR49
L51 SDVO_STALLP
K46 L_DDC_CLK AT50
L_DDC_DATA SDVO_INTN AT48
TESTPAD TP72 R42 SDVO_INTP
TESTPAD TP73 M40 L_CTRL_CLK
L_CTRL_DATA
route LVD_IBG as close as possible R137 1 22.37K_0402_1% AH42 W42
TESTPAD TP74 AH40 LVD_IBG SDVO_CTRLCLK R44
to the PCH and away from any toggling LVD_VBG SDVO_CTRLDATA
signals (minimum spacing of 20 mils or 0.508 mm). AG51
AG49 LVD_VREFH AW51
LVD_VREFL DDPB_AUXN AW49
C
DDPB_AUXP AY42 C
AK44 DDPB_HPD

LVDS
AK46 LVDSA_CLK# AY48
LVDSA_CLK DDPB_0N AY50
AR46 DDPB_0P AY44
AN49 LVDSA_DATA#0 DDPB_1N AY46

Digital Display Interface


AN44 LVDSA_DATA#1 DDPB_1P BB44
AK40 LVDSA_DATA#2 DDPB_2N BB46
LVDSA_DATA#3 DDPB_2P BA49
AR44 DDPB_3N BA51
AN51 LVDSA_DATA0 DDPB_3P
AN46 LVDSA_DATA1
AK42 LVDSA_DATA2 T50
LVDSA_DATA3 DDPC_CTRLCLK U44
DDPC_CTRLDATA
AH46
AH44 LVDSB_CLK# AU51
LVDSB_CLK DDPC_AUXN AU49
AM50 DDPC_AUXP BE46
AL49 LVDSB_DATA#0 DDPC_HPD
AJ51 LVDSB_DATA#1 BC49
AH50 LVDSB_DATA#2 DDPC_0N BC51
LVDSB_DATA#3 DDPC_0P BD48
AM48 DDPC_1N BD50
AL51 LVDSB_DATA0 DDPC_1P BF46
AJ49 LVDSB_DATA1 DDPC_2N BF45
AH48 LVDSB_DATA2 DDPC_2P BE49
LVDSB_DATA3 DDPC_3N BE51
DDPC_3P

M46 M48
CRT_BLUE DDPD_CTRLCLK VGA_HDMI_CLK 24
R46 U42
CRT_GREEN DDPD_CTRLDATA VGA_HDMI_DATA 24
U46
CRT_RED
AU46
DDPD_AUXN
R49
N49 CRT_DDC_CLK CRT DDPD_AUXP
AU44
BK44 TMDS_D_HPD 24
CRT_DDC_DATA DDPD_HPD
B B
BG51
DDPD_0N VGA_HDMI_TX2- 24
M50 BG49
N51 CRT_HSYNC DDPD_0P BF42 VGA_HDMI_TX2+ 24
CRT_VSYNC DDPD_1N VGA_HDMI_TX1- 24
BD42
DDPD_1P BJ47 VGA_HDMI_TX1+ 24
R51 DDPD_2N BL47 VGA_HDMI_TX0- 24
R138 1K_0402_0.5%
DAC_IREF DDPD_2P VGA_HDMI_TX0+ 24
T48 BL45
CRT_IRTN DDPD_3N VGA_HDMI_CLK- 24
BJ45
DDPD_3P VGA_HDMI_CLK+ 24
QS77-QPRF-C1_BGA1017

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/09/03 Deciphered Date 2012/09/03 PCH (4/9) LVDS, CRT,DP,HDMI
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
VENUS2 0.1

Date: Saturday, January 26, 2013 Sheet 16 of 46


5 4 3 2 1
5 4 3 2 1

D D

U10E
BE3
RSVD1 BE1
BH24 RSVD2 AU8
BK24 TP1 RSVD3 BJ7
BH20 TP2 RSVD4
BK16 TP3 BA3
BH16 TP4 RSVD5 BH3
AN42 TP5 RSVD6
AN40 TP6 AU6
AR40 TP7 RSVD7 AW3
AR42 TP8 RSVD8 AW1
D20 TP9 RSVD9 AY6
M30 TP10 RSVD10 AY2
TESTPAD TP60 RSVD_PM_TEST_RST# E3 TP11 RSVD11 AY4
AM4 TP12 RSVD12 BC3
AT4 TP13 RSVD13 BC1
TP14 RSVD14

RSVD
AT2 BG1
AD10 TP15 RSVD15 BG3
B24 TP16 RSVD16 BE6
D24 TP17 RSVD17 BH4
AD44 TP18 RSVD18 BF7
AD46 TP19 RSVD19 BJ4

RSVD
TP20 RSVD20 BJ5
RSVD21 BK6
BJ48 RSVD22
BL7 TP21 AY8
W40 TP22 RSVD23
K30 TP23
BH49 TP24 BL5
BB42 TP41 RSVD24
C
TP42 BB6 C
RSVD25
BJ25 BD2
BJ27 USB3Rn1 RSVD26 BD4
BJ31 USB3Rn2 RSVD27
BJ29 USB3Rn3 BA1
30 USB3_RX4_N USB3Rn4 RSVD28

USB3.0
BL25 BF6
BL27 USB3Rp1 RSVD29
BL31 USB3Rp2
BL29 USB3Rp3 F24
30 USB3_RX4_P USB3Rp4 USBP0N
BF26 H24
BB28 USB3Tn1 USBP0P C25
BF28 USB3Tn2 USBP1N A25
BF30 USB3Tn3 USBP1P C27
30 USB3_TX4_N USB3Tn4 USBP2N
BD26 A27
AY28 USB3Tp1 USBP2P H28
USB3Tp2 USBP3N USB_PN3 30
BD28 F28 USB3.0
USB3Tp3 USBP3P USB_PP3 30
BD30 M26
30 USB3_TX4_P USB3Tp4 USBP4N K26
+3VS USBP4P D28
USBP5N B28 USB_PN5 23
MCU Sensor HUB
USBP5P USB_PP5 23
RP28 H26
USBP6N F26 USB_PN6 31
Wifi
USBP6P USB_PP6 31
1 8 PCI_PIRQA# PCI_PIRQA# D49 D32
2 7 PIRQA# USBP7N USB_PN7 27
PCI_PIRQB# PCI_PIRQB# C48 B32 Camera
PIRQB# USBP7P USB_PP7 27

PCI
3 6 PCI_PIRQC# PCI_PIRQC# C47 M28
PIRQC# USBP8N

USB2.0
4 5 PCI_PIRQD# PCI_PIRQD# C45 K28
PIRQD# USBP8P C29
8.2K_8P4R_5% PCI_REQ1# G46 USBP9N A29 USB_PN9 27
USB Port on FPC IO board
USB9 is Debug port
REQ1#/GPIO50 USBP9P USB_PP9 27
RP21 PCI_REQ2# K44 C31
REQ2#/GPIO52 USBP10N USB_PN10 27
PCI_REQ3# F46 A31 cardreader
REQ3#/GPIO54 USBP10P USB_PP10 27
1 8 PCI_REQ1# TP196 H33
USBP11N USB_PN11 22
2 7 PCI_REQ2# TP197 TESTPAD TP68 BBS_BIT1 F42 F33 Touch Panel
GNT1#/GPIO51 USBP11P USB_PP11 22
3 6 PCI_REQ3# TP198 TESTPAD TP69 PCI_GNT2# H42 H30
4 5 GNT2#/GPIO53 USBP12N USB_PN12 31
PCI_REQE# TESTPAD TP78 PCI_GNT3# D44 F30 BlueTooth
GNT3#/GPIO55 USBP12P M33 USB_PP12 31
10K_8P4R_5% USBP13N K33 +3V_VCCSUS_PCH
RP22 PCI_REQE# A47 USBP13P
B
PCI_REQF# C41 PIRQE#/GPIO2 B
1 8 PCI_REQF# TP200 PCI_REQG# F45 PIRQF#/GPIO3 C33 RP23
2 7 PCI_REQH# F40 PIRQG#/GPIO4 USBRBIAS#
3 6 PCI_REQG# TP201 PIRQH#/GPIO5 TP203 USB_OC#3 1 8
4 5 PCI_REQH# TP202 A33 TP204 USB_OC#5 2 7
TESTPAD TP61 PCI_PME# H2 USBRBIAS USB_OC#1 3 6
10K_8P4R_5% PME# TP206 USB_OC#0 4 5
F7 C17 USB_OC#0 R139
34,6 PLT_RST# PLTRST# OC0#/GPIO59 A17 USB_OC#1 10K_8P4R_5%
OC1#/GPIO40 USB_OC#1 30
A13 USB_OC#2 22.6_0402_1% RP24
TESTPAD TP62 G51 OC2#/GPIO41 D16 USB_OC#3
E49 CLKOUT_PCI0 OC3#/GPIO42 A11 1 8
CLKOUT_PCI1 OC4#/GPIO43 USB_OC#4 27 14 SML1_ALERT#
R140 22_0402_5% H48 B16 USB_OC#5 USB_OC#4 2 7
14 CLK_PCI_FB CLKOUT_PCI2 OC5#/GPIO9
J43 C23 TP207 USB_OC#2 3 6
CLKOUT_PCI3 OC6#/GPIO10 USB_OC#6 14
BBS_BIT1 R162 22_0402_5% G45 H15 USB_OC#7 4 5
34 CLK_PCI_LPC CLKOUT_PCI4 OC7#/GPIO14 USB_OC#7 14 15,34 SUS_PWR_ACK
10K_8P4R_5%
2

QS77-QPRF-C1_BGA1017
R167
10K_0402_5%
@
1

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/09/03 Deciphered Date 2012/09/03 PCH (5/9) PCI, USB
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
VENUS2 0.1

Date: Saturday, January 26, 2013 Sheet 17 of 46


5 4 3 2 1
5 4 3 2 1

D D

U10F

BMBUSY# W1 K42
BMBUSY#/GPIO0 TACH4/GPIO68 PUR_PCH_TRIG 23
B40 A43
34 KBSMI# TACH1/GPIO1 TACH5/GPIO69 RST_MSP430# 23
C43 D40 TP65 TESTPAD
14 DGPU_HPD_INTR# TACH2/GPIO6 TACH6/GPIO70
A45 A41 TP66 TESTPAD
34 SCI# TACH3/GPIO7 TACH7/GPIO71
TESTPAD TP76 H17
GPIO8
TESTPAD TP64 C5
LAN_PHY_PWR_CTRL/GPIO12 PLACE R142 NEAR TO U16
TP205 HOST_ALERT#1 K6 U3
GPIO15 A20GATE H_A20GATE 34
R1421 2 43_0402_5%
PECI_EC 34
AU12
PECI H_PECI 6

CPU/MISC
TP208 SSD1_DETECT# AA3
SATA4GP/GPIO16 U6 +3VS
RCIN# H_RCIN# 34
@

GPIO
B44 AU10 R143 2 10_0402_5%
14 GPIO17 TACH0/GPIO17 PROCPWRGD H_CPUPWRGD 6
BIOS_REC W3 BC9 R145 1 2390_0402_5% R146
SCLOCK/GPIO22 THRMTRIP# H_THRMTRIP# 6
HOST_ALERT#2 K15 R6 TP67 TESTPAD 2.2K_0402_5%
GPIO24/MEM_LED INIT3_3V#
1 2 D23 PCH_GP27_WAKE_R C15 BC7 NV_CLE R87 2 11K_0402_5%
34 PCH_GP27_WAKE# GPIO27 DF_TVS H_SNB_IVB# 6
PLL_ODVR_EN G1 +3VS
SDM10U45LP-7_DFN1006-2-2 GPIO28 AK10
SSD0_DETECT# R3 TS_VSS1
STP_PCI#/GPIO34 AH12 RP25
C W12 TS_VSS2 DMI & FDI Termination Voltage C
22 FPBACK GPIO35 AK12 H_RCIN# 1 8
SATA2GP W6 TS_VSS3 NV_CLE Set to Vss when Low 2 7
SATA2GP/GPIO36 14 PCIECLKREQ1#
AH10 TP212 GPIO39 3 6
SATA3GP M6 TS_VSS4 4 5
SATA3GP/GPIO37 U40 13 SATA_LED#
MFG_MODE N3 NC_1 10K_8P4R_5%
SLOAD/GPIO38 RP26
GPIO39 U10
SDATAOUT0/GPIO39 PCH_GPIO48 1 8
PCH_GPIO48 U1 BL48 2 7
SDATAOUT1/GPIO48 VSS_NCTF_15 14 PCIECLKREQ2#
SSD0_DETECT# 3 6
AA1 BL49 MFG_MODE 4 5
13 BOARD_ID1 SATA5GP/GPIO49 VSS_NCTF_16
GPIO57 K17 BL51 10K_8P4R_5%
GPIO57 VSS_NCTF_17 RP27
C3
VSS_NCTF_18 SSD1_DETECT# 1 8
A4 C49 2 7
VSS_NCTF_1 VSS_NCTF_19 13,34 INT_SERIRQ 3 6
BMBUSY#
A48 C51 BIOS_REC 4 5
VSS_NCTF_2 VSS_NCTF_20
A49 D1 10K_8P4R_5%
VSS_NCTF_3 VSS_NCTF_21

NCTF
A5 D51 SCI# R149 2 110K_0402_5%
VSS_NCTF_4 VSS_NCTF_22 KBSMI# R165 2 110K_0402_5%
A51 E1
VSS_NCTF_5 VSS_NCTF_23
BH1 +3V_VCCSUS_PCH
VSS_NCTF_6
BH51
VSS_NCTF_7
BJ1
VSS_NCTF_8 HOST_ALERT#1 R147 2 @ 11K_0402_5%
BJ3
VSS_NCTF_9 HOST_ALERT#2 R56 2 @ 110K_0402_5%
BJ49
VSS_NCTF_10 GPIO57 R60 2 110K_0402_5%
B B
BJ51
VSS_NCTF_11
BL1
VSS_NCTF_12
BL3
VSS_NCTF_13 +3VALW +3VLP
BL4
VSS_NCTF_14
PCH_GP27_WAKE_R R68 2 110K_0402_5%
QS77-QPRF-C1_BGA1017 R71 @2 110K_0402_5%

SATA3GP R72 2 110K_0402_5%

SATA2GP R1512 110K_0402_5%

PLL_ODVR_EN R102@2 11K_0402_5%


the On-Die PLL Voltage Regulator is disabled

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/09/03 Deciphered Date 2012/09/03 PCH (6/9) GPIO, CPU, MISC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
VENUS2 0.1

Date: Saturday, January 26, 2013 Sheet 18 of 46


5 4 3 2 1
5 4 3 2 1

+1.05VS U10G POWER +3VS


D L2 D
AB21
AB23 VCCCORE[1] U51 1 2
1 1 1 1 VCCCORE[2] VCCADAC
C256 C257 C244
C258 AC21 1 1
@ AC23 VCCCORE[3] C212 C262

CRT
AE21 VCCCORE[4] V50 BLM15BD221SN1D_2P
10U_0402_6.3V6M 1U_0402_10V6K
1U_0402_10V6K
1U_0402_10V6K C260
2 2 2 2 AE23 VCCCORE[5] VSSADAC 0.01U_0201_10V6K
0.1u_0201_10V6K
10U_0402_6.3V6M
AF21 VCCCORE[6] 2 @ 2
AF23 VCCCORE[7] +3VS
AG21 VCCCORE[8]

VCC CORE
AG23 VCCCORE[9] AF33 L9 1 @ 2
BLM15BD221SN1D_2P
AG25 VCCCORE[10] VCCALVDS[1] AG33
AG27 VCCCORE[11] VCCALVDS[2]
VCCCORE[12]

2
AJ21
AJ23 VCCCORE[13] AC33 R223
AJ25 VCCCORE[14] VSSALVDS[1] AE33
VCCCORE[15] VSSALVDS[2] 0_0402_5%
AJ27
AJ29 VCCCORE[16]
VCCCORE[17]

LVDS

1
AJ31 AF37
AK29 VCCCORE[18] VCCTX_LVDS[1]
AK31 VCCCORE[19] AG37
AK33 VCCCORE[20] VCCTX_LVDS[2]
AM33 VCCCORE[21] AG39
AM35 VCCCORE[22] VCCTX_LVDS[3]
+1.05VS VCCCORE[23] AJ37
VCCTX_LVDS[4]
AM21
VCCIO[28] +3VS
+1.05VS @
L3
L1 1 21.0UH_LQM21PN1R0MC0D_20% AP19
VCCAPLLEXP T39 1 2
1 VCC3_3[6]

HVCMOS
C265 1
@ AR15 C213 C264
10U_0402_6.3V6M VCCIO[15] 10UH_GLFR1608T100M-LR_20%
2 AT13 U37 0.1u_0201_10V6K
10U_0402_6.3V6M
VCCIO[16] VCC3_3[7] 2

+1.05VS AR23 TP220 +1.5VS


C
VCCIO[17] C
AR25
VCCIO[18] AU21
AR27 VCCVRM[3] AW21 VCCDMI[1] power trace needs to be
1 1 1 1 1 VCCIO[19] VCCVRM[4]
C266 C259 C267 C268 C269 +1.05VS 20 mils width with full VSS/VCC
@ AR29 reference plane
10U_0402_6.3V6M
1U_0402_10V6K
1U_0402_10V6K
1U_0402_10V6K
1U_0402_10V6K VCCIO[20] AM23
2 2 2 2 2 VCCDMI[1] 1
AU23 C270 same with cpu vccio voltage

DMI
VCCIO[21]

VCCIO
AU25 1U_0402_10V6K +1.05VS
VCCIO[22] 2 L59
AU27 AP39 1 2
VCCIO[23] VCCCLKDMI
1
AU29 C271
VCCIO[24] @ 10UH_GLFR1608T100M-LR_20%
1U_0402_10V6K
AU35 2
VCCIO[25] AJ13
AW34 VccDFTERM[1] +3VS
+3VS VCCIO[26]

NAND / SPI
AJ15
BK28 VccDFTERM[2]
C216 VCC3_3[3] C218
+1.5VS AK15
0.1u_0201_10V6K VccDFTERM[3] 0.1u_0201_10V6K
AU19
+1.05VS AW18 VCCVRM[5] AL13
VCCVRM[6] VccDFTERM[4]
L38
1 2 AP13
@ AP15 VCCAFDPLL[1] +3VS
VCCAFDPLL[2]
BLM15BD221SN1D_2P AK21 Y19

FDI
VCCIO[27] VCCSPI
1
+1.05VS C272
AU15 @
AW16 VCCDMI[2] 1U_0402_10V6K
same with cpu vccio voltage VCCDMI[3] 2
B B

QS77-QPRF-C1_BGA1017

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/09/03 Deciphered Date 2012/09/03 PCH (7/9) PWR


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
VENUS2 0.1

Date: Saturday, January 26, 2013 Sheet 19 of 46


5 4 3 2 1
5 4 3 2 1

+3VALW +3VALW +5VALW

1
D5 R157
SDM10U45LP-7_DFN1006-2-2
10_0402_5%

2
6

4
+12VSB R49 1 @ 2 100K_0402_5%
Q3
+1.05VS R36 1 2 0_0402_5%
SLP_SUSD_R# 1 3 AO6802L_TSOP6
SLP_SUSD_R#
36 SLP_SUSD#
D L52 D
1 2
1 +3V_VCCSUS_PCH

2
C310
BLM15BD221SN1D_2P@
U10J POWER +1.05VS
L53
+3VLP +3VALW 1U_0402_10V6K 1 2
@ 2 AC51 R23
@ VCCACLK VCCIO[29]
L40 1 2BLM15BD221SN1D_2P 1 1 1
R25 C275 BLM15BD221SN1D_2P
L41 1 2 BLM15BD221SN1D_2P R12 VCCIO[30] C196 C197
VCCDSW3_3 U23 1U_0402_10V6K 22U_0603_6.3V6-M
22U_0603_6.3V6-M
C219 VCCIO[31] 2 2 2
+3VS TESTPAD TP70 PCH_VCCDSW R10 U25
0.1u_0201_10V6K DCPSUSBYP VCCIO[32]
L4
R156 1
1_0402_5% 2 +V3.3S_VCC_CLKF33 +V3.3S_VCC_CLKF33 V37 +3V_VCCSUS_PCH
V39 VCC3_3[5] +5VREF_SUS_PCH
+1.05VS VCC3_3[6] R27
1
10UH_GLFR1608T100M-LR_20% 1 VCCSUS3_3[7] L54
C279 C277 @
L5 1 2 10UH_GLFR1608T100M-LR_20% AW31 R29 C220 1 2
10U_0402_6.3V6M
1U_0402_10V6K +1.05VS VCCAPLLDMI2 VCCSUS3_3[8]
2 2 1
C282 AP27 U27 0.1u_0201_10V6K 1
VCCIO[14] VCCSUS3_3[9]

USB
@ BLM15BD221SN1D_2P
10U_0402_6.3V6M U29 +3V_VCCSUS_PCH C198
2 V13 VCCSUS3_3[10] 22U_0603_6.3V6-M
DCPSUS[1] N27 2
1 VCCSUS3_3[6]
C276 AR33 +5VREF_SUS_PCH
@ AU33 DCPSUS[2] +1.05VS C221
1U_0402_10V6K DCPSUS[3] N18
2 VCCIO[34] 0.1u_0201_10V6K
AB27
VCCASW[1] M37
AB29 V5REF_SUS
VCCASW[2] +3VS +5VS C222

Clock and Miscellaneous


AB31 AU31
VCCASW[3] DCPSUS[4] +3V_VCCSUS_PCH 0.1u_0201_10V6K
1

1
AC27 AM27 C280
C
VCCASW[4] VCCSUS3_3[1] @ D6 R158 C
AC29 Confirm. 1U_0402_10V6K SDM10U45LP-7_DFN1006-2-2
VCCASW[5] 2 10_0402_5%
AC31
VCCASW[6]

2
N36
AE27 V5REF
VCCASW[7] 1
C285
+1.05VS AE29 R33 +3V_VCCSUS_PCH
VCCASW[8] VCCSUS3_3[2]

PCI/GPIO/LPC
1U_0402_10V6K
AE31 R35 2
VCCASW[9] VCCSUS3_3[3]
1 1 1 1 1 1
C132 C133 C286 C289
C290 U21 U33 C291
@ VCCASW[10] VCCSUS3_3[4]
22U_0603_4V6M 22U_0603_4V6M 1U_0402_10V6K
1U_0402_10V6K 1U_0402_10V6K V21 U35 1U_0402_10V6K
2 2 2 2 2 VCCASW[11] VCCSUS3_3[5] 2 +3VS
V23
VCCASW[12] AB19
V25 VCC3_3[1]
VCCASW[13] AC19 +3VS C223
Y21 VCC3_3[8]
VCCASW[14] R40 0.1u_0201_10V6K
Y23 VCC3_3[4] C224
VCCASW[15]
Y25 0.1u_0201_10V6K
VCCASW[16] +3VS
Y27
VCCASW[17] AF6
Y29 VCC3_3[2]
VCCASW[18] C225
Y31 AA13
VCCASW[19] VCCIO[5] +1.05VS 0.1u_0201_10V6K

R15 AG13
U15 DCPRTC[1] VCCIO[12]
DCPRTC[2] 1
+1.05VS C226 AG15 C292
Confirm 1.5V/1.05V/1.8V? +1.5VS VCCIO[13]
0.1u_0201_10V6K AC39 1U_0402_10V6K
VCCVRM[4] AF15 2 +1.05VS
B
L6 1 210UH_GLFR1608T100M-LR_20% +1.05V_VCCA_DPLLA VCCIO[6] @
B

SATA
1 +1.05VS AM2 L7 1 210UH_GLFR1608T100M-LR_20%
CT11 +1.05V_VCCA_DPLLA BF40 VCCAPLLSATA
1 VCCADPLLA +1.5VS
1
+ C297 C299
1 +1.05V_VCCA_DPLLB BD40 AE19 @
220U_B2_6.3VM_R35M
1U_0402_10V6K C298 VCCADPLLB VCCVRM[1] AF17 10U_0402_6.3V6M
2 2 +1.05VS VCCVRM[2] +1.05VS 2
1U_0402_10V6K AJ17
2 AC37 VCCIO[7] AB15
1 VCCDIFFCLKN[1] VCCIO[2]
L8 1 210UH_GLFR1608T100M-LR_20% +1.05V_VCCA_DPLLB C300 AE37 1
AE39 VCCDIFFCLKN[2] AC13 C301
1 VCCDIFFCLKN[3] VCCIO[3]
CT12 1 +1.05VS 1U_0402_10V6K
+ C302 2 AC15 1U_0402_10V6K
AC35 VCCIO[4] 2
1U_0402_10V6K
220U_B2_6.3VM_R35M VCCSSC
2 2 1
C303 +1.05VS
U17
1U_0402_10V6K DCPSST U19
2 C227 VCCASW[22]
FUSE

+1.05VS 0.1u_0201_10V6K R19


VCCASW[23] +3VALW +3V_VCCSUS_PCH
CPU

AM17
V_PROC_IO power trace needs to be V_PROC_IO V19
1 VCCASW[21] L43
20 mils width with full VSS/VCC C228C229
reference plane C306 @ 1 2 @
4.7U_0402_6.3V6M L42
0.1u_0201_10V6K
0.1u_0201_10V6K
2 N16 V31 1 2
RTC

VCCRTC VCCSUSHDA
HDA

BLM15BD221SN1D_2P
C230
BLM15BD221SN1D_2P
VCCRTC QS77-QPRF-C1_BGA1017
0.1u_0201_10V6K

1
C304 C232 C231
@
1U_0402_10V6K
0.1u_0201_10V6K
0.1u_0201_10V6K
A 2 A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/09/03 Deciphered Date 2012/09/03 PCH (8/9) PWR


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
VENUS2 0.1

Date: Saturday, January 26, 2013 Sheet 20 of 46


5 4 3 2 1
5 4 3 2 1

U10H U10I
G7
D VSS[0] BA25 J18 D
AA11 AL41 BA27 VSS[159] VSS[264] J21
AA39 VSS[1] VSS[80] AL43 BA29 VSS[160] VSS[265] J23
AA41 VSS[2] VSS[81] AL45 BA31 VSS[161] VSS[266] J25
AA43 VSS[3] VSS[82] AL7 BA34 VSS[162] VSS[267] J27
AA45 VSS[4] VSS[83] AL9 BA36 VSS[163] VSS[268] J29
AA7 VSS[5] VSS[84] AM15 BA39 VSS[164] VSS[269] J31
AA9 VSS[6] VSS[85] AM19 BA41 VSS[165] VSS[270] J34
AB17 VSS[7] VSS[86] AM25 BA43 VSS[166] VSS[271] J36
AB2 VSS[8] VSS[87] AM29 BA45 VSS[167] VSS[272] L25
AB25 VSS[9] VSS[88] AM31 BA7 VSS[168] VSS[273] J41
AB33 VSS[10] VSS[89] AM37 BA9 VSS[169] VSS[274] J45
AB35 VSS[11] VSS[90] AP11 BB4 VSS[170] VSS[275] J7
AB37 VSS[12] VSS[91] AP17 F2 VSS[171] VSS[276] J9
AB4 VSS[13] VSS[92] AP2 BB48 VSS[172] VSS[277] K2
AB48 VSS[14] VSS[93] AP21 BB50 VSS[173] VSS[278] K4
AB50 VSS[15] VSS[94] AP23 BC11 VSS[174] VSS[279] K48
AC11 VSS[16] VSS[95] AP25 BC13 VSS[175] VSS[280] K50
AC17 VSS[17] VSS[96] AP29 BC16 VSS[176] VSS[281] L11
AC25 VSS[18] VSS[97] AP31 BC18 VSS[177] VSS[282] L13
AC41 VSS[19] VSS[98] AP33 BC21 VSS[178] VSS[283] L16
AC43 VSS[20] VSS[99] AP35 BC23 VSS[179] VSS[284] L18
AC45 VSS[21] VSS[100] AP37 BC25 VSS[180] VSS[285] L29
AC7 VSS[22] VSS[101] AP4 BC27 VSS[181] VSS[286] L21
AE13 VSS[23] VSS[102] AP41 BC29 VSS[182] VSS[287] L23
AE15 VSS[24] VSS[103] AP43 BC31 VSS[183] VSS[288] L27
AE17 VSS[25] VSS[104] AP45 BC34 VSS[184] VSS[289] L9
AE25 VSS[26] VSS[105] AP48 BC36 VSS[185] VSS[290] L31
AE35 VSS[27] VSS[106] AP50 BC39 VSS[186] VSS[291] L34
AE41 VSS[28] VSS[107] AP7 BC41 VSS[187] VSS[292] L36
AE43 VSS[29] VSS[108] AP9 BC43 VSS[188] VSS[293] L39
AE45 VSS[30] VSS[109] AR19 BC45 VSS[189] VSS[294] L41
AE7 VSS[31] VSS[110] AR21 BE11 VSS[190] VSS[295] L43
AE9 VSS[32] VSS[111] AR31 BE13 VSS[191] VSS[296] L45
AF19 VSS[33] VSS[112] AR35 BE16 VSS[192] VSS[297] L7
AF2 VSS[34] VSS[113] AR37 BE21 VSS[193] VSS[298] N13
AF25 VSS[35] VSS[114] AT11 BE23 VSS[194] VSS[299] N21
C AF27 VSS[36] VSS[115] AT39 BE27 VSS[195] VSS[300] R37 C
AF29 VSS[37] VSS[116] AT41 BE29 VSS[196] VSS[301] N23
AF31 VSS[38] VSS[117] AT43 BE31 VSS[197] VSS[302] N29
AF4 VSS[39] VSS[118] AT45 BE34 VSS[198] VSS[303] N31
AF48 VSS[40] VSS[119] AT7 BE36 VSS[199] VSS[304] N34
AF50 VSS[41] VSS[120] AT9 BE39 VSS[200] VSS[305] N39
AG11 VSS[42] VSS[121] AU17 BE41 VSS[201] VSS[306] N41
AG17 VSS[43] VSS[122] AU37 BE43 VSS[202] VSS[307] N43
AC9 VSS[44] VSS[123] AV2 BE45 VSS[203] VSS[308] N45
AE11 VSS[45] VSS[124] AV4 BE7 VSS[204] VSS[309] N7
AG19 VSS[46] VSS[125] AV48 BE9 VSS[205] VSS[310] N9
AG29 VSS[47] VSS[126] AV50 BE18 VSS[206] VSS[311] P2
AG31 VSS[48] VSS[127] AW11 BF2 VSS[207] VSS[312] P4
AG35 VSS[49] VSS[128] AW13 BF4 VSS[208] VSS[313] P48
AG41 VSS[50] VSS[129] AW23 BF48 VSS[209] VSS[314] P50
AG43 VSS[51] VSS[130] AW25 BF50 VSS[210] VSS[315] R17
AG45 VSS[52] VSS[131] AW27 BH10 VSS[211] VSS[316] R21
AG7 VSS[53] VSS[132] AW29 BH14 VSS[212] VSS[317] R31
AG9 VSS[54] VSS[133] AW36 BH26 VSS[213] VSS[318] T11
AH2 VSS[55] VSS[134] AW39 BH32 VSS[214] VSS[319] T13
AJ11 VSS[56] VSS[135] AW43 BH34 VSS[215] VSS[320] T41
AJ19 VSS[57] VSS[136] AW45 BH38 VSS[216] VSS[321] T43
AJ33 VSS[58] VSS[137] AW7 BH42 VSS[217] VSS[322] T45
AJ35 VSS[59] VSS[138] AW9 BH44 VSS[218] VSS[323] T7
AJ39 VSS[60] VSS[139] AY10 BH46 VSS[219] VSS[324] T9
AJ41 VSS[61] VSS[140] B10 G21 VSS[220] VSS[325] BH28
AJ43 VSS[62] VSS[141] B14 BH48 VSS[221] VSS[328] N25
AJ45 VSS[63] VSS[142] B18 BH6 VSS[222] VSS[329] AF8
AJ7 VSS[64] VSS[143] B22 BK10 VSS[223] VSS[330] AF35
AJ9 VSS[65] VSS[144] B26 BK14 VSS[224] VSS[331] BB2
AK17 VSS[66] VSS[145] B30 BK18 VSS[225] VSS[333] BE25
AK19 VSS[67] VSS[146] B34 BK22 VSS[226] VSS[334] BH30
AK2 VSS[68] VSS[147] B38 BK26 VSS[227] VSS[335] F4
AK23 VSS[69] VSS[148] B42 D14 VSS[228] VSS[337] G25
AK25 VSS[70] VSS[149] B46 BK32 VSS[229] VSS[338] N11
AK27 VSS[71] VSS[150] B6 BK34 VSS[230] VSS[340] BH18
AK35 VSS[72] VSS[151] BA11 BK38 VSS[231] VSS[342] BH22
AK37 VSS[73] VSS[152] BA13 BK42 VSS[232] VSS[343] BK30
B
AK4 VSS[74] VSS[153] BA16 BK46 VSS[233] VSS[344] AR17 B
AK48 VSS[75] VSS[154] AW41 D10 VSS[234] VSS[345] J39
AK50 VSS[76] VSS[155] BA18 D18 VSS[235] VSS[346] U31
AL11 VSS[77] VSS[156] BA21 D22 VSS[236] VSS[353] U49
AL39 VSS[78] VSS[157] BA23 D26 VSS[237] VSS[354] V11
VSS[79] VSS[158] D30 VSS[238] VSS[355] V15
QS77-QPRF-C1_BGA1017 D34 VSS[239] VSS[356] V17
D38 VSS[240] VSS[357] V2
D42 VSS[241] VSS[358] V27
D46 VSS[242] VSS[359] V29
F48 VSS[243] VSS[360] V33
F50 VSS[244] VSS[361] V35
G11 VSS[245] VSS[362] V4
G13 VSS[246] VSS[363] V41
G16 VSS[247] VSS[364] V43
G18 VSS[248] VSS[365] V45
G23 VSS[249] VSS[366] V48
G27 VSS[250] VSS[367] V7
G29 VSS[251] VSS[368] V9
G31 VSS[252] VSS[369] Y15
G34 VSS[253] VSS[370] Y17
G36 VSS[254] VSS[371] Y33
G39 VSS[255] VSS[372] Y35
G41 VSS[256] VSS[373] Y37
D6 VSS[257] VSS[374] AR8
G43 VSS[258] VSS[347] AR6
G9 VSS[259] VSS[348] BF15
J11 VSS[260] VSS[349] BD15
J13 VSS[261] VSS[350] BF24
J16 VSS[262] VSS[351] BD24
VSS[263] VSS[352]

QS77-QPRF-C1_BGA1017

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/09/03 Deciphered Date 2012/09/03 PCH (9/9) VSS


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
VENUS2 0.1

Date: Saturday, January 26, 2013 Sheet 21 of 46


5 4 3 2 1
5 4 3 2 1

+1.05VS
+3VLP
HPD INVERSION FOR EDP

2
R65
100K_0402_5% R15
1K_0402_5%

1
EDP_HPD
EDP_HPD 5
D2
R39 2 11K_0402_5% 1 2 BLON TP230
34 MXLID#
3
2 SDM10U45LP-7_DFN1006-2-2 2 Q4B
6 TP229
C207 Q4A C208
D 0.1U_0402_25V6 0.1U_0402_25V6 EDP_HPD_OUT 5 D
1 1
2
18 FPBACK

100K_0402_5%
AO5804EL_SC89-6
4

1
31 LID_30#

RC76
AO5804EL_SC89-6
TP221 1

2
R37 2 110K_0402_5% BLON
16 L_BKLT_EN

2
R173
C293
100K_0402_5% 0.1U_0402_25V6
1

+3VS

2
@
TP231 R43
1K_0402_5%

1
@ R345 1 2 0_0402_5% LCD_PWM_BKLT
34 EC_PWM_BKLT
@
R54 2 10_0402_5%
16 L_BKLT_CTRL

TP105 TP95
+3VS
TESTPAD TP226 TESTPAD
+3V_eDPVCC
C U9 C
TP224
L29
1 8
@ 2 GND OC1 7 1 2
R69 2 10_0402_5% 3 IN OUT1 6
16 LVDS_VDD_EN EN1 OUT2 1 2
4 5 BLM15PX121SN1D_2P C235
EN2 OC2 JP1013
1

C209
R70 9 2.2U_0402_6.3V6M 0.1U_0402_25V6 1 2
100K_0402_5% PAD 2 1 C156 1 2 0.1U_0402_25V6 DTX1N_OUT 3 1 2 4 DTX1P_OUT 0.1U_0402_25V6 2 1 C194
TPS2066ADRBR_SON8_3X3 5 EDP_TX1_DN 5 3 4 6 0.1U_0402_25V6 2 1 C157 EDP_TX1_DP 5
DTX0N_OUT
5 6 EDP_TX0_DN 5
TP227 C195 1 2 0.1U_0402_25V6 DTX0P_OUT 7 8
5 EDP_TX0_DP 7 8
2

C192 1 2 0.1U_0402_25V6 DAUXP_OUT 9 10 DAUXN_OUT 0.1U_0402_25V6 2 1 C199


5 EDP_AUX_DP 11 9 10 12 EDP_AUX_DN 5
11 12 +3V_eDPVCC
Max Current: 300mA +3V_eDPVCC 13 14
15 13 14 16
B+ V_BL_LED EDP_HPD_OUT 17 15 16 18
19 17 18 20
21 19 20 22 BLON
L30 1 2BLM15PX121SN1D_2P LCD_PWM_BKLT 23 21 22 24
25 23 24 26
25 26 V_BL_LED
L37 1 2BLM15PX121SN1D_2P Max Current: 2A V_BL_LED 27 28
27 28
1

C203 C204 29 30
C200 31 29 30 32
0.1U_0402_25V6 0.1U_0402_25V6 +3V_TOUCHPANEL 33 31 32 34
10U_0805_25V6K
33 34
2

35 36
17 USB_PN11 35 36 USB_PP11 17
37 38
39 37 38 40
39 40
TP228 41 42
43 GND1 GND2 44
GND3 GND4

I-PEX_20474-040E-12

B B

+3VS

2
100K_0402_5%
R251 100K_0402_5%
@ R253

2
@

1
DAUXN_OUT

DAUXP_OUT

2
@
100K_0402_5% 100K_0402_5%
R252 R233
@

1
+3VS +3V_TOUCHPANEL

L50 1 2 BLM15BD221SN1D_2P
2
2
A 0.1U_0402_25V6
C188 A
C236
1 0.1U_0402_25V6
1

Security Classification LC Future Center Secret Data Title

Issued Date 2012/09/03 Deciphered Date 2012/09/03 EDP/ Camera


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
VENUS2 0.1

Date: Saturday, January 26, 2013 Sheet 22 of 46


5 4 3 2 1
5 4 3 2 1

+3VS +3V_MCU +3V_MCU_A


L47
C1 E8
D2 P6.4/CB4/A4 P4.0/PM_UCB1STE/PM_UCA1CLK E7 1 2 R2111 2 0_0402_5%
D1 P6.5/CB5/A5 P4.1/PM_UCB1SIMO/PM_UCB1SDA D9
D3 P6.6/CB6/A6 P4.2/PM_UCB1SOMI/PM_UCB1SCL D8
P6.7/CB7/A7 P4.3/PM_UCB1CLK/PM_UCA1STE BLM15BD221SN1D_2P 1 2 C237 2 C337 2 C245 1 2 C284
D7 C544 C547
E1 P4.4/PM_UCA1TXD/PM_UCA1SIMO C9
E2 P5.0/A8/VREF+/VeREF+ P4.5/PM_UCA1RXD/PM_UCA1SOMI C8 10U_0402_6.3V6M 10U_0402_6.3V6M
P5.1/A9/VREF-/VeREF- P4.6/PM_NONE C7 +3V_MCU 2 1 0.1U_0402_10V6K
1 0.1U_0402_10V6K
1 0.1U_0402_10V6K 2 1 0.1U_0402_10V6K
F2 P4.7/PM_NONE R2131 2 0_0402_5%
+3V_MCU_A AVCC1
G2 F9
D AVSS1 DVSS2 E9 D
F1 DVCC2 B8
G1 P5.4/XIN VSSU1 B9 AGND_MCU
P5.5/XOUT VSSU2
+3V_MCU
H1 A9
DVCC1 PU.0/DP USB_PP5 17
J1 A8
DVSS1 PU.1/DM USB_PN5 17
J2
VCORE B7 PUR_MCU TP233
H2 PUR A7 VBUS_MCU
H3 P1.0/TA0CLK/ACLK VBUS A6 VUSB_MCU TP235
1 P1.1/TA0.0 VUSB
J3
27 MCU_ALS_INT# P1.2/TA0.1
+3V_MCU C395 G4 B6 V18_MCU
0.47U_0402_25V6K H4 P1.3/TA0.2 V18
2 P1.4/TA0.3
2

PANEL_ACC_INT1 J4 A5
R100 G5 P1.5/TA0.4 AVSS2
10K_0402_5% H5 P1.6/TA1CLK/CBOUT B5 XT2IN_MCU
P1.7/TA1.0 P5.2/XT2IN B4 XT2OUT_MCU
GSENSOR
J5 P5.3/XT2OUT SLAVE I2C ADDRESS:0001111
27 INT_MPU6050 P2.0/TA1.1
1

27 INT_COMPASS G6 A4 TEST_MSP430 +3VS


+3V_MCU J6 P2.1/TA1.2 TEST/SBWTCK
H6 P2.2/TA2CLK/SMCLK C5 TDO_MSP430
J7 P2.3/TA2.0 PJ.0/TDO C4 TDI_MSP430
R38 R41 J8 P2.4/TA2.1 PJ.1/TDI/TCLK A3 TMS_MSP430 +3V_MCU U24
J9 P2.5/TA2.2 PJ.2/TMS B3 TCK_MSP430
2.2K_0402_5% 2.2K_0402_5% P2.6/RTCCLK/DMAE0 PJ.3/TCK 1 10 MCU_I2C_SDA
H7 A2 47K_0402_5% R366 2 VDD_IO SDA 9 MCU_I2C_SCL
MCU_I2C_SDA H8 P2.7/UCB0STE/UCA0CLK RST#/NMI/SBWTDIO C184 C330 3 DNC1 SCL 8
P3.0/UCB0SIMO/UCB0SDA 1 DNC2 DNC4
MCU_I2C_SCL H9 A1 C288 4 7 PANEL_ACC_INT1
G8 P3.1/UCB0SOMI/UCB0SCL P6.0/CB0/A0 B2 0.1u_0201_10V6K
0.1u_0201_10V6K 5 GND INT 6
TESTPAD TP75 UART_G9 G9 P3.2/UCB0CLK/UCA0STE P6.1/CB1/A1 B1 2200P_0402_50V7K VDD DNC3
TESTPAD TP79 UART_G7 G7 P3.3/UCA0TXD/UCA0SIMO P6.2/CB2/A2 C2 2
P3.4/UCA0RXD/UCA0SOMI P6.3/CB3/A3 KXTI9-1001_LGA10_3X3

C6 E6
D4 Reserved1 Reserved8 F3 RST_MSP430_R#
0_0402_5% 2 @ 1R186
Reserved2 Reserved9 RST_MSP430# 18
D5 F4
D6 Reserved3 Reserved10 F5
C E3 Reserved4 Reserved11 F6 C
E4 Reserved5 Reserved12 F7
E5 Reserved6 Reserved13 F8
Reserved7 Reserved14 G3 +3VS
Reserved15
+3VS
U28
MCU_I2C_SCL 8 6 C191 0.1u_0201_10V6K
R235 R236
MSP430F5528IZQE_BGA80 U15 SCL0/A VCC/B 7 4.7K_0402_5% 4.7K_0402_5%
MCU_I2C_SDA 1 NC/VCCA 3
SDA0/A EN
5
SCL1/B MCU_I2C_RE_SCL 27
9
2 THERMAL 4
GND SDA1/B MCU_I2C_RE_SDA 27

PCA9517ATP_HWSON8_2X3

MCU_I2C_SCL R2151 @ 2 0_0402_5% MCU_I2C_RE_SCL

MCU_I2C_SDA R2161 @ 2 0_0402_5% MCU_I2C_RE_SDA

+3V_MCU
+5VS
2

R210
0_0402_5%
@
USB_PP5
1

V18_MCU VUSB_MCU VBUS_MCU R1721 @ 2 0_0402_5% PUR_MCU R369 1.4K_0402_1%


18 PUR_PCH_TRIG
1 C287 1 C254 1 C255
2

B B
C183
0.22U_0402_10V6K
0.22U_0402_10V6K 0.22U_0402_10V6K10U_0805_25V6K R85
1

2 2 2 1M_0402_5%

+3V_MCU
PUR_MCU 10K_0402_5% 1 R370 2
@
R42 1M_0402_5% 10K_0402_5% 1 R371 2 RST_MSP430_R#
@
4

Y3 Please pull R370,R371 on the top layer


XT2IN_MCU 1 3 XT2OUT_MCU
2

1 24MHZ_6PF_XRCGB24M000F3M00R0
1
C185 C186

6P_0402_50V9-C 6P_0402_50V9-C
2 2

+3V_MCU
MCU JTAG
TP37 TESTPAD TCK_MSP430 TP32 TESTPAD
A TP38 TESTPAD TMS_MSP430 TP33 TESTPAD A
TEST_MSP430 TP39 TESTPAD TDI_MSP430 TP34 TESTPAD
RST_MSP430_R# TP40 TESTPAD TDO_MSP430 TP36 TESTPAD

Security Classification LC Future Center Secret Data Title

Issued Date 2012/09/03 Deciphered Date 2012/09/03 SENSOR


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
VENUS2 0.1

Date: Saturday, January 26, 2013 Sheet 23 of 46


5 4 3 2 1
5 4 3 2 1

+3VS
HDMI_CLK+_CON 1 2 +3VS 5V_HDMI_S0
C1016 3.3P_0402_50V8C
@
HDMI_CLK-_CON 1 2
C1017 3.3P_0402_50V8C
@

3
4

3
4
RP9
HDMI_TX0+_CON 1 2 2.2K_0404_4P2R_5% RP8
C1022 3.3P_0402_50V8C 2.2K_0404_4P2R_5%
@

2
1

5
HDMI_TX0-_CON 1 2

2
1
C1021 3.3P_0402_50V8C
D D
@
VGA_HDMI_CLK 4 3 HDMI_SCL
16 VGA_HDMI_CLK

2
HDMI_TX1+_CON 1 2
C1024 3.3P_0402_50V8C Q140B
@ AO5800E_SC89-6
HDMI_TX1-_CON 1 2 VGA_HDMI_DATA 1 6 HDMI_SDA
16 VGA_HDMI_DATA
C1023 3.3P_0402_50V8C
@
Q140A
HDMI_TX2+_CON 1 2 AO5800E_SC89-6
C1028 3.3P_0402_50V8C
@
HDMI_TX2-_CON 1 2
C1027 3.3P_0402_50V8C
+5VS
@ 5V_HDMI_S0

TP103
Q5 TESTPAD
FDG315N_SC70-6 TP244

6 F1
4 5 1 2
2
1 0.5A_6V_0805L050WR C249

0.1u_0201_10V6K D31

3
HDMI_CLK-_CON 1
HDMI_CLK+_CON 2 D1+ 10
10,35,36 MAIND 3 D1- NC4 9
C 8 GND1 NC3 7 C
HDMI_TX0-_CON 4 GND2 NC2 6
HDMI_TX0+_CON 5 D2+ NC1
D2-
TPD4EUSB30DQAR_SON10

+3VS
@

2
R862 TP240
1M_0402_5% D32
HDMI_TX1-_CON 1
D1+

2
HDMI_TX1+_CON 2 10
1 3 D1- NC4 9
8 GND1 NC3 7
R1486 1 @ 2 0_0402_5% 1 6 HDMI_HPD_OUT HDMI_TX2-_CON 4 GND2 NC2 6
16 TMDS_D_HPD 5 D2+ NC1
HDMI_TX2+_CON
D2-

2
TP242 R885 TPD4EUSB30DQAR_SON10
Q141A
20K_0402_5%
HDMI_HPD_OUT

HDMI_SDA
HDMI_SCL

AO5800E_SC89-6
@

1
2

U37 U33 U38


2

B B
AIES12U020R2_0402-2
AIES12U020R2_0402-2
AIES12U020R2_0402-2

@ @ @
5V_HDMI_S0
1

1
1

C250
DLP11SN900HL2L_4P
16 VGA_HDMI_TX0+ VGA_HDMI_TX0+ CV255 1 2 0.1U_0402_10V6K HDMI_TX0+_C 4 3 0.1u_0201_10V6K
J11
18 15 HDMI_SCL
VGA_HDMI_TX0- CV256 1 2 0.1U_0402_10V6K HDMI_TX0-_C 1 2 +5V_POWER SCL 16 HDMI_SDA
16 VGA_HDMI_TX0- SDA
HDMI_CLK+_CON R342 1 2680_0402_5%
L12 HDMI_TX0+_CON 7
HDMI_CLK-_CON R344 1 2680_0402_5% DLP11SN900HL2L_4P HDMI_TX0-_CON 9 TMDS_DATA0+ 13
VGA_HDMI_TX1+ CV257 1 2 0.1U_0402_10V6K HDMI_TX1+_C 4 3 HDMI_TX1+_CON 4 TMDS_DATA0- CEC 17
16 VGA_HDMI_TX1+ TMDS_DATA1+ DDC/CEC_GROUNG
HDMI_TX0+_CON R381 1 2680_0402_5% HDMI_TX1-_CON 6 19 HDMI_HPD_OUT
HDMI_TX2+_CON 1 TMDS_DATA1- HOT_PLUG_DETECT
HDMI_TX0-_CON R382 1 2680_0402_5% VGA_HDMI_TX1- CV258 1 2 0.1U_0402_10V6K HDMI_TX1-_C 1 2 HDMI_TX2-_CON 3 TMDS_DATA2+ 14
16 VGA_HDMI_TX1- TMDS_DATA2- RESERVED#14
HDMI_TX1+_CON R383 1 2680_0402_5% L13 8
L14 5 TMDS_DATA0_SHIELD
HDMI_TX1-_CON R384 1 2680_0402_5% VGA_HDMI_TX2+ CV259 1 2 0.1U_0402_10V6K HDMI_TX2+_C 1 2 2 TMDS_DATA1_SHIELD
16 VGA_HDMI_TX2+ TMDS_DATA2_SHIELD
HDMI_TX2+_CON R385 1 2680_0402_5% 20
VGA_HDMI_TX2- CV260 1 2 0.1U_0402_10V6K HDMI_TX2-_C 4 3 11 GND0 21
16 VGA_HDMI_TX2- TMDS_CLOCK_SHIELD GND1
HDMI_TX2-_CON R389 1 2680_0402_5% HDMI_CLK+_CON 10 22
DLP11SN900HL2L_4P HDMI_CLK-_CON 12 TMDS_CLOCK+ GND2 23
DLP11SN900HL2L_4P TMDS_CLOCK- GND3
3

A A
Q141B 16 VGA_HDMI_CLK+ VGA_HDMI_CLK+ CV253 1 2 0.1U_0402_10V6K HDMI_CLK+_C 4 3

5
+3VS
AO5800E_SC89-6 16 VGA_HDMI_CLK- VGA_HDMI_CLK- CV254 1 2 0.1U_0402_10V6K HDMI_CLK-_C 1 2 ACON_HMR2S-AK120F

1 @ 2 L15
4

R388 100K_0402_5% Title


Security Classification LC Future Center Secret Data
Issued Date 2012/09/03 Deciphered Date 2012/09/03 HDMI CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
VENUS2
Date: Saturday, January 26, 2013 Sheet 24 of 46
5 4 3 2 1
5 4 3 2 1

TP245
L36
1 2
+3VS +3V_mSATA

BLM15PX121SN1D_2P
1 1
C137 @ C340
C1019
22U_0603_4V6M 4.7U_0402_6.3V6M
0.1u_0201_10V6K
2 2
D D

MINI PCIE CON FOR mSATA (Full Card)


TESTPAD
TP77
+3V_mSATA +3V_mSATA
JP6

1.5V_mSATA 6 13
+1.5V_1 REFCLK+ 11
2 REFCLK-
+3.3V_1 23 C205 2 1 0.01U_0201_10V6K
PERN0 SATA_RXP0 13
28 25 C182 2 1 0.01U_0201_10V6K
+1.5V_2 PERP0 SATA_RXN0 13
48
+1.5V_3 31 C247 2 1 0.01U_0201_10V6K
PETN0 SATA_TXN0 13
52 33 C248 2 1 0.01U_0201_10V6K
+3.3V_2 PETP0 SATA_TXP0 13
24 36
+3.3VAUX USB_D- 38
USB_D+
3 30
5 RESERVED#1 SMB_CLK 32
8 RESERVED#2 SMB_DATA
10 UIM_PWR
12 UIM_DATA 1
14 UIM_CLK WAKE# 7
16 UIM_RESET CLKREQ# 22
17 UIM_VPP PERST#
19 UIM_C8
C 20 UIM_C4 4 C
37 W_DISABLE# GND1 9
39 RESERVED#3/GND GND2 15
41 RESERVED#4/+3.3V GND3 18
43 RESERVED#5/+3.3V GND4 21
R200 @ 45 RESERVED#6/GND GND5 26
100_0402_1% 47 RESERVED#7 GND6 27
EC_TX 1 2 49 RESERVED#8 GND7 29
31,34 EC_TX 1 2 51 RESERVED#9 GND8 34
EC_RX
31,34 EC_RX RESERVED#10 GND9 35
100_0402_1% GND10 40
R197 @ 42 GND11 50
44 LED_WWAN# GND12 53
46 LED_WLAN# SHIELD1 54
LED_WPAN# SHIELD2
55
NP_NC1 56
NP_NC2

ACES_50714-0524W-001

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/09/03 Deciphered Date 2012/09/03 SSD


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
VENUS2 0.1

Date: Saturday, January 26, 2013 Sheet 25 of 46


5 4 3 2 1
5 4 3 2 1

D D
TP154

FAN Conn

+5VS

JFAN1
1 5
2 1 GND1
3 2
2 1 3
4 6
C986 C175 @ 4 GND2
10U_0805_10V6K 0.1U_0402_10V7K
1 2 ACES_50208-00401-001

34 EC_FAN_SPEED

TP115
34 EC_FAN_PWM TESTPAD

Close U35 SMSC thermal sensor


1
REMOTE1+
+3VS placed near by VRAM Close to memory side
REMOTE1+
C451 U35 1

1
2200P_0402_50V7K @ C
2 REMOTE1- C982 2 Q137
C 1 10 EC_SMB_CLK_DEV 100P_0402_50V8J B MMST3904-7-F_SOT323-3 C
VDD SMCLK EC_SMB_CLK_DEV 27,34 2 E

3
2 1 REMOTE1+ 2 9 EC_SMB_DAT_DEV REMOTE1-
DP1 SMDATA EC_SMB_DAT_DEV 27,34
C193
REMOTE2+ C443 REMOTE1- 3 8 TEMP_ALERT# TEMP_ALERT# 34
0.1U_0402_16V4Z
1U_0402_10V6K DN1 ALERT#
1 1 2 REMOTE2+ 4 7 SYS_SHDN# SYS_SHDN# 34
DP2 THERM#
C658
2200P_0402_50V7K REMOTE2- 5 6 Close to PCH side
2 REMOTE2- DN2 GND TP247 +3VS REMOTE2+
TP248 1

1
@ C
2
FAN_PWM & TACH EMC1403-2-AIZL-TR_MSOP10 C984
100P_0402_50V8J B
Q138
MMST3904-7-F_SOT323-3
2

1
for PWM FAN Address 1001_101xb E

3
R625 R624 REMOTE2-
10K_0402_5% 10K_0402_5%

TEMP_ALERT#

2
internal pull up 1.2K to 1.5V REMOTE2+/-:
R for initial thermal SYS_SHDN# Trace width/space:10/10 mil
shutdown temp Trace length:<8"

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/09/03 Deciphered Date 2012/09/03 Thermal Sensor/ FAN


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
VENUS2 0.1

Date: Saturday, January 26, 2013 Sheet 26 of 46


5 4 3 2 1
5 4 3 2 1

JP1014
1 2
USB_PN10 3 1 2 4 USB_PN9
D 17 USB_PN10 5 3 4 6 USB_PN9 17 D
USB_PP10 USB_PP9
17 USB_PP10 7 5 6 8 USB_PP9 17
ALS_INT# 9 7 8 10 USB_PN7
34 ALS_INT# 11 9 10 12 USB_PN7 17
INT_COMPASS USB_PP7
23 INT_COMPASS 13 11 12 14 USB_PP7 17
INT_MPU6050
23 INT_MPU6050 15 13 14 16
MCU_ALS_INT# PCH_SMB_CLK
23 MCU_ALS_INT# 17 15 16 18 PCH_SMB_CLK 12,14
SPK_R+ PCH_SMB_DAT PCH_SMB_CLK TP256
28 SPK_R+ 19 17 18 20 PCH_SMB_DAT 12,14
SPK_R- TP_CLK PCH_SMB_DAT TP257
28 SPK_R- 21 19 20 22 TP_CLK 34
LID_PAD# TP_DATA TP_CLK TP258
34 LID_PAD# 23 21 22 24 TP_DATA 34
EC_SMB_DAT_DEV EC_SMB_CLK TP_DATA TP259
26,34 EC_SMB_DAT_DEV EC_SMB_CLK_DEV 25 23 24 26 EC_SMB_DAT EC_SMB_CLK 34,38 EC_SMB_CLK TP260
26,34 EC_SMB_CLK_DEV AC_IN 27 25 26 28 MCU_I2C_RE_SDA EC_SMB_DAT 34,38
+3VS 34 AC_IN ADAPTER_ID 29 27 28 30 MCU_I2C_RE_SCL MCU_I2C_RE_SDA 23 MCU_I2C_RE_SDA TP262
34 ADAPTER_ID ADAPTER_ID_ON# 31 29 30 32 MCU_I2C_RE_SCL 23 MCU_I2C_RE_SCL TP263
+3VALW +3VLP 34 ADAPTER_ID_ON# 31 32
AC_IOT 33 34
34 AC_IOT 35 33 34 36
37 35 36 38
TP278 39 37 38 40 PSENSOR_IRQ# PSENSOR_IRQ# TP249
41 39 40 42 PSENSOR_IRQ# 34
CAMERA_END CAMERA_END TP250
43 41 42 44 CAMERA_END 36
WIN8_BUTTON# WIN8_BUTTON# TP251
45 43 44 46 WIN8_BUTTON# 34
USB_OC#4 USB_OC#4 TP252
47 45 46 48 USB_ON USB_OC#4 17
49 47 48 50 ROTATION_LOCK# USB_ON 30,34 ROTATION_LOCK# TP254
49 50 ROTATION_LOCK# 34
C C

ACON_BBR43-50KB533
USB_PN10
USB_PP10 TP255

ALS_INT# TP264
INT_COMPASS TP265
INT_MPU6050 TP266
MCU_ALS_INT# TP267
SPK_R+ TP268
SPK_R- TP269
LID_PAD# TP270
EC_SMB_DAT_DEV TP271
EC_SMB_CLK_DEV TP272
AC_IN TP273
ADAPTER_ID TP274
ADAPTER_ID_ON# TP275 BATT+
AC_IOT TP276
PTP28 PTP34 PTP18
JP8 PTP35
1
BATT+ 1
B 2 7 B
B+ 2 SIDE2
3
+5V 3
4 6
5 4 SIDE1
5 B+

ACES_50269-00501-001 PTP38 PTP39 PTP40

+5V

PTP42 PTP43

Place in BOT side for Production Line Test


A A

Security Classification LC Future Center Secret Data Title


Issued Date 2012/09/03 Deciphered Date 2012/09/03 Cardreader
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
VENUS2
Date: Saturday, January 26, 2013 Sheet 27 of 46
5 4 3 2 1
5 4 3 2 1

TP94
TESTPAD J7
1 2
+3VS +3V_AUD
L44
+3V_AUD JUMPER
1 2
R106 1 @ 2 0_0402_5%
BLM15BD221SN1D_2P TP101
TESTPAD
1
C380 C319 C320
@ +5VS +5V_AUD R20 1 @ 2 0_0402_5%
L34
10U_0402_6.3V6M
0.1u_0201_10V6K
0.1u_0201_10V6K
2 1 2
D D
BLM15PX121SN1D_2P
AUDGND

Tied at one point only under the


+3V_AUD
Codec or near the Codec

1
C377 C273 C329
@
10U_0402_6.3V6M
0.1u_0201_10V6K
0.1u_0201_10V6K FILT_1.8V
2 TP287
1
C362 C263

10U_0402_6.3V6M
0.1u_0201_10V6K 1
2 C214 C316

1U_0402_10V6K
0.1u_0201_10V6K
2
CX20672-21Z_QFN40_6X6
TP283 U30
LDO_OUT_3.3V
HDA_SDIN0 13 HDA_RST# 9 3 AUDGND
RESET# FILT_1.8
1

C238 2 TP286
@ 5 VAUX_3.3 7
13 HDA_BCLK_24M BIT_CLK VDD_IO 1
20P_0201_25V8 13 HDA_SYNC_CODEC 8 18 C381 C321
SYNC DVDD_3.3
2

R196 33_0402_5%6 26 +5V_AUD


13 HDA_SDIN0 SDATA_IN AVDD_HP
13 HDA_SDOUT 4 10U_0402_6.3V6M
0.1u_0201_10V6K
SDATA_OUT 2
29 1
FILT_1.65 C382 C324
TP284 27 @
AVDD_3.3 AUDGND 10U_0402_6.3V6M
0.1u_0201_10V6K
33_0402_5% 10 28 2
C
13 PCH_BEEP C323 0.1u_0201_10V6K BEEP#_L R195
39 PC_BEEP
SPDIF
CX20672-21Z AVDD_5V
+5V_AUD
C
12 +3V_AUD
TP280 LPWR_5.0
1 1
38 15 C327 C325 C326
C383 C384
37 GPIO0/EAPD# RPWR_5.0 @ R283
34 VOL_MUTE# GPIO1/SPK_MUTE# 17 0.1u_0201_10V6K0.1u_0201_10V6K
0.1u_0201_10V6K
10U_0402_6.3V6M
10U_0402_6.3V6M
CLASS-D_REF 2 2 5.11K_0402_1%
R51 33_0402_5% 40
31 DMIC_CLK 1 DMIC_CLK 36
for MIC noise_20121223 31 DMIC_DATA SENSE_A
DMIC_1/2 SENSE_A
DMIC_CLK 35 MIC_R
SPK_L+ 11 PORTB_R 34 MIC_L
LEFT+ PORTB_L
1

SPK_L- 13 33 PORTB_BIAS TP282


C390 LEFT- B_BIAS
47P_0402_50V8J 32
C_BIAS
2

SPK_R- 14 31
27 SPK_R- RIGHT- PORTC_R
SPK_R+ 16 30
27 SPK_R+ RIGHT+ PORTC_L
19
C3421 21U_0402_10V6K 20 FLY_P 25
FLY_N NC2 24
AVEE 21 NC1
AVEE 23 HP_R
1 PORTA_R
C328 C385 22 HP_L
PORTA_L
0.1u_0201_10V6K
10U_0402_6.3V6M
2

41
GND

B B

TP116
TESTPAD
ACES_50208-00201-001
BEEP#_L AUDGND
1 1 SPK_L+ L10 1 2 BLM15AG121SH1D_2P 1
C378 C379 L11 1 2 BLM15AG121SH1D_2P 2 1
2
1

JP1007 TP117 TESTPAD


470P_0402_50V8-J
470P_0402_50V8-J 1 1
@ RA3 2 2 1 C152 C151 3
10K_0402_5% HP_L R57 62_0402_1% HP_L_R 2 1 SPK_L- 4 GND
3 2 1000P_0402_50V7K 1000P_0402_50V7K GND
3
2

HP_R R59 62_0402_1% HP_R_R 4 2 2


4 JP1003
R164 39.2K_0402_1% PORTA JACK SENSE 5
7 5
6 7
6

Q15
3

DMG1012T-7_SOT523-3 AUDGND PORTB_BIAS_CNTL


2 R161 33K_0402_5% PORTB_BIAS_CNTL R205 100_0402_5% C3491 22.2U_0402_6.3V6M
MIC_L HP_R_R
HP_L_R
1 C3501 22.2U_0402_6.3V6M
MIC_R PORTA JACK SENSE
C215 R62
D7 D9 D10 D11
1

1
1U_0402_10V6K 2K_0402_5%
SENSE_A R1631 220K_0402_1%
PORTB JACK SENSE 2
PORTB_BIAS
AUDGND @ @ @
A R63 A

2
4.7K_0402_5%
UCLAMP0511T.TCT_SLP1006P2T2
UCLAMP0511T.TCT_SLP1006P2T2
UCLAMP0511T.TCT_SLP1006P2T2
UCLAMP0511T.TCT_SLP1006P2T2

AUDGND

Security Classification LC Future Center Secret Data Title

Issued Date 2012/09/03 Deciphered Date 2012/09/03 AUDIO/ SPK/ MIC


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
VENUS2 0.1

Date: Wednesday, January 30, 2013 Sheet 28 of 46


5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/09/03 Deciphered Date 2012/09/03 SENSOR


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
VENUS2 0.1

Date: Saturday, January 26, 2013 Sheet 29 of 46


5 4 3 2 1
5 4 3 2 1

USB3.0_PWR_1

USB3.0 &USB2.0 Port JP7

C253 0.1u_0201_10V6K USB3_TX4_P_U 9


17 USB3_TX4_P 1 STDA_SSTX+
C261 0.1u_0201_10V6K USB3_TX4_N_U 8 VBUS
RP16 17 USB3_TX4_N
D 1 4 2 STDA_SSTX- D
17 USB_PN3 2 3 4 D-
17 USB_PP3 3 GND 10
0_0404_4P2R_5% 6 D+ GND_PAD1 11
17 USB3_RX4_P 7 STDA_SSRX+ GND_PAD2 12
5 GND_D GND_PAD3 13
17 USB3_RX4_N STDA_SSRX- GND_PAD4

2
U13 U14

2
+5V AIES12U020R2_0402-2
AIES12U020R2_0402-2
USB3.0_PWR_1
@ @

C174

1
TP288
0.1u_0201_10V6K USB3.0_PWR_1
U8

1
1 8 R144 1 @ 2 0_0402_5%
2 GND FAULT 7 USB_OC#1 17
TP110 1
TESTPAD 3 IN1 OUT1 6
4 IN2 OUT2 5 CT13 +
27,34 USB_ON EN ILIM 220U_B2_6.3VM_R35M C281
9 0.1u_0201_10V6K
GND_PAD 2

1
C
TPS2557DRBR_SON8_3X3 R312 C
48.7K_0402_1%

D33 @
USB3_TX4_P_U 1
USB3_TX4_N_U 2 D1+ 10
3 D1- NC4 9
8 GND1 NC3 7
USB3_RX4_P 4 GND2 NC2 6
USB3_RX4_N 5 D2+ NC1
D2-
TPD4EUSB30DQAR_SON10
B B

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2012/09/03 Deciphered Date 2012/09/03 USB2.0/ USB3.0
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
VENUS2
Date: Saturday, January 26, 2013 Sheet 30 of 46
5 4 3 2 1
5 4 3 2 1

WIFI$BT Board Connector +3V_WLAN


+3VALW RTC Connector
R1892 @ 110K_0402_5% WLAN_OFF#
TP104 C176 +3VS +3V_WLAN
R1922 @ 110K_0402_5% BT_OFF# TESTPAD @
0.1u_0201_10V6K
U5 L39 1 2BLM15PX121SN1D_2P TP107
1 8 TP108
2 GND OC1 7 L35 1 @ 2BLM15PX121SN1D_2P RTC_VCC
3 IN OUT1 6
TP97 34 AOAC_WIFI_ON EN1 OUT2 JP4
4 5 2 2 1
TESTPAD EN2 OC2 @ C233 1
9 C138 C348 2 1
PAD 0.1U_0402_25V6 1U_0402_10V6K 2
JP1010 TPS2066ADRBR_SON8_3X3 1
0.1U_0402_25V6 1 2 3
D
1 2 4 GND1 D
+3V_WLAN 1 2 WLAN_OFF# 34 GND2
3 4
5 3 4 6 WIFI_USB_PN6
7 5 6 8 WIFI_USB_PP6 ACES_50208-00201-001
9 7 8 10
11 9 10 12
11 12 +3V_WLAN
13 14
15 13 14 16 BT_OFF# 34
R23 2 @ 110K_0402_5%
17 15 16 18
19 17 18 20 BT_USB_PP12 +3VALW
21 19 20 22 U6
BT_USB_PN12 @
23 21 22 24 9 7
23 24 VDD D_IN_B USB_PP6 17
25 26 WIFI_USB_PP6 1 6
25 26 WAKE_ON_WLAN 34 D_OUT D_IN_B# USB_PN6 17
27 28 C177 WIFI_USB_PN6 2 5
29 27 28 30 WLAN_HOST_WAKE 34 3 D_OUT# D_IN_A 4
29 30 +3V_WLAN GND D_IN_A#
0.1u_0201_10V6K 8 10 R50 1 @ 2 0_0402_5%
OE# SEL SUSON 34,36,40
31 32
33 GND1 GND2 34 PI3USB42ZMEX_UQFN10_1P4X1P8
GND3 GND4 @
WIFI_USB_PP6 R185 1 @ 2 0_0402_5% USB_PP6 U36 +3VALW
WIFI_USB_PN6 R182 1 @ 2 0_0402_5% USB_PN6
1 3 1 R259 1 2 0_0402_5%
HRS_DF40C-30DP-0P4V(51) NC VDD
C389
0.1U_0402_25V6
2 4 2 @
GND OUT LID_KB# 34
+3VALW
U18 @
9 7
1 VDD D_IN_B 6 USB_PP12 17
BT_USB_PP12 HGDESM031A_MAP4_1P1X0P9
D_OUT D_IN_B# USB_PN12 17
C178 BT_USB_PN12 2 5
@ 3 D_OUT# D_IN_A 4
0.1u_0201_10V6K 8 GND D_IN_A# 10
R53 1 @ 2 0_0402_5% SUSON
OE# SEL
PI3USB42ZMEX_UQFN10_1P4X1P8

C
UART Debug Connector C

Keyboard Connector
ACES_50519-02601-001
TP118 TESTPAD KSO0
TP119 TESTPAD KSO1 28 26
G2 26 KSO0 34
TP120 TESTPAD KSO2 27 25
G1 25 KSO1 34
@ TP121 TESTPAD KSO3 24
24 KSO2 34
+5VS RM890 1 2
0_0402_5% TP122 TESTPAD KSO4 23
23 KSO3 34
J10 TP123 TESTPAD KSO5 22
22 KSO4 34
RM892 1 @ 2 0_0402_5% 1 5 TP124 TESTPAD KSO6 21
+3VS 1 GND1 21 KSO5 34
2 TP125 TESTPAD KSO7 20
25,34 EC_TX 2 20 KSO6 34
3 TP126 TESTPAD KSO8 19
25,34 EC_RX 3 19 KSO7 34
4 6 TP127 TESTPAD KSO9 18
4 GND2 18 KSO8 34
1

TP128 TESTPAD KSO10 17


17 16 KSO9 34
R261 TP129 TESTPAD KSO11
100K_0402_5% 16 KSO10 34
ACES_50208-00401-001 TP130 TESTPAD KSO12 15
15 14 KSO11 34
R_0402 TP131 TESTPAD KSO13
14 KSO12 34
@ TP132 TESTPAD KSO14 13
13 KSO13 34
2

TP133 TESTPAD KSO15 12


12 KSO14 34
TP134 TESTPAD KSI0 11
11 KSO15 34
TP135 TESTPAD KSI1 10
10 9 KSI0 34
TP136 TESTPAD KSI2
9 KSI1 34
TP137 TESTPAD KSI3 8
8 KSI2 34
TP138 TESTPAD KSI4 7
7 KSI3 34
TP139 TESTPAD KSI5 6
6 KSI4 34
TP140 TESTPAD KSI6 5
5 KSI5 34
TP141 TESTPAD KSI7 4
4 KSI6 34
3
3 KSI7 34
2
2 1 1RM889 0_0402_5%
2 CAP_LED# 34
+3VS_CAPSLK
1 +3VS
@
JP3 RM891 1 @ 2 0_0402_5%
B +3VALW B

TP142 TESTPAD TP156

Power&Volume Board Connector

JP2
1
34 VOLUME_UP# 1
2 VOLUME_UP# TESTPAD TP143
34 VOLUME_DOWN# 2
+3VS 3 16 VOLUME_DOWN# TESTPAD TP144
4 3 GND1
28 DMIC_CLK 4
5
28 DMIC_DATA 6 5
7 6
34 NBSWON# 7
8
34 NOVO_BTN# 8
9 NOVO_BTN# TESTPAD TP148
+3VALW 9
10 15
34 MBATLED_ORANGE# 10 GND2
11 MBATLED_ORANGE# TESTPAD TP149
34 MBATLED_WHITE# 11
12 MBATLED_WHITE# TESTPAD TP150
13 12
22 LID_30# 13
R2501 @ 2 0_0402_5% 14
34 PWR_LED# 14 PWR_LED# TESTPAD TP152

ACES_50501-0140N-001
A A

NBSWON#

D36
1

Security Classification LC Future Center Secret Data Title


@
Issued Date 2012/09/03 Deciphered Date 2012/09/03 Connector
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
UCLAMP0511T.TCT_SLP1006P2T2 Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
VENUS2 0.1

Date: Monday, January 28, 2013 Sheet 31 of 46


5 4 3 2 1
5 4 3 2 1

D D

46J_BARCODE_16X7 UUID_BARCODE_16X7
B1 B2

1
1

1
FD1 FD2 FD3 FD4
1

C C

H37 H38 H39 H40 H41


HOLEA HOLEA HOLEA HOLEA HOLEA
1

padl_ct5p0d8p0d3p2 padl_ct5p0d3p2 padl_ct5p0d8p0d3p2 padl_ct5p0d8p0d3p2 padl_ct5p0d8p0d3p2

H28 H35
HOLEA HOLEA
1

PAD_CT5P0B10P0D3P0 PAD_C8P0D5P2

H36
HOLEA H26
HOLEA
B B
1

PAD_C8P0D5P4 PAD_SHAPET8P0X6P5B8P0X6P5D2P5

H25 H27
HOLEA HOLEA
1

PAD_CB5P0D2P1 PAD_CB5P0D2P5

H34
HOLEA
1

PAD_SHAPET8P4X8P0CB8P0D5P2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/09/03 Deciphered Date 2012/09/03 Screw and Hole


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
VENUS2 0.1

Date: Saturday, January 26, 2013 Sheet 32 of 46


5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/09/03 Deciphered Date 2012/09/03 HALL SENSOR


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
VENUS2 0.1

Date: Saturday, January 26, 2013 Sheet 33 of 46


5 4 3 2 1
5 4 3 2 1

SH BM=1: Enable shared m em ory with hos t BIOS

I/O Addres s
BADDR1-0 Index Data
AO5804EL_SC 89-6 0 0 2E 2F
Q35A 0 1 4E 4F
(For PLL Power) 1 0 (HCFGBAH, HCFGBAL) (HCFGBAH, HCFGBAL)+1
1 1 Res erved
EC _SMB_CLK 6 1
+3VALW EC _SMB_CLK_DEV 26,27
BLM15BD 221SN 1D_2P TP98 VCCRTC VCCRTC_EC
TESTPAD L56
@ @ +3VS
+3VLP L57 1 2 +3VALW_EC R256 +3VALW_EC _R 1 2 R160 1 2 0_0402_5% RP29
1 2 0_0402_5% MAINON 36,40,41,42 2
@ +5VS R442 110K_0402_5% 1 4
BLM15BD 221SN 1D_2P @ IMVP_VR_ON 43 2 3
BLM15BD 221SN 1D_2P PM_RSMRST# 15
L55 1 2 R1681 2 0_0402_5% 5
1 1 @ 10K_0404_4P2R_5%
D PC H_DPWROK 15 D
C294 C344 C295 C308 C315 C335 C336 C296
WIN8_BU TTON# 27
C373
@ 10U_0402_6.3V6M
0.1u_0201_10V6K 1U_0402_10V6K
0.1u_0201_10V6K 0.1u_0201_10V6K
0.1u_0201_10V6K
0.1u_0201_10V6K
0.1u_0201_10V6K
0.1u_0201_10V6K R155 1 2 0_0402_5% EC _SMB_DAT 3 4
2 2 ALS_INT# 27 EC _SMB_DAT_DEV 26,27
R258 1 @ 2 0_0402_5%
WLAN_HOST_WAKE 31
R257 1 @ 2 0_0402_5%
+3VS+3VALW_EC _R LID_KB# 31 Q35B
R154 1 @ 2 0_0402_5%
Should have a 0.1uF capacitor clos e to every WAKE_ON_WLAN 31 AO5804EL_SC 89-6
PM_CLKR UN# 15
GND-VCC pair + one larger cap on the C322 2 10.01U_0201_10V6K +3VALW_EC
s upply. * Recommended net "+3VAUX"
and "RTCVCC" minimum trace
width 12mils. UE1 RP31 4.7K_0404_4P2R_5%

C11

C12
E12

A10

A11
B12
F12
F10
J12
EC _SMB_CLK 1 4

G5
G8

G2
G3
IT8519G-H X_TFBGA128 +3VS

D1
E6
E7
E8

A1

E5
EC _SMB_DAT 2 3
E1 B6

VBAT

EG CLK/W UI27/G PE3(Dn)


EG CS#/W UI26/G PE2(Dn)
EG AD/W UI25/G PE1(Dn)

L80HLAT/BAO /W UI24/G PE0(Dn)


L80LLAT/W UI7/G PE7(Up)

HMO SI/G PH6/ID6(Dn)


HMISO /G PH5/ID5(Dn)

CLKRUN#/W UI16/G PH0/ID0(Dn)


HSCK/G PH4/ID4(Dn)
HSCE#/W UI19/G PH3/ID3(Dn)
13 LPC _AD0 EC _SMB_CLK 27,38

VCC
VSTBY1
VSTBY2
VSTBY3
VSTBY4
VSTBY5

AVCC

VSTBY6
D2 LAD0/GPM0(X) SMCLK0/GPB3(X) C6
13 LPC _AD1 D4 LAD1/GPM1(X) SMDAT0/GPB4(X) B5 EC _SMB_DAT 27,38
13 LPC _AD2 LAD2/GPM2(X) SM BUS SMCLK1/GPC1(X) EC _SMB_CLK1 14

4
3
C3 A6
13 LPC _AD3 LAD3/GPM3(X) SMDAT1/GPC2(X) EC _SMB_DAT1 14
R179 1 @ 2 0_0402_5%
H3 C5 RP30 NBSWON # R472 110K_0402_5%
17,6 PLT_RST# E2 LPCRST#/WUI4/GPD2(Up) PECI/SMCLK2/WUI22/GPF6(Up) C4 PECI_EC 18
+3VALW_EC TP314 10K_0404_4P2R_5% NOVO_BTN# R552 110K_0402_5%
17 CLK_PC I_LPC D3 LPCCLK/GPM4(X) SMDAT2/WUI23/GPF7(Up) PC H_SU SACK# 15 LID_PAD# R642 110K_0402_5%
13 LPC _FRAME# LFRAME#/GPM5(X) E10 WIN8_BU TTON# R672 110K_0402_5%
PS2CLK0/TMB0/GPF0(Up) ADAPTER _ID_ON# 27

1
2
D19 2 1 R180 1 @ E3
2 0_0402_5% E11 MBATLED _ORANGE# 2
R254 @ 110K_0402_5%
18 H_A20GATE 15 SU S_STAT# LPCPD#/WUI6/GPE6(Dn) PS2DAT0/TMB1/GPF1(Up) D11 ME_FLASH 13 2 110K_0402_5%
R174 MBATLED _WHITE# R255 @
PS2CLK2/WUI20/GPF4(Up) TP_CLK 27
D17 2 1 B2 D12

PS/2
18 KBSMI# SD M10U45LP-7_DFN1006-2-2 A2 GA20/GPB5(X) PS2DAT2/WUI21/GPF5(Up) TP_DATA 27
100K_0402_5%
13,18 INT_SERIRQ SERIRQ/GPM6(X) LPC
D20 2 1 F2
18 SC I# SD M10U45LP-7_DFN1006-2-2 H2 ECSMI#/GPD4(Up)
EC _WRST# F1 ECSCI#/GPD3(Up)
WRST# MIN 10us
SD M10U45LP-7_DFN1006-2-2 WRST# GPIO
TP311 C2 +3VS
D21 2 1 G1 KBRST#/GPB6(X)
1 PWUREQ#/BBO/SMCLK2ALT/GPC7(Up)
C343 18 H_RCIN#

IT8519
2 M10U45LP-7_DFN1006-2-2
D18 SD 1 J3
15 PC H_PWRBTN# PWM0/GPA0(Up) EC _FAN_PWM 26
1U_0402_10V6K J2
2 PWM1/GPA1(Up) J1 PWR_LED # 31
TP293 SYS_PWROK R822 110K_0402_5%
SD M10U45LP-7_DFN1006-2-2 USB_ON 27,30
BGA-128
B4 PWM2/GPA2(Up) K1
18 PC H_GP27_WAKE# A4 CRX0/GPC0(Dn) PWM3/GPA3(Up) M1 PM_BATLOW# 15 H_A20GATE 2 110K_0402_5%
CTX0/TMA0/GPB2(Dn) CIR EC _PWM_BKLT 22 TP294 R126
15 PM_PC H_PWROK PWM4/GPA4(Up) L1
PWM5/GPA5(Up) LID_PAD# 27 2 110K_0402_5%
Not pin to pin ! PWM
VOLUME_UP# R159

G12 VOLUME_DOWN # 2
R169 110K_0402_5%
C 31 MBATLED _ORANGE# B9 DAC4/DCD0#/GPJ4(X) L6 EC _FAN_PWM 2 110K_0402_5% C
R187 @
31 MBATLED _WHITE# L2 DSR0#/GPG6(X) TACH0A/GPD6(Dn) J9 AUXON 39 EC _FAN_SPEED 2 110K_0402_5%
EC _FAN_SPEED 26 TP298 R201
31 WLAN_OFF# D10 GINT/CTS0#/GPD5(Up) TACH1A/TMA1/GPD7(Dn)
40 1.35VSU S_PWRGD F11 PS2DAT1/RTS0#/GPF3(Up) A5 VOL_MUTE ROTATION_LOCK# 2 110K_0402_5%
R170 @
15 AC_PR ESEN T D9 DAC5/RIG0#/GPJ5(X) TMRI0/WUI2/GPC4(Dn) B3
31 CAP_LED # EC _TX A8 PS2CLK1/DTR0#/GPF2(Up) TMRI1/WUI3/GPC6(Dn) MBAT_PR ES# 38 ALS_INT# 2 110K_0402_5%
R171
25,31 EC _TX B8 TXD/SOUT0/GPB1(Up)
EC _RX
25,31 EC _RX RXD/SIN0/GPB0(Up)
+3VALW_EC K11 UART port A3
15 SU SC # J11 ADC5/DCD1#/WUI29/GPI5(X) PWRSW/GPE4(Up) F3 NBSWON # 31 +3V
15,36 SLP_SU S# H11 ADC6/DSR1#/WUI30/GPI6(X) RI1#/WUI0/GPD0(Up) H1 NOVO_BTN# 31
15 SU SB# M3 ADC7/CTS1#/WUI31/GPI7(X) RI2#/WUI1/GPD1(Up) MXLID# 22
27 AC_IN RTS1#/WUI5/GPE5(Dn) WAKE UP
K2
31 AOAC_WIFI_ON C7 PWM7/RIG1#/GPA7(Up) A7 @
42,6 ALL_SYS_PWRGD B11 DTR1#/SBUSY/GPG1/ID7(Dn) RING#/PWRFAIL#/CK32KOUT/LPCRST#/GPB7(Dn) ROTATION_LOCK# 27
R184 4.7K_0402_5% TP301 R217 1
SU SOK @ 2 0_0402_5% R177 100K_0402_5%
15 SYS_PWROK CTX1/WUI18/SOUT1/GPH2/SMDAT3/ID2(Dn)
R181 1 @ 2 0_0402_5% A12
31,36,40 SU SON CRX1/WUI17/SIN1/SMCLK3/GPH1/ID1(Dn)
TP290 2
C8 C338
TP289 R183 C305 EC _SC K
EC _SC E# C10 FSCK TP302 ALL_SYS_PWRGD
U17 EC _SI A9 FSCE#
1 8
4.7K_0402_5%
1
0.01U_0201_10V6K
C9 FMOSI EXTERNAL SERIAL FLASH M12 R232 C339
EC _SC E# EC _SO
EC _SO 2 /CS VCC 7 FMISO ADC0/GPI0(X) L12 SU S_PWR_ACK 15,17 CLK_PC I_LPC 1 0.1u_0201_10V6K
2 1 2
3 DO(IO1) /HOLD 6 EC _SC K H_PR OCHOT K8 ADC1/GPI1(X) K12 AC_IOT 27
TP291
4 /WP CLK 5 EC _SI K7 KSO16/SMOSI/GPC3(Dn) ADC2/GPI2(X) M11 CPU _IMON 43
TP292
GND DI(IO0) 36 CAMERA_EN M2 KSO17/SMISO/GPC5(Dn) ADC3/GPI3(X) L11 TEMP_ALER T# 26 33_0402_5% 10P_0402_50V8J
9 31 BT_OFF# PWM6/SSCK/GPA6(Up) ADC4/WUI28/GPI4(X) ADAPTER _ID 27
GND_PAD FAN_DETEC T R188 1 2 0_0402_5% B10
@ 27 PSEN SOR_IRQ# SSCE0#/GPG2(X) A/D D/A
B7
SSCE1#/GPG0(X) SPI ENABLE @
7 DRAMRST_CNTRL_EC H10 +3VALW_EC
W25X20CLZPIG_WSON8_6X5 R166 1 2 0_0402_5%
L3 TACH2/GPJ0(X) J10 SU SOK SYS_SH DN# 26
31 KSO0 K3 KSO0/PD0 GPJ1(X) G10
31 KSO1 KSO1/PD1 TACH0B/DAC2/GPJ2(X) VOLUME_UP# 31

1
J4 G11
31 KSO2 L4 KSO2/PD2 TACH1B/DAC3/GPJ3(X) VOLUME_DOWN # 31
R176
31 KSO3 H5 KSO3/PD3
31 KSO4 M4 KSO4/PD4 KBMX @
31 KSO5 K4 KSO5/PD5 10K_0402_5%
31 KSO6 KSO6/PD6

2
M5 TP303 FAN_DETEC T
31 KSO7 L5 KSO7/PD7
31 KSO8 KSO8/ACK#

1
K5
31 KSO9 M6 KSO9/BUSY R175
31 KSO10 H6 KSO10/PE C1 10K_0402_5%
KSI3/SLIN#

31 KSO11
KSI1/AFD#

KSO11/ERR# CK32KE
KSI0/STB#
KSI2/INIT#

M7 CLOCK B1 @
B 31 KSO12 K6 KSO12/SLCT CK32K B

VCO RE
31 KSO13 KSO13 Y4

2
AVSS
L7
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
KSI4
KSI5
KSI6
KSI7

31 KSO14 H7 KSO14 2 1
31 KSO15 KSO15 CLOSE PIN
2 2
32.768KH Z_12.5PF_CM8V-T1A
M8
L9
M9
L8
K9
M10
L10
K10

F5
F6
F7
G6
G7
H8

H12

VCORE_RF8
C387 C388
31 KSI0
10P_0402_50V8J 10P_0402_50V8J
31 KSI1 1 1
31 KSI2
31 KSI3
31 KSI4
C307
31 KSI5
31 KSI6 0.1u_0201_10V6K
31 KSI7
EC _AGND

J2
H_PR OCHOT# 43,6 1 2
1

JUMPER
R237 EC _AGND +3VALW_EC

7.5_0402_5%

Note 1 : Since all GPIO belong to VSTBY power domain, and


2

TP308

Q6A
6
there are some special considerations below:
H_PR OCHOT 2
(1) If it is output to external VCC derived power domain TP306
U7
1 6
MRDLY VCC
circuit, this signal should be isolated by a diode such as 2
3 GND RESET#
CD MR#
5
4
EC _WRST#
NBSWON #

1
R178
AO5804EL_SC 89-6
100K_0402_5%
1 KBRST# and GA20. C246 1 C347
@ G677L308A31U_ADFN6_1P5X1P5
0.1U_0402_25V6
(2) If it is input from external VCC derived power domain

2
0.22U_0402_10V6K
2
circuit, this external circuit must consider not to float
A the GPIO input. A

VOL_MUTE# 28

3 Note 2 :
Q6B

5
(1) Each input pin should be driven or pulled.
VOL_MUTE

(2) Each output-drain output pin should be pulled.


AO5804EL_SC 89-6
4

Security Classification LC Future Center Secret Data Title


Issued Date 2012/09/03 Deciphered Date 2012/09/03 IT8519
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Docum ent Num ber Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Cus tom
VENUS2 0.1

Date: Saturday, January 26, 2013 Sheet 34 of 46


5 4 3 2 1
5 4 3 2 1

+5VALW +5VALW

5
Q22 Q21

4 4
D D
FDMC8884_MLP-8-5 FDMC8884_MLP-8-5
@

1
2
3

1
2
3
+5VS
R219 2 @ 1 0_0402_5% +5V
36 SUSD 10,24,36 MAIND

C309 C311
+1.35V
0.1u_0201_10V6K 0.1u_0201_10V6K

5
+5VALW +5V Q27
PJ18

4
C
PJ_43x79_6 C
FDMC8884_MLP-8-5

1
2
3
2
+1.35V_CPU
R206 PJ13
0_0402_5%

PJ_43x79_6 C314

1
+3VALW +3VALW TP317 MAIND 0.1u_0201_10V6K
5

5
Q23 Q24

@
4 4

FDMC8884_MLP-8-5 FDMC8884_MLP-8-5

B B
1
2
3

1
2
3
+3VS
+3V

SUSD MAIND
C313
C312
0.1u_0201_10V6K
@ 0.1u_0201_10V6K

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2012/09/03 Deciphered Date 2012/09/03 Blank
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
VENUS2
Date: Saturday, January 26, 2013 Sheet 35 of 46
5 4 3 2 1
5 4 3 2 1

+5VLP +5V +3V +12VSB +5VLP +12VSB

1
R225 R241 R242 R234 R226 R238
100K_0402_5% 22_0402_5% 22_0402_5% @ 330K_0402_5% 100K_0402_5% 330K_0402_5%
@
@ @

2
SUSON# CAMERA_EN#
SUSD 35 CAMERA_END 27
6 3 6 3 6 3
Q7A Q8B Q8A Q7B 1 Q42A Q42B 1
D D
@ @ @ @ @
C391 C441
2 5 2 5 1000P_0201_25V7K 2 5 1000P_0201_25V7K
31,34,40 SUSON 2 34 CAMERA_EN 2

AO5804EL_SC89-6 AO5804EL_SC89-6 AO5804EL_SC89-6 AO5804EL_SC89-6 AO5804EL_SC89-6 AO5804EL_SC89-6


1 4 1 4 1 4

+5VLP +1.35V +5VLP +12VSB


1

1
R228 R243 R227 R239
100K_0402_5% 22_0402_5% 100K_0402_5% 330K_0402_5%
@ @
2

2
TP320 SLP_SUS TP322
SLP_SUSD# 20
6 3 6 3
C
Q9A Q9B Q36A Q36B 1 C

@ @ C439
SUSON 2 5 2 5 1000P_0201_25V7K
15,34 SLP_SUS# 2

AO5804EL_SC89-6 AO5804EL_SC89-6 AO5804EL_SC89-6 AO5804EL_SC89-6


1 4 1 4
TP321

+5VLP +5VS +3VS +1.35V_CPU +1.05VS +0.68VS VCCSA +12VSB


1

R229 R244 R245 R246 R247 R248 R249 R240


100K_0402_5% 22_0402_5% 22_0402_5% 22_0402_5% 22_0402_5% 22_0402_5% 22_0402_5% 330K_0402_5%

B TP325 TP326 TP327 TP328 @ @ B


2

TP324 MAINON#
MAIND 10,24,35
6 3 6 3 6 6 3 3
Q10A Q10B Q11A Q11B Q12A Q13A Q13B Q12B 1
@ @ C392
2 5 2 5 2 2 5 5 1000P_0201_25V7K
34,40,41,42 MAINON 2
TP323
AO5804EL_SC89-6 AO5804EL_SC89-6 AO5804EL_SC89-6 AO5804EL_SC89-6 AO5804EL_SC89-6 AO5804EL_SC89-6 AO5804EL_SC89-6 AO5804EL_SC89-6
1 4 1 4 1 1 4 4

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2012/09/03 Deciphered Date 2012/09/03 CPU (1/7) DMI, FDI, PEG
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
VENUS2
Date: Saturday, January 26, 2013 Sheet 36 of 46
5 4 3 2 1
5 4 3 2 1

+3VLP/ 100mA
B+ Silergy
SY8208BQNC
D
AC Adapter Converter +3VALW/ 4A D

20V / 45W EC_ON EN FOR SYSTEM PGOOD ALW_PWRGD


PAGE 39
+3V Anpec
APL5932AQBI-TRG +1_5VS/200mA
+5VLP/ 100mA
Silergy MAINON EN LDO
PAGE 41 PGOOD
SY8208CQNC +5VALW/5A
Converter
EC_ON EN FOR SYSTEM PGOOD ALW_PWRGD
PAGE 39

+5VALW Silergy
VCCSA/3A
SY8037DDCC
MAINON EN Converter
PAGE 42 PGOOD

C TI C

BQ24735RGRR TI
Battery Charger TPS51362RVER +1.35V/5A
Switch Mode Converter
IO Board / Page7
+1.35V TI
FOR DDR3L TPS51206DSQR +0.68V/1A
SUSON EN PGOOD SUSON S5
PAGE 40 1.35VSUS_PWRGD
MAINON S3 LDO
PAGE 40

SMBus
TI
TPS51362RVER +1.05VS/8A
Converter
MAINON EN FOR CPU/PCH PGOOD 1.05VS_PWRGD
PAGE 41

B B
Battery INTERSIL
Li-ion ISL95831HRTZ CPU_CORE / 11A
4S1P / 42.7W Switch Mode
FOR CPU IMVP7
IMVP_VR_ON EN PGOOD IMVP_VR_CPU_OK
PAGE 43

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/09/03 Deciphered Date 2012/09/03 PWR_BLOCK DIAGRAM


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
VENUS2 0.1

Date: Saturday, January 26, 2013 Sheet 37 of 46


5 4 3 2 1
5 4 3 2 1

D D

BATT+ BATT+_1 BATT+_2


JBATT1
PL1 PF1
1
3.5A SMB3025500YA_2P
2 1
7A_32V_0437007.WR
1 2 2 1
EC_SMCA 3 2
EC_SMDA 4 3 PQ1
5 4 TP0610K-T1-E3_SOT23-3
6 5 PJ1

MBAT_PRES#_R
6

1
PC1 PC2 7 BATT+_2 JUMP_43X39
8 7 3 1 +12VSBP 1 2
GND_1 PTP24 PTP23 PTP1 B+ 1 2 +12VSB
9
1000P_0402_50V7K

1000P_0402_50V7K
GND_2

0.22U_0603_25V7K
2

2
PR1 PR2

1
1

2
PC3
ACES_50299-00701-001 PR5
100K_0402_1% PC4

100_0402_1%

100_0402_1%
0.1U_0603_25V7K

1
2

2
+3VLP PR6
22K_0402_1%
PTP25 1 2 VSB_ON_3

VSB_ON_2
@
PR7
PTP32
100K_0402_5%
TESTPAD
27,34 EC_SMB_CLK
PTP16

1
PR8 PQ2

1
1K_0402_1% D
27,34 EC_SMB_DAT 1 2 VSB_ON_1 2 2N7002KW_SOT323-3
+3VLP 39 ALW_PWRGD
TESTPAD Place in BOT side for Production Line Test G

1U_0402_6.3V6K
@ PR9 1 S
TP41

3
1K_0402_1%
1

1 2

PC5
PR3
100K_0402_5% 2
R_0402 TESTPAD
PR4 PTP29
PTP17
2

C 0_0402_5% C
1 2
34 MBAT_PRES#

TESTPAD

Place in TOP side for Production Line Test

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/09/03 Deciphered Date 2012/09/03 PWR_BATTERY CONN


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
A2
VENUS2 0.1

Date: Saturday, January 26, 2013 Sheet 38 of 46


5 4 3 2 1
5 4 3 2 1

D D

12/24 Add PR19 for PU1 version updated


B+ NC PR11,PR14 for PU1 version updated
PU1
PJ2

1
JUMP_43X39
2 1.5A +3V_VIN 7 2 +3V_PWRGD
1 2 EN2 PG

SY8208BQNC_QFN10_3X3
1

1
+3VALW

10U_0805_25V6K

1M_0402_5%
0.1U_0402_25V6
@ PR14
@PR14 PC8

PC6

PC7

2
8 6 +3VBS 1 2

PR19
IN BS

0_0402_5%
12/27 Delete PC11 for PL2 Placement
PJ3 4A

2
PTP33 0.1U_0603_25V7-M PL2

2
9 10 +3VLX 1 2 +3VALW_P
PR33 GND LX

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
0_0402_5% 3V_GND 2.2UH_PCMB051H-2R2MS_5A_20%

1
1 2 +3VALW_EN 1 4 +3VALW_P PJ_43x79_6
34 AUXON EN1 OUT

PC9

PC10

PC12

PC13

PC14
TESTPAD
100mA +3VLP @ PR10

2
+3VALW_FB 3 5 4.7_0603_5%
FB LDO

1 2
1

4.7U_0603_6.3V6K

@
1M_0402_5% @ PR11
@PR11 PC17
@ PC43 @ 680P_0402_50V7K

1M_0402_5%
0.1U_0402_25V6
PR12

PC15
2

2
2

2
3V_GND
3V_GND 3V_GND 3V_GND

PR17
PC127
1K_0402_1%
1 2 1 2

J5
1 2 470P_0402_50V7K

JUMPER

12/24 Add PC127/PR17 for PU1 version updated


C C
3V_GND

+3VALW

2
PR16
100K_0402_5%
PR31
0_0402_5%

1
+3V_PWRGD 1 2
ALW_PWRGD 38
12/24 NC PR22,PR47 for PU2 version updated
B+ PU2 PR32
PJ4
2.5A +5V_VIN 8 2 +5V_PWRGD
0_0402_5%
1 2
IN PG
SY8208CQNC_QFN10_3X3

+5VALW
1

10U_0805_25V6K
0.1U_0402_25V6
PC19

PC20

@ PR22 PC21 Change PL3 from SH00000SM00 to SH00000T300 for SIV PBCR
2

PJ_43x79_6 9 6 +5VBS 1 2
GND BS
0_0402_5%

PJ5 5A PTP5
2

PC28 0.1U_0603_25V7-M PL3


1 2+5VVCC 5 10 +5VLX 1 2 +5VALW_P
PR30 VCC LX
1

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
0_0402_5% 1U_0603_10V6K 3.3UH_PCMB062D-3R3MS_5.5A_20%
TESTPAD

1
AUXON 1 2 5V_GND +5VALW_EN 1 4 +5VALW_P PJ_43x79_6
EN OUT

PC22

PC23

PC24

PC25

PC26

PC27
100mA +5VLP @ PR18

2
+5VFB 3 7 4.7_0603_5%
FB LDO
1 2
1

4.7U_0603_6.3V6K

@
@ PR47 PC30
B B
1

1M_0402_5%

1M_0402_5%

@ 680P_0402_50V7K
PR20

PC29

@ PC120
2

0.1U_0402_25V6
PTP7
2

TESTPAD
5V_GND

5V_GND 5V_GND 5V_GND

PR23
PC16 1K_0402_1%
1 2 1 2

0.033U_0402_16V7-K
J6
1 2

JUMPER
12/24 Add PC16/PR23 for PU2 version updated

5V_GND

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/09/03 Deciphered Date 2012/09/03 PWR_BATTERY CONN


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
VENUS2 0.1

Date: Saturday, January 26, 2013 Sheet 39 of 46


5 4 3 2 1
5 4 3 2 1

+5VALW

@ PR39
2 1
0_0402_5%
12/25 Delete PR40 0 ohm

12/25 Delete PR46 0 ohm


1.35V_GND
PC36

1
1.35V_GND PC35
1 2 B+

5600P_0402_25V7-K
+1.35V_P

2
D 0.1U_0402_25V6 D
PJ16
12/24 Add PR44 from 270K to 287K to increase Vout for device side
1.35V_VIN
1A 1
JUMP_43X39
2
1 2

1.35V_SLEW
1
PR44

1
1.35V_GND 287K_0402_1% PC37 PC38 PC39

C_0402
0.1U_0402_25V6

C_0805
10U_0805_25V6K

C_0805
10U_0805_25V6K
23

22

21

20

19

18

17

16

15
2

2
SLEW

V5
GND1

VIN3

VIN2

VIN1
GSNS

VSNS

TRIP
1
PR43 24 14
130K_0402_1% REFIN2 PGND1
1.35V_REFIN25 13
REFIN PU3 PGND2

2
1.35V_VREF 26 12
VREF TPS51362RVER_QFN28_3P5X4P5 PGND3
27 11
RA PGND4

1
PC42
1.35V_EN 28 10
EN PGND5

0.1U_0402_25V6

PGOOD
PTP19

2
29

MODE
C_0402

SW1

SW2

SW3

SW4
GND2

BST
TESTPAD

LP#

NC
1.35V_GND
+1.35V

1.35V_PGOOD1

9
PR38
1 2

1 1.35V_BST
2 1.35V_LP#
31,34,36 SUSON PL4 PJ7

1.35V_SW
0_0402_5% 1 2 +1.35V_P
5A

1
R_0402
@ PC41 0.33UH_PCMB062D-R33MS_18A_20% 1 1 1 1 1 1 PJ_43x79_6
C C

1
0.1U_0402_25V6 PC44 PC45 PC46 PC47 PC55 @ PC40 PC48

2
+3VALW @ PR54 PR56

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

0.1U_0402_25V6
0_0402_5% 5.1_0603_5% @ PR13

2
1.35V_GND 4.7_0603_5% 2 2 2 2 2 2
1

1 2
PR42
100K_0402_5% PC18
R_0402 @ 680P_0402_50V7K
PC135
2

2
1 2
34 1.35VSUS_PWRGD
0.1U_0402_25V6
1.35V_GND C_0402
12/24 NC PR54 for SIV PBCR

J1
1 2

JUMPER

1.35V_GND

B B
+1.35V
+0.68VS
PU4

PJ8 PJ14
PTP9
1
JUMP_43X39
2 1A 0.68V_VIN 1 3 0.68V_P
1A 1
JUMP_43X39
2
PTP20 1 2 VDDQSNS VTT 1 2
1

TESTPAD PD4
TESTPAD

1
1 2 PC49 2 5
10U_0603_6.3V6M VLDOIN VTTSNS PC51
PR48 PTP21
2

SDM10U45LP-7_DFN1006-2-2 10U_0603_6.3V6M

2
1 2 1 2 0.68V_S3 7 4 TESTPAD
34,36,41,42 MAINON S3 PGND
PR49 10K_0402_5%
1K_0402_5%
SUSON 1 PR50 2 0.68V_S5 9 6
S5 VTTREF +0.68V
+5VALW
0_0402_5%
POWERPAD

10 8
VDD GND
1

PC53 PC54 PC52


1

PC50 1U_0402_10V6K
2
C_0402
0.1U_0402_25V6

C_0402
0.1U_0402_25V6
2

C_0402
0.1U_0402_25V6
2

11

TPS51206DSQR_SON10_2X2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/09/03 Deciphered Date 2012/09/03 PWR_1.35V/0.68VS


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
VENUS2 0.1

Date: Saturday, January 26, 2013 Sheet 40 of 46


5 4 3 2 1
5 4 3 2 1

+5VALW

@ PR41 12/25 Delete PR45 0 ohm

+1.05VS_P
2 1
0_0402_5%

1
@ PR57
D 1.05V_GND D
10_0402_5%
PC126

1
1.05V_GND PC125

2
PR58 1 2 B+
1 2

5600P_0402_25V7-K
9 VCCP_SENSE 1.05V_VSNS

2
0.1U_0402_25V6
0_0402_5% R_0402

1.05V_SLEW
PJ9

1
PR59
2 1.05V_GSNS 1.05V_VIN
1A 1
JUMP_43X39
2
9 VSSP_SENSE 1 2
0_0402_5% R_0402

1
PC56 PC57 PC58
@ PR60

C_0402
0.1U_0402_25V6

C_0805
10U_0805_25V6K

C_0805
10U_0805_25V6K
23

22

21

20

19

18

17

16

15

2
10_0402_5%

SLEW

V5
GND1

VIN3

VIN2

VIN1
GSNS

VSNS

TRIP
2
24 14
1.05V_GND REFIN2 PGND1
25 13
1.05V_GND REFIN PU5 PGND2
1.05V_VREF 26 12
VREF TPS51362RVER_QFN28_3P5X4P5 PGND3
27 11

0.1U_0402_25V6
RA PGND4

1
PC68
1.05V_EN 28 10
EN PGND5

PGOOD
2
29

MODE

SW1

SW2

SW3

SW4
GND2

BST
LP#

NC
1.05V_GND +1.05VS

1.05V_PGOOD 1

9
PR53 PL5
C C
1 2 0.33UH_PCMB062D-R33MS_18A_20%
34,36,40,42 MAINON PJ10 PTP10
8A

1.05V_BST
1.05V_LP#

1.05V_SW
0_0402_5% 1 2 +1.05VS_P

1
R_0402 @
PC67 1 1 1 1 1 1 PJ_43x79_6
TESTPAD

1
0.1U_0402_25V6 PC62 PC63 PC64 PC65 PC59 PC60 PC66

2
+3VS

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

0.1U_0402_25V6
@ @ PR15

2
4.7_0603_5% 2 2 2 2 2 2

C_0402
1.05V_GND PR55
1

0_0402_5%

1 2
@PR52
@ PR52 PR51
100K_0402_5% 5.1_0603_5% PC31

2
R_0402 @ 680P_0402_50V7K
PC61
2

2
1 2
42 +1.05VS_PWRGD
1.05V_GND 0.1U_0402_25V6
C_0402
12/24 NC PR52 12/24 NC PR55 for SIV PBCR

J4
1 2

JUMPER

1.05V_GND

B B

+5VALW

+1.5VS
+3VALW
1

PC83 PU6 12/25 Delete PR62 0 ohm


1U_0402_10V6K APL5932AQBI-TRG_TDFN10_3X3
2

12/25 Delete PR117 0 ohm

10 1
300mA
300mA VCNTL VOUT1
9 2 1
VIN3 VOUT2
1

1
8 3 PR61
PC69 VIN2 VOUT3 21.5K_0402_1% PC70
1U_0402_10V6K 7 4 10U_0603_6.3V6M
VIN1 FB
2

2
PR63
MAINON 1 2 6 5
EN/ENB POK
1
GND

0_0402_5% PR120
1

24K_0402_1%
PC72 @ PR21
11

0.1U_0402_25V6 100K_0402_5%
2

R_0402
2

+3VS
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/09/03 Deciphered Date 2012/09/03 PWR_1.05VS/1.5VS


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
VENUS2 0.1

Date: Saturday, January 26, 2013 Sheet 41 of 46


5 4 3 2 1
5 4 3 2 1

+5VALW 12/25 NC PC73

D
PJ11
JUMP_43X39 0.5A D
1 2 VCCSA_VIN
1 2

1
VCCSA
PR119 VCCSA_P

1
@ PC73 PC74 PC71
10_0402_5%
PU7

22U_0805_6.3V6M

22U_0805_6.3V6M

0.1U_0402_25V6
2

2
VCCSA_SVIN
PL6 PJ12 PTP12
12/25 NC PC75
3A

2
12 1 VCCSA_LX 1 2 VCCSA_P

SY8037DDCC_DFN12_3X3
PC81 PVIN2 LX1

1
1U_0603_10V6K 11 2 2.2UH_PCMB051H-2R2MS_5A_20% PJ_43x79_6
PVIN1 LX2 TESTPAD

1
10 3 @ PR67
SVIN LX3

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
PR66 VCCSA_GND 4.7_0603_5%

1
0_0402_5%

1 2

1
1 2 VCCSA_EN 5 8

PC75

PC76

PC77

PC78
34,36,40,41 MAINON EN VOUT PC82 PR69

2
PC80 68P_0402_50V8J @ 680P_0402_50V7K

2
6 9 1 2

100_0402_1%
VCCSA_FB @
VID0 FB

2
@PR64
@ PR64

2
1
PR68 @ @ PC79 7 4 VCCSA_PG 1 2

GND
VID1 PG +3VS
47K_0402_5% 0.1U_0402_25V6
100K_0402_5%

13
12/24 NC PR64

VCCSA_GND VCCSA_GND VCCSA_SENSE 10


12/25 Delete PR104,PR106 0 ohm

10 VCCSA_VID0
12/25 Delete PR114 0 ohm
10 VCCSA_VID1

J8
1 2
2

2
C PR65 PR70 JUMPER C
1K_0402_5% 1K_0402_5%
1

VCCSA_GND

VCCSA_GND VCCSA_GND

+3VS
2

PR88
100K_0402_5%
1

PR34
0_0402_5%
41 +1.05VS_PWRGD 1 2
ALL_SYS_PWRGD 34,6

PR35
VCCSA_PG 1 2

0_0402_5%
B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/09/03 Deciphered Date 2012/09/03 PWR_VCCSA


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
VENUS2 0.1

Date: Saturday, January 26, 2013 Sheet 42 of 46


5 4 3 2 1
5 4 3 2 1

B+

2A PJ17
PJ_43x79_6

GFX_VIN 1

1
+ PC86 PC89 PC90 PC87

33U_D2_25VM_R60M

10U_0805_25V6K

1U_0603_25V7K

0.1U_0402_25V6
2

2
2

1
PC85 0.1U_0402_25V6

1
PR71 1 2 NTCG
8.06K_0402_1% PC84

ISL95831_GND
1000P_0402_50V7K @PR72
@ PR72 @ PR73
@PR73

2
3.83K_0402_1% 470K_0402_1%
D D

5
1 2 1 2 PQ8
PC88 330P_0402_50V8J
1 2

FDMC7692_MLP-8-5
@ PR74
PC91 27.4K_0402_1%
PR76 PC92 VCC_AXG_SENSE 10 1 2
ISL95831_GND
68P_0402_50V8J 226_0402_1% 1200P_0402_50V7-K 4
1 2 1 2 1 2 1 2 VSS_AXG_SENSE 10
GFX_CORE
PC93 1000P_0402_50V7K PL7 15A PTP13
PR77 PR78 0.33UH_PCMB062D-R33MS_18A_20%
PC94

3
2
1
453K_0402_1% 1.2K_0402_1% GFX_PH 1 2
1 2 1 2 1 2
PC95

1
ISL95831_GND PR79 2_0402_5% PQ6 TESTPAD
120P_0402_50V8-J 1 2 1 2 PR82
@PR82
@ 1 1

1
FDMS0306AS_POWER56-8-5
2.2_0603_5% PC99
1

0.22U_0603_25V7K + PC97 + PC98


1

0.1U_0402_10V7K
PR80

2
4

330U_D1_2VM_R6M

330U_B2_2VM_R15M
7.5K_0402_1% PC96 PR81
0.047U_0402_25V7K 2 2
11.5K_0402_1%
2

1
2

@PC100
@ PC100

1
0.47U_0402_25V6K

3
2
1

2
ISL95831_GND
ISL95831_GND

GFX_COMP
GFX_VW
GFX_IMON
PR83

GFX_BOOT
GFX_FB
ISPG 1 2

GFX_HG

GFX_LG
GFX_PH
PROG2

1
NTCG
9 VR_SVID_DATA

ISNG
ISPG
PR84 PR85
3K_0402_1%

1
2K_0402_1%
9 VR_SVID_ALERT#

4.02K_0402_1%
PC101

1 2
+1.05VS +1.05VS +3VS

0.1U_0402_25V6
49

48

47

46

45

44

43

42

41

40

39

38

37
9 VR_SVID_CLK

2
PH2

VSENG

PHG
COMPG

FBG

ISNG
GND

RTNG

NTCG

PROG2
ISPG

BOOTG

UGG
PR89

LGG
1

34 IMVP_VR_ON
10K_0402_1%_TSM0A103F34D1RZ B+
PR118 PR86 PR87 1 36 ISNG 1 2
VWG BOOT2

1 2
1.91K_0402_1%

2 35
54.9_0402_1%

130_0402_1%

C PC102 C
IMONG UG2 1.37K_0402_1%
2

0.1U_0402_10V7K
GFX_PWRGD 3 34
PGOODG PH2

2
+5VS PJ15
34 CPU_IMON 4 33
PC103 SDA VSSP2
ISL95831_GND 1.5A PJ_43x79_6
1

5 32 CPU_VIN 1
ALERT# LG2
0.047U_0402_25V7K

PR90 PU8

1
7.5K_0402_1% PR93 6 31 PQ9 + PC107 PC104 PC105 PC106
SCLK VDDP
2

33U_D2_25VM_R60M

10U_0805_25V6K
ISL95831_GND

PTP22 0_0402_5% PR92 100K_0402_5%

1U_0603_25V7K

0.1U_0402_25V6
1 2 7 30 1 2

FDMC7692_MLP-8-5
VR_ON ISL95831CRZ-T_TQFN48_6X6 PWM3
VR_ON PWM3
2

2
PC108 2
1 PR91 CPU_PGOOD 2 8 29 CPU_LG 1U_0402_10V6K
+3VS PGOOD LG1

2
1.91K_0402_1% 4
9
IMON VSSP1
28 CPU_CORE
PR94 0_0402_5% PL8
1 2 VRHOT# 10 27
34,6 H_PROCHOT# PC109 0.1U_0402_25V6 VR_HOT# PH1
CPU_PH
0.33UH_PCMB062D-R33MS_18A_20% 12A PTP14

3
2
1
1 2 NTC 11 26 CPU_UG CPU_PH 1 2
NTC UG1
ISEN3/ FB2

PR95 PC110
ISL95831_GND
1

5
@ VW 12 25 CPU_BOOT 1 2 1 2 PQ7

PROG1
PR96

ISUMN
VW BOOT1

ISUMP
TESTPAD

1
COMP

ISEN2

ISEN1

VSEN
PC111 @PR98
@ PR98 470K_0402_5% 2_0402_5%

VDD
1 2 1 2 RTN

VIN

FDMS0306AS_POWER56-8-5
47P_0402_50V8J 0.22U_0603_25V7K @PR97
@ PR97
FB
2

2.2_0603_5%
3.83K_0402_1%
COMP 13

14

15

16

17

18

19

20

21

22

23

24
@PR99
@ PR99 27.4K_0402_1% 4

1 2
1 2

PROG1
FB

VSUM+

VDD
ISEN2

VIN
ISUM-

@PC112
@ PC112
0.47U_0402_25V6K

3
2
1

2
1
1

PR102 PR100
1

1 2 0_0402_5%
B+
PR101 PC113
8.06K_0402_1% 1000P_0402_50V7K
0_0402_5%
2

2
2

PR103 1_0402_5%
1 2
+5VS
B ISL95831_GND B
1

PC114 @
PC115
1U_0402_10V6K

0.22U_0603_25V7K
2

PR105 PC117
PC116 +5VS PR107 ISL95831_GND ISL95831_GND PR109 3K_0402_1%
1 2 1 2 1 2 1 2 1 2
100K_0402_1%
1

150P_0402_50V8-J 255_0402_1% 1000P_0402_50V7K


PR108
PC119 2K_0402_1%
PR112 PR113
1

PC118 PR111 1K_0402_1%


2

1 2 1 2 1 2
0.1U_0402_25V6

4.02K_0402_1%
2

120P_0402_50V8-J 453K_0402_1%
PH1
2

12/24 Change PC116 from 68pF to 150pF for CPU_CORE shutdown issue.
10K_0402_1%_TSM0A103F34D1RZ
PR115
2

PC121 330P_0402_50V8J 2 1
1 2
1.74K_0402_1%
ISL95831_GND

PC123
9 VCC_SENSE
PR116 0.1U_0402_10V7K
1 2 1 2
9 VSS_SENSE
2

1 2 PC122 100_0402_1%
3300P_0402_50V7-K ISL95831_GND
PC124 1000P_0402_50V7K

A J3 A
1 2

JUMPER

ISL95831_GND

Security Classification LC Future Center Secret Data Title

Issued Date 2012/09/03 Deciphered Date 2012/09/03 PWR_CPU_CORE/GFX_CORE


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
VENUS2 0.1

Date: Saturday, January 26, 2013 Sheet 43 of 46


5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/09/03 Deciphered Date 2012/09/03 CPU (1/7) DMI, FDI, PEG
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
VENUS2 0.1

Date: Saturday, January 26, 2013 Sheet 44 of 46


5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/09/03 Deciphered Date 2012/09/03 CPU (1/7) DMI, FDI, PEG
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
VENUS2 0.1

Date: Saturday, January 26, 2013 Sheet 45 of 46


5 4 3 2 1
5 4 3 2 1

SIV Change List


1. change Touchpad SMBUS link to SMBCLK&SMBDAT in PCH. P14
2. add uart debug connector in P35.
delete CLK_REF14_SIO on p14,PCH_DRQ#0 on P13,CLK_PCI_SIO on P17,CLK_PCI_LPC_DEBUG on P17.
3. add uart debug connector in P35.
D D
add UART TX on UE1.A8,UART RX on UE1.B8, move FAN_DETECT,DRAMRST_CNTRL_EC to UE1.B7. modify FAN_DETECT pull high to +3VLAW if use DRAMRST_CNTRL_EC in future
4. reserve C138 for +3V_WLAN, it maybe filter the power noise for WIFI module
5. add R185,R182 for WIFI USB, if USB SI is OK, which can help to save the cost
6. add UART debug in SSD connnector
7. the following items are for save thermal sensor cost:
remove GPA2, WIN8_BUTTON_LED#
remove GPC4, OS_SWITCH#
remove GPG2, NFC_EN. GPG0, I2C_INT_NFC#
change GPA0_VOL_MUTE to GPC4
change GPD7_USB_ONto GPA2
add EC_FAN_PWM_GPA0, EC_FAN_SPEED_GPD7 to save thermal sensor cost

8. the following change items are for eDP panel:


C remove the LVDS interface ; C
add the eDP interface in P05;
add the CFG[4] pull down 1k resistor to enable the eDP;
change the VCCPLL power rail from +1.8vs to +1.35_CPU;
remove the power rail for VCCTX_LVDS in P19, and connected to GND;
9. add VCCSA_VID[0,1], VCCSA_sense in Page10
10. spearate the VREF_DQ,VREF_CA in P12, according to Intel's suggestion
11. remove the D22,add 0hom for AC_PRSENT, because no leakage current
12. to save the cost, change EMC2104 to EMC1403
13. change C183 Value from 0.1uf to 4.7uf to power stable
14. Change USB3.0 Port, OC changed to OC#1 since SUB2.0 Port changed to USB2.0 Port3
15. reserve R219,R217 to save the 5v,3v Switch MOSFET
16. reserve VREF_DQ,VREF_CA divider network for SO-DIMM(M3)
B B
17.add DPWROK pull down 10k acccording to schematic checklist

SIT Change List


1.replace 0ohm to R-Short to cost down
2.change R51 from 100ohm to 33ohm,and add 47pf on the trace of DMIC_CLK to lower the MIC record noise
3.remove reserved 5vs for touchpanel, and remove reserved 3vs power switch for touchpanel
4.replace the 0ohm to common choke for USB2.0 Port
5.replace the 0ohm to common choke for HDMI Port
6.add fuse for HDMI 5v power to satify the saft test requirement
7.combine some mosfet in discharge schematic for cost down
8.remove 5v,3v discharge
A
9.remove the win8_button# pull up to +3vs in I/O board A

10.remove mic in power board and rotation board, and add one connector in power board for mic module solution
11.remove reserved PECI to PCH Security Classification LC Future Center Secret Data Title
12.change J9 to R_Short for layout Issued Date 2012/09/03 Deciphered Date 2012/09/03 HW change list
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
SIT2 Change List 1.Add the test point 2. change the F1 size from 0402 to 0805 Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
VENUS2
Date: Saturday, January 26, 2013 Sheet 46 of 46
5 4 3 2 1

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