A B C D E

Model Name : A5WAM

File Name : LA-B981P

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m
Compal Confidential
.co
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fixEA51_BM DIS M/B Schematics Document
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se
.ro

Intel Bay Trail M + N15V-GL/N15V-GM

w
w

2014-05-12
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REV:0.1
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4 4

PCB@
DAX PCB 15Y LA-B981P REV0 MB 2
Part Number Description
DA60019D000 PCB 15Y LA-B981P REV0 MB 2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/03/19 Deciphered Date 2015/03/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A5WAM_Bay Trail M_LA‐B981P
Date: Monday, May 12, 2014 Sheet 1 of 47
A B C D E
 A B C D E

HDMI Conn. eDP Conn.

Nvidia N15V-GL
with DDR3 x4
1
page 15~21 204pin DDR3L-SO-DIMM X1 1

P.13
P.23 P.22 PCIe 2.0 x 2
5GT/s
port 0 port 1
port 0/1
Memory BUS 204pin DDR3L-SO-DIMM X1
Dual Channel P.14
1.35V DDR3L 1066/1333

CRT Conn. DDI x2

VGA x1
USB2.0 x4 port 0 port 1 port 2 port 3
P.24
PCIE 2.0 x1
VALLEYVIEW-M USB3.0 x1 USB HUB Touch Panel
HD Camera
port 3 Conn.
2 RJ45 Conn. GL850G Conn. P.22 2

P.28 P.22
LAN(GbE) / Card Reader USB 3.0
RTL8411B P.25,26
SOC Conn P.28 HUB port1

PCIE 2.0 x1
MINI CARD
FCBGA 1170 Pin port 2
WLAN/BT
P.26

Card Reader
2 in 1(SD)
SATA 2.0 x2 HD Audio HDA Codec
page 05~12 ALC283
P.27 port 1 P.27 port 0 P.31
LPC BUS SPI

3 3

SPI ROM Speaker Combo Jack Int. MIC

SATA ODD Conn. EC 1.8V (8MB) P.31 P.31 P.31
ENE KB9022 P.08
RTC CKT.
P.29
P.08
SATA HDD Conn.
P.30 P.30
DC/DC Interface CKT.
P.32
Sub Board
Power Circuit DC/DC LS_B161P PWR Touch Pad Int.KBD
P.33~P.44 PS2/I2C

4 LED/Power On/Off LS_B162P USB

HUB port2,3
4

P.30

Fan Control Security Classification Compal Secret Data Compal Electronics, Inc.
2014/03/19 2015/03/18 Title
P.27
Issued Date Deciphered Date Block Diagrams
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A5WAM_Bay Trail M_LA‐B981P
Date: Monday, May 12, 2014 Sheet 2 of 47
A B C D E
 A B C D E

Voltage Rails Board ID / SKU ID Table for AD channel

Power Plane Description S0 S3 S4/S5
VIN 19V Adapter power supply ON ON ON
BATT+ 12V Battery power supply ON ON ON
B+ AC or battery power rail for power circuit. (19V/12V) ON ON ON
+RTCVCC RTC Battery Power ON ON ON
BOARD ID Table_LA-B212
1
+1.0VALW +1.0v Always power rail ON ON ON 1

+1.8VALW +1.8v Always power rail ON ON ON Board ID PCB Revision

+3VALW +3.3v Always power rail ON ON ON 10 EVT_LA-B212PR01
+5VALW +5.0v Always power rail ON ON ON 11 PVT_LA-B981PR01
+1.35V +1.35V power rail for DDR3L ON ON OFF
+3V_PTP +3.3V power rail for PTP ON ON OFF
+SOC_VCC Core voltage for SOC ON OFF OFF
+SOC_VNN GFX voltage for SOC ON OFF OFF
+0.675VS +0.675V power rail for DDR3L Terminator ON OFF OFF
+1.0VS +1.0v system power rail ON OFF OFF
+1.05VS +1.05v system power rail ON OFF OFF
+1.35VS +1.35v system power rail ON OFF OFF
+1.5VS +1.5v system power rail ON OFF OFF
+1.8VS +1.8v system power rail ON OFF OFF
43 level BOM table
+3VS +3.3v system power rail ON OFF OFF
+5VS +5.0v system power rail ON OFF OFF 43 Level Description BOM Structure
2
+3VSDGPU +3.3V dGPU power rail ON** OFF OFF 4319URBOL01 SMT MB AB212 A5WAM GM2G N3530 HDMI N3530@/9022@/DBG@/EMC@/PCB@/1DMIC@/NTPM@/VGA@/VGM@/X762G@ 2

+VGA_CORE Core voltage for dGPU ON** OFF OFF 4319URBOL02 SMT MB AB212 A5WAM GL1G N2930 HDMI N2930@/9022@/DBG@/EMC@/PCB@/1DMIC@/NTPM@/VGA@/VGL@/X761G@
+1.5VSDGPU +1.5V dGPU power rail ON** OFF OFF 4319URBOL03 SMT MB AB212 A5WAM GL1G N2830 HDMI N2830@/9022@/DBG@/EMC@/PCB@/1DMIC@/NTPM@/VGA@/VGL@/X761G@
+1.05VSDGPU +1.05V dGPU power rail ON** OFF OFF 4319URBOL04 SMT MB AB212 A5WAM GL1G N3530 HDMI N3530@/9022@/DBG@/EMC@/PCB@/1DMIC@/NTPM@/VGA@/VGM@/X761G@
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF. 4319URBOL05 SMT MB AB212 A5WAM GM2G N2930 HDMI N2930@/9022@/DBG@/EMC@/PCB@/1DMIC@/NTPM@/VGA@/VGL@/X762G@
Note : ON** dGPU optimus on 4319URBOL06 SMT MB AB212 A5WAM GM2G N2830 HDMI N2830@/9022@/DBG@/EMC@/PCB@/1DMIC@/NTPM@/VGA@/VGL@/X762G@

BOM Option Table BOM Option Table

Item BOM Structure Item BOM Structure
2.2K Unpop @ X76 1G VRAM X761G@
Connector CONN@ X76 2G VRAM X762G@
2.2K
+1.8VS EMC requirement EMC@ 1GHYN@
BH10
EMC requirement depop @EMC@ 1GFFR@
PCU_SMB_CLK
BSS138 KB9012 9012@ 1GSAM@
BG12 PCU_SMB_DATA
SOC BSS138 KB9022 9022@ 2GAFR@
Touch Screen I2C TSI@ 2GSAM@
3 KB BL BL@ 2GMIC@ 3

2.2K
DMIC*1 1DMIC@
DMIC*2 2DMIC@
2.2K
+3VALW TPM TPM@
NTPM NTPM@
77 EC_SMB_CK1 100 ohm 7
SCL1 BATTERY Debug SW DBG@
78 100 ohm
SDA1
EC_SMB_DA1 6
CONN dGPU VGA@
2.2K
N15V‐GL  SKU VGL@ 2.2K 2.2K
N15V‐GM SKU VGM@
2.2K +3VS Charger +1.8VS 2.2K +3V_PTP
2.2K
KBC SCL2 79 EC_SMB_CK2 BG25 SOC_I2C2_DATA
BSS138
I2C2_SDA_TP

BJ25 SOC_I2C2_CLK Touch Pad

SDA2 80 EC_SMB_DA2 I2C2_SCL_TP
BSS138
200
2.2K 2.2K
202 SMBUS Address [A0h]
KB9022 DIMMA
SOC
200 2.2K
+1.8VS 2.2K +TS_PWR
4 202 SMBUS Address [A2h] BH28 SOC_I2C5_DATA I2C5_SDA_PNL
4
DIMMB
2.2K BSS138
30 BG28 SOC_I2C5_CLK Touch Panel
I2C5_SCL_PNL
BSS138
32 2.2K +3VSDGPU_AON
WLAN
Security Classification Compal Secret Data Compal Electronics, Inc.
I2CS_SCL 2014/03/19 2015/03/18 Title
2N7002DW I2CS_SDA VGA
Issued Date Deciphered Date Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A5WAM_Bay Trail M_LA‐B981P
Date: Monday, May 12, 2014 Sheet 3 of 47
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 A B C D E

12000mA
+SOC_VNN
VR_ON ISL95833HRTZ-T
(PU801) 14000mA
+SOC_VCC

1
SPOK SY8208DQNC 325mA SUSP ME4856-G 2750mA 1

(PU601) +1.0VALWP +1.0VS

(U60)

ADAPTER
SYSON RT8207MZQW 5250mA SUSP#
(PU501) +1.35VP +0.675VSP

SUSP# TPS22966DPUR 420mA

+1.35VS
(U59)
CHARGER B+
EC_ON SY8208BQNC SUSP# SY8003DFC_DFN8 958mA
(PU401) +3VALWP +1.5VSP
(PU602)
SUSP# APL5930KAI-TRG 1000mA VGA_PWROK AO4478L
+1.05VSP +1.05VS +1.05VSDGPU
(PU701) (U40)
SPOK APL5930KAI-TRG 110mA TPS22966DPUR
BATTERY +1.8VALWP +1.8VS
2 (PU702) (U59) 2

SUSP# TPS22966DPUR JP8

+3VS +3VS_WLAN
(U11)
ENVDD G5243AT11U
+LCDVDD
LAN_PWR_EN
(U8)
G5243AT11U
+3V_LAN
(U67) DGPU_PWR_EN G5243T11U
+3VSDGPU_AON
(U12)

EC_ON SY8208BQNC SUSP# TPS22966DPUR 958mA J1

+5VALWP +5VS +VDDA
(PU402) (U11)

0 ohm
+5VS_HDD
3 3
0 ohm
+5VS_ODD

USB_PWR_EN# SY6288D10CAC
+USB3_VCCA
(U25)
DGPU_PWR_EN

RT8813AGQW
+VGA_CORE
(PU1201)

VGA_PWROK
TPS51212DSCR
+1.5VSDGPU
(PU1001)

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

2014/03/19 2015/03/18 Title
Issued Date Deciphered Date Power Rail
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A5WAM_Bay Trail M_LA‐B981P
Date: Monday, May 12, 2014 Sheet 4 of 47
A B C D E
 5 4 3 2 1

DDR_A_D[0..63] 13 DDR_B_D[0..63] 14

DDR_A_DQS[0..7] 13 DDR_B_DQS[0..7] 14

DDR_A_DQS#[0..7] 13 DDR_B_DQS#[0..7] 14
USOC1A USOC1B
13 DDR_A_MA[0..15] 14 DDR_B_MA[0..15]
DDR_A_MA0 K45 M36 DDR_A_D0 DDR_B_MA0 AY45 BG38 DDR_B_D0
DDR_A_MA1 H47 DRAM0_MA_0 DRAM0_DQ_0 J36 DDR_A_D1 DDR_B_MA1 BB47 DRAM1_MA_0 DRAM1_DQ_0 BC40 DDR_B_D1
DDR_A_MA2 L41 DRAM0_MA_1 DRAM0_DQ_1 P40 DDR_A_D2 DDR_B_MA2 AW41 DRAM1_MA_1 DRAM1_DQ_1 BA42 DDR_B_D2
DDR_A_MA3 H44 DRAM0_MA_2 DRAM0_DQ_2 M40 DDR_A_D3 DDR_B_MA3 BB44 DRAM1_MA_2 DRAM1_DQ_2 BD42 DDR_B_D3
D DDR_A_MA4 H50 DRAM0_MA_3 DRAM0_DQ_3 P36 DDR_A_D4 DDR_B_MA4 BB50 DRAM1_MA_3 DRAM1_DQ_3 BC38 DDR_B_D4 D
DDR_A_MA5 G53 DRAM0_MA_4 DRAM0_DQ_4 N36 DDR_A_D5 DDR_B_MA5 BC53 DRAM1_MA_4 DRAM1_DQ_4 BD36 DDR_B_D5
DDR_A_MA6 H49 DRAM0_MA_5 DRAM0_DQ_5 K40 DDR_A_D6 DDR_B_MA6 BB49 DRAM1_MA_5 DRAM1_DQ_5 BF42 DDR_B_D6
DDR_A_MA7 D50 DRAM0_MA_6 DRAM0_DQ_6 K42 DDR_A_D7 DDR_B_MA7 BF50 DRAM1_MA_6 DRAM1_DQ_6 BC44 DDR_B_D7
DDR_A_MA8 G52 DRAM0_MA_7 DRAM0_DQ_7 B32 DDR_A_D8 DDR_B_MA8 BC52 DRAM1_MA_7 DRAM1_DQ_7 BH32 DDR_B_D8
DDR_A_MA9 E52 DRAM0_MA_8 DRAM0_DQ_8 C32 DDR_A_D9 DDR_B_MA9 BE52 DRAM1_MA_8 DRAM1_DQ_8 BG32 DDR_B_D9
DDR_A_MA10 K48 DRAM0_MA_9 DRAM0_DQ_9 C36 DDR_A_D10 DDR_B_MA10 AY48 DRAM1_MA_9 DRAM1_DQ_9 BG36 DDR_B_D10
DDR_A_MA11 E51 DRAM0_MA_10 DRAM0_DQ_10 A37 DDR_A_D11 DDR_B_MA11 BE51 DRAM1_MA_10 DRAM1_DQ_10 BJ37 DDR_B_D11
DDR_A_MA12 F47 DRAM0_MA_11 DRAM0_DQ_11 C33 DDR_A_D12 DDR_B_MA12 BD47 DRAM1_MA_11 DRAM1_DQ_11 BG33 DDR_B_D12
DDR_A_MA13 J51 DRAM0_MA_12 DRAM0_DQ_12 A33 DDR_A_D13 DDR_B_MA13 BA51 DRAM1_MA_12 DRAM1_DQ_12 BJ33 DDR_B_D13
DDR_A_MA14 B49 DRAM0_MA_13 DRAM0_DQ_13 C37 DDR_A_D14 DDR_B_MA14 BH49 DRAM1_MA_13 DRAM1_DQ_13 BG37 DDR_B_D14
DDR_A_MA15 B50 DRAM0_MA_14 DRAM0_DQ_14 B38 DDR_A_D15 DDR_B_MA15 BH50 DRAM1_MA_14 DRAM1_DQ_14 BH38 DDR_B_D15
DRAM0_MA_15 DRAM0_DQ_15 F36 DDR_A_D16 DRAM1_MA_15 DRAM1_DQ_15 AU36 DDR_B_D16
13 DDR_A_DM[0..7] DRAM0_DQ_16 14 DDR_B_DM[0..7] DRAM1_DQ_16
DDR_A_DM0 G36 G38 DDR_A_D17 DDR_B_DM0 BD38 AT36 DDR_B_D17
DDR_A_DM1 B36 DRAM0_DM_0 DRAM0_DQ_17 F42 DDR_A_D18 DDR_B_DM1 BH36 DRAM1_DM_0 DRAM1_DQ_17 AV40 DDR_B_D18
DDR_A_DM2 F38 DRAM0_DM_1 DRAM0_DQ_18 J42 DDR_A_D19 DDR_B_DM2 BC36 DRAM1_DM_1 DRAM1_DQ_18 AT40 DDR_B_D19
DDR_A_DM3 B42 DRAM0_DM_2 DRAM0_DQ_19 G40 DDR_A_D20 DDR_B_DM3 BH42 DRAM1_DM_2 DRAM1_DQ_19 BA36 DDR_B_D20
DDR_A_DM4 P51 DRAM0_DM_3 DRAM0_DQ_20 C38 DDR_A_D21 DDR_B_DM4 AT51 DRAM1_DM_3 DRAM1_DQ_20 AV36 DDR_B_D21
DDR_A_DM5 V42 DRAM0_DM_4 DRAM0_DQ_21 G44 DDR_A_D22 DDR_B_DM5 AM42 DRAM1_DM_4 DRAM1_DQ_21 AY42 DDR_B_D22
DDR_A_DM6 Y50 DRAM0_DM_5 DRAM0_DQ_22 D42 DDR_A_D23 DDR_B_DM6 AK50 DRAM1_DM_5 DRAM1_DQ_22 AY40 DDR_B_D23
DDR_A_DM7 Y52 DRAM0_DM_6 DRAM0_DQ_23 A41 DDR_A_D24 DDR_B_DM7 AK52 DRAM1_DM_6 DRAM1_DQ_23 BJ41 DDR_B_D24
DRAM0_DM_7 DRAM0_DQ_24 C41 DDR_A_D25 DRAM1_DM_7 DRAM1_DQ_24 BG41 DDR_B_D25
M45 DRAM0_DQ_25 A45 DDR_A_D26 AV45 DRAM1_DQ_25 BJ45 DDR_B_D26
13 DDR_A_RAS# DRAM0_RAS# DRAM0_DQ_26 14 DDR_B_RAS# DRAM1_RAS# DRAM1_DQ_26
M44 B46 DDR_A_D27 AV44 BH46 DDR_B_D27
13 DDR_A_CAS# DRAM0_CAS# DRAM0_DQ_27 14 DDR_B_CAS# DRAM1_CAS# DRAM1_DQ_27
H51 C40 DDR_A_D28 BB51 BG40 DDR_B_D28
13 DDR_A_WE# DRAM0_WE# DRAM0_DQ_28 14 DDR_B_WE# DRAM1_WE# DRAM1_DQ_28
B40 DDR_A_D29 BH40 DDR_B_D29
K47 DRAM0_DQ_29 B48 DDR_A_D30 AY47 DRAM1_DQ_29 BH48 DDR_B_D30
13 DDR_A_BS0 DRAM0_BS_0 DRAM0_DQ_30 14 DDR_B_BS0 DRAM1_BS_0 DRAM1_DQ_30
K44 B47 DDR_A_D31 AY44 BH47 DDR_B_D31
13 DDR_A_BS1 DRAM0_BS_1 DRAM0_DQ_31 14 DDR_B_BS1 DRAM1_BS_1 DRAM1_DQ_31
D52 K52 DDR_A_D32 BF52 AY52 DDR_B_D32
13 DDR_A_BS2 DRAM0_BS_2 DRAM0_DQ_32 14 DDR_B_BS2 DRAM1_BS_2 DRAM1_DQ_32
K51 DDR_A_D33 AY51 DDR_B_D33
P44 DRAM0_DQ_33 T52 DDR_A_D34 AT44 DRAM1_DQ_33 AP52 DDR_B_D34
13 DDR_A_CS0# DRAM0_CS_0# DRAM0_DQ_34 14 DDR_B_CS0# DRAM1_CS_0# DRAM1_DQ_34
T51 DDR_A_D35 AP51 DDR_B_D35
C P45 DRAM0_DQ_35 L51 DDR_A_D36 AT45 DRAM1_DQ_35 AW51 DDR_B_D36 C
13 DDR_A_CS2# DRAM0_CS_2# DRAM0_DQ_36 14 DDR_B_CS2# DRAM1_CS_2# DRAM1_DQ_36
L53 DDR_A_D37 AW53 DDR_B_D37
DRAM0_DQ_37 R51 DDR_A_D38 DRAM1_DQ_37 AR51 DDR_B_D38
C47 DRAM0_DQ_38 R53 DDR_A_D39 BG47 DRAM1_DQ_38 AR53 DDR_B_D39
13 DDR_A_CKE0 DRAM0_CKE_0 DRAM0_DQ_39 14 DDR_B_CKE0 DRAM1_CKE_0 DRAM1_DQ_39
D48 T47 DDR_A_D40 BE46 AP47 DDR_B_D40
F44 RESERVED_D48 DRAM0_DQ_40 T45 DDR_A_D41 BD44 RESERVED_BE46 DRAM1_DQ_40 AP45 DDR_B_D41
13 DDR_A_CKE2 DRAM0_CKE_2 DRAM0_DQ_41 14 DDR_B_CKE2 DRAM1_CKE_2 DRAM1_DQ_41
E46 Y40 DDR_A_D42 BF48 AK40 DDR_B_D42
RESERVED_E46 DRAM0_DQ_42 V41 DDR_A_D43 RESERVED_BF48 DRAM1_DQ_42 AM41 DDR_B_D43
T41 DRAM0_DQ_43 T48 DDR_A_D44 AP41 DRAM1_DQ_43 AP48 DDR_B_D44
13 DDR_A_ODT0 DRAM0_ODT_0 DRAM0_DQ_44 14 DDR_B_ODT0 DRAM1_ODT_0 DRAM1_DQ_44
T50 DDR_A_D45 AP50 DDR_B_D45
P42 DRAM0_DQ_45 Y42 DDR_A_D46 AT42 DRAM1_DQ_45 AK42 DDR_B_D46
13 DDR_A_ODT2 DRAM0_ODT_2 DRAM0_DQ_46 14 DDR_B_ODT2 DRAM1_ODT_2 DRAM1_DQ_46
AB40 DDR_A_D47 AH40 DDR_B_D47
DRAM0_DQ_47 V45 DDR_A_D48 DRAM1_DQ_47 AM45 DDR_B_D48
M50 DRAM0_DQ_48 V47 DDR_A_D49 AV50 DRAM1_DQ_48 AM47 DDR_B_D49
13 DDR_A_CLK0 DRAM0_CKP_0 DRAM0_DQ_49 14 DDR_B_CLK0 DRAM1_CKP_0 DRAM1_DQ_49
M48 AD48 DDR_A_D50 AV48 AF48 DDR_B_D50
13 DDR_A_CLK0# DRAM0_CKN_0 DRAM0_DQ_50 14 DDR_B_CLK0# DRAM1_CKN_0 DRAM1_DQ_50
AD50 DDR_A_D51 AF50 DDR_B_D51
DRAM0_DQ_51 V48 DDR_A_D52 DRAM1_DQ_51 AM48 DDR_B_D52
P50 DRAM0_DQ_52 V50 DDR_A_D53 DRAM1_DQ_52 AM50 DDR_B_D53
13 DDR_A_CLK2 DRAM0_CKP_2 DRAM0_DQ_53 DRAM1_DQ_53
P48 AB44 DDR_A_D54 AT50 AH44 DDR_B_D54
13 DDR_A_CLK2# DRAM0_CKN_2 DRAM0_DQ_54 14 DDR_B_CLK2 DRAM1_CKP_2 DRAM1_DQ_54
Y45 DDR_A_D55 AT48 AK45 DDR_B_D55
DRAM0_DQ_55 14 DDR_B_CLK2# DRAM1_CKN_2 DRAM1_DQ_55
V52 DDR_A_D56 AM52 DDR_B_D56
DRAM0_DQ_56 W51 DDR_A_D57 DRAM1_DQ_56 AL51 DDR_B_D57
P41 DRAM0_DQ_57 AC53 DDR_A_D58 DRAM1_DQ_57 AG53 DDR_B_D58
13 DDR_A_RST# DRAM0_DRAMRST# DRAM0_DQ_58 DRAM1_DQ_58
AC51 DDR_A_D59 AT41 AG51 DDR_B_D59
DRAM0_DQ_59 14 DDR_B_RST# DRAM1_DRAMRST# DRAM1_DQ_59
W53 DDR_A_D60 AL53 DDR_B_D60
DRAM0_DQ_60 Y51 DDR_A_D61 DRAM1_DQ_60 AK51 DDR_B_D61
AF44 DRAM0_DQ_61 AD52 DDR_A_D62 DRAM1_DQ_61 AF52 DDR_B_D62
+DDR_SOC_VREF DRAM_VREF 0.675V DRAM0_DQ_62 DRAM1_DQ_62
AD51 DDR_A_D63 AF51 DDR_B_D63
DRAM0_DQ_63 DRAM1_DQ_63
100K_0402_5% 1 2 R960 DDR_TERMN0 AF42 J38 DDR_A_DQS0 BF40 DDR_B_DQS0
100K_0402_5% 1 2 R961 DDR_TERMN1 AH42 ICLK_DRAM_TERMN_AF42 DRAM0_DQSP_0 K38 DDR_A_DQS#0 DRAM1_DQSP_0 BD40 DDR_B_DQS#0
ICLK_DRAM_TERMN_AH42 DRAM0_DQSN_0 C35 DDR_A_DQS1 DRAM1_DQSN_0 BG35 DDR_B_DQS1
B DRAM0_DQSP_1 B34 DDR_A_DQS#1 DRAM1_DQSP_1 BH34 DDR_B_DQS#1 B
DRAM0_DQSN_1 D40 DDR_A_DQS2 DRAM1_DQSN_1 BA38 DDR_B_DQS2
AD42 DRAM0_DQSP_2 F40 DDR_A_DQS#2 DRAM1_DQSP_2 AY38 DDR_B_DQS#2
37 DDR_PWROK DRAM_VDD_S4_PWROK DRAM0_DQSN_2 DRAM1_DQSN_2
AB42 B44 DDR_A_DQS3 BH44 DDR_B_DQS3
8 DDR_CORE_PWROK DRAM_CORE_PWROK DRAM0_DQSP_3 DRAM1_DQSP_3
C43 DDR_A_DQS#3 BG43 DDR_B_DQS#3
DRAM0_DQSN_3 N53 DDR_A_DQS4 DRAM1_DQSN_3 AU53 DDR_B_DQS4
23.2_0402_1% 1 2 R962 DDR_RCOMP0 AD44 DRAM0_DQSP_4 M52 DDR_A_DQS#4 DRAM1_DQSP_4 AV52 DDR_B_DQS#4
29.4_0402_1% 1 2 R963 DDR_RCOMP1 AF45 DRAM_RCOMP_0 DRAM0_DQSN_4 T42 DDR_A_DQS5 DRAM1_DQSN_4 AP42 DDR_B_DQS5
162_0402_1% 1 2 R964 DDR_RCOMP2 AD45 DRAM_RCOMP_1 DRAM0_DQSP_5 T44 DDR_A_DQS#5 DRAM1_DQSP_5 AP44 DDR_B_DQS#5
DRAM_RCOMP_2 DRAM0_DQSN_5 Y47 DDR_A_DQS6 DRAM1_DQSN_5 AK47 DDR_B_DQS6
DRAM0_DQSP_6 DRAM1_DQSP_6
Follow CRB v2.0 DRAM0_DQSN_6
Y48 DDR_A_DQS#6
DRAM1_DQSN_6
AK48 DDR_B_DQS#6
AF40 AB52 DDR_A_DQS7 AH52 DDR_B_DQS7
AF41 RESERVED_AF40 DRAM0_DQSP_7 AA51 DDR_A_DQS#7 DRAM1_DQSP_7 AJ51 DDR_B_DQS#7
AD40 RESERVED_AF41 DRAM0_DQSN_7 DRAM1_DQSN_7
AD41 RESERVED_AD40
RESERVED_AD41 1 OF 13 2 OF 13

2 1 DDR_CORE_PWROK FH8065301546401_FCBGA131170 FH8065301546401_FCBGA131170

EMC@ C1159 B0@ B0@
0.047U_0402_16V4Z Close To SOC Pin

+1.35V_L +DDR_SOC_VREF

1 2
R965 1
4.7K_0402_1%
C1132
USOC1 USOC1 USOC1 1 2 .1U_0402_16V7K
N2820@ N2920@ N3520@ R966 2
4.7K_0402_1%
A A
S IC FH8065301616602 QFW4 B3 2.13G ABO! S IC FH8065301616203 SR1SF B3 1.86G ABO! S IC FH8065301616103 SR1SE B3 2.17G ABO!
SA00007EK80 SA00007E840 SA00007E970

USOC1 USOC1 USOC1

N2830@ N2930@ N3530@ Security Classification Compal Secret Data Compal Electronics, Inc.
2014/03/19 2015/03/18 Title
Issued Date Deciphered Date VLV-M SOC Memory DDR3L
S IC FH8065301729602 SR1W4 C0 2.16G ABO! S IC FH8065301729501 SR1W3 C0 1.83G ABO! S IC FH8065301728501 SR1W2 C0 2.16G FCBGA 1170
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SA00007QRD0 SA00007RVB0 SA00007QQB0 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A5WAM_Bay Trail M_LA‐B981P
Date: Monday, May 12, 2014 Sheet 5 of 47
5 4 3 2 1
 5 4 3 2 1

D D

USOC1C

AV3 AG3
23 HDMI_TX2+ DDI0_TXP_0 DDI1_TXP_0 EDP_TXP0 22
AV2 1.0V 1.0V AG1
23 HDMI_TX2- DDI0_TXN_0 DDI1_TXN_0 EDP_TXN0 22
AT2 AF3
23 HDMI_TX1+ DDI0_TXP_1 DDI1_TXP_1 EDP_TXP1 22
AT3 AF2
23 HDMI_TX1- DDI0_TXN_1 DDI1_TXN_1 EDP_TXN1 22
AR3 AD3
23 HDMI_TX0+ DDI0_TXP_2 DDI1_TXP_2
AR1 AD2
23 HDMI_TX0- DDI0_TXN_2 DDI1_TXN_2
23 HDMI_CLK+
AP3
DDI0_TXP_3 DDI1_TXP_3
AC3
eDP Panel
HDMI 23 HDMI_CLK-
AP2
DDI0_TXN_3 DDI1_TXN_3
AC1

AL3 1.0V AK3 EDP_AUXP 22

AL1 DDI0_AUXP DDI1_AUXP AK2
DDI0_AUXN 1.0V DDI1_AUXN EDP_AUXN 22
D27 1.8V 1.8V K30
23 HDMI_HPD# DDI0_HPD DDI1_HPD EDP_HPD# 22
C26 1.8V 1.8V P30 DDI1_ENABLE R967 1 2 2.2K_0402_5% +1.8VS
23 HDMI_DDCDATA DDI0_DDCDATA DDI1_DDCDATA
C28 1.8V 1.8V G30
23 HDMI_DDCCLK DDI0_DDCCLK DDI1_DDCCLK
B28 1.8V N30 DDI1_ENVDD
C27 DDI0_VDDEN DDI1_VDDEN J30 DDI1_ENBKL
DDI0_BKLTEN 1.8V DDI1_BKLTEN
B26 1.8V M30 DDI1_PWM
DDI0_BKLTCTL DDI1_BKLTCTL
AH3
VSS_AH3
1 R968 2 DDI0_RCOMPP AK12
DDI0_RCOMP_P VSS_AH2
AH2 Follow CRB v2.0 0ohm till to GND
402_0402_1% DDI0_RCOMPN AK13
AM14 DDI0_RCOMP_N AH14
AM13 RESERVED_AM14 RESERVED_AH14 AH13
AM3 RESERVED_AM13 RESERVED_AH13 AF14
VSS_AM3 RESERVED_AF14
C
Follow CRB v2.0 0ohm till to GND AM2
VSS_AM2 RESERVED_AF13
AF13 C

BA3 CRT_R
VGA_RED CRT_R 24
AY2 CRT_B
VGA_BLUE CRT_B 24
BA1 CRT_G
VGA_GREEN CRT_G 24
AW1 CRT_IREF 1 2
VGA_IREF AY3 R969 357_0402_1%
VGA_IRTN
3.3V
3.3V
VGA_HSYNC
VGA_VSYNC
BD2 CRT_HSYNC
BF2 CRT_VSYNC
CRT_HSYNC
CRT_VSYNC
24
24
CRT
3.3V BC1 CRT_DDC_CLK
VGA_DDCCLK CRT_DDC_CLK 24
3.3V BC2 CRT_DDC_DATA
VGA_DDCDATA CRT_DDC_DATA 24
T2 T7
T3 RESERVED_T2 RESERVED_T7 T9
AB3 RESERVED_T3 RESERVED_T9 AB13
AB2 RESERVED_AB3 RESERVED_AB13 AB12
Y3 RESERVED_AB2 RESERVED_AB12 Y12
RESERVED_Y3 RESERVED_Y12
Y2
W3 RESERVED_Y2 RESERVED_Y13
Y13
V10
CRT RP43
W1 RESERVED_W3 RESERVED_V10 V9 150_0804_8P4R_1%
V2 RESERVED_W1 RESERVED_V9 T12 CRT_R 8 1
V3 RESERVED_V2 RESERVED_T12 T10 CRT_G 7 2
R3 RESERVED_V3 RESERVED_T10 V14 CRT_B 6 3
R1 RESERVED_R3 RESERVED_V14 V13 5 4
+1.8VS AD6 RESERVED_R1 RESERVED_V13 T14
AD4 RESERVED_AD6 RESERVED_T14 T13
AB9 RESERVED_AD4 RESERVED_T13 T6
RESERVED_AB9 RESERVED_T6
1

AB7 T4
@ Y4 RESERVED_AB7 RESERVED_T4 P14
RESERVED_Y4 RESERVED_P14 +1.8VS
B
R970
10K_0402_5%
Y6
V4 RESERVED_Y6 F34
eDP B
V6 RESERVED_V4 GPIO_S0_NC_15 M32
2

RESERVED_V6 GPIO_S0_NC_16

5
GPIO_NC13 A29 D28 U61
@ GPIO_NC14 C29 GPIO_S0_NC_13 GPIO_S0_NC_17 J28 1

P
T186 GPIO_S0_NC14 GPIO_S0_NC_18 NC
1

AB14 K34 4
RESERVED_AB14 GPIO_S0_NC_19 Y ENBKL 29
@ GPIO_NC12 B30 D34 DDI1_ENBKL 2
T187 GPIO_S0_NC_12 GPIO_S0_NC_20 A

G
R971 C30 F32
10K_0402_5% RESERVED_C30 GPIO_S0_NC_21 F28 NL17SZ07DFT2G_SC70-5 +3VS

3
GPIO_S0_NC_22 K28 SA00004BV00
2

GPIO_S0_NC_23 J34 9012@ ENBKL 1 9012@ 2

GPIO_S0_NC_24 N32 4.7K_0402_5% R1159
GPIO_S0_NC_25 D32 R1142 1 RS@ 2 0_0402_5%
GPIO_S0_NC_26
Follow CRB v2.0 3 OF 10 ENVDD 1 2
4.7K_0402_5% R1160
FH8065301546401_FCBGA131170 +1.8VALW
PVT modify
INVT_PWM_SOC 1 2
GPIO_S0_NC[13]: B0@ 4.7K_0402_5% R1161

5
U62
Multiplexed with Hardware Straps Pin:MDSI_DDCDATA 1

P
NC 4
Y ENVDD 22
DDI1_ENVDD 2
A

G
NL17SZ07DFT2G_SC70-5

3
SA00004BV00

RP45
+1.8VALW DDI1_ENBKL 8 1
PVT modify DDI1_ENVDD 7 2
DDI1_PWM 6 3

5
U64 5 4
1

P
NC 4 100K_0804_8P4R_5%
A Y INVT_PWM_SOC 22 A
DDI1_PWM 2
A

G
NL17SZ07DFT2G_SC70-5

3
SA00004BV00

Security Classification Compal Secret Data Compal Electronics, Inc.

2014/03/19 2015/03/18 Title
Issued Date Deciphered Date VLV-M SOC Display
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A5WAM_Bay Trail M_LA‐B981P
Date: Monday, May 12, 2014 Sheet 6 of 47
5 4 3 2 1
 5 4 3 2 1

Follow ACER 2014 X86 HSIO DG V1.03

D D

USOC1D

BF6 AY7 PEG_HTX_GRX_P0 C76 1 2 VGA@ .1U_0402_16V7K

27 SATA_PTX_DRX_P0 SATA_TXP_0 PCIE_TXP_0 PEG_HTX_C_GRX_P0 15
BG7 AY6 PEG_HTX_GRX_N0 C77 1 2 VGA@ .1U_0402_16V7K
27 SATA_PTX_DRX_N0 SATA_TXN_0 PCIE_TXN_0 PEG_HTX_C_GRX_N0 15
HDD
AU16 AT14 PEG_GTX_C_HRX_P0
27 SATA_PRX_DTX_P0 SATA_RXP_0 PCIE_RXP_0 PEG_GTX_C_HRX_P0 15
AV16 AT13 PEG_GTX_C_HRX_N0
27 SATA_PRX_DTX_N0 SATA_RXN_0 PCIE_RXN_0 PEG_GTX_C_HRX_N0 15
BD10 AV6 PEG_HTX_GRX_P1 C78 1 2 VGA@ .1U_0402_16V7K
dGPU
27 SATA_PTX_DRX_P1 SATA_TXP_1 PCIE_TXP_1 PEG_HTX_C_GRX_P1 15
BF10 AV4 PEG_HTX_GRX_N1 C79 1 2 VGA@ .1U_0402_16V7K
27 SATA_PTX_DRX_N1 SATA_TXN_1 PCIE_TXN_1 PEG_HTX_C_GRX_N1 15
ODD
AY16 AT10 PEG_GTX_C_HRX_P1
27 SATA_PRX_DTX_P1 SATA_RXP_1 PCIE_RXP_1 PEG_GTX_C_HRX_P1 15
BA16 AT9 PEG_GTX_C_HRX_N1
27 SATA_PRX_DTX_N1 SATA_RXN_1 PCIE_RXN_1 PEG_GTX_C_HRX_N1 15
BB10 AT7 PCIE_PTX_DRX_P2 C1135 1 2 .1U_0402_16V7K
VSS_BB10 PCIE_TXP_2 PCIE_PTX_C_DRX_P2 26
Follow CRB V2.0 0ohm till to GND BC10
VSS_BC10 PCIE_TXN_2
AT6 PCIE_PTX_DRX_N2 C1000 1 2 .1U_0402_16V7K
PCIE_PTX_C_DRX_N2 26
SOC_SCI# BA12 AP12 PCIE_PRX_DTX_P2
WLAN
8 SOC_SCI# SATA_GP0 / GPIO_S0_SC_0 PCIE_RXP_2 PCIE_PRX_DTX_P2 26
@ T188 DEVSLP_SOC AY14 AP10 PCIE_PRX_DTX_N2
SATA_GP1 / SATA_DEVSLP_0 / GPIO_S0_SC_1 PCIE_RXN_2 PCIE_PRX_DTX_N2 26
AY12
SATA_LED# / GPIO_S0_SC_2 AP6 PCIE_PTX_DRX_P3 C1133 1 2 .1U_0402_16V7K
C PCIE_TXP_3 PCIE_PTX_C_DRX_P3 25 C
1 R972 2 SATA_RCOMPP AU18 AP4 PCIE_PTX_DRX_N3 C1134 1 2 .1U_0402_16V7K
SATA_RCOMP_P PCIE_TXN_3 PCIE_PTX_C_DRX_N3 25
402_0402_1% SATA_RCOMPN AT18 PCIE LAN
SATA_RCOMP_N AP9 PCIE_PRX_DTX_P3 +1.8VS
PCIE_RXP_3 PCIE_PRX_DTX_P3 25
AP7 PCIE_PRX_DTX_N3 RP51
PCIE_RXN_3 PCIE_PRX_DTX_N3 25
AT22 VGA_CLKREQ# 1 8
MMC1_CLK / GPIO_S0_SC_16 BB7 PCIE_CLKREQ_1# 2 7
VSS_BB7
AV20
MMC1_D0 / GPIO_S0_SC_17 VSS_BB5
BB5 Follow CRB V2.0 0ohm till to GND WLAN_CLKREQ# 3 6
AU22 LAN_CLKREQ# 4 5
AV22 MMC1_D1 / GPIO_S0_SC_18 BG3 VGA_CLKREQ#
MMC1_D2 / GPIO_S0_SC_19 PCIE_CLKREQ_0# / GPIO_S0_SC_3 VGA_CLKREQ# 15
AT20 BD7 PCIE_CLKREQ_1# 10K_0804_8P4R_5%
AY24 MMC1_D3 / GPIO_S0_SC_20 PCIE_CLKREQ_1# / GPIO_S0_SC_4 BG5 WLAN_CLKREQ#
MMC1_D4 / GPIO_S0_SC_21 PCIE_CLKREQ_2# / GPIO_S0_SC_5 WLAN_CLKREQ# 26
AU26 BE3 LAN_CLKREQ#
MMC1_D5 / GPIO_S0_SC_22 PCIE_CLKREQ_3# / GPIO_S0_SC_6 LAN_CLKREQ# 25
AT26 BD5 RP46
AU20 MMC1_D6 / GPIO_S0_SC_23 SD3_WP / GPIO_S0_SC_7 HDA_SYNC 8 1
MMC1_D7 / GPIO_S0_SC_24 HDA_SYNC_AUDIO 31
AP14 PCIE_RCOMPP 1 R975 2 HDA_SDOUT 7 2 HDA_SDOUT_AUDIO 31
AV26 PCIE_RCOMP_P AP13 PCIE_RCOMPN 402_0402_1% HDA_BIT_CLK 6 3
MMC1_CMD / GPIO_S0_SC_25 PCIE_RCOMP_N HDA_BITCLK_AUDIO 31
BA24 HDA_RST# 5 4 HDA_RST_AUDIO# 31
MMC1_RST# / SATA_DEVSLP_0 / GPIO_S0_SC_26 BB4
AY18 RESERVED_BB4 BB3 33_0804_8P4R_5%
MMC1_RCOMP RESERVED_BB3 EMC@
AV10
BA18 RESERVED_AV10 AV9
AY20 SD2_CLK / GPIO_S0_SC_27 RESERVED_AV9 HDA_RCOMP R976 1 2 49.9_0402_1%
BD20 SD2_D0 / GPIO_S0_SC_28 BF20 HDA_RCOMP
BA20 SD2_D1 / GPIO_S0_SC_29 HDA_LPE_RCOMP BG22 HDA_RST# HDA_BITCLK_AUDIO C1001 1 2 22P_0402_50V8J
BD18 SD2_D2 / GPIO_S0_SC_30 HDA_RST# / LPE_I2S0_CLK / GPIO_S0_SC_8 BH20 HDA_SYNC
BC18 SD2_D3_CD# / GPIO_S0_SC_31 HDA_SYNC / LPE_I2S0_FRM / GPIO_S0_SC_9 BJ21 HDA_BIT_CLK @EMC@
SD2_CMD / GPIO_S0_SC_32 HDA_CLK / LPE_I2S0_DATAOUT / GPIO_S0_SC_10 BG20 HDA_SDOUT
HDA_SDO / LPE_I2S0_DATAIN / GPIO_S0_SC_11 BG19 HDA_SDIN0
HDA_SDI0 / LPE_I2S1_CLK / GPIO_S0_SC_12 HDA_SDIN0 31
BG21 @
HDA_SDI1 / LPE_I2S1_FRM / GPIO_S0_SC_13 T189
AY26 BH18 GPIO_S0_SC_14
AT28 SD3_CLK / GPIO_S0_SC_33 HDA_DOCKRST# / LPE_I2S1_DATAOUT / GPIO_S0_SC_14 BG18 @
B SD3_D0 / GPIO_S0_SC_34 HDA_DOCKEN# / LPE_I2S1_DATAIN / GPIO_S0_SC_15 T191 B
BD26 GPIO_S0_SC_63:
AU28 SD3_D1 / GPIO_S0_SC_35 BF28
BA26 SD3_D2 / GPIO_S0_SC_36 LPE_I2S2_CLK / SATA_DEVSLP_1 / GPIO_S0_SC_62 BA30 GPIO_S0_SC_63 BIOS Boot Selection
BC24 SD3_D3 / GPIO_S0_SC_37 LPE_I2S2_FRM / GPIO_S0_SC_63 BD28
AV28 SD3_CD# / GPIO_S0_SC_38 LPE_I2S2_DATAIN / GPIO_S0_SC_64 BC30 GPIO_S0_SC_65 Follow CRB v2.0 0 = LPC
SD3_CMD / GPIO_S0_SC_39 LPE_I2S2_DATAOUT / GPIO_S0_SC_65 +1.8VS
BF22
SD3_1P8EN / GPIO_S0_SC_40
1 = SPI
BD22 P34
SD3_PWREN# / GPIO_S0_SC_41 RESERVED_P34 N34 R979
BF26 RESERVED_N34 73.2_0402_1% GPIO_S0_SC_63 R977 2 1 10K_0402_5%
SD3_RCOMP AK9 1 2
RESERVED_AK9 +1.0VS
AK7
RESERVED_AK7
C24 H_PROCHOT# 29
PROCHOT#
4 OF 10 Internal PD 2K
FH8065301546401_FCBGA131170
2
@EMC@
GPIO_S0_SC_65:
B0@ C1002 Security Flash Descriptors
10P_0402_50V8J 0 = Override
1
1 = Normal Operation   (Internal PU)
+1.8VS

1
R978
10K_0402_5%
EC programing :

2
GPIO_S0_SC_65 "High"for Flash BIOS
DGPU_HOLD_RST#_SOC1.8V R1175 1 @ 2 0_0402_5% GPIO_S0_SC_14
15,9 DGPU_HOLD_RST#_SOC1.8V D

1
A 2 A
TXE_DBG 29
G
S Q62

3
MESS138W-G_SOT323-3

Security Classification Compal Secret Data Compal Electronics, Inc.

2014/03/19 2015/03/18 Title
Issued Date Deciphered Date VLV-M SOC SATA/PCI-E/HDA
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A5WAM_Bay Trail M_LA‐B981P
Date: Monday, May 12, 2014 Sheet 7 of 47
5 4 3 2 1
 5 4 3 2 1

+3VS
+1.8VALW
PVT modify

1
R982

5
XTAL_25M_IN USOC1E U53 4.7K_0402_5%
1.8V 1 3.3V

2
NC

1
XTAL_25M_IN AH12 AU34 R983 2 1 2.2K_0402_5% +1.8VALW 4
ICLK_OSCIN SIO_UART1_RXD / GPIO_S0_SC_70 Y PLT_RST_BUF# 15,25,26,29,30
R981 XTAL_25M_OUT AH10 AV34 PMC_PLTRST# 2
ICLK_OSCOUT SIO_UART1_TXD / GPIO_S0_SC_71 A

G
Y7 1M_0402_5% BA34
25MHZ_10PF_7V25000014 AD9 SIO_UART1_RTS# / GPIO_S0_SC_72 AY34 PMC_ACIN D40 2 1 NL17SZ07DFT2G_SC70-5
ACIN 29,35

3
RESERVED_AD9 SIO_UART1_CTS# / GPIO_S0_SC_73 SA00004BV00

2
10P_0402_50V8J

1 3 XTAL_25M_OUT ICLK_ICOMP AD14 BF34 RB751V-40-YS_SOD323-2

1 3 ICLK_RCOMP AD13 ICLK_ICOMP SIO_UART2_RXD / GPIO_S0_SC_74 BD34
1 GND GND 1 ICLK_RCOMP SIO_UART2_TXD / GPIO_S0_SC_75 PLT_RST# Buffer
C1003

BD32 PLT_RST_BUF# 1 2
D C1004 AD10 SIO_UART2_RTS# / GPIO_S0_SC_76 BF32 C1174 @EMC@ D
2 4 10P_0402_50V8J AD12 RESERVED_AD10 SIO_UART2_CTS# / GPIO_S0_SC_77 0.01U_0402_16V7K
2 2 RESERVED_AD12 +1.8VALW
AF6 RP47
15 CLK_PEG_VGA# PCIE_CLKN_0
dGPU 15 CLK_PEG_VGA
AF4
PCIE_CLKP_0 PMC_SUSPWRDNACK / GPIO_S5_11
D26 PMC_PCIE_WAKE# 1 8
G24 PMC_SUSCLK T192@ 32.768k output PMC_BATLOW# 2 7
AF9 PMC_SUSCLK_0 / GPIO_S5_12 F18 DGPU_PRSNT# 3 6
AF7 PCIE_CLKN_1 PMC_SLP_S0IX# / GPIO_S5_13 F22 PMC_SLP_S4# LS_OE 4 5
R984 1 2 4.02K_0402_1% ICLK_ICOMP PCIE_CLKP_1 PMC_SLP_S4# D22 PMC_SLP_S3#
PMC_SLP_S3#
R985 1 2 47.5_0402_1% ICLK_RCOMP
GPIO_S5_14
J20 DGPU_PRSNT# DGPU_PRSNT# 10K_0804_8P4R_5%
AK4 D20 PMC_ACIN
26 CLK_PCIE_WLAN# PCIE_CLKN_2 PMC_ACPRESENT
WLAN 26 CLK_PCIE_WLAN
AK6
PCIE_CLKP_2 PMC_WAKE_PCIE_0# / GPIO_S5_15
F26 PMC_PCIE_WAKE# UMA H R485 1 2 100K_0402_5%
K26 PMC_BATLOW#
PMC_BATLOW#
25 CLK_PCIE_LAN#
AM4
PCIE_CLKN_3 PMC_PWRBTN# / GPIO_S5_16
J26 PMC_PWRBTN# DIS L* @EMC@
LAN 25 CLK_PCIE_LAN
AM6
PCIE_CLKP_3 PMC_RSTBTN#
BG9 PMC_RSTBTN# T209@ PMC_CORE_PWROK C1007 1 2 0.047U_0402_25V7K
F20 PMC_PLTRST#
AM9 PMC_PLTRST# J24 GPIO_S5_17 T205@ EMC@
RESERVED_AM9 GPIO_S5_17
For XDP use AM10
RESERVED_AM10 PMC_SUS_STAT# / GPIO_S5_18
G18 PMC_SUS_STAT# T207@ DDR_CORE_PWROK C1158 1 2 0.01U_0402_16V7K
+1.8VALW
EMC@
R989 1 2 51_0402_5% XDP_H_PRDY# PMC_PLTRST# C1006 1 2 .1U_0402_16V7K
R1026 1 2 51_0402_5% XDP_H_TDO C11 RTC_TEST#
R1024 1 2 200_0402_5% XDP_H_PREQ_BUF# BH7 ILB_RTC_TEST# C12 RTC_RST#
BH5 PMC_PLT_CLK_0 / GPIO_S0_SC_96 ILB_RTC_RST# EC_RSMRST# R990 1 2 100K_0402_5%
RP52 BH4 PMC_PLT_CLK_1 / GPIO_S0_SC_97
4 5 XDP_H_TDI BH8 PMC_PLT_CLK_2 / GPIO_S0_SC_98 B10 EC_RSMRST# EMC@
PMC_PLT_CLK_3 / GPIO_S0_SC_99 PMC_RSMRST# EC_RSMRST# 29
3 6 XDP_H_TMS BH6 B7 PMC_CORE_PWROK C1155 1 2 .1U_0402_16V7K
2 7 XDP_H_TCK BJ9 PMC_PLT_CLK_4 / GPIO_S0_SC_100 PMC_CORE_PWROK
PMC_PLT_CLK_5 / GPIO_S0_SC_101 +1.0VS
1 8 XDP_H_TRST# RTC domain
C9 ILB_RTC_X1
51_0804_8P4R_5% XDP_H_TCK D14 ILB_RTC_X1 A9 ILB_RTC_X2 RP55
TAP_TCK ILB_RTC_X2

1
XDP_H_TRST# G12 B8 ILB_RTC_EXTPAD 1 2 1 8
C XDP_H_TMS F14 TAP_TRST# ILB_RTC_EXTPAD P22 C1008 R1064 PMC_SLP_S4# 2 7 EC_SLP_S4# C
XDP_H_TDI F12 TAP_TMS RTC_VCC_P22 .1U_0402_16V7K 73.2_0402_1% SOC_KBRST# 3 6 EC_KBRST#
TAP_TDI +RTCVCC
XDP_H_TDO G16 SOC_LID_OUT#4 5 EC_LID_OUT#
XDP_H_PRDY# D18 TAP_TDO

2
XDP_H_PREQ_BUF# F16 TAP_PRDY# B24 VR_SVID_ALERT#_SOC R1065 1 2 20_0402_1% 0_0804_8P4R_5%
TAP_PREQ# SVID_ALERT# VR_SVID_ALERT# 40
AT34 A25 VR_SVID_DATA_SOC R1066 1 2 16.9_0402_1% 9022@
RESERVED_AT34 SVID_DATA VR_SVID_DATA 40
C25 RP56
SVID_CLK VR_SVID_CLK 40
SOC_SPI_CS0# C23 1 8
@ T193
@T193 C21 PCU_SPI_CS_0# SOC_SMI# 2 7 EC_SMI#
SOC_SPI_MISO B22 PCU_SPI_CS_1# / GPIO_S5_21 AU32 SOC_SCI# 3 6 EC_SCI#
SOC_SPI_MOSI A21 PCU_SPI_MISO SIO_PWM_0 / GPIO_S0_SC_94 AT32 PMC_PWRBTN# 4 5 PBTN_OUT#
SOC_SPI_CLK C22 PCU_SPI_MOSI SIO_PWM_1 / GPIO_S0_SC_95
PCU_SPI_CLK 0_0804_8P4R_5%
ILB_RTC_X1 9022@
SOC_KBRST# B18 ILB_RTC_X2 +1.8VALW +3VALW_EC
0_0402_5%1 TSI@ 2 R1016 TS_INT#_CPU B16 GPIO_S5_0 K24 1 2 U54 9012@
22 TS_INT_R# GPIO_S5_1 / PMC_WAKE_PCIE_1 GPIO_S5_22
0_0402_5%1 RS@ 2 R1015 TP_INT#_CPU C18 N24 R994 2 19
30 TP_INT# GPIO_S5_2 / PMC_WAKE_PCIE_2 GPIO_S5_23 VCCA VCCB
A17 M20 10M_0402_5%
SOC_LID_OUT# C17 GPIO_S5_3 / PMC_WAKE_PCIE_3 GPIO_S5_24 J18 PMC_SLP_S3# 1 20
GPIO_S5_4 GPIO_S5_25 A1 B1 EC_SLP_S3# 29
C16 M18 32.768KHZ_12.5PF_Q13FC135000040 PMC_SLP_S4# 3 18
GPIO_S5_5 / PMU_SUSCLK_1 GPIO_S5_26 A2 B2 EC_SLP_S4# 29
B14 K18 Y8 1 2 SOC_KBRST# 4 17
GPIO_S5_6 / PMU_SUSCLK_2 GPIO_S5_27 A3 B3 EC_KBRST# 29
SOC_SMI# C15 K20 SOC_LID_OUT# 5 16
GPIO_S5_7 / PMU_SUSCLK_3 GPIO_S5_28 A4 B4 EC_LID_OUT# 29
M22 1 1 SOC_SERIRQ 6 15
GPIO_S5_29 9 SOC_SERIRQ A5 B5 EC_SERIRQ 29,30
M24 SOC_SMI# 7 14
GPIO_S5_30 A6 B6 EC_SMI# 29
C1009 C1010 SOC_SCI# 8 13
7 SOC_SCI# A7 B7 EC_SCI# 29
C13 18P_0402_50V8J 18P_0402_50V8J PMC_PWRBTN# 9 12
GPIO_S5_8 2 2 A8 B8 PBTN_OUT# 29
A13
C19 GPIO_S5_9 AV32 LS_OE 10 11
GPIO_S5_10 SIO_SPI_CS# / GPIO_S0_SC_66 BA28 OE GND
SIO_SPI_MISO / GPIO_S0_SC_67 AY28 TXB0108PWR_TSSOP20
GPIO_RCOMP N26 SIO_SPI_MOSI / GPIO_S0_SC_68 AY30
GPIO_RCOMP 5 OF 13 SIO_SPI_CLK / GPIO_S0_SC_69
2

B B
R995 FH8065301546401_FCBGA131170 SOC_SERIRQ R1021 2 NTPM@ 1 0_0402_5% EC_SERIRQ
49.9_0402_1% B0@
PMC_SLP_S3# R1025 2 NTPM@ 1 0_0402_5% EC_SLP_S3#
1

+1.8VALW +3VALW_EC
U71 TPM@ +1.8VALW
1 6
2 VCCA VCCB 5
SOC_SERIRQ 3 GND EO 4 EC_SERIRQ +1.8VALW
A4 B4
G2129TL1U_SC70-6
+BIOS_SPI

2
+BIOS_SPI +1.8VALW +RTCVCC
R999 1 2 3.3K_0402_5% SPI_CS0# RS@ R1034
R998 2 1 0_0402_5% R996 10K_0402_5%

2
G
R1001 1 2 3.3K_0402_5% SPI_WP# 20K_0402_1% TPM@
C1013 2 1 .1U_0402_16V7K RTC_TEST# 2 1

1
R1000 1 2 3.3K_0402_5% SPI_HOLD# PMC_SLP_S3# 3 1 EC_SLP_S3#
RTC_RST# 2 1

D
2 1 R997 20K_0402_1% TPM@ Q83
From EC MESS138W-G_SOT323-3

SPI ROM ( 8MByte ) 1.8V

C1011 C1012 +RTCBATT +CHGRTC W=20mils
(For share ROM) RP53
+BIOS_SPI
1U_0402_6.3V6K
1 2
1U_0402_6.3V6K D22
+RTCVCC +1.35VS
2
EC_SPICS# 1 8 SPI_CS0# U56 W=10mil
29 EC_SPICS#

1
EC_MISO 2 7 SPI_MISO SPI_CS0# 1 8 1 +3VALW
29 EC_MISO CS# VCC
EC_MOSI 3 6 SPI_MOSI SPI_MISO 2 7 SPI_HOLD# W=20mils R993
29 EC_MOSI DO(IO1) HOLD#(IO3)
EC_SPICLK 4 5 SPI_CLK SPI_WP# 3 6 SPI_CLK 3 10K_0402_5%
29 EC_SPICLK WP#(IO2) CLK

5
4 5 SPI_MOSI RTC_TEST# 2 RS@ 1 CLR_CMOS# CLR_CMOS# 29 1 U55
GND DI(IO0)
22_0804_8P4R_5% 0_0402_5% R1088 BAS40-04_SOT23-3 3.3V 1 1.35V

2
A EMC@ W25Q64DWSSIG_SO8 RTC_RST# 2 @ 1 C151 NC 4 A
Y DDR_CORE_PWROK 5
1

0_0402_5% R1089 @ .1U_0402_16V7K 2

29 PMC_CORE_PWROK A

G
RP48 JCMOS1 2
From CPU SOC_SPI_CS0# 4 5 SPI_CS0# Clear CMOS SHORT PADS NL17SZ07DFT2G_SC70-5
2

3
SOC_SPI_MISO 3 6 SPI_MISO Close to RAM door SA00004BV00
SOC_SPI_MOSI 2 7 SPI_MOSI
SOC_SPI_CLK 1 8 SPI_CLK Reserve for EMI(Near SPI ROM)
22_0804_8P4R_5% Security Classification Compal Secret Data Compal Electronics, Inc.
EMC@ SPI_CLK 1 2 2 1 2014/03/19 2015/03/18 Title
@EMC@ R1002 @EMC@ C1014
Issued Date Deciphered Date VLV-M SOC CLK/PMU/SPI
33_0402_5% 10P_0402_50V8J
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A5WAM_Bay Trail M_LA‐B981P
Date: Monday, May 12, 2014 Sheet 8 of 47
5 4 3 2 1
 5 4 3 2 1

N15V‐GL/GM GPIO
GPIO_S0_SC_59 +1.8VS

N15V‐GL H

1
USOC1F
R1036
PVT modify G2 M10 N15V‐GM L 1K_0402_5%
GPIO_S5_31 RESERVED_M10 M9
RESERVED_M9 VGL@

2
D DGPU_PWR_EN_SOC1.8V R1173 1 @ 2 0_0402_5% GPIO_S5_SC_32 M3 P6 GPIO_S0_SC_59 D
PH at dGPU side 32 DGPU_PWR_EN_SOC1.8V GPIO_S5_32 RESERVED_P6
DGPU_HOLD_RST#_SOC1.8V R1174 1 VGA@ 2 0_0402_5% GPIO_S5_SC_33 L1 P7
15,7 DGPU_HOLD_RST#_SOC1.8V GPIO_S5_33 RESERVED_P7

1
PH at dGPU side K2
K3 GPIO_S5_34 R1003 R1037
M2 GPIO_S5_35 M7 1.24K_0402_1%
GPIO_S5_36 RESERVED_M7 10K_0402_5%
N3 M12 USB3_REXT0 1 2 VGM@
P2 GPIO_S5_37 USB3_REXT0

2
L3 GPIO_S5_38 P10
GPIO_S5_39 RESERVED_P10 P12
RESERVED_P12
M4
J3 RESERVED_M4 M6
P3 GPIO_S5_40 RESERVED_M6
H3 GPIO_S5_41 D4
GPIO_S5_42 USB3_RXP0 PCH_USB3_RX0_P 28
B12 E3 PCH_USB3_RX0_N 28
GPIO_S5_43 USB3_RXN0
K6
USB3 Port 0
USB3_TXP0 PCH_USB3_TX0_P 28
M16 K7
28 USB20_P0 USB_DP0 USB3_TXN0 PCH_USB3_TX0_N 28
USB3.0 Port K16
28 USB20_N0 USB_DN0
J14
28 USB20_P1 USB_DP1
USB Hub G14
28 USB20_N1 USB_DN1
K12
Touch Panel
22 USB20_P2
J12 USB_DP2 BIOS/EFI Top Swap
22 USB20_N2 USB_DN2
K10
22 USB20_P3 USB_DP3 +1.8VS
Camera H10 H8
+1.8VALW 22 USB20_N3 USB_DN3 RESERVED_H8 H7
RESERVED_H7

1
R1007 1 2 10K_0402_5% USB_OC0# 1K_0402_1% 1 2 R1004 ICLK_USB_TERMP D10
R1009 1 2 10K_0402_5% USB_OC1# 1K_0402_1% 1 2 R1005 ICLK_USB_TERMN F10 ICLK_USB_TERMP H4 R1006
C ICLK_USB_TERMN RESERVED_H4 H5 C
RESERVED_H5 10K_0402_5%
@
C20
28 USB_OC0#

2
USB_OC1# B20 USB_OC_0# / GPIO_S5_19 GPIO_S0_SC_56
USB_OC_1# / GPIO_S5_20

1
R1011
R1008 1 2 USB_RCOMP D6 BD12 10K_0402_5%
45.3_0402_1% C7 USB_RCOMPO GPIO_S0_SC_55 BC12 GPIO_S0_SC_56 @
USB_RCOMPI GPIO_S0_SC_56 BD14 DBG_UART_TXD T203@

2
GPIO_S0_SC_57 / PCU_UART_TXD BC14
@EMC@ R1010 1 @ 2 USB_PLL_MON M13 GPIO_S0_SC_58 BF14 GPIO_S0_SC_59
C1015 2 1 10P_0402_50V8J LPC_CLK_0 0_0402_5% USB_PLL_MON GPIO_S0_SC_59 BD16
GPIO_S0_SC_60 BC16 DBG_UART_RXD T204@
GPIO_S0_SC_61 / PCU_UART_RXD GPIO_S0_SC_56: Top Swap( A16 Override )
B4
USB_HSIC0_DATA
0 = Top address bit is unchanged
B5 BH12 SOC_SPKR
USB_HSIC0_STROBE ILB_8254_SPKR / GPIO_S0_SC_54 SOC_SPKR 31 1 = Top address bit is inverted
Reference EDS2.0 Page 51
E2
D2 USB_HSIC1_DATA
NOTE: Ref checklist rev1.2 p.25 USB_HSIC1_STROBE BH22
USB_HSIC_RCOMP must NOT float if they are not being used. SIO_I2C0_DATA / GPIO_S0_SC_78 BG23
1 2 HSIC_RCOMP A7 SIO_I2C0_CLK / GPIO_S0_SC_79
R1012 45.3_0402_1% USB_HSIC_RCOMP
BG24 For Touch Screen
SIO_I2C1_DATA / GPIO_S0_SC_80 BH24 +1.8VS
49.9_0402_1%1 2 R1013 LPC_RCOMP BF18 SIO_I2C1_CLK / GPIO_S0_SC_81
+1.8VS BH16 LPC_RCOMP / VGA_RCOMP SOC_I2C5_DATA R1143 1 TSI@ 2 2.2K_0402_5%
29,30 LPC_AD0 ILB_LPC_AD_0 / GPIO_S0_SC_42
RP49 BJ17 BG25 SOC_I2C2_DATA
29,30 LPC_AD1 ILB_LPC_AD_1 / GPIO_S0_SC_43 SIO_I2C2_DATA / GPIO_S0_SC_82
5 4 PCU_SMB_CLK BJ13 BJ25 SOC_I2C2_CLK SOC_I2C5_CLK R1144 1 TSI@ 2 2.2K_0402_5%
29,30 LPC_AD2 ILB_LPC_AD_2 / GPIO_S0_SC_44 SIO_I2C2_CLK / GPIO_S0_SC_83
6 3 PCU_SMB_DATA BG14
B 29,30 LPC_AD3 ILB_LPC_AD_3 / GPIO_S0_SC_45 +1.8VS B
7 2 PCU_SMB_ALERT# BG17
29,30 LPC_FRAME# ILB_LPC_FRAME# / GPIO_S0_SC_46
8 1 22_0402_5% 1 EMC@ 2 R1014 LPC_CLK_0 BG15 BG26
29 LPC_CLK_EC ILB_LPC_CLK_0 / GPIO_S0_SC_47 SIO_I2C3_DATA / GPIO_S0_SC_84
22_0402_5% 1 TPM@ 2 R1017 LPC_CLK_1 BH14 BH26
30 LPC_CLK_TPM ILB_LPC_CLK_1 / GPIO_S0_SC_48 SIO_I2C3_CLK / GPIO_S0_SC_85
4.7K_0804_8P4R_5% BG16
30 LPC_CLKRUN# ILB_LPC_CLKRUN# / GPIO_S0_SC_49

5
BG13
+1.8VS 8 SOC_SERIRQ ILB_LPC_SERIRQ / GPIO_S0_SC_50 BF27 TSI@

G
SIO_I2C4_DATA / GPIO_S0_SC_86 BG27 SOC_I2C5_DATA 4 3
SIO_I2C4_CLK / GPIO_S0_SC_87 I2C5_SDA_PNL 22

D
Q80A

2
DMN63D8LDW-7_SOT363-6
5

Pull High at EC side BH28 SOC_I2C5_DATA TSI@

G
PCU_SMB_DATA BG12 SIO_I2C5_DATA / GPIO_S0_SC_88 BG28 SOC_I2C5_CLK SOC_I2C5_CLK 1 6
G

PCU_SMB_DATA / GPIO_S0_SC_51 SIO_I2C5_CLK / GPIO_S0_SC_89 I2C5_SCL_PNL 22

D
3 4 PCU_SMB_CLK PCU_SMB_CLK BH10 Q80B
13,14,15,26,29 EC_SMB_CK2 PCU_SMB_CLK / GPIO_S0_SC_52
D

Q79A PCU_SMB_ALERT# BG11 DMN63D8LDW-7_SOT363-6

PCU_SMB_ALERT# / GPIO_S0_SC_53
2

DMN63D8LDW-7_SOT363-6 BJ29
SIO_I2C6_DATA / GPIO_S0_SC_90 BG29
G

6 1 PCU_SMB_DATA SIO_I2C6_CLK / GPIO_S0_SC_91 / SD3_WP

13,14,15,26,29 EC_SMB_DA2
D

ILB_LPC_CLK_0 : Output of 25MHz,

Q79B BH30 GPIO_S0_SC_92
DMN63D8LDW-7_SOT363-6 Need Check with EC GPIO_S0_SC_092 BG30 GPIO_S0_SC_93 T202@ For Touch Pad
6 OF 13 GPIO_S0_SC_093 +1.8VS
ILB_LPC_CLK_1 is for CLK_0 feedback.(Input)
FH8065301546401_FCBGA131170 SOC_I2C2_DATA R1153 1 2 2.2K_0402_5%
Set to Output for Normal Usage B0@
SOC_I2C2_CLK R1152 1 2 2.2K_0402_5%

+1.8VS

PVT modify

5
PH at dGPU side DGPU_PWR_EN_SOC1.8V R1176 1 VGA@ 2 0_0402_5% GPIO_S0_SC_92

G
SOC_I2C2_DATA 4 3
I2C2_SDA_TP 30

D
A Q81A A

2
DMN63D8LDW-7_SOT363-6

G
SOC_I2C2_CLK 1 6
I2C2_SCL_TP 30

D
Q81B
DMN63D8LDW-7_SOT363-6

Security Classification Compal Secret Data Compal Electronics, Inc.

2014/03/19 2015/03/18 Title
Issued Date Deciphered Date VLV-M SOC USB/LPC/SMBus
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A5WAM_Bay Trail M_LA‐B981P
Date: Monday, May 12, 2014 Sheet 9 of 47
5 4 3 2 1
 5 4 3 2 1

D D

+1.35V_SOC +1.35V_L

12A +SOC_VCC USOC1G 20mil @EMC@ L61

AA27 AD38 2 1
AA29 CORE_VCC_S0IX_AA27 DRAM_VDD_S4_AD38 AF38 HCB2012KF-121T50_2P
AA30 CORE_VCC_S0IX_AA29 DRAM_VDD_S4_AF38
AC27 CORE_VCC_S0IX_AA30 A48 C1017 1 2 1U_0402_6.3V6K @EMC@ L62
AC29 CORE_VCC_S0IX_AC27 DRAM_VDD_S4_A48 AK38 C1018 1 2 .1U_0402_16V7K 2 1
AC30 CORE_VCC_S0IX_AC29 DRAM_VDD_S4_AK38 AM38 HCB2012KF-121T50_2P
CORE_VCC_S0IX_AC30 DRAM_VDD_S4_AM38 AV41
DRAM_VDD_S4_AV41
AD27
CORE_VCC_S0IX_AD27 DRAM_VDD_S4_AV42
AV42 1250mA @EMC@ L63
AD29 BB46 2 1
AD30 CORE_VCC_S0IX_AD29 DRAM_VDD_S4_BB46 BD49 HCB2012KF-121T50_2P
AF27 CORE_VCC_S0IX_AD30 DRAM_VDD_S4_BD49 BD52
C AF29 CORE_VCC_S0IX_AF27 DRAM_VDD_S4_BD52 BD53 JP3 JP@ C
AG27 CORE_VCC_S0IX_AF29 DRAM_VDD_S4_BD53 BF44
AG29 CORE_VCC_S0IX_AG27 DRAM_VDD_S4_BF44 BG51
AG30 CORE_VCC_S0IX_AG29 DRAM_VDD_S4_BG51 BJ48 C1019 2 1 2.2U_0402_6.3V6M JUMP_43X118
P26 CORE_VCC_S0IX_AG30 DRAM_VDD_S4_BJ48 C51 C1020 2 1 2.2U_0402_6.3V6M
P27 CORE_VCC_S0IX_P26 DRAM_VDD_S4_C51 D44 C1021 2 1 2.2U_0402_6.3V6M
U27 CORE_VCC_S0IX_P27 DRAM_VDD_S4_D44 F49 C1022 2 1 2.2U_0402_6.3V6M
JP3 short
U29 CORE_VCC_S0IX_U27 DRAM_VDD_S4_F49 F52
V27 CORE_VCC_S0IX_U29 DRAM_VDD_S4_F52 F53
V29 CORE_VCC_S0IX_V27 DRAM_VDD_S4_F53 H46
V30 CORE_VCC_S0IX_V29 DRAM_VDD_S4_H46 M41
Y27 CORE_VCC_S0IX_V30 DRAM_VDD_S4_M41 M42 C1147 1 2 10U_0603_6.3V6M
Y29 CORE_VCC_S0IX_Y27 DRAM_VDD_S4_M42 V38 C1148 1 2 10U_0603_6.3V6M
Y30 CORE_VCC_S0IX_Y29 DRAM_VDD_S4_V38 Y38
CORE_VCC_S0IX_Y30 DRAM_VDD_S4_Y38

@ T194 TP2_CORE_VCC_S0iX AA22

TP2_CORE_VCC_S0IX
0715 Add for CRT flicker
+3VALW
14A +SOC_VNN +1.35VS U65
420mA VGA_V1P35_S3_F1 5
OUT IN
1
AM22 AG18
UNCORE_VNN_S3_AM22 ICLK_V1P35_S3_F2_AG18

1
AK32 AJ19 2 1
AK30 UNCORE_VNN_S3_AK32 ICLK_V1P35_S3_F1_AJ19 GND
AK29 UNCORE_VNN_S3_AK30 R1084 4 3 C1179
AK27 UNCORE_VNN_S3_AK29 BD1 VGA_V1P35_S3_F1 C1023 1 2 10U_0603_6.3V6M 8.06K_0402_1% BYP SHDN
UNCORE_VNN_S3_AK27 VGA_V1P35_S3_F1_BD1 1U_0402_6.3V6K
AK25 G916T1UF_SOT23-5 2

2
AK24 UNCORE_VNN_S3_AK25
AK22 UNCORE_VNN_S3_AK24
UNCORE_VNN_S3_AK22

1
AJ24 AD36
AJ22 UNCORE_VNN_S3_AJ24 DRAM_V1P35_S0IX_F1_AD36
+SOC_VNN +SOC_VCC AG24 UNCORE_VNN_S3_AJ22 AG32 R1085
AG22 UNCORE_VNN_S3_AG24 UNCORE_V1P35_S0IX_F2_AG32 V36 100K_0402_1%
B AF24 UNCORE_VNN_S3_AG22 UNCORE_V1P35_S0IX_F3_V36 U36 B

2
AF22 UNCORE_VNN_S3_AF24 UNCORE_V1P35_S0IX_F4_U36
UNCORE_VNN_S3_AF22
1

AD22 AA25
AC24 UNCORE_VNN_S3_AD22 UNCORE_V1P35_S0IX_F5_AA25
R1018 R1019 AC22 UNCORE_VNN_S3_AC24 2 1
UNCORE_VNN_S3_AC22 29,32,37,38,39 SUSP#
100_0402_1% 100_0402_1% AA24 R1087 1
AD24 UNCORE_VNN_S3_AA24 36K_0402_5%
2

UNCORE_VNN_S3_AD24 C1181
AF19 C1024 1 2 22U_0805_6.3V6M .1U_0402_16V7K
UNCORE_V1P35_S0IX_F6_AF19 2
40 VGFX_VSNS
BB8
UNCORE_VNN_SENSE UNCORE_V1P35_S0IX_F1_AG19
AG19 C1025 1 2 1U_0402_6.3V6K VOUT = 1.25 (1 + R1/R2).
P28 C1026 1 2 1U_0402_6.3V6K
40 VCORE_VSNS CORE_VCC_SENSE_P28 7 OF 13
N28 C1027 1 2 1U_0402_6.3V6K
40 VCORE_GSNS CORE_VSS_SENSE_N28 C1028 1 2 1U_0402_6.3V6K
1

C1029 1 2 1U_0402_6.3V6K
FH8065301546401_FCBGA131170 C1030 1 2 1U_0402_6.3V6K
R1020 C1031 1 2 1U_0402_6.3V6K
100_0402_1% B0@ C1032 1 2 1U_0402_6.3V6K
C1033 1 2 1U_0402_6.3V6K
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

2014/03/19 2015/03/18 Title
Issued Date Deciphered Date VLV-M SOC Power
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A5WAM_Bay Trail M_LA‐B981P
Date: Monday, May 12, 2014 Sheet 10 of 47
5 4 3 2 1
 5 4 3 2 1

D D

Follow CRBv1.15
USOC1H +1.05VS
325mA 1000mA
+1.0VALW U22 AC32
V22 UNCORE_V1P0_G3_U22 CORE_V1P0_S3_AC32 Y32
C1034 1 2 1U_0402_6.3V6K C5 UNCORE_V1P0_G3_V22 CORE_V1P0_S3_Y32
UNCORE_V1P0_G3 1uF*4 C1035 1 2 1U_0402_6.3V6K B6 UNCORE_V1P0_G3_C5 AA33
C1036 1 2 1U_0402_6.3V6K UNCORE_V1P0_G3_B6 CORE_V1P05_S3_AA33 AF33
C1037 1 2 1U_0402_6.3V6K Y19 CORE_V1P05_S3_AF33 AG33 C1038 1 2 0.47U_0402_6.3V6K
C3 USB3_V1P0_G3_Y19 CORE_V1P05_S3_AG33 AG35
USB3_V1P0_G3 0.01uF*1 C1039 1 2 0.01U_0402_16V7K USB3_V1P0_G3_C3 CORE_V1P05_S3_AG35 U33 C1040 1 2 1U_0402_6.3V6K
CORE_V1P05_S3_U33 U35 C1041 1 2 1U_0402_6.3V6K CORE_V1P05_S3 1uF*3
CORE_V1P05_S3_U35
2750mA CORE_V1P05_S3_V33
V33 C1042 1 2 1U_0402_6.3V6K
+1.0VS V32
BJ6 SVID_V1P0_S3_V32 +1.8VALW
C AD35 VGA_V1P0_S3_BJ6 C
AF35 DRAM_V1P0_S0IX_AD35 U24
C1043 1 2 1U_0402_6.3V6K AF36 DRAM_V1P0_S0IX_AF35 UNCORE_V1P8_G3_U24 V25
C1044 1 2 1U_0402_6.3V6K AA36 DRAM_V1P0_S0IX_AF36 PCU_V1P8_G3_V25 N20 C1045 1 2 1U_0402_6.3V6K PMC_V1P8_G3 1uF*1
DRAM_V1P0_S0iX 1uF*4 DRAM_V1P0_S0IX_AA36 USB_V1P8_G3_N20
C1046 1 2 1U_0402_6.3V6K AJ36
DRAM_V1P0_S0IX_AJ36
65mA PMU_V1P8_G3_U25 U25
C1047 1 2 1U_0402_6.3V6K AK35 AA18
AK36 DRAM_V1P0_S0IX_AK35 UNCORE_V1P8_G3_AA18
Y35 DRAM_V1P0_S0IX_AK36 +1.8VS
DRAM_V1P0_S0IX_Y35
C1048 1 2 1U_0402_6.3V6K Y36
DRAM_V1P0_S0IX_Y36
10mA
C1049 1 2 1U_0402_6.3V6K AK19 AM30
DDI_V1P0_S0iX 1uF*4 C1050 1 2 1U_0402_6.3V6K AK21 DDI_V1P0_S0IX_AK19 UNCORE_V1P8_S3_AM30 AN32 C1051 1 2 1U_0402_6.3V6K UNCORE_V1P8_S3 1uF*4
C1052 1 2 1U_0402_6.3V6K AJ18 DDI_V1P0_S0IX_AK21 UNCORE_V1P8_S3_AN32 U38 C1053 1 2 1U_0402_6.3V6K
AM16 DDI_V1P0_S0IX_AJ18 UNCORE_V1P8_S3_U38 C1054 1 2 1U_0402_6.3V6K
AN29 DDI_V1P0_S0IX_AM16 C1055 1 2 1U_0402_6.3V6K +1.5VS
VIS_V1P0_S0IX_AN29
AN30
VIS_V1P0_S0IX_AN30
58mA
C1056 1 2 22U_0603_6.3V6M V24 AM32
UNCORE_V1P0_S0iX 22uF*3 C1057 1 2 22U_0603_6.3V6M Y22 VIS_V1P0_S0IX_V24 HDA_V1P5_S3_AM32 C1058 1 2 1U_0402_6.3V6K HDA_LPE_V1P5V1P8_S3 1uF*1
1uF*2 C1059 1 2 22U_0603_6.3V6M Y24 VIS_V1P0_S0IX_Y22 +3VALW
C1060 1 2 1U_0402_6.3V6K AF16 VIS_V1P0_S0IX_Y24
C1061 1 2 1U_0402_6.3V6K AF18 UNCORE_V1P0_S3_AF16 N22 +3VALW_SOC 2 RS@ 1
UNCORE_V1P0_S3_AF18
Y18
UNCORE_V1P0_S3_Y18
50mA PCU_V3P3_G3_N22 R1022 0_0402_5%
PCIE_SATA_V1P0_S3 1uF*1 C1062 1 2 1U_0402_6.3V6K G1 N18 C1063 1 2 .1U_0402_16V7K USB_V3P3_G3 0.1uF*1
UNCORE_V1P0_S3 1uF*1 C1064 1 2 1U_0402_6.3V6K AK18 UNCORE_V1P0_S3_G1 USB_V3P3_G3_N18 P18 C1065 1 2 1U_0402_6.3V6K USB_ULPI_V1P8_S3 1uF*1
PCIE_V1P0_S3 1uF*1 C1066 1 2 1U_0402_6.3V6K AM18 PCIE_V1P0_S3_AK18 USB_V3P3_G3_P18 C1067 1 2 1U_0402_6.3V6K PCU_V3P3_G3 1uF*1
VGA_V1P0_S3 1uF*1 C1068 1 2 1U_0402_6.3V6K AM21 PCIE_V1P0_S3_AM18 +3VS
USB_V1P0_S3 0.1uF*1 PCIE_V1P0_S3_AM21
C1069 1 2 .1U_0402_16V7K AN21
PCIE_V1P0_S3_AN21
33mA
USB3DEV_V1P0_S3 0.01uF*1 C1070 1 2 0.01U_0402_16V7K AN18 AN24 +3VS_SOC 2 RS@ 1
GPIO_V1P0_S3 1uF*1 C1071 1 2 1U_0402_6.3V6K AN19 PCIE_SATA_V1P0_S3_AN18 VGA_V3P3_S3_AN24 R1023 0_0402_5% VGA_V3P3_S3 1uF*1
SVID_V1P0_S3 1uF*1 C1072 1 2 1U_0402_6.3V6K AF21 SATA_V1P0_S3_AN19 AN27 1 2 +3VS
AG21 UNCORE_V1P0_S0IX_AF21 SD3_V1P8V3P3_S3_AN27 C1073 1U_0402_6.3V6K
M14 UNCORE_V1P0_S0IX_AG21 AM27 +1.8VS_3.3VS LPC 2 TPM@ 1 +1.8VS
U18 USB_V1P0_S3_M14 LPC_V1P8V3P3_S3_AM27 R1031 0_0402_5%
B U19 USB_V1P0_S3_U18 2 NTPM@ 1 B
USB_V1P0_S3_U19
AN25
GPIO_V1P0_S3_AN25
35mA R1032 0_0402_5%
V18 1 2
USB_HSIC_V1P2_G3_V18 C1075 1U_0402_6.3V6K +1.0VALW
USB_HSIC_V1P2_G3 1uF*1
F1
RESERVED_F1 VSS_AD16
AD16 C1074 1 2 1U_0402_6.3V6K Disable HSIC
AD18 @
T195 TP_CORE_V1P05_S4 AF30 VSS_AD18
Pop when use +1.2VALW If the USB HSIC is not used, pin V18 can be connected
TP_CORE_V1P05_S4_AF30
@ to either +V1P2A or +V1P0A.
8 OF 13
FH8065301546401_FCBGA131170

B0@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/03/19 Deciphered Date 2015/03/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VLV-M SOC Power
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A5WAM_Bay Trail M_LA‐B981P
Date: Monday, May 12, 2014 Sheet 11 of 47
5 4 3 2 1
 5 4 3 2 1

D D

C C
USOC1I USOC1J USOC1K USOC1L USOC1M

A11 AC36 AG38 AH47 AT24 AY36 BF30 E8 K9 U3

A15 VSS_A11 VSS_AC36 AC38 AH4 VSS_AG38 VSS_AH47 AH48 AT27 VSS_AT24 VSS_AY36 AY4 BF36 VSS_BF30 VSS_E8 F19 L13 VSS_K9 VSS_U3 U30
A19 VSS_A15 VSS_AC38 AD19 AH41 VSS_AH4 VSS_AH48 AH50 AT30 VSS_AT27 VSS_AY4 AY50 BF4 VSS_BF36 VSS_F19 F2 L19 VSS_L13 VSS_U30 U32
A23 VSS_A19 VSS_AD19 AD21 AH45 VSS_AH41 VSS_AH50 AH51 AT35 VSS_AT30 VSS_AY50 AY9 BG31 VSS_BF4 VSS_F2 F24 L27 VSS_L19 VSS_U32 U40
A27 VSS_A23 VSS_AD21 AD25 AH7 VSS_AH45 VSS_AH51 AH6 AT38 VSS_AT35 VSS_AY9 BA14 BG34 VSS_BG31 VSS_F24 F27 L35 VSS_L27 VSS_U40 U42
A31 VSS_A27 VSS_AD25 AD32 AH9 VSS_AH7 VSS_AH6 AM44 AT4 VSS_AT38 VSS_BA14 BA19 BG39 VSS_BG34 VSS_F27 F30 M19 VSS_L35 VSS_U42 U43
A35 VSS_A31 VSS_AD32 AD33 AJ1 VSS_AH9 VSS_AM44 AM51 AT47 VSS_AT4 VSS_BA19 BA22 BG42 VSS_BG39 VSS_F30 F35 M26 VSS_M19 VSS_U43 U45
A39 VSS_A35 VSS_AD33 AD47 AJ16 VSS_AJ1 VSS_AM51 AM7 AT52 VSS_AT47 VSS_BA22 BA27 BG45 VSS_BG42 VSS_F35 F5 M27 VSS_M26 VSS_U45 U46
A43 VSS_A39 VSS_AD47 AD7 AJ21 VSS_AJ16 VSS_AM7 AN1 AU1 VSS_AT52 VSS_BA27 BA32 BG49 VSS_BG45 VSS_F5 F7 M34 VSS_M27 VSS_U46 U48
A47 VSS_A43 VSS_AD7 AE1 AJ25 VSS_AJ21 VSS_AN1 AN11 AU24 VSS_AU1 VSS_BA32 BA35 BJ11 VSS_BG49 VSS_F7 G10 M35 VSS_M34 VSS_U48 U49
AA1 VSS_A47 VSS_AE1 AE11 AJ27 VSS_AJ25 VSS_AN11 AN12 AU3 VSS_AU24 VSS_BA35 BA40 BJ15 VSS_BJ11 VSS_G10 G20 M38 VSS_M35 VSS_U49 U5
AA16 VSS_AA1 VSS_AE11 AE12 AJ29 VSS_AJ27 VSS_AN12 AN14 AU30 VSS_AU3 VSS_BA40 BA53 BJ19 VSS_BJ15 VSS_G20 G22 M47 VSS_M38 VSS_U5 U51
AA19 VSS_AA16 VSS_AE12 AE14 AJ3 VSS_AJ29 VSS_AN14 AN22 AU38 VSS_AU30 VSS_BA53 BB19 BJ23 VSS_BJ19 VSS_G22 G26 M51 VSS_M47 VSS_U51 U53
AA21 VSS_AA19 VSS_AE14 AE3 AJ30 VSS_AJ3 VSS_AN22 AN3 AU51 VSS_AU38 VSS_BB19 BB27 BJ27 VSS_BJ23 VSS_G26 G28 N1 VSS_M51 VSS_U53 U6
AA3 VSS_AA21 VSS_AE3 AE4 AJ32 VSS_AJ30 VSS_AN3 AN33 AV12 VSS_AU51 VSS_BB27 BB35 BJ31 VSS_BJ27 VSS_G28 G32 N16 VSS_N1 VSS_U6 U8
AA32 VSS_AA3 VSS_AE4 AE40 AJ33 VSS_AJ32 VSS_AN33 AN35 AV13 VSS_AV12 VSS_BB35 BC20 BJ35 VSS_BJ31 VSS_G32 G34 N38 VSS_N16 VSS_U8 U9
AA35 VSS_AA32 VSS_AE40 AE42 AJ35 VSS_AJ33 VSS_AN35 AN36 AV14 VSS_AV13 VSS_BC20 BC22 BJ39 VSS_BJ35 VSS_G34 G42 N51 VSS_N38 VSS_U9 V12
AA38 VSS_AA35 VSS_AE42 AE43 AJ38 VSS_AJ35 VSS_AN36 AN38 AV18 VSS_AV14 VSS_BC22 BC26 BJ43 VSS_BJ39 VSS_G42 H19 P13 VSS_N51 VSS_V12 V16
AA53 VSS_AA38 VSS_AE43 AE45 AJ53 VSS_AJ38 VSS_AN38 AN40 AV19 VSS_AV18 VSS_BC26 BC28 BJ47 VSS_BJ43 VSS_H19 H27 P16 VSS_P13 VSS_V16 V19
AB10 VSS_AA53 VSS_AE45 AE46 AK10 VSS_AJ53 VSS_AN40 AN42 AV24 VSS_AV19 VSS_BC28 BC32 BJ7 VSS_BJ47 VSS_H27 H35 P19 VSS_P16 VSS_V19 V21
AB4 VSS_AB10 VSS_AE46 AE48 AK14 VSS_AK10 VSS_AN42 AN43 AV27 VSS_AV24 VSS_BC32 BC34 C14 VSS_BJ7 VSS_H35 J1 P20 VSS_P19 VSS_V21 V35
AB41 VSS_AB4 VSS_AE48 AE50 AK16 VSS_AK14 VSS_AN43 AN45 AV30 VSS_AV27 VSS_BC34 BC42 C31 VSS_C14 VSS_J1 J16 P24 VSS_P20 VSS_V35 V40
AB45 VSS_AB41 VSS_AE50 AE51 AK33 VSS_AK16 VSS_AN45 AN46 AV35 VSS_AV30 VSS_BC42 BD19 C34 VSS_C31 VSS_J16 J19 P32 VSS_P24 VSS_V40 V44
AB47 VSS_AB45 VSS_AE51 AE53 AK41 VSS_AK33 VSS_AN46 AN48 AV38 VSS_AV35 VSS_BD19 BD24 C39 VSS_C34 VSS_J19 J22 P35 VSS_P32 VSS_V44 V51
AB48 VSS_AB47 VSS_AE53 AE6 AK44 VSS_AK41 VSS_AN48 AN49 AV47 VSS_AV38 VSS_BD24 BD27 C42 VSS_C39 VSS_J22 J27 P38 VSS_P35 VSS_V51 V7
AB50 VSS_AB48 VSS_AE6 AE8 AM12 VSS_AK44 VSS_AN49 AN5 AV51 VSS_AV47 VSS_BD27 BD30 C45 VSS_C42 VSS_J27 J32 P4 VSS_P38 VSS_V7 Y10
AB51 VSS_AB50 VSS_AE8 AE9 AM19 VSS_AM12 VSS_AN5 AN51 AV7 VSS_AV51 VSS_BD30 BD35 C49 VSS_C45 VSS_J32 J35 P47 VSS_P4 VSS_Y10 Y14
AB6 VSS_AB51 VSS_AE9 AF10 AM24 VSS_AM19 VSS_AN51 AN53 AW13 VSS_AV7 VSS_BD35 BE19 D12 VSS_C49 VSS_J35 J40 P52 VSS_P47 VSS_Y14 Y16
AC16 VSS_AB6 VSS_AF10 AF12 AM25 VSS_AM24 VSS_AN53 AN6 AW19 VSS_AW13 VSS_BE19 BE2 D16 VSS_D12 VSS_J40 J53 P9 VSS_P52 VSS_Y16 Y21
B AC18 VSS_AC16 VSS_AF12 AF25 AM29 VSS_AM25 VSS_AN6 AN8 AW27 VSS_AW19 VSS_BE2 BE35 D24 VSS_D16 VSS_J53 K14 T40 VSS_P9 VSS_Y21 Y25 B
AC19 VSS_AC18 VSS_AF25 AF32 AM33 VSS_AM29 VSS_AN8 AN9 AW3 VSS_AW27 VSS_BE35 BE8 D30 VSS_D24 VSS_K14 K22 U1 VSS_T40 VSS_Y25 Y33
AC21 VSS_AC19 VSS_AF32 AF47 AM35 VSS_AM33 VSS_AN9 AP40 AW35 VSS_AW3 VSS_BE8 BF12 D36 VSS_D30 VSS_K22 K32 U11 VSS_U1 VSS_Y33 Y41
AC25 VSS_AC21 VSS_AF47 AG16 AM36 VSS_AM35 VSS_AP40 AT12 AY10 VSS_AW35 VSS_BF12 BF16 D38 VSS_D36 VSS_K32 K36 U12 VSS_U11 VSS_Y41 Y44
AC33 VSS_AC25 VSS_AG16 AG25 AM40 VSS_AM36 VSS_AT12 AT16 AY22 VSS_AY10 VSS_BF16 BF24 E19 VSS_D38 VSS_K36 K4 U14 VSS_U12 VSS_Y44 Y7
AC35 VSS_AC33 VSS_AG25 AG36 M28 VSS_AM40 VSS_AT16 AT19 AY32 VSS_AY22 VSS_BF24 BF38 E35 VSS_E19 VSS_K4 K50 U21 VSS_U14 VSS_Y7 Y9
B2 VSS_AC35 9 OF 13VSS_AG36 B52 VSS_M28 10 OF 13 VSS_AT19 VSS_AY32 11 OF 13
VSS_BF38 VSS_E35 12 OF 13 VSS_K50 VSS_U21 13 OF 13 VSS_Y9
A6 VSS_B2 VSS_B52 B53
A52 VSS_A6 VSS_B53 BE1 FH8065301546401_FCBGA131170 FH8065301546401_FCBGA131170 FH8065301546401_FCBGA131170 FH8065301546401_FCBGA131170
A51 VSS_A52 VSS_BE1 BE53
A5 VSS_A51 VSS_BE53 BG1
VSS_A5 VSS_BG1 B0@ B0@ B0@ B0@
A49 BJ2
A3 VSS_A49 VSS_BJ2 BJ3
BH53 VSS_A3 VSS_BJ3 BJ5
BH52 VSS_BH53 VSS_BJ5 BJ49
BH2 VSS_BH52 VSS_BJ49 BJ51
BH1 VSS_BH2 VSS_BJ51 BJ52
BG53 VSS_BH1 VSS_BJ52 C1
E53 VSS_BG53 VSS_C1 C53
VSS_E53 VSS_C53 E1
VSS_E1
U16
AN16 USB_VSSA_U16
VSSA_AN16

FH8065301546401_FCBGA131170

B0@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

2014/03/19 2015/03/18 Title
Issued Date Deciphered Date VLV-M SOC GND
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A5WAM_Bay Trail M_LA‐B981P
Date: Monday, May 12, 2014 Sheet 12 of 47
5 4 3 2 1
 A B C D E

+DDR_A_VREF_DQ +1.35V_L CONN@ +1.35V_L

JDIMM1
1 2
3 VREF_DQ VSS 4 DDR_A_D4
VSS DQ4 DDR_A_DQS#[0..7] 5
DDR_A_D0 5 6 DDR_A_D5
DDR_A_D1 7 DQ0 DQ5 8
DQ1 VSS DDR_A_DQS[0..7] 5
9 10 DDR_A_DQS#0
DDR_A_DM0 11 VSS DQS0# 12 DDR_A_DQS0
DM0 DQS0 DDR_A_D[0..63] 5
13 14
DDR_A_D2 15 VSS VSS 16 DDR_A_D6
DQ2 DQ6 DDR_A_MA[0..15] 5
DDR_A_D3 17 18 DDR_A_D7
19 DQ3 DQ7 20
VSS VSS DDR_A_DM[0..7] 5
DDR_A_D8 21 22 DDR_A_D12
DDR_A_D9 23 DQ8 DQ12 24 DDR_A_D13
1 25 DQ9 DQ13 26 1
DDR_A_DQS#1 27 VSS VSS 28 DDR_A_DM1
DDR_A_DQS1 29 DQS1# DM1 30
DQS1 RESET# DDR_A_RST# 5
31 32
DDR_A_D10 33 VSS VSS 34 DDR_A_D14
DDR_A_D11 35 DQ10 DQ14 36 DDR_A_D15
37 DQ11 DQ15 38 EMC@
DDR_A_D16 39 VSS VSS 40 DDR_A_D20 DDR_A_RST# C1077 1 2.1U_0402_16V7K
DDR_A_D17 41 DQ16 DQ20 42 DDR_A_D21
43 DQ17 DQ21 44
DDR_A_DQS#2 45 VSS VSS 46 DDR_A_DM2
DDR_A_DQS2 47 DQS2# DM2 48 FOR EMI/ESD Require 01/15
49 DQS2 VSS 50 DDR_A_D22
DDR_A_D18 51 VSS DQ22 52 DDR_A_D23
DDR_A_D19 53 DQ18 DQ23 54
55 DQ19 VSS 56 DDR_A_D28
All VREF traces should DDR_A_D24 57 VSS DQ28 58 DDR_A_D29
have 10 mil trace width DDR_A_D25 59 DQ24 DQ29 60
61 DQ25 VSS 62 DDR_A_DQS#3
DDR_A_DM3 63 VSS DQS3# 64 DDR_A_DQS3
65 DM3 DQS3 66
VSS VSS
DDR_A_D26 67
DQ26 DQ30
68 DDR_A_D30 Signal voltage level = 0.675 V
DDR_A_D27 69 70 DDR_A_D31
71 DQ27 DQ31 72 PLACE TWO 4.7K RESISTORS CLOSE TO
VSS VSS
DIMMS ON DIMM_VREF_CA / DIMM_VREF_DQ
73 74 Decoupling caps are needed; one 0.1 µF placed close to VREF pins of each DDR3 SODIMM.
5 DDR_A_CKE0 CKE0 CKE1 DDR_A_CKE2 5
75 76
77 VDD VDD 78 DDR_A_MA15
79 NC A15 80 DDR_A_MA14
5 DDR_A_BS2 BA2 A14 +1.35V_L +DDR_A_VREF_DQ
81 82
DDR_A_MA12 83 VDD VDD 84 DDR_A_MA11
2 DDR_A_MA9 85 A12/BC# A11 86 DDR_A_MA7 1 2 +1.35V +1.35V_L 2
87 A9 A7 88 R1027
DDR_A_MA8 89 VDD VDD 90 DDR_A_MA6 4.7K_0402_1% L59 @EMC@
A8 A6 1
DDR_A_MA5 91 92 DDR_A_MA4 1 2 1 2
93 A5 A4 94 R1028 C1076 HCB2012KF-221T30_2P
DDR_A_MA3 95 VDD VDD 96 DDR_A_MA2 4.7K_0402_1%
A3 A2 .1U_0402_16V7K
DDR_A_MA1 97 98 DDR_A_MA0 2 L60 @EMC@
99 A1 A0 100 1 2
101 VDD VDD 102 HCB2012KF-221T30_2P
5 DDR_A_CLK0 CK0 CK1 DDR_A_CLK2 5
5 DDR_A_CLK0# 103 104 DDR_A_CLK2# 5
105 CK0# CK1# 106
DDR_A_MA10 107 VDD VDD 108 +1.35V_L +DDR_A_VREF_CA
A10/AP BA1 DDR_A_BS1 5
5 DDR_A_BS0 109 110 DDR_A_RAS# 5 JP5 JP@
111 BA0 RAS# 112 1 2
113 VDD VDD 114 R1029
5 DDR_A_WE# WE# S0# DDR_A_CS0# 5
5 DDR_A_CAS# 115 116 4.7K_0402_1% 1 JUMP_43X118
CAS# ODT0 DDR_A_ODT0 5
117 118 1 2
DDR_A_MA13 119 VDD VDD 120 R1030 C1078
121 A13 ODT1 122
DDR_A_ODT2 5
4.7K_0402_1%
JP5 short
5 DDR_A_CS2# S1# NC .1U_0402_16V7K
123 124 2
125 VDD VDD 126
TEST VREF_CA +DDR_A_VREF_CA
127 128
DDR_A_D32 129 VSS VSS 130 DDR_A_D36
DDR_A_D33 131 DQ32 DQ36 132 DDR_A_D37
133 DQ33 DQ37 134
DDR_A_DQS#4 135 VSS VSS 136 DDR_A_DM4
DDR_A_DQS4 137 DQS4# DM4 138
139 DQS4 VSS 140 DDR_A_D38
Layout Note:
DDR_A_D34 141 VSS DQ38 142 DDR_A_D39 Place near JDIMM1
DDR_A_D35 143 DQ34 DQ39 144
145 DQ35 VSS 146 DDR_A_D44
DDR_A_D40 147 VSS DQ44 148 DDR_A_D45
3 DDR_A_D41 149 DQ40 DQ45 150 +1.35V_L 3
151 DQ41 VSS 152 DDR_A_DQS#5 +1.35V
DDR_A_DM5 153 VSS DQS5# 154 DDR_A_DQS5 C111 1 2 10U_0603_6.3V6M
155 DM5 DQS5 156 C112 1 2 10U_0603_6.3V6M @EMC@
DDR_A_D42 157 VSS VSS 158 DDR_A_D46 C113 1 2 10U_0603_6.3V6M C167 1 2 .1U_0402_16V7K
DDR_A_D43 159 DQ42 DQ46 160 DDR_A_D47 C114 1 2 10U_0603_6.3V6M C166 1 2 .1U_0402_16V7K
161 DQ43 DQ47 162
DDR_A_D48 163 VSS VSS 164 DDR_A_D52 @EMC@
DDR_A_D49 165 DQ48 DQ52 166 DDR_A_D53 C110 1 2 .1U_0402_16V7K
167 DQ49 DQ53 168 C109 1 2 .1U_0402_16V7K
DDR_A_DQS#6 169 VSS VSS 170 DDR_A_DM6 C108 1 2 .1U_0402_16V7K
DDR_A_DQS6 171 DQS6# DM6 172 C107 1 2 .1U_0402_16V7K
173 DQS6 VSS 174 DDR_A_D54 C115 1 2 .1U_0402_16V7K
DDR_A_D50 175 VSS DQ54 176 DDR_A_D55 C116 1 2 .1U_0402_16V7K
DDR_A_D51 177 DQ50 DQ55 178 C117 1 2 .1U_0402_16V7K
179 DQ51 VSS 180 DDR_A_D60 C164 1 2 .1U_0402_16V7K
DDR_A_D56 181 VSS DQ60 182 DDR_A_D61
DDR_A_D57 183 DQ56 DQ61 184
185 DQ57 VSS 186 DDR_A_DQS#7
DDR_A_DM7 187 VSS DQS7# 188 DDR_A_DQS7
189 DM7 DQS7 190
DDR_A_D58 191 VSS VSS 192 DDR_A_D62
DDR_A_D59 193 DQ58 DQ62 194 DDR_A_D63 +0.675VS
195 DQ59 DQ63 196
197 VSS VSS 198 C123 1 2 10U_0603_6.3V6M
199 SA0 EVENT# 200
+3VS VDDSPD SDA EC_SMB_DA2 14,15,26,29,9
201 202
SA1 SCL EC_SMB_CK2 14,15,26,29,9
+0.675VS 203 204 +0.675VS C124 1 2 1U_0402_6.3V6K
VTT VTT C122 1 2 1U_0402_6.3V6K
RS@ RS@ 205 206
GND1 GND2
2

1 R211 R212 207 208

BOSS1 BOSS2
Channel A
0_0402_5%

0_0402_5%

4 C125 4
.1U_0402_16V7K LCN_DAN06-K4406-0100
2
Part Number = SP07000N300 Layout Note:
1

LCN_DAN06-K4406-0100_204P Place near JDIMM1.203,204

<Address: SA1:SA0=00 (A0H)> Security Classification Compal Secret Data Compal Electronics, Inc.
2014/03/19 2015/03/18 Title
Issued Date Deciphered Date DDR3L DIMMA
DIMM_1 STD H:4mm THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A5WAM_Bay Trail M_LA‐B981P
Date: Monday, May 12, 2014 Sheet 13 of 47
A B C D E
 A B C D E

+DDR_B_VREF_DQ +1.35V_L CONN@ +1.35V_L

JDIMM2
1 2
3 VREF_DQ VSS1 4 DDR_B_D4
VSS2 DQ4 DDR_B_DQS#[0..7] 5
DDR_B_D0 5 6 DDR_B_D5
DDR_B_D1 7 DQ0 DQ5 8
DQ1 VSS3 DDR_B_DQS[0..7] 5
9 10 DDR_B_DQS#0
DDR_B_DM0 11 VSS4 DQS#0 12 DDR_B_DQS0
DM0 DQS0 DDR_B_D[0..63] 5
13 14
DDR_B_D2 15 VSS5 VSS6 16 DDR_B_D6
DQ2 DQ6 DDR_B_MA[0..15] 5
DDR_B_D3 17 18 DDR_B_D7
19 DQ3 DQ7 20
VSS7 VSS8 DDR_B_DM[0..7] 5
DDR_B_D8 21 22 DDR_B_D12
DDR_B_D9 23 DQ8 DQ12 24 DDR_B_D13
1 25 DQ9 DQ13 26 1
DDR_B_DQS#1 27 VSS9 VSS10 28 DDR_B_DM1
DDR_B_DQS1 29 DQS#1 DM1 30
DQS1 RESET# DDR_B_RST# 5
31 32
DDR_B_D10 33 VSS11 VSS12 34 DDR_B_D14
DDR_B_D11 35 DQ10 DQ14 36 DDR_B_D15
37 DQ11 DQ15 38 DDR_B_RST# 1 2
DDR_B_D16 39 VSS13 VSS14 40 DDR_B_D20 C84
DDR_B_D17 41 DQ16 DQ20 42 DDR_B_D21 .1U_0402_16V7K
43 DQ17 DQ21 44
DDR_B_DQS#2 45 VSS15 VSS16 46 DDR_B_DM2 FOR EMI/ESD Require 01/15
DDR_B_DQS2 47 DQS#2 DM2 48
49 DQS2 VSS17 50 DDR_B_D22
DDR_B_D18 51 VSS18 DQ22 52 DDR_B_D23
DDR_B_D19 53 DQ18 DQ23 54
55 DQ19 VSS19 56 DDR_B_D28
All VREF traces should DDR_B_D24 57 VSS20 DQ28 58 DDR_B_D29 +1.35V_L +DDR_B_VREF_DQ
have 10 mil trace width DDR_B_D25 59 DQ24 DQ29 60
61 DQ25 VSS21 62 DDR_B_DQS#3 1 2
DDR_B_DM3 63 VSS22 DQS#3 64 DDR_B_DQS3 R1069
65 DM3 DQS3 66 4.7K_0402_1%
VSS23 VSS24 1
DDR_B_D26 67 68 DDR_B_D30 1 2
DDR_B_D27 69 DQ26 DQ30 70 DDR_B_D31 R1067 C128
71 DQ27 DQ31 72 4.7K_0402_1%
VSS25 VSS26 .1U_0402_16V7K
2

5 DDR_B_CKE0 73 74 DDR_B_CKE2 5
75 CKE0 CKE1 76
77 VDD1 VDD2 78 DDR_B_MA15 +1.35V_L +DDR_B_VREF_CA
79 NC1 A15 80 DDR_B_MA14
5 DDR_B_BS2 BA2 A14
81 82 1 2
2 DDR_B_MA12 83 VDD3 VDD4 84 DDR_B_MA11 R1070 2
DDR_B_MA9 85 A12/BC# A11 86 DDR_B_MA7 4.7K_0402_1%
A9 A7 1
87 88 1 2
DDR_B_MA8 89 VDD5 VDD6 90 DDR_B_MA6 R1068 C142
DDR_B_MA5 91 A8 A6 92 DDR_B_MA4 4.7K_0402_1%
A5 A4 .1U_0402_16V7K
93 94 2
DDR_B_MA3 95 VDD7 VDD8 96 DDR_B_MA2
DDR_B_MA1 97 A3 A2 98 DDR_B_MA0
99 A1 A0 100
101 VDD9 VDD10 102
5 DDR_B_CLK0 CK0 CK1 DDR_B_CLK2 5
5 DDR_B_CLK0# 103 104 DDR_B_CLK2# 5
105 CK0# CK1# 106 +1.35V_L
DDR_B_MA10 107 VDD11 VDD12 108
A10/AP BA1 DDR_B_BS1 5
5 DDR_B_BS0 109 110 DDR_B_RAS# 5 C133 1 2 10U_0603_6.3V6M
111 BA0 RAS# 112 C134 1 2 10U_0603_6.3V6M
113 VDD13 VDD14 114 C135 1 2 10U_0603_6.3V6M
5 DDR_B_WE# WE# S0# DDR_B_CS0# 5
5 DDR_B_CAS# 115 116 DDR_B_ODT0 5 C136 1 2 10U_0603_6.3V6M
117 CAS# ODT0 118
DDR_B_MA13 119 VDD15 VDD16 120
A13 ODT1 DDR_B_ODT2 5
5 DDR_B_CS2# 121 122 C129 1 2 .1U_0402_16V7K
123 S1# NC2 124 C130 1 2 .1U_0402_16V7K
125 VDD17 VDD18 126 C131 1 2 .1U_0402_16V7K
NCTEST VREF_CA +DDR_B_VREF_CA
127 128 C132 1 2 .1U_0402_16V7K
DDR_B_D32 129 VSS27 VSS28 130 DDR_B_D36 C137 1 2 .1U_0402_16V7K
DDR_B_D33 131 DQ32 DQ36 132 DDR_B_D37 C138 1 2 .1U_0402_16V7K
133 DQ33 DQ37 134 C139 1 2 .1U_0402_16V7K
DDR_B_DQS#4 135 VSS29 VSS30 136 DDR_B_DM4
DDR_B_DQS4 137 DQS#4 DM4 138
139 DQS4 VSS31 140 DDR_B_D38
DDR_B_D34 141 VSS32 DQ38 142 DDR_B_D39
DDR_B_D35 143 DQ34 DQ39 144
Layout Note:
145 DQ35 VSS33 146 DDR_B_D44 Place near JDIMM2
3 DDR_B_D40 147 VSS34 DQ44 148 DDR_B_D45 3
DDR_B_D41 149 DQ40 DQ45 150
151 DQ41 VSS35 152 DDR_B_DQS#5 +0.675VS
DDR_B_DM5 153 VSS36 DQS#5 154 DDR_B_DQS5
155 DM5 DQS5 156
DDR_B_D42 157 VSS37 VSS38 158 DDR_B_D46 C143 1 2 10U_0603_6.3V6M
DDR_B_D43 159 DQ42 DQ46 160 DDR_B_D47
161 DQ43 DQ47 162
DDR_B_D48 163 VSS39 VSS40 164 DDR_B_D52 C145 1 2 1U_0402_6.3V6K
DDR_B_D49 165 DQ48 DQ52 166 DDR_B_D53 C146 1 2 1U_0402_6.3V6K
167 DQ49 DQ53 168
DDR_B_DQS#6 169 VSS41 VSS42 170 DDR_B_DM6
DDR_B_DQS6 171 DQS#6 DM6 172
173 DQS6 VSS43 174 DDR_B_D54
DDR_B_D50 175 VSS44 DQ54 176 DDR_B_D55
DDR_B_D51 177 DQ50 DQ55 178
+3VS 179 DQ51 VSS45 180 DDR_B_D60
Layout Note:
DDR_B_D56 181 VSS46 DQ60 182 DDR_B_D61 Place near JDIMM2.203,204
DDR_B_D57 183 DQ56 DQ61 184
DQ57 VSS47
2

185 186 DDR_B_DQS#7

R229 DDR_B_DM7 187 VSS48 DQS#7 188 DDR_B_DQS7
10K_0402_5% 189 DM7 DQS7 190
DDR_B_D58 191 VSS49 VSS50 192 DDR_B_D62
DDR_B_D59 193 DQ58 DQ62 194 DDR_B_D63
1

195 DQ59 DQ63 196

197 VSS51 VSS52 198
199 SA0 EVENT# 200
+3VS VDDSPD SDA EC_SMB_DA2 13,15,26,29,9
201 202
SA1 SCL EC_SMB_CK2 13,15,26,29,9
+0.675VS 203 204 +0.675VS
VTT1 VTT2
205 206
G1 G2
2

1
4
C147
.1U_0402_16V7K
RS@
R231
0_0402_5%
TYCO_2-2013287-1
Part Number = SP07000KW00 Channel B 4

2 PCB Footprint = TYCO_2-2013287-1_204P

1

<Address: SA0:SA1=10 (A2H)> Security Classification Compal Secret Data Compal Electronics, Inc.
SA0/SA1 Follow INTEL demo board 2014/03/19 2015/03/18 Title
Issued Date Deciphered Date DDR3L DIMMB
DIMM_2 REV H:4mm THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A5WAM_Bay Trail M_LA‐B981P
Date: Monday, May 12, 2014 Sheet 14 of 47
A B C D E
 A B C D E

UGPU1A
GPIO I/O USAGE

Part 1 of 6 +3VSDGPU_AON
PEG_HTX_C_GRX_P0 AG6 C6 RP2000
GPIO0 I GC6_FB_EN
7 PEG_HTX_C_GRX_P0 PEX_RX0 GPIO0
PEG_HTX_C_GRX_N0 AG7 B2 10K_0804_8P4R_5%
7 PEG_HTX_C_GRX_N0 PEX_RX0_N GPIO1
PEG_HTX_C_GRX_P1 AF7 D6 GPIO8_OVERT 8 1 GPIO1 O MEM_VDD_CTL
7 PEG_HTX_C_GRX_P1 PEX_RX1 GPIO2
PEG_HTX_C_GRX_N1 AE7 C7 GPIO9_ALERT 7 2
7 PEG_HTX_C_GRX_N1 PEX_RX1_N GPIO3
AE9 F9 GPIO9_ALERT_GATE 6 3
AF9 PEX_RX2 GPIO4 A3 ACIN_BUF 5 4
AG9 PEX_RX2_N GPIO5 A4
GPIO2 O LCD_BL_PWM
AG10 PEX_RX3 GPIO6 B6 VGA@
AF10 PEX_RX3_N GPIO7 A6 GPIO8_OVERT
NC OVERT N14x for GPIO8 GPIO3 O LCD_VCC
N15x for OVERT*
AE10 F8 GPIO9_ALERT
AE12 NC GPIO9 C5
AF12 NC GPIO10 E7 DGPU_VID
1 AG12 NC GPIO11 D7 ACIN_BUF DGPU_VID 43 GPIO4 O LCD_BL_EN 1
AG13 NC GPIO12 B4 PSI

GPIO
AF13 NC GPIO13 B3 PSI 43
AE13 NC GPIO14 C3
GPIO5 O 3V3_MAIN_EN
AE15 NC GPIO15 D5
AF15 NC GPIO16 D4
AG15 NC GPIO17 C2
GPIO6 I GPU_EVENT#
AG16 NC GPIO18 F7
AF16 NC GPIO19 E6
AE16 NC GPIO20 C4
GPIO7 O 3D Vision
AE18 NC GPIO21 +3VSDGPU_AON
AF18 NC AB6
AG18 NC PEX_WAKE_NC GPIO8 I SYS_PEX_RST_MON#
AG19 NC
AF19 NC
AE19 NC I2CS_SDA 1 VGA@ 21.8K_0402_1%
GPIO9 I/O ALERT
AE21 NC AG3 R2000
AF21 NC NC AF4 I2CS_SCL 1 VGA@ 21.8K_0402_1%
AG21 NC NC AF3 R2001
GPIO10 O MEM_VREF_CTL
AG22 NC NC
NC PSI 2 VGA@ 1 10K_0402_5%
R2052 GPIO11 O PWM_VID
7 PEG_GTX_C_HRX_P0 C80 1 2 VGA@ .1U_0402_16V7K PEG_GTX_HRX_P0 AC9 AE3
PEX_TX0 NC

DACs
7 PEG_GTX_C_HRX_N0 C81 1 2 VGA@ .1U_0402_16V7K PEG_GTX_HRX_N0 AB9 AE4
C82 1 2 VGA@ .1U_0402_16V7K PEG_GTX_HRX_P1 AB10 PEX_TX0_N NC
7 PEG_GTX_C_HRX_P1 PEX_TX1
7 PEG_GTX_C_HRX_N1 C83 1 2 VGA@ .1U_0402_16V7K PEG_GTX_HRX_N1 AC10 EC GPIO12 I PWR_LEVEL
AD11 PEX_TX1_N ACIN_BUF 2 1

PCI EXPRESS
AC11 PEX_TX2 W5 D2000 DGPU_AC_DETECT 29 PLTRST_VGA#
AC12 PEX_TX2_N NC AE2 RB751V-40-YS_SOD323-2
PEX_TX3 TSEN_VREF GPIO13 O PSI
AB12 AF2 VGA@
AB13 PEX_TX3_N NC
NC

2
AC13 EC GPIO14 I HPD_A
AD14 NC
AC14 NC GPIO8_OVERT 1 6
NC GPU_OVERT 29
AC15 VGA@ GPIO15 I HPD_C
AB15 NC DMN66D0LDW-7_SOT363-6
2 NC 2
AB16 B7 R2003 1 VGA@ 2 1.8K_0402_1% Q2000A
AC16 NC I2CA_SCL A7 R2004 1 VGA@ 2 1.8K_0402_1%
NC I2CA_SDA GPIO16 RESERVED
AD17
AC17 NC C9 R2005 1 VGA@ 2 1.8K_0402_1% GPIO9_ALERT_GATE
AC18 NC I2CB_SCL C8 R2006 1 VGA@ 2 1.8K_0402_1%
NC I2CB_SDA GPIO17 I HPD_D

I2C
AB18
NC

5
AB19 A9 R2007 1 VGA@ 2 1.8K_0402_1% EC
AC19 NC I2CC_SCL B9 R2008 1 VGA@ 2 1.8K_0402_1%
AD20 NC I2CC_SDA GPIO9_ALERT 4 3
GPIO18 I HPD_E
NC GPU_ALERT 29
AC20 D9 I2CS_SCL VGA@
AC21 NC I2CS_SCL D8 I2CS_SDA DMN66D0LDW-7_SOT363-6
AB21 NC I2CS_SDA GPIO19 I HPD_F or HPD_B
NC Q2000B
AD23 Place Under L6
AE23 NC
AF24 NC VGA@
GPIO20 Reserved
AE24 NC L6 +PLLVDD 1 2
AG24 NC PLLVDD M6 C2000 0.1U_0402_16V4Z
AG25 NC SP_PLLVDD GPIO21 O GPU_PEX_RST_HOLD#
NC N6 VGA@ +3VSDGPU_AON
NC +GPU_PLLVDD 1 2
C2001
GPIO22

2
+3VSDGPU_AON 1 VGA@ 2 AE8 0.1U_0402_16V4Z
8 CLK_PEG_VGA PEX_REFCLK
R2009 10K_0402_5% AD8 EC SOC GPIO23
8 CLK_PEG_VGA# PEX_REFCLK_N
PEG_CLKREQ# AC6 Place Under M6 I2CS_SCL 1 6
PEX_CLKREQ_N EC_SMB_CK2 13,14,26,29,9
VGA@
PEX_TSTCLK_OUT+ AF22 DMN66D0LDW-7_SOT363-6
CLK

2 @ 1 PEX_TSTCLK_OUT- AE22 PEX_TSTCLK_OUT C11 XTALIN

GPIO24
PEX_TSTCLK_OUT_N XTAL_IN Q2001A
R2010 200_0402_1% B10 XTALOUT
XTAL_OUT +3VSDGPU_AON
PLTRST_VGA# AC7 A10 XTAL_SSIN R2012 1 VGA@ 2 10K_0402_5%
PEX_RST_N XTAL_SSIN

5
2 VGA@ 1 PEX_TREMP AF25 C10 XTAL_OUTBUFFR2013 1 VGA@ 2 10K_0402_5%
R2011 2.49K_0402_1% PEX_TERMP XTAL_OUTBUFF
I2CS_SDA 4 3
EC SOC
EC_SMB_DA2 13,14,26,29,9
GM108-ES-S-A1_FCBGA595 VGA@
@ DMN66D0LDW-7_SOT363-6
3 Q2001B 3
+3VSDGPU_AON
VGA_PWROK 32,42,43
1

+3VS
R1043 R1044
10K_0402_5% 0_0402_5%
VGA@ RS@
1
2

R2015 PH +1.8VS at SOC

10K_0402_5%
2

VGA@ U57 SOC/1.8V

G

GPU/3.3V 1
P
2

NC 4
PEG_CLKREQ# 3 1 PEG_CLKREQ_D# 2 Y VGA_CLKREQ# 7
A SM010019400 3000ma 33ohm@100mhz DCR 0.05
G
S

NL17SZ07DFT2G_SC70-5
38mA +1.05VSDGPU
3

Q36 SA00004BV00 VGA@

2N7002K_SOT23-3 VGA@ +PLLVDD 1 2
VGA@ L2000 CHILISIN PBY160808T-330Y-N
PVT modify +3VSDGPU_AON
1
C2003
PLL_VDD
VGA@ 27MHZ_10PF_7V27000023
+1.8VS +1.8VALW 0.1Ux1, 22Ux1 22U_0603_6.3V6M
 33ohm(ESR0.05)x1 2 XTALOUT 3 1 XTALIN
3 1
1

Near GPU
1

R2019 GND GND

10P_0402_50V8J

10P_0402_50V8J
1 1
R2018 10K_0402_5% SM010028480 1500ma 180ohm@100mhz DCR 0.18 VGA@ VGA@ X2000 VGA@
5

1K_0402_5% @ U58 VGA@ 4 2

1
GPU/3.3V 17mA
SOC/1.8V C2004 C2005
P

NC 4 DGPU_HOLD_RST# VGA@ 2 2
2

DGPU_HOLD_RST#_SOC1.8V 2 Y +GPU_PLLVDD 1 2
7,9 DGPU_HOLD_RST#_SOC1.8V A
G

L2001 BLM18PG181SN1D_2P
NL17SZ07DFT2G_SC70-5 SP_PLLVDD+VID_PLLVDD 1 1 Crystals must have a max ESR of 80 ohm
3

SA00004BV00 C2006 C2007

VGA@ 0.1Ux2, 4.7Ux1,22Ux1 VGA@ VGA@
4 180ohm(ESR0.2)x1 4.7U_0603_6.3V6K 22U_0603_6.3V6M DVT modify 11/27 4
2 2 TXC recommend from 18P change to 10P
Near GPU X2000 from SJ100009700 change to SJ10000G300
+3VSDGPU_AON
Watch out voltage level U2001
MC74VHC1G08DFT2G_SC70-5
5

VGA@
3.3V PLT_RST_BUF# 2
P

25,26,29,30,8 PLT_RST_BUF# B 4 PLTRST_VGA#

DGPU_HOLD_RST# 1 Y
A Security Classification Compal Secret Data Compal Electronics, Inc.
G

3.3V 1 @ 2 R2017 2014/03/19 2015/03/18 Title

29 DGPU_HOLD_RST#_EC Issued Date Deciphered Date
3

R1035 10K_0402_5%
0_0402_5% VGA@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N15X PEG 1/7
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
2

Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A5WAM_Bay Trail M_LA-B981P
Date: Monday, May 12, 2014 Sheet 15 of 47
A B C D E
 A B C D E

VRAM Interface

UGPU1B

MDA[15..0]
1 20 MDA[15..0] 1
Part 2 of 6
MDA[31..16] CMDA[31..0] 20,21
20 MDA[31..16]
MDA0 E18 C27 CMDA0
MDA[47..32] MDA1 F18 FBA_D00 FBA_CMD0 C26 CMDA1
21 MDA[47..32] FBA_D01 FBA_CMD1
MDA2 E16 E24 CMDA2
MDA[63..48] MDA3 F17 FBA_D02 FBA_CMD2 F24 CMDA3
21 MDA[63..48] FBA_D03 FBA_CMD3
MDA4 D20 D27 CMDA4
MDA5 D21 FBA_D04 FBA_CMD4 D26 CMDA5
MDA6 F20 FBA_D05 FBA_CMD5 F25 CMDA6
MDA7 E21 FBA_D06 FBA_CMD6 F26 CMDA7
MDA8 E15 FBA_D07 FBA_CMD7 F23 CMDA8
MDA9 D15 FBA_D08 FBA_CMD8 G22 CMDA9
MDA10 F15 FBA_D09 FBA_CMD9 G23 CMDA10
MDA11 F13 FBA_D10 FBA_CMD10 G24 CMDA11
MDA12 C13 FBA_D11 FBA_CMD11 F27 CMDA12
MDA13 B13 FBA_D12 FBA_CMD12 G25 CMDA13
MDA14 E13 FBA_D13 FBA_CMD13 G27 CMDA14
MDA15 D13 FBA_D14 FBA_CMD14 G26 CMDA15
MDA16 B15 FBA_D15 FBA_CMD15 M24 CMDA16
MDA17 C16 FBA_D16 FBA_CMD16 M23 CMDA17
MDA18 A13 FBA_D17 FBA_CMD17 K24 CMDA18
MDA19 A15 FBA_D18 FBA_CMD18 K23 CMDA19
MDA20 B18 FBA_D19 FBA_CMD19 M27 CMDA20
MDA21 A18 FBA_D20 FBA_CMD20 M26 CMDA21
MDA22 A19 FBA_D21 FBA_CMD21 M25 CMDA22
MDA23 C19 FBA_D22 FBA_CMD22 K26 CMDA23
MDA24 B24 FBA_D23 FBA_CMD23 K22 CMDA24
MDA25 C23 FBA_D24 FBA_CMD24 J23 CMDA25
MDA26 A25 FBA_D25 FBA_CMD25 J25 CMDA26
MDA27 A24 FBA_D26 FBA_CMD26 J24 CMDA27
MDA28 A21 FBA_D27 FBA_CMD27 K27 CMDA28 PVT modify 01/13
MDA29 B21 FBA_D28 FBA_CMD28 K25 CMDA29 DQSA, DQSA# reverse
MDA30 C20 FBA_D29 FBA_CMD29 J27 CMDA30
2 MDA31 C21 FBA_D30 FBA_CMD30 J26 CMDA31 2
MDA32 R22 FBA_D31 FBA_CMD31
FBA_D32 DQMA[3..0] 20
MDA33 R24 D19 DQMA0

INTERFACE A
MDA34 T22 FBA_D33 FBA_DQM0 D14 DQMA1
MDA35 R23 FBA_D34 FBA_DQM1 C17 DQMA2
MDA36 N25 FBA_D35 FBA_DQM2 C22 DQMA3
FBA_D36 FBA_DQM3 DQMA[7..4] 21
MDA37 N26 P24 DQMA4

MEMORY
MDA38 N23 FBA_D37 FBA_DQM4 W24 DQMA5
MDA39 N24 FBA_D38 FBA_DQM5 AA25 DQMA6
MDA40 V23 FBA_D39 FBA_DQM6 U25 DQMA7
NV 15x DG‐06803‐V03 MDA41
MDA42
V22
T23
FBA_D40
FBA_D41
FBA_DQM7
F19 DQSA#0
DQSA#[3..0] 20
MDA43 U22 FBA_D42 FBA_DQS_RN0 C14 DQSA#1
MDA44 Y24 FBA_D43 FBA_DQS_RN1 A16 DQSA#2
MDA45 AA24 FBA_D44 FBA_DQS_RN2 A22 DQSA#3
FBA_D45 FBA_DQS_RN3 DQSA#[7..4] 21
MDA46 Y22 P25 DQSA#4
MDA47 AA23 FBA_D46 FBA_DQS_RN4 W22 DQSA#5
MDA48 AD27 FBA_D47 FBA_DQS_RN5 AB27 DQSA#6
MDA49 AB25 FBA_D48 FBA_DQS_RN6 T27 DQSA#7
MDA50 AD26 FBA_D49 FBA_DQS_RN7
FBA_D50 DQSA[3..0] 20
MDA51 AC25 E19 DQSA0
MDA52 AA27 FBA_D51 FBA_DQS_WP0 C15 DQSA1
MDA53 AA26 FBA_D52 FBA_DQS_WP1 B16 DQSA2
MDA54 W26 FBA_D53 FBA_DQS_WP2 B22 DQSA3
FBA_D54 FBA_DQS_WP3 DQSA[7..4] 21
SM010019400 3000ma 33ohm@100mhz DCR 0.05 MDA55 Y25 R25 DQSA4
MDA56 R26 FBA_D55 FBA_DQS_WP4 W23 DQSA5
MDA57 T25 FBA_D56 FBA_DQS_WP5 AB26 DQSA6
MDA58 N27 FBA_D57 FBA_DQS_WP6 T26 DQSA7
+1.05VSDGPU MDA59 R27 FBA_D58 FBA_DQS_WP7
MDA60 V26 FBA_D59
VGA@
15+55mA MDA61 V27 FBA_D60
2 1 L2002 +FB_PLLAVDD MDA62 W27 FBA_D61
FBA_D62
22U_0603_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

CHILISIN PBY160808T-330Y-N MDA63 W25

3 FBA_D63 D24 3
FBA_CLK0 CLKA0 20
1 2 2 2 F16 D25
FB_PLLAVDD_1 FBA_CLK0_N CLKA0# 20
P22
C2008 C2011 C2010 C2009 FB_PLLAVDD_2 N22
FBA_CLK1 CLKA1 21
VGA@ VGA@ VGA@ VGA@ T97 @ D23 M22
2 1 1 1 FB_VREF_PROBE FBA_CLK1_N CLKA1# 21
D18
H22 FBA_WCK01 C18
FB_DLLAVDD FBA_WCK01_N D17
Place Near GPU Place Under F16 P22 H22 1 VGA@ 2 FB_CLAMP F3 FBA_WCK23 D16
10K_0402_5% R2028 FB_CLAMP FBA_WCK23_N T24
NC
FBA_WCK45 U24
60.4_0402_1% 1 @ 2 R2020FBA_CMD34 F22 FBA_WCK45_N V24
60.4_0402_1% 1 @ 2 R2022FBA_CMD35 J22 FBA_CMD34 FBA_WCK67 V25
+1.5VSDGPU FBA_CMD35 FBA_WCK67_N

GM108-ES-S-A1_FCBGA595
@

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/03/19 Deciphered Date 2015/03/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N15X VRAM 2/7
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A5WAM_Bay Trail M_LA-B981P
Date: Monday, May 12, 2014 Sheet 16 of 47
A B C D E
 A B C D E

UGPU1 UGPU1
BINARY LEVEL STRAPS
UGPU1C

Part 3 of 6 F11 +3VSDGPU_AON +3VSDGPU_AON

AC3 NC AD10
AC4 NC NC AD7 S IC N15V-GM-S-A2 BGA 595P GPU ABO ! S IC N15V-GL-S-A2 BGA 595P GPU ABO ! strap0 strap1 strap2 strap3 strap4
Y4 NC NC B19 VGM@ VGL@
NC FBA_CMD32

1
Y3 V5 SA00007BR20 SA00007OO10
AA3 NC NC V6 R2029 R2030 R2031 R2032 R2033 R2035 R2036 R2037
AA2 NC NC G1 @ @ @ @ @ @ @ @
AB1 NC NC G2 10K_0402_1% 10K_0402_1% 10K_0402_1% 10K_0402_1% 10K_0402_1% 30K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
NC NC

NC
AA1 G3 ZZZ

2
AA4 NC NC G4
NC NC N15V-GM/GL 1G MB X76
AA5 G5
NC NC G6 X761G@ STRAP0
1 NC X76550BOLB1|X76550BOLB0;X76550BOLB4 1
G7 STRAP1 ROM_SI
AB5 NC V1 STRAP2 ROM_SO
AB4 NC NC V2 N15V-GM/GL 1G VRAM X76 STRAP3 ROM_SCLK
AB3 NC NC W1 STRAP4
AB2 NC NC W2
AD3 NC NC W3 ZZZ
NC NC

1
AD2 W4 N15V-GM/GL 2G MB X76
AE1 NC NC R2038 R2039 R2040 R2041 R2042 R2044 R2045 R2046
AD1 NC X762G@ @ @ @ @ VGA@ VGA@ VGA@ VGA@
NC X76550BOLB3|X76550BOLB2;X76550BOLB5
AD4 10K_0402_1% 10K_0402_1% 10K_0402_1% 10K_0402_1% 10K_0402_1% 10K_0402_1% 10K_0402_1% 10K_0402_1%
AD5 NC D11 R2050 1 @ 2 10K_0402_5%

2
NC BUFRST_N N15V-GM/GL 2G VRAM X76
D10
T2 NC
T3 NC E9
T1 NC GPIO8
R1 NC E10
R2 NC NC
GENERAL

NC
LVDS/TMDS

R3 F10 For GC62.0 use
N2 NC NC For N15V‐GL/GM Binary strap table Decive ID : 0x1140
N3 NC N14x for CEC ,NC GPU FBVDD/FBVDDQ X76 Freq Memory Size Memory Config strap0 strap1 strap2 strap3 strap4 ROM_SI ROM_SO ROM_SCLK
NC D1 STRAP0 N15x for GPIO8
STRAP0 D2 STRAP1
STRAP1 X76550BOLB0 0x1 (SA000067550) Micron MT41J128M16JT-093G:K PU 10K PD10K PD 10K PD 10K
V3 E4 STRAP2
V4 NC STRAP2 E3 STRAP3 PU 10K PD10K PU 10K PD 10K
NC STRAP3 0x5 (SA000068U00) Samsung K4W2G1646E-BC1A
U3 D3 STRAP4 900MHz 128Mx16x4
U4 NC STRAP4 C1 PD 10K PD10K PU 10K PU 10K
NC NC Set +1.5VSDGPU X76550BOLB1 0xC (SA00006H430) Hynix H5TC2G63FFR-11C
T4
NC N15V-GL power rail as +1.35V
T5 X76550BOLB4 0xE (SA000068U90) Samsung K4W2G1646Q-BC1A PD 10K PU 10K PU 10K PU 10K PD 10K PD 10K PD 10K PD 10K
R4 NC F6 MULTI_STRAP_REF0_GND 1 @ 2 N15V-GM PR1007 9.31K ohm
R5 NC MULTI_STRAP_REF0_GND F4 R2051 40.2K_0402_1% PU 10K PD10K PD 10K PU 10K
NC NC X76550BOLB5 0x9 (SA000076P20) Samsung K4W4G1646D-BC1A
F5
NC 256Mx16x4
2
X76550BOLB2 900MHz 0xD (SA000077K20) Micron MT41J256M16HA-093G:E PU 10K PD10K PU 10K PU 10K
2
N1
M1 NC PD 10K PD10K PU 10K PD 10K
NC X76550BOLB3 0x4 (SA00006E840) Hynix H5TC4G63AFR-11C
M2 F12
M3 NC THERMDP
K2 NC E12
NC THERMDN Binary [3210] Hexadecimal Bom
K3
K1 NC
NC 0000 0x0
J1
NC
DG‐06246‐001_v04 0001 0x1 1GMIC@
M4 F2 VCCSENSE_VGA 0010 0x2
M5 NC VDD_SENSE VCCSENSE_VGA 43
L3 NC
NC 0011 0x3
L4
K4 NC
NC 0100 0x4 2GAFR@
K5 0101 0x5
J4 NC F1 VSSSENSE_VGA
NC GND_SENSE VSSSENSE_VGA 43
0110 0x6
0111 0x7
J5
N4 NC
NC TEST 1000 0x8
N5
NC
1001 0x9 2GSAM@
P3 AD9 TESTMODE R2054 1 VGA@ 2 10K_0402_5%
P4 NC TESTMODE AE5 JTAG_TCK PAD @ T18
NC JTAG_TCK 1010 0xA
AE6 JTAG_TDI PAD @ T1
JTAG_TDI AF6 JTAG_TDO PAD @ T197
JTAG_TDO 1011 0xB
J2 AD6 JTAG_TMS PAD @ T3
J3 NC JTAG_TMS AG4 JTAG_RST R2053 1 VGA@ 210K_0402_5%
NC JTAG_TRST_N 1100 0xC 1GFFR@
1101 0xD 2GMIC@
3 H3 3
H4 NC
NC SERIAL 1110 0xE 1GSAM@
D12 1111 0xF
ROM_CS_N B12 ROM_SI
ROM_SI A12 ROM_SO
ROM_SO C12 ROM_SCLK
ROM_SCLK
0xC (SA00006H430) Hynix H5TC2G63FFR-11C 0x1 (SA000067550) Micron MT41J128M16JT-093G:K 0xE (SA000068U90) Samsung K4W2G1646Q-BC1A
GM108-ES-S-A1_FCBGA595
@ 0 0 1 1 1 0 0 0 0 1 1 1
strap0 strap1 strap2 strap3 strap0 strap1 strap2 strap3 strap0 strap1 strap2 strap3

R2031 R2032 R2029 R2030 R2031 R2032

10K_0402_1% 10K_0402_1% 10K_0402_1% 10K_0402_1% 10K_0402_1% 10K_0402_1%
RVL‐06891‐001_V05 1GFFR@ 1GFFR@ 1GMIC@ 1GSAM@ 1GSAM@ 1GSAM@

R2038 R2039 R2039 R2040 R2041 R2038

10K_0402_1% 10K_0402_1% 10K_0402_1% 10K_0402_1% 10K_0402_1% 10K_0402_1%
1GFFR@ 1GFFR@ 1GMIC@ 1GMIC@ 1GMIC@ 1GSAM@

0x4 (SA00006E840) Hynix H5TC4G63AFR-11C 0x9 (SA000076P20) Samsung K4W4G1646D-BC1A 0xD (SA000077K20) Micron MT41J256M16HA-093G:E

0 0 1 0 1 0 0 1 1 0 1 1

strap0 strap0 strap2 strap3 strap0 strap1 strap2 strap3 strap0 strap1 strap2 strap3

R2031 R2029 R2032 R2029 R2031 R2032

10K_0402_1% 10K_0402_1% 10K_0402_1% 10K_0402_1% 10K_0402_1% 10K_0402_1%
2GAFR@ 2GSAM@ 2GSAM@ 2GMIC@ 2GMIC@ 2GMIC@
4 4

R2038 R2039 R2041 R2039 R2040 R2039

10K_0402_1% 10K_0402_1% 10K_0402_1% 10K_0402_1% 10K_0402_1% 10K_0402_1%
2GAFR@ 2GAFR@ 2GAFR@ 2GSAM@ 2GSAM@ 2GMIC@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/03/19 Deciphered Date 2015/03/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N15X LVDS 3/7
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A5WAM_Bay Trail M_LA-B981P
Date: Monday, May 12, 2014 Sheet 17 of 47
A B C D E
 A B C D E

NV 15x DG‐06803‐V03

1 1

UGPU1D +1.05VSDGPU
+1.5VSDGPU 3.24A 1.257A
Part 4 of 6

4.7U_0603_6.3V6K
B26 AA10
FBVDDQ_01 PEX_IOVDDQ_1

10U_0603_6.3V6M

22U_0603_6.3V6M
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
0.1U_0402_16V4Z

0.1U_0402_16V4Z
4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
C25 AA12
VGA@ C2039 FBVDDQ_02 PEX_IOVDDQ_2

VGA@ C2040

VGA@ C2032

VGA@ C2033

VGA@ C2021

VGA@ C2022

VGA@ C2013

VGA@ C2014

VGA@ C2016

VGA@ C2017
1 1 1 1 2 2 E23 AA13 1 1 1 1
E26 FBVDDQ_03 PEX_IOVDDQ_3 AA16
F14 FBVDDQ_04 PEX_IOVDDQ_4 AA18
F21 FBVDDQ_05 PEX_IOVDDQ_5 AA19
2 2 2 2 1 1 G13 FBVDDQ_06 PEX_IOVDDQ_6 AA20 2 2 2 2
G14 FBVDDQ_07 PEX_IOVDDQ_7 AA21
G15 FBVDDQ_08 PEX_IOVDDQ_8 AB22
Under GPU G16 FBVDDQ_09 PEX_IOVDDQ_9 AC23
G18 FBVDDQ_10 PEX_IOVDDQ_10 AD24
FBVDDQ_11 PEX_IOVDDQ_11

10U_0603_6.3V6M
G19 AE25 Under GPU Near GPU
FBVDDQ_12 PEX_IOVDDQ_12

22U_0603_6.3V6M
VGA@ C2045

VGA@ C2047
G20 AF26 Midway GPU & Power supply
DA‐06925‐001_v05_secured 1 1
G21 FBVDDQ_13 PEX_IOVDDQ_13 AF27
H24 FBVDDQ_14 PEX_IOVDDQ_14
H26 FBVDDQ_AON
2 2 J21 FBVDDQ_AON AA22
K21 FBVDDQ_AON PEX_IOVDD_1 AB23
L22 FBVDDQ_AON PEX_IOVDD_2 AC24
L24 FBVDDQ_19 PEX_IOVDD_3 AD25
Near GPU

POWER
L26 FBVDDQ_20 PEX_IOVDD_4 AE26
M21 FBVDDQ_21 PEX_IOVDD_5 AE27
2 N21 FBVDDQ_22 PEX_IOVDD_6 2
R21 FBVDDQ_23
T21 FBVDDQ_24
V21 FBVDDQ_25 +3VSDGPU_AON
W21 FBVDDQ_26
FBVDDQ_27 G10
3V3_AON

1U_0402_6.3V6K
0.1U_0402_16V4Z

4.7U_0603_6.3V6K
G12 56mA
3V3_AON

VGA@ C2048

VGA@ C2049

VGA@ C2050
G8 2 1 1
VDD33_3 G9
VDD33_4

V7 1 2 2
W7 NC +1.5VSDGPU
AA6 NC
W6 NC D22 FB_CAL_PD_VDDQ 1 VGA@ 2
NC FB_CAL_PD_VDDQ Under GPU Near GPU
Y6 40.2_0402_1% R2078 +3VSDGPU_AON
NC
C24 FB_CAL_PU_GND 1 VGA@ 2
FB_CAL_PU_GND 42.2_0402_1% R2079

1U_0402_6.3V6K
0.1U_0402_16V4Z

0.1U_0402_16V4Z

4.7U_0603_6.3V6K
VGA@ C2051

VGA@ C2052

VGA@ C2053

VGA@ C2054
M7 B25 FB_CAL_TERM_GND1 VGA@ 2 2 2 1 1
N7 NC FB_CAL_TERM_GND 51.1_0402_1% R2080
T6 NC
P6 NC
NC 1 1 2 2

T7 Under GPU Near GPU
R7 IFPD_PLLVDD_2 +3VSDGPU_AON
U6 NC
R6 IFPD_RSET AA8
286mA
NC PEX_PLL_HVDD_1 AA9
PEX_PLL_HVDD_2

0.1U_0402_16V4Z

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
VGA@ C2034

VGA@ C2035

VGA@ C2036
3 AB8 2 1 1 3
PEX_SVDD_3V3

J7
K7 NC 1 2 2
K6 NC AA14
H6 NC PEX_PLLVDD_1 AA15
J6 NC PEX_PLLVDD_2
NC Near GPU
+1.05VSDGPU
130mA +PEX_PLLVDD 2 @ 1

0.1U_0402_16V4Z
R2075 0_0603_5%

VGA@ C2041

VGA@ C2042

VGA@ C2043
1U_0402_6.3V6K

4.7U_0603_6.3V6K
2 1 1
GM108-ES-S-A1_FCBGA595
@
1 2 2

Under GPU Near GPU

R2075 R2075

BLM18PG121SN1D_0603 BLM18PG121SN1D_0603
VGL@ VGM@
4 SM01000BW00 SM01000BW00 4

SM010028800 2000ma 120ohm@100mhz DCR 0.1

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/03/19 Deciphered Date 2015/03/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N15X POWER & GND 4/9
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A5WAM_Bay Trail M_LA-B981P
Date: Monday, May 12, 2014 Sheet 18 of 47
A B C D E
 A B C D E

NV 15x DG‐06803‐V03

UGPU1F
UGPU1E +VGA_CORE +VGA_CORE
Part 6 of 6
A2 Part 5 of 6 K11
A26 GND_001 GND_057 K13 K10 V18
AB11 GND_002 GND_058 K15 K12 VDD_001 VDD_041 V16
1 GND_003 GND_059 VDD_002 VDD_040 1
AB14 K17 K14 V14
AB17 GND_004 GND_060 L10 K16 VDD_003 VDD_039 V12
AB20 GND_005 GND_061 L12 K18 VDD_004 VDD_038 V10
AB24 GND_006 GND_062 L14 L11 VDD_005 VDD_037 U17
GND_007 GND_063 VDD_006 VDD_036

POWER
AC2 L16 L13 U15
AC22 GND_008 GND_064 L18 L15 VDD_007 VDD_035 U13
AC26 GND_009 GND_065 L2 L17 VDD_008 VDD_034 U11
AC5 GND_010 GND_066 L23 M10 VDD_009 VDD_033 T18
AC8 GND_011 GND_067 L25 M12 VDD_010 VDD_032 T16
AD12 GND_012 GND_068 L5 M14 VDD_011 VDD_031 T14
AD13 GND_013
GND_014
GND_069
GND_070
M11 M16 VDD_012
VDD_013
VDD_030
VDD_029
T12 DA‐06925‐V05
AD15 M13 M18 T10
AD16 GND_015 GND_071 M15 N11 VDD_014 VDD_028 R17
AD18 GND_016 GND_072 M17 N13 VDD_015 VDD_027 R15
AD19 GND_017 GND_073 N10 N15 VDD_016 VDD_026 R13
AD21 GND_018 GND_074 N12 N17 VDD_017 VDD_025 R11
AD22 GND_019 GND_075 N14 P10 VDD_018 VDD_024 P18
AE11 GND_020 GND_076 N16 P12 VDD_019 VDD_023 P16
AE14 GND_021 GND_077 N18 VDD_020 VDD_022 P14
AE17 GND_022 GND_078 P11 VDD_021
AE20 GND_023 GND_079 P13
AF1 GND_024 GND_080 P15
AF11 GND_025 GND_081 P17
GND
AF14 GND_026 GND_082 P2
AF17 GND_027 GND_083 P23
AF20 GND_028 GND_084 P26
AF23 GND_029 GND_085 P5
AF5 GND_030 GND_086 R10
AF8 GND_031 GND_087 R12 GM108-ES-S-A1_FCBGA595
AG2 GND_032 GND_088 R14 @
AG26 GND_033 GND_089 R16
B1 GND_034 GND_090 R18
B11 GND_035 GND_091 T11
2 B14 GND_036 GND_092 T13 2
B17 GND_037 GND_093 T15
B20 GND_038 GND_094 T17
B23 GND_039
GND_040
GND_095
GND_096
U10 DA07075‐V01
B27 U12
B5 GND_041 GND_097 U14
B8 GND_042 GND_098 U16
E11 GND_043 GND_099 U18
E14 GND_044 GND_100 U2
E17 GND_045 GND_101 U23
E2 GND_046 GND_102 U26
E20 GND_047 GND_103 U5
E22 GND_048 GND_104 V11
E25 GND_049 GND_105 V13
E5 GND_050 GND_106 V15
E8 GND_051 GND_107 V17
H2 GND_052 GND_108 Y2
H23 GND_053 GND_109 Y23
H25 GND_054 GND_110 Y26
H5 GND_055 GND_111 Y5
GND_056 GND_112

AA7
GND AB7
GND

GM108-ES-S-A1_FCBGA595
@

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/03/19 Deciphered Date 2015/03/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N15X POWER & GND 5/7
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A5WAM_Bay Trail M_LA-B981P
Date: Monday, May 12, 2014 Sheet 19 of 47
A B C D E
 A B C D E

VRAM DDR3 chips 16,21 DQSA[7..0]

DQSA[7..0]

DQSA#[7..0] U2004 U2004

16,21 DQSA#[7..0]
DQMA[7..0]
16,21 DQMA[7..0]

16,21 MDA[63..0]
MDA[63..0]

CMDA[30..0]
Low 32 SA00006H430 SA00006E840
16,21 CMDA[30..0]
Mode D H5TC2G63FFR-11C H5TC4G63AFR-11C
Address 0..31 32..63 1GFFR@ 2GAFR@

CMD0 CS0_L# U2005 U2005

1 CMD1 1

CMD2 ODT_L
U2004 U2005
CMD3 CKE_L SA00006H430 SA00006E840
+MEM_VREF0 M8 E3 MDA12 +MEM_VREF1 M8 E3 MDA3 H5TC2G63FFR-11C H5TC4G63AFR-11C
VREFCA DQL0 VREFCA DQL0
+MEM_VREF1 H1
VREFDQ DQL1
F7 MDA13 +MEM_VREF0 H1
VREFDQ DQL1
F7 MDA4 CMD4 A14 A14 1GFFR@ 2GAFR@
F2 MDA8 F2 MDA2
DQL2 DQL2
CMDA9 N3
A0 DQL3
F8 MDA15 CMDA9 N3
A0 DQL3
F8 MDA7 CMD5 RST RST U2006 U2006
CMDA11 P7 H3 MDA9 Group1 CMDA11 P7 H3 MDA0 Group0
A1 DQL4 A1 DQL4
CMDA8 P3
A2 DQL5
H8 MDA11 CMDA8 P3
A2 DQL5
H8 MDA5 CMD6 A9 A9
CMDA25 N2 G2 MDA10 CMDA25 N2 G2 MDA1
A3 DQL6 A3 DQL6
CMDA10 P8
A4 DQL7
H7 MDA14 CMDA10 P8
A4 DQL7
H7 MDA6 CMD7 A7 A7
CMDA24 P2 CMDA24 P2
A5 A5
CMDA22 R8
A6
CMDA22 R8
A6 CMD8 A2 A2 SA00006H430 SA00006E840
CMDA7 R2 D7 MDA17 CMDA7 R2 D7 MDA27 H5TC2G63FFR-11C H5TC4G63AFR-11C
A7 DQU0 A7 DQU0
CMDA21 T8
A8 DQU1
C3 MDA21 CMDA21 T8
A8 DQU1
C3 MDA29 CMD9 A0 A0 1GFFR@ 2GAFR@
CMDA6 R3 C8 MDA18 CMDA6 R3 C8 MDA25
A9 DQU2 A9 DQU2
CMDA29 L7
A10/AP DQU3
C2 MDA23 CMDA29 L7
A10/AP DQU3
C2 MDA30 CMD10 A4 A4 U2007 U2007
CMDA23 R7 A7 MDA19 Group2 CMDA23 R7 A7 MDA24 Group3
A11 DQU4 A11 DQU4
CMDA28 N7
A12 DQU5
A2 MDA22 CMDA28 N7
A12 DQU5
A2 MDA28 CMD11 A1 A1
CMDA20 T3 B8 MDA16 CMDA20 T3 B8 MDA26
A13 DQU6 A13 DQU6
CMDA4 T7
A14 DQU7
A3 MDA20 CMDA4 T7
A14 DQU7
A3 MDA31 CMD12 BA0 BA0
CMDA14 M7 CMDA14 M7
A15/BA3 A15/BA3
+1.5VSDGPU +1.5VSDGPU CMD13 WE* WE* SA00006H430 SA00006E840
H5TC2G63FFR-11C H5TC4G63AFR-11C
CMDA12 M2
BA0 VDD
B2 CMDA12 M2
BA0 VDD
B2 CMD14 A15 A15 1GFFR@ 2GAFR@
CMDA27 N8 D9 CMDA27 N8 D9
BA1 VDD BA1 VDD
CMDA26 M3
BA2 VDD
G7 CMDA26 M3
BA2 VDD
G7 CMD15 CAS* CAS*
K2 K2
VDD VDD
VDD
K8
VDD
K8 CMD16 CS0_H#
N1 N1
VDD VDD
CLKA0 J7
CK VDD
N9 CLKA0 J7
CK VDD
N9 CMD17
CLKA0# K7 R1 CLKA0# K7 R1 U2004 U2004
CK VDD CK VDD
2 CMDA3 K9
CKE/CKE0 VDD
R9
+1.5VSDGPU
CMDA3 K9
CKE/CKE0 VDD
R9
+1.5VSDGPU
CMD18 ODT_H 2

CMD19 CKE_H
CMDA2 K1 A1 CMDA2 K1 A1
ODT/ODT0 VDDQ ODT/ODT0 VDDQ
CMDA0 L2
CS/CS0 VDDQ
A8 CMDA0 L2
CS/CS0 VDDQ
A8 CMD20 A13 A13
CMDA30 J3 C1 CMDA30 J3 C1 SA000067550 SA000077K20
RAS VDDQ RAS VDDQ
CMDA15 K3
CAS VDDQ
C9 CMDA15 K3
CAS VDDQ
C9 CMD21 A8 A8 MT41J128M16JT-093G:K MT41J256M16HA-093G:E
CMDA13 L3 D2 CMDA13 L3 D2 1GMIC@ 2GMIC@
WE VDDQ WE VDDQ
310mAVDDQ E9
VDDQ
E9 CMD22 A6 A6
F1 310mAVDDQ F1 U2005 U2005
VDDQ
DQSA1 F3
DQSL VDDQ
H2 DQSA0 F3
DQSL VDDQ
H2 CMD23 A11 A11
DQSA2 C7 H9 DQSA3 C7 H9
DQSU VDDQ DQSU VDDQ
CMD24 A5 A5
DQMA1 E7
DML VSS
A9 DQMA0 E7
DML VSS
A9 CMD25 A3 A3
DQMA2 D3 B3 DQMA3 D3 B3 SA000067550 SA000077K20
DMU VSS DMU VSS
VSS
E1
VSS
E1 CMD26 BA2 BA2 MT41J128M16JT-093G:K MT41J256M16HA-093G:E
G8 G8 1GMIC@ 2GMIC@
VSS VSS
DQSA#1 G3
DQSL VSS
J2 DQSA#0 G3
DQSL VSS
J2 CMD27 BA1 BA1
DQSA#2 B7 J8 DQSA#3 B7 J8 U2006 U2006
DQSU VSS DQSU VSS
VSS
M1
VSS
M1 CMD28 A12 A12
M9 M9
VSS VSS
VSS
P1
VSS
P1 CMD29 A10 A10
CMDA5 T2 P9 CMDA5 T2 P9
RESET VSS RESET VSS
VSS
T1
VSS
T1 CMD30 RAS* RAS*
ZQ0 L8 T9 ZQ1 L8 T9 SA000067550 SA000077K20
ZQ/ZQ0 VSS ZQ/ZQ0 VSS
Not Available MT41J128M16JT-093G:K MT41J256M16HA-093G:E
1

1
1GMIC@ 2GMIC@
J1 B1 J1 B1 LOW HIGH
R2081 VGA@ L1 NC/ODT1 VSSQ B9 R2082 VGA@ L1 NC/ODT1 VSSQ B9 U2007 U2007
243_0402_1% J9 NC/CS1 VSSQ D1 243_0402_1% J9 NC/CS1 VSSQ D1
L9 NC/CE1 VSSQ D8 L9 NC/CE1 VSSQ D8
2

2
NCZQ1 VSSQ E2 NCZQ1 VSSQ E2
VSSQ VSSQ Command Bit Default Pull-down
3 E8 E8 3
VSSQ F9 VSSQ F9 ODTx 10k
VSSQ G1 VSSQ G1
VSSQ VSSQ 10k
SA000067550 SA000077K20
G9 G9 DDR3 CKEx MT41J128M16JT-093G:K MT41J256M16HA-093G:E
VSSQ VSSQ 1GMIC@ 2GMIC@
RST 10k
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 CS* No Termination
H5TQ2G63BFR-11C_FBGA96 H5TQ2G63BFR-11C_FBGA96
@ @

+1.5VSDGPU +1.5VSDGPU

R2085 R2086
VGA@ VGA@
1.33K_0402_1% 1.33K_0402_1%
+1.5VSDGPU CLKA0
16 CLKA0

1
+MEM_VREF0 +MEM_VREF1
CMDA2 R2093 1 VGA@ 2 10K_0402_5% VGA@
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

CMDA3 R2094 1 VGA@ 2 10K_0402_5% 1 1 R2087

VGA@ C2071

VGA@ C2072

VGA@ C2073

VGA@ C2074

VGA@ C2075

VGA@ C2076

VGA@ C2077

VGA@ C2078

VGA@ C2079

VGA@ C2080

VGA@ C2081

VGA@ C2082

1 1 1 1 1 1 1 1 1 1 1 1 CMDA5 R2095 1 VGA@ 2 10K_0402_5% R2091 C2055 R2092 C2056 160_0402_1%

CMDA18 R2098 1 VGA@ 2 10K_0402_5% VGA@ VGA@ VGA@ VGA@

2
CMDA19 R2099 1 VGA@ 2 10K_0402_5% 1.33K_0402_1% 0.1U_0402_16V4Z 1.33K_0402_1% 0.1U_0402_16V4Z CLKA0#
2 2 16 CLKA0#
4 4
2 2 2 2 2 2 2 2 2 2 2 2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/03/19 Deciphered Date 2015/03/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N15X DDR3 6/7
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A5WAM_Bay Trail M_LA-B981P
Date: Monday, May 12, 2014 Sheet 20 of 47
A B C D E
 A B C D E

VRAM DDR3 chips 16,20 DQSA[7..0]

DQSA[7..0]

DQSA#[7..0]
Mode D
Address 0..31 32..63
16,20 DQSA#[7..0]

16,20 DQMA[7..0]
DQMA[7..0] CMD0 CS0_L#
16,20 MDA[63..0]
MDA[63..0] CMD1
16,20 CMDA[30..0]
CMDA[30..0] CMD2 ODT_L
CMD3 CKE_L
1 CMD4 A14 A14 1

High 32 CMD5
CMD6
RST
A9
RST
A9
U2007 CMD7 A7 A7
U2006
+MEM_VREF3 M8
VREFCA DQL0
E3 MDA45 CMD8 A2 A2
+MEM_VREF2 M8 E3 MDA39 +MEM_VREF2 H1 F7 MDA40
VREFCA DQL0 VREFDQ DQL1
+MEM_VREF3 H1
VREFDQ DQL1
F7 MDA35
DQL2
F2 MDA46 CMD9 A0 A0
F2 MDA37 CMDA9 N3 F8 MDA41
DQL2 A0 DQL3
CMDA9 N3
A0 DQL3
F8 MDA33 CMDA11 P7
A1 DQL4
H3 MDA47 Group5 CMD10 A4 A4
CMDA11 P7 H3 MDA38 Group4 CMDA8 P3 H8 MDA43
A1 DQL4 A2 DQL5
CMDA8 P3
A2 DQL5
H8 MDA32 CMDA25 N2
A3 DQL6
G2 MDA44 CMD11 A1 A1
CMDA25 N2 G2 MDA36 CMDA10 P8 H7 MDA42
A3 DQL6 A4 DQL7
CMDA10 P8
A4 DQL7
H7 MDA34 CMDA24 P2
A5 CMD12 BA0 BA0
CMDA24 P2 CMDA22 R8
A5 A6
CMDA22 R8
A6
CMDA7 R2
A7 DQU0
D7 MDA53 CMD13 WE* WE*
CMDA7 R2 D7 MDA61 CMDA21 T8 C3 MDA49
A7 DQU0 A8 DQU1
CMDA21 T8
A8 DQU1
C3 MDA59 CMDA6 R3
A9 DQU2
C8 MDA55 CMD14 A15 A15
CMDA6 R3 C8 MDA60 CMDA29 L7 C2 MDA50
A9 DQU2 A10/AP DQU3
CMDA29 L7
A10/AP DQU3
C2 MDA57 CMDA23 R7
A11 DQU4
A7 MDA52 Group6 CMD15 CAS* CAS*
CMDA23 R7 A7 MDA63 Group7 CMDA28 N7 A2 MDA48
A11 DQU4 A12 DQU5
CMDA28 N7
A12 DQU5
A2 MDA56 CMDA20 T3
A13 DQU6
B8 MDA54 CMD16 CS0_H#
CMDA20 T3 B8 MDA62 CMDA4 T7 A3 MDA51
A13 DQU6 A14 DQU7
CMDA4 T7
A14 DQU7
A3 MDA58 CMDA14 M7
A15/BA3 +1.5VSDGPU
CMD17
CMDA14 M7
A15/BA3 +1.5VSDGPU CMD18 ODT_H
CMDA12 M2 B2
BA0 VDD
CMDA12 M2
BA0 VDD
B2 CMDA27 N8
BA1 VDD
D9 CMD19 CKE_H
CMDA27 N8 D9 CMDA26 M3 G7
BA1 VDD BA2 VDD
CMDA26 M3
BA2 VDD
G7
VDD
K2 CMD20 A13 A13
K2 K8
VDD VDD
2
VDD
K8
VDD
N1 CMD21 A8 A8 2
N1 CLKA1 J7 N9
VDD CK VDD
CLKA1 J7
CK VDD
N9 CLKA1# K7
CK VDD
R1 CMD22 A6 A6
CLKA1# K7 R1 CMDA19 K9 R9
CK VDD CKE/CKE0 VDD
CMDA19 K9
CKE/CKE0 VDD
R9
+1.5VSDGPU
+1.5VSDGPU CMD23 A11 A11
CMDA18 K1
ODT/ODT0 VDDQ
A1 CMD24 A5 A5
CMDA18 K1 A1 CMDA16 L2 A8
ODT/ODT0 VDDQ CS/CS0 VDDQ
CMDA16 L2
CS/CS0 VDDQ
A8 CMDA30 J3
RAS VDDQ
C1 CMD25 A3 A3
CMDA30 J3 C1 CMDA15 K3 C9
RAS VDDQ CAS VDDQ
CMDA15 K3
CAS VDDQ
C9 CMDA13 L3
WE VDDQ
D2 CMD26 BA2 BA2
CMDA13 L3 D2 310mAVDDQ E9
WE VDDQ
310mAVDDQ E9
VDDQ
F1 CMD27 BA1 BA1
F1 DQSA5 F3 H2
VDDQ DQSL VDDQ
DQSA4 F3
DQSL VDDQ
H2 DQSA6 C7
DQSU VDDQ
H9 CMD28 A12 A12
DQSA7 C7 H9
DQSU VDDQ
CMD29 A10 A10
DQMA5 E7 A9
DML VSS
DQMA4 E7
DML VSS
A9 DQMA6 D3
DMU VSS
B3 CMD30 RAS* RAS*
DQMA7 D3 B3 E1
DMU VSS E1 VSS G8
VSS VSS Not Available
G8 DQSA#5 G3 J2
DQSA#4 G3 VSS J2 DQSA#6 B7 DQSL VSS J8
DQSA#7 B7 DQSL VSS J8 DQSU VSS M1
LOW HIGH
DQSU VSS M1 VSS M9
VSS M9 VSS P1
VSS P1 CMDA5 T2 VSS P9
VSS RESET VSS Command Bit Default Pull-down
CMDA5 T2 P9 T1
RESET VSS T1 ZQ3 L8 VSS T9 ODTx 10k
ZQ2 L8 VSS T9 ZQ/ZQ0 VSS
ZQ/ZQ0 VSS 10k

1
VGA@ DDR3 CKEx
1

R2101 J1 B1 RST 10k

VGA@ J1 B1 243_0402_1% L1 NC/ODT1 VSSQ B9
3 R2100 L1 NC/ODT1 VSSQ B9 J9 NC/CS1 VSSQ D1 CS* No Termination 3
243_0402_1% J9 NC/CS1 VSSQ D1 L9 NC/CE1 VSSQ D8

2
L9 NC/CE1 VSSQ D8 NCZQ1 VSSQ E2
2

NCZQ1 VSSQ E2 VSSQ E8

VSSQ E8 VSSQ F9
VSSQ F9 VSSQ G1
VSSQ G1 VSSQ G9
VSSQ G9 VSSQ
VSSQ 96-BALL
96-BALL SDRAM DDR3
SDRAM DDR3 H5TQ2G63BFR-11C_FBGA96
H5TQ2G63BFR-11C_FBGA96 @
@

+1.5VSDGPU
+1.5VSDGPU

R2089
+1.5VSDGPU R2088 VGA@
VGA@ 1.33K_0402_1%
1.33K_0402_1%
CLKA1
16 CLKA1
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
+MEM_VREF3
1

VGA@ C2059

VGA@ C2060

VGA@ C2061

VGA@ C2062

VGA@ C2063

VGA@ C2064

VGA@ C2065

VGA@ C2066

VGA@ C2067

VGA@ C2068

VGA@ C2069

VGA@ C2070
1 1 1 1 1 1 1 1 1 1 1 1 +MEM_VREF2
R2090 1
VGA@ 1 R2097 C2058
160_0402_1% R2096 C2057 VGA@ VGA@
2 2 2 2 2 2 2 2 2 2 2 2 VGA@ VGA@ 1.33K_0402_1% 0.1U_0402_16V4Z
4 4
2

CLKA1# 1.33K_0402_1% 0.1U_0402_16V4Z 2

16 CLKA1# 2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/03/19 Deciphered Date 2015/03/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N15X DDR3 7/7
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A5WAM_Bay Trail M_LA-B981P
Date: Monday, May 12, 2014 Sheet 21 of 47
A B C D E
 A B C D E

LCD POWER CIRCUIT LCD/ LED PANEL Conn.

SM010014520 3000ma
R959
+3VS +LCDVDD 220ohm@100mhz 0_0402_5%
U8 DCR 0.04
1
W=60mils EMC@ 1 2
1 5 VOUT B+ L11 +INVPWR_B+ 1
VIN HCB2012KF-221T30_2P
2
1 W=60mils 1 2
W=60mils JLVDS1
4 GND C367
W=60mils 1
VIN +INVPWR_B+ 1
1 4.7U_0603_6.3V6K 1 1 2 41
3 2 @EMC@ @EMC@ 3 2 G1 42
C140 EN C365 C364 4 3 G2 43
1U_0402_6.3V6K G5243AT11U_SOT23-5 68P_0402_50V8J 1000P_0402_50V7K 5 4 G3 44
2 2 2 6 5 G4 45
6 INVT_PWM_SOC 6 G5
7 46
29 EC_BKOFF# 7 G6
1 2 EDP_HPD_CONN 8
6 ENVDD 8
C549 @EMC@ +LCDVDD 9
220P_0402_50V7K 10 9
1 2 TS_EN_1 11 10
C528 @EMC@ 12 11
220P_0402_50V7K 13 12
14 13
15 14
TS_RST# 16 15
29 TS_RST# 16
17
18 17
+1.8VS 19 18
EDP_AUXN_C R1063 2 @ 1 100K_0402_5% 20 19
+LCDVDD 20
21
9 I2C5_SDA_PNL 21
1

EDP_AUXP_C 1 @ 2 100K_0402_5% I2C TS 22

9 I2C5_SCL_PNL 22
R1062 23
R383 24 23
10K_0402_5% C377 1 2 .1U_0402_16V7K EDP_AUXN_C 25 24
6 EDP_AUXN 25
Intel recommends having a pull-up resistor of 100 kΩ for 6 EDP_AUXP C376 1 2 .1U_0402_16V7K EDP_AUXP_C 26
2

27 26
6 EDP_HPD# AUXN and a pull-down resistor of 100 kΩ for AUXP between C371 1 2 .1U_0402_16V7K EDP_TXP0_C 28 27
6 EDP_TXP0 28
1

the AC capacitor and the connector, to assist source 6 EDP_TXN0

C372 1 2 .1U_0402_16V7K EDP_TXN0_C 29
29
2 D 30 2
Q13 2 EDP_HPD_CONN detection by the sink device. C373 1 2 .1U_0402_16V7K EDP_TXP1_C 31 30
6 EDP_TXP1 31
2N7002K_SOT23-3 G C374 1 2 .1U_0402_16V7K EDP_TXN1_C 32
6 EDP_TXN1 32
1

S TS_INT# 33
34 33
+TS_PWR
3

R364 35 34
9 USB20_P2 35
100K_0402_5% R427 1 RS@ 2 0_0402_5% USB TS 36
9 USB20_N2 36
R428 1 RS@ 2 0_0402_5% +3VS 2 RS@ 1 +3VS_Camcra 37
2

L27 0_0402_5% R1162 USB20_P3_CAMERA 38 37

USB20_P3 3 4 USB20_P3_CAMERA USB20_N3_CAMERA 39 38
9 USB20_P3 3 4 39
40
40
USB20_N3 2 1 USB20_N3_CAMERA E-T_0871K-F40N-00L
9 USB20_N3 2 1 SP010011Z00
WCM2012F2SF-670T04-0805_4P CONN@
@EMC@

+TS_PWR

For Touch Panel
2 TSI@ 1 I2C5_SDA_PNL
2.2K_0402_5% R1147
2 TSI@ 1 I2C5_SCL_PNL
3 +5VS +TS_PWR 2.2K_0402_5% R1150 3
1 TSI@ 2 TS_INT#
10K_0402_5% R635
1 2
R1145 1 TSI@ 2 TS_RST#
0_0603_5% 10K_0402_5% R636

+3VS

1 @ 2 R1033 1 RS@ 2 0_0402_5% TS_EN_1

29 TS_EN
R1146
0_0603_5%

+1.8VS
1

4 TSI@ R634 4
10K_0402_5%
2
G
2

TS_INT_R# 3 1 TS_INT#
8 TS_INT_R#
S

TSI@ Q78
MESS138W-G_SOT323-3
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/03/19 Deciphered Date 2015/03/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
eDP CONN.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A5WAM_Bay Trail M_LA‐B981P
Date: Monday, May 12, 2014 Sheet 22 of 47
A B C D E
 A B C D E

W=40mils R368 2 RS@ 1 0_0402_5%

+5VS +HDMI_5V_OUT

HDMI_C_CLK- 4 3 HDMI_R_CK-
U52 4 3
WCM2012F2S-900T04_0805
1 3 HDMI_C_CLK+ L53 @EMC@1 2 HDMI_R_CK+ 1
OUT 1 2
1
1
IN C378 R369 2 RS@ 1 0_0402_5%
2 .1U_0402_16V7K
GND 2

AP2330W-7_SC59-3 R370 2 RS@ 1 0_0402_5%

HDMI_C_TX0- 4 3 HDMI_R_D0-
4 3
WCM2012F2S-900T04_0805
HDMI_C_TX0+ L54 @EMC@1 2 HDMI_R_D0+
1 2

R371 2 RS@ 1 0_0402_5%

6 HDMI_TX1- C381 2 1 .1U_0402_16V7K HDMI_C_TX1-

6 HDMI_TX1+ C382 2 1 .1U_0402_16V7K HDMI_C_TX1+
6 HDMI_TX2- C379 2 1 .1U_0402_16V7K HDMI_C_TX2- R372 2 RS@ 1 0_0402_5%
6 HDMI_TX2+ C380 2 1 .1U_0402_16V7K HDMI_C_TX2+

6 HDMI_TX0- C383 2 1 .1U_0402_16V7K HDMI_C_TX0- HDMI_C_TX1- 4 3 HDMI_R_D1-

C384 2 1 .1U_0402_16V7K HDMI_C_TX0+ 4 3
6 HDMI_TX0+
6 HDMI_CLK- C385 2 1 .1U_0402_16V7K HDMI_C_CLK- WCM2012F2S-900T04_0805
6 HDMI_CLK+ C386 2 1 .1U_0402_16V7K HDMI_C_CLK+ HDMI_C_TX1+ L55 @EMC@1 2 HDMI_R_D1+
1 2

R373 2 RS@ 1 0_0402_5%

2 2

R374 2 RS@ 1 0_0402_5%

+1.8VS
RP15
HDMI_C_TX2- 4 3 HDMI_R_D2-
HDMI_DDCDATA 5 4 +HDMI_5V_OUT 4 3
HDMI_DDCCLK 6 3 WCM2012F2S-900T04_0805
HDMI_SDATA 7 2 HDMI_C_TX2+ L56 @EMC@1 2 HDMI_R_D2+
HDMI_SCLK 8 1 1 2

2.2K_0804_8P4R_5% R375 2 RS@ 1 0_0402_5%

+1.8VS

HDMI_C_TX1- R1071 1 2 619_0402_1%

HDMI_C_TX1+ R1072 1 2 619_0402_1%
5

HDMI_C_TX2- R1073 1 2 619_0402_1%

HDMI_C_TX2+ R1074 1 2 619_0402_1%
G

4 3 HDMI_SCLK

HDMI_GND
6 HDMI_DDCCLK
S

Q82A HDMI_C_TX0- R1075 1 2 619_0402_1%

2

DMN63D8LDW-7_SOT363-6 HDMI_C_TX0+ R1076 1 2 619_0402_1%

HDMI_C_CLK- R1077 1 2 619_0402_1%
G

1 6 HDMI_SDATA HDMI_C_CLK+ R1078 1 2 619_0402_1%

6 HDMI_DDCDATA
S

Q82B
DMN63D8LDW-7_SOT363-6
3 3

3
D

+3VS 5 G Q14A
S DMN66D0LDW-7_SOT363-6

4
+1.8VS
1

R376 HDMI connector

10K_0402_5% JHDMI1
HDMI_HPD 19
18 HP_DET
+HDMI_5V_OUT
2

17 +5V
6 HDMI_HPD# DDC/CEC_GND
HDMI_SDATA 16
SDA
6

HDMI_SCLK 15
Q14B
D
G 2 HDMI_HPD 14 SCL
Reserved

2
DMN66D0LDW-7_SOT363-6 S 13
CEC
1

HDMI_R_CK- 12
1

R121 11 CK-
HDMI_R_CK+ 10 CK_shield
100K_0402_5% CK+
HDMI_R_D0- 9
8 D0-
2

D2 HDMI_R_D0+ 7 D0_shield
@EMC@ HDMI_R_D1- 6 D0+
YSLC05CH_SOT23-3 5 D1-

1
HDMI_R_D1+ 4 D1_shield 20
HDMI_R_D2- 3 D1+ GND 21
2 D2- GND 22
D2_shield GND
Reserved for ESD HDMI_R_D2+ 1
D2+ GND
23
4 4
SUYIN_100042GR019M23MZR
DC232001I00
CONN@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/03/19 Deciphered Date 2015/03/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDMI CONN.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A5WAM_Bay Trail M_LA‐B981P
Date: Monday, May 12, 2014 Sheet 23 of 47
A B C D E
 A B C D E

1 1

+HDMI_5V_OUT

W=40mils
07/05 : ripple reduce 1
C450
.1U_0402_16V7K
CRT Connector
T196
2 @
Video Filter
JCRT1
L42 EMC@ 6
77MHz@1920x1200x60Hz BLM15BB470SN1D_2P 11
1 2 CRT_R_2 1
6 CRT_R
L45 EMC@ 7
BLM15BB470SN1D_2P CRT_DATA 12
1 2 CRT_G_2 2
6 CRT_G
L46 EMC@ 8
BLM15BB470SN1D_2P 13
1 2 CRT_B_2 3
6 CRT_B
9
14

15P_0402_50V8J
C648 EMC@

15P_0402_50V8J
C615 EMC@

15P_0402_50V8J
C611 EMC@

10P_0402_50V8J
C647 EMC@

10P_0402_50V8J
C618 EMC@

10P_0402_50V8J
C616 EMC@
RP50 1 1 1 1 1 1 @ T206
@T206 4
CRT_R 8 1 10 G 16
CRT_G 7 2 CRT_CLK 15 G 17
CRT_B 6 3 5
5 4 2 2 2 2 2 2
CCM_070546HR015M25FZR
150_0804_8P4R_1% DC060005810

2
CONN@ 2

+HDMI_5V_OUT
CRT_HSYNC_B
U24 1
1 5 @EMC@
OE Vcc C448
74kHz@1920x1200x60Hz 10P_0402_50V8J
2 2
6 CRT_HSYNC IN A

3 4 CRT_VSYNC_B
GND OUT Y
1
M74VHC1GT125DF2G_SC70-5 @EMC@
U23 C449
1 5 10P_0402_50V8J
OE Vcc 2
60Hz@1920x1200x60Hz
2
6 CRT_VSYNC IN A

3 4
GND OUT Y

M74VHC1GT125DF2G_SC70-5

3 3

+3VS
2

+3VS
G

CRT_DDC_DATA 1 6 CRT_DATA RP42 +HDMI_5V_OUT

6 CRT_DDC_DATA
S

CRT_DDC_DATA 5 4
Q27B CRT_DDC_CLK 6 3
5

DMN66D0LDW-7_SOT363-6 CRT_DATA 7 2
CRT_CLK 8 1
G

CRT_DDC_CLK 4 3 CRT_CLK
6 CRT_DDC_CLK
S

2.2K_0804_8P4R_5%
Q27A
DMN66D0LDW-7_SOT363-6

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/03/19 Deciphered Date 2015/03/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT CONN.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A5WAM_Bay Trail M_LA‐B981P
Date: Monday, May 12, 2014 Sheet 24 of 47
A B C D E
 5 4 3 2 1

+3VALW J8 +3V_LAN
JUMP_43X39
1 2
@ 1 2
W=60mil
IDC=1200mA +LAN_VDD +3V_LAN
60mil U67
60mil W=60mil W=60mil
1 L52
300mA 1.4A
5 OUT +REGOUT 1 2
IN 2.2UH_NLC252018T-2R2J-N_5%

4.7U_0603_6.3V6K
C1215

.1U_0402_16V7K
C1216

.1U_0402_16V7K
C1217

.1U_0402_16V7K
C1218

.1U_0402_16V7K
C1219

.1U_0402_16V7K
C1220

.1U_0402_16V7K
C1221

1U_0402_6.3V6K
C1222

.1U_0402_16V7K
C1223

4.7U_0603_6.3V6K
C1224

.1U_0402_16V7K
C1225

.1U_0402_16V7K
C1226

.1U_0402_16V7K
C1227
2
4 GND
IN 1 1 1 1 1 1 1 1 1 1 1 1 1
2
3 LAN_PWR_EN 29
C1214 EN
D 1U_0402_6.3V6K G5243T11U_SOT23-5 2 2 2 2 2 2 2 2 2 2 2 2 2 D
1
Part Number = SA000028Y10

Using for Switch mode

From EC Place near Pin 3,8,33,46 Place near Pin 20 Using for Switch mode Place near Pin 11,32,48
The trace length from Lx to
PIN36 (REGOUT) and from C to Lx The trace length
High active.
EN threshold voltage min:1.2V typ:1.6V max:2.0V must < 200mils. from C to
Current limit threshold 1.5~2.8A +3V_LAN PIN35(VDDREG)
must < 200mils.
+3V_LAN Rising time must >0.5ms and <100ms

1
R1140
10K_0402_5%

U68

2
Power Manahement/Isolation Internal pull high
RS@ ISOLATEB 31
R1124 1 2 0_0402_5% LAN_PME# 39 ISOLATEBPIN
29 EC_PME# LANWAKEB Card Reader
15 SD_D0 R1126 1 2 0_0402_5% RS@ SD_D0_R
PCI-Express SD_D0/MS_D1 14 SD_D1 R1127 1 2 0_0402_5% RS@ SD_D1_R
CLK_PCIE_LAN 23 SD_D1 16 SD_CLK R1128 1 2 10_0402_5% SD_CLK_R
8 CLK_PCIE_LAN REFCLK_P SD_CLK/MS_D0
8 CLK_PCIE_LAN# CLK_PCIE_LAN# 24 17 SD_CMD R1125 1 2 0_0402_5% RS@ SD_CMD_R SD_CLK_R 2 1
REFCLK_N SD_CMD/MS_D2 18 SD_D3 R1129 1 2 0_0402_5% RS@ SD_D3_R
PLT_RST_BUF# 30 SD_D3/MS_D3 19 SD_D2 R1130 1 2 0_0402_5% RS@ SD_D2_R @EMC@ C1229 5P_0402_50V8C
15,26,29,30,8 PLT_RST_BUF# PERSTBPIN SD_D2/MS_CLK
LAN_CLKREQ# 29 28 SD_WP
7 LAN_CLKREQ# CLKREQBPIN MS_BS/SD_WP#
C1228,C1230 7 PCIE_PRX_DTX_P3
C1228 1 2 .1U_0402_16V7K PCIE_PRX_C_DTX_P3 25
HSOP
Reserve for EMI please close to IC
C C1230 1 2 .1U_0402_16V7K PCIE_PRX_C_DTX_N3 26 C
Place near Pin 25,26 7 PCIE_PRX_DTX_N3 HSON
7 PCIE_PTX_C_DRX_P3 21 42 SD_CD#
22 HSIP SD_CD# 43
7 PCIE_PTX_C_DRX_N3 HSIN MS_CD#
Transceiver Interface
LAN_MIDI0+ 1
26 LAN_MIDI0+ MDIP0
LAN_MIDI0- 2
26 LAN_MIDI0- MDIN0
LAN_MIDI1+ 4
26 LAN_MIDI1+ MDIP1 +3V_LAN
LAN_MIDI1- 5 48
26 LAN_MIDI1- MDIN1 HV_GIGA
LAN_MIDI2+ 6 11
26 LAN_MIDI2+ MDIP2 HV_GIGA
26 LAN_MIDI2-
LAN_MIDI2- 7
MDIN2 VDD33
12 1400mA
LAN_MIDI3+ 9 32
+3VS 26 LAN_MIDI3+ MDIP3 VDD33
LAN_MIDI3- 10
26 LAN_MIDI3- MDIN3
Write protect Write protect
1

R1131 XTLI 44 33 Card Detect

1K_0402_5% XTLO 1K_0402_5% 1 2 R1202 XTLO_R 45 CKXTAL1 Clock VDD10 3 300mA
+LAN_VDD      (Lock)      (Unlock)
CKXTAL2 AVDD10 8
AVDD10 Without Card Open Open Open
2

ISOLATEB Regulator and Reference

+REGOUT 36 20 Card Inserted Open Close Close
35 REG_OUT VDDTX
40mil +3V_LAN VDDREG
2

SWR mode 34
ENSWREG
800mA
R1132 +LAN_VDD 46 13 +CARD_3V3
LV_GEN CARD_3V3
15K_0402_5%
R1133 2 1 2.49K_0402_1% LAN_RST 47
RSET 27 +VDD33_18
10mil
1

DV33/18

.1U_0402_16V7K
C1231

4.7U_0603_6.3V6K
C1232

.1U_0402_16V7K
C1233
@ T198 41
GPO 38 LED0
LED1/GPO 1 1 1
37 LEDs
@ T199 LED2
40
B @ T200 LED_CR 49 @ B
E_PAD 2 2 2
+3V_LAN
Card Reader Connector
1 @ 2 Place near Pin 27 JREAD1
R1135 SD_D3_R 1
10K_0402_5% CD/DAT3
RTL8411B-CGT_QFN48_6X6
+CARD_3V3 SD_CMD_R 2
1 @ 2 GPO CMD
29 LAN_PHY_EN
R1197 3
0_0402_5% VSS1
Close to Card Reader CONN
4
VDD

4.7U_0603_6.3V6K
C1234

.1U_0402_16V7K
C1235
SD_CLK_R 5
CLK
1 1
6
VSS2
SD_D0_R 7
2 2 DAT0
Y10 SD_D1_R 8 12
25MHZ_10PF_7V25000014 DAT1 G1
SD_D2_R 9 13
XTLI 1 3 XTLO DAT2 G2
1 3 SD_CD# 10 14
GND GND CD G3
1 1
SD_WP 11 15
C1236 2 4 C1237 WP G4
15P_0402_50V8J 15P_0402_50V8J TAITW_PSDAT4-11GLBS1NN4H2
2 2 CONN@
SP07000ZC00

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/03/19 Deciphered Date 2015/03/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN RTL8411B-CG
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A5WAM_Bay Trail M_LA‐B981P
Date: Monday, May 12, 2014 Sheet 25 of 47
5 4 3 2 1
 A B C D E

LAN Connector
JRJ1

T210
RJ45_MIDI3- 8
1 LAN_TERMAL1 24 PR4- 1
LAN_MIDI3- 2 TCT1 MCT1 23 RJ45_MIDI3- RJ45_MIDI3+ 7
25 LAN_MIDI3- TD1+ MX1+ PR4+
25 LAN_MIDI3+ LAN_MIDI3+ 3 22 RJ45_MIDI3+
TD1- MX1- RJ45_MIDI1- 6
4 21 PR2-
LAN_MIDI2- 5 TCT2 MCT2 20 RJ45_MIDI2- RJ45_MIDI2- 5
25 LAN_MIDI2- TD2+ MX2+ PR3-
25 LAN_MIDI2+ LAN_MIDI2+ 6 19 RJ45_MIDI2+
TD2- MX2- RJ45_MIDI2+ 4
7 18 PR3+
LAN_MIDI1- 8 TCT3 MCT3 17 RJ45_MIDI1- RJ45_MIDI1+ 3
25 LAN_MIDI1- TD3+ MX3+ PR2+
25 LAN_MIDI1+ LAN_MIDI1+ 9 16 RJ45_MIDI1+
TD3- MX3- RJ45_MIDI0- 2
10 15 PR1- 10
LAN_MIDI0- 11 TCT4 MCT4 14 RJ45_MIDI0- RJ45_MIDI0+ 1 SHLD2 9
25 LAN_MIDI0- TD4+ MX4+ PR1+ SHLD1
25 LAN_MIDI0+ LAN_MIDI0+ 12 13 RJ45_MIDI0+
TD4- MX4-
JP40 @EMC@

75_0402_1%

75_0402_1%

75_0402_1%

75_0402_1%
B88069X9231T203_4P5X3P2-2

1
GST5009-E 2 1
SP050006B10 SANTA_130452-0B 40mil

R1136

R1137

R1138

R1139
1 DC234005310
CONN@ RJ45_GND 1 2 LANGND
C1238 C1239

2
.1U_0402_16V7K 40mil 10P_0402_50V8J
2

1
Place close to TCT pin LANGND

3
MESC5V02BD03_SOT23-3
JP@

D47
JUMP_43X118 JP42
JP41 @EMC@
RJ45_GND B88069X9231T203_4P5X3P2-2

EMC@

2
2 2

1
+3VS_WLAN
For Wireless LAN

2
+3VS_WLAN
R429
+3VS 60mil +3VS_WLAN
4.7K_0402_5%
+1.5VS_WLAN
JP8 JP@

1
JMINI1
2 1 1 1 29 WLAN_PME# 1 2
JUMP_43X118 @ 3 WAKE# 3.3V 4
C441 C458 C459 C460 5 NC GND 6
4.7U_0603_6.3V6K .1U_0402_16V7K .1U_0402_16V7K 7 NC 1.5V 8
470P_0402_50V7K 7 WLAN_CLKREQ# CLKREQ# NC
1 2 2 2 9 10
3
EMC@ GND NC 3
11 12
8 CLK_PCIE_WLAN# REFCLK- NC
13 14
8 CLK_PCIE_WLAN REFCLK+ NC
15 16
17 GND NC 18
19 NC GND 20
+1.5VS +1.5VS_WLAN NC NC WL_OFF# 29
JP9 21 22
GND PERST# PLT_RST_BUF# 15,25,29,30,8
JUMP_43X39 7 PCIE_PRX_DTX_N2 23 24
1 2 25 PERn0 +3.3Vaux 26
7 PCIE_PRX_DTX_P2
@ 1 2
1 27 PERp0 GND 28
@ 29 GND +1.5V 30 MINI1_SMBCLK R432 1 @ 2 0_0402_5%
GND SMB_CLK EC_SMB_CK2 13,14,15,29,9
C461 31 32 MINI1_SMBDATAR434 1 @ 2 0_0402_5% EC_SMB_DA2 13,14,15,29,9
7 PCIE_PTX_C_DRX_N2 PETn0 SMB_DATA
.1U_0402_16V7K 33 34
2 7 PCIE_PTX_C_DRX_P2 PETp0 GND
35 36
GND USB_D- USB20_Hub_N1 28
37 38
NC USB_D+ USB20_Hub_P1 28
+3VS_WLAN 39 40
41 NC GND 42
43 NC LED_WWAN# 44
45 NC LED_WLAN# 46
+3VS_WLAN 47 NC LED_WPAN# 48
+3VALW R1079 0_0402_5% 1 RS@ 2 49 NC +1.5V 50
29 E51TXD_P80DATA NC GND
U9 @ R1080 0_0402_5% 1 RS@ 2 51 52
29 E51RXD_P80CLK NC +3.3V
1 W=60mils
5 VOUT 53 54
VIN BT_ON# use RX to work. GND GND

1
2
4 GND R437 ACES_50709-0524W-P01
VIN 100K_0402_5% CONN@
1
@ 3 DC04000C400
WLAN_ON 29
2

C165 EN
1U_0402_6.3V6K G5243AT11U_SOT23-5
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/03/19 Deciphered Date 2015/03/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN/WLAN/BT
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A5WAM_Bay Trail M_LA‐B981P
Date: Monday, May 12, 2014 Sheet 26 of 47
A B C D E
 A B C D E

SATA Re-Driver HDD2 Conn. Reserve

+3VS
+3VS

0.01U_0402_16V7K
RD@ C1246

0.1U_0402_16V7K
RD@ C1247
R1180
1 1
SATA HDD2 Cable Conn.
4.7K_0402_5%
RD@
U69 2 2 CL 4.0 mm

2
1 7 10 1
EN VDD 20 JHDD2
SATA_PTX_DRX_P0 RD@ C1248 2 1 SATA_PTX_C_DRX_P0_1 0.01U_0402_16V7K 1 VDD 1
SATA_PTX_DRX_N0 RD@ C1249 2 1 SATA_PTX_C_DRX_N0_1 0.01U_0402_16V7K 2 A_INp 6 1 R1184 2 8527@ RDSATA_PTX_DRX_P0 C1244 1 2 RD@ 0.01U_0402_16V7K RDSATA_PTX_C_DRX_P0 2 1
A_INn NC 16 4.99K_0402_1% RDSATA_PTX_DRX_N0 C1242 1 2 RD@ 0.01U_0402_16V7K RDSATA_PTX_C_DRX_N0 3 2
SATA_PRX_DTX_P0 RD@ C1250 2 1 SATA_PRX_C_DTX_P0_1 0.01U_0402_16V7K 5 NC 4 3
SATA_PRX_DTX_N0 RD@ C1251 2 1 SATA_PRX_C_DTX_N0_1 0.01U_0402_16V7K 4 B_OUTp 9 APE0 RDSATA_PRX_DTX_N0 C1243 1 2 RD@ 0.01U_0402_16V7K RDSATA_PRX_C_DTX_N0 5 4
B_OUTn A_PRE0 8 BPE0 RDSATA_PRX_DTX_P0 C1245 1 2 RD@ 0.01U_0402_16V7K RDSATA_PRX_C_DTX_P0 6 5
APE1 19 B_PRE0 7 6
BPE1 17 A_PRE1 15 RDSATA_PTX_DRX_P0 8 7
B_PRE1 A_OUTp 14 RDSATA_PTX_DRX_N0 9 8
TEST 18 A_OUTn 10 9
R1190 TEST 10
3 11 RDSATA_PRX_DTX_P0 11
2 1 13 GND B_INp 12 RDSATA_PRX_DTX_N0 12 11
+3VS GND B_INn 12
21 +5VS_HDD 13
EPAD 14 13
4.7K_0402_5% 14

2
PS8520CTQFN20GTR2-A_TQFN20_4X4 15
@ R1192 R1193 RD@ 16 15
0_0402_5% 4.7K_0402_5% 17 16
8520@ 8527@ 18 17
19 18
Check BOM structure

1
20 19
21 20
22 G1
23 G2
24 G3
+3VS G4
ACES_50406-02071-001
R1181 1 RD@ 2 4.7K_0402_5% APE0 R1187 1 @ 2 4.7K_0402_5% APE0 CONN@
SP010016L00
R1182 1 RD@ 2 4.7K_0402_5% BPE0 R1188 1 @ 2 4.7K_0402_5% BPE0

2 R1183 1 @ 2 4.7K_0402_5% APE1 R1189 1 RD@ 2 4.7K_0402_5% APE1 2

R1185 1 @ 2 4.7K_0402_5% BPE1 R1191 1 RD@ 2 4.7K_0402_5% BPE1

R1186 1 @ 2 4.7K_0402_5% TEST R1194 1 RD@ 2 4.7K_0402_5% TEST

FAN1 Conn
SATA HDD1 Conn. +5VS C632
4.7U_0603_6.3V6K
1 2

JHDD1
SATA ODD Conn.
U31
1 1 8
C392 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_P0 2 GND JODD1 2 EN GND 7
7 SATA_PTX_DRX_P0 A+ VIN GND
7 SATA_PTX_DRX_N0 C393 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_N0 3 +VCC_FAN1 3 6
3 4 A- 1 4 VOUT GND 5 3
GND GND 29 EN_DFAN1 VSET GND
C391 1 2 0.01U_0402_16V7K SATA_PRX_C_DTX_N0 5 7 SATA_PTX_DRX_P1 C401 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_P1 2
7 SATA_PRX_DTX_N0 B- A+
C394 1 2 0.01U_0402_16V7K SATA_PRX_C_DTX_P0 6 7 SATA_PTX_DRX_N1 C402 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_N1 3 APE8875M_SO8
7 SATA_PRX_DTX_P0 B+ A-
7 4
+3VS GND C403 1 2 0.01U_0402_16V7K SATA_PRX_C_DTX_N1 5 GND  SA000050J00
7 SATA_PRX_DTX_N1 B-
C405 1 2 0.01U_0402_16V7K SATA_PRX_C_DTX_P1 6
7 SATA_PRX_DTX_P1 B+
8 7
9 V33 GND
10 V33 +5VS
11 V33 8
+5VS 12 GND R1154 1 RS@ 2 0_0805_5%
80mils +5VS_ODD 9 DP +3VS C629
13 GND 10 +5V 4.7U_0603_6.3V6K
GND +5V
10U_0603_6.3V6M

.1U_0402_16V7K
R1155 1 RS@ 2 0_0805_5% +5VS_HDD 14 1 1 ODD_MD 11 1 2
V5 MD

1
C404

C407
15 T185 12 14
16 V5 @ 13 GND GND 15 R516
17 V5 GND GND
GND 10K_0402_5%
18 2 2
19 Reserved 23 SANTA_201902-1_13P
40mil JFAN1

2
+5VS_HDD 20 GND GND 24 CONN@ +VCC_FAN1 1
21 V12 GND 25 SP01001RS00 2 1 4
V12 GND 29 FAN_SPEED1 2 GND
100mils 22 26 3 5
V12 GND 3 GND
1
EMC@
10U_0603_6.3V6M

1U_0402_6.3V6K

.1U_0402_16V7K

1 1 1 CCM_C127043HR022M27FZR_22P C630 ACES_88231-03041

C420

C161

C397

CONN@ .1U_0402_16V7K CONN@

DC010009X00 2 SP020020710
@
2 2 2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/03/19 Deciphered Date 2015/03/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD/ODD/FAN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A5WAM_Bay Trail M_LA‐B981P
Date: Monday, May 12, 2014 Sheet 27 of 47
A B C D E
 A B C D E

L24 EMC@ For ESD request +5VALW +USB3_VCCA

CMMI21T-900Y-N_4P
9 PCH_USB3_TX0_P 2 1 PCH_USB3_TX0_P_C 2
2 1
1 U3TXDP0 @EMC@ U25 W=60mils
C484 .1U_0402_16V7K D15 @EMC@ .1U_0402_16V7K1 2 C483 1 8
2 GND OUT 7
2 1 PCH_USB3_TX0_N_C 3 4 U3TXDN0 U3RXDN0 1 1 109 U3RXDN0 3 IN OUT 6
1
9 PCH_USB3_TX0_N 3 4 IN OUT 1
C482 .1U_0402_16V7K USB_PWR_EN# 4 5 R454 1 @ 2 0_0402_5%
EN/ENB OCB USB_OC0# 9
SM070003K00 U3RXDP0 2 2 98 U3RXDP0
SY6288D10CAC_MSOP8
U3TXDN0 4 4 77 U3TXDN0
L25 EMC@
CMMI21T-900Y-N_4P U3TXDP0 5 5 66 U3TXDP0
PCH_USB3_RX0_P 2 1 U3RXDP0
9 PCH_USB3_RX0_P 2 1 +USB3_VCCA
3 3

PCH_USB3_RX0_N 3 4 U3RXDN0 8 W=100mils

9 PCH_USB3_RX0_N 3 4

150U_D2_6.3VY_R17M
SM070003K00 L05ESDL5V0NA-4_SLP2510P8-10-9

1000P_0402_50V7K

.1U_0402_16V7K
C487 @EMC@

C994 @EMC@
1 2 2

C486
+

R458 1 RS@ 2 0_0402_5% 1 1

2 USB3.0 Conn.
L26 @EMC@
DLW21HN900HQ2L_4P JUSB1
2 1 USB20_P0_L 1
9 USB20_P0 2 1 VBUS
USB20_N0_L 2
USB20_P0_L 3 D-
3 4 USB20_N0_L 4 D+
9 USB20_N0 3 4 GND
U3RXDN0 5
SM070003Y00 U3RXDP0 6 StdA-SSRX- 10
7 StdA-SSRX+ GND 11
R461 1 RS@ 2 0_0402_5% U3TXDN0 8 GND-DRAIN GND 12
U3TXDP0 9 StdA-SSTX- GND 13
StdA-SSTX+ GND
ACON_TARAC-9V1391
2 CONN@ 2
DC23300AG00

+3VALW +3V_HUB
R259
0_0603_5%
+3V_HUB 1 RS@ 2

10U_0603_6.3V6M

.1U_0402_16V7K
1 1

C282

C281
1 2
C279 .1U_0402_16V7K C279 close to U72 pin5
1 2 C280 close to U72 pin9 2 2
C280 .1U_0402_16V7K
C283 close to U72 pin14
1 2 C284 close to U72 pin21
C283 .1U_0402_16V7K

1 2
C284 .1U_0402_16V7K
3 +3V_HUB USB/B Conn. 3

5
U72
1
(USB Port 1, Port2)
AVDD DM0 USB20_N1 9 +5VALW
9 2
AVDD DP0 USB20_P1 9
14 JUSB2
+3V_HUB 21 AVDD 3 1
+3V_HUB DVDD DM1 USB20_Hub_N1 26 1
27 4 To BT 2
V5 DP1 USB20_Hub_P1 26 2
28 3
V33 3
1

1 2 PSELF 6 USB20_Hub_N2 4
R261 100K_0402_5% R263 DM2 7 USB20_Hub_P2 USB_PWR_EN# 5 4
DP2 29 USB_PWR_EN# 5
R973 10K_0402_5% 18 6
1 2 HUB_DM4 0_0402_5% 26 TEST/SCL 12 USB20_Hub_N3 USB20_Hub_N2 7 6
R1134 1K_0402_5% PWREN1#/SDA DM3 13 USB20_Hub_P3 USB20_Hub_P2 8 7
Port4 disable.
2

1 2 HUB_DP4 1 @ 2 RESET# 17 DP3 9 8

29,37 SYSON RESET# 9
R1141 1K_0402_5% 2 15 HUB_DM4 USB20_Hub_N3 10
HUB_XIN 10 DM4 16 HUB_DP4 USB20_Hub_P3 11 10
1 2 OVCUR2# C285 HUB_XOUT 11 X1 DP4 Port4 disable. 12 11
R264 10K_0402_5% X2 25 13 12
1 2 OVCUR3#
Port2,3 is removable. 1
1U_0402_6.3V6K
PSELF 22 OVCUR1#/SMC 24 OVCUR2# 14 13
R265 10K_0402_5% PGANG 23 PSELF OVCUR2#/SMD 20 OVCUR3#
Port2,3 is removable. 14
PGANG OVCUR3# 19 ACES_88514-01201-071
OVCUR4# CONN@
29 8 RREF 2 1 SP01001BF00
1 2 PGANG GND RREF R260 680_0402_1%
R262 100K_0402_5%
GL850G-OHY32_QFN28_5X5

SA000066310, S IC GL850G‐OHY32 QFN 28P USB2.0 HUB
4 4

Y9
HUB_XIN 1 4 1
1
C287 C286
20P_0402_50V8 20P_0402_50V8
2 3 2 HUB_XOUT Security Classification Compal Secret Data Compal Electronics, Inc.
2
Issued Date 2014/03/19 Deciphered Date 2015/03/18 Title
12MHZ_18PF_7V12000001
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB Conn & Hub GL850G
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A5WAM_Bay Trail M_LA‐B981P
Date: Monday, May 12, 2014 Sheet 28 of 47
A B C D E
 A B C D E

+1.8VALW_EC +3VALW_EC

1
+3VLP +3VALW_EC L31 +EC_VCCA R1090 R1091
BLM15AG121SN1D_L0402_2P 0_0603_5% 0_0603_5%
1 RS@ 2 1 2 +EC_VCCA
+1.8VALW +1.8VALW_EC NTPM@ TPM@
1

2
.1U_0402_16V7K
C502

.1U_0402_16V7K
C503

.1U_0402_16V7K
C504

.1U_0402_16V7K
C505

1000P_0402_50V7K
C506 @EMC@

1000P_0402_50V7K
C507 @EMC@
R236 1 1 1 1 2 2

+VCC_LPC
0_0805_5% C508
.1U_0402_16V7K R237 1 RS@ 2 0_0805_5% +VCC_LPC
1 2 1
2 2 2 2 1 1 +3VALW_EC

@
ECAGND 34

+3VALW_EC LID_SW# R476 1 2 47K_0402_5%

111
125
R480 2 9012@ 1 47K_0402_5% EC_RST#

22
33
96

67
9
U28 +3V_PTP
C509 2 1 .1U_0402_16V7K

EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD0
EC_VDD/VCC

EC_VDD/AVCC
TP_CLK R478 1 2 4.7K_0402_5%
9012@ TP_DATA R479 1 2 4.7K_0402_5%

1 21 +3VS
+3VALW_EC 2 GATEA20/GPIO00 GPIO0F 23 BEEP#
8 EC_KBRST# KBRST#/GPIO01 BEEP#/GPIO10 BEEP# 31
3 26 EC_MUTE# R481 1 @ 2 10K_0402_5%
30,8 EC_SERIRQ 4 SERIRQ GPIO12 27 EC_CLR_CMOS
30,9 LPC_FRAME# LPC_FRAME# ACOFF/GPIO13
R484 1 @ 2 100K_0402_5% EC_PME# 5
30,9 LPC_AD3 LPC_AD3
7 PWM Output C510 2 1 100P_0402_50V8J ECAGND
30,9 LPC_AD2 LPC_AD2
R496 1 TPM@ 2 10K_0402_5% EC_SLP_S3# 8 63 BATT_TEMP
30,9 LPC_AD1 LPC_AD1 BATT_TEMP/AD0/GPIO38 BATT_TEMP 34
10 LPC & MISC 64 VCIN1_BATT_DROP
30,9 LPC_AD0 LPC_AD0 AD1/GPIO39 65 ADP_I
VCIN1_BATT_DROP
ADP_I 34,35
34 Reserve EC_CLR_CMOS for clear CMOS
+3VALW_EC 12 ADP_I/AD2/GPIO3A 66 AD_BID0
9 LPC_CLK_EC CLK_PCI_EC AD Input AD3/GPIO3B
RP12 13 75 WLAN_PME#
15,25,26,30,8 PLT_RST_BUF# PCIRST#/GPIO05 AD4/GPIO42 WLAN_PME# 26
1 8 EC_SMB_CK1 EC_RST# 37 76 EC_PME#
EC_RST# IMON/AD5/GPIO43 EC_PME# 25
2 7 EC_SMB_DA1 20 CLR_CMOS# 8
8 EC_SCI# EC_SCII#/GPIO0E
3 6 EC_SMB_CK2 38
26 WLAN_ON GPIO1D
+3VS 4 5 EC_SMB_DA2

1
68 LAN_PWR_EN
DAC_BRIG/GPIO3C LAN_PWR_EN 25 D
2.2K_0804_8P4R_5% DA Output 70 EN_DFAN1
+1.8VALW_EC EN_DFAN1/GPIO3D EN_DFAN1 27
KSI0 55 71 TP_EN TP_EN 30 EC_CLR_CMOS 2 Q51
KSI1 56 KSI0/GPIO30 IREF/GPIO3E 72 KBL_EN# G
KSI1/GPIO31 CHGVADJ/GPIO3F KBL_EN# 30 2N7002K_SOT23-3

2
KSI2 57 S @
R488 1 9022@ 2 10K_0402_5% EC_SMI# KSI3 58 KSI2/GPIO32 83 EC_MUTE# R483

3
R492 1 9022@ 2 10K_0402_5% EC_SCI# KSI4 59 KSI3/GPIO33 EC_MUTE#/GPIO4A 84 USB_PWR_EN# EC_MUTE# 31
KSI4/GPIO34 USB_EN#/GPIO4B USB_PWR_EN# 28 10K_0402_5%
2 R494 1 9022@ 2 10K_0402_5% EC_LID_OUT# KSI5 60 85 EC_I2C_TPCLK 2
KSI5/GPIO35 CAP_INT#/GPIO4C EC_I2C_TPCLK 30 @
KSI6 61 PS2 Interface 86 EC_I2C_TPDAT
EC_I2C_TPDAT 30

1
KSI7 62 KSI6/GPIO36 EAPD/GPIO4D 87 TP_CLK
+3VALW_EC KSI7/GPIO37 TP_CLK/GPIO4E TP_CLK 30
KSO0 39 88 TP_DATA
KSO0/GPIO20 TP_DATA/GPIO4F TP_DATA 30
KSO1 40
KSO2 41 KSO1/GPIO21
R489 1 9012@ 2 10K_0402_5% EC_SMI# KSI[0..7] KSO3 42 KSO2/GPIO22 97 ENBKL
30 KSI[0..7] KSO3/GPIO23 CPU1.5V_S3_GATE/GPXIOA00 ENBKL 6
R493 1 9012@ 2 10K_0402_5% EC_SCI# KSO4 43 98
KSO[0..17] KSO4/GPIO24 WOL_EN/GPXIOA01 TP_PWR_EN 30
R495 1 9012@ 2 10K_0402_5% EC_LID_OUT# KSO5 44 99
30 KSO[0..17]
KSO6 45 KSO5/GPIO25 Int. K/B ME_EN/GPXIOA02 109 VCIN0_PH
TXE_DBG 7
KSO7 46 KSO6/GPIO26 Matrix VCIN0_PH/GPXIOD00 VCIN0_PH 34
H_PROCHOT#_EC R1169 1 RS@ 2 0_0402_5%
KSO7/GPIO27 SPI Device Interface
KSO8 47
@EMC@ KSO9 48 KSO8/GPIO28 119 EC_MISO
KSO9/GPIO29 SPIDI/GPIO5B EC_MISO 8
C511 1 2 0.01U_0402_16V7K PLT_RST_BUF# KSO10 49 120 EC_MOSI R482 2 RS@ 1 0_0402_5% H_PROCHOT# 7
KSO10/GPIO2A SPIDO/GPIO5C EC_MOSI 8 40 VR_HOT#
KSO11 50 SPI Flash ROM 126 EC_SPICLK
KSO11/GPIO2B SPICLK/GPIO58 EC_SPICLK 8

1
KSO12 51 128 EC_SPICS#
KSO12/GPIO2C SPICS#/GPIO5A EC_SPICS# 8 D
ESD request KSO13 52
KSO13/GPIO2D
KSO14 53 H_PROCHOT#_EC 2 Q50
EMC@ KSO15 54 KSO14/GPIO2E 73 GPU_ALERT G
KSO15/GPIO2F ENBKL/AD6/GPIO40 GPU_ALERT 15 2N7002K_SOT23-3
C1157 2 1 0.047U_0402_25V7K PMC_CORE_PWROK KSO16 81 74 TP_INT#_EC S 9012@
KSO16/GPIO48 PECI_KB930/AD7/GPIO41 TP_INT#_EC 30
KSO17 82 89 GPU_OVERT
GPU_OVERT 15

3
KSO17/GPIO49 FSTCHG/GPIO50 90 BATT_BLUE_LED#
BATT_CHG_LED#/GPIO52 BATT_BLUE_LED# 30
91
CAPS_LED#/GPIO53
Charger and BATT 34,35 EC_SMB_CK1
77
EC_SMB_CK1/GPIO44 GPIO PWR_LED#/GPIO54
92 PWR_LED PWR_LED 30
78 93 BATT_AMB_LED#
34,35 EC_SMB_DA1 EC_SMB_DA1/GPIO45 BATT_LOW_LED#/GPIO55 BATT_AMB_LED# 30
79 SM Bus 95 SYSON Latest design guide suggest change to
13,14,15,26,9 EC_SMB_CK2 EC_SMB_CK2/GPIO46 SYSON/GPIO56 SYSON 28,37
To SOC 13,14,15,26,9 EC_SMB_DA2
80
EC_SMB_DA2/GPIO47 VR_ON/GPIO57
121 VR_ON
VR_ON 40
127 74LVC1G06.
PM_SLP_S4#/GPIO59

6 100 EC_RSMRST#
8 EC_SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 EC_RSMRST# 8
14 101 EC_LID_OUT#
3 PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXIOA04 EC_LID_OUT# 8 3
15 102 VCIN1_PROCHOT R509 2 RS@ 1 0_0402_5% ACIN 35,8
8 EC_SMI# EC_SMI#/GPIO08 PROCHOT_IN/GPXIOA05 VCIN1_PROCHOT 34
16 103 H_PROCHOT#_EC
22 TS_RST# GPIO0A H_PROCHOT#_EC/GPXIOA06 H_PROCHOT#_EC 34
22 TS_EN 17 104 MAINPWON EMC@
GPIO0B VCOUT0_PH/GPXIOA07 MAINPWON 34,36
18 GPO 105 EC_BKOFF# EC_ACIN C512 2 1 100P_0402_50V8J
+3VS 26 WL_OFF# GPIO0C BKOFF#/GPXIOA08 EC_BKOFF# 22
19 GPIO 106 LAN_PHY_EN
15 DGPU_HOLD_RST#_EC GPIO0D PBTN_OUT#/GPXIOA09 LAN_PHY_EN 25
25 107 DGPU_AC_DETECT
36,38,39 SPOK EC_INVT_PWM/GPIO11 PCH_APWROK/GPXIOA10 DGPU_AC_DETECT 15
28 108
R486 1 2 10K_0402_5% GPU_ALERT 27 FAN_SPEED1 29 FAN_SPEED1/GPIO14 SA_PGOOD/GPXIOA11
32 DGPU_PWR_EN_EC EC_PME#/GPIO15
30
26 E51TXD_P80DATA EC_TX/GPIO16
R487 1 2 10K_0402_5% GPU_OVERT 31 110 EC_ACIN
26 E51RXD_P80CLK EC_RX/GPIO17 AC_IN/GPXIOD01
32 112 EC_ON
8 PMC_CORE_PWROK PCH_PWROK/GPIO18 EC_ON/GPXIOD02 EC_ON 36
34 114 ON/OFFBTN#
30 PWR_SUSP_LED# SUSP_LED#/GPIO19 ON/OFF/GPXIOD03 ON/OFFBTN# 30
36 GPI 115 LID_SW#
NUM_LED#/GPIO1A LID_SW#/GPXIOD04 LID_SW# 30 +3VALW_EC
116 SUSP#
SUSP#/GPXIOD05 SUSP# 10,32,37,38,39
117 VGATE
GPXIOD06 VGATE 40 +1.8VALW_EC
118
PECI_KB9012/GPXIOD07
AGND/AGND

122
8 PBTN_OUT# XCLKI/GPIO5D
123 124 +V18R R1092 1 RS@ 2 0_0603_5%
GND/GND
GND/GND
GND/GND
GND/GND

8 EC_SLP_S4# XCLKO/GPIO5E V18R

2
1
For 9022 +V18R, +EC_VCCLPC can be
GND0

@ @
C515 changed to 1.8V if supports 1.8V I/F R696 R697
4.7U_0603_6.3V6K 10K_0402_5% 10K_0402_5%
KB9012QF-A4_LQFP128_14X14 2 9012@
11
24
35
94
113

69

1
Part Number = SA00004OB30 20mil VCIN0_PH
9012@ VCIN1_PROCHOT
ECAGND 1 2
+3VALW_EC L32
Board ID BLM15AG121SN1D_L0402_2P
Analog Board ID definition,
2

Please see page 3. EMC@

4
Ra R503 U28 EC_RSMRST# C1156 1 2 .1U_0402_16V7K
4
100K_0402_1% Phase Revision BID0 9022@
For ESD request
1

AD_BID0 EVT 0.1 10 KB9022QD_LQFP128_14X14

1

1 * PVT 0.2 11 SA000075S30

R506 @
Rb 160K_0402_1% C517
2
.1U_0402_16V7K Security Classification Compal Secret Data Compal Electronics, Inc.
2

Issued Date 2014/03/19 Deciphered Date 2015/03/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EC ENE KB9012/KB9022
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
PVT modify DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A5WAM_Bay Trail M_LA‐B981P
Date: Monday, May 12, 2014 Sheet 29 of 47
A B C D E
 A B C D E

+3VALW +3V_PTP
U10 W=20mils H3 H4 H9 H10 H11 H8 H17 FD1 FD2
1 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0
5 VOUT
KB Conn. VIN
1 @ @

1
2

1
4 GND C368 FIDUCIAL_C40M80 FIDUCIAL_C40M80
JKB1 VIN 4.7U_0603_6.3V6K
1 2
3 +3V_PTP FD3 FD4
KSO0 1 C141 EN @ @ @ @ @ @ @
KSO1 2 1 1U_0402_6.3V6K G5243AT11U_SOT23-5
KSO2 3 2 2 TP_SDATA 1 2 H13 H14 H15 @ @

1
KSO3 4 3 R1156 2.2K_0402_5% H_4P0 H_4P0 H_4P0
1 KSO4 5 4 TP_SCLK 1 2 FIDUCIAL_C40M80 FIDUCIAL_C40M80 1
5 29 TP_PWR_EN
KSO5 6 R1157 2.2K_0402_5%
KSO6 7 6 TP_INT#_R 2 1

1
KSO7 8 7 R633 10K_0402_5%
KSO8 9 8
KSO9 10 9 H5 H6 H16 H20 H27
KSO10 11 10 +3V_PTP @ @ @ H_3P0 H_6P5 H_4P0 H_4P0 H_3P7
KSO11 12 11
KSO12 13 12 H22 H23
KSO13 14 13 TP module Conn. R1170 1 @ 2 0_0402_5% +3VALW H_3P0N H_3P0X3P5N

1
KSO14 15 14
KSO15 16 15 R1171 1 @ 2 0_0402_5%
16 +3VS
KSO16 17 R1164 1 RS@ 2 0_0402_5% TP_SDATA @ @
9 I2C2_SDA_TP

1
KSO17 18 17 JTP1 @ @ @ @ @
KSI0 19 18 8 C663 1 2 .1U_0402_16V7K R1165 1 RS@ 2 0_0402_5% TP_SCLK
19 8 9 I2C2_SCL_TP
KSI1 20 9 7 TP_CLK
20 G2 7 TP_CLK 29
KSI2 21 10 6 TP_DATA
21 G1 6 TP_DATA 29
KSI3 22 5 R1167 1 @ 2 0_0402_5%
22 5 29 EC_I2C_TPDAT
KSI4 23 4 TP_SDATA
KSI5 24 23 4 3 TP_SCLK R1168 1 @ 2 0_0402_5%
24 3 29 EC_I2C_TPCLK
KSI6 25 27 2 TP_INT#_R
KSI7 26 25
26
G1
G2
28 2
1
1 TP_EN TP_EN 29 LED
CVILU_CF31081D0R4-10-NH R1163 1 2 0_0402_5% TP_INT#_R
29 TP_INT#_EC
E-T_6905-E26N-01R CONN@
CONN@
SP01000IJ00 +1.8VS LED6 +3VALW

TP_CLK 29 BATT_BLUE_LED# BATT_BLUE_LED# 1 2 1 2

KSI[0..7] TP_DATA B R699 200_0402_1%
KSI[0..7] 29

1
KSO[0..17] 1 1 BATT_AMB_LED# 3 4 1 2
2 KSO[0..17] 29 29 BATT_AMB_LED# A 2
R1166 @EMC@ @EMC@ R698 390_0402_5%
2.2K_0402_5% C551 C553

2
G
100P_0402_50V8J 100P_0402_50V8J LTST-C295TBKF-CA_AMBER-BLUE
2 2 LED7

2
TP_INT# 3 1 TP_INT#_R
8 TP_INT#
PWR_LED# 1 2 1 2

D
Q77 B R700 200_0402_1%
MESS138W-G_SOT323-3
29 PWR_SUSP_LED# PWR_SUSP_LED# 3 4 1 2
A R701 390_0402_5%

LTST-C295TBKF-CA_AMBER-BLUE

KB BackLight Conn. Reserve
BL@
Q44
+5VS DMG2301U-7_SOT23-3
JBL1

D
3 1+5VS_BL 4 6
PWR/B Conn. 3 4
3
G2
G1
5
2 PWR_LED#
JPWR1 +5VALW 1 2

G
2
1

1
1 +3VALW BL@
1 2 1
100K_0402_5% 2 R451 KBL_EN_R ACES_50504-0040N-001 D
2 +3VLP
3 LID_SW# LID_SW# 29 SP01000Z300 29 PWR_LED 2 Q17
3 4 PWR_LED# CONN@ G
4 2N7002K_SOT23-3

2
.1U_0402_16V7K

.1U_0402_16V7K
7 5 ON/OFFBTN# S
G1 5

C525

C524
8 6 1 1 R452

3
G2 6
RS@ 100K_0402_5%
ACES_51524-0060N-001 29 KBL_EN# 1 2
SP010014M10 @ @

1
3 CONN@ R592 2 2 3
0_0402_5%

+3VALW +3VALW_TPM
TPM Reserve +3VS_TPM
+3VALW_TPM +3VS_TPM
TPM@ U70 TPM@
0_0603_5% 1 2 R1203 5
1 VSB 10
ON/OFF BTN GPIO0/XOR_OUT VDD

1
+3VLP
10U_0603_6.3V6M

.1U_0402_16V7K

2 19
GPIO1 VDD
C421 TPM@

C398 TPM@

1 1 R517 TPM@ 6 24
Test only EMC@
C408 1 2 .1U_0402_16V7K
10K_0402_5% 0_0402_5% 1 @ 2 R1172 TPM_BADD 9
15
GPIO2/GPX
GPIO3/BADD
VDD
8
9 LPC_CLKRUN# GPIO4/CLKRUN# TEST

2
2 2 LPC_CLKRUN# 26
29,9 LPC_AD0 LAD0/MISO
2

near Pin5 23
29,9 LPC_AD1 LAD1/MOSI
R534 20 3
29,9 LPC_AD2 LAD2/SPI_IRQ# NC
SW1 @ 100K_0402_5% 17 12
29,9 LPC_AD3 LAD3 NC
TJE-532QR5_6P 13
1 3 NC 14
Internal PU
1

+3VS +3VS_TPM 28 NC
Internal PU LPCPD#
2 4 ON/OFFBTN# BADD SELECTION 21
ON/OFFBTN# 29 9 LPC_CLK_TPM LCLK/SCLK
TPM@ 22
29,9 LPC_FRAME# LRFAME#/SCS#
0_0603_5% 1 2 R1204 0 EEh ‐ EFh 15,25,26,29,8 PLT_RST_BUF# 16 4
5
6

27 LRSET#/SPI_RST# GND 11
29,8 EC_SERIRQ SERIRQ GND
10U_0603_6.3V6M

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

7 18
* 1 7Eh ‐ 7Fh PP GND
C422 TPM@

C399 TPM@

C400 TPM@

C406 TPM@

1 1 1 1 25
GND
4 4
NPCT650AA0WX_TSSOP28
2 2 2 2 @EMC@ @EMC@ SA00007IO00
SW2 DBG@ near Pin10,19,24 LPC_CLK_TPM R148 1 2 33_0402_5% C175 1 2 22P_0402_50V8J
TJE-532QR5_6P
1 3

2 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/03/19 Deciphered Date 2015/03/18 Title
5
6

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
KB/TP/LED/TPM/Screw Hole
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A5WAM_Bay Trail M_LA‐B981P
Date: Monday, May 12, 2014 Sheet 30 of 47
A B C D E
 A B C D E

HD Audio Codec +5VS +VDDA

PVT modify Int. Speaker Conn.
J1 40mil
SM01000EJ00 3000ma 220ohm@100mhz DCR 0.04 40mil
+PVDD_HDA 40mil 1 2 40mil JSPK1
1 SPKR+ EMC@ R1094 1 2 PBY160808T-121Y-N_2P SPK_R+ 1
1
+VDDA
L51 2 1 JUMP_43X118 4.75V SPKR- EMC@ R1095 1 2 PBY160808T-121Y-N_2P SPK_R- 2
2
HCB2012KF-221T30_2P C1185 @ SPKL+ EMC@ R1096 1 2 PBY160808T-121Y-N_2P SPK_L+ 3 5
3 G1

10U_0603_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z
0.1U_0402_16V4Z SPKL- EMC@ R1097 1 2 PBY160808T-121Y-N_2P SPK_L- 4 6
1 1 (output = 300 mA) 4 G2

1
2

C1186

C1187

C1188
@EMC@
ACES_88266-04001

2
@ SP02000K200 GND

2
2 2

MESC5V02BD03_SOT23-3

MESC5V02BD03_SOT23-3
GND CONN@

D41 @EMC@

D42 @EMC@
+AVDD1_HDA
1 1
Place near Pin41 Place near Pin46 20mil
GND R1093 1 RS@ 2 0_0603_5%
+VDDA
1 1

1
1
+1.5VS_DVDDIO

0.1U_0402_16V4Z
C1189

0.1U_0402_16V4Z
C1190

10U_0603_6.3V6M
C1191
GND
R1201 1 RS@ 2 0_0603_5% 20mil
+1.5VS

2
2 @ 2 GND GND

1U_0402_6.3V6K

0.1U_0402_16V4Z
2 1

C2141

C1192
+MICBIAS2
Place near Pin26 GNDA
1 2 Int. MIC Reserve

2
+1.5VS_VDDA R1099 1 RS@ 2 0_0603_5% @ R1195
+3VS_DVDD +1.5VS
Place near Pin9 GND 1 2.2K_0402_5%

1
0.1U_0402_16V4Z
C1193

10U_0603_6.3V6M
C1194
15mil @EMC@
15mil JMIC1
20mil

1
+3VS R1098 1 RS@ 2 0_0603_5% INT_MIC_R R1196 1 2 0_0603_5% INT_MIC_R_1 1

2
2 2 1
2
10U_0603_6.3V6M

1 1 0.1U_0402_16V4Z 1
C1195

C1196 GNDA C1252

@EMC@ 3
220P_0402_50V7K 4 G1
2 2
Place near Pin40 2 G2

41

46

26

40
1

9
U66 ACES_88266-02001
SP020008Y00

DVDD

DVDD-IO

PVDD1

PVDD2

AVDD1

AVDD2
Place near Pin 1 GND GND CONN@
GNDA
Internal MIC Reserve LINE1-L 22
LINE1-R 21 LINE1-L(PORT-C-L) 43 SPKL- +3VS +3VS
2 INT_MIC_R 2 @ 1 INT_MIC C770 1 2 LINE2_C_L LINE1-R(PORT-C-R) SPK-OUT-L-
SPK-OUT-L+
42 SPKL+ Digital MIC MIC2 @ 2
R726 1K_0402_5% @ 4.7U_0603_6.3V6K 24 6 5 DMIC_DATA
C62 1 2 C769 1 2 LINE2_C_R 23 LINE2-L(PORT-E-L) 45 SPKR+ MIC1 @ VDD DATA
GNDA LINE2-R(PORT-E-R) SPK-OUT-R+
@EMC@ 1000P_0402_50V7K @ 4.7U_0603_6.3V6K 44 SPKR- 6 5 DMIC_DATA_S 2 4 DMIC_CLK
RING2 17 SPK-OUT-R- VDD DATA CS CLK
SLEEVE 18 MIC2-L(PORT-F-L) /RING2 2 4 DMIC_CLK 2 R1199 1 1 3
Combo MIC 40mil MIC2-R(PORT-F-R) /SLEEVE CS CLK ENHANCE GND

3
32 HP_LEFT 0_0402_5%
HPOUT-L(PORT-I-L)

2
+MICBIAS +MICBIAS 31 33 HP_RIGHT 1 3 2DMIC@ S MIC ST MP45DT02TR
LINE1-VREFO-L HPOUT-R(PORT-I-R) ENHANCE GND

MESC5V02BD03_SOT23-3
+MICBIAS2 +MICBIAS2 30
LINE1-VREFO-R
SYNC
10 HDA_SYNC_AUDIO HDA_SYNC_AUDIO 7 S MIC ST MP45DT02TR
Main

2
D43 @EMC@

0_0402_5%
R1198 1DMIC@

0.1U_0402_16V4Z

0_0402_5%
R1200 1DMIC@
DMIC_DATA 2 6 HDA_BITCLK_AUDIO 2
GPIO0/DMIC-DATA BCLK HDA_BITCLK_AUDIO 7

C2140
DMIC_CLK 3
GPIO1/DMIC-CLK 1 @EMC@2
R1100
1
0_0402_5%
2 C1197 @EMC@
22P_0402_50V8J
GND Slave 1
D48
MESC5V02BD03_SOT23-3
EC_MUTE# 47
ALC283-CG 5 HDA_SDOUT_AUDIO HDA_SDOUT_AUDIO 7 @EMC@

1
HDA_RST_AUDIO# 11 PDB SDATA-OUT 8 HDA_SDIN0_AUDIO 1 2 @
HDA_SDIN0 7

1
RESETB SDATA-IN
48
R1102 33_0402_5%
左聲道 右聲道
SPDIF-OUT/GPIO2 +MIC2_VREFO
MONO_IN 12
PCBEEP 16
Close codec MONO-OUT
HP_PLUG# R1103 2 1 39.2K_0402_1% SENSE_A 13
14 SENSE A LDO3_CAP C1198 2 1 10U_0603_6.3V6M +MIC2_VREFO
10mil SENSE B GND
1 29
CBP 37 MIC2-VREFO
C1199 CBN 35 CBP 7 LDO2_CAP C1200 2 1 10U_0603_6.3V6M
CBN LDO3-CAP GNDA

1
2.2U_0402_6.3V6M 39
2 LDO2-CAP 27 LDO1_CAP C1201 2 1 10U_0603_6.3V6M HPOUT_L_2 R1107 R1108
LDO1-CAP GNDA
+3VS_DVDD 36 HPOUT_R_2 2.2K_0402_5% 2.2K_0402_5%
CPVDD R1104 1 2 100K_0402_5% 10mil

2
28 CODEC_VREF L57 EMC@

2
VREF

MESC5V02BD03_SOT23-3
+3VS 100K_0402_5% 2 @ 1 R1123 CPVREF 20 1 1 1 SLEEVE_L 1 2 SLEEVE
CPVREF

0.1U_0402_16V4Z
C1203

2.2U_0402_6.3V6M
C1204

10U_0603_6.3V6M
C1205

D45
15 JDREF 20K_0402_1% 1 2 R1106 GNDA BLM15PX330SN1D_2P
3 10U_0603_6.3V6M 2 1 C1202 MIC_CAP 19 JDREF 34 CPVEE RING2_L 1 2 RING2 3
GNDA MIC-CAP CPVEE BLM15PX330SN1D_2P
Close codec

2
2 2 2

@EMC@

680P_0402_50V7K

680P_0402_50V7K
1 1 1 L58 EMC@

AZ5123-02S.R7G_SOT23-3

C2143 EMC@

C2142 EMC@
4
49 DVSS 25 C1206
Thermal PAD AVSS1

D46
38 2.2U_0402_6.3V6M

1
AVSS2 2 2 2

EMC@
ALC283-CG_MQFN48_6X6 Place next pin27 GND
GND
GND

1
GNDA GNDA
R1111 C1207 GND
47K_0402_5% 1U_0402_6.3V6K GND Headphone Jack
2 @ 1 BEEP#_R 1 2 MONO_IN
29 BEEP# +3VLP JHP1
RING2_L 3
2
100P_0402_50V8J

R1114 1 HP_LEFT R1109 1 2 0_0603_5% HPOUT_L_1 R1110 1 2 59_0603_1% HPOUT_L_2 1

C1208 @EMC@

4.7K_0402_5%

47K_0402_5%
R1115

2 1
9 SOC_SPKR
2
100K_0402_5%
R1118

HP_PLUG# 5
2
1

RING2 HP_RIGHT R1112 1 2 0_0603_5% HPOUT_R_1 R1113 1 2 59_0603_1% 6

DMN66D0LDW-7_SOT363-6

HPOUT_R_2 2
1

D
5 G LINE1-L C1209 1 2 4.7U_0603_6.3V6K SLEEVE_L 4
@ S
2 2 7
6
DMN66D0LDW-7_SOT363-6

GNDA R1119 2 1 10K_0402_5% Q75A LINE1-R C1210 1 2 4.7U_0603_6.3V6K C1211 C1212

29 EC_MUTE#
4

D
2 G @EMC@ @EMC@
R1122 2 1 10K_0402_5% S +MICBIAS D44 330P_0402_50V7K 330P_0402_50V7K SINGA_2SJ3080-001111F
7 HDA_RST_AUDIO# 1 1
J2 J3 Q75B 2 R1120 2 1 4.7K_0402_5% GNDA DC23000B300
1

4 JUMP_43X39 JUMP_43X39 CONN@ 4

1 2 1 2 1
@ 1 2 @ 1 2
GNDA
J4 J5 3 R1121 2 1 4.7K_0402_5%
JUMP_43X39 JUMP_43X39 GNDA
1 2 1 2 BAT54A-7-F_SOT23-3
@ 1 2 @ 1 2
GNDA
J6 J7
JUMP_43X39 JUMP_43X39 To solve the background noise while combo jack Security Classification Compal Secret Data Compal Electronics, Inc.
1 2 1 2 2014/03/19 2015/03/18 Title
@ 1 2 @ 1 2 connecting to an active Issued Date Deciphered Date
speaker and system entry into S3/S4/S5 without analog
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HD Audio Codec_ALC283-CG
power AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
GND GNDA GND GNDA Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A5WAM_Bay Trail M_LA‐B981P
Date: Monday, May 12, 2014 Sheet 31 of 47
A B C D E
 A B C D E

VIH=1.2~5.5V Rise Time:

3.3V@100k/0.1uF=3.538ms 3.3V@330pF = 889.68us
U11 JP36JP@
3.3V@120k/0.1uF=4.272ms 1 14 +3VS_OUT 5.0V@330pF = 1348us
R927
100K_0402_5%
+3VALW
2 VIN1
VIN1
VOUT1
VOUT1
13
C976 JUMP_43X118
+3VS
+1.0VALW TO +1.0VS
SUSP# 2 1 3VS_ON 3 12 2 1 330P_0402_50V7K
ON1 CT1
0708:Change to SB00000PZ00 / need apply footprint
C980 2 1 4 11 +5VALW
+5VALW VBIAS GND +1.0VALW
.1U_0402_16V7K U60 +1.0VS
1 2 5VS_ON 5 10 2 1 ME4856_SO8
ON2 CT2

2
1 R926 330P_0402_50V7K 8 1 1
0701 update 120K_0402_5% +5VALW 6
VIN2 VOUT2
9 C967 JP37JP@ 2 7 2 2 R1057
1 2 7 8 +5VS_OUT +5VS C1129 6 3 C1130 100K_0402_5%
C979 VIN2 VOUT2 4.7U_0603_6.3V6K 5 4.7U_0603_6.3V6K
.1U_0402_16V7K 15 JUMP_43X118

1
GPAD 1 1 SUSP
37 SUSP

2
TPS22966DPUR_SON14_2X3 B+
@

3
2 @ 1 R1052
R1081 470_0603_5%
+5VALW 10K_0402_5% Q2002B
U11,U59 change to SA00006FD00, S IC APE8990GN3B DFN 14P DUAL LOAD SW

1
5 DMN66D0LDW-7_SOT363-6
10,29,37,38,39 SUSP#
2 1 1.0VS_GATE +1.0VS_R

1
VIH=1.2~5.5V Rise Time: R1061

4
3.3V@82k/0.1uF=3.042ms 1.8V@330pF = 485.28us 10K_0402_5% 1 D R1059

1
U59 JP38JP@ C1131 2 SUSP 10K_0402_5%
3.3V@47k/0.1uF=1.893ms 1 14 +1.8VS_OUT 1.35V@330pF = 363.96us R1082 .1U_0402_16V7K G
+1.8VALW VIN1 VOUT1 +1.8VS
R1055 2 13 10K_0402_5% S Q71 @

2
82K_0402_5% VIN1 VOUT1 C1123 JUMP_43X79 SUSP 2 @ 2 2N7002K_SOT23-3

3
SUSP# 2 1 1.8VS_ON 3 12 2 1 330P_0402_50V7K

2
ON1 CT1 Q2002A

1
C1125 1 2 +5VALW 4 11 DMN66D0LDW-7_SOT363-6
VBIAS GND
0701 update .1U_0402_16V7K
2 1 1.35VS_ON 5 10 2 1
R1056 ON2 CT2 330P_0402_50V7K
47K_0402_5% +1.35V_L 6 9 C1127 JP39JP@
1 2 7 VIN2 VOUT2 8 +1.35VS_OUT
VIN2 VOUT2 +1.35VS
C1128
.1U_0402_16V7K 15 JUMP_43X79
GPAD @JP2
@ JP2
TPS22966DPUR_SON14_2X3 +1.05VS 1 2 +1.0VS
1 2
JUMP_43X118

2 2

+1.05VS to +1.05VSDGPU
160mil
+1.05VS +1.05VSDGPU
U40
+3VS to +3VSDGPU_AON for GPU AO4478L_SO8
8 1
7 2 +VGA_CORE

10U_0603_6.3V6M
C613
6 3

1
+3VS +3VSDGPU_AON

C617
10U_0603_6.3V6M

0.1U_0603_25V7K
C683
5 1

2
U12 VGA@ 100mil(1.5A) VGA@ VGA@
1 VGA@ VGA@ VGA@ R514 R572

4
5 OUT 47_0402_5% 47_0603_5%

2
IN 2 @
2
2 +VGA_CORE_R

1
4 GND C621 +1.05VSDGPU_R
IN VGA@
2 10mil

1
C620 3 1 4.7U_0603_6.3V6K
4.7U_0603_6.3V6K EN 10mil R469 1 VGA@ 2 20K_0402_1% 1.05VSDGPU_GATE D
B+
VGA@ G5243T11U_SOT23-5 DGPU_PWR_EN# 2
1 VGA@ 5 VGA_PWROK# G
1

6
C622 Q1007B S
0.1U_0603_25V7K DMN66D0LDW-7_SOT363-6

3
VGA@ Q35
DGPU_PWR_EN VGA_PWROK# 2 2 2N7002K_SOT23-3
Q1007A @
DMN66D0LDW-7_SOT363-6 VGA@

1
3 3

DVT modify 11/20

+5VALW +3VLP +5VALW change to +3VLP
EC/3.3V GPU/3.3V +1.5VSDGPU

2
R1038 1 @ 2 0_0402_5% DGPU_PWR_EN @ VGA@
29 DGPU_PWR_EN_EC
R1039 R1040

2
100K_0402_5% 100K_0402_5%
PVT modify R571
47_0603_5%
1

1
DGPU_PWR_EN# VGA_PWROK# @
+1.8VS +1.8VALW +3VS

1
Q33 Q34
1

2N7002K_SOT23-3 1 2N7002K_SOT23-3
1

@ D D VGA@ +1.5VSDGPU_R
1

R2023 DGPU_PWR_EN 2 2
43 DGPU_PWR_EN VGA_PWROK 15,42,43

1
R2021 10K_0402_5% G G
5

2
1K_0402_5% U63 VGA@ S S Q45 D
1
GPU/3.3V R1041 VGA@ 2 VGA_PWROK#
SOC/1.8V 2N7002K_SOT23-3
P

NC 4 DGPU_PWR_EN @ R1042 @ G
2

DGPU_PWR_EN_SOC1.8V 2 Y 100K_0402_5% 100K_0402_5%

9 DGPU_PWR_EN_SOC1.8V S
A
G

3
NL17SZ07DFT2G_SC70-5
3

SA00004BV00
VGA@

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/03/19 Deciphered Date 2015/03/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC INTERFACE
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A5WAM_Bay Trail M_LA‐B981P
Date: Monday, May 12, 2014 Sheet 32 of 47
A B C D E
 A B C D

1 1

@ PJP101 EMI@ PL101

VIN
ACES_50305-00441-001_4P HCB2012KF-121T50_0805
DC_IN_S1 1 2
1
2
3
4
GND

1
GND

1
EMI@ PC102
100P_0603_50V8 EMI@ PC103

2
1000P_0603_50V7K

2
2 2

3 3

@PR111
@ PR111
0_0402_5%
1 2
+3VLP +CHGRTC

- PBJ101 @ + PR112
560_0603_5%
PR113
560_0603_5%
2 1 1 2 1 2 +RTCBATT

ML1220T13RE

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/03/19 Deciphered Date 2015/03/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DCIN / RTC
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A5WAM_Bay Trail M_LA‐B981P
Date: Monday, May 12, 2014 Sheet 33 of 47
A B C D
 A B C D

+3VLP

1
@ PJP201 @ PC202
OCTEK_BTJ-08KEAB_8P-T 0.1U_0603_25V7K

2
10
GND 9

1
1
GND 8 1

8 7 PR209 100_0402_1% @ PR204 @ PR205

7 6 EC_SMDA 2 1 10K_0402_1% 10K_0402_1%
6 5 EC_SMB_DA1 29,35
PR208 100_0402_1%

2
5 4

1
EC_SMCK 2 1 @ PU201
4 3 EC_SMB_CK1 29,35
@ PR206 1 8
3 2 TH 2 1 100K_0402_1% VCC TMSNS1
2 1 +3VLP
PR201 2 7 2 1
1 6.49K_0402_1% GND RHYST1

2
@ PR211 1 2 MAINPWON 3 6 @ PR207
BATT_TEMP 29 OT1 TMSNS2

1
0_0402_5% PR210 47K_0402_1%
BI 1 2 1K_0402_1% 4 5
OT2 RHYST2 @ PH201
G718TM1U_SOT23-8 100K_0402_1%_NCP15WF104F03RC

2
EMI@ PL201
HCB2012KF-121T50_0805
BATT_S1 1 2 BATT+
EMI@ PL202
HCB2012KF-121T50_0805
1 2
1

EMI@ PC201
1000P_0402_50V7K
2

2
For KB9012 For KB9022 Need confirm the setting 2

---Battery_pin define--- ---Battery Con_pin define--- OTP OTP

PIN1 GND PIN8 GND For KB9012
Active Recovery
PIN2 GND PIN7 GND sense 10mΩ
PIN3 SMD PIN6 SMD
92℃ 1.2V 1.0V
PIN4 SMC PIN5 SMC
PIN5 TS PIN4 TS 56℃ 1.2V 1.0V
PIN6 B/I PIN3 B/I
PIN7 Batt+ PIN2 Batt+ 65W 69.55W,0.73V 55.9W,0.59V
PIN8 Batt+ PIN1 Batt+ PR216 22.6K ohm32.4K ohm
40W 42.8W,0.73V 34.4W,0.59V
PR227 26.1K ohm30.9K ohm

+EC_VCCA

ADP_I 29,35
9022@ PR216

1
3 3

9012@ 16.9K_0402_1%

1
PR216
22.6K_0402_1% PR202
10K_0402_1%

2
29 VCIN0_PH

B+ @9012@ PR227 @9022@ PR227

26.1K_0402_1% 30.9K_0402_1%
29,36 MAINPWON
1 2 VCIN1_PROCHOT 29
@ PR223
@9022@ 162K_0402_1%
1

PR230 1 2 H_PROCHOT#_EC 29
80.6K_0402_1%

B value:4250K±1%
@9022@ PR231
2

0_0402_5%

1
1 2
VCIN1_BATT_DROP 29 PH202
100K_0402_1%_NCP15WF104F03RC

1
2

@9022@ PC203

2
1

PR203
0.1U_0402_25V6 @9022@ PR229 10K_0402_1%
1

COMMON PART

2
10K_0402_1%
2

4 4

29 ECAGND

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/03/19 Deciphered Date 2015/03/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BATTERY CONN / OTP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A5WAM_Bay Trail M_LA‐B981P
Date: Monday, May 12, 2014 Sheet 34 of 47
A B C D
 A B C D

Protection for reverse input

Vgs = 20V

1
PQ301 D
2 Vds = 60V B+
G Id = 250mA
S 2N7002KW_SOT323-3

3
PR302
PR301
1 2 1 2 Rds(on) typ = 35mohm max
1
Vgs = 20V Rds(on) = 35mohm max 1

1M_0402_5% 3M_0402_5% max Power loss 0.22W for 90W;0.12W for 65W system Vgs = 20V
Need check the SOA for inrush Vds = 30V CSR rating: 1W
ID = 7.7A (Ta=70C) Vds = 30V
VIN VACP-VACN spec < 80.64mV ID = 7.7A (Ta=70C)
P1 P2
1 PR303 EMI@ PL301 CHG_B+
2 1 8 0.02_1206_1% 1UH_NRS4018T1R0NDGJ_3.2A_30% 8 1
5 3 2 7 1 4 1 2 7 2
Isat: 4A

2200P_0402_25V7K
10U_0805_25V6K

10U_0805_25V6K
3 6 6 3
2200P_0402_50V7K

0.1U_0402_25V6
5 2 3 5
DCR: 27mohm

0.1U_0402_25V6

@EMI@ PC306
4

1
0_0402_5%

PC303

PC304

EMI@ PC305

0.01U_0402_50V7K
PQ302
PC301

@ PR304

4
1

1
AON6414AL_DFN8-5 PQ303 VIN PQ304

PC302

PC307
AO4406AL_SO8 AO4406AL_SO8

2
2

VF = 0.5V
2

2
3

2
PD301
BQ24725A_ACDRV_1 BAS40CW_SOT323-3

0.1U_0402_25V6
0.1U_0402_25V6
BQ24725A_BATDRV 1 2BQ24725A_BATDRV_1
Rds(on) = 30mohm max

1
1
PC308

PC310
PR305
Vgs = 20V

1 1
1 2

10_1206_1%
PC311 4.12K_0603_1%
0.047U_0402_25V7K Vds = 30V

PR306
2
PC309 1 2 ID = 7A (Ta=70C)
0.1U_0402_25V6 VF = 0.37V

5
2.2_0603_5%

AON7408L_DFN8-5
PR307
PD302

BQ24725A_VCC2
RB751V-40_SOD323-2
7X7X3 Power loss: 0.32W for 3.5A

PQ305
PR308

BQ24725A_ACP
0_0603_5%

BQ24725A_REGN
Isat: 3.8A CSR rating: 1W

BQ24725A_BST2

2
2
DH_CHG 1 2 4 2

VSRP-VSRN spec < 81.28mV

BQ24725A_LX
4.12K_0603_1%

4.12K_0603_1%
1

PC312 BATT+
PR309

PR310

DH_CHG
1 2 PL302
10UH_3.5A_20%_7X7X3_M PR311

3
2
1
1U_0603_25V6K 1 2 0.01_1206_1%

BQ24725A_ACN
BQ24725A_LX 1 2 CHG 1 4
2

PC313

5
1U_0603_25V6K 2 3

AON7408L_DFN8-5
20

19

18

17

16
PU301

CSON1
CSOP1
1

680P_0402_50V7K 4.7_1206_5%
VCC

PHASE

HIDRV

BTST

REGN

10U_0805_25V6K

10U_0805_25V6K
PQ306

@EMI@ PC319 @EMI@ PR312

21

0.1U_0402_25V6

0.1U_0402_25V6
PAD

PC314

PC315
1

1
1 15 DL_CHG 4
ACN LODRV

PC316

PC317
2

2
2 14
ACP GND PR313

3
2
1

2
1
BQ24725ARGRR_QFN20_3P5X3P5 10_0603_1%
BQ24725A_CMSRC 3 13 SRP1 2 CSOP1
CMSRC SRP

1
PR314

2
6.8_0603_1%
BQ24725A_ACDRV 4 12 SRN1 2 CSON1

2
ACDRV SRN PC318
0.1U_0603_16V7K
+3VLP 1 2 5
ACOK BATDRV
11 BQ24725A_BATDRV **Design Notes**
PR315 100K_0402_1%
#For 65 /90W system, 3S1P/3S2P battery
ACDET

IOUT

SDA

ILIM
SCL
Maximum Charging current 3.5A
29,8 ACIN Maximum Battery discharge power 55W.
#Register Setting
6

10
+3VALW
3 3

1. 0X12 bit8 set 0 (default 1) to disable IFAULT HI if add ISN choke

BQ24725A_ACDET

BQ24725A_ILIM 1 2
#Circuit Design
BQ24725A_IOUT

PR316
1. ACOK,ILIM pull high voltage need base on 3/5V enable control

100K_0402_1%

0.01U_0402_25V7K
316K_0402_1%

1
2. Use 10X10 choke and 3X3 H/L Side MOSFET

PC320
PR317

1
PR318
422K_0402_1% Charge current 3.5A
VIN 1 2 Power loss : 1.82W

2
Power density : 0.81 (15X15)
2

3. If use 4S per cell 4.35V battery, need additional circuit

for ACDET(PR218/PR220/PR222 change to 0.1%, parallel resistors
with PR222 for ACDET setting)
4. PC223 0.22U can't be changed. (Wrong adapter concern)
5. For the design, need double confirm PQ202,PQ203,PQ204 rating
0.22U_0402_16V7K

#Protect function
66.5K_0402_1%

EC_SMB_CK1 29,34
Vin Dectector 1. ACOVP : ACDET voltage > 3.14V
100P_0402_50V8J
1

1
PC321

2. Charger timeout : No communication within 175s(default)

1
PC322

Min. Typ Max.

PR319

L-->H 17.16V 17.63V 18.12V 3. ACOC : 3.33 X Input current DAC setting(default)
2

EC_SMB_DA1 29,34
4. CHGOCP : 3/4.5/6A based on current current setting
2

H-->L 16.76V 17.22V 17.70V @ PR320

@PR320
5. BATOVP : 103-106%
2

0_0402_5%
1 2
ADP_I 29,34 6. BATLOWV : 2.5V
VILIM = 20*ILIM*Rsr 7. TSHUT : 155C
1

ILIM = 3.3*100/(100+316)/20/0.01 @ PC323 8. IFAULT HI : 750mV (default)

= 3.966 A 100P_0402_50V8J 9. IFAULT LOW : 150mV (default)
2

4
Close EC chip 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/03/19 Deciphered Date 2015/03/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Charger
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A5WAM_Bay Trail M_LA‐B981P
Date: Monday, May 12, 2014 Sheet 35 of 47
A B C D
 A B C D E

1 1

EN1 and EN2 dont't floating

PR402
499K_0402_1%
ENLDO_3V5V 1 2
B+

1
150K_0402_1%
PU401
B+

PR404
EMI@ PL401 7 1 3V5V_EN PC402 PR403
HCB2012KF-121T50_0805 EN2 EN1 0.022U_0402_25V7K 1K_0402_5%

2200P_0402_50V7K
1 2 3V_VIN 8 3 3V_FB 1 2 1 2
IN FB PR401 PC403

2
10U_0805_25V6K

10U_0805_25V6K
@EMI@ PC401

EMI@ PC404
0.1U_0402_25V6
6 1
BST_3V 2 1 2
BS
1

1
PC406
1_0603_5%

PC405
0.1U_0603_25V7K
PL402
2

2
10 LX_3V 1 2
@ LX +3VALWP
9 4 1.5UH_PCMB053T-1R5MS_6A_20%
GND OUT

@EMI@

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
PR405
1

1
680P_0603_50V7K 4.7_1206_5%
2 5
+3VALWP PG LDO +3VLP

@ PC407

PC408

PC409

PC410
1
SYX198BQNC_QFN10_3X3

2
PC411

13V_SN
4.7U_0603_6.3V6M

2
1

PR412
100K_0402_5% 3.3V LDO 150mA~300mA

@EMI@

PC412
2

2
2
Vout is 3.234V~3.366V 2

29,38,39 SPOK

TDC=6A
@ PJ401
+3VALWP 1 2 +3VALW
1 2
JUMP_43X118

B+ EMI@ PL403 EN1 and EN2 dont't floating

HCB2012KF-121T50_0805
1 2 5V_VIN

@ PJ402
+5VALWP 1 2 +5VALW
1 2

Vout is 4.998V~5.202V
2200P_0402_50V7K
10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6

PU402 PC413 PR406 JUMP_43X118

8 1 3V5V_EN 6800P_0402_25V7K 1K_0402_5%
IN EN 5V_FB 1 2 1 2
1

TDC=6A
PC414

PC415

EMI@ PC417

@EMI@ PC418

3 PC416
FB 0.1U_0603_25V7K
6 BST_5V 1 2 1 2
2

BS
@ @ PR407
0_0603_5% PL404
9 10 LX_5V 1 2 +5VALWP
GND LX
VCC_3V 5 4 1.5UH_PCMB053T-1R5MS_6A_20%
VCC OUT

680P_0603_50V7K 4.7_1206_5%

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
PR408

1
@EMI@
SPOK 2 7
PG LDO VL
1

PC419

PC420

PC421

PC422

PC423
4.7U_0603_6.3V6M

3 3
SYX198CQNC_QFN10_3X3

2
15V_SN
2

2
1

PC424
4.7U_0603_6.3V6M
2

PC425
@EMI@

PR409
2.2K_0402_5%
1 2 5V LDO 150mA~300mA
29 EC_ON
@ PR410
1 2
29,34 MAINPWON 0_0402_5%

3V5V_EN
1M_0402_1%

4.7U_0402_6.3V6M
1

EC VDD0 is +3VL, PC13 UNPOP

1
PR411

PC426

EC VDD0 is +3VALW, PC13 POP

2
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/03/19 Deciphered Date 2015/03/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
3VALW/5VALW
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A5WAM_Bay Trail M_LA‐B981P
Date: Monday, May 12, 2014 Sheet 36 of 47
A B C D E
 5 4 3 2 1

D D

Pin19 need pull separate from +1.35VP.

If you have +1.35V and +0.675V sequence question, 0.675Volt +/- 5%
EMI@ PL501
HCB2012KF-121T50_0805
you can change from +1.35VP to +1.35VS. TDC 0.84A
B+ 1 2 1.35V_B+ PR501 Peak Current 1.2A
2.2_0603_5%
BST_1.35V 1 2 BOOT_1.35V
+1.35VP

2200P_0402_50V7K

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6
1

1
@EMI@ PC502 +0.675VSP

EMI@ PC503

PC504

PC505
DH_1.35V
2

1
PC501

10U_0805_6.3V6K

10U_0805_6.3V6K
SW_1.35V
0.1U_0603_25V7K

1
PC506

PC507
5

16

17

18

19

20
C PU501 C

2
PHASE

UGATE

BOOT

VTT
VLDOIN
COMMON PART
21
PQ501 PAD
AON7408L_DFN8-5 4 DL_1.35V 15 1
LGATE VTTGND

14 2
PL502 PR502 PGND VTTSNS

1
2
3
1UH_11A_20%_7X7X3_M 9.1K_0402_1%
1 2 1 2 CS_1.35V 13 3
+1.35VP PC508 CS RT8207MZQW_WQFN20_3X3 GND
1

1U_0603_10V6K
1 2 12 4 VTTREF_1.35V
VDDP VTTREF

5
SF000002Z00 H=4.5 @EMI@ PR503 PR504

1
330U_2.5V_ESR17M_6.3X4.5

1 4.7_1206_5% 5.1_0603_5%
COMMON PART

1 2 VDD_1.35V 11 5 PC510
1 2

+ +5VALW VDD VDDQ

+1.35VP 0.033U_0402_16V7K
PC509

PGOOD

2
ESR=15m ohm

TON
1
@EMI@ PC512 4

FB
S5

S3
2 680P_0402_50V7K PC513
+5VALW
2

1U_0603_10V6K

10

6
PQ502
1 2
+1.35VP
1
2
3

FB_1.35V
AON7506_DFN33-8-5

EN_0.675VSP
EN_1.35V
TON_1.35V
PR505 100K_0402_5% PR506
8.06K_0402_1%
5 DDR_PWROK 2 1 +1.35VP
PR507
B 887K_0402_1% B

MOSFET: 3x3 DFN 1.35V_B+ 1 2

1
Co-Lay H/S Rds(on): 27mohm(Typ), 34mohm(Max)
Idsm: 7.5A@Ta=25C, 5.5A@Ta=70C PR509 PR508
680K_0402_1% 10K_0402_1%
1 2
28,29 SYSON

2
Mode Level +0.675VSP VTTREF_1.35V L/S Rds(on): 9.9mohm(Typ), 13mohm(Max)
S5 L off off Idsm: 13.5A@Ta=25C, 11A@Ta=70C

1
@ PC514
S3 L off on 0.1U_0402_16V7K
S0 H on on Choke: 7x7x3

2
Rdc=8.3mohm(Typ), 10mohm(Max)
Note: S3 - sleep ; S5 - power off PR510
200K_0402_1%
Switching Frequency: 285kHz 1 2 @ PJ501
10,29,32,38,39 SUSP# +1.35VP 1 2 +1.35V
Ipeak=10A PC515 1 2
Iocp~13A

1
JUMP_43X118
D

1
0.1U_0402_16V7K @ PJ502
OVP: 110%~120% 2 1 2
VFB=0.75V, Vout=1.515V

2
32 SUSP G 1 2

MOSFET footprint: SIS412DN @ PQ503

JUMP_43X118
S

3
2N7002KW_SOT323-3 @ PJ503
1 2
+0.675VSP 1 2 +0.675VS
JUMP_43X39
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/03/19 Deciphered Date 2015/03/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.35VP/0.675VSP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A5WAM_Bay Trail M_LA‐B981P
Date: Monday, May 12, 2014 Sheet 37 of 47
5 4 3 2 1
 5 4 3 2 1

D D

EN pin don't floating

If have pull down resistor at HW side, pls delete PR2
PR602
10K_0402_1%
1 2 SPOK
SPOK 29,36,39
C C

1
PC602
PR603 0.1U_0402_16V7K
1M_0402_1%

2
2
@EMI@ PR604 @EMI@ PC603
4.7_1206_5% 680P_0603_50V7K
EMI@ PL601 1 2SNB_1.0V 1 2
HCB2012KF-121T50_0805 PU601
B+ 1 2 B+_1.0V 8
IN EN
1 @ PR601 PC601 TDC 8A
10U_0805_25V6K

10U_0805_25V6K

0_0603_5% 0.1U_0603_25V7K
2200P_0402_50V7K

6 BST_1.0V 1 2 1 2 PL602
0.1U_0402_25V6

BS
1

1
PC606

PC604

PC607

1.5UH_PCMC063T-1R5MN_9A_20%
LDO_3V
+1.0VALWP
PC605

9 10 LX_1.0V 1 2
GND LX
@EMI@
2

2
EMI@

15.4K_0402_1%

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
@
1

330P_0402_50V7K
1

1
PR606
4
FB
Rup

PC608

PC609

PC610

PC611

PC612
@ PR605
0_0402_5% ILMT_1.0V 3 7
+3VALW

2
ILMT BYP

4.7U_0603_6.3V6K
2

2
ILMT_1.0V
+3VALW 1 2 +1.0V_PGOOD 2 5 LDO_3V
4.7U_0603_6.3V6K
PG LDO
1

PC614
PR608
2

PC613

10K_0402_5% SYX198DQNC_QFN10_3X3
@ PR607 FB = 0.6V
2

1
0_0402_5%
2

PR609
Rdown
1

20K_0402_1%

2
Pin 7 BYP is for CS. VFB=0.6V
B
The current limit is set to 8A, 12A or 16A when this pin Common NB can delete +3VALW and PC614 B
is pull low, floating or pull high Vout=0.6V* (1+Rup/Rdown)
Vout=1.062V +1.0VALWP PJ601
1 2 +1.0VALW
1 2
JUMP_43X118 @

+3VS PR610
2.55K_0402_1%
+1.05VSP_ON 1 2
SUSP# 10,29,32,37,39
1

0.1U_0402_16V7K

1
PC615

@ PR611
1

100K_0402_5% @ PR612
1M_0402_5%
Note:Iload(max)=2.5A
2

PU602
9
1 PGND 8
FB SGND
2 7 PL603
@ PJ602 PG EN 1UH_2.8A_30%_4X4X2_F
+3VALW 1 2 3 6 LX_1.05V 1 2
1 2 IN LX +1.05VSP
COMMON PART
1

4 5
68P_0402_50V8J

JUMP_43X79
PGND NC
1

1
@EMI@ PR613
4.7_0603_5%

PC616
1
PC617

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0805_6.3VAM
2

SY8003DFC_DFN8_2X2 PR614
Rup
PC618

PC619

15K_0402_1%
2
2

@ PJ603
FB_1.05V 1 2
A +1.05VSP 1 2 +1.05VS A
JUMP_43X79
1
1

FB=0.6V
@EMI@ PC620
680P_0402_50V7K

Note:Iload(max)=3A PR615
Rdown
20K_0402_1%
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/03/19 Deciphered Date 2015/03/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.05VS/1.0VALW
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A5WAM_Bay Trail M_LA‐B981P
Date: Monday, May 12, 2014 Sheet 38 of 47
5 4 3 2 1
 5 4 3 2 1

+3VALW

1
1
JUMP_43X79
@ PJ701

2
2
D
Ultra Low Dropout 0.23V(typical) at 3A Output Current D

1
@ PC702
1U_0402_6.3V6K

2
PC703 PU701

1
4.7U_0805_6.3V6K APL5930KAI-TRG_SO8
6
5 VCNTL 3
PJ702

2
PR701 9 VIN VOUT 4 @
51K_0402_1% VIN VOUT
+1.5VSP +1.5VSP 1
1 2
2 +1.5VS

20K_0402_1%
SUSP# 1 2 8
10,29,32,37,38 SUSP# EN

1
1 2 7 2 JUMP_43X79
+3VS

GND
POK FB

PR703
PC704
@ PR702
Rup 0.01U_0402_25V7K

2
1

1
PC701 100K_0402_5% PC705

2
0.15U_0402_10V6K @ PR704 22U_0603_6.3V6M
22K_0402_5%

2
2

1
PR705
Rdown 22.6K_0402_1%

2
C C
+3VALW
Vout=0.8V* (1+Rup/Rdown)=1.507V

1
Ultra Low Dropout 0.23V(typical) at 3A Output Current
JUMP_43X79 1
@ PJ703
2
2

@ PC706
1U_0402_6.3V6K
2

PC707 PU702
1

4.7U_0805_6.3V6K APL5930KAI-TRG_SO8
6
B 5 VCNTL 3 B
PJ704
2

PR706 9 VIN VOUT 4 @

20K_0402_1% VIN VOUT
+1.8VALWP +1.8VALWP 1
1 2
2 +1.8VALW

20K_0402_1%
1 2 8
29,36,38 SPOK EN

1
1 2 7 2 JUMP_43X79
+3VS
GND

POK FB

PR708
PC709
1

@ PR707
Rup 0.01U_0402_25V7K
0.1U_0402_16V7K

1
PC708

@ PR709 100K_0402_5% PC710

1

2
22K_0402_5% 22U_0603_6.3V6M
2

2
2

1
PR710
Rdown 15.8K_0402_1%
2

Vout=0.8V* (1+Rup/Rdown)=1.81V

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/03/19 Deciphered Date 2015/03/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.5VSP/1.8VALWP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A5WAM_Bay Trail M_LA‐B981P
Date: Monday, May 12, 2014 Sheet 39 of 47
5 4 3 2 1
 A B C D E

Layout Note
Reduce Acoustic Noise
1. The AL bulk capacitor of B+ should be very
close to CPU_CORE MOSFET.

1
@ PC802
1000P_0402_50V7K 2. Input ceramic caps must place on symmetry
10 VGFX_VSNS
same location on top side and bottom side.

2
1
+CPU_B+
PC803
0.01UF_0402_25V7K

10U_0805_25V6K

10U_0805_25V6K
1

1
PC805

PC806
5
1 PQ803 1

2
PC804
6800P_0402_25V7K
OCP setting=21A
1 2 PR804 4

2K_0402_1%
1
PC807 PC808 0_0603_5%
120P_0402_50V8 470P_0402_50V7K UGA_GFX 1 2 UGA_GFX-1 MDV1525URH_PDFN33-8-5 0.36uH DCR= 1.4+-5% m ohm, Idc~Isat= 16.8~24A

PR802
Close GFX choke 1 2 1 2 1
PR803
2

3
2
1
PR805 PC809 499_0402_1% PL802 +SOC_VNN

2
VSUMG-
COMMON PART 1
324_0402_1%
2 1 2
1000P_0402_25V8J
1 2 1 2
0.36UH_PDME064T-R36MS_24A_20%

PR806 PHASEA_GFX 1 4

1
137K_0402_1% PR807

@EMI@ PR813
4.7_1206_5%
PH802 2.05K_0402_1% PC813 2 3

5
21K_0402_1%
10K_0402_1%_B25/50 3370K

.1U_0402_16V7K
PR808 BOOTA_GFX 1 2 1 2

0.1U_0402_16V7K
1

1
11K_0402_1%
PC810

PR809
0.047U_0402_25V7K
2K_0402_1% PR812

1
2.2_0603_5% 0.1U_0603_25V7K

PC811
2

1 2
1
Design Note

PC812
PR811
2

2.61K_0402_1%

2
1

1
This circuit is for ULV 1+1 17W. +3VALWP
PC814 LGA_GFX 4

1 2

1
680P_0402_50V7K
PQ804

PR810
1000P_0402_50V7K
CPU: IccMax=33A, TDC=16A(TDP NOM)

2
1_0402_5%

@EMI@ PC815
AON6554_DFN5X6-8-5
3.65K_0603_1% PR815

1.91K_0402_1%
Loadline: -2.9 m V/A

1
VSUMG+ PR814

3
2
1

2
Output Cap. follow Intel PDDG Rds=13.5mΩ(Typ)

2
16.5mΩ(Max)

VSUMG+
330uF/9m*3, 22uF_0805*12, 2.2uF_0402*16

VSUMG-
2
GFX(GT2): IccMax=33A, TDC=21.5A
Loadline: -3.9 m V/A

PR816
BOOTA_GFX

Output Cap. follow Intel PDDG UGA_GFX

330uF/9m*2, 22uF_0805*6, 10uF_0603*6 , 1uF_0402*11 PHASEA_GFX

Close GFX L/S MOS LGA_GFX +5VALW
PR817

33

32

31

30

29

28

27

26

25
27.4K_0402_1% PR817 and PR826
1 2 PU801
27.4K ohm for 100 degree

PAD

ISUMPG

ISUMNG

RTNG

FBG

COMPG

PGOODG

BOOTG

UGATEG

1U_0603_10V6K
2 NTCG_1 2
PH803 PR818 61.9K ohm for 110 degree

1
3.83K_0402_1%

1
1 2 1 2 1 24 PR821

PC816
NTCG PHASEG
@PR820
@
1
PR820
2
COMMON PART 2 23
@ PR819
@PR819
0_0603_5%
1_0603_5%
+CPU_B+

2
29 VR_ON 470K_0402_5%_B25/50 4700K VR_ON LGATEG EMI@ PL801

2
0_0402_5% 1 PR843 2 3 22 FBMA-L11-322513-151LMA50T_1210
8 VR_SVID_CLK SCLK VCCP
20_0402_1% 1 2 B+

10U_0805_25V6K

10U_0805_25V6K
PR844 SVID_ALERT# 4 21
8 VR_SVID_ALERT# ALERT# VDD

1U_0603_10V6K
16.9_0402_1% ISL95833BHRTZ-T_QFN32_4X4 @PR822
@ PR822 1.91K_0402_1%

2200P_0402_50V7K
PC817

0.1U_0402_25V6
1 2 SVID_DATA 5 20 1 2 1
8 VR_SVID_DATA SDA PWM2

1
Height 8 mm

68U_25V_M
PC819

PC820

@EMI@ PC823
1
+

EMI@ PC821

@ PC822
6 19 LG1_CPU
29 VR_HOT# VR_HOT# LGATE1 100u_SF000000I80

2
NTC 7 18 PHASE1_CPU Height 6 mm

2
NTC PHASE1 2
For VR_HOT#, already @ PR823
@PR823
68u_SF000000W00
1 2 8 17

PGOOD
UG1_CPU
pull high at power side.

BOOT1
ISUMN
ISUMP
ISEN2 UGATE1

COMP
ISEN1
69.8_0402_1%
499_0402_1%

69.8_0402_1%

RTN
1

@ PC818 0_0402_5% BOOT_CPU

FB
PR801

PR824

PR825

3.83K_0402_1%

47P_0402_50V8J
1

+5VALW
2

10

11

12

13

14

15

16
PR829

@
2

VGATE 29

1 2 +3VALWP
+1.0VS
1

27.4K_0402_1%
1

1.91K_0402_1% PR827
PR826

@PC801
@ PC801
0.1U_0402_16V7K
2

+CPU_B+
2

PH801
470K_0402_5%_B25/50 4700K
COMMON PART

5
Close CPU L/S MOS PQ801
3
OCP setting=18A 3
PR828
0_0603_5% MDV1525URH_PDFN33-8-5
VDD source use +5VS and PGOOD source use +3VS UG1_CPU 1 2 UG1_CPU-1 4 0.36uH DCR= 1.4+-5% m ohm, Idc~Isat= 16.8~24A
Please confirm power on and down sequence,
make sure VGATE after CPU_CORE on. PL803 +SOC_VCC
0.36UH_PDME064T-R36MS_24A_20%

3
2
1
PC826 PR834 PR835 VSUM+ PHASE1_CPU 1 4

2.61K_0402_1%
680P_0402_50V7K 2K_0402_1% 66.5K_0402_1%

680P_0402_50V7K 4.7_1206_5%
1 2 1 2 1 2 PC824 2 3

5
PR836

@EMI@ PR831
BOOT_CPU 1 2 1 2
11K_0402_1%

PR830
2K_0402_1%

0.047U_0402_25V7K

2.2_0603_5% 0.1U_0603_25V7K
1
PR838

PC827 PC828
0.1U_0402_16V7K

2
1
PC829

470P_0402_50V7K 120P_0402_50V8
1

1
3.65K_0603_1%
1 2 1 2 1 2 LG1_CPU 4
PC830
1

1
280_0402_1%

PR837
Close CPU choke PQ802
1_0402_5%

1
PR839

PR832
499_0402_1% AON6554_DFN5X6-8-5
2

PR833
PR840

@EMI@ PC825
2
6800P_0402_25V7K

PH804

3
2
1

2
1

Rds=13.5mΩ(Typ)
PC832

PR841 PC831 10K_0402_1%_B25/50 3370K

2

2
1.78K_0402_1%
1 2 1 2
1000P_0402_25V8J
1 2
COMMON PART 16.5mΩ(Max)

VSUM+
2

VSUM-
PR842
137K_0402_1% VSUM-
.1U_0402_16V7K
1

Layout Note
PC833

10 VCORE_VSNS @ PC834
SVID routing 330P_0402_50V7K
2

1 2
1. Alert# signal must be routed between
the Clock and Date lines to reduce the cross
talk between them. Signal order arrangement: 1 2 Cn = L/((Rntcnet*Rsum)/(Rntcnet+Rsum))*DCR)
mobile order is Clock-Alert-Date. PC835 If Cn is correctly selected, when the load current has a
4
0.01UF_0402_25V7K square change, the output voltage also has a square response. 4
2. SVID spacing requirement is 18mils(0.475mm).
10 VCORE_GSNS

3. Maximum total microstrip routing length of

each SVID signal must not exceed 6000mils(152.4mm).
4. The SVID bus must be ground reference, It cannot be
referenced to input (Vbat or 12V) power plans as they can
couple noise into the SVID bus as power states change.
5. Avoid routing under noisy circuit, e.g. switch node , Security Classification Compal Secret Data Compal Electronics, Inc.
Gate driver, B+, Vin, high speed signal. Issued Date 2014/03/19 2015/03/18 Title
Deciphered Date
6. When SVID signal changes Layer, GND return path CPU_CORE/GFX_CORE
may be changed also. We need add GND via for GND THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 0.1
reference. DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A5WAM_Bay Trail M_LA‐B981P
Date: Monday, May 12, 2014 Sheet 40 of 47
A B C D E
 5 4 3 2 1

3 X 330u/9m(47W)
PWR Rule 2 X 330u/9m(37W)
需確認最新SPEC. 24 pcs 22uF and reserve 4 pcs
2013/08/16
Modify 8/6.
D D

+SOC_VCC =+CPU_CORE +SOC_VNN =+VGFX_CORE

+SOC_VNN
+SOC_VCC
PC913 1 2 22U_0603_6.3V6M
PC903 1 2 22U_0603_6.3V6M PC914 1 2 22U_0603_6.3V6M

Output Cap PC904 1

PC905 1
2
2
22U_0603_6.3V6M
22U_0603_6.3V6M Output Cap PC915 1
PC916 1
2
2
22U_0603_6.3V6M
22U_0603_6.3V6M
PC906 1 2 22U_0603_6.3V6M
(330uF*2+22uF*4) (330uF*3+22uF*4) PC917 2 1 330U_D2_2V_Y
PC901 2 1 330U_D2_2V_Y

+
PC918 2 1 330U_D2_2V_Y

+
PC902 2 1 330U_D2_2V_Y

+
+
+SOC_VCC

Package Edge Cap PC929 1 2 22U_0603_6.3V6M

(22uF*3) PC907 1 2 22U_0603_6.3V6M +SOC_VNN

PC930 1 2 22U_0603_6.3V6M

C PC908 1 2 22U_0603_6.3V6M Package Edge Cap PC920 1

PC921 1
2 10U_0603_6.3V6M
2 10U_0603_6.3V6M C
PC922 1 2 22U_0603_6.3V6M

Back Side Cap PC909 1

PC910 1
2 22U_0603_6.3V6M
2 22U_0603_6.3V6M
(22uF*3)
(10uF*1+4.7uF*2+2.2uF*2) PC911 1
PC912 1
2 2.2U_0402_6.3V6M
2 2.2U_0402_6.3V6M PC923 1 2 1U_0402_6.3V6K
PC924 1 2 1U_0402_6.3V6K
PC925 1 2 1U_0402_6.3V6K

Back Side Cap

(1uF*3) @ PC927 1
@ PC928 1
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/03/19 Deciphered Date 2015/03/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU/GFX capacitor
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A5WAM_Bay Trail M_LA‐B981P
Date: Monday, May 12, 2014 Sheet 41 of 47
5 4 3 2 1
 5 4 3 2 1

Module model information

TPS51212_V1.mdd for Single layer
TPS51212_V2.mdd for Dual layer
VGA_EMI@ PL1001
HCB2012KF-121T50_0805
D D
+1.5VSDGPUP_B+ 1 2
B+

2200P_0402_50V7K

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6

PC1005
1

1
@EMI@ PC1002

PC1003

VGA@ PC1004
2

2
@

VGA_EMI@
VGA@
2013/10/20 update 4 PQ1001
AON7408L_DFN8-5
Setting OCP__PR1003-->102K VGA@ VGA@ PR1001 VGA@ PC1001 2013/10/28 update PL1002 change
PU1001 2.2_0603_5% 0.1U_0603_25V7K
Common part 7*7*3 SH00000YV00
VGA@ PR1003 1 10 1
BST_+1.5VSDGPUP 2 1 2
0.9% 1.51V

3
2
1
102K_0402_1% PGOOD VBST
VGA@ PR1004 1 2TRIP_+1.5VSDGPUP2 9 UG_+1.5VSDGPUP VGA@ PL1002
0_0402_5% TRIP DRVH 2.2UH_ETQP3W2R2WFN_8.5A_20%
15,32,43 VGA_PWROK 1 2 EN_+1.5VSDGPUP 3 8 SW_+1.5VSDGPUP 1 2
EN SW
+1.5VSDGPUP
FB_+1.5VSDGPUP 4 7
VFB V5IN
+5VALW

1
0.1U_0402_16V7K

2013/10/28 update PC509 chang

PC1009 VGA@
RF_+1.5VSDGPUP 5 6 LG_+1.5VSDGPUP @EMI@
TST DRVL Common part SF000006S00 H4.5
1
PC1006

PR1005

1
11

330U_2.5V_M
4.7_1206_5%

AON7506_DFN33-8-5
TP 1

VGA@ PQ1002
C VGA@ VGA@ C
2

2
+
PR1006 TPS51212DSCR_SON10_3X3 PC1007
1U_0603_6.3V6M
4 ESR=15m ohm
@ 470K_0402_1%

1
2 PC1010 @EMI@
680P_0402_50V7K 2
H=4.5

3
2
1

2
SF000002Z00

PR1007
9.31K_0402_1%
1 2
1

VGA@
PR1008
10K_0402_1%
2

@ PJ1001
+1.5VSDGPUP 1 2 +1.5VSDGPU
1 2
B B
JUMP_43X118

+1.2V +1.05V MOSFET: 3x3 DFN @ PJ1002

1 2
H/S Rds(on): 27mohm(Typ), 34mohm(Max) 1 2
Switching Frequency: 290kHz Switching Frequency: 290kHz L/S Rds(on): 22mohm(Typ), 13.5mohm(Max) JUMP_43X118
Imax=8A Imax=5.4A
OCP~10.5A Ipeak=6.5A Choke: 7x7x3
OVP: 120%~130% Iocp=7.8A Rdc=15.5mohm +/-15%
VFB=0.704V, Vout=1.207V OVP: 120%-130%
VFB=0.704V, Vout=1.055V Switching Frequency: 290kHz
Ipeak=10A
Delta I =2.16A
Vout PR1007 PR1008 PR1003 Iocp=12.14~16.67A
OVP: 120%~130%
+1.5V 11.5k 10k VFB=0.704V, Vout=1.51V

+1.35V 9.31k 10k

+1.2V 7.15K 10k 105K

A A

+1.05V 4.99k 10k 93.1k

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/03/19 Deciphered Date 2015/03/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.5VSDGPUP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A5WAM_Bay Trail M_LA‐B981P
Date: Monday, May 12, 2014 Sheet 42 of 47
5 4 3 2 1
 A B C D E

Vboot=Vvref*Rref2/(Rref1+Rref2+Rboot) Current Limit threshold setting Different VGA Chip (different EDP-Peak Current) need select different solution
Rt=Rrefadj // (Rboot+Rref2) Rocset= (Ivalley * Rds(on) + 40 mV) / 10uA
Module model information:
Vmin= Vvref*[Rref2/(Rref2+Rboot)]*[Rt/(Rref1+Rt)] I_ripple=(19-0.9)*0.9/ VGA Chip N14P-GV N14P-GV2 N14M-GS N14M-LP N14P-LP N14P-GE N14P-GS N14P-GT N15S-GT N15V-GM
RT8813A_V1A for IC module (304.89Khz*0.36u*19)=7.811A
Vmax=Vvref*Rref2/[(Rref1//Rrefadj)+Rboot+Rref2]
RT8813A_V1B for SW module OpenVReg Configurations Config B Config B Config B Config B Config B Config B Config B Config B Config B Config C
Vout=Vmin+N*Vstep OCP=54A/2=27A per phase
1 Vstep=(Vmax-Vmin)/Nmax Ivalley=27A-7.811A/2=23.1A Rated TDP Power at Tj=102C 18W 25W 18W 13W 18.9W 25W 25.6W 35.5W 18W 18.16W 1

PWM-VID Spec and component Values Boosted GPU Total at Tj=102C 25W 32W 25W 20W 23W N/A 30W 40W 25W 24.72W
H-side MOS:AON6552 L-side MOS:AON6554
PWM-VID Spec Config B Config C Config D Rds(on): Rds(on): EDP-Continuous at Tj=102C 24A 32A 26A 22A 25A 27A 38A 45A 31A 29.2A
5.6mohm@Vgs=10V 3.2mohm@Vgs=10V
Vmin 0.6V 0.65V 0.9V 6.7mohm@Vgs=4.5V 3~3.8mohm@Vgs=4.5V EDP-Peak at Tj=102C 35A 55A 45A 35A 35A 40A 60A 75A 60A 44.3A
Vmax 1.2V 1.15V 1.15V Id :20A@Ta=25 degC Id :85A@Ta=25 degC
Vboot 0.9V 0.9V 1.028V Istep max (Evaluation) 15A 27A 25A 20A 14A 12A 31.5A 35A
Voltage step 6.25mV 25mV 12.5mV Choke: 0.22uH (Size:7*7*4)
Rdc=0.97mohm +-5% OCP Setting Current 42A 66A 54A 42A 42A 48A 72A 90A 72A 54A
N of Voltage level 96 20 20
Heat Rating Current=34A
Rrefadj PR1206 20K 39K 27K Saturation Current=25A Rocset 8.96K 12.45K 10.7K 8.96K 8.96K 9.83K 8.3K 9.39K 13K 10.2K
Rref1 PR1204 20K 30K 7.5K
Recommendation 2phase 1H1L 2phase 1H1L 2phase 1H1L 2phase 1H1L 2phase 1H1L 2phase 1H1L 2phase 1H2L 2phase 1H2L 2phase 1H1L 2phase 1H1L
Rboot PR1205 2K 3K 0 C=3*330uF (9mohm)=990uF
Rref2=PR1209 PR1209 18K 24K 6.2K Vripple=Iripple*ESR(min)=7.811A*3mohm=23.4mV 6mohm * 3 4.5mohm * 3
+PR1212 Polymer Cap (330uF) 6mohm * 2 9mohm * 3 9mohm * 3 6mohm * 2 6mohm * 2 6mohm * 2 (L=0.22uH) (L=0.15uH)
PR1212 0 3K 1.74K
C PC1209 2.7nf 1.8nf 5.6nf
Or OSCON (390uF) 10mohm * 3 10mohm * 3 10mohm * 3 10mohm * 3 10mohm * 3 10mohm * 3 NULL NULL GT@ GM@
N15S-GT N15V-GL N15V-GM @VGA@ PR1202
1K_0402_5%
1 2 +3VS
PWM VID and Output voltage control GM@ PR1211 GL@ PR1211 GM@ PR1234
7.5K_0402_1% 30K_0402_1% 27K_0402_1%
1.Boot mode
1 2 DGPU_VID 15
2.Standby mode (don't support) GPU_B+
3.Normal mode @VGA@ PR1203
0_0402_1% Operation phase Number PSI Voltage setting
GL@PR1234
GL@PR1234
2 39K_0402_1% 1 phase with DEM 0V to 0.8V VGA_EMI@ PL1201 2
1

VGA@ GM@ PR1208 GL@ PR1208 HCB2012KF-121T50_0805

1

B+
PC1202 0_0402_5% 3K_0402_1% Rref1 GT@ 1 phase with CCM 1.2V to 1.8V
1U_0402_6.3V6K PR1211 1 2
2

20K_0402_1% Active phase with CCM 2.4V to 5.5V

VGA@

2200P_0402_50V7K

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6
Rboot Rrefadj
2

GT@ PSI Pull high on HW side PR1233

GT@PR1208
GT@PR1208 PR1234 @VGA@ PR1207 2.2_0603_5%

1
PSI 15

@VGA_EMI@ PC1216

VGA_EMI@ PC1204

VGA@ PC1205

VGA@ PC1206
2K_0402_5% 20K_0402_1% 1 2 1
U2_BOOT1 2 VGA@
1 2 1 2
PQ1201

AON6552_DFN5X6-8-5
GM@ PR1209 GL@ PR1209 0_0402_1% 1 +VGA_CORE

2
5
18K_0402_1%
GT@ PR1209

6.2K_0402_1% 24K_0402_1% VGA@ PR1238

1

EDP-Continuous 31A
2700P_0402_50V7K
0.01U_0402_16V7K

GL@ PC1209 15K_0402_1% PC1207 VGA@

PC1208

1800P_0402_50V7K 1 2 0.22U_0603_25V7K
DGPU_PWR_EN 32 EDP-Peak 60A
GPU_VID

2
1
1

OCP min 72A

GT@ PC1209

Rref2 0.1U_0402_25V6 U2_UGATE1 1 2 4

2

VGA@ PR1223
2

1
GPU_REFADJ

2
@VGA@

VGA@
GT@ PR1237

PC1210

0_0603_5%
U2_BOOT1
U2_UGATE1
1

0_0402_5%

GM@ PR1237 GL@ PR1237 C Reserve Location

GPU_PSI

GPU_EN

1.74K_0402_1% 3K_0402_1% VGA@ PL1202

2

3
2
1
GM@ PC1209 0.22UH 20% FDUE0640J -H 25A +VGA_CORE
5600P_0402_25V7K 1 4
2

GPU_FBRTN U2_PHASE1
2 3
VGA@ VGA@
6

AON6554_DFN5X6-8-5
PU1201 PQ1202

1
VGA@ PR1201 @VGA_EMI@
REFADJ

VID

EN
PSI

UGATE1

BOOT1

Rton 365K_0402_1% PR1231 2013/12/13 update PL1202 PL1203 change to

GPU_B+ 1 2 4.7_1206_5%
@VGA@ 1 GPU_REFIN 7 24 U2_PHASE1 Common part SH000011H00
PR1214 REFIN PHASE1 U2_LGATE1 4

2
17 VSSSENSE_VGA 0_0402_1% @VGA@ GPU_VREF 8 23 U2_LGATE1
1 2 PC1201 VREF LGATE1 @VGA_EMI@

1
2 0.01UF_0402_25V7K

13K_0402_1%
GPU_TON 9 22 U2_PWM3 U2_PWM3 PC1211
TON GND/PWM3

GT@ PR1217
GM@ PR1217 GL@ PR1217 680P_0603_50V7K

3
2
1
1 2 GPU_FBRTN 10 21 10.2K_0402_1% 10.2K_0402_1%

2
RGND PVCC
Rocset
1

VGA@ PR1215 @VGA@ 11 20 U2_LGATE2

TALERT/ISEN2

2
3 100_0402_1% PC1212 VSNS LAGTE2 3
TSNS/ISEN3

VCC/ISNE1

47P_0402_50V8J GPU_COMP 12 19 U2_PHASE2

2

SS PHASE2
UGATE2
PGOOD

@VGA@ PR1235
BOOT2

1 2 GPU_FB
GND

17 VCCSENSE_VGA 0_0402_1%
@VGA@ PC1213 RT8813AGQW_WQFN24_4X4
25

13

14

15

16

17

18

1 2 Css 0.01U_0402_16V7K
+VGA_CORE 1 2
GPU_B+
GPU_DSBL/ISEN1

VGA@ PR1228
GPU_TSNS/ISEN3

GPU_HOT#

100_0402_1%
U2_UGATE2
VGA_PWROK

U2_BOOT2

VGA@ PR1219 VGA@

2200P_0402_50V7K

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6
2.2_0603_5%
PQ1203

@VGA_EMI@

PC1222

PC1218
AON6552_DFN5X6-8-5
U2_BOOT21 2

VGA_EMI@
PC1215
1

1
PC1203
VGA@ PC1214
0.22U_0603_25V7K

2
GPU_VREF 2

VGA@

VGA@
1. VSNS Soft-Start time (Internal) is 0.7ms (PC1213 un-pop) U2_UGATE2 1 2 4
Tss=(Css*Vrefin)/Iss+2.3ms
18.7K_0402_1%

=0.01U*0.9V/5uA+2.3ms=4.1ms (PC1213 pop) VGA@ PR1232

1

+3VS 0_0603_5%
PR1221

VGA@ PL1203
2013/10/28 update PH1201 chang

3
2
1
VGA@

2. Switching frequency setting: +VGA_CORE

470K_0402_5%_TSM0B474J4702RE

0.22UH 20% FDUE0640J -H 25A

Fsw=(Vin-0.5)/(2*Vin*Rton*3.2p)=304.89Khz
1

@VGA@ PR1222

U2_PHASE2 1 4
Common part SL200002E00

10K_0402_1%

2 3
3. Thermal monitoring: VGA@
1

5
1U_0402_6.3V6K

AON6554_DFN5X6-8-5
PQ1204 @VGA_EMI@
2

(VGPU_VREF-VTSNS)/PR23=VTSNS/Rth

1
+5VS PR1227
1
VGA@
VGA@ PH1201

PC1219

4.7_1206_5%
VGA_PWROK 15,32,42
T_min T_typical T_max
2

VGA@ U2_LGATE2 4

1 2
PR1221=18.7K 96.73C 100C 103.1C PR1226
2.2_0603_5%
@VGA_EMI@
PC1220
1 2 680P_0603_50V7K

3
2
1

2
4 4

PR1221=13K 106.38C 110C 113.4C VGA@

PR1225
1

VGA@
+3VS 1 2 PC1221
1U_0402_6.3V6K
2

100K_0402_1%

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/03/19 Deciphered Date 2015/03/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+VGA_CORE
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A5WAM_Bay Trail M_LA‐B981P
Date: Monday, May 12, 2014 Sheet 43 of 47
A B C D E
 5 4 3 2 1

+VGA_CORE
+VGA_CORE PC1305
Under VGA Core
PC1306

PC1307

PC1308

PC1309

PC1310

PC1311

PC1312

PC1313

PC1314
4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
1

1
D D
2

2
VGA@

VGA@

VGA@

VGA@

VGA@

VGA@

VGA@

VGA@

VGA@

VGA@
N15x 2013/12/10

330U_D2_2V_Y
1 1 1

560U_2.5V_M

560U_2.5V_M
+ + + Under

PC1302

@ PC1303

PC1304
4.7uF_0603_10pcs
2 2 2 1uF_0402_4pcs
Near

VGA@

VGA@
47uF_0805_1pcs
22uF_0603_1pcs(2PCS unpop)
4.7U_0805_6.3V6K

4.7uF_0805_5pcs
1

VGA@ PC1346

N15x2013/10/17
2

+VGA_CORE Under
4.7uF_0603_15pcs
Near VGA Core 1uF_0402_8pcs
Near
47uF_0805_0pcs
22uF_0603_9pcs(2PCS unpop)

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
4.7uF_0805_5pcs

1
C C

PC1326 @

PC1327 VGA@

PC1328 @
VGA@ PC1335

VGA@ PC1336

VGA@ PC1337

VGA@ PC1338
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1

2
N15x2013/10/07
Under
2

4.7uF_0603_15pcs
1uF_0402_8pcs
Near
47uF_0805_0pcs
22uF_0805_9pcs(2PCS unpop)
4.7uF_0805_5pcs

N15x2013/10/02
Under
4.7uF_0603_15pcs
1uF_0402_8pcs
Near
47uF_0805_0pcs
22uF_0805_14pcs
4.7uF_0805_5pcs

B B
N14x
47U_0805_6.3V6M

4.7U_0805_6.3V6K

4.7U_0805_6.3V6K

4.7U_0805_6.3V6K

4.7U_0805_6.3V6K
VGA@ PC1341

VGA@ PC1342

VGA@ PC1343

VGA@ PC1344

VGA@ PC1345
Under
1

1
4.7uF_0603_10pcs
0.1uF_0402_4pcs
2

2
Near
47uF_0805_1pcs
22uF_0805_1pcs
4.7uF_0805_5pcs

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/03/19 Deciphered Date 2015/03/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA_CORE CAP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A5WAM_Bay Trail M_LA‐B981P
Date: Monday, May 12, 2014 Sheet 44 of 47
5 4 3 2 1
 5 4 3 2 1

Version change list (P.I.R. List) Page 1 of 2

for PWR
Item Fixed Issue Reason for change Rev. PG# Modify List Date Phase

D 1 D

CPU tranistion 40 PR839 change to 280 ohm 4/9 DVT

2 NV power sequence 43 PR1222 VGA@->@VGA@ 4/9 DVT
3 PR1238 0->15K_0402_1% 4/9 DVT
4
5 PC1210 pop 0.1U(SE00000G880) 4/9 DVT
6 For EMI test 42 PR1007 change to 9.31K 4/23 PVT
7 unused part 38 PR607 change to R-Short 0402 4/23 PVT
8 PR601 change to R-Short 0603 4/23 PVT
9 36 PR407 change to R-Short 0603 4/23 PVT
10 For voltage adjust 38 PR606 change to 15.4K 5/6 PVT
11
C 12 C

13
14

15

16
17
18

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/03/19 Deciphered Date 2015/03/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_PIR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A5WAM_Bay Trail M_LA‐B981P
Date: Monday, May 12, 2014 Sheet 45 of 47
5 4 3 2 1
 5 4 3 2 1

Version Change List ( P. I. R. List ) Page 1/1 for HW

Item Page# Function Date Request Issue Description Solution Description Rev.
Owner
1 P.6/8/28/32 U63.5/U58.5/U53.5/U62.5/U64.5
D HW 5/8 Fix S3/S5 have pluse at singal D
change power source from +1.8VS to +1.8VALW

Change R-short for cost down R236,R237 change to R-Short 0805

2 P.8/15/29 HW 5/8
R1044 change to R-Short 0402
R1015 change to R-Short 0402
3 P.31 HW 5/8 EMI Request from EMI add Bead at speaker
R1094/R1095/R1096/R1097
change from 0ohm to BEAD(SM01000CC00)

4 P.29 HW 5/8 Change EC version to latest change EC U28 to SA000075S30(KB9022QD)

0.2
R506 change from 130K->160K_0402_1%(SD034160380)

5 P.9 HW
5/8 Add for Debug ADD R973 0_0402_5%(@) at USB_HUB reset (connect to SYSON)
ADD R1176/R1173 0_0402_5% for DGPU_PWR_EN_SOC1.8V
C ADD R1175/R1174 0_0402_5% for DGPU_HOLD_RST#_SOC1.8V C

ADD JP2@ R1081@ R1082@(for debug)

6 P.15 HW 5/8 Add PH resistor R1043 change from 0ohm->10K_0402_5%
unpop R2018(DGPU_HOLD_RST#_SOC1.8V) PH resistor

7 P.11 HW 5/8 change cap to improve +1.0VS power rail C1056 C1057 C1059 change footprint from 22U_0805->0603

8 P.4 HW 5/8 Update DA P/N DA P/N change to DA60019D000

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/03/19 Deciphered Date 2015/03/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW P.I.R (1/3)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A5WAM_Bay Trail M_LA‐B981P
Date: Monday, May 12, 2014 Sheet 46 of 47
5 4 3 2 1
 5 4 3 2 1

Z5WE3_DVT Power Sequence AC mode

2013-08-08
BIOS:v0.05
EC:v0.05 G3->S0 S0->S3 S3->S0 S0->S5
ACIN
ACIN
+3VLP
+3VLP
EC_ON
EC_ON 1.53ms
D D
+3VALW
+3VALW 1.58ms

+5VALW
+5VALW
SPOK
SPOK 7.28ms

+1.0VALW
+1.0VALW 8.23ms

+1.8VALW
+1.8VALW

ON/OFF
ON/OFF 95.38ms

101ms EC_RSMRST#
EC_RSMRST#
101ms PBTN_OUT#
PBTN_OUT#
102ms
EC_SLP_S4#
EC_SLP_S4#
102ms
EC_SLP_S3#
EC_SLP_S3#
222ms 204ms
SYSON
SYSON 0.6ms
3.29ms
+1.35V
C
+1.35V 1.71ms
C

3.29ms
33.68ms DDR_PWROK
DDR_PWROK 21ms 22.32ms 36.20ms

VR_ON
VR_ON 2.49ms 2.50ms
8.85ms 9.81ms
+SOC_VCC
+SOC_VCC 2.50ms 2.50ms
10.55ms 11.5ms
+SOC_VNN
+SOC_VNN 0.28ms 279us

VGATE
VGATE 42.56ms
263ms 11.71ms 5.57ms
SUSP#
SUSP# 31.28us 31.12us
2.56ms 2.18ms
+1.0VS
+1.0VS 1.30ms 1.29ms
1.56ms 1.52ms
+1.05VS
+1.05VS 1.84ms 1.83ms
8ms 8.12ms
+1.35VS
+1.35VS 2.79ms 2.8ms
10.71ms 10.71ms
+1.5VS
+1.5VS 2.11ms 2.08ms
16.59ms 16.63ms
+1.8VS
+1.8VS 3.77ms 3.77ms
15.31ms 15.34ms
+3VS
+3VS 4.41ms 4.41ms
B B
20.48ms 20.27ms
+5VS
+5VS 12.83ms 12.77ms
19.61ms 19.60ms
+0.675VS
+0.675VS 49.83ms 49.87ms

144ms
148.3ms
KBRST#
KBRST# 110ms 110ms
11.71ms
PMC_CORE_PWROK
PMC_CORE_PWROK 110ms 110ms
11.71ms
DDR_CORE_PWROK
DDR_CORE_PWROK 116ms 116ms
584ms 8.8ms SUSP#
PMC_PLTRST#
PMC_PLTRST#
2.38ms

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/03/19 Deciphered Date 2015/03/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power Sequence
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A5WAM_Bay Trail M_LA‐B981P
Date: Monday, May 12, 2014 Sheet 47 of 47
5 4 3 2 1