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Compal Confidential
Model Name : A5WAH/A5WAB
File Name : LA-B991P
1 1
Compal Confidential
2 2
3 2014-08-27 3
REV:1.0
4 4
VGA eDP
LVDS
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LVDS-Translator
Fan Control
RTD2132R
page 24
page 36
page 28 page 25
Memory BUS 204pin DDR3L-SO-DIMM X1
BANK 0, 1, 2, 3 page 15
1 HDMI Conn. Dual Channel 1
DP to VGA
ITE IT6513FN eDP
Intel Broadwell ULT 1.35V DDR3L 1333/1600
page 27 204pin DDR3L-SO-DIMM X1
BANK 4, 5, 6, 7 page 16
DDI
DP x 2 lanes
page 26 Broadwell ULT
HDMI x 4 lanes
Processor USB 3.0 USB 2.0
conn x1 conn x2 CMOS
OPI USB port 0 USB/B (port 1,2) Camera
Nvidia N15x USB port 7
with DDR3 x4 or 8
page 31 page 17~23
MINI Card Finger
WLAN PCIe 2.0 PCIe 2.0 x4
USB port 4 5GT/s 5GT/s Print
2
port 4 port 5
Wildcat point USB (port 5)
2
Flexible IO
page 33 page 33 page 25 page 33
PCH
PCIe 2.0 48MHz
5GT/s USBx8
SATA3.0 SATA3.0
port 3 6.0 Gb/s 6.0 Gb/s
port 0 port 1 3.3V 24MHz
HD Audio
Touch
LAN(GbE)/ Card Reader SATA HDD SATA CDROM Screen
Conn. Conn. HDA Codec I2C (PORT1)
Realtek 8411B 1168pin BGA USB (port 6)
page 29 ALC283
page 04~14 page 36 page 25
SPI
page 32 page 32 SPI ROM x2 Int. Speaker Int. MIC Combo Jack
CLK=24MHz
page 7
page 30 ENE page 36 page 36 page 36
page 30 KB9012/9022
page 34
page 33
page 38
+0.675VS +0.675VS power rail for DDR3L terminator ON OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+1.05VS_VTT +1.05V power rail for CPU ON OFF OFF
OFF OFF
Board ID / SKU ID Table for AD channel
+1.05VSDGPU +1.05VSDGPU switched power rail for GPU ON
+1.35V power rail for DDR3L ON ON OFF
Vcc 3.3V +/- 5%
+1.35V
+1.5VSDGPU +1.5VSDGPU power rail for GPU ON OFF OFF
Ra/Rc/Re 100K +/- 5%
Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
+1.5VS +1.5V power rail for CPU ON OFF OFF
ON ON ON*
0 0 0 V 0 V 0 V
+3VALW +3VALW always on power rail
ON ON ON
1 12K +/- 5% 0.347 V 0.354 V 0.360 V
+3VLP B+ to +3VLP power rail for suspend power
ON OFF OFF
2 15K +/- 5% 0.423 V 0.430 V 0.438 V
+3VS +3VALW to +3VS power rail
+3VSDGPU +3VS to +3VSDGPU power rail for GPU ON OFF OFF
3 20K +/- 5% 0.541 V 0.550 V 0.559 V
ON ON ON*
4 27K +/- 5% 0.691 V 0.702 V 0.713 V
+5VALW +5VALWP to +5VALW power rail
ON OFF OFF
5 33K +/- 5% 0.807 V 0.819 V 0.831 V
+5VS +5VALW to +5VS power rail
+RTCVCC RTC power ON ON ON
6 43K +/- 5% 0.978 V 0.992 V 1.006 V
7 56K +/- 5% 1.169 V 1.185 V 1.200 V
8 75K +/- 5% 1.398 V 1.414 V 1.430 V
9 100K +/- 5% 1.634 V 1.650 V 1.667 V
2 2
10 130K +/- 5% 1.849 V 1.865 V 1.881 V
11 160K +/- 5% 2.015 V 2.031 V 2.046 V
12 200K +/- 5% 2.185 V 2.200 V 2.215 V
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
13 240K +/- 5% 2.316 V 2.329 V 2.343 V
EC SM Bus1 address EC SM Bus2 address USB Port Table BTO Option Table
Device Device
3 External BTO Item BOM Structure
Address Address USB 2.0 Port USB Port Unpop @
Smart Battery 0x16 On Board Thermal Senser 0x96
VGA Internal Thermal Senser 0x9E
0 USB Port(Left 3.0) Connector CONN@
1 USB Port(Right 2.0) EC 9022 9022@
2 USB Port(Right 2.0) EC 9012 9012@
PCH SM Bus address 3 UMA Component UMA@
EHCI1
4 Mini Card (WLAN+BT) GPU VGA@
Device Address
ChannelA DIMM0 1010 0000 JDIMM1
5 Touch Screen On Board HDD HDD@
ChannelB DIMM1 1010 0010 JDIMM2
6 Camera EDP panel EDP@
3 7 Finger Print eDP to LVDS LVDS@ 3
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HASWELL_MCP_E
U1A
D D
C54 C45
<29> CPU_DP1_N0 DDI1_TXN0 EDP_TXN0 EDP_TXN0 <27>
C55 B46
<29>
<29>
CPU_DP1_P0
CPU_DP1_N1
B58 DDI1_TXP0
DDI1_TXN1
EDP_TXP0
EDP_TXN1
A47
EDP_TXP0
EDP_TXN1
<27>
<27>
eDP Panel
C58 B47
DP to CRT <29> CPU_DP1_P1
B55 DDI1_TXP1
DDI1_TXN2
EDP_TXP1 EDP_TXP1 <27>
A55 C47
A57 DDI1_TXP2 EDP_TXN2 C46
B57 DDI1_TXN3 EDP_TXP2 A49
DDI1_TXP3 DDI EDP EDP_TXN3 B49
C51 EDP_TXP3
<28> CPU_DP2_N0 DDI2_TXN0
C50 A45 EDP_AUXN <27>
<28> CPU_DP2_P0 DDI2_TXP0 EDP_AUXN
C53 B45 EDP_AUXP <27>
<28> CPU_DP2_N1 DDI2_TXN1 EDP_AUXP
B54
HDMI <28>
<28>
CPU_DP2_P1
CPU_DP2_N2
C49 DDI2_TXP1
DDI2_TXN2 EDP_RCOMP
D20 EDP_COMP R1 1 2 24.9_0402_1% +VCCIOA_OUT
B50 A43 Trace width=20 mils,Spacing=25mil,Max length=100mils
<28> CPU_DP2_P2 DDI2_TXP2 EDP_DISP_UTIL
A53
<28> CPU_DP2_N3 DDI2_TXN3
B53
<28> CPU_DP2_P3 DDI2_TXP3 EDP_DISP_UTIL <27>
1 OF 19 Rev1p2
HASWELL-MCP-E-ULT_BGA1168
@
C C
HASWELL_MCP_E
U1B
C94 1 2 6.8P_0402_50V8C
XEMC@ T20 @ D61
T2 @ K61 PROC_DETECT MISC
N62 CATERR J62 XDP_PRDY#_R @ T157
+1.35V <36> H_PECI PECI PRDY XDP_PREQ#_R
K62 @ T158
2 1 R68 R8 JTA G
PREQ E60 XDP_TCK_R @ T159
+1.05VS_VTT PROC_TCK XDP_TMS_R
62_0402_5% 56_0402_5% E61 @ T160
1 2 H_PROCHOT#_R K63 PROC_TMS E59 XDP_TRST#_R @ T161
<36,41> H_PROCHOT# PROCHOT PROC_TRST XDP_TDI_R
THERMAL F63 @ T162
1
U1 U1 U1 U1
CPU_Haswell intel PMD3558U 1.7G CPU_Haswell intel I3-4030 1.9G CPU Haswell InteI I5-4200U 1.6G CPU Haswell Intel I3-4010U 1.7G
3558@ 4030@ 4200@ 4010@
SA00007G260 SA00007TA60 SA00006SMB0 SA00006SX70
U1 U1 U1 U1 U1
CPU_Haswell intel I5-4210 1.7G CPU_Haswell intel I7-4510 2G CPU Haswell Intel I7-4500U 1.8G CPU_Haswell intel I3-4158U 2G CPU Haswell InteI I3-4005 1.7G
4210@ 4510@ 4500@ 4158@ 4005@
SA00007LO70 SA00007M760 SA00006SLB0 SA00006VW40 SA000072QD0
U1 U1 U1 U1 U1
CPU_Haswell intel I3-4020 1.9G CPU_Haswell intel PMD3556U 1.7G CPU_Haswell intel I7-4550U 1.5G CPU_Haswell intel PDC2957 1.4G CPU_Boardwell intel QGHB 1.6G
A 4020@ 3556@ 4550@ 2957@ QGHB@ A
SA00007MG50 SA000072Y70 SA00006SJA0 SA00007G060 SA00007UH20
ZZZ U1 U1 U1 U1
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D D
HASWELL_MCP_E HASWELL_MCP_E
U1C U1D
<15> DDR_A_DQS#[0..7]
<15> DDR_A_DQS[0..7]
3 OF 19 Rev1p2 4 OF 19 Rev1p2
HASWELL-MCP-E-ULT_BGA1168 HASWELL-MCP-E-ULT_BGA1168
@ @
A A
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PCH_RTCX1
1 2 PCH_RTCX2
R101 10M_0402_5%
Y1
32.768KHZ_12.5PF_Q13FC135000040
2 1
D D
15P_0402_50V8J
18P_0402_50V8J
1 1
C153 C154
2 2
HASWELL_MCP_E
U1E
+RTCVCC
1
C149
+RTCVCC 1U_0402_6.3V6K ME CMOS PCH_RTCX1 AW5
PCH_RTCX2 AY5 RTCX1
R69 2 R72 1 2 1M_0402_5% SM_INTRUDER# AU6 RTCX2 J5
+RTCVCC PCH_INTVRMEN INTRUDER SATA_RN0/PERN6_L3 SATA_PRX_DTX_N0 <34>
20K_0402_1% AV7 RTC H5
1 2 PCH_SRTCRST#
PCH_RTCRST#
AV6 INTVRMEN
SRTCRST
SATA_RP0/PERP6_L3
SATA_TN0/PETN6_L3
B15
SATA_PRX_DTX_P0
SATA_PTX_DRX_N0
<34>
<34>
HDD
1 2 AU7 A15
PCH_INTVRMEN RTCRST SATA_TP0/PETP6_L3 SATA_PTX_DRX_P0 <34>
R73 1 2 330K_0402_5% R70
R74 1 @ 2 330K_0402_5% 20K_0402_1% 1 J8 SATA_PRX_DTX_N1 <34>
1
C150 D
Q52 SATA_RN1/PERN6_L2 H8
SATA_RP1/PERP6_L2 SATA_PRX_DTX_P1 <34>
INTVRMEN 1U_0402_6.3V6K JME1 JME2 2 L2N7002LT1G_SOT23-3 A17
* L:
H:I nt egr at ed VR M enabl e 2
0_0603_5%
<36> EC_RTCRST#
0_0603_5%
DVT modify 11/12
G @ SATA_TN1/PETN6_L2
SATA_TP1/PETP6_L2
B17
SATA_PTX_DRX_N1
SATA_PTX_DRX_P1
<34>
<34>
ODD
I nt egr at ed VR M di s abl e @ @ S
3
add Q19 for EC_RTCRST# HDA_BIT_CLK AW8 J6
2
pull low on EC side HDA_SYNC HDA_BCLK/I2S0_SCLK SATA_RN2/PERN6_L1
AV11 H6
HDA_RST# AU8 HDA_SYNC/I2S0_SFRM SATA_RP2/PERP6_L1 B14
HDA_SDIN0 AY10 HDA_RST/I2S_MCLK SATA_TN2/PETN6_L1 C15
<38> HDA_SDIN0 HDA_SDI0/I2S0_RXD SATA_TP2/PETP6_L1
T6 @ AU12 AUDIO S ATA
C HDA_SDOUT AU11 HDA_SDI1/I2S1_RXD F5 C
HDA for AUDIO ME Debug T7 @ AW10 HDA_SDO/I2S0_TXD
HDA_DOCK_EN/I2S1_TXD
SATA_RN3/PERN6_L0
SATA_RP3/PERP6_L0
E5
<36> HDA_SDO R122 1 @ 2 0_0402_5% T8 @ AV10 C17
T9 @ AY8 HDA_DOCK_RST/I2S1_SFRM SATA_TN3/PETN6_L0 D17
RP14 EMC@ I2S1_SCLK SATA_TP3/PETP6_L0
1 8 HDA_SDOUT RTCRST close RAM door
<38> HDA_SDOUT_AUDIO HDA_RST# PCH_GPIO34
<38> HDA_RST_AUDIO# 2 7 V1 PCH_GPIO34 <9>
3 6 HDA_SYNC SATA0GP/GPIO34 U1 PCH_GPIO35
<38> HDA_SYNC_AUDIO HDA_BIT_CLK SATA1GP/GPIO35 PCH_GPIO36 PCH_GPIO35 <9> +1.05VS_ASATA3PLL
<38> HDA_BITCLK_AUDIO 4 5 V6
SATA2GP/GPIO36 PCH_GPIO37 PCH_GPIO36 <9>
AC1
PCH_JTAG_RST# SATA3GP/GPIO37 PCH_GPIO37 <9>
33_0804_8P4R_5% T95 @ AU62
51_0402_5% 1 @ 2 R97 PCH_JTAG_TCK AE62 PCH_TRST A12 SATA_IREF R75 1 @ 2 0_0603_5%
T21 @ PCH_JTAG_TDI AD61 PCH_TCK SATA_IREF L11 @ T13
T19 @ PCH_JTAG_TDO AE61 PCH_TDI RSVD K10 @ T14
EMI Request C519
PCH_RTCRST#
T15 @ PCH_JTAG_TMS AD62 PCH_TDO
PCH_TMS
JTA G RSVD
SATA_RCOMP
C12 SATA_RCOMP R2 1 2 3.01K_0402_1%
1 2 T10 @ AL11 U3 R10 1 2 +3VS
T11 @ AC4 RSVD SATALED 10K_0402_5%
PVT modify 12/31 T22 @ PCH_TCK_JTAGX AE63 RSVD
0.1U_0402_16V4Z EMI reserved C519 JTAGX SATA_RCOMP, IREF
T12 @ AV2 Trace width=12~15 mil, Spcing=12 mils
XEMC@ RSVD
Max trace length= 500 mil
B BAS40-04_SOT23-3 1 B
C151
0.1U_0402_16V4Z
+RTCBATT
+RTCBATT
2
+CHGRTC
R446
+
1K_0402_5%
@
3 1
+RTCBATT_R
2
20mil
20mil
+RTCVCC
D32
1
CHN202UPT_SC70-3 JBATT1
-
1 @ LOTES_AAA-BAT-054-K01
2
C168 CONN@
0.1U_0402_16V4Z SP07000H700
@
2
A A
1
R52 1 2 10K_0402_5% AD1 CLKOUT_PCIE_P2 SIGNALS TESTLOW_AK8 AL8 R148 1 2 10K_0402_5%
+3VS PCIECLKRQ2/GPIO20 TESTLOW_AL8
C2 C3 <31> LAN_CLKREQ# CLK_PCIE_MINI1# B38 AN15 CLKOUT_LPC0 R390 2 EMC@ 1 22_0402_5%
15P_0402_50V8J 15P_0402_50V8J <33> CLK_PCIE_MINI1# CLK_PCI_LPC <36>
2
6 OF 19 Rev1p2
HASWELL-MCP-E-ULT_BGA1168
@
HASWELL_MCP_E
U1G
LPC_AD0 AU14 AN2 PCH_GPIO11
+3VS <36,37> LPC_AD0 LPC_AD1 LAD0 SMBALERT/GPIO11 PCH_SMBCLK PCH_GPIO11 <9>
AW12 AP2
<36,37> LPC_AD1 LPC_AD2 LAD1 LPC SMBCLK PCH_SMBDATA PCH_SMBCLK <33>
AY12 AH1
<8,9,40,51> DGPU_PWR_EN <36,37> LPC_AD2 LPC_AD3 LAD2 SMBDATA PCH_GPIO60 PCH_SMBDATA <33>
AW11 AL2
<36,37> LPC_AD3 PCH_GPIO60 <9>
1
SML1ALERT/PCHHOT/GPIO73
G
SML0DATA
1
7 OF 19 Rev1p2
HASWELL-MCP-E-ULT_BGA1168
@
+3V_SPI for Share EC ROM, +3VS change to +3VALW PVT modify 1/20
R105 1 2 1K_0402_5% PCH_SPI_IO2_1 R126 chang R126 to R-short
R106 1 2 1K_0402_5% PCH_SPI_IO3_1 +3V_SPI 1 @ 2 0_0402_5%
+3V_SPI +3VALW
R123
+3V_SPI 1 @ 2 0_0402_5%
PCH_SPI_HOLD1# +3VS
R103 1 @ 2 1K_0402_5%
R102 1 @ 2 1K_0402_5% PCH_SPI_WP1# SPI ROM ( 8MByte ) +3VS
2ROM pop
C66 1 2 +3VS
2
U6 RP19
PCH_SPI_CS0# 1 8 0.1U_0402_16V4Z PCH_SPI_MISO_1 1 8 PCH_SPI_MISO R116 R119
PCH_SPI_MISO_1 2 CS# VCC 7 PCH_SPI_IO3_1 PCH_SPI_IO3_1 2 7 PCH_SPI_HOLD1# SPI ROM Q7A 4.7K_0402_5% 4.7K_0402_5%
2
PCH_SPI_WP1# 2 1 PCH_SPI_IO2_1 3 DO(IO1) HOLD#(IO3) 6 PCH_SPI_CLK_1 PCH_SPI_CLK_1 3 6 PCH_SPI_CLK DMN66D0LDW-7_SOT363-6
R108 15_0402_5% 4 WP#(IO2) CLK 5 PCH_SPI_MOSI_1 PCH_SPI_MOSI_1 4 5 PCH_SPI_MOSI
1
B GND DI(IO0) PCH_SMBDATA 6 1 D_CK_SDATA B
D_CK_SDATA <15,16,39>
EN25QH64-104HIP_SO8 15_0804_8P4R_5%
5
DDR, G-sensor
PCH_SMBCLK 3 4 D_CK_SCLK
D_CK_SCLK <15,16,39>
Reserve for EMI(Near SPI ROM) PCH_SPI_MOSI_1
C152 R498 1 @ 2 0_0402_5% EC_SPI_SO <36> Q7B
10P_0402_50V8J PCH_SPI_CLK_1 R500 1 @ 2 0_0402_5% From EC DMN66D0LDW-7_SOT363-6
EC_SPI_CLK <36>
1 2 2 1 PCH_SPI_CLK_1 PCH_SPI_MISO_1 R502 1 @ 2 0_0402_5% EC_SPI_SI <36>
(For share ROM)
R104 XEMC@ 33_0402_5% PCH_SPI_CS0# R505 1 @ 2 0_0402_5% EC_SPI_CS# <36>
XEMC@
DVT modify 11/15 +3VS
pop share rom
PVT modify 01/06
change to R-short Q8A
2
DMN66D0LDW-7_SOT363-6
PU 2.2K at EC side (+3VS)
SML1CLK 6 1 EC_SMB_CK2 <17,36>
5
+3V_SPI VGA, EC
SPI ROM ( 4MByte ) 2ROM pop PCH_SPI_MOSI_2
RP20 SML1DATA 3 4 EC_SMB_DA2 <17,36>
C67 1 2 1 8 PCH_SPI_MOSI
U7 @ PCH_SPI_CLK_2 2 7 PCH_SPI_CLK Q8B
PCH_SPI_CS1# 1 8 0.1U_0402_16V4Z PCH_SPI_IO3_2 3 6 PCH_SPI_HOLD1# DMN66D0LDW-7_SOT363-6
PCH_SPI_MISO_2 2 CS# VCC 7 PCH_SPI_IO3_2 PCH_SPI_MISO_2 4 5 PCH_SPI_MISO
PCH_SPI_WP1# 2 @ 1 R109 PCH_SPI_IO2_2 3 DO HOLD# 6 PCH_SPI_CLK_2 33_0804_8P4R_5%
4 WP# CLK 5 PCH_SPI_MOSI_2 @
33_0402_5% GND DI
EN25QH32-104HIP_SO8
@
A A
+3VS
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1
R227
10K_0402_5% DSWODVREN - On Die DSW VR Enable
H:Ena bl e( DEF A UL T)
2
SYS_RESET#
* L :Di s a bl e
+RTCVCC
2 HASWELL_MCP_E
PVT modify 01/06 U1H
C513 R62, R64 change to R-short R124 1 2 330K_0402_5%
D 0.01U_0402_16V7K R125 1 @ 2 330K_0402_5%
D
1 R206 SYSTEM POWER MANAGEMENT
XEMC@
SUSWARN# 1 @ 2 0_0402_5% SUSACK# AK2 AW7 DSWODVREN
SYS_RESET# AC3 SUSACK DSWVRMEN AV5 PCH_RSMRST#_R
SYS_PWROK R61 1 @ 2 0_0402_5% SYS_PWROK_R AG2 SYS_RESET DPWROK AJ5 PCH_PCIE_WAKE#
place near AC3 SYS_PWROK WAKE PCH_PCIE_WAKE# <31>
R62 1 @ 2 0_0402_5% PCH_PWROK_R AY7 1K_0402_5% 1 2 R120
<36> PCH_PWROK PM_APWROK PCH_PWROK +3VALW_PCH
<11,36> VCCST_PG_EC R63 1 @ 2 0_0402_5% AB5 8.2K_0402_5% 1 2 R157 +3VS
AG7 APWROK V5 CLKRUN#
PCH_PWROK_R PLTRST CLKRUN/GPIO32 CLKRUN# <37>
R64 1 @ 2 0_0402_5% AG4
PLT_RST# SUS_STAT/GPIO61 AE6 SUSCLK R127 1 @ 2
<17,36,37> PLT_RST# SUSCLK/GPIO62 PM_SLP_S5# 10K_0402_5%
AP5
PCH_RSMRST# SLP_S5/GPIO63 PM_SLP_S5# <36>
R117 1 2 10K_0402_5% <36> PCH_RSMRST# R79 1 @ 2 0_0402_5% PCH_RSMRST#_R AW6 @ T27
SUSWARN# AV4 RSMRST @ T28 @ T29
<9> SUSWARN# PBTN_OUT#_R SUSWARN/SUSPWRDNACK/GPIO30 PM_SLP_S4#
<36> PBTN_OUT# R110 1 @ 2 0_0402_5% AL7 AJ6
PCH_ACIN PWRBTN SLP_S4 PM_SLP_S3# PM_SLP_S4# <36>
AJ8 AT4
ACPRESENT/GPIO31 SLP_S3 PM_SLP_S3# <36>
+3VALW_PCH R156 1 2 8.2K_0402_5% PCH_BATLOW# AN4 AL5 @ T30
T31 @ AF3 BATLOW/GPIO72 SLP_A AP4 @ T96
AM5 SLP_S0 SLP_SUS AJ7 PM_SLP_LAN# R118 1 @ 2
+3VALW_PCH SLP_WLAN/GPIO29 SLP_LAN +3VALW_PCH
10K_0402_5%
1
1 2 PCH_ACIN
<36,41,43> ACIN ACPRESENT funct i on
RB751V-40 SOD-323
+3VS
5
C R65 C
PCH_PWROK
DDPB_CTRLDATA: Port B Detected
2 0_0402_5%
P
B 4 SYS_PWROK 1 2 PCH_PWROK
VGATE_3V Y DDPC_CTRLDATA: Port C Detected
1
A
G
1
HASWELL_MCP_E
U1I
+3VS
+3VS
+1.05VS_VTT B8 B9
<26,27> PCH_INV_PWM
1
RP27 1 8 G_SEN_INT
2 7 PCH_GPIO80
3 6 MINI1_CLKREQ# 9 OF 19 Rev1p2
MINI1_CLKREQ# <7,33>
4 5 DEVSLP0 DEVSLP0 <9,34> HASWELL-MCP-E-ULT_BGA1168
10K_0804_8P4R_5% @
+3VS
10K_0402_5%
+3VS
5
U30
+3VS +3VS PLT_RST# 2
P
B 4
Y PLT_RST_BUF# <31,33>
1
1
1
G
A
R205 R204 MC74VHC1G08DFT2G_SC70-5 R416
Project_ID1 Project_ID0
3
10K_0402_5% 10K_0402_5% 100K_0402_5%
BA50@ @ Project ID
GPIO54 GPIO53
2
2
Project_ID1 Project_ID0
*Z5WAH 0 0
2
+3VS
RP23 1 8 PCH_GPIO87
+3VS
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RP36 1 8 EC_SMI#_SCI#
2 7 PCH_GPIO51 2 7 PCH_GPIO85
PCH_GPIO51 <8> PCH_GPIO92
3 6 3 6
4 5 PCH_GPIO83 4 5 PCH_GPIO88
10K_0804_8P4R_5% 10K_0804_8P4R_5%
RP24 1 8 PCH_GPIO68
2 7 PCH_GPIO69
3 6
4 5 change to I2C0 for TS use
10K_0804_8P4R_5%
RP25 1 8 PCH_GPIO1 +1.05VS_VTT
2 7 PCH_GPIO94
D PCH_GPIO93 D
3 6
1
4 5 PCH_GPIO2 U1J HASWELL_MCP_E
10K_0804_8P4R_5% R144
RP26 1 8 PCH_GPIO91
1K_0402_5%
2 7 PCH_GPIO0
3 6 PCH_GPIO90
2
4 5 PCH_GPIO38 PCH_GPIO76 P1 D60 H_THERMTRIP#
10K_0804_8P4R_5% PCH_GPIO8 AU2 BMBUSY/GPIO76 THERMTRIP V4
PCH_GPIO19 GPIO8 RCIN/GPIO82 EC_KBRST# <36>
RP16 1 8 PCH_GPIO19 <7> AM7 T4 SERIRQ SERIRQ <36,37>
2 7 PCH_GPIO36 EC_LID_OUT# AD6 LAN_PHY_PWR_CTRL/GPIO12 CPU/ SERIRQ AW15 PCH_OPIRCOMP 1 2 R145
TP_INT# PCH_GPIO36 <6> <36> EC_LID_OUT# PCH_GPIO16 GPIO15 MISC PCH_OPI_RCOMP
3 6 TP_INT# <8,37> Y1 AF20 @ T106 49.9_0402_1%
4 5 SERIRQ PCH_GPIO17 T3 GPIO16 RSVD AB21 @ T32
10K_0804_8P4R_5% PCH_GPIO24 AD5 GPIO17 RSVD
RP28 1 8 PCH_GPIO18 CPU_IDEN AN5 GPIO24
PCH_GPIO35 PCH_GPIO18 <7> PCH_GPIO28 GPIO27
2 7 PCH_GPIO35 <6> AD7
3 6 PCH_GPU_ACIN DGPU_IDEN AN3 GPIO28
4 5 PCH_GPIO34 GPIO26 R6 PCH_GPIO83
PCH_GPIO34 <6> PCH_GPIO56 AG6 GSPI0_CS/GPIO83 PCH_GPIO84
10K_0804_8P4R_5% L6 +3VS +3VS
RP29 1 8 PCH_GPIO71 PCH_GPIO57 AP1 GPIO56 GSPI0_CLK/GPIO84 N6 PCH_GPIO85
2 7 PCH_GPIO16 PCH_GPIO58 AL4 GPIO57 GSPI0_MISO/GPIO85 L8 PCH_GPIO86 PVT modify 01/06
3 6 EC_KBRST# PCH_GPIO59 AT5 GPIO58 GSPI0_MOSI/GPIO86 R7 PCH_GPIO87 change PCH GPIO4/GPIO5 to
4 5 PCH_GPIO37 R71 PCH_GPIO44 AK4 GPIO59 GSPI1_CS/GPIO87 L5 PCH_GPIO88 PCH_I2C0_SDA/PCH_I2C0_SCL
PCH_GPIO37 <6> PCH_GPIO47 AB6 GPIO44 GSPI1_CLK/GPIO88 PCH_GPIO89
10K_0804_8P4R_5% 0_0402_5% GPIO N7
DGPU_AC_DETECT 1 @ 2 PCH_GPU_ACIN U4 GPIO47 GSPI1_MISO/GPIO89 K2 PCH_GPIO90 R275 R274
<17,36> DGPU_AC_DETECT
2
RP30 8 1 PCH_GPIO67 DGPU_PRSNT# Y3 GPIO48 GSPI_MOSI/GPIO90 J1 PCH_GPIO91 2.2K_0402_5%
GPIO49 UART0_RXD/GPIO91 2.2K_0402_5%
7 2 PCH_GPIO65 TS_INT# P3 K3 PCH_GPIO92
DGPU_HOLD_RST# <27> TS_INT# PCH_GPIO71 GPIO50 UART0_TXD/GPIO92 PCH_GPIO93
6 3 DGPU_HOLD_RST# <8,17> Y2 J2 R277 R276
5 4 PCH_GPIO64 PCH_GPIO13 AT3 HSIOPC/GPIO71 LPIO UART0_RTS/GPIO93 G1 PCH_GPIO94 2.2K_0402_5% 2.2K_0402_5%
10K_0804_8P4R_5% PCH_GPIO14 AH4 GPIO13 UART0_CTS/GPIO94 K4 PCH_GPIO0
1
RP31 8 1 PCH_GPIO84 PCH_GPIO25 AM4 GPIO14 UART1_RXD/GPIO0 G2 PCH_GPIO1
7 2 PCH_GPIO3 PCH_GPIO45 AG5 GPIO25 UART1_TXD/GPIO1 J3 PCH_GPIO2
6 3 PCH_GPIO46 AG3 GPIO45 UART1_RST/GPIO2 J4 PCH_GPIO3
5 4 PCH_GPIO89 GPIO46 UART1_CTS/GPIO3 F2 PCH_I2C0_SDA
C PCH_GPIO9 AM3 I2C0_SDA/GPIO4 PCH_I2C0_SCL PCH_I2C0_SDA <27> Touch Screen C
10K_0804_8P4R_5% F3
PCH_GPIO17 PCH_GPIO10 AM2 GPIO9 I2C0_SCL/GPIO5 PCH_I2C1_SDA PCH_I2C0_SCL <27>
RP32 8 1 G4
PCH_GPIO23 GPIO10 I2C1_SDA/GPIO6 PCH_I2C1_SCL PCH_I2C1_SDA <37>
7 2 PCH_GPIO23 <7> DEVSLP0 P2 F1 Touch Pad
PCH_GPIO76 GPU_EVENT# <8,34>DEVSLP0 PCH_GPIO70 DEVSLP0/GPIO33 I2C1_SCL/GPIO7 PCH_GPIO64 PCH_I2C1_SCL <37>
6 3 2 1 C4 E3
<17> GPU_EVENT# SDIO_POWER_EN/GPIO70 SDIO_CLK/GPIO64
5 4 R2058 GC6@ 0_0402_5% PCH_GPIO38 L2 F4 PCH_GPIO65
10K_0804_8P4R_5% EC_SMI#_SCI# N5 DEVSLP1/GPIO38 SDIO_CMD/GPIO65 D3 PCH_GPIO66
<36> EC_SMI#_SCI# PCH_SPKR DEVSLP2/GPIO39 SDIO_D0/GPIO66 PCH_GPIO67
V2 E4
PCH_GPIO70 <38> PCH_SPKR SPKR/GPIO81 SDIO_D1/GPIO67 PCH_GPIO68
R216 1 NGC6@ 2 C3
10K_0402_5% SDIO_D2/GPIO68 E2 PCH_GPIO69
R217 1 2 DGPU_PWR_EN SDIO_D3/GPIO69
DGPU_PWR_EN <7,8,40,51>
10K_0402_5% 10 OF 19 Rev1p2
Pre MP modify 03/10 HASWELL-MCP-E-ULT_BGA1168
+3VALW_PCH solve VGA sequence error issue @
RP34 1 8 PCH_GPIO10
2 7 PCH_GPIO11
PCH_GPIO57 PCH_GPIO11 <7>
3 6
4 5 PCH_GPIO13
10K_0804_8P4R_5%
RP35 1 8 USB_OC1#
PCH_GPIO8 USB_OC1# <10>
2 7
3 6 PCH_GPIO73
PCH_GPIO73 <7>
4 5 SUSWARN#
SUSWARN# <8>
10K_0804_8P4R_5% +3VALW_PCH +3VS
RP37 1 8 PCH_GPIO46
2 7 PCH_GPIO42 R269 1 @ 2 1K_0402_5% PCH_SPKR
PCH_GPIO14 PCH_GPIO42 <10> EC_LID_OUT#
3 6 R247 1 @ 2 10K_0402_5%
4 5 PCH_GPIO60
PCH_GPIO60 <7>
10K_0804_8P4R_5%
RP38 1 8 GPIO15 : TLS Conf i dent ial i t SPKR / GPIO81 : NO REBOOT
2 7 PCH_GPIO47
3 6 PCH_GPIO45
B 4 5 PCH_GPIO24 B
1: Intel ME TLS with conf i dent ial i ty 1: ENABLED
10K_0804_8P4R_5%
RP39 1 8 PCH_GPIO43
0: Intel ME TLS with no conf i dent ial i t 0: DISABLED (Have internal PD)
2
3
7
6
PCH_GPIO59
PCH_GPIO25
PCH_GPIO58
PCH_GPIO43 <10>
* (Have internal PD)
*
4 5
10K_0804_8P4R_5%
RP40 1 8 USB_OC0#
PCH_GPIO56 USB_OC0# <10,35>
2 7
3 6 PCH_GPIO44
4 5 PCH_GPIO9
10K_0804_8P4R_5% +3VS
PCH_GPIO66 R270 1 @ 2 1K_0402_5%
+3VALW_PCH PCH_GPIO86 R272 1 @ 2 1K_0402_5%
+3VS R273 1 2 1K_0402_5%
1
1
R2605
R306 10K_0402_5% GSPI0_MOSI / GPIO86 : Boot BIOS Strap SDIO_D0 / GPIO66 : Top-Block Swap Override
10K_0402_5% SR@ A5WAH Pre MP 0819
UMA@ SR for PU, DR for PD
2
PCH_GPIO28
DGPU_PRSNT# GPIO49 CPU INFO 0: SPI ROM (Have internal PD) 0: DISABLED (Have internal PD)
* *
2
DGPU_PRSNT#
2
R2604
R219 10K_0402_5%
Dual Rank 0
10K_0402_5%
DIS,Optimus 0 DR@
VGA@
Single Rank 1
UMA 1
1
1
+3VALW_PCH +3VALW_PCH
A A
1
R311 R312
10K_0402_5% 10K_0402_5%
VGM@ BW@
2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A5WAH M/B LA-B991P
Date: Friday, October 17, 2014 Sheet 9 of 54
5 4 3 2 1
5 4 3 2 1
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D D
HASWELL_MCP_E
U1K
A A
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+1.35V +1.35V_CPU
@ J6
1 2
D
+CPU_CORE D
HASWELL_MCP_E
JUMP_43X118 U1L
Shark Bay ULT have internal gate for VDDQ T37 @ L59 C36
+1.35V_CPU T38 @ J58 RSVD VCC C40
RSVD VCC C44
AH26 VCC C48
AJ31 VDDQ VCC C52
AJ33 VDDQ VCC C56
AJ37 VDDQ VCC E23
AN33 VDDQ VCC E25
AP43 VDDQ VCC E27
+3VS AR48 VDDQ VCC E29
+1.05VS_VTT AY35 VDDQ VCC E31
AY40 VDDQ VCC E33
1
1
R422 +CPU_CORE AY50 VDDQ VCC E37
100K_0402_5% U16 R309 VDDQ VCC E39
@ 1 5 10K_0402_5% F59 VCC E41
NC VCC R166 T39 @ N58 VCC VCC E43
2
2
A 4 VCCST_PG_EC_R 1 @ 2 +1.05VS_VTT RSVD VCC E47
Y VCCST_PWRGD <36,46> VCC_SENSE_R VCC
3 E63 E49
GND T41 @ AB23 VCC_SENSE VCC E51
74AUP1G07GW_TSSOP5 2 R164 1 A59 RSVD VCC E53
@ 0_0603_5% E20 VCCIO_OUT VCC E55
+VCCIOA_OUT VCCIOA_OUT VCC
T42 @ AD23 E57
T43 @ AA23 RSVD VCC F24
T44 @ AE59 RSVD VCC F28
RSVD VCC F32
H_CPU_SVIDALRT# L62 VCC F36
0_0402_5% 1 @ 2 R165 H_CPU_SVIDCLK N63 VIDALERT VCC F40
<48> VR_SVID_CLK VIDSCLK VCC
VIDSOUT L63 F44
+1.05VS_VTT VCCST_PG_EC_R B59 VIDSOUT HSW ULT POWER VCC F48
C 0_0402_5% 1 @ 2 R167 PCH_VR_EN F60 VCCST_PWRGD VCC F52 C
<48> VR_ON VR_READY VR_EN VCC
<8,48> VGATE 0_0402_5% 1 @ 2 R168 C59 F56
@ C167 VR_READY VCC G23
2
1 2 0.1U_0402_16V4Z D63 VCC G25
R169 CPU_PWR_DEBUG H59 VSS VCC G27
SVID ALERT 150_0402_1% Reserved Only P62 PWR_DEBUG
VSS
VCC
VCC
G29
@ T45 @ P60 G31
1 PVT modify 01/06 T46 @ P61 RSVD_TP VCC G33
+1.05VS_VTT R167, R168 change to R-short T47 @ N59 RSVD_TP VCC G35
Place the CPU CPU_PWR_DEBUG RSVD_TP VCC
resistors close to CPU T48 @ N61 G37
T98 @ T59 RSVD_TP VCC G39
1
0_0402_5%
2 @ 1 VIDSOUT +1.05VS_VTT
<48> VR_SVID_DATA
+1.35V_CPU
+CPU_CORE
VDDQ DECOUPLING
1U_0402_6.3V6K
@
22U_0805_6.3V6M
1 1
1
C7
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
EMC@ EMC@ 1
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
C6
R177 1 1 1 1 1 1 1 1 1 1
C8
C9
C10
C11
@ @ + C18
100_0402_1% Note: 0 ohm PLACED CLOSE TO CPU
2 2
C12
C13
C14
C15
C16
C17
330U_2.5V_M
2
VCC_SENSE_R 2 @ 1 R178 2 2 2 2 2 2 2 2 2 2 2
VCC_SENSE <48>
0_0402_5% SF000006S00
330U 2.5V H4.2
17mohm OSCON
<13> VSS_SENSE_R 2 @ 1 R235
VSS_SENSE <48>
0_0402_5%
1
+1.35V : 470UF/2V/7343 *2
R233
100_0402_1%
10UF/6.3V/0603 * 6
2.2UF/6.3V/0402 * 4
2
A A
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D D
+1.05VS_VTT
+1.05VS_VTT HASWELL_MCP_E
U1M
K9 +3VALW_PCH +RTCVCC
L10 VCCHSIO
1U_0402_6.3V6K
1 SF000006R00 M9 VCCHSIO C30 1 2 1U_0402_6.3V6K
1U_0402_6.3V6K
C408 + 220U 6.3V OSCON N8 VCCHSIO mPHY AH11
ESR 17mohm@100Khz P9 VCC1_05 RTC VCCSUS3_3 AG10
1U_0402_6.3V6K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 1 1 VCC1_05 VCCRTC +RTCVCC
220U_6.3V_M +1.05VS_AUSB3PLL B18 AE7 +VCCRTCEXT 1 2 1 1 1
2 VCCUSB3PLL DCPRTC
C21
C20
C31 +1.05VS_ASATA3PLL B11 C54 0.1U_0402_16V4Z @ @
VCCSATA3PLL +3V_SPI
C52
C51
C50
1U_0402_6.3V6K
2 2 2
EMC@ 2 2 2
Y20 SPI Y8 C58 2 1 0.1U_0402_16V4Z
AA21 RSVD OPI VCCSPI @
Near PJ601 +1.05VS_APLLOPI VCCAPLL
Near K9 Near L10 Near M9 W21
VCCAPLL AG14
VCCASW +1.05VS_VTT
AG13
+3VALW_PCH VCCASW
+1.05VS_VTT +1.05VS_AUSB3PLL +1.05VS_VTT
HDA --> 3.3V or 1.5V T105 @ J13 USB3 @
Near B18 I2C --> 1.8V DCPSUS3 J11 C27 1 2 10U_0603_6.3V6M C2567 0.47U_0402_6.3V6K
C42 1 2 1U_0402_6.3V6K VCC1_05 H11 C33 1 2 1U_0402_6.3V6K 1 2
VCC1_05 +3VALW_PCH
L1 1 2 C32 1 2 100U_1206_6.3V6M 2 1 C38 AH14 AXALIA/HDA H15 C40 1 2 10U_0603_6.3V6M
2.2UH_LQM2MPN2R2NG0L_30% 1U_0402_6.3V6K VCCHDA VCC1_05 AE8 EMC@
VCC1_05 Broadwell only
Idc 1.2A Rdc 0.11ohm +/-30% AF22 1U_0402_6.3V6K Intel recommends a 0.47uF boot strap
T116 @ AH13 VRM/USB2/AZALIA VCC1_05 AG19 +PCH_VCCDSW 1 @ 2+PCH_VCCDSW_R C41 1 2
+1.05VS_ASATA3PLL DCPSUS2 CORE DCPSUSBYP capacitor to be placed between V3.3DSW
AG20 R209 0_0402_5%
C +3VALW_PCH DCPSUSBYP AE9
and DcpSUSByp power rail C
VCCASW +1.05VS_VTT to support in-rush current.
Near B11 C28 AF9 C36 1 2 22U_0805_6.3V6M
C46 1 2 1U_0402_6.3V6K Near AC9 2 1 22U_0805_6.3V6M AC9 VCCASW AG8 C37 1 2 1U_0402_6.3V6K
L2 1 2 C61 1 2 100U_1206_6.3V6M C59 @ AA9 VCCSUS3_3 VCCASW AD10 C43 @1 2 1U_0402_6.3V6K
2.2UH_LQM2MPN2R2NG0L_30% Near AH10 2 1 0.1U_0402_16V4Z AH10 VCCSUS3_3 DCPSUS1 AD8
Idc 1.2A Rdc 0.11ohm +/-30% C29 V8 VCCDSW3_3 GPIO/LCC DCPSUS1
Near V8 2 1 22U_0805_6.3V6M W9 VCC3_3
+1.05VS_APLLOPI VCC3_3 J15
+3VS VCCTS1_5 +1.5VS
THERMAL SENSOR K14
VCC3_3 +3VS
Near AA21 K16 C55 1 2 0.1U_0402_16V4Z
C47 1 2 1U_0402_6.3V6K VCC3_3
L3 1 2 C22 1 2 100U_1206_6.3V6M
2.2UH_LQM2MPN2R2NG0L_30% +1.05VS_AXCK_DCB J18
Idc 1.2A Rdc 0.11ohm +/-30% K19 VCCCLK SDIO/PLSS U8
VCCCLK VCCSDIO +3VS
+1.05VS_AXCK_LCPLL A20 T9 C44 1 2 1U_0402_6.3V6K
J17 VCCACLKPLL VCCSDIO
+1.05VS_VTT VCCCLK
C57 R21
+1.05VS_VTT +1.05VS_AXCK_DCB Near J17 2 1 1U_0402_6.3V6K T21 VCCCLK LPT LP POWER C53 @1 2 1U_0402_6.3V6K
C56 T100 @ K18 VCCCLK SUS OSCILLATOR AB8 C25 @1 2 100U_1206_6.3V6M
Near J18 Near R21 2 1 1U_0402_6.3V6K T101 @ M20 RSVD DCPSUS4
C48 1 2 1U_0402_6.3V6K T102 @ V21 RSVD
L4 1 2 C23 1 2 100U_1206_6.3V6M AE20 RSVD AC20 @ T103
+3VALW_PCH VCCSUS3_3 RSVD
2.2UH_LQM2MPN2R2NG0L_30% AE21 AG16 +1.05VS_VTT
Idc 1.2A Rdc 0.11ohm +/-30% VCCSUS3_3 USB2 VCC1_05 AG17
VCC1_05 C45 1 2 1U_0402_6.3V6K
+1.05VS_AXCK_LCPLL
Near A20
C49 1 2 1U_0402_6.3V6K 13 OF 19 Rev1p2
L5 1 2 C24 1 2 100U_1206_6.3V6M HASWELL-MCP-E-ULT_BGA1168
2.2UH_LQM2MPN2R2NG0L_30% @
Idc 1.2A Rdc 0.11ohm +/-30%
B B
A A
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D D
HASWELL_MCP_E HASWELL_MCP_E
U1N U1O U1P HASWELL_MCP_E
H17
A11 AJ35 AP22 AV59 D33 VSS H57
A14 VSS VSS AJ39 AP23 VSS VSS AV8 D34 VSS VSS J10
A18 VSS VSS AJ41 AP26 VSS VSS AW16 D35 VSS VSS J22
A24 VSS VSS AJ43 AP29 VSS VSS AW24 D37 VSS VSS J59
A28 VSS VSS AJ45 AP3 VSS VSS AW33 D38 VSS VSS J63
A32 VSS VSS AJ47 AP31 VSS VSS AW35 D39 VSS VSS K1
A36 VSS VSS AJ50 AP38 VSS VSS AW37 D41 VSS VSS K12
A40 VSS VSS AJ52 AP39 VSS VSS AW4 D42 VSS VSS L13
A44 VSS VSS AJ54 AP48 VSS VSS AW40 D43 VSS VSS L15
A48 VSS VSS AJ56 AP52 VSS VSS AW42 D45 VSS VSS L17
A52 VSS VSS AJ58 AP54 VSS VSS AW44 D46 VSS VSS L18
A56 VSS VSS AJ60 AP57 VSS VSS AW47 D47 VSS VSS L20
AA1 VSS VSS AJ63 AR11 VSS VSS AW50 D49 VSS VSS L58
AA58 VSS VSS AK23 AR15 VSS VSS AW51 D5 VSS VSS L61
AB10 VSS VSS AK3 AR17 VSS VSS AW59 D50 VSS VSS L7
AB20 VSS VSS AK52 AR23 VSS VSS AW60 D51 VSS VSS M22
AB22 VSS VSS AL10 AR31 VSS VSS AY11 D53 VSS VSS N10
AB7 VSS VSS AL13 AR33 VSS VSS AY16 D54 VSS VSS N3
AC61 VSS VSS AL17 AR39 VSS VSS AY18 D55 VSS VSS P59
AD21 VSS VSS AL20 AR43 VSS VSS AY22 D57 VSS VSS P63
AD3 VSS VSS AL22 AR49 VSS VSS AY24 D59 VSS VSS R10
C AD63 VSS VSS AL23 AR5 VSS VSS AY26 D62 VSS VSS R22 C
AE10 VSS VSS AL26 AR52 VSS VSS AY30 D8 VSS VSS R8
AE5 VSS VSS AL29 AT13 VSS VSS AY33 E11 VSS VSS T1
AE58 VSS VSS AL31 AT35 VSS VSS AY4 E17 VSS VSS T58
AF11 VSS VSS AL33 AT37 VSS VSS AY51 F20 VSS VSS U20
AF12 VSS VSS AL36 AT40 VSS VSS AY53 F26 VSS VSS U22
AF14 VSS VSS AL39 AT42 VSS VSS AY57 F30 VSS VSS U61
AF15 VSS VSS AL40 AT43 VSS VSS AY59 F34 VSS VSS U9
AF17 VSS VSS AL45 AT46 VSS VSS AY6 F38 VSS VSS V10
AF18 VSS VSS AL46 AT49 VSS VSS B20 F42 VSS VSS V3
AG1 VSS VSS AL51 AT61 VSS VSS B24 F46 VSS VSS V7
AG11 VSS VSS AL52 AT62 VSS VSS B26 F50 VSS VSS W20
AG21 VSS VSS AL54 AT63 VSS VSS B28 F54 VSS VSS W22
AG23 VSS VSS AL57 AU1 VSS VSS B32 F58 VSS VSS Y10
AG60 VSS VSS AL60 AU16 VSS VSS B36 F61 VSS VSS Y59
AG61 VSS VSS AL61 AU18 VSS VSS B4 G18 VSS VSS Y63
AG62 VSS VSS AM1 AU20 VSS VSS B40 G22 VSS VSS
AG63 VSS VSS AM17 AU22 VSS VSS B44 G3 VSS
AH17 VSS VSS AM23 AU24 VSS VSS B48 G5 VSS V58
AH19 VSS VSS AM31 AU26 VSS VSS B52 G6 VSS VSS AH46
AH20 VSS VSS AM52 AU28 VSS VSS B56 G8 VSS VSS V23
AH22 VSS VSS AN17 AU30 VSS VSS B60 H13 VSS VSS E62
VSS VSS VSS VSS VSS VSS_SENSE VSS_SENSE_R <11>
AH24 AN23 AU33 C11 AH16
AH28 VSS VSS AN31 AU51 VSS VSS C14 16 OF 19 Rev1p2 VSS
AH30 VSS VSS AN32 AU53 VSS VSS C18 HASWELL-MCP-E-ULT_BGA1168
AH32 VSS VSS AN35 AU55 VSS VSS C20
VSS VSS VSS VSS @
AH34 AN36 AU57 C25
AH36 VSS VSS AN39 AU59 VSS VSS C27
AH38 VSS VSS AN40 AV14 VSS VSS C38
AH40 VSS VSS AN42 AV16 VSS VSS C39
AH42 VSS VSS AN43 AV20 VSS VSS C57
AH44 VSS VSS AN45 AV24 VSS VSS D12
AH49 VSS VSS AN46 AV28 VSS VSS D14
B AH51 VSS VSS AN48 AV33 VSS VSS D18 B
AH53 VSS VSS AN49 AV34 VSS VSS D2
AH55 VSS VSS AN51 AV36 VSS VSS D21
AH57 VSS VSS AN52 AV39 VSS VSS D23
AJ13 VSS VSS AN60 AV41 VSS VSS D25
AJ14 VSS VSS AN63 AV43 VSS VSS D26
AJ23 VSS VSS AN7 AV46 VSS VSS D27
AJ25 VSS VSS AP10 AV49 VSS VSS D29
AJ27 VSS VSS AP17 AV51 VSS VSS D30
AJ29 VSS VSS AP20 AV55 VSS VSS D31
VSS VSS VSS 15 OF 19 Rev1p2 VSS
HASWELL-MCP-E-ULT_BGA1168
@
14 OF 19 Rev1p2
HASWELL-MCP-E-ULT_BGA1168
@
A A
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D D
HASWELL_MCP_E
U1R
HASWELL_MCP_E
U1Q
T51 @ AT2 N23 @ T64
T52 @ AU44 RSVD RSVD R23 @ T65
DC_TEST_AY2_AW2 AY2 A3 DC_TEST_A3_B3 T53 @ AV44 RSVD RSVD T23 @ T66
DC_TEST_AY3_AW3 AY3 DAISY_CHAIN_NCTF_AY2 DAISY_CHAIN_NCTF_A3 A4 @ T58 T54 @ D15 RSVD RSVD U10 @ T67
T49 @ AY60 DAISY_CHAIN_NCTF_AY3 DAISY_CHAIN_NCTF_A4 RSVD RSVD
DC_TEST_AY61_AW61 AY61 DAISY_CHAIN_NCTF_AY60 A60 @ T59
DC_TEST_AY62_AW62 AY62 DAISY_CHAIN_NCTF_AY61 DAISY_CHAIN_NCTF_A60 A61 DC_TEST_A61_B61 T55 @ F22 AL1 @ T68
T50 @ B2 DAISY_CHAIN_NCTF_AY62 DAISY_CHAIN_NCTF_A61 A62 @ T60 T56 @ H22 RSVD RSVD AM11 @ T69
DC_TEST_A3_B3 B3 DAISY_CHAIN_NCTF_B2 DAISY_CHAIN_NCTF_A62 AV1 @ T61 T57 @ J21 RSVD RSVD AP7 @ T70
DC_TEST_A61_B61 B61 DAISY_CHAIN_NCTF_B3 DAISY_CHAIN_NCTF_AV1 AW1 @ T62 RSVD RSVD AU10 @ T71
DC_TEST_B62_B63 B62 DAISY_CHAIN_NCTF_B61 DAISY_CHAIN_NCTF_AW1 AW2 DC_TEST_AY2_AW2 RSVD AU15 @ T72
B63 DAISY_CHAIN_NCTF_B62 DAISY_CHAIN_NCTF_AW2 AW3 DC_TEST_AY3_AW3 RSVD AW14 @ T73
DC_TEST_C1_C2 C1 DAISY_CHAIN_NCTF_B63 DAISY_CHAIN_NCTF_AW3 AW61 DC_TEST_AY61_AW61 RSVD AY14 @ T74
C2 DAISY_CHAIN_NCTF_C1 DAISY_CHAIN_NCTF_AW61 AW62 DC_TEST_AY62_AW62 RSVD
DAISY_CHAIN_NCTF_C2 DAISY_CHAIN_NCTF_AW62 AW63 @ T63
17 OF 19 Rev1p2 DAISY_CHAIN_NCTF_AW63 18 OF 19 Rev1p2
HASWELL-MCP-E-ULT_BGA1168 HASWELL-MCP-E-ULT_BGA1168
@ @
U1S HASWELL_MCP_E
C C
T104 @ CFG0 AC60 AV63 @ T75
T107 @ CFG1 AC62 CFG0
CFG1
RSVD_TP
RSVD_TP
AU63 @ T76 CFG Straps for Processor
T108 @ CFG2 AC63
T166 @ CFG3 AA63 CFG2
T167 @ CFG4 AA60 CFG3 C63 @ T77
T168 @ CFG5 Y62 CFG4 RSVD_TP C62 @ T78
T169 @ CFG6 Y61 CFG5 RSVD_TP B43 @ T79 CFG3
T170 @ CFG7 Y60 CFG6 RSVD
1
T171 @ CFG8 V62 CFG7 A51 @ T80
T172 @ CFG9 V61 CFG8 RSVD_TP B51 @ T81 R224
T182 @ CFG10 V60 CFG9 RSVD_TP 1K_0402_5%
T181 @ CFG11 U60 CFG10 L60 @ T82 @
T180 @ CFG12 T63 CFG11 RESERVED RSVD_TP
2
T179 @ CFG13 T62 CFG12 N60 @ T83
T178 @ CFG14 T61 CFG13 RSVD
T177 @ CFG15 T60 CFG14 W23 @ T84
CFG15 RSVD Y22 @ T85
T176 @ CFG16 AA62 RSVD AY15 OPI_COMP
T175 @ CFG18 U63 CFG16 PROC_OPI_RCOMP
T174 @ CFG17 AA61 CFG18 AV62 @ T86
CFG17 RSVD Physical Debug Enable (DFX Privacy)
T173 @ CFG19 U62 D58 @ T87
CFG19 RSVD
CFG_RCOMP V63 P22
CFG_RCOMP VSS 1: DISABLED
N21 CFG3
T90 @ A5 VSS
RSVD
0: ENABLED; SET DFX ENABLED BIT
P20 @ T88 IN DEBUG INTERFACE MSR
T91 @ E1 RSVD R20 @ T89
T92 @ D1 RSVD RSVD
T93 @ J20 RSVD
T94 @ H18 RSVD CFG4
TD_IREF B12 RSVD
1
TD_IREF
B 19 OF 19 Rev1p2 R225 B
HASWELL-MCP-E-ULT_BGA1168 1K_0402_5%
@
2
2 1 CFG_RCOMP
R222 49.9_0402_1%
2 1 OPI_COMP
R223 49.9_0402_1% Display Port Presence Strap
2 1 TD_IREF
R226 8.2K_0402_5%
1 : Disabled; No Physical Display Port
CFG4 at t ac hed t o E mbedded Dis pl ay Port
A A
+1.35V
www.laptopblue.vn
+1.35V
JDIMM1
+1.35V +1.35V
1
+V_DDR_REFA 1 2
VREF_DQ VSS1 DDR_A_D9 +5VALW +5VS
0.1U_0402_16V4Z
3 4
DDR_A_D13 VSS2 DQ4 DDR_A_D12
C34
R54 5 6 1
R293 1.8K_0402_1% DDR_A_D8 7 DQ0 DQ5 8 @
2_0402_1% 9 DQ1 VSS3 10 DDR_A_DQS#1 R187 1 2 SA_ODT0
2
1 2 11 VSS4 DQS#0 12 DDR_A_DQS1 66.5_0402_1%
<5> SA_DIMM_VREFDQ DM0 DQS0 2
2.2U_0402_6.3V6M
1 13 14
2
@ DDR_A_D14 15 VSS5 VSS6 16 DDR_A_D15
1 1 DDR_A_D10 DQ2 DQ6 DDR_A_D11 SA_ODT1
+1.35V
C105
0.1U_0402_16V4Z
C106
C158 @ 17 18 R186 R191 R188 1 2
0.022U_0402_25V7K R185 19 DQ3 DQ7 20 U45 66.5_0402_1%
100K_0402_5% 100K_0402_5%
2 1.8K_0402_1% DDR_A_D29 21 VSS7 VSS8 22 DDR_A_D25 1 5 Q18
@
1
2 2 DDR_A_D28 23 DQ8 DQ12 24 DDR_A_D24 NC VCC LBSS138LT1G_SOT-23-3
1
25 DQ9 DQ13 26 2 D
R189 1 2 SB_ODT0
1 DDR_A_DQS#3 VSS9 VSS10 <4> DDR_PG_CTRL A SB_ODT0 <16> 1
R176 27 28 4 2 66.5_0402_1%
24.9_0402_1% DDR_A_DQS3 29 DQS#1 DM1 30 DIMM_DRAMRST# 3 Y G
DQS1 RESET# DIMM_DRAMRST# <4,16> GND
@ 31 32 S
2
3
DDR_A_D30 33 VSS11 VSS12 34 DDR_A_D27 74AUP1G07GW_TSSOP5 M_A_B_DIMM_ODT R190 1 2 SB_ODT1
DDR_A_D31 DQ10 DQ14 DDR_A_D26 SB_ODT1 <16>
35 36 66.5_0402_1%
37 DQ11 DQ15 38
DDR_A_D44 39 VSS13 VSS14 40 DDR_A_D45
DDR_A_D41 DQ16 DQ20 DDR_A_D40 DDR_VTT_PG_CTRL <45>
41 42
43 DQ17 DQ21 44
DDR_A_DQS#5 VSS15 VSS16 DDR_A_DQS#[0..7] <5>
45 46 1 1
DDR_A_DQS5 47 DQS#2 DM2 48
DQS2 VSS17 DDR_A_D42 DDR_A_DQS[0..7] <5> XEMC@ XEMC@
49 50
DDR_A_D43 51 VSS18 DQ22 52 DDR_A_D46 100P_0402_50V8J 100P_0402_50V8J
DDR_A_D47 DQ18 DQ23 DDR_A_D[0..63] <5> 2 2 C2145
53 54 C2144
55 DQ19 VSS19 56 DDR_A_D52 PVT modify 12/31
All VREF traces should DDR_A_D51 VSS20 DQ28 DDR_A_D53 DDR_A_MA[0..15] <5> EMI add C2144
Layout Note: have 10 mil trace width 57 58
DDR_A_D50 59 DQ24 DQ29 60 EMI reserved C2145
Place near JDIMM1 DQ25 VSS21 DDR_A_DQS#6
61 62
+1.35V 63 VSS22 DQS#3 64 DDR_A_DQS6
A5WAH PVT: ESD request add 65 DM3 DQS3 66
EMC@ DDR_A_D49 67 VSS23 VSS24 68 DDR_A_D54
DDR_A_D48 69 DQ26 DQ30 70 DDR_A_D55
DQ27 DQ31
1U_0402_6.3V6K
C107
1U_0402_6.3V6K
C108
1U_0402_6.3V6K
C109
1U_0402_6.3V6K
C110
71 72
VSS25 VSS26
1 1 1 1
@
DDRA_CKE0_DIMMA 73 74 DDRA_CKE1_DIMMA
2 2 2 2 <5> DDRA_CKE0_DIMMA CKE0 CKE1 DDRA_CKE1_DIMMA <5>
75 76
77 VDD1 VDD2 78 DDR_A_MA15
DDR_A_BS2 79 NC1 A15 80 DDR_A_MA14
<5> DDR_A_BS2 BA2 A14
81 82
DDR_A_MA12 83 VDD3 VDD4 84 DDR_A_MA11
DDR_A_MA9 85 A12/BC# A11 86 DDR_A_MA7
2 87 A9 A7 88 2
+1.35V DDR_A_MA8 89 VDD5 VDD6 90 DDR_A_MA6
DDR_A_MA5 91 A8 A6 92 DDR_A_MA4
93 A5 A4 94
DDR_A_MA3 95 VDD7 VDD8 96 DDR_A_MA2
DDR_A_MA1 A3 A2 DDR_A_MA0
10U_0603_6.3V6M
C111
10U_0603_6.3V6M
C112
10U_0603_6.3V6M
C113
10U_0603_6.3V6M
C114
97 98
99 A1 A0 100
1 1 1 1 SA_CLK_DDR0 VDD9 VDD10 SA_CLK_DDR1
<5> SA_CLK_DDR0 101 102 SA_CLK_DDR1 <5>
@ SA_CLK_DDR#0 103 CK0 CK1 104 SA_CLK_DDR#1
<5> SA_CLK_DDR#0 CK0# CK1# SA_CLK_DDR#1 <5>
105 106
2 2 2 2 DDR_A_MA10 107 VDD11 VDD12 108 DDR_A_BS1
DDR_A_BS0 A10/AP BA1 DDR_A_RAS# DDR_A_BS1 <5> +1.35V
<5> DDR_A_BS0 109 110 DDR_A_RAS# <5>
111 BA0 RAS# 112
DDR_A_WE# 113 VDD13 VDD14 114 DDRA_CS0_DIMMA#
<5> DDR_A_WE# DDRA_CS0_DIMMA# <5>
1
DDR_A_CAS# 115 WE# S0# 116 SA_ODT0
<5> DDR_A_CAS# CAS# ODT0
117 118 R56
DDR_A_MA13 119 VDD15 VDD16 120 SA_ODT1 1.8K_0402_1%
DDRA_CS1_DIMMA# 121 A13 ODT1 122
+1.35V <5> DDRA_CS1_DIMMA# S1# NC2
123 124 R296
2
125 VDD17 VDD18 126 +VREF_CA 1 2
NCTEST VREF_CA SM_DIMM_VREFCA <5>
127 128 2_0402_1% 1
1
EMC@ EMC@ DDR_A_D0 129 VSS27 VSS28 130 DDR_A_D5 @
DDR_A_D1 DQ32 DQ36 DDR_A_D4
10U_0603_6.3V6M
C115
10U_0603_6.3V6M
C116
10U_0603_6.3V6M
C117
10U_0603_6.3V6M
C161
2.2U_0402_6.3V6M
0.1U_0402_16V4Z
1 131 132 C162
@ 133 DQ33 DQ37 134 R295 0.022U_0402_25V7K
1 1 1 1 DDR_A_DQS#0 VSS29 VSS30 1 1
2
C119
C120
@ + C118 135 136 @ 1.8K_0402_1%
1
330U_2.5V_M DDR_A_DQS0 137 DQS#4 DM4 138
2
139 DQS4 VSS31 140 DDR_A_D3
2 2 2 2 2 DDR_A_D2 141 VSS32 DQ38 142 DDR_A_D7 2 2 @ R294
SF000006S00 DDR_A_D6 143 DQ34 DQ39 144 24.9_0402_1%
330U 2.5V H4.2 145 DQ35 VSS33 146 DDR_A_D18
2
17mohm OSCON DDR_A_D21 147 VSS34 DQ44 148 DDR_A_D19
DDR_A_D20 149 DQ40 DQ45 150
151 DQ41 VSS35 152 DDR_A_DQS#2
3 153 VSS36 DQS#5 154 DDR_A_DQS2 3
155 DM5 DQS5 156
DDR_A_D17 157 VSS37 VSS38 158 DDR_A_D22
DDR_A_D16 159 DQ42 DQ46 160 DDR_A_D23
+0.675VS DQ43 DQ47 +VREF_CA <16>
161 162
DDR_A_D36 163 VSS39 VSS40 164 DDR_A_D37
DDR_A_D33 165 DQ48 DQ52 166 DDR_A_D32
167 DQ49 DQ53 168
DDR_A_DQS#4 VSS41 VSS42
1U_0402_6.3V6K
C121
1U_0402_6.3V6K
C122
1U_0402_6.3V6K
C123
1U_0402_6.3V6K
C124
169 170
DDR_A_DQS4 171 DQS#6 DM6 172
1 1 1 1 DQS6 VSS43 DDR_A_D35
@ @ 173 174
DDR_A_D34 175 VSS44 DQ54 176 DDR_A_D39
DDR_A_D38 177 DQ50 DQ55 178
2 2 2 2 179 DQ51 VSS45 180 DDR_A_D63
DDR_A_D62 181 VSS46 DQ60 182 DDR_A_D59
DDR_A_D58 183 DQ56 DQ61 184
185 DQ57 VSS47 186 DDR_A_DQS#7
187 VSS48 DQS#7 188 DDR_A_DQS7
189 DM7 DQS7 190
DDR_A_D60 191 VSS49 VSS50 192 DDR_A_D56
DDR_A_D61 193 DQ58 DQ62 194 DDR_A_D57
Layout Note: DQ59 DQ63
Place near JDIMM1.203,204 195 196
197 VSS51 VSS52 198
199 SA0 EVENT# 200 D_CK_SDATA
+3VS VDDSPD SDA D_CK_SCLK D_CK_SDATA <7,16,39>
201 202
SA1 SCL D_CK_SCLK <7,16,39>
+0.675VS 203 204 +0.675VS
VTT1 VTT2
10P_0402_50V8J
205 206
2
G1 G2
1 1
Channel A
0.1U_0402_16V4Z
C125
C126
0_0402_5%
R211
0_0402_5%
R212
@ @ LCN_DAN06-K4406-0100
2 2
SP07000N300
1
CONN@
4 4
EMC@
<Address: SA1:SA0=00>
DIMM_1 H:4mm
DIS for Standard type Security Classification Compal Secret Data Compal Electronics, Inc.
UMA for Reverse type Issued Date 2013/10/01 Deciphered Date 2014/05/24 Title
DDRIII DIMMA
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A5WAH M/B LA-B991P
Date: Friday, October 17, 2014 Sheet 15 of 54
A B C D E
A B C D E
+1.35V
www.laptopblue.vn
+1.35V
JDIMM2
+1.35V
DDR_B_DQS#[0..7] <5>
1
+V_DDR_REFB 1 2
3 VREF_DQ VSS1 4 DDR_B_D12
DDR_B_D8 VSS2 DQ4 DDR_B_D9 DDR_B_DQS[0..7] <5>
R57 5 6
R297 1.8K_0402_1% DDR_B_D14 7 DQ0 DQ5 8
DQ1 VSS3 DDR_B_DQS#1 DDR_B_D[0..63] <5>
2_0402_1% 9 10
2
1 2 11 VSS4 DQS#0 12 DDR_B_DQS1
<5> SB_DIMM_VREFDQ DM0 DQS0 DDR_B_MA[0..15] <5>
2.2U_0402_6.3V6M
1 13 14
1
@ DDR_B_D10 15 VSS5 VSS6 16 DDR_B_D13
1 1 DDR_B_D11 DQ2 DQ6 DDR_B_D15
C127
0.1U_0402_16V4Z
C128
C159 @ 17 18
0.022U_0402_25V7K R213 19 DQ3 DQ7 20
2 1.8K_0402_1% DDR_B_D28 21 VSS7 VSS8 22 DDR_B_D25
1
2 2 DDR_B_D29 23 DQ8 DQ12 24 DDR_B_D24
2
25 DQ9 DQ13 26
1 DDR_B_DQS#3 VSS9 VSS10 1
R179 27 28
24.9_0402_1% DDR_B_DQS3 29 DQS#1 DM1 30 DIMM_DRAMRST#
DQS1 RESET# DIMM_DRAMRST# <4,15>
@ 31 32
2
DDR_B_D26 33 VSS11 VSS12 34 DDR_B_D30
DDR_B_D27 35 DQ10 DQ14 36 DDR_B_D31
37 DQ11 DQ15 38
DDR_B_D40 39 VSS13 VSS14 40 DDR_B_D45
DDR_B_D41 41 DQ16 DQ20 42 DDR_B_D44
43 DQ17 DQ21 44
DDR_B_DQS#5 45 VSS15 VSS16 46
DDR_B_DQS5 47 DQS#2 DM2 48
49 DQS2 VSS17 50 DDR_B_D47
DDR_B_D46 51 VSS18 DQ22 52 DDR_B_D43
DDR_B_D42 53 DQ18 DQ23 54
55 DQ19 VSS19 56 DDR_B_D61
All VREF traces should DDR_B_D56 VSS20 DQ28 DDR_B_D60
Layout Note: have 10 mil trace width 57 58
DDR_B_D57 59 DQ24 DQ29 60
Place near JDIMM2 DQ25 VSS21 DDR_B_DQS#7
61 62
+1.35V 63 VSS22 DQS#3 64 DDR_B_DQS7
65 DM3 DQS3 66
DDR_B_D59 67 VSS23 VSS24 68 DDR_B_D63
DDR_B_D58 69 DQ26 DQ30 70 DDR_B_D62
DQ27 DQ31
1U_0402_6.3V6K
C129
1U_0402_6.3V6K
C130
1U_0402_6.3V6K
C131
1U_0402_6.3V6K
C132
71 72
VSS25 VSS26
1 1 1 1
@ @
DDRB_CKE0_DIMMB 73 74 DDRB_CKE1_DIMMB
2 2 2 2 <5> DDRB_CKE0_DIMMB CKE0 CKE1 DDRB_CKE1_DIMMB <5>
75 76
77 VDD1 VDD2 78 DDR_B_MA15
DDR_B_BS2 79 NC1 A15 80 DDR_B_MA14
<5> DDR_B_BS2 BA2 A14
81 82
DDR_B_MA12 83 VDD3 VDD4 84 DDR_B_MA11
DDR_B_MA9 85 A12/BC# A11 86 DDR_B_MA7
2 87 A9 A7 88 2
+1.35V DDR_B_MA8 89 VDD5 VDD6 90 DDR_B_MA6
DDR_B_MA5 91 A8 A6 92 DDR_B_MA4
93 A5 A4 94
DDR_B_MA3 95 VDD7 VDD8 96 DDR_B_MA2
DDR_B_MA1 A3 A2 DDR_B_MA0
10U_0603_6.3V6M
C133
10U_0603_6.3V6M
C134
10U_0603_6.3V6M
C135
10U_0603_6.3V6M
C136
97 98
99 A1 A0 100
1 1 1 1 SB_CLK_DDR0 VDD9 VDD10 SB_CLK_DDR1
<5> SB_CLK_DDR0 101 102 SB_CLK_DDR1 <5>
SB_CLK_DDR#0 103 CK0 CK1 104 SB_CLK_DDR#1
<5> SB_CLK_DDR#0 CK0# CK1# SB_CLK_DDR#1 <5>
105 106
2 2 2 2 DDR_B_MA10 107 VDD11 VDD12 108 DDR_B_BS1
DDR_B_BS0 A10/AP BA1 DDR_B_RAS# DDR_B_BS1 <5>
<5> DDR_B_BS0 109 110 DDR_B_RAS# <5>
111 BA0 RAS# 112
DDR_B_WE# 113 VDD13 VDD14 114 DDRB_CS0_DIMMB#
<5> DDR_B_WE# DDR_B_CAS# WE# S0# SB_ODT0 DDRB_CS0_DIMMB# <5>
<5> DDR_B_CAS# 115 116 SB_ODT0 <15>
117 CAS# ODT0 118
DDR_B_MA13 119 VDD15 VDD16 120 SB_ODT1
DDRB_CS1_DIMMB# A13 ODT1 SB_ODT1 <15>
<5> DDRB_CS1_DIMMB# 121 122
+1.35V 123 S1# NC2 124
125 VDD17 VDD18 126 +VREF_CA
NCTEST VREF_CA +VREF_CA <15>
127 128
DDR_B_D4 129 VSS27 VSS28 130 DDR_B_D5
DDR_B_D1 DQ32 DQ36 DDR_B_D0
10U_0603_6.3V6M
C137
10U_0603_6.3V6M
C138
10U_0603_6.3V6M
C139
2.2U_0402_6.3V6M
131 132
133 DQ33 DQ37 134
1 1 1 DDR_B_DQS#0 VSS29 VSS30 1 1
C141
0.1U_0402_16V4Z
C142
135 136 @
DDR_B_DQS0 137 DQS#4 DM4 138
@ 139 DQS4 VSS31 140 DDR_B_D2
2 2 2 DDR_B_D3 141 VSS32 DQ38 142 DDR_B_D6 2 2
DDR_B_D7 143 DQ34 DQ39 144
145 DQ35 VSS33 146 DDR_B_D16
DDR_B_D21 147 VSS34 DQ44 148 DDR_B_D17
DDR_B_D20 149 DQ40 DQ45 150
151 DQ41 VSS35 152 DDR_B_DQS#2
3 153 VSS36 DQS#5 154 DDR_B_DQS2 3
155 DM5 DQS5 156
DDR_B_D22 157 VSS37 VSS38 158 DDR_B_D19
DDR_B_D23 159 DQ42 DQ46 160 DDR_B_D18
+0.675VS 161 DQ43 DQ47 162
DDR_B_D36 163 VSS39 VSS40 164 DDR_B_D37
DDR_B_D33 165 DQ48 DQ52 166 DDR_B_D32
167 DQ49 DQ53 168
DDR_B_DQS#4 VSS41 VSS42
1U_0402_6.3V6K
C143
1U_0402_6.3V6K
C144
1U_0402_6.3V6K
C145
1U_0402_6.3V6K
C146
169 170
DDR_B_DQS4 171 DQS#6 DM6 172
1 1 1 1 DQS6 VSS43 DDR_B_D34
@ @ 173 174
DDR_B_D35 175 VSS44 DQ54 176 DDR_B_D38
DDR_B_D39 177 DQ50 DQ55 178
2 2 2 2 179 DQ51 VSS45 180 DDR_B_D51
DDR_B_D52 181 VSS46 DQ60 182 DDR_B_D55
+3VS DDR_B_D49 183 DQ56 DQ61 184
185 DQ57 VSS47 186 DDR_B_DQS#6
187 VSS48 DQS#7 188 DDR_B_DQS6
2
205 206
2
G1 G2
1 1
Channel B
0.1U_0402_16V4Z
C147
C148
0_0402_5%
R231
@ LCN_DAN06-K4406-0100
2 2
SP07000N300
1
CONN@
4 4
EMC@
<Address: SA1:SA0=10>
DIMM_2 H:4mm
DIS for Standard type Security Classification Compal Secret Data Compal Electronics, Inc.
UMA for Reverse type Issued Date 2013/10/01 Deciphered Date 2014/05/24 Title
DDRIII DIMMB
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A5WAH M/B LA-B991P
Date: Friday, October 17, 2014 Sheet 16 of 54
A B C D E
A B C D E
UGPU1Awww.laptopblue.vn
Part 1 of 6 +3VSDGPU_AON
GPIO I/O USAGE
GPIO
AF13 NC GPIO13 B3 PSI <51> D2000 DGPU_AC_DETECT <9,36> 3VSDGPU_MAIN_EN 7 2
AE13 NC GPIO14 C3 GPU_PEX_RST_HOLD# 6 3
GPIO5 O 3V3_MAIN_EN
RB751V-40_SOD323-2
AE15 NC GPIO15 D5 VGA@ GC6_FB_EN 5 4
AF15 NC GPIO16 D4
AG15 NC GPIO17 C2 GC6@
GPIO6 I GPU_EVENT#
AG16 NC GPIO18 F7
AF16 NC GPIO19 E6
AE16 NC GPIO20 C4 GPU_PEX_RST_HOLD# GPIO7 O 3D Vision
AE18 NC GPIO21 +3VSDGPU_AON
AF18 NC AB6
AG18 NC PEX_WAKE_NC GPIO8 I SYS_PEX_RST_MON#
AG19 NC SYS_PEX_RST_MON# 2 R2056 1 10K_0402_5%
AF19 NC @
AE19 NC I2CS_SDA 1 VGA@ 21.8K_0402_5%
GPIO9 I/O ALERT
AE21 NC AG3 R2000
AF21 NC NC AF4 I2CS_SCL 1 VGA@ 21.8K_0402_5%
AG21 NC NC AF3 R2001
GPIO10 O MEM_VREF_CTL
AG22 NC NC
NC PSI 2 VGA@ 1 10K_0402_5%
R2052 GPIO11 O PWM_VID
<10> PEG_GTX_HRX_P0 AC9 AE3
PEX_TX0 NC
DACs
<10> PEG_GTX_HRX_N0 AB9 AE4
AB10 PEX_TX0_N NC
<10> PEG_GTX_HRX_P1 PEX_TX1
<10> PEG_GTX_HRX_N1 AC10 GPIO12 I PWR_LEVEL
PEX_TX1_N
PCI EXPRESS
<10> PEG_GTX_HRX_P2 AD11
AC11 PEX_TX2 W5 PLTRST_VGA#
<10> PEG_GTX_HRX_N2 PEX_TX2_N NC
<10> PEG_GTX_HRX_P3 AC12 AE2 GPIO13 O PSI
AB12 PEX_TX3 TSEN_VREF AF2
<10> PEG_GTX_HRX_N3 PEX_TX3_N NC
AB13
2
AC13 NC
2 AD14 NC GPIO14 I HPD_A 2
AC14 NC GPIO8_OVERT 1 6
NC GPU_OVERT <36>
AC15 VGA@ GPIO15 I HPD_C
AB15 NC DMN66D0LDW-7_SOT363-6
AB16 NC B7 R2003 1 VGA@ 2 1.8K_0402_5%
NC I2CA_SCL Q2000A
AC16 A7 R2004 1 VGA@ 2 1.8K_0402_5% GPIO16 RESERVED
AD17 NC I2CA_SDA
AC17 NC C9 R2005 1 VGA@ 2 1.8K_0402_5% GPIO9_ALERT_GATE
AC18 NC I2CB_SCL C8 R2006 1 VGA@ 2 1.8K_0402_5%
NC I2CB_SDA GPIO17 I HPD_D
I2C
AB18
5
AB19 NC A9 R2007 1 VGA@ 2 1.8K_0402_5%
AC19 NC I2CC_SCL B9 R2008 1 VGA@ 2 1.8K_0402_5%
AD20 NC I2CC_SDA GPIO9_ALERT 4 3
GPIO18 I HPD_E
NC I2CS_SCL GPU_ALERT <36>
AC20 D9 VGA@
AC21 NC I2CS_SCL D8 I2CS_SDA DMN66D0LDW-7_SOT363-6
AB21 NC I2CS_SDA GPIO19 I HPD_F or HPD_B
Q2000B
AD23 NC
AE23 NC Place Under L6
AF24 NC VGA@
GPIO20 Reserved
AE24 NC L6 +PLLVDD 1 2
AG24 NC PLLVDD M6 C2000 0.1U_0402_16V4Z
AG25 NC SP_PLLVDD GPIO21 O GPU_PEX_RST_HOLD#
NC N6 VGA@ +3VSDGPU_AON
NC +GPU_PLLVDD 1 2
C2001
GPIO22
2
+3VSDGPU_AON 1 VGA@ 2 AE8 0.1U_0402_16V4Z
<7> CLK_PEG_VGA PEX_REFCLK
R2009 10K_0402_5% AD8 GPIO23
PEG_CLKREQ# <7> CLK_PEG_VGA# PEX_REFCLK_N I2CS_SCL
AC6 Place Under M6 1 6
<7> PEG_CLKREQ# PEX_CLKREQ_N EC_SMB_CK2 <7,36>
VGA@
PEX_TSTCLK_OUT+ AF22 DMN66D0LDW-7_SOT363-6
CLK
5
2 VGA@ 1 PEX_TREMP AF25 PEX_RST_N XTAL_SSIN C10 XTAL_OUTBUFF
R2013 1 VGA@ 2 10K_0402_5%
R2011 2.49K_0402_1% PEX_TERMP XTAL_OUTBUFF
I2CS_SDA 4 3
EC_SMB_DA2 <7,36>
GM108-ES-S-A1_FCBGA595 VGA@
DMN66D0LDW-7_SOT363-6
@ Q2001B
10P_0402_50V8J
10P_0402_50V8J
0.1Ux1, 22Ux1 1 1
GC6@ R2014 22U_0603_6.3V6M VGA@ VGA@ X2000 VGA@
10K_0402_5%
33ohm(ESR0.05)x1 2 4 2
R2016 GC6@ Near GPU C2004 C2005
1 NGC6@ 2 2 2
<40,51> VGA_PWROK
2
1
G
A 4.7U_0603_6.3V6K 22U_0603_6.3V6M
4 4
+3VSDGPU_AON R2019 R2017 2 2
3
R2055
D2002 10K_0402_5%
SYS_PEX_RST_MON# 2 GC6@
Security Classification Compal Secret Data Compal Electronics, Inc.
2
1 PLTRST_VGA#
RP33
CMDA12 1 8
2 7
CMDA14 3 6 +1.5VSDGPU +1.5VSDGPU
N15V-GM 4 5
VGM@ UGPU1B 2 2
SA00007BR20 100_0804_8P4R_5% C2084 C2083
1 1
VGA@ @ @
MDA[15..0] RP42 0.1U_0402_16V4Z 0.1U_0402_16V4Z
<22,23> MDA[15..0] 1 1
UGPU1 Part 2 of 6 CMDA22 1 8
MDA[31..16] CMDA[31..0] <22,23,24,25>
2 7
<22,23> MDA[31..16]
MDA0 E18 C27 CMDA0 CMDA21 3 6
MDA[47..32] MDA1 F18 FBA_D00 FBA_CMD0 C26 CMDA1 4 5 +1.5VSDGPU +1.5VSDGPU
<24,25> MDA[47..32] FBA_D01 FBA_CMD1
MDA2 E16 E24 CMDA2
MDA[63..48] MDA3 F17 FBA_D02 FBA_CMD2 F24 CMDA3 100_0804_8P4R_5%
<24,25> MDA[63..48] FBA_D03 FBA_CMD3 2 2
N15V-GT MDA4 D20 D27 CMDA4 VGA@ C2086 C2085
SGT@ MDA5 D21 FBA_D04 FBA_CMD4 D26 CMDA5 RP43 @ @
MDA6 F20 FBA_D05 FBA_CMD5 F25 CMDA6 CMDA5 1 8 0.1U_0402_16V4Z 0.1U_0402_16V4Z
SA00007GJ10 FBA_D06 FBA_CMD6
MDA7 E21 F26 CMDA7 2 7 1 1
MDA8 E15 FBA_D07 FBA_CMD7 F23 CMDA8 CMDA8 3 6
UGPU1 MDA9 D15 FBA_D08 FBA_CMD8 G22 CMDA9 4 5
MDA10 F15 FBA_D09 FBA_CMD9 G23 CMDA10 +1.5VSDGPU +1.5VSDGPU
MDA11 F13 FBA_D10 FBA_CMD10 G24 CMDA11 100_0804_8P4R_5%
MDA12 C13 FBA_D11 FBA_CMD11 F27 CMDA12
FBA_D12 FBA_CMD12 VGA@ 2 2
MDA13 B13 G25 CMDA13 RP44 C2088 C2087
MDA14 E13 FBA_D13 FBA_CMD13 G27 CMDA14 CMDA26 1 8 @ @
N15V-GL MDA15 D13 FBA_D14 FBA_CMD14 G26 CMDA15 2 7 0.1U_0402_16V4Z 0.1U_0402_16V4Z
VGL@ MDA16 B15 FBA_D15 FBA_CMD15 M24 CMDA16 CMDA23 3 6 1 1
MDA17 C16 FBA_D16 FBA_CMD16 M23 CMDA17 4 5
SA00007OO10 FBA_D17 FBA_CMD17
MDA18 A13 K24 CMDA18
MDA19 A15 FBA_D18 FBA_CMD18 K23 CMDA19 100_0804_8P4R_5%
MDA20 B18 FBA_D19 FBA_CMD19 M27 CMDA20
FBA_D20 FBA_CMD20 VGA@
MDA21 A18 M26 CMDA21 RP45
MDA22 A19 FBA_D21 FBA_CMD21 M25 CMDA22 CMDA4 1 8
MDA23 C19 FBA_D22 FBA_CMD22 K26 CMDA23 2 7
MDA24 B24 FBA_D23 FBA_CMD23 K22 CMDA24 CMDA10 3 6
MDA25 C23 FBA_D24 FBA_CMD24 J23 CMDA25 4 5
MDA26 A25 FBA_D25 FBA_CMD25 J25 CMDA26
MDA27 A24 FBA_D26 FBA_CMD26 J24 CMDA27 100_0804_8P4R_5%
MDA28 A21 FBA_D27 FBA_CMD27 K27 CMDA28 PVT modify 01/13
2 FBA_D28 FBA_CMD28 DQSA, DQSA# reverse VGA@ 2
MDA29 B21 K25 CMDA29 RP46
MDA30 C20 FBA_D29 FBA_CMD29 J27 CMDA30 CMDA24 1 8
MDA31 C21 FBA_D30 FBA_CMD30 J26 CMDA31 2 7
MDA32 R22 FBA_D31 FBA_CMD31 CMDA13 3 6 +1.5VSDGPU +1.5VSDGPU
FBA_D32 DQMA[3..0] <22,23>
MDA33 R24 D19 DQMA0 4 5
FBA_D33 FBA_DQM0
INTERFACE A
MDA34 T22 D14 DQMA1 2 2
MDA35 R23 FBA_D34 FBA_DQM1 C17 DQMA2 100_0804_8P4R_5% C2089 C2090
MDA36 N25 FBA_D35 FBA_DQM2 C22 DQMA3 @ @
FBA_D36 FBA_DQM3 DQMA[7..4] <24,25> VGA@
MDA37 N26 P24 DQMA4 RP47 0.1U_0402_16V4Z 0.1U_0402_16V4Z
MEMORY
MDA38 N23 FBA_D37 FBA_DQM4 W24 DQMA5 CMDA9 1 8 1 1
MDA39 N24 FBA_D38 FBA_DQM5 AA25 DQMA6 2 7
MDA40 V23 FBA_D39 FBA_DQM6 U25 DQMA7 CMDA6 3 6
NV 15x DG-06803-V03 MDA41
MDA42
V22
T23
FBA_D40
FBA_D41
FBA_DQM7
F19 DQSA#0
DQSA#[3..0] <22,23>
4 5 +1.5VSDGPU +1.5VSDGPU
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
GM108-ES-S-A1_FCBGA595
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N15X VRAM 2/9
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A5WAH M/B LA-B991P
Date: Friday, October 17, 2014 Sheet 18 of 54
A B C D E
A B C D E
UGPU1C
www.laptopblue.vn
MULTI LEVEL STRAPS
Part 3 of 6 F11
AC3 NC AD10 +3VSDGPU_AON +3VSDGPU_MAIN
AC4 NC NC AD7
Y4 NC NC B19 strap0 strap1 strap2 strap3 strap4
Y3 NC FBA_CMD32 V5
1
AA3 NC NC V6
AA2 NC NC G1 R2029 R2030 R2031 R2032 R2033 R2035 R2036 R2037
AB1 NC NC G2 @ @ @ @ @ @ @ @
NC NC
NC
AA1 G3 45.3K_0402_1% 4.99K_0402_1% 20K_0402_1% 4.99K_0402_1% 10K_0402_1% 30K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
AA4 NC NC G4
2
AA5 NC NC G5
1 NC NC 1
G6
NC G7 STRAP0
AB5 NC V1 STRAP1 ROM_SI
AB4 NC NC V2 STRAP2 ROM_SO
AB3 NC NC W1 STRAP3 ROM_SCLK
AB2 NC NC W2 STRAP4
AD3 NC NC W3
AD2 NC NC W4
1
AE1 NC NC
AD1 NC R2038 R2039 R2040 R2041 R2042 R2044 R2045 R2046
AD4 NC @ @ @ @ @ @ @ @
NC For GC62.0 use
AD5 D11 R2050 1 @ 2 10K_0402_5% N14x for CEC ,NC 4.99K_0402_1% 34.8K_0402_1% 15K_0402_1% 4.99K_0402_1% 10K_0402_1% 10K_0402_1% 10K_0402_1% 4.99K_0402_1%
NC BUFRST_N
N15x for GPIO8
2
D10
T2 NC
T3 NC E9 SYS_PEX_RST_MON#
NC GPIO8 SYS_PEX_RST_MON# <17>
T1
R1 NC E10
NC NC
GENERAL
R2
LVDS/TMDS
R3 NC F10
N2 NC NC
N3 NC
NC D1 STRAP0
STRAP0 D2 STRAP1
V3 STRAP1 E4 STRAP2
V4 NC STRAP2 E3 STRAP3
U3 NC STRAP3 D3 STRAP4
U4 NC STRAP4 C1
T4 NC NC
T5 NC
R4 NC F6 MULTI_STRAP_REF0_GND 1 SGT@ 2
R5 NC MULTI_STRAP_REF0_GND F4 R2051 40.2K_0402_1%
NC NC F5
2 NC 2
02/19 PreMP modify strap resistor for 1.35V VRAM
N1
M1 NC
M2 NC F12
M3 NC THERMDP For N15S-GT Binary strap table Decive ID : 0x1341
K2 NC E12 GPU X76 Freq Memory Size Memory Config strap0 strap1 strap2 strap3 strap4 ROM_SI ROM_SO ROM_SCLK
K3 NC THERMDN
K1 NC 0xA (SA000067550) Micron MT41J128M16JT-093G:K PU 15K
J1 NC
NC 1GHz 128Mx16x4 0xB (SA000068U90) Samsung K4W2G1646Q-BC1A PU 20K
J5
N4 NC For N15V-GL/GM Binary strap table Decive ID : 0x1140
N5 NC TEST GPU X76 Freq Memory Size Memory Config strap0 strap1 strap2 strap3 strap4 ROM_SI ROM_SO ROM_SCLK
NC
P3 AD9 TESTMODE R2054 1 VGA@ 2 10K_0402_5% X76550BOL03 0x1 (SA000067550) Micron MT41J128M16JT-093G:K PU 10K PD10K PD 10K PD 10K
P4 NC TESTMODE AE5 JTAG_TCK PAD @ T18
NC JTAG_TCK AE6 JTAG_TDI PAD @ T1 0x5 (SA000068U00) Samsung K4W2G1646E-BC1A PU 10K PD10K PU 10K PD 10K
JTAG_TDI AF6 JTAG_TDO PAD @ T186 1GHz 128Mx16x4
J2 JTAG_TDO AD6 JTAG_TMS PAD @ T3 0xC (SA00006H430) Hynix H5TC2G63FFR-11C PD 10K PD10K PU 10K PU 10K
NC JTAG_TMS JTAG_RST
X76550BOL08
J3 AG4 R2053 1 VGA@ 210K_0402_5% N15V-GL
NC JTAG_TRST_N 0xE (SA000068U90) Samsung K4W2G1646Q-BC1A PD 10K PU 10K PU 10K PU 10K PD 10K PD 10K PD 10K PD 10K
N15V-GM X76550BOL10
3 3
H3 X76550BOL12 0x9 (SA000076P20) Samsung K4W4G1646D-BC1A PU 10K PD10K PD 10K PU 10K
H4 NC
NC SERIAL X76550BOL14 2GHz 256Mx16x4 0xD (SA000077K20) Micron MT41J256M16HA-093G:E PU 10K PD10K PU 10K PU 10K
D12
ROM_CS_N B12 ROM_SI 0x4 (SA00006E840) Hynix H5TC4G63AFR-11C PD 10K PD10K PU 10K PD 10K
ROM_SI X76550BOL13
A12 ROM_SO
ROM_SO C12 ROM_SCLK
ROM_SCLK
GM108-ES-S-A1_FCBGA595
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N15X LVDS 3/9
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A5WAH M/B LA-B991P
Date: Friday, October 17, 2014 Sheet 19 of 54
A B C D E
A B C D E
www.laptopblue.vn
NV 15x DG-06803-V03
1 1
4.7U_0603_6.3V6K
C25 FBVDDQ_01 PEX_IOVDDQ_1 AA12
10U_0603_6.3V6M
22U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
VGA@ C2039 FBVDDQ_02 PEX_IOVDDQ_2
VGA@ C2040
VGA@ C2032
VGA@ C2033
VGA@ C2021
VGA@ C2022
VGA@ C2013
VGA@ C2014
VGA@ C2016
VGA@ C2017
1 1 1 1 2 2 E23 AA13 1 1 1 1
E26 FBVDDQ_03 PEX_IOVDDQ_3 AA16
F14 FBVDDQ_04 PEX_IOVDDQ_4 AA18
F21 FBVDDQ_05 PEX_IOVDDQ_5 AA19
2 2 2 2 1 1 G13 FBVDDQ_06 PEX_IOVDDQ_6 AA20 2 2 2 2
G14 FBVDDQ_07 PEX_IOVDDQ_7 AA21
G15 FBVDDQ_08 PEX_IOVDDQ_8 AB22
Under GPU G16 FBVDDQ_09 PEX_IOVDDQ_9 AC23
G18 FBVDDQ_10 PEX_IOVDDQ_10 AD24
G19 FBVDDQ_11 PEX_IOVDDQ_11 AE25
10U_0603_6.3V6M
FBVDDQ_12 PEX_IOVDDQ_12 Under GPU Near GPU
VGA@ C2045
VGA@ C2047
G20 AF26
22U_0603_6.3V6M
1 1 FBVDDQ_13 PEX_IOVDDQ_13 Midway GPU & Power supply
G21 AF27
H24 FBVDDQ_14 PEX_IOVDDQ_14
H26 FBVDDQ_AON
2 2 J21 FBVDDQ_AON AA22
K21 FBVDDQ_AON PEX_IOVDD_1 AB23
L22 FBVDDQ_AON PEX_IOVDD_2 AC24
L24 FBVDDQ_19 PEX_IOVDD_3 AD25
Near GPU
POWER
L26 FBVDDQ_20 PEX_IOVDD_4 AE26
M21 FBVDDQ_21 PEX_IOVDD_5 AE27
2 N21 FBVDDQ_22 PEX_IOVDD_6 2
R21 FBVDDQ_23
T21 FBVDDQ_24
V21 FBVDDQ_25 +3VSDGPU_AON
W21 FBVDDQ_26
FBVDDQ_27 G10
3V3_AON G12
1U_0402_6.3V6K
56mA
0.1U_0402_16V4Z
4.7U_0603_6.3V6K
3V3_AON
VGA@ C2048
VGA@ C2049
VGA@ C2050
G8 2 1 1
VDD33_3 G9
VDD33_4
V7 1 2 2
W7 NC +1.5VSDGPU
AA6 NC
W6 NC D22 FB_CAL_PD_VDDQ 1 VGA@ 2
NC FB_CAL_PD_VDDQ Under GPU Near GPU
Y6 40.2_0402_1% R2078 +3VSDGPU_MAIN
NC
C24 FB_CAL_PU_GND 1 VGA@ 2
FB_CAL_PU_GND 42.2_0402_1% R2079
1U_0402_6.3V6K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
4.7U_0603_6.3V6K
B25 FB_CAL_TERM_GND1 VGA@ 2
VGA@ C2051
VGA@ C2052
VGA@ C2053
VGA@ C2054
M7 2 2 1 1
N7 NC FB_CAL_TERM_GND 51.1_0402_1% R2080
T6 NC
P6 NC
NC 1 1 2 2
change to 1.35VSDGPU
T7 Under GPU Near GPU
R7 IFPD_PLLVDD_2 +3VSDGPU_AON
U6 NC
R6 IFPD_RSET AA8
286mA
NC PEX_PLL_HVDD_1 AA9
PEX_PLL_HVDD_2
0.1U_0402_16V4Z
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
AB8
VGA@ C2034
VGA@ C2035
VGA@ C2036
3 3
PEX_SVDD_3V3 2 1 1
J7
K7 NC 1 2 2
K6 NC AA14
H6 NC PEX_PLLVDD_1 AA15
J6 NC PEX_PLLVDD_2
NC Near GPU +1.05VSDGPU
130mA +PEX_PLLVDD 2 1
R2075 SGT@ 0_0603_5%
0.1U_0402_16V4Z
VGA@ C2041
VGA@ C2042
VGA@ C2043
1U_0402_6.3V6K
4.7U_0603_6.3V6K
2 1 1
GM108-ES-S-A1_FCBGA595
@ 1 2 2
R2075 R2075
BLM18PG121SN1D_0603 BLM18PG121SN1D_0603
VGL@ VGM@
4 SM01000BW00 SM01000BW00 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N15X POWER & GND 4/9
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A5WAH M/B LA-B991P
Date: Friday, October 17, 2014 Sheet 20 of 54
A B C D E
A B C D E
www.laptopblue.vn
UGPU1F
UGPU1E +VGA_CORE +VGA_CORE
Part 6 of 6
A2
A26 GND_001
Part 5 of 6
GND_057
K11
K13 K10 V18
NV 15x DG-06803-V03
AB11 GND_002 GND_058 K15 K12 VDD_001 VDD_041 V16
1 GND_003 GND_059 VDD_002 VDD_040 1
AB14 K17 K14 V14
AB17 GND_004 GND_060 L10 K16 VDD_003 VDD_039 V12
AB20 GND_005 GND_061 L12 K18 VDD_004 VDD_038 V10
AB24 GND_006 GND_062 L14 L11 VDD_005 VDD_037 U17
POWER
AC2 GND_007 GND_063 L16 L13 VDD_006 VDD_036 U15
AC22 GND_008 GND_064 L18 L15 VDD_007 VDD_035 U13
AC26 GND_009 GND_065 L2 L17 VDD_008 VDD_034 U11
AC5 GND_010 GND_066 L23 M10 VDD_009 VDD_033 T18
AC8 GND_011 GND_067 L25 M12 VDD_010 VDD_032 T16
AD12 GND_012 GND_068 L5 M14 VDD_011 VDD_031 T14
AD13 GND_013 GND_069 M11 M16 VDD_012 VDD_030 T12
AD15 GND_014 GND_070 M13 M18 VDD_013 VDD_029 T10
AD16 GND_015 GND_071 M15 N11 VDD_014 VDD_028 R17
AD18 GND_016 GND_072 M17 N13 VDD_015 VDD_027 R15
AD19 GND_017 GND_073 N10 N15 VDD_016 VDD_026 R13
AD21 GND_018 GND_074 N12 N17 VDD_017 VDD_025 R11
AD22
AE11
GND_019
GND_020
GND_075
GND_076
N14
N16
P10
P12
VDD_018
VDD_019
VDD_024
VDD_023
P18
P16
DA-06840-V03
AE14 GND_021 GND_077 N18 VDD_020 VDD_022 P14
AE17 GND_022 GND_078 P11 VDD_021
AE20 GND_023 GND_079 P13
AF1 GND_024 GND_080 P15
GND_025 GND_081
GND
AF11 P17
AF14 GND_026 GND_082 P2
AF17 GND_027 GND_083 P23
AF20 GND_028 GND_084 P26
AF23 GND_029 GND_085 P5
AF5 GND_030 GND_086 R10
AF8 GND_031 GND_087 R12 GM108-ES-S-A1_FCBGA595
AG2 GND_032 GND_088 R14
AG26 GND_033 GND_089 R16
GND_034 GND_090 @
B1 R18
B11 GND_035 GND_091 T11
2 B14 GND_036 GND_092 T13 2
B17 GND_037 GND_093 T15
B20 GND_038 GND_094 T17
B23 GND_039 GND_095 U10
B27 GND_040 GND_096 U12
B5
B8
GND_041
GND_042
GND_097
GND_098
U14
U16
DA-06925-V05
E11 GND_043 GND_099 U18
E14 GND_044 GND_100 U2
E17 GND_045 GND_101 U23
E2 GND_046 GND_102 U26
E20 GND_047 GND_103 U5
E22 GND_048 GND_104 V11
E25 GND_049 GND_105 V13
E5 GND_050 GND_106 V15
E8 GND_051 GND_107 V17
H2 GND_052 GND_108 Y2
H23 GND_053 GND_109 Y23
H25 GND_054 GND_110 Y26
H5 GND_055 GND_111 Y5
GND_056 GND_112
AA7
GND AB7
GND
GM108-ES-S-A1_FCBGA595
@ DA07075-V01
3 3
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N15X POWER & GND 5/9
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A5WAH M/B LA-B991P
Date: Friday, October 17, 2014 Sheet 21 of 54
A B C D E
A B C D E
<18,23,24,25>
DQSA[7..0]
DQSA#[7..0]
DQSA[7..0]
DQSA#[7..0]
www.laptopblue.vn
DQMA[7..0]
<18,23,24,25> DQMA[7..0]
MDA[63..0]
<18,23,24,25> MDA[63..0]
CMDA[30..0]
<18,23,24,25> CMDA[30..0]
1
CMD30 BA2 BA2
J1 B1 J1 B1
R2081 VGA@ L1 NC/ODT1 VSSQ B9 R2082 VGA@ L1 NC/ODT1 VSSQ B9
NC/CS1 VSSQ NC/CS1 VSSQ Not Available
243_0402_1% J9 D1 243_0402_1% J9 D1
L9 NC/CE1 VSSQ D8 L9 NC/CE1 VSSQ D8
2
2
3 NCZQ1 VSSQ E2 NCZQ1 VSSQ E2 3
VSSQ E8 VSSQ E8
VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1
VSSQ VSSQ Command Bit Default Pull-down
G9 G9
VSSQ VSSQ ODTx 10k
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 DDR3 CKEx 10k
H5TQ2G63BFR-11C_FBGA96 H5TQ2G63BFR-11C_FBGA96 RST 10k
CS* No Termination
CLKA0
<18,23> CLKA0
1
VGA@
R2087
160_0402_1% +1.5VSDGPU +1.5VSDGPU
2
CLKA0#
<18,23> CLKA0#
R2085 R2086
VGA@ VGA@
1.33K_0402_1% 1.33K_0402_1%
+MEM_VREFCA0 +MEM_VREFDQ0
+MEM_VREFCA0 <23> +MEM_VREFDQ0 <23>
1 1
CMDA0 R2093 1 VGA@ 2 10K_0402_5% R2091 C2055 R2092 C2056
CMDA3 R2094 1 VGA@ 2 10K_0402_5% VGA@ VGA@ VGA@ VGA@
+1.5VSDGPU CMDA16 R2095 1 VGA@ 2 10K_0402_5% 1.33K_0402_1% 0.1U_0402_16V4Z 1.33K_0402_1% 0.1U_0402_16V4Z
CMDA19 R2098 1 VGA@ 2 10K_0402_5% 2 2
4 CMDA20 R2099 1 VGA@ 2 10K_0402_5% 4
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
VGA@ C2071
VGA@ C2072
VGA@ C2073
VGA@ C2074
VGA@ C2075
VGA@ C2076
VGA@ C2077
VGA@ C2078
VGA@ C2079
VGA@ C2080
VGA@ C2081
VGA@ C2082
1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N15X Upper Rank0 6/9
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A5WAH M/B LA-B991P
Date: Friday, October 17, 2014 Sheet 22 of 54
A B C D E
A B C D E
DQSA#[7..0]
<18,22,24,25> DQSA#[7..0]
DQMA[7..0]
<18,22,24,25> DQMA[7..0]
MDA[63..0]
<18,22,24,25> MDA[63..0]
CMDA[30..0]
<18,22,24,25> CMDA[30..0]
Upper Rank 1 TOP SIDE
1 1
Rank0 Rank1
Mode E
Address 0..31 32..63 0..31 32..63
U2007 X76@ CMD0 ODT ODT
U2006 X76@
+MEM_VREFCA0 M8 E3 MDA30
+MEM_VREFCA0 M8 +MEM_VREFDQ0 H1 VREFCA DQL0 CMD1 CS1*
E3 MDA16 F7 MDA25
<22> +MEM_VREFCA0 +MEM_VREFDQ0 H1 VREFCA DQL0 VREFDQ DQL1
F7 MDA23 F2 MDA28 CMD2 CS0*
<22> +MEM_VREFDQ0 VREFDQ DQL1 DQL2
F2 MDA18 CMDA9 N3 F8 MDA24
CMDA9 N3 DQL2 F8 MDA22 CMDA24 P7 A0 DQL3 H3 MDA29 Group3
A0 DQL3 A1 DQL4 CMD3 CKE CKE
CMDA24 P7 H3 MDA17 Group2 CMDA10 P3 H8 MDA26
CMDA10 P3 A1 DQL4 H8 MDA20 CMDA13 N2 A2 DQL5 G2 MDA31
A2 DQL5 A3 DQL6 CMD4 A9 A9 A11 A11
CMDA13 N2 G2 MDA19 CMDA26 P8 H7 MDA27
CMDA26 P8 A3 DQL6 H7 MDA21 CMDA22 P2 A4 DQL7
A4 DQL7 A5 CMD5 A6 A6 A7 A7
CMDA22 P2 CMDA21 R8
CMDA21 R8 A5 CMDA5 R2 A6 D7 MDA1
A6 A7 DQU0 CMD6 A3 A3 BA1 BA1
CMDA5 R2 D7 MDA9 CMDA8 T8 C3 MDA6
CMDA8 T8 A7 DQU0 C3 MDA12 CMDA23 R3 A8 DQU1 C8 MDA2
A8 DQU1 A9 DQU2 CMD7 A0 A0 A12 A12
CMDA23 R3 C8 MDA11 CMDA28 L7 C2 MDA4
CMDA28 L7 A9 DQU2 C2 MDA14 CMDA4 R7 A10/AP DQU3 A7 MDA3 Group0
A10/AP DQU3 A11 DQU4 CMD8 A8 A8 A8 A8
CMDA4 R7 A7 MDA8 Group1 CMDA7 N7 A2 MDA7
CMDA7 N7 A11 DQU4 A2 MDA15 CMDA14 T3 A12 DQU5 B8 MDA0
A12 DQU5 A13 DQU6 CMD9 A12 A12 A0 A0
CMDA14 T3 B8 MDA10 CMDA12 T7 A3 MDA5
CMDA12 T7 A13 DQU6 A3 MDA13 M7 A14 DQU7
A14 DQU7 A15/BA3 +1.5VSDGPU
CMD10 A1 A1 A2 A2
M7
A15/BA3 +1.5VSDGPU CMD11 RAS* RAS* RAS* RAS*
CMDA29 M2 B2
CMDA29 M2 B2 CMDA6 N8 BA0 VDD D9
BA0 VDD BA1 VDD CMD12 A13 A13 A14 A14
CMDA6 N8 D9 CMDA30 M3 G7
CMDA30 M3 BA1 VDD G7 BA2 VDD K2
BA2 VDD VDD CMD13 BA1 BA1 A3 A3
K2 K8
2 VDD K8 VDD N1 2
VDD VDD CMD14 A14 A14 A13 A13
N1 CLKA0 J7 N9
CLKA0 J7 VDD N9 CLKA0# K7 CK VDD R1
<18,22> CLKA0 CK VDD CK VDD CMD15 CAS* CAS* CAS* CAS*
CLKA0# K7 R1 CMDA3 K9 R9
<18,22> CLKA0# CK VDD CKE/CKE0 VDD +1.5VSDGPU
CMDA3 K9 R9 CMD16 ODT ODT
CKE/CKE0 VDD +1.5VSDGPU
CMDA0 K1 A1 CMD17 CS1*
CMDA0 K1 A1 CMDA1 L2 ODT/ODT0 VDDQ A8
CMDA1 L2 ODT/ODT0 VDDQ A8 CMDA11 J3 CS/CS0 VDDQ C1
CS/CS0 VDDQ RAS VDDQ CMD18 CS0*
CMDA11 J3 C1 CMDA15 K3 C9
CMDA15 K3 RAS VDDQ C9 CMDA25 L3 CAS VDDQ D2
CAS VDDQ WE VDDQ CMD19 CKE CKE
CMDA25 L3 D2 310mAVDDQ E9
WE VDDQ E9 F1
310mAVDDQ VDDQ CMD20 RST RST RST RST
F1 DQSA3 F3 H2
DQSA2 F3 VDDQ H2 DQSA0 C7 DQSL VDDQ H9
DQSL VDDQ DQSU VDDQ CMD21 A7 A7 A6 A6
DQSA1 C7 H9
DQSU VDDQ
CMD22 A4 A4 A5 A5
DQMA3 E7 A9
DQMA2 E7 A9 DQMA0 D3 DML VSS B3
DML VSS DMU VSS CMD23 A11 A11 A9 A9
DQMA1 D3 B3 E1
DMU VSS E1 VSS G8
VSS VSS CMD24 A2 A2 A1 A1
G8 DQSA#3 G3 J2
DQSA#2 G3 VSS J2 DQSA#0 B7 DQSL VSS J8
DQSL VSS DQSU VSS CMD25 A10 A10 WE* WE*
DQSA#1 B7 J8 M1
DQSU VSS M1 VSS M9
VSS VSS CMD26 A5 A5 A4 A4
M9 P1
VSS P1 CMDA20 T2 VSS P9
VSS RESET VSS CMD27 BA2 BA2
CMDA20 T2 P9 T1
RESET VSS T1 ZQ3 L8 VSS T9
VSS ZQ/ZQ0 VSS CMD28 WE* WE* A10 A10
ZQ2 L8 T9
1
ZQ/ZQ0 VSS GT4G@ CMD29 BA0 BA0 BA0 BA0
1
R2101 J1 B1
GT4G@ J1 B1 243_0402_1% L1 NC/ODT1 VSSQ B9
NC/ODT1 VSSQ NC/CS1 VSSQ CMD30 BA2 BA2
3 R2100 L1 B9 J9 D1 3
243_0402_1% J9 NC/CS1 VSSQ D1 L9 NC/CE1 VSSQ D8 Not Available
2
L9 NC/CE1 VSSQ D8 NCZQ1 VSSQ E2
2
+1.5VSDGPU
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
GT4G@ C2059
GT4G@ C2060
GT4G@ C2061
GT4G@ C2062
GT4G@ C2063
GT4G@ C2064
GT4G@ C2065
GT4G@ C2066
GT4G@ C2067
GT4G@ C2068
GT4G@ C2069
GT4G@ C2070
1 1 1 1 1 1 1 1 1 1 1 1
4
2 2 2 2 2 2 2 2 2 2 2 2 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N15X Upper Rank1 7/9
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A5WAH M/B LA-B991P
Date: Friday, October 17, 2014 Sheet 23 of 54
A B C D E
A B C D E
<18,22,23,25>
DQSA[7..0]
DQSA#[7..0]
DQSA[7..0]
DQSA#[7..0]
www.laptopblue.vn
DQMA[7..0]
<18,22,23,25> DQMA[7..0]
<18,22,23,25> MDA[63..0]
MDA[63..0]
CMDA[30..0]
Lower Rank 0 BOT SIDE
<18,22,23,25> CMDA[30..0]
1 Rank0 Rank1 1
Mode E
Address 0..31 32..63 0..31 32..63
U2008 X76@ U2009 X76@
+MEM_VREFCA1 M8 +MEM_VREFCA1
CMD0 ODT ODT
E3 MDA32 M8 E3 MDA50
+MEM_VREFDQ1 H1 VREFCA DQL0 F7 MDA39 +MEM_VREFDQ1 H1 VREFCA DQL0 F7 MDA52
VREFDQ DQL1 VREFDQ DQL1 CMD1 CS1*
F2 MDA34 F2 MDA49
CMDA7 N3 DQL2 F8 MDA36 CMDA7 N3 DQL2 F8 MDA53
A0 DQL3 A0 DQL3 CMD2 CS0*
CMDA10 P7 H3 MDA33 Group4 CMDA10 P7 H3 MDA48 Group6
CMDA24 P3 A1 DQL4 H8 MDA37 CMDA24 P3 A1 DQL4 H8 MDA55
A2 DQL5 A2 DQL5 CMD3 CKE CKE
CMDA6 N2 G2 MDA35 CMDA6 N2 G2 MDA51
CMDA22 P8 A3 DQL6 H7 MDA38 CMDA22 P8 A3 DQL6 H7 MDA54
A4 DQL7 A4 DQL7 CMD4 A9 A9 A11 A11
CMDA26 P2 CMDA26 P2
CMDA5 R8 A5 CMDA5 R8 A5
A6 A6 CMD5 A6 A6 A7 A7
CMDA21 R2 D7 MDA56 CMDA21 R2 D7 MDA46
CMDA8 T8 A7 DQU0 C3 MDA59 CMDA8 T8 A7 DQU0 C3 MDA41
A8 DQU1 A8 DQU1 CMD6 A3 A3 BA1 BA1
CMDA4 R3 C8 MDA58 CMDA4 R3 C8 MDA44
CMDA25 L7 A9 DQU2 C2 MDA62 CMDA25 L7 A9 DQU2 C2 MDA42
A10/AP DQU3 A10/AP DQU3 CMD7 A0 A0 A12 A12
CMDA23 R7 A7 MDA57 Group7 CMDA23 R7 A7 MDA47 Group5
CMDA9 N7 A11 DQU4 A2 MDA61 CMDA9 N7 A11 DQU4 A2 MDA43
A12 DQU5 A12 DQU5 CMD8 A8 A8 A8 A8
CMDA12 T3 B8 MDA60 CMDA12 T3 B8 MDA45
CMDA14 T7 A13 DQU6 A3 MDA63 CMDA14 T7 A13 DQU6 A3 MDA40
A14 DQU7 A14 DQU7 CMD9 A12 A12 A0 A0
M7 M7
A15/BA3 +1.5VSDGPU A15/BA3 +1.5VSDGPU CMD10 A1 A1 A2 A2
CMDA29 M2 B2 CMDA29 M2 B2 CMD11 RAS* RAS* RAS* RAS*
CMDA13 N8 BA0 VDD D9 CMDA13 N8 BA0 VDD D9
CMDA27 M3 BA1 VDD G7 CMDA27 M3 BA1 VDD G7
BA2 VDD BA2 VDD CMD12 A13 A13 A14 A14
K2 K2
VDD K8 VDD K8
VDD VDD CMD13 BA1 BA1 A3 A3
N1 N1
CLKA1 J7 VDD N9 CLKA1 J7 VDD N9
CK VDD CK VDD CMD14 A14 A14 A13 A13
CLKA1# K7 R1 CLKA1# K7 R1
2 CMDA19 K9 CK VDD R9 CMDA19 K9 CK VDD R9 2
CKE/CKE0 VDD +1.5VSDGPU CKE/CKE0 VDD +1.5VSDGPU
CMD15 CAS* CAS* CAS* CAS*
CMD16 ODT ODT
CMDA16 K1 A1 CMDA16 K1 A1
CMDA18 L2 ODT/ODT0 VDDQ A8 CMDA18 L2 ODT/ODT0 VDDQ A8
CS/CS0 VDDQ CS/CS0 VDDQ CMD17 CS1*
CMDA11 J3 C1 CMDA11 J3 C1
CMDA15 K3 RAS VDDQ C9 CMDA15 K3 RAS VDDQ C9
CAS VDDQ CAS VDDQ CMD18 CS0*
CMDA28 L3 D2 CMDA28 L3 D2
WE VDDQ E9 WE VDDQ E9
VDDQ 310mAVDDQ CMD19 CKE CKE
310mAVDDQ F1 F1
DQSA4 F3 H2 DQSA6 F3 VDDQ H2
DQSL VDDQ DQSL VDDQ CMD20 RST RST RST RST
DQSA7 C7 H9 DQSA5 C7 H9
DQSU VDDQ DQSU VDDQ
CMD21 A7 A7 A6 A6
DQMA4 E7 A9 DQMA6 E7 A9 CMD22 A4 A4 A5 A5
DQMA7 D3 DML VSS B3 DQMA5 D3 DML VSS B3
DMU VSS E1 DMU VSS E1
VSS VSS CMD23 A11 A11 A9 A9
G8 G8
DQSA#4 G3 VSS J2 DQSA#6 G3 VSS J2
DQSL VSS DQSL VSS CMD24 A2 A2 A1 A1
DQSA#7 B7 J8 DQSA#5 B7 J8
DQSU VSS M1 DQSU VSS M1
VSS VSS CMD25 A10 A10 WE* WE*
M9 M9
VSS P1 VSS P1
VSS VSS CMD26 A5 A5 A4 A4
CMDA20 T2 P9 CMDA20 T2 P9
RESET VSS T1 RESET VSS T1
VSS VSS CMD27 BA2 BA2
ZQ5 L8 T9 ZQ4 L8 T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS
CMD28 WE* WE* A10 A10
1
1
J1 B1 J1 B1 CMD29 BA0 BA0 BA0 BA0
R2083 VGA@ L1 NC/ODT1 VSSQ B9 R2084 VGA@ L1 NC/ODT1 VSSQ B9
243_0402_1% J9 NC/CS1 VSSQ D1 243_0402_1% J9 NC/CS1 VSSQ D1
NC/CE1 VSSQ NC/CE1 VSSQ CMD30 BA2 BA2
L9 D8 L9 D8
2
2
NCZQ1 VSSQ E2 NCZQ1 VSSQ E2
VSSQ VSSQ Not Available
3 E8 E8 3
VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1
VSSQ G9 VSSQ G9
VSSQ VSSQ
96-BALL 96-BALL Command Bit Default Pull-down
SDRAM DDR3 SDRAM DDR3
H5TQ2G63BFR-11C_FBGA96 H5TQ2G63BFR-11C_FBGA96 ODTx 10k
+1.5VSDGPU +1.5VSDGPU
+1.5VSDGPU
R2088 R2089
VGA@ VGA@
1.33K_0402_1% 1.33K_0402_1%
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
VGA@ C2098
VGA@ C2104
VGA@ C2094
VGA@ C2103
VGA@ C2095
VGA@ C2097
VGA@ C2100
VGA@ C2096
VGA@ C2102
VGA@ C2101
VGA@ C2099
VGA@ C2105
1 1 1 1 1 1 1 1 1 1 1 1 CLKA1
+MEM_VREFCA1 +MEM_VREFDQ1 <18,25> CLKA1
+MEM_VREFCA1 <25> +MEM_VREFDQ1 <25>
1
1 1 VGA@
2 2 2 2 2 2 2 2 2 2 2 2 R2096 C2057 R2097 C2058 R2103
VGA@ VGA@ VGA@ VGA@ 160_0402_1%
1.33K_0402_1% 0.1U_0402_16V4Z 1.33K_0402_1% 0.1U_0402_16V4Z
2
4
2 2 CLKA1# 4
<18,25> CLKA1#
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N15X Lower Rank0 8/9
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A5WAH M/B LA-B991P
Date: Friday, October 17, 2014 Sheet 24 of 54
A B C D E
A B C D E
DQSA#[7..0]
<18,22,23,24> DQSA#[7..0]
DQMA[7..0]
<18,22,23,24> DQMA[7..0]
MDA[63..0]
<18,22,23,24> MDA[63..0]
CMDA[30..0]
<18,22,23,24> CMDA[30..0]
Rank0 Rank1
Mode E
Address 0..31 32..63 0..31 32..63
CMD0 ODT ODT
U2010 X76@ U2011 X76@
+MEM_VREFCA1 M8 +MEM_VREFCA1 M8
CMD1 CS1*
E3 MDA39 E3 MDA52
<24> +MEM_VREFCA1 +MEM_VREFDQ1 H1 VREFCA DQL0 +MEM_VREFDQ1 H1 VREFCA DQL0
F7 MDA32 F7 MDA50 CMD2 CS0*
<24> +MEM_VREFDQ1 VREFDQ DQL1 VREFDQ DQL1
F2 MDA36 F2 MDA53
CMDA9 N3 DQL2 F8 MDA34 CMDA9 N3 DQL2 F8 MDA49
A0 DQL3 A0 DQL3 CMD3 CKE CKE
CMDA24 P7 H3 MDA38 Group4 CMDA24 P7 H3 MDA54 Group6
CMDA10 P3 A1 DQL4 H8 MDA35 CMDA10 P3 A1 DQL4 H8 MDA51
A2 DQL5 A2 DQL5 CMD4 A9 A9 A11 A11
CMDA13 N2 G2 MDA37 CMDA13 N2 G2 MDA55
CMDA26 P8 A3 DQL6 H7 MDA33 CMDA26 P8 A3 DQL6 H7 MDA48
A4 DQL7 A4 DQL7 CMD5 A6 A6 A7 A7
CMDA22 P2 CMDA22 P2
CMDA21 R8 A5 CMDA21 R8 A5
A6 A6 CMD6 A3 A3 BA1 BA1
CMDA5 R2 D7 MDA59 CMDA5 R2 D7 MDA41
CMDA8 T8 A7 DQU0 C3 MDA56 CMDA8 T8 A7 DQU0 C3 MDA46
A8 DQU1 A8 DQU1 CMD7 A0 A0 A12 A12
CMDA23 R3 C8 MDA62 CMDA23 R3 C8 MDA42
CMDA28 L7 A9 DQU2 C2 MDA58 CMDA28 L7 A9 DQU2 C2 MDA44
A10/AP DQU3 A10/AP DQU3 CMD8 A8 A8 A8 A8
CMDA4 R7 A7 MDA63 Group7 CMDA4 R7 A7 MDA40 Group5
CMDA7 N7 A11 DQU4 A2 MDA60 CMDA7 N7 A11 DQU4 A2 MDA45
A12 DQU5 A12 DQU5 CMD9 A12 A12 A0 A0
CMDA14 T3 B8 MDA61 CMDA14 T3 B8 MDA43
CMDA12 T7 A13 DQU6 A3 MDA57 CMDA12 T7 A13 DQU6 A3 MDA47
A14 DQU7 A14 DQU7 CMD10 A1 A1 A2 A2
M7 M7
A15/BA3 +1.5VSDGPU A15/BA3 +1.5VSDGPU CMD11 RAS* RAS* RAS* RAS*
CMDA29 M2 B2 CMDA29 M2 B2 CMD12 A13 A13 A14 A14
CMDA6 N8 BA0 VDD D9 CMDA6 N8 BA0 VDD D9
CMDA30 M3 BA1 VDD G7 CMDA30 M3 BA1 VDD G7
BA2 VDD BA2 VDD CMD13 BA1 BA1 A3 A3
K2 K2
2 VDD K8 VDD K8 2
VDD VDD CMD14 A14 A14 A13 A13
N1 N1
CLKA1 J7 VDD N9 CLKA1 J7 VDD N9
<18,24> CLKA1 CK VDD CK VDD CMD15 CAS* CAS* CAS* CAS*
CLKA1# K7 R1 CLKA1# K7 R1
<18,24> CLKA1# CK VDD CK VDD
CMDA19 K9 R9 CMDA19 K9 R9 CMD16 ODT ODT
CKE/CKE0 VDD +1.5VSDGPU CKE/CKE0 VDD +1.5VSDGPU
CMD17 CS1*
CMDA16 K1 A1 CMDA16 K1 A1
CMDA17 L2 ODT/ODT0 VDDQ A8 CMDA17 L2 ODT/ODT0 VDDQ A8
CS/CS0 VDDQ CS/CS0 VDDQ CMD18 CS0*
CMDA11 J3 C1 CMDA11 J3 C1
CMDA15 K3 RAS VDDQ C9 CMDA15 K3 RAS VDDQ C9
CAS VDDQ CAS VDDQ CMD19 CKE CKE
CMDA25 L3 D2 CMDA25 L3 D2
WE VDDQ E9 WE VDDQ E9
310mAVDDQ 310mAVDDQ CMD20 RST RST RST RST
F1 F1
DQSA4 F3 VDDQ H2 DQSA6 F3 VDDQ H2
DQSL VDDQ DQSL VDDQ CMD21 A7 A7 A6 A6
DQSA7 C7 H9 DQSA5 C7 H9
DQSU VDDQ DQSU VDDQ
CMD22 A4 A4 A5 A5
DQMA4 E7 A9 DQMA6 E7 A9 CMD23 A11 A11 A9 A9
DQMA7 D3 DML VSS B3 DQMA5 D3 DML VSS B3
DMU VSS E1 DMU VSS E1
VSS VSS CMD24 A2 A2 A1 A1
G8 G8
DQSA#4 G3 VSS J2 DQSA#6 G3 VSS J2
DQSL VSS DQSL VSS CMD25 A10 A10 WE* WE*
DQSA#7 B7 J8 DQSA#5 B7 J8
DQSU VSS M1 DQSU VSS M1
VSS VSS CMD26 A5 A5 A4 A4
M9 M9
VSS P1 VSS P1
VSS VSS CMD27 BA2 BA2
CMDA20 T2 P9 CMDA20 T2 P9
RESET VSS T1 RESET VSS T1
VSS VSS CMD28 WE* WE* A10 A10
ZQ6 L8 T9 ZQ7 L8 T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS
CMD29 BA0 BA0 BA0 BA0
1
1
J1 B1 J1 B1 CMD30 BA2 BA2
3 R2090 GT4G@ L1 NC/ODT1 VSSQ B9 R2102 GT4G@ L1 NC/ODT1 VSSQ B9 3
243_0402_1% J9 NC/CS1 VSSQ D1 243_0402_1% J9 NC/CS1 VSSQ D1
NC/CE1 VSSQ NC/CE1 VSSQ Not Available
L9 D8 L9 D8
2
2
NCZQ1 VSSQ E2 NCZQ1 VSSQ E2
VSSQ E8 VSSQ E8
VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1
VSSQ G9 VSSQ G9
VSSQ VSSQ Command Bit Default Pull-down
96-BALL 96-BALL ODTx 10k
SDRAM DDR3 SDRAM DDR3
H5TQ2G63BFR-11C_FBGA96 H5TQ2G63BFR-11C_FBGA96 DDR3 CKEx 10k
RST 10k
CS* No Termination
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
GT4G@ C2110
GT4G@ C2151
GT4G@ C2147
GT4G@ C2150
GT4G@ C2148
GT4G@ C2149
GT4G@ C2107
GT4G@ C2152
GT4G@ C2146
GT4G@ C2109
GT4G@ C2108
GT4G@ C2106
1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N15X Lower Rank1 9/9
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A5WAH M/B LA-B991P
Date: Friday, October 17, 2014 Sheet 25 of 54
A B C D E
5 4 3 2 1
D D
+3VS_TL
+3VS +3VS_TL U50 LVDS@
LVDS@ 19 TXOUT_CLK+
TXEC+ TXOUT_CLK+ <27>
30mil 30mil L63 2 1 DP_V33 40mil 3 20 TXOUT_CLK-
TXOUT_CLK- <27>
2 1 HCB2012KF-221T30_0805 DP_V33 TXEC-
R928 LVDS@ 0_0603_5% LVDS@ 60mil13 SWR_VDD TXE2+
21 TXOUT2+ TXOUT2+ <27>
+1.2V_TL 1 SWR_VDD
Power
L73 2 18 22 TXOUT2-
LVDS
+3VS PVCC TXE2- TXOUT2- <27>
HCB2012KF-221T30_0805
LVDS@ L6 1 2 +1.2V_TL_OUT 60mil12 23 TXOUT1+
SWR_LX TXE1+ TXOUT1+ <27>
60mil 4.7UH_PG031B-4R7MS_1.1A_20% 11 24 TXOUT1- TXOUT1- <27>
27 SWR_VCCK TXE1-
+1.2V_TL VCCK
7 25 TXOUT0+ TXOUT0+ <27>
DP_V12 TXE0+ 26 TXOUT0-
60mil TXE0- TXOUT0- <27>
Close to Pin3
DP_V33 RTD2132S
2
<27> EDP_AUXP_C_TL AUX_P
10U_0603_6.3V6M
C1016
0.1U_0402_16V4Z
C1015
0.1U_0402_16V4Z
C983
DP-IN
1 14
GPIO
<27> EDP_AUXN_C_TL AUX_N GPIO(PWM OUT) TL_INVT_PWM <27>
1 1 1 15
GPIO(Panel_VCC) TL_ENVDD <27>
5 16 R934 1 LVDS@ 2 0_0402_5%
<27> EDP_TXP0_C_TL LANE0P GPIO(PWM IN) PCH_INV_PWM <8,27>
6 17
<27> EDP_TXN0_C_TL LANE0N GPIO(BL_EN) TL_BKOFF# <27>
LVDS@
LVDS@
LVDS@
2 2 2
CSCL 9 29 I2CC_SCL
CIICSCL1 LVDS MIICSCL1 I2CC_SDA I2CC_SCL <27>
CSDA 10 28
C CIICSDA1 EDID MIICDA1 I2CC_SDA <27> C
Other
1 2 TL_HPD 32 31 MODE_CFG1
<27> EDP_HPD HPD ROM MIICSCL0 MODE_CFG0
30
R936 8 MIICSDA0
1K_0402_5% 4 DP_REXT 33
2
LVDS@ DP_GND GND
Close to L64 Close to Pin13 Close to P18
LVDS@
SWR_VDD R938 RTD2132N-CG_QFN32_5X5
12K_0402_1% Part Number = SA00007A300 LVDS@ +3VS_TL
10U_0603_6.3V6M
C984
0.1U_0402_16V4Z
C1020
22U_0805_6.3V6M
C986
0.1U_0402_16V4Z
C1019
0.1U_0402_16V4Z
C1018
RP41
1
I2CC_SCL 1 8
1 1 1 1 1
use 2132S symbol I2CC_SDA 2 7
CSCL 3 6
LVDS@
LVDS@
LVDS@
LVDS@
LVDS@
CSDA 4 5
2 2 2 2 2
4.7K_8P4R_5%
+3VS_TL
2
@
R943 R944
Close to L6 Close to Pin27 Close to Pin7
4.7K_0402_5% 4.7K_0402_5%
+1.2V_TL LVDS@ +3VS_TL
10U_0603_6.3V6M
C1014
1
0.1U_0402_16V4Z
C1022
0.1U_0402_16V4Z
C1017
0.1U_0402_16V4Z
C1021
1 MODE_CFG0
1 1 1 MODE_CFG1
LVDS@
2
2
LVDS@
LVDS@
LVDS@
@
2 2 2 R945 R946 @
2
B 4.7K_0402_5% 4.7K_0402_5% Q53A B
LVDS@
CSDA 1 6
EC_I2C_TPDAT <36,37>
1
DMN66D0LDW-7_SOT363-6 @
5
Q53B
CSCL 4 3
MODE_CFG0(PIN30) EC_I2C_TPCLK <36,37>
DMN66D0LDW-7_SOT363-6
0 1 DVT modify 11/18
LVDS EP mode SMbus on SMbus3
0 X EP MODE
MODE_CFG1(PIN31)
1 ROM ONLY MODE* EEPROM MODE
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LVDS Translator - RTD2132R
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A5WAH M/B LA-B991P
Date: Friday, October 17, 2014 Sheet 26 of 54
5 4 3 2 1
A B C D E
5 OUT HCB2012KF-221T30_0805
IN 2 1
1 1
2 C368 XEMC@ EMC@
GND
1U_0402_6.3V6K
C140
1000P_0402_50V7K
C364
4 0.1U_0402_16V4Z 1 1 XEMC@
IN @ C365
1 SM01000EJ00 3000ma
3 C367 2 2 68P_0402_50V8J 220ohm@100mhz
EN 4.7U_0603_6.3V6K
2 2 DCR 0.04
G5243T11U_SOT23-5
2 LCD/ LED PANEL Conn.
R947 1 EDP@ 2 0_0402_5%
<8> PCH_ENVDD
R950 1 LVDS@ 2 0_0402_5% R959
<26> TL_ENVDD
1 2
0_0402_5%
W=60mils JLVDS1
+INVPWR_B+ 1
2 1 41
DVT modify 12/09 3 2 G1 42
change to SA00000OH00 4 3 G2 43
U20 @ +3VS +3VS W=60mils 5 4 G3 44
M74VHC1GT125DF2G_SC70-5 +3VS INVTPWM 6 5 G4 45
1 @ 2 1 5 XEMC@ DISPOFF# 7 6 G5 46
5
R362 OE Vcc U22 LVDS@ INVTPWM C549 1 2 220P_0402_50V7K EDP_HPD 8 7 G6
100K_0402_5% R401 BKOFF# 2 XEMC@ 9 8
P
<36> BKOFF# B +LCDVDD 9
2 1K_0402_5% 4 DISPOFF# C528 1 2 220P_0402_50V7K 10
IN A TL_BKOFF# 1 Y TS_EN_1 11 10
@ <26> TL_BKOFF#
G
A TXOUT_CLK+ 12 11
<26> TXOUT_CLK+
2
3 4 INVTPWM MC74VHC1G08DFT2G_SC70-5 TXOUT_CLK- 13 12
<26> TXOUT_CLK-
3
GND OUT Y R951 TXOUT2+ 14 13
<26> TXOUT2+ 14
100K_0402_5% TXOUT2- 15
2 <26> TXOUT2- TS_RST# 15 2
LVDS@ 16
<36> TS_RST# 16
R363 1 EDP@ 2 0_0402_5% R949 1 EDP@ 2 0_0402_5% TXOUT1+ 17
<8,26> PCH_INV_PWM <26> TXOUT1+
1
TXOUT1- 18 17
<26> TXOUT1-
1
24 23
EDP_AUXN_C 25 24
EDP_AUXP_C 26 25
27 26
EDP_TXP0_C 28 27
PVT modify 01/13 EDP_TXN0_C 29 28
DVT modify 11/15 change PCH_I2C1_SDA/PCH_I2C1_SCL to 30 29
Co-lay TS_I2C and LVDS EDID PCH_I2C0_SDA/PCH_I2C0_SCL EDP_TXP1_C 31 30
EDP_TXN1_C 32 31
TS_INT# 33 32
<9> TS_INT# 33
+TS_PWR 34
R438 1 EDP@ 2 0_0402_5% EDID_I2C_SDA USB20_P5 35 34
<9> PCH_I2C0_SDA EDID_I2C_SCL <10> USB20_P5 USB20_N5 35
Touch Screen R439 1 EDP@ 2 0_0402_5% Touch Screen 36
<9> PCH_I2C0_SCL <10> USB20_N5 36
+3VS 37
USB20_P6_CAMERA 38 37
R415 1 LVDS@ 2 0_0402_5% USB20_N6_CAMERA 39 38
<26> I2CC_SDA For Camera 39
LVDS EDID R433 1 LVDS@ 2 0_0402_5% 40
<26> I2CC_SCL 40
E-T_0871K-F40N-00L
CONN@
SP010011Z00
3 3
eDP Camera
Touch Screen
C372 1 2 EDP@ 0.1U_0402_16V7K EDP_TXN0_C
<4> EDP_TXN0 EDP_TXP0_C
C371 1 2 EDP@ 0.1U_0402_16V7K PreMP modify 2/17 R427 1 2 0_0402_5%
<4> EDP_TXP0 EDP_TXN0_C_TL Add 3VS power rail for AUO Touch screen
C377 1 2 LVDS@0.1U_0402_16V7K EDP_TXN0_C_TL <26> R428 1 2 0_0402_5%
C376 1 2 LVDS@0.1U_0402_16V7K EDP_TXP0_C_TL +TS_PWR
EDP_TXP0_C_TL <26> +3VS USB20_N6 USB20_N6_CAMERA
R82 3 4
<10> USB20_N6 3 4
0_0603_5%
C374 1 2 0.1U_0402_16V7K EDP_TXN1_C 1 @ 2
<4> EDP_TXN1
C373 1 2 0.1U_0402_16V7K EDP_TXP1_C USB20_P6 2 1 USB20_P6_CAMERA
<4> EDP_TXP1 <10> USB20_P6 2 1
+5VS DVT modify 11/12 L27 XEMC@
+3VS R81 Port 7 change to Port 6 DLW21HN900HQ2L_4P
EDP@ 0_0603_5%
<4> EDP_AUXN C369 1 2 0.1U_0402_16V7K EDP_AUXN_C R613 2 @ 1 100K_0402_5% 1 TS@ 2
<4> EDP_AUXP C370 1 2 0.1U_0402_16V7K EDP_AUXP_C R614 2 @ 1 100K_0402_5% JCAM1
EDP@ 1
C388 1 2 LVDS@0.1U_0402_16V7K 2 1
EDP_AUXN_C_TL <26> TS_INT# 2
C389 1 2 LVDS@0.1U_0402_16V7K EDP_AUXP_C_TL <26> +3VS R615 1 TS@ 2 100K_0402_5% 3 5
4 3 G1 6
4 G2
R616 1 @ 2 100K_0402_5% TS_RST# No used, so remove ACES_88266-04001
CONN@
SP02000K200
4 4
1 @ 2 EDP_HPD R414 1 TS@ 2 0_0402_5% TS_EN_1
<8> CPU_EDP_HPD EDP_HPD <26> <36> TS_EN
R406
0_0402_5%
1
R364
100K_0402_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
eDP Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A5WAH M/B LA-B991P
Date: Friday, October 17, 2014 Sheet 27 of 54
A B C D E
A B C D E
1 1
RP15
2.2K_0804_8P4R_5%
1 8 HDMI_SCLK
2 7 HDMI_SDATA
+HDMI_5V_OUT
3 6 DDI2_CTRL_CK
4 5 DDI2_CTRL_DATA
+3VS
HDMI connector
JHDMI1
+3VS HDMI_HPD 19
18 HP_DET
+HDMI_5V_OUT +5V
17
+HDMI_5V_OUT Q15A HDMI_SDATA 16 DDC/CEC_GND
2
+5VS U3 DMN66D0LDW-7_SOT363-6 HDMI_SCLK 15 SDA
14 SCL
3
W=40mils 1 6 HDMI_SCLK 13 Reserved
OUT <8> DDI2_CTRL_CK HDMI_R_CK- CEC
1 12
1 4 3 HDMI_SDATA 11 CK-
2 IN <8> DDI2_CTRL_DATA HDMI_R_CK+ CK_shield 2
1 1 C378 Q15B 10
2 0.1U_0402_16V4Z DMN66D0LDW-7_SOT363-6 HDMI_R_D0- 9 CK+
C398 C396 GND 2 EMC@ 8 D0-
5
0.1U_0402_16V4Z 0.1U_0402_16V4Z HDMI_R_D0+ 7 D0_shield
2 2 +3VS HDMI_R_D1- D0+
EMC@ EMC@ AP2330W-7_SC59-3 Place closed to JHDMI1 6
5 D1-
HDMI_R_D1+ 4 D1_shield 20
HDMI_R_D2- 3 D1+ GND 21
2 D2- GND 22
HDMI_R_D2+ 1 D2_shield GND 23
D2+ GND
SUYIN_100042GR019M23MZR
CONN@
SM070001310 400ma 90ohm@100mhz DCR 0.3
+3VS HDMI_CLK- R368 1 XEMC@ 2 0_0402_5% HDMI_R_CK- DC232001I00
+3VS HDMI_CLK+ R369 1 XEMC@ 2 0_0402_5% HDMI_R_CK+
1
R376
1M_0402_5% Q14A
2
HDMI_GND
2 EMC@ HDMI_TX1+ R373 1 XEMC@ 2 0_0402_5% HDMI_R_D1+ C383 2 1 0.1U_0402_16V7K HDMI_TX0- 4 5
<4> CPU_DP2_N2
2
3
Q14B
DMN66D0LDW-7_SOT363-6
+3VS 5
4
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDMI Conn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A5WAH M/B LA-B991P
Date: Friday, October 17, 2014 Sheet 28 of 54
A B C D E
5 4 3 2 1
DP to VGA-IT6513 www.laptopblue.vn
+3VS_6513
10U_0603_6.3V6M
0.1U_0402_16V4Z
0.1U_0402_16V4Z
4.7U_0603_6.3V6K
+3VS +3VS_6513 1 @ 2 1 @ 2 1 @ 2
1U_0402_6.3V6K
+3VS +HDMI_5V_OUT
1U_0402_6.3V6K
1 1 1 1 1
@ L2500 0_0603_5% L2501 0_0603_5% L2502 0_0603_5%
1U_0402_6.3V6K
1
C2500
C2501
C2502
C2505
0_0603_5% 2 @ 1 R929 1
D D
+3VS
C2503
1
2 2 2 2 2
C2504
2
C2506
R2502 R2503 R2504 R2505
2 4.7K_0402_5% 4.7K_0402_5% 2.2K_0402_5% 2.2K_0402_5%
PVT modify 01/06
R929, L2500, L2501, L2502
2
2
change to R-short
Place near Pin 35,36 Place near Pin 13,48
CRT_DATA_1 1 6 CRT_DATA
CRT_DATA <30>
5
Q2501A
DMN66D0LDW-7_SOT363-6
CRT_CLK_1 4 3 CRT_CLK
CRT_CLK <30>
+1.8V_VDDO Q2501B
DMN66D0LDW-7_SOT363-6
1
10U_0603_6.3V6M DVT modify 11/25
add level shift
C2507
@ +1.8V_RX_VDD
+3VS_6513
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
R2501 1 @ 2 0_0402_5% DP_HPD 2
<8> CPU_DP_HPD
1 1 1
1
ISPSDA
C2508
C2509
C2510
R2506 ISPSCL
4.7K_0402_5%
2 2 2
13
48
35
36
38
39
12
14
44
46
2
U2500
1
2
DVT modify 11/25
+3VS_6513 form +5VS_6513 change to +3VS_6513
IVDDO
IVDDO
DDCSCL
IVDD33
IVDD33
DDCSDA
OVDD
OVDD
IVDD
IVDD
IVDD
IVDD
DP_HPD 40
C HPD C
45 +3VS_6513
C2511 2 1 0.1U_0402_16V7K CPU_DP1_C_P0 26 270mA 270mA MCUVDDH
<4> CPU_DP1_P0 RX0P
C2512 2 1 0.1U_0402_16V7K CPU_DP1_C_N0 27
<4> CPU_DP1_N0 RX0N
C2513 2 1 0.1U_0402_16V7K CPU_DP1_C_P1 29 47 @ T2501
<4> CPU_DP1_P1 RX1P MCURSTN
C2514 2 1 0.1U_0402_16V7K CPU_DP1_C_N1 30
<4> CPU_DP1_N1 RX1N
28 @ T2502
R2508 2 @ 1 1M_0402_5% URDBG
+3VS
C2515 15 ISPSCL 1 2 R2510 22_0402_5%
0.1U_0402_16V7K ISPSCL 16 ISPSDA 1 2 R2511 22_0402_5%
2 1 DDI1_AUX_C_DP 20 ISPSDA
<8> DDI1_AUX_DP DDI1_AUX_C_DN RXAUXP CRT_CLK_1
2 1 19 23 R2514 2 1 22_0402_5%
<8> DDI1_AUX_DN RXAUXN VGADDCCLK CRT_DATA_1
C2516 21 R2515 2 1 22_0402_5%
0.1U_0402_16V7K VGADDCSDA
18 3
DCAUXP VSYNC VSYNC <30>
R2516 2 @ 1 1M_0402_5% 17 4
DCAUXN HSYNC HSYNC <30>
+1.8V_DAC_VDD
C2517
C2519
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 1
+1.8V_RX_VCC 25 10
31 AVCC VDDC
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2 1 AVCC
C2518
C2520
1 2 22
PVCC
IT6513FN 2 2
11 CRT_R
IORP CRT_R <30>
9 CRT_G
Place near Pin 22 IOGP CRT_G <30>
B B
+1.8V_RX_VDD 2 24
DVDD18 8 CRT_B
IOBP CRT_B <30>
C2521
1
0.1U_0402_16V4Z 41
1 NC/VGADETECT
5 R2517 1 2 100_0402_1%
32 RSET
+1.8V_RX_VCC 2 ASPVCC
75_0402_1% 2
75_0402_1% 2
75_0402_1% 2
C2522
7 +1.8V_DAC_VDD
0.1U_0402_16V4Z VDDA
1
DVT modify 11/25 6 1 2
form +5VS_6513 change to +3VS_6513 COMP
R2518
R2519
R2520
1 R2521 2 2.2K_0402_5% 43 C2523 0.1U_0402_16V4Z
1 R2522 2 2.2K_0402_5% 42 PCSDA
+3VS_6513 PCSCL XTALIN_6513
34
XTALIN 33 XTALOUT_6513
XTALOUT
PWDNB
1M_0402_5%
XTALOUT_6513 @ XTALIN_6513
IT6513FN_QFN48_6X6
37
49
X2500
27MHZ_10PF_X3G027000BA1H-U
R2549 Crystal
+3VS_6513 1 2 PWDNB 3 4
OUT GND
2 1
10K_0402_5% @1 GND IN
18P_0402_50V8J
1@
18P_0402_50V8J
DVT modify 11/25
add pull high 10K C2524 @
2 C2525
A
2 A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ITE IT6513FN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A5WAH M/B LA-B991P
Date: Friday, October 17, 2014 Sheet 29 of 54
5 4 3 2 1
A B C D E
www.laptopblue.vn
CRT conn.
W=40mils
+HDMI_5V_OUT
1 CRB1.0 use 47ohm@100Mhz Bead 1
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
13
1 1 1 1 1 1 3
9
C2529
C2530
C2531
C2532
C2533
C2534
14
T109 @ 4
2 2 2 2 2 2 10 G 16
15 G 17
5
CCM_070546HR015M25FZR
CONN@
R2524
DC060005810
+HDMI_5V_OUT 1 @ 2 0_0603_5% CRT_HSYNC_2
U2502 @
1 5 0.1U_0402_16V4Z 2 1 C2535 R2525 CRT_CLK <29>
R2526 OE Vcc 1 @ 2 0_0603_5% CRT_VSYNC_2
CRT_DATA <29>
0_0402_5% 1 1
2 @ 1 CRT_HSYNC 2 @ @
2 <29> HSYNC IN A 2
PVT modify 12/31 C2536 C2537
form +5VS_6513 change to +HDMI_5V_OUT 10P_0402_50V8J 10P_0402_50V8J
3 4 CRT_HSYNC_1 2 2
GND OUT Y
M74VHC1GT125DF2G_SC70-5
R2528 +HDMI_5V_OUT
0_0402_5% U2503
2 @ 1 1 5
OE Vcc
2 @ 1 CRT_VSYNC 2
<29> VSYNC IN A
R2529
0_0402_5%
3 4 CRT_VSYNC_1
GND OUT Y
M74VHC1GT125DF2G_SC70-5
3 3
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A5WAH M/B LA-B991P
Date: Friday, October 17, 2014 Sheet 30 of 54
A B C D E
5 4 3 2 1
LAN-RTL8411B www.laptopblue.vn
+3VALW DVT modify 12/20 +3V_LAN
reserve 0 ohm
2 1
@ 0_0603_5% W=60mil W=60mil
R2551 IDC=1200mA +LAN_VDD +3V_LAN
W=60mil
60mil U2504
60mil L2506
300mA 1.4A
D D
1 +REGOUT 1 2
5 OUT 2.2UH_NLC252018T-2R2J-N_5%
IN
4.7U_0603_6.3V6K
C2538
0.1U_0402_16V7K
C2539
0.1U_0402_16V7K
C2540
0.1U_0402_16V7K
C2541
0.1U_0402_16V7K
C2542
0.1U_0402_16V7K
C2543
0.1U_0402_16V7K
C2544
1U_0402_6.3V6K
C2545
0.1U_0402_16V7K
C2546
4.7U_0603_6.3V6K
C2547
0.1U_0402_16V7K
C2548
0.1U_0402_16V7K
C2549
0.1U_0402_16V7K
C2550
2 1 1 1 1 1 1 1 1 1 1 1 1 1
4 GND
IN
2 LAN_PWR_EN
3 LAN_PWR_EN <36>
C2551 EN 2 2 2 2 2 2 2 2 2 2 2 2 2
1U_0402_6.3V6K G5243T11U_SOT23-5
1
Part Number = SA000028Y10
+REGOUT 36 20
35 REG_OUT VDDTX
+3V_LAN VDDREG
SWR mode 34 800mA
46 ENSWREG 13
+LAN_VDD LV_GEN Card_3V3 +CARD_3V3 Protect cotact Card contact
2 R2542 1 LAN_RST 47
B 2.49K_0402_1% RSET 27 +VDD33_18 B
DV33/18 Write protect Write Enable
(Lock) (Unlock)
0.1U_0402_16V7K
C2555
4.7U_0603_6.3V6K
C2556
0.1U_0402_16V7K
C2557
41
Y2500 R2540 1 @ 2GPO 38 LED0
<36> LAN_GPO LED1/GPO 1 1 1
25MHZ_10PF_7V25000014 0_0402_5% 37 LEDs
40 LED2 Card Uninsert Open Open Open
XTLI 1 3 XTLO_R LED_CR 49 @
1 3 DVT modify 12/20 E_Pad 2 2 2 Card insert Open Close Close
GND GND for disable PHY
1 1 reserve 0 ohm
10P_0402_50V8J
10P_0402_50V8J 2 4 C2559
C2558 Place near Pin 27
2 2
RTL8411B-CGT_QFN48_6X6
DVT modify 11/27
TXC recommend from 12P change to 10P
+3VS
1
R2543
1K_0402_5%
2
ISOLATEB
2
R2544
15K_0402_5%
A A
1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN RTL8411-CG
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A5WAH M/B LA-B991P
Date: Friday, October 17, 2014 Sheet 31 of 54
5 4 3 2 1
5 4 3 2 1
D D
T2500
LAN_TERMAL1 24
LAN_MIDI3- 2 TCT1 MCT1 23 RJ45_MIDI3-
<31>
<31>
LAN_MIDI3-
LAN_MIDI3+
LAN_MIDI3+ 3 TD1+
TD1-
MX1+
MX1-
22 RJ45_MIDI3+ LAN Connector
4 21 JRJ1
LAN_MIDI2- 5 TCT2 MCT2 20 RJ45_MIDI2-
<31> LAN_MIDI2- LAN_MIDI2+ TD2+ MX2+ RJ45_MIDI2+
<31> LAN_MIDI2+ 6 19
TD2- MX2-
7 18
LAN_MIDI1- 8 TCT3 MCT3 17 RJ45_MIDI1- RJ45_MIDI0+ 1 9
<31> LAN_MIDI1- LAN_MIDI1+ TD3+ MX3+ RJ45_MIDI1+ PR1+ SHLD1
<31> LAN_MIDI1+ 9 16 10
TD3- MX3- RJ45_MIDI0- 2 SHLD2
10 15 PR1-
LAN_MIDI0- 11 TCT4 MCT4 14 RJ45_MIDI0- RJ45_MIDI1+ 3
<31> LAN_MIDI0- LAN_MIDI0+ TD4+ MX4+ RJ45_MIDI0+ PR2+
<31> LAN_MIDI0+ 12 13
TD4- MX4- RJ45_MIDI2+ 4
PR3+ JP2501 XEMC@
RJ45_MIDI2-
75_0402_1%
75_0402_1%
75_0402_1%
75_0402_1%
5 B88069X9231T203_4P5X3P2-2
1
GST5009-E PR3- 2 1
SP050006B10 RJ45_MIDI1- 6
PR2- 40mil
R2545
R2546
R2547
R2548
1 RJ45_MIDI3+ RJ45_GND
7 1 2 LANGND
C2561 PR4+ C2560
2
RJ45_MIDI3- 8 10P_0402_50V8J
C 2
0.1U_0402_16V7K
PR4- 40mil C
1
@
JUMP_43X118
J15 JP2500
RJ45_GND XEMC@
SANTA_130452-0B D1 B88069X9231T203_4P5X3P2-2
2
EMC@
CONN@
MESC5V02BD03 3P C/A SOT23
DC234005310
1
Card Reader Connector
JREAD1
SD_D3_R 1
<31> SD_D3_R CD/DAT3
+CARD_3V3 SD_CMD_R 2
<31> SD_CMD_R CMD
B 3 B
VSS1
Close to Card Reader CONN 4
VDD
SD_CLK_R
4.7U_0603_6.3V6K
C2564
0.1U_0402_16V7K
C2565
<31> SD_CLK_R 5
CLK
1 1
6
VSS2
SD_D0_R 7
2 2 <31> SD_D0_R DAT0
SD_D1_R 8 12
<31> SD_D1_R DAT1 G1
SD_D2_R 9 13
<31> SD_D2_R DAT2 G2
SD_CD# 10 14
<31> SD_CD# CD G3
SD_WP 11 15
<31> SD_WP WP G4
TAITW_PSDAT4-11GLBS1NN4H2
CONN@
SP07000ZC00
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN RJ45/CR SD Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A5WAH M/B LA-B991P
Date: Friday, October 17, 2014 Sheet 32 of 54
5 4 3 2 1
A B C D E
1
IN R436 53 54
GND
2 BT_ON# used RX to work 0_0402_5% GND GND
1U_0402_6.3V6K
C165
4 R437
2 IN 100K_0402_5% ACES_50709-0524W-P01 2
1
3 CONN@
2
@ EN
G5243T11U_SOT23-5
2 @
DC04000C400
<36> WLAN_ON
3 3
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MINI CARD (WLAN)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A5WAH M/B LA-B991P
Date: Friday, October 17, 2014 Sheet 33 of 54
A B C D E
A B C D E
www.laptopblue.vn
SATA HDD1 Conn. SATA ODD Conn.
JHDD1
1 1
JODD1
1
SATA_PTX_DRX_P0 HDD@ C392 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_P0 2 GND 1
<6> SATA_PTX_DRX_P0 SATA_PTX_DRX_N0 SATA_PTX_C_DRX_N0 A+ SATA_PTX_C_DRX_P1 GND
<6> SATA_PTX_DRX_N0 HDD@ C393 1 2 0.01U_0402_16V7K 3 <6> SATA_PTX_DRX_P1 C401 1 2 0.01U_0402_16V7K 2
4 A- C402 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_N1 3 A+
SATA_PRX_DTX_N0 SATA_PRX_C_DTX_N0 GND <6> SATA_PTX_DRX_N1 A-
HDD@ C391 1 2 0.01U_0402_16V7K 5 4
<6> SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 SATA_PRX_C_DTX_P0 B- SATA_PRX_C_DTX_N1 GND
HDD@ C394 1 2 0.01U_0402_16V7K 6 C403 1 2 0.01U_0402_16V7K 5
<6> SATA_PRX_DTX_P0 B+ <6> SATA_PRX_DTX_N1 SATA_PRX_C_DTX_P1 B-
7 C405 1 2 0.01U_0402_16V7K 6
GND <6> SATA_PRX_DTX_P1 B+
7
GND
R308 8 +5VS R593
+3VS V33
0_0402_5% 9 0_0805_5% 80mils 8
1 @ 2 +3VS_HDD 10 V33 1 @ 2 +5VS_ODD 9 DP
V33 +5V
10U_0603_6.3V6M
C404
0.1U_0402_16V4Z
C407
11 1 10
1
R307 1 @ 2 0_0402_5% 12 GND ODD_MD 11 +5V
<8,9> DEVSLP0 GND MD
13 12 14
R49 1 @ 2 0_0805_5% +5VS_HDD 14 GND T185 @ 13 GND GND 15
+5VS
2
15 V5 2 GND GND
16 V5
17 V5 SANTA_201902-1
18 GND CONN@
19 Reserved 23
+3VS +5VS 20 GND GND 24
21 V12 GND 25
SP01001RS00
22 V12 GND 26
100mils V12 GND
10U_0603_6.3V6M
C420
0.1U_0402_16V4Z
C397
1 1 CCM_C127043HR022M27FZR
1
0.1U_0402_16V4Z
C390
@ CONN@
HDD@ HDD@
DC010009X00
2
2 2
2 2
0.01U_0402_16V7K
BA@ C410
0.1U_0402_16V7K
BA@ C411
1 1
R589
4.7K_0402_5%
@ 2 2
U2506
2
7 10
SATA_PTX_DRX_P0 BA@ C406 2 1 SATA_PTX_C_DRX_P0_1 0.01U_0402_16V7K 1
EN VDD
VDD
20 SATA HDD1 Conn.
3 SATA_PTX_DRX_N0 BA@ C409 2 1 SATA_PTX_C_DRX_N0_1 0.01U_0402_16V7K 2 A_INp 6 1 R660 2 BA@ 3
A_INn NC 16 4.99K_0402_1%
CL 4.0 mm
SATA_PRX_DTX_P0 BA@ C399 2 1 SATA_PRX_C_DTX_P0_1 0.01U_0402_16V7K 5 NC
SATA_PRX_DTX_N0 BA@ C400 2 1 SATA_PRX_C_DTX_N0_1 0.01U_0402_16V7K 4 B_OUTp 9 APE0 JHDD2
B_OUTn A_PRE0 8 BPE0 1
APE1 19 B_PRE0 RDSATA_PTX_DRX_P0 C534 1 2 BA@ 0.01U_0402_16V7K RDSATA_PTX_C_DRX_P0 2 1
BPE1 17 A_PRE1 15 RDSATA_PTX_DRX_P0 RDSATA_PTX_DRX_N0 C535 1 2 BA@ 0.01U_0402_16V7K RDSATA_PTX_C_DRX_N0 3 2
B_PRE1 A_OUTp 14 RDSATA_PTX_DRX_N0 4 3
TEST 18 A_OUTn RDSATA_PRX_DTX_N0 C536 1 2 BA@ 0.01U_0402_16V7K RDSATA_PRX_C_DTX_N0 5 4
R665 TEST RDSATA_PRX_DTX_P0 RDSATA_PRX_DTX_P0 5
3 11 C537 1 2 BA@ 0.01U_0402_16V7K RDSATA_PRX_C_DTX_P0 6
2 1 13 GND B_INp 12 RDSATA_PRX_DTX_N0 7 6
+3VS GND B_INn 7
21 8
EPAD +3VS 8
9
4.7K_0402_5% PS8520CTQFN20GTR2-A_TQFN20_4X4 10 9
2
@ BA@ 11 10
R658 R659 12 11
0_0402_5% 4.7K_0402_5% 13 12
USE 8527 re-driver 13
@ BA@ 14
+3VS SA00007JU00 +5VS
15 14
1
10U_0603_6.3V6M
C421
0.1U_0402_16V4Z
C412
R337 1 @ 2 4.7K_0402_5% BPE1 1 23
1
24 G3
R334 1 @ 2 4.7K_0402_5% TEST BA@ BA@ G4
ACES_50406-02071-001
2
2 CONN@
R586 1 @ 2 4.7K_0402_5% APE0
SP010016L00
4 R339 1 @ 2 4.7K_0402_5% BPE0 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD/ODD/ HDD Re-Driver
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A5WAH M/B LA-B991P
Date: Friday, October 17, 2014 Sheet 34 of 54
A B C D E
A B C D E
+USB3_VCCA SF000006R00
220U 6.3V OSCON
R458 1 @ 2 0_0402_5% W=100mils ESR 17mohm@100Khz
R461 1 @ 2 0_0402_5% EMC@
USB20_P0 U2DP0_L 1 1
3 4 C487
<10> USB20_P0 3 4 C486 +
0.1U_0402_16V4Z
USB3.0 Conn.
USB20_N0 2 1 U2DN0_L 150U_6.3V_M_D2 2
<10> USB20_N0 2 1 2
L26 XEMC@
DLW21HN900HQ2L_4P
JUSB1
1
U2DN0_L 2 VBUS
U2DP0_L 3 D-
4 D+
U3RXDN0 5 GND
2 U3RXDP0 6 StdA-SSRX- 10 2
7 StdA-SSRX+ GND 11
U3TXDN0 8 GND-DRAIN GND 12
U3TXDP0 9 StdA-SSTX- GND 13
StdA-SSTX+ GND
ACON_TARAC-9V1391
CONN@
DC23300AG00
JPWR1
1 +3VALW
3 1 2 +3VS +5VALW 3
2 3 LID_SW# +3VLP
LID_SW# <36> JFP1 JUSB2
3 4 PWR_LED# 4 6 1
4 5 PWR_LED# <37> USB20_P7 4 G2 1
7 ON/OFFBTN# ON/OFFBTN# <36,37> 3 5 2
<10> USB20_P7
8 G1 5 6 USB20_N7 2 3 G1 3 2
G2 6 <10> USB20_N7 2 3
1 4
ACES_51524-0060N-001 DVT modify 11/12 1 USB_EN# 5 4
2
14
ACES_88514-01201-071
CONN@
SP01001BF00
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB3.0 Conn/USB_B/PWR_B
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A5WAH M/B LA-B991P
Date: Friday, October 17, 2014 Sheet 35 of 54
A B C D E
A B C D E
C501
22P_0402_50V8J
2 1 2 XEMC@ 1
XEMC@ R477
CLK_PCI_LPC
33_0402_5%
+3VLP
R236
@ 2 www.laptopblue.vn
+3VALW_EC DVT modify 11/12
change to SM010009U00
XEMC@ XEMC@
1
L31
BLM15BD121SN1D_2P
2 +EC_VCCA
SM010030010 200ma
+EC_VCCA
1
120ohm@100mhz DCR 0.2 LID_SW#
EC_I2C_TPCLK R489
EC_I2C_TPDAT R488
R476 1
1
1
@
@
2 100K_0402_5%
2
2
2.2K_0402_5%
2.2K_0402_5%
+3VALW_EC
1 1 1 1 2 2
0.1U_0402_16V4Z
C502
0.1U_0402_16V4Z
C503
0.1U_0402_16V4Z
C504
0.1U_0402_16V4Z
C505
1000P_0402_50V7K
C506
1000P_0402_50V7K
C507
0_0805_5% @ @ C508
0.1U_0402_16V4Z TP_CLK R485 1 @ 2 4.7K_0402_5%
2 TP_DATA +3VS
ECAGND
+3VALW_EC R483 1 @ 2 4.7K_0402_5%
R480 2 9012@ 1 47K_0402_5% EC_RST# 2 2 2 2 1 1
EC_MUTE# R481 1 @ 2 10K_0402_5% +3VS
C509 2 1 0.1U_0402_16V4Z
ECAGND <42>
111
125
22
33
96
67
U28
9
EMC@ PVT modify 1/16 EC_LID_OUT# R482 1 @ 2 10K_0402_5%
EMI request +3VS
EC_VDD0
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/AVCC
GPU_ALERT R486 1 2 10K_0402_5%
1 +3VS 1
9022: ECRST# is internally pull-up to VCC via 40Kohm resistor, VCCST_PG_EC
so can remove external pull-up resistor and capacitor. 1 21
EC_KBRST# 2 GATEA20/GPIO00 GPIO0F 23 BEEP# VCCST_PG_EC <8,11> GPU_OVERT R487 1 2 10K_0402_5%
<9> EC_KBRST# KBRST#/GPIO01 BEEP#/GPIO10 BEEP# <38> +3VS
SERIRQ 3 26
<9,37> SERIRQ LPC_FRAME# 4 SERIRQ GPIO12 27 EC_RTCRST#
<7,37> LPC_FRAME# LPC_AD3 LPC_FRAME# ACOFF/GPIO13 EC_RTCRST# <6>
5
<7,37> LPC_AD3 LPC_AD2 LPC_AD3 9012_PECI
7 PWM Output C510 2 1 100P_0402_50V8J ECAGND R497 1 2 43_0402_1%
<7,37> LPC_AD2 LPC_AD1 LPC_AD2 BATT_TEMP H_PECI <4>
8 63
+3VALW_EC <7,37> LPC_AD1 LPC_AD0 LPC_AD1 BATT_TEMP/GPIO38 VCIN1_BATT_DROP BATT_TEMP <41,42>
10 LPC & MISC 64
<7,37> LPC_AD0 LPC_AD0 GPIO39 ADP_I VCIN1_BATT_DROP <42>
65
CLK_PCI_LPC ADP_I/GPIO3A AD_BID0 ADP_I <42,43>
12 AD Input 66
EC_PME# <7> CLK_PCI_LPC PLT_RST# CLK_PCI_EC GPIO3B WLAN_PME#
R484 1 @ 2 100K_0402_5% 13 75
<8,17,37> PLT_RST# EC_RST# PCIRST#/GPIO05 GPIO42 EC_PME# WLAN_PME# <33>
37 76
EC_SMI#_SCI# EC_RST# IMON/GPIO43 EC_PME# <31>
20 R509 1 @ 2 0_0402_5% ACIN <8,41,43>
+3VALW_EC <9> EC_SMI#_SCI# WLAN_ON EC_SCII#/GPIO0E
RP12 38
<33> WLAN_ON GPIO1D LAN_PWR_EN
68
EC_SMB_CK1 DAC_BRIG/GPIO3C EN_DFAN1 LAN_PWR_EN <31> EC_ACIN
1 8 70 C512 2 1 100P_0402_50V8J
EC_SMB_DA1 EN_DFAN1/GPIO3D TP_EN EN_DFAN1 <39>
2 7 DA Output 71
EC_SMB_CK2 IREF/GPIO3E KBL_EN# TP_EN <37>
3 6 KSI0 55 72
EC_SMB_DA2 KSI0/GPIO30 CHGVADJ/GPIO3F KBL_EN# <37>
+3VS 4 5 KSI1 56 PVT modify 12/31
KSI2 57 KSI1/GPIO31 EMI add C518
2.2K_0804_8P4R_5% KSI3 58 KSI2/GPIO32 83 EC_MUTE# EMC@
KSI4 59 KSI3/GPIO33 EC_MUTE#/GPIO4A 84 USB_EN# EC_MUTE# <38> C518 1 2 0.1U_0402_16V4Z
KSI5 60 KSI4/GPIO34 USB_EN#/GPIO4B 85 EC_I2C_TPCLK USB_EN# <35>
PLT_RST# KSI5/GPIO35 CAP_INT#/GPIO4C EC_I2C_TPDAT EC_I2C_TPCLK <26,37> EC_RTCRST#
C511 1 2 0.01U_0402_16V7K KSI6 61 PS2 Interface 86 R490 1 2 10K_0402_5%
KSI6/GPIO36 EAPD/GPIO4D TP_CLK EC_I2C_TPDAT <26,37>
EMC@ KSI7 62 87
KSI7/GPIO37 TP_CLK/GPIO4E TP_DATA TP_CLK <37>
ESD request KSO0 39 88
KSI[0..7] KSO0/GPIO20 TP_DATA/GPIO4F TP_DATA <37>
KSO1 40 DVT modify 11/15
<37> KSI[0..7] KSO1/GPIO21 EC pin will have HiZ status on Reset mode
KSO2 41 R691 2 1 100K_0402_5%
KSO[0..17] KSO3 42 KSO2/GPIO22 97 ENBKL
+3VS <37> KSO[0..17] KSO3/GPIO23 CPU1.5V_S3_GATE/GPXIOA00 TP_PWR_EN ENBKL <8>
KSO4 43 98 PVT modify 01/13
KSO4/GPIO24 WOL_EN/GPXIOA01 HDA_SDO TP_PWR_EN <37> add TP_PWR_EN
KSO5 44 99
KSO6 45 KSO5/GPIO25 Int. K/B HDA_SDO/GPXIOA02 109 VCIN0_PH_R HDA_SDO <6>
2 R492 1 @ EC_SMI#_SCI#
2 10K_0402_5% KSO7 46 KSO6/GPIO26 Matrix VCIN0_PH/GPXIOD00 KB9022&9012 Co-Layout Item 2
KSO7/GPIO27 SPI Device Interface
KSO8 47 Reserve for Share ROM EC
KSO9 48 KSO8/GPIO28 119 EC_SPI_SI
KSO9/GPIO29 SPIDI/GPIO5B EC_SPI_SO EC_SPI_SI <7>
KSO10 49 120 EC_SPI_SO <7>
KSO11 50 KSO10/GPIO2A SPIDO/GPIO5C 126 EC_SPI_CLK H_PROCHOT#_EC 1 9022@ 2
9022:Change control method from push-pull to open-drain, KSO11/GPIO2B SPI Flash ROM SPICLK/GPIO58 EC_SPI_CS# EC_SPI_CLK <7>
so EC_SCI# must be pull high. *PU on PCH side KSO12 51 128 EC_SPI_CS# <7> R499 0_0402_5%
KSO13 52 KSO12/GPIO2C SPICS#/GPIO5A
(Pull high in PCH side) KSO13/GPIO2D
KSO14 53 1 2 H_PROCHOT# <4,41>
KSO14/GPIO2E GPU_ALERT <48> VR_HOT#
KSO15 54 73 R496 0_0402_5%
KSO15/GPIO2F ENBKL/GPIO40 GPU_OVERT GPU_ALERT <17>
KSO16 81 74
KSO16/GPIO48 PECI_KB930/GPIO41 GPU_OVERT <17>
KSO17 82 89
1
KSO17/GPIO49 FSTCHG/GPIO50 90 BATT_BLUE_LED# D
BATT_CHG_LED#/GPIO52 BATT_BLUE_LED# <37> H_PROCHOT#_EC
91 2 Q50
For abnormal shutdown EC_SMB_CK1 77 CAPS_LED#/GPIO53 92 PWR_LED
<42,43> EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK1/GPIO44 GPIO PWR_LED#/GPIO54 BATT_AMB_LED# PWR_LED <37> G L2N7002LT1G_SOT23-3
78 93 S 9012@
<42,43> EC_SMB_DA1 BATT_AMB_LED# <37>
3
D25 EC_SMB_CK2 79 EC_SMB_DA1/GPIO45 BATT_LOW_LED#/GPIO55 95 SYSON
<7,17> EC_SMB_CK2 EC_SMB_DA2 EC_SMB_CK2/GPIO46SM Bus SYSON/GPIO56 EC_TP_INT# SYSON <40,45> Latest design guide suggest change to
RB751V-40 SOD-323 80 121
SPOK 1 2 PCH_RSMRST# <7,17> EC_SMB_DA2 EC_SMB_DA2/GPIO47 VR_ON/GPIO57 127
EC_TP_INT# <37> 74LVC1G06.
PM_SLP_S4#/GPIO59
D26
RB751V-40 SOD-323 PM_SLP_S3# 6 100 PCH_RSMRST#
PCH_PWROK <8> PM_SLP_S3# PM_SLP_S5# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 EC_LID_OUT# PCH_RSMRST# <8>
@ 1 2 14 101
<8> PM_SLP_S5# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXIOA04 VCIN1_PROCHOT EC_LID_OUT# <9>
15 102
TS_RST# 16 EC_SMI#/GPIO08 PROCHOT_IN/GPXIOA05 103 H_PROCHOT#_EC
<27> TS_RST# TS_EN GPIO0A H_PROCHOT#_EC/GPXIOA06 H_PROCHOT#_EC <42>
17 104 MAINPWON
<27> TS_EN WL_OFF# GPIO0B VCOUT0_PH/GPXIOA07 MAINPWON <42,44>
18 GPO BKOFF#/GPXIOA08 105 BKOFF#
<33> WL_OFF# EC_GPIO0D GPIO0C LAN_GPO BKOFF# <27> +3VALW_EC
19 GPIO 106
GPIO0D PBTN_OUT#/GPXIOA09 DGPU_AC_DETECT LAN_GPO <31>
SPOK 25 107
+3VALW_EC <44> SPOK FAN_SPEED1 EC_INVT_PWM/GPIO11 PCH_APWROK/GPXIOA10 VCCST_PWRGD DGPU_AC_DETECT <9,17>
28 108
<39> FAN_SPEED1 FAN_SPEED1/GPIO14 SA_PGOOD/GPXIOA11 VCCST_PWRGD <11,46>
29
Board ID <33> E51TXD_P80DATA
E51TXD_P80DATA 30 EC_PME#/GPIO15
2
2
E51RXD_P80CLK 31 EC_TX/GPIO16 110 EC_ACIN
Analog Board ID definition, <33> E51RXD_P80CLK PCH_PWROK EC_RX/GPIO17 AC_IN/GPXIOD01 EC_ON
R503 Please see page 3. 32 112
<8> PCH_PWROK PWR_SUSP_LED# PCH_PWROK/GPIO18 EC_ON/GPXIOD02 EC_ON <44>
3 Ra 100K_0402_5% 34 114 ON/OFFBTN# @ @ 3
<37> PWR_SUSP_LED# SUSP_LED#/GPIO19 ON/OFF/GPXIOD03 LID_SW# ON/OFFBTN# <35,37>
36 GPI 115 R697 R696
NUM_LED#/GPIO1A LID_SW#/GPXIOD04 LID_SW# <35>
116 SUSP# 10K_0402_5% 10K_0402_5%
SUSP# <40,45,46,47>
1
1
AD_BID0 SUSP#/GPXIOD05 117 VGATE_3V VCIN0_PH_R R501 1 @ 2 0_0402_5%
GPXIOD06 9012_PECI VGATE_3V <8> VCIN1_PROCHOT VCIN0_PH <42>
118
VCIN1_PROCHOT <42>
1
@
2 PVT2 modify 2/24 C515
2
69
L32
20mil BLM15BD121SN1D_2P
ECAGND 1 2
reserve for LVDS EP mode
SM010030010 200ma 120ohm@100mhz DCR 0.2
DVT modify 11/12
R491 1 @ 2 10K_0402_5% EC_GPIO0D change to SM010009U00
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EC ENE-KB9012
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A5WAH M/B LA-B991P
Date: Friday, October 17, 2014 Sheet 36 of 54
A B C D E
A B C D E
KB Conn. JKB1
www.laptopblue.vn
TP/B Conn.
+3V_PTP
PVT modify 01/13
add +3V_PTP
4.7U_0603_6.3V6K
KSO4 5 10 1
KSO5 6 5 KSI[0..7] GND 9 0.1U_0402_16V4Z OUT 5
6 KSI[0..7] <36> GND 1 IN
C2563
KSO6 7 8 C663 1 2
KSO7 8 7 KSO[0..17] 8 7 @ TP_CLK_TP 2
8 KSO[0..17] <36> 7 TP_DATA_TP GND
KSO8 9 6 EC PS2 4
KSO9 10 9 6 5 2 IN
10 5 TP_SDATA
2
KSO10 11 4 3
1 11 4 TP_SCLK EN 1
KSO11 12 3 C2562
KSO12 13 12 3 2 TP_INT#_R G5243T11U_SOT23-5 1U_0402_6.3V6K
KSO13 14 13 2 1 TP_EN Part Number = SA000028Y10 1
14 1 TP_EN <36>
KSO14 15 PreMP modify 02/21
<36> TP_PWR_EN
KSO15 16 15 change JTP1 ACES_51524-00801-001
KSO16 17 16
KSO17 18 17
18 TP_PWR_EN follow SYSON behavior
KSI0 19
KSI1 20 19 SP01001A910
KSI2 21 20
KSI3 22 21 EC_TP_INT# 1 @ 2 TP_INT#_R PVT modify 01/06
22 <36> EC_TP_INT# R462, R453, R448, R449
KSI4 23 R453 0_0402_5%
KSI5 24 23 change to R-short
KSI6
KSI7
25
26
24
25 G1
27
28
EC I2C <26,36> EC_I2C_TPDAT
EC_I2C_TPDAT 1
R445
@ 2
0_0402_5%
TP_SDATA
To BA50 TP/B Conn.
26 G2 SP01000IJ00
EC_I2C_TPCLK 1 @ 2 TP_SCLK +5VS
<26,36> EC_I2C_TPCLK
E-T_6905-E26N-01R R447 0_0402_5% C664 BA@
CONN@ JTP2 0.1U_0402_16V4Z
1 1 2
PCH_I2C1_SDA 1 @ 2 TP_SDATA 1 2 TP_DATA_TP
<9> PCH_I2C1_SDA 2 TP_CLK_TP
R448 0_0402_5% 3
3
ACES_51524-0060N-001
CONN@
+5VS +3V_PTP PVT modify 01/13
JBL1 +3VALW change to +3V_PTP SP010014M10
+5VS_BL
S
3 1 4 6
2
+5VALW 34 G2 5
KB@ 23 G1 SW7 BA@ SW6 BA@
2 R451 Q44 12 R633 TP_CLK_TP TJE-532QR5_4P TJE-532QR5_4P 2
G
2
100P_0402_50V8J
1
TP_INT# TP_INT#_R
C553
XEMC@ C551
CONN@ 2 1 4 2 4 2
100P_0402_50V8J
<8,9> TP_INT# 1 1
SP01000Z300 RB751V-40_SOD323-2
5
6
5
6
1
2 2
XEMC@
<36> KBL_EN# 1 @ 2 1 @ 2
R592 C524 R452 0_0402_5% DVT modify 11/26
0_0402_5% for TP wake function
0.1U_0603_25V7K Q51 remove, add D22
2
@ +3VS change to +3VALW
1
PVT modify 01/22
+3VALW +3VALW_TPM +3VS +3VS_TPM R2509 R2507 Add level shifter on T/P PS2 signal
R534
R2600 R2601 4.7K_0402_5% 4.7K_0402_5%
1 2 1 2 ON/OFFBTN# 1 2 +3VLP
10U_0603_6.3V6M
0.1U_0402_16V4Z
10U_0603_6.3V6M
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0_0603_5% 0_0603_5%
2
C2600 TPM@
C2601 TPM@
C2602 TPM@
C2603 TPM@
C2604 TPM@
C2605 TPM@
5
2 2 2 2 2 2 Q2503A
Test Only SW3 @ DMN66D0LDW-7_SOT363-6
EVQPLDA15_4P TP_DATA_TP 3 4
TP_DATA <36>
3 1 3 3
TOP Q2503B
near pin10, 19, 24 2 4 DVT modify 12/10 DMN66D0LDW-7_SOT363-6
chagne to SN100000K00
@
6
5
1 2
R456 0_0402_5%
BADD SELECTION 1 2
R457 0_0402_5%
0 EEh - EFh
<35,36> ON/OFFBTN#
* 1 7Eh - 7Fh
U2600
5 +3VALW_TPM
1 VSB 10
GPIO0/XOR_OUT VDD +3VS_TPM
GPIO3/BADD with Internal PH (default) 2 19 PreMP modify 03/07 PVT modify 01/14
6 GPIO1 VDD 24 R699,R700 change to 200 ohm R699, R700 change to 330 ohm
GPIO2/GPX VDD R698,R701 change to 390 ohm R698, R701 change to 560 ohm
0_0402_5% 1 @ 2 R2602 TPM_BADD 9
CLKRUN# 15 GPIO3/BADD 8
<8> CLKRUN#
LED
GPIO4/CLKRUN# TEST
CLKRUN PH 10K to +3VS at PCH side LPC_AD0 26 LED6 +3VALW
<7,36> LPC_AD0 LPC_AD1 LAD0/MISO
23
<7,36> LPC_AD1 LPC_AD2 LAD1/MOSI BATT_BLUE_LED#
20 3 <36> BATT_BLUE_LED# 1 2 1 2
<7,36> LPC_AD2 LPC_AD3 LAD2/SPI_IRQ# NC B
17 12 R699 200_0402_5%
<7,36> LPC_AD3 LAD3 NC PWR_LED#
13
LPCPD# had internal PH NC 14
PWR_LED# <35> BATT_AMB_LED# 3 4 1 2
<36> BATT_AMB_LED#
1
28 NC D
Q17 A
R698 390_0402_5%
CLK_PCI_TPM 21 LPCPD# 2 L2N7002LT1G_SOT23-3
<7> CLK_PCI_TPM LPC_FRAME# LCLK/SCLK <36> PWR_LED
22 G LTST-C295TBKF-CA_AMBER-BLUE
<7,36> LPC_FRAME#
1
XEMC@ XEMC@ THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
KB & TP & TPM Connector & LED
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A5WAH M/B LA-B991P
Date: Friday, October 17, 2014 Sheet 37 of 54
A B C D E
A B C D E
1
40mil 1
J1
JUMP_43X118
2 40mil
4.75V
+VDDA
SPKR+
SPKR-
EMC@1
EMC@1
R2120
R2121
2
2
PBY160808T-121Y-N_2P
PBY160808T-121Y-N_2P
40mil SPK_R+
SPK_R-
1
2
JSPK1
1
@ SPKL+ EMC@1 R2122 2 PBY160808T-121Y-N_2P SPK_L+ 3 2 5
0.1U_0402_16V4Z SPKL- EMC@1 R2123 2 PBY160808T-121Y-N_2P SPK_L- 4 3 G1 6
XEMC@2
(output = 300 mA) 4 G2
3
+PVDD_HDA Reserved for ESD PVT modify 01/16 ACES_88266-04001
SM01000EJ00 3000ma 220ohm@100mhz DCR 0.04 40mil EMI request for solve EMI noise CONN@ GND
L2003 2 1 0.1U_0402_16V4Z 0.1U_0402_16V4Z GND
+VDDA +AVDD1_HDA
HCB2012KF-221T30_0805 1 1 D2003 D2004
1
10U_0603_6.3V6M
C2112
C2113 C2114 MESC5V02BD03_SOT23-3 MESC5V02BD03_SOT23-3
XEMC@ XEMC@
@
20mil
2
2 2
1 1
0.1U_0402_16V4Z R2119 1 @ 2
+VDDA
1
C2117
10U_0603_6.3V6M
GND GND 1 1
1
Place near Pin41 Place near Pin46 0_0603_5%
C2115 C2116 GND GND
@
2
2 2 +MICBIAS2
+3VS_DVDD 0.1U_0402_16V4Z Int. MIC Reserve
2
20mil GNDA
+3VS R2124 1 @ 2 0.1U_0402_16V4Z +3VS_DVDD Place near Pin26 @ R544
2.2K_0402_5%
0_0603_5% 1 1 1 15mil 15mil
C2118 C2119 C2120@ +1.5VS_VDDA 0.1U_0402_16V4Z R2125 1 @ 2 XEMC@ JMIC1
+1.5VS
1
INT_MIC_R 1 2 INT_MIC_R_1 1
1
1
1
C2122
10U_0603_6.3V6M
10U_0603_6.3V6M C2121 0_0603_5% R9 2
2 2 2 0_0603_5% 2
1
0.1U_0402_16V4Z C550
2
2 XEMC@ 3
PVT modify 01/06 220P_0402_50V7K 4 G1
Place near Pin1, 9 GND G2
R2124, R2125, R2119 2
GNDA change to R-short
U2012 Place near Pin40 ACES_88266-02001
41
46
26
40
1
9
CONN@
GND SP020008Y00
DVDD-IO
PVDD1
PVDD2
AVDD1
AVDD2
DVDD
GNDA
Internal MIC Reserve LINE1-L 22
LINE1-R 21 LINE1-L(PORT-C-L) 43 SPKL-
INT_MIC_R 2 @ 1 INT_MIC C770 1 2 LINE2_C_L LINE1-R(PORT-C-R) SPK-OUT-L- 42 SPKL+
R726 1K_0402_5% @ 4.7U_0603_6.3V6K 24 SPK-OUT-L+
GNDA C62 1 2 C769 1 2 LINE2_C_R 23 LINE2-L(PORT-E-L)
LINE2-R(PORT-E-R) SPK-OUT-R+
45 SPKR+ Digital MIC Conn.
XEMC@ 1000P_0402_50V7K @ 4.7U_0603_6.3V6K 44 SPKR-
RING2 17 SPK-OUT-R-
2 40mil SLEEVE 18 MIC2-L(PORT-F-L) /RING2 Slave(reserved)+3VS Main (EA50) 2
Combo MIC MIC2-R(PORT-F-R) /SLEEVE HP_LEFT
32 Fortemedia Solution
+MICBIAS 31 HPOUT-L(PORT-I-L) 33 HP_RIGHT +3VS
+MICBIAS +MICBIAS2_R LINE1-VREFO-L HPOUT-R(PORT-I-R) MIC2
+MICBIAS2 1 @ 2 30 @
R450 0_0402_5% LINE1-VREFO-R 10 HDA_SYNC_AUDIO 6 5 DMIC_DATA
DMIC_DATA SYNC HDA_BITCLK_AUDIO HDA_SYNC_AUDIO <6> MIC1 VDD DATA
2 6 @
DMIC_CLK GPIO0/DMIC-DATA BCLK HDA_BITCLK_AUDIO <6> DMIC_DATA_S DMIC_CLK
3 6 5 2 4
GPIO1/DMIC-CLK 1 XEMC@ 2 1 2 C2123 XEMC@ VDD DATA CS CLK
GND DMIC_CLK
R2126 0_0402_5% 22P_0402_50V8J 2 4 2 R459 1 1 3
PVT modify 12/31 EC_MUTE# 47 5 HDA_SDOUT_AUDIO CS CLK 0_0402_5% ENHANCE GND
ALC283-CG HDA_SDOUT_AUDIO <6>
3
EMI add C2143 EMC@ HDA_RST_AUDIO# 11 PDB SDATA-OUT 8 HDA_SDIN0_AUDIO 1 R2127 2 1 3 EA50@ 2MIC@ S MIC ST MP45DT02TR
RESETB SDATA-IN HDA_SDIN0 <6> ENHANCE GND
C2143 1 2 100P_0402_50V8J 33_0402_5%
2
0_0402_5%
48 S MIC ST MP45DT02TR
0.1U_0402_16V4Z
MONO_IN SPDIF-OUT/GPIO2 +MIC2_VREFO 2 EA50@
R455
12
PCBEEP 0_0402_5%
C2141
Close codec 16
HP_PLUG# R2129 2 1 39.2K_0402_1% SENSE_A 13 MONO-OUT 10U_0603_6.3V6M 2 1 C2124 D2005 R460
SENSE A GND 1
10mil 14 MESC5V02BD03_SOT23-3 D2009
1
SENSE B 29 XEMC@ @ MESC5V02BD03_SOT23-3
1 MIC2-VREFO
37 10U_0603_6.3V6M 2 1 C2126 GNDA XEMC@
1
C2125 35 CBP 7
2.2U_0402_6.3V6M CBN LDO3-CAP 39
2 LDO2-CAP 27 10U_0603_6.3V6M 2 1 C2127 R526 Realtek add request
LDO1-CAP GNDA
+3VS_DVDD 36
CPVDD 1 R2130 2 +MIC2_VREFO
28 CODEC_VREF 100K_0402_5%
10mil Headphone Out
1 @ R2131 2100K_0402_5% 20 VREF
+3VS CPVREF 1 1 1
2.2U_0402_6.3V6M
C2130
@
Realtek add request 15 20K_0402_1% 1 2 R2132 GNDA @
JDREF HPOUT_L_2
0.1U_0402_16V4Z
C2129
10U_0603_6.3V6M
C2131
10U_0603_6.3V6M 2 1 C2128 19 34 CPVEE
GNDA MIC-CAP CPVEE HPOUT_R_2
Close codec
1
2 2 2
TVNST52302AB0_SOT523-3
1
3
4 R2133 R2134
49 DVSS 25 C2132 2.2K_0402_5% 2.2K_0402_5%
Thermal PAD AVSS1
D2007
38 2.2U_0402_6.3V6M DVT modify 12/10
3 AVSS2 2 change to Bead R2149 EMC@ 3
2
BLM15PX330SN1D 0402
ALC283-CG_MQFN48_6X6 XEMC@ SLEEVE_L 1 2 SLEEVE
Place next pin27
1
RING2_L 1 2 RING2
GND
3
GND
GNDA GNDA GND BLM15PX330SN1D 0402
R2150 EMC@
2 2
C2142 C2140
D2008
R2137 AZ5123-02S.R7G 3P C/A SOT23 680P_0402_50V7K 680P_0402_50V7K DVT modify 12/10
47K_0402_5% +3VALW +3VS +3VLP EMC@ EMC@ 1 1 EMC@ change to 680P
2 @ 1 BEEP#_R 1 2 MONO_IN
<36> BEEP#
1
C2133 GND GND
2
RING2_L
100P_0402_50V8J
C2134
4.7K_0402_5%
R2141
R2135/R2136
5
D
G
R2138/R2139,Resistor exchange
Q2003A 6
GNDA S
DMN66D0LDW-7_SOT363-6
+5VS C632
4.7U_0603_10V6K +5VS
1 2
H3 H4 H5 H6 H9 H10 H11 H21 H17 FD1 FD2
H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_6P5
U31
1 8 1 @ @
1
2 EN GND 7
1
+VCC_FAN1 3 VIN GND 6 C413 FIDUCIAL_C40M80 FIDUCIAL_C40M80
2 @ 1 4 VOUT GND 5 0.1U_0402_16V4Z
<36> EN_DFAN1 VSET GND 2
EMC@ FD3 FD4
R515 NCT3942S SOP 8P @ @ @ @ @ @ @ @ @
1
0_0402_5%
C626 H13 H14 H15 H16 H20 H7 @ @
1
0.1U_0402_16V4Z DVT modify 12/04 H_4P0 H_4P0 H_4P0 H_4P0 H_4P0 H_3P0
2 @ ESD request add 0.1u to 5VS FIDUCIAL_C40M80 FIDUCIAL_C40M80
1
C627
4.7U_0603_10V6K
+3VS 1 2 @ @ @ @ @ @
@ C631 H27
1
1000P_0402_50V7K H_3P7
R516 1 2
10K_0402_5%
40mil
1
JFAN1
2
+VCC_FAN1 1
2 1 4
<36> FAN_SPEED1 2 GND @
3 5
3 GND
1
C630
1000P_0402_50V7K ACES_88231-03041 H23 H25
XEMC@ CONN@ H_3P5X3P0N H_3P0N
2
SP020020710
@ @
1
G-Sensor for BA50
+3VS
1
R518 +3VS
10K_0402_5%
BA@ U2 BA@
1 C633 1 2 10U_0603_6.3V6M
2
8 Vdd_IO BA@
4 CS 14 C628 1 2 0.1U_0402_16V4Z
<7,15,16> D_CK_SCLK SCLSPC Vdd
<7,15,16> D_CK_SDATA 6
7 SDA/SDI/SDO
R519 1 @ 2 10K_0402_5% SDO/SA0 11 G_SEN_INT
+3VS INT1 G_SEN_INT <8>
R520 1 BA@ 2 10K_0402_5% 16 9
15 ADC1 INT2
13 ADC2 10
ADC3 RES
2
3 NC 5
NC GND 12
GND
LIS3DHTR_LGA16_3X3
BA@
LIS3DH
SA0 ->0, Address is 0011 000 (0x30h)
SA0 ->1, Address is 0011 001 (0x32h)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FAN & Screw Hole & G-Sensor
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A5WAH M/B LA-B991P
Date: Friday, October 17, 2014 Sheet 39 of 54
A B C D E
10U_0603_6.3V6M
0.1U_0402_16V4Z 1 1 1 22U_0805_6.3V6M
1 5VS_ON 1
2 @ 1 5 10 2 1 EMC@
ON2 CT2
C92
R926 330P_0402_50V7K C39 C64
0_0402_5% C979 +5VALW 6 9 C967 @ J37 EMC@ EMC@
1 2 EMC@ 7 VIN2 VOUT2 8 +5VS_OUT 1 2 2 2 2
VIN2 VOUT2 1 2 +5VS
0.1U_0402_16V4Z 22U_0805_6.3V6M
Reserved for ESD 15 JUMP_43X118 22U_0805_6.3V6M
GPAD
TPS22966DPUR_SON14_2X3
+5VALW
+1.35V +5VALW
2
+0.675VS +1.05VS_VTT
2
R552
2
100K_0402_5% R573 R554
2
@ 470_0603_5% 100K_0402_5%
R566 R567 @ @
1
470_0603_5% 470_0603_5%
1
SUSP @ @
1
+1.35V_R SYSON#
2
+0.675VS_R
3
+1.05VS_VTT_R
1
@ D
1
2 D D
<36,45,46,47> SUSP#
G SUSP 2 2 SUSP SYSON# 2 5 SYSON
SYSON <36,45>
1
S G G Q40A Q40B
3
R555 Q29 Q36 S S Q37 DMN66D0LDW-7_SOT363-6 DMN66D0LDW-7_SOT363-6
4
10K_0402_5% L2N7002LT1G_SOT23-3 L2N7002LT1G_SOT23-3 L2N7002LT1G_SOT23-3 @ @
@ @ @
2 2
+1.05VS_VTT to +1.05VSDGPU
160mil
+1.05VS_VTT +1.05VSDGPU +VGA_CORE
U40
AO4478L_SO8
2
8 1
+3VS to +3VSDGPU_AON for GPU 7 2 R572
10U_0603_6.3V6M
C613
6 3 47_0603_5%
C617
10U_0603_6.3V6M
0.1U_0603_25V7K
C683
5 1 @
1
VGA@ VGA@ +VGA_CORE_R
1
+3VS +3VSDGPU_AON VGA@ VGA@ VGA@ R514
4
U12 VGA@ 100mil(1.5A) 47_0402_5% L2N7002LT1G_SOT23-3
1
2 D
1 @
5 OUT DGPU_PWR_EN# 2
2
IN +1.05VSDGPU_R G
2
2 10mil S
3
3
3 4 GND C621 Q35 3
IN VGA@
10mil R469 1 VGA@ 2 47K_0402_5% 1.05VSDGPU_GATE
2 1 4.7U_0603_6.3V6K B+
C620 3
4.7U_0603_6.3V6K EN VGA@ 5 VGA_PWROK#
1
6
VGA@ G5243T11U_SOT23-5 C622 Q1007B
1 0.1U_0603_25V7K DMN66D0LDW-7_SOT363-6
4
VGA@
VGA_PWROK# 2 2
Q1007A
DGPU_PWR_EN DMN66D0LDW-7_SOT363-6 VGA@
1
+3VSDGPU_AON +3VSDGPU_MAIN
@ J14
1 2 +5VALW +1.5VSDGPU
1 2 DVT modify 11/20
JUMP_43X79 +5VALW +3VLP +5VALW change to +3VLP
2
@
R998 R571
2
1
+3VS to +3VSDGPU_MAIN for GC6-2.0 1.5VS_DGPU_PWR_EN# +1.5VSDGPU_R
1
DGPU_PWR_EN# VGA_PWROK#
6
+3VS +3VSDGPU_MAIN L2N7002LT1G_SOT23-3 L2N7002LT1G_SOT23-3
1
U14 @ D D VGA@
1 2 2 1.5VS_DGPU_PWR_EN 5 2 1.5VS_DGPU_PWR_EN#
OUT <7,8,9,51> DGPU_PWR_EN VGA_PWROK <17,51> <17,50> 1.5VS_DGPU_PWR_EN
5 100mil(1.5A) G G Q45A
2
IN S S @ Q45B DMN66D0LDW-7_SOT363-6
2
3
1
2
1
GC6@ EN
1
1U_0402_6.3V6K G5243T11U_SOT23-5
1 GC6@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC Interface
3VSDGPU_MAIN_EN From GPU AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A5WAH M/B LA-B991P
Date: Friday, October 17, 2014 Sheet 40 of 54
A B C D E
A B C D
www.laptopblue.vn
+5VS
1 VIN 1
1
PC101 9012@
GND @ESD@ EMI@ PC102 EMI@ PC103 PR102 9012@
0.1U_0603_25V7K 100P_0603_50V8 1000P_0603_50V7K <4,36> H_PROCHOT# 47K_0402_1% PR103
2
2
10K_0402_1%
9012@
2
8
PC104
6
D 3
9012@ 0.022U_0402_16V7K
P
+ BATT_TEMP <36,42>
2 2 1 1
PQ101A G O 2
-
G
DMN66D0LDW-7_SOT363-6 PU101A
1
S 9012@ LM393DR_SO8
4
PD101 9012@ 9012@
1
LL4148_LL34-2 PR101
1
1.5M_0402_5% 9012@ 9012@
PC105 PR104
2
100P_0402_50V8J 100K_0402_1%
2
1
9012@
2
PR105 2
H_PROCHOT# 47K_0402_1% 9012@
9012@ PU101B
8
PC106 LM393DR_SO8
3
D 5
9012@ 0.022U_0402_16V7K
P
5 2 1 7 +
PQ101B G O 6
- ACIN <8,36,43>
G
DMN66D0LDW-7_SOT363-6 9012@
1
S
4
PD104 9012@
LL4148_LL34-2 PR106
1.5M_0402_5%
2
3 3
@ PR111
0_0402_5%
1 2
+3VLP +CHGRTC
- PBJ101 @ + PR112
560_0603_5%
PR113
560_0603_5%
2 1 1 2 1 2
+RTCBATT
ML1220T13RE
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DCIN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, October 17, 2014 Sheet 41 of 54
A B C D
A B C D
www.laptopblue.vn +3VLP
1
@ PJP201
OCTEK_BTJ-08KEAB_8P-T @ PC202
1
10 0.1U_0603_25V7K
2
GND 9
1
GND 8 @ PR204 @ PR205
1
2
6 5 PR208 100_0402_1%
5 4
1
EC_SMCK 2 1 @ PU201
4 3 EC_SMB_CK1 <36,43> 1 8
@ PR206
3 2 TH 2 1 100K_0402_1% VCC TMSNS1
2 1 +3VLP
PR201 2 7 2 1
1 6.49K_0402_1% GND RHYST1
1
@ PR211 1 2 MAINPWON 3 6 @ PR207
BATT_TEMP <36,41> OT1 TMSNS2
0_0402_5% PR210 47K_0402_1%
BI 1 2 1K_0402_1% 4 5 @ PH201
OT2 RHYST2 100K_0402_1%_NCP15WF104F03RC
G718TM1U_SOT23-8
2
EMI@ PL201
HCB2012KF-121T50_0805
BATT_S1 1 2 BATT+ 2013/10/28 update PH201 chang
EMI@ PL202
HCB2012KF-121T50_0805 Common part SL200002H00
1 2
1
EMI@ PC201
1000P_0402_50V7K
2 2
1
ESD@ PC204 HSW@ 18.2K_0402_1%
Connect to ENE9022 pin64 AD1. 330P_0402_50V7K PR216 65W@
16.9K_0402_1% PR202
1 2 22.6K_0402_1%
Battery is 3-cell design.
2
@9022@
1
B+=9V PR230
80.6K_0402_1%
<36> VCIN0_PH
@9022@ PR227
PR229 30K_0402_1%
2
@9022@ 0_0402_5%
<36,44> MAINPWON
1 2 VCIN1_PROCHOT <36>
1 2
VCIN1_BATT_DROP <36> @65W@ PR223
1
54.9K_0402_1%
PH202 1 2 H_PROCHOT#_EC <36>
1
100K_0402_1%_NCP15WF104F03RC
2
2
0.1U_0402_25V6 10K_0402_1% T201
1
T202
Common part SL200002H00
1
1
PR203
1
0_0402_5%
1_0402_1%
PR225
PR226
10K_0402_1%
2
4 4
2
For 40W adapter==>action 52W , Recovery 40W
2
<36> ECAGND
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2013/10/01 Deciphered Date 2014/05/24 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BATTERY CONN / OTP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, October 17, 2014 Sheet 42 of 54
A B C D
A B C D
Vgs = 20V
www.laptopblue.vn
2013/10/14
1
2
PQ301 D
Vds = 60V PR303 10m ohm chang -->20m ohm B+
G Id = 250mA SD00000S120
S 2N7002KW _SOT323-3
3
PR302
PR301
1 2 1 2
1M_0402_5% 3M_0402_5% 2014/01/21 update PL301 change
1
VIN
P1 P2
1 1 8 PR303 EMI@ PL301 CHG_B+
2 2 7 0.02_1206_1% 1UH +-30% 2.8A 8 1
5 3 3 6 1 4 1 2 7 2
5 Isat: 4A 6 3
2200P_0402_25V7K
10U_0805_25V6K
10U_0805_25V6K
2 3 5
2200P_0402_50V7K
0.1U_0402_25V6
DCR: 27mohm
0.1U_0402_25V6
4
@EMI@PC306
1
1
PC303
PC304
EMI@ PC305
PQ302 0_0402_5% PQ303
0.01U_0402_50V7K
PC301
@ PR304
4
1
1
AON6414AL_DFN8-5 AO4406AL_SO8 VIN PQ304
PC302
PC307
AO4406AL_SO8
2
2
VF = 0.5V
2
2
3
2
PD301
BQ24725A_ACDRV_1
BAS40CW _SOT323-3
0.1U_0402_25V6
BQ24725A_BATDRV 1 2BQ24725A_BATDRV_1
0.1U_0402_25V6
Rds(on) = 30mohm max
1
1
PC308
PR305
PC310
Vgs = 20V
1 1
1 2
10_1206_1%
PC311 4.12K_0603_1%
0.047U_0402_25V7K Vds = 30V
PR306
2
PC309 1 2 ID = 7A (Ta=70C)
0.1U_0402_25V6 2013/11/29 update PL302 change
VF = 0.37V Common part SH00000YB00
5
2.2_0603_5%
AON7408L_DFN8-5
PR307
PD302
BQ24725A_VCC2
RB751V-40_SOD323-2 Support max charge 3.5A
PR308 7*7*3
BQ24725A_ACP
Power loss: 0.245W
PQ305
0_0402_5%
BQ24725A_REGN
BQ24725A_BST2
2
DH_CHG 1 2 4 CSR rating: 1W
BQ24725A_LX
VSRP-VSRN spec < 81.28mV
4.12K_0603_1%
4.12K_0603_1%
2 2
1
PC312 BATT+
PR309
PR310
DH_CHG
1 2 PL302
10UH_PCMB063T-100MS_4A_20% PR311
3
2
1
1U_0603_25V6K 1 2 0.01_1206_1%
BQ24725A_ACN
BQ24725A_LX 1 2 CHG1 4
2
PC313
5
1U_0603_25V6K 2 3
20
19
18
17
16
PU301
AON7408L_DFN8-5
CSON1
CSOP1
1
4.7_1206_5%
VCC
PHASE
HIDRV
BTST
REGN
10U_0805_25V6K
10U_0805_25V6K
@EMI@
PR312
21
PAD
0.1U_0402_25V6
0.1U_0402_25V6
PC314
PC315
1
1
DL_CHG
PQ306
1 15 4
ACN LODRV
PC316
PC317
2
2
2 14
680P_0402_50V7K
ACP GND PR313
3
2
1
2
1
@EMI@
BQ24735RGRR_QFN20_3P5X3P5 10_0603_1%
PC318
BQ24725A_CMSRC 3 13 SRP1 2 CSOP1
CMSRC SRP
1
PR314
2
6.8_0603_1%
BQ24725A_ACDRV 4 12 SRN1 2 CSON1
2
ACDRV SRN PC319
0.1U_0603_16V7K
1 2 5 11 BQ24725A_BATDRV
+3VLP ACOK BATDRV **Design Notes**
PR315 100K_0402_1%
Module model information
ACDET
#For 65 /90W system, 3S1P/3S2P battery
IOUT
SDA
SCL
ILIM
Maximum Charging current 3.5A
BQ24735A_V1.mdd Battery discharge power 55W.
<8,36,41> ACIN #Register Setting
6
10
+3VALW
1. 0X12 bit8 set 0 (default 1) to disable IFAULT HI if add ISN choke
3
BQ24735A_V2.mdd BQ24725A_ILIM 2. 0X12 bit3 set 1 (default 0) to enable turbo boost function 3
BQ24725A_ACDET
1 2
BQ24725A_IOUT
100K_0402_1%
316K_0402_1%
0.01U_0402_25V7K
#Circuit Design
PC320
PR317
1. ACOK,ILIM pull high voltage need base on 3/5V enable control
1
PR318
422K_0402_1% 2. Use 10X10 choke and 3X3 H/L side MOSFET
1 2 Charge current 3.5A
VIN
2
Power loss : 1.82W
2
66.5K_0402_1%
1
PC322
PR319
1 2 EC_SMB_DA1 <36,42>
PC324
4. CHGOCP : 3/4.5/6A based on current current setting
2
@ PR320
2
4
Close EC chip 4
Vin Dectector
Min. Typ Max.
L-->H 17.16V 17.63V 18.12V
H-->L 16.76V 17.22V 17.70V
Security Classification Compal Secret Data Compal Electronics, Inc.
VILIM = 20*ILIM*Rsr Issued Date 2013/10/01 Deciphered Date 2014/05/24 Title
ILIM = 3.3*100/(100+107)/20/0.02
= 3.986 A THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CHARGER
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Common Circuit 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, October 17, 2014 Sheet 43 of 54
A B C D
A B C D E
1 1
1
150K_0402_1%
PU401 PC402 PR403
B+ 3V5V_EN
PR404
EMI@ PL401 7 1 0.01U_0402_25V7K 1K_0402_5%
HCB2012KF-121T50_0805 IN EN1 1 2 1 2
3V_VIN 3V_FB
2200P_0402_50V7K
1 2 8 3
IN EN2 PR401 PC403
2
BST_3V
10U_0805_25V6K
10U_0805_25V6K
@EMI@ PC401
EMI@ PC404
0.1U_0402_25V6
6 1 2 1 2
BS
1
1
PC406
2.2_0603_5%
PC405
0.1U_0603_25V7K
PL402
2
2
10 LX_3V 1 2
@ LX +3VALWP
9 4 1.5UH_PCMB053T-1R5MS_6A_20%
GND OUT
@EMI@
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
PR405
1
1
680P_0603_50V7K 4.7_1206_5%
2 5
+3VALWP PG LDO +3VLP
PC407
PC408
PC409
PC410
1
SY8208BQNC_QFN10_3X3
2
PC411
1 3V_SN
4.7U_0603_6.3V6M
2
1
@EMI@
PC412
3.3V LDO 150mA~300mA
2
2
2 2
Vout is 3.234V~3.366V Ipeak=4.65A
<36> SPOK
Imax=3.25A
TDC=6A Iocp=10A
@ PJ401
+3VALWP 1 2 +3VALW
1 2
JUMP_43X118
B+ EMI@ PL403
HCB2012KF-121T50_0805
1 2 5V_VIN
@ PJ402
+5VALWP 1 2 +5VALW
1 2
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
5V_FB
PC414
PC415
EMI@ PC417
@EMI@ PC418
3 PR407 PC416
EN2 2.2_0603_5% 0.1U_0603_25V7K
6 BST_5V 1 2 1 2
2
BS
5*5*3
@
PL404
9 10 LX_5V 1 2
GND LX +5VALWP
VCC_3V 5 4 1.5UH_PCMB053T-1R5MS_6A_20% @ @
VCC OUT
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
PR408
680P_0603_50V7K 4.7_1206_5%
1
@EMI@
SPOK 2 7
PG LDO VL
1
PC419
PC420
PC421
PC422
PC423
PC428
PC427
3
4.7U_0603_6.3V6M
3
SY8208CQNC_QFN10_3X3
2
1 5V_SN
2
2
1
PC424
4.7U_0603_6.3V6M
2
PC425
@EMI@
Vout is 4.998V~5.202V
TDC=6A Ipeak=9A
5V LDO 150mA~300mA Imax=6.25A
Iocp=10A
PR409
2.2K_0402_5%
1 2
<36> EC_ON @ PR410
0_0402_5%
1 2
<36,42> MAINPWON
3V5V_EN
1M_0402_1%
4.7U_0402_6.3V6M
1
PC426
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+3VALW/+5VALW
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, October 17, 2014 Sheet 44 of 54
A B C D E
5 4 3 2 1
www.laptopblue.vn
Module model information
RT8207M_V1.mdd For Single layer
RT8207M_V2.mdd For Dual layer
D D
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
+1.35VP
1
1
@EMI@ PC502
EMI@ PC503
PC504
PC505
DH_1.35V +0.675VSP
2
2
SW _1.35V
10U_0805_6.3V6K
10U_0805_6.3V6K
1
1
PC501
PC506
PC507
5
0.1U_0603_25V7K
16
17
18
19
20
2
C
2013/10/20 update PU501 C
2
VLDOIN
PHASE
UGATE
BOOT
VTT
Setting OCP__PR502-->6.65K 21
PQ501 PAD
AON7408L_DFN8-5 4 DL_1.35V 15 1
LGATE VTTGND
2013/10/28 update PL502 chang
1.364V 1.1%Common part 7*7*3 SH00000YE00 14 2
PL502 PR502 PGND VTTSNS
1
2
3
1UH_PCMB063T-1R0MS_12A_20% 6.65K_0402_1%
1 2 1 2 CS_1.35V 13 3
+1.35VP PC508 CS RT8207MZQW _W QFN20_3X3 GND
1
1U_0603_10V6K
5
1 2 12 4 VTTREF_1.35V
H=4.5 @EMI@ PR503 PR504 VDDP VTTREF
SF000002Z00 4.7_1206_5% 5.1_0603_5%
VDD_1.35V
PQ502 1 2 11 5
330U_2.5V_M
1
1 2
1
PGOOD
AON7506_DFN33-8-5
+ 4 PC510
PC509
ESR=15m ohm
TON
1
@EMI@ PC512 0.033U_0402_16V7K
FB
S5
S3
2
2013/10/28 update PC509 chang 680P_0402_50V7K PC513
+5VALW
2
2 1U_0603_10V6K
Common part SF000006S00 H4.5
10
6
1
2
3
FB_1.35V
EN_0.675VSP
TON_1.35V
EN_1.35V
PR506
8.2K_0402_1%
2013/10/14 update PR507 1 2 +1.35VP
887K_0402_1%
B PQ502__AON7702A EOL change 1.35V_B+ 1 2 B
-->AON7506_SB000010A00
1
Mode Level +0.75VSP VTTREF_1.5V @ PR509 PR508
0_0402_5% 10K_0402_1%
S5 L off off 1 2
<36,40> SYSON
2
S3 L off on
S0 H on on
1
MOSFET: 3x3 DFN ESD@ PC514
0.1U_0402_16V4Z
Note: S3 - sleep ; S5 - power off H/S Rds(on): 27mohm(Typ), 34mohm(Max)
2
L/S Rds(on): 22mohm(Typ), 13.5mohm(Max) @ PR510
0_0402_5%
Choke: 7x7x3 1 2
<36,40,46,47> SUSP# PR511
Rdc=8.3mohm(Typ), 10mohm(Max) 0_0402_5% @ PJ501
1 2 +1.35VP 1 2 +1.35V
<15> DDR_VTT_PG_CTRL 1 2
Switching Frequency: 285kHz
1
HSW _ESD@ JUMP_43X118
Ipeak=5.4A PC515 @ PJ502
Delta I =4.4A 0.1U_0402_16V4Z 1 2
2
1 2
Iocp=9.15~6.58A
OVP: 110%~120% JUMP_43X118
VFB=0.75V, Vout=1.364V @ PJ503
A5WAH PVT: ESD request add 0.1u 1 2
+0.675VSP 1 2 +0.675VS
A
JUMP_43X39 A
www.laptopblue.vn
D D
1
@ PC602
1M_0402_1%
0.22U_0402_10V6K
2
PR603
2
@EMI@ PR604 @EMI@ PC603
4.7_1206_5% 680P_0603_50V7K
EMI@ PL601 1 2SNB_1.05V 1 2
HCB2012KF-121T50_0805 PU601
B+_1.05V
B+ 1 2 8
IN EN
1 PR601
0_0603_5%
PC601
0.1U_0603_25V7K
TDC 8A
10U_0805_25V6K
10U_0805_25V6K
6 BST_1.05V
1 2 1 2 PL602
1.062V 1.1%
0.1U_0402_25V6
2200P_0402_50V7K
BS
1
1UH_PCMB063T-1R0MS_12A_20%
PC606
PC604
PC607
LDO_3V LX_1.05V
9 10 1 2
+1.05VSP
EMI@ PC605
GND LX
2
15.4K_0402_1%
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1
1
@EMI@
330P_0402_50V7K
1
1
4
PR606
@ PR605 FB
PC608
PC609
PC610
PC611
PC612
PC615
0_0402_5%
ILMT_1.05V3 7
Rup
+3VALW
2
ILMT BYP
2
2
4.7U_0603_6.3V6K
ILMT_1.05V VCCST_PWRGD LDO_3V
+3VS 1 2 2 5
4.7U_0603_6.3V6K
PG LDO
1
PR608 @
PC614
1
10K_0402_5% SY8208DQNC_QFN10_3X3
PC613
FB = 0.6V
2
1
PR607 @
2
0_0402_5%
PR609
Rdown
2
20K_0402_1%
2
<11,36> VCCST_PWRGD +1.05VSP PJ601
Pin 7 BYP is for CS. 1 2
1 2 +1.05VS_VTT
B
The current limit is set to 8A, 12A or 16A when this pin Common NB can delete +3VALW and PC15 B
JUMP_43X118 @
is pull low, floating or pull high
VFB=0.6V
Vout=0.6V* (1+Rup/Rdown)
Vout=1.05V
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.05VSP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, October 17, 2014 Sheet 46 of 54
5 4 3 2 1
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+3VS +5VALW
1
D D
1
@ PJ701 PC702
1
JUMP_43X39 1U_0402_6.3V6K
2
2
2
PC703 PU701
1
4.7U_0805_6.3V6K APL5930KAI-TRG_SO8
6
1.507V 0.53%
5 VCNTL 3
2
PR701 9 VIN VOUT 4 @ PJ702
100K_0402_5% VIN VOUT
+1.5VSP +1.5VSP 1
1 2
2 +1.5VS
20K_0402_1%
1 2 8
<36,40,45,46> SUSP# 7 EN
1
2 JUMP_43X39
GND
POK FB
PR703
PC704
0.1U_0402_16V7K
0.01U_0402_25V7K
Rup
1
PC701
PR704 PC705
2
47K_0402_5% 22U_0603_6.3V6M
2
2
1
PR705
22.6K_0402_1%
Rdown
2
C C
Vout=0.8V* (1+Rup/Rdown)
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.5VSP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, October 17, 2014 Sheet 47 of 54
5 4 3 2 1
5 4 3 2 1
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Base on BDW PDDG Rev_0_73 H-side MOS: MDV1525URH
Module model information: Rds(on):
ISL95813 (for 15W & 28W CPU) 15W 28W <10.1mohm@Vgs=10V
<14.0mohm@Vgs=4.5V
Id :24A@Vgs=10V
TDC 14A TDC 19A
VR_SVID_ALRT#
fsw=700KHz CPU_B+
VR_SVID_DATA
1 2
VR_SVID_CLK
2200P_0402_50V7K
0.01U_0402_50V7K
<11> VR_ON
10U_0805_25V6K
10U_0805_25V6K
68U_25V_M_R0.36
28W@ PR804 1
EMI@ PC805
EMI@ PC806
PC807
113K_0402_1% Height 8 mm
PRGM1
1
PC804
+
AON7518_DFN8-5
PR805
100u_SF000000I80
1
PC803
1.91K_0402_1%
PQ801
1 2
2
PR806 2 Height 6 mm
2
0_0603_5%
21
20
19
18
17
PU801 1 2 4
68u_SF000000W00
<8,11> VGATE
SCLK
SDA
PAD
ALERT#
PRGM1
PC808 VR_ON 1 16
2014/01/21 update PL802 change PL802
LAGTE
Common part SH000011H00
3
2
1
1000P_0402_50V7K VR_ON LGATE
1 2 0.22UH 20% FDUE0640J -H 25A
2 15 PHASE 1 4
PR807 PGOOD PHASE +CPU_CORE
4.7_1206_5%
@EMI@ PR808
121K_0402_1% 2 3
1
1 2 IMON 3 14 UAGTE
IMON UGATE PR801 PC801 28W@
5
AON6554_DFN5X6-8-5
AON6554_DFN5X6-8-5
ISL95813HRZ-T_QFN20_3X4 2.2_0603_5% 0.22U_0603_16V7K PQ803 PQ802
1
VR_HOT_1# 4 13 BOOT 1 2 1 2
<36> VR_HOT# VR_HOT# BOOT
PH802 PR809
2
47P_0402_50V8J
680P_0603_50V7K
PC809
@EMI@ PC810
4 4 TDC 19A
OTP Setting: 100C active
2
1
5.62K_0402_1% MAX 40A
Pin5 (NTC) voltage <0.88V, Protect PR811 COMP 6 11 PRGM2
OCP 48A
2
COMP PRGM2
1
Pin5 (NTC) voltage >0.92v, recovery 27.4K_0402_1%
ISUMN
ISUMP
Loadline=-2.0mv/A
2
1 2 PC811
RTN
3
2
1
3
2
1
124K_0402_1% 0.1U_0402_25V6
FB
2
1
PR812
10
FB
ISUMN
ISUMP
PR813
Note:
33P_0402_50V8J PR812=124K
1
=>Slew rate=53mV/us
6800P_0402_25V7K
2K_0402_1%
10_0402_1%
PC812
Vboot = 1.7V
2
@ PR815
15W@
2
PR814
1
1.27K_0402_1%
PC813
PR816
2
1
390P_0402_50V7K
4.99M_0402_1%
1
1
330P_0402_50V7K
PR818
2
1
@ PC815
PR817
2.61K_0402_1%
RC Match
2
PC814
Droop
2
2
15W@
2
1
28W@ PR816
1.58K_0402_1% PC816 PC817 PR819
@ 0.033U_0402_16V7K 0.1U_0402_16V4Z 11K_0402_1%
2
1
<11> VCC_SENSE
28W@ PC816 PH801
28W@ PR820 OCP Setting 0.022U_0402_16V7K 10KB_0402_5%_ERTJ0ER103J
499_0402_1%
@ PC818
15W: 38A
28W: 48A
2
0.082U_0402_16V7K
1 2
2013/10/28 update PH801 chang
@ PC819
330P_0402_50V7K
Common part SL200002G00
1
PR820 15W@
1 2
A A
2
PC820 392_0402_1%
1 2
0.01U_0402_50V7K
@ PC821 @ PR821
1 2 1 2
<11> VSS_SENSE 123
4700P_0402_25V7K 1.5K_0402_1% Title
5 4 3 2 1
5 4 3 2 1
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PWR Rule
需需需 需 需 SP EC.
Modify 8/6.
D D
+CPU_CORE
30 X 22uF 0805
2012/10/23
22U_0603_6.3V6M
PC901
22U_0603_6.3V6M
PC902
22U_0603_6.3V6M
PC903
22U_0603_6.3V6M
PC904
1
1
check the output cap Qty!!!
2012/10/24
23 pcs 22uF and reserve 7 pcs
2
2
2013/01/14
22uF*17 unpop:22uF*3
22U_0603_6.3V6M
PC909
20130828
22U_0603_6.3V6M
PC910
15W: 22uF*14
1
1
28W: 22uF*16
2
2
@ @
C C
22U_0603_6.3V6M
PC911
22U_0603_6.3V6M
PC912
22U_0603_6.3V6M
PC913
22U_0603_6.3V6M
PC914
1
28W@
2
@ @
22U_0603_6.3V6M
PC916 28W@
22U_0603_6.3V6M
PC917
22U_0603_6.3V6M
PC918
22U_0603_6.3V6M
PC919
1
1
2
B B
220U_D2_2.5VY_R9M
1
+
PC921
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU_CORE_CAP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2 Date: Friday, October 17, 2014 1 Sheet 49 of 54
5 4 3 2 1
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D D
VGA@
PR1002
0_0402_5%
1 2 1.5VS_DGPU_PW R_EN <17,40>
1
VGA@
@
PC1002
1M_0402_1%
0.22U_0402_10V6K
2
PR1003
@
PJ1001
C 1 2 C
2
1 2
JUMP_43X39 @VGA_EMI@
@VGA_EMI@
PR1004 PC1006
@ 4.7_1206_5% 680P_0603_50V7K
PL1001 VGA@ 1 2SNB_1.5VSDGPUP
1 2
HCB2012KF-121T50_0805 PU1001 VGA@ VGA@
1 2 B+_1.5VSDGPUP8 1 PR1001 PC1001
GPU_B+ IN EN TDC 8A
0_0603_5% 0.1U_0603_25V7K
10U_0805_25V6K
10U_0805_25V6K
6 BST_1.5VSDGPUP
1 2 1 2 PL1002 VGA@
1.365V 1.1%
2200P_0402_50V7K
0.1U_0402_25V6
BS
1
1UH_PCMB063T-1R0MS_12A_20%
@VGA_EMI@ PC1004
PC1005
PC1007
LX_1.5VSDGPUP
9 10 1 2
+1.5VSDGPUP
VGA_EMI@ PC1003
GND LX
2
25.5K_0402_1%
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1
330P_0402_50V7K
Common part 7*7*3 SH00000YE00
1
VGA@
VGA@
PR1005
FB
VGA@ PC1008
VGA@ PC1009
VGA@ PC1010
VGA@ PC1011
VGA@ PC1012
VGA@ PC1013
@VGA@ PC1016
@VGA@ PC1017
ILMT_1.5VSDGPUP Rup
VGA@
3 7
+3VALW
2
ILMT BYP
4.7U_0603_6.3V6K
2
2 5 LDO_3V_1.5VSDGPUP
PG LDO
VGA@ PC1015
4.7U_0603_6.3V6K
1
SY8208DQNC_QFN10_3X3
VGA@ PC1014
FB = 0.6V
1
2
@
PR1006 PJ1002
LDO_3V_1.5VSDGPUP Rdown 20K_0402_1% +1.5VSDGPUP 1 2 +1.5VSDGPU
1 2
2
B B
VGA@
JUMP_43X118
1
ILMT_1.5VSDGPUP
Vout=0.6V* (1+Rup/Rdown)
1
PR1008
0_0402_5%
Vout=1.365V
2
The current limit is set to 8A, 12A or 16A when this pin
is pull low, floating or pull high
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.5VSDGPUP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, October 17, 2014 Sheet 50 of 54
5 4 3 2 1
A B C D
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Vboot=Vvref*Rref2/(Rref1+Rref2+Rboot) Current Limit threshold setting Different VGA Chip (different EDP-Peak Current) need select different solution
Rocset= (Ivalley * Rds(on) + 40 mV) / 10uA
Rt=Rrefadj // (Rboot+Rref2)
Module model information:
Vmin= Vvref*[Rref2/(Rref2+Rboot)]*[Rt/(Rref1+Rt)] I_ripple=(19-0.9)*0.9/ VGA Chip N14P-GV N14P-GV2 N14M-GS N14M-LP N14P-LP N14P-GE N14P-GS N14P-GT N15S-GT N15V-GM
RT8813A_V1A for IC module (304.89Khz*0.36u*19)=7.811A
RT8813A_V1B for SW module Vmax=Vvref*Rref2/[(Rref1//Rrefadj)+Rboot+Rref2]
OpenVReg Configurations Config B Config B Config B Config B Config B Config B Config B Config B Config B Config C
Vout=Vmin+N*Vstep OCP=54A/2=27A per phase
Ivalley=27A-7.811A/2=23.1A
Vstep=(Vmax-Vmin)/Nmax Rated TDP Power at Tj=102C 18W 25W 18W 13W 18.9W 25W 25.6W 35.5W 18W 18.16W
PWM-VID Spec and component Values Boosted GPU Total at Tj=102C 25W 32W 25W 20W 23W N/A 30W 40W 25W 24.72W
H-side MOS:AON6552 L-side MOS:AON6554
Rds(on): Rds(on):
PWM-VID Spec Config B Config C Config D 5.6mohm@Vgs=10V 3.2mohm@Vgs=10V EDP-Continuous at Tj=102C 24A 32A 26A 22A 25A 27A 38A 45A 31A 29.2A
1 1
VGA@
Rboot Rrefadj
0.1U_0402_25V6
10U_0805_25V6K
10U_0805_25V6K
2200P_0402_50V7K
2
1
2K_0402_5% 20K_0402_1% 1 2 PSI <17> U2_BOOT1
1 2 VGA@
PC1216
VGA_EMI@ PC1204
VGA@ PC1205
VGA@ PC1206
1 2 1 2
GM@ PR1209 GL@ PR1209 0_0402_1% PQ1201
1 +VGA_CORE
2
AON6552_DFN5X6-8-5
5
6.2K_0402_1% 24K_0402_1% @VGA@ PR1210 Pull high on HW side
GT@ PR1209
18K_0402_1%
EDP-Continuous 31A
1
@VGA_EMI@
2700P_0402_50V7K
0.01U_0402_16V7K
3VSDGPU_MAIN_EN <17,40> 2
GPU_VID
Rref2 24.9K_0402_1%
GT@ PC1209
1 2 U2_UGATE1 1 2 4
0.1U_0402_25V6
2
1
2 0_0603_5%
VGA@
@VGA@
GPU_REFADJ
GT@ PR1212
PC1210
U2_BOOT1
1
U2_UGATE1
GM@ PR1212 GL@ PR1212 C Reserve Location
0_0402_5%
GPU_EN
3
2
1
GM@ PC1209 0.22UH 20% FDUE0640J -H 25A +VGA_CORE
5600P_0402_25V7K 1 4
2
GPU_FBRTN U2_PHASE1
2 3
VGA@ VGA@
6
5
PU1201 PQ1202
AON6554_DFN5X6-8-5
1
VGA@ PR1201 @VGA_EMI@
UGATE1
BOOT1
VID
PSI
EN
REFADJ
2
<19> VSSSENSE_VGA 0_0402_1% @VGA@ GPU_VREF 8 23 U2_LGATE1
1 2 PC1201 VREF LGATE1 @VGA_EMI@
1
2 0.01UF_0402_25V7K GPU_TON 9 22 U2_PWM3 U2_PWM3 PC1211
13K_0402_1%
TON GND/PWM3 GM@ PR1216 GL@ PR1216 680P_0603_50V7K
GT@ PR1216
3
2
1
1 2 GPU_FBRTN 10 21 10.2K_0402_1% 10.2K_0402_1%
2
RGND PVCC
Rocset
1
11 20 U2_LGATE2
TALERT/ISEN2
2
100_0402_1% PC1212 VSNS LAGTE2
TSNS/ISEN3
VCC/ISNE1
3
47P_0402_50V8J GPU_COMP 12 19 U2_PHASE2 3
2
SS PHASE2
UGATE2
PGOOD
@VGA@ PR1217
BOOT2
1 2 GPU_FB
GND
13
14
15
16
17
18
1 2 Css 0.01U_0402_16V7K
+VGA_CORE 1 2
VGA@ PR1218 GPU_B+
GPU_DSBL/ISEN1
GPU_TSNS/ISEN3
100_0402_1%
GPU_HOT#
U2_UGATE2
VGA_PWROK
2.2_0603_5%
0.1U_0402_25V6
10U_0805_25V6K
10U_0805_25V6K
2200P_0402_50V7K
U2_BOOT2 1 2 PQ1203
PC1217
PC1218
@VGA_EMI@
AON6552_DFN5X6-8-5
5
PC1215
VGA_EMI@
1
1
PC1203
VGA@ PC1214
0.22U_0603_25V7K
2
GPU_VREF 2
VGA@
VGA@
1. VSNS Soft-Start time (Internal) is 0.7ms (PC1213 un-pop) U2_UGATE2 1 2 4
Tss=(Css*Vrefin)/Iss+2.3ms
=0.01U*0.9V/5uA+2.3ms=4.1ms (PC1213 pop) VGA@ PR1220
18.7K_0402_1%
1
+3VS 0_0603_5%
VGA@ PL1203
PR1221
2013/10/28 update PH1201 chang
3
2
1
VGA@
U2_PHASE2
470K_0402_5%_TSM0B474J4702RE
1 4
Common part SL200002E00
VGA@ PR1222
10K_0402_1%
2 3
3. Thermal monitoring: VGA@
1
5
PQ1204 @VGA_EMI@
(VGPU_VREF-VTSNS)/PR23=VTSNS/Rth
1U_0402_6.3V6K
AON6554_DFN5X6-8-5
1
+5VS PR1223
1
4.7_1206_5%
VGA@
VGA@ PH1201
PC1219
VGA_PWROK <17,40>
T_min T_typical T_max
2
VGA@ U2_LGATE2 4
1 2
PR1221=18.7K 96.73C 100C 103.1C PR1224 @VGA_EMI@
4 4
2.2_0603_5% PC1220
1 2 680P_0603_50V7K
3
2
1
2
PR1221=13K 106.38C 110C 113.4C VGA@
PR1225
1
VGA@
+3VS 1 2 PC1221
1U_0402_6.3V6K
2
100K_0402_1%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RT8813
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, October 17, 2014 Sheet 51 of 54
A B C D
5 4 3 2 1
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+VGA_CORE
+VGA_CORE Under VGA Core
PC1305
PC1306
PC1307
PC1308
PC1309
PC1310
PC1311
PC1312
PC1313
PC1314
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
1
1
D D
2
2
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
N15x 2013/12/10
330U_D2_2V_Y
1 1 1
560U_2.5V_M
560U_2.5V_M
+ + + Under
PC1302
@ PC1303
PC1304
4.7uF_0603_10pcs
2 2 2
1uF_0402_4pcs
Near
47uF_0805_1pcs
VGA@
VGA@
22uF_0603_1pcs(2PCS unpop)
4.7uF_0805_5pcs
47U_0805_6.3V6M
1
PC1346
N15x 2013/10/17
2
Under
+VGA_CORE 4.7uF_0603_15pcs
1uF_0402_8pcs
C
Near VGA Core Near C
47uF_0805_0pcs
22uF_0603_9pcs(2PCS unpop)
4.7uF_0805_5pcs
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1
1
PC1326 @
PC1327 VGA@
PC1328 @
VGA@ PC1335
VGA@ PC1336
VGA@ PC1337
VGA@ PC1338
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1
2
N15x 2013/10/07
Under
2
4.7uF_0603_15pcs
1uF_0402_8pcs
Near
47uF_0805_0pcs
22uF_0805_9pcs(2PCS unpop)
4.7uF_0805_5pcs
N15x 2013/10/02
Under
B 4.7uF_0603_15pcs B
1uF_0402_8pcs
Near
47uF_0805_0pcs
22uF_0805_14pcs
4.7uF_0805_5pcs
4.7U_0805_6.3V6K N14x
4.7U_0805_6.3V6K
4.7U_0805_6.3V6K
4.7U_0805_6.3V6K
4.7U_0805_6.3V6K
VGA@ PC1341
VGA@ PC1342
VGA@ PC1343
VGA@ PC1344
VGA@ PC1345
Under
1
1
4.7uF_0603_10pcs
0.1uF_0402_4pcs
Near
2
2
47uF_0805_1pcs
22uF_0805_1pcs
4.7uF_0805_5pcs
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA_CORE CAP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, October 17, 2014 Sheet 52 of 54
5 4 3 2 1
5 4 3 2 1
C
4 C
5
B B
15
16
A 17 A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PIR (PWR)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, October 17, 2014 Sheet 53 of 54
5 4 3 2 1
A B C D E
Item Fixed Issue Reason for change PG# Modify List Date Phase
1
2 Desidn change
3 Desidn change
1
4 Desidn change 1
5 Desidn change
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12 Desidn change
13 Desidn change
15 Desidn change
16 Desidn change
17 Desidn change
18 CRT leakage
19 CRT leakage
20 CRT leakage
2
21 CRT leakage 2
22 Desidn change
23 Desidn change
24 Desidn change
25 Desidn change
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27 Desidn change
28 Desidn change
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30 Desidn change
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36 Desidn change
37 Desidn change
3 38 Desidn change 3
39 Desidn change
40 Desidn change
41 Desidn change
42 Desidn change
43 Desidn change
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PIR-HW
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Z5WAH M/B LA-B161P
Date: Friday, October 17, 2014 Sheet 54 of 54
A B C D E