La C621P PDF

A B C D E
COMPAL CONFIDENTIAL
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1 MODEL NAME : ADM60 1
PCB NO : DAA000AD000
BOM P/N : 4319XY31L01/L02
Park City 12" UMA

Skylake U
2
2015-09-25 2
REV : 1.0 (A00)

@ : Nopop Component
EMC@ : EMI, ESD and RF Component

@EMC@ : EMI, ESD and RF Nopop Component
CXDP@ : XDP Component
3
CONN@ : Connector Component 3
X76@ : SATA REDRIVER OPTION
MB PCB
Part Number Description
DAA000AD000 PCB 1DK LA-C621P REV0 MB
Layout Dell logo
4 4
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
COPYRIGHT 2015 PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Cover Sheet
ALL RIGHT RESERVED Size Document Number Rev
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
REV: A00 1.0
PWB: 6N3K7
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
LA-C621P
Date: Thursday, September 24, 2015 Sheet 1 of 60
A B C D E
A B C D E
Reverse Type
Block Diagram DDR4-SO-DIMM X2
Memory BUS (DDR4)
BANK 0, 1, 2, 3
2133MHz
Vinafix.com P20~21
1 1
USB2.0[9] LCD Touch

eDP Lane x 2
EDP CONN P26
P26
USB2.0[2] Camera
Trough eDP Cable
HDMI 1.4b DDI[1] P26
VGA CONN CONN P22 USB2.0[1] PI5USB2544 USB2.0[1]_PS
P25 USB POWER SHARE USB3.0 Conn
P36 USB3.0[1] PS(RIGHT)
USB P36
VGA Switch DP DeMUX USB2.0[4]
VGA SYNATICS PS8338
DDI[2] SKYLAKE_U MCP USB3.0 Conn
P25 USB3.0[4] (REAR LEFT)
VMM3320 P23 P37
DP
DP P24
DOCKING WIGIG DP USB2.0[3]
CONN USB3.0 Conn
P38
USB3.0[3] (LEFT)
2
To M2 WiGig card P37 2
DAI
LAN PAGE 6~19
HD Audio I/F INT.Speaker
SATA1 P30
DOCK_USB2.0[5]
Card reader PCIE[10]
DOCK_USB2.0[6] SD4.0 SATA[0]/PCIE[7] HDA Codec Universal Jack
P28 RTS5250 P28
DOCK_USB3.0[5]
SATA[2]/PCIE[11],[12]
ALC3235 P30 P30
SPI
Dig. MIC
W25Q128FVSIQ Trough eDP Cable
SATA REPEATER
LPC
P8
PCIE[9] PCIE[3] PCIE[5] PCIE[6] P42
Spindle
W25Q64CVSSIQ HDD Conn LID SWITCH
P8 P42 LED/B
SATA/PCIE REPEATER X1
PS8555 P34
3
Intel Jacksonville M.2,3042 Key B M.2,3030 Key A USH CONN 3
SMSC SIO TPM2.0 P33

I219LM P27 WWAN/LTE/HCA Key M
WLAN+BT/WIGIG ECE5048 NPCT650JAAYX SATA/PCIE REPEATER X1
P29 P29 P31
P33 HDD Conn
PS8555 P34 P35 CPU&PCH XDP Port
P14
USB2.0[10] USB2.0[8]
Transformer
P27 WIGIG_DP BC BUS KB/TP CONN AUTOMATIC POWER
USB3.0[5] P39 reserve PCIE signal for SATA express HDD SWITCH(APS) P11
SMSC KBC
MEC5085
RJ45 P27 P32 FAN CONN
P32
DC/DC Interface
P41
Smart Card TDA8034HN POWER ON/OFF

USB2.0[7]
SW & LED P40
4
USH TPM1.2 4
BCM58102
RFID/NFC SPI
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
Fingerprint SPI TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Block diagram
CONN USH board BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
Size Document Number Rev
1.0
P30
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-C621P
A B C D E
5 4 3 2 1
POWER STATES
Signal SLP SLP SLP SLP ALWAYS M SUS RUN CLOCKS
USB3.0 SSIC PCIE SATA DESTINATION USB PORT# DESTINATION
S3# S4# S5# A# PLANE PLANE PLANE PLANE
State USB3.0-1 JUSB3-->Right 1 JUSB1-->Right
USB3.0-2 SSIC-1 EDOCK PORT1 2 Camera
S0 (Full ON) / M0 HIGH HIGH Vinafix.com
HIGHHIGH ON ON ON ON ON
USB3.0-3 SSIC-2 JUSB1-->LEFT 3 JUSB2-->LEFT
D D
S3 (Suspend to RAM) / M3 LOW HIGH HIGH HIGH ON ON ON OFF OFF
USB3.0-4 JUSB2-->Rear LEFT 4 JUSB3-->Rear LEFT
S4 (Suspend to DISK) / M3 LOW LOW HIGH HIGH ON ON OFF OFF OFF USB3.0-5 PCIE-1 M2 3042(WWAN) 5 EDOCK PORT1
S5 (SOFT OFF) / M3 LOW LOW LOW HIGH ON ON OFF OFF OFF USB3.0-6 PCIE-2 NA 6 EDOCK PORT2
M.2 3042(HCA or QCA LTE)
PCIE-3 7 USH
S3 (Suspend to RAM) / M-OFF LOW HIGH HIGH LOW ON OFF ON OFF OFF
PCIE-4 NA 8 M.2 304230(BT)
S4 (Suspend to DISK) / M-OFF LOW LOW HIGH LOW ON OFF OFF OFF OFF PCIE-5 M.2 3030(WLAN) 9 Touch Screen
S5 (SOFT OFF) / M-OFF LOW LOW LOW LOW ON OFF OFF OFF OFF
PCIE-6 M.2 3030(WIGIG) 10 M2 3042(WWAN)
PCIE-7 SATA-0 HDD SATA
PM TABLE PCIE-8 SATA-1 EDOCK E-SATA

0 BIO
USH
C +5V_ALW
PCIE-9 LOM C
(M-OFF)
1 NA
+3.3V_ALW PCIE-10 Card Reader
+3.3V_ALW_DSW +3.3V_SUS +5V_RUN
+3.3V_M +3.3V_M PCIE-11 SATA-1* M.2 Socket 3 (Key M) Check
+3.3V_ALW_PCH +1.2V_MEM +3.3V_RUN
power +VCC_CORE (PCIex2 or SATA)
plane +RTC_CELL +1.0V_VCCST +0.6V_DDR_VTT PCIE-12 SATA-2
+VCC_GT
+1.8V_PRIM +2.5V_MEM +1.5V_RUN
+1.0VS_VCCIO
+1.0V_PRIM
+VCC_SA
+1.0V_PRIM_CORE
+5V_ALW2
State
+3.3V_ALW2
+3.3V_RTC_LDO
+1.0V_MPHYGT
S0 ON ON ON ON ON
B S3 ON ON OFF ON OFF B
S5 S4/AC ON OFF OFF ON OFF
S5 S4/AC doesn't exist OFF OFF OFF OFF OFF
A A
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
Port assignment
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
5 4 3 2 1
5 4 3 2 1
CPU PWR
0.675_DDR_VTT_ON
RT8207M SIO_SLP_S4# RT8207 PCH PWR
+1.2V_MEM LDOIN
(PU201) +0.6V_DDR_VTT
(PU201) GPU PWR
Peripheral Device PWR
MPHYP_PWR_EN
TPS22961
(UZ20) +1.0V_MPHYGT
ADAPTER
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SIO_SLP_SUS# TPS22961 SIO_SLP_S3#
D SYX198D (UZ19) +1.0V_VCCSTG D
(PU301) +1.0V_PRIM
RUN_ON TPS22961 SIO_SLP_S4#

TPS62134A (UZ21) +1.0V_VCCST
(PU401) +1.0VS_VCCIO
TPS22967 3.3V_HDD_EN
CHARGER (UZ23) +5V_HDD
BQ24777 +PWR_SRC
HUB_LP_EN TPS22961
(PU801) (UV28) +1.0V_RUN_VMM EM5209 RUN_ON
(UZ4) +5V_RUN
SIO_SLP_SUS#
TPS62134B
(PU402) +1.0V_PRIM_CORE
EM5209 AUD_PWR_EN
(UZ5) +5V_RUN_AUDIO
+5V_ALW
SYX198C ALWON PI5USB2544 USB_PWR_SHR_VBUS_EN
(UI3) +5V_USB_CHG_PWR
(PU100)
BATTERY
+5V_ALW2
SY6288 USB_PWR_EN1#
(UI1) +USB_LEFT_PWR
C C
SYX198B +3.3V_RTC_LDO
(PU100)
SY6288 USB_PWR_EN2#
ALWON (UI2) +USB_REAR_PWR
+3.3V_ALW2
SY8032A SIO_SLP_SUS#
(PU501) +1.8V_PRIM
+3.3V_ALW
SIO_SLP_LAN#
+3.3V_LAN
AO6405 EM5209
ISL95857 (QV1) (UZ2)
(PU602) 3.3V_WWAN_EN
@SIO_SLP_WLAN# +3.3V_WWAN AP7175SP SIO_SLP_S4#
(PU1500) +2.5V_MEM
EN_INVPWR
IMVP_VR_ON
IMVP_VR_ON
IMVP_VR_ON
3.3V_TS_EN
AUX_EN_WOWL LP2301
@SIO_SLP_WLAN# +3.3V_WLAN (QV8) +3V_TSP
EM5209
+BL_PWR_SRC (UZ3)
B
+VCC_SA +VCC_GT +VCC_CORE RUN_ON
+3.3V_RUN AP7175SP +3.3V_RUN
+1.5V_RUN
B
(PU502)
3.3V_CAM_EN#
LP2301A
(QZ1) +3.3V_CAM
EM5209 AUD_PWR_EN
(UZ5) +3.3V_RUN_AUDIO +3.3V_HDD
A_ON
TPS22967 +3.3V_M
(UZ8)
SIO_SLP_SUS#
EM5209 +3.3V_ALW_PCH
(UZ4) @PCH_ALW_ON
TPS22967 CV2_ON
(UZ18) +3.3V_CV2
USH/B
A A
ENVCC_PCH
AP2821
(UV24) +LCDVDD
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Power rails
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
5 4 3 2 1
5 4 3 2 1
1K 2.2K
1K
+3.3V_ALW_PCH 2.2K
+3.3V_RUN
R7 MEM_SMBCLK 202
MEM_SMBDATA
2N7002
R8 200 DIMMA
Vinafix.com
499
2N7002
202
D
SKL-U D
+3.3V_ALW_PCH 200 DIMMB
499
R9 SML0_SMBCLK 28
W2 SML0_SMBDATA 31 LOM
W3 V3 53
51 XDP
1K
SML1_SMBDATA
SML1_SMBCLK
+3.3V_ALW_PCH
1K
A5 B6 2.2K
3A 3A
2.2K +3.3V_ALW
B4 DOCK_SMB_CLK 127
1A
129 Dock
1A A3 DOCK_SMB_DAT
C C
B5
1B
A4
1B
2.2K
KBC 2.2K
+3.3V_ALW
100 ohm 7
1C A56 PBAT_SMBCLK
100 ohm 6 BATTERY
1C B59 PBAT_SMBDAT CONN
@2.2K 2.2K
+3.3V_ALW +3.3V_CV2
@2.2K 2.2K
A50
1E USH_SMBCLK M9
MEC 5085 1E
B53
USH_SMBDAT L9
USH
B B
USH/B
2B A49
2B B52
10K
+3.3V_ALW
10K
B50 9
1G CHARGER_SMBCLK
A47 8 Charger
1G CHARGER_SMBDAT
2D B7
A A
2D A7
2.2K
+3.3V_RUN DELL CONFIDENTIAL/PROPRIETARY
2.2K
2A B48 GPU_SMBDAT PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT SMbus Block diagram
B49 GPU_SMBCLK BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
2A NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
5 4 3 2 1
5 4 3 2 1
+3.3V_RUN
UC1A SKL-U
2 1 CPU_DP1_CTRL_CLK E55 C47

RC175
2
RC178
2.2K_0402_5%
1 CPU_DP1_CTRL_DATA
2.2K_0402_5%
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<22> CPU_DP1_N0
<22> CPU_DP1_P0
<22> CPU_DP1_N1
F55
E58
F58
DDI1_TXN[0]
DDI1_TXP[0]
DDI1_TXN[1]
EDP_TXN[0]
EDP_TXP[0]
EDP_TXN[1]
C46
D46
C45
EDP_TXN0 <26>
EDP_TXP0 <26>
EDP_TXN1 <26> Support QHD
2 1 CPU_DP2_CTRL_CLK <22> CPU_DP1_P1 F53 DDI1_TXP[1] EDP_TXP[1] A45 EDP_TXP1 <26>
D RC176 2.2K_0402_5% <22> CPU_DP1_N2 G53 DDI1_TXN[2] EDP_TXN[2] B45 D
2 1 CPU_DP2_CTRL_DATA <22> CPU_DP1_P2 F56 DDI1_TXP[2] EDP_TXP[2] A47
RC177 2.2K_0402_5% <22> CPU_DP1_N3 G56 DDI1_TXN[3] EDP_TXN[3] B47
<22> CPU_DP1_P3 DDI1_TXP[3] EDP_TXP[3] +3.3V_RUN
C50 E45
<23> CPU_DP2_N0 D50 DDI2_TXN[0] DDI EDP EDP_AUXN F45 EDP_AUXN <26>
<23> CPU_DP2_P0 C52 DDI2_TXP[0] EDP_AUXP EDP_AUXP <26>
<23> CPU_DP2_N1 D52 DDI2_TXN[1] B52
<23> CPU_DP2_P1 A50 DDI2_TXP[1] EDP_DISP_UTIL
<23> CPU_DP2_N2 B50 DDI2_TXN[2] G50 CPU_DP1_AUXN
<23> CPU_DP2_P2 D51 DDI2_TXP[2] DDI1_AUXN F50 CPU_DP1_AUXP CPU_DP1_AUXN 2 1
<23> CPU_DP2_N3 C51 DDI2_TXN[3] DDI1_AUXP E48 100K_0402_5% RC179
<23> CPU_DP2_P3 DDI2_TXP[3] DDI2_AUXN F48 CPU_DP2_AUXN <23> CPU_DP2_AUXN 2 1
DDI2_AUXP G46 CPU_DP3_AUXN CPU_DP2_AUXP <23>
100K_0402_5% RC181
DISPLAY SIDEBANDS DDI3_AUXN F46 CPU_DP3_AUXP PAD~D @ T1
CPU_DP1_CTRL_CLK L13 DDI3_AUXP PAD~D @ T2
<22> CPU_DP1_CTRL_CLK CPU_DP1_CTRL_DATA L12 GPP_E18/DDPB_CTRLCLK L9 CPU_DP2_AUXP 2 1
<22> CPU_DP1_CTRL_DATA GPP_E19/DDPB_CTRLDATA GPP_E13/DDPB_HPD0 L7 CPU_DP1_HPD <22>
100K_0402_5% RC182
CPU_DP2_CTRL_CLK N7 GPP_E14/DDPC_HPD1 L6 CPU_DP2_HPD <23> CPU_DP1_AUXP 2 1
<23> CPU_DP2_CTRL_CLK CPU_DP2_CTRL_DATA N8 GPP_E20/DDPC_CTRLCLK GPP_E15/DDPD_HPD2 N9 100K_0402_5% RC180
<23> CPU_DP2_CTRL_DATA GPP_E21/DDPC_CTRLDATA GPP_E16/DDPE_HPD3 L10 EDP_HPD 2 1
N11 GPP_E17/EDP_HPD EDP_HPD <26>
100K_0402_5% RC1
GPP_E23 N12 GPP_E22/DDPD_CTRLCLK R12 CPU_DP1_HPD 2 1
T120@ PAD~D GPP_E23/DDPD_CTRLDATA EDP_BKLTEN PANEL_BKLEN <26> @ RC312
R11 100K_0402_5%
RC2 1 2 24.9_0402_1% EDP_COMP E52 EDP_BKLTCTL U13 EDP_BIA_PWM <26> CPU_DP2_HPD 2 1
+1.0VS_VCCIO EDP_RCOMP 1 OF 20 EDP_VDDEN ENVDD_PCH <26,32> 100K_0402_5% RC242
SKL-U_BGA1356
COMPENSATION PU FOR eDP
CAD Note:Trace width=20 mils ,Spacing=25mil, SKL-U Ballout Rev0.71 & INTEL symbol Rev1.0
Max length=100 mils.
C C
SKL_ULT
UC1I
CSI-2
A36 C37
B36 CSI2_DN0 CSI2_CLKN0 D37
C38 CSI2_DP0 CSI2_CLKP0 C32
D38 CSI2_DN1 CSI2_CLKN1 D32
C36 CSI2_DP1 CSI2_CLKP1 C29
D36 CSI2_DN2 CSI2_CLKN2 D29
A38 CSI2_DP2 CSI2_CLKP2 B26
B B38 CSI2_DN3 CSI2_CLKN3 A26 B
CSI2_DP3 CSI2_CLKP3
C31 E13 CSI2_COMP 1 2
D31 CSI2_DN4 CSI2_COMP B7 RC3 100_0402_1%
C33 CSI2_DP4 GPP_D4/FLASHTRIG
D33 CSI2_DN5
A31 CSI2_DP5 EMMC
B31 CSI2_DN6 AP2
A33 CSI2_DP6 GPP_F13/EMMC_DATA0 AP1
B33 CSI2_DN7 GPP_F14/EMMC_DATA1 AP3
CSI2_DP7 GPP_F15/EMMC_DATA2 AN3
A29 GPP_F16/EMMC_DATA3 AN1
B29 CSI2_DN8 GPP_F17/EMMC_DATA4 AN2
C28 CSI2_DP8 GPP_F18/EMMC_DATA5 AM4
D28 CSI2_DN9 GPP_F19/EMMC_DATA6 AM1
A27 CSI2_DP9 GPP_F20/EMMC_DATA7
B27 CSI2_DN10 AM2
C27 CSI2_DP10 GPP_F21/EMMC_RCLK AM3
D27 CSI2_DN11 GPP_F22/EMMC_CLK AP4
CSI2_DP11 GPP_F12/EMMC_CMD
AT1 EMMC_RCOMP 1 2
EMMC_RCOMP RC4 200_0402_1%
SKL-U_BGA1356 9 OF 20
A A
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT CPU (1/14)
5 4 3 2 1
5 4 3 2 1
<20> DDR_A_DQS#[0..7]
<20> DDR_A_D[0..63]
<20> DDR_A_DQS[0..7]
<20> DDR_A_MA[0..16]
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D <21> DDR_B_DQS#[0..7] D
<21> DDR_B_D[0..63]
<21> DDR_B_DQS[0..7]
DDR4, Ballout for side by side(Non-Interleave) <21> DDR_B_MA[0..16]
SKL-U
UC1B SKL-U UC1C
AU53 DDR_A_CLK#0
DDR_A_D0 AL71 DDR0_CKN[0] AT53 DDR_A_CLK0 DDR_A_CLK#0 <20> DDR_A_D16 AF65 AN45 DDR_B_CLK#0
DDR_A_D1 AL68 DDR0_DQ[0] DDR0_CKP[0] AU55 DDR_A_CLK#1 DDR_A_CLK0 <20> DDR_A_D17 AF64 DDR1_DQ[0]/DDR0_DQ[16] DDR1_CKN[0] AN46 DDR_B_CLK#1 DDR_B_CLK#0 <21>
DDR_A_D2 AN68 DDR0_DQ[1] DDR0_CKN[1] AT55 DDR_A_CLK1 DDR_A_CLK#1 <20> DDR_A_D18 AK65 DDR1_DQ[1]/DDR0_DQ[17] DDR1_CKN[1] AP45 DDR_B_CLK0 DDR_B_CLK#1 <21>
DDR_A_D3 AN69 DDR0_DQ[2] DDR0_CKP[1] DDR_A_CLK1 <20> DDR_A_D19 AK64 DDR1_DQ[2]/DDR0_DQ[18] DDR1_CKP[0] AP46 DDR_B_CLK1 DDR_B_CLK0 <21>
DDR_A_D4 AL70 DDR0_DQ[3] BA56 DDR_A_CKE0 DDR_A_D20 AF66 DDR1_DQ[3]/DDR0_DQ[19] DDR1_CKP[1] DDR_B_CLK1 <21>
DDR_A_D5 AL69 DDR0_DQ[4] DDR0_CKE[0] BB56 DDR_A_CKE1 DDR_A_CKE0 <20> DDR_A_D21 AF67 DDR1_DQ[4]/DDR0_DQ[20] AN56 DDR_B_CKE0
DDR_A_D6 AN70 DDR0_DQ[5] DDR0_CKE[1] AW56 DDR_A_CKE2 DDR_A_CKE1 <20> DDR_A_D22 AK67 DDR1_DQ[5]/DDR0_DQ[21] DDR1_CKE[0] AP55 DDR_B_CKE1 DDR_B_CKE0 <21>
DDR_A_D7 AN71 DDR0_DQ[6] DDR0_CKE[2] AY56 DDR_A_CKE3 PAD~D @ T3 DDR_A_D23 AK66 DDR1_DQ[6]/DDR0_DQ[22] DDR1_CKE[1] AN55 DDR_B_CKE2 DDR_B_CKE1 <21>
DDR_A_D8 AR70 DDR0_DQ[7] DDR0_CKE[3] PAD~D @ T4 DDR_A_D24 AF70 DDR1_DQ[7]/DDR0_DQ[23] DDR1_CKE[2] AP53 DDR_B_CKE3 PAD~D @ T5
DDR_A_D9 AR68 DDR0_DQ[8] AU45 DDR_A_CS#0 DDR_A_D25 AF68 DDR1_DQ[8]/DDR0_DQ[24] DDR1_CKE[3] PAD~D @ T6
DDR_A_D10 AU71 DDR0_DQ[9] DDR0_CS#[0] AU43 DDR_A_CS#1 DDR_A_CS#0 <20> DDR_A_D26 AH71 DDR1_DQ[9]/DDR0_DQ[25] BB42 DDR_B_CS#0
DDR_A_D11 AU68 DDR0_DQ[10] DDR0_CS#[1] AT45 DDR_A_ODT0 DDR_A_CS#1 <20> DDR_A_D27 AH68 DDR1_DQ[10]/DDR0_DQ[26] DDR1_CS#[0] AY42 DDR_B_CS#1 DDR_B_CS#0 <21>
DDR_A_D12 AR71 DDR0_DQ[11] DDR0_ODT[0] AT43 DDR_A_ODT1 DDR_A_ODT0 <20> DDR_A_D28 AF71 DDR1_DQ[11]/DDR0_DQ[27] DDR1_CS#[1] BA42 DDR_B_ODT0 DDR_B_CS#1 <21>
DDR_A_D13 AR69 DDR0_DQ[12] DDR0_ODT[1] DDR_A_ODT1 <20> DDR_A_D29 AF69 DDR1_DQ[12]/DDR0_DQ[28] DDR1_ODT[0] AW42 DDR_B_ODT1 DDR_B_ODT0 <21>
DDR_A_D14 AU70 DDR0_DQ[13] BA51 DDR_A_MA5 DDR_A_D30 AH70 DDR1_DQ[13]/DDR0_DQ[29] DDR1_ODT[1] DDR_B_ODT1 <21>
Check ODT schematic 0918
DDR_A_D15 AU69 DDR0_DQ[14] DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] BB54 DDR_A_MA9 DDR_A_D31 AH69 DDR1_DQ[14]/DDR0_DQ[30] AY48 DDR_B_MA5 Check ODT schematic 0918
DDR_A_D32 BB65 DDR0_DQ[15] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] BA52 DDR_A_MA6 DDR_A_D48 AT66 DDR1_DQ[15]/DDR0_DQ[31] DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] AP50 DDR_B_MA9
DDR_A_D33 AW65 DDR0_DQ[16]/DDR0_DQ[32] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] AY52 DDR_A_MA8 DDR_A_D49 AU66 DDR1_DQ[16]/DDR0_DQ[48] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] BA48 DDR_B_MA6
C DDR_A_D34 AW63 DDR0_DQ[17]/DDR0_DQ[33] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] AW52 DDR_A_MA7 DDR_A_D50 AP65 DDR1_DQ[17]/DDR0_DQ[49] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] BB48 DDR_B_MA8 C
DDR_A_D35 AY63 DDR0_DQ[18]/DDR0_DQ[34] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] AY55 DDR_A_BG0 DDR_A_D51 AN65 DDR1_DQ[18]/DDR0_DQ[50] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] AP48 DDR_B_MA7
DDR_A_D36 BA65 DDR0_DQ[19]/DDR0_DQ[35] DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] AW54 DDR_A_MA12 DDR_A_BG0 <20> DDR_A_D52 AN66 DDR1_DQ[19]/DDR0_DQ[51] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] AP52 DDR_B_BG0
DDR_A_D37 AY65 DDR0_DQ[20]/DDR0_DQ[36] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] BA54 DDR_A_MA11 DDR_A_D53 AP66 DDR1_DQ[20]/DDR0_DQ[52] DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] AN50 DDR_B_MA12 DDR_B_BG0 <21>
DDR_A_D38 BA63 DDR0_DQ[21]/DDR0_DQ[37] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] BA55 DDR_A_ACT# DDR_A_D54 AT65 DDR1_DQ[21]/DDR0_DQ[53] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] AN48 DDR_B_MA11
DDR_A_D39 BB63 DDR0_DQ[22]/DDR0_DQ[38] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# AY54 DDR_A_BG1 DDR_A_ACT# <20> DDR_A_D55 AU65 DDR1_DQ[22]/DDR0_DQ[54] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] AN53 DDR_B_ACT#
DDR_A_D40 BA61 DDR0_DQ[23]/DDR0_DQ[39] DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] DDR_A_BG1 <20> DDR_A_D56 AT61 DDR1_DQ[23]/DDR0_DQ[55] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# AN52 DDR_B_BG1 DDR_B_ACT# <21>
DDR_A_D41 AW61 DDR0_DQ[24]/DDR0_DQ[40] AU46 DDR_A_MA13 DDR_A_D57 AU61 DDR1_DQ[24]/DDR0_DQ[56] DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1] DDR_B_BG1 <21>
DDR_A_D42 BB59 DDR0_DQ[25]/DDR0_DQ[41] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] AU48 DDR_A_MA15 DDR_A_D58 AP60 DDR1_DQ[25]/DDR0_DQ[57] BA43 DDR_B_MA13
DDR_A_D43 AW59 DDR0_DQ[26]/DDR0_DQ[42] DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15] AT46 DDR_A_MA14 DDR_A_D59 AN60 DDR1_DQ[26]/DDR0_DQ[58] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13] AY43 DDR_B_MA15
DDR_A_D44 BB61 DDR0_DQ[27]/DDR0_DQ[43] DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14] AU50 DDR_A_MA16 DDR_A_D60 AN61 DDR1_DQ[27]/DDR0_DQ[59] DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15] AY44 DDR_B_MA14
DDR_A_D45 AY61 DDR0_DQ[28]/DDR0_DQ[44] DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16] AU52 DDR_A_BA0 DDR_A_D61 AP61 DDR1_DQ[28]/DDR0_DQ[60] DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14] AW44 DDR_B_MA16
DDR_A_D46 BA59 DDR0_DQ[29]/DDR0_DQ[45] DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] AY51 DDR_A_MA2 DDR_A_BA0 <20> DDR_A_D62 AT60 DDR1_DQ[29]/DDR0_DQ[61] DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16] BB44 DDR_B_BA0
DDR_A_D47 AY59 DDR0_DQ[30]/DDR0_DQ[46] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] AT48 DDR_A_BA1 DDR_A_D63 AU60 DDR1_DQ[30]/DDR0_DQ[62] DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] AY47 DDR_B_MA2 DDR_B_BA0 <21>
DDR_B_D0 AY39 DDR0_DQ[31]/DDR0_DQ[47] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] AT50 DDR_A_MA10 DDR_A_BA1 <20> DDR_B_D16 AU40 DDR1_DQ[31]/DDR0_DQ[63] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2] BA44 DDR_B_BA1
DDR_B_D1 AW39 DDR0_DQ[32]/DDR1_DQ[0] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] BB50 DDR_A_MA1 DDR_B_D17 AT40 DDR1_DQ[32]/DDR1_DQ[16] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] AW46 DDR_B_MA10 DDR_B_BA1 <21>
DDR_B_D2 AY37 DDR0_DQ[33]/DDR1_DQ[1] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] AY50 DDR_A_MA0 DDR_B_D18 AT37 DDR1_DQ[33]/DDR1_DQ[17] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] AY46 DDR_B_MA1
DDR_B_D3 AW37 DDR0_DQ[34]/DDR1_DQ[2] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] BA50 DDR_A_MA3 DDR_B_D19 AU37 DDR1_DQ[34]/DDR1_DQ[18] DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] BA46 DDR_B_MA0
DDR_B_D4 BB39 DDR0_DQ[35]/DDR1_DQ[3] DDR0_MA[3] BB52 DDR_A_MA4 DDR_B_D20 AR40 DDR1_DQ[35]/DDR1_DQ[19] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0] BB46 DDR_B_MA3
DDR_B_D5 BA39 DDR0_DQ[36]/DDR1_DQ[4] DDR0_MA[4] DDR_B_D21 AP40 DDR1_DQ[36]/DDR1_DQ[20] DDR1_MA[3] BA47 DDR_B_MA4
DDR_B_D6 BA37 DDR0_DQ[37]/DDR1_DQ[5] AM70 DDR_A_DQS#0 DDR_B_D22 AP37 DDR1_DQ[37]/DDR1_DQ[21] DDR1_MA[4]
DDR_B_D7 BB37 DDR0_DQ[38]/DDR1_DQ[6] DDR0_DQSN[0] AM69 DDR_A_DQS0 DDR_B_D23 AR37 DDR1_DQ[38]/DDR1_DQ[22] AH66 DDR_A_DQS#2
DDR_B_D8 AY35 DDR0_DQ[39]/DDR1_DQ[7] DDR0_DQSP[0] AT69 DDR_A_DQS#1 DDR_B_D24 AT33 DDR1_DQ[39]/DDR1_DQ[23] DDR1_DQSN[0]/DDR0_DQSN[2] AH65 DDR_A_DQS2
DDR_B_D9 AW35 DDR0_DQ[40]/DDR1_DQ[8] DDR0_DQSN[1] AT70 DDR_A_DQS1 DDR_B_D25 AU33 DDR1_DQ[40]/DDR1_DQ[24] DDR1_DQSP[0]/DDR0_DQSP[2] AG69 DDR_A_DQS#3
DDR_B_D10 AY33 DDR0_DQ[41]/DDR1_DQ[9] DDR0_DQSP[1] BA64 DDR_A_DQS#4 DDR_B_D26 AU30 DDR1_DQ[41]/DDR1_DQ[25] DDR1_DQSN[1]/DDR0_DQSN[3] AG70 DDR_A_DQS3
DDR_B_D11 AW33 DDR0_DQ[42]/DDR1_DQ[10] DDR0_DQSN[2]/DDR0_DQSN[4] AY64 DDR_A_DQS4 DDR_B_D27 AT30 DDR1_DQ[42]/DDR1_DQ[26] DDR1_DQSP[1]/DDR0_DQSP[3] AR66 DDR_A_DQS#6
DDR_B_D12 BB35 DDR0_DQ[43]/DDR1_DQ[11] DDR0_DQSP[2]/DDR0_DQSP[4] AY60 DDR_A_DQS#5 DDR_B_D28 AR33 DDR1_DQ[43]/DDR1_DQ[27] DDR1_DQSN[2]/DDR0_DQSN[6] AR65 DDR_A_DQS6
DDR_B_D13 BA35 DDR0_DQ[44]/DDR1_DQ[12] DDR0_DQSN[3]/DDR0_DQSN[5] BA60 DDR_A_DQS5 DDR_B_D29 AP33 DDR1_DQ[44]/DDR1_DQ[28] DDR1_DQSP[2]/DDR0_DQSP[6] AR61 DDR_A_DQS#7
DDR_B_D14 BA33 DDR0_DQ[45]/DDR1_DQ[13] DDR0_DQSP[3]/DDR0_DQSP[5] BA38 DDR_B_DQS#0 DDR_B_D30 AR30 DDR1_DQ[45]/DDR1_DQ[29] DDR1_DQSN[3]/DDR0_DQSN[7] AR60 DDR_A_DQS7
DDR_B_D15 BB33 DDR0_DQ[46]/DDR1_DQ[14] DDR0_DQSN[4]/DDR1_DQSN[0] AY38 DDR_B_DQS0 DDR_B_D31 AP30 DDR1_DQ[46]/DDR1_DQ[30] DDR1_DQSP[3]/DDR0_DQSP[7] AT38 DDR_B_DQS#2
DDR_B_D32 AY31 DDR0_DQ[47]/DDR1_DQ[15] DDR0_DQSP[4]/DDR1_DQSP[0] AY34 DDR_B_DQS#1 DDR_B_D48 AU27 DDR1_DQ[47]/DDR1_DQ[31] DDR1_DQSN[4]/DDR1_DQSN[2] AR38 DDR_B_DQS2
DDR_B_D33 AW31 DDR0_DQ[48]/DDR1_DQ[32] DDR0_DQSN[5]/DDR1_DQSN[1] BA34 DDR_B_DQS1 DDR_B_D49 AT27 DDR1_DQ[48] DDR1_DQSP[4]/DDR1_DQSP[2] AT32 DDR_B_DQS#3
B DDR_B_D34 AY29 DDR0_DQ[49]/DDR1_DQ[33] DDR0_DQSP[5]/DDR1_DQSP[1] BA30 DDR_B_DQS#4 DDR_B_D50 AT25 DDR1_DQ[49] DDR1_DQSN[5]/DDR1_DQSN[3] AR32 DDR_B_DQS3 B
DDR_B_D35 AW29 DDR0_DQ[50]/DDR1_DQ[34] DDR0_DQSN[6]/DDR1_DQSN[4] AY30 DDR_B_DQS4 DDR_B_D51 AU25 DDR1_DQ[50] DDR1_DQSP[5]/DDR1_DQSP[3] AR25 DDR_B_DQS#6
DDR_B_D36 BB31 DDR0_DQ[51]/DDR1_DQ[35] DDR0_DQSP[6]/DDR1_DQSP[4] AY26 DDR_B_DQS#5 DDR_B_D52 AP27 DDR1_DQ[51] DDR1_DQSN[6] AR27 DDR_B_DQS6
DDR_B_D37 BA31 DDR0_DQ[52]/DDR1_DQ[36] DDR0_DQSN[7]/DDR1_DQSN[5] BA26 DDR_B_DQS5 DDR_B_D53 AN27 DDR1_DQ[52] DDR1_DQSP[6] AR22 DDR_B_DQS#7
DDR_B_D38 BA29 DDR0_DQ[53]/DDR1_DQ[37] DDR0_DQSP[7]/DDR1_DQSP[5] DDR_B_D54 AN25 DDR1_DQ[53] DDR1_DQSN[7] AR21 DDR_B_DQS7
DDR_B_D39 BB29 DDR0_DQ[54]/DDR1_DQ[38] AW50 DDR_A_ALERT# DDR0_PAR,DDR0_ALERT# for DDR4 DDR_B_D55 AP25 DDR1_DQ[54] DDR1_DQSP[7]
DDR_B_D40 AY27 DDR0_DQ[55]/DDR1_DQ[39] DDR0_ALERT# AT52 DDR_A_PARITY DDR_A_ALERT# <20> DDR_B_D56 AT22 DDR1_DQ[55] AN43
DDR1_PAR,DDR1_ALERT# for
DDR_B_ALERT# DDR4
DDR_B_D41 AW27 DDR0_DQ[56]/DDR1_DQ[40] DDR0_PAR DDR_A_PARITY <20> DDR_B_D57 AU22 DDR1_DQ[56] DDR1_ALERT# AP43 DDR_B_PARITY DDR_B_ALERT# <21>
DDR_B_D42 AY25 DDR0_DQ[57]/DDR1_DQ[41] AY67 DDR_B_D58 AU21 DDR1_DQ[57] DDR1_PAR AT13 DDR_DRAMRST# DDR_B_PARITY <21>
DDR_B_D43 DDR0_DQ[58]/DDR1_DQ[42] DDR_VREF_CA +DDR_VREF_CA DDR1_DQ[58] DRAM_RESET# DDR_DRAMRST# <20>
AW25 AY68 +DDR_VREF_A_DQ DDR_B_D59 AT21 AR18 SM_RCOMP0
DDR_B_D44 BB27 DDR0_DQ[59]/DDR1_DQ[43] DDR0_VREF_DQ BA67 PAD~D @ T132 DDR_B_D60 AN22 DDR1_DQ[59] DDR_RCOMP[0] AT18 SM_RCOMP1
DDR CH - A
DDR_B_D45 DDR0_DQ[60]/DDR1_DQ[44] DDR1_VREF_DQ +DDR_VREF_B_DQ DDR_B_D61 DDR1_DQ[60] DDR CH - B DDR_RCOMP[1] SM_RCOMP2
BA27 AP22 AU18
DDR_B_D46 BA25 DDR0_DQ[61]/DDR1_DQ[45] AW67 DDR_B_D62 AP21 DDR1_DQ[61] DDR_RCOMP[2]
DDR_B_D47 BB25 DDR0_DQ[62]/DDR1_DQ[46] DDR_VTT_CNTL DDR_VTT_CTRL <20> DDR_B_D63 AN21 DDR1_DQ[62]
DDR0_DQ[63]/DDR1_DQ[47] DDR1_DQ[63]
SKL-U_BGA1356 2 OF 20 SKL-U_BGA1356 3 OF 20
DDR4 COMPENSATION SIGNALS

A SM_RCOMP0 RC5 1 2 121_0402_1% A
SM_RCOMP1 RC6 1 2 80.6_0402_1%
SM_RCOMP2 RC7 1 2 100_0402_1%

CAD Note: Compal Electronics, Inc.
Trace width=12~15 mil, Spacing=20 mils PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
Max trace length= 500 mil TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
CPU (2/14)
5 4 3 2 1
5 4 3 2 1
+3.3V_RUN +3.3V_RUN
SPI_MOSI= SPI_IO0
SPI_MISO= SPI_IO1 DDR_XDP_WAN_SMBDAT 2 1
PCH EDS R0.7 p.235~236 SKL-U 2.2K_0402_5% RC318
UC1E DDR_XDP_WAN_SMBCLK 2 1
2
2.2K_0402_5% RC319
SPI - FLASH
SMBUS, SMLINK
PCH_SPI_CLK AV2 MEM_SMBCLK 6 1
PCH_SPI_D1 AW3 SPI0_CLK R7 MEM_SMBCLK DDR_XDP_WAN_SMBCLK <14,20,21,42>
<14> PCH_SPI_DO_XDP
RC10 1 2 1K_0402_1%
Vinafix.com
PCH_SPI_D0 AV3 SPI0_MISO
SPI0_MOSI
GPP_C0/SMBCLK
GPP_C1/SMBDATA
R8 MEM_SMBDATA QC2A
5
RC11 1 2 1K_0402_1% PCH_SPI_D2 AW2 R10 PCH_SMB_ALERT# DMN65D8LDW-7_SOT363-6
<14> PCH_SPI_DO2_XDP PCH_SPI_D3 AU4 SPI0_IO2 GPP_C2/SMBALERT#
PCH_SPI_CS#0 AU3 SPI0_IO3 R9 SML0_SMBCLK MEM_SMBDATA 3 4
D PCH_SPI_CS#1 AU2 SPI0_CS0# GPP_C3/SML0CLK W2 SML0_SMBDATA SML0_SMBCLK <27> DDR_XDP_WAN_SMBDAT <14,20,21,42> D
PCH_SPI_CS#2 AU1 SPI0_CS1# GPP_C4/SML0DATA W1 GPP_C5 SML0_SMBDATA <27>
QC2B
+3.3V_RUN <33> PCH_SPI_CS#2 SPI0_CS2# GPP_C5/SML0ALERT# DMN65D8LDW-7_SOT363-6 +3.3V_LAN
W3 SML1_SMBCLK
SPI - TOUCH GPP_C6/SML1CLK V3 SML1_SMBDATA SML1_SMBCLK <32>
GPP_C7/SML1DATA SML1_SMBDATA <32>
1
ONE_DIMM# M2 GPP_B23
10K_0402_5%
AM7
GPP_D1/SPI1_CLK GPP_B23/SML1ALERT#/PCHHOT# SML0_SMBCLK
@ RC267
M3 1 2
<33> TPM_PIRQ# J4 GPP_D2/SPI1_MISO @ RC19 499_0402_1%
<42> FFS_INT2 V1 GPP_D3/SPI1_MOSI SML0_SMBDATA 1 2
V2 GPP_D21/SPI1_IO2 @ RC20 499_0402_1%
2
+3.3V_RUN M1 GPP_D22/SPI1_IO3 +3.3V_ALW_PCH

LPC
ONE_DIMM# <28> MEDIACARD_IRQ# GPP_D0/SPI1_CS# AY13
GPP_A1/LAD0/ESPI_IO0 BA13 LPC_LAD0 <31,32> MEM_SMBCLK 1 2
GPP_A2/LAD1/ESPI_IO1 LPC_LAD1 <31,32>
1
C LINK
10K_0402_5%
10K_0402_5%
BB13 RC12 1K_0402_5%

GPP_A3/LAD2/ESPI_IO2 LPC_LAD2 <31,32> MEM_SMBDATA
RC13
G3 AY12 1 2
<29> PCH_CL_CLK1 CL_CLK GPP_A4/LAD3/ESPI_IO3 LPC_LAD3 <31,32>
RC268
G2 BA12 RC14 1K_0402_5%

<29> PCH_CL_DATA1 G1 CL_DATA GPP_A5/LFRAME#/ESPI_CS# BA11 SUS_STAT# LPC_LFRAME# <31,32> SML1_SMBCLK 1 2
<29> PCH_CL_RST1# CL_RST# GPP_A14/SUS_STAT#/ESPI_RESET# Reserve RC15 1K_0402_5%
2
SML1_SMBDATA 1 2
AW13 AW9 PCI_CLK_LPC0 EMC@ RC16 1 2 22_0402_5% RC17 1K_0402_5%
<32> SIO_RCIN# GPP_A0/RCIN# GPP_A9/CLKOUT_LPC0/ESPI_CLK AY9 PCI_CLK_LPC1 CLK_PCI_5048 <31> SUS_STAT# 1 2
AY11 GPP_A10/CLKOUT_LPC1 AW11 EMC@ RC18 1 2 22_0402_5% Reserve @ RC26 10K_0402_5%
<31,32> IRQ_SERIRQ GPP_A6/SERIRQ GPP_A8/CLKRUN# CLK_PCI_MEC <32> SML0_SMBCLK 1 2
DIMM Detect +3.3V_RUN RC21 1 2 10K_0402_1% RC347 499_0402_1%
SKL-U_BGA1356 5 OF 20 EMC@ RC22 1 2 22_0402_5% SML0_SMBDATA 1 2
CLK_PCI_LPDEBUG <32> RC348 499_0402_1%
HIGH 1 DIMM CLKRUN# <31,32>
EMC@ RC24 1 2 22_0402_5%
LOW 2 DIMM CLK_PCI_DOCK <38> +3.3V_RUN
8/5 CKLT0.9
CLKRUN# 1 2
C CLK_PCI_5048 2 1 RC27 8.2K_0402_5% C
27P_0402_50V8J EMC@
SOFTWARE TAA CC3
FFS_INT2 1 2
PCH_SPI_CLK_1_R PCH_SPI_CLK_0_R CLK_PCI_MEC 2 1 RC322 10K_0402_5%
27P_0402_50V8J EMC@
CC4
2
2
33_0402_5%
33_0402_5%
CLK_PCI_LPDEBUG +3.3V_ALW_PCH
RC28
@EMC@
RC29
@EMC@
RPC1 2 1
27P_0402_50V8J EMC@
PCH_SPI_D1_R1 1 8 PCH_SPI_D1_0_R CC5
<33> PCH_SPI_D1_R1 PCH_SPI_D0_R1 2 7 PCH_SPI_D0_0_R
+3.3V_SPI
1
<33> PCH_SPI_D0_R1 PCH_SPI_CLK_R1 3 6 PCH_SPI_CLK_0_R CLK_PCI_DOCK 2 1 PCH_SMB_ALERT# 2 1

<33> PCH_SPI_CLK_R1 PCH_SPI_D3_R1 PCH_SPI_D3_0_R
33P_0402_50V8J
33P_0402_50V8J
4 5 27P_0402_50V8J EMC@ RC23 2.2K_0402_5%

1 2 PCH_SPI_D2_R1 CC6
2
2
CC7
@EMC@
CC8
@EMC@
@RC30 1K_0402_5% 33_0804_8P4R_5%

1 2 PCH_SPI_D3_R1
TLS CONFIDENTIALITY
@ RC31 1K_0402_5% Reserve for RF HIGH ENABLE
1
1 2 PCH_SPI_D3_R1 @RPC2 LOW(DEFAULT) DISABLE

@RC316 1K_0402_5%
PCH_SPI_D3_R1 1 8 PCH_SPI_D3_1_R
PCH_SPI_CLK_R1 2 7 PCH_SPI_CLK_1_R
+3.3V_ALW_PCH
33_0804_8P4R_5%
E-T_6705K-Y20N-00L
9/5 MOW 22 GPP_C5 1 2
Option 1: Implement a 1 kOhm pull-down resistor on the signal and de-populate the 21 GND2 @ RC25 10K_0402_5%
required 1 kOhm pull-up resistor. In this case, customers must ensure that the SPI 2 1 PCH_SPI_CS#1_R120 GND1
B
flash device on the platform has HOLD functionality disabled by default. @RC32 0_0402_5% PCH_SPI_CS#1 19 20 B
2 1 PCH_SPI_D0_R1 18 19
RC33 0_0402_5% PCH_SPI_D0 17 18
EC interface
Note that the pull down resistor on SPI0_IO3 is only needed for SKL U/Y platforms 2 1 PCH_SPI_D1_R1 16 17
PCH_SPI_D1 15 16
HIGH ESPI
with ES and SKL S/H platforms with pre-ES1/ES1 samples. RC34 0_0402_5%
LOW(DEFAULT) LPC
2 1 PCH_SPI_CLK_R1 14 15
+3.3V_SPI RC35 0_0402_5% PCH_SPI_CLK 13 14
2 1 PCH_SPI_CS#0_R112 13
CC9 RC36 0_0402_5% PCH_SPI_CS#0 11 12
1 2 2 1 PCH_SPI_D2_R1 10 11
RC38 0_0402_5% PCH_SPI_D2 9 10
128Mb Flash ROM 0.1U_0201_10V6K 2 1 PCH_SPI_D3_R1 8 9 +3.3V_RUN +3.3V_ALW_PCH
UC5 PCH_SPI_D3 7 8
RC40 0_0402_5%
PCH_SPI_CS#0_R1 PCH_SPI_CS#0_R2 6 7
150K_0402_5%
150K_0402_5%
@ RC37 1 2 0_0402_5% 1 8
/CS VCC +3.3V_SPI
5 6
2
PCH_SPI_D1_0_R 2 7 PCH_SPI_D3_0_R 2 1
DO(IO1) /HOLD(IO3) +3.3V_ALW_PCH @
4 5
@
PCH_SPI_D2_R1 RC39 1 2 33_0402_5% PCH_SPI_D2_0_R 3 6 PCH_SPI_CLK_0_R RC289 0_0402_5% 2 1
/WP(IO2) CLK PCH_SPI_D0_0_R 3 4
RC326
RC317
4 5 2 1 @ RC327 0_0402_5%
GND DI(IO0) +3.3V_M
@ RC276 0_0402_5% 2 3
1 2
1
W25Q128FVSIQ_SO8 2 1 +3.3V_SPI_R 1 GPP_B23 3 1 GPP_B23_Q
D
+3.3V_SPI @ RC41 0_0402_5% @ QC3
JSPI1
CONN@ L2N7002WT1G_SC-70-3
@ CC10
G
2
1 2 2 1
64Mb Flash ROM <11,32> SIO_SLP_A# @ RC339 0_0402_5%
0.1U_0201_10V6K
UC6 @ 2 1
PCH_SPI_CS#1_R1 PCH_SPI_CS#1_R2 <11,17,18,32,41,46,47,48> SIO_SLP_SUS#
@RC42 1 2 0_0402_5% 1
/CS VCC
8 @ RC340 0_0402_5% EXI BOOT STALL BYPASS
PCH_SPI_D1_1_R 2 7 PCH_SPI_D3_1_R
PCH_SPI_D2_R1 PCH_SPI_D2_1_R DO(IO1) /HOLD(IO3) PCH_SPI_CLK_1_R
@RC43 1 2 33_0402_5% 3
/WP(IO2) CLK
6
HIGH ENABLED
4 5 PCH_SPI_D0_1_R
GND DI(IO0) LOW(DEFAULT) DIABLED
A W25Q64FVSSIQ_SO8 WEAK INTERNAL PD A
5 4 3 2 1
5 4 3 2 1
+3.3V_ALW_PCH
+3.3V_RUN
8/21 KB_DET# 1 2
RC288 10K_0402_5%
UC1F SKL-U
Vinafix.com AN8
LPSS ISH
1 2 3.3V_TP_EN Reserve AP7 GPP_B15/GSPI0_CS# P2 DIMM_TYPE

D RC270 10K_0402_5% AP8 GPP_B16/GSPI0_CLK GPP_D9 P3 D
NRB_BIT AR7 GPP_B17/GSPI0_MISO GPP_D10 P4
1 2 TS_EN GPP_B18/GSPI0_MOSI GPP_D11 P1
RC282 100K_0402_5% Reserve 3.3V_TP_EN AM5 GPP_D12
1 2 LPSS_UART2_TXD AN7 GPP_B19/GSPI1_CS# M4
<32> SIO_EXT_SCI# AP5 GPP_B20/GSPI1_CLK GPP_D5/ISH_I2C0_SDA N3
@ RC335 49.9K_0402_1%
1 2 LPSS_UART2_RXD <26> TS_EN AN5 GPP_B21/GSPI1_MISO GPP_D6/ISH_I2C0_SCL
<42> HDD_EN GPP_B22/GSPI1_MOSI N1
@ RC336 49.9K_0402_1%
1 2 AUD_PWR_EN AB1 GPP_D7/ISH_I2C1_SDA N2
RC279 10K_0402_5% AB2 GPP_C8/UART0_RXD GPP_D8/ISH_I2C1_SCL 9/24: Reserve for embedded location ,refer Intel PDG 0.9
1 2 HOST_SD_WP# <32> UART0_TXD W4 GPP_C9/UART0_TXD AD11
RC292 10K_0402_5% AB3 GPP_C10/UART0_RTS# GPP_F10/I2C5_SDA/ISH_I2C2_SDA AD12 ISH_I2C2_SDA <29> WWAN
<28> HOST_SD_WP# GPP_C11/UART0_CTS# GPP_F11/I2C5_SCL/ISH_I2C2_SCL ISH_I2C2_SCL <29>
2 1 SIO_EXT_SCI# LPSS_UART2_RXD AD1 +3.3V_RUN
RC237 10K_0402_5% LPSS_UART2_TXD AD2 GPP_C20/UART2_RXD U1
AD3 GPP_C21/UART2_TXD GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA U2 ISH_UART0_RXD <29>
<32> SIO_EXT_WAKE# AD4 GPP_C22/UART2_RTS# GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL U3 ISH_UART0_TXD <29>
Reserve
GPP_C23/UART2_CTS# GPP_D15/ISH_UART0_RTS# U4 ISH_UART0_RTS# <29> WLAN
+3.3V_ALW_PCH GPP_D16/ISH_UART0_CTS#/SML0BALERT# ISH_UART0_CTS# <29>
U7 AC1
U6 GPP_C16/I2C0_SDA GPP_C12/UART1_RXD/ISH_UART1_RXD AC2 LCD_CBL_DET# 1 2
GPP_C17/I2C0_SCL GPP_C13/UART1_TXD/ISH_UART1_TXD AC3 RC287 100K_0402_5%
1 2 SIO_EXT_WAKE# U8 GPP_C14/UART1_RTS#/ISH_UART1_RTS# AB4 LCD_CBL_DET# <26>
<39> I2C_1_SDA U9 GPP_C18/I2C1_SDA GPP_C15/UART1_CTS#/ISH_UART1_CTS# IR_CAM_DET# 1 2
RC283 10K_0402_5%
<39> I2C_1_SCL GPP_C19/I2C1_SCL AY8 CLKDET# RC346 100K_0402_5%
1 2 LPSS_UART2_RXD AH9 GPP_A18/ISH_GP0 BA8 PAD~D @ T121
AH10 GPP_F4/I2C2_SDA GPP_A19/ISH_GP1 BB7 VMM3320_LPM_DIS <24>
RC330 49.9K_0402_1%
GPP_F5/I2C2_SCL GPP_A20/ISH_GP2 BA7 KB_DET# <39>
1 2 LPSS_UART2_TXD AH11 GPP_A21/ISH_GP3 AY7 NON_DOCK AUD_PWR_EN <30>
RC331 49.9K_0402_1% AH12 GPP_F6/I2C3_SDA GPP_A22/ISH_GP4 AW7
GPP_F7/I2C3_SCL GPP_A23/ISH_GP5 AP13 IR_CAM_DET# <26>
AF11 GPP_A12/BM_BUSY#/ISH_GP6
C AF12 GPP_F8/I2C4_SDA C
GPP_F9/I2C4_SCL NON_DOCK 1 2
@ RH359 100_0402_1%
+3.3V_ALW_PCH
1 2 NRB_BIT
@ RC186 4.7K_0402_5%
NO REBOOT STRAP +3.3V_ALW_PCH

HIGH No REBOOT
LOW(DEFAULT) REBOOT ENABLE +5V_ALW
Weak IPD
1
@RC341
JUART1 10K_0402_5%
1
LPSS_UART2_TXD 2 1
2
LPSS_UART2_RXD 3 2 DIMM_TYPE
4 3
4
1
B 5 B
+3.3V_ALW_PCH 6 GND RC342
GND
10K_0402_5%
ACES_50207-00471-P01
DIMM_TYPE
2
1
@ RC184 HIGH DDR3L

8.2K_0402_5%
LOW DDR4
2
HDD_EN
BOOT BIOS Destination(Bit 10)

HIGH LPC
LOW(DEFAULT) SPI
A A
5 4 3 2 1
5 4 3 2 1
UC1H SKL-U
Vinafix.com PCIE/USB3/SATA
SSIC / USB3
USB3_1_RXN
H8
G8 USB3_PRX_DTX_N1 <36>
H13 USB3_1_RXP C13 USB3_PRX_DTX_P1 <36>
D <29> USB3_PRX_DTX_N5 G13 PCIE1_RXN/USB3_5_RXN USB3_1_TXN D13 USB3_PTX_DRX_N1 <36> -----> Ext USB3 Port 3 Charge(RIGHT) D
WWAN <29> USB3_PRX_DTX_P5 B17 PCIE1_RXP/USB3_5_RXP USB3_1_TXP USB3_PTX_DRX_P1 <36>
<29> USB3_PTX_DRX_N5 A17 PCIE1_TXN/USB3_5_TXN J6
<29> USB3_PTX_DRX_P5 PCIE1_TXP/USB3_5_TXP USB3_2_RXN/SSIC_1_RXN H6 USB3_PRX_DTX_N2 <38>
G11 USB3_2_RXP/SSIC_1_RXP B13 USB3_PRX_DTX_P2 <38>
F11 PCIE2_RXN/USB3_6_RXN USB3_2_TXN/SSIC_1_TXN A13 USB3_PTX_DRX_N2 <38> -----> EDOCK
D16 PCIE2_RXP/USB3_6_RXP USB3_2_TXP/SSIC_1_TXP USB3_PTX_DRX_P2 <38>
C16 PCIE2_TXN/USB3_6_TXN J10
PCIE2_TXP/USB3_6_TXP USB3_3_RXN/SSIC_2_RXN H10 USB3_PRX_DTX_N3 <37>
H16 USB3_3_RXP/SSIC_2_RXP B15 USB3_PRX_DTX_P3 <37>
<29> PCIE_PRX_DTX_N3 G16 PCIE3_RXN USB3_3_TXN/SSIC_2_TXN A15 USB3_PTX_DRX_N3 <37> -----> Ext USB3 Port 1(LEFT)
<29> PCIE_PRX_DTX_P3 D17 PCIE3_RXP USB3_3_TXP/SSIC_2_TXP USB3_PTX_DRX_P3 <37>
WWAN ---> <29> PCIE_PTX_DRX_N3 C17 PCIE3_TXN E10
<29> PCIE_PTX_DRX_P3 PCIE3_TXP USB3_4_RXN F10 USB3_PRX_DTX_N4 <37>
G15 USB3_4_RXP C15 USB3_PRX_DTX_P4 <37>
F15 PCIE4_RXN USB3_4_TXN D15 USB3_PTX_DRX_N4 <37> -----> Ext USB3 Port 2(REAR LEFT)
B19 PCIE4_RXP USB3_4_TXP USB3_PTX_DRX_P4 <37>
A19 PCIE4_TXN AB9
PCIE4_TXP USB2N_1 AB10 USB20_N1 <36>
F16 USB2P_1 USB20_P1 <36> -----> Ext USB Port 3 Charge(RIGHT)
<29> PCIE_PRX_DTX_N5 E16 PCIE5_RXN AD6
<29> PCIE_PRX_DTX_P5 C19 PCIE5_RXP USB2N_2 AD7 USB20_N2 <26>
WLAN ---> <29> PCIE_PTX_DRX_N5 D19 PCIE5_TXN USB2P_2 USB20_P2 <26> -----> Camera
<29> PCIE_PTX_DRX_P5 PCIE5_TXP AH3
G18 USB2N_3 AJ3 USB20_N3 <37>
<29> PCIE_PRX_DTX_N6 F18 PCIE6_RXN USB2P_3 USB20_P3 <37> -----> Ext USB Port 1(LEFT)
<29> PCIE_PRX_DTX_P6 D20 PCIE6_RXP AD9
WIGIG---> <29> PCIE_PTX_DRX_N6 C20 PCIE6_TXN USB2N_4 AD10 USB20_N4 <37>
<29> PCIE_PTX_DRX_P6 PCIE6_TXP USB2P_4 USB20_P4 <37> -----> Ext USB Port 2(REAR LEFT)
F20 AJ1
<42> SATA_PRX_DTX_N0 E20 PCIE7_RXN/SATA0_RXN USB2N_5 AJ2 USB20_N5 <38>
<42> SATA_PRX_DTX_P0 B21 PCIE7_RXP/SATA0_RXP USB2P_5 USB20_P5 <38> -----> EDOCK PORT1
C SATA HDD---> <42> SATA_PTX_DRX_N0 A21 PCIE7_TXN/SATA0_TXN
USB2
AF6 C
<42> SATA_PTX_DRX_P0 PCIE7_TXP/SATA0_TXP USB2N_6 AF7 USB20_N6 <38>
G21 USB2P_6 USB20_P6 <38> -----> EDOCK PORT2
<38> SATA_PRX_DTX_N1 F21 PCIE8_RXN/SATA1A_RXN AH1
<38> SATA_PRX_DTX_P1 D21 PCIE8_RXP/SATA1A_RXP USB2N_7 AH2 USB20_N7 <33>
E DOCK ESATA---> <38> SATA_PTX_DRX_N1 C21 PCIE8_TXN/SATA1A_TXN USB2P_7 USB20_P7 <33> -----> USH
<38> SATA_PTX_DRX_P1 PCIE8_TXP/SATA1A_TXP AF8
E22 USB2N_8 AF9 USB20_N8 <29>
<27> PCIE_PRX_DTX_N9 E23 PCIE9_RXN USB2P_8 USB20_P8 <29> -----> BT
<27> PCIE_PRX_DTX_P9 B23 PCIE9_RXP AG1
10/100/1G LAN ---> <27> PCIE_PTX_DRX_N9 A23 PCIE9_TXN USB2N_9 AG2 USB20_N9 <26>
<27> PCIE_PTX_DRX_P9 PCIE9_TXP USB2P_9 USB20_P9 <26> -----> LCD Touch
F25 AH7
<28> PCIE_PRX_DTX_N10 E25 PCIE10_RXN USB2N_10 AH8 USB20_N10 <29>
<28> PCIE_PRX_DTX_P10 D23 PCIE10_RXP USB2P_10 USB20_P10 <29>-----> M2 3042(WWAN) +3.3V_ALW_PCH
Card Reader ---> <28> PCIE_PTX_DRX_N10 C23 PCIE10_TXN AB6 USBCOMP RC44 1 2 113_0402_1% 8/19 for layout routing change
<28> PCIE_PTX_DRX_P10 PCIE10_TXP USB2_COMP AG3 @ RC3371 2 0_0402_5%
PCIE_RCOMPN F5 USB2_ID AG4 RC3381 2 1K_0402_5% RPC3
RC45 1 2 100_0402_1% PCIE_RCOMPP E5 PCIE_RCOMPN USB2_VBUSSENSE USB_OC0# 4 5
PCIE_RCOMPP A9 USB_OC3# 3 6
D56 GPP_E9/USB2_OC0# C9 USB_OC0# <36> USB_OC1# 2 7
<14> CPU_XDP_PRDY# D61 PROC_PRDY# GPP_E10/USB2_OC1# D9 USB_OC1# <37> USB_OC2# 1 8
<14> CPU_XDP_PREQ# BB11 PROC_PREQ# GPP_E11/USB2_OC2# B9 USB_OC3# USB_OC2# <37>
Reserve
<42> HDD_FALL_INT GPP_A7/PIRQA# GPP_E12/USB2_OC3# 10K_8P4R_5% +3.3V_RUN
E28 J1
<34> PCIE_PRX_DTX_N11 E27 PCIE11_RXN/SATA1B_RXN GPP_E4/DEVSLP0 J2 HDD_DEVSLP <42>
<34> PCIE_PRX_DTX_P11 D24 PCIE11_RXP/SATA1B_RXP GPP_E5/DEVSLP1 J3 RPC4
<34> PCIE_PTX_DRX_N11 C24 PCIE11_TXN/SATA1B_TXN GPP_E6/DEVSLP2 M2_DEVSLP <35> HDD_FALL_INT 4 5
<34> PCIE_PTX_DRX_P11 E30 PCIE11_TXP/SATA1B_TXP H2 IFDET_SATA#_PCIE 3 6
SATA EXPRESS HDD ---> <34> PCIE_PRX_DTX_N12 F30 PCIE12_RXN/SATA2_RXN GPP_E0/SATAXPCIE0/SATAGP0 H3 SATAGP1 Reserve
HDD_DET# <42> PCH_SATA_LED# 2 7
<34> PCIE_PRX_DTX_P12 A25 PCIE12_RXP/SATA2_RXP GPP_E1/SATAXPCIE1/SATAGP1 G4 HDD_DET# 1 8
<34> PCIE_PTX_DRX_N12 B25 PCIE12_TXN/SATA2_TXN GPP_E2/SATAXPCIE2/SATAGP2 IFDET_SATA#_PCIE <34,35>
B <34> PCIE_PTX_DRX_P12 PCIE12_TXP/SATA2_TXP H1 10K_8P4R_5% B
GPP_E8/SATALED# PCH_SATA_LED# <35,40>
+3.3V_ALW_PCH
SATAGP1 1 2
RC246 10K_0402_5%
CKLT0.9
A A
5 4 3 2 1
5 4 3 2 1
CC21
1 2
SUSCLK 1 2
@ RC48 1K_0402_5% 15P_0402_50V8J
2
1M_0402_1%
3
4
RC46
UC1J SKL_ULT
YC1
CLOCK SIGNALS 24MHZ_12PF_X3G024000DC1H
1
2
D42
Vinafix.com
<29> CLK_PCIE_N0 C42 CLKOUT_PCIE_N0 XTAL24_IN CC22
<29> CLK_PCIE_P0 AR10 CLKOUT_PCIE_P0 XTAL24_OUT 1 2 XTAL24_OUT_R 1 2
WWAN <29> CLKREQ_PCIE#0
RC189 1 2 10K_0402_5% GPP_B5/SRCCLKREQ0# @ RC295 0_0402_5%
+3.3V_RUN
B42 15P_0402_50V8J
D <29> CLK_PCIE_N1 A42 CLKOUT_PCIE_N1 F43 CLK_ITPXDP_N 1 2 0_0402_5% D
@ RC297 For Skylake YC1 24MHz(50 Ohm ESR)
<29> CLK_PCIE_P1 AT7 CLKOUT_PCIE_P1 CLKOUT_ITPXDP_N E43 CLK_ITPXDP_P 1 2 0_0402_5% CLK_ITPXDP_N_R <14>
WLAN---> @ RC298
<29> CLKREQ_PCIE#1
RC47 1 2 10K_0402_5% GPP_B6/SRCCLKREQ1# CLKOUT_ITPXDP_P CLK_ITPXDP_P_R <14> For Cannonlake YC1 38.4MHz(30 Ohm ESR)
+3.3V_RUN
<29> CLK_PCIE_N2
D41
CLKOUT_PCIE_N2 GPD8/SUSCLK
BA17
SUSCLK <29,35>
546765_546765_2014WW48_Skylake_MOW_Rev_1_0
C41
<29> CLK_PCIE_P2 AT8 CLKOUT_PCIE_P2 E37 XTAL24_IN For Skylake pop RC52 and depop RC324
WIGIG---> <29> CLKREQ_PCIE#2
RC50 1 2 10K_0402_5% GPP_B7/SRCCLKREQ2# XTAL24_IN E35 XTAL24_OUT For Cannonlake depop RC52 and pop RC324
+3.3V_RUN XTAL24_OUT
<35> CLK_PCIE_N3
D40
CLKOUT_PCIE_N3
546765_546765_2014WW48_Skylake_MOW_Rev_1_0
C40 E42 XCLK_BIASREF 1 2
<35> CLK_PCIE_P3 CLKOUT_PCIE_P3 XCLK_BIASREF +1.0V_CLK5
AT10 RC52 2.7K_0402_1%
SATA EXPRESS HDD---> <35> CLKREQ_PCIE#3
RC59 1 2 10K_0402_5% GPP_B8/SRCCLKREQ3# AM18 PCH_RTCX1 1 2
+3.3V_RUN RTCX1 PCH_RTCX2
B40 AM20 @ RC324 59_0402_1%
<27> CLK_PCIE_N4 A40 CLKOUT_PCIE_N4 RTCX2
<27> CLK_PCIE_P4 AU8 CLKOUT_PCIE_P4 AN18 1 2 20K_0402_5%
SRTCRST# RC56
LAN---> <27> CLKREQ_PCIE#4
RC51 1 2 10K_0402_5% GPP_B9/SRCCLKREQ4# SRTCRST# AM16
+RTC_CELL
+3.3V_RUN RTCRST#
E40 CC24 1 2 1U_0402_6.3V6K CC23
<28> CLK_PCIE_N5 E38 CLKOUT_PCIE_N5 PCH_RTCX1 2 1
<28> CLK_PCIE_P5 AU7 CLKOUT_PCIE_P5 PCH_RTCX2
MMI ---> <28> CLKREQ_PCIE#5
RC190 1 2 10K_0402_5% GPP_B10/SRCCLKREQ5# PCH_RTCRST# RC57 1 2 20K_0402_5% 5P_0402_50V8C
+3.3V_RUN
1
CC25 1 2 1U_0402_6.3V6K
RC54 YC2
SKL-U_BGA1356 10 OF 20 32.768KHZ 9PF10PPM 9H03200055
10M_0402_5%
H_CPUPWRGD VCCST_PWRGD ESR MAX=50k ohm
2
PCH_PLTRST# 0_0402_5% 2 1 RC61 @ 1 2
PLTRST_VMM2320# <24>
1
1 2
100P_0402_50V8J
EMC@ CC300
100P_0402_50V8J
@EMC@ CC301
0_0402_5% 2 1 RC62 @ CC26

2 1 RC64 @ PLTRST_LAN# <27> 1 2 PCH_RTCX2_R 2 1
0_0402_5%
PLTRST_5048# <31>
1
0_0402_5% 2 1RC244 @ @ RC296 0_0402_5%

2 1 RC60 @ PCH_PLTRST#_EC <32> SHORT PADS~D
0_0402_5% 5P_0402_50V8C
2 1RC325 @ PLTRST_TPM# <33> @ CMOS1
0_0402_5%
2
CMOS1 must take care short & touch risk on layout placement
C C
+3.3V_ALW_PCH
ESD Request:place near CPU side
5
1
P
B 4 PCH_PLTRST#_AND
2 O PCH_PLTRST#_AND <28,29,33,35> +3.3V_ALW_PCH
A
G
1
UC7
TC7SH08FU_SSOP5~D @ RC65 1 2
3
100K_0402_5% @ RC344 10K_0402_5%

+3.3V_ALW +RTC_CELL
2
+3.3V_ALW_DSW
1 2 PCH_PCIE_WAKE# SIO_SLP_LAN# 1 2 INTRUDER# 1 2

RC67 1K_0402_5% @ RC68 10K_0402_5% RC69 1M_0402_5%
1 2 LAN_WAKE#
+1.0V_VCCST RC323 10K_0402_5% +3.3V_ALW_DSW
8/21 can change to 10K for merge to RP +3.3V_ALW +3.3V_ALW_PCH
1 2 VCCST_PWRGD
RC71 1K_0402_5% +3.3V_RUN PCH_BATLOW# 1 2
RC72 8.2K_0402_5% VRALERT# 1 2
+3.3V_ALW_PCH AC_PRESENT 1 2 @ RC73 10K_0402_5%
1 2 ME_RESET# RC243 10K_0402_5%
1 2 ME_SUS_PWR_ACK @ RC225 8.2K_0402_5% UC1K SKL-U 1 2
@ RC74 10K_0402_5% RC343 10K_0402_5%
10/6 depop, prevent singal step. SYSTEM POWER MANAGEMENT
AT11 JAPS1
GPP_B12/SLP_S0# AP15 SIO_SLP_S0# <17,33,47> SLP_S0# for support connect stand by mode 1
PCH_PLTRST# GPD4/SLP_S3# SIO_SLP_S3# <17,32,48> +3.3V_ALW_PCH SIO_SLP_S3# 1
AN10 BA16 2
<14,39> PCH_RSMRST#_Q SYS_RESET# B5 GPP_B13/PLTRST# GPD5/SLP_S4# AY16 SIO_SLP_S4# <17,32,45,54> 3 2
B PCH_RSMRST#_Q AY17 SYS_RESET# GPD10/SLP_S5# SIO_SLP_S5# <32> +3.3V_ALW_DSW SIO_SLP_S5# 3 B
RC75 1 2 10K_0402_5% 8/21 CRB1.0 change to 0603 1/10W 4
RSMRST# AN15 SIO_SLP_S4# 5 4
H_CPUPWRGD_R@ RC77 1 2 1K_0402_5% H_CPUPWRGD A68 SLP_SUS# AW15 SIO_SLP_SUS# <8,17,18,32,41,46,47,48> SIO_SLP_A# 6 5
T9 @ PAD~D PROCPWRGD SLP_LAN# SIO_SLP_LAN# <32,41> 6
RC78 1 2 60.4_0402_1% VCCST_PWRGD_CPU B65 BB17 7
<14,32> VCCST_PWRGD VCCST_PWRGD GPD9/SLP_WLAN# SIO_SLP_WLAN# <31,41> +3.3V_ALW_DSW 7
AN16 8
B6 GPD6/SLP_A# SIO_SLP_A# <8,32> PCH_RTCRST# 9 8
<14,32> RESET_OUT# BA20 SYS_PWROK BA15 10 9
<49> PCH_PWROK BB20 PCH_PWROK GPD3/PWRBTN# AY15 SIO_PWRBTN# <14,32> 11 10
<32> PCH_DPWROK DSW_PWROK GPD1/ACPRESENT AU13 PCH_BATLOW# AC_PRESENT <32> <32,40> POWER_SW#_MB 12 11
AR13 GPD0/BATLOW# SYS_RESET# 13 12
<32> ME_SUS_PWR_ACK AP11 GPP_A13/SUSWARN#/SUSPWRDNACK 14 13
<32> SUSACK# GPP_A15/SUSACK# AU11 SIO_SLP_S0# 15 14
PME#
BB15 GPP_A11/PME# AP16 INTRUDER# PAD~D @ T115 16 15
<31,32> PCH_PCIE_WAKE# AM15 WAKE# INTRUDER# 17 16
<27,32> LAN_WAKE# AW17 GPD2/LAN_WAKE# AM10 18 17
<27> PM_LANPHY_ENABLE AT15 GPD11/LANPHYPC GPP_B11/EXT_PWR_GATE# AM11 VRALERT# MPHYP_PWR_EN <18> 19 18
<26> 3.3V_CAM_EN# GPD7/RSVD GPP_B2/VRALERT# 20 GND
connect to VCCMPHYGTAON_1P0 enable pin GND
RC215 1 2 SKL-U_BGA1356 11 OF 20 CONN@
POP NO Support Deep sleep RC311 10K_0402_5% ACES_50506-01841-P01
SYS_RESET#
DE-POP Support Deep sleep 8/28 schematic review
0.1U_0402_25V6
@EMC@
PCH_DPWROK 1 2 PCH_RSMRST#_Q
1
@ RC215 0_0402_5% 1 2 +3.3V_RUN
@ RC290 0_0402_5%
1
10K_0402_5%
0.01UF_0402_25V7K
100K_0402_1%
2
1
CC302
+3.3V_RUN
CC266
RC220
@ RC291
2
2
A XDP_DBRESET# 1 ESD Request:place near CPU side A

P
<14> XDP_DBRESET# B 4 SYS_RESET#_R 1 2 SYS_RESET#

2 1 ME_RESET# 2 O RC224 1K_0402_5%
A
G
@ RC227 8.2K_0402_5% @ UC12

74AHC1G09GW_TSSOP5
3

if pop UC12, RC291 also need pop(74AHC1G09GW is OD output)
5 4 3 2 1
5 4 3 2 1
+1.0V_VCCST
8/21 DG0.9 +1.0V_VCCSTG
1 2 H_CATERR#
@ RC79 49.9_0402_1%
1 2 H_THERMTRIP#
RC80 1K_0402_5% PCH_JTAG_TDI 2 1 RC81
51_0402_5%
+1.0V_VCCSTG PCH_JTAG_TDO 2 1 RC82
8/19 DG0.9 100_0402_1%
1 2 H_PROCHOT# PCH_JTAG_TMS 2 1 RC130
RC83 1K_0402_5%
Vinafix.com H_CATERR# D63
UC1D SKL-U 51_0402_5%
+3.3V_RUN <32> PECI_EC A54 CATERR#

8/19 DG0.9
D 1 2 H_PROCHOT#_R C65 PECI D
<32,49,51> H_PROCHOT# PROCHOT# JTAG
1 2 TOUCHPAD_INTR# RC84 499_0402_1% H_THERMTRIP# C63
<20,21,32> H_THERMTRIP# A65 THERMTRIP# B61 CPU_XDP_TCLK
RC272 10K_0402_5%
SKTOCC# PROC_TCK D60 CPU_XDP_TDI CPU_XDP_TCLK <14>
RPC5 CPU MISC
4 5 C55 PROC_TDI A61 CPU_XDP_TDO CPU_XDP_TDI <14>
3 6 TOUCH_SCREEN_PD# <14> XDP_OBS0_R D55 BPM#[0] PROC_TDO C60 CPU_XDP_TMS CPU_XDP_TDO <14>
2 7 CAM_MIC_CBL_DET# <14> XDP_OBS1_R XDP_OBS2_R B54 BPM#[1] PROC_TMS B59 CPU_XDP_TRST# CPU_XDP_TMS <14>
CONTACTLESS_DET# T10 @ PAD~D XDP_OBS3_R C56 BPM#[2] PROC_TRST# CPU_XDP_TRST# <14>
1 8
T11 @ PAD~D BPM#[3] PCH_JTAG_TCK PCH_JTAG_TCK <14> 2
B56 1
10K_8P4R_5% A6 PCH_JTAG_TCK D59 PCH_JTAG_TDI @ RC86 51_0402_5%
<32> SIO_EXT_SMI# A7 GPP_E3/CPU_GP0 PCH_JTAG_TDI A56 PCH_JTAG_TDO PCH_JTAG_TDI <14>
<26> TOUCH_SCREEN_PD# BA5 GPP_E7/CPU_GP1 PCH_JTAG_TDO C59 PCH_JTAG_TMS PCH_JTAG_TDO <14>
+3.3V_ALW_PCH <39> TOUCHPAD_INTR# AY5 GPP_B3/CPU_GP2 PCH_JTAG_TMS C61 CPU_XDP_TRST# PCH_JTAG_TMS <14>
<26> TOUCH_SCREEN_DET# GPP_B4/CPU_GP3 PCH_TRST# A59 XDP_JTAGX 1 2
CPU_POPIRCOMP AT16 JTAGX +1.0V_VCCSTG
@ RC87 1K_0402_5%
PCH_POPIRCOMP AU16 PROC_POPIRCOMP 2 1 CPU_XDP_TCLK
1 2 SIO_EXT_SMI# EDRAM_OPIO_RCOMP H66 PCH_OPIRCOMP @ RC328 0_0402_5%
RC236 10K_0402_5% EOPIO_RCOMP H65 OPCE_RCOMP
OPC_RCOMP
1
49.9_0402_1%
49.9_0402_1%
49.9_0402_1%
49.9_0402_1%
RC88
RC89
RC90
RC91
Service Mode Switch:

Add a switch to ME_FWP signal to unlock the ME region and
2
allow the entire region of the SPI flash to be updated using FPT.
+3.3V_ALW_PCH
ME_FWP_EC 2 1 ME_FWP
@ RC221 0_0402_5%
1
PT,ST pop RC222 and SW1; MP pop RC221
C @RC222 C
1K_0402_5%
2
@ SW1
1
<31> ME_FWP_EC A
2
ME_FWP 3 B
4 C
5 G1
G2
SS3-CMFTQR9_3P
ME_FWP PCH has internal 20K PD.
(suspend power rail)
UC1G SKL-U
FLASH DESCRIPTOR SECURITY OVERRIDE
AUDIO LOW = ENABLE (DEFAULT) -->Pin1 & Pin3 short
RC92 1 2 33_0402_5% HDA_SYNC BA22 HIGH = DISABLE (ME can update) -->Pin2 & Pin3 short
<30> HDA_SYNC_R 1 2 HDA_BIT_CLK AY22 HDA_SYNC/I2S0_SFRM
EMC@ RC93 33_0402_5%
<30> HDA_BIT_CLK_R 1 2 HDA_SDOUT BB22 HDA_BLK/I2S0_SCLK
RC94 33_0402_5% SDIO/SDXC
<30> HDA_SDOUT_R ME_FWP RC223 1 2 BA21 HDA_SDO/I2S0_TXD
1K_0402_5%
<30> HDA_SDIN0 AY21 HDA_SDI0/I2S0_RXD AB11
1 2 33_0402_5% HDA_RST# AW22 HDA_SDI1/I2S1_RXD GPP_G0/SD_CMD AB13 CAM_MIC_CBL_DET# <26>
RC95
<30> HDA_RST#_R J5 HDA_RST#/I2S1_SCLK GPP_G1/SD_DATA0 AB12
AY20 GPP_D23/I2S_MCLK GPP_G2/SD_DATA1 W12
AW20 I2S1_SFRM GPP_G3/SD_DATA2 W11 CONTACTLESS_DET#
HDA_BIT_CLK_R I2S1_TXD GPP_G4/SD_DATA3 W10 CONTACTLESS_DET# <33>
AK7 GPP_G5/SD_CD# W8
AK6 GPP_F1/I2S2_SFRM GPP_G6/SD_CLK W7
1 GPP_F0/I2S2_SCLK GPP_G7/SD_WP
AK9
B CC27 AK10 GPP_F2/I2S2_TXD BA9 B
GPP_F3/I2S2_RXD GPP_A17/SD_PWR_EN#/ISH_GP7 BB9
22P_0402_50V8J GPP_A16/SD_1P8_SEL
2
H5 AB7 SD_RCOMP RC96 1 2 200_0402_1%
D7 GPP_D19/DMIC_CLK0 SD_RCOMP
Close to RC93 GPP_D20/DMIC_DATA0
D8 AF13
C8 GPP_D17/DMIC_CLK1 GPP_F23
GPP_D18/DMIC_DATA1
AW5
<30> SPKR GPP_B14/SPKR
+3.3V_ALW_PCH +3.3V_ALW_PCH
1 2 SPKR 1 2 HDA_SDOUT
@ RC183 8.2K_0402_5% @ RC187 4.7K_0402_5%
A TOP SWAP STRAP Flash Descriptor Security override A
HIGH ENABLE HIGH DISABLE

LOW(DEFAULT) DISABLE LOW(DEFAULT) ENABLE
5 4 3 2 1
5 4 3 2 1
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D D
CFG[2][5][6][7] for SKYLAKE-H CPU CFG strap pin

UC1S SKL-U
UC1T SKL-U
RESERVED SIGNALS-1
<14> CFG[0..19] 1/5 2014WW52 MOW reserve to support SPARE
CFG0 CFG0 E68 BB68 Cannonlake-U PCH compatibility
CFG1 1 2 CFG1 B67 CFG[0] RSVD_TP_BB68 BB69 PAD~D @ T12 AW69 F6
CFG[1] RSVD_TP_BB69 PAD~D @ T13 close UC1.U11/U12 and <400mil RSVD_AW69 RSVD_F6
CFG2 @ RC112 10K_0402_1% CFG2 D65 AW68 E3
CFG3 1 2 CFG3 D67 CFG[2] AK13 AU56 RSVD_AW68 RSVD_E3 C11
CFG4 CFG4 E70 CFG[3] RSVD_TP_AK13 AK12 PAD~D @ T14 +1.8V_PRIM +VCC_1P8 AW48 RSVD_AU56 RSVD_C11 B11
@ RC110 10K_0402_1%
C68 CFG[4] RSVD_TP_AK12 PAD~D @ T15 C7 RSVD_AW48 RSVD_B11 A11
CFG5 CFG5
CFG6 CFG6 D68 CFG[5] BB2 1 2 U12 RSVD_C7 RSVD_A11 D12
CFG7 CFG7 C67 CFG[6] RSVD_BB2 BA3 @ RC313 0_0402_5% U11 RSVD_U12 RSVD_D12 C12
CFG[7] RSVD_BA3 RSVD_U11 RSVD_C12
1U_0402_6.3V6K
CFG8 CFG8 F71 1 H11 F52
CFG9 CFG9 G69 CFG[8] RSVD_H11 RSVD_F52
CFG[9]
CC222
CFG10 CFG10 F70 AU5
CFG11 CFG11 G68 CFG[10] TP5 AT5 PAD~D @ T128
CFG12 CFG12 H70 CFG[11] TP6 PAD~D @ T129 2 20 OF 20
SKL-U_BGA1356
CFG13 CFG13 G71 CFG[12] @
CFG14 CFG14 H69 CFG[13] D5
CFG15 CFG15 G70 CFG[14] RSVD_D5 D4
CFG16 CFG[15] RSVD_D4 B2
CFG17 CFG16 E63 RSVD_B2 C2
CFG18 CFG17 F63 CFG[16] RSVD_C2
CFG19 CFG[17] B3
CFG18 E66 RSVD_B3 A3
CFG19 F66 CFG[18] RSVD_A3
C CFG[19] AW1 C
2 1 CFG_RCOMP E60 RSVD_AW1
RC114 49.9_0402_1% CFG_RCOMP E1
2 1 ITP_PMODE E8 RSVD_E1 E2
+1.0V_PRIM_XDP ITP_PMODE RSVD_E2
RC115 1.5K_0402_5%
AY2 BA4
1 2 CFG0 AY1 RSVD_AY2 RSVD_BA4 BB4
<14> ITP_PMODE RSVD_AY1 RSVD_BB4
@ RC113 10K_0402_1%
D1 A4
D3 RSVD_D1 RSVD_A4 C4
RSVD_D3 RSVD_C4
K46 BB5
K45 RSVD_K46 TP4 PAD~D @ T130
RSVD_K45 A69
Stall reset sequence AL25 RSVD_A69 B69
AL27 RSVD_AL25 RSVD_B69
HIGH(DEFAULT) No stall(Normal Operation) RSVD_AL27 AY3
LOW stall C71 RSVD_AY3
B70 RSVD_C71 D71
RSVD_B70 RSVD_D71 C70
F60 RSVD_C70
RSVD_F60 C54
A52 RSVD_C54 D54
RSVD_A52 RSVD_D54
BA70 AY4
T16 @ PAD~D RSVD_TP_BA70 TP1 PAD~D @ T126
BA68 BB3
T17 @ PAD~D RSVD_TP_BA68 TP2 PAD~D @ T127
J71 AY71
J68 RSVD_J71 VSS_AY71 AR56
1 2 CFG4 RSVD_J68 ZVM#
RC109 1K_0402_5% F65 AW71
ZVM# for SKYLAKE-U 2+3e
G65 VSS_F65 RSVD_TP_AW71 AW70 PAD~D @ T113
B VSS_G65 RSVD_TP_AW70 PAD~D @ T114 B
F61 AP56
E61 RSVD_F61 MSM# C64 1 2
MSM# for SKYLAKE-U 2+3e
RSVD_E61 PROC_SELECT# @ +1.0V_VCCST
RC120 100K_0402_5%
eDP enable For Skylake RC120 depop
SKL-U_BGA1356 19 OF 20 For Cannonlake RC120 pop
HIGH(DEFAULT) Disabled 546765_546765_2014WW48_Skylake_MOW_Rev_1_0
LOW Enabled
A A
5 4 3 2 1
5 4 3 2 1
+1.0V_PRIM +1.0V_PRIM_XDP
1 2 +1.0V_PRIM_XDP CXDP@
@ RC216 0_0603_1% CPU XDP XDP_PRSNT_PIN1 1
RC121
2 CFG3
1K_0402_5% +1.0V_PRIM_XDP
<13> CFG[0..19]
1 2 +3.3V_RUN
@ RC122 0_0402_5%
+1.0V_PRIM_XDP JXDP1 CC30
1 2 1 2
<10> CPU_XDP_PREQ#
CPU_XDP_PREQ# 3 GND0 GND1 4 CFG17 UC8
CPU_XDP_PRDY# 5 OBSFN_A0 OBSFN_C0
0.1U_0201_10V6K
0.1U_0201_10V6K
6 CFG16 0.1U_0201_10V6K
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<10> CPU_XDP_PRDY# OBSFN_A1 OBSFN_C1
@ CC28
@ CC29
1 1 7 8 14
CFG0 9 GND2 GND3 10 CFG8 VCC
CFG1 11 OBSDATA_A0 OBSDATA_C0 12 CFG9 TDO_XDP 2 3 CPU_XDP_TDO <12>
13 OBSDATA_A1 OBSDATA_C1 14 1A 1B
D 2 2 CFG2 15 GND4 GND5 16 CFG10 D
CFG3 17 OBSDATA_A2 OBSDATA_C2 18 CFG11 1
19 OBSDATA_A3 OBSDATA_C3 20 1OE
CXDP@ RC239 1 2 0_0402_5% XDP_OBS0 21 GND6 GND7 22 CFG19 TDI_XDP 5 6 CPU_XDP_TDI <12>
<12> XDP_OBS0_R XDP_OBS1 23 OBSFN_B0 OBSFN_D0 2A 2B
CXDP@ RC240 1 2 0_0402_5% 24 CFG18
<12> XDP_OBS1_R 25 OBSFN_B1 OBSFN_D1 26
Place near CFG4 27 GND8 GND9 28 CFG12 4
JXDP1 CFG5 29 OBSDATA_B0 OBSDATA_D0 30 CFG13 2OE
RC5 need to close to JCPU1 31 OBSDATA_B1 OBSDATA_D1 32 XDP_TMS 9 8 CPU_XDP_TMS <12>
CFG6 33 GND10 GND11 34 CFG14 3A 3B
@ RC123 1 2 1K_0402_5% CFG7 35 OBSDATA_B2 OBSDATA_D2 36 CFG15
<11,32> VCCST_PWRGD 37 OBSDATA_B3 OBSDATA_D3 38 10
<11,39> PCH_RSMRST#_Q RC1241 2 H_VCCST_PWRGD_XDP 39 GND12 GND13 40 3OE
41 PWRGOOD/HOOK0 ITPCLK/HOOK4 42 CLK_ITPXDP_P_R <11> TRST#_XDP 12 11
CXDP@ 1K_0402_5% CPU_XDP_TRST# <12>
FIVR_EN <11,32> SIO_PWRBTN# HOOK1 ITPCLK#/HOOK5 CLK_ITPXDP_N_R <11> 4A 4B
@ RC2171 2 0_0402_5% 43 44
CFG0 @ RC1261 2 1K_0402_5% FIVR_EN_R 45 VCC_OBS_AB VCC_OBS_CD 46 ITP_PMODE
RESET_OUT#_R 47 HOOK2 RESET#/HOOK6 XDP_DBRESET# ITP_PMODE <13>
CXDP@ RC1281 2 0_0402_5% 48 XDP_DBRESET# <11> 13 7
<8> PCH_SPI_DO_XDP 49 HOOK3 DBR#/HOOK7 <31,32> RUNPWROK 4OE GND
@ RC1291 2 0_0402_5% 50
<11,32> RESET_OUT# 51 GND14 GND15 52 TDO_XDP 15
<8,20,21,42> DDR_XDP_WAN_SMBDAT 53 SDA TD0 54 TRST#_XDP GND PAD
<8,20,21,42> DDR_XDP_WAN_SMBCLK 55 SCL TRST# 56 TDI_XDP
<12> PCH_JTAG_TCK CPU_XDP_TCLK 57 TCK1 TDI 58 XDP_TMS
<12> CPU_XDP_TCLK TCK0 TMS 74CBTLV3126BQ_DHVQFN14_2P5X3
59 60
GND16 GND17 PCH_SPI_DO2_XDP <8>
SAMTE_BSH-030-01-L-D-A CONN@
+3.3V_ALW_PCH +1.0V_VCCSTG
+1.0VS_VCCIO 9/1 follow SPI PWR rail
CPU_XDP_TMS 2 1 RC131
1
FIVR_EN_R
1.5K_0402_5%
CXDP@ RC133
1 2 51_0402_5%
C RC132 150_0402_5% +3.3V_ALW_DSW EDS0.7 CPU_XDP_TDI 2 1 RC134 C
+1.0V_VCCST 51_0402_5%
Place near JXDP1.48 CPU_XDP_TDO 2 1 RC135
1
FIVR_EN XDP_DBRESET#
0.1U_0402_25V6
1.5K_0402_5%
1 2 2 100_0402_1%
RC241
@
@ RC218 150_0402_5%
1
FIVR_EN PCH_SPI_DO_XDP CPU_XDP_TRST# 2
CC32
CXDP@
1 2 1 RC136 CXDP@
@ RC219 10K_0402_5% 51_0402_5%
2
RESET_OUT#_R CPU_XDP_TCLK 2 1 RC139
2
SIO_PWRBTN#
0.1U_0402_25V6
51_0402_5%
1
@ CC33
0.1U_0402_25V6
1
CC269
@
2
+3.3V_RUN Place near JXDP1.41 XDP_TMS 1 2

PCH_JTAG_TMS <12>
2
@ RC228 0_0402_5%
RC137 1 2 XDP_DBRESET# TDI_XDP 1 2
@ RC229 PCH_JTAG_TDI <12>
1K_0402_5% Place near JXDP1.47 0_0402_5%
+1.0V_PRIM_XDP TDO_XDP 1 2
@ RC230 PCH_JTAG_TDO <12>
0_0402_5%
@ RC138 1 2 CPU_XDP_PREQ#
51_0402_5% CKLT0.9
B B
A A
5 4 3 2 1
5 4 3 2 1
+VCC_CORE: 0.3~1.35V +VCC_CORE +VCC_CORE

PSC(Primary side cap) : Place as close to the package as possible
UC1L SKL-U BSC(Backside cap) : Place on secondary side, underneath the package
CPU POWER 1 OF 4
A30 G32
A34 VCC_A30 VCC_G32 G33
Component placement order:
A39 VCC_A34 VCC_G33 G35 Package edge > 0402 caps > 0805 caps > Bulk caps >Power source
A44 VCC_A39 VCC_G35 G37
AK33
AK35
AK37
VCC_A44
VCC_AK33
VCC_AK35
Vinafix.com VCC_G37
VCC_G38
VCC_G40
G38
G40
G42
AK38 VCC_AK37 VCC_G42 J30
D AK40 VCC_AK38 VCC_J30 J33 D
AL33 VCC_AK40 VCC_J33 J37
AL37 VCC_AL33 VCC_J37 J40
AL40 VCC_AL37 VCC_J40 K33 +VCC_CORE
AM32 VCC_AL40 VCC_K33 K35
AM33 VCC_AM32 VCC_K35 K37
VCC_AM33 VCC_K37
100_0402_1%
AM35 K38
AM37 VCC_AM35 VCC_K38 K40
VCC_AM37 VCC_K40
RC140
AM38 K42
G30 VCC_AM38 VCC_K42 K43
VCC_G30 VCC_K43
2
+VCC_CORE_G0 K32 E32 VCCSENSE
T122@ PAD~D RSVD_K32 VCC_SENSE VCCSENSE <49>
E33 VSSSENSE
+VCC_CORE_G1 AK32 VSS_SENSE VSSSENSE <49>
T123@ PAD~D RSVD_AK32
100_0402_1%
B63 H_CPU_SVIDALRT#
AB62 VIDALERT# A63 VIDSCLK
ESD Request
VCCOPC_AB62 VIDSCK VIDSCLK <49>
RC141
P62 D64 VIDSOUT
V62 VCCOPC_P62 VIDSOUT
VCCOPC_V62 G20
2
H63 VCCSTG_G20
VCC_OPC_1P8_H63 +VCC_CORE +1.2V_MEM
G61
VCC_OPC_1P8_G61 1 2
AC63 @EMC@ CC282 22U_0603_6.3V6M
AE63 VCCOPC_SENSE
VSSOPC_SENSE +1.0V_VCCSTG_R 1 2
+1.0V_VCCSTG +1.0V_PRIM +VCC_CORE
AE62 @ RC143 0_0603_5%
AG62 VCCEOPIO
VCCEOPIO 1 2
AL63 @EMC@ CC283 22U_0603_6.3V6M
AJ62 VCCEOPIO_SENSE
VSSEOPIO_SENSE 1 2
C @EMC@ CC284 22U_0603_6.3V6M C
VCCOPC,VCCOPC_1P8,VCCEOPIO for SKYLAKE-U 2+3e +1.0V_PRIM +3.3V_RUN

(w/ on package cache)
1 2
@EMC@ CC285 22U_0603_6.3V6M
+1.0V_PRIM +1.2V_MEM
1 2
@EMC@ CC286 22U_0603_6.3V6M
+VCC_CORE +3.3V_RUN
1 2
@EMC@ CC287 22U_0603_6.3V6M
B B
8/21 CRB1.0 , DG0.9

+1.0V_VCCST
SVID ALERT
1
56_0402_1%
RC152
CAD Note: Place the PU resistors close to CPU

RC204 close to CPU 300 - 1500mils
2
2 1 H_CPU_SVIDALRT#
<49> VIDALERT_N
220_0402_5% RC153
+1.0V_VCCST
SVID DATA
100_0402_1%
1
CAD Note: Place the PU resistors close to CPU

RC157
RC208close to CPU 300 - 1500mils

A A
2
VIDSOUT
<49> VIDSOUT
5 4 3 2 1
5 4 3 2 1
+VCCGT: 0.3~1.35V
+VCCGTX : 0.3~1.35V
+VCC_GT
UC1M SKL-U
Vinafix.com +VCC_GT
D CPU POWER 2 OF 4 D
N70
A48 VCCGT N71
A53 VCCGT VCCGT R63
A58 VCCGT VCCGT R64
A62 VCCGT VCCGT R65
A66 VCCGT VCCGT R66
AA63 VCCGT VCCGT R67
AA70 VCCGT VCCGT T62
AA71 VCCGT VCCGT U65
AC64 VCCGT VCCGT U68
AC65 VCCGT VCCGT U71
AC66 VCCGT VCCGT W63
J43 VCCGT VCCGT W69
J45 VCCGT VCCGT W70
J46 VCCGT VCCGT W71
J48 VCCGT VCCGT Y62
J50 VCCGT VCCGT +VCC_GTUS Reserve for soldering
J52 VCCGT
J53 VCCGT AK42
J55 VCCGT VCCGTX_AK42 AK43
C J60 VCCGT VCCGTX_AK46 AK48 C
K48 VCCGT VCCGTX_AK48 AK50
L62 VCCGT VCCGTX_AK70 AL43
L63 VCCGT VCCGTX_AL43 AL46
VCCGTX for SKYLAKE-U 2+3e
L68 VCCGT VCCGTX_AL60 AM48
+VCC_GT L69 VCCGT VCCGTX_AM48 AM50
L70 VCCGT VCCGTX_AM50 AM52
L71 VCCGT VCCGTX_AM52 AM53
M62 VCCGT VCCGTX_AM53 AM56
VCCGT VCCGTX_AM56
1
100_0402_1%
N63 AM58
N64 VCCGT VCCGTX_AM58 AU58
VCCGT VCCGTX_AU58
RC161
N66 AU63
N67 VCCGT VCCGTX_AU63 BB57
N69 VCCGT VCCGTX_BB57 BB66
2
VCCGT VCCGTX_BB66
VCC_GT_SENSE J70 AK62
<49> VCC_GT_SENSE VSS_GT_SENSE J69 VCCGT_SENSE VCCGTX_SENSE AL61
<49> VSS_GT_SENSE VSSGT_SENSE VSSGTX_SENSE
1
100_0402_1%
B B
RC163
2
A A
5 4 3 2 1
5 4 3 2 1
+1.2V_MEM_CPUCLK +1.2V_MEM +1.0V_VCCST source

@ RC231
1 2
0_0402_5%
VDDQ: 8.45A
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1.35V in DDR3L,
+1.2V_MEM
1.2V in LPDDR3 and DDR4 2 1
+1.0V_PRIM
1
UZ21 2
PJP27
1
+1.0V_VCCST
DG0.9 CZ95 1U_0402_6.3V6K 2 VIN1
D BSC PSC VIN2 PAD-OPEN1x1m D
+5V_ALW 7 6 +1.0V_VCCST_C 1 2
VIN thermal VOUT @ CZ78 0.1U_0201_10V6K
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
3
VBIAS
1 1 1 1 1 1
@ CC174
@ CC175
CC176
CC177
CC178
CC179
4 5
<11,17,32,45,54> SIO_SLP_S4# ON GND
+1.0VS_VCCIO
2 2 2 2 2 2 UC1N SKL-U TPS22961DNYR_WSON8
CPU POWER 3 OF 4
AU23 AK28
BSC AU28 VDDQ_AU23 VCCIO AK30
AU35 VDDQ_AU28 VCCIO AL30
AU42 VDDQ_AU35 VCCIO AL42
BB23 VDDQ_AU42 VCCIO AM28
VDDQ_BB23 VCCIO +1.0VS_VCCIO
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1 1 1 BB32 AM30 INTEL PDG 1.0

BB41 VDDQ_BB32 VCCIO AM42 +VCC_SA
+1.2V_MEM_CPUCLK VDDQ_BB41 VCCIO
@ CC256
@ CC257
@ CC254
@ CC255
CC294
CC295
CC296
BB47
BB51 VDDQ_BB47 AK23
BSC BSC
2 2 2 2 2 2 2 VDDQ_BB51 VCCSA AK25
BSC VCCSA G23
VCCSA
10U_0402_6.3V6M
10U_0402_6.3V6M
AM40 G25
VDDQC VCCSA
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
G27 1 1 1 1 1 1
VCCSA +1.0VS_VCCIO
10U_0402_6.3V6M
1U_0402_6.3V6K
CC248
CC249
A18 G28
VCCST VCCSA
CC181
CC182
CC185
CC186
1 1 J22
VCCSA
CC297
@ CC194
A22 J23
VCCSTG_A22 VCCSA J27 2 2 2 2 2@ 2@
VCCSA
100_0402_1%
AL23 K23 @ @ @ @
2 2 VCCPLL_OC VCCSA
RC165
K25 8/14 PWR request
+1.0V_VCCST K20 VCCSA K27
K21 VCCPLL_K20 VCCSA K28
C PSC VCCPLL_K21 VCCSA K30 C
2
VCCSA
AM23 VCCIO_SENSE PSC
VCCIO_SENSE AM22 VSSIO_SENSE VCCIO_SENSE <47>
+1.0V_VCCSTG VSSIO_SENSE VSSIO_SENSE <47>
1U_0402_6.3V6K
1
H21
BSC VSSSA_SENSE
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
CC195
H20 1 1 1 1
VCCSA_SENSE
1
100_0402_1%
100_0402_1%
2
CC252
CC253
CC250
CC251
RC166
RC167
+VCC_SFR_OC 2 2 2 2
1U_0402_6.3V6K
1 1 2
+VCC_SA
@ CC199
RC168 100_0402_1%
2
+1.0V_VCCST
2 PSC
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1 DG0.9
VSA_SEN- <49>
CC288
S0 S0Ix S3
VSA_SEN+ <49>
CC202
2
2 SIO_SLP_S0# HIGH LOW LOW
SIO_SLP_S3# HIGH HIGH LOW
AND HIGH LOW LOW
B B
+VCCPLL_OC source +1.2V_MEM +VCC_SFR_OC

+1.0V_VCCSTG source
1 2 +1.0V_VCCSTG +1.0V_VCCST
@ RZ119 0_0603_5%
1 2
@ RC238 0_0603_5%
UZ26 pop option with UZ19
1
1 +1.0V_PRIM
2 1 2 VIN1 PJP32
CZ113 1U_0402_6.3V6K VIN2 UZ19 PAD-OPEN1x1m
+5V_ALW 7 6 1 2 1
VIN thermal VOUT @ CZ114 0.1U_0201_10V6K 2 1 2 VIN1
3 CZ87 1U_0402_6.3V6K VIN2
2
VBIAS +5V_ALW 7 6 +1.0V_VCCSTG_C1 2
1 2 4 5 VIN thermal VOUT @ CZ82 0.1U_0201_10V6K
<11,17,32,48> SIO_SLP_S3# @ ON GND 3
RZ120 0_0402_5%
VBIAS
+3.3V_ALW TPS22961DNYR_WSON8 +3.3V_ALW 4 5
ON GND
1 2
@ CZ115 0.1U_0201_10V6K TPS22961DNYR_WSON8
5
4.4mohm/6A
5
1
P
<8,11,18,32,41,46,47,48> SIO_SLP_SUS# B 4 1 TR=12.5us@Vin=1.05V
P
2 O <11,33,47> SIO_SLP_S0# B 4
<11,17,32,45,54> SIO_SLP_S4# A O
G
UC14 2
<11,17,32,48> SIO_SLP_S3# A
G
TC7SH08FU_SSOP5~D UC13
3
TC7SH08FU_SSOP5~D
3
A A
@ RC3201 2 0_0402_5%
5 4 3 2 1
5 4 3 2 1
close UC1.AL1 and <120mil +1.0V_MPHYGT

+1.0V_PRIM
+1.0V_MPHYAON +1.0V_PRIM
+1.0VO_DSW +1.0V_PRIM_CORE
close UC1.K17 and <120mil close UC1.AB19 and <400mil
PCH PWR close UC1.Y16 and <400mil +1.0V_SRAM
+1.0V_PRIM_CORE
+3.3V_ALW_PCH 1 2
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 2 @ RC309 0_0603_5%
1 1 1 close UC1.AG15 and <120mil
+3.3V_ALW_PCH +3.3V_PGPPE
@ CC206
@ RC194 0_0805_5%
Vinafix.com +1.0V_APLLEBB
CC203
CC204
+1.0V_MPHYAON UC1O SKL-U close UC1.T16 and <400mil
Imax : 2.57A 2 2 2
1U_0402_6.3V6K
1 1 2
CPU POWER 4 OF 4
@ CC208
1 2 @ RC310 0_0603_5%
D @ RC299 0_0603_5% AB19 D
AB20 VCCPRIM_1P0 AK15
VCCPRIM_1P0 VCCPGPPA +3.3V_1.8V_PGPPA 2
+1.0V_CLK6 P18 AG15
VCCPRIM_1P0 VCCPGPPB Y16
1 2 AF18 VCCPGPPC Y15
@ VCCPRIM_CORE VCCPGPPD +3.3V_PGPPD
RC300 0_0402_5% AF19 T16
V20 VCCPRIM_CORE VCCPGPPE AF16
VCCPRIM_CORE VCCPGPPF +1.8V_PRIM +3.3V_ALW_PCH
+1.0V_DTS V21 AD15
VCCPRIM_CORE VCCPGPPG +3.3V_1.8V_PGPPG
1 2 AL1 V19
@ RC301 0_0402_5% DCPDSW_1P0 VCCPRIM_3P3_V19
close UC1.V19 and <120mil
+1.8V_PRIM
1U_0402_6.3V6K
K17 T1 1
VCCMPHYAON_1P0 VCCPRIM_1P0_T1 +1.0V_DTS
@ CC209
+1.0V_CLK1 L1
VCCMPHYAON_1P0 AA1
VCCATS_1P8 close UC1.AA1 and <400mil
1 2 +1.0V_MPHYGT N15
VCCMPHYGT_1P0_N15 +RTC_CELL 2
1U_0402_6.3V6K
@ RC302 0_0402_5% N16 AK17
VCCMPHYGT_1P0_N16 VCCRTCPRIM_3P3 +3.3V_ALW_PCH 1
close UC1.N15 and CC210 <400mil, CC211 <120mil N17
VCCMPHYGT_1P0_N17
CC212
+1.0V_CLK3 P15 AK19
VCCMPHYGT_1P0_P15 VCCRTC_AK19
47U_0805_6.3V6M
1U_0402_6.3V6K
1 1 P16 BB14 close UC1.AK19 and <120mil
VCCMPHYGT_1P0_P16 VCCRTC_BB14 2
0.1U_0201_10V6K
1U_0402_6.3V6K
@ CC210
1 2 1 1
CC211
@ RC303 0_0402_5% K15 BB10 +DCPRTC
+1.0V_AMPHYPLL VCCAMPHYPLL_1P0 DCPRTC
CC270
CC213
L15 close UC1.BB10 and <120mil
2 2 VCCAMPHYPLL_1P0
0.1U_0201_10V6K
A14 1
VCCCLK1 +1.0V_CLK1 2 2
V15
+1.0V_VCCAPLL VCCAPLL_1P0
CC214
K19
+1.8V_PRIM VCCCLK2 +1.0V_CLK2
AB17
+1.0V_PRIM VCCPRIM_1P0_AB17 2
Y18 L21
VCCPRIM_1P0_Y18 VCCCLK3 +1.0V_CLK3
AD17 N20 DG0.9
+3.3V_ALW_DSW VCCDSW_3P3_AD17 VCCCLK4 +1.0V_CLK4
AD18
+3.3V_1.8V_PGPPG AJ17 VCCDSW_3P3_AD18 L19 +1.0V_CLK6
VCCDSW_3P3_AJ17 VCCCLK5 +1.0V_CLK5
C 1 2 AJ19 A10 C
@ +3.3V_VCCHDA VCCHDA VCCCLK6
RC234 0_0402_5% 10/30: layout limit, change from 0603 to 0402 close UC1.A10 and <120mil
+1.0V_SRAM
1U_0402_6.3V6K
AJ16 AN11 CORE_VID0 <47> 1
+3.3V_ALW_PCH +3.3V_SPI VCCSPI GPP_B0/CORE_VID0
@ CC216
AN13 CORE_VID1 <47>
AF20 GPP_B1/CORE_VID1
close UC1.AF20 and <400mil VCCSRAM_1P0
1 2 AF21
+3.3V_ALW_PCH VCCSRAM_1P0 2
1U_0402_6.3V6K
@ RC235 0_0402_5% T19

1 VCCSRAM_1P0 Take care!!! Note1 on Page 19
@ CC217
T20
+3.3V_1.8V_PGPPA +1.0V_PRIM VCCSRAM_1P0
AJ21
1 2 2 +1.0V_APLLEBB VCCPRIM_3P3_AJ21
@ RC211 0_0402_5% AK20
VCCPRIM_1P0_AK20
+1.8V_PRIM N18
VCCAPLLEBB
1U_0402_6.3V6K
1 2 1 close UC1.N18 and <120mil

@ RC212 0_0402_5% SKL-U_BGA1356 15 OF 20
CC218
+3.3V_ALW_PCH
2
+3.3V_PGPPD
1 2
@ RC307 0_0402_5%
+3.3V_PGPPE
+1.0V_MPHYGT +1.0V_AMPHYPLL +1.0V_PRIM +1.0V_CLK2 +1.0V_PRIM +1.0V_CLK5 +3.3V_ALW_PCH
1 2 close UC1.K15, UC1.L15 and <100mil close UC1.AK17 and <120mil
@ RC308 0_0402_5%
1 2 1 2 1 2
@ RC169 0_0603_5% @ RC170 0_0402_5% @ RC171 0_0402_5%
close UC1.K15 and <120mil
47U_0805_6.3V6M
47U_0805_6.3V6M
47U_0805_6.3V6M
0.1U_0201_10V6K
1U_0402_6.3V6K
0.1U_0201_10V6K
1U_0402_6.3V6K
1 1 1 1 1 DG0.9 1 1
B +3.3V_ALW_PCH +3.3V_VCCHDA B
@ CC219
@ CC220
@ CC221
CC223
close UC1.L19 and <100mil
@ CC281
@ CC264
CC224
LC1
2 2 2
close UC1.K19 and <100mil 2 2 2 2
1 2
0.1U_0402_25V6
BLM15HG601SN1D
1U_0402_6.3V6K
1 1 Pop PJP35 & Depop UZ20/RZ83/CZ84

@ CC215
CC310
8/26 vender suggest depop

+1.0V_PRIM +1.0V_MPHYGT
2 2 PJP35
+1.0V_PRIM +1.0V_VCCAPLL +1.0V_MPHYGT source 1
PAD-OPEN1x3m
2
LC2 +1.0V_PRIM +1.0V_CLK4 +1.0V_PRIM

1 2 11/0 change power source
0.1U_0402_25V6
BLM15HG601SN1D UZ20 @
47U_0805_6.3V6M
1 1 1 2 2 1 1
VIN1 +1.0V_MPHYGT
@ CC225
CC311
@ RC173 0_0402_5% @ CZ84 1U_0402_6.3V6K 2

+3.3V_ALW +3.3V_ALW_DSW VIN2
47U_0805_6.3V6M
close UC1.N20 and <100mil 1 @ CC226
+5V_ALW 7 6
2 2 VIN thermal VOUT
0.1U_0201_10V6K
1 2 1
@ RC214 0_0402_5% 3
2 VBIAS
CZ85
22U_0603_6.3V6M
@ CC279
22U_0603_6.3V6M
@ CC280
1 1 4 5
ON GND 2
@
TPS22961DNYR_WSON8
2 2
+3.3V_ALW +1.8V_PRIM +1.0V_PRIM +1.0V_PRIM_CORE 4.4mohm/6A
TR=12.5us@Vin=1.05V
2 1
<8,11,17,32,41,46,47,48> SIO_SLP_SUS#
47U_0805_6.3V6M
47U_0805_6.3V6M
47U_0805_6.3V6M
47U_0805_6.3V6M
1 1 1 1 8/26 vender suggestion @ RZ82 0_0402_5%

A A
CC271
CC272
CC273
CC274
8/26 vender suggest depop 2 1

<11> MPHYP_PWR_EN
@ RZ83 0_0402_5%
2 2 2 2
5 4 3 2 1
5 4 3 2 1
Note1: VCCPRIM_CORE Implementation with PCH CORE_VID Recommendation
UC1P SKL-U UC1Q SKL-U R1: PR408,PR411 ; R2: PR417,PR418 ; R3,PR419,PR420 ; R4: PR423 ; R5: PR424
UC1R SKL-U
GND 1 OF 3 GND 2 OF 3
GND 3 OF 3
A5 AL65 AT63 BA49 F8 L18
A67
A70
AA2
VSS
VSS
VSS
VSS
VSS
VSS
AL66
AM13
AM21
AT68
AT71
AU10
Vinafix.com
VSS
VSS
VSS
VSS
VSS
VSS
BA53
BA57
BA6
G10
G22
G43
VSS
VSS
VSS
VSS
VSS
VSS
L2
L20
L4
AA4 VSS VSS AM25 AU15 VSS VSS BA62 G45 VSS VSS L8
D AA65 VSS VSS AM27 AU20 VSS VSS BA66 G48 VSS VSS N10 D
AA68 VSS VSS AM43 AU32 VSS VSS BA71 G5 VSS VSS N13
AB15 VSS VSS AM45 AU38 VSS VSS BB18 G52 VSS VSS N19
AB16 VSS VSS AM46 AV1 VSS VSS BB26 G55 VSS VSS N21
AD13 VSS VSS AM68 AV71 VSS VSS BB43 G63 VSS VSS P17
AD16 VSS VSS AM71 AW10 VSS VSS BB55 G66 VSS VSS P19
AD19 VSS VSS AM8 AW12 VSS VSS BB6 H15 VSS VSS P20
AD20 VSS VSS AN20 AW14 VSS VSS BB60 H18 VSS VSS P21
AD21 VSS VSS AN23 AW16 VSS VSS BB64 H71 VSS VSS R13
AD62 VSS VSS AN28 AW18 VSS VSS BB67 J11 VSS VSS R6
AD8 VSS VSS AN30 AW21 VSS VSS BB70 J13 VSS VSS T15
AE64 VSS VSS AN32 AW23 VSS VSS C1 J25 VSS VSS T17
AE67 VSS VSS AN37 AW30 VSS VSS D10 J35 VSS VSS T21
AE68 VSS VSS AN38 AW32 VSS VSS D11 J38 VSS VSS T4
AE69 VSS VSS AN40 AW34 VSS VSS D14 J42 VSS VSS U10
AF1 VSS VSS AN42 AW36 VSS VSS D18 J8 VSS VSS U63
AF10 VSS VSS AN58 AW38 VSS VSS D22 K16 VSS VSS U64
AF15 VSS VSS AN63 AW41 VSS VSS D25 K18 VSS VSS U66
AF17 VSS VSS AP10 AW43 VSS VSS D26 K22 VSS VSS U67
AF63 VSS VSS AP23 AW49 VSS VSS D39 K64 VSS VSS V16
AG16 VSS VSS AP28 AW51 VSS VSS D44 K65 VSS VSS V17
AG17 VSS VSS AP32 AW53 VSS VSS D45 K66 VSS VSS V18
AG18 VSS VSS AP35 AW55 VSS VSS D47 K67 VSS VSS W13
C AG21 VSS VSS AP58 AW60 VSS VSS D58 K71 VSS VSS Y17 C
AG71 VSS VSS AP63 AW62 VSS VSS D6 L11 VSS VSS Y19
AH13 VSS VSS AP68 AW64 VSS VSS D62 L16 VSS VSS Y20
AH6 VSS VSS AP70 AW66 VSS VSS D66 L17 VSS VSS Y21
AH63 VSS VSS AR11 AW8 VSS VSS D69 VSS VSS
AH64 VSS VSS AR15 AY66 VSS VSS E11
AH67 VSS VSS AR16 B10 VSS VSS E15
AJ15 VSS VSS AR20 B14 VSS VSS E18
AJ18 VSS VSS AR23 B18 VSS VSS E21 SKL-U_BGA1356 18 OF 20
AK11 VSS VSS AR42 B34 VSS VSS E53
AK27 VSS VSS AR5 B58 VSS VSS F1
AK8 VSS VSS AR55 BA1 VSS VSS F23
AL2 VSS VSS AR58 BA10 VSS VSS F27
AL35 VSS VSS AT2 BA2 VSS VSS F33
AL52 VSS VSS AT4 F68 VSS VSS F40
AL58 VSS VSS AT56 VSS VSS BA41
B AL64 VSS VSS AT58 VSS B
VSS VSS
SKL-U_BGA1356 16 OF 20 SKL-U_BGA1356 17 OF 20
A A
5 4 3 2 1
5 4 3 2 1
JDIMM1 REV Type H=4

<7> DDR_A_DQS#[0..7] +1.2V_MEM +1.2V_MEM
JDIMM1
<7> DDR_A_D[0..63]
1 2
<7> DDR_A_DQS[0..7] DDR_A_D1 3 VSS1 VSS2 4 DDR_A_D4
5 DQ5 DQ4 6
<7> DDR_A_MA[0..16] DDR_A_D0 7 VSS3 VSS4 8 DDR_A_D5
Vinafix.com 9 DQ1 DQ0 10

DDR_A_DQS#0 11 VSS5 VSS6 12
DDR_A_DQS0 13 DQS0_c DM0_n/DBI0_n 14
Layout Note: 15 DQS0_t VSS7 16 DDR_A_D3
VSS8 DQ6
D Place near JDIMM1 DDR_A_D6 17
19 DQ7 VSS9
18
20 DDR_A_D7 +1.2V_MEM D
DDR_A_D2 21 VSS10 DQ2 22
23 DQ3 VSS11 24 DDR_A_D9
DDR_A_D13 25 VSS12 DQ12 26
DQ13 VSS13
1
DDR_A_D8
470_0402_1%
27 28
DDR_A_D12 29 VSS14 DQ8 30
+1.2V_MEM DQ9 VSS15 DDR_A_DQS#1 DG0.9 470ohm+/-1%
RD2
31 32
33 VSS16 DQS1_c 34 DDR_A_DQS1
35 DM1_n/DBI_n DQS1_t 36
2
DDR_A_D15 37 VSS17 VSS18 38 DDR_A_D10
DQ15 DQ14
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
39 40
DDR_A_D14 41 VSS19 VSS20 42 DDR_A_D11 1 2 DDR_DRAMRST#
DQ10 DQ11 <21> DDR_DRAMRST#_R DDR_DRAMRST# <7>
1
1
43 44 @ RD29 0_0402_5%
DDR_A_D35 VSS21 VSS22 DDR_A_D32
CD7
CD2
CD3
CD8
CD9
CD4
CD10
CD11
CD78
CD79
CD80
CD81
CD82
CD83
CD84
CD85
45 46
47 DQ21 DQ20 48
2
2
51 DQ17 DQ16 52
57 DQS2_t VSS27 58 DDR_A_D39
DDR_A_D38 59 VSS28 DQ22 60
61 DQ23 VSS29 62 DDR_A_D33
DDR_A_D34 63 VSS30 DQ18 64 +1.2V_MEM
65 DQ19 VSS31 66 DDR_A_D40
+1.2V_MEM DDR_A_D44 67 VSS32 DQ28 68
DQ29 VSS33
1K_0402_1%
1
69 70 DDR_A_D41
DDR_A_D45 71 VSS34 DQ24 72
DQ25 VSS35 DDR_A_DQS#5
RD18
73 74
VSS36 DQS3_c DDR_A_DQS5
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
330U_D3_2.5VY_R6M
75 76
77 DM3_n/DBI3_n DQS3_t 78 +DDR_VREF_A_CA +DDR_VREF_CA
2
DQ30 DQ31
1
81 82
@ CD20
VSS39 VSS40
1
1
CD12
CD13
CD14
CD15
CD16
CD17
CD18
CD19
CD86
CD87
CD88
CD89
CD90
CD91
CD92
CD93
+ DDR_A_D46 83 84 DDR_A_D43 1 2
85 DQ26 DQ27 86 RD19 2_0402_1%
VSS41 VSS42
0.022U_0402_16V7K
87 88
2
2
CB5/NC CB4/NC
1K_0402_1%
89 90
VSS43 VSS44
1
91 92
CB1/NC CB0/NC
1
RD20
CD36
93 94
95 VSS45 VSS46 96
C 97 DQS8_c DM8_n/DBI_n/NC 98 C
2
99 DQS8_t VSS47 100
2
101 VSS48 CB6/NC 102
CB2/NC VSS49
1
24.9_0402_1%
103 104
VSS50 CB7/NC
RD21
105 106
107 CB3/NC VSS51 108 DDR_DRAMRST#_R
DDR_A_CKE0 109 VSS52 RESET_n 110 DDR_A_CKE1
<7> DDR_A_CKE0 CKE0 CKE1 DDR_A_CKE1 <7> 1
111 112
2
DDR_A_BG1 113 VDD1 VDD2 114 DDR_A_ACT# @CD6
<7> DDR_A_BG1 DDR_A_BG0 115 BG1 ACT_n 116 DDR_A_ALERT# DDR_A_ACT# <7>
<7> DDR_A_BG0 BG0 ALERT_n DDR_A_ALERT# <7> 0.1U_0402_25V6
117 118 2
DDR_A_MA12 119 VDD3 VDD4 120 DDR_A_MA11
follow INTEL PDG1.0 page167
DDR_A_MA9 121 A12 A11 122 DDR_A_MA7
123 A9 A7 124
DDR_A_MA8 125 VDD5 VDD6 126 DDR_A_MA5
Layout Note: DDR_A_MA6 127 A8 A5 128 DDR_A_MA4
A6 A4
Place near DDR_A_MA3
129
131 VDD7 VDD8
130
132 DDR_A_MA2 JDIMM1_EVENT# 1 2
JDIMM1.203,204 DDR_A_MA1 133 A3 A2 134 JDIMM1_EVENT# @ RD61 1K_0402_5%
H_THERMTRIP# <12,21,32>
135 A1 EVENT_n/NF 136
DDR_A_CLK0 137 VDD9 VDD10 138 DDR_A_CLK1
<7> DDR_A_CLK0 DDR_A_CLK#0 139 CK0_t CK1_t/NF 140 DDR_A_CLK#1 DDR_A_CLK1 <7>
<7> DDR_A_CLK#0 141 CK0_c CK1_c/NF 142 DDR_A_CLK#1 <7>
DDR_A_PARITY 143 VDD11 VDD12 144 DDR_A_MA0
<7> DDR_A_PARITY PARITY A0
DDR_A_BA1 145 146 DDR_A_MA10

+2.5V_MEM <7> DDR_A_BA1 147 BA1 A10/AP 148
+0.6V_DDR_VTT
DDR_A_CS#0 149 VDD13 VDD14 150 DDR_A_BA0
<7> DDR_A_CS#0 DDR_A_MA14 CS0_n BA0 DDR_A_MA16 DDR_A_BA0 <7>
151 152
<7> DDR_A_MA14 153 WE_n/A14 RAS_n/A16 154
VDD15 VDD16
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_10V6M
10U_0603_10V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_10V6M
10U_0603_10V6M
DDR_A_ODT0 155 156 DDR_A_MA15

<7> DDR_A_ODT0 DDR_A_CS#1 157 ODT0 CAS_n/A15 158 DDR_A_MA13
1 1 1 1 1 1 1 1 <7> DDR_A_CS#1 CS1_n A13
1
1
CD24
CD25
CD26
CD27
@ 159 160 +DDR_VREF_A_CA

DDR_A_ODT1 VDD17 VDD18
CD28
CD29
CD70
CD71
CD72
CD73
161 162 T50 @ PAD~D

<7> DDR_A_ODT1 163 ODT1 C0/CS2_n/NC 164 +DDR_VREF_A_CA
2
2 2 2 2 2 2 2 2 PAD~D @ T51 165 VDD19 VREFCA 166 DIMM1_SA2

167 C1, CS3_n,NC SA2 168
171 DQ37 DQ36 172
B DDR_A_D26 173 VSS55 VSS56 174 DDR_A_D25 B
175 DQ33 DQ32 176

181 DQS4_t VSS59 182 DDR_A_D28
DDR_A_D27 183 VSS60 DQ39 184
185 DQ38 VSS61 186 DDR_A_D24
DDR_A_D29 187 VSS62 DQ35 188
189 DQ34 VSS63 190 DDR_A_D20
DDR_A_D21 191 VSS64 DQ45 192
193 DQ44 VSS65 194 DDR_A_D16
DDR_A_D17 195 VSS66 DQ41 196
197 DQ40 VSS67 198 DDR_A_DQS#2
DIMM Select +3.3V_RUN +3.3V_RUN +3.3V_RUN
+3.3V_RUN DDR_A_D19
199
201
203
VSS68
DM5_n/DBI5_n
VSS69
DQS5_c
DQS5_t
VSS70
200
202
204
DDR_A_DQS2
DDR_A_D18 +1.2V_MEM
DQ46 DQ47
1
205 206
@ RD62 @ RD63 @ RD64 DDR_A_D22 207 VSS71 VSS72 208 DDR_A_D23 UD1
DQ42 DQ43
1
0_0402_5% 0_0402_5% 0_0402_5% 209 210 1 5 1 2

@RD65 DDR_A_D48 211 VSS73 VSS74 212 DDR_A_D53 NC VCC @ CD30 0.1U_0201_10V6K
0_0603_5% 213 DQ52 DQ53 214 2
2
DDR_A_D49 215 VSS75 VSS76 216 DDR_A_D52 <7> DDR_VTT_CTRL A 4

DIMM1_SA0 217 DQ49 DQ48 218 3 Y 0.6V_DDR_VTT_ON <45>
2
DIMM1_SA1 +3.3V_RUN_DIMM1 DDR_A_DQS#6 219 VSS77 VSS78 220 GND 1 2

DIMM1_SA2 DDR_A_DQS6 DQS6_c DM6_n/DBI6_n +3.3V_ALW
0.1U_0201_10V6K
221 222 SN74AUP1G07DCKR SC70 5P RD30 100K_0402_5%

SA0 SA1 SA2 DQS6_t VSS79
2.2U_0402_6.3V6M
223 224 DDR_A_D54

1 1 VSS80 DQ54
1
CD32
DDR_A_D50 225 226

DIMM1 0 0 0 DQ55 VSS81 DDR_A_D55
CD31
@RD66 @RD67 @RD68 227 228

0_0402_5% 0_0402_5% 0_0402_5% DDR_A_D51 229 VSS82 DQ50 230
DIMM2 1 0 0 2 2 231 DQ51 VSS83 232 DDR_A_D61
DDR_A_D56 233 VSS84 DQ60 234
DIMM3 0 1 0
2
235 DQ61 VSS85 236 DDR_A_D60

DDR_A_D57 237 VSS86 DQ57 238
DIMM4 1 1 0 239 DQ56 VSS87 240 DDR_A_DQS#7
241 VSS88 DQS7_c 242 DDR_A_DQS7
243 DM7_n/DBI7_n DQS7_t 244
247 DQ62 DQ63 248
A 251 DQ58 DQ59 252 A
253 VSS93 VSS94 254
<8,14,21,42> DDR_XDP_WAN_SMBCLK +3.3V_RUN_DIMM1 255 SCL SDA 256 DIMM1_SA0 DDR_XDP_WAN_SMBDAT <8,14,21,42>
257 VDDSPD SA0 258
+2.5V_MEM VPP1 VTT DIMM1_SA1 +0.6V_DDR_VTT
259 260
261 VPP2 SA1 262
GND1 GND2
LOTES_ADDR0107-P005A
CONN@
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT DDR4
5 4 3 2 1
5 4 3 2 1
<7> DDR_B_DQS#[0..7]
JDIMM2 REV Type H=4
+1.2V_MEM +1.2V_MEM
<7> DDR_B_D[0..63] JDIMM2
<7> DDR_B_DQS[0..7] 1 2
DDR_B_D1 3 VSS1 VSS2 4 DDR_B_D5
<7> DDR_B_MA[0..16] 5 DQ5 DQ4 6
9 DQ1 DQ0 10
DDR_B_DQS#0 11 VSS5 VSS6 12
Vinafix.com DDR_B_DQS0 13 DQS0_c DM0_n/DBI0_n 14

15 DQS0_t VSS7 16 DDR_B_D2
DDR_B_D7 17 VSS8 DQ6 18
19 DQ7 VSS9 20 DDR_B_D3
Layout Note: DDR_B_D6 21 VSS10 DQ2 22
D DQ3 VSS11 D
Place near JDIMM2 DDR_B_D13
23
25 VSS12 DQ12
24
26
DDR_B_D9
27 DQ13 VSS13 28 DDR_B_D8

DDR_B_D12 29 VSS14 DQ8 30
31 DQ9 VSS15 32 DDR_B_DQS#1
33 VSS16 DQS1_c 34 DDR_B_DQS1
35 DM1_n/DBI_n DQS1_t 36
39 DQ15 DQ14 40 JDIMM2_EVENT# 1 2
+1.2V_MEM DDR_B_D15 41 VSS19 VSS20 42 DDR_B_D10 H_THERMTRIP# <12,20,32>
@ RD4 1K_0402_5%
43 DQ10 DQ11 44
47 DQ21 DQ20 48
DDR_B_D36 VSS23 VSS24 DDR_B_D32
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
49 50
51 DQ17 DQ16 52
VSS25 VSS26
1
1
DDR_B_DQS#4 53 54
DDR_B_DQS4 DQS2_c DM2_n/DBI2_n
CD37
CD38
CD39
CD40
CD41
CD42
CD43
CD44
CD102
CD103
CD104
CD105
CD106
CD107
CD108
CD109
55 56
57 DQS2_t VSS27 58 DDR_B_D34
2
2
DDR_B_D39 59 VSS28 DQ22 60
61 DQ23 VSS29 62 DDR_B_D35
DDR_B_D38 63 VSS30 DQ18 64
65 DQ19 VSS31 66 DDR_B_D40
DDR_B_D42 67 VSS32 DQ28 68
69 DQ29 VSS33 70 DDR_B_D41
DDR_B_D43 71 VSS34 DQ24 72
+1.2V_MEM 75 VSS36 DQS3_c 76 DDR_B_DQS5
81 DQ30 DQ31 82
VSS39 VSS40
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
330U_D3_2.5VY_R6M
DDR_B_D45 83 84 DDR_B_D47
85 DQ26 DQ27 86
87 VSS41 VSS42 88
CB5/NC CB4/NC
1
89 90
@CD53
VSS43 VSS44
1
1
CD45
CD46
CD47
CD48
CD49
CD50
CD51
CD52
CD94
CD95
CD96
CD97
CD98
CD99
CD100
CD101
+ 91 92
93 CB1/NC CB0/NC 94
95 VSS45 VSS46 96
2
2
97 DQS8_c DM8_n/DBI_n/NC 98
99 DQS8_t VSS47 100
C 101 VSS48 CB6/NC 102 C
103 CB2/NC VSS49 104
105 VSS50 CB7/NC 106
107 CB3/NC VSS51 108 DDR_DRAMRST#_R
DDR_B_CKE0 109 VSS52 RESET_n 110 DDR_B_CKE1 DDR_DRAMRST#_R <20>
<7> DDR_B_CKE0 111 CKE0 CKE1 112 DDR_B_CKE1 <7>
DDR_B_BG1 113 VDD1 VDD2 114 DDR_B_ACT#
<7> DDR_B_BG1 BG1 ACT_n DDR_B_ACT# <7> 1
DDR_B_BG0 115 116 DDR_B_ALERT#
<7> DDR_B_BG0 117 BG0 ALERT_n 118 DDR_B_ALERT# <7> @CD35
DDR_B_MA12 119 VDD3 VDD4 120 DDR_B_MA11
A12 A11 0.1U_0402_25V6
DDR_B_MA9 121 122 DDR_B_MA7 2
123 A9 A7 124
DDR_B_MA6 127 A8 A5 128 DDR_B_MA4
129 A6 A4 130
DDR_B_MA1 133 A3 A2 134 JDIMM2_EVENT#
135 A1 EVENT_n/NF 136
DDR_B_CLK0 137 VDD9 VDD10 138 DDR_B_CLK1
<7> DDR_B_CLK0 DDR_B_CLK#0 139 CK0_t CK1_t/NF 140 DDR_B_CLK#1 DDR_B_CLK1 <7>
<7> DDR_B_CLK#0 141 CK0_c CK1_c/NF 142 DDR_B_CLK#1 <7>
DDR_B_PARITY 143 VDD11 VDD12 144 DDR_B_MA0
<7> DDR_B_PARITY PARITY A0
Layout Note:
Place near <7> DDR_B_BA1
DDR_B_BA1 145
147 BA1 A10/AP
146
148
DDR_B_MA10
JDIMM2.203,204 <7> DDR_B_CS#0

DDR_B_CS#0 149 VDD13 VDD14 150 DDR_B_BA0
DDR_B_BA0 <7>
DDR_B_MA14 151 CS0_n BA0 152 DDR_B_MA16
<7> DDR_B_MA14 153 WE_n/A14 RAS_n/A16 154
DDR_B_ODT0 155 VDD15 VDD16 156 DDR_B_MA15
<7> DDR_B_ODT0 DDR_B_CS#1 157 ODT0 CAS_n/A15 158 DDR_B_MA13
<7> DDR_B_CS#1 159 CS1_n A13 160 +DDR_VREF_B_CA
DDR_B_ODT1 161 VDD17 VDD18 162 T54 @ PAD~D
<7> DDR_B_ODT1 163 ODT1 C0/CS2_n/NC 164 +DDR_VREF_B_CA
+0.6V_DDR_VTT
PAD~D @ T55 165 VDD19 VREFCA 166 DIMM2_SA2 +1.2V_MEM
+2.5V_MEM 167 C1, CS3_n,NC SA2 168
VSS53 VSS54
1
DDR_B_D21 DDR_B_D16
1K_0402_1%
169 170
171 DQ37 DQ36 172
VSS55 VSS56
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_10V6M
10U_0603_10V6M
DDR_B_D20 173 174 DDR_B_D17
RD22
DQ33 DQ32
@ CD62
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_10V6M
10U_0603_10V6M
1 1 1 1 175 176
VSS57 VSS58
1
B B
CD57
CD58
CD59
CD60
CD61
DDR_B_DQS#2 177 178 +DDR_VREF_B_CA +DDR_VREF_B_DQ

1 1 1 1
2
DDR_B_DQS2 179 DQS4_c DM4_n/DBI4_n 180
DQS4_t VSS59 DDR_B_D18
CD74
CD75
CD76
CD77
181 182
2
2 2 2 2 DDR_B_D23 183 VSS60 DQ39 184 1 2

2 2 2 2 185 DQ38 VSS61 186 DDR_B_D19 RD75 2_0402_1%
DDR_B_D22 VSS62 DQ35
0.022U_0402_16V7K
187 188
DQ34 VSS63 DDR_B_D28
1K_0402_1%
189 190
VSS64 DQ45
1
DDR_B_D24 191 192
DQ44 VSS65
1
DDR_B_D29
RD24
CD54
193 194
DDR_B_D25 195 VSS66 DQ41 196
2
199 VSS68 DQS5_c 200 DDR_B_DQS3
2
DDR_B_D26 VSS69 VSS70 DDR_B_D31
24.9_0402_1%
203 204
DQ46 DQ47
1
205 206
+3.3V_RUN DDR_B_D27 VSS71 VSS72 DDR_B_D30
RD25
207 208
209 DQ42 DQ43 210
DIMM Select +3.3V_RUN +3.3V_RUN +3.3V_RUN DDR_B_D52 211 VSS73
DQ52
VSS74
DQ53
212 DDR_B_D53
1
213 214
2
@RD60 DDR_B_D49 215 VSS75 VSS76 216 DDR_B_D48
DQ49 DQ48
1
0_0603_5% 217 218 follow INTEL PDG1.0 page167

@ RD69 @RD70 @ RD71 DDR_B_DQS#6 219 VSS77 VSS78 220
0_0402_5% 0_0402_5% 0_0402_5% DDR_B_DQS6 221 DQS6_c DM6_n/DBI6_n 222
2
+3.3V_RUN_DIMM2 223 DQS6_t VSS79 224 DDR_B_D50

DDR_B_D55 VSS80 DQ54
0.1U_0201_10V6K
225 226
2
DQ55 VSS81
2.2U_0402_6.3V6M
227 228 DDR_B_D51

1 VSS82 DQ50
1
DIMM2_SA0
CD64
DDR_B_D54 229 230

DIMM2_SA1 DQ51 VSS83 DDR_B_D61
CD63
231 232
DIMM2_SA2 DDR_B_D56 233 VSS84 DQ60 234
SA0 SA1 SA2
2
2 235 DQ61 VSS85 236 DDR_B_D60

VSS86 DQ57
1
DDR_B_D57 237 238

DIMM1 0 0 0 @RD72 @ RD73 @RD74 239 DQ56 VSS87 240 DDR_B_DQS#7
0_0402_5% 0_0402_5% 0_0402_5% 241 VSS88 DQS7_c 242 DDR_B_DQS7
DIMM2 1 0 0 243 DM7_n/DBI7_n DQS7_t 244
* DIMM3 0 1 0
2
247 DQ62 DQ63 248

DIMM4 1 1 0 251 DQ58 DQ59 252
253 VSS93 VSS94 254
<8,14,20,42> DDR_XDP_WAN_SMBCLK +3.3V_RUN_DIMM2 255 SCL SDA 256 DIMM2_SA0 DDR_XDP_WAN_SMBDAT <8,14,20,42>
A A
257 VDDSPD SA0 258
+2.5V_MEM VPP1 VTT DIMM2_SA1 +0.6V_DDR_VTT
259 260
261 VPP2 SA1 262
GND1 GND2
LOTES_ADDR0107-P005A
CONN@ DELL CONFIDENTIAL/PROPRIETARY
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT DDR4
5 4 3 2 1
5 4 3 2 1
2 1 HDMI_TX_P2 EMC@ RV647 1 2 8.2_0402_1% HDMI_L_TX_P2

<6> CPU_DP1_P0 0.1U_0402_25V6
CV17
2
EMC@
Vinafix.com RV648
150_0402_5%
1
D <6> CPU_DP1_N0
2
CV18
1
0.1U_0402_25V6
HDMI_TX_N2
EMC@ RV649
1 2
8.2_0402_1%
HDMI_L_TX_N2
D

<6> CPU_DP1_P1 0.1U_0402_25V6
CV21
2
EMC@
RV651
150_0402_5%
1
2 1 HDMI_TX_N1 1 2 HDMI_L_TX_N1
<6> CPU_DP1_N1 0.1U_0402_25V6
CV22 EMC@ RV652 8.2_0402_1%

<6> CPU_DP1_P2 0.1U_0402_25V6
CV28
2
EMC@
RV654
150_0402_5%
1
2 1 HDMI_TX_N0 1 2 HDMI_L_TX_N0
<6> CPU_DP1_N2 0.1U_0402_25V6
CV29 EMC@ RV655 8.2_0402_1%
+5V_RUN
2 1 HDMI_CLKP EMC@ RV656 1 2 8.2_0402_1% HDMI_L_CLKP
<6> CPU_DP1_P3 0.1U_0402_25V6
CV13
2
EMC@
0.1U_0201_10V6K
RV657
150_0402_5% 1
C C
@
1
1
HDMI_CLKN HDMI_L_CLKN
CV23
2 1 1 2 +VHDMI_VCC
<6> CPU_DP1_N3 0.1U_0402_25V6 2
CV14 EMC@ RV658 8.2_0402_1%
IN
AP2330W-7_SC59-3
UV2
0.1U_0201_10V6K
10U_0603_10V6M
1
CV27
GND
OUT
@
CV26
2
2
3
HDMI connector
+3.3V_RUN
JHDMI1
HDMI_HPD 19
18 HP_DET
17 +5V
QV3A +VHDMI_VCC +3.3V_RUN HDMI_CTRL_DATA 16 DDC/CEC_GND
SDA
2
DMN65D8LDW-7_SOT363-6 HDMI_CTRL_CLK 15
14 SCL
1 6 HDMI_CTRL_CLK 1 2 2 1 HDMI_CEC 13 Reserved
<6> CPU_DP1_CTRL_CLK HDMI_L_CLKN CEC
RV21 2.2K_0402_5% 10K_0402_5% @ RV8 12 20
CK- GND
5
11 21
HDMI_L_CLKP 10 CK_shield GND 22
4 3 HDMI_CTRL_DATA 1 2 HDMI_L_TX_N0 9 CK+ GND 23
<6> CPU_DP1_CTRL_DATA D0- GND
RV18 2.2K_0402_5% 8
QV3B HDMI_TX_P2 RV10 1 2 470_0402_1% HDMI_OB HDMI_L_TX_P0 7 D0_shield
DMN65D8LDW-7_SOT363-6 HDMI_TX_N2 RV11 1 2 470_0402_1% HDMI_L_TX_N1 6 D0+
HDMI_TX_P1 RV12 1 2 470_0402_1% 5 D1-
HDMI_TX_N1 RV13 1 2 470_0402_1% HDMI_L_TX_P1 4 D1_shield
D1+
B HDMI_TX_P0
HDMI_TX_N0
RV14
RV15
1
1
2
2
470_0402_1%
470_0402_1%
HDMI_L_TX_N2 3
2 D2- B
HDMI_CLKP RV16 1 2 470_0402_1% HDMI_L_TX_P2 1 D2_shield
+3.3V_RUN HDMI_CLKN RV17 1 2 470_0402_1% D2+
CONCR_099BKAC19YBLCNF
1
D CONN@
1M_0402_5%
+3.3V_RUN RV19 1 2 10K_0402_5% 2 QV4

2
G L2N7002WT1G_SC-70-3
RV22
3
2
G
1
3 1 HDMI_HPD 1 2
<6> CPU_DP1_HPD RV20 20K_0402_5%
S
QV5
L2N7002WT1G_SC-70-3
A A
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT HDMI CONN
5 4 3 2 1
+3.3V_RUN
+3.3V_RUN
Dock has high priority when both ports plugged
0.01UF_0402_25V7K
0.01UF_0402_25V7K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
1 1 1
1
2 SW1_PS8338_CFG0
CV602
CV601
CV600
1 UV26
CV604
CV603
RV601 4.7K_0402_5%
5
2
2 2 2 21 VDD33 50
30 VDD33 OUT1_D0p 49 SW1_DP0_P0 <24>
51 VDD33 OUT1_D0n SW1_DP0_N0 <24>
RV604
1
1
2 SW1_DP0_AUXN
100K_0402_5%
2 SW1_DP1_AUXN
Vinafix.com 57 VDD33
VDD33 OUT1_D1p
OUT1_D1n
47
46 SW1_DP0_P1
SW1_DP0_N1
<24>
<24>
RV605 100K_0402_5% CV606 1 2 0.1U_0402_25V6 CPU_DP2_P0_C 6 45 -----> VMM3320
D <6> CPU_DP2_P0 CPU_DP2_N0_C IN_D0p OUT1_D2p SW1_DP0_P2 <24> D
CV607 1 2 0.1U_0402_25V6 7 44
1 2 SW1_DP0_CADET <6> CPU_DP2_N0 IN_D0n OUT1_D2n SW1_DP0_N2 <24>
RV606 1M_0402_5% CV608 1 2 0.1U_0402_25V6 CPU_DP2_P1_C 9 42
1 2 SW1_DP1_CADET <6> CPU_DP2_P1 CPU_DP2_N1_C IN_D1p OUT1_D3p SW1_DP0_P3 <24>
CV609 1 2 0.1U_0402_25V6 10 41
<6> CPU_DP2_N1 IN_D1n OUT1_D3n SW1_DP0_N3 <24>
RV607 1M_0402_5%
1 2 SW1_DP0_AUXP CV610 1 2 0.1U_0402_25V6 CPU_DP2_P2_C 12
<6> CPU_DP2_P2 CPU_DP2_N2_C IN_D2p
RV608 100K_0402_5% CV611 1 2 0.1U_0402_25V6 13 40
1 2 SW1_DP1_AUXP <6> CPU_DP2_N2 IN_D2n OUT2_D0p 39 SW1_DP1_P0 <29>
RV609 100K_0402_5% CV612 1 2 0.1U_0402_25V6 CPU_DP2_P3_C 15 OUT2_D0n SW1_DP1_N0 <29>
<6> CPU_DP2_P3 CPU_DP2_N3_C IN_D3p
CV613 1 2 0.1U_0402_25V6 16 37
<6> CPU_DP2_N3 IN_D3n OUT2_D1p 36 SW1_DP1_P1 <29>
OUT2_D1n SW1_DP1_N1 <29>
35 -----> WIGIG
4 OUT2_D2p 34 SW1_DP1_P2 <29>
+3.3V_RUN 3 IN_CA_DET OUT2_D2n SW1_DP1_N2 <29>
<6> CPU_DP2_HPD 2 IN_HPD 32
SW1_PS8338_P1 1 I2C_CTL_EN OUT2_D3p 31 SW1_DP1_P3 <29>
SW1_PS8338_P0 60 Pl1/SCL_CTL OUT2_D3n SW1_DP1_N3 <29>
Pl0/SDA_CTL
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
for support TMDS signal need contact SCL/SDA to P22,23 26

OUT1_AUXp_SCL SW1_DP0_AUXP <24>
1
22 27
<6> CPU_DP2_CTRL_CLK IN_DDC_SCL OUT1_AUXn_SDA SW1_DP0_AUXN <24>
@ RV610
@ RV611
@ RV612
@ RV613
@ RV614
@ RV603
@ RV615
23
<6> CPU_DP2_CTRL_DATA 2 0.1U_0402_25V6 CPU_DP2_AUXP_C 24 IN_DDC_SDA
CV79 1 28
<6> CPU_DP2_AUXP 2 0.1U_0402_25V6 CPU_DP2_AUXN_C 25 IN_AUXp OUT2_AUXp_SCL SW1_DP1_AUXP <29>
CV80 1 29
<6> CPU_DP2_AUXN IN_AUXn OUT2_AUXn_SDA SW1_DP1_AUXN <29>
2
SW1_PS8338_P0 SW1_PS8338_CFG0 59 43 SW1_DP0_CADET

58 CFG0 OUT1_CA_DET 48
SW1_PS8338_P1 SW1_PS8338_PC10 56 CFG1 OUT1_HPD SW1_DP0_HPD <24>
SW1_PS8338_PC11 55 PC10 33 SW1_DP1_CADET
SW1_PS8338_PC10 SW1_PS8338_PC20 54 PC11 OUT2_CA_DET 38
SW1_PS8338_PC21 53 PC20 OUT2_HPD SW1_DP1_HPD <29>
SW1_PS8338_PC11 PC21 18 SW1_PS8338_SW
C 11 SW 8 SW1_PS8338_PEQ C
SW1_PS8338_PC20 19 GND PEQ 14
52 GND PD 17
SW1_PS8338_PC21 61 GND CEXT 20
PAD(GND) REXT
2.2U_0402_6.3V6M
1
SW1_PS8338_PEQ
4.99K_0402_1%
PS8338BQFN60GTR-A0_QFN60_5X9
1
RV600
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
1
CV605
@ RV616
@ RV617
@ RV618
@ RV619
@ RV620
@ RV621
2
2
2
+3.3V_RUN
1
RV602 Port switching control or priority configuration. Internal pull down ~150KΩ, 3.3V I/O
4.7K_0402_5%
For Control Switching Mode (CFG0 = L):
2
SW1_PS8338_SW
SW = L: Port1 is selected (default)
1
D SW = H: Port2 is selected
2 QV11
<25,27,31> DOCKED
G L2N7002WT1G_SC-70-3 For Automatic Switching Mode (CFG0 = H):
S SW = L: Port1 has higher priority when both ports are plugged (default)
3
B SW = H: Port2 has higher priority when both ports are plugged B
A A
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT DP SW
5 4 3 2 1
2 1
+1.0V_RUN_VMM
+3.3V_RUN_VDDA +3.3V_RUN_VMM
LV22 UV8B LV25
1 2 +1.0V_VMM_VDD E6 3.3V Analog H5 1 2
BLM15PX181SN1D_2P E7 VDD VDDRX_33 C10 BLM15PX181SN1D_2P
Vinafix.com
VDD VDDTX0_33
10U_0603_10V6M
0.1U_0201_10V6K
0.1U_0201_10V6K
0.01UF_0402_25V7K
0.01UF_0402_25V7K
0.01UF_0402_25V7K
0.01UF_0402_25V7K
0.1U_0201_10V6K
E8 H12
VDD VDDTX1_33
10U_0603_10V6M
1 1 E9 K6 1
VDD VGA_AVDD33
1
CV83
CV84
CV100
H6 K7
VDD VGA_AVDD33
CV82
CV85
CV86
CV98
CV99
CV101
H7 UV8A
VDD SW1_DP0_P0_C
1V Digital
H8 0.1U_0402_25V6 1 2 CV102 G1 B7
2
2 2 H9 VDD C5 2 <23> SW1_DP0_P0 1 2 SW1_DP0_N0_C G2 RxP0 Tx0P0 A7 HUB_DP0_P0 <38>
0.1U_0402_25V6 CV103
VDD VSS D5 <23> SW1_DP0_N0 1 2 SW1_DP0_P1_C F1 RxN0 Tx0N0 B8 HUB_DP0_N0 <38>
0.1U_0402_25V6 CV104
E3 VSS D6 <23> SW1_DP0_P1 1 2 SW1_DP0_N1_C F2 RxP1 Tx0P1 A8 HUB_DP0_P1 <38>
0.1U_0402_25V6 CV105
G3 VDDRX VSS D7 <23> SW1_DP0_N1 1 2 SW1_DP0_P2_C E1 RxN1 Tx0N1 B9 HUB_DP0_N1 <38>
0.1U_0402_25V6 CV106
VDDRX VSS D8 <23> SW1_DP0_P2 1 2 SW1_DP0_N2_C E2 RxP2 Tx0P2 A9 HUB_DP0_P2 <38>
0.1U_0402_25V6 CV107
C8 VSS D9 <23> SW1_DP0_N2 1 2 SW1_DP0_P3_C D1 RxN2 Tx0N2 B10 HUB_DP0_N2 <38>
0.1U_0402_25V6 CV108
C9 VDDTX0 VSS D10 <23> SW1_DP0_P3 1 2 SW1_DP0_N3_C D2 RxP3 Tx0P3 A10 HUB_DP0_P3 <38>
0.1U_0402_25V6 CV109
VDDTX0 VSS <23> SW1_DP0_N3 RxN3 Tx0N3 HUB_DP0_N3 <38>
1U_0603_10V6K
0.1U_0201_10V6K
0.01UF_0402_25V7K
F12 D11 0.1U_0402_25V6 1 2 CV110 SW1_DP0_AUXP_C H1 A14
+1.0VS_VCCIO G12 VDDTX1 VSS E4 <23> SW1_DP0_AUXP 1 2 SW1_DP0_AUXN_C H2 RxAUXP CAD0 B11 HUB_DP0_AUXP HUB_DP0_CADET <25,38>
1 0.1U_0402_25V6 CV111
VDDTX1 VSS <23> SW1_DP0_AUXN RXAUXN Tx0AUXP HUB_DP0_AUXP <25>
1
1
CV88 E11 HUB_SRCDET C2 A11 HUB_DP0_AUXN
VSS RxSRCDET Tx0AUXN HUB_DP0_AUXN <25>
CV87
CV89
J3 F4 J1 B12 HUB_DP0_SCL
VDDLP VSS F5 <23> SW1_DP0_HPD RxHPD Tx0DDCSCL A12 HUB_DP0_SDA HUB_DP0_SCL <25>
HUB_DP0_SDA <25>
2
2
2 E5 VSS F6 Tx0DDCSDA A6
+1.0V_RUN_VMM VDDLP VSS F7 Tx0HPD HUB_DP0_HPD <38>
H3 VSS A13 E13
F3 NC F8 <11> PLTRST_VMM2320# RSTN_IN Tx1P0 E14 HUB_DP1_P0 <38>
LV23
1 2 +1.0V_VMM_VDDTX D3 VDDRXA1 VSS F9 2 1 HUB_GPIO9 B5 Tx1N0 F13 HUB_DP1_N0 <38>
VDDRX VSS +3.3V_RUN_VDDIO VDDIO Tx1P1 HUB_DP1_P1 <38>
BLM15PX181SN1D_2P F10 1M_0402_5% @ RV73 B6 F14
1 V Analog
VSS 1 HUB_DP0_AUXP HUB_SPI_WP# VDDIO Tx1N1 HUB_DP1_N1 <38>
10U_0603_10V6M
0.1U_0201_10V6K
0.01UF_0402_25V7K
0.01UF_0402_25V7K
E10 F11 2 B1 G13

C7 NC VSS G4 1M_0402_5% RV74 NC Tx1P2 G14 HUB_DP1_P2 <38>
B 1 VDDTX0A1 VSS Tx1N2 HUB_DP1_N2 <38> B
1
1
CV90
CV91
CV92
CV93
C6 G5 2 1 HUB_DP1_AUXP H13
VDDTX0A2 VSS 1M_0402_5% RV75 HUB_SPI_CS# A4 Tx1P3 H14 HUB_DP1_P3 <38>
H11 G6 2 1 HUB_VGA_RED HUB_SPI_CLK B3 SPICS Tx1N3 M14 HUB_DP1_N3 <38>
2
2 E12 NC VSS G7 150_0402_1% RV76 HUB_SPI_DIN B4 SPICLK CAD1 J13 HUB_DP1_AUXP HUB_DP1_CADET <25,38>
D12 VDDTX1A1 VSS G8 2 1 HUB_VGA_GREEN HUB_SPI_DO A3 SPIDI Tx1AUXP J14 HUB_DP1_AUXN HUB_DP1_AUXP <25>
VDDTX1A2 VSS G9 SPIDO Tx1AUXN K13 HUB_DP1_SCL HUB_DP1_AUXN <25>
150_0402_1% RV77
J10 VSS G10 2 1 HUB_VGA_BLUE Tx1DDCSCL L14 HUB_DP1_SDA HUB_DP1_SCL <25>
+3.3V_RUN_VMM K8 VGA_AVDD VSS G11 D14 Tx1DDCSDA K14 HUB_DP1_SDA <25>
150_0402_1% RV78
LV24 K9 VGA_AVDD VSS H4 2 1 VMM3320_LPM_DIS D13 GPIO0 Tx1HPD HUB_DP1_HPD <38>
1 2 +3.3V_RUN_VDDIO K10 VGA_AVDD VSS D4 100K_0402_5% @ RV79 C14 GPIO1 L9
BLM15PX181SN1D_2P VGA_AVDD VSS C13 GPIO2 VGA_VSYNC M9 HUB_VGA_VSYNC <25>
HUB_GPIO4 GPIO3 VGA_HSYNC HUB_VGA_HSYNC <25>
10U_0603_10V6M
0.1U_0201_10V6K
0.01UF_0402_25V7K
0.01UF_0402_25V7K
J2 B14 M6
VDDSA J5 HUB_GPIO5 B13 GPIO4 VGA_RP L6 HUB_VGA_RED <25>
1 VSS GPIO5 VGA_RN
1
HUB_GPIO6
CV95
C3 J11 C1 M7
VDDHRX_33 VSS GPIO6 VGA_GP HUB_VGA_GREEN <25>
CV94
CV96
CV97
C4 J12 HUB_GPIO7 M12 L7

VDDHRX_33 VSS GPIO7 VGA_GN
3.3V IO
C11 K5 +3.3V_RUN_VMM HUB_GPIO8 M13 M8
2
2 C12 VDDHTX0_33 VSS H10 HUB_GPIO9 L3 NC VGA_BP L8 HUB_VGA_BLUE <25>

K3 VDDIO VGA_AVSS J6 2 1 VMM3320_LPM_DIS VMM3320_LPM_DIS B2 NC VGA_BN L4
K4 VDDIO VGA_AVSS J7 <9> VMM3320_LPM_DIS HUB_LP_EN A5 LP_CTL VGA_SCL M4 HUB_VGA_SCL <25>
2.2K_0402_5% @ RV516
K11 VDDIO VGA_AVSS J8 LP_EN VGA_SDA HUB_VGA_SDA <25>
K12 VDDIO VGA_AVSS J9
J4 VDDIO VGA_AVSS M3 HUB_VGA_DET
+3.3V_RUN_VDDA VDDXT3V VGA_DET HUB_VGA_IREF
K2 M5
VMM3320BJGR_BGA168 L2 RX_STS VGA_IREF L5 HUB_VGA_NC @ T108PAD~D
M1 TX0_STS NC
M2 TX1_STS A1 I2C_HUB_SDA
TX2_STS SSDA A2 I2C_HUB_SCL
+1.0VS_VCCIO +1.0V_RUN_VMM SSCL
PJP24 M11
1 2 0.786A CLK_27M_IN K1 NC M10
XIN RxDDCSDA L12
NC
1
1M_0402_5%
L13
PAD-OPEN1x1m CLK_27M_OUT L1 NC L11
XOUT NC
RV80
L10
+3.3V_RUN +3.3V_RUN_VMM RxDDCSCL
PJP25 YV2
74mA
2
1 2 27MHZ_12PF_X1E000021042600 VMM3320BJGR_BGA168
1 3 CLK_27M_OUT_R 1 2
IN OUT
18P_0402_50V8J
18P_0402_50V8J
RV81 2.2K_0402_5%
PAD-OPEN1x1m 2 4
GND GND
CV113
+3.3V_RUN_VMM
CV115
2
2
HUB_DP1_AUXN 1 2
1M_0402_5% RV82
HUB_GPIO6 1 2
2.2K_0402_5% RV83
HUB_SRCDET 1 2
1M_0402_5% RV84
+5V_ALW HUB_SPI_WP# 2 1
2.2K_0402_5% @ RV517
+1.0V_RUN_VMM
HUB_GPIO4 2 1
2
0_0402_5%
2.2K_0402_5% @ RV518
HUB_GPIO5
@ RV662
2 1
VO=0.8*(R1+R2)/R2 Volt
1
2.2K_0402_5% @ RV519
RV659
27.4K_0402_1% RPV1
1
2 1 UV29 HUB_DP1_SCL 1 8
CV619 1U_0402_6.3V6K 10 1 100K_0402_5% 2 1 RV661 HUB_DP1_SDA 2 7
EEPROM
2
ADJ HUB_LP_EN 9 VCNTL POK 2 ADJ +3.3V_RUN_VMM HUB_GPIO8 3 6

+1.8V_PRIM 8 EN FB 3 HUB_GPIO7 4 5
VIN VOUT
1
7 4 CV114 8/21 for layout routing

GND
VIN VOUT +1.0V_RUN_VMM

RV660 6 5 1 2 2.2K_0804_8P4R_5%
VIN VOUT
1
88.7K_0402_1% RPV2
1
CV618 UV9 0.1U_0201_10V6K I2C_HUB_SDA 1 8

11
10U_0603_10V6M CV617 HUB_SPI_CS# 1 8 I2C_HUB_SCL 2 7

2
10U_0603_10V6M HUB_SPI_DIN 2 CS# VCC 7 HUB_SPI_HOLD HUB_DP0_SDA 3 6

2
HUB_SPI_WP# 3 DO(IO1) HOLD#(IO3) 6 HUB_SPI_CLK HUB_DP0_SCL 4 5

4 WP#(IO2) CLK 5 HUB_SPI_DO
APL5930QBI-TRG_TDFN10_3X3 GND DI(IO0) 2.2K_0804_8P4R_5%
W25X10CVSNIG_SO8 HUB_DP0_AUXN 1 2
1M_0402_5% RV85
HUB_SPI_CS# 2 1
10K_0402_5% RV86
HUB_SPI_HOLD 2 1
2.2K_0402_5% RV87
A Low Power Mode by external Load switch Pop UV28 &PJP33, depop PJP24
HUB_VGA_DET
10K_0402_5%
2 1
RV88
A
HUB_VGA_IREF 1 2
3.74K_0402_1% RV89
+1.0V_RUN_VMM
1
PJP33
PAD-OPEN1x1m
+1.0VS_VCCIO
@ UV28
2 1 1
2
@ CV616 1U_0402_6.3V6K 2 VIN1

VIN2
+5V_ALW 7 6 +1.0V_RUN_VMM_P 1 2
VIN thermal VOUT @ CV615 0.1U_0201_10V6K
3
VBIAS
HUB_LP_EN 4 5
ON GND
TPS22961DNYR_WSON8
VMM2320 Operation power consumption for 1.0V=1.464A (Max) TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
DP 1.2 MST HUB
2 1
5 4 3 2 1
+3.3V_RUN_VMM
+3.3V_RUN
+3.3V_RUN +5V_RUN
AUX/DDC SW for DPC to E-DOCK CV121
1 2
1 2 HUB_VGA_SDA
VGA SW for MB/DOCK 0.1U_0201_10V6K
0.01UF_0402_25V7K
0.01UF_0402_25V7K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
RV250 2.2K_0402_5% Use SA00004RS00 as main source UV12
1
RV251
2 HUB_VGA_SCL
2.2K_0402_5% Vinafix.com 1
@
1
@
1 1 1 1 <24> HUB_DP0_AUXP
2
CV122
1 HUB_DP0_AUXP_C
0.1U_0402_25V6
1
2 BE0
A0
VCC
BE3
14
13
CV128
CV127
CV126
CV125
CV124
CV144
+5V_RUN +3.3V_RUN 3 12
D <38> HUB_SW1_AUXP B0 A3 HUB_DP0_SCL <24> D
UV16 2 2 2 2 2 2 4 11
1 16 2 1 HUB_DP0_AUXN_C 5 BE1 B3 10
<24> HUB_VGA_RED 2 R 5V VDD <24> HUB_DP0_AUXN A1 BE2
CV123 0.1U_0402_25V6
<24> HUB_VGA_GREEN 5 G 4 6 9
<24> HUB_VGA_BLUE 6 B VDD 23 <38> HUB_SW1_AUXN B1 A2 HUB_DP0_SDA <24>
<24> HUB_VGA_HSYNC 7 H_SOURCE VDD 32 7 8
<24> HUB_VGA_VSYNC 9 V_HOURCE VDD GND B2
<24> HUB_VGA_SDA 10 SDA_SOURCE 27 SW2_VGA1_RED PI3C3125LEX_TSSOP14~D
<24> HUB_VGA_SCL SCL_SOURCE R1 25 SW2_VGA1_GREEN
G1 22 SW2_VGA1_BLUE
DOCKED 30 B1 20 SW2_VGA1_HSYNC
<23,27,31> DOCKED SEL H1_OUT 18 SW2_VGA1_VSYNC +3.3V_RUN_VMM
V1_OUT 12 SW2_VGA1_SDA
29 SDA1 14 SW2_VGA1_SCL
+3.3V_RUN TEST SCL1
100K_0402_5%
1
RV121 1 2 4.7K_0402_5% 8 26
+3.3V_RUN Reserved R2 SW2_VGA2_RED <38>
24
G2 SW2_VGA2_GREEN <38>
RV91
3 21
11 GND B2 19 SW2_VGA2_BLUE <38>
28 GND H2_OUT 17 SW2_VGA2_HSYNC <38>
2
31 GND V2_OUT 13 SW2_VGA2_VSYNC <38>
33 GND SDA2 15 SW2_VGA2_SDA <38> HUB_DP0_CADETN
GPAD SCL2 SW2_VGA2_SCL <38>
L2N7002WT1G_SC-70-3
SEL Chanel Source
TS3V713ELRTGR_WQFN32_6X3~D
1
D
0 A=B1 MB HUB_DP0_CADET
QV10
2
<24,38> HUB_DP0_CADET
1 A=B2 APR/SPR G
S
3
C C
+3.3V_RUN_VMM
AUX/DDC SW for DPB to E-DOCK CV118
1 2
0.1U_0201_10V6K
+5V_RUN
UV11
2
3
PJDLC05C_SOT23-3
PJDLC05C_SOT23-3
1 14
1 HUB_DP1_AUXP_C BE0 VCC
@EMC@ DV5
@EMC@ DV6
2 2 13
<24> HUB_DP1_AUXP A0 BE3
1
CV119 0.1U_0402_25V6
UV4 3 12
IN
<38> HUB_SW2_AUXP B0 A3 HUB_DP1_SCL <24>
AP2330W-7_SC59-3
4 11
2 1 HUB_DP1_AUXN_C 5 BE1 B3 10
<24> HUB_DP1_AUXN A1 BE2
CV120 0.1U_0402_25V6
6 9
HUB_DP1_SDA <24>
1
<38> HUB_SW2_AUXN B1 A2
GND
OUT
7 8
SW2_VGA1_RED 1 2 GND B2
EMC@ LV16 BLM15BB470SN1D_2P PI3C3125LEX_TSSOP14~D
2
SW2_VGA1_GREEN 1 2 +CRT_VCC
EMC@ LV17 BLM15BB470SN1D_2P
SW2_VGA1_BLUE 1 2
EMC@ LV18 BLM15BB470SN1D_2P +3.3V_RUN_VMM
40mils
2.2P_0402_50V8C
2.2P_0402_50V8C
2.2P_0402_50V8C
3.3P_0402_50V8C
3.3P_0402_50V8C
3.3P_0402_50V8C
1
1
1
150_0402_1%
150_0402_1%
150_0402_1%
100K_0402_5%
B B
1 1 1
1
1 1 1 CV50
RV90
RV32
RV33
RV34
CV54
CV55
CV56
1U_0402_6.3V6K
2 JCRT1
2 2 2
CV51
CV52
CV53
@ @ @ 6
2
2 2 2 @ T87 PAD~D JCRT-11 11
2
VGA1_RED_L 1
7 HUB_DP1_CADETN
12
VGA1_GREEN_L
L2N7002WT1G_SC-70-3
+CRT_VCC 2
8
1
VGA1_HSYNC_L 13 D
VGA1_BLUE_L HUB_DP1_CADET
QV9
3 2
<24,38> HUB_DP1_CADET
1K_0402_5%
1K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
9 G
1
VGA1_VSYNC_L 14 16 S
G
3
M_ID2#
RV35
RV36
RV37
RV38
4 17
G
10
15
@
5
2
SW2_VGA1_SDA
0.1U_0402_25V6
1 FUTUR_061-D531-0207
SW2_VGA1_SCL
CV57
CONN@
SW2_VGA1_HSYNC 1 2
EMC@ LV19 BLM15AG121SN1D_L0402_2P 2
SW2_VGA1_VSYNC 1 2 1 2 HUB_DP1_CADET
EMC@ LV20 BLM15AG121SN1D_L0402_2P RV508 1M_0402_5%
DP HDMI
22P_0402_50V8J
22P_0402_50V8J
1 2 HUB_DP0_CADET
1 1 DPB_CA_DET 0 1
CV58
CV59
RV509 1M_0402_5%
@
A 2 2 DPC_CA_DET 0 1 A
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT DP SW
5 4 3 2 1
5 4 3 2 1
LINK 50398-04041-001 DONE

+3.3V_TSP
TOUCH_PANEL_INTR#:  EMC@
JEDP1 Close lid >> TP_EN = 0 >> Disable touch events LV27
1 Open lid >> TP_EN = 1 >> Enable touch events 1 2
1 2 USB20_N9_R 1 2 USB20_N9 <10>
2 3 USB20_P9_R
3 4 4 3
4 5 4 3 USB20_P9 <10>
5 6 TOUCH_SCREEN_PD# <12>
MCM1012B900F06BP_4P
6
PESD5V0U2BT_SOT23-3
7
7 DMIC0 <30>
@EMC@ DV4
8
8 9
Vinafix.com
3
9 10 DMIC_CLK0 <30>
10
11
11
USB20_N2_R +3.3V_CAM
+3.3V_RUN
IR CAM Conn
100P_0402_50V8J
@EMC@ CA5
100P_0402_50V8J
@EMC@ CA6
1
12
D 12 13 USB20_P2_R D
1
13
1
14 +PWR_SRC
14 15 CAM_MIC_CBL_DET# <12>
15 16 Pin15: LOOP_BACK JIR1
2
16 17 1
17 +BL_PWR_SRC <9> IR_CAM_DET# 1
18 2
18 19 3 2
19 ESD depop location 3
20 +3.3V_RUN 4
20 21 EMC@ LV1 1 2 BIA_PWM 5 4
21 22 DISP_ON BLM15BB221SN1D_2P 6 5
22 6
1
10K_0402_5%
23 7
23 24 8 GND
24 GND
RV623
25
25 26 ACES_50450-0067N-P01
26 27 EDP_HPD <6>
CONN@
2
27 28 TOUCH_SCREEN_DET#
28 29
29 30 LCD_TST <31>
30 31
31 +LCDVDD
TOUCH_SCREEN_DET#
32
32 33 EDP_AUXN_C CV1 2 1TOUCH_SCREEN_DET#
0.1U_0402_25V6
<12>
33 34 EDP_AUXP_C 2 1 0.1U_0402_25V6 EDP_AUXN <6>
CV2
34 35 EDP_TXP0_C 2 1 0.1U_0402_25V6 EDP_AUXP <6>
CV3
41 35 36 EDP_TXN0_C 2 1 0.1U_0402_25V6 EDP_TXP0 <6>
CV4
42 G1 36 37 EDP_TXP1_C 2 1 0.1U_0402_25V6 EDP_TXN0 <6>
CV5
43 G2 37 38 EDP_TXN1_C 2 1 0.1U_0402_25V6 EDP_TXP1 <6>
CV6
44 G3 38 39 EDP_TXN1 <6>
45 G4 39 40
G5 40 LCD_CBL_DET# <9>
ACES_50398-04041-001
CONN@
C
For Touchscreen C
+BL_PWR_SRC +LCDVDD +3.3V_CAM +3.3V_TSP +3.3V_RUN +3.3V_RUN +3.3V_TSP +3.3V_RUN

QV8
0.1U_0603_50V7K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
LP2301ALT1G_SOT23-3
1
10K_0402_5%
1 1 1 1
1
@ @ @ @ 1 3
S
CV7
CV8
CZ1
CZ2
CA7
RV6
2
2 2 2 2
G
2
2
Close to JEDP1.17~19 Close to JEDP1.30~31 Close to JEDP1.11 Close to JEDP1.1 Close to JEDP1.10
L2N7002WT1G_SC-70-3
1
D
DV2
QV7
DV1 2
3 3 <9> TS_EN
G
EDP_BIA_PWM <6> PANEL_BKLEN <6>
S
3
BIA_PWM 1 DISP_ON 1
2 2
BIA_PWM_EC <32> PANEL_BKEN_EC <31>
1
4.7K_0402_5%
4.7K_0402_5%
1
BAT54CW_SOT323-3
BAT54CW_SOT323-3
RV1
RV2
2
B B
WebCAM Backlight POWER +BL_PWR_SRC LCDVDD POWER +LCDVDD +EDP_VDD

+PWR_SRC QV1 +3.3V_ALW
@ CV9 PJP29 UV24
+3.3V_CAM +3.3V_RUN 6 2 1 1 2 1
D
4 5 VOUT 5
S
QZ1 2 10U_0603_10V6M VIN

1000P_0402_50V7K
LP2301ALT1G_SOT23-3 1 PAD-OPEN1x1m 2
GND
270K_0402_5%
0.1U_0603_50V7K
0.01UF_0402_25V7K
4
G
EN
1
@
1 3 AO6405_TSOP6
D
3
1
CV10
3
/OC
CV11
RV4
CV12
DV3 G524B1T11U_SOT23-5
G
2
2
2
2
<31> LCD_VCC_TEST_EN
<11> 3.3V_CAM_EN# BL_PWR_SRC_ON 1 EN_LCDPWR
QV2 3
<6,32> ENVDD_PCH
2
100K_0402_5%
L2N7002WT1G_SC-70-3
0.01U_0402_50V7K
RV3
1
1 2 1 3 BAT54CW_SOT323-3
D
S
CV374
RV5 47K_0402_5%
MCM1012B900F06BP_4P
1
4 3 USB20_P2_R 2
G
<10> USB20_P2
2
4 3
A 1 2 USB20_N2_R A
<10> USB20_N2 1 2 <32> EN_INVPWR
LZ1 EMC@
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT eDP CONN & Touch screen
5 4 3 2 1
5 4 3 2 1
+3.3V_LAN
@ RL1
1 2 TP_LAN_JTAG_TMS
10K_0402_5% UL1
Layout Notice : Place bead as
close UL1 as possible +3.3V_LAN LAN ANALOG SWITCH
1 2 TP_LAN_JTAG_TCK
@ RL2 10K_0402_5% CLKREQ_PCIE#4 48 13 LAN_MDIP0 EMC@ RL71 1 2 2.2_0603_5% LAN_MDIP0_L
CLKREQ_PCIE#4 <11> CLKREQ_PCIE#4 CLK_REQ_N MDI_PLUS0 LAN_MDIN0 2 2.2_0603_5% LAN_MDIN0_L
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
2 1 36 14 EMC@ RL72 1
<11> PLTRST_LAN# PE_RST_N MDI_MINUS0
@ RL4 4.7K_0402_5% 1 1 1
LAN_WAKE# LAN_MDIP1 2 2.2_0603_5% LAN_MDIP1_L
CL25
CL26
CL27
1 2 44 17 EMC@ RL73 1
@ RL70 10K_0402_5%
<11> CLK_PCIE_P4 45 PE_CLKP MDI_PLUS1 18 LAN_MDIN1 EMC@ RL74 1 2 2.2_0603_5% LAN_MDIN1_L
1: TO DOCK
<11> CLK_PCIE_N4 PE_CLKN MDI_MINUS1 DOCKED
PCIE
2 1 PCIE_PRX_C_DTX_P9
MDI
<10> PCIE_PRX_DTX_P9 38 20 LAN_MDIP2 2 2.2_0603_5% LAN_MDIP2_L 2 2 2
CL1 0.1U_0402_25V6 EMC@ RL75 1 0: TO RJ45
2 1 PCIE_PRX_C_DTX_N9 39 PETp MDI_PLUS2 21 LAN_MDIN2 EMC@ RL76 1 2 2.2_0603_5% LAN_MDIN2_L
<10> PCIE_PRX_DTX_N9
Vinafix.com CL2 0.1U_0402_25V6 PETn MDI_MINUS2

+3.3V_LAN 1 2 PCIE_PTX_C_DRX_P9 41 23 LAN_MDIP3 EMC@ RL77 1 2 2.2_0603_5% LAN_MDIP3_L
39
30
21
14
<10> PCIE_PTX_DRX_P9 PERp MDI_PLUS3
8
4
1
CL5 0.1U_0402_25V6 42 24 LAN_MDIN3 EMC@ RL78 1 2 2.2_0603_5% LAN_MDIN3_L UL4
1 2 PCIE_PTX_C_DRX_N9 PERn MDI_MINUS3
VDD
VDD
VDD
VDD
VDD
VDD
VDD
<10> PCIE_PTX_DRX_N9
10K_0402_5%
CL6 0.1U_0402_25V6 38 SW_LAN0_MDIN3
B0+
1
D VCT_LAN_R1 SW_LAN0_MDIP3 D
@ RL5
28 6 2 1 37
<8> SML0_SMBCLK SMB_CLK SVR_EN_N B0-
SMBUS
31 @ RL3 0_0402_5% LAN_MDIN3_L 2
<8> SML0_SMBDATA SMB_DATA +RSVD_VCC3P3_1 RL6 A0+ SW_LAN0_MDIN2
1 2 1 4.7K_0402_5% +3.3V_LAN 34
RSVD_VCC3P3_1 LAN_MDIP3_L 3 B1+ 33 SW_LAN0_MDIP2
2 5 A0- B1-
2
1 2 <11,32> LAN_WAKE# LAN_DISABLE#_R 3 LANWAKE_N VDD3P3_IN 29 SW_LAN0_MDIN1
<11> PM_LANPHY_ENABLE @ LAN_DISABLE_N 4 +3.3V_LAN_OUT 2 1 LAN_MDIN2_L 6 B2+ 28 SW_LAN0_MDIP1
RL7 0_0402_5% SMBus Device Address 0xC8 VDD3P3_4 +3.3V_LAN A1+ B2-
0.1U_0201_10V6K
@ RL8 0_0603_5%
<31> LAN_DISABLE#_R LAN_MDIP2_L SW_LAN0_MDIN0
10K_0402_5%
LAN CKLT0.7 15 1 7 25
VDD3P3_15 A1- B3+
1
@ RL9
CL7
LOM_ACTLED_YEL# 26 19 24 SW_LAN0_MDIP0
LOM_SPD100LED_ORG# 27 LED0 VDD3P3_19 29 B3-
LOM_SPD10LED_GRN# LED1 VDD3P3_29 +0.9V_LAN LAN_MDIN1_L SW_LAN0_ACTLED_YEL#
LED
25 9 17
LED2 2 A2+ LEDB0 18 SW_LAN0_100_ORG#
2 47 LAN_MDIP1_L 10 LEDB1 41 SW_LAN0_10_GRN#
VDD0P9_47 46 A2- LEDB2
@ T88 PAD~D TP_LAN_JTAG_TDI 32 VDD0P9_46 37 36
TP_LAN_JTAG_TDO 34 JTAG_TDI VDD0P9_37 LAN_MDIN0_L 11 C0+ 35 SW_LAN1_MDIN3 <38>
@ T89 PAD~D
JTAG_TDO A3+ C0- SW_LAN1_MDIP3 <38>
JTAG
+0.9V_LAN TP_LAN_JTAG_TMS 33 43
TP_LAN_JTAG_TCK 35 JTAG_TMS VDD0P9_43 LAN_MDIP0_L 12 32
JTAG_TCK 11 A3- C1+ 31 SW_LAN1_MDIN2 <38>
VDD0P9_11 C1- SW_LAN1_MDIP2 <38>
XTALO_R 1 2 XTALO 9 40 13 27
XTAL_OUT VDD0P9_40 <23,25,31> DOCKED SEL C2+ SW_LAN1_MDIN1 <38>
22U_0603_6.3V6M
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
@ RL34 0_0402_5% XTALI 10 22 26

XTAL_IN VDD0P9_22 C2- SW_LAN1_MDIP1 <38>
1
1 1 1 1 16
VDD0P9_16
1
+0.9V_LAN
CL9
CL10
CL11
CL8
8 LOM_ACTLED_YEL# 15 23
LAN_TEST_EN VDD0P9_8 LOM_SPD100LED_ORG# LEDA0 C3+ SW_LAN1_MDIN0 <38>
CL12
RL11 30 16 22
TEST_EN LOM_SPD10LED_GRN# 42 LEDA1 C3- SW_LAN1_MDIP0 <38>
1M_0402_5% 8/28 schematic review
2
2 2 2 2 YL1 RES_BIAS 12 7 +REGCTL_PNP10 1 2 LEDA2 19

SW_LAN1_ACTLED_YEL# <38>
2
3 1 RBIAS CTRL0P9 4.7UH_BRC2012T4R7MD_20% LL1 5 LEDC0 20
OUT IN PD LEDC1 SW_LAN1_100_ORG# <38>
27P_0402_50V8J
0.1U_0201_10V6K
10U_0603_10V6M
49 Idc_min=500mA 40
VSS_EPAD LEDC2 SW_LAN1_10_GRN# <38>
1
27P_0402_50V8J
1K_0402_5%
3.01K_0402_1%
4 2 DCR=100mohm 43
@ CL4
GND GND 1 PAD_GND
1
CL3
WGI219LM-QREF- A0_QFN48_6X6~D
2
2
CL13
RL12
RL13
Note: 25MHZ_18PF_7V25000034
+1.0V_LAN will work at 0.95V to 1.15V CL14
2
change to SA000081G0L, S IC A32 WGI219LM QREF A0 QFN 48P PHY 2
1
2
PI3L720ZHEX_TQFN42_9X3P5
C For Layout routing , change port mapping C

Place CL3, CL4 and LL1 close to UL1
+3.3V_LAN_OUT
22U_0805_6.3V6M
1
CL28
Place CL28 close to UL1.5
2
+3.3V_LAN
TL1
SW_LAN0_MDIN3 1 1:1 24 RJ45_MDIN3 LAN CKLT0.7

TD1+ TX1+
470P_0402_50V7K
0.1U_0201_10V6K
1
CL18
CL19
SW_LAN0_MDIP3 2
TD1- 23 RJ45_MDIP3
RJ45 LOM circuit
2
TX1- 2
3 22 Z2805
TDCT1 TXCT1 +3.3V_LAN:20mils
4 21 Z2807 JLOM1 CONN@
SW_LAN0_MDIN2 5 TDCT2 TXCT2 20 RJ45_MDIN2
TD2+ 1:1 TX2+ LAN_ACTLED_YEL# 1 2 LAN_ACTLED_YEL_R# 10
RL14 150_0402_5% Yellow LED-
9
Yellow LED+
SW_LAN0_MDIP2 6 19 RJ45_MDIP2 RJ45_MDIN3 8
TD2- TX2- PR4-
+3.3V_LAN RJ45_MDIP3 7
B PR4+ B
@ CL15 RJ45_MDIN1 6
PR2-
0.1U_0201_10V6K
0.1U_0201_10V6K
1 2
SW_LAN0_MDIN1 7 1:1 18 RJ45_MDIN1 RJ45_MDIN2 5
TD3+ TX3+ PR3-
1
0.1U_0201_10V6K
5
RJ45_MDIP2
CL16
CL17
4
LOM_SPD100LED_ORG# 1 PR3+ 17
P
B 4 SW_LAN0_MDIP1 8 RJ45_MDIP1 3 GND

LOM_SPD10LED_GRN# 2 O WLAN_DISBL# <31> TD3- 17 RJ45_MDIP1 PR2+ 16
A TX3- GND
G
UL2 RJ45_MDIN0 2
TC7SH08FU_SSOP5~D PR1- 15
3
9 16 Z2806 RJ45_MDIP0 1 GND

TDCT3 TXCT3 PR1+ 14
LED_10_GRN# 1 2 LED_10_GRN_R# 11 GND
10 15 Z2808 RL19 150_0402_5% Green LED-
SW_LAN0_MDIN0 11 TDCT4 1:1 TXCT4 14 RJ45_MDIN0 LED_100_ORG# 1 2 LED_100_ORG_R# 13
TD4+ TX4+ Orange LED-
0.1U_0201_10V6K
0.1U_0201_10V6K
QL1A RL20 150_0402_5%

DMN65D8LDW-7_SOT363-6 12
Green-Orange LED+
1
SW_LAN0_ACTLED_YEL#1 6 LAN_ACTLED_YEL#
CL20
CL21
SW_LAN0_MDIP0 12 13 RJ45_MDIP0 SANTA_130456-511

2
+3.3V_LAN TD4- TX4-

Link 130456-511 DONE
1 75_0402_1%
1 75_0402_1%
1 75_0402_1%
1 75_0402_1%
2
SYS_LED_MASK#
SYS_LED_MASK# <31,40>
1
MHPC_NS692417
RL29
1M_0402_5%
QL1B
DMN65D8LDW-7_SOT363-6
2
SW_LAN0_100_ORG# 4 3 LED_100_ORG#
+3.3V_LAN
RL15 2
RL16 2
RL17 2
RL18 2
5
1
SYS_LED_MASK#
RL30 GND 1 2 +GND_CHASSIS
1M_0402_5% EMC@ CL22 1500P_1808_2KV7K
A QL2A CHASSIS use 40mil trace if necessary A
2
SW_LAN0_10_GRN# 1 6 LED_10_GRN#
2
SYS_LED_MASK#
QL2B
4 3 PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT LAN
5
1.0
5 4 3 2 1
A B C D E
+3.3V_RUN +3.3V_MMI_IN
1
PJP26
2 Vinafix.com +3.3V_MMI_AUX +3.3V_MMI_IN
PAD-OPEN1x2m
1 1
0.1U_0201_10V6K
10U_0402_6.3V6M
0.1U_0201_10V6K
10U_0402_6.3V6M
+3.3V_MMI_AUX +3.3V_MMI_IN
1 1 1 1
CR43
support D3 Hot(if D3 cold PIN11,PIN27 need Add MOS on/off 3V3AUX)
CR36
CR42
CR8
1 2
@ R274 0_0603_5%
2 2 2 2
+3.3V_MMI_AUX
1 2 MEDIACARD_IRQ# 7/18 Vender suggest.
27
11
RR19 10K_0402_5% UR2
3V3_IN
3V3aux
1 12 +3.3V_RUN_CARD
<11,29,33,35> PCH_PLTRST#_AND PERST# CARD_3V3 +DV33_18
2 18 1 2
<11> CLKREQ_PCIE#5 CLK_REQ# DV33_18 CR37 1U_0402_6.3V6K
5
<11> CLK_PCIE_P5 REFCLKP
6 15 SD/MMCDAT1/RCLK- RR21 @ 1 2 0_0402_5% SD/MMCDAT1/RCLK-_R
<11> CLK_PCIE_N5 REFCLKN SP1 16 SD/MMCDAT0/RCLK+ RR22 @ 1 2 0_0402_5% SD/MMCDAT0/RCLK+_R
CR24 1 2 0.1U_0402_25V6 PCIE_PTX_C_DRX_P10 3 RTS5242 SP2 17 SD/MMCCLK EMC@ RR1 1 2 10_0402_5% SD/MMCCLK_R
<10> PCIE_PTX_DRX_P10 PCIE_PTX_C_DRX_N10 HSIP SP3 0_0402_5% SD/MMCCMD_R
@EMC@ CR23
CR25 1 2 0.1U_0402_25V6 4 19 SD/MMCCMD @ RR23 1 2
<10> PCIE_PTX_DRX_N10 HSIN SP4
5P_0402_50V8C
CR26 1 2 0.1U_0402_25V6 PCIE_PRX_C_DTX_P10 7 20 SD/MMCDAT3 @ RR17 1 2 0_0402_5% SD/MMCDAT3_R
<10> PCIE_PRX_DTX_P10 CR27 1 2 0.1U_0402_25V6 PCIE_PRX_C_DTX_N10 8 HSOP SP5 21 SD/MMCDAT2 @ RR18 1 2 0_0402_5% SD/MMCDAT2_R
<10> PCIE_PRX_DTX_N10 HSON SP6
1
29 SDWP
SP7
32
2
<8> MEDIACARD_IRQ# 31 WAKE#
SD/MMCCD# 30 MS_INS#
+1.2V_LDO SD_CD#
7/18 Vender suggest
CR13 close to UR2.10 22 SD_UHS2_D1P EMI depop location
2 SD_LN1_P 23 SD_UHS2_D1N 2
CR9 CR10 close to UR2.14 SD_LN1_M
10
14 AV12 26 SD_UHS2_D0P
DV12S SD_LN0_P 25 SD_UHS2_D0N
SD_LN0_M
4.7U_0603_6.3V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
+1.8V_RUN_CARD 13
SD_VDD2 24 +SDREG2 1 2
1 1
E-PAD
SDREG2
CR9
+RREF 9 28 CR35 1U_0402_6.3V6K
CR10
CR13
RREF GPIO SD_GPIO 2 1 +3.3V_MMI_AUX
10K_0402_5% RR16
2
2 2 RTS5242-GR_QFN32_4X4
33
1
6.2K_0402_1%
RR20
2
HOST_SD_WP# SDWP_Q SDWP STATUS
High High Write Protect(SD LOCK)

L2N7002WT1G_SC-70-3
3 High 3
Low Low Write Enable SDWP 1 3 SDWP_Q
S
JSD1
QR1 +3.3V_RUN_CARD 4
High High Write Protect(SD& FW LOCK) 14 VDD/VDD1
G
+1.8V_RUN_CARD
2
SD/MMCCMD_R 2 VDD2
Low SD/MMCCLK_R 5 CMD
<9> HOST_SD_WP# CLK
Low High Write Protect(FW LOCK)
SD/MMCCD# 18
SDWP_Q 19 CARD DETECT
WRITE PROTEC
SD/MMCDAT0/RCLK+_R 7
SD/MMCDAT1/RCLK-_R 8 DAT0/RCLK+
SD/MMCDAT2_R 9 DAT1/RCLK-
+3.3V_RUN_CARD +1.8V_RUN_CARD SD/MMCDAT3_R 1 DAT2
SD_UHS2_D0P 11 CD/DAT3
SD_UHS2_D0N 12 D0+
SD_UHS2_D1P 16 DO-
SD_UHS2_D1N D1+
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
15 20
0.1U_0201_10V6K
0.1U_0201_10V6K
D1- GND1 21
2 2 GND2
CR40
3 22
CR39
CR41
VSS1 GND3
CR38
6 23
10 VSS2 GND4 24
1
1 1 13 VSS3 GND5 25
17 VSS4 GND6 26
VSS5 GND7
T-SOL_156-2000302608_NR
CONN@
CR38,CR39 near JSD1.4 CR40,CR41 near JSD1.14
4 4
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Card Reader
A B C D E
5 4 3 2 1
+3.3V_WWAN
NGFF slot A Key A
NGFF slot B Key B 80148-3221&80148-4221 Footprint the same
+3.3V_WLAN
1 2 WWAN_PWR_EN
JNGFF1 CONN@
@ RZ43 0_0402_5%
+3.3V_WWAN 1 2
3 1 2 4
<10> USB20_P8 3 4
JNGFF2 CONN@ 5 6
<10> USB20_N8 5 6
1 2 7
<31> SLOT2_CONFIG_3 1 2 7
3 4
5 3 4 6 WWAN_PWR_EN
Vinafix.com
7 5 6 8 WWAN_RADIO_DIS#_R
<10> USB20_P10 7 8
9 10 8
<10> USB20_N10 9 10 8
11 9 10
11 1 2 SW1_DP1_N3_C 11 9 10 12 SW1_DP1_AUXN_C 2 1
<23> SW1_DP1_N3 SW1_DP1_P3_C 11 12 SW1_DP1_AUXP_C SW1_DP1_AUXN <23>
CV145 1 2 0.1U_0402_25V6 13 14 0.1U_0402_25V6 2 1CV150
D <23> SW1_DP1_P3 13 14 SW1_DP1_AUXP <23>
CV146 0.1U_0402_25V6 15 16 0.1U_0402_25V6 CV149 D
12 1 2 SW1_DP1_N2_C 17 15 16 18 SW1_DP1_N1_C 2 1
12 <23> SW1_DP1_N2 SW1_DP1_P2_C 17 18 SW1_DP1_P1_C0.1U_0402_25V6 SW1_DP1_N1 <23>
13 14 CV148 1 2 0.1U_0402_25V6 19 20 2 1CV152
<31> SLOT2_CONFIG_0 13 14 <23> SW1_DP1_P2 19 20 SW1_DP1_P1 <23>
15 16 CV147 0.1U_0402_25V6 21 22 0.1U_0402_25V6 CV153
<31> WWAN_WAKE# 15 16 HW_GPS_DISABLE#_R 21 22 SW1_DP1_N0_C
17 18 23 24 2 1
17 18 <23> SW1_DP1_HPD 23 24 SW1_DP1_P0_C0.1U_0402_25V6 SW1_DP1_N0 <23>
19 20 25 26 2 1CV156
USB3_PRX_L_DTX_N5 19 20 UIM_RESET PCIE_PTX_C_DRX_P5 25 26 SW1_DP1_P0 <23>
21 22 CZ13 1 2 0.1U_0402_25V6 27 28 0.1U_0402_25V6 CV157
USB3_PRX_L_DTX_P5 21 22 UIM_CLK <10> PCIE_PTX_DRX_P5 PCIE_PTX_C_DRX_N5 27 28
23 24 CZ14 1 2 0.1U_0402_25V6 29 30
23 24 UIM_DATA <10> PCIE_PTX_DRX_N5 29 30 PCH_CL_RST1# <8>
25 26 31 32
USB3_PTX_L_DRX_N5 25 26 31 32 PCH_CL_DATA1 <8>
27 28 33 34
USB3_PTX_L_DRX_P5 29 27 28 30
+SIM_PWR WLAN <10> PCIE_PRX_DTX_P5 35 33 34 36
PCH_CL_CLK1 <8>
31 29 30 32 ISH_I2C2_SCL_R 2 1 <10> PCIE_PRX_DTX_N5 37 35 36 38
31 32 ISH_I2C2_SDA_R ISH_I2C2_SCL <9> 37 38
33 34 @ RZ76 2 1
0_0402_5% 39 40
<10> PCIE_PRX_DTX_N3 33 34 ISH_I2C2_SDA <9> <11> CLK_PCIE_P1 39 40 WIGIG_32KHZ
35 36 @ RZ77 0_0402_5% 41 42 @ RZ56 2 1 0_0402_5%
<10> PCIE_PRX_DTX_P3 35 36 <11> CLK_PCIE_N1 41 42 PCH_PLTRST#_AND SUSCLK <11,35>
37 38 43 44
PCIE_PTX_C_DRX_N3 37 38 43 44 BT_RADIO_DIS#_R PCH_PLTRST#_AND <11,28,33,35>
CZ58 1 2 0.1U_0402_25V6 39 40
9/24: Reserve for embedded location ,refer Intel PDG 0.9 45 46
<10> PCIE_PTX_DRX_N3 PCIE_PTX_C_DRX_P3 39 40 PCH_PLTRST#_AND <11> CLKREQ_PCIE#1 PCIE_WAKE# 45 46 WLAN_WIGIG60GHZ_DIS#_R
CZ59 1 2 0.1U_0402_25V6 41 42 47 48
<10> PCIE_PTX_DRX_P3 41 42 <31,35> PCIE_WAKE# 47 48 ISH_UART0_RXD_R
43 44 49 50 2 1
43 44 PCIE_WAKE# CLKREQ_PCIE#0 <11> PCIE_PTX_C_DRX_P6 49 50 ISH_UART0_TXD_R @ RZ78 2 ISH_UART0_RXD <9>
45 46 CZ21 1 2 0.1U_0402_25V6 51 52 1 0_0402_5%
<11> CLK_PCIE_N0 45 46 <10> PCIE_PTX_DRX_P6 PCIE_PTX_C_DRX_N6 51 52 ISH_UART0_CTS#_R @ RZ79 2 ISH_UART0_TXD <9>
47 48 CZ22 1 2 0.1U_0402_25V6 53 54 1 0_0402_5%
<11> CLK_PCIE_P0 47 48 <10> PCIE_PTX_DRX_N6 53 54 ISH_UART0_RTS#_R @ RZ80 2 ISH_UART0_CTS# <9>
49 50 55 56 1 0_0402_5%
49 50 55 56 PCH_PLTRST#_AND @ RZ81 ISH_UART0_RTS# <9>
51 52 57 58 0_0402_5%
53 51 52 54 <10> PCIE_PRX_DTX_P6 59 57 58 60
55 53 54 56 WIGI <10> PCIE_PRX_DTX_N6 61 59 60 62 PCIE_WAKE# CLKREQ_PCIE#2 <11>
57 55 56 58 SIM_DET 63 61 62 64
57 58 <11> CLK_PCIE_P2 63 64
59 60 65 66
61 59 60 62
<11> CLK_PCIE_N2
67 65 66 9/24: Reserve for embedded location ,refer Intel PDG 0.9
<31> SLOT2_CONFIG_1 61 62 67
63 64
65 63 64 66
67 65 66 69 68
<31> SLOT2_CONFIG_2 67 GND GND
69 68
GND GND
BELLW_80148-4221
BELLW_80149-4221
BELLW_80148-4221 LINK DONE

+3.3V_WWAN
80149-4221 LINK DONE
C C
.047U_0402_16V7K
.047U_0402_16V7K
33P_0402_50V8J
33P_0402_50V8J
150U_B2_6.3VM_R35M
47P_0402_50V8J
1
22U_0603_6.3V6M
1
1
+
@ CZ105
@CZ57
CZ51
CZ52
CZ53
CZ54
CZ55
2
2 2
1 2 WWAN_RADIO_DIS#_R +3.3V_WLAN
<31> WWAN_RADIO_DIS#
DZ5
RB751S40T1G_SOD523-2
0.1U_0201_10V6K
.047U_0402_16V7K
.047U_0402_16V7K
0.1U_0201_10V6K
0.1U_0201_10V6K
4.7U_0603_6.3V6K
WLAN_WIGIG60GHZ_DIS#_R
47P_0402_50V8J
1 2
<31> WLAN_WIGIG60GHZ_DIS#
1 1 1 1
1
1 2 HW_GPS_DISABLE#_R DZ1 @
@CZ106
<31> HW_GPS_DISABLE#
CZ15
CZ20
CZ16
CZ17
CZ18
CZ19
DZ6
2
RB751S40T1G_SOD523-2 2 2 2 2
1 2 USB3_PRX_L_DTX_P5 1 2 BT_RADIO_DIS#_R
<10> USB3_PRX_DTX_P5 @ <31> BT_RADIO_DIS#
RI27 0_0402_5%
DZ2
1 2 USB3_PRX_L_DTX_N5 RB751S40T1G_SOD523-2
<10> USB3_PRX_DTX_N5 @ RI28 0_0402_5%
Power Rating TBD
Primary Power Aux Power
PWR Voltage
Rail Tolerance
Peak Normal Normal
2 1 USB3_PTX_C_DRX_P5 1 2 USB3_PTX_L_DRX_P5 +3.3V

<10> USB3_PTX_DRX_P5 @
CI30 0.1U_0402_25V6 RI29 0_0402_5%
2 1 USB3_PTX_C_DRX_N5 1 2 USB3_PTX_L_DRX_N5
<10> USB3_PTX_DRX_N5 @
CI29 0.1U_0402_25V6 RI30 0_0402_5%
B B
+SIM_PWR
SIM Card Push-Push
JSIM1 CONN@
1U_0402_6.3V6K
1 5
UIM_RESET 2 VCC GND 6
RST VPP
1
UIM_CLK 3 7 UIM_DATA
CLK I/O
C263
4 8
RFU1 RFU2
2
9 SIM_DET_R 1 2 SIM_DET
DTSW @ RI31 0_0402_5%
10
11 GND 14
12 GND GND 15
13 GND GND 16
UIM_RESET GND GND
UIM_CLK T-SOL_5-991503004000-6
UIM_DATA
T-SOL_5-991503004000-6 LINK DONE

33P_0402_50V8J
@EMC@ CZ65
33P_0402_50V8J
@EMC@ CZ66
33P_0402_50V8J
@EMC@ CZ67
A A
1
1
2
For RF team request PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
NGFF Card
5 4 3 2 1
2 1
+5V_RUN_AUDIO +1.5V_RUN +3.3V_RUN_AUDIO +5V_RUN_AUDIO
1W x 1ch, 4ohm (Transducer spec is 8Ohm/0.5Watt per unit, there are two transducer units in one speaker box.)
1
0_0805_5%
place close to pin27
Internal Speakers Header
0_0603_5%
@ RA3
0_0603_5%
@ RA4
@ RA39
LA5
+VDDA_AVDD1 1 2
0.1U_0201_10V6K
10U_0603_10V6M
40 mils trace keep 20 mil spacing +3.3V_RUN_AUDIO BLM15PX600SN1D_2P
Vinafix.com
JSPK1 CA11 close to pin9 1
2
1
INT_SPK_L+ INT_SPKR_L+
CA8
EMC@ LA6 1 2 BLM15PX330SN1D_2P 1 CA10 close to pin3 place close to pin40
1
CA9
INT_SPK_L- EMC@ LA7 1 2 BLM15PX330SN1D_2P INT_SPKR_L- 2 +1.5V_RUN_AUDIO
INT_SPK_R+ INT_SPKR_R+ 2
4.7U_0603_6.3V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
EMC@ LA8 1 2 BLM15PX330SN1D_2P 3
4.7U_0603_6.3V6K
2
INT_SPK_R- EMC@ LA9 1 2 BLM15PX330SN1D_2P INT_SPKR_R- 4 3 2
4 1 1 1 place close to pin38
CA10
CA11
CA50
L03ESDL5V0CC3-2_SOT23-3
CA16
0.1U_0201_10V6K
5
4.7U_0603_6.3V6K
GND1 place close to pin41 place close to pin46
3
6 1 1
UA1
2
GND2 2 2 2
@EMC@
@EMC@
CA17
0.1U_0201_10V6K
0.1U_0201_10V6K
10U_0603_10V6M
10U_0603_10V6M
CA18
ACES_50271-0040N-001 1 27 1 1 1 1
<31> EN_I2S_NB_CODEC# I2S I/F Float AVDD1
@EMC@ CA22
@EMC@ CA23
@EMC@ CA19
@EMC@ CA24
CA45
CA47
CONN@ 40
AVDD2 2 2
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
CA46
CA48
1
3 38 +VDDA_PVDD
DVDD_IO CPVDD 2 2 2 2
DA6
DA7
41
PVDD1 46 +5V_RUN_PVDD
2
9 PVDD2
1
DVDD 13 AUD_SENSE_A
HP/MIC1 JD(JD1) 14 AUD_SENSE_B
I2S_IN/I2S_OUT JD(JD2) 22 1 2
HDA_BIT_CLK_R TV Mode/LINE1-JD (JD3) +3.3V_RUN_AUDIO
6 @ RA45 0_0402_5%
<12> HDA_BIT_CLK_R BCLK
HDA_SDOUT_R 5 28 RING2 +VREFOUT
<12> HDA_SDOUT_R SDATA-OUT LINE1-L(PORT-C-L)/RING2
Close to UA1 29 SLEEVE SLEEVE/RING2 please keep 40 mils trace width
10 LINE1-R(PORT-C-R)/SLEEVE 23 RING2 1 2
B <12> HDA_SYNC_R SYNC LINE1-VREFO +VREFOUT B
Place RA9 close to codec 1 2 2.2K_0402_5% RA5
1 2 HDA_SDIN0_R 8 31 CA25 10U_0603_10V6M SLEEVE 1 2
<12> HDA_SDIN0 RA9 33_0402_5% SDATA-IN MIC-CAP 33 AUD_OUT_L 1 2 AUD_HP_OUT_L 2.2K_0402_5% RA6
HDA_RST#_R 11 HPOUT-L(PORT-A-L) 32 AUD_OUT_R RA7 1 2 24.9_0402_1% AUD_HP_OUT_R
<12> HDA_RST#_R RESET# HPOUT-R(PORT-A-R) RA8 24.9_0402_1% AUD_HP_OUT_L/ AUD_HP_OUT_Rplease keep 15 mils trace width
42 INT_SPK_L+
SPK-OUT-L+ 43 INT_SPK_L-
1 2 I2S_MCLK 15 SPK-OUT-L- +VREFOUT
<38> DAI_12MHZ# EMC@ RA30 22_0402_5% I2S_MCLK 45 INT_SPK_R+
Close to UA1 pin6 2 I2S_BCLK SPK-OUT-R+ INT_SPK_R-
1U_0603_10V6K
1 16 44 2 1 1 2
<38> DAI_BCLK# I2S_SCLK SPK-OUT-R- SPKR <12>
@
EMC@ RA31 22_0402_5% CA27 0.1U_0402_25V6 RA12 1K_0402_5%
HDA_BIT_CLK_R 2 I2S_DO AUD_PC_BEEP
CA26
1 Place RA32 close to codec 17 12 2 1 1 2
<38> DAI_DO# I2S_DOUT PCBEEP BEEP <32>
@EMC@ RA17
RA32 33_0402_5% CA28 0.1U_0402_25V6 RA13 1K_0402_5%
2
18
<38> DAI_LRCK# I2S_LRCK
1
DMIC_CLK_CODEC DMIC_CLK0
33_0402_5%
2 1 2
24 GPIO0/DMIC-CLK 4 EMC@ RA14 33_0402_5% DMIC_CLK0 <26>
<38> DAI_DI I2S_DIN GPIO1/DMIC-DATA12
47
SPDIF-OUT/DMIC-DATA34/GPIO2 DMIC0 <26>
2
BCLK: Audio serial data bus bit clock input/output MIC1_L 19

MIC1-L(PORT-B-L)
10P_0402_50V8J
@EMC@ CA33
LRCK: Audio serial data bus word clock input/output MIC1_R 20

MIC1-R(PORT-B-R) Place CA29 close to Codec
1
35
CBN
AUD_NB_MUTE# 48 36 2 1
<31> AUD_NB_MUTE#
2
EAPD+PD CBP
1U_0603_10V6K
CA29 1U_0603_10V6K
34 2 1
CPVEE
1
1 2 21 25 CA49 2 1 1U_0603_10V6K
+3.3V_RUN_AUDIO LDO1-CAP VREF
CA31
RA18 10K_0402_5% 39 CA35 2.2U_0402_6.3V6M
7 LDO2-CAP 30 +MIC1_VREF_OUT
2
LDO3-CAP MIC1-VREFO
1
100K_0402_5%
26
AVSS1
1
4.7U_0603_6.3V6K
CA51
4.7U_0603_6.3V6K
CA52
4.7U_0603_6.3V6K
CA53
RA44
49 37
GND AVSS2
Verb table configures as 1 JD mode with
internal 47K pull high to save external rBOM. ALC3235-CG_MQFN48_6X6
2
2
DMIC_CLK0
AUD_SENSE_A
@EMC@
Place closely to Pin 13.
22P_0402_50V8J
1
CA54
2
2
2
L2N7002WT1G_SC-70-3
DA4
DA5
1
D
QA1
2 8/4 place close to UA1 pin2

AUD_HP_NB_SENSE <31>
2 1
2 1
0.1U_0402_25V6
4.7K_0402_5%
4.7K_0402_5%
G
1
S
3
CA41
@
RA24
RA25
place at AGND and DGND plane
Add for solve
2
pop noise and

1 2
detect issue HP-Out-Right Nokia-MIC
1
@ RA35 0_0402_5% CA43
MIC1_L 1 2 AUD_HP_OUT_L
HP-Out-Left iPhone-MIC
1 2 CA44 4.7U_0603_6.3V6K
AUD_SENSE_B 1 2 @ RA36 0_0402_5% MIC1_R 1 2 AUD_HP_OUT_R
+3.3V_RUN_AUDIO
RA38 100K_0402_5% PJP6
Place closely to Pin 14 for DOCK only 1 2 4.7U_0603_6.3V6K
1 2
1
1
100K_0402_5%
200K_0402_5%
@ RA37 0_0402_5% PAD-OPEN1x1m

+3.3V_RUN_AUDIO +3.3V_RUN_AUDIO +3.3V_RUN_AUDIO
RA28
RA27
680P_0402_50V7K
@EMC@ CA13
1
100K_0402_5%
Global Headset
1
1
100K_0402_5%
Universal Jack
2
2
RA29
2
RA26
RA1
10K_0402_5%
6
3
2
2
JHP1
7
2 5 RING2 EMC@ LA10 1 2 BLM15PX330SN1D_2P RING2_R 4 GND
<31> DOCK_HP_DET DOCK_MIC_DET <31> AUD_HP_OUT_L EMC@ LA2 1 AUD_HP_OUT_L1 #4 G/M
QA3A QA3B 2 BLM15BD601SN1D_2P 1 Normal
DMN65D8LDW-7_SOT363-6 DMN65D8LDW-7_SOT363-6 #1 L/R
A
Open A
1
SLEEVE 5
#5
PJP9 +RTC_CELL AUD_HP_NB_SENSE 6

Power sequence +5V_RUN_AUDIO(501us) > +3.3V_RUN_AUDIO(1204 us) > +1.5V_RUN
+5V_RUN 1 2 +5V_RUN_AUDIO
#6 AGND
AUD_HP_OUT_R EMC@ LA3 1 2 BLM15BD601SN1D_2P AUD_HP_OUT_R1 2
+5V_RUN_AUDIO SLEEVE EMC@ LA11 1 2 BLM15PX330SN1D_2P SLEEVE_R 3 #2 R/L
PAD-OPEN1x3m 2.5A #3 M/G
1
100K_0402_5%
Reserve for support D3 cold SINGA_2SJ3095-022111F

PAD-OPEN1x3m
2
RA21
EMC@ CA1
@EMC@ CA2
@EMC@ CA3
EMC@ CA4
PJP10 EMC@ EMC@ EMC@ CONN@
3
RA2
1 2 DA1 DA2 DA3
+3.3V_RUN +3.3V_RUN_AUDIO
1
680P_0402_50V7K
220P_0402_50V7K
220P_0402_50V7K
680P_0402_50V7K
680P_0402_50V7K
@EMC@ CA12
PJP31
1 1 1 1 1
2
+5V_RUN
AZ5123-02S.R7G_SOT23-3
PAD-OPEN1x1m
0.5A 5
@
QA2B
UZ5 @
1
+5V_RUN_AUDIO_UZ5 2 2 2 2 2
100K_0402_5%
1 14 1 2
4
2
2 VIN1 VOUT1 13 @ CZ89 0.1U_0201_10V6K
VIN1 VOUT1
3 12 1 2 2 AUD_NB_MUTE#
<9> AUD_PWR_EN
1
ON1 CT1
QA2A
@ CZ90 220P_0402_50V7K
4 11
+5V_ALW
1
VBIAS GND
5 10 1 2
ON2 CT2 @ CZ91 1000P_0402_50V7K
6 9 @ PJP30
+3.3V_RUN
7 VIN2
VIN2
VOUT2
VOUT2
8 +3.3V_RUN_AUDIO_UZ5 1 2
+3.3V_RUN_AUDIO DELL CONFIDENTIAL/PROPRIETARY
GPAD
15
PAD-OPEN1x1m Realtek feedback
EM5209VF_SON14_2X3 1 2 Prevent the Noise from Combo Jack PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
@ CZ92 0.1U_0201_10V6K while system entry into S3 / S4 /S5 TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Codec ALC3235
2 1
5 4 3 2 1
+3.3V_ALW
+3.3V_ALW
+3.3V_ALW +3.3V_ALW_UE1
PCIE_WAKE#_R 2 1
PJP14 10K_0402_5% RE35
1 2
RPE9 WWAN_WAKE# 2 1
USB_PWR_SHR_VBUS_EN
10U_0603_10V6M
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
8 1 PAD-OPEN1x1m 10K_0402_5% RE38
1
7 2 USB_PWR_EN1# 1 1 1 1 1
USB_PWR_EN2#
CE1
CE2
CE3
CE4
CE5
CE6
6 3 PD_ACE_DET# 2 1
5 4 USB_PWR_SHR_EN# <31,36>
Vinafix.com 100K_0402_5% RE310
2
100K_0804_8P4R_5% 2 2 2 2 2 PROCHOT_GATE 2 1
100K_0402_5% @ RE311
D RPE12 D
8 1 SLICE_BAT_PRES#
A17
B30
A43
A54
7 2 WLAN_WIGIG60GHZ_DIS#
B5
6 3 DOCK_SMB_ALERT# UE1
5 4 WWAN_RADIO_DIS# +3.3V_RUN
VCC1
VCC1
VCC1
VCC1
VCC1
A23
100K_0804_8P4R_5% B52 GPIOI0 B63 RPE8
A49 GPIOA0 GPIOI1 A60 PD_ACE_DET# LPC_LDRQ1# 1 8
B53 GPIOA1 GPIOI2/TACH0 A61 PROCHOT_GATE D_DLDRQ1# 2 7
<27> LAN_DISABLE#_R GPIOA2 GPIOI3
RPE11 A50 B65 D_SERIRQ 3 6
<43,51,52> AC_DIS GPIOA3 GPIOI4
8 1 SLOT2_CONFIG_3 LID_CL_SIO# B54 A62 D_CLKRUN# 4 5
7 2 SLOT2_CONFIG_0 DOCK_SMB_ALERT# A51 GPIOA4 GPIOI5 B66 USH_RST# <33>
<38,43> DOCK_SMB_ALERT# GPIOA5 GPIOI6
6 3 SLOT2_CONFIG_2 B55 A63 100K_0804_8P4R_5%
5 4 SLOT2_CONFIG_1 A52 GPIOA6 GPIOI7 DOCK_AC_OFF_EC <52>
GPIOA7 B67
100K_0804_8P4R_5% USB_PWR_EN2# A33 GPIOJ0 A64 AUX_EN_WOWL <41>
<37> USB_PWR_EN2# GPIOB0 GPIOJ1/TACH1 ME_FWP_EC <12>
B36 A5
1 2 BT_RADIO_DIS# <30> EN_I2S_NB_CODEC# A34 GPIOB1 GPIOJ2/TACH2 B6
<33> USH_PWR_STATE# GPOC2 GPIOJ3 PCIE_WAKE# <29,35>
RE11 100K_0402_5% B37 A6
HW_GPS_DISABLE# <52> EN_DOCK_PWR_BAR HW_GPS_DISABLE# GPOC3 GPIOJ4 GPIO_PSID_SELECT <43>
1 2 A35 B7
<29> HW_GPS_DISABLE# GPOC4 GPIOJ5
RE12 100K_0402_5% B38 A7
AC_DIS Reserve <26> PANEL_BKEN_EC LCD_TST GPOC5 GPIOJ6 DOCK_HP_DET <30>
1 2 A36 B8
<26> LCD_TST GPOC6/TACH4 GPIOJ7 DOCK_MIC_DET <30> PCIE_WAKE#_R 2
@ RE83 100K_0402_5% A37 1 1 2 PCH_PCIE_WAKE# <11,32>
<43> PSID_DISABLE# B40 GPIOC7 A8 @ RE275 0_0402_5% 0_0402_5% @ RE274
AR_SMBUS_ALERT# GPIOD0 GPIOK0 USB_PWR_SHR_EN# <31,36>
1 2 A38 B9
<23,25,27> DOCKED GPIOC1 GPIOK1/TACH3 PCIE_WAKE#_R MASK_SATA_LED# <40>
RE309 10K_0402_5% B41 B10
<38,52> DOCK_DET# GPIOC0 GPIOK2
A39 A10 Stuff RE275 and no stuff RE274 keep E5 design
<30> AUD_NB_MUTE# GPIOB7 GPIOK3 LED_SATA_DIAG_OUT# <40> Stuff RE274 and no stuff RE275 to save two GPIOs on EC(PCH_PCIE_WAKE# should be output with OD)
B42 B11
<41> 3.3V_WWAN_EN A40 GPIOB6 GPIOK4 A11
<26> LCD_VCC_TEST_EN WWAN_WAKE# GPIOB5 GPIOK5 SLOT2_CONFIG_0
B43 B12 SLOT2_CONFIG_0 <29>
<29> WWAN_WAKE# A41 GPIOB4 GPIOK6 A12
<30> AUD_HP_NB_SENSE USB_PWR_EN1# GPIOB3 GPIOK7
B44
<37> USB_PWR_EN1# GPIOB2 CPU_ID
B60
+3.3V_RUN GPIOL0/PWM7 A57 SLICE_BAT_ON 2 1
B32 GPIOL1/PWM8 B64 RE17 100K_0402_5%
C SLICE_BAT_ON A31 GPIOD1 GPIOL2/PWM0 B68 C
<52> SLICE_BAT_ON GPIOD2 GPIOL3/PWM1 WLAN_DISBL# <27>
1 2 USH_DET# SLICE_BAT_PRES# B33 A9
RC281 10K_0402_5% <38,43,52> SLICE_BAT_PRES# GPIOD4 B15 GPIOD3 GPIOL4/PWM3 B1
@ T97 PAD~D GPIOD4 GPIOL5/PWM2
Reserve @ T99 PAD~D GPIOD5 A15 A18 SLOT2_CONFIG_1
GPIOD5 GPIOL6 SLOT2_CONFIG_1 <29>
Reserve B16 A44 SLOT2_CONFIG_2
GPIOD6 GPIOL7/PWM5 SLOT2_CONFIG_2 <29>
A16
<33> USH_DET# GPIOD7 SLOT2_CONFIG_3
B34
SYS_LED_MASK# GPIOM1 SLOT2_CONFIG_3 <29>
1 2 B39
RE21 10K_0402_5% WLAN_WIGIG60GHZ_DIS# A1 GPIOM3/PWM4 B51
<29> WLAN_WIGIG60GHZ_DIS# GPIOE0/RXD GPIOM4/PWM6 DIS_BAT_PROCHOT# <52>
<32> EC5048_TX B2
GPIOE2 A2 GPIOE1/TXD
@ T98 PAD~D GPIOE2/RTS#
1 2 LCD_TST Reserve B3 A27
GPIOE3/DSR# LAD0 LPC_LAD0 <8,32>
RE20 100K_0402_5% A3 A26
GPIOE4/CTS# LAD1 LPC_LAD1 <8,32>
B45 B26
GPIOE5/DTR# LAD2 LPC_LAD2 <8,32>
A42 B25
GPIOE6/RI# LAD3 LPC_LAD3 <8,32>
B4 A21
GPIOE7/DCD# LFRAME# LPC_LFRAME# <8,32>
B22
LRESET# CLK_PCI_5048 PLTRST_5048# <11>
A28 CLK_PCI_5048 <8>
A59 PCICLK B20 CLKRUN#
GPIOF0 CLKRUN# CLKRUN# <8,32>
B62
<33> BCM5882_ALERT# AR_SMBUS_ALERT# A58 GPIOF1 A22 LPC_LDRQ1#
B61 GPIOF2 LDRQ1# B21
GPIOF3/TACH8 SER_IRQ IRQ_SERIRQ <8,32>
A56 A32
VGA_ID B59 GPIOF4/TACH7 14.318MHZ/GPIOM0 B35
GPIOF5 CLK32/GPIOM2 EC_32KHZ_ECE5048 <32>
A55
+3.3V_ALW B58 GPIOF6
GPIOF7 B29
DLAD0 D_LAD0 <38>
B28
DLAD1 D_LAD1 <38>
B47 A25
VGA_ID GPIOG0/TACH5 DLAD2 D_LAD2 <38>
1 2 A45 A24
SYS_LED_MASK# GPIOG1 DLAD3 D_LAD3 <38>
100K_0402_5% RE84 <27,40> SYS_LED_MASK# B48 B23
VGA_ID GPIOG2 DLFRAME# D_CLKRUN# D_LFRAME# <38>
1 2 A46 A19
GPIOG3 DCLKRUN# D_DLDRQ1# D_CLKRUN# <38>
@ 100K_0402_5% RE85 B49 B24
GPIOG4 DLDRQ1# D_SERIRQ D_DLDRQ1# <38>
A47 A20
USB_PWR_SHR_VBUS_EN GPIOG5 DSER_IRQ D_SERIRQ <38>
B B50 B
<36> USB_PWR_SHR_VBUS_EN A48 GPIOG6
GPIOG7/TACH6 A29
BC_INT# BC_INT#_ECE5048 <32>
VGA_ID0 B31
BC_DAT BC_DAT_ECE5048 <32>
B13 A30
BT_RADIO_DIS# GPIOH0 BC_CLK BC_CLK_ECE5048 <32>
Discrete 0 A13
<29> BT_RADIO_DIS# WWAN_RADIO_DIS# GPIOH1
A53 +3.3V_ALW
<29> WWAN_RADIO_DIS# SYSOPT1/GPIOH2
UMA 1 B57 A4 RUNPWROK
B14 SYSOPT0/GPIOH3 PWRGD RUNPWROK <14,32>
A14 GPIOH4 B56
<11,41> SIO_SLP_WLAN# GPIOH5 OUT65
1
100K_0402_5%
B17
B18 GPIOH6
+3.3V_ALW GPIOH7
RE25
B19 1 2
TEST_PIN RE24 10K_0402_5% +CAP_LDO trace width 20 mils
B46 +CAP_LDO
2
CAP_LDO
4.7U_0603_6.3V6K
CPU_ID 1 2 B27
VSS
1
@ 100K_0402_5% RE298 C1 LID_CL_SIO# 2 1
CPU_ID EP LID_CL# <40>
CE7
1 2 RE26 10_0402_5%
100K_0402_5% RE299 DB Version 0.4 CLK_PCI_5048
@EMC@ RE27
.047U_0402_16V7K
ECE5048-LZY_DQFN132_11X11~D
1
33_0402_5%
CE8
CPU_ID0
2
U CPU 0
@EMC@ CE9
33P_0402_50V8J
H_CPU 1
1
2
EMI depop location
A A
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT ECE5048
5 4 3 2 1
5 4 3 2 1
+3.3V_ALW +RTC_CELL
1 2 +RTC_CELL_VBAT +RTC_CELL
0.1U_0201_10V6K
@ RE32 0_0402_5% +RTC_CELL
1
1
BC_DAT_ECE5048
CE11
100K_0402_5%
1 2
1
100K_0402_5%
RE36 100K_0402_5%
+3.3V_RUN
RE31
RE62
@ CE10 @ CE44
RPE13 2 1 2 1 2
1 8 PBAT_SMBCLK +3.3V_ALW_UE2
2
2 7 PBAT_SMBDAT 1U_0402_6.3V6K 1U_0402_6.3V6K
2
3 6 GPU_SMBCLK Reserve
GPU_SMBDAT POWER_SW_IN# DOCK_PWR_SW#
0.1U_0201_10V6K
1U_0402_6.3V6K
4 5 Reserve 1 2 1 2
POWER_SW#_MB <11,40> DOCK_PWR_BTN# <38> 2 1
1 RE33 10K_0402_5% RE42 10K_0402_5%
1
CE13
1U_0402_6.3V6K
1U_0402_6.3V6K
2.2K_0804_8P4R_5% 0_0402_5% @ RE304
1
CE14
+3.3V_ALW_UE2
CE12
CE45
2
2 +3.3V_ALW
Vinafix.com
2
@ CE53
1 2 FAN1_PWM 1 2 UE4 +3.3V_ALW
RE48 10K_0402_5%
5
FAN1_TACH
0.1U_0201_10V6K
1 2 0.1U_0402_25V6 1 5
IMVP_VR_ON_EC NC VCC
1U_0402_6.3V6K
RE51 10K_0402_5% 1 1
P
B
1
IMVP_VR_ON
CE20
D 4 2 D
SIO_SLP_S3# O A VCCST_PWRGD
CE15
UE2 2 4
A Y
G
UE3 3
2
2 B64 A10 PANEL_ID TC7SH08FU_SSOP5~D GND
3
VBAT GPIO021/RC_ID1 B10 BOARD_ID SN74AUP1G07DCKR SC70 5P
GPIO020/RC_ID2 B8 mCARD_PCIE#_SATA
+3.3V_ALW +3.3V_ALW_UE2 GPIO014/GPTP-IN7/RC_ID3 PAD~D T131 @
A22 B27
H_VTR GPIO025/UART_CLK B44 HOST_DEBUG_TX LAN_WAKE# <11,27>
PJP15 GPIO120/UART_TX/V2P_COUT_HI1 B46 IMVP_VR_ON <49>
1 2 A58 GPIO124/GPTP-OUT5/UART_RX/V2P_COUT_LO1 B26 RUNPWROK PCH_PCIE_WAKE# <11,31>
VTR_ADC VCC_PWRGD A25 EN_INVPWR RUNPWROK <14,31>
GPIO060/KBRST/BCM_B_INT# EN_INVPWR <26>
10U_0603_10V6M
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
PAD-OPEN1x1m B36
GPIO101/ECGP_SCLK SIO_SLP_S4# <11,17,45,54>
@ CE16
1 1 1 1 1 1 B3 B37
VTR GPIO103/ECGP_MISO SIO_SLP_LAN# <11,41>
1
EN_INVPWR SIO_SLP_S3#
CE17
CE22
CE18
CE23
CE19
1 2 A11 B38 1 2
VTR GPIO105/ECGP_MOSI PCH_ALW_ON
CE21
RE55 100K_0402_5% A26 A34 0_0402_5% @ RE280
1 2 RESET_OUT# B35 VTR GPIO102/BCM_C_INT# A35 PCH_ALW_ON <41>
SIO_SLP_S3# <11,17,48>
2
RE56 10K_0402_5% 2 2 2 2 2 2 A41 VTR GPIO104/SLP_S0# A36
A52 VTR GPIO106 A40 MSDATA PCH_DPWROK <11>
VTR GPIO116/MSDATA/V2P_COUT_LO/TAP_SEL_STRAP B43 MSCLK RUN_ON_EC 2 1
GPIO117/MSCLK/V2P_COUT_HI A45 PCH_RSMRST# @ RUN_ON <32,41,47>
0_0402_5% RE292
GPIO127/A20M B65 FWP# PCH_RSMRST# <39>
A5 nFWP +3.3V_ALW
<8> SML1_SMBDATA GPIO007/I2C1D_DATA/PS2_CLK0B/I2C3A_DATA
+5V_RUN B6 @ CE52
<8> SML1_SMBCLK A37 GPIO010/I2C1D_CLK/PS2_DAT0B/I2C3A_CLK/GANG_DATA0 B57 1 2
RPE2
1 8 CLK_KBD <39> CLK_TP_SIO B40 GPIO110/PS2_CLK2/GPTP-IN6 GPIO156/LED1/GANG_DATA1 B1 BREATH_LED# <38,40>
2 7 DAT_KBD <39> DAT_TP_SIO CLK_KBD A38 GPIO111/PS2_DAT2/GPTP-OUT6 GPIO157/LED0 A55 BAT1_LED# <40>
for no-dock : A38 use LCD_TST 0.1U_0402_25V6
<38> CLK_KBD GPIO112/PS2_CLK1A GPIO153/LED2/GANG_DATA4 BAT2_LED# <40>
5
3 6 CLK_MSE for no-dock : B41 use Free DAT_KBD B41 A1 IMVP_VR_ON_EC
4 5 DAT_MSE <38> DAT_KBD CLK_MSE A39 GPIO113/PS2_DAT1A GPIO027/GPTP-OUT1 B28 1
for no-dock : A39 use SLP_ME_CSW_DEV# 8/11
P
<38> CLK_MSE DAT_MSE B42 GPIO114/PS2_CLK0A GPIO026/GPTP-IN1 B2 SIO_SLP_A# <8,11> B 4
for no-dock :B42 use Free <38> DAT_MSE EC_32KHZ_ECE5048 <31> for no-dock : B2 use Free
4.7K_8P4R_5% PBAT_SMBDAT B59 GPIO115/PS2_DAT0A GPIO001/ECSPI_CS1/32KHZ_OUT A8 2 O
<43> PBAT_SMBDAT GPIO154/I2C1C_DATA/PS2_CLK1B/GANG_DATA5 GPIO015/GPTP-OUT7 ME_SUS_PWR_ACK <11> A
G
PBAT_SMBCLK A56 B9 RUN_ON_EC UE5
<43> PBAT_SMBCLK GPIO155/I2C1C_CLK/PS2_DAT1B/GANG_DATA6 GPIO016/GPTP-IN8 A9 TC7SH08FU_SSOP5~D
CV2_ON <33>
3
1 2 MSDATA JTAG_TDI A51 GPIO017/GPTP-OUT8 B39 RESET_OUT#
JTAG_TDO B55 GPIO145/I2C1K_DATA/JTAG_TDI GPIO107/NRESET_OUT A44 VCCST_PWRGD_EC 2 1 RESET_OUT# <11,14>
RE86 10K_0402_5% +3.3V_ALW
JTAG_CLK B56 GPIO146/I2C1K_CLK/JTAG_TDO GPIO125/GPTP-IN5/PECI_REQUEST#/GANG_BUSY 0_0402_5% @ RE308 VCCST_PWRGD <11,14>
1 2 DOCK_POR_RST# JTAG_TMS A53 GPIO147/I2C1J_DATA/I2C2C_DATA/JTAG_CLK A54
JTAG_RST# B47 GPIO150/I2C1J_CLK/I2C2C_CLK/JTAG_TMS GPIO151/GPTP-IN4/GANG_DATA2 B58 SIO_PWRBTN# AC_PRESENT <11>
RE277 100K_0402_5%
JTAG_RST# GPIO152/GPTP-OUT4 SIO_PWRBTN# <11,14>
RPE3
RPE10 FAN1_TACH B22 A3 DOCK_SMB_DAT CHARGER_SMBCLK 1 8
8 1 CV2_ON DOCK_POR_RST# A21 GPIO050/FAN_TACH1/GTACH0/GANG_START GPIO003/I2C1A_DATA B4 DOCK_SMB_CLK DOCK_SMB_DAT <38> CHARGER_SMBDAT 2 7
for no-dock : A21 use LID_CL_SIO# <38> DOCK_POR_RST#
7 2 RUN_ON B23 GPIO051/FAN_TACH2/GANG _MODE GPIO004/I2C1A_CLK A4 A_ON DOCK_SMB_CLK <38> DOCK_SMB_DAT 3 6
6 3 A_ON trace width 20 mils B24 GPIO052/FAN_TACH3/GTACH1/GANG_ERROR GPIO005/I2C1B_DATA/BCM_B_DAT B5 A_ON <41> DOCK_SMB_CLK 4 5
PCH_ALW_ON <43> PS_ID GPIO053/PWM0 GPIO006/I2C1B_CLK/BCM_B_CLK SIO_EXT_WAKE# <9>
5 4 trace width 20 mils A23 B7 Reserve
B25 GPIO054/PWM1/GPWM1 GPIO012/I2C1H_DATA/I2C2D_DATA A7 SUSACK# <11>
<26> BIA_PWM_EC 2.2K_0804_8P4R_5%
FAN1_PWM A24 GPIO055/PWM2 GPIO013/I2C1H_CLK/I2C2D_CLK/GANG_DATA3 B48 GPU_SMBDAT ENVDD_PCH <6,26>
100K_0804_8P4R_5% Reserve
GPIO056/PWM3/GPWM0 GPIO130/I2C2A_DATA/BCM_C_DAT B49 GPU_SMBCLK Reserve
GPIO131/I2C2A_CLK/BCM_C_CLK A47 CHARGER_SMBDAT 8/21 CRB1.0 change to 0603 1/10W THERMATRIP3# 1 2
GPIO132/I2C1G_DATA B50 CHARGER_SMBCLK CHARGER_SMBDAT <51> 10/30 move to EC side RE301 10K_0402_5%
A43 GPIO140/I2C1G_CLK B52 SIO_SLP_SUS#_R CHARGER_SMBCLK <51>
for no-dock : A43 use BC_CLK_ECE1099 RC76 1 2 43K_0402_1%
<31> BC_CLK_ECE5048 B45 GPIO123/BCM_A_CLK GPIO141/I2C1F_DATA/I2C2B_DATA A49 SIO_SLP_SUS# <8,11,17,18,41,46,47,48>
for no-dock : B45 use BC_DAT_ECE1099
<31> BC_DAT_ECE5048 A42 GPIO122/BCM_A_DAT GPIO142/I2C1F_CLK/I2C2B_CLK B53 PBAT_PRES# <43,51,52>
for no-dock : A42 use BC_INT#_ECE1099 +3.3V_ALW
<31> BC_INT#_ECE5048 B20 GPIO121/BCM_A_INT# GPIO143/I2C1E_DATA A50 USH_SMBDAT <33>
C <51,52> ACAV_IN_NB A18 GPIO032/BCM_E_CLK GPIO144/I2C1E_CLK USH_SMBCLK <33> C
<11> SIO_SLP_S5# B19 GPIO031/GPTP-OUT2/BCM_E_DAT A59 1 2 RPE5
<30> BEEP GPIO030/GPTP-IN2/BCM_E_INT#/GANG_DATA7 SYSPWR_PRES +3.3V_ALW2
A20 RE57 1K_0402_5% 1 8 +RTC_CELL
<39> BC_CLK_ECE1117 GPIO047/LSBCM_D_CLK
1
BC_DAT_ECE1117
100K_0402_5%
B21 B62 2 7
<39> BC_DAT_ECE1117 GPIO046/LSBCM_D_DAT/GANG_STROBE BGP0 EC_FPM_EN <33> POA_WAKE#
A19 A64 3 6
<39> BC_INT#_ECE1117 GPIO045/LSBCM_D_INT# VCI_OVRD_IN ACAV_IN <51,52>
Reserve VCI_IN2#
RE58
A60 4 5
A6 VCI_OUT B67 POWER_SW_IN# ALWON <44>
<12> SIO_EXT_SMI# A27 GPIO011/nSMI VCI_IN0# A63 DOCK_PWR_SW# 100K_0804_8P4R_5%
2
<8> SIO_RCIN# A28 GPIO061/LPCPD# VCI_IN1# B63 VCI_IN2# Reserve
<8,31> IRQ_SERIRQ B30 SER_IRQ VCI_IN2# B68 POA_WAKE#
<11> PCH_PLTRST#_EC CLK_PCI_MEC A29 LRESET# VCI_IN3# POA_WAKE# <33>
<8> CLK_PCI_MEC PCI_CLK RE59 close to UE2 at least 250mils
B31 B51 +PECI_VREF 1 2
<8,31> LPC_LFRAME# LFRAME# VREF_PECI PECI_EC_R +1.0VS_VCCIO
A30 A48 1 2 @ RE59 0_0402_5%
<8,31> LPC_LAD0 LAD0 PECI_DAT PECI_EC <12>
0.1U_0201_10V6K
B32 RE60 43_0402_5%
<8,31> LPC_LAD1 A31 LAD1 B13 REM_DIODE1_N CE24 1 2 2200P_0402_50V7K
<8,31> LPC_LAD2 LAD2 DN1_DP1A/THERM
1
REM_DIODE1_P
CE25
B33 A13
<8,31> LPC_LAD3 LAD3 DP1_DN1A/VREF_T REM_DIODE2_N
A32 B14 CE26 1 2 2200P_0402_50V7K
<8,31> CLKRUN# A33 CLKRUN# DN2_DP2A A14 REM_DIODE2_P
<9> SIO_EXT_SCI#
2
GPIO100/NEC_SCI DP2_DN2A A15
MEC_XTAL1 A61 DN3_DP3A B16
MEC_XTAL2_R A62 XTAL1 DP3_DN3A A16 REM_DIODE4_N CE27 1 2 2200P_0402_50V7K
XTAL2 DN4_DP4A B17 REM_DIODE4_P
DP4_DN4A B15 CE24, CE26, CE27 Place near UE2
VIN A17 VSET_5085 PCH_RSMRST# 1 2
VSET A12 RE88 10K_0402_5%
VCP I_ADP <51>
B34 THERMATRIP2#
THERMTRIP2# A2 THERMATRIP3#
GPIO002/THERMTRIP3# B29 THSEL_STRAP
VSS_ADC
GPIO024/THSEL_STRAP
VSS_RO
VR_CAP
A46 H_PROCHOT#_R1 RE288 1 2 100_0402_5%
H_VSS
PROCHOT_IN#/PROCHOT_IO# H_PROCHOT# <12,49,51>
AGND
B61 1 2
I_BATT <51>
VSS
V_ISYS0 A57 RE641 2 4.7K_0402_5%
EP
V_ISYS1 I_SYS <49,51>
RE312 0_0402_5%
1
MEC5085-LZY_DQFN132_11X11
B66
B11
B60
+VR_CAP B12
B54
B18
C1
@ RE313
15mil 10K_0402_5%
2
Setting for Thermal Design
4.7U_0603_6.3V6K
1
Link 50271-0040N-001 DONE
CE31
+3.3V_ALW JFAN1
Thermal diode mapping
2
1
MEC_XTAL2_R 1 2 FAN1_PWM
2
1
FAN1_TACH
100K_0402_5%
3
ESR <2ohms 5085 Channel Location 3 4
4 +5V_RUN
RE63
10U_0603_10V6M
5
DP1/DN1 CPU GND1
1
@RE290 CLK_PCI_MEC 6
32 KHz Clock
2
GND2
1
@EMC@ RE66
@ DE1
0_0402_5%
1
10_0402_5%
CE32
B JTAG_RST# DP2/DN2 WiGig ACES_50271-0040N-001
CONN@ B
2
2
DN2a/DP2a DDR
1
MEC_XTAL1 1 2 MEC_XTAL2 8/28 schematic review +3.3V_RUN

2
1U_0402_6.3V6K
4.7P_0402_50V8C
@EMC@ CE34
1
1
@SHORT PADS~D
JTAG1 CONN@
100_0402_1%
33P_0402_50V8J
33P_0402_50V8J
10K_0402_5%
YE1
DP3/DN3 NA
1
1
@ RE65
32.768KHZ_12.5PF_Q13FC135000040
1
1
CE30
RE67
+3.3V_ALW reserve for DC fan
CE28
CE29
DP4/DN4 V.R
2
+3.3V_ALW
2
100K_0402_5%
2
EMI depop location

Place under CPU
1
RUNPWROK
Place CE35 close to the QE3 as possible
2
RE68
8.2K_0402_5%
Place close pin A29
1
REM_DIODE1_P
3
RE69
+1.0VS_VCCIO SIO_SLP_S3#
100P_0402_50V8J
2
1
QE2B
C
RUN_ON#
@ CE35
5 2
2
B
1
6
2
E QE3
G
4
3
METR3904W-G NPN SOT323-3 THERMATRIP2#
REM_DIODE1_N
QE2A
1 3 1 2
METR3904W-G NPN SOT323-3

2 RE70 2.2K_0402_5%
S
+3.3V_ALW <32,41,47> RUN_ON
0.1U_0402_25V6
1
QE11 C
1
QE4
L2N7002WT1G_SC-70-3 2
CE36
B
DN2/DP2 for DDR on QE7, place QE7 close
49.9_0402_1%
E
to DDR and CE46 close to QE7
3
1
8
7
6
5
+3.3V_ALW
10K_8P4R_5%
1 2
2
RE71
DN2/DP2 for Wigig on QE5, place QE5 close to Wigig and @ RE90 0_0402_5%
RPE7
CE37 close to QE5

1
REM_DIODE2_P
10K_0402_5%
10K_0402_5%
10K_0402_5%
100K_0402_5%
CONN@ <12,20,21> H_THERMTRIP#

2
1
2
3
4
@ RE75
JDEG1
RE72
RE73
RE74
100P_0402_50V8J
1 METR3904W-G NPN SOT323-3
1
1
JTAG_TDI
100P_0402_50V8J
@ CE37
2 C
E
2
1
JTAG_TMS
@ CE46
3 2 2
B
2
3 4 JTAG_CLK B
2
4 5 JTAG_TDO C
QE7 E QE5
3
11 5 6 MSCLK METR3904W-G NPN SOT323-3
12 G1 6 7 MSDATA
G2 7 8 HOST_DEBUG_TX REM_DIODE2_N
8 9 2 1
9 10 @ EC5048_TX <31>
RE305 0_0402_5%
10 Pin8 5085_TXD for EC Debug 2 1
HB_A531015-SCHR21 pin9 5048_TXD for SBIOS @ RE306 0_0402_5%
UART0_TXD <9> DP4/DN4 for Skin on QE6, place QE6 close to Vcore VR choke.
debug +3.3V_ALW +3.3V_ALW +3.3V_ALW REM_DIODE4_P VSET_5085 THSEL_STRAP 1 2
RE78 1K_0402_5%
100P_0402_50V8J
0.1U_0402_25V6
RE300 CE47 PANEL SIZE
1
10K_0402_5%
240K_0402_5%
1.58K_0402_1%
1
1
+3.3V_RUN
1K_0402_5%
@CE39
CONN@ C
* 240K 4700p 12"
RE79
RE81
RE300
CE38
RE77
A JLPDE1 2 A
1 RE79 CE40 REV B
130K 4700p 14" Channel 1
2
1 2 E QE6
240K 4700p X00 Thermal Monitoring Interface Strap Option
2
2 3 LPC_LAD0 METR3904W-G NPN SOT323-3
33K 4700p 15"
2
3 4 LPC_LAD1
4 5 LPC_LAD2 130K 4700p X01 BOARD_ID FWP# PANEL_ID REM_DIODE4_N HIGH Thermistor Readings
11 5 6 LPC_LAD3 4.3K 4700p 17" LOW Diode Readings
G1 6 LPC_LFRAME# 33K 4700p X02
4700P_0402_25V7K
4700P_0402_25V7K
12 7
G2 7
2
PCH_PLTRST#_EC
10K_0402_5%
8
8
8.2K 4700p X03/X04
1
1
@ RE82
9
9 Rest=1.58K , Tp=96 degree
CE40
CE47
10 CLK_PCI_LPDEBUG <8>
10
4.3K 4700p X05
2
HB_A531015-SCHR21
1
* 1K 4700p A00 PANEL_ID rise time is measured from 5%~68%. DELL CONFIDENTIAL/PROPRIETARY
BOARD_ID rise time is measured from 5%~68%. TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
MEC5085
5 4 3 2 1
5 4 3 2 1
power rail option: TPM power rail must same as +3.3V_SPI (SPI ROM)
+3.3V_M +3.3V_M_TPM
Vinafix.com
D D
@ RZ72 1 2 0_0603_5%
+3.3V_ALW_PCH +3.3V_M_TPM +3.3V_ALW

PJP11
1 2 1 2 USH_SMBCLK
@ RZ8 2.2K_0402_5%
PAD-OPEN1x1m 1 2 USH_SMBDAT
@ RZ9 2.2K_0402_5%
+3.3V_M_TPM 1 2 USH_PWR_STATE#
RZ10 1M_0402_5%
1 2
+3.3V_M_TPM @ RZ88 0_0402_5%
1 2 TPM_PIRQ# 7/18 vender suggest.
RZ69 10K_0402_5% 1 2 +UZ12_TPM
+3.3V_RUN @ RZ89 0_0402_5%
USH CONN
+3.3V_RUN JUSH1 CONN@
28
C 27 GND C
+3.3V_M_TPM +3.3V_ALW GND
1 2 @ RZ85 1 2 0_0402_5% +PWR_SRC_R26
@
+PWR_SRC +3.3V_ALW2_R 26
RZ90 10K_0402_5% UZ12 +3.3V_ALW2 @ RZ84 1 2 0_0402_5% 25
1 24 25
1 2 29 VSB <32> CV2_ON 23 24
<11,17,47> SIO_SLP_S0# @ 30 GPIO0/SDA/XOR_OUT 8 +UZ12_TPM <32> POA_WAKE# 22 23
RZ112 0_0402_5%
TPM_LPM# 3 GPIO1/SCL VDD 14 <32> EC_FPM_EN 21 22
6 GPIO2/GPX VDD 22 20 21
GPIO3/BADD VDD 20
0.1U_0201_10V6K
0.1U_0201_10V6K
10U_0603_10V6M
0.1U_0201_10V6K
0.1U_0201_10V6K
10U_0603_10V6M
19
2 33_0402_5% PCH_SPI_D1_2_R <10> USB20_N7 19
RZ58 1 24 2 1 1 1 1 1 1 18
<8> PCH_SPI_D1_R1 2 33_0402_5% PCH_SPI_D0_2_R LAD0/MISO NC <10> USB20_P7 18
RZ59 1 21 7 17
<8> PCH_SPI_D0_R1 LAD1/MOSI NC 17
CZ74
CZ75
CZ76
CZ73
CZ71
CZ72
18 10 16
<8> TPM_PIRQ# 15 LAD2/SPI_IRQ# NC 11 <32> USH_SMBCLK 15 16
LAD3 NC 25 2 2 2 2 2 2 <32> USH_SMBDAT 14 15
RZ60 1 2 33_0402_5% PCH_SPI_CLK_2_R 19 NC 26 <31> BCM5882_ALERT# 13 14
<8> PCH_SPI_CLK_R1 PCH_SPI_CS#2_R 20 LCKL/SCLK NC 13
@ RZ61 1 2 0_0402_5% 31
+3.3V_ALW
12
<8> PCH_SPI_CS#2 17 LFRAME#/SCS# NC 11 12
<11> PLTRST_TPM# 27 LRESET#/SPI_RST#/SRESET# 9 @ RZ86 1 2 0_0402_5% +5V_ALW2_R 10 11
TPM_GPIO4 13 SERIRQ GND +5V_ALW2 10
1 2 16 9
CLKRUN#/GPIO4/SINT# GND +5V_ALW 9
@ RZ110 0_0402_5% 28 23 8
LPCPD# GND +3.3V_RUN 8
1
10K_0402_5%
32 place CZ73 as close as UZ12.8 @ RZ114 1 2 0_0402_5% 7

GND <11,28,29,35> PCH_PLTRST#_AND +5V_RUNPCH_PLTRST#_AND_R 7
RZ62
4 33 CZ74,CZ76 as close as UZ12.14 @ RZ115 1 2 0_0402_5% 6

5 PP PGND 12 <31> USH_RST# 5 6
TEST Reserved CZ75 as close as UZ12.22 <31> USH_PWR_STATE# 5
4
<12> CONTACTLESS_DET# 3 4
NPCT650JAAYX_QFN32_5X5 place CZ71,CZ72 as close as UZ12.1
2
2 3
@ RZ87 1 2 0_0402_5% USH_DET#_R1 2
<31> USH_DET# 1
PCH_SPI_CLK_2_R DZ7 E-T_6705K-Y26N-00L
2 1
33_0402_5%
2
@EMC@
B RB751S40T1G_SOD523-2 B
RZ63
1
0.1U_0402_25V6
1
+3.3V_M_TPM PCH_PLTRST#_AND
@EMC@
CZ77
+5V_ALW2 +3.3V_ALW2 +5V_RUN +3.3V_RUN +3.3V_ALW

2
.047U_0402_16V7K
3
1
S
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
PCH_SPI_CS#2_R
G LP2301ALT1G_SOT23-3
CZ68
EMC@
1 2 2 1 1 1 1 1
@
RZ113 100_0402_5% QZ9
CZ94
CZ24
CZ10
CZ11
CZ12
D
1
TPM_LPM# 2 2 2 2 2
1
RZ111 For ESD solution

10K_0402_5%
RZ113 RZ111 POP Close to JUSH1
1K 1K MMBT3906
2
100 10K LP2301A
A A
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT USH & TPM
5 4 3 2 1
5 4 3 2 1
+3.3V_HDD_M2 +3.3V_HDD_M2 +3.3V_HDD_M2
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
1
1
@ RN25
@ RN26
@ RN27
@ RN28
@ RN42
@ RN43
@ RN44
@ RN49
@ RN51
RN50
Vinafix.com
2
2
D RD1_A_DE0 D
RD1_A_DE1 RD1_A_EQ0 RD1_B_EQ0
RD1_B_DE0 RD1_A_EQ1 RD1_B_EQ1 +3.3V_HDD_M2 IFDET_SATA#_PCIE

RD1_B_DE1 RD1_A_EQ2 RD1_B_EQ2 (SATAXPCIE0) FLEX IO 11
0.1U_0201_10V6K
0 PCIE
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
0.01UF_0402_25V7K
1 1
1
1
@ RN40
@ RN41
@ RN45
@ RN46
@ RN47
@ RN52
@ RN53
@ RN54
CN19
RN38
RN39
CN20
1 SATA
2 2
2
2
PCIE/SATA Repeater
UN4
if signal is PCIE GEN3/SATA GEN3 maybe change C value
12 or no need for DG0.9 SATA EXPRESS HDD
24 VDD_3.3
VDD_3.3 8/25
0.22U_0402_10V6K 1 2 CN21 PCIE_PTX_C_RD_DRX_P12 1 18 PCIE_PTX_RD_DRX_P12 CN25 2 1 0.22U_0402_10V6K
<10> PCIE_PTX_DRX_P12 1 2 CN22 PCIE_PTX_C_RD_DRX_N12 2 A_INP A_OUTP 17 PCIE_PTX_RD_DRX_N12 PCIE_PTX_C_DRX_P12 <35>
Programmable output de-emphasis level Equalizer control and program for channel A. 0.22U_0402_10V6K CN26 2 1 0.22U_0402_10V6K
<10> PCIE_PTX_DRX_N12 A_INN A_OUTN PCIE_PTX_C_DRX_N12 <35>
setting for channel A . A_EQ0, A_EQ1 and A_EQ2: internally pulled down at ~150K
A_DE0: internally pulled up at ~150K; <10> PCIE_PRX_DTX_P12
0.22U_0402_10V6K 1 2 CN23 PCIE_PRX_C_RD_DTX_P12 5
B_OUTP B_INP
14 PCIE_PRX_RD_DTX_P12 RN77 2 10_0402_5%
PCIE_PRX_C_DTX_P12 <35>
A_DE1 internally pulled down at ~150K [A_EQ2,A_EQ1,A_EQ0] == 0.22U_0402_10V6K 1 2 CN24 PCIE_PRX_C_RD_DTX_N12 4 15 PCIE_PRX_RD_DTX_N12 RN78 2 10_0402_5%
<10> PCIE_PRX_DTX_N12 B_OUTN B_INN PCIE_PRX_C_DTX_N12 <35>
LLL: EQ Level1(default) RD1_A_EQ0 23 6 RD1_A_DE0
[A_DE1,A_DE0] == LHL: EQ Level2 RD1_A_EQ1 22 A_EQ0 A_DE0 8 RD1_A_DE1
C RD1_A_EQ2 19 A_EQ1 A_DE1 C
LL: -7.5dB HLL: EQ Level3 A_EQ2 PWD Funtion
HL: -2dB HHL: EQ Level4 if signal is PCIE GEN3/SATA GEN3 maybe change C value
or no need for DG0.9 SATA EXPRESS HDD RD1_B_EQ0 11 13 RD1_B_DE0
LH: -3.5dB (default) LLH: EQ Level5 RD1_B_EQ1 21 B_EQ0 B_DE0 9 RD1_B_DE1 0 Normal mode(default)
B_EQ1 B_DE1
HH: -6dB LHH: EQ Level6 RD1_B_EQ2 16
B_EQ2
HLH: EQ Level7 3
HHH: EQ Level8 7 PWD 10 RD1_REXT RN30 1 2 4.99K_0402_1% 1 power down mode
25 GND REXT 20
Programmable output de-emphasis level EPAD MODE IFDET_SATA#_PCIE <10,35>
setting for channel B. Equalizer control and program for channel B.
B_DE0: internally pulled up at ~150K; B_EQ0, B_EQ1 and B_EQ2: internally pulled down at ~150K PS8558BTQFN24GTR2-A_TQFN24_4X4
B_DE1 internally pulled down at ~150K
[B_EQ2,B_EQ1,B_EQ0] ==
[B_DE1,B_DE0] == LLL: EQ Level1(default)
LL: -7.5dB LHL: EQ Level2
HL: -2dB HLL: EQ Level3
HHL: EQ Level4 +3.3V_HDD_M2
LH: -3.5dB (default)
HH: -6dB LLH: EQ Level5
LHH: EQ Level6
HLH: EQ Level7
0.1U_0201_10V6K
HHH: EQ Level8
0.01UF_0402_25V7K
1 1
CN29
CN30
+3.3V_HDD_M2 +3.3V_HDD_M2 +3.3V_HDD_M2 2 2
B
PCIE/SATA Repeater B
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
UN5
1
1
@ RN55
@ RN56
@ RN57
@ RN58
@ RN63
@ RN64
@ RN65
@ RN69
@ RN70
@ RN71
12
24 VDD_3.3
VDD_3.3
0.22U_0402_10V6K 1 2 CN32 PCIE_PTX_C_RD_DRX_P11 1 18 PCIE_PTX_RD_DRX_P11 CN35 2 1 0.22U_0402_10V6K
<10> PCIE_PTX_DRX_P11
2
0.22U_0402_10V6K 1 2 CN31 PCIE_PTX_C_RD_DRX_N11 2 A_INP A_OUTP 17 PCIE_PTX_RD_DRX_N11 CN36 2 1 0.22U_0402_10V6K PCIE_PTX_C_DRX_P11 <35>
<10> PCIE_PTX_DRX_N11 A_INN A_OUTN PCIE_PTX_C_DRX_N11 <35>
RD2_A_DE0
0.22U_0402_10V6K 1 2 CN33 PCIE_PRX_C_RD_DTX_P11 5 14 PCIE_PRX_RD_DTX_P11 RN81 2 1 0_0402_5%
RD2_A_DE1 RD2_A_EQ0 RD2_B_EQ0 <10> PCIE_PRX_DTX_P11 1 2 CN34 PCIE_PRX_C_RD_DTX_N11 4 B_OUTP B_INP 15 PCIE_PRX_RD_DTX_N11 PCIE_PRX_C_DTX_P11 <35>
0.22U_0402_10V6K RN82 2 1 0_0402_5%
<10> PCIE_PRX_DTX_N11 B_OUTN B_INN PCIE_PRX_C_DTX_N11 <35>
RD2_B_DE0 RD2_A_EQ1 RD2_B_EQ1 RD2_A_EQ0 23 6 RD2_A_DE0
RD2_A_EQ1 22 A_EQ0 A_DE0 8 RD2_A_DE1
RD2_B_DE1 RD2_A_EQ2 RD2_B_EQ2 RD2_A_EQ2 19 A_EQ1 A_DE1
if signal is PCIE GEN3/SATA GEN3 maybe change C value A_EQ2
or no need for DG0.9 SATA EXPRESS HDD RD2_B_EQ0 11 RD2_B_DE0
13
RD2_B_EQ1 21 B_EQ0 B_DE0 RD2_B_DE1
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
9
B_EQ1 B_DE1
1
RD2_B_EQ2 16
@ RN59
@ RN60
@ RN61
@ RN62
@ RN66
@ RN67
@ RN68
@ RN72
@ RN73
@ RN74
B_EQ2
3
7 PWD 10 RD2_REXT RN31 1 2 4.99K_0402_1%
25 GND REXT 20 IFDET_SATA#_PCIE
2
EPAD MODE
PS8558BTQFN24GTR2-A_TQFN24_4X4
A A
Mini Card-2/2
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
LA-C621P 1.0
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
+3.3V_HDD_M2
0.1U_0201_10V6K
0.1U_0201_10V6K
22U_0603_6.3V6M
22U_0603_6.3V6M
@
1 1
1
CN41
CN42
CZ60
CZ61
2
2
2 2
2280 SSD
Place near HDD CONN
NGFF slot C Key M
+3.3V_HDD_M2
2A
JNGFF3 PJP34
1 2 1 2
GND 3P3VAUX +3.3V_RUN
3 4
5 GND 3P3VAUX 6 PAD-OPEN1x2m
7 PERn3 NC 8
9 PERp3 NC 10 NVME_LED# 2 1
11 GND DAS/DSS# 12 @ RZ118 PCH_SATA_LED# <10,40>
+3.3V_HDD_M2 0_0402_5%
8/5 CKLT0.9 13 PETn3 3P3VAUX 14
15 PETp3 3P3VAUX 16
C 1 2 M2_DEVSLP 17 GND 3P3VAUX 18 C
@ RN37 10K_0402_5% 19 PERn2 3P3VAUX 20
21 PERp2 NC 22
23 GND NC 24
25 PETn2 NC 26
27 PETp2 NC 28
29 GND NC 30
<34> PCIE_PRX_C_DTX_N11 31 PERn1 NC 32
<34> PCIE_PRX_C_DTX_P11 33 PERp1 NC 34
35 GND NC 36
<34> PCIE_PTX_C_DRX_N11 37 PETn1 NC 38
<34> PCIE_PTX_C_DRX_P11 39 PETp1 DEVSLP 40 M2_DEVSLP <10>
41 GND NC 42
<34> PCIE_PRX_C_DTX_P12 43 PERn0/SATA-B+ NC 44
Double check P/N <34> PCIE_PRX_C_DTX_N12 45 PERp0/SATA-B- NC 46
47 GND NC 48
<34> PCIE_PTX_C_DRX_N12 49 PETn0/SATA-A- NC 50
<34> PCIE_PTX_C_DRX_P12 51 PETp0/SATA-A+ PERST# 52 PCH_PLTRST#_AND <11,28,29,33>
53 GND CLKREQ# 54 PCIE_WAKE# CLKREQ_PCIE#3 <11>
<11> CLK_PCIE_N3 55 REFCLKN PEWake# 56 PCIE_WAKE# <29,31>
<11> CLK_PCIE_P3 57 REFCLKP NC 58
GND NC
59 60 SUSCLK_R 1 2
61 NC SUSCLK(32kHz) 62 @ SUSCLK <11,29>
RN99 0_0402_5%
<10,34> IFDET_SATA#_PCIE 63 PEDET(NC-PCIE/GND-SATA) 3P3VAUX 64
65 GND 3P3VAUX 66
67 GND 3P3VAUX
GND 68
GND1 69
B GND2 B
BELLW_SD-80159-4221
CONN@
Link BELLW_80159-4221 DONE
A A
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT HDD CONN
5 4 3 2 1
5 4 3 2 1
1 2 USB3_PRX_L_DTX_P1 +5V_USB_CHG_PWR
Vinafix.com
<10> USB3_PRX_DTX_P1 @ RI15 0_0402_5%
DI4 EMC@ JUSB3
1 2 USB3_PRX_L_DTX_N1 USB3_PRX_L_DTX_N1 1 1 10 9 USB3_PRX_L_DTX_N1 1
<10> USB3_PRX_DTX_N1 USB20_N1_R VBUS
150U_B2_6.3VM_R35M
@ RI16 0_0402_5% 2
USB3_PRX_L_DTX_P1 2 2 USB3_PRX_L_DTX_P1 USB20_P1_R D-
100U_1206_6.3V6M
0.1U_0201_10V6K
D D
9 8 1 3
D+
@
1 1 4
USB3_PTX_L_DRX_N1 4 4 USB3_PTX_L_DRX_N1 USB3_PRX_L_DTX_N1 GND
CI32
7 7 + 5
SSRX-
CI14
USB3_PRX_L_DTX_P1
CI17
PESD5V0U2BT_SOT23-3
6 10
SSRX+ GND
2
USB3_PTX_L_DRX_P1 5 5 6 6 USB3_PTX_L_DRX_P1 7 11
2 2 2 USB3_PTX_L_DRX_N1 GND GND
EMC@ DI5
8 12
2
3 3 USB3_PTX_L_DRX_P1 9 SSTX- GND 13
2 1 USB3_PTX_C_DRX_P1 1 2 USB3_PTX_L_DRX_P1 SSTX+ GND
<10> USB3_PTX_DRX_P1
1
CI16 0.1U_0402_25V6 @ RI17 0_0402_5% 8 SINGA_2UB4008-900101F
CONN@
1
2 1 USB3_PTX_C_DRX_N1 1 2 USB3_PTX_L_DRX_N1 L05ESDL5V0NA-4_SLP2510P8-10-9
CI13 0.1U_0402_25V6 RI18 0_0402_5%
LINK SUB4008-90010F DONE
+5V_ALW
+5V_USB_CHG_PWR
UI3
1 12
IN OUT
2
<10> USB20_N1 3 DM_OUT
<10> USB20_P1 DP_OUT 10 SW_USB20_P1
13 DP_IN 11 SW_USB20_N1 MCM1012B900F06BP_4P
<10> USB_OC0# FAULT# DM_IN SW_USB20_N1 1 2 USB20_N1_R
ILIM_SEL 4 1 2
ILIM_SEL
5 15 SW_USB20_P1 4 3 USB20_P1_R
<31> USB_PWR_SHR_VBUS_EN EN ILIM_LO 16 2 1 4 3
RI14
ILIM_HI 22.1K_0402_1% EMC@ LI7
C +5V_ALW 6 C
<31> USB_PWR_SHR_EN# 7 CTL1 9
8 CTL2 NC 14
ILIM_SEL CTL3 GND
0.1U_0402_25V6
RI13 2 1 17
10K_0402_5% GNDP
1
CI33
@EMC@
PI5USB2544ZHEX_TQFN16_3X3
Link Pericom PI5USB2544 Done
+5V_ALW
10U_0402_6.3V6M
0.1U_0201_10V6K
1 1
@ CI31
CI19
2 2
Place near UI3.1
B B
A A
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT USB SW
5 4 3 2 1
5 4 3 2 1
+USB_LEFT_PWR
DI1 EMC@
USB3_PRX_L_DTX_N3 USB3_PRX_L_DTX_N3 JUSB1 CONN@
1 1 10 9
USB3_PTX_L_DRX_P3 9
USB3_PRX_DTX_P3 1 2 USB3_PRX_L_DTX_P3 USB3_PRX_L_DTX_P3 2 2 USB3_PRX_L_DTX_P3 SSTX+
<10> USB3_PRX_DTX_P3 9 8 1
VBUS
@ RI19 0_0402_5% USB3_PTX_L_DRX_N3 8
USB3_PTX_L_DRX_N3 USB3_PTX_L_DRX_N3 SSTX-
0.1U_0201_10V6K
4 4 7 7 USB20_P3_R 3
USB3_PRX_DTX_N3 USB3_PRX_L_DTX_N3 D+
100U_1206_6.3V6M
1 2 1 7
<10> USB3_PRX_DTX_N3 GND
1
USB3_PTX_L_DRX_P3 USB3_PTX_L_DRX_P3
CI3
@ RI20 0_0402_5% 5 5 6 6 USB20_N3_R 2 10
USB3_PRX_L_DTX_P3 D- GND
CI1
PESD5V0U2BT_SOT23-3
6 11
Vinafix.com
SSRX+ GND
2
3 3 4 12
2
2 GND GND
EMC@ DI2
USB3_PRX_L_DTX_N3 5 13
2
8 SSRX- GND
LOTES_AUSB0014-P003A
1
D L05ESDL5V0NA-4_SLP2510P8-10-9 D
1
USB3_PTX_DRX_P3 2 1 USB3_PTX_C_DRX_P3 1 2 USB3_PTX_L_DRX_P3
<10> USB3_PTX_DRX_P3
CI4 0.1U_0402_25V6 @ RI21 0_0402_5% EMC@ LI3 Link LOTES_AUSB0014-P003A DONE
USB20_P3 4 3 USB20_P3_R
USB3_PTX_DRX_N3 USB3_PTX_C_DRX_N3 USB3_PTX_L_DRX_N3 <10> USB20_P3 4 3
2 1 1 2
CI5 0.1U_0402_25V6 RI22 0_0402_5%
USB20_N3 1 2 USB20_N3_R
<10> USB20_N3 1 2
MCM1012B900F06BP_4P
8/19 for layout routing change
+USB_LEFT_PWR
+5V_ALW
UI1
1
5 OUT
IN 2
GND
10U_0603_10V6M
0.1U_0201_10V6K
4
<31> USB_PWR_EN1# EN
1 3
OCB USB_OC1# <10>
@ CI6
CI7
0.1U_0402_25V6
SY6288D20AAC_SOT23-5
1
2
2
CI34
@EMC@
9/3 change to SOT23 package
2
C C
+USB_REAR_PWR
JUSB2 CONN@
B 1 B
1 2 USB3_PRX_L_DTX_P4 USB20_N4_R 2 VBUS
<10> USB3_PRX_DTX_P4 @ USB20_P4_R D-
RI23 0_0402_5% 3
DI6 EMC@ D+
100U_1206_6.3V6M
0.1U_0201_10V6K
4
1 2 USB3_PRX_L_DTX_N4 USB3_PRX_L_DTX_N4 1 1 USB3_PRX_L_DTX_N4 USB3_PRX_L_DTX_N4 GND
<10> USB3_PRX_DTX_N4 10 9 1 5
SSRX-
CI10
@ RI24 0_0402_5% USB3_PRX_L_DTX_P4 6 10
USB3_PRX_L_DTX_P4 USB3_PRX_L_DTX_P4 SSRX+ GND
CI8
2 2 9 8 7 11
GND GND
PESD5V0U2BT_SOT23-3
USB3_PTX_L_DRX_N4 8 12
2
SSTX- GND
3
USB3_PTX_L_DRX_N4 4 4 USB3_PTX_L_DRX_N4 2 USB3_PTX_L_DRX_P4
7 7 9
SSTX+ GND
13
EMC@ DI3
2
3
USB3_PTX_L_DRX_P4 5 5 6 6 USB3_PTX_L_DRX_P4 ACON_TARAV-9R1U91
1
3 3
Link TARAV-9R1U91 DONE
1
2 1 USB3_PTX_C_DRX_P4 1 2 USB3_PTX_L_DRX_P4 8
<10> USB3_PTX_DRX_P4 @ RI25
CI28 0.1U_0402_25V6 0_0402_5%
L05ESDL5V0NA-4_SLP2510P8-10-9
2 1 USB3_PTX_C_DRX_N4 1 2 USB3_PTX_L_DRX_N4
<10> USB3_PTX_DRX_N4 @ RI26
CI27 0.1U_0402_25V6 0_0402_5%
+USB_REAR_PWR
+5V_ALW
UI2
1
5 OUT
EMC@ LI4 IN 2
USB20_P4 USB20_P4_R GND
10U_0603_10V6M
0.1U_0201_10V6K
4 3 4
<10> USB20_P4 4 3 <31> USB_PWR_EN2# EN
@ CI11
1 3 USB_OC2# <10>
OCB
CI12
USB20_N4 USB20_N4_R
0.1U_0402_25V6
1 2 SY6288D20AAC_SOT23-5
<10> USB20_N4 1 2
1
2
2
CI35
@EMC@
MCM1012B900F06BP_4P
9/3 change to SOT23 package
A A
2
8/19 for layout routing change
USB3.0
5 4 3 2 1
5 4 3 2 1
JDOCK1 CONN@
DOCK_DET_1 1 2 DOCK_AC_OFF
3 1 2 4 DOCK_AC_OFF <52>
<27> SW_LAN1_10_GRN# 5 3 4 6 SW_LAN1_100_ORG# <27>
<24,25> HUB_DP0_CADET 7 5 6 8 HUB_DP1_CADET <24,25>
<24> HUB_DP0_P0
<24> HUB_DP0_N0
C302 2
C295 2
1 0.1U_0402_25V6
1 0.1U_0402_25V6 Vinafix.com
HUB_DP0_P0_C
HUB_DP0_N0_C
EMC@ R259 1
EMC@ R252 1
2 33_0402_5% HUB_DP0_P0_R
2 33_0402_5% HUB_DP0_N0_R
9
11
13
7
9
11
8
10
12
10
12
14
HUB_DP1_P0_R
HUB_DP1_N0_R
EMC@ R260 1
EMC@ R261 1
2 33_0402_5% HUB_DP1_P0_C
2 33_0402_5% HUB_DP1_N0_C
C294 2
C296 2
1 0.1U_0402_25V6
1 0.1U_0402_25V6 HUB_DP1_P0
HUB_DP1_N0
<24>
<24>
C297 2 1 0.1U_0402_25V6 HUB_DP0_P1_C EMC@ R253 1 2 33_0402_5% HUB_DP0_P1_R 15 13 14 16 HUB_DP1_P1_R EMC@ R254 1 2 33_0402_5% HUB_DP1_P1_C C298 2 1 0.1U_0402_25V6
D <24> HUB_DP0_P1 HUB_DP0_N1_C 2 33_0402_5% HUB_DP0_N1_R 15 16 HUB_DP1_N1_R 2 33_0402_5% HUB_DP1_N1_C HUB_DP1_P1 <24> D
C299 2 1 0.1U_0402_25V6 EMC@ R255 1 17 18 EMC@ R256 1 C303 2 1 0.1U_0402_25V6
<24> HUB_DP0_N1 19 17 18 20 HUB_DP1_N1 <24>
<24> HUB_DP0_P2 HUB_DP0_N2_C 2 33_0402_5% HUB_DP0_N2_R 21 22 HUB_DP1_N2_R 2 33_0402_5% HUB_DP1_N2_C HUB_DP1_P2 <24>
C306 2 1 0.1U_0402_25V6 EMC@ R263 1 23 24 EMC@ R264 1 C307 2 1 0.1U_0402_25V6
<24> HUB_DP0_N2 25 23 24 26 HUB_DP1_N2 <24>
<24> HUB_DP0_P3 HUB_DP0_N3_C 2 33_0402_5% HUB_DP0_N3_R 27 28 HUB_DP1_N3_R 2 33_0402_5% HUB_DP1_N3_C HUB_DP1_P3 <24>
C301 2 1 0.1U_0402_25V6 EMC@ R266 1 29 30 EMC@ R267 1 C309 2 1 0.1U_0402_25V6
<24> HUB_DP0_N3 31 29 30 32 HUB_DP1_N3 <24>
33 31 32 34
<25> HUB_SW1_AUXP 35 33 34 36 HUB_SW2_AUXP <25>
<25> HUB_SW1_AUXN 37 35 36 38 HUB_SW2_AUXN <25>
HUB_DP0_HPD 39 37 38 40 HUB_DP1_HPD
<24> HUB_DP0_HPD 39 40 HUB_DP1_HPD <24>
0.033U_0402_16V7K
41 42
+NBDOCK_DC_IN_SS 41 42 ACAV_DOCK_SRC# <52>
0.033U_0402_16V7K
43 44
43 44
1
45 46
@EMC@
<25> SW2_VGA2_BLUE 45 46 SW2_VGA2_SDA <25>
@EMC@
1
C311
47 48
C310
49 47 48 50 SW2_VGA2_SCL <25>
2
51 49 50 52
2
53 51 52 54 SATA_PRX_C_DTX_P1 2 1
Close to DOCK <25> SW2_VGA2_RED 53 54 SATA_PRX_DTX_P1 <10> Close to DOCK
55 56 SATA_PRX_C_DTX_N1 C312 2 1 0.01UF_0402_25V7K
Its for Enhance ESD on 57 55 56 58 C313 0.01UF_0402_25V7K
SATA_PRX_DTX_N1 <10> Its for Enhance ESD on dock
dock issue. 59 57 58 60 SATA_PTX_C_DRX_P1 1 2 issue.
<25> SW2_VGA2_GREEN 61 59 60 62 SATA_PTX_C_DRX_N1 C314 1 2 0.01UF_0402_25V7K SATA_PTX_DRX_P1 <10>
63 61 62 64 C315 0.01UF_0402_25V7K SATA_PTX_DRX_N1 <10>
65 63 64 66
<25> SW2_VGA2_HSYNC 67 65 66 68 USB20_P6 <10>
HUB_DP0_HPD <25> SW2_VGA2_VSYNC 69 67 68 70 USB20_N6 <10>
71 69 70 72
<32> CLK_MSE 73 71 72 74 USB20_P5 <10>
<32> DAT_MSE 75 73 74 76 USB20_N5 <10>
75 76
1
100K_0402_5%
77 78
<30> DAI_BCLK# 79 77 78 80 CLK_KBD <32>
<30> DAI_LRCK# 79 80 DAT_KBD <32>
R268
C 81 82 C
83 81 82 84
<30> DAI_DI 85 83 84 86 USB3_PRX_DTX_N2 <10>
<30> DAI_DO# USB3_PRX_DTX_P2 <10>
2
87 85 86 88
87 88 EMI solution for E-Docking USB
89 90
<30> DAI_12MHZ# 91 89 90 92 USB3_PTX_DRX_N2 <10>
93 91 92 94 USB3_PTX_DRX_P2 <10> HUB_DP1_HPD
95 93 94 96
97 95 96 98
<31> D_LAD0 97 98 BREATH_LED# <32,40>
100K_0402_5%
99 100
<31> D_LAD1 99 100 SW_LAN1_ACTLED_YEL# <27>
1
101 102
101 102
R271
103 104
<31> D_LAD2 105 103 104 106 SW_LAN1_MDIP0 <27>
<31> D_LAD3 107 105 106 108 SW_LAN1_MDIN0 <27>
109 107 108 110
<31> D_LFRAME#
2
111 109 110 112 SW_LAN1_MDIP1 <27> +3.3V_ALW2
<31> D_CLKRUN# 113 111 112 114 SW_LAN1_MDIN1 <27> +LOM_VCT
115 113 114 116
<31> D_SERIRQ 115 116 DOCK_DET#
1U_0402_6.3V6K
117 118 1 2
<31> D_DLDRQ1# 117 118 +LOM_VCT
119 120 100K_0402_5% R272
119 120
@ C316
121 122
<8> CLK_PCI_DOCK 123 121 122 124 SW_LAN1_MDIP2 <27>
125 123 124 126 SW_LAN1_MDIN2 <27>
2
127 125 126 128
<32> DOCK_SMB_CLK 129 127 128 130 SW_LAN1_MDIP3 <27>
<32> DOCK_SMB_DAT 131 129 130 132 SW_LAN1_MDIN3 <27>
133 131 132 134
<31,43> DOCK_SMB_ALERT# 135 133 134 136 DOCK_DCIN_IS+ <51>
<43> DOCK_PSID 137 135 136 138 DOCK_DCIN_IS- <51>
139 137 138 140
<32> DOCK_PWR_BTN# 141 139 140 142 DOCK_POR_RST# <32>
D19
SLICE_BAT_PRES# 143 141 142 144 DOCK_DET_R# 1 2
B <31,43,52> SLICE_BAT_PRES# 143 144 DOCK_DET# <31,52> B
145 149 RB751S40T1G_SOD523-2
146 GND1 PWR2 150
+DOCK_PWR_BAR PWR1 PWR2 +DOCK_PWR_BAR
147 151
PWR1 PWR2
3
2
4.7U_0805_25V6-K
0.1U_0603_50V7K
L30ESD24VC3-2_SOT23-3
148 152
PWR1 GND2
0.1U_0603_50V7K
1
D20 @EMC@
C318
153 159
Shield_G Shield_G
1
1
@ C33
C317
154 160
155 Shield_G Shield_G 161
2
2

Shield_G Shield_G DAI_12MHZ# DAI_BCLK# CLK_PCI_DOCK
1
10_0402_5%
10_0402_5%
10_0402_5%
JAE_WD2F144WB5R400
EMC@
EMC@
R273
EMC@
R41
R6
LINK JAE_WD2F144WB5R400 DONE
2
4.7P_0402_50V8C
4.7P_0402_50V8C
4.7P_0402_50V8C
1
1
C43
EMC@
C42
EMC@
C319
EMC@
2
2
EMI depop location
A A
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT E-Dock
5 4 3 2 1
5 4 3 2 1
Touch Pad +3.3V_RUN +3.3V_TP
PJP16
1 2
+3.3V_TP
Vinafix.com PAD-OPEN1x1m
4.7K_0402_5%
4.7K_0402_5%
1
1
D D
RZ18
RZ19
2
2
2 1 DAT_TP_SIO_R
<32> DAT_TP_SIO @ RZ22 0_0402_5%
<32> CLK_TP_SIO @
2
RZ23
1 CLK_TP_SIO_R
0_0402_5% Keyboard CONN@
JKBTP1
330P_0402_50V8J
330P_0402_50V8J
1
<9> KB_DET# 1
1
2
2
CZ30
EMC@
CZ31
EMC@
3
4 3
2
5 4
+5V_RUN 5
6
+3.3V_ALW 6 +3.3V_TP +3.3V_ALW +5V_RUN
7
<32> BC_INT#_ECE1117 8 7
<32> BC_DAT_ECE1117 9 8
10 9
<32> BC_CLK_ECE1117 10
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
EMI depop location 11 1 1 1
11
@
12
+3.3V_TP DAT_TP_SIO_R 12
CZ27
CZ28
CZ29
13
+3.3V_TP +3.3V_TP CLK_TP_SIO_R 14 13
15 14 2 2 2
16 15
<12> TOUCHPAD_INTR# 16
10K_0402_5%
10K_0402_5%
17
17
1
1
I2C_1_SDA_R
4.7K_0402_5%
4.7K_0402_5%
18
18
1
I2C_1_SCL_R
RZ21
RZ116
RZ117
19
19
RZ20
20
C Reserve for future use 21 20 Place close to JKBTP1 C
22 GND1
2
2
GND2
2
ACES_50506-02041-P01
2 1 I2C_1_SDA_R
<9> I2C_1_SDA @ RZ26 0_0402_5%
2 1 I2C_1_SCL_R
<9> I2C_1_SCL @ RZ29 0_0402_5% Link 50506-02041-P0 DONE
Reserve for future use
@ eDP Cable W CAM

@ LED FFC
DC02C007600 H-CONN SET 13D MB-EDP-CAMERA
NBX0001JG00 FFC 10P F P0.5 PAD0.3 172MM MB-LED/B 13D
@ eDP TS Cable W CAM
@ FP FFC
DC02C007C00 H-CONN SET 13D MB-EDP-CAMERA-TS
NBX0001JK00 FFC 8P F P0.5 PAD.3 123MM MB-FP VALIDITY
@ eDP Cable W/O CAM
@ TP FFC
DC02C007D00 H-CONN SET 13D MB-EDP
NBX0001JI00 FFC 16P F P0.5 PAD=0.3 119MM MB-TP 13D
B @ SATA SPINDLE Cable B
@ USH Board FFC
DC02C007500 H-CONN SET 13D MB-SPINDLE HDD
NBX0001JJ00 FFC 26P G P0.5 PAD.3 88MM MB-USH/B 13D
RSMRST circuit +3.3V_ALW

@ SATA Cable
Part Number Description @ RTC BATT
@ CZ34
1 2 DC02C007400 H-CONN SET 13D MB-MSATA HDD Part Number Description
GC02001DS00 BATT CR2032 3V 225MAH PA 5 W/C 30MM
0.1U_0201_10V6K @ DC-IN Cable
5
Part Number Description @ FAN

1
P
<32> PCH_RSMRST# B DC30100Q100 CONN SET 13F DCJACK-MB 2DW1003-041110F Part Number Description
4
O PCH_RSMRST#_Q <11,14>
2 DC28A000800 FAN SET DAQ20 DC5V AB7405HB-HB3 ADDA
<44> ALW_PWRGD_3V_5V A
G
@ BATT Cable
UZ6
3
TC7SH08FU_SSOP5~D Part Number Description @ Speak

DC02001X800 H-CONN SET 13D MB-BATT CABLE Part Number Description
PK230003Q0L SPK PACK ZJX 2.0W 4 OHM FG
A A
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Keyboard
5 4 3 2 1
5 4 3 2 1
HDD LED solution for White LED Battery LED

+3.3V_ALW
1
10K_0402_5%
SATA_LED
RZ24
3
Vinafix.com
2
QZ3B QZ3A
DMN65D8LDW-7_SOT363-6 DZ3 DMN65D8LDW-7_SOT363-6 1 2 BATT_WHITE#
4 3 1 2 1 6 SATA_LED# 2 <32> BAT2_LED#
RZ25 220_0402_5%
<10,35> PCH_SATA_LED#
RB751S40T1G_SOD523-2 QZ4 1 2 BATT_YELLOW#
D DDTA114EUA-7-F_SOT323-3 <32> BAT1_LED# D
RZ28 330_0402_5%
2
<31> MASK_SATA_LED#
1
DZ4
1 2
<31> LED_SATA_DIAG_OUT# SYS_LED_MASK# 1 2
RB751S40T1G_SOD523-2 RZ27 220_0402_5%
LED P/N change to SC50000FL00 from SC50000BA00
Breath LED
C +5V_ALW C
QZ7B LED3
DMN65D8LDW-7_SOT363-6 LTW-C193DC-C_WHITE
4 3 BREATH_LED#_Q 1 2 BREATH_WHITE_LED_SNIFF# 1 2
<32,38> BREATH_LED#
RZ32 150_0402_5%
Place LED3 close to SW3
5
MASK_BASE_LEDS#
1 2 BREATH_WHITE_LED#
RZ34 220_0402_5%
+3.3V_ALW
@ CZ48
1 2
0.1U_0201_10V6K LED board CONN

5
1
P
<27,31> SYS_LED_MASK# B 4 MASK_BASE_LEDS#

2 O +5V_ALW
<31,40> LID_CL# A JLED1 CONN@
G
UZ10
TC7SH08FU_SSOP5~D 1
3
BREATH_WHITE_LED# 2 1
SATA_LED 3 2
BATT_YELLOW# 4 3
BATT_WHITE# 5 4
6 5
B
7 6 B
<31,40> LID_CL# 8 7
+3.3V_ALW
POWER & INSTANT ON SWITCH 9
10
8
GND1
GND2
ACES_50506-00841-P01
2 SW3 1
<11,32> POWER_SW#_MB
4 3
SKRBAAE010_4P
LED Circuit Control Table

Fiducial Mark
@ FD1
1 SYS_LED_MASK# LID_CL#
FIDUCIAL MARK~D
@ FD2
Mask All LEDs (Unobtrusive mode) 0 X
1
A
Mask Base MB LEDs (Lid Closed) 1 0 A
FIDUCIAL MARK~D
Do not Mask LEDs (Lid Opened) 1 1
@ FD3
1
FIDUCIAL MARK~D CPU NGFF

@ FD4 @ H1 @ H2 @ H3 @ H4 @ H6 @ H7 @ H8 @ H9 @ H10 @ H11 @ H12 @ H13 @ H14 @ H15 @ H16 @ H17 @ H19 @ H18 @ H21 @ H20 @ H23 @ H22 @ H24 @ H25
1 H3P8 H3P8 H3P8 H3P8
@ H5
H_2P6N H_3P0X2P0N H_3P2 H_3P2 H_0P9N H_0P8N H_2P4 H_2P4 H_2P4 H_2P4 H_2P4 H_2P4 H_2P4 H_2P4 H_2P4 H_2P4 H_2P4 H_3P3 H_2P4 H_2P4 H_3P8 DELL CONFIDENTIAL/PROPRIETARY
FIDUCIAL MARK~D
1
1
1
1
1
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT PAD, LED
5 4 3 2 1
5 4 3 2 1
+3.3V_WWAN/+3.3V_LAN source PJP23 2.5A

+3.3V_M source
1 2
+3.3V_ALW +3.3V_WWAN
PJP20 0.013A
Vinafix.com
1 2 +3.3V_M
PAD-OPEN1x3m +3.3V_ALW UZ8 @
UZ2
1 14 +3.3V_WWAN_UZ2 1 2 PAD-OPEN1x1m
2 VIN1 VOUT1 13 @ CZ39 0.1U_0201_10V6K 1 7
D VIN1 VOUT1 2 VIN VOUT 8 +3.3V_M_UZ8 1 2 D
3.3V_WWAN_EN 3 12 1 2 VIN VOUT @ CZ43 0.1U_0201_10V6K
<31> 3.3V_WWAN_EN ON1 CT1 CZ38 470P_0402_50V7K 3 6 1 2
<32> A_ON ON CT
+5V_ALW 4 11 @ CZ42 470P_0402_50V7K
VBIAS GND
5 10 1 2 +5V_ALW 4
<11,32> SIO_SLP_LAN# ON2 CT2 VBIAS
CZ23 470P_0402_50V7K 5
6 9 GND 9
7 VIN2 VOUT2 8 +3.3V_LAN_UZ2 1 2 GND
VIN2 VOUT2 @ CZ50 0.1U_0201_10V6K
15
GPAD PJP13 AOZ1336_DFN8_2X2
EM5209VF_SON14_2X3 1 2 +3.3V_LAN
1 2 3.3V_WWAN_EN
RZ40 100K_0402_5% PAD-OPEN1x1m 1A
+3.3V_WLAN/+3.3V_RUN source +5V_RUN/+3.3V_ALW_PCH source

1 2 AUX_EN_WOWL
RZ38 100K_0402_5%
PJP21 2A
C 1 2 C
3.435A +5V_RUN
PJP22 +5V_ALW
1 2 UZ4 PAD-OPEN1x2m
+3.3V_ALW +3.3V_RUN
1 14 1 2
UZ3 2 VIN1 VOUT1 13 +5V_RUN_UZ4 @ CZ44 0.1U_0201_10V6K
1 14 +3.3V_RUN_UZ3 PAD-OPEN1x3m VIN1 VOUT1
2 VIN1 VOUT1 13 1 2 3 12 1 2
VIN1 VOUT1 @ CZ47
<32,47> RUN_ON ON1 CT1
0.1U_0201_10V6K CZ45 470P_0402_50V7K
RUN_ON 3 12 1 2 4 11
ON1 CT1 CZ46 470P_0402_50V7K VBIAS GND
+5V_ALW 4 11 @ RZ65 1 2 0_0402_5% 5 10 1 2
VBIAS GND <32> PCH_ALW_ON ON2 CT2
1 2 CZ69 470P_0402_50V7K
<8,11,17,18,32,46,47,48> SIO_SLP_SUS#
5 10 1 2 @ RZ64
+3.3V_ALW 0_0402_5% 6 9 1 2
ON2 CT2 CZ37 470P_0402_50V7K 7 VIN2 VOUT2 8 +3.3V_ALW_PCH_UZ24 @ CZ64 0.1U_0201_10V6K
1 2 6 9 +3.3V_WLAN_UZ3 1 2 VIN2 VOUT2
<11,31> SIO_SLP_WLAN# VIN2 VOUT2 @ CZ36
@ RZ71 0_0402_5% 7 8 0.1U_0201_10V6K 15
1 2 VIN2 VOUT2 GPAD PJP19
<31> AUX_EN_WOWL @ RZ70 0_0402_5% 15 PJP12 EM5209VF_SON14_2X3 1 2 0.63A
+3.3V_ALW_PCH
GPAD 1 2 +3.3V_WLAN
EM5209VF_SON14_2X3
PAD-OPEN1x2m PAD-OPEN1x1m
SWAP for BC12 layout routing 2A
B B
A A
Power control
5 4 3 2 1
5 4 3 2 1
pin 3 pin 6 pin 13 pin 16 pin 18 +3.3V_HDD +5V_HDD

+3.3V_HDD
Pericom NC NC
1
100K_0402_5%
TDet_B# TDet_A# TDeT_EN
@ RN1
+3.3V_RUN
GND DEW2 GND DEW1 GND
1
4.7K_0402_5%
X76@RN8
4.7K_0402_5%
X76@RN10
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
TI
0.01UF_0402_25V7K
0.1U_0201_10V6K
@ RN12
@ RN14
@ RN18
@ RN20
@ RN22
@ RN84
2
GND REXT
1
DEW
100K_0402_5%
1 1
Parade B_EQ2 A_EQ2
Vinafix.com
SATA Repeater
FFS_INT2_Q
RN2
2
3
CN46
CN49
2 2
2
HDD_A_PRE
QN1B
D UN7 X76@ D
DEW2 6 10 5
DEW1 16 NC VDD 20 HDD_B_PRE
NC VDD
4
6
3 13 HDD_B_EQ2 HDD_A_EQ
HDD_A_EQ 17 TDet_B# TDet_A# 19 HDD_B_EQ
HDD_A_PRE A_EQ B_EQ HDD_B_PRE HDD_B_EQ
QN1A
9 8
7 A_EM B_EM 18 HDD_A_EQ2 FFS_INT2 2
EN TDeT_EN DEW2 <8> FFS_INT2
CN47 1 SATA_PTX_C_RD_DRX_P0 1
2 0.01UF_0402_25V7K 15 SATA_PTX_RD_DRX_P0
<10> SATA_PTX_DRX_P0
1
CN50 1 SATA_PTX_C_RD_DRX_N0 2
2 0.01UF_0402_25V7K AI+ AO+ 14 SATA_PTX_RD_DRX_N0 DEW1
<10> SATA_PTX_DRX_N0 AI- AO-
CN45 1 SATA_PRX_C_RD_DTX_N0 4
2 0.01UF_0402_25V7K 12 SATA_PRX_RD_DTX_N0 HDD_B_EQ2
<10> SATA_PRX_DTX_N0 BO- BI-
CN48 1 SATA_PRX_C_RD_DTX_P0 5
2 0.01UF_0402_25V7K 11 SATA_PRX_RD_DTX_P0
<10> SATA_PRX_DTX_P0 BO+ BI+ HDD_A_EQ2
21
GND
1
4.7K_0402_5%
4.7K_0402_5%
X76@RN11
4.7K_0402_5%
X76@RN13
4.7K_0402_5%
X76@RN16
7.87K_0402_1%
X76@RN19
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
@ RN9
@ RN21
PI3EQX6741STZDEX_TQFN20_4X4
RN23
RN83
HDD_A_EQ HDD_B_EQ HDD_A_EQ2 HDD_B_EQ2 DEW1 DEW2 HDD_A_PRE HDD_B_PRE
2
PIN17 PIN19 PIN18 PIN13 PIN16 PIN6 PIN9 PIN8
Pericom PI3EQX6741ST NC PD PD PD NC NC NC PD
(RN16) (RN83) (RN23) (IPU) (RN11) +3.3V_RUN
TI SN75LVCP601 PD NC PD PD NC NC PH PH
(RN13) (RN83) (RN23) (IPU) (IPU) (RN8) (RN10)
10U_0603_10V6M
0.1U_0201_10V6K
C C
Parade PS8527C PD PD PD PD NC PD NC NC
Free Fall Sensor
1
(RN16) (RN83) (RN23) (1/2 VDD) (RN19) (1/2 VDD) (1/2 VDD)
(RN13)
CN1
CN2
2
2
UN1
LNG2DM
A_EQ B_EQ A_EM B_EM 10 5
9 VDD_IO RES
VDD 12
INT 1 FFS_INT2 HDD_FALL_INT <10>
3 11
0 3dB 3dB 0 0dB 0dB 4 SDO/SA0 INT 2
<8,14,20,21> DDR_XDP_WAN_SMBDAT SDA/SDI/SDO
1 6
Main Pericom NC 6dB 6dB NC <8,14,20,21> DDR_XDP_WAN_SMBCLK SCL/SPC GND 7
2 GND 8
1 9dB 9dB 1 1.5dB 1.5dB CS GND
LNG2DMTR_LGA12_2X2
0 7dB 7dB 0 0dB 0dB
2nd TI NC 0dB 0dB NC -4dB -4dB
1 14dB 14dB 1 -2dB -2dB
+3.3V_HDD
EQ2 EQ1 A_EQ B_EQ A_EM B_EM 1 2 HDD_DEVSLP

@ RN5 10K_0402_5%
(M = VDD/2)
B JSATA1CONN@ B
0 M 2.4dB 2.4dB 1
SATA_PTX_RD_DRX_P0 CN43 2 1 0.01UF_0402_25V7K SATA_PTX_C_DRX_P0 2 1
0 0 7.4dB 7.4dB SATA_PTX_RD_DRX_N0 CN44 2 1 0.01UF_0402_25V7K SATA_PTX_C_DRX_N0 3 2
3rd Parade 14.4dB 14.4dB 4 3
0 1 0 0dB 0dB SATA_PRX_RD_DTX_N0 CN18 2 1 0.01UF_0402_25V7K SATA_PRX_C_DTX_N0 5 4
5
M M 12.2dB 12.2dB M -3.5dB -3.5dB SATA_PRX_RD_DTX_P0 CN17 2 1 0.01UF_0402_25V7K SATA_PRX_C_DTX_P0 6
7 6
PJP36 8 7
M 0 9.4dB 9.4dB 1 -1.5dB -1.5dB 1 2 +3.3V_HDD 9 8
+3.3V_RUN 9
M 1 13.3dB 13.3dB 10
11 10
PAD-OPEN1x2m
<10> HDD_DEVSLP 12 11
1 M 6.2dB 6.2dB * red color is current setting 13 12
<10> HDD_DET# 13
1 0 11.2dB 11.2dB 14
15 14
+5V_HDD +3.3V_HDD
16 15
1 1 5dB 5dB +5V_HDD
17 16
18 17
FFS_INT2_Q 18
1000P_0402_50V7K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
19
+5V_RUN +5V_HDD 20 19
20
1
+3.3V_ALW
CN13
CN14
@ CN15
CN16
@ PJP1603 21
2 1 22 G1
23 G2
+5V_HDD source
2
2
24 G3
PAD-OPEN1x1m G4
1
@ RN6 PJP805
10K_0402_5% 1 2 1.5A+5V_HDD STARC_115B20-100020-G2-R
+5V_ALW UZ23
PAD-OPEN1x1m
2
1 7
HDD_EN 2 VIN VOUT 8 +5V_HDD_UZ2 1 2
A VIN VOUT @ CZ99 0.1U_0201_10V6K A
3 6 1 2
Place near HDD CONN
<9> HDD_EN ON CT CZ100 470P_0402_50V7K
1
@ RN7 4
10K_0402_5%
VBIAS
GND
5
9
GND
2
AOZ1336_DFN8_2X2
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT HDD CONN
5 4 3 2 1
5 4 3 2 1
+COINCELL
COIN RTC Battery
2200P_0402_50V7K
1
PR2
1
@EMC@ PC8
1K_0402_5%
+3.3V_RTC_LDO
+Z4012 2
2
Vinafix.com +COINCELL
@ JRTC1
1
2 1 G 4
3
2 G
D D
ACES_50271-0020N-001
2
+RTC_CELL
1
EMC@ PD2 EMC@ PD3
TVNST52302AB0_SOT523-3 TVNST52302AB0_SOT523-3 EMC@ PL2 PD1
1
FBMJ4516HS720NT_2P
+3.3V_ALW BAS40CW SOT-323 1
1 2 PC2
3
Primary Battery Connector 1U_0603_25V6K
EMC@ PL3
1
FBMJ4516HS720NT_2P 2
PBATT+_C 1 2 +PBATT
@PBATT1 PR3
1
1 2 100K_0402_5%
2
2 3 PRP1
3 4 PBAT_SMBCLK_C 8 1
2200P_0402_50V7K
4 5 PBAT_SMBDAT_C 7 2
5 PBAT_PRES#_C PBAT_SMBDAT <32>
6 6 3
6 PBAT_SMBCLK <32> PBAT_PRES# <32,51,52>
1
EMC@ PC3
7 5 4
7 8
8 9 100_0804_8P4R_5% PQ2
2
9 10
10 DMG2301U-7 1P SOT23-3
11 PD4
GND 12 1 2 1 3
3
GND DOCK_SMB_ALERT# <31,38>
DEREN_40-42251-01001RHF SDMK0340L-7-F_SOD323-2~D
2
2
PR4
GND 1 2
<31,38,52> SLICE_BAT_PRES#
0_0402_5%~D
1
PC4
C C
1500P_0402_50V7K
2
<38> DOCK_PSID
PESD5V0U2BT_SOT23-3
PD7 EMC@
+3.3V_ALW
1
@ PR5 PU1
2
1 2 1 6
NO IN GPIO_PSID_SELECT <31>
0_0402_5%
PR6
2 5
EMC@ PL4 PR7
2.2K_0402_5% GND V+ +5V_ALW
1
BLM15AG102SN1D_2P 33_0402_5%
NB_PSID 2 1 1 3 1 2 NB_PSID_TS5A63157 3 4
D
S
NC COM PS_ID <32>
PQ3 TS5A63157DCKR_SC70-6~D
2
FDV301N-G_SOT23-3 +5V_ALW
G
2
PR8
100K_0402_1%
3
PD6 EMC@
1
1
B B
PESD5V0U2BT_SOT23-3 C
2 PQ4 PR9
B MMST3904-7-F_SOT323~D 10K_0402_1%
E
1
3
2
2
PR10
@ PR11
15K_0402_1%
1 2
PSID_DISABLE# <31>
1
10K_0402_5%
DC_IN+ Source
+DC_IN +DC_IN_SS
PQ5
S TR AON7401 1P DFN
DCX124EK-7-F PNP/NPN_SC74-6~D
1
EMC@ PL1 2
FBMJ4516HS720NT_2P 3 5
1 2
3
1
1M_0402_5%
0.022U_0805_50V7K
4
2
PQ1B
@
PR1
PC5
10U_0805_25V6K
100K_0402_5%
1
2
1
PC7
1000P_0603_50V7K
2
1
PR12
PR14
0.1U_0603_25V7K
4.7K_0805_5%
1
1 2
@ PJPDC1 SOFT_START_GC <52>
2
1
EMC@ PC1
PC6
2
1 -DCIN_JACK 10K_0402_5%
PR13
1
1
2
2
2 3 +DCIN_JACK 5
@EMC@
AC_DIS <31,51,52>
2
3 4
A PR15 A
@
4
@
5 PQ1A
5 1M_0402_5%
2
ACES_50290-0050N-001 DCX124EK-7-F PNP/NPN_SC74-6~D

6
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D +DCIN
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Size Document Number Rev
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 1.0
LA-C631P, C641P
5 4 3 2 1
A B C D E
+3.3V_ALW
@ PC101
0.1U_0402_10V7K
1 2 0_0402_5%~D
PR119
1 2
5
@ PR101
PGOOD_3V 1 0_0402_5%
P
Vinafix.com PGOOD_5V 2
B
A
O
4 1 2 ALW_PWRGD_3V_5V <39>
G
PR120
@ PU101
3
1 TC7SH08FU_SSOP5~D 1 2 1
0_0402_5%~D
PR102
499K_0402_1%
+PWR_SRC ENLDO_3V5V 1 2
PR100
+PWR_SRC
PJP100 PC102
1
499K_0402_1%
1 2 3V_VIN BST_3V1 2 1 2
PR103
PAD-OPEN 1x2m~D 0.1U_0603_25V7K
0_0603_5%~D
2200P_0402_50V7K
1
PU100
2
10U_0805_25V6K
10U_0805_25V6K
@EMC@ PC100
@EMC@ PC103
0.1U_0402_25V6
BS
IN
IN
IN
IN
1
1
LX_3V 6
PC105
@ PC104
20 PL100
LX LX 1.5UH_PCMC063T-1R5MN_9A_20%
2
7 19 LX_3V 1 2
GND LX +3.3V_ALWP
@EMC@ PR106
8 SY8288BRAC QFN 20P PWM 18 PR104
GND GND
4.7_1206_5%
0_0402_5%~D
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
9 17 1 2
PG LDO +3.3V_ALW2
1
Update PH401 change
PC106
PC107
PC108
PC109
@ PC110
10 16
NC NC 1 2
to Common Part
+3.3V_RTC_LDO 3VALWP
OUT
2
EN2
EN1
21 SH000016800 20141202
NC
FF
GND PR105 TDC 7.087 A
1 3V_SN 2
PR107 0_0402_5%~D
Peak Current 8.504 A
11
12
13
14
15
680P_0603_50V7K
100K_0402_5% 3.3V LDO 150mA~300mA
@EMC@ PC112
1 2
+3.3V_ALW OCP Current 9 A fix by IC
1
ENLDO_3V5V
2 PC111 2
4.7U_0603_6.3V6K
Vout is 3.234V~3.366V
2
PGOOD_3V
PJP102
150K_0402_1%
PC113 PR108 +3.3V_ALWP 1 2 +3.3V_ALW
1 2
1
@ PR109
1000P_0402_50V7K 1K_0402_5%
3V5V_EN 3V_FB 1 2 1 2 JUMP_43X118
2
+PWR_SRC
1
150K_0402_1%
PJP103
@ PR110
+5V_ALWP 1 2 +5V_ALW
PJP101 PR111 1 2
PC114
1 2 5V_VIN BST_5V 1 2 1 2 JUMP_43X118
2
PAD-OPEN 1x2m~D 0.1U_0603_25V7K
0_0603_5%~D
2200P_0402_50V7K
1
10U_0805_25V6K
10U_0805_25V6K
@EMC@ PC115
@EMC@ PC116
0.1U_0402_25V6
PU102
1
BS
IN
IN
IN
IN
PC117
PC118
LX_5V 6 20 PL101
2
LX LX 2.2UH +-20% 7.8A 7X7X3 MOLDING

7 19 LX_5V 1 2
GND LX +5V_ALWP
8 SY8286CRAC_QFN20_3X3 18
GND GND
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
PR112
680P_0603_50V7K 4.7_1206_5%
3 PC119 3
1
@EMC@
9 17 1 2
PC120
PC121
PC122
PC123
@ PC124
PG VCC
Update PH401 change
10 16
to Common Part
2
NC NC 4.7U_0603_6.3V6K
15V_SN
OUT
LDO
2
EN2
EN1
21 SH000016800 20141202
FF
GND
11
12
13
14
15
PC125
PR113
+5V_ALW2
@EMC@
100K_0402_5%
2
1 2
+3.3V_ALW
ENLDO_3V5V
5V LDO 150mA~300mA
3V5V_EN
PGOOD_5V
PC126
4.7U_0603_6.3V6K
PR114
5VALWP
2
150K_0402_1%
1 2
<32> ALWON
TDC 4.5 A
1
@ PR115
0_0402_5%~D Peak Current 6.3 A
3V5V_EN OCP Current 9 A fix by IC
2
1M_0402_1%
4.7U_0402_6.3V6M
1
1
150K_0402_1%
PR116
PC128
PC127 PR117
@ PR118
1000P_0402_50V7K 1K_0402_5%
5V_FB 1 2 1 2
2
2
2
EN1 and EN2 dont't floating
4 4
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL +5V_ALW/3.3V_ALW
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C631P, C641P
A B C D E
5 4 3 2 1
0.6Volt +/- 5%
TDC 0.7 A
Peak Current 1.0 A
Vinafix.com OCP Current 2.6 A fix by IC
D D
+PWR_SRC PJP202
1 2 1.2V_B+
PJP203
PR202
PAD-OPEN 1x2m~D 1 2 BOOT_1.2V +VLDOIN_1.2V 1 2 +1.2V_MEN_P
2.2_0603_5%
2200P_0402_50V7K
0.1U_0402_25V6
PAD-OPEN1x1m
10U_0805_25V6K
10U_0805_25V6K
+0.6V_P
0.22U_0603_16V7K
DH_1.2V
1
PC201
PC202
@EMC@ PC203
@EMC@ PC204
22U_0603_6.3V6M
PC205
1
SW _1.2V
2
2
@
1
DL_1.2V
PC206
16
17
18
19
20
PU201
VLDOIN
PHASE
UGATE
BOOT
VTT
2
21
PAD
15 1
+1.2V_MEN_P Footprint use AON6932A LGATE VTTGND
PR203 14 2
For RT8207P PGND VTTSNS +V_DDR_REF
7
PL201 PQ201 5.1K_0402_1%
1UH_PCMB063T-1R0MS_12A_20% AON6994 2N DFN5X6D 1 2 CS_1.2V
D1
G1
S1/D2
1 2 13 3
PC207 CS RT8207PGQW_WQFN20_3X3 GND
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1U_0603_10V6K
1
12 4 +V_DDR_REF
G2
4.7_1206_5%
S2
S2
S2
VDDP VTTREF
@EMC@ PR204
C C
PR205
+1.2V_MEN_P
3
6
1
VDD_1.2V
PC220
PC218
PC217
PC216
PC215
PC219
1 2 11 5
VDD VDDQ
PGOOD
5.1_0603_5%
2
TON
2
PC210
FB sense trace
FB
+5V_ALW
S5
S3
PC209
SNUB_1.2V
0.033U_0402_16V7K
when FB pull down to GND
1
1U_0603_10V6K
10
6
PR201
2.2_0603_5%
680P_0603_50V7K
PR206
2
1
@EMC@ PC211
12K_0402_1%
1.2V_FB 1 2
+5V_ALW
2
PC212
100P_0402_50V8J
For RT8207P 1 2
PR207
1.2V_B+ 1 2
PR208
S5_1.2V 453K_0402_1%
1 2
<11,17,32,54> SIO_SLP_S4#
1
0_0402_5%~D
1
PR209 @ PC213
20K_0402_1%
PR210 .1U_0402_16V7K
2
B 1 2 B
<20> 0.6V_DDR_VTT_ON
2
1
@ PC214
.1U_0402_16V7K 0_0402_5%~D
2
+1.2V_MEN_P
Mode S3 S5 +1.2V_MEN +V_DDR_REF +0.6V_P
S5 L L off off off
S3 L H on on off FB sense trace
S0 H H on on on
+1.2V_MEM
TDC 8.75 A
Peak Current 12.25 A
OCP Current 14.7 A PJP204
TYP MAX 1
1 2
2
H/S Rds(on) 6.7mohm , 8.5mohm JUMP_1x3m
L/S Rds(on) 2.4mohm , 3.2mohm
A
Choke DCR 3.0mohm , 3.5mohm PJP201
PJP205 A
CAP ESR 11mohm +1.2V_MEN_P 1 2

+1.2V_MEM +0.6V_P 1 2 +0.6V_DDR_VTT
1 2 DELL CONFIDENTIAL/PROPRIETARY
JUMP_1x3m PAD-OPEN1x1m

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL +1.2V_MEN/+0.6V_DDR_VTT
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
PR312
1 2
SIO_SLP_SUS# <8,11,17,18,32,41,47,48>
0_0402_5%~D
EN_+1VALWP
1
1M_0402_1%
PR302 PJP302
+1VALWP 1 2 +1.0V_PRIM
2
1 2
JUMP_43X118
@EMC@ PR303 @EMC@ PC302

4.7_1206_5% 680P_0603_50V7K
2 SNB_+1VALWP 1
+PWR_SRC PJP301 PU301
1 2
1 2 2200P_0402_50V7K +1VALW P_B+ 8 1

0.1U_0402_25V6
PC304
IN EN PR304
10U_0805_25V6K
10U_0805_25V6K
0.1U_0603_25V7K
PAD-OPEN 1x2m~D 6 BST_+1VALWP 1 2BST_+1VALWP_C
1 2 PL301
BS
1
1
@ PC305
PC306
0.68UH_MMD-05CZ-R68M-X2L_8.5A_20%
SW_+1VALWP +1VALWP
@EMC@ PC301
@EMC@ PC303
C 9 10 1 2 C
GND LX 0_0603_5%~D
2
47U_0805_6.3V6M
47U_0805_6.3V6M
22U_0805_6.3VAM
22U_0805_6.3VAM
330P_0402_50V7K
1
1
4 FB_+1VALWP
FB
PC307
PC308
@ PC309
PC310
PC311
6.65K_0402_1%
1
ILMT_+1VALWP 3 7
+3.3V_ALW
2
ILMT BYP
PR306
4.7U_0603_6.3V6K
+3.3V_ALW 2 5
4.7U_0603_6.3V6K
PG LDO
1
1K_0402_5%
PC312
1
PC313
PR308
SYX196DQNC_QFN10_3X3
2
1
2
2
@ PR307
2
0_0402_5%
2
ILMT_+1VALWP
1
1
PR311
10K_0402_1%
@ PR310
0_0402_5%
2
+1.0V_PRIM
2
TDC 5 A
Peak Current 7 A
OCP Current 9 A Fix by IC
B TYP MAX B
Choke DCR 11.0mohm , 12.0mohm
The current limit is set to 6A, 9A or 12A when this pin

is pull low, floating or pull high
A A
Title
+1VALWP
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
LA-C631P, C641P
5 4 3 2 1
5 4 3 2 1
+3.3V_ALW
1
@
PR425 PR404
<11,17,33,47> SIO_SLP_S0# 1 2 0_0402_5%
0_0402_5%
2
PR402
<32,41>
Vinafix.com
RUN_ON
1 2
EN_1VS_VCCIO
0.1U_0402_25V6
0_0402_5%~D
1
@ PC402
PR403
D 1M_0402_1% D
@ PJP401
2
JUMP_43X79
1 2
+1VS_VCCIOP +1.0VS_VCCIO
2
1 2
13
14
15
16
17
PU401
Vin=3~17V
TP
LPM
EN
PGND
PGND
@ PJP403
+5V_ALW 1 2 VIN_1VS_VCCIO 12
PVIN VOS
1
+1VS_VCCIOP
10U_0603_10V6M
10U_0603_10V6M
PL402
PAD-OPEN1x1m 1UH_1277AS-H-1R0N-P2_3.3A_30%
1
+3.3V_ALW LX_1VS_VCCIO
+1VS_VCCIOP
PC403
PC404
11 2 1 2
PVIN SW
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
2
2
S IC SY8057QDC QFN 16P PWM
1
PC406
PC407
PC422
10 3
AVIN SW
2
2200P_0402_50V7K
@
0.1U_0402_25V6
1
1
1SNUB_1VS_VCCIO
VID0_VCCIO 9 4
PC408
@EMC@ PC409
VID0 PG @EMC@ PR405
1
AGND
4.7_0603_5%
VID1
FBS
@ PR413 PR414 @EMC@
SS
2
10K_0402_1% 10K_0402_1%
2
5
VID0_VCCIO
@EMC@ PC401
VID1_VCCIO +1VS_VCCIOP
SS_1VS_VCCIO
VID1_VCCIO
100_0402_1%
470P_0402_50V7K
1
1
PR421
PR415 @ PR416
10K_0402_1% 10K_0402_1%
PR422
2
470P_0402_50V7K
C C
2
2
2 1
1
PR427 VCCIO_SENSE <17>
PC410
0_0402_5%~D
PR412 0_0402_5%~D +1.0VS_VCCIO
2
2 1 TDC 2.5 A
1
@ VSSIO_SENSE <17>
"R" for SILERGY
Peak Current 3.5 A
0_0402_5%~D
OCP Current 4.2 A Fix by IC
TYP MAX
Choke DCR 48.0mohm
+3.3V_ALW
1
@ PR426 PR410
1 2 0_0402_5%
<11,17,33,47> SIO_SLP_S0#
0_0402_5%
2
EN_1.0V_PRIM_COREP
PR406
<8,11,17,18,32,41,46,48> SIO_SLP_SUS# 1 2
0.1U_0402_25V6
0_0402_5%~D
1
1
@ PC411
PR407
1M_0402_1%
2
@ PJP402
2
JUMP_43X79
1 2
13
14
15
16
17
PU402 +1.0V_PRIM_COREP 1 2 +1.0V_PRIM_CORE

B Vin=3~17V B
TP
LPM
EN
PGND
PGND
@ PJP404
VIN_1V_PRIM
+5V_ALW 1 2 12
PVIN VOS
1
+1.0V_PRIM_COREP
+3.3V_ALW
10U_0603_10V6M
10U_0603_10V6M
PL404
PAD-OPEN1x1m 1UH_1277AS-H-1R0N-P2_3.3A_30%
1
LX_1V_PRIM
+1.0V_PRIM_COREP
PC412
PC413
11 2 1 2
PVIN SW
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
2
S IC SY8057QDC QFN 16P PWM
1
PC424
PC415
PC416
10 3
AVIN SW
Rup
2
2200P_0402_50V7K
@
0.1U_0402_25V6
1
9 4
PC417
@EMC@ PC418
VID0 PG
1SNUB_1V_PRIM
@EMC@ PR409
PR417 PR418
2
AGND
VID0_PRIM_CORE
10K_0402_1% 10K_0402_1% 4.7_0603_5%

VID1
FBS
@EMC@
SS
2
VID0_PRIM_CORE
+1.0V_PRIM_CORE
8
VID1_PRIM_CORE TDC 1.8 A

@EMC@ PC419
Peak Current 2.5 A
SS_1V_PRIM
1
OCP Current 4.2 A Fix by IC

VID1_PRIM_CORE
470P_0402_50V7K
2
@ PR408
@ PR419 @ PR420 0_0402_5% TYP MAX
10K_0402_1% 10K_0402_1% <18> CORE_VID0
1 2 Choke DCR 48.0mohm
2
@ PR411
PR423
0_0402_5%
1 2 1 2
<18> CORE_VID1
0_0402_5%~D
1
470P_0402_50V7K
A A
1
@ PR424
1M_0402_1%
1
PR428
100K_0402_1%
PC420
2
"R" for SILERGY @

2
@
Title
+1VS_VCCIOP/+1.0V_PRIM_COREP
1.0
LA-C631P, C641P
5 4 3 2 1
5 4 3 2 1
Vinafix.com @ PJP502
JUMP_43X79
D D
1 2
+1.8VALWP 1 2 +1.8V_PRIM
PC502
22U_0603_6.3V6M
Imax= 2A, Ipeak= 3A
FB=0.6V
1 2 PU501
SY8032ABC_SOT23-6
@ PJP501 PL501
JUMP_43X79 1UH_1277AS-H-1R0N-P2_3.3A_30%
1 2 VIN_1.8VALW 4 3 LX_1.8VALW 1 2
+3.3V_ALW 1 2 IN LX +1.8VALWP
5 2
68P_0402_50V8J
PG GND
22U_0603_6.3V6M
22U_0603_6.3V6M
1
1
PC503
6 1
FB EN
1
PC501
PC504
@EMC@ PR502
PR501
2
4.7_0603_5%
PR504
2
20K_0402_1%
2
1 2 EN_1.8VALW
<8,11,17,18,32,41,46,47> SIO_SLP_SUS#
2
SNUB_1.8VALW
Rup
0_0402_5%~D
1
PR505 @ PC505 FB_1.8VALW
1M_0402_1% 0.1U_0402_16V7K
1
2
PR506
1
@EMC@ PC506
10K_0402_1%
Rdown
680P_0402_50V7K
2
C
Note: C
When design Vin=5V, please stuff snubber +1.8V_PRIM
to prevent Vin damage TDC 0.665 A
Vout=0.6V* (1+Rup/Rdown) Peak Current 0.931 A
OCP Current 3.5A fix by IC
+3.3V_RUN
+5V_ALW
1
PJP503
PAD-OPEN1x1m
1
PC507
2
1U_0402_6.3V6K
Footprint use APL5930
2
+1.5V_VIN
PR511
<11,17,32> SIO_SLP_S3#
6
B B
47K_0402_5% PU502
+1.5V_RUN
1
1 2 5
VCNTL
VIN
7
POK
PC508
4.7U_0805_6.3V6K
TDC 0.021 A
+3.3V_RUN 4
PJP504 Peak Current 0.6 A
2
VOUT
@ PR507 VOUT
3 1.5VSP 1 2
+1.5V_RUN OCP Current 5.7 A fix by IC
1
1 2 8 2 PAD-OPEN1x1m
EN FB
1
GND
100K_0402_5%
9 PR508 PC509
VIN
1
8.87K_0402_1% 0.01UF_0402_25V7K
1
PR509 PC510 @EMC@ PC511
1
2
AP7175SP-13_SO-8EP-8
2
47K_0402_5% .1U_0402_16V7K 22U_0805_6.3V6M
2
1
2
PR510
10.2K_0402_1%
2
A A
Title
+1.8VALWP/+1.5VSP
1.0
LA-C631P, C641P
5 4 3 2 1
5 4 3 2 1
+1.0V_VCCST VCC_SA
TDC 3.7A
0_0402_5%~D
Peak Current 4.5A
PR602
OCP current 5.4A
0.1U_0402_25V6
1
1
45.3_0402_1%
75_0402_1%
100_0402_1%
1 2
PC602
+5V_ALW Choke DCR 13 m ohm
PR605
PR601
PR604
Local sense put on HW site
Vinafix.com
2
PJP603
@ 1 2 CPU_B+
0.22U_0603_25V7K
2
2
1 2
1U_0603_10V6K
1 2 VIDSCLK_A 1 2 VCCSA_B+ CPU_B+
<15> VIDSCLK 0_0402_5%~D
1
PR606 0_0402_5%~D 49.9_0402_1% PR618
PC603
PC604
D PAD-OPEN1x1m D
<15> VIDALERT_N 1 2 VIDALERT_N_A 1 2 PR603
PR607 0_0402_5%~D 0_0402_5%~D PR625
2
<15> VIDSOUT 1 2 VIDSOUT_A 1 2
10_0402_1% PR626
PR678 PR609 0_0402_5%~D VCCSA_B+
VIDALERT_N_B
<12,32,51> H_PROCHOT#
VIDSOUT_B
VIDSCLK_B
100_0402_1%
1 2 1 2
1 2
PC605 47P_0402_50V8J~D
PR608
PH601 PR610 78.7K_0402_1%
10U_0805_25V6K
10U_0805_25V6K
470K_0402_5% 10K_0402_1% 1 2
1 2 1 2 PR613 1.91K_0402_1% PR612
1
86.6K_0402_1% 1 2 PR611
PC612
PC608
1 2 1 2 +3.3V_RUN 0_0402_5%~D PR614 48.7K_0402_1%
PR631 PC613 <11> PCH_PWROK 1 2
2
27.4K_0402_1% 330P_0402_50V8J @
1 2 1 2
<32> IMVP_VR_ON
PC614 PR617
2200P_0402_50V7K 3.92K_0402_1% PR616
1 2 1 2 0_0402_5%~D
40
39
38
37
36
35
34
33
32
31
PU602 SA_UGATE
PC616 PR619
VR_ENABLE
VR_READY
SCLK
SDA
VCC
VIN
VR_HOT#
ALERT#
PROG1
PROG2
68P_0402_50V8J 0_0402_5%~D 1 2
PC617 PR621 PR620
1 2
1200P_0402_50V7K 316_0402_1% 1 2 1 30 PWM_VSA 2.2_0603_5%PU606 AON7934_DFN3X3A-8-10
<32,51> I_SYS PSYS PWM_C
1
1 2 1 2 2 29 FCCM_VSA ISL95808HRZ-TS2378_DFN8_2X2 PQ501
<16> VCC_GT_SENSE IMON_B FCCM_C
PR622 3 28 PL601
D1
D1
D1
G1
@ PC618 1.96K_0402_1% 4 NTC_B ISUMN_C 27 1 8 1UH_MMD-05CZ-1R0M-M7L_7A_20%
1 2 1 2 5 COMP_B ISUMP_C 26 PC611 UGATE PHASE
0.082U_0402_16V7K
6 FB_B RTN_C 25 FB_VSA 1 2 2 7 10 9 SA_SW 1 2

PC620
RTN_B FB_C BOOT FCCM D1 D2/S1 +VCC_SA

1
COMP_VSA
PR627 @EMC@
330P_0402_50V7K 7 24 0.22U_0603_16V7K
PC621 PR623 8 ISUMP_B COMP_C 23 IMON_VSA PWM_VSA 3 6
PC619 680P_0402_50V7K 2K_0402_1% 9 ISUMN_B IMON_C 22 PWM VCC
4.7_1206_5%
G2
S2
S2
S2
2
ISEN1_B PWM_A PWM_IA <50>
1
C SA_LGATE C
1 2 @ 1 2 1 2 10 21 4 5
ISEN2_B FCCM_A FCCM_IA <50> GND LGATE
1
TP
ISUMN_A
ISUMP_A
PR624
PWM1_B
PWM2_B
COMP_A
8
FCCM_B
IMON_A
0.01UF_0402_25V7K 41
NTC_A
RTN_A
AGND 3.65K_0603_1%
1
FB_A
<16> VSS_GT_SENSE
9
PR679
2
0_0402_5%~D
ISUMP_VSA 2
+5V_RUN
SA_SNUB
11
12
13
14
15
16
17
18
19
20
ISUMN_VSA
S IC ISL95857HRTZ-TS2778 TQFN 40P PWM
2
1U_0402_10V6K
<50> ISUMP_GT
FCCM_VSA
IMON_IA
FB_IA
<50> FCCM_GT
NTC_IA
COMP_IA
PC685
4.42K_0402_1%
<50> PWM1_GT
2
1
PR628
PC625
680P_0603_50V7K
330P_0402_50V7K
10K_0402_5%
1
1 2
@EMC@ PC622
0.047U_0402_25V7K
PR629
2
0.033U_0402_16V7K
88.7K_0402_1%
2
1
1
1 2
PC624
PC626
10P_0402_50V8J
7.32K_0402_1%
PR630
PH603
1
1
PR632 PC627 470K_0402_5%
11K_0402_1%
2200P_0402_50V7K
1200P_0402_50V7K
2
2
1
2200P_0402_50V7K 1 2 1 2
PH602
PR633
PC628
1K_0402_1%
1 2 1 2 ISUMP_VSA
2
PR647 27.4K_0402_1% PR635 1 2
340_0402_1%
1
PR638 1 2 10K_0402_1%
2.61K_0402_1%
2
1
374_0402_1% PR636 1.24K_0402_1%
PC630
PR640
2
1 2 PC629
PC631
PR639
PR642
<50> ISUMN_GT 2200P_0402_50V7K 3.6K_0402_1% 1 2 1 2
2
1 2 1 2
10KB_0402_5%
2
PC632 PR641
.1U_0402_16V7K
0.033U_0402_16V7K
2
1
2
PC636 2200P_0402_25V7K 1K_0402_1%
1K_0402_1%
11K_0402_1%
68P_0402_50V8J
PC641
6800P_0402_25V7K
PR643
1
1
1 2
PR644
PC633
PC637
2
1
PC639 PR645 PR646 PC640
+5V_ALW
1
B 2200P_0402_50V7K 316_0402_1% 1 2 1 2 B
1 2 1 2
330P_0402_50V7K
2
PH604
316_0402_1% 2200P_0402_50V7K
PR648
2
1 2 PR649
1
PC642 1 2
124K_0402_1%
1
1.37K_0402_1% 0.033U_0402_16V7K ISUMN_VSA
PC643
PR651
1.62K_0402_1% PC644
2K_0402_1%
1
1
1 2 .1U_0402_16V7K
2K_0402_1%
2
1 2
PR652
.1U_0402_16V7K
2
1
PR650
PC645
2
1 2
PC646
680P_0402_50V7K
680P_0402_50V7K
0.047U_0402_25V7K
2
1 2 VSA_SEN- <17>
PC647
PC601
2
1
PC649
0.01UF_0402_25V7K
0.082U_0402_16V7K
1 2
PR656
11K_0402_1%
<15> VCCSENSE
2
1 2
PC650
@ PC652
PR657
1
@ PC651 PH605 @ 330P_0402_50V7K
1 2 4.42K_0402_1% 10KB_0402_5% 1 2
1 2 1 2
0.082U_0402_16V7K
PC653
330P_0402_50V7K
1
VSA_SEN+ <17>
ISUMN_IA <50>
2
PC654 @
1 2
A A
ISUMP_IA <50>
0.01UF_0402_25V7K
<15> VSSSENSE
Local sense put on HW site
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL PWR_VCORE_ISL95812 for QC
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
+PWR_SRC VCC_core
PJP601
TDC 21A
1 2
Peak Current 28A
CPU_B+ PAD-OPEN 4x4m OCP current 34A
@EMC@ PL602 Choke DCR 0.9 +-7%m ohm
1 2
@EMC@
@EMC@
2200P_0402_50V7K SUPPRE_9A Z80 10M 1812
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
100U_D_20VM_R55M
0.1U_0402_25V6K~D
1
1
+
PC656
PC657
PC658
PC659
PC660
PC606
2
@ 2
VCC_GT
TDC 18A
Peak Current 31A
PU603
PL603
0.15UH_MMD06CZER15MG_37A_20%
OCP current 37A
9
PGND2
Choke DCR 0.9 +-7%m ohm
PC655 8
<49> PWM_IA PWM CORE_SW
1 2 7 4 4 1
BOOT VSW +VCC_CORE
PR663 @EMC@
0.22U_0603_16V7K 3
1 2 6 PGND1 2 3 2
PR660 5 BOOT_R VDD 1
4.7_1206_5%
VIN SKIP#
1
C PJP602 C
2.2_0603_5%
1
1 2
CSD97374CQ4M_SON8_3P5X4P5
PR661 GPU_B+ CPU_B+
10P_0402_50V8K
3.65K_0603_1%
5.11K_0402_1%
PAD-OPEN 1x2m~D
1
PC680
PC686
PR662
1U_0402_10V6K
+5V_RUN
2
1
1000P_0402_50V7K
2
2
1
PC661
CORE_SNUB
2
<49>
<49>
ISUMP_IA
ISUMN_IA
PR659
2
0_0402_5%~D
2
<49>
FCCM_IA
GPU_B+
680P_0603_50V7K
1
@EMC@ PC662
2
10U_0805_25V6K
10U_0805_25V6K
1
1
PC672
PC673
2
2
@
PL604
PU605
B 0.15UH_MMD06CZER15MG_37A_20% B
9
PC671 8 PGND2
<49> PWM1_GT PWM GT_SW1
1 2 7 4 4 1
BOOT VSW
+VCC_GT
PR676 @EMC@
0.22U_0603_16V7K 3
1 2 6 PGND1 2 3 2
PR672 5 BOOT_R VDD 1
4.7_1206_5%
2GT1P
VIN SKIP#
1
2.2_0603_5%
CSD97374CQ4M_SON8_3P5X4P5
10P_0402_50V8K
1
5.11K_0402_1%
PR674
1
PC688
PR680
PC679
1U_0402_10V6K
3.65K_0603_1%
+5V_RUN
2
1
1000P_0402_50V7K
PC677
2
<49>
ISUMN_GT
GT_SNUB1
2
2
PR671
0_0402_5%~D
2
<49>
FCCM_GT
680P_0603_50V7K
<49>
ISUMP_GT
1
@EMC@ PC678
2
A A
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc.

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL PWR_VCORE_ISL95812 for QC
5 4 3 2 1
A B C D
EMC@ PL802
1UH +-20% 6.6A
2 1 TYP MAX
PQ802 PR802
H/S Rds(on) 7.4mohm , 8.8mohm
SI4835DDY-T1-GE3_SO8 +SDC_IN 0.01_1206_1% +PWR_SRC_AC CHAGER_SRC L/S Rds(on) 2.6mohm , 3.1mohm
8
7
1
2 4 1 1
@ PJP801
2
Choke DCR 5.8mohm , 7.0mohm
+DC_IN_SS 6 3
0.1U_0603_25V7K
+PWR_SRC
5 3 2 PAD-OPEN 4x4m
@
1
Near PL701
PC802
PR803
Vinafix.com PR804
1
1 2 D
DC_BLOCK_GC <52> 1 2 2 PQ803
<52> CSS_GC
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
0_0402_5% G DMP3056L-7 1P SOT23-3
1
1 1
D S
3
0_0402_5%~D 2 PQ804
PD802
1
PC803
PC804
PC805
PC806
PC807
G DMP3056L-7 1P SOT23-3
2 1 PQ801 S
+DOCK_PWR_BAR
D
DMP3056L-7 1P SOT23-3 3 1 DOCK_DCIN_IS+ <38>
2
SDMK0340L-7-F_SOD323-2~D
CSSN_1
CSSP_1
PD801 PQ805
G
2
2 1 PR805 DMP3056L-7 1P SOT23-3
+DC_IN_SS 100_0402_1%
D
SDMK0340L-7-F_SOD323-2~D 2 1 3 1
+PWR_SRC
100K_0402_1%
PD803 DOCK_DCIN_IS- <38>
1
2 1
+PBATT
G
100K_0402_1%
2
1
1
PR808
PR806 PR807
SDMK0340L-7-F_SOD323-2~D 0_0402_5%~D 0_0402_5%~D
PR809
22U_0805_25V6M
10U_0805_25V6K
PC808 PC809
1
AC Det PR811 1U_0603_25V6K 0.1U_0402_25V6
PR810
2
+SDC_IN 10_1206_5% 1 2 1 2 1 2
Max:16.82V
1
PC811
@EMC@ PC812
2 1
DK_CSS_GC <52>
Typ :16.54V PC810
34K_0402_1%
Min :16.26V 0.1U_0402_25V6
2
0_0402_5%~D
PC813
1
BQ24770_REGN
PR812
PC814 PU801 1 2
10U_0805_25V6K
ACDRV
ACP
ACN
2 1 +DCIN 28 1U_0603_10V6K
VCC
BQ24770_REGN
PR813 3 24
1
6.49K_0402_1% CMSRC REGN PR814 PC821
2 1 6 2.2_0603_5% 0.047U_0603_16V7K
ACDET
22U_0805_25V6M
22U_0805_25V6M
22U_0805_25V6M
22U_0805_25V6M
25 1 2 2 1
2200P_0402_50V7K
PR836 0_0402_5%~D
0.1U_0402_25V6
PC815 1 2 11 BTST
SDA
@EMC@ PC817
@EMC@ PC816
CHARGER_SMBCLK 2 1 PR835 0_0402_5%~D
1
CHG_UGATE
PC818
PC819
PC822
PC820
CHARGER_SMBDAT 1 2 12 26
SCL HIDRV
1
pull up 10K in HW side (R827 R828) 0.1U_0402_25V6 PR815 0_0402_5%~D

PR801 1 2 5
2
100K_0402_1% ACOK 27 CHG_SW
<32> CHARGER_SMBDAT PHASE
2 7 2
IADP
<32> CHARGER_SMBCLK
2
8 23 CHG_LGATE
IDCHG LODRV
<32,52> ACAV_IN PR816 0_0402_5%~D 9
ISYS
1
1 2 PR818 100_0402_1%
<32> I_ADP
1
D
<31,43,52> AC_DIS 2
PR817 PR819
1
0_0402_5%~D
2
1 2 10
/PROCHOT GND
22 +PWR_SRC
154K_0402_1%
G <32> I_BATT PR820 0_0402_5%~D
PR821
2
PQ809 S 1 2 PR823 +VCHGR
AON6992 2N DFN5X6D
3
DMN65D8LW-7_SOT323-3 <32,49> I_SYS 13 21 1 2 BQ24770_REGN

100P_0402_50V8J
100P_0402_50V8J
CMPIN 0.01_1206_1%
S1/D2
G1
D1
CMPIN NC
1
30.1K_0402_1%
2 PL801
PQ808
CMPOUT 14 10K_0402_1% 2 1 4 1
CMPOUT
2
2
PC823
PC824
PR822
PR837 20 3.3UH_PCMB063T-3R3MS_6.5A_20%
1M_0402_1% SRP 3 2
G2
S2
S2
S2
4.7_1206_5%
15 19
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0603_25V7K
2
/BATPRES SRN
@EMC@ PR824
PR825
1
3
<52> /BATPRES
@EMC@ PC825
4.02K_0402_1%
1
16 18 1 2
CELL /BATDRV
PC826
PC801
PC827
<12,32,49> H_PROCHOT#
1 CHG_SNUB 1
29 17 1 2
2
PWPD BAT
PR826 @
10_0603_1%+PBATT
1000P_0603_50V7K
BQ24777RUYR_WQFN28_4x4 PC829 PC830 @ PC831
PR828
0.1U_0402_25V6 0.1U_0402_25V6 0.1U_0402_25V6
1 BQ24770_REGN
@EMC@ PC832
<32,43,52> PBAT_PRES# 1 2 1 2 1 2 1 2 1 2
PC828
0_0402_5%~D 1U_0603_25V6K
2
PR827
1K_0402_5%
2
3 3
1
@ PR829
154K_0402_1%
2
+DC_IN
BATDRV# <52>
1
PR830
649K_0402_1%
PR831
100K_0402_1%
2
1 2 CMPIN
1
CMPOUT
PR832 PC833
3M_0402_5% 100P_0402_50V8J
2
PR833
2
<32,52> ACAV_IN_NB 1 2
1
0_0402_5%~D PC834
PR834 100P_0402_50V8J
1
10K_0402_1%
2
+3.3V_ALW
4 4
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Charger
A B C D
5 4 3 2 1
Purpose: Trigger PROCHOT# when

active battery is removed from
system.
+PBATT Allows EC to re-establish
system performance for battery +3.3V_ALW
next in line.
1
+3.3V_ALW PR902
100K_0402_5%
+PWR_SRC_AC
1
Vinafix.com
2
PR903 @ PR904
+3.3V_ALW 100K_0402_5% 0_0402_5%
1 2 /BATPRES <51>
@ PD902
PQ902B
PDS5100H-13_POWERDI5-3
1
3
D 3 D
+VCHGR 1 PR905
2 100K_0402_5%
5
PQ903
2
SI4835DDY-T1-GE3_SO8
+3.3V_ALW
4
1 8
PR906
PQ902A
2 7 PC902 PC903
6
3 6 1 2 1 2 0.1U_0402_10V7K
5 1 2
0.47U_0805_25V6K
0_0402_5%~D 2
5
1
P
<32,43,51> PBAT_PRES#
1
STSTART_DCBLOCK_GC
B
1
2
3
<51> BATDRV# 4
2 O
A
G
1
4 PU902
3
PD903
PQ904
PDS5100H-13_POWERDI5-3 PR907
S TR AO4423L 1P SO8 TC7SH08FU_SSOP5~D
<31> DIS_BAT_PROCHOT# 1 2
8
7
6
5
0_0402_5%~D
3
PR908
330K_0402_5%
2 1
+DOCK_PWR_BAR
5
PQ905
S TR AON7401 1P DFN
4
Purpose: Turn on the PQ817
for primary or module bay
battery to provide power to
1
2
3
+3.3V_ALW2 1 PR909 2
dock side without AC exist.
+3.3V_ALW2
100K_0402_5%
C PC905 100K_0402_5% C
@
2 1
1
PC904 PU903
PR910
PQ907A
6
1500P_0402_50V7K TC7SH08FU_SSOP5~D 0.1U_0402_10V7K
5
2
1
P
B
1
2
3
4 2 DOCK_DET# <31,38,52>
O 2 ACAV_IN#
10K_0402_5%
A
1
1
PQ901 4
3
PR912
S TR AO4423L 1P SO8
2
8
7
6
5
DMN65D8LW-7_SOT323-3
1
D
2
PQ908
G
S
3
PQ909 Vth=0.5-1.5V +3.3V_ALW2
1
DMG2301U-7 1P SOT23-3
PR913
PD904
3
3 1
1
+3.3V_ALW 1 2
SDMK0340L-7-F_SOD323-2~D PR914
100K_0402_5%
1
2
0_0402_5%~D
2
2
PR915
2
100K_0402_5%
ACAV_IN#
PQ911A
2
DMP3099L-7_SOT23-3
PR936
PQ907B
1 6 2 1
3
100K_0402_5%
D PQ906
1
PR916 PQ911B
<31,43,51> AC_DIS DMN65D8LW-7_SOT323-3
2
1 2 2
1
DMN65D8LDW-7_SOT363-6 1
PQ910
<32,51,52> ACAV_IN 5
10K_0402_5% G 4 3 2
S PR917
2 1 2
3
PD905
4
+3.3V_ALW2 3
3
100K_0402_5% 3
+DC_IN_SS
2 5
PR924
PR911
100_0603_1% 1 2 1
B PR935 1 2 PR919 100K_0402_5% B
100_0603_1% +DOCK_PWR_BAR 0_0402_5%~D 2
+NBDOCK_DC_IN_SS
1 2
+DC_IN_SS
BAT54CW_SOT323-3
1
PR921 <31,38,52> DOCK_DET#

DK_PWRBAR
CD3301_DCIN PD901
1 2
+DC_IN
DC_IN_SS
PR933 2
47_0805_5%~D
100_0603_1%
1
PC906 1 2 1
DOCK_AC_OFF <38>
0.1U_0603_25V7K +PBATT
PR937 3
2
0_0402_5%~D
CD_PBATT_OFF
P50ALW 1 2 BAT54CW_SOT323-3
36
35
34
33
32
31
30
29
28
PR925
+3.3V_ALW2
PR920
<43> SOFT_START_GC
PU901 +5V_ALW
1 2 PR930 0_0402_5%~D 10K_0402_5%
NC
CHARGERVR_DCIN
DK_PWRBAR
GND
NC
BLK_MOSFET_GC
DSCHRG_MOSFET_GC
DC_IN_SS
PBatt+
1 2
PR923 SLICE_BAT_ON <31>
2
100K_0402_5%
1 2 ACAVDK_SRC
<38> ACAV_DOCK_SRC#
PR928 1 27
100_0603_1% 0_0402_5%~D 2 DC_IN P50ALW 26
SS_GC PBATT_OFF DK_AC_OFF PR922
1 2 ERC1 3 25 0_0402_5%~D
+SDC_IN 4 ERC1 DK_AC_OFF_EN 24 3301_ACAV_IN_NB 1 2
ACAVDK_SRC ACAV_IN_NB ACAV_IN_NB <32,51>
5 23
CD3301_SDC_IN 6 GND GND 22 DK_AC_OFF_EN 1 2
SDC_IN DK_AC_OFF_EN SL_BAT_PRES# DOCK_AC_OFF_EC <31>
7 21
<51> DC_BLOCK_GC ACAVIN 8 DC_BLK_GC SL_BAT_PRES# 20 PR938 0_0402_5%~D
PR918 PR929
P33ALW2 9 ACAV_IN BLKNG_MOSFET_GC 19 1 2
1 2 P33ALW2 NBDK_DCINSS
EN_DK_PWRBAR
<32,51,52> ACAV_IN 1M_0402_5%

SS_DCBLK_GC
PR926 0_0402_5%~D
1 2
DK_CSS_GC
0_0402_5%~D SLICE_BAT_PRES# <31,38,43>

PWR_SRC
PR932
CSS_GC
P33ALW
37 @ PR927
1 2 TP 0_0402_5%
ERC3
ERC2
+3.3V_ALW2
GND
1 2
+NBDOCK_DC_IN_SS
0_0402_5%~D PR901
CD3301BRHHR_QFN36_6X6~D
10
11
12
13
14
15
16
17
18
1 2
PR931 EN_DOCK_PWR_BAR <31>
0.1U_0603_25V7K
<51> CSS_GC 1 2
P33ALW
ERC2
<51> DK_CSS_GC 0_0402_5%~D

+3.3V_ALW
1
PC908
ERC3
A 0_0402_5%~D A
EN_DK_PWRBAR
0.047U_0603_25V7M
2
0.1U_0402_25V6
PR934
1 2
PC907
1M_0402_5%
1
STSTART_DCBLOCK_GC
PC901
PR939
100_0603_1%
2
@ 3301_PWRSRC 1 2
+PWR_SRC_AC
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Selector
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-C631P, C641P
5 4 3 2 1
4
3
2
1
+VCC_CORE
A
A
2 1 2 1
2
1
2
1
+
330U_D2_2.5VM_R9M
PC1099 PC1083 PC1076
PC1127
1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M
2 1 2 1
2
1
2
1
2
1
+
@
@
330U_D2_2.5VM_R9M
PC1095 PC1030 PC1081 PC1078
@ PC1062
1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1
Back Side.
2
1
2
1
@ PC1170 PC1094 PC1031 PC1080 PC1077

Primary Side.
22U_0603_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

2 1 2 1 2 1
2
1
2
1
@
@ PC1171 PC1096 PC1032 PC1082 PC1079
2 1 2 1 2 1
2
1
2
1
@ PC1172 PC1090 PC1033 PC1067 PC1001

VCC_CORE Place on CPU

2 1 2 1 2 1
2
1
2
1
@
@
@ PC1173 PC1093 PC1034 PC1072 PC1002

2 1 2 1 2 1
2
1
2
1
@ PC1174 PC1091 PC1035 PC1069 PC1003

2 1 2 1
22U_0603 * 13 pcs+330u_D2*1 pcs
2
1
2
1
22U_0603 * 7 pcs +1U_0201*35 pcs
PC1097 PC1036 PC1074 PC1004

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
B
B
2 1 2 1
2
1
2
1
PC1092 PC1037 PC1070 PC1005

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1
Vinafix.com
2
1
2
1
PC1098 PC1038 PC1061 PC1006

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1
2
1
2
1
PC1050 PC1039 PC1071 PC1007

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1
2
1
2
1
PC1051 PC1084 PC1066 PC1008

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1
2
1
2
1
PC1052 PC1086 PC1073 PC1009

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1
2
1
2
1
PC1053 PC1085 PC1068 PC1010

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1
2
1
2
1
PC1054 PC1088 PC1075 PC1011

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1
2
1
2
1
PC1126 PC1087 PC1064 PC1012

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1
2
1
2
1
C
C
PC1164 PC1089 PC1065 PC1013

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1
PC1125
1U_0201_6.3V6M
Back Side.
Primary Side.
22U_0603 * 8 pcs
VCC_SA Place on CPU
+VCC_GT
2 1
2
1
2
1
2
1
330U_D2_2.5VM_R9M
PC1040 PC1133 PC1014
PC1128
1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1
22U_0603 * 4 pcs + 1U_0201*7 pcs
2
1
2
1
2
1
+VCC_SA
@
330U_D2_2.5VM_R9M
PC1041 PC1137 PC1015
PC1063
1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1
2
1
2
1
2 1 @ PC1181 PC1042 PC1129 PC1016
D
D
2
1
22U_0603_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

Back Side.
PC1153 PC1057 2 1 2 1
2
1
2
1
1U_0201_6.3V6M 22U_0603_6.3V6M
2 1 @ PC1180 PC1043 PC1132 PC1017
Primary Side.
2
1
22U_0603_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

PC1147 PC1058 2 1 2 1
2
1
2
1
1U_0201_6.3V6M 22U_0603_6.3V6M
@
2 1 @ PC1177 PC1044 PC1136 PC1018

2
1
22U_0603_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

PC1148 PC1059 2 1 2 1
VCC_GT Place on CPU
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2
1
2
1
1U_0201_6.3V6M 22U_0603_6.3V6M
@
2 1 @ PC1179 PC1045 PC1134 PC1019

2
1
22U_0603_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

PC1149 PC1060 2 1 2 1
2
1
2
1
1U_0201_6.3V6M 22U_0603_6.3V6M
@
2 1 @ PC1176 PC1046 PC1135 PC1020

2
1
22U_0603_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

Title
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
PC1150 PC1139 2 1 2 1
Date:
2
1
2
1
1U_0201_6.3V6M 22U_0603_6.3V6M
@
2 1 @ PC1178 PC1047 PC1138 PC1021

2
1
22U_0603_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

22U_0603 * 7 pcs +330u_D2*2 pcs
PC1151 PC1140 2 1 2 1
2
1
2
1
1U_0201_6.3V6M 22U_0603_6.3V6M
22U_0603 * 11 pcs +1U_0201*12 pcs
2 1 @ PC1175 PC1048 PC1027 PC1022

2
1
22U_0603_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

PC1152 PC1141 2 1
2
1
2
1
1U_0201_6.3V6M 22U_0603_6.3V6M
Document Number
PC1049 PC1028 PC1023

2
1
1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

PC1142 2 1
2
1
2
1
22U_0603_6.3V6M
Thursday, September 24, 2015
PC1055 PC1130 PC1024

2
1
1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

PC1143 2 1
2
1
2
1
22U_0603_6.3V6M
E
E
PC1056 PC1029 PC1025

2
1
1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

PC1144
Sheet
2
1
2
1
22U_0603_6.3V6M
@
PC1131 PC1026
2
1
22U_0603_6.3V6M 22U_0603_6.3V6M
53
LA-C631P, C641P
PC1145
22U_0603_6.3V6M
of
2
1
PC1146
22U_0603_6.3V6M
PROCESSOR DECOUPLING
60
Rev
1.0
4
3
2
1
A B C D
Vinafix.com
1 1
+3.3V_ALW
+5V_ALW
1
PJP1501 +2.5V_MEM
PAD-OPEN1x1m TDC 0.45 A
Peak Current 0.6 A
1
PC1500
2
OCP Current 5.7 A fix by IC 2
2
1U_0402_6.3V6K
2
+2.5V_VIN
6
PU1500
1
5
VCNTL
7 VIN PC1501
POK 4 4.7U_0805_6.3V6K
PJP1500
2
VOUT
3 2.5VSP 1 2
PR1500
VOUT
+2.5V_MEM
1
1 2 8 2 PAD-OPEN1x1m
<11,17,32,45> SIO_SLP_S4# EN FB
1
GND
47K_0402_5%
9 PR1501 PC1502
VIN
1
1
21.5K_0402_1% 0.01UF_0402_25V7K
1
PR1502 PC1504@EMC@ PC1503
2
AP7175SP-13_SO-8EP-8
2
47K_0402_5% .1U_0402_16V7K 22U_0805_6.3V6M
2
1
2
PR1503
10.2K_0402_1%
2
3 3
4 4
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc.

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL +2.5V_MEM
LA-C451P
A B C D
5 4 3 2 1
+1.0V_PRIM
VCCPRIM_1P0 PCH SIO_PWRBTN# 8
Timing Diagram for S5 to S0 mode VCCPRIM_CORE
DCPDSW_1P0
VCCMPHYAON_1P0
VCCAPLL_1P0
PWRBTN#
RSMRST#
PCH_RSMRST#
7
VCCCLK1~6 SIO_SLP_SUS#
TPS22961 VCCMPHYGT_1P0
VCCSRAM_1P0
SLP_SUS# 5
SIO_SLP_S5#
+PWR_SRC 6 +1.0V_MPHYGT VCCAMPHYPLL_1P0
VCCAPLLEBB
SLP_S5#
9
6 SIO_SLP_S4#
+1.0V_PRIM SYX198
EXT_PWR_GATE#
EXT_PWR_GATE#
SLP_S4# 10
SIO_SLP_S3#
+3.3V_ALW +3.3V_ALW_DSW SLP_S3#
Vinafix.com
3
+3.3V_SPI 5 +3.3V_ALW_PCH
VCCDSW_3P3
SLP_A#
SIO_SLP_A#
D VCCST_PWRGD
CPU
+VCC_CORE VCCHDA SLP_LAN#
SIO_SLP_LAN#
11 D
VCCSPI
12 VCCST_PWRGD VCC VCCPRIM_3P3
VCCPGPPA~E
SLP_WLAN#/GPD9
SIO_SLP_WLAN#
+1.0VS_VCCIO VCCRTCPRIM RESET_OUT#
H_CPUPWRGD
VCCIO
5 +1.8V_PRIM SYS_PWROK
16
15 PROCPWRGD +VCC_GT VCCPGPPG
VCCATS PCH_PWROK
PCH_PWROK
PCH_PLTRST#
VCCGT
+RTC_CELL 14
+1.35V_MEM
17 PLTRST#
VDDQ
VCCRTC
VCCST_PWRGD
VCCST_PWRGD
12
0.675V_DDR_VTT_ON
VDDQC
VCCPLL_OC +1.0V_PRIM 5 +1.0V_PRIM_CORE
VCCPRIM_CORE
12 DDR_VTT_CNTL +1.0V_VCCST 10 SIO_SLP_S4# PROCPWRGD
H_CPUPWRGD
15
VCCST TPS22961 PCH_PLTRST#
VCCSTG
VCCPLL
17 PLTRST#
+VCC_SA
VCCSA
PCH_DPWROK
4 DSW_PWROK
+3.3V_ALW
ENVDD_PCH
+LCDVDD AP2821K EDP_VDDEN
+PWR_SRC
+1.0V_PRIM_CORE SIO_SLP_SUS# +3.3V_ALW
5 TLV62130
SIO_SLP_LAN#
+3.3V_ALW 11 +3.3V_LAN EM5209VF SLP_LAN#
5 +1.8V_PRIM
TLV62130
+5V_RUN
C 3.3V_TS_EN C
+5V_TSP LP2301ALT1G GPP_B21
+3.3V_RUN
3.3V_CAM_EN#
+3.3V_CAM LP2301ALT1G GPD7
Power Button
SIO 5048 1BAT 2AC

11 SIO_SLP_WLAN#
11 ADAPTER
+PWR_SRC
+5V_ALW ALWON
+5V_ALW2
RUN_ON
EC 5085 SYX198
+5V_ALW
+5V_RUN +5V_HDD 1BAT
EM5209VF
+PWR_SRC
+3.3V_ALW +3.3V_RTC_LDO
BATTERY SYX198
+3.3V_ALW2 2AC
EM5209VF +3.3V_RUN +3.3V_HDD +3.3V_ALW
+3.3V_RUN
11
APL5930 +1.5V_RUN PCH_RSMRST# 5
B
+PWR_SRC 7 SIO_SLP_SUS#
+3.3V_ALW
B
+3.3V_ALW @SIO_SLP_WLAN# TLV62130 +1.0VS_VCCIO PCH_DPWROK

4 EM5209VF
@PCH_ALW_ON +3.3V_ALW_PCH 5
RESET_OUT#
11 +3.3V_WLAN EM5209VF AUX_EN_WOWL 16 +3.3V_ALW
11 Pop option
A_ON
EM5209VF +3.3V_M +3.3V_SPI
5 SIO_SLP_SUS#
10 SIO_SLP_S4#
10 +3.3V_ALW
SIO_SLP_S5# SUS_ON
9 EM5209VF +3.3V_SUS
SIO_SLP_LAN#
11 SIO_SLP_S3# +PWR_SRC
SIO_SLP_A# EN_INVPWR
AO6405 +BL_PWR_SRC 18
+PWR_SRC
12
+VCC_SA IMVP_VR_ON 10 +PWR_SRC
13 +VCC_CORE ISL95857 SUS_ON
+VCC_GT +1.35V_MEM VDDQ
RT8207MZ VTT
DDR
+0.675V_DDR_VTT
PCH_PWROK
12
0.675V_DDR_VTT_ON
A
BC BUS 14 A

Power Sequence
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Size Document Number Rev
1.0
LA-C631P, C641P
5 4 3 2 1
5 4 3 2 1
Version Change List ( P. I. R. List )

Request
Item Page# Title Date Owner Issue Description Solution Description Rev.
Vinafix.com
D D
VCCIOP
1 47 PRIM_COREP 1/27 Compal For +1.0VS_VCCIO, +1.0V_PRIM_CORE IC 2nd source Add PR403, PR406, PR427, PR428
+VCC_CORE change PR613 to 86.6k

2 49 +VCC_SA 1/27 Compal Fine tune IMON change PR651 to 124k
+VCC_GT change PR629 to 88.7k
change PR638 to 374

+VCC_CORE change PC624 to 0.033uF
49 +VCC_SA 1/27 Compal Fine tune VR current loop change PC642 to 0.1uF
3 +VCC_GT depop PC646
+5V_ALW Remove PU101, PR101, PC101

4 44 +3.3V_ALW 1/27 Compal For 3V5V Pgood Add PR119, PR120
C C
+1.35V_MEN
5 +2.5V_MEM 3/3 Remove +2.5V_MEM, GPU_VRAM power rail circuit
45 Compal For DDR change to DDR3L change power setting from +1.2 to +1.35
GPU_VRAM
change PR640 to 340

+VCC_CORE change PC642 to 0.033uF
6 49 +VCC_SA 3/27 Compal Fine tune VR control loop change PC646 to 0.047uF
+VCC_GT change PR657 to 4.42k
change PR628 to 4.42k
+1.2V_MEN
B
+2.5V_MEM 4/10 Compal For DDR change to DDR4 Add +2.5V_MEM, GPU_VRAM power rail circuit B
7 45 GPU_VRAM change power setting from +1.35 to +1.2
+2.5V_MEM
8 54 +1.8VALWP 4/20 Compal Disable LDO pull up when floating enable pin change PR1500, PR1502, PR509, PR511 to 47k
+1.5VSP
9 51 Charger 4/20 Compal fine tune monitor Psys change PR822 to 40.2k
10 +1VS_VCCIOP
+1.0V_PRIM_COREP change to SY80657
A A
11 CPU MLCC cap depop

cost down CPU MLCC cap +VCC_CORE, 22U*15,330U*1 DELL CONFIDENTIAL/PROPRIETARY
cost down +VCC_GT, 22U*8 Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT PWR P.I.R (1/1)
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-C631P, C641P
5 4 3 2 1
5 4 3 2 1

Rev.
Item Page# Title Date Vinafix.com
Owner Issue Description Solution Description
D D
1 8/22/27/ QA2, QA3, QC2, QE2, QL1, QL2, QN1, QV3, QZ3 and QZ7 from SB00000DH00 0.2(X01)
30/40/42 Material 2015/01/05 COMPAL Material EOL change to SB00000ZU00
32 MEC5085 2015/01/05 DELL Add Re305 and RE306 reserve UART0_TXD path 0.2(X01)
2 For Next Gen EC debug
3 33 USH & TPM 2015/01/12 COMPAL system will shut down when insert FP. change USH conn pin define, and add RZ85, RZ86, DZ7, reserve RZ84, RZ87 0.2(X01)
4 32 MEC5085 2015/01/12 COMPAL change BID to X01. change RE79 to 130K ohm. 0.2(X01)
add net name "LPSS_UART2_TXD", "LPSS_UART2_RXD", and add RC330, RC331
5 9 CPU (4/14) 2015/01/12 COMPAL add UART port 2 for USB debug. and JUART1 CON 0.2(X01)
6 13 CPU (8/14) 2015/01/12 INTEL Follow 546765_546765_2014WW52_Skylake_ reserve CC222 and RC313. 0.2(X01)
MOW_Rev_1_0
7 8 CPU (3/14) 2015/01/12 INTEL support DCI. add RC327 and reserve RC326, QC3 0.2(X01)
C 8 32 MEC5085 2015/01/12 COMPAL For Power down sequence. add UE3, UE4, RE304,RE308. 0.2(X01) C
9 11 CPU (6/14) 2015/01/12 COMPAL For PLTRST glitch issue. 1.UC7.5 change from +3.3V_RUN to +3.3V_ALW_PCH 0.2(X01)
2.Pop RC325,depop RC60.
21 DDR4 2015/01/12 COMPAL DIMM select error cause can't recognize Stuff RD70, RD72 and no stuff RD69, RD73. 0.2(X01)
10 DIMM2.
11 27 Transformer 2015/01/12 COMPAL ME height limit TL1 changed from SP050006F00 to SP050006Y00 0.2(X01)
12 11 Crystal 2015/01/12 TXC Material EOS YC2 changed from SJ10000LD00 to SJ10000LV00 0.2(X01)
13 22 HDMI CONN 2015/01/20 COMPAL For HDMI EMI solution. add RV647 ~ RV658 path and depop commom-chock 0.2(X01)
14 26 LCD 2015/01/20 COMPAL BOM changed UV24 from SA00006EE00 to SA00006Y800 0.2(X01)
15 32 EC 2015/01/20 COMPAL BOM changed QE3/QE4/QE5/QE6/QE7 from SB000008P00 to SB000013V00 0.2(X01)

B B
16 32 EC 2015/01/20 COMPAL BOM changed UD1 and UE4 from SA00005U600 to SA00007UR00 0.2(X01)
1. Reserve10K ohm (RZ90) and Pull-up to +3.3V_RUN on UZ12 pin 29.
17 33 TPM 2015/01/20 COMPAL TPM issue 2. change VSB power (UZ12.1) to +3.3V_ALW_PCH. 0.2(X01)
3. added QZ8 and RZ109 between pin3/pin20 to control LPM
4. reserve RZ110 and de-pop.
5. Reserve +3.3V_RUN on UZ12 pin 8 (add RZ88, RZ89)
6. change RZ109 pin 1to +3.3V_M_TPM add QZ9, RZ111
18 9 CPU (4/14) 2015/01/20 COMPAL Non-Dock config Reserve RH359 pull-down for non-dock config 0.2(X01)
19 32 EC 2015/01/20 COMPAL Power sequence fail Depop RE280 and RE304 then pop RE292 and UE3 0.2(X01)
20 18 CPU (13/14) 2015/02/04 COMPAL KB boss and stand off interference Removed RC304/RC305/RC306/CC205/CC207/CC265 0.3(X02)
21 10 CPU (5/14) 2015/02/04 INTEL MOW update Add RC337 connect to GND and RC338 1K pull down 0.3(X02)
22 12 CPU (7/14) 2015/02/04 INTEL MOW update Add RC328 XDP_JTAGX need connect to CPU_XDP_TCLK for DCI 0.3(X02)
A 23 8 CPU (3/14) 2015/02/04 INTEL MOW update Changed RC317 from 4.7k to 150k and reserved SIO_SLP_SUS# on RC340 0.3(X02) A
24 20,21 DDR4 2015/02/04 Follow 546765_546765_2015WW02_Skylake No stuff CD6, CD35. 0.3(X02)

INTEL _MOW_Rev_1_0 DELL CONFIDENTIAL/PROPRIETARY
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT EE P.I.R (1/3)
5 4 3 2 1
5 4 3 2 1

Rev.
D 1.for allow further reducing power in TPM 2.0 D
F/W,when system is in S3/4/5 and main power 1.reserve RZ90

25 33 USH & TPM 2015/03/02 Nuvoton 2.reserve RZ112.
is off. 0.3(X02)
2.for support modern standby. 3.Depop RZ88 and pop RZ89, pop RZ112
26 11,27 CPU (6/14) 2015/03/02 COMPAL Solve auto power on issue. De-pop RL70 and pop RC323. 0.3(X02)
27 32 MEC5085 2015/03/02 COMPAL Solve power down sequence fail. De-pop RE308. 0.3(X02)
28 32 MEC5085 2015/03/02 COMPAL change BID to X02. change RE79 to 33K ohm. 0.3(X02)
eDP CONN
29 26 & TS 2015/03/02 DELL Customer request. add 6 pin IR Conn. 0.3(X02)
30 40 PAD, LED 2015/03/02 COMPAL ME design change. change H6 from 4mm to 3mm. 0.3(X02)
31 11/32 Crystal 2015/03/02 COMPAL X'tal EA measurement. change CC23 and CC26 from 18pf to 12pf 0.3(X02)
32 8 CPU (3/14) 2015/03/02 Intel Intel MOW_2015WW06:Pull-up Resistors on de-pop RC30, RC316 0.3(X02)
C
SPI_IO2 and SPI_IO3 Requirement Update C
33 8 CPU (3/14) 2015/03/02 COMPAL Follow CRB setting RC23 changed from 8.2K to 2.2K 0.3(X02)
34 33 TPM 2015/03/02 COMPAL support modern standby Add RZ112 connect to SIO_SLP_S0# with TPM 0.3(X02)
35 32 EC 2015/03/02 COMPAL Option DDR3L and DDR4 Add GPP_D9(DIMM_TYPE), RC342 and RC341 that selected DDR3L and DDR4. 0.3(X02)
36 32 EC 2015/03/02 COMPAL Follow Intel power sequence Pop RE292 and depop RE280 0.3(X02)
37 8 CPU (3/14) 2015/03/02 COMPAL RF request Pop CC3/CC4/CC5/CC6 from 22p to 27p 0.3(X02)
38 33 TPM 2015/03/02 Nunoton TPM detected sequence Add RZ113 100 ohm 0.3(X02)
39 11 CPU (6/14) 2015/03/02 COMPAL Deep S3 leakage VRALERT# changed power rail from +3.3V_ALW to +3.3V_ALW_PCH 0.3(X02)
B 40 27 LAN 2015/03/02 COMPAL IEEE EA measurement. change LL2 ~ LL9 to 2.2 ohm Res (RL71~RL78). 0.3(X02) B
1.add IR_CAM_DET# on JIR1 pin 1.

41 9 CPU (4/14) 2015/04/02 COMPAL IR Function 2.add IR_CAM_DET# on UC1.AW7, and PU 100K(RC346) to +3.3V_RUN 0.4(X03)
1.Reserve RZ114/RZ115 on JUSH1 pin 21
42 31/33 EC/USH 2015/04/02 Broadcom Vender recommend 2.add USH_RST# on UE1.A62 0.4(X03)
43 12 CPU (7/14) 2015/04/02 COMPAL SIO_EXT_SMI# to wake up system when non-deep S3 Add RC236 SIO_EXT_SMI# change power to +3.3V_ALWS_PCH 0.4(X03)
44 29 NGFF Card 2015/04/02 COMPAL ME request Change JSIM1 conn to T-SOL_5-991503004000-6 0.4(X03)
45 32 MEC5085 2015/04/02 COMPAL change BID to X03 change RE79 to 1K ohm. 0.4(X03)
46 9 CPU (4/14) 2015/04/02 COMPAL for DIMM type option Pop RC342 and de-pop RC341 0.4(X03)
47 40 PAD, LED 2015/04/02 COMPAL ME request Add H9 and H10 for different SIM CON 0.4(X03)
A 48 29 NGFF 2015/04/02 COMPAL SIM detect Add RI31 connecting with JSIM1.9 and NGFF2.58 0.4(X03) A
Title
5 4 3 2 1
5 4 3 2 1

Rev.
D D
49 39 KB 2015/04/20 ALPS For new U1 TP module Add RZ116 and RZ117 PU on I2C._1_SDA_R/I2C_1_SCL_R 0.4(X03)
50 31 5048 2015/04/20 COMPAL PC common EC code issue need reserved PU Add AR_SMBUS_ALERT# 10K(RE309) PU on ECE5048 pin58 GPIOF2 0.4(X03)
R274,RA35,RA36,RA37,RC143,RC169,RC170,RC171,RC172,RC173,RC211,RC214,
RC228,RC229,RC230,RC231,RC235,RC290,RC295,RC296,RC299,RC300,RC301,RC302,
RC303,RC307,RC308,RC309,RC310,RC325,RC327,RC328,RC337,RC37,RD29,RD60,
51 31 All 2015/04/20 COMPAL Changed 0 ohm short-pad RD65,RD66,RD67,RD68,RD70,RD72,RD74,RE290,RE305,RI15,RI16,RI17
RI18,RI19,RI20,RI21,RI22,RI23,RI24,RI25,RI26,RI27,RI28,RI29,RI30,RI31 0.4(X03)
RL34,RL7,RN99,RR17,RR18,RR21,RR22,RR23,RZ22,RZ23,RZ56,RZ70,RZ85,
RZ86
52 8 CPU(3/14) 2015/04/20 COMPAL SMBUS LAN backdrive Add RC347 and RC348 PU to +3.3V_ALW_PCH 0.4(X03)
53 11 CPU(6/14) 2015/05/20 COMPAL Crystal EA -R issue Changed YC2-CL 9pf from 12pf and cc23/cc26 changed to 6pf from 12pf 0.5(X04)
54 35 M2280 2015/05/20 COMPAL Insert NVME SATA LED no function JNGFF3.10 connected to PCH_SATA_LED# 0.5(X04)
C C
55 36 USB 2015/05/20 COMPAL Insert Storage Bus shutdown Add CI32 150U prevent charger current over spec 0.5(X04)
56 39 TP 2015/05/20 COMPAL TP function sometimes lag or crazy CZ30 and CZ31 change from 10p to 330p improve signal quality 0.5(X04)
1. Add 5048 GPIO(PROCHOT_GATE) and reserve RE311 pull high

57 31 5048 2015/05/20 COMPAL For Type-C function 2. Add 5048(PD_ACE_DET#) for AR config and pull high on RE310 0.5(X04)
58 32 MEC5085 2015/05/20 COMPAL change BID to X04 change RE79 to 8.2K ohm. 0.5(X04)
1.Add RC349 and CC303 on VCCHDA
59 18 CPU(13/14) 2015/05/27 COMPAL 5.76GHz noise observed on thie Wi-Fi antenna 2.Add RC350 and CC304 on VCCAPLL_1P0 0.5(X04)
1.Add CI33 0.1U cap to GND on USB_OC0#
60 36/37 USB3.0 2015/05/27 COMPAL ESD request 2.Add CI34 0.1U cap to GND on USB_OC1# 0.5(X04)
3.Add CI35 0.1U cap to GND on USB_OC2#
61 26 eDP 2015/06/27 COMPAL Material shortage Changed DV1, DV2 and DV3 from SCS00003800 to SCS00006400 0.6(X05)
B B
62 33 TPM 2015/06/27 COMPAL Change TPM FW to 1.2 version Changed UZ12 from SA000082D00 to SA00008EL20 0.6(X05)
63 32 KBC 2015/06/27 COMPAL WinPE Global reset shutdown issue Add QE11 prevent +1.0V_VCCST timing down before +1.0V_VCCIO 0.6(X05)
64 32 KBC 2015/06/27 COMPAL Follow intel power sequence Add UE5 AND Gate control Run_on timing and depop RE292 0.6(X05)
65 11 CPU(6/14) 2015/06/27 COMPAL Cystal EA Changed CC21 and CC22 from 22p to 15p 0.6(X05)
66 33 USH 2015/06/27 COMPAL TPM1.2 deep S3 resume issue UZ12.1 changed power rail from +3.3V_ALW_PCH to +3.3V_ALW 0.6(X05)
67 24 DP HUB 2015/07/20 COMPAL For DP hub display flicker issue 1.Add UV29,CV617,CV618,CV619,RV659,RV650,RV661 0.6(X05)
2.Depop UV28,PJP33,CV615,CV616
68 36 HW 2015/07/20 COMPAL For Sourcer request CI32 change from SGA00002N80 to SGA00004E10 0.6(X05)
69 32 MEC5085 2015/07/20 COMPAL change BID to X05 change RE79 to 4.3K ohm. 0.6(X05)
A A
Title
5 4 3 2 1
5 4 3 2 1

Rev.
D D
70 41 CPU(12/14) 2015/07/31 COMPAL Follow Intel DG1.5 Add load switch (UZ26) control to +VCCPLL_OC power rail 0.6(X05)
71 18 CPU(13/14) 2015/07/31 COMPAL 5.76GHz noise observed on thie Wi-Fi antenna Change RC349 and RC350 to LC1 and LC2 0.6(X05)
72 36 USB 2015/08/12 COMPAL Low battery shut down issue Depop CI32 and then pop CI14 0.6(X05)
73 32 5085 2015/08/12 COMPAL DC mode CPU trubo issue Reserved RE313 pull down path on I_SYS 0.6(X05)
74 34 PCIE 2015/08/12 COMPAL M.2 SATA iEMT Pop RN50 change to level2 0.6(X05)
75 11 CPU(6/14) 2015/08/12 COMPAL RTC delay YC2 changed to 10ppm(SJ10000Q800) and CC23/CC26 changed to 5pf 0.6(X05)
76 24 HUB 2015/09/12 COMPAL Display no function RV662 chnanged to 0 ohm from 1 ohm. 1.0(A00)
77 ALL All 2015/09/12 COMPAL Changed 0 ohm short-pad RC41,RC289,RZ89,RZ112,RZ64,RC221,RZ118,RV662 1.0(A00)

C C
78 12 CPU(7/14) 2015/09/12 COMPAL Service mode switch Depop RC222 and SW1 and then short RC221 1.0(A00)
79 32 5085 2015/09/12 COMPAL syn-up with power material issue 1.Change SC600001600 to SCA00000T00(DI2,DI3,DI5,DV4)
2.Change SB000013V00 to SB00000Z500(QE3,QE4,QE5,QE6,QE7) 1.0(A00)
80 32 MEC5085 2015/09/12 COMPAL change BID to A00 change RE79 to 1K ohm. 1.0(A00)
81 22 HDMI 2015/09/18 COMPAL DFX request Delete LV3/LV6/LV9/LV12 co-lay footprint 1.0(A00)
82 12/14 XDP 2015/09/20 COMPAL Follow PDG2.0 Changed RC82 and RC135 to 100 from 51. 1.0(A00)
B B
A A
Title
5 4 3 2 1

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A B C D E

Park City 12" UMA

REV : 1.0 (A00)

EMC@ : EMI, ESD and RF Component

X76@ : SATA REDRIVER OPTION

DAA000AD000 PCB 1DK LA-C621P REV0 MB

Layout Dell logo

USB2.0[9] LCD Touch

SMSC SIO TPM2.0 P33

Smart Card TDA8034HN POWER ON/OFF

PM TABLE PCIE-8 SATA-1 EDOCK E-SATA

S5 S4/AC ON OFF OFF ON OFF

S5 S4/AC doesn't exist OFF OFF OFF OFF OFF

RUN_ON TPS22961 SIO_SLP_S4#

2 1 CPU_DP1_CTRL_CLK E55 C47

DDR4, Ballout for side by side(Non-Interleave) <21> DDR_B_MA[0..16]

DDR4 COMPENSATION SIGNALS

SM_RCOMP1 RC6 1 2 80.6_0402_1%

SM_RCOMP2 RC7 1 2 100_0402_1%

+3.3V_RUN M1 GPP_D22/SPI1_IO3 +3.3V_ALW_PCH

BB13 RC12 1K_0402_5%

G2 BA12 RC14 1K_0402_5%

<33> PCH_SPI_D0_R1 PCH_SPI_CLK_R1 3 6 PCH_SPI_CLK_0_R CLK_PCI_DOCK 2 1 PCH_SMB_ALERT# 2 1

4 5 27P_0402_50V8J EMC@ RC23 2.2K_0402_5%

@RC30 1K_0402_5% 33_0804_8P4R_5%

1 2 PCH_SPI_D3_R1 @RPC2 LOW(DEFAULT) DISABLE

1 2 3.3V_TP_EN Reserve AP7 GPP_B15/GSPI0_CS# P2 DIMM_TYPE

NO REBOOT STRAP +3.3V_ALW_PCH

@ RC184 HIGH DDR3L

BOOT BIOS Destination(Bit 10)

0_0402_5% 2 1 RC62 @ CC26

0_0402_5% 2 1RC244 @ @ RC296 0_0402_5%

100K_0402_5% @ RC344 10K_0402_5%

1 2 PCH_PCIE_WAKE# SIO_SLP_LAN# 1 2 INTRUDER# 1 2

A XDP_DBRESET# 1 ESD Request:place near CPU side A

<14> XDP_DBRESET# B 4 SYS_RESET#_R 1 2 SYS_RESET#

@ RC227 8.2K_0402_5% @ UC12

Compal Electronics, Inc.

+3.3V_RUN <32> PECI_EC A54 CATERR#

Service Mode Switch:

A TOP SWAP STRAP Flash Descriptor Security override A

HIGH ENABLE HIGH DISABLE

CFG[2][5][6][7] for SKYLAKE-H CPU CFG strap pin

+3.3V_RUN Place near JXDP1.41 XDP_TMS 1 2

+VCC_CORE: 0.3~1.35V +VCC_CORE +VCC_CORE

VCCOPC,VCCOPC_1P8,VCCEOPIO for SKYLAKE-U 2+3e +1.0V_PRIM +3.3V_RUN

8/21 CRB1.0 , DG0.9

CAD Note: Place the PU resistors close to CPU

CAD Note: Place the PU resistors close to CPU

RC208close to CPU 300 - 1500mils

+1.2V_MEM_CPUCLK +1.2V_MEM +1.0V_VCCST source

1 1 1 1 1 1 1 BB32 AM30 INTEL PDG 1.0

SIO_SLP_S3# HIGH HIGH LOW

AND HIGH LOW LOW

+VCCPLL_OC source +1.2V_MEM +VCC_SFR_OC

<8,11,18,32,41,46,47,48> SIO_SLP_SUS# B 4 1 TR=12.5us@Vin=1.05V

close UC1.AL1 and <120mil +1.0V_MPHYGT

@ RC235 0_0402_5% T19

1 2 1 close UC1.N18 and <120mil

1 1 Pop PJP35 & Depop UZ20/RZ83/CZ84

8/26 vender suggest depop

LC2 +1.0V_PRIM +1.0V_CLK4 +1.0V_PRIM

@ RC173 0_0402_5% @ CZ84 1U_0402_6.3V6K 2