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1 1
LCFC Confidential
G Project M/B Schematics Document
2
AMD FP4 Bristol Ridge and Stoney Ridge SOC with DDRVI 2
AMD R16M-M1-30
2015-06-06
REV:1.0
3 3
4 4
LCFC confidential
File Name : Toronto
LH
S3 Package: 23 mmX 23mm 4x Gen3/8x GenJfBristol ridgem Memory BUS (DDR4 )
Single Channel B DDR4-SO-DIMM XI DDR4 DRAM DOWN
VRAM 256* 16 -
PEG 0 3/ PEG 0~7
^
1
DDR3L*4 2GB
1.2V DDR4 1866MT/S
Li UP TO 8G x 1 4pcs x!6 1
USB Left
HDMl x4 Lane Port /
USB 3.0 lx
USB 2.0 lx
rUSB 2.0 Port5 ! "
HDMl Conn.
USB 3.0 Portl :
Int. MIC Conn. USB 2.0 DB board reserved USB 3.0 board for Z
USB 2.0 lx
USB 3.0 lx
m 37mm*2 9mm «-
SATA ODD
SATA Portl
SATA Genl n i l
dllii USB 2.0 lx NGFF Card
WLAN& BT
PCle lx Key E
PCIe Portl
USB2.0 Port 2
LAN Realtek
3
RJ45 Conn.
^ RTL8111GUL
PCIe Port 2
PCIe lx
SPI BUS SPI ROM
8 MB
Sub-board for 14
USB BOARD 3
HD Audio
TP BOARD
mm TPM LPC
Codec SPK Conn. reserve
Conexant~CXI 1802 33Z “ r '
1
Sub-board for 15
EC
IT 8886 HE - AXLQFP 128 USB BOARD
WWW.AliSaler.Com
A B C D E
EC_SMB_DA1 +3VL X V X X X X V X X X 0
1
GFX ST
EC_SMB_CK2
IT886H 2 GPU
EC_SMB_DA2 +3VS V X X X V V X X X X 3 BR
+3VS_VGA 1.8VS
4 GPU
EC_SMB_CK3 5
IT886H
X X X X X X X X V X N/A
EC_SMB_DA3 +3VALW 6
7
APU_SCLK0
APU
APU_SDATA0
+3VS X X X V V X X X X X S4GX4@ X76 SAMSUNG 2G
M4GX4@ X76 MICRON 2G
H4GX4@ X76 HYNIX 2G
VRAM SAMSUNG 2G
S2G@
EC SM Bus0 address EC SM Bus1 address EC SM Bus2 address EC SM Bus3 address M2G@ MICRON 2G
4
Device Address Device Address Device Address Device Address H2G@ HYNIX 2G 4
PMIC ? Battery 0X16 Thermal Sensor 1001_100xb(reserve) Vcore VR ?
HDMI@ HDMI Logo
GFxcore VR ? Charger 0001 0010 b GPU 0x41(default)
APU SB-TSI releate to F3x1E4[SbiAddr] or
Address Select Pins setting
APU SM Bus address Security Classification LC Future Center Secret Data Title
Device Address
Issued Date 2013/08/15 Deciphered Date 2013/08/15 Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
DDR4 SO-DIMM ? AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
WLAN RSVD MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG516
Date: Tuesday, April 12, 2016 Sheet 3 of 51
A B C D E
5 4 3 2 1
UC2B
PCIE
D D
U10 R1
U9 P_GPP_RXP0 P_GPP_TXP0 R2
P_GPP_RXN0 P_GPP_TXN0
PCIE_PRX_DTX_P1 T6 R4 PCIE_PTX_DRX_P1 0.1U_0201_6.3V6-K 1 2 CC1 PCIE_PTX_C_DRX_P1
31 PCIE_PRX_DTX_P1 PCIE_PRX_DTX_N1 P_GPP_RXP1 P_GPP_TXP1 PCIE_PTX_DRX_N1 0.1U_0201_6.3V6-K 1 PCIE_PTX_C_DRX_N1 PCIE_PTX_C_DRX_P1 31
T5 R3 2 CC2
WLAN 31 PCIE_PRX_DTX_N1 P_GPP_RXN1 P_GPP_TXN1 PCIE_PTX_C_DRX_N1 31 WLAN
PCIE_PRX_DTX_P2 T9 N1 PCIE_PTX_DRX_P2 0.1U_0201_6.3V6-K 1 2 CC3 PCIE_PTX_C_DRX_P2
28 PCIE_PRX_DTX_P2 PCIE_PRX_DTX_N2 P_GPP_RXP2 P_GPP_TXP2 PCIE_PTX_DRX_N2 0.1U_0201_6.3V6-K 1 PCIE_PTX_C_DRX_N2 PCIE_PTX_C_DRX_P2 28
T8 N2 2 CC4
LAN 28 PCIE_PRX_DTX_N2 P_GPP_RXN2 P_GPP_TXN2 PCIE_PTX_C_DRX_N2 28 LAN
P7 N4
+0.95VS P6 P_GPP_RXP3 P_GPP_TXP3 N3
P_GPP_RXN3 P_GPP_TXN3
RC1 1 2 196_0402_1% P_TX_ZVDD U7 U6 P_RX_ZVDD 196_0402_1% 1 2 RC3
P_ZVDDP P_ZVSS/P_RX_ZVDDP
A A
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5 4 3 2 1
DDRB_DQS[0..7]
12,13 DDRB_DQS[0..7]
DDRB_DQS#[0..7]
Stoney Ridge not support ChannelA 12,13 DDRB_DQS#[0..7]
UC2A UC2I
MEMORY A MEMORY B
12,13 DDRB_MA[13..0] DDRB_MA0 DDRB_DQ0 DDRB_DQ[63..0] 12,13
AE28 H17 AG31 A25
Y27 MA_ADD0 MA_DATA0 J17 DDRB_MA1 AC30 MB_ADD0 MB_DATA0 C25 DDRB_DQ1
Y29 MA_ADD1 MA_DATA1 F20 DDRB_MA2 AC31 MB_ADD1 MB_DATA1 C27 DDRB_DQ2
Y26 MA_ADD2 MA_DATA2 H20 DDRB_MA3 AB32 MB_ADD2 MB_DATA2 D27 DDRB_DQ3
W28 MA_ADD3 MA_DATA3 E17 DDRB_MA4 AA32 MB_ADD3 MB_DATA3 B24 DDRB_DQ4
D
W29 MA_ADD4 MA_DATA4 F17 DDRB_MA5 AA33 MB_ADD4 MB_DATA4 B25 DDRB_DQ5 DQ bit swapping is allowed in a byte lane. D
W26 MA_ADD5 MA_DATA5 K18 DDRB_MA6 AA31 MB_ADD5 MB_DATA5 B27 DDRB_DQ6
U29 MA_ADD6 MA_DATA6 E20 DDRB_MA7 Y33 MB_ADD6 MB_DATA6 A27 DDRB_DQ7
W25 MA_ADD7
MA_ADD8
MA_DATA7 DDRB_MA8 AA30 MB_ADD7
MB_ADD8
MB_DATA7 APU SO-DIMM DRAM APU SO-DIMM DRAM
U26
MA_ADD9 MA_DATA8
A21 DDRB_MA9 W32
MB_ADD9 MB_DATA8
A29 DDRB_DQ8 DA0 DQ2 UD1.0 DA32 DQ39 UD3.1
AG29 C21 DDRB_MA10 AG32 C29 DDRB_DQ9
MA_ADD10 MA_DATA9 MB_ADD10 MB_DATA9
U27
MA_ADD11 MA_DATA10
C23 DDRB_MA11 Y32
MB_ADD11 MB_DATA10
B32 DDRB_DQ10 DA1 DQ7 UD1.3 DA33 DQ36 UD3.6
T28 D23 DDRB_MA12 W33 D32 DDRB_DQ11
MA_ADD12 MA_DATA11 MB_ADD12 MB_DATA11
AK26
MA_ADD13 MA_DATA12
B20 DDRB_MA13 AL31
MB_ADD13 MB_DATA12
B28 DDRB_DQ12 DA2 DQ6 UD1.4 DA34 DQ35 UD3.2
T26 B21 DDRB_BG1 W30 B29 DDRB_DQ13
MA_ADD14/MA_BG1 MA_DATA13 12 DDRB_BG1 MB_ADD14/MB_BG1 MB_DATA13
T25
MA_ADD15/MA_ACT_L MA_DATA14
B23
12,13 DDRB_ACT#
DDRB_ACT# V32
MB_ADD15/MB_ACT_L MB_DATA14
A31 DDRB_DQ14 DA3 DQ0 UD1.5 DA35 DQ34 UD3.7
A23 C31 DDRB_DQ15
MA_DATA15 MB_DATA15
DA4 DQ1 UD1.2 DA36 DQ37 UD3.5
G22 E30 DDRB_DQ16
MA_DATA16 MB_DATA16
AG26
MA_BANK0 MA_DATA17
H22
12,13 DDRB_BA0
DDRB_BA0 AH32
MB_BANK0 MB_DATA17
E31 DDRB_DQ17 DA5 DQ5 UD1.7 DA37 DQ32 UD3.3
AG27 E25 DDRB_BA1 AG33 G33 DDRB_DQ18
MA_BANK1 MA_DATA18 12,13 DDRB_BA1 MB_BANK1 MB_DATA18
T29
MA_BANK2/MA_BG0 MA_DATA19
G25
12,13 DDRB_BG0
DDRB_BG0 W31
MB_BANK2/MB_BG0 MB_DATA19
G32 DDRB_DQ19 DA6 DQ4 UD1.1 DA38 DQ38 UD3.4
J20 C33 DDRB_DQ20
MA_DATA20 12,13 DDRB_DM[7..0] MB_DATA20
E19
MA_DM0 MA_DATA21
E22 DDRB_DM0 D25
MB_DM0 MB_DATA21
D33 DDRB_DQ21 DA7 DQ3 UD1.6 DA39 DQ33 UD3.0
D21 H23 DDRB_DM1 D29 G30 DDRB_DQ22
MA_DM1 MA_DATA22 MB_DM1 MB_DATA22
K21
MA_DM2 MA_DATA23
J23 DDRB_DM2 E33
MB_DM2 MB_DATA23
G31 DDRB_DQ23 DA8 DQ12 UD1.11 DA40 DQ45 UD3.15
F29 DDRB_DM3 J33
MA_DM3 MB_DM3
AP28
MA_DM4 MA_DATA24
F26 DDRB_DM4 AR30
MB_DM4 MB_DATA24
J30 DDRB_DQ24 DA9 DQ13 UD1.9 DA41 DQ44 UD3.9
AV26 E27 DDRB_DM5 AW30 J31 DDRB_DQ25
MA_DM5 MA_DATA25 MB_DM5 MB_DATA25
AR22
MA_DM6 MA_DATA26
J26 DDRB_DM6 BC30
MB_DM6 MB_DATA26
L33 DDRB_DQ26 DA10 DQ11 UD1.12 DA42 DQ47 UD3.14
BC22 J27 DDRB_DM7 BC26 L32 DDRB_DQ27
MA_DM7 MA_DATA27 MB_DM7 MB_DATA27
K29
MA_DM8 MA_DATA28
H25 @ TC20 1 DDRB_DM8 N33
MB_DM8 MB_DATA28
H32 DDRB_DQ28 DA11 DQ10 UD1.14 DA43 DQ46 UD3.8
E26 H33 DDRB_DQ29
MA_DATA29 MB_DATA29
H19
MA_DQS_H0 MA_DATA30
G28 DDRB_DQS0 B26
MB_DQS_H0 MB_DATA30
L30 DDRB_DQ30 DA12 DQ9 UD1.13 DA44 DQ40 UD3.13
G19 G29 DDRB_DQS#0 A26 L31 DDRB_DQ31
MA_DQS_L0 MA_DATA31 MB_DQS_L0 MB_DATA31
B22
MA_DQS_H1
DDRB_DQS1 B30
MB_DQS_H1
DA13 DQ8 UD1.15 DA45 DQ41 UD3.11
A22 AN26 DDRB_DQS#1 A30 AN31 DDRB_DQ32
MA_DQS_L1 MA_DATA32 MB_DQS_L1 MB_DATA32
F23
MA_DQS_H2 MA_DATA33
AP29 DDRB_DQS2 F32
MB_DQS_H2 MB_DATA33
AP32 DDRB_DQ33 DA14 DQ15 UD1.8 DA46 DQ43 UD3.12
E23 AR26 DDRB_DQS#2 E32 AT32 DDRB_DQ34
C MA_DQS_L2 MA_DATA34 MB_DQS_L2 MB_DATA34 C
G27
MA_DQS_H3 MA_DATA35
AP24 DDRB_DQS3 K32
MB_DQS_H3 MB_DATA35
AU32 DDRB_DQ35 DA15 DQ14 UD1.10 DA47 DQ42 UD3.10
F27 AN29 DDRB_DQS#3 J32 AN33 DDRB_DQ36
MA_DQS_L3 MA_DATA36 MB_DQS_L3 MB_DATA36
AP25
MA_DQS_H4 MA_DATA37
AN27 DDRB_DQS4 AR32
MB_DQS_H4 MB_DATA37
AN32 DDRB_DQ37 DA16 DQ20 UD2.7 DA48 DQ55 UD4.0
AP26 AR29 DDRB_DQS#4 AR33 AR31 DDRB_DQ38
MA_DQS_L4 MA_DATA38 MB_DQS_L4 MB_DATA38
AW27
MA_DQS_H5 MA_DATA39
AR27 DDRB_DQS5 AW32
MB_DQS_H5 MB_DATA39
AT33 DDRB_DQ39 DA17 DQ16 UD2.3 DA49 DQ49 UD4.3
AV27 DDRB_DQS#5 AW33
MA_DQS_L5 MB_DQS_L5
AV22
MA_DQS_H6 MA_DATA40
AU26 DDRB_DQS6 BA29
MB_DQS_H6 MB_DATA40
AU30 DDRB_DQ40 DA18 DQ19 UD2.4 DA50 DQ54 UD4.2
AU22 AV29 DDRB_DQS#6 AY29 AV32 DDRB_DQ41
MA_DQS_L6 MA_DATA41 MB_DQS_L6 MB_DATA41
BA21
MA_DQS_H7 MA_DATA42
AU25 DDRB_DQS7 BA25
MB_DQS_H7 MB_DATA42
BA33 DDRB_DQ42 DA19 DQ18 UD2.1 DA51 DQ48 UD4.7
AY21 AW25 DDRB_DQS#7 AY25 AY32 DDRB_DQ43
MA_DQS_L7 MA_DATA43 MB_DQS_L7 MB_DATA43
L27
MA_DQS_H8 MA_DATA44
AU29 @ TC8 1 DDRB_DQS8 P32
MB_DQS_H8 MB_DATA44
AU33 DDRB_DQ44 DA20 DQ17 UD2.0 DA52 DQ53 UD4.5
L26 AU28 @ TC9 1 DDRB_DQS#8 N32 AU31 DDRB_DQ45
MA_DQS_L8 MA_DATA45 MB_DQS_L8 MB_DATA45 DQ21
MA_DATA46
AW26
MB_DATA46
AW31 DDRB_DQ46 DA21 UD2.2 DA53 DQ52 UD4.1
AE25 AT25 DDRB_CLK0 AE33 AY33 DDRB_DQ47
MA_CLK_H0 MA_DATA47 12 DDRB_CLK0 MB_CLK_H0 MB_DATA47
AE26
MA_CLK_L0 12 DDRB_CLK0#
DDRB_CLK0# AE32
MB_CLK_L0
DA22 DQ22 UD2.6 DA54 DQ50 UD4.6
AD26 AV23 DDRB_CLK1 AE30 BC31 DDRB_DQ48
AD27 MA_CLK_H1 MA_DATA48 AW23
SO-DIMM0 12 DDRB_CLK1 DDRB_CLK1# AE31 MB_CLK_H1 MB_DATA48 BB30 DDRB_DQ49 DA23 DQ23 UD2.5 DA55 DQ51 UD4.4
MA_CLK_L1 MA_DATA49 12 DDRB_CLK1# DDRB_CLK2 MB_CLK_L1 MB_DATA49 DDRB_DQ50
AB28 AV20 AD32 BB28
MA_CLK_H2 MA_DATA50 13 DDRB_CLK2 MB_CLK_H2 MB_DATA50
AB29
MA_CLK_L2 MA_DATA51
AW20
13 DDRB_CLK2#
DDRB_CLK2# AD33
MB_CLK_L2 MB_DATA51
AY27 DDRB_DQ51 DA24 DQ24 UD2.9 DA56 DQ61 UD4.14
AB25 AR23 AC33 BB32 DDRB_DQ52
AB26 MA_CLK_H3 MA_DATA52 AT23
SO-DIMM1 AC32 MB_CLK_H3 MB_DATA52 BA31 DDRB_DQ53 DA25 DQ28 UD2.11 DA57 DQ56 UD4.10
MA_CLK_L3 MA_DATA53 AR20 MB_CLK_L3 MB_DATA53 BC29 DDRB_DQ54
MA_DATA54 MB_DATA54 DQ30
N29
MA_RESET_L MA_DATA55
AT20
12,13 MEM_MB_RST#
RC240 1 2 10_0402_5% MEM_MB_RST#_R T33
MB_RESET_L MB_DATA55
BB29 DDRB_DQ55 DA26 UD2.12 DA58 DQ63 UD4.11
AE29 MEM_MB_EVENT#AG30
MA_EVENT_L 12 MEM_MB_EVENT# MB_EVENT_L
MA_DATA56
BB23
MB_DATA56
BB27 DDRB_DQ56 DA27 DQ26 UD2.8 DA59 DQ58 UD4.12
P27 BB22 DDRB_CKE0 U32 BB26 DDRB_DQ57
MA_CKE0 MA_DATA57 12,13 DDRB_CKE0 MB_CKE0 MB_DATA57
P29
MA_CKE1 MA_DATA58
BB20
12 DDRB_CKE1
DDRB_CKE1 U33
MB_CKE1 MB_DATA58
BB24 DDRB_DQ58 DA28 DQ25 UD2.13 DA60 DQ60 UD4.13
AY19 AY23 DDRB_DQ59
MA_DATA59 MB_DATA59 DQ29
MA_DATA60
BA23
MB_DATA60
BA27 DDRB_DQ60 DA29 UD2.15 DA61 DQ57 UD4.9
BC23 BC27 DDRB_DQ61
MA_DATA61 MB_DATA61 DQ27
AK27
MA0_ODT0 MA_DATA62
BC21
SO-DIMM1 12 DDRB_ODT0
DDRB_ODT0 AL30
MB0_ODT0 MB_DATA62
BC25 DDRB_DQ62 DA30 UD2.14 DA62 DQ59 UD4.15
AL26 BB21 DDRB_ODT1 AM32 BB25 DDRB_DQ63
AH25 MA0_ODT1 MA_DATA63 SO-DIMM 12 DDRB_ODT1 DDRB_ODT2 AJ32 MB0_ODT1 MB_DATA63
DA31 DQ31 UD2.10 DA63 DQ62 UD4.8
MA1_ODT0 13 DDRB_ODT2 MB1_ODT0
AL25 K26 AM33 N30
MA1_ODT1 MA_CHECK0 K28 MB1_ODT1 MB_CHECK0 N31
B B
AH26 MA_CHECK1 N26 DDRB_CS0# AJ33 MB_CHECK1 R33
MA0_CS_L0 MA_CHECK2 12 DDRB_CS0# DDRB_CS1# MB0_CS_L0 MB_CHECK2
AL29 N28 AL32 R32
AH29 MA0_CS_L1 MA_CHECK3 J29
SO-DIMM0 12 DDRB_CS1# DDRB_CS2# AJ30 MB0_CS_L1 MB_CHECK3 M32
MA1_CS_L0 MA_CHECK4 13 DDRB_CS2# MB1_CS_L0 MB_CHECK4
AL28 K25 AL33 M33
MA1_CS_L1 MA_CHECK5 L29
SO-DIMM1 MB1_CS_L1 MB_CHECK5 R30
MA_CHECK6 N25 MB_CHECK6 R31
AG24 MA_CHECK7 DDRB_MA16_RAS# AH33 MB_CHECK7
MA_RAS_L/MA_RAS_L_ADD16 12,13 DDRB_MA16_RAS# DDRB_MA15_CAS# AK32 MB_RAS_L/MB_RAS_L_ADD16
AK29 +1.2V +1.2V
MA_CAS_L/MA_CAS_L_ADD15 12,13 DDRB_MA15_CAS# DDRB_MA14_WE# MB_CAS_L/MB_CAS_L_ADD15
AH28 AJ31
MA_WE_L/MA_WE_L_ADD14 12,13 DDRB_MA14_WE# MB_WE_L/MB_WE_L_ADD14
B19 AD29 MA_ZVDDIO RC33 1 @ 2 39.2_0402_1% @ TC70 1 APU_M_VREFDQ A19 AF32 MB_ZVDDIO RC10 1 2 39.2_0402_1%
+MEM_VREF T32 MA_VREFDQ MA_ZVDDIO_MEM_S MB_VREFDQ MB_ZVDDIO_MEM_S
M_VREF
FP4 REV 0.93 FP4 REV 0.93
@ AMD-CARRIZO_FP4-BGA968 @ AMD-CARRIZO_FP4-BGA968
+1.2V
+1.2V
1
RC4
1K_0402_1% RC9 1 2 1K_0402_5% MEM_MB_EVENT#
2
@ +MEM_VREF
1000P_0201_50V7-K
.047U_0201_6.3V6K
0.1U_0201_6.3V6-K
1
1 1 1
CC13
CC14
CC15
RC5
A A
1K_0402_1%
2 2 2
2
@ @ @
@
+3VS_APU
UC2C RPC18
APU_DDC_CLK 1 4
APU_DDC_DATA 2 3
DISPLAY/SVI2/JTAG/TEST
2.2K_0404_4P2R_5%
APU_DP2_TX0+ B6 A9 DP_2K_ZVSS RC55 1 2 2K_0402_1%
26 APU_DP2_TX0+ APU_DP2_TX0- DP2_TXP0 DP_ZVSS DP_150_ZVSS
A6 B9 RC12 1 2 150_0402_1%
+1.8VS 26 APU_DP2_TX0- DP2_TXN0 DP_AUX_ZVSS DP_ENBKL APU_EDP_HPD
G5 RC35 1 2 100K_0402_5%
DP to VGA APU_DP2_TX1+ D7 DP_BLON G6 DP_ENVDD Hot Plug Detect pins is I-IO18-S,but 3.3V tolerant.
26 APU_DP2_TX1+ APU_DP2_TX1- DP2_TXP1 DP_DIGON DP_EDP_PWM
C7 F11
26 APU_DP2_TX1- DP2_TXN1 DP_VARY_BL
1
RC18 A7 +1.8VS
DP2_TXP2 APU_DP2_AUX RPC11
300_0402_5% B7 H9
D DP2_TXN2 DP2_AUXP APU_DP2_AUX# APU_DP2_AUX 26 D
G9 ALERT# 3 2
D9 DP2_AUXN E9 APU_DP2_HPD APU_DP2_AUX# 26 DP to VGA APU_PROCHOT#_R 4 1
APU_DP2_HPD 26
2
1
APU_EDP_TX0- E1 AL24 TEST411 1 @ TC17
1 23 APU_EDP_TX0- DP0_TXN0 TEST411
RC19 CC215 P24 TEST4 1 @ TC13 +3VALW_APU RC70
300_0402_5% 1000P_0201_50V7-K APU_EDP_TX1+ E3 TEST4 N24 TEST5 1 @ TC14 4.7K_0402_5%
eDP 23 APU_EDP_TX1+ APU_EDP_TX1- E4 DP0_TXP1 TEST5 AN24
23 APU_EDP_TX1- DP0_TXN1 TEST6
2
2 AB8
@
2
2
D1 TEST9 Y9 RC71
APU_PWROK D2 DP0_TXP2 TEST10 B10 APU_TEST14_BP0 RC21 1 @ 2 1K_0402_5% 10K_0402_5%
DP0_TXN2 TEST14 APU_TEST15_BP1 PCH_EDP_PWM 23
D11 1 @ TC18
C1 TEST15 A10 APU_TEST16_BP2 RC23 1 @ 2 1K_0402_5%
PLACE CC17 CAPS CLOSE TO APU,CRB reserve 27pf
1
B1 DP0_TXP3 TEST16 C11 APU_TEST17_BP3 RC24 1 @ 2 1K_0402_5%
1 DP0_TXN3 TEST17
3
B11 APU_TEST11_BP4 RC1891 @ 2 1K_0402_5% D
CC17 RC279 1 @ 2 0_0402_5% APU_SVT_RA C15 TEST11 A14 APU_TEST18_PLLTEST1 4 1 +3VS_APU 5 QC8B
220P_0201_25V7-K 50 APU_SVT APU_SVC_RA SVT0 TEST18 APU_TEST19_PLLTEST0 G
RC213 1 @ 2 0_0402_5% D17 B14 3 2 DMN5L06DWK-7 2N SOT363-6
2 50 APU_SVC APU_SVD_RA SVC0 TEST19
@ RC215 1 @ 2 0_0402_5% D19 1K_0404_4P2R_5%
50 APU_SVD SVD0 +1.8VS S
RPC14
4
6
RC280 1 @ 2 0_0402_5% APU_GFX_SVT_RA B15 A13 APU_TEST28_H_PLLCHARZ 1 @ TC21 D
C 51 APU_GFX_SVT APU_GFX_SVC_RA SVT1 TEST28_H APU_TEST28_L_PLLCHARZ DP_EDP_PWM C
RC217 1 @ 2 0_0402_5% B16 B13 1 @ TC23 RC2591 @ 2 1K_0402_5% 2 QC8A
51 APU_GFX_SVC APU_GFX_SVD_RA SVC1 TEST28_L APU_TEST31_MEM_TEST G
RC219 1 @ 2 0_0402_5% A18 P26 1 @ TC25 RC28 1 2 1K_0402_5% DMN5L06DWK-7 2N SOT363-6
+1.8VS +1.8VS 51 APU_GFX_SVD SVD1 TEST31 APU_TEST36_STEREOSYNC
E11 RC27 1 @ 2 1K_0402_5%
DP_STEREOSYNC/TEST36
1
APU_SIC B18 A17 APU_TEST37 RC29 1 @ 2 1K_0402_5% S
1
APU_SID C17 SIC TEST37 RC30 1 @ 2 1K_0402_5% RC11
SID 100K_0402_5%
APU_RST# D15
RESET_L
4
3
APU_PWROK
50,51 APU_PWROK
C19 Test36 pull high for APU read EDID by HDMI DDC signal
2
RPC10 PWROK RC2051 @ 2 0_0402_5%
5
D13 AY18 1
APU_TMS G15 TCK VDDP_SENSE TC26 @
QC6B TMS
2
1
APU_TRST# J14 H12 APU_VSS_SEN_L RC2361 @ 2 0_0402_5%
G
2
APU_SID 1 6
S
EC_SMB_DA2 16,30,36
2
RC73
D
PCH_ENVDD 23
FP4 REV 0.93 10K_0402_5%
QC6A @ @
DMN5L06DWK-7 2N SOT363-6 AMD-CARRIZO_FP4-BGA968
3
D
5 QC9B
G DMN5L06DWK-7 2N SOT363-6
APU_VDDNB_SEN_H 1 @ TC27
S
@
4
6
APU_VDDCORE_SEN_H 1 @ TC28 D
DP_ENVDD 2 QC9A
APU_VDD_SEN_L 1 @ TC29 G DMN5L06DWK-7 2N SOT363-6
B B
@
1
APU_VDDGFX_SEN_H 1 @ TC30 S
1
RC13
APU_VDDGFX_SEN_L 1 @ TC31 100K_0402_5%
@
2
RC206 1 @ 2 0_0402_5%
With HDT+ Header LCD Power IC can change for PCH_ENVDD for cost down
+1.8VS +1.8VS
+3VS_APU
+1.8VS JHDT1 @ RPC5 +1.8VS +1.8VS
1 2 APU_TCK 8 1
1 2
2
7 2
3 4 APU_TMS 6 3 RC77
3 4 1
2
1
5 4 +3VALW_APU 2.2K_0402_5%
RC7 5 6 APU_TDI CC25 RC32 RC36
5 6 @
1K_0402_5% 1K_0804_8P4R_5% 0.1U_0201_6.3V6-K 300_0402_5% 300_0402_5%
1
2
7 8 APU_TDO HDT@ 2
7 8 RC75
PCH_ENBKL 23
1
2
APU_TRST# RC76 1 HDT@ 2 33_0402_5% APU_TRST#_R 9 10 APU_PWROK_BUF UC6 10K_0402_5%
9 10 APU_PWROK 3 4 APU_PWROK_BUF @
11 12 APU_RST#_BUF 2A 2Y
2
1
11 12
3
2 5 D
CC84 13 14 APU_DBRDY GND VCC 5 QC10B
13 14 APU_RST# 1 6 APU_RST#_BUF G
0.01U_0201_10V6K 1A 1Y DMN5L06DWK-7 2N SOT363-6
1 15 16 RC273 1 HDT@ 2 33_0402_5% APU_DBREQ#
15 16 S
@
HDT@ SN74LVC2G07YZPR_WCSP6
4
8
7
6
5
6
17 18 APU_TEST19_PLLTEST0 D
RPC17 17 18 DP_ENBKL 2 QC10A
10K_0804_8P4R_5% 19 20 APU_TEST18_PLLTEST1 G DMN5L06DWK-7 2N SOT363-6
19 20
HDT@ @
1
S
1
2
3
4
1
A RC14 A
SAMTE_ASP-136446-07-B APU_DBREQ# APU_TDI 100K_0402_5%
@
2 2
2
RC2071 2 0_0402_5%
CC213 CC212 PCH_ENBKL con EC 1.8V level GPI pin cost down
0.01U_0201_10V6K 0.01U_0201_10V6K
1 HDT@ 1 @
Security Classification LC Future Center Secret Data Title
Issued Date 2013/08/15 Deciphered Date 2013/08/15 FP4 (DISPLAY/CLK/MISC)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG516
Date: Tuesday, April 12, 2016 Sheet 6 of 51
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5 4 3 2 1
+3VALW_APU
RC46 1 2 33_0402_5% LPC_RST#_R
30,36 APU_LPC_RST#
1
CC20
2
150P_0402_50V8-J
RC39 RC40 RC41 RC257 RC265 RC263 RC268
2
10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 2K_0402_5%
15@ UMA@ NOKBL@ @ @ @ @
1
BOARD_ID0
RC38 1 2 33_0402_5% PCIE_RST#_R BOARD_ID1
15,28,31 PLT_RST# BOARD_ID2
BOARD_ID3
ID2--5 internal pull up 40K
ID6 internal pull low 40K
1
BOARD_ID4
1
RC43 BOARD_ID5
@ 100K_0402_5% CC19 BOARD_ID6
D D
100P_0201_25V8J
2 2
2
RC47 RC269 RC49 RC258 RC264 RC266 RC267
10K_0402_5% 10K_0402_5% 2K_0402_5% 2K_0402_5% 2K_0402_5% 2K_0402_5% 10K_0402_5%
14@ PX@ KBL@ @ @ @ @
1
+1.8VALW
RC243 2 @ 1 0_0402_5%
1
Connected to 10-ms RC-delay circuit on VDD_18_S5 power rail.
RC53
1K_0402_5%
(CRB PWR Dealy: 22K/0.1uF) UC2D
ACPI/SD/AZ/GPIO/RTC/I2C/UART/MISC
DC1 LPC_RST#_R BB12 BB2 @1 TC61
2
1 2 RSMRST#_R PCIE_RST#_R AN7 LPC_RST_L SD0_WP/EGPIO101 BB5 @1
36 EC_RSMRST# PCIE_RST_L/EGPIO26 SD0_PWR_CTRL/AGPIO102 TC44
BC2 @1 TC71
RB751V-40_SOD323-2 RSMRST#_R AE4 SD0_CD/AGPIO25 BB4 @1
1 RSMRST_L SD0_CLK/EGPIO95 TC45
EC set RSMRST OD output CC21
SD0_CMD/EGPIO96
AY5 @1
TC59
0.1U_0402_25V6 PBTN_OUT# RC191 1 @ 2 0_0402_5% PWRBTN#_R AE1
36 PBTN_OUT# SYS_PWRGD_R PWR_BTN_L/AGPIO0
BC9
2 SYS_RESET# AF2 PWR_GOOD
11 SYS_RESET# PCIE_WAKE#_RA SYS_RESET_L/AGPIO1
AG2 BC3 @1 TC62
WAKE_L/AGPIO2 SD0_DATA0/EGPIO97 BA3 @1 TC63
PM_SLP_S3# RC193 1 @ 2 0_0402_5% PM_SLP_S3#_R AK7 SD0_DATA1/EGPIO98 BC5 @1 TC64
36 PM_SLP_S3# PM_SLP_S5# RC194 PM_SLP_S5#_R SLP_S3_L SD0_DATA2/EGPIO99
1 @ 2 0_0402_5% AH5 BA5 @1 TC65
36 PM_SLP_S5# SLP_S5_L SD0_DATA3/EGPIO100 BB6 @1 TC72
BOARD_ID1 AE8 SD0_LED/EGPIO93
APU_S5_MUX_CTRL AH8 S0A3_GPIO/AGPIO10 BA15 APU_SMB_CLK
9 APU_S5_MUX_CTRL S5_MUX_CTRL/EGPIO42 SCL0/I2C2_SCL/EGPIO113 APU_SMB_DATA APU_SMB_CLK 12,31
TEST0 AH6 SDA0/I2C2_SDA/EGPIO114
AY17
RPC2
APU_SMB_DATA 12,31 DIMM1, DIMM2, Mini CARD
TEST1 AK8 TEST0 AG5 SCL1 1 4
TEST2 AE3 TEST1/TMS SCL1/I2C3_SCL/AGPIO19 AG4 SDA1 2 3
+3VS_APU TEST2 SDA1/I2C3_SDA/AGPIO20 @
C KBRST# AY15 10K_0404_4P2R_5% C
36 KBRST# ESPI_RESET_L/KBRST_L/AGPIO129
BC19
36 GATEA20 GA20IN/AGPIO126
1
AD7 AL5
36 EC_SCI# LPC_PME_L/AGPIO22 AGPIO3 AGPIO3 11
RC72 BB13 AL6
10K_0402_5% LPC_SMI_L/AGPIO86 AGPIO4 AJ1 AGPIO5
@ AC_PRESENT AG3 AGPIO5 AJ3 LDT_RST_L @1 TC67 +3VS_APU
36 AC_PRESENT BOARD_ID4 AC_PRES/USB_OC4_L/IR_RX0/AGPIO23 AGPIO6/LDT_RST_L LDT_PWROK
AD5 AH1 @1 TC68
2
CC38 1 2 USB_OC2# 2 3
RC84 RC85 RC20 0.1U_0201_6.3V6-K Max ESR < 65K ohm !!
2 32.768KHZ_12.5PF_202740-PG14 10K_0404_4P2R_5%
2.2K_0402_5% 1K_0402_5% 2.2K_0402_5%
20P_0402_50V8
20P_0402_50V8
PM_SLP_S5#
CC23
CC210
2
1K_0402_5%
1K_0402_5%
1K_0402_5%
GPU_CLKREQ#
RC260
RC261
RC262
RC65 1 PX@ 2 2K_0402_5%
RC98 1 PX@ 2 10K_0402_5% PXS_PWREN_R
RC101 1 @ 2 100K_0402_5% HDA_BITCLK RC90 1 BR@ 2 1K_0402_5%
BR@ BR@ BR@ HDA_SDIN0_R RC91 1 @ 2 10K_0402_5%
1
1
APU_SHUTDOWN# RC256 1 @ 2 2K_0402_5%
A A
RSMRST#_R RC87 1 2 100K_0402_5%
SYS_PWRGD_R RC89 1 2 100K_0402_5%
+3VS_APU
HDA_SDIN2 RC241 1 2 10K_0402_5%
HDA_SDIN1 RC242 1 2 10K_0402_5%
RC100 1 @ 2 10K_0402_5% VR_VGA_PWRGD
RC104 1 UMA@2 2K_0402_5%
UC2E
CLK/SATA/USB/SPI/LPC
SATA_PTX_DRX_P0 AU3 AP8 CLK_USB48M 1 @ TC69
34 SATA_PTX_DRX_P0 SATA_PTX_DRX_N0 SATA_TX0P USBCLK/25M_48M_OSC
AU4
34 SATA_PTX_DRX_N0 SATA_TX0N USB_RCOMP
HDD AP5 RC112 1 2 11.8K_0402_1%
SATA_PRX_DTX_N0 AV1 USB_ZVSS
34 SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 SATA_RX0N USB20_P0
AV2 AR2
34 SATA_PRX_DTX_P0 SATA_RX0P USB_HSD0P USB20_N0 USB20_P0 37
AR1 RIGHT USB (2.0)
SATA_PTX_DRX_P1 USB_HSD0N USB20_N0 37
AY2
34 SATA_PTX_DRX_P1 SATA_PTX_DRX_N1 SATA_TX1P USB20_P1
AY1 AR3
34 SATA_PTX_DRX_N1 SATA_TX1N USB_HSD1P USB20_N1 USB20_P1 37
ODD AR4 Right USB (2.0) for stoney ridge only
SATA_PRX_DTX_N1 USB_HSD1N USB20_N1 37
AW4
D 34 SATA_PRX_DTX_N1 SATA_PRX_DTX_P1 SATA_RX1N USB20_P2 D
AW3 AN2
34 SATA_PRX_DTX_P1 SATA_RX1P USB_HSD2P USB20_N2 USB20_P2 31
AN1 Blue Tooth
+0.95VS SATA_CALRN USB_HSD2N USB20_N2 31
RC113 1 2 1K_0402_1% AW1
RC114 1 2 1K_0402_1% SATA_CALRP AW2 SATA_ZVSS AN3 USB20_P3
SATA_ZVDDP USB_HSD3P USB20_N3 USB20_P3 23
RC270 1 2 10K_0402_5% EGPIO67 AT17 AN4 Camera
DEVSLP0/EGPIO67 USB_HSD3N USB20_N3 23
RC271 1 2 10K_0402_5% EGPIO70 AT12
RC143 1 2 10K_0402_5% AGPIO130 BB15 DEVSLP1/EGPIO70 AM1 USB20_P4
SATA_ACT_L/AGPIO130 USB_HSD4P USB20_N4 USB20_P4 33
AM2 Card Reader
USB_HSD4N USB20_N4 33
AU2
SATA_X1 AL2 USB20_P5
USB_HSD5P USB20_N5 USB20_P5 32
AL1 LEFT USB (3.0)
USB_HSD5N USB20_N5 32
AU1 AL3 USB20_P6
SATA_X2 USB_HSD6P USB20_N6 USB20_P6 37
AL4 Right USB (3.0) for Bristiol Ridge
USB_HSD6N USB20_N6 37
CLK_PCIE_GPU RC117 1 @ 2 0_0402_5% CLK_PCIE_GPU_R U4 AK2
15 CLK_PCIE_GPU CLK_PCIE_GPU# GFX_CLKP USB_HSD7P
RC118 1 @ 2 0_0402_5% CLK_PCIE_GPU#_R U3 AJ2
15 CLK_PCIE_GPU# GFX_CLKN USB_HSD7N
U1
U2 GPP_CLK0P USB3.0 port0 must map to USB2.0 port4,
GPP_CLK0N
CLK_PCIE_WLAN
USB3.0 port1 must map to USB2.0 port5,
RC119 1 @ 2 0_0402_5% CLK_PCIE_WLAN_R W4
31 CLK_PCIE_WLAN
31 CLK_PCIE_WLAN#
CLK_PCIE_WLAN# RC120 1 @ 2 0_0402_5% CLK_PCIE_WLAN#_R W3 GPP_CLK1P USB3.0 port2 must map to USB2.0 port6,
GPP_CLK1N
CLK_PCIE_LAN RC121 1 @ 2 0_0402_5% CLK_PCIE_LAN_R W1
USB3.0 port4 must map to USB2.0 port7
28 CLK_PCIE_LAN CLK_PCIE_LAN# GPP_CLK2P
RC122 1 @ 2 0_0402_5% CLK_PCIE_LAN#_R W2
28 CLK_PCIE_LAN# GPP_CLK2N
Y2
Y1 GPP_CLK3P
GPP_CLK3N
C C
TC53 @ 1 X14M_25M_48M_OSC BC10
X25M_48M_OSC AD2 USBSS_CALRN RC123 1 2 1K_0402_1% +0.95VALW
USB_SS_ZVSS AD1 USBSS_CALRP RC124 1 2 1K_0402_1%
48M_X1 T2 USB_SS_ZVDDP
X48M_X1 AA3
USB_SS_0TXP AA4
USB_SS_0TXN
48M_X2 T1 W9
X48M_X2 USB_SS_0RXP W8
RC125 1 TPM@ 2 22_0402_5% USB_SS_0RXN
30 TPM_CLK
RC126 1 2 3.3_0402_1% LPCCLK0 AW14 AA2 USB30_TX_P1
11,36 CLK_PCI_EC LPCCLK0/EGPIO74 USB_SS_1TXP USB30_TX_N1 USB30_TX_P1 32
RC127 1 @ 2 0_0402_5% LPCCLK1 AY13 AA1
11 LPC_CLK1 LPCCLK1/EGPIO75 USB_SS_1TXN USB30_TX_N1 32
LEFT USB (3.0)
+3VS_APU BB11 W5 USB30_RX_P1
30,36 LPC_AD0 LAD0 USB_SS_1RXP USB30_RX_N1 USB30_RX_P1 32
BA11 W6
30,36 LPC_AD1 LAD1 USB_SS_1RXN USB30_RX_N1 32
30,36 LPC_AD2 AY11
RC99 1 @ 2 10K_0402_5% PXS_RST# BA13 LAD2 AC1 USB30_TX_P2
30,36 LPC_AD3 LAD3 USB_SS_2TXP USB30_TX_P2 37
RC103 1 2 10K_0402_5% AV14 AC2 USB30_TX_N2
11,30,36 LPC_FRAME# LFRAME_L USB_SS_2TXN USB30_TX_N2 37
TC54 @ 1 BA1 Right USB (3.0) for Bristiol Ridge
BC14 ESPI_ALERT_L/LDRQ0_L Y6 USB30_RX_P2
30,36 SERIRQ SERIRQ/AGPIO87 USB_SS_2RXP USB30_RX_P2 37
BC11 Y7 USB30_RX_N2
30 LPC_CLKRUN# LPC_CLKRUN_L/AGPIO88 USB_SS_2RXN USB30_RX_N2 37
1 2 10K_0402_5% AGPIO21 AE9
RC149 LPC_PD_L/AGPIO21 AC4
USB_SS_3TXP AC3
EC_SPI_CLK RC209 1 @ 2 0_0402_5% SPI_CLK BC6 USB_SS_3TXN
36 EC_SPI_CLK EC_SPI_CS0# RC202 1 @ 2 0_0402_5% SPI_CS0# BB8 SPI_CLK/ESPI_CLK/EGPIO117 AB5 Connect the four USB 3.0 ports to onboard devices first
36 EC_SPI_CS0# SPI_CS1_L/EGPIO118 USB_SS_3RXP
EC_SPI_D1
RC144 1 2 10K_0402_5% EGPIO119
SPI_D1
AW7
SPI_CS2_L/ESPI_CS_L/EGPIO119 USB_SS_3RXN
AB6 starting from the lower ports and then the remaining
RC199 1 @ 2 0_0402_5% BA9
36
36
EC_SPI_D1
EC_SPI_D0
EC_SPI_D0 RC198 1 @ 2 0_0402_5% SPI_D0 AY7 SPI_DI/ESPI_DATA/EGPIO120 ports can be used for routing to USB 3.0 connectors.
B EC_SPI_D2 SPI_D2 SPI_DO/EGPIO121 B
36 EC_SPI_D2 EC_SPI_D3
RC132
RC133
1
1
@
@
2
2
0_0402_5%
0_0402_5% SPI_D3
AW11
BA7 SPI_WP_L/EGPIO122 Less than four USB 3.0 ports can be utilized provided
36 EC_SPI_D3 SPI_HOLD_L/EGPIO133 the unused ports are higher-numbered consecutive
RC116 1 @ 2 0_0402_5% AW12
15 PXS_RST# SPI_TPM_CS_L/AGPIO76
FP4 REV 0.93 ports.
+3VALW @ AMD-CARRIZO_FP4-BGA968 None of the four USB 3.0 ports can be configured
as USB 2.0 external ports.
+1.8VS +1.8VS
2
LPCCLK0
PCH_SPI_CS0# 1 8 50mA
/CS VCC YC2
1
1
GND DI(IO0) 0.1U_0201_6.3V6-K 0_0201_5% EMC_NS@ OSC1 NC2
2 EMC_NS@ 2 3
2
CC26 1 1
1 10P_0201_25V8G
CC218 EMC_NS@ CC28 48MHZ_10PF_7V48000017 CC29
8M ROM 1
CC219 22P_0201_25V8 2 10P_0402_50V8-J 12P_0402_50V8-J
22P_0201_25V8 EMC_NS@ 2 2
A
2 EMC A
EMC_NS@
2
EMC
PCH_SPI_CS0#
EMC
PCH_SPI_CLK PCH_SPI_CS0# 36
PCH_SPI_D0 PCH_SPI_CLK 36
PCH_SPI_D1 PCH_SPI_D0 36 Security Classification LC Future Center Secret Data Title
PCH_SPI_D2 PCH_SPI_D1 36 CC219 and CC218 should 27pf as EMC suggest
PCH_SPI_D3 PCH_SPI_D2 36 Issued Date 2013/08/15 Deciphered Date 2013/08/15 FP4 (SATA/USB/LPC/SPI)
PCH_SPI_D3 36
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG516
Date: Tuesday, April 12, 2016 Sheet 8 of 51
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5 4 3 2 1
180P_0402_50V8-J
P28 W7
0.22U_0201_6.3V6-K
0.22U_0201_6.3V6-K
0.22U_0201_6.3V6-K
0.22U_0201_6.3V6-K
0.22U_0201_6.3V6-K
0.22U_0201_6.3V6-K
0.22U_0201_6.3V6-K
0.22U_0201_6.3V6-K
T24 VDDIO_MEM_S3_2 VDDCR_CPU_2 W12
T27 VDDIO_MEM_S3_3 VDDCR_CPU_3 W15
0.22U_0201_6.3V6-K
0.22U_0201_6.3V6-K
0.22U_0201_6.3V6-K
0.22U_0201_6.3V6-K
0.22U_0201_6.3V6-K
0.22U_0201_6.3V6-K
VDDIO_MEM_S3_4 VDDCR_CPU_4 1 1 1 1 1 1 1 1 1
180P_0402_50V8-J
CC129
CC130
CC131
CC132
CC133
CC134
CC135
CC136
CC137
U25 W18
U28 VDDIO_MEM_S3_5 VDDCR_CPU_5 W21
1 1 1 1 1 1 1 VDDIO_MEM_S3_6 VDDCR_CPU_6
+1.2V
CC157
CC158
CC159
CC160
CC161
CC163
CC165
V30 Y8
V33 VDDIO_MEM_S3_7 VDDCR_CPU_7 Y10 2 2 2 2 2 2 2 2 2
W24 VDDIO_MEM_S3_8 VDDCR_CPU_8 Y13
2 2 2 2 2 2 2 W27 VDDIO_MEM_S3_9 VDDCR_CPU_9 Y16
VDDIO_MEM_S3_10 VDDCR_CPU_10
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
Y25 Y19 SIT1CD@ SIT1CD@
Y28 VDDIO_MEM_S3_11 VDDCR_CPU_11 Y22
1 1 1 1 1 1 1 1 1 1 1
SIT1CD@ SIT1CD@ VDDIO_MEM_S3_12 VDDCR_CPU_12 OK
CC42
CC54
CC55
CC56
CC57
CC58
CC59
CC60
CC53
CC61
CC62
Y30 AB7
AB24 VDDIO_MEM_S3_13 VDDCR_CPU_13 AB9
OK VDDIO_MEM_S3_14 VDDCR_CPU_14
D AB27 AB12 D
@ 2 2 2 2 2 2 2 2 @ 2 @ 2 2 AB30 VDDIO_MEM_S3_15 VDDCR_CPU_15 AB15 +APU_GFX
AB33 VDDIO_MEM_S3_16 VDDCR_CPU_16 AB18
AD25 VDDIO_MEM_S3_17 VDDCR_CPU_17 AB21
AD28 VDDIO_MEM_S3_18 VDDCR_CPU_18 AD6
0.22U_0201_6.3V6-K
0.22U_0201_6.3V6-K
0.22U_0201_6.3V6-K
0.22U_0201_6.3V6-K
0.22U_0201_6.3V6-K
0.22U_0201_6.3V6-K
0.22U_0201_6.3V6-K
0.22U_0201_6.3V6-K
0.22U_0201_6.3V6-K
SIT1CD@ SIT1CD@ SIT1CD@ VDDIO_MEM_S3_19 VDDCR_CPU_19
180P_0402_50V8-J
AD30 AD10
+VAUDIO +VDDIO_AZ_APU AE24 VDDIO_MEM_S3_20 VDDCR_CPU_20 AD13
VDDIO_MEM_S3_21 VDDCR_CPU_21 1 1 1 1 1 1 1 1 1 1
CC147
CC148
CC149
CC150
CC151
CC152
CC153
CC154
CC156
CC155
RC212 1 @ 2 0_0402_5% AE27 AD16
VDDIO_MEM_S3_22 VDDCR_CPU_22
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
Wake-on-Ring not supported: AF30 AD19
AF33 VDDIO_MEM_S3_23 VDDCR_CPU_23 AD22
+VDDIO_AZ_APU Connect to +1.5V S0 rail 1 1 1 VDDIO_MEM_S3_24 VDDCR_CPU_24 BR@ 2 BR@ 2 2 2 BR@ 2 BR@ 2 BR@ 2 BR@ 2 BR@ 2 BR@ 2
CC184
CC185
CC193
AG25 AE7
AG28 VDDIO_MEM_S3_25 VDDCR_CPU_25 AE12
AH24 VDDIO_MEM_S3_26 VDDCR_CPU_26 AK9
2 2 2 AH27 VDDIO_MEM_S3_27 VDDCR_CPU_42 AG10 SIT1CD@SIT1CD@
+0.95VS +0.95VS_GFX_APU AH30 VDDIO_MEM_S3_28 VDDCR_CPU_31 AK10
VDDIO_MEM_S3_29 VDDCR_CPU_43 OK
1 BR@ 2 0_0805_5% AK25 AG13
0.22U_0201_6.3V6-K
RC210 SIT1CD@ VDDIO_MEM_S3_30 VDDCR_CPU_32
10U_0603_6.3V6M
AK28 AK13
VDDIO_MEM_S3_31 VDDCR_CPU_44
100_0402_5%
AK30 AG16
RC210,CC180,CC181 must add BRUMA@ in Virtual symbol 1 1 VDDIO_MEM_S3_32 VDDCR_CPU_33
CC180
CC181
AK33 AK16
VDDIO_MEM_S3_33 VDDCR_CPU_45 +1.2V
RC229
AL27 AG19
AM30 VDDIO_MEM_S3_34 VDDCR_CPU_34 AK19
BR@ 2 BR@ 2 VDDIO_MEM_S3_35 VDDCR_CPU_46 AG22
AR19 VDDCR_CPU_35 AK22
0.22U_0201_6.3V6-K
0.22U_0201_6.3V6-K
0.22U_0201_6.3V6-K
0.22U_0201_6.3V6-K
@ 0.2A
2
VDDIO_AUDIO VDDCR_CPU_47
180P_0402_50V8-J
180P_0402_50V8-J
AH7
AE6 VDDCR_CPU_36 AE18
+3VS
1.5A VDDP_GFX_2 VDDCR_CPU_28 1 1 1 1 1 1
CC168
CC169
CC170
CC172
CC179
CC176
AE5 AE21
RC214 +3VS_APU VDDP_GFX_1 VDDCR_CPU_29 AH21
VDDCR_CPU_40
10U_0603_6.3V6M
0_0402_5% AN6
AP16 VDDCR_CPU_49 AH15
0.22U_0201_6.3V6-K
CC173
2 2 AP15
1 1 0.2A VDD_33_S5_1
CC188
CC189
AR15 L8
0.22U_0201_6.3V6-K
+0.95VALW VDD_33_S5_2 VDDCR_GFX_14
10U_0603_6.3V6M
L13
AN12 VDDCR_GFX_15 L16
0.22U_0201_6.3V6-K
2 2 1 1 0.8A VDDP_S5_1 VDDCR_GFX_16 Design Guide G FP4 CRB
10U_0603_6.3V6M
CC190
CC191
AP12 L19
C +VDDCR_FCH_S5 VDDP_S5_2 VDDCR_GFX_17 L22 9*22uf 0603 9*22uf 0805 13*22uf 0603 C
1 1 VDDCR_GFX_18
CC182
CC183
0.2A AP13 N7 VDDCR_CPU 8*0.22uf 0402 8*0.22uf 0402 8*0.22uf 0402
+0.95VS 2 2 AR12 VDDCR_FCH_S5_1 VDDCR_GFX_19 N12 1*180pf 0402 1*180pf 0402 1*180pf 0402
+0.95VS VDDCR_FCH_S5_2 VDDCR_GFX_20 N15 4*22uf 0603 4*22uf 0805 6*22uf 0603
2 2 AW19 VDDCR_GFX_21 N18
0.22U_0201_6.3V6-K
0.22U_0201_6.3V6-K
0.22U_0201_6.3V6-K
0.22U_0201_6.3V6-K
0.22U_0201_6.3V6-K
0.22U_0201_6.3V6-K
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
180P_0402_50V8-J
CC174
CC171
CC167
CC178
CC177
CC197
CC198
CC201
CC202
CC203
CC217 AV17 P13 VDDCR_GFX 9*0.22uf 0402 9*0.22uf 0402 9*0.22uf 0402
47P_0402_50V8J AV19 VDDP_3 VDDCR_GFX_25 P16 1*180pf 0402 1*180pf 0402 1*180pf 0402
RF@ AW17 VDDP_4 VDDCR_GFX_26 P19 8*22uf 0603 8*22uf 0603 8*22uf 0603
2 2 2 2 2 2 2 2 2 2 2 2 +APU_CORE_NB VDDP_5 VDDCR_GFX_27 P22 6*0.22uf 0402 split*4 6*0.22uf 0402 split*4 8*0.22uf 0402 split*4
VDDCR_GFX_28 VDDIO_MEM_S3
12A AL12 T7 1*180pf 0402 split*2 1*180pf 0402 split*2 1*180pf 0402 split*2
AL13 VDDCR_NB_1 VDDCR_GFX_29 F12 2*10uf 0402 2*10uf 0603 2*10uf 0603
SIT1CD@ SIT1CD@ AL15 VDDCR_NB_2 VDDCR_GFX_1 F15 1*0.22uf 0402 1*0.22uf 0402 1*0.22uf 0402
VDDCR_NB_3 VDDCR_GFX_2 VDDCR_FCH_S5
OK AL18 G11
AL21 VDDCR_NB_4 VDDCR_GFX_3 G14 4*10uf 0402 4*10uf 0603 4*10uf 0603
AN13 VDDCR_NB_5 VDDCR_GFX_4 J8 1*0.22uf 0402 1*0.22uf 0402 1*0.22uf 0402
VDDCR_NB_6 VDDCR_GFX_5 VDDP
AN16 J9 1*180pf 0402 1*180pf 0402 1*180pf 0402
+APU_CORE_NB AN19 VDDCR_NB_7 VDDCR_GFX_6 J11 1*10uf 0402 1*10uf 0603 1*10uf 0603
AN22 VDDCR_NB_8 VDDCR_GFX_7 K7 1*0.22uf 0402 1*0.22uf 0402 1*0.22uf 0402
VDDCR_NB_9 VDDCR_GFX_8 VDDP_GFX
K12
+RTCBATT +RTCBATT_APU VDDCR_GFX_9
180P_0402_50V8-J
K13
0.22U_0201_6.3V6-K
0.22U_0201_6.3V6-K
0.22U_0201_6.3V6-K
0.22U_0201_6.3V6-K
0.22U_0201_6.3V6-K
0.22U_0201_6.3V6-K
0.22U_0201_6.3V6-K
0.22U_0201_6.3V6-K
0.22U_0201_6.3V6-K
0.22U_0201_6.3V6-K
0.22U_0201_6.3V6-K
0.22U_0201_6.3V6-K
CC139
CC140
CC141
CC142
CC143
CC144
CC146
CC145
CC195
CC196
CC199
CC200
T12
0.22U_0201_6.3V6-K
1*22uf 0603 1*22uf 0603 1*22uf 0603
VDDCR_GFX_30 T15 1*10uf 0402 1*10uf 0402 1*10uf 0603
VDDCR_GFX_31 VDD_18
1 T18
2 2 2 2 2 2 2 2 2 2 2 2 2 VDDCR_GFX_32
CC192
@ @ @ @ T21 1*10uf 0402 1*10uf 0603 1*10uf 0603
VDDCR_GFX_33 U13 1*0.22uf 0402 1*0.22uf 0402 1*0.22uf 0402
VDDCR_GFX_34 VDD_18_S5
U16
SIT1CD@ SIT1CD@ 2 VDDCR_GFX_35 U19
VDDCR_GFX_36 U22 1*10uf 0402 1*10uf 0603 1*10uf 0603
OK follow CRB reserve VDDCR_GFX_37 VDD_33
K19
VDDCR_GFX_13 1*10uf 0402 1*10uf 0403 1*10uf 0603
FP4 REV 0.93
VDD_33_S5 1*0.22uf 0402 1*0.22uf 0402 1*0.22uf 0402
UC5
+VCCRTC @ AMD-CARRIZO_FP4-BGA968
RC231 1 2 10K_0402_5% 1 VDDIO_AUDIO 3*1uf 0402 3*1uf 0402 3*1uf 0402
Vin
3 +RTCBATT
Vout
1U_0402_6.3V6K
1U_0402_6.3V6K
B 2 B
1 GND 1
1
CC37
CC194
JCMOS1 RC8 @
SHORT PADS 470_0603_5%
AP2138N-1.5TRG1_SOT23-3 @
2
2 2
12
D QC7
2 EC_RTCRST#_ON
G EC_RTCRST#_ON 36 QC1/QC2/QC3/QC4 Rds on should less possible, CRB is 11.8mohm,
RC2181 @ 2 0_0402_5%
there is no load swtich for 0.775V power, so it need mos
1
CC225 EMC_NS@
1 1
0.1U_0201_6.3V6-K
0.1U_0201_6.3V6-K
1 1 2 2
5 3 3 5 1 2 0_0603_5%
0.22U_0201_6.3V6-K
RC233 @
22U_0603_6.3V6-M
22U_0603_6.3V6-M
10U_0603_6.3V6M
10U_0603_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
+5VALW
2 2 1 1 1 1 1 1 1
CC127
CC128
CC125
CC126
CC162
CC164
CC166
4
4
FCHMOS@ FCHMOS@
2
+3VALW_APU_FCH
RC146 2 @ 2 2 @ 2 2 2 2
+20VSB
OK EMC +APU_CORE_NB
10K_0402_5%
FCHMOS@
8
FCH_S5_POWER 2
-_1
1
RC227 FCHMOS@
RC230 1M_0402_5% AS393MTR-G1_SO8
4
100K_0402_5% FCHMOS@
S5_MUX_CTRL: Enable MUX(S0 to S3)-->LOW RC223 1 @ 2 0_0402_5% RC2221 @ 2 0_0402_5%
2
@ D QC5B
Disable MUX(S3 to S0)-->HIGH
2
VIN1_1 VOUT_1
10U_0603_6.3V6M
RC228 1 2 2 2 2
7 APU_S5_MUX_CTRL
0_0402_5% G FCH_S5_POWER_COMP +0.95VALW FCH_S5_POWER 5 3 3 5 2
VIN1_2 VOUT_2
7
1
+0.775VALW
CC207
QC5A
1
S
2N7002KDWH_SOT363-6 RC225 1 @2 0_0603_5% 3 6 APU_S5_MUX_CTRL
1
1
VIN2 SEL
1
+5VALW +5VALW
10U_0603_6.3V6M
RC232
4
2
A A
RC272 100K_0402_5% CC124 +3VALW_APU_FCH 4 5
FCHMOS@ FCHMOS@ VCC EN
1
220P_0201_25V7-K
CC208
1U_0402_6.3V6K
100K_0402_5% FCHMOS@
2
@ 2 @ 9
1
2
GND
CC209
RC148
2
2
10K_0402_5%
8
FCHMOS@
FCHMOS@ AS393MTR-G1_SO8
4
UC2G UC2H
GND GND
A8 L28 AE10 AV30
A12 VSS_1 VSS_63 M4 AE13 VSS_125 VSS_187 AV33
A16 VSS_2 VSS_64 M30 AE16 VSS_126 VSS_188 AW22
A20 VSS_3 VSS_65 N10 AE19 VSS_127 VSS_189 AY4
A24 VSS_4 VSS_66 N13 AE22 VSS_128 VSS_190 AY6
A28 VSS_5 VSS_67 N16 AF1 VSS_129 VSS_191 AY8
D D
A32 VSS_6 VSS_68 N19 AF4 VSS_130 VSS_192 AY10
B2 VSS_7 VSS_69 N22 AG9 VSS_131 VSS_193 AY12
B8 VSS_8 VSS_70 N27 AG12 VSS_132 VSS_194 AY14
B12 VSS_9 VSS_71 P1 AG15 VSS_133 VSS_195 AY16
B33 VSS_10 VSS_72 P2 AG18 VSS_134 VSS_196 AY20
C3 VSS_11 VSS_73 P4 AG21 VSS_135 VSS_197 AY22
D4 VSS_12 VSS_74 P5 AH4 VSS_136 VSS_198 AY24
D6 VSS_13 VSS_75 P12 AH10 VSS_137 VSS_199 AY26
D8 VSS_14 VSS_76 P15 AH13 VSS_138 VSS_200 AY28
D10 VSS_15 VSS_77 P18 AH16 VSS_139 VSS_201 AY30
D12 VSS_16 VSS_78 P21 AH19 VSS_140 VSS_202 BB1
D14 VSS_17 VSS_79 P30 AH22 VSS_141 VSS_203 BB33
D16 VSS_18 VSS_80 P33 AK1 VSS_142 VSS_204 BC4
D18 VSS_19 VSS_81 T4 AK4 VSS_143 VSS_205 BC8
D20 VSS_20 VSS_82 T10 AK12 VSS_144 VSS_206 BC12
D22 VSS_21 VSS_83 T13 AK15 VSS_145 VSS_207 BC16
D24 VSS_22 VSS_84 T16 AK18 VSS_146 VSS_208 BC20
D26 VSS_23 VSS_85 T19 AL16 VSS_147 VSS_209 BC24
D28 VSS_24 VSS_86 T22 AL19 VSS_148 VSS_210 BC28
D30 VSS_25 VSS_87 T30 AL22 VSS_149 VSS_211 BC32
F1 VSS_26 VSS_88 U5 AM4 VSS_150 VSS_212
F2 VSS_27 VSS_89 U12 AN9 VSS_151
F4 VSS_28 VSS_90 U15 AN10 VSS_152
F9 VSS_29 VSS_91 U18 AN15 VSS_153
C
F19 VSS_30 VSS_92 U21 AN18 VSS_154 C
F22 VSS_31 VSS_93 U24 AN21 VSS_155
F25 VSS_32 VSS_94 V1 AN25 VSS_156
F30 VSS_33 VSS_95 V2 AN28 VSS_157
F33 VSS_34 VSS_96 V4 AP1 VSS_158
G7 VSS_35 VSS_97 W10 AP2 VSS_159
G17 VSS_36 VSS_98 W13 AP4 VSS_160
G20 VSS_37 VSS_99 W16 AP7 VSS_161
G23 VSS_38 VSS_100 W19 AP22 VSS_162
G26 VSS_39 VSS_101 W22 AP27 VSS_163
H4 VSS_40 VSS_102 Y4 AP30 VSS_164
H30 VSS_41 VSS_103 Y5 AP33 VSS_165
VSS_42 VSS_104 VSS_166 UC2J
J5 Y12 AR6
J15 VSS_43 VSS_105 Y15 AR25 VSS_167
J19 VSS_44 VSS_106 Y18 AR28 VSS_168 @ TC4 1 U30
J22 VSS_45 VSS_107 Y21 AT4 VSS_169 @ TC6 1 U31 RSVD_2
J25 VSS_46 VSS_108 Y24 AT19 VSS_170 @ TC5 1 AN30 RSVD_3
J28 VSS_47 VSS_109 AB1 AT22 VSS_171 RSVD_4
K1 VSS_48 VSS_110 AB2 AT30 VSS_172
K2 VSS_49 VSS_111 AB4 AU5 VSS_173
K4 VSS_50 VSS_112 AB10 AU8 VSS_174
K10 VSS_51 VSS_113 AB13 AU11 VSS_175
K22 VSS_52 VSS_114 AB16 AU14 VSS_176
K27 VSS_53 VSS_115 AB19 AU20 VSS_177
K30 VSS_54 VSS_116 AB22 AU23 VSS_178 FP4 REV 0.93
B B
K33 VSS_55 VSS_117 AD4 AU27 VSS_179
L5 VSS_56 VSS_118 AD9 AV4 VSS_180 @
VSS_57 VSS_119 VSS_181 AMD-CARRIZO_FP4-BGA968
L12 AD12 AV7
L15 VSS_58 VSS_120 AD15 AV9 VSS_182
L18 VSS_59 VSS_121 AD18 AV12 VSS_183 L24
L21 VSS_60 VSS_122 AD21 AV15 VSS_184 VSS_213 AL10
L25 VSS_61 VSS_123 AD24 AV25 VSS_185 VSS_215 AK21
VSS_62 VSS_124 VSS_186 VSS_214
FP4 REV 0.93 FP4 REV 0.93
@ AMD-CARRIZO_FP4-BGA968 @ AMD-CARRIZO_FP4-BGA968
A A
4 3 2
Date: Tuesday, April 12, 2016 Sheet
1
10 of 51
5 4 3 2 1
2
RC152 RC153 RC154 RC155 RC156 RC157 RC81
10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
@ @
D D
1
8,30,36 LPC_FRAME#
8 LPC_CLK1
8,36 CLK_PCI_EC
7 AGPIO3
7 SYS_RESET#
7,31 SUSCLK
7 HVB_EN
1
RC79
C RC159 RC160 RC161 RC162 RC163 RC164 C
2K_0402_5% 2K_0402_5% 2K_0402_5% 2K_0402_5% 2K_0402_5% 2K_0402_5% 0_0402_5%
@ @ @ @ @
@
2
STRAP PINS
Type II II II I I I
SPI ROM Internal Boot Fail Timer RTC Coin Battery is Normal Power Up Enhanced reset floating
PULL CLK Gen Enabled implemented &Reset Timing logic (for quicker
HIGH S5 resume) Disable HVB
Default Default Default on FP4 platforms
Default Default
Default
B B
Boot Fail Timer Reserved traditional connected to VSS
PULL LPC ROM Reserved Disabled RTC Coin Battery is reset logic
LOW not implemented Enable HVB
Default on FP4 platforms
Type I straps become valid immediately after capture with the rising edge of RSMRST_L,they are captured only once when power is first applied to the processor
Type II straps become valid after PWR_GOOD is asserted,straps are captured every time the systems powers up from the S5 state. A transition from S3 to S0 does not trigger capture.
Type II straps should be pulled up to S0 power rail to prevent leakage when the signal is connected to a device in S0 power domain.
If the LPC bus is connected to devices that are on S0 power rail, then a pull-up resistor to VDD_33 is implemented.
All Strap pins must be configured with either external pull-up or pull-down resistors.
Platforms that are designed for AOAC complaint are recommended to use the Alternate Reset by strapping this pin to ‘ 1’ for C
Z
AGPIO3
A A
DDRB_DQ[0..63]
DDRB_DQ[0..63] 5,13
DDRB_DQS[0..7]
DDRB_DQS[0..7] 5,13
DDRB_DQS#[0..7]
DDRB_DQS#[0..7] 5,13
DDR3 SO-DIMM A DDRB_MA[0..13]
DDRB_MA[0..13] 5,13
+1.2V +1.2V DDRB_DM[0..7]
DDRB_DM[0..7] 5,13
JDDR1B
+3VS +VDDSPD
RD271 1 2 0_0402_5%
+2.5VS
B +1.2V B
+1.2V RD272 1 @ 2 0_0402_5%
+2.5V +2.5VS
1
1
D
RD10 3 1
RD258 +VREF_CA QD1
1K_0402_1%
1K_0402_1% LP2301ALT1G_SOT23-3
G
15mil Layout Note: Place near JDDR1
2
2
@
2
0.1U_0201_6.3V6-K
0.1U_0201_6.3V6-K
2
DDR4_ALERT
1000P_0201_50V7-K
25,38 SUSP
RD11 1 1 1
1K_0402_1% +0.6VS +1.2V
CD262
CD116
CD117
follow CRB 1pcs 4.7uf + 1pcs 0.1uf follow CRB 6pcs 0.1uf
1
2 2 2
180P_0402_50V8-J
0.1U_0201_6.3V6-K
0.1U_0201_6.3V6-K
0.1U_0201_6.3V6-K
0.1U_0201_6.3V6-K
0.1U_0201_6.3V6-K
0.1U_0201_6.3V6-K
0.1U_0201_6.3V6-K
0.1U_0201_6.3V6-K
0.1U_0201_6.3V6-K
0.1U_0201_6.3V6-K
0.1U_0201_6.3V6-K
0.1U_0201_6.3V6-K
0.1U_0201_6.3V6-K
4.7U_0402_6.3V6M
1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 CD16 CD17 CD18 CD20 CD21 CD22 CD23 CD58 CD59 CD60 CD61 CD62 CC211
CD249 CD251 CD250 CD248 @ EMC@ @ EMC@ @ @
@ @
2 2 2 2 2 2 2 2 2 2 2 2 2
2 2 2 2
10U_0603_6.3V6M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
1U_0402_6.3V6K
0.1U_0201_6.3V6-K
0.1U_0201_6.3V6-K
180P_0402_50V8-J
1 1 1 1 1 1 1
1
DDRB_DQ[0..63]
DDRB_DQ[0..63] 5,12
DDRB_DQS[0..7]
DDRB_DQS[0..7] 5,12
UD1 UD2 DDRB_DQS#[0..7]
DDRB_DQS#[0..7] 5,12
DDRB_MA0 P3 G2 DDRB_DQ0D 15_0201_5% 1 2 RD166 DDRB_DQ0 DDRB_MA0 P3 G2 DDRB_DQ20D 15_0201_5% 1 2 RD187 DDRB_DQ20 DDRB_MA[0..13]
DDRB_MA1 P7 A0 DQ0 F7 DDRB_DQ6D 1 2 DDRB_DQ6 DDRB_MA1 P7 A0 DQ0 F7 DDRB_DQ19D 1 2 DDRB_DQ19 DDRB_MA[0..13] 5,12
15_0201_5% RD172 15_0201_5% RD188
DDRB_MA2 R3 A1 DQ1 H3 DDRB_DQ4D 15_0201_5% 1 2 RD170 DDRB_DQ4 DDRB_MA2 R3 A1 DQ1 H3 DDRB_DQ21D 15_0201_5% 1 2 RD186 DDRB_DQ21 DDRB_DM[0..7]
DDRB_MA3 A2 DQ2 DDRB_DQ1D DDRB_DQ1 DDRB_MA3 A2 DQ2 DDRB_DQ17D DDRB_DQ17 DDRB_DM[0..7] 5,12
N7 H7 15_0201_5% 1 2 RD167 N7 H7 15_0201_5% 1 2 RD183
DDRB_MA4 N3 A3 DQ3 H2 DDRB_DQ2D 15_0201_5% 1 2 RD168 DDRB_DQ2 DDRB_MA4 N3 A3 DQ3 H2 DDRB_DQ18D 15_0201_5% 1 2 RD189 DDRB_DQ18
DDRB_MA5 P8 A4 DQ4 H8 DDRB_DQ3D 15_0201_5% 1 2 RD169 DDRB_DQ3 DDRB_MA5 P8 A4 DQ4 H8 DDRB_DQ23D 15_0201_5% 1 2 RD184 DDRB_DQ23
DDRB_MA6 P2 A5 DQ5 J3 DDRB_DQ7D 15_0201_5% 1 2 RD173 DDRB_DQ7 DDRB_MA6 P2 A5 DQ5 J3 DDRB_DQ22D 15_0201_5% 1 2 RD185 DDRB_DQ22
DDRB_MA7 R8 A6 DQ6 J7 DDRB_DQ5D 15_0201_5% 1 2 RD171 DDRB_DQ5 DDRB_MA7 R8 A6 DQ6 J7 DDRB_DQ16D 15_0201_5% 1 2 RD182 DDRB_DQ16
DDRB_MA8
DDRB_MA9
R2
R7
A7
A8
DQ7
DQ8
A3
B8
DDRB_DQ14D
DDRB_DQ9D
15_0201_5%
15_0201_5%
1
1
2
2
RD180
RD175
DDRB_DQ14
DDRB_DQ9
DDRB_MA8
DDRB_MA9
R2
R7
A7
A8
DQ7
DQ8
A3
B8
DDRB_DQ27D
DDRB_DQ24D
15_0201_5%
15_0201_5%
1
1
2
2
RD192
RD190
DDRB_DQ27
DDRB_DQ24 CD163 change from K to J
DDRB_MA10 M3 A9 DQ9 C3 DDRB_DQ15D 15_0201_5% 1 2 RD181 DDRB_DQ15 DDRB_MA10 M3 A9 DQ9 C3 DDRB_DQ31D 15_0201_5% 1 2 RD197 DDRB_DQ31 +1.2V
DDRB_MA11 T2 A10/AP DQ10 C7 DDRB_DQ8D 15_0201_5% 1 2 RD174 DDRB_DQ8 DDRB_MA11 T2 A10/AP DQ10 C7 DDRB_DQ25D 15_0201_5% 1 2 RD191 DDRB_DQ25
DDRB_MA12 M7 A11 DQ11 C2 DDRB_DQ10D 15_0201_5% 1 2 RD176 DDRB_DQ10 DDRB_MA12 M7 A11 DQ11 C2 DDRB_DQ26D 15_0201_5% 1 2 RD193 DDRB_DQ26 DDRB_CLK2# RD122 1 2 39_0402_5% CD163 1 2 0.01UF_0402_25V7-K
DDRB_MA13 T8 A12/BC_N DQ12 C8 DDRB_DQ12D 15_0201_5% 1 2 RD178 DDRB_DQ12 DDRB_MA13 T8 A12/BC_N DQ12 C8 DDRB_DQ28D 15_0201_5% 1 2 RD196 DDRB_DQ28 DDRB_CLK2 RD123 1 2 39_0402_5%
A13 DQ13 D3 DDRB_DQ11D 15_0201_5% 1 2 RD177 DDRB_DQ11 A13 DQ13 D3 DDRB_DQ30D 15_0201_5% 1 2 RD195 DDRB_DQ30
D D
DDRB_MA14_WE# L2 DQ14 D7 DDRB_DQ13D 15_0201_5% 1 2 RD179 DDRB_DQ13 DDRB_MA14_WE# L2 DQ14 D7 DDRB_DQ29D 15_0201_5% 1 2 RD194 DDRB_DQ29
5,12 DDRB_MA14_WE#
5,12 DDRB_MA15_CAS#
DDRB_MA15_CAS#
DDRB_MA16_RAS#
M8
L8
WE_N/A14
CAS_N/A15
DQ15
+1.2V
DDRB_MA15_CAS#
DDRB_MA16_RAS#
M8
L8
WE_N/A14
CAS_N/A15
DQ15
+1.2V 2/22: change to K back for materil stock risk, and this change +0.6VS
5,12 DDRB_MA16_RAS#
5 DDRB_CLK2#
DDRB_CLK2#
DDRB_CLK2
K8
RAS_N/A16
CK_C
VDD1
VDD2
D1
J1 DDRB_CLK2#
DDRB_CLK2
K8
RAS_N/A16
CK_C
VDD1
VDD2
D1
J1 has conf i r m
t o A MD DDRB_MA0
K7 L1 K7 L1 RD148 1 2 39_0402_5%
5 DDRB_CLK2 CK_T VDD3 CK_T VDD3 DDRB_MA1
R1 R1 RD149 1 2 39_0402_5%
DDRB_CKE0 K2 VDD4 B3 DDRB_CKE0 K2 VDD4 B3 DDRB_MA2 RD124 1 2 39_0402_5%
5,12 DDRB_CKE0 CKE VDD5 CKE VDD5 DDRB_MA3
G7 G7 RD125 1 2 39_0402_5%
DDRB_DQS#0 15_0201_5% 1 2 RD150 DDRB_DQS#0D F3 VDD6 B9 DDRB_DQS#2 15_0201_5% 1 2 RD232 DDRB_DQS#2D F3 VDD6 B9 DDRB_MA4 RD126 1 2 39_0402_5%
DDRB_DQS0 15_0201_5% 1 2 RD151 DDRB_DQS0D G3 LDQS_C VDD7 J9 DDRB_DQS2 15_0201_5% 1 2 RD233 DDRB_DQS2D G3 LDQS_C VDD7 J9 DDRB_MA5 RD127 1 2 39_0402_5%
DDRB_DQS#1 15_0201_5% 1 2 RD152 DDRB_DQS#1D A7 LDQS_T VDD8 L9 DDRB_DQS#3 15_0201_5% 1 2 RD234 DDRB_DQS#3D A7 LDQS_T VDD8 L9 DDRB_MA6 RD128 1 2 39_0402_5%
DDRB_DQS1 15_0201_5% 1 2 RD153 DDRB_DQS1D B7 UDQS_C VDD9 T9 DDRB_DQS3 15_0201_5% 1 2 RD235 DDRB_DQS3D B7 UDQS_C VDD9 T9 DDRB_MA7 RD129 1 2 39_0402_5%
UDQS_T VDD10 UDQS_T VDD10 DDRB_MA8 RD130 1 2 39_0402_5%
DDRB_DM1 15_0201_5% 1 2 RD231 DDRB_DM1D E2 A1 DDRB_DM3 15_0201_5% 1 2 RD237 DDRB_DM3D E2 A1 DDRB_MA9 RD131 1 2 39_0402_5%
DDRB_DM0 15_0201_5% 1 2 RD230 DDRB_DM0D E7 NF/UDM_N/UDBI_N VDDQ1 C1 DDRB_DM2 15_0201_5% 1 2 RD236 DDRB_DM2D E7 NF/UDM_N/UDBI_N VDDQ1 C1 DDRB_MA10 RD132 1 2 39_0402_5%
NF/LDM_N/LDBI_N VDDQ2 G1 NF/LDM_N/LDBI_N VDDQ2 G1 DDRB_MA11 RD133 1 2 39_0402_5%
DDRB_BA0 N2 VDDQ3 F2 DDRB_BA0 N2 VDDQ3 F2 DDRB_MA12 RD134 1 2 39_0402_5%
5,12 DDRB_BA0 DDRB_BA1 BA0 VDDQ4 DDRB_BA1 BA0 VDDQ4 DDRB_MA13
RF N8 J2 N8 J2 RD135 1 2 39_0402_5%
5,12 DDRB_BA1 BA1 VDDQ5 BA1 VDDQ5
F8 F8
+1.2V DDRB_ACT# L3 VDDQ6 J8 +1.2V DDRB_ACT# L3 VDDQ6 J8 DDRB_MA14_WE# RD138 1 2 39_0402_5%
5,12 DDRB_ACT# DDRB_CS2# ACT_N VDDQ7 DDRB_CS2# ACT_N VDDQ7 DDRB_MA15_CAS# RD139
L7 A9 L7 A9 1 2 39_0402_5%
5 DDRB_CS2# CS_N VDDQ8 CS_N VDDQ8 DDRB_MA16_RAS# RD140
1K_0402_1% 1 2 RD260 P9 D9 1K_0402_1% 1 2 RD264 P9 D9 1 2 39_0402_5%
ALERT_N VDDQ9 G9 ALERT_N VDDQ9 G9
DDRB_BG0 M2 VDDQ10 +2.5V DDRB_BG0 M2 VDDQ10 +2.5V DDRB_ACT# RD144 1 2 39_0402_5%
5,12 DDRB_BG0 BG0 BG0
B1 B1
DDRB_ODT2 K3 VPP1 R9 DDRB_ODT2 K3 VPP1 R9 DDRB_ODT2 RD147 1 2 39_0402_5%
5 DDRB_ODT2 ODT VPP2 +VREF_CA ODT VPP2 +VREF_CA DDRB_CS2# RD145 1 2 39_0402_5%
DDRB_CKE0
1U_0402_6.3V6K
1U_0402_6.3V6K
1 2 RD261 T3 M1 1 2 RD265 T3 M1 1 2
0.1U_0201_6.3V6-K
0.1U_0201_6.3V6-K
0_0402_5% 0_0402_5% RD141 39_0402_5%
PAR VREFCA PAR VREFCA
1 1 1 1
1000P_0201_50V7-K
1000P_0201_50V7-K
CD202
CD203
CD232
CD233
2 RD251 N9 E1 1 2 RD253 N9 E1
0.1U_0201_6.3V6-K
0.1U_0201_6.3V6-K
10K_0402_5%1 TEN1 10K_0402_5% TEN2
TEN VSS1 K1 TEN VSS1 K1
VSS2 1 1 VSS2 1 1
MEM_MB_RST# MEM_MB_RST#
CD189
CD188
CD230
CD231
P1 N1 P1 N1
5,12 MEM_MB_RST# RESET_N VSS3 T1 2 2 RESET_N VSS3 T1 2 2 DDRB_BA0 1 2
0.1U_0201_6.3V6-K
0.1U_0201_6.3V6-K
RD142 39_0402_5%
F1 VSS4 B2 F1 VSS4 B2 DDRB_BA1 RD143 1 2 39_0402_5%
H1 VSSQ1 VSS5 G8 2 2 H1 VSSQ1 VSS5 G8 2 2
1 VSSQ2 VSS6 1 VSSQ2 VSS6
CD132
CD160
A2 E9 A2 E9
D2 VSSQ3 VSS7 K9 D2 VSSQ3 VSS7 K9
E3 VSSQ4 VSS8 M9 E3 VSSQ4 VSS8 M9 DDRB_BG0 RD146 1 2 39_0402_5%
@ 2 A8 VSSQ5 VSS9 @ 2 A8 VSSQ5 VSS9
D8 VSSQ6 T7 D8 VSSQ6 T7
E8 VSSQ7 NC E8 VSSQ7 NC
C9 VSSQ8 C9 VSSQ8
H9 VSSQ9 H9 VSSQ9
C VSSQ10 VSSQ10 C
F9 F9
ZQ ZQ
1
1
+1.2V
RD116 MT40A512M16HA083EA_FBGA96 RD117 MT40A512M16HA083EA_FBGA96
240_0402_1% 240_0402_1%
@ @
Layout Note: Place near DRAM
2
2
CD266 1 CD267 1 CD268 1 CD269 1 CD270 1 CD271 1 CD272 1 CD273 1 CD274 1 CD275 1 CD276 1 CD277 1 3A@1.5V
47P_0201_25V8-J
47P_0201_25V8-J
47P_0201_25V8-J
47P_0201_25V8-J
EMC_NS@
EMC@
EMC@
EMC@
EMC@
EMC@
EMC@
EMC_NS@
EMC@
EMC_NS@
EMC_NS@
EMC@
2 2 2 2 2 2 2 2 2 2 2 2
ser Res change to 0201 from 0402 follow SCL 20pcs 0.22uf
0.22U_0201_6.3V6-K
0.22U_0201_6.3V6-K
0.22U_0201_6.3V6-K
0.22U_0201_6.3V6-K
0.22U_0201_6.3V6-K
0.22U_0201_6.3V6-K
0.22U_0201_6.3V6-K
0.22U_0201_6.3V6-K
0.22U_0201_6.3V6-K
0.22U_0201_6.3V6-K
1 1 1 1 1 1 1 1 1 1
CD154 CD155 CD142 CD127 CD141 CD152 CD150 CD158 CD143 CD137
2 2 2 2 2 2 2 2 2 2
UD3
UD4
DDRB_MA0 P3 G2 DDRB_DQ39D 15_0201_5% 1 2 RD205 DDRB_DQ39
DDRB_MA1 P7 A0 DQ0 F7 DDRB_DQ32D 15_0201_5% 1 2 RD203 DDRB_DQ32 DDRB_MA0 P3 G2 DDRB_DQ48D 15_0201_5% 1 2 RD221 DDRB_DQ48
DDRB_MA2 R3 A1 DQ1 H3 DDRB_DQ34D 15_0201_5% 1 2 RD204 DDRB_DQ34 DDRB_MA1 P7 A0 DQ0 F7 DDRB_DQ53D 15_0201_5% 1 2 RD214 DDRB_DQ53
DDRB_MA3 A2 DQ2 DDRB_DQ37D DDRB_DQ37 DDRB_MA2 A1 DQ1 DDRB_DQ50D DDRB_DQ50
3A@1.5V
N7 H7 15_0201_5% 1 2 RD202 R3 H3 15_0201_5% 1 2 RD216
DDRB_MA4 N3 A3 DQ3 H2 DDRB_DQ38D 15_0201_5% 1 2 RD200 DDRB_DQ38 DDRB_MA3 N7 A2 DQ2 H7 DDRB_DQ49D 15_0201_5% 1 2 RD218 DDRB_DQ49
DDRB_MA5 P8 A4 DQ4 H8 DDRB_DQ36D 15_0201_5% 1 2 RD199 DDRB_DQ36 DDRB_MA4 N3 A3 DQ3 H2 DDRB_DQ55D 15_0201_5% 1 2 RD220 DDRB_DQ55 +1.2V
DDRB_MA6 P2 A5 DQ5 J3 DDRB_DQ33D 15_0201_5% 1 2 RD198 DDRB_DQ33 DDRB_MA5 P8 A4 DQ4 H8 DDRB_DQ52D 15_0201_5% 1 2 RD215 DDRB_DQ52
DDRB_MA7 R8 A6 DQ6 J7 DDRB_DQ35D 15_0201_5% 1 2 RD201 DDRB_DQ35 DDRB_MA6 P2 A5 DQ5 J3 DDRB_DQ54D 15_0201_5% 1 2 RD217 DDRB_DQ54
DDRB_MA8 R2 A7 DQ7 A3 DDRB_DQ43D 15_0201_5% 1 2 RD213 DDRB_DQ43 DDRB_MA7 R8 A6 DQ6 J7 DDRB_DQ51D 15_0201_5% 1 2 RD219 DDRB_DQ51
DDRB_MA9 R7 A8 DQ8 B8 DDRB_DQ41D 15_0201_5% 1 2 RD210 DDRB_DQ41 DDRB_MA8 R2 A7 DQ7 A3 DDRB_DQ63D 15_0201_5% 1 2 RD227 DDRB_DQ63
DDRB_MA10 A9 DQ9 DDRB_DQ47D DDRB_DQ47 DDRB_MA9 A8 DQ8 DDRB_DQ61D DDRB_DQ61
0.22U_0201_6.3V6-K
0.22U_0201_6.3V6-K
0.22U_0201_6.3V6-K
0.22U_0201_6.3V6-K
0.22U_0201_6.3V6-K
0.22U_0201_6.3V6-K
0.22U_0201_6.3V6-K
0.22U_0201_6.3V6-K
0.22U_0201_6.3V6-K
0.22U_0201_6.3V6-K
M3 C3 15_0201_5% 1 2 RD209 R7 B8 15_0201_5% 1 2 RD222
DDRB_MA11 T2 A10/AP DQ10 C7 DDRB_DQ45D 15_0201_5% 1 2 RD206 DDRB_DQ45 DDRB_MA10 M3 A9 DQ9 C3 DDRB_DQ57D 15_0201_5% 1 2 RD223 DDRB_DQ57
A11 DQ11 A10/AP DQ10 1 1 1 1 1 1 1 1 1 1
DDRB_MA12 M7 C2 DDRB_DQ46D 15_0201_5% 1 2 RD211 DDRB_DQ46 DDRB_MA11 T2 C7 DDRB_DQ58D 15_0201_5% 1 2 RD225 DDRB_DQ58 CD174 CD173 CD169 CD165 CD167 CD172 CD171 CD175 CD168 CD166
DDRB_MA13 T8 A12/BC_N DQ12 C8 DDRB_DQ44D 15_0201_5% 1 2 RD212 DDRB_DQ44 DDRB_MA12 M7 A11 DQ11 C2 DDRB_DQ59D 15_0201_5% 1 2 RD224 DDRB_DQ59
A13 DQ13 D3 DDRB_DQ42D 15_0201_5% 1 2 RD208 DDRB_DQ42 DDRB_MA13 T8 A12/BC_N DQ12 C8 DDRB_DQ60D 15_0201_5% 1 2 RD228 DDRB_DQ60
DDRB_MA14_WE# L2 DQ14 D7 DDRB_DQ40D 15_0201_5% 1 2 RD207 DDRB_DQ40 A13 DQ13 D3 DDRB_DQ56D 15_0201_5% 1 2 RD226 DDRB_DQ56 2 2 2 2 2 2 2 2 2 2
DDRB_MA15_CAS# M8 WE_N/A14 DQ15 DDRB_MA14_WE# L2 DQ14 D7 DDRB_DQ62D 15_0201_5% 1 2 RD229 DDRB_DQ62
DDRB_MA16_RAS# L8 CAS_N/A15 +1.2V DDRB_MA15_CAS# M8 WE_N/A14 DQ15
RAS_N/A16 D1 DDRB_MA16_RAS# L8 CAS_N/A15 +1.2V
DDRB_CLK2# K8 VDD1 J1 RAS_N/A16 D1
B DDRB_CLK2 K7 CK_C VDD2 L1 DDRB_CLK2# K8 VDD1 J1 B
CK_T VDD3 R1 DDRB_CLK2 K7 CK_C VDD2 L1 +1.2V
DDRB_CKE0 K2 VDD4 B3 CK_T VDD3 R1 +1.2V
CKE VDD5 G7 DDRB_CKE0 K2 VDD4 B3
DDRB_DQS#4 15_0201_5% 1 2 RD238 DDRB_DQS#4D F3 VDD6 B9 CKE VDD5 G7
DDRB_DQS4 15_0201_5% 1 2 RD239 DDRB_DQS4D G3 LDQS_C VDD7 J9 DDRB_DQS#6 15_0201_5% 1 2 RD244 DDRB_DQS#6D F3 VDD6 B9
DDRB_DQS#5 15_0201_5% 1 DDRB_DQS#5D LDQS_T VDD8 DDRB_DQS6 15_0201_5% 1 DDRB_DQS6D LDQS_C VDD7
0.22U_0201_6.3V6-K
0.22U_0201_6.3V6-K
0.22U_0201_6.3V6-K
0.22U_0201_6.3V6-K
2 RD240 A7 L9 2 RD245 G3 J9
DDRB_DQS5 15_0201_5% 1 2 RD241 DDRB_DQS5D B7 UDQS_C VDD9 T9 DDRB_DQS#7 15_0201_5% 1 2 RD246 DDRB_DQS#7D A7 LDQS_T VDD8 L9
UDQS_T VDD10 UDQS_C VDD9 1 1 1 1
DDRB_DQS7 15_0201_5% 1 2 RD247 DDRB_DQS7D B7 T9 CD215 CD218 CD212 CD211
UDQS_T VDD10 1 1
DDRB_DM5 15_0201_5% 1 2 RD243 DDRB_DM5D E2 A1 @ @ @ @ CD133 CD153
DDRB_DM4 15_0201_5% 1 2 RD242 DDRB_DM4D E7 NF/UDM_N/UDBI_N VDDQ1 C1 DDRB_DM7 15_0201_5% 1 2 RD249 DDRB_DM7D E2 A1 22P_0402_50V8-J 22P_0402_50V8-J
NF/LDM_N/LDBI_N VDDQ2 G1 DDRB_DM6 15_0201_5% 1 2 RD248 DDRB_DM6D E7 NF/UDM_N/UDBI_N VDDQ1 C1 2 2 2 2 RF@ RF@
DDRB_BA0 N2 VDDQ3 F2 NF/LDM_N/LDBI_N VDDQ2 G1 2 2
DDRB_BA1 N8 BA0 VDDQ4 J2 DDRB_BA0 N2 VDDQ3 F2
BA1 VDDQ5 F8 DDRB_BA1 N8 BA0 VDDQ4 J2
+1.2V DDRB_ACT# L3 VDDQ6 J8 BA1 VDDQ5 F8
DDRB_CS2# L7 ACT_N VDDQ7 A9 +1.2V DDRB_ACT# L3 VDDQ6 J8
1K_0402_1% 1 2 RD266 P9 CS_N VDDQ8 D9 DDRB_CS2# L7 ACT_N VDDQ7 A9
ALERT_N VDDQ9 G9 1K_0402_1% 1 2 RD262 P9 CS_N VDDQ8 D9
DDRB_BG0 M2 VDDQ10 +2.5V ALERT_N VDDQ9 G9 +0.6VS
BG0 B1 DDRB_BG0 M2 VDDQ10 +2.5V
DDRB_ODT2 K3 VPP1 R9 BG0 B1
ODT VPP2 +VREF_CA DDRB_ODT2 K3 VPP1 R9 follow SCL 10pcs 0.22uf
ODT VPP2 +VREF_CA
1U_0402_6.3V6K
1 2 RD267 T3 M1
0.1U_0201_6.3V6-K
0_0402_5%
PAR VREFCA
0.22U_0201_6.3V6-K
0.22U_0201_6.3V6-K
0.22U_0201_6.3V6-K
0.22U_0201_6.3V6-K
0.22U_0201_6.3V6-K
0.22U_0201_6.3V6-K
0.22U_0201_6.3V6-K
0.22U_0201_6.3V6-K
0.22U_0201_6.3V6-K
0.22U_0201_6.3V6-K
1U_0402_6.3V6K
0.1U_0201_6.3V6-K
1 1 0_0402_5% 1 2 RD263 T3 M1
PAR VREFCA
1000P_0201_50V7-K
CD236
CD237
2 RD255 N9 E1
0.1U_0201_6.3V6-K
10K_0402_5%1 TEN3 1 1 1 1 1 1 1 1 1 1 1 1
TEN VSS1
1000P_0201_50V7-K
CD240
CD241
K1 2 RD257 N9 E1
0.1U_0201_6.3V6-K
1 1 10K_0402_5%1 TEN4 CD146 CD148 CD139 CD138 CD201 CD245 CD246 CD244 CD243 CD242
MEM_MB_RST# VSS2 TEN VSS1
CD234
CD235
P1 N1 K1 1 1
RESET_N VSS3 2 2 MEM_MB_RST# VSS2
CD238
CD239
T1 P1 N1
0.1U_0201_6.3V6-K
F1 B2 T1
H1 VSSQ1 VSS5 G8 2 2 F1 VSS4 B2
1 VSSQ2 VSS6 VSSQ1 VSS5 2 2
CD161
A2 E9 1 H1 G8
VSSQ3 VSS7 VSSQ2 VSS6
CD162
D2 K9 A2 E9
E3 VSSQ4 VSS8 M9 D2 VSSQ3 VSS7 K9
@ 2 A8 VSSQ5 VSS9 E3 VSSQ4 VSS8 M9
D8 VSSQ6 T7 @ 2 A8 VSSQ5 VSS9
E8 VSSQ7 NC D8 VSSQ6 T7 +0.6VS +0.6VS
C9 VSSQ8 E8 VSSQ7 NC +2.5V
H9 VSSQ9 C9 VSSQ8
VSSQ10 H9 VSSQ9
VSSQ10
180P_0402_50V8-J
F9
ZQ
0.22U_0201_6.3V6-K
0.22U_0201_6.3V6-K
F9 1 1
ZQ
1
CC205
1 1 1 1 CD265
1
Power-Up/Down Sequence
"Topaz" has the following requirements with regards to power-supply sequencing to
avoid damaging the ASIC:
D D
All the ASIC supplies must reach their respective nominal voltages within 20 ms
of the start of the ramp-up sequence, though a shorter ramp-up duration is
preferred. The maximum slew rate on all rails is 50 mV/μ s. VRAM ID config
It is recommended that the 3.3-V rail ramp up first.
The 3.3-V, 1.8-V, and 0.95-V rails must reach their ready state at least 10 μ s Memory Type
VRAM ID PU resistor PD resistor
before VDDC, VDDCI, and VMEMIO start to ramp up. PS_3[3:1] RV63 RV70
The power rails that are shared with other components on the system should be
gated for the dGPU so that when the dGPU is powered down (for example
NA 100 4.53K 4.99K
AMD PowerXpress idle state), all the power rails are removed from the dGPU.
The gate circuits must meet the slew rate requirement (such as ≤ 50 mV/μ s).
For power down, reversing the ramp-up sequence is recommended. 128Mx16
NA 111 4.75K NC
Samsung
PCIE_VDDC(+0.95VGS) K4W4G1646E-BC1A 4Gb 900(1G)
001 8.45K 2K
10us min.
VDDR1(+1.35VGS)
REFCLK(CLK_PCIE_VGA)
B B
A A
WWW.AliSaler.Com
5 4 3 2 1
PCIE_CTX_C_GRX_P[7..0] PCIE_CRX_GTX_P[7..0]
4 PCIE_CTX_C_GRX_P[7..0] PCIE_CRX_GTX_P[7..0] 4
UV1A
PCIE_CTX_C_GRX_N[7..0] PCIE_CRX_GTX_N[7..0]
4 PCIE_CTX_C_GRX_N[7..0] PCIE_CRX_GTX_N[7..0] 4
V30 W24
U31 NC#V30 NC#W24 W23
NC#U31 NC#W23
U29 V27 with BOM strcture control, CV1--CV8 change to 0.22uf for CZ
T28 NC#U29 NC#V27 U26
NC#T28 NC#U26
R29 T26
P28 NC#R29 NC#T26 T27
NC#P28 NC#T27
P30
NC#P30 NC#T24
T24 change the GPU PN to AMD(EXO-S3 PRO), symbol check ok
N31 T23
NC#N31 NC#T23
N29
NC#N29 NC#P27
P27 11/4 change to PC sample SA000074V10
M28 P26
NC#M28 NC#P26
M30 P24
L31 NC#M30 NC#P24 P23
B NC#L31 NC#P23 B
L29 M27
K30 NC#L29 NC#M27 N26
NC#K30 NC#N26
CLOCK
CLK_PCIE_GPU AK30
8 CLK_PCIE_GPU CLK_PCIE_GPU# PCIE_REFCLKP
AK32
8 CLK_PCIE_GPU# PCIE_REFCLKN
+0.95VGS
CALIBRATION
Y22 RV3 1 PX@ 2 1.69K_0402_1%
PCIE_CALR_TX
1K_0402_1% 1 PX@ 2 RV4 N10 AA22 RV5 1 PX@ 2 1K_0402_1%
TEST_PG PCIE_CALR_RX
GPU_RST# AL27
16 GPU_RST# PERSTB
PX@
DV3
1
LBAT54AWT1G SOT323
5
A A
UV2
VCC
1
8 PXS_RST# IN1 GPU_RST#
4
2 OUT
Title
GND
PX@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG516
Date: Tuesday, April 12, 2016 Sheet 15 of 51
5 4 3 2 1
5 4 3 2 1
RECOMMENDED SETTINGS
CONFIGURATION STRAPS 0= DO NOT INSTALL RESISTOR
1 = INSTALL 10K RESISTOR
UV1B ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE X = DESIGN DEPENDANT
GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESET NA = NOT APPLICABLE
AF2
NC#AF2 RECOMMENDED
NC#AF4
AF4 MLPS Bit Strap Name Description
SETTINGS
N9 AG3 PS_0[1] ROM_CONFIG[0] Define the ROM type when STRAP_BIOS_ROM_EN = 1,
L9 DBG_DATA16 NC#AG3 AG5 PS_0[2] ROM_CONFIG[1] Define the primary memory-aperture size when STRAP_BIOS_ROM_EN = 0.
AE9 DBG_DATA15 NC#AG5 PS_0[3] ROM_CONFIG[2] X
DBG_DATA14 DPA
Y11 AH3 001 = 256MB
AE8 DBG_DATA13 NC#AH3 AH1
AD9 DBG_DATA12 NC#AH1 PS_0[4] N/A Reserved for internal use only. Must be 1 at reset. 1
AC10 DBG_DATA11 AK3
AD7 DBG_DATA10 NC#AK3 AK1 AUD_PORT_CONN_ The LSB (least significant bit) of the strap option that
AC8 DBG_DATA9 NC#AK1 PS_0[5] PINSTRAP[0] indicates the number of audio-capable display outputs. 1
DVO
AC7 DBG_DATA8 AK5
AB9 DBG_DATA7 NC#AK5 AM3 1 = PCIe GEN3 is supported.
AB8 DBG_DATA6 NC#AM3 PS_1[1] STRAP_BIF_GEN3_EN_A 0 = PCIe GEN3 is not supported. 1= Not support X
AB7 DBG_DATA5 AK6
AB4 DBG_DATA4 NC#AK6 AM5 0 = The CLKREQB power management capability is disabled
DBG_DATA3 NC#AM5
Reserve AB2
DBG_DATA2 DPB PS_1[2] STRAP_BIF_CLK_PM_EN 1 = The CLKREQB power management capability is enabled 0
Y8 AJ7
D
Y7 DBG_DATA1 NC#AJ7 AH6 PS_1[3] N/A Reserved for internal use only. Must be 0 at reset. 0 D
1
TOPAZ@ GPU_VR_HOT# RV104 1 PX@ 2 0_0402_5% GPU_GPIO8 P10 AJ27 4.7K_0402_5% 1 TOPAZ@2 RV22
RV101 1 2 0_0402_5% +VGA_CORE_GPIO2 GPU_GPIO9 P4 GPIO_8_ROMSO NC_VSYNC RV71 RV74
TOPAZ@ GPU_GPIO10 P2 GPIO_9_ROMSI 8.45K_0402_1% 8.45K_0402_1%
RV102 1 2 0_0402_5% +VGA_CORE_GPIO14 GPU_GPIO11 N6 GPIO_10_ROMSCK AD22 PX@ PX@
GPU_GPIO12 NC_GPIO_11 NC_RSET Pull down for none OBFF design
TOPAZ@ @ PAD TV3 1 N5
2
RV108 1 2 0_0402_5% +VGA_CORE_GPIO18 GPU_GPIO13 N3 NC_GPIO_12 AG24 PS_0 PS_1
TOPAZ@ +VGA_CORE_GPIO14 Y9 NC_GPIO_13 NC_AVDD AE22
NC_GPIO_14 NC_AVSSQ
1
GPU_SVD 0_0402_5% 1 EXO@2 RV103 GPU_VID3 N1
GPIO_15_PWRCNTL_0 1 1
C 10K_0402_5% 1 @ 2 RV67 GPU_GPIO16 M4 AE23 RV77 CV15 RV80 CV16 C
0_0402_5% 1 @ 2 RV107 GPU_GPIO17 R6 GPIO_16 NC_VDD1DI AD23 2K_0402_1% .01U_0402_16V7-K 2K_0402_1% .01U_0402_16V7-K
36,49 GPU_VR_HOT# +VGA_CORE_GPIO18 W10 GPIO_17_THERMAL_INT NC_VSS1DI PX@ @ PX@ @
10K_0402_5% 1 PX@ 2 RV68 GPIO_19_CTF M2 NC_GPIO_18 2 2
FutureASIC/SEYMOUR/PARK
2
GPU_SVC 0_0402_5% 1 EXO@2 RV105 GPU_VID4 P8 GPIO_19_CTF AM12 CEC_1 1 @ TV5
GPU_GPIO21 P7 GPIO_20_PWRCNTL_1 CEC_1 PAD
GPU_GPIO22 N8 GPIO_21
GPU_VID2 AK10 GPIO_22_ROMCSB AK12 GPU_SVD_R RV110 1TOPAZ@ 2 0_0402_5% +1.8VGS +1.8VGS
GPU_VR_HOT# 0_0402_5% 1 GPIO_29 NC_SVI2#AK12 GPU_SVD 49
@ 2 RV1012 GPU_VID1 AM10 AL11 GPU_SVT_R RV109 1TOPAZ@ 2 0_0402_5%
GPU_CLKREQ#_R GPIO_30 NC_SVI2#AL11 GPU_SVC_R GPU_SVT 49
0_0402_5% 1 @ 2 RV124 N7 AJ11 RV111 1TOPAZ@ 2 0_0402_5%
7 GPU_CLKREQ# CLKREQB NC_SVI2#AJ11 GPU_SVC 49
1
JTAG_TRSTB L6 RV60 RV63
+3VGS JTAG_TDI L5 JTAG_TRSTB 10K_0402_5% 8.45K_0402_1%
JTAG_TCK L3 JTAG_TDI @ @
PAD JTAG_TMS L1 JTAG_TCK AL13 GENLK_CLK 1 TV1 PAD @
2
10K_0402_5% 1 @ 2 RV72 JTAG_TRSTB TV7 @ 1JTAG_TDO K4 JTAG_TMS NC_GENLK_CLK AJ13 GENLK_VSYNC 1 TV2 PAD @ PS_2 PS_3
10K_0402_5% 1 @ 2 RV75 JTAG_TDI RV64 1 PX@ 2 TESTEN K7 JTAG_TDO NC_GENLK_VSYNC
TESTEN
1
10K_0402_5% 1 @ 2 RV78 JTAG_TMS 1K_0402_5% AF24 1 1
NC#AF24 AG13 RV69 CV18 RV70 CV19
10K_0402_5% 1 @ 2 RV40 JTAG_TCK NC_SWAPLOCKA AH12 4.75K_0402_1% .01U_0402_16V7-K 2K_0402_1% .01U_0402_16V7-K
0_0402_5% 1 2 RV112 AB13 NC_SWAPLOCKB PX@ @ @ @
+VGA_CORE NC_GENERICA 2 2
TOPAZ@ W8
2
0_0402_5% 1 2 RV113 W9 NC_GENERICB
TOPAZ@ W7 NC_GENERICC AC19 PS_0
0_0402_5% 1 2 RV114 AD10 NC_GENERICD PS_0
TOPAZ@ AJ9 NC_GENERICE_HPD4 AD19 PS_1
AL9 NC#AJ9 PS_1
DBG_CNTL0 PS_2
Bit BOM
AE17 MLPS
PS_2
PX_EN
AC14
NC_HPD1 PS_3
5 4 3 2 1 R _ p u ( ) R _ p d ( ) C(nF)
PAD TV6 @ 1 AB16 AE20
PX_EN PS_3
PS_0[5:1] 1 1 0 0 1 RV71=8.45k RV77=2K CV15=NC
4.7K_0402_5% 1 @ 2RV54
PX@ 2 1 CV25 XTALIN AE19 PS_1[5:1] 1 1 0 0 1 RV74=NC RV77=4.75K CV16=NC
AC16 TS_A
8P_0201_25V8-D NC_DBG_VREFG
PS_2[5:1] 1 1 0 0 0 RV60=NC RV69=4.75K CV18=NC
PS_3[5:1] 1 1 X X X RV63=X76 RV70=X76 CV19=X76
DDC/AUX
2
AE6
27MHZ_10PF_7V27000050
NC_DDC1CLK
YV1 PLL/CLOCK AE5 with BOM strcture control, R_pu (Ω ) R_pd (Ω ) Bits [3:1]
GND1
OSC1
PX@ NC_DDC1DATA
RV63,RV70 change to different value to
1
SEYMOUR/FutureASIC AC1
GPU_DPLUS NC_DDCVGACLK
no symbol for 8pf cap, PLM has PN,change the PN PAD TV13@ 1
GPU_DMINUS
T4
DPLUS THERMAL NC_DDCVGADATA
AC3 RV23 NC 11 Note: 0402 1% resistors are required.
PAD TV14@ 1 T2
DMINUS 0_0402_5%
EXO@ +3VGS +VDDIO_GPU
2
RV41 1 @ 2 GPIO_28_FDO R5
+3VGS GPIO28_FDO
10K_0402_5% +1.8VGS LV3 1 2 PX@ +TSVDD AD17
TSVDD SVC SVD Output Voltage (V) RV234 1 2 EXO@
BLM15PD121SN1D_2P AC17 +1.8VGS 0_0402_5%
TSVSS +VGA_CORE
CV21
0 0 1.1
1U_0402_6.3V6K
2
2
1 1 0.8
RV205 RV204 RV209
10K_0402_5% 10K_0402_5% 10K_0402_5%
Connect GPIO_28 to 10K pull @ PX@ @
down to enable MLPS.
1
GPU_SVD
GPU_SVC
GPU_SVT
RV242 2 @ 1 0_0402_5% WRST# 36
2
2
RV206 RV210
RV243 2 @ 1 0_0402_5% APU_SHUTDOWN# 7 10K_0402_5% RV207 10K_0402_5%
PX@ 10K_0402_5% @
@
1
1
1
@ C QV13
GPU_RST# 1 2 DV2 RV128 1 @ 2 2 MMBT3904WH_SOT323-3 Internal VGA Thermal Sensor
15 GPU_RST# B
2.2K_0402_5% @
E
0.1U_0201_6.3V6-K
SDM10U45LP-7_DFN1006-2-2
3
1
+3VGS
1
RV131 CV215 +3VGS
GPIO_19_CTF 1 @ 2 RV132 1K_0402_5%
47K_0402_5% @
1
A
2 A
2
RV43 RV44
2
47K_0402_5% 47K_0402_5%
G
PX@ PX@
2
EC_SMB_CK2 6,30,36
D
2N7002KDWH_SOT363-6
G
EC_SMB_DA2 6,30,36
D
2N7002KDWH_SOT363-6
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THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
3 2
Size
Date:
Document Number
Custom
UV1F
+VGA_CORE
D D
AB11 RV117 1 2 0_0402_5% TOPAZ@
NC_VARY_BL AB12 RV119 1 2 0_0402_5% TOPAZ@
NC_DIGON
AL15
NC_UPHYAB_TMDPA_TX0N AK14
NC_UPHYAB_TMDPA_TX0P
AH16
NC_UPHYAB_TMDPA_TX1N AJ15
NC_UPHYAB_TMDPA_TX1P
AL17
NC_UPHYAB_TMDPA_TX2N AK16
NC_UPHYAB_TMDPA_TX2P
AH18
NC_UPHYAB_TMDPA_TX3N AJ17
NC_UPHYAB_TMDPA_TX3P
AL19
NC_TXOUT_L3P AK18
NC_TXOUT_L3N
C C
TMDP
AH20
NC_UPHYAB_TMDPB_TX0N AJ19
NC_UPHYAB_TMDPB_TX0P
AL21
NC_UPHYAB_TMDPB_TX1N AK20
NC_UPHYAB_TMDPB_TX1P
AH22
NC_UPHYAB_TMDPB_TX2N AJ21
NC_UPHYAB_TMDPB_TX2P
AL23
NC_UPHYAB_TMDPB_TX3N AK22
NC_UPHYAB_TMDPB_TX3P
AK24
NC_TXOUT_U3P AJ23
NC_TXOUT_U3N
A A
PX@
PX@
10U_0603_6.3V6M
1U_0402_6.3V6K
DP POWER NC/DP POWER
1 1
AG15 AE11 AA27 A3
AG16 NC_DP_VDDR#AG15 NC#AE11 AF11 AB24 GND_1 GND_65 A30
D D
AF16 NC_DP_VDDR#AG16 NC#AF11 AE13 AB32 GND_2 GND_66 AA13
2 2 NC_DP_VDDR#AF16 NC#AE13 GND_3 GND_67
CV39
CV40
AG17 AF13 AC24 AA16
AG18 NC_DP_VDDR#AG17 NC#AF13 AG8 AC26 GND_4 GND_68 AB10
AG19 NC_DP_VDDR#AG18 NC#AG8 AG10 AC27 GND_5 GND_69 AB15
AF14 NC_DP_VDDR#AG19 NC#AG10 AD25 GND_6 GND_70 AB6
DP_VDDR#AF14 AD32 GND_7 GND_71 AC9
AE27 GND_8 GND_72 AD6
+0.95VGS GND_9 GND_73
(0.95V@560mA DP_VDDC) AF32
GND_10 GND_74
AD8
@ AG27 AE7
RV47 1 2 0_0603_5% +DP_VDDC AG20 AF6 AH32 GND_11 GND_75 AG12
NC_DP_VDDC#AG20 NC#AF6 GND_12 GND_76
CV38
AG21 AF7 K28 AH10
AF22 NC_DP_VDDC#AG21 NC#AF7 AF8 K32 GND_13 GND_77 AH28
0.1U_0201_6.3V6-K
NC_DP_VDDC#AF22 NC#AF8 GND_14 GND_78
1U_0402_6.3V6K
AG22 AF9 L27 B10
AD14 NC_DP_VDDC#AG22 NC#AF9 M32 GND_15 GND_79 B12
1 1 DP_VDDC#AD14 GND_16 GND_80
CV37
N25 B14
N27 GND_17 GND_81 B16
P25 GND_18 GND_82 B18
2 2 AG14 AE1 P32 GND_19 GND_83 B20
NC_DP_VSSR_1 NC#AE1 GND_20 GND_84
PX@
PX@
AH14 AE3 R27 B22
AM14 NC_DP_VSSR_2 NC#AE3 AG1 T25 GND_21 GND_85 B24
AM16 NC_DP_VSSR_3 NC#AG1 AG6 T32 GND_22 GND_86 B26
AM18 NC_DP_VSSR_4 NC#AG6 AH5 U25 GND_23 GND_87 B6
AF23 NC_DP_VSSR_5 NC#AH5 AF10 U27 GND_24 GND_88 B8
AG23 NC_DP_VSSR_6 NC#AF10 AG9 V32 GND_25 GND_89 C1
C
AM20 NC_DP_VSSR_7 NC#AG9 AH8 W25 GND_26 GND_90 C32 C
AM22 NC_DP_VSSR_8 NC#AH8 AM6 W26 GND_27 GND_91 E28
AM24 NC_DP_VSSR_9 NC#AM6 AM8 W27 GND_28 GND_92 F10
AF19 NC_DP_VSSR_10 NC#AM8 AG7 Y25 GND_29 GND_93 F12
AF20 NC_DP_VSSR_11 NC#AG7 AG11 Y32 GND_30 GND_94 F14
AE14 NC_DP_VSSR_12 NC#AG11 GND_31 GND_95 F16
DP_VSSR_13 GND_96 F18
GND_97 F2
GND_98 F20
RV49 1 2 @ AF17 AE10 M6 GND_99 F22
150_0402_1% NC_UPHYAB_DP_CALR NC#AE10 N13 GND_32 GND_100 F24
N16 GND_33 GND_101 F26
N18 GND_34 GND_102 F6
S IC 216-0867-071 A0 FCBGA 631P GPU 12 N21 GND_35 GND
GND_103 F8
EXO@ P6 GND_36 GND_104 G10
P9 GND_37 GND_105 G27
R12 GND_38 GND_106 G31
R15 GND_39 GND_107 G8
R17 GND_40 GND_108 H14
R20 GND_41 GND_109 H17
T13 GND_42 GND_110 H2
T16 GND_43 GND_111 H20
T18 GND_44 GND_112 H6
T21 GND_45 GND_113 J27
T6 GND_46 GND_114 J31
B B
U15 GND_47 GND_115 K11
U17 GND_48 GND_116 K2
U20 GND_49 GND_117 K22
U9 GND_50 GND_118 K6
V13 GND_51 GND_119
V16 GND_52
V18 GND_53
Y10 GND_54
Y15 GND_55
Y17 GND_56
Y20 GND_57
R11 GND_58 A32
T11 GND_59 VSS_MECH_1 AM1
AA11 GND_60 VSS_MECH_2 AM32
M12 GND_61 VSS_MECH_3
N11 GND_62
V11 GND_63
GND_64
A A
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5 4 3 2 1
+1.35VGS
For DDR3/GDDR5, 1500mA@1.5V
CV48
CV51
CV52
CV53
CV54
CV55
0.1U_0201_6.3V6-K
10U_0603_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
0.01U_0201_10V6K
CV217
1 1 1 1 1 1 1 1 1 UV1D +1.8VGS
CV56
CV501 (1.8V@100mA PCIE_PVDD)
33P_0402_50V8J AM30
PCIE_PVDD
PCIE
MEM I/O
CV46
CV47
RF_PXNS@
2 2 2 2 2 2 2 2 2
10U_0603_6.3V6M
1U_0402_6.3V6K
H13 AB23
VDDR1_1 NC#AB23
PX@
PX@
PX@
PX@
PX@
SIT1CD@
H16 AC23 1 1
VDDR1_2 NC#AC23
PX@
PX@
RF H19 AD24
J10 VDDR1_3 NC#AD24 AE24
J23 VDDR1_4 NC#AE24 AE25
VDDR1_5 NC#AE25
PX@
PX@
J24 AE26 2 2
J9 VDDR1_6 NC#AE26 AF25
K10 VDDR1_7 NC#AF25 AG26
VDDR1_8 NC#AG26
+1.8VGS (1.8V@13mA VDD_CT) +VDD_CT K23
VDDR1_9
+0.95VGS
K24
VDDR1_10 (0.95V@2500mA PCIE_VDDC)
D LV7 1 @ 2 0_0402_5% K9 L23 D
VDDR1_11 PCIE_VDDC_1
CV144
L11 L24
VDDR1_12 PCIE_VDDC_2
CV64
CV65
CV66
CV67
CV68
CV69
CV71
1U_0402_6.3V6K
L12 L25
VDDR1_13 PCIE_VDDC_3
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 L13 L26
L20 VDDR1_14 PCIE_VDDC_4 M22
VDDR1_15 PCIE_VDDC_5 1 1 1 1 1 1 1 1
L21 N22 CV502
L22 VDDR1_16 PCIE_VDDC_6 N23 33P_0402_50V8J
VDDR1_17 PCIE_VDDC_7
PX@
2 N24 RF_PXNS@
PCIE_VDDC_8
PX@
PX@
PX@
PX@
PX@
PX@
2 2 2 2 2 2 2 2
SIT1CD@
R22
PCIE_VDDC_9 T22
LEVEL PCIE_VDDC_10 RF
U22
TRANSLATION PCIE_VDDC_11 V22
AA20 PCIE_VDDC_12 +VGA_CORE
AA21 VDD_CT_1
AB20 VDD_CT_2 AA15
VDD_CT_3 CORE VDDC_1
+3VGS (3.3V@25mA VDDR3) AB21
VDD_CT_4 VDDC_2
N15
CV141
CV143
CV146
CV148
CV150
CV152
CV159
CV133
CV137
CV151
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
CV73
CV74
CV75
CV76
CV77
CV84
N17
LV8 1 @ 2 0_0402_5% +VDDR3 VDDC_3 R13
VDDC_4
CV149
I/O R16
VDDC_5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
change LV4 to SM01000MK00 (S SUPPRE_ BLM15AG221SN1 122)
1U_0402_6.3V6K
AA17 R18
VDDR3_1 VDDC_6
as DFC suggest, footprint with 1 AA18
VDDR3_2 VDDC_7
Y21
AB17 T12
MURAT_BLM15PD121SN1D_2P VDDR3_3 VDDC_8
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
AB18 T15 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
VDDR3_4 VDDC_9 T17
VDDC_10
PX@
2 V12 T20
Y12 NC_VDDR4_1 VDDC_11 U13
+1.8VGS U12 NC_VDDR4_2 VDDC_12 U16
NC_VDDR4_3 VDDC_13
(1.8V@130mA MPLL_PVDD) VDDC_14
U18
PX@ V21
LV4 1 2 +MPLL_PVDD VDDC_15 V15
VDDC_16
CV26
CV34
CV27
CV139
CV153
CV156
CV160
CV134
CV135
BLM15AG221SN1 V17
VDDC_17
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
V20
VDDC_18
10U_0603_6.3V6M
10U_0603_6.3V6M
POWER
1U_0402_6.3V6K
0.1U_0201_6.3V6-K
Y13 1 1 1 1 1 1 1
VDDC_19 Y16 CV503
1 1 1 VDDC_20
1 Y18 33P_0402_50V8J
CV24 VDDC_21 AA12 RF_PXNS@
VDDC_22
PX@
PX@
PX@
2 2 2 2 2 2 2
@
SIT1CD@
SIT1CD@
SIT1CD@
For EMC M11
2 2 2 VDDC_23 N12
2 VDDC_24 U11
VDDC_25
PX@
PX@
SIT1CD@
RF
PLL
C +0.95VGS C
(0.95V@1400mA BIF_VDDC)
+1.8VGS R21
BIF_VDDC_1
(1.8V@75mA SPLL_PVDD) BIF_VDDC_2
U21
1
LV5 1 2 PX@ +SPLL_PVDD +MPLL_PVDD L8 CV41
MPLL_PVDD
CV29
CV30
CORE I/O
1 1 M13
+SPLL_PVDD H7 VDDCI_1 M15
1 SPLL_PVDD VDDCI_2
CV28 M16
VDDCI_3
@
+0.95VGS
CV218
CV219
CV158
CV132
CV136
CV138
0.1U_0201_6.3V6-K
0.1U_0201_6.3V6-K
M17
For EMC 2 2 VDDCI_4
10U_0603_6.3V6M
10U_0603_6.3V6M
(0.95V@100mA SPLL_VDDC)
CV220
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
M18
2 VDDCI_5 M20 +VGA_CORE
VDDCI_6 1 1 1 1 1 1 1 1
PX@
PX@
1
0.1U_0201_6.3V6-K
J7 RF_PXNS@
SPLL_PVSS
PX@
PX@
PX@
PX@
PX@
PX@
PX@
2 2 2 2 2 2 2 2
1U_0402_6.3V6K
0.1U_0201_6.3V6-K
RV166
1 1 470_0603_5%
CV36
1 RF @
CV33 S IC 216-0867-071 A0 FCBGA 631P GPU 12
1 2
@
For EMC EXO@
2 2 QV19 D
2 PXS_PWREN# 2
PX@
PX@
@ S 2N7002KW_SOT323-3
3
MOS. AO3402 VGS MAX is 12V
+1.8VALW TO +1.8VGS
+1.8VALW +1.8VGS Can change to low cost and small
QV2 +0.95VALW +0.95VGS
AO3402_SOT-23-3 size MOS. AO3402
PX@ +1.8VGS /0.5A Rdson<65mohm +0.95VALW to +0.95VGS QV3
1 3 AON7408L_DFN8-5
D S
10U_0603_6.3V6M
10U_0603_6.3V6M
B 1 B
small size MOS.Rdson<22mohm S1
G
5 2
D S2
1
470_0603_5%
S3
10U_0603_6.3V6M
10U_0603_6.3V6M
RV1001
CV242
1U_0402_6.3V6K
1 1 1 1 1 1
1
PXS_PWREN#_H
CV239
+5VALW CV518 CV519 CV241 CV243 1 @ 2 RV245 CV520 1
CV240
CV238
0.1U_0201_6.3V6-K 0.1U_0201_6.3V6-K @ 15K_0402_5% 0.1U_0201_6.3V6-K CV521
4
+20VSB 1 PX@ 2 RV1015 @ @ 2 PX@ 2@ 2 PX@ @ 0.1U_0201_6.3V6-K RV1002
PX@
1 2
1 2
120K_0402_5% 2 PXS_PWREN# +5VALW 130K_0402_5%
G 1 @ 2 RV1016 D QV21
1
1
1
CV237 120K_0402_5% 2 PXS_PWREN#
1
1
1
D RV123 0.1U_0201_25V6-K S @ D RV1004 CV221 G
3
3
2 2N7002KW_SOT323-3
2
2
PX@ S PX@ S
3
2N7002KW_SOT323-3 2N7002KW_SOT323-3
RV127 is 1% , will change to 5%
change MOS from 7408 to 6414 for Rds on consider
LP2301ALT1G_SOT23-3
10U_0603_6.3V6M
1U_0402_6.3V6K
470_0603_5%
G
1 1
2
RV1007 @
470_0603_5%
1 2
PX@
+5VALW @
PX@
2 2 D QV25
2
1
RV1009 PX@ 2 PXS_PWREN# 2 PX@ 1 RV1010 2 PXS_PWREN#
20K_0402_5% 15K_0402_5% G
1
A D QV28 A
1
CV517 2 PXS_PWREN# S 2N7002KW_SOT323-3
3
1
D 0.1U_0201_6.3V6-K G @
PXS_PWREN 2 QV27 PX@
7,48,49 PXS_PWREN G 2 S 2N7002KW_SOT323-3
3
@
PX@ S
3
2N7002KW_SOT323-3
UV1C
FBA_D[63..0]
FBA_D[63..0] 21,22 GDDR5/DDR3 GDDR5/DDR3
FBA_D0 K27 K17 FBA_MA0
FBA_MA[15..0] FBA_D1 J29 DQA0_0 MAA0_0/MAA_0 J20 FBA_MA1
FBA_MA[15..0] 21,22 FBA_D2 DQA0_1 MAA0_1/MAA_1 FBA_MA2
H30 H23
FBA_BA[2..0] FBA_D3 H32 DQA0_2 MAA0_2/MAA_2 G23 FBA_MA3
FBA_BA[2..0] 21,22 FBA_D4 DQA0_3 MAA0_3/MAA_3 FBA_MA4
G29 G24
FBA_D5 F28 DQA0_4 MAA0_4/MAA_4 H24 FBA_MA5
FBA_D6 F32 DQA0_5 MAA0_5/MAA_5 J19 FBA_MA6
D DQA0_6 MAA0_6/MAA_6 D
FBA_D7 F30 K19 FBA_MA7
FBA_D8 C30 DQA0_7 MAA0_7/MAA_7 G20 FBA_MA13
FBA_D9 F27 DQA0_8 MAA0_8/MAA_13 L17 FBA_MA15
FBA_D10 A28 DQA0_9 MAA0_9/MAA_15
FBA_D11 C28 DQA0_10 J14 FBA_MA8
FBA_D12 E27 DQA0_11 MAA1_0/MAA_8 K14 FBA_MA9
FBA_D13 G26 DQA0_12 MAA1_1/MAA_9 J11 FBA_MA10
FBA_D14 D26 DQA0_13 MAA1_2/MAA_10 J13 FBA_MA11
FBA_D15 F25 DQA0_14 MAA1_3/MAA_11 H11 FBA_MA12
FBA_D16 A25 DQA0_15 MAA1_4/MAA_12 G11 FBA_BA2
FBA_D17 C25 DQA0_16 MAA1_5/MAA_BA2 J16 FBA_BA0
FBA_D18 E25 DQA0_17 MAA1_6/MAA_BA0 L15 FBA_BA1
FBA_D19 D24 DQA0_18 MAA1_7/MAA_BA1 G14 FBA_MA14
FBA_D20 E23 DQA0_19 MAA1_8/MAA_14 L16
MEMORY INTERFACE
FBA_D21 F23 DQA0_20 MAA1_9/RSVD
FBA_D22 DQA0_21 FBA_DQM0 FBA_DQM[7..0] 21,22
D22 E32
FBA_D23 F21 DQA0_22 WCKA0_0/DQMA0_0 E30 FBA_DQM1
FBA_D24 E21 DQA0_23 WCKA0B_0/DQMA0_1 A21 FBA_DQM2
FBA_D25 D20 DQA0_24 WCKA0_1/DQMA0_2 C21 FBA_DQM3
FBA_D26 F19 DQA0_25 WCKA0B_1/DQMA0_3 E13 FBA_DQM4
FBA_D27 A19 DQA0_26 WCKA1_0/DQMA1_0 D12 FBA_DQM5
FBA_D28 D18 DQA0_27 WCKA1B_0/DQMA1_1 E3 FBA_DQM6
FBA_D29 F17 DQA0_28 WCKA1_1/DQMA1_2 F4 FBA_DQM7
FBA_D30 A17 DQA0_29 WCKA1B_1/DQMA1_3
FBA_D31 DQA0_30 FBA_DQS0 FBA_DQS[7..0] 21,22
C17 H28
FBA_D32 E17 DQA0_31 EDCA0_0/QSA0_0 C27 FBA_DQS1
FBA_D33 D16 DQA1_0 EDCA0_1/QSA0_1 A23 FBA_DQS2
C DQA1_1 EDCA0_2/QSA0_2 C
+1.35VGS FBA_D34 F15 E19 FBA_DQS3
FBA_D35 A15 DQA1_2 EDCA0_3/QSA0_3 E15 FBA_DQS4
FBA_D36 D14 DQA1_3 EDCA1_0/QSA1_0 D10 FBA_DQS5
DQA1_4 EDCA1_1/QSA1_1
1
FBA_D60 J6
B DQA1_28 B
RV62 FBA_D61 J1 G19 FBA_CASA0#
FBA_D62 DQA1_29 CASA0B FBA_CASA1# FBA_CASA0# 21
40.2_0402_1% J3 G16
FBA_D63 DQA1_30 CASA1B FBA_CASA1# 22
PX@ J5
DQA1_31 H22 FBA_CSA0#
FBA_CSA0# 21
2
1 G13 FBA_CSA1#
CSA1B_0 FBA_CSA1# 22
RV66 CV157 J25 K13
100_0402_1% 1U_0402_6.3V6K RV55 1 2 PX@ K25 NC#J25 CSA1B_1
PX@ PX@ 120_0402_1% MEM_CALRP0 K20 FBA_CKEA0
2 CKEA0 FBA_CKEA1 FBA_CKEA0 21
J17
FBA_CKEA1 22
2
CKEA1
G25 FBA_WEA0#
WEA0B FBA_WEA1# FBA_WEA0# 21
DRAMRST L10 H10
DRAM_RST WEA1B FBA_WEA1# 22
PAD @ TV8 1 CLKTESTA K8
PAD @ TV9 1 CLKTESTB L7 CLKTESTA
CLKTESTB
RV58 1
4.99K_0402_1% CV147
PX@ 120P_0402_50V8-J
Security Classification LC Future Center Secret Data Title
PX@
2
2
Issued Date 2013/08/08 Deciphered Date 2013/08/05 ATI_JET-LE_MEM IF
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG516
Date: Tuesday, April 12, 2016 Sheet 20 of 51
5 4 3 2 1
WWW.AliSaler.Com
5 4 3 2 1
FBA_MA[15..0] 20,22
FBA_BA[2..0] 20,22
FBA_DQS[3..0] 20
FBA_DQM[3..0] 20
FBA_D[31..0] 20
20
UV6
D UV5 D
+FBA_VREFC0_L M8 E3 FBA_D19
+FBA_VREFC0_U M8 E3 FBA_D1 H1 VREFCA DQL0 F7 FBA_D16 +1.35VGS +1.35VGS
H1 VREFCA DQL0 F7 FBA_D6 VREFDQ DQL1 F2 FBA_D23
VREFDQ DQL1 F2 FBA_D2 FBA_MA0 N3 DQL2 F8 FBA_D21
DQL2 A0 DQL3 Group2 (IN1)
1
FBA_MA0 N3 F8 FBA_D7 FBA_MA1 P7 H3 FBA_D22
FBA_MA1 P7 A0 DQL3 H3 FBA_D0 FBA_MA2 P3 A1 DQL4 H8 FBA_D18 RV18 RV20
FBA_MA2 A1 DQL4 FBA_D5
Group0 (IN3) FBA_MA3 A2 DQL5 FBA_D20
P3 H8 N2 G2 4.99K_0402_1% 4.99K_0402_1%
FBA_MA3 N2 A2 DQL5 G2 FBA_D3 FBA_MA4 P8 A3 DQL6 H7 FBA_D17 PX@ PX@
FBA_MA4 P8 A3 DQL6 H7 FBA_D4 FBA_MA5 P2 A4 DQL7
2
FBA_MA5 P2 A4 DQL7 FBA_MA6 R8 A5 +FBA_VREFC0_U +FBA_VREFC0_L
FBA_MA6 R8 A5 FBA_MA7 R2 A6 D7 FBA_D9
FBA_MA7 R2 A6 D7 FBA_D31 FBA_MA8 T8 A7 DQU0 C3 FBA_D10
A7 DQU0 A8 DQU1
1
FBA_MA8 T8 C3 FBA_D27 FBA_MA9 R3 C8 FBA_D13 1 1
FBA_MA9 R3 A8 DQU1 C8 FBA_D30 FBA_MA10 L7 A9 DQU2 C2 FBA_D12 RV19 CV100 RV21 CV101
FBA_MA10 A9 DQU2 FBA_D25 FBA_MA11 A10/AP DQU3 FBA_D8
Group1 (TOP)
L7 C2 R7 A7 4.99K_0402_1% 0.1U_0201_6.3V6-K 4.99K_0402_1% 0.1U_0201_6.3V6-K
FBA_MA11 R7 A10/AP DQU3 A7 FBA_D28 FBA_MA12 N7 A11 DQU4 A2 FBA_D14 PX@ PX@ PX@ PX@
FBA_MA12 A11 DQU4 FBA_D24
Group3 (BOT) FBA_MA13 A12/BC DQU5 FBA_D15 2 2
N7 A2 T3 B8
2
FBA_MA13 T3 A12/BC DQU5 B8 FBA_D29 FBA_MA14 T7 A13 DQU6 A3 FBA_D11
FBA_MA14 T7 A13 DQU6 A3 FBA_D26 A14 DQU7
A14 DQU7 +1.35VGS
+1.35VGS
FBA_BA0 M2 B2
FBA_BA0 M2 B2 FBA_BA1 N8 BA0 VDD_1 D9
FBA_BA1 N8 BA0 VDD_1 D9 FBA_BA2 M3 BA1 VDD_2 G7
FBA_BA2 M3 BA1 VDD_2 G7 BA2 VDD_3 K2
BA2 VDD_3 K2 VDD_4 K8
VDD_4 K8 VDD_5 N1
VDD_5 N1 FBA_CLKA0 J7 VDD_6 N9
FBA_CLKA0 J7 VDD_6 N9 FBA_CLKA0# K7 CK VDD_7 R1
20 FBA_CLKA0 FBA_CLKA0# CK VDD_7 FBA_CKEA0 CK VDD_8
K7 R1 K9 R9
20 FBA_CLKA0# FBA_CKEA0 CK VDD_8 CKE VDD_9
K9 R9
20 FBA_CKEA0 CKE VDD_9
FBA_ODTA0 K1 A1
FBA_ODTA0 K1 A1 FBA_CSA0# L2 ODT VDDQ_1 A8
C 20 FBA_ODTA0 FBA_CSA0# ODT VDDQ_1 FBA_RASA0# CS VDDQ_2 C
L2 A8 J3 C1
20 FBA_CSA0# FBA_RASA0# CS VDDQ_2 FBA_CASA0# RAS VDDQ_3
J3 C1 K3 C9
20 FBA_RASA0# FBA_CASA0# RAS VDDQ_3 FBA_WEA0# CAS VDDQ_4
K3 C9 L3 D2
20 FBA_CASA0# FBA_WEA0# CAS VDDQ_4 WE VDDQ_5
L3 D2 E9
20 FBA_WEA0# WE VDDQ_5 VDDQ_6
E9 F1
VDDQ_6 F1 FBA_DQS2 F3 VDDQ_7 H2
FBA_DQS0 F3 VDDQ_7 H2 FBA_DQS1 C7 DQSL VDDQ_8 H9
FBA_DQS3 C7 DQSL VDDQ_8 H9 DQSU VDDQ_9
DQSU VDDQ_9
FBA_DQM2 E7 A9
FBA_DQM0 E7 A9 FBA_DQM1 D3 DML VSS_1 B3
FBA_DQM3 D3 DML VSS_1 B3 DMU VSS_2 E1
DMU VSS_2 E1 VSS_3 G8
VSS_3 G8 FBA_DQS#2 G3 VSS_4 J2
FBA_DQS#0 G3 VSS_4 J2 FBA_DQS#1 B7 DQSL VSS_5 J8
FBA_DQS#3 B7 DQSL VSS_5 J8 DQSU VSS_6 M1
DQSU VSS_6 M1 VSS_7 M9
VSS_7 M9 VSS_8 P1
VSS_8 P1 FBA_RST# T2 VSS_9 P9 FBA_CLKA0
FBA_RST# T2 VSS_9 P9 RESET VSS_10 T1
20,22 FBA_RST# RESET VSS_10 VSS_11
T1 L8 T9
VSS_11 ZQ VSS_12
1
L8 T9
ZQ VSS_12 RV26
J1 B1 40.2_0402_1%
NC1 VSSQ_1
1
1
J1 B1 L1 B9 PX@
RV15 RV16 L1 NC1 VSSQ_1 B9 RV17 J9 NC2 VSSQ_2 D1
2
10K_0402_5% 243_0402_1% J9 NC2 VSSQ_2 D1 243_0402_1% L9 NC3 VSSQ_3 D8 CV104
@ PX@ L9 NC3 VSSQ_3 D8 PX@ FBA_MA15 M7 NC4 VSSQ_4 E2 1 2
FBA_MA15 M7 NC4 VSSQ_4 E2 NC5 VSSQ_5 E8
2
1
F9 G1
VSSQ_7 G1 VSSQ_8 G9 RV27
VSSQ_8 G9 VSSQ_9 40.2_0402_1%
VSSQ_9 96-BALL PX@
B 96-BALL SDRAM DDR3 B
2
SDRAM DDR3 K4W4G1646B-HC11_FBGA96
K4W4G1646B-HC11_FBGA96 FBA_CLKA0#
@
@
+1.35VGS UV5 SIDE +1.35VGS UV6 SIDE
CV78 CV79 CV80 CV81 CV82 CV83 CV89 CV90 CV91 CV92 CV93 CV94
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1
PX@
PX@
PX@
SIT1CD@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
SIT1CD@
2 2 2 2 2 2 2 2 2 2 2 2
+1.35VGS
UV5 SIDE +1.35VGS UV6 SIDE
CV155 CV85 CV86 CV87 CV88 CV95 CV96 CV97 CV98 CV99
0.1U_0201_6.3V6-K
0.1U_0201_6.3V6-K
0.1U_0201_6.3V6-K
0.1U_0201_6.3V6-K
0.1U_0201_6.3V6-K
0.1U_0201_6.3V6-K
0.1U_0201_6.3V6-K
0.1U_0201_6.3V6-K
0.1U_0201_6.3V6-K
0.1U_0201_6.3V6-K
1 1 1 1 1 1 1 1 1 1 1 1
CV505 CV506
33P_0402_50V8J 33P_0402_50V8J
PX@
SIT1CD@
SIT1CD@
SIT1CD@
SIT1CD@
SIT1CD@
SIT1CD@
SIT1CD@
SIT1CD@
PX@
RF_PXNS@ RF_PXNS@
2 2 2 2 2 2 2 2 2 2 2 2
RF RF
A A
FBA_MA[15..0] 20,21
FBA_BA[2..0] 20,21
FBA_DQS[7..4] 20
FBA_DQM[7..4] 20
Memory Partition A - Upper 32 bits FBA_DQS#[7..4] 20
FBA_D[63..32] 20
UV7 UV8
1
FBA_MA3 N2 G2 FBA_D39 FBA_MA3 N2 G2 FBA_D63 RV30
FBA_MA4 P8 A3 DQL6 H7 FBA_D33 FBA_MA4 P8 A3 DQL6 H7 FBA_D58 RV32
FBA_MA5 P2 A4 DQL7 FBA_MA5 P2 A4 DQL7 4.99K_0402_1% 4.99K_0402_1%
FBA_MA6 R8 A5 FBA_MA6 R8 A5 PX@ PX@
FBA_MA7 R2 A6 D7 FBA_D40 FBA_MA7 R2 A6 D7 FBA_D55
2
FBA_MA8 T8 A7 DQU0 C3 FBA_D45 FBA_MA8 T8 A7 DQU0 C3 FBA_D51 +FBA_VREFC1_U +FBA_VREFC1_L
FBA_MA9 R3 A8 DQU1 C8 FBA_D43 FBA_MA9 R3 A8 DQU1 C8 FBA_D54
FBA_MA10 L7 A9 DQU2 C2 FBA_D44 FBA_MA10 L7 A9 DQU2 C2 FBA_D48
A10/AP DQU3 A10/AP DQU3
1
FBA_MA11 R7 A7 FBA_D42 Group5 (TOP) FBA_MA11 R7 A7 FBA_D52 Group6 (BOT) 1 1
FBA_MA12 N7 A11 DQU4 A2 FBA_D46 FBA_MA12 N7 A11 DQU4 A2 FBA_D50 RV31 CV127 RV33 CV128
FBA_MA13 T3 A12/BC DQU5 B8 FBA_D41 FBA_MA13 T3 A12/BC DQU5 B8 FBA_D53 4.99K_0402_1% 0.1U_0201_6.3V6-K 4.99K_0402_1% 0.1U_0201_6.3V6-K
FBA_MA14 T7 A13 DQU6 A3 FBA_D47 FBA_MA14 T7 A13 DQU6 A3 FBA_D49 PX@ PX@ PX@ PX@
A14 DQU7 A14 DQU7 2 2
2
+1.35VGS +1.35VGS
FBA_BA0 M2 B2 FBA_BA0 M2 B2
FBA_BA1 N8 BA0 VDD_1 D9 FBA_BA1 N8 BA0 VDD_1 D9
FBA_BA2 M3 BA1 VDD_2 G7 FBA_BA2 M3 BA1 VDD_2 G7
BA2 VDD_3 K2 BA2 VDD_3 K2
VDD_4 K8 VDD_4 K8
VDD_5 N1 VDD_5 N1
FBA_CLKA1 J7 VDD_6 N9 FBA_CLKA1 J7 VDD_6 N9
20 FBA_CLKA1 FBA_CLKA1# K7 CK VDD_7 FBA_CLKA1# CK VDD_7
R1 K7 R1
20 FBA_CLKA1# FBA_CKEA1 K9 CK VDD_8 FBA_CKEA1 CK VDD_8
R9 K9 R9
20 FBA_CKEA1 CKE VDD_9 CKE VDD_9
FBA_ODTA1 K1 A1 FBA_ODTA1 K1 A1
20 FBA_ODTA1 FBA_CSA1# ODT VDDQ_1 FBA_CSA1# ODT VDDQ_1
L2 A8 L2 A8
20 FBA_CSA1# FBA_RASA1# CS VDDQ_2 FBA_RASA1# CS VDDQ_2
J3 C1 J3 C1
20 FBA_RASA1# FBA_CASA1# RAS VDDQ_3 FBA_CASA1# RAS VDDQ_3
K3 C9 K3 C9
C 20 FBA_CASA1# FBA_WEA1# CAS VDDQ_4 FBA_WEA1# CAS VDDQ_4 C
L3 D2 L3 D2
20 FBA_WEA1# WE VDDQ_5 WE VDDQ_5
E9 E9
VDDQ_6 F1 VDDQ_6 F1
FBA_DQS4 F3 VDDQ_7 H2 FBA_DQS7 F3 VDDQ_7 H2
FBA_DQS5 C7 DQSL VDDQ_8 H9 FBA_DQS6 C7 DQSL VDDQ_8 H9
DQSU VDDQ_9 DQSU VDDQ_9
FBA_DQM4 E7 A9 FBA_DQM7 E7 A9
FBA_DQM5 D3 DML VSS_1 B3 FBA_DQM6 D3 DML VSS_1 B3
DMU VSS_2 E1 DMU VSS_2 E1
VSS_3 G8 VSS_3 G8
FBA_DQS#4 G3 VSS_4 J2 FBA_DQS#7 G3 VSS_4 J2
FBA_DQS#5 B7 DQSL VSS_5 J8 FBA_DQS#6 B7 DQSL VSS_5 J8
DQSU VSS_6 M1 DQSU VSS_6 M1
VSS_7 M9 VSS_7 M9
VSS_8 P1 VSS_8 P1
FBA_RST# T2 VSS_9 P9 FBA_RST# T2 VSS_9 P9
20,21 FBA_RST# RESET VSS_10 RESET VSS_10 FBA_CLKA1
T1 T1
L8 VSS_11 T9 L8 VSS_11 T9
ZQ VSS_12 ZQ VSS_12
1
1
1
J1 B1 J1 B1 RV38
RV28 L1 NC1 VSSQ_1 B9 RV29 L1 NC1 VSSQ_1 B9 40.2_0402_1%
243_0402_1% J9 NC2 VSSQ_2 D1 243_0402_1% J9 NC2 VSSQ_2 D1 PX@
PX@ L9 NC3 VSSQ_3 D8 PX@ L9 NC3 VSSQ_3 D8
2
FBA_MA15 M7 NC4 VSSQ_4 E2 FBA_MA15 M7 NC4 VSSQ_4 E2 CV131
2
2
NC5 VSSQ_5 E8 NC5 VSSQ_5 E8 1 2
VSSQ_6 F9 VSSQ_6 F9
VSSQ_7 G1 VSSQ_7 G1 PX@ .01U_0402_16V7-K
VSSQ_8 VSSQ_8
1
G9 G9
VSSQ_9 VSSQ_9 RV39
96-BALL 96-BALL 40.2_0402_1%
SDRAM DDR3 SDRAM DDR3 PX@
K4W4G1646B-HC11_FBGA96 K4W4G1646B-HC11_FBGA96
2
B B
FBA_CLKA1#
@ @
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1
PX@
SIT1CD@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
SIT1CD@
2 2 2 2 2 2 2 2 2 2 2 2
0.1U_0201_6.3V6-K
0.1U_0201_6.3V6-K
0.1U_0201_6.3V6-K
0.1U_0201_6.3V6-K
0.1U_0201_6.3V6-K
0.1U_0201_6.3V6-K
0.1U_0201_6.3V6-K
0.1U_0201_6.3V6-K
0.1U_0201_6.3V6-K
1 1 1 1 1 1 1 1 1 1 1 1
CV507 CV508
33P_0402_50V8J 33P_0402_50V8J
PX@
SIT1CD@
PX@
SIT1CD@
SIT1CD@
PX@
SIT1CD@
SIT1CD@
SIT1CD@
PX@
RF_PXNS@ RF_PXNS@
2 2 2 2 2 2 2 2 2 2 2 2
RF RF
A A
WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG516
Date: Tuesday, April 12, 2016 Sheet 22 of 51
5 4 3 2 1
5 4 3 2 1
+3VS
Need Short
RF_PXNS@
2A 80 mil
1U_0402_6.3V6K
D
0.1U_0201_6.3V6-K
1 2 Q7 3 1 2 R22 1
GND
4.7U_0805_25V6-K
0.1U_0201_25V6-K
33P_0402_50V8J
C1
4.7U_0402_6.3V6M
.1U_0402_10V6-K
0.01U_0402_25V7K
D 0_0805_5% C25 D
10U_0603_6.3V6M
0.1U_0201_6.3V6-K
PCH_ENVDD 4 3 1 @1 1 1 @ 1 1 1 C23
EN OCB
C1323
C1322
G
1 1
2
2 C1321 C3
SY6288C20AAC_SOT23-5 @ C23 0.1u for G HSW panel blink issue
2 2 2 2 @ 2 @ 2 2
2 2
C2
C122
C123
R5 1 @ 2 CMOS_ON#
PCH_ENVDD 36,38 PCH_CMOSP
100K_0402_5%
6 PCH_ENVDD
1
1
R35 C10
100K_0402_5% For RF .1U_0402_10V6-K
@
2
2
JEDP1
+LEDVDD 1
2 1
3 2
APU output enable Voh min is 1.8V-0.45V=1.35V 3
4
APU_EDP_TX0+ C19 2 1 0.1U_0201_6.3V6-K EDP_TX0+ 5 4
6 APU_EDP_TX0+ APU_EDP_TX0- C16 EDP_TX0- 5
2 1 0.1U_0201_6.3V6-K 6
6 APU_EDP_TX0- 6
7
APU_EDP_TX1+ C17 2 1 0.1U_0201_6.3V6-K EDP_TX1+ 8 7
6 APU_EDP_TX1+ APU_EDP_TX1- C18 EDP_TX1- 8
2 1 0.1U_0201_6.3V6-K 9
6 APU_EDP_TX1- 9
10
C APU_EDP_AUX C20 2 1 0.1U_0201_6.3V6-K EDP_AUX 11 10 C
6 APU_EDP_AUX APU_EDP_AUX# C21 EDP_AUX# 11
2 1 0.1U_0201_6.3V6-K 12
6 APU_EDP_AUX# 12
13
DISPOFF# 14 13
14
R19 1 2 0_0402_5% INVT_PWM
AUX don't pull high and pull low for eDP panel INVT_PWM
15
16 15
6 PCH_EDP_PWM 16
@ 17
+3VS 18 17
18
1
19
6 APU_EDP_HPD 19
R20 R21 1 @ 2 20
100K_0402_5% 0_0402_5% 21 20
1 +LCDVDD_CON 21
@
C22 470P_0201_50V7-K
W=60mils 22
23 22
+3VS
2
@ 24 23
2 35 DMIC_DATA 24
35 DMIC_CLK 25
26 25
Need Short 26
27
2 0_0402_5% USB20_P3_R 27
CMOS Camera
R182 1 @ 28
8 USB20_P3 28
R183 1 @ 2 0_0402_5% USB20_N3_R 29
+3VS 8 USB20_N3 29
+3VS_CMOS 30
31 30
1 G1
C1320 W=40mils 32
G2
2
.047U_0201_6.3V6K
R10 EMC_NS@ DRAPH_FC5AF301-3181H
B 4.7K_0402_5% L12 EMC_NS@ 2 B
ME@
@ USB20_N3 1 2 USB20_N3_R
1 2
1
470P_0201_50V7-K
470P_0201_50V7-K
100K_0402_5%
100P_0201_25V8J
EMC_NS@
EMC_NS@
C11
C12
C13
1 1 1
2
EMC_NS@
2 2 2
EMC
A A
1 1 1 1 1 1 1
CS2 CS3 CS4 CS5 CS11 CS12 CS13
0.1U_0201_6.3V6-K 0.1U_0201_6.3V6-K 0.1U_0201_6.3V6-K 0.1U_0201_6.3V6-K 0.1U_0201_6.3V6-K 0.1U_0201_6.3V6-K 0.1U_0201_6.3V6-K
2 2 2 2 2 2 2
D @ @ D
1 1 1 1
CS6 CS7 CS8 CS10
0.1U_0201_6.3V6-K 0.1U_0201_6.3V6-K 0.1U_0201_6.3V6-K 0.1U_0201_6.3V6-K
2 2 2 2
@ @
C C
CS14
CS18 +APU_GFX +APU_GFX
+5VS 1 2 +3VS
+APU_CORE_NB 1 2 +APU_CORE 1 1
0.1U_0201_6.3V6-K CS22 CS23
@ 0.1U_0201_6.3V6-K 0.1U_0201_6.3V6-K 0.1U_0201_6.3V6-K
@ 2 2
CS15
@ @
CS19
+5VS 1 2 +3VS
+APU_CORE_NB 1 2 +APU_CORE
0.1U_0201_6.3V6-K
@ 0.1U_0201_6.3V6-K
CS20
+1.2V +1.2V +1.2V +1.2V +1.2V
+APU_GFX 1 2 +APU_CORE
B 1 1 1 1 1 B
0.1U_0201_6.3V6-K CS24 CS25 CS26 CS27 CS28
0.1U_0402_25V6 0.1U_0402_25V6 0.1U_0402_25V6 0.1U_0402_25V6 0.1U_0402_25V6
CS17 @
CS21 2 2 2 2 2
+5VS 1 2 +3VS
+APU_GFX 1 2 +APU_CORE
0.1U_0201_6.3V6-K
0.1U_0201_6.3V6-K
@ reserve to reduce 1.2VAPU noise affected by B+
A A
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5 4 3 2 1
L2 EMC@
HDMI_CLK-_C 1 2 HDMI_CLK-_CON 1 2 EMC_NS@
1 2 C26 10P_0201_25V8G
5
C28 10P_0201_25V8G D3
G
Q1B HDMI_DET 1 1 10 9 HDMI_DET
HDMI_TX0+_C 4 3 HDMI_TX0+_CON 1 2 EMC_NS@
4 3 2 2
C29 10P_0201_25V8G HDMICLK_R 9 8 HDMICLK_R
EXC24CH900U_4P APU_DDC_CLK 4 3 HDMICLK_R
S
6 APU_DDC_CLK
4 4
D
HDMIDAT_R 7 7 HDMIDAT_R
L4 EMC@ 2N7002KDWH_SOT363-6
2
HDMI_TX1-_C 1 2 HDMI_TX1-_CON 1 2 EMC_NS@ +5VS_HDMI 5 5 6 6 +5VS_HDMI
G
1 2 C30 10P_0201_25V8G Q1A
3 3
HDMI_TX1+_C 4 3 HDMI_TX1+_CON 1 2 EMC_NS@
4 3 C31 10P_0201_25V8G APU_DDC_DATA 1 6 HDMIDAT_R 8
S
6 APU_DDC_DATA
D
EXC24CH900U_4P
2N7002KDWH_SOT363-6
L5 EMC@ AZ1045-04F_DFN2510P10E-10-9
HDMI_TX2-_C 1 2 HDMI_TX2-_CON 1 2 EMC_NS@ EMC_NS@
1 2 C32 10P_0201_25V8G
HDMI_TX2+_C HDMI_TX2+_CON 1
EMC
4 3 2 EMC_NS@
4 3 C33 10P_0201_25V8G
EXC24CH900U_4P
EMC +5VS_HDMI
+5VS +5VS_HDMI_F +5VS_HDMI
D5
2
2 F1
D4 1 1 2
+3VS 3
C @ RB491D_SOT23-3 0.5A_6V_1206L050YRHF C
@
BAT54S-7-F_SOT23-3
1
HDMI_CLK-_C R29 1 2 499_0402_1% 1 3
S
Follow Zx05 and beema Q22 1
1
HDMI_CLK+_C R30 1 2 499_0402_1% C LP2301ALT1G_SOT23-3 C34
Q43 2 R202 1 2 150K_0402_5% 0.1U_0201_6.3V6-K
G
2
4
3
HDMI_TX0-_C R31 1 2 499_0402_1% B
E MMBT3904WH_SOT323-3 RP2 2
12,38 SUSP
3
HDMI_TX0+_C R32 1 2 499_0402_1% 2.2K_0404_4P2R_5%
6 APU_HDMI_HPD
1
1
HDMI_TX1-_C R33 1 2 499_0402_1% R257
1
2
R910 100K_0402_5%
HDMI_TX1+_C R34 1 2 499_0402_1% 100K_0402_5% JHDMI1
HDMI_DET 19
2
HDMI_TX2-_C R37 1 2 499_0402_1% 18 HP_DET
2
17 +5V
HDMI_TX2+_C R38 1 2 499_0402_1% HDMIDAT_R 16 DDC/CEC_GND
HDMICLK_R 15 SDA
14 SCL
13 Reserved
CEC
1
D6 D7
HDMI_CLK+_CON 1 1 10 9 HDMI_CLK+_CON HDMI_TX1-_CON 1 1 10 9 HDMI_TX1-_CON
3 3 3 3
8 8
AZ1045-04F_DFN2510P10E-10-9 AZ1045-04F_DFN2510P10E-10-9
EMC_NS@ EMC_NS@
EMC
A A
+3VS +DP_3V3
@ +IVDDO +RX_AVCC
RVG161 2 0_0603_5%
0.1U_0201_6.3V6-K
1 LVG2 1 2 0_0402_5%
10U_0603_6.3V6M
CVG8 @
CVG10
10U_0603_6.3V6M 1 1
CVG15
D 2 D
32
23
25
16
30
31
6 APU_DP2_HPD UVG1
9
+IVDDO +RX_IVDD
OVDD1
OVDD2
IVDD33
IVDDO
IVDD1
IVDD2
IVDD3
IVDD4
RVG4 1 24.7K_0402_5% APU_DP2_HPD 26 @
HPD
0.1U_0201_6.3V6-K
RVG191 2 0_0603_5%
CVG51
CVG25 2 1 0.1U_0201_6.3V6-K DRX0N 19
6 APU_DP2_TX0- RX0N
@
CVG26 2 1 0.1U_0201_6.3V6-K DRX1P 20
6 APU_DP2_TX1+ RX1P 2
CVG23 2 1 0.1U_0201_6.3V6-K DRX1N 21
6 APU_DP2_TX1- RX1N
10
ISPSCL 11
CVG27 2 1 0.1U_0201_6.3V6-K AUXP 15 ISPSDA
6 APU_DP2_AUX RXAUXP
CVG24 2 1 0.1U_0201_6.3V6-K AUXN 14 13
6 APU_DP2_AUX# RXAUXN VGADDCCLK CRT_DDC_CLK 27
12
VGADDCSDA CRT_DDC_DAT 27 +IVDDO +DAC_VDDC
1
VSYNC VGADP_VS 27
2
HSYNC VGADP_HS 27
4.7U_0402_6.3V6M
0.1U_0201_6.3V6-K
LVG4 1 2 0_0402_5%
C @ C
1 1
+DAC_VDDC
CVG17
CVG11
+RX_AVCC
4
17
22 AVCC
ASPVCC
IT6516BFN VDDAC 2 2
7 CRTDP_R
IORP CRTDP_R 27
@ TVG4 1 29 6 CRTDP_G
PCSDA IOGP CRTDP_G 27
1 28
@ TVG2 PCSCL
5 CRTDP_B
IOBP CRTDP_B 27
3 RVG3 1 2 200_0402_1%
RSET
TVG5
RVG3 closed to pin3
1 24
@ URDBG
CRTDP_R
B B
GND CRTDP_G
IT6516BFN-BX-0061_QFN32_4X4
33
CRTDP_B
1
RVG25 RVG26 RVG27
75_0402_1% 75_0402_1% 75_0402_1%
2
CLOSE TO UVG1
A A
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DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG516
Date: Tuesday, April 12, 2016 Sheet 26 of 51
5 4 3 2 1
5 4 3 2 1
+CRT_VCC_CON +5VS_HDMI
CRT Connector
+5VS @
+CRT_VCC RVG391 2 0_0603_5%
DVG1
@ 2 FVG1
1 1 2 @ +CRT_VCC_CON
3 1
0.5A_6V_1206L050YRHF CVG34
1
D RB491D_SOT23-3 0.1U_0201_6.3V6-K D
DVG2
W=40mils
1
2 AZ5725-01F_DFN1006P2X2
EMC_NS@
2
EMC
2
JCRT1
6
@ PAD TVG3 1 CRT_DET# 11
CRTDP_R LVG6 1 2 EMC@ CRT_R_CON 1
26 CRTDP_R
BLM15BA220SN1D_2P 7
CRT_DDC_DAT_CON 12
CRTDP_G LVG7 1 2 EMC@ CRT_G_CON 2
26 CRTDP_G
BLM15BA220SN1D_2P 8
HSYNC_CON 13
CRTDP_B LVG8 1 2 EMC@ CRT_B_CON 3
26 CRTDP_B
BLM15BA220SN1D_2P 9
VSYNC_CON 14
15P_0402_50V8J
CVG35
15P_0402_50V8J
CVG36
15P_0402_50V8J
CVG37
15P_0402_50V8J
CVG38
15P_0402_50V8J
CVG39
15P_0402_50V8J
CVG40
1 1 1 1 1 1 4
10 G 16
CRT_DDC_CLK_CON 15 G 17
EMC@ EMC@ EMC@ EMC@ EMC@ EMC@ 5
2 2 2 2 2 2
1
CVG41 SUYIN_070546HR015M25KZR
100P_0201_25V8J @ ME@
2
C EMC C
3 3 3 3
B B
+CRT_VCC_CON
2
1
RPVG3
2.2K_0404_4P2R_5%
3
4
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
0.1U_0201_6.3V6-K
0.1U_0201_6.3V6-K
1 1 1 1 4.7U_0402_6.3V6M 0.1U_0201_6.3V6-K
D
Q14 3 1 @ CL4 CL5 CL6 CL7
1
2 2
0.01U_0201_10V6K
SIT1CD@ SIT1CD@
RL2 1 1
100K_0402_5% CL8 CL9 2 2 2 2
G
2
@ 0.1U_0201_6.3V6-K
@ @
2
2 2
SIT1CD@ SIT1CD@
RL3 1 @ 2
36 LAN_PWR_ON#
47K_0402_5%
Close to Pin11 Close to Pin32 Close to Pin11 Close to Pin32
+3VALW_LAN +3VS
2
+3VALW_LAN
2
RL4
G
10K_0402_5% QL1
2
@
RL5
1
10K_0402_5% UL1 LAN_CLKREQ#_R 1 3 @
LAN_CLKREQ# 7
@
S
2N7002KW_SOT323-3
1
+LAN_REGOUT 24 8 +LAN_VDD10
RL9 +LAN_VDDREG 23 REGOUT AVDD10_2 7 LAN_MDI2-
+LAN_VDD10 VDDREG MDIN2 LAN_MDI2+ LAN_MDI2- 29
1K_0402_1% 22 6
PCIE_WAKE#_R DVDD10 MDIP2 LAN_MDI1- LAN_MDI2+ 29
21 5
LANWAKEB MDIN1 LAN_MDI1+ LAN_MDI1- 29
ISOLATE# 20 4
LAN_MDI1+ 29
2
RL11 CL11 close to Pin17
15K_0402_5%
@
2
RTL8111GUL-CG_QFN32_4X4
8111GUL@
B B
For RTL8111GUL/ RTL8106EUL (SWR mode)
LAN_XTALI For RTL8111H (LDO mode) RL19 stuf f
YL1 LAN_XTALO 8111H@ +LAN_VDD10
RL19 1 2 0_0805_5%
1 4
OSC1 GND2
2 3 +LAN_REGOUT LL1 1 2
GND1 OSC2 2.2UH_NLC252018T-2R2J-N_5%
1 1 8111GUL@ 1 1 1 1 1 1 1 1
Layout Note: LL1 must be CL15 CL16 CL17 CL18 CL19 CL20 CL22
CL12 25MHZ_10PF_7V25000014 CL13 4.7U_0603_6.3V6K 0.1U_0201_6.3V6-K 0.1U_0201_6.3V6-K 0.1U_0201_6.3V6-K 0.1U_0201_6.3V6-K 0.1U_0201_6.3V6-K CL21 0.1U_0201_6.3V6-K
10P_0402_50V8J 12P_0402_50V8-J within 200mil to Pin24, 1U_0402_6.3V6K @
2 2 CL15,CL16 must be within 2 2 2 2 2 2 2 @ 2
200mil to LL1
+LAN_REGOUT: Width =60mil
Close to Pin3, 8, 22, 30 Close to Pin22(Reserved)
follow G CarrizoL 10pf
A A
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5 4 3 2 1
DL1/DL2
1'S PN:SC300003M00
D TL1 D
24 1 MCT
DL1 MCT1 TCT1
LAN_MDI1+ 1 10 LAN_MDI1+ LAN_MDI3+ 23 2 LAN_MDO3+
LINE1IN LINE1OUT 28 LAN_MDI3+ MX1+ TD1+
LAN_MDI1- 2 9 LAN_MDI1- LAN_MDI3- 22 3 LAN_MDO3-
LINE2IN LINE2OUT 28 LAN_MDI3- MX1- TD1-
1
3 8 21 4 MCT RL17
GND1 GND2 MCT2 TCT2 20_0603_5%
1
LAN_MDI0+ 4 7 LAN_MDI0+ LAN_MDI2+ 20 5 LAN_MDO2+
LINE3IN LINE3OUT 28 LAN_MDI2+ MX2+ TD2+ DL3
1
2
LAN_MDI0- 5 6 LAN_MDI0- LAN_MDI2- 19 6 LAN_MDO2- PDT5061_DO-214AA
LINE4IN LINE4OUT 28 LAN_MDI2- MX2- TD2-
2
11 13 18 7 MCT
GND3 GND5 MCT3 TCT3
2
12 LAN_MDI1+ 17 8 LAN_MDO1+
GND4 28 LAN_MDI1+ MX3+ TD3+ EMC@
AZ3133-08F.R7G_DFN3020P10E10 LAN_MDI1- 16 9 LAN_MDO1-
28 LAN_MDI1- MX3- TD3-
EMC_NS@
15 10 MCT
MCT4 TCT4
1 1
LAN_MDI0+ 14 11 LAN_MDO0+ CL25
28 LAN_MDI0+ MX4+ TD4+ CL32 1000P_1206_2KV7-K
DL2 1 LAN_MDI0- 13 12 LAN_MDO0- 0.022U_0603_50V7K EMC_NS@
C
LAN_MDI2- LAN_MDI2- 28 LAN_MDI0- MX4- TD4- 2 2 C
1 10 CL24
LINE1IN LINE1OUT 0.01U_0201_25V6-K EMC@
LAN_MDI2+ 2 9 LAN_MDI2+ EMC@ BOTH_GST5009 LF
LINE2IN LINE2OUT 2
3 8
GND1 GND2
LAN_MDI3- 4 7 LAN_MDI3-
LINE3IN LINE3OUT
LAN_MDI3+ 5 6 LAN_MDI3+ CHASSIS1_GND
LINE4IN LINE4OUT
11 13
GND3 GND5
12
GND4
AZ3133-08F.R7G_DFN3020P10E10
EMC_NS@
A A
Close to U1 REMOTE2+
REMOTE+_R R176 1 @ 2 0_0402_5% REMOTE2+ REMOTE1+
Near GPU&VRAM 1
Near CPU core
1
REMOTE+_R C46 C
1
1
C45 C 100P_0201_25V8J 2 Q16
1
C44 REMOTE-_R R177 1 @ 2 0_0402_5% REMOTE2- 100P_0201_25V8J 2 Q15 @ B MMBT3904WH_SOT323-3
2200P_0402_25V7-K @ B MMBT3904WH_SOT323-3 2 E @
3
@ 2 E @ REMOTE2-
3
2 REMOTE-_R R178 1 @ 2 0_0402_5% REMOTE1- REMOTE1-
D D
+3VALW
REMOTE+/-_R, REMOTE1+/-, REMOTE2+/-: +3VALW
Trace width/space:10/10 mil Near CPU
Trace length:<8"
1
R17
13.7K_0402_1% R25
SMSC thermal sensor PX@ 13.7K_0402_1%
2
NTC_V1
2
NTC_V2
1
+3VS
1
U1 PH2
1 8 EC_SMB_CK2 100K_0402_1%_NCP15WF104F03RC PH3
VDD SCL EC_SMB_CK2 6,16,36
PX@ 100K_0402_1%_NCP15WF104F03RC
1 REMOTE+_R 2 7 EC_SMB_DA2
EC_SMB_DA2 6,16,36
2
C47 D+ SDA
2
0.1U_0201_6.3V6-K REMOTE-_R 3 6
D- ALERT#
2
@
2
2 R51 2 @ 1 4 5 R184 R185
+3VS T_CRIT# GND
10K_0402_5% @ 0_0402_5% 0_0402_5% R191 R192
NCT7718W_MSOP8 PX@ @ 0_0402_5% 0_0402_5%
Address 1001_101xb @
1
@
1
+5VLP +5VLP EC_AGND
C C
+5VLP EC_AGND
HW thermal sensor
2
1 R252 R253
C4 21.5K_0402_1% 21.5K_0402_1%
0.1U_0201_6.3V6-K @ @
@
1
2 @
U4
1 8 TMSNS1 R196 1 @ 2 0_0402_5% NTC_V1
VCC TMSNS1 NTC_V1 36
2 7 PHYST1 R6 1 @ 2 10K_0402_5%
GND RHYST1
3 6 TMSNS2 R197 1 @ 2 0_0402_5% NTC_V2
46 EC_ON_R OT1 TMSNS2 NTC_V2 36
4 5 PHYST2 R7 1 @ 2 10K_0402_5%
OT2 RHYST2
G718TM1U_SOT23-8 +3VALW
56+/-30C
TPM
+3VS_TPM
FAN Conn UTPM1 TPM@
+5VS 1 24
2 NC_1 VDD3 10
@ JFAN1 3 NC_2 VDD1
R52 1 2 0_0603_5% +5VS_FAN 1 RTPM13 1 @ 2 0_0402_5% 7 NC_3 28 RTPM2 1 TPM@ 2 10K_0402_5%
2 1 PP LPCPD# 27 SERIRQ_TPM RTPM5 1 TPM@ 2 0_0402_5%
36 EC_FAN_SPEED 2 SERIRQ SERIRQ 8,36
3 6 26 LPC_AD0_TPM RTPM6 1 TPM@ 2 0_0402_5%
3 NC_4 LAD0 LPC_AD1_TPM LPC_AD0 8,36
1 1 36 EC_FAN_ANTI 4 9 23 RTPM7 1 TPM@ 2 0_0402_5%
4 NC_7 LAD1 LPC_FRAME#_TPM LPC_AD1 8,36
C49 C50 36 EC_FAN_PWM 5 22 RTPM8 1 TPM@ 2 0_0402_5%
5 LFRAME# LPC_AD2_TPM LPC_FRAME# 8,11,36
10U_0805_10V6K 0.1U_0201_6.3V6-K 6 4 20 RTPM9 1 TPM@ 2 0_0402_5%
GND1 GND_1 LAD2 LPC_AD3_TPM LPC_AD2 8,36
@ 7 11 17 RTPM10 1 TPM@ 2 0_0402_5%
2 2 GND2 GND_2 LAD3 LPC_AD3 8,36
18
ACES_50273-0050N-001 GND_3 25 +3VS_TPM
ME@ RTPM14 1 @ 2 0_0603_5% 5 GND_4 21
+3VALW NC_5 LCLK TPM_CLK 8
8 19
RTPM15 1 @ 2 0_0603_5% 12 NC_6 VDD2 15 RTPM11 1 TPM@ 2 0_0402_5%
+3VS NC_8 CLK_RUN#
13 RTPM16 1 TPM@ 2 0_0402_5% LPC_CLKRUN# 8
14 NC_9 16
NC_10 LRESET# APU_LPC_RST# 7,36
A A
Z32H320TC_TSSOP28
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DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
3 2
Custom
Mini-Express Card(WLAN/WiMAX)
+3VS_WLAN
JWLAN1
1 1
1 2
3 GND1 3.3VAUX1 4
8 USB20_P2 USB_D+ 3.3VAUX2
5 6 1 @ T2
8 USB20_N2 USB_D- LED#1
7 8
9 GND2 PCM_CLK 10
11 SDIO_CLK PCM_SYNC 12
13 SDIO_CMD PCM_IN 14
15 SDIO_DAT0 PCM_OUT 16 1 @ T3
17 SDIO_DAT1 LED#2 18
19 SDIO_DAT2 GND11 20
21 SDIO_DAT3 UART_WAKE 22
23 SDIO_WAKE UART_RX
SDIO_RESET
KEY E
25 PIN24~PIN31 NC PIN 24
27 26
29 28
31 30
33 32
35 GND3 UART_TX 34
4 PCIE_PTX_C_DRX_P1 PETP0 UART_CTS
37 36
4 PCIE_PTX_C_DRX_N1 PETN0 UART_RTS
39 38
41 GND4 RSRVD10 40
4 PCIE_PRX_DTX_P1 PERP0 RSRVD11
43 42
4 PCIE_PRX_DTX_N1 PERN0 RSRVD9
45 44 R88 1 2 0_0402_5%
GND5 COEX3 EC_RX 36
47 46 @
8 CLK_PCIE_WLAN REFCLKP0 COEX2
49 48
8 CLK_PCIE_WLAN# REFCLKN0 COEX1 SUSCLK_R
2 51 50 R55 1 2 0_0402_5% 2
WLAN_CLKREQ# GND6 SUSCLK PLT_RST# SUSCLK 7,11
7 WLAN_CLKREQ# 53 52 @
CLKEQ0# PERSTO# BT_OFF# PLT_RST# 7,15,28
55 54 R53 1 2 1K_0402_5%
7,28,36 PCIE_WAKE# PEWAKE0# RSRVD/W_DISABLE#2 WLAN_OFF# PCH_BT_OFF# 7
57 56 R56 1 2 0_0402_5%
GND7 W_DISABLE#1 PCH_WLAN_OFF# 7
R57 1 @ 2 0_0402_5% @
28,36 LAN_WAKE#
59 58 APU_SMB_DATA_R R58 1 @ 2 0_0402_5%
RSRVD/PETP1 I2C_DATA APU_SMB_CLK_R R59 APU_SMB_DATA 7,12
61 60 1 @ 2 0_0402_5%
RSRVD/PETN1 I2C_CLK APU_SMB_CLK 7,12
63 62
65 GND8 ALERT 64 EC_TX_R R89 1 2 0_0402_5%
RSRVD/PERP1 RSRVD6 EC_TX 36
67 66 @
69 RERVD/PERN1 RSRVD7 68 +3VS_WLAN
GND9 RSRVD8
1
71 70
73 RSRVD1 RSRVD12 72 R186
75 RSRVD2 3.3VAUX3 74 100K_0402_5%
GND10 3.3VAUX4
77 76
2
GND15 GND14
LCN_DAN05-67406-0102
ME@
3 3
+3VS_WLAN
+3VS Need short
J2 @
1 2 1
1 2 C53
JUMP_43X79 0.1U_0201_6.3V6-K
@
2
4 4
1
1 USB20_P5_R 1
D11 USB20_N5_R
1
+5VALW +USB_VCCA EMC_NS@
U22 AZ5725-01F_DFN1006P2X2
5 1
IN OUT
2
1
2
C201 2 D12 EMC_NS@ D13
GND USB30_RX_R_N1 9 10
1U_0402_6.3V6K 1 1USB30_RX_R_N1 AZC199-02S.R7G_SOT23-3
2
4 3 USB_OC1# EMC_NS@
2 36,37 USB_ON# ENB OCB USB_OC1# 7 USB30_RX_R_P1 8 9 2 2 USB30_RX_R_P1
SY6288D20AAC_SOT23-5 1
C202 USB30_TX_R_N1 7 7 4 4 USB30_TX_R_N1
1000P_0201_50V7-K
Low Active 2.5A @ USB30_TX_R_P1 6 6 5 5 USB30_TX_R_P1
2
3 3
1
8
AZ1045-04F_DFN2510P10E-10-9
2 EMC 2
+
220U_6.3V_M
USB30_RX_N1 4 3 USB30_RX_R_N1
4 3 C1319 1 2
EXC24CH900U_4P @ 47U_0805_6.3V6-M
C83 1 2
L16 EMC@ @ 1U_0402_6.3V6K
USB30_TX_C_P1 1 2 USB30_TX_R_P1
1 2 C88 1 2
@ 1U_0402_6.3V6K
USB30_TX_C_N1 4 3 USB30_TX_R_N1
4 3 JUSB1 ME@
EXC24CH900U_4P USB30_TX_P1 C84 1 2 0.1U_0201_6.3V6-K USB30_TX_C_P1 R95 1 @ 2 0_0402_5% USB30_TX_R_P1 9
8 USB30_TX_P1 StdA_SSTX+
1
3 L8 EMC@ USB30_TX_N1 C89 1 2 0.1U_0201_6.3V6-K USB30_TX_C_N1 R96 1 @ 2 0_0402_5% USB30_TX_R_N1 8 VBUS 3
USB20_P5 USB20_P5_R 8 USB30_TX_N1 USB20_P5 USB20_P5_R StdA_SSTX-
1 2 R97 1 @ 2 0_0402_5% 3
1 2 8 USB20_P5 D+
7
USB20_N5 R93 1 @ 2 0_0402_5% USB20_N5_R 2 GND_DRAIN 10
USB20_N5 USB20_N5_R 8 USB20_N5 USB30_RX_P1 USB30_RX_R_P1 D- GND_1
4 3 R94 1 @ 2 0_0402_5% 6 11
4 3 8 USB30_RX_P1 StdA_SSRX+ GND_2
4 12
EXC24CH900U_4P USB30_RX_N1 R92 1 @ 2 0_0402_5% USB30_RX_R_N1 5 GND_5 GND_3 13
8 USB30_RX_N1 StdA_SSRX- GND_4
EMC
SUYIN_020053GR009M2736L
4 4
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5 4 3 2 1
UW1
+3VALW +3VS
D RW2 1 2 6.2K_0402_1% RREF 1 24 VDD18 1U_0402_6.3V6K 2 1 CW1 D
USB20_N4 RW9 1 @ 2 0_0402_5% USB20_N4_R 2 RREF V18 23
8 USB20_N4 USB20_P4 USB20_P4_R DM XD_D7
RW10 1 @ 2 0_0402_5% 3 22
8 USB20_P4 +3V3_CARD DP SP14 SD_D2_R
RW11 1 @ 2 0_0603_5% 4 21
RW12 1 2 0_0603_5% CARD_3V3 5 3V3_IN SP13 20 SD_D3_R
SDREG 6 CARD_3V3 SP12 19
7 SDREG SP11 18 SD_CMD_R
1 1 XD_CD# SP10
SD_WP
1U_0402_6.3V6K
CW2 CW3 8 17
4.7U_0402_6.3V6M 0.1U_0201_6.3V6-K 9 SP1 GPIO0 16
1 SP2 SP9
CW4 SD_D1_R 10 15 SD_CLK_R
2 2 SD_D0_R 11 SP3 SP8 14
LW1 12 SP4 SP7 13 SD_CD#
USB20_N4 1 2 USB20_N4_R 2 SP5 SP6
1 2 25
GND
USB20_P4 4 3 USB20_P4_R
4 3 RTS5170-GRT_QFN24_4X4
EXC24CH900U_4P
EMC_NS@
FOR EMI
C C
CARD_3V3
FOR EMI
JREAD1
4
VDD
FOR ESD Close to Connector
4.7U_0402_6.3V6M
0.1U_0201_6.3V6-K
SD_D0_R RW3 1 @ 2 0_0402_5% SD_D0
CW5 1 2 22P_0201_25V8 1 1 SD_D0 7
EMC_NS@ SD_CD# SD_WP CW9 CW10 SD_D1 8 DAT0
AZ5123-01F.R7GR_DFN1006P2X2
AZ5123-01F.R7GR_DFN1006P2X2
AZ5123-01F.R7GR_DFN1006P2X2
SD_D1_R RW4 1 @ 2 0_0402_5% SD_D1 CARD_3V3 SD_D2 9 DAT1
CW6 1 2 22P_0201_25V8 SD_D3 1 DAT2
EMC_NS@ DW3 DW2 DW1 2 2 CD/DAT3
1
SD_D2_R RW5 1 @ 2 0_0402_5% SD_D2 SD_CD# 11
CW7 1 2 22P_0201_25V8 SD_WP 10 C/D
1
EMC_NS@ W/P
SD_D3_R RW6 1 @ 2 0_0402_5% SD_D3 Close to Connector SD_CMD
SD_CLK
2
CMD
CW8 1 2 22P_0201_25V8 5
EMC_NS@ CLK
2
SD_CMD_R RW7 1 2 15_0402_5% SD_CMD 3 12
CW11 1 2 5.6P_0402_50V8-D 6 VSS1 GND_1 13
2
B EMC@ EMC_NS@ EMC_NS@ EMC_NS@ VSS2 GND_2 B
SD_CLK_R RW8 1 2 15_0402_5% SD_CLK DEREN_404232501111RHF_NR
CW12 1 2 5.6P_0402_50V8-D ME@
EMC@
+3V3_CARD
U23
RW13 1 @ 2 0_0603_5% 5 1
RW14 1 @ 2 0_0603_5% IN OUT
2
RE96 1 @ 2 10K_0402_5% GND
RE94 1 @ 2 0_0402_5% 4 3
36 Card_PWREN EN OCB
RE95 1 @ 2 0_0402_5%
36,38,47 SUSP#
@
1 SY6288C20AAC_SOT23-5
A CW13 A
4.7U_0402_6.3V6M
@
2 Security Classification LC Future Center Secret Data Title
Issued Date 2014/12/11 Deciphered Date 2015/12/11 Cardreader
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG516
Date: Tuesday, April 12, 2016 Sheet 33 of 51
5 4 3 2 1
A B C D E F G H
10
SATA ODD Conn.
SATA_PTX_DRX_P0 C66 1 2 0.01U_0201_10V6K SATA_PTX_C_DRX_P0 9 10
8 SATA_PTX_DRX_P0 9
SATA_PTX_DRX_N0 C67 1 2 0.01U_0201_10V6K SATA_PTX_C_DRX_N0 8
8 SATA_PTX_DRX_N0 8
7 12
1 SATA_PRX_DTX_N0 C68 1 2 0.01U_0201_10V6K SATA_PRX_C_DTX_N0 6 7 GND2 1
8 SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 C69 1 2 0.01U_0201_10V6K SATA_PRX_C_DTX_P0 5 6 JODD1
8 SATA_PRX_DTX_P0 4 5 1
3 4 11 SATA_PTX_DRX_P1 14@ C70 1 2 0.01U_0201_10V6K SATA_PTX_C_DRX_P1_14 2 GND_1
3 GND1 8 SATA_PTX_DRX_P1 RX+
2 SATA_PTX_DRX_N1 14@ C71 1 2 0.01U_0201_10V6K SATA_PTX_C_DRX_N1_14 3
2 8 SATA_PTX_DRX_N1 RX-
1 4
1 SATA_PRX_DTX_N1 14@ C72 1 2 0.01U_0201_10V6K SATA_PRX_C_DTX_N1_14 5 GND_2
ELCO_006809610010846 8 SATA_PRX_DTX_N1 SATA_PRX_DTX_P1 14@ C73 1 2 0.01U_0201_10V6K SATA_PRX_C_DTX_P1_14 6 TX-
8 SATA_PRX_DTX_P1 7 TX+
Need short +5VS_HDD
ME@ GND_3
J3 @ 8
1 2 9 DP
+5VS 1 2 +5V_ODD +5V_1
10
JUMP_43X79 11 +5V_2 14
12 MD GND1 15
13 GND_4 GND2
GND_5
+5VS_HDD SUYIN_127382FB013S255ZL
ME@
1 1 1 1 1
C74 C75 C76 C77 C78
1000P_0201_50V7-K 0.1u_0201_10V6K 47P_0402_50V8J 10U_0805_10V6K 47P_0402_50V8J
EMC_NS@ RF@ RF@
2 2 2 2 2
FOR 15"
2 EMC 2
SATA ODD FFC Conn
J4 @
1 2
3 1 2 3
JUMP_43X79
1 1 1
ODD DA???
C85 C86 C1324
10U_0805_10V6K 0.1u_0201_10V6K 47P_0402_50V8J
RF@
2 2 2
4 4
WWW.AliSaler.Com
5 4 3 2 1
+3VS AVDD_HP
0.1U_0201_6.3V6-K
0.1U_0201_6.3V6-K
+5VA
@ +3VS
RA2 1 2 0_0603_5% +3.3VD 1 1
RA3 1 @ 2 0_0603_5%
+VAUDIO +3VALW
CA11
CA12
RA8 1 2 0_0402_5% DVDD_IO RA5 1 @ 2 0_0603_5% AVDD_HP 2 2
+5VS +3VL
0.1U_0201_6.3V6-K
@
@ 1 @
RA7 1 2 0_0603_5% +5VA CA1 RA25 1 2 0_0603_5%
D @
2
Close to Pin28 Close to Pin24 D
RA10 1 2 0_0603_5% +5VD
+1.5VS +VAUDIO Close to Pin3
RA11 1 @ 2 0_0402_5%
Close to Pin7
DA1
2 +1.8VS
36 BEEP#
CA16 close to Pin18
4.7U_0402_6.3V6M
0.1U_0201_6.3V6-K
1 PC_BEEP1 CA2 1 2 PC_BEEP RA30 1 2 0_0402_5% 1 1 CA17 close to Pin2
Close to Pin27
1
7 PCH_BEEP 3 0.1U_0201_6.3V6-K
0.1U_0201_6.3V6-K
RA14
2 2
CA3
CA4
1U_0402_6.3V6K
BAT54CW_SOT323-3 10K_0402_5%
2.2U_0402_6.3V6M
0.1U_0201_6.3V6-K
2
UA1 2 1
CA7
CA8
1 1
HDA_RST_AUDIO# 9 3 FILT_1.8V
7 HDA_RST_AUDIO# RESET# FILT_1.8V DVDD_IO 1 2
CA5
CA6
7
VDD_IO 2
HDA_BITCLK_AUDIO 5 VDDO_3.3 18 +3.3VD 2 2
7 HDA_BITCLK_AUDIO BIT_CLK DVDD_3.3
HDA_SYNC_AUDIO 8 27 AVDD_3.3
7 HDA_SYNC_AUDIO RA16 SYNC AVDD_3.3 29 VREF_1.65V
33_0402_5% 1 2 SDATA_IN 6 VREF_1.65V 28 +5VA
7 HDA_SDIN0 HDA_SDOUT_AUDIO SDATA_IN AVDD_5V
1U_0402_6.3V6K
0.1U_0201_6.3V6-K
4
LINE_B_R
LINE_B_L
7 HDA_SDOUT_AUDIO SDATA_OUT
CA10
MICBIASB
+3.3VD
1 1
PC_BEEP 10
PC_BEEP CX11802 LEFT+
12 SPK_L+
LBAT54AWT1G SOT323
SPKR_MUTE# SPK_L-
CA9
39 14
SPKR_MUTE# LEFT-
2
JSENSE 38 17 SPK_R+ DA2 2 2
JSENSE RIGHT+
2
4
3
37 15 SPK_R- RA42 RA41
C RA15 GPIO1/PORTC_R_MIC RIGHT- RPA2 C
0_0402_5% 0_0402_5%
5.11K_0402_1% 36 35 @ 100_0404_4P2R_1%
MUSIC_REQ/GPIO0/PORTC_L_MIC MICBIASC
23 DMIC_CLK
33_0402_5% 1 RA18 2 DMIC_CLK_R 40 34 MICBIASB @ @ Close to Pin29
1
0_0402_5%1 2 DMIC_DATA_R 1 DMIC_CLK/MUSIC_REQ/GPIO0 MICBIASB
23 DMIC_DATA
1
1
2
RA19 @ DMIC_DAT/GPIO1 33 LINE_B_R
PLUG_IN RA17 1 2 JSENSE 0.1u_0201_10V6K PORTB_R_LINE 32 LINE_B_L
+5VD 1 2 11 PORTB_L_LINE
CLASS-D_REF 1 1
39.2K_0402_1% CA13 30 PORTD_A_MIC
PORTD_A_MIC
1
RA36 1 2 13 31 PORTD_B_MIC CA35 CA36
20K_0402_1% 16 LPWR_5.0 PORTD_B_MIC RA37 RA38 4.7U_0603_10V6-K 4.7U_0603_10V6-K
RPWR_5.0 25 RING2_CONN 3K_0402_1% 3K_0402_1% 2 2
CA14 1 2 1U_0402_6.3V6K 19 HGNDA 26 RING3_CONN
20 FLY_P HGNDB
2
FLY_N 24 AVDD_HP
CA17 1 2 2.2U_0402_6.3V6M 21 AVDD_HP
RPA3
AVEE 23 HPOUT_R 1 4 HP_OUTR
41 PORTA_R 22 HPOUT_L 2 3 HP_OUTL
GND PORTA_L
82.5_0404_4P2R_1%
+5VD RPA1
CX11802-33Z_QFN40_5X5 PORTD_A_MIC 2 3 CA20 1 2 2.2U_0402_6.3V6M RING3_CONN
PORTD_B_MIC 1 4 CA21 1 2 2.2U_0402_6.3V6M RING2_CONN
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
0.1U_0201_6.3V6-K
0.1U_0201_6.3V6-K
1 1 1 1 100_0404_4P2R_1% JHP1
RING2_CONN
CA15
CA16
RA1 1 @ 2 0_0402_5% 3
G/M
CA18
CA19
2 2 2 2 0_0402_5% @
RA6 1 @ 2 0_0402_5% 470P_0201_50V7-K PLUG_IN 5
6 5
RA9 1 @ 2 0_0402_5% 6
RA24 1 @ 2 R912 1 2 @ 1 2 CA42 HP_OUTR 2
1
100P_0201_25V8J
100P_0201_25V8J
DA3 1 2 @ 7
2
MS
1 1
SPKR_MUTE#
GND GNDA SINGA_2SJ3095-091111F
RB751V-40_SOD323-2 ME@
36 EC_MUTE#
EC_MUTE# DA4 1 2 @ Use 250mils wide trace bridging 2 2
CA44
CA45
AGND and DGND at codec
1 2
RA35 @
0_0402_5% RING3_CONN
JSPK1 RING2_CONN
15_0402_5% 1 2
EMC_NS@ RA26SPK_R+ LA1 1 2 EMC@ PBY160808T-221Y-N_2PSPK_R+_CONN 1 HP_OUTL
15_0402_5% 1 2
EMC_NS@ RA29SPK_R- LA2 1 2 EMC@ PBY160808T-221Y-N_2PSPK_R-_CONN 2 1 HP_OUTR
15_0402_5% 1 2
EMC_NS@ RA32SPK_L+ LA3 1 2 EMC@ PBY160808T-221Y-N_2PSPK_L+_CONN 3 2 PLUG_IN
HDA_RST_AUDIO# DMIC_CLK_R 15_0402_5% 1 2
EMC_NS@ RA33SPK_L- LA4 1 2 EMC@ PBY160808T-221Y-N_2PSPK_L-_CONN 4 3
4
EMC_NS@
EMC_NS@
EMC_NS@
EMC_NS@
AZ5725-01F_DFN1006P2X2
AZ5725-01F_DFN1006P2X2
AZ5725-01F_DFN1006P2X2
AZ5725-01F_DFN1006P2X2
DA5 DA6 DA7 DA8 DA9
AZ5123-01F.R7GR_DFN1006P2X2
220P_0201_25V7-K
220P_0201_25V7-K
220P_0201_25V7-K
220P_0201_25V7-K
HDA_SYNC_AUDIO
100P_0201_25V8J
5
GND1
1
470P_0201_50V7-K
470P_0201_50V7-K
470P_0201_50V7-K
470P_0201_50V7-K
EMC@
EMC@
EMC@
EMC@
EMC@
1 2 2 2 2 6
HDA_SDOUT_AUDIO GND2
1
1
1 1 1 1 ACES_88231-04001 CA43
RA27 1 2 EMC_NS@HDA_BITCLK_AUDIO ME@ 1000P_0402_50V7K
2 1 1 1 1
C15
27_0402_5% EMC_NS@
HDA_SDIN0 2
CA27
CA28
CA29
CA30
2 2 2 2
2
CA31
CA32
CA33
CA34
EMC_NS@
EMC_NS@
EMC_NS@
EMC_NS@
2
22P_0201_25V8
22P_0201_25V8
EMC@
DMIC_DATA_R
68P_0402_50V8J
33P_0402_50V8J
33P_0402_50V8J
A A
1 1 1 1 1
100P_0201_25V8J
1
2 2 2 2 2
CA25
CA26
EMC
CA22
CA23
CA24
2
C56
2
@
RE83 1 2 0_0603_5% RE52 RE51
+3VL_EC
Config LPC 3.3V S0 power 1 1
0_0402_5%
@
0_0402_5%
@
CE21 CE5
set register GCR23 0 Bit to 1b Config SERIRQ 3.3V S0 power All capacitors close to EC
1
+3VL_EC 0.1U_0201_6.3V6-K 1000P_0201_50V7-K
RE4 1 2 0_0402_5% @
0.1U_0201_6.3V6-K
0.1U_0201_6.3V6-K
0.1U_0201_6.3V6-K
0.1U_0201_6.3V6-K
0.1U_0201_6.3V6-K
0.1U_0201_6.3V6-K
+3VS 2 EC_AGND 2
@ RE84 1 2 0_0603_5% RPE4
+3VL_EC_R TP_DATA 1 4
1 1 1 1 1 1
CE6 CE7 CE8 CE9 CE10 CE11 TP_CLK 2 3
+3VL RE58 1 2 0_0402_5% @ EC_AGND
@ 4.7K_0404_4P2R_5%
2 2 2 2 2 2 +3VS
D CE3 EC_FAN_SPEED D
RE10 1 2 10K_0402_5%
IT8886H need VHSPI ready before VCC, 1 2 VCOREVCC EC_FAN_PWM RE11 1 @ 2 10K_0402_5%
at least 2ms mismatch. ENBKL
EC_GFX_PWRGD
RE9
RE12
1
1
@
ST@
2
2
100K_0402_5%
10K_0402_5%
0.1U_0201_6.3V6-K minimum trace width 12 mil
114
121
127
106
SERIRQ RE81 1 @ 2 10K_0402_5%
12
11
26
50
92
74
UE1
Close EC HSPI (supplied by VHSPI if IT8886HE): CPU to EC 1.8VS
VCORE
VCC
VSTBY1
VSTBY2
VSTBY3
VSTBY4
VSTBY5
AVCC
VSTBY(PLL)
VFHSPI/VFSPI/VHSPI
+5VALW
FSPI (supplied by VSTBY if IT8886HE): EC to SPI Rom 3.3VALW/VL?
USB_ON# RE15 1 2 10K_0402_5%
37 KSI[0..7]
KSI[0..7] LQFP-128L ADC5/DCD1#/GPI5
ADC6/DSR1#/GPI6
72
73
EC_GFX_ON_RE ADP_I 45
RE23 1 BR@
RE71 1
2 1K_0402_5%
2 0_0402_5%
EC_GFX_ON 512_5VEN
KSO[0..17] KSI0 58 ADC7/CTS1#/GPI7
37 KSO[0..17]
KSI1 59 KSI0/STB# 78 change reserved EC_RTCRST#_ON for GPU HOT
+3VL_EC +3VS KSI1/AFD# DAC2/TACH0B/GPJ2 EC_GFX_PWRGD VR_APU_PWRGD 50 VR_GFX_PWRGD
KSI2 60 79 RE28 1 BR@ 2 0_0402_5%
KSI3 61 KSI2/INIT# DAC3/TACH1B/GPJ3 80 EC_APU_ALWEN RE89 1 PX@ 2 0_0402_5%
KSI3/SLIN# DAC DAC4/DCD0#/GPJ4 EC_APU_ALWEN 47 GPU_VR_HOT# 16,49
KSI4 62 81
KSI4 DAC5/RIG0#/GPJ5 EC_SYS_PWRGD 7 GPU_EC_HOT#
KSI5 63 RE91 1 PX@ 2 0_0402_5%
KSI5
1
C KSI6 64 85 QE6 D C
KSI6 PS2CLK0/TMB0/CEC/GPF0 EC_RTCRST#_ON 9 1
2
1
KSI7 65 86 2 CE23
KSI7 PS2DAT0/TMB1/GPF1 PBTN_OUT# 7
2
1
3
KSO3 39 KSO2/PD2
@
3
4
EC_SMB_CK1 EC_SMB_DA2 KSO5 41 KSO4/PD4 HSCE#/GPH3/ID3 97 GPG1 def mode GPO L internal Pull down
EC_SMB_DA1 KSO6 42 KSO5/PD5 HSCK/GPH4/ID4 98
KSO6/PD6 EXTERNAL SERIAL FLASH HMISO/GPH5/ID5
KSO7 43 99 H_PROCHOT#_EC RE82 1 @ 2 0_0402_5%
KSO7/PD7 FDIO3/DSR0#/GPG6
AMD request SIC/SID( EC_SMB2 ) pul l hig h 1K KSO8
KSO9
44
45 KSO8/ACK# 101
KSO10 46 KSO9/BUSY FSCE# 102 RE34 1 @ 2 0_0402_5%
KSO10/PE FMOSI 45,47,50,51 VR_HOT# H_PROCHOT# 6
KSO11 51 SPI Flash ROM 103
KSO12 52 KSO11/ERR# FMISO 105
KSO12/SLCT FSCK H_PROCHOT#
1
SMBus0:PMIC KSO13 53 QE1 D
KSO13 1
+3VL_EC +3VALW SMBus1:Charger/Battery KSO14 54 FSPI,GPG6 can't pull up H_PROCHOT#_EC 2 CE14
KSO15 55 KSO14 G 47P_0201_25V8-J
SMBus2:APU/GPU/thermal sensor KSO15 EC_TX
KSO16 56 17 @
KSO16/SMOSI/GPC3 TXD/SOUT0/LPCPD#/GPE6 EC_TX 31
2
3
RE74 RE73 KSO17/SMISO/GPC5 RXD/SIN0/PWUREQ#/BBO/SMCLK2ALT/GPC7
0_0402_5% 0_0402_5% GPG0 def mode GPO H
@ @ EC_SMB_CK1 115 82 GPG1 def mode GPO L internal Pull down
44,45 EC_SMB_CK1 EC_SMB_DA1 SMCLK1/GPC1 EGAD/GPE1 PCH_CMOSP 23,38
116 83
44,45 EC_SMB_DA1 EC_MUTE# 35
1
95 GPIO
RPE5 94 HDIO3/GPJ1 VDDGFX_PD=1 -> VDDCR_GFX VRM turned OFF
TACH2/HDIO2/GPJ0
1
2.2K_0404_4P2R_5% BKOFF# 113 107 QE5 D
23 BKOFF# CRX0/GPC0 GPE4/BTN# NOVO# 37
+3VL SYSON RE85 2 1 0_0402_5% 123 119 PAD 1 @ VDDGFX_PD RE16 1 @ 2 10K_0402_5% VDDGFX_PD_R 2
CTX0/TMA0/GPB2 CRX1/SIN1/SMCLK3/GPH1/ID1 IT10 G
3
4
EC_SMB_CK0 RE27 1 @ 2 0_0402_5% 112 EC set GPH0 OD output for EC_RSMRST# is 1.8V level
EC_SMB_DA0 100 VSTBY0 @ S 2N7002KW_SOT323-3
1224 change GPH0 to push pull output 1
3
FDIO2/DTR1#/SBUSY/GPG1/ID7
1
VGA_AC_DET 125 76 EC_RSMRST#
16 VGA_AC_DET SSCE1#/GPG0 CLKRUN#/GPH0/ID0 EC_ON EC_RSMRST# 7
122 WAKE UP 48 RE7 CE15
33 Card_PWREN PM_SLP_S5# 21 CTX1/SOUT1/SMDAT3/GPH2/ID2 TACH1A/TMA1/GPD7 47 EC_FAN_SPEED EC_ON 46,47
7 PM_SLP_S5# EC_FAN_SPEED 30 100K_0402_5% 1000P_0201_50V7-K
PM_SLP_S3# 18 RI2#/GPD1 TACH0A/GPD6 19 @ 2
7 PM_SLP_S3# RI1#/GPD0 L80HLAT/BAO/GPE0 CAPS_LED# 37 @
20
NUM_LED# 37
2
B USB_ON# 33 L80LLAT/GPE7 108 ACIN# B
32,37 USB_ON# GINT/CTS0#/GPD5 AC_IN#/GPB0 LID_SW#
35 109
28 LAN_PWR_ON# RTS1#/GPE5 LID_SW#/GPB1 LID_SW# 37 EC_ON
RE93 1 @ 2 1K_0402_5% 93 111 RE67 2 @ 1 0_0402_5%
will cost down in future if EC internal logic verify ok
7 ECBTN HMOSI/GPH6/ID6 XLP_OUT/GPB4
2 QE3B
7,28,31 PCIE_WAKE# GPJ7 GPIO XLP_OUT can't be set normal GPIO Pin
EC_VR_ON 3 2N7002KDWH_SOT363-6
50 EC_VR_ON GPH7 EC_GFX_PWRGD
128 3 4
D
7 AC_PRESENT GPJ6 VR_GFX_PWRGD 7,51
S
AVSS
VSS1
VSS2
VSS3
VSS4
VSS5
+3VL @
GPG0 ( VGA_AC_DET )can't pull up
IT8886HE-AX_LQFP128_14X14 +3VS
1
27
49
91
75
104
G
5
1
RE13 1 @ 2 10K_0402_5%
RE56
100K_0402_5%
6
APUALW_PWRGD D 1
EC_AGND VDDGFX_PD 2 QE3A C48
change reserved APUTYPE for GPU HOT
2
@ ACIN# 2 RE88 1 G 2N7002KDWH_SOT363-6 0.1U_0201_6.3V6-K
DE2 1 2 RB751V-40_SOD323-2 1 @ @
RE90 1 @ 2 0_0402_5% GPU_EC_HOT# CE22 0_0402_5% S 2
1
1
0.1U_0402_25V6 D QE2 @
SYSON RE86 2 1 0_0402_5% @ 2
+3VL_EC 1_2VEN 47 2 G ACIN 45
2N7002KW_SOT323-3 S @
3
APUTYPE RE70 2 BR@ 1 10K_0402_5% @
RE69 2 ST@ 1 10K_0402_5% DE3 1 2 RB751V-40_SOD323-2
when mirror, GPG2 pull high
when no mirror, GPG2 pull low Reserve Factory EC flash, need confirm with ITE EMC
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AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG516
Date: Tuesday, April 12, 2016 Sheet 36 of 51
5 4 3 2 1
5 4 3 2 1
ON/OFFBTN#
1
+3VL +3VALW KSI[0..7]
KSI[0..7] 36
SW2
1
@ D31 KSO[0..17]
KSO[0..17] 36
1
R923 1 2 0_0402_5% AZ5123-01F.R7GR_DFN1006P2X2
R82 R83 EVQP7L01K SPST EMC@ K/B Connector
1
100K_0402_5% 100K_0402_5% D33
2
@ AZ5123-01F.R7GR_DFN1006P2X2
4
EMC_NS@ JKB1 EMC_NS@
2
D15 PWR_CAPS_LED C133 1 2 100P_0201_25V8J
KB_P32
2
NOVO# 2 R937 1 @ 2 0_0402_5% 32 33
36 NOVO# PWR_NUM_LED 1 2 100P_0201_25V8J KB_P31 32 GND1
C134 ON/OFFBTN# R938 1 @ 2 0_0402_5% 31 34
2
1 NOVO_BTN# R930 1 2 0_0402_5% NUM_LED#_R 30 31 GND2
36 NUM_LED# 15@
PWR_NUM_LED 30
@ EMC_NS@ +3VS R928 1 15@ 2 29
ON/OFF R85 1 2 0_0402_5% 3 300_0402_5% KSO17 R931 1 2 0_0402_5% KSO17_R 28 29
15@
KSO16 R932 1 2 0_0402_5% KSO16_R 27 28
D 15@ D
BAT54CW_SOT323-3 KSI1 26 27
KSI7 25 26
@ 25
KSI6 24
ON/OFFBTN# KSO12 R291 1 14@ 2 0_0402_5% KB_P32 KSO9 23 24
+3VALW +3VL EMC_NS@ KSI4 22 23
22
place near KB Conn
3
CAPS_LED# C117 1 2 100P_0201_25V8J KSO14 R292 1 15@ 2 0_0402_5% KSI5 21
21
1
KSO0 20
20
2
NUM_LED#_R C118 1 2 100P_0201_25V8J KSI2 19
1
R111 R114 SW1 D30 KSI3 18 19
100K_0402_5% 100K_0402_5% SKRBAAE010_4P AZ5123-01F.R7GR_DFN1006P2X2 EMC_NS@ KSO5 17 18
@ 14@ EMC_14@ KSI2 R289 1 14@ 2 0_0402_5% KB_P31 KSO1 16 17
KSI0 15 16
1
15
2
@ KSI5 R290 1 15@ 2 0_0402_5% KSO2 14
4
ON/OFFBTN# R119 1 2 0_0402_5% ON/OFF KSO4 13 14
ON/OFF 36
2
+3VS KSO7 12 13
KSO8 11 12
J5 1 2 @ CAPS_LED# NUM_LED#_R KSO6 10 11
KSO3 9 10
9
1
SHORT PADS KSO12 8
ON/OFFBTN# R929 KSO13 7 8
7
1
300_0402_5% KSO14 6
place bottom side 6
3
KSO11 5
1
5
1
D23 D22 KSO10 4
2
AZ5123-01F.R7GR_DFN1006P2X2 AZ5123-01F.R7GR_DFN1006P2X2 KSO15 3 4
1
SW3 D32 EMC@ EMC_15@ CAPS_LED# 2 3
36 CAPS_LED# PWR_CAPS_LED 2
SKRBAAE010_4P AZ5123-01F.R7GR_DFN1006P2X2 1
1
2
15@ EMC_15@
CVILU_CF32321D0RONH
2
2
ME@
2
For EMC
12
11 12 14
USB20_P1 R913 1 @ 2 0_0402_5% USB20_P_CONN 10 11 GND2
USB20_P6 R920 1 @ 2 0_0402_5% 9 10 13
USB20_N0_R 8 9 GND1
USB20_P0_R 7 8
6 7
L20 EMC@ USB20_P_CONN 5 6
+5VS TP_PWR TP_CLK USB20_P1 1 2 USB20_P_CONN USB20_N_CONN 4 5
R160 1 @ 2
TP/B Connector TP_DATA 8 USB20_P1 1 2
PWR_LED#
3
2
4
3
36 PWR_LED# 2
2
+3VS 0_0402_5% USB20_N1 4 3 USB20_N_CONN 1
8 USB20_N1 4 3 +5VALW 1
JTP1 DT1
1
R141
2
TP_CLK
1
2 1
Right Side USB2.0 Port X 2 (USB/B) EXC24CH900U_4P ACES_50506-01201-AT1
EMC_NS@
ME@
0.1U_0201_6.3V6-K
36 TP_CLK TP_DATA 2
0_0402_5% 3
36 TP_DATA 3 +5VALW +USB_VCCB
@ 4 L18 EMC_NS@
100P_0201_25V8J
100P_0201_25V8J
1 4 USB20_N6 1 2 USB20_N_CONN
EMC_NS@
EMC_NS@
C114 1 1 U19
8 USB20_N6 1 2
5 5 1
2
6 GND1
GND2 1
C193
IN OUT
2 USB20_P6 4 3 USB20_P_CONN
USB I/O Connector for G, USB2.0*2
2 2 1U_0402_6.3V6K GND 8 USB20_P6 4 3
C115
C116
HIGHS_FC1AF040-1201H
ME@ AZC199-02S.R7G_SOT23-3 4 3 USB_OC2# EXC24CH900U_4P
32,36 USB_ON#
1
2 ENB OCB USB_OC2# 7 JUSB4
EMC SY6288D20AAC_SOT23-5 1 22
C194 21 GND2
EMC GND1
1000P_0201_50V7-K L14 EMC_NS@ R915 1 @ 2 0_0402_5% USB30_RX_R_P2 20
USB30_RX_P2 USB30_RX_R_P2 8 USB30_RX_P2 20
Low Active 2A @ 1 2 R916 1 @ 2 0_0402_5% USB30_RX_R_N2 19
2 1 2 8 USB30_RX_N2 18 19
R917 1 @ 2 0_0402_5% USB30_TX_R_P2 17 18
USB30_RX_N2 USB30_RX_R_N2 8 USB30_TX_P2 17
4 3 R918 1 @ 2 0_0402_5% USB30_TX_R_N2 16
4 3 8 USB30_TX_N2 16
15
EXC24CH900U_4P 14 15
USB20_N0_R/USB20_P0_R pin assgin is different from G SKL 13 14
L19 EMC_NS@ 12 13
USB30_TX_P2 USB30_TX_R_P2 +USB_VCCB 12
1 2 11
1 2 10 11
9 10
USB30_TX_N2 4 3 USB30_TX_R_N2 R67 1 @ 2 0_0402_5% USB20_N0_R 8 9
4 3 8 USB20_N0 8
B R66 1 @ 2 0_0402_5% USB20_P0_R 7 B
8 USB20_P0 7
EXC24CH900U_4P 6
USB20_P_CONN 5 6
USB20_N_CONN 4 5
3 4
L21 EMC@ PWR_LED# 2 3
USB20_N0 1 2 USB20_N0_R 1 2
1 2 +5VALW 1
HIGHS_FC5AF201-1151H
USB20_P0 4 3 USB20_P0_R ME@
4 3
EXC24CH900U_4P
+5VS
1
1
EMC_NS@ R927 LP2301ALT1G_SOT23-3 JKBL1
10K_0402_5% KBL@ +VCC_KB_LED 1
BATT_CHG_LED# 1
2
D
LED2 1 2 R924 1 2 1.5K_0402_5% KBL@ 3 1 2
36 BATT_CHG_LED# +5VALW 2
3
2
L-C192WDT-LCFC_WHITE 4 3
1 1
2
C1316 4
G
1
2
1 R934 2 C1315 0.1U_0201_6.3V6-K C1314 5
10K_0402_5% 10U_0603_6.3V6M KBL@ 0.1U_0201_6.3V6-K 6 GND1
2 2 GND2
check LED location and BOM structure when placement and Load BOM, PWR LED and BATT LED KBL@ 1 KBL@ KBL@
2
have the same location on 14"/15" 02/26 C1317 HIGHS_FC1AF040-1201H
0.01U_0201_10V6K ME@
KBL@
2
1
D
LED_KB_PWM 2 Q155
A 36 LED_KB_PWM G A
2N7002KW_SOT323-3
1
R933 KBL@
10K_0402_5% S
1
3
KBL@ C1318
0.1U_0201_6.3V6-K
1 KBL@
2
C195 2
U21 100P_0201_25V8J
1
GND 2
1
C196 3 LID_SW#
0.01U_0201_10V6K OUTPUT LID_SW# 36
Security Classification LC Future Center Secret Data Title
R1
1 2
0_0402_5% 2 +VCC_LID 2
+3VL
@ VCC Issued Date 2013/08/08 Deciphered Date 2013/08/05 KBD/PWR/IO/LED/TP Conn.
AH9247-W-7_SC59-3
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG516
Date: Tuesday, April 12, 2016 Sheet 37 of 51
5 4 3 2 1
A B C D E
EC need 1.8VS power ready before 3.3VS, chagne C173 from 2200pf to 4700pf
+5VLP +5VALW
Load Switch modify load swt i c h fr o m
APL3523 t o G5016KD1 U T DF N 14P
+5VALW To +5VS +3VS, C173 ‐‐> 5.78ms
+3VALW To +3VS +5VS, C176 ‐‐> 1.71ms
1
R156 R157 @ VIN 5V and 3.3V (VBIAS=5V), IMAX(per channel)=6A, Rds=16mohm Need Short
100K_0402_5% 100K_0402_5% R4 1 2 0_0402_5% 3VSON +3VALW +3VS
@ U13 J11 @
1 1 14 +3VS_LS 1 2 1
2
2 IN1_1 OUT1_2 13 1 2
SUSP IN1_2 OUT1_1 JUMP_43X118
12,25 SUSP 1 1
@ 3VSON 3 12 C173 1 2 2200P_0402_25V7-K C175
SUSP# R2 1 2 0_0402_5% 5VSON C178 EN1 CT1 0.1U_0201_6.3V6-K
1U_0402_6.3V6K 4 11 @
2 +5VALW VBIAS GND 2
@
1
Q6 D 5VSON 5 10 C176 1 2 1000P_0201_50V7-K
1 1 EN2 CT2
2 +5VALW +5VS
33,36,47 SUSP# G C180 C179 6 9 J12 @
1U_0402_6.3V6K 1U_0402_6.3V6K 7 IN2_1 OUT2_2 8 +5VS_LS 1 2
S 2N7002KW_SOT323-3 2 2 IN2_2 OUT2_1 1 2
3
1 15 JUMP_43X118 1
GPAD C174
Need Short
C177 G5016KD1U_TDFN14_2X3 0.1U_0201_6.3V6-K
1U_0402_6.3V6K @
2 @ 2
1
@ 2 2 C146 C145 1U_0402_6.3V6K
1 1
4
1
0.1U_0201_6.3V6-K @ 470_0603_5% @ 2 2
1 1
4
@ 2 C1327 C1328 0.01U_0201_10V6K R188 @
2 2 0.1U_0201_6.3V6-K @ 470_0603_5%
2
@
2 2 R206
2
R211 R194 1 2 1.8VS_GATE
1.8VS_GATE_R 1 2 1 2 1.8VS_GATE 2 R214 1 0_0402_5%
+20VSB
0_0402_5% 0_0402_5% R193
330K_0402_5% 0.95VS_GATE_R 1 2 1 R190 20.95VS_GATE 2 R189 1 +20VSB
1
1
D Q45 Q46 @ D 0_0402_5% 0_0402_5% 470K_0402_5%
1
C143 R212 2 SUSP 2 @ @
1
0.01U_0201_25V6-K 1M_0402_5% G G D Q37 Q40 @ D
1
C144 R187 2 SUSP 2
2 S 2N7002KW_SOT323-3 S 2N7002KW_SOT323-3 0.01U_0201_25V6-K 820K_0402_5% G G
2
3
@
2 S 2N7002KW_SOT323-3 S 2N7002KW_SOT323-3
3
@
3
20VSB will change to 6V in DC mode, careful the Res divide voltage 3
1
JUMP_43X79
R159 R935 R939 R940
Id=3.2A 47_0603_5% 47_0603_5% 47_0603_5% 47_0603_5%
@ @ @ @
LP2301ALT1G_SOT23-3
2
@
S
Q29 3 1
1
D Q8 D Q156 D Q157 D Q158
0.01U_0201_10V6K
0.1U_0201_6.3V6-K
@ @ 2N7002KW_SOT323-3 S @ 2N7002KW_SOT323-3 S @ 2N7002KW_SOT323-3 S @ 2N7002KW_SOT323-3 S @
3
2 2
4 4
1
C131
R164 0.1U_0201_6.3V6-K
100K_0402_5% @
2
@
Security Classification LC Future Center Secret Data Title
2
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5 4 3 2 1
1
1
1
PAD_O2P6X2P5D2P6X2P5N PAD_O3P0X2P5d3P0X2P5N PAD_O2P5X2P9D2P5X2P9N
H1 H3 NH4 H5 H6 H4 H10
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
1
1
CHASSIS1_GND
PAD_D3P4 PAD_CT7P0B9P0D3P0 PAD_C3P0D3P0N PAD_C8P0 PAD_C5P0 pad_ct4p5b7p0d3p3 PAD_C7P0D3P3
C C
H11 H12 H13 H14 H15 H16 H17 H18 H19 H20
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
1
1
PAD_CT7P0B9P0D3P0 pad_ct6p0b7p0d4p0 pad_ct6p0b7p0d4p0 pad_ct6p0b7p0d4p0 pad_ct6p0b7p0d4p0 PAD_ShapeT9P0X8P0CB9P0D3P0 PAD_ShapeT7P5X8P0D3P4 PAD_CT7P0B6P0D3P3 PAD_C7P0D3P0 PAD_C7P0
H21
HOLEA JSPON1
JSPON2
B 1 B
1 1
1
SHIELDING_PS-25G_5P5X3_1P
PAD_C6P0D2P5 SHIELDING_PS-25G_5P5X3_1P
A A
BRISTOL FM980PADY44AB 2.7G PR 1.0 BRISTOL AM970PADY44AB 2.5G PR 1.0 BRISTOL AM960PADY44AB 2.4G PR 1.0
PCB CG516 NM-A741 NS-A741/A743/A744 LAN Chip HDMI Loga FX9800P@ A129700P@ A109600P@
DAZ12300100 PCB_MB SA000074W00 HDMI@ SA00007RC10 SA00007RE10 SA00007TF00
8111H@ LAN Chip RO00000040J HDMI Logo APU type
D D
ZZZ8 ZZZ9
C C
MT40A512M16HA-083E:A MT40A512M16HA-083E:A MT40A512M16HA-083E:A MT40A512M16HA-083E:A 2K_0402_5% 10K_0402_5%
SA000079F10 SA000079F10 SA000079F10 SA000079F10 SD02820018J SD02810028J
DRAM_Micron 4G
DRAM_Hynix 4G
B B
VRAM ID config
UV5 H4G@ UV6 H4G@ UV7 H4G@ UV8 H4G@ RV70 H4G@
UV5 M4G@ UV6 M4G@ UV7 M4G@ UV8 M4G@ RV63 M4G@ RV70 M4G@ 128Mx16
NA 111 4.75K NC
VRAM_Micron_256M*16 010
Hynix
000 NC 4.75K
H5TC4G63CFR-N0C 4Gb 900(1G)
UV5 S4G@ UV6 S4G@ UV7 S4G@ UV8 S4G@ RV63 S4G@ RV70 S4G@
Micron
256Mx16 010 4.53K 2K
MT41J256M16LY-091G:N 4Gb 900(1G)
A A
K4W4G1646E-BC1A 4Gb K4W4G1646E-BC1A 4Gb K4W4G1646E-BC1A 4Gb K4W4G1646E-BC1A 4Gb 8.45K_0402_1% 2K_0402_1%
SA000063F20 SA000063F20 SA000063F20 SA000063F20 SD000011R00 SD03420018J Samsung
001 8.45K 2K
VRAM_Samsung_256M*16 001 K4W4G1646E-BC1A 4Gb 900(1G)
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DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG412
Date: Tuesday, April 12, 2016 Sheet 40 of 51
5 4 3 2 1
5 4 3 2 1
8 PXS_PWREN
A2 ACIN# EC_RSMRST#
V
A1
V
AC +0.95VGS
MODE
V
VIN
9 PBTN_OUT# VDDGFX_PD PU802
V V
V
A3 B2 3VL VR_GFX_PWRGD
PU501
V V V
PM_SLP_S3#
BATT BATT PM_SLP_S5# 10 APU +APU_GFX
D
V D
V
MODE +0.95VGS
V
B1
V
15 EC_SYS_PWRGD
+APU_CORE QV3
V
PLT_RST# 16
V
EC_ON A4 +APU_CORE_NB +3VGS
EC
V
QV6
V
17
KBRST# V V V V V V
V
B4
VGA
+1.8VGS
V
V APU_S5_MUX_CTRL +VDDCR_FCH_S5
ALW_PWRGD QV2
V
V
5 V PU602
B3
Compare
V
+0.7755VALW +1.35VGS
V
V
V
ALW_PWRGD ON/OFF
PU801
V
V
APUALW_PWRGD +0.95VALW +0.95VS
+3VALW +5VALW PU901
12 SUSP# Q41
V
C C
6 EC_APU_ALWEN
+1.8VS VGA_PWRGD
V
V V +1.8VALW
Q39
12 SUSP# 12 SUSP#
V
U13 loadswitch
V
V
PU701
+3VS +5VS
+0.6VS
V
V V
12 SUSP#
+1.5VS(reserve)
V
+2.5VS
V
B PU1103 B
14
VR_APU_PWRGD
13 EC_VR_ON +APU_CORE
V
PU1001
+APU_CORE +APU_CORE_NB
+APU_CORE_NB
13 EC_GFX_ON
PU1101 +APU_GFX
V
+APU_GFX
14
VR_GFX_PWRGD
A VDDGFX_PD A
B+
+5VLP/ 100mA
Silergy
SY8288C +5VALW/8A
Adaptor Converter
EC_ON EN FOR SYSTEM PGOOD ALW_PWRGD
+3VLP/ 100mA
D Silergy D
SY8286B
Converter +3VALW/6A
LCFC +1.2V/6A
LCFC5075
1.2VEN S5 PMIC +0.6VS/1A
SUSP# S3
TI FOR SYS PGOOD
BQ24780SRUYR +5VALW
Battery Charger +1.05VALW/6A
EC_APU_ALWEN EN
PGOOD APUALW_PWRGD
Switch Mode
C
+3VALW +1.8VALW/3A C
SMBus +1.8VALW
+0.775VALW/0.5A
EC_APU_ALWEN EN
+3.3VALW
Battery 2.5VEN EN
+2.5V/0.5A
Li-ion
2S1P
MPS
NB685GQ-Z APU GFX/22A/35A
Converter
B
FOR 1.35VGS B
PXS_PWREN EN PGOOD
Richtek
RT3662EBGQW
Switch Mode +VGA_CORE/20A
FOR VGA_CORE
PXS_PWREN EN PGOOD VR_VGA_PWRGD
02 APU_CORE/22A
BH5321
Switch Mode APU_CORE_NB/12A
APU_SVID VIDs
EN FOR CPU CORE&NB PGOOD VR_APU_PWRGD Security Classification LC Future Center Secret Data Title
EC_VR_ON
A
Issued Date 2013/08/15 Deciphered Date 2013/08/15 Power Diagram A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG516
02 Date: Tuesday, April 12, 2016 Sheet 42 of 51
BH5321 APU_GFX/22A
Switch Mode
APU_GFX_SVID VIDs
EN FOR CPU GFX PGOOD APU_PWROK
EC_GFX_ON
5 4 3 2 1
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5 4 3 2 1
D D
VIN
PL301 EMC@
JDCIN1 PF301 HCB2012KF-121T50_0805
1 APDIN 1 2 APDIN1 1 2
1 2
GND1 3 7A_24VDC_429007.WRML 1 2
GND2 4 PL302 EMC@
GND3 5
470P_0402_50V7K
HCB2012KF-121T50_0805
GND4 6
GND5
1
PC302
7 PC304
GND6 470P_0402_50V7K
PC301 EMC@ EMC@ PC305
2
HIGHS_PJSS0026-8B01H 1000P_0402_50V7K 1000P_0402_50V7K
ME@ EMC_NS@ EMC_NS@
C C
+3VL
PD301
2
+VCCRTC
1
RTC_VCC
3
JRTC1
2 PR301 1 1
1
1U_0402_10V6K
BAT54CW_SOT323-3 2
1K_0603_5% 3 2
B 2 G1 B
PC306
4
G2
1 @ ACES_50273-0020N-001
ME@
A A
SUYIN_125022HB008M202ZL
2
1 1 2 1 2
D
1
2
2
EC_SMCA
BATT+ D
9 3 PR401 1 2 100_0402_1% EC_SMB_CK1 36,45 PL402 EMC@
10 GND1 3 4 EC_SMDA PR402 1 2 100_0402_1% HCB2012KF-121T50_0805
GND2 4 EC_SMB_DA1 36,45
5 1 2
5 6
6
1
7
7 8 PC401 PC402 PD401
8 1000P_0402_50V7K 0.01U_0402_25V7K EC_SMCA AZC199-02S.R7G_SOT23-3
2
ME@ PR403 EMC@ EMC@ EC_SMDA EMC_NS@
100K_0402_1% BATT_TEMP_IN
1 2
+3VALW
1
Reverse PD305 For EMI request
1
BATT_TEMP_IN 1 2
BATT_TEMP 36,45
PD402
1
PR404 AZ5215-01F_DFN1006P2E2
10K_0402_5% EMC_NS@
2
2
C C
B B
A A
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5 4 3 2 1
PL502 EMC_NS@
HCB2012KF-121T50_0805
1 2
PL503 EMC_NS@
HCB2012KF-121T50_0805
1 2
VIN PQ501 PQ502
P3
AON6414AL_DFN8-5 AON7408L_DFN8-5
P2 @ PR501
1 1 PJ501 0.01_1206_1%
2 2 JUMP_43X118
5 3 3 5 1
1 2
2 1 4
B+
2 3
D D
10U_0805_25V6K
10U_0805_25V6K
1
2
1
PC503
PC504
PC502
PC501 PR502 0.022U_0402_25V7K
1
4.7_0603_5%
2
470P_0402_50V7K
5
0.1U_0402_25V6
2
PQ503
PC505
EMC_NS@ AON6414AL_DFN8-5
EMC_NS@ 1 2
BQ24780_BATDRV 4
1
PC506 PC507
1
1U_0603_25V6K 0.1U_0402_25V6
3
2
1
2
PR503
499K_0402_1% PC508
0.01U_0402_25V7K
1
VIN BATT+
2
BAT54CW_SOT323-3
PD501
2
3
B+
AC pull in hang up issue PR513 BOM 7.15K
10U_0805_25V6K
10U_0805_25V6K
VIN
1
1
2
PC510
4.02K_0603_1%
4.02K_0603_1%
PC509
ACN
ACP
PR507
PR508
PC511
2200P_0402_50V7K
EMC@
1
2
PR511
5
PR510 10_1206_5% BQ24780_VDD
2
1
C PC512 C
6.81K_0603_1% 43.2K_0603_1% 1U_0603_25V6K
ACP
ACN
1 2
1
PR513 2 1 780_VCC
28 24 1 2 PQ506
2
VCC REGN 2.2U_0603_10V6-K PC514 4
1 2 ACDET 6 AON7408L_DFN8-5
PC513 ACDET PR514 PC515
0.01U_0402_25V7K 25 BST_CHG
1 2 2 1
BTST 2.2_0603_5% PL501 PR515
3
2
1
0.047U_0603_16V7K 4.7UH_PCMB063T-4R7MS_5.5A_20% 0.01_1206_1%
3 26 DH_CHG
PR512 20K_0402_1% @ CMSRC HIDRV 1 2 CHG 1 4 BATT+
2 1 4
ACDRV 2 3
1
PR516 2 @ 1 100K_0402_1% 27 LX_CHG
BQ24780_VDD PHASE
10U_0805_25V6K
10U_0805_25V6K
PR517
2
ACIN_R 2.2_0805_5%
PC516
PR518 1 2 5
36 ACIN ACOK
PC517
0_0402_5% EMC_NS@
PR519 10_0402_5% 2@ EC_SMB_DA1_R
11
36,44 EC_SMB_DA1
1
SDA PU501 23 DL_CHG PQ507 4
0_0402_5% LODRV
1
PR520 1 2@ EC_SMB_CK1_R 12 BQ24780SRUYR 22 AON7408L_DFN8-5
36,44 EC_SMB_CK1 SCL GND PC518
1200P_0402_50V7-K
3
2
1
2
36 ADP_I PR521 1 2 ADP_I_R 7 29 EMC_NS@
0.1U_0402_25V6
0.1U_0402_25V6
0_0402_5% IADP PAD
1
BQ24780_BATDRV
PC519
PC520
IDCHG 8 18
IDCHG BATDRV
100P_0402_50V8J
PMON 9
100P_0402_50V8J
100P_0402_50V8J
PR522 10_0603_5%
2
PMON 17 2 1
BATSRC
20 SRP_R 2 1 SRP
10 SRP PR523 10_0603_5%
36,47,50,51 VR_HOT# PROCHOT#
1
2
13 PC524
CMPIN
2
0.1U_0402_25V6
2
BATPRES#
TB_STAT#
PC521
@ 14
1
CMPOUT SRN_R
PC522
PC523
19 2 1 SRN
1
B
ILIM 21 SRN PR524 10_0603_5% B
@ ILIM
2
PR525
16
15
0_0402_5%
1
1 2 ILIM_R 1 2TB_STAT#
+3VALW BATT_TEMP 36,44
PR526 14.7K_0402_1%
316K_0402_1% PR527
1
1
PR528
PC525 100K_0402_1%
0.1U_0402_25V6
2
A A
D D
B+ @
2
PJ601
1
1.5A +3V_VIN
PU601
5 9 +3V_PWRGD
10U_0805_25V6K
2 1 4 IN1 PG
1
1 +3VBS 1 2
10U_0805_25V6K
0.1U_0402_25V6
3 IN2 BS
1M_0402_5%
PC626
PC603
+3VALW
SY8286BRAC_QFN20_3X3
2 IN3
EMC@
PC602
PC601
PR601
JUMP_43X79 0.1U_0603_25V7-M
2
IN4 6 @
5A
2
7 LX1 19 PL601 PJ602
8 GND1 LX2 20 +3VLX 1 2 +3VALW_P 2 1
2
18 GND2 LX3 2 1
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
2.2UH_PCMB063T-2R2MS_8A_20%
21 GND3
GND4
1
PR602 JUMP_43X79
EC_ON_R +3VALW_EN +3VALW_P 3VLAW
PC604
PC605
PC606
PC607
2 1 2 1 12 14 PR604
EN1 OUT
36,47 EC_ON 0_0402_5% 0_0402_5% +3V_VIN 11 2.2_0805_5% TDC=5A OCP=8A
2
PR603 EN2 13 +3VALW_FB EMC_NS@
10 FF
1 2
NC1
30 EC_ON_R 15
NC2 100mA +3VLP
1M_0402_5%
16 17
0.1U_0402_25V6
NC3 LDO
PR606
PC610
PC608
1200P_0402_50V7-K
4.7U_0603_6.3V6K
2
1
@ EMC_NS@
PC609
2
2
PC612
PR609
1 2 1 2
1000P_0402_50V7K 1K_0402_1%
+3VL
+3VLP @
C PJ603 C
2 1
2 1
JUMP_43X39
+3VALW
2
PR610
100K_0402_5%
PR611
1
+3V_PWRGD 1 2
ALW_PWRGD 47
B+ 0_0402_5%
PU602
2
PJ604
1
2.5A +5V_VIN 5 9 +5V_PWRGD PC616 1
PR612
2 +5VALW
2 1 4 IN1 PG 1 +5VBS 1 2
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
IN2 BS
1
6A
PC614
PC615
3 0_0402_5%
IN3
PC613
7 LX1 19 2 1
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
@ GND1 LX2
8 20
GND2 LX3
1
18 PR618 @ 2.2UH_PCMB063T-2R2MS_8A_20% JUMP_43X79
GND3
PC618
PC627
PC620
PC621
EMC@ 21 0_0402_5% PR615
PR613 GND4 14 1 2+5VALW_P 4.7_0805_5%
@
2
EC_ON_R 1 2 +5VALW_EN 12 OUT EMC_NS@
+5V_VIN 11 EN1 13
1 2
EN2 FF
0_0402_5%
15
100mA 5VLAW
LDO +5VLP TDC=6A OCP=9A
1M_0402_5%
10 PC624
NC1
1
B 1000P_0402_50V9-J B
16 17
2
NC2 VCC
1
PR616
EMC_NS@
@ PC622
0.1U_0402_25V6 SY8288CRAC_QFN20_3X3
2
4.7U_0603_6.3V6K
2
PC623
PC617
1U_0603_25V6M
1
PC625
PR617
1 2 1 2
1000P_0402_25V7-K 1K_0402_1%
A A
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THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG516
Date: Tuesday, April 12, 2016 Sheet 46 of 51
5 4 3 2 1
5 4 3 2 1
PMIC_VCC
+5VALW PR722
2 1
@
10_0603_5%
+5VLP PR701
D D
2 1
1_2VEN PR715
36 1_2VEN 0_0402_5%
10_0603_5%
1
1 2
+DDR_S3 EC_ON 36,46
PR703 2 1 0_0402_5% PC701
33,36,38 SUSP# 10U_0603_6.3V6M
2
PR706 PR704
PR705 2 1 0_0402_5% 1.8VALW_EN 1.2V_B+ 1 2 10_0402_5% 0_0402_5% @
36 EC_APU_ALWEN EN_PMIC 1 2
0.1U_0402_25V7-K
2 ALW_PWRGD 46 1.05VLAW
PC702
0.1U_0402_10V7K
PR723
PMIC_VCC TDC=6A OCP=8A FSW=1.2MHZ
2
0_0402_5% 1.0VALW_EN
PC703
PR707 2 1 0_0402_5%
1 1 2
1.8VLAW
1
PR708 10K_0402_5% @ @
2 1 EC_LDO1_R TDC=3A OCP=6A FSW=1.2MHZ
28
27
41
PU701
9
0.1U_0402_10V7K
0.1U_0402_10V7K
0.047U_0402_25V7K
VSYS
VCC
PMIC_EN
GND
1
EC_LDO2_R
1.2V
1M_0402_5%
PR709 2 1 @ 0_0402_5%
36 2_5VEN EC_LDO1_R PCH_I2C2_SDA_PMIC
PR710
0_0402_5% 29 25 PR711 2 1
0.1U_0402_10V7K
EC_SMB_DA0 36
EN_LDO1 SDA TDC=6A OCP=14A FSW=1MHZ
2
PC707
PC708
PC709
@
0.047U_0402_25V7K
2
PC705
PC704
PC706
2
1.0VALW_EN 11 24 PR713 2 1 @ 0_0402_5%
EN_V1P0A T_ALERT_B VR_HOT# 36,45,50,51
@ @
1
1.8VALW_EN 16 22 APUALW_PWRGD
@ EN_V1P8A POK_V1P0A
1_2VEN 31 21 APUALW_PWRGD
EN_VDDQ POK_V1P8A
+3VALW +DDR_S3 36
EN_VTT POK_VDDQ
23 1 PAD @ PTC701 +0.95VALW 0.95VALW 实 际 电 压为1.0 5V
+5VALW
PL701 在 EC setting 注 意
PJ701 @ 12 PJ702 @
6A
22U_0603_6.3V6-M
22U_0603_6.3V6-M 22U_0603_6.3V6-M
2 1 7 LX_V1P0A_12 13 1 2 +0.95VALWP 2 1
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
0.1U_0402_25V6
LV5075AGQV_VQFN40_5X5
2 1 8 VIN_V1P0A_7 LX_V1P0A_13 14 2 1
1 VIN_V1P0A_8 LX_V1P0A_14
1
100K_0402_5%
PC710
PC711
PC717
15
EMC_NS@
0.33UH_PCMB063T-R33MS_21A_20% JUMP_43X79
JUMP_43X39 LX_V1P0A_15
+1.8VALW
PC713
PC714
PC715
PC716
PC712
1
0.1U_0402_25V7-K
PR716
R_0402
C 10 C
2
VO_V1P0A
+3VALW 2 EMC_NS@
2
PJ703
@
1 19 LX_V1P8A_17
17
18 1
PL702
2 +1.8VALWP 2
PJ704 @
1
3A
2
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
APUALW_PWRGD 36 1
1
PC718
@ 20 JUMP_43X79
0.1U_0402_25V6
JUMP_43X39 VO_V1P8A_20
1
PC719
0.1U_0402_25V7-K
PC720
PC721
PC722
PC723
2 2 33 UG_1.2V
EMC_NS@
EMC_NS@
2
38 UGATE_VDDQ PC725
PC724 1 2 10U_0603_10V6K +1.2VSP VIN_VTT 32 1 PR717 2 2 1
BOOT_VDDQ 0_0603_5%
10U_0603_6.3V6M
1A
+0.6VS 39
VTT
0.1U_0603_25V7-M @
1
LX_1.2V
PC726
34
PHASE_VDDQ
40 35 LG_1.2V
2
VSNS_VTT LGATE_VDDQ
37 +1.2VSP
VSNS_VDDQ
+1.8VALW PR718 1 2 28.7K_0402_1% 30
CS_VDDQ
1
PC728
+3VALW JUMP_43X39 PC727 10U_0603_6.3V6M JUMP_43X39 @
4.7U_0603_6.3V6K
2
2
PJ707 3 +2.5VP 2
PJ708
500mA
1 +2.5V
2 1 Vin_LDO2 4 LDO2 2 1
2 1 VIN_LDO2 2
FB_LDO2 JUMP_43X39
1
24.9K_0402_1%
PJ709 @
JUMP_43X39
1
@ 1.2V_B+
PR719
PC730 2 1
@ 4.7U_0603_6.3V6K PC729 2 1 B+
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
2
1
LDO2_FB
10U_0603_6.3V6M
PC731
PC732
PC733
JUMP_43X79
2
2
2
B B
10.5K_0402_1%
5
PR720
EMC@
2
PQ701
UG_1.2V 4
AON7408L_DFN8-5
+5VALW
3
2
1
PL703
0.68UH_PCMB063T-R68MN_16A_20% PJ710 @ 6A
LX_1.2V 1 2 +1.2VSP 2 1
+3VALW 2 1
+1.2V
+1.5VSP +1.5VS
1
5
JUMP_43X118 1
1
500mA
330U_2.5V_M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
PC1142 @
0.1U_0402_25V6
1
+
PC741
1U_0603_25V6M PR721
2
1
500mA
PC739
4.7_0603_5%
PC734
PC735
PC736
PC737
PC738
PC1151
PU1103 EMC_NS@
2
PJ1104 6 PJ1105 LG_1.2V 4 @ 2
2
2 1 5 VCNTL 3 2 1
2 1 9 VIN1 VOUT1 4 2 1
4.7U_0603_6.3V6K
VIN2 VOUT2
1
1
220P_0402_50V7K
10.5K_0402_1%
PQ702 PC740
10U_0603_6.3V6M
PR1136
@ SUSP# 8
3
2
1
EN
1
@
PC1143
PC1144
@ 7 2 AON7506_DFN EMC_NS@ @
GND
EMC_NS@
2
2
POK FB
1
@ PC1141 G971LADJF11U_SO8
1
0.047U_0402_25V7K @
2
@
PR1134 @ @
@ 100K_0402_5%
1
12K_0402_1%
PR1135
2
A A
2
+3VS @
PJ801
2 1 2A 1.35VGS_B+
B+ 2 1
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
JUMP_43X79
@
1
PC801
PC802
PC803
2
2
1 PR801 PC804 1
PU801 0_0603_5% 0.1U_0603_25V7-M
PX@ PX@ EMC_PX@ 1 10 BST_1.35VGS 1 2 2 1 PL801
PR802 VIN BST 0.68UH_PCMB063T-R68MN_16A_20%
LX_1.35VGS PX@
100K_0402_1%
SW
9 PX@ 1 2
+1.35VGSP
NB685GQ-Z_QFN16_3X3
4.7_0603_5%
1 2 16 PX@
EN1 PR805 PC805
2
EN_1.35VGS 15 1.35VGS_FB
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
PR804
PX@ 13 1M_0402_5% 220P_0402_50V7K
EN2 FB
0.1U_0402_25V6
2 1 2 1
1
PC808
PC806
PC809
PC810
PC807
12 6
+3VALW PG VDDQ
+1.35VGSP EMC_PX_NS@ @ @
2
680P_0402_50V7K
499_0402_1%
1 2 1.35VGS_3V3 3 @
3V3 PX@ PX@ PX@ PX@
1
PR807 4.7_0402_5% PC811 5 NB685_VTT EMC_PX_NS@
VTT
1
PC812
PR808
PX@ 1U_0402_6.3V6K
PX@ 4
2
AGND 8 EMC_PX_NS@
2
2 VTTS
2
PGND
1U_0402_6.3V6K
1.35VGS_GND 7 PX@
VTTREF 1 2
NB685_REF
1
PC813
Mode 14 11
MODE OTW# PR809
PX@ 41.2K_0402_1%
2
2
PX@
EN_1.35VGS
1U_0402_6.3V6K
1 2
7,19,49 PXS_PWREN PR811 PX@
1
PX@ 0_0402_5%
1
1M_0402_5%
200K_0402_1%
PC815
.1U_0402_10V6-K
PR812
2
PR810 32.4K_0402_1%
1
1
PR813
PC814
PX@
2
PX@
2
PX@ 1.35VGS_GND
2
1 1.35VGS_GND
1.35VGS_GND
PX@
PJ802
1 2
JUMPER
@
PJ803
1.35VGS_GND
+1.35VGSP 2 1
+1.35VGS
2 2
2 1
@ JUMP_43X79
PJ805 no short
+5VALW
+3VALW
+0.95VGSP +0.95VGS
1
PC816 500mA
1U_0603_25V6M
2
500mA @
PU802
PJ804 6 PJ805
2 1 5 VCNTL 3 2 1
2 1 VIN1 VOUT1 2 1
4.7U_0603_6.3V6K
9 4
VIN2 VOUT2
1
1
PR814
3
JUMP_43X39 PXS_PWREN 2EN_0.95VGS JUMP_43X39 @ 3
PC817
1 8 PR815
EN
1
7 2 14.7K_0402_1%
GND
2
@ 220P_0402_50V7K 10U_0603_6.3V6M
2
PC820 G971LADJF11U_SO8
@ @
1
.1U_0402_10V6-K @
2
@
@ PR816
@
100K_0402_5%
1
@
PR817
2
47K_0402_1%
2
+3VS @
VFB=0.8V
4 4
WWW.AliSaler.Com
2013/08/15 Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG516
Date: Tuesday, April 12, 2016 Sheet 48 of 51
A B C D
5 4 3 2 1
+VGA_B+
PJ901
2 1
+5VALW 2 1
B+
JUMP_43X79
@
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
PR901 PC904 PC909 PC908 change to SE00000W10J
1
PC901
PC902
PC903
4.7_0603_5%
5
PX@
+5VALW
2
+VGA_CORE
AON6372_DFN
D
PC904
PU901
+VDDIO_GPU D
PQ901
2.2U_0402_6.3V6-K
PC908 2.2U_0402_6.3V6-K VGA_UGATE1 4 TDC :20A
1
PX@ VGA_VCC
14 19 2 1 EMC_PX@ PX@ PX@
PR902
1 VCC VDDIO 1
PR906
OCP :35A
0_0603_5% 4.7_0402_5%
PC909 PX@
+VGA_B+
3
2
1
2 2 PR903 4.7_0402_5% PL901
PX@ PX@
2
2 1 27 1 2 1 VGA_PHASE1 1 2
PVCC VIN +VGA_CORE
1.21K_0402_1%
1
2.2U_0402_6.3V6-K PC910 PX@ PR907 PX@ 0.22UH_SPS-06CZ-R22M-V1_23A_20%
PR909
330U_2.0V_M
330U_2.0V_M
330U_2.0V_M
1U_0402_25V6-K 2.2_0603_5% PX@ 1 1 1
2 PR911 1
VGA_BOOT1 2 VGA_BOOT1_R
4.7_0805_5%
PR908 24.9K_0402_1% PR910 0_0402_5% 21 1 1 2
VSEN + + +
PC906
PC912
PC913
2 1 2 1 11 EMC_PX_NS@
AON6764_DFN
AON6764_DFN
SET1 PC907 56P_0402_50V8-J PC905 220P_0402_50V7K PC911 PX@ PX@
2
PQ902
PQ903
PX@ PR905
PX@ 2 1 2 1 0.22U_0603_25V7K PC915 0.47U_0402_25V6K
PH901 VGA_LGATE1 PX@ 2 2 2
1PR904 21 2 4 4 2 1
0_0402_5% 18.7K_0402_1% 2 1 PX@ PX@
PX@ PX@ 3 2 1 2 1 2 1 PX@ PX@ PX@
COMP
2
PX@
PR915 100K_0402_1%_TSM0B104F4251RZ
1
PR916 4 PR912 61.9K_0402_1% PR913 10K_0402_1% PC917 300_0402_5% PC918
VGA_ISEN1P
+VGA_CORE
3
2
1
3
2
1
2 1 1 2 2 PX@ 1 10 FB PC916 680P_0402_50V7K PR914
PX@ PX@ PX@ 0.1U_0402_25V6
1
0_0402_1% TSEN 2 EMC_PX_NS@ PX@
100P_0402_50V8J
2
66.5K_0402_1% PR917 61.9K_0402_1% RGND
PX@ PX@
PX@ PX@ @
1
PR919 PC1152 @
1PR918 21 2 0.1U_0402_25V6 PC1145
0_0402_5% 33.2K_0402_1% 22 0.1U_0402_25V6 2 1 PR920 10_0402_5%
2
NC VGA_BOOT1
VREF PX@ PX@ 13 23 @ 1 2
VREF_PINSET BOOT1
1
24 VGA_UGATE1 1 PX@ 2
PR922 UGATE1
3.9_0402_1% 100K_0402_1%_TSM0B104F4251RZ 25 VGA_PHASE1 PR921 10_0402_5%
PH902 PHASE1
PX@
1 2 1 2 2 1 12 26 VGA_LGATE1 VGA_CORE_SEN 16
2
IMON LGATE1
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
PR923
PX@
PX@ 10.7K_0402_1% PR924
1
C 11K_0402_1% VGA_VSS_SEN 16 C
PX@
1
PC1153
PC1154
PC1155
PC1156
PC925
PC926
PC927
PC928
PC919 PX@
0.47U_0402_25V6K 7 VGA_ISEN1P
2
1 2 ISEN1P
2
PR925 15.8K_0402_1% 8 +VGA_CORE
ISEN1N
PX@
9 @ @ @ @ PX@ PX@ PX@ PX@
16,36 GPU_VR_HOT# VRHOT_L
15
15 VGA_PWROK PWROK
20 31
7,15 VR_VGA_PWRGD PGOOD BOOT2
30
UGATE2
0_0402_5%
PR926 1 2 16 29
16 GPU_SVC SVC PHASE2
@
0_0402_5% 28
PR927 1 2 17 LGATE2
16 GPU_SVD SVD
@
0_0402_5%
PR928 1 2 18
16 GPU_SVT SVT
@
PR929
2 1 32 5 VGA_VCC
7,19,48 PXS_PWREN EN ISEN2P
200K_0402_1%
PX@
2
33
1 2 GND 6
ISEN2N
1
PD901 PC923
RB751V-40_SOD323-2 .1U_0402_10V6-K
@
RT3662EBGQW_WQFN32_4X4
B B
PX@
+3VGS
2
10K_0402_5%
2
10K_0402_5%
PR938
4.7K_0402_5%
PR939
PR940
PX@
VR_VGA_PWRGD 1
GPU_VR_HOT# 1
A PX@ PX@ A
VGA_PWROK
CPU_B+
PJ1001
2 1
2 1
B+
5
2 1 FB_NB_3 2 1 JUMP_43X79 1 1
68U_25V_M
68U_25V_M
PQ1006 @
10U_0805_25V6K
10U_0805_25V6K
D
+ +
PC1039
PC1035
PC1004 PR1061
0.1U_0402_25V6
1
PC1036
PC1037
PC1038
680P_0402_50V7K 2K_0402_1% PC1007 AON7400AL_DFN8-5 @
PR1002 150P_0402_50V8-J
0_0402_5% 1 2 1 2FB_NB_2
1 2 1 2 UGATE_NB 4 2 2 +APU_CORE_NB
2
1 2 PR1058 G
6 APU_VDDNB_SEN_H
PR1059 82K_0402_1% PR1060@ EMC@
S3
S2
S1
1.58K_0402_1% 32.4K_0402_1% TDC :12A
PR1057 100_0402_1%
OCP :22A
3
2
1
1 2 1 2FB_NB_1
1 2 1 2 PC1017
+APU_CORE_NB PR1056 47P_0402_50V8J
PL1003
0.36UH 20% PCMB063T-R36MS 20A
PC1014 499_0402_1%
@ PC1018 100P_0402_50V8J PHASE_NB 1 4
330P_0402_50V8J +APU_CORE_NB
1 2 PR1024 PC1042 2 3
5
D 2.2_0603_5% 0.22U_0603_25V7K PR1029 D
BOOT_NB 1 2 BOOT_NB_R1 2 3.65K_0402_1%
330U_2.0V_M
330U_2.0V_M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
AON6372_DFN
1 1
VSUMP_NB 1 2
1
VSUMP_NB + +
EMC@
PQ1007
PC1044
PC1045
1
LGATE_NB
PC1046
PC1047
PC1048
PC1049
PC1050
PC1051
4
10K_0402_1%_TSM0A103F34D1RZ
PR1028
COMP_NB
VSEN_NB
2
PR1023 4.7_0805_5% VSUMN_NB 1 2 2 2
FB_NB
2 NB_NTCS
2.61K_0402_1%
1 1
1
EMC@
PR1030
3
2
1
2
1
PR1055 PC1020 10_0402_1%
11K_0402_1% PC1019 0.1U_0402_25V6 PC1052
0.047U_0402_25V7K @ PGOOD_NB 680P_0402_50V7K @ @
2
PH1004
2
LGATE_NB
PR1021
1K_0402_1% PHASE_NB
VSUMN_NB 1 1 2 VSUMN_NB_11
UGATE_NB
1 2 NB_R_B
2 1
2
BOOT_NB
PC1022 PC1021 PR1054@
0.1U_0402_25V6 0.22U_0201_6.3V6-K 10K_0402_5%
1
PR1053
40
39
38
37
36
35
34
33
32
31
@
27.4K_0402_1% PU1010
1 2
ISUMP_NB
ISUMN_NB
VSEN_NB
FB_NB
COMP_NB
PGOOD_NB
LGATE_NB
PHASE_NB
BOOT_NB
UGATE_NB
PR1032 PH1002
10.7K_0402_1% 470K_0402_3%_NCP15WM474E03RC
1 2 62771NTC_NB_R 1 2 62771NTC_NB 1 30
NTC_NB BOOT2
IMON_NB 2 29 PR1008
0_0402_5% IMON_NB UGATE2
PR1016 1 2 @ 62771_SVC_A 3 28 1 2 0_0402_5%
6 APU_SVC
0_0402_5% SVC PHASE2
+5VALW CPU_B+
PR1020 1 2 @ 62771_VRHOT_A 4 27
1000P_0402_50V7K
0_0402_5%
1
62771_SVD_A APU_VDDP
PC1023
PR1017 1 2 @ 5 26
6 APU_SVD SVD VDDP
2
PR1052
0_0402_5%
PR1078 1 2 @ 62771_VDDIO_A 6 25 APU_VDD 1 2
+1.8VS
10U_0805_25V6K
10U_0805_25V6K
0_0402_5% VDDIO ISL62771HRTZ_TQFN40_5X5 VDD PR1051
0.1U_0402_25V6
1
1
62771_SVT_A LGATE1_APU
EMC@
PC1001
PC1002
PC1003
PR1018 1 2 @ 7 24 1_0603_5%
6 APU_SVT
2
SVT LGATE1
2
PR10501 2
0_0402_5% 62771_EN_A 8 23 PHASE1_APU
36 EC_VR_ON
2
ENABLE PHASE1
5
1U_0603_25V6M
1U_0603_25V6M
0_0402_5%
1
62771_PWROK_A 9 UGATE1_APU
PC1024
PC1025
PR1013 1 2 @ 22
6,51 APU_PWROK PWROK UGATE1
1M_0402_5%
AON6372_DFN
AON6372_DFN
+APU_CORE
1
2 1 62771A_IMON 10 21 BOOT1_APU
IMON BOOT1
PQ1001
PQ1107
PR1045
PR1049
133K_0402_1% UGATE1_APU 4 UGATE1_APU
4
PGOOD
TDC :22A
ISUMN
ISUMP
COMP
ISEN2
ISEN1
VSEN
C @ C
NTC
RTN
1 2
OCP :TBD
FB
TP
2
PL1001
PC1034 0.36UH_PCMC104T-R36MN1R105_30A_20%
11
12
13
14
15
16
17
18
19
20
41
3
2
1
3
2
1
0.1U_0402_25V6
PR1048 +3VS PHASE1_APU 1 4
27.4K_0402_1% +APU_CORE
62771_VSEN_APU
62771_FB_APU
62771_ISUMN_APU
62771_RTN_APU
1 2 62771NTC_APU PR1001 PC1005 2 3
5
2.2_0603_5% 0.22U_0603_25V7K
BOOT1_APU
EMC@
PR1047 1 2BOOT1_R_A
1 2
2
APU_NTC_1
1 2 1.91K_0402_1%
PRE-PWROK METAL VID CODES
AON6764_DFN
AON6764_DFN
PR1005
PQ1002
PQ1003
+5VALW
PH1001 0_0402_5% 4.7_0805_5%
1
2
330U_2.0V_M
330U_2.0V_M
470K_0402_3%_NCP15WM474E03RC
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
SVC SVD Boot Voltage
330U_D2_2V_Y
VR_APU_PWRGD 36 1 1 1
PR1031
1 1
1
+ + +
EMC@
PC1008
PC1009
PC1010
10.7K_0402_1%
0 0 1.1V
1
PC1016
PC1011
PC1012
PC1013
0_0402_5%
PR1046 PGOOD_NB PR1011 1 2 @ PC1015
0 1 1.0V
1
3
2
1
3
2
1
2
10K_0402_5% 680P_0402_50V7K 2 2 2
2
1 0 0.9V
2
1 1 0.8V(Default)
ISEN2_APU @ @
ISEN1_APU PR1006
3.65K_0402_1%
1
VSUM+_APU 1 2VSUM+_APU1_R
PR1044
10K_0402_5%
PC1040
0.1U_0402_25V6
2
1 2
PR1010
330P_0402_50V8J
PR1003 32.4K_0402_1%
2.61K_0402_1% 2 1APU_R_B
1 2
0.047U_0402_25V7K
1 2 1 2APU_FB_1
1 2
+1.8VS
2
1
@ 1.58K_0402_1%
1
1
PC1056
1APU_FB_3 1
PC1006
2 2
10K_0402_1%_TSM0A103F34D1RZ
PR1034
2
2
1
PH1003
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
1K_0402_1%
10_0402_1%
1
B 2 1 +APU_CORE
B
1
VSUM+_APU
PC1026
PC1027
PC1028
PC1029
PC1030
PC1031
PC1032
PC1033
2
2
PR10072 1 APU_VDDCORE_SEN_H 6
+1.8VS 0_0402_5%
1
62771_SVC_A PC1058
@ 330P_0402_50V8J PR1025
62771_SVD_A @ 0_0402_5%
2
2 1
2
APU_VDD_SEN_L 6
1
PC1059 PR1022 2 1
1
.1U_0402_10V6-K
2
PR1019 PR1015
220_0402_5% @
@
220_0402_5%
2
A A
5 4 3 2 1
WWW.AliSaler.Com
5 4 3 2 1
+GFX_B+
PJ1101
2 1
2 1
B+
JUMP_43X79
10U_0805_25V6K
10U_0805_25V6K
@
0.1U_0402_25V6
1
EMC@
PC1157
PC1159
PC1158
2
2
5
APU_GFX
AON6372_DFN
10K_0402_5%
PQ1101
TDC :22A
1
D GFX_UGATE1 D
10K_0402_5%
10K_0402_5%
@ 4
1
0_0402_5%
OCP :TBD
PR1109
PR1113
PR1114
PR1118
PR1119 PL1101
0_0402_5% 0.36UH_PCMC104T-R36MN1R105_30A_20%
3
2
1
@
2
2 1 GFX_PHASE1 1 4
PC1101 +APU_GFX
PR1122 0.22U_0603_25V7K 2 3
330U_2.0V_M
330U_2.0V_M
2.2_0603_5%
330U_D2_2V_Y
40
39
38
37
36
35
34
33
32
31
1 1 1
1
PU1101 GFX_BOOT1 1 2 GFX_BOOT1_R
1 2
+ + +
PC1114
PC1115
PC1116
PR1115
AON6764_DFN
AON6764_DFN
ISUMP_NB
ISUMN_NB
VSEN_NB
FB_NB
COMP_NB
PGOOD_NB
LGATE_NB
PHASE_NB
UGATE_NB
BOOT_NB
4.7_0603_5%
PQ1103
PQ1104
EMC@
2
PR1120100K_0402_1% GFX_LGATE1 4 GFX_LGATE1
4 2 2 2
2
1 2 1 30 PR1116
NTC_NB BOOT2 @
680P_0402_50V7K
10_0402_1%
1100K_0402_1%
PR1121 2 2 29 PR1117
GFX_VSUM-
IMON_NB UGATE2
PC1118
0_0402_5%
GFX_VSUM+
3.65K_0402_1%
3
2
1
3
2
1
1
PR1110 1 2 @ APU_GFX_SVC_R 3 28
6 APU_GFX_SVC
1
0_0402_5% SVC PHASE2
2
PR1123 1 2 @ GFX_VRHOT_L4 27 PR1124
36,45,47,50 VR_HOT# VR_HOT_L LGATE2
0_0402_5% 0_0402_5% EMC@
PR1111 1 2 @ APU_GFX_SVD_R 5 26 GFX_VDDP 1 2
6 APU_GFX_SVD SVD VDDP PR1125 +5VALW
GFX_VDD
+1.8VS
6 25 1 2
0_0402_5% VDDIO ISL62771HRTZ_TQFN40_5X5 VDD 1_0603_5%
PR1112 1 2 @ APU_GFX_SVT_R 7 24 GFX_LGATE1
6 APU_GFX_SVT SVT LGATE1
1
2 1 GFX_ENABLE 8 23 GFX_PHASE1 PC1102 PC1103
36 EC_GFX_ON ENABLE PHASE1
0_0402_5% 1U_0603_25V6M 1U_0603_25V6M
2
0_0402_5% PR1126 1 2 @ GFX_PWROK9 22 GFX_UGATE1
6,50 APU_PWROK PWROK UGATE1
2
1M_0402_5%
PR1168
1
10 21 GFX_BOOT1
IMON BOOT1
PR1169
PGOOD
PC1104
ISUMN
ISUMP
COMP
ISEN2
ISEN1
VSEN
.1U_0402_10V6-K
NTC
RTN
PR1127
FB
TP
C C
2
100K_0402_1%
11
12
13
14
15
16
17
18
19
20
41
2 1
+3VS
0.1U_0402_25V6
1
PC1121
GFX_ISUMN
VR_GFX_PWRGD 7,36
GFX_COMP
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
PR1128
27.4K_0402_1%
GFX_FB
1
1 2 GFX_NTC
PC1128
PC1122
PC1123
PC1129
PC1130
PC1124
PC1131
PC1125
PC1132
PC1133
PC1126
PC1134
2
2
2
470K_0402_3%_NCP15WM474E03RC
1
PR1130
10.7K_0402_1% GFX_NTC @ @
+5VALW
2
PR1140
10K_0402_5%
2 1
GFX_ISEN1
PC1109 PC1110
PR1131 2 1 0.1U_0402_25V6 PC1108 PR1132 47P_0402_50V8J PR1133@
10K_0402_5% 1 2 100P_0402_50V8J 499_0402_1% 32.4K_0402_1%
PR1101604_0402_1% 1 2 GFX_FB_2 1 2 1 2 1 2
GFX_VSUM-
330P_0402_50V8J
1 2
PR1141
1
267K_0402_1% PC1112
B B
PR1102 PR1137 150P_0402_50V8-J
2GFX_FB_1 1
PC1111
2.61K_0402_1% 10K_0402_5% 1 2 1 2
2
1
0.047U_0402_25V7K
2 @ 1 1 2
PR1142 PR1138
2 2
10K_0402_1%_TSM0A103F34D1RZ
0.1U_0402_25V6
1GFX_FB_3 1
PH1102
PC1119
@ 2 2
2
1
PC1117
2
1
GFX_VSUM+ PR1154
0_0402_5%
2 1
APU_VDDGFX_SEN_H 6
1
PR1139
PC1127 10_0402_1%
330P_0402_50V8J 2 1 +APU_GFX
2
+1.8VS
+1.8VS
1
PC1135 PR1151
1000P_0402_50V7K 10_0402_1%
2 1
2
PR1155
1
PC1160
.1U_0402_10V6-K
2
APU_GFX_SVC
@
APU_GFX_SVD
A A
PR1104 PR1105
220_0402_5% @ SVC SVD Boot Voltage
@
220_0402_5%
0 0 1.1V
2