Intel 100 MHZ Pentium (TM) Ii Processor/440Bx Agpset Dual Processor Customer Reference Schematics

A B C D E
Intel 100 MHz Pentium(tm) II processor/440BX AGPset Dual

Processor Customer Reference Schematics
4 Revision 1.0 4
TITLE PAGE
COVER SHEET 1
** Please note that these schematics are subject
BLOCK DIAGRAM 2
to change.
SLOT 1 CONNECTOR 3,4,5,6
THIS SCHEMATIC IS PROVIDED "AS IS" WITH NO WARRANTIES
CLK SYNTHESIZER 7
WHATSOEVER, INCLUDING ANY WARRANTY OF
82443BX 8,9,10 MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE,
FET SWITCHES 11,12 OR ANY WARRANTY OTHERWISE ARISING OUT OF PROPOSAL,
SPECIFICATION OR SAMPLE.
DIMM SOCKETS 13,14,15,16
3 PIIX4E 17.18 No license, express or implied, by estoppel or otherwise, 3
to any intellectual property rights is granted herein.
IOAPIC 19
ULTRA I/O 20 Intel disclaims all liability, including liability for infringement of
any proprietary rights, relating to use of information in this
AGP CONNECTOR 21
specification. Intel does not warrant or represent that such
PCI CONNECTORS 22,23 use will not infringe such rights.
ISA CONNECTORS 24
I2C is a two-wire communications bus/protocol developed
IDE CONNECTORS 25 by Philips. SMBus is a subset of the I2C bus/protocol and
USB CONNECTORS 26 was developed by Intel. Implementations of the I2C
bus/protocol or the SMBus bus/protocol may require
FLASH BIOS 27 licenses from various entities, including Philips Electronics
PARALLEL 28 N.V. and North American Philips Corporation.
2 2
SERIAL/FLOPPY 29
*Third-party brands and names are the property
KEYBOARD/MOUSE 30 of their respective owners.
VRM 31
POWER CONNECTOR 32 Copyright * Intel Corporation 1997, 1998
PROCESSOR BUS/CORE FREQ. 33

PCI/AGP PULL-UPS & PULL-DOWNS 34
ISA PULL-UPS 35
INTEL CORPORATION
82443BX/DRAM DECOUPLING 36
PLATFORM COMPONENTS DIVISION
BULK DECOUPLING 37 1900 PRAIRIE CITY RD. FM5-62
1 FOLSOM, CA 95630 1
TERMINATION DECOUPLING 38
Title
LM79 39 Intel Pentium(tm) II processor/440BX AGPset Dual Processor Cover Sheet
REVISION HISTORY 40 S ize Document Number Rev
Custom Intel(R) 440BX AGPset 1.0
Date: Thursday, April 09, 1998 Sheet 1 of 40

A B C D E
1 2 3 4 5 6 7 8
APIC BUS
THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT
BEEN VERIFIED FOR MANUFACTURING AN END USER
PRODUCT. iNTEL ISNOT RESPONSIBLE FOR THE MISUSE OF
VRM PENTIUM(tm) II PENTIUM(tm) II VRM THIS INFORMATION.
VTT GEN. Processor Processor VTT GEN.
PG. 31
(SLOT 1)
PG. 3,4
CK100 (SLOT 1)
PG. 5,6 PG. 31
A & DEVICE TABLE
A
MAX1617 ME ITP CON. MAX1617 ME
ADDR
CNTL
DATA
ADDR
CNTL
DATA
PG. 7
PG. 3 PG. 5 DEVICE REFERENCE PAGE #
TYPE DESIGNATOR
FUSES F1,F2,F3,F4 26,30
S Y S TEM BUS S Y S T EM BUS SMBus

SMBus Interface
Slot 1 Connectors J1A,B J2A,B 3,4,5,6
ADDR
CNTL
DATA
Interface ITP Connector J3
DIMM Sockets J4,J5,J6,J7 13,14,15,16
CNTL
M E M O RY AGP Connector J8 21
IOAPIC AGP 4 SDRAM DIMM PCI Connector J9,J10,J11,J12 22,23

MODULES
CONN. ADDR/DATA ISA Connector J13, J14 35
82093AA 82443BX ADDR
PG. 13-16
PG. 19 IDE Connector J15, J16 25

492 BGA
PG. 21
CNTL CKBF USB Connector J17,J18 26
PG. 8 VRM8.2 J25,J26 31
AGP SIDEBAND PG. 8-10 DATA
B B
BLM31A700S L1-L13 26,30
ADD/DATA
CNTL
CK100 U1 7
82443BX U2 - 1,2,3 8,9,10
PCI BUS CKBF U3 8
FET SWITCHES U4,5,6,7,8,9 11,12
(74CBT16212)
ADD/DATA
82371EB (PIIX4E) U10A,B 17,18

USB
USB
CNTL
2 USB CONN.
PG. 22-23
2 PCI IDE 74LVC14 3VSB U11A,B,C,D,E,F 18, 32, 33
PG. 26
CONNECTORS
82093AA (IOAPIC) U12 19
PCI CONN
PCI CONN
PCI CONN
PCI CONN
PG. 25
CNTL 74LVC125 3VSB U13A,B,C,D 19,35
IDE
SECONDARY
IDE
PRIMARY
CNTL FDC37C932FR U14 20

82371EB
324 BGA
(Ultra I/O)
74AS07 U15A,B,C,D,E,F 21,35
CONTROL ADDR/DATA
74HCT14 U16 A,B,C,D,E,F 27,32,35
PG. 17-18 ADDR/DATA
E28F002BC-T(FLASH) U17 27
C
INTERRUPTS 74ALS08 U20 A,B,C,D 32,35 C
CONTROL
ADDR
CNTL
DATA
74ALS05 U21 A,B,C,D,E,F 32,33,35

74HC10 5VSB U22 A,B,C 18,32
ISA BUS 74F07 U23A,B,C,D,E,F 32,33
74FCT3244 U24 33
LM79 U25 39
P G 35
ADDR
CNTL
DATA
ADDR
MAX 1617 ME U28,U29 3,5
ADDR
ISA CONN
ISA CONN
74HCT14 5VSB U30 18,35
FLASH DATA X-BUS 74HC112 U32 18
BPG.I O S 74F07 5VSB U36A,B,C,D,E,F 18, 32, 35
27
KEYBOARD
ULTRA I/O
PG.14 CNTL LT1575 VR1 31
PG. 30
LT1585 VR2 31
LM79 Crystal (14.318 MHz) Y1 7

MOUSE DATA
PG. 38
PG. 30
D D
SER.
FLOPPY PARA. CONN. INTEL CORPORATION
CONN. CONN.
PG. 29 PG. 28 PG .29 PG. 32 P L A T F O R M COMPONENTS DIVISION
RESET, POWER CONNECTORS 1 9 0 0 P R A I R I E CITY RD. FM5-62
SER. FOLSOM, CA 95630
CONN. PCI, AGP, & ISA RESISTORS PG. 34-35
Title
I n t e l 1 0 0 M H z P e n t i u m ( t m ) I I p r o c essor/440BX AGPset Block Dia gram
DECOUPLING CAPACITORS PG. 36-37
Size Document Number Rev
Custom 1.0
Intel(R) 440BX AGPset
Date: T hursday, April 09, 1998 Sheet 2 of 40
1 2 3 4 5 6 7 8
A B C D E
VTT
VCC3 V C C C O RE1 VTT

J1A
VCC3 B01 EMI VCC_VTT A01

4 B02 FLUSH# GND A02 4
5,34 F L U S H # B03 SMI# VCC_VTT A03
5,19 H S M I# B04 INIT# IERR# A04
C111 5 , 1 8,34 HINIT# B05 VCC_VTT A20M# A05 A20M# 5 , 33,34
R281 B06 STPCLK# GND A06
4 . 7K 5 , 1 8,34 STPCLK# B07 TCK FERR# A07
0.1 uF 7 TCK_1 F E R R# 5 , 1 8,34
U28 B08 SLP# IGNNE# A08 I G N N E # 5 , 33,34
5 , 1 8,34 SLP#
2
B09 VCC_VTT TDI A09 T D I_1 7
7 TMS_1
B10 TMS GND A10
V+
5,7 TRST#
15 B11 TRST# TDO A11 TDO_1 5 , 7
S T BY#
B12 RESERVED PWRGOOD A12 P W R G O O D 5 , 27,32
3 C198 B13 VCC_CORE TESTHI1 A13
D+ T E S THI 5,34
S M B SLAVE 4 2200pF B14 RESERVED GND A14
D-
A D D R ESS 6 B15 RESERVED THERMTRIP# A15 T H E RMTRIP# 5,34
ADD1
= 0011000b 10 B16 LINT[1] RESERVED A16
ADD0
B17 VCC_CORE LINT[0] A17
MAX1617 ME 5 , 33,34 LINT1
7 P I C CLK_P1
B18 PICCLK GND A18
LINT0 5,33,34
16p QSOP B19 BP#[2] PICD[0] A19 P I C D0 5 , 19,34

5 , 8 , 1 5,16,18,34,39 S M BDATA 12 B20 RESERVED PREQ# A20 ITPREQ#0 7
S M BDATA
5 , 7 ,16 100/66# B21 100/66# BP#[3] A21
5 , 8 , 1 5,16,18,34,39 SMBCLK 14 B22 PICD[1] GND A22
SMBCLK 5 , 19,34 P I C D 1
11 B23 PRDY# BPM#[0] A23
SMB_ALERT# 7 P R D Y #0
B24 BPM#[1] BINIT# A24
B25 VCC_CORE DEP#[0] A25
1 THERM# 5 , 18,34 B26 DEP#[2] GND A26
R E SV
5 B27 DEP#[4] DEP#[1] A27
R E SV
9 B28 DEP#[7] DEP#[3] A28
R E SV
3 13 B29 VCC_CORE DEP#[5] A29 3
R E SV
16 H D # 62 B30 D#[62] GND A30
R E SV
H D # 58 B31 D#[58] DEP#[6] A31
GND
GND
H D # 63 B32 D#[63] D#[61] A32 H D #61

B33 VCC_CORE D#[55] A33 H D #55
H D # 56 B34 D#[56] GND A34
7
MAX1617_2 B35 D#[50] D#[60] A35

H D # 50 H D #60
H D # 54 B36 D#[54] D#[53] A36 H D #53
B37 VCC_CORE D#[57] A37 H D #57
H D # 59 B38 D#[59] GND A38
H D # 48 B39 D#[48] D#[46] A39 H D #46
H D # 52 B40 D#[52] D#[49] A40 H D #49
B41 EMI D#[51] A41 H D #51
H D # 41 B42 D#[41] GND A42
H D # 47 B43 D#[47] D#[42] A43 H D #42
H D # 44 B44 D#[44] D#[45] A44 H D #45
B45 VCC_CORE D#[39] A45 H D #39
H D # 36 B46 D#[36] GND A46
H D # 40 B47 D#[40] RESERVED A47
H D # 34 B48 D#[34] D#[43] A48 H D #43
B49 VCC_CORE D#[37] A49 H D #37
H D #38 B50 D#[38] GND A50
H D #32 B51 D#[32] D#[33] A51 H D #33
H D #28 B52 D#[28] D#[35] A52 H D #35
B53 VCC_CORE D#[31] A53 H D #31
H D #29 B54 D#[29] GND A54
H D #26 B55 D#[26] D#[30] A55 H D #30
2 H D #25 B56 D#[25] D#[27] A56 H D #27 2
B57 VCC_CORE D#[24] A57 H D #24
H D # 22 B58 D#[22] GND A58
H D # 19 B59 D#[19] D#[23] A59 H D #23
H D # 18 B60 D#[18] D#[21] A60 H D #21
B61 EMI D#[16] A61 H D #16
H D # 20 B62 D#[20] GND A62
H D #17 B63 D#[17] D#[13] A63 H D #13
H D # 15 B64 D#[15] D#[11] A64 H D #11
B65 VCC_CORE D#[10] A65 H D #10
H D # 12 B66 D#[12] GND A66
HD#7 B67 D#[7] D#[14] A67 H D #14
HD#6 B68 D#[6] D#[9] A68 HD#9
B69 VCC_CORE D#[8] A69 HD#8
HD#4 B70 D#[4] GND A70
HD#2 B71 D#[2] D#[5] A71 HD#5
HD#0 B72 D#[0] D#[3] A72 HD#3
EMI_PD3
EMI_PD2
EMI_PD1
SLOT1_0.8
SLOT 1a
5,10 H D # [ 6 3 : 0]
1 1
R1 R2 R3 I N T E L C O R P O RATION
0 0 0 P L A T F O R M C O M P O NENTS DIVISION
1 9 0 0 P R A I R I E C I T Y RD. FM5-62
F O L S OM, CA 95630
Title
* Please place as close to the connector as possible F I R S T S L O T 1 (PART I)

D a t e : Thursday, April 09, 1998 Sheet 3 of 40

A B C D E
A B C D E
V C C C O RE1
VCC VCC3
4 4
J1B
6 , 7,8 H R E SET# B74 RESET# GND A74

6 BREQ1# B75 BREQ1# BCLK A75 C P U H C LK1 7
B76 FRCERR# BREQ0# A76 BREQ0# 6 , 8
B77 VCC_CORE BERR# A77
B78 A#[35] GND A78
B79 A#[32] A#[33] A79
H A # 29 B80 A#[29] A#[34] A80
B81 EMI A#[30] A81 H A # 30
H A # 26 B82 A#[26] GND A82
H A # 24 B83 A#[24] A#[31] A83 H A # 31
H A # 28 B84 A#[28] A#[27] A84 H A # 27
B85 VCC_CORE A#[22] A85 H A # 22
HA#20 B86 A#[20] GND A86
H A # 21 B87 A#[21] A#[23] A87 H A # 23
H A # 25 B88 A#[25] RESERVED A88
B89 VCC_CORE A#[19] A89 H A # 19
HA#15 B90 A#[15] GND A90
HA#17 B91 A#[17] A#[18] A91 H A # 18
HA#11 B92 A#[11] A#[16] A92 H A # 16
B93 VCC_CORE A#[13] A93 H A # 13
H A # 12 B94 A#[12] GND A94
HA#8 B95 A#[8] A#[14] A95 H A # 14
HA#7 B96 A#[7] A#[10] A96 H A # 10
B97 VCC_CORE A#[5] A97 HA#5
3 HA#3 B98 A#[3] GND A98 3
HA#6 B99 A#[6] A#[9] A99 HA#9
B100 EMI A#[4] A100 HA#4
3 2 ,34 A _ SLOTOCC# B101 SLOTOCC# BNR# A101
BNR# 6,8
H R E Q#0 B102 REQ#[0] GND A102
H R E Q#1 B103 REQ#[1] BPRI# A103 B P RI# 6 , 8
H R E Q#4 B104 REQ#[4] TRDY# A104 HTRDY# 6,8
B105 VCC_CORE DEFER# A105 D E F ER# 6 , 8
B106 LOCK# GND A106
6,8 H L O CK#
B107 DRDY# REQ#[2] A107 H R E Q#2
6,8 D R D Y #
B108 RS#[0] REQ#[3] A108 H R E Q#3
6,8 RS#0
B109 VCC_5 HITM# A109 HITM# 6 , 8
B110 HIT# GND A110
6,8 HIT#
B111 RS#[2] DBSY# A111 D B S Y# 6 , 8
6,8 RS#2
B112 RESERVED RS#[1] A112 RS#1 6 , 8
B113 VCC_3 RESERVED A113
B114 RP# GND A114
B115 RSP# ADS# A115 A D S# 6 , 8
B116 AP#[1] RESERVED A116
B117 VCC_3 AP#[0] A117
B118 AERR# GND A118
V I D _ A3 R 4 0 VA3 B119 VID[3] VID[2] A119 VA2 R5 0 V I D _ A2
V I D _ A0 R 6 0 VA0 B120 VID[0] VID[1] A120 VA1 R7 0 V I D _ A1
B121 VCC_3 VID[4] A121 VA4 R8 0 V I D _ A4
SLOT1_0.8
2 SLOT 1b 2
6 , 8 H A # [ 3 1 : 3]
6 , 8 H R E Q # [ 4 :0]
31 VID_A[4:0]
EMI_PD5
EMI_PD4
VCC
JP1 1 S E L _VID_A0 R9
V I D _ A0 2 8 . 2K
3
* Please place as close to the R10 R11
c o n n ector as possible 0 0 JP2 1 S E L _VID_A1 R12 VRM optional override
V I D _ A1 2 8 . 2K jumpers & resistors
3
Jumper position 1-2 is
JP3 R13
1 S E L _VID_A2 s t u f f e d a s the default. To
V I D _ A2 2
3
8 . 2K override, R4-R8 must be
removed.
JP4 1 S E L _VID_A3 R14
1 1
V I D _ A3 2 I N T E L C O R P O RATION
8 . 2K
3
P L A T F O R M C O M P O NENTS DIVISION
JP5 1 S E L _VID_A4 R15 F O L S OM, CA 95630
V I D _ A4 2 8 . 2K
3 Title
F I R S T S L O T 1 (PART II)


A B C D E
A B C D E
VTT
V C C C ORE2 VTT
VCC3 J2A
B01 EMI VCC_VTT A01

4 VCC3 B02 FLUSH# GND A02 4
3,34 F L U S H# B03 SMI# VCC_VTT A03
3,19 H S M I# B04 INIT# IERR# A04
3 , 18,34 HINIT# B05 VCC_VTT A20M# A05 A20M# 3 , 33,34
C112 B06 STPCLK# GND A06
R282 3 , 18,34 STPCLK# B07 TCK FERR# A07
4.7K 7 TCK_2 F E R R # 3 , 18,34
0.1 uF B08 SLP# IGNNE# A08 I G N N E # 3 ,33,34
3 , 18,34 SLP#
U29 B09 VCC_VTT TDI A09 TDO_1 3 , 7
7 TMS_2
2
B10 TMS GND A10
3 , 7 TRST#
B11 TRST# TDO A11
V+
TDO_2 7
15 B12 RESERVED PWRGOOD A12 P W RGOOD 3 , 27,32
S T BY# C199 B13 VCC_CORE TESTHI1 A13 T E S T HI 3 , 34
3 2200pF B14 RESERVED GND A14
D+
4 B15 RESERVED THERMTRIP# A15 T H E R MTRIP# 3,34
SMB SLAVE D-
6 B16 LINT[1] RESERVED A16
ADD1
A D D RESS 10 3 , 3 3,34 LINT1 B17 VCC_CORE LINT[0] A17 LINT0 3 , 3 3,34
ADD0
B18 PICCLK GND A18
= 0011010b
MAX1617 ME 7 P I CCLK_P2
B19 BP#[2] PICD[0] A19 P I C D 0 3 , 19,34
16p QSOP B20 RESERVED PREQ# A20 ITPREQ#1 7
3 , 8 , 1 5,16,18,34,39 S M BDATA 12 B21 100/66# BP#[3] A21
S M BDATA 3 , 7 ,16 100/66#
B22 PICD[1] GND A22
3 , 19,34 P I C D1
3 , 8 , 1 5,16,18,34,39 SMBCLK 14 B23 PRDY# BPM#[0] A23
SMBCLK 7 P R D Y #1
11 B24 BPM#[1] BINIT# A24
SMB_ALERT#
B25 VCC_CORE DEP#[0] A25
B26 DEP#[2] GND A26
1 THERM# 3 , 18,34 B27 DEP#[4] DEP#[1] A27
R E SV
5 B28 DEP#[7] DEP#[3] A28
R E SV
3 9 B29 VCC_CORE DEP#[5] A29 3
R E SV
13 H D # 62 B30 D#[62] GND A30
R E SV
16 H D # 58 B31 D#[58] DEP#[6] A31
R E SV
H D # 63 B32 D#[63] D#[61] A32 H D # 61
GND
GND
B33 VCC_CORE D#[55] A33 H D # 55

H D # 56 B34 D#[56] GND A34
H D # 50 B35 D#[50] D#[60] A35 H D # 60
7
MAX1617_2 B36 D#[54] D#[53] A36

H D # 54 H D # 53
B37 VCC_CORE D#[57] A37 H D # 57
H D # 59 B38 D#[59] GND A38
H D # 48 B39 D#[48] D#[46] A39 H D # 46
H D # 52 B40 D#[52] D#[49] A40 H D # 49
B41 EMI D#[51] A41 H D # 51
H D # 41 B42 D#[41] GND A42
H D # 47 B43 D#[47] D#[42] A43 H D # 42
H D # 44 B44 D#[44] D#[45] A44 H D # 45
B45 VCC_CORE D#[39] A45 H D # 39
H D # 36 B46 D#[36] GND A46
H D # 40 B47 D#[40] RESERVED A47
H D # 34 B48 D#[34] D#[43] A48 H D # 43
B49 VCC_CORE D#[37] A49 H D # 37
H D # 38 B50 D#[38] GND A50
H D # 32 B51 D#[32] D#[33] A51 H D # 33
H D # 28 B52 D#[28] D#[35] A52 H D # 35
B53 VCC_CORE D#[31] A53 H D # 31
H D # 29 B54 D#[29] GND A54
H D # 26 B55 D#[26] D#[30] A55 H D # 30
2 H D # 25 B56 D#[25] D#[27] A56 H D # 27 2
B57 VCC_CORE D#[24] A57 H D # 24
H D # 22 B58 D#[22] GND A58
H D # 19 B59 D#[19] D#[23] A59 H D # 23
H D # 18 B60 D#[18] D#[21] A60 H D # 21
B61 EMI D#[16] A61 H D # 16
H D # 20 B62 D#[20] GND A62
H D # 17 B63 D#[17] D#[13] A63 H D # 13
H D # 15 B64 D#[15] D#[11] A64 H D # 11
B65 VCC_CORE D#[10] A65 H D # 10
H D # 12 B66 D#[12] GND A66
HD#7 B67 D#[7] D#[14] A67 H D # 14
HD#6 B68 D#[6] D#[9] A68 HD#9
HD#4 B70 D#[4] GND A70
HD#2 B71 D#[2] D#[5] A71 HD#5
HD#0 B72 D#[0] D#[3] A72 HD#3
EMI_PD8
EMI_PD7
EMI_PD6
SLOT1_0.8
SLOT 1a
3,10 H D # [ 6 3 : 0]
1 1
R16 R17 R18 I N T E L C O R P O RATION
0 0 0 P L A T F O R M C O M P O NENTS DIVISION
Title
* P lease place as close to the connector as possible S E C O N D S L O T 1 (PART I)


A B C D E
A B C D E
V C C C O RE2
VCC VCC3
4 4
J2B
4 , 7,8 H R E SET# B74 RESET# GND A74

4 , 8 BREQ0# B75 BREQ1# BCLK A75 C P U H C LK2 7
B76 FRCERR# BREQ0# A76 BREQ1# 4
B77 VCC_CORE BERR# A77
B78 A#[35] GND A78
B79 A#[32] A#[33] A79
H A # 29 B80 A#[29] A#[34] A80
B81 EMI A#[30] A81 H A # 30
H A # 26 B82 A#[26] GND A82
H A # 24 B83 A#[24] A#[31] A83 H A # 31
H A # 28 B84 A#[28] A#[27] A84 H A # 27
B85 VCC_CORE A#[22] A85 H A # 22
HA#20 B86 A#[20] GND A86
H A # 21 B87 A#[21] A#[23] A87 H A # 23
H A # 25 B88 A#[25] RESERVED A88
B89 VCC_CORE A#[19] A89 H A # 19
HA#15 B90 A#[15] GND A90
HA#17 B91 A#[17] A#[18] A91 H A # 18
HA#11 B92 A#[11] A#[16] A92 H A # 16
B93 VCC_CORE A#[13] A93 H A # 13
H A # 12 B94 A#[12] GND A94
HA#8 B95 A#[8] A#[14] A95 H A # 14
HA#7 B96 A#[7] A#[10] A96 H A # 10
B97 VCC_CORE A#[5] A97 HA#5
3 HA#3 B98 A#[3] GND A98 3
HA#6 B99 A#[6] A#[9] A99 HA#9
B100 EMI A#[4] A100 HA#4
3 2 ,34 B_SLOTOCC# B101 SLOTOCC# BNR# A101
BNR# 4,8
H R E Q#0 B102 REQ#[0] GND A102
H R E Q#1 B103 REQ#[1] BPRI# A103 B P RI# 4 , 8
H R E Q#4 B104 REQ#[4] TRDY# A104 HTRDY# 4,8
B105 VCC_CORE DEFER# A105 D E F ER# 4 , 8
B106 LOCK# GND A106
4,8 H L O CK#
B107 DRDY# REQ#[2] A107 H R E Q#2
4,8 D R D Y #
B108 RS#[0] REQ#[3] A108 H R E Q#3
4,8 RS#0
B109 VCC_5 HITM# A109 HITM# 4 , 8
B110 HIT# GND A110
4,8 HIT#
B111 RS#[2] DBSY# A111 D B S Y# 4 , 8
4,8 RS#2
B112 RESERVED RS#[1] A112 RS#1 4 , 8
B113 VCC_3 RESERVED A113
B114 RP# GND A114
B115 RSP# ADS# A115 A D S# 4 , 8
B116 AP#[1] RESERVED A116
B117 VCC_3 AP#[0] A117
B118 AERR# GND A118
VID_B3 R19 0 VB3 B119 VID[3] VID[2] A119 VB2 R20 0 VID_B2
VID_B0 R21 0 VB0 B120 VID[0] VID[1] A120 VB1 R22 0 VID_B1
B121 VCC_3 VID[4] A121 VB4 R23 0 VID_B4
SLOT1_0.8
2 SLOT 1b 2
4 , 8 H A # [ 3 1 : 3]
4 , 8 H R E Q # [ 4 :0]
31 V I D _ B [ 4 :0]
EMI_PD10
EMI_PD9
VCC
JP6 1 S E L_VID_B0 R24
VID_B0 2 8 . 2K
3
* Please place as close to R25 R26
the connector as possible 0 0 JP7 1 S E L_VID_B1 R27 VRM optional override
VID_B1 2 8 . 2K jumpers & resistors
3
Jumper position 1-2 is
JP8 R28
1 S E L_VID_B2 s t u f f e d a s the default. To
VID_B2 2
3
8 . 2K override, R19-R23 must
be removed.
JP9 1 S E L_VID_B3 R29
1 1
VID_B3 2 I N T E L C O R P O RATION
8 . 2K
3
JP10 1 S E L_VID_B4 R30 F O L S OM, CA 95630
VID_B4 2 8 . 2K
3 Title
S E C O N D S L O T 1 (PART II)


A B C D E
A B C D E
VCC3 CLOCK SYNTHESIZER L14

VCC2.5
1 L15 2 2 1
FBHS01L
FBHS01L
CD85 CD86 CD87 CD88 CD89 CD90 C168
+
0.01 uF 0.01 uF 0.01uF 100pF 100pF 100pF C172 C173 C174 C175 C176 C177
16V 16V 16V 16V 16V 16V 22uF +
100pF 1 0 0 pF 0.01uF 0.01uF 0.01uF
4 16V 16V 16V 16V 16V 22uF 4
VCC3
15
19
21
33
48
46
41
37
U1
9
VCC3 VCC3
R31
VDDCORE0
VDDQREF
V D D 4 8 M HZ
V D D A P IC
V D D C O RE1
V D D P C I0
V D D P C I1
VDDCPU0
VDDCPU1
*NOTE* Override to 200 40 R32 22 * N O T E * F o r p o w e r m a naged systems, the PIIX4 must be
CPUCLK0 CPUHCLK1 4
39 R33 22
66MHz only. CPUCLK1 CPUHCLK2 6 c o n n e c t e d t PCICLK_F of the CKE100 which is a free
36 R34 22
CPUCLK2 BXHCLK 8
CPUCLK3
35 R35 22 r u n n i ng PCLK not affected by the assertion of
I T P C LK
4 7 R36 22 PCISTOP#.
X T A LIN PCICLK_F P X P CLK 1 8
8 R37 22 STUFFING OPTION
PCICLK_1 P C L K 1 22
R38 R39 R40 R283 R284 R285 10 R41 22
PCICLK_2 P C L K 2 22
JP11 8.2K 8.2K 8.2K 10K 10K 10K 11 R42 22 * N O T E* 10-15 pF caps to ground may be
5 CK100 PCICLK_3 13 R43 22
P C L K 3 23
P C L K 4 23
XTALOUT PCICLK_4 14 R44 22 desirable to reduce the effects of EMI.
PCICLK_5 B X P CLK 9
42 16 R45 22
RESV PCICLK_6 PCLKAPIC 19 R46
28 17
RESV PCICLK_7 P I C C L K _ P1 3
R47 10
27 22 22
S E L0 48MHZ_0 4 8 M h z_0 1 8
26 23
25 S E L1 48MHZ_1
3 , 5 , 1 6 1 0 0 / 6 6# S E L _ 1 0 0 /66# 45 R48 22
APICCLK_0 APICCLK 19 R50
44 HPICCLK P I C C L K _ P2 5
R381 31 APICCLK_1
1 8 P C I _ S T P# P C I _ S TP# R51 10
30 1 22
0 C P U _ S T P# REF0 OSC1 24
29 2 R52 22
R382 PWRDWN# REF1 OSC2 18
47 R53 22
VSSCORE1
3 18 CPU_STP# OSC3 20 3
V S S CORE0
VSS48MHZ
Y1 REF2
V S S C PU0
V S S C PU1
VSSAPIC
0
VSSPCI1
VSSPCI2
V S S PCI0
VSSREF
R383
18 SUSA#
0 14.318MHz
3
6
12
18
20
24
32
38
34
43
R54 C1 C2 C K 1 0 0 _05
DO NOT STUFF
0 10pF 10pF
Stuffing option to enable the
stopping of the CPUCLKs,
PCICLKs, and the powerdown of
the CK100. Please note that the
resistors are not stuffed. VCC2.5 VTT
Stuffing option to enable Spread#
function for possible EMI reduction. VCC2.5 VTT VTT
R55 R56 R57

1K
OPTIONAL ITP
R58 R59
1K 1K
5% TEST R61 56 56
R60
CONNECTOR 330 R63
J3 330
4,6,8 H R E S E T #
240 I T P _RST
1 2
3 2 D B R E S ET# 3 4
2 2
3 T C K _1 5 6
R64 47 7 8
9 10
5 T C K _2 11 12 T R ST# 3 , 5
R65 47 13 14
15 16 I T P R E Q#0 3
3 T M S_1 17 18 R_PRDY0 PRDY#0 3
47 R67 240
R66 19 20
21 22 R_PRDY1 I T P R E Q#1 5
5 T M S_2 R68 240 PRDY#1 5
23 24
R69 47 25 26
27 28
I T P C LK R70
29 30 VCC2.5 VCC2.5
ITP CONN 680
ITP_JMP CONFIG R73

R71 R72
150 150 330
TDO_JMP TDI_JMP CPU JP13
JP12
JP12 JP13 CONFIG 3 , 5 T D O _1 1 1 TDI_1 3
2 2
3 3
5 T D O _2
1-2 1-2 SINGLE CPU1 T D O _ J MP
TDI_JMP
1
2-3 1-2 DUAL CPU 1
INTEL CORPORATION
2-3 2-3 SINGLE CPU2 PLATFORM COMPONENTS DIVISION
1900 PRAIRIE CITY RD. FM5-62
FOLSOM, CA 95630
Title
CLOCK SYNTHESIZER


A B C D E
A B C D E
VCC3
AA18
AA20
G21
AA7
AA9
Y21
V21
F18
F20
4,6 H A # [ 3 1 : 3]
J21
G6
F7
F9
J6
U2-1 M A A [ 1 3:0] 1 3 ,14
HA#3 G25 AF17 MAA0
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
HA3# MAA0
HA#4 H22 AB16 MAA1
HA4# MAA1
HA#5 G23 AE17 MAA2
HA5# MAA2
HA#6 H23 AC17 MAA3
HA6# MAA3
HA#7 G24 AF18 MAA4
HA7# MAA4
HA#8 F26 AE19 MAA5
HA8# MAA5
4 HA#9 G26 AF19 MAA6 4
HA9# MAA6
H A # 10 G22 AC18 MAA7
H A 1 0# MAA7
H A # 11 F22 AC19 MAA8
H A 1 1# MAA8
H A # 12 F23 AE20 MAA9
H A 1 2# MAA9
H A # 13 F24 AD20 MAA10
H A 1 3# MAA10
H A # 14 F25 AF21 MAA11
H A 1 4# MAA11
H A # 15 E23 AC21 MAA12
H A 1 5# MAA12
H A # 16 E26 AF25 MAA13 M A B #[13:0] 15,16
H A 1 6# MAA13
H A # 17 E25
H A 1 7#
H A # 18
H A # 19
D25
D26
H A 1 8# 82443BX MAB0#
AD16
AC16
MAB#0
MAB#1
H A 1 9# MAB1#
H A # 20 B25 AD17 MAB#2
H A 2 0# MAB2#
H A # 21 C26
H A 2 1# 492 BGA MAB3#
AB17 MAB#3
H A # 22 A25 AE18 MAB#4
H A 2 2# MAB4#
H A # 23 C25 AD19 MAB#5
H A 2 3# MAB5#
H A # 24 A24 AB18 MAB#6
H A 2 4# MAB6# L16 VCC3
H A # 25 D24 AB19 MAB#7
H A 2 5# MAB7#
SYSTEM INTERFACE
H A # 26 C23 AF20 MAB#8 2 1
H A 2 6# MAB8#
H A # 27 B24 AC20 MAB#9
H A 2 7# MAB9#
H A # 28 C24 AB20 MAB10 F B H S01L
H A 2 8# MAB10
H A # 29 A23 AE21 MAB#11
H A 2 9# MAB11#
H A # 30 E22 AD21 MAB#12
DRAM INTERFACE
H A 3 0# MAB12# 100pF C183
H A # 31 D23 AF22 MAB13 C S _ A # [1:0] 13
H A 3 1# MAB13
. 0 1 uF C184
4 , 6 ,7 H R E SET# B23 AB14 CS_A#0 C S _ A # [3:2] 14
C P U R ST# CSA0#
4,6 ADS# K21 AF15 CS_A#1 100pF
A D S# CSA1# C185
4,6 BNR# H24 AE15 CS_A#2 C S _ A # [5:4] 15
BNR# CSA2#
3 4,6 B P R I# H26 AC15 CS_A#3 . 0 1 uF 3
B P R I# CSA3# C186
AD15 CS_A#4 C S _ A # [7:6] 16
CSA4#
4,6 DBSY# L23 AE16 CS_A#5 100pF
D B S Y# CSA5# C187
4,6 D E F ER# J26 AE24 CS_A#6
D E F ER# CKE2/CSA6#
4,6 DRDY# K23 AD23 CS_A#7 C S _ B #[1:0] 13 . 0 1 uF
DRDY# CKE3/CSA7# C188
4,6 HIT# L24
HIT#
4,6 HITM# L22 AE25 CS_B#0 C S _ B #[3:2] 14 100pF
HITM# CSB0# C189
4,6 H L O CK# K22 AD24 CS_B#1
H L O CK# CSB1#
4,6 HTRDY# H25 AD26 CS_B#2 C S _ B #[5:4] 15 . 0 1 uF
HTRDY# CSB2# C190
4,6 BREQ0# B26 AC24 CS_B#3
BREQ0# CSB3#
AC26 CS_B#4 C S _ B #[7:6] 16 100pF
CSB4# C191
RS#0 K26 AB23 CS_B#5
RS#0 CSB5#
RS#1 L26 AC23 CS_B#6 . 0 1 uF
RS#1 CKE4/CSB6# C192
RS#2 L25 AF24 CS_B#7 D Q M A [ 7:0] 1 3 ,14,15,16
RS#2 CKE5/CSB7#
2 2 uF
+
J22 AD13 DQMA0 C193
4 , 6 R S # [ 2 :0] H R E Q#0 H R E Q#0 DQMA0
H R E Q#1 J23 AC13 DQMA1 VCC3
H R E Q#1 DQMA1
H R E Q#2 K24 AC25 DQMA2
H R E Q#2 DQMA2
H R E Q#3 K25 AB26 DQMA3
VCC3 H R E Q#3 DQMA3
H R E Q#4 J25 AE14 DQMA4 D C L K [ 1 5:0] 1 3 , 14,15,16
H R E Q#4 DQMA4 R74
AC14 DQMA5
23
12
16
20
29
33
37
42
46
DQMA5 U3
3
7
AA22 DQMA6 4.7k
DQMA6
AA24 DQMA7
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
4,6 H R E Q # [ 4 :0]
VDDIIC
R75 DQMA7
**PLEASE NOTE**
8 . 2K AE13 DQMB1 4 R76 0 D C LK10
DQMB1 DQMB1 15,16 SDRAM0 These clock
N23 AD14 DQMB5 5 R77 0 D C LK11
7 BXHCLK HCLKIN DQMB5 DQMB5 15,16 SDRAM1
F E N A 11,12 SDRAM2
8 R78 0 D C LK6 assignments may
M25 AC22 9 R79 0 D C LK7
2
33 C R ESET# CRESET# M26
T E S TIN#
CRESET#
CKE0/FENA
CKE1/GCKE
AF23
G C KE 10
38
OE
CKBF SDRAM3
SDRAM4
13 R80 0 D C LK0
not be optimum. 2
**On 4-DIMM solutions that don't support 14 R81 0 D C LK1

s e l f -refresh mode, GCKE should be N/C. R398 47 SDRAM5 R82 0
1 7 ,21,22,23 P C I RST# A3 11 17 D C LK14
P C I RST# BUF_IN SDRAM6 R83 0
AF16 S R A S_A# 13,14 18 D C LK15
SRAS_A# SDRAM7 R84 0
AA17 S R AS_B# 15,16 25 31 D C LK13
SRAS_B# SCLOCK SDRAM8 R85 0
AF12 S C A S_A# 13,14 24 32 D C LK12
SCAS_A# S D ATA SDRAM9 R86 0
**TESTIN# pullup may be SCAS_B#
AB13 S C AS_B# 15,16 SDRAM10
35
R87 0
D C LK3
36 D C LK2
removed after validation SDRAM11 R88 0
AE12 W E _ A # 13,14 1 40 D C LK5
WE_A# R E SV SDRAM12 R89 0
h a s been completed. AE22 AC12 W E _ B# 15,16 2 41 D C LK4
R E S VA WE_B# R E SV SDRAM13 R90 0
AE23 47 44 D C LK9
R E SVB R E SV SDRAM14
P22 A B 2 1 R399 22 48 45 R92 0 D C LK8
R E S VC DCLKO R E SV SDRAM15 R93 0
AD25 21 D C L K REF
DCLKWR SDRAM16 R385 0
AB22 28
VSSIIC
DCLKRD SDRAM17 S R CLK 10
D C L K REF
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
*The unused SDRAM clocks
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
26
6
10
15
19
22
27
30
34
39
43
CKBF m a y be disabled using the
C3
S M B u s interface.
2 0 pF slave address =
A1
H6
A14
A26
H21
J3
J24
E12
E15
E24
F6
F8
F19
F21
C5
C9
C18
C22
E3
443BX_10
1101001b
* * L o cate R398 close to CKBF and SMBCLK 3 , 5 , 1 5,16,18,34,39

R399 close to 443BX. S M BDATA 3 , 5 , 1 5,16,18,34,39
1 1
**Locate "T" and cap close to BX. I N T E L C O R P O RATION
** Please make DCLKREF trace length equal to 2.5" more P L A T F O R M C O M P O NENTS DIVISION
than the DCLK outputs to the DIMMs. DCLK outputs to F O L S OM, CA 95630
the DIMMs should all be the same recommended length. Title
8 2 4 4 3 B X S Y S T E M AND DRAM INTERFACES
E x a m ple: if DCLK[0-11] = 2.5" Size Document Number Rev
then DCLKREF = 2.5" + 2.5". Custom Intel(R) 440BX AGPset 1.0

A B C D E
A B C D E
VCC3
M12
M15
AE1
R12
R15
N11
N16
N26
P11
P16
T11
T13
T14
T16
L11
L13
L14
L16
P1
Y6
V6
1 7 ,22,23 A D [ 3 1 : 0] U 2 -2 G A D [ 3 1 :0] 21
AD0 K6 AB5 G A D0
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
AD0 GAD0
AD1 K2 AE2 G A D1
AD1 GAD1
4 AD2 K4 AD3 G A D2 4
AD2 GAD2
AD3 K3 AD2 G A D3
AD3 GAD3
AD4 K5 AD1 G A D4
AD4 GAD4
AD5 J1 AC3 G A D5
AD5 GAD5
AD6 J2 AC1 G A D6
AD6 GAD6
AD7 H2 AB4 G A D7
AD7 GAD7
AD8 H1 AB1 G A D8
AD8 GAD8
AD9 J5 AA5 G A D9
AD9 GAD9
A D 10 H3 AA3 G A D10
A D 10 GAD10
A D 11 H5 AA4 G A D11
A D 11 GAD11
A D 12 H4 AA2 G A D12
A D 12 GAD12
A D 13 G1 AA1 G A D13
A D 13 GAD13
A D 14 G2 Y5 G A D14
A D 14 GAD14
A D 15 G4 Y3 G A D15
A D 15 GAD15
A D 16
A D 17
D1
D3
A D 16 82443BX GAD16
W1
V2
G A D16
G A D17
A D 17 GAD17
A D 18 D2 W2 G A D18
A D 19 C1
A D 18 492 BGA GAD18
U5 G A D19
A D 19 GAD19
A D 20 A2 V1 G A D20
A D 20 GAD20
A D 21 C3 U4 G A D21
A D 21 GAD21
A D 22 B3 U3 G A D22
A D 22 GAD22
A D 23 D4 U1 G A D23
A D 23 GAD23
A D 24 E5 T3 G A D24
A D 24 GAD24
A D 25 A4 T4 G A D25
A D 25 GAD25
P C I INTERFACE
A D 26 D5 T2 G A D26
A D 26 GAD26
A D 27 B4 T1 G A D27
A D 27 GAD27
A D 28 B5 U6 G A D28
A D 28 GAD28
3 A D 29 A5 R3 G A D29 3
A D 29 GAD29
A D 30 E6 R4 G A D30
A D 30 GAD30
1 7 ,22,23 C / B E # [ 3:0] A D 31 C6 R2 G A D31 G C / B E # [3:0] 21
A D 31 GAD31
AGP INTERFACE
C / BE#0 J4 AB2 GCBE#0
C / BE0# GC/BE0#
C / BE#1 G3 Y4 GCBE#1
C / BE1# GC/BE1#
C / BE#2 E4 V4 GCBE#2
C / BE2# GC/BE2#
C / BE#3 C4 U2 GCBE#3
C / BE3# GC/BE3#
1 7 , 22,23,34 F R AME# E2 W3 G F RAME# 21,34

FRAME# GFRAME#
1 7 , 22,23,34 D E VSEL# F3 W5 G D EVSEL# 2 1 ,34
DEVSEL# GDEVSEL#
1 7 , 22,23,34 IRDY# E1 V5 G I R D Y # 21,34
IRDY# GIRDY#
1 7 , 22,23,34 TRDY# F5 W4 G T R D Y# 21,34
TRDY# GTRDY#
1 7 , 22,23,34 STOP# F4 Y1 GSTOP# 21,34
STOP# GSTOP#
17,22,23 PAR G5 Y2 G P A R 21,34
PAR GPAR
1 7 , 22,23,34 S E RR# F1
VCC3 S E RR#
22,23,34 PLOCK# F2 L5 G R EQ# 21,34
PLOCK# GREQ#
L3 G G N T# 21,34
GGNT#
17,34 P H L D# B6
R95 P H OLD# R97
D6 P5
10K
17,34 P H L D A#
AE3
P H L DA# GCLKOUT
N5 R98 G C L KOUT 21 ** Note** Please make the
19 W S C # WSC# GCLKIN 22
GCLKIN trace length 3.3"
P C I ARB & PWR MGT
1 7 , 22,23,34 P R E Q #[3:0] 22
PREQ#0 A6
P R E Q0#/IOREQ# PIPE#
M3 P I PE# 21,34 more than the GCLKOUT
PREQ#1 C7 K1 SBA0
PREQ#2 F10
PREQ1#
PREQ2#
SBA0
SBA1
M2 SBA1 recommended trace length.
PREQ#3 D8 M1 SBA2
2 34 PREQ#4 PREQ#4 D10
PREQ3# SBA2
N2 SBA3 Stub to tee should be 1" 2
R400 PREQ4# SBA3
18 S U STAT# AD4
S U STAT# SBA4
P2
P4
SBA4
SBA5
MAX.
0 2 2 ,23,34 P G N T # [ 3:0] SBA5
PGNT#0 E7 P3 SBA6
P G N T 0 #/IOGNT# SBA6
PGNT#1 D7 R1 SBA7
PGNT1# SBA7
DO NOT STUFF PGNT#2 E10
PGNT2# S B A [ 7 :0] 21
PGNT#3 E8 M4 R B F# 21,34
PGNT3# RBF#
S t u f fing option to enable and test 34 PGNT#4 PGNT#4 E9
PGNT4#
AF3 L4 ST0 VCC3
the POS state. 18,32 P W R O K
AC4
BX-PWROK ST0
L2 ST1
C L K R U N# ST1
C2 L1 ST2
18 V R E F 5V R E F V CC5 ST2
B2 S T [ 2 :0] 21
7 BXPCLK P C L K IN R99
GADSTB-A
AC2 A D S T B-A 21,34 150
**NOTE: It is
T5 A D S TB-B 21,34
GADSTB-B
N3 1% recommended
SB-STB SBSTB 21,34
that the tolerance
R294 N4
AGPREFV on these
resistors be 1%
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
100 R101
C5 100 in order to meet
**NOTE** Locate 0 . 001uF 1% the margins of
circuitry close to
N1
V3
N12
N13
N14
N15
T12
T15
V24
L12
L15
M11
M13
M14
M16
M22
P12
P13
P14
P15
P26
R5
R11
R13
R14
R16
R22
M5
W21
W6
443BX
443BX. this reference
voltage.
1 1
I N T E L C O R P O RATION
Title
8 2 4 4 3 B X P C I A N D AGP INTERFACES


A B C D E
A B C D E
VCC3
H D # [ 6 3 : 0] 3,5
AE26
AF14
N22
AF2
B1
11,12 M D [ 6 3:0] U2-3
MD0 AF4 B22 HD#0
VDD
VDD
VDD
VDD
VDD
MD0 HD0#
MD1 AE4 D22 HD#1
MD1 HD1#
MD2 AF5 E21 HD#2
MD2 HD2#
MD3 AD6 A22 HD#3
MD3 HD3#
MD4 AE6 D21 HD#4
MD4 HD4#
MD5 AB7 C21 HD#5
MD5 HD5# U33
MD6 AC7 A21 HD#6 4 . 7K
MD6 HD6# R386
4 MD7 AF7 C20 HD#7 1 4
MD7 HD7# 1EN
MD8 AB8 B21 HD#8 8 S R CLK 48
MD8 HD8# C1
MD9 AB9
MD9 HD9#
E20 HD#9 24
2EN **NOTE** The trace
MD10 AC9 A20 H D # 10 25
MD11 AE9
MD10 HD10#
E19 H D # 11 R396 4.7K C2 lengths of
MD11 HD11# C194
MD12 AB10 B20 H D # 12 B C K E [ 7 : 0 ] should
MD12 HD12#
MD13 AC10 E18 H D # 13 27pF
MD13 HD13#
MD14 AF10
MD14 HD14#
D20 H D # 14 47
1D1 1 1Q1
2 be 3.0"
MD15 AD11 D19 H D # 15
MD15 HD15#
MD16 Y24 D18 H D # 16 8 G C KE 46 3 B_CKE7 16
MD16 HD16# 1D2 1Q2
MD17 Y25 C19 H D # 17
MD17 HD17#
MD18 W23
MD18 HD18#
B19 H D # 18 **NOTE** GCKE trace length 44
1D3 1Q3
5
MD19
MD20
W24
W26
MD19 82443BX HD19#
A18
A19
H D # 19
H D # 20 from the 443BX to the shift 43 6
MD20 HD20# 1D4 1Q4 B_CKE6 16
MD21 W25 B18 H D # 21 register should be between
MD22 V26
MD21 492 BGA HD21#
C17 H D # 22 41 8
MD22 HD22# 1" MIN and 4" MAX. 1D5 1Q5
MD23 U24 E17 H D # 23
MD23 HD23#
MD24 U23 D17 H D # 24 40 9 B_CKE5 15
MD24 HD24# 1D6 1Q6
MD25 T22 B17 H D # 25
MD25 HD25#
MD26 T23 C16 H D # 26 38 11
MD26 HD26# 1D7 1Q7
MD27 T26 A17 H D # 27
MD27 HD27#
MD28 R24 C15 H D # 28 37 12 B_CKE4 15
MD28 HD28# 1D8 1Q8
M E M O R Y DATA BUS
MD29 R25 B16 H D # 29
MD29 HD29#
MD30 P23
MD30 HD30#
D16 H D # 30 36
2D1 2 2Q1
13
MD31 N25 A16 H D # 31
MD31 HD31#
MD32 AC5 B15 H D # 32 **NOTE** If GCKE is not used 35 14
HOST DATA BUS

MD32 HD32# 2D2 2Q2 B_CKE3 14
MD33 AE5 A15 H D # 33
MD33 HD33# then each CKE requires a 22K
3 MD34 AB6 D14 H D # 34 33 16 3
MD34 HD34# 2D3 2Q3
MD35 AC6 D15 H D # 35 pullup to VCC3.
MD35 HD35#
MD36 AF6 B13 H D # 36 32 17 B_CKE2 14
MD36 HD36# 2D4 2Q4
MD37 AD7 C14 H D # 37
MD37 HD37#
MD38 AE7 E14 H D # 38 30 19
MD38 HD38# 2D5 2Q5
MD39 AC8 D13 H D # 39
MD39 HD39#
MD40 AD8 A13 H D # 40 29 20 B_CKE1 13
MD40 HD40# 2D6 2Q6
MD41 AF8 D12 H D # 41
MD41 HD41#
MD42 AE8 B12 H D # 42 27 22
MD42 HD42# 2D7 2Q7
MD43 AF9 B14 H D # 43
MD43 HD43#
MD44 AD10 C13 H D # 44 26 23 B_CKE0 13
MD44 HD44# 2D8 2Q8
MD45 AE10 E13 H D # 45
MD45 HD45#
MD46 AB11 D11 H D # 46 S N 7 4 LVCH16374
MD46 HD46#
MD47 AC11 A12 H D # 47
MD47 HD47#
MD48 Y23 B11 H D # 48
MD48 HD48#
MD49 Y26 A11 H D # 49
MD49 HD49#
MD50 W22 B7 H D # 50
MD50 HD50#
MD51 V22
MD51 HD51#
C12 H D # 51 **NOTE** The seven
MD52 V23 C8 H D # 52
MD52 HD52# outputs that circle around
MD53 V25 B10 H D # 53
MD53 HD53#
MD54 U22 A10 H D # 54 to become inputs on the
MD54 HD54#
MD55 U25 A9 H D # 55
MD55 HD55# SN74LVCH16374 should
MD56 U26 A7 H D # 56
MD56 HD56#
MD57 T24 E11 H D # 57
MD58 T25
MD57 HD57#
D9 H D # 58
have trace lengths no
MD58 HD58#
MD59 U21
MD59 HD59#
C11 H D # 59 longer than 2".
MD60 R23 C10 H D # 60
MD60 HD60#
2 MD61 R26 B8 H D # 61 2
MD61 HD61#
MD62 P24 A8 H D # 62
MD62 HD62#
MD63 P25 B9 H D # 63
MD63 HD63#
G T LREF2
MECC0 AE11 G T LREF1
MECC0
MECC1 AA10
MECC1
MECC2 AA23
MECC2
MECC3 AA26 M23
MECC3 GTLREFA
MECC4 AF11 E16
MECC4 GTLREFB
MECC5 AD12 M24 VTT
MECC5 VTTA
MECC6 AA25 F17
MECC6 VTTB
MECC7 Y22
MECC7
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
12 M E C C [ 7:0]
AA6
AA8
AA19
AA21
N24
AB3
AF1
AD5
AD9
AF13
AF26
AB25
AB12
AB15
AB24
AD18
AD22
443BX_10
VTT VTT
R102 R104
75 75
1% 1%
1 GTLREF1 G T LREF2 1
R103 R105 P L A T F O R M C O M P O NENTS DIVISION

150 C6 150 C7 1 9 0 0 P R A I R I E C I T Y RD. FM5-62
1% 0 . 001uF 1% 0 . 0 01uF F O L S OM, CA 95630
Title
8 2 4 4 3 BX MD/HD BUS


A B C D E
A B C D E
VCC
FET-SWITCHES (MEMORY DATA LINES & ECC) VCC

R106
4 . 7K
VCC U4
FENA 1
S0
56 17
S1 VCC
M D [ 63:0] 55 M D _ A [ 63:0]
S2
4 4
R107 VCC MD12 2 54 MD_A12
1A1 1B1
4.7K 3 53 MD_B12
1A2 1B2
MD13 4 52 MD_A13
U5 R295 2A1 2B1
5 51 MD_B13
2A2 2B2
8,12 F E N A 1 MD14 6 50 MD_A14
56
S0
17 R296 500 7
3A1 3B1
48 MD_B14
S1 VCC 3A2 3B2
10,12 M D [ 63:0] 55 M D _ A [ 63:0] 1 2 ,13,14 500 MD15 9 47 MD_A15
S2 R297 4A1 4B1
10 46 MD_B15
4A2 4B2
MD0 2 54 MD_A0 MD16 11 45 MD_A16
3
1A1 1B1
53 MD_B0 R298 500 12
5A1 5B1
44 MD_B16
1A2 1B2 5A2 5B2
MD1 4 52 MD_A1 500 MD17 13 43 MD_A17
R299 2A1 2B1 R300 6A1 6B1
5 51 MD_B1 14 42 MD_B17
2A2 2B2 6A2 6B2
MD2 6 50 MD_A2 MD18 15 41 MD_A18
R301 500 7
3A1 3B1
48 MD_B2 R302 500 16
7A1 7B1
40 MD_B18
3A2 3B2 7A2 7B2
500 MD3 9 47 MD_A3 500 MD19 18 39 MD_A19
R303 4A1 4B1 R304 8A1 8B1
10 46 MD_B3 20 37 MD_B19
4A2 4B2 8A2 8B2
MD4 11 45 MD_A4 MD20 21 36 MD_A20
R305 500 12
5A1 5B1
44 MD_B4 R306 500 22
9A1 9B1
35 MD_B20
5A2 5B2 9A2 9B2
500 MD5 13 43 MD_A5 500 MD21 23 34 MD_A21
R307 6A1 6B1 R308 10A1 10B1
14 42 MD_B5 24 33 MD_B21
6A2 6B2 10A2 10B2
MD6 15 41 MD_A6 MD22 25 32 MD_A22
R309 500 16
7A1 7B1
40 MD_B6 R310 500 26
11A1 11B1
31 MD_B22
7A2 7B2 11A2 11B2
500 MD7 18 39 MD_A7 500 MD23 27 30 MD_A23
R311 8A1 8B1 R312 12A1 12B1
20 37 MD_B7 28 29 MD_B23
8A2 8B2 12A2 12B2
MD8 21 36 MD_A8
R313 500 22
9A1 9B1
35 MD_B8 R314 500 8
9A2 9B2 GND
3 500 MD9 23 34 MD_A9 500 19 M D _ B [63:0] 3
R315 10A1 10B1 GND
24 33 MD_B9 38
10A2 10B2 GND
MD10 25 32 MD_A10 49
R316 500 26
11A1 11B1
31 MD_B10
GND
11A2 11B2
500 MD11 27 30 MD_A11 P I 5C16212A
R317 12A1 12B1
28 29 MD_B11
12A2 12B2
R318 500 8
GND
500 19 M D _ B [63:0] 1 2 ,15,16
GND
38
GND
49
GND
PI5C16212A
VCC
FET ENABLE TRUTH TABLE
S0
FUNCTION S2 S1 [FENA] A1 A2
R108 VCC
4 . 7K A1 = DRAM DATA LINES
U6
A1 TO B1, A2 TO B2 H H L B1 B2 A2 = GND
FENA 1
S0 B1 = DIMM 0,1 DATA LINES
M D [ 6 3:0] 56
S1 VCC
17 A1 TO B1, A2 TO B2 H H H B2 B1 B2 = DIMM 2,3 DATA LINES
55 M D _ A [ 63:0]
S2
MD24 2 54 MD_A24
1A1 1B1
2 3 53 MD_B24 2
1A2 1B2
MD25 4 52 MD_A25
R319 2A1 2B1
5 51 MD_B25
2A2 2B2
MD26 6 50 MD_A26
R320 500 7
3A1 3B1
48 MD_B26
3A2 3B2
500 MD27 9 47 MD_A27
R321 4A1 4B1
10 46 MD_B27
4A2 4B2
MD28 11 45 MD_A28
R322 500 12
5A1 5B1
44 MD_B28
5A2 5B2
500 MD29 13 43 MD_A29
R323 6A1 6B1
14 42 MD_B29
6A2 6B2
MD30 15 41 MD_A30
R324 500 16
7A1 7B1
40 MD_B30
7A2 7B2
500 MD31 18 39 MD_A31
R325 8A1 8B1
20 37 MD_B31
8A2 8B2
MD32 21 36 MD_A32
R326 500 22
9A1 9B1
35 MD_B32
9A2 9B2
500 MD33 23 34 MD_A33
R327 10A1 10B1
24 33 MD_B33
10A2 10B2
MD34 25 32 MD_A34
R328 500 26
11A1 11B1
31 MD_B34
11A2 11B2
500 MD35 27 30 MD_A35
R329 12A1 12B1
28 29 MD_B35
12A2 12B2
R330 500 8
GND
500 19 M D _ B [63:0]
GND
38
GND
1 49 1
GND I N T E L C O R P O RATION
P I 5C16212A
F O L S O M, CA. 95630
Title
F E T S W I T C H E S ( DP/4 DIMM Design)

Date: Thursday, April 09, 1998 S h eet 11 of 40

A B C D E
A B C D E
FET-SWITCHES (DRAM DATA LINES & ECC)

VCC
VCC
4 R109 VCC 4
4.7K R110 VCC
U7 4 . 7K
1 U8
8,11 F E N A S0
56 17 FENA 1
S1 VCC S0
10,11 M D [ 6 3:0] 55 M D _ A [ 63:0] 1 1 ,13,14 56 17
S2 S1 VCC
M D [ 63:0] 55 M D _ A [63:0]
S2
MD36 2 54 MD_A36
1A1 1B1
3 53 MD_B36 MD48 2 54 MD_A48
1A2 1B2 1A1 1B1
MD37 4 52 MD_A37 3 53 MD_B48
R331 2A1 2B1 1A2 1B2
5 51 MD_B37 MD49 4 52 MD_A49
2A2 2B2 R332 2A1 2B1
MD38 6 50 MD_A38 5 51 MD_B49
R333 500 7
3A1 3B1
48 MD_B38 MD50 6
2A2 2B2
50 MD_A50
MD39 9
3A2 3B2
47 MD_A39 R334 500 7
3A1 3B1
48 MD_B50
500 R335 4A1 4B1 3A2 3B2
10 46 MD_B39 500 MD51 9 47 MD_A51
4A2 4B2 R336 4A1 4B1
MD40 11 45 MD_A40 10 46 MD_B51
R337 500 12
5A1 5B1
44 MD_B40 MD52 11
4A2 4B2
45 MD_A52
MD41 13
5A2 5B2
43 MD_A41 R338 500 12
5A1 5B1
44 MD_B52
500 R339 6A1 6B1 5A2 5B2
14 42 MD_B41 500 MD53 13 43 MD_A53
6A2 6B2 R340 6A1 6B1
MD42 15 41 MD_A42 14 42 MD_B53
R341 500 16
7A1 7B1
40 MD_B42 MD54 15
6A2 6B2
41 MD_A54
MD43 18
7A2 7B2
39 MD_A43 R342 500 16
7A1 7B1
40 MD_B54
500 R343 8A1 8B1 7A2 7B2
20 37 MD_B43 500 MD55 18 39 MD_A55
8A2 8B2 R344 8A1 8B1
MD44 21 36 MD_A44 20 37 MD_B55
R345 500 22
9A1 9B1
35 MD_B44 MD56 21
8A2 8B2
36 MD_A56
MD45 23
9A2 9B2
34 MD_A45 R346 500 22
9A1 9B1
35 MD_B56
500 R347 10A1 10B1 9A2 9B2
3 24 33 MD_B45 500 MD57 23 34 MD_A57 3
10A2 10B2 R348 10A1 10B1
MD46 25 32 MD_A46 24 33 MD_B57
R349 500 26
11A1 11B1
31 MD_B46 MD58 25
10A2 10B2
32 MD_A58
MD47 27
11A2 11B2
30 MD_A47 R350 500 26
11A1 11B1
31 MD_B58
500 R351 12A1 12B1 11A2 11B2
28 29 MD_B47 500 MD59 27 30 MD_A59
12A2 12B2 R352 12A1 12B1
28 29 MD_B59
R353 500 8
12A2 12B2
GND
19 R354 500 8
500 GND M D _ B [63:0] 1 1 ,15,16 GND
38 500 19 M D _ B[63:0]
GND GND
49 38
GND GND
49
GND
PI5C16212A
P I 5C16212A
VCC
FET ENABLE TRUTH TABLE
S0
R111 VCC FUNCTION S2 S1 [FENA] A1 A2
4.7K
U9
A1 = DRAM DATA LINES
M D _ B [63:0] A1 TO B1, A2 TO B2 H H L B1 B2 A2 = GND
2 FENA 1 2
S0
56
S1 VCC
17 B1 = DIMM 0,1 DATA LINES
M D [ 6 3:0] 55
S2
M D _ A [ 63:0] A1 TO B1, A2 TO B2 H H H B2 B1 B2 = DIMM 2,3 DATA LINES
MD60 2 54 MD_A60
1A1 1B1
3 53 MD_B60
1A2 1B2
MD61 4 52 MD_A61
R355 2A1 2B1
5 51 MD_B61
2A2 2B2
MD62 6 50 MD_A62
R356 500 7
3A1 3B1
48 MD_B62
3A2 3B2
500 MD63 9 47 MD_A63 M E C C _ A [7:0] 1 3 ,14,15,16
R357 4A1 4B1
10 46 MD_B63
4A2 4B2
MECC0 11 45 M E CC_A0
R358 500 12
5A1 5B1
44 MECC_B0
5A2 5B2
500 MECC1 13 43 M E CC_A1
R359 6A1 6B1
14 42 MECC_B1
6A2 6B2
R360 500 16
7A1 7B1
40 MECC_B2
7A2 7B2
500 MECC3 18 39 M E CC_A3
R361 8A1 8B1
20 37 MECC_B3
8A2 8B2
R362 500 22
9A1 9B1
35 MECC_B4
9A2 9B2
500 MECC5 23 34 M E CC_A5
R363 10A1 10B1
24 33 MECC_B5
10A2 10B2
R364 500 26
11A1 11B1
31 MECC_B6
11A2 11B2
500 MECC7 27 30 M E CC_A7
R365 12A1 12B1
1 28 29 MECC_B7 1
12A2 12B2 I N T E L C O R P O RATION
R366 500 8
GND P L A T F O R M C O M P O NENTS DIVISION
500 19 M E C C _ B[7:0] 1 3 ,14,15,16
GND 1 9 0 0 P R A I R I E C I T Y RD. FM5-62
38
GND F O L S O M, CA. 95630
49
GND
10 M E C C [ 7:0]
Title
PI5C16212A
F E T S W I T C H E S ( DP/4 DIMM Design)


A B C D E
A B C D E
DIMM SOCKET 0
VCC3 VCC3
11,12,14 MD_A[63:0]
4 4
102
110
124
133
143
157
168
18
26
40
41
90
49
59
73
84
J4
6
MD_A0 2 55 MD_A16
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
DQ0 DQ16
MD_A1 3 56 MD_A17
DQ1 DQ17
MD_A2 4 57 MD_A18
DQ2 DQ18
MD_A3 5 58 MD_A19
DQ3 DQ19
MD_A4 7 60 MD_A20
DQ4 DQ20
MD_A5 8 65 MD_A21
DQ5 DQ21
MD_A6 9 66 MD_A22
DQ6 DQ22
MD_A7 10 67 MD_A23
DQ7 DQ23
MD_A8 11 69 MD_A24
DQ8 DQ24
MD_A9 13 70 MD_A25
DQ9 DQ25
MD_A10 14 71 MD_A26
DQ10 DQ26
MD_A11 15 72 MD_A27
DQ11 DQ27
MD_A12 16 74 MD_A28
DQ12 DQ28
MD_A13 17 75 MD_A29
DQ13 DQ29
MD_A14 19 76 MD_A30
DQ14 DQ30
MD_A15 20 77 MD_A31
DQ15 DQ31
MD_A32 86 139 MD_A48
DQ32 DQ48
MD_A33 87 140 MD_A49
DQ33 DQ49
MD_A34 88 141 MD_A50
DQ34 DQ50
MD_A35 89 142 MD_A51
DQ35 DQ51
MD_A36 91 144 MD_A52
DQ36 DQ52
MD_A37 92 149 MD_A53 **NOTE ON ALL DIMM SOCKETS**
DQ37 DQ53
MD_A38 93 150 MD_A54
DQ38 DQ54 Pin 147 should be pulled to a high state
MD_A39 94 151 MD_A55
DQ39 DQ55
3
MD_A40 95 153 MD_A56
to accommodate registered DIMMs. 3
DQ40 DQ56
8,14 MAA[13:0] MD_A41 97 154 MD_A57
DQ41 DQ57
MD_A42 98 155 MD_A58
DQ42 DQ58
MD_A43 99 156 MD_A59
DQ43 DQ59 VCC3
MD_A44 100 158 MD_A60
DQ44 DQ60
MD_A45 101 159 MD_A61
DQ45 DQ61
MD_A46 103 160 MD_A62
DQ46 DQ62
MD_A47 104 161 MD_A63
DQ47 DQ63 R367
MAA0 33 134 0 ohm
A0 NC
MAA1 117 135
A1 NC
MAA2 34 146
A2 NC
MAA3 118 164
A3 NC
MAA4 35 62
A4 NC
MAA5 119
A5
MAA6 36 147 **NOTE** If GCKE is not used
A6 REGE
MAA7 120 128 B_CKE0 10
A7 CKE0 then each CKE requires a
MAA8 37 63 B_CKE1 10
A8 CKE1
MAA9 121 22K pullup to VCC3.
A9
MAA10 38 21 MECC_A0
A10 (AP) CB0
MAA13 123 22 MECC_A1
A11 CB1
126 52 MECC_A2
A12 CB2
8,14,15,16 DQMA[7:0] 132 53 MECC_A3
A13 CB3
105 MECC_A4
CB4
DQMA0 28 106 MECC_A5
DQMB0 CB5
DQMB1 CB6
DQMB2 CB7
DQMA3 47 MECC_A[7:0] 12,14,15,16
DQMB3
DQMA4 112
DQMB4
2 DQMA5 113
DQMB5 SA0
165 SLAVE ADDRESS 2
DQMA6 130 166
DQMA7 131
DQMB6 SA1
167
= 1010000b
DQMB7 SA2 SMBDATA 3,5,8,15,16,18,34,39
SMBCLK 3,5,8,15,16,18,34,39
MAA11 122 82
BA0 SDA
MAA12 39 83 CS_A#[1:0] 8
BA1 SCL
24 30 CS_A#0 CS_B#[1:0] 8
NC /S0
25 114 CS_A#1
NC /S1
31 45 CS_B#0
NC /S2
44 129 CS_B#1
NC /S3
48 27 WE_A# 8,14
NC /WE0
50 111 SCAS_A# 8,14
NC /CAS
51 115 SRAS_A# 8,14
NC /RAS
61
NC
80 42 DCLK12
NC CK0
81 125 DCLK13
NC CK1
109 79 DCLK14
NC CK2
108 163 DCLK15
NC CK3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
145
NC
DCLK[15:0] 8,14,15,16
1
12
23
32
43
54
64
68
78
85
96
107
116
127
138
148
152
SDRAM DIMM 162
1 1
INTEL CORPORATION
PLATFORM COMP ONENTS DIVISION

1 9 0 0 P R A IRIE CITY RD. FM5-62
FOLSOM, CA 95630
Title
DIMM SOCKET 0


A B C D E
A B C D E
DIMM SOCKET 1
VCC3 VCC3
11,12,13 MD_A[63:0]
4 4
102
110
124
133
143
157
168
18
26
40
41
90
49
59
73
84
J5
6
MD_A0 2 55 MD_A16
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
DQ0 DQ16
MD_A1 3 56 MD_A17
DQ1 DQ17
MD_A2 4 57 MD_A18
DQ2 DQ18
MD_A3 5 58 MD_A19
DQ3 DQ19
MD_A4 7 60 MD_A20
DQ4 DQ20
MD_A5 8 65 MD_A21
DQ5 DQ21
MD_A6 9 66 MD_A22
DQ6 DQ22
MD_A7 10 67 MD_A23
DQ7 DQ23
MD_A8 11 69 MD_A24
DQ8 DQ24
MD_A9 13 70 MD_A25
DQ9 DQ25
MD_A10 14 71 MD_A26
DQ10 DQ26
MD_A11 15 72 MD_A27
DQ11 DQ27
MD_A12 16 74 MD_A28
DQ12 DQ28
MD_A13 17 75 MD_A29
DQ13 DQ29
MD_A14 19 76 MD_A30
DQ14 DQ30
MD_A15 20 77 MD_A31
DQ15 DQ31
MD_A32 86 139 MD_A48
DQ32 DQ48
MD_A33 87 140 MD_A49
DQ33 DQ49
MD_A34 88 141 MD_A50
DQ34 DQ50
MD_A35 89 142 MD_A51
DQ35 DQ51
MD_A36 91 144 MD_A52
DQ36 DQ52
MD_A37 92 149 MD_A53
DQ37 DQ53
MD_A38 93 150 MD_A54
DQ38 DQ54
MD_A39 94 151 MD_A55 **NOTE ON ALL DIMM SOCKETS**
DQ39 DQ55
3 3
MD_A40 95 153 MD_A56 Pin 147 should be pulled to a high state
DQ40 DQ56
MD_A41 97 154 MD_A57 to accommodate registered DIMMs.
DQ41 DQ57
MD_A42 98 155 MD_A58
DQ42 DQ58
MD_A43 99 156 MD_A59
DQ43 DQ59 VCC3
MD_A44 100 158 MD_A60
DQ44 DQ60
MD_A45 101 159 MD_A61
DQ45 DQ61
MD_A46 103 160 MD_A62
DQ46 DQ62
8,13 MAA[13:0] MD_A47 104 161 MD_A63
DQ47 DQ63 R368
MAA0 33 134 0 ohm
A0 NC
MAA1 117 135
A1 NC
MAA2 34 146 **NOTE** If GCKE is not used
A2 NC
MAA3 118 164
A3 NC then each CKE requires a 22K
MAA4 35 62
A4 NC
MAA5 119 pullup to VCC3.
A5
MAA6 36 147
A6 REGE
MAA7 120 128 B_CKE2 10
A7 CKE0
MAA8 37 63 B_CKE3 10
A8 CKE1
MAA9 121 MECC_A[7:0] 12,13,15,16
A9
MAA10 38 21 MECC_A0
A10 (AP) CB0
MAA13 123 22 MECC_A1
A11 CB1
126 52 MECC_A2
A12 CB2 VCC3
8,13,15,16 DQMA[7:0] 132 53 MECC_A3
A13 CB3
105 MECC_A4
CB4
DQMB0 CB5
DQMB1 CB6
DQMB2 CB7 R114
DQMA3 47
DQMB3
DQMA4 112 4.7K
DQMB4
2 DQMA5 113
DQMB5 SA0
165 R_SA0 SLAVE ADDRESS = 1010001b 2
DQMA6 130 166
DQMB6 SA1
DQMA7 131 167 SMBDATA 3,5,8,15,16,18,34,39
DQMB7 SA2
SMBCLK 3,5,8,15,16,18,34,39
MAA11 122 82
BA0 SDA
MAA12 39 83 CS_A#[3:2] 8
BA1 SCL
24 30 CS_A#2 CS_B#[3:2] 8
NC /S0
25 114 CS_A#3
NC /S1
31 45 CS_B#2
NC /S2
44 129 CS_B#3
NC /S3
48 27 WE_A# 8,13
NC /WE0
50 111 SCAS_A# 8,13
NC /CAS
51 115 SRAS_A# 8,13
NC /RAS
61
NC
80 42 DCLK8
NC CK0
81 125 DCLK9
NC CK1
109 79 DCLK10
NC CK2
108 163 DCLK11
NC CK3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
145
NC
DCLK[15:0] 8,13,15,16
1
12
23
32
43
54
64
68
78
85
96
107
116
127
138
148
152
162
SDRAM DIMM
1 1
INTEL CORPORATION

FOLSOM, CA 95630
Title
DIMM SOCKET 1


A B C D E
A B C D E
DIMM SOCKET 2
VCC3 VCC3
11,12,16 MD_B[63:0]
4 4
102
110
124
133
143
157
168
18
26
40
41
90
49
59
73
84
J6
6
MD_B0 2 55 MD_B16
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
DQ0 DQ16
MD_B1 3 56 MD_B17
MD_B2 4 DQ1 DQ17 57 MD_B18
DQ2 DQ18
MD_B3 5 58 MD_B19
7 DQ3 DQ19 60
MD_B4 MD_B20
DQ4 DQ20
MD_B5 8 65 MD_B21
MD_B6 9 DQ5 DQ21 66 MD_B22
DQ6 DQ22
MD_B7 10 67 MD_B23
DQ7 DQ23
MD_B8 11 69 MD_B24
MD_B9 13 DQ8 DQ24 70 MD_B25
DQ9 DQ25
MD_B10 14 71 MD_B26
15 DQ10 DQ26 72
MD_B11 MD_B27
DQ11 DQ27
MD_B12 16 74 MD_B28
17 DQ12 DQ28 75
MD_B13 MD_B29
DQ13 DQ29
MD_B14 19 76 MD_B30
MD_B15 20 DQ14 DQ30 77 MD_B31
DQ15 DQ31
MD_B32 86 139 MD_B48
DQ32 DQ48
MD_B33 87 140 MD_B49
MD_B34 88 DQ33 DQ49 141 MD_B50
DQ34 DQ50
MD_B35 89 142 MD_B51
91 DQ35 DQ51 144
MD_B36 MD_B52
DQ36 DQ52
MD_B37 92 149 MD_B53
93 DQ37 DQ53 150
MD_B38 MD_B54
DQ38 DQ54
3 MD_B39 94 151 MD_B55 3
DQ39 DQ55
MD_B40 95 153 MD_B56 **NOTE ON ALL DIMM SOCKETS**
97 DQ40 DQ56 154 VCC3
MD_B41 MD_B57
DQ41 DQ57 Pin 147 should be pulled to a
MD_B42 98 155 MD_B58
99 DQ42 DQ58 156
MD_B43 MD_B59 high state to accommodate
DQ43 DQ59
MD_B44 100 158 MD_B60
101 DQ44 DQ60 159 registered DIMMs.
MD_B45 MD_B61
DQ45 DQ61
MD_B46 103 160 MD_B62
104 DQ46 DQ62 161 R369
8,16 MAB#[13:0] MD_B47 MD_B63
DQ47 DQ63
0 ohm
MAB#0 33 134
A0 NC
MAB#1 117 135 **NOTE** If GCKE is not used
34 A1 NC 146
MAB#2
A2 NC then each CKE requires a 22K
MAB#3 118 164
35 A3 NC 62
MAB#4 pullup to VCC3.
A4 NC
MAB#5 119
36 A5 147
MAB#6 B _ C K E 4 10
A6 REGE
MAB#7 120 128 B _ C K E 5 10
37 A7 CKE0 63
MAB#8 MECC_B[7:0] 12,13,14,16
A8 CKE1
MAB#9 121
38 A9 21
MAB10 MECC_B0
A10 (AP) CB0
MAB13 123 22 MECC_B1
126 A11 CB1 52 MECC_B2
A12 CB2
8,13,14,16 DQMA[7:0] 132 53 MECC_B3
A13 CB3 105 MECC_B4
CB4
DQMA0 28 106 MECC_B5
29 DQMB0 CB5 136
8,16 D Q M B 1 MECC_B6
DQMB1 CB6 VCC3
47 DQMB2 CB7
DQMA3
DQMB3
2 DQMA4 112
DQMB4
Slave address = 1010010b 2
113 165 R116
DQMB5 SA0
DQMA6 130 166 R_SA1
131 DQMB6 SA1 167
8,16 D Q M B 5 DQMA7 S M B D A T A 3,5,8,16,18,34,39
DQMB7 SA2 4.7K
S M B C L K 3,5,8,16,18,34,39
MAB#11 122 82
BA0 SDA
MAB#12 39 83 CS_A#[5:4] 8
BA1 SCL
24 30 CS_A#4 CS_B#[5:4] 8
25 NC /S0 114
NC /S1 CS_A#5
31 45 CS_B#4
44 NC /S2 129
NC /S3 CS_B#5
48 27 W E _ B # 8,16
50 NC /WE0 111
NC /CAS SCAS_B# 8,16
51 115 SRAS_B# 8,16
61 NC /RAS
NC
80 42 DCLK4
81 NC CK0 125 DCLK5
NC CK1
109 79 DCLK6
108 NC CK2 163 DCLK7
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC CK3
145
NC
DCLK[15:0] 8,13,14,16
1
12
23
32
43
54
64
68
78
85
96
107
116
127
138
148
152
162
SDRAM DIMM
1 1
INTEL CORPORATION

FOLSOM, CA 95630
Title
DIMM SOCKET 2

Custom 1.0
Date: Thursday, April 09, 1998 S heet 15 of 40
A B C D E
A B C D E
DIMM SOCKET 3
VCC3 VCC3
11,12,15 MD_B[63:0]
4 4
102
110
124
133
143
157
168
18
26
40
41
90
49
59
73
84
J7
6
MD_B0 2 55 MD_B16
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
DQ0 DQ16
MD_B1 3 56 MD_B17
MD_B2 4 DQ1 DQ17 57 MD_B18
DQ2 DQ18
MD_B3 5 58 MD_B19
MD_B4 7 DQ3 DQ19 60 MD_B20
DQ4 DQ20
MD_B5 8 65 MD_B21
MD_B6 9 DQ5 DQ21 66 MD_B22
DQ6 DQ22
MD_B7 10 67 MD_B23
DQ7 DQ23
MD_B8 11 69 MD_B24
MD_B9 13 DQ8 DQ24 70 MD_B25
DQ9 DQ25
MD_B10 14 71 MD_B26
15 DQ10 DQ26 72
MD_B11 MD_B27
DQ11 DQ27
MD_B12 16 74 MD_B28
MD_B13 17 DQ12 DQ28 75 MD_B29
DQ13 DQ29
MD_B14 19 76 MD_B30
MD_B15 20 DQ14 DQ30 77 MD_B31
DQ15 DQ31
MD_B32 86 139 MD_B48
DQ32 DQ48
MD_B33 87 140 MD_B49
MD_B34 88 DQ33 DQ49 141 MD_B50
DQ34 DQ50
MD_B35 89 142 MD_B51
MD_B36 91 DQ35 DQ51 144 MD_B52
DQ36 DQ52
MD_B37 92 149 MD_B53
MD_B38 93 DQ37 DQ53 150 MD_B54
DQ38 DQ54
3 MD_B39 94 151 MD_B55 3
DQ39 DQ55
MD_B40 95 153 MD_B56
MD_B41 97 DQ40 DQ56 154 MD_B57
DQ41 DQ57 VCC3
MD_B42 98 155 MD_B58 **NOTE ON ALL DIMM SOCKETS**
MD_B43 99 DQ42 DQ58 156 MD_B59
DQ43 DQ59 Pin 147 should be pulled to a
MD_B44 100 158 MD_B60
101 DQ44 DQ60 159
MD_B45 MD_B61 high state to accommodate
R120 DQ45 DQ61 R370
3,5,7 100/66# MAB#12 MD_B46 103 160 MD_B62
DQ46 DQ62
10K 8,15 MAB#[13:0] MD_B47 104
DQ47 DQ63
161 MD_B63 0 ohm registered DIMMs.
MAB#0 33 134
JP16 A0 NC
MAB#11 MAB#1 117 135
MAB#2 34 A1 NC 146
IOQ DEPTH SEL A2 NC **NOTE** If GCKE is not
MAB#3 118 164
MAB#4 35 A3 NC 62 used then each CKE
A4 NC
MAB#5 119 B _ C K E 6 10 requires a 22K pullup to
MAB#6 36 A5 147
A6 REGE B _ C K E 7 10
MAB#7 120 128 VCC3.
MAB#8 37 A7 CKE0 63
A8 CKE1 MECC_B[7:0] 12,13,14,15
MAB#9 121
R119 MAB10 38 A9 21 MECC_B0
A10 (AP) CB0 VCC3
10K MAB13 123 22 MECC_B1
126 A11 CB1 52 MECC_B2
A12 CB2
8,13,14,15 DQMA[7:0] 132 53 MECC_B3
A13 CB3 105 MECC_B4
CB4
29 DQMB0 CB5 136 R121
8,15 D Q M B 1 DQMB1 CB6
MECC_B6 Slave address =
DQMA2 46 137 MECC_B7 4.7K
DQMA3 47 DQMB2 CB7 1010011b
DQMB3
2 DQMA4 112 2
113 DQMB4 165
DQMB5 SA0
DQMA6 130 166
DQMA7 131 DQMB6 SA1 167
8,15 D Q M B 5 DQMB7 SA2 S M B D A T A 3,5,8,15,18,34,39
S M B C L K 3,5,8,15,18,34,39
MAB#11 122 82
BA0 SDA
MAB#11: 1 = IOQ depth of 4 (default), 0 = IOQ depth of 1 MAB#12 39
BA1 SCL
83 CS_A#[7:6] 8
24 30 CS_A#6 CS_B#[7:6] 8
25 NC /S0 114
NC /S1 CS_A#7
31 45 CS_B#6
44 NC /S2 129
NC /S3 CS_B#7
48 27 W E _ B # 8,15
50 NC /WE0 111
NC /CAS SCAS_B# 8,15
51 115 SRAS_B# 8,15
61 NC /RAS
NC
80 42 DCLK0
81 NC CK0 125
NC CK1 DCLK1
109 79 DCLK2
108 NC CK2 163 DCLK3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC CK3
145
NC
DCLK[15:0] 8,13,14,15
1
12
23
32
43
54
64
68
78
85
96
107
116
127
138
148
152
162
SDRAM DIMM
1 1
INTEL CORPORATION

FOLSOM, CA 95630
Title
DIMM SOCKET 3

Custom 1.0
A B C D E
A B C D E
U10A
AD0 B10 E15 S D D0
AD0 SDD0
AD1 A10 B15 S D D1
AD1 SDD1
AD2 D9 D14 S D D2
AD2 SDD2
AD3 C9 C14 S D D3
AD3 SDD3
AD4 B9 A14 S D D4
AD4 SDD4
AD5 A9 C13 S D D5
AD5 SDD5
AD6 D8 A13 S D D6
AD6 SDD6
AD7 E8 C12 S D D7
IDE SIGNALS
AD7 SDD7
AD8 B8 D12 S D D8
AD8 SDD8
AD9 A8 B13 S D D9
AD9 SDD9
A D 10 D7 D13 S D D10
A D 10 SDD10
4 A D 11 C7 B14 S D D11 4
A D 11 SDD11
A D 12 B7 E14 S D D12
A D 12 SDD12
A D 13 A7 A15 S D D13
A D 13 SDD13
A D 14 D6 C15 S D D14
A D 14 SDD14
A D 15 E6 D15 S D D15
A D 15 SDD15
A D 16 E4 S D D [ 1 5 :0] 25
A D 16
A D 17 C4 C18 SCS3# 25
A D 17 SCS3#
A D 18 B4 H16 PCS3# 25
PCI BUS INTERFACE

A D 18 PCS3#
A D 19 A4 B18 SCS1# 25
A D 19 SCS1#
A D 20 D3 H17 PCS1# 25
A D 20 PCS1#
A D 21 E3
A D 21
A D 22 C3
A D 22
A D 23 B3 U11 SA0
A D 23 SA0
A D 24 E2 T11 SA1
A D 24 SA1
A D 25 C2 W11 SA2
A D 25 SA2
A D 26 B2 Y11 SA3
A D 26 SA3
A D 27 A2 T10 SA4
A D 27 SA4
A D 28 D1 W10 SA5
A D 28 SA5
A D 29 E1 U9 SA6
A D 29 SA6
A D 30 C1 V9 SA7
A D 31 B1
A D 30
A D 31 82371EB SA7
SA8
SA9
Y9
T8
SA8
SA9
W8 SA10
9 , 22,23 A D [ 3 1 : 0] SA10
C / BE#0 C8 U7 SA11
C / B E#0 SA11
C / BE#1 C6 V7 SA12
C / B E#1 SA12
C / BE#2 D4 Y7 SA13
C / B E#2 SA13
C / BE#3 D2 V6 SA14
3 C / B E#3 SA14 3
9 , 22,23 C / B E # [ 3:0] Y6 SA15
SA15
C10 T5 SA16
C L O C K R U N# SA16
E5 W5 SA17
9 , 22,23,34 D E VSEL# D E VSEL# SA17
A5 U4 SA18
9 , 2 2,23,34 F R AME# F R AME# SA18
R _ AD18 A3 V4 SA19
I D S EL SA19
R371 9 , 2 2,23,34 I R D Y # B5 S A [ 1 9 :0] 1 9 , 2 0,24,27,35,39
IRDY#
9 , 22,23 P A R B6
100 PAR
8 , 2 1,22,23 P C I R ST# A1 V3 SD0
P C I R ST# SD0
9 , 34 P H L D# B12 W3 SD1
P H O LD# SD1
9,34 P H L D A# A12 U2 SD2
P H O L DA# SD2
9 , 2 2,23,34 S E RR# A6 T2 SD3
S E R R# SD3
R122 D5 W2 SD4
9 , 2 2,23,34 STOP# STOP# SD4
9 , 2 2,23,34 T R D Y # C5 Y2 SD5
100 TRDY# SD5
9 , 2 2,23,34 P R E Q #[3:0] T1 SD6
SD6
A D 18 PREQ#0 E10 V1 SD7
REQ0# SD7
PREQ#1 A11 W16 SD8
REQ1# SD8
ISA/EIO SIGNALS
PREQ#2 B11 T16 SD9
REQ2# SD9
PREQ#3 C11 Y17 SD10
REQ3# SD10
25 S D A [ 2 : 0] V17 SD11
SD11
S D A0 C17 Y18 SD12
S D A0 SD12
S D A1 B17 W18 SD13
S D A1 SD13
S D A2 A18 Y19 SD14
S D A2 SD14
25 P D D A CK# G19 W19 SD15
P D D A CK# SD15
25 S D D A CK# A17 S D [ 1 5 :0] 2 0 ,24,35
S D D A CK#
25 P D R EQ F18
P D R EQ
25 S D R EQ A16 Y15 LA17
S D R EQ LA17
25 P D I O R# F17 T14 LA18
2 P D I O R# LA18 2
25 PDIOW# F16 W14 LA19
P D IOW# LA19
25 PIORDY G20 U13 LA20
PIORDY LA20
25 S D I O R# C16 V13 LA21
S D I O R# LA21
25 S D IOW# B16 Y13 LA22
S D IOW# LA22
IDE SIGNALS
25 SIORDY D16 T12 LA23

SIORDY LA23
P D A0 G16 L A [ 2 3:17] 24,35
P D A0
P D A1 G18 Y12 MEMCS16# 24,35
P D A1 MEMCS16#
P D A2 G17 V15 MEMR# 1 9 ,24,27,35
P D A2 MEMR#
U15 MEMW# 1 9 ,24,27,35
25 P D A [ 2 : 0] MEMW#
W4 SMEMR# 24
SMEMR#
P D D0 F20
PDD0
P D D1 E18 U3 SMEMW# 24
PDD1 SMEMW#
P D D2 E20 T7 S Y S CLK 24,39
PDD2 SYSCLK
P D D3 D18 U10 BALE 24
PDD3 BALE
P D D4 D20 Y1 I O C H K# 24,35
PDD4 IOCHK#
P D D5 C20
PDD5
P D D6 B20 W7 R E F R ESH# 24,35
PDD6 REFRESH#
P D D7 A20 V12 I O CS16# 24,35
PDD7 IOCS16#
P D D8 A19 Y3 Z E R O W S # 24,35
PDD8 ZEROWS#
P D D9 B19
PDD9
P D D10 C19 W12 SBHE# 24
P D D10 SBHE#
P D D11 D19 W1 R S T D RV 20,32
P D D11 RSTDRV
P D D12 D17 Y5 I O R# 2 0 , 24,35,39
P D D12 IOR#
P D D13 E19 T4 IOW# 2 0 , 24,35,39
P D D13 IOW#
P D D14 E17 T3 I O C H R D Y 2 0 ,24,35
P D D14 IOCHRDY
P D D15 F19 Y4 A E N 20,24
P D D15 AEN
1 1
25 P D D [ 1 5:0]
PIIX4_15
F O L S O M, CA 95630
Title
8 2 3 7 1 EB (PART I)


A B C D E
A B C D E
VCC3 VCC3 3VSB VCC3
R15
R16
N16
E11
E12
E16
P15
F15
F14
G6
R6
R7
E9
K5
F6
F5
T6
U10B
20,24 D A C K # [ 3 : 0 ]
DACK#0 U14 F1 5VSB
USBP1+ 26
VCC
VCC
VCC
VCC
VCC
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
DACK0# USBP1+
VCCSUS
VCCSUS
VCCUSB
DACK#1 W6 H2
4 DACK1# USBP1- USBP1- 26 4
DACK#2 Y10 G2 JP29 CONFIG.
DACK2# USBP0+ USBP0+ 26
USB
DACK#3 V5 H3
24 DACK#[7:5] DACK3# USBP0- USBP0- 26
DACK#5 T15
DACK5# OC0
J1
OC#0 26 SAVE STATE ON
DACK#6 V16 J2 3VSB 5VSB R413 1-2
W17 DACK6# OC1 OC#1 26 POWER DOWN.
DACK#7 10K
DACK7#
DMA SIGNALS
PIIX4 POWERS ON SYS.
20,24,35 DRQ0 W15
DREQ0 EXTSMI#
V20
EXTSMI# 34,39 2-3 AT POWER-UP.
20,24,35 DRQ1 U6 W20 14 U11F 14 U36A
DREQ1 SUSA# SUSA# 7
20,24,35 DRQ2 V2 V19
DREQ2 GPO15/SUSB#
20,24,35 DRQ3 U5 U18 SUSC# 13 12 1 2
Y16 DREQ3 GPO16/SUSC#
24,35 DRQ5 C12
DREQ5
POWER MANAGEMENT
24,35 DRQ6 U16 R1 CPU_STP# 7 7 7
U17 DREQ6 GPO17/CPU_STP# R2
24,35 DRQ7 PCI_STP# 7 0.01 uF 74LVC14 74F07
DREQ7 GPO18/PCI_STP# K16
GPO19/ZZ
34 REQ#A M1
N2 REQA#/GPI2 JP29
34 REQ#B REQB#/GPI3
34 REQ#C P3 H19 T H E R M # 3,5,34 3
N1 REQC#/GPI4 GPI8/THERM# U19 2
GNTA#/GPO9 GPI9/BATLOW# BATLOW# 34 B_SUSC 32
P2 M17 1
GNTB#/GPO10 RSMRST# RSMRST# 32
P4 U20 PWRBT# 32
GNTC#/GPO11 PWRBT# JMP_3P
20,24 T C V10
TC 82371EB GPI10/LID
SMBDATA
SMBCLK
P16
T20
R19
LID 32,34
S M B D A T A 3,5,8,15,16,34,39
S M B C L K 3,5,8,15,16,34,39
VCC3
**External logic shown
is used to handle
J17 N17 power loss condition.
19 APICACK# APICACK#/GPO12 GPI11/SMBALERT# SMBALERT# 34
H18 P18
19,34 A P I C C S # APICCS#/GPO13 GPI12/RI#A A G P _ P M E # 21,34
K18
19,34 A P I C R E Q # APICREQ#/GPI5
H20 P17 D1 VCC

1 9 IRQ0 IRQ0/GPO14 SUSCLK
J20 T17 SUSTAT# 9 SCHOTTKY
19,20,35 IRQ1 T9 IRQ1 GPO20/SUS_STAT1# T18
19,20,24,35 IRQ3 IRQ3 GPO21/SUS_STAT2# BAR43
W9 J18 S T P C L K # 3,5,34
3 19,20,24,35 IRQ4 U8 IRQ4 STPCLK# K20 R128 3
19,20,24,35 IRQ5 IRQ5 SLP# S L P # 3,5,34
IRQ SIGNALS
V8 1K
19,20,24,35 IRQ6 IRQ6
19,20,24,35 IRQ7 Y8
Y20 IRQ7
19,35 IRQ#8 IRQ8/GPI6
U1 J16 VREF5V 9
19,20,24,35 IRQ9 U12 IRQ9 VREF
19,20,24,35 IRQ10 IRQ10
W13 +
19,20,24,35 IRQ11 IRQ11 C13
T13 C14
19,20,24,35 IRQ12 IRQ12
V14 1.0 uF
19,20,24,25,35 IRQ14 IRQ14
Y14 P19 0.1 uF
19,20,24,25,35 IRQ15 IRQ15 GPI1 P C I _ P M E # 22,23,34
L2 GPI13 5VSB
GPI13
3 4 GPI7 J19 J3 GPI14
SERIRQ/GPI7 GPI14
19,21,22,23,34 PIRQ#A PIRQ#A R3 L5 GPI15
PIRQA# GPI15 5VSB
19,21,22,23,34 PIRQ#B PIRQ#B R4 K3 GPI16
PIRQB# GPI16
3
PIRQ#C P5 K4 GPI17 5VSB SPS3 Q8
19,22,23,34 PIRQ#C PIRQC# GPI17 U22C
19,22,23,34 PIRQ#D PIRQ#D G1 H1 GPI18 14
PIRQD# GPI18 H4 9 R286 2N7002
GPI19 GPI19
H5 GPI20 SUSC# 10 8 10K 2
GPI20 WOLLID 32
M19 G3 11
K19 CPURST GPI21 7
G P O /GPI/GPIO/SCAN
CPU INTERFACE
3,5,34 F E R R # FERR# GPI[20:13] 34
1
33,34 P X 4 _ I G N N E # L17 74HC10
IGNNE#
3,5,34 HINIT# L18
INIT
19,33,34 PX4_INTR L19
INTR
20,34 A 2 0 G A T E P1 GPI21 2 9
A20GATE
L20 SPS2
33,34 P X 4 _ N M I NMI
19,34 P X 4 _ S M I # P20
PX4_SMI#
3VSB N20 G4 GPO0 RTC_BAT
20,34 K B R S T # RCIN# GPO0 FAN_LED 32
3
33,34 P X 4 _ A 2 0 M# M20 T19 GPO8 Q6
A20M# GPO8
M18 G5 GPO27 1
9,32 P W R O K PWROK GPO27 TP3 2N7002
32 SPKR K17 F2 GPO28 1 10K
SPKR GPO28 TP4
V18 F3 IRQ9OUT 19 8.2K 2 POWER-ON 32
34 TEST# TEST# GPO29 R387
2 F4 2
GPO30 R414
1
D2
SCHOTTKY N4
MCCS# 5VSB
BAR43 20 XOE# M4
XOE#/GPO23
M3 L4 1
X-BUS
2 0 XDIR# XDIR#/GPO22 PGCS0# PGCS#0 TP5

M2 N5
10
27 BIOSCS# BIOSCS# PGCS1# PGCS#1 P G C S # 1 34,39 U32A U32B
4
L1 16 16
RTCALE/GPO25 R388 VCC VCC
RTC_BAT K2 J4 32 PS_POK 3 5 11 9
PR
PR
K1 RTCCS#/GPO24 N/C N18 J Q J Q
R129 KBCCS#/GPO26 N/C 1K 10K
1 JP17 N3 R389 1 13
VB2 N/C CLK CLK
2 L16 M5 R415
1K VBAT N/C 1.5K
3 RTCX2 R20 M16 2 6 12 7
CL
CL
RTCX2 N/C K Q K Q
RTCX1 N19 R5 8 8
RTCX1 N/C 5VSB GND GND
15
14
3
C15 R287 74HC112 74HC112
0.1 uF L3 R17 14 U30B Q5
0 7 48Mhz_0 48Mhz CONFIG1 PX4_CFG1 34
GPO8#
D3 7 OSC2 V11 R18 JK_CLR 2N7002
OSC CONFIG2
SCHOTTKY D11 3 4 2
VSS_USB
7 PXPCLK PCICLK
BAR43
7 C113
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
1
CMOS_CLR
Y2 R130 74HCT14 R288

R131 2 1 8.2K 0.1uF 8.2K RSMRST#
J9
J5
J10
J11
J12
L9
L10
L11
L12
M10
M11
M12
E13
K10
K11
K12
M9
D10
E7
K9
PIIX4_15
1K 32.768KHz
C16 C17
1 VB1
18pF 18pF
CLEAR CMOS RTC_BAT
BT1
JP6 CONFIG
1 1 -2 NORMAL 1
2
2-3 CLEAR CMOS

INTEL CORPORATION
P L A TFORM COMPONENTS DIVISION

FOLSOM, CA 95630
Title
82371EB (PART II)


A B C D E
A B C D E
IOAPIC
4 4
VCC
19
51
64
U34
VCC
VCC
VCC
2
7 P C L K APIC CLK
7 A P I C C LK 62
A P I C C LK
60
V C C PINS :
33 CRESET RESET
61
18,34 A P I C CS# CS- 19, 51, 64
18 A P I C A CK# 10 9 A P I C R EQ# 18,34
A P I C A C K1- APICREQ-
9 WSC# 8
A P I C A C K2-
1 7 , 24,27,35 MEMR# 12
RD- SMIOUT-
6 A P C_SMI# 34 **NOTE** JP18 is used for
11
1 7 , 24,27,35 MEMW# WR- JP18 validation purposes and
7 1
NC
20 2 H S M I# 3 , 5 will not be necessary on
NC
1 7 , 2 0,24,27,35,39 S A 0 13 32 PX4_SMI# 3
A0 NC production boards.
14 36
3
1 7 , 2 0,24,27,35,39 S A 1
1 7 , 20,24,27,35 S A 4
15
17
A1
D/I- 82093AA NC
NC
NC
45
46
47
JP19 SMI SOURCE
3
1 8 ,33,34 P X 4_INTR INTIN0 NC
1 8 ,20,24,35 I R Q [ 7 : 1 ] IRQ1 34
INTIN1 NC
48 1 -2 APIC SMI
18 I R Q 0 35 49
INTIN2 NC
IRQ3 25
INTIN3 NC
63 3 -4 PIIX4 SMI
IRQ4 26
INTIN4
IRQ5 27 4 P I C D0 3 , 5,34
INTIN5 APICD0
IRQ6 28 5 P I C D1 3 , 5,34
INTIN6 APICD1
IRQ7 29
INTIN7
A P C _I8 31
INTIN8
30 X D [ 7:0] 2 0 ,27,39
1 8 , 20,24,35 IRQ9 INTIN9
24
1 8 , 20,24,35 I R Q 10 INTIN10
1 8 , 20,24,35 I R Q 11 23
INTIN11
1 8 , 20,24,35 I R Q 12 22 59 XD0
INTIN12 D0
16 58 XD1
INTIN13 D1
1 8 , 20,24,25,35 I R Q 14 18 57 XD2
INTIN14 D2
1 8 , 20,24,25,35 I R Q 15 21 56 XD3
INTIN15 D3
55 XD4
D4
54 XD5
D5
1 8 , 21,22,23,34 P I R Q #A 37 53 XD6
INTIN16 D6
1 8 , 21,22,23,34 P I R Q#B 38 50 XD7
INTIN17 D7
39
VCC RP1 1 8 , 22,23,34 P I R Q #C INTIN18
1 8 , 22,23,34 P I R Q #D 40
INTIN19
2 18 I R Q 9 O UT 41
R1 INTIN20
R2
3 P U _ I21 42
INTIN21
GND PINS :
4 P U _ I22 43
R3 INTIN22
1
PU R4
5 18,34 PX4_SMI# 44
INTIN23 1, 33, 52
6
R5
2 7 P U _ I13 2
R6
8 P U _ T S TIN 3
GND
GND
GND
R7 T E S T IN-
9
R8
10
R9
82093AA
1
33
52
4.7K
33 C R S T_STBY
3 V SB
1
14
2 3 A P C _I8
18,35 I R Q#8
7 U13A
74LVC125
1 1
Title
IOAPIC


A B C D E
1 2 3 4 5 6 7 8
VCC
101
125
139
21
60
U14
121 37
VCC
VCC
VCC
VCC
VCC
V B AT 14CLK01
122 38
XTAL1 14CLK02
124 39 TP076 1 TP6
XTAL2 14CLK03
7 OSC3 22
1 4 C LOCKI
1 7 ,24,35,39 I O R # 68 36 TP077 1 TP7
IOR# 16CLK
1 7 ,24,35,39 IOW# 69 35 TP088 1 TP8
IOW# 24CLK
17,24 A E N 70
AEN
A 17,32 R S T D RV 80 14 INDEX# 29 A
R S T D RV INDEX#
17,24,35 I O C H R D Y 90 9 D I R # 29
IOCHRDY DIR#
17,24,35 S D [ 1 5 :0] 10 STEP# 29
STEP#
SD0 72 11 W D ATA# 29
SD0 WDATA#
SD1 73 12 WGATE# 29
SD1 WGATE#
SD2 74 15 TRK0# 29 R401
SD2 TRK0# 1K
SD3 75 16 W P T# 29
SD3 WPT#
SD4 76 17 R D A TA# 29 R402
SD4 RDATA# 1K
SD5 77 13 S I DE1# 29
SD5 SIDE1#
SD6 78 18 D S K C HG# 29
SD6 DSKCHG# Stuff for 93X only
SD7 79 4 MOTEA# 29
SD7 MTR0#
7 MOTEB# 29
MTR1#
18,24 TC 89 6 D R V S A# 29
TC DRVSEL0#
1 8 ,24,35 D R Q [ 7 : 0] 5 D R V SB# 29
DRVSEL1#
D R Q0 82 2 R E D W C # 29
D R Q0 DRVDEN0
D R Q1 84 3 D R ATE0 29
D R Q1 DRVDEN1 Stuff for 93XFR
D R Q2 86 20 TP090 1 TP9
D R Q2 MEDID0
D R Q3 88 19 I R R 4_MODE
D R Q3 MEDID1
18,24 D A C K # [ 3 :0] R403 0
D A C K#0 81 P D R [ 7 : 0] 28
D A C K0
D A C K#1 83 138 P D R0
D A C K1 PD0
D A C K#2 85 137 P D R1
D A C K2 PD1
D A C K#3 87 136 P D R2
VCC D A C K3 PD2
1 8 , 19,24,35 I R Q [ 7 : 0] 135 P D R3
PD3
IRQ1 67 134 P D R4
IRQ1 PD4
IRQ3 66 133 P D R5
IRQ4 65
64
IRQ3
IRQ4
FDC37C932FR PD5
PD6
132
131
P D R6
IRQ5 P D R7
B R374
10K IRQ6 63
62
IRQ5
IRQ6
160 PIN QFP PD7
140
B
IRQ7 IRQ7 SLIN# S L I N #R 28

B _ IRQ#8 61 141 INIT#R 28
I R Q8# INIT#
1 8 , 19,24,35 IRQ9 IRQ9 59
IRQ9 AFD#
143 A F D # R 28 Config Port Address
1 8 , 19,24,35 I R Q 10 I R Q 10 58 144 STB#R 28
I R Q10 STB#
1 8 , 19,24,35 I R Q 11 I R Q 11 57 128 B U S Y 28
I R Q11 BUSY VCC
1 8 , 19,24,35 I R Q 12 I R Q 12 56 129 A C K# 28
I R Q12 ACK# 3 7 0 h I / O Decode
1 8 , 19,24,25,35 I R Q 14 I R Q 14 55 127 PE 28
I R Q14 PE
1 8 , 19,24,25,35 I R Q 15 I R Q 15 54 126 SLCT 28 R404
I R Q15 SLCT
1 7 , 1 9,24,27,35,39 S A [ 1 9:0] 142 E R R# 28
ERR#
SA0 41
SA0 10K
SA1 42 145 RX0 29
SA1 RXD1
SA2 43 146 TX0 29
SA2 TXD1
SA3 44 148 RTS0# 29
SA3 RTS1#
SA4 45 149 CTS0# 29
SA4 CTS1#
SA5 46 150 DTR0# 29
SA5 DTR1#
SA6 47 147 DSR0# 29 R132
SA6 DSR1#
SA7 48 152 RLSD0# 29
SA7 DCD1#
SA8 49 151 R I 0# 29
VCC SA8 RI1# 1K
SA9 50
SA9
SA10 51 155 RX1 29 3 F 0 h I / O Decode
SA10 RXD2
SA11 52 156 TX1 29
SA11 TXD2 ( D E F A ULT) VCC
SA12 53 158 RTS1# 29
S A 1 2/CS RTS2#
SA13 27 159 CTS1# 29
R133 S A 1 3 / HDCS2# CTS2#
SA14 28 160 DTR1# 29 C18
8.2K S A 1 4 / HDCS3# DTR2#
SA15 29 157 DSR1# 29
S A 1 5 / IDE2_IRQ DSR2# 4 7 0pF JP19
C 154 RLSD1# 29 C
DCD2#
S I O _PU2 26 153 R I 1# 29
I D E 1 _IRQ RI2# 6
1 TP080 23
TP10
1 24
IDE1_OE# KEY 5
TP11 TP081 H D C S 0# 4
VCC VCC 1 TP082 25 96 TP092 1
TP12 H D C S 1# GP10/IRQIN TP13 3
1 TP083 30 97 TP091 1 TP15
RP2 Stuff for 93XFR TP14 I O ROP# GP11/IRQIN 2
1 TP084 31 98 I R RX
TP16 IOWOP# GP12/IRRX 1
1 8 99 IRTX
R405 GP13/IRTX
2 7 1 TP079 34 100 TP073 1 TP18 INFRARED HDR
TP17 I D E _A0 GP14/RS
3 6 0 1 TP078 33 102 TP072 1 TP20
TP19 I D E _A1 GP15/WS C19 C20
4 5 1 TP085 32 103 TP087 1 TP22
TP21 I D E _A2 GP16/JOYRS
4 . 7K 104 TP075 1 TP23 470pF
GP17/JSWS 470pF
30 KBCLK# 92 105 KBRST# 18,34
KCLK GP20/IDE2_OE C21 C22
30 K B DAT# 91 106 R_GP21
K D AT GP21/EEDIN
30 MSCLK# 94 107 TP071 1 TP24
MSCLK GP22/EDOUT
30 MSDAT# 93 108 TP070 1 TP25 0 . 1 uF 0.1 uF
MSDAT GP23/EECLK
109 TP069 1 TP26
GP24/EEEN
XD0 111 110 A20GATE 18,34
RD0 GP25/8042_P21
XD1 112
RD1
XD2 113
RD2
XD3 114
RD3 VCC
XD4 115
RD4
XD5 116 R134
RD5
XD6 117
RD6
XD7 118
RD7 8.2K
1 9 ,27,39 X D [ 7:0]
D 18 XOE# 119 D
VSS
VSS
VSS
VSS
VSS
VSS
VSS
ROMCS# I N T E L C O R P O RATION
18 X D IR# 120
R O M DIR#
1
8
40
71
95
123
130
F D C 3 7 C932FR_1.3 1 9 0 0 P R A I R I E C I T Y RD. FM5-62

Stuff for 93XFR R406 F O L S OM, CA 95630
1K Title
I / O C O N T R O L L E R ( U LTRA I/O)

ULTRA I/O Custom Intel(R) 440BX AGPset

1.0
1 2 3 4 5 6 7 8
A B C D E
AGP CONNECTOR
VCC3 VCC3
9 SBA[7:0]
9 ST[2:0]
4 VCC3 4
VCC3 J8 +12V
VCC
26 AGP_OC#
R135
R136 B1 A1 4.7K
OVRCNT# 12V
4.7K
B2 A2
5V SPARE
B3 A3
5V RESERVED
26 USBAGP+ B4 A4
USB+ USB- USBAGP- 26
B5 A5
U15C GND GND 3 4
PIRQ3#A PIRQ#A 18,19,22,23,34
6 5 PIRQ3#B B6 A6
18,19,22,23,34 PIRQ#B INTB# INTA# U15B 74AS07
9 GCLKOUT B7 A7
74AS07 CLK RST# PCIRST# 8,17,22,23
B8 A8
9,34 GREQ# REQ# GNT# GGNT# 9,34
B9 A9
VCC3.3 VCC3.3
ST0 B10 A10 ST1
ST0 ST1
ST2 B11 A11
ST2 RESERVED
B12 A12
9,34 RBF# RBF# PIPE# PIPE# 9,34
B13 A13
GND GND
B14 A14
SPARE SPARE
SBA0 B15 A15 SBA1
SBA0 SBA1
B16 A16
VCC3.3 VCC3.3
SBA2 B17 A17 SBA3
SBA2 SBA3
B18 A18
9,34 SBSTB SB_STB RESERVED
B19 A19
GND GND
3 3
SBA4 B20 A20 SBA5
SBA4 SBA5
SBA6 B21 A21 SBA7
SBA6 SBA7
GAD31 B26 A26 GAD30

AD31 AD30
GAD29 B27 A27 GAD28
AD29 AD28
B28 A28
VCC3.3 VCC3.3
GAD27 B29 A29 GAD26
AD27 AD26
GAD25 B30 A30 GAD24
AD25 AD24
B31 A31
GND GND
9,34 ADSTB-B B32 A32
AD_STB1 RESERVED
GAD23 B33 A33 GC/BE#3
AD23 GC/BE3#
B34 A34
Vddq3.3 Vddq3.3
GAD21 B35 A35 GAD22
AD21 AD22
GAD19 B36 A36 GAD20
AD19 AD20
B37 A37
GND GND
GAD17 B38 A38 GAD18
AD17 AD18
GC/BE#2 B39 A39 GAD16
C/BE2# AD16
B40 A40
Vddq3.3 Vddq3.3
B41 A41
9,34 GIRDY# IRDY# FRAME# GFRAME# 9,34
2 2
B42 A42
SPARE SPARE
B43 A43
GND GND
B44 A44
SPARE SPARE
B45 A45
VCC3.3 VCC3.3
B46 A46
9,34 GDEVSEL# DEVSEL# TRDY# GTRDY# 9,34
B47 A47
Vddq3.3 STOP# GSTOP# 9,34
B48 A48
34 GPERR# PERR# PME# AGP_PME# 18,34
B49 A49
GND GND
B50 A50
34 GSERR# SERR# PAR GPAR 9,34
GC/BE#1 B51 A51 GAD15
C/BE1# AD15
B52 A52
Vddq3.3 Vddq3.3
GAD14 B53 A53 GAD13
AD14 AD13
GAD12 B54 A54 GAD11
AD12 AD11
B55 A55
GND GND
GAD10 B56 A56 GAD9
AD10 AD9
GAD8 B57 A57 GC/BE#0
AD8 C/BE0#
B58 A58
Vddq3.3 Vddq3.3
9,34 ADSTB-A B59 A59
AD_STB0 RESERVED
GAD7 B60 A60 GAD6
AD7 AD6
B61 A61
GND GND
GAD5 B62 A62 GAD4
AD5 AD4
GAD3 B63 A63 GAD2
1 AD3 AD2 1
B64 A64
Vddq3.3 Vddq3.3
GAD1 B65 A65 GAD0
AD1 AD0
B66 A66
RESERVED RESERVED
INTEL CORPORATION
AGP_CONN_1.3 PLATFORM COMPONENTS DIVISION

FOLSOM, CA 95630
Title
9 GAD[31:0] ACCELERATED GRAPHICS PORT (AGP) CONNECTOR
GC/BE#[3:0] Size Document Number Rev


A B C D E
1 2 3 4 5 6 7 8
PCI CONNECTORS
VCC3
VCC3
1 AND 2 VCC3
VCC3
VCC VCC
-12V VCC -12V VCC

VCC +12V VCC +12V R137 R138
5.6K 5.6K
A J9 J10 A
B1 A1 PTRST# 23 B1 A1 PTRST#
-12V TRST# -12V TRST#
23 PTCK B2 A2 PTCK B2 A2
TCK +12V TCK +12V
B3 A3 B3 A3 PTMS
GND TMS PTMS 23 GND TMS
B4 A4 B4 A4 PTDI
TDO TDI PTDI 2 3 TDO TDI
B5 A5 R139 B5 A5
+5V +5V +5V +5V
B6 A6 B6 A6 PIRQ#B
+5V INTA# PIRQ#A 18,19,21,23,34 +5V INTA#
B7 A7 5.6K PIRQ#C B7 A7 PIRQ#D
18,19,21,23,34 PIRQ#B INTB# INTC# PIRQ#C 18,19,23,34 INTB# INTC#
B8 A8 PIRQ#A B8 A8 R140
18,19,23,34 PIRQ#D INTD# +5V INTD# +5V
PRSNT#11 B9 A9 PRSNT#21 B9 A9
PRSNT1# RSV PRSNT1# RSV
B10 A10 B10 A10 5.6K
RSV +5V RSV +5V
B12 A12 B12 A12
GND GND GND GND
B13 A13 B13 A13
B14 GND GND A14 B14 GND GND A14
RSV RSV RSV RSV
B15 A15 PCIRST# 8,17,21,23 B15 A15 PCIRST#
GND RESET# GND RESET#
7 PCLK1 B16 A16 7 PCLK2 B16 A16
CLK +5V CLK +5V
B17 A17 B17 A17
GND GNT# P G N T # 0 9,34 GND GNT# P G N T # 1 9,34
9,17,34 PREQ#0 B18 A18 B18 A18
REQ# GND 9,17,34 PREQ#1 REQ# GND
B19 A19 PCI_PME# B19 A19
+5V PME# +5V PME# P C I _ P M E # 18,23,34
AD31 B20 A20 AD30 AD31 B20 A20 AD30
AD(31) AD(30) AD(31) AD(30)
AD29 B21 A21 AD29 B21 A21
AD(29) +3.3V AD(29) +3.3V
B22 A22 AD28 B22 A22 AD28
GND AD(28) GND AD(28)
AD27 B23 A23 AD26 AD27 B23 A23 AD26
B24 AD(27) AD(26) A24 B24 AD(27) AD(26) A24
AD25 AD(25) GND AD25 AD(25) GND
B25 A25 AD24 B25 A25 AD24
+3.3V AD(24) +3.3V AD(24)
C/BE#3 B26 A26 R_AD26 C/BE#3 B26 A26 R_AD27
C/BE#3) IDSEL C/BE#3) IDSEL
B27 A27 B27 A27
AD(23) +3.3V AD(23) +3.3V
AD23 B28 A28 AD22 AD23 B28 A28 AD22
AD21 B29 A29 AD20 AD21 B29 A29 AD20
AD(21) AD(20) AD(21) AD(20)
AD19 B30 A30 AD19 B30 A30
B AD(19) GND AD(19) GND B
B31 A31 AD18 B31 A31 AD18
+3.3V AD(18) +3.3V AD(18)
AD17 B32 A32 AD16 AD17 B32 A32 AD16
AD(17) AD(16) AD(17) AD(16)
C/BE#2 B33 A33 C/BE#2 B33 A33
B34 C/BE#(2) +3.3V A34 B34 C/BE#(2) +3.3V A34
GND FRAME# F R A M E # 9,17,23,34 GND FRAME# FRAME#
9,17,23,34 IRDY# B35 A35 IRDY# B35 A35
IRDY# GND IRDY# GND
B36 A36 B36 A36 TRDY#
+3.3V TRDY# TRDY# 9,17,23,34 +3.3V TRDY#
9,17,23,34 DEVSEL# B37 A37 DEVSEL# B37 A37
DEVSEL# GND DEVSEL# GND
B38 A38 S T O P # 9,17,23,34 B38 A38 STOP#
GND STOP# GND STOP#
9,23,34 P L O C K # B39 A39 PLOCK# B39 A39
LOCK# +3.3V LOCK# +3.3V
23,34 P E R R # B40 A40 SDONE_P1 PERR# B40 A40 SDONE_P2
PERR# SDONE PERR# SDONE
B41 A41 SBO_P1 B41 A41 SBO_P2
+3.3V SBO# +3.3V SBO#
9,17,23,34 SERR# B42 A42 SERR# B42 A42
SERR# GND SERR# GND
B43 A43 P A R 9,17,23 B43 A43 PAR
+3.3V PAR +3.3V PAR
C/BE#1 B44 A44 AD15 C/BE#1 B44 A44 AD15
C/BE#(1) AD(15) C/BE#(1) AD(15)
B45 A45 B45 A45
AD(14) +3.3V AD(14) +3.3V
AD14 B46 A46 AD13 AD14 B46 A46 AD13
AD12 B47 A47 AD11 AD12 B47 A47 AD11
AD(12) AD(11) AD(12) AD(11)
AD10 B48 A48 AD10 B48 A48
AD(10) GND AD(10) GND
B49 A49 AD9 B49 A49 AD9
AD8 B52
AD(8)
KEY C/BE#(0)
A52 C/BE#0 AD8 B52
AD(8)
KEY C/BE#(0)
A52 C/BE#0
AD7 B53 A53 AD7 B53 A53
AD(7) +3.3V AD(7) +3.3V
B54 A54 AD6 B54 A54 AD6
+3.3V AD(06) +3.3V AD(06)
AD5 B55 A55 AD4 AD5 B55 A55 AD4
AD(5) AD(04) AD(5) AD(04)
AD3 B56 A56 AD3 B56 A56
AD(3) GND AD(3) GND
B57 A57 AD2 B57 A57 AD2
AD1 B58 A58 AD0 AD1 B58 A58 AD0
AD(1) AD(00) AD(1) AD(00)
B59 A59 B59 A59
+5V +5V +5V +5V
PU1_REQ64# B60 A60 PU1_ACK64# PU2_REQ64# B60 A60 PU2_ACK64#
ACK64# REQ64# ACK64# REQ64#
B61 A61 B61 A61
C +5V +5V +5V +5V C
B62 A62 B62 A62
+5V +5V +5V +5V
PCI_CONN PCI_CONN
9,17,23 C/BE#[3:0]
9,17,23 AD[31:0]
C23
PRSNT#11
VCC R141
0.1 uF AD26 R_AD26
VCC C24 R142 100

RP3
PRSNT#12 PU1_ACK64#
SDONE_P1 1 8 R143
SDONE_P2 2 7 0.1 uF R144 2.7K AD27 R_AD27
SBO_P1 3 6 PU1_REQ64#
SBO_P2 4 5 C25 100
PRSNT#21 2.7K R145
5.6K PU2_ACK64#
0.1 uF
D R146 2.7K D
C26 PU2_REQ64#
PRSNT#22 INTEL CORPORATION
2.7K
0.1 uF
P L A T F O R M COMPONENTS DIVISION
1 9 0 0 P R A I R I E CITY RD. FM5-62
FOLSOM, CA 95630
Title
P C I CONNECTORS 1 & 2

1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
VCC3
PCI CONNECTORS VCC3
-12V VCC
VCC3
3 AND 4 -12V VCC
VCC3
+12V +12V
VCC VCC
A J11 J12 A
B1 A1 PTRST# 22 B1 A1 PTRST#
-12V TRST# -12V TRST#
22 PTCK B2 A2 PTCK B2 A2
TCK +12V TCK +12V
B3 A3 B3 A3 PTMS
GND TMS PTMS 22 GND TMS
B4 A4 B4 A4 PTDI
TDO TDI PTDI 2 2 TDO TDI
B5 A5 B5 A5
+5V +5V +5V +5V
B6 A6 B6 A6 PIRQ#D
+5V INTA# PIRQ#C 18,19,22,34 +5V INTA#
B7 A7 PIRQ#A B7 A7 PIRQ#B
18,19,22,34 PIRQ#D INTB# INTC# PIRQ#A 18,19,21,22,34 INTB# INTC#
18,19,21,22,34 PIRQ#B B8 A8 PIRQ#C B8 A8
INTD# +5V INTD# +5V
B10 A10 B10 A10
RSV +5V RSV +5V
B12 A12 B12 A12
GND GND GND GND
B13 A13 B13 A13
B14 GND GND A14 B14 GND GND A14
RSV RSV RSV RSV
B15 A15 PCIRST# 8,17,21,22 B15 A15 PCIRST#
GND RESET# GND RESET#
7 PCLK3 B16 A16 7 PCLK4 B16 A16
CLK +5V CLK +5V
B17 A17 B17 A17
GND GNT# P G N T # 2 9,34 GND GNT# P G N T # 3 9,34
9,17,34 P R E Q # 2 B18 A18 9,17,34 PREQ#3 B18 A18
REQ# GND REQ# GND
B19 A19 PCI_PME# B19 A19
+5V PME# +5V PME# PCI_PME# 18,22,34
AD31 B20 A20 AD30 AD31 B20 A20 AD30
AD(31) AD(30) AD(31) AD(30)
AD29 B21 A21 AD29 B21 A21
AD(29) +3.3V AD(29) +3.3V
B22 A22 AD28 B22 A22 AD28
AD27 B23 A23 AD26 AD27 B23 A23 AD26
B24 AD(27) AD(26) A24 B24 AD(27) AD(26) A24
AD25 AD(25) GND AD25 AD(25) GND
B25 A25 AD24 B25 A25 AD24
+3.3V AD(24) +3.3V AD(24)
C/BE#3 B26 A26 R_AD29 C/BE#3 B26 A26 R_AD31
C/BE#3) IDSEL C/BE#3) IDSEL
B27 A27 B27 A27
AD(23) +3.3V AD(23) +3.3V
AD23 B28 A28 AD22 AD23 B28 A28 AD22
AD21 B29 A29 AD20 AD21 B29 A29 AD20
AD(21) AD(20) AD(21) AD(20)
AD19 B30 A30 AD19 B30 A30
B AD(19) GND AD(19) GND B
B31 A31 AD18 B31 A31 AD18
+3.3V AD(18) +3.3V AD(18)
AD17 B32 A32 AD16 AD17 B32 A32 AD16
AD(17) AD(16) AD(17) AD(16)
C/BE#2 B33 A33 C/BE#2 B33 A33
B34 C/BE#(2) +3.3V A34 B34 C/BE#(2) +3.3V A34
GND FRAME# FRAME# 9,17,22,34 GND FRAME# FRAME#
9,17,22,34 IRDY# B35 A35 IRDY# B35 A35
IRDY# GND IRDY# GND
B36 A36 B36 A36 TRDY#
+3.3V TRDY# TRDY# 9,17,22,34 +3.3V TRDY#
9,17,22,34 DEVSEL# B37 A37 DEVSEL# B37 A37
DEVSEL# GND DEVSEL# GND
B38 A38 S T O P # 9,17,22,34 B38 A38 STOP#
GND STOP# GND STOP#
9,22,34 P L O C K # B39 A39 PLOCK# B39 A39
LOCK# +3.3V LOCK# +3.3V
22,34 P E R R # B40 A40 SDONE_P3 PERR# B40 A40 SDONE_P4
PERR# SDONE PERR# SDONE
B41 A41 SBO_P3 B41 A41 SBO_P4
+3.3V SBO# +3.3V SBO#
9,17,22,34 SERR# B42 A42 SERR# B42 A42
SERR# GND SERR# GND
B43 A43 P A R 9,17,22 B43 A43 PAR
+3.3V PAR +3.3V PAR
C/BE#1 B44 A44 AD15 C/BE#1 B44 A44 AD15
C/BE#(1) AD(15) C/BE#(1) AD(15)
B45 A45 B45 A45
AD(14) +3.3V AD(14) +3.3V
AD14 B46 A46 AD13 AD14 B46 A46 AD13
AD12 B47 A47 AD11 AD12 B47 A47 AD11
AD(12) AD(11) AD(12) AD(11)
AD10 B48 A48 AD10 B48 A48
AD(10) GND AD(10) GND
B49 A49 AD9 B49 A49 AD9
AD8 B52
AD(8)
KEY C/BE#(0)
A52 C/BE#0 AD8 B52
AD(8)
KEY C/BE#(0)
A52 C/BE#0
AD7 B53 A53 AD7 B53 A53
AD(7) +3.3V AD(7) +3.3V
B54 A54 AD6 B54 A54 AD6
+3.3V AD(06) +3.3V AD(06)
AD5 B55 A55 AD4 AD5 B55 A55 AD4
AD(5) AD(04) AD(5) AD(04)
AD3 B56 A56 AD3 B56 A56
AD(3) GND AD(3) GND
B57 A57 AD2 B57 A57 AD2
AD1 B58 A58 AD0 AD1 B58 A58 AD0
AD(1) AD(00) AD(1) AD(00)
B59 A59 B59 A59
+5V +5V +5V +5V
PU3_REQ64# B60 A60 PU3_ACK64# PU4_REQ64# B60 A60 PU4_ACK64#
ACK64# REQ64# ACK64# REQ64#
B61 A61 B61 A61
C +5V +5V +5V +5V C
B62 A62 B62 A62
+5V +5V +5V +5V
PCI_CONN PCI_CONN
9,17,22 C/BE#[3:0]
9,17,22 AD[31:0]
C27
PRSNT#31
VCC
0.1 uF R147
AD29 R_AD29
C28 R148
PRSNT#32 PU3_ACK64# 100
VCC
RP4
0.1 uF R149 2.7K R150
SDONE_P3 1 8 PU3_REQ64# AD31 R_AD31
SDONE_P4 2 7 C29
SBO_P3 3 6 PRSNT#41 2.7K R151 100
SBO_P4 4 5 PU4_ACK64#
0.1 uF
D R152 2.7K D
5.6K
C30 PU4_REQ64#
PRSNT#42 INTEL CORPORATION
2.7K
0.1 uF
FOLSOM, CA 95630
Title
P C I CONNECTORS 3 & 4


1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
VCC
R153
A A
1K
ISA SLOTS 0 & 1
VCC
R154
1K
VCC
VCC
J13 J14
B1 A1 IOCHK# 17,35 B1 A1 IOCHK#
B2 GND IOCHK# A2 B2 GND IOCHK# A2
32 B R S T D R V BRSTDRV SD7 S D 7 17,20,35 BRSTDRV BRSTDRV SD7 SD7
-5V B3 A3 B3 A3 SD6
VCC SD6 S D 6 17,20,35 VCC SD6
18,19,20,35 IRQ9 B4 A4 S D 5 17,20,35 -5V IRQ9 B4 A4 SD5
-12V IRQ9 SD5 IRQ9 SD5
B5 A5 S D 4 17,20,35 B5 A5 SD4
B6 -5V SD4 A6 -12V B6 -5V SD4 A6
18,20,35 D R Q 2 DREQ2 SD3 S D 3 17,20,35 DRQ2 DREQ2 SD3 SD3
+12V B7 A7 B7 A7 SD2
-12V SD2 S D 2 17,20,35 -12V SD2
17,35 Z E R O W S # B8 A8 S D 1 17,20,35 +12V ZEROWS# B8 A8 SD1
ZEROWS# SD1 ZEROWS# SD1
B9 A9 S D 0 17,20,35 B9 A9 SD0
B10 +12V SD0 A10 B10 +12V SD0 A10
GND IOCHRDY I O C H R D Y 17,20,35 GND IOCHRDY IOCHRDY
17 S M E M W# B11 A11 AEN 17,20 S M E M W# B11 A11 AEN
B12 S M E M W# AEN A12 B12 S M E M W# AEN A12
17 S M E M R# S M E M R# SA19 SA19 17,27,35 S M E M R# S M E M R# SA19 SA19
17,20,35,39 IOW# B13 A13 SA18 17,27,35 IOW# B13 A13 SA18
B14 IOW# SA18 A14 B14 IOW# SA18 A14
17,20,35,39 IOR# IOR# SA17 SA17 17,27,35 IOR# IOR# SA17 SA17
B 18,20 DACK#3 B15 A15 SA16 17,27,35 DACK#3 B15 A15 SA16 B
B16 DACK3# SA16 A16 B16 DACK3# SA16 A16
18,20,35 D R Q 3 DREQ3# SA15 SA15 17,20,27,35 DRQ3 DREQ3# SA15 SA15
18,20 DACK#1 B17 A17 SA14 17,20,27,35 DACK#1 B17 A17 SA14
B18 DACK1# SA14 A18 B18 DACK1# SA14 A18
18,20,35 D R Q 1 DREQ1 SA13 SA13 17,20,27,35 DRQ1 DREQ1 SA13 SA13
17,35 R E F R E S H # B19 A19 SA12 17,20,27,35 REFRESH# B19 A19 SA12
B20 REFRESH# SA12 A20 B20 REFRESH# SA12 A20
17,39 S Y S C L K SYSCLK SA11 SA11 17,20,27,35 SYSCLK SYSCLK SA11 SA11
18,19,20,35 IRQ7 B21 A21 SA10 17,20,27,35 IRQ7 B21 A21 SA10
B22 IRQ7 SA10 A22 B22 IRQ7 SA10 A22
18,19,20,35 IRQ6 IRQ6 SA9 SA9 17,20,27,35 IRQ6 IRQ6 SA9 SA9
18,19,20,35 IRQ5 B23 A23 SA8 17,20,27,35 IRQ5 B23 A23 SA8
18,19,20,35 IRQ4 IRQ4 SA7 SA7 17,20,27,35 IRQ4 IRQ4 SA7 SA7
18,19,20,35 IRQ3 B25 A25 SA6 17,20,27,35 IRQ3 B25 A25 SA6
18,20 DACK#2 DACK2# SA5 SA5 17,20,27,35 DACK#2 DACK2# SA5 SA5
18,20 T C B27 A27 SA4 17,19,20,27,35 TC B27 A27 SA4
B28 TC SA4 A28 B28 TC SA4 A28
17 BALE BALE SA3 SA3 17,20,27,35 BALE BALE SA3 SA3
B29 A29 SA2 17,20,27,35,39 B29 A29 SA2
B30 VCC SA2 A30 NS1 B30 VCC SA2 A30
7 OSC1 OSC SA1 SA1 17,19,20,27,35,39 OSC1 OSC SA1 SA1
B31 A31 TBD B31 A31 SA0
GND SA0 SA0 17,19,20,27,35,39 GND SA0
17,35 M E M C S 1 6# D1 C1 S B H E # 17 M E M C S 16# D1 C1 SBHE#

M E M C S 1 6# SBHE# M E M C S 1 6# SBHE#
17,35 IOCS16# D2 C2 LA23 17,35 IOCS16# D2 C2 LA23
D3 IOCS16# LA23 C3 D3 IOCS16# LA23 C3
18,19,20,35 IRQ10 IRQ10 LA22 LA22 17,35 IRQ10 IRQ10 LA22 LA22
18,19,20,35 IRQ11 D4 C4 LA21 17,35 **NOTE** DEFAULT NO STUFF. IRQ11 D4 C4 LA21
D5 IRQ11 LA21 C5 D5 IRQ11 LA21 C5
18,19,20,35 IRQ12 IRQ12 LA20 LA20 17,35 IRQ12 IRQ12 LA20 LA20
18,19,20,25,35 IRQ15 D6 C6 THIS CAP USED TO FILTER IRQ15 D6 C6 LA19
IRQ15 LA19 LA19 17,35 IRQ15 LA19
18,19,20,25,35 IRQ14 D7 C7 LA18 17,35 NOISE ON TC SIGNAL IRQ14 D7 C7 LA18
IRQ14 LA18 IRQ14 LA18
18,20 DACK#0 D8 C8 LA17 17,35 DACK#0 D8 C8 LA17
D9 DACK0# LA17 C9 D9 DACK0# LA17 C9
18,20,35 D R Q 0 DREQ0 MEMR# M E M R # 17,19,27,35 DRQ0 DREQ0 MEMR# M E M R#
18 DACK#5 D10 C10 M E M W # 17,19,27,35 DACK#5 D10 C10 M E M W#
D11 DACK5# MEMW# C11 D11 DACK5# MEMW# C11
18,35 D R Q 5 DREQ5 SD8 S D 8 17,35 DRQ5 DREQ5 SD8 SD8
C
18 DACK#6 D12 C12 S D 9 17,35 DACK#6 D12 C12 SD9 C
D13 DACK6# SD9 C13 D13 DACK6# SD9 C13
18,35 D R Q 6 DREQ6 SD10 S D 1 0 17,35 DRQ6 DREQ6 SD10 SD10
18 DACK#7 D14 C14 S D 1 1 17,35 DACK#7 D14 C14 SD11
D15 DACK7# SD11 C15 D15 DACK7# SD11 C15
18,35 D R Q 7 DREQ7 SD12 S D 1 2 17,35 DRQ7 DREQ7 SD12 SD12
D16 C16 S D 1 3 17,35 D16 C16 SD13
D17 VCC SD13 C17 D17 VCC SD13 C17
35 R M A S T E R # M A S T E R# SD14 S D 1 4 17,35 R M A S T E R# M A S T E R# SD14 SD14
D18 C18 S D 1 5 17,35 D18 C18 SD15
GND SD15 GND SD15
CON_ISA16C CON_ISA16C
C31 ISA 0 ISA 1

47pF
C32
47pF
D D
INTEL CORPORATION

FOLSOM, CA 95630
Title
ISA SLOTS


1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
A A
IDE CONNECTORS
1 7 SDD[15:0]
1 7 PDD[15:0]
J15 J16
R155 R156
R_BRSTDRV#1 1 2 BRSTDRV# R_BRSTDRV#2 1 2
32 BRSTDRV#
33 33
DD7#1 3 4 DD8#1 DD7#2 3 4 DD8#2
RP5 DD6#1 5 6 DD9#1 RP6 RP7 DD6#2 5 6 DD9#2 RP8

PDD7 1 16 1 16 PDD8 SDD7 1 16 1 16 SDD8
PDD6 2 15 DD5#1 7 8 DD10#1 2 15 PDD9 SDD6 2 15 DD5#2 7 8 DD10#2 2 15 SDD9
PDD5 3 14 3 14 PDD10 SDD5 3 14 3 14 SDD10
B B
PDD3 5 12 5 12 PDD12 SDD3 5 12 5 12 SDD12
PDD1 7 10 7 10 PDD14 SDD1 7 10 7 10 SDD14
VCC VCC
33 DD1#1 15 16 DD14#1 33 33 R391 DD1#2 15 16 DD14#2 33
R390 R158 10K
R157 10K DD0#1 17 18 DD15#1 1K DD0#2 17 18 DD15#2
1K
19 20 19 20
R159 R160
17 PDREQ R_PDDREQ# 21 22 17 SDREQ R_SDDREQ# 21 22
33 R161 33 R162
17 PDIOW# R_PDIOW# 23 24 17 SDIOW# R_SDIOW# 23 24
R163 33 R164 33
1 7 PDIOR# R_PDIOR# 25 26 1 7 SDIOR# R_SDIOR# 25 26
33 R375 R165 33 R376 R166
1 7 PIORDY 27 28 PRI_PD1 1 7 SIORDY 27 28 SEC_PD1
47 470 47 470
RP9 29 30 RP10 29 30
17 P D D A C K # 1 8 RPDACK# 17 S D D A C K # 1 8 RSDACK#
2 7 31 32 2 7 31 32
PDA1 3 6 R_PDA1 SDA1 3 6 R_SDA1
R167 R168
PDA0 4 5 R_PDA0 33 34 PDA2 SDA0 4 5 R_SDA0 33 34 SDA2
33 33
33 35 36 R_PDA2 33 35 36 R_SDA2
R169 R170 PCS3# 17 R171 R172
17 PCS1# R_PCS1# 37 38 R_PCS3# 17 SCS1# R_SCS1# 37 38 R_SCS3# SCS3# 17
33 33 33 33
32 IDEACTP# 39 40 32 IDEACTS# 39 40
C C
1 7 PDA[2:0] 1 7 SDA[2:0]
PRIMARY SECONDARY
R377 IDE CONN. R378
18,19,20,24,35 IRQ14 18,19,20,24,35 IRQ15 RIRQ15 IDE CONN.
R173 47 R174 47
5.6K 5.6K
D D
INTEL CORPORATION
FOLSOM, CA 95630
Title
P C I IDE CONNECTORS


1 2 3 4 5 6 7 8
A B C D E
F1
VCC USB_PWR0
1.5-2.0A R175
470K
18 O C # 0
BLM31A700S USB CONNECTORS
1 L1
4 4
C33 2
R176
0.001uF 560K
+
C34 C35
68 uF (TANTALUM) J17
0.1 uF
USBV0 1
VCC
5 UGND0
5
USBD0- 2
DATA-
BLM31A700S USBD0+ 3
DATA+
F2 6
6
VCC USB_PWR1 1 L4 2 USBG0 4
GND
2
1.5-2.0A + L2
R177
2
C38 C39
470K USB_CON_0.0
68 uF (TANTALUM) 0.1 uF C36
R289 L3
18 O C # 1 470 pF BLM31A700S
0
1
BLM31A700S
VCC3 C37
R178
1
3 0.001uF 560K J18
3
R290
R380 0 USBV1 1
VCC
330K 5 UGND1
5
USBD1- 2
DATA-
USBD1+ 3
DATA+
21 A G P _ O C # DO NOT STUFF 6
6
USBG1 4
GND
2
L5
2
R126 USB_CON_0.0
18 USBP0- C40
27 470 pF L6 BLM31A700S
R125
18 U S B P 0 +
1
27 BLM31A700S
1
R124 R179
18 USBP1-
27 0
R123 R180
18 U S B P 1 +
2 27 0 2
R181 R182 R183 R184

**NOTE: C11 C10 C9 C8
15K 15K 15K 15K
PLACE R123-126 AND R_USBD1+
R185
U S B A G P + 21
C8-11 AS CLOSE AS 47pF 47pF 47pF 47pF 0
POSSIBLE TO THE DO NOT STUFF
PIIX4. R186
R_USBD1- U S B A G P - 21
0
NOTE: USE PIIX4

APPLICATION
NOTE FOR
LAYOUT
GUIDELINES
INTEL CORPORATION
1 PLATFORM COMPONENTS DIVISION 1

FOLSOM, CA 95630
Title
USB HEADER


A B C D E
1 2 3 4 5 6 7 8
A A
STUFFING OPTION
VCC
JP21
SYSTEM RO M SA19
2
4
1
3
SA16 SA18
6 5
SA15 SA17
8 7
SA12 SA14
10 9
SA7 SA13
12 11
SA6 SA8
14 13
SA5 SA9
MODE JP20 SA4
16 15 SA11
18 17
SA3 M E M W#
NORMAL 1-2 SA2
20 19
SA10
U16A 22 21
SA1 BIOSCS#
RECOVERY 24 23
2-3 SA0 XD7
1 2 26 25
B_SA17 XD0 XD6
28 27
JP20 XD1 XD5
30 29
1 XD2 XD4
2 32 31 XD3
74HCT14 J_SA17 34 33
SA17 3
Emulator Header
FLASH SOCKET
B 17,19,20,24,35,39 SA[19:0] XD[7:0] 19,20,39 B
U17
40 12
SA17
SA16 1 A17 DU * Header provided for BIOS emulation
A16
SA15 2
3 A15
SA14 A14
SA13 4
MODE JP22 JP23 SA12 5 A13
A12
Prog Boot Block 1-2 SA11 6
2-3 SA10 36 A11 25 XD0
+12V A10 DQ0
PROG DEV SA9 7 26 XD1
(incl. boot block) 1-2 1-2 SA8 8 A9 DQ1 27 XD2
A8 DQ2
SA7 14 28 XD3
PnP 2-3 1-2 SA6 15 A7 DQ3 32 XD4
A6 DQ4
Write Protect SA5 16 33 XD5
2-3 2-3 SA4 17 A5 DQ5 34 XD6
A4 DQ6
JP22 SA3 18 35 XD7
1 19 A3 DQ7
SA2 A2
2 SA1 20 13 +12V
3 21 A1 NC 29
3,5,32 P W R G O O D R_RP# SA0 A0 NC
37
9 NC 38
17,19,24,35 M E M W# JP23
WE# NC
17,19,24,35 M E M R# 24 1
22 OE# 11 2
CE# VPP FL_VPP
FL2MPU 10 3 FL1MPU
RP#
E 2 8 F 0 0 2 B C -T
TSOP SOCKET
C C
C41
0.01 uF
C42
0.01 uF
18 BIOSCS#
D D
INTEL CORPORATION

FOLSOM, CA 95630
Title
S Y S T E M R OM


1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
C43
180pF
A A
C44
180pF
C45
180pF
VCC
C46
180pF
D4
IN4148 C47
180pF
PAR5VOLTS
20 PDR[7:0] 5
RP11
4
C48
180pF PARALLEL HEADER
6 3
7 2 C49 J19
8 1 180pF STB# 1
B B
AFD# 14
RP12 1K PD0 2
PDR0 5 4 ERR# 15
20 AFD#R 6 3 PD1 3
20 STB#R 7 2 INIT# 16
20 INIT#R 8 1 C50 PD2 4
180pF SLIN# 17
33 PD3 5
RP13 C51 18
5 4 180pF PD4 6
6 3 19
7 2 PD5 7
PDR3 8 1 20
PD6 8
RP14 1K 21
PDR2 5 4 C52 PD7 9
20 SLIN#R 6 3 180pF 22
PDR1 7 2 ACK# 10
8 1 C53 23
180pF BUSY 11
33 24
PE 12
25
RP15 SLCT 13
1 8
2 7 C54
3 6 180pF C ONNECTOR DB25
4 5
C55
C
RP16 1K 180pF C
PDR7 5 4
PDR6 6 3
PDR5 7 2
PDR4 8 1
33 C56
RP17 180pF
5 4
6 3 C57
7 2 180pF
8 1
1K
20 ERR#
20 SLCT
20 PE C58
20 BUSY 180pF
20 ACK#
RP18
1 8
2 7
3 6
4 5 C59
180pF
1K
D D
INTEL CORPORATION

FOLSOM, CA 95630
Title
PARALLEL PORT


1 2 3 4 5 6 7 8
A B C D E
+12V VCC
J20
U18 SP_DCD0
1 20 1
VCC+ VCC S P _ RXD0 2
SP_DCD0 2 19 RLSD0# 20 SP_TXD0
RA RY 3
S P _ R XD0
SP_DSR0
3
4 RA RY
18
17
RX0 20 S P _ D TR0 4 COM 0
RA RY DSR0# 20 5
5 16 S P _ D S R0
4
S P _ D T R0
S P _TXD0 6 DY
DY
DA
DA
15
DTR0# 20
TX0 2 0 S P _ RTS0
6
7
HEADER 4
S P _ C TS0 7 14 S P _ CTS0
RA RY C T S 0# 2 0 8
S P _ R TS0 8 13 SP_RI0
DY DA R T S 0# 2 0 9
SP_RI0 9 12 RI0# RI0# 20
10 RA RY 11 HEADER 9
VCC- GND
G D 7 5 2 3 2SOP C60 C61
100pF 100pF
-12V C62 C63

100pF 100pF
C64 C65
100pF 1 0 0 pF
C66 C67
1 0 0 pF 100pF
3 3
+12V VCC
U19 J21
1 20 SP_DCD1
2 VCC+ VCC 19 1
SP_DCD1 S P _ RXD1
S P _ R XD1 3
4
RA
RA
RY
RY
18
17
RLSD1# 20
RX1 20 SP_TXD1
2
3
COM 1
SP_DSR1 RA RY DSR1# 20 S P _ D TR1 4
S P _ D T R1 5 16
S P _TXD1 6 DY
DY
DA
DA
15
DTR1# 20
TX1 2 0 S P _ D S R1
5
6
HEADER
S P _ C TS1 7 14 S P _ RTS1
RA RY C T S 1# 2 0 7
S P _ R TS1 8 13 S P _ CTS1
DY DA R T S 1# 2 0 8
SP_RI1 9 12 RI1# SP_RI1
RA RY RI1# 20 9
10 11
VCC- GND
HEADER 9
G D 7 5 2 3 2SOP
C68 C69
100pF 100pF
-12V
C70 C71
C72 C73 100pF 100pF
100pF 1 0 0 pF
2 2
VCC C74 C75

1 0 0 pF 100pF
RP19
5 4
6 3
7 2
8 1 FLOPPY
1K INTERFACE
R189
1.0K
HEADER
G P I 21 18
J22 **NOTE** Connected to
20 DSKCHG# 34 33 GPI21 of the PIIX4 for BIOS
20 SIDE1# 32 31
20 R D A T A# 30 29 detection of a floppy drive.
20 W P T# 28 27
2 0 T R K 0# 26 25
2 0 W G ATE# 24 23
2 0 W D A T A# 22 21
2 0 S T EP# 20 19
20 DIR# 18 17
20 M O TEB# 16 15
20 DRVSA# 14 13
1 20 D R V S B # 12 11 1
20 M O TEA# 10 9 INTEL CORPORATION
20 INDEX# 8 7
20 D R A T E0 6 5 PLATFORM COMPONENTS DIVISION
1 T P 094
TP27 4 3 1900 PRAIRIE CITY RD. FM5-62
20 REDWC# 2 1 FOLSOM, CA 95630
Title
SERIAL AND FLOPPY


A B C D E
1 2 3 4 5 6 7 8
VCC
A A
STUFFING F3 F4
1 . 25A 1 . 35A
OPTION
KB5V
2
L7
BLM31A700S
1
L8 J23
B 20 KBDAT# 2 1 K B DAT_FB# B
1
1 TP095
TP28 2
BLM31A700S K B S I GND 3 KEYBOARD
KB5V_FB 4
KBCLK_FB# 5
CONNECTOR
L9 1
TP29 TP096 6
20 KBCLK# 2 1
7
8
BLM31A700S 9
L10 J24
20 MSDAT# 2 1 MSDAT_FB# 1
TP30
1 TP097 2 M O USE
BLM31A700S 3 CONNECTOR
4
MSCLK_FB# 5
L11 1
TP31 TP098 6
20 MSCLK# 2 1
7
8
BLM31A700S 9
C76 C77 C78 C79

C
470pf 470pF 470pF 470pF C80 C
0.1 uF K B S H G ND
1
L12
BLM31A700S
2
L13
BLM31A700S
D D
Title
K E Y B O A R D / M O U S E INTERFACE


1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
4 VID_A[4:0] 6 V I D _ B [ 4 :0]
V C C C O RE1 V C C C O RE2
+12V +12V
+12V +12V
VCC VCC VCC3 VCC3 VCC VCC VCC3 VCC3

J25 J26
A A1 B1 A1 B1 A
5 V in 5Vin 5 V in 5Vin
A2 B2 R190 A2 B2 R192
5 V in 5Vin 10K R191 5 V in 5Vin 10K R193
A3 B3 10K A3 B3 10K
5 V in 5Vin 5 V in 5Vin
A4 B4 A4 B4
1 2 Vin 12VIN 1 2 Vin 12VIN
A5 B5 A5 B5
1 2 Vin RES. 1 2 Vin RES.
A6 B6 R O E1 A6 B6 ROE1
ISHARE OUTEN ISHARE OUTEN
V I D _ A0 A7 B7 V I D _ A1 VRM1_PGD 32 VID_B0 A7 B7 VID_B1 VRM2_PGD 32
VID0 VID1 VID0 VID1
V I D _ A2 A8 B8 V I D _ A3 VID_B2 A8 B8 VID_B3
VID2 VID3 V C C C O RE1 VID2 VID3 V C C C O RE2
V I D _ A4 A9 B9 VID_B4 A9 B9
VID4 PWRGD VID4 PWRGD
A10 B10 A10 B10
V C C c ore Vss V C C c ore Vss
A11 B11 A11 B11
Vss VCCcore Vss VCCcore
A12 B12 A12 B12
A13 B13 A13 B13
A14 B14 A14 B14
B B
A15 B15 A15 B15
A16 B16 A16 B16
A17 B17 A17 B17
A18 B18 A18 B18
A19 B19 **NOTE** A VRM should not A19 B19
A20
V C C c ore Vss
B20 be installed if a processor is A20
V C C c ore Vss
B20
not installed unless
VRM8_2.05 V R M x _ P G D i s a s s e r t e d b y the VRM8_2.05
VRM with a VID = 1111. If not
asserted by the VRM, then
circuitry must be provided to
the block VRMx_PGD for the
unpopulated Slot 1.
VCC3
C C
+12V VR1
2.5V REGULATOR
VTT V25_G1 1
S/D IPOS
8
4
2
VCC3 VTT
REGULATOR 2 7
VR2 VIN INEG Q1 V C C 2 .5
2 3 6 R194 1
VOUT GND GATE V 2 5_R1 V2G
C81 MMFT3055EL
1.0 uF 10
3 + 4 5 V25_R2
VIN FB COMP
3
C82 C E R A M IC C83
2 2 uF C114 X7R R195 1.0 uF
C84 + 1 16V 1.0 uF
GND LT1575_0.1
2 2 uF 20% 100 +
16V (Solid Tantalum) C87
LT1585A-1.5 R196
20% C85 V25_R3 C86 22uF
(Solid Tantalum) **NOTE** 1 . 0 uF 1 . 0 uF 16V
1.30K
V2R
C E R A MIC 20%
1. VOLTAGE REGULATOR 1% X7R
SHOULD BE LOCATED NEAR R197
1.21K C88 C89
THE 443BX 1% 2200pF 0 . 0 1 uF
2. 6A OF OUTPUT CURRENT IS NECESSARY

FOR A DP DESIGN. THE LT1585A-1.5 IS ONLY
CAPABLE OF 5A. MAY NEED ANOTHER
REGULATOR.
D D
Title
D C - D C C O N V E R T E R C O NNECTORS


1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
+12V +12V
R392 R393
BRSTDRV# 25
U35A 4.7K 1K
U16B U16C 1 2
18 FAN_LED
Q7
17,20 R S T D R V 3 4 5 6 VCC P-FET
BRSTDRV 24 D9
74F06
A A
R394
74HCT14 74HCT14 U23F POWER LED DUAL-COLOR LED
S P E AKER 330 H E ADER 1N4148
VCC 13 12 R407
R200 J29
1
C181 GREEN 1.2K
VCC 100pF J28
KEY 2 74F07
68 TP32 TP888 3 1
key D10 D11
4 R395 2
R202
U35B 3
SPK2 BUZZ2
330 RED VCC VCC
68 3 4
C182
R203
Q2
74F06 100pF OPTIONAL ATX R397 R199
18 SPKR SPK1
MMBT3904L C93 +12V C P U FAN CONNECTOR U15D
2.2K 0.1 uF H E ADERS J35 4.7K 4.7K
J36 VCC 4 1 9 8
1394M FanM PSFAN 39
3 SENSE 5 1394V FanC 2
6 3
VCC VCC VCC 2 +12V R408
RES Sense
1 Molex 39-30-1060 VCC3 74AS07
GND
640456-3 4.7K
C90 R412
R204 R205 H A RD DRIVE R206 0.1 uF CPUFAN1 39
0
10K 10K 470
LED
CONNECTOR
B B
U20A J31 +12V
1 ILPU1 3VSB
25 IDEACTP# 1 J37
3 VCC
25 IDEACTS# 2
IDE_LED 2
SENSE
ACPI required POWER BUTTON to be
3 3 3VSB
VCC3 4 2 +12V
R409
located on the front of the chassis. 1 4 U11B
74ALS08 1 GND S1
4 HEADER 3 4 PWRBT# 18
R208 C92
640456-3 4.7K
1
C95 C96 0.1 uF SW PUSHBUTTON 7
4.7K CPUFAN2 39
U21A 470pF 470pF R207 C94 74LVC14
JP24 510K 0.1 uF
1 2
4,34 A _ S L O T O C C #
VCC3
VCC3
2
74ALS05
PWR_ON_JMP
VCC3 5VSB
POWER-ON 18
R209 R210
3VSB
4.7K R211
4.7K U22A 240 VCC2.5
U21B 14 U21C
1
3 4 2 12 5 6
6,34 B _ S L O T O C C #
13 R212
74ALS05 7 74ALS05 4.7K
7 DBRESET# R213
74HC10 330
U21D
31 VRM1_PGD
VCC3 5VSB 9 8
PWRGOOD 3,5,27
74ALS05
U20B R214 14 U22B U23A
4 3
4.7K 3VSB
6 4 6 PG4 1 2 PG5
C 5 5 C
31 VRM2_PGD
7
74ALS08 74F07 14 U11C
74HC10
R215 18 B_SUSC
JP_RST 5 6 P W R O K 9,18
100
7
+ +12V 74LVC14
C97 C98 ( + 3 . 3 V) VCC
R E S ET J32 S2 VCC3
PG3
SWITCH
0.01 uF 10uF ATX POWER (+5.0V)
C O NNECTOR V C C
H E ADER 18 WOLLID
R216
J33 8.2K
5VSB 5VSB
1 2
3 4
U16D U16E
Wake-On-LAN
5 6
7 8 PG1 9 8 PG2 11 10 PS_POK 18 U36B 5VSB
Header
7
9 10 J34
11 12 4 3
74HCT14 74HCT14 18,34 LID
13 14 3
3VSB 15 16 2
14
17 18 1
1
19 20 3VSB 74F07
3VSB R416
1K AMP 173981-3
R217 (or Foxconn HF58030)
56 14 U11D 14 U11E
2
-5V **OPTIONAL** WOL support
3
9 8 BRSM1 11 10
D7 + -12V RSMRST# 18 requires 600mA of Stand-By
D C99 C100 7 7 c u rrent. D
MMBZ5226BL 0.01 uF 10uF R218 74LVC14 74LVC14
SOT-23 R_RSMRST#
1
22K INTEL CORPORATION

C101
1.0 uF PLATFORM COMPONENTS DIVISION
R e s ume Reset circuitry 1 9 0 0 PRAIRIE CITY RD. FM5-62
FOLSOM, CA 95630
using a 22 msec delay and
Title
S c h m itt trigger logic. FRONT PANEL


1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
o de}
PROCESSOR BUS/CORE FREQUENCY
A A
VCC3
4
3
2
1
RP20
4 . 7K P r o c e s s o r Core Freq : LINT[1] LINT[0] IGNNE# A20M#
S y s t e m B u s F req JP28 JP27 JP26 JP25
5
6
7
8
U23B L L L
2 L
JP25
KL_CFG1 A20_PB 3 4 A20M# 3 , 5,34 L
3 L H L
JP26 4 L L L H
KL_CFG2 74F07
5 L L H H
JP27 U23C
KL_CFG3 5/2 L L
L H
I G N E_PB 5 6 I G N N E # 3 ,5,34
JP28 7/2 L H L
H
KL_CFG4
B VCC3 74F07 B
R e s e r v ed All Other Combinations, HLLL-HHHL
U24 U23D 2 H H H H
2 18 9 8 LINT0 3 , 5 ,34
1A1 1Y1
4 16
R291 1A2 1Y2
6 14
1A3 1Y3
8 12 74F07
1A4 1Y4
10K 18,34 PX4_A20M# 11 9
2A1 2Y1
18,34 P X 4_IGNNE# 13 7 U23E
2A2 2Y2
18,19,34 P X 4_INTR 15 5 LINT0_PB
2A3 2Y3
18,34 PX4_NMI 17 3 L I NT1_PB 11 10 LINT1 3 , 5 ,34
2A4 2Y4
1
8 C R ESET# 1G
19 74F07
2G VCC3
74FCT3244
R219
330
U 2 1E
11 10 C R ESET 19
74ALS05
3 V SB
C C
14 U11A
1 2 C R S T_STBY 19
7 74LVC14
D D
Title
P R O C E S S O R B U S / C O R E FREQUENCY


1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
VCC3
R222
4,32 A _ S L O T O C C #
RP21 VCC
2 8.2K
22,23 PERR# R1 R223
9,17,22,23 SERR# 3 6,32 B _ S L O T O C C #
R2
9,22,23 PLOCK# 4
R3 8.2K
9,17,22,23 STOP# 5 1
R4 PU VCC2.5
9,17,22,23 DEVSEL# 6
R5
9,17,22,23 TRDY# 7 R292
R6
8
9,17,22,23 IRDY# R7 3,5,18 F E R R #
9,17,22,23 FRAME# 9
R8 220
9 PREQ#4 10 R224
R9
PCI BUS
A 3,5 THERMTRIP# A
2.7K
220
R226
RP22
3,5 TESTHI
18,19,22,23 PIRQ#D 2 VCC
R1 4.7K
18,19,22,23 PIRQ#C 3
R2
18,19,21,22,23 PIRQ#B 4
R3
18,19,21,22,23 PIRQ#A 5 1
R4 PU R227
9,17,23 PREQ#3 6 PICD0
R5
9,17,23 PREQ#2 7
R6 150
9,17,22 PREQ#1 8
R7
9,17,22 PREQ#0 9
R8 R228
10 PICD1
R9 VCC3
3,5,19 PICD[1:0] 150
2.7K
RP23 R229
9 PGNT#4 1 8 3,5 F L U S H #
9,23 PGNT#3 2 7
SLOT 1
3 6 510
9,23 PGNT#2
9,22 PGNT#1 4 5
8.2K
RP24 R230
9,22 P G N T # 0 1 8 3,5,18 STPCLK#
2 7 **NOTE** Resistor values on
3 6 430
R231
4 5 19 APC_SMI#
signals STPCLK#, APC_SMI#,
430 PX4_SMI#, SLP# & HINIT#
8.2K R232
18,19 P X 4 _ S M I # enable an LAI to be used for
430 board debug. If an LAI will not
B R233 B
18,39 P G C S # 1 3,5,18 S L P # be used for debug the resistor
RP25
9,17 PHLD#
2 VCC3 330
R234
values should be changed to 1K
3 R1
9,17 PHLDA#
4
R2 3,5,18 HINIT# ohm.
18 REQ#A R3 330
5 1
18 REQ#B R4 PU
18 REQ#C 6
R5
7 RP26
18,19 APICREQ# R6
8 2 VCC2.5
3,5,18 THERM# R7 3,5,33 A 2 0 M # R1
9 3,5,33 IGNNE# 3
18,20 A20GATE R8 R2
10 4
18,20 KBRST# R9 R3
3,5,33 LINT0 5 1
R4 PU
8.2K 3,5,33 LINT1 6
R5
7
R6
RP27 8
3VSB R7
18 TEST# 2 9
R1 R8
3 10
18 SMBALERT# R2 R9
4
18 BATLOW# R3
18,22,23 PCI_PME# 5 1 330
R4 PU
6
18,32 LID R5
7
18,39 EXTSMI# R6 VCC3
8
18 PX4_CFG1 R7
9
R8
10
R9 R235
21 GPERR#
8.2K 8.2K R236
21 GSERR#
R237 8.2K
9,21 G S T O P #
8.2K R239
C 9,21 G D E V S E L # C
R241 8.2K
VCC3
9,21 GTRDY#
R238 AGP 8.2K R243
PIIX4
18,19 A P I C C S # 9,21 GIRDY#

R240 8.2K R244 8.2K
3,5,8,15,16,18,39 SMBDATA 9,21 G F R A M E #
2.7K R242 8,2K R245
3,5,8,15,16,18,39 SMBCLK 9,21 A D S T B - A
2.7K R246 8.2K
9,21 A D S T B - B
RP29 8.2K R247
18,19,33 PX4_INTR 1 8 9,21 S B S T B
2 7 8.2K
18,33 P X 4 _ I G N N E #
18,33 P X 4 _ A 2 0 M # 3 6
4 5
18,33 P X 4 _ N M I R249
9,21 G G N T #
1 8 GPI[20:13] 2.7K R250 8.2K
RP30
9,21 G R E Q #
GPI13 1 8 8.2K R251
GPI14 2 7 9,21 P I P E #
GPI15 3 6 8.2K
R252
GPI16 4 5
9,21 R B F #
8.2K
2.7K 3VSB
R411
RP31
18,21 A G P _ P M E #
GPI17 1 8 8.2K
GPI18 2 7
R248
GPI19 3 6
9,21 G P A R
GPI20 4 5 100K
2.7K
D RP32 D
1 8
1 8 GPI7 2 7
INTEL CORPORATION
3 6
4 5
2.7K FOLSOM, CA 95630
Title
BUS RESISTORS


1 2 3 4 5 6 7 8
A B C D E
U N U S ED GATES
3VSB
4
VCC U21F 14
4 13 12 5 6 4
3VSB R253 U20C 74ALS05 7

R254 17,24 IOCHK# 9 U13B
18,19 IRQ#8 8
4.7K 10 U16F 74LVC125
8.2K
R255 74ALS08 13 12
VCC 17,24 ZEROWS#
10
1K U20D 74HCT14 14
RP33 12
18,19,20,24 IRQ12 1 8 R256 11 9 8
18,19,20,24,25 IRQ14 2 7 17,20,24 IOCHRDY 13
18,19,20,24,25 IRQ15 3 6 7
4 5 1K 74ALS08 U13C
R257 74LVC125
8.2K
24 RMASTER# U35C
1K
RP34 VCC 5 6
13
2 R258 U15A 14
18,19,20 IRQ1 R1
18,19,20,24 IRQ3 3 17,24 REFRESH#
R2
18,19,20,24 IRQ4 4 74F06 1 2 12 11
R3
18,19,20,24 IRQ5 5 1 1K
R4 PU
18,19,20,24 IRQ6 6 7
R5 U35D
18,19,20,24 IRQ7 7 R259 74AS07 U13D
R6
18,19,20,24 IRQ9 8 17,20,24,39 IOR#
R7 74LVC125
18,19,20,24 IRQ10 9 9 8
R8 U15E
18,19,20,24 IRQ11 10 8.2K
R9
3 3
8.2K R260 74F06 11 10
17,19,24,27 MEMR#
17,20,24 SD[15:0] U35E
8.2K 5VSB
74AS07
RP35 VCC
SD0 2 R261 11 10
R1 U15F U30A
SD1 3 17,24 MEMCS16# 14
R2
SD2 4
R3
SD3 5 1 1K 74F06 13 12 1 2
R4 PU
ISA BUS
SD4 6
R5
SD5 7 R262 7
R6 U35F
SD6 8 17,24 IOCS16# 74AS07 74HCT14
R7
SD7 9
R8
SD8 10 1K 13 12
R9 U30C
14
8.2K
74F06 5 6
17,19,20,24,27,39 SA[19:0] RP36 VCC
RP37 VCC SA19 2 7
SD9 R1
2 SA18 3 74HCT14
SD10 R1 R2
3 SA17 4
SD11 R2 R3
4 SA16 5 1
SD12 R3 R4 PU U30D
5 1 SA15 6 14
SD13 R4 PU R5
6 SA14 7
SD14 R5 R6
7 SA13 8 9 8
SD15 R6 R7
8 SA12 9
R7 R8
17,20,24,39 IOW# 9 SA11 10 7
R8 R9
17,19,24,27 MEMW# 10 74HCT14
R9
8.2K
8.2K 5VSB
RP38 VCC 14 U30E
2 2
SA10 2
R1
SA9 3 11 10
R2
RP39 SA8 4 14 U36C
R3
18,20,24 DRQ0 2 SA7 5 1 7
R1 R4 PU
18,20,24 DRQ1 3 SA6 6 5 6 74HCT14
R2 R5
18,20,24 DRQ2 4 SA5 7
R3 R6
18,20,24 DRQ3 5 1 SA4 8 7
R4 PU R7 U30F
18,24 DRQ5 6 SA3 9 74F07 14
R5 R8
18,24 DRQ6 7 SA2 10
R6 R9
18,24 DRQ7 8 13 12
R7
9 8.2K
R8
10 14 U36D 7
R9 VCC
RP40 74HCT14
5.6K SA1 2 9 8
R1
SA0 3
R2
LA23 4 7
R3
LA22 5 1 74F07
R4 PU
LA21 6
R5
LA20 7
R6
LA19 8
R7
LA18 9 14 U36E
R8
LA17 10
R9
11 10
17,24 LA[23:17] 8.2K
7
74F07
14 U36F
1 1
13 12
7 I N T E L C ORPORATION
74F07
P L A T F O R M C O M P O N E N T S D IVISION
FOLSOM, CA 95630
Title
I S A B U S PULLUPS
Size D ocument Number Rev

Date: Thursday, April 09, 1998 S h e et 35 of 40

A B C D E
1 2 3 4 5 6 7 8
D I M M D E COUPLING
VCC3
VCC3
443BX DECOUPLING
A A
C102
0.1 uF 0.1 uF 0.1 uF +
0.1 uF 0.01 uF
CD1 16V CD2 16V CD3 16V 22uF 16V

CD4 16V CD5 16V
C103
0.1 uF 0.1 uF 0.1 uF + 0.1 uF 0.01 uF
CD6 16V CD7 16V CD8 16V 22uF 16V CD9 16V CD10 16V
0.1 uF 0.01 uF
C104
0.1 uF 0.1 uF 0.1 uF +
CD11 16V CD12 16V
CD13 16V CD14 16V CD15 16V 22uF 16V
0.1 uF 0.01 uF
C105
0.1 uF 0.1 uF 0.1 uF +
CD16 16V CD17 16V
CD18 16V CD19 16V CD20 16V 22uF 16V
0.1 uF 0.1 uF 0.1 uF C116

+
CD21 16V CD22 16V CD85 16V

22uF 16V
B B
0.1 uF 0.1 uF 0.1 uF
CD23 16V CD24 16V CD86 16V
0.1 uF 0.1 uF 0.1 uF
CD87 16V CD88 16V CD89 16V
C
CKBF DECOUPLING CK100 DECOUPLING C
VCC3
VCC3 VCC2.5
C195
+
22uF
CD98 CD99 C171 C178 C179 C180
C196
+ +
0.01 uF 470pF 0.01uF 470pF
16V 16V 22uF 16V 16V 22uF
470pF
C197
0.01uF
D D
INTEL CORPORATION
FOLSOM, CA 95630
Title
D R A M , C L O C K A N D 443BX DECOUPLING CAPACITORS


1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
BULK POWER DECOUPLING
A **MAY NEED TO ADD MORE VCC3 VCC A
DECOUPLING TO VCC3 FOR

THIS DP DESIGN. C106 C107
+ +
22 uF 16V 22 uF 16V
0.1 uF 0.1 uF
CD48 16V CD49 16V
0.1 uF 0.1 uF
CD52 16V CD53 16V 3 VOLT DECOUPLING

VCC3
0.1 uF 0.1 uF
+12v -5v -12v
CD42 16V CD43 16V

C108 C109 C110 0.1 uF 0.1 uF
+ + +
B B
CD44 16V CD45 16V

22 uF 16V 22 uF 16V 22 uF 16V
0.1 uF 0.1 uF
0.1 uF 0.1 uF 0.1 uF
CD46 16V CD47 16V

CD62 16V CD63 16V CD64 16V
0.1 uF 0.1 uF
CD50 16V CD51 16V
0.1 uF 0.1 uF
CD54 16V CD55 16V
0.1 uF 0.1 uF
CD56 16V CD57 16V
0.1 uF 0.1 uF
CD58 16V CD59 16V
0.1 uF 0.1 uF
C C
CD60 16V CD61 16V
CORE VOLTAGE DECOUPLING 0.1 uF 0.1 uF
CD65 16V CD66 16V

VCCCORE VCCCORE VCCCORE VCCCORE VCC
0.1 uF 0.1 uF
10uF 10uF 100uF 0.01uF CD67 16V CD68 16V
CD100 16V CD101 16V CD102 16V CD103 16V
10uF 10uF 100uF
CD104 16V CD105 16V CD106 16V
10uF 10uF 100uF
CD107 16V CD108 16V CD109 16V
10uF 10uF
CD110 16V CD111 16V
10uF
D D
CD112 16V
INTEL CORPORATION
FOLSOM, CA 95630
Title
3 . 3 V O L T A N D BULK POWER DECOUPLING


1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
A A
**THIS TERMINATION DE COUPLING IS OPTIONAL.
TERMINATION VOLTAGE DE COUPLING

VTT
0.1 uF 0.1 uF
CD69 16V CD70 16V
B B
0.1 uF 0.1 uF
CD71 16V CD72 16V
0.1 uF 0.1 uF
CD73 16V CD74 16V
CD76
0.1 uF
CD75 16V
0.1 uF
16V
0.1 uF 0.1 uF
CD77 16V CD78 16V
0.1 uF 0.1 uF
CD79 16V CD80 16V
0.1 uF 0.1 uF
C C
CD81 16V CD82 16V
0.1 uF 0.1 uF
CD83 16V CD84 16V
D D
INTEL CORPORATION
FOLSOM, CA 95630
Title
T E R M I N ATION DECOUPLING


1 2 3 4 5 6 7 8
A B C D E
4 VCC 4
C115
VCC 0 . 1 uF
12
U25
1
VCC5
1 7 , 20,24,35 I O R # IORD#
1 7 , 20,24,35 IOW# 2
I O W R# R263 R264
17,24 S Y S CLK 3
S Y S CLK
XD0 11 2 . 7K 2.7K
R265 D0
XD1 10
D1
XD2 9
D2
10K XD3 8
D3
XD4 7
D4
XD5 6
D5
XD6 5
D6
XD7 4
D7
19,20,27 X D [ 7:0] 44
CS#
18,34 PGCS#1 43 40 EXTSMI# 18,34
1 7 , 1 9,20,24,27,35 S A 0 42
A0
A1
LM79 SMI#
1 7 , 1 9,20,24,27,35 S A 1 41
A2 NMI/IRQ#
39 ** NOTE** This device is powered by
3
1 7 , 2 0,24,27,35 S A 2
VID0 37 HARDWARE 5V only and requires a VIH of 3.5V on
3
VID0 it's SMBUS interface. Here is a 5V-3V
V C C C O RE VTT V C C 3 VCC +12V -12V -5V MUX for VID pins under construction. VID1 36
VID1 MONITOR
VID2 35 16 SMBUS level translation circuit.
VID2 PS_BYPASS
VID3 34
VID3
VID4 23 22
R266 R267 R268 R269 R270 R271 R272 VID4/NTEST RESET#
V I D[ 4 : 0] 14
S M I _ IN#
15 Q3
CHASIS_INTRU
10K 10K 10K 66.5K 232K 232K 100K 38
B T I#
32 C P U F A N 1 19
FAN1
32 P S F A N 18
FAN2
32 C P U F A N 2 17
FAN3 D8 2N3904
Slave address = S D A 21 S M BDATA 3 , 5 , 8 ,15,16,18,34
33 20
32
IN0 0101101b SCL SMBCLK 3 , 5 , 8 ,15,16,18,34
IN1 S C H O TTKY
31 BAR54
IN2
30 Q4
IN3
29
IN4
28
-IN5 VCC3
27
FB5
V S SA
V S SD
26
FB6 2N3904
25
-IN6 R273
2 . 7K
13
24
LM79
R274 R275 R276 R277
R293 R279
2 2 . 7K 2
100K 80.6K 66.5K 66.5K 10K
1 1
F O L S O M, CA. 95630
Title
L M 79-75 MONITORS


A B C D E
A B C D E
REVISION 1.0 - Initial public release -- April, 1998.
4 4
3 3
2 2
1 1
INTEL CORPORATION
FOLSOM, CA 95630
Title
R evision History

Date: Sheet 40 of 40
A B C D E

Intel 100 MHZ Pentium (TM) Ii Processor/440Bx Agpset Dual Processor Customer Reference Schematics

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Intel 100 MHZ Pentium (TM) Ii Processor/440Bx Agpset Dual Processor Customer Reference Schematics

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A B C D E

Intel 100 MHz Pentium(tm) II processor/440BX AGPset Dual

PROCESSOR BUS/CORE FREQ. 33

Date: Thursday, April 09, 1998 Sheet 1 of 40

MAX1617 ME ITP CON. MAX1617 ME

S Y S TEM BUS S Y S T EM BUS SMBus

IOAPIC AGP 4 SDRAM DIMM PCI Connector J9,J10,J11,J12 22,23

PG. 19 IDE Connector J15, J16 25

82371EB (PIIX4E) U10A,B 17,18

CNTL FDC37C932FR U14 20

74ALS05 U21 A,B,C,D,E,F 32,33,35

LM79 Crystal (14.318 MHz) Y1 7

VCC3 V C C C O RE1 VTT

VCC3 B01 EMI VCC_VTT A01

16p QSOP B19 BP#[2] PICD[0] A19 P I C D0 5 , 19,34

H D # 63 B32 D#[63] D#[61] A32 H D #61

MAX1617_2 B35 D#[50] D#[60] A35

Size Document Number Rev

D a t e : Thursday, April 09, 1998 Sheet 3 of 40

6 , 7,8 H R E SET# B74 RESET# GND A74

Size Document Number Rev

D a t e : Thursday, April 09, 1998 Sheet 4 of 40

B01 EMI VCC_VTT A01

B33 VCC_CORE D#[55] A33 H D # 55

MAX1617_2 B36 D#[54] D#[53] A36

Size Document Number Rev

D a t e : Thursday, April 09, 1998 Sheet 5 of 40

4 , 7,8 H R E SET# B74 RESET# GND A74

Size Document Number Rev

D a t e : Thursday, April 09, 1998 Sheet 6 of 40

VCC3 CLOCK SYNTHESIZER L14

R55 R56 R57

ITP_JMP CONFIG R73

Size Document Number Rev

Date: Thursday, April 09, 1998 Sheet 7 of 40

**On 4-DIMM solutions that don't support 14 R81 0 D C LK1

* * L o cate R398 close to CKBF and SMBCLK 3 , 5 , 1 5,16,18,34,39

D a t e : Thursday, April 09, 1998 Sheet 8 of 40

1 7 , 22,23,34 F R AME# E2 W3 G F RAME# 21,34

Size Document Number Rev

D a t e : Thursday, April 09, 1998 Sheet 9 of 40

HOST DATA BUS

R103 R105 P L A T F O R M C O M P O NENTS DIVISION

Size Document Number Rev

D a t e : Thursday, April 09, 1998 Sheet 10 of 40

FET-SWITCHES (MEMORY DATA LINES & ECC) VCC

Size Document Number Rev

Date: Thursday, April 09, 1998 S h eet 11 of 40

FET-SWITCHES (DRAM DATA LINES & ECC)

Size Document Number Rev

Date: Thursday, April 09, 1998 S h eet 12 of 40

PLATFORM COMP ONENTS DIVISION

Size Document Number Rev

Date: Thursday, April 09, 1998 Sheet 13 of 40

PLATFORM COMP ONENTS DIVISION

Size Document Number Rev

Date: Thursday, April 09, 1998 Sheet 14 of 40

PLATFORM COMPONENTS DIVISION

Size Document Number Rev

PLATFORM COMPONENTS DIVISION

Size Document Number Rev

PCI BUS INTERFACE

25 SIORDY D16 T12 LA23