Nirvana 13 Discrete GDDR5 Schematics Document Sandy Bridge

5 4 3 2 1
Nirvana 13 Discrete GDDR5 Schematics Document

D D
Sandy Bridge
Intel PCH
C
2011-01-18 C
REV : A00
DY :None Installed B
10mW: External circuit for 10mW solution installed.

GSENSOR_ADI: Stuff for ADI G-Sensor
VCCSA_PWM: Stuff for VCCSA PWM solution.
P2800A1: Stuff for P2800EA1
A <Core Design> A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Cover
Size Document Number Rev
A3
Nirvana 13 A00
Date: Tuesday, January 18, 2011 Sheet 1 of 104
5 4 3 2 1
5 4 3 2 1
CPU DC/DC
Nirvana 13 Block Diagram PCB LAYER VT1316+VT1317 42
DIS INPUTS OUTPUTS
(Discrete 8 layers) L1:Top
L2:GND
5V_S5
SYSTEM DC/DC
VCC_CORE
L3:Signal 44
GDDR5 VRAM Project Code: 91.4ID01.001 VT1316+VT1317
Seymour:512M (64M*32b*2) L4:Signal
512MB L5:VCC INPUTS OUTPUTS
D 884 PCB P/N : 10244 L6:Signal 5V_S5 VCC_GFXCORE D
Revision : -1 L7:GND
SYSTEM DC/DC
L8:Bottom
GDDR5 1.25GHZ TPS51461 48
INPUTS OUTPUTS
Intel CPU 5V_S5 0D85V_S0
DDRIII 1066/1333 Channel A DDRIII Slot 1
Sandy Bridge 1066/1333 14 VGA
AMD Graphic PCIe x 16
VT357 92
INPUTS OUTPUTS
DDRIII 1066/1333 Channel B DDRIII Slot 2
(Discrete) 5V_S0 VGA_CORE
1066/1333 15
SEYMOUR-XT-S3 SYSTEM DC/DC
VT358/RT9026 46
83,84,85,86,87 4,5,6,7,8,9,10,11,12,13 INPUTS OUTPUTS
1D5V_S3
5V_S5/5V_S5 0D75V_S0
DDR_VREF_S3
C
FDIx4x2 DMIx4 SYSTEM DC/DC C
(On Daughter Board) VT357 45
(HDMI V1.3)
INPUTS OUTPUTS
HDMI PCIE x 1 10/100/1000 LOM RJ45 5V_S5 1D05V_VTT
HDMI 51 Realtek CONN
Intel RTL8111E-VB
TI CHARGER
BQ24745 40
LCD 49
LVDS(Single Channel) PCH
PCIE x 1 USB3.0 Controller INPUTS OUTPUTS
Cougar Point NEC uPD720200F1
USB3.0 x 2 +DC_IN_S5
+PBATT DCBATOUT
CRT RGB CRT
50 14 USB 2.0/1.1 ports SYSTEM DC/DC
ETHERNET (10/100/1000Mb) PCIE x 1,USB2.0 x 1 Mini-Card TPS51427 41
SIM
SD/MMC+/MS/ Card Reader High Definition Audio WWAN INPUTS OUTPUTS
USB 2.0 x 1 82
MS Pro/xD/SDXC RTS5138 32 SATA ports (6) 5V_AUX_S5
3D3V_AUX_S5
(8 in 1) 74 PCIE ports (8)
PCIE x 1,USB2.0 x 1 Mini-Card DCBATOUT 5V_S5
3D3V_S5
Bluetooth V3.0 USB 2.0 x 1 USB2.0 x 4 LPC I/F 802.11a/b/g 65 15V_S5
63
26
B ACPI 1.1 SYSTEM DC/DC B
USB2.0 x 1 USB CHARGE ESATA/USB 47

PI5USB14550 57
TPS51311
Finger Print 64 USB 2.0 x 1 Combo 57
INPUTS OUTPUTS
3D3V_S5 1D8V_S0
17,18,19,20,21,22,23,24,25,26 SATA x 1
CAMERA HDA
w/ Digital MIC 49 USB 2.0 x 1 SYSTEM DC/DC
G9731 93
INPUTS OUTPUTS
SPI
26
SATA x 2 HDD 56
SMBus
LPC Bus
1D5V_S3 1V_VGA_S0
Switches 36,93
Flash ROM ODD 56 INPUTS OUTPUTS
CODEC Free Fall Sensor
4MB 60 79
1D5V_S3
5V_S5
1D5V_S0
5V_S0
HP 3D3V_S5 3D3V_S0
IDT 1D8V_S0 1D8V_VGA_S0
92HD87B1 KBC 1D5V_S3 1D5V_VGA_S0
MIC IN 29 ADC
A
NUVOTON <Core Design> A
27 NPCE795PA DAC
Thermal Sensor Wistron Corporation
Main:ENEP2800 Taipei Hsien 221, Taiwan, R.O.C.
28
1CH SPEAKER Title
Touch Int. FAN Controller Block Diagram
PAD69 KB69 Main: G991P11U
28 Fan 55 A3
25 Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
PCH Strapping Huron River Schematic Checklist Rev.1_0 Processor Strapping Huron River Schematic Checklist Rev.1_0
Name Schematics Notes Pin Name Strap Description Configuration (Default value for each bit is Default
SPKR Reboot option at power-up 1 unless specified otherwise) Value
Default Mode: Internal weak Pull-down.
No Reboot Mode with TCO Disabled: Enable when Pull-up. CFG[2] PCI-Express Static 1: Normal Operation.
Lane Reversal 0: Lane Numbers Reversed 15 -> 0, 14 -> 1, ... 0
INIT3_3V# Weak internal pull-up. This signal should not be pulled low. Leave as "No Connect".
GNT[3:0]# functionality is not available on Mobile. Disabled - No Physical Display Port attached to
D GNT3#/GPIO55 Mobile: Used as GPIO only CFG[4] Display Port 1: Embedded Display Port. D
GNT2#/GPIO53 Pull-up resistors are not required on these signals. Presence strap 1
GNT1#/GPIO51 Enabled - An external Display Port device is
If pull-ups are used, they should be tied to the Vcc3_3 power rail. 0: connectd to the Embedded Display Port
Integrated 1.05 V VRM Enable / Disable 11 : x16 - Device 1 functions 1 and 2 disabled
CFG[6:5] PCI-Express 10 : x8, x8 - Device 1 function 1 enabled ;
INTVRMEN Integrated 1.05 V VRMs is enabled when high. This signal should always be pulled high Port Bifurcation function 2 disabled
DMI and FDI Tx/Rx Termination Voltage Straps 01 : Reserved - (Device 1 function 1 disabled ; 11
function 2 enabled)
Weak internal pull-down. It needs to be connected to PROC_SELECT with a 1K±5% pull-up 00 : x8, x4, x4 - Device 1 functions 1 and 2
DF_TVS resistor to PCH VCCPNAND rail and a 4.7K±5% series resistor. enabled
Boot BIOS Strap bit 0
This Signal has a weak internal pull-up.
Note: This field determines the destination of accesses to the BIOS memory range. CFG[7] PEG DEFER TRAINING 1: PEG Train immediately following xxRESETB de assertion
This strap is used in conjunction with Boot BIOS 0: PEG Wait for BIOS for training 1
SATA1GP Destination Selection 1 strap.
/GPIO19 Bit11 Bit 10 Boot BIOS Destination
0 1 Reserved
1 0 PCI
1 1 SPI
0 0 LPC
Voltage Rails
POWER PLANE VOLTAGE DESCRIPTION
C Signal has a weak internal pull-down. ACTIVE IN C
5V_S0 5V
Default: the security measures defined in the Flash Descriptor will be in effect. 3D3V_S0 3.3V
HDA_SDO Pull-up: the Flash Descriptor Security will be overridden. 1D8V_S0 1.8V
This strap should only be asserted high via external pull-up in manufacturing 1D5V_S0 1.5V
1D05V_VTT 1.05V
or debug environments ONLY. 0D85V_S0 0.95 - 0.85V
0D75V_S0 0.75V
VCC_CORE 0.35V to 1.5V
On-Die PLL Voltage Regulator Voltage Select VCC_GFXCORE 0.4 to 1.25V S0
1D8V_VGA_S0 1.8V
HDA_SYNC This signal has a weak internal pull-down. 3D3V_VGA_S0 3.3V CPU Core Rail
1V_VGA_S0 1V Graphics Core Rail
On Die PLL VR is supplied by 1.5 V when sampled high, 1.8 V when sampled low.
Needs to be pulled High for Huron River platform.
TLS Confidentiality 5V_USBX_S3 5V

1D5V_S3 1.5V S3
Low - Intel ME Crypto Transport Layer Security (TLS) cipher suite with no confidentiality DDR_VREF_S3 0.75V
High - Intel ME Crypto Transport Layer Security (TLS) cipher suite with confidentiality
GPIO15 This signal has a weak internal pull-down. BT+ 6V-14.1V AC Brick Mode only
NOTE: A strong pull-up may be needed for GPIO functionality DCBATOUT 6V-14.1V
5V_S5 5V All S states
5V_AUX_S5 5V
3D3V_S5 3.3V
Deep S4/S5 Well On-Die Voltage Regulator Enable
DSWVRMEN This signal enables the internal Deep Sleep 1.05 V regulators.
3D3V_LAN_S5 3.3V WOL_EN Legacy WOL
This signal must be always pulled-up to VccRTC.
B B
On-Die PLL Voltage Regulator

3D3V_AUX_KBC 3.3V DSW, Sx ON for supporting Deep Sleep states
This signal has a weak internal pull-up.
GPIO28 The On-Die PLL voltage regulator is enabled when sampled high.
When sampled low the On-Die PLL Voltage Regulator is disabled. Powered by Li Coin Cell in G3
If not used, 8.2-kȍ to 10-kȍ pull-up to +V3.3A power-rail. 3D3V_AUX_S5 3.3V G3, Sx and +V3ALW in Sx
USB Table
PCIE Routing SATA Table Pair Device
0 X SMBus ADDRESSES
SATA
LANE1 X 1 ESATA / USB COMBO
Pair Device I 2 C / SMBus Addresses
2 Fingerprint HURON RIVER ORB
Device Ref Des Address Hex Bus
LANE2 LAN (I/O Board) 0 HDD1 3 BLUETOOTH EC SMBus 1
N/A Mini Card2 (WWAN) Battery KBC_SDA1/KBC_SCL1
LANE3 Mini Card2(WWAN) 1 4 Capacity Board KBC_SDA1/KBC_SCL1
2 N/A 5 CARD READER EC SMBus 2
LANE4 Mini Card1(WLAN) 3 N/A 6 X
PCH
MXM KBC_SDA2/KBC_SCL2
A LCD KBC_SDA2/KBC_SCL2 <Core Design> A
LANE5 USB3.0 4 ODD 7 X Thermal Sensor
KBC_SDA2/KBC_SCL2
ESATA X KBC_SDA2/KBC_SCL2
5 8 Wistron Corporation
PCH SMBus
LANE6 X 9 X CK505 Clock Generator 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
SO-DIMMA (SPD) Taipei Hsien 221, Taiwan, R.O.C.
10 X SO-DIMMB (SPD)
LANE7 X Digital Pot PCH_SMBDATA/PCH_SMBCLK Title
11 Mini Card1 (WLAN) PCH_SMBDATA/PCH_SMBCLK
LANE8 X PCH_SMBDATA/PCH_SMBCLK Table of Content

12 CAMERA PCH_SMBDATA/PCH_SMBCLK Size Document Number Rev
A3
13 X Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
SSID = CPU
Signal Routing Guideline:
PEG_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils.
PEG_ICOMPI & PEG_RCOMPO keep W/S=4/15 mils and routing length less than 500 mils.
1D05V_VTT
CPU1A 1 OF 9
J22 PEG_IRCOMP_R R401 1 2 24D9R2F-L-GP
PEG_ICOMPI
(19) DMI_TXN[3:0] SANDY PEG_ICOMPO J21
Note: DMI_TXN0 B27 H22
DMI_RX#0 PEG_RCOMPO
D Intel DMI supports both Lane DMI_TXN1
DMI_TXN2
B25
A25
DMI_RX#1 PEG_RXN[0..15]
D
Reversal and polarity inversion DMI_RX#2 PEG_RXN[0..15] (83)
DMI_TXN3 B24 K33 PEG_RXN15
but only at PCH side. This is DMI_RX#3 PEG_RX#0 PEG_RXN14
(19) DMI_TXP[3:0] PEG_RX#1 M35
enabled via a soft strap. DMI_TXP0 B28 L34 PEG_RXN13
DMI_TXP1 DMI_RX0 PEG_RX#2 PEG_RXN12
B26 DMI_RX1 PEG_RX#3 J35
DMI
DMI_TXP2 A24 J32 PEG_RXN11
DMI_TXP3 DMI_RX2 PEG_RX#4 PEG_RXN10
B23 DMI_RX3 PEG_RX#5 H34 Reverse the Bus for Layout 6/28
H31 PEG_RXN9
(19) DMI_RXN[3:0] DMI_RXN0 PEG_RX#6 PEG_RXN8
G21 DMI_TX#0 PEG_RX#7 G33
DMI_RXN1 E22 G30 PEG_RXN7
DMI_RXN2 DMI_TX#1 PEG_RX#8 PEG_RXN6
F21 DMI_TX#2 PEG_RX#9 F35
DMI_RXN3 D21 E34 PEG_RXN5
DMI_TX#3 PEG_RX#10 PEG_RXN4
(19) DMI_RXP[3:0] PEG_RX#11 E32
DMI_RXP0 G22 D33 PEG_RXN3
DMI_RXP1 DMI_TX0 PEG_RX#12 PEG_RXN2
D22 DMI_TX1 PEG_RX#13 D31
PCI EXPRESS* - GRAPHICS

DMI_RXP2 F20 B33 PEG_RXN1
DMI_RXP3 DMI_TX2 PEG_RX#14 PEG_RXN0
C21 DMI_TX3 PEG_RX#15 C32
PEG_RXP[0..15]
PEG_RXP[0..15] (83)
J33 PEG_RXP15
PEG_RX0 PEG_RXP14
PEG_RX1 L35
K34 PEG_RXP13
(19) FDI_TXN[7:0] FDI_TXN0 PEG_RX2 PEG_RXP12
A21 FDI0_TX#0 PEG_RX3 H35
FDI_TXN1 H19 H32 PEG_RXP11
FDI_TXN2 FDI0_TX#1 PEG_RX4 PEG_RXP10
Note: E19 FDI0_TX#2 PEG_RX5 G34
FDI_TXN3 F18 G31 PEG_RXP9
Intel(R) FDI
Intel FDI supports both Lane FDI0_TX#3 PEG_RX6
FDI_TXN4 B21 F33 PEG_RXP8
Reversal and polarity inversion FDI_TXN5 C20
FDI1_TX#0 PEG_RX7
F30 PEG_RXP7
but only at PCH side. This is FDI_TXN6 FDI1_TX#1 PEG_RX8 PEG_RXP6
D18 FDI1_TX#2 PEG_RX9 E35
C enabled via a soft strap. FDI_TXN7 E17 FDI1_TX#3 PEG_RX10 E33
F32
PEG_RXP5
PEG_RXP4 NOTE.
C
PEG_RX11 PEG_RXP3
(19) FDI_TXP[7:0] PEG_RX12 D34 If PEG is not implemented, the RX&TX pairs can be left as No Connect
FDI_TXP0 A22 E31 PEG_RXP2
FDI_TXP1 FDI0_TX0 PEG_RX13 PEG_RXP1
G19 FDI0_TX1 PEG_RX14 C33
FDI_TXP2 E20 B32 PEG_RXP0 PEG Static Lane Reversal PEG_TXN[0..15]
FDI_TXP3 FDI0_TX2 PEG_RX15 PEG_TXN[0..15] (83)
G18 FDI0_TX3
FDI_TXP4 B20 M29 PEG_C_TXN15 C401 1 2 SCD22U10V2KX-1GP PEG_TXN15
FDI_TXP5 FDI1_TX0 PEG_TX#0 PEG_C_TXN14 C402 SCD22U10V2KX-1GP PEG_TXN14
C19 FDI1_TX1 PEG_TX#1 M32 1 2
FDI_TXP6 D19 M31 PEG_C_TXN13 C403 1 2 SCD22U10V2KX-1GP PEG_TXN13
FDI_TXP7 FDI1_TX2 PEG_TX#2 PEG_C_TXN12 C404 SCD22U10V2KX-1GP PEG_TXN12
F17 FDI1_TX3 PEG_TX#3 L32 1 2
L29 PEG_C_TXN11 C405 1 2 SCD22U10V2KX-1GP PEG_TXN11
PEG_TX#4 PEG_C_TXN10 C406 SCD22U10V2KX-1GP PEG_TXN10
(19) FDI_FSYNC0 J18 FDI0_FSYNC PEG_TX#5 K31 1 2
Note: J17 K28 PEG_C_TXN9 C407 1 2 SCD22U10V2KX-1GP PEG_TXN9
(19) FDI_FSYNC1 FDI1_FSYNC PEG_TX#6
Lane reversal does not apply to J30 PEG_C_TXN8 C408 1 2 SCD22U10V2KX-1GP PEG_TXN8
(19) FDI_INT H20 J28 1 2
FDI sideband signals. FDI_INT PEG_TX#8
H29 PEG_C_TXN6 C410 1 2 SCD22U10V2KX-1GP PEG_TXN6
(19) FDI_LSYNC0 J19 FDI0_LSYNC PEG_TX#10 G27 1 2
H17 E29 PEG_C_TXN4 C412 1 2 SCD22U10V2KX-1GP PEG_TXN4
(19) FDI_LSYNC1 FDI1_LSYNC PEG_TX#11
F27 PEG_C_TXN3 C413 1 2 SCD22U10V2KX-1GP PEG_TXN3
PEG_TX#13 D28 1 2
F26 PEG_C_TXN1 C415 1 2 SCD22U10V2KX-1GP PEG_TXN1
PEG_TX#15 E25 1 2
R402 1 2 24D9R2F-L-GP DP_COMP A18 PEG_TXP[0..15]
1D05V_VTT EDP_COMPIO PEG_TXP[0..15] (83)
A17 M28 PEG_C_TXP15 C417 1 2 SCD22U10V2KX-1GP PEG_TXP15
EDP_ICOMPO PEG_TX0 PEG_C_TXP14 C418 SCD22U10V2KX-1GP PEG_TXP14
B16 EDP_HPD PEG_TX1 M33 1 2
M30 PEG_C_TXP13 C419 1 2 SCD22U10V2KX-1GP PEG_TXP13
PEG_TX2 PEG_C_TXP12 C420 SCD22U10V2KX-1GP PEG_TXP12
PEG_TX3 L31 1 2
C15 L28 PEG_C_TXP11 C421 1 2 SCD22U10V2KX-1GP PEG_TXP11
EDP_AUX PEG_TX4 PEG_C_TXP10 C422 SCD22U10V2KX-1GP PEG_TXP10
D15 K30 1 2
B Signal Routing Guideline: EDP_AUX#
eDP PEG_TX5
PEG_TX6 K27 PEG_C_TXP9 C423 1 2 SCD22U10V2KX-1GP PEG_TXP9 B
EDP_ICOMPO keep W/S=12/15 mils and routing J29 PEG_C_TXP8 C424 1 2 SCD22U10V2KX-1GP PEG_TXP8
PEG_TX7 PEG_C_TXP7 C425 SCD22U10V2KX-1GP PEG_TXP7
C17 J27 1 2
length less than 500 mils. F16
EDP_TX0 PEG_TX8
H28 PEG_C_TXP6 C426 1 2 SCD22U10V2KX-1GP PEG_TXP6
EDP_COMPIO keep W/S=4/15 mils and routing EDP_TX1 PEG_TX9 PEG_C_TXP5 C427 SCD22U10V2KX-1GP PEG_TXP5
C16 EDP_TX2 PEG_TX10 G28 1 2
length less than 500 mils. G15 E28 PEG_C_TXP4 C428 1 2 SCD22U10V2KX-1GP PEG_TXP4
EDP_TX3 PEG_TX11 PEG_C_TXP3 C429 SCD22U10V2KX-1GP PEG_TXP3
PEG_TX12 F28 1 2
C18 D27 PEG_C_TXP2 C430 1 2 SCD22U10V2KX-1GP PEG_TXP2
EDP_TX#0 PEG_TX13 PEG_C_TXP1 C431 SCD22U10V2KX-1GP PEG_TXP1
E16 EDP_TX#1 PEG_TX14 E26 1 2
D16 D25 PEG_C_TXP0 C432 1 2 SCD22U10V2KX-1GP PEG_TXP0
EDP_TX#2 PEG_TX15
NOTE. F15 EDP_TX#3
Processor strap CFG[4] should be pulled low to enable Embedded DisplayPort.
SANDY
Stuff to disable internal graphics

function for power saving.
NOTE:
Select a Fast FET similar to 2N7002E whose rise/
fall time is less than 6 ns. If HPD on eDP interface is
disabled, connect it to CPU VCCIO via a 10-kȍ pull-Up
resistor on the motherboard.
A <Core Design>
A
Wistron Corporation
Title
CPU 1/7(PEG/DMI/FDI/eDP)
Nirvana 13 A00
5 4 3 2 1
Disabling Guidelines:
SSID = CPU CPU1B 2 OF 9
If motherboard only supports external graphics:
Connect DPLL_REF_SSCLK on Processor to GND through
1K +/- 5% resistor.
SANDY Connect DPLL_REF_SSCLK# on Processor to VCCP
A28 CLK_EXP_P (20) through 1K +/- 5% resistorpower (~15 mW) may be
MISC
CLOCKS
BCLK
(18) H_SNB_IVB# C26 SNB_IVB# BCLK# A27 CLK_EXP_N (20) wasted.
1D05V_VTT RN502
1 SKTOCC#_R AN34
TPAD14-GP TP501 SKTOCC#
A16 CLK_DP_P_R 2 3
DPLL_REF_SSCLK
D 1
R501
2 H_PROCHOT# DPLL_REF_SSCLK# A15 CLK_DP_N_R 1 4 1D05V_VTT D
20110104 A00:
62R2J-GP H_CATERR# SRN1KJ-7-GP merge R512,R514 to RN502 1k array resistor.
TPAD14-GP TP502 1 AL33 CATERR#
1
20110113 A00:
C502 Swap RN502 base on swap report.
THERMAL
SC47P50V2JN-3GP 1R502 2
2
AN33 R8 4K99R2F-L-GP SM_DRAMRST# (37)

(22,27) H_PECI PECI SM_DRAMRST#
DDR3
MISC
R513
CRB : 47pf 1 2 H_PROCHOT#_R AL32 AK1 SM_RCOMP_0 R506 1 2 140R2F-GP
(27,40,42) H_PROCHOT# PROCHOT# SM_RCOMP0
CEKLT:43pf 56R2J-4-GP SM_RCOMP1
A5 SM_RCOMP_1 R507 1
SM_RCOMP_2 R508 1
2 25D5R2F-GP
A4 2 200R2F-L-GP
SM_RCOMP2
Connect EC to PROCHOT# through inverting OD buffer.
(22,36) H_THERMTRIP# AN32 THERMTRIP#
Signal Routing Guideline:
SM_RCOMP keep routing length less than 500 mils.
1R503 2 H_CPUPWRGD_R AP29

10KR2J-3-GP PRDY#
PREQ# AP27
AR26 XDP_TCLK
TCK
PWR MANAGEMENT
XDP_TMS
JTAG & BPM

AR27
TMS XDP_TRST#
(19) H_PM_SYNC AM34 AP30
PM_SYNC TRST#
AR28 XDP_TDI
R504 TDI XDP_TDO
AP26
TDO 1D05V_VTT
C (22,36) H_CPUPWRGD 1 2 H_CPUPWRGD_R AP33
UNCOREPWRGOOD C
0R0402-PAD
AL35 XDP_DBRESET# RN501
R505 2 VDDPWRGOOD DBR# XDP_TDI
(19,37) PM_DRAM_PWRGD 1 V8 1 8
0R2J-2-GP SM_DRAMPWROK XDP_TMS
DY XDP_TDO
2 7
AT28 3 6
BPM#0 XDP_TCLK
(37) VDDPWRGOOD BPM#1 AR29 4 5
BPM#2 AR30
1 R510 2 BUF_CPU_RST# AR33 AT30 SRN51J-1-GP
(18,27,65,71,82,83) PLT_RST# RESET# BPM#3
AP32
1K5R2F-2-GP BPM#4 XDP_TRST# R511 1
AR31 2 51R2J-2-GP
BPM#5
1
BPM#6 AT31
R509 AR32
BPM#7
1
750R2F-GP
C501
DY SC220P50V2KX-3GP
2
SANDY
3D3V_S0
XDP_DBRESET# 1 2 R516
10KR2J-3-GP
B B
1D05V_VTT
3D3V_S0
1
DY R518
1
Buffered reset to CPU 75R2J-1-GP

DY C503 XDP_DBRESET# XDP_DBRESET# (19)
2
U501 SCD1U10V2KX-5GP
2
1 5
IN B VCC
(18,27,65,71,82,83) PLT_RST# 2
IN A DY
3 4 BUFO_CPU_RST# 1 DY 43R2J-GP
2 BUF_CPU_RST#
GND OUT Y R517
1
74VHC1G09DFT2G-GP
73.01G09.AAH R515
DY0R2J-2-GP
2
<Core Design>
A A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Title
CPU 2/7(THERMAL/CLOCK/PM )
Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
SSID = CPU
CPU1C 3 OF 9 CPU1D 4 OF 9
M_B_DQ[63:0]
SANDY (15) M_B_DQ[63:0]
AB6
SANDY AE2
M_A_DQ[63:0] SA_CLK0 M_A_DIM0_CLK_DDR0 (14) SB_CLK0 M_B_DIM0_CLK_DDR0 (15)
(14) M_A_DQ[63:0] SA_CLK#0 AA6 M_A_DIM0_CLK_DDR#0 (14) SB_CLK#0 AD2 M_B_DIM0_CLK_DDR#0 (15)
M_A_DQ0 C5 V9 M_B_DQ0 C9 R9
M_A_DQ1 SA_DQ0 SA_CKE0 M_A_DIM0_CKE0 (14) M_B_DQ1 SB_DQ0 SB_CKE0 M_B_DIM0_CKE0 (15)
D D5 SA_DQ1 A7 SB_DQ1 D
M_A_DQ2 D3 M_B_DQ2 D10
M_A_DQ3 SA_DQ2 M_B_DQ3 SB_DQ2
D2 SA_DQ3 C8 SB_DQ3
M_A_DQ4 D6 AA5 M_B_DQ4 A9 AE1
M_A_DQ5 SA_DQ4 SA_CLK1 M_A_DIM0_CLK_DDR1 (14) M_B_DQ5 SB_DQ4 SB_CLK1 M_B_DIM0_CLK_DDR1 (15)
C6 SA_DQ5 SA_CLK#1 AB5 M_A_DIM0_CLK_DDR#1 (14) A8 SB_DQ5 SB_CLK#1 AD1 M_B_DIM0_CLK_DDR#1 (15)
M_A_DQ6 C2 V10 M_B_DQ6 D9 R10
M_A_DQ7 SA_DQ6 SA_CKE1 M_A_DIM0_CKE1 (14) M_B_DQ7 SB_DQ6 SB_CKE1 M_B_DIM0_CKE1 (15)
C3 SA_DQ7 D8 SB_DQ7
M_A_DQ8 F10 M_B_DQ8 G4
F8 SA_DQ9 F4 SB_DQ9
M_A_DQ10 G10 AB4 M_B_DQ10 F1 AB2
M_A_DQ11 SA_DQ10 SA_CLK2 M_B_DQ11 SB_DQ10 SB_CLK2
G9 SA_DQ11 SA_CLK#2 AA4 G1 SB_DQ11 SB_CLK#2 AA2
M_A_DQ12 F9 W9 M_B_DQ12 G5 T9
M_A_DQ13 SA_DQ12 SA_CKE2 M_B_DQ13 SB_DQ12 SB_CKE2
F7 SA_DQ13 F5 SB_DQ13
M_A_DQ14 G8 M_B_DQ14 F2
G7 SA_DQ15 G2 SB_DQ15
M_A_DQ16 K4 AB3 M_B_DQ16 J7 AA1
M_A_DQ17 SA_DQ16 SA_CLK3 M_B_DQ17 SB_DQ16 SB_CLK3
K5 SA_DQ17 SA_CLK#3 AA3 J8 SB_DQ17 SB_CLK#3 AB1
M_A_DQ18 K1 W10 M_B_DQ18 K10 T10
M_A_DQ19 SA_DQ18 SA_CKE3 M_B_DQ19 SB_DQ18 SB_CKE3
J1 SA_DQ19 K9 SB_DQ19
M_A_DQ20 J5 M_B_DQ20 J9
J4 SA_DQ21 J10 SB_DQ21
M_A_DQ22 J2 AK3 M_B_DQ22 K8 AD3
M_A_DQ23 SA_DQ22 SA_CS#0 M_A_DIM0_CS#0 (14) M_B_DQ23 SB_DQ22 SB_CS#0 M_B_DIM0_CS#0 (15)
K2 SA_DQ23 SA_CS#1 AL3 M_A_DIM0_CS#1 (14) K7 SB_DQ23 SB_CS#1 AE3 M_B_DIM0_CS#1 (15)
M_A_DQ24 M8 AG1 M_B_DQ24 M5 AD6
M_A_DQ25 SA_DQ24 SA_CS#2 M_B_DQ25 SB_DQ24 SB_CS#2
N10 SA_DQ25 SA_CS#3 AH1 N4 SB_DQ25 SB_CS#3 AE6
M_A_DQ26 N8 M_B_DQ26 N2
N7 SA_DQ27 N1 SB_DQ27
M_A_DQ28 M10 M_B_DQ28 M4
M9 SA_DQ29 SA_ODT0 AH3 M_A_DIM0_ODT0 (14) N5 SB_DQ29 SB_ODT0 AE4 M_B_DIM0_ODT0 (15)
DDR SYSTEM MEMORY B

C M_A_DQ30 N9 AG3 M_B_DQ30 M2 AD4 C
M_A_DQ31
M_A_DQ32
M7
AG6
SA_DQ30
SA_DQ31 DDR SYSTEM MEMORY A SA_ODT1
SA_ODT2 AG2
AH2
M_A_DIM0_ODT1 (14) M_B_DQ31
M_B_DQ32
M1
AM5
SB_DQ30
SB_DQ31
SB_ODT1
SB_ODT2 AD5
AE5
M_B_DIM0_ODT1 (15)
M_A_DQ33 SA_DQ32 SA_ODT3 M_B_DQ33 SB_DQ32 SB_ODT3

AG5 SA_DQ33 AM6 SB_DQ33
M_A_DQ34 AK6 M_B_DQ34 AR3
AK5 SA_DQ35 AP3 SB_DQ35
M_A_DQ36 AH5 M_A_DQS#[7:0] (14) M_B_DQ36 AN3 M_B_DQS#[7:0] (15)
M_A_DQ37 SA_DQ36 M_A_DQS#0 M_B_DQ37 SB_DQ36 M_B_DQS#0
AH6 SA_DQ37 SA_DQS#0 C4 AN2 SB_DQ37 SB_DQS#0 D7
M_A_DQ38 AJ5 G6 M_A_DQS#1 M_B_DQ38 AN1 F3 M_B_DQS#1
M_A_DQ39 SA_DQ38 SA_DQS#1 M_A_DQS#2 M_B_DQ39 SB_DQ38 SB_DQS#1 M_B_DQS#2
AJ6 SA_DQ39 SA_DQS#2 J3 AP2 SB_DQ39 SB_DQS#2 K6
M_A_DQ40 AJ8 M6 M_A_DQS#3 M_B_DQ40 AP5 N3 M_B_DQS#3
AK8 SA_DQ41 SA_DQS#4 AL6 AN9 SB_DQ41 SB_DQS#4 AN5
M_A_DQ42 AJ9 AM8 M_A_DQS#5 M_B_DQ42 AT5 AP9 M_B_DQS#5
AK9 SA_DQ43 SA_DQS#6 AR12 AT6 SB_DQ43 SB_DQS#6 AK12
M_A_DQ44 AH8 AM15 M_A_DQS#7 M_B_DQ44 AP6 AP15 M_B_DQS#7
M_A_DQ45 SA_DQ44 SA_DQS#7 M_B_DQ45 SB_DQ44 SB_DQS#7
AH9 SA_DQ45 AN8 SB_DQ45
M_A_DQ46 AL9 M_B_DQ46 AR6
AL8 SA_DQ47 AR5 SB_DQ47
M_A_DQ48 AP11 M_A_DQS[7:0] (14) M_B_DQ48 AR9 M_B_DQS[7:0] (15)
M_A_DQ49 SA_DQ48 M_A_DQS0 M_B_DQ49 SB_DQ48 M_B_DQS0
AN11 SA_DQ49 SA_DQS0 D4 AJ11 SB_DQ49 SB_DQS0 C7
M_A_DQ50 AL12 F6 M_A_DQS1 M_B_DQ50 AT8 G3 M_B_DQS1
M_A_DQ51 SA_DQ50 SA_DQS1 M_A_DQS2 M_B_DQ51 SB_DQ50 SB_DQS1 M_B_DQS2
AM12 SA_DQ51 SA_DQS2 K3 AT9 SB_DQ51 SB_DQS2 J6
M_A_DQ52 AM11 N6 M_A_DQS3 M_B_DQ52 AH11 M3 M_B_DQS3
AL11 SA_DQ53 SA_DQS4 AL5 AR8 SB_DQ53 SB_DQS4 AN6
M_A_DQ54 AP12 AM9 M_A_DQS5 M_B_DQ54 AJ12 AP8 M_B_DQS5
AN12 SA_DQ55 SA_DQS6 AR11 AH12 SB_DQ55 SB_DQS6 AK11
M_A_DQ56 AJ14 AM14 M_A_DQS7 M_B_DQ56 AT11 AP14 M_B_DQS7
M_A_DQ57 SA_DQ56 SA_DQS7 M_B_DQ57 SB_DQ56 SB_DQS7
AH14 SA_DQ57 AN14 SB_DQ57
M_A_DQ58 AL15 M_B_DQ58 AR14
B M_A_DQ59 SA_DQ58 M_B_DQ59 SB_DQ58 B
AK15 SA_DQ59 AT14 SB_DQ59
M_A_DQ60 AL14 M_B_DQ60 AT12
M_A_DQ61 SA_DQ60 M_A_A0 M_A_A[15:0] (14) M_B_DQ61 SB_DQ60 M_B_A0 M_B_A[15:0] (15)
AK14 SA_DQ61 SA_MA0 AD10 AN15 SB_DQ61 SB_MA0 AA8
M_A_DQ62 AJ15 W1 M_A_A1 M_B_DQ62 AR15 T7 M_B_A1
M_A_DQ63 SA_DQ62 SA_MA1 M_A_A2 M_B_DQ63 SB_DQ62 SB_MA1 M_B_A2
AH15 SA_DQ63 SA_MA2 W2 AT15 SB_DQ63 SB_MA2 R7
W7 M_A_A3 T6 M_B_A3
SA_MA3 M_A_A4 SB_MA3 M_B_A4
SA_MA4 V3 SB_MA4 T2
V2 M_A_A5 T4 M_B_A5
SA_MA6 W3 SB_MA6 T3
(14) M_A_BS0 AE10 W6 M_A_A7 (15) M_B_BS0 AA9 R2 M_B_A7
SA_BS0 SA_MA7 M_A_A8 SB_BS0 SB_MA7 M_B_A8
(14) M_A_BS1 AF10 SA_BS1 SA_MA8 V1 (15) M_B_BS1 AA7 SB_BS1 SB_MA8 T5
(14) M_A_BS2 V6 W5 M_A_A9 (15) M_B_BS2 R6 R3 M_B_A9
SA_BS2 SA_MA9 M_A_A10 SB_BS2 SB_MA9 M_B_A10
SA_MA10 AD8 SB_MA10 AB7
V4 M_A_A11 R1 M_B_A11
SA_MA12 W4 SB_MA12 T1
(14) M_A_CAS# AE8 AF8 M_A_A13 (15) M_B_CAS# AA10 AB10 M_B_A13
SA_CAS# SA_MA13 M_A_A14 SB_CAS# SB_MA13 M_B_A14
(14) M_A_RAS# AD9 SA_RAS# SA_MA14 V5 (15) M_B_RAS# AB8 SB_RAS# SB_MA14 R5
(14) M_A_W E# AF9 V7 M_A_A15 (15) M_B_W E# AB9 R4 M_B_A15
SA_WE# SA_MA15 SB_WE# SB_MA15
SANDY SANDY
A <Core Design> A
Wistron Corporation
Title
CPU 3/7(DDR)
Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
SSID = CPU
CFG2
CPU1E 5 OF 9
1
PEG Static Lane Reversal
R702
L7 1KR2J-1-GP 1: Normal Operation; Lane #
RSVD#L7
RSVD#AG7 AG7 CFG2 definition matches socket pin map definition
AK28 SANDY AE7
2
CFG0 RSVD#AE7
AK29 CFG1 RSVD#AK2 AK2 0:Lane Reversed
D CFG2 AL26 W8 D
CFG2 RSVD#W8
AL27 CFG3
CFG4 AK26
CFG5 CFG4
AL29 CFG5 RSVD#AT26 AT26
CFG6 AL30 AM33
CFG7 CFG6 RSVD#AM33
AM31 CFG7 RSVD#AJ27 AJ27
AM32 CFG4
CFG8
AM30 CFG9
AM28 CFG10
Display Port Presence Strap
1
AM26 CFG11
AN28 R703 CFG4 1: Disabled; No Physical Display Port
AN31
CFG12
T8
DY 3K3R2F-2-GP attached to Embedded Display Port
CFG13 RSVD#T8
AN26 CFG14 RSVD#J16 J16
AM27 H16 0: Enabled; An external Display Port device is
2
CFG15 RSVD#H16
AK31 CFG16 RSVD#G16 G16 connected to the Embedded Display Port
1 CFG17 AN29
TPAD14-GP TP712 CFG17
RSVD#AR35 AR35
AJ31 RSVD#AJ31 RSVD#AT34 AT34
AH31 RSVD#AH31 RSVD#AT33 AT33
AJ33 AP35 CFG5
RSVD#AJ33 RSVD#AP35
AH33 RSVD#AH33 RSVD#AR34 AR34
CFG6 PCIE Port Bifurcation Straps
1
AJ26
M3 - Processor Generated SO-DIMM VREF_DQ RSVD#AJ26
RESERVED
R701 R704 CFG[6:5] 11: x16 - Device 1 functions 1 and 2 disabled
DY DY
C
DY B4:VREF_DQ CHA RSVD#B34 B34 10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled C
M_VREF_DQ_DIMM0 R708 1 DY 2 0R2J-2-GP M_VREF_DQ_DIMM0_C B4 A33 01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)
2
RSVD#B4 RSVD#A33
R709 1 2 0R2J-2-GP M_VREF_DQ_DIMM1_C D1 A34 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
1KR2J-1-GP
1KR2J-1-GP
M_VREF_DQ_DIMM1 RSVD#D1 RSVD#A34
RSVD#B35 B35
D1:VREF_DQ CHB RSVD#C35 C35
1
F25 RSVD#F25
R711 R712 F24 CFG7
RSVD#F24
F23 RSVD#F23
1KR2F-3-GP 1KR2F-3-GP D24 AJ32 PEG DEFER TRAINING
RSVD#D24 RSVD#AJ32
1
M_VREF_CA_DIMM0 R707 1 DY 2 0R2J-2-GP G25 AK32
2
RSVD#G25 RSVD#AK32 R705

G24 RSVD#G24 1: PEG Train immediately following xxRESETB de assertion
R706 1 2 0R2J-2-GP 1KR2J-1-GP CFG7
M_VREF_CA_DIMM1 DY E23 RSVD#E23 DY
D23 RSVD#D23
0: PEG Wait for BIOS for training
C30 AH27
2
RSVD#C30 RSVD#AH27
A31 RSVD#A31
B30 RSVD#B30
B29 RSVD#B29
D30 AN35 RSVD#AN35 1
RSVD#D30 RSVD#AN35 RSVD#AM35 TP713 TPAD14-GP
20 mils B31 RSVD#B31 RSVD#AM35 AM35 1
A30 TP714 TPAD14-GP
RSVD#A30
C29 RSVD#C29
J20 RSVD#J20
B18 RSVD#B18 RSVD#AT2 AT2
R710 1 DY 2 0R2J-2-GP H_VCCP_SEL A19 AT1
RSVD#A19 RSVD#AT1
RSVD#AR1 AR1
B B
J15 RSVD#J15
SANDY
A <Core Design> A
Wistron Corporation
Title
Size
CPU 4/7(RESERVED)
Document Number Rev
Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
SSID = CPU
D D
CPU1F POWER 6 OF 9
VCCIO Output Decoupling Recommendation:
2 x 330 uF (3 x 330 uF for 2012 capable designs)
5 x 22 uF & 5 x 0805 no-stuff at Bottom
VCC_CORE SANDY 7 x 22 uF & 2 x 0805 no-stuff at Top
1D05V_VTT
AG35
VCC
AG34 AH13
VCC VCCIO
AG33 AH10
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC4D7U6D3V5KX-3GP
VCC VCCIO
C805
C806
C807
C808
C809
C810
C838
C839
C840
C841
AG32 AG10
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
1
1
VCC VCCIO
AG31 AC10
VCC VCCIO
AG30
VCC VCCIO
Y10 DY DY DY DY
AG29 U10
2
VCC VCCIO
AG28 P10
VCC VCCIO
AG27 L10
VCC VCCIO
AG26 J14
VCC VCCIO
AF35 J13
VCC VCCIO
AF34 J12
VCC VCCIO
AF33 J11
VCC VCCIO
AF32 H14
VCC VCCIO
AF31 H12
VCC VCCIO
AF30 H11
VCC VCCIO
AF29 G14
VCC VCCIO
AF28 G13 No-stuff sites outside the socket may be removed.
PEG AND DDR

VCC VCCIO
AF27 G12
AF26
VCC VCCIO
F14 No-stuff sites inside the socket cavity need to remain.
VCC VCCIO
AD35 F13
VCC VCCIO
AD34 F12
VCC VCCIO
AD33 F11
VCC VCCIO
AD32 E14
VCC VCCIO 1D05V_VTT
PROCESSOR CORE POWER AD31
VCC VCCIO
E12
AD30
VCC_CORE VCC
AD29 E11
53A AD28
VCC VCCIO
D14
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC4D7U6D3V5KX-3GP
SC4D7U6D3V5KX-3GP
VCC VCCIO
C829
C830
C842
C843
C844
C845
C AD27 D13 C
1
VCC VCCIO
AD26 D12
VCC VCCIO
AC35 D11 DY
SC22U6D3V5MX-2GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
VCC VCCIO
C801
C802
C803
C804
C811
AC34 C14
2
1
VCC VCCIO
AC33 C13
VCC VCCIO
DY AC32
VCC VCCIO
C12
AC31 C11
2
VCC VCCIO
AC30 B14
VCC VCCIO
AC29 B12
VCC VCCIO
AC28 A14
VCC VCCIO
AC27 A13
VCC VCCIO
AC26 A12
VCC VCCIO
AA35 A11
VCC VCCIO
AA34
VCC
AA33 J23
VCC VCCIO
AA32
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
VCC
C820
C819
C818
C817
C815
AA31
1
VCC
AA30
VCC These resistors need to close to power IC.
AA29
VCC
AA28
2
VCC 1D05V_VTT
AA27
VCC
AA26
CORE SUPPLY
VCC
Y35
VCC VR_SVID_ALERT# R805
Y34 1 2 75R2J-1-GP
20110118 A00: VCC
Y33
Change C823, C824, C825 to 22uF from 10uF (0805 size). VCC H_CPU_SVIDCLK R806
Y32 1 DY 2 54D9R2F-L1-GP
SC22U6D3V5MX-2GP
VCC
Y31
VCC H_CPU_SVIDDAT R804
Y30 1 2 130R2F-1-GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
VCC
Y29
SC22U6D3V5MX-2GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
VCC
C816
C821
C822
C823
C824
C825
C826
C827
Y28
1
VCC
Y27
VCC
Y26
VCC
V35
2
SVID
VCC H_CPU_SVIDALRT# R803

V34 AJ29 1 2 43R2J-GP VR_SVID_ALERT# (42)
VCC VIDALERT# H_CPU_SVIDCLK
V33 AJ30
VCC VIDSCLK H_CPU_SVIDDAT H_CPU_SVIDCLK (42)
V32 AJ28 H_CPU_SVIDDAT (42)
VCC VIDSOUT
V31
VCC
V30
VCC
V29
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
VCC
V28
VCC
V27
B VCC B
V26
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
VCC
C837
C836
C835
C834
C833
C832
C831
C828
U35
1
VCC
U34
VCC
U33
VCC 20101231 A00:
U32
2
VCC Merge R801,R802 to RN801 100 ohm array resistor.

U31
VCC 20110113 A00:
U30
VCC Change RN801 to 100 ohm 1% (66.10156.04L).
U29
VCC 20110113 A00:
U28
VCC Swap RN801 base on swap report.
U27
VCC
U26
VCC
R35
VCC
R34 RN801
VCC
R33
VCC
VCC Output Decoupling Recommendation: R32
VCC VCC_CORE 2 R2
3
4 x 470 uF at Bottom Socket Edge R31 1 4
VCC R1
R30
8 x 22 uF at Top Socket Cavity VCC
R29
SENSE LINES
VCC SRN100F-1-GP
8 x 22 uF at Top Socket Edge R28
VCC
8 x 22 uF at Bottom Socket Cavity R27 AJ35 VCCSENSE (42)
VCC VCC_SENSE
R26 AJ34 VSSSENSE (42)
VCC VSS_SENSE
P35
VCC
P34
VCC
P33
VCC
P32 B10 VCCIO_SENSE (45)
VCC VCCIO_SENSE
P31 A10 VSSIO_SENSE (45)
VCC_CORE VCC VSSIO_SENSE
P30
VCC
P29
VCC
P28
VCC
P27
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
VCC
P26
VCC
C846
C847
C848
1
DY DY DY
2
SANDY
A 20110118 A00: A
Reserve C846~C848 22uF (0805 size).
<Core Design>
Wistron Corporation
Title
Size
CPU 5/7(VCC_CORE)
Document Number Rev
Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
VAXG Output Decoupling Recommendation:

SSID = CPU 2 x 470 uF at Bottom Socket Edge
2 x 22 uF at Top Socket Cavity
4 x 22 uF at Top Socket Edge
2 x 22 uF at Bottom Socket Cavity 20101231 A00:
Merge R906,R907 to RN902 100 ohm array resistor.
4 x 22 uF at Bottom Socket Edge
VCC_GFXCORE
CPU1G
POWER 7 OF 9
20110113 A00:
Change RN801 to 100 ohm 1% (66.10156.04L).
RN902
PROCESSOR VAXG: 33A VCC_AXG_SENSE 1 R1
4 VCC_GFXCORE
SENSE
LINES
AT24 AK35 VCC_AXG_SENSE (42) VSS_AXG_SENSE 2 R2
3
VAXG VAXG_SENSE
AT23 AK34
SC22U6D3V5MX-2GP
SC10U6D3V5KX-1GP
D D
SC4D7U6D3V5KX-3GP
SC4D7U6D3V5KX-3GP
SC4D7U6D3V5KX-3GP
SC4D7U6D3V5KX-3GP
VAXG VSSAXG_SENSE VSS_AXG_SENSE (42)
C901
AT21 SRN100F-1-GP
VAXG SANDY
1
C902
C903
C904
C905
C906
AT20 VAXG
DY AT18 VAXG
Refer to the latest Huron River Mainstream PDG
AT17 (Doc# 436735) for more details on S3 power
2
VAXG
AR24 VAXG reduction implementation.
AR23 VAXG
AR21 VAXG
AR20 +V_SM_VREF_CNT should have 10 mil trace width
VAXG
VREF
AR18 VAXG
AR17 VAXG
AP24 AL1 +V_SM_VREF_CNT
VAXG SM_VREF +V_SM_VREF_CNT (37)
AP23 VAXG
AP21 VAXG
AP20 VAXG
AP18 VAXG
C908
C920
C921
SC10U6D3V3MX-GP AP17
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
VAXG
1
1
AN24 VAXG
Routing Guideline:
DY DY DY AN23 VAXG Power from DDR_VREF_S3 and +V_SM_VREF_CNT
AN21 1D5V_S0
2
2
AN20
VAXG should have 10 mils trace width.
ST330U2VDM-4-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
VAXG
DDR3 -1.5V RAILS

AN18 VAXG
AN17 VAXG PROCESSOR VDDQ: 10A
GRAPHICS
AM24 VAXG VDDQ AF7
AM23 AF4
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC4D7U6D3V5KX-3GP
VAXG VDDQ 1D5V_S3
TC901
C909
C910
C911
C912
C913
C914
AM21 AF1
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
VAXG VDDQ
1
C907
C918
C919
C925
AM20 VAXG VDDQ AC7 DY DY DY DY
AM18 VAXG VDDQ AC4 DY DY DY
AM17 AC1
2
C VAXG VDDQ C
AL24 VAXG VDDQ Y7
AL23 VAXG VDDQ Y4
AL21 Y1
AL20
VAXG VDDQ
U7
79.33719.20L
VAXG VDDQ
AL18 VAXG VDDQ U4 2nd = 77.C3371.13L
AL17 VAXG VDDQ U1 VDDQ Output Decoupling Recommendation:
AK24 VAXG VDDQ P7 1 x 330 uF
AK23 P4
AK21
VAXG VDDQ
P1 0D85V_S0 6 x 10 uF
VAXG VDDQ
AK20 VAXG
AK18 VAXG PROCESSOR VCCSA: 6A
AK17 VAXG
AJ24
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
VAXG
C916
C915
C917
AJ23 VAXG
1
AJ21 VAXG
AJ20 VAXG
VCCSA Output Decoupling Recommendation:
AJ18 1 x 330 uF
2
VAXG
AJ17
AH24
VAXG 2 x 10 uF at Bottom Socket Cavity
SA RAIL
VAXG 1 x 10 uF at Bottom Socket Edge
AH23 VAXG
AH21 VAXG VCCSA M27
AH20 VAXG VCCSA M26
Disabling Guidelines for External Graphics Designs: AH18 VAXG VCCSA L26
Can connect to GND if motherboard only supports external AH17 VAXG VCCSA J26
J25
graphics and if GFX VR is not stuffed. VCCSA
J24
Can be left floating (Gfx VR keeps VAXG rail from floating) VCCSA
VCCSA H26
if the VR is stuffed VCCSA H25
B
1.8V RAIL B
1D8V_S0
PROCESSOR VCCPLL: 1.2A VCCUSA_SENSE
B6 VCCPLL VCCSA_SENSE H23 VCCUSA_SENSE (48)
MISC
A6
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC10U6D3V5KX-1GP
VCCPLL
C923
C922
C924
A2 VCCPLL
1
C22 H_FC_C22
FC_C22 VCCSA_SEL H_FC_C22 (48)
C24
2
VCCSA_VID1 VCCSA_SEL (48)
2
1
RN901
SANDY SRN1KJ-7-GP
3
4
VCCPLL Output Decoupling Recommendation:
1 x 330 uF
2 x 1 uF
1 x 10 uF
A <Core Design> A
Wistron Corporation
Title
Size Document Number

CPU 6/7(VCC_GFX_CORE) Rev
Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
SSID = CPU
CPU1H 8 OF 9 CPU1I 9 OF 9
AT35 VSS VSS AJ22

AT32 VSS VSS AJ19
AT29 VSS VSS AJ16 T35 VSS SANDY VSS F22
AT27 VSS VSS AJ13 T34 VSS VSS F19
AT25 VSS VSS AJ10 T33 VSS VSS E30
D AT22 VSS VSS AJ7 T32 VSS VSS E27 D
AT13 VSS SANDY VSS AJ2 T29 VSS VSS E18
AT7 VSS VSS AH35 T27 VSS VSS E13
AT4 VSS VSS AH34 T26 VSS VSS E10
AT3 VSS VSS AH32 P9 VSS VSS E9
AR25 VSS VSS AH30 P8 VSS VSS E8
AR10 VSS VSS AH22 N35 VSS VSS E3
AR2 VSS VSS AH7 N32 VSS VSS D35
AP34 VSS VSS AH4 N31 VSS VSS D32
AP31 VSS VSS AG9 N30 VSS VSS D29
AP22 VSS VSS AF6 N27 VSS VSS D17
AP19 VSS VSS AF5 N26 VSS VSS C34
AP16 VSS VSS AF3 M34 VSS VSS C31
AP13 VSS VSS AF2 L33 VSS VSS C28
AP10 VSS VSS AE35 L30 VSS VSS C27
C AN30 AE31 L6 C1 C
VSS VSS VSS VSS
AN27 VSS VSS AE30 L5 VSS VSS B22
AN25 AE29 L4 B19
AN22
AN19
VSS
VSS
VSS
VSS VSS
VSS
VSS
AE28
AE27
L3
L2
VSS
VSS
VSS
VSS VSS
VSS
VSS
B17
B15
AN16 VSS VSS AE26 L1 VSS VSS B13
AN13 VSS VSS AE9 K35 VSS VSS B11
AN10 VSS VSS AD7 K32 VSS VSS B9
AN7 VSS VSS AC9 K29 VSS VSS B8
AN4 VSS VSS AC8 K26 VSS VSS B7
AM29 VSS VSS AC6 J34 VSS VSS B5
AM25 VSS VSS AC5 J31 VSS VSS B3
AM22 VSS VSS AC3 H33 VSS VSS B2
AM19 VSS VSS AC2 H30 VSS VSS A35
AM16 VSS VSS AB35 H27 VSS VSS A32
AM2 VSS VSS AB29 H10 VSS
AM1 VSS VSS AB28 H9 VSS
AL34 VSS VSS AB27 H8 VSS
AL31 VSS VSS AB26 H7 VSS
AL28 VSS VSS Y9 H6 VSS
B B
AL10 VSS VSS W35 G35 VSS
AK33 VSS VSS W31 G23 VSS
AK22 VSS VSS W27 F34 VSS
AK19 VSS VSS W26 F31 VSS
AK16 VSS VSS U9 F29 VSS
AK13 VSS VSS U8
AK10 VSS VSS U6
AK7 VSS VSS U5
AK4 VSS VSS U3
AJ25 VSS VSS U2
SANDY SANDY
A <Core Design> A
Wistron Corporation
Title
CPU 7/7(VSS)
Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
Remove the XDP connector for space saving 6/28
B B
A <Core Design> A
Wistron Corporation
Title
XDP
A3
NIRVANA 13 A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
SSID = MEMORY
DM1
M_A_A0 98 NP1
M_A_A1 A0 NP1
97 NP2
M_A_A2 A1 NP2
M_A_A[15:0] (6) 96
M_A_A3 A2
95 110 M_A_RAS# (6)
DDR_VREF_S3 M_A_A4 A3 RAS#
92 113 M_A_WE# (6)
M_A_A5 A4 WE#
91 115 M_A_CAS# (6)
M_A_A6 A5 CAS# SA0_DIM0
90 Note:
2
M_A_A7 A6
86 114 M_A_DIM0_CS#0 (6)
R1405 M_A_A8 A7 CS0# SA1_DIM0 If SA0 DIM0 = 0, SA1_DIM0 = 0
89 121 M_A_DIM0_CS#1 (6)
M_A_A9 A8 CS1#
D 0R0402-PAD 85 SO-DIMMA SPD Address is 0xA0 D
M_A_A10 A9
107 73 M_A_DIM0_CKE0 (6)
A10/AP CKE0
M_VREF_CA_DIMM0 M_A_A11 84 74 M_A_DIM0_CKE1 (6) SO-DIMMA TS Address is 0x30
1
M_A_A12 A11 CKE1

83
M_A_A13 A12
119 101 M_A_DIM0_CLK_DDR0 (6)
2
1
A13 CK0
M_A_A14 80
A14 CK0#
103 M_A_DIM0_CLK_DDR#0 (6) If SA0 DIM0 = 1, SA1_DIM0 = 0
M_A_A15 78 RN1401
SO-DIMMA SPD Address is 0xA2
1
1
A15 20101231 A00:
79 102 M_A_DIM0_CLK_DDR1 (6) 0R4P2R-PAD
C1423 C1425 C1424 (6) M_A_BS2 A16/BA2 CK1 Merge R1401,R1402 to RN1401 10k ohm array resistor.
RN
DY CK1#
104 M_A_DIM0_CLK_DDR#1 (6)
20110104 A00:
SO-DIMMA TS Address is 0x32
109
SCD1U10V2KX-5GP
SC2D2U10V3KX-1GP
SCD1U10V2KX-5GP
2
3
4
(6) M_A_BS0 BA0 Change RN1401 to 0R short pad.
108 11
(6) M_A_BS1 BA1 DM0 20110113 A00:
(6) M_A_DQ[63:0] 28
M_A_DQ0 DM1 Swap RN1401 base on swap report.
5 46
M_A_DQ1 DQ0 DM2
7 63
M_A_DQ2 DQ1 DM3
15 136
M_A_DQ3 DQ2 DM4
17 153
M_A_DQ4 DQ3 DM5
4 170
M_A_DQ5 DQ4 DM6
6 187
M_A_DQ6 DQ5 DM7
16
DDR_VREF_S3 M_A_DQ7 DQ6
18 200 PCH_SMBDATA (15,20,65,79,82)
M_A_DQ8 DQ7 SDA
21 202
M_A_DQ9 23
DQ8 SCL PCH_SMBCLK (15,20,65,79,82) Thermal EVENT
2
M_A_DQ10 DQ9 3D3V_S0

33 198 TS#_DIMM0_1 (15)
R1404 M_A_DQ11 DQ10 EVENT# 3D3V_S0
35
20101224 A00: M_A_DQ12 DQ11
0R0402-PAD 22 199
0402 0R pad: R1404 R1405. M_A_DQ13 DQ12 VDDSPD TS#_DIMM0_1
24 1R1403 2
M_VREF_DQ_DIMM0 M_A_DQ14 DQ13 SA0_DIM0 10KR2J-3-GP
34 197
1
1
M_A_DQ15 DQ14 SA0 SA1_DIM0 C1401 C1402
36 201
M_A_DQ16 DQ15 SA1
39
M_A_DQ17 41
DQ16
77
DY
SCD1U10V2KX-5GP
SC2D2U10V3KX-1GP
2
2
M_A_DQ18 DQ17 NC#1
51 122
1
M_A_DQ19 DQ18 NC#2 1D5V_S3

53 125
C1411 C1412 C1413 M_A_DQ20 DQ19 NC#/TEST
40
DY M_A_DQ21 42
DQ20
75
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SC2D2U10V3KX-1GP
2
M_A_DQ22 DQ21 VDD1

50 76
M_A_DQ23 DQ22 VDD2
52 81
M_A_DQ24 DQ23 VDD3
57 82
M_A_DQ25 DQ24 VDD4 1D5V_S3
59 87 SODIMM A DECOUPLING
ST330U2VDM-4-GP
M_A_DQ26 DQ25 VDD5
67 88
M_A_DQ27 DQ26 VDD6
69 93
M_A_DQ28 DQ27 VDD7
56 94
M_A_DQ29 DQ28 VDD8
C 58 99 C
M_A_DQ30 DQ29 VDD9
68 100
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
DQ30 VDD10
TC1401
M_A_DQ31
C1403
C1404
C1405
C1406
C1407
C1408
C1409
C1410
70 105
1
M_A_DQ32 DQ31 VDD11
129 106
M_A_DQ33 DQ32 VDD12
M_A_DQ34
131
DQ33 VDD13
111
DY DY DY DY DY DY DY DY
141 112
2
M_A_DQ35 DQ34 VDD14
143 117
M_A_DQ36 DQ35 VDD15
130 118
M_A_DQ37 DQ36 VDD16
132 123
M_A_DQ38 140
DQ37 VDD17
124
79.33719.20L
M_A_DQ39 DQ38 VDD18
M_A_DQ40
142
DQ39 2nd = 77.C3371.13L
147 2
M_A_DQ41 DQ40 VSS
149 3
M_A_DQ42 DQ41 VSS
157 8
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
M_A_DQ43 DQ42 VSS
C1414
C1415
C1416
C1417
159 9
1
M_A_DQ44 DQ43 VSS
M_A_DQ45
146
DQ44 VSS
13 Layout Note:
0D75V_S0 Place these caps M_A_DQ46
148
DQ45 VSS
14
Place these Caps near DY DY
158 19
2
close to VTT1 and M_A_DQ47 DQ46 VSS
160 20 SO-DIMMA.
M_A_DQ48 DQ47 VSS
VTT2. 163 25
M_A_DQ49 DQ48 VSS
165 26
M_A_DQ50 DQ49 VSS
175 31
M_A_DQ51 DQ50 VSS
177 32
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
M_A_DQ52 DQ51 VSS

C1419
C1420
C1421
C1422
164 37
1
M_A_DQ53 DQ52 VSS

166 38
C1418 M_A_DQ54 DQ53 VSS
DY DY DY M_A_DQ55
174
176
DQ54 VSS
43
44
SC10U6D3V5KX-1GP
2
M_A_DQ56 DQ55 VSS

181 48
M_A_DQ57 DQ56 VSS
183 49
M_A_DQ58 DQ57 VSS
191 54
M_A_DQ59 DQ58 VSS
193 55
M_A_DQ60 DQ59 VSS
180 60
M_A_DQ61 DQ60 VSS
182 61
M_A_DQ62 DQ61 VSS
192 65
M_A_DQ63 DQ62 VSS
194 66
DQ63 VSS
71
M_A_DQS#0 VSS
10 72
M_A_DQS#1 DQS0# VSS
27 127
M_A_DQS#2 DQS1# VSS
45 128
M_A_DQS#3 DQS2# VSS
62 133
M_A_DQS#4 DQS3# VSS
B M_A_DQS#5
135
152
DQS4# VSS
134
138
PART NUMBER Height TYPE B
M_A_DQS#6 DQS5# VSS
M_A_DQS#[7:0] (6) 169 139
M_A_DQS#7 DQS6# VSS
186 144
M_A_DQS[7:0] (6)
DQS7# VSS
145
62.10017.N61 9.2mm
M_A_DQS0 VSS
12 150
M_A_DQS1 DQS0 VSS
29 151
M_A_DQS2 DQS1 VSS
M_A_DQS3
47
64
DQS2 VSS
155
156
62.10017.U01 9.2mm
M_A_DQS4 DQS3 VSS
137 161
M_A_DQS5 DQS4 VSS
154 162
M_A_DQS6 DQS5 VSS
171 167
M_A_DQS7 188
DQS6 VSS
168
62.10017.T11 9.2mm
DQS7 VSS
172
VSS
116 173
(6) M_A_DIM0_ODT0 ODT0 VSS
120 178
(6) M_A_DIM0_ODT1 ODT1 VSS
179
VSS
M_VREF_CA_DIMM0 126 184
VREF_CA VSS
M_VREF_DQ_DIMM0 1 185
VREF_DQ VSS
189
VSS
30 190
(15,37) DDR3_DRAMRST# RESET# VSS
195
VSS
196
VSS
0D75V_S0 203 205
VTT1 VSS
204 206
VTT2 VSS
H=9.2mm
DDR3-204P-42-GP
62.10017.N61
A A
<Core Design>
Wistron Corporation
Title
DDR3-DIMM1 SOCKET1
Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
DM2
SSID = MEMORY M_B_A0 98
A0 NP1
NP1
M_B_A1 97 NP2
M_B_A2 A1 NP2
M_B_A[15:0] (6) 96
M_B_A3 A2
95 110 M_B_RAS# (6)
M_B_A4 A3 RAS#
92 113 M_B_WE# (6)
M_B_A5 A4 WE#
91 115 M_B_CAS# (6)
M_B_A6 A5 CAS#
90
M_B_A7 A6 3D3V_S0
86 114 M_B_DIM0_CS#0 (6)
M_B_A8 A7 CS0#
89 121 M_B_DIM0_CS#1 (6)
M_B_A9 A8 CS1#
85
M_B_A10 A9
107 73 M_B_DIM0_CKE0 (6)
1
M_B_A11 A10/AP CKE0
84 74 M_B_DIM0_CKE1 (6)
M_B_A12 A11 CKE1 R1501
83
M_B_A13 A12 10KR2J-3-GP
119 101 M_B_DIM0_CLK_DDR0 (6)
M_B_A14 A13 CK0
M_B_A15
80
A14 CK0#
103 M_B_DIM0_CLK_DDR#0 (6) Note:
78
2
A15 SO-DIMMB SPD Address is 0xA4
79 102 M_B_DIM0_CLK_DDR1 (6)
(6) M_B_BS2 A16/BA2 CK1 SA1_DIM1
D 104 M_B_DIM0_CLK_DDR#1 (6) SO-DIMMB TS Address is 0x34 D
CK1#
109
(6) M_B_BS0 BA0 SA0_DIM1
108 11
(6) M_B_BS1 BA1 DM0
(6) M_B_DQ[63:0] 28
M_B_DQ0 DM1
5 46 SO-DIMMB is placed farther from
1
DDR_VREF_S3 M_B_DQ1 DQ0 DM2
7 63
M_B_DQ2 DQ1 DM3 R1502 the Processor than SO-DIMMA
15 136
M_B_DQ3 DQ2 DM4
17 153 0R0402-PAD
M_B_DQ4 DQ3 DM5
4 170
2
M_B_DQ5 DQ4 DM6 20100104 A00:

6 187
2
R1504 M_B_DQ6 DQ5 DM7 Change R1502 to 0R0402 short pad.
16
M_B_DQ7 DQ6
0R0402-PAD 18 200 PCH_SMBDATA (14,20,65,79,82)
M_B_DQ8 DQ7 SDA
21 202 PCH_SMBCLK (14,20,65,79,82)
M_VREF_CA_DIMM1 M_B_DQ9 DQ8 SCL
23
1
M_B_DQ10 DQ9 3D3V_S0

33 198 TS#_DIMM0_1 (14)
M_B_DQ11 DQ10 EVENT#
35
M_B_DQ12 DQ11
22 199
M_B_DQ13 DQ12 VDDSPD
24
1
1
M_B_DQ14 DQ13 SA0_DIM1 C1501
C1523 C1524 C1522 M_B_DQ15
34
36
DQ14 SA0
197
201 SA1_DIM1 DYC1502
DY M_B_DQ16 39
DQ15 SA1
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SC2D2U10V3KX-1GP
SC2D2U10V3KX-1GP
2
2
M_B_DQ17 DQ16
41 77
M_B_DQ18 DQ17 NC#1
51 122
M_B_DQ19 DQ18 NC#2 1D5V_S3
53 125
M_B_DQ20 DQ19 NC#/TEST
40
M_B_DQ21 DQ20
42 75
M_B_DQ22 DQ21 VDD1
50 76
M_B_DQ23 DQ22 VDD2
52 81
M_B_DQ24 DQ23 VDD3
57 82
M_B_DQ25 DQ24 VDD4
59 87
M_B_DQ26 DQ25 VDD5
67 88
DDR_VREF_S3 20101224 A00: M_B_DQ27 DQ26 VDD6
69 93
0402 0R pad: R1503 R1504. M_B_DQ28 DQ27 VDD7
56 94
M_B_DQ29 DQ28 VDD8
58 99
M_B_DQ30 DQ29 VDD9
68 100
2
M_B_DQ31 DQ30 VDD10

70 105
R1503 M_B_DQ32 DQ31 VDD11
129 106
M_B_DQ33 DQ32 VDD12
0R0402-PAD 131 111
M_B_DQ34 DQ33 VDD13
141 112
M_VREF_DQ_DIMM1 M_B_DQ35 DQ34 VDD14
143 117
1
M_B_DQ36 DQ35 VDD15

130 118
M_B_DQ37 DQ36 VDD16
C 132 123 C
M_B_DQ38 DQ37 VDD17
140 124
M_B_DQ39 DQ38 VDD18 1D5V_S3
142
1
M_B_DQ40 DQ39
C1515 C1516 C1517 M_B_DQ41
147
DQ40 VSS
2 SODIMM B DECOUPLING
149 3
DY M_B_DQ42 157
DQ41 VSS
8
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SC2D2U10V3KX-1GP
2
M_B_DQ43 DQ42 VSS

159 9
M_B_DQ44 DQ43 VSS
146 13
SC22U6D3V5MX-2GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC4D7U6D3V5KX-3GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
M_B_DQ45 DQ44 VSS
C1503
C1504
C1505
C1506
C1507
C1508
C1509
C1510
148 14
1
M_B_DQ46 DQ45 VSS
158 19
M_B_DQ47 DQ46 VSS
M_B_DQ48
160
DQ47 VSS
20
DY DY DY DY DY
163 25
2
M_B_DQ49 DQ48 VSS
165 26
M_B_DQ50 DQ49 VSS
175 31
M_B_DQ51 DQ50 VSS
177 32
M_B_DQ52 DQ51 VSS
164 37
M_B_DQ53 DQ52 VSS
166 38
M_B_DQ54 DQ53 VSS
174 43
M_B_DQ55 DQ54 VSS
Place these caps M_B_DQ56
176
DQ55 VSS
44
181 48
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
0D75V_S0 close to VTT1 and M_B_DQ57 DQ56 VSS
C1511
C1512
C1513
C1514
183 49
1
M_B_DQ58 DQ57 VSS
VTT2. M_B_DQ59
191
DQ58 VSS
54 Layout Note:
M_B_DQ60
193
DQ59 VSS
55
Place these Caps near DY
180 60
2
M_B_DQ61 DQ60 VSS
182 61 SO-DIMMB.
M_B_DQ62 DQ61 VSS
C1518
C1519
C1520
C1521
192 65
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
1
M_B_DQ63 DQ62 VSS

194 66
DQ63 VSS
DY DY M_B_DQS#0 10
VSS
71
72
2
M_B_DQS#1 DQS0# VSS

27 127
M_B_DQS#2 DQS1# VSS
45 128
M_B_DQS#3 DQS2# VSS
62 133
M_B_DQS#4 DQS3# VSS
135 134
M_B_DQS#5 DQS4# VSS
152 138
M_B_DQS#6 DQS5# VSS
169 139
M_B_DQS#7 DQS6# VSS
186
DQS7# VSS
144
145
PART NUMBER Height TYPE
M_B_DQS0 VSS
12 150
M_B_DQS1 DQS0 VSS
29 151
M_B_DQS#[7:0] (6)
M_B_DQS2 47
DQS1 VSS
155
62.10017.P41 5.2mm
M_B_DQS3 DQS2 VSS
M_B_DQS[7:0] (6) 64 156
B M_B_DQS4 DQS3 VSS B
137 161
M_B_DQS5 DQS4 VSS
M_B_DQS6
154
171
DQS5 VSS
162
167
62.10017.T91 5.2mm
M_B_DQS7 DQS6 VSS
188 168
DQS7 VSS
172
VSS
116 173
(6) M_B_DIM0_ODT0
120
ODT0 VSS
178
62.10017.T01 5.2mm
(6) M_B_DIM0_ODT1 ODT1 VSS
179
VSS
M_VREF_CA_DIMM1 126 184
VREF_CA VSS
M_VREF_DQ_DIMM1 1 185
VREF_DQ VSS
189
VSS
30 190
(14,37) DDR3_DRAMRST# RESET# VSS
195
VSS
196
VSS
0D75V_S0 203 205
VTT1 VSS
204 206
VTT2 VSS
H=5.2mm
DDR3-204P-48-GP
62.10017.P41
A A
<Core Design>
Wistron Corporation
Title
DDR3-DIMM2 SOCKET2
Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
PCH1D 4 OF 10
(27) L_BKLT_EN J47 L_BKLTEN SDVO_TVCLKINN AP43
(49) LVDS_VDD_EN M45 L_VDD_EN
Cougar SDVO_TVCLKINP AP45
(49) L_BKLT_CTRL P45 L_BKLTCTL

Point SDVO_STALLN AM42
L_DDC_DATA(PAGE17): LVDS_DDC_CLK_R SDVO_STALLP AM40
(49,97) LVDS_DDC_CLK_R T40 L_DDC_CLK DDI Port B Detect:(SDVO_CTRL_ DATA)
This signal is on the LVDS interface. (49,97) LVDS_DDC_DATA_R LVDS_DDC_DATA_R K47 AP39 1: Port B detected
L_DDC_DATA SDVO_INTN
D This signal needs to be left NC if eDP is SDVO_INTP AP40 D
RN1702 L_CTRL_CLK T45 0: Port B not detected
L_BKLT_EN used for the local flat panel display 20101224 A00: L_CTRL_DATA L_CTRL_CLK
1 4 P39 L_CTRL_DATA
2 3 LVDS_VDD_EN Change RN1704 to 0402 0 ohm pad.
LVDS_IBG AF37 P38
LVD_IBG SDVO_CTRLCLK PCH_HDMI_CLK (51)
RN
SRN100KJ-6-GP TPAD14-GP TP1701 1 LVDS_VBG AF36 M39
LVD_VBG SDVO_CTRLDATA PCH_HDMI_DATA (51)
RN1704
1
1 4 LVDS_VREFH AE48
R1701 LVDS_VREFL LVD_VREFH
2 3 AE47 LVD_VREFL DDPB_AUXN AT49
2K37R2F-GP AT47
0R4P2R-PAD DDPB_AUXP
DDPB_HPD AT40 HDMI_PCH_DET (51)
Place near PCH (49) LVDSA_CLK# AK39
LVDS
2
LVDSA_CLK#
(49) LVDSA_CLK AK40 LVDSA_CLK DDPB_0N AV42 HDMI_DATA2_R# (51)
DDPB_0P AV40 HDMI_DATA2_R (51)
(49) LVDSA_DATA0# AN48 LVDSA_DATA#0 DDPB_1N AV45 HDMI_DATA1_R# (51)
(49) LVDSA_DATA1# AM47 AV46 HDMI_DATA1_R (51)
Digital Display Interface

LVDSA_DATA#1 DDPB_1P
(49) LVDSA_DATA2# AK47 LVDSA_DATA#2 DDPB_2N AU48 HDMI_DATA0_R# (51)
AJ48 LVDSA_DATA#3 DDPB_2P AU47 HDMI_DATA0_R (51)
DDPB_3N AV47 HDMI_CLK_R# (51)
3D3V_S0 AN47 AV49
(49) LVDSA_DATA0 LVDSA_DATA0 DDPB_3P HDMI_CLK_R (51)
(49) LVDSA_DATA1 AM49 LVDSA_DATA1
RN1703 (49) LVDSA_DATA2 AK49
PCH_HDMI_DATA LVDSA_DATA2
1 8 Impedance:90 ohm AJ47 LVDSA_DATA3 DDPC_CTRLCLK P46
2 7 PCH_HDMI_CLK P42
L_CTRL_DATA DDPC_CTRLDATA
3 6
4 5 L_CTRL_CLK AF40 LVDSB_CLK#
AF39 LVDSB_CLK DDPC_AUXN AP47
SRN2K2J-2-GP 0617 Modify: AP49
DDPC_AUXP
Joseph Removed LVDSB related net for AH45 LVDSB_DATA#0 DDPC_HPD AT38 Impedance:90 ohm Impedance:100 ohm
C AH47 C
20110104 A00: single LVDS channel base on Dell updated spec. LVDSB_DATA#1
AF49 LVDSB_DATA#2 DDPC_0N AY47
Merge RN1701,RN1706 to RN1703 2.2k array resistor. AF45 AY49
20110113 A00: LVDSB_DATA#3 DDPC_0P
DDPC_1N AY43
Swap RN1703.7,RN1703.5; swap RN1703.8,RN1703.6.
AH43 LVDSB_DATA0 DDPC_1P AY45
AH49 LVDSB_DATA1 DDPC_2N BA47
AF47 LVDSB_DATA2 DDPC_2P BA48
Close to PCH side AF43 LVDSB_DATA3 DDPC_3N BB47
DDPC_3P BB49
CRT_GREEN
CRT_BLUE (50) CRT_BLUE N48 M43
CRT_RED CRT_BLUE DDPD_CTRLCLK
(50) CRT_GREEN P49 CRT_GREEN DDPD_CTRLDATA M36
(50) CRT_RED T49 CRT_RED
AT45
CRT
DDPD_AUXN
(50) CRT_DDC_CLK T39 CRT_DDC_CLK DDPD_AUXP AT43
(50) CRT_DDC_DATA M40 CRT_DDC_DATA DDPD_HPD BH41
5
6
7
8
RN1705 BB43
SRN150F-1-GP DDPD_0N
(50) CRT_HSYNC M47 CRT_HSYNC DDPD_0P BB45
(50) CRT_VSYNC M49 CRT_VSYNC DDPD_1N BF44
DDPD_1P BE44
BF42
4
3
2
1
DAC_IREF_R DDPD_2N
T43 DAC_IREF DDPD_2P BE42
T42 CRT_IRTN DDPD_3N BJ42
1
DDPD_3P BG42
R1702
Notes: 1KR2D-1-GP COUGAR-GP-U2-NF
B B
1K 0.5% 0402.
2
A <Core Design> A
Wistron Corporation
Title
PCH 1/9(LVDS/CRT/DDI)
Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
SSID = PCH
PCH1E 5 OF 10 1D8V_S0
RSVD AY7
Cougar RSVD AV7
1
BG26 TP1 RSVD AU3
BJ26 TP2
Point RSVD BG4 R1808
BH25 TP3 2K2R2J-2-GP
BJ16 TP4 RSVD AT10
BG16 BC8 R1809
2
TP5 RSVD
D RN1801 AH38 D
TP6 NV_CLE
1 10 3D3V_S0 AH37 TP7 RSVD AU2 1 2 H_SNB_IVB# (5)
INT_PIRQB# 2 9 INT_PIRQD# AK43 AT4 1KR2J-1-GP
INT_PIRQF# INT_PIRQE# TP8 RSVD
3 8 AK45 TP9 RSVD AT3
INT_PIRQA# 4 7 INT_PIRQC# C18 AT1
INT_PIRQG# TP10 RSVD
3D3V_S0 5 6 N30 TP11 RSVD AY3 DMI & FDI Termination Voltage
H3 TP12 RSVD AT5
SRN8K2J-2-GP-U AH12 AV3 Set to Vss when LOW
NVRAM
TP13 RSVD NV_CLE
AM4 TP14 RSVD AV1
AM5 TP15 RSVD BB1 Set to Vcc when HIGH
Y13 TP16 RSVD BA3
K24 TP17 RSVD BB5
L24 TP18 RSVD BB3
AB46 TP19 RSVD BB7
AB45 BE8
RSVD
R1801 TP20 RSVD
2 1 4K7R2J-2-GP PCI_GNT3# BD4
DY RSVD
BF6
RSVD
B21 AV5 NV_ALE 1D8V_S0
TP21 RSVD NV_CLE
M20 TP22 DF_TVS AY1
AY16 TP23
1
A16 swap override Strap/Top-Block BG46 AV10 NV_RCOMP 1 TP1803 TPAD14-GP Danbury Technology:
TP24 RSVD R1810
Swap Override jumper Disabled when Low.
AT8 1KR2J-1-GP
RSVD Enable when High. DY
PCI_GNT#3 Low = A16 swap BE28 AY5
2
TP25 RSVD
override/Top-Block RN1803 BC30 BA2
DGPU_HOLD_RST# TP26 RSVD NV_ALE
Swap Override enabled 1 4 BE32 TP27
DGPU_PW R_EN# 2 3 BJ32 AT12
C High = Default
BC28
TP28 RSVD
BF3
USB Ext. port 1 (HS) C
TP29 RSVD
SRN10KJ-5-GP BE30 TP30 External debug port use on Huron river platform
BF32 TP31
BG32 TP32 USBP0N C24
AV26 TP33 USBP0P A24
BB26 TP34 USBP1N C25 USB_PN1 (57)
AU28 TP35 USBP1P B25 USB_PP1 (57)
AY30 TP36 USBP2N C26 USB_PN2 (64)
AU26 TP37 USBP2P A26 USB_PP2 (64)
1 2R1802 BBS_BIT1 AY26 K28
DY 1KR2J-1-GP AV28
TP38 USBP3N
H28
USB_PN3
USB_PP3
(63)
(63)
TP39 USBP3P
1 2R1803 BBS_BIT0 AW30 E28
DY 1KR2J-1-GP BBS_BIT0 (21) TP40 USBP4N
D28
USB_PN4
USB_PP4
(82)
(82)
3D3V_S0 USBP4P
USBP5N C28 USB_PN5 (32)
USBP5P A28 USB_PP5 (32)
USBP6N C29
2 USBP6P B29
BOOT BIOS Strap INT_PIRQA# K40 N28
R1814 INT_PIRQB# PIRQA# USBP7N
K38 M28
PCI
PIRQB# USBP7P
GNT1#/GPIO51 SATA1GP/GPIO19 BOOT BIOS Location 8K2R2J-3-GP INT_PIRQC# H38 PIRQC# USBP8N L30
INT_PIRQD# G38 K30
PIRQD# USBP8P
0 0 LPC G30
1
USBP9N
C46 E30
USB
(83) DGPU_HOLD_RST# REQ1#/GPIO50 USBP9P
0 1 Reserved TPAD14-GP TP1807 1 DGPU_SELECT# C44 C30
DGPU_PW R_EN# REQ2#/GPIO52 USBP10N
E40 A30
1 0 Reserved
(93) DGPU_PW R_EN#
BBS_BIT1 D47
REQ3#/GPIO54
GNT1#/GPIO51
USBP10P
USBP11N
USBP11P
L32
K32
USB_PN11
USB_PP11
(65)
(65)
USB Table
1 1 SPI(Default) TPAD14-GP TP1806 1DGPU_PW M_SELECT# E42 GNT2#/GPIO53 USBP12N G32 USB_PN12 (49) Pair Device
TPAD14-GP TP1801 1 PCI_GNT3# F46 E32 USB_PP12 (49)
B GNT3#/GPIO55 USBP12P B
USBP13N C32 0 X
USBP13P A32
(79) HDD_FALL_INT1 1 R1812 0R0402-PAD
2 INT_PIRQE# G42 1 E-SATA / USB Combo
R1813 0R0402-PAD INT_PIRQF# PIRQE#/GPIO2
(56) SATA_ODD_DA# 1 2 G40 PIRQF#/GPIO3
(82) USB30_SMI# 1 R1815 0R0402-PAD
2 INT_PIRQG# C42 C33 USB_RBIAS 1 2 2 Fingerprint
R1817 0R0402-PAD INT_PIRQH# PIRQG#/GPIO4 USBRBIAS# R1811
(69) KB_LED_BL_DET 1 2 D44 PIRQH#/GPIO5 22D6R2F-L1-GP 3 BLUETOOTH
USBRBIAS B33
20101231 A00: RN1804 TPAD14-GP TP1802 1 PCI_PME# K10 4 Mini Card2 (WWAN)
Merge R1804,R1806 to RN1804 22 ohm array resistor. PME#
2 3
20110113 A00: PCI_PLTRST# USB_OC#0_1
Swap RN1804 base on swap report.
1 4 C6 PLTRST# OC0#/GPIO59 A14 USB_OC#0_1 (61) 5 CARD READER
K20 USB_OC#2_3
SRN22-3-GP OC1#/GPIO40 USB_OC#4_5
OC2#/GPIO41 B17 6 X
(65,71,97) CLK_PCI_LPC CLK_PCI_LPC_R H49 C16 USB_OC#6_7
R1805 CLKOUT_PCI0 OC3#/GPIO42
(20) CLK_PCI_FB 1 2 22R2J-2-GP CLK_PCI_FB_R H43 CLKOUT_PCI1 OC4#/GPIO43 L16 USB_OC#8_9 7 X
(27) CLK_PCI_KBC CLK_PCI_KBC_R J48 A16 USB_OC#10_11
CLKOUT_PCI2 OC5#/GPIO9 USB_OC#12_13
K42 CLKOUT_PCI3 OC6#/GPIO10 D14 8 X
H40 CLKOUT_PCI4 OC7#/GPIO14 C14 FFS_INT2_R (79)
2
9 X
EC1801 EC1802
KBC CLK EMI COUGAR-GP-U2-NF 10 X
DY DY
1
1
SC4D7P50V2CN-1GP
SC4D7P50V2CN-1GP
20101224 A00: 11 Mini Card1 (WLAN)

0402 0R pad: R1807. OC[3:0]# for Device 29 (Ports 0-7)
R1807 OC[7:4]# for Device 26 (Ports 8-13) 12 CAMERA
(5,27,65,71,82,83) PLT_RST# 2 1 PCI_PLTRST# 13 X
A 0R0402-PAD <Core Design> A
Wistron Corporation
1
R1816 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

RN1802 Taipei Hsien 221, Taiwan, R.O.C.
DY
100KR2J-1-GP
USB_OC#2_3 1 10 3D3V_S5 Title

C1801 2 9 USB_OC#12_13
DY
2
SC220P50V2KX-3GP R1818 10KR2J-3-GP USB_OC#6_7 USB_OC#8_9

3 8
PCH 2/9(PCI/USB/NVRAM)
2
1 2 FFS_INT2_R USB_OC#0_1 4 7 USB_OC#10_11

5 6 USB_OC#4_5 Size Document Number Rev
3D3V_S5
SRN8K2J-2-GP-U
Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
SSID = PCH (4) DMI_RXN[3:0]

(4) DMI_RXP[3:0] FDI_TXN[7:0] (4)
FDI_TXP[7:0] (4)
(4) DMI_TXN[3:0]
(4) DMI_TXP[3:0]
PCH1C 3 OF 10
BC24 BJ14
(4)
(4)
DMI_RXN0
DMI_RXN1 BE20
DMI0RXN Cougar FDI_RXN0
AY14
FDI_TXN0
FDI_TXN1
(4)
(4)
DMI1RXN FDI_RXN1
D (4) DMI_RXN2 BG18
BG20
DMI2RXN Point FDI_RXN2 BE14
BH13
FDI_TXN2 (4) D
(4) DMI_RXN3 DMI3RXN FDI_RXN3 FDI_TXN3 (4)
Signal Routing Guideline: FDI_RXN4 BC12 FDI_TXN4 (4)
DMI_ZCOMP keep W=4 mils and (4) DMI_RXP0 BE24 DMI0RXP FDI_RXN5 BJ12 FDI_TXN5 (4)
(4) DMI_RXP1 BC20 BG10 FDI_TXN6 (4)
routing length less than 500 BJ18
DMI1RXP FDI_RXN6
BG9
(4) DMI_RXP2 DMI2RXP FDI_RXN7 FDI_TXN7 (4)
mils. (4) DMI_RXP3 BJ20 DMI3RXP
DMI_IRCOMP keep W=4 mils and FDI_RXP0 BG14 FDI_TXP0 (4)
routing length less than 500 (4) DMI_TXN0 AW24 DMI0TXN FDI_RXP1 BB14 FDI_TXP1 (4)
(4) DMI_TXN1 AW20 BF14 FDI_TXP2 (4)
mils. BB18
DMI1TXN FDI_RXP2
BG13
(4) DMI_TXN2 DMI2TXN FDI_RXP3 FDI_TXP3 (4)
AV18 BE12
DMI
FDI
(4) DMI_TXN3 DMI3TXN FDI_RXP4 FDI_TXP4 (4)
FDI_RXP5 BG12 FDI_TXP5 (4)
(4) DMI_TXP0 AY24 DMI0TXP FDI_RXP6 BJ10 FDI_TXP6 (4)
(4) DMI_TXP1 AY20 DMI1TXP FDI_RXP7 BH9 FDI_TXP7 (4)
(4) DMI_TXP2 AY18 DMI2TXP
(4) DMI_TXP3 AU18 DMI3TXP
FDI_INT AW16 FDI_INT (4)
1D05V_VTT BJ24 AV12
DMI_ZCOMP FDI_FSYNC0 FDI_FSYNC0 (4) For platforms not supporting Deep S4/S5
R1901 2 49D9R2F-GP DMI_COMP_R
1 BG25 DMI_IRCOMP FDI_FSYNC1 BC10 FDI_FSYNC1 (4) 1.VccSUS3_3 and VccDSW3_3 will rise at the same time (connected on board)
R1902 1 2 750R2F-GP RBIAS_CPY BH21 DMI2RBIAS FDI_LSYNC0 AV14 FDI_LSYNC0 (4) 2.DPWROK and RSMRST# will rise at the same time (connected on board)
FDI_LSYNC1 BB10 FDI_LSYNC1 (4) 3.SLP_SUS# and SUSACK# are left as ‘no connect’
4.SUSWARN# used as SUSPWRDNACK/GPIO30
1 DY 2 R1926 SYS_PW ROK
C 10KR2J-3-GP A18 DSW ODVREN C
DSWVRMEN
1 2 R1904 PW ROK
System Power Management

100KR2J-1-GP 1 R1910 2 0R0402-PAD PM_RSMRST#
SUS_PW R_ACK 1 2 SUSACK# C12 E22 PCH_DPW ROK 1 R1911 2 10KR2J-3-GP
R1903 0R0402-PAD SUSACK# DPWROK DY RTC_AUX_S5
(5) XDP_DBRESET# 1 2 SYS_RESET# K3 B9 PCH_W AKE# (27)

R1925 0R0402-PAD SYS_RESET# WAKE#
1 2 R1905
(36)
3D3V_S0
SYS_PW ROK
DY 10KR2J-3-GP P12 N3
SYS_PWROK CLKRUN#/GPIO32 PM_CLKRUN# (27)
1R1923 2
PW ROK
DY 0R2J-2-GP PM_SUS_STAT# TP1901 TPAD14-GP
(27,36) S0_PW R_GOOD 1 2 L22 PWROK SUS_STAT#/GPIO61 G8 1
R1924 0R0402-PAD
1 R1906 2 0R0402-PAD
(45,46,47) RUNPW ROK 1 R1907 2 MEPW ROK L10 APWROK SUSCLK/GPIO62 N14 SUS_CLK 1 R1913 2 0R0402-PAD PCH_SUSCLK_KBC (27)
0R2J-2-GP DSWODVREN - On Die DSW VR Enable
DY
(5,37) PM_DRAM_PW RGD B13 D10 PM_SLP_S5# 1 HIGH Enabled (DEFAULT)
DRAMPWROK SLP_S5#/GPIO63 TP1902 TPAD14-GP
S0_PWR_GOOD after PM_SLP_S3# delay 200 ms
PM_RSMRST# C21 H4
LOW Disabled
RSMRST# SLP_S4# PM_SLP_S4# (27,46)
(27) SUS_PW R_ACK K16 SUSWARN#/SUSPWRDNACK/GPIO30 SLP_S3# F4 PM_SLP_S3# (27,36,37,46,47) RTC_AUX_S5
(27) PM_PW RBTN# E20 G10 PM_SLP_A# 1

PWRBTN# SLP_A# TP1903TPAD14-GP R1917 1 2 330KR2J-L1-GP
B B
(27) AC_PRESENT H20 G16 PM_SLP_SUS# 1

ACPRESENT/GPIO31 SLP_SUS# TP1904TPAD14-GP DSW ODVREN R1918 1 2 330KR2J-L1-GP
DY
BATLOW # E10 AP14 H_PM_SYNC
BATLOW#/GPIO72 PMSYNCH H_PM_SYNC (5)
PM_RI# A10 K14 PM_SLP_LAN# 1

RI# SLP_LAN#/GPIO29 TP1905TPAD14-GP
COUGAR-GP-U2-NF
3D3V_S0
PM_RSMRST# 1 R1912 2 RSMRST#_KBC (27)
0R0402-PAD
PM_CLKRUN# R1919 1 2 8K2R2J-3-GP
3D3V_S5
RN1901
8 1 BATLOW #
7 2 PM_RI# PCH_SUSCLK_KBC
6 3 PCH_W AKE#
5 4 SUS_PW R_ACK
2
SRN10KJ-6-GP EC1901
DY
SC4D7P50V2CN-1GP
R1921
2 1 AC_PRESENT
A 100KR2J-1-GP <Core Design> A
R1922 2 1 10KR2J-3-GP PM_PW RBTN#

R1920 2 DY 1 10KR2J-3-GP PM_SLP_LAN#
DY Wistron Corporation
Title
2 R1908 1 PM_RSMRST# PCH 3/9(DM I/FDI/PM)

10KR2J-3-GP Size Document Number Rev
Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
3D3V_S5
3D3V_S5
SSID = PCH SMB_CLK 4 1 RN2003
1
SMB_DATA 3 2 SRN2K2J-1-GP
R2004
DY 10KR2J-3-GP SML0_DATA 3 2 RN2004
PCH1B 2 OF 10 SML0_CLK 4 1 SRN2K2J-1-GP
2
BG34 Cougar PEG_CLKREQ#_R SML1_CLK 2 3 RN2005
PERN1 EC_SW I# SML1_DATA
BJ34 PERP1 SMBALERT#/GPIO11 E12 EC_SW I# (27) 1 4 SRN2K2J-1-GP
1
AV32 PETN1 Point SMB_CLK R2005 PCIE_CLK_REQ6#
AU32 PETP1 SMBCLK H14 1 4 RN2006
D 10KR2J-3-GP PCH_GPIO74 2 3 SRN10KJ-5-GP D
BE34 C9 SMB_DATA
(82) PCIE_RXN2 PERN2 SMBDATA
(82) PCIE_RXP2 BF34
2
C2001 PERP2
(82) PCIE_TXN2 1 2 SCD1U10V2KX-5GP PCIE_TXN2_C BB32 PETN2 LAN
C2002 1 2 SCD1U10V2KX-5GP PCIE_TXP2_C AY32 DRAMRST_CNTRL_PCH 1 R2009 2
SMBUS
(82) PCIE_TXP2 PETP2 DRAMRST_CNTRL_PCH 1KR2J-1-GP
SML0ALERT#/GPIO60 A12 DRAMRST_CNTRL_PCH (37)
BG36 3D3V_S0
(82) PCIE_RXN3 PERN3
BJ36 C8 SML0_CLK RN2007
(82) PCIE_RXP3 PERP3 SML0CLK
C2011 1 2 SCD1U10V2KX-5GP PCIE_TXN3_C AV34 2 3
(82) PCIE_TXN3 C2012 1 2 SCD1U10V2KX-5GP PCIE_TXP3_C AU34
PETN3 W-WAN G12 SML0_DATA 1 4
(82) PCIE_TXP3 PETP3 SML0DATA
BF36 SRN2K2J-1-GP
(65) PCIE_RXN4 PERN4
BE36 WLAN
(65) PCIE_RXP4
C2005 1 2 SCD1U10V2KX-5GP PCIE_TXN4_C AY34
PERP4
C13 PCH_GPIO74 2nd = 84.DM601.03F
(65) PCIE_TXN4 C2006 PETN4 SML1ALERT#/PCHHOT#/GPIO74 84.2N702.A3F
(65) PCIE_TXP4 1 2 SCD1U10V2KX-5GP PCIE_TXP4_C BB34 PETP4
E14 SML1_CLK 2N7002KDW -GP
PCI-E*
SML1CLK/GPIO58 SML1_CLK (27,85)
(82) PCIE_RXN5 BG37 PERN5
BH37 M16 SML1_DATA SMB_DATA 6 1
(82) PCIE_RXP5 PERP5 SML1DATA/GPIO75 SML1_DATA (27,85) PCH_SMBDATA (14,15,65,79,82)
C2009 1 2 SCD1U10V2KX-5GP PCIE_TXN5_C AY36
(82) PCIE_TXN5 C2010 1 2 SCD1U10V2KX-5GP PCIE_TXP5_C BB36
PETN5 USB3.0 5 2
(82) PCIE_TXP5 PETP5
BJ38 PERN6 4 3
BG38
Controller
PERP6 CL_CLK
AU36 PETN6 Intel GBE LAN CL_CLK1 M7 1 Q2001
AV36 TP2001 TPAD14-GP
PETP6
Link
PCH_SMBCLK (14,15,65,79,82)
BG40 T11 CL_DATA 1
PERN7 CL_DATA1 TP2002 TPAD14-GP SMB_CLK
BJ40 PERP7
AY40 PETN7 Dock
C BB40 P10 CL_RST# 1 C
PETP7 CL_RST1# TP2003 TPAD14-GP 20110112 A00:
BE38 Change C2007,C2008 to 15pF from 12pF base on vendor's report.
20101224 A00: PERN8 C2008
BC38 PERP8 NEW CARD
Change RN2011~RN2014 to 0402 0 ohm pad. AW38 XTAL25_IN 2 1
PETN8 X2001
AY38 PETP8
RN
SC15P50V2JN-2-GP
PEG_A_CLKRQ#/GPIO47 M10 PEG_CLKREQ#_R 1 2R2003
DY 0R2J-2-GP PEG_CLKREQ# (85) 1 4
2
RN
(82) CLK_PCIE_W W AN# 1 RN2011 4 CLK_PCH_SRC0_N Y40 CLKOUT_PCIE0N
::$1&/. (82) CLK_PCIE_W W AN 2 3 CLK_PCH_SRC0_P Y39 R2006
0R4P2R-PAD CLKOUT_PCIE0P CLKOUT_PEG_A_N
CLKOUT_PEG_A_N AB37 1 RN2016 4 CLK_PCIE_VGA# (83) 1M1R2J-GP
CLOCKS
(82) CLK_PCIE_W W AN_REQ# J2 AB38 CLKOUT_PEG_A_P 2 3 CLK_PCIE_VGA (83) 2 3
PCIECLKRQ0#/GPIO73 CLKOUT_PEG_A_P 0R4P2R-PAD C2007
1
XTAL25_OUT 2 1
:/$1&/. 2 RN2012 3
(65) CLK_PCIE_W LAN# CLK_PCH_SRC1_N AB49 AV22 CLKOUT_DMI_N 2 RN2010 3 CLK_EXP_N (5) XTAL-25MHZ-155-GP
CLK_PCH_SRC1_P AB47 CLKOUT_PCIE1N CLKOUT_DMI_N CLKOUT_DMI_P SC15P50V2JN-2-GP
(65) CLK_PCIE_W LAN 1 4 CLKOUT_PCIE1P CLKOUT_DMI_P AU22 1 4 CLK_EXP_P (5)
0R4P2R-PAD 0R4P2R-PAD
(65) CLK_PCIE_W LAN_REQ# M1 20101224 A00: 82.30020.D41
2nd = 82.30020.G71
PCIECLKRQ1#/GPIO18
RN
RN
Change RN2016,RN2010 to 0402 0 ohm pad.
CLKOUT_DP_N AM12 3rd = 82.30020.G61
CLKOUT_DP_P AM13
AA48 3D3V_S0 3D3V_S0
CLKOUT_PCIE2N
AA47 CLKOUT_PCIE2P
UMA_DISCRETE#
BF18 CLK_BUF_EXP_N UMA: 1 1
CLKIN_DMI_N
1
PCIE_CLK_RQ2# V10 BE18 CLK_BUF_EXP_P
PCIECLKRQ2#/GPIO20 CLKIN_DMI_P R2012 R2013 DIS :0 1
RN2008 SRN10KJ-5-GP SG(PX) : 0 0
DY
10KR2J-3-GP
10KR2J-3-GP
(82) CLK_PCIE_LAN# 2 RN2014 3 CLK_PCH_SRC3_N Y37 CLKOUT_PCIE3N CLKIN_GND1_N BJ30 CLK_BUF_CPYCLK_N 2 3 ATI(Muxless) : 1 0
/$1&/. (82) CLK_PCIE_LAN 1 4 CLK_PCH_SRC3_P Y36 BG30 CLK_BUF_CPYCLK_P 1 4
2
0R4P2R-PAD CLKOUT_PCIE3P CLKIN_GND1_P UMA_DIS#
B UMA_DIS# (22) B
(82) PCIE_CLK_LAN_REQ# A8 DGPU_PRSNT#
PCIECLKRQ3#/GPIO25
RN
RN
G24 CLK_BUF_DOT96_N
CLKIN_DOT_96N
1
E24 CLK_BUF_DOT96_P
CLKIN_DOT_96P
(82) CLK_PCIE_USB3# 1 RN2013 4 CLK_PCH_SRC4_N Y43 CLKOUT_PCIE4N PL 10K FOR Integrated CLOCK GEN mode. R2010 R2011
86%&/. 2 3 CLK_PCH_SRC4_P Y45 DY
10KR2J-3-GP
10KR2J-3-GP
(82) CLK_PCIE_USB3 0R4P2R-PAD CLKOUT_PCIE4P CLK_BUF_CKSSCD_N RN2020 SRN10KJ-5-GP
CLKIN_SATA_N AK7
(82) USB3_PEGB_CLKREQ# L12 AK5 CLK_BUF_CKSSCD_P CLK_BUF_DOT96_N 1 4
2
PCIECLKRQ4#/GPIO26 CLKIN_SATA_P CLK_BUF_DOT96_P 2 3
V45 K45 CLK_BUF_REF14

CLKOUT_PCIE5N REFCLK14IN RN2021
V46 CLKOUT_PCIE5P CLK_BUF_CKSSCD_N 2 3 SRN10KJ-5-GP 3D3V_S5 RN2001
PCIE_CLK_REQ5# L14 H45 CLK_PCI_FB CLK_PCI_FB (18) CLK_BUF_CKSSCD_P 1 4 1 8 CLK_PCIE_W W AN_REQ#
PCIECLKRQ5#/GPIO44 CLKIN_PCILOOPBACK
2 7
3 6 PCIE_CLK_LAN_REQ#
AB42 V47 XTAL25_IN 4 5 USB3_PEGB_CLKREQ#
3D3V_S0 CLKOUT_PEG_B_N XTAL25_IN XTAL25_OUT RN2019 SRN10KJ-5-GP
AB40 CLKOUT_PEG_B_P XTAL25_OUT V49
RN2018 CLK_BUF_EXP_N 1 4 SRN10KJ-6-GP
1 4 PCIE_CLK_RQ2# PEG_B_CLKRQ# E6 CLK_BUF_EXP_P 2 3 RN2002
CLK_PCIE_W LAN_REQ# PEG_B_CLKRQ#/GPIO56 R2007
2 3 1 8 EC_SW I#
Y47 XCLK_RCOMP
1 2 +VCCDIFFCLKN 2 7 PCIE_CLK_REQ5#
SRN10KJ-5-GP XCLK_RCOMP 90D9R2F-1-GP CLK_BUF_REF14
V40 CLKOUT_PCIE6N 1 R2008 2 3 6 CLK_PCIE_NEW _REQ#
PCIECLKRQ1# and PCIECLKRQ2# V42 CLKOUT_PCIE6P 4 5 PEG_B_CLKRQ#
10KR2J-3-GP
Support S0 power only PCIE_CLK_REQ6# T13 PCIECLKRQ6#/GPIO45
need very close to PCH SRN10KJ-6-GP
V38 CLKOUT_PCIE7N CLKOUTFLEX0/GPIO64 K43 JTAG_TCK 1R2001 DY2 JTAG_TCK_VGA (83,85)

V37 22R2J-2-GP
FLEX CLOCKS
CLKOUT_PCIE7P CLK_48_USB30
A CLKOUTFLEX1/GPIO65 F47 1R2016 2 For RTS5138<Core Design>
CLK_PCH_48M (32,97) A
CLK_PCIE_NEW _REQ# K12 22R2J-2-GP
PCIECLKRQ7#/GPIO46
CLKOUTFLEX2/GPIO66 H47 CLKOUTFLEX2 1 For VGA_ 27M
ITPXDP_N TP2007 TPAD14-GP
TPAD14-GP TP2005
1
1 ITPXDP_P
AK14
AK13
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P CLKOUTFLEX3/GPIO67 K49 DGPU_PRSNT# Wistron Corporation
TPAD14-GP TP2006 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
COUGAR-GP-U2-NF
Title
– Prioritize 27/14/24/48/25-MHz FLEX on FLEX1 and FLEX3 PCH 4/9(PCI-E/SMBUS/CLOCK/CL)

– Do not configure 27/14/24/48/25-MHz FLEX clock on FLEX0 and FLEX2
if more than 2 PCI clocks + PCI loopback are routed. Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
20110110 A00:
Merge R2115,R2116 to RN2101.
20110113 A00:
SSID = PCH RTC_AUX_S5
RN2101
2 3 INTVRMEN- Integrated SUS
1 4
RTC_X1 1.05V VRM Enable
1
SRN20KJ-1-GP C2103 High - Enable internal VRs
1 2 RTC_X2 SC1U6D3V2KX-GP
R2101 10MR2J-L-GP
Low - Enable external VRs
2
D D
PCH1A 1 OF 10 LPC_AD[0..3]
X2101 LPC_AD[0..3] (27,65,71)
1 4 RTC_X1 A20 C38 LPC_AD0
RTCX1 Cougar FWH0/LAD0
A38 LPC_AD1
FWH1/LAD1
LPC
RTC_X2 C20 Point B37 LPC_AD2
SC15P50V2JN-2-GP
RTCX2 FWH2/LAD2
1
1
C2101
2 3 C37 LPC_AD3
C2102 RTC_RST# FWH3/LAD3
D20 RTCRST#
X-32D768KHZ-67-GP SC15P50V2JN-2-GP D36 LPC_FRAME# (27,65,71)
2
2
FWH4/LFRAME#
2
82.30001.A81 G2101 1M1R2J-GP SRTC_RST# G22 SRTCRST#
1
2nd = 82.30001.691 C2104 R2104 E36
LDRQ0#
RTC
SC1U6D3V2KX-GP 2 1 SM_INTRUDER# K22 K36 KB_DET# (69)
INTRUDER# LDRQ1#/GPIO23
3rd = 82.30001.861 GAP-OPEN
2
RTC_AUX_S5 1 2 PCH_INTVRMEN C17 V5 INT_SERIRQ (27)
1
INTVRMEN SERIRQ
R2105
330KR2F-L-GP AM3 SATA_RXN0 (56)
33R2J-2-GP2 SATA0RXN
1R2122 HDA_SYNC HDA_BITCLK N34 AM1
(29) HDA_CODEC_SYNC 33R2J-2-GP2 DY 1R2123 HDA_SDOUT
HDA_BCLK SATA0RXP SATA_RXP0 (56)
HDD1
SATA 6G
(29) HDA_CODEC_SDOUT SATA0TXN AP7 SATA_TXN0 (56)
HDA_SYNC L34 AP5 SATA_TXP0 (56)
HDA_SYNC SATA0TXP
T10 AM10
RN2102
HDA_RST#
(29) HDA_SPKR
HDA_RST#
SPKR SATA1RXN
SATA1RXP AM8 HDD2
(29) HDA_CODEC_RST# 1 4 K34 HDA_RST# SATA1TXN AP11
2 3 HDA_BITCLK AP10
(29) HDA_CODEC_BITCLK SATA1TXP
SRN33J-5-GP-U (29) HDA_SDIN0 E34 AD7
HDA_SDIN0 SATA2RXN
SATA2RXP AD5
G34 AH5
C Notes: HDA_SDIN1 SATA2TXN
AH4 C
SATA2TXP
ME_UNLOCK (HDA_SDO) connect to EC. C34 HDA_SDIN2
IHDA
SATA3RXN AB8
Make sure EC drive this pin "low" all the time. A34 HDA_SDIN3 SATA3RXP AB10
AF3
SATA3TXN
SATA3TXP AF1
Flash Descriptor Security Overide HDA_SDOUT A36 HDA_SDO
1 R2107 2 1KR2J-1-GP
SATA
(27) ME_UNLOCK SATA4RXN Y7 SATA_RXN4 (56)
Low = Default Y5
+3VS_+1.5VS_HDA_IO
HDA_SDOUT High = Enable (49) CE CE C36 HDA_DOCK_EN#/GPIO33
SATA4RXP
SATA4TXN AD3
SATA_RXP4
SATA_TXN4
(56)
(56) ODD
SATA4TXP AD1 SATA_TXP4 (56)
N32 HDA_DOCK_RST#/GPIO13
Y3
DY 1 R2102 21KR2J-1-GP HDA_SDOUT SATA5RXN
Y1
SATA_RXN5 (57)
TPAD14-GP TP2101 PCH_JTAG_TCK_BUF

SATA5RXP
SATA5TXN AB3
SATA_RXP5
SATA_TXN5
(57)
(57) ESATA
1 J3 JTAG_TCK SATA5TXP AB1 SATA_TXP5 (57)
NO REBOOT STRAP TPAD14-GP TP2102 1 PCH_JTAG_TMS H7 Y11 1D05V_VTT

3D3V_S0 JTAG_TMS SATAICOMPO
JTAG
No Reboot Strap TPAD14-GP TP2103 1 PCH_JTAG_TDI K5 Y10 SATA_COMP R2112 1 2 37D4R2F-GP
JTAG_TDI SATAICOMPI
DY1 R2106 21KR2J-1-GP HDA_SPKR Low = Default TPAD14-GP TP2104 1 PCH_JTAG_TDO H1 1D05V_VTT
JTAG_TDO
HDA_SPKR High = No Reboot SATA3RCOMPO AB12
AB13 SATA3_COMP R2113 1 2 49D9R2F-GP

SATA3COMPI
+3VS_+1.5VS_HDA_IO 1 2 PCH_SPI_CLK T3 AH1 RBIAS_SATA3 R2114 1 2 750R2F-GP

(27,60) SPI_CLK_R SPI_CLK SATA3RBIAS
R2108 33R2J-2-GP
B B
1 R2103 2 1KR2J-1-GP HDA_SYNC (27,60) SPI_CS0#_R 1 2 PCH_SPI_CS0# Y14 SPI_CS0#
R2109 33R2J-2-GP
This signal has a weak internal pull down. T1 SPI_CS1#
SPI
On Die PLL VR is supplied by 1.5V when SATALED# P3 SATA_LED# (68)
sampled high, 1.8 V when sampled low.
(27,60) SPI_SI_R 1 2 PCH_SPI_SI V4 SPI_MOSI SATA0GP/GPIO21 V14 SATA_DET#0
Needs to be pulled High for Huron River platform. R2110 33R2J-2-GP
co-operate with R2310 (27,60) SPI_SO_R U3 P1 BBS_BIT0 BBS_BIT0 (18)
SPI_MISO SATA1GP/GPIO19
COUGAR-GP-U2-NF
PLL ODVR VOLTAGE
HDA_SYNC: This strap is sampled on rising edge of RSMRST# and is used to
Low = 1.8V (Default)
HDA_SYNC High = 1.5V sample 1.5V VccVRM supply mode. 1K external pull-up resistor is required on this
signal on the board. Signal may have leakage paths via powered off devices (Audio
Codec) and hence contend with the external pull-up. A blocking FET is
recommended in such a case to isolate HDA_SYNC from the Audio Codec device
until after the Strap sampling is complete.
3D3V_S0
RUN_ENABLE 2N7002K-2-GP
RN2103
G SATA_DET#0 1 8
R2124 INT_SERIRQ 2 7
D HDA_SYNC_R 2 1 HDA_SYNC (22) S_GPIO 3 6
EC_SMI# 4 5
(22,27) EC_SMI#
A HDA_CODEC_SYNCS 33R2J-2-GP HDA_CODEC_BITCLK HDA_CODEC_SDOUT SPI_CS0#_R <Core Design> A
SRN10KJ-6-GP
2
Q2101 RN2104
2
R2117 84.2N702.J31
100KR2J-1-GP
2ND = 84.2N702.031 EC2102 EC2103 EC2101
(22)
(22)
FP_DET#
PSW _CLR#
4
3
1
2 Wistron Corporation
DY DY DY
1
1
SC4D7P50V2CN-1GP
SC4D7P50V2CN-1GP
SC4D7P50V2CN-1GP
SRN10KJ-5-GP Taipei Hsien 221, Taiwan, R.O.C.

1
Title
PCH 5/9(SPI/RTC/LPC/SATA/IHDA)
Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
3D3V_S0 SSID = PCH GSENSOR_ADI GSENSOR_ST

R2202 Note: R2205 DY 10K
1 2 SATA_ODD_PRSNT# For PCH debug with XDP, need to NO STUFF R2218
PCH1F 6 OF 10
100KR2J-1-GP R2206 100K DY
S_GPIO 1 R2218 2 GPIO0 T7 C40
3D3V_S0
(21) S_GPIO 100R2J-2-GP BMBUSY#/GPIO0 Cougar TACH4/GPIO68 SATA_ODD_PW RGT (56)
(21,27) EC_SMI# EC_SMI# A42 Point B41 UMA_DIS# UMA_DIS# (20)

TACH1/GPIO1 TACH5/GPIO69
RN2203
D 1 4 H_A20GATE DGPU_HPD_INTR# H36 C41 VRAM_SIZE1 1 TP2204 TPAD14-GP 3D3V_S0 D
H_RCIN# TACH2/GPIO6 TACH6/GPIO70
2 3
EC_SCI# E38 A40 VRAM_SIZE2 1 TP2205 TPAD14-GP
(27) EC_SCI# TACH3/GPIO7 TACH7/GPIO71
1
SRN10KJ-5-GP
GPIO27 has a weak[20K] internal pull up. ICC_EN# C10 R2205
GPIO8
To enable on-die PLL Voltage regurator,
RTC_DET#
GSENSOR_ST 10KR2J-3-GP
should not place external pull down. (60) RTC_DET# C4 LAN_PHY_PWR_CTRL/GPIO12
2
PCH_GPIO15 G2 P4 H_A20GATE (27) GSENSOR_DET
GPIO15 A20GATE
1
AU16 H_PECI_R R2203
DY1 2 H_PECI (5,27)
CPU/MISC
20100104 A00: PECI 0R2J-2-GP
(56) SATA_ODD_PRSNT# 1 2 PCH_GPIO16 U2 SATA4GP/GPIO16 GSENSOR_ADI R2206
3D3V_S0 Merge RN2201,R2222,R2223 to 10k array resistor. R2213 0R0402-PAD P5 100KR2J-1-GP
20110113 A00: RCIN# H_RCIN# (27)
GPIO
Combine PCH_TEMP_ALERT#,MFG_MODE to RN2202. DGPU_PW ROK
(86,92,93) DGPU_PW ROK D40 AY11 H_CPUPW RGD (5,36)
2
Combine EC_SCI#,DGPU_HPD_INTR# to RN2204 TACH0/GPIO17 PROCPWRGD
1R2220 2 PCH_GPIO48
10KR2J-3-GP (49) DBC_EN DBC_EN T5 AY10 PCH_THERMTRIP_R R2204 1 2 390R2J-1-GP H_THERMTRIP# (5,36)
SCLOCK/GPIO22 THRMTRIP#
3G_EN E8 T14 INIT3_3V# 1 TP2201 TPAD14-GP
(82) 3G_EN GPIO24/MEM_LED INIT3_3V#
3D3V_S0 TPAD14-GP TP2203 1 PCH_GPIO27 E16 GPIO27
RN2202 PLL_ODVR_EN P8 GPIO28
TS_VSS1 AH8
PCH_TEMP_ALERT# 1 4 PSW _CLR# K1
(21) PSW _CLR# STP_PCI#/GPIO34
MFG_MODE 2 3 AK11 TS Signal Disable Guideline:
TS_VSS2
(21) FP_DET# K4 GPIO35
SRN10KJ-5-GP AH10 TS_VSS1, TS_VSS2, TS_VSS3 and TS_VSS4
TS_VSS3
2
GAP-OPEN
DMI_OVRVLTG V8 should not float on the motherboard. They should
RN2204 SATA2GP/GPIO36
C
TS_VSS4 AK10 TS_VSS 1 2 C
G2201 FDI_OVRVLTG M5 SATA3GP/GPIO37
R2219 0R0402-PAD be tied to GND directly.
EC_SCI# 1 4 P37
DGPU_HPD_INTR# MFG_MODE NC_1
2 3 N2
1
SLOAD/GPIO38
SRN10KJ-5-GP GSENSOR_DET M3 SDATAOUT0/GPIO39
PCH_GPIO48 V13 BG2
R2214 10KR2J-3-GP SDATAOUT1/GPIO48 NCTF_VSS#BG2
DBC_EN PCH_TEMP_ALERT# 3D3V_S0
1 DY 2 V3 SATA5GP/GPIO49 NCTF_VSS#BG48 BG48
PCH_GPIO57 D6 BH3
GPIO57 NCTF_VSS#BH3
1
FDI TERMINATION VOLTAGE OVERRIDE
20100104 A00: BH47 R2207
Merge RN2215,R2216 to RN2201 10k array resistor. NCTF_VSS#BH47 10KR2J-3-GP
3D3V_S5 TPAD14-GP TP2206 PCH_NCTF_1
1 A4 NCTF_VSS#A4 NCTF_VSS#BJ4 BJ4 DY
RN2201 GPIO37 LOW - Tx, Rx terminated to same voltage
2
A44 BJ44 FDI_OVRVLTG (FDI_OVRVLTG) (DC Coupling Model DEFAULT)
A4,A44,A45,A46,A5,A6,B3,B47,BD1,BD49,BE1,BE49,BF1,BF49
RTC_DET# NCTF_VSS#A44 NCTF_VSS#BJ44
1 4
1
PCH_GPIO57 2 3 A45 BJ45
NCTF_VSS#A45 NCTF_VSS#BJ45
BG2,BG48,BH3,BH47,BJ4,BJ44,BJ45,BJ46,BJ5,BJ6,C2,C48
R2208
NCTF
SRN10KJ-5-GP A46 BJ46 10KR2J-3-GP
NCTF TEST PIN:

NCTF_VSS#A46 NCTF_VSS#BJ46
1R2217 DY2 A5 BJ5
2
10KR2J-3-GP NCTF_VSS#A5 NCTF_VSS#BJ5
A6 NCTF_VSS#A6 NCTF_VSS#BJ6 BJ6 DMI TERMINATION VOLTAGE OVERRIDE
PCH_GPIO15 1 R2201 2 B3 C2
1KR2J-1-GP NCTF_VSS#B3 NCTF_VSS#C2
B 3D3V_S0 B
B47 C48 GPIO36 LOW - Tx, Rx terminated to same voltage
R2221 NCTF_VSS#B47 NCTF_VSS#C48
(DMI_OVRVLTG) (DC Coupling Model DEFAULT)
3G_EN 1 2 BD1 D1
NCTF_VSS#BD1 NCTF_VSS#D1
1
10KR2J-3-GP
D1,D49,E1,E49,F1,F49
BD49 D49 R2209
NCTF_VSS#BD49 NCTF_VSS#D49 10KR2J-3-GP
TPAD14-GP TP2207 1 PCH_NCTF_2 BE1 E1 DY Integrated Clock Enable functionality is achieved
NCTF_VSS#BE1 NCTF_VSS#E1
via soft-strap. The default is integrated clock
2
TPAD14-GP TP2208 1 PCH_NCTF_3 BE49 E49 DMI_OVRVLTG
NCTF_VSS#BE49 NCTF_VSS#E49
enable.
1
BF1 NCTF_VSS#BF1 NCTF_VSS#F1 F1
R2210
For thermal sensor detection. TPAD14-GP TP2209 1 PCH_NCTF_4 BF49 NCTF_VSS#BF49 NCTF_VSS#F49 F49 10KR2J-3-GP
Integrated Clock Chip Enable
2
3D3V_S0 COUGAR-GP-U2-NF
ICC_EN# HIGH (R2211 DY)- DISABLED [DEFAULT]
1
LOW (R2211)- ENABLED

R2224 ICC_EN#1 R2211 2
1KR2J-1-GP
DY 10KR2J-3-GP GPIO8 has a weak[20K] internal pull up.
Integrated Clock Enable functionality is achieved
via soft-strap. The default is integrated clock
2
enable.
VRAM_SIZE1
A <Core Design> A
1
R2225 PLL ON DIE VR ENABLE

10KR2J-3-GP
DY
NOTE:This signal has a weak internal pull-up 20K Wistron Corporation
ENABLED -- HIGH (R2212 UNSTUFFED) DEFAULT
2

DISABLED -- LOW (R2212 STUFFED)
Title
PCH 6/9(GPIO/CPU)
PLL_ODVR_EN DY 1 R2212 2 Size Document Number Rev
1KR2J-1-GP
Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
SSID = PCH 6A 3D3V_DAC_S0
1
20101228 A00:
0402 0R pad: R2301. R2301
0R0402-PAD 3D3V_S0
1D05V_VTT
PCH1G POWER 7 OF 10 (0.1uF/0.01uF x1)
0.001A (10uF x1_0603)
2
1.3A Cougar L2301
AA23 U48 +VCCA_DAC_1_2 1 DY 2
SCD01U16V2KX-3GP
D D
AC23
VCCCORE Point VCCADAC HCB1608KF-181-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC10U6D3V5KX-1GP
VCCCORE
1
CRT
C2301
C2302
C2303
C2304
(1uFx3) AD21 C2313 C2314 C2315
VCCCORE 68.00214.051
1
(10uFx1_0603) AD23 U47 2nd = 68.00206.041
SCD1U10V2KX-5GP
SC10U6D3V5KX-1GP
VCCCORE VSSADAC
VCC CORE
AF21 3rd = 68.00335.081
2
VCCCORE
AF23
2
VCCCORE 3D3V_S0
AG21 VCCCORE 0.001A
AG23 VCCCORE +3VS_VCCA_LVDS
0.001A
AG24 VCCCORE VCCALVDS AK36 1 R2304 2
AG26 0R0603-PAD
VCCCORE
AG27 VCCCORE VSSALVDS AK37
AG29 VCCCORE
AJ23
LVDS
VCCCORE 1D8V_S0
AJ26 VCCCORE VCCTX_LVDS AM37 0.06A
AJ27 VCCCORE +1.8VS_VCCTX_LVDS
0.06A
AJ29 AM38 1 R2305 2
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
VCCCORE VCCTX_LVDS 0R0805-PAD
AJ31 VCCCORE
C2316
C2317
VCCTX_LVDS AP36
1
1D05V_VTT C2318 (0.01uF x2)
AP37 (22uF x1)
SC10U6D3V5KX-1GP
VCCTX_LVDS
AN19
2
VCCIO
TPAD14-GP TP2301 1 VCCAPLLEXP BJ22

1D05V_VTT VCCAPLLEXP
(10uF x1)
2.925A(Total current of VCCIO) V33
HVCMOS
VCC3_3
AN16 VCCIO 3D3V_S0
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC10U6D3V5KX-1GP
C2305
C2306
C2307
C2308
C2309
(1uF x4) AN17 VCCIO 0.266A (0.1uFx1)
1
1
C V34 C
VCC3_3 20101224 A00:
1
AN21 0402 0R pad: R2301,R2306,R2307,R2308.
2
2
VCCIO C2319
AN26 SCD1U10V2KX-5GP 1D5V_S0
R2308
2
VCCIO
0.16A VCCVRM
AN27 VCCIO VCCVRM AT16 2 1
1D05V_VTT
AP21 VCCIO 0.042A R2306 0R0402-PAD
AP23 AT20 +1.05VS_VCC_DMI 2 1
VCCIO VCCDMI
(1uF x1)
DMI
1
AP24
VCCIO
VCCIO C2320 0R0402-PAD
AP26 AB36 SC1U6D3V2KX-GP
2
VCCIO VCCCLKDMI
1D05V_VTT
AT24 VCCIO 0.02A R2307
+1.05VS_VCC_DMI_CCI
0.02A
0.266A (Totally VCC3_3 current) 2 1
AN33 VCCIO
1
0R0402-PAD
(1uFx1)
3D3V_S0 AN34 AG16 C2321 (10uFx1)
VCCIO VccDFTERM SC1U6D3V2KX-GP
2
NAND / SPI
(0.1uF x1) BH29 VCC3_3 VccDFTERM AG17
1
C2310
0.159A(Totally current of VCCVRM) SCD1U10V2KX-5GP AJ16
2
VccDFTERM 1D8V_S0
B B
1D5V_S0 AP16 VCCVRM 0.19A 0.19A
VccDFTERM AJ17
VCCVRM(Internal PLL and VRMs):
1
TPAD14-GP TP2302 1 VCCFDIPLL BG6 C2322
A.1.5V for Mobile VCCAFDIPLL SCD1U10V2KX-5GP (0.1uFx1)
B.1.8 V for Desktop
2
1D05V_VTT AP17 VCCIO
FDI
VCCSPI V1
3D3V_S5
+1.05VS_VCC_DMI AU20 0.02A 0.02A
VCCDMI
0.042A (Totally current of VCCDMI)
1
COUGAR-GP-U2-NF (1uFx1)
C2323
SC1U6D3V2KX-GP
2
3.3V CRT LDO
5V_S5 3D3V_DAC_S0
3D3V_S0 U2301 Current Limit=360mA
1 VIN VOUT 5
2 GND
A 3 EN NC#4 4 <Core Design> A
1
C2311 G9091-330T11U-GP C2312

74.09091.J3F Wistron Corporation
SC1U10V2KX-1GP
SC1U6D3V2KX-GP
2

2nd = 74.09198.G7F Taipei Hsien 221, Taiwan, R.O.C.
Title
3rd = 74.07716.A7F
PCH 7/9(POWER1)
Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
SSID = PCH
PCH1J POWER 10 OF 10 1D05V_VTT
TPAD14-GP TP2401 1 VCCACLK AD49 N26

VCCACLK Cougar VCCIO
(1uFx1)
1
0.002A Point VCCIO P26
3D3V_S5 1 R2403 2 +VCCPDSW T16 VCCDSW3_3
C2423
3D3V_S0 0R0603-PAD P28 SC1U6D3V2KX-GP
2
VCCIO
(0.1uFx1)
TPAD14-GP TP2405 1 DCPSUSBYP V12 T27
DCPSUSBYP VCCIO 3D3V_S5 5V_S5
(10uFx1)
(1uFx1) VCCIO T29
D +V3.3S_VCC_CLKF33 T38 3D3V_S5 D
VCC3_3
2
L2401 0.097A (Totally current of VCCSUS3_3)
1 2 +V3.3S_VCC_CLKF33 T23 D2401
IND-10UH-218-GP C2401 TPAD14-GP TP2404 +VCCAPLL_CPY_PCH VCCSUS3_3
1 BH23 VCCAPLLDMI2
(0.1uFx1) CH751H-40PT-GP
1
68.10050.10Y T24 C2424 2nd = 83.R2004.B8F 83.R0304.A8F
C2402 VCCSUS3_3 SCD1U10V2KX-5GP R2408
2nd = 68.10090.10B 1D05V_VTT (10uFx1) AL29
SC10U6D3V5KX-1GP
1
SC1U10V2KX-1GP VCCIO
V23 1 2
USB
2
2
VCCSUS3_3
TPAD14-GP TP2402 1 +VCCSUS1 AL24 V24 3D3V_S5 10R2J-2-GP (0.1uFx1)
DCPSUS VCCSUS3_3
1
P24 C2426
VCCSUS3_3 SCD1U10V2KX-5GP
(0.1uFx1)
2
1
AA19 VCCASW
T26 1D05V_VTT C2425
VCCIO SCD1U10V2KX-5GP
AA21
2
VCCASW
+5VA_PCH_VCC5REFSUS
0.001A
AA24 VCCASW V5REF_SUS M26
3D3V_S0 5V_S0
Clock and Miscellaneous

AA26 VCCASW
AN23 +VCCA_USBSUS 1 TP2403 TPAD14-GP
1D05V_VTT DCPSUS
AA27 VCCASW
2
1.01A (Total current of VCCASW) VCCSUS3_3 AN24 3D3V_S5
AA29 VCCASW DYC2437
SC1U10V2KX-1GP
D2402
CH751H-40PT-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
2
C2406
C2407
C2408
(22uFx2_0603) C2403 C2404 AA31 2nd = 83.R2004.B8F 83.R0304.A8F
VCCASW
1
1
(1uFx3) 0.001A R2407
1
AC26 P34 +5VS_PCH_VCC5REF 1 2
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
VCCASW V5REF
(1uFx1)
2
2
AC27 10R2J-2-GP
VCCASW
1
C N20 3D3V_S5 C
VCCSUS3_3
PCI/GPIO/LPC
AC29 C2427
VCCASW SC1U10V2KX-1GP
N22
2
1D05V_VTT VCCSUS3_3
(1uFx1) AC31 VCCASW
(1uFx1)
1
(220uFx1) VCCSUS3_3 P20
L2402 0.08A+1.05VS_VCCA_A_DPL AD29 C2428
VCCASW SC1U6D3V2KX-GP
1 2 P22
2
IND-10UH-218-GP VCCSUS3_3
AD31
SC10U6D3V3MX-GP SC10U6D3V3MX-GP
VCCASW
1
68.10050.10Y C2443
2nd = 68.10090.10B C2409 W21 AA16 3D3V_S0
VCCASW VCC3_3
DY SC1U6D3V2KX-GP
2
W23 VCCASW VCC3_3 W16

(0.1uFx2)
1
(1uFx1) W24 VCCASW VCC3_3 T34
L2403 (220uFx1)
0.08A+1.05VS_VCCA_B_DPL C2430 C2431
1 2 W26 SCD1U10V2KX-5GP SCD1U10V2KX-5GP
2
IND-10UH-218-GP VCCASW
1
68.10050.10Y C2444 W29 3D3V_S0

C2410 VCCASW
2nd = 68.10090.10B
DY SC1U6D3V2KX-GP W31 AJ2
2
VCCASW VCC3_3
(0.1uFx1)
1
W33 VCCASW
AF13 C2429
VCCIO SCD1U10V2KX-5GP
2
+VCCRTCEXT N16 DCPRTC 1D05V_VTT
0.16A (Totally current of VCCVRM VCCIO AH13
1
C2411 (0.1uFx1) 1D5V_S0 Y49 AH14

SCD1U10V2KX-5GP VCCVRM VCCIO
(1uFx1)
2
1
B B
AF14 C2432
+1.05VS_VCCA_A_DPL VCCIO SC1U6D3V2KX-GP
BD47
SATA
2
VCCADPLLA 1D05V_VTT
VCCAPLLSATA AK1
+1.05VS_VCCA_B_DPL BF47 R2411
VCCADPLLB +V1.05S_VCCAPLL_SATA3 1 2
AF11 1D5V_S0 C2434 DY (10uFx1)
VCCVRM
1
1D05V_VTT 1D05V_VTT +VCCDIFFCLKN +VCCDIFFCLK AF17 0R3J-0-U-GP
VCCIO
0.055A (1uFx1) AF33
DY
SC10U6D3V5KX-1GP
R2404 1 +VCCDIFFCLK VCCDIFFCLKN
2 1 R2406 2 AF34 AC16
2
0R0603-PAD VCCDIFFCLKN VCCIO
(1uFx1) AG34 VCCDIFFCLKN
1
0R0402-PAD 1D05V_VTT
C2412 C2414
0.095A VCCIO AC17
SC1U6D3V2KX-GP SC1U6D3V2KX-GP +V1.05S_SSCVCC AG33 AD17

2
SCD1U10V2KX-5GP(1uFx1) VCCSSC VCCIO

(1uFx1)
1
C2415
1D05V_VTT (0.1uFx1) 2 1 +VCCSST V16 C2435
DCPSST 1D05V_VTT SC1U6D3V2KX-GP
2
2 R2405 1 +V1.05S_SSCVCC
T17 DCPSUS VCCASW T21
1
0R0402-PAD (1uFx1) TPAD14-GP TP2406 1 DCPSUS V19 DCPSUS

MISC
C2413 +3VS_+1.5VS_HDA_IO
SC1U6D3V2KX-GP 1D05V_VTT V21
2
VCCASW
0.001A 1 R2409 2
CPU
3D3V_S5
BJ8 0R0603-PAD
SCD1U10V2KX-5GP
V_PROC_IO +3VS_+1.5VS_HDA_IO
C2418
(0.1uFx2) VCCASW T19

1
20101224 A00: (4.7uFx1_0603)

0402 0R pad: R2404,R2405. C2417
A SC4D7U6D3V3KX-GP 0.01A <Core Design> A
2
RTC
A22 P32
HDA
RTC_AUX_S5 VCCRTC VCCSUSHDA

(0.1uFx1)
1
6uA COUGAR-GP-U2-NF C2433 Wistron Corporation
SCD1U10V2KX-5GP 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
2 Taipei Hsien 221, Taiwan, R.O.C.

C2421
C2422
(0.1uFx2)
1
(1uFx1)
Title
PCH 8/9(POWER2)
2

Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
SSID = PCH PCH1I 9 OF 10
AY4 VSS Cougar VSS H46

AY42 VSS VSS K18
AY46 VSS Point VSS K26
AY8 VSS VSS K39
B11 VSS VSS K46
B15 VSS VSS K7
B19 VSS VSS L18
B23 VSS VSS L2
B27 VSS VSS L20
D B31 VSS VSS L26 D
PCH1H 8 OF 10 B35 L28
VSS VSS
H5 VSS B39 VSS VSS L36
Cougar B7 VSS VSS L48
AA17 VSS VSS AK38 F45 VSS VSS M12
AA2 VSS Point VSS AK4 BB12 VSS VSS P16
AA3 VSS VSS AK42 BB16 VSS VSS M18
AB11 VSS VSS AL16 BB24 VSS VSS M30
AB7 VSS VSS AL26 BC14 VSS VSS M46
AC19 VSS VSS AL27 BC18 VSS VSS M8
AC2 VSS VSS AL31 BC2 VSS VSS N18
AC21 VSS VSS AL33 BC22 VSS VSS P30
AC24 VSS VSS AL34 BC26 VSS VSS N47
AC33 VSS VSS AL48 BC32 VSS VSS P11
AC34 VSS VSS AM11 BC34 VSS VSS P18
AC48 VSS VSS AM14 BC36 VSS VSS T33
AD10 VSS VSS AM36 BC40 VSS VSS P40
AD13 VSS VSS AM45 BD46 VSS VSS P7
AD19 VSS VSS AM46 BD5 VSS VSS R2
AD24 VSS VSS AM7 BE22 VSS VSS R48
C AD26 AN2 BE26 T12 C
VSS VSS VSS VSS
AD27 VSS VSS AN29 BE40 VSS VSS T31
AD33 VSS VSS AN3 BF10 VSS VSS T37
AD34 VSS VSS AN31 BF12 VSS VSS T4
AD36 VSS VSS AP12 BF16 VSS VSS W34
AD37 VSS VSS AP19 BF20 VSS VSS T46
AD4 VSS VSS AP32 BF26 VSS VSS V11
AD42 VSS VSS AP4 BD3 VSS VSS V26
AD8 VSS VSS AR2 BF8 VSS VSS V36
AE2 VSS VSS AR48 BG17 VSS VSS V39
AE3 VSS VSS AT11 BG21 VSS VSS V43
AF10 VSS VSS AT13 BG33 VSS VSS V7
AF12 VSS VSS AT18 BG44 VSS VSS W17
AD14 VSS VSS AT22 BG8 VSS VSS W19
AD16 VSS VSS AT26 BH11 VSS VSS W2
AF16 VSS VSS AT28 BH15 VSS VSS W27
AF19 VSS VSS AT30 BH17 VSS VSS W48
AF24 VSS VSS AT32 BH19 VSS VSS Y12
AF26 VSS VSS AT34 H10 VSS VSS Y38
B B
AF4 VSS VSS AU24 BH39 VSS VSS BG29
AF42 VSS VSS AU30 BH43 VSS VSS N24
AF46 VSS VSS AV16 BH7 VSS VSS AJ3
AF5 VSS VSS AV20 D3 VSS VSS AD47
AF7 VSS VSS AV24 D12 VSS VSS B43
AF8 VSS VSS AV30 D16 VSS VSS BE10
AG19 VSS VSS AV38 D18 VSS VSS BG41
AG2 VSS VSS AV4 D22 VSS VSS G14
AG31 VSS VSS AV43 D24 VSS VSS H16
AG48 VSS VSS AV8 D26 VSS VSS T36
AH11 VSS VSS AW14 D30 VSS VSS BG22
AH3 VSS VSS AW18 D32 VSS VSS BG24
AH36 VSS VSS AW2 D34 VSS VSS C22
AH39 VSS VSS AW22 D38 VSS VSS AP13
AH40 VSS VSS AW26 D42 VSS VSS M14
AH42 VSS VSS AW28 D8 VSS VSS AP3
AH46 VSS VSS AW32 E18 VSS VSS AP1
AH7 VSS VSS AW34 E26 VSS VSS BE16
AJ19 VSS VSS AW36 G18 VSS VSS BC16
AJ21 VSS VSS AW40 G20 VSS VSS BG28
AJ24 VSS VSS AW48 G26 VSS VSS BJ28
AJ33 VSS VSS AV11 G28 VSS
AJ34 VSS VSS AY12 G36 VSS
AK12 VSS VSS AY22 G48 VSS
AK3 VSS VSS AY28 H12 VSS
H18 VSS
COUGAR-GP-U2-NF H22 VSS
H24 VSS
A H26 VSS <Core Design> A
H30 VSS
H32 VSS
H34
F3
VSS
VSS
Wistron Corporation
COUGAR-GP-U2-NF Title
PCH 9/9(VSS)
Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
3D3V_AUX_KBC
3D3V_AUX_KBC MODEL_ID_DET(GPIO07) PULL-LOW RESISTOR PULL-HIGH RESISTOR VOLTAGE
SSID = KBC 20101224 A00 Modify:
Change R2724 to 47K from 33K.
PCB VERSION A/D(PIN98) PULL-LOW RESISTOR PULL-HIGH RESISTOR VOLTAGE
DQ15_UMA 100.0K 10.0K(64.10025.6DL) 3.0V
1
X00 100.0K 10.0K 3.0V
SCD1U10V2KX-5GP
SC2D2U10V3KX-1GP
1
R2710 DQ15_ATI 100.0K 20.0K(64.20025.6DL) 2.75V
3D3V_AUX_KBC R2724 X01 100.0K 20.0K 2.75V 174KR2F-GP
3D3V_S0 47KR2F-GP DQ15_NVIDIA 100.0K 33.0K 2.48V
1 R2702 2 VBAT X02 100.0K 33.0K 2.48V
2
C2709
C2710
0R0603-PAD DN15_UMA 100.0K 47.0K(64.47025.6DL) 2.24V
2
2
1
A00 100.0K 47.0K 2.24V
R2771 PCB_VER_AD MODEL_ID_DET DN15_ATI 100.0K 64.9K(64.64925.6DL) 2.0V
1
2D2R3-1-U-GP Reserved 100.0K 64.9K 2.0V
1
C2702 C2703 Reserved 100.0K 76.8K 1.87V
DY
2
3D3V_AUX_KBC_VCC SCD1U10V2KX-5GP SC2D2U10V3KX-1GP R2726 Reserved 100.0K 76.8 1.87V R2739
1
2
100KR2F-L1-GP C2718 100KR2F-L1-GP Reserved 100.0K 100.0K 1.65V
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C2704
C2705
C2706
C2707
C2708
C2717 Reserved 100.0K 100.0K 1.65V
SCD1U10V2KX-5GP
1
1
1
EC_AGND SCD1U10V2KX-5GP DN13_UMA 100.0K 143.0K 1.358V
2
C2701 Reserved 100.0K 143.0K 1.358V
DY DN13_ATI 100.0K 174.0K 1.204V
SC2D2U10V3KX-1GP
D D
2
115
102
C2711 Reserved 100.0K 174.0K 1.204V
19
46
76
88
DY
4
U2701A 1 OF 2 1 2 EC_AGND EC_AGND DQ15_Ventura 100.0K 215.0K 1.048V
SC220P50V2KX-3GP Reserved 100.0K 215.0K 1.048V
VCC
VCC
VCC
VCC
VCC
AVCC
VDD
(40) AD_IA
PLT_RST#_EC R2735 1
C2714 1 2 SCD1U10V2KX-5GP
104
VREF LRESET#
7
2
2
0R0402-PAD
PLT_RST# (5,18,65,71,82,83) NOTES:
EC_AGND LCLK CLK_PCI_KBC (18)
PCB_VER_AD
97
98
GPIO90/AD0 LFRAME#
3
1 LPC_AD3
LPC_FRAME# (21,65,71) The NPCE795P GPIO/PWM outputs that are connected
GPIO91/AD1 LAD3
(38) PSID_EC 99
100
GPIO92/AD2 LAD2
128
127
LPC_AD2
LPC_AD1
LPC_AD[0..3] (21,65,71) to LEDs have high drive buffers (20mA) and can be Notes:
(28) CPU_THRM GPIO93/AD3 LAD1
LAD0
126 LPC_AD0 connected directly to the LEDs.
(28)
(49)
FAN1_DAC
LCD_TST
101
105
GPIO94/DA0 SERIRQ
125
8
INT_SERIRQ (21)
PM_CLKRUN# (19)
The total SPI interface signal between EC and PCH
MEDIA_BTN2# GPIO95/DA1 GPIO11/CLKRUN# PANEL_BLEN
106 9
GPIO96/DA2 GPIO65/SMI#
ECSCI#/GPIO54
29 ECSCI#_KBC can’t not exceed 6500mil. The mismatch between
124 HDMI_IN# (51)
GPIO10/LPCPD#
20101228 A00:
VGA_THRM change to USB_PWR_EN.
(19) SUS_PWR_ACK
(57) USBCHARGER_CB0
79
95
GPIO2 GPIO67/PWUREQ#
123
121
ECSWI#_KBC
H_A20GATE (22)
SPI signal must be within 500mil
20101229 A00: USB3_PWR_ON GPIO3/AD6 GPIO85/GA20 U2701B 2 OF 2
(62,82) USB3_PWR_ON 96 122 H_RCIN# (22) KCOL[0..16] (69)
Rename USB_PWR_EN to USB3_PWR_ON. GPIO4/AD5 KBRST#/GPIO86
(28) SYS_THRM 108
PSL_IN2 GPIO5/AD4 KCOL0
93 (28) FAN_TACH1 31 53
MODEL_ID_DET PSL_IN2#_GPIO6 GPIO56/TA1 KBSOUT0/JENK# KCOL1
94 27 BLON_OUT (49) (19) PM_PWRBTN# 117 52
GPIO7/AD7 GPIO52/PSDAT3/RDY# AD_IA_HW2 GPIO20/TA2 KBSOUT1/TCK KCOL2
(68) BATT_WHITE_LED# 114 25 AD_IA_HW2 (40) (82) PCIE_WAKE# 63 51
ECSMI#_KBC GPIO16 GPIO50/PSCLK3/TDO GPIO14/TB1 KBSOUT2/TMS KCOL3
6 11 PCH_WAKE# (19) (19,36,37,46,47) PM_SLP_S3# 64 50
GPIO24 GPIO27/PSDAT2 MEDIA_BTN1# GPIO01/TB2 KBSOUT3/TDI KCOL4
(69) CAP_LED 109 10 49
GPIO30 GPIO26/PSCLK2 KBSOUT4/JEN0# KCOL5
(36) S5_ENABLE 14 71 TPDATA (69) (68) CHG_AMBER_LED# 32 48
GPIO34/CIRRXL GPIO35/PSDAT1 GPIO15/A_PWM KBSOUT5/TDO KCOL6
(82) MEDIA_BTN3# 15
80
GPIO36 GPIO37/PSCLK1
72 TPCLK <------ TP
(69) (29) KBC_BEEP 118
62
GPIO21/B_PWM KBSOUT6/RDY#
47
43 KCOL7
(39) BAT_IN# GPIO41 (82) MEDIA_LED1# GPIO13/C_PWM KBSOUT7
17 65 42 KCOL8
(70) LID_CLOSE# GPIO42/TCK (69) KB_BL_CTRL GPIO32/D_PWM KBSOUT8 KCOL9
(19) RSMRST#_KBC 20
21
GPIO43/TMS GPIO17/SCL1
70
69
BAT_SCL (39,40) <------ BATTERY / CHARGER (40) AD_IA_HW 81
66
GPIO66/G_PWM KBSOUT9/SDP_VIS#
41
40 KCOL10
(19,46) PM_SLP_S4# GPIO44/TDI GPIO22/SDA1 BAT_SDA (39,40) (82) MEDIA_LED3# GPIO33/H_PWM KBSOUT10/P80_CLK KCOL11
(21) ME_UNLOCK 23
26
GPIO46/CIRRXM/TRST# GPIO73/SCL2
67
68
SML1_CLK (20,85) <------PCH / eDP (82) MEDIA_LED2# 22
16
GPIO45/E_PWM KBSOUT11/P80_DAT
39
38 KCOL12
(38) RCID GPIO51 GPIO74/SDA2 SML1_DATA (20,85) (68) PWRLED# GPIO40/F_PWM KBSOUT12/GPIO64
PSL_IN1 73 119 37 KCOL13
PSL_IN1_GPIO70 GPIO23/SCL3 PM_LAN_ENABLE (82) KBSOUT13/GPIO63
PSL_OUT 74 120 EC_ENABLE#_1 36 KCOL14
EC_GPIO72 PSL_OUT_GPIO71 GPIO31/SDA3 PROCHOT_EC ECRST# KBSOUT14/GPIO62 KCOL15
75 24 85 35
VBKUP GPIO47/SCL4 VCC_POR# KBSOUT15/GPIO61/XOR_OUT KCOL16
(65) WIFI_RF_EN 82 28 34
GPIO75 GPIO53/SDA4 LCD_TST_EN (49) GPIO60/KBSOUT16 USB_DET#
(63,65) BLUETOOTH_EN 83 33
GPO76/SHBM 20101224 A00: GPIO57/KBSOUT17
(19,36) S0_PWR_GOOD 84 (65) E51_RxD 113 KROW[0..7] (69)
GPIO77 0402 0R pad: R2737,R2735. GPIO87/CIRRXM/SIN_CR KROW0
C
(68) TP_LOCK_LED# 91 (65) E51_TxD 111 54 C
GPIO81 GPIO83/SOUT_CR/TRIST# KBSIN0 KROW1
(61) USB_PWR_EN# 110 55
GPO82/IOX_LDSH/TEST# EC_SPI_CS#_C KBSIN1 KROW2
(19) AC_PRESENT 112 90 2 R2736 1 33R2J-2-GP SPI_CS0#_R (21,60) (29) AMP_MUTE# 30 56
GPIO84/IOX_SCLK/XORTR# F_CS0# EC_SPI_CLK_C GPIO55/CLKOUT/IOX_DIN_DIO KBSIN2 KROW3
(36,42) IMVP_PWRGD 107 92 2 R2719 1 33R2J-2-GP SPI_CLK_R (21,60) (19) PCH_SUSCLK_KBC 77 57
GPIO97 F_SCK EC_SPI_DI_C GPIO00/EXTCLK KBSIN3 KROW4
86 2 R2737 1 0R0402-PAD SPI_SO_R (21,60) 58
F_SDI/F_SDIO1 EC_SPI_DO_C KBSIN4 KROW5
87 2 R2722 1 33R2J-2-GP SPI_SI_R (21,60) 59
USB_PWR_EN# KBC_VCORF F_SDIO/F_SDIO0 KBSIN5
AFTP2701 1 44 (5,22) H_PECI R2721 1 2 43R2J-GP PECI13 60 KROW6
AFTP2702 AC_PRESENT VCORF EC_VTT12 PECI KBSIN6 KROW7
1 1D05V_VTT 1 2 61 D2705
1
AFTP2703 E51_TxD R2720 0R0402-PAD VTT KBSIN7

1 NOTE: (21,22) EC_SMI# 1
1
AGND
C2712
GND
GND
GND
GND
GND
GND
SC1U10V3ZY-6GP
Locate resistors R2719 and R2722 close
C2716 NPCE795PA0DX-GP-U DY 3 ECSMI#_KBC
2
to the NPCE791L. Need very close to EC
SCD1U16V2KX-3GP
2
NPCE795PA0DX-GP-U 2
18
45
78
89
116
5
103
EC_SPI_DI_C
1
BAS16-6-GP
NOTE: 83.00016.K11
EC_AGND
Connect GND and AGND planes via either R2773

100KR2J-1-GP 2ND = 83.00016.F11
ROSA Multi GPIO setting 0R resistor or one point layout connection.
2
1 2 3D3V_AUX_S5
R2711 0R0402-PAD 20101224 A00:
0402 0R pad: R2760.
1
ECRST#
EC_AGND R2705 EC_SMI# 2 R2760 1 ECSMI#_KBC
C2719 SCD1U10V2KX-5GP 10KR2J-3-GP 0R0402-PAD
CPU_THRM
C2720
2
DY1
SCD1U10V2KX-5GP D2701
1
USB3_PWR_ON 2 1 1
DY (20) EC_SWI# EC_GPIO47 High Active
E
C2721 SCD1U10V2KX-5GP C2715
SYS_THRM 2
DY ECSWI#_KBC MMBT3906-4-GP
DY1 3 (28,36,85) PURE_HW_SHUTDOWN# B
2
Q2702
BAS16-6-GP
DY
SC1U6D3V2KX-GP
2 PROCHOT_EC G Q2701
C
EC_AGND MEDIA BUTTON CONTROL
83.00016.K11 D H_PROCHOT#_EC
1 2 84.T3906.A11
H_PROCHOT# (5,40,42)
1
2ND = 83.00016.F11 R2733 0R0402-PAD 2nd = 84.03906.F11

(17) L_BKLT_EN 1 2 PANEL_BLEN R2732 S
R2761 0R0402-PAD D2704
100KR2J-1-GP
(22) EC_SCI# 1
2N7002K-2-GP
DY
2
B 3 ECSCI#_KBC 84.2N702.J31 B
BAS16-6-GP 3D3V_AUX_KBC
2
2ND = 84.2N702.031
USB_DET# 1 2
83.00016.K11 R2772 100KR2J-1-GP
2ND = 83.00016.F11 MEDIA_BTN1# 1 2
R2770 100KR2J-1-GP
20101224 A00: MEDIA_BTN2# 1 2
0402 0R pad: R2758,R2759. PSL SOLUTION 10mW SOLUTION EC GPIO standard PH/PL MEDIA_BTN3#
R2774
1 2
100KR2J-1-GP
(20) EC_SWI# 2 R2758 1ECSWI#_KBC R2775 100KR2J-1-GP

0R0402-PAD PCIE_WAKE# 1 2
PSL_IN2 3D3V_AUX_KBC R2776 100KR2J-1-GP
(22) EC_SCI# 2 R2759 1ECSCI#_KBC
0R0402-PAD
RTC_AUX_S5
R2756
3D3V_AUX_KBC VBACKUP BAT54CPT-GP
RN2701
1 2 EC_GPIO72 1 R2734 2 EC_GPIO72 1 MEDIA_BTN1#
0R0402-PAD 0R2J-2-GP BAT_SCL
BAT54CPT-GP
R2704 DY BAT_SDA
3
4
2
1 (82) INSTANT_ON#
INSTANT_ON# 3 83.R2003.E81
1 1 2 EC_GPIO72 2ND = 83.00054.Q81
330KR2J-L1-GP 2 KBC_ON#_R
3D3V_AUX_S5 SRN4K7J-8-GP
(68) KBC_PWRBTN# 3 83.R2003.E81
2ND = 83.00054.Q81 3D3V_AUX_S5 R2763 RN2703 D2706
2 AC_OK 1 R2768 2 PSL_IN1 AC_IN#_KBC 1 2 PSL_IN1 BAT_IN# 4 1
(40) AC_OK
1
C2722 0R0402-PAD AC_IN#_KBC 3 2

1 2
DY BAT54CPT-GP
D2702
KBC_ON#
RN2706 SCD1U10V2KX-5GP
0R2J-2-GP
DY R2769
100KR2J-1-GP
PSL_IN1 SRN100KJ-6-GP
1 USB_DET#
S
4 1
2
KBC_ON#_R 3 2KBC_ON#_GATE G Q2703 RN2705 USBDET_CON# 3 83.R2003.E81

(57) USBDET_CON#
G
DMP2130L-7-GP S5_ENABLE 8 1 2ND = 83.00054.Q81
SRN10KJ-5-GP ECRST# 7 2 2 KBC_ON#_R
D2703 D 2ND = 84.03413.A31
6 3
Q2704
PSL_OUT
1
2 EC_ENABLE#_1 5 4 D2707
D
C2713 DY 84.02130.031 3D3V_AUX_KBC G

10mW 3 AC_IN# (40) SCD1U10V2KX-5GP SRN10KJ-6-GP
2
D KBC_ON#
2ND = 83.00054.Q81 1 DY
83.R2003.E81 3D3V_AUX_KBC 1 R2767 2 KBC_ON#_R EC_ENABLE#_1 S
10mW BAT54CPT-GP
0R2J-2-GP 3D3V_S0 1MEDIA_BTN2#

BAT54CPT-GP Q2705
PSL_OUT 2N7002K-2-GP FAN_TACH1 DATA_RECOVERY# 3
A
2N7002K-2-GP G (28) FAN_TACH1 1 2 (82) DATA_RECOVERY# 83.R2003.E81 A
AC_IN#_KBC 84.2N702.J31 R2712 10KR2J-3-GP 2ND = 83.00054.Q81
G D 2 KBC_ON#_R
DY 2ND = 84.2N702.031
D S5_ENABLE S KBC_ON# 1 R2766 2 KBC_ON#_R
0R0402-PAD E51_RxD 1
DY 2
D2708
S R2708 10KR2J-3-GP
2N7002K-2-GP 20101228 A00: <Core Design>
Q2706 84.2N702.J31 Change R2756,R2763,R2766 to 0R short pad.
84.2N702.J31 2ND = 84.2N702.031
2ND = 84.2N702.031 Wistron Corporation
BLUETOOTH_EN 1
DY 2
R2709 10KR2J-3-GP
NOTES: Title
Please make sure there's no pull-down resistor on USB_PWR_EN#,AC_PRESENT,E51_TXD.
Size
KBC Nuvoton NPCE785P
Document Number Rev
A2 Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
SSID = Thermal Thermal sensor P2800 Fan controller

U2802
R2802 0R2J-2-GP
1 DY 2 FON# 1 8
FON# GND 5V_S0
5V_S0 2 VIN GND 7
3D3V_DAC_S0 FAN_VCC 3 6
VO GND
(27) FAN1_DAC 4 VSET GND 5
*Layout* 10 mil
1
G991P11U-GP
D 3D3V_DAC_S0 R2803
107KR2F-GP
For linear FAN 74.00991.031 D
P2800A1
1
2nd = 74.02793.A31 C2803 C2804
1
C2802
87.1 Degree
SC4D7U6D3V3KX-GP
2
SCD1U10V2KX-5GP
2
2
ADJ 3rd = 74.05606.A71
SCD1U10V2KX-5GP
1
R2804 C2805
SCD1U10V2KX-5GP
226KR2F-GP
P2800A1
P2800A1
2
2
Layout notice :
Both DXN and DXP routing 10 mil
20101224 A00 Modify:
trace width and 10 mil spacing. If stuff P2800EA1 then must stuff R2803,R2804
C2805 but if stuff P28003B0 should be un-stuff. FAN1
P2800_DXP 5
P2800EA1-GP 1 2 FAN_TACH1_C 3
(27) FAN_TACH1
1
2ND = 84.03904.P11 R2807 0R0402-PAD 2

3
84.03904.L06 C2806 1 5 VCC TDR 4 SYS_THRM (27) *Layout* 15 mil

Q2801 SC470P50V3JN-2GP C2807 FAN_VCC
DY 1 6 3 CPU_THRM (27) 1
2
PMBS3904-1-GP SC2200P50V2KX-2GP DXP TDL

7 2 4
2
THERM_SYS_SHDN#_OTZ DXN GND ADJ

8 1
2
OTZ ADJ
2
P2800_DXN
R2808 D2802 ACES-CON3-11-GP
1
NTC-100K-8-GP 2.System Sensor, Put on palm rest U2801 C2808 C2809 C2810 20.F0772.003
C 1.H/W T8 Shutdown C
SC2200P50V2KX-2GP
SC4D7U6D3V3KX-GP
DY CH551H-30PT-GP DY
SCD1U16V2KX-3GP
2
2
74.02800.A71 83.R5003.C8F 2nd = 20.F1841.003
2ND = 83.R5003.H8H
AFTP2801 1FAN_TACH1_C 3rd = 83.5R003.08F
AFTP2802 1FAN_VCC
R2805 3D3V_S0
THERM_SYS_SHDN#_OTZ 1 2
1
0R2J-2-GP
R2809
100KR2J-1-GP
Q2802
2
S THERM_SYS_SHDN#
(27,36,85) PURE_HW _SHUTDOW N# D
G 3D3V_S0
1
C2811
2N7002K-2-GP
DY
SCD1U10V2KX-5GP
84.2N702.J31
2
B 2ND = 84.2N702.031 B
20101228 A00 Modify:

Un-stuff U2805 G709T1UF related circuit
and R2812 then stuff R2805 at X-Build.
RSET = 0.0012T 2 — 0.9308T + 96.147

3D3V_DAC_S0
T=87 ; RSET=24.25ohm
R2806
24K3R2F-1-GP U2805 R2801
U2805_1 U2805_5
DY
1 DY 2 1 SET VCC 5 2 1
1
2 150R2F-1-GP
THERM_SYS_SHDN# 1 U2805_3 GND
R2812
2 3 OUT# DY HYST 4 DY C2817
DY 0R2J-2-GP SCD1U10V2KX-5GP
2
G709T1UF-GP R2810 3D3V_DAC_S0
U2805_4 2 DY 1
R2811 0R2J-2-GP
74.00709.A7F 2 DY 1
0R2J-2-GP
Hysterisis is 10°C for HYST = VCC, 2°C for HYST = GND.
A <Core Design> A
Wistron Corporation
Title
THERMAL P2800 / Fan control

A3
Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
+AVDD 5V_S0 +PVDD 5V_S0

SSID = AUDIO AUD_SPK_L-
AUD_SPK_L+ AUD_SPK_L- (58)
AUD_SPK_L+ (58)
1 R2903 2
AMP_MUTE# +PVDD +AVDD 1 R2902 2 0R0603-PAD
(27) AMP_MUTE# 0R0603-PAD
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC10U6D3V5MX-3GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
AUD_VREG
C2905
C2906
C2908
C2909
C2910
2
1
1 R2904 2
0R0603-PAD
2
Close to codec
AUD_DVDDCORE
41
40
39
38
37
36
35
34
33
32
31
D D
U2901
PORTD_-L
PORTD_+L
AVDD2
THERMAL_PAD
EAPD
PVDD
PORTD_+R
PORTD_-R
PVDD
PVSS
VREG/+2_5V
C2901
SC10U6D3V5MX-3GP
2
PUMP_CAPP
2
C2914
1 30 SC2D2U10V3KX-1GP
1
AUD_DMIC_CLK DVDD_LV CAP+ PUMP_CAPN
(49,97) AUD_DMIC_CLK 2 DMIC_CLK/GPIO_1 CAP- 29
3D3V_S0 AUD_DMIC_IN0 3 28 AUD_V_B
(49,97) AUD_DMIC_IN0 HDA_CODEC_SDOUT DMIC_0/GPIO_2 V-
(21) HDA_CODEC_SDOUT 4 SDATA_OUT AVSS2 27
HDA_CODEC_BITCLK 5 26 AUD_HP1_JACK_R R2906 1 2 60D4R2F-GP
(21) HDA_CODEC_BITCLK BITCLK PORTB_R AUD_HP1_JACK_R2 (58)
Close to codec (21) HDA_SDIN0 1 R2901 2HDA_CODEC_SDIN0 6 SDATA_IN PORTB_L 25 AUD_HP1_JACK_L R2905 1 2 60D4R2F-GP AUD_HP1_JACK_L2 (58)
33R2J-2-GP 7 24
HDA_CODEC_SYNC DVDD AVSS2 AUD_EXT_MIC_R C2922
(21) HDA_CODEC_SYNC 8 SYNC PORTA_R 23 2 1 SC1U10V3KX-3GP MIC_IN_R (58)
HDA_CODEC_RST# 9 92HD87B1A5NDGXTBX8-GP 22 AUD_EXT_MIC_L C2921 2 1 SC1U10V3KX-3GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
(21) HDA_CODEC_RST# RESET# PORTA_L MIC_IN_L (58)

1
2
C2903
C2904
C2902
AUD_PC_BEEP 10 71.92H87.A03 21 +AVDD

PCBEEP AVDD1
VREFOUT_C
VREFOUT_A
Put C2921 and C2922 close to codec
2
PORTC_R
VREFFILT
PORTF_R
SENSE_A
SENSE_B
PORTC_L
PORTF_L
CAP2
11
12
13
14
15
16
17
18
19
20
C C
2010/06/30 Change to 92HD87 (71.92H87.A03)
AUD_VREFOUT_B
AUD_SENSE_A
AUD_SENSE_B
AUD_PC_BEEP
AUD_VREFFLT
AUD_CAP2
3D3V_S0
AUD_CAP2
AUD_VREFFLT
1
R2908 AUD_V_B
10KR2J-3-GP
AUD_VREG
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC4D7U6D3V3KX-GP
2
SC1U6D3V2KX-GP
C2917
C2918
C2915
C2916
AMP_MUTE#
1
AUD_VREFOUT_B
R2907 120KR2J-L-GP From PCH
2
HDA_CODEC_BITCLK_1 1 HDA_CODEC_BITCLK R2909
DY 2 AUD_PC_BEEP C2912 2 1 SCD1U10V2KX-5GP SB_SPKR_R 1 2 HDA_SPKR (21)
47R2J-2-GP
C2913 2 1 SCD1U10V2KX-5GP KBC_BEEP_R 1 2
AUD_PC_BEEP KBC_BEEP (27)
1
C2923
SC1U10V2KX-1GP DY C2907
SC4D7P50V2CN-1GP
Trace width>15 mils G2901
R2910
470KR2J-2-GP
From EC
Close to codec
2
DUMMY-C2
B B
1
AUD_VREFOUT_B
2
1
RN2901
$]DOLD,)(0,
SRN4K7J-8-GP
3
4
HDA_CODEC_SDOUT
1
R2912
47R2J-2-GP
DY +AVDD +AVDD (58) MIC_IN_L
R2913 (58) MIC_IN_R
2
1 2 AUD_HP1_JD# (58)
1
1
PCH_AZ_CODEC_SDOUT1
R2915 20KR2F-L-GP R2916

2K49R2F-GP 2K49R2F-GP
2
A AUD_SENSE_A AUD_SENSE_B <Core Design> A

1
1
R2918
C2919 20KR2F-L-GP Wistron Corporation
SC1000P50V3JN-GP-U R2919 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
2
2 1 Taipei Hsien 221, Taiwan, R.O.C.

2
EXT_MIC_JD# (58)
1
C2920 39K2R2F-L-GP Title

DY SCD1U10V2KX-5GP Audio Codec 92HD87B1
2
Close to Pin13 Size Document Number Rev

Close to Pin14 A3 A00
Nirvana 13
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
SSID = SDIO
D
48MHz clock input trace of characteristic impedance (Zo) must be 50 ±15%. 3D3V_CARD_S0
D
3D3V_CARD_S0
(20,97) CLK_PCH_48M
1
C3206 C3207
SCD1U10V2KX-4GP SC4D7U6D3V5KX-3GP
2
XD_D7 XD_D7 (74)
SP14 SP14 (74)
SP13 SP13 (74)
SP12 SP12 (74)
SP11 SP11 (74) Close to chip
C3201
1 RREF U3201
DY2
24
23
22
21
20
19
RTS5138-GR-GP
3D3V_S0 SC100P50V2JN-3GP
XD_D7
SP14
SP13
SP12
SP11
CLK_IN
1 R3201 2
6K2R2F-GP 1 18 SP10 SP10 (74)
USB_PN5_R RREF SP10
MAX 0.4A 2 DM GPIO0 17
USB_PP5_R 3 16 SP9 SP9 (74)
DP SP9 SP8
4 3V3_IN SP8 15 SP8 (74)
3D3V_CARD_S0 5 14 SP7 SP7 (74)
V18 CARD_3V3 SP7 SP6
6 V18 SP6 13 SP6 (74)
2
XD_CD#
C3203 DY C3204 1 C3202
SP1
SP2
SP3
SP4
SP5
SCD1U10V2KX-4GP SC4D7U6D3V3KX-GP SC1U10V2KX-1GP 25
1
C GND C
2
71.05138.003
7
8
9
10
11
12
SP5 SP5 (74)
SP4 SP4 (74)
SP3 SP3 (74)
SP2 SP2 (74)
SP1 SP1 (74)
XD_CD# XD_CD# (74)
The maximum range of the PMOS output current

1. xD-Picture Card: 250mA
2. SD/MMC Card: 250mA
B B
3. MS/MSPRO/Duo-HG: 250mA The pin2 / pin3 (DM/DP) of RTS5138 chip trace layout
with differential characteristic impedance (Zdiff) is 90ȍ± 10%
POWER TRACE
1.RTS5138: pin 4 (3V3_IN) trace fixed width is 30 mils (minimum). (18) USB_PP5 1 R3211 2 USB_PP5_R
2.RTS5138: pin 5 (CARD_3V3) trace fixed width is 30 mils (minimum). 0R0402-PAD
3.RTS5138: pin 6 (V18) trace fixed width is 12 mils (minimum).

Keep the trace routing lengths as short as possible.
4.RTS5138: pin 1(RREF) trace fixed width is 12 mils (minimum).
5.RTS5138: pin 1(RREF) trace must far away 48MHz clock trace.
6.De-coupling and Bulk capacitor should place near to RT5138 chip and Combo Socket.
7.It is recommended that use of ferrites bead on power trace.
8.Via size: Pad>=32 mils, Finished hole>=16 mils. (18) USB_PN5 1 R3210 2 USB_PN5_R
0R0402-PAD
20101227 A00:
A
Change R3210,R3211 to 0R 0402 pad. <Core Design> A
20100104 A00:
Remove TR3201.
Wistron Corporation
Title
Card Reader RTS5138
A3
Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3 Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
20101224 A00: R3622

0402 0R pad: R3614. 2 1
1D05V_VTT H_THERMTRIP# (5,22)
56R2J-4-GP
2 R3614 1 SYS_PWROK
(27,42) IMVP_PWRGD
0R0402-PAD
SSID = Reset.Suspend
E
1
C3612 DY 1 R3601 2 H_PWRGD_R B DY Q3601
SCD01U50V2KX-1GP (5,22) H_CPUPWRGD 1KR2J-1-GP
DY
1
CHT2222APT-GP
C
Q3603 C3602 DY
PS_S3CNTRL G SCD1U10V2KX-5GP
2
S
D
Power Sequence 2ND = 83.00016.F11
2N7002K-2-GP 83.00016.K11
BAS16-6-GP
D 2 D
2
3 PURE_HW_SHUTDOWN# (27,28,85)
(19,27) S0_PWR_GOOD 3
(41) 3V_5V_EN 1
1 SYS_PWROK (19) D3601
200KR2J-L1-GP
1
D3602 1 2 S5_ENABLE (27)
R3602
BAS16-6-GP R3603 1KR2J-1-GP
83.00016.K11 DY
2ND = 83.00016.F11
2
SSID = Reset.Suspend
Run Power 15V_S5

AO4468 MAX 9A
Rds(on) = 18.5mOhm +5V_RUN
2nd = 84.08882.037
5V_S5 84.04468.037 5V_S0
2
AO4468-GP
+5V_RUN Comsumption
R3604 5 4
100KR2J-1-GP 6
D G
3
Peak current 7.73A
D S
7 D S 2
8 1
1
D S
1
U3601
1 R3605 2 5V_RUN_ENABLE C3603
3D3V_AUX_S5 10KR2J-3-GP SC10U10V5ZY-1GP
2
1
C C3608 C
SCD01U50V2KX-1GP
PS_S3CNTRL (37)
1 R3606 2 PS_S3CNTRL 2
100KR2J-1-GP
D G S
6
Rds(on) = 18.5mOhm
Q3602 AO4468 MAX 11.6A
2N7002KDW-GP
2nd = 84.08882.037
+3.3V_RUN
84.2N702.A3F 3D3V_S5 84.04468.037 3D3V_S0
1
2nd = 84.DM601.03F AO4468-GP

+3.3V_RUN Comsumption
S G D 5 D G 4
Peak current 8.14A
6 D S 3
7 D S 2
8 1
1
D S
(19,27,37,46,47) PM_SLP_S3# U3602 C3604
RUN_ENABLE 1 R3607 2 3.3V_RUN_ENABLE SC10U6D3V5KX-1GP
2
10KR2J-3-GP
1
C3605
SCD01U50V2KX-1GP
2
+1.5V_RUN_CPU Comsumption 1D5V_S0

B Peak current 10A 1D5V_S3 1D5V_S0 B
+1.5V_RUN for Mini-Card Comsumption

Peak current 1A TPCA8062-H-GP MAX 28A MAX Current ? mA
Rds(on) = 4.1~5.4m OHM Design Current ? mA
U3606
8 D S 1
7 D S 2
Total= 11.39A
6 D S 3
1
5 D G 4
C3609
TPCA8062-H-GP SC4D7U6D3V5KX-3GP
2
1 R3630 2 1.5V_RUN_ENABLE
10KR2J-3-GP
84.08062.037
1
C3610 2nd = 84.00460.037

SCD01U50V2KX-1GP
2
3rd = 84.00312.037
A A
<Core Design>
Wistron Corporation
Title

Power Plane Enable Rev
A2
Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
Close to DIMM
S3 Power Reduction Circuit SM_DRAMPWROK
0D75V_S0 1D5V_S0
1
Close to CPU
D S3 Power Reduction Circuit Processor VREF_DQ Implementation
R3707
R3703
22R2J-2-GP 2 DY
R3704
220R2J-L2-GP D
0R2J-2-GP
Q3702_D2
1 DY 2
Q3701_D
Q3708
S +V_SM_VREF_CNT (9)
D
D
2
M_VREF_DQ_DIMM0 1 2 +V_SM_VREF D Q3702
R3708 0R0402-PAD R3705 Q3701 2N7002K-2-GP
G 100KR2J-1-GP 2N7002K-2-GP
DY 84.2N702.J31
84.2N702.J31
2ND = 84.2N702.031
1
2N7002K-2-GP
2ND = 84.2N702.031
84.2N702.J31
S
2ND = 84.2N702.031
S
RUN_ENABLE PS_S3CNTRL
(36) PS_S3CNTRL
C
Close to CPU C
5 S3 Power Reduction 1D5V_S3
2N7002K-2-GP
1
(36) PS_S3CNTRL G
R3706
D 0D75V_EN 1KR2J-1-GP
1.05VTT_PW RGD (45,48)
S
2
R3709
Q3704
DY1 2
0R2J-2-GP
2ND = 84.2N702.031
1
84.2N702.J31 S3 Power Reduction Circuit
R3710 20101224 A00: 84.2N702.J31
2ND = 84.2N702.031 0402 0R pad: R3710. Q3703 SM_DRAMRST#
0R0402-PAD
(5) SM_DRAMRST# S
2
D SM_DRAMRST#_D
1 R3718 2 DDR3_DRAMRST# (14,15)
1KR2J-1-GP
1
(19,27,36,46,47) PM_SLP_S3# 1
R3716
DY 22R2J-2-GP
2 0D75V_EN (46) G
C3702
SC100P50V2JN-3GP
2
2N7002K-2-GP
1
C3705 DRAMRST_CNTRL_PCH (20)
DY SCD1U10V2KX-5GP
2
B B
C3703
2 1DRAMRST_CNTRL_PCH
Close to CPU SCD047U16V2KX-1-GP
3D3V_S0
3D3V_S0 1D5V_S0
1
R3713
CEKLT V1.0: PCH to 1K,CUP to 200R
1
200R2F-L-GP
R3702
U3701 200R2F-L-GP
DY
2
(5,19) PM_DRAM_PW RGD 1

5 R3719
2
0D75V_EN 2
4 VDDPW RGOOD_R 1 2 VDDPW RGOOD (5)
1
3
R3721
TC7SZ08FU-2-GP 39R2J-L-GP 910R2F-GP
73.7SZ08.EAH
DY
1
2ND = 73.01G08.L04
2
3rd = 73.7SZ08.DAH Q3707_D R3720

750R2F-GP
D
A DY Q3707
2N7002K-2-GP
<Core Design> A
R3717 84.2N702.J31
(5,19) PM_DRAM_PW RGD 1 DY 2 VDDPW RGOOD_R 2ND = 84.2N702.031 Wistron Corporation
0R2J-2-GP 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
G
Title
SM_DRAMPWROK must have a maximum of 15ns rise or fall time PS_S3CNTRL
over VDDQ * 0.55± 200mV and the edge must be monotonic S3 Power Reduction
A3
Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
5V_S5
84.03904.L06
D 2nd = 84.03904.P11 D
2
PR3801
3rd = 84.03904.T11
1
15KR2J-1-GP
PQ3802 PR3802 3D3V_S5
2
PMBS3904-1-GP 10KR2J-3-GP
1
PQ3802_1 1 3D3V_S5
2
2
1
3
1
PR3803 PSID_DISABLE#_R PD3803
100KR2J-1-GP BAV99-5-GP-U PR3806
2K2R2J-2-GP
83.00099.T11
G
1
PQ3801 2nd = 83.00099.K11
2
FDV301N-NL-GP
PR3804
PR3807 3rd = 83.BAV99.D11
PS_ID_R 1 2 PS_ID_1 D S PS_ID 1 2
D
(82) PS_ID_R PSID_EC (27)
0R0402-PAD 33R2J-2-GP
2N7002K-2-GP
1
(27) RCID G
PD3804 PR3808
DY
2
1 2 PR3812 DY D
B240A-13-GP
DY 100KR2J-1-GP
33R2J-2-GP S
DY
2
PQ3803
1
C 84.2N702.J31 C
2ND = 84.2N702.031
This cap should be used

only as last resort for
EMI suppression.
+DC_IN AD+
280mils or Copper Shape PU3801
1 S D 8
S D
PC3805
PC3802
PC3803
PC3806
2 7
SC1U25V5KX-1GP
SC10U25V6KX-1GP
SCD01U50V2KX-1GP
SCD01U50V2KX-1GP
SCD01U50V2KX-1GP
1
S D
PC3804
PR3810
Place close to BTB connector
240KR3-GP
3 6
K
1
4 G D 5
PD3801 PC3801
1SMB22AT3G-GP-U
DY SCD1U50V3KX-GP AO4407A-GP DY DY
2
83.22R03.03G
2
A
2ND = 83.P6SBM.AAG Id=-12A
PU3801_G
Qg=-25nC
Rdson=10~38mohm
2
B PR3811 B
47KR3J-L-GP
1
AFTP3801 1 PS_ID_R
AFTP3802 1 +DC_IN
AFTP3803 1 +DC_IN
<Core Design>
A A
Wistron Corporation
Title
DCIN Jack
A3
Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
400mils or Copper Shape Batt Connecter
1SMA18AT3G-GP
BT+
K
1
1
G3901
PD3902
2 1 C3902 C3901
(40) BATT_SENSE SCD1U50V3KX-GP SC2200P50V2KX-2GP DY BATT1
2
D GAP-CLOSE-PW R-3-GP 10 D
A
1
PN3901
(27) BAT_IN# 1 8 2
2 7 PBAT_SMBCLK1 3
3 6 PBAT_SMBDAT1 4
(27,40) BAT_SDA
4 5 PBAT_PRES1# 5
(27,40) BAT_SCL
6
SRN33J-7-GP AFTP3901 1 BAT_ALERT 7
8
9
20101224 A00: EC3901 EC3902 11
Rename PRN3901 to PN3901.
SC10P50V2JN-4GP
SC10P50V2JN-4GP
1
1
TCN-CON9-3-GP
DY DY
2
20.81327.009
AFTP3902 1 PBAT_PRES1#
AFTP3903 1 PBAT_SMBDAT1
AFTP3904 1 PBAT_SMBCLK1
C AFTP3905 1 BT+ C
For actual location, need to be swap all pin
Placement: Close to Batt Connector

BAT_SCL
BAT_IN#
BAT_SDA
B B
3
D3902 D3903 D3901

BAV99-5-GP-U BAV99-5-GP-U BAV99-5-GP-U
1
83.00099.T11
2nd = 83.00099.K11
83.00099.T11
2nd = 83.00099.K11
83.00099.T11
2nd = 83.00099.K11
3rd = 83.BAV99.D11 3rd = 83.BAV99.D11 3rd = 83.BAV99.D11
3D3V_AUX_KBC
A <Core Design> A
Wistron Corporation
Title
BATT CONN
A3
Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
SSID = Charger
AD+
280mils or Copper Shape AD+_TO_SYS DCBATOUT BT+
PU4002 400mils or Copper Shape
8 D S 1 PR4002 PU4003
7 D S 2 20101222 A00 1 2 1 S D 8
6 D S 3 Power/Brian: Change PR4047 to 174k ohm from 121k ohm. 2 S D 7
D01R2512F-4-GP
1
5 D G 4 Change PR4035 to 300k from 49.9k. AD+ 3 S D 6
Change PR4031 to 150k from 0 ohm. G D 5
PR4003
4
100KR2J-1-GP
PWR_CHG_REF
Id=-12A AO4407A-GP
1
AO4407A-GP
Qg=-25nC 84.04407.F37 PQ4003_D
1
PG4002 PG4003 Id=-12A
2nd = 84.P1403.B37 AD+_G_2 84.04407.F37
1
D Rdson=10~38mohm PR4035 GAP-CLOSE-PWR-3-GP GAP-CLOSE-PWR-3-GP
Qg=-25nC D
PG4001
PG4006
PG4004
PG4005
300KR2F-L-GP PR4006 2nd = 84.P1403.B37
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
470KR2J-2-GP Rdson=10~38mohm
D
2
1
10KR2J-3-GP
10KR2F-2-GP
1
AD+
PR4524_03
PR4004
PR4005
PQ4003 PR4047
1PR4533_02
2 1
DY
2
84.2N702.A3F 2N7002K-2-GP 174KR2F-GP
84.2N702.J31 PR4007
2nd = 84.DM601.03F 0R2J-2-GP
1
2
AD+_G_1
PQ4001 2ND = 84.2N702.031
1
DC_IN_D 3 4 PR4031 PR4008 PR4010
316KR3F-2-GP
S
150KR2F-L-GP 0R0402-PAD 0R0402-PAD20101222 A00
1
PWR_CHG_ACOK 2 5 Power/Brian: Change PR4032 to 0 ohm pad.

2PQ4003_G
160mils or Copper Shape
PR4009
2
(27) AD_IA_HW
PR4034
ICREF
1 6 (5,27,42) H_PROCHOT# 1 2
1 2 PR4032 PWR_DCBATOUT_CHG
0R0402-PAD CHG_AGND PC4002
SCD1U50V3KX-GP
2
2N7002KDW-GP SCD1U50V3KX-GP 0R0402-PAD
SC2200P50V2KX-2GP
PR4033 CHG_AGND CHG_AGND PWR_DCBATOUT_CHG
SCD1U25V2ZY-1GP
1
PC4004
20R5F-1GP 1 2 PU4001
SC1U6D3V2KX-GP
2
EC4001
EC4002
PC4005
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SCD1U50V3KX-GP
ICREF
1
PWR_CHG_DCIN PWR_CHG_CSSP 1
PC4006
PC4007
PC4008
PC4009
1 2 22 28 2
1
DCIN CSSP
PR4013
DY DY
33R3J-2-GP
1
5
6
7
8
PC4003 PWR_CHG_ACIN 2 SCD1U50V3KX-GP
DY
SIS412DN-T1-GE3-GP
2
D
D
D
D
SCD47U50V5KX-1GP ACIN PWR_CHG_CSSN CHG_AGND
27
3D3V_AUX_KBC DY
2
PWR_CHG_REF CSSN PWR_CHG_ICOUT
11 26
49K9R2F-L-GP
VDDSMB ICOUT
PU4004
PU4004
10KR2F-2-GP
2
PD4001
1
1
PC4010
PR4016
PC4001
SCD01U50V2KX-1GP
SCD1U10V2KX-5GP 25 PWR_CHG_BOOT 1 PR4017 2PWR_CHG_BST1

K A 1
CHG_AGND
2
Id=12A
1
BOOT
G
S
S
S
21 PWR_CHG_VDDP 0R0603-PAD PC4011 Qg=3.8nC Charger Current=1.4~3.6A
2
CHG_AGND PWR_CHG_ACOK VDDP SD103AWS-1-GP

1 PR4012 2 13 SCD1U50V3KX-GP
Rdson=24~30mohm
4
3
2
1
0R0402-PAD ACOK
83.1R504.A8F
2
AC_OK PWR_CHG_UGATE
PR4014
24 2nd = 83.1R504.B8F
1
PWR_CHG_SCL UGATE PC4013 PL4001 BT+_R BT+
2 1 10 1 2
2
(27,39) BAT_SCL SCL

PG4007 GAP-CLOSE-PWR-3-GP PC4012 SC3300P50V3KX-1GP PR4019
23 PWR_CHG_PHASE 1 PR4018 2 SCD1U50V3KX-GP DY PWR_CHG_LX1 1 2 1 2 240mils or Copper Shape
2
PHASE 0R0603-PAD D01R2512F-4-GP
SIS412DN-T1-GE3-GP
PWR_CHG_SDA
PU4005
2 1 9 1 2 84.00412.037 IND-5D6UH-48-GP-U1
DY
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SC10U25V6KX-1GP
(27,39) BAT_SDA
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
CHG_AGND PG4008 GAP-CLOSE-PWR-3-GP SDA PWR_CHG_LGATE PC4014
20
SCD1U50V3KX-GP
LGATE
PC4034
SC220P50V2JN-3GP PL4001
5
6
7
8
1
Id=7.5A
D
D
D
D
PG4010
PG4009
C 14 19 C
NC#14 PGND
PR4001 DCR=23mohm(Max)
2
SCD1U50V3KX-GP
PWR_CHG_CSOP
PC4015
PC4016
PC4017
PC4018
PC4019
(27) AD_IA 1 2 18
Size=10*10
1
CHG_AGND CSOP
20KR2J-L2-GP PWR_CHG_CSON
2
CSON
17 PU4005
G
S
S
S
PWR_CHG_VICM 8
2PG4009_1
PWR_CHG_FBO VICM Id=16A
PC4020
4
3
2
1
PR4022 Qg=7.3nC
1
SC220P50V2JN-3GP
PR4021 200KR2F-L-GP
4K7R2J-2-GP 1 2
Rdson=13.5~16.5mohm
6
8K45R2F-2-GP
FBO CHG_AGND
PWR_CHG_EAI 5 16 1 PR4023 2 PWR_CHG_CSOP_1 PR4024
1PWR_CHG_FBO1
PC4022 PWR_CHG_EAO EAI NC#16 0R0402-PAD 0R0402-PAD

4
2
PR4026
1
2
PWR_CHG_REF EAO
PR4025
PC4024
SC2200P50V2KX-2GP 3
7K5R2F-1-GP
1
VREF
1 2 2 1PR4526_01
2 1 PWR_CHG_CE 7 PC4023
1
CE
1 PR4027 2 SCD1U50V3KX-GP
DY 12 15
GND
1
PC4021 0R0402-PAD GND VFB
2
PC4025
SC150P50V2JN-3GP 1 2 PWR_CHG_VFB 1 PR4028 2
2
BATT_SENSE (39)
1
BQ24745RHDR-GP 0R0402-PAD
SCD1U50V3KX-GP
SC56P50V2JN-2GP
29
1
PC4031
PC4029
PC4026 DY DYPC4027 DY DYPC4030
DY
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
2
1
PC4028
SCD1U50V3KX-GP
SCD01U50V2KX-1GP
2
1
SCD1U25V2ZY-1GP
1
PC4032
PR4030
SCD01U50V2KX-1GP 1 PR4029 2
DY
1K8R6J-GP
0R0402-PAD 1 PR4020 2
2
DY 0R0402-PAD
2
CHG_AGND CHG_AGND
CHG_AGND
CHG_AGND CHG_AGND
This Resistor
must be 1%
tolerance.
(27) AC_IN# PQ4004_D
1
PR4037
D
76K8R2F-GP
1
PC4033 PQ4002
SCD1U10V2KX-5GP
DY 2N7002K-2-GP D
2
PQ4004
84.2N702.J31
2
B 3D3V_AUX_S5 2N7002K-2-GP B
2ND = 84.2N702.031 84.2N702.J31
1
PR4040 ICREF
DY2ND = 84.2N702.031
S
10KR2J-3-GP
AC_OK
2
AC_OK (27)
(27) AD_IA_HW2 1 2PQ4004_G

PR4036
0R0402-PAD CHG_AGND
20101222 A00
Power/Brian: Change PR4036 to 0 ohm pad.
Stuff PQ4004.
Change PR4037 to 76.8k ohm from 49.9k ohm.
A A
<Core Design>
Wistron Corporation
Title
CHARGER BQ24745
Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
20110110 A00:
Change PG4102~PG4109,PG4111,PG4113 to ZZ.CLOSE.001.
3D3V_AUX_S5
5V_AUX_S5 DCBATOUT PWR_DCBATOUT_5V3D3V
5V_AUX_S5 +5V_VCC1
PU4105 PG4102 GAP-CLOSE-PWR-3-GP
1 2 1 2
PC4131
PR4102 10R3J-3-GP 1 5
SC1U10V3KX-3GP
1
20110110 A00: VIN VOUT
2
1
Change PG4110,PG4112,PG4114~PG4119,PG4122,PG4126,PG4129,PG4131,PG4133,PG4135~PG4138,PG4140,PG4142 to ZZ.CLOSE.001. PC4102 GND PG4103 GAP-CLOSE-PWR-3-GP
3 4
SC1U10V3KX-3GP
SC4D7U10V5KX-1GP EN NC#4
1 2
PC4132
2
G9091-330T11U-GP
5V_S5 5V_PWR DCBATOUT PWR_5V3D3V_VREF2 PG4104 GAP-CLOSE-PWR-3-GP
2
PG4110 GAP-CLOSE-PWR-3-GP 1 2
1 2 74.09091.J3F
20101230 A00: PWR_5V3D3V_VREF3 +5V_VCC1 +5V_VCC1
0R0805-PAD
0R0805-PAD
1
1
Change PR4103,PR4104 to 0R0805 short pad. PG4105 GAP-CLOSE-PWR-3-GP
D
2nd = 74.09198.G7F D
PR4103
PR4104
PG4112 GAP-CLOSE-PWR-3-GP 1 2
1 2 PC4103
1 2 3rd = 74.07716.A7F GAP-CLOSE-PWR-3-GP PG4106
1
2 1
0R2J-2-GP
2
PR4105
PG4114 GAP-CLOSE-PWR-3-GP SC1U25V3KX-1-GP PR4106
SC1U25V3KX-1-GP
1
1 2 PR4107 20110103 A00: GAP-CLOSE-PWR-3-GP PG4107
0R2J-2-GP DY 0R0603-PAD
Change PR4106 to 0R0603 short pad.
PC4105
2 1
1
PWR_5V3D3V_VIN
PWR_5V3D3V_TONSEL
DY
2
PG4115 GAP-CLOSE-PWR-3-GP PC4104 GAP-CLOSE-PWR-3-GP PG4108
1 2 SCD1U25V3KX-GP 2 1
2
PWR_DCBATOUT_5V3D3V
1 2 GAP-CLOSE-PWR-3-GP PG4109
Vout(5V)=VFB1*(1+R1/R2) DY0R2J-2-GP
2
PG4116 GAP-CLOSE-PWR-3-GP PR4108 2 1
PR4109
1 2 PWR_5V3D3_AGND
0R2J-2-GP
PWR_DCBATOUT_5V3D3V 1 2PC4106 GAP-CLOSE-PWR-3-GP PG4111
DY
SC1KP50V2KX-1GP
PG4117 GAP-CLOSE-PWR-3-GP SC1U25V3KX-1-GP 2 1
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SCD1U50V3KX-GP
SCD1U50V3KX-GP
PC4107
PC4108
PC4109
PC4110
PC4111
1 2
1
GAP-CLOSE-PWR-3-GP PG4113
PU4104 2 1
PC4112
PC4113
PC4114
PC4115
PC4129
PC4116
PG4119 GAP-CLOSE-PWR-3-GP AON7410-GP
SC1KP50V2KX-1GP
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SCD1U50V3KX-GP
2
1
8
7
6
5
4
3
2
1
1 2 PU4103
PWR_5V3D3_AGND
LDO
VREF3
EN_LDO
TONSEL
VREF2
LDOREFIN
VIN
V5FILT
5
6
7
8
2
8
7
6
5
8
7
6
5
D
D
D
D
PG4122 GAP-CLOSE-PWR-3-GP CLOSE TO PIN 10
D
D
D
D
D
D
D
D
1 2 33
SIR172DP-T1-GE3-GP
SIR172DP-T1-GE3-GP
GND
2 1
DY PC4117 32 PWR_5V3D3V_REFIN2 84.07410.A37
REFIN2 PWR_3D3V_TRIP21 PR4101 2 187KR2F-GP
PU4102
PU4101
PG4124 GAP-CLOSE-PWR-3-GP Design Current = 16A SCD1U25V3KX-GP 9 31 Design Current = 7.4A
VSW TRIP2
G
S
S
S
1 2 84.00172.037 84.00172.037 PWR_5V3D3_AGND 10 30 PWR_3D3V_VOUT2
5V_PWR 25.1A<OCP< 29.3A VOUT1 TPS51427RHBR-GP VOUT2 PWR_5V3D3V_SKIPSEL 11.6A<OCP< 13.7A
11 29 1 DY 2
1 S
2 S
3 S
4 G
1 S
2 S
3 S
4 G
4
3
2
1
VFB1 SKIPSEL
20101224 A00: 1 2PWR_5V_TRIP1 12 28 3V/5V_POK PR4110
PG4126 GAP-CLOSE-PWR-3-GP Rename PTC4101~PTC4103 to PT4101~PT4103. PR4111 3V/5V_POK TRIP1 PGOOD2 PWR_5V3D3V_EN 0R2J-2-GP 3D3V_PWR 3D3V_S5 20110110 A00:
13 27 PL4101
PWR_5V3D3V_EN
105KR2F-1-GP PGOOD1 EN2 PWR_3D3V_DVRH2 PG4118 Change PG4118,PG4120,PG4123,PG4101,PG4127,PG4130,PG4132,PG4134 to ZZ.CLOSE.001.
1 2 PL4102 14 26
PWR_5V_DRVH1 EN1 DVRH2 PWR_3D3V_LL2
15 25 1 2 2 1
PWR_5V_LL1 DRVH1 LL2 IND-2D2UH-46-GP-U GAP-CLOSE-PWR-3-GP
1 2 16
PG4129 GAP-CLOSE-PWR-3-GP IND-1D5UH-34-GP LL1
68.2R210.20B
V5DRV
DRVL1
DRVL2
VBST1
VBST2
NC#20
GAP-CLOSE-PWR-3-GP
1
PGND
PC4120
PC4121
1 2 68.1R510.10J PG4120
SC680P50V2KX-2GP
GND
SCD1U25V3KX-GP
1
5
6
7
8
1
PT4102
PT4101
PC4119
DY PG4121 2 1
SCD1U10V2KX-4GP
ST220U6D3VDM-20GP
ST220U6D3VDM-20GP
8
7
6
5
8
7
6
5
D
D
D
D
DY PU4107 PC4118 GAP-CLOSE-PWR-3-GP
ST220U6D3VDM-20GP
SIR460DP-T1-GE3-GP
SIR460DP-T1-GE3-GP
2
1
1
D
D
D
D
D
D
D
D
PT4103
PC4124
PG4131 GAP-CLOSE-PWR-3-GP PC4122 AON7702-GP SC680P50V2KX-2GP
SCD1U10V2KX-4GP
2
17
18
19
20
21
22
23
24
PU4108 PWR_3D3V_SNUB
PU4106
C 1 2 SCD1U25V3KX-GP PG4123 C
2PG4121_2 2
1
PG4125 PWR_5V_SNUB 20101230 A00:
84.07702.037 2 1
2
2
Change PR4115 to 0R0603 short pad. GAP-CLOSE-PWR-3-GP
1
1
G
S
S
S
PG4133 GAP-CLOSE-PWR-3-GP 20101230 A00:
2D2R6J-3-GP
GAP-CLOSE-PWR-3-GP
2
1
Change PR4116 to 0R0603 short pad.

1 2 DY PR4112 PG4101
S
S
S
S
S
S
G
4
3
2
1
PR4113
PR4115 PR4116 2D2R6J-3-GP 2 1

1
2
3
4
1
2
3
4
PWR_5V__VBST1_1 1 2PWR_5V__VBST1 PWR_3D3V_VBST2 2PWR_3D3V_VBST2_1 GAP-CLOSE-PWR-3-GP
DY 1
1PWR_5V_VOUT1 2
PG4135 GAP-CLOSE-PWR-3-GP 0R0603-PAD 0R0603-PAD PR4114
2
20101224 A00: PWR_3D3V_DRVL2 PG4127
1 2 0R0402-PAD 77.22271.27L
2
Rename PTC4101~PTC4103 to PT4101~PT4103. 2 1

PG4143 GAP-CLOSE-PWR-3-GP GAP-CLOSE-PWR-3-GP
1
PG4136 GAP-CLOSE-PWR-3-GP PWR_5V__DRVL1 1 2 20101230 A00:
1 2 20110110 A00: Change PR4114 to 0R short pad. PG4130
1
Change PG4143 to ZZ.CLOSE.001. CLOSE TO PIN 30 2 1
2
PC4123 GAP-CLOSE-PWR-3-GP
PG4137 GAP-CLOSE-PWR-3-GP SCD1U25V3KX-GP
DY PR4118
2
1 2 PR4117 PWR_5V3D3_AGND 0R2J-2-GP PG4132
0R2J-2-GPDY 2 1
GAP-CLOSE-PWR-3-GP
1
PG4138 GAP-CLOSE-PWR-3-GP 5V_AUX_S5
2
1 2 PR4119_2 PG4134
1
PC4101 PWR_5V3D3_AGND 2 1
1
PD4102 SC1U25V3KX-1-GP PWR_5V3D3_AGND GAP-CLOSE-PWR-3-GP

PG4140 GAP-CLOSE-PWR-3-GP PR4119 1
2
1 2 0R0402-PAD PWR_5V3D3V_EN 1 2 3V_5V_EN (36)
3 5V_C_1 1 2 PR4120 2KR2J-1-GP
1
20101230 A00: PC4125
V_REFIN2=VREF2*PR4109/(PR4109+PR4105)
2
PG4142 GAP-CLOSE-PWR-3-GP Change PR4119 to 0R short pad. 2 SCD1U25V2ZY-1GP

1 2 10V_C PR4122
PWR_5V3D3_AGND BAT54SW-2-GP 200KR2J-L1-GP Vout(3.3V)=V_REFIN2*(1+R1/R2)
1
PD4103 3D3V_S5
2
2
PC4126 1
SCD1U25V2ZY-1GP Connect REFIN2 to V5FILT for fixed 3.3V operation
Connect VFB1 to GND for fixe 5V opteration
2
1
3 5V_C_2 1 2 PD4101
PC4127 BAT54-7-F-GP PR4123
15V_S5 15V_PWR 15V_C 2 SCD1U25V2ZY-1GP 100KR2J-1-GP
1
BAT54SW-2-GP
2
GAP-CLOSE-PWR-3-GP PG4139 3V/5V_POK
2 1 1 2 1 215V_C_1
PR4124 PR4125
B 24D9R3F-GP 200KR2J-L1-GP B
1
GAP-CLOSE-PWR-3-GP PG4141
2 1 PR4127
1
39KR2J-GP
PC4128
SCD1U25V2ZY-1GP
2
20110110 A00:
Change PG4139,PG4141 to ZZ.CLOSE.001.
SKIPSEL GND FLOAT/VREF2 V5IN
PWR_5V3D3_AGND
Mode Auto Skip OOA. PWM Only
TONSEL GND VREF2 or Float V5FILT

Ch1 400 kHz 400 kHz 200 kHz
Ch2 500 kHz 300 kHz 300 kHz
A A
1A= 40mils
0.5A= 20mils <Core Design>
0.375A= 15mils
Wistron Corporation
Title

TPS51427_5V/3D3V Rev
A2
Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
SSID = CPU.Regulator
3D3V_PW R 5V_S5
1D05V_VTT 3D3V_S0
1
D PR4204 PR4205 20101231 A00: D
1R2F-GP 1R2F-GP Change PR4209,PR4212 to PN4201 10k array resistor.
20110117 A00:
Swap PN4201 base on the swap report.
1 PR4210
1 PR4208
2
1
2
PC4213
PC4201
SCD1U25V3KX-GP
SCD1U25V3KX-GP
PN4201
1
1D05V_PW R SRN10KJ-5-GP
4
3
130R2F-1-GP
54D9R2F-L1-GP
GND_1316 GND_1316 PU4201
1
DYPR4215
100R2F-L1-GP-U
DYPR4216
100R2F-L1-GP-U
PW R_VCORE_VDD5 12 VDD5 DCMDRP1 18
19
PW R_VCORE_DCMDRP1
PW R_VCORE_DCMDRP2
PW R_VCORE_VDD3 DCMDRP2
43 VDD3
PW R_VCORE_VDD3 42 14 PW R_VCORE_SENSE1- PR4217 1 2 0R0402-PAD
VSSSENSE (8)
2
VDD3 SENSE1- PW R_VCORE_SENSE1+ PR4218 0R0402-PAD

SENSE1+ 13 1 2 VCCSENSE (8)
15 PW R_VCORE_SENSE2- PR4219 1 2 0R0402-PAD 20101227 A00:
SENSE2- VSS_AXG_SENSE (9) Change PR4217~PR4220,PR4254 to 0R 0402 pad.
16 PW R_VCORE_SENSE2+ PR4220 1 2 0R0402-PAD
SENSE2+ VCC_AXG_SENSE (9)
PW R_VCORE_IMON1 21
PW R_VCORE_IMON2 IMON1 PW R_VCORE_TEMP_SENSE1
25 IMON2 TEMP_SENSE1 29
TEMP_SENSE_GFX 1PR4254 TEMP_SENSE_GFX_R 1 2H_PROCHOT#
PC4214
PC4231
30 2
SCD022U16V2KX-3GP
SCD022U16V2KX-3GP
C TEMP_SENSE2 0R0402-PAD PR4224 100KR2F-L1-GP C

(43) PW R_VCORE_DB0 37 DB10
1
36 40 PW R_VCORE_SPHASE_0
(43) PW R_VCORE_DB1 DB11 SPHASE1_0 PW R_VCORE_SPHASE_0 (43)
1
1
PR4221 PR4222 35 39 PW R_VCORE_SPHASE_1
6K98R2-GP 8K87R2F-2-GP (43) PW R_VCORE_DB2 DB12 SPHASE1_1 PW R_VCORE_SPHASE_1 (43) PR4255 PR4256
(44) DB0_GFX 33 DB20 SPHASE1_2 38
32 34 61K9R2F-GP NTC-220K-2-GP
2
(44) DB1_GFX DB21 SPHASE2 SPHASE_GFX (44)

31
2
(44) DB2_GFX DB22

5 H_CPU_SVIDCLK (8)
2
PW R_VCORE_IDES1_N VCLK
(43) PW R_VCORE_IDES1_N 24 IDES1_N VDIO 4 H_CPU_SVIDDAT (8)
PW R_VCORE_IDES1_P 23 NTCG104QH224HT
(43) PW R_VCORE_IDES1_P IDES1_P
(44) IDES_N_GFX 27 IDES2_N VR_ENABLE 6 D85V_PW RGD (48)
(44) IDES_P_GFX 28 IDES2_P VR_TT# 10 H_PROCHOT# (5,27,40)
GND_1316 8
PW R_VCORE_R_OSC VR1_READY PW R_VCORE_VR2_DELAY IMVP_PW RGD (27,36)
1 2 41 R_OSC VR2_READY 9
130KR2F-GP PR4225 1 2 PW R_VCORE_R_REF1 22
44K2R2D-GP PR4226 1 PW R_VCORE_R_REF2 R_REF1
2 26 R_REF2 ALERT# 7 VR_SVID_ALERT# (8)
44K2R2D-GP PR4229
PR4233
1 2 PW R_VCORE_R_SEL0 2 17
23K7R2F-GP PR4231 PW R_VCORE_R_SEL1 R_SEL0 NC#17
1 2 1 R_SEL1 NC#20 20 1 2PW R_VCORE_TEMP_SENSE1_R
1 2 H_PROCHOT#
1 2 39K2R2F-L-GP PR4232 1 2 PW R_VCORE_R_SEL2 48 PR4223 100KR2F-L1-GP
PG4203 39K2R2F-L-GP PR4234 PW R_VCORE_R_SEL3 R_SEL2 5K76R2F-2-GP
PC4218
PC4219
1 2 47
SCD047U25V2KX-GP
SCD047U25V2KX-GP
R_SEL3
1
GAP-CLOSE-PW R 32K4R2F-1-GP PR4235 1 2 PW R_VCORE_R_SEL4 46 49 NTCG104QH224HT
27K4R2F-GP PR4236 PW R_VCORE_R_SEL5 R_SEL4 GND PR4239
1 2 45 11
43K2R2F-L-GP
R_SEL5 GND
1
39K2R2F-L-GP PR4237 PW R_VCORE_R_SEL6 NTC-220K-2-GP
PR4238
1 2 44 R_SEL6 GND 3
GND_1316 3K74R2F-GP PR4201
1D05V_PW R
2
VT1316MAFQX-041-GP 1D05V_PW R
GND_1316 74.01316.F33 PW R_VCORE_DB1 DB1_GFX
B 20101223 A00: B
Power/Brian:
Change PU4201 to 74.01316.F33. GND_1316 20101012
1
PR4243 PR4244 PR4245 PR4246
48K7R3F-1-GP 221KR2F-GP 158KR2F-GP 475KR3F-GP
5V_S5
2
PW R_VCORE_DCMDRP1 PW R_VCORE_DCMDRP2
1
5V_S5
PR4207
20101012
PR4251 DY100R2F-L1-GP-U
1
1
1
PW R_VCORE_IDES1_P 2 1 PQ4202_D PR4249 PC4228
2
PR4253 PQ4203 1K54R2F-GP SC2200P50V2KX-2GP PR4250 PC4229

DY
2
S
AO7401-GP 5K11R2F-L1-GP SC2200P50V2KX-2GP

DY 1KR2F-3-GP
2
1KR2F-3-GP PQ4203_G G
2
DY
D
2
PQ4202
D
DMN601K-7-GP
DY G PQ4201_D PC4428
1
GND_1316 GND_1316
DYSC4700P50V2KX-1GP
D
PW R_VCORE_DB1 (43)
A <Core Design> A
2
S
PQ4201
DMN601K-7-GP PR4240
DY G PQ4201_G 2
DY 1 D85V_PW RGD (48)
Wistron Corporation
0R2J-2-GP
1
S
PC4211 Title
DY SC220P50V2JN-3GP
VT1316+1317_CPU_CORE(1/3)
2

A3
Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
PR4202 PR4203 5V_S5

1 2 1 2
6K19R2F-GP 11K3R2F-2-GP
PC4208
PC4204
PC4205
PC4209
PC4206
PC4210
PC4207
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SCD1U25V3KX-GP
1
1
1 2PW R_VCORE_IDES1_N_2 PC4203
PC4202 SC1KP50V2KX-1GP SC4700P50V2KX-1GP
2
D PW R_VCORE0_IDES_P_1 D
1
PR4206
3K09R2F-1-GP
G4
G5
G6
C6
C5
C4
E4
E5
E6
J4
J5
J6
PU4202
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
PR4213 PR4214
PW R_VCORE0_IDES_N A5 H1 PW R_VCORE_VX0
PW R_VCORE0_IDES_P IDES_N VX#H1
1 2 1 2 A4 IDES_P VX#H2 H2
6K19R2F-GP H3
VX#H3
11K3R2F-2-GP VX#H4 H4
PC4212 A6 H5
(42) PW R_VCORE_DB0 DB0 VX#H5
1 2PW R_VCORE_IDES0_P_1 (42) PW R_VCORE_DB1 A1 DB1 VX#H6 H6
(42) PW R_VCORE_DB2 B1 DB2 VX#D1 D1
SC1KP50V2KX-1GP D2
VX#D2
(42) PW R_VCORE_SPHASE_0 B6 SPHASE VX#D3 D3
VX#D4 D4
PR4211 D5
5V_S5 1 2 A3
74.01317.B3Z VX#D5
D6
AVDD VX#D6
B3 AGND VX#F6 F6
1PU4202_AVDD
10R2J-2-GP B4 F5
C AGND VX#F5 C
B5 AGND VX#F4 F4
VX#F3 F3
VX#F2 F2
AGND
AGND
F1
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VX#F1
PC4215 VT1317SFCX-001-GP 20101231 A00: VCC_CORE
A2
B2
E3
E2
E1
C1
C2
C3
J3
J2
J1
G3
G2
G1
SCD1U25V3KX-GP Power/Brian: change PL4201 to 68.2415N.101 from 68.10110.10G.
2
PR4230 PR4227
1 2 1 2
PG4201
1 2
4
6K19R2F-GP 11K3R2F-2-GP GAP-CLOSE-PW R PL4201
1
PC4217 IND-240NH-GP
PW R_VCORE_IDES1_N 1 2PW R_VCORE_IDES1_N_1 SC4700P50V2KX-1GP GND_1317S_1
(42) PW R_VCORE_IDES1_N
PC4216 SC1KP50V2KX-1GP 2
PW R_VCORE_IDES1_P 5V_S5
(42) PW R_VCORE_IDES1_P
1
68.2415N.101
PC4220
PC4221
PC4222
PC4223
PC4224
PC4225
PC4226
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SCD1U25V3KX-GP
PW R_VCORE1_IDES_P_1
1
2
2
1
B B
PR4241
3K09R2F-1-GP
2
G4
G5
G6
C6
C5
C4
E4
E5
E6
J4
J5
J6
PU4203
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
PR4247 PR4248
PW R_VCORE1_IDES_N A5 H1 PW R_VCORE_VX1
PW R_VCORE1_IDES_P IDES_N VX#H1
1 2 1 2 A4 IDES_P VX#H2 H2
6K19R2F-GP H3
VX#H3
11K3R2F-2-GP VX#H4 H4
(42) PW R_VCORE_DB0 A6 DB0 VX#H5 H5
PC4227 1 2PW R_VCORE_IDES1_P_1 A1 H6
(42) PW R_VCORE_DB1 DB1 VX#H6
SC1KP50V2KX-1GP B1 D1
(42) PW R_VCORE_DB2 DB2 VX#D1
VX#D2 D2
(42) PW R_VCORE_SPHASE_1 B6 SPHASE VX#D3 D3
PR4242 VX#D4 D4
D5
5V_S5 1 2 A3
74.01317.B3Z VX#D5
D6
AVDD VX#D6
B3 AGND VX#F6 F6
10R2J-2-GP B4 F5
AGND VX#F5
B5 AGND VX#F4 F4
VX#F3 F3
1PU4203_AVDD
VX#F2 F2
AGND
AGND
F1
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VX#F1
A <Core Design> A
VT1317SFCX-001-GP
A2
B2
E3
E2
E1
C1
C2
C3
J3
J2
J1
G3
G2
G1
PC4230
SCD1U25V3KX-GP Wistron Corporation
2
PG4202 Title
1 2
VT1316+1317_CPU_CORE(2/3)
GAP-CLOSE-PW R Size Document Number Rev
A3
GND_1317S_2 Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
D D
20101012 PR4402 PR4403
(42) IDES_N_GFX 1 2 1 2
3K24R2F-GP 11KR2F-L-GP PC4414

1
5V_S5 VCC_GFXCORE
PC4413 1 2 IDES_N_GFX_1 SC4700P50V2KX-1GP
2
SC2700P50V2KX-1-GP
PC4415
PC4416
PC4417
PC4418
PC4419
PC4420
PC4421
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SCD1U25V3KX-GP
PW R_AXG_IDES_P_1 5V_S5
1
2
2
1
1
PR4404
3K09R2F-1-GP
PR4401
10R2J-2-GP
PC4422 1 2 IDES_P_GFX_1
8+a8+
G4
G5
G6
C6
C5
C4
SC2700P50V2KX-1-GP
E4
E5
E6
J4
J5
J6
PU4401 PL4401 2120mils or Copper Shape
C C
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
PR4406 PR4405
PW R_AXG_IDES_N A5 H1 PW R_AXG_VX
1 2
PW R_AXG_IDES_P A4 IDES_N VX#H1 IND-D1UH-26-GP
(42) IDES_P_GFX 1 2 1 2 IDES_P VX#H2 H2
PC4423
PC4401
PC4424
PC4425
PC4426
H3 68.R1010.10T
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
20101012 VX#H3
3K24R2F-GP 11KR2F-L-GP VX#H4 H4
1
(42) DB0_GFX A6 DB0 VX#H5 H5
(42) DB1_GFX A1 DB1 VX#H6 H6
(42) DB2_GFX B1 D1
2
DB2 VX#D1
VX#D2 D2
(42) SPHASE_GFX B6 SPHASE VX#D3 D3
VX#D4 D4
VX#D5 D5
A3 AVDD VX#D6 D6
B3 F6
B4
AGND 74.01317.B3Z VX#F6
F5
AGND VX#F5
B5 AGND VX#F4 F4
F3
1PWR_AXG_AVDD
VX#F3
F2
VX#F2 2120mils or Copper Shape
AGND
AGND
F1
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VX#F1
A2
B2
E3
E2
E1
C1
C2
C3
J3
J2
J1
G3
G2
G1
VT1317SFCX-001-GP
PC4402
PC4403
PC4404
PC4405
PC4406
PC4407
PC4408
PC4409
PC4410
PC4411
PC4412
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
1
1
PC4427
SCD1U25V3KX-GP DY DY
2
2
B B
1 2
PG4401
GAP-CLOSE-PW R
GND_1317S_3
A <Core Design> A
Wistron Corporation
Title
VT1316+1317_AXG_CORE(3/3)
A3
Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
1D05V_PW R 1D05V_VTT
1 2
PG4501
GAP-CLOSE-PW R
1 2
PG4502
GAP-CLOSE-PW R
1 2
PG4503
D GAP-CLOSE-PW R D
1 2
PG4504
GAP-CLOSE-PW R
1 2
5V_S5 PG4505
GAP-CLOSE-PW R
5V_S5
1 2
PG4506
1
GAP-CLOSE-PW R
PR4512 1 2
10R2J-2-GP PG4507
SC1U10V2KX-1GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
GAP-CLOSE-PW R
PC4502
PC4503
PC4504
PC4501
PC4505
2
1
PW R_1D05V_AVDD 1 2
PG4508
GAP-CLOSE-PW R
2
1
3D3V_S0
PC4524
SCD22U10V3KX-2GP
VREF=1.21V 1
PG4509
2
2
Vout=VREF*(Rdes/Rbios) GAP-CLOSE-PW R
C4
C5
B3
E4
E5
Design Current = 9.4A<OCP<A
PU4501 1 2
1
AGND_1R05B_VTT PG4510
AVDD
VDD
VDD
VDD
VDD
PR4502 GAP-CLOSE-PW R
C 100KR2J-1-GP PL4501 1D05V_PW R C
PW R_1D05V_IRIPL B2 D1 PW R_1D05V_VX 1 2
2
IRIPL VX#D1
B4 TEMP VX#D2 D2
PW R_1D05V_BIAS A1 D3 COIL-D20UH-GP
SC6800P25V2KX-1GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SCD1U10V2KX-4GP
PW R_1D05V_R_SEL/LOAD BIAS VX#D3
PC4508
PC4509
PC4510
PC4511
PC4512
PC4513
PC4514
PC4515
A2 R_SEL/ILOAD VX#D4 D4 68.R2010.201
VX#D5 D5
1
VT357FCX-ADJ-007-GP
PR4503 1 2 0R0402-PAD PW R_1D05V_OE A5 A4
(19,46,47) RUNPW ROK OE VSENSE+
PR4505 1 2 0R0402-PAD PW R_1D05V_STAT B5 A3 PW R_1D05V_VDES
2
(37,48) 1.05VTT_PW RGD STAT VDES
34K8R2F-1-GP
AGND
44K2R2D-GP
GND
GND
GND
GND
GND
GND
SCD01U25V2KX-3GP
20101227 A00:
1
Change PR4503,PR4505,PR4504,PR4509
PC4507
PR4501
PR4506
to 0R 0402 pad. PR4507 22u * 12PCS
C1
C2
C3
E1
E2
E3
B1
6K49R2F-1-GP
2
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
2
PC4516
PC4517
PC4518
PC4519
PC4520
PC4521
1
1
AGND_1R05B_VTT
DY DY
2
AGND_1R05B_VTT
B B
1 2 1D05V_PW R
PG4511
GAP-CLOSE-PW R
2
PR4513
AGND_1R05B_VTT 100R2F-L1-GP-U
close output MLCC1 PR4504 2
1
PW R_1D05V_VSENSE+
VCCIO_SENSE (8)
0R0402-PAD
VSENSE-TRACE
ROUTED DIFFERENTIALLY
1
PR4508
1MR2F-GP DY PR4511
38K3R2D-GP
PC4522
SC2200P50V2KX-2GP PARALLEL TO VSENSE+
2
2
2
PW R_1D05V_VSENSE- 1 PR4509 2 VSSIO_SENSE (8)
close output MLCC 0R0402-PAD
0.5A= 20mils
2
PR4514
100R2F-L1-GP-U
A <Core Design> A
1
Wistron Corporation
Title
VT357_+1.05V_VTT
A3
Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
SSID = PWR.Plane.Regulator_1p5v0p75v
5V_S5
ˢ
VREF=1.21V
Vout=VREF*(Rdes/Rbios)
SC1U10V2KX-1GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
1
PR4606
PC4628
PC4607
PC4617
PC4618
PC4611
10R2J-2-GP
1
D PU4602 1D5V_PW R 1D5V_S3 D
2
20101227 A00: PW R_1D5V_BIAS A1 C4 Design Current = 13.7A
2
Change PR4605,PR4607,PR4611,PR4602 to 0R 0402 pad. PW R_1D5V_R_SEL/ILOAD BIAS VDD
A2 C5 1 2
A3
R_SEL/ILOAD VDD
E5
21.6A<OCP< 25.4A PG4617
VDES VDD GAP-CLOSE-PW R
A4 VSENSE+ VDD G4
1 2 PW R_1D5V_OE A5 E4
(19,27) PM_SLP_S4# OE VDD
(19,45,47) RUNPW ROK 1 PR4607 2 0R0402-PAD PW R_1D5V_STAT B5 STAT VDD G5 1 2
PR4605 0R0402-PAD B4 PC4625 PG4604
PW R_1D5V_IRIPL TEMP PW R_1D5V_AVDD
B2 IRIPL AVDD B3 2 1 SCD22U10V2KX-1GP GAP-CLOSE-PW R
1D5V_PW R
PL4601 1 2
1
B1 AGND_1D5V_PW R PG4606
5K9R2F-GP
44K2R2D-GP
34K8R2F-1-GP
SCD01U25V2KX-3GP
AGND
1
PR4604
PW R_1D5V_VX GAP-CLOSE-PW R
PC4614
PR4610
PR4603
VX#D1 D1 1 2
C1 GND VX#D2 D2
C2 D3 1 2
SC6800P25V2KX-1GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SCD1U10V2KX-4GP
2
GND VX#D3 COIL-D20UH-GP PG4605

2 C3 D4
2
GND VX#D4 GAP-CLOSE-PW R
E1 GND VX#D5 D5 68.R2010.201
1
PC4610
PC4623
PC4619
PC4608
PC4621
PC4624
PC4627
PC4609
E2 GND VX#F1 F1
E3 GND VX#F2 F2 1 2
G1 F3 PG4608
2
GND VX#F3 GAP-CLOSE-PW R
G2 GND VX#F4 F4
AGND_1D5V_PW R G3 F5
GND VX#F5
1 2
PG4607
VT358FCX-ADJ-007-GP GAP-CLOSE-PW R
74.00358.A3Z 22u * 12PCS
1 2
PG4614
C 1 2 GAP-CLOSE-PW R C
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
PG4618
GAP-CLOSE-PW R 1 2
1
PG4609
PC4622
PC4620
PC4613
PC4616
PC4615
PC4612
GAP-CLOSE-PW R
AGND_1D5V_PW R DY DY
2
1 2
PG4611
GAP-CLOSE-PW R
1 2
PW R_1D5V_VSENSE+ 1 2 1D5V_PW R PG4610
PG4619 GAP-CLOSE-PW R
GAP-CLOSE-PW R
PW R_1D5V_VDES 1 2
close output MLCC PG4613
GAP-CLOSE-PW R
SC2200P50V2KX-2GP
56K2R2F-2-GP
1
PC4626
1 2
PR4601
1
VSENSE-TRACE PG4612
PR4608
1MR2F-GP DY GAP-CLOSE-PW R
2
PARALLEL TO VSENSE+ 1 2
2
PG4616
GAP-CLOSE-PW R
PW R_1D5V_VSENSE- 1 2
PG4620 1 2
GAP-CLOSE-PW R PG4615
GAP-CLOSE-PW R
B close output MLCC B
RT9026 for 0D75V_S0

5V_S5 1D5V_S3
Please near 0D75V_PW R_VLDOIN 1 2

PG4603
U34/Pin10 GAP-CLOSE-PW R
PC4606
PC4605
SC10U6D3V3MX-GP
SCD1U10V2KX-4GP
1
PC4603
SC4D7U10V5KX-1GP 1A= 40mils
0.75V_PWR
2
Design Current: 0.7A

0.5A= 20mils
PU4601
10 1 0D75V_PW R 0D75V_S0
0D75V_PW R_S5 VIN VDDQSNS
(19,27) PM_SLP_S4# 1 2 9 S5 VLDOIN 2
A PR4611 0R0402-PAD 8 3 1 2 <Core Design> A
0D75V_PW R_S3 GND VTT PG4601
(19,27,36,37,47) PM_SLP_S3# 1
PR4613
DY 2
0R2J-2-GP
7 S3 PGND 4
GAP-CLOSE-PW R
DDR_VREF_S3 6 VTTREF VTTSNS 5
PC4604
PC4601
Wistron Corporation
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
GND
1
PC4629
PC4630
1 2
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
1 2 PG4602 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

(37) 0D75V_EN
1
PR4602 0R0402-PAD PC4602 RT9026PFP-GP GAP-CLOSE-PW R Taipei Hsien 221, Taiwan, R.O.C.
11
DY DY SCD1U10V2KX-4GP
2
Title
2
VT358_+1.5V_SUS/+0.75V_SUS
A3
Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
SSID = PWR.Plane.Regulator_1p8v
D
1A= 40mils D
1.5A= 60mils
0.5A= 20mils
3D3V_S5
1
PC4707 3D3V_S5
SCD1U25V3KX-GP
2
PW R_1D8V_VIN 1 2
PG4701
PU4701 GAP-CLOSE-PW R
12 VDD VIN 13 1 2
14 PG4702
C PC4702 SC100P50V2JN-3GP VIN GAP-CLOSE-PW R C
1
1 2 11 AGND
17 15 PC4708 PC4715 PC4721
PR4705 PGND PGND SCD1U25V3KX-GP SC10U6D3V5MX-3GP SC10U6D3V5MX-3GP
16
2
PGND
1 2PW R_1D8V_FB_1 1 2 PW R_1D8V_FB 10 FB
PC4718 SC2200P50V2KX-2GP
5K9R2F-GP PW R_1D8V_COMP 9 4 PW R_1D8V_VBST 1 PR4706 2PW R_1D8V_VBST_1
COMP VBST 0R0603-PAD
1
2 PW R_1D8V_RUN 1D8V_S0
PW R_1D8V_PS RES PC4716 PL4701
8 MODE
3D3V_S0 1 2 SCD1U25V3KX-GP IND-2D2UH-46-GP-U
2
PR4707 20KR2J-L2-GP 68.2R210.20B PG4704
1
3 5 PW R_1D8V_SW 1 2 1 2
20KR2F-L-GP
(19,45,46) RUNPW ROK PGOOD SW#5
1
1D8V_EN
PR4702
1 2 1 6
DY (19,27,36,37,46) PM_SLP_S3# EN SW#6
1
PR4717 PR4715 10KR2J-3-GP 7 PC4717 GAP-CLOSE-PW R
57K6R2F-GP SW#7 SC2200P50V2KX-2GP
PC4719
PC4720
SC10U6D3V5MX-3GP
SC22U6D3V5MX-2GP
PG4705
1PWR_1D8V_FB_2
2
2
1
1
PC4703 TPS51311RGTR-GP 1 2
2
SC1U6D3V2KX-GP 74.51311.073 DY GAP-CLOSE-PW R
2
2
PG4706
1 2
GAP-CLOSE-PW R
PG4707
PR4718 1 2
40D2R2F-GP
GAP-CLOSE-PW R
B B
2
PW R_1D8V_FB
1
PR4716
10KR2F-2-GP
2
A <Core Design> A
Wistron Corporation
Title
TPS51311_ +1.8V_RUN
A3
Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
TPS51461 for VCCSA
D
3D3V_S0 D
5V_S5
1
PR4809
4K7R2J-2-GP
1
1
PC4814
2
SC1U10V2KX-1GP
PR4806 1 PR4808 2 D85V_PW RGD (42)
2
1R2F-GP 0R0402-PAD
PR4812
1 DY2
1KR2F-3-GP
2
PW R_VCCSA_VID1 1 PR4804 2 VCCSA_SEL (9)
PWR_VCCSA_PGOOD
PC4816 0R0402-PAD
SC2D2U10V3KX-1GP
PW R_VCCSA_VID0 1 PR4805 2 H_FC_C22 (9)
2 0R0402-PAD
PW R_VCCSA_EN 1 PR4801 2
0R0402-PAD 1.05VTT_PW RGD (37,45)
1
PWR_VCCSA_V5DRV
DY
2
PC4804
18
17
16
15
14
13
U4801 SC1U6D3V2KX-GP
VID1
VID0
PGOOD
EN
V5DRV
V5FILT
C TPS51461RGER-GP PC4805 Design Current = 4.2A C
SCD1U25V3KX-GP
19
6.6A<OCP< 7.8A
5V_S5 PGND PW R_VCCSA_BST 1 PR4807 2 PW R_VCCSA_BST_R
20 PGND BST 12 1 2
21 11 0R0603-PAD 0D85V_S0
PGND SW#11
22 VIN SW#10 10
23 VIN SW#9 9 PL4801
24 VIN SW#8 8
1
PC4803 PC4815 PC4813 PC4819 25 7 PW R_VCCSA_SW 1 2

GND SW#7
PC4808
PC4809
PC4807
PC4810
PC4811
PC4801
COMP
MODE
1
SLEW
SC4D7U25V5KX-GP
SC4D7U25V5KX-GP
SC4D7U25V5KX-GP
VOUT
SCD1U25V3KX-GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
VREF
IND-D47UH-22-GP
GND
2
PR4803
1
74.51461.043 DY 2D2R5F-2-GP DY DY PC4812
68.R4710.10M DY
1
2
3
4
5
6
SCD1U25V3KX-GP
1PWR_VCCSA_SNUB
PR4811
2
PW R_VCCSA_VOUT
PWR_VCCSA_VREF
PWR_VCCSA_COMP
1 2 0D85V_S0
PW R_VCCSA_SLEW 100R2F-L1-GP-U
1 PR4810 2 VCCUSA_SENSE (9)

2
0R0402-PAD
PC4806
SCD01U50V2KX-1GP PC4818
1
DY SC560P50V-GP
1
2
PR4802
4K99R2F-L-GP
B B
2 PWR_VCCSA_COMP_1
VID0 VID1 VCCSA
L L 0.9V
L H 0.8V
H L 0.725V
1
PC4817
H H 0.675V SC3300P50V3KX-1GP
2
2
PC4802
SCD22U10V2KX-1GP
1
A <Core Design> A
Wistron Corporation
Title
APL5916_VCCSA
A3
Nirvana 13 A00
5 4 3 2 1
SSID = VIDEO
DBC_EN_C 2 R4901 1 DBC_EN (22)
SSID = VIDEO
33R2J-2-GP CE_C 2 R4911 1 CE (21)
33R2J-2-GP
1
LCD POWER for ROSA
1
R4906
10KR2J-3-GP R4912
DY DY 10KR2J-3-GP
LVDS CONNECTOR
2
LCD1 DCBATOUT_LCD
31
NP1 83.1R504.A8F
1 2nd = 83.1R504.B8F
PD4901
2
3 BLON_OUT_C_1 K A BLON_OUT_C LCDVDD 3D3V_S0
4 LCD_BRIGHTNESS 2 R4902 1 L_BKLT_CTRL (17) BAT54CPT-GP U4901
5 DBC_EN_C SD103AWS-1-GP 33R2J-2-GP
6 3D3V_CAMERA_S0 (17) LVDS_VDD_EN 1 R4904 1 EN IN#5 5
7 USB_CAMERA# 1 2 2
USB_PN12 (18) GND
8 USB_CAMERA 0R2J-2-GP1 R4908 2 3 LCDVDD_EN 1 2ENVDD 3 4
USB_PP12 (18) OUT IN#4
9 0R2J-2-GP R4909
SC1U10V3KX-3GP
3D3V_S0
SCD1U10V2KX-5GP
10 20101227 A00: 2 0R0402-PAD
AUD_DMIC_CLK (29,97) (27) LCD_TST_EN
C4908
Change R4908,R4909,R4919,R4920,R4903,R4910,R4913~R4916
C4907
11 G5285T11U-GP
49K9R2F-L-GP
AUD_DMIC_IN0 (29,97)
1
R4917,R4918 to 0R 0402 pad.
R4905
12 D4901
LVDSA_CLK_R 20110111 A00:
13
74.05285.07F
1
2
LVDSA_CLK#_R Change R4908,R4909,R4903,R4910,R4913~R4916
14 83.R2003.E81 DY
2
R4917,R4918 to 0R 0402 reisstors.
15 CE_C 1 TP4903TPAD14-GP 2ND = 83.00054.Q81 2nd = 74.09724.09F
2
16 LVDSA_DATA2_R SRN2K2J-1-GP
17 LVDSA_DATA2#_R RN9403
18
19 LVDSA_DATA1_R
4
3
20 LVDSA_DATA1#_R LVDS_VDD_EN
21 LVDS_DDC_CLK_R
1
22 LVDSA_DATA0_R LVDS_DDC_DATA_R
23 LVDSA_DATA0#_R R4951 1 R4907 2
24 LVDS_DDC_DATA_R_1 1
LVDS_DDC_CLK_R_1 0R2J-2-GP
2 LVDS_DDC_DATA_R (17,97) 100KR2J-1-GP DY 100KR2J-1-GP
25 1 2 R4919 LVDS_DDC_CLK_R (17,97) RN4901
26 LCD_TST_C 1 0R2J-2-GP R4920 BLON_OUT_C 1 4 BLON_OUT (27)
2
27 TP4904TPAD14-GP 3D3V_S0 LCD_TST_C 2 3 LCD_TST (27)
28 LCDVDD
29 SRN100J-3-GP
30
SCD1U10V2KX-5GP
C4901
NP2
1
32 C4902
BLON_OUT_C_1 1 R4921 2
PS-CON30-GP SC1U6D3V2KX-GP 100KR2J-1-GP
2
20.F1816.030
LVDSA_DATA2_R 1 R4903 2 0R2J-2-GP LVDSA_DATA2 (17)

LVDSA_DATA2#_R 1 R4910 2 0R2J-2-GP LVDSA_DATA2# (17)
LVDSA_DATA2_R EC4906 1 DY2 SC10P50V2JN-4GP
CAMERA and DIGITAL MIC PIN DEFINE! LVDSA_DATA2#_R EC4907 1 DY2 SC10P50V2JN-4GP

LVDSA_DATA1#_R EC4909 1 DY2 SC10P50V2JN-4GP

LVDSA_DATA0#_R EC4911 1 DY2 SC10P50V2JN-4GP
LVDSA_CLK_R 1 R4917 2 0R2J-2-GP LVDSA_CLK (17)

LVDSA_CLK#_R 1 R4918 2 0R2J-2-GP LVDSA_CLK# (17)
DCBATOUT_LCD DCBATOUT
20100104 A00:
F4901 Remove TR4902.
2 1
1
POLYSW -1D1A24V-GP-U For EMI request

C4904 C4905 Close to LVDS connector
69.50007.A31
SCD1U50V3KX-GP
SC1KP50V2KX-1GP
2
2nd = 69.50007.A41 LCD_BRIGHTNESS

LCD_TST_C
LVDSA_CLK#
<Core Design>
LVDSA_CLK
Camera Power
1
EC4904 EC4905 EC4901 EC4902

3D3V_S0 3D3V_CAMERA_S0
DY DY DY Wistron Corporation
SC5D6P50V2CN-1GP
SC5D6P50V2CN-1GP
F4902 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

2
1 2 Taipei Hsien 221, Taiwan, R.O.C.

DY
SC33P50V2JN-3GP
SC33P50V2JN-3GP
0R3J-0-U-GP Title
1
EC4903
DY C4903
SC10U6D3V5KX-1GP
LCD/Inverter Connector
SCD1U10V2KX-5GP Size Document Number Rev
2
A3
20110107 A00: Nirvana 13 A00
Change F4902 to 0603 0 ohm. Date: Tuesday, January 18, 2011 Sheet 49 of 104
5 4 3 2 1
500mA 5V_CRT_S0 Place closer 5V_CRT_S0_R

5V_S0
D5001 F5001
1 2 1 2
Reserve for ATI to debug 83.R5003.C8FCH551H-30PT-GP FUSE-1D1A6V-4GP-U

2ND = 83.R5003.H8H 69.50007.691 CRT1
3rd = 83.5R003.08F 2nd = 69.50007.771
R5007 1 DY 2 0R2J-2-GP R5006 16
(85) VGA_CRT_RED R5008 1
D
(85) VGA_CRT_GREEN DY 2 0R2J-2-GP 1 DY 2 D
R5009 1 DY 2 0R2J-2-GP 6
(85) VGA_CRT_BLUE 0R3J-0-U-GP CRT_R 1 11
7
CRT_G 2 12 CRT_DDCDATA_CON
5V_CRT_S0_R 8
L5001 CRT_B 3 13 CRT_HSYNC_CON
2 1 CRT_RED_R 1 2 CRT_R 9
(17) CRT_RED R5010 0R0402-PAD FCM1608CF-220T05-GP CRT_VSYNC_CON
4 14
10
1
L5002 5 15 CRT_DDCCLK_CON
2 1 CRT_GREEN_R 1 2 CRT_G C5013
(17) CRT_GREEN R5011 0R0402-PAD FCM1608CF-220T05-GP SCD01U16V2KX-3GP 17
2
L5003 D-SUB-15-81-GP
2 1 CRT_BLUE_R 1 2 CRT_B
(17) CRT_BLUE R5012 0R0402-PAD FCM1608CF-220T05-GP
C5001
C5002
C5003
SC10P50V2JN-4GP
SC10P50V2JN-4GP
SC10P50V2JN-4GP
1
1
150R2F-1-GP
150R2F-1-GP
150R2F-1-GP
SC10P50V2JN-4GP
SC10P50V2JN-4GP
SC10P50V2JN-4GP
1
1
R5001
R5002
R5003
1
20101224 A00:
C5004
C5005
C5006
Change R5010~R5012 to 0402 0 ohm pad. DY DY DY
2
2
2
CRT_DDCDATA_CON
CRT_B
CRT_G
CRT_R
C CRT_HSYNC_CON C
CRT_VSYNC_CON
Reduce layout branch trace.
3
3D3V_S0
D5004 D5003 D5002 CRT_DDCCLK_CON
Keep reserved component near main signal BAV99PT-GP-U BAV99PT-GP-U BAV99PT-GP-U
1
C5011
C5010
C5009
C5008
DY DY DY
SC18P50V2JN-1-GP
SC18P50V2JN-1-GP
SC100P50V2JN-3GP
SC100P50V2JN-3GP
DY DY DY DY
2
CRT Hsync & Vsync level shift
CRT DDCDATA & DDCCLK level shift
B B
Reserve for ATI to debug 3D3V_S0 5V_CRT_S0

RN5001
SRN0J-6-GP RN5002
1 4 SRN0J-6-GP
(83,85) VGA_CRT_HSYNC DY
2
1
(83,85) VGA_CRT_VSYNC 2 3 (85) VGA_CRT_DDCDATA 1 4
2
1
2 3 RN5007 3D3V_S0
(85) VGA_CRT_DDCCLK DY SRN2K2J-1-GP RN5003
SRN2K2J-1-GP
RN5004
(17) CRT_HSYNC 2 1 CRT_HSYNC_R 1 4 CRT_HSYNC_CON
Q5001
3
4
(17) CRT_VSYNC R5013
2 0R0402-PAD
1 CRT_VSYNC_R 2 3 CRT_VSYNC_CON
3
4
R5014 0R0402-PAD 2 1 CRT_DDC_DATA_R 4 3 CRT_DDCDATA_CON
(17) CRT_DDC_DATA
SRN33J-5-GP-U R5015 0R0402-PAD
5 2
20101227 A00: 20101231 A00:
Change R5013~R5016 to 0R 0402 pad. Change R5004,R5005 to RN5001 33 ohm array resistor. 6 1
2N7002KDW -GP
2 1 CRT_DDC_CLK_R 84.2N702.A3F
(17) CRT_DDC_CLK
R5016 0R0402-PAD 2nd = 84.DM601.03F
CRT_DDCCLK_CON
A <Core Design> A
Wistron Corporation
Title
CRT Connector
A3
Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
SSID = VIDEO HDMI Level Shifter & CONNECTOR HDMI CONN

Removed HDMI_IN# CIRCUIT
connect to KBC GPIO.
HDMI_PLL_GND HDMI1
23
2
21
R5123 1 HDMI_DATA2_R_C
D
DY 0R2J-2-GP
D Removed LEVEL SHIFTER base on DELL feedback spec. Q5103 2 D
2N7002K-2-GP 3 HDMI_DATA2_R_C#
(No support 220MHZ deep color mode, so can be removed
1
4 HDMI_DATA1_R_C
84.2N702.J31 5
HDMI LEVEL SHIFTER circuit. 2ND = 84.2N702.031 6
7
HDMI_DATA1_R_C#
HDMI_DATA0_R_C
5V_S0 8
S
9 HDMI_DATA0_R_C#
10 HDMI_CLK_R_C
11
1
12 HDMI_CLK_R_C#
R5113 13
DY 100KR2J-1-GP 14
15 DDC_CLK_HDMI
16 DDC_DATA_HDMI 5V_CRT_S0_R
2
17
18
19
20
1
22 C5102
Close to GPU SCD1U10V2KX-5GP
SKT-HDMI23-GP
2
RN5108
HDMI_CLK# 1 4 HDMI_CLK_R#_1 C5103 1 2 SCD1U10V2KX-5GP HDMI_CLK_R_C#
(85) HDMI_CLK# 22.10296.341
HPD_HDMI_CON
HDMI_CLK 2 DY 3 HDMI_CLK_R_1 C5104 1 2 SCD1U10V2KX-5GP HDMI_CLK_R_C
(85) HDMI_CLK SRN0J-6-GP
HDMI_DATA0# 1 SRN0J-6-GP
4 HDMI_DATA0_R#_1 C5105 1 2 SCD1U10V2KX-5GP HDMI_DATA0_R_C#
(85) HDMI_DATA0# HDMI_DATA0 HDMI_DATA0_R_1 C5106 SCD1U10V2KX-5GP HDMI_DATA0_R_C 3D3V_S0
(85) HDMI_DATA0 2 DY 3 1 2
C RN5109 C
RN5110
HDMI_DATA1# 1 4 HDMI_DATA1_R#_1 C5110 1 2 SCD1U10V2KX-5GP HDMI_DATA1_R_C#
(85) HDMI_DATA1#
3
HDMI_DATA1 2 DY 3 HDMI_DATA1_R_1 C5107 1 2 SCD1U10V2KX-5GP HDMI_DATA1_R_C
(85) HDMI_DATA1 SRN0J-6-GP 1 2HDMI_HPD_B 1 Q5102
HDMI_DATA2# 1 SRN0J-6-GP
4 HDMI_DATA2_R#_1 C5108 1 2 SCD1U10V2KX-5GP HDMI_DATA2_R_C# R5111 150KR2J-L1-GP PMBS3904-1-GP
(85) HDMI_DATA2# HDMI_DATA2 HDMI_DATA2_R_1 C5109 SCD1U10V2KX-5GP HDMI_DATA2_R_C
2 DY 3 1 2
2
(85) HDMI_DATA2
1
84.03904.L06 R5124
RN5111 R5110 2nd = 84.03904.P11 HDMI_HPD_E 1 DY 2 0R2J-2-GP HDMI_HPD_DET (85)
Close to HDMI Connector 200KR2J-L1-GP
DY 3rd = 84.03904.T11
1
1 2 HDMI_PCH_DET (17)
8
7
6
5
8
7
6
5
R5112 R5125 0R0402-PAD
2
RN5106 RN5107 10KR2J-3-GP
Close to PCH SRN680J-GP SRN680J-GP
2
RN5112 SRN0J-6-GP
2 3 HDMI_CLK_R#_1
1
2
3
4
1
2
3
4
(17) HDMI_CLK_R# HDMI_CLK_R_1 HDMI_PLL_GND
(17) HDMI_CLK_R 1 4
2 3 HDMI_DATA0_R#_1
(17) HDMI_DATA0_R# HDMI_DATA0_R_1 5V_CRT_S0_R
(17) HDMI_DATA0_R 1 4
RN5113 SRN0J-6-GP
4
3
RN5115 SRN0J-6-GP 3D3V_S0
2 3 HDMI_DATA1_R#_1
(17) HDMI_DATA1_R# HDMI_DATA1_R_1 RN5101
(17) HDMI_DATA1_R 1 4
SRN2K2J-1-GP
B HDMI_DATA2_R#_1 B
(17) HDMI_DATA2_R# 2 3
1 4 HDMI_DATA2_R_1
Q5104
1
2
(17) HDMI_DATA2_R
RN5114 SRN0J-6-GP PCH_HDMI_CLK 4 3 DDC_CLK_HDMI
20100106 A00: 5 2
Remove RN5112~RN5115. ATI GPU has 5V Tolerance
20110111 A00: 6 1
Change RN5112~RN5115 to 0R array resistors. 20101224 A00:
RN5105 Change RN5117,RN5112~RN5115 to 0402 0 ohm pad.
DDC_CLK_HDMI 20110111 A00: PCH_HDMI_DATA 2N7002KDW -GP
(85) GPU_HDMI_CLK 2 3
DDC_DATA_HDMI Change RN5117 to 0 ohm resistor. 84.2N702.A3F
(85) GPU_HDMI_DATA 1 DY 4 20110118 A00: DDC_DATA_HDMI
Remove RN5117 for PCH_HDMI_CLK and PCH_HDMI_DATA.
SRN0J-6-GP 2nd = 84.DM601.03F
3D3V_S0 Already PH on PCH side.(RN1706)
(17) PCH_HDMI_CLK PCH_HDMI_CLK

(17) PCH_HDMI_DATA PCH_HDMI_DATA
1
DY R5109
20KR2J-L2-GP
Routing Guidelines:
2
HDMI_OE# 1 DY 2 R5127 HDMI_IN# (27)

0R2J-2-GP
CTRLDATA must be routed longer than CTRLCLK within 1000 mils (25.4 mm).
A <Core Design>
D
Q5101
The total delay on CTRLDATA should be longer than CTRLCLK.
2N7002K-2-GP
84.2N702.J31 Wistron Corporation
DY 2ND = 84.2N702.031 Taipei Hsien 221, Taiwan, R.O.C.
Title
G
HPD_HDMI_CON HDMI Level Shifter/Connector

A3
Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
D D
(Blanking)
C C
B B
A <Core Design> A
Wistron Corporation
Title
LVDS_Switch
A3
Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
SSID = User.Interface
ITP Connector
D D
H_CPURST# use pull-up Resistor close
ITP connector 500 mil ( max ),
others place near CPU side.
CPU ITP Connector

TCK(PIN 5)
TCK(PIN AC5)
FBO(PIN 11)
C C
B B
A <Core Design> A
Wistron Corporation
Title
Size
ITP
Document Number Rev
A3
Nirvana 13 A00
5 4 3 2 1
SSID = SATA SATA HDD Connector
3D3V_S0 5V_S0
SC56P50V2JN-2GP
SC56P50V2JN-2GP
1
1
C5604
C5601
C5605 C5606
HDD1
19 20 HDD1_20 1 TP5601 TPAD14-GP
SCD1U10V2KX-5GP
SC10U10V5ZY-1GP
2
2
1
2 SATA_TXP0_C
SATA_TXN0_C 3
4
SATA_RXN0_C 5
6 SATA_RXP0_C
7
8
3D3V_S0 9
10 3D3V_S0
11
12 5V_S0
5V_S0 13
14
(79) FFS_INT2 15
16
17
18
TPAD14-GP TP5602 1HDD1_21 21 22 HDD1_22 1
TP5603 TPAD14-GP
(21) SATA_TXP0 SCD01U16V2KX-3GP 2 1 C5614 SATA_TXP0_C MLX-CONN18A-S1GP
(21) SATA_TXN0 SCD01U16V2KX-3GP 2 1 C5613 SATA_TXN0_C 20.K0229.018
(21) SATA_RXN0 C5616 1 2 SCD01U16V2KX-3GP SATA_RXN0_C
(21) SATA_RXP0 C5615 1 2 SCD01U16V2KX-3GP SATA_RXP0_C
AFTP5601 1 FFS_INT2
SATA Zero Power ODD
ODD Connector (22) SATA_ODD_PW RGT
U5601
SATA_RX- and SATA_RX+ Trace G547F1P81U-GP
ODD1 5V_S0
8
Length match within 20 mil 4 5
EN/EN# OC# ODD_PW R_5V
Mars: 3 IN#3 OUT#6 6
S1 Exchange ODD and ESATA differential pair each other. 2 IN#2 OUT#7 7
1 GND OUT#8 8
1
S2 SATA_TXP4_C C5612 1 2 SCD01U16V2KX-3GP SATA_TXP4 (21) C5609
S3 SATA_TXN4_C C5611 1 2 SCD01U16V2KX-3GP SC10U6D3V5KX-1GP
S4
SATA_TXN4 (21) When the drive is powered on, the FET to the MD/DA pin drive is OFF. 74.00547.C79
2
SATA_RX4-_C C5607 1 2SCD01U16V2KX-3GP
S5
S6 SATA_RX4+_C C5608 1 2SCD01U16V2KX-3GP
SATA_RXN4
SATA_RXP4
(21)
(21)
When the drive is powered off, the FET to the MD/DA pin is ON 2ND = 74.02191.079
S7
5V_S0
P1 ODD_PW R_5V
SATA_ODD_PRSNT# (22) ƵƌƌĞŶƚůŝŵŝƚ
2
P2
R5605
P3
P4 SATA_ODD_DA#_C 0R2J-2-GP 2 1 R5602 100KR2J-1-GP ĐƚŝǀĞ,ŝŐŚ
DY SATA_ODD_DA# (18)
P5
ƚǇƉсхϮ
1
P6
1
R5604
10KR2J-3-GP SATA_ODD_DA#_C
ODD_PWRGT#
9 DY
SKT-SATA7P+6P-50-GP
2
3D3V_S0
62.10065.651 RN5601 <Core Design>
6
2nd = 62.10065.221 SATA_ODD_PW RGT 4 1

SATA_ODD_DA# 3 2 Q5601
2N7002KDW -GP
SRN10KJ-5-GP 84.2N702.A3F Wistron Corporation
2nd = 84.DM601.03F 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
1

SUPPORT ZERO SATA ODD Title

HDD/ODD Rev
SATA_ODD_PW RGT SATA_ODD_DA#
A3
Nirvana 13 A00
5 4 3 2 1
SSID = ESATA
D D
USB CHARGER
U5702
R5721
1 11 0R0402-PAD
USB_PP1_R S0 GND CB
2 D+ S1 10 1 2 USBCHARGER_CB0 (27)
USB_PN1_R 3 9
D- Y+ USB_PP1 (18)
4 GND Y- 8 USB_PN1 (18)0809
5 A+ VDD 7 5V_S5
A- 6
2
PI5USB14550AZEE-GP
C5701
Switch Control Bit:
73.5USB1.003
1
CB=0 (AM):auto detection charger identification active.
SCD1U10V2KX-4GP
C
S0
0
S1
0 Auto
CB=1 (PM):connect DP/DM to TDP/TDM. C
0 1
1 0
1 1 D+/- connects to Y+/-
ESATA CONN
20100104 A00:
Remove R5718,R5719 5V_USB1_S3 ESATA1
1 12 ESATA1_D1 1 2
VBUS DT1 R5722 0R0402-PAD
DT2 13
B USBDET_CON# (27) B
(21) SATA_TXP5 C5707 1 2 SCD01U16V2KX-3GP SATA_TXP5_C 6 4
C5708 1 A+ GND
(21) SATA_TXN5 2 SCD01U16V2KX-3GP SATA_TXN5_C 7 A- GND 5 1 DY2SC5P50V2CN-2GP
8 EC5701
C5705 1 GND
(21) SATA_RXP5 2 SCD01U16V2KX-3GP SATA_RXP5_C10 B+ GND 11
(21) SATA_RXN5 C5702 1 2 SCD01U16V2KX-3GP SATA_RXN5_C 9 14
USB_PP1_R TR5701 USB_PP1_C B- GND
1 2 GND 15
69.10084.081 USB_PP1_C 3 16
USB_PN1_C D+ GND
2 D- GND 17
USB_PN1_R 4 3 USB_PN1_C
W CM2012F2S-GP-U2
SKT-ESATA-USB-11P-6-GP-U
22.10321.W11 1
2nd = 22.10339.261 AFTP5714

AFTE14P-GP
close to ESATA1
AFTP5716 AFTE14P-GP 1 5V_USB1_S3
AFTP5715 AFTE14P-GP 1 USB_PN1_C
AFTP5703 AFTE14P-GP 1 USB_PP1_C
A <Core Design> A
Wistron Corporation
Title
USB/ESATA
A3
Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
SSID = AUDIO
6SHDNHU
/,1(287
&RQQHFWRU 20101224 A00:
Rename LINEOUT1 to LOUT1.
D 20101224 A00: D
0402 0R pad: R5805,R5806.
20101224 A00: L5801 LOUT1

Change R5803,R5804 to 0603 0 ohm pad. AUD_HP1_JACK_L2 1 2AUD_HP1_JACK_L2_R 1 2 AUD_HP1_JACK_L1 8
(29) AUD_HP1_JACK_L2 0R0402-PAD R5805 BLM18BD601SN1D-GP 7
SPK1 3
3 L5802 1
(29) AUD_SPK_L-
40 mils R5803 1 2
0R0603-PAD
AUD_SPK_L-_C 1 (29) AUD_HP1_JACK_R2
AUD_HP1_JACK_R2 1
0R0402-PAD R5806
2AUD_HP1_JACK_R2_R 1 2
BLM18BD601SN1D-GP
AUD_HP1_JACK_R1 4
1 2 AUD_SPK_L+_C 2 2
(29) AUD_SPK_L+ R5804 0R0603-PAD 4 5
AUD_HP1_JD# 6
JST-CON2-33-GP (29) AUD_HP1_JD#
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
MLVG0402220NV05BP-GP-U
MLVG0402220NV05BP-GP-U
21.D0300.102 PHONE-JK383-GP-U
22.10133.K31
1
1
EC5803
EC5804
DY DY 1
EC5801 EC5802 EC5805 EC5806
SC1KP50V2KX-1GP SC1KP50V2KX-1GP AFTP5810
2
2
1
AFTP5805
C C
06/28
AFTP5811 1 AUD_HP1_JD#
AFTP5803 1 AUD_HP1_JACK_L1
1 AUD_SPK_L-_C AFTP5804 1 AUD_HP1_JACK_R1

AFTP5801 1 AUD_SPK_L+_C
AFTP5802
06/28
0,&,1
B B
600ohm 100MHz
200mA 0.5ohm DC MICIN1
MIC_IN_L 1 2 MIC_IN_L_C 8
(29) MIC_IN_L R5801 BLM18BD601SN1D-GP 7
3
1
MIC_IN_R 1 2 MIC_IN_R_C 4
(29) MIC_IN_R R5802 BLM18BD601SN1D-GP
2
5
(29) EXT_MIC_JD# 6
EC5807 EC5808 PHONE-JK383-GP-U

22.10133.K31
SC100P50V2JN-3GP
SC100P50V2JN-3GP
1
06/28
DY DY 1
AFTP5808
2
AFTP5806 1 MIC_IN_L_C
AFTP5807 1 MIC_IN_R_C
AFTP5809 1 EXT_MIC_JD#
A <Core Design> A
Wistron Corporation
Title
Audio Jack
A3
Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
D D
C
(Blanking) C
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
SSID = Flash.ROM
SPI FLASH ROM (4M byte) for PCH 3D3V_S5

Notes:
3D3V_S5 The total SPI interface signal between EC and PCH
D can’t not exceed 6500mil. The mismatch between D
1
C6002
C6001
SPI signal must be within 500mil
8
7
6
5
SC10U6D3V5KX-1GP
2
2
RN6001
DY
SCD1U10V2KX-5GP
SRN4K7J-10-GP
1
2
3
4
SPI_HOLD_0#
3D3V_S5
U6001
(21,27) SPI_CS0#_R 1 CS# VCC 8

(21,27) SPI_SO_R 1 2 SPI_SO 2 7
R6001 33R2J-2-GP SPI_W P# DO HOLD#
3 WP# CLK 6 SPI_CLK_R (21,27)
4 VSS DI 5 SPI_SI_R (21,27)
1
DY
1
EC6002 W 25Q32BVSSIG-1-GP
SC4D7P50V2CN-1GP EC6003 DY DY EC6001
72.25Q32.A01
SC4D7P50V2CN-1GP
SC4D7P50V2CN-1GP
2
2
2nd = 72.25320.C01
3rd = 72.25P32.C01
C C
Priority Wistron P/N Manufacturer Vendor P/N

1 72.25Q32.A01 WINDBOND W25Q32BVSSIG
2 72.25320.C01 MXIC MX25L3206EM2I-12G
3 72.25P32.C01 NUMONYX M25PX32-VMW6F
B B
SSID = RBATT
3D3V_AUX_S5
RTC_AUX_S5 Q6001
2
+RTC_VCC
3 RTC1
1 RTC_PW R 1 2R6002 1 PWR

2
1KR2J-1-GP 2
C6003 GND
CH715FPT-GP NP1
R6004 SC1U6D3V2KX-GP NP1
NP2
1
TPAD14-GP TP6001 NP2

1 DY 2 83.R0304.B81 1
A 100R2J-2-GP 2nd = 83.00040.E81 <Core Design> A
2N7002K-2-GP Width=20mils BAT-060003HA002M213ZL-GP
RTC_PW R G
62.70014.001 Wistron Corporation
1
D RTC_DET# (22)
R6003 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
10MR2J-L-GP S Taipei Hsien 221, Taiwan, R.O.C.
TPAD14-GP TP6002 1 +RTC_VCC
Q6002 Title
2
84.2N702.J31
2ND = 84.2N702.031 Size Document Number
Flash/RTC Rev
A3
Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
SSID = USB
Close to ESATA Combo connector
Support 2A
5V_S5 5V_USB1_S3
U6101
USB POWER SW
at least 80 mil
D Main G547F2P81U-GP P/N:74.00547.A79 at least 80 mil 1 GND OUT#8 8 D
2 IN#2 OUT#7 7
3 IN#3 OUT#6 6
1
(27) USB_PW R_EN# 4 EN/EN# OC# 5
1
C6103 C6101 C6102 TC6101
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SC1U10V2KX-1GP ST100U6D3VAM-3-GP
2
G547F2P81U-GP
80.10715.B1L
2
74.00547.A79 2nd = 77.C1071.20L
USB_OC#0_1 (18)
2nd = 74.00547.079
C C
B B
<Core Design>
A A
Wistron Corporation
Title
USB2.0 Power SW
Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
1V_USB30 LDO
20101227 A00:
Change R6205 to 0R 0402 pad.
20101228 A00: USB3.0 Host RT (R6202) RB (R6203) VOUT
20101229 A00:
Remove R6205,R6201 and rename USB3_PWR_ON from USB_PWR_EN. NEC 2.37k ohm (64.23715.6DL) 7.5k ohm (64.75015.6DL)
1.05V
D
TI 11.8k ohm (64.11825.6DL) 30.9k ohm (64.30925.6DL) 1.1V D
2
(27,82) USB3_PW R_ON U6201 R6203
3D3V_S5
RB DY 7K5R2F-1-GP
1 POK GND 9
2 8
1
VEN GND
3 VIN ADJ 7 1V_USB30_LDO_FB (82)
4 VPP VO 6
1
5V_S5 5
NC#5
2
C6202
R6202
SC10U10V5ZY-1GP
2
G9661-25ADJF11U-GP RT DY 2K37R2F-GP 1V_USB30

1
C6203
74.09661.07D 0.6A Vo = 0.8 * ( 1 + ( RT / RB ) )
1
SC1U10V2KX-1GP
2
2nd = 74.09025.03D
1
C6201
SC10U10V5ZY-1GP
2
C C
B B
A <Core Design> A
Wistron Corporation
Title
USB 3.0 Port

A3
Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
Bluetooth Module
D D
BT1
15
NP1
AFTP6301 1 BLUETOOTH_DET# 1 2 BT_ACT 3D3V_S0
WLAN_ACT 3 4
AFTP6302 1 BDC_ON 5 6 USB_PP3
BLUETOOTH_EN 7 BT 8 USB_PN3
AFTP6304 1 BT_LED 9 10
1
AFTP6305 1 BLUETOOTH_GPIO3 11 12 C6301
AFTP6307 1 BLUETOOTH_GPIO5 13 14 BT
NP2 SC2D2U6D3V3KX-GP
2
16
1 AFTP6306
ACES-CONN14D-GP
20.F1500.014
C C
AFTP6309 1 WLAN_ACT
(18) USB_PP3 AFTP6310 1 BLUETOOTH_EN
(18) USB_PN3 AFTP6308 1 BT_ACT
(65) BT_ACT BT_ACT AFTP6311 1 3D3V_S0
(27,65) BLUETOOTH_EN BLUETOOTH_EN AFTP6312 1 USB_PP3
(65) WLAN_ACT WLAN_ACT AFTP6313 1 USB_PN3
1
R6301 EC6301 R6302
SC220P50V2KX-3GP
100KR2J-1-GP
10KR2J-3-GP
DY DY BT
2
2
2
B B
R6303
1 2
DY
0R2J-2-GP
Q6301
BT_LED G
D WLAN_WWAN_LED# WLAN_WWAN_LED# (68) <Core Design>

BT
S
A
Wistron Corporation A
2N7002K-2-GP 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
84.2N702.J31 Taipei Hsien 221, Taiwan, R.O.C.
2ND = 84.2N702.031 Title
Bluetooth
A4
Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
3D3V_S0
FP1
7
1
C6401 1
SCD1U10V2KX-4GP
2
D Biometric_USBPP 2 D
Biometric_USBPN 3
4
5
6
1
AFTP40 ACES-CON6-7GP
20101227 A00:
Change R6403,R6404 to 0R 0402 pad.
20.K0256.006
20100104 A00:
Remove TR6401.
R6403
C C
(18) USB_PN2 1 2 Biometric_USBPN
0R0402-PAD
AFTP42 1 3D3V_S0
AFTP43 1 Biometric_USBPN
AFTP44 1 Biometric_USBPP
(18) USB_PP2 1 R6404 2 Biometric_USBPP
0R0402-PAD
B B
<Core Design>
A
Title
Finger Printer Conn
A4
Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
SSID = Wireless
Mini Card Connector(802.11a/b/g/n)
D D
3D3V_S0 1D5V_S0
1
1
C6502 C6503 C6504 C6505 C6506 C6507
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
2
2
3D3V_S0 1D5V_S0
5V_S5
W LAN_ACT W LAN1
1
6 1.5V REFCLK+ 13 CLK_PCIE_W LAN (20)

C6501 C6508 11
DY REFCLK- CLK_PCIE_W LAN# (20)
SC220P50V2KX-3GP
2
SCD1U16V2KX-3GP
2
3.3V
PERN0 23 PCIE_RXN4 (20)
28 +1.5V PERP0 25 PCIE_RXP4 (20)
48 +1.5V
PETN0 31 PCIE_TXN4 (20)
C 52 33 C
+3.3V PETP0 PCIE_TXP4 (20)
24 36 USB_P11-
+3.3VAUX USB_D- USB_P11+
USB_D+ 38
(63) W LAN_ACT 3 RESERVED#3 SMB_CLK 30 PCH_SMBCLK (14,15,20,79,82)

(63) BT_ACT 5 RESERVED#5 SMB_DATA 32 PCH_SMBDATA (14,15,20,79,82)
R6505 1 2 0R2J-2-GP LPC_AD0_C 8
(21,27,71) LPC_AD0 R6504 1 DY 2 0R2J-2-GP LPC_AD1_C 10
RESERVED#8
RESERVED#10
1
RESERVED#12 WAKE#
7
R6501 (21,27,71) LPC_AD3 R6509 1 DY 2 0R2J-2-GP LPC_FRAME#_C 16 RESERVED#14 CLKREQ#
22
CLK_PCIE_W LAN_REQ# (20)
(27) E51_RXD
DY10R2J-2-GP 2
(21,27,71) LPC_FRAME# E51_RXD_R DY 17
RESERVED#16 PERST# PLT_RST# (5,18,27,71,82,83)
E51_TXD_R RESERVED#17
(27) E51_TXD 1 2 19 RESERVED#19
R6502 20 4
DY0R2J-2-GP (27) W IFI_RF_EN
37
RESERVED#20 GND
9
RESERVED#37 GND
3D3V_S0 39 RESERVED#39 GND 15
41 RESERVED#41 GND 18
(27,63) BLUETOOTH_EN 1 2 45 26 USB_P11- 1 2
20101227 A00: RESERVED#45 GND USB_PN11 (18)
R6510 0R0603-PAD 47 27 R6406
Change R6510 to 0R 0603 pad. RESERVED#47 GND
49 RESERVED#49 GND 29 0R0402-PAD
1 2 +5V_MINI_DEBUG 51 34
5V_S5
R6503 DY 0R3J-0-U-GP RESERVED#51 GND
35
GND
GND 40
42 LED_WWAN# GND 50
(68) W LAN_LED# 44 LED_WLAN# GND 53
(68) W PAN_LED# W PAN_LED# 1 2 W PAN_LED#_R 46 54
NP1
NP2
R6511 0R0402-PAD LED_WPAN# GND
B B
20101227 A00: SKT-MINI52P-42-GP-U1
NP1
NP2
(18,71,97) CLK_PCI_LPC
1
R6508 DY 2
0R2J-2-GP
62.10043.831
USB_P11+ 1 2 USB_PP11 (18)

R6405
0R0402-PAD
20101230 A00:
Change R4606,R4605 to 0R short pad.
20100104 A00:
Remove TR6501.
A <Core Design> A
Wistron Corporation
Title
MINICARD(WLAN)/ITP CONN
A3
Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
D D
(Blanking)
C C
B B
<Core Design>
A
Title
Reserved
A4
Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
Power LED(White) 20110103 A00:
Change R6804,R6806,R6808,R6810 to 620 ohm 5%.
20100106 A00:
LED BD Connector
5V_S5 Change R6804,R6806,R6808,R6810 to 1k ohm 5%.
Q6801
R2
E
PWRLED#_C B R1
C LED_PWR 1 R6804 2 PWR_LED_B LEDBD1
1KR2J-1-GP 7
1
EC6801
PDTA143ET-GP POWER_SW_LED_B PWR_LED_B
1R6801 2 1
DYSC220P50V2KX-3GP 1KR2J-1-GP
84.00143.M11
2
2nd = 84.02143.011 SATA_LED 2
3rd = 84.00143.N11 20110103 A00: BAT_WHITE 3
Change R6801 to 1k. BAT_AMBER 4
LED_WLAN_OUT_B 5
D 6 D
SATA HDD LED(White) 8

5V_S0 ACES-CON6-13-GP
Q6802 20.K0320.006
R2
E
SATA_LED#_C B R1
C SATA_LED_R 1 R6806 2 SATA_LED
1KR2J-1-GP
SC220P50V2KX-3GP
1
EC6805
PDTA143ET-GP
DY AFTP6801 1PWR_LED_B
84.00143.M11
2
2nd = 84.02143.011 AFTP6802 1SATA_LED
3rd = 84.00143.N11 AFTP6803 1BAT_WHITE
AFTP6804 1BAT_AMBER
RN6801 AFTP6805 1LED_WLAN_OUT_B
1 8 PWRLED#_C
(27) PWRLED#
(27) BATT_WHITE_LED#
(27) CHG_AMBER_LED#
2
3
4
7
6
5
WHITE_LED_BAT#
AMBER_LED_BAT#
SATA_LED#_C
Battery LED1(White) AFTP6806
AFTP6807
1 KBC_PWRBTN#_C
1 POWER_SW_LED_B
(21) SATA_LED# 5V_AUX_S5
Q6805
SRN15KJ-2-GP R2
E
WHITE_LED_BAT# B R1
C WHITE_LED_BAT 1 R6808 2 BAT_WHITE
1KR2J-1-GP
SC220P50V2KX-3GP
1
EC6604
PDTA143ET-GP
DY
84.00143.M11
2
2nd = 84.02143.011
3rd = 84.00143.N11
Battery LED2(Amber)
5V_AUX_S5
Q6804
C C
R2
E
AMBER_LED_BAT# B R6809
R1
C AMBER_LED_BAT 1 2 BAT_AMBER
390R2J-1-GP
WLAN_WWAN_LED#
1
(63) WLAN_WWAN_LED# PDTA143ET-GP
EC6802
84.00143.M11
2nd = 84.02143.011
DY SC220P50V2KX-3GP
2
3D3V_S0
3rd = 84.00143.N11
WLAN LED (White)

1
R6805
DY 100KR2J-1-GP
5V_S0
U6801 Q6803
1
2
(65) WLAN_LED# R6802

R2
E
83.BAT54.U81 3 WLAN_WWAN_LED# 1 2 LED_WLAN_OUT_R# B R1
C WLAN_LED 1 R6810 2 LED_WLAN_OUT_B
2 15KR2J-1-GP 1KR2J-1-GP
(82) WWAN_LED#
1
PDTA143ET-GP
BAT54A-5-GP
EC6803
D6801
84.00143.M11
2nd = 84.02143.011
DY SC220P50V2KX-3GP
2
1 3rd = 84.00143.N11
3
(65) WPAN_LED#
2
BAS16-6-GP
83.00016.K11
2ND = 83.00016.F11
B B
TPLOCK LED 5V_S0

Q6812
R2
E
R6807
1 2 Q6804_B B R6813 LED1
(27) TP_LOCK_LED# 15KR2J-1-GP
R1
TP_LOCK_LED_R TP_LOCK_LED_A A
C 1 2 K
SC220P50V2KX-3GP
1
EC6804
390R2J-1-GP LED-Y-57-GP
Need change to LOW actived from KBC GPIO PDTA143ET-GP
83.01921.P70
DY
84.00143.M11
2
2nd = 84.02143.011
3rd = 84.00143.N11
Power button LED(White) 20101224 A00:

Rename PWRBTN1 to PWRBT1.
PWRBT1
4
1 2 KBC_PWRBTN#_C 3
(27) KBC_PWRBTN#
R6803 100R2J-2-GP 2
POWER_SW_LED_B 1
5
A A
1
EC6806 EC6807
ACES-CON4-10-GP-U
DY DY
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
20.K0320.004
2
<Core Design>
Wistron Corporation
Title
LED Bord/Power Button

A2
Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
SSID = KBC Internal KeyBoard Connector CAP LED CONTROL
D 20110103 A00: D
Change R6906 to 620 ohm 5%.
5V_S5 20110106 A00:
Q6902 Change R6906 to 1k ohm 5%. CAP_LED_R
KB1 1 R2
31 AFTP6936 R6905 E
1 KB_DET# (21) (27) CAP_LED 1 2 B R1
C CAP_LED_Q 1R6906 2 CAP_LED_R
2 KROW 7 1 15KR2J-1-GP 1KR2J-1-GP
3 KROW 6 1 AFTP6911
KROW 4 AFTP6912 PDTA143ET-GP
4 1
5 KROW 2 1 AFTP6913 84.00143.M11
2nd = 84.02143.011
6 KROW 5 1 AFTP6914 3rd CAP_LED_1
= 84.00143.N11
7 KROW 1 1 AFTP6917 1 2
8 KROW 3 1 AFTP6918 R6907 DY100R2J-2-GP
9 KROW 0 1 AFTP6915
10 KCOL5 1 AFTP6916 CAP_LED:(X01 Low actived)
11 KCOL4 1 AFTP6921
KCOL7 AFTP6922
Connect to KB driving internal LED directly.(MAX 25mA)
12 1 KROW [0..7] (27)
13 KCOL6 1 AFTP6919
14 KCOL8 1 AFTP6920
15 KCOL3 1 AFTP6925 KCOL[0..16] (27)
16 KCOL1 1 AFTP6926
17 KCOL2 1 AFTP6923
18 KCOL0 1 AFTP6924
19 KCOL12 1 AFTP6929
C 24 KCOL9 1 AFTP6934 C
27 CAP_LED_R AFTP6935 CAP_LED_R
28
29
30
32 1 AFTP6901
JAE-CON30-7-GP 1 AFTP72 TouchPad LOCKED

20.K0565.030
5V_S0
5V_S0
TouchPad Connector
1
EC6901 C6901
2
1
DY SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
RN6901
2
SRN10KJ-5-GP
TPAD1
6
3
4
4
B B
3
KB Backlight Connector (27)
(27)
TPDATA
TPCLK 2
1
+5V_KB_BL
5V_S0 C6902 DY DY C6903 5
R6902
SC33P50V2JN-3GP SC33P50V2JN-3GP
2
1 2 1
AFTP71 PTW O-CON4-9-GP-U1
1
0R0402-PAD C6905
SCD1U10V2KX-5GP
20101227 A00: 20.K0382.004
2

KBLIT1 1 5V_S0
5 AFTP73 1 TPCLK
1 AFTP74 1 TPDATA
R6904 AFTP75 2010/07/16 Modify
1 2 KB_LED_DET_C 2
(18) KB_LED_BL_DET
3
51KR2J-1-GP 4
1
6
KB_BL_CTRL#
1
R6903 C6906
SCD1U10V2KX-5GP
+5V_KB_BL
100KR2J-1-GP
1
ACES-CON4-34-GP KB_LED_BL_DET 1 AFTP76
2
20.K0589.004 KB_BL_CTRL# 1 AFTP77

2
2nd = 20.K0613.004 AFTP78

1
AFTP79
A <Core Design>
D
Q6901
P8503BMG-GP
(27) KB_BL_CTRL G
84.P8503.031 Wistron Corporation
2nd = 84.03404.C31
1

S
R6901
100KR2J-1-GP Title
Key Board/Touch Pad/Media Board

2

A3
Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
AFTP80 AFTE14P-GP 1 3D3V_S5

AFTP81 AFTE14P-GP 1 LID_CLOSE#_1
3D3V_S5
D 3D3V_S5 20101224 A00: D
1
Rename HALLSW1 to LID1.
C7002
1
SCD1U10V2KX-5GP
2
R7001 AFTP82
DY 100KR2J-1-GP AFTE14P-GP
1
LID1
R7002
1
2
LID_CLOSE# LID_CLOSE#_1 VCC
(27) LID_CLOSE# 1 2 2 VOUT
3 GND
1
0R0402-PAD
C7001
DY SCD047U16V2KX-1-GP TCS20DPR-GP
2
20101227 A00:
Change R7002 to 0R 0402 pad. 74.TCS20.03B
2nd = 74.09132.A7B
C C
B B
<Core Design>
A
Title
Hall Sensor
A4
Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
D D
3D3V_S0
DB1
11
1 20101229 A00 Modify:
C DB1 change to ZZ.00PAD.Y41(solder mask type) C
2
DY and keep un-stuff at X-Build stage.
(21,27,65) LPC_AD0
(21,27,65) LPC_AD1 3
(21,27,65) LPC_AD2 4
(21,27,65) LPC_AD3 5
(21,27,65) LPC_FRAME# 6
(5,18,27,65,82,83) PLT_RST# 7
8
(18,65,97) CLK_PCI_LPC 9
10
12
PAD-10P-177042-GP
ZZ.00PAD.Y41
PCB Footprint = PAD-10P-177042
B B
<Core Design>
A
Title
Dubug CONN
A4
Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
SSID = SDIO
3D3V_CARD_S0 Close to CARD1
SC10U6D3V5MX-3GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD01U16V2KX-3GP
SC2D2U6D3V3KX-GP
C7403
C7405
1
1
C7401
C7402
C7404
D
DY DY D
2
2
SD/XD/MS/MMC+ Card Reader
3D3V_CARD_S0
CARD1
P13 SD_VCC XD_CD 1 XD_CD# (32)

XD_R/B 2 SP1 (32)
P22 MS_VCC XD_RE 3 SP2 (32)
XD_CE 4 SP3 (32)
18 XD_VCC XD_CLE 5 SP4 (32)
XD_ALE 6 SP5 (32)
XD_WE 7 SP6 (32)
C P4 8 C
(32) SP4 SD_DAT0 XD_WP_IN SP7 (32)
(32) SP3 P3 SD_DAT1
(32) SP13 P25 SD_DAT2 XD_D0 10 SP8 (32)
(32) SP12 P23 SD_DATA3 XD_D1 11 SP9 (32)
XD_D2 12 SP10 (32)
(32) SP8 P10 SD_CLK XD_D3 13 SP11 (32)
(32) SP6 P1 SD_CD XD_D4 14 SP12 (32)
(32) SP1 P2 SD_WP XD_D5 15 SP13 (32)
(32) SP10 P19 SD_CMD XD_D6 16 SP14 (32)
XD_D7 17 XD_D7 (32)
(32) SP14 P9 MS_BS

(32) SP2 P16 MS_INS SD_WP_COM/SDIO_GND P26
(32) SP1 P20 MS_SCLK SD_CD_COM/SDIO_GND P27
SD_GND P7
(32) SP9 P12 MS_DATA0 SD_GND P15
(32) SP12 P11 MS_DATA1
(32) SP8 P14 MS_DATA2 MS_GND P6
(32) SP5 P18 MS_DATA3 MS_GND P24
XD_GND 9
(32) SP11 P21 MMC_DATA4 XD_GND 19
(32) SP9 P17 MMC_DATA5
(32) SP7 P8 MMC_DATA6 NP1 NP1
(32) SP5 P5 MMC_DATA7 NP2 NP2
CARD-PUSH-46P-1-GP-U
B B
20.I0129.001
2nd = 20.I0135.001
XD_CD# XD_D7 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1
For EMI Reserved

1
1
R7417
R7402
R7404
R7403
R7406
R7405
R7408
R7407
R7410
R7409
R7412
R7411
R7414
R7413
R7416
R7415
47R2J-2-GP
47R2J-2-GP
47R2J-2-GP
47R2J-2-GP
47R2J-2-GP
47R2J-2-GP
47R2J-2-GP
47R2J-2-GP
47R2J-2-GP
47R2J-2-GP
47R2J-2-GP
47R2J-2-GP
47R2J-2-GP
47R2J-2-GP
47R2J-2-GP
47R2J-2-GP
DY DY DY DY DY DY DY DY DY DY DY DY DY DY DY DY
2
2
XD_D7_1
XD_CD#_1
SP14_1
SP13_1
SP12_1
SP11_1
SP10_1
SP9_1
SP8_1
SP7_1
SP6_1
SP5_1
SP4_1
SP3_1
SP2_1
SP1_1
SC220P50V2KX-3GP
SC220P50V2KX-3GP
SC220P50V2KX-3GP
SC220P50V2KX-3GP
SC220P50V2KX-3GP
SC220P50V2KX-3GP
SC220P50V2KX-3GP
SC220P50V2KX-3GP
SC220P50V2KX-3GP
SC220P50V2KX-3GP
SC220P50V2KX-3GP
SC220P50V2KX-3GP
SC220P50V2KX-3GP
SC220P50V2KX-3GP
SC220P50V2KX-3GP
SC220P50V2KX-3GP
1
1
EC7402
EC7403
EC7404
EC7405
EC7406
EC7407
EC7408
EC7409
EC7410
EC7411
EC7412
EC7413
EC7414
EC7415
EC7416
EC7417
A <Core Design> A
DY DY DY DY DY DY DY DY DY DY DY DY DY DY DY DY
2
2 Wistron Corporation
Title
CARD Reader CONN

A3
Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
D
Free Fall Sensor D
Note
- no via, trace, under the sensor (keep out area around 2mm)
- stay away from the screw hole or metal shield soldering joints
3D3V_S0 - design PCB pad based on our sensor LGA pad size (add 0.1mm)
- solder stencil opening to 90% of the PCB pad size
- mount the sensor near the center of mass of the NB as possible as you can
1
C7901 C7902
SC10U6D3V5MX-3GP DY SCD1U10V2KX-4GP
2
3D3V_S0
1
U7901
1
R7902
(14,15,20,65,82) PCH_SMBCLK 100KR2J-1-GP
DY
VDD_IO
VDD
(14,15,20,65,82) PCH_SMBDATA
3D3V_S0
2
PCH_SMBCLK 14 8 HDD_FALL_INT1
SCL/SPC INT1 HDD_FALL_INT1 (18)
1
3D3V_S0 PCH_SMBDATA 13 9 R7903
SDA/SDI/SDO INT2 100KR2J-1-GP
C For ADI G-sensor : R7901 is required. GSENSOR_ADIR7901HDD_FALL_SDO C
1 2 12 SDO
100KR2J-1-GP
For ST G-sensor : R7901 need DY
2
7 FALL_INT2
CS
GND 2
GND 4
3 RESERVED#3 GND 5
1
3D3V_S0 Q7901 5V_S0
2N7002KDW -GP
84.2N702.A3F
1
DE351DLTR8-GP
6
2nd = 84.DM601.03F R7906
10KR2J-3-GP
09/0422 74.00351.0B3 DYR7904
100KR2J-1-GP DY
(#1) Just pull +3.3V_RUN ~ Ref. Rothschild 2nd = 74.00345.0BZ
2
(#2) FAE/ DY is ok, chip internal pull-up resistors
FFS_INT2_R
(#3) From spec, Slave ADdress(SAD) is 001110xb FFS_INT2 (56)
Pull HIGH SAD is 0011101b
Pull GND SAD is 0011100b 1 2 R7905
DY 0R2J-2-GP
FFS_INT2_R (18)
B B
Note
(1) Keep all signals are the same trace width. (included VDD, GND).
(2) No VIA under IC bottom.
A <Core Design> A
Wistron Corporation
Title
Free Fall Sensor

A3
Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
IO Board CONN 80 pin
IOBD1
NP4 NP1
80 1
86%&/.
D (20) CLK_PCIE_USB3
(20) CLK_PCIE_USB3#
79
78
2
3
PCIE_TXP5
PCIE_TXN5
(20)
(20)
86%3&,( D
::$186% 77 4
(18) USB_PP4
(18) USB_PN4
76
75
5
6
PCIE_RXP5
PCIE_RXN5
(20)
(20)
86%3&,(
74 7
73
72
8
9
CLK_PCIE_LAN (20)
CLK_PCIE_LAN# (20)
/$1&/.
(38) PS_ID_R 71 10
70 11 CLK_PCIE_W W AN (20) ::$1&/.
::$13&,( (20) PCIE_RXP3
(20) PCIE_RXN3
69
68
12
13
CLK_PCIE_W W AN# (20)
67 14
::$13&,( (20) PCIE_TXP3
(20) PCIE_TXN3
66
65
15
16
5V_S5
64 17 at least 160 mil 5V_USB FOR USB3.0 POWER at least 4A
::$160%86
(14,15,20,65,79) PCH_SMBDATA
(14,15,20,65,79) PCH_SMBCLK
63
62
18
19
USB3_PW R_ON 61 20
(27,62) USB3_PW R_ON
60 21
3D3V_S0
1D05V_VTT FOR USB3.0 POWER at least ?A
1V_USB30 59 22
58 23
(62) 1V_USB30_LDO_FB
3D3V_S5 57 24 3D3V_S5 FOR LAN POWER at least over 3pin amount.
20101224 A00: 56 25
Change R8210 to 0402 0 ohm pad.
20101228 A00:
55 26
1D5V_S0
PM_LAN_ENABLE (27) 1D5V_S0 FOR USB3.0 POWER at least ?A
(20) CLK_PCIE_W W AN_REQ# 54 27 PLT_RST# (5,18,27,65,71,83)
20101229 A00: (22) 3G_EN 53 28 PCIE_W AKE# (27)
Remove R2809 and R8210. Connect USB3_PWR_ON from KBC to IOBD1.61. (68) W W AN_LED# 52 29 USB3_PEGB_CLKREQ# (20)
(18) USB30_SMI# 51 30
C 50 31 C
/$13&,( (20) PCIE_RXP2

(20) PCIE_RXN2
49
48
32
33
47 34
/$13&,( (20) PCIE_TXP2
(20) PCIE_TXN2
46
45
35
36
+DC_IN
44 37
(20) PCIE_CLK_LAN_REQ# 43 38
42 39
41 40
NP3 NP2
ACES-CONN80C-GP-U
20.F1432.080
B B
Media Button Board Connector

5V_S5
RN8209
MEDIA_LED1# 8 1 MEDIA1_1
MEDIA_LED2# 7 2 MEDIA1_2
MEDIA_LED3# 6 DY 3 MEDIA1_3
5 4
20110103 A00: INSTANT_ON#
Change R8201~R8203 to 1k. SRN10KJ-6-GP DATA_RECOVERY#
20110104 A00: MEDIA_BTN3#
Merge R8201~R8203 to RN8201 1k array resistor.
EC8208
EC8207
EC8206
EC8205
EC8204
EC8203
1
1
20110113 A00:
MEDIA1 DY DY DY DY DY DY
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
2
2
9 Low active
RN8201
1 5V_S5
4 5 MEDIA_LED1# (27)
2 MEDIA1_1 3 6 MEDIA_LED2# (27)
3 MEDIA1_2 2 7
A 4 MEDIA1_3 1 8 MEDIA_LED3# (27) <Core Design> A
5 5V_S5
INSTANT_ON# (27)
6 SRN1KJ-4-GP DATA_RECOVERY# (27)
AFTP8201 1 MEDIA1_1
7
8
MEDIA_BTN3# (27)
Wistron Corporation
1
AFTP8202 1 MEDIA1_2 EC8201 EC8202 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
AFTP8203 MEDIA1_3 Taipei Hsien 221, Taiwan, R.O.C.
1 10 DY DY
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
AFTP8204 1 5V_S5
2
AFTP8205 1 INSTANT_ON# Title

AFTP8206 1 DATA_RECOVERY#
AFTP8207 1 MEDIA_BTN3# ACES-CON8-19-GP
IO Board Connector Rev
20.K0320.008 A3 Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
(4) PEG_TXP[0..15] VGA1A 1 OF 7 PEG_RXP[0..15] (4) CONFIGURATION STRAPS RECOMMENDED SETTINGS

(4) PEG_TXN[0..15] 0= DO NOT INSTALL RESISTOR
PEG_RXN[0..15] (4)
ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED, 1 = INSTALL 3K RESISTOR
X = DESIGN DEPENDANT
THEY MUST NOT CONFLICT DURING RESET NA = NOT APPLICABLE
PLATFORM
PEG_TXP0 AF30 AH30 PEG_C_RXP0 C8301 1 2 SCD1U10V2KX-5GP PEG_RXP0 STRAPS PIN DESCRIPTION OF DEFAULT SETTINGS RECOMMEND
PEG_TXN0 AE31
PCIE_RX0P PCIE_TX0P
AG31 PEG_C_RXN0 C8302 1 2 SCD1U10V2KX-5GP PEG_RXN0
SETTING
PCIE_RX0N PCIE_TX0N
Transmitter Power Savings Enable
PEG_TXP1
TX_PWRS_ENB GPIO0 0: 50% Tx output swing 1: Full Tx output swing X 1
AE29 PCIE_RX1P PCIE_TX1P AG29 PEG_C_RXP1 C8303 1 2 SCD1U10V2KX-5GP PEG_RXP1
PEG_TXN1 AD28 AF28 PEG_C_RXN1 C8304 1 2 SCD1U10V2KX-5GP PEG_RXN1 PCIE TRANSMITTER DE-EMPHASIS ENABLED
PCIE_RX1N PCIE_TX1N
D TX_DEEMPH_EN GPIO1 0:Tx de-emphasis disabled 1:Tx de-emphasis enabled X 1 D
PEG_TXP2 AD30 AF27 PEG_C_RXP2 C8305 1 2 SCD1U10V2KX-5GP PEG_RXP2 0:Advertises the PCIe device as 2.5GT/s capable at power on.
PEG_TXN2 PCIE_RX2P PCIE_TX2P
AC31 PCIE_RX2N PCIE_TX2N AF26 PEG_C_RXN2 C8306 1 2 SCD1U10V2KX-5GP PEG_RXN2 BIF_GEN2_EN_A GPIO2 1:Advertises the PCIe device as 5.0GT/s capable at power on. 0 0
PEG_TXP3
optional input allow the system to request a fast
AC29 AD27 PEG_C_RXP3 C8308 1 2 SCD1U10V2KX-5GP PEG_RXP3 GPIO5_AC_BATT GPIO5 ? 0
PEG_TXN3 AB28
PCIE_RX3P PCIE_TX3P
AD26 PEG_C_RXN3 C8307 1 2 SCD1U10V2KX-5GP PEG_RXN3 power reduction by setting GPIO5 to low.
PCIE_RX3N PCIE_TX3N
PEG_TXP4
GPIO8_ROMSO GPIO8 RESERVED 0 0
AB30 PCIE_RX4P PCIE_TX4P AC25 PEG_C_RXP4 C8309 1 2 SCD1U10V2KX-5GP PEG_RXP4
PCI EXPRESS INTERFACE

PEG_TXN4 AA31 AB25 PEG_C_RXN4 C8310 1 2 SCD1U10V2KX-5GP PEG_RXN4 0:VGA Controller capacity enabled
PCIE_RX4N PCIE_TX4N
VGA_DIS GPIO9 1:The device won't be recognized as the system's VGA controller 0 0
PEG_TXP5 AA29 Y23 PEG_C_RXP5 C8311 1 2 SCD1U10V2KX-5GP PEG_RXP5 BIOS_ROM_EN=1, Config[2:0] defines the ROM type 0 0 1
Y28 Y24 PEG_C_RXN5 C8312 1 2 SCD1U10V2KX-5GP PEG_RXN5 ROMIDCFG[2:0] GPIO[13:11] BIOS_ROM_EN=0, Config[2:0] defines the primary memory aperture size X X X
PCIE_RX5N PCIE_TX5N (256MB)
PEG_TXP6 Y30 AB27 PEG_C_RXP6 C8313 1 2 SCD1U10V2KX-5GP PEG_RXP6 GPIO21_BB_EN GPIO21 RESERVED 0 0
W31 PCIE_RX6N PCIE_TX6N AB26 PEG_C_RXN6 C8314 1 2 SCD1U10V2KX-5GP PEG_RXN6
0:Disable external BIOS ROM device
BIOS_ROM_EN GPIO_22_ROMCSB X 0
PEG_TXP7
1:Enable external BIOS ROM device
W29 PCIE_RX7P PCIE_TX7P Y27 PEG_C_RXP7 C8316 1 2 SCD1U10V2KX-5GP PEG_RXP7
PEG_TXN7 V28 Y26 PEG_C_RXN7 C8315 1 2 SCD1U10V2KX-5GP PEG_RXN7 VIP Device Strap Enable indicates to the software driver that it sense
PCIE_RX7N PCIE_TX7N VIP_DEVICE_STRAP_EN X
V2SYNC whether or not a VIP device is connected on the VIP Host interface. 0
PEG_TXP8 V30 W24 PEG_C_RXP8 C8318 1 2 SCD1U10V2KX-5GP PEG_RXP8
U31 PCIE_RX8N PCIE_TX8N W23 PEG_C_RXN8 C8317 1 2 SCD1U10V2KX-5GP PEG_RXN8 RSVD H2SYNC RESERVED 0 0
C C
PEG_TXP9 U29 V27 PEG_C_RXP9 C8320 1 2 SCD1U10V2KX-5GP PEG_RXP9 RSVD GENERICC RESERVED 0 0
T28 PCIE_RX9N PCIE_TX9N U26 PEG_C_RXN9 C8319 1 2 SCD1U10V2KX-5GP PEG_RXN9
AUD[1] HSYNC X 1
PEG_TXP10 T30 U24 PEG_C_RXP10 C8321 1 2 SCD1U10V2KX-5GP PEG_RXP10 AUD[1:0]:11-Audio for both DisplayPort and HDMI
R31 PCIE_RX10N PCIE_TX10N U23 PEG_C_RXN10 C8322 1 2 SCD1U10V2KX-5GP PEG_RXN10
AUD[0] VSYNC X 1
PEG_TXP11 R29 T26 PEG_C_RXP11 C8323 1 2 SCD1U10V2KX-5GP PEG_RXP11
PEG_TXN11 PCIE_RX11P PCIE_TX11P PEG_C_RXN11 C8324
P28 PCIE_RX11N PCIE_TX11N T27 1 2 SCD1U10V2KX-5GP PEG_RXN11
PEG_TXP12 P30 T24 PEG_C_RXP12 C8325 1 2 SCD1U10V2KX-5GP PEG_RXP12 3D3V_VGA_S0 3D3V_VGA_S0

PEG_TXN12 PCIE_RX12P PCIE_TX12P PEG_C_RXN12 C8326
N31 T23 1 2 SCD1U10V2KX-5GP PEG_RXN12
PCIE_RX12N PCIE_TX12N PIN STRAPS
R8324
PEG_TXP13 N29 P27 PEG_C_RXP13 C8328 1 2 SCD1U10V2KX-5GP PEG_RXP13 1 2 10KR2J-3-GP
PEG_TXN13 M28
PCIE_RX13P PCIE_TX13P
P26 PEG_C_RXN13 C8327 1 2 SCD1U10V2KX-5GP PEG_RXN13
(85) JTAG_TMS_VGA DY
PCIE_RX13N PCIE_TX13N R8301 3KR2J-2-GP R8328
(85) TX_PW RS_ENB 1 2
2 1 10KR2J-3-GP
PEG_TXP14 M30 P24 PEG_C_RXP14 C8330 1 2 SCD1U10V2KX-5GP PEG_RXP14 (85) TX_DEEMPH_EN R8302 1 2 3KR2J-2-GP DY
L31 PCIE_RX14N PCIE_TX14N P23 PEG_C_RXN14 C8329 1 2 SCD1U10V2KX-5GP PEG_RXN14 (84) TESTEN
(85) BIF_GEN2_EN_A R8303 1 2 10KR2J-3-GP R8327
1 2 5K11R2F-L1-GP
PEG_TXP15 L29 M27 PEG_C_RXP15 C8332 1 2 SCD1U10V2KX-5GP PEG_RXP15 R8304 1 2 10KR2J-3-GP
PEG_TXN15 K30
PCIE_RX15P PCIE_TX15P
N26 PEG_C_RXN15 C8331 1 2 SCD1U10V2KX-5GP PEG_RXN15
(85) GPIO8_ROMSO DY
PCIE_RX15N PCIE_TX15N R8305 1 2 10KR2J-3-GP R8322 1 DY 2 10KR2J-3-GP
(85) VGA_DIS DY (85) JTAG_TRST#_VGA
B R8323 1 B
(20,85) JTAG_TCK_VGA 2 10KR2J-3-GP
CLOCK R8306 1 2 10KR2J-3-GP
(85) CONFIG0
AK30
(20) CLK_PCIE_VGA
AK32
PCIE_REFCLKP R8307 1 2 10KR2J-3-GP
DY
(20) CLK_PCIE_VGA# PCIE_REFCLKN (85) CONFIG1 DY
1V_VGA_S0 R8308 1 2 10KR2J-3-GP
CALIBRATION
(85) CONFIG2 DY
PCIE_CALRP Y22 PCIE_CALRP 1 2 (50,85) VGA_CRT_VSYNC
R8309 1 DY 2 10KR2J-3-GP JTAG SIGNAL OPTION
R8326 1K27R2F-L-GP
1 2 PW RGOOD N10 AA22 PCIE_CALRN 1 2 R8310 1 DY 2 10KR2J-3-GP Normal Debug pilot run
PWRGOOD PCIE_CALRN (50,85) VGA_CRT_HSYNC
R8317 10KR2F-2-GP R8318 2KR2F-3-GP Signal mode mode mode
VGA_RST# AL27
PERST# R8311 1
DY 2 10KR2J-3-GP TESTEN "1"(PU) "1"(PU) "0"(PD)
Colay with Seymour-XT-S3 (85) VSYNC_DAC2
1
C8333
DY SC47P50V2JN-3GP 71.ROBSO.M01 (71.SEYMR.M01) R8312 1
DY 2 10KR2J-3-GP
ROBSON-GP-U (85) HSYNC_DAC2
JTAG_TRST# "0"(PD) "1"(PU) NC
2
R8313 1 2 10KR2J-3-GP
(85) BIOS_ROM_EN DY
R8314 1
DY 2 10KR2J-3-GP JTAG_TCK CLK "1"(PU) NC
dGPU reset for PX/SG transitions (85) GPIO5_AC_BATT
R8315 1
DY 2 10KR2J-3-GP
(85) GPIO21_BB_EN
20101224 A00:
JTAG_TMS "1"(PU) "1"(PU) NC
(5,18,27,65,71,82) PLT_RST# 1 R8321 2 VGA_RST#
0R2J-2-GP Change R8316 to 0402 0 ohm pad. PE_GPIO0
DY
dGPU mode H
1 R8316 2
A 0R0402-PAD IGPU L <Core Design> A
R8319 U8302 3D3V_VGA_S0
PLT_RST# 3D3V_VGA_S0
(86) 1D5V_VGA_PW OK 2 DY 1
0R2J-2-GP
1 B
U8303
VCC 5 (18) DGPU_HOLD_RST# 1 B IGPU with BACO H Wistron Corporation
1D8V_S0_VGA_PG_1 2 5
R8325 1 A U8301_Y VCC 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
(93) 1D8V_S0_VGA_PG 2 DY Y 4 2 A VGA_RST# Taipei Hsien 221, Taiwan, R.O.C.
DY 3 GND DY Y 4 VGA_RST# (85)
1
0R2J-2-GP C8334 3
SCD1U10V2KX-4GP 74LVC1G08GW -1-GP GND Title
DY 73.01G08.L04 74LVC1G08GW -1-GP
GPU_PEG/STRAPPING(1/5)
2
73.01G08.L04
A3 Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
VGA1C 3 OF 7
(88) DQA0_[31..0]
MAA0_8 MAA0_[8..0] (88)
DQA0_0 K27 K17 MAA0_0
DQA0_1 DQA_0 MAA_0 MAA0_1
J29 J20
H30 H23
H32 G23
G29 G24
F28 H24
MEMORY INTERFACE
F32 J19
F30 K19
DQA0_8 DQA_7 MAA_7 MAA1_0 MAA1_[8..0] (88)
C30 J14
F27 K14
A28 J11
C28 J13
D E27 H11 D
G26 G20
D26 J16
DQA0_15 DQA_14 MAA_14/BA0 MAA1_7
PLACE MVREF DIVIDERS AND CAPS CLOSE TO ASIC DQA0_16
F25
DQA_15 MAA_15/BA1
L15
MAA1_5
A25 G11
DQA0_17 DQA_16 MAA_BA2 MAA1_8
C25
DQA0_18 DQA_17
E25 E32 WCKA0_0 (88)
DQA0_19 DQA_18 DQMA_0
D24 E30 WCKA0_0# (88)
1D5V_VGA_S0 1D5V_VGA_S0 DQA0_20 DQA_19 DQMA_1
E23 A21 WCKA0_1 (88)
F23 C21 WCKA0_1# (88)
D22 E13 WCKA1_0 (88)
1
1
Ra Ra F21
DQA_23 DQMA_5
D12 WCKA1#_0 (88)
R8410 R8411 DQA0_24 E21 E3
40D2R2F-GP 40D2R2F-GP DQA_24 DQMA_6 WCKA1_1 (88)
DQA0_25 D20 F4
DQA0_26 DQA_25 DQMA_7 WCKA1#_1 (88)
F19
DQA0_27 DQA_26
A19 H28
2
2
DQA_27 RDQSA_0 EDCA0_0 (88)
MVREFDA MVREFSA DQA0_28 D18 C27
DQA0_29 F17 A23 EDCA0_2 (88)
1
1
C8402 C8403 DQA0_30 DQA_29 RDQSA_2
Rb Rb A17
DQA_30 RDQSA_3
E19 EDCA0_3 (88)
R8414 SCD1U10V2KX-5GP R8415 SCD1U10V2KX-5GP DQA0_31 C17 E15
100R2F-L1-GP-U 100R2F-L1-GP-U (88) DQA1_[31..0] DQA_31 RDQSA_4 EDCA1_0 (88)
DQA1_0 E17 D10
2
2
DQA1_1 DQA_32 RDQSA_5 EDCA1_1 (88)
D16 D6 EDCA1_2 (88)
DQA1_2 DQA_33 RDQSA_6
F15 G5
2

DQA1_3 A15
DQA1_4 DQA_35
D14 H27 DDBIA0_0 (88)
DQA1_5 DQA_36 WDQSA_0
F13 A27
DDR3/GDDR3 Memory Stuff Option (ROBSON-S3/SEYMOUR-XT-S3) DQA1_6 A13
DQA_37
DQA_38
WDQSA_1
WDQSA_2
C23
DDBIA0_1
DDBIA0_2
(88)
(88)
DQA1_7 C13 C19
DQA_39 WDQSA_3 DDBIA0_3 (88)
DQA1_8 E11 C15
DDR5 DDR3 DQA1_9 A11 E9
DQA1_10 C11 C5
DQA1_11 DQA_42 WDQSA_6 DDBIA1_2 (88)
F11 H4 DDBIA1_3 (88)
DQA1_12 DQA_43 WDQSA_7
MVDDQ 1.5V 1.5V/1.8V A9
DQA_44
DQA1_13 C9 L18
DQA_45 ODTA0 ADBIA0 (88)
DQA1_14 F9 K16
DQA_46 ODTA1 ADBIA1 (88)
Ra 40.2R 40.2R DQA1_15 D8
DQA1_16 DQA_47
E7 H26
DQA1_17 DQA_48 CLKA0 CLKA0 (88)
A7 H25
DQA1_18 DQA_49 CLKA0# CLKA0# (88)
Rb 100R 100R C7
DQA_50
DQA1_19 F7 G9
DQA1_20 DQA_51 CLKA1 CLKA1 (88)
A5 H9
DQA1_21 DQA_52 CLKA1# CLKA1# (88)
C E5 C
DQA1_22 DQA_53
C3 G22
DQA1_23 DQA_54 RASA0# RASA0# (88)
E1 G17
DQA1_24 DQA_55 RASA1# RASA1# (88)
G7
DQA1_25 DQA_56
G6 G19
DQA1_26 DQA_57 CASA0# CASA0# (88)
G1 G16
DQA1_27 DQA_58 CASA1# CASA1# (88)
1D5V_VGA_S0
DPC_CALR (Park/Robson-S3): G3
DQA_59
DQA1_28 J6 H22
Analog calibration. DQA1_29 J1
DQA_60 CSA0#_0
J22
CSA0#_0 (88)
Connect DPxx_CALR to GND through a 150-ȍ (1%) resistor. DQA1_30 DQA_61 CSA0#_1
J3
DQA1_31 DQA_62
J5 G13
150R2F-1-GP DQA_63 CSA1#_0 CSA1#_0 (88)
K13
CSA1#_1
R8403 1 2 243R2F-2-GP MEM_CALRN0 R8407 1 2 MVREFDA K26
MEM_CALRP0 MVREFSA MVREFDA 20101227 A00:
1 2 J26 K20
R8408 243R2F-2-GP MVREFSA CKEA0 CKEA0 (88) Change R8409 to 0R 0402 pad.
Must be tied to ground (0 V) through a MEM_CALRN0 J25 CKEA1
J17
CKEA1 (88)
1-k to 10-k resistor for normal ASIC operation TESTEN MEM_CALRN0
(83) TESTEN K7 G25
TESTEN WEA0# WEA0# (88)
H10 R8409
MEM_CALRP1/DPC_CALR J8 WEA1# WEA1# (88)
MEM_CALRP0 K25 MEM_CALRP1/DPC_CALR PX_EN_R
AB16 1 2 PX_EN (86)
R8405 R8402 MEM_CALRP0 PX_EN
2
(88) MEM_RST 1 2DRAM_RST_1 1 2 DRAM_RST L10 0R0402-PAD
51R2J-2-GP 10R2J-2-GP DRAM_RST R8412
R_MEM_2 R_MEM_1 TP8401 1CLKTESTA K8 G14 MAA1_8 10KR2J-3-GP
1
CLKTESTA RSVD#G14
** This basic topology should be used for DRAM_RST for TP8402 1CLKTESTB L7
2
C8401 R8404 CLKTESTB

DDR3/GDDR3/GDDR5.These Capacitors and Resistor values
1
C_MEM 5K1R2F-2-GP
are an example only. The Series R and || Cap values ROBSON-GP-U
R_MEM_3
SC120P50V2JN-1GP
1
will depend on the DRAM load and will have to be

71.ROBSO.M01
2
calculated for different Memory ,DRAM Load and board

to pass Reset Signal Spec.
Colay with Seymour-XT-S3
(71.SEYMR.M01)
Designator For SEYMOUR For Robson Place all these components very close to GPU
(Within 25mm) and keep all component close
to each Other (within 5mm) except R_MEM_2
R_MEM_1 10R 10R
B B
R_MEM_2 50R 50R
R_MEM_3 5K 5K
C_MEM 120pF 120pF
A A
<Core Design>
Wistron Corporation
Title
GPU Memory(2/5)
A2 Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
MEMORY ID Table LVDS Interface

VGA1B 2 OF 7
DVPDATA[0:3] Description VGA1F 6 OF 7
0001 GDDR5 1.25GHZ Hynix-H5GQ2H24MFR-T2C 64M*32 M93-S3/M92-S2 TXCAP_DPA3P

AF2 HDMI_CLK (51)
AE9 AF4 HDMI_CLK# (51)
DVCNTL_0/DVPDATA_18 TXCAM_DPA3N LVDS CONTROL
L9 AB11
DVCNTL_1/NC#L9 VARY_BL
0000 GDDR5 1.25GHZ SAMSUNG-K4G20325FC-HC04 64M*32 N9
DVCNTL_2/TESTEN#2 TX0P_DPA2P
AG3 HDMI_DATA0 (51) DIGON
AB12
AE8
DVDATA_12/DVPDATA_16 DPA TX0M_DPA2N
AG5 HDMI_DATA0# (51)
AD9
DVDATA_11/DVPDATA_20
AC10 AH3 HDMI_DATA1 (51)
DVDATA_10/DVPDATA_22 TX1P_DPA1P
AD7 AH1 HDMI_DATA1# (51)
DVDATA_9/DVPDATA_12 TX1M_DPA1N
AC8 AH20
DVDATA_8/DVPDATA_14 TXCLK_UP_DPF3P
AC7 AK3 HDMI_DATA2 (51) AJ19
DVDATA_7/DVPCNTL_0 TX2P_DPA0P TXCLK_UN_DPF3N
AB9 AK1 HDMI_DATA2# (51)
DVDATA_6/DVPDATA_8 TX2M_DPA0N
DVPDATA[0:3] Default:Pull down AB8
DVDATA_5/DVPDATA_6 TXOUT_U0P_DPF2P
AL21
AB7 AK5 AK20
1D8V_VGA_S0 DVDATA_4DVPDATA_4 TXCBP_DPB3P TXOUT_U0N_DPF2N
For Seymour, AB4
DVDATA_3/DVPDATA_19 TXCBM_DPB3N
AM3
DPC_PVDD is DPC_VDD18 R8519 1
DY AB2
DVDATA_2/DVPDATA_21 TXOUT_U1P_DPF1P
AH22
2 10KR2J-3-GP MEM_ID1 Y8 AK6 AJ21
DVDATA_1/DVPDATA_2 TX3P_DPB2P TXOUT_U1N_DPF1N
DPC_PVSS and all DPC_VSSR are DP_VSSR MEM_ID Control R8518 1 2 10KR2J-3-GP MEM_ID0 Y7
DVDATA_0/DVPDATA_0 TX3M_DPB2N
AM5
Hynix_512 DPB 3D3V_VGA_S0 AL23
TXOUT_U2P_DPF0P
AJ7 AK22
TX4P_DPB1P TXOUT_U2N_DPF0N
DVO TX4M_DPB1N
AH6
AK24
D TXOUT_U3P D
AK8 AJ23
1D8V_VGA_S0 TX5P_DPB0P TXOUT_U3N
AL7
THERMTRIP_R
TX5M_DPB0N
4
3
20101224 A00 Modify:
un-stuff THERMTRIP_VGA P.87 M93-S3/M92-S2 RN8504 LVTMDP
related circuit at A00 stage for W6 SRN4K7J-8-GP
fixed auto shut down issue. THERMTRIP_VGA DPC_PVDD/DVPDATA_11
V6
DPC_PVSS/GND M92-S2/M93-S3 TXCLK_LP_DPE3P
AL15
1
V4 AK14
R8522 1V_VGA_S0 DVPDATA_3/TXCCP_DPC3P TXCLK_LN_DPE3N
AC6 U5
1
2
DPC_VDD18#1/DVPDAT10 DVPCNTL_2/TXCCM_DPC3N Q8503
10KR2J-3-GPDY AC5 AH16
DPC_VDD18#2/DVPDAT23 GPIO_VGA_04_CLK TXOUT_L0P_DPE2P
W3 1 6 SML1_CLK (20,27) AJ15
L8507 DVPDATA_7/TX0P_DPC2P TXOUT_L0N_DPE2N
(1.0V@110mA DPC_VDD10) AA5 V2
2
DPC_VDD10#1/DVPDAT15 DVPDATA_1/TX0M_DPC2N
6
1 2 DPC_VDD10 AA6 2 5 AL17

Q8501 0R0402-PAD-2-GP DPC_VDD10#2/DVPDAT17 TXOUT_L1P_DPE1P
Y4 AK16
DVPCNTL_MV1/TX1P_DPC1P TXOUT_L1N_DPE1N
2N7002KDW-GP DY W5 3 4
SC1U6D3V2KX-GP
SC10U6D3V5KX-1GP
SCD1U10V2KX-5GP
DVPDATA_9/TX1M_DPC1N
C8526
C8527
C8528
AH18
84.2N702.A3F TXOUT_L2P_DPE0P
1
U1 AA3 AJ17
1
2nd = 84.DM601.03F DPC_VSSR#1/DVPCLK DVPDATA_13/TX2P_DPC0P 2N7002KDW-GP TXOUT_L2N_DPE0N

DY DY W1
DPC_VSSR#2/DVPDAT5 DVPCNTL_1/TX2M_DPC0N
Y2
84.2N702.A3F SML1_DATA (20,27)
U3 AL19
2
DPC_VSSR#3/GND GPIO_VGA_03_DATA TXOUT_L3P
Y6
DPC_VSSR#4/GND NC#AA12
AA12 2nd = 84.DM601.03F TXOUT_L3N
AK18
Q5801_2
AA1
DPC_VSSR#5/DVPCNTL_MV0
(27,28,36) PURE_HW_SHUTDOWN#
R8521
(83) VGA_RST# 2 DY 1
20100105 A00:
DPC ROBSON-GP-U
1
0R2J-2-GP C8529 Change L8507 to 0 ohm short pad, un-stuff C8526,C8527.

DY SCD1U10V2KX-4GP 71.ROBSO.M01
R1
2
SCL
R3
SDA I2C
AM26 VGA_CRT_RED (50)
GENERAL PURPOSE I/O R
AK26
R#
(83) TX_PWRS_ENB U6
GPIO_0
(83) TX_DEEMPH_EN U10 AL25 VGA_CRT_GREEN (50)
GPIO_1 G
(83) BIF_GEN2_EN_A T10 AJ25
GPIO_VGA_03_DATA GPIO_2 G#
1 U8
TP8517 TPAD14-GP GPIO_VGA_04_CLK GPIO_3_SMBDATA
1 U7 AH24 VGA_CRT_BLUE (50)
TP8512 TPAD14-GP GPIO_4_SMBCLK B 1D8V_VGA_S0 AVDD_A2VDDQ
(83) GPIO5_AC_BATT T9 AG25
TPAD14 TP8505 GPIO6_VGA GPIO_5_AC_BATT B#
1 T8
GPIO_6 DAC1 (1.8V@65mA AVDD)
1 R8523 2 VGA_BLEN T7 AH26 VGA_CRT_HSYNC (50,83) 1 2
10KR2J-3-GP GPIO_7_BLON HSYNC R8507 0R0603-PAD
(83) GPIO8_ROMSO P10 AJ27 VGA_CRT_VSYNC (50,83)
GPIO_8_ROMSO VSYNC
1
P4 C8503 C8504
SCD1U10V2KX-5GP
(83) VGA_DIS GPIO_9_ROMSI
TPAD14 TP8510 1 GPIO_10_ROMSCK P2 C8501 DY DY
GPIO_10_ROMSCK GPU_RSET SC4D7U6D3V3KX-GP SC1U6D3V2KX-GP
(83) CONFIG0 N6 AD22 1 2
2
GPIO_11 RSET AVDD_A2VDDQ R8514 499R2F-2-GP
(83) CONFIG1 N5
GPIO_12
(83) CONFIG2 N3 AG24
GPIO_13 AVDD AVSSQ
Y9 AE22
PWRCNTL_0 GPIO_14_HPD2 AVSSQ AVDD_A2VDDQ
(92) PWRCNTL_0 N1
TPAD14 TP8502 GPIO16_SSIN GPIO_15_PWRCNTL_0 AVDD_A2VDDQ
1 M4 AE23
R8503 2 GPIO17_VGA GPIO_16_SSIN VDD1DI AVSSQ
3D3V_VGA_S0 1 R6
GPIO_17_THERMAL_INT VSS1DI
AD23 (1.8V@100mA VDD1DI)
10KR2J-3-GP TPAD14 TP8507 1 GPIO18_VGA W10
THERMTRIP_VGA GPIO_18_HPD3 20101224 A00:
M2
GPIO_19_CTF M92-S2/M93-S3
1
PWRCNTL_1 P8 AM12 Change R8506,R8509 to 0402 0 ohm pad. C8506 C8507
SC1U6D3V2KX-GP
GPIO_6,GPIO_15_PWRCNTL_0,GPIO_16_SSIN,GPIO_20_PWRCNTL_1: (92) PWRCNTL_1 GPIO_20_PWRCNTL_1 R2/NC#AM12 Change R8507 to 0603 0 ohm pad.
(83) GPIO21_BB_EN P7 AK12 C8502 DY DY SCD1U10V2KX-5GP
Voltage control signals for the core (VDDC and VDDCI). GPIO_21_BB_EN R2#/NC#AK12 SC4D7U6D3V3KX-GP
(83) BIOS_ROM_EN N8
2
At Reset, these signals will be inputs with weak internal pull-down resistors. GPIO_22_ROMCSB
(20) PEG_CLKREQ# N7 AL11
VBIOS can define all voltage control signals to be either 3.3-V or open drain outputs (all signals GPIO_23_CLKREQB G2/NC#AL11 R8506 1
AJ11 2
must be the same type). The output state (high/low) of these signals is programmable for each PowerPlay state. G2#/NC#AJ11 0R0402-PAD
AK10
C B2/NC#AK10 C
(83) JTAG_TRST#_VGA L6 AL9
TP8501 JTAG_TDI_VGA JTAG_TRST# B2#/NC#AL9 AVSSQ AVDD_A2VDDQ
1 L5
Rev 3.05 (June 2010) JTAG_TDI
(20,83) JTAG_TCK_VGA L3
JTAG_TCK (1.8V@50mA VDD2DI)
Renamed the Park/Robson-S3 AF24 ball from TESTEN to RSVD. L1 AH12
(83) JTAG_TMS_VGA JTAG_TMS C/NC#AH12
TP8503 1 JTAG_TDO_VGA K4 DAC2 AM10
JTAG_TDO Y/NC#AM10
1
TP8506 1 RSVD AF24 AJ9 C8508 C8509
RSVD#AF24 COMP/NC#AJ9
TP8504 GEN_A SCD1U10V2KX-5GP
DY DY SC1U6D3V2KX-GP
1 AB13
2
1D8V_VGA_S0 TP8508 GEN_B GENERICA
1 W8 AL13 HSYNC_DAC2 (83)
GENERICB H2SYNC
W9 AJ13 VSYNC_DAC2 (83)
GENERICC V2SYNC
W7
GENERICD
1
PLACE VREFG DIVIDER AND CAP TP8509 1 GENERICE_HPD4 AD10 50 mA DY

GENERICE_HPD4 VDD2DI_GPU R8504 2
CLOSE TO ASIC R8515 AD19 1 0R2J-2-GP AVDD_A2VDDQ AVDD_A2VDDQ
20101230 A00: 499R2F-2-GP HDMI_HPD_DET VDD2DI/NC#AD19 AC19_GND 1DY
(51) HDMI_HPD_DET AC14 AC19 2
Change R8512 to 0R0603 short pad. HPD1 VSS2DI/NC#AC19
(1.8V@1.5mA A2VDDQ)
1D8V_VGA_S0 DPLL_PVDD R8520 0R2J-2-GP 130 mA DY
2
R8512 (1.8V@75mA DPLL_PVDD) GPU_VREFG AE20 A2VDD_GPU R8508 2 1 0R2J-2-GP
SC1U6D3V2KX-GP
A2VDD/NC#AE20 A2VDD
1
C8510 C8511 20100105 A00:
1.5 mA DY
1
A2VDDQ_GPU R8505 2 1 0R2J-2-GP Un-stuff C8501 C8502 C8504 C8506 C8511

2 1
A2VDDQ/NC#AE17
AE17 AVDD_A2VDDQ DY
1
0R0603-PAD R8516 C8514 AC16 SCD1U10V2KX-5GP
2
VREFG
1
C8515 C8516 249R2F-GP SCD1U10V2KX-5GP AE19

SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
A2VSSQ
1
C8505 DY
2
SC4D7U6D3V3KX-GP R8501
2
AG13 R2SET 1 DY 2
2
R2SET/NC#AG13 A2VDD
715R2F-GP 3D3V_VGA_S0
M92-S2/M93-S3 M92-S2/M93-S3 (3.3V@130mA A2VDD)
AE6 VGA_CRT_DDCCLK (50) 2 R8509 1
PLL/CLOCK DDC1CLK 0R0402-PAD
DDC1DATA
AE5 VGA_CRT_DDCDATA (50) DDC1 channel for CRT
1
AF14 C8512 C8513
SC1U6D3V2KX-GP
DPLL_PVDD SCD1U10V2KX-5GP
1V_VGA_S0 DPLL_VDDC
AE14
DPLL_PVSS AUX1P
AD2 DY DY
AD4
2
L8506 DDC/AUX AUX1N
(1.0V@125mA DPLL_VDDC)
1 2 AD14 AC11 GPU_HDMI_CLK (51)
BLM18PG471SN1D-GP DPLL_VDDC DDC2CLK
DDC2DATA
AC13 GPU_HDMI_DATA (51) DDC2 channel for HDMI
68.00143.181 C8517
1
C8518 C8519 R8525 XTALIN_R AM28 AD13

XTALIN_R XTALOUT_R XTALIN AUX2P
2nd = 68.00214.211 DY 1 DY 2 AK28 AD11
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
0R2J-2-GP XTALOUT AUX2N

DDC1/DDC2/DDC6 have 5V-tolerant
2
SC4D7U6D3V3KX-GP AE16
DDCCLK_AUX5P
AD16
R8517 1 DDCDATA_AUX5N
DY 2 0R2J-2-GP XO_IN AC22
R8526 1 NC#AC22/XO_IN
DY 2 0R2J-2-GP XO_IN2 AB22 AC1
NC#AB22/XO_IN2 DDC6CLK
AC3
DDC6DATA
AD20
NC#AD20/DDCCLK_AUX3P
1
AC20
C8523 THERMAL NC#AC20/DDCDATA_AUX3N
20101227 A00: SC2200P50V2KX-2GP
DY P2800_VGA_DXP T4
2
Change R8524 to 0R 0402 pad. P2800_VGA_DXN DPLUS

T2
1D8V_VGA_S0 DMINUS
TSVDD
R8524
TP8511 1 FAN_PWM_C R5
TS_FDO
1 2 (1.8V@20mA TSVDD) AD17
TSVDD
20110112 A00: AC17
Change C8524,C8525 to 18pF from 12pF base on vendor's report. 0R0402-PAD TSVSS
1
C8521 C8522 ROBSON-GP-U

R8511
C8520
DY SC1U6D3V2KX-GP SCD1U10V2KX-5GP
B SC4D7U6D3V3KX-GP
71.ROBSO.M01 B
1 DY 2
2
1MR2F-GP
Colay with Seymour-XT-S3 1Mbit SERIAL EEPROM is optional for Seymour GDDR5 Design
(71.SEYMR.M01)
1Mbit SERIAL EEPROM is required for Park/Robson GDDR5 Design
X8501
C8524
1 2 XTAL_X1 1 4 NOTE: Designs that do not include an EEPROM must still provide
Clock Input Configuraiton -GDDR3/DDR3 access to the ROM interface signals for debug purposes
SC18P50V2JN-1-GP C8525
2 3 XTAL_X2 1 2 a) 27MHz crystal connected to XTALIN or XTALOUT or
SC18P50V2JN-1-GP
b) 27MHz (1.8V) oscillator connected to XTALIN or
XTAL-27MHZ-85-GP c) 27MHz (3.3V) oscillator connected to XO_IN (Park, Madison, and Broadway only)
82.30034.641
2nd = 82.30034.651 Clock Input Configuration -GDDR5 with Park, Robson and Seymour
3rd = 82.30034.681 a) 27MHz (3.3V) oscillator connected to XO_IN, AND
The value (in pF) of these crystal caps should equal (CL -6
pF)*2. In this equation, CL= crystal load capacitance in pF. b) 100MHz (3.3V) oscillator (no spread or spread) connected to XO_IN2
For X8501 with 12 pF load capacitance, each
crystal capacitor would be 12 pF [(12-6) x 2 = 12].
1
C8533
DY2 SC1U6D3V2KX-GP
1 2
20110105 A00: C8532 SCD1U10V2KX-5GP 1 2
Un-stuff C8536,C8533,C8534 and change L8501 to 0 ohm short pad. 1 DY2 R8527 DY 150R2F-1-GP
C8534 SC1U6D3V2KX-GP 1 2 XTALIN_R 1.8V
1 2 R8529 DY 124R2F-U-GP
3D3V_S0 L8501 C8535 SCD1U10V2KX-5GP U8606
1 2 3D3V_S0_U8606 4 9 CLK_27R 1 2 XO_IN 3.3V

0R0603-PAD VDD_100M 27M R8502 47R2J-2-GP
8
VDD_27M
1
C8536 5 CLK_100R 1 2 XO_IN2 3.3V

SC10U6D3V5KX-1GP 100M R8510 33R2J-2-GP
DY XTAL_X1 1
2
3D3V_S0 XTAL_X2 XIN

10
XOUT
2
A SS_SEL0 GND_27M A
R8531 1
1 DY 2 7
SS_SEL0 GND_100M
6
DY 2 10KR2J-3-GP SS_SEL1 3 11
R8532 10KR2J-3-GP SS_SEL1 GND
1
R8528 R8530 6V40088DNBGI8-GP

10KR2J-3-GP 10KR2J-3-GP
71.64088.003
2
<Core Design>
Wistron Corporation
Title
GPU_DP/LVDS/CRT/GPIO(3/5)
A1
Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
1D5V_VGA_S0
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
C8606
C8607
C8608
C8609
C8610
C8611
C8612
1
1
VGA1D 4 OF 7 1D8V_VGA_S0
MEM I/O
2
PCIE (1.8V@504mA PCIE_VDDR)
H13 AB23
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SC4D7U6D3V3KX-GP
VDDR1 PCIE_VDDR
C8613
C8615
C8616
C8729
H16 AC23
VDDR1 PCIE_VDDR
1
H19 AD24
VDDR1 PCIE_VDDR
J10 AE24
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
VDDR1 PCIE_VDDR
J23 AE25
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
2
VDDR1 PCIE_VDDR
C8621
C8622
C8623
C8624
C8625
C8626
C8627
J24 AE26
VDDR1 PCIE_VDDR
1
J9 AF25
VDDR1 PCIE_VDDR 1V_VGA_S0
K10 AG26
VDDR1 PCIE_VDDR
K23
2
2
VDDR1
K24
VDDR1 (1.0V@1920mA PCIE_VDDC)
K9 L23
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC4D7U6D3V3KX-GP
VDDR1 PCIE_VDDC
C8628
C8629
C8630
C8631
C8632
C8633
C8602
C8730
L11 L24
VDDR1 PCIE_VDDC
1
L12 L25
VDDR1 PCIE_VDDC
L13 L26
SC22U6D3V5MX-2GP
SC10U6D3V5KX-1GP
D VDDR1 PCIE_VDDC D
C8697
C8698
L20 M22
2
VDDR1 PCIE_VDDC
1
1
L21 N22
VDDR1 PCIE_VDDC
L22 N23
VDDR1 PCIE_VDDC
N24
2
PCIE_VDDC
R22
PCIE_VDDC
T22
1D8V_VGA_S0 VDDC_CT LEVEL PCIE_VDDC
U22
TRANSLATION PCIE_VDDC
V22
PCIE_VDDC VGA_CORE
AA20
VDD_CT
R8605 AA21
VDD_CT
(1.8V@110mA VDD_CT) AB20 AA15
SCD1U10V2KX-5GP SC1U6D3V2KX-GP SC1U6D3V2KX-GP
SC1U6D3V2KX-GP SC1U6D3V2KX-GP SC1U6D3V2KX-GP
SC1U6D3V2KX-GP SC1U6D3V2KX-GP
SC4D7U6D3V3KX-GP
VDD_CT CORE VDDC
C8650
C8664
C8638
C8639
C8640
C8641
C8642
C8644
1 2 AB21 N15
VDD_CT VDDC
C8699
C8652
C8653
N17
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP SCD1U10V2KX-5GP
VDDC
1
1
0R0402-PAD M93-S3/M92-S2 R13
POWER
VDDC
VDDC
R16 DY
AA17 R18
2
2
20101227 A00: VDDR3 VDDC
AA18
VDDR3 I/O VDDC
Y21
AB17 T12
VDDR3 VDDC
AB18 T15
SC1U6D3V2KX-GP
VDDR3 VDDC
C8646
C8649
C8665
C8669
C8647
C8670
C8645
C8648
C8672
C8675
C8671
3D3V_VGA_S0 T17
SC4D7U6D3V3KX-GP
VDDC
V12 T20
VDDR4/VDDR5 VDDC
1
C8700
C8666
C8667 Y12 U13

SC1U6D3V2KX-GP
VDDR4 VDDC
1
U12 U16
VDDR4/VDDR5 VDDC
U18
2
VDDC
AA11 V21
2
NC#AA11/VDDR4 VDDC
Y11 V15
DVCLK/VDDR4 VDDC
V17
VDDC
C8677
V11 V20
NC#V11/VDDR5 VDDC
C8679
C8680
C8676
U11 Y13
NC#U11 VDDC
1
Y16 BIF_VDDC
SCD1U10V2KX-5GP VDDC
Y18
VDDC
C8673
C8674
R21
SC1U6D3V2KX-GP
2
VDDC/BIF_VDDC
U21
VDDC/BIF_VDDC
1
MEM CLK
MPV18
55mA in BACO mode
L8604 L17
VDDRHA
(Park: 1.8V@75mA MPV18)
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC4D7U6D3V3KX-GP
ISOLATED
C8733
C8735
C8736
1 2 L16
VSSRHA
1
CORE I/O
C8722
C8716
C8690
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
1
BLM15BD121SS1D-GP MPV18 M13 DY

PLL VDDCI
68.00084.F81 M15
2
VDDCI
2ND = 68.00217.701 AM30 M16
2
MPV18 PCIE_PVDD VDDCI

M17
VDDCI
M18
VDDCI
L8 M20
1V_VGA_S0 SPV18 MPV18 VDDCI
M21
VDDCI
N20
VDDCI
H7
L8606 SPV18
(1.8V@75mA SPV18)
1 2 SPV10 H8
BLM15BD121SS1D-GP SPV10 VGA_CORE
SC4D7U6D3V3KX-GP
C8724
C8727
C8728
68.00084.F81 J7 (GDDR3/DDR3 1.12V@4A VDDCI)

SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SPVSS
1
2ND = 68.00217.701
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SCD1U16V2KX-3GP
C8657
C8655
C8656
C8659
C8660
C8658
2
1
BACK BIAS
SPV18 M11
L8605 BBP#1
(1.8V@75mA SPV18) M12
2
BBP#2 BIF_VDDC
1 2
SC4D7U6D3V3KX-GP
C C
C8723
C8692
C8694
VGA_CORE
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
1
BLM15BD121SS1D-GP
68.00084.F81
1
M11_M12 ROBSON-GP-U C8601 20101229 A00:
2ND = 68.00217.701 1DY 2 71.ROBSO.M01
SC10U6D3V5KX-1GP
2
Change C8601 to 10uF 0805 size.
C8738
1
R8602 0R2J-2-GP SC10U6D3V5KX-1GP
2
Colay with Seymour-XT-S3 DY
2
(71.SEYMR.M01)
PX_EN Mode BIF_VDDC PX_EN 8209A_EN/DEM_VGA1D5V_VGA_PWOK_R PX_EN# PX_EN## BIF_VDDC

BIF_VDDC U8601 U8603 VGA_CORE BIF_VDDC U8602 U8604 1V_VGA_S0
AO3400A-GP AO3400A-GP AO3418-GP AO3418-GP
0 Normal VGA_Core
Non-BACO 0 1 1 0 1 VGA_Core
S D BIF_VDDC_CORE D S S D BIF_VDDC_1V D S 1 BACO 1V_VGA
BACO 1 0 0 1 0 1V_VGA
3D3V_VGA_S0
3D3V_VGA_S0
84.03400.B37
2nd = 84.03203.031 84.03418.031
G
84.03400.B37 2nd = 84.P8503.031 PX_EN# = High, BIF_VDDC = 1V_VGA_S0

2nd = 84.03203.031 84.03418.031
2nd = 84.P8503.031 PX_EN## = High, BIF_VDDC = VGA_CORE
1
1
R8604
R8603 1KR2J-1-GP
1KR2J-1-GP
2
PX_EN#
2
PX_EN##
20101224 A00:
Change R8601 to 0402 0 ohm pad.
DGPU_PWROK 1 R8601 2 1D5V_VGA_PWOK_R

(22,92,93) DGPU_PWROK
0R0402-PAD
U8605 3D3V_VGA_S0
Q8602
(83) 1D5V_VGA_PWOK 1
5 4 3
(92,93) 8209A_EN/DEM_VGA 2
DY 4 1D5V_VGA_PWOK_R 5 2 PX_EN#
3
PX_EN## 6 1
TC7SZ08FU-2-GP
73.7SZ08.EAH 2N7002KDW-GP
2ND = 73.01G08.L04
B 3rd = 73.7SZ08.DAH 84.2N702.A3F B
2nd = 84.DM601.03F
3D3V_S5
2N7002K-2-GP
(84) PX_EN G
D 8209A_EN/DEM_VGA
1
3D3V_VGA_S0
S DY R8607
100KR2J-1-GP
10KR2J-3-GP
Q8601
R8606
84.2N702.J31
2
2ND = 84.2N702.031
1
Q8604_C
1D5V_VGA_PWOK
2N7002K-2-GP DY
Q8604_C G
2
R8608
3
D 1D5V_VGA_PWOK 1D5V_VGA_S0 1 DY 2 Q8604_B 1 DY Q8604

PMBS3904-1-GP
DY
S
2
2K2R2J-2-GP
SCD1U10V2KX-5GP
1
Q8603 C8693 84.03904.L06

84.2N702.J31 DY
2ND = 84.2N702.031 2nd = 84.03904.P11
2
3rd = 84.03904.T11
A A
<Core Design>
Wistron Corporation
Title
GPU_POWER(4/5)
A1
Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
20101224 A00:
Change L8703,L8704,L8705,L8706 to 0402 0 ohm pad.
Un-stuff DPx_VDD18 caps.
1D8V_VGA_S0
1D8V_VGA_S0 DPEF_VDD18 DPAB_VDD18 L8704
L8705 VGA1G 7 OF 7 (1.8V@300mA DPAB_VDD18)
1 2
SC4D7U6D3V3KX-GP
DP E/F POWER DP A/B POWER
C8713
1 2 0R0402-PAD-2-GP
SCD1U10V2KX-5GP
SC4D7U6D3V3KX-GP
1
C8717
C8714
C8712
0R0402-PAD-2-GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
D D
1
C8718
C8719
AG15 AE11 DY DY DY
SC1U6D3V2KX-GP
DPE_VDD18 DPA_VDD18
DY DY DY AG16 AF11
2
DPE_VDD18 DPA_VDD18
2
DPEF_VDD10 DPAB_VDD10
1V_VGA_S0 AG20 AF6 1V_VGA_S0

L8706 DPE_VDD10 DPA_VDD10 L8703
AG21 DPE_VDD10 DPA_VDD10 AF7
(1.0V@220mA DPAB_VDD10)
VGA1E 5 OF 7 1 2 1 2
SC4D7U6D3V3KX-GP
C8721
0R0402-PAD-2-GP AG14 AE1 0R0402-PAD-2-GP
SCD1U10V2KX-5GP
DPE_VSSR DPA_VSSR
1
C8720
C8725
C8702
C8703
C8705
AH14 AE3
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SC10U6D3V5KX-1GP
DPE_VSSR DPA_VSSR
DY DY DY AM14 DPE_VSSR DPA_VSSR AG1 DY DY DY
AA27 A3 AM16 AG6
2
PCIE_VSS GND DPE_VSSR DPA_VSSR
AB24 PCIE_VSS GND A30 AM18 DPE_VSSR DPA_VSSR AH5
AB32 PCIE_VSS GND/EVDDQ AA13
AC24 AA16 DPEF_VDD18 DPAB_VDD18
PCIE_VSS GND
AC26 PCIE_VSS GND AB10
AC27 PCIE_VSS GND/EVDDQ AB15 AF16 DPF_VDD18 DPB_VDD18 AE13
AD25 PCIE_VSS GND AB6 AG17 DPF_VDD18 DPB_VDD18 AF13
AD32 PCIE_VSS GND AC9
AE27 AD6 DPEF_VDD10 DPAB_VDD10
PCIE_VSS GND
AF32 PCIE_VSS GND AD8
AG27 PCIE_VSS GND AE7 AF22 DPF_VDD10 DPB_VDD10 AF8
AH32 PCIE_VSS GND AG12 AG22 DPF_VDD10 DPB_VDD10 AF9
K28 PCIE_VSS GND AH10
K32 PCIE_VSS GND AH28
L27 PCIE_VSS GND B10 AF23 DPF_VSSR DPB_VSSR AF10
M32 PCIE_VSS GND B12 AG23 DPF_VSSR DPB_VSSR AG9
C N25 B14 AM20 AH8 C
PCIE_VSS GND DPF_VSSR DPB_VSSR
N27 PCIE_VSS GND B16 AM22 DPF_VSSR DPB_VSSR AM6
P25 PCIE_VSS GND B18 AM24 DPF_VSSR DPB_VSSR AM8
P32 PCIE_VSS GND B20
R27 PCIE_VSS GND B22
T25 B24 R8703
PCIE_VSS GND
T32 PCIE_VSS GND B26
U25 PCIE_VSS GND B6 1 2DPCD_CALR AF17 DPEF_CALR DPAB_CALR AE10 DPAB_CALR 1 2
U27 B8 R8701 150R2F-1-GP 150R2F-1-GP
PCIE_VSS GND DPEF_VDD18 DPAB_VDD18
V32 PCIE_VSS GND C1
W25 PCIE_VSS GND C32
W26 E28 AG18 DP PLL POWER AG8
PCIE_VSS GND DPE_PVDD DPA_PVDD
W27 PCIE_VSS GND F10 AF19 DPE_PVSS DPA_PVSS AG7
Y25 F12 DPEF_VDD18 DPAB_VDD18
PCIE_VSS GND N11_GND
Y32 PCIE_VSS GND F14 1DY 2
GND F16
F18 R8702 0R2J-2-GP AG19 AG10
GND N12_GND DPF_PVDD DPB_PVDD
GND F2 1DY 2 AF20 DPF_PVSS DPB_PVSS AG11
GND F20
M6 F22 R8704 0R2J-2-GP
N11_GND GND GND
N11 GND GND F24
N12_GND N12 F26 ROBSON-GP-U
GND GND
N13 GND GND F6 71.ROBSO.M01
N16 F8
N18
N21
GND
GND
GND
GND GND
GND
GND
G10
G27 Colay with Seymour-XT-S3
P6 GND GND G31
P9 GND GND G8 (71.SEYMR.M01)
R12 GND GND H14
B B
R15 GND GND H17
R17 GND GND H2
R20 GND GND H20
T13 GND GND H6
T16 GND GND J27
T18 GND GND J31
T21 GND GND K11
T6 GND GND K2
U15 GND GND K22
U17 GND GND K6
U20 GND GND T11
U9 R11 1D8V_VGA_S0 1D8V_VGA_S0 P.85
GND GND
V13 GND
V16 GND
V18 GND (1.8V@130mA DPB_VDD18)
Y10 GND
Y15 GND
1
1
Y17 A32 VSS_MECH1 TPAD14-GP1 TP8701 C8709 C8710 C8711
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SC4D7U6D3V3KX-GP
GND VSS_MECH
Y20 GND VSS_MECH AM1 VSS_MECH2 TPAD14-GP1 TP8702 DY DY
AM32 VSS_MECH3 TPAD14-GP1 TP8703
2
2
VSS_MECH
ROBSON-GP-U
71.ROBSO.M01
<Core Design>
A A
Colay with Seymour-XT-S3 Wistron Corporation

(71.SEYMR.00U) Taipei Hsien 221, Taiwan, R.O.C.
Title
GPU_DPPWR/GND(5/5)
A3 Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
1D5V_VGA_S0 VRAM2A 1 OF 2
1D5V_VGA_S0 VRAM1A 1 OF 2 C5 B5
VDD VSS
C10 B10
VDD VSS
C5 B5 D11 D10
VDD VSS VDD VSS
C10 B10 G1 G5
VDD VSS VDD VSS
D11 D10 G4 G10
VDD VSS VDD VSS
G1 G5 G11 H1
VDD VSS VDD VSS
G4 G10 G14 H14
VDD VSS VDD VSS
G11 H1 L1 K1
VDD VSS VDD VSS
G14 H14 L4 K14
VDD VSS VDD VSS
L1 K1 L11 L5
VDD VSS VDD VSS
L4 K14 L14 L10
VDD VSS VDD VSS
L11 L5 P11 P10
VDD VSS VDD VSS
L14 L10 R5 T5
VDD VSS 1D5V_VGA_S0 VDD VSS
P11 P10 R10 T10
VDD VSS VDD VSS
R5 T5
1D5V_VGA_S0 VDD VSS
R10 T10 B1 A1
VDD VSS VDDQ VSSQ
B3 A3
VDDQ VSSQ
D B1 A1 B12 A12 D
VDDQ VSSQ VDDQ VSSQ
B3 A3 B14 A14
VDDQ VSSQ VDDQ VSSQ
B12 A12 D1 C1
VDDQ VSSQ VDDQ VSSQ
B14 A14 D3 C3
VDDQ VSSQ VDDQ VSSQ
D1 C1 D12 C4
VDDQ VSSQ VDDQ VSSQ
D3 C3 D14 C11
VDDQ VSSQ VDDQ VSSQ
D12 C4 E5 C12
VDDQ VSSQ VDDQ VSSQ
D14 C11 E10 C14
VDDQ VSSQ VDDQ VSSQ
E5 C12 F1 E1
VDDQ VSSQ VDDQ VSSQ
E10 C14 F3 E3
VDDQ VSSQ VDDQ VSSQ
F1 E1 F12 E12
VDDQ VSSQ VDDQ VSSQ
F3 E3 F14 E14
VDDQ VSSQ VDDQ VSSQ
F12 E12 G2 F5
VDDQ VSSQ VDDQ VSSQ
F14 E14 G13 F10
VDDQ VSSQ VDDQ VSSQ
G2 F5 H3 H2
VDDQ VSSQ VDDQ VSSQ
G13 F10 H12 H13
VDDQ VSSQ VDDQ VSSQ
H3 H2 K3 K2
VDDQ VSSQ VDDQ VSSQ
H12 H13 K12 K13
VDDQ VSSQ VDDQ VSSQ
K3 K2 L2 M5
VDDQ VSSQ VDDQ VSSQ
K12 K13 L13 M10
VDDQ VSSQ VDDQ VSSQ
L2 M5 M1 N1
VDDQ VSSQ VDDQ VSSQ
L13 M10 M3 N3
VDDQ VSSQ VDDQ VSSQ
M1 N1 M12 N12
VDDQ VSSQ VDDQ VSSQ
M3 N3 M14 N14
VDDQ VSSQ VDDQ VSSQ
M12 N12 N5 R1
VDDQ VSSQ VDDQ VSSQ
M14 N14 N10 R3
VDDQ VSSQ VDDQ VSSQ
N5 R1 P1 R4
VDDQ VSSQ C8862 VDDQ VSSQ
N10 R3 1D5V_VGA_S0 1 2 SC1U6D3V2KX-GP P3 R11
VDDQ VSSQ VDDQ VSSQ
P1 R4 P12 R12
C8824 VDDQ VSSQ VDDQ VSSQ
1D5V_VGA_S0 1 2 SC1U6D3V2KX-GP P3 R11 R8823 1 22K37R2F-GP P14 R14
VDDQ VSSQ R8822 1 VDDQ VSSQ
P12 R12 2 5K49R2F-GP T1 U1
R8814 1 VDDQ VSSQ VDDQ VSSQ
22K37R2F-GP P14 R14 C8865 1 2 SC1U6D3V2KX-GP T3 U3
R8815 1 VDDQ VSSQ VDDQ VSSQ
2 5K49R2F-GP T1 U1 T12 U12
C8825 1 VDDQ VSSQ VDDQ VSSQ
2 SC1U6D3V2KX-GP T3 U3 T14 U14
VDDQ VSSQ C8864 VDDQ VSSQ
T12 U12 1 2 SC1U6D3V2KX-GP
VDDQ VSSQ R8820 1 VREFC_A1
T14 U14 1D5V_VGA_S0 22K37R2F-GP J14 A5
C8826 VDDQ VSSQ VREFC VPP/NC#A5
1 2 SC1U6D3V2KX-GP R8821 1 2 5K49R2F-GP U5
R8816 1 VREFC_A0 VREFD1_A1 VPP/NC#U5
1D5V_VGA_S0 22K37R2F-GP J14 A5 C8863 1 2 SC1U6D3V2KX-GP A10
R8817 1 VREFC VPP/NC#A5 VREFD2_A1 VREFD
2 5K49R2F-GP U5 C8867 1 2 SC1U6D3V2KX-GP U10
C8827 VREFD1_A0 VPP/NC#U5 VREFD
1 2 SC1U6D3V2KX-GP A10 1D5V_VGA_S0 R8824 1 22K37R2F-GP
C8829 VREFD2_A0 VREFD
1 2 SC1U6D3V2KX-GP U10 R8825 1 2 5K49R2F-GP
R8818 1 VREFD
C
1D5V_VGA_S0 22K37R2F-GP C8866 1 2 SC1U6D3V2KX-GP H5GQ1H24AFR-T2L-GP C
R8819 1 2 5K49R2F-GP
C8828 1 2 SC1U6D3V2KX-GP H5GQ1H24AFR-T2L-GP DQA1_[31..0] (84)
(84) MAA1_[8..0] VRAM2B 2 OF 2
(84) MAA0_[8..0] DQA0_[31..0] (84)
VRAM1B 2 OF 2 MAA1_0 K4 A4 DQA1_22
MAA1_6 A8/A7 DQ0 DQA1_20
H5 A2
MAA0_7 DQA0_12 MAA1_7 A9/A1 DQ1 DQA1_23
K4 A4 H4 B4
MAA0_1 A8/A7 DQ0 DQA0_13 MAA1_1 A10/A0 DQ2 DQA1_21
H5 A2 K5 B2
MAA0_0 A9/A1 DQ1 DQA0_8 MAA1_8 A11/A6 DQ3 DQA1_18
H4 B4 J5 E4
MAA0_6 A10/A0 DQ2 DQA0_9 A12/RFU#J5/NC#J5 DQ4 DQA1_19
K5 B2 E2
MAA0_8 A11/A6 DQ3 DQA0_10 MAA1_4 DQ5 DQA1_17
J5 E4 H11 F4
A12/RFU#J5/NC#J5 DQ4 DQA0_11 1D5V_VGA_S0 MAA1_3 BA0/A2 DQ6 DQA1_16
E2 K10 F2
MAA0_2 DQ5 DQA0_15 MAA1_2 BA1/A5 DQ7 DQA1_30
H11 F4 K11 A11
1D5V_VGA_S0 MAA0_5 BA0/A2 DQ6 DQA0_14 MAA1_5 BA2/A4 DQ8 DQA1_29
K10 F2 H10 A13
MAA0_4 BA1/A5 DQ7 DQA0_0 BA3/A3 DQ9 DQA1_27
K11 A11 B11
MAA0_3 BA2/A4 DQ8 DQA0_3 DQ10 DQA1_26
H10 A13 (84) ADBIA1 J4 B13
1
BA3/A3 DQ9 DQA0_1 ABI# DQ11 DQA1_31
B11 G3 E11
60D4R2F-GP
60D4R2F-GP
DQ10 (84) CASA1# RAS# DQ12
DQA0_2 DQA1_28
R8827
R8826
(84) ADBIA0 J4 B13 (84) WEA1# G12 E13
1
ABI# DQ11 DQA0_6 CS# DQ13 DQA1_24

G3 E11 L3 F11
60D4R2F-GP
60D4R2F-GP
(84) RASA0# RAS# DQ12 (84) RASA1# CAS# DQ14

DQA0_4 DQA1_25
R8809
R8810
(84) CSA0#_0 G12 E13 (84) CSA1#_0 L12 F13

CS# DQ13 DQA0_7 WE# DQ15 DQA1_8
L3 F11 U11
2
(84) CASA0# CAS# DQ14 DQ16
L12 F13 DQA0_5 J12 U13 DQA1_9
(84) WEA0# WE# DQ15 (84) CLKA1 CK DQ17
U11 DQA0_22 J11 T11 DQA1_10
(84) CLKA1#
2
DQ16 DQA0_20 CK# DQ18 DQA1_11

(84) CLKA0 J12 U13 (84) CKEA1 J3 T13
CK DQ17 DQA0_23 CKE# DQ19 DQA1_13
(84) CLKA0# J11 T11 N11
CK# DQ18 DQA0_21 DQ20 DQA1_14
(84) CKEA0 J3 T13 (84) DDBIA1_2 D2 N13
CKE# DQ19 DQA0_19 DBI0# DQ21 DQA1_12
N11 (84) DDBIA1_3 D13 M11
DQ20 DQA0_17 DBI1# DQ22 DQA1_15
(84) DDBIA0_1 D2 N13 (84) DDBIA1_1 P13 M13
DBI0# DQ21 DQA0_16 DBI2# DQ23 DQA1_0
(84) DDBIA0_0 D13 M11 (84) DDBIA1_0 P2 U4
DBI1# DQ22 DQA0_18 1D5V_VGA_S0 DBI3# DQ24 DQA1_1
(84) DDBIA0_2 P13 M13 U2
DBI2# DQ23 DQA0_29 DQ25 DQA1_2
(84) DDBIA0_3 P2 U4 (84) MEM_RST J2 T4
1D5V_VGA_S0 DBI3# DQ24 DQA0_31 R8829 1 RESET# DQ26 DQA1_3
U2 DY 2 0R2J-2-GP T2
DQ25 DQA0_26 R8830 1 SEN_A1 DQ27 DQA1_4
(84) MEM_RST J2 T4 2 0R0402-PAD J10 N4
R8813 1 RESET# DQ26 DQA0_30 VRAM2_ZQ SEN DQ28 DQA1_7
DY 2 0R2J-2-GP T2 R8828 1 2 120R2F-GP J13 N2
R8812 1 SEN_A0 DQ27 DQA0_27 ZQ DQ29 DQA1_6
2 0R0402-PAD J10 N4 1D5V_VGA_S0 J1 M4
R8811 1 VRAM1_ZQ SEN DQ28 DQA0_28 MF DQ30 DQA1_5
2 120R2F-GP J13 N2 MF=1 M2
ZQ DQ29 DQA0_24 DQ31
J1 M4 Mirror (84) WCKA1_1 D4
MF DQ30 DQA0_25 WCK1
M2 (84) WCKA1#_1 D5 C2 EDCA1_2 (84)
DQ31 WCK1# EDC0
(84) WCKA0_0 D4 C13 EDCA1_3 (84)
WCK1 EDC1
(84) WCKA0_0# D5 C2 EDCA0_1 (84) (84) WCKA1_0 P4 R13 EDCA1_1 (84)
B WCK1# EDC0 WCK23 EDC2 B
C13 EDCA0_0 (84) (84) WCKA1#_0 P5 R2 EDCA1_0 (84)
EDC1 20101227 A00: WCK23# EDC3
(84) WCKA0_1 P4 R13 EDCA0_2 (84)
WCK23 EDC2 Change R8812,R8830 to 0R 0402 pad.
(84) WCKA0_1# P5 R2 EDCA0_3 (84)
WCK23# EDC3 H5GQ1H24AFR-T2L-GP
H5GQ1H24AFR-T2L-GP
Samsung = 72.20325.00U
Hynix = 72.05224.00U
Use internal Vref memory voltage
1D5V_VGA_S0
1D5V_VGA_S0
1
1
C88302
C88312
C88322
C88332
C88342
C88352
C88362
C88372
C88382
C88392
C88402
C88412
C88422
C88432
C88442
C88452
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C88552
C88472
C88492
C88512
C88532
C88562
C88582
C88602
C88462
C88482
C88502
C88522
C88542
C88572
C88592
C88612
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1D5V_VGA_S0
1D5V_VGA_S0
SC10U6D3V5KX-1GP
A A
C8801
1
SC10U6D3V5KX-1GP
C8802
1
2
<Core Design>
2
Wistron Corporation
Title

GPU-VRAM1,2 (1/4) Rev
A2 Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Size
RESERVED
Document Number Rev
A3
Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
3D3V_AUX_S5
2
1 2
5V_S0 3D3V_VGA_S0 PR9221 10KR2J-3-GP
DY PR9218
100KR2J-1-GP
PWR_VGA_CORE_EN_R#
1
PD9201
2 DY1 8209A_EN/DEM_VGA 8209A_EN/DEM_VGA (86,93)
(93) DGPU_PWR_EN
1
D CH551H-30PT-GP PC9216 D
1
DY SCD1U10V2KX-4GP
4
5V_S0
PC9201
PC9202
PC9203
PC9204
SC10U10V5KX-2GP
SC10U10V5KX-2GP
SCD01U16V2KX-3GP
SCD1U10V2KX-4GP
VGA_CORE
2
PQ9206
2
DMN66D0LDW-7-GP DY
2
1
3
PR9220
1
DY 100R2J-2-GP
PR9201
10R2J-2-GP
1
8209A_EN/DEM_VGA PQ9206_3
2
PWR_VGA_AVDD
1
PC9205
SCD22U10V3KX-2GP
3D3V_VGA_S0
2
Design Current = 9.03A
1
PR9214 14.19A<OCP< 16.77A

10KR2J-3-GP AGND_VGA
C4
C5
B3
E4
E5
2
PU9201
PWR_VGA_CORE_PGOOD 1 PR9215 2
AVDD
VDD
VDD
VDD
VDD
DGPU_PWROK (22,86,93) VGA_CORE
0R0402-PAD
1
PC9219 20101224 A00: PR9205 1 23K7R2F-GP

2 PWR_VGA_IRIPL B2 D1 PWR_VGA_VX 1 2
SC100P50V2JN-3GP Change PR9215 to 0402 0 ohm pad. IRIPL VX#D1 PL9201 IND-D2UH-11-GP
B4 D2
2
PR9203 1 44K2R2D-GP PWR_VGA_BIAS TEMP VX#D2

2 A1 D3
PR9204 1 6K49R2F-1-GP
2 PWR_VGA_R_SEL/ILOAD
A2
BIAS VX#D3
D4 68.R2010.10I
R_SEL/ILOAD VX#D4
D5
VX#D5
1
8209A_EN/DEM_VGA A5 A4
PWR_VGA_CORE_PGOOD OE VSENSE+
DY DY
PC9206
PC9207
PC9208
PC9209
PC9210
PC9211
PC9212
PC9213
B5 A3
SC6800P25V2KX-1GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SCD1U10V2KX-4GP
STAT VDES
2
C C
AGND
GND
GND
GND
GND
GND
GND
1
PC9215
SC1U10V2KX-1GP DY
AGND_VGA VT357FCX-ADJ-007-GP
C1
C2
C3
E1
E2
E3
B1
2 1 PWR_VGA_VSENSE+ 2 1 VGA_CORE
PG9210 PWR_VGA_VDES PG9211
SC2200P50V2KX-2GP
GAP-CLOSE-PWR GAP-CLOSE-PWR
AGND_VGA
close output MLCC
1
453KR2F-1-GP
PR9224
365KR2F-GP
PR9223
PC9214
3D3V_VGA_S0
1
1
PR9206
38K3R2F-GP
DY VSENSE-TRACE
1
PD9202
2
PR9209 A PWRCNTL_1_D
K DY 1 DY 2
2
10KR2F-2-GP
PWRCNTL_1#
PWRCNTL_0#
DY
B0530WS-7-F-GP PR9207
5K1R2F-2-GP
PARALLEL TO VSENSE+
2
PR9208
PWRCNTL_1_R PWR_VGA_VSENSE-
(85) PWRCNTL_1 1 DY 2 2 1
PG9212
2
PC9222
10K7R2F-GP GAP-CLOSE-PWR
100KR2J-1-GP
SCD047U16V2KX-1-GP
1
PR9202
DY DY
close output MLCC
2
1
5V_S5
3D3V_VGA_S0
1
PC9217
14
PU9202A
SCD1U10V2KX-4GP
2
1
PD9203 2
PR9213 K A PWRCNTL_0_D 1 2 1
B 10KR2F-2-GP 5V_S5 VGA_CORE B
DY B0530WS-7-F-GP PR9212
3
5K1R2F-2-GP TSLVC02APW-GP
PR9210
2
7
1 2 PWRCNTL_0_R PU9202_1
(85) PWRCNTL_0
2
1
PC9223
10K7R2F-GP
14
PU9202B
100KR2J-1-GP
SCD047U16V2KX-1-GP
1
PR9211
PR9217 PR9216
3D3R5J-GP 3D3R5J-GP
PC9218
5
SCD1U10V2KX-4GP
PR9219
4 PQ9202_4
2
2
1 2 PU9202_6 6
1
2
(85) PWRCNTL_0 2
52K3R2F-L-GP PQ9203_D
TSLVC02APW-GP
7
PC9220
SCD01U50V2KX-1GP
1
14
PU9202C PU9206
1 5
D
B VCC
8
10 2 PQ9203
A AO3404A-GP
(85) PWRCNTL_1 9
3 4 PU9206_Y G 84.03404.B31
GND Y
TSLVC02APW-GP
7
74LVC1G32GW-1GP
VID1 VID0
S
PQ9202_10
GPIO20 GPIO15 Voltage PR9222 14
73.01G32.AHH
PQ9204 PU9202D
1 6 PWRCNTL_1# 1 2 PQ9202_11 11
0 0 1.05V 13 PQ9202_13
2
PWRCNTL_1_R 2 5 PWRCNTL_0_R 52K3R2F-L-GP 12

PC9221
0 1 1.0V PWRCNTL_0# 3 4 SCD01U50V2KX-1GP TSLVC02APW-GP
1
1 0 0.9V 2N7002KDW-GP
84.2N702.A3F 73.07402.EHB
1 1 0.95V 2nd = 84.DM601.03F
A A
PR9206 38.3 kohm
PR9224 DY <Core Design>
PR9223 365 kohm Wistron Corporation

Title
VT357_+VGA_CORE
A2
Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
Power on sequence for Robson-XT and SEYMOUR-XT: AO4468, SO-8

3D3V_S0 to 3D3V_VGA_S0 Transfer 3D3V_VGA_S0 --> 1V_VGA_S0 --> 1D8V_VGA_S0 1D8V_VGA_S0 Id=??A, Qg=9~12nC
Rdson=17.4~22m ohm
1D8V_S0
1D8V_VGA_S0
PU9306
8 D S 1
7 D S 2
DY 6 D S 3
1
1 2 PR9301 5 D G 4 PC9331
1
0R2J-2-GP PC9330
DMP2130L-7-GP 3D3V_VGA_S0 SC10U6D3V3MX-GP AO4468-GP SC10U6D3V3MX-GP
2
PQ9302 84.04468.037
2
3D3V_S0 S 2nd = 84.08882.037
D
D
84.02130.031
G
2ND = 84.03413.A31 3D3V_VGA discharge
2
1
D
3D3V_AUX_S5 D
G
PR9316
10KR2J-3-GP 1 2 1D8V_VGA_EN# 1D8V_ENABLE_RC
2
PC9324 PR9334 100KR2J-1-GP
PR9333
SCD1U10V2KX-5GP D G S
1
PR9319 2 1
PR9319_1 1 2 PR9319_2
1
10KR2J-3-GP 20101228 A00 Modify: PQ9306 15V_S5 20KR2F-L-GP
Change PR9320 to short pad at X-Build. 2N7002KDW-GP PC9329
20110105 A00: SCD01U50V2KX-1GP
84.2N702.A3F
2
2
Change PR9316 to 10k ohm (follow the standard schematics).
3
6
2
PR9314 2nd = 84.DM601.03F
PQ9303 470R2J-2-GP G9731_PGOOD_1V 1 PR9320 2 1D8V_VGA_EN S G D PR9335
2N7002KDW-GP 0R0402-PAD 100KR2J-1-GP
84.2N702.A3F PC9323
SCD1U10V2KX-5GP
2nd = 84.DM601.03F
1
DY
2
1D8V_ENABLE
3.3V_RUN_VGA_1
PR9305
3D3V_S0 1 2 PD9303
(92) DGPU_PWR_EN 2 DY 1
DGPU_PWR_EN
10KR2F-2-GP
CH551H-30PT-GP
1D8V_VGA_S0
3D3V_S5 3D3V_VGA_S0
1D8V_VGA_S0_PG Discharge Circuit
10KR2J-3-GP
DGPU_PWR_EN (92)
PR9339
1
20101224 A00 Modify: PR9337
1
un-stuff 1D8V_S0_VGA_PG related circuit 470R2J-2-GP
at X-Build stage. PR9338
DY 100KR2J-1-GP DY
2
2
2
PQ9309
C C
DIS_1D8V_VGA_S0
PQ9310_C G
DGPU_PWR_EN#
84.03904.L06 D 1D8V_S0_VGA_PG (83)
dGPU mode L 2nd = 84.03904.P11 DY
PQ9311 3rd = 84.03904.T11 S
IGPU H
3
1 6 DGPU_PWR_EN
PQ9310_B 1 2N7002K-2-GP
1D8V_VGA_S0 1 PR9340 2 PQ9310
IGPU with BACO L 1D8V_VGA_EN# PMBS3904-1-GP 84.2N702.J31
(18) DGPU_PWR_EN#
2 5 DY DY
2ND = 84.2N702.031
2
2K2R2J-2-GP
SCD1U10V2KX-5GP
DIS_1D8V_VGA_S0 3 4
1
PC9301
2N7002KDW-GP DY
2
84.2N702.A3F
2nd = 84.DM601.03F
1D5V_VGA_S0
change low Rds(on) MOSFET
1D5V_S3 1D5V_VGA_S0
G9731 for 1V_VGA_S0
PU9305
Park_Madison Does Not Support BACO, So follow Old Sequence
AO4468, SO-8 8 D S 1
7 D S 2 Seymour_Whistler_Robson Support BACO, So Change Sequence
Id=?A, Qg=9~12nC 6 D S 3
1
Rdson=17.4~22m ohm 5 D G 4 PC9332

1V_VGA
1
1D5V_ENABLE_RC
PC9327 1D5V_S3 1V_VGA_S0_LDOIN

AO4468-GP SC10U6D3V3MX-GP Design current = 1.72A
2
84.04468.037 PG9301
SC10U6D3V3MX-GP
2
1D5V_S3 to 1D5V_VGA_S0 trace need increase 2nd = 84.08882.037 1 2
to avoid 1D5V_VGA_S0 DROP Voltage. GAP-CLOSE-PWR

PU9303 Vo(cal.)=1.0036V 1V_PWR 1V_VGA_S0
PG9302
1 2 PC9303 5 PG9305
PR9330 VIN
SC10U10V5KX-2GP
B B
Park_Madison Does Not Support BACO, So follow Old Sequence 5V_S5 6
VPP VO#4
4 1 2
SC1U10V2KX-1GP
Seymour_Whistler_Robson Support BACO, So Change Sequence 1 2 GAP-CLOSE-PWR 7 3
1
PC9313 POK VO#3 PC9012 GAP-CLOSE-PWR
8 2
Discharge Circuit
1K27R2F-L-GP
1
20KR2F-L-GP VEN ADJ PG9306
3D3V_VGA_S0 should ramp-up before VGA_Core 9 1 DY
1
GND GND
1 2
SCD01U16V2KX-3GP
1
2
1
3D3V_AUX_S5 PC9326 1D5V_VGA_S0 VGA_Core should ramp-up before 1V_VGA_S0 PC9317 PC9316
1
SCD01U50V2KX-1GP
2 PR9322
G9731F11U-GP GAP-CLOSE-PWR
2
1 2 1D5V_VGA_EN# 1V_VGA_S0 should ramp up before 1D8V_VGA_S0 DY

74.G9731.03D
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
PR9332 100KR2J-1-GP
2
1
D G S so 1V_VGA_S0 EN have to fine tune RC delay 20100106 A00:

2nd = 74.05930.03D Power: un-stuff PC9317.
PR9336
470R2J-2-GP
after VGA_Core
6
3D3V_VGA_S0 1 2PWR_1V_PGOOD
PQ9305 15V_S5 PR9304 100KR2J-1-GP PR9315_2
DIS_1D5V_VGA_S02
2N7002KDW-GP PR9312
4K99R2F-L-GP
1 2 G9731_PGOOD_1V 1 PR9311 2
84.2N702.A3F 3D3V_VGA_S0
0R0402-PAD
1
1
PD9301 2nd = 84.DM601.03F PQ9307
10KR2J-3-GP 20101224 A00 Modify:
S G D Change PR9311 to short pad at X-Build.
PR9315
2 DY 1 PR9331
(92) DGPU_PWR_EN 100KR2J-1-GP G 1D5V_VGA_EN# 0629 Modify: PWR_1V_EN
CH551H-30PT-GP Reserved PD9302 connect DGPU_PWR_EN to
PWR_1V_EN for power down sequence.
Vout=0.8V*(R1+R2)/R2
PR9326 D
1
2
1D5V_VGA_EN PC9318
1 DY 2
1
(22,86,92) DGPU_PWROK
SCD1U10V2KX-5GP
0R2J-2-GP S PD9302
1D5V_ENABLE 2 DY 1
(92) DGPU_PWR_EN
2
2N7002K-2-GP
1 PR9327 2 CH551H-30PT-GP
(86,92) 8209A_EN/DEM_VGA 0R0402-PAD 84.2N702.J31
20101224 A00 Modify: 2ND = 84.2N702.031
Change PR9327 to short pad at X-Build.
PR9302 Discharge Circuit

3D3V_AUX_S5 1 2 PWR_1V_EN#
A A
100KR2J-1-GP
6
PQ9301
2N7002KDW-GP
<Core Design>
84.2N702.A3F
1
2nd = 84.DM601.03F
Wistron Corporation
PR9303 Taipei Hsien 221, Taiwan, R.O.C.
PQ9311_3 2 1 1V_VGA_S0 Title
PWR_1V_EN
470R2J-2-GP
DISCRETE VGA POWER
A2 Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
<Core Design>
A A
Wistron Corporation
Title
Reserved
Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
D D
C
(Blanking) C
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
H3 STF276R160H209-1-GP H4 H6
H2 H5 H7
HOLE335R115-GP STF296R138H83-GP HOLE256R115-GP HT85BE85R29-U-5-GP HOLE256R115-GP H8
H1 HOLE256R115-GP
HT85B85X925R29-S-GP 34.4ID01.001 H10 H11
HT85BE85R29-U-5-GP HOLE197R166-1-GP
ZZ.00PAD.D11 ZZ.00PAD.D41 ZZ.00PAD.D11
1
ZZ.00PAD.D01
1
1
1
ZZ.00PAD.V71
D D
H14
HT85BE85R29-U-5-GP H15 H16 H17
HOLE335R115-GP HT85B85X925R29-S-GP HOLE276R158-GP
H12
ZZ.00PAD.U61
H13 HOLE197R166-1-GP
HOLE197R166-1-GP ZZ.00PAD.D01
ZZ.00PAD.D41
1
1
1
1
ZZ.00PAD.V71
ZZ.00PAD.V71
SPR4 SPR7 SPR8

SPRING-24-GP-U SPRING-57-GP SPRING-51-GP
SPR1 SPR2 SPR3 SPR6
34.42T14.002
SPRING-51-GP
34.4F822.002
SPRING-24-GP-U
SPRING-24-GP-U
SPRING-24-GP-U
DY DY DY DY
1
34.45T31.001 34.4F822.002
C C
RF Request EMI Request

AUD_DMIC_CLK AUD_DMIC_IN0 LVDS_DDC_DATA_R LVDS_DDC_CLK_R
47R2J-2-GP
47R2J-2-GP
1
1
DCBATOUT 5V_S5 5V_S0 3D3V_S0 5V_S5
R9701
R9702
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
CLK_PCI_LPC (18,65,71)
DY DY
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SC56P50V2JN-2GP
EC9709
EC9710
EC9711
EC9712
EC9713
EC9714
EC9715
EC9716
EC9717
EC9718
SC56P50V2JN-2GP DY DY
SC56P50V2JN-2GP
SC56P50V2JN-2GP
2
1
EC9702
EC9704
EC9721
EC9722
2
2
EC9705
DY DY DY DY DY DY DY DY
SC82P50V2JN-3GP
SC4D7P50V2CN-1GP
SC4D7P50V2CN-1GP
SC4D7P50V2CN-1GP
2
2
EC9703
EC9706
EC9707
EC9708
2
AUD_DMIC_CLK1
AUD_DMIC_IN01
EC9701
DY DY DY DY DY
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SC4D7P50V2CN-1GP
1
DY DY
SCD1U50V3KX-GP
SCD1U50V3KX-GP
1
EC9719
EC9720
2
2
(20,32) CLK_PCH_48M
(29,49) AUD_DMIC_CLK
(29,49) AUD_DMIC_IN0
(17,49) LVDS_DDC_DATA_R
1D5V_S3 3D3V_S0 3D3V_S0 5V_S5 5V_S5 (17,49) LVDS_DDC_CLK_R
EC9745
EC9746
EC9747
EC9748
1 EC9749
1 EC9750
1 EC9751
CLK_PCH_48M +PVDD 5V_S0

SCD1U10V2KX-5GP
1
B EC9755 B
DY DY DY DY DY DY DY 2
DY
1
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC56P50V2JN-2GP
SC56P50V2JN-2GP
2
SC1KP50V2KX-1GP 2
SC1KP50V2KX-1GP 2
SC1KP50V2KX-1GP 2
1
EC9723
SCD1U10V2KX-5GP
5V_S5 5V_S0
DY
2
5V_S0 EC9756
2 1
DY
SCD1U10V2KX-5GP
3D3V_S0
EC9753
1 EC9754
5V_S0
EC9752
1D5V_S3 5V_S5 5V_S5

Place close to H2 1D5V_S3
Place close to SPR2 5V_S0
Place close to H6 +DC_IN +DC_IN DCBATOUT
1
1
PC4035
PC4036
EC9768
DY DY
SC56P50V2JN-2GP
1
EC9724
DY
SC56P50V2JN-2GP
SC1KP50V2KX-1GP 2
1
2
DY
1
DY EC9725 DY EC9728 DY EC9736
2
SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP

2
2
EC9726 SC56P50V2JN-2GP
2
2
DY
1
SCD1U50V3KX-GP
SCD1U50V3KX-GP
SCD1U50V3KX-GP
SCD1U10V2KX-5GP
EC9729
2 1
DY
SCD1U10V2KX-5GP
Place close to H7 Place close to H14 Place close to H10
5V_S5 5V_S0 5V_S5
3D3V_DAC_S0
1
1
1D5V_S3 VCC_CORE 3D3V_DAC_S0 3D3V_DAC_S0
DY
EC9769
EC9770
EC9771
DY EC9730
SCD1U10V2KX-5GP
EC9735
DY EC9738
SCD1U10V2KX-5GP
2
2
SC56P50V2JN-2GP
1
EC9727
2 1
DY DY DY
DY
SC56P50V2JN-2GP
SC56P50V2JN-2GP
SC56P50V2JN-2GP
3D3V_S5 3D3V_S5 SCD1U10V2KX-5GP
2
3D3V_S5 3D3V_S5 3D3V_S5 5V_S5 5V_S5 3D3V_S5 3D3V_S5 3D3V_S5 5V_S5
A 5V_S5 5V_S0 A
EC9757
EC9758
EC9759
EC9760
EC9761
EC9762
EC9763
EC9764
EC9765
EC9766
EC9767
3D3V_S5 1D05V_VTT
1
5V_S5 3D3V_S5 5V_S5 3D3V_S0 2 1 EC9742

DY DY EC9731 EC9732 EC9734 SC56P50V2JN-2GP 2
2 1 2 1 EC9739 DY 1
SCD1U10V2KX-5GP
DY DY
SC56P50V2JN-2GP
SC56P50V2JN-2GP
SC56P50V2JN-2GP
SC56P50V2JN-2GP
SC56P50V2JN-2GP
SC56P50V2JN-2GP
SC56P50V2JN-2GP
SC56P50V2JN-2GP
SC56P50V2JN-2GP
SC56P50V2JN-2GP
SC56P50V2JN-2GP
2
SCD1U10V2KX-5GP SCD1U10V2KX-5GP 2
EC9740
1
DY
SCD1U10V2KX-5GP <Core Design>
2 1 2 1 1D5V_S3 5V_S0
EC9733 SC56P50V2JN-2GP DY
SCD1U10V2KX-5GP
EC9737 EC9741 EC9743 Wistron Corporation
2
DY
1
SC1U6D3V2KX-GP
2
DY
1
SCD1U10V2KX-5GP
2
DY
1
SCD1U10V2KX-5GP
3D3V_S5 5V_S5
Title
2
EC9744
1
UNUSED PARTS/EMI Capacitors
DYSCD1U10V2KX-5GP
Size
A2
Document Number Rev
Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
Huron River Platform Power Sequence

(AC mode) red word: KBC GPIO
(DC mode) red word: KBC GPIO
+RTC_VCC
+RTC_VCC T1 >9ms
T1 >9ms
RTC_RST#
RTC_RST#
DCBATOUT
DCBATOUT T2
T2
Within logic high level and disable if
3D3V_AUX_S5
D it is less than the logic low level.
3D3V_AUX_S5 D
KBC GPIO34 control power on by 3V_5V_EN
S5_ENABLE Sense the power button status Press Power button
KBC_PWRBTN# Platform to KBC PSL_IN2
5V_S5 T3
V5REF_Sus must be powered up before EC_ENABLE#_1(GPIO31) keep low
VccSus3_3, or after VccSus3_3 within
0.7 V. Also, V5REF_Sus must power
3D3V_S5 T4 3D3V_AUX_KBC
down after VccSus3_3, or before
T3 KBC GPIO34 control power on by 3V_5V_EN
VccSus3_3 within 0.7 V.
+5VA_PCH_VCC5REFSUS T5 S5_ENABLE
KBC GPIO43 to PCH
PM_RSMRST#(EC Delay 40ms) T6 >10ms 5V_S5 T4
PCH to KBC GPIO00 V5REF_Sus must be powered up before
+5V_ALW & +3.3V_ALW need meet 0.7V difference
VccSus3_3, or after VccSus3_3 within
PCH_SUSCLK_KBC T7 >5ms 0.7 V. Also, V5REF_Sus must power
3D3V_S5 T5
KBC GPO84 to PCH down after VccSus3_3, or before
+5V_ALW & +3.3V_ALW need meet 0.7V difference
Not floating. VccSus3_3 within 0.7 V.
AC_PRESENT 0ms<T8 <90ms +5VA_PCH_VCC5REFSUS T6
T7 >16ms KBC GPIO20 to PCH

Press Power button
3D3V_AUX_KBC PM_PWRBTN#
Platform to KBC PSL_IN2
Sense the power button status
AC KBC_PWRBTN#
KBC GPIO43 to PCH
This signal has an internal T9 >16ms PM_RSMRST# T8 >10ms
pull-up resistor and has an KBC GPIO20 to PCH
internal 16 ms de-bounce on the PCH to KBC GPIO00
input. AC PM_PWRBTN#
PCH_SUSCLK_KBC T9 >5ms
AC PM_PWRBTN# DC PCH_RSMRST#
T10 T10
PCH to KBC GPIO44 PCH to KBC GPIO44
PM_SLP_S4# PM_SLP_S4#
T11 PCH to KBC GPIO01 T11 PCH to KBC GPIO01
PM_SLP_S3# >30us PM_SLP_S3# >30us
KBC GPIO23 to LAN KBC GPIO23 to LAN
PM_LAN_ENABLE PM_LAN_ENABLE
Enable by PM_SLP_S4# Enable by PM_SLP_S4#
1D5V_S3 T12 1D5V_S3 T12
C C
DDR_VREF_S3(0.75V) T13 DDR_VREF_S3(0.75V) T13
+5V_RUN & +3.3V_RUN need meet 0.7V difference +5V_RUN & +3.3V_RUN need meet 0.7V difference
5V_S0 T14 5V_S0 T14
V5REF must be powered up before 3D3V_S0 T15 V5REF must be powered up before 3D3V_S0 T15
Vcc3_3, or after Vcc3_3 within 0.7 V. Vcc3_3, or after Vcc3_3 within 0.7 V.
Also, V5REF must power down after Also, V5REF must power down after
Vcc3_3, or before Vcc3_3 within 0.7 V. Vcc3_3, or before Vcc3_3 within 0.7 V.
+5VS_PCH_VCC5REF T16 +5VS_PCH_VCC5REF T16
1D5V_S0 T17 1D5V_S0 T17
1D8V_S0 T18 1D8V_S0 T18
0D75V_S0 T19 0D75V_S0 T19

1D8V_S0 & 1D5V_S3 power ready 1D8V_S0 & 1D5V_S3 power ready
RUNPWROK T20 RUNPWROK T20
1D05V_VTT T21 1D05V_VTT T21

VT357FCX PGOOD VT357FCX PGOOD
1.05VTT_PWRGD T22 1.05VTT_PWRGD T22
0D85V_S0 T23 0D85V_S0 T23
0D85V_S0 0D85V_S0
T24 TPS51461RGER PGOOD T24 TPS51461RGER PGOOD
D85V_PWRGD D85V_PWRGD
SetVID ACK SetVID ACK

CPU SVID BUS 50us< T25 <2000us CPU SVID BUS 50us< T25 <2000us
VCC_CORE VCC_CORE
VCC_GFXCORE VCC_GFXCORE
T26 T26
<5ms
ISL95831 PGOOD to system <5ms
ISL95831 PGOOD to system
IMVP_PWRGD IMVP_PWRGD
CLK_EXP_P CLK_EXP_P
B B
ALL_SYS_PWRGD=D85V_PWRGD ALL_SYS_PWRGD=D85V_PWRGD
This signal represents the Power
T27 >99ms KBC GPIO77 to PCH This signal represents the Power
T27 >99ms KBC GPIO77 to PCH
Good for all the non-CORE and PWROK Good for all the non-CORE and PWROK
non-graphics power rails. non-graphics power rails.
T28 >0us T28 >0us
D85V_PWRGD D85V_PWRGD
2ms< T29 <650ms PCH to CPU 2ms< T29 <650ms PCH to CPU
VDDPWRGOOD VDDPWRGOOD
T30 >1ms T30 >1ms
T31 >2ms T31 >2ms
1D8V_S0 1D8V_S0
5ms< T32 <650ms PCH to CPU 5ms< T32 <650ms PCH to CPU
H_CPUPWRGD H_CPUPWRGD
SYS_PWROK T33 >0ms SYS_PWROK T33 >0ms

T34 >1ms+60us T34 >1ms+60us
1ms< T35 <100ms PCH to all system 1ms< T35 <100ms PCH to all system
PLT_RST# PLT_RST#
T36 <200us T36 <200us
DMI DMI
Robson XT Power-Up/Down Sequence
3D3V_S0
PCH GPIO54 output
DGPU_PWR_EN#(Discrete only)
3D3V_VGA_S0(Discrete only)
3D3V_VGA_S0 above VT357 VIH
8209A_EN/DEM_VGA(Discrete only)
A A
VGA_CORE(Discrete only) Ta >0ms
1V_VGA_S0(Discrete only)
RT9035 PGOOD
9035_PGOOD_1V(Discrete only)
Tb >0ms
1D8V_VGA_S0(Discrete only)
Tc >0ms
VT357 PGOOD <Core Design>
DGPU_PWROK(Discrete only)
Wistron Corporation
1D5V_VGA_S0(Discrete only) Td <20ms Taipei Hsien 221, Taiwan, R.O.C.
Title
For power-down, reversing the ramp-up sequence is recommended. Power Sequence

A1
Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
Wistron HURON RIVER POWER UP SEQUENCE DIAGRAM

5V_S5 DCBATOUT
-6
AC AD+
Adapter in
D Page38
-3.1 -3.1 -3.1 D
VDDP VIN 1D5V_S3
PWR_5V3D3V_ENC 3V_5V_EN S5_ENABLE VOUT
3
PM_SLP_S4#
EN
-3.2 -3.3 DDR_VREF_S3
PWR_CHG_ACOK REF
SWITCH ENC 5V_S5 15V_S5
LL1 PUMP
Page40
3D3V_S5 TPS51116RGER
LL2
0D75V_S0
5V_AUX_S5 VTT
RT8223MGQW VREG5
DC/DC 3D3V_AUX_S5 -5
-6.1 (3V/5V) VREG3 3 RUNPWROK
PGD
DCBATOUT 3V_5V_POK PM_SLP_S4#

VIN PGOOD -2 Page46
5
Page41
4 5V_S5 3D3V_S5
DC BQ24745 5V_S0
BT+ PM_SLP_S3#
Battery Charger SWITCH
Page39 -3 BJT Page37
3D3V_AUX_KBC VDD VIN 1D8V_S0
-3.1 4 VOUT
Page40 ACOK 3D3V_S0
S5_ENABLE SWITCH
-4 Page37 PM_SLP_S3# TPS53311RGTR
EN
RUNPWROK
C AC_IN# GPIO34 PGD C
GPIO70 1D5V_S0
Page47
SWITCH
Page37 5
1 SLP_S4# SLP_S3#
-1
KBC
KBC_PWRBTN#
GPIO6 NPCE795P -2.1
11 AND GATE
Power Button PM_RSMRST# 0D75V_EN
PM_SLP_S4# GPIO43 RSMRST# B VDDPWRGOOD
GPIO44 PM_PWRBTN# PM_DRAM_PWRGD Y SM_DRAMPWROK
PM_SLP_S3# GPIO20 PWRBTN# DRAMPWRGD A
GPIO01
2 H_CPUPWRGD H_CPUPWRGD_R
PROCPWRGD UNCOREPWRGOOD
Page27 Cougar Point 12
GPIO77 PCH Sandy Bridge
13 CPU
S0_PWR_GOOD
APWROK
PWROK PLT_RST# BUF_CPU_RST#
PLTRST# RSTIN#
SYS_PWROK SVID
SYS_PWROK
SVID
10
8
5V_S5 DCBATOUT
B B
V5IN VIN 1D05_VTT

VOUT
5 AND GATE 10
S0_PWR_GOOD
RUNPWROK TPS51218DSCR A SYS_PWROK
EN 1.05VTT_PWRGD IMVP_PWRGD Y
Page45 PGOOD B
5V_S5 DCBATOUT 5a
VDDP VIN 0D85_S0 -5

VOUT
5a -7 3D3V_AUX_S5
1.05VTT_PWRGD RT8208BGQW RTC_AUX_S5
EN D85V_PWRGD
Page48 PGOOD -8
+RTC_VCC
6
DCBATOUT
RTC battery
8 VIN VCC_CORE
A
OUTPUT A
SVID
SVID VCC_GFXCORE
VR OUTPUT
6 7 ISL95831HRTZ <Core Design>
D85V_PWRGD IMVP_VR_ON 9
VR_ON IMVP_PWRGD Wistron Corporation
Page42 & 43 & 44 PGOOD 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Title
Power Up Sequence Diagram
Power Up Sequence: -8 ~ 13 Size
A2
Document Number Rev
A00
Nirvana 13
5 4 3 2 1
5 4 3 2 1
D D
DCBATOUT POLYSW DCBATOUT_LCD

Adapter
AO4407A
Charger
BQ24745
Battery +PBATT
TPS51427
C C
15V_S5 3D3V_AUX_S5 5V_AUX_S5 5V_S5 3D3V_S5
G547F2P81 AO4468 TPS51461

1D5V_S3
AO4468 AO3403
TPS51311
RT9026 VT1316+VT1317 VT1317 VT357
5V_USB1_S3 5V_S0 0D85V_S0

3D3V_S0 3D3V_LAN_S5
1D8V_S0
1D05V_VTT
DDR_VREF_S3 0D75V_S0 VCC_CORE VCC_GFXCORE
RT9035 TPCA8062
VT357
B B
1V_VGA_S0 1D5V_S0 AO4468 G5285T11 RTS5138 DMP2130L

VGA_CORE
1D8V_VGA_S0 LCDVDD 3D3V_CARD_S0 3D3V_VGA_S0
Power Shape
Regulator LDO Switch

A <Core Design> A
Wistron Corporation
Title
Size
Power Block Diagram
Document Number Rev
A3
Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
PCH SMBus Block Diagram KBC SMBus Block Diagram

3D3V_S5 3D3V_S0
Ʉ Ʉ 5V_S0
3D3V_S0 Ʉ
SRN2K2J-1-GP
Ʉ SRN2K2J-1-GP
DIMM 1
Ʉ Ʉ
SRN10KJ-5-GP
Ʉ Ʉ
SMBCLK SMB_CLK PCH_SMBCLK
TouchPad Conn.
Ʉ
SCL
D D
SMBDATA SMB_DATA PCH_SMBDATA
Ʉ
SDA
PSDAT1 TPDATA TPDATA TPDATA
3D3V_S5
PSCLK1 TPCLK TPCLK TPCLK
SMBus Address:A0
Ʉ 2N7002KDW
3D3V_S5
3D3V_AUX_KBC
Ʉ
SRN2K2J-8-GP
Ʉ
SML1CLK SML1_CLK
SRN4K7J-8-GP
To KBC DIMM 2
Ʉ
SML1DATA SML1_DATA SRN2K2J-1-GP
Battery Conn.
Ʉ
PCH_SMBCLK SCL SRN33J-7-GP
SML0CLK SML0_CLK PCH_SMBDATA GPIO17/SCL1 BAT_SCL PBAT_SMBCLK1 CLK_SMB
SDA
SML0DATA SML0_DATA GPIO22/SDA1 BAT_SDA PBAT_SMBDAT1 DAT_SMB SMBus address:16
3D3V_S0
SMBus Address:A4
Ʉ G-Sensor BQ24745
Ʉ KBC
3D3V_S0 SCL
PCH
SRN2K2J-1-GP
Ʉ Ʉ
PCH_SMBCLK
PCH_SMBDATA
SCLK
SDATA
NPCE795P SDA SMBus address:12
PCH_HDMI_CLK DDC_CLK_HDMI
SMBus address:xx
C PCH_HDMI_DATA DDC_DATA_HDMI C
SDVO_CTRLCLK
SDVO_CTRLDATA
2N7002KDW Minicard 3D3V_S5
Ʉ WLAN Ʉ
Ʉ
PCH_SMBCLK SMB_CLK
3D3V_S0
PCH_SMBDATA
SMB_DATA
Ʉ SRN2K2J-1-GP
SRN2K2J-1-GP Minicard GPIO73/SCL2 SML1_CLK SCL
PCH_SMBCLK
W-WAN GPIO74/SDA2 SML1_DATA SDA PCH
L_DDC_CLK LVDS_DDC_CLK_R SMB_CLK
PCH_SMBDATA SMB_DATA
L_DDC_DATA LVDS_DDC_DATA_R
CRT_DDC_CLK CRT_DDC_CLK
LVDS_DDC_CLK_R CLK
CRT_DDC_DATA CRT_DDC_DATA
LVDS_DDC_DATA_R DATA LCD CONN
B B
DDC1CLK
DDC1DATA
SRN0J-6-GP
DDC2CLK VGA_CRT_DDCCLK
DDC2DATA VGA_CRT_DDCDATA
DY
3D3V_S0 5V_CRT_S0
VGA Ʉ Ʉ
3D3V_S0
SRN2K2J-1-GP
Ʉ SRN2K2J-1-GP
0R2J-2-GP CRT_DDCCLK_CON
0R2J-2-GP CRT_DDCDATA_CON
CRT CONN
5V_CRT_S0_R
Ʉ 2N7002KDW
SRN2K2J-1-GP
A A
SRN0J-6-GP
DDC2CLK GPU_HDMI_CLK DDC_CLK_HDMI

DY
DDC2DATA GPU_HDMI_DATA DDC_DATA_HDMI
HDMI CONN <Core Design>
Wistron Corporation
Title
SMBUS Block Diagram

A2 Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
Thermal Block Diagram Audio Block Diagram

D D
SPKR_PORT_D_L-
PAGE28 DXP P2800_DXP SPKR_PORT_D_L+ SPEAKER

MMBT3904-3-GP
SC2200P50V2KX-2GP
DXN P2800_DXN
UMA Place near CPU
Codec
Thermal PWM CORE
92HD79B1
P2800 HP1_PORT_B_L HP
MMBT3904-3-GP HP1_PORT_B_R
PAGE27 GPIO5 SYS_THRM TDR T8

OUT
C
KBC GPIO92 CPU_THRM TDL
OTZ THERM_SYS_SHDN#
2N7002
D
PURE_HW_SHUTDOWN#
EN 3V/5V
C
NPCE795P S
G
IMVP_PWRGD PGOD
VR
Put under CPU(T8 HW shutdown)
GPIO94 GPIO56
GPIO4 VGA_THRM TDR
PAGE28
HP0_PORT_A_L MIC
P2800_VGA_DXP HP0_PORT_A_R
DXP THRMDA
VREFOUT_A_OR_F IN
FAN_TACH1
SC2200P50V2KX-2GP SC2200P50V2KX-2GP
VGA DXN
P2800_VGA_DXN
THRMDC
VGA
Thermal
FAN1_DAC
TACH Place near GPU(DISCRETE only).

P2800
FAN
B VIN
MMBT3904-3-GP DMIC_CLK/GPIO1 Digital B
5V
DMIC0/GPIO2
MIC
PH
OTZ
VSET VOUT
VIN
FAN CONTROL
P2793 PORTC_L
PAGE28 PORTC_R
Analog
VREFOUT_C MIC
A <Core Design> A
Wistron Corporation
Title
Size
Thermal/Audio Block Diagram
Document Number Rev
A3
Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
Version Date Page Function Change Item
A00 20101222 40 Power Power/Brian: Change PR4047 to 174k ohm from 121k ohm. Change PR4035 to 300k from 49.9k. Change PR4031 to 150k from 0 ohm. Change PR4034 to 0 ohm pad. Stuff PQ4003. Change PR4036 to 0 ohm pad. Stuff PQ4004.
Change PR4037 to 76.8k ohm from 49.9k ohm. Change PR4032 to 0 ohm pad.
A00 20101222 42 Power Power/Brian: Change PU4201 to 74.01316.F33.
A00 20101224 85 EE Un-stuff THERMTRIP_VGA related circuit at A00 stage for fixed auto shut down issue.
D D
A00 20101224 EE Change all of 0ohm to short pad at X-build stage:
0402: R1404 R1405 R1503 R1504 R5010~R5012 R1807 R2301 R2306 R2307 R2308 R2404 R2405 R2735 R2737 R2758 R2759 R2760 R3614 R3710 R8210, R8506,R8509, L8703,L8704,L8705,L8706, R8316,R8601, PR9215
0603: R5803 R5804 R8507
Parallel resistor: RN1704 RN2010 RN2011 RN2012 RN2013 RN2014 RN2016
RN5117,RN5112,RN5113,RN5114,RN5115
A00 20101224 93 EE Un-stuff 1D8V_S0_VGA_PG related circuit at X-Build stage.
A00 20101224 EE Rename PRN3901 to PN3901. Rename PTC4101~PTC4103 to PT4101~PT4103. Rename LINEOUT1 to LOUT1. Rename PWRBTN1 to PWRBT1. Rename HALLSW1 to LID1.
A00 20101224 27 EE Change R2724 to 47K from 33K.
A00 20101224 28 EE If stuff P2800EA1 then must stuff R2803,R2804 C2805 but if stuff P28003B0 should be un-stuff.
A00 20101224 93 EE Change PR9311,PR9327 to short pad at X-Build.
C A00 20101227 32,42,46 EE Change R3210,R3211,PR4217~PR4220,PR4254;PR4605,PR4607,PR4611,PR4602;R4908,R4909,R4919,R4920,R4903,R4910,R4913~R4916R4917,R4918; R5013~R5016; R6205; R6403,R6404;R6511;R6902;R7002;R8409;R8524;R8605 ;R8812,R8830to 0R 0402 pad. C
62,64,65
70,84~86
88
A00 20101228 93 EE Change PR9320 to short pad at X-Build.
A00 20101228 23 EE 0402 0R pad: R2301.
A00 20101228 27,62,82 EE VGA_THRM change to USB_PWR_EN.
A00 20101228 27 EE Change R2756,R2763,R2766 to 0R short pad.
A00 20101228 28 EE Un-stuff U2805 G709T1UF related circuit and R2812 then stuff R2805 at X-Build.
A00 20101229 86 EE Change C8601 to 10uF 0805 size.
A00 20101229 71 EE DB1 change to ZZ.00PAD.Y41(solder mask type) and keep un-stuff at X-Build stage.
B B
A00 20101229 27,62,82 EE Rename USB_PWR_EN to USB3_PWR_ON. Remove R6205,R620. Remove R2809 and R8210. Connect USB3_PWR_ON from KBC to IOBD1.61.
A00 20101230 41,65,85 EE Change PR4119 to 0R short pad. Change PR4114 to 0R short pad. Change R6406,R6405 to 0R short pad. Change PR4115 to 0R0603 short pad. Change PR4116 to 0R0603 short pad. Change R6510 to 0R 0603 pad. Change R8512 to 0R0603 short pad.
Change PR4103,PR4104 to 0R0805 short pad.
A00 20101231 43 Power Power/Brian: change PL4201 to 68.2415N.101 from 68.10110.10G.
A00 20101231 42,50,18 EE Change PR4209,PR4212 to PN4201 10k array resistor. Change R5004,R5005 to RN5001 33 ohm array resistor. Merge R1804,R1806 to RN1804 22 ohm array resistor. Merge R1401,R1402 to RN1401 10k ohm array resistor.
14,9,8 Merge R906,R907 to RN902 100 ohm array resistor. Merge R801,R802 to RN801 100 ohm array resistor.
A00 20110103 68,82 EE Change R6801,R8201~R8203 to 1k.
A00 20110103 41 Power Change PR4106 to 0R0603 short pad.
A00 20110104 5 EE merge R512,R514 to RN502 1k array resistor.
A00 20110104 8 EE Swap VCC_CORE to RN801.4 and VCCSENSE to RN801.1.
A A00 20110104 9 EE Swap VCC_GFXCORE to RN902.1 and VCC_AXG_SENSE to RN902.4. <Core Design> A
A00 20110104 14 EE Change RN1401 to 0R short pad.

Wistron Corporation
A00 20110104 15 EE Change R1502 to 0R0402 short pad. Taipei Hsien 221, Taiwan, R.O.C.
Title
A00 20110104 17 EE Merge RN1701,RN1706 to RN1703 2.2k array resistor.
Change History
A00 20110104 22 EE Merge RN2201,R2222,R2223 to 10k array resistor. A3
Nirvana 13 A00
5 4 3 2 1
5 4 3 2 1
Version Date Page Function Change Item
A00 20110104 22 EE Merge RN2215,R2216 to RN2201 10k array resistor.
A00 20110104 32,49,57 EE Remove TR3201,TR4902,R5718,R5719,TR6401,TR6501.

64,65
A00 20110104 68,69 EE Change R6804,R6806,R6808,R6810,R6906 to 620 ohm 5%.
A00 20110104 82 EE Merge R8201~R8203 to RN8201 1k array resistor.

D D
A00 20110105 85 EE Change L8507 to 0 ohm short pad, un-stuff C8526,C8527,Un-stuff C8501 C8502 C8504 C8506 C8511.
A00 20110105 93 EE Change PR9316 to 10k ohm (follow the standard schematics).
A00 20110105 85 EE Un-stuff C8536,C8533,C8534 and change L8501 to 0 ohm short pad.
A00 20110106 93 Power Un-stuff PC9317.
A00 20110107 51 EE Remove RN5112~RN5115.
A00 20110107 68,69 EE Change R6804,R6806,R6808,R6810,R6906 to 1k ohm 5%.
A00 20110107 49 EE Change F4902 to 0603 0 ohm.
A00 20110110 21 EE Merge R2115,R2116 to RN2101.
A00 20110110 41 Power Change PG4110,PG4112,PG4114~PG4119,PG4122,PG4126,PG4129,PG4131,PG4133,PG4135~PG4138,PG4140,PG4142,PG4102~PG4109,PG4111,PG4113,PG4118,PG4120,PG4123,PG4101,PG4127,PG4130,PG4132,PG4134, PG4139,PG4141 to ZZ.CLOSE.001.
C A00 20110111 49,51 EE Change R4908,R4909,R4903,R4910,R4913~R4916 R4917,R4918 to 0R 0402 reisstors. Change RN5112~RN5115 to 0R array resistors. Change RN5117 to 0 ohm resistor. C
A00 20110112 20 EE Change C2007,C2008 to 15pF from 12pF base on vendor's report.
A00 20110112 85 EE Change C8524,C8525 to 18pF from 12pF base on vendor's report.
A00 20110113 8,9 EE Change RN801,RN902 to 100 ohm 1% (66.10156.04L).
A00 20110113 22 EE Combine PCH_TEMP_ALERT#,MFG_MODE to RN2202. Combine EC_SCI#,DGPU_HPD_INTR# to RN2204.
A00 20110113 5,8,14, EE Swap RN502,RN801,RN1401,RN1804,RN2101,PN4201, RN8201 base on swap report. Swap RN1703.7,RN1703.5. swap RN1703.8,RN1703.6
21,42,17
18,82
A00 20110117 42 EE Swap PN4201 base on the swap report.
A00 20110118 8 EE Change C823, C824, C825 to 22uF from 10uF (0805 size). Reserve C846~C848 22uF (0805 size).
A00 20110118 51 EE Remove RN5117 for PCH_HDMI_CLK and PCH_HDMI_DATA.

B B
A <Core Design> A
Wistron Corporation
Title
Change History
A3
Nirvana 13 A00
5 4 3 2 1

Nirvana 13 Discrete GDDR5 Schematics Document Sandy Bridge

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5 4 3 2 1

Nirvana 13 Discrete GDDR5 Schematics Document

10mW: External circuit for 10mW solution installed.

USB2.0 x 1 USB CHARGE ESATA/USB 47

TLS Confidentiality 5V_USBX_S3 5V

On-Die PLL Voltage Regulator

LANE8 X PCH_SMBDATA/PCH_SMBCLK Table of Content

PCI EXPRESS* - GRAPHICS

Stuff to disable internal graphics

AN33 R8 4K99R2F-L-GP SM_DRAMRST# (37)

1R503 2 H_CPUPWRGD_R AP29

JTAG & BPM

Buffered reset to CPU 75R2J-1-GP

DDR SYSTEM MEMORY B

M_A_DQ33 SA_DQ32 SA_ODT3 M_B_DQ33 SB_DQ32 SB_ODT3

RSVD#G25 RSVD#AK32 R705

PEG AND DDR

VCC H_CPU_SVIDALRT# R803

VCC Merge R801,R802 to RN801 100 ohm array resistor.

VAXG Output Decoupling Recommendation:

DDR3 -1.5V RAILS

VCCSA_VID1 VCCSA_SEL (48)

Size Document Number

AT35 VSS VSS AJ22

M_A_A12 A11 CKE1

M_A_DQ10 DQ9 3D3V_S0

M_A_DQ19 DQ18 NC#2 1D5V_S3

M_A_DQ22 DQ21 VDD1

M_A_DQ52 DQ51 VSS

M_A_DQ53 DQ52 VSS

M_A_DQ56 DQ55 VSS

M_B_DQ5 DQ4 DM6 20100104 A00:

M_B_DQ10 DQ9 3D3V_S0

M_B_DQ31 DQ30 VDD10

M_B_DQ36 DQ35 VDD15

M_B_DQ43 DQ42 VSS

M_B_DQ63 DQ62 VSS

M_B_DQS#1 DQS0# VSS

(49) L_BKLT_CTRL P45 L_BKLTCTL

Digital Display Interface

20101224 A00: 11 Mini Card1 (WLAN)

R1816 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

USB_OC#2_3 1 10 3D3V_S5 Title

SC220P50V2KX-3GP R1818 10KR2J-3-GP USB_OC#6_7 USB_OC#8_9

1 2 FFS_INT2_R USB_OC#0_1 4 7 USB_OC#10_11

SSID = PCH (4) DMI_RXN[3:0]

System Power Management

(5) XDP_DBRESET# 1 2 SYS_RESET# K3 B9 PCH_W AKE# (27)

(27) SUS_PW R_ACK K16 SUSWARN#/SUSPWRDNACK/GPIO30 SLP_S3# F4 PM_SLP_S3# (27,36,37,46,47) RTC_AUX_S5

(27) PM_PW RBTN# E20 G10 PM_SLP_A# 1

(27) AC_PRESENT H20 G16 PM_SLP_SUS# 1

PM_RI# A10 K14 PM_SLP_LAN# 1

R1922 2 1 10KR2J-3-GP PM_PW RBTN#

2 R1908 1 PM_RSMRST# PCH 3/9(DM I/FDI/PM)

86%&/. 2 3 CLK_PCH_SRC4_P Y45 DY

V45 K45 CLK_BUF_REF14

V38 CLKOUT_PCIE7N CLKOUTFLEX0/GPIO64 K43 JTAG_TCK 1R2001 DY2 JTAG_TCK_VGA (83,85)

– Prioritize 27/14/24/48/25-MHz FLEX on FLEX1 and FLEX3 PCH 4/9(PCI-E/SMBUS/CLOCK/CL)

TPAD14-GP TP2101 PCH_JTAG_TCK_BUF

NO REBOOT STRAP TPAD14-GP TP2102 1 PCH_JTAG_TMS H7 Y11 1D05V_VTT

AB13 SATA3_COMP R2113 1 2 49D9R2F-GP

+3VS_+1.5VS_HDA_IO 1 2 PCH_SPI_CLK T3 AH1 RBIAS_SATA3 R2114 1 2 750R2F-GP

SRN10KJ-5-GP Taipei Hsien 221, Taiwan, R.O.C.

86%&/. 2 3 CLK_PCH_SRC4_P Y45 DY

84.03904.L06 C2806 1 5 VCC TDR 4 SYS_THRM (27) Layout 15 mil