5 4 3 2 1

D D

Round Rock MLK 13.3" Schematics Document

Broadwell ULT

C C

2015-08-19
REV : A00
DY : None Installed
B
XDP: For CPU XDP Debug Port installed B

PCH_XDP: For PCH XDP Debug Port installed

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Cover Page
Size Document Number Rev
A3 A00
Round Rock MLK 13.3"
Date: W ednesday, August 19, 2015 Sheet 1 of 110
5 4 3 2 1
 5 4 3 2 1

CHARGER
Project code : 4PD06F010001 BQ24777 44
PCB P/N : 15203 INPUTS OUTPUTS

Round Rock MLK 13.3" Block Diagram Revision : A00 AD+

BT+

SYSTEM DC/DC
DCBATOUT

TPS51275 45
INPUTS OUTPUTS
3D3V_AUX_S5
3D3V_S5
DCBATOUT 5V_S5
DDR3L Channel A DDR3L Slot A
D D
1333/1600MHz 12 CPU DC/DC
eDP 13.3" Panel eDP 1-lane
52 TPS51624 46~47
Intel CPU DDR3L Channel B DDR3L Slot B INPUTS OUTPUTS
1333/1600MHz 13 DCBATOUT VCC_CORE
BroadWell-U
Touch Panel USB2.0 SYSTEM DC/DC
98 15W SATA GEN3 / PCIE GEN2 SY8206DQNC 48
INPUTS OUTPUTS
Camera DCBATOUT 1D05V_M
52 USB2.0 USB2.0 NGFF Micro SIM
60 SYSTEM DC/DC 49
Internal Digital MIC WWAN
WPT_LP SY8206DQNC & APL5338
10/100/1000 Lan USB3.0 59 INPUTS OUTPUTS
8 USB 2.0/1.1 ports
RJ45 LAN Realtek PCIE GEN1 1D35V_S3
4 USB 3.0 ports DCBATOUT 0D675V_S0
31 RTL8111HSD-CG 30 DDR_VREF_S3
High Definition Audio PCIE
4 SATA ports
NGFF Load Switches 36
HDMI 54 DDI1
6 PCIE ports 802.11a/b/g/n INPUTS OUTPUTS
USB2.0 5V_S5 5V_S0
LPC I/F BT V4.0 combo 58 3D3V_S5 3D3V_S0
3D3V_S5_PCH
mini DP 55 DDI2 ACPI 4.0a 3D3V_M
3D3V_LAN
1D05V_MODPHY
HDD 2.5" 1D05V_M 1D05V_S0
SATA GEN3 7 mm M.2 SSD
C C

56 PCB LAYER(FR4-6 Layer)

L1:Top L6:Bottom
L2:PWR/GND
L3:Signal
SM Bus Free Fall Sensor L4:Signal
ST Micro - LNG2DM L5:PWR/GND
USB Port : 1 USB3.0
67
USB3.0 / PowerShare
USB2.0
USB PowerShare USB2.0
34 Pericom 35
PI5USB2544

USB Port : 2
(Debug Port)
USB2.0 USB3.0
USB 3.0
34

B
LPC debug port LPC BUS B
65
Card Reader
PCIE Gen2 Connector
Realtek
SD/SDHC/SDXC/SD SDIO UHS2
RTS5242 32
(SD4.0) 33
4,5,6,7,8,9,10,15,16
EC 17,18,19,20,21,22,23
SMSC 25
MEC 5085 24
BC
Audio Codec
SPI

PS2 BC
HDA RealTek Universal Jack
ALC3234 27
Touch Pad KBC SIO Expander
Thermal & Fan Int KB
26 62
ECE1117c 62 ECE 1099 99 2CH Speaker
( 2W, 4ohm /channel )

TPM
Flash ROM
25 Nuvoton
8 MB
NPCT650JA0YX 88
A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Block Diagram
Size Document Number Rev
A2 A00
Round Rock MLK 13.3"
Date: Monday, August 17, 2015 Sheet 2 of 110

5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (PCIE/DMI/FDI)
Size Document Number Rev
A4 A00
Round Rock MLK 13.3"
Date: Monday, August 17, 2015 Sheet 3 of 110
5 4 3 2 1
 5 4 3 2 1

SSID = CPU
+V1.05S_VCCST

R401 1 2 62R2J-GP H_PROCHOT#

D D

HSW_ULT_DDR3L
CPU1B 2 OF 19

D61 PROC_DETECT#
1 H_CATERR# K61 MISC
TP402 CATERR#
R402 1 2 H_PECI_R N62 J62 XDP_PRDY# 96
24 H_PECI PECI PRDY#
0R0402-PAD-2-GP K62 XDP_PREQ# 96
PREQ#
PROC_TCK E60 XDP_TCK 96
PROC_TMS E61 XDP_TMS 96
R404 1 2 56R2J-4-GP H_PROCHOT#_R K63 JTAG E59
24,44,46 H_PROCHOT# PROCHOT# PROC_TRST# XDP_TRST# 19,96
THERMAL F63
PROC_TDI XDP_TDI 96
PROC_TDO F62 XDP_TDO 96
SM_DRAMRST#
R405 1 2 10KR2J-3-GP H_CPUPWRGD C61 PROCPWRGD
1

PWR
J60 XDP_BPM0 XDP_BPM0 96
ED401 BPM#0

1
EC401 H60 XDP_BPM1 XDP_BPM1 96
DY AZ5725-01FDR7G-GP BPM#1 XDP_BPM2
DY SC1KP50V2KX-1GP BPM#2 H61
XDP_BPM3
1 TP401
C
EV EMC H62 1 TP403
C
2 SM_RCOMP_0 BPM#3 XDP_BPM4
AU60 SM_RCOMP0 BPM#4 K59 1 TP404
SM_RCOMP_1 DDR3L XDP_BPM5
2

AV60 SM_RCOMP1 BPM#5 H63 1 TP405

SM_RCOMP_2 AU61 K60 XDP_BPM6 1
SM_RCOMP2 BPM#6 TP406
SM_DRAMRST# AV15 J61 XDP_BPM7 1
SM_DRAMRST# BPM#7 TP407
14 DDR_PG_CTRL AV61 SM_PG_CNTL1

HASWELL-6-GP-U
+V1.05S_VCCST
71.HASWE.G0U
XDP_TMS R406 1 XDP 2 51R2J-2-GP
Design Guideline: XDP_TDI R407 1 XDP 2 51R2J-2-GP
SM_RCOMP keep routing length less than 500 mils. XDP_TDO R409 1 2 51R2J-2-GP

R408 1 2 200R2F-L-GP SM_RCOMP_0 XDP_TCK R412 1 2 51R2J-2-GP

R410 1 2 121R2F-GP SM_RCOMP_1 EV follow PDG XDP_TRST# R413 1 XDP 2 51R2J-2-GP
B R411 1 2 100R2F-L1-GP-U SM_RCOMP_2 B

1
EC402
DY SC1KP50V2KX-1GP

2
EV EMC
Layout Note: Colse to DIMM
XDP_BPM0R414 1 DY 2 0R2J-2-GP XDP_BPM1
1D35V_S3
1

R415 <Core Design>

470R2J-2-GP

Wistron Corporation
2

A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, A

SM_DRAMRST# R416 1 2 0R0402-PAD-2-GP DDR3_DRAMRST#_1 12 Taipei Hsien 221, Taiwan, R.O.C.
R417 1 2 0R0402-PAD-2-GP DDR3_DRAMRST#_2 13 Title
CPU (THERMAL/CLOCK/PM )
Size Document Number Rev
A4 A00
Round Rock MLK 13.3"
Date: Monday, August 17, 2015 Sheet 4 of 110
5 4 3 2 1
 5 4 3 2 1

SSID = CPU

D D

HSW_ULT_DDR3L 3 OF 19 HSW_ULT_DDR3L 4 OF 19
CPU1C CPU1D

12 M_A_DQ[63:0]
M_A_DQ0 AH63 AU37
SA_DQ0 SA_CLK#0 M_A_DIM0_CLK_DDR#0 12 13 M_B_DQ[63:0]
M_A_DQ1 AH62 AV37 M_B_DQ0 AY31 AM38
M_A_DQ2 SA_DQ1 SA_CLK0 M_A_DIM0_CLK_DDR0 12 M_B_DQ1 SB_DQ0 SB_CK#0 M_B_DIM0_CLK_DDR#0 13
AK63 AW36 AW31 AN38
M_A_DQ3 SA_DQ2 SA_CLK#1 M_A_DIM0_CLK_DDR#1 12 M_B_DQ2 SB_DQ1 SB_CK0 M_B_DIM0_CLK_DDR0 13
AK62 AY36 AY29 AK38
M_A_DQ4 SA_DQ3 SA_CLK1 M_A_DIM0_CLK_DDR1 12 M_B_DQ3 SB_DQ2 SB_CK#1 M_B_DIM0_CLK_DDR#1 13
AH61 AW29 AL38
M_A_DQ5 SA_DQ4 M_B_DQ4 SB_DQ3 SB_CK1 M_B_DIM0_CLK_DDR1 13
AH60 AU43 AV31
M_A_DQ6 SA_DQ5 SA_CKE0 M_A_DIM0_CKE0 12 M_B_DQ5 SB_DQ4
AK61 AW43 AU31 AY49
M_A_DQ7 SA_DQ6 SA_CKE1 M_A_DIM0_CKE1 12 M_B_DQ6 SB_DQ5 SB_CKE0 M_B_DIM0_CKE0 13
AK60 AY42 AV29 AU50
M_A_DQ8 SA_DQ7 SA_CKE2 M_B_DQ7 SB_DQ6 SB_CKE1 M_B_DIM0_CKE1 13
AM63 AY43 AU29 AW49
M_A_DQ9 SA_DQ8 SA_CKE3 M_B_DQ8 SB_DQ7 SB_CKE2
AM62 AY27 AV50
M_A_DQ10 SA_DQ9 M_B_DQ9 SB_DQ8 SB_CKE3
AP63 AP33 AW27
M_A_DQ11 SA_DQ10 SA_CS#0 M_A_DIM0_CS#0 12 M_B_DQ10 SB_DQ9
AP62 AR32 AY25 AM32
M_A_DQ12 SA_DQ11 SA_CS#1 M_A_DIM0_CS#1 12 M_B_DQ11 SB_DQ10 SB_CS#0 M_B_DIM0_CS#0 13
AM61 AW25 AK32
M_A_DQ13 SA_DQ12 SB_DQ11 SB_CS#1 M_B_DIM0_CS#1 13
AM60 AP32 TP_M_A_DIM0_ODT0 1 TP501
M_B_DQ12 AV27
M_A_DQ14 SA_DQ13 SA_ODT0 M_B_DQ13 SB_DQ12
AP61 AU27 AL32 TP_M_B_DIM0_ODT0 1 TP502
M_A_DQ15 SA_DQ14 M_B_DQ14 SB_DQ13 SB_ODT0
AP60 AY34 M_A_RAS# 12 AV25
M_A_DQ16 SA_DQ15 SA_RAS# M_B_DQ15 SB_DQ14
AP58 AW34 M_A_WE# 12 AU25 AM35 M_B_RAS# 13
M_A_DQ17 SA_DQ16 SA_WE# M_B_DQ16 SB_DQ15 SB_RAS#
AR58 AU34 M_A_CAS# 12 AM29 AK35 M_B_WE# 13
M_A_DQ18 SA_DQ17 SA_CAS# M_B_DQ17 SB_DQ16 SB_WE#
AM57 AK29 AM33 M_B_CAS# 13
M_A_DQ19 SA_DQ18 M_B_DQ18 SB_DQ17 SB_CAS#
AK57 AU35 M_A_BS0 12 AL28
M_A_DQ20 SA_DQ19 SA_BA0 M_B_DQ19 SB_DQ18
AL58 AV35 M_A_BS1 12 AK28 AL35 M_B_BS0 13
M_A_DQ21 SA_DQ20 SA_BA1 M_B_DQ20 SB_DQ19 SB_BA0
AK58 AY41 M_A_BS2 12 AR29 AM36 M_B_BS1 13
M_A_DQ22 SA_DQ21 SA_BA2 M_B_DQ21 SB_DQ20 SB_BA1
AR57 M_A_A[15:0] 12 AN29 AU49 M_B_BS2 13
M_A_DQ23 SA_DQ22 M_A_A0 M_B_DQ22 SB_DQ21 SB_BA2
AN57 AU36 AR28
M_A_DQ24 SA_DQ23 SA_MA0 M_A_A1 M_B_DQ23 SB_DQ22 M_B_A0 M_B_A[15:0] 13
AP55 AY37 AP28 AP40
M_A_DQ25 SA_DQ24 SA_MA1 M_A_A2 M_B_DQ24 SB_DQ23 SB_MA0 M_B_A1
AR55 AR38 AN26 AR40
M_A_DQ26 SA_DQ25 SA_MA2 M_A_A3 M_B_DQ25 SB_DQ24 SB_MA1 M_B_A2
AM54 AP36 AR26 AP42
M_A_DQ27 SA_DQ26 SA_MA3 M_A_A4 M_B_DQ26 SB_DQ25 SB_MA2 M_B_A3
C AK54 AU39 AR25 AR42 C
M_A_DQ28 SA_DQ27 SA_MA4 M_A_A5 M_B_DQ27 SB_DQ26 SB_MA3 M_B_A4
AL55 AR36 AP25 AR45
M_A_DQ29 SA_DQ28 SA_MA5 M_A_A6 M_B_DQ28 SB_DQ27 SB_MA4 M_B_A5
AK55 AV40 AK26 AP45
M_A_DQ30 SA_DQ29 SA_MA6 M_A_A7 M_B_DQ29 SB_DQ28 SB_MA5 M_B_A6
AR54 AW39 AM26 AW46
M_A_DQ31 SA_DQ30 DDR CHANNEL A SA_MA7 M_A_A8 M_B_DQ30 SB_DQ29 SB_MA6 M_B_A7
AN54 AY39 AK25 AY46
M_A_DQ32 SA_DQ31 SA_MA8 M_A_A9 M_B_DQ31 SB_DQ30 SB_MA7 M_B_A8
AY58 AU40 AL25 AY47
M_A_DQ33 SA_DQ32 SA_MA9 M_A_A10 M_B_DQ32 SB_DQ31 DDR CHANNEL B SB_MA8 M_B_A9
AW58 AP35 AY23 AU46
M_A_DQ34 SA_DQ33 SA_MA10 M_A_A11 M_B_DQ33 SB_DQ32 SB_MA9 M_B_A10
AY56 AW41 AW23 AK36
M_A_DQ35 SA_DQ34 SA_MA11 M_A_A12 M_B_DQ34 SB_DQ33 SB_MA10 M_B_A11
AW56 AU41 AY21 AV47
M_A_DQ36 SA_DQ35 SA_MA12 M_A_A13 M_B_DQ35 SB_DQ34 SB_MA11 M_B_A12
AV58 AR35 AW21 AU47
M_A_DQ37 SA_DQ36 SA_MA13 M_A_A14 M_B_DQ36 SB_DQ35 SB_MA12 M_B_A13
AU58 AV42 AV23 AK33
M_A_DQ38 SA_DQ37 SA_MA14 M_A_A15 M_B_DQ37 SB_DQ36 SB_MA13 M_B_A14
AV56 AU42 AU23 AR46
M_A_DQ39 SA_DQ38 SA_MA15 M_B_DQ38 SB_DQ37 SB_MA14 M_B_A15
AU56 M_A_DQS#[7:0] 12 AV21 AP46
M_A_DQ40 SA_DQ39 M_A_DQS#0 M_B_DQ39 SB_DQ38 SB_MA15
AY54 AJ61 AU21 M_B_DQS#[7:0] 13
M_A_DQ41 SA_DQ40 SA_DQSN0 M_A_DQS#1 M_B_DQ40 SB_DQ39 M_B_DQS#0
AW54 AN62 AY19 AW30
M_A_DQ42 SA_DQ41 SA_DQSN1 M_A_DQS#2 M_B_DQ41 SB_DQ40 SB_DQSN0 M_B_DQS#1
AY52 AM58 AW19 AV26
M_A_DQ43 SA_DQ42 SA_DQSN2 M_A_DQS#3 M_B_DQ42 SB_DQ41 SB_DQSN1 M_B_DQS#2
AW52 AM55 AY17 AN28
M_A_DQ44 SA_DQ43 SA_DQSN3 M_A_DQS#4 M_B_DQ43 SB_DQ42 SB_DQSN2 M_B_DQS#3
AV54 AV57 AW17 AN25
M_A_DQ45 SA_DQ44 SA_DQSN4 M_A_DQS#5 M_B_DQ44 SB_DQ43 SB_DQSN3 M_B_DQS#4
AU54 AV53 AV19 AW22
M_A_DQ46 SA_DQ45 SA_DQSN5 M_A_DQS#6 M_B_DQ45 SB_DQ44 SB_DQSN4 M_B_DQS#5
AV52 AL43 AU19 AV18
M_A_DQ47 SA_DQ46 SA_DQSN6 M_A_DQS#7 M_B_DQ46 SB_DQ45 SB_DQSN5 M_B_DQS#6
AU52 AL48 AV17 AN21
M_A_DQ48 SA_DQ47 SA_DQSN7 M_B_DQ47 SB_DQ46 SB_DQSN6 M_B_DQS#7
AK40 M_A_DQS[7:0] 12 AU17 AN18
M_A_DQ49 SA_DQ48 M_A_DQS0 M_B_DQ48 SB_DQ47 SB_DQSN7
AK42 AJ62 AR21 M_B_DQS[7:0] 13
M_A_DQ50 SA_DQ49 SA_DQSP0 M_A_DQS1 M_B_DQ49 SB_DQ48 M_B_DQS0
AM43 AN61 AR22 AV30
M_A_DQ51 SA_DQ50 SA_DQSP1 M_A_DQS2 M_B_DQ50 SB_DQ49 SB_DQSP0 M_B_DQS1
AM45 AN58 AL21 AW26
M_A_DQ52 SA_DQ51 SA_DQSP2 M_A_DQS3 M_B_DQ51 SB_DQ50 SB_DQSP1 M_B_DQS2
AK45 AN55 AM22 AM28
M_A_DQ53 SA_DQ52 SA_DQSP3 M_A_DQS4 M_B_DQ52 SB_DQ51 SB_DQSP2 M_B_DQS3
AK43 AW57 AN22 AM25
M_A_DQ54 SA_DQ53 SA_DQSP4 M_A_DQS5 M_B_DQ53 SB_DQ52 SB_DQSP3 M_B_DQS4
AM40 AW53 AP21 AV22
M_A_DQ55 SA_DQ54 SA_DQSP5 M_A_DQS6 M_B_DQ54 SB_DQ53 SB_DQSP4 M_B_DQS5
AM42 AL42 AK21 AW18
M_A_DQ56 SA_DQ55 SA_DQSP6 M_A_DQS7 M_B_DQ55 SB_DQ54 SB_DQSP5 M_B_DQS6
AM46 AL49 AK22 AM21
M_A_DQ57 SA_DQ56 SA_DQSP7 M_B_DQ56 SB_DQ55 SB_DQSP6 M_B_DQS7
AK46 AN20 AM18
M_A_DQ58 SA_DQ57 M_B_DQ57 SB_DQ56 SB_DQSP7
AM49 AP49 +V_SM_VREF_CNT 14 AR20
M_A_DQ59 SA_DQ58 SM_VREF_CA M_B_DQ58 SB_DQ57
AK49 AR51 DDR_WR_VREF01 14 AK18
M_A_DQ60 SA_DQ59 SM_VREF_DQ0 M_B_DQ59 SB_DQ58
AM48 AP51 DDR_WR_VREF02 14 AL18
M_A_DQ61 SA_DQ60 SM_VREF_DQ1 M_B_DQ60 SB_DQ59
AK48 AK20
M_A_DQ62 SA_DQ61 M_B_DQ61 SB_DQ60
AM51 AM20
M_A_DQ63 SA_DQ62 M_B_DQ62 SB_DQ61
AK51 AR18
SA_DQ63 M_B_DQ63 SB_DQ62
AP18
SB_DQ63

B B

HASWELL-6-GP-U HASWELL-6-GP-U

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
CPU (DDR)
Size Document Number Rev
A2 A00
Round Rock MLK 13.3"
Date: Monday, August 17, 2015 Sheet 5 of 110
5 4 3 2 1
 5 4 3 2 1

SSID = CPU
EAR-STALL/NOT STALL RESET SEQUENCE AFTER PCU PLL IS LOCKE
0:Lane Reversed
CFG0
1:(Default) Normal Operation; No stall

CFG0
1

D D

R601
DY 1KR2J-1-GP
2

PCH/PCH LESS MODE SELECTION

CPU1S HSW_ULT_DDR3L 19 OF 19
0:Lane Reversed
CFG1
1:(Default) Normal Operation

CFG1 96 CFG[19:0] CFG0 AC60 CFG0 RSVD_TP#AV63 AV63

CFG1 AC62 AU63
CFG1 RSVD_TP#AU63
1

CFG2 AC63
CFG3 CFG2
AA63 CFG3
R602
DY 1KR2J-1-GP CFG4 AA60 C63
CFG5 CFG4 RSVD_TP#C63
Y62 CFG5 RSVD_TP#C62 C62
CFG6 Y61 B43 TP_EDP_SPARE 1
TP601
2

CFG7 CFG6 RSVD#B43

Y60 CFG7
CFG8 V62 A51
CFG9 CFG8 RSVD_TP#A51
V61 CFG9 RSVD_TP#B51 B51
CFG10 V60
C CFG11 CFG10 C
U60 CFG11 RSVD_TP#L60 L60
CFG12 T63
CFG13 CFG12 RESERVED
T62 CFG13 RSVD#N60 N60
CFG14 T61
CFG15 CFG14
T60 CFG15 RSVD#W23 W23
RSVD#Y22 Y22
CFG16 AA62 AY15 OPI_COMP1 R603 1 2 49D9R2F-GP
CFG18 CFG16 PROC_OPI_RCOMP
U63 CFG18
CFG17 AA61 AV62
CFG19 CFG17 RSVD#AV62
U62 CFG19 RSVD#D58 D58

CFG_RCOMP V63 P22

CFG_RCOMP VSS
VSS N21

1
A5 RSVD#A5
R604 P20 TP_HVM_CLK# 1
RSVD#P20 TP602
49D9R2F-GP E1 R20 TP_HVM_CLK 1
RSVD#E1 RSVD#R20 TP603
D1 RSVD#D1
J20

2
RSVD#J20
H18 RSVD#H18
TD_IREF B12 TD_IREF

1
Display Port Presence Strap HASW ELL-6-GP-U
R605
1 : Disabled; No Physical Display Port 8K2R2F-1-GP
attached to Embedded Display Port
CFG4

2
0 : Enabled; An external Display Port device is
B
connected to the Embedded Display Port B

CFG4
1

R606
1KR2J-1-GP
2

ALLOW THE USE OF NOA ON LOCKED UNITS NO SVID PROTOCOL CAPABLE VR CONNECTED SAFE MODE BOOT
1: Enable(Default): Noa will be disable in 1: VRS support SVID protocol are present 1: POWER FEATURES ACTIVATED DURING
locked units and enable in un-locked units RESET
CFG8 CFG9 0:No VR support SVID is present CFG10
0: Enable Noa will be available pegardless of The chip will not generate(OR Respond to) 0: POWER FEATURES (ESPECIALLY CLOCK
the locking of the unit SVID activity GATINE ARE NOT ACTIVATED

CFG8 CFG9 CFG10

1

A R607
DY 1KR2J-1-GP R608
DY 1KR2J-1-GP R609
DY 1KR2J-1-GP <Core Design> A
2

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (XDP)
Size Document Number Rev
A3 A00
Round Rock MLK 13.3"
Date: Monday, August 17, 2015 Sheet 6 of 110
5 4 3 2 1
 5 4 3 2 1

SSID = CPU

VCC_CORE
HSW_ULT_DDR3L 12 OF 19
D CPU1L D

L59 RSVD#L59 VCC C36

1D35V_S3 J58 C40
RSVD#J58 VCC
VCC C44
AH26 VDDQ VCC C48
AJ31 VDDQ VCC C52
AJ33 VDDQ VCC C56
AJ37 VDDQ VCC E23
AN33 E25
VDDQ VCC
AP43 VDDQ VCC E27
AR48 VDDQ VCC E29
AY35 E31
VDDQ VCC
AY40 E33
VDDQ VCC
AY44 E35
VDDQ VCC
AY50 E37
VDDQ VCC
VCC E39
VCC_CORE F59 E41
VCC_CORE VCC VCC
Layout Note: R702 should be placed within 2 N58
AC58
RSVD#N58 VCC E43
E45
R702 1 RSVD#AC58 VCC
inches (50.8 mm) of the processor. 2 100R2F-L1-GP-U VCC E47
46 VCC_SENSE E63 E49
VCC_SENSE VCC
AB23 RSVD#AB23 VCC E51
1 VCCIO_OUT A59 E53
TP702 VCCIO_OUT VCC
VCCIOA_OUT E20 VCCIOA_OUT VCC E55
AD23 E57
RSVD#AD23 VCC
AA23 F24
RSVD#AA23 VCC
AE59 F28
RSVD#AE59 VCC
F32
R703 1 H_CPU_SVIDALRT# VCC
C 2 43R2J-GP L62 F36 C
46 VR_SVID_ALERT# VIDALERT# HSW ULT POWER VCC
46 H_CPU_SVIDCLK N63 F40
R701 1 0R0402-PAD-2-GP H_CPU_SVIDDAT_R VIDSCLK VCC
46 H_CPU_SVIDDAT 2 L63 VIDSOUT VCC F44
R704 1 2 0R0402-PAD-2-GP H_VCCST_PW RGD_R B59 F48
36,96 H_VCCST_PW RGD R705 1 0R0402-PAD-2-GP H_VR_ENABLE_R VCCST_PWRGD VCC
36,46 H_VR_ENABLE 2 F60 VR_EN VCC F52
R706 1 2 0R0402-PAD-2-GP H_VR_READY_R C59 F56
36 H_VR_READY VR_READY VCC
VCC G23
D63 VSS VCC G25
96 PW R_DEBUG H59 G27
PWR_DEBUG# VCC
P62 VSS VCC G29
+V1.05S_VCCST RSVD_TP_P60 P60
EV
close to CPU TP703
TP704
1
1 RSVD_TP_P61 P61 RSVD_TP#P60
RSVD_TP#P61
VCC
VCC
G31
G33
1 RSVD_TP_N59 N59 G35
TP705 RSVD_TP#N59 VCC
R707 1 2 130R2F-1-GP H_CPU_SVIDDAT_R 1 RSVD_TP_N61 N61 G37
TP701 RSVD_TP#N61 VCC
1 RSVD_T59 T59 G39
TP706 RSVD#T59 VCC
R708 1 2 75R2F-2-GP VR_SVID_ALERT# 1 RSVD_AD60 AD60 G41
TP707 RSVD#AD60 VCC
1 RSVD_AD59 AD59 G43
TP708 RSVD#AD59 VCC
1 RSVD_AA59 AA59 G45
TP709 RSVD#AA59 VCC
1 RSVD_AE60 AE60 G47
TP710 RSVD#AE60 VCC
1 RSVD_AC59 AC59 G49
TP711 RSVD#AC59 VCC
1 RSVD_AG58 AG58 G51
1D05V_S0 +V1.05S_VCCST TP712 RSVD#AG58 VCC
1 RSVD_U59 U59 G53
+V1.05S_VCCST TP713 RSVD#U59 VCC
1 RSVD_V59 V59 G55
TP714 RSVD#V59 VCC
VCC G57
R709 1 2 0R0603-PAD-2-GP-U AC22 H23
VCCST VCC
1

C701 AE22 J23

SC1U10V2KX-1GP
VCCST VCC
1
R710 VCC_CORE AE23 K23
150R2J-L1-GP-U DY VCCST VCC
K57
VCC
AB57 L22
2

B VCC VCC B
AD57 M23
2

PW R_DEBUG VCC VCC

AG57 M57
VCC VCC
C24 P57
VCC VCC
1

C28 U57
R711 VCC VCC
C32 W57
VCC VCC
DY 10KR2J-3-GP
HASW ELL-6-GP-U
2

H_VCCST_PW RGD_R
1

EC701
DY SC1KP50V2KX-1GP
2

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (VCC_CORE)
Size Document Number Rev
Custom A00
Round Rock MLK 13.3"
Date: Monday, August 17, 2015 Sheet 7 of 110
5 4 3 2 1
 5 4 3 2 1

SSID = CPU

D D

CPU1A HSW_ULT_DDR3L 1 OF 19

54 HDMI_DATA2# C54 DDI1_TXN0 EDP_TXN0 C45 eDP_TXN0_CPU 52

54 HDMI_DATA2 C55 DDI1_TXP0 EDP_TXP0 B46 eDP_TXP0_CPU 52 eDP
54 HDMI_DATA1# B58 DDI1_TXN1 EDP_TXN1 A47
54 HDMI_DATA1 C58 DDI1_TXP1 EDP_TXP1 B47
HDMI 54 HDMI_DATA0# B55 DDI1_TXN2
54 HDMI_DATA0 A55 DDI1_TXP2 EDP_TXN2 C47
54 HDMI_CLK# A57 DDI1_TXN3 EDP_TXP2 C46
54 HDMI_CLK B57 DDI1_TXP3 EDP_TXN3 A49
DDI EDP B49
EDP_TXP3
C
55 DDPC_DATA0# C51 DDI2_TXN0
C
55 DDPC_DATA0 C50 DDI2_TXP0 EDP_AUXN A45 eDP_AUXN_CPU 52
55 DDPC_DATA1# C53 DDI2_TXN1 EDP_AUXP B45 eDP_AUXP_CPU 52
55 DDPC_DATA1 B54 DDI2_TXP1
DP/HDMI 55 DDPC_DATA2# C49 D20 EDP_RCOMP R801 1 2 24D9R2F-L-GP VCCIOA_OUT
DDI2_TXN2 EDP_RCOMP DP_UTIL
55 DDPC_DATA2 B50 DDI2_TXP2 EDP_DISP_UTIL A43 DP_UTIL 52
55 DDPC_DATA3# A53 DDI2_TXN3
55 DDPC_DATA3 B53 DDI2_TXP3

HASWELL-6-GP-U

B DDI HDMI Display Port B

DDI_TXN0 HDMI_DATA2_N DP_LANE0_N

DDI_TXP0 HDMI_DATA2_P DP_LANE0_P
DDI_TXN1 HDMI_DATA1_N DP_LANE1_N
DDI_TXP1 HDMI_DATA1_P DP_LANE1_P
DDI_TXN2 HDMI_DATA0_N DP_LANE2_N
DDI_TXP2 HDMI_DATA0_P DP_LANE2_P
DDI_TXN3 HDMI_CK_N DP_LANE3_N
DDI_TXP3 HDMI_CK_P DP_LANE3_P

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (DDI/EDP)
Size Document Number Rev
A4 A00
Round Rock MLK 13.3"
Date: Monday, August 17, 2015 Sheet 8 of 110
5 4 3 2 1
 5 4 3 2 1

SSID = CPU

CPU1P HSW_ULT_DDR3L 16 OF 19

VSS H17
D D33 H57 D
VSS VSS
D34 VSS VSS J10
D35 VSS VSS J22
D37 VSS VSS J59
D38 VSS VSS J63
D39 VSS VSS K1
D41 VSS VSS K12
D42 VSS VSS L13
D43 VSS VSS L15
D45 VSS VSS L17
D46 VSS VSS L18
D47 VSS VSS L20
D49 VSS VSS L58
D5 VSS VSS L61
D50 VSS VSS L7
D51 VSS VSS M22
D53 VSS VSS N10
D54 VSS VSS N3
D55 VSS VSS P59
D57 VSS VSS P63
C D59 VSS VSS R10 C
D62 VSS VSS R22
D8 VSS VSS R8
E11 VSS VSS T1
E17 VSS VSS T58
F20 VSS VSS U20
F26 VSS VSS U22
F30 VSS VSS U61
F34 VSS VSS U9
F38 VSS VSS V10
F42 VSS VSS V3
F46 VSS VSS V7
F50 VSS VSS W20
F54 VSS VSS W22
F58 VSS VSS Y10
F61 VSS VSS Y59
G18 VSS VSS Y63
G22 VSS
G3 VSS
G5 VSS VSS V58
B G6 VSS VSS AH46 B
G8 VSS VSS V23
H13 VSS VSS_SENSE E62 VSS_SENSE 46
VSS AH16
1

HASWELL-6-GP-U R901 Layout Note: R901 should be placed within 2

100R2F-L1-GP-U
inches (50.8 mm) of the processor.
Net Rule: VCC_SENSE and VSS_SENSE differential signals
2

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (VSS)
Size Document Number Rev
A4 A00
Round Rock MLK 13.3"
Date: Monday, August 17, 2015 Sheet 9 of 110
5 4 3 2 1
 5 4 3 2 1

1D35V_S3

C1001
SC10U6D3V3MX-GP

C1002
SC10U6D3V3MX-GP

C1003
SC10U6D3V3MX-GP

C1004
SC10U6D3V3MX-GP

C1005
SC10U6D3V3MX-GP

C1006
SC10U6D3V3MX-GP

C1007
SC10U6D3V3MX-GP

C1008
SC2D2U6D3V3KX-GP

C1009
SC10U6D3V3MX-GP
D 1 D

1
DY DY
2

2
C C

B B

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (Power CAP1)

Size Document Number Rev
A4 A00
Round Rock MLK 13.3"
Date: Monday, August 17, 2015 Sheet 10 of 110
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
A Taipei Hsien 221, Taiwan, R.O.C. A

Title

CPU (Power CAP2)

Size Document Number Rev
A A00
Round Rock MLK 13.3"
Date: Monday, August 17, 2015 Sheet 11 of 110
5 4 3 2 1
 5 4 3 2 1

SSID = MEMORY

DM1
DQ0 M_A_DQ13
5 M_A_A[15:0] M_A_A0 98 NP1
M_A_A1 A0 NP1
DQ1 M_A_DQ8 97
A1 NP2
NP2
M_A_A2 96
M_A_A3 A2
DQ2 M_A_DQ14 95
A3 RAS#
110 M_A_RAS# 5
D M_A_A4 92 113 D
A4 WE# M_A_WE# 5
DQ3 M_A_DQ10 M_A_A5 91 115 M_A_CAS# 5
M_A_A6 A5 CAS#
DQS1 90
A6 Note:
DQ4 M_A_DQ9 M_A_A7 86 114
A7 CS0# M_A_DIM0_CS#0 5
M_A_A8 89 121 M_A_DIM0_CS#1 5 If SA0 DIM0 = 0, SA1_DIM0 = 0
M_A_A9 A8 CS1#
DQ5 M_A_DQ12 85
A9 SO-DIMMA SPD Address is 0xA0
M_A_A10 107 73 M_A_DIM0_CKE0 5
A10/AP CKE0
DQ6 M_A_DQ15 M_A_A11 84
A11 CKE1
74 M_A_DIM0_CKE1 5 SO-DIMMA TS Address is 0x30
M_A_A12 83
M_A_A13 A12
DQ7 M_A_DQ11 119
A13 CK0
101 M_A_DIM0_CLK_DDR0 5
M_A_A14 80
A14 CK0#
103 M_A_DIM0_CLK_DDR#0 5 If SA0 DIM0 = 1, SA1_DIM0 = 0
M_A_A15
Layout Note: 78
79
A15
102 M_A_DIM0_CLK_DDR1 5
SO-DIMMA SPD Address is 0xA2
5 M_A_BS2 A16/BA2 CK1
Place these caps close to VREF_CA DQ8 M_A_DQ29 CK1#
104 M_A_DIM0_CLK_DDR#1 5 SO-DIMMA TS Address is 0x32
109
M_VREF_CA_DIMMA 5 M_A_BS0 BA0
DQ9 M_A_DQ28 5 M_A_BS1
108
BA1 DM0
11
5 M_A_DQ[63:0] 28
M_A_DQ13 DM1
DQ10 M_A_DQ30 5
DQ0 DM2
46
M_A_DQ8 7 63
M_A_DQ14 DQ1 DM3
DQ11 M_A_DQ31 15
DQ2 DM4
136
DQS3 M_A_DQ10 17 153
DQ3 DM5
C1201
SCD1U16V2KX-3GP

EC1
SCD1U16V2KX-3GP

C1202
SCD1U16V2KX-3GP

DQ12 M_A_DQ25 M_A_DQ9 4 170

1

M_A_DQ12 DQ4 DM6

6 187
M_A_DQ15 DQ5 DM7
DY DQ13 M_A_DQ24 16
DQ6
M_A_DQ11 18 200 PCH_SMBDATA 13,18,67,96
2

M_A_DQ29 DQ7 SDA

DQ14 M_A_DQ27 21
DQ8 SCL
202 PCH_SMBCLK 13,18,67,96
M_A_DQ28 23
M_A_DQ30 DQ9 3D3V_S0
DQ15 M_A_DQ26 33
DQ10 EVENT#
198
M_A_DQ31 35
M_A_DQ25 DQ11
22 199
M_A_DQ24 DQ12 VDDSPD
24
M_A_DQ27 DQ13
DQ16 M_A_DQ44 34 197 C1203

1
M_A_DQ26 DQ14 SA0
36 201
Layout Note: DQ17 M_A_DQ41 M_A_DQ44 39
DQ15 SA1 SCD1U16V2KX-3GP
M_A_DQ41 DQ16
Place these caps close to VREF_DQ 41 77

2
M_A_DQ43 DQ17 NC#1
M_VREF_DQ_DIMMA
DQ18 M_A_DQ43 51
DQ18 NC#2
122
1D35V_S3
M_A_DQ47 53 125
M_A_DQ45 DQ19 NC#/TEST
DQ19 M_A_DQ47 40
DQ20
DQS5 M_A_DQ40 42 75
M_A_DQ42 DQ21 VDD1
DQ20 M_A_DQ45 50
DQ22 VDD2
76
M_A_DQ46 52 81
M_A_DQ51 DQ23 VDD3
C DQ21 M_A_DQ40 57
DQ24 VDD4
82 C
C1204
SCD1U16V2KX-3GP

C1205
SC2D2U10V3KX-1GP

C1206
SCD1U16V2KX-3GP

M_A_DQ50 59 87
DQ25 VDD5
1

DQ22 M_A_DQ42 M_A_DQ49 67 88

M_A_DQ48 DQ26 VDD6
69 93
DY DQ23 M_A_DQ46 M_A_DQ52 56
DQ27 VDD7
94
2

M_A_DQ53 DQ28 VDD8

58 99
M_A_DQ54 DQ29 VDD9 1D35V_S3
68 100
M_A_DQ55 DQ30 VDD10
70 105
M_A_DQ0 DQ31 VDD11
DQ24 M_A_DQ51 129
DQ32 VDD12
106 DM1 DECOUPLING
M_A_DQ1 131 111
M_A_DQ2 DQ33 VDD13
DQ25 M_A_DQ50 141
DQ34 VDD14
112
M_A_DQ6 143 117
DQ35 VDD15

C1207
SC10U6D3V3MX-GP

C1208
SC10U6D3V3MX-GP

C1209
SC10U6D3V3MX-GP

C1210
SC10U6D3V3MX-GP

C1211
SC10U6D3V3MX-GP

C1212
SC10U6D3V3MX-GP

C1213
SC10U6D3V3MX-GP

C1214
SC10U6D3V3MX-GP

C1221
SC10U6D3V3MX-GP

C1222
SC10U6D3V3MX-GP
DQ26 M_A_DQ49 M_A_DQ5 130 118

1
M_A_DQ4 DQ36 VDD16
132 123
M_A_DQ3 DQ37 VDD17
DQ27 M_A_DQ48 140
DQ38 VDD18
124 DY DY DY DY DY DY
DQS6 M_A_DQ7 142

2
M_A_DQ21 DQ39
DQ28 M_A_DQ52 147
DQ40 VSS
2
M_A_DQ20 149 3
M_A_DQ17 DQ41 VSS
DQ29 M_A_DQ53 157
DQ42 VSS
8
M_A_DQ16 159 9
M_A_DQ18 DQ43 VSS
0D675V_S0
DQ30 M_A_DQ54 146
DQ44 VSS
13
M_A_DQ19 148 14
M_A_DQ22 DQ45 VSS
Place these caps DQ31 M_A_DQ55 158
DQ46 VSS
19
M_A_DQ23 160 20
close to VTT1 and VTT2. DQ47 VSS

C1215
SCD1U16V2KX-3GP

C1216
SCD1U16V2KX-3GP
M_A_DQ36 163
DQ48 VSS
25 Layout Note:

1
M_A_DQ33 165 26
M_A_DQ34 DQ49 VSS Place these Caps near DM1.
DQ32 M_A_DQ0 175
DQ50 VSS
31
M_A_DQ38 177 32
C1217
SC1U10V2KX-1GP

C1218
SC1U10V2KX-1GP

C1219
SC1U10V2KX-1GP

2
1

M_A_DQ37 DQ51 VSS

DY DQ33 M_A_DQ1 164
DQ52 VSS
37
M_A_DQ32 166 38
M_A_DQ35 DQ53 VSS
DQ34 M_A_DQ2 174 43
2

M_A_DQ39 DQ54 VSS

176 44
M_A_DQ62 DQ55 VSS
DQ35 M_A_DQ6 181
DQ56 VSS
48
DQS0 M_A_DQ58 183 49
M_A_DQ60 DQ57 VSS
DQ36 M_A_DQ5 191
DQ58 VSS
54
M_A_DQ61 193 55
M_A_DQ63 DQ59 VSS
DQ37 M_A_DQ4 180
DQ60 VSS
60
M_A_DQ59 182 61
M_A_DQ56 DQ61 VSS
DQ38 M_A_DQ3 192
DQ62 VSS
65
M_A_DQ57 194 66
DQ63 VSS
DQ39 M_A_DQ7 VSS
71
B M_A_DQS#1 10 72 B
M_A_DQS#3 DQS0# VSS
27 127
M_A_DQS#5 DQS1# VSS
45 128
M_A_DQS#6 DQS2# VSS
DQ40 M_A_DQ21 62
DQS3# VSS
133
M_A_DQS#0 135 134
M_A_DQS#2 DQS4# VSS
DQ41 M_A_DQ20 152
DQS5# VSS
138
5 M_A_DQS#[7:0] M_A_DQS#4 169 139
M_A_DQS#7 DQS6# VSS
DQ42 M_A_DQ17 186
DQS7# VSS
144
5 M_A_DQS[7:0] 145
M_A_DQS1 VSS
DQ43 M_A_DQ16 12
DQS0 VSS
150
DQS2 M_A_DQS3 29 151
M_A_DQS5 DQS1 VSS
DQ44 M_A_DQ18 47
DQS2 VSS
155
M_A_DQS6 64 156
M_A_DQS0 DQS3 VSS
DQ45 M_A_DQ19 137
DQS4 VSS
161
M_A_DQS2 154 162
M_A_DQS4 DQS5 VSS
DQ46 M_A_DQ22 171
DQS6 VSS
167
M_A_DQS7 188 168
DQS7 VSS
DQ47 M_A_DQ23 VSS
172
116 173
14 M_A_DIM0_ODT0 ODT0 VSS
120 178
14 M_A_DIM0_ODT1 ODT1 VSS
179
VSS
DQ48 M_A_DQ36 M_VREF_CA_DIMMA 126
VREF_CA VSS
184
M_VREF_DQ_DIMMA 1 185
VREF_DQ VSS
DQ49 M_A_DQ33 VSS
189
30 190
4 DDR3_DRAMRST#_1 RESET# VSS
DQ50 M_A_DQ34 VSS
195
C1220
SCD1U16V2KX-3GP

196
1

VSS
DQ51 M_A_DQ38 DY 0D675V_S0 203
VTT1 VSS
205
DQS4 204
VTT2 VSS
206
DQ52 M_A_DQ37 H =4mm
2

DQ53 M_A_DQ32 DDR3-204P-106-GP-U

62.10017.X31
DQ54 M_A_DQ35 2nd = 62.10024.M51
DQ55 M_A_DQ39

DQ56 M_A_DQ62
A A
DQ57 M_A_DQ58
DQ58 M_A_DQ60
DQ59 M_A_DQ61 <Core Design>
DQS7
DQ60 M_A_DQ63
DQ61 M_A_DQ59 Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
DQ62 M_A_DQ56 Taipei Hsien 221, Taiwan, R.O.C.

DQ63 M_A_DQ57 Title

DDR3L-SODIMM1
Size Document Number Rev
A2 A00
Round Rock MLK 13.3"
Date: Monday, August 17, 2015 Sheet 12 of 110

5 4 3 2 1
 5 4 3 2 1

SSID = MEMORY

DM2

M_B_A0 98 NP1
M_B_A1 A0 NP1
DQ0 M_B_DQ8 97
A1 NP2
NP2
M_B_A[15:0] 5 M_B_A2 96
M_B_A3 A2
DQ1 M_B_DQ14 95
A3 RAS#
110 M_B_RAS# 5
M_B_A4 92 113
A4 WE# M_B_WE# 5
DQ2 M_B_DQ10 M_B_A5 91 115
A5 CAS# M_B_CAS# 5
D M_B_A6 90 D
M_B_A7 A6
DQ3 M_B_DQ11 86
A7 CS0#
114 M_B_DIM0_CS#0 5
DQS1 M_B_A8 89 121
A8 CS1# M_B_DIM0_CS#1 5
DQ4 M_B_DQ12 M_B_A9 85
M_B_A10 A9
107 73 M_B_DIM0_CKE0 5
M_B_A11 A10/AP CKE0
DQ5 M_B_DQ9 84
A11 CKE1
74 M_B_DIM0_CKE1 5
M_B_A12 83
M_B_A13 A12
DQ6 M_B_DQ13 119
A13 CK0
101 M_B_DIM0_CLK_DDR0 5
M_B_A14 80 103 M_B_DIM0_CLK_DDR#0 5 Note:
M_B_A15 A14 CK0#
DQ7 M_B_DQ15 78
A15
79
A16/BA2 CK1
102 M_B_DIM0_CLK_DDR1 5
SO-DIMMB SPD Address is 0xA4
5 M_B_BS2
Layout Note: 109
CK1#
104 M_B_DIM0_CLK_DDR#1 5 SO-DIMMB TS Address is 0x34
5 M_B_BS0 BA0
Place these caps close to VREF_CA DQ8 M_B_DQ28 5 M_B_BS1
108
BA1 DM0
11
5 M_B_DQ[63:0] 28
M_VREF_CA_DIMMB M_B_DQ8 DM1
DQ9 M_B_DQ29 5
DQ0 DM2
46 SO-DIMMB is placed farther from
M_B_DQ14 7 63
M_B_DQ10 DQ1 DM3 the Processor than SO-DIMMA
DQ10 M_B_DQ26 15
DQ2 DM4
136
M_B_DQ11 17 153
M_B_DQ12 DQ3 DM5
DQ11 M_B_DQ27 4
DQ4 DM6
170
C1301
SCD1U16V2KX-3GP

EC2
SCD1U16V2KX-3GP

C1302
SCD1U16V2KX-3GP

DQS3 M_B_DQ9 6 187

DQ5 DM7
1

DQ12 M_B_DQ25 M_B_DQ13 16

M_B_DQ15 DQ6
18 200 PCH_SMBDATA 12,18,67,96
M_B_DQ28 DQ7 SDA
DQ13 M_B_DQ24 21 202 PCH_SMBCLK 12,18,67,96
2

M_B_DQ29 DQ8 SCL

23
M_B_DQ26 DQ9 3D3V_S0
DQ14 M_B_DQ30 33
DQ10 EVENT#
198
M_B_DQ27 35
M_B_DQ25 DQ11
DQ15 M_B_DQ31 22
DQ12 VDDSPD
199
M_B_DQ24 24 C1303

1
M_B_DQ30 DQ13
34 197 SCD1U16V2KX-3GP
M_B_DQ31 DQ14 SA0 SA1_DIM1 R1301 1
36 201 2
M_B_DQ40 DQ15 SA1
Layout Note: DQ16 M_A_DQ40 39 10KR2J-3-GP

2
M_B_DQ41 DQ16
41 77
M_B_DQ46 DQ17 NC#1
Place these caps close to VREF_DQ DQ17 M_A_DQ41 51
DQ18 NC#2
122
M_B_DQ42 53 125 1D35V_S3
M_VREF_DQ_DIMMB M_B_DQ45 DQ19 NC#/TEST
DQ18 M_A_DQ46 40
DQ20
M_B_DQ44 42 75
M_B_DQ47 DQ21 VDD1
DQ19 M_A_DQ42 50
DQ22 VDD2
76
DQS5 M_B_DQ43 52 81
M_B_DQ56 DQ23 VDD3
DQ20 M_A_DQ45 57
DQ24 VDD4
82
C1305
SCD1U16V2KX-3GP

C1306
SCD1U16V2KX-3GP

M_B_DQ57 59 87
DQ25 VDD5
1

C DQ21 M_A_DQ44 M_B_DQ59 67 88 C

M_B_DQ58 DQ26 VDD6
69 93
M_B_DQ61 DQ27 VDD7
DQ22 M_A_DQ47 56 94
2

M_B_DQ60 DQ28 VDD8

58 99
M_B_DQ63 DQ29 VDD9
DQ23 M_A_DQ43 68
DQ30 VDD10
100
M_B_DQ62 70 105
M_B_DQ4 DQ31 VDD11
129 106
M_B_DQ1 DQ32 VDD12
131 111
M_B_DQ3 DQ33 VDD13
DQ24 M_A_DQ56 141
DQ34 VDD14
112
M_B_DQ7 143 117
M_B_DQ5 DQ35 VDD15 1D35V_S3
DQ25 M_A_DQ57 130
DQ36 VDD16
118
M_B_DQ0
M_B_DQ2
132
DQ37 VDD17
123 DM2 DECOUPLING
DQ26 M_A_DQ59 140
DQ38 VDD18
124
M_B_DQ6 142
M_B_DQ21 DQ39
DQ27 M_A_DQ58 147
DQ40 VSS
2

C1307
SC10U6D3V3MX-GP

C1308
SC10U6D3V3MX-GP

C1309
SC10U6D3V3MX-GP

C1310
SC10U6D3V3MX-GP

C1311
SC10U6D3V3MX-GP

C1312
SC10U6D3V3MX-GP

C1313
SC10U6D3V3MX-GP

C1314
SC10U6D3V3MX-GP

TC1
ST330U2VDM-4-GP-U

C1322
SCD1U16V2KX-3GP
DQS7 M_B_DQ20 149 3

1
M_B_DQ22 DQ41 VSS
DQ28 M_A_DQ61 157
DQ42 VSS
8
DY
M_B_DQ23 159 9 DY DY DY DY DY
M_B_DQ16 DQ43 VSS
DQ29 M_A_DQ60 146 13

2
M_B_DQ17 DQ44 VSS
148 14
0D675V_S0 M_B_DQ19 DQ45 VSS
Place these caps DQ30 M_A_DQ63 158
DQ46 VSS
19
M_B_DQ18 160 20
close to VTT1 and VTT2. M_B_DQ36 DQ47 VSS
DQ31 M_A_DQ62 163
DQ48 VSS
25
M_B_DQ33 165 26
M_B_DQ35 DQ49 VSS
175 31
M_B_DQ39 DQ50 VSS
177 32
C1315
SC1U10V2KX-1GP

C1316
SC1U10V2KX-1GP

C1317
SC1U10V2KX-1GP
1

M_B_DQ37 DQ51 VSS

DQ32 M_A_DQ4 164
DQ52 VSS
37
DY

C1318
SCD1U16V2KX-3GP

C1319
SCD1U16V2KX-3GP
M_B_DQ32 166 38 Layout Note:

1
M_B_DQ34 DQ53 VSS
DQ33 M_A_DQ1 174 43
2

M_B_DQ38 DQ54 VSS Place these Caps near DM2

176 44
M_B_DQ52 DQ55 VSS
DQ34 M_A_DQ3 181 48

2
M_B_DQ49 DQ56 VSS
183 49
M_B_DQ48 DQ57 VSS
DQ35 M_A_DQ7 191
DQ58 VSS
54
DQS0 M_B_DQ53 193 55
M_B_DQ51 DQ59 VSS
DQ36 M_A_DQ5 180
DQ60 VSS
60
M_B_DQ55 182 61
M_B_DQ54 DQ61 VSS
DQ37 M_A_DQ0 192
DQ62 VSS
65
M_B_DQ50 194 66
DQ63 VSS
DQ38 M_A_DQ2 VSS
71
M_B_DQS#1 10 72
M_B_DQS#3 DQS0# VSS
DQ39 M_A_DQ6 27
DQS1# VSS
127
B M_B_DQS#5 45 128 B
M_B_DQS#7 DQS2# VSS
62 133
M_B_DQS#0 DQS3# VSS
135 134
M_B_DQS#2 DQS4# VSS
DQ40 M_A_DQ21 152
DQS5# VSS
138
M_B_DQS#4 169 139
M_B_DQS#6 DQS6# VSS
DQ41 M_A_DQ20 186
DQS7# VSS
144
145
M_B_DQS1 VSS
DQ42 M_A_DQ22 12
DQS0 VSS
150
M_B_DQS3 29 151
M_B_DQS#[7:0] 5 DQS1 VSS
DQ43 M_A_DQ23 M_B_DQS5 47 155
M_B_DQS7 DQS2 VSS
DQS2 M_B_DQS[7:0] 5 64
DQS3 VSS
156
DQ44 M_A_DQ16 M_B_DQS0 137 161
M_B_DQS2 DQS4 VSS
154 162
M_B_DQS4 DQS5 VSS
DQ45 M_A_DQ17 171
DQS6 VSS
167
M_B_DQS6 188 168
DQS7 VSS
DQ46 M_A_DQ19 VSS
172
116 173
14 M_B_DIM0_ODT0 ODT0 VSS
DQ47 M_A_DQ18 14 M_B_DIM0_ODT1
120
ODT1 VSS
178
179
VSS
M_VREF_CA_DIMMB 126 184
VREF_CA VSS
M_VREF_DQ_DIMMB 1 185
VREF_DQ VSS
DQ48 M_A_DQ36 VSS
189
30 190
4 DDR3_DRAMRST#_2 RESET# VSS
DQ49 M_A_DQ33 VSS
195
C1320
SCD1U16V2KX-3GP

196
1

VSS
DQ50 M_A_DQ35 0D675V_S0 203
VTT1 VSS
205
DY
DQ51 M_A_DQ39
204
VTT2 H = 4mm VSS
206
2

DQS4
DQ52 M_A_DQ37 DDR3-204P-106-GP-U
62.10017.X31
DQ53 M_A_DQ32 2nd = 62.10024.M51
DQ54 M_A_DQ34
DQ55 M_A_DQ38

DQ56 M_A_DQ52
A A
DQ57 M_A_DQ49
DQ58 M_A_DQ48
DQ59 M_A_DQ53 <Core Design>
DQS6
DQ60 M_A_DQ51
DQ61 M_A_DQ55 Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
DQ62 M_A_DQ54 Taipei Hsien 221, Taiwan, R.O.C.

DQ63 M_A_DQ50 Title

DDR3L-SODIMM1
Size Document Number Rev
A2 A00
Round Rock MLK 13.3"
Date: Monday, August 17, 2015 Sheet 13 of 110

5 4 3 2 1
 5 4 3 2 1

VREF circuit -M1 (Voltage Driver Network) & M3 (Driven by Processor) Implementation
SSID = MEMORY

SA_DIMM_VREFDQ
Driven by process (PIN#AR51)

D
0D675V_VTTREF D
DDR_W R_VREF01 5
1D35V_S3
1

0D675V_VTTREF 1D35V_S3
R1401 5 +V_SM_VREF_CNT

1
0R0402-PAD-2-GP

1
R1402 R1404
1K8R2F-GP R1403 R1405
DY 0R2J-2-GP
SODIMM1
2

1K8R2F-GP
DY 0R2J-2-GP

2
R1410

2
DDR_W R_VREF01_R R1406 1 2 2R2F-GP DDR_W R_VREF01_B4 1 2 M_VREF_DQ_DIMMA M_VREF_CA_DIMMA 1 2 +V_SM_VREF1 R1409 1 2 2R2F-GP +V_SM_VREF1_R 1 2
R1407 R1408 0R0402-PAD-2-GP
0R0402-PAD-2-GP 0R0402-PAD-2-GP

1
C1402
1

C1401 R1411 R1412 SCD022U16V2KX-3GP

SCD022U16V2KX-3GP 1K8R2F-GP 1K8R2F-GP

2
2

+V_VREF_PATH3

1
+V_VREF_PATH1
1

R1414
R1413 24D9R2F-L-GP
24D9R2F-L-GP

2
2

1
C C
R1415 R1416
0R0402-PAD-2-GP 0R2J-2-GP
DY

2
SB_DIMM_VREFDQ
Driven by process (PIN#AP51) 0D675V_VTTREF
1D35V_S3
DDR_W R_VREF02 5 1D35V_S3 1
1

R1418
1

1
R1417 DY 0R2J-2-GP
0R0402-PAD-2-GP R1419 R1420
1K8R2F-GP SODIMM2 DY 1K8R2F-GP
2
2

2
DDR_W R_VREF02_R R1421 1 2 2R2F-GP DDR_W R_VREF02_D1 1 2 M_VREF_DQ_DIMMB M_VREF_CA_DIMMB 1 2 +V_SM_VREF2 R1424 1 DY 2 2R2F-GP +V_SM_VREF2_R
R1422 R1423
0R0402-PAD-2-GP 0R0402-PAD-2-GP
1

1
C1403 C1404
B SCD022U16V2KX-3GP R1425 R1426 B
1K8R2F-GP 1K8R2F-GP
DY SCD022U16V2JX-GP
DY
2

2
+V_VREF_PATH2 +V_VREF_PATH4
2

2
1

1
R1427 R1428
24D9R2F-L-GP DY 24D9R2F-L-GP
2

2
1D35V_S3

1D35V_S3
C1405
SCD1U16V2KX-3GP

D
1

Q1401
5V_S5 2N7002K-2-GP
2

84.2N702.J31
1

2ND = 84.2N702.031
R1429 3rd = 84.2N702.W31
U1401 220KR2J-L2-GP
G

1 5 R1431 1 2 66D5R2F-GP M_A_DIM0_ODT0 12

NC#1 VCC
2

R1430 1 2 0R0402-PAD-2-GP DDR_PG_CTRL_R 2 R1432 1 2 66D5R2F-GP M_A_DIM0_ODT1 12

4 DDR_PG_CTRL R1433 1 A
A DY 2 0R2J-2-GP <Core Design> A
3 4 DDR_VTT_PG_CTRL M_A_B_DIMM_ODT R1434 1 2 66D5R2F-GP M_B_DIM0_ODT0 13
GND Y
1

R1435 1 2 66D5R2F-GP
74AUC1G07DCKR-GP R1436
M_B_DIM0_ODT1 13
Wistron Corporation
2MR2-GP 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
73.01G07.02H DY Taipei Hsien 221, Taiwan, R.O.C.
2ND = 73.01G07.AHG DDR_VTT_PG_CTRL 49
2

Title

M1 & M3 Implementation
Size Document Number Rev
A3 A00
Round Rock MLK 13.3"
Date: Monday, August 17, 2015 Sheet 14 of 110
5 4 3 2 1
 5 4 3 2 1

D D

HSW_ULT_DDR3L
CPU1I 9 OF 19

52 BIA_PW M_PCH BIA_PW M_PCH B8 B9 PCH_HDMI_CLK

EDP_BKLCTL DDPB_CTRLCLK PCH_HDMI_CLK 54
52 PANEL_BKEN_PCH PANEL_BKEN_PCH A9 EDP_BKLEN eDP SIDEBAND DDPB_CTRLDATA C9 PCH_HDMI_DATA
PCH_HDMI_DATA 54 HDMI
24,36 ENVDD_PCH ENVDD_PCH C6 D9 DP_HDMI_CLK
EDP_VDDEN DDPC_CTRLCLK DP_HDMI_CLK 55
DDPC_CTRLDATA D11 DP_HDMI_DATA
DP_HDMI_DATA 55 DP/HDMI

20 CONTACTLESS_DET# U6 PIRQA#/GPIO77
DGPU_PW ROK P4 C5 DDPB_AUX#
R1508 PIRQB#/GPIO78 DDPB_AUXN
67 FFS_PCH_INT 2 1 0R0402-PAD-2-GP FFS_PCH_INT_R N4 PIRQC#/GPIO79 DDPC_AUXN B6 LP_DDPC_AUX# 55
DISPLAY
3D3V_S0 R1507 1 2 10KR2J-3-GP MCP_GPIO80 N2 PIRQD#/GPIO80 DDPB_AUXP B5 DDPB_AUX DP/HDMI
TP1501 1 MCP_PME# AD4 PME# DDPC_AUXP A6 LP_DDPC_AUX 55
C PCIE C
MCP_GPIO55 U7
18 MCP_GPIO55 TOUCH_RST_N_GYRO_INT1 GPIO55
L1 GPIO52
L3 C8 HDMI_PCH_DET
GPIO54 DDPB_HPD PCH_DPC_HPD HDMI_PCH_DET 54
R5 GPIO51 DDPC_HPD A8 PCH_DPC_HPD 55
CODEC_IRQ L4 D6 EDP_HPD
GPIO53 EDP_HPD EDP_HPD 52

HASW ELL-6-GP-U
R1502 1 2 100KR2J-1-GP DDPB_AUX

R1503 1 DY 2 1KR2F-5-GP CODEC_IRQ

R1504 1 DY 2 100KR2J-1-GP ENVDD_PCH

Schematic check list no need pull-low

R1505 1 2 100KR2J-1-GP PCH_DPC_HPD

R1506 1 DY 2 20KR2J-L2-GP HDMI_PCH_DET

3D3V_S0
RN1501
PCH_HDMI_DATA 1 4
PCH_HDMI_CLK 2 3
B B

SRN2K2J-1-GP
3D3V_S0 RN1502
DP_HDMI_CLK 1 4
RN1503 DP_HDMI_DATA 2 3
1 8 3.3V_TS_EN 3.3V_TS_EN 20,98
2 7 SRN2K2J-1-GP
3 6 3.3V_TP_EN 3.3V_TP_EN 20,62
4 5 MCP_GPIO84 20
SRN10KJ-6-GP

RN1504
1 4 DGPU_PW ROK
2 3 MINI2CLK_REQ# MINI2CLK_REQ# 18,59
SRN10KJ-5-GP

R1513 1 2 10KR2J-3-GP TOUCH_RST_N_GYRO_INT1

R1514 1 2 100KR2J-1-GP DDPB_AUX#

R1515 1 DY 2 10KR2J-3-GP MCP_PME#

Schematic check list required pull-up 10k
R1517 1 2 10KR2J-3-GP FFS_PCH_INT_R

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (/DDI/PCI)
Size Document Number Rev
A3 A00
Round Rock MLK 13.3"
Date: Monday, August 17, 2015 Sheet 15 of 110
5 4 3 2 1
 5 4 3 2 1

SSID = PCH USB2.0 Table

Pair Device
0 USB port 1 (USB Charger)
Broadwell ULT: 1 USB port 2 (Win Debug)
USB Ext. port 1 2 WWAN
External debug port use on Broadwell ULT 3 WLAN (BT)
D 4 N/A D

5 CAMERA
HSW_ULT_DDR3L 11 OF 19
CPU1K 6 Touch Panel
7 N/A
F10 PERN5_L0 USB2N0 AN8 USB_PN0 35
E10 PERP5_L0 USB2P0 AM8 USB_PP0 35

C23 AR7
C22
PETN5_L0
PETP5_L0
USB2N1
USB2P1 AT7
USB_PN1
USB_PP1
34
34 EV follow ARD USB3.0 Table
F8 PERN5_L1 USB2N2 AR8 USB_W W AN_N 59
E8 PERP5_L1 USB2P2 AP8 USB_W W AN_P 59 Pair Device
B23 PETN5_L1 USB2N3 AR10 USB_W LAN_N 58 1 USB port 1
A23 PETP5_L1 USB2P3 AT10 USB_W LAN_P 58
2 USB port 2
H10 PERN5_L2 USB2N4 AM15
G10 PERP5_L2 USB2P4 AL15 3 WWAN
B21 PETN5_L2 USB2N5 AM13 USB_CAMERA_N 52 4 N/A
C21 PETP5_L2 USB2P5 AN13 USB_CAMERA_P 52

E6 PERN5_L3 USB2N6 AP11 TOUCHPANEL_N 98

F6 PERP5_L3 USB2P6 AN11 TOUCHPANEL_P 98

B22 PETN5_L3 USB2N7 AR13

C A21 AP13 C
PETP5_L3 USB2P7

30 PCIE_RXN3 G11 PERN3

30 PCIE_RXP3 F11 PERP3 USB3RN1 G20 USB3_RX0_N 34
LAN C1603 1 2 SCD1U16V2KX-3GP PCIE_TXN3_C C29
USB3RP1 H20 USB3_RX0_P 34
30 PCIE_TXN3 PETN3 PCIE USB
30 PCIE_TXP3 C1604 1 2 SCD1U16V2KX-3GP PCIE_TXP3_C B30 C33 USB3_TX0_N 34
PETP3 USB3TN1
USB3TP1 B34 USB3_TX0_P 34
58 PCIE_RXN4 F13 PERN4
58 PCIE_RXP4 G13 PERP4 USB3RN2 E18 USB3_RX1_N 34
WLAN B29
USB3RP2 F18 USB3_RX1_P 34
58 PCIE_TXN4 PETN4
58 PCIE_TXP4 A29 PETP4 USB3TN2 B33 USB3_TX1_N 34
EV follow ARD USB3TP2 A33 USB3_TX1_P 34
59 USB3_RXN3 G17 PERN1/USB3RN3
59 USB3_RXP3 F17 PERP1/USB3RP3
WWAN 59 USB3_TXN3 C30 PETN1/USB3TN3
59 USB3_TXP3 C31 AJ10 USB_COMP R1602 1 2 22D6R2F-L1-GP
PETP1/USB3TP3 USBRBIAS#
USBRBIAS AJ11
32 PCIE_RXN2 F15 PERN2/USB3RN4 RSVD#AN10 AN10
32 PCIE_RXP2 G15 PERP2/USB3RP4 RSVD#AM10 AM10
Card Reader C1606 1 2 SCD1U16V2KX-3GP PCIE_TXN2_C B31 3D3V_S5_PCH
32 PCIE_TXN2 PETN2/USB3TN4
32 PCIE_TXP2 C1605 1 2 SCD1U16V2KX-3GP PCIE_TXP2_C A31 RN2004
PETP2/USB3TP4 USB_OC#0_1 USB_OC#0_1
OC0/GPIO40# AL3 USB_OC#0_1 35 8 1
AT1 USB_OC#2_3 USB_OC#4_5 7 2
+V1.05S_AUSB3PLL OC1/GPIO41# USB_OC#4_5 USB_OC#2_3 35 USB_OC#6_7
OC2/GPIO42# AH2 6 3
E15 AV3 USB_OC#6_7 SIO_EXT_SMI# 5 4
B RSVD#E15 OC3/GPIO43# 20,24 SIO_EXT_SMI# B
E13 RSVD#E13
R1601 1 2 3K01R2F-3-GP PCIE_RCOMP A27 SRN10KJ-6-GP
R1607 1 PCIE_RCOMP
2 0R0402-PAD-2-GP PCIE_IREF B27 PCIE_IREF RN2005
USB_OC#2_3 4 1
20,62 KB_DET# KB_DET# 3 2

HASW ELL-6-GP-U SRN10KJ-5-GP

PCIE_RXN4
PCIE_RXP4
2

2
EC1601
SC22P50V2JN-4GP

EC1602
SC22P50V2JN-4GP

DY DY
1

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (PCIE/USB)
Size Document Number Rev
A3 A00
Round Rock MLK 13.3"
Date: Monday, August 17, 2015 Sheet 16 of 110
5 4 3 2 1
 5 4 3 2 1

SSID = PCH RTC_AUX_S5

PCH_DPW ROK R1702 1 DY 2 0R2J-2-GP PM_RSMRST#

1
Reserve for NON DS3
CPU1H HSW_ULT_DDR3L 8 OF 19 R1707

SYSTEM POWER MANAGEMENT

DY 10KR2J-3-GP
ME_SUS_PW R_ACK_R R1703 1 2 0R2J-2-GP
DY 0R0402-PAD-2-GP

2
24 SUSACK# R1704 1 2 SUSACK#_R AK2 AW7 DSW ODVREN
SYS_RESET# SUSACK# DSWVRMEN PCH_DPW ROK
96 SYS_RESET# AC3 SYS_RESET# DPWROK AV5 PCH_DPW ROK 24
24,96 SYS_PW ROK R1705 1 2 0R0402-PAD-2-GP SYS_PW ROK_R AG2 AJ5 PCH_PCIE_W AKE# 24
R1706 1 SYS_PWROK WAKE#
24,36 RESET_OUT# 2 0R0402-PAD-2-GP PCH_PW ROK AY7 PCH_PWROK
36 APW ROK R1708 1 2 0R0402-PAD-2-GP APW ROK_R AB5
PCH_PLTRST# APWROK CLKRUN#
D AG7 PLTRST# CLKRUN#/GPIO32 V5 CLKRUN# 24 D
AG4 SUS_STAT#/LPCPD# EV Remove LPC TPM
PM_RSMRST# SUS_STAT#/GPIO61 SUSCLK R1709 1
EV 18 PM_RSMRST# SUSCLK/GPIO62 AE6
SIO_SLP_S5#
DY 2 0R2J-2-GP SUSCLK_NGFF 58,59
SLP_S5#/GPIO63 AP5 SIO_SLP_S5# 24
24 ME_SUS_PW R_ACK R1710 1 2 0R0402-PAD-2-GP ME_SUS_PW R_ACK_R AW6 RSMRST#
96 PM_PW RBTN#_R AV4 SUSWARN#/SUSPWRDNACK#/GPIO30
24 SIO_PW RBTN# R1711 1 2 0R0402-PAD-2-GP PM_PW RBTN#_R AL7 AJ6 SIO_SLP_S4# 24,36,49
AC_PRESENT PWRBTN# SLP_S4#
24 AC_PRESENT AJ8 ACPRESENT/GPIO31 SLP_S3# AT4 SIO_SLP_S3# 24,36,49
PCH_BATLOW # AN4 AL5 R1712 1 DY 2 0R2J-2-GP
SIO_SLP_S0# BATLOW#/GPIO72 SLP_A# SLP_A# R1713 1
88 SIO_SLP_S0# AF3 SLP_S0# SLP_SUS# AP4 2 SIO_SLP_A# 24,36,48
99 SIO_SLP_W LAN# AM5 AJ7 SIO_SLP_SUS# 0R0402-PAD-2-GP SIO_SLP_SUS# 24
SLP_WLAN#/GPIO29 SLP_LAN# SIO_SLP_LAN# 1 TP1701
EV Remove Intel LAN
NOTE:
PWRBTN# Integrated Pull-Up.

HASW ELL-6-GP-U
DSWODVREN - On Die DSW VR Enable

HIGH Enabled (DEFAULT)

LOW Disabled
3D3V_S0

R1716 1 2 8K2R2J-3-GP CLKRUN# RTC_AUX_S5

3D3V_S0
R1719 1 DY 2 10KR2J-3-GP SYS_RESET#
C
3D3V_S5_PCH R1721 1 2 330KR2J-L1-GP C
EV follow Huston, pull high on XDP side

1
C1701
SCD1U16V2KX-3GP DSW ODVREN R1723 2 330KR2J-L1-GP
U1701
1
DY

2
R1724 1 1 5
2 10KR2J-3-GP ME_SUS_PW R_ACK
PCH_PLTRST# A VCC
2 B
3 4 PLTRST# R1725 1 2 0R0402-PAD-2-GP PCH_PLTRST#_EC 24,65,88
R1726 1 2 10KR2J-3-GP SUSACK# GND Y R1717 1 2 0R0402-PAD-2-GP PLTRST_MMI# 32,58,59
R1718 1 2 0R0402-PAD-2-GP PLTRST_XDP# 96
R1729 1 DY 2 10KR2J-3-GP SUS_STAT#/LPCPD# U74LVC1G08G-AL5-R-GP-U

1
R1720 1 2 0R0402-PAD-2-GP PLTRST_LAN# 30
73.01G08.EHG R1727
2ND = 73.7SZ08.DAH 100KR2J-1-GP APS1
+V3.3A_DSW _P
19

2
3D3V_S5_PCH 1
R1728 1 2 10KR2J-3-GP PCH_BATLOW #
SIO_SLP_S3# 2
RN1701 +V3.3A_DSW _P 3
SIO_SLP_S5# 4
1 4 PCH_PCIE_W AKE#
SIO_SLP_S4# 5
2 3 AC_PRESENT
SIO_SLP_A# 6
SRN10KJ-5-GP +V3.3A_DSW _P 7
8
19 RTC_RST# 9 APS
R1722 1 10
DY 2 10KR2J-3-GP SIO_SLP_LAN#
24,61 MB_PW R_BTN# 11
B B
12
SYS_RESET# 13
14
R1733 1 DY 2 10KR2J-3-GP AC_PRESENT SIO_SLP_S0# 15
16
R1734 1 DY 2 100KR2J-1-GP PCH_DPW ROK Schematic check list required pull-low 100k 17
18
R1735 1 DY 2 10KR2J-3-GP SYS_PW ROK
20
R1736 1 DY 2 10KR2J-3-GP PCH_PW ROK
ETY-CON18-2-GP
R1730 1 2 10KR2J-3-GP PM_RSMRST# 20.K0493.018

SYS_PW ROK_R
PCH_PW ROK
APW ROK_R
PCH_DPW ROK
SYS_RESET#
PCH_PLTRST#
PM_RSMRST#
1

1
EC1701
SC1KP50V2KX-1GP

EC1702
SC1KP50V2KX-1GP

EC1703
SC1KP50V2KX-1GP

EC1704
SC1KP50V2KX-1GP

EC1705
SC1KP50V2KX-1GP

EC1706
SC1KP50V2KX-1GP

EC1707
SC1KP50V2KX-1GP

A <Core Design> A
DY
2

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (PM)
Size Document Number Rev
A3 A00
Round Rock MLK 13.3"
Date: Monday, August 17, 2015 Sheet 17 of 110
5 4 3 2 1
 5 4 3 2 1

SSID = PCH PCIECLKRQ1# and PCIECLKRQ2#

R1802
Support S0 power only XTAL24_IN 1 2 XTAL24_IN_R C1802 1 2 SC15P50V2JN-2-GP
0R0402-PAD-2-GP
HSW_ULT_DDR3L
CPU1F 6 OF 19
X1801

1
1 2
R1803 82.30004.641
1M1R2J-GP 2nd = 82.30004.841
PCIECLKRQn# is route to PCIE Port (n+1) C43 A25 XTAL24_IN 3rd = 82.30004.831
CLKOUT_PCIE_N0 XTAL24_IN XTAL24_OUT
C42 B25 4 3

2
EV PCIECLKRQ0# CLKOUT_PCIE_P0 XTAL24_OUT
U2 PCIECLKRQ0#/GPIO18
D K21 MCP_K21 1 +V1.05S_AXCK_LCPLL XTAL-24MHZ-56-GP D
RSVD#K21 TP1802
32 CLK_PCIE_CARD# RN1802 2 3 0R4P2R-PAD CLK_PCH_SRC1_N B41 CLKOUT_PCIE_N1 RSVD#M21 M21 MCP_M22 1 TP1803 +/- 20 ppm
32 CLK_PCIE_CARD 1 4 CLK_PCH_SRC1_P A41 CLKOUT_PCIE_P1
PCIE Port 2 DIFFCLK_BIASREF C26 XCLK_BIASREF R1804 1 2 3K01R2F-3-GP Loading 12pF
20,32 MMICLK_REQ# MMICLK_REQ# Y5 PCIECLKRQ1#/GPIO19 MCP_TESTLOW 1 XTAL24_OUT
TESTLOW_C35 C35 1 2

RN RN
RN1801 2 3 0R4P2R-PAD CLK_PCH_SRC2_N C41 CLOCK C34 MCP_TESTLOW 2 C1803
30 CLK_PCIE_LAN# CLKOUT_PCIE_N2 TESTLOW_C34
30 CLK_PCIE_LAN 1 4 CLK_PCH_SRC2_P B42 AK8 MCP_TESTLOW 3 SC15P50V2JN-2-GP
CLKOUT_PCIE_P2 SIGNALS TESTLOW_AK8
20,30 LANCLK_REQ# LANCLK_REQ# AD1 PCIECLKRQ2#/GPIO20
PCIE Port 3 TESTLOW_AL8 AL8 MCP_TESTLOW 4

RN
58 CLK_PCIE_N3_W LAN# RN1809 1 4 0R4P2R-PAD CLK_PCH_SRC3_N B38 AN15 CLKOUT_LPC_0 R1813 1 2 22R2J-2-GP CLK_PCI_MEC 24
CLK_PCH_SRC3_P CLKOUT_PCIE_N3 CLKOUT_LPC_0 CLKOUT_LPC_1 R1806 1 3D3V_S5_PCH
58 CLK_PCIE_P3_W LAN 2 3 C37 CLKOUT_PCIE_P3 CLKOUT_LPC_1 AP15 2 22R2J-2-GP CLK_PCI_DEBUG 65
58 MINI1CLK_REQ# MINI1CLK_REQ# N1 PCIECLKRQ3#/GPIO21
PCIE Port 4
CLKOUT_ITPXDP# B35 EV change to 2.2k

1
A39 A35 C1805 C1804
CLKOUT_PCIE_N4 CLKOUT_ITPXDP_P

SC10P50V2JN-4GP

SC10P50V2JN-4GP
B39 DY DY LOM_SMBCLK R1807 1 2 2K2R2J-2-GP
CLKOUT_PCIE_P4
MINI4CLK_REQ# U5 PCIE Port 5 LOM_SMBDAT R1808 1 2 2K2R2J-2-GP

2
PCIECLKRQ4#/GPIO22

59 CLK_PCIE_N5_W W AN# RN1803 2 3 0R4P2R-PAD CLK_PCH_SRC5_N B37

CLK_PCH_SRC5_P CLKOUT_PCIE_N5 SMB_CLK RN1804 2
59 CLK_PCIE_P5_W W AN 1 4 A37 CLKOUT_PCIE_P5 3 SRN2K2J-1-GP
15,59 MINI2CLK_REQ# MINI2CLK_REQ# T2 PCIECLKRQ5#/GPIO23
PCIE Port 6 SMB_DATA 1 4
RN

SML1_SMBCLK RN1805 1 4 SRN2K2J-1-GP

HASW ELL-6-GP-U SML1_SMBDATA 2 3
HSW_ULT_DDR3L
CPU1G 7 OF 19

R1801 1 2 0R0402-PAD-2-GP LPC_LAD0_MCP AU14 AN2 PCH_SMB_ALERT#

24,65 LPC_LAD0 LAD0 SMBALERT#/GPIO11
R1812 1 2 0R0402-PAD-2-GP LPC_LAD1_MCP AW12 AP2 SMB_CLK MCP_GPIO73 R1817 1 2 10KR2J-3-GP
24,65 LPC_LAD1 LAD1 SMBCLK
R1809 1 2 0R0402-PAD-2-GP LPC_LAD2_MCP AY12 LPC AH1 SMB_DATA
24,65 LPC_LAD2 LAD2 SMBUS SMBDATA
C R1810 1 2 0R0402-PAD-2-GP LPC_LAD3_MCP AW11 AL2 MCP_GPIO60 PCH_SMB_ALERT# R1816 1 2 10KR2J-3-GP C
24,65 LPC_LAD3 LAD3 SML0ALERT#/GPIO60
24,65 LPC_LFRAME# R1811 1 2 0R0402-PAD-2-GP LPC_LFRAME#_MCP AV12 AN1 LOM_SMBCLK Remove for Intel LAN
LFRAME# SML0CLK LOM_SMBDAT
AK1 EV MCP_GPIO60 R1818 1
SML0DATA 2 10KR2J-3-GP
SML1ALERT#/PCHHOT#/GPIO73 AU4 MCP_GPIO73
SML1_SMBCLK
DY
SML1CLK/GPIO75 AU3 SML1_SMBCLK 24
AH3 SML1_SMBDATA
SML1DATA/GPIO74 SML1_SMBDATA 24
25,88 PCH_SPI_CLK PCH_SPI_CLK AA3 RN1808
PCH_SPI_CS0# SPI_CLK MCP_TESTLOW 1
25 PCH_SPI_CS0# Y7 SPI_CS0# CL_CLK AF2 CL_CLK 58 2 3 SRN10KJ-5-GP
1 PCH_SPI_CS1# Y4 AD2 MCP_TESTLOW 2 1 4
TP1806 SPI_CS1# CL_DATA CL_DATA 58
88 PCH_SPI_CS2# AC2 SPI_CS2#
SPI C-LINK
CL_RST# AF4 CL_RST# 58
25,88 PCH_SPI_SI PCH_SPI_SI AA2 RN1810
PCH_SPI_SO SPI_MOSI MCP_TESTLOW 3
25,88 PCH_SPI_SO AA4 SPI_MISO 1 4 SRN10KJ-5-GP
25 SPI0_W P# SPI0_W P# Y6 MCP_TESTLOW 4 2 3
SPI_IO2
25 SPI_HOLD_0# AF1 SPI_IO3

3D3V_S0
HASW ELL-6-GP-U
RN1807
MCP_GPIO55 8 1
15 MCP_GPIO55 PCH_GPIO83
20 PCH_GPIO83 7 2
MINI1CLK_REQ# 6 3
5 4

SRN10KJ-6-GP

MINI4CLK_REQ# 10KR2J-3-GP 2 1 R1819

B 5V_S5 PCIECLKRQ0# 10KR2J-3-GP B
2 1 R1822
1

R1814 3D3V_S0
33R2J-2-GP RN1806
U1801 1 4
2 3
2

RESET#/RESET 2
U1801_VDD 3 SRN2K2J-1-GP
VDD
GND 1
1

3D3V_S5
C1806
SCD1U16V2KX-3GP

RT9818A-44GU3-GP 3D3V_S5 Q1801

2

74.09818.NBB SMB_DATA 6 1 PCH_SMBDATA 12,13,67,96

R1820
2ND = 74.76144.0BB 100KR2J-1-GP 5 2
84.2N702.A3F
EV 2nd = 84.DMN66.03F 4 3
2

R1823 U1802 2N7002KDW -GP

1 2 RSMRST# 1 5
24,45 ALW _PW RGD_3V_5V DY 0R2J-2-GP A VCC EV PCH_SMBCLK 12,13,67,96

24 PCH_RSMRST# 2 SMB_CLK
B
3 GND Y 4 PM_RSMRST# 17

A U74LVC1G08G-AL5-R-GP-U <Core Design> A

73.01G08.EHG
2ND = 73.7SZ08.DAH
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
1 2 Taipei Hsien 221, Taiwan, R.O.C.
R1821 DY 0R2J-2-GP
Title

CPU (CLOCK/SMBUS/CL/LPC/SPI)
Size Document Number Rev
A3 A00
Round Rock MLK 13.3"
Date: Monday, August 17, 2015 Sheet 18 of 110
5 4 3 2 1
 5 4 3 2 1

SSID = PCH RTC_AUX_S5

1
2
INTVRMEN- Integrated SUS
RN1901
SRN20KJ-GP-U
1.05V VRM Enable
High - Enable internal VRs
Low - Enable external VRs

4
3
CPU1E HSW_ULT_DDR3L 5 OF 19

2
D
RTC_AUX_S5 D

1
G1902 C1902
SC1U10V2KX-1GP RTC_X1 AW5
GAP-OPEN RTC_X2 RTCX1
AY5

2
R1901 1 RTCX2
2 1M1R2J-GP SM_INTRUDER# AU6 J5 SATA_RXN0 56

1
R1903 1 INTRUDER# SATA_RN0/PERN6_L3
2 330KR2F-L-GP PCH_INTVRMEN AV7 H5
SRTC_RST#
RTC_RST#
AV6
INTVRMEN
SRTCRST#
RTC
SATA_RP0/PERP6_L3
SATA_TN0/PETN6_L3 B15
SATA_RXP0
SATA_TXN0
56
56
HDD
AU7 RTCRST# SATA_TP0/PETP6_L3 A15 SATA_TXP0 56

1
J8
C1903
SC1U10V2KX-1GP
17 RTC_RST# SATA_RN1/PERN6_L2
1

G1901 H8
SATA_RP1/PERP6_L2
GAP-OPEN
DY ED1901 SATA_TN1/PETN6_L2 A17
AZ5725-01FDR7G-GP B17
2

SATA_TP1/PETP6_L2
EV EMC
1

HDA_BITCLK AW8 J6

2
HDA_SYNC HDA_BCLK/I2S0_SCLK SATA_RN2/PERN6_L1
AV11 HDA_SYNC/I2S0_SFRM SATA_RP2/PERP6_L1 H6
HDA_RST# AU8 B14
HDA_RST#/I2S_MCLK# AUDIO SATA SATA_TN2/PETN6_L1
27 HDA_SDIN0 AY10 HDA_SDI0/I2S0_RXD SATA_TP2/PETP6_L1 C15
AU12 HDA_SDI1/I2S1_RXD
98 ME_FW P R1904 1 2 1KR2J-1-GP HDA_SDOUT AU11 F5 SATA_RN3/PERN6_L0 59
HDA_SDO/I2S0_TXD SATA_RN3/PERN6_L0
AW10
AV10
HDA_DOCK_EN#/I2S1_TXD# SATA_RP3/PERP6_L0 E5
C17
SATA_RP3/PERP6_L0 59
SATA_TN3/PETN6_L0 59
WWAN
RTC_X1 HDA_DOCK_RST#/I2S1_SFRM# SATA_TN3/PETN6_L0
AY8 I2S1_SCLK SATA_TP3/PETP6_L0 D17 SATA_TP3/PETP6_L0 59
R1905 1 2 10MR2J-L-GP RTC_X2
V1 MPCIE_RST#
SATA0GP/GPIO34
1

U1 HDD_DET# +V1.05S_ASATA3PLL
R1906 SATA1GP/GPIO35 HDD_DET# 56
V6 MCP_GPIO36
0R0402-PAD-2-GP SATA2GP/GPIO36
X1901 SATA3GP/GPIO37 AC1 NGFF_PCIE#_SATA 24
C
4,96 XDP_TRST# R1907 1 DY 2 0R2J-2-GP XDP_TRST#_R AU62 C
R1908 1 PCH_TRST#
96 PCH_JTAG_TCK 2 0R2J-2-GP PCH_JTAG_TCK_BUF AE62 A12 SATA_IREF R1909 1 2 0R0402-PAD-2-GP
2

RTC_X1_R DY PCH_JTAG_TDI PCH_TCK SATA_IREF MCP_L11

1 4 AD61 PCH_TDI RSVD#L11 L11 1 TP1901
PCH_JTAG_TDO AE61 K10 MCP_K10 1
PCH_TDO RSVD#K10 TP1902
SC2P50V2CN-GP
C1901

C1904
SC2P50V2CN-GP

PCH_JTAG_TMS AD62 JTAG C12 SATA_RCOMP R1910 1 2 3K01R2F-3-GP

PCH_TMS SATA_RCOMP
1

AL11 RSVD#AL11 SATALED# U3 SATA_LED# 61

2 3 AC4 RSVD#AC4
96 PCH_JTAGX PCH_JTAGX AE63
2

JTAGX
AV2 RSVD#AV2
XTAL-32D768KHZ-6-GP
+/- 20 ppm
CL=7 pF

82.30001.B21
2nd = 82.30001.661 HASW ELL-6-GP-U
3rd = 82.30001.B41 X02
R1911 1 2 33R2J-2-GP HDA_SYNC
27 HDA_CODEC_SYNC R1912 1 33R2J-2-GP HDA_SDOUT
27 HDA_CODEC_SDOUT 2
R1913 1 2 33R2J-2-GP HDA_RST#
27 HDA_CODEC_RST# R1914 1 33R2J-2-GP HDA_BITCLK
27 HDA_CODEC_BITCLK 2
1

DY C1905
SC27P50V2JN-2-GP
2

B B

3D3V_S0

HDD_DET# R1931 1 2 10KR2J-3-GP

MPCIE_RST# R1925 1 2 10KR2J-3-GP

1D05V_M

PCH_JTAGX R1919 1PCH XDP 2 51R2J-2-GP MCP_GPIO36 R1920 1 2 10KR2J-3-GP

PCH_JTAG_TMS R1921 1PCH XDP 2 51R2J-2-GP

PCH_JTAG_TDI R1922 1PCH XDP 2 51R2J-2-GP
PCH_JTAG_TDO R1923 1PCH XDP 2 51R2J-2-GP
PCH_JTAG_TCK_BUF R1924 1PCH XDP 2 51R2J-2-GP

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
PCH_JTAG_TDO R1928 1PCH XDP 2 0R2J-2-GP Taipei Hsien 221, Taiwan, R.O.C.
CPU_XDP_TDO_PCH 96
PCH_JTAG_TDI R1929 1PCH XDP 2 0R2J-2-GP Title
CPU_XDP_TDI_PCH 96
PCH_JTAG_TMS R1930 1PCH XDP 2 0R2J-2-GP CPU_XDP_TMS_PCH 96
CPU (RTC/SATA/HDA/JTAG)
Size Document Number Rev
A3 A00
Round Rock MLK 13.3"
Date: Monday, August 17, 2015 Sheet 19 of 110
5 4 3 2 1
 5 4 3 2 1

SSID = PCH 3D3V_S5_PCH

+V3.3A_DSW _P

1
RN2001
R2004
2 3 PM_LANPHY_ENABLE
LAN_W AKE#_C 8K2R2F-1-GP
1 4

SRN10KJ-5-GP

2
3D3V_S5_PCH MCP_GPIO15

R2005 1 2 10KR2J-3-GP SIO_EXT_W AKE#

D D

R2008 1 DY 2 10KR2J-3-GP NFC_IRQ

R2015 1 2 10KR2J-3-GP MEDIACARD_PW REN +V1.05S_VCCST

RN1601

1
8 1 SNSR_HUB_PW REN
HSW_ULT_DDR3L
7 2 MCP_GPIO9 CPU1J 10 OF 19 R2012
6 3 SLATE_MODE 1KR2J-1-GP
5 4 SNSR_HUB_RST#
EDS no ask GPIO9 required external PH

2
SRN10KJ-6-GP
PCH_AUDIO_PW R P1 D60 H_THERMTRIP#_R R2014 1 2 H_THERMTRIP# 24
EV for Card reader SIO_EXT_W AKE# BMBUSY#/GPIO76 THRMTRIP# SIO_RCIN# 0R0402-PAD-2-GP
24 SIO_EXT_W AKE# AU2 GPIO8 RCIN#/GPIO82 V4 SIO_RCIN# 24
PM_LANPHY_ENABLE AM7 T4 IRQ_SERIRQ IRQ_SERIRQ 24
R2010 1 LAN_PHY_PWR_CTRL/GPIO12 CPU/ SERIRQ
2 10KR2J-3-GP MEDIACARD_RST# MCP_GPIO15 AD6 GPIO15 PCH_OPI_RCOMP AW15 PCH_OPIRCOMP R2016 1 2 49D9R2F-GP
LAN_RST# Y1 MISC AF20
R2018 1 2 10KR2J-3-GP MCP_GPIO47 X01 MCP_GPIO17 T3
GPIO16 RSVD#AF20
AB21
R2021 1 GPIO17 RSVD#AB21
[25] RTC_DET# 2 0R0402-PAD-2-GP RTC_DET#_C AD5 GPIO24
24,30,99 LAN_W AKE# R2011 1 2 0R0402-PAD-2-GP LAN_W AKE#_C AN5
R2030 1 2 100KR2J-1-GP MCP_GPIO59 GPIO27
AD7 GPIO28
NFC_IRQ AN3
R2022 1 2 10KR2J-3-GP RTC_DET# GPIO26
GSPI0_CS#/GPIO83 R6 PCH_GPIO83 18
MEDIACARD_RST# AG6 L6 MCP_GPIO84 MCP_GPIO84 15
X01 Remove for Card reader MEDIACARD_PW REN AP1
GPIO56 GSPI0_CLK/GPIO84
N6 HDD_PW R_EN
3D3V_S0 GPIO57 GSPI0_MISO/GPIO85 HDD_PW R_EN 56
SLATE_MODE AL4 L8 BBS_BIT
MCP_GPIO59 GPIO58 GSPI0_MOSI/GPIO86 DBC_PANEL_EN EV reserved for modern standby
AT5 GPIO59 GSPI1_CS#/GPIO87 R7 DBC_PANEL_EN 52
C SNSR_HUB_RST# AK4 GPIO L5 3.3V_TP_EN C
GPIO44 GSPI1_CLK/GPIO88 3.3V_TP_EN 15,62
Reseve for SD read only mode check with SW for card reader wake pin MCP_GPIO47 AB6 N7 3.3V_TS_EN
GPIO47 GSPI1_MISO/GPIO89 3.3V_TS_EN 15,98
DIMM_DET U4 K2 3.3V_HDD_EN 3.3V_HDD_EN 56
R2058 1 DY 2 10KR2J-3-GP HOST_SD_W P# GPIO48 GSPI_MOSI/GPIO90
32 MEDIACARD_IRQ# MEDIACARD_IRQ# Y3 J1 MCP_GPIO91
GPIO49 UART0_RXD/GPIO91 MCP_GPIO92
R2057 1 98 TOUCH_PANEL_INTR# P3 K3
2 10KR2J-3-GP PCH_AUDIO_PW R MPHYP_PW R_EN GPIO50 UART0_TXD/GPIO92
36 MPHYP_PW R_EN Y2 HSIOPC/GPIO71 UART0_RTS#/GPIO93 J2 Reseve for SD read only mode
KB_DET# AT3 SERIAL IO G1
R2019 1 2 100KR2J-1-GP SIO_EXT_SCI# 16,62 KB_DET# GPIO13 UART0_CTS#/GPIO94
1 MCP_GPIO14 AH4 K4 HOST_SD_W P# 32
TP2008 GPIO14 UART1_RXD/GPIO0
52 3.3V_CAM_EN# 3.3V_CAM_EN# AM4 G2 FFS_INT2 FFS_INT2 67
R2020 1 DY 2 1KR2F-3-GP HDA_SPKR GPIO25 UART1_TXD/GPIO1
16,24 SIO_EXT_SMI# R2013 1 2 SIO_EXT_SMI#_R AG5 J3 LCD_CBL_DET# LCD_CBL_DET# 52
0R0402-PAD-2-GP SNSR_HUB_PW REN GPIO45 UART1_RST#/GPIO2
R2024 1 AG3 J4
2 2K2R2J-2-GP I2C0_SDA GPIO46 UART1_CTS#/GPIO3 I2C0_SDA EDS ask GPIO3 need external PH onpage94
I2C0_SDA/GPIO4 F2
MCP_GPIO9 AM3 F3 I2C0_SCL
R2025 1 2 2K2R2J-2-GP I2C0_SCL GPIO9 I2C0_SCL/GPIO5
1 MCP_GPIO10 AM2 G4 DAT_I2C_TP_SIO
TP2006 GPIO10 I2C1_SDA/GPIO6
56 mSATA_DEVSLP P2 F1 CLK_I2C_TP_SIO
R2026 1 2 2K2R2J-2-GP DAT_I2C_TP_SIO DEVSLP0/GPIO33 I2C1_SCL/GPIO7
C4 E3 USH_DET#
R2017 1 SDIO_POWER_EN/GPIO70 SDIO_CLK/GPIO64
R2027 1 59 NGFF_DEVSLP1 DY 2 0R2J-2-GP MCP_GPIO38 L2 F4 CAM_MIC_CBL_DET# CAM_MIC_CBL_DET# 52
2 2K2R2J-2-GP CLK_I2C_TP_SIO SIO_EXT_SCI# DEVSLP1/GPIO38 SDIO_CMD/GPIO65 MCP_GPIO66
24 SIO_EXT_SCI# N5 DEVSLP2/GPIO39 SDIO_D0/GPIO66 D3
27 HDA_SPKR HDA_SPKR V2 E4 CPU_SEL
R2028 1 2 100KR2J-1-GP MCP_GPIO91 SPKR/GPIO81 SDIO_D1/GPIO67
C3 TPM_ID1
SDIO_D2/GPIO68 SLP_ME_CSW _DEV#
R2029 1 E2
2 100KR2J-1-GP MCP_GPIO92 SDIO_D3/GPIO69
No Reboot Strap
R2041 1 2 20KR2J-L2-GP TPM_ID1
Low = Default HASW ELL-6-GP-U
HDA_SPKR High = No Reboot
RN2009
DBC_PANEL_EN
EV
1 8
2 7 LANCLK_REQ# LANCLK_REQ# 18,30
3 6 LAN_RST# 3D3V_S0
B MPHYP_PW R_EN B
4 5

SRN10KJ-6-GP
RN2008

1
1 8 CAM_MIC_CBL_DET#
2 7 MCP_GPIO17 R1512
3 6 USH_DET# 10KR2J-3-GP
4 5 SLP_ME_CSW _DEV# BDW

2
SRN10KJ-6-GP CPU_SEL
RN2007
FFS_INT2 3D3V_S0
1 8
CPU detect pin

1
2 7 3D3V_S0 3D3V_S0
3 6 LCD_CBL_DET# R1516
4 5 HDD_PW R_EN 10KR2J-3-GP
HSW

1
1

SRN10KJ-6-GP EV
R2043

2
R2044 R2045
DY 10KR2J-3-GP DY 10KR2J-3-GP DY 1KR2J-1-GP

2
DIMM_DET
2

BBS_BIT MCP_GPIO66

1
1

R2046
RN2003 R2049 R2051
1KR2J-1-GP
1 8 SIO_RCIN# DY 1KR2J-1-GP DY 1KR2F-3-GP
2 7 MMICLK_REQ# MMICLK_REQ# 18,32
IRQ_SERIRQ
2
3 6
2

A 4 5 CONTACTLESS_DET# 15 <Core Design> A

SRN10KJ-6-GP
BOOT BIOS Strap TOP-BLOCK SWAP OVERRIDE
R2054 1 2 10KR2J-3-GP NFC_IRQ Wistron Corporation
GPIO86 BOOT BIOS Location GPIO66 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
R2055 1 2 100KR2J-1-GP 3.3V_CAM_EN# Taipei Hsien 221, Taiwan, R.O.C.
0 SPI(Default) HIGH pop R20545
Title
1 LPC LOW pop R2051(DEFAULT)
CPU (GPIO/CPU)
Size Document Number Rev
A3 A00
Round Rock MLK 13.3"
Date: Monday, August 17, 2015 Sheet 20 of 110
5 4 3 2 1
 5 4 3 2 1

SSID = PCH

D D
1D05V_M

+V1.05S_AUSB3PLL 1D05V_MODPHY
1D05V_MODPHY +V1.05A_AOSCSUS L2102 1 2 IND-2D2UH-196-GP
R2101 1 3D3V_S5_PCH DY
2 0R0805-PAD-2-GP-U
68.2R21D.10R

C2105
SC100U6D3V6MX-GP
L2101 1 2 IND-2D2UH-196-GP +V1.05S_AUSB3PLL

C2103
SC1U10V2KX-1GP

C2104
SC1U10V2KX-1GP

C2106
SC1U10V2KX-1GP
1

1
+VCCPRTCSUS R2102 1 2 0R0402-PAD-2-GP RTC_AUX_S5 2ND = 68.2R21G.10Q
68.2R21D.10R HSW_ULT_DDR3L

C2101
SC1U10V2KX-1GP

C2102
SC22U6D3V5MX-2GP
CPU1M 13 OF 19
DY DY

1
2ND = 68.2R21G.10Q C2107 R2103 1 2 0R2J-2-GP
DY

2
1D05V_S0

C2111
SCD1U16V2KX-3GP

C2108
SCD1U16V2KX-3GP

C2109
SC1U10V2KX-1GP
+V1.05DX_MODPHY_PCH K9 SC1U10V2KX-1GP
VCCHSIO

1
L10

2
VCCHSIO
M9
VCCHSIO HSIO RTC
N8 AH11

2
VCC1_05 VCCSUS3_3
P9 AG10
+V1.05S_AUSB3PLL VCC1_05 VCCRTC +VCCRTCEXT C2110 1
B18 AE7 2
+V1.05S_ASATA3PLL +V1.05S_ASATA3PLL VCCUSB3PLL DCPRTC 1D05V_M
B11
1D05V_MODPHY VCCSATA3PLL SCD1U16V2KX-3GP 3D3V_M

L2103 1 2 IND-2D2UH-196-GP +V1.05S_ASATA3PLL TP2101 1 TP_VCCAPLLOPI_VAL Y20 SPI Y8 +V1.05A_SUS_PCH R2104 2 DY 1 0R2J-2-GP
+V1.05S_APLLOPI RSVD#Y20 VCCSPI
AA21 OPI
VCCAPLL

1
68.2R21D.10R
C2113
SC1U10V2KX-1GP

C2115
SC22U6D3V5MX-2GP

C2116
SC22U6D3V5MX-2GP
W21 C2114

SC1U10V2KX-1GP
C2117
1

1
2ND = 68.2R21G.10Q VCCAPLL
AG14 SC1U10V2KX-1GP
VCCASW DY
AG13 1D05V_M

2
VCCASW 1D05V_S0
2

2
3D3V_S5_PCH +V3.3A_1.5A_HDA +V1.05A_VCCUSB3SUS J13 USB3
DCPSUS3
J11
1D05V_S0 VCC1_05
VCC1_05
H11 Broadwell(#514849): No series resistors (0 ohm).

C2118
SC1U10V2KX-1GP
R2105 1 2 +V3.3A_1.5A_HDA AH14 HDA H15 Haswell(#486713):Series resistor:5 ohm.

1
0R0402-PAD-2-GP VCCHDA VCC1_05
AE8

C2119
SC1U10V2KX-1GP

C2120
SCD1U16V2KX-3GP
1

1
R2107 1 2 0R0402-PAD-2-GP +V1.05S_APLLOPI VCC1_05
AF22 BDW/HSW C2121 SC1U10V2KX-1GP
+V1.05A_USB2SUS VRM VCC1_05
AH13 AG19 PCH_VCCDSW 1 2PCH_VCCDSW_R 1 2

2
DCPSUS2 DCPSUSBYP#AG19 1D05V_S0
C2125
SC1U10V2KX-1GP

CORE AG20 R2106 0R2J-2-GP

2
DCPSUSBYP#AG20
1

AE9
VCCASW 1D05V_M
AF9
3D3V_S0 +V3.3A_PSUS VCCASW +V1.05S_AXCK_DCB IND-2D2UH-196-GP
AC9 AG8 2 1 L2105
2

VCCSUS3_3 VCCASW +V1.05A_SUS_PCH

AA9 GPIO/LPC AD10
VCCSUS3_3 DCPSUS1#AD10 68.2R21D.10R

C2130
SC100U6D3V6MX-GP

C2131
SC1U10V2KX-1GP
+V3.3A_DSW_P AH10 AD8
VCCDSW3_3 DCPSUS1#AD8

1
2ND = 68.2R21G.10Q

C2128
SC1U10V2KX-1GP

C2129
SC22U6D3V5MX-2GP
R2108 1 2 +V3.3S_PCORE V8

1
0R0402-PAD-2-GP VCC3_3 3D3V_S0
W9

1
1D05V_M C2127 VCC3_3
J15 +1.5V_THERMAL DY

2
SC22U6D3V5MX-2GP THERMAL SENSOR VCCTS1_5
C K14 C

2
VCC3_3
K16

2
VCC3_3

C2134
SC1U10V2KX-1GP
R2109 1 DY 2 0R2J-2-GP +V1.05A_VCCUSB3SUS

1
1D05V_S0 +V1.05S_AXCK_LCPLL 3D3V_S0
C2132
SC1U10V2KX-1GP

C2133
SC10U6D3V3MX-GP

+V1.05S_AXCK_DCB J18
VCCCLK
1

K19 SERIAL IO U8 +V3.3S_1.8S_LPSS_SDIO

2
DY DY L2106 1 2 IND-2D2UH-196-GP +V1.05S_AXCK_LCPLL A20
VCCCLK VCCSDIO
T9
+V1.05S_SSCF100 VCCACLKPLL VCCSDIO +V3.3S_1.8S_LPSS_SDIO R2110 1
J17 2
2

68.2R21D.10R VCCCLK
C2135
SC1U10V2KX-1GP

C2136
SC100U6D3V6MX-GP

+V1.05S_SSCFF R21 0R0402-PAD-2-GP

1

1
2ND = 68.2R21G.10Q T21
VCCCLK LPT LP POWER C2137
TP_V1.05S_SSCF100 VCCCLK SUS OSCILLATOR
1 K18 AB8 +V1.05A_AOSCSUS SC1U10V2KX-1GP
TP2102 TP_V1.05S_AXCK_DCB RSVD#K18 DCPSUS4
1 M20
2

2
1D05V_M TP2103 TP_V1.05S_SSCFF RSVD#M20
1 V21
TP2104 +V3.3A_PSUS RSVD#V21 RSVD#AC20 TP2105 1D05V_S0
AE20 AC20 1
R2111 1 VCCSUS3_3 RSVD#AC20
3D3V_S5_PCH 2 AE21 AG16 1D05V_S0
R2112 1 +V1.05A_USB2SUS VCCSUS3_3 USB2 VCC1_05
DY 2 0R2J-2-GP 0R0402-PAD-2-GP AG17

1
VCC1_05

C2139
SC22U6D3V5MX-2GP
+V1.05S_SSCFF R2117 2 1
C2138
SC1U10V2KX-1GP

0R0402-PAD-2-GP
1

SC1U10V2KX-1GP
C2141
2
DY

1
HASWELL-6-GP-U
2

2
+V3.3A_DSW_P
3D3V_S5_PCH

R2114 1 2 0R2J-2-GP +V3.3A_DSW_P

DY
3D3V_S5
1

C2142
R2115 1 2 0R0402-PAD-2-GP SCD1U16V2KX-3GP
+V3.3A_DSW_P PCH_VCCDSW
2

C2147

1 DY2
1D05V_S0 SCD47U6D3V2KX-GP

R2116 1 2 0R0402-PAD-2-GP +V1.05S_SSCF100

B B
C2143
SC1U10V2KX-1GP
1
2

3D3V_S0
+1.5V_THERMAL
U2101

5 1
VOUT VIN
2
VSS

C2145
SC1U10V2KX-1GP

C2146
SC1U10V2KX-1GP
4 3
NC#4 ON/OFF

1
S-1339D15-M5001-GP

2
74.01339.B3F
2nd = 074.09198.0A3F
53 mA

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (POWER1)
Size Document Number Rev
A2 A00
Round Rock MLK 13.3"
Date: Monday, August 17, 2015 Sheet 21 of 110
5 4 3 2 1
 5 4 3 2 1

D D

HSW_ULT_DDR3L
CPU1Q 17 OF 19

TP2201 1 DC_TEST_AY2_AW2 AY2 A3 DC_TEST_A3_B3

TP2202 DC_TEST_AY3_AW3 DAISY_CHAIN_NCTF_AY2 DAISY_CHAIN_NCTF_A3 TP_DC_TEST_A4 TP2203
1 AY3 DAISY_CHAIN_NCTF_AY3 DAISY_CHAIN_NCTF_A4 A4 1
TP2204 1 TP_DC_TEST_AY60 AY60
TP2205 DC_TEST_AY61_AW61 AY61 DAISY_CHAIN_NCTF_AY60 TP_DC_TEST_A60 TP2206
1 DAISY_CHAIN_NCTF_AY61 DAISY_CHAIN_NCTF_A60 A60 1
TP2207 1 DC_TEST_AY62_AW62 AY62 A61 DC_TEST_A61_B61
TP2208 TP_DC_TEST_B2 DAISY_CHAIN_NCTF_AY62 DAISY_CHAIN_NCTF_A61 TP_DC_TEST_A62 TP2209
1 B2 DAISY_CHAIN_NCTF_B2 DAISY_CHAIN_NCTF_A62 A62 1
TP2210 1 DC_TEST_A3_B3 B3 AV1 TP_DC_TEST_AV1 1 TP2211
TP2212 DC_TEST_A61_B61 DAISY_CHAIN_NCTF_B3 DAISY_CHAIN_NCTF_AV1 TP_DC_TEST_AW1 1 TP2213
1 B61 DAISY_CHAIN_NCTF_B61 DAISY_CHAIN_NCTF_AW1 AW1
DC_TEST_B62_B63 B62 AW2 DC_TEST_AY2_AW2
DAISY_CHAIN_NCTF_B62 DAISY_CHAIN_NCTF_AW2 DC_TEST_AY3_AW3
B63 DAISY_CHAIN_NCTF_B63 DAISY_CHAIN_NCTF_AW3 AW3
DC_TEST_C1_C2 C1 AW61 DC_TEST_AY61_AW61
DAISY_CHAIN_NCTF_C1 DAISY_CHAIN_NCTF_AW61 DC_TEST_AY62_AW62
C2 DAISY_CHAIN_NCTF_C2 DAISY_CHAIN_NCTF_AW62 AW62
AW63 TP_DC_TEST_AW63 1 TP2214
DAISY_CHAIN_NCTF_AW63
HASWELL-6-GP-U
C C

HSW_ULT_DDR3L
CPU1R 18 OF 19

RSVD#N23 N23
RSVD#R23 R23
AT2 RSVD#AT2 RSVD#T23 T23
AU44 RSVD#AU44 RSVD#U10 U10
AV44 RSVD#AV44
D15 RSVD#D15
RSVD#AL1 AL1
RSVD#AM11 AM11
F22 RSVD#F22 RSVD#AP7 AP7
H22 RSVD#H22 RSVD#AU10 AU10
B B
J21 RSVD#J21 RSVD#AU15 AU15
RSVD#AW14 AW14
RSVD#AY14 AY14

HASWELL-6-GP-U

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (RSVD)
Size Document Number Rev
A4 A00
Round Rock MLK 13.3"
Date: Monday, August 17, 2015 Sheet 22 of 110
5 4 3 2 1
 5 4 3 2 1

SSID = PCH

HSW_ULT_DDR3L
CPU1O 15 OF 19
CPU1N HSW_ULT_DDR3L 14 OF 19
AP22 VSS VSS AV59
A11 VSS VSS AJ35 AP23 VSS VSS AV8
A14 VSS VSS AJ39 AP26 VSS VSS AW16
D A18 VSS VSS AJ41 AP29 VSS VSS AW24 D
A24 VSS VSS AJ43 AP3 VSS VSS AW33
A28 VSS VSS AJ45 AP31 VSS VSS AW35
A32 VSS VSS AJ47 AP38 VSS VSS AW37
A36 VSS VSS AJ50 AP39 VSS VSS AW4
A40 VSS VSS AJ52 AP48 VSS VSS AW40
A44 VSS VSS AJ54 AP52 VSS VSS AW42
A48 VSS VSS AJ56 AP54 VSS VSS AW44
A52 VSS VSS AJ58 AP57 VSS VSS AW47
A56 VSS VSS AJ60 AR11 VSS VSS AW50
AA1 VSS VSS AJ63 AR15 VSS VSS AW51
AA58 VSS VSS AK23 AR17 VSS VSS AW59
AB10 VSS VSS AK3 AR23 VSS VSS AW60
AB20 VSS VSS AK52 AR31 VSS VSS AY11
AB22 VSS VSS AL10 AR33 VSS VSS AY16
AB7 VSS VSS AL13 AR39 VSS VSS AY18
AC61 VSS VSS AL17 AR43 VSS VSS AY22
AD21 VSS VSS AL20 AR49 VSS VSS AY24
AD3 VSS VSS AL22 AR5 VSS VSS AY26
AD63 VSS VSS AL23 AR52 VSS VSS AY30
AE10 VSS VSS AL26 AT13 VSS VSS AY33
AE5 VSS VSS AL29 AT35 VSS VSS AY4
AE58 VSS VSS AL31 AT37 VSS VSS AY51
AF11 VSS VSS AL33 AT40 VSS VSS AY53
AF12 VSS VSS AL36 AT42 VSS VSS AY57
AF14 VSS VSS AL39 AT43 VSS VSS AY59
AF15 VSS VSS AL40 AT46 VSS VSS AY6
AF17 VSS VSS AL45 AT49 VSS VSS B20
AF18 VSS VSS AL46 AT61 VSS VSS B24
C AG1 AL51 AT62 B26 C
VSS VSS VSS VSS
AG11 VSS VSS AL52 AT63 VSS VSS B28
AG21 VSS VSS AL54 AU1 VSS VSS B32
AG23 VSS VSS AL57 AU16 VSS VSS B36
AG60 VSS VSS AL60 AU18 VSS VSS B4
AG61 VSS VSS AL61 AU20 VSS VSS B40
AG62 VSS VSS AM1 AU22 VSS VSS B44
AG63 VSS VSS AM17 AU24 VSS VSS B48
AH17 VSS VSS AM23 AU26 VSS VSS B52
AH19 VSS VSS AM31 AU28 VSS VSS B56
AH20 VSS VSS AM52 AU30 VSS VSS B60
AH22 VSS VSS AN17 AU33 VSS VSS C11
AH24 VSS VSS AN23 AU51 VSS VSS C14
AH28 VSS VSS AN31 AU53 VSS VSS C18
AH30 VSS VSS AN32 AU55 VSS VSS C20
AH32 VSS VSS AN35 AU57 VSS VSS C25
AH34 VSS VSS AN36 AU59 VSS VSS C27
AH36 VSS VSS AN39 AV14 VSS VSS C38
AH38 VSS VSS AN40 AV16 VSS VSS C39
AH40 VSS VSS AN42 AV20 VSS VSS C57
AH42 VSS VSS AN43 AV24 VSS VSS D12
AH44 VSS VSS AN45 AV28 VSS VSS D14
AH49 VSS VSS AN46 AV33 VSS VSS D18
AH51 VSS VSS AN48 AV34 VSS VSS D2
AH53 VSS VSS AN49 AV36 VSS VSS D21
AH55 VSS VSS AN51 AV39 VSS VSS D23
AH57 VSS VSS AN52 AV41 VSS VSS D25
AJ13 VSS VSS AN60 AV43 VSS VSS D26
AJ14 VSS VSS AN63 AV46 VSS VSS D27
B B
AJ23 VSS VSS AN7 AV49 VSS VSS D29
AJ25 VSS VSS AP10 AV51 VSS VSS D30
AJ27 VSS VSS AP17 AV55 VSS VSS D31
AJ29 VSS VSS AP20
HASW ELL-6-GP-U

HASW ELL-6-GP-U

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (VSS)
Size Document Number Rev
A3 A00
Round Rock MLK 13.3"
Date: Monday, August 17, 2015 Sheet 23 of 110
5 4 3 2 1
 5 4 3 2 1

3D3V_S5
SSID = KBC 3D3V_S5

RTC_AUX_S5

1
R2403 R2402 1 2 0R0402-PAD-2-GP
0R0402-PAD-2-GP

1
EV
C2402 EV follow Houston
SCD1U16V2KX-3GP U2401

2
R2401 1 2 0R0603-PAD-2-GP-U VTR_ADC 68.00084.921 VBAT B64 A10 AC_DIS AC_DIS 44 RN2407
VBAT GPIO21/RC_ID1/GANG_FULL

C2401
SCD1U16V2KX-3GP

C2406
SC1U10V2KX-1GP
2nd = 68.00217.401 B10 BOARD_ID PBAT_SMBCLK 5 4
GPIO20/RC_ID2

1
B8 NGFF_PCIE#_SATA PBAT_SMBDAT 6 3
GPIO14/GPTP-IN7/RC_ID3 NGFF_PCIE#_SATA 19
L2107 1 2 BLM15AG121SN-1GP H_VTR A22 B27 LAN_WAKE#_EC 1 2 USH_SMBDAT 7 2
H_VTR GPIO25/UART_CLK HOST_DEBUG_TX R2471 0R0402-PAD-2-GP LAN_WAKE# 20,30,99 USH_SMBCLK
B44 8 1

2
GPIO120/UART_TX/V2P_COUT_HI1

1
C2407 C2408 B46 ME_FWP_EC ME_FWP_EC 98
SCD1U16V2KX-3GP SC1U10V2KX-1GP VTR_ADC GPIO124/GPTP-OUT5/UART_RX/V2P_COUT_LO1 SRN2K2J-4-GP
A58 B26
VTR_ADC VCC_PWRGD EN_INVPWR RUNPWROK 36 RN2405
A25 EN_INVPWR 52

2
GPIO60/KBRST/BCM_B_INT# EXPRESS_SMBDATA
B36 3 2
5085_VTR GPIO101/ECGP_SCLK SIO_SLP_S4# 17,36,49 EXPRESS_SMBCLK
D B3 B37 LANPWR_EN_EC 36 4 1 D
VTR GPIO103/ECGP_MISO

C2409
SC10U10V5KX-2GP

C2410
SCD1U16V2KX-3GP

C2403
SCD1U16V2KX-3GP

C2411
SCD1U16V2KX-3GP

C2404
SCD1U16V2KX-3GP

C2405
SCD1U16V2KX-3GP

C2412
SCD1U16V2KX-3GP

C2413
SCD1U16V2KX-3GP
A11 B38 USBPOWERSHARE_EN#

1
VTR GPIO105/ECGP_MOSI PCH_ALW_ON USBPOWERSHARE_EN# 35 SRN2K2J-1-GP
A26 A34 PCH_ALW_ON 36
VTR GPIO102/BCM_C_INT# RN2406
B35 A35
VTR GPIO104/SLP_S0# SIO_SLP_S3# 17,36,49 CHARGER_SMBCLK
A41 A36 PCH_DPWROK 17 4 1

2
VTR GPIO106 MSDATA CHARGER_SMBDAT
A52 A40 3 2
VTR GPIO116/MSDATA/V2P_COUT_LO0/TAP_SEL_STRAP MSCLK
B43
GPIO117/MSCLK/V2P_COUT_HI0 PCH_RSMRST# SRN10KJ-5-GP
A45 PCH_RSMRST# 18
GPIO127/A20M FWP#
B65
FWP# BC_DAT_ECE1117 100KR2J-1-GP
18 SML1_SMBDATA A5 2 1 R2404
GPIO7/I2C1D_DATA/PS2_CLK0B/I2C3A_DATA BC_DAT_ECE1099 100KR2J-1-GP
18 SML1_SMBCLK B6 2 1 R2405
GPIO10/I2C1D_CLK/PS2_DAT0B/I2C3A_CLK/GANG_DATA0 BREATH_LED#_EC
62 CLK_TP_SIO A37 B57 1 2 BREATH_LED# 61
GPIO110/PS2_CLK2/GPTP-IN6 GPIO156/LED1/GANG_DATA1 R2467 0R0402-PAD-2-GP
62 DAT_TP_SIO B40 B1 BAT1_LED# 61
GPIO111/PS2_DAT2/GPTP-OUT6 GPIO157/LED0
52 LCD_TST A38 A55 BAT2_LED# 61
GPIO112/PS2_CLK1A GPIO153/LED2/GANG_DATA4 ALW_PWRGD_3V_5V_EC1
EV reverve for factory test 42 AC_DIS_TEST B41 A1 2
GPIO113/PS2_DAT1A GPIO27/GPTP-OUT1 SIO_SLP_A# R2468 0R0402-PAD-2-GP ALW_PWRGD_3V_5V 18,45 BREATH_LED# 100KR2J-1-GP
36 LCD_VCC_TEST_EN A39 B28 SIO_SLP_A# 17,36,48 2 DY 1 R2428
GPIO114/PS2_CLK0A GPIO26/GPTP-IN1 EC_32KHZ_MEC5085 1
B42 B2 TP2411
PBAT_SMBDAT GPIO115/PS2_DAT0A GPIO1/ECSPI_CS1/32KHZ_OUT PBAT_PRES# 100KR2J-1-GP 2
43 PBAT_SMBDAT B59 A8 1 R2412
PBAT_SMBCLK GPIO154/I2C1C_DATA/PS2_CLK1B/GANG_DATA5 GPIO15/GPTP-OUT7 RUN_ON ME_SUS_PWR_ACK 17
43 PBAT_SMBCLK A56 B9 RUN_ON 36,49
GPIO155/I2C1C_CLK/PS2_DAT1B/GANG_DATA6 GPIO16/GPTP-IN8 PM_APWROK
A9 PM_APWROK 36
JTAG_TDI GPIO17/GPTP-OUT8 RESET_OUT#
A51 B39 RESET_OUT# 17,36
0 = Reset JTAG I/F JTAG_TDO B55
GPIO145/I2C1K_DATA/JTAG_TDI GPIO107/RESET_OUT#
A44 PCH_PCIE_WAKE#
GPIO146/I2C1K_CLK/JTAG_TDO GPIO125/GPTP-IN5/PECI_REQUEST#/GANG_BUSY PCH_PCIE_WAKE# 17
1 = Disable JTAG_CLK B56 B47 JTAG_RST#
JTAG_TMS GPIO147/I2C1J_DATA/I2C2C_DATA/JTAG_CLK JTAG_RST#
A53 A54 AC_PRESENT 17
I_SYS GPIO150/I2C1J_CLK/I2C2C_CLK/JTAG_TMS GPIO151/GPTP-IN4/GANG_DATA2 SIO_PWRBTN# AC_DIS 100KR2J-1-GP 2
44 I_SYS A57 B58 SIO_PWRBTN# 17 DY 1 R2406
3D3V_S0 V_ISYS1 GPIO152/GPTP-OUT4
FAN1_TACH_FB B22 A3 EXPRESS_SMBDATA
26 FAN1_TACH_FB GPIO50/FAN_TACH1/GTACH0/GANG_START GPIO3/I2C1A_DATA
LID_CL_SIO# A21 B4 EXPRESS_SMBCLK
61,98 LID_CL_SIO# GPIO51/FAN_TACH2/GANG_MODE GPIO4/I2C1A_CLK
36,49 SUS_ON B23 A4
GPIO52/FAN_TACH3/GTACH1/GANG_ERROR GPIO5/I2C1B_DATA/BCM_B_DAT A_ON 36,48
R2409 1 FAN1_TACH_FB B24 B5 SIO_EXT_WAKE# 20
2 10KR2J-3-GP 42 PSID_EC GPIO53/PWM0 GPIO6/I2C1B_CLK/BCM_B_CLK
17 SUSACK# R2464 1 2 0R0402-PAD-2-GP EC_GPIO54 A23 B7 SYS_PWROK
R2411 1 FAN1_PWM BIA_PWM_EC GPIO54/PWM1/GPWM1 GPIO12/I2C1H_DATA/I2C2D_DATA SYS_PWROK 17,96
2 10KR2J-3-GP 52 BIA_PWM_EC B25 A7
FAN1_PWM GPIO55/PWM2 GPIO13/I2C1H_CLK/I2C2D_CLK/GANG_DATA3 GPU_SMBDAT ENVDD_PCH 15,36
R2408 1 NGFF_PCIE#_SATA 26 FAN1_PWM A24 B48
2 100KR2J-1-GP GPIO56/PWM3/GPWM0 GPIO130/I2C2A_DATA/BCM_C_DAT GPU_SMBCLK
B49
RN2404 GPIO131/I2C2A_CLK/BCM_C_CLK CHARGER_SMBDAT
A47 CHARGER_SMBDAT 44
GPU_SMBDAT GPIO132/I2C1G_DATA CHARGER_SMBCLK
2 3 B50 CHARGER_SMBCLK 44
GPU_SMBCLK GPIO140/I2C1G_CLK SIO_SLP_SUS# USBPOWERSHARE_EN# 100KR2J-1-GP
1 4 99 BC_CLK_ECE1099 A43 B52 SIO_SLP_SUS# 17 2 1 R2415
GPIO123/BCM_A_CLK GPIO141/I2C1F_DATA/I2C2B_DATA PBAT_PRES#
99 BC_DAT_ECE1099 B45 A49 PBAT_PRES# 43,44
SRN2K2J-1-GP R2433 GPIO122/BCM_A_DAT GPIO142/I2C1F_CLK/I2C2B_CLK USH_SMBDAT
A42 B53 THERMATRIP3#
99 BC_INT#_ECE1099 ACAV_IN_NB GPIO121/BCM_A_INT# GPIO143/I2C1E_DATA USH_SMBCLK EV 10KR2J-3-GP 2 1 R2456
44 ACAV_IN 1 DY 2 B20
GPIO32/BCM_E_CLK GPIO144/I2C1E_CLK
A50
0R2J-2-GP 17 SIO_SLP_S5# A18
BEEP GPIO31/GPTP-OUT2/BCM_E_DAT SYSPWR_PRES
C
27 BEEP B19 A59 C
BC_CLK_ECE1117 GPIO30/GPTP-IN2/BCM_E_INT#/GANG_DATA7 SYSPWR_PRES
62 BC_CLK_ECE1117 A20
BC_DAT_ECE1117 GPIO47/LSBCM_D_CLK
62 BC_DAT_ECE1117 B21 A64
R2466 1 LANPWR_EN_EC BC_INT#_ECE1117 GPIO46/LSBCM_D_DAT/GANG_STROBE VCI_OVRD_IN ALWON ACAV_IN 44
2 100KR2J-1-GP 62 BC_INT#_ECE1117 A19 A60 ALWON 36
GPIO45/LSBCM_D_INT# VCI_OUT POWER_SW_IN# RTC_AUX_S5
B67
R2431 1 2 100KR2J-1-GP PCH_ALW_ON EV A6
VCI_IN0#
A63 EC5085_VCI_IN1# 1D05V_S0
16,20 SIO_EXT_SMI# GPIO11/SMI# VCI_IN1#
A27 B63 VCI_IN2# VCI_IN2# 100KR2J-1-GP 1 2 R2417
20 SIO_RCIN# GPIO61/LPCPD# VCI_IN2#
IRQ_SERIRQ A28 B68 POA_WAKE# R2424 1 2 0R0402-PAD-2-GP
R2425 1 2 100KR2J-1-GP LCD_TST 20 IRQ_SERIRQ SER_IRQ VCI_IN3#
17,65,88 PCH_PLTRST#_EC PCH_PLTRST#_EC B30 POA_WAKE# 100KR2J-1-GP 1 2 R2419
R2470 1 A_ON CLK_PCI_MEC LRESET# PECI_VREF
2 100KR2J-1-GP 18 CLK_PCI_MEC A29 B51 C2415 1 2 SCD1U16V2KX-3GP
LPC_LFRAME# PCI_CLK VREF_PECI PECI_EC_R R2426 1 SIO_PWRBTN#
R2469 1 RUN_ON 18,65 LPC_LFRAME# B31 A48 2 43R2J-GP 100KR2J-1-GP 1 DY 2 R2421
2 100KR2J-1-GP LPC_LAD0 LFRAME# PECI_DAT H_PECI 4
18,65 LPC_LAD0 A30
R2465 1 SUS_ON LPC_LAD1 LAD0 EC5085_VCI_IN1#
2 100KR2J-1-GP 18,65 LPC_LAD1 B32 C2416 1 DY2 SC100P50V2JN-3GP 100KR2J-1-GP 1 2 R2436
LPC_LAD2 LAD1 REM_DIODE1_N
18,65 LPC_LAD2 A31 B13 REM_DIODE1_N 26
LPC_LAD3 LAD2 DN1_DP1A/THERM REM_DIODE1_P
18,65 LPC_LAD3 B33 A13 REM_DIODE1_P 26
R2422 1 PCH_RSMRST# LAD3 DP1_DN1A/VREF_T REM_DIODE2_N
2 10KR2J-3-GP 17 CLKRUN# A32 B14 REM_DIODE2_N 26
CLKRUN# DN2_DP2A REM_DIODE2_P
20 SIO_EXT_SCI# A33 A14 REM_DIODE2_P 26
R2423 1 FAN1_PWM GPIO100/EC_SCI# DP2_DN2A
DY 2 100KR2J-1-GP A15
MEC_XTAL1 DN3_DP3A
A61 B16
MEC_XTAL2 XTAL1 DP3_DN3A
R2432 1 2 0R0402-PAD-2-GP MEC_XTAL2_R A62 A16 REM_DIODE4_N
REM_DIODE4_N 26
XTAL2 DN4_DP4A REM_DIODE4_P
B62 B17 REM_DIODE4_P 26
R2427 1 EN_INVPWR BGPO DP4_DN4A
2 100KR2J-1-GP B15
VIN VSET_5085
A17
X2401 VSET I_ADP
A12
VCP THERMATRIP2# I_ADP 44 RTC_AUX_S5
B34
THERMTRIP2# THERMATRIP3#
A2
RESET_OUT# 1 4 GPIO2/THERMTRIP3# THSEL_STRAP

VSS_ADC
R2429 1 2 10KR2J-3-GP B29

VSS_RO
GPIO24/THSEL_STRAP

VR_CAP

1
A46 PROCHOT#_EC

H_VSS
1

PROCHOT_IN#/PROCHOT_IO#

AGND
B61 I_BATT_R R2434 1 2 4K7R2J-2-GP R2418

GND
VSS
C2417 C2418 V_ISYS0 I_BATT 44
R2430 1 2 100KR2J-1-GP FAN1_TACH_FB
DY SC20P50V2JN-1GP 2 3 SC20P50V2JN-1GP 100KR2J-1-GP
2

MEC5085-LZY-RRM00-GP

B66

B11

B60

B12

B54

B18

C1

2
XTAL-32D768KHZ-6-GP 071.05085.0B03
POWER_SW_IN# 1 2 R2435
+/- 20 ppm MB_PWR_BTN# 17,61
CL=7 pF 10KR2J-3-GP
A00
82.30001.B21

1
1KBC_VR_CAP
C2419
2nd = 82.30001.661 SC1U10V2KX-1GP
3rd = 82.30001.B41 X02

2
B B

C2421
SC4D7U6D3V3KX-GP

2
R2437
THSEL_STRAP 1KR2J-1-GP 2 1

3D3V_S5 3D3V_S5
EV
CLK_PCI_MEC
VSET_5085
1
1

1
C2422
SCD1U16V2KX-3GP
R2439

1
R2438 10R2J-2-GP R2440 3D3V_S5 R2441
100KR2J-1-GP
DY 10KR2J-3-GP 953R2F-GP
2

2
Place close
CLK_PCI_MEC_C
2

2
1
JTAG_RST# FWP#
to Pin58 R2442
2

1
C2423
SC1U10V2KX-1GP

8K2R2J-3-GP
1

R2443 R2444
100R2J-2-GP DY DY 10KR2J-3-GP

2
THERMATRIP2#
2

C2424 3D3V_S5 1D05V_S0 3D3V_AUX_S5

C
1

C2425
SCD1U16V2KX-3GP
DY SC4D7P50V2CN-1GP

1
R2445 1 2THERMTRIP2#_B B Q2402
2

2K2R2J-2-GP LMBT3904LT1G-GP

2
1

1
R2446
49D9R2F-GP

R2447
10KR2J-3-GP

R2448
10KR2J-3-GP

R2449
10KR2J-3-GP

R2450
10KR2J-3-GP

R2451
10KR2J-3-GP

R2452
100KR2J-1-GP

R2453
10KR2J-3-GP

R2454
10KR2J-3-GP

20 H_THERMTRIP# 84.T3904.H11
2nd = 84.T3904.K11 R2455
JTAG DY 3rd = 84.03904.E11 1KR2J-1-GP
3D3V_S5
2

2
JTAG1 SYSPWR_PRES
A00 11
Round Rock MLK 13.3"

1
JTAG_PU
1

1
R2458
R2457 BOARD_ID 2 JTAG_TDI 100KR2J-1-GP
1KR2F-L-GP
REV 3 JTAG_TMS EV
A Cap. Value Res. Value 4 JTAG_CLK A

2
240k ohm EV JTAG_TDO
2

BOARD_ID JTAG 5
MSCLK
PROCHOT#_EC R2461 1 2 0R0402-PAD-2-GP H_PROCHOT# 4,44,46
6
130k ohm X01 MSDATA

1
7
HOST_DEBUG_TX_C R2460 1 2 0R2J-2-GP HOST_DEBUG_TX
1

C2427 8 JTAG C2428

SC4700P50V2KX-1GP 4700pF 33k ohm X02 9 EC5048_TX SC47P50V2JN-3GP <Core Design>

2
10
1k ohm A00
2

12

ACES-CON10-28-GP-U R2463 pull DN, Enable JTAG debug mode Wistron Corporation
20.K0460.010 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
MSDATA R2463 1 2 10KR2J-3-GP
Title

EC - MEC5085
Size Document Number Rev
A2 A00
Round Rock MLK 13.3"
Date: Tuesday, August 18, 2015 Sheet 24 of 110
5 4 3 2 1
 5 4 3 2 1

SSID = Flash.ROM SPI ROM Equal length need to less than 500mil

3D3V_M 3D3V_M
ROMSK1
R2501 1 2 1KR2J-1-GP SPI_HOLD# SPI_CS0# 1 8
SPI_DIN_64 2 7 SPI_HOLD#
R2509 1 2 1KR2J-1-GP SPI0_W P# SPI0_W P#_1 3 6 SPI_CLK_64
D 4 5 SPI_DI_64 D
R2510 1 2 3K3R2J-3-GP PCH_SPI_CS0#
SKT-G6179HT0321-001-GP
Schematic Design Checklist
Single Device: 15 62.10089.011
3D3V_M
Multiple Devices: 33 per branch

C2502
SC10U6D3V3MX-GP

C2501
SCD1U16V2KX-3GP
R2502

1
18,88 PCH_SPI_SO 1 2 SPI_DIN_64
33R2J-2-GP
DY

2
SYSTEM SPI ROM 3D3V_M
R2503
18,88 PCH_SPI_CLK 1 2 SPI_CLK_64 U2501
33R2J-2-GP
R2511 1 2 0R0402-PAD-2-GP SPI_CS0#
18 PCH_SPI_CS0#
SPI_DIN_64
1
2
CS# VCC 8
7 SPI_HOLD# Layout Note: Close to U2501 Pin 8
R2514 1 DO/IO1 HOLD#/IO3
18 SPI0_W P# 2 33R2J-2-GP SPI0_W P#_1 3 WP#/IO2 CLK 6 SPI_CLK_64
4 5 SPI_DI_64
R2504 GND DI/IO0

18,88 PCH_SPI_SI 1 2 SPI_DI_64

1
SC4D7P50V2CN-1GP
W 25Q64FVSSIQ-GP EC2501
33R2J-2-GP DY EC2507 72.25Q64.K01 DY DY EC2502
SC4D7P50V2CN-1GP 2nd = 72.25647.00A SC4D7P50V2CN-1GP

2
C C

R2505
18 SPI_HOLD_0# 1 2 SPI_HOLD#
33R2J-2-GP

EV

SSID = RTC 3D3V_AUX_S5

RTC_AUX_S5 Q2501
2 +RTC_PW R

3 RTC1
R2528 3
1 RTC_PW R 1 2 +RTC_PW R 1
B B
BAS40CW -GP 1KR2J-1-GP 2
83.00040.E81 AFTP2501 1 4
2nd = 83.R2004.C81 Width=20mils
ACES-CON2-20-GP-U
20.F1639.002
2nd = 20.F1841.002

+RTC_PW R 1 AFTP2502

Q2502
G
1

D RTC_DET# [20]
R2506
10MR2J-L-GP S

2N7002K-2-GP
2

84.2N702.J31
2ND = 84.2N702.031
3rd = 84.2N702.W31
A <Variant Name> A

X02 Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Flash/RTC
Size Document Number Rev
A3
Round Rock MLK 13.3"A00
Date: Monday, August 17, 2015 Sheet 25 of 110
5 4 3 2 1
 5 4 3 2 1

SSID = Thermal 3D3V_S0

R2601
1 DY 2
0R2J-2-GP

U2601
D REM_DIODE1_P REM_DIODE1_P 24 24 FAN1_PWM 1 6 FAN1_PWM_Q D

2 5
C

1
Q2601 B DY C2601 C2607 FAN1_TACH_Q 3 4 FAN1_TACH_FB 24
LMBT3904LT1G-GP SC100P50V2JN-3GP SC2200P50V2KX-2GP

2
2N7002KDW-GP
E

84.T3904.H11 REM_DIODE1_N REM_DIODE1_N 24 84.2N702.A3F

2nd = 84.T3904.K11 2nd = 84.DMN66.03F
3rd = 84.03904.E11

Layout Note: Close to EC R2602

1 DY 2
0R2J-2-GP
Layout Note: Place to CPU
Both DXN and DXP routing 10 mil trace width and 10 mil spacing.

5V_S0 5V_S0

C C
FAN

1
2K2R2J-2-GP
R2529

2K2R2J-2-GP
R2530
REM_DIODE2_P REM_DIODE2_P 24
C

Q2602 B DY C2602 C2603

2
LMBT3904LT1G-GP SC100P50V2JN-3GP SC2200P50V2KX-2GP FAN1
2

6
E

84.T3904.H11 REM_DIODE2_N REM_DIODE2_N 24 FAN1_PWM_Q 4

2nd = 84.T3904.K11 FAN1_TACH_Q 3
3rd = 84.03904.E11 5V_S0 2

AFTP2601
Layout Note: Close to EC 1 1
5
Layout Note:Place to DIMM ACES-CON4-29-GP

1
Both DXN and DXP routing 10 mil trace width and 10 mil spacing. C2604 20.F1639.004
SC4D7U6D3V3KX-GP 2nd = 20.F1804.004

2
EV ME
B B

REM_DIODE4_P REM_DIODE4_P 24
Layout Note: FAN1_TACH_Q 1 AFTP2602
Signal Routing Guideline: FAN1_PWM_Q 1 AFTP2603
Trace width = 15mil
C

Q2603 B DY C2605 C2606

LMBT3904LT1G-GP SC100P50V2JN-3GP SC2200P50V2KX-2GP
2

2
E

84.T3904.H11 REM_DIODE4_N REM_DIODE4_N 24

2nd = 84.T3904.K11
3rd = 84.03904.E11

Layout Note: Close to EC

Layout Note:Place to V.R <Core Design>
Both DXN and DXP routing 10 mil trace width and 10 mil spacing.

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
Thermal/Fan
Size Document Number Rev
A4 A00
Round Rock MLK 13.3"
Date: Monday, August 17, 2015 Sheet 26 of 110
5 4 3 2 1
 5 4 3 2 1

SSID = AUDIO
3D3V_S0 3V_DVDD
106.871mA
R2745
1 2
29 MIC2-VREFO 0R0603-PAD-2-GP-U

AUD_AGND

AUD_AGND
29 LINE1-VREFO-R

1
29 LINE1-VREFO-L C2727
29 AUD_HP1_JACK_L SC10U6D3V3MX-GP
29 AUD_HP1_JACK_R

2
1.5A

SC1U10V2KX-1GP
5V_S0 5V_PVDD
Max =50mA

SC2D2U6D3V2MX-GP
+1.5V_THERMAL +3V_1D5V_AVDD

SC10U6D3V3MX-GP
R2705
D 1 2 1 2 D
5V_S0 5V_AVDD 0R0603-PAD-2-GP-U R2703 0R0402-PAD-2-GP
14.542 mA

1 C2710

1 C2711
C2728 C2705 C2706 C2709

SCD1U16V2KX-3GP
R2738 R2706

1
SC10U6D3V3MX-GP

SCD1U16V2KX-3GP

SC10U6D3V3MX-GP
1 2 1 2 EV Moat

3V_DVDD
0R0603-PAD-2-GP-U 0R0603-PAD-2-GP-U R2737

1
100KR2J-1-GP

CPVEE 2
1

1
C2702 C2703 C2704
SC4D7U6D3V3KX-GP
Moat Layout Note:

LINE1-VREFO-R
LINE1-VREFO-L
SC4D7U6D3V3KX-GP

C2707

2
SCD1U16V2KX-3GP
2

Place close to Pin 26

AUD_VREF

LDO1_CAP
1 2 5V_AVDD

CBN
Layout Note: Layout Note: AUD_AGND
Moat

1
Close PIN41 Close PIN46 C2712 C2701 AUD_AGND close to pin 40
SC1U10V2KX-1GP SC4D7U6D3V3KX-GP

2
AUD_AGND

36

35

34

33

32

31

30

29

28

27

26

25
U2701

CPVEE

HPOUT-L/PORT-I-L

LINE1-VREFO-L

MIC2-VREFO

LDO1-CAP

AVDD1

AVSS1
CPVDD

CBN

HPOUT-R/PORT-I-R

LINE1-VREFO-R

VREF
R2740
1 2
0R0603-PAD-2-GP-U CBP 37 24
R2741 Layout Note: CBP LINE2_L/PORT-E-L
1 2 trace width=30mil AUD_AGND 38
AVSS2 LINE2_R/PORT-E-R
23
0R0603-PAD-2-GP-U R2707,R2709,R2710,R2711 near CODEC
R2742 SC10U6D3V3MX-GP 2 1 C2713 LDO2_CAP 39 22
AUD_AGND LDO2-CAP LINE1_L/PORT-C-L LINE1-L 29
1 2
0R0603-PAD-2-GP-U 3D3V_S5
Analog +3V_1D5V_AVDD 40
AVDD2 LINE1_R/PORT-C-R
21
LINE1-R 29
V3D3_STB R2722 1 0R0402-PAD-2-GP
DigiTal 5V_PVDD 41
PVDD1 NC#20
20 2

AUD_AGND Layout Note: R2707 1 2 0R0603-PAD-2-GP-U AUD_SPK_L+ 42 19 MIC_CAP 1 2 AUD_AGND

29 AUD_SPK_L+_R SPK-OUT-L+ MIC-CAP
Tied at point only under SSID 0x070C C2714 SC10U6D3V3MX-GP
R2709 1 2 0R0603-PAD-2-GP-U AUD_SPK_L- 43 18
Codec or near the Codec 29 AUD_SPK_L-_R SPK-OUT-L- SVID 0x1028 MIC2_R/PORT-F-R/SLEEVE SLEEVE 29
R2710 1 2 0R0603-PAD-2-GP-U AUD_SPK_R- 44 17 3V_DVDD
29 AUD_SPK_R-_R SPK-OUT-R- MIC2_L/PORT-F-L/RING RING2 29
R2711 1 2 0R0603-PAD-2-GP-U AUD_SPK_R+ 45 16 R2727

1
29 AUD_SPK_R+_R SPK-OUT-R+ MONO-OUT 0R2J-2-GP
5V_PVDD 46 15 SPDIFO 1 DY 2 AUD_AGND
Layout Note: DY R2736
PVDD2 SPDIFO/FRONT_JD/JD3/GPIO3
Place close to Pin 13

GPIO0/DMIC-DATA
C 100KR2J-1-GP C

GPIO1/DMIC-CLK
R2714 1 2 0R0402-PAD-2-GP EAPD# 47 14
99 AUD_NB_MUTE# PDB MIC2/LINE2_JD/JD2 R2715

2
SDATA-OUT
48 13 AUD_SENSE_A 1 2
SPDIF-OUT/GPIO2 HP/LINE1_JD/JD1 AUD_HP_NB_SENSE 29,99

LDO3-CAP

SDATA-IN

DVDD-IO

PCBEEP

1
Moat

RESET#
49 200KR2J-L1-GP

2
GND

DVDD

SYNC
DVSS

BCLK
2 1 3V_DVDD R2743
100KR2J-1-GP R2746 100KR2J-1-GP DY DY C2729
1 DY 2 Analog SC4D7U6D3V3KX-GP

1
R2716 ALC3234-CG-GP

10

11

12

2
10KR2J-3-GP
1 2
71.03234.003 DigiTal
3V_DVDD
R2717

1 LDO3_CAP
1KR2J-1-GP

1 R2724 DVSS
3V_DVDD 3V_DVDD
C2717

C2719
0R2J-2-GP
1

C2718
EV follow Houston C2716

SCD1U16V2KX-3GP
SC4D7U6D3V3KX-GP

1
SB_SPKR_R

2
DY

RN
SC10U6D3V3MX-GP

1
SCD1U16V2KX-3GP
1 RN2701 4

2
DMIC: > 5mil and keep out the analog signal AUD_PC_BEEP 1 2 AUD_PC_BEEP_D 3 HDA_SPKR 20
2 3 BEEP 24
close to pin 3 D2701

1
R2719 1 2 DMIC_DATA_R C2720
52 DMIC_DATA LBAT54CLT1G-GP 0R4P2R-PAD
0R0402-PAD-2-GP SCD1U16V2KX-3GP R2718

2
DMIC_CLK R2720 1 2 DMIC_CLK_R 1KR2J-1-GP 83.R2003.V81
52 DMIC_CLK 0R2J-2-GP 2nd = 75.00054.E7D
2

KBC_BEEP_R

2
C2721
DY ER2701 1 2 PCH_AZ_CODEC_SDOUT1 3rd = 75.00054.A7D
19 HDA_CODEC_SDOUT 0R0402-PAD-2-GP
SC22P50V2JN-4GP
1

1 DY 2
EC2701 SCD1U16V2KX-3GP X02
EV vendor review
Azalia I/F EMI
ER2702 1 2 HDA_CODEC_BITCLK_C
DMIC_DATA 19 HDA_CODEC_BITCLK 0R0402-PAD-2-GP
1 DY 2
2

EC2702 SCD1U16V2KX-3GP
B NON Delay B
DYEC2706
SC22P50V2JN-4GP 1
R2721
2 HDA_CODEC_SDIN0
1

19 HDA_SDIN0 33R2J-2-GP
3D3V_S5
19 HDA_CODEC_SYNC
HDA_CODEC_RST#
19 HDA_CODEC_RST#

1
R2723
100KR2J-1-GP DY

2Q2904_D
AUD_AGND

4
Q2701
3D3V_S0 DY 2N7002KDW-GP
84.2N702.A3F

3
2nd = 84.DMN66.03F

1
DY R2725
100KR2J-1-GP SLEEVE 29
R2726
0R2J-2-GP

2
99 AUD_NB_MUTE# 1 DY 2

R2729
1 DY 2 HDA_CODEC_RST#_R
19 HDA_CODEC_RST#
0R2J-2-GP

1
C2723
DY SC1U6D3V2KX-GP

2
A A

EC2703 1 2 SCD1U16V2KX-3GP

EC2704 1 2 SCD1U16V2KX-3GP

EC2705 1 2 SCD1U16V2KX-3GP <Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
AUD_AGND Title

Audio Codec ALC3234

Size Document Number Rev
A2 A00
Round Rock MLK 13.3"
Date: Monday, August 17, 2015 Sheet 27 of 110
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
A Taipei Hsien 221, Taiwan, R.O.C. A

Title

Reserved
Size Document Number Rev
A A00
Round Rock MLK 13.3"
Date: Monday, August 17, 2015 Sheet 28 of 110
5 4 3 2 1
 5 4 3 2 1

SSID = AUDIO
2W/ch
Speaker
SPK1
6
4 AUD_SPK_L+_R
D AUD_SPK_L-_R AUD_SPK_L+_R 27 D
3 AUD_SPK_L-_R 27
2 AUD_SPK_R-_R
AUD_SPK_R-_R 27
1 AUD_SPK_R+_R AUD_SPK_L+_R
AUD_SPK_R+_R 27 AUD_SPK_L-_R
5
AUD_SPK_R-_R
ACES-CON4-29-GP AUD_SPK_R+_R
20.F1639.004

1
83.RSB56.CAF

RSB5D6SMT2N-GP
D2901
83.RSB56.CAF

RSB5D6SMT2N-GP
D2902
83.RSB56.CAF

RSB5D6SMT2N-GP
D2903
83.RSB56.CAF

RSB5D6SMT2N-GP
D2904
2ND = 20.F1804.004

2
SC1KP50V2KX-1GP

SC1KP50V2KX-1GP

SC1KP50V2KX-1GP

SC1KP50V2KX-1GP
EV ME

EC2901

EC2902

EC2903

EC2904
1

1
AFTP2902 1 AUD_SPK_L-_R
AFTP2903 1 AUD_SPK_L+_R

2
AFTP2904 1 AUD_SPK_R-_R
AFTP2905 1 AUD_SPK_R+_R

C R2733 1 2 2K2R2J-2-GP 3V_DVDD C

Combo Jack MIC2-VREFO 27
R2734 1 2 2K2R2J-2-GP

1
R2901
AUDIO1 DY 10KR2J-3-GP
9
RING2_R R2911 2 0R0603-PAD-1-GP-U

2
1 1 RING2 27 AUD_JACK_PWR
MIC_JACK_R EL2904 1 2 0R0603-PAD-1-GP-U

1
2 SLEEVE 27
3 AUD_JACK_PWR
R2902
4 AUD_HP_NB_SENSE AUD_HP_NB_SENSE 27,99 0R0402-PAD-2-GP
5 AUD_PORTA_R_R_B EL2903 1 2 0R0603-PAD-1-GP-U AUD_HP1_JACK_R1 R2908 1 2 10R2J-2-GP
AUD_PORTA_L_R_B R2912 1 AUD_HP1_JACK_L1 R2907 1 AUD_HP1_JACK_R 27
6 2 0R0603-PAD-1-GP-U 2 10R2J-2-GP AUD_HP1_JACK_L 27

2
7
8
10 AUD_AGND
EC2905
SC470P50V2KX-3GP

EC2906
SC470P50V2KX-3GP

EC2907
SC470P50V2KX-3GP

EC2908
SC470P50V2KX-3GP
ACES-CON8-44-GP NON DELAY
1

1
B 20.F2191.008 B
AUD_AGND 2ND = 20.F1261.008 AUD_AGND
2

2 C2901 1 2 SC4D7U6D3V2MX-GP-U LINE1-L 27

C2902 1 2 SC4D7U6D3V2MX-GP-U LINE1-R 27
AUD_AGNDAUD_AGNDAUD_AGNDAUD_AGND
R2909 1 2 4K7R2J-2-GP
Default install to avoid radio noise issue LINE1-VREFO-L 27
R2910 1 2 4K7R2J-2-GP LINE1-VREFO-R 27

RING2_R
AUD_PORTA_L_R_B
<Core Design>
AUD_HP_NB_SENSE
AUD_PORTA_R_R_B
MIC_JACK_R
Wistron Corporation
1

1
83.RSB56.CAF

RSB5D6SMT2N-GP
D2905

83.RSB56.CAF

RSB5D6SMT2N-GP
D2906

83.RSB56.CAF

RSB5D6SMT2N-GP
D2907

83.RSB56.CAF

RSB5D6SMT2N-GP
D2908

83.RSB56.CAF

RSB5D6SMT2N-GP
D2909

A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, A

Taipei Hsien 221, Taiwan, R.O.C.
AFTP2901 1 MIC_JACK_R
AFTP2906 1 AUD_PORTA_L_R_B Title
AFTP2907 1 AUD_PORTA_R_R_B
AFTP2908 1 RING2_R Speaker/HPMIC CONN
2

AFTP2909 1 AUD_HP_NB_SENSE Size Document Number Rev

A4
Round Rock MLK 13.3" A00
Date: Monday, August 17, 2015 Sheet 29 of 110
5 4 3 2 1
 5 4 3 2 1

SSID = LAN
VDD10 U3001

3 AVDD10 HSIP 13 PCIE_TXP3 16

3D3V_LAN 8 14
AVDD10 HSIN PCIE_TXN3 16
30
Layout: C3021: colse to Pin8
AVDD10
17 PCIE_RXDP3 C3014 1 2 SCD1U16V2KX-3GP
VDD10 HSOP PCIE_RXP3 16
* Place C3021 to C3024 close to each VDD10 pin--3, 8, 22, 30 C3022 close to Pin3 32 18 PCIE_RXDN3 C3016 1 2 SCD1U16V2KX-3GP PCIE_RXN3 16
AVDD33 HSON
11 AVDD33
C3025: close to Pin30 19 LAN_RST#_R
SC1U10V2KX-1GP 2 PERST#
D C3024: close to Pin22 1 C3018 VDDREG 23 VDDREG CLKREQ# 12 LANCLK_REQ# 18,20 D
VDD10
L3001
SCD1U16V2KX-3GP2 1 C3023 22 15
LAN_REGOUT 1 2 DVDD10 REFCLK_P CLK_PCIE_LAN 18
REFCLK_N 16 CLK_PCIE_LAN# 18
IND-4D7UH-300-GP-U
68.4R71G.10G 31 LAN_MDI0P 1 MDIP0
2ND = 68.4R71E.10R C3012 C3019 C3021 C3022 C3025 C3024 2 28 LANXIN
31 LAN_MDI0N MDIN0 CKXTAL1 LANXOUT

1
CKXTAL2 29
4

SC4D7U6D3V3KX-GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
31 LAN_MDI1P MDIP1
31 LAN_MDI1N 5 MDIN1

2
27 LAN_LED0# 31
6
LED0
26 10M(Green)
31 LAN_MDI2P MDIP2 LED1/GPO LAN_LED1# 31 100M(Orange)
31 LAN_MDI2N 7 MDIN2 LED2 25 LAN_LED2# 31
LAN TX/RX (Yellow)
31 LAN_MDI3P 9 MDIP3
10 24 LAN_REGOUT
31 LAN_MDI3N MDIN3 REGOUT LAN_RSET
RSET 31

1
20,24,99 LAN_W AKE# 21 LANWAKE#
20 33 R3032
99 LAN_DISABLE# ISOLATE# GND
2K49R2F-GP
Layout: C3008: close to Pin32
* Place C3007 and C3008 close to each VDD33 pin-- 11, 32 C3007: close to Pin11 EV from SIO RTL8111HSD-CGT-1-GP

2
071.8111H.M001

3D3V_LAN VDDREG
C C
40 mils 1 R3006 2 0R0603-PAD-2-GP-U
C3011
LANXOUT 1 2
C3013 C3020
1

C3007 C3008 RTL8111HSD-CGT

SC15P50V2JN-2-GP
1

3D3V_LAN
SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SC4D7U6D3V3KX-GP

SCD1U16V2KX-3GP
2

071.8111H.M001
2

C3004 C3005

3
X3001

1
XTAL-25MHZ-181-GP SWR mode
DY DY

2
SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP
10/100/1000M

2
82.30020.G71
2nd = 82.30020.D41
Layout:
C3004: close to Pin11
3D3V_S0 C3001 C3005: close to Pin32
LANXIN 1 2

SC15P50V2JN-2-GP
1

3D3V_S5 3D3V_LAN rise time must be controlled

R3014 between 0.5 mS and 100 mS.
R3033 1KR2J-1-GP
2 1 LAN_W AKE#
DY
2

10KR2J-3-GP
B LAN_DISABLE# B
Pull high at SIO side
1

R3015
DY 15KR2J-1-GP
2

3D3V_LAN
C3017
SCD1U16V2KX-3GP
1

If use Intel LAN

need add pull high resistance
2

U3003
LAN_LED0#
EV
1 A VCC 5
R3001 1 2 LAN_RST#_R
LAN_LED1# 2 17 PLTRST_LAN#
B 0R0402-PAD-2-GP
A 3 4 <Core Design> A
GND Y W LAN_LAN_DISBL# 99

U74LVC1G08G-AL5-R-GP-U
73.01G08.EHG
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
2ND = 73.7SZ08.DAH Taipei Hsien 221, Taiwan, R.O.C.

Title

LAN
Size Document Number Rev
A3
Round Rock MLK 13.3" A00
Date: Monday, August 17, 2015 Sheet 30 of 110
5 4 3 2 1
 A B C D E

SSID = LOM

EV
4 Q3101 4

4 3 LOM_GRN#
30 LAN_LED0#
MASK_BASE_LEDS# 5 2 MASK_BASE_LEDS#
EU3101
LOM_ORG# 6 1
LAN_MDI0P 1 10 LAN_MDI0P 3D3V_LAN
LAN_MDI0N IN1 NC#10 LAN_MDI0N
2 IN2 NC#9 9 2N7002KDW -GP
3 GND GND 8
LAN_MDI1P
LAN_MDI1N
4 IN3 DY NC#7 7 LAN_MDI1P
LAN_MDI1N
84.2N702.A3F
5 IN4 NC#6 6 2nd = 84.DMN66.03F
30 LAN_LED1#
TVW DF1004AD0-1-GP
75.01004.073
RJ45
EU3102 10M(Green) 10 CHASSIS#10
LOM_GRN# R3101 1 2 510R2J-1-GP LOM_GRN#_R A1
100M(Orange) A3
GREEN_LED
LAN_MDI2P 1 10 LAN_MDI2P 3D3V
LAN_MDI2N 2
IN1 NC#10
9 LAN_MDI2N 1000M(Green+Orange) LOM_ORG# R3106 1 2 510R2J-1-GP LOM_ORG#_R A2 ORANGE_LED
IN2 NC#9 MDO3- 8
3 8 MDO3-
LAN_MDI3P 4
GND DY GND 7 LAN_MDI3P
MDO3+
MDO1-
7 MDO3+
LAN_MDI3N IN3 NC#7 LAN_MDI3N 6
5 6 MDO2- MDO1-
IN4 NC#6 5
MDO2+ MDO2-
4 MDO2+
MDO1+ 3
TVW DF1004AD0-1-GP LAN TX/RX (Yellow) Q3102 MDO0- 2
MDO1+
3 MDO0- 3
75.01004.073 S MDO0+ 1
30 LAN_LED2# MDO0+
B1 3D3V
D LOM_ACTLED_YEL#_R R3102 1 2 510R2J-1-GP NB_LOM_ACTLED_YEL#_R B2
AFTP3101 YELLOW_LED
1 9 CHASSIS#9
61 MASK_BASE_LEDS# G
RJ45-13P-33-GP
EV EMC 2N7002K-2-GP 022.10001.0E21
84.2N702.J31 Follow Plano 2nd = 022.10001.00K1
2ND = 84.2N702.031
3rd = 84.2N702.W31 EV ME

XF3101
MCT3
30 LAN_MDI3N 2 23 MDO3- MCT2
MCT1
1 24 MCT0 MCT0

30 LAN_MDI3P 3 22 MDO3+
1CT:1CT
30 LAN_MDI2N 5 20 MDO2-
MDO3- 1 AFTP3102
2 MDO3+ AFTP3103 2

4
3
2
1
MCT1 1
4 21 MDO2- AFTP3104
RN3101 1
MDO2+ 1 AFTP3105
30 LAN_MDI2P 6 19 MDO2+ SRN75J-1-GP MDO1- 1 AFTP3106
1CT:1CT MDO1+ AFTP3107
MDO1- 1
30 LAN_MDI1N 8 17 MDO0- AFTP3108
1
MDO0+ AFTP3109

5
6
7
8
MCT2 1
7 18 LOM_GRN#_R AFTP3110
1
NB_LOM_ACTLED_YEL#_R 1 AFTP3111

MCT
30 LAN_MDI1P 9 16 MDO1+
3D3V_LAN 1 AFTP3112
1CT:1CT LOM_ORG#_R AFTP3113
MDO0- 1
30 LAN_MDI0N 11 14

1
10 15 MCT3
C3101
12 13 MDO0+ SC56P3KV8JN-GP
30 LAN_MDI0P

2
1CT:1CT
078.5603N.0141
XFORM-24P-101-GP
068.IH219.3001
2nd = 068.89240.3001

Layout note: Follow Plano

LOM_TCT

30 mil spacing between MDI differential pairs. Layout note:

30 mil spacing between MDI differential pairs.

1 <Core Design> 1

Wistron Corporation
1

C3102 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

SCD01U50V2KX-1GP Taipei Hsien 221, Taiwan, R.O.C.
2

Title
RJ45/Transformer
Follow Reference Schematic 0.01uF~0.4uF Size Document Number Rev
A3
A00
Round Rock MLK 13.3"
Date: Monday, August 17, 2015 Sheet 31 of 110
A B C D E
 5 4 3 2 1

SSID =Card Reader

EV for card reader 3D3V_S0_CARD

D
3D3V_S0 3D3V_S0_CARD D
R3201 1 2 PCIE_CARD_PLT_RST#
17,58,59 PLTRST_MMI# 0R0402-PAD-2-GP 1200 mA
R3206
1 2

0R0805-PAD-2-GP-U
R3217
1 2

0R0805-PAD-2-GP-U

3D3V_S0_CARD 3D3V_AUX_CARD
3D3V_S0_CARD 3D3V_AUX_CARD

R3202
1 2
0R0603-PAD-2-GP-U
SD_CLK
SC10U6D3V3MX-GP

SCD1U16V2KX-3GP

SC10U6D3V3MX-GP

SCD1U16V2KX-3GP
C3203

C3204
C3235

C3236
1

1
EC3201
SC6D8P50V2CN-GP DY
2

2
C C

Close to pin11 Close to pin27 SD_VDD2 SD_VDD1 U3201

1D2V_LDO 10 15 SD_D1_RCLK_M_R R3204 1 20R0402-PAD-2-GP

3D3V_S0_CARD AV12 SP1 SD_D0_RCLK_P_R R3207 1 SD_D1_RCLK_M 33
11 3V3_IN SP2 16 20R0402-PAD-2-GP SD_D0_RCLK_P 33
12 17 SD_CLK_R R3209 1 20R0402-PAD-2-GP 3D3V_AUX_CARD
1D2V_LDO CARD_3V3 SP3 SD_CMD_R R3210 1 SD_CLK 33
13 SD_VDD2 SP4 19 20R0402-PAD-2-GP SD_CMD 33
1D2V_LDO 14 20 SD_D3_R R3211 1 20R0402-PAD-2-GP
SC1U10V2KX-1GP 2 DV12S SP5 SD_D3 33
1 C3202 DV33_18 18 DV33_18 SP6 21 SD_D2_R R3213 1 20R0402-PAD-2-GP SD_D2 33
3D3V_AUX_CARD 27 29 SD_W PI
3V3AUX SP7

2
SD_CD# 30 SD_CD# 33
Layout Note: 16 PCIE_TXP2 3 HSIP MS_INS# 31 R3205
16 PCIE_TXN2 4 HSIN 10KR2J-3-GP
SCD1U16V2KX-3GP 1 PCIE_CARD_PLT_RST#
PERST#
1 C3230 PCIE_RXP2_C
1

C3227 C3226 C3231 16 PCIE_RXP2 2 7 2 MMICLK_REQ# 18,20

1
HSOP CLK_REQ#
16 PCIE_RXN2 2 1 C3229 PCIE_RXN2_C 8 HSON WAKE# 32 DEV_W AKE# 1 2 MEDIACARD_IRQ# 20
R3212 0R0402-PAD-2-GP MEDIACARD_IRQ#
SC4D7U6D3V2MX-GP-U

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
CARD_RREF
2

18 CLK_PCIE_CARD 5 REFCLKP RREF 9

SCD1U16V2KX-3GP

6 24 CARD_SDREG2
18 CLK_PCIE_CARD# REFCLKN SDREG2
R3203
33 SD_D0P 26 28 CARD_GPIO 1 2 3D3V_AUX_CARD
SD_LN0_P GPIO
33 SD_D0N 25 SD_LN0_M 10KR2J-3-GP
For UHS-II

1
33 SD_D1P 22 SD_LN1_P

1
33 SD_D1N 23 SD_LN1_M GND 33 C3205 R3208
6K2R2F-GP

SC1U10V2KX-1GP
RTS5242-GR-GP-U

2
B 071.05242.0003 B

Close to pin14 Close to pin10

1 2
R3214 DY 0R2J-2-GP

Q3201
S SD_W PI_Q 33
SD_W PI D

G HOST_SD_W P# 20

2N7002K-2-GP
84.2N702.J31
2ND = 84.2N702.031
3rd = 84.2N702.W31
EV reseve for SD read only mode

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
Card Reader
Size Document Number Rev
A3
Round Rock MLK 13.3" A00
Date: Monday, August 17, 2015 Sheet 32 of 110
5 4 3 2 1
 5 4 3 2 1

SSID =Card Reader

SD_VDD1

D D
SCD1U16V2KX-3GP
C3302

C3304
SC4D7U6D3V3KX-GP
1

SD 4.0 Card Connector

2

SD_VDD2 SD_VDD1

CARD1

4 VDD/VDD1 D0+ 11 SD_D0P 32

D0- 12 SD_D0N 32
14 VDD2
D1+ 16 SD_D1P 32
R3301 15 SD_D1N 32
SD_CLK_C D1-
32 SD_CLK 1 2 5 CLK
0R0402-PAD-2-GP 7 SD_D0_RCLK_P 32
DAT0/RCLK+
32 SD_CMD 2 CMD DAT1/RCLK- 8 SD_D1_RCLK_M 32
9 SD_D2 32 SD_CD# 1 AFTP3301
DAT2 SD_D3 AFTP3302
Layout Note:Close to Card Reader CONN

1
CD/DAT3 1 SD_D3 32 1
EC3314 FG1 SD_CLK_C 1 AFTP3303
SC6D8P50V2CN-GP DY FG2
FG1
CD SD_CD# 32 SD_CMD 1 AFTP3304
FG2 CARD_DETECT SD_D0_RCLK_P AFTP3305

2
FG3 FG3 WRITE_PROTECT WP SD_W PI_Q 32 1
FG4 SD_D1_RCLK_M 1 AFTP3306
FG4
FG5 FG5
EV SD_D2 1 AFTP3307
FG6 3 SD_W PI_Q 1 AFTP3308
SD_VDD2 FG6 VSS1 SD_VDD1 AFTP3309
FG7 FG7 VSS2 6 1
C 10 SD_D0P 1 AFTP3311 C
VSS3 SD_D0N AFTP3312
NP1 NP1 VSS4 13 1
NP2 17 SD_D1P 1 AFTP3313
NP2 VSS5
SCD1U16V2KX-3GP

SD_D1N 1 AFTP3310
C3306

C3307
SC4D7U6D3V3KX-GP
1

SKT-SDCARD-44-GP-U
62.10051.I01
2nd = 062.10002.0051
2

EV ME

B B

SD_D3
SD_CMD
SD_D2

SD_D1_RCLK_M
SD_D0_RCLK_P
SD_D1N
SD_D1P
SD_D0N
SD_D0P
SC6D8P50V2CN-GP

SC6D8P50V2CN-GP

SC6D8P50V2CN-GP

SC6D8P50V2CN-GP

SC6D8P50V2CN-GP

SC6D8P50V2CN-GP
EC3304

EC3305

EC3306

EC3309

EC3310

EC3311
2

1
SC6D8P50V2CN-GP
EC3303

SC6D8P50V2CN-GP
EC3307

SC6D8P50V2CN-GP
EC3308
A DY DY DY DY DY DY DY DY DY <Core Design> A
1

2
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
Card Reader CONN
Size Document Number Rev
A3
Round Rock MLK 13.3" A00
Date: Tuesday, August 18, 2015 Sheet 33 of 110
5 4 3 2 1
 5 4 3 2 1

SSID = USB
U3401

USB30_TXDP1_C 1 10 USB30_TXDP1_C
C3401 1 2 SCD1U16V2KX-3GP USB30_TXDP1_R R3401 1 2 0R0402-PAD-2-GP USB30_TXDP1_C USB30_TXDN1_C LINE_1 NC#10 USB30_TXDN1_C
16 USB3_TX1_P 2 9
LINE_2 NC#9
3 8
USB30_RXDP1_C GND GND USB30_RXDP1_C
4 7
USB30_RXDN1_C LINE_3 NC#7 USB30_RXDN1_C
5 6
LINE_4 NC#6

AZ1045-04F-R7G-GP EXT Port2 Right Side

75.01045.073
2nd = 075.00550.0071 EV EMC USB30_VCCA
USB2
X02 1 10
VBUS CHASSIS#10
D 11 D
USB20_DN1_C CHASSIS#11
2 12
USB20_DP1_C D- CHASSIS#12
3 13
U3402 D+ CHASSIS#13
USB20_DN1_C 1 6 USB20_DP1_C
USB30_VCCA
C3402 1 2 SCD1U16V2KX-3GP USB30_TXDN1_R R3402 1 2 0R0402-PAD-2-GP USB30_TXDN1_C USB30_RXDN1_C 5
16 USB3_TX1_N USB30_RXDP1_C SSRX-
6
SSRX+
4
USB30_TXDN1_C PGND
8
USB30_TXDP1_C SSTX- AFTP3402
2 5 9 7 1
SSTX+ GND
USB3.0

2
SKT-USB13-179-GP
C3405
022.10005.0831
SCD1U16V2KX-3GP

1
3 4
2nd = 022.10005.00A1
AOZ8902CIL-1-GP
EV ME
USB3_RX1_P R3403 1 2 0R0402-PAD-2-GP USB30_RXDP1_C
75.08902.07C X02
16 USB3_RX1_P 2nd = 075.01256.007C

TR3403
X02 16 USB_PN1 1 4 USB20_DN1_C

2 3 USB20_DP1_C USB30_VCCA 1 AFTP3401

16 USB_PP1
USB30_TXDP1_C 1 AFTP3403
FILTER-4P-156-GP-U USB30_TXDN1_C 1 AFTP3404
068.24900.2001 USB20_DN1_C 1 AFTP3405
USB3_RX1_N R3405 1 2 0R0402-PAD-2-GP USB30_RXDN1_C 2ND = 68.11900.201 USB20_DP1_C 1 AFTP3406
16 USB3_RX1_N
USB30_RXDP1_C 1 AFTP3407
USB30_RXDN1_C 1 AFTP3408
X02
C C

U3403

USB30_TXDP0_C 1 10 USB30_TXDP0_C
USB30_TXDN0_C LINE_1 NC#10 USB30_TXDN0_C
2 9
LINE_2 NC#9
3 8
C3403 1 2 SCD1U16V2KX-3GP USB30_TXDP0_R R3407 1 2 0R0402-PAD-2-GP USB30_TXDP0_C USB30_RXDP0_C GND GND USB30_RXDP0_C
16 USB3_TX0_P 4 7
USB30_RXDN0_C LINE_3 NC#7 USB30_RXDN0_C
5 6
LINE_4 NC#6

AZ1045-04F-R7G-GP
75.01045.073
2nd = 075.00550.0071 EV EMC
USB30_VCCB EXT Port1 Lef Side, Support Power Share
X02
USB1

U3404 1 10
VBUS 10
USB20_DN0_C USB20_DP0_C 11
B 1 6 USB30_VCCB 11 B
12
USB20_DN0_C 12
2 13
D- 13
C3404 1 2 SCD1U16V2KX-3GP USB30_TXDN0_R R3408 1 2 0R0402-PAD-2-GP USB30_TXDN0_C USB20_DP0_C 3
16 USB3_TX0_N D+
USB30_RXDN0_C 5
2 5 USB30_RXDP0_C STDA_SSRX- AFTP3409
6 7 1
USB30_TXDN0_C STDA_SSRX+ GND_DRAIN
8

2
USB30_TXDP0_C STDA_SSTX-
9 4
C3406 STDA_SSTX+ GND
SCD1U16V2KX-3GP

1
3 4 SKT-USB13-26-GP-U1
AOZ8902CIL-1-GP 22.10339.791
2nd = 22.10339.C41
75.08902.07C X02
2nd = 075.01256.007C
EV ME

USB30_VCCB 1 AFTP3410
USB20_DN0_C 1 AFTP3411
16 USB3_RX0_P R3409 1 2 0R0402-PAD-2-GP USB30_RXDP0_C USB20_DP0_C 1 AFTP3412
USB30_TXDN0_C 1 AFTP3413
USB30_TXDP0_C 1 AFTP3414
USB30_RXDN0_C 1 AFTP3415
USB30_RXDP0_C 1 AFTP3416

TR3405
1 4 USB20_DN0_C
35 USB_PN0_R
2 3 USB20_DP0_C
35 USB_PP0_R
X02
FILTER-4P-156-GP-U
068.24900.2001
2ND = 68.11900.201

X02
A A
16 USB3_RX0_N R3412 1 2 0R0402-PAD-2-GP USB30_RXDN0_C

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

USB 3.0 Port

Size Document Number Rev
A2
Round Rock MLK 13.3" A00
Date: Monday, August 17, 2015 Sheet 34 of 110
5 4 3 2 1
 5 4 3 2 1

SSID = USB
5V_S5

EV follow Houston
5V_S5
USB3.0 Port1
1
USB_OC#0_1 16 USB30_VCCB
R3505
10KR2J-3-GP
D D
2

C3505
SCD1U16V2KX-3GP

C3506
SC1U10V2KX-1GP

C3508
SC100U6D3V6MX-GP
TC3502

1
C3507

1
ST150U6D3VBM-9-GP
ILIM_SEL SCD1U25V2KX-GP
DY 80.15715.D2L

2
2nd = 77.21571.15L

2
13

12
1

9
U3502

NC#9
FAULT#
IN

OUT
99 USBPW RSHR_VBUS_EN 5 EN DP_OUT 3 USB_PP0 16
DM_OUT 2 USB_PN0 16
ILIM_SEL 4 ILIM_SEL
15 ILIM_LO DP_IN 10 USB_PP0_R 34
ILIM_HI 16 11 USB_PN0_R 34
PERICOM 2.275 A ILIM_HI DM_IN

CTL1
CTL2
CTL3

GND
GND
R3501
Imax SILEGO 2.275 A 22K1R2F-L-GP
22.1k ohm PI5USB2544ZHEX-GP

6
7
8

14
17
074.52544.0093
2

TI 2.275 A
2nd = 074.55544.0073
3rd = 74.02544.073
24 USBPOW ERSHARE_EN#

C C

USB3.0 Port2
USB30_VCCA

5V_S5 Low Active USB30_VCCA

C3502
SCD1U16V2KX-3GP

C3503
SC1U10V2KX-1GP

C3509
SC100U6D3V6MX-GP
U3501 TC3501

1
ST150U6D3VBM-9-GP
1 GND OUT#8 8 EV follow Houston DY 80.15715.D2L
2 7 2nd = 77.21571.15L

2
IN#2 OUT#7
1

C3501 3 6
SC1U10V2KX-1GP IN#3 OUT#6
4 EN/EN# OCB 5 USB_OC#2_3 16
2

SY6288DCAC-GP
74.06288.A79
99 USB_SIDE_EN#
2nd = 74.02301.079
3rd = 074.07549.0079

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

USB3.0 Power SW
Size Document Number Rev
Round Rock MLK 13.3" A00
Date: Monday, August 17, 2015 Sheet 35 of 110
5 4 3 2 1
 5 4 3 2 1

3D3V_AUX_S5
SSID = Reset.Suspend 5V_S5 1D05V_S0 2327 mA

1
15V_S5 1D05V_M 1D05V_S0
5V_S0/3D3V_S0 R3638

Power Sequence 5V_S5 100KR2J-1-GP

U3614

1
C3637 3169.5 mA 8 D S 1

SIO_SLP_S3 2
SC10U6D3V3MX-GP U3601 7 D S 2
5V_S0 6 D S 3

2
GND 15 R3639 5 D G 4
1 14 100KR2J-1-GP

2
VIN1#1 VOUT1#14

C3603
SC10U6D3V3MX-GP

SC10U6D3V3MX-GP
C3618

C3617
SCD1U16V2KX-3GP
2 13 2611 mA TPCA8062-H-GP
VIN1#2 VOUT1#13

1
R3603 1 2 RUN_ON_R 3 12 5V_S0_CT 1 2 SIO_SLP_S3#_Q_R 84.08062.037
17,24,49 SIO_SLP_S3# 0R0402-PAD-2-GP ON1 CT1 3D3V_S0
4 VBIAS GND 11 2nd = 84.00460.037

1
R3607 1 DY 2 0R2J-2-GP 5 10 3D3V_S0_CT R3640 C3629 TPCA8062 ID= 28A

2
24,49 RUN_ON ON2 CT2

4
R3601 1 2 0R0402-PAD-2-GP 6 9 10KR2J-3-GP
45 3V_5V_EN ALWON 24 VIN2#6 VOUT2#9 Rds(on) = 5.4~4.1m Ohm

C3605
SC10U6D3V3MX-GP

SCD01U50V2KX-1GP
3D3V_S5 7 8 Q3619

2
VIN2#7 VOUT2#8

1
C3601
SC1KP50V2KX-1GP

C3604
SC470P50V2KX-3GP
1 2N7002KDW-GP

1
84.2N702.A3F
R3605 TPS22966DPUR-GP 2nd = 84.DMN66.03F
DY

3
1
200KR2J-L1-GP C3638 74.22966.093

2
SC10U6D3V3MX-GP 2nd = 074.05016.0093
D 3rd = 074.22966.0093 D
2

2
CT Pin: Use 16V+ cap. SIO_SLP_S3#_Q

R3637 1 2 SIO_SLP_S3#_R
17,24,49 SIO_SLP_S3# 0R0402-PAD-2-GP

24,49 RUN_ON
R3612 1 DY 2 0R2J-2-GP 1D05V_MODPHY 1963 mA
3D3V_S5 15,24 ENVDD_PCH 3D3V_AUX_S5 15V_S5 1D05V_MODPHY

3D3V_S5
3D3V_LAN/LCDCDD POWER LCDVDD 1D05V_M
200 mA

1
U3611
1

1
R3626 R3651 8 D S 1
R3614 1 2 100KR2J-1-GP DY DY D S

MPHYP_PWR_EN#
7 2

C3607
SC10U6D3V3MX-GP
100KR2J-1-GP 3 LCDPWR_EN C3634 6 D DY S 3

1
SC10U6D3V3MX-GP POLYSW-1D5A6V-12-GP R3608 5 D G 4
D3601

2
1
47KR2J-2-GP 069.50001.0031 100KR2J-1-GP
LBAT54CLT1G-GP
RUN_ON# 2

2
1D05V_S0 1D05V_MODPHY

C3611
SC10U6D3V3MX-GP

C3615
SCD1U16V2KX-3GP
R3606 U3602 2ND = 069.50001.0071 TPCA8062-H-GP
R3654

2
83.R2003.V81

1
DY 1 2 1 DY 2 MPHYP_PWR_EN_Q_R 84.08062.037
2nd = 75.00054.E7D 5V_S5 15 0R0805-PAD-2-GP-U 2nd = 84.00460.037 DY DY
GND

1
3D3V_S0 1 14 LCDVDD_OUT R3615 C3609
24 LCD_VCC_TEST_EN

2
3rd = 75.00054.A7D VIN1#1 VOUT1#14
2
VIN1#2 VOUT1#13
13 156.6 mA R3656
10KR2J-3-GP DY TPCA8062 ID= 28A

SCD01U50V2KX-1GP
3 12 LCDVDD_CT 1 2
Rds(on) = 5.4~4.1m Ohm

2
ON1 CT1

4
4 11 3D3V_LAN 0R0805-PAD-2-GP-U
VBIAS GND
6

R3604 1 2 LANPWR_EN 5 10 3D3V_LAN_CT Q3617

Q3601 24 LANPWR_EN_EC 0R0402-PAD-2-GP ON2 CT2 2N7002KDW-GP
6 VIN2#6 VOUT2#9 9 DY

C3608
SC10U6D3V3MX-GP
2N7002KDW-GP 3D3V_S5 7 8 84.2N702.A3F
VIN2#7 VOUT2#8
1

1
C3635
SC470P50V2KX-3GP

C3606
SC470P50V2KX-3GP
84.2N702.A3F EV assign from EC 2nd = 84.DMN66.03F

3
1

1
2nd = 84.DMN66.03F R3618 C3636
1

10KR2J-3-GP SC10U6D3V3MX-GP TPS22966DPUR-GP

2
74.22966.093

2
2nd = 074.05016.0093
2

3rd = 074.22966.0093
CT Pin: Use 16V+ cap. 20 MPHYP_PWR_EN 1 DY 2 MPHYP_PWR_EN_R MPHYP_PWR_EN_Q
R3644 0R2J-2-GP
Q3601_2

RUNPWROK 24
3D3V_AUX_S5
15V_S5 3D3V_S5_PCH
R3610 1 2 73 mA
17,24,49 SIO_SLP_S3# 0R0402-PAD-2-GP

1
3D3V_AUX_S5 3D3V_S5 3D3V_S5 3D3V_S5_PCH
R3652
R3609 1 DY 2 0R2J-2-GP 100KR2J-1-GP
24,49 RUN_ON

1
3D3V_S5 R3641 U3615
R3620 100KR2J-1-GP 1 D D 6

PCH_ALW_ON#
2

2
C3619 +V1.05S_VCCST 100KR2J-1-GP 2 D D 5
15V_S5 3D3V_M
SCD1U16V2KX-3GP

1 2 PCH_ALW_ON_Q_R 3 G S 4

2
1

1
94 mA R3642 C3632 AO6402A-GP

SC10U6D3V3MX-GP
C3631

C3630
SCD1U16V2KX-3GP
C 10KR2J-3-GP C

SIO_SLP_A
84.06402.B3D
1

1
3D3V_S5 3D3V_S5 3D3V_M

SCD01U50V2KX-1GP
2ND = 84.P2703.03D
2

2
U3606 R3621 3rd = 84.03456.D3D
1 5 1KR2J-1-GP R3635 AO6402A MAX 7A

2
NC#1 VCC

4
R3616 U3613
RESET_OUT# 2 100KR2J-1-GP 1 D D 6 1 DY 2 Q3620 Rds(on) = 27~40m Ohm
17,24 RESET_OUT#
2

2
A 0R3J-0-U-GP 2N7002KDW-GP
2 D D 5

4
3 4 H_VCCST_PWRGD 7,96 1 2SIO_SLP_A#_Q_R 3 G S 4 84.2N702.A3F
GND Y Q3618 2nd = 84.DMN66.03F

3
1
2N7002KDW-GP R3617 C3628 AO6402A-GP

C3627
SC10U6D3V3MX-GP

C3626
SCD1U16V2KX-3GP
74AUC1G07DCKR-GP 84.2N702.A3F 10KR2J-3-GP 84.06402.B3D

1
SCD01U50V2KX-1GP
73.01G07.02H 2nd = 84.DMN66.03F 2ND = 84.P2703.03D

2
2ND = 73.01G07.AHG 3rd = 84.03456.D3D
AO6402A MAX 7A

2
SIO_SLP_A#_R
PCH_ALW_ON_Q
SIO_SLP_A#_Q Rds(on) = 27~40m Ohm R3611 1 2 PCH_ALW_ON_R
24 PCH_ALW_ON 0R0402-PAD-2-GP

17,24,48 SIO_SLP_A# R3619 1 2

0R0402-PAD-2-GP
R3624 1 DY 2 0R2J-2-GP
24,48 A_ON

1D35V_S3

1
R3648
1KR2J-1-GP
3D3V_M 5V_S0 1D05V_S0
1D05V_MODPHY 3D3V_S0

2
RUN_ON#
1

1
0D675V_S0 3D3V_AUX_S5

1D35V_S3_DISCHG
1

1
R3646
1KR2J-1-GP DY R3643
1KR2J-1-GP
R3645 R3650
R3649
1KR2J-1-GP
DY 1KR2J-1-GP 1KR2J-1-GP

1
R3647 R3653

+1.05V_RUN_CHG
+3.3V_ALWPCH 2

+5V_RUN_CHG 2

2
+1.5V_RUN_CHG

+3.3V_RUN_CHG

1KR2J-1-GP 100KR2J-1-GP
2

Q3609 Q3610 Q3611 Q3612 Q3613

2
B B
SIO_SLP_A G RUN_ON# G G G G

0D675V_S0_DISCHG
6

4
R3613 1 DY 2 0R2J-2-GP SUS_ON 24,49
Q3615
D D D D D Q3614
DY DY 2N7002KDW-GP G Q3615_G R3655 1 2 SIO_SLP_S4# 17,24,49
S S S S S 84.2N702.A3F 0R0402-PAD-2-GP
2nd = 84.DMN66.03F D

3
2N7002K-2-GP 2N7002K-2-GP 2N7002K-2-GP 2N7002K-2-GP 2N7002K-2-GP
S
84.2N702.J31 84.2N702.J31 84.2N702.J31 84.2N702.J31 84.2N702.J31
2ND = 84.2N702.031 2ND = 84.2N702.031 2ND = 84.2N702.031 2ND = 84.2N702.031 2ND = 84.2N702.031 SIO_SLP_S4
2N7002K-2-GP
3rd = 84.2N702.W31 3rd = 84.2N702.W31 3rd = 84.2N702.W31 3rd = 84.2N702.W31 3rd = 84.2N702.W31 84.2N702.J31
2ND = 84.2N702.031
3rd = 84.2N702.W31

Intel Power Sequence

+V1.05S_VCCST
EV follow PDG 2.0
7,46 H_VR_ENABLE
1

R3622 R3623
1K5R2J-3-GP DY 10KR2J-3-GP
2

R3625

7 H_VR_READY 1 2 IMVP_PWRGD 46
0R0402-PAD-2-GP 3D3V_AUX_S5

C3620 D3602
1

SCD1U16V2KX-3GP

K A
DY DY

1
C3622
2

RB751V-40H-GP SCD1U16V2KX-3GP
83.R2004.G8F U3609

2
2nd = 83.R2004.C8F 17,24,48 SIO_SLP_A# SIO_SLP_A# 1 5
R3657 A VCC
A 24 PM_APWROK 1 2 PWR_1D05_PGOOD_R 2 A
0R0402-PAD-2-GP B
R3658 3 4 APWROK 17
GND Y
48 PWR_1D05_PGOOD 1 DY 2
0R2J-2-GP U74LVC1G08G-AL5-R-GP-U

1
73.01G08.EHG R3633
2ND = 73.7SZ08.DAH 10KR2J-3-GP

R3634 1 DY 2 0R2J-2-GP <Core Design>

2
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Power Plane Enable

Size Document Number Rev
Custom A00
Round Rock MLK 13.3"
Date: Monday, August 17, 2015 Sheet 36 of 110
5 4 3 2 1
 5 4 3 2 1

SSID = Reset.Suspend

D D

C C

(Blanking)

B B

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

(Reserved)
Size Document Number Rev
A4 A00
Round Rock MLK 13.3"
Date: Monday, August 17, 2015 Sheet 37 of 110
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

<Variant Name>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
Reserved
Size Document Number Rev
A4
Round Rock MLK 13.3"A00
Date: Monday, August 17, 2015 Sheet 38 of 110
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
A Taipei Hsien 221, Taiwan, R.O.C. A

Title

Reserved
Size Document Number Rev
A
Round Rock MLK 13.3" A00
Date: Monday, August 17, 2015 Sheet 39 of 110
5 4 3 2 1
 5 4 3 2 1

SSID = OBFF

D D

C C

(Blanking)

B B

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A4
Round Rock MLK 13.3" A00
Date: Monday, August 17, 2015 Sheet 40 of 110
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
A Taipei Hsien 221, Taiwan, R.O.C. A

Title

Reserved
Size Document Number Rev
A
Round Rock MLK 13.3" A00
Date: Monday, August 17, 2015 Sheet 41 of 110
5 4 3 2 1
 5 4 3 2 1

SSID = PWR.Support 5V_S5

0103 Add EC4203 3D3V_S5

ndde close to EL4202

2
84.T3904.H11

1
PR4202
15KR2F-GP
2nd = 84.T3904.K11 PR4203

E
3rd = 84.03904.E11 10KR2J-3-GP
EV remove

1
PQ3802_1 B PQ4202 3D3V_S5
LMBT3904LT1G-GP PD4203

2
2
D
Layout Note: LBAV99LT1G-1-GP D

1
PR4211 PSID_DISABLE#_R_C 75.00099.O7D
PSID Layout width > 25mil 100KR2J-1-GP 2nd = 75.00099.E7D PR4206
3rd = 75.00099.Q7D 2K2R2J-2-GP

3
G
1
JGND PQ4201

2
FDV301N-NL-GP
SCD1U50V5JX-1-GP PR4219 PR4207
EC4203 PS_ID_R 1 2 PS_ID_R2 D S PS_ID 1 2

D
PSID_EC 24
1 2
0R0603-PAD-2-GP-U 84.00301.A31 33R2J-2-GP
2nd = 84.3K329.031

1
EL4202
PD4204 PR4208
2 1 DY PESD24VS2UT-GP 1 2
DY
BCMS453215A800-9A-GP 33R2J-2-GP
68.00376.081

3
2nd = 68.00230.271
DCIN1
6
NP1 1 AFTP4204
1

2 1 AFTP4203
3
4 +DC_IN AD+

SC10U25V5KX-GP
EL4201
5 PU4201
C +DC_IN_C 1 S D C

PC4206
NP2 1 2 8
2 S D

PC4205
240KR3-GP
7 7

SC1U25V5KX-1GP

SCD01U50V2KX-1GP
1
SC10U25V5KX-GP

EC4202
SCD1U50V3KX-GP

BCMS453215A800-9A-GP S D
EC4201

PC4201

PR4209
3 6

K
1

1
ACES-CON5-27-GP-U 68.00376.081 D 5
2nd = 68.00230.271 PD4201 PC4202 G
20.F2182.005 1
PR4216 1SMB22AT3G-GP-U1 SCD1U50V3KX-GP
2

2
2nd = 20.F2198.005 AFTP4205 83.22R03.03G

2
DY 3K3R6J-GP 2nd = 83.P6SBM.CAG FDMC6675BZ-GP-U

A
EV ME 84.06675.030
2nd = 84.07121.037
2

PQ4205 3rd = 84.07403.037

1
R2
JGND JGND PQ4206_3 PQ4204 E Id=-9.6A
C AD_OFF_L B
B R1 R1 DY C AD_OFF_R Qg=-25nC
DY E PR4210 Rdson=18~30mohm
R2 PDTA124EU-1-GP 47KR3J-L-GP

2
PDTC124EU-1-GP R1=R2=22K
R1=R2=22K 84.00124.K1K
84.00124.H1K 2nd = 84.05124.A11
2nd = 84.05124.011 3rd = 84.00024.01K
3rd = 84.00024.A1K

PQ4206
S
B B

D
DY
G

2N7002K-2-GP
1 DY 2 PW R_CHG_AD_OFF_R
84.2N702.J31 PR4212
2ND = 84.2N702.031 1KR2J-1-GP
3rd = 84.2N702.W31
PR4220
1 2 AC_DIS#_R
24 AC_DIS_TEST DY
0R2J-2-GP

EV reverve for factory test, confirmed with SW there's no need to install

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

DCIN JACK
Size Document Number Rev
A3 A00
Round Rock MLK 13.3"
Date: Monday, August 17, 2015 Sheet 42 of 110
5 4 3 2 1
 A B C D E

SSID = PWR.Support

4 4

BT+
MAIN BATTERY CONNECTOR

PC4301
SCD1U50V3KX-GP

PC4302
SC2200P50V2KX-2GP

FC3409
SCD1U50V3KX-GP
1

1
2

2
BATT1
10
1

RN4301 2
1 8 PBAT_SMBCLK_R 3
24 PBAT_SMBCLK
2 7 PBAT_SMBDAT_R 4
24 PBAT_SMBDAT
24,44 PBAT_PRES# 3 6 PBAT_PRES#_R 5
4 5 6
3 1 BAT_ALERT 7 3
SRN100J-4-GP AFTP4318 8
AFTP4301 1 9
11

ALP-CON9-6-GP-U
20.81925.009
2nd = 20.81928.009

BT+ 1 AFTP4302
PBAT_SMBCLK_R 1 AFTP4303
PBAT_SMBDAT_R 1 AFTP4304
PBAT_PRES#_R 1 AFTP4305

Layout Note: Place near Battery CONN

2 PBAT_PRES# PBAT_SMBDAT PBAT_SMBCLK 2
3

PD4301 PD4302 PD4303

LBAV99LT1G-1-GP LBAV99LT1G-1-GP LBAV99LT1G-1-GP
75.00099.O7D 75.00099.O7D 75.00099.O7D
2nd = 75.00099.E7D 2nd = 75.00099.E7D 2nd = 75.00099.E7D
3rd = 75.00099.Q7D 3rd = 75.00099.Q7D 3rd = 75.00099.Q7D
1

3D3V_AUX_S5

<Variant Name>
1 1

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

BATTERY CONN
Size Document Number Rev
A3
Round Rock MLK 13.3" A00
Date: Monday, August 17, 2015 Sheet 43 of 110

A B C D E
 5 4 3 2 1

Main Func = Charger

AD+ +SDC_IN CHARGER_SRC

PR4426
PU4405
8 D S 1 1 2
7 D S 2 D01R3721F-GP-U
6 D S 3
5 D

1
G PG4406 PG4402
PR4435 GAP-CLOSE-PWR-3-GP GAP-CLOSE-PWR-3-GP

4
100KR2J-1-GP
FDMC6675BZ-GP-U

2
84.06675.030

2
2nd = 84.07121.037

1
D 3rd = 84.07403.037 PR4421 D
PR4418 AD+_G_2 0R2J-2-GP
3K3R6J-GP 2 DY 1

2
2
PR4423 1 PC4428

DC_IN_D
2
10KR2F-2-GP SCD1U25V2KX-GP

PQ4407

SCD1U25V2KX-GP
AD+_G_1

PC4418
SCD1U25V2KX-GP

PC4416
3 4

2
ACAV_OK 2 5
DY

1
1 6

1
BT+
2N7002KDW-GP
PD4405 A K 84.2N702.A3F BQ24770_AGND
SD103AWS-2-GP 83.2R004.08F 2nd = 84.DMN66.03F
AD+ 2nd = 83.1R004.G8F BQ24770_AGND
CHARGER_SRC
PD4406 A K PWR_CHG_1 1 2 PWR_CHG_VCC
PC4410
SD103AWS-2-GP 83.2R004.08F PR4403 10R5J-GP
SC1U25V3KX-1-GP

PC4413
2nd = 83.1R004.G8F
PU4406:

PC4427

PC4407
PC4433

PC4425

PC4411

PC4434
VacDET=2.4V AD+ SCD1U25V2KX-GP
PC4421

SCD1U25V2KX-GP
2
Acok setting=2.4*((PR4444+PR4411)/PR4411) PC4432 PWR_CHG_BTST1

1
1 2

PWR_CHG_ACP
2

PWR_CHG_ACN
2.4*((309+49.9)k/49.9k)=17.26172V
main source: 84.03660.037

SC1U25V3KX-1-GP

SC10U25V5KX-GP

SC10U25V5KX-GP

SC10U25V5KX-GP

SC10U25V5KX-GP

SC10U25V5KX-GP
Setting=17.26v

2
BQ24770_AGND SCD047U25V3KX-3-GP

2
DY 2nd = 075.06992.0073
1

BQ24770_AGND PR4425

2
PR4444
KBC FOR DT MODE 0R3J-0-U-GP

K
309KR2F-GP +SDC_IN PU4406
PD4401 FDMS3600-02-RJK0215-COLAY-GP
CHECK EE PULL HIGH

PWR_CHG_BTST 1
BQ24770_AGND SD103AWS-2-GP 2
2

1
3

1
PR4439 PU4404 83.2R004.08F 1 4

A
DCBATOUT
X02

SC10U25V5KX-GP

SC10U25V5KX-GP

SC10U25V5KX-GP

SC10U25V5KX-GP
4K02R2F-GP 2nd = 83.1R004.G8F 10

ACP
SCD01U50V2KX-1GP

ACN
3D3V_AUX_S5 28 9
PWR_CHG_REGN
1

VCC
DY 7
2

PC4403

PC4430

PC4408

PC4409
C PR4411 BQ24777RUYR-GP 8 6 C
49K9R2F-L-GP PWR_CHG_CMSRC 3 25 5 83.8R010.A87
2

CMSRC BTST

1
PC4402

X01
1

4
2

PR4432 PR4414 ACDRV PWR_CHG_REGN +VCHGR

24 1 2
ZZ.00215.037

2
3K3R2J-3-GP 3K3R2J-3-GP REGN PD4402 V8P10-5300M3-86A-GP
DY DY BQ24770_AGND PWR_CHG_ACDET 6
ACDET
PC4422 Change to 84.03660.037 PL4401 1

SC10U25V5KX-GP

SC10U25V5KX-GP
BQ24770_AGND SC2D2U25V3KX-GP
2

ACAV_IN 26 PWR_CHG_HIDRV 1 2 1 2 3
HIDRV

PC4440
ACAV_OK 2 1 PWR_CHG_ACOK 5 IND-2D2UH-158-GP-U PR4443
H=ACIN ACOK

PR4427

2D2R5F-2-GP

PC4439

PC4415
PR4430 0R0402-PAD-2-GP 68.2R21C.10Q D01R2512F-3-GP 2

PC4441
SC10U25V5KX-GP
1
L=UNAC BT+

PC4420
PG4401 27 PWR_CHG_PHASE 2nd = 68.2R210.20R

SC1U25V3KX-1-GP
PHASE

1
PWR_SCL

1
24 CHARGER_SMBCLK 2 1 12
SCL 3rd = 68.2R21B.10I
DY PC4442 DY

2
GAP-CLOSE-PWR-3-GP

GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP PG4408 23 PWR_CHG_LODRV
SC10U25V5KX-GP

2
LODRV

PG4407

PG4403
PWR_SDA

2
24 CHARGER_SMBDAT 2 1 11 PU4403

2
SDA S D
1 8

SC10U25V5KX-GP
22 DCBATOUT_SNUB 2 S D 7 PC4424
GAP-CLOSE-PWR-3-GP

1
PR4466 BQ24770_IADP GND S D
2 1 7 3 6

SC330P50V3KX-GP
24 I_ADP 0R0402-PAD-2-GP IADP D
Discharge Current Monitor 5

SCD01U50V2KX-1GP
PR4434 BQ24770_IDCHG G

PC4406
24 I_BATT
2 1 8
IDCHG PWR_CHG_SRP
DY
0R0402-PAD-2-GP 20 PR4438 1 2 0R0402-PAD-2-GP PWR_CHG_SRP_R DY

4
PR4467 BQ24770_PMON SRP
2 1 9

2
24 I_SYS 0R0402-PAD-2-GP PMON FDMC6675BZ-GP-U
SC100P50V2JN-3GP
PC4435

SC100P50V2JN-3GP
PC4436

System Power Monitor

PR4469 PWR_CHG_SRN PR4417 1 2 0R0402-PAD-2-GP PC4429 BATDRV# 84.06675.030
1

19
PR4476 PROCHOT#_BQ24770 SRN
1 2 10 1 2 2nd = 84.07121.037
1

PROCHOT# PWR_CHG_BAT
These pins can be floating 20KR2F-L-GP 0R0402-PAD-2-GP
BAT
17 2 1 BT+ 3rd = 84.07403.037

1
if they are not in use. PC4401 SCD1U25V2KX-GP PC4412
15 PBAT_PRES# 24,43 PR4408 SCD1U25V2KX-GP SCD1U25V2KX-GP
IADP=40*V(acp_acn) or 80*V(acp_acn)
2

BQ24777_CMPIN BATPRES# 20R3F-L-GP

2

13

2
IDCHG=8*V(srn-srp) or 16*V(srn-srp) CMPIN PWR_CHG_BATDRV BATDRV#

1
18 1 2 PC4438
1

BATDRV#
14
CMPOUT

SC1U25V3KX-1-GP
PR4431 21 ILIM PR4409 BQ24770_AGND BQ24770_AGND
NC#21(IDOCK) PWR_CHG_SRN_R
1KR2F-3-GP

2
0R0402-PAD-2-GP 16
GND

4,24,46 H_PROCHOT# CELL

2

PWR_CHG_REGN PWR_CHG_REGN
29

74.24777.073

BQ24770_AGND
1

1
B B
PR4449 PR4470
100KR2J-1-GP 100KR2J-1-GP
PR4406 0R0402-PAD-2-GP
1 2
2

2
CHARGER_CELL_PIN
BQ24770_AGND
1
PWR_CHG_REGN
DY PR4471
100KR2J-1-GP
1

PR4453
100KR2J-1-GP
1 2

PWR_CHG_REGN
PR4442
120KR2J-GP
1

PR4450
2

100KR2J-1-GP
PQ4414
PWR_CHG_REGN
2

4 3 ACAV_OK#

ACAV_OK
1

5 2
PR4454
100KR2J-1-GP 6 1

2N7002KDW-GP
1 2

84.2N702.A3F
2nd = 84.DMN66.03F
PR4445
120KR2J-GP
PQ4415
A G AC_DIS 24 A
2

D
24 ACAV_IN
S

2N7002K-2-GP <Core Design>

84.2N702.J31
2ND = 84.2N702.031
3rd = 84.2N702.W31 Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
For peak shifting (with learn mode)
Title
CHARGER
Size Document Number Rev
A2
Round Rock MLK 13.3" A00
Date: Monday, August 17, 2015 Sheet 44 of 110
5 4 3 2 1
 A B C D E

SSID = PWR.Plane.Regulator_5v3p3v
PWR_5V_VCLK

1
PC4525

1
DCBATOUT PWR_DCBATOUT_3D3V 3D3V_AUX_S5 DCBATOUT PWR_DCBATOUT_5V

1
SC1KP50V2KX-1GP PC4532
PC4526
PG4501 PG4502 SCD1U50V3KX-GP

2
SCD1U50V3KX-GP

2
1

BST15V_1

2
1 2 2 1

BST15V_2
PR4502
GAP-CLOSE-PWR-3-GP DY 0R2J-2-GP GAP-CLOSE-PWR-3-GP
PG4503 PG4504
1 2 2 1

2
PD4503
PR4503

3
GAP-CLOSE-PWR-3-GP PR4501 GAP-CLOSE-PWR-3-GP BAT54S-7-F-GP PD4502
PG4505 PWR_5V_EN1 2 1 PWR_5V_EN1_R 1 DY 2 PG4506 BAT54S-7-F-GP
4
0R0402-PAD-2-GP
75.00054.B7D 4
1 2 2 1 2nd = 75.00054.07D 75.00054.B7D
0R2J-2-GP 2nd = 75.00054.07D

1
GAP-CLOSE-PWR-3-GP GAP-CLOSE-PWR-3-GP
PG4507 PR4504 PG4508 5V_PWR 15V_S5

2
1 2 0R0402-PAD-2-GP 2 1 PG4530
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP GAP-CLOSE-PWR-3-GP

2
PR4505 PG4509 BOOST_10V 15V_PWR
PWR_3D3V_EN2 2 2 1
1 2 1
0R0402-PAD-2-GP 3V_5V_EN 36
GAP-CLOSE-PWR-3-GP

K
1

1
1
PC4527 PC4534 PC4533
PG4510
SCD1U50V3KX-GP SCD1U50V3KX-GP SC1U25V3KX-1-GP PD4501
2 1
DYBZT52C15S-GP

2
2
GAP-CLOSE-PWR-3-GP

A
PWR_DCBATOUT_3D3V DCBATOUT
PWR_DCBATOUT_5V
PC4505 PC4506
PC4502 PC4503 PC4504

SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
PC4507 PC4508 PC4509
1

1
SC10U25V5KX-GP

SCD1U50V3KX-GP

SC10U25V5KX-GP

SCD1U50V3KX-GP
D D

SC10U25V5KX-GP

SC10U25V5KX-GP
Design Current=5.894 A PU4502 DY PU4503

5
6
7
8

1
FDMC8884-GP-U
8.841A<OCP>10.6A FDMC8884-GP-U
2

2
D 8
D 7
D 6
D 5

D
D
D
D
84.08884.A37 84.08884.A37 5V_PWR 5V_S5
2nd = 84.00412.037

2
2nd = 84.00412.037 3rd = 84.30707.037 PG4511
3rd = 84.30707.037 G

12
2 1
G PU4501

G
4

S
S
S
4 GAP-CLOSE-PWR-3-GP
G

VIN
PG4512
S
S
S

3
2
1
S 2 1
1
2
3

3D3V_S5 3D3V_PWR
3 PG4513
S 2
PC4510
1
PR4506
1PWR_3D3V_VBST2_1 2 PWR_3D3V_VBST29
TPS51275RUKR-1-GP-U
17 PWR_5V_VBST1 1
PR4507
2PWR_5V_VBST1_1 2 1
PC4511 Design Current=5.153 A
GAP-CLOSE-PWR-3-GP 3
2 1 SCD1U50V3KX-GP 1D5R3F-GP VBST2 VBST1 1D5R3F-GP 8.3A<OCP>9.2A PG4514
3D3V_PWR PL4501 PWR_3D3V_DRVH2 10 16 PWR_5V_DRVH1 SCD1U50V3KX-GP PL4502 5V_PWR 2 1
GAP-CLOSE-PWR-3-GP DRVH2 DRVH1
PG4515 1 2 PWR_3D3V_LL2 8 18 PWR_5V_LL1 1 2 GAP-CLOSE-PWR-3-GP
SW2 SW1 PG4516
2 1 IND-3D3UH-57-GP-U IND-4D7UH-88-GP-U
1

PWR_3D3V_DRVL2 PWR_5V_DRVL1
D 11
DRVL2 DRVL1
15 2 1

1
GAP-CLOSE-PWR-3-GP 68.3R310.20A D 68.4R710.20D
D 8
D 7
D 6
D 5

5
6
7
8
PG4519
2nd = 68.3R31A.10VDY 2nd = 68.4R71C.10K PG4521 GAP-CLOSE-PWR-3-GP

D
D
D
D

SCD1U16V2KX-3GP
PC4513

ST220U6D3VBM-3-GP
PT4502
PG4518 PR4508 PU4505 PWR_5V_VO1 PU4504 PR4509 PG4520
14 DY 2D2R5F-2-GP
PC4512
SCD1U16V2KX-3GP

VO1
1

1
2 1
ST220U6D3VBM-3-GP
PT4501

FDMC8878-GP

FDMC8878-GP

GAP-CLOSE-PWR-3-GP
2D2R5F-2-GP 2 1
2
1

GAP-CLOSE-PWR-3-GP

PWR_3D3V_FB2 4 2 PWR_5V_FB1
GAP-CLOSE-PWR-3-GP

2
VFB2 VFB1 GAP-CLOSE-PWR-3-GP
1PWR_3D3V_SNUB

PG4517

2
PG4522
2

2
2 1

G
S
S
S
2 1
1 S
2 S
3 S
4 G

1PWR_5V_SNUB
PWR_3D3V_EN2 PWR_5V_EN1
GAP-CLOSE-PWR-3-GP 6 20 G S

4
3
2
1
EN SKIPSEL
PG4523 S G GAP-CLOSE-PWR-3-GP
PG4524
2 1 PWR_3D3V_CS2 PWR_5V_CS1
5 1 2 1
CS2 CS1
77.C2271.45L
3V_FEEDBACK

GAP-CLOSE-PWR-3-GP
1

1
77.C2271.45L 2nd = 77.22271.33L GAP-CLOSE-PWR-3-GP
PG4529
PR4510 PWR_5V_VCLK R9952 PG4525
2 1 2nd = 77.22271.33L PC4515
DY 84.08878.A30 80K6R2F-GP VCLK
19
71K5R2F-1-GP
84.08878.A30 PC4514
3rd = 77.22271.39L
3rd = 77.22271.39L 2nd = 84.00780.037 2nd = 84.00780.037 DY 2 1
2

1
SC330P50V3KX-GP SC560P50V-GP
GAP-CLOSE-PWR-3-GP 3rd = 84.31007.037 3rd = 84.31007.037

2
PWR_5V3D3V_PGOOD 7 21 PR4512 GAP-CLOSE-PWR-3-GP
2

2
PGOOD GND
DY 200R2F-L-GP
VREG3

VREG5

2
1

1
74.51275.B73
3

13

PR4514 5V_PWR_2 PR4515

1
PR4513 DY0R2J-2-GP 3D3V_AUX_S5 3D3V_PWR_2 0R2J-2-GP DY
6K65R2F-GP PG4528 PR4516
1 2 15KR2F-GP
2

1 2

1 2
PWR_3D3V_FB2_R PWR_5V_FB1_R
PC4516 GAP-CLOSE-PWR-3-GP

2
DYSC18P50V2JN-1-GP PC4517 DY
SC18P50V2JN-1-GP
2

2
1

1
3D3V_S5
2 PR4517 PR4518 2
1

10KR2F-2-GP 9K76R2F-1-GP
1

PC4501 PC4518
PR4519 SC4D7U6D3V3KX-GP SC4D7U6D3V3KX-GP Close to VFB Pin (pin2)
2

2
100KR2J-1-GP

PR4521
2

18,24 ALW_PWRGD_3V_5V 2 1
Close to VFB Pin (pin5) 0R0402-PAD-2-GP

I/P cap: CHIP CAP C 10U 25V K0805 X5R/ 78.10622.51L

Inductor: CHIP IND 3.3UH PCMC063T-3R3MN Cyntec 28mohm/30mohm Isat =13.5Arms 68.3R310.20A
O/P cap: CHIP CAP POL 220U 6.3V M 6.3*4.5 /Matsuti/ 17mOhm / 77.52271.09L I/P cap: CHIP CAP C 10U 25V K0805 X5R/ 78.10622.51L
H/S:SIS412DN-T1-GE3 / 24mOhm/30mOhm@4.5Vgs / 84.00412.037 Inductor: CHIP IND 3.3UH PCMC063T-3R3MN Cyntec 28mohm/30mohm Isat =13.5Arms 68.3R310.20A
L/S:SIS406DN-T1-GE3 / 11.5mOhm/14.5mOhm@4.5Vgs / 84.00406.037 O/P cap: CHIP CAP POL 220U 6.3V M 6.3*4.5 /Matsuti/ 17mOhm / 77.52271.09L
H/S:SIS412DN-T1-GE3 / 24mOhm/30mOhm@4.5Vgs / 84.00412.037
L/S:SIS406DN-T1-GE3 / 11.5mOhm/14.5mOhm@4.5Vgs / 84.00406.037

1 1

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

3V/5V TPS51275
Size Document Number Rev
A2
Round Rock MLK 13.3" A00
Date: Monday, August 17, 2015 Sheet 45 of 110
A B C D E
 5 4 3 2 1

SSID = CPU.Regulator
PW R_VCC_VREF

1
PR4602 PR4603 PR4604 PR4605
499KR2F-1-GP 71K5R2F-1-GP
D
69.60037.031 NTC-100K-10-GP-U DY 75R2F-2-GP D
2nd = 69.60013.201

2
PC4602

2
1 2

1
SC4700P50V2KX-1GP
PR4628 9K09R2F-GP
1 2 PR4601 PR4607 PR4608
PR4610 PR4609 75KR2F-GP 39KR2F-GP
1 2 1 2 150KR2F-L-GP
549KR2F-GP 150KR2F-L-GP
PC4603

2
1 2
X01
SC1KP50V2KX-1GP

PR4611 1 DY 2 75R2F-2-GP PW R_VCC_B-RAMP

PW R_VCC_F-Imax
PR4612

PWR_VCC_THERM
PW R_VCC_O-USR

PWR_VCC_OCP-1
PWR_VCC_IMON
1 2PW R_VCC_SLEW A

39KR2F-GP

PR4613
DCBATOUT 1 2PW R_VCC_VBAT

10R3J-3-GP

16

15

14

13

12

11

10

9
C
PU4601 C
IMVP_PW RGD

THERM

IMON

O-USR
SLEWA

OCP-I

F-IMAX
VBAT

BOOT
17 8 IMVP_VRON PR4615 1 2 H_VR_ENABLE 7,36 EC4602
47 PW R_VCC_CSP1 CSP1 VR_ON

SCD1U25V2KX-GP
0R0402-PAD-2-GP

1
47 PW R_VCC_CSN1 18 CSN1 SKIP# 7 PW R_VCC_SKIP# 47
19 6 PW R_VCC_PW M1 47
DY

2
CSN2 PWM1
3D3V_S5 20 CSP2 PWM2 5
TPS51624RSMR-GP-U1 NC#4 PR4626 1
21 NC#21 MODE 4 2
150KR2F-L-GP
22
74.51624.073 3 PW R_PG PR4625 1 2 IMVP_PW RGD 36
NC#22 PGOOD 0R0402-PAD-2-GP
PR4616 1 2 0R0402-PAD-2-GP PW R_VCC_GFB 23 2 PW R_VCC_VDD PR4618 1 2 10R3J-3-GP 3D3V_S5
9 VSS_SENSE GFB VDD +V1.05S_VCCST

PC4609
SC1U10V2KX-1GP
PR4617 1 0R0402-PAD-2-GP PW R_VCC_VFB

1
7 VCC_SENSE 2 24 VFB VDIO 1
SCD1U16V2KX-3GP PC4605

VR_HOT#
2 DY 1

ALERT#
DROOP

COMP

VREF

VCLK
H_CPU_SVIDDAT 130R2F-1-GP 2 PR4621

2
1
GND

GND
V5A

H_CPU_SVIDCLK 54D9R2F-L1-GP 1 2 PR4622

25

26

27

28

29

30

31

32

33
VR_SVID_ALERT# 130R2F-1-GP 1 DY 2 PR4623

+V1.05S_VCCST

B B
PW R_VCC_DROOP H_PROCHOT# 56R2J-4-GP 1 DY 2 PR4630

PC4604 H_CPU_SVIDDAT 7
PWR_VCC_V5A

SC470P50V2JN-GP
2 DY 1 PW R_VCC_COMP VR_SVID_ALERT# 7

H_CPU_SVIDCLK 7
PR4620 H_PROCHOT# 4,24,44
1 2 1 2 PW R_VCC_VREF
PR4619 PR4624 1 2 10R3J-3-GP
1K58R2F-GP 5V_S5
2
SCD33U6D3V2KX-1-GP
PC4606

10KR2F-2-GP
PC4607
SC10U6D3V3MX-GP

X01
1
1

1 2 1 2
2

PR4627 PC4608
4K75R2F-1-GP SC1500P50V2KX-2GP
PWR_VCC_COMP_1

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

TPS51624_CPUCORE(1/2)
Size Document Number Rev
A3 A00
Round Rock MLK 13.3"
Date: Monday, August 17, 2015 Sheet 46 of 110
5 4 3 2 1
 5 4 3 2 1

SSID = CPU.Regulator

D D

DCBATOUT

1
PT4702 PC4701 PC4702 PC4703 EC2910

SCD1U50V3KX-GP
ST33U25VDM-3-GP

SC10U25V5KX-GP

SC10U25V5KX-GP

SC10U25V5KX-GP
DY

2
2

For acoustic noice

DCBATOUT
C C

1
PC4704 PU4701 5V_S5
PC4705 SC2D2U6D3V3KX-GP
SC1KP50V2KX-1GP

2
5 VIN VDD 2 1 2

PC4706
46 PW R_VCC_SKIP# 1 2PW R_VCC_SKIP#1 1 SKIP# BOOT_R 6 PW R_VCC_BOOTR11 2 VCC_BOOTR1_R

2
PR4701 0R0402-PAD-2-GP PR4702 0R0402-PAD-2-GP
SCD22U25V3KX-GP
8 7 PW R_VCC_BOOT1 VCC_CORE
46 PW R_VCC_PW M1 PWM BOOT PL4701

PGND
3 4 PW R_VCC_VSW 1 1 2
PGND VSW
IND-D22UH-21-GP

1
CSD97374Q4M-GP-U1 68.R2210.20C

9
74.97374.043 PR4703 2nd = 68.R2210.10W

2
GAP-CLOSE-PWR-3-GP
2

GAP-CLOSE-PWR-3-GP
2D2R3-1-U-GP

PG4708
PG4707
VCC_CORE

1
VCC_VSW1_GP 1
VCC_VSW 1_R

1
PC4707
PC4729

PC4730

PC4731

PC4732

PC4733

PC4734

PC4725

PC4736

PC4737

PC4738
SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP
SC22U6D3V3MX-1-GP

SC22U6D3V3MX-1-GP

SC22U6D3V3MX-1-GP

SC22U6D3V3MX-1-GP

SC22U6D3V3MX-1-GP

SC1KP50V2KX-1GP
1

B B

2
2

1
PR4704
3K32R2F-GP
X01

2
PR4705
1 2
5K23R2F-GP
PC4719

PC4720

PC4721

PC4722

PC4726

PC4709

PC4710

PC4711

PC4724

PC4735
SC10U6D3V3MX-GP

SC10U6D3V3MX-GP
SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP
SC22U6D3V3MX-1-GP

SC22U6D3V3MX-1-GP

SC22U6D3V3MX-1-GP

SC22U6D3V3MX-1-GP

SC22U6D3V3MX-1-GP
1

1
UMA_28W

PR4706 PR4707
DY 1 2VCC_CSN1_R 1 2 PW R_VCC_CSN1 46
2

NTC-10K-26-GP-U
3K01R2F-3-GP
69.60037.011
2nd = 69.60013.131
PC4708 1 2

SCD047U25V3KX-3-GP
PC4714

PC4727

PC4728

PC4715

PC4739

PC4740

PC4716

PC4741

PC4742

PC4743
SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

PW R_VCC_CSP1 46
1

1
UMA_28W

UMA_28W

UMA_28W

UMA_28W

UMA_28W

A
DY DY DY <Core Design> A
2

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

TPS51624_CPUCORE(2/2)
Size Document Number Rev
A3 A00
Round Rock MLK 13.3"
Date: Monday, August 17, 2015 Sheet 47 of 110
5 4 3 2 1
 5 4 3 2 1

SSID = PWR.Plane.Regulator_1p05v

DCBATOUT +PW R_SRC_1D05V

PG4813 1D05V_PW R 1D05V_M

1 2
PG4818
GAP-CLOSE-PW R-3-GP
1 2
D PG4819 D
GAP-CLOSE-PW R-3-GP
1 2 PG4815
GAP-CLOSE-PW R-3-GP 1 2

PG4816 GAP-CLOSE-PW R-3-GP

PG4814
1 2
1 2
GAP-CLOSE-PW R-3-GP
GAP-CLOSE-PW R-3-GP
PG4822 PG4817
1 2
1 2

PC4836 GAP-CLOSE-PW R-3-GP SY8206D for 1D05V GAP-CLOSE-PW R-3-GP

PG4812
1

1 2
ST33U25VDM-3-GP

DY GAP-CLOSE-PW R-3-GP
2

PG4823
1 2
+PW R_SRC_1D05V
GAP-CLOSE-PW R-3-GP

1
PC4820 PC4832
PR4830

SC4D7U25V5KX-GP
SC4D7U25V5KX-GP PU4801 PC4823

2
1 2 1D05V_PW R_BS_R 1 2
C Design Current = 3.634A C
SCD1U25V2KX-GP
0R3J-0-U-GP 5.451A<OCP<6.5412A
8 6 1D05V_PW R_BS
IN BS 1D05V_PW R
3D3V_M PL4801
36 PW R_1D05_PGOOD
PR4834
3D3V_M 1 2 10 1D05V_PW R_PH 1 2
100KR2J-1-GP LX
COIL-1UH-63-GP

GAP-CLOSE-PWR-3-GP
1KR2J-1-GP
DY 2 68.1R010.20I

1
1 1D05V_PW R_FB PC4830 PC4825 PC4829 PC4822 PC4831 PC4828
PR4814 2 PG FB 4

2
2nd = 68.1R01B.10K DY DY

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SCD1U16V2KX-3GP
PR4813 2 DY 1 PW R_1D05V_PW R_ILIM 3 7 1D05V_PW R_BYP PG4820

2
470KR2F-GP ILMT BYP 3D3V_S5
1

1
EN
1 2
1D05V_PW R_LDO PR4810
1

9 5
SCD1U16V2KX-3GP

GND LDO
1

DY 0R0402-PAD
PR4802 2 DY 1 0R2J-2-GP PC4818

1
24,36 A_ON PR4812
DY 1MR2J-1-GP SY8206DQNC-GP-U PC4802
2

PR4801 PW R_1D05_EN

1
17,24,36 SIO_SLP_A# 2 1 PC4803 SC1U10V2KX-1GP
0R0402-PAD-2-GP 74.08206.C73

2
SC2D2U10V3KX-1GP
2

2
1D05V_PW R_FBL

1
OCP setting PR4815 PC4801
B 75KR2F-GP SC220P50V2KX-3GP B
High 12A

2
Float 8A

2
Low 6A

1
Vo=0.6x(1+R1/R2) PR4811
=0.6x(1+75/100) 100KR2F-L1-GP

=1.05V

2
A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

SY8206_1D05V_M
Size Document Number Rev
A3 A00
Round Rock MLK 13.3"
Date: Monday, August 17, 2015 Sheet 48 of 110
5 4 3 2 1
 5 4 3 2 1

SSID = PWR.Plane.Regulator_1p35v0p675v

DCBATOUT +PWR_SRC_1D35V
PG4903 1D35V_PWR 1D35V_S3
PG4902
1 2
1 2
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
PG4901 +PWR_SRC_1D35V PG4904
1 2
D
1 2 D
GAP-CLOSE-PWR-3-GP PC4911 PC4912 PC4917
GAP-CLOSE-PWR-3-GP

1
PG4906

SC10U25V5KX-GP

SC10U25V5KX-GP

SCD01U50V2KX-1GP
DY PG4905
1 2

2
1 2
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
PG4907
1 2
PU4901
GAP-CLOSE-PWR-3-GP
3D3V_S5 Freq=800KHz Design Current = 3.08A
PG4909
4.622<OCP<5.55A
2D2R3-1-U-GP PC4906 1 2
1

PR4916 SCD1U25V2KX-GP
GAP-CLOSE-PWR-3-GP
PR4905 8 6 PWR_1D35V_BOOT 1 2 PWR_1D35V_BOOT_R 1 2
IN BS
DY 1KR2J-1-GP PL4901
1D35V_PWR
2

10 PWR_1D35V_PHASE 1 2
LX
COIL-1UH-63-GP
PWR_1D35V_PGOOD 2 4 PWR_1D35V_VFB 68.1R010.20I

1
PG FB DY

1
0R2J-2-GP 2nd = 68.1R01B.10KPG4920 PC4908
PC4924 PC4921 PC4922 PC4923 PC4927

SCD1U16V2KX-3GP
PR4907 1 DY 2 PWR_1D35V_IMAX 3 7 PWR_1D35V_BYP PR4902 1 2

SC22U6D3V5MX-2GP
3D3V_S0
ILMT BYP DY

GAP-CLOSE-PWR-3-GP

SC22U6D3V5MX-2GP
0R0402-PAD-2-GP

2
SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP
2

2
SC22U6D3V5MX-2GP
PR4928 2 1
24,36 SUS_ON DY 1 0R2J-2-GP EN

2
9 5 PWR_1D35V_LDO_P5
17,24,36 SIO_SLP_S4# PR4903 1 2 0R0402-PAD-2-GP PWR_1D35V_EN GND LDO
PC4902
SCD1U16V2KX-3GP

SY8206DQNC-GP-U
PWR_1D35V_VFB_H
1

DY
74.08206.C73

1
1

1
PC4919 PC4910
2

1
C SC220P50V2KX-3GP C
SC2D2U10V3KX-1GP PC4913

2
SC1U10V2KX-1GP PR4906

2
150KR2F-L-GP
R1

2
OCP setting PWR_1D35V_VFB
High 12A

1
Float 8A
Low 6A PR4904 R2 Vo=0.6x(1+R1/R2)
120KR2F-L-GP =0.6x(1+150/120)
=1.35V

2
B B
0D675V_VTTREF

0D675V_PWR 0D675V_S0
PG4917
PC4916 1 2
1
SCD1U16V2KX-3GP

GAP-CLOSE-PWR-3-GP
1D35V_S3
PG4918
2

1 2

GAP-CLOSE-PWR-3-GP

0R2J-2-GP 2 DY 1 PR4926 PC4915

24,36 RUN_ON
1

0R2J-2-GP 2 DY 1 PR4925 SC10U6D3V3MX-GP PC4918

17,24,36 SIO_SLP_S3#
14 DDR_VTT_PG_CTRL 1 2 PR4909 VTT_EN SCD1U16V2KX-3GP
0R0402-PAD-2-GP
2

0326
0R2J-2-GP DY 1 PR4927
11

24,36 SUS_ON 2
PU4902
1 2 PR4914 PU4902_S5 0D675V_PWR
GND

17,24,36 SIO_SLP_S4#
0R0402-PAD-2-GP
6 5
PR4917 VTTREF VTTSEN
7 4
S3 PGND
5V_S5 2 1 8 3
GND VTT
1

9 2 PC4914
0R2J-2-GP 0D675V_VCNTL S5 VIN SC22U6D3V5MX-2GP
10 1
VCNTL VREF
2
1

PR4918 PC4901
3D3V_S5 2 DY 1 SC1U10V2KX-1GP APL5338XAI-TRG-GP
74.05338.079
2

0R2J-2-GP

A A

If use 74.02997.B79, Stuff PR4918 and Dummy PR4917.

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

SY8206_1D35V & 0D675V

Size Document Number Rev
C A00
Round Rock MLK 13.3"
Date: Monday, August 17, 2015 Sheet 49 of 110
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A4
Round Rock MLK 13.3"
Date: Monday, August 17, 2015 Sheet 50 of 110
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A4 A00
Round Rock MLK 13.3"
Date: Monday, August 17, 2015 Sheet 51 of 110
5 4 3 2 1
SSID = VIDEO eDP_TXN0_CPU
eDP_TXP0_CPU
eDP_AUXN_CPU
eDP CONNECTOR eDP_AUXP_CPU

DCBATOUT_LCD

SC4D7P50V2CN-1GP
EC5201

SC4D7P50V2CN-1GP
EC5202

SC4D7P50V2CN-1GP
EC5203

SC4D7P50V2CN-1GP
EC5204
LCD1

1
38
DY DY DY DY
31 39

2
1

2
32 3
4
5
6 EMB_HPD
7 BLON_OUT_C
8 LCD_BRIGHTNESS_C
9 DBC_PANEL_EN 20
10 LCD_CBL_DET# 20
33 11 DP_DATA0_R# C5201 1 2 SCD1U16V2KX-3GP eDP_TXN0_CPU 8
12 DP_DATA0_R C5203 1 2 SCD1U16V2KX-3GP eDP_TXP0_CPU 8
13 DP_AUX# C5204 1 2 SCD1U16V2KX-3GP
eDP_AUXN_CPU 8 LCDVDD
14 DP_AUX C5205 1 2 SCD1U16V2KX-3GP
eDP_AUXP_CPU 8
15 LCD_TST_C R5205 1 2 100R2J-2-GP
LCD_TST 24
16
17

C5209
SCD1U16V2KX-3GP

C5210
SC1U10V2KX-1GP
1

1
18
34 19 NOTE: EN has an internal pull down resistor to GND.
20

2
21 DMIC_CLK 27
22 DMIC_DATA 27 PANEL_BKEN_PCH 15
23 X02
24
25 CAM_MIC_CBL_DET# 20

1
26
35 27 USB_CAMERA_N_R 3D3V_MIC_S0 3D3V_S0 R5217
28 USB_CAMERA_P_R R5231 BLON_OUT_C 1 2 BLON_OUT_R 3
29 1 2 0R0402-PAD-2-GP
D5201
30 3D3V_CAMERA_S0 LBAT54CLT1G-GP

1 R5219
100KR2J-1-GP
POLYSW -1D5A6V-12-GP

2
36 40 069.50001.0031 83.R2003.V81
2ND = 069.50001.0071 2nd = 75.00054.E7D
37 PANEL_BKEN_EC 99
3rd = 75.00054.A7D

2
IPEX-CON30-8-GP X02 Need change to 20.F2173.030
20.F2089.030
3D3V_S0 LCD_BRIGHTNESS_R
DCBATOUT_LCD AFTP4306
1
R5220
DY 2
0R2J-2-GP DP_UTIL 8
1
EMB_HPD 1 AFTP4308 X02
BLON_OUT_C 1 AFTP4309 R5207 1 DY 2 1KR2J-1-GP LCD_BRIGHTNESS_R

1
LCD_BRIGHTNESS_C 1 AFTP4310 1 2
DP_DATA0_R# AFTP4311 R5208 1 BIA_PW M_PCH 15
1 DY 2 1KR2J-1-GP PANEL_BKEN_PCH R5222 R5221 0R0402-PAD-2-GP
DP_DATA0_R 1 AFTP4312 LCD_BRIGHTNESS_C 1 2 LCD_BRIGHTNESS 3
DP_AUX# 1 AFTP4313 HPD Inversion for eDP 0R0402-PAD-2-GP
D5203

1
DP_AUX 1 AFTP4314
LBAT54CLT1G-GP
LCDVDD 1 AFTP4319 R5224

2
LCD_TST_C 1 AFTP4320 EMB_HPD R5225 1 2 100R2J-2-GP EDP_HPD 15 10KR2J-3-GP
LCD_CBL_DET# 1 AFTP4321
DMIC_DATA 1 AFTP4322 BIA_PW M_EC 24

2
1
USB_CAMERA_N_R 1 AFTP4323 83.R2003.V81
USB_CAMERA_P_R 1 AFTP4324 R5226
3D3V_CAMERA_S0 1 AFTP4325 100KR2J-1-GP 2nd = 75.00054.E7D
DMIC_CLK 1 AFTP4307 3rd = 75.00054.A7D
CAM_MIC_CBL_DET# 1 AFTP4315

2
DBC_PANEL_EN 1 AFTP4316
3D3V_MIC_S0 1 AFTP4317
84.02130.031 only for layout
Camera Power 3D3V_S0
Q5201
3D3V_CAMERA 3D3V_CAMERA_S0
DCBATOUT_LCD
INVERTER POWER
84.02130.031
DMP2130L-7-GP
SI3457 continuous 2.5A
2ND = 84.00102.031 R5228
1 2
Rds(on) = 0.113~0.092 Ohm
3rd = 84.03413.B31 S
DCBATOUT
SCD1U16V2KX-3GP

C5222
SC1KP50V2KX-1GP

C5223
SCD1U50V3KX-GP

C5224 D POLYSW -1D5A6V-12-GP U5203

1

2
D

SCD1U16V2KX-3GP C5225 069.50001.0031 1 D D 6

1

1
G

C5228 2ND = 069.50001.0071 2 D D 5

SCD1U16V2KX-3GP

DY C5227 3 G S 4
2

1
G

SC10U6D3V3MX-GP
2

1
SI3457CDV-T1-GE3-GP

1
84.03457.A3D
R5227 2ND = 84.00658.B3D C5226 R5213
20 3.3V_CAM_EN# 1 2 3.3V_CAM_EN#_R DMP2130 continuous 2.4A SCD1U25V2KX-GP 100KR2J-1-GP

2
0R0402-PAD-2-GP
Rds(on) = 99~125 mOhm

2
R_PW R_SRC

2
R5216
USB_CAMERA_N_R 47KR2J-2-GP
USB_CAMERA_N 16
C_PW R_SRC

1
TR5201
4 1
D

<Core Design>
3 2 Q5202
2N7002K-2-GP
FILTER-4P-156-GP-U
068.24900.2001
X02 84.2N702.J31 Wistron Corporation
2ND = 84.2N702.031 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
2ND = 68.11900.201 3rd = 84.2N702.W31 Taipei Hsien 221, Taiwan, R.O.C.

USB_CAMERA_P_R Title
USB_CAMERA_P 16
G

eDP Connector
Size Document Number Rev
24 EN_INVPW R
A3
Round Rock MLK 13.3" A00
Date: Monday, August 17, 2015 Sheet 52 of 110
 5 4 3 2 1

D D

C
(Blanking) C

B B

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A4 A00
Round Rock MLK 13.3"
Date: Monday, August 17, 2015 Sheet 53 of 110
5 4 3 2 1
 5 4 3 2 1

SSID = VIDEO HDMI CONNECTOR

HDMI1
Close to HDMI Connector 20

HDMI_DATA2_R_C_CON 1
C5401 1 2 SCD1U16V2KX-3GP HDMI_CLK_R_C#
8 HDMI_CLK# C5402 SCD1U16V2KX-3GP HDMI_CLK_R_C
8 HDMI_CLK 1 2 2
HDMI_DATA2_R_C#_CON 3
D C5403 1 2 SCD1U16V2KX-3GP HDMI_DATA0_R_C# HDMI_DATA1_R_C_CON 4 D
8 HDMI_DATA0# C5404 SCD1U16V2KX-3GP HDMI_DATA0_R_C
8 HDMI_DATA0 1 2 5
HDMI_DATA1_R_C#_CON 6
HDMI_DATA0_R_C_CON 7
8
HDMI_DATA0_R_C#_CON 9
C5405 1 2 SCD1U16V2KX-3GP HDMI_DATA1_R_C# HDMI_CLK_R_C_CON 10
8 HDMI_DATA1# C5406 SCD1U16V2KX-3GP HDMI_DATA1_R_C
8 HDMI_DATA1 1 2 11
HDMI_CLK_R_C#_CON 12
C5407 1 2 SCD1U16V2KX-3GP HDMI_DATA2_R_C# AFTP5414 1 HDMI_CEC 13
8 HDMI_DATA2# C5408 SCD1U16V2KX-3GP HDMI_DATA2_R_C 5V_S0 5V_HDMI
8 HDMI_DATA2 1 2 14
DDC_CLK_HDMI 15
D5401 DDC_DATA_HDMI 16
17
OUT 2 18

8
7
6
5

8
7
6
5
3 HPD_HDMI_CON 19
IN

C5409
SCD1U16V2KX-3GP
RN5401 RN5402 1
GND

1
C5410
SCD1U16V2KX-3GP
SRN470J-5-GP SRN470J-5-GP AFTP5401 1 21

1
5V_S0
Q5403
AP2331SA-7-GP SKT-HDMI21-6-GP

2
G 074.02331.009B 22.10296.751

1
2
3
4

1
2
3
4

2
2ND = 74.03517.07B 2ND = 22.10296.711
1

D HDMI_PLL_GND
R5401
DY 100KR2J-1-GP S EV ME

1
R5402
2

2N7002K-2-GP 0R2J-2-GP 3D3V_S0

DY
84.2N702.J31
C C
2ND = 84.2N702.031 2
3rd = 84.2N702.W31

1
Q5404
R5403
1MR2J-1-GP G
R5407
D HDMI_HPD_D 1 2 HPD_HDMI_CON

2
0R0402-PAD-2-GP
R5406

1
15 HDMI_PCH_DET 1 2 HDMI_HPD_S S
0R0402-PAD-2-GP R5408
20KR2J-L2-GP
HDMI_CLK_R_C# R5404 1 0R0402-PAD-2-GP HDMI_CLK_R_C#_CON HDMI_DATA1_R_C# R5405 1 0R0402-PAD-2-GP HDMI_DATA1_R_C#_CON 2N7002K-2-GP
2 2
84.2N702.J31

2
2ND = 84.2N702.031
3rd = 84.2N702.W31

5V_S0

3
HDMI_CLK_R_C R5410 1 2 0R0402-PAD-2-GP HDMI_CLK_R_C_CON HDMI_DATA1_R_C R5409 1 2 0R0402-PAD-2-GP HDMI_DATA1_R_C_CON D5402
LBAW 56LT1G-GP
83.00056.Y11
2nd = 75.00056.I7D
3rd = 75.00056.07D

1
B B

15V_S0_D2

5V_S0_D1
HDMI_DATA0_R_C# R5411 1 2 0R0402-PAD-2-GP HDMI_DATA0_R_C#_CON HDMI_DATA2_R_C# R5412 1 2 0R0402-PAD-2-GP HDMI_DATA2_R_C#_CON

2
3D3V_S0 RN5403
SRN2K2J-1-GP

4
3
Q5401
HDMI_DATA2_R_C_CON 1 AFTP5402
15 PCH_HDMI_CLK 4 3 DDC_CLK_HDMI HDMI_DATA2_R_C#_CON 1 AFTP5403
HDMI_DATA1_R_C_CON 1 AFTP5404
HDMI_DATA0_R_C R5413 1 2 0R0402-PAD-2-GP HDMI_DATA0_R_C_CON 5 2 HDMI_DATA1_R_C#_CON 1 AFTP5405
HDMI_DATA2_R_C R5414 1 2 0R0402-PAD-2-GP HDMI_DATA2_R_C_CON HDMI_DATA0_R_C_CON 1 AFTP5406
6 1 HDMI_DATA0_R_C#_CON 1 AFTP5407
HDMI_CLK_R_C_CON 1 AFTP5408
2N7002KDW -GP HDMI_CLK_R_C#_CON 1 AFTP5409
84.2N702.A3F DDC_CLK_HDMI 1 AFTP5410
2nd = 84.DMN66.03F DDC_DATA_HDMI 1 AFTP5411
15 PCH_HDMI_DATA HPD_HDMI_CON 1 AFTP5412
5V_HDMI 1 AFTP5413
EV DDC_DATA_HDMI

A <Variant Name> A
HDMI_CLK_R_C#_CON HDMI_DATA0_R_C#_CON HDMI_DATA1_R_C#_CON HDMI_DATA2_R_C#_CON
1

R5415 R5416 R5417 R5418 Wistron Corporation

150R2J-L1-GP-U 150R2J-L1-GP-U 150R2J-L1-GP-U 150R2J-L1-GP-U 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2

HDMI_CLK_R_C_CON HDMI_DATA0_R_C_CON HDMI_DATA1_R_C_CON HDMI_DATA2_R_C_CON Title

HDMI Level Shifter/Connector
Size Document Number Rev
A3
Round Rock MLK 13.3" A00
Date: Monday, August 17, 2015 Sheet 54 of 110
5 4 3 2 1
 5 4 3 2 1

5V_S0
SSID = VIDEO
8 DDPC_DATA0 1 2 mDP_DATA0_A_C mDP_DATA0_A 8 DDPC_DATA2 1 2 mDP_DATA2_A_C mDP_DATA2_A

1
C5502 SCD1U16V2KX-3GP C5506 SCD1U16V2KX-3GP
C5513
SCD1U16V2KX-3GP

2
TR5502

16
TR5501
U5501 1 4
1 4

VCC
2 3
2 3
LP_DDPC_AUX_C DDPC_AUX FILTER-4P-156-GP-U
D 15
15
LP_DDPC_AUX
DP_HDMI_CLK
1
C5509
2
SCD1U16V2KX-3GP
2
3
1B1 1A 4
X02 FILTER-4P-156-GP-U X02 068.24900.2001 D

1 2 LP_DDPC_AUX#_C 5
1B2
7 DDPC_AUX# 068.24900.2001 2ND = 68.11900.201
15 LP_DDPC_AUX# 2B1 2A 2ND = 68.11900.201
15 DP_HDMI_DATA C5510 SCD1U16V2KX-3GP 6 2B2
11 3B1 3A 9
10 3B2 mDP_DATA0_A#_C mDP_DATA0_A# mDP_DATA2_A#_C mDP_DATA2_A#
8 DDPC_DATA0# 1 2 8 DDPC_DATA2# 1 2
14 4B1 4A 12 C5503 SCD1U16V2KX-3GP C5505 SCD1U16V2KX-3GP
13 4B2
15 1 mDP_CA_DET
OE# S

1
GND
GND
8 DDPC_DATA1# 1 2 mDP_DATA1_A#_C mDP_DATA1_A# 8 DDPC_DATA3# 1 2 mDP_DATA3_A#_C mDP_DATA3_A#
C5501 SCD1U16V2KX-3GP C5508 SCD1U16V2KX-3GP
DY D5502
VARISTOR-27V-2-GP

8
17
74FST3257MNTW G-GP X01 69.80005.081
TR5503 TR5504

2
73.03257.B03 1 4 1 4

2 3 2 3

FILTER-4P-156-GP-U FILTER-4P-156-GP-U
X02 068.24900.2001 X02 068.24900.2001
2ND = 68.11900.201 2ND = 68.11900.201

8 DDPC_DATA1 1 2 mDP_DATA1_A_C mDP_DATA1_A 8 DDPC_DATA3 1 2 mDP_DATA3_A_C mDP_DATA3_A

C5504 SCD1U16V2KX-3GP C5507 SCD1U16V2KX-3GP

C C

DP1

1MR2J-1-GP 2 1 R5507 mDP_CA_DET 4 16 DDPC_AUX

DP_CEC CONFIG_1 AUX_CHP DDPC_AUX#
6 CONFIG_2 AUX_CHN 18

mDP_DATA0_A# 5 21
mDP_DATA0_A ML_LANGE0N CHASSIS#21
3 ML_LANGE0P CHASSIS#22 22
CHASSIS#23 23
5V_S0 mDP_DATA1_A# 11 24
mDP_DATA1_A ML_LANGE1N CHASSIS#24
9 ML_LANGE1P
25 25
Schematic check list mDP_DATA2_A# 17 26
mDP_DATA2_A ML_LANGE2N 26
no need pull-up 15 ML_LANGE2P
Remove R5508 Q5501
G

LSK3541G1ET2L-GP mDP_DATA3_A# 12
mDP_DATA3_A ML_LANGE3N
84.03541.F31 10 ML_LANGE3P GND 1
2ND = 84.03K15.C31 GND 7
GND 8
15 PCH_DPC_HPD S D DPC_HPD 2 13
HOT_PLUG_DETECT GND
GND 14
1

3D3V_DP_S0
SCD01U50V2KX-1GP

20 DP_PWR/PWR_OUT GND 19
1

C5539

D5503 MINI_DP
VARISTOR-27V-2-GP
DY SKT-DISPLAY20P-41-GP-U1
2

1
SCD1U16V2KX-3GP
C5511

SCD022U16V2KX-3GP
C5512

C5514
SC22U6D3V5MX-2GP

B
69.80005.081 62.10105.581 B
DY DY
2

X02 mDP_DATA0_A# mDP_DATA2_A

mDP_DATA0_A mDP_DATA2_A#
mDP_DATA1_A mDP_DATA3_A#
3D3V_DP_S0 mDP_DATA0_A 1 AFTP5501 mDP_DATA1_A# mDP_DATA3_A
3D3V_S0
500mA mDP_DATA0_A# 1 AFTP5502
U5502 U5503
mDP_DATA1_A 1 AFTP5503
D5501 1 10 1 10
mDP_DATA1_A# 1 AFTP5504
mDP_DATA2_A 1 AFTP5505
OUT 2 mDP_DATA2_A# AFTP5506 2 9 2 9
1
3 IN DPC_HPD AFTP5507
1
GND 1 mDP_CA_DET AFTP5508 3 3
1

1
SCD1U16V2KX-3GP
C5515

DP_CEC AFTP5509 8 8
1
mDP_DATA3_A AFTP5510 4 7 4 7
AP2337SA-7-GP 1
mDP_DATA3_A# AFTP5511
2

1
074.02337.009B DDPC_AUX 1 AFTP5512 5 6 5 6
2ND = 074.03534.009B DDPC_AUX# 1 AFTP5513
3D3V_DP_S0 1 AFTP5514

RCLAMP0524PATCT-1-GP-U RCLAMP0524PATCT-1-GP-U
3D3V_S0 75.00524.073 75.00524.073
2ND = 075.01043.0073 2ND = 075.01043.0073
DDPC_AUX# 100KR2J-1-GP 2 1 R5502 INPUT SWITCH X01 EMI X01 EMI
OE# S DDPC_AUX
A DDPC_AUX# <Core Design> A
DDPC_AUX 100KR2J-1-GP 2 1 R5503
L L nA to nB1 U5504
DP_CEC 5M1R2J-GP 1 R5504
2
L H nA to nB2 1 6 Wistron Corporation
DPC_HPD 100KR2J-1-GP 2 1 R5505 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
2 5 Taipei Hsien 221, Taiwan, R.O.C.
3
4 Title
H X Switch Off
RCLAMP0522PDTCT-GP Mini Display Port
75.00522.073 Size Document Number Rev
A3
X01 EMI Round Rock MLK 13.3" A00
Date: Monday, August 17, 2015 Sheet 55 of 110
5 4 3 2 1
SSID = SATA R5601
3D3V_S0_HDD

3D3V_S0 1 2
0R0603-PAD-2-GP-U

1
C5602
C5601 SC3D3P50V2CN-GP R5605
SC68P-GP
DY 0R2J-2-GP

2
HDD1

2
P1 V33 23 23
5V_S0_HDD P2 24
V33 24
20 mSATA_DEVSLP 1 2 mSATA_DEVSLP_R P3 V33
R5602 R5604 0R0402-PAD-2-GP
5V_S0 1 2 P7 V5

SC10U6D3V3MX-GP
0R0603-PAD-2-GP-U P8 V5

C5603
P9 V5

1
R5603 C5604
1 2 SCD1U16V2KX-3GP P13 S1
V12 GND
0R0603-PAD-2-GP-U P14 S4

2
V12 GND
P15 V12 GND S7
GND P4
3D3V_AUX_S5 SCD01U50V2KX-1GP P5
C5605 1 SATA_TXP0_C GND HDD_DET# 19
19 SATA_TXP0 2 S2 A+ GND P6

1
19 SATA_TXN0 C5606 1 2 SATA_TXN0_C S3 P10 EC5601
SCD01U50V2KX-1GP A- GND SC1KP50V2KX-1GP
GND P12
C5608 1 2 SATA_RXP0_C S6

2
19 SATA_RXP0 B+
1

C5607 1 2 SATA_RXN0_C S5 P11

R5607 19 SATA_RXN0 B- DAS/DSS
100KR2J-1-GP SCD01U50V2KX-1GP
DY SCD01U50V2KX-1GP SKT-SATA7P-15P-85-GP-U
FFS_INT2_Q 67
15V_S5
20.81599.022
2

5V_HDD_ENABLE#
2nd = 22.10300.C51

1
DY R5606 5V_S0 5V_S0_HDD
EV reserved for modern stanby 100KR2J-1-GP

2
6

Q5601
2N7002KDW-GP
DY U5603 U5602
84.2N702.A3F 1 D D 6
2nd = 84.DMN66.03F 2 D D 5
SATA_TXP0_C SATA_TXP0_C
3 G DY
5V_HDD_ENABLE 1 10
1

S 4 LINE_1 NC#10
SATA_TXN0_C 2 9 SATA_TXN0_C
LINE_2 NC#9
AO6402A-GP 3 GND GND 8
SATA_RXN0_C 4 7 SATA_RXN0_C
C5909 84.06402.B3D LINE_3 NC#7
1 SATA_RXP0_C 5 6 SATA_RXP0_C
2ND = 84.P2703.03D LINE_4 NC#6

SC4700P50V2KX-1GP
R5608 DY
2 DY 1 HDD_PWR_EN_R 3rd = 84.03456.D3D
20 HDD_PWR_EN AO6402A MAX 7A
2

0R2J-2-GP AZ1045-04F-R7G-GP
1

Rds(on) = 27~40m Ohm 75.01045.073

R5610 2nd = 75.01004.073
R5609
99 HDD_PWR_EN_SIO 2 DY 1 DY 100KR2J-1-GP
0R2J-2-GP EV EMC
2

550 mA
U5601 3D3V_S0_HDD
3D3V_S0

GND 9
1 8 <Core Design>
VIN#1 VOUT#8
2 VIN#2 DY VOUT#7 7
1

C5612 20 3.3V_HDD_EN 3 6 3D3V_S0_HDD_CT

ON CT
Wistron Corporation
C5611
SC470P50V2KX-3GP
SC10U10V5KX-2GP DY 5V_S5 4 5
VBIAS GND 1
2

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

TPS22965DSGR-GP-U
DY Taipei Hsien 221, Taiwan, R.O.C.
2

74.22965.093 Title
2nd = 74.03526.093
HDD
Size Document Number Rev
A4 A00
Round Rock MLK 13.3"
Date: Monday, August 17, 2015 Sheet 56 of 110
 5 4 3 2 1

D D

C C

(Blanking)

B B

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A4 A00
Round Rock MLK 13.3"
Date: Monday, August 17, 2015 Sheet 57 of 110
5 4 3 2 1
 5 4 3 2 1

SSID = WIRELESS

3D3V_AUX_S5 15V_S5

1
700 mA
R5817
100KR2J-1-GP R5818 3D3V_S5 3D3V_S5_WLAN
100KR2J-1-GP

2
D 3.3V_WLAN_ENABLE# U5801 D
1 D D 6
2 D D 5
3.3V_WLAN_ENABLE 3 G S 4

AO6402A-GP
C5817 84.06402.B3D

1
2ND = 84.P2703.03D

SC4700P50V2KX-1GP

C5806
SC470P50V2KX-3GP

C5807
SC470P50V2KX-3GP

C5808
SC10U6D3V3MX-GP
Q5801 3rd = 84.03456.D3D

1
EV 84.2N702.A3F
2nd = 84.DMN66.03F
2N7002KDW-GP AO6402A MAX 7A

2
Rds(on) = 27~40m Ohm

2
R5820
1 2 3.3V_WLAN_EN
99 AUX_EN_WOWL
0R0402-PAD-2-GP

1
R5816
100KR2J-1-GP

2
1 2 MINI_CARD_RST#
17,32,59 PLTRST_MMI#
R5830 0R0402-PAD-2-GP

BT_RADIO_DISABLE#_R 2 1 R5808
3D3V_S5_WLAN 0R0402-PAD-2-GP BT_RADIO_DISABLE# 99
Follow M.2 spec
WLAN1
3D3V_S5_WLAN WLAN_RADIO_DIS#_R 2 1 R5806
NP2 NP1 0R0402-PAD-2-GP WLAN_RADIO_DIS# 99
NP2 NP1
C5801
SCD1U16V2KX-3GP

C5803
SC4D7U6D3V3KX-GP

C5804
SCD1U16V2KX-3GP

76 77
EV removed 2nd PCIE (doesn't support WIGIG)
1

76 77
74 75
3_3V GND
C DY 72
3_3V REFCLKN1
73 C
70 71
2

PEWAKE1#_0/3_3V REFCLKP1
68 69
CLKREQ1#_0/3_3V GND
66 67
PERST1#_0/3_3V PETN1
64 65
RESERVED#64 PETP1
62 63
ALERT_0/3_3 GND
60 61
I2C_CLK_0/3_3 PERN1
58 59
WLAN_RADIO_DIS#_R I2C_DATA_0/3_3 PERP1
56 57
BT_RADIO_DISABLE#_R W_DISABLE#1_0/3_3V GND
54 55 PCIE_WLAN_WAKE# 59,99
R5815 MINI_CARD_RST# RESERVED/W_DISABLE#2_0/3_3V PEWAKE0#_0/3_3V
52 53 MINI1CLK_REQ# 18
SUSCLK_NGFF_R PERST0#_0/3_3V CLKREQ0#_0/3_3V
17,59 SUSCLK_NGFF 1 DY 2 50 51
0R2J-2-GP SUSCLK/32KHZ_0/3_3V GND
48 49 CLK_PCIE_N3_WLAN# 18
COEX1_0/1_8V REFCLKN0
46 47 CLK_PCIE_P3_WLAN 18
COEX2_0/1_8V REFCLKP0
44 45
R5809 1 CL_CLK_R COEX3_0/1_8V GND PCIE_RXN4_C
18 CL_CLK DY 2 0R2J-2-GP 42 43 R5828 1 2 0R0402-PAD-2-GP PCIE_RXN4 16
R5810 1 CL_DATA_R CLINK_CLK PETN0 PCIE_RXP4_C
18 CL_DATA DY 2 0R2J-2-GP 40 41 R5829 1 2 0R0402-PAD-2-GP PCIE_RXP4 16
R5811 1 CL_RST#_R CLINK_DATA PETP0 USB_WLAN_N_R
18 CL_RST# DY 2 0R2J-2-GP 38 39 16 USB_WLAN_N
CLINK_RESET GND PCIE_TXN4_C C5809 1
36 37 2 SCD1U16V2KX-3GP PCIE_TXN4 16
GND PERN0 PCIE_TXP4_C C5810 1
34 35 2 SCD1U16V2KX-3GP PCIE_TXP4 16
DP_ML0P PERP0
32 33
DP_ML0N GND
30 31
GND DP_HPD_0/3_3V
28 29
DP_ML1P GND TR5801
26
24
DP_ML1N Module Key DP_ML2P
27
25 1 4
GND DP_ML2N
22 23
DP_AUXP GND X02
20 21 2 3
DP_AUXN DP_ML3P
18 19
GND DP_ML3N FILTER-4P-156-GP-U
61 BT_LED# 16 17
LED#2 DP_MLDIR
068.24900.2001
2ND = 68.11900.201
61 WLAN_LED# 6 7
LED#1 GND USB_WLAN_N_R
4 5
3_3V USB_D- USB_WLAN_P_R
2 3
3_3V USB_D+ USB_WLAN_P_R
1 16 USB_WLAN_P
NGFF_KEY_A 75P GND

SKT-MINI67P-12-GP-U
062.10007.0081
2nd = 062.10003.0621
B EV ME B

3D3V_S5_WLAN 1 AFTP5801
PCIE_WLAN_WAKE# 1 AFTP5802
MINI1CLK_REQ# 1 AFTP5803
CLK_PCIE_N3_WLAN# 1 AFTP5804
EMI request
CLK_PCIE_P3_WLAN 1 AFTP5805
WLAN_RADIO_DIS#_R 1 AFTP5810
MINI_CARD_RST#
CLK_PCIE_N3_WLAN#

1 AFTP5811
CLK_PCIE_P3_WLAN

PCIE_RXN4_C 1 AFTP5812
PCIE_RXP4_C 1 AFTP5813
PCIE_TXN4_C 1 AFTP5814
BT_RADIO_DISABLE#_R 1 AFTP5815
PCIE_TXP4_C 1 AFTP5816
EC2912

EC2911

USB_WLAN_N_R 1 AFTP5817
USB_WLAN_P_R 1 AFTP5819
WLAN_LED# 1 AFTP5821
BT_LED# 1 AFTP5823
SC33P50V2JN-3GP

SC33P50V2JN-3GP

SUSCLK_NGFF_R
1

1 AFTP5818
CL_CLK_R 1 AFTP5820
CL_DATA_R 1 AFTP5822
DY DY
CL_RST#_R
2

1 AFTP5824

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

MINICARD(WLAN)
Size Document Number Rev
Round Rock MLK 13.3" A00
Date: Monday, August 17, 2015 Sheet 58 of 110
5 4 3 2 1
 5 4 3 2 1

SSID = WIRELESS NGFF(WWAN/SSD)

3D3V_AUX_S5 15V_S5
Place near WWAN CONN

1
3D3V_S5_W W AN 2750 mA 3D3V_S5_W W AN
R5910
100KR2J-1-GP
WWAN WWAN100KR2J-1-GP
R5909 3D3V_S5 3D3V_S5_W W AN
WWAN WWAN WWAN WWAN

C5901
SCD1U16V2KX-3GP

C5902
C5902
SCD1U16V2KX-3GP

C5903
C5903
SCD1U16V2KX-3GP
1

1
ST220U6D3VBM-3-GP
TC5901

ST220U6D3VBM-3-GP
TC5902
R5903 1 WWAN 2 1MR2J-1-GP UIM_DET

2
D
R5907 1
DY D
DY 2 100KR2J-1-GP NGFF_DEVSLP1

2
2ND = 77.22271.33L
77.C2271.45L

2ND = 77.22271.33L
77.C2271.45L
3.3V_W W AN_ENABLE# U5901
1 D D 6
2 D D 5 3D3V_S5_W W AN
3.3V_W W AN_ENABLE 3 G WWAN S 4
MINI2CLK_REQ# R5915 1 DY 2 10KR2J-3-GP
AO6402A-GP
C5908 84.06402.B3D NGFF_CONFIG_0 R5917 1 2 100KR2J-1-GP

1
2ND = 84.P2703.03D

SC4700P50V2KX-1GP
Q5901 WWAN 3rd = 84.03456.D3D NGFF_CONFIG_1 R5918 1 2 100KR2J-1-GP
84.2N702.A3F 2N7002KDW -GP AO6402A MAX 7A
WWAN

2
2nd = 84.DMN66.03F NGFF_CONFIG_2 R5919 1 2 100KR2J-1-GP
Rds(on) = 27~40m Ohm

3
NGFF_CONFIG_3 R5920 1 2 100KR2J-1-GP

R5924
99 MCARD_W W AN_PW REN 2 1 W W AN_PW R_EN_D
0R0402-PAD-2-GP

1
R5911 Follow M.2 Spec
100KR2J-1-GP WWAN W W AN1
EV
77

2
77
76 76
99 NGFF_CONFIG_2 75 USB3_0_IND CONFIG2
73 GND 3_3VAUX 74 3D3V_S5_W W AN
C 71 72 C
GND 3_3VAUX
99 NGFF_CONFIG_1 69 PEDET CONFIG1 3_3VAUX 70
W W AN_RESET# 67 68 SUSCLK_NGFF_C R5923 1 DY 2 0R2J-2-GP SUSCLK_NGFF 17,58
RESET# SUSCLK_32KHZ
65 ANTCTL3 SIM_DETECT 66 UIM_DET 60
63 ANTCTL2 COEX1 64
61 ANTCTL1 COEX2 62
59 ANTCTL0 COEX3 60 NC on EM7455
57 GND NC#58 58
18 CLK_PCIE_P5_W W AN 55 REFCLKP NC#56 56
53 54 NGFF_W AKE# R5913 1 DY 2 0R2J-2-GP PCIE_W LAN_W AKE# 58,99
18 CLK_PCIE_N5_W W AN# REFCLKN PEWAKE#
EV 51 GND CLKREQ# 52 MINI2CLK_REQ# 15,18
19 SATA_TP3/PETP6_L0 C5906 1 DY2 SCD1U16V2KX-3GP PETP0/SATA_A+ 49 50 W W AN_RESET# R5929 1 DY 2 0R2J-2-GP PLTRST_MMI# 17,32,58
C5907 1 SCD1U16V2KX-3GP PETN0/SATA_A- PERP0/SATA_A+ PERST#
19 SATA_TN3/PETN6_L0 DY2 47 PERN0/SATA_A- GNSS4 48
45 GND GNSS3 46
19 SATA_RN3/PERN6_L0 R5914 1 DY 2 0R2J-2-GP PERN0/SATA_B- 43 44
R5904 2 0R2J-2-GP PERP0/SATA_B+ PETP0/SATA_B- GNSS2 NC on EM7455
19 SATA_RP3/PERP6_L0 1 DY 41 PETN0/SATA_B+ WWAN GNSS1 42
39 GND GNSS0 40
3D3V_S5_W W AN 1 AFTP5901 C5904 WWAN1 2 SCD1U16V2KX-3GP USB3_TXP3_R 37 38 NGFF_mSATA_DEVSLP R5902 1 DY 2 0R2J-2-GP NGFF_DEVSLP1 20
W W AN_PW R_OFF# 16 USB3_TXP3 C5905 WWAN SCD1U16V2KX-3GP USB3_TXN3_R PERP1/USB3_0_RX+/SSIC_RXP DEVSLP UIM_PW R
1 AFTP5902 16 USB3_TXN3 1 2 35 PERN1/USB3_0_RX-/SSIC_RXN UIM_PWR 36 UIM_PW R 60
W W AN_RADIO_DIS# 1 AFTP5903 33 34 UIM_DATA_R R5906 1 2 0R0402-PAD-2-GP UIM_DATA 60
LED_W W AN_OUT# R5927 1 GND UIM_DATA
1 AFTP5904 16 USB3_RXP3 2 0R0402-PAD-2-GP USB3_RXP3_R 31 PETP1/USB3_0_TX+/SSIC_TXP UIM_CLK 32 UIM_CLK_R R5905 1 2 0R0402-PAD-2-GP UIM_CLK 60
HW _GPS_DISABLE2# 1 AFTP5905 16 USB3_RXN3 R5928 1 2 0R0402-PAD-2-GP USB3_RXN3_R 29 30 UIM_RESET UIM_RESET 60
MINI2CLK_REQ# PETN1/USB3_0_TX-/SSIC_TXN UIM_RESET UIM_RFU R5908
1 AFTP5921 27 GND UIM_RFU 28 1 DY 2 0R2J-2-GP UIM_VPP 60
UIM_DET 1 AFTP5907 25 DPR W_DISABLE#2 26 HW _GPS_DISABLE2# 99
SUSCLK_NGFF_C RESERVED#25 AUDIO3
1 AFTP5908 99 W W AN_W AKE# 23 RESERVED#23 WAKE_ON_WAN# NC AUDIO2 24
USB_W W AN_P_R 1 AFTP5909 99 NGFF_CONFIG_0 21 NC AUDIO1 22
WWAN/SSD_INDCONFIG0
USB_W W AN_N_R 1 AFTP5910 NC AUDIO0 20 NC on EM7455
NGFF_W AKE# 1 AFTP5912
PERP0/SATA_B+ 1 AFTP5913 11
B PERN0/SATA_B- USB_W W AN_N_R GND B
1 AFTP5914 9 USB_D- LED#1/DAS/DSS# 10 LED_W W AN_OUT# 61
PETN0/SATA_A- 1 AFTP5915 USB_W W AN_P_R 7 8 W W AN_RADIO_DIS# 99
PETP0/SATA_A+ USB_D+ W_DISABLE#1 W W AN_PW R_OFF# R5901 1
1 AFTP5916 5 GND FULL_CARD_POWER_OFF# 6 2 0R0402-PAD-2-GP 3D3V_S5_W W AN
NGFF_mSATA_DEVSLP 1 AFTP5906 3 4
CLK_PCIE_N5_W W AN# GND 3_3VAUX
1 AFTP5922 99 NGFF_CONFIG_3 1 PRESENCE_IND CONFIG3 3_3VAUX 2 3D3V_S5_W W AN
CLK_PCIE_P5_W W AN 1 AFTP5923
NGFF_CONFIG_0 1 AFTP5911 NP2 NP1
NGFF_CONFIG_1 NP2 NGFF_KEY_B 75P NP1
1 AFTP5917
NGFF_CONFIG_2 1 AFTP5919
NGFF_CONFIG_3 1 AFTP5920 SKT-MINI67P-GP-U1
W W AN_RESET# 1 AFTP5929 62.10043.I71
2ND = 062.10003.0121 EV ME

16 USB_W W AN_N USB_W W AN_N_R

TR5901
1 4
WWAN X02
2 3
A <Core Design> A
FILTER-4P-156-GP-U
068.24900.2001
2ND = 68.11900.201
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
16 USB_W W AN_P USB_W W AN_P_R Taipei Hsien 221, Taiwan, R.O.C.

Title

NGFF-WWAN/SSD
Size Document Number Rev
Round Rock MLK 13.3" A00
Date: Monday, August 17, 2015 Sheet 59 of 110
5 4 3 2 1
 5 4 3 2 1

SSID =WIRELESS

D D
SIM1

59 UIM_PWR UIM_PWR C1 C7 UIM_DATA UIM_DATA 59

VCC I/O
PIN 62.10034.561 Micro SIM PinDefine
UIM_RESET
WWAN AFTP6007
59 UIM_RESET C2 RST GND C5 1 C1 VCC
59 UIM_CLK UIM_CLK C3 8
UIM_VPP CLK GND
59 UIM_VPP C6 VPP GND 9 C2 RST
GND 10
59 UIM_DET UIM_DET SW 11 C3 CLK
SW GND
C4 Reserve
SKT-SIMM7-2-GP
62.10034.561 C5 GND
C6 VPP
C7 I/O
C SW SIM Card Detect C

8 PTH GND
9 PTH GND
10 PTH GND
11 PTH GND

UIM_PWR 1 AFTP6001
UIM_VPP 1 AFTP6002
UIM_RESET 1 AFTP6003
UIM_DET 1 AFTP6004
UIM_DATA 1 AFTP6005
UIM_CLK 1 AFTP6006

B B
D6001
UIM_RESET 1 6 UIM_VPP

2 5 UIM_PWR
DY

UIM_CLK 3 4 UIM_DATA
SC1U10V2KX-1GP
SC33P50V2JN-3GP

SC33P50V2JN-3GP

SC33P50V2JN-3GP

SC33P50V2JN-3GP

AOZ8902CIL-1-GP
C6001

C6002

C6003

C6004

C6005

75.08902.07C
1

<Core Design>
2

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
WWAN WWAN WWAN WWAN
WWAN Title
Layout Close to SIM1 Connector
uSIM
Size Document Number Rev
Round Rock MLK 13.3" A00
Date: Monday, August 17, 2015 Sheet 60 of 110
5 4 3 2 1
 5 4 3 2 1

SSID = User.Interface

19 SATA_LED#

1
R6101 SATA HDD LED

10KR2J-3-GP
Q6105
3D3V_S0 3D3V_S5 LOW actived from PCH GPIO 3D3V_S5
2 1 6

2 5

SCD1U16V2KX-3GP
C6101
1
3 4

1
R6116 5V_S5
D 2N7002KDW-GP 10KR2J-3-GP Q6102 DY D
SATA_LED#_M S Q6103 HDLED1 U6101

2
84.2N702.A3F R2
E 1

2
2nd = 84.DMN66.03F 24,98 LID_CL_SIO# B

3
D SATA_LED#_B B R6102 5
LED_SATA_DIAG_OUT# 99 R1
SATA_LED SATA_LED_R 1A VCC
C 1 2 2K 2
G
99 SYS_LED_MASK# A DY 4 MASK_BASE_LEDS#
MASK_BASE_LEDS# 31
LMUN2132LT1G-GP 150R2J-L1-GP-U Y
LED-W-27-GP-U 3
GND
2N7002K-2-GP 084.02132.0031 83.01221.R70
MASK_BASE_LEDS# 2nd = 84.02143.011 2nd = 083.00110.0070 74LVC1G08GW-1-GP
84.2N702.J31 73.01G08.L04
2ND = 84.2N702.031 R1=R2=4.7K
3rd = 84.2N702.W31 2ND = 73.01G08.EHG
3rd = 73.7SZ08.DAH

Battery LED2(White_LED) 1
R6115
2
LOW actived from KBC GPIO 0R0402-PAD-2-GP
5V_S5

Q6109 R2
Q6104 E
LED_BATCHG R6104
1 6 B
24 BAT2_LED# R1
C BAT_WHITE_LED_A_R 1 2
WHITE
MASK_BASE_LEDS# 2 5 MASK_BASE_LEDS# CHLED1
LMUN2132LT1G-GP 330R2J-3-GP
3 4
BAT1_LED# 24
084.02132.0031
2nd = 84.02143.011 BAT_WHITE_LED_A 2
5V_S5 + White
3
2N7002KDW-GP -
BAT_AMBER_LED_A 1
84.2N702.A3F Q6115
+ Yellow

2nd = 84.DMN66.03F R2
E
LED_BATLOW B R6105 LED-YW-5-GP
R1
C BAT_AMBER_LED_A_R 1 2 083.1212A.0070
2ND = 083.00327.0070
LMUN2132LT1G-GP 680R2J-3-GP
Battery LED1(Orange_LED) 084.02132.0031 Yellow
2nd = 84.02143.011
LOW actived from KBC GPIO
C C

WLAN LED 99 WIRELESS_LED#

LOW actived from KBC GPIO

3D3V_S5_WLAN 5V_S5
Q6106 Q6107
1 6 WIRELESS_LED# S Q6108 WLED1
58 WLAN_LED# R2
E

3
R6107 1 2 100KR2J-1-GP WLAN_LED# 2 5 D WIRELESS_LED#_D B R6106
3D3V_S5_WLAN 3D3V_S5_WLAN R1
C WLAN_LED_R 1 2 WLAN_LED_A 1A 2K
R6108 1 2 100KR2J-1-GP BT_LED# 3 4 G
BT_LED# 58 LMUN2132LT1G-GP 150R2J-L1-GP-U LED-W-27-GP-U
2N7002KDW-GP 084.02132.0031 83.01221.R70
2N7002K-2-GP
84.2N702.A3F 84.2N702.J31 2nd = 84.02143.011 2nd = 083.00110.0070
2nd = 84.DMN66.03F 2ND = 84.2N702.031 R1=R2=4.7K
3D3V_S5_WWAN MASK_BASE_LEDS#
3rd = 84.2N702.W31

R6109 1 2 100KR2J-1-GP LED_WWAN_OUT# R6114

2 DY 1

0R2J-2-GP
5V_S5
Q6114
S Q6113 R2
E NETWK1
D WIRELESS_LED_C# B R6113 3
R1
C WIFI_CASEA_LED#_R 1 2 WIFI_CASEA_LED#_A 1
Q6110 G 150R2J-L1-GP-U
S LMUN2132LT1G-GP AFTP6103 1 2
59 LED_WWAN_OUT#
2N7002K-2-GP 084.02132.0031 4
D
99 MASK_ACASE_WIFI_LED# 84.2N702.J31 2nd = 84.02143.011
R1=R2=4.7K ACES-CON2-20-GP-U
B Power LED 3D3V_S5_WWAN G 2ND = 84.2N702.031
3rd = 84.2N702.W31 20.F1639.002 B
2nd = 20.F1841.002
LOW actived from KBC GPIO 2N7002K-2-GP
84.2N702.J31
2ND = 84.2N702.031
5V_S5 3rd = 84.2N702.W31
Q6111
S Q6112 PLED1 WIFI_CASEA_LED#_A 1
24 BREATH_LED# R2
AFTP6102
E
3

D BREATH_LED#_D B R6110
R1
C BREATH_LED#_C 1 2 BREATH_LED1#_A 1A 2K
MASK_BASE_LEDS# G
LMUN2132LT1G-GP 150R2J-L1-GP-U LED-W-27-GP-U
2N7002K-2-GP 084.02132.0031 83.01221.R70
84.2N702.J31 2nd = 84.02143.011 2nd = 083.00110.0070
2ND = 84.2N702.031 R1=R2=4.7K
3rd = 84.2N702.W31

Already reseve on EC side

POWER BUTTON LED POWER BUTTON
SWLED1 R6103
MB_PWR_BTN#_R 1 2 MB_PWR_BTN# 17,24
R6111 1 2 680R2J-3-GP BREATH_SWLED1#_A A K 0R0402-PAD-2-GP
LED-W-45-GP
83.19213.H70

PWRBT1
1 2 MB_PWR_BTN#_R 1
AFTP6101

1
5 6 EC6101
A DY SC1KP50V2KX-1GP A

2
3 4

SW-TACT-4P-7-GP
62.40009.A91
A00 <Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

LED
Size Document Number Rev

Round Rock MLK 13.3" A00

Date: Wednesday, August 19, 2015 Sheet 61 of 110
5 4 3 2 1
 5 4 3 2 1

SSID = KBC SSID = Touch.Pad

3D3V_TP
RN6201
DAT_TP_SIO_R
1
2
4
3 CLK_TP_SIO_R TouchPad Connector
SRN4K7J-8-GP

D TPAD1 D
9

2
3
3D3V_TP 4
5
R6201 1 2 0R0402-PAD-2-GP DAT_TP_SIO_R 6
24 DAT_TP_SIO
R6202 1 2 0R0402-PAD-2-GP CLK_TP_SIO_R 7
24 CLK_TP_SIO
8

10

ACES-CON8-35-GP

1
C6201
SC33P50V2JN-3GP

C6202
SC33P50V2JN-3GP
20.K0529.008
DY DY 2nd = 20.K0392.008

2
3D3V_S0 3D3V_S0 3D3V_TP

R6203 1 2 0R0603-PAD-2-GP-U

C6203
SC1U6D3V2KX-GP

C6204
SCD1U16V2KX-3GP

C6205
SCD1U16V2KX-3GP
1

1
R6204
10KR2J-3-GP DY DY
2

2
U6201
2

9
GND CLK_TP_SIO_R
1 8 AFTP6205 1
VIN#1 VOUT#8 DAT_TP_SIO_R
VIN#2DY
2 7 AFTP6206 1
R6205 1 3.3V_TP_EN_R VOUT#7 3D3V_TP_CT 3D3V_TP
15,20 3.3V_TP_EN DY 2 0R2J-2-GP 3 6 AFTP6208 1
ON CT

C6207
SC220P50V2JN-3GP
5V_S5 4 5

1
VBIAS GND
C
TPS22965DSGR-GP-U
DY C

2
74.22965.093
CT Pin: Use 16V+ cap.

KBC SMSC ECE1117c

Layout:
Close each VCC pin. U6202

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
1 2 1117C_VCC 4 11 KSO0
3D3V_S5 VCC KSO00

SCD1U16V2KX-3GP
24 13 KSO1
R6207 VCC KSO01

2
37 12 KSO2
0R0402-PAD-2-GP VCC KSO02

C6209

C6210
KSO3

C6208
14
KSO03 KSO4
MB Pin NO. Description Module Pin NO. 16

1
KSO04 KSO5
17
KSO05 KSO6
15
KSO06 KSO11
32 Diagnostic 1 38
39
GPIO10
GPIO11
KSO11
KSO12
5
10 KSO12
40 7 KSO13
31 KSI[7]:S8 2 CAP_LED# 41
GPIO12/PWM1
GPIO13/PWM2
KSO13
KSO14
6 KSO14
F4_LED# 42 8 KSO15
30 KSI[6]:S7 3 43
GPIO14/PWM3
GPIO15/PWM4
KSO15
KSO16
9 KSO16
44 3 KSO17
29 KSI[4]:S5 4 3D3V_S5
GPIO20/PWM7 KSO17
GPIO01/KSO18
2 KSO18
1 KSO19
28 KSI[2]:S3 5 GPIO00/KSO19
GPIO23/KSO20/PWM8
47 KSO20
46
27 KSI[5]:S6 6 GPIO22/KSO21/PWM9
GPIO21/KSO22
45

B
26 KSI[1]:S2 7 B

25 KSI[3]:S4 8 31

10KR2J-3-GP

10KR2J-3-GP
1

1
GPIO04/TP_DAT
30
GPIO03/TP_CLK
24 KSI[0]:S1 9

R6206

R6208
DY DY
Internal KeyBoard Connector 23 KSO[5]:D6 10 BC link
36
35
GPIO07/PS2_DAT
GPIO06/PS2_CLK

2
22 KSO[4]:D5 11
KB1 34
21 KSO[11]:D8 12 24
24
BC_DAT_ECE1117
BC_CLK_ECE1117 33
BC_DAT_UP/SMB_DAT_UP
BC_CLK_UP/SMB_CLK_UP KSI0
18 KSI0
34 1 AFTP6210 32 20 KSI1
20 KSO[6]:D7 13 24 BC_INT#_ECE1117 BC_INT_UP#/SMB_INT_UP# KSI1
KSI2
23 KSI2
32 19 KSI3
31 KSI7
KSI6
1
KB_DET#
AFTP6211
16,20
19 KSO[12]:D9 14 Pin28 SMBus Address select strap pin. R6209
2 1
10KR2J-3-GP
KBC_SMB_ADDR 28
SMB_ADDR
KSI3
KSI4
25 KSI4
KSI5
30 1 AFTP6212 48 22
29
28
KSI4
KSI2
1
1
AFTP6213 18 KSO[3]:D4 15 10K pull ground=0111 000b
10K pull VCC=0111 001b R6210
2 DY 1
10KR2J-3-GP
KBC_TEST_PIN 29
OCS_TRM
TEST_PIN
KSI5
KSI6
26
27
KSI6
KSI7
AFTP6214 KSI7
27
26
KSI5
KSI1
1
1
AFTP6215 17 KSO[1]:D2 16 ECE1117_VR_CAP 1 2 1117_VRCAP_R 21
AFTP6216 Pin29 has a weak internal pull-down VR_CAP
25
24
KSI3
KSI0
1
1
AFTP6217 16 KSO[2]:D3 17 R6211
49
AFTP6218 15R2J-GP GND
23 KSO5
KSO4
1 AFTP6219 15 KSO[0]:D1 18

1
22 1 AFTP6220
KSO11
21 1 AFTP6221 14 KSO[16]:D13 19 C6211
ECE1117-HZH-1-TR-GP-U
20 KSO6
KSO12
1 AFTP6222 SC4D7U6D3V3KX-GP X01 071.01117.0003

2
19
18 KSO3
1
1
AFTP6223
AFTP6224
13 KSO[20]:D17 20
17 KSO1 1
16 KSO2 1
AFTP6225
AFTP6226
12 KSO[19]:D16 21
15 KSO0 1
14 KSO16 1
AFTP6227
AFTP6228
11 KSO[17]:D14 22
13 KSO20 1
12 KSO19
KSO17
1
AFTP6229
AFTP6230
10 KSO[18]:D15 23
11 1 AFTP6231
10 KSO18
KSO13
1 AFTP6232 9 KSO[13]:D10 24
9 1 AFTP6233
8
7
KSO15
KSO14
1
1
AFTP6234 8 KSO[15]:D12 25
AFTP6235
6
5
7 KSO[14]:D11 26
A A
4
3 CAP_LED_R
6 NC 27
5V_S0 CAP_LED_R 5V_S0 F4_LED_R
2
5 NC 28
Q6201 Q6202
1 F4_LED_R 4 GND 29 R2
E
R2
E
33 CAP_LED# B R6213 F4_LED# B R6217 <Core Design>
3 Caps Lock LED 30 R1
C CAP_LED#_Q1 2
R1
C F4_LED#_Q 1 2

ACES-CON32-11-GP 2 GND 31 LMUN2132LT1G-GP 680R2J-3-GP LMUN2132LT1G-GP 680R2J-3-GP Wistron Corporation

020.K0013.0032 084.02132.0031 084.02132.0031 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
1 F4 LED 32 2nd = 84.02143.011 2nd = 84.02143.011 Taipei Hsien 221, Taiwan, R.O.C.
R1=R2=4.7K R1=R2=4.7K
Title

1
R6214
DY 2
100R2J-2-GP R6216
1 DY 2
100R2J-2-GP
Key Board/Touch Pad
Size Document Number Rev

Round Rock MLK 13.3" A00

Date: Monday, August 17, 2015 Sheet 62 of 110
5 4 3 2 1
 5 4 3 2 1

D D

C
(Blanking) C

B B

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

IO CONN
Size Document Number Rev
A4 A00
Round Rock MLK 13.3"
Date: Monday, August 17, 2015 Sheet 63 of 110
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

(Reserved)Hall Sensor
Size Document Number Rev
Round Rock MLK 13.3" A00
Date: Monday, August 17, 2015 Sheet 64 of 110
5 4 3 2 1
 5 4 3 2 1

SSID = DEBUG PORT

D D

C C
3D3V_S0 DB1
11
1

18,24 LPC_LAD0 2
18,24 LPC_LAD1 3
18,24 LPC_LAD2 4
18,24 LPC_LAD3 5
18,24 LPC_LFRAME# 6
17,24,88 PCH_PLTRST#_EC 7
8
18 CLK_PCI_DEBUG 9
10
12

PAD-10P-177042-GP

ZZ.00PAD.Y41
B B
A00

<Core Design>

Wistron Corporation
A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, A
Taipei Hsien 221, Taiwan, R.O.C.

Title

Debug connector
Size Document Number Rev
Round Rock MLK 13.3" A00
Date: Monday, August 17, 2015 Sheet 65 of 110
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A DLP10 A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
SENSOR
Size Document Number Rev
A3
Round Rock MLK 13.3" A00
Date: Monday, August 17, 2015 Sheet 66 of 110
5 4 3 2 1
 5 4 3 2 1

SSID = User.interface

Note
D - no via, trace, under the sensor (keep out area around 2mm) D
- stay away from the screw hole or metal shield soldering joints
- design PCB pad based on our sensor LGA pad size (add 0.1mm)
Free Fall Sensor - solder stencil opening to 90% of the PCB pad size
- mount the sensor near the center of mass of the NB as possible as you can
3D3V_S0

11 uA
R6701
2 1 3D3V_RUN_FFS
0R0603-PAD-2-GP-U
C6701

3D3V_S0

C6703
SC10U6D3V3MX-GP
1

1
C6702
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP

DY

1
U6701 R6702
2

DY
10KR2J-3-GP
9 VDD CS 2
5

2
RES
10 VDD_IO
12 FFS_PCH_INT
INT1 FFS_PCH_INT 15
INT2 11

12,13,18,96 PCH_SMBCLK 1 SCL/SPC

12,13,18,96 PCH_SMBDATA 4 SDA/SDI/SDO GND 6
C
3D3V_RUN_FFS 3 7 C
SDO/SA0 GND 3D3V_S0
GND 8

1
LNG2DMTR-GP
R6703
074.LNG2D.00BZ 100KR2J-1-GP

2
FALL_INT2

Q6701

1
Note 3D3V_S0 2N7002KDW -GP 5V_S0
(1) Keep all signals are the same trace width. (included VDD, GND). 84.2N702.A3F
(2) No VIA under IC bottom. 2nd = 84.DMN66.03F

1
4

6
R6705
100KR2J-1-GP
DY R6704
100KR2J-1-GP
DY

2
FFS_INT2
PCH 20 FFS_INT2 FFS_INT2_Q 56 HDD
1 2 R6706
DY 0R2J-2-GP

1
B B
R6707
1MR2J-1-GP

2
Vender suggest,reserve to prevent error trigger

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Free Fall Sensor

Size Document Number Rev
A3 A00
Round Rock MLK 13.3"
Date: Monday, August 17, 2015 Sheet 67 of 110
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Thunderbolt (1/5)
Size Document Number Rev
A3
Round Rock MLK 13.3" A00
Date: Monday, August 17, 2015 Sheet 68 of 110
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
A Taipei Hsien 221, Taiwan, R.O.C. A

Title

Thunderbolt (2/5)
Size Document Number Rev
A
Round Rock MLK 13.3" A00
Date: Monday, August 17, 2015 Sheet 69 of 110
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
A Taipei Hsien 221, Taiwan, R.O.C. A

Title

Thunderbolt (3/5)
Size Document Number Rev
A
Round Rock MLK 13.3" A00
Date: Monday, August 17, 2015 Sheet 70 of 110
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
A Taipei Hsien 221, Taiwan, R.O.C. A

Title

Thunderbolt (4/5)
Size Document Number Rev
A
Round Rock MLK 13.3" A00
Date: Monday, August 17, 2015 Sheet 71 of 110
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
A Taipei Hsien 221, Taiwan, R.O.C. A

Title

Thunderbolt (5/5)
Size Document Number Rev
A
Round Rock MLK 13.3" A00
Date: Monday, August 17, 2015 Sheet 72 of 110
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
A Taipei Hsien 221, Taiwan, R.O.C. A

Title

GPU (1/5) PEG

Size Document Number Rev
A
Round Rock MLK 13.3" A00
Date: Monday, August 17, 2015 Sheet 73 of 110
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
A Taipei Hsien 221, Taiwan, R.O.C. A

Title

GPU (2/5) DIGITAL

Size Document Number Rev
A
Round Rock MLK 13.3" A00
Date: Monday, August 17, 2015 Sheet 74 of 110
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
A Taipei Hsien 221, Taiwan, R.O.C. A

Title

GPU (3/5) VRAM

Size Document Number Rev
A
Round Rock MLK 13.3" A00
Date: Monday, August 17, 2015 Sheet 75 of 110
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
A Taipei Hsien 221, Taiwan, R.O.C. A

Title

GPU (4/5) GPIO

Size Document Number Rev
A
Round Rock MLK 13.3" A00
Date: Monday, August 17, 2015 Sheet 76 of 110
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
A Taipei Hsien 221, Taiwan, R.O.C. A

Title

GPU (5/5) PWR/GND

Size Document Number Rev
A
Round Rock MLK 13.3" A00
Date: Monday, August 17, 2015 Sheet 77 of 110
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
A Taipei Hsien 221, Taiwan, R.O.C. A

Title

VRAM1,2 (1/4)
Size Document Number Rev
A
Round Rock MLK 13.3" A00
Date: Monday, August 17, 2015 Sheet 78 of 110
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
A Taipei Hsien 221, Taiwan, R.O.C. A

Title

VRAM3,4 (2/4)
Size Document Number Rev
A
Round Rock MLK 13.3" A00
Date: Monday, August 17, 2015 Sheet 79 of 110
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
A Taipei Hsien 221, Taiwan, R.O.C. A

Title

VRAM5,6 (3/4)
Size Document Number Rev
A
Round Rock MLK 13.3" A00
Date: Monday, August 17, 2015 Sheet 80 of 110
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
A Taipei Hsien 221, Taiwan, R.O.C. A

Title

VRAM7,8 (4/4)
Size Document Number Rev
A
Round Rock MLK 13.3" A00
Date: Monday, August 17, 2015 Sheet 81 of 110
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
A Taipei Hsien 221, Taiwan, R.O.C. A

Title

VGA_CORE
Size Document Number Rev
A
Round Rock MLK 13.3" A00
Date: Monday, August 17, 2015 Sheet 82 of 110
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
A Taipei Hsien 221, Taiwan, R.O.C. A

Title

DISCRETE VGAPOWER
Size Document Number Rev
A
Round Rock MLK 13.3" A00
Date: Monday, August 17, 2015 Sheet 83 of 110
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
A Taipei Hsien 221, Taiwan, R.O.C. A

Title

Switchable GFXLCD
Size Document Number Rev
A
Round Rock MLK 13.3" A00
Date: Monday, August 17, 2015 Sheet 84 of 110
5 4 3 2 1
 D

A00
Wistron Corporation

Rev

110
3D3V_S5_WLAN

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

5V_S0
5V_S5

1 2
Round Rock MLK 13.3"
Taipei Hsien 221, Taiwan, R.O.C.

1 2
EC8555
of

EC8531 SC18P50V2JN-1-GP
5V_S5

SCD1U25V2KX-GP 1 2
3D3V_S5_WWAN
1

1
5V_S5

EC8556
85
EMI Capacitors1

1 2
SC120P50V2JN-1GP
3D3V_S5_WWAN

3D3V_S5

Sheet

EC8530 1 2
SCD1U25V2KX-GP
5V_S5

1 2 EC8554
1 2 SC120P50V2JN-1GP
DCBATOUT

EC8553
3D3V_S5

EC8529 SC120P50V2JN-1GP
3D3V_S5

1 2
SCD1U25V2KX-GP
5V_S0

1 2
5V_S5

1 2
Date: Monday, August 17, 2015

EC8514 1 2 EC8551
SCD1U25V2KX-GP
EC8552 SC120P50V2JN-1GP
Document Number
3D3V_S5

SC120P50V2JN-1GP
1 2 EC8528
SCD1U25V2KX-GP
3D3V_S0
3D3V_S0

3D3V_S5
5V_S5

1 2 1 2
EC8513 1 2
SCD1U25V2KX-GP
<Core Design>

EC8550 EC8548
3D3V_S5

SC120P50V2JN-1GP SC120P50V2JN-1GP
EC8527
DCBATOUT 3D3V_S5_WLAN

3D3V_S0
3D3V_S5

1 2
SCD1U25V2KX-GP
2

2
A4
5V_S5

1 2
Size
Title

EC8512 1 2
SCD1U25V2KX-GP 1 2 EC8547
SC120P50V2JN-1GP
3D3V_S5

EC8526 EC8549
3D3V_S0
3D3V_S5

1 2
SCD1U25V2KX-GP SC120P50V2JN-1GP 1 2
5V_S5

EC8511 1 2 EC8546
SCD1U25V2KX-GP 1 2
SC18P50V2JN-1-GP
3D3V_S0

3D3V_S0
3D3V_S5

1 2 EC8525 EC8539
SCD1U25V2KX-GP SC120P50V2JN-1GP 1 2
DCBATOUT
5V_S5

EC8508 1 2 EC8545
SCD1U25V2KX-GP 1 2 SC120P50V2JN-1GP
DCBATOUT

3D3V_S0
3D3V_S5

EC8524 EC8538 1 2
SCD1U25V2KX-GP SC120P50V2JN-1GP
DCBATOUT

1 2
5V_S5

EC8544
1 2 SC18P50V2JN-1-GP
EC8510 1 2
SCD1U25V2KX-GP

3D3V_S5_WWAN
EC8522 EC8537
DCBATOUT
3

3
SCD1U25V2KX-GP SC120P50V2JN-1GP
DCBATOUT
5V_S5

3D3V_S5
1 2
1 2
1 2 1 2
EC8507
SCD1U25V2KX-GP EC8521 EC8536 EC8543
SCD1U25V2KX-GP SC120P50V2JN-1GP SC120P50V2JN-1GP
DCBATOUT

DCBATOUT

3D3V_S5_WWAN
5V_S5

1 2 1 2
1 2

3D3V_S5
EC8506 EC8520 EC8535
3D3V_S5_WWAN

SCD1U25V2KX-GP SCD1U25V2KX-GP SC120P50V2JN-1GP 1 2

DCBATOUT
5V_S0

1 2 EC8542
1 2
1 2 SC18P50V2JN-1-GP
EC8509 EC8534
SCD1U25V2KX-GP EC8519 SC120P50V2JN-1GP
5V_S0

DCBATOUT DCBATOUT

1D05V_S0
SCD1U25V2KX-GP

3D3V_S5
1 2
3D3V_S5_WWAN

1 2
1 2
EC8505
4

4
EC8541
SCD1U25V2KX-GP EC8533
SC120P50V2JN-1GP
1D35V_S3

SC120P50V2JN-1GP

1D05V_S0
1 2

3D3V_S5
1 2
1 2 1 2
EC8518
EC8504 SCD1U25V2KX-GP
EC8532 EC8540
SCD1U25V2KX-GP
SC120P50V2JN-1GP SC18P50V2JN-1-GP
1D35V_S3

1 2 3D3V_S5 1 2

X02
RF
EC8503 EC8517
SCD1U25V2KX-GP SCD1U25V2KX-GP
1D35V_S3

3D3V_S5

Near U5501
1 2 1 2

1D35V_S3
EC8502 EC8516
SCD1U25V2KX-GP SCD1U25V2KX-GP 1 2
1D35V_S3

3D3V_S5
1 2 1 2 EC8523
SCD1U25V2KX-GP
5

5
EC8501 EC8515
SCD1U25V2KX-GP SCD1U25V2KX-GP
D

A
 5 4 3 2 1

DCBATOUT DCBATOUT DCBATOUT DCBATOUT DCBATOUT DCBATOUT DCBATOUT DCBATOUT DCBATOUT DCBATOUT DCBATOUT DCBATOUT DCBATOUT DCBATOUT DCBATOUT
DCBATOUT 3D3V_S5

1
EC8625
SCD1U25V2KX-GP

EC8626
SCD1U25V2KX-GP

EC8627
SCD1U25V2KX-GP

EC8628
SCD1U25V2KX-GP

EC8629
SCD1U25V2KX-GP

EC8630
SCD1U25V2KX-GP

EC8607
SCD1U25V2KX-GP

EC8608
SCD1U25V2KX-GP

EC8609
SCD1U25V2KX-GP

EC8610
SCD1U25V2KX-GP

EC8601
SCD1U25V2KX-GP

EC8602
SCD1U25V2KX-GP

EC8603
SCD1U25V2KX-GP

EC8604
SCD1U25V2KX-GP

EC8605
SCD1U25V2KX-GP
EC8612 DY
1 2

2
D SCD1U25V2KX-GP D

5V_S5 5V_S5 5V_S5 5V_S5 5V_S5 5V_S5 3D3V_S0 3D3V_S5 3D3V_S0_HDD USB30_VCCB VCC_CORE VCC_CORE AD+ DCBATOUT_LCD

1
EC8613
SCD1U25V2KX-GP

EC8614
SCD1U25V2KX-GP

EC8615
SCD1U25V2KX-GP

EC8616
SCD1U25V2KX-GP

EC8617
SCD1U25V2KX-GP

EC8619
SCD1U25V2KX-GP

EC8620
SCD1U25V2KX-GP

EC8621
SCD1U25V2KX-GP

EC8622
SCD1U25V2KX-GP

EC8618
SCD1U25V2KX-GP

EC8623
SCD1U25V2KX-GP

EC8624
SCD1U25V2KX-GP

EC8606
SCD1U25V2KX-GP

EC8611
SCD1U25V2KX-GP
DY

2
H7 H8
C H1 H2 H3 H4 H5 H6 H9 G1 G2 C
GNDPAD GNDPAD

1
1
1

1
ZZ.NDPAD.XXX ZZ.NDPAD.XXX
HOLE335R115-GP HOLE335R115-GP HOLE335R115-GP HOLE335R115-GP HOLE335R115-GP HOLE335R115-GP HOLE335R115-GP
ZZ.HOLEX.XX2 ZZ.00PAD.D01 ZZ.HOLEX.XX6 ZZ.HOLEX.XX3 ZZ.00PAD.D01 ZZ.00PAD.D01 HT10X10BE10R32-D-5-GP HT85B95X975R29-S-GP ZZ.00PAD.D01
ZZ.00PAD.J91 ZZ.HOLEX.XX1
EV ME
H10 H11 H12 H13 H14

EMI RF
B B
1

SPR1 SPR2 SPR3 SPR10 SPR4 SPR8

SPR7
SPRING-157-GP SPRING-157-GP SPRING-157-GP SPRING-157-GP SPRING-64-GP SPRING-64-GP
SPRING-157-GP
HOLE197R166-1-GP HOLE197R166-1-GP HOLE197R166-1-GP
ZZ.00PAD.V71 ZZ.00PAD.V71 ZZ.00PAD.V71 HOLE197R99-1-GP HOLE197R99-1-GP DY
ZZ.HOLEX.XX5 ZZ.HOLEX.XX4
1

1
1
HS1 HS2 H15
STF236R128H101-3-GP STF237R113H62-4-GP

34.4YW17.001 34.4YW17.001 34.4YW17.001 34.4YW17.001

34.4H602.001 34.4YW17.001 34.4H602.001
1
1

SPR5 SPR6 SPR9 <Core Design>

SPRING-64-GP SPRING-64-GP SPRING-64-GP

A
HOLE197R99-1-GP
ZZ.HOLEX.XX5 DY DY
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
34.4YG18.001 34.4SE26.001
1

1
Taipei Hsien 221, Taiwan, R.O.C.
2ND = 34.4YG18.101 2ND = 34.4SE26.101
3rd = 34.4YG18.201 3rd = 34.4SE26.201 Title

EMI Capacitors2
Size Document Number Rev
34.4H602.001 34.4H602.001 34.4H602.001 Round Rock MLK 13.3" A00
Date: Monday, August 17, 2015 Sheet 86 of 110
5 4 3 2 1
 A B C D E

SSID = USH

4 4

3 3

(Blanking)

2 2

<Variant Name>

1
Wistron Corporation 1
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
USH Board Connector
Size Document Number Rev
A4 Round Rock MLK 13.3" A00
Date: Monday, August 17, 2015 Sheet 87 of 110
A B C D E
 5 4 3 2 1

SSID = TPM

D D

3D3V_TPM

51 mA

2
R8816 R8813
3D3V_S5_PCH 1 2 0R2J-2-GP 10KR2J-3-GP
DY EV Reseved for modern stanby DY
3D3V_TPM R8814 1 DY 2 10KR2J-3-GP TPM_GPIO2 3D3V_S5 1 2 0R2J-2-GP TPM_VSB

C8806
SCD1U16V2KX-3GP

C8807
SC2200P50V2KX-2GP

1
R8815
X02

1
2 DY 1
17 SIO_SLP_S0#
Measure power consumption on EV board R8817

2
0R2J-2-GP
U8801
3D3V_M
3D3V_TPM 1 29 TPM_GPIO0
C VSB GPIO0/SDA/XOR_OUT C
GPIO1/SCL 30
3 TPM_GPIO2
R8801 1 GPX/GPIO2
2 0R2J-2-GP 8 VDD GPIO3/BADD 6
14 13 TPM_GPIO4
VDD CLKRUN#/GPIO4/SINT#

C8801
SCD1U16V2KX-3GP

C8802
SC2200P50V2KX-2GP

C8803
SC2200P50V2KX-2GP

C8804
SC2200P50V2KX-2GP
22 VDD LPCPD# 28
1

1
PP 4
84.02130.031 only for layout SPI_SO_ROM_TPM 24
2

2
SPI_SI_ROM_TPM LAD0/MISO
R8806 21 LAD1/MOSI NC#2 2
3D3V_TPM 2 1 SPI_IRQ# 18 7
DY LAD2/SPI_IRQ# NC#7
3D3V_TPM 15 LAD3 NC#10 10
84.02130.031 10KR2J-3-GP 11
SPI_CLK_ROM_TPM NC#11
Q8801 2ND = 84.00102.031 19 25
PCH_SPI_CS2#_R LCLK/SCLK NC#25
DMP2130L-7-GP 20 LFRAME#/SCS# NC#26 26
3rd = 84.03413.B31 17 31
17,24,65 PCH_PLTRST#_EC SERIRQ_TPM SRESET#/LRESET#/SPI_RST# NC#31
27 SERIRQ
S
D TPM_GPIO2

1
9
D

GND
5 16
G

R8805 TEST GND

1

10KR2J-3-GP 12 RESERVED GND 23

B B
PCH_SPI_CS2#_Q G

R8809 GND 32
10KR2J-3-GP 3D3V_TPM GND 33

2
NPCT650JA0YX-GP
2

R8807 071.00650.0B03
10KR2J-3-GP
2

PCH_SPI_CS2#_R 2 TPM_GPIO4
2

1
R8812
R8811 DY 0R2J-2-GP
100R2J-2-GP

PCH_SPI_CS2#_R
1

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
18,25 PCH_SPI_SO
R8802 1 2 33R2J-2-GP SPI_SO_ROM_TPM Taipei Hsien 221, Taiwan, R.O.C.

18,25 PCH_SPI_SI
R8803 1 2 33R2J-2-GP SPI_SI_ROM_TPM Title
R8804 1 2 33R2J-2-GP SPI_CLK_ROM_TPM
18,25 PCH_SPI_CLK
R8808 1 2 0R2J-2-GP PCH_SPI_CS2#_R TPM
18 PCH_SPI_CS2# Size Document Number Rev
Round Rock MLK 13.3" A00
Date: Monday, August 17, 2015 Sheet 88 of 110
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
A Taipei Hsien 221, Taiwan, R.O.C. A

Title

Finger Print
Size Document Number Rev
A
Round Rock MLK 13.3" A00
Date: Monday, August 17, 2015 Sheet 89 of 110
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
NFC Connector
Size Document Number Rev
A4
Round Rock MLK 13.3" A00
Date: Monday, August 17, 2015 Sheet 90 of 110
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
Smart Card
Size Document Number Rev
Round Rock MLK 13.3" A00
Date: Monday, August 17, 2015 Sheet 91 of 110
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
A Taipei Hsien 221, Taiwan, R.O.C. A

Title

Reserved
Size Document Number Rev
A
Round Rock MLK 13.3" A00
Date: Monday, August 17, 2015 Sheet 92 of 110
5 4 3 2 1
 5 4 3 2 1

SSID = Docking

D D

C C

(Blanking)

B B

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
DOCKING
Size Document Number Rev
A4
Round Rock MLK 13.3" A00
Date: Monday, August 17, 2015 Sheet 93 of 110
5 4 3 2 1
 5 4 3 2 1

D D

C (Blanking) C

B B

<Core Design>

Wistron Corporation
A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, A
Taipei Hsien 221, Taiwan, R.O.C.

Title

(Reserved)
Size Document Number Rev
A4 A00
Round Rock MLK 13.3"
Date: Monday, August 17, 2015 Sheet 94 of 110
 5 4 3 2 1

D D

C
(Blanking) C

B B

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

LAN SW
Size Document Number Rev
A4 A00
Round Rock MLK 13.3"
Date: Monday, August 17, 2015 Sheet 95 of 110
5 4 3 2 1
 5 4 3 2 1

SSID = CPU_XDP

D D

6 CFG[19:0]
CPU_XDP
XDP1
3D3V_S5 NP1
61
1 2
62
1

3 4 CFG17
R9601 4 XDP_PREQ# CFG16
4 XDP_PRDY# 5 6
DY 1KR2J-1-GP CFG0
7 8
CFG8
9 10
CFG1 11 12 CFG9
2

13 14
H_SYS_PW ROK_XDP CFG2 15 16 CFG10 EV
CFG3_XDP R9602 1 XDP 2 1KR2J-1-GP CFG3 17 18 CFG11 1D05V_S0
C9601
SCD1U16V2KX-3GP

19 20
1

C XDP_BPM0 21 22 CFG19 3D3V_S0 C

DY 4 XDP_BPM0
XDP_BPM1 23 24 CFG18
1D05V_S0 4 XDP_BPM1

C9602
SCD1U16V2KX-3GP
25 26
2

1
CFG4 27 28 CFG12
CFG5 29 XDP 30 CFG13 XDP

1
31 32

2
CFG6 33 34 CFG14 R9603
C9603
SCD1U16V2KX-3GP

CFG7 35 36 CFG15 1KR2J-1-GP

1

37 38
XDP R9604 1 XDP 2 1KR2J-1-GP H_CPUPW RGD_XDP 39 40
7,36 H_VCCST_PW RGD

2
R9605 1 XDP 2 0R2J-2-GP PM_PW RBTN#_XDP 41 42
2

17 PM_PW RBTN#_R
43 44
R9606 1 XDP 2 1KR2J-1-GP XDP_HOOK2 45 46 XDP_RST#_R R9607 1 XDP 2 1KR2J-1-GP
7 PW R_DEBUG PLTRST_XDP# 17
R9608 1 XDP 2 0R2J-2-GP H_SYS_PW ROK_XDP 47 48 XDP_DBRESET# R9620 1 2
17,24 SYS_PW ROK SYS_RESET# 17
49 50 0R0402-PAD-2-GP
R9609 1 XDP 2 0R2J-2-GP SML0_DATA_XDP 51 52
12,13,18,67 PCH_SMBDATA XDP_TDO 4
R9610 1 XDP 2 0R2J-2-GP SML0_CLK_XDP 53 54
12,13,18,67 PCH_SMBCLK XDP_TRST# 4,19
XDP_TCK1 55 56 R9611 1 DY 2 0R2J-2-GP
XDP_TDI 4 CPU_XDP_TDO_PCH 19
R9612 1 XDP 2 0R2J-2-GP XDP_TCK_R 57 58 XDP_TDI R9613 1 DY 2 0R2J-2-GP
4 XDP_TCK CFG3_XDP XDP_TMS 4
59 60
63
64 R9614 1 DY 2 0R2J-2-GP CPU_XDP_TDI_PCH 19
CAD Note: The resistor for NP2 R9615 1 DY 2 0R2J-2-GP CPU_XDP_TMS_PCH 19
XDP_DBRESET#
HOOK2 (pin45) should be

C9604
SCD1U16V2KX-3GP
placed such that the stub is PAD-60P-GP

1
very small on CFG0 net ZZ.00PAD.Q81 XDP
PHYSICAL_DEBUG_ENABLED (DFX PRIVACY)

2
B 3D3V_S5
A00 0:Enable
B
AFTP9601 1 XDP_TCK CFG3 SET DFX ENABLED BIT IN DEBUG INTERFACE MSR
AFTP9602 1 XDP_TCK1 1:Disable
1

R9616
DY 1KR2J-1-GP XDP_TCK1 R9617 1 DY 2 0R2J-2-GP PCH_JTAG_TCK 19
R9618 1 DY 2 0R2J-2-GP
2

PM_PW RBTN#_XDP XDP_TCK_R R9619 1 DY 2 0R2J-2-GP PCH_JTAGX 19

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU_XDP
Size Document Number Rev
A3 A00
Round Rock MLK 13.3"
Date: Monday, August 17, 2015 Sheet 96 of 110
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

USB2.0 HUB
Size Document Number Rev
A4 A00
Round Rock MLK 13.3"
Date: Monday, August 17, 2015 Sheet 97 of 110
5 4 3 2 1
 5 4 3 2 1

SSID = User.Interface TOUCH PANEL POWER

84.02130.031 only for layout
5V_TSP 5V_TSP_S0
3D3V_S0 Q9801
5V_S0 84.02130.031
DMP2130L-7-GP
R9809
2ND = 84.00102.031
3rd = 84.03413.B31 S R9806
1 2 TOUCH_PANEL_INTR#
D 2 1

D
C9810

1
G
10KR2J-3-GP SC10U6D3V3MX-GP POLYSW -1D5A6V-12-GP
D D

SCD1U16V2KX-3GP
069.50001.0031 C9812

G
1
2ND = 069.50001.0071 SC10U10V5KX-2GP

2
1

100KR2J-1-GP
R9808
C9811
DY

2
TOUCH PANEL CONNECTOR R9807 1 2 0R0402-PAD-2-GP 3.3V_TS_EN_R G
Q9802

15,20 3.3V_TS_EN
5V_TSP_S0 D 3.3V_TS_EN#

TOUCH1 S
7
2N7002K-2-GP
1
84.2N702.J31
2 2ND = 84.2N702.031
3 TOUCHLCD_N 3rd = 84.2N702.W31
4 TOUCHLCD_P
5
6 TOUCH_PANEL_INTR# 20

8 1 AFTP9805
TOUCHLCD_N
TOUCHPANEL_N 16
C
ACES-CON6-20-GP-U C
20.F1639.006
2ND = 20.F1804.006
EV ME 5V_TSP_S0 TR9801
3 2
U9802 X02
4 1
1 4
FILTER-4P-156-GP-U
AFTP9801 5V_TSP_S0 TOUCHLCD_N
DY TOUCHLCD_P 068.24900.2001
1 2 3
AFTP9802 1 TOUCH_PANEL_INTR# 2ND = 68.11900.201
AFTP9803 1 TOUCHLCD_N
AFTP9804 1 TOUCHLCD_P AZC002-02N-GP
TOUCHLCD_P
TOUCHPANEL_P 16

EV follow ARD
ME_FW P_EC R9802 1 2 0R2J-2-GP ME_FW P

B Install after MP B

Firmware SW 1
MESW 1

24 ME_FW P_EC A
EV DY for LIDSW1 is PP C
19 ME_FW P
DY
C1
Lid Close 3D3V_S5 3D3V_S5
3D3V_S5_PCH 2
R9812
1 MESW 1_B B
DY
1KR2J-1-GP
1

2
R9804
DY SW -SLIDE6P-6-GP
LIDSW 1 100KR2J-1-GP 62.40018.691
1 R9805
2

VSS
VDD 2
3 LID_CL# 2 1 LID_CL_SIO# 24,61
OUT
C2414
SCD1U16V2KX-3GP
1

S-5712ACDL1-M3T1U-GP 10R2J-2-GP
74.05712.0BB DY
A 2ND = 74.01810.0BB A B <Core Design> A
2

Low High
ME_FWP
Normal Operation Override Wistron Corporation
(Default) 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Function Button
Size Document Number Rev
Round Rock MLK 13.3" A00
Date: Tuesday, August 18, 2015 Sheet 98 of 110
5 4 3 2 1
 5 4 3 2 1

SSID = SIO
59 NGFF_CONFIG_0
59 NGFF_CONFIG_1
59 NGFF_CONFIG_2 VGA_ID
61 MASK_ACASE_W IFI_LED# PCIE_W AKE# R9903 1 2 0R0402-PAD-2-GP
PCIE_W LAN_W AKE# 58,59
W LAN_RADIO_DIS# 58
W IRELESS_LED# W IRELESS_LED# 61

D 3D3V_S5 1 2 1099_VCC D

SC10U6D3V3MX-GP
R9906

C9804
SCD1U16V2KX-3GP

C9805

C9806
SCD1U16V2KX-3GP
0R0402-PAD-2-GP

1
DY

28

23
22
21
20
19
18
17
16
R9905 1 DY 2 0R2J-2-GP PCIE_W LAN_W AKE#

8
20,24,30 LAN_W AKE# U9901

GPIO37/KSO15
GPIO36/KSO14
GPIO35/KSO13
GPIO34/KSO12
GPIO33/KSO11
GPIO32/KSO10
GPIO31/KSO09
GPIO30/KSO08
VCC
VCC
59 NGFF_CONFIG_3 NGFF_CONFIG_3 24 15 LED_SATA_DIAG_OUT# 61
USBPW RSHR_VBUS_EN GPIO00/KSO16 GPIO27/KSO07
35 USBPW RSHR_VBUS_EN 25 GPIO01/KSO17 GPIO26/KSO06 14 SYS_LED_MASK# 61
PROCHOT_GATE 26 13
MCARD_W W AN_PW REN GPIO02/KSO18 GPIO25/KSO05 W LAN_LAN_DISBL# 30
59 MCARD_W W AN_PW REN 27 GPIO03/KSO19 GPIO24/KSO04 12 BT_RADIO_DISABLE# 58
59 HW _GPS_DISABLE2# HW _GPS_DISABLE2# 29 11 W W AN_W AKE# 59
USB_SIDE_EN# GPIO04/KSO20 GPIO23/KSO03
35 USB_SIDE_EN# 30 GPIO05/KSO21 GPIO22/KSO02 10
31 GPIO06/KSO22 GPIO21/KSO01 9
C
56 HDD_PW R_EN_SIO HDD_PW R_EN_SIO 36 7 C
GPIO07 GPIO20/KSO00
EV reserved for modern standby
37 RESERVED#37 BC_DAT/SMB_DATA 32 BC_DAT_ECE1099 24
R9949 1 2 10KR2J-3-GP TEST_PIN 38 33 BC_CLK_ECE1099 24
R9950 1 TEST_PIN BC_CLK/SMB_CLK
2 10KR2J-3-GP SMB_ADDR 35 SMB_ADDR BC_INT#/SMB_INT# 34 BC_INT#_ECE1099 24

GPIO10/KSI0
GPIO11/KSI1
GPIO12/KSI2
GPIO13/KSI3
GPIO14/KSI4
GPIO15/KSI5
GPIO16/KSI6
GPIO17/KSI7

GND
3D3V_S5
ECE1099-FZG-GP

39
40
1
2
3
4
5
6

41
71.01099.003

R9913 1 2 100KR2J-1-GP W W AN_RADIO_DIS#

R9926 1 2 10KR2J-3-GP MASK_ACASE_W IFI_LED# 17 SIO_SLP_W LAN#
R9912 1 2 100KR2J-1-GP W LAN_RADIO_DIS# 30 LAN_DISABLE#
R9911 1 2 100KR2J-1-GP W LAN_LAN_DISBL# 27,29 AUD_HP_NB_SENSE
27 AUD_NB_MUTE#
R9910 1 2 100KR2J-1-GP BT_RADIO_DISABLE# 59 W W AN_RADIO_DIS#
R9924 1 2 10KR2J-3-GP W W AN_W AKE# 52 PANEL_BKEN_EC
58 AUX_EN_W OW L
R9907 1 2 100KR2J-1-GP W IRELESS_LED#
B B
R9908 1 DY 2 100KR2J-1-GP PROCHOT_GATE
R9917 1 2 100KR2J-1-GP HW _GPS_DISABLE2#
R9902 1 2 100KR2J-1-GP USBPW RSHR_VBUS_EN
R9901 1 2 10KR2J-3-GP PCIE_W AKE#
R9904 1 2 100KR2J-1-GP USB_SIDE_EN#
R9923 1 2 100KR2J-1-GP VGA_ID

<Core Design>
A A

R9936 1 2 100KR2J-1-GP AUX_EN_W OW L

Wistron Corporation
R9944 1 2 10KR2J-3-GP SYS_LED_MASK# 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

SIO - ECE1099
Size Document Number Rev
A3 A00
Round Rock MLK 13.3"
Date: Monday, August 17, 2015 Sheet 99 of 110

5 4 3 2 1
 A B C D E
Processor Strapping Broadwell ULT Processor Platform Design Guide Rev2.0 USB2.0 MCP Side
Pair Device
Name Strap Description Schematics Notes
0 USB port 1 (usb charger)
CFG[0] Connect a series 1 k resistor on the critical CFG[0] trace in a manner which does not introduce any stubs to CFG[0] trace. 1 USB port 2 (win debug)
Route as needed from the opposite side of this series isolation resistor to the debug port. ITP will drive the net to GND.
2 WWAN
3 WLAN (BT)
CFG[4] Display Port Presence 1:Disabled - No Physical Display Port attached to Embedded DisplayPort. No connect for disable.
strap 0:Enabled - An external Display Port device is connected to the Embedded Display Port. 4 N/A
4 Pull-down to GND through a 1KΩ ± 5% resistor to enable port. CAMERA
4
5
6 Touch Panel
SPKR/GPIO81 No Reboot on TCO This signal has an integrated weak pull-down (20KΩ nominal) to enable reboot on TCO Timer expiration.
Timer expiration Pull up to VCC3_3 through a 1K to 8.2KΩ ± 5% resistor to disable this capability. 7 N/A

SDIO_D0/GPIO66 Top-Block Swap Override This signal has an integrated weak pull-down (20KΩ nominal) resistor to disable Top-Block Swap mode.
USB3.0 MCP Side
To enable Top-Block Swap, this signal should be pulled up to VCCSDIO through a 1K to 4.7KΩ ± 5% resistor. Pair Device
The reference voltage for this strap is VCCSDIO.
1 USB port 1
INTVRMEN Integrated VRM This signal has no integrated pull-up/pull-down resistor. 2 USB port 2
Enable/Disable To enable the integrated voltage regulator for DCPSUS1, DCPSUS2, DCPSUS3 and DCPSUS4 this signal must be pulled to VCCRTC 3 WWAN
through a weak resistor (e.g.330KΩ ± 5%).
To disable the integrated voltage regulator, this signal must be pulled down through a weak resistor (e.g. 330KΩ ± 5%) 4 N/A
and the DCPSUS rails must be powered externally.
PCIE Table
GSPI0_MOSI/GPIO86 Boot BIOS Strap Bit This signal has an integrated weak pull-down (20KΩ nominal) resistor to enable boot from SPI.
(BBS) To enable boot to LPC this signal must be pulled up to VCC3_3 through a 1K to 8.2KΩ ± 5% resistor.
PCIE
Lane Device

3 HDA_SDO/I2S0_TXD Flash Descriptor Security This signal has an integrated weak pull-down (20KΩ nominal) resistor to enable security measures in the flash descriptor.
Override To enable Flash Descriptor Security Override this signal must be pulled up to VCCHDA through a 1K to 4.7KΩ ± 5% resistor.
1 NA 3
2 Card Reader
GPIO15 TLS Confidentiality This signal has an integrated weak pull-down (20KΩ nominal) resistor to enable Intel ME Crypto Transport Layer Security 3 LOM
(TLS) cipher suite with no confidentiality. 4 WLAN
To enable Intel ME Crypto Transport Layer Security (TLS) cipher suite with confidentiality this signal must be pulled up to
VCCSUS3_3 through a 1K to 8.2KΩ ± 5% resistor. 5 NA
6 NA
DDPB_CTRLDATA Port B Detected This signal has an integrated weak pull-down (20KΩ nominal) resistor.
When this signal is pulled up to VCC3_3 through a 1K to 3.6KΩ ± 5% resistor at the rising edge of PCH_PPWROK
the Digital Display Port B will be detected.
SATA Table
DDPC_CTRLDATA Port C Detected This signal has an integrated weak pull-down (20KΩ nominal) resistor. SATA
When this signal is pulled up to VCC3_3 through a 1K to 3.6KΩ ± 5% resistor at the rising edge of PCH_PPWROK Pair Device
the Digital Display Port C will be detected.
0 HDD
DSWVRMEN Deep Sx Well On-Die This signal has no integrated pull-up/pull-down.
1 NA
Voltage Regulator Enable This signal must always be pulled to VCCRTC through a weak resistor (e.g. 330KΩ ± 5%).
2 NA
3 NGFF WWAN
2 2

1 <Core Design>
1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Table of Content
Size Document Number Rev
A3 A00
Round Rock MLK 13.3"
Date: Monday, August 17, 2015 Sheet 100 of 110
 5 4 3 2 1

Intel-Power Up Sequence
(DC mode) Red word: KBC GPIO
(AC mode) Red word: KBC GPIO
+RTC_PWR(VccRTC) t200
+RTC_PWR(VccRTC) t200 RTC_RST#
RTC_RST# DCBATOUT
DCBATOUT 3D3V_AUX_S5
D 3D3V_AUX_S5 D

ALWON
5V_S5
3D3V_S5(VccDSW3_3) t225

ALW_PWRGD_3V_5V
MB_PWR_BTN#(PWRBTN#)
AC_PRESENT t_plt02
ALWON
PCH_DPWROK(DWPROK) t200a t200b
5V_S5
PCH_BATLOW#
3D3V_S5(VccDSW3_3)
SIO_SLP_SUS#(SLP_SUS#) t202
ALW_PWRGD_3V_5V
PCH_ALW_ON t200b
PCH_DPWROK(DWPROK)
3D3V_S5_PCH(VccSUS3_3) t200c
PCH_BATLOW#
PCH_RSMRST#(RSMRST#)(EC wait ALW_PWRGD_3V_5V) t201
SIO_SLP_SUS#(SLP_SUS#) t202
ME_SUS_PWR_ACK(SUSWARN#/SUSPWRDNACK#)
PCH_ALW_ON
SUSACK# t200c
3D3V_S5_PCH(VccSUS3_3)
PCH_RSMRST#(RSMRST#)(EC wait ALW_PWRGD_3V_5V) t201

ME_SUS_PWR_ACK(SUSWARN#/SUSPWRDNACK#)
SUSACK#
MB_PWR_BTN#(PWRBTN#)
SIO_PWRBTN#
SIO_SLP_S5#(SLP_S5#) t203
SIO_SLP_S4#(SLP_S4#)
SUS_ON
1D35V_S3(VDDQ)
SIO_PWRBTN#
C SIO_SLP_A#(SLP_A#) C
SIO_SLP_S5#(SLP_S5#) t203
A_ON
SIO_SLP_S4#(SLP_S4#)
1D05V_M(VccASW)
SUS_ON
3D3V_M(VccSPI)
1D35V_S3(VDDQ)
PM_APWROK
SIO_SLP_A#(SLP_A#)
APWROK t251 t207
A_ON
CL_RST# t213
1D05V_M(VccASW)
SIO_SLP_S3#(SLP_S3#) t204
3D3V_M(VccSPI)
RUN_ON
PM_APWROK
1D05V_S0(VccPLL) t207
APWROK
3D3V_S0(VccCore(PCH)) t_plt08 t_plt09
CL_RST# t213
RUNPWROK(All_SYS_PWROK) t205a
SIO_SLP_S3#(SLP_S3#) t204
RESET_OUT#(PCH_PWROK)(Aftre RUNPWROK 100ms) t_plt07 t_plt04
RUN_ON
H_VCCST_PWRGD
1D05V_S0(VccPLL)
H_VR_ENABLE(VR12.5_VR_EN) t_plt09
3D3V_S0(VccCore(PCH))
VCC_CORE(CPU) t205a
RUNPWROK(All_SYS_PWROK) t_plt04
H_VR_READY(VR_ Ready) t_plt07
RESET_OUT#(PCH_PWROK)(Aftre RUNPWROK 100ms)
SM_DRAMRST# t223
H_VCCST_PWRGD
Clock(PCH Clock Output) t209
H_VR_ENABLE(VR12.5_VR_EN)
H_CPUPWRGD(PROCPWRGOOD) t_plt03
VCC_CORE(CPU)
SYS_PWROK(After RESETOUT 10ms)) t_plt05
H_VR_READY(VR_ Ready)
PLTRST# t223
SM_DRAMRST#
SPI Signals
Clock(PCH Clock Output) t209
B
H_CPUPWRGD(PROCPWRGOOD) t_plt03 B

SYS_PWROK(After RESETOUT 10ms)) t_plt05

PLTRST#
SPI Signals

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Power Sequence
Size Document Number Rev

Round Rock MLK 13.3" A00

Date: Monday, August 17, 2015 Sheet 101 of 109
5 4 3 2 1
 5 4 3 2 1

Intel-Power Down Sequence

(DC mode) red word: KBC GPIO
(AC mode) red word: KBC GPIO

PLTRST#

H_CPUPWRGD(PROCPWRGOOD) PLTRST#
t217
D Clock t219 H_CPUPWRGD(PROCPWRGOOD) D
t217
H_VCCST_PWRGD Clock t219

CL_RST# H_VCCST_PWRGD

H_VR_ENABLE(VR12.5_VR_EN) CL_RST#

H_VR_READY(VR12.5_ PWRGD (VR_ Ready)) H_VR_ENABLE(VR12.5_VR_EN)

VCC_CORE(CPU) H_VR_READY(VR12.5_ PWRGD (VR_ Ready))

RESET_OUT#(PCH_PWROK) VCC_CORE(CPU)
t222
SYS_PWROK RESET_OUT#(PCH_PWROK)
t222
SIO_SLP_A#(SLP_A#) SYS_PWROK

A_ON SIO_SLP_A#(SLP_A#)

APWROK A_ON

1D05V_M(VccASW) APWROK

3D3V_M(VccSPI) 1D05V_M(VccASW)

SIO_SLP_S3#(SLP_S3#) 3D3V_M(VccSPI)

RUN_ON SIO_SLP_S3#(SLP_S3#)

1D05V_S0(VccPLL) RUN_ON

t233 1D05V_S0(VccPLL)
3D3V_S0(VccCore(PCH)) t231
3D3V_S0(VccCore(PCH)) t233
SIO_SLP_S4#(SLP_S4#) t231
t221
SUS_ON SIO_SLP_S4#(SLP_S4#)
t221
1D35V_S3(VDDQ) SUS_ON
C C

SM_DRAMRST# 1D35V_S3(VDDQ)
t_plt12
SM_DRAMRST#

SIO_SLP_S5#(SLP_S5#) t_plt12

PCH_RSMRST#(RSMRST#) t235
PCH_ALW_ON

3D3V_S5_PCH(VccSUS3_3)

ALWON

3D3V_S5

5V_S5

B B

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Power Sequence
Size Document Number Rev

Round Rock MLK 13.3" A00

Date: Monday, August 17, 2015 Sheet 101 of 109
5 4 3 2 1
 5 4 3 2 1

Adapter AD+ SI7121DN CHARGER_SRC

SI7121DN
Charger
BQ24777
D Battery BT+ D

DCBATOUT

TPS51624 SY8206D SY8206D TPS51275RUKR

VCC_CORE 1D35V_S3 1D05V_M 5V_PWR_2

3D3V_S5

3D3V_AUX_S5
(3D3V_PWR_2)

APL5338XAI
TPCA8062 TPCA8062
C
AO6402A-GP TPS22966 AO6402A-GP TPS22966 AO6402A-GP TPS22966 C

0D675V_S0 0D675V_VTTREF 1D05V_MODPHY 1D05V_S0 3D3V_S5_PCH 3D3V_S0 3D3V_M 3D3V_LAN 3D3V_S5_WWAN 3D3V_S5_WLAN LCDVDD

S-1339D15-M5001-GP 3D3V_S0_HDD DMP2130L

+1.5V_THERMAL 3D3V-CAMERA

5V_S5

B B

SY6288DCAC PI5USB2544 TPS22966

USB30_VCCA USB30_VCCB 5V_S0

AO6402A-GP

5V_S0_HDD

A A

Power Shape <Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Regulator LOAD SWITCH Switch Taipei Hsien 221, Taiwan, R.O.C.

Title
Power Block Diagram
Size Document Number Rev
Round Rock MLK 13.3" A00
Date: Monday, August 17, 2015 Sheet 103 of 110
5 4 3 2 1
 A B C D E

2.2K 2.2K
3D3V_S5_PCH 3D3V_S0
SMB_DATA 2.2K 2.2K PCH_SMBDATA 200
AH1 2N7002
SMB_CLK PCH_SMBCLK 202 DIMM1 SMB Addr=[A0]
AP2 2N7002
1 2.2K 1
200
3D3V_S5_PCH
202 DIMM2 SMB Addr=[A4]
PCH 2.2K
AK1 LOM_SMBDAT
AN1 LOM_SMBCLK SML0_DATA_XDP 51
Dummy
SML0_CLK_XDP 53 XDP Conn SMB Addr=[XX]
Dummy

4
AU3 AH3 SMB Addr=[?]
1 FFS
2.2K
SML1_SMBDATA
3D3V_S5_PCH
SML1_SMBCLK
2.2K

10K
A5 B6
3D3V_S5
CHARGER_SMBDAT 10K 8
A47
CHARGER_SMBCLK 9 CHARGER SMB Addr=[?]
B50
2
EC 2

2.2K
3D3V_S5
MEC5085
B59 PBAT_SMBDAT 2.2K PBAT_SMBDAT_R 4 Battery
A56 PBAT_SMBCLK PBAT_SMBCLK_R 3 SMB Addr=[16]
Conn
4.7K
3D3V_TP
B40 DAT_TP_SIO 4.7K DAT_TP_SIO_R 6 Touch Pad
A37 CLK_TP_SIO CLK_TP_SIO_R 7 SMB Addr=[?]
Conn

3 3

4 4

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

SMBUS Block Diagram

Size Document Number Rev
Round Rock MLK 13.3" A00
Date: Monday, August 17, 2015 Sheet 104 of 110
A B C D E
 A B C D E

Thermal Block Diagram Audio Block Diagram

1 1

DP1-VREF_T REM_DIODE1_P SPK-OUT-L- AUD_SPK_L-

LMBT3904LT1G-GP SPK-OUT-L+ AUD_SPK_L+

SC2200P50V2KX-2GP SC470P50V2JN-GP

DN1-THERM REM_DIODE1_N
SPK-OUT-R- AUD_SPK_R-
SPEAKER
Place near CPU SPK-OUT-R+ AUD_SPK_R+

DP2 REM_DIODE2_P
EC LMBT3904LT1G-GP

MEC5085 DN2
SC2200P50V2KX-2GP SC470P50V2JN-GP HPOUT-L/PORT-A-L

HPOUT-R/PORT-A-R
AUD-HP1-JACK-L1

AUD-HP1-JACK-R1
Universal
REM_DIODE2_N
Place near DIMM JACK
2 2

DP4 REM_DIODE4_P

LMBT3904LT1G-GP
SC2200P50V2KX-2GP SC470P50V2JN-GP

DN4 REM_DIODE4_P

Place near V.R

FAN1_TACH
FAN1_PWM

5V
3 3

TACH

FAN Codec
ALC3234

4 4
<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Thermal/Audio Block Diagram

Size Document Number Rev

Round Rock MLK 13.3" A00

Date: Monday, August 17, 2015 Sheet 105 of 110
A B C D E
 5
SSID = User.Interface 4 3 2 1

Regulatory model:P47G
Regulatory Type:P47G002;Latitude 3350

D CLKOUT_PCIE_N1 Card-Reader D
CLKOUT_PCIE_N1
RTS5242

CLKOUT_PCIE_N2 LAN X3001

CPU CLKOUT_PCIE_P2
RTL8111HSD-CG
25MHZ

CLKOUT_PCIE_N3

CLKOUT_PCIE_N3 WLAN
XTAL24_IN
X1801
24MHZ XTAL24_OUT
C CLKOUT_PCIE_N5 C
CLKOUT_PCIE_P5 WWAN

33 Ohm CODEC
HDA_BITCLK
ALC3234

22 Ohm KBC
CLKOUT_LPC_0 X2401
MEC5085 32.768 kHZ

22 Ohm
B CLKOUT_LPC_1
Debug 1 B
SA_CLK#0

SA_CLK#1
SA_CLK0

SA_CLK1

SB_CK#0

SB_CK#1
SB_CK0

SB_CK1
CK0#

CK1#

CK0#

CK1#
CK0

CK1

CK0

CK1
DM1

DM2

<Core Design>
A A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CLK Block
Size Document Number Rev
A3 A00
Round Rock MLK 13.3"
Date: Monday, August 17, 2015 Sheet 106 of 110
 5 4 3 2 1

Item Page# Date Request By Issue description Solution Description Rev.

Add R6211
1 62 2015/5/12 EE Vendor suggest increase ECE1117C ESD protection. X01
This request by EMI . Because EMI test result is fail. 1. Change PR4703 from 2.2R 0402 to 2.2R 0603 (64.2R205.55L) and stuff
2 47 2015/5/12 Power So we msut add snubber to solve EMI issue . 2. Change PC4707 from 1500P to 1000P (78.10224.2FL) and stuff X01
PL4401 after heat & vibration test will be broken.
D
3 44 2015/5/13 Power Change to a part with glue Change PL4401 to 68.2R21C.10Q X01 D

4 48/49 2015/5/13 Power PL4801, PL4901 main source no share PL4801, PL4901 change to 68.1R010.20I X01
5 55 2015/5/25 EMC To solve Broadwell ESD issue Stuff U5502, U5503, U5504 X01
6 20/25 2015/6/2 EE Add RTC circuit for factory request Add RTC detect circuit : Q2502, R2506, R2021, R2022 X01
7 25 2015/7/1 EE Change RTC circuit for RTC leakage Mirror Q2502 vertically X02
8 88 2015/7/1 EE Fix TPM resume from DS3 will be lost issue Change U8801 VSB form 3D3V_S5_PCH to 3D3V_S5 X02
9 24 2015/7/1 EE Change board ID version Change R2457 to 33K X02
C 10 19/24 2015/7/9 EE Fix alternative parts loop issue Change both X1901 & X2401 to same 3 sources X02 C

R402, R416, R417, R701, R704, R705, R706, R709, R1401, R1407, R1408, R1410
R1415, R1417, R1422, R1423, R1430, R1508, R1607, R1704, R1705, R1706, R1708
R1710, R1711, R1713, R1717, R1718, R1720, R1725, RN1801, RN1802, RN1803
RN1809, R1801, R1802, R1809, R1810, R1811, R1812, R1906, R1909, R2011, R2013
R2014, R2021, R2101, R2102, R2105, R2107, R2108, R2110, R2111, R2115, R2116
R2117, R2401, R2402, R2403, R2424, R2432, R2464, R2461, R2467, R2468, R2471
R2511, R2703, R2705, R2706, R2707, R2709, R2710, R2711, R2714, R2719, R2722
ER2701, ER2702, RN2701, R2738, R2740, R2741, R2742, R2745, R2911, EL2904

11 All 2015/7/17 EE Change to short pad

EL2903, R2912, R2902, R3006, R3001, R3201, R3206, R3217, R3202, R3204, R3207
R3209, R3210, R3211, R3213, R3212, R3301, R3401, R3402, R3403, R3405, R3407
X02
R3408, R3409, R3412, R3601, R3610, R3603, R3604, R3637, R3654, R3656, R3619
R3611, R3655, R3625, R3657, PR4466, PR4434, PR4467, PR4430, PR4469
PR4501, PR4505, PR4521, PR4615, PR4625, PR4801, PR4903, R5217, R5222, R5221
R5227, R5406, R5407, R5601, R5602, R5603, R5604, R5820, R5830, R5808, R5806
R5828, R5829, R5924, R5927, R5928, R5901, R5906, R5905, R6115, R6103, R6201
R6202, R6203, R6207, R6701, R9620, R9807, R9906, R9903

B B

PR4406, PR4417, PR4430, PR4431, PR4434, PR4438, PR4466, PR4467, PR4469

12 All 2015/7/17 Power Change to short pad PR4501, PR4505, PR4521, PR4615, PR4616, PR4617, PR4625, PR4801, PR4902 X02
PR4903

13 55 2015/7/17 EMC Change for source reason Change TR5501, TR5502, TR5503, TR5504 form 69.10118.001 to 068.24900.2001 X02
14 42 2015/7/20 Power Change for source reason Remove PD4402 2ND 083.10100.008R X02
15 52 2015/7/21 ME Change for source reason Remove LCD1 main 20.F2089.030 X02
16 55 2015/7/21 ME Change for source reason Remove DP1 2nd 62.10105.431 X02
17 61 2015/7/21 ME Change for source reason Remove PWRBT1 2nd 62.40009.A81 X02
A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
Change History-01
Size Document Number Rev
Round Rock MLK 13.3" A00
Date: Tuesday, August 18, 2015 Sheet 107 of 110
5 4 3 2 1
 5 4 3 2 1

Item Page# Date Request By Issue description Solution Description Rev.

18 85 2015/7/21 RF Add Caps for RF solution EC8532~EC8556 X02

19 45 2015/8/17 EE Remove parts with halogen Remove PD4502, PD4503 2nd source 75.00054.C7D A00
D
20 25 2015/8/17 EE Remove parts with halogen Change Q2501 main source from 83.R0304.B81 to 83.00040.E81 A00 D

Chagne PD4401 PD4405 PD4406 main source

21 44 2015/8/17 EE Remove parts with halogen
from 83.1R504.B8F to 83.2R004.08F A00
22 24 2015/8/17 EE Change EC to MP P/N Change U2401 to 071.05085.0B03 A00
23 24 2015/8/17 EE Change board ID version Change R2457 to 1K A00
24 96 2015/8/18 EE Change XDP conn to P/N with solder mask Change XDP1 to ZZ.00PAD.Q81 A00
25 65 2015/8/18 EE Change DB conn to P/N with solder mask Change DB1 to ZZ.00PAD.Y41 A00
26 61 2015/8/19 ME Remove PWRBT1 2nd 062.40001.0211 A00
C 27 61 2015/8/19 ME Remove SWLED1 2nd 83.00191.F70 A00 C

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
Change History-02
Size Document Number Rev
Round Rock MLK 13.3" A00
Date: W ednesday, August 19, 2015 Sheet 108 of 110
5 4 3 2 1
 5 4 3 2 1

Item Page# Date Request By Issue description Solution Description Rev.

44
45
D D

46
48
49
50
51
52

C C
53
54
55
56
57
58
59
B
60 B

61
62
63
64
65
66
67
A <Core Design> A

Wistron Corporation
68 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
Change History-02
69 Size Document Number Rev
Round Rock MLK 13.3" A00
Date: Monday, August 17, 2015 Sheet 109 of 110
5 4 3 2 1
 5 4 3 2 1

Item Page# Date Request By Issue description Solution Description Rev.

70
71
D D

72
73
74
75
76
77
78
C C
79
80
81

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
Change History-04
Size Document Number Rev
Round Rock MLK 13.3" A00
Date: Monday, August 17, 2015 Sheet 110 of 110
5 4 3 2 1