Dell Inspiron N5010-AMD

5 4 3 2 1
Berry Discrete/UMA Schematics Document

D D
AMD Danube CPU S1g4

AMD GPU Madison-LP/M96-LP M2
C
RS880M + SB820M C
2010-03-08
B B
REV : A00
<Core Design>
A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Cover Page
DY : Nopop Component Size
A4
Document Number Rev
Berry AMD Discrete/UMA A00
Date: Monday, March 08, 2010 Sheet 1 of 95
5 4 3 2 1
5 4 3 2 1
CHARGER
Project code :91.4HH01.001
PCB P/N :
Berry DG15 Discrete/UMA Block Diagram BQ24745
INPUTS OUTPUTS
45
28,
+DC_IN_SS
Revision :X-Build +VCHGR
+PWR_SRC
DDR III 1333 DDRIII DIMM1 SYSTEM DC/DC

AMD Champlain 800/1066/1333 18
3
RT8205B 46
D
VRAM CPU S1G4 INPUTS OUTPUTS D
64Mx16bx8 (1GB) 35W Max DDR III 1333 DDRIII DIMM2

4
85,86,87,88 8,9,10,11 800/1066/1333 19 +3.3V_RTC_LDO
2
+PWR_SRC +5V_ALW
DDR3 +3.3V_ALW
800MHz HyperTransport
OUT
IN
16X16 CPU VDDR
AMD Graphic RT9025 48
PCIe x 16 RJ45 INPUTS OUTPUTS
M96-M2 LP VRAM
80,81,82,83
SIDE-PORT CONN +1.5V_SUS +CPU_VDDR 3
North Bridge 64Mx16bx1 (1GB)
14 CPU CORE
CPU I/F ISL6265AHRTZ-T-GP 47
HDMI HDMI(Share PCIe x 4)
57 AMD RS880M INPUTS OUTPUTS
LVDS, CRT I/F PCIE x 1 10/100 NIC
Realtek RTL8103T
+VCC_CORE
+PWR_SRC
INTEGRATED GRAHPICS +VDDNB 3
C C
AMD RS880M CORE

12,13,14,15 USB 2.0 x 1 RT8209 50
LCD Conn LVDS(Dual Channel) USB x 1
INPUTS OUTPUTS
I/O Board
Connector
(LVDS & Camera Conn.) 54
A-LINK +PWR_SRC +NB_VDDC
3
4X4 AMD SB820M S5 POWER
RT9025 48
SATA x 1 E-SATA/USB INPUTS OUTPUTS
CRT RGB CRT South Bridge COMBO
+3.3V_ALW +1.1V_ALW
CRT Board
Connector
AMD SB820M DDR III SUS&VTT

PCIE x 2& USB 2.0 x 2
RT8207 49
14 USB 2.0 ports MiniCard x 2
USB2.0 x 2
WLAN&WWAN
INPUTS OUTPUTS
USB x 2 ETHERNET (10/100/1000Mb) 76
77 +PWR_SRC +1.5V_SUS
High Definition Audio
2 PCIE GPP DDR III SUS&VTT
RT8207 49
6 SATA ports
B
CardReader USB 2.0 USB 2.0 x 1 Camera Conn INPUTS OUTPUTS
B
Card Reader ACPI 1.1 (LVDS & Camera Conn.)

54
Realtek Connector USB2.0 +PWR_SRC +0.75V_DDR_VTT 2
78
LPC I/F
RTS5159 AMD GPU CORE
PCI/PCI BRIDGE USB 2.0 x 1 Bluetooth Conn RT8208B 89
LPC Bus 73
20,21,22,23,24 INPUTS OUTPUTS
+PWR_SRC +VGA_CORE
SD/SDIO/MMC PCB LAYER
MS/MS Pro/xD L1: Top
KBC L2: VCC
Azalia
SATA
SATA
SPI NUVOTON L3: Signal

Internal Analog MIC
CODEC NPCE781BA0DX 37 L4: Signal
AZALIA
L5: GND
MIC IN & L6: Bottom
OP AMP
A HP1 <Core Design> A
IDT 92HD79B1 Flash ROM Touch Int. Thermal
30 HDD ODD
2MB PAD KB EMC2102 Wistron Corporation
59 59 62 68 68 2539 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
2CH SPEAKER Title
Block Diagram
Fan Size Document Number Rev
58
A3 Berry AMD Discrete/UMA A00
Date: Thursday, March 04, 2010 Sheet 2 of 95
5 4 3 2 1
A B C D E
Power Shape
Regulator LDO Switch
4
Power Block Diagram 4
+PWR_SRC
Adapter
ISL6265AHRTZ RT8208B RT8209EGQW RT8207

AO4407A
Charger
BQ24745 +VCC_CORE +VDDNB(CPU) +VGA_CORE +1.1V_RUN +1.5V_SUS
Battery +VCHGR
AO4468 AO4468 APL5930 RT9025

RT8205B
3 3
+1.5V_RUN +1.5V_RUN_VGA +1.0V_RUN_VGA VDDR(CPU)

+3.3V_RTC_LDO +5V_ALW +3.3V_ALW
UP7534 AO4468 UP7534 AO4468 PA102FMG APL5930 APL5930 RT9025
+5V_USB1 +5V_RUN +5V_USB2 +3.3V_RUN +3.3V_LAN +1.8V_RUN +1.8V_RUN_VGA +1.1V_ALW
2 2
RESISTER RESISTER SI2301BDS G5285T11U RTS5159 RT9013-25PB RTL8103T
+PVDD +AVDD +3.3V_RUN_VGA +LCDVDD +3.3V_RUN_CARD +2.5V_RUN +1.2V_LOM
1 <Core Design> 1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Title
Power Block Diagram
Size Document Number Rev
A3
A B C D E
5 4 3 2 1
SB820M SMBus Block Diagram KBC SMBus Block Diagram

D D
+5V_RUN
+3.3V_RUN
SB_SMBCLK
CLK GEN
SCL
SB_SMBDATA SDA
SRN10KJ-5-GP
SRN2K2J
SMBus Address:0xD2
PSDAT1 TPDATA TPDATA TPDATA
TouchPad Conn.
PSCLK1 TPCLK TPCLK TPCLK
SB820M SCL0
SDA0
SB_SMBCLK_R
SB_SMBDATA_R SB_SMBCLK
DIMM 1 +KBC_PWR
SCL
C SB_SMBDATA C
SDA
SCL1 SMB_CLK
+3.3V_ALW
SDA1 SMB_DATA SMBus Address:0xA0,0x30 SMBus address:
SRN4K7J-8-GP
SCL3_LV/IMC_GPIO13
SDA3_LV/IMC_GPIO14
CPU_SIC
CPU_SID SRN10KJ-5-GP DIMM 2 Battery Conn.

SB_SMBCLK SRN100J-3-GP
SCL
SCL1 BAT_SCL PBAT_SMBCLK1 CLK_SMB
SB_SMBDATA
SDA
SDA1 BAT_SDA PBAT_SMBDAT1 DAT_SMB
SMBus Address:0xA4,0x34
BQ24745RHDR
WWAN
MINI CARD KBC SCL
SDA
SB_SMBCLK
SB_SMBDATA
SMB_CLK
SMB_DATA
NPCE781 SMBus address:0x12
+3.3V_RUN
SMBus address:
WLAN +3.3V_ALW
+3.3V_RUN
MINI CARD SRN4K7J-8-GP
B
SB_SMBCLK
SB_SMBDATA
SMB_CLK
SMB_DATA
Thermal B
THERM_SCL SCL
SRN4K7J-8-GP
THERM_SDA SDA
+1.5V_SUS SMBus address:
SMBus address:0x7A
GPIO61/SCL2 KBC_SCL1
SRN1KJ-7-GP CPU S1G4 GPIO62/SDA2 KBC_SDA1

2N7002SPT
SIC
CPU_SIC
SID
CPU_SID
SMBus address:
A A
<Core Design>
Wistron Corporation
Title
SMBUS BLOCK DIAGRAM
A2
5 4 3 2 1
5 4 3 2 1
Thermal Block Diagram Audio Block Diagram

D D
SPKR_PORT_D_L+
SPKR_PORT_D_L-
AUD_SPK_L+
AUD_SPK_L-
SPEAKER
SPKR_PORT_D_R- AUD_SPK_R-
SPKR_PORT_D_R+ AUD_SPK_R+
60
CPU 60D4R2F
DP1 H_THERMDA THERMDA HP1_PORT_B_L
HP1_PORT_B_R
AUD_HP1_JACK_L
AUD_HP1_JACK_R
Bead
Bead
AUD_HP1_JACK_L1
AUD_HP1_JACK_R1
HP
SC470P50V3JN-2GP
DN1 H_THERMDC THERMDC

60D4R2F
OUT
C C
Thermal Codec 60
EMC2102 92HD79B1
DP2 VGA_THERMDA DPLUS
GPU
VREFOUT_A_OR_F AUD_VREFOUT_B
SC470P50V3JN-2GP
4K7R2J-2-GP
4K7R2J-2-GP
DN2 VGA_THERMDC DMINUS MIC
HP0_PORT_A_L AUD_EXT_MIC_L IN
HP0_PORT_A_R AUD_EXT_MIC_R
60
PMBS3904
B B
SC1U10V3KX-3GP
DP3 EMC2102_DP3
AUD_INT_MIC_R_L INT_MIC_L_R
SC470P50V3JN-2GP
PMBS3904 PORT_C_L Internal
DN3 EMC2102_DN3 PORT_C_R AUD_INT_MIC_R_L MIC
System sensor, put VREFOUT_C
between CPU and NB. AUD_VREFOUT_C
4K7R2J-2-GP 60
30
A <Core Design> A
Wistron Corporation
Title
THERMAL/AUDIO BLOCK DIAGRAM
A3
5 4 3 2 1
5 4 3 2 1
SB820M Strapping RS880M Strapping

Capture from 45484 Rev. 1.02 AMD SB8xx-Series Southbridge Design Guide Capture from 46113_rs880m_ds_nda_1.03
Name Strap Name Schematic Note Name Strap Function Schematic Note
Embedded Controller (EC) Enables debug bus access
LPCCLK0 ECEnableStrap 0 V – Disabled
DAC_VSYNC STRAP_DEBUG_BUS_GPIO through memory I/O pads and GPIOs.
* 3.3 V - Enabled _ENABLE# 0: Enable
D
* 1: Disable D
ROMTYPE_1 ROMTYPE_0 ROM TYPE

3.3V 0V SPI ROM Indicates if memory side-port is available or not
3.3V 3.3V Reserved DAC_HSYNC SIDE_PORT_EN# 0: Available(UMA)
EC_PWM3 {ROMTYPE_1, 1: Not available(Discrete)
EC_PWM2 0V 0V Firmware Hub
ROMTYPE_0 }
0V 3.3V
LPC ROM Selects loading of strap values from EEPROM.
* (supports both LPC and PMC ROM types) 0: I2C master can load strap values from EEPROM if
Defines clock generator connected, or use default values if EEPROM is not
SUS_STAT# LOAD_EEPROM_STRAPS# connected. Please refer to RS880M's reference
* External clock mode: Use 100-MHz PCIeR schematics for system level implementation details.
CLKGEN 0V – clock as reference clock and generate i
LPCCLK1 * 1: Use default values
nternal clocks only.
3.3V– Integrated clock mode: Use 25-MHz crystal

clock and generate both internal and external clocks
Set PCIe to Gen II mode

BIF_GEN2_
PCICLK1 COMPLIANCE_Strap 0V– Force PCIe interface at Gen I mode
* 3.3V- PCIe interfacce is at Gen II mode
Not Applicable to SB820M but provision for
pull-down is required.
C USB Table PCIE Routing C
Watchdog function USB RS880M

PCICLK2 BootFailTmrEn * Pair Device
0V– Disable the boot fail timer function
0 USB0 (I/O Board/ESATA) LANE0 MiniCard WLAN
3.3V- Enable the boot fail timer function
1 USB1 (I/O Board)
USB2 (CRT Board)
LANE1 LAN
Default Debug Straps 2
3 USB3 (CRT Board) LANE2 MiniCard WWAN
PCICLK3 DefaultStrapMode * 0V– Disable Debug Straps. 4 WLAN USB
3.3V– Select external Debug Straps
5 WWAN USB
6 RESERVED
CPU/NB HT Clock Selection RESERVED
7
Reserved. 8 RESERVED
PCICLK4 CPUClkSel 0V–
* 3.3V– Required setting for integrated clock mode. 9 BLUETOOTH
This strap is not used if the strap CLKGEN is 10 CARD READER
configured for external clock generator mode.
11 CAMERA (LVDS CONN)
12 RESERVED
Slow down core clock for low power platform. RESERVED
13
AZ_SDOUT CoreSpeedMode * 0V– Performance mode
3.3V- Low Power mode
B B
A A
<Core Design>
Wistron Corporation
Title
Table of Content
A2
5 4 3 2 1
5 4 3 2 1
+3.3V_RUN +3.3V_CLK_VDD
+3.3V_CLK_VDD (40 mils)
1 R702 2
0R0603-PAD
SC10U6D3V5KX-1GP
1231-1 1119-3
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1
1
C701
C703
C704
C705
C706
C707
C708
C709
D D
2
9/22
+3.3V_RUN +3.3V_CLK_VDDIO
CLKREQ# MAP
1 R703 2
0R0603-PAD
CLKREQ0# No use
SC10U6D3V5KX-1GP
1231-1 1119-3
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
CLKREQ1# CLKSRC1 WLAN
1
1
C710
C712
C713
C714
C715
C716
C717
DY
CLKREQ2# CLKSRC2 WWAN
2
2
C718
CLKREQ3# CLKSRC3 LAN
9/22 10/1 1 2
X-14D31818M-37GP
CLKREQ4# No use
1MR2J-L2-GP
SC12P50V2JN-3GP
1
+3.3V_CLK_VDD
R704
X701
U701
+3.3V_RUN +3.3V_CLK_VDDREF +3.3V_CLK_VDDIO DY
2
26 61 CLKGEN_X1 C719
2
+3.3V_CLK_VDDREF VDDATIG X1
1 R701 2 25 VDDATIG_IO X2 62 CLKGEN_X2 1 2 0107-1
0R0603-PAD
9/22 0114-2 SC12P50V2JN-3GP
1231-1 48
SCD1U10V2KX-5GP
VDDCPU SB_SMBCLK_CK
C 47 VDDCPU_IO SMBCLK 2 1 4 RN712 SB_SMBCLK_R (18,21)
SB_SMBCLK_CK 1 2 C
1
+3.3V_RUN
C721
3 SB_SMBDATA_CK 2 3 SRN33J-5-GP-U SB_SMBDATA_CK C722 1 SC47P50V2JN-3GP

2
SMBDAT SB_SMBDATA_R (18,21)
16 C723 SC47P50V2JN-3GP
VDDSRC
10KR2J-3-GP
GFX_CLKP RN709
1119-3 17 1
DIS 4 CLK_PCIE_VGA (80)
2
VDDSRC_IO
1
11 30 GFX_CLKN 2 3 SRN0J-6-GP
VDDSRC_IO ATIG0T_LPRS CLK_PCIE_VGA# (80)
RN
R705
35
ATIG0C_LPRS 29
28
VGA(100MHz)
VDDSB_SRC ATIG1T_LPRS
34 VDDSB_SRC_IO ATIG1C_LPRS 27 NB_GFX_CLK_R 10R4P2R-PAD
4 NB_GFX_CLK (13) Need External PU Resistor
EC702 NB_GFX_CLK_R# 2 3 NB_GFX_CLK# (13)
2
R706 SC10P50V2JN-4GP RN707 +3.3V_RUN

40 VDDSATA 10/2
TP_CLKREQ0#
(21,41) SB_PW RGD 1 DY 2 4 VDD CLKREQ0# 23 9/23
1
55 45 W LAN_CLK_REQ# RN711
VDDHTT CLKREQ1# W LAN_CLK_REQ# (76)
0R2J-2-GP 56 44 W W AN_CLK_REQ# W LAN_CLK_REQ# 1 4
VDDREF CLKREQ2# W W AN_CLK_REQ# (76)
DY 63 39 TP_CLKREQ3# W W AN_CLK_REQ# 2 3
2
VDD48 CLKREQ3# TP_CLKREQ4#

CLKREQ4# 38
RN
SRN10KJ-5-GP
CLKGEN_PD# 51 PD#
CPUKG0T_LPRS 50 CPU_HT_CLK 10R4P2R-PAD
4 CPU_CLK (10) CPU_CLK(200MHz) CPU_CLK
0105-1
49 CPU_HT_CLK# 2 3 CPU_CLK#
CPUKG0C_LPRS RN708 CPU_CLK# (10)
R_NB_GPP_CLK 22 SRC0T_LPRS
SC10P50V2JN-4GP
EC704
EC705
SC10P50V2JN-4GP
WLAN(100MHz) (76) CLK_PCIE_W LAN 2RN702 3 R_NB_GPP_CLK# 21 SRC0C_LPRS 48MHZ_0 64 48M_CLK R710 1 2 22R2J-2-GP
USB_48M_CLK (21) SB820M_USB(48MHz)
1
1
1 4 CLK_MINI1_R 20
(76) CLK_PCIE_W LAN# SRC1T_LPRS
SC4D7P50V2CN-1GP
0R4P2R-PAD CLK_MINI1#_R
CLK_SRC2
19 SRC1C_LPRS FS0
1116-9
15 59
DY DY
2
2
SRC2T_LPRS REF0/SEL_HTT66
1
RN
EC703
WWAN(100MHz) (76) CLK_PCIE_W W AN 2RN710 3 CLK_SRC2# 14 SRC2C_LPRS REF1/SEL_SATA 58 SB_14M_CLK +3.3V_RUN
1 4 LAN_CLK_R 13 57 FS2 DY
(76) CLK_PCIE_W W AN# SRC3T_LPRS REF2/SEL_27
0R4P2R-PAD LAN_CLK#_R
10/5 12 For EMI
2
TP_CLK_SRC4 SRC3C_LPRS
9 SRC4T_LPRS
1
RN
8K2R2J-3-GP
8K2R2J-3-GP
LAN(100MHz) (76) CLK_PCIE_LAN 2RN703 3 TP_CLK_SRC4# 8 SRC4C_LPRS
B B
R711
R712
TP_CLK_SRC6
(76) CLK_PCIE_LAN# 1 4
0R4P2R-PAD TP_CLK_SRC6#
42
41
SRC6T/SATAT_LPRS GNDSATA 43
24
0225-2
R713 1 SRC6C/SATAC_LPRS GNDATIG
2 47R2J-2-GP R_VGA_27M_SS_CLK
(82) CLK_VGA_27M_SS DIS 6 SRC7T_LPRS/27MHZ_SS GND 7
RN
R714 1 2 33R2J-2-GP R_VGA_27M_NSS_CLK

VGA(27MHz) DIS 5 52
2
(82) CLK_VGA_27M_NSS SRC7C_LPRS/27MHZ_NS GNDHTT R715 1
1113-2 10/5 GNDREF 60 2 158R2F-GP NB_14M_CLK (13) NB OSCIN(14MHz)
2RN704 NB_GPPSB_CLK_R GNDCPU 46 SB_14M_CLK (21) SB OSCIN(14MHz)
(13) NB_GPPSB_CLK 3
NB_GPPSB_CLK#_R
37 SB_SRC0T_LPRS GND48 1 0105-3
NB(100MHz) (13) NB_GPPSB_CLK# 1 4
0R4P2R-PAD SB_PCIE_CLK_R
36
32
SB_SRC0C_LPRS
10
SB_SRC1T_LPRS GNDSRC
1
90D9R2F-1-GP
8K2R2J-3-GP
SB_PCIE_CLK#_R 31 18
SB_SRC1C_LPRS GNDSRC
RN
R718
R717
(20) SB_PCIE_CLK 2RN705 3 GNDSB_SRC 33 DY
SB(100MHz) (20) SB_PCIE_CLK# 1 4
0R4P2R-PAD
54
53
HTT0T_LPRS/66M
65
2
HTT0C_LPRS/66M GND
RN
(13) CLK_NBHT_CLK 2RN706 3 CLK_NBHT_CLK_R ICS9LPRS480BKLFT-GP Place together

1 4 CLK_NBHT_CLK#_R 71.09480.A03
(13) CLK_NBHT_CLK# 0R4P2R-PAD
1st 71.09480.A03
RN
10/1 2nd 71.08628.003
TP701 1 TP_CLK_SRC6
TP702 1 TP_CLK_SRC6#
TP703 TP_CLKREQ0#
TP704
1
1 TP_CLKREQ3#
NB ALINK SEL_HTT66 1 66 MHz 3.3V single ended HTT clock
TP705
TP706
1 TP_CLKREQ4#
TP_CLK_SRC4
(100MHz) FS0
0* 100 MHz differential HTT clock
A 1 <Core Design> A
TP707 TP_CLK_SRC4#
TP709
1
1 R_NB_GPP_CLK
SB PCIE SEL_SATA 1* 100 MHz non-spreading differential SRC clock
TP708 1 R_NB_GPP_CLK# (100MHz) FS1
0 100 MHz spreading differential SRC clock Wistron Corporation
27MHz non-spreading singled clock on pin 5 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
VGA Madison SEL_27MHz 1* and 27MHz spread clock on pin 6 Taipei Hsien 221, Taiwan, R.O.C.
(27MHz) FS2
0 100MHz differential spreading SRC clock Title
* default Clock Generator ICS9LPRS480
A3
5 4 3 2 1
5 4 3 2 1
+1.1V_RUN
SSID = CPU Place close to socket

1.1V(1.5A) for VLDT
SC22U6D3V5MX-2GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
SC180P50V2JN-1GP
SC180P50V2JN-1GP
1
1
C801
C802
C803
C804
C805
C806
C807
D CPU1A 1 OF 6 D
DY DY DY
2
D1 VLDT_A0 VLDT_B0 AE2
DANUBE
D2 VLDT_A1 VLDT_B1 AE3
1119-3 D3
D4
VLDT_A2 VLDT_B2 AE4
AE5
VLDT_A3 VLDT_B3
(12) HT_NB_CPU_CAD_H0 E3 L0_CADIN_H0 L0_CADOUT_H0 AD1 HT_CPU_NB_CAD_H0 (12)

(12) HT_NB_CPU_CAD_L0 E2 L0_CADIN_L0 L0_CADOUT_L0 AC1 HT_CPU_NB_CAD_L0 (12)
(12) HT_NB_CPU_CAD_H1 E1 L0_CADIN_H1 L0_CADOUT_H1 AC2 HT_CPU_NB_CAD_H1 (12)
(12) HT_NB_CPU_CAD_L1 F1 L0_CADIN_L1 L0_CADOUT_L1 AC3 HT_CPU_NB_CAD_L1 (12)
(12) HT_NB_CPU_CAD_H2 G3 L0_CADIN_H2 L0_CADOUT_H2 AB1 HT_CPU_NB_CAD_H2 (12)
(12) HT_NB_CPU_CAD_L2 G2 L0_CADIN_L2 L0_CADOUT_L2 AA1 HT_CPU_NB_CAD_L2 (12)
(12) HT_NB_CPU_CAD_H3 G1 L0_CADIN_H3 L0_CADOUT_H3 AA2 HT_CPU_NB_CAD_H3 (12)
(12) HT_NB_CPU_CAD_L3 H1 L0_CADIN_L3 L0_CADOUT_L3 AA3 HT_CPU_NB_CAD_L3 (12)
(12) HT_NB_CPU_CAD_H4 J1 L0_CADIN_H4 L0_CADOUT_H4 W2 HT_CPU_NB_CAD_H4 (12)
(12) HT_NB_CPU_CAD_L4 K1 L0_CADIN_L4 L0_CADOUT_L4 W3 HT_CPU_NB_CAD_L4 (12)
(12) HT_NB_CPU_CAD_H5 L3 L0_CADIN_H5 L0_CADOUT_H5 V1 HT_CPU_NB_CAD_H5 (12)
(12) HT_NB_CPU_CAD_L5 L2 L0_CADIN_L5 L0_CADOUT_L5 U1 HT_CPU_NB_CAD_L5 (12)
(12) HT_NB_CPU_CAD_H6 L1 L0_CADIN_H6 L0_CADOUT_H6 U2 HT_CPU_NB_CAD_H6 (12)
C
(12) HT_NB_CPU_CAD_L6 M1 L0_CADIN_L6 L0_CADOUT_L6 U3 HT_CPU_NB_CAD_L6 (12)
C
(12) HT_NB_CPU_CAD_H7 N3 L0_CADIN_H7 L0_CADOUT_H7 T1 HT_CPU_NB_CAD_H7 (12)

(12) HT_NB_CPU_CAD_L7 N2 L0_CADIN_L7 L0_CADOUT_L7 R1 HT_CPU_NB_CAD_L7 (12)
(12) HT_NB_CPU_CAD_H8 E5 L0_CADIN_H8 L0_CADOUT_H8 AD4 HT_CPU_NB_CAD_H8 (12)
(12) HT_NB_CPU_CAD_L8 F5 L0_CADIN_L8 L0_CADOUT_L8 AD3 HT_CPU_NB_CAD_L8 (12)
(12) HT_NB_CPU_CAD_H9 F3 L0_CADIN_H9 L0_CADOUT_H9 AD5 HT_CPU_NB_CAD_H9 (12)
(12) HT_NB_CPU_CAD_L9 F4 L0_CADIN_L9 L0_CADOUT_L9 AC5 HT_CPU_NB_CAD_L9 (12)
(12) HT_NB_CPU_CAD_H10 G5 L0_CADIN_H10 L0_CADOUT_H10 AB4 HT_CPU_NB_CAD_H10 (12)
(12) HT_NB_CPU_CAD_L10 H5 L0_CADIN_L10 L0_CADOUT_L10 AB3 HT_CPU_NB_CAD_L10 (12)
(12) HT_NB_CPU_CAD_H11 H3 L0_CADIN_H11 L0_CADOUT_H11 AB5 HT_CPU_NB_CAD_H11 (12)
(12) HT_NB_CPU_CAD_L11 H4 L0_CADIN_L11 L0_CADOUT_L11 AA5 HT_CPU_NB_CAD_L11 (12)
(12) HT_NB_CPU_CAD_H12 K3 L0_CADIN_H12 L0_CADOUT_H12 Y5 HT_CPU_NB_CAD_H12 (12)
(12) HT_NB_CPU_CAD_L12 K4 L0_CADIN_L12 L0_CADOUT_L12 W5 HT_CPU_NB_CAD_L12 (12)
(12) HT_NB_CPU_CAD_H13 L5 L0_CADIN_H13 L0_CADOUT_H13 V4 HT_CPU_NB_CAD_H13 (12)
(12) HT_NB_CPU_CAD_L13 M5 L0_CADIN_L13 L0_CADOUT_L13 V3 HT_CPU_NB_CAD_L13 (12)
(12) HT_NB_CPU_CAD_H14 M3 L0_CADIN_H14 L0_CADOUT_H14 V5 HT_CPU_NB_CAD_H14 (12)
(12) HT_NB_CPU_CAD_L14 M4 L0_CADIN_L14 L0_CADOUT_L14 U5 HT_CPU_NB_CAD_L14 (12)
N5 T4
SKT-BGA638H176 (12)
(12)
HT_NB_CPU_CAD_H15
HT_NB_CPU_CAD_L15 P5
L0_CADIN_H15
L0_CADIN_L15
L0_CADOUT_H15
L0_CADOUT_L15 T3
HT_CPU_NB_CAD_H15 (12)
HT_CPU_NB_CAD_L15 (12)
J3 Y1
B
1'nd 62.10055.111 (12)
(12)
(12)
HT_NB_CPU_CLK_H0
HT_NB_CPU_CLK_L0
HT_NB_CPU_CLK_H1
J2
J5
L0_CLKIN_H0
L0_CLKIN_L0
L0_CLKIN_H1
L0_CLKOUT_H0
L0_CLKOUT_L0
L0_CLKOUT_H1
W1
Y4
HT_CPU_NB_CLK_H0
HT_CPU_NB_CLK_L0
HT_CPU_NB_CLK_H1
(12)
(12)
(12)
B
2'nd 62.10055.171 (12)
(12)
HT_NB_CPU_CLK_L1
HT_NB_CPU_CTL_H0
K5
N1
L0_CLKIN_L1
L0_CTLIN_H0
L0_CLKOUT_L1
L0_CTLOUT_H0
Y3
R2
HT_CPU_NB_CLK_L1
HT_CPU_NB_CTL_H0
(12)
(12)
(12) HT_NB_CPU_CTL_L0 P1 L0_CTLIN_L0 L0_CTLOUT_L0 R3 HT_CPU_NB_CTL_L0 (12)
(12) HT_NB_CPU_CTL_H1 P3 L0_CTLIN_H1 L0_CTLOUT_H1 T5 HT_CPU_NB_CTL_H1 (12)
(12) HT_NB_CPU_CTL_L1 P4 L0_CTLIN_L1 L0_CTLOUT_L1 R5 HT_CPU_NB_CTL_L1 (12)
<Core Design>
A
Title
CPU_HT_LINK I/F_(1/4)
A4
5 4 3 2 1
5 4 3 2 1
SSID = CPU (18) M_A_DQ[63..0]

3 OF 6 CPU1C
M_B_DQ[63..0] (19)
M_A_DQ0 G12 C11 M_B_DQ0
M_A_DQ1 MA_DATA0 MB_DATA0 M_B_DQ1
F12 MA_DATA1 MB_DATA1 A11
DANUBE
M_A_DQ2 H14 A14 M_B_DQ2
G14 MA_DATA3 MB_DATA3 B14
M_A_DQ4 H11 G11 M_B_DQ4
MA_DATA4 MB_DATA4
1231-2 4.7UF*4 M_A_DQ5 H12 MA_DATA5 MB_DATA5 E11 M_B_DQ5
0.22UF*4 M_A_DQ6 C13 D12 M_B_DQ6
D
Set empty: C905,C906,C903,C909,C913,C910,C915 1000PF*4 M_A_DQ8
E13
H15
MA_DATA7 MB_DATA7 A13
A15 M_B_DQ8 D
180PF*4 M_A_DQ9 MA_DATA8 MB_DATA8 M_B_DQ9
E15 MA_DATA9 MB_DATA9 A16
M_A_DQ10 E17 A19 M_B_DQ10
H17 MA_DATA11 MB_DATA11 A20
M_A_DQ12 E14 C14 M_B_DQ12
+CPU_VDDR M_A_DQ13 MA_DATA12 MB_DATA12 M_B_DQ13
Place near to CPU M_A_DQ14
F14
C17
MA_DATA13 MB_DATA13 D14
C18 M_B_DQ14
G17 MA_DATA15 MB_DATA15 D18
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
SC4D7U6D3V3KX-GP
SC1000P50V3JN-GP-U
SC1000P50V3JN-GP-U
SC1000P50V3JN-GP-U
SC180P50V2JN-1GP
SC180P50V2JN-1GP
SC180P50V2JN-1GP
SC180P50V2JN-1GP
M_A_DQ16 G18 D20 M_B_DQ16
C19 MA_DATA17 MB_DATA17 A21
1
1
C901
C902
C903
C913
C904
C914
C905
C906
C907
C915
C908
C909
C910
C911
C916
C912
M_A_DQ18 D22 D24 M_B_DQ18
E20 MA_DATA19 MB_DATA19 C25
DY DY DY DY DY DY DY M_A_DQ20 E18 B20 M_B_DQ20
2
2
F18 MA_DATA21 MB_DATA21 C20
M_A_DQ22 B22 B24 M_B_DQ22
C23 MA_DATA23 MB_DATA23 C24
M_A_DQ24 F20 E23 M_B_DQ24
1119-3 1231-2 M_A_DQ26
F22
H24
MA_DATA25 MB_DATA25 E24
G25 M_B_DQ26
J19 MA_DATA27 MB_DATA27 G26
M_A_DQ28 E21 C26 M_B_DQ28
E22 MA_DATA29 MB_DATA29 D26
M_A_DQ30 H20 G23 M_B_DQ30
H22 MA_DATA31 MB_DATA31 G24
M_A_DQ32 Y24 AA24 M_B_DQ32
+CPU_VDDR 0.9V, 1.25A--DDR1066 M_A_DQ34
AB24 MA_DATA33 MB_DATA33 AA23
M_B_DQ34
AB22 MA_DATA34 MB_DATA34 AD24
1.05V, 1.75A---DDR1333 M_A_DQ35 AA21 AE24 M_B_DQ35
W22 MA_DATA36 MB_DATA36 AA26
C M_A_DQ37 W21 AA25 M_B_DQ37 C
CPU1B 2 OF 6 +1.5V_SUS M_A_DQ38 MA_DATA37 MB_DATA37 M_B_DQ38
Y22 MA_DATA38 MB_DATA38 AD26
M_A_DQ39 M_B_DQ39
D10 W10
1119-3 M_A_DQ40
AA22
Y20
MA_DATA39 MB_DATA39 AE25
AC22 M_B_DQ40
VDDR VDDR MA_DATA40 MB_DATA40
SCD1U10V2KX-5GPSCD1U10V2KX-5GP
C10 AC10 M_A_DQ41 AA20 AD22 M_B_DQ41
DANUBE
1
1KR3F-GP
B10 AB10 M_A_DQ42 AA18 AE20 M_B_DQ42
1
+1.5V_SUS
C918
R902
AD10 AA10 M_A_DQ43 AB18 AF20 M_B_DQ43
VDDR VDDR M_A_DQ44 MA_DATA43 MB_DATA43 M_B_DQ44
VDDR A10 +0.75V_SUS_CPU_M_VREF AB21 MA_DATA44 MB_DATA44 AF24
R901 1 2 39D2R2F-L-GP MEMZP AF10 M_A_DQ45 AD21 AF23 M_B_DQ45
2
R903 1 MEMZP MA_DATA45 MB_DATA45
2 39D2R2F-L-GP MEMZN AE10 Y10 TP_CPU_VDDR_SENSE 1 TP901 M_A_DQ46 AD19 AC20 M_B_DQ46
2
MEMZN VDDR_SENSE M_A_DQ47 MA_DATA46 MB_DATA46 M_B_DQ47
DY 1117-8 Y18 AD20
SC10U6D3V3MX-GP

(18) DDR3_A_DRAMRST# H16 MA_RESET# MEMVREF W17 AD17 MA_DATA48 MB_DATA48 AD18
1
SC1000P50V3JN-GP-U
C917 M_A_DQ49 M_B_DQ49
Remove W16 MA_DATA49 MB_DATA49 AE18
1
1KR3F-GP
T19 B18 M_A_DQ50 W14 AC14 M_B_DQ50
(18) MEM_MA0_ODT0 MA0_ODT0 MB_RESET# DDR3_B_DRAMRST# (19) MA_DATA50 MB_DATA50
1
C919
C920
R905
V22 M_A_DQ51 Y14 AD14 M_B_DQ51
(18) MEM_MA0_ODT1
2
MA0_ODT1 M_A_DQ52 MA_DATA51 MB_DATA51 M_B_DQ52

U21 MA1_ODT0 MB0_ODT0 W26 MEM_MB0_ODT0 (19) Y17 MA_DATA52 MB_DATA52 AF19
V19 W23 M_A_DQ53 AB17 AC18 M_B_DQ53
MEM_MB0_ODT1 (19)
2
MA1_ODT1 MB0_ODT1 M_A_DQ54 MA_DATA53 MB_DATA53 M_B_DQ54
Y26 AB15 AF16
2
MB1_ODT0 M_A_DQ55 MA_DATA54 MB_DATA54 M_B_DQ55
(18) MEM_MA0_CS#0 T20 MA0_CS#0 AD15 MA_DATA55 MB_DATA55 AF15
U19 V26 M_A_DQ56 AB13 AF13 M_B_DQ56
(18) MEM_MA0_CS#1 MA0_CS#1 MB0_CS#0 MEM_MB0_CS#0 (19) MA_DATA56 MB_DATA56
U20 W25 M_A_DQ57 AD13 AC12 M_B_DQ57
MA1_CS#0 MB0_CS#1 MEM_MB0_CS#1 (19) MA_DATA57 MB_DATA57
M_A_DQ58 M_B_DQ58
V20 MA1_CS#1 MB1_CS#0 U22 1119-1 CLOSE TO CPU M_A_DQ59
Y12
W11
MA_DATA58 MB_DATA58 AB11
Y11 M_B_DQ59
(18) MEM_MA_CKE0 J22 MA_CKE0 MB_CKE0 J25 MEM_MB_CKE0 (19) AB14 MA_DATA60 MB_DATA60 AE14
(18) MEM_MA_CKE1 J20 H26 M_A_DQ61 AA14 AF14 M_B_DQ61
MA_CKE1 MB_CKE1 MEM_MB_CKE1 (19) MA_DATA61 MB_DATA61
M_A_DQ62 AB12 AF11 M_B_DQ62
(18) MEM_MA_CLK0_P N19 MA_CLK_H5 MB_CLK_H5 P22 MEM_MB_CLK0_P (19) AA12 MA_DATA63 MB_DATA63 AD11
(18) MEM_MA_CLK0_N N20 MA_CLK_L5 MB_CLK_L5 R22 MEM_MB_CLK0_N (19) (18) M_A_DM[7..0] M_B_DM[7..0] (19)
E16 A17 M_A_DM0 E12 A12 M_B_DM0
B MA_CLK_H1 MB_CLK_H1 M_A_DM1 MA_DM0 MB_DM0 M_B_DM1 B
F16 MA_CLK_L1 MB_CLK_L1 A18 C15 MA_DM1 MB_DM1 B16
Y16 AF18 M_A_DM2 E19 A22 M_B_DM2
MA_CLK_H7 MB_CLK_H7 M_A_DM3 MA_DM2 MB_DM2 M_B_DM3
AA16 MA_CLK_L7 MB_CLK_L7 AF17 F24 MA_DM3 MB_DM3 E25
P19 R26 M_A_DM4 AC24 AB26 M_B_DM4
(18) MEM_MA_CLK1_P MA_CLK_H4 MB_CLK_H4 MEM_MB_CLK1_P (19) MA_DM4 MB_DM4
P20 R25 M_A_DM5 Y19 AE22 M_B_DM5
(18) MEM_MA_CLK1_N MA_CLK_L4 MB_CLK_L4 MEM_MB_CLK1_N (19) MA_DM5 MB_DM5
M_A_DM6 AB16 AC16 M_B_DM6
(18) MEM_MA_ADD[0..15] MEM_MB_ADD[0..15] (19) MA_DM6 MB_DM6
MEM_MA_ADD0 N21 P24 MEM_MB_ADD0 M_A_DM7 Y13 AD12 M_B_DM7
MEM_MA_ADD1 MA_ADD0 MB_ADD0 MEM_MB_ADD1 MA_DM7 MB_DM7
M20 MA_ADD1 MB_ADD1 N24
MEM_MA_ADD2 N22 P26 MEM_MB_ADD2 G13 C12
MA_ADD2 MB_ADD2 (18) M_A_DQS0 MA_DQS_H0 MB_DQS_H0 M_B_DQS0 (19)
MEM_MA_ADD3 M19 N23 MEM_MB_ADD3 H13 B12
MA_ADD3 MB_ADD3 (18) M_A_DQS#0 MA_DQS_L0 MB_DQS_L0 M_B_DQS#0 (19)
MEM_MA_ADD4 M22 N26 MEM_MB_ADD4 G16 D16
MEM_MA_ADD5 L20 L23 MEM_MB_ADD5 G15 C16
MEM_MA_ADD6 M24 N25 MEM_MB_ADD6 C22 A24
MEM_MA_ADD7 L21 L24 MEM_MB_ADD7 C21 A23
MEM_MA_ADD8 L19 M26 MEM_MB_ADD8 G22 F26
MEM_MA_ADD9 K22 K26 MEM_MB_ADD9 G21 E26
MEM_MA_ADD10 R21 T26 MEM_MB_ADD10 AD23 AC25
MEM_MA_ADD11 L22 L26 MEM_MB_ADD11 AC23 AC26
MEM_MA_ADD12 K20 L25 MEM_MB_ADD12 AB19 AF21
MEM_MA_ADD13 V24 W24 MEM_MB_ADD13 AB20 AF22
MEM_MA_ADD14 K24 J23 MEM_MB_ADD14 Y15 AE16
MEM_MA_ADD15 K19 J24 MEM_MB_ADD15 W15 AD16
(18) M_A_DQS7 W12 MA_DQS_H7 MB_DQS_H7 AF12 M_B_DQS7 (19)
(18) MEM_MA_BANK0 R20 MA_BANK0 MB_BANK0 R24 MEM_MB_BANK0 (19) (18) M_A_DQS#7 W13 MA_DQS_L7 MB_DQS_L7 AE12 M_B_DQS#7 (19)
(18) MEM_MA_BANK1 R23 MA_BANK1 MB_BANK1 U26 MEM_MB_BANK1 (19)
(18) MEM_MA_BANK2 J21 MA_BANK2 MB_BANK2 J26 MEM_MB_BANK2 (19)
(18) MEM_MA_RAS# R19 MA_RAS# MB_RAS# U25 MEM_MB_RAS# (19)

A (18) MEM_MA_CAS# T22 MA_CAS# MB_CAS# U24 MEM_MB_CAS# (19) <Core Design> A
(18) MEM_MA_W E# T24 MA_WE# MB_WE# U23 MEM_MB_W E# (19)
Wistron Corporation
Title
CPU_DDR_(2/4)
5 4 3 2 1
5 4 3 2 1
SSID = CPU LYAOUT:ROUTE VDDA TRACE APPROX.

50mils WIDE(USE 2X25 mil TRACES TO
EXIT BALL FIELD) AND 500 mils LONG.
+2.5V_RUN 1119-1 +2.5V_RUN_VDDA

L1001
2.5V(250mA) for VDDA
1 2 1225-4
SC180P50V2JN-1GP
SC10U10V5ZY-1GP
SCD22U10V2KX-1GP
D PBY160808T-330Y-N-GP D
C1001
C1002
33R, 3A
SC3300P50V3KX-1GP
C1004
1
1
C1003
+1.5V_SUS +1.5V_SUS
9/25 9/14
2
11/6
4
3
1
1KR2J-1-GP
300R2J-4-GP
CPU1D 4 OF 6 RN1006
R1006
R1007
SRN1KJ-7-GP
F8 VDDA VSS M11
Cloce To CPU F9 W18
DANUBE
+1.5V_RUN R1008 1 VDDA RSVD#W18
2169R2F-GP
1
2
2
C1005 1 2SC3900P50V2KX-2GP CPUCLK_IN
10/5 (7) CPU_CLK
C1006 1 2SC3900P50V2KX-2GP CPUCLK_IN#
A9 CLKIN_H SVC A6 CPU_SVC (47)
CPU_CLK(200MHz) (7) CPU_CLK# A8 CLKIN_L SVD A4 CPU_SVD (47)
CPU_R_LDT_RST# B7 RESET#
4
3
SCD1U10V2KX-5GP
CPU_R_LDT_PW RGD A7 PWROK
C1007
RN1001 R1009 CPU_R_LDT_STOP# CPU_THERMTRIP#
0108-5 F10 LDTSTOP# THERMTRIP# AF6
1
For HDT DBG HDT_RST_R#1 CPU_LDT_REQ# CPU_PROCHOT#
SRN300J-3-GP
DY 2 C6 LDTREQ# PROCHOT# AC7
AA8 CPU_MEMHOT# 1
CPU_PROCHOT# (20)
MEMHOT# TP1002
1231-1 0R2J-2-GP
Close CPU DY CPU_SIC AF4 S1G4 not support MEMHOT
2
CPU_SID SIC
AF5
1
2
SID
EC1001
SCD01U16V2KX-3GP
1 2 CPU_R_LDT_RST# CPU_ALERT# AE6 W7
(20) CPU_LDT_RST# +1.1V_RUN ALERT# THERMDC H_THERMDC (39)
R1001 0R0402-PAD W8
THERMDA H_THERMDA (39)
1
1 2 CPU_R_LDT_PW RGD R1010 1 2 44D2R2F-GP CPU_HTREF0 R6
(20,42) CPU_LDT_PW RGD HT_REF0
R1002 0R0402-PAD R1011 1 2 44D2R2F-GP CPU_HTREF1 P6
CPU_R_LDT_STOP# HT_REF1
(13,20) CPU_LDT_STOP# 1 2
DY
2
C1008
R1003 0R0402-PAD SC10P50V2JN-4GP TP_CPU_VDDIO_SUS_FB_H
(47) CPU_VDD0_RUN_FB_H F6 VDD0_FB_H VDDIO_FB_H W9
1
TP_CPU_VDDIO_SUS_FB_L
C
11/6 (47) CPU_VDD0_RUN_FB_L E6 VDD0_FB_L VDDIO_FB_L Y9
C
(47) CPU_VDD1_RUN_FB_H Y6 H6
2
VDD1_FB_H VDDNB_FB_H CPU_VDDNB_RUN_FB_H (47)

9/11 S1g4 no support LDTREQ# (47) CPU_VDD1_RUN_FB_L AB6 VDD1_FB_L VDDNB_FB_L G6 CPU_VDDNB_RUN_FB_L (47)
1231-2 CPU_DBRDY G10 R1015
+1.5V_RUN CPU_TMS DBRDY CPU_DBREQ# 1
AA9 TMS DBREQ# E10 2 +1.5V_SUS
+1.5V_SUS CPU_TCK
R1012 1 2 300R2J-4-GP CPU_LDT_REQ#
1129-1 CPU_TRST#
AC9 TCK CPU_TDO 300R2J-4-GP
DY CPU_TDI
AD9
AF9
TRST# TDO AE9
TDI
1
R1013 1 300R2J-4-GP CPU_DBRDY 1 CPU_TEST23 TP_CPU_TEST28_H

R1014 1 DY 2
300R2J-4-GP TP_CPU_TEST14 R1018 R1019
AD7 TEST23 TEST28_H J7
TP_CPU_TEST28_L
R1016 1 DY 2
300R2J-4-GP TP_CPU_TEST15 510R2F-L-GP DY 510R2F-L-GP CPU_TEST18 TEST28_L H8
R1017 1 DY 2
2 1KR2J-1-GP CPU_TEST23 CPU_TEST19
H10
G9
TEST18
D7 TP_CPU_TEST17
R1025 1 1KR2J-1-GP CPU_TEST12 TEST19 TEST17 TP_CPU_TEST16
2 E7
2
CPU_TEST25_H TEST16 TP_CPU_TEST15

E9 TEST25_H TEST15 F7
RN1002 1 4 SRN1KJ-7-GP CPU_TEST18 CPU_TEST25_L E8 C7 TP_CPU_TEST14
CPU_TEST19 TEST25_L TEST14 +1.1V_RUN
2 3
CPU_TEST21 AB8 C3 TP_CPU_TEST7
TEST21 TEST7
1
CPU_TEST20 CPU_TEST10
R1020
AF7 TEST20 TEST10 K8 1
DY 2
RN1004 510R2F-L-GP DYR1022

510R2F-L-GP
1231-1 CPU_TEST24
CPU_TEST22
AE7
AE8
TEST24
C4
R1021
TP_CPU_TEST8
300R3-GP
CPU_TEST20 CPU_TEST12 TEST22 TEST8

1 8 AC8 TEST12
2 7 CPU_TEST21 CPU_TEST27 AF8
2
CPU_TEST24 R1023 TEST27 CPU_TEST29H

3 6 TEST29_H C9
CPU_TEST22 CPU_TEST9 CPU_TEST29L
4 5 1 2 C2
AA6
TEST9 TEST29_L C8
R1024
1 2
80D6R2F-L-GP
LAYOUT: Route FBCLKOUT_H/L
SRN1KJ-8-GP 0R0402-PAD TEST6
differentially impedance 80
B 1231-1 1231-1 A3
A5
RSVD#A3 RSVD#H18 H18
H19
B
HDT Connectors
RSVD#A5 RSVD#H19
B3 RSVD#B3 RSVD#AA7 AA7
+1.5V_SUS B5 D5
RSVD#B5 RSVD#D5
C1 RSVD#C1 RSVD#C5 C5
2
R1026 HDT1
1KR2J-1-GP +1.5V_SUS 1 2
11/11 DY 4
11/6 3
2 1
CPU_TEST27
9/22 5 6
3
4
+KBC_PW R +1.5V_RUN
2K2R2J-2-GP
1KR2J-1-GP
CPU_DBREQ# 7 8
R1032
R1033
R1029 RN1005 CPU_DBRDY 9 10

CPU_TCK
DY 300R2J-4-GP SRN1KJ-7-GP 11 12
1
8K2R2J-3-GP
2K2R2J-2-GP
CPU_TMS 13 14
R1027
R1028
TP1001 1 TP_CPU_VDDIO_SUS_FB_H CPU_TDI 15 16
1
TP1003 TP_CPU_VDDIO_SUS_FB_L CPU_TRST#

1
DY 17 18
2
1
TP1004 1 TP_CPU_TEST28_H CPU_SIC CPU_TDO 19 20

(21) CPU_SIC
TP1005 1 TP_CPU_TEST28_L 21 22
1 2
1
TP1006 1 TP_CPU_TEST17 (21) CPU_SID CPU_SID +1.5V_SUS 23 24

TP1007 1 TP_CPU_TEST16 26
TP1008 TP_CPU_TEST15 CPU_ALERT# CPU_R_LDT_RST#1
TP1009
1
1 TP_CPU_TEST14
(21,39) TALERT# 3 2
3 2 CPU_THERMTRIP# 1.5V R1038 DY0R2J-2-GP
2
SMC-CONN26A-FP
Q1001 (21,37,39,42,82) H_THERMTRIP#
TP1010 1 TP_CPU_TEST8
TP1011 TP_CPU_TEST7 PMBS3904-1-GP Q1002 HDT_RST#
1
PMBS3904-1-GP
3.3V
1229-1 For old HDT tool (3.3V level)
+3.3V_RUN +1.8V_RUN
+3.3V_RUN +1.5V_RUN +3.3V_RUN +1.8V_RUN
A <Core Design> A
1
10KR2J-3-GP
2K2R2J-2-GP
1
1
8K2R2J-3-GP
2K2R2J-2-GP
10KR2J-3-GP
2K2R2J-2-GP
R1034
R1035
Wistron Corporation
R1040
R1039
R1037
R1036

DY DY Taipei Hsien 221, Taiwan, R.O.C.
2
1 2
2
1 2
1 2
Title
Q1003
3
PMBS3904-1-GP
2 CPU_R_LDT_PW RGD
CPU_Control&Debug_(3/4)
(47) CPU_PW RGD_SVID_REG Size Document Number Rev
CPU_PROCHOT# HDT_RST# HDT_RST_R#
(37) CPU_PROCHOT#_EC 2 3
Q1004
3
DY 2PMBS3904-1-GP A3
Q1005 1
R1041 DY 2
0R2J-2-GP
PMBS3904-1-GP 0112-2 Date: Thursday, March 04, 2010 Sheet 10 of 95
5 4 3 2 1
5 4 3 2 1
SSID = CPU
D D
CPU1F 6 OF 6 (36A) for 35W S1G4 VDD

AA4 VSS VSS J6
+VCC_CORE CPU1E 5 OF 6 +VCC_CORE
DANUBE
AA11 VSS VSS J8
AA13
AA15
VSS VSS J10
J12
Bottom Side Decoupling G4 P8
Bottom Side Decoupling
VSS VSS VDD VDD
SC22U6D3V5MX-2GP
SC10U6D3V5KX-1GP
SC22U6D3V5MX-2GP
SC10U6D3V5KX-1GP
SCD22U10V2KX-1GP
SC180P50V2JN-1GP
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
SCD22U10V2KX-1GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
AA17 J14 H2 P10
DANUBE
VSS VSS VDD VDD
SCD01U16V2KX-3GP
AA19 VSS VSS J16 J9 VDD VDD R4
C1101
C1103
C1104
C1105
C1102
C1106
C1107
C1108
C1109
C1110
C1111
C1112
C1141
C1114
AB2 VSS VSS J18 J11 VDD VDD R7
1
AB7 VSS VSS K2 J13 VDD VDD R9
AB9 VSS VSS K7 J15 VDD VDD R11
AB23 K9
DY K6 T2
DY DY
2
VSS VSS VDD VDD
AB25 VSS VSS K11 K10 VDD VDD T6
AC11 VSS VSS K13 K12 VDD VDD T8
AC13 VSS VSS K15 K14 VDD VDD T10
AC15
AC17
VSS VSS K17
L6
1231-2 1119-3 L4
L7
VDD VDD T12
T14
1119-3 1231-2
VSS VSS VDD VDD
AC19 VSS VSS L8 L9 VDD VDD U7
AC21 VSS VSS L10 22uF *2 L11 VDD VDD U9 22uF *2
AD6 L12 L13 U11
C AD8
VSS VSS
L14
10uF *2 L15
VDD VDD
U13
10uF *2 C
VSS VSS VDD VDD
AD25 VSS VSS L16 0.22uF *1 M2 VDD VDD U15 0.22uF *1
AE11 VSS VSS L18 0.01uF *1 M6 VDD VDD V6 0.01uF *1
AE13 VSS VSS M7 M8 VDD VDD V8
AE15 M9 180pF *1 M10 V10 180pF *1
VSS VSS VDD VDD
AE17 VSS VSS AC6 N7 VDD VDD V12
AE19 VSS VSS M17 N9 VDD VDD V14
+VDDNB
AE21
AE23
VSS VSS N4
N8
0.9V(4A) for VDDNB N11 VDD VDD W4
Y2
VSS VSS VDD
B4 VSS VSS N10 K16 VDDNB VDD AC4
SC22U6D3V5MX-2GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
B6 N16 M16 AD2 +1.5V_SUS
VSS VSS VDDNB VDD
B8 VSS VSS N18 P16 VDDNB Place near to CPU
C1115
C1116
C1117
B9 VSS VSS P2 T16 VDDNB VDDIO Y25
1
SC180P50V2JN-1GP
SC180P50V2JN-1GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
B11 VSS VSS P7 22UF *3 V16 VDDNB VDDIO V25
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
B13 VSS VSS P9 VDDIO V23
C1118
C1119
C1122
C1123
C1124
C1125
C1126
C1127
C1128
C1129
B15 P11
DY H25 V21
2
2
VSS VSS VDDIO VDDIO
1
B17 VSS VSS P17 J17 VDDIO VDDIO V18
B19 VSS VSS R8 K18 VDDIO VDDIO U17
B21 R10 K21 T25
DY DY DY DY DY DY DY
2
VSS VSS VDDIO VDDIO
B23
B25
VSS VSS R16
R18
1231-2 K23
K25
VDDIO VDDIO T23
T21
VSS VSS VDDIO VDDIO
D6 VSS VSS T7 L17 VDDIO VDDIO T18
D8 VSS VSS T9 M18 VDDIO VDDIO R17 1119-3 1231-2 1231-2
D9
D11
VSS VSS T11
T13 +1.5V_SUS 1.5V(3A) for VDDIO M21
M23
VDDIO VDDIO P25
P23
VSS VSS VDDIO VDDIO
D13 VSS VSS T15 Bottom Side Decoupling M25 VDDIO VDDIO P21
D15 VSS VSS T17 1119-1 N17 VDDIO VDDIO P18 0.01UF *1
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
SC180P50V2JN-1GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
D17 U4
VSS VSS 0.1UF *2
SCD01U16V2KX-3GP
D19 VSS VSS U6
B B
C1130
C1131
C1132
C1133
C1120
C1135
C1121
D21 VSS VSS U8 0.22UF *4
1
1
C1134
D23 VSS VSS U10 4.7UF *4

D25 VSS VSS U12
180PF *2 9/14
E4 U14
DY
2
2
VSS VSS
F2 VSS VSS U16
F11 VSS VSS U18
F13 VSS VSS V2
F15
F17
VSS VSS V7
V9
1231-2 1119-3
VSS VSS
F19 VSS VSS V11
F21 VSS VSS V13 10UF *2
F23 V15
F25
VSS VSS
V17
0.22UF *2
VSS VSS
H7 VSS VSS W6 180PF *1
H9 VSS VSS Y21
H21 VSS VSS Y23
H23 VSS VSS N6
J4 VSS
A <Core Design> A
Wistron Corporation
Title
CPU_Power_(4/4)
A3
5 4 3 2 1
5 4 3 2 1
U1A
(8) HT_CPU_NB_CAD_H0 Y25 HT_RXCAD0P HT_TXCAD0P D24 HT_NB_CPU_CAD_H0 (8)
Y24 PART 1 OF 6 D25
SSID = N.B (8)
(8)
(8)
HT_CPU_NB_CAD_L0
HT_CPU_NB_CAD_H1
HT_CPU_NB_CAD_L1
V22
V23
HT_RXCAD0N
HT_RXCAD1P
HT_RXCAD1N
HT_TXCAD0N
HT_TXCAD1P
HT_TXCAD1N
E24
E25
HT_NB_CPU_CAD_L0
HT_NB_CPU_CAD_H1
HT_NB_CPU_CAD_L1
(8)
(8)
(8)
(8) HT_CPU_NB_CAD_H2 V25 HT_RXCAD2P HT_TXCAD2P F24 HT_NB_CPU_CAD_H2 (8)
(8) HT_CPU_NB_CAD_L2 V24 HT_RXCAD2N HT_TXCAD2N F25 HT_NB_CPU_CAD_L2 (8)
RS880M : 71.RS880.M05 (8)
(8)
HT_CPU_NB_CAD_H3
HT_CPU_NB_CAD_L3
U24
U25
HT_RXCAD3P
HT_RXCAD3N
HT_TXCAD3P
HT_TXCAD3N
F23
F22
HT_NB_CPU_CAD_H3
HT_NB_CPU_CAD_L3
(8)
(8)
(8) HT_CPU_NB_CAD_H4 T25 HT_RXCAD4P HT_TXCAD4P H23 HT_NB_CPU_CAD_H4 (8)
(8) HT_CPU_NB_CAD_L4 T24 HT_RXCAD4N HT_TXCAD4N H22 HT_NB_CPU_CAD_L4 (8)
P22 J25
HYPER TRANSPORT CPU I/F

(8) HT_CPU_NB_CAD_H5 HT_RXCAD5P HT_TXCAD5P HT_NB_CPU_CAD_H5 (8)
(8) HT_CPU_NB_CAD_L5 P23 HT_RXCAD5N HT_TXCAD5N J24 HT_NB_CPU_CAD_L5 (8)
D (8) HT_CPU_NB_CAD_H6 P25 HT_RXCAD6P HT_TXCAD6P K24 HT_NB_CPU_CAD_H6 (8) D
(8) HT_CPU_NB_CAD_L6 P24 HT_RXCAD6N HT_TXCAD6N K25 HT_NB_CPU_CAD_L6 (8)
(8) HT_CPU_NB_CAD_H7 N24 HT_RXCAD7P HT_TXCAD7P K23 HT_NB_CPU_CAD_H7 (8)
(8) HT_CPU_NB_CAD_L7 N25 HT_RXCAD7N HT_TXCAD7N K22 HT_NB_CPU_CAD_L7 (8)
(8) HT_CPU_NB_CAD_H8 AC24 HT_RXCAD8P HT_TXCAD8P F21 HT_NB_CPU_CAD_H8 (8)

(8) HT_CPU_NB_CAD_L8 AC25 HT_RXCAD8N HT_TXCAD8N G21 HT_NB_CPU_CAD_L8 (8)
(8) HT_CPU_NB_CAD_H9 AB25 HT_RXCAD9P HT_TXCAD9P G20 HT_NB_CPU_CAD_H9 (8)
(8) HT_CPU_NB_CAD_L9 AB24 HT_RXCAD9N HT_TXCAD9N H21 HT_NB_CPU_CAD_L9 (8)
(8) HT_CPU_NB_CAD_H10 AA24 HT_RXCAD10P HT_TXCAD10P J20 HT_NB_CPU_CAD_H10 (8)
(8) HT_CPU_NB_CAD_L10 AA25 HT_RXCAD10N HT_TXCAD10N J21 HT_NB_CPU_CAD_L10 (8)
(8) HT_CPU_NB_CAD_H11 Y22 HT_RXCAD11P HT_TXCAD11P J18 HT_NB_CPU_CAD_H11 (8)
(8) HT_CPU_NB_CAD_L11 Y23 HT_RXCAD11N HT_TXCAD11N K17 HT_NB_CPU_CAD_L11 (8)
(8) HT_CPU_NB_CAD_H12 W21 HT_RXCAD12P HT_TXCAD12P L19 HT_NB_CPU_CAD_H12 (8)
(8) HT_CPU_NB_CAD_L12 W20 HT_RXCAD12N HT_TXCAD12N J19 HT_NB_CPU_CAD_L12 (8)
V21 M19 PCIE_NTX_GRX_P[12..15]
(8) HT_CPU_NB_CAD_H13 HT_RXCAD13P HT_TXCAD13P HT_NB_CPU_CAD_H13 (8) PCIE_NTX_GRX_P[12..15] (57)
(8) HT_CPU_NB_CAD_L13 V20 HT_RXCAD13N HT_TXCAD13N L18 HT_NB_CPU_CAD_L13 (8)
U20 M21 PCIE_NTX_GRX_N[12..15]
(8) HT_CPU_NB_CAD_H14 HT_RXCAD14P HT_TXCAD14P HT_NB_CPU_CAD_H14 (8) PCIE_NTX_GRX_N[12..15] (57)
(8) HT_CPU_NB_CAD_L14 U21 HT_RXCAD14N HT_TXCAD14N P21 HT_NB_CPU_CAD_L14 (8)
(8) HT_CPU_NB_CAD_H15 U19 HT_RXCAD15P HT_TXCAD15P P18 HT_NB_CPU_CAD_H15 (8)
(8) HT_CPU_NB_CAD_L15 U18 HT_RXCAD15N HT_TXCAD15N M18 HT_NB_CPU_CAD_L15 (8) PCIE_NTX_GRX_P[0..11]
PCIE_NTX_GRX_P[0..11] (80)
(8) HT_CPU_NB_CLK_H0 T22 HT_RXCLK0P HT_TXCLK0P H24 HT_NB_CPU_CLK_H0 (8)
T23 H25 PCIE_NTX_GRX_N[0..11]
(8) HT_CPU_NB_CLK_L0 HT_RXCLK0N HT_TXCLK0N HT_NB_CPU_CLK_L0 (8) PCIE_NTX_GRX_N[0..11] (80)
(8) HT_CPU_NB_CLK_H1 AB23 HT_RXCLK1P HT_TXCLK1P L21 HT_NB_CPU_CLK_H1 (8)
(8) HT_CPU_NB_CLK_L1 AA22 HT_RXCLK1N HT_TXCLK1N L20 HT_NB_CPU_CLK_L1 (8)
M22 M24 PCIE_NRX_GTX_P[0..15]
(8) HT_CPU_NB_CTL_H0 HT_RXCTL0P HT_TXCTL0P HT_NB_CPU_CTL_H0 (8) PCIE_NRX_GTX_P[0..15] (80)
(8) HT_CPU_NB_CTL_L0 M23 HT_RXCTL0N HT_TXCTL0N M25 HT_NB_CPU_CTL_L0 (8)
C R21 P19 PCIE_NRX_GTX_N[0..15] C
(8) HT_CPU_NB_CTL_H1 HT_RXCTL1P HT_TXCTL1P HT_NB_CPU_CTL_H1 (8) PCIE_NRX_GTX_N[0..15] (80)
(8) HT_CPU_NB_CTL_L1 R20 HT_RXCTL1N HT_TXCTL1N R18 HT_NB_CPU_CTL_L1 (8)
R1201 1 2 301R2F-GP HT_RXCALP C23 B24 HT_TXCALP R1202 1 2 301R2F-GP
HT_RXCALN HT_RXCALP HT_TXCALP HT_TXCALN
A24 HT_RXCALN HT_TXCALN B25
RS880M-1-GP
Place < 100mils from pin C23 and A24 Place < 100mils from pin B25 and B24
9/15 U1B
1119-3 9/15
PCIE_NRX_GTX_P15 D4 A5 PCIE_NTX_GRX_C_P15 C1231 1 2 SCD1U10V2KX-5GP PCIE_NTX_GRX_P15
PCIE_NRX_GTX_N15 GFX_RX0P GFX_TX0P PCIE_NTX_GRX_C_N15 C1232 1
C4 GFX_RX0N PART 2 OF 6 GFX_TX0N B5 2 SCD1U10V2KX-5GP PCIE_NTX_GRX_N15
PCIE_NRX_GTX_P14 A3 A4 PCIE_NTX_GRX_C_P14 C1229 1 2 SCD1U10V2KX-5GP PCIE_NTX_GRX_P14
B3 GFX_RX1N GFX_TX1N B4 2 SCD1U10V2KX-5GP PCIE_NTX_GRX_N14
PCIE_NRX_GTX_P13 C2 C3 PCIE_NTX_GRX_C_P13 C1227 1 2 SCD1U10V2KX-5GP PCIE_NTX_GRX_P13
C1 GFX_RX2N GFX_TX2N B2 2 SCD1U10V2KX-5GP PCIE_NTX_GRX_N13
PCIE_NRX_GTX_P12 E5 D1 PCIE_NTX_GRX_C_P12 C1225 1 2 SCD1U10V2KX-5GP PCIE_NTX_GRX_P12
PCIE_NRX_GTX_N12 GFX_RX3P GFX_TX3P PCIE_NTX_GRX_C_N12 C1226 1 2 SCD1U10V2KX-5GP PCIE_NTX_GRX_N12
LANE REVERSAL
F5 GFX_RX3N GFX_TX3N D2
PCIE_NRX_GTX_P11 PCIE_NTX_GRX_C_P11 C1223 1 SCD1U10V2KX-5GP
2DIS PCIE_NTX_GRX_P11
LANE REVERSAL
G5 GFX_RX4P GFX_TX4P E2
PCIE_NRX_GTX_N11 G6 E1 PCIE_NTX_GRX_C_N11 C1224 1 SCD1U10V2KX-5GP
2DIS PCIE_NTX_GRX_N11
PCIE_NRX_GTX_P10 GFX_RX4N GFX_TX4N PCIE_NTX_GRX_C_P10 C1221 1 SCD1U10V2KX-5GP PCIE_NTX_GRX_P10
H5 GFX_RX5P GFX_TX5P F4 2DIS
PCIE_NRX_GTX_N10 H6 F3 PCIE_NTX_GRX_C_N10 C1222 1 SCD1U10V2KX-5GP
J6 GFX_RX6P GFX_TX6P F1 2DIS
PCIE_NRX_GTX_N9 J5 F2 PCIE_NTX_GRX_C_N9 C1220 1 SCD1U10V2KX-5GP
J7 GFX_RX7P GFX_TX7P H4 2DIS
PCIE_NRX_GTX_N8 J8 H3 PCIE_NTX_GRX_C_N8 C1218 1 SCD1U10V2KX-5GP
L5 GFX_RX8P GFX_TX8P H1 2DIS
PCIE_NRX_GTX_N7 L6 H2 PCIE_NTX_GRX_C_N7 C1216 1 SCD1U10V2KX-5GP
M8 GFX_RX9P GFX_TX9P J2 2DIS
B PCIE_NRX_GTX_N6 PCIE_NTX_GRX_C_N6 C1214 1 SCD1U10V2KX-5GP PCIE_NTX_GRX_N6 B
L8 GFX_RX9N GFX_TX9N J1 2DIS
PCIE_NRX_GTX_P5 P7 K4 PCIE_NTX_GRX_C_P5 C1211 1 SCD1U10V2KX-5GP
PCIE I/F GFX
PCIE_NRX_GTX_N5 GFX_RX10P GFX_TX10P PCIE_NTX_GRX_C_N5 C1212 1 SCD1U10V2KX-5GP PCIE_NTX_GRX_N5

M7 GFX_RX10N GFX_TX10N K3 2DIS
PCIE_NRX_GTX_P4 P5 K1 PCIE_NTX_GRX_C_P4 C1209 1 SCD1U10V2KX-5GP
M5 GFX_RX11N GFX_TX11N K2 2DIS
PCIE_NRX_GTX_P3 R8 M4 PCIE_NTX_GRX_C_P3 C1207 1 SCD1U10V2KX-5GP
P8 GFX_RX12N GFX_TX12N M3 2DIS
PCIE_NRX_GTX_P2 R6 M1 PCIE_NTX_GRX_C_P2 C1205 1 SCD1U10V2KX-5GP
R5 GFX_RX13N GFX_TX13N M2 2DIS
PCIE_NRX_GTX_P1 P4 N2 PCIE_NTX_GRX_C_P1 C1203 1 SCD1U10V2KX-5GP
P3 GFX_RX14N GFX_TX14N N1 2DIS
PCIE_NRX_GTX_P0 T4 P1 PCIE_NTX_GRX_C_P0 C1201 1 SCD1U10V2KX-5GP
9/11 T3 GFX_RX15N GFX_TX15N P2 2DIS
(76) PCIE_RXP0 AE3 AC1 PCIE_C_TXP0 C1264 1 2 SCD1U10V2KX-5GP

GPP_RX0P GPP_TX0P PCIE_TXP0 (76)
PCIE_C_TXN0 C1261 1 SCD1U10V2KX-5GP
WLAN (76)
(76)
PCIE_RXN0
PCIE_RXP1
AD4
AE2
GPP_RX0N
GPP_RX1P
GPP_TX0N
GPP_TX1P
AC2
AB4 PCIE_C_TXP1 C1266 1
2
2 SCD1U10V2KX-5GP
PCIE_TXN0
PCIE_TXP1
(76)
(76)
WLAN
PCIE_C_TXN1 C1262 1 SCD1U10V2KX-5GP
LAN (76)
(76)
PCIE_RXN1
PCIE_RXP2
AD3
AD1
GPP_RX1N
GPP_RX2P
GPP_TX1N
GPP_TX2P
AB3
AA2 PCIE_C_TXP2 C1265 1
2
2 SCD1U10V2KX-5GP
PCIE_TXN1
PCIE_TXP2
(76)
(76)
LAN
PCIE I/F GPP PCIE_C_TXN2 C1263 1 SCD1U10V2KX-5GP
WWAN (76) PCIE_RXN2 AD2
V5
GPP_RX2N
GPP_RX3P
GPP_TX2N
GPP_TX3P
AA1
Y1
2 PCIE_TXN2 (76) WWAN
W6
U5
GPP_RX3N GPP_TX3N Y2
Y4
9/11
GPP_RX4P GPP_TX4P
U6 GPP_RX4N GPP_TX4N Y3
U8 GPP_RX5P GPP_TX5P V1
U7 GPP_RX5N GPP_TX5N V2
A-LINK
ALINK_NBTX_SBRX_C_P0 C1237 1 SCD1U10V2KX-5GP
A
A-LINK (20)
(20)
ALINK_NBRX_SBTX_P0
ALINK_NBRX_SBTX_N0
AA8
Y8
SB_RX0P
SB_RX0N
SB_TX0P
SB_TX0N
AD7
AE7 ALINK_NBTX_SBRX_C_N0 C1238 1
2
2 SCD1U10V2KX-5GP
ALINK_NBTX_SBRX_P0
ALINK_NBTX_SBRX_N0
(20)
(20) <Core Design> A
(20) ALINK_NBRX_SBTX_P1 AA7 AE6 ALINK_NBTX_SBRX_C_P1 C1239 1 2 SCD1U10V2KX-5GP
SB_RX1P SB_TX1P ALINK_NBTX_SBRX_P1 (20)
(20) ALINK_NBRX_SBTX_N1 Y7 AD6 ALINK_NBTX_SBRX_C_N1 C1240 1 2 SCD1U10V2KX-5GP
SB_RX1N SB_TX1N ALINK_NBTX_SBRX_N1 (20)
PCIE I/F SB ALINK_NBTX_SBRX_C_P2 C1241 1 SCD1U10V2KX-5GP
(20)
(20)
ALINK_NBRX_SBTX_P2
ALINK_NBRX_SBTX_N2
AA5
AA6
SB_RX2P
SB_RX2N
SB_TX2P
SB_TX2N
AB6
AC6 ALINK_NBTX_SBRX_C_N2 C1242 1
2
2 SCD1U10V2KX-5GP
ALINK_NBTX_SBRX_P2
ALINK_NBTX_SBRX_N2
(20)
(20)
Wistron Corporation
W5 AD5 ALINK_NBTX_SBRX_C_P3 C1243 1 2 SCD1U10V2KX-5GP 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
(20) ALINK_NBRX_SBTX_P3 SB_RX3P SB_TX3P ALINK_NBTX_SBRX_P3 (20)
Y5 AE5 ALINK_NBTX_SBRX_C_N3 C1244 1 2 SCD1U10V2KX-5GP Taipei Hsien 221, Taiwan, R.O.C.
(20) ALINK_NBRX_SBTX_N3 SB_RX3N SB_TX3N ALINK_NBTX_SBRX_N3 (20)
AC8 PCE_PCAL R1203 1 2 1K27R2F-L-GP Title
PCE_CALRP
PCE_CALRN AB8 PCE_NCAL R1204 1 2 2KR2F-3-GP +1.1V_RUN_VDDPCIE AMD-RS880M_HT LINK&PCIe(1/4)
RS880M-1-GP A3
Place < 100mils from pin AC8 and AB8 Berry AMD Discrete/UMA A00
5 4 3 2 1
5 4 3 2 1
UMA DAC Signal: STRAP_DEBUG_BUS_GPIO_ENABLE# ( RS880M use DAC_VSYNC)

GREEN/BLUE: Connected to GND through two separate +3.3V_RUN
SSID = N.B 150- 1% resistors.
*1
Enables debug bus access through memory I/O pads and GPIOs.
: Disable
0 : Enable
1
RED: Connected to GND through two separate 133- 1%
3KR2J-2-GP
3KR2J-2-GP
R1302
R1303
RS880M : 71.RS880.M05 resistors.(For match resistor on CRT/B 150- 1%) SIDE_PORT_EN# ( RS880M use DAC_HSYNC)
1 = Memory Side port Not available DIS
SPM_Disable
2
+1.1V_RUN +3.3V_RUN +3.3V_RUN_AVDD VGA_VSYNC 0 = Memory Side port available UMA_SPM
VGA_HSYNC
1.1V, 65mA 3.3V, 110mA
SC1U6D3V2KX-GP
L1308 1 R1342
D
UMA
2 D
1
C1307
3KR2J-2-GP
3KR2J-2-GP
PLLVDD LOAD_EEPROM_STRAPS#(RS880M use SUS_STAT#)
UMA
1 2
1
SC1U6D3V2KX-GP
R1304
R1305
0R3J-0-U-GP
C1312
BLM15AG221SS1D-GP 1 10/8 0106-2 DY Selects Loading of STRAPS From EEPROM
220R, 0.3A UMA/DIS *1 : use Default Values
2
SPM_Enable 0 : I2C Master can load strap values from EEPROM if connected,
2
UMA/DIS 10/8
2
or use default values if not connected

+1.8V_RUN +1.8V_RUN_AVDDDI
1.8V, 20mA *DEFAULT
SCD1U10V2KX-5GP
1 R1333
UMA2
C1306
1
+1.8V_RUN 0R3J-0-U-GP
L1307
1.8V, 20mA U1C
UMA/DIS
2
PLLVDD18
UMA
1 2 F12 AVDD1 TXOUT_L0P A22 VGA_TXAOUT0+ (55)
SC2D2U6D3V3KX-GP
1119-1 E12 AVDD2 PART 3 OF 6 TXOUT_L0N B22 VGA_TXAOUT0- (55)

BLM15AG221SS1D-GP +1.8V_RUN +1.8V_RUN_AVDDDQ F14 A21 VGA_TXAOUT1+ (55)
AVDDDI TXOUT_L1P
1
C1311
R1344
220R, 0.3A 1.8V, 4mA G15 AVSSDI TXOUT_L1N B21 VGA_TXAOUT1- (55)
UMA
2 1 H15
H14
AVDDQ TXOUT_L2P B20
A20
VGA_TXAOUT2+
VGA_TXAOUT2-
(55)
(55)
2
AVSSQ TXOUT_L2N
1
0R3J-0-U-GP C1308
UMA/DIS SC2D2U6D3V3KX-GP E17
TXOUT_L3P A19
B19
C_Pr TXOUT_L3N
UMA/DIS F17
2
Y
F15 COMP_Pb TXOUT_U0P B18 VGA_TXBOUT0+ (55)
9/22 A18
CRT/TVOUT
TXOUT_U0N VGA_TXBOUT0- (55)
Layout Note (77) M_RED UMA2150R2F-1-GP G18 RED TXOUT_U1P A17 VGA_TXBOUT1+ (55)
Trace at least 15 mil R1326 1 G17 REDb TXOUT_U1N B17 VGA_TXBOUT1- (55)
C (77) M_GREEN
1
UMA2 E18
F18
GREEN TXOUT_U2P D20
D21
VGA_TXBOUT2+
VGA_TXBOUT2-
(55)
(55)
C
R1327 GREENb TXOUT_U2N
+1.8V_RUN (77) M_BLUE UMA2150R2F-1-GP E19 BLUE TXOUT_U3P D18
L1301
1.8V, 20mA UMA: DAC_CLK and DATA R1328
1
150R2F-1-GP
F19 BLUEb TXOUT_U3N D19
+1.8V_VDDA18HTPLL VGA_HSYNC
1 2 1119-3 with 5V-tolerant. (77) VGA_HSYNC A11 DAC_HSYNC TXCLK_LP B16 VGA_TXACLK+ (55)
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
VGA_VSYNC B11 A16 VGA_TXACLK- (55) +1.8V_RUN

(77) VGA_VSYNC DAC_VSYNC TXCLK_LN
C1302
C1303
BLM15AG221SS1D-GP not need level shift (77) DDC_CLK_CON

DDC_CLK_CON F8 DAC_SCL TXCLK_UP D16 VGA_TXBCLK+ (55)
1
DDC_DATA_CON
220R, 0.3A (77) DDC_DATA_CON E8 DAC_SDA TXCLK_UN D17 VGA_TXBCLK- (55) 1119-1
Trace at least 10 mil 1 2 DAC_RSET G14 1.8V, 15mA 220R, 0.3A
2
R1306 715R2F-GP DAC_RSET

A13 VDDLTP18_R L1305 1
PLLVDD VDDLTP18 BLM15AG221SS1D-GP
2
UMA
10/8 PLLVDD18
A12 PLLVDD VSSLTP18 B13
D14 PLLVDD18 VDDLT18_R
1.8V, 300mA L1306 1
B12 PLLVSS VDDLT18_1 A15 2
PBY160808T-221Y-N-GP UMA
9/22 1.8V, 120mA VDDLT18_2 B15
SCD1U10V2KX-5GP
SC4D7U6D3V3KX-GP
C1313
+1.8V_VDDA18HTPLL H17 A14 220R, 2A
LVTM
VDDA18HTPLL VDDLT33_1
C1310
1 R1343 2 +1.8V_VDDA18PCIEPLL B14
PLL PWR
VDDLT33_2
1
SC2D2U6D3V3KX-GP
SCD1U10V2KX-5GP
+1.8V_VDDA18PCIEPLL D7 C1309
VDDA18PCIEPLL1
C1305
0R0603-PAD E7 C14 SC2D2U6D3V3KX-GP

VDDA18PCIEPLL2 VSSLT1
1
1
SC22U6D3V5MX-2GP
C1304
D15
UMA UMA/DIS UMA/DIS
2
VSSLT2
(20,37,80) PLTRST#_NB_GPU D8 SYSRESET# VSSLT3 C16
(41) NB_PW RGD_IN 9/16 A10 C18
2
POWERGOOD VSSLT4
1
C1301
+1.1V_RUN NB_LDT_STOP# C10 C20

LDTSTOP# VSSLT5
1
NB_ALLOW _LDTSTOP
1119-3 C12 ALLOW_LDTSTOP VSSLT6 E20
2
SC180P50V2JN-1GP SC180P50V2JN-1GP C22

2
EC1301 EC1302 VSSLT7

C25
CLOCKs PM
(7) CLK_NBHT_CLK
2
R1312 HT_REFCLKP
(7) CLK_NBHT_CLK# C24 HT_REFCLKN
4K7R2F-GP
1231-2 1 2 NB_REFCLK_P E11
11/12-4
(7) NB_14M_CLK
1
B R1341 0R0402-PAD NB_REFCLK_N REFCLK_P/OSCIN B

F11 REFCLK_N LVDS_DIGON E9 NB_LCDPW R_EN (55)
LVDS_BLON F7 NB_BL_PW M (55)
2
SCD1U10V2KX-5GP
NB_GFX_CLK T2 G12 NB_BL_EN (55)

(7) NB_GFX_CLK GFX_REFCLKP LVDS_ENA_BL
C1315
R1313 NB_GFX_CLK# T1
(7) NB_GFX_CLK# GFX_REFCLKN
1
4K7R2F-GP
TP1306 1NB_GPP_CLK
9/25 10/2 TP1307 1NB_GPP_CLK#
U1 GPP_REFCLKP RN1301 9/22
DY U2
1
GPP_REFCLKN
1 4
+1.5V_RUN +1.8V_RUN
10/7 (7) NB_GPPSB_CLK V4
V3
GPPSB_REFCLKP 2 UMA 3
(7) NB_GPPSB_CLK# GPPSB_REFCLKN
9/15 B9
SRN10KJ-5-GP
(55) LDDC_CLK I2C_CLK TP_TMDS_HPD TP1308
(55) LDDC_DATA A9 I2C_DATA MIS. TMDS_HPD D9 1 0225-1
1
R1309 R1322 1 2 0R2J-2-GP HDMI_HPD_DET

300R2J-4-GP DY R1311 (57) NB_DDC_DATA0 B8
A8
DDC_DATA0/AUX0N HPD D10
R1317
HDMI_HPD_DET (57,82)
2K2R2J-2-GP (57) NB_DDC_CLK0 DDC_CLK0/AUX0P NB_SUS_STAT#
B7 DDC_CLK1/AUX1P SUS_STAT# D12 1 UMA
2 SUS_STAT# (21)
U1301
9/15 1120-6 A7 DDC_DATA1/AUX1N
AE8 0R2J-2-GP
2
STRP_DATA THERMALDIODE_P
B10 STRP_DATA THERMALDIODE_N AD8
(10,20) CPU_LDT_STOP# 1 6 NB_LDT_STOP#
A1 Y1
1
SCD1U10V2KX-5GP
2 5 TP1305 1 TP_NB_RESERVED G11 D13 TESTMODE_NB

GND VCC RESERVED TESTMODE
C1314
3 4 R1318
A2 Y2
1
1
1K8R2F-GP
2KR2J-1-GP 1 2 RS780_AUX_CAL C8 AUX_CAL
R1320
R1319 150R2F-1-GP
RS880M-1-GP
2
NC7W Z07P6X-1GP +3.3V_RUN

11/6
2
2
A +1.8V_RUN <Core Design> A
R1314
1
4K7R2J-2-GP
R1315
1KR2J-1-GP Wistron Corporation
1
NB_SUS_STAT# 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
2
1
1 2 NB_ALLOW _LDTSTOP
(20) ALLOW _LDTSTOP R1321 Title
R1316 ALLOW_LDTSTOP: 3KR2J-2-GP
DY AMD-RS880M_LVDS&CRT_(2/4)
0R0402-PAD 1 = LDTSTOP# can be asserted
0 = LDTSTOP# has to be de-asserted Size Document Number Rev
2
A3
5 4 3 2 1
5 4 3 2 1
SSID = N.B
MEM_VDDQ
U1D
U1401 PAR 4 OF 6
D SPM_A0 AB12 AA18 SPM_DQ0 D
SPM_DQ2 SPM_A1 MEM_A0 MEM_DQ0/DVO_VSYNC SPM_DQ1
K8 VDD DQL0 E3 AE16 MEM_A1 MEM_DQ1/DVO_HSYNC AA20
K2 F7 SPM_DQ1 SPM_A2 V11 AA19 SPM_DQ2
VDD DQL1 SPM_DQ5 SPM_A3 MEM_A2 MEM_DQ2/DVO_DE SPM_DQ3
N1 VDD DQL2 F2 AE15 MEM_A3 MEM_DQ3/DVO_D0 Y19
R9 F8 SPM_DQ3 SPM_A4 AA12 V17 SPM_DQ4
VDD DQL3 SPM_DQ7 SPM_A5 MEM_A4 MEM_DQ4 SPM_DQ5
B2 VDD DQL4 H3 AB16 MEM_A5 MEM_DQ5/DVO_D1 AA17
D9 H8 SPM_DQ0 SPM_A6 AB14 AA15 SPM_DQ6
VDD DQL5 SPM_DQ4 SPM_A7 MEM_A6 MEM_DQ6/DVO_D2 SPM_DQ7
G7 VDD DQL6 G2 AD14 MEM_A7 MEM_DQ7/DVO_D4 Y15
R1 H7 SPM_DQ6 SPM_A8 AD13 AC20 SPM_DQ8
VDD DQL7 SPM_A9 MEM_A8 MEM_DQ8/DVO_D3 SPM_DQ9
N9 VDD AD15 MEM_A9 MEM_DQ9/DVO_D5 AD19
D7 SPM_DQ13 SPM_A10 AC16 AE22 SPM_DQ10
SBD_MEM/DVO_I/F
DQU0 SPM_DQ8 SPM_A11 MEM_A10 MEM_DQ10/DVO_D6 SPM_DQ11
A8 VDDQ DQU1 C3 AE13 MEM_A11 MEM_DQ11/DVO_D7 AC18
A1 C8 SPM_DQ10 SPM_A12 AC14 AB20 SPM_DQ12
VDDQ DQU2 SPM_DQ12 SPM_A13 MEM_A12 MEM_DQ12 SPM_DQ13
C1 VDDQ DQU3 C2 Y14 MEM_A13 MEM_DQ13/DVO_D9 AD22
C9 A7 SPM_DQ15 AC22 SPM_DQ14
VDDQ DQU4 SPM_DQ11 SPM_BA0 MEM_DQ14/DVO_D10 SPM_DQ15
D2 VDDQ DQU5 A2 AD16 MEM_BA0 MEM_DQ15/DVO_D11 AD21
E9 B8 SPM_DQ14 SPM_BA1 AE17
VDDQ DQU6 SPM_DQ9 SPM_BA2 MEM_BA1 SPM_DQS0P
F1 VDDQ DQU7 A3 AD17 MEM_BA2 MEM_DQS0P/DVO_IDCKP Y17
H9 W18 SPM_DQS0N
VDDQ SPM_DQS1P SPM_RAS# MEM_DQS0N/DVO_IDCKN SPM_DQS1P
H2 VDDQ DQSU C7 W12 MEM_RAS# MEM_DQS1P AD20
SPM_DQS1N MEM_VDDQ SPM_CAS# SPM_DQS1N
DQSU# B7 Y12 MEM_CAS# MEM_DQS1N AE21
SPM_VREF1 H1 SPM_W E# AD18
SPM_VREF2 M8 VREFDQ SPM_DQS0P SPM_CS# MEM_WE# SPM_DM0
VREFCA DQSL F3 AB13 MEM_CS# MEM_DM0 W17
1
R1408 1 2243R2F-2-GP SPM_ZQ L8 G3 SPM_DQS0N SPM_CKE AB18 AE19 SPM_DM1
ZQ DQSL# R1411 SPM_ODT MEM_CKE MEM_DM1/DVO_D8
UMA_SPM SPM_ODT 10KR2J-3-GP
V14 MEM_ODT IOPLLVDD18
SPM_A0 ODT K1
SPM_CLKP
1
R1401 DY 2
100R2F-L1-GP-U IOPLLVDD18 AE23
IOPLLVDD
SPM_A1
N3
P7
A0 UMA_SPM 9/15 SPM_CLKN
V15
W14
MEM_CKP IOPLLVDD AE24
2
SPM_A2 A1 SPM_CS# MEM_CKN
C SPM_A3
P3
N2
A2 CS# L2
T2 R1409 1
UMA_SPM
2 40D2R2F-GP MEM_COMPP AE12
IOPLLVSS AD23
C
A3 RESET# SP_DDR3_RST# (21) MEM_COMPP
SPM_A4 P8 MEM_VDDQ R1410 1 2 40D2R2F-GP MEM_COMPN AD12 AE18 SPM_VREF0
A4 MEM_COMPN MEM_VREF
SCD1U10V2KX-5GP
SPM_A5 P2 A5 UMA_SPM
C1415
SPM_A6 R8 T7 RS880M-1-GP
A6 NC#T7
1
SPM_A7 R2 L9
SPM_A8 A7 NC#L9
T8 A8 NC#L1 L1
SPM_A9 R3 J9
DY
2
SPM_A10 A9 NC#J9
L7 A10/AP NC#J1 J1
SPM_A11
SPM_A12
R7
N7
A11 10/7
SPM_A13 A12/BC#
T3 A13 VSS J8
M7 NC#M7 VSS M1
VSS M9
VSS J2
SPM_BA0 +1.8V_RUN
SPM_BA1
M2
N8
BA0 VSS P9
G8
1.8V(0.015A) for IOPLLVDD18
BA1 VSS L1401
SPM_BA2 M3 B3
BA2 VSS IOPLLVDD18
VSS T1 1 2
SC2D2U6D3V3KX-GP
VSS A9
C1401
SPM_CLKP J7 T9 0R0402-PAD
CK VSS
1
SPM_CLKN K7 CK# VSS E1
P1
1231-1
SPM_CKE VSS
K9
2
CKE
VSSQ G1 UMA_SPM
VSSQ F9
SPM_DM1 D3 E8
SPM_DM0 DMU VSSQ
E7 DML VSSQ E2
VSSQ D8
VSSQ D1
B SPM_W E# B
L3 WE# VSSQ B9
SPM_CAS# +1.1V_RUN
SPM_RAS#
K3
J3
CAS# VSSQ B1
G9
1.1V(0.026A) for IOPLLVDD
RAS# VSSQ L1402
IOPLLVDD 1 2
SC2D2U6D3V3KX-GP
K4W 1G1646E-HC12-GP
0R0402-PAD
UMA_SPM_Samsung
1
C1402
1231-1
2
UMA_SPM
MEM_VDDQ
MEM_VDDQ MEM_VDDQ
MEM_VDDQ +1.5V_RUN
SCD1U10V2KX-5GP
1.5V(0.35A) for IOPLLVDD R1412

1
1KR3F-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1
1
R1402
C1404
1KR3F-GP
1KR3F-GP
1 2
1
1
R1403
C1406
R1404
C1408
UMA_SPM
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
2
0R3J-0-U-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC10U6D3V5KX-1GP
UMA_SPM UMA_SPM SC10U6D3V5KX-1GP

2
C1411
C1412
A UMA_SPM UMA_SPM UMA_SPM UMA_SPM <Core Design> A
2
1
C1414
C1413
C1410
C1409
SPM_VREF0
SPM_VREF1 SPM_VREF2
1
1KR3F-GP
SCD1U10V2KX-5GP
Wistron Corporation
2
2
1
1
R1405
C1403
1KR3F-GP
SCD1U10V2KX-5GP
1KR3F-GP
SCD1U10V2KX-5GP
UMA_SPM UMA_SPM UMA_SPM

1
1
R1406
C1405
R1407
C1407

UMA_SPM UMA_SPM UMA_SPM Taipei Hsien 221, Taiwan, R.O.C.
2
UMA_SPM
2
Title
UMA_SPM UMA_SPM UMA_SPM UMA_SPM
2
UMA_SPM/DIS_NOSPM AMD-RS880M_SidePort_(3/4)
A3
5 4 3 2 1
5 4 3 2 1
SSID = N.B
D D
+1.1V_RUN
1231-1
40 mils 1.1V(0.6A) for VDDHT
R1501
+1.1V_RUN_VDDHT U1F
1 2
SC4D7U6D3V3KX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
A25 VSSAHT1 VSSAPCIE1 A2
+1.1V_RUN_VDDPCIE +1.1V_RUN
C1502
C1506
C1503
0R0603-PAD 1215-1 D23 VSSAHT2 PART 6/6 VSSAPCIE2 B1
1
1
C1501
U1E 1.1V(2.5A) for VDDPCIE 130 mils G1501

E22
G22
VSSAHT3 VSSAPCIE3 D3
D5
VSSAHT4 VSSAPCIE4
DY DY J17 A6 1 2 G24 E4
2
2
VDDHT_1 VDDPCIE_1 VSSAHT5 VSSAPCIE5
SC4D7U6D3V3KX-GP
SCD1U10V2KX-5GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
K16 PART 5/6 B6 GAP-CLOSE-PW R-3-GP G25 G1
C1508
C1504
C1509
C1510
C1505
L16 C6 G1502 H19 G2
1
M16 VDDHT_4 VDDPCIE_4 D6 1 2 J22 VSSAHT8 VSSAPCIE8 G4
P16 E6 GAP-CLOSE-PW R-3-GP L17 H7
+1.1V_RUN VDDHT_5 VDDPCIE_5 G1503 VSSAHT9 VSSAPCIE9
R16 F6
DY DY L22 J4
2
40 mils 1.1V(0.7A) for VDDHTRX

R1505 T16 VDDHT_7 VDDPCIE_7 G7 1 2 L24 VSSAHT11 VSSAPCIE11 R7
H8 GAP-CLOSE-PW R-3-GP L25 L1
+1.1V_RUN_VDDHTRX VDDPCIE_8 G1504 VSSAHT12 VSSAPCIE12
1 2 H18 VDDHTRX_1 VDDPCIE_9 J9 1231-2 1231-2 M20 VSSAHT13 VSSAPCIE13 L2
SC4D7U6D3V3KX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
G19 VDDHTRX_2 VDDPCIE_10 K9 1 2 N22 VSSAHT14 VSSAPCIE14 L4

C1511
C1507
C1512
C1513
F20 M9 GAP-CLOSE-PW R-3-GP P20 L7

0R0603-PAD VDDHTRX_3 VDDPCIE_11 VSSAHT15 VSSAPCIE15
1
E21 VDDHTRX_4 VDDPCIE_12 L9 R19 VSSAHT16 VSSAPCIE16 M6

D22 VDDHTRX_5 VDDPCIE_13 P9 R22 VSSAHT17 VSSAPCIE17 N4
DY DY B23 R9 R24 P6
2
C VDDHTRX_6 VDDPCIE_14 VSSAHT18 VSSAPCIE18 C

A23 VDDHTRX_7 VDDPCIE_15 T9
V9
+NB_VCORE R25
H20
VSSAHT19 VSSAPCIE19 R1
R2
VDDPCIE_16 +NB_VDDC VSSAHT20 VSSAPCIE20
1231-2 AE25 VDDHTTX_1 VDDPCIE_17 U9
0.95~1.1V(12A) for VDDC U22 VSSAHT21 VSSAPCIE21 R4
+1.1V_RUN
AD24 VDDHTTX_2 550 mils V19 VSSAHT22 VSSAPCIE22 V7
20 mils 1.1V(0.4A) for VDDHTTX AC23 K12 W22 U4
GROUND
R1503 VDDHTTX_3 VDDC_1 VSSAHT23 VSSAPCIE23
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
AB22 VDDHTTX_4 VDDC_2 J14 10/8 10/8 W24 VSSAHT24 VSSAPCIE24 V8
C1519
C1520
C1522
C1524
C1525
C1526
C1527
1 2 +1.2V_RUN_VDDHTTX AA21 U16 W25 V6
VDDHTTX_5 VDDC_3 VSSAHT25 VSSAPCIE25
1
SC4D7U6D3V3KX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
Y20 VDDHTTX_6 VDDC_4 J11 Y21 VSSAHT26 VSSAPCIE26 W1

C1514
C1515
C1516
C1517
C1518
0R0603-PAD W19 VDDHTTX_7 VDDC_5 K15 AD25 VSSAHT27 VSSAPCIE27 W2

1
V18 M12
DY DY W4
2
VDDHTTX_8 VDDC_6 VSSAPCIE28
U17 L14 L12 W7
POWER
VDDHTTX_9 VDDC_7 VSS11 VSSAPCIE29
DY DY T17 L11 M14 W8
2

R17
P17
VDDHTTX_11 VDDC_9 M13
M15
1231-2 1231-2 N13
P12
VSS13 VSSAPCIE31 Y6
AA4
+1.8V_RUN
1231-2 M17 VDDHTTX_13 VDDC_11 N12 P15 VSS15 VSSAPCIE33 AB5
VDDC_12 N14 10/5 R11 VSS16 VSSAPCIE34 AB1
40 mils 1.8V(0.7A) for VDDA18PCIE SBD MEM ENABLE

J10 VDDA18PCIE_1 VDDC_13 P11 R14 VSS17 VSSAPCIE35 AB7
L1505 P10 P13 T12 AC3
+1.8V_RUN_VDDA18PCIE VDDA18PCIE_2 VDDC_14 +1.5V_RUN VSS18 VSSAPCIE36
1 2 K10 VDDA18PCIE_3 VDDC_15 P14
1.5V(0.1A) for VDD_MEM R1506 U14 VSS19 VSSAPCIE37 AC4
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
PBY160808T-221Y-N-GP M10 VDDA18PCIE_4 VDDC_16 R12 15 mils U11 VSS20 VSSAPCIE38 AE1
C1528
C1529
C1530
C1531
C1532
C1533
220R, 2A L10 R15 VDD_MEM_SDP 0R3J-0-U-GP

1 2 U15 AE4
VDDA18PCIE_5 VDDC_17 VSS21 VSSAPCIE39
1
UMA_SPM/DIS_NOSPM
SC4D7U6D3V3KX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
W9 VDDA18PCIE_6 VDDC_18 T11 UMA_SPM9/11 V12 VSS22 VSSAPCIE40 AB2
C1541
C1537
C1538
C1539
C1540
1119-1 H9 VDDA18PCIE_7 VDDC_19 T15 W11 VSS23
1
DY DY T10 U12 W15
2
VDDA18PCIE_8 VDDC_20 VSS24

R10 VDDA18PCIE_9 VDDC_21 T14 AC12 VSS25 VSS1 AE14
Y9 J16
DY AA14 D11
2
VDDA18PCIE_10 VDDC_22 VSS26 VSS2
AA9 VDDA18PCIE_11 UMA_SPM Y18 VSS27 VSS3 G8
AB9 VDDA18PCIE_12 VDD_MEM1 AE10 UMA_SPM UMA_SPM AB11 VSS28 VSS4 E14
B
AD9
AE9
VDDA18PCIE_13 VDD_MEM2 AA11
Y11
1231-2 AB15
AB17
VSS29 VSS5 E15
J15
B
+1.8V_RUN VDDA18PCIE_14 VDD_MEM3 VSS30 VSS6
15 mils 1.8V(0.01A) for VDD18

U10 VDDA18PCIE_15 VDD_MEM4 AD10 AB19 VSS31 VSS7 J12
VDD_MEM5 AB10 AE20 VSS32 VSS8 K14
F9 AC10 +3.3V_RUN AB21 M11
VDD18_1 VDD_MEM6 VSS33 VSS9
SC1U6D3V2KX-GP
G9 VDD18_2 3.3V(0.06A) for VDD33 K11 VSS34 VSS10 L15

C1534
AE11 VDD18_MEM1 VDD33_1 H11 15 mils

1
AD11 H12 RS880M-1-GP

VDD18_MEM2 VDD33_2
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C1535
C1536
RS880M-1-GP
2
1
Layout Note
2
DY
2
+1.8V_RUN
R1502 1.8V(0.025A) for VDD18 1231-2
1 2
15 mils VDD18_MEM
SC1U10V3KX-3GP
UMA
C1542
0R3J-0-U-GP
1
1117-2
UMA/DIS
2
+NB_VDDC +1.1V_RUN
9/15 0104-1
R1507
1 2
Layout Note PBY160808T-330Y-N-GP
A R1508 <Core Design> A
1 2
PBY160808T-330Y-N-GP
R1509
1 2 Wistron Corporation
PBY160808T-330Y-N-GP 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
R1510 Taipei Hsien 221, Taiwan, R.O.C.
1 2
PBY160808T-330Y-N-GP Title
1
R1511
2
AMD-RS880M_PWR&GD_(4/4)
PBY160808T-330Y-N-GP Size Document Number Rev
A3
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
5 4 3 2 1
5 4 3 2 1
SSID = MEMORY
11/10
DM1
(9) MEM_MA_ADD[0..15]
MEM_MA_ADD0 98 NP1
MEM_MA_ADD1 A0 NP1
97 NP2
MEM_MA_ADD2 A1 NP2
96
MEM_MA_ADD3 A2
95 110 MEM_MA_RAS# (9)
MEM_MA_ADD4 A3 RAS#
92 113 MEM_MA_WE# (9)
MEM_MA_ADD5 A4 WE#
91 115 MEM_MA_CAS# (9)
MEM_MA_ADD6 A5 CAS# +1.5V_SUS
90
MEM_MA_ADD7 A6
86 114 MEM_MA0_CS#0 (9)
MEM_MA_ADD8 A7 CS0#
89 121 MEM_MA0_CS#1 (9)
MEM_MA_ADD9 A8 CS1#
D 85 D
MEM_MA_ADD10 A9 PM_EXTTS#0
MEM_MA_ADD11
107
84
A10/AP CKE0
73
74
MEM_MA_CKE0 (9)
MEM_MA_CKE1 (9)
1
4K7R2J-2-GP DY 2
R1806
MEM_MA_ADD12 A11 CKE1
83
MEM_MA_ADD13 A12
119 101 MEM_MA_CLK0_P (9)
MEM_MA_ADD14 A13 CK0
80 103 MEM_MA_CLK0_N (9)
MEM_MA_ADD15 A14 CK0#
78
A15
79 102 MEM_MA_CLK1_P (9)
(9) MEM_MA_BANK2 A16/BA2 CK1
104 MEM_MA_CLK1_N (9)
CK1#
109 M_A_DM[7..0] (9)
(9) MEM_MA_BANK0 BA0 M_A_DM0
108 11
(9) MEM_MA_BANK1 BA1 DM0 M_A_DM1
(9) M_A_DQ[63..0] 28
M_A_DQ0 DM1 M_A_DM2
5 46
M_A_DQ1 DQ0 DM2 M_A_DM3
7 63
15 136
M_A_DQ4
17
4
DQ3 DM5
153
170 M_A_DM6
0107-4
DQ4 DM6
RN
M_A_DQ5 6 187 M_A_DM7
M_A_DQ6 DQ5 DM7
16
DQ6
M_A_DQ7 18 200 SB_SMBDATA
(19,76) SB_SMBDATA 10R4P2R-PAD
4 SB_SMBDATA_R (7,21)
M_A_DQ8 DQ7 SDA SB_SMBCLK
21 202 (19,76) SB_SMBCLK 2 3 SB_SMBCLK_R (7,21)
M_A_DQ9 DQ8 SCL RN1801
23
M_A_DQ10 DQ9 PM_EXTTS#0 +3.3V_RUN
33 198
M_A_DQ11 DQ10 EVENT#
35
DQ11 3.3V, 2mA
M_A_DQ12 22 199
DQ12 VDDSPD
SCD1U10V2KX-5GP
M_A_DQ13 24
DQ13 DY2
C1802
M_A_DQ14 34 197 SB_SMBCLK 1
1
M_A_DQ15 DQ14 SA0 SB_SMBDATA C1823 SC10P50V2JN-4GP
M_A_DQ16
36
DQ15 SA1
201 9/23 C1824
1 2
SC10P50V2JN-4GP
M_A_DQ17
39
DQ16 DY
41 77 9/23
2
M_A_DQ18 DQ17 NC#1
51 122
M_A_DQ19 DQ18 NC#2 +1.5V_SUS
53 125
M_A_DQ20 DQ19 NC#/TEST
40
DQ20 1.5V, 3.5A
M_A_DQ21 42 75
M_A_DQ22 DQ21 VDD1
50 76
M_A_DQ23 DQ22 VDD2
52 81
M_A_DQ24 DQ23 VDD3
57 82
M_A_DQ25 DQ24 VDD4
59 87
M_A_DQ26 DQ25 VDD5
67 88
M_A_DQ27 DQ26 VDD6
69 93
M_A_DQ28 DQ27 VDD7
M_A_DQ29
56
DQ28 VDD8
94 Note:
C 58 99 C
M_A_DQ30 DQ29 VDD9 SA0 = 0, SA1 = 0
68 100
M_A_DQ31 DQ30 VDD10
70 105 SO-DIMMA SPD Address is 0xA0
M_A_DQ32 DQ31 VDD11
129 106
DQ32 VDD12
M_A_DQ33 131
DQ33 VDD13
111 SO-DIMMA TS Address is 0x30
M_A_DQ34 141 112
M_A_DQ35 DQ34 VDD14
143 117
M_A_DQ36 DQ35 VDD15
130 118
M_A_DQ37 DQ36 VDD16
132 123
M_A_DQ38 DQ37 VDD17
140 124
M_A_DQ39 DQ38 VDD18
142
M_A_DQ40 DQ39
147 2
M_A_DQ41 DQ40 VSS
149 3
M_A_DQ42 DQ41 VSS
157 8
M_A_DQ43 DQ42 VSS
159 9
M_A_DQ44 DQ43 VSS
M_A_DQ45
146
DQ44 VSS
13 SODIMM A DECOUPLING (ONE CAP PER POWER PIN)
148 14
M_A_DQ46 DQ45 VSS
158 19
M_A_DQ47 DQ46 VSS +1.5V_SUS
160 20
M_A_DQ48 DQ47 VSS
163 25
M_A_DQ49 DQ48 VSS
165 26
M_A_DQ50 DQ49 VSS
175 31
M_A_DQ51 DQ50 VSS
177 32
DQ51 VSS
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
M_A_DQ52 164 37
DQ52 VSS
C1804
C1805
C1806
C1807
C1808
C1809
M_A_DQ53 166
DQ53 VSS
38 Layout Note:
1
M_A_DQ54 174 43
M_A_DQ55 DQ54 VSS Place these Caps near
176 44
M_A_DQ56 DQ55 VSS
181 48 SO-DIMMA.
2
M_A_DQ57 DQ56 VSS
183 49
M_A_DQ58 DQ57 VSS
191 54
M_A_DQ59 DQ58 VSS
193 55
M_A_DQ60 DQ59 VSS
180 60
M_A_DQ61 DQ60 VSS
182 61
M_A_DQ62 DQ61 VSS
M_A_DQ63
192
194
DQ62 VSS
65
66
1225-1
DQ63 VSS
71
VSS
SE330U2VDM-L-GP
10 72
(9) M_A_DQS#0 DQS0# VSS
TC1801
27 127 C1812 C1813 C1814 C1815 C1816 C1817
1
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
45 128
1
62 133
(9) M_A_DQS#3
135
DQS3# VSS
134
DY DY DY DY DY DY
2
B (9) M_A_DQS#4 DQS4# VSS B
152 138
2
169 139
186 144
145
M_A_DQS0 VSS
12 150
(9) M_A_DQS0 M_A_DQS1 DQS0 VSS
29 151
47 155
64 156
137 161
154 162
171 167
188 168
(9) M_A_DQS7 DQS7 VSS
172
VSS
116 173
+V_DDR_REF (9) MEM_MA0_ODT0 ODT0 VSS
120 178
(9) MEM_MA0_ODT1 ODT1 VSS
179
VSS
9/14 9/23 126
VREF_CA VSS
184
SCD1U10V2KX-5GP
SCD01U50V3KX-4GP
SCD1U10V2KX-5GP
1 185
VREF_DQ VSS
C1825
C1810
C1811
189
VSS
1
30 190
(9) DDR3_A_DRAMRST# RESET# VSS
SCD1U10V2KX-5GP
195
VSS
C1822
196
2
VSS
203 205
VTT1 VSS
204 206
VTT2 VSS
DY
2
10/7 DDR3-204P-41-GP-U
0108-3
62.10017.N41
+0.75V_DDR_VTT
H =5.2mm
0.75V, 0.5A
SC2D2U6D3V3KX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
Place these caps

C1819
C1820
C1821
1
close to VTT1 and

VTT2.
DY DY
2
A A
1231-2
<Core Design>
Wistron Corporation
Title
DDR3-SODIMM1

5 4 3 2 1
5 4 3 2 1
DM2
11/10
SSID = MEMORY (9) MEM_MB_ADD[0..15]
MEM_MB_ADD0
MEM_MB_ADD1
98
97
A0
A1
NP1
NP2
NP1
NP2
MEM_MB_ADD2 96
MEM_MB_ADD3 A2
95 110 MEM_MB_RAS# (9)
MEM_MB_ADD4 A3 RAS#
92 113 MEM_MB_WE# (9)
MEM_MB_ADD5 A4 WE#
91 115 MEM_MB_CAS# (9)
MEM_MB_ADD6 A5 CAS#
90
MEM_MB_ADD7 A6
86 114 MEM_MB0_CS#0 (9)
MEM_MB_ADD8 A7 CS0#
89 121 MEM_MB0_CS#1 (9)
MEM_MB_ADD9 A8 CS1#
85
MEM_MB_ADD10 A9
107 73 MEM_MB_CKE0 (9)
MEM_MB_ADD11 A10/AP CKE0
84 74 MEM_MB_CKE1 (9)
MEM_MB_ADD12 A11 CKE1
83
MEM_MB_ADD13 A12
119 101 MEM_MB_CLK0_P (9)
MEM_MB_ADD14 A13 CK0
80 103 MEM_MB_CLK0_N (9)
MEM_MB_ADD15 A14 CK0#
78
A15
D 79 102 MEM_MB_CLK1_P (9) D
(9) MEM_MB_BANK2 A16/BA2 CK1
104 MEM_MB_CLK1_N (9)
CK1#
109 M_B_DM[7..0] (9)
(9) MEM_MB_BANK0 BA0 M_B_DM0
108 11
(9) MEM_MB_BANK1 BA1 DM0 M_B_DM1
(9) M_B_DQ[63..0] 28
M_B_DQ0 DM1 M_B_DM2
5 46
M_B_DQ1 DQ0 DM2 M_B_DM3
7 63
15 136
17 153
4 170
M_B_DQ6
6
16
DQ5 DM7
187 9/23
M_B_DQ7 DQ6 SB_SMBDATA
18 200 SB_SMBDATA (18,76)
M_B_DQ8 DQ7 SDA SB_SMBCLK
21 202 SB_SMBCLK (18,76)
M_B_DQ9 DQ8 SCL
23
M_B_DQ10 DQ9 PM_EXTTS#1 +3.3V_RUN
33 198
M_B_DQ11 DQ10 EVENT# +1.5V_SUS
35
DQ11 3.3V, 2mA
M_B_DQ12 22 199
DQ12 VDDSPD
SCD1U10V2KX-5GP
M_B_DQ13 24
DQ13
C1902
M_B_DQ14 34 197
1
M_B_DQ15 DQ14 SA0 PM_EXTTS#1
M_B_DQ16
36
39
DQ15 SA1
201 +3.3V_RUN 9/23 1
4K7R2J-2-GP DY 2
R1906
M_B_DQ17 DQ16
41 77 9/23
2
M_B_DQ18 DQ17 NC#1
51 122
M_B_DQ19 DQ18 NC#2 +1.5V_SUS
53 125
M_B_DQ20 DQ19 NC#/TEST
40
DQ20 1.5V, 3.5A
M_B_DQ21 42 75
M_B_DQ22 DQ21 VDD1
50 76
M_B_DQ23 DQ22 VDD2
52 81
M_B_DQ24 DQ23 VDD3
57 82
M_B_DQ25 DQ24 VDD4
59 87
M_B_DQ26 DQ25 VDD5
67 88
M_B_DQ27 DQ26 VDD6
M_B_DQ28
69
DQ27 VDD7
93 Note:
56 94
M_B_DQ29 DQ28 VDD8 SA0 = 0, SA1 = 1
58 99
M_B_DQ30 DQ29 VDD9
68 100 SO-DIMMB SPD Address is 0xA4
M_B_DQ31 DQ30 VDD10
70 105
DQ31 VDD11
M_B_DQ32 129
DQ32 VDD12
106 SO-DIMMB TS Address is 0x34
M_B_DQ33 131 111
M_B_DQ34 DQ33 VDD13
141 112
M_B_DQ35 DQ34 VDD14
143 117
M_B_DQ36 DQ35 VDD15
C 130 118 C
M_B_DQ37 DQ36 VDD16
132 123
M_B_DQ38 DQ37 VDD17
140 124
M_B_DQ39 DQ38 VDD18
M_B_DQ40
142
DQ39 SODIMM B DECOUPLING (ONE CAP PER POWER PIN)
147 2
M_B_DQ41 DQ40 VSS +1.5V_SUS
149 3
M_B_DQ42 DQ41 VSS
157 8
M_B_DQ43 DQ42 VSS
159 9
M_B_DQ44 DQ43 VSS
146 13
M_B_DQ45 DQ44 VSS
148 14
DQ45 VSS
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
M_B_DQ46 158 19
DQ46 VSS
C1906
C1907
C1908
C1909
C1910
C1911
M_B_DQ47 160 20
DQ47 VSS
1
M_B_DQ48 163 25 Layout Note:
M_B_DQ49 DQ48 VSS
165 26
M_B_DQ50 DQ49 VSS Place these Caps near
175 31
2
M_B_DQ51 DQ50 VSS
177 32 SO-DIMMB.
M_B_DQ52 DQ51 VSS
164 37
M_B_DQ53 DQ52 VSS
166 38
M_B_DQ54 DQ53 VSS
174 43
M_B_DQ55 DQ54 VSS
176 44
M_B_DQ56 DQ55 VSS
181 48
M_B_DQ57 DQ56 VSS
183 49
M_B_DQ58 DQ57 VSS
191 54
M_B_DQ59 DQ58 VSS
193 55
M_B_DQ60 DQ59 VSS C1912 C1913 C1914 C1915 C1916 C1917
180 60
DQ60 VSS
1
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
M_B_DQ61 182 61
M_B_DQ62 DQ61 VSS
192 65
M_B_DQ63 194
DQ62 VSS
66
DY DY DY DY DY DY
2
DQ63 VSS
71
VSS
(9) M_B_DQS#0 10 72
DQS0# VSS
(9) M_B_DQS#1 27 127
DQS1# VSS
(9) M_B_DQS#2 45 128
DQS2# VSS
(9) M_B_DQS#3 62 133
DQS3# VSS
(9) M_B_DQS#4 135 134
DQS4# VSS
(9) M_B_DQS#5 152 138
DQS5# VSS
(9) M_B_DQS#6 169 139
DQS6# VSS
(9) M_B_DQS#7 186 144
DQS7# VSS
145
M_B_DQS0 VSS
(9) M_B_DQS0 12 150
M_B_DQS1 DQS0 VSS
(9) M_B_DQS1 29 151
M_B_DQS2 DQS1 VSS
(9) M_B_DQS2 47 155
B M_B_DQS3 DQS2 VSS B
(9) M_B_DQS3 64 156
M_B_DQS4 DQS3 VSS
(9) M_B_DQS4 137 161
M_B_DQS5 DQS4 VSS
(9) M_B_DQS5 154 162
M_B_DQS6 DQS5 VSS
(9) M_B_DQS6 171 167
M_B_DQS7 DQS6 VSS
(9) M_B_DQS7 188 168
DQS7 VSS
172
VSS
116 173
+V_DDR_REF (9) MEM_MB0_ODT0 ODT0 VSS
120 178
(9) MEM_MB0_ODT1 ODT1 VSS
179
VSS
9/14 9/23 126
VREF_CA VSS
184
SCD1U10V2KX-5GP
SCD01U50V3KX-4GP
SCD1U10V2KX-5GP
1 185
VREF_DQ VSS
C1922
C1904
C1905
189
1
VSS
30 190
(9) DDR3_B_DRAMRST# RESET# VSS
SCD1U10V2KX-5GP
195
VSS
C1921
196
2
VSS
203 205
VTT1 VSS
204 206
VTT2 VSS
10/7 DY
2
0108-3 DDR3-204P-40-GP-U
+0.75V_DDR_VTT
0.75V, 0.5A H = 9.2mm SO-DIMMB is placed farther from

the Processor than SO-DIMMA
SC2D2U6D3V3KX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
Place these caps

C1918
C1919
C1920
1
close to VTT1 and

VTT2.
DY DY
2
1231-2
A A
<Core Design>
Wistron Corporation
Title
DDR3-SODIMM2

5 4 3 2 1
5 4 3 2 1
SSID = S.B SB820M : 71.SB820.M02

U2A
C2001 1 2 SC150P50V2KX-GP Part 1 of 5
PCIE_RST#_SB P1 W2
A_RST# R2024 PCIE_RST# PCICLK0
1 2 22R2J-2-GP A_RST#_R L1 A_RST# PCICLK1/GPO36 W1 PCI_CLK1 (24)
STRAP PIN
PCI CLKS
PCICLK2/GPO37 W3 PCI_CLK2 (24)
C2002 1 2 SCD1U10V2KX-5GP ALINK_NBRX_SBTX_C_P0 AD26 W4
(12) ALINK_NBRX_SBTX_P0 A_TX0P PCICLK3/GPO38 PCI_CLK3 (24)
C2003 1 2 SCD1U10V2KX-5GP ALINK_NBRX_SBTX_C_N0 AD27 Y1 PCLK_FW H_R R2029 1 DY2 22R2J-2-GP
(12) ALINK_NBRX_SBTX_N0 A_TX0N PCICLK4/14M_OSC/GPO39 PCLK_FW H (24,70)
C2004 1 2 SCD1U10V2KX-5GP ALINK_NBRX_SBTX_C_P1 AC28
(12) ALINK_NBRX_SBTX_P1 A_TX1P
C2005 SCD1U10V2KX-5GP ALINK_NBRX_SBTX_C_N1 PCI_RST# 1
D
(12) ALINK_NBRX_SBTX_N1
C2006
1
1
2
2 SCD1U10V2KX-5GP ALINK_NBRX_SBTX_C_P2
AC29
AB29
A_TX1N PCIRST# V2
TP2008
9/24 D
(12) ALINK_NBRX_SBTX_P2 A_TX2P
C2007 1 2 SCD1U10V2KX-5GP ALINK_NBRX_SBTX_C_N2 AB28
(12) ALINK_NBRX_SBTX_N2 A_TX2N
C2008 1 2 SCD1U10V2KX-5GP ALINK_NBRX_SBTX_C_P3 AB26 AA1
(12) ALINK_NBRX_SBTX_P3 A_TX3P AD0/GPIO0
C2009 1 2 SCD1U10V2KX-5GP ALINK_NBRX_SBTX_C_N3 AB27 AA4
(12) ALINK_NBRX_SBTX_N3 A_TX3N AD1/GPIO1
AD2/GPIO2 AA3
(12) ALINK_NBTX_SBRX_P0 AE24
AE23
A_RX0P AD3/GPIO3 AB1
AA5
9/16
(12) ALINK_NBTX_SBRX_N0 A_RX0N AD4/GPIO4 +3.3V_RUN
(12) ALINK_NBTX_SBRX_P1 AD25 A_RX1P AD5/GPIO5 AB2
PCI EXPRESS INTERFACES

(12) ALINK_NBTX_SBRX_N1 AD24
AC24
A_RX1N AD6/GPIO6 AB6
AB5
11/6
(12) ALINK_NBTX_SBRX_P2 A_RX2P AD7/GPIO7
1
(12) ALINK_NBTX_SBRX_N2 AC25 A_RX2N AD8/GPIO8 AA6
R2026
(12) ALINK_NBTX_SBRX_P3 AB25
AB24
A_RX3P AD9/GPIO9 AC2
AC3
11/6 10KR2J-3-GP
(12) ALINK_NBTX_SBRX_N3 A_RX3N AD10/GPIO10
AC4 R2025
+1.1V_RUN_PCIE_VDDR R2002 1 AD11/GPIO11
Place R <100mils form 2 590R2F-GP SB_PCIE_CALRP AD29 AC1 22R2J-2-GP
2
R2007 1 PCIE_CALRP AD12/GPIO12
2 2KR2F-3-GP SB_PCIE_CALRN AD28 AD1 PCIE_RST#_SB 2 1 PLTRST#_LAN_W LAN
pins AD29,AD28 PCIE_CALRN AD13/GPIO13
AD2
PLTRST#_LAN_W LAN (70,76,78)
AD14/GPIO14
AA28 GPP_TX0P AD15/GPIO15 AC6
2
AA29 GPP_TX0N AD16/GPIO16 AE2
Y29 AE1 C2013
GPP_TX1P AD17/GPIO17 SC150P50V2KX-GPDY
Y28 AF8
1
GPP_TX1N AD18/GPIO18
Y26 GPP_TX2P AD19/GPIO19 AE3
Y27 GPP_TX2N AD20/GPIO20 AF1
NOTE: SB8XX ONLY SUPPORTS 2 GPP

W28 GPP_TX3P AD21/GPIO21 AG1 11/6
W29 GPP_TX3N AD22/GPIO22 AF2
AE9
9/22
PORT 2 AND 3 IS NOT SUPPORTED. (From CRB) AA22
AD23/GPIO23
AD9
PCI_AD23 (24)
R2028
GPP_RX0P AD24/GPIO24 VDDR_SEL (24,51)
Y21 GPP_RX0N AD25/GPIO25 AC11 PCI_AD25 (24) 2 DY 1
AA25 GPP_RX1P AD26/GPIO26 AF6 PCI_AD26 (24)
C AA24 AF4 0R2J-2-GP C
GPP_RX1N AD27/GPIO27 PCI_AD27 (24)
W23 AF3 TP_PCI_AD28 1
GPP_RX2P AD28/GPIO28 TP_PCI_AD29 TP2009
V24 GPP_RX2N AD29/GPIO29 AH2 1
TP2001
W24
W25
GPP_RX3P AD30/GPIO30 AG2
AH3
1119-1
GPP_RX3N AD31/GPIO31
CBE0# AA8
+3.3V_ALW
9/11 CBE1# AD5
AD8
CBE2#
CBE3# AA10
SCD1U10V2KX-5GP
9/23 FRAME# AE8 1119-1
C2010
DEVSEL# AB9 9/25
1
SB_PCIE_CLK M23 AJ3 U2001
(7) SB_PCIE_CLK PCIE_RCLKP/NB_LNK_CLKP IRDY#
SB_PCIE_CLK#
(7) SB_PCIE_CLK# P23 PCIE_RCLKN/NB_LNK_CLKN TRDY# AE7 (21) GP_PCIE_RST# 1 B DY 1231-1
PCI INTERFACE
AC5 5
DY
2
PAR A_RST# VCC R2005
U29 NB_DISP_CLKP STOP# AF5 2 A
U28 AE6 4 PLTRST# 2 1
NB_DISP_CLKN PERR# Y PLTRST#_NB_GPU (13,37,80)
SERR# AE4 3 GND 0R0402-PAD
T26
T27
NB_HT_CLKP REQ0# AE11
AH5 74LVC1G08GW -1-GP R2008
GPU,NB
NB_HT_CLKN REQ1#/GPIO40
REQ2#/CLK_REQ8#/GPIO41 AH4 2 1 PLTRST#_EC (37)
V21 CPU_HT_CLKP REQ3#/CLK_REQ5#/GPIO42 AC12 1 2
0R0402-PAD
T21 CPU_HT_CLKN GNT0# AD12
AJ5 R2021
1231-1 KBC
GNT1#/GPO44 0R0402-PAD
V23
T23
SLT_GFX_CLKP GNT2#/GPO45 AH6
AB12 SB_GPIO46 1 TP2004
11/6
SLT_GFX_CLKN GNT3#/CLK_REQ7#/GPIO46
CLKRUN# AB11 PM_CLKRUN# (37)
L29 GPP_CLK0P LOCK# AD7
L28 GPP_CLK0N
B
N29
INTE#/GPIO32 AJ6
AG6
9/23 B
GPP_CLK1P INTF#/GPIO33
N28 GPP_CLK1N INTG#/GPIO34 AG4
INTH#/GPIO35 AJ4
M29 GPP_CLK2P 1118-2
M28 GPP_CLK2N DY
T25 RN2008
1
C2018
2
SC10P50V2JN-4GP
9/23
GPP_CLK3P LPCCLK0_R
V25 GPP_CLK3N LPCCLK0 H24 1 4 PCLK_KBC (24,37)
LPCCLK1_R
L24
LPCCLK1 H25
J27 LPC_LAD0
2 3 LPCCLK1 (24) 11/12-1
GPP_CLK4P LAD0 LPC_LAD0 (37,70)
L23 J26 LPC_LAD1 SRN22-3-GP 1 2
GPP_CLK4N LAD1 LPC_LAD1 (37,70)
H29 LPC_LAD2 C2011
LAD2 LPC_LAD2 (37,70)
LPC
LPC_LAD3 SC18P50V2JN-1-GP
P25 GPP_CLK5P LAD3 H28 LPC_LAD3 (37,70) LPC Bus Routing first connects to
M25 G28
CLOCK GENERATOR
GPP_CLK5N LFRAME#
J25 TP_LPC_LDRQ0# 1 MINICARD then connects to KBC
LPC_LFRAME# (37,70)
LDRQ0#
3
TP_LPC_LDRQ1# TP2005
P29
P28
GPP_CLK6P LDRQ1#/CLK_REQ6#/GPIO49 AA18
AB19
1
TP2006
to EC R2014
GPP_CLK6N SERIRQ/GPIO48 INT_SERIRQ (37)
20MR3-GP
N26 GPP_CLK7P
N27
2
GPP_CLK7N 32K_X1
G21 ALLOW _LDTSTOP (13)
2
ALLOW_LDTSTP/DMA_ACTIVE# X2002
T29 GPP_CLK8P PROCHOT# H21 CPU_PROCHOT# (10)
T28 K19 X-32D768KHZ-38GPU
GPP_CLK8N LDT_PG CPU_LDT_PW RGD (10,42)
CPU
G22 R2016
LDT_STP# CPU_LDT_STOP# (10,13) 32K_X2_R 32K_X2
LDT_RST# J24 CPU_LDT_RST# (10) 2 1 1 2
1nd 82.30020.791 L25 14M_25M_48M_OSC
C2012
0R0402-PAD SC15P50V2JN-2-GP
2nd 82.30020.851 25M_X1 32K_X1
32K_X1 C1
R2018
1 2
10R2J-2-GP RTCCLK_KBC (37) 1231-1 11/12-1
A <Core Design> A
25M_X1 L26 C2 32K_X2_R
R2017 25M_X1 32K_X2 RTC_CLK (39)
1 2 1MR2J-1-GP 25M_X2
RTC_CLK
X2001
RTCCLK D2
B2 INTRUDER_ALERT# 1 Wistron Corporation
RTC
25M_X2 INTRUDER_ALERT# TP2007 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
1 2 L27 25M_X2 VDDBT_RTC_G B1 +RTC_CELL
SCD1U10V2KX-5GP

C2017
XTAL-25MHZ-96GP
2
SB820M-1-GP Title
C2014
SC12P50V2JN-3GP
1113-1 C2015
SC12P50V2JN-3GP
SB820M_PCIE&PCI_(1/5)
DY
1

A3
Date: Friday, March 05, 2010 Sheet 20 of 95
5 4 3 2 1
5 4 3 2 1
SSID = S.B
+3.3V_RUN U2D
1119-5 TP2101 1 TP_PCI_PME# J2 A10 USB_48M_CLK
PCI_PME#/GEVENT4# USBCLK/14M_25M_48M_OSC USB_48M_CLK (7)
RN2101 (37) SIO_EXT_W AKE# K1 RI#/GEVENT22#
SC180P50V2JN-1GP
SB_SMBDATA_R G19 USB_RCOMP
1 4 9/23 D3 SPI_CS3#/GBE_STAT1/GEVENT21# USB_RCOMP 1 2
EC2103
SB_SMBCLK_R R2102
2 3 (37,41,42,49,52,89) PM_SLP_S3# F1 SLP_S3# DY
1
H1 Part 4 of 5 11K8R2F-GP
SRN4K7J-8-GP (37,49) PM_SLP_S5# PM_PW RBTN#_R SLP_S5#
1 2 F2
ACPI / WAKE UP EVENTS

D (37) PM_PW RBTN# D
0R0402-PAD R2106 PWR_BTN#
(7,41) SB_PW RGD H5
2
SUS_STAT# PWR_GOOD
9/23 (13) SUS_STAT# 1231-1 SB_TEST0
G6
B3
SUS_STAT# USB_FSD1P/GPIO186 J10
H11
SB_TEST1 TEST0 USB_FSD1N
10/7 1
C2102 DY
2
SC180P50V2JN-1GP SB_TEST2
C4 TEST1/TMS 10/7
+3.3V_ALW 9/22 0113-1 F6
AD21
TEST2 USB_FSD0P/GPIO185 H9
J8
(37) SIO_A20GATE GA20IN/GEVENT0# USB_FSD0N
MISC
SIO_RCIN#
1.1
RN2103 (37) SIO_RCIN# AE21 KBRST#/GEVENT1#
(37) SIO_EXT_SCI# K2 LPC_PME#/GEVENT3# USB_HSD13P B12
USB
1 4 SMB_DATA (37) SIO_EXT_SMI# J29 A12
LPC_SMI#/GEVENT23# USB_HSD13N
USB
2 3 SMB_CLK C2105 H2
SCD047U10V2KX-2GP TP2120 SYS_RESET# GEVENT5#
1 J1 F11
2
SYS_RESET#/GEVENT19# USB_HSD12P
SRN10KJ-5-GP (76) PCIE_W AKE# H6 WAKE#/GEVENT8# USB_HSD12N E11
F3 IR_RX1/GEVENT20# USB
SB_THERMTRIP#
9/22 (10,37,39,42,82) H_THERMTRIP# 1
R2109
2
0R0402-PAD
J6
AC19
THRMTRIP#/SMBALERT#/GEVENT2# USB_HSD11P E14
E12
USB_PP11 (54)
Pair Device
(41) NB_PW RGD NB_PWRGD USB_HSD11N USB_PN11 (54)
1 2 R2132 TALERT#
SCD1U10V2KX-5GP
10KR2J-3-GP (37) KBC_RSMRST# R2111 1 2 PM_RSMRST#_R G1

RSMRST# USB_HSD10P J12 USB_PP10 (78) 0 USB0 (I/O Board/ESATA)
C2104
SCD1U10V2KX-5GP
0R0402-PAD Close SB USB_HSD10N J14 USB_PN10 (78)
1
C2101
1
DY 2 R2108 SB_TEST2
1231-1 AD19 CLK_REQ4#/SATA_IS0#/GPIO64 1 USB1 (I/O Board)
1
2K2R2J-2-GP AA16 A13 USB_PP9 (73)
CLK_REQ3#/SATA_IS1#/GPIO63 USB_HSD9P
GP_PCIE_RST# GP_PCIE_RST# AB21 B13 USB_PN9 (73) 2 USB2 (CRT Board)
2
(20) GP_PCIE_RST# SMARTVOLT1/SATA_IS2#/GPIO50 USB_HSD9N

2 R2110 SB_TEST1
1
DY AC18
DY
2
CLK_REQ0#/SATA_IS3#/GPIO60
2K2R2J-2-GP
9/25 AF20 9/23 SATA_IS4#/FANOUT3/GPIO55 USB_HSD8P D13 3 USB3 (CRT Board)
AE19 SATA_IS5#/FANIN3/GPIO59 USB_HSD8N C13
1
DY 2 R2112 SB_TEST0
(30) ACZ_SPKR AF19 SPKR/GPIO66 4 WLAN USB
2K2R2J-2-GP SB_SMBCLK_R AD22 G12
(7,18) SB_SMBCLK_R SCL0/GPIO43 USB_HSD7P
SB_SMBDATA_R AE22 WWAN USB
USB 2.0
(7,18) SB_SMBDATA_R SDA0/GPIO47 USB_HSD7N G14 5
1 2 R2113 PCIE_W AKE# SMB_CLK F5 SCL1/GPIO227
C 10KR2J-3-GP SMB_DATA F4 SDA1/GPIO228 USB_HSD6P G16 6 RESERVED C
TP2127 1 CLK_REQ2# AH21 G18
CLK_REQ2#/FANIN4/GPIO62 USB_HSD6N
1
DY 2 R2114 KBC_RSMRST# SP_VRAM_SEL AB18
CLK_REQ1#/FANOUT4/GPIO61 7 RESERVED
10KR2J-3-GP E1 D16 USB_PP5
IR_LED#/LLB#/GPIO184 USB_HSD5P USB_PP5 (76)
R2131 TP2113 1 SB_GPIO51 AJ21 SMARTVOLT2/SHUTDOWN#/GPIO51 USB_HSD5N C16 USB_PN5
USB_PN5 (76) 8 RESERVED
1 2 R2115 SIO_EXT_W AKE#
(14) SP_DDR3_RST# 1 UMA_SPM
2 GEVENT7# H4 DDR3_RST#/GEVENT7#
10KR2J-3-GP 0R2J-2-GP D5 GBE_LED0/GPIO183 USB_HSD4P B14 USB_PP4 (76) 9 BLUETOOTH
D7 GBE_LED1/GEVENT9# USB_HSD4N A14 USB_PN4 (76)
1
DY 2 R2116 SIO_EXT_SCI# G5 GBE_LED2/GEVENT10# 10 CARD READER
10KR2J-3-GP
GPIO
K3 GBE_STAT0/GEVENT11# USB_HSD3P E18 USB_PP3 (77)
(7) SB_14M_CLK 1 DY 2R2128 SB_OSCIN AA20 CLK_REQG#/GPIO65/OSCIN/IDLEEXT# USB_HSD3N E16 USB_PN3 (77) 11 CAMERA (LVDS CONN)
R2117 SIO_EXT_SMI# 0R2J-2-GP
1
DY 2 9/23
SCD1U10V2KX-5GP
10KR2J-3-GP
USB_HSD2P J16 USB_PP2 (77) 12 RESERVED
C2103
TP2133 USB_OC7#
9/22 1 H3 BLINK/USB_OC7#/GEVENT18# USB_HSD2N J18 USB_PN2 (77)
1
TP2129 1 USB_OC6# D1 USB_OC6#/IR_TX1/GEVENT6# 13 RESERVED

R2118 SB_SDIN_CODEC USB_PP1
1
DY 2 (10,39) TALERT# E4 USB_OC5#/IR_TX0/GEVENT17# USB_HSD1P B17 USB_PP1 (76)
USB OC
10KR2J-3-GP TP2132 1 USB_OC4# D4 A17 USB_PN1
USB_PN1 (76)
2
R2119 ACZ_BIT_CLK TP2131 USB_OC4#/IR_RX0/GEVENT16# USB_HSD1N

1 USB_OC3#
1
DY 2 10KR2J-3-GP TP2130 1 USB_OC2#
E8
F7
USB_OC3#/AC_PRES/TDO/GEVENT15#
A16 USB_PP0 (76)
USB_OC#2_3 USB_OC2#/TCK/GEVENT14# USB_HSD0P
(63) USB_OC#2_3 E7 USB_OC1#/TDI/GEVENT13# USB_HSD0N B16 USB_PN0 (76)
1 2 R2133 SP_VRAM_SEL (63) USB_OC#0_1 USB_OC#0_1 F8 USB_OC0#/TRST#/GEVENT12#
0R2J-2-GP
VRAMUMA_SPM_Hynix 1116-3 (24) ACZ_SDATAOUT_R
0225-4 (30) SB_AZ_CODEC_BITCLK

R2120 1 2 33R2J-2-GP ACZ_BIT_CLK M3 AZ_BITCLK SCL2/GPIO193 D25 SCL2 Not use
R2121 1 2 33R2J-2-GP N1 F23 SDA2
(30) SB_AZ_CODEC_SDOUT AZ_SDOUT SDA2/GPIO194
(30) SB_SDIN_CODEC 9/16 L2
M2
AZ_SDIN0/GPIO167 SCL3_LV/GPIO195 B26
E26
CPU_SIC (10)
AZ_SDIN1/GPIO168 SDA3_LV/GPIO196 CPU_SID (10)
1 EC2101
B DY
2
SC180P50V2JN-1GP
M1
M4
AZ_SDIN2/GPIO169 EC_PWM0/EC_TIMER0/GPIO197 F25
E22
B
R2122 33R2J-2-GP ACZ_SYNC_R AZ_SDIN3/GPIO170 EC_PWM1/EC_TIMER1/GPIO198
(30) SB_AZ_CODEC_SYNC 1 2 N2 AZ_SYNC EC_PWM2/EC_TIMER2/GPIO199 F22 SB_GPO199 (24)
R2123 1 2 33R2J-2-GP ACZ_RST#_R P2 E21 SB_GPO200 (24)
(30) SB_AZ_CODEC_RST# AZ_RST# EC_PWM3/EC_TIMER3/GPIO200
SC180P50V2JN-1GP
HD AUDIO
EC2102
DY KSI_0/GPIO201 G24
1
+3.3V_ALW GBE_COL
10/1 GBE_CRS
T1 GBE_COL KSI_1/GPIO202 G25
Strap Pin / define to use LPC or SPI ROM
9/16 T4 E28
GbE MAC Not Enabled
GBE_CRS KSI_2/GPIO203
RN2102 L6 E29
2
GBE_COL GBE_MDIO GBE_MDCK KSI_3/GPIO204

1 8 L5 GBE_MDIO KSI_4/GPIO205 D29
2 7 GBE_CRS T9 D28
EC Not Implemented
GBE_RXERR GBE_RXCLK KSI_5/GPIO206
3 6 U1 GBE_RXD3 KSI_6/GPIO207 C29
4 5 GBE_MDIO U3 C28
GBE_RXD2 KSI_7/GPIO208
T2 GBE_RXD1
GBE LAN
SRN10KJ-6-GP U2 B28
GBE_RXD0 KSO_0/GPIO209
T5 GBE_RXCTL/RXDV KSO_1/GPIO210 A27
R2124 1 210KR2J-3-GP GBE_PHY_INTR GBE_RXERR V5 B27
GBE_RXERR KSO_2/GPIO211
P5 GBE_TXCLK KSO_3/GPIO212 D26
M5 GBE_TXD3 KSO_4/GPIO213 A26
RN2104 P9 C26
SCL2 GBE_TXD2 KSO_5/GPIO214
1 4 T7 GBE_TXD1 KSO_6/GPIO215 A24
2 3 SDA2 P7 B25
GBE_TXD0 KSO_7/GPIO216
EMBEDDED CTRL
M7 GBE_TXCTL/TXEN KSO_8/GPIO217 A25
SRN10KJ-5-GP P4 GBE_PHY_PD KSO_9/GPIO218 D24
M9 GBE_PHY_RST# KSO_10/GPIO219 B24
GBE_PHY_INTR
9/23 9/24 V7 GBE_PHY_INTR KSO_11/GPIO220 C24
B23
TP2135 TP_DEBUG_DAT KSO_12/GPIO221
1 E23 PS2_DAT/SDA4/GPIO187 KSO_13/GPIO222 A23
TP2134 1 TP_DEBUG_CLK E24 D22
TP2116 SPI_CS2# PS2_CLK/SCL4/GPIO188 KSO_14/GPIO223
EMBEDDED CTRL
A 1 F21 SPI_CS2#/GBE_STAT2/GPIO166 KSO_15/GPIO224 C22 <Core Design> A

TP2117 1 GPO160 G29 A22
FC_RST#/GPO160 KSO_16/GPIO225
KSO_17/GPIO226 B22
D27
F28
PS2KB_DAT/GPIO189
PS2KB_CLK/GPIO190
Wistron Corporation
EC Not Implemented F29
E27
PS2M_DAT/GPIO191 Taipei Hsien 221, Taiwan, R.O.C.
PS2M_CLK/GPIO192
Title
SB820M-1-GP SB820M_USB&GPIO_(2/5)
A3
5 4 3 2 1
SSID = S.B
U2B
Part 2 of 5
(59) SATA_TXP0 C2201 1 2SCD01U50V2ZY-1GP SATA_TXP0_C AH9 AH28
C2202 1 SATA_TX0P FC_CLK
(59) SATA_TXN0 2SCD01U50V2ZY-1GP SATA_TXN0_C AJ9 SATA_TX0N FC_FBCLKOUT AG28
SATA HDD (59) SATA_RXN0 C2203 1 2SCD01U50V2ZY-1GP SATA_RXN0_C AJ8
FC_FBCLKIN AF26
C2204 1 SATA_RX0N
(59) SATA_RXP0 2SCD01U50V2ZY-1GP SATA_RXP0_C AH8 SATA_RX0P FC_OE#/GPIOD145 AF28
FC_AVD#/GPIOD146 AG29
(59) SATA_TXP1 C2205 1 2SCD01U50V2ZY-1GP SATA_TXP1_C AH10 AG26
C2206 1 SATA_TX1P FC_WE#/GPIOD148
(59) SATA_TXN1 2SCD01U50V2ZY-1GP SATA_TXN1_C AJ10 SATA_TX1N FC_CE1#/GPIOD149 AF27
SATA ODD (59) SATA_RXN1 C2208 1 2SCD01U50V2ZY-1GP SATA_RXN1_C AG10
FC_CE2#/GPIOD150 AE29
AF29
C2207 1 SATA_RX1N FC_INT1/GPIOD144
(59) SATA_RXP1 2SCD01U50V2ZY-1GP SATA_RXP1_C AF10 SATA_RX1P FC_INT2/GPIOD147 AH27
(76) SATA_TXP2 C2211 1 2SCD01U50V2ZY-1GP SATA_TXP2_C AG12 AJ27

C2214 1 SATA_TX2P FC_ADQ0/GPIOD128
(76) SATA_TXN2 2SCD01U50V2ZY-1GP SATA_TXN2_C AF12 SATA_TX2N FC_ADQ1/GPIOD129 AJ26
E-SATA (76) SATA_RXN2 SATA_RXN2 AJ12
FC_ADQ2/GPIOD130 AH25
AH24
SATA_RXP2 SATA_RX2N FC_ADQ3/GPIOD131
(76) SATA_RXP2 AH12 SATA_RX2P FC_ADQ4/GPIOD132 AG23
FC_ADQ5/GPIOD133 AH23
10/6 AH14
AJ14
SATA_TX3P FC_ADQ6/GPIOD134 AJ22
AG21
GPIOD[150:128] are open drain GPIO pins
SATA_TX3N FC_ADQ7/GPIOD135 where as GPO160 is an open drain GPO pin.
FC_ADQ8/GPIOD136 AF21
AG14 SATA_RX3N FC_ADQ9/GPIOD137 AH22 These pins are not programmed to GPIO mode by default.
AF14 SATA_RX3P FC_ADQ10/GPIOD138 AJ23
PLACE SATA AC DECOUPLING FC_ADQ11/GPIOD139 AF23
AG17 AJ24
CAPS CLOSE TO SB820M AF17
SATA_TX4P FC_ADQ12/GPIOD140
AJ25
SATA_TX4N FC_ADQ13/GPIOD141
FC_ADQ14/GPIOD142 AG25 If use as GPIO, need to pull up to 1.8V_RUN
AJ17 SATA_RX4N FC_ADQ15/GPIOD143 AH26
AH17
FLASH
SATA_RX4P
Very Close AJ18

AH18
SATA_TX5P
W5
SATA_TX5N FANOUT0/GPIO52
to SB820 FANOUT1/GPIO53 W6
AH19 SATA_RX5N FANOUT2/GPIO54 Y9
AJ19
SERIAL ATA
SATA_RX5P
FANIN0/GPIO56 W7
1KR2F-3-GP V9
+1.1V_RUN_AVDD_SATA R2201 FANIN1/GPIO57
1 2 SATA_CALP AB14 SATA_CALRP FANIN2/GPIO58 W8
1 2 SATA_CALN AA14 SATA_CALRN 1119-1
R2202 931R2F-1-GP B6 TEMPIN0
TEMPIN0/GPIO171 TEMPIN1
(66) SATA_LED# AD11
TEMPIN1/GPIO172 A6
A5 TEMPIN2
Move to P.51
SATA_ACT#/GPIO67 TEMPIN2/GPIO173 TEMPIN3
9/15 TEMPIN3/TALERT#/GPIO174 B5
C7
9/22
TEMP_COMM
VIN0
XTAL SATA_X1 AD16
VIN0/GPIO175 A3
B4 VIN1
SATA_X1 VIN1/GPIO176
1'nd 82.30020.851 VIN2/GPIO177 A4 VIN2
VIN3
2'nd 82.30020.791 VIN3/GPIO178 C5
MEM_1V5
10/9
C2209 DY VIN4/GPIO179 A7
B7 VIN5
MEM_1V5 (51)
VIN5/GPIO180
XTAL-25MHZ-102-GP
1 2 SATA_X1 B8 VIN6
SATA_X2 VIN6/GBE_STAT3/GPIO181 VIN7
HW MONITOR
DY AC16 SATA_X2 VIN7/GBE_LED3/GPIO182 A8
1
+3.3V_ALW
10MR2J-L-GP
SC12P50V2JN-3GP
DY
X2201
R2204
RN2201
TEMPIN0
C2210 DY TEMPIN1
1
2
8
7
2
1 2 SATA_X2 J5 G27 TEMPIN2 3 6

2
SPI_DI/GPIO164 NC#G27 TEMPIN3

E2 SPI_DO/GPIO163 NC2#Y2 Y2 4 5
SPI ROM
SC12P50V2JN-3GP K4
K9
SPI_CLK/GPIO162 9/16 SRN10KJ-6-GP
SPI_CS1#/GPIO165
G2 ROM_RST#/GPIO161 10/1 +3.3V_ALW
9/24 SB820M-1-GP VIN2
RN2202
SPI ROM in KBC side VIN0
1
2
8
7
VIN1 3 6
VIN3 4 5
10/9 SRN10KJ-6-GP
+3.3V_ALW
RN2203
VIN7 1 8
VIN6 2 7
VIN5 3 6
4 5
SRN10KJ-6-GP 1116-1
<Core Design>
Wistron Corporation
Title
SB820M_SATA-IDE_(3/5)
A3
5 4 3 2 1
+3.3V_RUN
R2301
+3.3V_SB_VDDIO
78mA
SSID = S.B
1 2
SC10U6D3V5KX-1GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
U2E
TC2301
C2301
C2302
C2303
0R0603-PAD
1
1231-1 Part 5 of 5
DY DY Y14 AJ2
2
VSSIO_SATA VSS
Y16 VSSIO_SATA VSS A28
AB16 VSSIO_SATA VSS A2
AC14 VSSIO_SATA VSS E5
D U2C +1.1V_RUN AE12 D23 D
VSSIO_SATA VSS
Part 3 of 5 790mA AE14 VSSIO_SATA VSS E25
AH1 VDDIO_33_PCIGP VDDCR_11 N13 AF9 VSSIO_SATA VSS E6
+1.8V_RUN +1.8V_SB_VDDIO_FC
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC10U6D3V5KX-1GP
R2302 V6 VDDIO_33_PCIGP VDDCR_11 R15 AF11 VSSIO_SATA VSS F24
C2304
C2308
C2309
C2310
C2311
0.15mA Y19 VDDIO_33_PCIGP VDDCR_11 N17 AF13 VSSIO_SATA VSS N15
1
CORE S0
1 2 AE5 VDDIO_33_PCIGP VDDCR_11 U13 AF16 VSSIO_SATA VSS R13
SCD1U10V2KX-5GP
AC21 VDDIO_33_PCIGP VDDCR_11 U17 AG8 VSSIO_SATA VSS R17
C2307
9/17 AA2 V12
DY DY AH7 T10
2
0R0603-PAD VDDIO_33_PCIGP VDDCR_11 VSSIO_SATA VSS
1
AB4 VDDIO_33_PCIGP VDDCR_11 V18 AH11 VSSIO_SATA VSS P10
1231-1 AC8 VDDIO_33_PCIGP VDDCR_11 W12 AH13 VSSIO_SATA VSS V11
Removed DY AA7 W18 AH16 U15
2
VDDIO_33_PCIGP VDDCR_11 VSSIO_SATA VSS
AA9 VDDIO_33_PCIGP AJ7 VSSIO_SATA VSS M18
AF7 VDDIO_33_PCIGP AJ11 VSSIO_SATA VSS V19
AA19 K28 +1.1V_RUN_SB_CLKGEN +1.1V_RUN AJ13 M11
PCI/GPIO I/O
VDDIO_33_PCIGP VDDAN_11_CLK VSSIO_SATA VSS
VDDAN_11_CLK K29
J28
382mA 1 2
AJ16 VSSIO_SATA VSS L12
L18
VDDAN_11_CLK VSS
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC10U6D3V5KX-1GP
+3.3V_RUN +3.3V_VDDPL_PCIE K26 R2304 0R0603-PAD A9 J7
VDDAN_11_CLK VSSIO_USB VSS
C2315
C2316
C2317
C2318
TC2302
L2301
11mA VDDAN_11_CLK J21 B10 VSSIO_USB VSS P3
1
SCD1U10V2KX-5GP
1 2 AF22 VDDIO_18_FC VDDAN_11_CLK J20 1231-1 K11 VSSIO_USB VSS V4

SC2D2U6D3V3KX-GP
C2313
C2314
AE25 VDDIO_18_FC VDDAN_11_CLK K21 B9 VSSIO_USB VSS AD6

1
BLM15AG221SS1D-GP AF24 J22

DY DY D10 AD4
2
VDDIO_18_FC VDDAN_11_CLK VSSIO_USB VSS
220R, 0.3A AC22 VDDIO_18_FC D12 VSSIO_USB VSS AB7
DY D14 AC9
2
VSSIO_USB VSS
CLKGEN I/O
VDDRF_GBE_S V1 D17 VSSIO_USB VSS V8
1119-1 POWER E9 W9
FLASH I/O
VSSIO_USB VSS
VDDIO_33_GBE_S M10 F9 VSSIO_USB VSS W10
F12 VSSIO_USB VSS AJ28
9/15 AE28 VDDPL_33_PCIE GBE PHY not used F14 VSSIO_USB VSS B29
GBE LAN
+1.1V_RUN +1.1V_RUN_PCIE_VDDR F16 U4
C L2303 +3.3V_ALW VSSIO_USB VSS C
690mA C9 VSSIO_USB VSS Y18
PCI EXPRESS
1 2 U26 VDDAN_11_PCIE VDDCR_11_GBE_S L7
49mA G11 VSSIO_USB VSS Y10
SC10U6D3V5KX-1GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
PBY160808T-330Y-N-GP V22 L9 F18 Y12
GROUND
VDDAN_11_PCIE VDDCR_11_GBE_S VSSIO_USB VSS
TC2303
C2321
C2322
SC2D2U6D3V3KX-GP
SC2D2U6D3V3KX-GP
33R, 3A V26 VDDAN_11_PCIE D9 VSSIO_USB VSS Y11
1
1
C2319
C2320
C2323
C2324
V27 VDDAN_11_PCIE H12 VSSIO_USB VSS AA11
1
V28 VDDAN_11_PCIE VDDIO_GBE_S M6 H14 VSSIO_USB VSS AA12
DY DY DY V29 P8 H16 G4
2
VDDAN_11_PCIE VDDIO_GBE_S VSSIO_USB VSS

W22 H18 J4
2
VDDAN_11_PCIE VSSIO_USB VSS
W26 VDDAN_11_PCIE J11 VSSIO_USB VSS G8
J19 VSSIO_USB VSS G9
+3.3V_RUN +3.3V_VDDPL_SATA K12 M12
L2304 VSSIO_USB VSS
1 2
15mA AD14
K14
K16
VSSIO_USB VSS AF25
H7
VDDPL_33_SATA VSSIO_USB VSS
SC2D2U6D3V3KX-GP
SCD1U10V2KX-5GP
A21 +1.1V_ALW K18 AH29

VDDIO_33_S VSSIO_USB VSS
C2325
C2326
BLM15AG221SS1D-GP AJ20 VDDAN_11_SATA VDDIO_33_S D21

113mA H19 VSSIO_USB VSS V10
1
220R, 0.3A AF18 VDDAN_11_SATA VDDIO_33_S B21 VSS P6

AH20 VDDAN_11_SATA VDDIO_33_S K10 VSS N4
+3.3V_ALW
C2327
C2328
DY AG19 L10
15mA Y4 L4
2
VDDAN_11_SATA VDDIO_33_S EFUSE VSS
1
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
1119-1 AE18
AD18
VDDAN_11_SATA VDDIO_33_S J9
T6 1 20R0402-PAD D8
VSS L8
VDDAN_11_SATA VDDIO_33_S VSSAN_HWM
SC2D2U6D3V3KX-GP
C2329
AE16 T8 R2303
2
VDDAN_11_SATA VDDIO_33_S
1
9/15
+1.1V_RUN +1.1V_RUN_AVDD_SATA
SERIAL ATA 1231-1 M19 VSSXL VSSPL_SYS M20
3.3V_S5 I/O
L2305
1350mA
2
1 2 CORE S5 VDDCR_11_S F26 P21 VSSIO_PCIECLK VSSIO_PCIECLK H23
SC10U6D3V5KX-1GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
PBY160808T-330Y-N-GP A18 G26 P20 H26

VDDAN_33_USB_S VDDCR_11_S VSSIO_PCIECLK VSSIO_PCIECLK
TC2304
C2332
C2333
33R, 3A A19 VDDAN_33_USB_S M22 VSSIO_PCIECLK VSSIO_PCIECLK AA21

1
1
C2330
C2331
A20 M8 +3.3VALW _VDDIO_AZ M24 AA23

VDDAN_33_USB_S VDDIO_AZ_S +1.1V_ALW _VDDR_USB +1.1V_ALW VSSIO_PCIECLK VSSIO_PCIECLK
B18 VDDAN_33_USB_S M26 VSSIO_PCIECLK VSSIO_PCIECLK AB23
B L2306 B
DY DY B19 A11
58mA P22 AD23
2
VDDAN_33_USB_S VDDCR_11_USB_S VSSIO_PCIECLK VSSIO_PCIECLK

B20 VDDAN_33_USB_S VDDCR_11_USB_S B11 1 2 P24 VSSIO_PCIECLK VSSIO_PCIECLK AA26
USB I/O
BLM15AG221SS1D-GP
1119-1 C18 VDDAN_33_USB_S P26 VSSIO_PCIECLK VSSIO_PCIECLK AC26
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SC10U6D3V5KX-1GP
C20 VDDAN_33_USB_S 220R, 0.3A T20 VSSIO_PCIECLK VSSIO_PCIECLK Y20
C2334
C2335
C2336
D18 VDDAN_33_USB_S VDDPL_33_SYS M21 3.3V_RUN_VDDPL T22 VSSIO_PCIECLK VSSIO_PCIECLK W21
1
+3.3V_ALW +3.3V_AVDD_USB D19 T24 W20
L2307 VDDAN_33_USB_S 1.1V_ALW _VDDPL VSSIO_PCIECLK VSSIO_PCIECLK
534mA D20 VDDAN_33_USB_S VDDPL_11_SYS_S L22 V20 VSSIO_PCIECLK VSSIO_PCIECLK AE26
1 2 E19
DY J23 L21
2
VDDAN_33_USB_S VSSIO_PCIECLK VSSIO_PCIECLK
PLL
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC10U6D3V5KX-1GP
SC10U10V5ZY-1GP
PBY160808T-221Y-N-GP F19 K20

VDDPL_33_USB_S VSSIO_PCIECLK
C2339
1
1
C2337
C2338
C2340
220R, 2A C11
D11
VDDAN_11_USB_S VDDAN_33_HWM_S D6 1119-1
VDDAN_11_USB_S 3.3V_ALW _VDDXL SB820M-1-GP
L20
2
VDDXL_33_S
9/17 +3.3V_AVDD_USB
+1.1V_ALW +1.1V_AVDD_USB SB820M-1-GP
L2309 16mA
88mA
SCD1U10V2KX-5GP
SC2D2U6D3V3KX-GP
1 2
SC2D2U6D3V3KX-GP
SCD1U10V2KX-5GP
C2347
C2348
1
1
C2343
C2344
BLM15AG221SS1D-GP
1
220R, 0.3A
2
2
5mA 65mA 46mA

+3.3V_ALW
A
+3.3V_ALW +1.1V_ALW +3.3V_RUN <Core Design> A
L2308 L2312 L2313 12mA
SCD1U10V2KX-5GP
3.3V_ALW _VDDXL 1.1V_ALW _VDDPL 3.3V_RUN_VDDPL
1 2 1 2 1 2
Wistron Corporation
SCD1U10V2KX-5GP
SC2D2U6D3V3KX-GP
SC2D2U6D3V3KX-GP
SC2D2U6D3V3KX-GP
C2345
BLM15AG221SS1D-GP
1
C2341
C2342
C2349
C2350
BLM15AG221SS1D-GP BLM15AG221SS1D-GP 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

220R, 0.3A 10/1
1

9/15 220R, 0.3A 220R, 0.3A
DY
2
Title
DY Removed
2
SB820M_POWER&GND_(4/5)
A3
5 4 3 2 1
5 4 3 2 1
SSID = S.B
REQUIRED STRAPS DEBUG STRAPS

D
+3.3V_RUN +3.3V_ALW
9/15 D
9/22
R2401
R2402
R2403
R2404
R2405
R2406
R2407
R2408
R2409
PCI_AD23 (20)
VDDR_SEL (20,51)
PCI_AD25 (20)
1
9/15 PCI_AD26 (20)
PCI_AD27 (20)
DYDYDYDY DY DY DY DY
1119-1
1 R2411
1 R2412
1 R2413
1 R2414
1 R2415
2K2R2F-GP
2K2R2F-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
DYDYDYDYDY
2
(20) PCI_CLK1
Removed
2K2R2J-2-GP
2K2R2J-2-GP
2K2R2J-2-GP
2K2R2J-2-GP
2K2R2J-2-GP
(20) PCI_CLK2
(20) PCI_CLK3
(20,70) PCLK_FW H
9/23
C (20,37) PCLK_KBC C
(20) LPCCLK1
(21) SB_GPO200
(21) SB_GPO199
(21) ACZ_SDATAOUT_R
R2416
R2417
R2418
R2419
R2420
R2421
R2422
R2423
R2424
1
1
DY DY DY
2
2
2K2R2F-GP
2K2R2F-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
B USE this pin to determine INT/EXT CLK B

REQUIRED SYSTEM STRAPS
PCLK_KBC PCLK_FWH PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23
AZ_SDOUT# PCI_CLK1 PCI_CLK2 LPCCLK0 LPCCLK1 SB_GPO200 , SB_GPO199
(PCI_CLK3) (PCI_CLK4) ROM TYPE:
USE PCI Disable ILA USE FC USE DEFAULT
PULL Allow WatchDOG USE PULL PLL AUTORUN PLL PCIE STRAPS Disable PCI
PCIE GEN2 (NB_PWRGD) DEBUG non_Fusion ENABLE EC CLKGEN H, H = Reserved MEM BOOT
HIGH LOW POWER HIGH
ENABLED STRAPS CLOCK mode ENABLED
MODE (DEFAULT) (DEFAULT) (DEFAULT) (DEFAULT) (DEFAULT)
DEFAULT DEFAULT (Use Internal) H, L = SPI ROM
DEFAULT BYPASS Enable ILA BYPASS FC USE EEPROM Enable PCI
PULL PERFORMANCE Force WatchDog IGNORE DISABLE EC CLKGEN L, H = LPC ROM DEFAULT PULL PCI PLL AUTORUN PLL PCIE STRAPS MEM BOOT
MODE PCIE GEN1 (NB_PWRGD) DEBUG Fusion DISABLED
LOW LOW
DISABLED STRAPS CLOCK mode
(Use External) L, L = FWH ROM
DEFAULT DEFAULT DEFAULT DEFAULT
Note: SB820M has 15K internal PU FOR PCI_AD[27:23]
A <Core Design> A
Wistron Corporation
Title
SB820M_STRAPPING_(5/5)
A3
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
<Core Design>
A
Title
Size
Reserved
Document Number Rev
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Size
Reserved
Document Number Rev
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
5 4 3 2 1
5 4 3 2 1
SSID = AUDIO
3.3V, 25mA
+AVDD
+5V_RUN
+3.3V_RUN +3.3V_RUN
1231-1
Close to codec 84mA R3002
1 2
Close to codec
SC1U10V3KX-3GP
D D
SCD1U10V2KX-5GP
AUD_DVDDCORE 0R0603-PAD +5V_RUN
+PVDD 1231-1
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1
1.4A R3003
C3005
C3006
SC1U6D3V2KX-GP
1
1
C3002
C3003 1 2
SC10U6D3V5KX-1GP
C3001
C3004
2
U3001
SCD1U10V2KX-5GP
0R0603-PAD
SC1U10V3KX-3GP
SC10U10V5ZY-1GP
2
1
R3004
C3008
C3009
C3010
1 27
DVDD_CORE AVDD
38 1 2
AVDD AUD_AGND
9
2
DVDD 0R0603-PAD
39
PVDD
3 45
DVDD_IO PVDD
13 AUD_SENSE_A
SB_AZ_CODEC_BITCLK SENSE_A AUD_SENSE_B AUD_AGND
6 14
(21) SB_AZ_CODEC_BITCLK HDA_BITCLK SENSE_B
R3001 1 2 33R2J-2-GP SB_SDIN_CODEC_C0 8
(21) SB_SDIN_CODEC HDA_SDI AUD_EXT_MIC_L
28 AUD_EXT_MIC_L (60)
SB_AZ_CODEC_SDOUT HP0_PORT_A_L AUD_EXT_MIC_R
9/23 (21) SB_AZ_CODEC_SDOUT
5
HDA_SDO HP0_PORT_A_R
29
23 AUD_VREFOUT_B
AUD_EXT_MIC_R (60)
VREFOUT_A_OR_F AUD_VREFOUT_B (60)
SB_AZ_CODEC_SYNC 10
(21) SB_AZ_CODEC_SYNC HDA_SYNC AUD_HP1_JACK_L R3005
31 1 2 60D4R2F-GP
SB_AZ_CODEC_RST# HP1_PORT_B_L AUD_HP1_JACK_R R3006 AUD_HP1_JACK_L2 (60)
11 32 1 2 60D4R2F-GP
(21) SB_AZ_CODEC_RST# HDA_RST# HP1_PORT_B_R AUD_HP1_JACK_R2 (60)
19 AUD_INT_MIC_R_L C3011 1 2 SC1U10V3KX-3GP
PORT_C_L INT_MIC_L_R (60)
20
PORT_C_R AUD_VREFOUT_C R3007 1
24 2 2K2R2J-2-GP 9/17
TP3001 AUD_DMIC_CLK VREFOUT_C
+3.3V_RUN TP3002
1
1 AUD_DMIC_IN0
2
4
DMIC_CLK/GPIO1
40 AUD_SPK_L+
1129-2 R3009 From SB
DMIC0/GPIO2 SPKR_PORT_D_L+ AUD_SPK_L- AUD_SPK_L+ (60) C3012
41 120KR2F-L-GP
SPKR_PORT_D_L- AUD_SPK_L- (60) SB_SPKR_R
46 1 2SCD1U10V2KX-5GP 1 2 ACZ_SPKR (21)
DMIC1/GPIO0/SPDIF_OUT_1 AUD_SPK_R-
43
SPKR_PORT_D_R- AUD_SPK_R- (60)
1
48 44 AUD_SPK_R+ 1 2 KBC_BEEP_R 1 2
SPDIF_OUT_0 SPKR_PORT_D_R+ AUD_SPK_R+ (60) SCD1U10V2KX-5GP KBC_BEEP (37)
R3008 R3010
10KR2J-3-GP AMP_MUTE# 47 15 C3013 499KR2F-1-GP From EC
(37) AMP_MUTE# EAPD PORT_E_L
16
PORT_E_R
2
PUMP_CAPN 17
AMP_MUTE# PORT_F_L AUD_PC_BEEP
35 18
1
CAP- PORT_F_R
C3014
C
SC2D2U6D3V3KX-GP 36
PC_BEEP
12 AUD_PC_BEEP C
2
CAP+
PUMP_CAPP
MONO_OUT
25 Trace width>15 mils
11/9 7
DVSS
33 22 AUD_CAP2
AVSS CAP2
30
AVSS AUD_VREFFLT
26 21
AVSS VREFFILT
42 34 AUD_V_B
PVSS V-
49 37 AUD_VREG
GND VREG
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC4D7U6D3V3KX-GP
SC1U6D3V2KX-GP
92HD79B1A5NLGXTAX-GP
C3016
C3015
1
1
C3017
C3018
AUD_AGND
2
Reserve AUD_HP1_JACK_R2 AUD_HP1_JACK_L2
AUD_AGND AUD_AGND AUD_AGND AUD_AGND
D
Close to codec Q3002
P8503BMG-GP
Q3003
P8503BMG-GP
DY G G
DY
S
CODEC_Q2601_03 CODEC_Q2602_04
S
+15V_ALW
G G
B B
P8503BMG-GP DY DY P8503BMG-GP
Q3004 Q3005
D
R3013
DY100KR2J-1-GP
Azalia I/F EMI
2
SB_AZ_CODEC_SDOUT HP_CODEC_MUTE
1
D
R3015
47R2J-2-GP
1231-1 Q3001
DY +AVDD R3016 +AVDD R3014
20KR2F-L-GP 2 1 AMP_MUTE# G
DY
2
1 2 2N7002A-7-GP
1
AUD_HP1_JD# (60) 0R0603-PAD

SB_AZ_CODEC_SDOUT1
R3018 R3019
S
2K49R2F-GP 2K49R2F-GP R3017
2 1
2
AUD_SENSE_A AUD_SENSE_B 0R0603-PAD

1
1
R3021
C3019 R3022 20KR2F-L-GP 2 R3020 1
SCD1U10V2KX-5GP
SC1000P50V3JN-GP-U 39K2R2F-L-GP
2
C3020
2 1 0R0603-PAD
2
EXT_MIC_JD# (60)
1
AUD_AGND
AUD_AGND
DY
2
AUD_AGND
Close to Pin13
Close to Pin14
A A
<Core Design>
Wistron Corporation
Title
Audio Codec 92HD79B1
A2 A00
Date:
Berry AMD Discrete/UMA
Thursday, March 04, 2010
Sheet 30 of 95
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
<Core Design>
A
Title
Size
Reserved
Document Number Rev
A4
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
5 4 3 2 1
A B C D E
4 4
3 3
(Blanking)
2 2
1 <Core Design> 1
Wistron Corporation
Title
Reserved
A3
A B C D E
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
5 4 3 2 1
+KBC_PWR 5
9/16 4 3 2 +KBC_PWR 1
R3701
CAP close to VCC-GND pin pair +3.3V_RUN
SSID = KBC
1
1 2
0R3J-0-U-GP DY +3.3V_RTC_LDO
3.3V, 2mA R3703
100KR2J-1-GP
SCD1U10V2KX-5GP
VBAT
C3702
L3701 1 2 BLM18AG601SN-3GP 1120-5
1
R3709
2
C3703 KBC_PWRBTN_EC#
1119-1 DY 2
DY 1
SC2D2U6D3V3KX-GP
SC2D2U6D3V3KX-GP
3.3V, 23mA SC2D2U10V3KX-1GP 0R2J-2-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
2
C3701
C3704
C3705
C3706
C3707
C3708
C3709
C3710
1
2
3 +3.3V_RTC_LDO +KBC_PWR
2
DY (66) KBC_PWRBTN#
115
102
+3.3V_RUN
88
76
46
19
80
4
U3701A 1 OF 2 D3702
BAT_IN# (44)
1
BAT54C-U-GP
GPIO41
VCC
VCC
VCC
VCC
VCC
AVCC
VDD
1
R3704
G
KBC_AGND
9/24 1
R3702 DY 2
0R2J-2-GP +3.3V_RTC_LDO
10KR2J-3-GP
+KBC_PWR
D Reserved R3707 104 124 WWAN_RADIO_DIS# (76)
D
2
VREF GPIO10/LPCPD# PLTRST#_EC KBC_ON# EC_SHUTDOWN#
1 2 11/6 AD_IA_KBC LRESET#
7 U3702
Q3703
D
Q3705
S
10KR2J-3-GP S0_LKG_DET
97
98
GPI90/AD0 A/D LCLK
2
3
PCLK_KBC (20,24)
4 3 KBC_SDA1 SI2301CDS-T1-GE3-GP 2N7002A-7-GP
LPC_LFRAME# (20,70)
S
GPI91/AD1 LFRAME# LPC_LAD0 (39) THERM_SDA
99 126 LPC_LAD0 (20,70) R3756
(82) THERMTRIP_VGA# GPI92/AD2 LAD0 LPC_LAD1 KBC_ON_R# 2
(76) PSID_EC 100 127 LPC_LAD1 (20,70) 5 2 G 1 AC_IN# (45)
1
DISCRETE_ID GPI93/AD3 LAD1 LPC_LAD2
2 1R3705 108 128
+KBC_PWR DY 10KR2J-3-GP KBC_THERMTRIP# GPIO05 LAD2 LPC_LAD3
LPC_LAD2 (20,70)
KBC_SCL1 10KR2J-3-GP R3750
2
DY 1 96 LPC 1 LPC_LAD3 (20,70) 6 1 THERM_SCL (39)
2
(10,21,39,42,82) H_THERMTRIP# R3751 0R2J-2-GP GPIO04 LAD3
125 INT_SERIRQ (20) DY 0R2J-2-GP
3
SERIRQ C3720
0108-5 1 2 8 PM_CLKRUN# (20) 9/15
D
C3718 SCD1U10V2KX-5GP GPIO11/CLKRUN# DMN66D0LDW-7-GP +KBC_PWR SCD1U10V2KX-5GP AC_IN#_KBC
1229-1 122 SIO_RCIN# (21) 2 1
2
R3712 KBRST# D3703
101 121
(10) CPU_PROCHOT#_EC KB_DET_KBC GPI94 GA20 ECSCI#_KBC
SIO_A20GATE (21) DY 2 R3708 1 BAT54C-U-GP
1 2
2K2R2J-2-GP
105
GPI95 ECSCI#/GPIO54
29 1
(55) C3725 SCD1U10V2KX-5GP DY 2
Close to Q3703
(76) 8103_GPO
PCB_VER2
106
107
GPI96 D/A GPIO65/SMI#
9
123 ECSWI#_KBC
PANEL_BKEN
0R2J-2-GP
1205-1
GPI97 GPIO67/PWUREQ#
PD for Berry Keyboard Matrix
1216-2 1
R3714
2
10KR2J-3-GP
0113-1
PU for DJ Keyboard Matrix
64 68 KBC_SDA1
(21,41,42,49,52,89) PM_SLP_S3# GPIO01/TB2 GPIO74/SDA2
KBC_PWRBTN_EC# KBC_SCL1
95
AC_IN#_KBC
93
GPIO03 SMB GPIO73/SCL2
67
69
GPIO06 GPIO22/SDA1 BAT_SDA (44,45)
(69) LID_CLOSE#
PCB_VER0
94
119
GPIO07 GPIO17/SCL1
70 BAT_SCL (44,45) 1231-1 +KBC_PWR
KBC_BIOS_ID GPIO23
+KBC_PWR 2
R3715
DIS2K2R2J-2-GP
1 6
GPIO24 RN3704
(42,49) 1.5V_RUN_EN 109
PCB_VER1 GPIO30 KBC_SCL1 S5_ENABLE
120
65
GPIO31 SP GPIO66/G_PWM
81 1.8V_VGA_RUN_EN (52,90)
KBC_SDA1
8
7
1
2 R3723
1 2
10KR2J-3-GP
(66) PWRLED# GPIO32/D_PWM
PU for Discrete (66) PWR_BTN_LED#
PWR_BTN_LED# 66
GPIO33/H_PWM
BAT_SDA 6 3 KCOL0 1
DY 2
16 BAT_SCL 5 4 R3724 10KR2J-3-GP
Internal PL for UMA (66) AMBER_LED#_KBC
17
GPIO40/F_PWM
84 ECSMI#_KBC BLUETOOTH_EN 1 2
(68) KB_LED_BL_DET GPIO42/TCK GPIO77 SRN4K7J-10-GP R3726 10KR2J-3-GP
PM_SLP_S5#
(21) KBC_RSMRST# 20
GPIO43/TMS SPI GPIO76/SHBM
83 BLUETOOTH_EN (73)
D3701 IMVP_VR_ON
(21,49) PM_SLP_S5# 21
GPIO44/TDI GPIO GPIO75
82 WIFI_RF_EN (76) 1 2
SCD1U10V2KX-5GP
KBC_PLTRST_DELAY# 22 91 NB_VDDC_EN 1 TP3714 1 R3727 10KR2J-3-GP

GPIO45/E_PWM GPIO81 (21) SIO_EXT_WAKE#
23 AC_IN#_KBC 1 2
2
(46,50) 3V_5V_POK SYS_PWRGD GPIO46/TRST# ECSWI#_KBC R3749 100KR2J-1-GP

(39,41) EC_RESET_OUT 2 1 24 3
R3747 0R0402-PAD GPIO47 RN3702
C3717
(62) EC_SPI_WP#_R 25
EC_SHUTDOWN# GPIO50/TDO E51_TxD LCD_CBL_DET#
0105-4 26 111 E51_TxD (76) 2 2 3
1
GPIO51 GPO83/SOUT_CR/BADDR1 E51_RxD KB_DET#

(54) BLON_OUT 27 113 E51_RxD (76) 1 4
GPIO52/RDY# GPIO87/SIN_CR BAS16PT-GP
(47) IMVP_VR_ON 28 112 3.3V_RUN_VGA_EN (90)
GPIO53 GPO84/BADDR0 D3704 SRN100KJ-6-GP
(76) PSID_DISABLE# 73
GPIO70
(89) GFX_CORE_EN 74
GPIO71 GPIO16
114 PM_LAN_ENABLE (76) (21) SIO_EXT_SCI# 1 1231-1
0108-5 75 14
C (90) 1.0V_RUN_VGA_EN
(63) USB_PWR_EN# 110
GPIO72
GPO82/TRIS#
SER/IR
GPIO34
GPIO36
15
VDDC_PWRGD (41,48)
S5_ENABLE (42) 3 ECSCI#_KBC +3.3V_RUN
C
2
44 KBC_VCORF BAS16PT-GP E51_RxD 1 2

VCORF D3705 R3710 DY 10KR2J-3-GP
C3711
1
SC1U10V3KX-3GP
(21) SIO_EXT_SMI#
AGND
SIO_A20GATE 1 2
DY
GND
GND
GND
GND
GND
GND
3ECSMI#_KBC R3711 10KR2J-3-GP
2
SIO_RCIN# 1 2
NPCE781BA0DX-GP 2 R3713 DY 10KR2J-3-GP
116
89
78
45
18
5
2KBC_AGND 103
BAS16PT-GP
Internal PU
VDDC_PWRGD 1
10KR2J-3-GP
2 1119-1
R3753
KBC_AGND
9/11
1119-1 0R2J-2-GP EC_RESET_OUT 1 2
1 2 R3739 KBC_PLTRST_DELAY# R3752 100KR2J-1-GP
DY
0R2J-2-GP
(13,20,80) PLTRST#_NB_GPU
R3732
S0_LKG_DET 1 2
R3754 100KR2J-1-GP
1
PLTRST#_EC
11/10
PLTRST#_EC (20)
9/14 9/24
1
C3713
DY SC470P50V3JN-2GP
Remove reserved crystal.
2
+3.3V_RTC_LDO
KBC_PWRBTN#
R3716
1
DY 2
100KR2J-1-GP
U3701B 2 OF 2
KCOL[0..16] (68)
B (20) RTCCLK_KBC 77
32KX1/32KCLKIN KBSOUT0/JENK#
KBSOUT1/TCK
53
52
KCOL0
KCOL1
KCOL2
B
1
C3716
2
DY
SC10P50V2JN-4GP KBSOUT2/TMS
51
50 KCOL3
TP3713 GPIO02 KBSOUT3/TDI KCOL4
10/7 1 79
30
32KX2 KBSOUT4/JEN0#
49
48 KCOL5
(30) AMP_MUTE# GPIO55/CLKOUT KBSOUT5/TDO
47 KCOL6
KBSOUT6/RDY# KCOL7
(41,47,48,51) IMVP_PWRGD 63 43
GPIO14/TB1 KBSOUT7 KCOL8
+3.3V_RUN (21) PM_PWRBTN# 117
31
GPIO20/TA2 KBC KBSOUT8
42
41 KCOL9
(54) LCD_TST_EN GPIO56/TA1 KBSOUT9
(30) KBC_BEEP 32 40 KCOL10
GPIO15/A_PWM KBSOUT10 KCOL11
(66) WHITE_LED#_KBC 118 39
GPIO21/B_PWM KBSOUT11 KCOL12
(68) KB_BL_CTRL 62 38
GPIO13/C_PWM KBSOUT12/GPIO64 KCOL13
0208-2 KBSOUT13/GPIO63
37
1
2
10KR2J-3-GP
R3731
10KR2J-3-GP
36 KCOL14
KBSOUT14/GPIO62
R3730
R3729 35 KCOL15
10KR2J-3-GP
DY MB VERSION (68) KB_DET# 13
12
GPIO12/PSDAT3
KBSOUT15/GPIO61/XOR_OUT
GPIO60/KBSOUT16
34
33
KCOL16
KCOL17 1 TP3705
(54) LCD_CBL_DET# GPIO25/PSCLK3 GPIO57/KBSOUT17
THERMTRIP_VGA_GATE 11
ID VER2 VER1 VER0 (82) THERMTRIP_VGA_GATE KROW[0..7] (68)
2
GPIO27/PSDAT2
(54) LCD_TST 10
PCB_VER0 GPIO26/PSCLK2 KROW0
(68) TPDATA 71 54
PCB_VER1 X00 0 0 0 (68) TPCLK 72
GPIO35/PSDAT1
GPIO37/PSCLK1 PS/2
KBSIN0
KBSIN1
55 KROW1
PCB_VER2 56 KROW2
X01 0 0 1 KBSIN2
KBSIN3
57 KROW3
1
1
10KR2J-3-GP
R3735
10KR2J-3-GP
58 KROW4
R3733 X02 0 1 0 (62) EC_SPI_DI
EC_SPI_DI 86
F_SDI
KBSIN4
KBSIN5
59 KROW5
R3734
10KR2J-3-GP EC_SPI_DO 87 60 KROW6

DY DY A00 0 1 1 (62) EC_SPI_DO
EC_SPI_CS# F_SDO KBSIN6 KROW7
(62) EC_SPI_CS#
EC_SPI_CLK EC_SPI_CLK_C
90
F_CS0# FIU KBSIN7
61
0112-1 (62) EC_SPI_CLK 1 2 92
2
R3737 33R2J-2-GP F_SCK

ECRST#
2 1 AD_IA_KBC
1117-5 VCC_POR#
85
(45) AD_IA
2
R3757
0R0402-PAD C3724 NPCE781BA0DX-GP
SC10P50V2JN-4GP DY
1
KBC CLK
EMI PCLK_KBC
A E51_TxD
10/7 1118-2 0108-4
1217-1
U3703 +KBC_PWR
A
2
1 R3743
DYR3741 +PWR_SRC +3.3V_RUN GND
3 1 2 ECRST#
4K7R2J-2-GP VCC <Core Design>
2
PSID_EC RESET# 4K7R2J-2-GP
1117-5 DY
1
C3721
Wistron Corporation
2
1 2 G690L293T73UF-GP
DY
1
1
C3715
1231-1 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
SC10P50V2JN-4GP
2
C3719 C3714 Taipei Hsien 221, Taiwan, R.O.C.
1
SC56P50V2JN-2GP SC56P50V2JN-2GP ECRST#_C SC1U10V3KX-3GP

1 2 1
(39,42) PURE_HW_SHUTDOWN# DY
2
2
R3744 0R0402-PAD Title
C3722
3
1 2
DY 1 2
0108-5 Q3701 Size
KBC Nuvoton NPCE781BA0DX Rev
Document Number
C3723 SCD1U10V2KX-5GP PMBS3906-GP A2
SC56P50V2JN-2GP
5 4 3 2 1
5 4 3 2 1
D D
(Blanking)
C C
B B
<Core Design>
A
Title
Reserved
A4
5 4 3 2 1
5 4 3 2 1
+5V_RUN +3.3V_RUN +5V_RUN

SSID = Thermal 5V, 600mA
1
10KR2J-3-GP
1
R3916
R3901 R3915
C3901 C3902 10KR2J-3-GP
SC10U10V5KX-2GP SCD1U10V2KX-5GP
1
DY 2 DY
2
0R2J-2-GP
2
D3901
EMC2102_FAN_TACH_1 2 1 EMC2102_FAN_TACH (58)
D D
EMC2102_FAN_DRIVE CH751H-40PT-GP 9/25

EMC2102_FAN_DRIVE (58)
RN3901
3 2 +3.3V_RUN
4 1
SRN4K7J-8-GP
THERM_SCL (37)
THERM_SDA (37)
R3902
+3.3V_RUN 49D9R2F-GP 3.3V, 0.75mA
EMC2102_VDD_3D3
29
28
27
26
25
24
23
22
2 1
Pleace near to CPU side 1.For CPU Sensor
Layout notice :
U3901
VDD_5Va
FANa
FANb
VDD_5Vb
GND
TACH
SMCLK
SMDATA
2
Both H_THERMDA and THERMDC routing +3.3V_RUN
10 mil trace width and 10 mil spacing C3903
(10) H_THERMDC SCD1U10V2KX-5GP
1
1
1
C3910
SC470P50V3JN-2GP C3904 1 21
SC470P50V3JN-2GP VDD_3V NC#21
DY
2
(10) H_THERMDA 2 DN1 GND 20
ALERT# R3903 2 0R2J-2-GP

3 DP1 ALERT# 19 1
DY TALERT# (10,21)
C 4 EMC2102 18 CLK_32K C
(82) VGA_THERMDC DN2 CLK_IN
0107-5 C3905
0105-4 Remove GND = Internal Oscillator Selected
1
SC470P50V3JN-2GP 5 17
DP2 CLK_SEL +3.3V = External 32.768kHz Clock Selected
Removed EMC2102_DN3 EM2102_RESET# R3914 0R2J-2-GP
6 16 1
DY2 EC_RESET_OUT (37,41)
2
DN3 RESET#
(82) VGA_THERMDA
EMC2102_DP3 7 15
DP3 NC#15 +3.3V_RUN
VGA_THERMDC 2.VGA Sensor
THERMTRIP#
POWER_OK#
SYS_SHDN#
Layout notice :
FAN_MODE
SHDN_SEL
Both VGA_THERMDA and VGA_THERMDC routing
TRIP_SET
2
10 mil trace width and 10 mil spacing.
1
2
NC#8
Q3904 UMA 1 0107-3 RN3902
PMBS3904-1-GP GND = Channel 1 SRN10KJ-5-GP
3
VGA_THERMDA EMC2102-DZK-GP
OPEN = Channel 3
10
11
12
13
14
+3.3V = Disabled 0226-1
4
3
THERM_POW ER_OK#
R3905 THERMTRIP# R3906 0R2J-2-GP
1
DY2 H_THERMTRIP# (10,21,37,42,82)
2
EMC2102_SHDN
C3906 C3907
1
DY 2
10KR2J-3-GP +3.3V_RUN
THERM_SYS_SHDN#
Q3901
1 1119-1
DY SC470P50V3JN-2GP SC470P50V3JN-2GP
1
1
PMBS3904-1-GP
3
+3.3V_RUN R3908 +KBC_PW R +3.3V_RUN

R3907 10KR2J-3-GP
3.HW T8 sensor
Layout notice :
1
DY 2 EMC2102_FAN_mode
10KR2J-3-GP
2
Both DN3 and DP3 routing 10 mil THERMAL_P_HW _SHT
trace width and 10 mil spacing. R3909
1
B R3910 B
10KR2J-3-GP
1
0R0402-PAD Q3902 R3911
1 2 2N7002A-7-GP C3908 10KR2F-2-GP
1
SCD1U10V2KX-5GP
2
S D PURE_HW _SHUTDOW N# (37,42)
2
GND = Fan is OFF
OPEN = Fan is at 60% full-scale TRIP_SET Pin Voltage
V_DEGREE
+3.3V = Fan is at 75% full-scale V_DEGREE=(((Degree-75)/21)
T8 shutdown is 88 deg-C.
1
1
R3912
C3909 2K37R2F-GP
SCD1U10V2KX-5GP
2
32K suspend clock output
Q3903
2N7002A-7-GP
R3913
(20) RTC_CLK D S CLK_32K_R 1 2 CLK_32K
A <Core Design> A
10R2J-2-GP
1
DY C3911 Wistron Corporation

G
SC4D7P50V2CN-1GP 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

2

(42) RUN_ENABLE
Title
Size
Thermal/Fan
Document Number
Controllor EMC2102 Rev
A3 A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
5 4 3 2 1
5 4 3 2 1
SSID = Reset.Suspend
D +3.3V_RUN D
+1.8V_RUN +1.8V_RUN
1
+3.3V_RUN
100KR2J-1-GP
1
R4102
300R2J-4-GP
R4103
+3.3V_ALW DY U4101
1
10KR2J-3-GP
9/28
2
R4101
D4101 1 5
2
SB_PWRGD_D NC#1 VCC
D4103 1DY 2 2 A
(37,48) VDDC_PWRGD 1
U4102 CH751H-40PT-GP
3 GND DY Y 4 NB_PWRGD_IN (13)
2
3
1 5 SNAUC1G17DCKR-1GP
NC#1 VCC
(21,37,42,49,52,89) PM_SLP_S3# 2 2
3
A
GND
DY Y 4 SB_PWRGD (7,21)
BAT54APT-GP R4104
SNAUC1G17DCKR-1GP (21) NB_PWRGD 1 2
D4102
C
(37,39) EC_RESET_OUT 1 0R0402-PAD
C
3
SB_PWRGD_R 1 2
0105-4
(37,47,48,51) IMVP_PWRGD 2
R4106
BAT54APT-GP 0R0402-PAD
1 2 VDDC_PWRGD
C4101 SCD1U10V2KX-5GP
1 2 IMVP_PWRGD
1116-5
R4105
B
(37,48) VDDC_PWRGD 1
DY 2 EC_RESET_OUT (37,39)
B
0R2J-2-GP
<Core Design>
A
Title
Power On Logic
A4
5 4 3 2 1
5 4 3 2 1
SSID = Reset.Suspend H_THERMTRIP# (10,21,37,39,82)
E
R4201
H_PW RGD_R
(10,20) CPU_LDT_PW RGD 1
DY 2 B
DYQ4201
SCD1U10V2KX-5GP
C4216
1
1KR2J-1-GP CHT2222APT-GP
C
D
DY D
2
2
D4201 3 PURE_HW _SHUTDOW N# (37,39)
(46) 3V_5V_EN 1
1
BAS16PT-GP
R4203
200KR2J-L1-GP
C4217
SCD047U10V2KX-2GP DY 0226-1
2
1 2 S5_ENABLE (37)
2
R4202 1KR2J-1-GP
0222-2
Run Power +15V_ALW
+3.3V_RTC_LDO +5V_ALW +5V_RUN

2
100KR2J-1-GP U4201
R4204 8 D S 1
1 2RUN_ON_5V# R4205 7 D S 2
C 100KR2J-1-GP D S C
D G S
6
5 D G
3
4
1117-2
1
1
R4206 AO4468-GP C4202
Remove
6
1 2 5V_RUN_ENABLE SC10U10V5KX-2GP
2
U4207
DMN66D0LDW -7-GP 10KR2J-3-GP
1
C4201
1
SC6800P25V2KX-1GP
2
S G D
RUN_ENABLE
(21,37,41,49,52,89) PM_SLP_S3#
(39) RUN_ENABLE +3.3V_ALW +3.3V_RUN

U4202
8 D S 1
7 D S 2
6 D S 3
5 D G 4
1
R4207 AO4468-GP C4204
1 2 3.3V_RUN_ENABLE SC10U6D3V5KX-1GP
2
1
10KR2J-3-GP
C4203
B SCD01U50V2KX-1GP +1.5V_RUN B
2
1
R4226
10R3J-3-GP
DY
2
D
+3.3V_RTC_LDO
100KR2J-1-GP Q4207
R4211 2N7002A-7-GP
2RUN_ON_1.5V# RUN_ON_1.5V#
1
+15V_ALW
G
DY
D G S
S
6
+1.5V_SUS +1.5V_RUN
U4209
DMN66D0LDW -7-GP R4212
100KR2J-1-GP U4204
8 D S 1
1
7 D S 2
S G D 6 D S 3
SC10U6D3V5KX-1GP
5 D G 4
1
C4208
A AO4468-GP <Core Design> A

1.5V_RUN_ENABLE_R 1 2 1.5V_RUN_ENABLE
(37,49) 1.5V_RUN_EN
2
R4213
Wistron Corporation
1
0R0402-PAD
C4207 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
SCD01U50V2KX-1GP Taipei Hsien 221, Taiwan, R.O.C.
2
Title
Size
Power Plane Enable
Document Number Rev
A3
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
5 4 3 2 1
5 4 3 2 1
SSID = BATT CONN Batt Connecter

+VCHGR
10/7
1
PG4401
2 1 PC4402 PC4401
D (45) BATT_SENSE SCD1U50V3KX-GP SC2200P50V2KX-2GP BATT1 D
2
GAP-CLOSE-PWR-3-GP 10
1
PRN4401 2
4 1 PBAT_SMBCLK1 3
(37,45) BAT_SCL
3 2 PBAT_SMBDAT1 4
(37,45) BAT_SDA
1 2 100R2J-2-GP PBAT_PRES1# 5
(37) BAT_IN#
PR4401 SRN100J-3-GP PR4402 6
+KBC_PWR 2 1 1BAT_ALERT 7
SC47P50V2JN-3GP
SC47P50V2JN-3GP
AFTP4401 8
1
C4402
C4401
470KR2J-2-GP 9
11
DY DY
2
ALP-CON9-2-GP-U
0222-2 20.81316.009
C
For actual location, need to be swap all pin C
Close to Batt Connector
BAT_IN#
BAT_SDA
BAT_SCL
3
3
AFTP4402 1 PBAT_PRES1#
AFTP4403 1 PBAT_SMBDAT1 PD4402 PD4403 PD4401
B AFTP4404 1 PBAT_SMBCLK1 BAV99-4-GP BAV99-4-GP BAV99-4-GP B
AFTP4405 1 +VCHGR
1
2
+KBC_PWR
<Core Design>
A
Title
BATT CONN
A4
5 4 3 2 1
5 4 3 2 1
SSID = Charger modify +VCHGR

+SDC_IN +PWR_SRC
PU4502 PU4503 +VCHGR
PR4502
+DC_IN_SS 8 D S 1 AO4407A-GP
7 D S 2 1 2 1 S D 8
1
6 D S 3 D01R2512F-4-GP 2 S D 7
5 D G S D 6
PR4503
4 3
100KR2J-1-GP
1
+DC_IN_SS 4 G D 5
D PG4502 D
AO4407A-GP PG4503
2
Id=-12A GAP-CLOSE-PWR-3-GP
10KR2J-3-GP
GAP-CLOSE-PWR-3-GP
2
PR4513_03
PR4504
Qg=-25nC
1
Id=-12A
2
Rdson=10~38mohm PR4506
10KR2F-2-GP
+DC_IN_SS Qg=-25nC
PG4501
PG4506
PG4504
PG4505
470KR2J-2-GP
PR4505
PR4533_02
1
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
DY Rdson=10~38mohm
2 1
PQ4502_03
2
1
PR4507
PQ4502_05
0R2J-2-GP PR4524_03
PQ4501
1
316KR3F-2-GP
0R2J-2-GP
3 4
1
0R2J-2-GP
PR4508
PR4510
BQ24745_ACOK
PR4509
2 5
2
1 6 CHAGER_SRC
SCD1U50V3KX-GP
2
DMN66D0LDW-7-GP 1 2
PC4502
SC2200P50V2KX-2GP
SCD1U50V3KX-GP
PC4504
PR4511
SCD1U25V2ZY-1GP
2
2 1 CHAGER_SRC
SC1U6D3V2KX-GP
1
1
PC4503 CHG_AGND
EC4501
EC4502
0R0402-PAD
1117-7
1
PC4505
DY
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SCD1U50V3KX-GP
ICREF
1
SCD1U50V3KX-GP BQ24745_DCIN BQ24745_CSSP 1
PR4513
PC4506
PC4507
PC4508
PC4509
22 28 2
DY
33R3J-2-GP
2
1
DCIN CSSP
5
6
7
8
2
SI4800BDY-T1-GP
BQ24745_ACIN SCD1U50V3KX-GP
2
DY DY
PU4504
ACIN
D
D
D
D
48K7R3F-1-GP
BQ24745_REF 27 BQ24745_CSSN CHG_AGND

+KBC_PWR
2
BQ24745_LDO CSSN BQ24745_ICOUT
11 26
10KR2F-2-GP
2
VDDSMB ICOUT
10KR2F-2-GP
PD4501
Charger Current=1.4~3.6A
1
CHG_AGND
PR4516
1
1
SCD01U50V2KX-1GP
PC4501 PR4517
SCD1U10V2KX-4GP PR4512 25 BQ24745_BOOT_1
1 2BQ24745_BST1 K A 1 2 65MOS
modify +VCHGR
1
BOOT BQ24745_LDO PC4511
G
S
S
S
PC4510
PR4515
21
DY 2 1 BQ24745_ACOK VDDP 0R0603-PAD SD103AWS-1-GP SCD1U50V3KX-GP
2
4
3
2
1
0R0402-PAD 13
PR4514
ACOK
CHG_AGND 1124 Change P/N
2
ACAV_IN BQ24745_CHARGER_UGATE
2
24 PL4501
UGATE
1
2 1 BAT_SCL_1 10 1 2 PC4513 +VCHGR1 +VCHGR
(37,44) BAT_SCL SCL
PG4507 GAP-CLOSE-PWR-3-GP PC4512 SC3300P50V3KX-1GP
PR4518 DY PR4519
1
23 1 2 SCD1U50V3KX-GP BQ24745_LX1 1 2 1 2
15K8R3F-GP
2
2009/08/04 PHASE
0R0603-PAD D01R2512F-4-GP
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
2 1 BAT_SDA_1 9 BQ24745_PHASE_GND 1 2
DY DY
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SC10U25V6KX-1GP
C (37,44) BAT_SDA SDA IND-5D6UH-52-GP C
CHG_AGND PG4508 GAP-CLOSE-PWR-3-GP BQ24745_LGATE_1 PC4514
PR4520
1SMA18AT3G-GP
20
SCD1U50V3KX-GP
K
0114-1
2
LGATE SC220P50V2JN-3GP
PC4515
PC4516
PC4517
PC4518
PC4519
5
6
7
8
2
1
SI4800BDY-T1-GP
PG4510
PG4509
PD4502
PR4501 DY
PU4505
D
D
D
D
(37) AD_IA 2 1 14
NC#14 PGND
19
DY
SCD1U50V3KX-GP
0R2J-2-GP
2
18 BQ24745_CSOP_1
A
CHG_AGND CSOP
2
CSON
17 65MOS
BQ24745_VICM
G
S
S
S
8
PC4520
VICM
4K7R2J-2-GP
BQ24745_FBO BQ24745_PR4505
4
3
2
1
SC220P50V2JN-3GP
1
1
PR4522
200KR2F-L-GP
PR4521
0R2J-2-GP
8K45R2F-2-GP
SCD1U50V3KX-GP
PR4524
1 2 PR4523
2
CHG_AGND BQ24745_CSOP
PR4525
6 1 2
BQ24745_EAI FBO
PC4524
5 16
1BQ24745_FBO1
0R0402-PAD
2
EAI NC#16
2
PC4522 BQ24745_EAO 4
PR4526
1
BQ24745_REF EAO
2SC2200P50V2KX-2GP
PC4523
1 3
1
VREF
2 1PR4526_01
2 7K5R2F-1-GP
1 1 2 BQ24745_CE 7
1
PC4521 CE BQ24745_CSON
DY 12 15
GND
PC4525 PR4527 GND VFB PR4528

SC150P50V2JN-3GP 1 2
SCD1U50V3KX-GP
SCD1U10V2KX-4GP
0R0402-PAD BAT_SENSE 2
2
2
1 BATT_SENSE (44)
PC4531
DY PC4527 SC56P50V2JN-2GP DY 0R0402-PAD
2
PU4501
PC4526 DY
29
1
SCD01U50V2KX-1GP
BQ24745RHDR-GP
PC4530
DY
2
1
SCD1U50V3KX-GP
DY
1K8R6J-GP
PC4528 PR4529
2
SCD1U25V2ZY-1GP
1
PC4532
PR4530
2 1
PC4529 DY DY
SCD01U50V2KX-1GP 0R0402-PAD
SC1U6D3V2KX-GP
2
2
CHG_AGND
CHG_AGND
CHG_AGND CHG_AGND
This Resistor
must be 1%
tolerance.
(37) AC_IN#
2N7002A-7-GP
D
1
B PC4533 B
DY PQ4502
2
SCD1U25V2ZY-1GP
G ACAV_IN
S
A A
<Core Design>
Wistron Corporation
Title
CHARGER BQ24745
A2
5 4 3 2 1
A B C D E
+3.3V_ALW +3D3V_PWR
PG4601
2 1 SSID = PWR.Plane.Regulator_3p3v5v +3.3V_ALW_2
51125_VCLK 51125_VCLK
GAP-CLOSE-PWR
1
PG4602 PC4603 PC4604
SC1KP50V2KX-1GP
PC4602
2 1 PR4602 SCD1U25V3KX-GP SCD1U25V3KX-GP
+PWR_SRC_3D3V 100KR2J-1-GP
2
GAP-CLOSE-PWR +PWR_SRC
PG4603
PD3903_1
PD3904_1
2 1 PG4604
1 2 51125_ENTRIP
GAP-CLOSE-PWR
PG4606 GAP-CLOSE-PWR
2 1 PG4605
D
1 2 51125_ENTIP1
3
GAP-CLOSE-PWR PQ4601
1
PG4607 GAP-CLOSE-PWR 2N7002A-7-GP
2 1 PG4608 (42) 3V_5V_EN G PC4601 DY PR4601 PD4601 PD4602
4 1 2 SC18P50V2JN-1-GP 127KR2F-GP BAT54S-5-GP BAT54S-5-GP 4
4
GAP-CLOSE-PWR
PG4609 GAP-CLOSE-PWR PU4606
1
2 1 PG4610 DMN66D0LDW-7-GP +15V_ALW +5V_PWR
1 2 PG4612
GAP-CLOSE-PWR GAP-CLOSE-PWR-3-GP
PD3903_04
1
3
PG4611 GAP-CLOSE-PWR
1 2 1 2 PD3903_2
GAP-CLOSE-PWR 51125_ENTIP2
1225-2
1
PG4613 PC4606
1
1 2 SC1U25V3KX-1-GP PC4607
SC18P50V2JN-1-GP
1
PR4603 SCD1U25V3KX-GP
2
1
GAP-CLOSE-PWR DY 127KR2F-GP
PC4605
PG4614
1 2 PC4608
2
SCD1U25V3KX-GP
2
GAP-CLOSE-PWR TPS51125 RT8205B
PG4615 PR4622 DY ASM
1 2
GAP-CLOSE-PWR
+PWR_SRC_3D3V +PWR_SRC
PR4622 0.55mA +PWR_SRC_5V
51125_EN 1 2
PC4611 PC4612
1117-7 1117-7
SC10U25V6KX-1GP
SCD01U50V2KX-1GP
820KR3J-GP
1
PC4610 TPS51125 RT8205B DY
SCD1U25V2KX-GP
PR4604 0R3J 4R7 TPS51125 RT8205B +5V_PWR +5V_ALW

PC4609
SCD1U25V2KX-GP
SC10U25V6KX-1GP
PR4605 0R3J 4R7 PG4618
2
D D PC4613 PC4614
PC4615
1 2
2
8
7
6
5
5
6
7
8
1
+PWR_SRC +PWR_SRC_5V
D
D
D
D
SC10U25V6KX-1GP
SC10U25V6KX-1GP
D
D
D
D
Design Current =7.57A PU4602 PU4603 GAP-CLOSE-PWR
FDS8884-GP
16
FDS8884-GP PG4617
11.89A<OCP<14.053A
2
PU4601 PG4616 1 2
PC4616 Design Current = 7.3A 1 2
VIN
65MOS SCD1U25V3KX-GP 65MOS GAP-CLOSE-PWR
11.45A<OCP< 16A
G
S
S
S
PR4604 PR4605 SCD1U25V3KX-GP GAP-CLOSE-PWR PG4619
S
S
S
G
4D7R3F-L-GP 4D7R3F-L-GP PC4617 G S PG4620 1 2

1
2
3
4
4
3
2
1
51125_VBST2_1 1 251125_VBST2 51125_VBST1 1 51125_VBST1_1
0114-1 S G 2 1 9
BOOT2 BOOT1
22 2 1 2 0210-1 2 1
GAP-CLOSE-PWR
+3D3V_PWR PL4601 51125_DRVH2 10 21 51125_DRVH1 +5V_PWR GAP-CLOSE-PWR PG4621
UGATE2 UGATE1 PL4602
3 PG4622 1 2 3
2 1 51125_LL2 11 20 51125_LL1 1 2 2 1
COIL-3D3UH-15-GP PHASE2 PHASE1 IND-2D2UH-46-GP-U GAP-CLOSE-PWR
1118-2
1
GAP-CLOSE-PWR-3-GP
51125_DRVL2 51125_DRVL1
D 12 19 GAP-CLOSE-PWR PG4625
1
1
PTC4601 PTC4602 LGATE2 LGATE1
D PG4624 1 2
SCD1U10V2KX-5GP
8
7
6
5
5
6
7
8
GAP-CLOSE-PWR-3-GP
ST100U6D3VBM-5GP
ST220U6D3VDM-15GP
PC4618 PR4606
DY 1124 Change P/N 2 1
SCD1U10V2KX-4GP
D
D
D
D
D
D
D
D
2D2R5F-2-GP PU4604 51125_VO2 51125_VO1 PU4605 PR4607 GAP-CLOSE-PWR
PC4619
DY 7 24
2
VOUT2 VOUT1
1
1
FDS6690AS-GP
FDS6690AS-GP
PG4623 2D2R5F-2-GP PG4626 GAP-CLOSE-PWR PG4627
2
51125_FB2 5 2 51125_FB1 PTC4603 PG4628 1 2

DY
2
FB2 FB1 ST220U6D3VDM-15GP
1125-1 2 1
2
1
65MOS 65MOS GAP-CLOSE-PWR

2
2
1
G
S
S
S
PC4621 1 2 51125_EN 13 23 3V_5V_POK GAP-CLOSE-PWR PG4629
S
S
S
G
SC330P50V2KX-3GP PR4608 DY820KR2F-GP EN PGOOD

G S PC4620
DY S 1 2
2
1
2
3
4
4
3
2
1
51125_ENTIP2 6 51125_ENTIP1 SC560P50V-GP
G 1
2
51125_VREF ENTRIP2 ENTRIP1 GAP-CLOSE-PWR
0210-1 3 15 PG4630
REF PGND
1 2
1
SCD22U10V2KX-1GP
PC4622
51125_TONSEL 4 25
TONSEL GND GAP-CLOSE-PWR
1
PR4611
2
1
14 18 51125_VCLK 0R2J-2-GP
1
PR4610 SKIPSEL LG1_CP
51125_SKIPSEL DY
PR4609 DY 0R2J-2-GP PR4612
VREG3
VREG5
6K65R2F-GP 33KR2F-GP
1 2
51125_FB1_R
2
1 2
51125_FB2_R
2
PC4623 RT8205BGQW-GP PC4624 DY
3D3V_AUX_S5_5_51125 8
17
+KBC_PWR
DYSC18P50V2JN-1-GP +5V_ALW2 SC18P50V2JN-1-GP
2
+3.3V_ALW_2
PG4631
2
1
1 2
1
PR4616 PR4614 PR4615

PR4613 2 1 GAP-CLOSE-PWR-3-GP 100KR2J-1-GP 21K5R2F-GP
51125_VREF
10KR2F-2-GP 0R0402-PAD Close to VFB Pin (pin2)
PR4617
2
+3.3V_ALW_2 2
DY 1 1225-3 3V_5V_POK (37,50)
2
SC22U6D3V5MX-2GP
0R2J-2-GP
PC4625
PC4627
2 PR4618
1
51125_VREF DY
1
0R2J-2-GP PC4626
SC4D7U10V5KX-4GP
Close to VFB Pin (pin5) PR4619 +3.3V_ALW_2 +3.3V_RTC_LDO I/P cap: 10U 25V K1206 X5R/ 78.10622.52L
SC10U10V5KX-2GP
2 2 1 2
+3.3V_ALW_2 Inductor: 2.2uH PCMC063T-2R2MN Cyntec 18mohm/20mohm Isat =14Arms 68.2R210.20B
2
0R0402-PAD PR4620
1 2 O/P cap: 220U 6.3V PSLV0J227M(25) 25mOhm 2.236Arms NEC_TOKIN/77.C2271.00L
2 PR4621
1 O/P cap: 100U 6.3V TEPSLB20J107M(45)8R 45mOhm 1.374Arms NEC_TOKIN/77.C1071.081
DY 0R2J-2-GP 0R0402-PAD
H/S: FDS8884 23mohm/30mOhm@4.5Vgs/ 84.08884.037
I/P cap: 10U 25V K1206 X5R/ 78.10622.52L
0105-5 L/S: FDS6690AS 12mOhm/15mOhm@4.5Vgs/ 84.06690.E37
Inductor: 3.3UH PCMC063T-3R3MN Cyntec 28mohm/30mohm Isat =13.5Arms 68.3R310.20A
O/P cap: 220U 6.3V PSLV0J227M(25) 25mOhm 2.236Arms NEC_TOKIN/77.C2271.00L TPS51125 RT8205B
O/P cap: 100U 6.3V TEPSLB20J107M(45)8R 45mOhm 1.374Arms NEC_TOKIN/77.C1071.081 PR4616 DY ASM
PR4617 ASM DY
H/S: FDS8884 23mohm/30mOhm@4.5Vgs/ 84.08884.037
L/S: FDS6690AS 12mOhm/15mOhm@4.5Vgs/ 84.06690.E37
TPS51125:
SKIPSEL VREG3 or VREG5 VREF(2V) GND
TONSEL CH1 CH2
Operating OOA Auto Skip Auto Skip
GND 200kHz 265kHz Mode PWM only
VREF 245kHz 305kHz
VREG3 300kHz 375kHz
EN0 Open 820kΩ to GND GND
VREG5 365kHz 460kHz
Operating
Mode enable both enable both LDOs, disable all
LDOs, VCLK on VCLK off and circuit
and ready to ready to turn on
RT8205B(74.08208.A73): turn on switcher channels
switcher
TONSEL CH1 CH2 channels
GND 200kHz 250kHz
VREF 300kHz 375kHz
1 1
VREG3 365kHz 460kHz
VREG5 365kHz 460kHz
TPS51125 74.51125.073 <Core Design>
RT8208BGQW 74.08208.A73
Wistron Corporation
Title
Size Document Number

RT8205B_5V/3D3V Rev
A2
A B C D E
5 4 3 2 1
SSID = CPU.Regulator ISL6265HRTZ-T for +VCC_CORE&+VDDNB

PC4702
+5V_RUN
1 2 I/P cap: 10U 25V K1206 X5R/ 78.10622.52L
Inductor:4.7uH PCMC063T-4R7MN 35mohm Isat =10Arms CYNTEC/68.4R710.20D
PR4701 5V, 10mA SC33P50V2JN-3GP
O/P cap: 330U 2V EEFSX0D331ER 9mOhm 3.0Arms Panasonic/79.33719.L01
1 2
SC1U10V3KX-3GP
PR4702 PC4703 H/S:VISHAY SIS412DN-T1-GE3/ 24mohm/30mOhm@4.5Vgs/ 84.00412.037 +PWR_SRC
PC4701
2R3J-GP 1 2 6265_FB_NB_R 1 2
L/S:VISHAY SIS412DN-T1-GE3/ 24mohm/30mOhm@4.5Vgs/ 84.00412.037
1
44K2R2F-1-GP SC1200P50V2KX-1GP
SCD1U25V2ZY-1GP
SC10U25V6KX-1GP
2
PC4738
PC4705
1
1
PC4704
5
6
7
8
1 2
D
D
D
D
SIS412DN-T1-GE3-GP
PU4702
D GNDA_VCORE D
2
+PWR_SRC SC1KP50V2KX-1GP
PR4703 PR4704 +VDDNB +VDDNB
1 2 1 2 GNDA_VCORE
Design Current: 2.8A
SCD1U50V3KX-GP
65MOS
1
Peak current: 4A
PC4707
10R2J-2-GP
G
S
S
S
2R3J-GP 22KR2F-GP
1117-7
PR4705
4.4A<OCP<5.6A
4
3
2
1
0R0402-PAD
2
PR4706 UGATE_NB
2
1 2 +VDDNB
CPU_VDDNB_RUN_FB_H (10) PR4708
+3.3V_RUN +5V_RUN +3.3V_RUN PC4708 PL4702
GNDA_VCORE 1 PR4707 2 PHASE_NB BOOT_NB 1 2BOOT_NB_R 1 2 PHASE_NB 1 2
CPU_VDDNB_RUN_FB_H_R
SC1U10V2KX-1GP
SC4D7U6D3V5KX-3GP
SE330U2VDM-L-GP
PTC4701
8K06R2F-GP
9/15
PC4709
PC4710
0R0603-PAD SCD22U25V3KX-GP IND-4D7UH-88-GP
1 1125-1
1
PHASE_NB_R
LGATE_NB
1
0R2J-2-GP
PR4710
0R0402-PAD
5
6
7
8
PR4709 PHASE_NB DY PR4711
6265_COMP_NB
DY
6265_FSET_NB
2
D
D
D
D
SIS412DN-T1-GE3-GP
PU4703
2D2R5F-2-GP
6265_FB_NB
UGATE_NB
6265_VCC
2
6265_VIN
2
1
1
10KR2J-3-GP
10KR2J-3-GP
CPU_VDDNB_RUN_FB_L_R
PHASENB_RC
1 2 CPU_VDDNB_RUN_FB_L (10)
PR4713
PR4714
65MOS
G
S
S
S
PR4712
DY
1
1
0R2J-2-GP
10R2F-L-GP
0R0402-PAD
4
3
2
1
PR4715
PR4716
6265_OFS/VFIXEN
2
GNDA_VCORE
49
48
47
46
45
44
43
42
41
40
39
38
37
DY
1
PU4701 LGATE_NB
PC4711
FB_NB
COMP_NB
FSET_NB
VSEN_NB
RTN_NB
OCSET_NB
PGND_NB
LGATE_NB
PHASE_NB
UGATE_NB
GND
VIN
VCC
2
2
SC330P50V2KX-3GP
DY
2
GNDA_VCORE
0210-1
1 36 BOOT_NB
OFS/VFIXEN BOOT_NB BOOT0
(37,41,48,51) IMVP_PWRGD 2 35
PGOOD BOOT0 UGATE0 +PWR_SRC
(10) CPU_PWRGD_SVID_REG 3 34
CPU_SVD_R PWROK UGATE0 PHASE0
(10) CPU_SVD 1 PR4717 2 0R0402-PAD 4 33
CPU_SVC_R SVD PHASE0
(10) CPU_SVC 1 PR4718 2 0R0402-PAD 5 32 +5V_RUN
VCC_CORE_EN 6 SVC PGND0 LGATE0
(37) IMVP_VR_ON 1 PR4719 2 31
ENABLE LGATE0
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SCD1U25V2ZY-1GP
0R0402-PAD PR4720 1 1% 293K1R2F-L-GP 6265_RBIAS 7 ISL6265AHRTZ-T-GP 30
RBIAS PVCC
SC2D2U10V3KX-1GP
PC4713
PC4714
1 PR4721 2 6265_OCSET 8 29 LGATE1
OCSET LGATE1
PC4712
PC4715
PC4717
24KR2F-GP 6265_VDIFF0 D
C
1229-2 9 28 C
1
6265_FB0 VDIFF0 PGND1 PHASE1
10 27
FB0 PHASE1
5
6
7
8
5
6
7
8
6265_COMP0 11 26 UGATE1 PU4704 +VCC_CORE
COMP0 UGATE1
D
D
D
D
D
D
D
D
GNDA_VCORE 6265_VW0 12 25 BOOT1 PU4710
Design Current: 36A
2
VW0 BOOT1
SCD01U50V2KX-1GP
SIS406DN-T1-GE3-GP
SIS406DN-T1-GE3-GP
39.6A<OCP<54A
PC4718
COMP1
VDIFF1
VSEN0
VSEN1
1
RTN0
RTN1
PG4701
ISN0
ISN1
ISP0
VW1
ISP1
FB1
DY 1 2 65MOS 65MOS
S
S
S
S
S
S
G
G
2
GAP-CLOSE-PWR
13
14
15
16
17
18
19
20
21
22
23
24
4
3
2
1
4
3
2
1
PL4701 +VCC_CORE
GNDA_VCORE G S
6265_COMP1
6265_VDIFF1
6265_VW1
6265_VSEN0
6265_VSEN1
ISP0 ISN1 UGATE0

6265_RTN0
6265_RTN1
6265_FB1
ISN0 ISP1 PHASE0 1 2

+1.8V_RUN
SE330U2VDM-L-GP
SE330U2VDM-L-GP
SE330U2VDM-L-GP
GAP-CLOSE-PWR-3-GP
PTC4703
PTC4704
PTC4705
2D2R5F-2-GP
1
1
+VCC_CORE +VCC_CORE COIL-D36UH-3-GP
16KR2F-GP
PR4724 PC4719 D D
1
1
1KR2J-1-GP
PR4722
BOOT0 BOOT0_R
PG4702
DY
PR4725
1 2 1 2 0114-1 0907
5
6
7
8
5
6
7
8
PR4723
1
D
D
D
D
D
D
D
D
10R2J-2-GP
0R2J-2-GP
PR4727
1R3J-L1-GP SCD22U25V3KX-GPPU4708 PU4705
2
PR4726
SIS402DN-T1-GE3-GP
SIS402DN-T1-GE3-GP
1PHASE0_RC 2
2
2
65MOS 65MOS PR4728

2
S
S
S
S
S
S
G
G
0114-1 PR4729 1 2 0R0402-PAD
1
4K02R2F-GP
2
(10) CPU_VDD0_RUN_FB_H
4
3
2
1
4
3
2
1
(10) CPU_VDD0_RUN_FB_L
PR4730 1 2 0R0402-PAD G S G S PC4720
1 2
PR4733 1 2 0R0402-PAD PC4721
(10) CPU_VDD1_RUN_FB_L
CPU_VDD1_RUN_FB_H PR4734 1 2 0R0402-PAD SC330P50V2KX-3GP SCD1U16V3KX-3GP
(10) CPU_VDD1_RUN_FB_H DY
2
LGATE0 PR4731 PR4732
1
1
10R2J-2-GP
10R2J-2-GP
ISP0_R
0210-1 1
DY 2 1 2
DY
PR4735
PR4736
ISP0
Parallel 10R2F-L-GP NTC-10K-26-GP
ISN0
0114-1
2
DY
Close to CPU socket

B B
6265_FB0_C +PWR_SRC
PR4737 PC4723 PC4724 PC4725 PR4738 PC4726 PC4727 PC4722

6265_FB1_C 1
1
249R2F-GP
2 1 2 1 2 1 2 1
DY 2 DY 2 1 2
DY 1
DY 2 0210-3
SC4700P50V2KX-1GP SC180P50V2JN-1GP SC1KP50V2KX-1GP 249R2F-GP SC4700P50V2KX-1GP SC180P50V2JN-1GP SC1KP50V2KX-1GP
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SCD1U50V3KX-GP
SE100U25VM-14GP
SE100U25VM-14GP
PC4729
PC4730
PC4731
PC4734
PTC4706
PTC4710
PR4742
PR4739 PR4740 PR4741 D
5
6
7
8
5
6
7
8
1
1 2 1 2 1 2 1 2 PU4706
DY DY
D
D
D
D
D
D
D
D
SC1200P50V2KX-1GP
SC1200P50V2KX-1GP
PU4711
1
1
54K9R2F-L-GP
PC4728
54K9R2F-L-GP
PC4733
SIS406DN-T1-GE3-GP
1KR2F-3-GP 6K81R2F-1-GP 1KR2F-3-GP 6K81R2F-1-GP SIS406DN-T1-GE3-GP
2
1
1
PR4744
PR4743
DY DY 65MOS 65MOS
2
S
S
S
S
S
S
G
G
0114-1
2
6265_FB0_R 6265_FB1_R
4
3
2
1
4
3
2
1
PL4703 +VCC_CORE
G S
UGATE1
PHASE1 1 2
SE330U2VDM-L-GP
SE330U2VDM-L-GP
SE330U2VDM-L-GP
GAP-CLOSE-PWR-3-GP
PTC4709
PTC4707
PTC4708
D
PG4703
1
COIL-D36UH-3-GP
16KR2F-GP
PR4746 PC4735 D
5
6
7
8
5
6
7
8
1
PR4748
BOOT1 1 2 BOOT1_R 1 2
2D2R5F-2-GP
1
D
D
D
D
D
D
D
D
PU4709 PU4707 DY
0907
SIS402DN-T1-GE3-GP
SIS402DN-T1-GE3-GP
1R3J-L1-GP SCD22U25V3KX-GP DY DY
PR4747
2
2
2
65MOS 65MOS PR4749
1PHASE1_RC 2
S
S
S
S
S
S
G
G
1 2
4 4K02R2F-GP
3
2
1
4
3
2
1
G S PC4736
G S 1 2
SCD1U16V3KX-3GP
PR4750 PR4751
LGATE1 PC4737 1 2 ISP1_R 1 2
SC330P50V2KX-3GP DY DY
DY
2
10R2F-L-GP NTC-10K-26-GP
A A
0210-1 0114-1
ISN1
ISP1
I/P cap: 10U 25V K1206 X5R/ 78.10622.52L <Core Design>
Inductor: 0.36UH PCMC104T-R36MN1R05J CYNTEC DCR 1.05(+5%~-5%)mohm
Isat =60Arms 68.R3610.20C Wistron Corporation
O/P cap: 330U 2V EEFSX0D331ER 9mOhm 3.0Arms Panasonic/79.33719.L01 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
H/S:VISHAY SiR462DP/ POWERPAK-8.2/810mOhm/ 4.5Vgs/ 84.00462.037
Title
L/S:VISHAY SI7658ADP/ POWERPAK-2.3/ 2.8mOhm/ 4.5Vgs/ 84.07658.037 VREG : +VCC_CORE&+VDDNB
A2
5 4 3 2 1
5 4 3 2 1
SSID = PWR.Plane.Regulator_+1.1V_RUN
1117-2
D 0222-3
RT8209EGQW for +1.1V_RUN 0222-3 D
Remove PWM TYPE PRa PRb +PW R_SRC
+5V_ALW
*RT8209B 10 ohm 4.7 ohm
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SCD1U50V3KX-GP
SC10U25V6KX-1GP
PC4803
PC4810
PC4806
TPS51117 300 ohm 0 ohm
1
SC1U10V3KX-3GP
PC4812
1
1
PC4801
10R3J-3-GP
*DEFAULT
1
PR4801
2
PRa
2
5
6
7
8
5
6
7
8
SIR164DP-T1-GE3-GP
2
D
D
D
D
D
D
D
D
PU4802
PU4805
SI7686DP-T1-GP
2
PRb
SC1U10V3KX-3GP
PC4802
1
PR4806 PC4811
+5V_ALW +1.1V_LL1
1 2 1 2 65MOS DY 1119-2
G
S
S
S
G
S
S
S
2
4D7R3J-L1-GP SCD1U25V3KX-GP Design Current = 7.4A
4
3
2
1
4
3
2
1
A
RB551V30-GP
5V, 1.25mA 0114-1 11.65A<OCP < 15.89A

PD4801
PU4801
+1.1V_VOUT_V5FILT 4 13 +1.1V_DRVH
VDD UGATE +1.1V_DRVL PL4801 +1.1V_RUN
10 VDDP LGATE 9
K
+1.1V_VOUT_VFB 5 12 +1.1V_LL 1 2
FB PHASE
SC4D7U6D3V5KX-3GP
SCD1U10V2KX-4GP
SE330U2D5VM-GP
+1.1V_VOUT_BST 14 COIL-1D5UH-25-GP
BOOT
1
2D2R5F-2-GP SC330P50V2KX-3GP
GAP-CLOSE-PWR-3-GP
PC4804
PC4807
PTC4801
+1.1V_VOUT
3 0308-1
ST330U2VDM-3GP
ST330U2VDM-3GP
VOUT
1
PR4802
6 VDDC_PW RGD
PGOOD VDDC_PW RGD (37,41)
PR4808 1 20R0402-PAD +VDDC_EN 1 7 DY
(37,41,47,51) IMVP_PW RGD EN/DEM GND
5
6
7
8
5
6
7
8
1
PG4817
C PR4804 1 2 300KR2F-GP +1.1V_VOUT_TON C
PTC4802
PTC4803
2 8
2
TON PGND
D
D
D
D
D
D
D
D
SC4700P50V2KX-1GP
SIR164DP-T1-GE3-GP
PU4804
SIR164DP-T1-GE3-GP
PU4803
+1.1V_VOUT_TRIP 11 15
2
CS NC#15
PC4808
1
PC4809
RT8209EGQW -GP
PR4803
9K31R2F-GP
2
1
DY
DY 65MOS
2
G
S
S
S
G
S
S
S
DY
2
+1.1V_VOUT
2
4
3
2
1
4
3
2
1
SC18P50V2JN-1-GP
1
18KR2F-GP
1
PR4805
PC4805
R1 DY
0210-1
2
2
+1.1V_VOUT_VFB
1
Close to VFB Pin (pin5) PR4807
38K3R2F-GP
R2
Vout=0.75V*(R1+R2)/R2
2
I/P cap: 10U 25V K1206 X5R/ 78.10622.52L
Inductor: 1.5UH PCMC104T-1R5MN 33Arms CYNTEC/ 68.1R510.10J
O/P cap: 330U 2.5V EEFCX0E331QR 15mOhm 2.7Arms PANASONIC/ 79.3371V.20L
B H/S: SI7686DP/ POWERPAK-8/11mOhm/14mOhm@4.5Vgs/ 84.07686.037 B
L/S: SiR164DP/ POWERPAK-8/ 2.6mOhm/3.2mohm@4.5Vgs/ 84.00164.037
A <Core Design> A
Wistron Corporation
Title
RT8209E_+1.1V_RUN
A3
5 4 3 2 1
5 4 3 2 1
SSID = PWR.Plane.Regulator_1p5v0p75v +5V_ALW
PR4901
1
5D1R3J-GP
+5V_ALW
1125-1
12KR2F-L-GP
2
1 2 51116_VDD
PR4902 5V, 0.8mA
SC1U10V3KX-3GP
1
+5V_ALW
PC4903
1 2
SC1U10V3KX-3GP
D 1125-1 D
1
PC4902 PC4901
1
SC1KP50V2KX-1GP PR4903 1 2 2D2R2J-GP 0D75V_EN
(21,37,41,42,52,89) PM_SLP_S3#
2
+3.3V_RUN DY PD4901 PR4907 1 2 0R2J-2-GP
CH551H-30PT-GP (21,37) PM_SLP_S5# DY
PR4904 1 2 0R2J-2-GP
11/9 DY
2
(37,42) 1.5V_RUN_EN
1120-7
SCD1U10V2KX-4GP
2
PC4923
16
14
15
1
PR4916 PU4901 PR4908
100KR2J-1-GP 0R0603-PAD
VDD
CS
VDDP
1
Refer to DJ1 PR8606
2
TPS51116_VBST1 2 TPS51116_VBST PC4904
0622 22 1
1
BOOT SCD1U10V2KX-4GP
(51,52,89,90) RUNPW ROK 13 1116-6
2
PGOOD
1PR4906 2
1118-3 12 21 TPS51116_UGT
+5116_PW R_SRC TON UGATE
620KR2F-GP
(21,37) PM_SLP_S5# 11 S5
0D75V_EN 10 20 TPS51116_PHS
S3 PHASE
TI: Non_ASM 23
RT: ASM +1.5V_SUS VLDOIN +PW R_SRC +5116_PW R_SRC
1
19 TPS51116_LGT PG4903
PC4905 LGATE
7 NC#7 2 1
+5V_ALW SC1U10V3KX-3GP
2
PR49091 2 1M1R2J-GP GAP-CLOSE-PW R
DY 1 18 PG4905
+1.5V_SUS VTTGND PGND
NC#17 17 2 1
C PR4910 1 2 0R0402-PAD 4 C
MODE TPS51116_VDDQSNS GAP-CLOSE-PW R
VDDQ 8
2
PG4907
PC4906 51116_VDDQSET
SC1KP50V2KX-1GP DY 24 VTT FB 9 2 1
1
+0D75V_DDR_P 2 +5V_ALW PR4911 GAP-CLOSE-PW R

VTTSNS
VTTREF
6 1 2 PG4909
DEM DY +5116_PW R_SRC 2 1
GND
GND
0R2J-2-GP
1
GAP-CLOSE-PW R
25 RT8207GQW -GP DY PC4907 PG4911
5
SC1U10V3KX-3GP 2 1
2
+V_DDR_REF GAP-CLOSE-PW R
PC4912
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SCD1U50V3KX-GP
SC4D7U25V5KX-GP
PC4909
PC4922
PC4911
2
1
1 PR4912 2 9/18
0R0603-PAD
1119-7
5
6
7
8
Design Current = 18.45A
2
D
D
D
D
SC2D2U6D3V3KX-GP
Design Current = 0.7A PU4902

28.99A<OCP< 34.3A
SI7686DP-T1-GP
1
PC4908
+0D75V_DDR_P
65MOS
2
G
S
S
S
4
3
2
1
+0D75V_DDR_P +0.75V_DDR_VTT +1.5V_SUS
PC4913
PC4914
PC4915
PC4916
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SCD1U10V2KX-4GP
PG4901 TPS51116_UGT PL4901

1
1 2
B TPS51116_VBST 1 TPS51116_PHS B
2 1 2
GAP-CLOSE-PW R COIL-1D5UH-25-GP
2
PG4917 PC4917
0114-1
SC4D7U6D3V5KX-3GP
5
6
7
8
1
1 2 SCD1U25V3KX-GP
SE220U2VDM-8GP
SE220U2VDM-8GP
SCD1U10V2KX-4GP
D
D
D
D
PU4903 PR4913
PC4918
PC4919
2
1
GAP-CLOSE-PW R 3D9R5J-GP
PTC4902
PTC4901
SIR164DP-T1-GE3-GP
GAP-CLOSE-PWR-3-GP
PG4918
0225-3
2
65MOS
1
G
S
S
S
TPS51116_PHS_SET
4
3
2
1
1
State S3 S5 VDDR VTTREF VTT
TPS51116_LGT PC4920
S0 Hi Hi On On On SC680P50V3JN-GP
2
S3 Lo Hi On On Off(Hi-Z)
1125-1
TPS51116_VDDQSNS
1
S4/S5 Lo Lo Off Off Off
1
PR4914 DY PC4921
30KR2F-GP SC18P50V2JN-1-GP
2
2
51116_VDDQSET
1
VDDQSET VDDQ (V) VTTREF and VTT NOTE Close to VFB Pin (pin5)
I/P cap: 10U 25V K1206 X5R/ 78.10622.52L PR4915
GND 2.5 VVDDQSNS/2 DDR 30KR2F-GP
Inductor: 1.5UHPCMC104T-1R5MN DCR:3.8/4.2mohm Isat =33Arms Cyntec/ 68.1R510.10J
A <Core Design> A
2
O/P cap: 220U 2V EEFCX0D221R 15mOhm 2.7Arms PANASONIC/ 79.22719.20L
V5IN 1.8 VVDDQSNS/2 DDR2 H/S: SI7686DP/ POWERPAK-8/11mOhm/14mOhm@4.5Vgs/ 84.07686.037
L/S: SiR164DP/ POWERPAK-8/ 2.6mOhm/3.2mohm@4.5Vgs/ 84.00164.037 Wistron Corporation
FB Resistors Adjustable VVDDQSNS/2 1.5 V < VVDDQ < 3 V 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Title
RT8207_+1.5V_SUS
A3
5 4 3 2 1
5 4 3 2 1
SSID = PWR.Plane.Regulator_+1.1V_ALW
1117-2
D
RT9025 for +1.1V_ALW D
+5V_ALW
SC1U10V3KX-3GP
PC5006
1
2
+3.3V_ALW
0106-1
SC10U6D3V5MX-3GP
PC5005
1
1
PR5004
10KR2J-3-GP
9
+1.1V_ALW _P +1.1V_ALW
GND
2
1.2mA 4 5 PG5002
VDD NC#5
3 VIN VOUT 6 1 2
SCD01U16V2KX-3GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
(37,46) 3V_5V_POK 1 DY 2 +1.1V_VOUT_EN 2 7 +1.1V_ALW _ADJ
EN ADJ
SC4700P50V2KX-1GP
PC5001
PC5002
PC5003
PR5002 1 8 GAP-CLOSE-PW R
PGOOD GND
1
PC5004
2K2R2J-2-GP PR5001 DY PG5001

1
1K02R2F-1-GP
DY 1 2
DY
2
C PU5001 GAP-CLOSE-PW R C
2
RT9025-25PSP-GP
2
TP5001
11.1V_RUN_PW RGD Vo=0.8*(1+(R1/R2))
Vout=0.8V*(R1+R2)/R2
1
PR5003
2K7R2F-GP
B B
A <Core Design> A
Wistron Corporation
Title
RT9025_+1.1V_ALW
A3
5 4 3 2 1
5 4 3 2 1
SSID = PWR.Plane.Regulator_VDDR
D D
RT9025 for +VDDR

11/6
+5V_ALW
5V, 1.2mA
PC5101
SC1U10V3KX-3GP
+1.5V_SUS
1
2
PC5106
SC10U6D3V5MX-3GP
1
2
C C
9
+VDDR_P +CPU_VDDR
GND
4 5 PG5101
VDD NC#5
3 VIN VOUT 6 1 2
PC5105
SCD01U16V2KX-3GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
(49,52,89,90) RUNPW ROK 1 2 VDDR_EN 2 7 +VDDR_ADJ
SC4700P50V2KX-1GP EN ADJ
PC5107
PC5103
PR5101 1 PGOOD GND 8 GAP-CLOSE-PW R +1.5V_RUN +/- 5%
1
PC5104
2K2R2J-2-GP 1 DY PG5102 Design Current: 0.805A
Vo=0.8*(1+(R1/R2)) PR5102
DY 1 2 Peak current 1.15A
DY R1
2
PU5101 1K05R2F-GP GAP-CLOSE-PW R
2
RT9025-25PSP-GP
2
1
1119-1 (37,41,47,48) IMVP_PW RGD
PR5107
5K62R2F-GP
1116-2 +3.3V_RUN Vout=0.8V*(R1+R2)/R2
1
PR5108
2
PR5106
1
DY 2 R2
1
0R2J-2-GP 8K2R2F-1-GP
PR5105
D
PD5101 10KR2F-2-GP
2
VDDR_SEL
(20,24) VDDR_SEL 1
PR5103
PQ5101
2N7002A-7-GP
1225-6
2
3 VDDR_SEL_R 2 1 VDDR_SEL_CNTL G
2
MEM_1V5 2 10KR2F-2-GP
100KR2J-1-GP
(22) MEM_1V5
1
B B
PC5102
PR5104
DY 0105-6
SCD047U16V2KX-1-GP
S
BAT54APT-GP DY
2
VDDR_SEL +CPU_VDDR
H 1.05V
L 0.9V
10/2
<Core Design>
A A
Wistron Corporation
Title
RT9025 +VDDR
A3
5 4 3 2 1
5 4 3 2 1
SSID = PWR.Plane.Regulator_1p8v
APL5930 for +1.8V_RUN
+3.3V_ALW +1.8V_RUN_VIN
D D
PG5201
2 1 +5V_ALW +1.8V_RUN_VIN
5V, 1.5mA
GAP-CLOSE-PW R
SC1U10V3KX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
PG5202
1
PC5201
PC5202
PC5203
2 1
GAP-CLOSE-PW R DY +1.8V_RUN_P +1.8V_RUN
2
PG5203
Design Current =0.92A 1 2
6
PU5201
GAP-CLOSE-PW R
VCNTL
(49,51,89,90) RUNPW ROK 7 5 PG5204
POK VIN#5 +1.8V_RUN_P
VIN#9 9 1 2
PR5201
(21,37,41,42,49,89) PM_SLP_S3# 1 21D8V_RUN_EN 8 EN VOUT#3 3 GAP-CLOSE-PW R
SC22U6D3V5MX-2GP
VOUT#4 4
SC68P50V2JN-1GP
PC5204
PC5205
SC22U6D3V5MX-2GP
2K2R2J-2-GP
1
16K5R2F-2-GP
PR5203
PC5206
DY
1
DY 2 2
GND
(37,90) 1.8V_VGA_RUN_EN FB
2
PR5202
5912_1.8V_RUN_FB
APL5930KAI-TRG-GP
2
0R2J-2-GP SO-8-P R1
C C
SC4700P50V2KX-1GP
1
PC5207
DY
2
Vout=0.8V*(R1+R2)/R2
1
PR5204
13K3R2F-L1-GP
R2
2
B B
A <Core Design> A
Wistron Corporation
Title
APL5930_+1.8V_RUN
A3
5 4 3 2 1
5 4 3 2 1
SSID = PWR.Plane.Regulator_0P9v
D D
C C
B B
RT9013-25PB for +2.5V_RUN

+3.3V_RUN PU5301 +2.5V_RUN
1 VIN VOUT 5
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC10U10V5ZY-1GP
2 GND
+2.5V_RUN +/- 5%
PC5301
PC5303
1 2 2D5V_RUN_EN 3 4 Design Current: 175mA
EN NC#4
1
1
PC5302
PC5304
SC1U10V3KX-3GP
Peak current 250mA

1
PR5301
0R0402-PAD RT9013-25PB-GP
DY
2
2
11/6
2
CHECK CURRENT IS ENOUGH OR NOT (CPU)
A <Core Design> A
Wistron Corporation
Title
VREG : +CPU_VDDR&+2.5V_RUN
A3
5 4 3 2 1
+3.3V_RUN
9/22
SSID = VIDEO SSID = Inverter
1
R5401 +3.3V_RUN
DY 10KR2J-3-GP
100R2J-2-GP INVERTER POWER
2
1
R5402 1 2 LBKLT_CTL (55)
LVDS CONNECTOR LCD_BRIGHTNESS RN5402

SRN2K2J-1-GP
0208-2
2
10/1
3
4
GFX_PW R_SRC +LCDVDD
LCD1
DY R5405 LVDS_CLK
SC1U10V3KX-3GP
SCD1U16V2ZY-2GP
48 100KR2J-1-GP LVDS_DATA
C5401
C5402
1
1
1
41 50
1
2
2 DIS +PW R_SRC
3 3.3V_LCD_RUN 1 2 +3.3V_RUN_VGA Change Poly-fuse
R5404 0R2J-2-GP
4
5
0105-7 1 2 GFX_PW R_SRC
+3.3V_RUN
42 6 R5407 UMA 0R2J-2-GP
F5401
7 3.3V_LCD_RUN
8 LCD_BRIGHTNESS 2 1
9 BLON_OUT_C
2
10 LCD_CBL_DET#_C
11 LCD_TST_C C5406 C5407 POLYSW -1D1A24V-1-GP
2
SC1KP50V2KX-1GP SCD1U50V3KX-GP
12 LVDSB_TX2 (55) 10/1
1
43 13 LVDSB_TX2# (55) R5408
14 LCD_DET_G 100KR2J-1-GP Main:69.50007.A41
15 LVDSB_TX1 (55) RN5401
16 BLON_OUT_C 1 8
Second:69.50007.A31
LVDSB_TX1# (55) BLON_OUT (37)
1
LCD_CBL_DET#_C
17
18
1120-1 LCD_TST_C
2
3
7
6
LCD_CBL_DET# (37)
LVDSB_TX0 (55) LCD_TST (37)
19 LVDSB_TX0# (55) LCD_DET_G 4 5
44 20
21 LVDSB_TXC (55) SRN100J-4-GP
22 LVDSB_TXC# (55)
23
24 LVDSA_TXC (55)
25 LVDSA_TXC# (55)
26
45 27 LVDSA_TX2 (55)
28 LVDSA_TX2# (55)
29
30 LVDSA_TX1 (55)
31 LVDSA_TX1# (55)
32
33
0222-1
LVDSA_TX0 (55)
46 34 LVDSA_TX0# (55) R5409
35 LVDS_DATA (55)
36 LVDS_CLK (55) 1 2 USB_PN11 (21)
37
38 USB_CAMERA# 0R0603-PAD
39 USB_CAMERA
47
40
51
+3.3V_CAMERA
1
R5411
2 USB_PP11 (21)
SSID = VIDEO
49 0R0603-PAD
IPEX-CONN40-2R-GP-U
LCD POWER
20.F1093.040
Close to LVDS connector
(55) LCDVDD_EN +LCDVDD +3.3V_RUN
LVDSB_TXC#
U5401
LVDSB_TXC
1231-1
1
Camera Power LVDSA_TXC#
R5412 3 OUT IN#4 4
1231-1 LCD_BRIGHTNESS D5401 3 ENVDD_D 1 2 ENVDD
2
1
GND
5
+3.3V_RUN +3.3V_CAMERA LVDSA_TXC EN IN#5
SC1U10V3KX-3GP
R5414
SCD1U10V2KX-5GP
LCD_TST BAT54C-U-GP 0R0402-PAD
1
C5409
EC5406 EC5407 EC5408 EC5409 G5285T11U-GP
C5405
1 2
49K9R2F-L-GP
SC33P50V2JN-3GP
SC33P50V2JN-3GP
1
R5413
EC5401
DY DY DY DY
SC5D6P50V2CN-1GP
SC5D6P50V2CN-1GP
SC5D6P50V2CN-1GP
SC5D6P50V2CN-1GP
0R0603-PAD EC5402
2
2
1
DY DY (37) LCD_TST_EN DY
2
EC5405 C5403
2
2
SCD1U10V2KX-5GP SC10U6D3V5MX-3GP
DY
2
For EMI request
<Core Design>
Wistron Corporation
Title
LCD/Inverter Connector
A3
5 4 3 2 1
SSID = VIDEO 9/18

RN5501 RN5507
(13) VGA_TXAOUT2- 5 4 LVDSA_TX2# (54) (13) VGA_TXBOUT1- 5 4 LVDSB_TX1# (54)
(13) VGA_TXAOUT2+ 6 3 LVDSA_TX2 (54) (13) VGA_TXBOUT1+ 6 3 LVDSB_TX1 (54)
(13) VGA_TXACLK- 7 2 LVDSA_TXC# (54) (13) VGA_TXBOUT2- 7 2 LVDSB_TX2# (54)
D 8 1 8 1 D
(13) VGA_TXACLK+ LVDSA_TXC (54) (13) VGA_TXBOUT2+ LVDSB_TX2 (54)
UMA SRN0J-7-GP UMA SRN0J-7-GP
RN5503 RN5508
(82) GPU_LVDSA_TX2# 4 5 (82) GPU_LVDSB_TX1# 4 5
(82) GPU_LVDSA_TX2 3 6 (82) GPU_LVDSB_TX1 3 6
(82) GPU_LVDSA_TXC# 2 7 (82) GPU_LVDSB_TX2# 2 7
(82) GPU_LVDSA_TXC 1 8 (82) GPU_LVDSB_TX2 1 8
DIS SRN0J-7-GP DIS SRN0J-7-GP
RN5505 RN5509
(13) VGA_TXAOUT0- 5 4 LVDSA_TX0# (54) (13) VGA_TXBCLK- 5 4 LVDSB_TXC# (54)
(13) VGA_TXAOUT0+ 6 3 LVDSA_TX0 (54) (13) VGA_TXBCLK+ 6 3 LVDSB_TXC (54)
(13) VGA_TXAOUT1- 7 2 LVDSA_TX1# (54) (13) VGA_TXBOUT0- 7 2 LVDSB_TX0# (54)
(13) VGA_TXAOUT1+ 8 1 LVDSA_TX1 (54) (13) VGA_TXBOUT0+ 8 1 LVDSB_TX0 (54)
C
UMA SRN0J-7-GP UMA SRN0J-7-GP C
RN5506 RN5510
(82) GPU_LVDSA_TX0# 4 5 (82) GPU_LVDSB_TXC# 4 5
(82) GPU_LVDSA_TX0 3 6 (82) GPU_LVDSB_TXC 3 6
(82) GPU_LVDSA_TX1# 2 7 (82) GPU_LVDSB_TX0# 2 7
(82) GPU_LVDSA_TX1 1 8 (82) GPU_LVDSB_TX0 1 8
DIS SRN0J-7-GP DIS SRN0J-7-GP
10/1
10/1
B RN5502 RN5512 B
5 4 (13) LDDC_CLK 1 4 LVDS_CLK (54)
(13) NB_LCDPWR_EN 6 3 LCDVDD_EN (54) (13) LDDC_DATA 2 3 LVDS_DATA (54)
(13) NB_BL_PWM 7 2 LBKLT_CTL (54)
8 1 PANEL_BKEN (37) UMA SRN0J-6-GP
(13) NB_BL_EN
UMA
SRN0J-7-GP
RN5504 RN5511
8 1 (82) GPU_LVDS_CLK 2 3
(82) VGA_LCDVDD_EN 7 2 (82) GPU_LVDS_DATA 1 4
(82) VGA_LBKLT_CTL 6 3
(82) VGA_BLEN 5 4 DIS SRN0J-6-GP
DIS
SRN0J-7-GP
<Core Design>
A
Title
LVDS_Switch
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
5 4 3 2 1
5 4 3 2 1
SSID = VIDEO HDMI CONNECTOR HDMI CONN

10/1
(12) PCIE_NTX_GRX_P[12..15] PCIE_N_H_TX_GRX_P[12..15] (80)
HDMI1 22.10296.211
(12) PCIE_NTX_GRX_N[12..15] PCIE_N_H_TX_GRX_N[12..15] (80) 22
20
1 HDMI_CN_DATA2 1 AFTP5703
HDMI DISCRETE/ UMA Co-lay 10/1 2

D 3 HDMI_CN_DATA2#1 AFTP5705 D
RN5708 RN5707 4 HDMI_CN_DATA1 1 AFTP5704
PCIE_NTX_GRX_N13 5 4 NB_HDMI_TX0N NB_HDMI_TXCN 5 4 HDMI_CN_CLK# 5
PCIE_NTX_GRX_P13 6 3 NB_HDMI_TX0P NB_HDMI_TXCP 6 3 HDMI_CN_CLK 6 HDMI_CN_DATA1#1 AFTP5701
PCIE_NTX_GRX_N12 7 UMA 2 NB_HDMI_TXCN NB_HDMI_TX0N 7 UMA 2 HDMI_CN_DATA0# 7 HDMI_CN_DATA0 1 AFTP5702
PCIE_NTX_GRX_P12 8 1 NB_HDMI_TXCP NB_HDMI_TX0P 8 1 HDMI_CN_DATA0 8
9 HDMI_CN_DATA0#1 AFTP5711
SRN0J-7-GP SRN0J-7-GP 10 HDMI_CN_CLK 1 AFTP5710
RN5710 RN5709 11
PCIE_NTX_GRX_N15 5 4 NB_HDMI_TX2N NB_HDMI_TX1N 5 4 HDMI_CN_DATA1# 12 HDMI_CN_CLK# 1 AFTP5708
PCIE_NTX_GRX_P15 6 3 NB_HDMI_TX2P NB_HDMI_TX1P 6 3 HDMI_CN_DATA1 13
PCIE_NTX_GRX_N14 7 UMA 2 NB_HDMI_TX1N NB_HDMI_TX2N 7 UMA 2 HDMI_CN_DATA2# 14
PCIE_NTX_GRX_P14 8 1 NB_HDMI_TX1P NB_HDMI_TX2P 8 1 HDMI_CN_DATA2 15 DDC_CLK_HDMI 1 AFTP5707 +5V_RUN
16 DDC_DATA_HDMI 1 AFTP5706
SRN0J-7-GP SRN0J-7-GP
11/12-3 17
SCD1U10V2KX-5GP
RN5706 18 1 AFTP5712
C5701
PCIE_NTX_GRX_P12 5 4 PCIE_N_H_TX_GRX_P12 (82) HDMI_PCH_DATA0# C5703 DIS
1 2 HDMI_CN_DATA0# 19 HPD_HDMI_CON 1 AFTP5713
1
PCIE_NTX_GRX_N12 6 3 PCIE_N_H_TX_GRX_N12 (82) HDMI_PCH_DATA0 C5704 DIS
1 SCD1U10V2KX-5GP
2 HDMI_CN_DATA0 21
PCIE_NTX_GRX_P13 7 DIS 2 PCIE_N_H_TX_GRX_P13 (82) HDMI_PCH_CLK# C5709 DIS
1 SCD1U10V2KX-5GP
2 HDMI_CN_CLK# 23 1 AFTP5709
PCIE_NTX_GRX_N13 8 1 PCIE_N_H_TX_GRX_N13 (82) HDMI_PCH_CLK C5702 DIS
1 SCD1U10V2KX-5GP
2 HDMI_CN_CLK
2
SCD1U10V2KX-5GP SKT-HDMI19P-69-GP
SRN0J-7-GP
RN5712
PCIE_NTX_GRX_P14 5 4 PCIE_N_H_TX_GRX_P14 (82) HDMI_PCH_DATA2# C5707 DIS
1 2 HDMI_CN_DATA2#
1 SCD1U10V2KX-5GP
2 HDMI_CN_DATA2
PCIE_NTX_GRX_P15 7 DIS 2 PCIE_N_H_TX_GRX_P15 (82) HDMI_PCH_DATA1# C5705 DIS
1 SCD1U10V2KX-5GP
2 HDMI_CN_DATA1#
1 SCD1U10V2KX-5GP
2 HDMI_CN_DATA1
SCD1U10V2KX-5GP
SRN0J-7-GP
C
9/23 C
HDMI_CN_CLK#
HDMI_CN_CLK
HDMI_CN_DATA0#
HDMI_CN_DATA0
9/15
+5V_RUN
HDMI_CN_DATA1#
HDMI_CN_DATA1
10/5 HDMI_CN_DATA2#
3
4
HDMI_CN_DATA2
RN5701
SRN4K7J-8-GP
499R2F-2-GP
499R2F-2-GP
499R2F-2-GP
499R2F-2-GP
499R2F-2-GP
499R2F-2-GP
499R2F-2-GP
499R2F-2-GP
1
1
2
1
RN5714
5V Tolerance SRN0J-6-GP
1 4 DDC_CLK_HDMI
(13) NB_DDC_CLK0
2
(13) NB_DDC_DATA0 2
UMA 3
R5715
R5716
R5717
R5718
R5719
R5720
R5721
R5722
RN5713
SRN0J-6-GP
(82) GPU_HDMI_CLK 1 4
DDC_DATA_HDMI
B (82) GPU_HDMI_DATA 2
DIS 3
B
+5V_RUN HDMI_PLL_GND
2
R5724
D
0R0402-PAD
Q5703
2N7002A-7-GP
1
HDMI_PLL_GATE G
9/22
S
R5714
100KR2J-1-GP
2
+3.3V_RUN
3
R5710
Q5702 1 HPD_HDMI_1 1 2 HPD_HDMI_CON
PMBS3904-1-GP
150KR2J-L1-GP
2
(13,82) HDMI_HPD_DET R5712

DY 200KR2J-L1-GP
1
A <Core Design> A
R5713
2
10KR2J-3-GP
Wistron Corporation
2

Title
HDMI Level Shifter/Connector

A3
5 4 3 2 1
5 4 3 2 1
SSID = User.Interface
D D
C C
SSID = Thermal
Fan Connector
B B
3 1
*Layout* 15 mil FAN1
5
(39) EMC2102_FAN_TACH EMC2102_FAN_TACH 3
AFTP5801 1 2
(39) EMC2102_FAN_DRIVE EMC2102_FAN_DRIVE 1

4
AFTP5802 1 EMC2102_FAN_TACH
FOX-CON3-6-GP-U AFTP5803 EMC2102_FAN_DRIVE
1
20.D0210.103
2
20.F1293.003
1
D5801
C5801 CH551H-30PT-GP
SC10U10V5ZY-1GP
2
A <Core Design> A
Wistron Corporation
Title
Size
ITP/Fan Connector
Document Number Rev
A3
5 4 3 2 1
SSID = SATA
SATA HDD Connector
9/24
HDD1
+3.3V_RUN P1 V33 16 16
P2 V33 17 17
P3 V33 18 18
SC56P50V2JN-2GP
SC56P50V2JN-2GP
1118-2 P7
+5V_RUN V5
P8
SC10U6D3V5MX-3GP
SC10U10V5ZY-1GP
V5
1
C5905
C5904
P9 V5
1
C5906
C5901 P13 S1
2
V12_1 GND
P14 S4
2
V12_2 GND
P15 V12_3 GND S7
GND P4
GND P5
(22) SATA_TXP0 S2 A+ GND P6
(22) SATA_TXN0 S3 A- GND P10
GND P12
(22) SATA_RXP0 S6 B+
(22) SATA_RXN0 S5 B- DAS/DSS P11
SKT-SATA7P-15P-17-GP
62.10065.C71
9/24
ODD Connector
ODD1
8
NP1
S1
S2 SATA_TXP1 (22)
S3 SATA_TXN1 (22) SATA_RX- and SATA_RX+ Trace
S4
S5
Length match within 20 mil
SATA_RXN1 (22)
S6 SATA_RXP1 (22)
S7
+5V_RUN
P1
P2
P3
1231-2
1
P4 C5909 C5910
P5 SC10U10V5ZY-1GP SC10U10V5ZY-1GP
P6 DY
2
NP2
9
SKT-SATA7P+6P-42-GP
62.10065.581
<Core Design>
Wistron Corporation
Title

HDD/ODD Rev
A3
5 4 3 2 1
SSID = AUDIO
Speaker LINE1
Connector Main 20.F0693.004 OUT
D SEC. 20.F0693.004 D
5
SPK1
FOX-CON4-24-GP
X01 0713
BLM18BD601SN1D-GP
1 AUD_HP1_JD#
(30) AUD_SPK_L- (30) AUD_HP1_JD# L6001 LINEOUT1
2 AUD_HP1_JACK_L2 1 2 AUD_HP1_JACK_L1 6
(30) AUD_SPK_L+ (30) AUD_HP1_JACK_L2
(30) AUD_SPK_R- 3 5
4 AUD_HP1_JACK_R2 1 2 AUD_HP1_JACK_R1 2
(30) AUD_SPK_R+ (30) AUD_HP1_JACK_R2
EC6007
SCD01U16V2KX-3GP
EC6008
SCD01U16V2KX-3GP
SC100P50V2JN-3GP
SC100P50V2JN-3GP
SC100P50V2JN-3GP
L6002
4
SC100P50V2JN-3GP
BLM18BD601SN1D-GP
1
1
6
1
1
EC6001
EC6002
EC6003
EC6004
3
EC6005 EC6006
0303-1 7
2
SC1KP50V2KX-1GP SC1KP50V2KX-1GP
DY DY DY DY 8
2
2
PHONE-JK383-GP
AUD_HP1_JD#
1
AFTP6002 AFTP6003
1
600ohm 100MHz
0107-2
1 AUD_SPK_L- 1 AUD_HP1_JACK_L1
AFTP6001
AFTP6005
1 AUD_SPK_L+
AUD_SPK_R-
AFTP6004
AUD_HP1_JACK_R1
200mA 0.5ohm DC AFTP6006 1 22.10133.K31
1 1
AFTP6007 1 AUD_SPK_R+ AFTP6008
AFTP6009
C C
AUD_AGND
1117-1
MIC IN Internal
(30) AUD_VREFOUT_B Microphone
2
1
MIC1 is in DIP
1
C6003
RN6001 SC1U10V3KX-3GP
SRN4K7J-8-GP 1 MIC1
2
(30) INT_MIC_L_R MICROPHONE-40-GP-U1

3
4
2
1
MICIN1
X01 0713 EC6009
SC1KP50V2KX-1GP
23.42143.001
8
2
B B
7
R6001 3
1
AUD_EXT_MIC_L C6001 1 SC1U10V3KX-3GP MIC_IN_L_2 MIC_IN_L_C
(30) AUD_EXT_MIC_L 2 2 1
0R0603-PAD
4 1117-1
R6002 2
5 R6005 1 2
AUD_EXT_MIC_R C6002 2 1 SC1U10V3KX-3GP MIC_IN_R_2 1 2 MIC_IN_R_C 6 0R2J-2-GP
(30) AUD_EXT_MIC_R 0R0603-PAD R6004 1 2
PHONE-JK383-GP 0R2J-2-GP
R6003 1
0R2J-2-GP DY 2
(30) EXT_MIC_JD# R6006 1
0R2J-2-GP DY 2
1
EC6011 R6009 1 2
EC6010 22.10133.K31 0R2J-2-GP
R6008 1
DY 2
SC100P50V2JN-3GP
2
1 AFTP6010 0R2J-2-GP
SC100P50V2JN-3GP
R6010 1
1 MIC_IN_L_C 0R2J-2-GP DY 2
AFTP6011
1 MIC_IN_R_C
AFTP6012
1 EXT_MIC_JD# AUD_AGND
AFTP6013
AUD_AGND
1117-1
A <Core Design> A
Wistron Corporation
Title
Audio Jack
A3
Berry A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
5 4 3 2 1
5 4 3 2 1
SSID = Flash.ROM
D D
SPI FLASH ROM (16M bits) for KBC

+KBC_PW R
+KBC_PW R
1118-2
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C6202
C6203
1
1
1
3
4
C6201
R6201 RN6201
DY DY
2
100KR2J-1-GP SRN100KJ-6-GP
DY
2
1231-2
2
1
EC_SPI_HOLD#
C
1231-1 U6201 +KBC_PW R C
(37) EC_SPI_CS# EC_SPI_CS# 1 8

R6202 CS# VCC
(37) EC_SPI_DI 1 2 0R0402-PAD EC_SPI_DI_R 2 DO/IO1 HOLD#/IO3 7 EC_SPI_HOLD#
(37) EC_SPI_W P#_R R6203 1 2 0R0402-PAD EC_SPI_W P# 3 6 EC_SPI_CLK (37)
WP#/IO2 CLK EC_SPI_DO_R
4 GND DI/IO0 5 1 2 EC_SPI_DO (37)
R6204 33R2J-2-GP
1
EC6201 R6207 W 25Q16BVSSIG-GP
SC4D7P50V2CN-1GP EC6202 EC6203
DY 100KR2J-1-GP
2
SC4D7P50V2CN-1GP SC22P50V2JN-4GP
DY
2
1117-6
2
1215-2
PN:72.25Q16.001
B B
SSID = RBATT
+3.3V_RTC_LDO
+RTC_CELL D6201
RTC Connector
0105-8
1
BAT54C-U-GP
R6205
1 2 RTC_PW R_L 3
0R0402-PAD
+RTC_VCC
1225-5
1
RTC1
2
A C6204 <Core Design> A

SC1U10V3KX-3GP RTC_PW R 1 R6206 2 1
2
1KR2J-1-GP PWR
1 2 GND
AFTP6203 NP1
NP2
NP1
NP2
Wistron Corporation
Width=20mils BAT-CON2-1-GP-U
Title
+RTC_VCC
62.70001.011 Size Document Number
Flash/RTC Rev
1
AFTP6202 A3
5 4 3 2 1
5 4 3 2 1
SSID = USB
Close to I/O connector
IO Board USB Power
D Support 2A D
+5V_ALW +5V_USB1
U6301
9/30
at least 80 mil
at least 80 mil 1 GND VOUT#8 8
SC1U10V3KX-3GP
2 VIN VOUT#7 7
C6302
3 VIN VOUT#6 6
1
(37) USB_PWR_EN# 4 EN# OC# 5
1
SCD1U10V2KX-5GP
C6301
DY
2
UP7534BRA8-15-GP
DY
2
USB_OC#0_1 (21) 1231-2
C C
CRT Board USB Power Close to CRT Board connector
Support 2A
+5V_ALW +5V_USB2
U6302
9/30
at least 80 mil
at least 80 mil 1 GND VOUT#8 8
SC1U10V3KX-3GP
2 VIN VOUT#7 7
C6304
3 VIN VOUT#6 6
1
SCD1U10V2KX-5GP
B
(37) USB_PWR_EN# 4 EN# OC# 5 B
1
C6303
DY
2
UP7534BRA8-15-GP
2
1231-2
USB_OC#2_3 (21)
1118-2
<Core Design>
A
Title
USB Power SW
5 4 3 2 1
5 4 3 2 1
D D
(Blanking)
C C
B B
<Core Design>
A
Title
Reserved
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
5 4 3 2 1
5 4 3 2 1
Power LED(White)
+5V_ALW
9/25 Q6602
R2
E
0111-2
PW RLED#_C B R1
D C LED_PW R 1 2 PW R_LED_B D
R6601 1KR2J-1-GP
10/1
1
EC6601
PDTA143ET-GP POW ER_SW _LED_B
RN6601
SATA_LED#_C DYSC220P50V2KX-3GP 1
R6603
2
470R2J-2-GP
1 4
84.00143.M11
2
(22) SATA_LED# PW RLED#_C
(37) PW RLED# 2 3
POW ER_SW _LED_C
SRN15KJ-3-GP
1
R6609 DY 21KR2J-1-GP
RN6602
0208-1
(37) AMBER_LED#_KBC
(37) W HITE_LED#_KBC
1
2
4
3
AMBER_LED_BAT#
W HITE_LED_BAT# SATA HDD LED(White)
SRN15KJ-3-GP +5V_RUN
9/25 Q6601
R2
E
0111-2
1 2AMBER_LED#_KBC SATA_LED#_C B R1
C6601 SCD1U10V2KX-5GP SATA_LED_R SATA_LED
1 2W HITE_LED#_KBC
1215-3 C 2
1KR2J-1-GP
1
R6604
1
PDTA143ET-GP EC6604
10/8
1116-7 DY SC220P50V2KX-3GP
84.00143.M11
2
LEDBD1
7
C Battery LED1(White) PW R_LED_B
SATA_LED
1
2
C
+5V_ALW BAT_W HITE

9/25 Q6603
BAT_AMBER
3
R2
E
0111-2 4
5
W HITE_LED_BAT# B 6
R1
C W HITE_LED_BAT 2 1 BAT_W HITE
1KR2J-1-GP R6602 8
1
PDTA143ET-GP EC6602 ACES-CON6-13-GP
DY SC220P50V2KX-3GP
84.00143.M11
2
20.K0320.006
Battery LED2(Amber)
+5V_ALW
9/25 Q6604
R2
E
0111-2
AMBER_LED_BAT# B R1
C AMBER_LED_BAT 1 2 BAT_AMBER
R6606 1KR2J-1-GP
PDTA143ET-GP
1
EC6603
B 84.00143.M11 DY SC220P50V2KX-3GP B
2
Power button LED(White)

1216-1
(37) KBC_PW RBTN# 1 2 PW RBTN1
R6605 0R0402-PAD 5
KBC_PW RBTN#_C 2
+5V_ALW POW ER_SW _LED_C
0208-1 POW ER_SW _LED_B
3
0208-1 4
9/25 Q6605
POW ER_SW _LED_C
R2
E
1
R6610 DY 21KR2J-1-GP 6
(37) PW R_BTN_LED# 1 2 PW R_BTN_LED#_C B R1

R6607 15KR2J-1-GP POW ER_SW _LED_R POW ER_SW _LED_B ACES-CON4-10-GP-U
C 1
DY 21KR2J-1-GP
SC180P50V2JN-1GP
R6608
A
20.K0320.004 <Core Design> A
EC6605
PDTA143ET-GP DY
1
84.00143.M11 Wistron Corporation

2

9/16 Taipei Hsien 221, Taiwan, R.O.C.
Title
LED Bard/Power Button

A3
Berry A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
5 4 3 2 1
5 4 3 2 1
SSID = KBC SSID = Touch.Pad
D
Internal KeyBoard Connector TouchPad Connector D
0111-1
+5V_RUN
KB1 1
31 AFTP6801
1 KB_DET# (37)
SCD1U10V2KX-5GP
1
2 KROW 7 1
3 KROW 6 1 AFTP6802 C6801
4 KROW 4 1 AFTP6803 +5V_RUN
2
5 KROW 2 1 AFTP6804
6 KROW 5 1 AFTP6805
KROW 1 AFTP6806
7
KROW 3
1
AFTP6807
10/7
8 1 10/2
2
1
9 KROW 0 1 AFTP6808
10 KCOL5 1 AFTP6809 RN6801
11 KCOL4 1 AFTP6810 SRN10KJ-5-GP
12 KCOL7 1 AFTP6811 KROW [0..7] (37) TPAD1
13 KCOL6 1 AFTP6812 6
14 KCOL8 1 AFTP6813
3
4
15 KCOL3 1 AFTP6814 KCOL[0..16] (37) 4
16 KCOL1 1 AFTP6815 (37) TPCLK 3
17 KCOL2 1 AFTP6816 (37) TPDATA 2
18 KCOL0 1 AFTP6817
19 KCOL12 1 AFTP6818 1 1
1
1
C 20 KCOL16 1 AFTP6819 AFTP6820 C
21 KCOL15 1 AFTP6821 C6802 C6803 5
22 KCOL13 1 AFTP6823 SC33P50V2JN-3GP SC33P50V2JN-3GP
2
2
23 KCOL14 1 AFTP6822 ACES-CON4-10-GP-U
24 KCOL9 1 AFTP6824
25 KCOL11 1 AFTP6825
26 KCOL10 1 AFTP6826
27 AFTP6827
28 20.K0320.004
29
30 1
AFTP6828
20.K0326.004
32
1 +5V_RUN
ACES-CON30-8-GP AFTP6829 1 TPCLK
AFTP6830 1 TPDATA
AFTP6831
20.K0524.030
20.K0461.030
B B
KB Backlight Connector
0208-2
+5V_RUN +5V_KB_BL
F6801
L6801 20.K0320.004
KB_LED_PW R 1
1
DY 2
DY 2
KBLIT1
1
C6804 FUSE-D5A6V-2-GP BLM18PG181SN1D-GP C6805 5

SCD1U10V2KX-5GP
DY DY
SC10U10V5KX-2GP
1
2
(37) KB_LED_BL_DET 2
3
KB_BL_CTRL# 4
6
DY +5V_KB_BL 1
SC10P50V2JN-4GP
EC6802
EC6801
SC10P50V2JN-4GP
KB_LED_BL_DET 1 AFTP6832
1
KB_BL_CTRL# 1 AFTP6833
ACES-CON4-10-GP-U AFTP6834
Q6801
DYDY 1
2
A 1 D D 6 AFTP6835 <Core Design> A

2 D D 5
3 G S 4
(37) KB_BL_CTRL DY
Wistron Corporation
1
SI3456DDV-T1-GE3-GP
R6801 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
DY 100KR2J-1-GP
0225-2 Taipei Hsien 221, Taiwan, R.O.C.
Title
2
Key Board/Touch Pad

A3
5 4 3 2 1
5 4 3 2 1
SSID = Hall.Sensor
D D
9/29
+3.3V_ALW
AFTP6901 1 +3.3V_ALW
AFTP6902 1 LID_CLOSE#_1
SCD1U10V2KX-5GP
C6903
9/29 11/9
1
+3.3V_ALW
2
C
9/17 0208-3 C
1
HALLSW1
DY R6901
100KR2J-1-GP 1 VDD
1231-1 3
GND 2
2 LID_CLOSE# OUTPUT
(37) LID_CLOSE# 1 R6902 1 2 0R0402-PAD LID_CLOSE#_1
DY SOT23-2D8-213H56-COLAY-GP
C6902
SCD047U16V2KX-1-GP
2
AFTP6903
74.06781.07B 1
B B
<Core Design>
A
Title
Hall Effect Sensor

A4
5 4 3 2 1
5 4 3 2 1
SSID = Debug
D D
+3.3V_RUN
DB1
1
(20,37) LPC_LAD0 LPC_LAD0 2
(20,37) LPC_LFRAME# 6
(20,76,78) PLTRST#_LAN_WLAN 7
8
DY
(20,24) PCLK_FWH 9
10
11
12
C MLX-CON10-7-GP C
20.D0183.110
B B
<Core Design>
A
Title
Dubug connector
A4
5 4 3 2 1
5 4 3 2 1
D D
(Blanking)
C C
B B
<Core Design>
A
Title
Size
RESERVED
Document Number Rev
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
RESERVED
A3
5 4 3 2 1
5 4 3 2 1
D Bluetooth Module conn. D
BT1
15
NP1
AFTP7301 1 BLUETOOTH_DET# 1 2 BT_ACT +3.3V_RUN
W LAN_ACT 3 4
AFTP7302 1 BDC_ON 5 6 USB_PP9
BLUETOOTH_EN 7 8 USB_PN9
AFTP7304 1 BT_LED 9 10
1
AFTP7305 1 BLUETOOTH_GPIO3 11 12
AFTP7314 1 BLUETOOTH_GPIO5 13 14 C7301
NP2 SC2D2U6D3V3KX-GP
2
16
1 AFTP7313
HRS-CONN14D-GP-U
(21) USB_PP9 USB_PP9 AFTP7316 1 W LAN_ACT

(21) USB_PN9 USB_PN9 AFTP7317 1 BLUETOOTH_EN
(76) BT_ACT BT_ACT AFTP7315 1 BT_ACT
(37) BLUETOOTH_EN BLUETOOTH_EN AFTP7318 1 +3.3V_RUN
(76) W LAN_ACT W LAN_ACT AFTP7319 1 USB_PP9
AFTP7320 1 USB_PN9
C C
1118-2
10KR2J-3-GP
100KR2J-1-GP
SC56P50V2JN-2GP
1
1
EC7302
1
R7303
R7304
DY
2
2
B B
A <Core Design> A
Wistron Corporation
Title
Bluetooth
A3
Berry A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
5 4 3 2 1
5 4 3 2 1
D D
(Blanking)
C C
B B
<Core Design>
A
Title
Reserved
A4
5 4 3 2 1
5 4 3 2 1
SSID = Int.Conn 10/9
IOBD1
85 NP1
D 86 84 D
(21) USB_PP0 2 1 SATA_TXN2 (22)

ESATA USB SATA(ESATA)
(21) USB_PN0 4 3 SATA_TXP2 (22)
6 5
(21) USB_PP5 8 7 SATA_RXN2 (22)
WWAN USB (21) USB_PN5 10 9 SATA_RXP2 (22) SATA(ESATA)
12 11
(21) USB_PN1 14 13
USB PORT (21) USB_PP1 16 15
PCIE_TXP0 (12)
PCIE_TXN0 (12)
WLAN PCIE
18 17
(21) USB_PP4 20 19
WLAN USB (21) USB_PN4 22 21
PCIE_RXP0 (12)
PCIE_RXN0 (12)
WLAN PCIE
24 23
(37) E51_RXD 26 25
(37) E51_TXD 28 27
CLK_PCIE_WLAN (7)
CLK_PCIE_WLAN# (7)
WLAN CLK
30 29
(12) PCIE_RXP2 32 31
WWAN PCIE (12) PCIE_RXN2 34 33
CLK_PCIE_LAN (7)
CLK_PCIE_LAN# (7)
LAN CLK
C 36 35 C
(12) PCIE_TXP2 38 37
WWAN PCIE (12) PCIE_TXN2 40 39
CLK_PCIE_WWAN (7)
CLK_PCIE_WWAN# (7)
WWAN CLK
42 41
44 43
SMBUS (18,19) SB_SMBDATA
(18,19) SB_SMBCLK 46 45 at least 80 mil
48 47 +5V_USB1
50 49 +5V_ALW
52 51
54 53
56 55 +3.3V_RUN
+DC_IN_SS 58 57
60 59
(37) WIFI_RF_EN 62 61 +3.3V_ALW
(7) WWAN_CLK_REQ# 64 63 +1.5V_RUN
(37) WWAN_RADIO_DIS#
(37) PSID_DISABLE#
66
68
65
67
0208-2 PM_LAN_ENABLE (37)
(37) 8103_GPO 70 69 PLTRST#_LAN_WLAN (20,70,78)
(12) PCIE_RXP1 72 71 WLAN_CLK_REQ# (7)
LAN PCIE (12) PCIE_RXN1 1216-2 74 73 PCIE_WAKE# (21)
B 76 75 BT_ACT (73) B
(12) PCIE_TXP1 78 77 WLAN_ACT (73)
LAN PCIE (12) PCIE_TXN1 80 79 PSID_EC (37)
83 81
82 NP2
ACES-CONN80D-GP
20.F1009.080
<Core Design>
A
0107-6 Wistron Corporation A
1
DY2 USB_PP5 Taipei Hsien 221, Taiwan, R.O.C.
C7602 1 SC10P50V2JN-4GP
2 USB_PN5
C7601 SC10P50V2JN-4GP Title
DY
IO Board Connector Rev
5 4 3 2 1
5 4 3 2 1
10/1 CRT Board Connector

SSID = Int.Conn CRTBD1
Pin define modified
11/12-5 21
1 1117-3
at least 80 mil
2 +5V_USB2
L7703 3
4 +5V_RUN
CRT_R 2 1 CRT_RED 5 USB_PN2 (21)
BLM18BB220SN-GP 6 USB_PP2 (21)
D L7702 7 USB PORT D
8 USB_PN3 (21)
CRT_G 2 1 CRT_GREEN 9 USB_PP3 (21)
BLM18BB220SN-GP 10 USB PORT
CRT_RED
L7701 11
12
0208-4
CRT_B 2 1 CRT_BLUE 13 CRT_GREEN
BLM18BB220SN-GP 14 CRT RGB CRT_RED 1
SC8P250V2CC-GP
SC8P250V2CC-GP
SC8P250V2CC-GP
C7703 C7702 C7704 CRT_BLUE CRT_GREEN 1 AFTP7701
C7706
C7705
C7707
15
5
6
7
8
1
CRT_BLUE 1 AFTP7702
RN7713
0108-2 16
17 CRT_HSYNC_CON AFTP7703
SC15P50V2JN-2-GP
SC15P50V2JN-2-GP
SC15P50V2JN-2-GP
SRN150F-1-GP
DY 2
DY DY 18 CRT_VSYNC_CON CRT H/VSYNC
2
19 CRT_DDCCLK_CON
20 CRT_DDCDATA_CON CRT SMBUS
22
4
3
2
1
1116-8
ACES-CON20-1-GP-U
20.F0772.020
SEC. 20.F1035.020
CRT Hsync & Vsync level shift Close to CRT Board CONN
CRT RGB
+5V_RUN_CRT
1120-2
C
Close to CRT Board CONN C
Filter design on CRT Board
RN7701 +5V_RUN_CRT +5V_RUN
D7701
1
1 8 CRT_R
(82) VGA_CRT_RED CRT_G C7701
(82) VGA_CRT_GREEN 2 7 2 1
CRT_B SCD1U10V2KX-5GP
3
DIS 6
2
(82) VGA_CRT_BLUE
4 5 CH551H-30PT-GP
SRN0J-7-GP
14
1
U7701A
9/18 RN7702
3.3V Tolerance
1 8 (80,82) VGA_CRT_HSYNC 2 3 CRT_HSYNC_OUT
(13) M_BLUE
(13) M_GREEN 2 7 (80,82) VGA_CRT_VSYNC
(13) M_RED 3
UMA 6
TSAHCT125PW -GP
14
4 5
7
4
U7701B RN7705
4 1 CRT_HSYNC_CON
SRN0J-7-GP CRT_VSYNC_OUT CRT_VSYNC_CON
5 6 3
DIS 2
TSAHCT125PW -GP SRN33J-5-GP-U
7
CRT DDCDATA & DDCCLK +5V_RUN_CRT
9/15
+3.3V_RUN
0108-2
14
13
B U7701D B
RN7711
9/29 12 11 NB_HSYNC_OUT 3 2
(13) VGA_HSYNC
3
4
RN7712
(13) VGA_VSYNC 4
UMA 1
TSAHCT125PW -GP
SRN2K2J-1-GP 3.3V Tolerance
7
SRN0J-6-GP
RN7709
5V Tolerance SRN0J-6-GP
9/29
14
10
2
1
1 4 CRT_DDCDATA_CON_C U7701C
(13) DDC_DATA_CON
(13) DDC_CLK_CON 2
UMA 3 U7702
9 8 NB_VSYNC_OUT
4 3 CRT_DDCDATA_CON
5 2 CRT_DDCCLK_CON TSAHCT125PW -GP
7
6 1
RN7710
9/18 SRN0J-6-GP DMN66D0LDW -7-GP
1 4 CRT_DDCCLK_CON_C
(82) VGA_CRT_DDCCLK
(82) VGA_CRT_DDCDATA 2
DIS 3
5V Tolerance
Pull High 5V Design on CRT Board
A <Core Design> A
Wistron Corporation
Title
CRT Board Connector

A3
5 4 3 2 1
5 4 3 2 1
SSID = SDIO
D D
Card Reader connector
10/7
+3.3V_RUN
CARDBD1
7
C
1116-9 1 C
(20,70,76) PLTRST#_LAN_WLAN 2
3
(21) USB_PN10 4
(21) USB_PP10 5
6
8
MLX-CON6-21-GP
20.F1035.006
B B
<Core Design>
A
Title
CARD Reader CONN

A4
5 4 3 2 1
5 4 3 2 1
H1 H2 H3 H4 H6 H7 H8 H9
HTE95BE95R29-R-5-GP HTE95BE95R29-R-5-GP HTE95BE95R29-R-5-GP HTE95BE95R29-R-5-GP HTE95BE95R29-R-5-GP HTE95BE95R29-R-5-GP HTE95BE95R29-R-5-GP HTE95BE95R29-R-5-GP H5
HOLE256R111-GP
1
1
1
D D
H11
HOLE256R111-GP
0210-2
H10
CPU Thermal module hole GPU Thermal module hole
HOLE335R115-GP
HTML1 HTML2 HTML3 stand off
1
HOLE197R166-GP HOLE197R166-GP HOLE197R166-GP HGPU1
STF237R117H83-1-GP HBT1
STF237R117H123-GP
1
1
1
1
DY
DY DY DY
EMI Reserve
C +PW R_SRC +VGA_CORE +3.3V_RUN +5V_ALW C
SPR1
1118-2
1
1
SCD1U10V2KX-5GP SPRING-58-GP
EC7901 EC7902 EC7904 EC7903 EC7905 EC7906 EC7907 EC7910 EC7911 EC7912
1
DY DY 10/6 DY
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
2
2
DY DY DY
10/5
EMI Reserve 1117-4
+PW R_SRC +3.3V_RUN

+3.3V_RUN +5V_RUN +5V_RUN +VCC_CORE +5V_RUN +PW R_SRC +5V_RUN +1.5V_RUN
2
1 EC7922 1 EC7919 1 EC7914 1 EC7918

B EC7924 EC7916 EC7920 EC7923 EC7917 DY
2
SC10P50V2JN-4GP DY
2
SC10P50V2JN-4GP DY
2
SC10P50V2JN-4GP DY
2
SC10P50V2JN-4GP B
SC10P50V2JN-4GP
SC10P50V2JN-4GP
SC10P50V2JN-4GP
SC10P50V2JN-4GP
SC10P50V2JN-4GP
DY DY DY DY DY
1
1 EC7915 1 EC7921 1 EC7913

DY
2
SC10P50V2JN-4GP DY
2
SC10P50V2JN-4GP DY
2
SC10P50V2JN-4GP
1118-2 RF Team Solution 0106-3 RF Team Solution 0108-1 EMC reserved
+PW R_SRC +1.5V_SUS

+3.3V_ALW +1.5V_RUN +5V_RUN +PW R_SRC
SC56P50V2JN-2GP
SC56P50V2JN-2GP
SC56P50V2JN-2GP
SC56P50V2JN-2GP
SC56P50V2JN-2GP
SC56P50V2JN-2GP
SC56P50V2JN-2GP
SC56P50V2JN-2GP
SC56P50V2JN-2GP
SC56P50V2JN-2GP
1
1
C7909 C7906 C7905 C7904 C7902 C7917 C7922 EC7927 EC7926 EC7925
DY DY DY DY DY DY
2
2 0224-1
A
+15V_ALW +1.5V_SUS <Core Design> A
+1.1V_RUN +1.8V_RUN +3.3V_RUN +PW R_SRC +DC_IN_SS +SDC_IN
0225-5
Wistron Corporation
SC56P50V2JN-2GP
SC56P50V2JN-2GP
SC56P50V2JN-2GP
SC56P50V2JN-2GP
SC56P50V2JN-2GP
EC7930
EC7931
EC7929
EC7932
SC56P50V2JN-2GP
SC56P50V2JN-2GP
SC56P50V2JN-2GP
SC56P50V2JN-2GP
1

SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
C7907 C7915 C7911 C7910 C7908 C7919 C7920 C7921 Taipei Hsien 221, Taiwan, R.O.C.
DY DY DY DY
2
Title
DY DY DY DY
2
UNUSED PARTS/EMI Capacitors

A3
Berry A00
5 4 3 2 1
5 4 3 2 1
CONFIGURATION STRAPS RECOMMENDED SETTINGS

0= DO NOT INSTALL RESISTOR
ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED, 1 = INSTALL 3K RESISTOR
X = DESIGN DEPENDANT
(57) PCIE_N_H_TX_GRX_P[12..15]
THEY MUST NOT CONFLICT DURING RESET NA = NOT APPLICABLE
10/8 PLATFORM
(57) PCIE_N_H_TX_GRX_N[12..15] PCIE_NRX_GTX_P[0..15] (12)
VGA1A 1 OF 8 DESCRIPTION OF DEFAULT SETTINGS RECOMMEND
STRAPS PIN SETTING
(12) PCIE_NTX_GRX_P[0..11] PCIE_NRX_GTX_N[0..15] (12)
Transmitter Power Savings Enable
(12) PCIE_NTX_GRX_N[0..11] TX_PWRS_ENB GPIO0 0: 50% Tx output swing 1: Full Tx output swing X 1
x01 change tolerant 20091117
D PCIE TRANSMITTER DE-EMPHASIS ENABLED D
PCIE_NTX_GRX_P0 PEG_C_RXP0C8001
TX_DEEMPH_EN GPIO1 0:Tx de-emphasis disabled 1:Tx de-emphasis enabled X 1
AA38 PCIE_RX0P PCIE_TX0P Y33 DIS
1 2 SCD1U10V2KX-5GP PCIE_NRX_GTX_P0
PCIE_NTX_GRX_N0 Y37 Y32 PEG_C_RXN0C8002 DIS
1 2 SCD1U10V2KX-5GP PCIE_NRX_GTX_N0 0:Advertises the PCIe device as 2.5GT/s capable at power on.
PCIE_RX0N PCIE_TX0N
BIF_GEN2_EN_A GPIO2 1:Advertises the PCIe device as 5.0GT/s capable at power on. 0 0
PCIE_NTX_GRX_P1 Y35 W33 PEG_C_RXP1C8003 DIS
1 2 SCD1U10V2KX-5GP PCIE_NRX_GTX_P1 optional input allow the system to request a fast
PCIE_NTX_GRX_N1 PCIE_RX1P PCIE_TX1P PEG_C_RXN1C8004
W36 W32 DIS
1 2 SCD1U10V2KX-5GP PCIE_NRX_GTX_N1 GPIO5_AC_BATT GPIO5 ? 0
PCIE_RX1N PCIE_TX1N power reduction by setting GPIO5 to low.
PCIE_NTX_GRX_P2 W38 U33 PEG_C_RXP2C8005 DIS
1 2 SCD1U10V2KX-5GP PCIE_NRX_GTX_P2 RESERVED GPIO8 RESERVED 0 0
V37 PCIE_RX2N PCIE_TX2N U32 DIS
1 2 SCD1U10V2KX-5GP PCIE_NRX_GTX_N2
0:VGA Controller capacity enabled
VGA_DIS GPIO9 1:The device won't be recognized as the system's VGA controller 0 0
PCIE_NTX_GRX_P3 V35 U30 PEG_C_RXP3C8008 DIS
U36 PCIE_RX3N PCIE_TX3N U29 DIS
1 2 SCD1U10V2KX-5GP PCIE_NRX_GTX_N3 BIOS_ROM_EN=1, Config[2:0] defines the ROM type 0 0 1
ROMIDCFG[2:0] GPIO[13:11] BIOS_ROM_EN=0, Config[2:0] defines the primary memory aperture size X X X
(256MB)
PCIE_NTX_GRX_P4 U38 T33 PEG_C_RXP4C8009 DIS
T37 PCIE_RX4N PCIE_TX4N T32 DIS
1 2 SCD1U10V2KX-5GP PCIE_NRX_GTX_N4 RESERVED GPIO21 RESERVED 0 0
0:Disable external BIOS ROM device
PCIE_NTX_GRX_P5 T35 T30 PEG_C_RXP5C8011 DIS
1 2 SCD1U10V2KX-5GP PCIE_NRX_GTX_P5 BIOS_ROM_EN GPIO_22_ROMCSB X 0
1:Enable external BIOS ROM device
R36 PCIE_RX5N PCIE_TX5N T29 DIS
PCI EXPRESS INTERFACE

VIP Device Strap Enable indicates to the software driver that it sense
VIP_DEVICE_STRAP_EN V2SYNC X 0
whether or not a VIP device is connected on the VIP Host interface.
R38 PCIE_RX6P PCIE_TX6P P33 DIS
PCIE_NTX_GRX_N6 P37 P32 PEG_C_RXN6C8014 DIS
PCIE_RX6N PCIE_TX6N
C
RSVD H2SYNC RESERVED 0 0 C
PCIE_NTX_GRX_P7 P35 P30 PEG_C_RXP7C8016 DIS
N36 PCIE_RX7N PCIE_TX7N P29 DIS
1 2 SCD1U10V2KX-5GP PCIE_NRX_GTX_N7 RSVD GENERICC RESERVED 0 0
PCIE_NTX_GRX_P8 N38 N33 PEG_C_RXP8C8018 DIS

1 2 SCD1U10V2KX-5GP PCIE_NRX_GTX_P8 AUD[1] HSYNC X 1
M37 PCIE_RX8N PCIE_TX8N N32 DIS
1 2 SCD1U10V2KX-5GP PCIE_NRX_GTX_N8 AUD[1:0]:11-Audio for both DisplayPort and HDMI
AUD[0] VSYNC X 1
M35 PCIE_RX9P PCIE_TX9P N30 DIS
PCIE_NTX_GRX_N9 L36 N29 PEG_C_RXN9C8019 DIS
PCIE_RX9N PCIE_TX9N
PCIE_NTX_GRX_P10 L38 L33 PEG_C_RXP10

C8021 DIS
PCIE_NTX_GRX_N10 PCIE_RX10P PCIE_TX10P PEG_C_RXN10
C8022
K37 PCIE_RX10N PCIE_TX10N L32 DIS
+3.3V_RUN_VGA
PIN STRAPS
PCIE_NTX_GRX_P11 K35 L30 PEG_C_RXP11
C8023 DIS
PCIE_NTX_GRX_N11 PCIE_RX11P PCIE_TX11P PEG_C_RXN11
C8024 DIS 2 SCD1U10V2KX-5GP PCIE_NRX_GTX_N11
J36 PCIE_RX11N PCIE_TX11N L29 1
(82) TX_PW RS_ENB R8001 1
DY 2 3KR2J-2-GP
PCIE_N_H_TX_GRX_P12 J38 K33 PEG_C_RXP12

C8025 DIS
1 2 SCD1U10V2KX-5GP PCIE_NRX_GTX_P12 (82) TX_DEEMPH_EN R8002 1
DY 2 3KR2J-2-GP
PCIE_N_H_TX_GRX_N12 PCIE_RX12P PCIE_TX12P PEG_C_RXN12
H37 PCIE_RX12N PCIE_TX12N K32 1
(82) BIF_GEN2_EN_A R8003 1
DY 2 10KR2J-3-GP
PCIE_N_H_TX_GRX_P13 H35 J33 PEG_C_RXP13

C8028 DIS
1 2 SCD1U10V2KX-5GP PCIE_NRX_GTX_P13 (82) GPIO8_ROMSO R8004 1
DY 2 10KR2J-3-GP
PCIE_N_H_TX_GRX_N13 PCIE_RX13P PCIE_TX13P PEG_C_RXN13
G36 PCIE_RX13N PCIE_TX13N J32 1
(82) VGA_DIS R8005 1
DY 2 10KR2J-3-GP
B PCIE_N_H_TX_GRX_P14 PEG_C_RXP14
C8030 B
DIS 2 SCD1U10V2KX-5GP PCIE_NRX_GTX_P14
PCIE_N_H_TX_GRX_N14
G38
F37
PCIE_RX14P PCIE_TX14P K30
K29 PEG_C_RXN14
C8029
1
DIS
1 2 SCD1U10V2KX-5GP PCIE_NRX_GTX_N14 (82) CONFIG0 R8006 1
DIS 2 10KR2J-3-GP
PCIE_RX14N PCIE_TX14N
(82) CONFIG1 R8007 1
DY 2 10KR2J-3-GP
PCIE_N_H_TX_GRX_P15 PEG_C_RXP15
C8032 DIS 2 SCD1U10V2KX-5GP PCIE_NRX_GTX_P15
PCIE_N_H_TX_GRX_N15
F35
E37
PCIE_RX15P PCIE_TX15P H33
H32 PEG_C_RXN15
C8031
1
DIS
1 2 SCD1U10V2KX-5GP PCIE_NRX_GTX_N15 (82) CONFIG2 R8008 1
DY 2 10KR2J-3-GP
PCIE_RX15N PCIE_TX15N
RN8001 1 4
(77,82) VGA_CRT_VSYNC
3 SRN10KJ-5-GP
CLOCK (77,82) VGA_CRT_HSYNC 2
DIS
(7) CLK_PCIE_VGA AB35
AA36
PCIE_REFCLKP 0105-3
(7) CLK_PCIE_VGA# PCIE_REFCLKN
R8012 1
DY 2 10KR2J-3-GP
CALIBRATION (82) VSYNC_DAC2
R8017 DIS
1204-3 AJ21 Y30 PCIE_CALRP 1 2 R8013 1
DY 2 10KR2J-3-GP
NC#AJ21 PCIE_CALRP (82) HSYNC_DAC2
DIS_Park/Mad 1K27R2F-L-GP
1 PW RGOOD
2
AK21
AH16
NC#AK21
Y29 PCIE_CALRN 1 2 R8014 1
DY 2 10KR2J-3-GP
R8018 10KR2F-2-GP PWRGOOD PCIE_CALRN R8019 2KR2F-3-GP
+1.0V_RUN_VGA (82) BIOS_ROM_EN
DIS (82) GPIO5_AC_BATT R8015 1
DY 2 10KR2J-3-GP
VGA_RST# AA30
PERST# R8016 DY 10KR2J-3-GP
0105-3 DIS_GPU (82) GPIO21_BB_EN 1 2
Remove MADISON-PRO-2-GP
(13,20,37) PLTRST#_NB_GPU 1 2
A R8021 0R0402-PAD <Core Design> A
10/7
Wistron Corporation
2

C8033 Taipei Hsien 221, Taiwan, R.O.C.
DY SCD1U10V2KX-5GP
1
Title
GPU_PCIE/STRAPPING(1/5)
A3 Berry A00
5 4 3 2 1
5 4 3 2 1
VGA1C
10/8 3 OF 8 VGA1D
10/8 4 OF 8
DDR2 DDR2 DDR2 DDR2
(85) MDA[0..31] GDDR3/GDDR5 GDDR5/GDDR3 (87) MDB[0..31] GDDR3/GDDR5 GDDR5/GDDR3
DDR3 DDR3 DDR3 DDR3
MDA0 C37 G24 MDB0 C5 P8
DQA0_0/DQA_0 MAA0_0/MAA_0 MAA0 (85,86) DQB0_0/DQB_0 MAB0_0/MAB_0 MAB0 (87,88)
MDA1 C35 J23 MDB1 C3 T9
MDA2 A35 H24 MDB2 E3 P9
MEMORY INTERFACE A
MEMORY INTERFACE B
MDA3 E34 J24 MDB3 E1 N7
MDA4 G32 H26 MDB4 F1 N8
MDA5 D33 J26 MDB5 F3 N9
MDA6 F32 H21 MDB6 F5 U9
MDA7 E32 G21 MDB7 G4 U8
MDA8 D31 H19 MDB8 H5 Y9
MDA9 F30 H20 MAA9 (85,86) MDB9 H6 W9 MAB9 (87,88)
MDA10 DQA0_9/DQA_9 MAA1_1/MAA_9 MDB10 DQB0_9/DQB_9 MAB1_1/MAB_9
D C30 L13 MAA10 (85,86) J4 AC8 MAB10 (87,88) D
A30 G16 MAA11 (85,86) K6 AC9 MAB11 (87,88)
F28 J16 MAA12 (85,86) K5 AA7 MAB12 (87,88)
C28 H16 A_BA2 (85,86) L4 AA8 B_BA2 (87,88)
MDA14 DQA0_13/DQA_13 MAA1_5/MAA_13_BA2 MDB14 DQB0_13/DQB_13 MAB1_5/BA2
A28 J17 A_BA0 (85,86) M6 Y8 B_BA0 (87,88)
MDA15 DQA0_14/DQA_14 MAA1_6/MAA_14_BA0 MDB15 DQB0_14/DQB_14 MAB1_6/BA0
E28 H17 A_BA1 (85,86) M1 AA9 B_BA1 (87,88)
MDA16 DQA0_15/DQA_15 MAA1_7/MAA_A15_BA1 MDB16 DQB0_15/DQB_15 MAB1_7/BA1
D27 M3
MDA17 DQA0_16/DQA_16 MDB17 DQB0_16/DQB_16
F26 A32 DQMA0 (85) M5 H3 DQMB0 (87)
MDA18 DQA0_17/DQA_17 WCKA0_0/DQMA_0 MDB18 DQB0_17/DQB_17 WCKB0_0/DQMB_0
C26 C32 DQMA1 (85) N4 H1 DQMB1 (87)
MDA19 DQA0_18/DQA_18 WCKA0#_0/DQMA_1 MDB19 DQB0_18/DQB_18 WCKB0#_0/DQMB_1
A26 D23 DQMA2 (85) P6 T3 DQMB2 (87)
F24 E22 DQMA3 (85) P5 T5 DQMB3 (87)
C24 C14 DQMA4 (86) R4 AE4 DQMB4 (88)
A24 A14 DQMA5 (86) T6 AF5 DQMB5 (88)
E24 E10 DQMA6 (86) T1 AK6 DQMB6 (88)
C22 D9 DQMA7 (86) U4 AK5 DQMB7 (88)
A22 V6
MDA26 DQA0_25/DQA_25 GDDR5/DDR2/GDDR3 MDB26 DQB0_25/DQB_25 GDDR5/DDR2/GDDR3
F22 C34 QSAP_0 (85) V1 F6 QSBP_0 (87)
MDA27 DQA0_26/DQA_26 EDCA0_0/QSA_0/RDQSA_0 MDB27 DQB0_26/DQB_26 EDCB0_0/QSB_0/RDQSB_0
D21 D29 QSAP_1 (85) V3 K3 QSBP_1 (87)
A20 D25 QSAP_2 (85) Y6 P3 QSBP_2 (87)
F20 E20 QSAP_3 (85) Y1 V5 QSBP_3 (87)
D19 E16 QSAP_4 (86) Y3 AB5 QSBP_4 (88)
(86) MDA[32..63] E18 E12 QSAP_5 (86) (88) MDB[32..63] Y5 AH1 QSBP_5 (88)
C18 J10 QSAP_6 (86) AA4 AJ9 QSBP_6 (88)
A18 D7 QSAP_7 (86) AB6 AM5 QSBP_7 (88)
F18 AB1
D17 A34 QSAN_0 (85) AB3 G7 QSBN_0 (87)
MDA36 DQA1_3/DQA_35 DDBIA0_0/QSA_0#/WDQSA_0 MDB36 DQB1_3/DQB_35 DDBIB0_0/QSB_0#/WDQSB_0
A16 E30 QSAN_1 (85) AD6 K1 QSBN_1 (87)
F16 E26 QSAN_2 (85) AD1 P1 QSBN_2 (87)
D15 C20 QSAN_3 (85) AD3 W4 QSBN_3 (87)
E14 C16 QSAN_4 (86) AD5 AC4 QSBN_4 (88)
F14 C12 QSAN_5 (86) AF1 AH3 QSBN_5 (88)
D13 J11 QSAN_6 (86) AF3 AJ8 QSBN_6 (88)
F12 F8 QSAN_7 (86) AF6 AM3 QSBN_7 (88)
A12 AG4
D11 J21 AH5 T7
MDA45 DQA1_12/DQA_44 ADBIA0/ODTA0 ODTA0 (85) MDB45 DQB1_12/DQB_44 ADBIB0/ODTB0 ODTB0 (87)
F10 G19 AH6 W7
MDA46 DQA1_13/DQA_45 ADBIA1/ODTA1 ODTA1 (86) MDB46 DQB1_13/DQB_45 ADBIB1/ODTB1 ODTB1 (88)
A10 AJ4
C10 H27 AK3 L9
MDA48 DQA1_15/DQA_47 CLKA0 CLKA0 (85) MDB48 DQB1_15/DQB_47 CLKB0 CLKB0 (87)
G13 G27 AF8 L8
MDA49 DQA1_16/DQA_48 CLKA0# CLKA0# (85) MDB49 DQB1_16/DQB_48 CLKB0# CLKB0# (87)
H13 AF9
J13 J14 AG8 AD8
MDA51 DQA1_18/DQA_50 CLKA1 CLKA1 (86) MDB51 DQB1_18/DQB_50 CLKB1 CLKB1 (88)
C H11 H14 AG7 AD7 C
MDA52 DQA1_19/DQA_51 CLKA1# CLKA1# (86) MDB52 DQB1_19/DQB_51 CLKB1# CLKB1# (88)
G10 AK9
G8 K23 AL7 T10
MDA54 DQA1_21/DQA_53 RASA0# RASA0# (85) MDB54 DQB1_21/DQB_53 RASB0# RASB0# (87)
K9 K19 AM8 Y10
MDA55 DQA1_22/DQA_54 RASA1# RASA1# (86) MDB55 DQB1_22/DQB_54 RASB1# RASB1# (88)
K10 AM7
G9 K20 AK1 W10
MDA57 DQA1_24/DQA_56 CASA0# CASA0# (85) MDB57 DQB1_24/DQB_56 CASB0# CASB0# (87)
A8 K17 AL4 AA10
MDA58 DQA1_25/DQA_57 CASA1# CASA1# (86) MDB58 DQB1_25/DQB_57 CASB1# CASB1# (88)
C8 AM6
E8 K24 AM1 P10
MDA60 DQA1_27/DQA_59 CSA0#_0 CSA0#_0 (85) MDB60 DQB1_27/DQB_59 CSB0#_0 CSB0#_0 (87)
A6
DQA1_28/DQA_60 CSA0#_1
K27 Reserved for JTAG AN4
DQB1_28/DQB_60 CSB0#_1
L10
MDA61 C6 MDB61 AP3
E6 M13 AP1 AD10
MDA63 DQA1_30/DQA_62 CSA1#_0 CSA1#_0 (86) MDB63 DQB1_30/DQB_62 CSB1#_0 CSB1#_0 (88)
A5 K16 AP5 AC10
DQA1_31/DQA_63 CSA1#_1 +3.3V_RUN_VGA DQB1_31/DQB_63 CSB1#_1
MVREFDA L18 K21 U10
MVREFSA MVREFDA CKEA0 CKEA0 (85) MVREFDB CKEB0 CKEB0 (87)
L20 J20 Y12 AA11
2
MVREFSA CKEA1 CKEA1 (86) MVREFSB MVREFDB CKEB1 CKEB1 (88) +1.5V_RUN
AA12
MEM_CALRN0 R8121 MVREFSB
L27 K26 N10
MEM_CALRN1 MEM_CALRN0 WEA0# WEA0# (85) WEB0# WEB0# (87)
N12 L15 10KR2J-3-GP AB11
1
MEM_CALRN2 AG12 MEM_CALRN1 WEA1# WEA1# (86) WEB1# WEB1# (88)
MEM_CALRN2 DIS_Mad ** R_MEM_3
MEM_CALRP1 M12 H23 MAA13 (85,86) 1 TEST_EN AD28 T8 MAB13 (87,88) DY R8102
MEM_CALRP0 MEM_CALRP1 MAA0_8 TESTEN MAB0_8 2K2R2J-2-GP
M27 J19 W8
MEM_CALRP2 MEM_CALRP0 MAA1_8 CLKTESTA AK10 MAB1_8
AH12 ** R_MEM_2
GDDR5
2
GDDR5
1
+1.5V_RUN MEM_CALRP2 CLKTESTB AL10 CLKTESTA DRAM_RST

AH11 1 2DIS_VRAMRST MEM_RST (85,86,87,88)
R8122 CLKTESTB DRAM_RST# R8103 0R2J-2-GP
DIS_Mad MEM_CALRN0
1
1 2 1KR2J-1-GP
2
1
1
243R2F-2-GP R8104
DIS_M96 RN8101
** R_MEM_1 R8105
10KR2J-3-GP
** C_MEM C8103
DIS_Park/Mad DIS_GPU SC2200P50V2KX-2GP
2
MEM_CALRN1
1 2 DIS_GPU SRN4K7J-8-GP
2
243R2F-2-GP R8106 MADISON-PRO-2-GP DIS_VRAMRST
DIS_M96
2
DIS_Mad MEM_CALRN2 MADISON-PRO-2-GP
1215-4 DIS_VRAMRST
1 2
3
4
243R2F-2-GP R8107
1218-2
DIS
R8110 1 2MEM_CALRP1
243R2F-2-GP
R8111 1
DIS_Mad
MEM_CALRP0
2
** This basic topology should be used for DRAM_RST for
DDR3/GDDR3/GDDR5.These Capacitors and Resistor values
243R2F-2-GP
are an example only. The Series R and || Cap values
B
DIS_Mad
MEM_CALRP2 will depend on the DRAM load and will have to be B
R8112 1 2
243R2F-2-GP calculated for different Memory ,DRAM Load and board
to pass Reset Signal Spec.
PLACE MVREF DIVIDERS AND CAPS CLOSE TO ASIC
1204-1
+1.5V_RUN +1.5V_RUN +1.5V_RUN +1.5V_RUN
1
Designator For Mannhatton For M96-M2

Ra R8113 Ra R8114 R8115 R8116
100R2F-L1-GP-U 100R2F-L1-GP-U Ra 100R2F-L1-GP-U Ra 100R2F-L1-GP-U
DIS_MEMVREF_M96/Mad DIS_MEMVREF_M96/Mad DIS_MEMVREF DIS_MEMVREF
R_MEM_1 68pF 10K
2
MVREFDA MVREFSA MVREFDB MVREFSB

X02-20091218
1
DIS_M96/Mad DIS_M96/Mad DIS DIS R_MEM_2 51R 0R/Short

R8117
DIS_M96/Mad C8104 R8118
DIS_M96/Mad C8105 DISR8119 C8106 DISR8120 C8107
Rb 100R2F-L1-GP-U Rb 100R2F-L1-GP-U Rb 100R2F-L1-GP-U Rb 100R2F-L1-GP-U
2
SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP R_MEM_3 DNI DNI

2
C_MEM 10K 2.2nF

x01 Change tolerant 20091117
DDR3/GDDR3 Memory Stuff Option(Mad/Park) DDR3/GDDR3 Memory Stuff Option(M96/M92)
GDDR5 GDDR3 DDR3 GDDR3 DDR3
MVDDQ 1.5V 1.8V/1.5V 1.5V MVDDQ 1.8V 1.5V
Ra 40.2R 40.2R 40.2R Ra 40.2R 100R
Rb 100R 100R 100R Rb 100R 100R

A A
<Core Design>
Wistron Corporation
Title
GPU_Memory(2/5)
A2 Berry A00
5 4 3 2 1
5 4 3 2 1
VGA1B 2 OF 8
MEMORY ID Table 10/8

DVPDATA[0:3] Description TXCAP_DPA3P
AU24 HDMI_PCH_CLK (57)
LVDS Interface 10/1
RN8203
AV23 HDMI_PCH_CLK# (57)
TXCAM_DPA3N
2 3
1000 DDR3 Hynix-H5TQ1G63BFR-12C (800MHz) TX0P_DPA2P
AT25 HDMI_PCH_DATA0 (57) 10/8 1 DIS 4
MUTI GFX AR24 VGA1G 7 OF 8
TX0M_DPA2N HDMI_PCH_DATA0# (57)
DPA SRN10KJ-5-GP
0000 DDR3 Samsung-K4W1G1646E-HC12 (800MHz) TX1P_DPA1P
AU26 HDMI_PCH_DATA1 (57)
AV25 HDMI_PCH_DATA1# (57)
TX1M_DPA1N LVDS CONTROL AK27 VGA_LBKLT_CTL (55)
VARY_BL
DVPDATA[0:3] Default:Pull down AR8
DVPCNTL_MVP_0 TX2P_DPA0P
AT27 HDMI_PCH_DATA2 (57) DIGON
AJ27 VGA_LCDVDD_EN (55)
MEM_ID Control AU8
AP8
DVPCNTL_MVP_1 TX2M_DPA0N
AR26 HDMI_PCH_DATA2# (57)
DVPCNTL_0
AW8 AR30
+1.8V_RUN_VGA DVPCNTL_1 TXCBP_DPB3P
VRAMDIS_Hynix AR3
AR1
DVPCNTL_2 TXCBM_DPB3N
AT29
AK35 GPU_LVDSB_TXC (55)
R8207 1 MEM_ID0 DVPCLK TXCLK_UP_DPF3P
D 2 10KR2J-3-GP AU1 AV31 AL36 GPU_LVDSB_TXC# (55) D
MEM_ID1 DVPDATA_0 TX3P_DPB2P TXCLK_UN_DPF3N
1 AU3 AU30
THERMTRIP_R
TP8224 MEM_ID2 AW3 DVPDATA_1 DPB TX3M_DPB2N

1 TPAD14-GP AJ38 GPU_LVDSB_TX0 (55)
TP8222 MEM_ID3 DVPDATA_2 TXOUT_U0P_DPF2P
1 TPAD14-GP AP6 AR32 AK37 GPU_LVDSB_TX0# (55)
THERMTRIP_VGA TP8223 TPAD14-GP DVPDATA_3 TX4P_DPB1P TXOUT_U0N_DPF2N
AW5 AT31
DVPDATA_4 TX4M_DPB1N
AU5 AH35 GPU_LVDSB_TX1 (55)
DVPDATA_5 TXOUT_U1P_DPF1P
AR6 AT33 AJ36 GPU_LVDSB_TX1# (55)
1
DVPDATA_6 TX5P_DPB0P TXOUT_U1N_DPF1N
THERMTRIP_VGA# (37) AW6 AU32
DVPDATA_7 TX5M_DPB0N
DY R8208 AU6
AT7
DVPDATA_8
AU14
TXOUT_U2P_DPF0P
AG38
AH37
GPU_LVDSB_TX2 (55)
GPU_LVDSB_TX2# (55)
6
10KR2J-3-GP DVPDATA_9 TXCCP_DPC3P TXOUT_U2N_DPF0N

AV7 AV13
D
DVPDATA_10 TXCCM_DPC3N
AN7 AF35
2
2N7002EDW-GP Q8202 DVPDATA_11 TXOUT_U3P

AV9 AT15 AG36
Q8203 DVPDATA_12 TX0P_DPC2P TXOUT_U3N
AT9 AR14
DVPDATA_13 TX0M_DPC2N
G AR10
84.27002.F3F DIS
1
DVPDATA_14 DPC LVTMDP

DIS 2N7002A-7-GP AW10
AU10
DVPDATA_15 TX1P_DPC1P
AU16
AV15
DVPDATA_16 TX1M_DPC1N JTAG_TCK_VGA
AP10 2 1 R8219 AP34
DY GPU_LVDSA_TXC (55)
S
DVPDATA_17 10KR2J-3-GP TXCLK_LP_DPE3P
AV11 AT17 AR34 GPU_LVDSA_TXC# (55)
DVPDATA_18 TX2P_DPC0P TXCLK_LN_DPE3N
(10,21,37,39,42) H_THERMTRIP# AT11
AR12
DVPDATA_19 TX2M_DPC0N
AR16 10/5 AW37
DVPDATA_20 TXOUT_L0P_DPE2P GPU_LVDSA_TX0 (55)
+3.3V_RUN_VGA AW12 AU20 AU35 GPU_LVDSA_TX0# (55)
DVPDATA_21 TXCDP_DPD3P TXOUT_L0N_DPE2N
(37) THERMTRIP_VGA_GATE 10/1 AU12
AP12
DVPDATA_22 TXCDM_DPD3N
AT19
AR37
DVPDATA_23 TXOUT_L1P_DPE1P GPU_LVDSA_TX1 (55)
10/5 AT21 AU39 GPU_LVDSA_TX1# (55)
2
1
TX3P_DPD2P TXOUT_L1N_DPE1N
AR20
RN8201 TX3M_DPD2N
AP35 GPU_LVDSA_TX2 (55)
R8202 1 VGA_BLEN DPD TXOUT_L2P_DPE0P
DIS 2 10KR2J-3-GP AU22 AR35
SRN4K7J-8-GP
DIS TX4P_DPD1P
AV21
TXOUT_L2N_DPE0N GPU_LVDSA_TX2# (55)
R8201 1 JTAG_TRST#_VGA TX4M_DPD1N
DIS 2 10KR2J-3-GP AN36
TXOUT_L3P
RN
I2C AT23 AP37
3
4
TX5P_DPD0P TXOUT_L3N
DDC channel for LVDS 0R4P2R-PAD TX5M_DPD0N
AR22
(55) GPU_LVDS_CLK 4 1 GPU_LVDS_CLK_C AK26
SCL
(55) GPU_LVDS_DATA 3 2 GPU_LVDS_DATA_C AJ26
RN8202 SDA
Straps DIS AD39 MADISON-PRO-2-GP
GENERAL PURPOSE I/O R VGA_CRT_RED (77)
AD37
R#
(80) TX_PWRS_ENB AH20
GPIO_0
(80) TX_DEEMPH_EN AH18 AE36 VGA_CRT_GREEN (77)
GPIO_1 G
(80) BIF_GEN2_EN_A AN16 AD35
GPIO_2 G#
AH23
GPIO_3_SMBDATA
C
+3.3V_RUN_VGA
AJ23
AH17
GPIO_4_SMBCLK B
AF37
AE38 +3.3V tolerant
VGA_CRT_BLUE (77) 10/1 C
(80) GPIO5_AC_BATT GPIO_5_AC_BATT B#
TP8207 1 TPAD14-GP GPIO6_VGA AJ17 DAC1 RN8204
GPIO_6 VGA_CRT_RED
(55) VGA_BLEN AK17 AC36 VGA_CRT_HSYNC (77,80) 1 8
2
GPIO_7_BLON HSYNC VGA_CRT_GREEN 2

AJ13 AC38 7
R8205
(80) GPIO8_ROMSO
(80) VGA_DIS AH15
GPIO_8_ROMSO VSYNC VGA_CRT_VSYNC (77,80) VGA_CRT_BLUE 3
DIS 6
GPIO_9_ROMSI
DIS 10KR2J-3-GP
AJ16
GPIO_10_ROMSCK GPU_RSET
DIS 4 5
(80) CONFIG0 AK16 AB34 1 2
GPIO_11 RSET R8214 499R2F-2-GP SRN150F-1-GP
(80) CONFIG1 AL16
1
GPIO_12
(80) CONFIG2 AM16 AD34 AVDD
JTAG_TMS_VGA TP8208 TPAD14-GP VPIO14_VGA GPIO_13 AVDD +1.8V_RUN_VGA
1 AM14 AE34
GPIO_14_HPD2 AVSSQ AVDD
(89) PWRCNTL_0 AM13
GPIO_15_PWRCNTL_0 (1.8V@70mA AVDD For M96)
1 TPAD14-GP GPIO16_SSIN AK14 AC33 L8202 DIS (1.8V@70mA AVDD For Madison)
GPIO_16_SSIN VDD1DI VDD1DI
TP8203
0107-5 AG30 AC34 1 2
SCD1U10V2KX-5GP
TPAD14-GP GPIO18_VGA GPIO_17_THERMAL_INT VSS1DI BLM15BD121SS1D-GP
1 AN14
GPIO_18_HPD3
1
TP8209 THERMTRIP_VGA AM17 120ohm, 0.3A C8203 C8204
GPIO_19_CTF C8201
(89) PWRCNTL_1 AL13
GPIO_20_PWRCNTL_1 R2
AC30
SC4D7U6D3V3KX-GP
DIS DIS DISSC1U6D3V2KX-GP
(80) GPIO21_BB_EN AJ14 AC31
2
GPIO_21_BB_EN R2#
(80) BIOS_ROM_EN AK13
TP8225 TPAD14-GP PEG_CLKREQ# GPIO_22_ROMCS#
1 AN13 AD30
JTAG_TRST#_VGA GPIO_23_CLKREQ# G2
AM23 AD31
R8204 TP8202 TPAD14-GP JTAG_TDI_VGA JTAG_TRST# G2#
Madison Only 1
JTAG_TCK_VGA
AN23
JTAG_TDI
(1.8V@45mA VDD1DI For M96) VDD1DI
JTAG SIGNAL OPTION (7) CLK_VGA_27M_SS 1 DIS 2
JTAG_TMS_VGA
AK23
AL24
JTAG_TCK B2
AF30
AF31 L8203 DIS (1.8V@45mA VDD1DI For Madison)
JTAG_TDO_VGA JTAG_TMS B2#
Normal Debug 1215-5 0R2J-2-GP TP8205 1 TPAD14-GP AM24
JTAG_TDO
1 2
Signal TP8206 1 TPAD14-GP GEN_A AJ19 BLM15BD121SS1D-GP
mode mode
1
TP8211 TPAD14-GP GEN_B GENERICA 120ohm, 0.3A C8206 C8207
1 DY
2 1 AK19 AC32
SC1U6D3V2KX-GP
C8229 SCD1U10V2KX-5GP TP8218 TPAD14-GP GENERICC GENERICB C C8202 SCD1U10V2KX-5GP
1
GENERICD
AJ20
GENERICC Y
AD32 DIS DIS
TESTEN "1"(PU) "1"(PU) 10/7 TP8219 1 TPAD14-GP AK20 AF32 SC4D7U6D3V3KX-GP DIS
2
TP8212 TPAD14-GP GENERICE_HPD4 GENERICD COMP
1 AJ24
TP8220 TPAD14-GP GENERICF GENERICE_HPD4 DAC2
1 AH26
GENERICG GENERICF
JTAG_TRST# "0"(PD) "1"(PU) TP8221 1 TPAD14-GP AH24
GENERICG H2SYNC
AD29 HSYNC_DAC2 (80)
AC29 VSYNC_DAC2 (80)
V2SYNC
JTAG_TCK CLK "1"(PU) +1.8V_RUN_VGA
(13,57) HDMI_HPD_DET AK24
HPD1 (1.8V@40mA VDD2DI For M96)
VDD2DI
AG31 (1.8V@50mA VDD2DI For Madison) +1.8V_RUN_VGA
AG32
VSS2DI
1
JTAG_TMS "1"(PU) "1"(PU)

R8216 PLACE VREFG DIVIDER AND CAP (3.3V@65mA A2VDD For M96)
DIS 499R2F-2-GP AG33 (3.3V@130mA A2VDD For Madison)
CLOSE TO ASIC A2VDD +3.3V_RUN_VGA
B AD33 B
A2VDDQ
2
GPU_VREFG A2VDDQ
AH13
VREFG
AF33
1
C8217 A2VSSQ
1
SCD1U10V2KX-5GP
R8217 DPLL_PVDD DIS A2VDDQ

249R2F-GP R2SET (1.8V@20mA A2VDDQ For M96)
DIS DIS R2SET
AA29 1
R8218
2
715R2F-GP
AM32
DIS (1.8V@1.5mA A2VDDQ For Madison)
2
DPLL_PVDD
AN32 1 2
2
DPLL_VDDC DPLL_PVSS R8203 0R3J-0-U-GP
SC1U6D3V2KX-GP
1
1
DDC/AUX AM26 C8212 C8213
DDC1CLK VGA_CRT_DDCCLK (77)
11/6 AN31
DPLL_VDDC DDC1DATA
AN26 VGA_CRT_DDCDATA (77) DDC channel for CRT DY DY
+1.8V_RUN_VGA DPLL_PVDD SCD1U10V2KX-5GP
1215-5 1113-3
2
(1.8V@120mA DPLL_PVDD For M96) 80D6R2F-L-GP AM27
L8201 XTALIN PLL/CLOCK AUX1P
DIS (1.8V@75mA DPLL_PVDD For Madison) 1 R8211 2 AV33 AL27
(7) CLK_VGA_27M_NSS DIS XTALIN AUX1N
SCD1U10V2KX-5GP
C8230
1 2 XTALOUT AU34
2
BLM18PG471SN1D-GP C8219 R8220 2 XTALOUT

1 AM19
DIS DDC2CLK GPU_HDMI_CLK (57)
1
1
SCD1U10V2KX-5GP
470ohm, 1A C8218 150R2F-1-GP AL19 DDC channel for HDMI

SC1U6D3V2KX-GP
GPU_HDMI_DATA (57)
1
C8205 R8221 1 XO_IN XO_IN DDC2DATA

DY DIS 2 DY 2 1 AW34
1
SC4D7U6D3V3KX-GP 0R2J-2-GP R8210 0R2J-2-GP XO_IN

DIS DIS DY AN20
2
AUX2P
AW35 AM20
2
XO_IN2 AUX2N
1204-2
(39) VGA_THERMDA 1204-2 DDCCLK_AUX3P
AL30
AM30
DDC1/DDC2/DDC6 have 5V-tolerant
1
C8226 DDCDATA_AUX3N
SC470P50V2JN-GP AL29
DDCCLK_AUX4P
AF29 AM29
DY
2
+1.0V_RUN_VGA DPLL_VDDC DPLUS THERMAL DDCDATA_AUX4N

(1.1V@150mA DPLL_VDDC For M96) (39) VGA_THERMDC AG29
DMINUS
DIS (1.0V@125mA DPLL_VDDC For Madison) DDCCLK_AUX5P
AN21
1 2 AM21
DDCDATA_AUX5N
SCD1U10V2KX-5GP
L8207 BLM18PG471SN1D-GP TP8214 1 TPAD14-GP FAN_PWM AK32

SC1U6D3V2KX-GP
TS_FDO
470ohm, 1A C8222 AJ30
DDC6CLK
1
C8221 AL31 AJ31

C8220 TSVDD TS_A DDC6DATA
SC4D7U6D3V3KX-GP
DY DIS DIS
AK30
2
DDCCLK_AUX7P
AJ32 AK29
TSVDD DDCDATA_AUX7N
AJ33
TSVSS
DIS_GPU
MADISON-PRO-2-GP
A A
+1.8V_RUN_VGA (1.8V@20mA TSVDD For M96) TSVDD

L8204 DIS (1.8V@5mA TSVDD For Madison) X8201 <Core Design>
1 2 C8227
BLM15BD121SS1D-GP
120ohm, 0.3A 2 1 XTALIN 1 4
Wistron Corporation
1
DIS C8225
C8223 DY C8224 DIS SCD1U10V2KX-5GP DY Clock Input Configuraiton -GDDR3/DDR3 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
SC1U6D3V2KX-GP SC18P50V2JN-1-GP C8228
SC4D7U6D3V3KX-GP
DY Taipei Hsien 221, Taiwan, R.O.C.
2
2 3 XTALOUT 1 2 a) 27MHz crystal connected to XTALIN or XTALOUT or

DY b) 27MHz (1.8V) oscillator connected to XTALIN or Title
XTAL-27MHZ-85-GP SC18P50V2JN-1-GP
c) 27MHz (3.3V) oscillator connected to XO_IN (Park, Madison, and Broadway only) GPU_DP/LVDS/CRT/GPIO(3/5)
1
R8222 DY21MR2J-1-GP A2
Berry A00
1218-1
5 4 3 2 1
5 4 3 2 1
VGA1E
10/8 5 OF 8 +1.8V_RUN_VGA
+1.5V_RUN (1.5V@2.9A VDDR1 For M96) MEM I/O (1.8V@210mA PCIE_VDDR For M96)
For DDR3/GDDR5, MVDDQ = 1.5V (1.5V@3.4A VDDR1 For Madison) PCIE (1.8V@400mA PCIE_VDDR For Madion)
AC7 AA31
VDDR1 PCIE_VDDR
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
AD11 AA32
SC1U6D3V2KX-GP
1
1
C8301 C8304 C8305 C8306 C8307 C8308 C8309 C8310 C8311 C8312 VDDR1 PCIE_VDDR C8313 C8314 C8315 C8316 C8317
AF7 AA33
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
VDDR1 PCIE_VDDR SC4D7U6D3V3KX-GP
DIS DIS DIS DIS DIS DIS DIS DIS DIS AG10
VDDR1 PCIE_VDDR
AA34 DIS
DY AJ7 V28
DY DIS DY DIS
2
VDDR1 PCIE_VDDR
AK8 W29
VDDR1 PCIE_VDDR
AL9 W30
VDDR1 PCIE_VDDR +1.0V_RUN_VGA
G11 Y31
VDDR1 PCIE_VDDR
G14
VDDR1
(1.1V@1.4A PCIE_VDDC For M96)
G17
VDDR1 (1.0V@1.1A PCIE_VDDC For Madison)
G20 G30
1
C8318 C8319 C8320 C8321 C8322 C8323 C8324 C8325 C8326 C8327 VDDR1 PCIE_VDDC
G23 G31
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
1
VDDR1 PCIE_VDDC C8328 C8329 C8330 C8331 C8332 C8333 C8302 C8334
G26 H29
SC1U6D3V2KX-GP
D D
VDDR1 PCIE_VDDC SC4D7U6D3V3KX-GP
DY DY DIS DY DIS DY DY DY DY DY G29 H30 DIS
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
2
2
VDDR1 PCIE_VDDC
H10 J29
DIS
SC1U6D3V2KX-GP
2
2
VDDR1 PCIE_VDDC
J7
J9
VDDR1 PCIE_VDDC
J30
L28
DIS DIS DIS DIS DIS DIS
VDDR1 PCIE_VDDC
K11 M28
VDDR1 PCIE_VDDC
K13 N28
VDDR1 PCIE_VDDC
K8 R28
VDDR1 PCIE_VDDC
L12 T28
VDDR1 PCIE_VDDC
L16 U28
1
C8303 C8335 VDDR1 PCIE_VDDC +VGA_CORE
L21
VDDR1 (25A VDDC For M96)
L23 (23.6A VDDC For Madison)
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
VDDR1
L26 AA15
2
VDDR1 CORE VDDC
DIS DIS L7 AA17
1
VDDR1 VDDC C8336 C8337 C8338 C8339 C8340 C8341 C8342 C8343 C8344 C8345
M11 AA20
SC1U6D3V2KX-GP
VDDR1 VDDC SC1U6D3V2KX-GP
N11 AA22
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
VDDR1 VDDC
P7 AA24
DIS DIS DY DY DIS DIS DIS DIS DIS DIS
2
VDDR1 VDDC
R11 AA27
VDDR1 VDDC
U11 AB16
VDDR1 VDDC
U7 AB18
VDDR1 VDDC
Y11 AB21
VDDR1 VDDC
Y7 AB23
VDDR1 VDDC
AB26
+1.8V_RUN_VGA VDDC
AB28
1
VDDC C8346 C8347 C8348 C8349 C8350
AC17
VDDC SC1U6D3V2KX-GP
AC20
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
VDDC_CT LEVEL VDDC
(1.8V@136mA VDD_CT For M96) AC22
DIS DIS DIS DIS DIS
2
TRANSLATION VDDC
DIS (1.8V@17mA VDD_CT For Madison) VDDC
AC24
POWER
1 2 AF26 AC27
VDD_CT VDDC
SCD1U10V2KX-5GP
L8301 BLM15BD121SS1D-GP AF27 AD18
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC4D7U6D3V3KX-GP
1
VDD_CT VDDC
120ohm, 0.3A C8351 C8352 C8353 C8354 C8355 AG26 AD21
VDD_CT VDDC
DIS DIS DIS DIS AG27
VDD_CT VDDC
AD23
AD26
10/6
DIS
2
2
VDDC
AF17
I/O VDDC
AF20
1
+3.3V_RUN_VGA VDDC C8356 C8357 C8358 C8359 C8360 C8361 C8362 C8363 C8364 C8365
AF23 AF22
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
VDDR3 VDDC
AF24 AG16
VDDR3 VDDC
AG23 AG18
DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS
2
VDDR3 VDDC
(3.3V@60mA VDDR3) AG24 AG21
SC4D7U6D3V3KX-GP
1
C8366 C8367 C8368 C8369 VDDR3 VDDC
AH22
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
VDDC
DIS VDDC
AH27
C AF13 AH28 C
2
2
VDDR4 VDDC
DIS DIS DIS AF15
VDDR4 VDDC
M26
AG13 N24
VDDR4 VDDC
AG15 N27
VDDR4 VDDC/BIF_VDDC
R18
VDDC
1
R21 C8370 C8371 C8372 C8373
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
VDDC
AD12 R23
VDDR4 VDDC
(1.8V@340mA VDDR4 For M96) AF11 R26
DIS DIS DIS DIS
2
VDDR4 VDDC
(1.8V@170mA VDDR4 For Madison) AF12
VDDR4 VDDC
T17
AG11 T20
VDDR4 VDDC
1204-5 VDDC
T22
SCD1U10V2KX-5GP
T24
VDDC
1
C8374 C8375 +1.5V_RUN T27

SC1U6D3V2KX-GP VDDC/BIF_VDDC
DIS DIS_M96 VDDRH VDDC
U16
1 2 DIS_M96 M20 U18
SC1U6D3V2KX-GP
2
NC_VDDRHA VDDC
L8306 BLM15BD121SS1D-GP 2VSSRHA
DIS 120ohm, 0.3A
1
R8302 0R2J-2-GP
M21
NC_VSSRHA VDDC
U21
U23
VDDC
C8397 1 U26
VDDC
DIS_M96 V12 V17
DIS_M96 1 2VSSRHB U12
NC_VDDRHB VDDC
V20 VDDCI and VDDC should have seperate regulators with a merge option on PCB
2
R8301 0R2J-2-GP NC_VSSRHB VDDC

V22
VDDC
V24
PCIE_PVDD
VDDC
VDDC
V27 For Madison and Park, VDDCI and VDDC can share one common regulator
(1.8V@68mA PCIE_PVDD For M96) VDDC
Y16
(1.8V@40mA PCIE_PVDD For Madison) PLL Y18
1
DIS 2 AB37
VDDC
Y21
PCIE_PVDD VDDC
SCD1U10V2KX-5GP
L8302 BLM15BD121SS1D-GP MPV18 Y23

VDDC
1
120ohm, 0.3A C8377 C8378 H7 Y26

SC1U6D3V2KX-GP
C8376 MPV18 VDDC

H8 Y28
SPV18 MPV18 VDDC
DIS DIS DIS
2
SC4D7U6D3V3KX-GP +VGA_CORE
+1.0V_RUN_VGA SPV10 (VDDC@136mA SPV10 For M96) AM10 (Same as VDDC)
L8303 SPV18
(1.0V@100mA SPV10 For Madison) VDDCI
AA13
1 DIS_Mad
2 AN9
SPV10 VDDCI
AB13
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
BLM18PG471SN1D-GP AC12
SC1U6D3V2KX-GP
SC4D7U6D3V3KX-GP
VDDCI
1
1
C8379 C8380 C8381 AN10 AC15 C8382 C8383 C8384 C8385 C8386 C8387 C8388
+VGA_CORE SPVSS VDDCI SC1U6D3V2KX-GP SC10U6D3V5KX-1GP
(For M96 SPV10 = VDDC) DIS DIS DIS AD13 DIS DIS
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
L8307 VDDCI
(For M97, Broadway, Madison and Park SPV10 = 1.0V) AD16
DIS DIS DIS DIS
2
2
VDDCI
1 DIS_M96
2
BLM18PG471SN1D-GP VDDCI
M15
DIS
M16
VOLTAGE VDDCI
B
1204-5 SENESE VDDCI
M18
M23 B
VDDCI
N13
VDDCI
M97, Broadway, Madison and Park only 0107-5 AF28
FB_VDDC VDDCI
N15
M96 do not support core vsense feature Removed VDDCI
N17
N20
VDDCI
AG28 N22
FB_VDDCI ISOLATED VDDCI
R12
CORE I/O VDDCI
1204-5 DIS_M96
1 2FB_GND AH29
VDDCI
R13
R16
R8303 0R2J-2-GP FB_GND VDDCI
T12
VDDCI
T15
VDDCI
VCORE_SEN/RTN and VDDCI_SEN/RTN route as differetial pair VDDCI
V15
Y13
VDDCI
1204-4
MADISON-PRO-2-GP
SPV18
DIS_Mad (1.8V@50mA SPV18)
SCD1U10V2KX-5GP
1 2
1
L8304 BLM15BD121SS1D-GP C8391

120ohm, 0.3A C8389 DIS_Mad C8390 DIS_Mad
SC1U6D3V2KX-GP
DIS_Mad
2
SC4D7U6D3V3KX-GP
NOTE1:
Back Bias is not supported on M97, Broadway, Madison and Park
For the M96 Back Bias circuitry, refer to REF134
NOTE2:
FB_VDDC, FB_VDDCI and FB_GND are not support on M96
MPV18
DIS_Mad (1.8V@150mA MPV18) NOTE3:
1 2
SCD1U10V2KX-5GP
L8305 BLM18PG471SN1D-GP
M97 VDDC and VDDCI ball assignments are different from M96.
1
A A
470ohm, 1A C8393 C8396
C8392 DIS_Mad DIS_Mad If M96 is populated on this design, VDDC and VDDCI will be shorted on the substrate.
DIS_Mad
SC1U6D3V2KX-GP
2
SC4D7U6D3V3KX-GP
NOTE4:
<Core Design>
For M2 design compatibility, refer to the document AN_M96_Ax and AN_M97_Ax
Wistron Corporation
Title
GPU_POWER(4/5)
A2
Berry A00
5 4 3 2 1
5 4 3 2 1
VGA1F
10/8 6 OF 8
VGA1H
10/8 8 OF 8
AB39 A3 DPA_VDD18
PCIE_VSS GND DPD_VDD18 DP C/D POWER DP A/B POWER
E39 A37
PCIE_VSS GND
F34
PCIE_VSS GND
AA16 (1.8V@130mA DPC_VDD18) 1204-4
F39 AA18 AP20 AN24
PCIE_VSS GND +1.0V_RUN_VGA DPC_VDD18 DPA_VDD18
G33 AA2 AP21 AP24
PCIE_VSS GND DPC_VDD18 DPA_VDD18 +1.0V_RUN_VGA
G34
PCIE_VSS GND
AA21 DNI for M96/M92
H31 AA23 (1.1V@200mA DPC_VDD10 For M96) DPA_VDD10 (1.1V@200mA DPA_VDD10 For M96)
PCIE_VSS GND
H34
PCIE_VSS GND
AA26 (1.0V@110mA DPC_VDD10 For Madison) (1.0V@110mA DPA_VDD10 For Madison) DIS
H39 AA28 AP13 AP31 1 2 +1.8V_RUN_VGA DPA_VDD18
SCD1U10V2KX-5GP
1
1
PCIE_VSS GND DPC_VDD10 DPA_VDD10 C8402 L8403 BLM15BD121SS1D-GP
J31 AA6 AT13 AP32
PCIE_VSS GND DPC_VDD10 DPA_VDD10
J34 AB12 DIS C8403 C8405 120ohm, 0.3A
SC1U6D3V2KX-GP
PCIE_VSS GND SC10U6D3V5KX-1GP
K31 AB15 DIS DIS DIS_Mad (1.8V@130mA DPA_VDD18)
2
PCIE_VSS GND
K34 AB17 AN17 AN27 1 2
PCIE_VSS GND DPC_VSSR DPA_VSSR L8402 BLM15BD121SS1D-GP
K39 AB20 AP16 AP27
1
PCIE_VSS GND DPC_VSSR DPA_VSSR 120ohm, 0.3A C8407 C8408
L31 AB22 AP17 AP28
SC1U6D3V2KX-GP
D D
PCIE_VSS GND DPC_VSSR DPA_VSSR C8406
L34
PCIE_VSS GND
AB24 AW14
DPC_VSSR DPA_VSSR
AW24
SC4D7U6D3V3KX-GP
DIS_Mad DIS_Mad
SCD1U10V2KX-5GP
M34 AB27 AW16 AW26 DIS_Mad
2
PCIE_VSS GND DPC_VSSR DPA_VSSR
M39 AC11
PCIE_VSS GND DPD_VDD18 DPB_VDD18
N31 AC13
PCIE_VSS GND DPB_VDD18
N34 AC16
PCIE_VSS GND +1.0V_RUN_VGA
P31 AC18 AP22 AP25
PCIE_VSS GND DPD_VDD18 DPB_VDD18
P34 AC2 AP23 AP26
PCIE_VSS GND DPD_VDD18 DPB_VDD18 +1.0V_RUN_VGA
P39
PCIE_VSS GND
AC21 DIS_Mad (1.8V@130mA DPB_VDD18)
R34
PCIE_VSS GND
AC23 (1.1V@200mA DPD_VDD10 For M96) 1 2
T31 AC26 (1.0V@110mA DPD_VDD10 For Madison) (1.1V@200mA DPB_VDD10 For M96) R8402 0R2J-2-GP
PCIE_VSS GND
1
T34 AC28 AP14 AN33 (1.0V@110mA DPB_VDD10 For Madison) DY C8410 C8411
SC1U6D3V2KX-GP
PCIE_VSS GND DPD_VDD10 DPB_VDD10 C8409
T39
PCIE_VSS GND
AC6 AP15
DPD_VDD10 DPB_VDD10
AP33
SC4D7U6D3V3KX-GP
DIS_Mad
SCD1U10V2KX-5GP
U31 AD15 DIS_Mad
2
PCIE_VSS GND
U34 AD17
PCIE_VSS GND
V34 AD20
PCIE_VSS GND
V39 AD22 AN19 AN29
PCIE_VSS GND DPD_VSSR DPB_VSSR
W31 AD24 AP18 AP29
W34 AD27 AP19 AP30
Y34 AD9 AW20 AW30
PCIE_VSS GND DPD_VSSR DPB_VSSR +1.8V_RUN_VGA
Y39 AE2 AW22 AW32
PCIE_VSS GND DPD_VSSR DPB_VSSR DPA_PVDD
GND
AE6 (1.8V@20mA DPA_PVDD For M96)
AF10 (1.8V@20mA DPA_PVDD For Madison)
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
GND R8401 DIS R8404
AF16 1 2
GND
AF18 1 2DPCD_CALR AW18 AW28DPAB_CALR1 2 L8404 BLM15BD121SS1D-GP
DIS0.3A
1
GND +1.8V_RUN_VGA LVDS mode 150R2F-1-GP DPCD_CALR DPAB_CALR 150R2F-1-GP C8412 120ohm,
AF21
GND GND
1
AG17 (1.8V@200mA DPE_VDD18 For M96) DPE_VDD18 DIS DIS C8413
GND L8401 C8414
F15 AG2 DIS (1.8V@200mA DPE_VDD18 For Madison) DP E/F POWER DP PLL POWER DIS DIS
2
GND GND SC4D7U6D3V3KX-GP DPD_VDD18
F17 AG20 1 2 AH34 AU28
SC1U6D3V2KX-GP
2
GND GND BLM18PG471SN1D-GP DPE_VDD18 DPA_PVDD
F19 AG22 AJ34 AV27
2
GND GND 470ohm, 1A C8401 C8418 C8419 DPE_VDD18 DPA_PVSS
F21 AG6
GND GND SC4D7U6D3V3KX-GP
F23
GND GND
AG9 DIS DIS DIS (1.8V@20mA DPB_PVDD For M96) DIS_Mad (1.8V@130mA DPD_VDD18)
F25 AH21 SCD1U10V2KX-5GP (1.8V@20mA DPB_PVDD For Madison) 1 2
1
GND GND R8405 0R2J-2-GP
F27 AJ10 AL33 AV29
2
GND GND DPE_VDD10 DPE_VDD10 DPB_PVDD C8421
F29 AJ11 AM33 AR28 DY
SC1U6D3V2KX-GP
GND GND DPE_VDD10 DPB_PVSS C8415 C8422
F31 AJ2
GND GND LVDS mode SC4D7U6D3V3KX-GP SCD1U10V2KX-5GP
F33 AJ28 (1.8V@20mA DPC_PVDD For M96) DIS_Mad
1
GND GND +1.0V_RUN_VGA
F7
GND GND
AJ6 (1.1V@100mA DPE_VDD10 For M96) (1.8V@20mA DPC_PVDD For Madison) DIS_Mad
F9
GND GND
AK11
DIS (1.0V@120mA DPE_VDD10 For Madison) AN34
DPE_VSSR DPC_PVDD
AU18
G2 AK31 1 2 AP39 AV17
GND GND L8408 BLM15BD121SS1D-GP DPE_VSSR DPC_PVSS
G6 AK7 AR39
SC1U6D3V2KX-GP
GND GND DPE_VSSR
1
C H9 AL11 120ohm, 0.3A C8404 C8424 AU37 (1.8V@20mA DPD_PVDD For M96) C
GND GND SC4D7U6D3V3KX-GP DIS C8425 DPE_VSSR
J2
GND GND
AL14 DIS DIS (1.8V@20mA DPD_PVDD For Madison)
J27 AL17 SCD1U10V2KX-5GP AV19
2
GND GND DPD_PVDD
J6 AL2 AR18
GND GND DPD_PVSS
J8 AL20
GND GND
K14
GND GND/PX_EN
AL21 AF34
DPF_VDD18 (1.8V@20mA DPE_PVDD For M96) DPE_PVDD
K7 AL23 DPF_VDD18 AG34 (1.8V@20mA DPE_PVDD For Madison)
GND GND LVDS mode DPF_VDD18
L11 AL26 AM37
GND GND +1.8V_RUN_VGA DPE_PVDD
L17
GND GND
AL32 (1.8V@200mA DPF_VDD18 For M96) DPE_PVSS
AN38
L2 AL6 L8405 DIS (1.8V@200mA DPF_VDD18 For Madison)
GND GND
L22 AL8 1 2 AK33
SC1U6D3V2KX-GP
GND GND BLM18PG471SN1D-GP DPF_VDD10
L24
GND GND
AM11 AK34
DPF_VDD10 DIS_Park/Mad (1.8V@20mA DPF_PVDD) DIS
1
2
L6 AM31 470ohm, 1A C8423 C8427 AL38 DPF_PVDD 1 2 1 2
GND GND SC4D7U6D3V3KX-GP C8428 DPF_PVDD R8407 0R2J-2-GP L8406 BLM15BD121SS1D-GP
M17 AM9 DIS DIS AM35
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SC4D7U6D3V3KX-GP
1
1
GND GND DPF_PVSS C8429 C8430 C8416 120ohm, 0.3A
M22 AN11 DIS SCD1U10V2KX-5GP
2
1
GND GND
M24 AN2 AF39
GND GND DPF_VSSR
N16 AN30 AH39 DIS_Park/Mad DIS
2
GND GND DPF_VDD10 DPF_VSSR DPF_PVSS
N18
GND GND
AN6 AK39
DPF_VSSR
1 2 DIS DIS
N2 AN8 AL34 R8408 0R2J-2-GP
GND GND DPF_VSSR
N21 AP11 AM34
GND GND LVDS mode DPF_VSSR
N23 AP7
GND GND +1.0V_RUN_VGA
N26
GND GND
AP9 (1.1V@100mA DPF_VDD10 For M96) 1204-2
N6
GND GND
AR5
DIS (1.0V@120mA DPF_VDD10 For Madison)
R15 B11 1 2 AM39
GND GND L8407 BLM15BD121SS1D-GP DPEF_CALR
R17 B13 DIS_GPU
2DPEF_CALR
GND GND
1
1
R2 B15 120ohm, 0.3A C8426 C8433 C8434
GND GND
SCD1U10V2KX-5GP
R20 B17 SC4D7U6D3V3KX-GP DIS DIS DIS MADISON-PRO-2-GP
SC1U6D3V2KX-GP
GND GND
R22 B19
2
2
GND GND
R24 B21
GND GND
R27 B23
GND GND
R6 B25
GND GND R8406
T11 B27
GND GND 150R2F-1-GP
T13
GND GND
B29 DIS
T16 B31
GND GND
T18 B33
1
GND GND
T21 B7
GND GND
T23 B9
GND GND
T26 C1
GND GND
U15 C39
GND GND
U17 E35
GND GND
U2 E5
B GND GND B
U20
GND GND
F11 For M97/M96, DPF_VDD18 can be shared with DPE_VDD18
U22 F13
GND GND
U24
GND For M97/M96, DPF_VDD10 can be shared with DPE_VDD10
U27
GND
U6
GND
V11
GND
V16
GND
For dual link DVI using DPA AND DPB, DPA_VDDxx and DPB_VDDxx can be shared respectively
V18
GND
V21
GND
V23
GND
For dual link DVI using DPC AND DPD, DPC_VDDxx and DPD_VDDxx can be shared respectively
V26
GND
W2
GND
W6
GND For dual link LVDS, DPE_VDDxx and DPF_VDDxx can be shared respectively
Y15
GND
Y17
GND
Y20
GND
Y22 A39 VSS_MECH1 TPAD14-GP1 TP8401
GND VSS_MECH
Y24 AW1 VSS_MECH2 TPAD14-GP1 TP8402
GND VSS_MECH
Y27 AW39VSS_MECH3 TPAD14-GP1 TP8403
GND VSS_MECH
U13
GND
V13
GND DIS_GPU
MADISON-PRO-2-GP
A A
<Core Design>
Wistron Corporation
Title
GPU_DPPWR/GND(5/5)
A2 Berry A00
5 4 3 2 1
5 4 3 2 1
+1.5V_RUN +1.5V_RUN
VRAM1 VRAM2
1.5V, 350mA MDA[0..31] (81) 1.5V, 350mA MDA[0..31] (81)
K8 E3 MDA3 K8 E3 MDA29
VDD DQL0 MDA7 VDD DQL0 MDA24
K2 F7 K2 F7
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
C8508
C8507
C8510
C8509
C8512
C8511
C8514
C8513
C8525
C8524
C8516
C8515
C8518
C8517
C8519
C8520
N1 VDD DQL2 F2 N1 VDD DQL2 F2
1
1
R9 F8 MDA6 R9 F8 MDA26
B2 VDD DQL4 H3 B2 VDD DQL4 H3
DIS_M96/MadDIS_M96/Mad MDA4 DIS_M96/Mad DIS_M96/Mad MDA27
D
DY DY D9 H8
DY DY DY D9 H8 D
2
2
DIS_M96/MadDIS_M96/Mad DY DY G7 VDD DQL6 G2
MDA5
DIS_M96/Mad DIS_M96/Mad DY G7 VDD DQL6 G2
MDA31
R1 VDD DQL7 H7 R1 VDD DQL7 H7
N9 VDD N9 VDD
D7 MDA20 D7 MDA8
DQU0 MDA19 DQU0 MDA14
A8 VDDQ DQU1 C3 A8 VDDQ DQU1 C3
A1 C8 MDA23 A1 C8 MDA9
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
C8502 C8505 VDDQ DQU2 MDA18 C8521 C8522 VDDQ DQU2 MDA10
C1 VDDQ DQU3 C2 C1 VDDQ DQU3 C2
1
C9 A7 MDA22 C9 A7 MDA15
VDDQ DQU4 MDA16 VDDQ DQU4 MDA12
DIS_M96/Mad D2 VDDQ DQU5 A2
MDA21 DYDIS_M96/Mad D2 VDDQ DQU5 A2
MDA13
DIS_M96/Mad E9 B8 E9 B8
2
F1 VDDQ DQU7 A3 F1 VDDQ DQU7 A3
H9 VDDQ H9 VDDQ
H2 VDDQ DQSU C7 QSAP_2 (81) H2 VDDQ DQSU C7 QSAP_1 (81)
DQSU# B7 QSAN_2 (81) DQSU# B7 QSAN_1 (81)
VRAM1_VREF H1 VRAM2_VREF H1
VRAM2_VREF VREFDQ VRAM1_VREF VREFDQ
M8 VREFCA DQSL F3 QSAP_0 (81) M8 VREFCA DQSL F3 QSAP_3 (81)
DIS_M96/Mad
1 2 VRAM_ZQ1 L8 G3 QSAN_0 (81) DIS_M96/Mad
1 2VRAM_ZQ2 L8 G3 QSAN_3 (81)
R8503 243R2F-2-GP ZQ DQSL# R8504 243R2F-2-GP ZQ DQSL#
ODT K1 ODTA0 (81) ODT K1 ODTA0 (81)

(81,86) MAA0 N3 A0 (81,86) MAA0 N3 A0
(81,86) MAA1 P7 A1 (81,86) MAA1 P7 A1
(81,86) MAA2 P3 A2 CS# L2 CSA0#_0 (81) (81,86) MAA2 P3 A2 CS# L2 CSA0#_0 (81)
(81,86) MAA3 N2 A3 RESET# T2 MEM_RST (81,86,87,88) (81,86) MAA3 N2 A3 RESET# T2 MEM_RST (81,86,87,88)
(81,86) MAA4 P8 A4 (81,86) MAA4 P8 A4
(81,86) MAA5 P2 A5 (81,86) MAA5 P2 A5
(81,86) MAA6 R8 A6 NC#T7 T7 (81,86) MAA6 R8 A6 NC#T7 T7
(81,86) MAA7 R2 A7 NC#L9 L9 (81,86) MAA7 R2 A7 NC#L9 L9
(81,86) MAA8 T8 A8 NC#L1 L1 (81,86) MAA8 T8 A8 NC#L1 L1
C R3 J9 R3 J9 C
(81,86) MAA9 A9 NC#J9 (81,86) MAA9 A9 NC#J9
(81,86) MAA10 L7 A10/AP NC#J1 J1 (81,86) MAA10 L7 A10/AP NC#J1 J1
(81,86) MAA11 R7 A11 (81,86) MAA11 R7 A11
(81,86) MAA12 N7 A12/BC# (81,86) MAA12 N7 A12/BC#
(81,86) MAA13 T3 A13 VSS J8 (81,86) MAA13 T3 A13 VSS J8
M7 NC#M7 VSS M1 M7 NC#M7 VSS M1
VSS M9 VSS M9
VSS J2 VSS J2
(81,86) A_BA0 M2 BA0 VSS P9 (81,86) A_BA0 M2 BA0 VSS P9
(81,86) A_BA1 N8 BA1 VSS G8 (81,86) A_BA1 N8 BA1 VSS G8
(81,86) A_BA2 M3 BA2 VSS B3 (81,86) A_BA2 M3 BA2 VSS B3
20090902 VSS T1
A9
VSS T1
A9
VSS VSS
(81) CLKA0 J7 CK VSS T9 (81) CLKA0 J7 CK VSS T9
(81) CLKA0# K7 CK# VSS E1 (81) CLKA0# K7 CK# VSS E1
VSS P1 VSS P1
(81) CKEA0 K9 CKE (81) CKEA0 K9 CKE
1
VSSQ G1 VSSQ G1
R8508 R8507 F9 F9
56R2J-4-GP VSSQ VSSQ
(81) DQMA2 D3 DMU VSSQ E8 (81) DQMA1 D3 DMU VSSQ E8
56R2J-4-GP
DIS_M96/Mad DIS_M96/Mad
(81) DQMA0 E7 E2 (81) DQMA3 E7 E2
DML VSSQ DML VSSQ
D8 D8
2
VSSQ VSSQ
VSSQ D1 VSSQ D1
GPU_CLKA0_T (81) W EA0# L3 B9 (81) W EA0# L3 B9
WE# VSSQ WE# VSSQ
(81) CASA0# K3 CAS# VSSQ B1 (81) CASA0# K3 CAS# VSSQ B1
(81) RASA0# J3 RAS# VSSQ G9 (81) RASA0# J3 RAS# VSSQ G9
1
C8503 DIS_M96/Mad
SCD01U50V2KX-1GP K4W 1G1646E-HC12-GP K4W 1G1646E-HC12-GP
2
B B
DIS_Samsung_M96/Mad 20090902
DIS_Samsung_M96/Mad
20090902
+1.5V_RUN
+1.5V_RUN
1
1
R8513
R8510 2K1R2F-GP
2K1R2F-GP
DIS_M96/Mad
DIS_M96/Mad
2
2
VRAM2_VREF
VRAM1_VREF
1
C8506
1
C8504 R8512 DIS_M96/Mad

R8511 2K1R2F-GP SCD1U16V2ZY-2GP
DIS_M96/Mad
2
2K1R2F-GP SCD1U16V2ZY-2GP DIS_M96/Mad
2
DIS_M96/Mad
2
2
A <Core Design> A
Wistron Corporation
Title
Size
GPU-VRAM1,2 (1/4)
Document Number Rev
A3 Berry A00
5 4 3 2 1
5 4 3 2 1
+1.5V_RUN +1.5V_RUN
VRAM3 VRAM4
1.5V, 350mA MDA[32..63] (81) 1.5V, 350mA MDA[32..63] (81)
K8 E3 MDA36 K8 E3 MDA61
SC1U6D3V2KX-GP K2 F7 K2 F7
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
C8602
C8607
C8610
C8609
C8612
C8611
C8614
C8613
C8621
C8618
C8623
C8622
C8625
C8624
C8616
C8615
1 N1 VDD DQL2 F2 N1 VDD DQL2 F2
1
R9 F8 MDA39 R9 F8 MDA60
DIS_M96/Mad MDA34 DIS_M96/Mad DIS_M96/Mad MDA56
DY DY DY DY D9 H8
DY DY DY D9 H8
2
2
DY DIS_M96/MadDIS_M96/Mad G7 VDD DQL6 G2
MDA37
DIS_M96/MadDIS_M96/Mad DIS_M96/Mad G7 VDD DQL6 G2
MDA58
R1 VDD DQL7 H7 R1 VDD DQL7 H7
N9 VDD N9 VDD
D D7 MDA46 D7 MDA50 D
DQU0 MDA43 DQU0 MDA55
A1 C8 MDA45 A1 C8 MDA49
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
C8606 C8608 VDDQ DQU2 MDA40 C8617 C8619 VDDQ DQU2 MDA52
1
C9 A7 MDA44 C9 A7 MDA48
MDA47
MDA51
DIS_M96/Mad E9 B8 DIS_M96/Mad E9 B8
2
H9 VDDQ H9 VDDQ
H2 VDDQ DQSU C7 QSAP_5 (81) H2 VDDQ DQSU C7 QSAP_6 (81)
DQSU# B7 QSAN_5 (81) DQSU# B7 QSAN_6 (81)
M8 VREFCA DQSL F3 QSAP_4 (81) M8 VREFCA DQSL F3 QSAP_7 (81)
DIS_M96/Mad
1 2VRAM_ZQ3 L8 ZQ DQSL# G3 QSAN_4 (81) DIS_M96/Mad
1 2VRAM_ZQ4 L8 ZQ DQSL# G3 QSAN_7 (81)
R8603 243R2F-2-GP R8604 243R2F-2-GP
ODT K1 ODTA1 (81) ODT K1 ODTA1 (81)
(81,85) MAA0 N3 A0 (81,85) MAA0 N3 A0
(81,85) MAA1 P7 A1 (81,85) MAA1 P7 A1
(81,85) MAA2 P3 A2 CS# L2 CSA1#_0 (81) (81,85) MAA2 P3 A2 CS# L2 CSA1#_0 (81)
(81,85) MAA3 N2 A3 RESET# T2 MEM_RST (81,85,87,88) (81,85) MAA3 N2 A3 RESET# T2 MEM_RST (81,85,87,88)
(81,85) MAA4 P8 A4 (81,85) MAA4 P8 A4
(81,85) MAA5 P2 A5 (81,85) MAA5 P2 A5
(81,85) MAA6 R8 A6 NC#T7 T7 (81,85) MAA6 R8 A6 NC#T7 T7
(81,85) MAA7 R2 A7 NC#L9 L9 (81,85) MAA7 R2 A7 NC#L9 L9
(81,85) MAA8 T8 A8 NC#L1 L1 (81,85) MAA8 T8 A8 NC#L1 L1
(81,85) MAA9 R3 A9 NC#J9 J9 (81,85) MAA9 R3 A9 NC#J9 J9
(81,85) MAA10 L7 A10/AP NC#J1 J1 (81,85) MAA10 L7 A10/AP NC#J1 J1
(81,85) MAA11 R7 A11 (81,85) MAA11 R7 A11
(81,85) MAA12 N7 A12/BC# (81,85) MAA12 N7 A12/BC#
C T3 J8 T3 J8 C
(81,85) MAA13 A13 VSS (81,85) MAA13 A13 VSS
VSS M9 VSS M9
VSS J2 VSS J2
(81,85) A_BA0 M2 BA0 VSS P9 (81,85) A_BA0 M2 BA0 VSS P9
(81,85) A_BA1 N8 BA1 VSS G8 (81,85) A_BA1 N8 BA1 VSS G8
(81,85) A_BA2 M3 BA2 VSS B3 (81,85) A_BA2 M3 BA2 VSS B3
VSS T1 VSS T1
VSS A9 VSS A9
(81) CLKA1 J7 CK VSS T9 (81) CLKA1 J7 CK VSS T9
(81) CLKA1# K7 CK# VSS E1 (81) CLKA1# K7 CK# VSS E1
VSS P1 VSS P1
(81) CKEA1 K9 CKE (81) CKEA1 K9 CKE
1
VSSQ G1 VSSQ G1
1
R8607 F9 F9
56R2J-4-GP R8608 VSSQ VSSQ
(81) DQMA5 D3 DMU VSSQ E8 (81) DQMA6 D3 DMU VSSQ E8
DIS_M96/Mad56R2J-4-GP (81) DQMA4 E7 DML VSSQ E2 (81) DQMA7 E7 DML VSSQ E2
DIS_M96/Mad D8 D8
2
VSSQ VSSQ
D1 D1
2
GPU_CLKA1_T VSSQ VSSQ

(81) W EA1# L3 WE# VSSQ B9 (81) W EA1# L3 WE# VSSQ B9
(81) CASA1# K3 CAS# VSSQ B1 (81) CASA1# K3 CAS# VSSQ B1
(81) RASA1# J3 RAS# VSSQ G9 (81) RASA1# J3 RAS# VSSQ G9
1
C8603 DIS_M96/Mad
SCD01U50V2KX-1GP K4W 1G1646E-HC12-GP K4W 1G1646E-HC12-GP
2
B
DIS_Samsung_M96/Mad DIS_Samsung_M96/Mad B
20090902 20090902
20090902 +1.5V_RUN
+1.5V_RUN
1
R8605
1
2K1R2F-GP
R8601 DIS_M96/Mad
2K1R2F-GP
2
DIS_M96/Mad VRAM4_VREF
2
VRAM3_VREF
1
C8605
R8606 DIS_M96/Mad
1
2K1R2F-GP SCD1U16V2ZY-2GP
C8601
C8626
2
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
R8602 DIS_M96/Mad
2K1R2F-GP
2
2
DIS_M96/Mad DIS_M96/Mad
DIS_M96/Mad
2
1120-3
A <Core Design> A
Wistron Corporation
Title
Size
GPU-VRAM3,4 (2/4)
Document Number Rev
A3
Berry A00
5 4 3 2 1
5 4 3 2 1
+1.5V_RUN +1.5V_RUN
VRAM5 VRAM6
1.5V, 350mA MDB[0..31] (81) 1.5V, 350mA MDB[0..31] (81)
K8 E3 MDB14 K8 E3 MDB16
VDD DQL0 MDB13 VDD DQL0 MDB18
SC1U6D3V2KX-GP K2 F7 K2 F7
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
C8702
C8707
C8710
C8709
C8712
C8711
C8713
C8714
C8717
C8715
C8720
C8721
C8723
C8722
C8724
C8725
1 N1 VDD DQL2 F2 N1 VDD DQL2 F2
1
R9 F8 MDB15 R9 F8 MDB19
DY
DY
DY
DY
DY
DY
DY
DY
DY
DIS
DIS
DIS
DIS
DIS
DIS
DIS
D9 H8 MDB8 D9 H8 MDB17
2
2
G7 VDD DQL6 G2 G7 VDD DQL6 G2
R1 H7 MDB10 R1 H7 MDB21
VDD DQL7 VDD DQL7
N9 VDD N9 VDD
D D7 MDB26 D7 MDB1 D
DQU0 MDB27 DQU0 MDB5
A1 C8 MDB30 A1 C8 MDB2
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
C8706 C8708 VDDQ DQU2 MDB24 C8718 C8719 VDDQ DQU2 MDB4
DIS 1
1
C9 A7 MDB31 C9 A7 MDB3
VDDQ DQU4 VDDQ DQU4
DIS
DIS
DIS
D2 A2 MDB25 D2 A2 MDB7
VDDQ DQU5 MDB29 VDDQ DQU5 MDB0
E9 B8 E9 B8
2
H9 VDDQ H9 VDDQ
H2 VDDQ DQSU C7 QSBP_3 (81) H2 VDDQ DQSU C7 QSBP_0 (81)
DQSU# B7 QSBN_3 (81) DQSU# B7 QSBN_0 (81)
M8 VREFCA DQSL F3 QSBP_1 (81) M8 VREFCA DQSL F3 QSBP_2 (81)
1 2 VRAM_ZQ5 L8 G3 QSBN_1 (81) 1 2 VRAM_ZQ6 L8 G3 QSBN_2 (81)
DIS DIS
ODT K1 ODTB0 (81) ODT K1 ODTB0 (81)
(81,88) MAB0 N3 A0 (81,88) MAB0 N3 A0
(81,88) MAB1 P7 A1 (81,88) MAB1 P7 A1
(81,88) MAB2 P3 A2 CS# L2 CSB0#_0 (81) (81,88) MAB2 P3 A2 CS# L2 CSB0#_0 (81)
(81,88) MAB3 N2 A3 RESET# T2 MEM_RST (81,85,86,88) (81,88) MAB3 N2 A3 RESET# T2 MEM_RST (81,85,86,88)
(81,88) MAB4 P8 A4 (81,88) MAB4 P8 A4
(81,88) MAB5 P2 A5 (81,88) MAB5 P2 A5
(81,88) MAB6 R8 A6 NC#T7 T7 (81,88) MAB6 R8 A6 NC#T7 T7
(81,88) MAB7 R2 A7 NC#L9 L9 (81,88) MAB7 R2 A7 NC#L9 L9
(81,88) MAB8 T8 A8 NC#L1 L1 (81,88) MAB8 T8 A8 NC#L1 L1
(81,88) MAB9 R3 A9 NC#J9 J9 (81,88) MAB9 R3 A9 NC#J9 J9
(81,88) MAB10 L7 A10/AP NC#J1 J1 (81,88) MAB10 L7 A10/AP NC#J1 J1
(81,88) MAB11 R7 A11 (81,88) MAB11 R7 A11
(81,88) MAB12 N7 A12/BC# (81,88) MAB12 N7 A12/BC#
C T3 J8 T3 J8 C
(81,88) MAB13 A13 VSS (81,88) MAB13 A13 VSS
VSS M9 VSS M9
VSS J2 VSS J2
(81,88) B_BA0 M2 BA0 VSS P9 (81,88) B_BA0 M2 BA0 VSS P9
(81,88) B_BA1 N8 BA1 VSS G8 (81,88) B_BA1 N8 BA1 VSS G8
20090902 (81,88) B_BA2 M3 BA2 VSS B3
T1
(81,88) B_BA2 M3 BA2 VSS B3
T1
VSS VSS
VSS A9 VSS A9
(81) CLKB0 J7 CK VSS T9 (81) CLKB0 J7 CK VSS T9
(81) CLKB0# K7 CK# VSS E1 (81) CLKB0# K7 CK# VSS E1
VSS P1 VSS P1
1
(81) CKEB0 K9 CKE (81) CKEB0 K9 CKE

R8707 R8708 G1 G1
56R2J-4-GP 56R2J-4-GP VSSQ VSSQ
VSSQ F9 VSSQ F9
DIS DIS (81) DQMB3 D3 DMU VSSQ E8 (81) DQMB0 D3 DMU VSSQ E8
(81) DQMB1 E7 E2 (81) DQMB2 E7 E2
2
DML VSSQ DML VSSQ

VSSQ D8 VSSQ D8
GPU_CLKB0_T D1 D1
VSSQ VSSQ
(81) W EB0# L3 WE# VSSQ B9 (81) W EB0# L3 WE# VSSQ B9
(81) CASB0# K3 CAS# VSSQ B1 (81) CASB0# K3 CAS# VSSQ B1
1
C8703 DIS (81) RASB0# J3 G9 (81) RASB0# J3 G9

RAS# VSSQ RAS# VSSQ
SCD01U50V2KX-1GP
2
K4W 1G1646E-HC12-GP K4W 1G1646E-HC12-GP
DIS_Samsung DIS_Samsung
B 20090902 B
20090902
+1.5V_RUN +1.5V_RUN
1
1
R8701 R8703
2K1R2F-GP 2K1R2F-GP
DIS DIS
2
2
VRAM5_VREF VRAM6_VREF
1
1
C8701 C8705
R8702 R8705
2K1R2F-GP SCD1U16V2ZY-2GP 2K1R2F-GP SCD1U16V2ZY-2GP
2
2
DIS DIS DIS DIS
2
A 2 <Core Design> A
Wistron Corporation
Title
GPU-VRAM5,6 (3/4)
A3
Berry A00
5 4 3 2 1
5 4 3 2 1
+1.5V_RUN +1.5V_RUN
VRAM7 VRAM8
1.5V, 350mA MDB[32..63] (81) 1.5V, 350mA MDB[32..63] (81)
K8 E3 MDB40 K8 E3 MDB53
K2 F7 K2 F7
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
C8802
C8808
C8809
C8810
C8811
C8812
C8813
C8814
C8816
C8819
C8820
C8821
C8822
C8823
C8824
C8825
N1 VDD DQL2 F2 N1 VDD DQL2 F2
1
1
R9 F8 MDB44 R9 F8 MDB49
DY
DY
DY
DY
DY
DY
DY
DY
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
D9 H8 MDB45 D9 H8 MDB48
2
2
G7 VDD DQL6 G2 G7 VDD DQL6 G2
D R1 H7 MDB46 R1 H7 MDB50 D
VDD DQL7 VDD DQL7
N9 VDD N9 VDD
D7 MDB36 D7 MDB61
DQU0 MDB35 DQU0 MDB62
A1 C8 MDB39 A1 C8 MDB58
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
C8806 C8807 VDDQ DQU2 MDB32 C8817 C8818 VDDQ DQU2 MDB59
1
C9 A7 MDB37 C9 A7 MDB63
DIS DIS D2 VDDQ DQU5 A2
MDB38
DIS DIS D2 VDDQ DQU5 A2
MDB57
E9 B8 E9 B8
2
H9 VDDQ H9 VDDQ
H2 VDDQ DQSU C7 QSBP_4 (81) H2 VDDQ DQSU C7 QSBP_7 (81)
DQSU# B7 QSBN_4 (81) DQSU# B7 QSBN_7 (81)
M8 VREFCA DQSL F3 QSBP_5 (81) M8 VREFCA DQSL F3 QSBP_6 (81)
1 2 VRAM_ZQ7 L8 G3 QSBN_5 (81) 1 2 VRAM_ZQ8 L8 G3 QSBN_6 (81)
DIS DIS
ODT K1 ODTB1 (81) ODT K1 ODTB1 (81)
(81,87) MAB0 N3 A0 (81,87) MAB0 N3 A0
(81,87) MAB1 P7 A1 (81,87) MAB1 P7 A1
(81,87) MAB2 P3 A2 CS# L2 CSB1#_0 (81) (81,87) MAB2 P3 A2 CS# L2 CSB1#_0 (81)
(81,87) MAB3 N2 A3 RESET# T2 MEM_RST (81,85,86,87) (81,87) MAB3 N2 A3 RESET# T2 MEM_RST (81,85,86,87)
(81,87) MAB4 P8 A4 (81,87) MAB4 P8 A4
(81,87) MAB5 P2 A5 (81,87) MAB5 P2 A5
(81,87) MAB6 R8 A6 NC#T7 T7 (81,87) MAB6 R8 A6 NC#T7 T7
(81,87) MAB7 R2 A7 NC#L9 L9 (81,87) MAB7 R2 A7 NC#L9 L9
(81,87) MAB8 T8 A8 NC#L1 L1 (81,87) MAB8 T8 A8 NC#L1 L1
(81,87) MAB9 R3 A9 NC#J9 J9 (81,87) MAB9 R3 A9 NC#J9 J9
(81,87) MAB10 L7 A10/AP NC#J1 J1 (81,87) MAB10 L7 A10/AP NC#J1 J1
C R7 R7 C
(81,87) MAB11 A11 (81,87) MAB11 A11
(81,87) MAB12 N7 A12/BC# (81,87) MAB12 N7 A12/BC#
(81,87) MAB13 T3 A13 VSS J8 (81,87) MAB13 T3 A13 VSS J8
VSS M9 VSS M9
VSS J2 VSS J2
(81,87) B_BA0 M2 BA0 VSS P9 (81,87) B_BA0 M2 BA0 VSS P9
20090902 (81,87) B_BA1 N8
M3
BA1 VSS G8
B3
(81,87) B_BA1 N8
M3
BA1 VSS G8
B3
(81,87) B_BA2 BA2 VSS (81,87) B_BA2 BA2 VSS
VSS T1 VSS T1
VSS A9 VSS A9
(81) CLKB1 J7 CK VSS T9 (81) CLKB1 J7 CK VSS T9
(81) CLKB1# K7 CK# VSS E1 (81) CLKB1# K7 CK# VSS E1
VSS P1 VSS P1
1
(81) CKEB1 K9 CKE (81) CKEB1 K9 CKE

R8807 R8808 G1 G1
56R2J-4-GP 56R2J-4-GP VSSQ VSSQ
VSSQ F9 VSSQ F9
DIS DIS (81) DQMB4 D3 DMU VSSQ E8 (81) DQMB7 D3 DMU VSSQ E8
(81) DQMB5 E7 E2 (81) DQMB6 E7 E2
2
DML VSSQ DML VSSQ

VSSQ D8 VSSQ D8
GPU_CLKB1_T D1 D1
VSSQ VSSQ
(81) W EB1# L3 WE# VSSQ B9 (81) W EB1# L3 WE# VSSQ B9
(81) CASB1# K3 CAS# VSSQ B1 (81) CASB1# K3 CAS# VSSQ B1
1
C8803 DIS (81) RASB1# J3 G9 (81) RASB1# J3 G9

RAS# VSSQ RAS# VSSQ
SCD01U50V2KX-1GP
2
K4W 1G1646E-HC12-GP K4W 1G1646E-HC12-GP
B DIS_Samsung DIS_Samsung B
20090902 20090902
+1.5V_RUN +1.5V_RUN
1
1
R8801 R8805
2K1R2F-GP 2K1R2F-GP
DIS DIS
2
2
VRAM7_VREF VRAM8_VREF
1
1
C8801 C8804
R8802 R8806
2K1R2F-GP SCD1U16V2ZY-2GP 2K1R2F-GP SCD1U16V2ZY-2GP
2
2
DIS DIS DIS DIS
2
A <Core Design> A
Wistron Corporation
Title
GPU-VRAM7,8 (4/4)
A3
Berry A00
5 4 3 2 1
5 4 3 2 1
SSID = Video.PWR.Regulator RT8208AGQW for +VCC_GFX_CORE
D D
+PW R_SRC
SCD1U25V2KX-GP
SCD1U25V2KX-GP
1117-6
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SC10U25V6KX-1GP
PC8911
PC8907
1
1
PC8914
PC8903
PC8905
DIS DIS DIS DIS DIS
2
+5V_ALW
5
6
7
8
Vout=0.75V*(R1+R2)/R2
D
D
D
D
5V, 1.25mA PU8902
SI7686DP-T1-GP
PR8910 Design Current = 21.94A

1
PC8908 +GFX_CORE_TON 1 DIS 2 DIS_65MOS 24.14A<OCP< 28.53A
G
S
S
S
SC1U10V2KX-1GP
2DIS 249KR2F-GP
4
3
2
1
PU8901
PR8902
PC8906
0114-1 +VGA_CORE
PR8903 16 13 +GFX_CORE_BOOT
2 DIS 1+GFX_CORE_BOOT_C
1 DIS2
TON BOOT 1R3J-L1-GP PL8901
2 DIS 1
10R2F-L-GP
9 VDDP +GFX_CORE_UGATE SCD1U25V3KX-GP
+GFX_CORE_VDD UGATE 12
+GFX_CORE_PHASE
DIS
2 VDD PHASE 11 1 2
8 +GFX_CORE_LGATE COIL-D56UH-2-GP
LGATE
SCD1U10V2KX-4GP
1
1
(49,51,52,90) RUNPW ROK 4 7 PTC8901
GAP-CLOSE-PWR-3-GP
PGOOD G0 PW RCNTL_0 (82)
1
SE330U2VDM-L-GP
C 1 DIS 2+GFX_CORE_CS 10 CS FB 3 +GFX_CORE_FB PU8903 PU8904 DY PR8906 PTC8902 PTC8903 C
5
6
7
8
5
6
7
8
SE330U2VDM-L-GP
SE330U2VDM-L-GP
PR8905 6K98R2-GP DIS 14 2D2R5F-2-GP DY
SC1U10V2KX-1GP
SCD1U10V2KX-5GP
SC10P50V2JN-4GP
SC10P50V2JN-4GP
PW RCNTL_1 (82)
2
G1
1
D
D
D
D
D
D
D
D
PW RCNTL_1#
PG8920
PC8915
0225-3 +GFX_CORE_EN_R 5
2
D1
1
PW RCNTL_0#
PC8918
PC8904
15 6 DIS DIS DIS
SIR460DP-T1-GE3-GP
SIR460DP-T1-GE3-GP
EM/DEM D0
1VGA_CORE_DIV
DIS +GFX_CORE_VOUT
DIS
17 1
2
2
GND VOUT
DIS_65MOS DIS_65MOS
1
S
S
S
S
S
S
G
G
RT8208BGQW -GP
DY DY
4
3
2
1
4
3
2
1
+GFX_CORE_VOUT
2
1120-8
PC8917
PC8913
Change to RT8208B(Pin to Pin) PC8910
PR8908
10KR2F-2-GP
SC330P50V2KX-3GP
DY
2
DIS
0210-1
2
PR8921 1 DY 2 0R2J-2-GP
(37) GFX_CORE_EN
PR8920 1 2 10KR2J-3-GP +GFX_CORE_EN_R
(21,37,41,42,49,52) PM_SLP_S3# DIS
+GFX_CORE_FB
1
PC8912
SCD1U10V2KX-4GP
1
DIS
2
PR8909 PR8911 PR8912

150KR2F-L-GP 49K9R2F-L-GP 49K9R2F-L-GP
11/9 DIS
DIS DIS_PowerPlay
2
B B
PWRCNTL_0#
PWRCNTL_1#
M96 Power Table Park Power Table
PWRCNTL_0 PWRCNTL_1 +VCC_GFX_CORE PWRCNTL_0 PWRCNTL_1 +VCC_GFX_CORE
H H 0.9V H H 0.9V
L H 0.95V L H 0.95V
H L 1.05V H L 1.05V
L L 1.1V L L 1.12V
PR8912=49.9KR PR8912=49.9KR
64.49925.6DL 64.44225.6DL
I/P cap: 10U 25V K1206 X5R/ 78.10622.52L

A Inductor: 0.56uH PCMC104T-R56MN Cyntec DCR:1.6mohm/1.8mohm Isat=25Arms 68.R5610.10D <Core Design> A
O/P cap: 330U 2.5V EEFSX0D331ER 9mOhm 3Arms Panasonic/ 79.33719.L01

H/S: SI7686DP/ POWERPAK-8/11mOhm/14mOhm@4.5Vgs/ 84.07686.037 Wistron Corporation
L/S: SiR460DP/ POWERPAK-8/ 4.9mOhm/6.1mohm@4.5Vgs/ 84.00460.037 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Title
RT8208B_+VCC_GFXCORE
A3
5 4 3 2 1
5 4 3 2 1
APL5930 for +1.8V_RUN_VGA +3.3V_RUN_VGA

+1.8V_RUN_VGA_P +1.8V_RUN_VGA 1
DIS_Park/Mad
2
R9001 0R2J-2-GP
+3.3V_RUN_VGA
Q9001
PG9002
D
+3.3V_RUN +1.8V_RUN_VGA_VIN +5V_RUN +1.8V_RUN_VGA_VIN
1 2
DIS +3.3V_RUN S DIS_M96
D
SI2301CDS-T1-GE3-GP
D
1
5V, 1.5mA GAP-CLOSE-PW R
PG9003 Id: 2A
G
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
R9002 DIS_M96
1 2
DIS Rds: 0.15ohm
1
PG9001 PC9002 PC9003 PC9004 100KR2J-1-GP
DIS GAP-CLOSE-PW R
2
DIS 1
DY
2
SC1U10V2KX-1GP 3.3V_ALW _1
2
GAP-CLOSE-PW R DIS
PG9004
1
2
DIS1
4
Design Current =1.13A Q9002 R9004
+5V_ALW GAP-CLOSE-PW R 100R2J-2-GP
2N7002EDW -GP DIS_M96
6
PU9001 DIS_M96
84.27002.F3F
VCNTL
2
2
(49,51,52,89) RUNPW ROK 7 5
3
R9006 POK VIN#5 +1.8V_RUN_VGA_P
VIN#9 9
DIS 100KR2J-1-GP
(37,52) 1.8V_VGA_RUN_EN 1 21.8V_VGA_RUN_EN_C 8 EN VOUT#3 3
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
4 3.3V_RUN_VGA_1
1
VOUT#4
SC68P50V2JN-1GP
PR9002 PC9005 PC9006 PC9007
Vo=0.8*(1+(R1/R2)) DIS
1
16K5R2F-2-GP
0R0402-PAD PC9001 PR9003 DIS
1.8V_DIS_GATE
SC4700P50V2KX-1GP
DY 2 DY
GND
FB
DIS (37) 3.3V_RUN_VGA_EN
2
DIS
5912_1.8V_DELAY_FB
APL5930KAI-TRG-GP
2
SO-8-P
C C
6
PQ9001 +1.8V_RUN_VGA
DIS 2N7002EDW -GP
84.27002.F3F
1
1
1.8V_DIS 1
DIS Vout=0.8V*(R1+R2)/R2 PR9006
13K3R2F-L1-GP 1208-1
R9005
2
10R2J-2-GP
DIS
2
1.8V_VGA_RUN_EN
APL5930KAI for +1.0V_RUN_VGA Will be Change to +1.0V_RUN_VGA
+5V_ALW +1.5V_SUS
5V, 1.5mA
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
1
1
PC9008 PC9009 PC9010
SC1U10V2KX-1GP
DIS DY
DIS
2
2
B B
+3.3V_ALW
+1.0V_RUN_VGA
6
PU9002
Design Current: 1.51A
2
VCNTL
R9007 (49,51,52,89) RUNPW ROK 7 5

POK VIN#5 +1.0V_RUN_VGA
DIS 100KR2J-1-GP VIN#9 9
(37) 1.0V_RUN_VGA_EN 1 21.0V_RUN_VGA_EN_C 8 3

1
EN VOUT#3
4
SCD01U16V2KX-3GP
VOUT#4
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
PR9007 PC9014
1.0V_DIS_GATE
SC4700P50V2KX-1GP
1
1
12KR2F-L-GP
0R0402-PAD PC9011 DIS PR9009 PC9012 PC9013

2 DIS DIS DY
GND
FB
DY DIS
2
APL5930KAI-TRG-GP 2
1
SO-8-P
6
PQ9002
DIS 2N7002EDW -GP
5930_1.0VRUN_FB
84.27002.F3F +1.0V_RUN_VGA
1
DIS PR9011
A 1.0V_DIS 1
R9010
2
10R2J-2-GP
Vout=0.8V*(R1+R2)/R2 32K4R2F-1-GP
<Core Design> A
DIS
Wistron Corporation
2
1.0V_RUN_VGA_EN
Title
DISCRETE VGA POWER
A3 Berry A00
Date: Tuesday, March 09, 2010 Sheet 90 of 95
5 4 3 2 1
5 4 3 2 1
POWER SEQUENCE +PWR_SRC
+3.3V_RTC_LDO
VBAT(+RTC_CELL)
KBC_ROM_STRAPS
D D
S5_ENABLE
+3.3V_ALW
+5V_ALW
WAKE#(PCIE_WAKE#)
RSMRST#(KBC_RSMRST#)
S5_ROM_STRAPS
PWR_BTN#(PM_PWRBTN#)
PM_SLP_S3#/PM_SLP_S5#
+3.3V_RUN, +5V_RUN
+1.5V_SUS
C C
+0.75V_DDR_VTT
+1.8V_RUN
+VGA_CORE
+2.5V_RUN
1.5V_RUN_EN, 1.0V_RUN_VGA_EN
+1.5V_RUN, +1.0V_RUN_VGA
1.8V_VGA_RUN_EN
+1.8V_RUN_VGA
3.3V_RUN_VGA_EN
B B
+3.3V_RUN_VGA
RUNPWROK
+CPU_VDDR
IMVP_VR_ON
+VCC_CORE, +VDDNB
IMVP_PWRGD
+1.1V_RUN
VDDC_PWRGD
SB_PWRGD
S0_ROM_STRAPS
A <Core Design> A
NB_PWRGD
Wistron Corporation
LDT_PG(CPU_LDT_PWRGD) 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Title
POWER SEQUENCE
A3 A00
5 4 3 2 1
5 4 3 2 1
Change notes - Page 1

VERSON DATE ITEM PAGE Modify List Issue Description OWNER
X01 11/6 1 10 Add C1002 10uF, C1007, EC1001 0.1uF, C1008 10pF. Insure signal quality. EE
2 13 Change R1314 to 4.7K. Meet CRB. EE
D 3 51 Swap PU5101 pin3, pin4. Correct input voltage level. EE D
4 82 Add R8210 0R. Reserve GPU clock input source. EE
11/9 1 30 Change C3014 to 2.2uF. Reduce package size. EE
2 69 Change C6903 to 0.1uF. Reduce package size. EE
3 49 Add PR4916 100KR. To prevent leakage in S3 status. EE
11/10 1 18,19 Change DIMM socket Part Number. Request by ME. ME
2 37 Add R3754 100KR. To detect leakage current. EE
11/11 1 10 Modify R1028 pull-up to +1.5V_RUN. Solve leakage in S3 status. EE
11/12 1 20 Change C2011 to 18pF, C2012 to 15pF. Set accurate clock frequency. EE
2 37 Add C3717 10pF. Stable singal level. EE

C C
3 57 Delete RN5711, RN5705. Redundant parts. EE
4 13 Delete R1331, R1332, R1308. Redundant parts. EE
5 77 Add Pi-filter. Cure EMI. EMC
11/13 1 20 Change X2001 P/N. Request by Sourcer. Sourcer
2 7 Change R713 to 47R. Fine tune damping. EE
3 82 Add R8211 80.6R, R8220 150R. Set a voltage divider to 1.8V level swing. EE
4 21 Add R2133 1KR. For UMA VRAM vendor selection. EE
11/16 1 22 Delete RN2203 pin 4, pin 5 connection. Solve S5 leakage. EE
2 51 Change PR5105 pull-up to +3.3V_RUN. Prevent leakage. EE
B
3 21 Add C2103, C2104 0.1uF. For signal stability. EE B
4 37 Add C3718 0.1uF. For signal stability. EE
5 41 Add C4101, C4102 0.1uF. For signal stability. EE
6 49 Add PC4923 0.1uF. For signal stability. EE
7 66 Add C6601, C6602 0.1uF. For signal stability. EE
8 77 Add RN7713 150R. Move impedance matching resistor from CRT/B to M/B. EMC
9 78 Change CARDBD1 pin 2 link to PLTRST#_LAN_WAN. Change card reader chip to RTS5159 to solve EMI. EMC
11/17 1 30 Add R3014, R3017, R3020 0R to link AGND and GND. Issue for pop noise when system boot. EE
2 42,48,50 Merge 1.1V power solution on main board. Save components. EE, Power
3 77 Modify CRTBD1 pin define. Relief EMI. EMC

A <Core Design> A
4 79 Add some decoupled capacitors. Request by EMC. EMC
5 37 Change R3737 to 33R, stuff C3715 10pF. Request by EMC. EMC Wistron Corporation
6 62,89 Sutff EC6203 22pF, PC8911, PC8907 0.1uF. Request by EMC. EMC
Title
7 45,46,47 Stuff EC4502 0.1uF, PC4605, PC4609, PC4738 0.1uF. Request by EMC. EMC Change notes
A3
5 4 3 2 1
5 4 3 2 1

X01 11/17 8 9 Delete R904. Remove redundant layout trace. EE
11/18 1 81 Swap R8105, C8103 location. Meet CRB. EE
D 2 79 Add some decoupled capacitor. By RF team request. RF D
3 49 Change PR4903 to 620KR. Change to common part. Power
11/19 1 All Synchronize with DJ schematic. Schematic standardlize. EE
2 48 Change P/N for PU4802, PU4803, PU4804, PU4805. Rquest by Power team Power
3 All Review all capacitors tolerance. Total review for deratig. EE
4 21 Add RN2105 0R. Reserve to fine tune signal quality. EE
5 21 Change RN2101 to 4.7KR. Fine tuned value for signal. EA
6 37 Add RN3705, R3755 0R. To isolate layout trace to DB1 connector. EA
7 49 Change PC4908 to 2.2uF. Changed by EA report. EA
11/20 1 54 Modify R5408 connection. To synchronize with DJ. EE

C C
2 57 Add D7701. To prevent leakage from RGB monitor. EE
3 86 Add C8626 0.1uF. By EA report. EA
4 37 Add R3756 10KR, C3720 0.1uF. Synchronize with DJ. EE
5 37 Delete RN3705, R3755. For more layout space. EE
6 13 Delete TP1303, TP1304. For more layout space. EE
7 49 Delete PR4905. For more layout space. EE
8 89 Add PC8918 0.1uF. Stable signal quality. EE
11/24 1 46,49 Change PU4601, PU4901 Power components. Request by Power team. Power
11/25 1 46,47,49,89 Change power components. Request by Power team. Power
B
11/29 1 10 Change C1008 to 10pF. Fine tuned signal slew rate to meet specification. EE B
2 30 Change R3007 to 2.2KR. By FAE suggestion. EE
X02 12/04 1 81 Set BOM mark R8104, R8106, R8107, R8110, R8111, R8112. Implement co-layout Madison and M96. EE
2 82,84 Add R8407, R8408 0R. Implement co-layout Madison and M96. EE
3 80 Add R8016 10KR. Implement co-layout Madison and M96. EE
4 83,84 Set BOM mark. Implement co-layout Madison and M96. EE
5 83 Add L8306, L8307, C8397, R8301, R8302, R8303. Implement co-layout Madison and M96. EE
12/05 1 37 Change R3756, C3720 connection. Correct soft-start for EC power. EE
12/08 1 90 Set BOM mark. Implement co-layout Madison and M96. EE
12/15 1 15 Delete RN1501, Add G1501~G1504. Synchronize with DJ and supply sufficient power rail. EE
A <Core Design> A
2 62 Add R6207 100KR. Insure SPI Write-Protect pin signal level. EE
3 66 Change C6602 net name. Correct signal name. EE Wistron Corporation

4 81 Add R8122 1KR, RN8101 4.7KR. Meet M96 schematic check list. EE
Title
5 82 Swap CLK_VGA_27M_NSS and CLK_VGA_27M_SS connection. Solve external RGB display tremble issue. EE Change notes
A3
5 4 3 2 1
5 4 3 2 1

X02 12/16 1 66 Change R6605 to 0R. Assure power button level set to low. EE
2 37,76 Add net "8103_GPO". Implement LAN DSM hardware function. EE
D 12/17 1 37 Add U3703. To solve SPI WP signal malfunction on EC. EE D
12/18 1 82 Add R8222 1MR. Assure crystal resonant clock stable. EE
2 81 Set VRAM reset circuit. Follow M96 reset circuit and reseve BOM option. EE
12/25 1 18 Change TC1801 to 330uF, 2V tolerance. Implement common part for 1.5V power rail. EE
2 46 Change PR4603 to 127KR. Set 5V current limitation. Power
3 46 Empty PR4618 and stuff PR4619. Set Ultra-sonic mode to keep +15V_ALW voltage level. Power
4 10 Set RN1006 PU to +1.5V_SUS. Follow AMD check list and cure +1.5V_RUN leakage. EE
5 62 Change R6206 to 1KR. According to Safety request, verified OK. Safety
6 51 Change PR5102 1KR, PR5106 8.2KR, PR5107 5.62KR. Set VDDR low voltage level to 0.9V. EE
12/29 1 10,37 Add Q1005, R1039, R1040. Request by AMD to set CPU into HTC mode in DOS. EE
C C
2 47 Change PR4720 93.1KR, PR4721 24KR. Set power OCP value. Power
12/31 1 ALL Change some resistors as short-pad or resistor array. Save component counts. EE
2 ALL Change some capacitors with smaller value or empty. Save component counts. EE
01/04 1 15 Change R1507,R1508,R1509,R1510,R1511 to bead. Filter power noise. EMC
01/05 1 7 Combine R707,R721 as RN711. For more layout space. EE
2 81 Delete TP8101,TP8102. Remove useless test point for more layout space. EE 0108
3 7,80 Delete R716,R8020, combine R8009,R8010 as RN8001. Redundant part. EE
4 37,39,41 R3747,R4104 short pad, delete R3722,R3904. Redundant part. EE
5 46 Change PR4620 as short pad. Redundant part. EE
B
6 51 Change PQ5101 with ESD protector. Change to common part. Power B
7 54 Empty R5405 and Stuff R5408. Avoid LCD white panel. EE
8 62 Change R6205 to 0R. Already have one 1KR ahead. EE
01/06 1 50 Add PR5004 10KR and empty PR5002. Avoid +1.1V_ALW leakage in South Bridge. EE
2 13 Change R1342 to size 0603. Synchronous schematic w/DJ. EE
3 79 Add R7921 and R7922. Reserved RF team solution. RF
01/07 1 7 Add RN712,C722,C723 Reserve for SMBus signal quality tuning. EE
2 60 Change EC6007,EC6008 to 0.01uF. According FAE Request. IDT FAE
3 39 Add Q3904. According thermal team request. Thermal
4 21,18 Change location RN2105 to RN1801, add C1823,C1824. For SMBus signal quality fine tune. EE
A <Core Design> A
5 39,82,83 Remove C3912,TP8301,TP8302,TP8213. Remove dummy part for more layout space. EE
6 76 Reserve C7601, C7602. Fine tune USB signal quality. EE Wistron Corporation
01/08 1 79 Reserve EC7925,EC7926,EC7927. Reserve by EMC team. EMC
Title
2 77 Change RN7711 to 0R, L7701,L7702,L7703 to bead 22R. According EMC measurement result. EMC Change notes
A3
5 4 3 2 1
5 4 3 2 1
X02 01/08 3 18,19 Add C1825,C1922. Reduce V_REF ripple by EA team result. EE
4 37 Reserve C3721,C3722. Prevent signal cross talk. EE

D 5 ALL Change capacitors value and add C3723. Ensure signal quality. EE
D
01/11 1 68 Change KB1 P/N. According ME request. ME
2 66 Change R6601,R6602,R6604,R6606 to 1KR, R6603 to 470R. Decrease LED brightness. EE
01/12 1 37 Add C3724, R3757. To set accurate current detection in EC. EE
2 10 Add R1041 0R. Add 0R for level shift off. EE
01/13 1 21,37 Add C3725, C2105. Reserve for singal quality. EE
01/14 1 Power Modify power team componets. Request by Power Team. Power
2 7 Change RN712 to 22R. Fine tuned damping resistor value. EE
A00 02/08 1 66 Reserve R6609, R6610 1KR. Add for future LED brightness balance. EE
2 68 Add keyboard back light circuit, remove R5403. Add for keyboard with back light module. EE
C C
3 69 Change HALLSW1 footprint for co-layout. Change for co-layout different kind of HALLSW1. EE
4 77 Add AFTP7701, AFTP7702, AFTP7703. Add AFTP test point for factory test. EE
02/10 1 Power Update Obsolete parts. Update obsolete parts due to policy. Power
2 79 Change HBT1 part number. Change HBT1 part number to match ME EMN file. ME
3 47 Add PTC4710. Add to solve board accoustic issue. EE
02/22 1 54 Remove co-layout pad. As factory requst. EE 0308-1

2 42 Add C4217, C4401, C4402. Ensure signal quality. EE
3 48 Delete Power Gap. Request by Power Team. Power
02/23 1 ALL Change to short pad. Change most of 0-ohm resistors to short pad. EE
B 02/24 1 7,68,79 Reserve C724, C725, C6806, C6807, EC7928-EC7932. As EMC team request. EMC B
02/25 1 13 Add TP1309. As factory requset to add. Factory
2 7,68 Rename EMC capacitor to EC704,EC705,EC6801,EC6802. Meet schematic standardization. EE
3 49,89 Change PR4913 to 3.9R, PR8905 to 6.98KR. PR4913 for snubber, PR8905 for OCP. Power
4 21 Change R2133 to 0R. Set GPIO input level from 0.5V to 0V. EE
5 79 Remove EC7928. Layout space limitation. EE
02/26 1 39,42 Empty R3906 and Change R4202 from 0R to 1KR. It is for solving T8 shutdown issue. EE
03/03 1 60 Change SPK1 part number. Request by ME. ME
03/05 1 20,24,37 Empty R2029,R2404,R3751. Saving unused components. EE
03/08 1 48 Stuff PU4803 and empty PU4804. Place the H/S and L/S MOS at the same surface. Power
A <Core Design>
A
Wistron Corporation
Title
Change notes

A3 Berry A00

Dell Inspiron N5010-AMD

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5 4 3 2 1

Berry Discrete/UMA Schematics Document

AMD Danube CPU S1g4

DDR III 1333 DDRIII DIMM1 SYSTEM DC/DC

64Mx16bx8 (1GB) 35W Max DDR III 1333 DDRIII DIMM2

AMD RS880M CORE

AMD SB820M DDR III SUS&VTT

Card Reader ACPI 1.1 (LVDS & Camera Conn.)

SPI NUVOTON L3: Signal

ISL6265AHRTZ RT8208B RT8209EGQW RT8207

AO4468 AO4468 APL5930 RT9025

+1.5V_RUN +1.5V_RUN_VGA +1.0V_RUN_VGA VDDR(CPU)

UP7534 AO4468 UP7534 AO4468 PA102FMG APL5930 APL5930 RT9025

+5V_USB1 +5V_RUN +5V_USB2 +3.3V_RUN +3.3V_LAN +1.8V_RUN +1.8V_RUN_VGA +1.1V_ALW

RESISTER RESISTER SI2301BDS G5285T11U RTS5159 RT9013-25PB RTL8103T

+PVDD +AVDD +3.3V_RUN_VGA +LCDVDD +3.3V_RUN_CARD +2.5V_RUN +1.2V_LOM

SB820M SMBus Block Diagram KBC SMBus Block Diagram

CPU_SID SRN10KJ-5-GP DIMM 2 Battery Conn.

MINI CARD SRN4K7J-8-GP

SRN1KJ-7-GP CPU S1G4 GPIO62/SDA2 KBC_SDA1

Thermal Block Diagram Audio Block Diagram

DN1 H_THERMDC THERMDC

SB820M Strapping RS880M Strapping

ROMTYPE_1 ROMTYPE_0 ROM TYPE

3.3V– Integrated clock mode: Use 25-MHz crystal

Set PCIe to Gen II mode

Watchdog function USB RS880M

3 SB_SMBDATA_CK 2 3 SRN33J-5-GP-U SB_SMBDATA_CK C722 1 SC47P50V2JN-3GP

R706 SC10P50V2JN-4GP RN707 +3.3V_RUN

VDD48 CLKREQ3# TP_CLKREQ4#

R714 1 2 33R2J-2-GP R_VGA_27M_NSS_CLK

(13) CLK_NBHT_CLK 2RN706 3 CLK_NBHT_CLK_R ICS9LPRS480BKLFT-GP Place together

10/1 2nd 71.08628.003

SSID = CPU Place close to socket

(12) HT_NB_CPU_CAD_H0 E3 L0_CADIN_H0 L0_CADOUT_H0 AD1 HT_CPU_NB_CAD_H0 (12)

(12) HT_NB_CPU_CAD_H7 N3 L0_CADIN_H7 L0_CADOUT_H7 T1 HT_CPU_NB_CAD_H7 (12)

2'nd 62.10055.171 (12)

SSID = CPU (18) M_A_DQ[63..0]

M_A_DQ48 MA_DATA47 MB_DATA47 M_B_DQ48

MA0_ODT1 M_A_DQ52 MA_DATA51 MB_DATA51 M_B_DQ52

(18) MEM_MA_RAS# R19 MA_RAS# MB_RAS# U25 MEM_MB_RAS# (19)

SSID = CPU LYAOUT:ROUTE VDDA TRACE APPROX.

+2.5V_RUN 1119-1 +2.5V_RUN_VDDA

VDD1_FB_H VDDNB_FB_H CPU_VDDNB_RUN_FB_H (47)

R1013 1 300R2J-4-GP CPU_DBRDY 1 CPU_TEST23 TP_CPU_TEST28_H

CPU_TEST25_H TEST16 TP_CPU_TEST15

RN1004 510R2F-L-GP DYR1022

CPU_TEST20 CPU_TEST12 TEST22 TEST8

CPU_TEST24 R1023 TEST27 CPU_TEST29H

R1029 RN1005 CPU_DBRDY 9 10

TP1003 TP_CPU_VDDIO_SUS_FB_L CPU_TRST#

TP1004 1 TP_CPU_TEST28_H CPU_SIC CPU_TDO 19 20

TP1006 1 TP_CPU_TEST17 (21) CPU_SID CPU_SID +1.5V_SUS 23 24

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

CPU1F 6 OF 6 (36A) for 35W S1G4 VDD

D23 VSS VSS U10 4.7UF *4

HYPER TRANSPORT CPU I/F

(8) HT_CPU_NB_CAD_H8 AC24 HT_RXCAD8P HT_TXCAD8P F21 HT_NB_CPU_CAD_H8 (8)

PCIE_NRX_GTX_N5 GFX_RX10P GFX_TX10P PCIE_NTX_GRX_C_N5 C1212 1 SCD1U10V2KX-5GP PCIE_NTX_GRX_N5

(76) PCIE_RXP0 AE3 AC1 PCIE_C_TXP0 C1264 1 2 SCD1U10V2KX-5GP

UMA DAC Signal: STRAP_DEBUG_BUS_GPIO_ENABLE# ( RS880M use DAC_VSYNC)

or use default values if not connected

1119-1 E12 AVDD2 PART 3 OF 6 TXOUT_L0N B22 VGA_TXAOUT0- (55)

VGA_VSYNC B11 A16 VGA_TXACLK- (55) +1.8V_RUN