5 4 3 2 1

PCB STACK UP
LAYER 1 : TOP
15.6" ZRP Block Diagram 01
LAYER 2 : SVCC
LAYER 3 : IN1
LAYER 4 : IN2
D
LAYER 5 : GND Channel A D

DDRIII-SODIMM TRAVIS_L
LAYER 6 : BOT P12 1333 MHZ
DP0 ANX3111(1 Ch) LVDS PANEL
CPU P25
Memory Down P24
Channel B eDP
256MB*16*4/8 = 2GB
Trinity APU eDP PANEL
P25
(17,19,25W)
Max. 2G P13
DP1 HDMI CONN
35mm X 35mm P26
LAN (Charger) PCIE-1
24PIN FFC
GPP
FP2 813pin BGA
RJ45 Conn. AR8151L P32 Thames Pro VRAM DDR3-256M*4
10/100/1G
P3, 4, 5, 6
PCI-E x 8 GPU Thames XT/Mars VRAM DDR3-128M*8
Thames XT/Mars VRAM DDR3-256M*8
PCIE-0 GFX
X'TAL
25MHz
MINI CARD DP2 UMI Thames Pro/XT VRAM DDRIII
PEG0~8
WLAN+BT USB2-7
Mars P22, 23
Daugther board P28
UMI LINK 29mm X 29mm
DP1(x4) 2.5GT /s P14~21
C C
X'TAL
UMI(x4) 27.0MHz
SATA0
SATA - HDD
P29

14PIN FFC
SATA - ODD
SATA1
SATA VGA-DAC
CRT Con.
P29 P25
Daugther board
SATA2
SATA - SSD
P28

Card Reader 5 IN 1 USB2-5 USB 2.0 (Port0~13) AMD USB 3.0 (Port0~3) USB3-0
Card Reader Con. USB2.0 USB3.0 USB3.0 Con.
P27 (AU6435B53-GDL-GR) P27 Hudson M3 USB2-10 (charger) P31 Charger (BQ24707A)

USB2-6 LAN Daugther board

CCD
P25 FCH SYSTEM 5V/3V (RT8223MP

24.5mm X 24.5mm P35

USB2-0 12PIN FFC
USB Con. DDR 1.5V(TPS51216)
X'TAL
B
P31 25MHz
P8 B
P36
RTC
USB2-3 1.1V_DUAL(TPS51211)
USB Con. X'TAL
32.768KHz P8
P37
BATTERY
P8 +1.2V(TPS51211)/+2.5V
Daugther board P7, 8, 9, 10, 11
Azalia IHDA
P38
NVRAM
LPC +VDD_CORE 1+1 (ISL62771)
SPI P39
P9
LPC
+VGPU CORE(TPS51728)
P40

Audio Codec GPU_POWER/+1.8V_GPU

EC 885L
CX20584 P30 P34
P41

VDDCI(TPS51518)
P42
A INT. MIC HP/MIC Seaker FAN HALL Sensor LED K/B Touch Pad A
Discharge /Thermal
P30 P30 P30 P33 P25 P32 P33 P33
P43

Quanta Computer Inc.

PROJECT :ZRP
Size Document Number Rev
BLOCK DIAGRAM A1A

Date: Friday, July 20, 2012 Sheet 1 of 46

5 4 3 2 1
 5 4 3 2 1

02
BOM Option
Power Sequence
ITEM DESCRIPTION MARK
AC IN
1 LVDS Panel Sku LVDS@ Hudson M3 SMBUS
3V/5VPCU
2 eDP Panel Sku eDP@
FCH SMBUS Pin NO. SMBUS Function Define
3 VGA Sku EV@ NBSWON#
D
PCLK_SMB AD26 D
4 VGA Thames Sku EV_T@ DDR / WLAN
DNBSWON# PDAT_SMB AD25
5 VGA Mars Sku EV_M@ (+3V)
S5_ON/S5
VGA Sku for Thames and Mars stuff SCLK1 T7
6 different value parts EV_SP@ Touch Pad
SDATA1 R7
RSMRST#
(+3V_S5)
7 GPU 128bit Sku EV_128@
SMB_EC_CLK (SCLK2) H19
GPU 128bit Sku of Special part PCIE_WAKE# EC
8 value change EV_128SP@ SMB_EC_DAT (SDATA2) G19
(+3V_S5)
SUSC
9 USB Charge Functions Sku CH@
SCLK3 G22
Not used
10 No USB Charge Functions Sku NCH@ SUSB SDATA3 G21
(+3VPCU)
11 USB3.0 Re-Driver Sku RD@
SUSON
SCL4 J19
12 No USB3.0 Re-Driver Sku NRD@ Not used
SDATA4 K19
MAINON
13 Always connect functions Sku AC@ (+3V_S5)

14 No Always connect functions Sku NAC@ VR_ON

C C

Special part value change or modify

15 for different BOM sku SP@ CPU_CORE
EC SMBUS
16 Key Board Back light Sku KBL@ VRM_PWRGD
KBC SMBUS Pin NO. SMBUS Function Define
17 SSD Sku SSD@
HWPG
18 Touch panel Sku TP@ MBCLK 70
ECPWROK MBDATA 69 Battery, FCH
(+3VPCU)
Page 9 GPIO strap pin SB_PWRGD_IN
APU_SIC_EC 67
ITEM DESCRIPTION MARK CPU RESET APU_SID_EC 68 APU
(+3V_S5)
1 Synaptics touch pad SYNP@ CPU POWER OK
GPUT_CLK 119
2 ELAN touch pad ELAN@
GPUT_DATA 120 GPU
3 For UMA Sku UMA@ (+3V_GFX)

B 4 ELPIDA on board DRAM ELP@ B

TPCLK 72
5 HYNIX on board DRAM HYN@ TPDATA 71 Touch Pad
(+3V)

EC FCH Device I2C_Device(S)

I2Ce_1(M) I2Cf_2(M) Charger Battery ALL/S5

I2Ce_2(M) APU ALL

I2Ce_3(M)

I2Cf_3(M) APU S5

I2Cf_1(M) S5

A
I2Cf_0(M) DDR WLAN/3G Image Sensor S0 A

EC will Conflict with FCH.

Do not mount

Quanta Computer Inc.

PROJECT : ZRP
Size Document Number Rev
SYSTEM INFORMATION A1A

Date: Friday, July 20, 2012 Sheet 2 of 46

5 4 3 2 1
 5 4 3 2 1

03
U25A

14 PEG_RXP0 AP1 AN1 PEG_TXP0_C C537 * PEG_TXP0 14

D P_GFX_RXP[0] P_GFX_TXP[0] PEG_TXN0_C C534 * D
14 PEG_RXN0 AP2 P_GFX_RXN[0] P_GFX_TXN[0] AN2 PEG_TXN0 14
14 PEG_RXP1 AM1 AM4 PEG_TXP1_C C540 * PEG_TXP1 14
P_GFX_RXP[1] P_GFX_TXP[1] PEG_TXN1_C C538 *
14 PEG_RXN1 AM2 P_GFX_RXN[1] P_GFX_TXN[1] AM3 PEG_TXN1 14
14 PEG_RXP2 AK3 AK2 PEG_TXP2_C C541 * PEG_TXP2 14
P_GFX_RXP[2] P_GFX_TXP[2]
PEG X 8

PEG X 8
14 PEG_RXN2 AK4 AK1 PEG_TXN2_C C544 * PEG_TXN2 14
P_GFX_RXN[2] P_GFX_TXN[2] PEG_TXP3_C C550 *
14 PEG_RXP3 AJ1 P_GFX_RXP[3] P_GFX_TXP[3] AH1 PEG_TXP3 14
14 PEG_RXN3 AJ2 AH2 PEG_TXN3_C C557 * PEG_TXN3 14
P_GFX_RXN[3] P_GFX_TXN[3] PEG_TXP4_C C555 *
14 PEG_RXP4 AH4 P_GFX_RXP[4] P_GFX_TXP[4] AF3 PEG_TXP4 14
14 PEG_RXN4 AH3 AF4 PEG_TXN4_C C561 * PEG_TXN4 14
P_GFX_RXN[4] P_GFX_TXN[4] PEG_TXP5_C C563 *
14 PEG_RXP5 AF2 P_GFX_RXP[5] P_GFX_TXP[5] AE1 PEG_TXP5 14
14 PEG_RXN5 AF1 AE2 PEG_TXN5_C C568 * PEG_TXN5 14
P_GFX_RXN[5] P_GFX_TXN[5] PEG_TXP6_C C569 *
14 PEG_RXP6 AD1 P_GFX_RXP[6] P_GFX_TXP[6] AD4 PEG_TXP6 14
14 PEG_RXN6 AD2 AD3 PEG_TXN6_C C565 * PEG_TXN6 14
P_GFX_RXN[6] P_GFX_TXN[6] PEG_TXP7_C C575 *

GRAPHICS
14 PEG_RXP7 AB3 P_GFX_RXP[7] P_GFX_TXP[7] AB2 PEG_TXP7 14
14 PEG_RXN7 AB4 AB1 PEG_TXN7_C C572 * PEG_TXN7 14
P_GFX_RXN[7] P_GFX_TXN[7]
AA1 P_GFX_RXP[8] P_GFX_TXP[8] Y1
FP2 only support PEG X 8 AA2 P_GFX_RXN[8] P_GFX_TXN[8] Y2 FP2 only support PEG X 8
Y4 P_GFX_RXP[9] P_GFX_TXP[9] V3
Y3 P_GFX_RXN[9] P_GFX_TXN[9] V4
V2 P_GFX_RXP[10] P_GFX_TXP[10] U1
V1 P_GFX_RXN[10] P_GFX_TXN[10] U2
T1 P_GFX_RXP[11] P_GFX_TXP[11] T4
C T2 T3 C
P_GFX_RXN[11] P_GFX_TXN[11]
P3 P_GFX_RXP[12] P_GFX_TXP[12] P2
P4 P_GFX_RXN[12] P_GFX_TXN[12] P1
N1 P_GFX_RXP[13] P_GFX_TXP[13] M1
N2 P_GFX_RXN[13] P_GFX_TXN[13] M2
M4 P_GFX_RXP[14] P_GFX_TXP[14] K3
M3 P_GFX_RXN[14] P_GFX_TXN[14] K4
K2 P_GFX_RXP[15] P_GFX_TXP[15] J1
K1 P_GFX_RXN[15] P_GFX_TXN[15] J2

AH5 AG7 PCIE_TXP0_C C45 0.1u/10V_4 PCIE_TXP0_WLAN 28

28 PCIE_RXP0_WLAN P_GPP_RXP[0] P_GPP_TXP[0]
TO WLAN AH6 AG8 PCIE_TXN0_C C53 0.1u/10V_4 PCIE_TXN0_WLAN 28 TO WLAN
28 PCIE_RXN0_WLAN P_GPP_RXN[0] P_GPP_TXN[0]
AG5 AE7 PCIE_TXP1_C C74 0.1u/10V_4 PCIE_TXP1_LAN 32
32 PCIE_RXP1_LAN P_GPP_RXP[1] P_GPP_TXP[1]
TO LAN AG6 AE8 PCIE_TXN1_C C67 0.1u/10V_4 PCIE_TXN1_LAN 32 TO LAN
32 PCIE_RXN1_LAN P_GPP_RXN[1] P_GPP_TXN[1]
AE6 P_GPP_RXP[2] P_GPP_TXP[2] AD7
AE5 P_GPP_RXN[2] P_GPP_TXN[2] AD8
AD6 P_GPP_RXP[3] P_GPP_TXP[3] AB6
AD5 AB5
GPP
P_GPP_RXN[3] P_GPP_TXN[3]
UMI_RXP0 AM10 AN6 UMI_TXP0_C C508 0.1u/10V_4 UMI_TXP0
P_UMI_RXP[0] P_UMI_TXP[0] UMI_TXN0_C C509 0.1u/10V_4
UMI_RXN0 AN10 P_UMI_RXN[0] P_UMI_TXN[0] AM6 UMI_TXN0
UMI_RXP1 AN8 AP6 UMI_TXP1_C C507 0.1u/10V_4 UMI_TXP1
B P_UMI_RXP[1] P_UMI_TXP[1] UMI_TXN1_C C506 0.1u/10V_4 B
UMI_RXN1 AM8 P_UMI_RXN[1] P_UMI_TXN[1] AR6 UMI_TXN1
UMI_RXP2 AP8 AP4 UMI_TXP2_C C511 0.1u/10V_4 UMI_TXP2
P_UMI_RXP[2] P_UMI_TXP[2] UMI_TXN2_C C510 0.1u/10V_4
UMI_RXN2 AR8 P_UMI_RXN[2] P_UMI_TXN[2] AR4 UMI_TXN2
UMI_RXP3 AR7 AP3 UMI_TXP3_C C513 0.1u/10V_4 UMI_TXP3
P_UMI_RXP[3] P_UMI_TXP[3] UMI_TXN3_C C512 0.1u/10V_4
UMI_RXN3 AP7 P_UMI_RXN[3] P_UMI_TXN[3] AR3 UMI_TXN3
UMI

+1.2V_VDDP R372 196/F_6 P_ZVDDP AR11 AP11 P_ZVSS R371 196/F_6

P_ZVDDP P_ZVSS
SP@TRINITY_APU_BGA813

SP : A10(AJ04655UT01)
A8(AJ04555VT01)
A6(AJ04455UT01)
A4(AJ04355UT00)

A A

Quanta Computer Inc.

PROJECT : ZRP
Size Document Number Rev
A1A
APU 1/4(PCIE/UMI/GPP/HDT)
Date: Friday, July 20, 2012 Sheet 3 of 46
5 4 3 2 1
 5 4 3 2 1

Soldermask openings for all bottom side vias/TPs under FS1

04
M_B_DQ[0..63] 13
U25B M_A_DQ[0..63] 12 13 M_B_A[15:0] U25C
12 M_A_A[15:0]
M_A_A0 AA28 F15 M_A_DQ0 M_B_A0 Y33 C16 M_B_DQ0
M_A_A1 MA_ADD[0] MA_DATA[0] M_A_DQ1 M_B_A1 MB_ADD[0] MB_DATA[0] M_B_DQ1
R29 MA_ADD[1] MA_DATA[1] E15 R32 MB_ADD[1] MB_DATA[1] B17
M_A_A2 T30 H19 M_A_DQ2 M_B_A2 T31 B20 M_B_DQ2
M_A_A3 MA_ADD[2] MA_DATA[2] M_A_DQ3 M_B_A3 MB_ADD[2] MB_DATA[2] M_B_DQ3
R28 MA_ADD[3] MA_DATA[3] F19 P33 MB_ADD[3] MB_DATA[3] C20
M_A_A4 R26 E14 M_A_DQ4 M_B_A4 P32 A16 M_B_DQ4
D M_A_A5 MA_ADD[4] MA_DATA[4] M_A_DQ5 M_B_A5 MB_ADD[4] MB_DATA[4] M_B_DQ5 D
P26 MA_ADD[5] MA_DATA[5] H15 P31 MB_ADD[5] MB_DATA[5] B16
M_A_A6 P27 E17 M_A_DQ6 M_B_A6 N32 B19 M_B_DQ6
M_A_A7 MA_ADD[6] MA_DATA[6] M_A_DQ7 M_B_A7 MB_ADD[6] MB_DATA[6] M_B_DQ7
P30 MA_ADD[7] MA_DATA[7] D18 M33 MB_ADD[7] MB_DATA[7] A20
M_A_A8 P29 M_B_A8 M32
M_A_A9 MA_ADD[8] M_A_DQ8 M_B_A9 MB_ADD[8] M_B_DQ8
M28 MA_ADD[9] MA_DATA[8] G20 L32 MB_ADD[9] MB_DATA[8] B22
M_A_A10 AB26 E20 M_A_DQ9 M_B_A10 AB31 C22 M_B_DQ9
M_A_A11 MA_ADD[10] MA_DATA[9] M_A_DQ10 M_B_A11 MB_ADD[10] MB_DATA[9] M_B_DQ10
M26 MA_ADD[11] MA_DATA[10] H23 M31 MB_ADD[11] MB_DATA[10] A26
M_A_A12 M29 G23 M_A_DQ11 M_B_A12 K32 B26 M_B_DQ11
M_A_A13 MA_ADD[12] MA_DATA[11] M_A_DQ12 M_B_A13 MB_ADD[12] MB_DATA[11] M_B_DQ12
AE27 MA_ADD[13] MA_DATA[12] E19 AF33 MB_ADD[13] MB_DATA[12] B21
M_A_A14 L26 H20 M_A_DQ13 M_B_A14 K33 A22 M_B_DQ13
M_A_A15 MA_ADD[14] MA_DATA[13] M_A_DQ14 M_B_A15 MB_ADD[14] MB_DATA[13] M_B_DQ14
12 M_A_BS#[2..0] L27 MA_ADD[15] MA_DATA[14] E22 13 M_B_BS#[2..0] J32 MB_ADD[15] MB_DATA[14] C24
D22 M_A_DQ15 B25 M_B_DQ15
M_A_BS#0 MA_DATA[15] M_B_BS#0 MB_DATA[15]
AB27 MA_BANK[0] AB33 MB_BANK[0]
M_A_BS#1 AA29 H25 M_A_DQ16 M_B_BS#1 AA32 A28 M_B_DQ16
M_A_BS#2 MA_BANK[1] MA_DATA[16] M_A_DQ17 M_B_BS#2 MB_BANK[1] MB_DATA[16] M_B_DQ17
12 M_A_DM[7..0] M30 MA_BANK[2] MA_DATA[17] F25 K31 MB_BANK[2] MB_DATA[17] B28
D28 M_A_DQ18 B31 M_B_DQ18
M_A_DM0 MA_DATA[18] M_A_DQ19 MB_DATA[18] M_B_DQ19
D16 MA_DM[0] MA_DATA[19] D29 13 M_B_DM0 C18 MB_DM[0] MB_DATA[19] A32
M_A_DM1 D20 E23 M_A_DQ20 B23 C26 M_B_DQ20
MA_DM[1] MA_DATA[20] 13 M_B_DM1 MB_DM[1] MB_DATA[20]
M_A_DM2 E25 D24 M_A_DQ21 C28 B27 M_B_DQ21
MA_DM[2] MA_DATA[21] 13 M_B_DM2 MB_DM[2] MB_DATA[21]
M_A_DM3 F30 D26 M_A_DQ22 D31 A30 M_B_DQ22
MA_DM[3] MA_DATA[22] 13 M_B_DM3 MB_DM[3] MB_DATA[22]
M_A_DM4 AK29 D27 M_A_DQ23 AM31 C30 M_B_DQ23
MA_DM[4] MA_DATA[23] 13 M_B_DM4 MB_DM[4] MB_DATA[23]
M_A_DM5 AL25 AN30
MA_DM[5] 13 M_B_DM5 MB_DM[5]
M_A_DM6 AM20 G28 M_A_DQ24 AR24 B33 M_B_DQ24
MA_DM[6] MA_DATA[24] 13 M_B_DM6 MB_DM[6] MB_DATA[24]
M_A_DM7 AM16 G29 M_A_DQ25 AN18 C32 M_B_DQ25
MA_DM[7] MA_DATA[25] 13 M_B_DM7 MB_DM[7] MB_DATA[25]
H27 M_A_DQ26 F33 M_B_DQ26
MA_DATA[26] M_A_DQ27 MB_DATA[26] M_B_DQ27
12 M_A_DQSP0 G17 MA_DQS_H[0] MA_DATA[27] J29 13 M_B_DQSP0 B18 MB_DQS_H[0] MB_DATA[27] F32
H17 E28 M_A_DQ28 A18 B32 M_B_DQ28
12 M_A_DQSN0 MA_DQS_L[0] MA_DATA[28] 13 M_B_DQSN0 MB_DQS_L[0] MB_DATA[28]
F22 F27 M_A_DQ29 B24 C31 M_B_DQ29
12 M_A_DQSP1 MA_DQS_H[1] MA_DATA[29] 13 M_B_DQSP1 MB_DQS_H[1] MB_DATA[29]
G22 H29 M_A_DQ30 A24 E32 M_B_DQ30
12 M_A_DQSN1 MA_DQS_L[1] MA_DATA[30] 13 M_B_DQSN1 MB_DQS_L[1] MB_DATA[30]
E26 H28 M_A_DQ31 B30 F31 M_B_DQ31
C 12 M_A_DQSP2 MA_DQS_H[2] MA_DATA[31] 13 M_B_DQSP2 MB_DQS_H[2] MB_DATA[31] C
12 M_A_DQSN2 F26 MA_DQS_L[2] 13 M_B_DQSN2 B29 MB_DQS_L[2]
12 M_A_DQSP3 H30 MA_DQS_H[3] MA_DATA[32] AH29 M_A_DQ32 13 M_B_DQSP3 D32 MB_DQS_H[3] MB_DATA[32] AK32 M_B_DQ32
12 M_A_DQSN3 G30 MA_DQS_L[3] MA_DATA[33] AJ30 M_A_DQ33 13 M_B_DQSN3 D33 MB_DQS_L[3] MB_DATA[33] AL32 M_B_DQ33
12 M_A_DQSP4 AL29 MA_DQS_H[4] MA_DATA[34] AM28 M_A_DQ34 13 M_B_DQSP4 AM32 MB_DQS_H[4] MB_DATA[34] AP32 M_B_DQ34
12 M_A_DQSN4 AL30 MA_DQS_L[4] MA_DATA[35] AM27 M_A_DQ35 13 M_B_DQSN4 AM33 MB_DQS_L[4] MB_DATA[35] AN31 M_B_DQ35
12 M_A_DQSP5 AH25 MA_DQS_H[5] MA_DATA[36] AH27 M_A_DQ36 13 M_B_DQSP5 AN28 MB_DQS_H[5] MB_DATA[36] AK31 M_B_DQ36
12 M_A_DQSN5 AJ25 MA_DQS_L[5] MA_DATA[37] AH28 M_A_DQ37 13 M_B_DQSN5 AP29 MB_DQS_L[5] MB_DATA[37] AK33 M_B_DQ37
12 M_A_DQSP6 AK20 MA_DQS_H[6] MA_DATA[38] AJ29 M_A_DQ38 13 M_B_DQSP6 AP23 MB_DQS_H[6] MB_DATA[38] AN32 M_B_DQ38
12 M_A_DQSN6 AL20 MA_DQS_L[6] MA_DATA[39] AK27 M_A_DQ39 13 M_B_DQSN6 AP24 MB_DQS_L[6] MB_DATA[39] AP33 M_B_DQ39
12 M_A_DQSP7 AK15 MA_DQS_H[7] 13 M_B_DQSP7 AR18 MB_DQS_H[7]
12 M_A_DQSN7 AL15 MA_DQS_L[7] MA_DATA[40] AK26 M_A_DQ40 13 M_B_DQSN7 AP18 MB_DQS_L[7] MB_DATA[40] AP30 M_B_DQ40
MA_DATA[41] AJ26 M_A_DQ41 MB_DATA[41] AR30 M_B_DQ41
12 M_A_CLKP0 W29 MA_CLK_H[0] MA_DATA[42] AK23 M_A_DQ42 13 M_B_CLKP0 W32 MB_CLK_H[0] MB_DATA[42] AP27 M_B_DQ42
12 M_A_CLKN0 Y30 MA_CLK_L[0] MA_DATA[43] AJ23 M_A_DQ43 13 M_B_CLKN0 Y32 MB_CLK_L[0] MB_DATA[43] AN26 M_B_DQ43
12 M_A_CLKP1 W26 MA_CLK_H[1] MA_DATA[44] AM26 M_A_DQ44 V33 MB_CLK_H[1] MB_DATA[44] AR32 M_B_DQ44
12 M_A_CLKN1 W27 MA_CLK_L[1] MA_DATA[45] AL26 M_A_DQ45 V32 MB_CLK_L[1] MB_DATA[45] AP31 M_B_DQ45
U29 MA_CLK_H[2] MA_DATA[46] AM24 M_A_DQ46 U32 MB_CLK_H[2] MB_DATA[46] AR28 M_B_DQ46
V30 MA_CLK_L[2] MA_DATA[47] AL23 M_A_DQ47 V31 MB_CLK_L[2] MB_DATA[47] AP28 M_B_DQ47
U26 MA_CLK_H[3] T33 MB_CLK_H[3]
U27 MA_CLK_L[3] MA_DATA[48] AK22 M_A_DQ48 T32 MB_CLK_L[3] MB_DATA[48] AP25 M_B_DQ48
MA_DATA[49] AH22 M_A_DQ49 MB_DATA[49] AN24 M_B_DQ49
12 M_A_CKE0 L29 MA_CKE[0] MA_DATA[50] AK19 M_A_DQ50 13 M_B_CKE0 H32 MB_CKE[0] MB_DATA[50] AR22 M_B_DQ50
12 M_A_CKE1 K30 MA_CKE[1] MA_DATA[51] AH19 M_A_DQ51 H33 MB_CKE[1] MB_DATA[51] AP21 M_B_DQ51
MA_DATA[52] AM22 M_A_DQ52 MB_DATA[52] AP26 M_B_DQ52
12 M_A_ODT0 AD30 MA0_ODT[0] MA_DATA[53] AL22 M_A_DQ53 13 M_B_ODT0 AF31 MB0_ODT[0] MB_DATA[53] AR26 M_B_DQ53
12 M_A_ODT1 AG28 MA0_ODT[1] MA_DATA[54] AJ20 M_A_DQ54 AH31 MB0_ODT[1] MB_DATA[54] AN22 M_B_DQ54
AE26 MA1_ODT[0] MA_DATA[55] AL19 M_A_DQ55 AE32 MB1_ODT[0] MB_DATA[55] AP22 M_B_DQ55
AG29 MA1_ODT[1] AH33 MB1_ODT[1]
MA_DATA[56] AK17 M_A_DQ56 MB_DATA[56] AR20 M_B_DQ56
12 M_A_CS#0 AD26 MA0_CS_L[0] MA_DATA[57] AJ17 M_A_DQ57 13 M_B_CS#0 AD31 MB0_CS_L[0] MB_DATA[57] AP19 M_B_DQ57
B AE29 AK14 M_A_DQ58 AF32 AP16 M_B_DQ58 B
12 M_A_CS#1 MA0_CS_L[1] MA_DATA[58] MB0_CS_L[1] MB_DATA[58]
AB30 MA1_CS_L[0] MA_DATA[59] AH14 M_A_DQ59 AC32 MB1_CS_L[0] MB_DATA[59] AR16 M_B_DQ59
AF30 MA1_CS_L[1] MA_DATA[60] AM18 M_A_DQ60 AG32 MB1_CS_L[1] MB_DATA[60] AN20 M_B_DQ60
MA_DATA[61] AL17 M_A_DQ61 MB_DATA[61] AP20 M_B_DQ61
12 M_A_RAS# AB29 MA_RAS_L MA_DATA[62] AH15 M_A_DQ62 13 M_B_RAS# AB32 MB_RAS_L MB_DATA[62] AP17 M_B_DQ62
12 M_A_CAS# AD29 MA_CAS_L MA_DATA[63] AL14 M_A_DQ63 13 M_B_CAS# AD32 MB_CAS_L MB_DATA[63] AN16 M_B_DQ63
12 M_A_WE# AD28 MA_WE_L 13 M_B_WE# AD33 MB_WE_L

12 M_A_RST# J28 MA_RESET_L 13 M_B_RST# H31 MB_RESET_L

12 M_A_EVENT# AA26 MA_EVENT_L TP8 Y31 MB_EVENT_L

+MEMVREF_CPU G32 M_VREF SP@TRINITY_APU_BGA813

+1.5VSUS R410 39.2/F_4 +M_ZVDDIO AJ32 M_ZVDDIO

SP : A10(AJ04655UT01)
Place close to APU within 1" SP@TRINITY_APU_BGA813 A8(AJ04555VT01)
A6(AJ04455UT01)
+1.5VSUS
A4(AJ04355UT00)
SP : A10(AJ04655UT01)
A8(AJ04555VT01)
A6(AJ04455UT01)
A4(AJ04355UT00)
R179

1K/F_4
+MEMVREF_CPU

A A
R186 *Short_4

R178
C319 C321 C317
1K/F_4 0.47u/6.3V_4 0.1u/10V_4 1000p/50V_4
Quanta Computer Inc.
PROJECT : ZRP
Size Document Number Rev
A1A
APU 2/4(DDR3 MEM I/F)
Date: Friday, July 20, 2012 Sheet 4 of 46
5 4 3 2 1
 5 4 3 2 1

05
+3V

U25D
C613 0.1u/10V_4 INT_LVDS_TXP0_C H2 INT_LVDS_AUXP_C C217 0.1u/10V_4 INT_LVDS_AUXP_C R462 1.8K_4 R190
INT_LVDS_TXP0
C612 0.1u/10V_4 INT_LVDS_TXN0_C H1 DP0_TXP[0] DP0_AUXP M5
INT_LVDS_AUXN_C C218 0.1u/10V_4
INT_LVDS_AUXP 24
INT_LVDS_AUXN_C R452 1.8K_4
LVDS / eDP *
DP0 INT_LVDS_TXN0 DP0_TXN[0] DP0_AUXN M6 INT_LVDS_AUXN 24
C611 0.1u/10V_4 INT_LVDS_TXP1_C H3 INT_HDMI_AUXP
LVDS/eDP L5

DISPLAY PORT 0
INT_LVDS_TXP1 DP0_TXP[1] DP1_AUXP INT_HDMI_AUXP 26
INT_LVDS_TXN1 C607 0.1u/10V_4 INT_LVDS_TXN1_C H4 L6 INT_HDMI_AUXN R191
DP0_TXN[1] DP1_AUXN INT_HDMI_AUXN 26 eDP_BL_EN 25
*

3
APU_DP_AUXP_C C263 0.1u/10V_4 APU_DP_AUXP APU_DP_AUXP_C R472 1.8K_4
F4
F3
DP0_TXP[2] DP2_AUXP J5
J6 APU_DP_AUXN_C C253 0.1u/10V_4 APU_DP_AUXN
APU_DP_AUXP 9
APU_DP_AUXN_C R467 1.8K_4
FCH VGA
DP0_TXN[2] DP2_AUXN APU_DP_AUXN 9
F1 P5 2 Q13
DP0_TXP[3] DP3_AUXP *
F2 DP0_TXN[3] DP3_AUXN P6
D D

DISPLAY PORT MISC.

3
C614 0.1u/10V_4 INT_HDMI_TXDP2_C E2 R5
26 INT_HDMI_TXDP2 DP1_TXP[0] DP4_AUXP
C616 0.1u/10V_4 INT_HDMI_TXDN2_C E1 R6
26 INT_HDMI_TXDN2

1
DP1_TXN[0] DP4_AUXN APU_BLEN 2
C621 0.1u/10V_4 INT_HDMI_TXDP1_C D4 U5

DISPLAY PORT 1
26 INT_HDMI_TXDP1 DP1_TXP[1] DP5_AUXP +1.5VSUS
C627 0.1u/10V_4 INT_HDMI_TXDN1_C D3
DP1 26 INT_HDMI_TXDN1 DP1_TXN[1] DP5_AUXN U6
R199 Q14

1
C624 0.1u/10V_4 INT_HDMI_TXDP0_C D1 INT_LVDS_eDP_HPD_Q * *
HDMI 26 INT_HDMI_TXDP0
C629 0.1u/10V_4 INT_HDMI_TXDN0_C D2 DP1_TXP[2] DP0_HPD M7
L7
26 INT_HDMI_TXDN0 DP1_TXN[2] DP1_HPD INT_HDMI_HPD 26
J7 INT_VGA_HPD_Q
C631 0.1u/10V_4 INT_HDMI_TXCP_C C1 DP2_HPD
26 INT_HDMI_TXCP DP1_TXP[3] DP3_HPD P7
C635 0.1u/10V_4 INT_HDMI_TXCN_C C2 R7 R413 +3V
26 INT_HDMI_TXCN DP1_TXN[3] DP4_HPD
U7 *39.2/F_4
C639 0.1u/10V_4 APU_DP_TXP0_C DP5_HPD
APU_DP_TXP0 B2 DP2_TXP[0]
C643 0.1u/10V_4 APU_DP_TXN0_C A2 C6 APU_BLEN M_TEST
APU_DP_TXN0 DP2_TXN[0] DP_BLON
D7 APU_DIGON
C658 0.1u/10V_4 APU_DP_TXP1_C DP_DIGON R206
DP2 B3 A6

DISPLAY PORT 2
APU_DP_TXP1 DP2_TXP[1] DP_VARY_BL APU_VARY_BL 24
C657 0.1u/10V_4 APU_DP_TXN1_C A3 M_TEST CONNECTION TBD *
APU_DP_TXN1 DP2_TXN[1] DP_AUX_ZVSS R513 150/F_4 To AMD HDT R418
Hudson-M3 VGA output C656 0.1u/10V_4 APU_DP_TXP2_C B4
DP_AUX_ZVSS B6
39.2/F_4
APU_DP_TXP2 DP2_TXP[2]
C655 0.1u/10V_4 APU_DP_TXN2_C A4 AL6 R205
APU_DP_TXN2 DP2_TXN[2] TEST6 eDP_DIGON 25
Y23 APU_TEST9 *
TEST9 TP9

3
C654 0.1u/10V_4 APU_DP_TXP3_C B5 V23 APU_TEST10
APU_DP_TXP3 DP2_TXP[3] TEST10 TP12
C653 0.1u/10V_4 APU_DP_TXN3_C A5 G9 APU_TEST14_BP0
APU_DP_TXN3 DP2_TXN[3] TEST14 TP19
F9 APU_TEST15_BP1
TEST15 TP18
AL9 E9 APU_TEST16_BP2 2 Q18
CLK_APU_HCLKP CLKIN_H TEST16 TP20 +1.5VSUS
Note: CLK_APU_HCLKP/N is 100MHZ SSC AK9 G8 APU_TEST17_BP3 *
CLK_APU_HCLKN CLKIN_L TEST17 TP17
APU_TEST18_PLLTEST1 R210 1K_4

TEST
TEST18 F12

3
AL7 E12 APU_TEST19_PLLTEST0 R209 1K_4

CLK
CLK_DP_NSSCP DISP_CLKIN_H TEST19
Note: CLK_DP_NSSCP/N is 100MHZ non-SSC AK7 F14 APU_TEST20_SCANCLK2 R212 1K_4
CLK_DP_NSSCN

1
DISP_CLKIN_L TEST20 APU_TEST24_SCANCLK1 R211 1K_4 APU_DIGON
TEST24 G12 2
SVC E5 AJ8 APU_TEST25_H R397 510/F_4
SVD SVC TEST25_H APU_TEST25_L R91 510/F_4 R402
E6 SVD TEST25_L AH8 +1.2V_VDDP
G14 300_4 R207 Q19

1
TEST28_H

SER.
2012-07-11 R521 *short_4 APU_SVT_R D6 H14 * *
C APU_SVT SVT TEST28_L C
Must be reserved +1.5V R514 *1K_4 V25 APU_TEST30_H APU_TEST35
TEST30_H TP11
APU_SIC AJ11 Y25 APU_TEST30_L
the two footprint. SIC TEST30_L TP10
APU_SID AH11 AH32 M_TEST DMAACTIVE_L controls
SID TEST31
EC +1.5VSUS R48 300_4 C787 150P/10V_4
AK11
TEST32_H R25
T25
APU_TEST32_H
APU_TEST32_L
TP16 entry and exit from the 7/8 For Comal.
R405
APU_RST# RESET_L TEST32_L TP14 sleep and power states
FCH APU_PWRGD_BUF
R55 300_4 C788 150P/10V_4
AH9 PWROK TEST35 AL5 APU_TEST35
R364 1K_4
*300_4 +3V
+1.5VSUS +1.5VSUS
R35 1K_4 H_PROCHOT# TEST35 PU FOR INTERNAL

CTRL
+1.5VSUS AL12 PROCHOT_L DMAACTIVE_L AP10 DMAACTIVE_L 8
APU_THERMTRIP#_C AK5 TEST35 PD FOR CUSTOMER
34 H_PROCHOT# +1.5VSUS THERMTRIP_L
APU_ALERT AR10 T23 CPU_THERMDA +5V
ALERT_L TEST4 TP13 R164
APU Core Power R532 1K_4 APU_TDI E11
TEST5 R23 CPU_THERMDC
TP15 1K_4
APU_TDO TDI
TP37 G11 TDO
20120-7-16 R543 1K_4 APU_TCK H12 TCK INT_VGA_HPD_Q R171
VIN R537 1K_4 APU_TMS

JTAG
For APU_PWRGD used F11 TMS RSVD L8
R495 1K_4 APU_TRST# 10K_4

3
H11 TRST_L RSVD P8 2N7002KDW_115MA
APU_DBRDY E8 AH12
TP40 DBRDY RSVD
R519 1K_4 APU_DBREQ#

RSVD
E7 DBREQ_L RSVD AJ12
C789 C790 5
RSVD AK12

6
39 APU_VDD_RUN_FB_L G6 VSS_SENSE Q12B 2N7002KDW_115MA
*0.1u/25V_4 *0.1u/25V_4 H6
TP36 VDDP_SENSE +1.5VSUS

4
39 APU_VDDNB_RUN_FB_H H5 VDDNB_SENSE +1.5VSUS FCH_VGA_HPD
2 FCH_VGA_HPD
G7

SENSE
TP38 VDDIO_SENSE
39 APU_VDD_RUN_FB_H G5 VDD_SENSE Q12A
TP39 H7 VDDR_SENSE R174

1
100K_4
SP@TRINITY_APU_BGA813 R124 C796
*300_4 *0.1u/10V_4
R168 *0_4

5
+1.5VSUS SP : A10(AJ04655UT01) U35
A8(AJ04555VT01) 8 APU_PWRGD 2
4 APU_PWRGD_BUF +3V
3

A6(AJ04455UT01) 1 *SN74AUP1G17DCKR
Q39 A4(AJ04355UT00)
B B
C795

3
FCH_PWRGD 2 R160 +5V
*150P/10V_4
LVDS@1K_4
+1.5VSUS FDV301N_200MA
INT_LVDS_eDP_HPD_Q R158
1

R399 100K_4 R316 0_4

LVDS@10K_4

3
LVDS@2N7002KDW_115MA
R390 R400 R398
10K_4 1K_4 1K_4 5

6
Q10B LVDS@2N7002KDW_115MA
Q41
METR3904-G_200MA

4
2

Q40 2 INT_LVDS_eDP_HPD
METR3904-G_200MA
Q10A
3 1 APU_THERMTRIP#_C 1 3 SYS_SHDN#
APU_THERMTRIP# SYS_SHDN# 15,35,40,43 BOOT VOLTAGE R163

1
100K_4

SVC SVD VFIX_+VDD VFIX_+VDD

=VCC/GND =OPEN R167 *

0 0 1.1 1.1
+1.5VSUS +1.5VSUS +1.5VSUS

0 1 1.0 1.2
+1.5V

R325 R339 R340 R351 R355 R10 R369 1 0 0.9 1.0

2K/F_4 2K/F_4 1K_4 1K_4 2K/F_4 *2K/F_4 1K_4
1 1 0.8 0.8 R491 R487 R197
*1K_4 *1K_4 *2.2K_4
2

A A
Q28
METR3904-G_200MA
Fan Q34
METR3904-G_200MA
APU_SIC APU_ALERT SVC R492 Rd 0_4 APU_SVC
34 APU_SIC_EC 3 1 33,34 SML1ALERT# 3 1 APU_SVC
SVD R486 Re 0_4 APU_SVD APU_SVD
1 2 1 2 Rf 0_4
D21 D23 APU_PWRGD_BUF R189 APU_PWRGD_SVID_REG APU_PWRGD_SVID_REG
RB500V-40_100MA RB500V-40_100MA
2

Q27
METR3904-G_200MA APU_SID
Q5
*METR3904-G_200MA H_PROCHOT# R494 R489 R194
for normal operation Quanta Computer Inc.
34 APU_SID_EC 3 1 3 1 open Ra , Rb,Rc
*220_4 *220_4 *220_4 C327
Ra Rb Rc *0.1u/10V_4
PROJECT : ZRP
1 2 1 2 Size Document Number Rev
D20 *RB500V-40_100MA D3 A1A
RB500V-40_100MA
APU 3/4(Display/Misc)
Date: Friday, July 20, 2012 Sheet 5 of 46
5 4 3 2 1
 5 4 3 2 1

06
U25F
A17 VSS VSS Y11
A19 VSS VSS Y12
+VDD_CORE +VDD_CORE 22A A21
A23
VSS VSS Y14
Y15
VSS VSS
U25E Maximum IDDspike 35A A25
A27
VSS VSS Y17
Y19
VSS VSS
J12 VDD VDD V17 A29 VSS VSS Y20
22A J14
J15
VDD VDD V19
V20
A31
B1
VSS VSS Y22
AA4
+VDDNB_CORE VDD VDD C145 C266 C265 C188 C193 C240 C189 C144 VSS VSS
Maximum IDDNBspike 33A J17
J19
VDD VDD V22
W8 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8
C3
C4
VSS VSS AA5
AB7
VDD VDD VSS VSS
J20 VDD VDD AA8 C33 VSS VSS AB8
D J22 AA9 D5 AC1 D
VDD VDD VSS VSS
M11 VDD VDD AA11 D9 VSS VSS AC2
C652 C676 C659 C681 M12 AA12 D11 AC4
22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 VDD VDD VSS VSS
M14 VDD VDD AA14 D13 VSS VSS AC9
M15 AA15 C238 C237 C292 C190 C134 C291 C293 D15 AC11
VDD VDD 22u/6.3V_8 22u/6.3V_8 *22u/6.3V_8 *22u/6.3V_8 *22u/6.3V_8 *22u/6.3V_8 *22u/6.3V_8 VSS VSS
M17 VDD VDD AA17 D17 VSS VSS AC12
M19 VDD VDD AA19 D19 VSS VSS AC14
M20 VDD VDD AA20 D21 VSS VSS AC15
M22 VDD VDD AA22 D23 VSS VSS AC17
R8 VDD VDD AD9 D25 VSS VSS AC19
C341 C335 C340 C345 C333 R9 AD11 D30 AC20
0.22u/10V_4 0.22u/10V_4 180p/50V_4 180p/50V_4 180p/50V_4 VDD VDD VSS VSS
R11 VDD VDD AD12 E4 VSS VSS AC22
R12 AD14 C219 C116 C143 C224 C117 C115 C223 C169 C221 E27 AC23
VDD VDD 0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 0.01u/25V_4 0.01u/25V_4 0.01u/25V_4 0.01u/25V_4 0.01u/25V_4 VSS VSS
R14 VDD VDD AD15 E29 VSS VSS AC25
R15 VDD VDD AD17 E30 VSS VSS AE4
For EMI R17
R19
VDD VDD AD19
AD20
E33
F5
VSS VSS AF9
AF11
VDD VDD VSS VSS
R20 VDD VDD AD22 F6 VSS VSS AF12
R22 VDD VDD AG12 F7 VSS VSS AF14
C168 C267 C220 C167
U8
V9
VDD VDD AG14
AG15 180p/50V_4 180p/50V_4 180p/50V_4 180p/50V_4 For EMI F8
F17
VSS VSS AF15
AF17
VDD VDD VSS VSS
V11 VDD VDD AG17 F20 VSS VSS AF19
V12 VDD VDD AG19 F23 VSS VSS AF20
V14 VDD VDD AG20 F28 VSS VSS AF22
+VDDNB_CAP V15 AG22 F29 AF23
+VDDNB_CORE VDD VDD +VDDNB_CORE VSS VSS
G1 VSS VSS AF25
G2 VSS VSS AG1
A7 VDDNB VDDNB B11 G4 VSS VSS AG2

C242 C294 C264 C234 C586

A8 VDDNB VDDNB B12 APU POWER TABLE G15 VSS VSS AG4
A9 VDDNB VDDNB B13 G19 VSS VSS AG9
C 180p/50V_4 *22u/6.3V_8 *22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 A10 B14 PIN NAME NET NAME VOLTAGE G25 AG11 C
VDDNB VDDNB VSS VSS
A11 VDDNB VDDNB B15 G26 VSS VSS AG26
A12 C8 VDD +VDD_CORE 1.0V ~ 1.3V G27 AH7
VDDNB VDDNB VSS VSS
A13 VDDNB VDDNB C10 G33 VSS VSS AH17
A14 C12 VDDNB +VDDNB_CORE 1.05V ~ 1.325V H8 AH20
VDDNB VDDNB VSS VSS
A15 VDDNB VDDNB C14 H9 VSS VSS AH23
B7 D8 VDDIO +1.5VSUS 1.5V H22 AH26
VDDNB VDDNB VSS VSS
B8 VDDNB VDDNB D10 H26 VSS VSS AH30
B9 D12 VDDP +1.2V_VDDP +1.2V J4 AJ4
VDDNB VDDNB +VDDNB_CAP VSS VSS
B10 VDDNB VDDNB D14 J8 VSS VSS AJ5
VDDR +1.2V_VDDR +1.2V J9 AJ6
VSS VSS
VDDNB_CAP M9 J11 VSS VSS AJ7
+1.5VSUS N9 VDDA +2.5V_VDDA +2.5V J23 AJ9
VDDNB_CAP VSS VSS
2.3A Up to DDR3-1333 @ 1.5V VDDIO J25 VSS VSS AJ14
J33 VDDIO VDDIO W33 J26 VSS VSS AJ15
K23 AA23 +1.5VSUS J27 AJ19
VDDIO VDDIO VSS VSS
K25 VDDIO VDDIO AA25 J30 VSS VSS AJ22
C122 C114 C124 C125 C273 C183 L28 AA27 K9 AJ27
0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 VDDIO VDDIO VSS VSS
L30 VDDIO VDDIO AA30 K11 VSS VSS AJ28
L33 VDDIO VDDIO AA33 K12 VSS VSS AJ33
M27 AB28 C277 C157 C256 C222 C302 C130 K14 AK6
VDDIO VDDIO 22u/6.3V_8 22u/6.3V_8 4.7u/6.3V_6 4.7u/6.3V_6 4.7u/6.3V_6 4.7u/6.3V_6 VSS VSS
N23 VDDIO VDDIO AC30 K15 VSS VSS AK8
N25 VDDIO VDDIO AC33 K17 VSS VSS AK25
N30 VDDIO VDDIO AD23 K19 VSS VSS AK28
C275 C184 C186 C123 N33 AD25 K20 AK30
0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 VDDIO VDDIO VSS VSS
P28 VDDIO VDDIO AD27 K22 VSS VSS AL1
R27 VDDIO VDDIO AE28 L1 VSS VSS AL2
R30 AE30 C241 C108 C276 C204
R33
VDDIO VDDIO
AE33 180p/50V_4 180p/50V_4 180p/50V_4 180p/50V_4 For EMI L2
L4
VSS VSS AL4
AL8
+1.2V_VDDP VDDIO VDDIO VSS VSS
U28 VDDIO VDDIO AG23 M8 VSS VSS AL11
B B
R75 *short_8
VDDP = 3.5A U30 VDDIO VDDIO AG25 M23 VSS VSS AL27
+1.2V U33 VDDIO VDDIO AG27 M25 VSS VSS AL28
W28 VDDIO VDDIO AG30 N4 VSS VSS AL33
+1.2V_VDDR +1.2V
C93 C502 C503 C100
W30 VDDIO VDDIO AG33 VDDR = 3.2A ( Up to DDR3-1333 @ 1.5V ) N11 VSS VSS AM5
N12 VSS VSS AM7
22u/6.3V_8 22u/6.3V_8 *22u/6.3V_8 0.22u/10V_4 AM12 AN14 R376 *short_8 N14 AM9
VDDP VDDR VSS VSS
AN12 VDDP VDDR AP14 N15 VSS VSS AM11
AP12 VDDP VDDR AP15 N17 VSS VSS AM15
AP13 AR14 C50 C51 C499 C52 C498 C500 C47 N19 AM17
VDDP VDDR 0.22u/10V_4 0.22u/10V_4 1000p/50V_4 180p/50V_4 180p/50V_4 4.7u/6.3V_6 4.7u/6.3V_6 VSS VSS
AR12 VDDP VDDR AR15 N20 VSS VSS AM19
AR13 VDDP N22 VSS VSS AM21
R1 VSS VSS AM23
C98 C102 C90 C99 C101 AA6 R2 AM25
180p/50V_4 180p/50V_4 1000p/50V_4 1000p/50V_4 0.22u/10V_4 +VDDP_CAP VDDP_CAP VSS VSS
AA7 VDDP_CAP R4 VSS VSS AM29
T9 VSS VSS AM30
AM13 VDDA SP : A10(AJ04655UT01) T11 VSS VSS AN3
AM14 VDDA A8(AJ04555VT01) T12 VSS VSS AN4
C49 C48 T14 AN33
0.01u/25V_4 0.01u/25V_4 A6(AJ04455UT01) VSS VSS
SP@TRINITY_APU_BGA813 T15 VSS VSS AP5
C208 C574 A4(AJ04355UT00) T17 AP9
*22u/6.3V_8 22u/6.3V_8 VSS VSS
T19 VSS VSS AR2
T20 VSS VSS AR5
T22 VSS VSS AR9
U4 VSS VSS AR17
+2.5V_VDDA
VDDA= 0.75A W1 VSS VSS AR19

+2.5V L5 DECOUPLING between PROCESSOR and DIMMs W2

W4
VSS VSS AR21
AR23
HCB1608KF-221T20_2A VSS VSS
W5 VSS VSS AR25
+1.5VSUS
C38 C37 C41 C39 Across VDDIO and VSS split W6
W7
VSS VSS AR27
AR29
A 4.7u/6.3V_6 0.22u/10V_4 3300p/50V_4 1000p/50V_4 VSS VSS A
Y9 VSS VSS AR31

SP@TRINITY_APU_BGA813
C181 C227 C178 C268 C309 C121 C185 C310 C126 C274
4.7u/6.3V_6 4.7u/6.3V_6 4.7u/6.3V_6 4.7u/6.3V_6 0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 39p/50V_4 39p/50V_4
SP : A10(AJ04655UT01)
A8(AJ04555VT01)
A6(AJ04455UT01)
Quanta Computer Inc.
If the VSS plane is cut to create a VDDIO plane,
A4(AJ04355UT00) ceramic capacitors are connected across PROJECT : ZRP
the VDDIO and VSS plane split as follows Size Document Number Rev
A1A
APU 4/4(POWER/GND)
Date: Saturday, July 21, 2012 Sheet 6 of 46
5 4 3 2 1
 5 4 3 2 1

+3V_S5
NC,no install by default
07
R251 *2.2K_4 FCH_TEST0

R226 *2.2K_4 FCH_TEST1 U34A

PCIE_RST2# AB6 G8
TP42 PCIE_RST2#/GEVENT4# USBCLK/14M_25M_48M_OSC
34 EC_WLAN_WAKE# R2 RI#/GEVENT22#
R231 *2.2K_4 FCH_TEST2 W7 B9 USB_RCOMP_SB R290 11.8K/F_6
D 29 ODD_PLUGIN# SPI_CS3#/GBE_STAT1/GEVENT21# USB_RCOMP D
SUSB# T3 SLP_S3#
34 SUSC# W2 H1 TP59

MISC
SLP_S5# USB_FSD1P/GPIO186

USB
remove pull hi ( chip internal have pull hi ) R618 *short_4 PWR_BTN# J4 H3
34 DNBSWON# PWR_BTN# USB_FSD1N TP60
FCH_PWRGD N7 PWR_GOOD HUDSON-M3 USB_FSD0P/GPIO185 H6 TP58
FCH_TEST0 T9 Part 4 of 5 H5
+3V TEST0 USB_FSD0N TP61
FCH_TEST1 T10

USB
FCH_TEST2 TEST1/TMS

1.1
ACPI / WAKE UP
V9 TEST2 USB_HSD13P H10
R248 2.2K_4 PCLK_SMB AE22 G10
34 SIO_A20GATE GA20IN/GEVENT0# USB_HSD13N
34 SIO_RCIN# AG19 KBRST#/GEVENT1#
R245 2.2K_4 PDAT_SMB R9 K10

EVENTS
34 SIO_EXT_SCI# PME#/GEVENT3# USB_HSD12P
34 SIO_EXT_SMI# C26 LPC_SMI#/GEVENT23# USB_HSD12N J12
R524 *10K_4 GPIO65 GEVENT5# T5
SYS_RST#
TP57
U4
LPC_PD#/GEVENT5#
SYS_RESET#/GEVENT19# USB_HSD11P G12 HUB3
PCIE_WAKE# K1 F12
32 PCIE_WAKE# WAKE#/GEVENT8# USB_HSD11N
GEVENT20# V7
TP43 IR_RX1/GEVENT20#
APU_THERMTRIP# R10 K12 USBP10+ 31
APU_THERMTRIP# THRMTRIP#/SMBALERT#/GEVENT2# USB_HSD10P
+3V R229 10K/F_4 WD_PWRGD AF19 K13 USBP10- 31 USB2.0 co-lay USB3.0 port
+3V_S5 WD_PWRGD USB_HSD10N

34 PCH_RSMRST# U2 RSMRST# USB_HSD9P B11

R249 2.2K_4 SCLK1 R583 10K_4 D11
USB_HSD9N
AG24 CLK_REQ4#/SATA_IS0#/GPIO64
R246 2.2K_4 SDATA1 AE24 E10 USBP8+ 25
32 PCIE_REQ_LAN# CLK_REQ3#/SATA_IS1#/GPIO63 USB_HSD8P
9 BOARD_ID8 AE26 SMARTVOLT1/SATA_IS2#/GPIO50 USB_HSD8N F10 USBP8- 25 Touch Panel
R228 *10K_4 VGA_PD 9 BOARD_ID9 AF22 CLK_REQ0#/SATA_IS3#/GPIO60
24 TRAVIS_EN# AH17 SATA_IS4#/FANOUT3/GPIO55 USB_HSD7P C10 USBP7+ 28
R585 10K_4 SYS_RST# AG18 A10 WLAN
30 SPKR AF24
SATA_IS5#/FANIN3/GPIO59
SPKR/GPIO66
USB_HSD7N USBP7- 28 HUB2
PCLK_SMB AD26 H9 USBP6+ 25
12,13,28 PCLK_SMB SCL0/GPIO43 USB_HSD6P
PDAT_SMB AD25 G9 USBP6- 25 CCD on LVDS
12,13,28 PDAT_SMB

USB
SCLK1 SDA0/GPIO47 USB_HSD6N

2.0
33 SCLK1 T7 SCL1/GPIO227
SDATA1 R7 A8 USBP5+ 27
C +3V_S5 33 SDATA1 SDA1/GPIO228 USB_HSD5P C
AG25 CLK_REQ2#/FANIN4/GPIO62 USB_HSD5N C8 USBP5- 27 Card Reader
AG22

GPIO
28 PCIE_REQ_WLAN# CLK_REQ1#/FANOUT4/GPIO61
R634 10K_4 APU_THERMTRIP# J2 F8
R289 10K_4 OC_1# GPIO51 IR_LED#/LLB#/GPIO184 USB_HSD4P
TP54 AG26 SMARTVOLT2/SHUTDOWN#/GPIO51 USB_HSD4N E8
R234 10K_4 OC_0# VGA_PD V8
VGA_PD DDR3_RST#/GEVENT7#/VGA_PD
R584 10K_4 FCH_JTAG_TCK W8 C6 USBP3+ 31
GBE_LED0/GPIO183 USB_HSD3P
9 SPI_HOLD# Y6 SPI_HOLD#/GBE_LED1/GEVENT9# USB_HSD3N A6 USBP3- 31 USB2.0 daughter
25 TP_INT_FCH V10 GBE_LED2/GEVENT10#
AA8 C5
15 PCIE_REQ_GPU#
R501 *EV_M@0_4 GPIO65 AF25
GBE_STAT0/GEVENT11#
CLK_REQG#/GPIO65/OSCIN/IDLEEXIT#
USB_HSD2P
USB_HSD2N A5 HUB1
USB_HSD1P C1
FCH_BLINK M7 C3
TP45 BLINK/USB_OC7#/GEVENT18# USB_HSD1N
SMBALERT#_R R8
GEVENT17# USB_OC6#/IR_TX1/GEVENT6#
TP56 T1 USB_OC5#/IR_TX0/GEVENT17# USB_HSD0P E1 USBP0+ 31
+3V_S5
29 ODD_EJ P6 USB_OC4#/IR_RX0/GEVENT16# USB_HSD0N E3 USBP0- 31 USB2.0 debug port daughter
FCH_JTAG_TDO F5
TP62 USB_OC3#/AC_PRES/TDO/GEVENT15#
FCH_JTAG_TCK P5 C16 USBSS_CALRP R652 1K/F_4
USB_OC2#/TCK/GEVENT14#

USB
R631 10K_4 PCIE_WAKE# R287 *short_4 FCH_JTAG_TDI USBSS_CALRP USBSS_CALRN R656 1K/F_4

OC
31 OC_1# J7 USB_OC1#/TDI/GEVENT13# USBSS_CALRN A16 +FCH_VDD_11_SSUSB_S
R632 10K_4 PWR_BTN# 31 OC_0# R238 *short_4 FCH_JTAG_RST# T8 USB_OC0#/SPI_TPM_CS#/TRST#/GEVENT12#
USB_SS_TX3P A14
GEVENT12# ~18# USB_SS_TX3N C14
are +3V_S5
HDaudio ACZ_BCLK_R AB3 C12
Note:LLB#, WAKE# and PWR_BTN need pull up to +3VPCU only if S5+ mode is supported ACZ_SDOUT_R AZ_BITCLK USB_SS_RX3P
interface AB1 AZ_SDOUT USB_SS_RX3N A12
5 6 ACZ_SDIN0 AA2
are ACZ_SDIN1 AZ_SDIN0/GPIO167
4 7 Y5 AZ_SDIN1/GPIO168 USB_SS_TX2P D15
+3V_S5 3 8 ACZ_SDIN2 Y3 B15
ACZ_SDIN3 AZ_SDIN2/GPIO169 USB_SS_TX2N
2 9 Y1 AZ_SDIN3/GPIO170
1 10 ACZ_SYNC_R AD6 E14
ACZ_RST#_R AZ_SYNC USB_SS_RX2P
AE4 F14
To Azalia R242 *10KX8
+3V_S5
AZ_RST# USB_SS_RX2N

USB
B F15 B

AUDIO

3.0
USB_SS_TX1P
TP44 K19 PS2_DAT/SDA4/GPIO187 USB_SS_TX1N G15

HD
ACZ_SDOUT_R R581 33_4 ACZ_SDOUT J19
ACZ_SDOUT_AUDIO 30 TP46 PS2_CLK/CEC/SCL4/GPIO188
20120712 J21 H13
SPI_CS2#/GBE_STAT2/GPIO166 USB_SS_RX1P
ACZ_SYNC_R R570 33_4 ACZ_SYNC
ACZ_SYNC_AUDIO 30 Add for S3 leakage USB_SS_RX1N G13
R660 R650
ACZ_BCLK_R R572 33_4 ACZ_BITCLK *EV@10K_4 *EV@10K_4 D21 J16 USB3_TXP0 USB3_TXP0 31
ACZ_BITCLK_AUDIO 30 PS2KB_DAT/GPIO189 USB_SS_TX0P
C20 H16 USB3_TXN0 USB3_TXN0 31
PS2KB_CLK/GPIO190 USB_SS_TX0N
DGPU_RST_L D23 PS2M_DAT/GPIO191 USB3.0
C705 33P/50V_4 C22 J15 USB3_RXP0 USB3_RXP0 31
40,41,42 DGPU_PWREN PS2M_CLK/GPIO192 USB_SS_RX0P
K15 USB3_RXN0 USB3_RXN0 31
USB_SS_RX0N
ACZ_RST#_R R568 33_4 ACZ_RST# 1 2 F21
ACZ_RESET#_AUDIO 30 34 SUSB# KSO_0/GPIO209
D29 RB500V-40_100MA E20 H19 SMB_EC_CLK
ACZ_SDIN0 KSO_1/GPIO210 SCL2/GPIO193 SMB_EC_DAT
ACZ_SDIN0 30 F20 KSO_2/GPIO211 SDA2/GPIO194 G19 GPIO193 ~196 are +3V_S5
31,34,36,38,43 MAINON 1 2 A22 KSO_3/GPIO212 SCL3_LV/GPIO195 G22
D30 RB500V-40_100MA E18 G21
KSO_5 KSO_4/GPIO213 SDA3_LV/GPIO196
A20 KSO_5/GPIO214 EC_PWM0/EC_TIMER0/GPIO197 E22
+3V_S5 R293 *10K_4 J18 H22
KSO_6/GPIO215 EC_PWM1/EC_TIMER1/GPIO198
H18 KSO_7/GPIO216 EC_PWM2/EC_TIMER2/WOL_EN/GPIO199 J22 EC_PWM2 11
G18 KSO_8/GPIO217 EC_PWM3/EC_TIMER3/GPIO200 H21
2 1 B21 KSO_9/GPIO218
G2 *SHORT_PAD K18 K21
KSO_10/GPIO219 EMBEDDED KSI_0/GPIO201
D19 KSO_11/GPIO220 KSI_1/GPIO202 K22
A18 CTRL F22
KSO_12/GPIO221 KSI_2/GPIO203
C18 KSO_13/GPIO222 KSI_3/GPIO204 F24
+3V_S5 B19 E24
KSO_14/XDB0/GPIO223 KSI_4/GPIO205
B17 KSO_15/XDB1/GPIO224 KSI_5/GPIO206 B23
+3V A24 C24
KSO_16/XDB2/GPIO225 KSI_6/GPIO207
D17 KSO_17/XDB3/GPIO226 KSI_7/GPIO208 F18

R221 R220
A R286 *10K_4 *10K_4 A
*10K_4 Q20
2

5 HUDSON-M3
Q22
1 3 SMBALERT#_R SMB_EC_CLK 4 3 MBCLK
33 SMBALERT# MBCLK 32,34
*2N7002K
2
SMB_EC_DAT MBDATA
Quanta Computer Inc.
1 6 MBDATA 32,34
PROJECT : ZRP
*2N7002DW Size Document Number Rev
A1A
FCH 1/5(GPIO/USB/AZ)
Date: Friday, July 20, 2012 Sheet 7 of 46
5 4 3 2 1
 5 4 3 2 1

08
C693 150p/50V_4 U34E

14,24,28,32,34 PCIE_RST# R557 33_4 PCIE_RST#_R AE2 PCIE_RST#

HUDSON-M3 PCICLK0 AF3
A_RST#_R AD5 Part 1 of 5 AF1 PCI_CLK1 11
A_RST# PCICLK1/GPO36
D PCICLK2/GPO37 AF5 D
UMI_RXP0 C692 0.1u/10V_4 UMI_RXP0_C AE30 AG2 PCI_CLK3 11
C697 0.1u/10V_4 UMI_RXN0_C UMI_TX0P PCICLK3/GPO38
UMI_RXN0 AE32 UMI_TX0N PCICLK4/14M_OSC/GPO39 AF6 PCI_CLK4 11
UMI_RXP1 C704 0.1u/10V_4 UMI_RXP1_C AD33

CLKS
C700 0.1u/10V_4 UMI_RXN1_C UMI_TX1P
UMI_RXN1 AD31 AB5

PCI
UMI_TX1N PCIRST# TP55
UMI_RXP2 C713 0.1u/10V_4 UMI_RXP2_C AD28
C708 0.1u/10V_4 UMI_RXN2_C UMI_TX2P
UMI_RXN2 AD29 UMI_TX2N
UMI_RXP3 C727 0.1u/10V_4 UMI_RXP3_C AC30 AJ3
C718 0.1u/10V_4 UMI_RXN3_C UMI_TX3P AD0/GPIO0
UMI_RXN3 AC32 UMI_TX3N AD1/GPIO1 AL5
AD2/GPIO2 AG4
UMI_TXP0 AB33 AL6 D10
UMI_RX0P AD3/GPIO3 *RB500V-40_100MA
UMI_TXN0 AB31 UMI_RX0N AD4/GPIO4 AH3
UMI_TXP1 AB28 AJ5 1 2 R288 *short_6
UMI_RX1P AD5/GPIO5 +3VPCU
UMI_TXN1 AB29 UMI_RX1N AD6/GPIO6 AL1
Y33 AN5 D12
UMI_TXP2
UMI_TXN2 Y31
UMI_RX2P
UMI_RX2N
AD7/GPIO7
AD8/GPIO8 AN6 RTC Circuitry(RTC)
UMI_TXP3 Y28 UMI_RX3P AD9/GPIO9 AJ1
UMI_TXN3 Y29 UMI_RX3N AD10/GPIO10 AL8

PCI EXPRESS
+3V_RTC

INTERFACES
AD11/GPIO11 AL3
R548 590/F_4 PCIE_CALRP AF29 AM7 BAT54C-7-F_200MA
R554 2K/F_4 PCIE_CALRN PCIE_CALRP AD12/GPIO12
+1.1V_PCIE_VDDR AF31 PCIE_CALRN AD13/GPIO13 AJ6
AK7 20MIL R646 510/F_4 +3VRTC 1 2 +VCCRTC_2
AD14/GPIO14
V33 GPP_TX0P AD15/GPIO15 AN8
D28
V31
W30
GPP_TX0N AD16/GPIO16 AG9
AM11 20MIL *RB500V-40_100MA
GPP_TX1P AD17/GPIO17 C781
W32 GPP_TX1N AD18/GPIO18 AJ10
AB26 GPP_TX2P AD19/GPIO19 AL12
R225 *0_4 1u/10V_4
AB27
AA24
GPP_TX2N AD20/GPIO20 AK11
AN12
PCIE_RST#_TRAVIS 20MIL
GPP_TX3P AD21/GPIO21
AA23 GPP_TX3N AD22/GPIO22 AG12
AE12 PCI_AD23 R291
AD23/GPIO23
AA27 GPP_RX0P AD24/GPIO24 AC12 PCI_AD24
AA26 AE13 PCI_AD25 1K/F_4
GPP_RX0N AD25/GPIO25
W27 GPP_RX1P AD26/GPIO26 AF13 PCI_AD26
V27 AH13

+BAT
GPP_RX1N AD27/GPIO27 PCI_AD27

INTERFACE
V26
W26
GPP_RX2P AD28/GPIO28 AH14
AD15 HUDSON_MEMHOT# R232 *2.2K_4 +3V
PE_PWRGD 40 20MIL
GPP_RX2N AD29/GPIO29
C W24 GPP_RX3P AD30/GPIO30 AC15 C
W23 AE16

PCI
GPP_RX3N AD31/GPIO31
CBE0# AN3
CBE1# AJ8
CBE2# AN10

1
+1.1V_CKVDD R280 2K/F_4 CLK_CALRN F27 CLK_CALRN CBE3# AD12 Net GPIO I/O Power Well DOS
FRAME# AG10 RTC Battery P/N
DEVSEL# AK9 1. AHL03017100
G30 AL10 PE_PWRGD GPIO28 DGPU_PWRGD I +3.3V "0->1"
G28
PCIE_RCLKP
PCIE_RCLKN
IRDY#
TRDY# AF10 2. AHL03001424
AE10 CN22
PAR
CLK_DP_NSSCP 4 3 INT_CLK_DP_NSSCP R26 AH1 PE_GPIO0 GPIO191 DGPU_RST# O +3.3V "0->1" RTC_SOCKET

2
INT_CLK_DP_NSSCN DISP_CLKP STOP#
CLK_DP_NSSCP/N is 100MHZ non-SSC CLK_DP_NSSCN 2 1 T26 DISP_CLKN PERR# AM9
RP2 0X2 AH8
SERR#
CLK_PCIE_TRAVISP 4 3 INT_CLK_PCIE_TRAVISP H33 DISP2_CLKP REQ0# AG15 PE_GPIO1 GPIO192 DGPU_PWREN O +3.3V "0->1"
CLK_PCIE_TRAVISP/N is 100MHZ non-SSC CLK_PCIE_TRAVISN 2 1 INT_CLK_PCIE_TRAVISN H31 AG13
RP6 *short-4p2r-0404 DISP2_CLKN REQ1#/GPIO40
REQ2#/CLK_REQ8#/GPIO41 AF15
CLK_APU_HCLKP 4 3 INT_CLK_APU_HCLKP T24 AM17
APU_CLKP REQ3#/CLK_REQ5#/GPIO42 TP52
CLK_APU_HCLKP/N is 100MHZ SSC CLK_APU_HCLKN 2 1 INT_CLK_APU_HCLKN T23 AD16
RP1 22X2 APU_CLKN GNT0#
GNT1#/GPO44 AD13
14 CLK_PCIE_VGAP 2 1 INT_CLK_PCIE_VGAP J30 AD21
INT_CLK_PCIE_VGAN SLT_GFX_CLKP GNT2#/SD_LED/GPO45
CLK_PCIE_VGAP/N is 100MHZ SSC 14 CLK_PCIE_VGAN 4 3 K29 SLT_GFX_CLKN GNT3#/CLK_REQ7#/GPIO46 AK17 TP53
RP5 *short-4p2r-0404 AD19 CLKRUN# 34
CLKRUN#
H27 GPP_CLK0P LOCK# AH9
H28 GPP_CLK0N
INTE#/GPIO32 AF18
28 CLK_PCIE_WLANP 4 3 INT_CLK_PCIE_WLANP J27 AE18
INT_CLK_PCIE_WLANN GPP_CLK1P INTF#/GPIO33
GPP_CLK1P/N is 100MHZ SSC capable 28 CLK_PCIE_WLANN 2 1 K26 GPP_CLK1N INTG#/GPIO34 AC16
RP3 22X2 AD18
INTH#/GPIO35
F33 GPP_CLK2P
F31 R655 33_4
GPP_CLK2N CLK_PCI_EC 34
R651 33_4
PCLK_DEBUG 28
32 CLK_PCIE_LANP 4 3 INT_CLK_PCIE_LANP E33 GPP_CLK3P
GPP_CLK3P/N is 100MHZ SSC capable 32 CLK_PCIE_LANN
RP7
2 1 INT_CLK_PCIE_LANN
*short-4p2r-0404
E31 GPP_CLK3N LPCCLK0
LPCCLK1
B25
D25
LPC_CLK0_R
LPC_CLK1_R
R658
R659
22_4
22_4
LPC_CLK0 11
LPC_CLK1 11
For EMI
M23 GPP_CLK4P LAD0 D27 LPC_LAD0 28,34
M24 GPP_CLK4N LAD1 C28 LPC_LAD1 28,34

LPC
GENERATOR
B A26 LPC_LAD2 28,34 PCLK_DEBUG C651 *15p/50V_4 B
LAD2
M27 GPP_CLK5P LAD3 A29 LPC_LAD3 28,34
M26 A31 CLK_PCI_EC C192 *15p/50V_4
CLOCK

GPP_CLK5N LFRAME# LPC_LFRAME# 28,34

B27 LDRQ#0
LDRQ0# TP63
N25 AE27 LDRQ#1
GPP_CLK6P LDRQ1#/CLK_REQ6#/GPIO49 TP41
N26 GPP_CLK6N SERIRQ/GPIO48 AE19 IRQ_SERIRQ 34
R23 32K_X1 C778 22p/50V_4
GPP_CLK7P
R24 GPP_CLK7N

1
DMA_ACTIVE# G25 DMAACTIVE_L 5
N27 GPP_CLK8P PROCHOT# E28 H_PROCHOT# 34
R27 E26
APU

GPP_CLK8N APU_PG APU_PWRGD 5

C785 33P/50V_4 G26 R639 Y3
LDT_STP# APU_RST# 20M_4 32.768KHZ
APU_RST# F26 APU_RST#
Card Reader R663 22_4 CardReader_48M_R J26
27 CardReader_48M 14M_25M_48M_OSC C447 *0.1u/10V_4

2
G2 32K_X1 32K_X2 C772 22p/50V_4
+5V 32K_X1
C783 27p/50V_4 25M_X1 C31 G4 32K_X2 USE GROUND GUARD FOR 32K_X1 AND 32K_X2
25M_X1 32K_X2
2

C455 H7 S5_CORE_EN S5_CORE_EN is necessary to connect enable pin of

S5_CORE_EN TP47 +3VPCU/+5VPCU regulator for S5+ mode implementation
Y4 R649 F1 RTC_CLK 11
0.1u/25V_4 25MHZ_30 25M_X2 RTCCLK INTRUDER_ALERT# R281 *1M/F_4
C33 25M_X2 INTRUDER_ALERT# F3 +3V_RTC
1M/F_4 E6 INTRUDER_ALERT# Left not connected
PLUS
1

VDDBT_RTC_G
(FCH has 50-kohm internal pull-up to
S5

C780 27p/50V_4
20MIL R647 C782
VBAT).

For CardReader_48M HUDSON-M3 560_4 0.1u/10V_4

layout issues

1
G1
+3V_S5
2 *SHORT_PAD

C672 *0.1u/10V_4
A U30 A
5

*TC7SH08FU
2 A_RST#_R
27,28,34 PLTRST# R534 33_4 A_RST# 4
1

C664
3

150p/50V_4

R541 *short_4 Quanta Computer Inc.

PROJECT :ZRP
Size Document Number Rev
A1A
FCH 2/5(ACPI/PCI/CLK)
Date: Friday, July 20, 2012 Sheet 8 of 46
5 4 3 2 1
 5 4 3 2 1

09
U34B

+3V_S5 +3V_S5
29 SATA_TXP0_C AK19 SATA_TX0P
HUDSON-M3 Part 2 of 5
SD_CLK/SCLK_2/GPIO73 AL14
29 SATA_TXN0_C AM19 SATA_TX0N SD_CMD/SLOAD_2/GPIO74 AN14
SATA0 HDD AL20
SD_CD#/GPIO75 AJ12
AH12 R193
29 SATA_RXN0 SATA_RX0N SD_WP/GPIO76
29 SATA_RXP0 AN20 SATA_RX0P SD_DATA0/SDATI_2/GPIO77 AK13 10K_4
D SD_DATA1/SDATO_2/GPIO78 AM13 D
AN22 AH15 U14 R198
29 SATA_TXP1_C SATA_TX1P SD_DATA2/GPIO79
AL22 AJ14 FCH_SPI_CS0# R196 *Short_4 1 8 10K_4

CARD
29 SATA_TXN1_C SATA_TX1N SD_DATA3/GPIO80 CE# VDD
FCH_SPI_CLK R192 *Short_4
SATA1 ODD 6

SD
FCH_SPI_SO R183 *Short_4 SCK
29 SATA_RXN1 AH20 SATA_RX1N GBE_COL AC4 5 SI
AJ20 AD3 FCH_SPI_SI R195 *Short_4 R188 33_4 FCH_SPI1_SI_R 2 7
29 SATA_RXP1 SATA_RX1P GBE_CRS SO HOLD# SPI_HOLD# 7
GBE_MDCK AD9
AJ22 W10 +3V_S5 3 4
28 SATA_TXP2 SATA_TX2P GBE_MDIO 34 SPI_CS WP# VSS
AH22 AB8 C325
28 SATA_TXN2 SATA_TX2N GBE_RXCLK 34 SPI_SCK
*22p/50V_4 W25Q32BVSSIG(SOIC)
SATA2 SSD AM23
GBE_RXD3 AH7
AF7
34
34
SPI_SDO
SPI_SDI C331
28 SATA_RXN2 SATA_RX2N GBE_RXD2
AK23 AE7 R177 0.1u/10V_4
28 SATA_RXP2 SATA_RX2P GBE_RXD1
GBE_RXD0 AD7 10K_4
AH24 SATA_TX3P GBE_RXCTL/RXDV AG8
AJ24 AD1

GBE
SATA_TX3N GBE_RXERR

LAN
AB7 FCH_SPI_WP
GBE_TXCLK
AN24 SATA_RX3N GBE_TXD3 AF9
AL24 SATA_RX3P GBE_TXD2 AG6
GBE_TXD1 AE8
AL26 SATA_TX4P GBE_TXD0 AD8
AN26 SATA_TX4N GBE_TXCTL/TXEN AB9
GBE_PHY_PD AC2
AJ26 SATA_RX4N GBE_PHY_RST# AA7
AH26 W9 GBE_PHY_INTR R227 10K_4 +3V_S5
SATA_RX4P GBE_PHY_INTR

SERIAL
AN29

ATA
SATA_TX5P FCH_SPI_SI
AL28 SATA_TX5N SPI_DI/GPIO164 V6
V5 FCH_SPI_SO
SPI_DO/GPIO163 FCH_SPI_CLK
AK27 SATA_RX5N SPI_CLK/GPIO162 V3
AM27 T6 FCH_SPI_CS0#
SATA_RX5P SPI_CS1#/GPIO165 FCH_SPI_WP
V1 R place close to FCH

ROM
ROM_RST#/SPI_WP#/GPIO161

SPI
AL29 NC6
AN31 NC7
L30 FCH_CRT_RED FCH_CRT_RED 25 FCH_CRT_RED R636 150/F_4
VGA_RED
AL31 NC8
PLACE SATA_CAL RES VERY AL33 L32 FCH_CRT_GRE FCH_CRT_GRE 25 FCH_CRT_GRE R630 150/F_4
NC9 VGA_GREEN
C
CLOSE TO BALL OF AH33 M29 FCH_CRT_BLU FCH_CRT_BLU 25 FCH_CRT_BLU R617 150/F_4 C
NC10 VGA_BLUE
HUDSON-M2/M3 AH31 NC11
AJ33 NC12 VGA_HSYNC/GPO68 M28 FCH_CRT_HSYNC 25
AJ31 NC13 VGA_VSYNC/GPO69 N30 FCH_CRT_VSYNC 25

VGA
DAC
VGA_DDC_SDA/GPO70 M33 FCH_DDCDAT 25
VGA_DDC_SCL/GPO71 N32 FCH_DDCCLK 25
R243 1K/F_4 SATA_CALRP AF28
R244 931/F_4 SATA_CALRN SATA_CALRP VGA_DAC_RSET R275 715/F_4
+1.1V_AVDD_SATA AF27 SATA_CALRN VGA_DAC_RSET K31

AUX_VGA_CH_P V28 APU_DP_AUXP 5

+3V R237 10K_4 SATA_LED# AD22 V29 APU_DP_AUXN 5
SATA_ACT#/GPIO67 AUX_VGA_CH_N
U28 AUXCAL R247 100/F_4 +FCH_VDDAN_11_ML
AUXCAL
AF21 SATA_X1
ML_VGA_L0P T31 APU_DP_TXP0
Integrated Clock Mode: SATA_X1, SATA_X2 leave unconnected. ML_VGA_L0N T33 APU_DP_TXN0
ML_VGA_L1P T29 APU_DP_TXP1
ML_VGA_L1N T28 APU_DP_TXN1
ML_VGA_L2P R32 APU_DP_TXP2
+3V AG21 R30
SATA_X2 ML_VGA_L2N APU_DP_TXN2
ML_VGA_L3P P29 APU_DP_TXP3
P28

MAINLINK
ML_VGA_L3N APU_DP_TXN3
R653 *10K_4 +3V_S5
R528 Remove Zero Power ODD funciton C29
ML_VGA_HPD/GPIO229 FCH_VGA_HPD
*10K_4
BOARD_ID1 VGA VIN0
AH16 N2 R591 10K_4
FANOUT0/GPIO52 VIN0/GPIO175 VIN1 R598 10K_4
29 FCH_ODD_EN AM15 FANOUT1/GPIO53 VIN1/GPIO176 M3
FCH_PROCHOT#_C AJ16 L2 VIN2 R601 10K_4
FANOUT2/GPIO54 HW VIN2/SDATI_1/GPIO177 VIN3 R592 10K_4
VIN3/SDATO_1/GPIO178 N4
BOARD_ID2 AK15 MONITOR P1 VIN4 R587 10K_4
33 BOARD_ID2 FANIN0/GPIO56 VIN4/SLOAD_1/GPIO179
BOARD_ID3 AN16 P3 VIN5 R586 10K_4
BOARD_ID4 FANIN1/GPIO57 VIN5/SCLK_1/GPIO180 VIN6 R600 10K_4
AL16 FANIN2/GPIO58 VIN6/GBE_STAT3/GPIO181 M1
Initial BIOS set internal pull down M5 VIN7 R597 10K_4
BOARD_ID5 VIN7/GBE_LED3/GPIO182
K6 TEMPIN0/GPIO171
BOARD_ID6 K5 AG16
R511 * BOARD_ID1 R529 NCH@10K_4 BOARD_ID7 TEMPIN1/GPIO172 NC1
B +3V K3 TEMPIN2/GPIO173 NC2 AH10 B
R512 1K_4 BOARD_ID2 R530 *10K_4 TEMPIN3 M6 A28
R509 * BOARD_ID3 R526 UMA@10K_4 TEMPIN3/TALERT#/GPIO174 NC3
NC4 G27
R510 * BOARD_ID4 R527 NAC@10K_4 L4
R500 ELP@1K_4 BOARD_ID8 R523 *HYN@10K_4 NC5
R502 * BOARD_ID9 R525 LVDS@10K_4 R277
10K_4
7 BOARD_ID8 HUDSON-M3
7 BOARD_ID9

+3V_S5 R279 * BOARD_ID5 R278 *

R614 *10K_4 BOARD_ID6 R613 10K_4
R626 *10K_4 BOARD_ID7 R625 10K_4

BOARD ID SETTING ID5,ID6,ID7 S5 Power State

ID1 ID2 ID3 ID4 ID5 ID6 ID7 ID8 ID9

Board ID
USB Charge H
No USB Charge L
ELAN H
Synaptics L
VGA SKU H
UMA SKU L
AC H
No AC L
A VRAM 2G H A
VRAM 1G L
H
Reserve L
H
Reserve L
ELPIDA DRAM H
HYNIX DRAM L
Quanta Computer Inc.
eDP Panel H
LVDS Panel L PROJECT :ZRP
Size Document Number Rev
A1A
FCH 3/5(SATA/VGA/GND/SPI)
Date: Monday, July 23, 2012 Sheet 9 of 46
5 4 3 2 1
 5 4 3 2 1

PLACE ALL THE DECOUPLING CAPS ON

THIS SHEET CLOSE TO SB AS POSSIBLE. U34D
10
+3.3V_FCH_R
A3
HUDSON-M3 T25
U34C +1.1V_VCC_FCH_R VSS_1 Part 5 of 5 VSS_65
VDDQ--3.3V I/O power 102mA VDD-- S/B CORE power A33 VSS_2 VSS_66 T27
R214 *short_8 1007mA TRACE WIDTH >=100mil
+3V
AB17 HUDSON-M3
VDDIO_33_PCIGP_1
Part 3 of 5
VDDCR_11_1 T14 R216 *short_8 +1.1V
B7
B13
VSS_3
VSS_4
VSS_67
VSS_68
U6
U14
AB18 VDDIO_33_PCIGP_2 VDDCR_11_2 T17 D9 VSS_5 VSS_69 U17
C349 C385 C377 C378 AE9 T20 D13 U20
22u/6.3V_8 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 VDDIO_33_PCIGP_3 VDDCR_11_3 C388 C395 C416 C397 C355 VSS_6 VSS_70
AD10 VDDIO_33_PCIGP_4 VDDCR_11_4 U16 E5 VSS_7 VSS_71 U21

PCI/GPIO I/O
D AG7 U18 0.1u/10V_4 0.1u/10V_4 1u/10V_4 1u/10V_4 10u/6.3V_8 E12 U30 D
VDDIO_33_PCIGP_5 VDDCR_11_5 VSS_8 VSS_72

CORE
AC13 VDDIO_33_PCIGP_6 VDDCR_11_6 V14 E16 VSS_9 VSS_73 U32
L35 TRACE WIDTH >=15mil AB12 V17 E29 V11

S0
+3V VDDIO_33_PCIGP_7 VDDCR_11_7 VSS_10 VSS_74
HCB1608KF-221T20_2A 12mA 20mA AB13 V20 F7 V16
VDDIO_33_PCIGP_8 VDDCR_11_8 VSS_11 VSS_75
AB14 VDDIO_33_PCIGP_9 VDDCR_11_9 Y17 F9 VSS_12 VSS_76 V18
C367 C364 AB16 +1.1V_CKVDD F11 W4
2.2u/6.3V_4 VDDIO_33_PCIGP_10 VSS_13 VSS_77
*0.1u/10V_4 340mA CKVDD_1.1V-- Internal clock Generator I/O power F13 W6
47mA H24 H26 TRACE WIDTH >=30mil F16
VSS_14 VSS_78
W25
+VDDPL_3.3V VDDPL_33_SYS VDDAN_11_CLK_1 VSS_15 VSS_79
R223 *short_8 +VDDPL_33_DAC V22 J25 L45 +1.1V F17 W28
R224 *short_8 +VDDPL_33_ML VDDPL_33_DAC VDDAN_11_CLK_2 HCB1608KF-181T15_1.5A VSS_16 VSS_80
+FCH_VDDPL_33_MLDAC U22 VDDPL_33_ML VDDAN_11_CLK_3 K24 F19 VSS_17 VSS_81 Y14
L33 TRACE WIDTH >=15mil
+FCH_VDDAN_33_DAC_R 200mA T22 VDDAN_33_DAC VDDAN_11_CLK_4 L22 F23 VSS_18 VSS_82 Y16
HCB1608KF-221T20_2A +FCH_VDDPL_33_SSUSB_S 11mA L18 VDDPL_33_SSUSB_S VDDAN_11_CLK_5 M22 C438 C426 C425 C434 C444
Check +1.1V_CKVDD leakage issues F25 VSS_19 VSS_83 Y18

CLKGEN
+FCH_VDDPL_33_SUSB_S 14mA D7 VDDPL_33_USB_S VDDAN_11_CLK_6 N21 0.1u/10V_4 0.1u/10V_4 1u/10V_4 1u/10V_4 22u/6.3V_8 F29 VSS_20 VSS_84 AA6
C368 C365 +FCH_VDDPL_33_PCIE 11mA AH29 N22 G6 AA12
+FCH_VDDPL_33_SATA VDDPL_33_PCIE VDDAN_11_CLK_7 VSS_21 VSS_85
2.2u/6.3V_4 *0.1u/10V_4 12mA AG28 P22 G16 AA13

I/O
VDDPL_33_SATA VDDAN_11_CLK_8 +1.1V_PCIE_VDDR VSS_22 VSS_86
G32 VSS_23 VSS_87 AA14
+1.5V R254 *0_4 1088mA TRACE WIDTH >=100mil PCIE_VDDR--PCIE I/O power H12 AA16
C417 *2.2u/6.3V_6 LDO_CAP M31 L29 VSS_24 VSS_88
LDO_CAP VDDAN_11_PCIE_1 AB24 +1.1V H15 VSS_25 VSS_89 AA17
Y21 HCB1608KF-181T15_1.5A H29 AA25
+FCH_VDDPL_11_DAC VDDAN_11_PCIE_2 VSS_26 VSS_90
+FCH_VDDAN_11_MLDAC L27 R203 *short_8 7mA V21 VDDPL_11_DAC VDDAN_11_PCIE_3 AE25 J6 VSS_27 VSS_91 AA28

GROUND
HCB1608KF-221T20_2A AD24 C392 C390 C376 C369 C356 J9 AA30
R202 *short_8 +FCH_VDDAN_11_ML 226mA VDDAN_11_PCIE_4 1u/10V_4 *1u/10V_4 22u/6.3V_8 VSS_28 VSS_92

EXPRESS
Y22 VDDAN_11_ML_1 VDDAN_11_PCIE_5 AB23 *0.1u/10V_4 0.1u/10V_4 J10 VSS_29 VSS_93 AA32
V23 VDDAN_11_ML_2 VDDAN_11_PCIE_6 AA22 J13 VSS_30 VSS_94 AB25
C334 V24 AF26 J28 AC6
VDDAN_11_ML_3 VDDAN_11_PCIE_7 VSS_31 VSS_95

PCI
MAIN
C336 C411

LINK
+FCH_VDDAN_11_ML V25 VDDAN_11_ML_4 VDDAN_11_PCIE_8 AG27 J32 VSS_32 VSS_96 AC18
0.1u/10V_4 4.7u/6.3V_6 0.1u/10V_4 +1.1V_AVDD_SATA K7 AC28
TRACE WIDTH >=50mil VSS_33 VSS_97
1337mA AVDD_SATA--SATA phy power K16 VSS_34 VSS_98 AD27
AB10 AA21 L36 +1.1V K27 AE6
VDDIO_33_GBE_S VDDAN_11_SATA_1 HCB1608KF-181T15_1.5A VSS_35 VSS_99
VDDAN_11_SATA_4 Y20 K28 VSS_36 VSS_100 AE15

GBE
AB21 L6 AE21

LAN
VDDAN_11_SATA_2 C389 C374 C384 C379 C359 VSS_37 VSS_101
VDDAN_11_SATA_3 AB22 L12 VSS_38 VSS_102 AE28
+3V_S5 +FCH_VDDPL_33_SSUSB_S +FCH_VDDPL_33_SUSB_S AB11 AC22 *0.1u/10V_4 0.1u/10V_4 1u/10V_4 1u/10V_4 22u/6.3V_8 L13 AF8
VDDCR_11_GBE_S_1 VDDAN_11_SATA_5 VSS_39 VSS_103
AA11 AC21 L15 AF12

SERIAL
L46 L43 VDDCR_11_GBE_S_2 VDDAN_11_SATA_6 VSS_40 VSS_104
VDDAN_11_SATA_7 AA20 L16 VSS_41 VSS_105 AF16

ATA
HCB1608KF-221T20_2A HCB1608KF-221T20_2A AA18 L21 AF33
VDDAN_11_SATA_8 VSS_42 VSS_106
AA9 VDDIO_GBE_S_1 VDDAN_11_SATA_9 AB20 M13 VSS_43 VSS_107 AG30
C445 C442 C450 C451 AA10 AC19 M16 AG32
2.2u/6.3V_6 2.2u/6.3V_6 1u/10V_4 VDDIO_GBE_S_2 VDDAN_11_SATA_10 VSS_44 VSS_108
C 0.1u/10V_4 M21 VSS_45 VSS_109 AH5 C
M25 VSS_46 VSS_110 AH11
N6 AH18
S5 plus mode N11
VSS_47
VSS_48
VSS_111
VSS_112 AH19
+VDDIO_33_S N13 AH21
TRACE WIDTH >=20mil VSS_49 VSS_113
59mA S5_3.3--3.3v standby power N23 VSS_50 VSS_114 AH23
G7 N18 R222 *short_6 +3V_S5 N24 AH25
+3V_AVDD_USB VDDAN_33_USB_S_1 VDDIO_33_S_1 VSS_51 VSS_115
H8 VDDAN_33_USB_S_2 VDDIO_33_S_2 L19 P12 VSS_52 VSS_116 AH27
TRACE WIDTH >=50mil 470mA J8 M18 P18 AJ18
L49 VDDAN_33_USB_S_3 VDDIO_33_S_3 C386 C391 C363 VSS_53 VSS_117
+3V_S5 K8 VDDAN_33_USB_S_4 VDDIO_33_S_4 V12 P20 VSS_54 VSS_118 AJ28

3.3V_S5 I/O
HCB1608KF-221T20_2A K9 V13 1u/10V_4 1u/10V_4 2.2u/6.3V_6 P21 AJ29
VDDAN_33_USB_S_5 VDDIO_33_S_5 VSS_55 VSS_119
M9 VDDAN_33_USB_S_6 VDDIO_33_S_6 Y12 P31 VSS_56 VSS_120 AK21
C448 C449 C441 C431 C432 M10 Y13 P33 AK25
10u/6.3V_8 10u/6.3V_8 1u/10V_4 1u/10V_4 VDDAN_33_USB_S_7 VDDIO_33_S_7 VSS_57 VSS_121
0.1u/10V_4 N9 VDDAN_33_USB_S_8 VDDIO_33_S_8 W11 R4 VSS_58 VSS_122 AL18
N10 +VDDXL_3.3V R11 AM21

USB
EMI VDDAN_33_USB_S_9 TRACE WIDTH >=15mil VSS_59 VSS_123
M12 VDDAN_33_USB_S_10 5mA L48
R25 VSS_60 VSS_124 AM25
N12 VDDAN_33_USB_S_11 VDDXL_33_S G24 +3V_S5 R28 VSS_61 VSS_125 AN1
+1.1V_DUAL L28 +FCH_VDDAN_11_USB_S M11 HCB1608KF-221T20_2A T11 AN18
HCB1608KF-221T20_2A C350 2.2u/6.3V_6 VDDAN_33_USB_S_12 +VDDCR_1.1V VSS_62 VSS_126
C358 0.1u/10V_4 TRACE WIDTH >=20mil U12
113mA TRACE WIDTH >=15mil C452 C453
T16 VSS_63 VSS_127 AN28
VDDAN_11_USB_S_1 VDDCR_11_S_1 N20 T18 VSS_64 VSS_128 AN33
C396 0.1u/10V_4 140mA U13 M20 R627 *short_6 +1.1V_DUAL *0.1u/10V_4 2.2u/6.3V_6
VDDAN_11_USB_S_2 VDDCR_11_S_2
L30 +FCH_VDDCR_11_USB_S
70mA N8 VSSAN_HWM VSSPL_DAC T21
T12 VDDCR_11_USB_S_1 VDDPL_11_SYS_S J24 VSSAN_DAC L28
HCB1608KF-221T20_2A TRACE WIDTH >=15mil T13 C767 C430 K25 K33
VDDCR_11_USB_S_2 1u/10V_4 1u/10V_4 VSSXL VSSANQ_DAC
C348 C420 C344
42mA 12mA VSSIO_DAC N28
VDDAN_33_HWM_S M8 H25 VSSPL_SYS
0.1u/10V_4 0.1u/10V_4 10u/6.3V_8 P16 S5_1.1V--1.1V standby power R6
+1.1V_DUAL +FCH_VDD_11_SSUSB_S VDDAN_11_SSUSB_S_1 EFUSE
M14 VDDAN_11_SSUSB_S_2 26mA
N14 VDDAN_11_SSUSB_S_3 VDDIO_AZ_S AA4

L47 R283 *short_8 +FCH_VDDAN_11_SSUSB_S

282mA P13 VDDAN_11_SSUSB_S_4 Trace width >=20 mil
P14 VDDAN_11_SSUSB_S_5
HCB1608KF-221T20_2A HUDSON-M3
N16
USB +VDDPL_1.1V +1.1V_DUAL
VDDCR_11_SSUSB_S_1 SS
R282 *short_8 +FCH_VDDCR_11_SSUSB_S
424mA N17 VDDCR_11_SSUSB_S_2 L59
P17 VDDCR_11_SSUSB_S_3
M17 HCB1608KF-221T20_2A
VDDCR_11_SSUSB_S_4
B C437 C433 C422 C428 C440 C769 B
10u/6.3V_8 1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 2.2u/6.3V_6
C427 C421 C435
1u/10V_4 0.1u/10V_4 0.1u/10V_4 POWER

+VDDAN_3.3V_HWM +3V_S5

L44
HUDSON-M3
HCB1608KF-221T20_2A

C443 C446
0.1u/10V_4 2.2u/6.3V_6

Check to connect +3.3V A-test

+3V +FCH_VDDAN_33_DAC_R +VDDIO_AZ

L31 R219 *0_8 +3V_S5

*HCB1608KF-221T20_2A
3

+15V C351 R218 0_8 +3V

C419 C387 C361
Q16 10u/6.3V_6 0.1u/10V_4 *0.1u/10V_4 2.2u/6.3V_6
2 PMV45EN_4A
R200
1M_4
1

+FCH_VDDAN_33_DAC L32
HCB1608KF-221T20_2A
Check pull down or not R204 100K_4 +1.1V
3

Q15
3

C330
2 *1u/10V_4 +FCH_VDDAN_33_DAC_R +FCH_VDDPL_33_MLDAC
VGA_PD
A R208 A
2 *0_8 R215 *short_8
FDV301N_200MA Q17
R201 C329 PMV45EN_4A +3V C357
1

100K_4 *1u/10V_4 C354 +3V +VDDPL_3.3V

10u/6.3V_6 0.1u/10V_4
1

L34 L60
*HCB1608KF-221T20_2A HCB1608KF-221T20

+FCH_VDDAN_11_MLDAC C773 C771

2.2u/6.3V_6 0.1u/10V_4
Quanta Computer Inc.
PROJECT :ZRP
Size Document Number Rev
A1A
FCH 4/5(POWER)
Date: Friday, July 20, 2012 Sheet 10 of 46
5 4 3 2 1
 5 4 3 2 1

OVERLAP COMMON PADS WHERE

POSSIBLE FOR DUAL-OP RESISTORS.
11
+3V +3V +3V +3V_S5 +3V_S5 +3V_S5 +3V_S5

STRAPS PINS
D D
R556 R550 R535 R657 R298 R661 R641
10K_4 *10K_4 *10K_4 *10K_4 10K_4 *10K_4 10K_4 FCH PWRGD CKT
8 PCI_CLK1 PCI_CLK1
+3V_S5
PCI_CLK3 +3V_S5
8 PCI_CLK3

8 PCI_CLK4 PCI_CLK4
R292
8 LPC_CLK0 LPC_CLK0 10K_4
C454
8 LPC_CLK1 LPC_CLK1 *0.1u/10V_4

7 EC_PWM2 EC_PWM2

5
U21
8 RTC_CLK RTC_CLK D13 *1SS355_100MA 2
39 VRM_PWRGD
4 R285 *0_4
FCH_PWRGD
1 *SN74LVC1G17DCKR
C456
*2.2u/6.3V_6

3
R555 R549 R520 R654 R299 R662 R648
*10K_4 10K_4 10K_4 10K_4 *10K_4 2.2K_4 *2.2K_4 EC_PWM2-->
SPI ROM: 2.2-KΩ 5% pull-down
LPC ROM: Pull-up to 3.3V_S5.
External pull-up resistor is not required as FCH has 34 PWROK_EC
D11 1SS355_100MA R284 *Short_4
integrated 10-KΩ pull-up to 3.3V_S5.
C C

Remove PCI_CLK2 function

-------- PCI_CLK1 PCI_CLK2 PCI_CLK3 PCI_CLK4 LPC_CLK0 LPC_CLK1 EC_PWM2 RTC_CLK

REQUIRED
STRAPS PULL ALLOW USE non_Fusion EC CLKGEN LPC ROM S5 PLUS MODE
HIGH PCIE Gen2 DEBUG CLOCK MODE ENABLED ENABLED DISABLED
-------- --------
DEFAULT STRAP DEFAULT DEFAULT

PULL FORCE IGNORE FUSION EC CLKGEN SPI ROM S5 PLUS MODE

LOW -------- PCIE Gen1 DEBUG CLOCK MODE DISABLED DISABLED ENABLED
--------
STRAP DEFAULT DEFAULT DEFAULT
DEFAULT

B B

DEBUG STRAPS
FCH HAS 15K INTERNAL PU FOR PCI_AD[27:23]

PCI_AD27
PCI_AD27
PCI_AD26
PCI_AD26
PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23
PCI_AD25
PCI_AD25
PCI_AD24 PULL USE PCI DISABLE ILA USE FC USE DEFAULT DISABLE PCI
PCI_AD24
PCI_AD23 HIGH PLL AUTORUN PLL PCIE STRAPS MEM BOOT
PCI_AD23
DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT

R239 R233 R241 R230 R531

*2.2K_4 *2.2K_4 *2.2K_4 *2.2K_4 *2.2K_4 PULL BYPASS ENABLE ILA BYPASS FC USE EEPROM ENABLE PCI
LOW PCI PLL AUTORUN PLL PCIE STRAPS MEM BOOT

A A

Quanta Computer Inc.

PROJECT :ZRP
Size Document Number Rev
A1A
FCH 5/5(STRAP & PWRGD)
Date: Friday, July 20, 2012 Sheet 11 of 46
5 4 3 2 1
 1 2 3 4 5 6 7 8

DDR3 DIMM-A +1.5VSUS 4,5,6,13,24,36,39,41

+0.75V_DDR_VTT 13,36,43
+3V 5,7,8,9,10,11,13,14,24,25,26,27,28,29,30,33,34,35,36,37,38,39,40,41,42,43 12
CN14A M_A_DQ[63:0] 4
4 M_A_A[15:0]
M_A_A0 98 5 M_A_DQ5
M_A_A1 A0 DQ0 M_A_DQ4 +1.5VSUS
97 A1 DQ1 7
M_A_A2 96 15 M_A_DQ3
M_A_A3 A2 DQ2 M_A_DQ2 CN14B
95 A3 DQ3 17
A M_A_A4 92 4 M_A_DQ1 75 44 A
M_A_A5 A4 DQ4 M_A_DQ0 VDD1 VSS16
91 A5 DQ5 6 76 VDD2 VSS17 48
M_A_A6 90 16 M_A_DQ7 81 49
M_A_A7 A6 DQ6 M_A_DQ6 VDD3 VSS18
86 A7 DQ7 18 82 VDD4 VSS19 54
M_A_A8 89 21 M_A_DQ13 87 55
M_A_A9 A8 DQ8 M_A_DQ8 VDD5 VSS20
85 A9 DQ9 23 88 VDD6 VSS21 60
M_A_A10 107 33 M_A_DQ14 93 61
M_A_A11 A10/AP DQ10 M_A_DQ15 VDD7 VSS22
84 A11 DQ11 35 94 VDD8 VSS23 65
M_A_A12 83 22 M_A_DQ12 99 66
M_A_A13 A12/BC# DQ12 M_A_DQ9 VDD9 VSS24
119 A13 DQ13 24 100 VDD10 VSS25 71
M_A_A14 80 34 M_A_DQ10 105 72
A14 DQ14 VDD11 VSS26

PC2100 DDR3 SDRAM SO-DIMM

M_A_A15 78 36 M_A_DQ11 106 127
A15 DQ15 VDD12 VSS27

PC2100 DDR3 SDRAM SO-DIMM

4 M_A_BS#[2:0] 39 M_A_DQ20 111 128
M_A_BS#0 DQ16 M_A_DQ16 VDD13 VSS28
109 BA0 DQ17 41 112 VDD14 VSS29 133
M_A_BS#1 108 51 M_A_DQ22 117 134
M_A_BS#2 BA1 DQ18 M_A_DQ23 VDD15 VSS30
79 BA2 DQ19 53 118 VDD16 VSS31 138
4 M_A_CS#0 M_A_CS#0 114 40 M_A_DQ21 123 139
M_A_CS#1 S0# DQ20 M_A_DQ17 +1.5VSUS VDD17 VSS32
4 M_A_CS#1 121 S1# DQ21 42 124 VDD18 VSS33 144
4 M_A_CLKP0 M_A_CLKP0 101 50 M_A_DQ18 145
M_A_CLKN0 CK0 DQ22 M_A_DQ19 R352 *short_8 +3V_JM9000 199 VSS34
4 M_A_CLKN0 103 CK0# DQ23 52 +3V VDDSPD VSS35 150
4 M_A_CLKP1 M_A_CLKP1 102 57 M_A_DQ28 151
M_A_CLKN1 CK1 DQ24 M_A_DQ26 R347 VSS36
4 M_A_CLKN1 104 CK1# DQ25 59 77 NC1 VSS37 155
4 M_A_CKE0 M_A_CKE0 73 67 M_A_DQ25 1K_4 122 156
M_A_CKE1 CKE0 DQ26 M_A_DQ31 NC2 VSS38
4 M_A_CKE1 74 CKE1 DQ27 69 125 NCTEST VSS39 161
4 M_A_CAS# M_A_CAS# 115 56 M_A_DQ29 162
M_A_RAS# CAS# DQ28 M_A_DQ24 VSS40
4 M_A_RAS# 110 RAS# DQ29 58 4 M_A_EVENT# 198 EVENT# VSS41 167
4 M_A_WE# M_A_WE# 113 68 M_A_DQ30 4 M_A_RST# 30 168
R359 10K_4 DIMM0_SA0 WE# DQ30 M_A_DQ27 RESET# VSS42
197 SA0 DQ31 70 VSS43 172
R342 10K_4 DIMM0_SA1 201 129 M_A_DQ37 173
PCLK_SMB SA1 DQ32 M_A_DQ32 +DDR_VREF2 VSS44
7,13,28 PCLK_SMB 202 SCL DQ33 131 1 VREF_DQ VSS45 178
B PDAT_SMB 200 141 M_A_DQ39 +DDR_VREF 126 179 B
7,13,28 PDAT_SMB SDA DQ34 VREF_CA VSS46
143 M_A_DQ38 184
M_A_ODT0 DQ35 M_A_DQ36 VSS47
4 M_A_ODT0 116 ODT0 DQ36 130 VSS48 185
4 M_A_ODT1 M_A_ODT1 120 132 M_A_DQ33 2 189
ODT1 DQ37 M_A_DQ34 VSS1 VSS49
4 M_A_DM[7:0] DQ38 140 3 VSS2 VSS50 190
M_A_DM0 11 142 M_A_DQ35 8 195

(204P)
DM0 DQ39 C763 C745 C570 C567 VSS3 VSS51
M_A_DM1 28 147 M_A_DQ45 9 196
M_A_DM2 DM1 DQ40 M_A_DQ40 VSS4 VSS52
46 149 13
(204P)
DM2 DQ41 0.1u/10V_4 1000p/50V_4 0.1u/10V_4 1000p/50V_4 VSS5
M_A_DM3 63 157 M_A_DQ47 14
M_A_DM4 DM3 DQ42 M_A_DQ46 VSS6
136 DM4 DQ43 159 19 VSS7
M_A_DM5 153 146 M_A_DQ41 20 600mA
M_A_DM6 DM5 DQ44 M_A_DQ44 VSS8
170 DM6 DQ45 148 25 VSS9
M_A_DM7 187 158 M_A_DQ43 26 203 +0.75V_DDR_VTT_A R332 *short_8 +0.75V_DDR_VTT
DM7 DQ46 M_A_DQ42 VSS10 VTT1
4 M_A_DQSP[7:0] DQ47 160 31 VSS11 VTT2 204
M_A_DQSP0 12 163 M_A_DQ52 32 C473 C474 C476
M_A_DQSP1 DQS0 DQ48 M_A_DQ49 VSS12
29 DQS1 DQ49 165 37 VSS13 GND 205
M_A_DQSP2 47 175 M_A_DQ54 38 206 4.7u/6.3V_6 4.7u/6.3V_6 0.1u/10V_4
M_A_DQSP3 DQS2 DQ50 M_A_DQ51 VSS14 GND
64 DQS3 DQ51 177 43 VSS15
M_A_DQSP4 137 164 M_A_DQ53
M_A_DQSP5 DQS4 DQ52 M_A_DQ48
154 DQS5 DQ53 166
M_A_DQSP6 171 174 M_A_DQ55 DDR3-DIMMA_H=5.2_STD
M_A_DQSP7 DQS6 DQ54 M_A_DQ50
4 M_A_DQSN[7:0] 188 DQS7 DQ55 176
M_A_DQSN0 10 181 M_A_DQ56
M_A_DQSN1 DQS#0 DQ56 M_A_DQ57
27 DQS#1 DQ57 183
M_A_DQSN2 45 191 M_A_DQ59
M_A_DQSN3 DQS#2 DQ58 M_A_DQ62
62 DQS#3 DQ59 193
M_A_DQSN4 135 180 M_A_DQ60
M_A_DQSN5 DQS#4 DQ60 M_A_DQ61
SM_MEM BUS ADDRESS 152 DQS#5 DQ61 182
M_A_DQSN6 169 192 M_A_DQ63 +1.5VSUS
M_A_DQSN7 DQS#6 DQ62 M_A_DQ58
C
SO-DIMM0 1010 000 186 DQS#7 DQ63 194
C

SO-DIMM1 1010 001

R448
DDR3-DIMMA_H=5.2_STD 1K/F_4

Place these Caps near So-Dimm A +SMDDR_VREF R450 *0_6 +DDR_VREF

3mA
R442
+1.5VSUS +1.5VSUS 1K/F_4

C599 C617 C280 C296 C226 C174 C609 C200 C250 C305 C303 C228

0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 4.7u/6.3V_6 4.7u/6.3V_6 2.2u/6.3V_6 2.2u/6.3V_6 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4
+1.5VSUS

R638
1K/F_4

R637 *0_6 +DDR_VREF2

+1.5VSUS
3mA
R633
+1.5VSUS
1K/F_4
D D
C312 C288 C311 C247 C205
C320 C262 C179
0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 C318
0.1u/10V_4 180P/50V_4 0.1u/10V_4 0.1u/10V_4

Quanta Computer Inc.

PROJECT : ZRP
Size Document Number Rev
DDR3 SO-DIMM A A1A
Date: Friday, July 20, 2012 Sheet 12 of 46
1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

13
<DDR> 4 M_B_DQSP[7:0] BYTE0_0-7 BYTE4_32-39 BYTE6_48-55
4 M_B_DQSN[7:0]
4 M_B_DQ[63:0]
BYTE2_16-23
BYTE1_8-15 BYTE5_40-47 BYTE7_56-63
U18 U15 BYTE3_24-31 U9 U3

+SMDDR_VREF_DIMM M8 E3 M_B_DQ3 +SMDDR_VREF_DIMM M8 E3 M_B_DQ22 +SMDDR_VREF_DIMM M8 E3 M_B_DQ36 +SMDDR_VREF_DIMM M8 E3 M_B_DQ49

SMDDR_VREF_DQ1 VREFCA DQL0 M_B_DQ7 SMDDR_VREF_DQ1 VREFCA DQL0 M_B_DQ18 SMDDR_VREF_DQ1 VREFCA DQL0 M_B_DQ38 SMDDR_VREF_DQ1 H1 VREFCA DQL0 M_B_DQ50
H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7 VREFDQ DQL1 F7
4 M_B_A[15:0] F2 M_B_DQ4 F2 M_B_DQ16 F2 M_B_DQ37 F2 M_B_DQ52
M_B_A0 DQL2 M_B_DQ6 M_B_A0 DQL2 M_B_DQ19 M_B_A0 DQL2 M_B_DQ35 M_B_A0 DQL2 M_B_DQ54
N3 A0 DQL3 F8 N3 A0 DQL3 F8 N3 A0 DQL3 F8 N3 A0 DQL3 F8
M_B_A1 P7 H3 M_B_DQ1 M_B_A1 P7 H3 M_B_DQ21 M_B_A1 P7 H3 M_B_DQ32 M_B_A1 P7 H3 M_B_DQ53
M_B_A2 A1 DQL4 M_B_DQ2 M_B_A2 A1 DQL4 M_B_DQ20 M_B_A2 A1 DQL4 M_B_DQ39 M_B_A2 A1 DQL4 M_B_DQ55
P3 A2 DQL5 H8 P3 A2 DQL5 H8 P3 A2 DQL5 H8 P3 A2 DQL5 H8
M_B_A3 N2 G2 M_B_DQ5 M_B_A3 N2 G2 M_B_DQ17 M_B_A3 N2 G2 M_B_DQ33 M_B_A3 N2 G2 M_B_DQ48
M_B_A4 A3 DQL6 M_B_DQ0 M_B_A4 A3 DQL6 M_B_DQ23 M_B_A4 A3 DQL6 M_B_DQ34 M_B_A4 A3 DQL6 M_B_DQ51
P8 A4 DQL7 H7 P8 A4 DQL7 H7 P8 A4 DQL7 H7 P8 A4 DQL7 H7
M_B_A5 P2 M_B_A5 P2 M_B_A5 P2 M_B_A5 P2
M_B_A6 A5 M_B_A6 A5 M_B_A6 A5 M_B_A6 A5
R8 A6 R8 A6 R8 A6 R8 A6
SO-DIMMB SPD Address is 0XA4 M_B_A7 R2 A7 DQU0 D7 M_B_DQ11 M_B_A7 R2 A7 DQU0 D7 M_B_DQ31 M_B_A7 R2 A7 DQU0 D7 M_B_DQ47 M_B_A7 R2 A7 DQU0 D7 M_B_DQ62
A SO-DIMMB TS Address is 0X34 M_B_A8 T8 C3 M_B_DQ8 M_B_A8 T8 C3 M_B_DQ25 M_B_A8 T8 C3 M_B_DQ45 M_B_A8 T8 C3 M_B_DQ60 A
M_B_A9 A8 DQU1 M_B_DQ10 M_B_A9 A8 DQU1 M_B_DQ27 M_B_A9 A8 DQU1 M_B_DQ46 M_B_A9 A8 DQU1 M_B_DQ59
R3 A9 DQU2 C8 R3 A9 DQU2 C8 R3 A9 DQU2 C8 R3 A9 DQU2 C8
M_B_A10 L7 C2 M_B_DQ12 M_B_A10 L7 C2 M_B_DQ29 M_B_A10 L7 C2 M_B_DQ41 M_B_A10 L7 C2 M_B_DQ57
M_B_A11 A10/AP DQU3 M_B_DQ14 M_B_A11 A10/AP DQU3 M_B_DQ30 M_B_A11 A10/AP DQU3 M_B_DQ42 M_B_A11 A10/AP DQU3 M_B_DQ63
R7 A11 DQU4 A7 R7 A11 DQU4 A7 R7 A11 DQU4 A7 R7 A11 DQU4 A7
M_B_A12 N7 A2 M_B_DQ9 M_B_A12 N7 A2 M_B_DQ28 M_B_A12 N7 A2 M_B_DQ40 M_B_A12 N7 A2 M_B_DQ56
M_B_A13 A12/BC DQU5 M_B_DQ15 M_B_A13 A12/BC DQU5 M_B_DQ26 M_B_A13 A12/BC DQU5 M_B_DQ43 M_B_A13 A12/BC DQU5 M_B_DQ58
T3 A13 DQU6 B8 T3 A13 DQU6 B8 T3 A13 DQU6 B8 T3 A13 DQU6 B8
M_B_A14 T7 A3 M_B_DQ13 M_B_A14 T7 A3 M_B_DQ24 M_B_A14 T7 A3 M_B_DQ44 M_B_A14 T7 A3 M_B_DQ61
M_B_A15 A14 DQU7 M_B_A15 A14 DQU7 M_B_A15 A14 DQU7 M_B_A15 A14 DQU7
M7 A15 M7 A15 M7 A15 M7 A15
+1.5VSUS +1.5VSUS +1.5VSUS +1.5VSUS
4 M_B_BS#[2:0]
M_B_BS#0 M2 B2 M_B_BS#0 M2 B2 M_B_BS#0 M2 B2 M_B_BS#0 M2 B2
M_B_BS#1 BA0 VDD#B2 M_B_BS#1 BA0 VDD#B2 M_B_BS#1 BA0 VDD#B2 M_B_BS#1 BA0 VDD#B2
N8 BA1 VDD#D9 D9 N8 BA1 VDD#D9 D9 N8 BA1 VDD#D9 D9 N8 BA1 VDD#D9 D9
M_B_BS#2 M3 G7 M_B_BS#2 M3 G7 M_B_BS#2 M3 G7 M_B_BS#2 M3 G7
BA2 VDD#G7 BA2 VDD#G7 BA2 VDD#G7 BA2 VDD#G7
VDD#K2 K2 VDD#K2 K2 VDD#K2 K2 VDD#K2 K2
VDD#K8 K8 VDD#K8 K8 VDD#K8 K8 VDD#K8 K8
VDD#N1 N1 VDD#N1 N1 VDD#N1 N1 VDD#N1 N1
4 M_B_CLKP0 J7 N9 M_B_CLKP0 J7 N9 M_B_CLKP0 J7 N9 M_B_CLKP0 J7 N9
CK VDD#N9 M_B_CLKN0 CK VDD#N9 M_B_CLKN0 CK VDD#N9 M_B_CLKN0 CK VDD#N9
4 M_B_CLKN0 K7 CK VDD#R1 R1 K7 CK VDD#R1 R1 K7 CK VDD#R1 R1 K7 CK VDD#R1 R1
4 M_B_CKE0 K9 R9 M_B_CKE0 K9 R9 M_B_CKE0 K9 R9 M_B_CKE0 K9 R9
CKE VDD#R9 CKE VDD#R9 CKE VDD#R9 CKE VDD#R9

4 M_B_ODT0 K1 A1 M_B_ODT0 K1 A1 M_B_ODT0 K1 A1 M_B_ODT0 K1 A1

ODT VDDQ#A1 M_B_CS#0 ODT VDDQ#A1 M_B_CS#0 ODT VDDQ#A1 M_B_CS#0 ODT VDDQ#A1
4 M_B_CS#0 L2 CS VDDQ#A8 A8 L2 CS VDDQ#A8 A8 L2 CS VDDQ#A8 A8 L2 CS VDDQ#A8 A8
4 M_B_RAS# J3 C1 M_B_RAS# J3 C1 M_B_RAS# J3 C1 M_B_RAS# J3 C1
RAS VDDQ#C1 M_B_CAS# RAS VDDQ#C1 M_B_CAS# RAS VDDQ#C1 M_B_CAS# RAS VDDQ#C1
4 M_B_CAS# K3 CAS VDDQ#C9 C9 K3 CAS VDDQ#C9 C9 K3 CAS VDDQ#C9 C9 K3 CAS VDDQ#C9 C9
4 M_B_WE# L3 D2 M_B_WE# L3 D2 M_B_WE# L3 D2 M_B_WE# L3 D2
WE VDDQ#D2 WE VDDQ#D2 WE VDDQ#D2 WE VDDQ#D2
VDDQ#E9 E9 VDDQ#E9 E9 VDDQ#E9 E9 VDDQ#E9 E9
VDDQ#F1 F1 VDDQ#F1 F1 VDDQ#F1 F1 VDDQ#F1 F1
M_B_DQSP0 F3 H2 M_B_DQSP2 F3 H2 M_B_DQSP4 F3 H2 M_B_DQSP6 F3 H2
M_B_DQSP1 DQSL VDDQ#H2 M_B_DQSP3 DQSL VDDQ#H2 M_B_DQSP5 DQSL VDDQ#H2 M_B_DQSP7 DQSL VDDQ#H2
C7 DQSU VDDQ#H9 H9 C7 DQSU VDDQ#H9 H9 C7 DQSU VDDQ#H9 H9 C7 DQSU VDDQ#H9 H9

4 M_B_DM0 E7 DML VSS#A9 A9 4 M_B_DM2 E7 DML VSS#A9 A9 4 M_B_DM4 E7 DML VSS#A9 A9 4 M_B_DM6 E7 DML VSS#A9 A9
4 M_B_DM1 D3 DMU VSS#B3 B3 4 M_B_DM3 D3 DMU VSS#B3 B3 4 M_B_DM5 D3 DMU VSS#B3 B3 4 M_B_DM7 D3 DMU VSS#B3 B3
VSS#E1 E1 VSS#E1 E1 VSS#E1 E1 VSS#E1 E1
VSS#G8 G8 VSS#G8 G8 VSS#G8 G8 VSS#G8 G8
M_B_DQSN0 G3 J2 M_B_DQSN2 G3 J2 M_B_DQSN4 G3 J2 M_B_DQSN6 G3 J2
M_B_DQSN1 DQSL VSS#J2 M_B_DQSN3 DQSL VSS#J2 M_B_DQSN5 DQSL VSS#J2 M_B_DQSN7 DQSL VSS#J2
B7 DQSU VSS#J8 J8 B7 DQSU VSS#J8 J8 B7 DQSU VSS#J8 J8 B7 DQSU VSS#J8 J8
B
VSS#M1 M1 VSS#M1 M1 VSS#M1 M1 VSS#M1 M1 B
VSS#M9 M9 VSS#M9 M9 VSS#M9 M9 VSS#M9 M9
VSS#P1 P1 VSS#P1 P1 VSS#P1 P1 VSS#P1 P1
4 M_B_RST# T2 P9 M_B_RST# T2 P9 M_B_RST# T2 P9 M_B_RST# T2 P9
RESET VSS#P9 RESET VSS#P9 RESET VSS#P9 RESET VSS#P9
VSS#T1 T1 VSS#T1 T1 VSS#T1 T1 VSS#T1 T1
M_B_ZQ1 L8 T9 M_B_ZQ2 L8 T9 M_B_ZQ3 L8 T9 M_B_ZQ4 L8 T9
ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9
Should be 243
Ohms +-1% Should be 243 Should be 243 Should be 243
VSSQ#B1 B1 Ohms +-1% VSSQ#B1 B1 Ohms +-1% VSSQ#B1 B1 Ohms +-1% VSSQ#B1 B1
2

2
VSSQ#B9 B9 VSSQ#B9 B9 VSSQ#B9 B9 VSSQ#B9 B9
R546 D1 R169 D1 R395 D1 R350 D1
VSSQ#D1 VSSQ#D1 VSSQ#D1 VSSQ#D1
243/F_4 VSSQ#D8 D8 243/F_4 VSSQ#D8 D8 243/F_4 VSSQ#D8 D8 243/F_4 VSSQ#D8 D8
VSSQ#E2 E2 VSSQ#E2 E2 VSSQ#E2 E2 VSSQ#E2 E2
J1 E8 J1 E8 J1 E8 J1 E8
1

1
NC#J1 VSSQ#E8 NC#J1 VSSQ#E8 NC#J1 VSSQ#E8 NC#J1 VSSQ#E8
L1 NC#L1 VSSQ#F9 F9 L1 NC#L1 VSSQ#F9 F9 L1 NC#L1 VSSQ#F9 F9 L1 NC#L1 VSSQ#F9 F9
J9 NC#J9 VSSQ#G1 G1 J9 NC#J9 VSSQ#G1 G1 J9 NC#J9 VSSQ#G1 G1 J9 NC#J9 VSSQ#G1 G1
L9 NC#L9 VSSQ#G9 G9 L9 NC#L9 VSSQ#G9 G9 L9 NC#L9 VSSQ#G9 G9 L9 NC#L9 VSSQ#G9 G9

100-BALL 100-BALL 100-BALL 100-BALL

SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
SP@RAM_DDR3 SP@RAM_DDR3 SP@RAM_DDR3 SP@RAM_DDR3

SP : ELPIDA DRAM P/N : AKD5JGST400

HYNIX DRAM P/N : AKD5JGQTW01

+3V
U5
PCLK_SMB 6 1
7,12,28 PCLK_SMB SCL A0
PDAT_SMB 5 2
7,12,28 PDAT_SMB SDA A1
A2 3

7 8 C44
WP VCC
GND 4 *0.1u/10V_4

*M24C02-WMN6TP
C C
address:A2
WP =1 : WRITE DISABLE

Place these Caps near Memory Down

+0.75V_DDR_VTT
+1.5VSUS +1.5VSUS +1.5VSUS

M_B_WE# R566 36/F_4

M_B_CAS# R615 36/F_4
M_B_RAS# R602 36/F_4 R148
C554 C633 C703 C559 C637 C689 C733 C715 C696 C691 C732 M_B_BS#0 R262 36/F_4 1K/F_4
0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 M_B_BS#1 R217 36/F_4 +SMDDR_VREF
M_B_BS#2 R578 36/F_4
M_B_CKE0 R594 36/F_4 +SMDDR_VREF_DIMM R140 *0_6
M_B_ODT0 R261 36/F_4
+0.75V_DDR_VTT M_B_CS#0 R595 36/F_4
M_B_A0 R579 36/F_4 R404
M_B_A1 R563 36/F_4 1K/F_4 C632 C686 C481 C230
+1.5VSUS +0.75V_DDR_VTT M_B_A2 R577 36/F_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4
M_B_A3 R263 36/F_4
M_B_A4 R560 36/F_4
M_B_A5 R264 36/F_4
M_B_A6 R573 36/F_4
C711 C667 C661 C497 C526 C634 C683 C380 C381 C382 C684 M_B_A7 R240 36/F_4
0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 M_B_A8 R561 36/F_4
M_B_A9 R576 36/F_4
M_B_A10 R593 36/F_4 +1.5VSUS
M_B_A11 R574 36/F_4
D M_B_A12 R564 36/F_4 D
M_B_A13 R575 36/F_4 R446
M_B_A14 R562 36/F_4 1K/F_4
M_B_A15 R565 36/F_4 +SMDDR_VREF
+1.5VSUS
SMDDR_VREF_DQ1 R449 *0_6

R375 C556 C666 C716 C571

C514 C494 C527 C682 C547 C488 M_B_CLKP0 R590 36/F_4 1K/F_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4
0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 0.22u/10V_4
C734 0.1u/10V_4 +1.5VSUS Quanta Computer Inc.
M_B_CLKN0 R589 36/F_4
PROJECT : ZRP
Size Document Number Rev
A1A
DDR3 MEMORY DOWNx16 B
Date: Monday, July 23, 2012 Sheet 13 of 46
1 2 3 4 5 6 7 8
 PART 1 0F 9
U26A

14
3 PEG_TXP0 AA38 PCIE_RX0P PCIE_TX0P Y33 C_PEG_RXP0 C182 *
PEG_RXP0 3
Y37 Y32 C_PEG_RXN0 C198 *
3 PEG_TXN0 PCIE_RX0N PCIE_TX0N
PEG_RXN0 3
Thames(Pro,XT) and Mars Power-on sequence
3
3
PEG_TXP1
PEG_TXN1
Y35
W36
PCIE_RX1P
PCIE_RX1N
PCIE_TX1P
PCIE_TX1N
W33 C_PEG_RXP1
W32 C_PEG_RXN1
C203
C211
*
*
PEG_RXP1 3
PEG_RXN1 3
PX5.0(no BACO)
3 PEG_TXP2 W38 PCIE_RX2P PCIE_TX2P U33 C_PEG_RXP2 C216 *
PEG_RXP2 3
3 PEG_TXN2 V37 PCIE_RX2N PCIE_TX2N U32 C_PEG_RXN2 C233 *
PEG_RXN2 3 DGPU_PWREN

3 PEG_TXP3 V35 PCIE_RX3P PCIE_TX3P U30 C_PEG_RXP3 C235 *

PEG_RXP3 3 VDDC/VDDCI/1.8V_IO
3 PEG_TXN3 U36 PCIE_RX3N PCIE_TX3N U29 C_PEG_RXN3 C249 *
PEG_RXN3 3 MVDDQ/+PCIE_VDDC
C_PEG_RXP4 C261 *
VDDR3
3 PEG_TXP4 U38 PCIE_RX4P PCIE_TX4P T33 PEG_RXP4 3
T37 PCIE_RX4N PCIE_TX4N T32 C_PEG_RXN4 C252 * 20ms max
3 PEG_TXN4 PEG_RXN4 3

T35 PCIE_RX5P PCIE_TX5P T30 C_PEG_RXP5 C272 * PE_PWRGD

3 PEG_TXP5 PEG_RXP5 3
R36 PCIE_RX5N PCIE_TX5N T29 C_PEG_RXN5 C283 *
3 PEG_TXN5 PEG_RXN5 3

3 PEG_TXP6 R38 PCIE_RX6P PCIE_TX6P P33 C_PEG_RXP6 C284 *

PEG_RXP6 3
3 PEG_TXN6 P37 PCIE_RX6N PCIE_TX6N P32 C_PEG_RXN6 C297 *
PEG_RXN6 3 PWRGOOD
100ms
3 PEG_TXP7 P35 PCIE_RX7P PCIE_TX7P P30 C_PEG_RXP7 C299 *
PEG_RXP7 3
3 PEG_TXN7 N36 PCIE_RX7N PCIE_TX7N P29 C_PEG_RXN7 C304 *
PEG_RXN7 3
PCIE_RST#
N38 PCIE_RX8P PCIE_TX8P N33
M37 PCIE_RX8N PCIE_TX8N N32

PCIE Clock
PCI EXPRESS INTERFACE

M35 PCIE_RX9P PCIE_TX9P N30

L36 PCIE_RX9N PCIE_TX9N N29

L38 PCIE_RX10P PCIE_TX10P L33

K37 PCIE_RX10N PCIE_TX10N L32
+3V
K35 PCIE_RX11P PCIE_TX11P L30
J36 PCIE_RX11N PCIE_TX11N L29
C595 *

J38 PCIE_RX12P PCIE_TX12P K33

5
H37 PCIE_RX12N PCIE_TX12N K32 U27
DGPU_RST_L 2
4 PERST#_BUF
H35 PCIE_RX13P PCIE_TX13P J33 8,24,28,32,34 PCIE_RST# 1
G36 PCIE_RX13N PCIE_TX13N J32
* R463

3
G38 PCIE_RX14P PCIE_TX14P K30 *EV@100K_4
F37 PCIE_RX14N PCIE_TX14N K29

F35 PCIE_RX15P PCIE_TX15P H33

E37 PCIE_RX15N PCIE_TX15N H32

CLOCK
8 CLK_PCIE_VGAP AB35 PCIE_REFCLKP

8 CLK_PCIE_VGAN AA36 PCIE_REFCLKN

R150 *
CALIBRATION

PCIE_CALR_TX Y30 PCIE_CALR_TX R149 *

R110 * TEST_PG AH16 TEST_PG PCIE_CALR_RX Y29 PCIE_CALR_RX R153 * +PCIE_VDDC_GFX

SP : Thames Pro,XT R=2K(CS22002FB19)

PERST#_BUF AA30 PERSTB
Mars R=1K(CS21002JB34) Quanta Computer Inc.
SP : Thames PRO()
EV_SP@GPU_M2
PROJECT : ZRP
Size Document Number Rev
Thames XT(AJ083300T26) A1A
Mars() Thames_M2/ PEG*16
Date: Friday, July 20, 2012 Sheet 14 of 46
 15
Thames Pro,XT Thermal
+3V_GFX
U26B

PART 2 0F 9 Check not stuff MOS of SMBUS

MUTI GFX
for Thames A-test
AD29 GENLK_CLK TXCAP_DPA3P AU24 R50
GENLK_CLK
AC29 GENLK_VSYNC TXCAM_DPA3N AV23 *
GENLK_VSYNC

2
TX0P_DPA2P AT25
AJ21 SWAPLOCKA TX0M_DPA2N AR24 34 GPUT_CLK 6 1 GPU_SMBCLK
DPA
AK21 SWAPLOCKB
TX1P_DPA1P AU26 Q8A *EV_T@2N7002KDW_115MA
TX1M_DPA1N AV25

AR8 DVPCNTL_MVP_0 TX2P_DPA0P AT27

AU8 DVPCNTL_MVP_1 TX2M_DPA0N AR26
AP8 DVPCNTL_0 +3V_GFX
AW8 DVPCNTL_1 TXCBP_DPB3P AR30 SP : Thames R=4.7K(CS24702JB38)
AR3 DVPCNTL_2 TXCBM_DPB3N AT29
AR1 DVPCLK
Mars R=45.3K(CS34532FB18)
RAM_STRAP0 AU1 DVPDATA_0 TX3P_DPB2P AV31
AU3 DVPDATA_1 TX3M_DPB2N AU30 R57
RAM_STRAP1 DPB
AW3 DVPDATA_2 *
RAM_STRAP2

5
RAM_STRAP3 AP6 DVPDATA_3 TX4P_DPB1P AR32
AW5 DVPDATA_4 TX4M_DPB1N AT31
AU5 DVPDATA_5
34 GPUT_DATA 3 4 GPU_SMBDAT
AR6 DVPDATA_6 TX5P_DPB0P AT33
1.8V GPIO AW6 DVPDATA_7 TX5M_DPB0N AU32 Q8B *EV_T@2N7002KDW_115MA
AU6 DVPDATA_8
AT7 DVPDATA_9 TXCCP_DPC3P AU14
AV7 DVPDATA_10 TXCCM_DPC3N AV13
AN7 DVPDATA_11
AV9 DVPDATA_12 TX0P_DPC2P AT15
AT9 DVPDATA_13 TX0M_DPC2N AR14
AR10 DVPDATA_14
DPC
AW10 AU16
AU10
DVPDATA_15
DVPDATA_16
TX1P_DPC1P
TX1M_DPC1N AV15 Mars Thermal
AP10 DVPDATA_17
AV11 DVPDATA_18 TX2P_DPC0P AT17
AT11 DVPDATA_19 TX2M_DPC0N AR16 +3V_GFX +3V_GFX
AR12 DVPDATA_20
AW12 DVPDATA_21 TXCDP_DPD3P AU20
AU12 DVPDATA_22 TXCDM_DPD3N AT19
AP12 DVPDATA_23 R34
TX3P_DPD2P AT21 *
TX3M_DPD2N AR20 C58
DPD
*
GPU_SMBCLK AJ23 SMBCLK TX4P_DPD1P AU22 U4
SMBus
GPU_SMBDAT AH23 SMBDATA TX4M_DPD1N AV21
GPUT_CLK 8 1 GPU_D+
SCLK VCC
TX5P_DPD0P AT23
TX5M_DPD0N AR22 GPUT_DATA 7 2
R77 *EV@4.7K_4 GPU_SCL SDA DXP C43
+3V_GFX AK26 SCL
I2C
R68 *EV@4.7K_4 GPU_SDA AJ26 SDA ALT#_GPIO17 6 3
ALERT# DXN *
R88 *EV_M@0_4 R AD39 4 5
40 GPU_DPRSLPVR OVERT# GND
GENERAL PURPOSE I/O AVSSN#1 AD37 GPU_D-
+3V_GFX AH20 GPIO_0
GPU_GPIO0
AH18 GPIO_1 G AE36 *
GPU_GPIO1
R41 *EV_M@10K_4 PCIE_REQ_GPU# AN16 GPIO_2 AVSSN#2 AD35
GPU_GPIO2
R381 *EV_M@100_4 B AF37
AH17 GPIO_5_AC_BATT AVSSN#3 AE38
42 PWRCNTRL5 AJ17 GPIO_6
DAC1
R92 *EV@10K_4 AK17 GPIO_7_BLON HSYNC AC36 GPU_HSYNC_COM 17
GPU_GPIO8
GPU_GPIO9
AJ13
AH15
GPIO_8_ROMSO
GPIO_9_ROMSI
VSYNC AC38 GPU_VSYNC_COM 17 Check need or not
AJ16 GPIO_10_ROMSCK +1.8V_GFX
GPU_GPIO10
AK16 GPIO_11 RSET AB34 R429 * +1.8V_AVDD
GPU_GPIO11
GPU_GPIO12 AL16 GPIO_12 DAC1 Analog Power : 1.8V@18mA
AM16 GPIO_13 AVDD AD34 L20
GPU_GPIO13
TP33 AM14 GPIO_14_HPD2 AVSSQ AE34 *
5,35,40,43 SYS_SHDN#
40 PWRCNTRL0 AM13 GPIO_15_PWRCNTL_0
3

R33 * AK14 GPIO_16 VDD1DI AC33 C160 C161 C166

40 PWRCNTRL2
ALT#_GPIO17 AG30 GPIO_17_THERMAL_INT VSS1DI AC34 * * *
Q38 AN14 GPIO_18_HPD3
2 GPIO_19_CTF AM17 GPIO_19_CTF

40 PWRCNTRL1 AL13 GPIO_20_PWRCNTL_1 NC#1 V13

GPU_GPIO21 AJ14 GPIO_21 NC#2 U13
*EV@ME2N7002E_200MA R380 AK13 GPIO_22_ROMCSB NC#3 AC31
17 GPU_GPIO22
*EV@10K_4 PCIE_REQ_GPU# AN13 CLKREQB NC#4 AD30 +1.8V_VDD1DI
7 PCIE_REQ_GPU#
1

NC#5 AC32 DAC1 Digital Power : 1.8V@117mA

NC#6 AD32 L17
R100 * AG32 GPIO_29 NC#7 AF32 *
40 PWRCNTRL3
R430 * AG33 GPIO_30 NC#8 AA29
40 PWRCNTRL4
NC#9 AG21 R113 * +VGPU_CORE C135 C132 C137
AJ19 GENERICA * * *
AK19 GENERICB

GPU_GENERICC AJ20 GENERICC

AK20 GENERICD
AJ24 GENERICE_HPD4 NC_TSVSSQ AF33 R115 *
AH26 GENERICF_HPD5
AH24 GENERICG_HPD6

PS_0 AM34 R70 * VDDC_CT VDDC_CT VDDC_CT

+1.8V_GFX
TP35 AC30 CEC_1 R71 * PS_0

Place close to Chip TP34 AK24 HPD1 PS_1 AD31 PS_1 R_pu R74 R_pu R102 R_pu R86
MLPS
R47 * *EV_M@0_4 *EV_M@0_4
*
PS_0 PS_1 PS_2
GPU_VREFG AH13 VREFG PS_2 AG31 PS_2
R_pd R_pd R_pd
Ca C89 R72 Ca C110 R101 Ca C95 R85
R374 C522 BACO * * *EV_M@0.1u/10V_4 * * *
* R367 *EV@4.7K_4 AL21 PX_EN PS_3 AD33 PS_3 17
*

DEBUG DDC/AUX
DDC1CLK AM26
MLPS
DDC1DATA AN26
R112 * TESTEN AD28 TESTEN R_pu R_pd Bits [3:1] Ra P/N MLPS Bit Bits [5:1] Ca Bits [5:4] P/N
AUX1P AM27
+3V_GFX R117 *EV_M@5.11K/F_4 AUX1N AL27
NC 4.75K 000 2K CS22002FB19 PS_0 01001 680nF 00 CH4681K9B00
R80 *EV@10K_4 AM23 JTAG_TRSTB DDC2CLK AM19
R378 *EV@10K_4 AN23 JTAG_TDI DDC2DATA AL19
R66 *EV@10K_4 AK23 JTAG_TCK 8.45K 2K 001 3.24K CS23242FB09 PS_1 11000 82nF 01 CH3823K1B00
R69 *EV@10K_4 AL24 JTAG_TMS AUX2P AN20
TP32 AM24 JTAG_TDO AUX2N AM20
4.53K 2K 010 3.4K CS23402FB08 PS_2 00000 10nF 10 CH31003KB11
DDCCLK_AUX3P AL30
DDCDATA_AUX3N AM30
THERMAL
6.98K 4.99K 011 4.53K CS24532FB08 PS_3 00XXX NC 11
DDCCLK_AUX4P AL29
GPU_D+ AF29 DPLUS DDCDATA_AUX4N AM29
GPU_D- AG29 DMINUS 4.53K 4.99K 100 4.75K CS24752FB12
+3V_GFX DDCCLK_AUX5P AN21
DDCDATA_AUX5N AM21
PU:Disable MLPS R84 * GPU_GPIO28 AK32 GPIO_28_FDO 3.24K 5.62K 101 4.99K CS24992FB26
R83 * DDCCLK_AUX6P AK30
PD:Enable MLPS AL31 TS_A DDCDATA_AUX6N AK29
3.4K 1M 110 5.62K CS25622FB18
on-die thermal sensor power : 1.8V@8mA DDCVGACLK AJ30
+1.8V_GFX L15 +1.8V_TSVDD AJ32 TSVDD DDCVGADATA AJ31
* AJ33 4.75K NC 111 6.98K CS26982FB01
C107
C106 C105
TSVSS
Quanta Computer Inc.
* * * 8.45K CS28452FB12
EV_SP@GPU_M2
SP : Thames PRO() PROJECT : ZRP
Size Document Number Rev
Thames XT(AJ083300T26) A1A
Mars()
1M CS51002FB11 02_Thames_M2/ GPIO_DP_CRT_I2C
Date: Friday, July 20, 2012 Sheet 15 of 46
 16
237mA
+1.8V_GFX L9 * DPLL_PVDD
U26G
C72 C81
C63
U26I PART 7 0F 9
* * *

VARY_BL AK27 R87 *EV@10K_4

PART 9 0F 9
LVDS CONTROL DIGON AJ27 R79 *EV@10K_4

AM32 DPLL_PVDD XTALIN AV33 GPU_XTALIN C520 * TXCLK_UP_DPF3P AK35

280mA TXCLK_UN_DPF3N AL36

2
+PCIE_VDDC_GFX L8 * DPLL_VDDC AN31 DPLL_VDDC
R391 Y1 TXOUT_U0P_DPF2P AJ38
C80 C71 * * TXOUT_U0N_DPF2N AK37
C62 AN32 DPLL_PVSS

1
* * * TXOUT_U1P_DPF1P AH35
XTALOUT AU34 GPU_XTALOUT C519 * TXOUT_U1N_DPF1N AJ36

TXOUT_U2P_DPF0P AG38
TXOUT_U2N_DPF0N AH37
H7 MPLL_PVDD
H8 MPLL_PVDD TXOUT_U3P AF35
150mA TXOUT_U3N AG36

LVTMDP
+1.8V_GFX L37 * MPLL_PVDD XO_IN AW34 TP48

C308 C353 AM10 SPLL_PVDD

PLLS/XTAL
C362
* * * TXCLK_LP_DPE3P AP34
TXCLK_LN_DPE3N AR34
AN9 SPLL_VDDC XO_IN2 AW35 TP49
TXOUT_L0P_DPE2P AW37
TXOUT_L0N_DPE2N AU35

AN10 SPLL_PVSS TXOUT_L1P_DPE1P AR37

TXOUT_L1N_DPE1N AU39
75mA
+1.8V_GFX L12 * SPLL_PVDD TXOUT_L2P_DPE0P AP35
CLKTESTA AK10 CLKTESTA TXOUT_L2N_DPE0N AR35
C91 C85 AF30 NC_XTAL_PVDD CLKTESTB AL10 CLKTESTB
C78 AF31 NC_XTAL_PVSS TXOUT_L3P AN36
* * * TXOUT_L3N AP37

C76 C77
*EV@0.1u/10V_4 *EV@0.1u/10V_4

EV_SP@GPU_M2
EV_SP@GPU_M2
100mA R58 R59 SP : Thames PRO()
+PCIE_VDDC_GFX L7 * SPLL_VDDC SP : Thames PRO() *EV@51.1/F_4 *EV@51.1/F_4
Thames XT(AJ083300T26)
C65 C73
Thames XT(AJ083300T26) Mars()
C59 Mars()
* * *

DPLL_PVDD R95 *EV_M@0_4

R114 *EV_M@0_4

Quanta Computer Inc.

PROJECT : ZRP
Size Document Number Rev
A1A
Thames_M2/ XTAL_LVDS
Date: Friday, July 20, 2012 Sheet 16 of 46
 Thames Pro,XT USE Mars USE
17
RAM_STRAP3 RAM_STRAP2 RAM_STRAP1 RAM_STRAP0 CONFIGURATION STRAPS -- SEE EACH DATABOOK FOR STRAP DETAILS
Vendor Vendor P/N STN B/S P/N Size MLPS ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED,
DVPDATA_3 DVPDATA_2 DVPDATA_1 DVPDATA_0 THEY MUST NOT CONFLICT DURING RESET

Default Setting
H5TQ1G63DFR-11C STRAPS MLPS GPIO PIN DESCRIPTION OF DEFAULT SETTINGS
AKD5LZWTW05 *8 1GB
(64M*16) 0 0 0 0 000
MLPS_DISABLE NA GPIO_28_FDO Enable MLPS, NA for Thames/Whistler/Seymour X
0: Enable MLPS, disable GPIO PINSTRAP
Hynix 1: Disable MLPS, enable GPIO PINSTRAP
AKD5MGWTW17 * 4 1GB
H5TQ2G63DFR-11C 0 0 0 1
TX_PWRS_ENB PS_1[4] GPIO0 Transmitter Power Savings Enable
(128M*16) 0: 50% Tx output swing X
1: Full Tx output swing
AKD5MGWTW17 * 8 2GB 0 0 1 0 001 TX_DEEMPH_EN PS_1[5] GPIO1 PCIE Transmitter De-emphasis Enable X
0: Tx de-emphasis disabled
1: Tx de-emphasis enabled
K4W1G1646G-BC11
AKD5EGGT500 *8 1GB
(64M*16) 0 1 0 0 010 BIF_GEN3_EN_A PS_1[1] GPIO2 PCIE Gen3 Enable (NOTE: RESERVED for Thames/Whistler/Seymour)
0: GEN3 not supported at power-on
1

1: GEN3 supported at power-on

BIF_VGA DIS PS_2[4] GPIO9 VGA Control 0

Samsung AKD5MGWT500 * 4 1GB
K4W2G1646C-HC11 0 1 0 1 0: VGA controller capacity enabled
1: VGA controller capacity disabled (for multi-GPU)
(128M*16)
ROMIDCFG[2:0] PS_0[3..1] GPIO[13:11] Serial ROM type or Memory Aperture Size Select
AKD5MGWT500 * 8 2GB 0 1 1 0 011 If GPIO22 = 0, defines memory aperture size XXX
If GPIO22 = 1, defines ROM type
100 - 512Kbit M25P05A (ST)
23EY2387MC11 101 - 1Mbit M25P10A
101 - 2Mbit M25P20
(ST)
(ST)
AKD5EZWT700 *8 1GB
(64M*16) 1 0 0 0 100 101 - 4Mbit M25P40
101 - 8Mbit M25P80
(ST)
(ST)
100 - 512Kbit Pm25LV512 (Chingis)
101 - 1Mbit Pm25LV010 (Chingis)

AKD5DZWT700 *4 1GB
AMD 23EY4187MC11 1 0 0 1 BIOS_ROM_EN PS_2[3] GPIO22 Enable external BIOS ROM device
0: Disabled
X

1: Enabled
(128M*16)
AUD[1] NA HSYNC 00 - No audio function XX
AKD5DZWT700 * 8 2GB 01 - Audio for DP only
1 0 1 0 101 AUD[0] NA VSYNC
10 - Audio for DP and HDMI if dongle is detected
11 - Audio for both DP and HDMI
HDMI must only be enabled on systems that are legally entitled. It is the
responsibility of the system designer to ensure that the system is entitled to
support this feature.

SP : Thames DDR3 Memory TYPE Set SP : Mars DDR3 Memory TYPE Set CEC_DIS PS_0[4] GENLK_VSYNC Enable CEC function. Reserved for Thames/Whistler/Seymour
0: Disabled
X

1: Enabled
R389 * +1.8V_GFX VDDC_CT
RAM_STRAP0
R388 *

R_pu R99 NOTE: ALLOW FOR PULLUP PADS FOR THE RESERVED STRAPS BUT DO NOT INSTALL RESISTOR
* IF THESE GPIOS ARE USEED, THEY MUST KEEP LOW AND NOT CONFLICT DURING RESET
R384 * +1.8V_GFX RESERVED PS_1[3] GENLK_CLK Reserved 0
RAM_STRAP1 15 PS_3
RESERVED PS_1[2] GPIO8 Reserved 0
R385 * R_pd RESERVED NA GPIO21 Reserved 0
Ca C133 R116 RESERVED NA GENERICC Reserved (for Thames/Whistler/Seymour only) 0
* *

R387 * +1.8V_GFX AUD_PORT_CONN_PINSTRAP[2] PS_3[5] NA STRAPS TO INDICATE THE NUMBER OF AUDIO CAPABLE DISPLAY OUTPUTS XXX
RAM_STRAP2
AUD_PORT_CONN_PINSTRAP[1] PS_3[4] NA 111 = 0 usable endpoints
R386 * NA 110 = 1 usable endpoints
AUD_PORT_CONN_PINSTRAP[0] PS_0[5] 101 = 2 usable endpoints
100 = 3 usable endpoints
MLPS Bit Bits [5:1] 011 = 4 usable endpoints
010 = 5 usable endpoints
R383 * +1.8V_GFX 001 = 6 usable endpoints
RAM_STRAP3
PS_3 00XXX 000 = all endpoints are usable
R382 *

System Memory Aperture size +3V_GFX

MLPS GPIO9 GPIO11 GPIO12 GPIO13 GPU_GPIO0

R73 *

BIOSROM ROMIDCFG0 ROMIDCFG1 ROMIDCFG2 R67 *

GPU_GPIO1
R_pu R_pd Bits [3:1] Ra P/N Ca Bits [5:4] P/N
R53 *EV_T@10K_4
0 128M 0 0 0 GPU_GPIO2
R51 *EV_T@10K_4
NC 4.75K 000 2K CS22002FB19 680nF 00 CH4681K9B00 GPU_GPIO8
0 256M 1 0 0 GPU_GPIO10
R65 *EV_T@10K_4
8.45K 2K 001 3.24K CS23242FB09 82nF 01 CH3823K1B00
R46 *EV_T@10K_4
0 64M 0 1 0 GPU_GPIO21
R60 *EV_T@10K_4
4.53K 2K 010 3.4K CS23402FB08 10nF 10 CH31003KB11 15 GPU_GPIO22
0 32M 1 1 0 GENLK_VSYNC
R119 *EV_T@10K_4
6.98K 4.99K 011 4.53K CS24532FB08 NC 11
R118 *EV_T@10K_4
GENLK_CLK
4.53K 4.99K 100 4.75K CS24752FB12 R78 *EV_T@10K_4
GPU_GENERICC
+3V_GFX R436 *EV@10K_4
15 GPU_HSYNC_COM
3.24K 5.62K 101 4.99K CS24992FB26
R437 *EV@10K_4
15 GPU_VSYNC_COM
3.4K 1M 110 5.62K CS25622FB18
R63 *EV_T@10K_4
GPU_GPIO9
4.75K NC 111 6.98K CS26982FB01 R54 *
GPU_GPIO11
R62 *EV_T@10K_4
GPU_GPIO12
8.45K CS28452FB12
R52 *EV_T@10K_4
GPU_GPIO13
1M CS51002FB11

Quanta Computer Inc.

PROJECT : ZRP
Size Document Number Rev
A1A
Thames_M2/ STRAPS_Thermal
Date: Friday, July 20, 2012 Sheet 17 of 46
 +1.5V_GFX
(2.2A)
AC7
AD11
MEM I/O
VDDR1
VDDR1
U26E

PART 5 0F 9

NC_PCIE_VDDR AA31
NC_PCIE_VDDR AA32
PCIE_VDDR
(440mA)
L19 *
+1.8V_GFX
18
AF7 VDDR1 NC_PCIE_VDDR AA33
C725 C412 C269 C301 C42 C342 AG10 VDDR1 NC_PCIE_VDDR AA34 C177 C149 C197 C155 C165
* * * * * * AJ7 VDDR1 NC_PCIE_VDDR W30 * * * * *
AK8 VDDR1 NC_PCIE_VDDR Y31
AL9 VDDR1 NC_BIF_VDDC V28
G11 VDDR1 NC_BIF_VDDC W29
G14 VDDR1 PCIE_PVDD AB37

PCIE
G17 VDDR1
G20 VDDR1 PCIE_VDDC G30
C111 C307 C136 C148 C286 C315 C281 G23 VDDR1 PCIE_VDDC G31 +PCIE_VDDC_GFX
* * * * * * * G26 VDDR1 PCIE_VDDC H29 (1.88A)
G29 VDDR1 PCIE_VDDC H30
H10 VDDR1 PCIE_VDDC J29
J7 VDDR1 PCIE_VDDC J30
J9 VDDR1 PCIE_VDDC L28 C270 C282 C258 C298 C243 C328 C326
K11 VDDR1 PCIE_VDDC M28 * * * * * * *
K13 VDDR1 PCIE_VDDC N28
C313 C162 C306 C118 K8 VDDR1 PCIE_VDDC R28
* * * * L12 VDDR1 PCIE_VDDC T28
L16 VDDR1 PCIE_VDDC U28
L21 VDDR1
L23 VDDR1 R141 * +VGPU_CORE
L26 VDDR1 BIF_VDDC N27
BACO
L7 VDDR1 BIF_VDDC T27 R187 * +PCIE_VDDC_GFX
+ M11 VDDR1
C287 C236 C245 C316 C486 N11 VDDR1 C323 C259 C295
* * * * * P7 VDDR1 VDDC AA15 * * *EV_M@4.7u/6.3V_6
CORE
R11 VDDR1 VDDC AA17
U11 VDDR1 VDDC AA20
U7 VDDR1 VDDC AA22
Y11 VDDR1 VDDC AA24
Y7 VDDR1 VDDC AA27
VDDC AB16 +VGPU_CORE
VDDC AB18 (30A)
VDDC AB21
Level translation between core and I/O, VDDC AB23
excluding memory receivers. VDDC_CT LEVEL VDDC AB26
(17mA) TRANSLATION VDDC AB28 C271 C152 C119 C154 C231 C229 C232
+1.8V_GFX L57 VDDC_CT AF26 VDD_CT VDDC AC17 * * * * * * *
* AF27 VDD_CT VDDC AC20
AG26 VDD_CT VDDC AC22
C577 C578 C140 C151 AG27 VDD_CT VDDC AC24
* * * * VDDC AC27
VDDC AD18
I/O power for 3.3-V pins, such as GPIOs. I/O VDDC AD21
(60mA) AF23 VDDR3 VDDC AD23
+3V_GFX L14 VDDR3 AF24 VDDR3 VDDC AD26
* AG23 VDDR3 VDDC AF17 C251 C175 C209 C158 C255 C244 C260 C213 C163 C176
AG24 VDDR3 VDDC AF20 * * * * * * * * * *
C109 C120 C138 C147 VDDC AF22
* *EV_M@4.7u/6.3V_6 * * DVP VDDC AG16
AD12 VDDR4 VDDC AG18
AF11 VDDR4
AF12 VDDR4 VDDC AH22
Power for all DVP pins; DVPDATA_[23:0]—DVO or GPIO. AF13 VDDR4 VDDC AH27
(300mA) VDDC AH28
+1.8V_GFX L54 VDDR4 VDDC M26
* AF15 VDDR4 VDDC N24 C173 C199 C210 C194 C180 C246 C139 C150 C285 C257
AG11 VDDR4 VDDC R18 * * * * * * * * * *
C501 C164 C141 AG13 VDDR4 VDDC R21
* * * AG15 VDDR4 VDDC R23
VDDC R26
VDDC T17
VDDC T20
VDDC T22
VDDC T24 SP: Thames XT stuff L21,L26 for +VGPU_CORE
VDDC U16 Thames Pro and Mars stuff L3,L4 for +VDDCI_GFX
VDDC U18
C518 C146 C129 VDDC U21
* * * VDDC U23
VDDC U26
VDDC V17
VDDC V20
VDDC V22
VDDC V24 L21 * +VGPU_CORE
VDDC V27 L26 *
VDDC Y16
VDDC Y18
VDDC Y21
VDDC Y23
VDDC Y26 L3 * +VDDCI_GFX
VDDC Y28 L4 *
(8.8A)
VDDCI AA13 VDDCI
VDDCI AB13
VDDCI AC12
VDDCI AC15 C171 C215 C239 C254
VDDCI AD13 * * * *
VDDCI AD16
VDDCI M15
VDDCI M16
GPUVDDC/GPUVSS route a differtial pair. VOLTAGE
VDDCI M18
VDDCI M23
SENESE
CORE I/O

VDDCI N13
ISOLATED

R94 * AF28 FB_VDDC VDDCI N15

40 GPUVDDC_SENSE
VDDCI N17 C289 C290 C187 C278 C279 C170
VDDCI N20 * * * * * *
TP31 AG28 FB_VDDCI VDDCI N22
VDDCI R12
VDDCI R13
R93 * AH29 R16
40 GPUVSS_SENSE FB_GND VDDCI
VDDCI T12 Quanta Computer Inc.
VDDCI T15 SP : Thames PRO()
VDDCI V15 Thames XT(AJ083300T26) PROJECT : ZRP
VDDCI Y13
Mars() Size Document Number Rev
A1A
EV_SP@GPU_M2
Thames_M2/ MainPower
Date: Friday, July 20, 2012 Sheet 18 of 46
 19
U26H

PART 8 0F 9
(330mA)
DPAB_VDD10 L10 +PCIE_VDDC_GFX
DP_VDDR DP_VDDC
*
DP_VDDC AP31 C64 C70 C79
DP_VDDC AP32
DP_VDDC AN33 * * *
DP_VDDC AP33
AN24 DP_VDDR
AP24 DP_VDDR DP_VDDC AP13 (330mA)
(330mA) AP25 DP_VDDR DP_VDDC AT13 DPCD_VDD10 L6
+1.8V_GFX L11 * DPAB_VDD18 AP26 DP_VDDR DP_VDDC AP14 *
AU28 DP_VDDR DP_VDDC AP15 C61 C82 C86
AV29 DP_VDDR
C68 C75 C83 DP_VDDC AL33 * * *
* * * DP_VDDC AM33
AP20 DP_VDDR DP_VDDC AK33
AP21 DP_VDDR DP_VDDC AK34 (220mA)
AP22 DP_VDDR DPEF_VDD10 L13
(330mA) AP23 DP_VDDR *
L55 * DPCD_VDD18 AU18 DP_VDDR C92 C103 C96
AV19 DP_VDDR
DP GND
* * *
C496 C504 C517 DP_VSSR AN27
* * * AH34 DP_VDDR DP_VSSR AP27
AJ34 DP_VDDR DP_VSSR AP28
AF34 DP_VDDR DP_VSSR AW24
AG34 DP_VDDR DP_VSSR AW26
(330mA) AM37 DP_VDDR DP_VSSR AN29
L56 * DPEF_VDD18 AL38 DP_VDDR DP_VSSR AP29
DP_VSSR AP30
DP_VSSR AW30
C542 C112 C128 DP_VSSR AW32
* * * DP_VSSR AN17
DP_VSSR AP16
DP_VSSR AP17
DP_VSSR AW14
DP_VSSR AW16
DP_VSSR AN19
DP_VSSR AP18
DP_VSSR AP19
CALIBRATION
DP_VSSR AW20
DP_VSSR AW22
DP_VSSR AN34
DP_VSSR AP39
R377 * AW28 DPAB_CALR DP_VSSR AR39
DP_VSSR AU37
DP_VSSR AF39
DP_VSSR AH39
R379 * AW18 DPCD_CALR DP_VSSR AK39
DP_VSSR AL34
DP_VSSR AV27
DP_VSSR AR28
R406 * AM39 DPEF_CALR DP_VSSR AV17
DP_VSSR AR18
DP_VSSR AN38
DP_VSSR AM35

EV_SP@GPU_M2

SP : Thames PRO()
Thames XT(AJ083300T26)
Mars()
Quanta Computer Inc.
PROJECT : ZRP
Size Document Number Rev
A1A
Thames_M2/ DP_Powers
Date: Friday, July 20, 2012 Sheet 19 of 46
<VGA>
PART 6 0F 9
U26F
20
AB39 PCIE_VSS GND A3
E39 PCIE_VSS GND A37
F34 PCIE_VSS GND AA16
F39 PCIE_VSS GND AA18
G33 PCIE_VSS GND AA2
G34 PCIE_VSS GND AA21
H31 PCIE_VSS GND AA23
H34 PCIE_VSS GND AA26
H39 PCIE_VSS GND AA28
J31 PCIE_VSS GND AA6
J34 PCIE_VSS GND AB12
K31 PCIE_VSS GND AB15
K34 PCIE_VSS GND AB17
K39 PCIE_VSS GND AB20
L31 PCIE_VSS GND AB22
L34 PCIE_VSS GND AB24
M34 PCIE_VSS GND AB27
M39 PCIE_VSS GND AC11
N31 PCIE_VSS GND AC13
N34 PCIE_VSS GND AC16
P31 PCIE_VSS GND AC18
P34 PCIE_VSS GND AC2
P39 PCIE_VSS GND AC21
R34 PCIE_VSS GND AC23
T31 PCIE_VSS GND AC26
T34 PCIE_VSS GND AC28
T39 PCIE_VSS GND AC6
U31 PCIE_VSS GND AD15
U34 PCIE_VSS GND AD17
V34 PCIE_VSS GND AD20
V39 PCIE_VSS GND AD22
W31 PCIE_VSS GND AD24
W34 PCIE_VSS GND AD27
Y34 PCIE_VSS GND AD9
Y39 PCIE_VSS GND AE2
GND AE6
GND AF10
GND AF16
GND AF18
GND GND AF21
GND AG17
F15 GND GND AG2
F17 GND GND AG20
F19 GND GND AG22 Mars AG22 NC
F21 GND GND AG6
F23 GND GND AG9
F25 GND GND AH21
F27 GND GND AJ10
F29 GND GND AJ11
F31 GND GND AJ2
F33 GND GND AJ28
F7 GND GND AJ6
F9 GND GND AK11
G2 GND GND AK31
G6 GND GND AK7
H9 GND GND AL11
J2 GND GND AL14
J27 GND GND AL17
J6 GND GND AL2
J8 GND GND AL20
K14 GND
K7 GND GND AL23
L11 GND GND AL26
L17 GND GND AL32
L2 GND GND AL6
L22 GND GND AL8
L24 GND GND AM11
L6 GND GND AM31
M17 GND GND AM9
M22 GND GND AN11
M24 GND GND AN2
N16 GND GND AN30
N18 GND GND AN6
N2 GND GND AN8
N21 GND GND AP11
N23 GND GND AP7
N26 GND GND AP9
N6 GND GND AR5
R15 GND GND B11
R17 GND GND B13
R2 GND GND B15
R20 GND GND B17
R22 GND GND B19
R24 GND GND B21
R27 GND GND B23
R6 GND GND B25
T11 GND GND B27
T13 GND GND B29
T16 GND GND B31
T18 GND GND B33
T21 GND GND B7
T23 GND GND B9
T26 GND GND C1
U15 GND GND C39
U17 GND GND E35
U2 GND GND E5
U20 GND GND F11
U22 GND GND F13
U24 GND
U27 GND
U6 GND
V11 GND
V16 GND
V18 GND
V21 GND
V23 GND
V26 GND
W2 GND
W6 GND
Y15 GND
Y17 GND
Y20 GND
Y22 GND VSS_MECH A39
Y24 GND VSS_MECH AW1
Y27 GND VSS_MECH AW39

EV_SP@GPU_M2

SP : Thames PRO()
Thames XT(AJ083300T26)
Mars()

Quanta Computer Inc.

PROJECT : ZRP
Size Document Number Rev
A1A
Thames_M2/ GND
Date: Friday, July 20, 2012 Sheet 20 of 46
<VGA>
23 VMB_DQ[63..0]
VMB_DQ[63..0]

VMB_DM[7..0]
21
23 VMB_DM[7..0] U26D
U26C
VMB_RDQS[7..0]
23 VMB_RDQS[7..0] PART 4 0F 9
PART 3 0F 9 VMB_WDQS[7..0]
VMA_DQ[63..0] 23 VMB_WDQS[7..0] GDDR5/DDR3
GDDR5/DDR3 VMB_DQ0 C5 DQB0_0 MAB0_0/MAB_0 P8 VMB_MA0
22 VMA_DQ[63..0] VMB_MA[15..0]
VMA_DQ0 C37 DQA0_0 MAA0_0/MAA_0 G24 VMA_MA0 VMB_DQ1 C3 DQB0_1 MAB0_1/MAB_1 T9 VMB_MA1
VMA_DM[7..0] 23 VMB_MA[15..0]
VMA_DQ1 C35 DQA0_1 MAA0_1/MAA_1 J23 VMA_MA1 VMB_DQ2 E3 DQB0_2 MAB0_2/MAB_2 P9 VMB_MA2
22 VMA_DM[7..0]
VMA_DQ2 A35 DQA0_2 MAA0_2/MAA_2 H24 VMA_MA2 VMB_DQ3 E1 DQB0_3 MAB0_3/MAB_3 N7 VMB_MA3
VMA_RDQS[7..0] VMA_DQ3 E34 DQA0_3 MAA0_3/MAA_3 J24 VMA_MA3 VMB_DQ4 F1 DQB0_4 MAB0_4/MAB_4 N8 VMB_MA4
22 VMA_RDQS[7..0]
VMA_DQ4 G32 DQA0_4 MAA0_4/MAA_4 H26 VMA_MA4 VMB_BA0 VMB_DQ5 F3 DQB0_5 MAB0_5/MAB_5 N9 VMB_MA5
VMA_WDQS[7..0] 23 VMB_BA0
VMA_DQ5 D33 DQA0_5 MAA0_5/MAA_5 J26 VMA_MA5 VMB_BA1 VMB_DQ6 F5 DQB0_6 MAB0_6/MAB_6 U9 VMB_MA6
22 VMA_WDQS[7..0] 23 VMB_BA1
VMA_DQ6 F32 DQA0_6 MAA0_6/MAA_6 H21 VMA_MA6 VMB_BA2 VMB_DQ7 G4 DQB0_7 MAB0_7/MAB_7 U8 VMB_MA7
23 VMB_BA2
VMA_DQ7 E32 DQA0_7 MAA0_7/MAA_7 G21 VMA_MA7 VMB_DQ8 H5 DQB0_8 MAB1_0/MAB_8 Y9 VMB_MA8

MEMORY INTERFACE A
VMA_DQ8 D31 DQA0_8 MAA1_0/MAA_8 H19 VMA_MA8 VMB_DQ9 H6 DQB0_9 MAB1_1/MAB_9 W9 VMB_MA9
VMA_MA[15..0] VMA_DQ9 F30 DQA0_9 MAA1_1/MAA_9 H20 VMA_MA9 VMB_DQ10 J4 DQB0_10 MAB1_2/MAB_10 AC8 VMB_MA10
22 VMA_MA[15..0]
VMA_DQ10 C30 DQA0_10 MAA1_2/MAA_10 L13 VMA_MA10 VMB_DQ11 K6 DQB0_11 MAB1_3/MAB_11 AC9 VMB_MA11
VMA_DQ11 A30 DQA0_11 MAA1_3/MAA_11 G16 VMA_MA11 VMB_DQ12 K5 DQB0_12 MAB1_4/MAB_12 AA7 VMB_MA12
VMA_BA0 VMA_DQ12 F28 DQA0_12 MAA1_4/MAA_12 J16 VMA_MA12 VMB_DQ13 L4 DQB0_13 MAB1_5/BA2 AA8 VMB_BA2
22 VMA_BA0
VMA_BA1 VMA_DQ13 C28 DQA0_13 MAA1_5/MAA_BA2 H16 VMA_BA2 VMB_DQ14 M6 DQB0_14 MAB1_6/BA0 Y8 VMB_BA0
22 VMA_BA1
VMA_BA2 VMA_DQ14 A28 DQA0_14 MAA1_6/MAA_BA0 J17 VMA_BA0 VMB_DQ15 M1 DQB0_15 MAB1_7/BA1 AA9 VMB_BA1
22 VMA_BA2
VMA_DQ15 E28 DQA0_15 MAA1_7/MAA_BA1 H17 VMA_BA1 VMB_DQ16 M3 DQB0_16

MEMORY INTERFACE B
VMA_DQ16 D27 DQA0_16 VMB_DQ17 M5 DQB0_17 WCKB0_0/DQMB_0 H3 VMB_DM0
VMA_DQ17 F26 DQA0_17 WCKA0_0/DQMA_0 A32 VMA_DM0 VMB_DQ18 N4 DQB0_18 WCKB0B_0/DQMB_1 H1 VMB_DM1
VMA_DQ18 C26 DQA0_18 WCKA0B_0/DQMA_1 C32 VMA_DM1 VMB_DQ19 P6 DQB0_19 WCKB0_1/DQMB_2 T3 VMB_DM2
VMA_DQ19 A26 DQA0_19 WCKA0_1/DQMA_2 D23 VMA_DM2 VMB_DQ20 P5 DQB0_20 WCKB0B_1/DQMB_3 T5 VMB_DM3
VMA_DQ20 F24 DQA0_20 WCKA0B_1/DQMA_3 E22 VMA_DM3 VMB_DQ21 R4 DQB0_21 WCKB1_0/DQMB_4 AE4 VMB_DM4
VMA_DQ21 C24 DQA0_21 WCKA1_0/DQMA_4 C14 VMA_DM4 VMB_DQ22 T6 DQB0_22 WCKB1B_0/DQMB_5 AF5 VMB_DM5
VMA_DQ22 A24 DQA0_22 WCKA1B_0/DQMA_5 A14 VMA_DM5 VMB_DQ23 T1 DQB0_23 WCKB1_1/DQMB_6 AK6 VMB_DM6
VMA_DQ23 E24 DQA0_23 WCKA1_1/DQMA_6 E10 VMA_DM6 VMB_DQ24 U4 DQB0_24 WCKB1B_1/DQMB_7 AK5 VMB_DM7
VMA_DQ24 C22 DQA0_24 WCKA1B_1/DQMA_7 D9 VMA_DM7 VMB_DQ25 V6 DQB0_25
VMA_DQ25 A22 DQA0_25 VMB_DQ26 V1 DQB0_26 EDCB0_0/QSB_0 F6 VMB_RDQS0
VMA_DQ26 F22 DQA0_26 EDCA0_0/QSA_0 C34 VMA_RDQS0 VMB_DQ27 V3 DQB0_27 EDCB0_1/QSB_1 K3 VMB_RDQS1
VMA_DQ27 D21 DQA0_27 EDCA0_1/QSA_1 D29 VMA_RDQS1 VMB_DQ28 Y6 DQB0_28 EDCB0_2/QSB_2 P3 VMB_RDQS2
VMA_DQ28 A20 DQA0_28 EDCA0_2/QSA_2 D25 VMA_RDQS2 VMB_DQ29 Y1 DQB0_29 EDCB0_3/QSB_3 V5 VMB_RDQS3
VMA_DQ29 F20 DQA0_29 EDCA0_3/QSA_3 E20 VMA_RDQS3 VMB_DQ30 Y3 DQB0_30 EDCB1_0/QSB_4 AB5 VMB_RDQS4
VMA_DQ30 D19 DQA0_30 EDCA1_0/QSA_4 E16 VMA_RDQS4 VMB_DQ31 Y5 DQB0_31 EDCB1_1/QSB_5 AH1 VMB_RDQS5
VMA_DQ31 E18 DQA0_31 EDCA1_1/QSA_5 E12 VMA_RDQS5 VMB_DQ32 AA4 DQB1_0 EDCB1_2/QSB_6 AJ9 VMB_RDQS6
VMA_DQ32 C18 DQA1_0 EDCA1_2/QSA_6 J10 VMA_RDQS6 VMB_DQ33 AB6 DQB1_1 EDCB1_3/QSB_7 AM5 VMB_RDQS7
VMA_DQ33 A18 DQA1_1 EDCA1_3/QSA_7 D7 VMA_RDQS7 VMB_DQ34 AB1 DQB1_2
VMA_DQ34 F18 DQA1_2 VMB_DQ35 AB3 DQB1_3 DDBIB0_0/QSB_0B G7 VMB_WDQS0
VMA_DQ35 D17 DQA1_3 DDBIA0_0/QSA_0B A34 VMA_WDQS0 VMB_DQ36 AD6 DQB1_4 DDBIB0_1/QSB_1B K1 VMB_WDQS1
VMA_DQ36 A16 DQA1_4 DDBIA0_1/QSA_1B E30 VMA_WDQS1 VMB_DQ37 AD1 DQB1_5 DDBIB0_2/QSB_2B P1 VMB_WDQS2
VMA_DQ37 F16 DQA1_5 DDBIA0_2/QSA_2B E26 VMA_WDQS2 VMB_DQ38 AD3 DQB1_6 DDBIB0_3/QSB_3B W4 VMB_WDQS3
VMA_DQ38 D15 DQA1_6 DDBIA0_3/QSA_3B C20 VMA_WDQS3 VMB_DQ39 AD5 DQB1_7 DDBIB1_0/QSB_4B AC4 VMB_WDQS4
VMA_DQ39 E14 DQA1_7 DDBIA1_0/QSA_4B C16 VMA_WDQS4 VMB_DQ40 AF1 DQB1_8 DDBIB1_1/QSB_5B AH3 VMB_WDQS5
VMA_DQ40 F14 DQA1_8 DDBIA1_1/QSA_5B C12 VMA_WDQS5 VMB_DQ41 AF3 DQB1_9 DDBIB1_2/QSB_6B AJ8 VMB_WDQS6
VMA_DQ41 D13 DQA1_9 DDBIA1_2/QSA_6B J11 VMA_WDQS6 VMB_DQ42 AF6 DQB1_10 DDBIB1_3/QSB_7B AM3 VMB_WDQS7
VMA_DQ42 F12 DQA1_10 DDBIA1_3/QSA_7B F8 VMA_WDQS7 VMB_DQ43 AG4 DQB1_11
VMA_DQ43 A12 DQA1_11 VMB_DQ44 AH5 DQB1_12 ADBIB0/ODTB0 T7 VMB_ODT0 23
VMA_DQ44 D11 DQA1_12 ADBIA0/ODTA0 J21 VMB_DQ45 AH6 DQB1_13 ADBIB1/ODTB1 W7
VMA_ODT0 22 VMB_ODT1 23
VMA_DQ45 F10 DQA1_13 ADBIA1/ODTA1 G19 VMB_DQ46 AJ4 DQB1_14
VMA_ODT1 22
VMA_DQ46 A10 DQA1_14 VMB_DQ47 AK3 DQB1_15 CLKB0 L9 VMB_CLK0
VMB_CLK0 23
VMA_DQ47 C10 DQA1_15 CLKA0 H27 VMA_CLK0 VMB_DQ48 AF8 DQB1_16 CLKB0B L8 VMB_CLK0#
VMA_CLK0 VMB_CLK0# 23
VMA_DQ48 G13 DQA1_16 CLKA0B G27 VMA_CLK0# VMB_DQ49 AF9 DQB1_17
VMA_CLK0#
VMA_DQ49 H13 DQA1_17 VMB_DQ50 AG8 DQB1_18 CLKB1 AD8 VMB_CLK1 VMB_CLK1 23
VMA_DQ50 J13 DQA1_18 CLKA1 J14 VMA_CLK1 VMB_DQ51 AG7 DQB1_19 CLKB1B AD7 VMB_CLK1#
VMA_CLK1 VMB_CLK1# 23
VMA_DQ51 H11 DQA1_19 CLKA1B H14 VMA_CLK1# VMB_DQ52 AK9 DQB1_20
VMA_CLK1#
VMA_DQ52 G10 DQA1_20 VMB_DQ53 AL7 DQB1_21 RASB0B T10 VMB_RAS0# VMB_RAS0# 23
Place MVREF dividers and Caps close to ASIC VMA_DQ53 G8 DQA1_21 RASA0B K23 VMA_RAS0# SP : Thames Pro 64bit sku not stuff VMB_DQ54 AM8 DQB1_22 RASB1B Y10 VMB_RAS1#
VMA_RAS0# 22 VMB_RAS1# 23
VMA_DQ54 K9 DQA1_22 RASA1B K19 VMA_RAS1# VMB_DQ55 AM7 DQB1_23
VMA_RAS1# 22
VMA_DQ55 K10 DQA1_23 VMB_DQ56 AK1 DQB1_24 CASB0B W10 VMB_CAS0# VMB_CAS0# 23
VMA_DQ56 G9 DQA1_24 CASA0B K20 VMA_CAS0# VMB_DQ57 AL4 DQB1_25 CASB1B AA10 VMB_CAS1#
VMA_CAS0# 22 VMB_CAS1# 23
+1.5V_GFX VMA_DQ57 A8 DQA1_25 CASA1B K17 VMA_CAS1# +1.5V_GFX VMB_DQ58 AM6 DQB1_26
VMA_CAS1# 22
VMA_DQ58 C8 DQA1_26 VMB_DQ59 AM1 DQB1_27 CSB0B_0 P10 VMB_CS0# VMB_CS0# 23
(0.7*VDDR1) VMA_DQ59 E8 DQA1_27 CSA0B_0 K24 VMA_CS0# (0.7*VDDR1) VMB_DQ60 AN4 DQB1_28 CSB0B_1 L10
VMA_CS0# 22
VMA_DQ60 A6 DQA1_28 CSA0B_1 K27 VMB_DQ61 AP3 DQB1_29
VMA_DQ61 C6 DQA1_29 VMB_DQ62 AP1 DQB1_30 CSB1B_0 AD10 VMB_CS1# VMB_CS1# 23
R176 VMA_DQ62 E6 DQA1_30 CSA1B_0 M13 VMA_CS1# R36 VMB_DQ63 AP5 DQB1_31 CSB1B_1 AC10
VMA_CS1# 22
* VMA_DQ63 A5 DQA1_31 CSA1B_1 K16 *
CKEB0 U10 VMB_CKE0 VMB_CKE0 23
MVREFDA L18 MVREFDA CKEA0 K21 VMA_CKE0 MVREFDB Y12 MVREFDB CKEB1 AA11 VMB_CKE1
VMA_CKE0 22 VMB_CKE1 23
MVREFSA L20 MVREFSA CKEA1 J20 VMA_CKE1 MVREFSB AA12 MVREFSB
VMA_CKE1 22
WEB0B N10 VMB_WE0# VMB_WE0# 23
R173 * L27 NC_MEM_CALRN0 WEA0B K26 VMA_WE0# VMA_WE0# 22 WEB1B AB11 VMB_WE1# VMB_WE1# 23
R175 C314 +1.5V_GFX R165 *EV_T@240/F_4 N12 NC_MEM_CALRN1 WEA1B L15 VMA_WE1# VMA_WE1# 22
R37 C207
* * R123 * AG12 NC_MEM_CALRN2 * *
MAB0_8/MAB_13 T8 VMB_MA13
R166 *EV_T@240/F_4 M12 NC_MEM_CALRP1 MAA0_8/MAA_13 H23 VMA_MA13 MAB1_8/MAB_14 W8 VMB_MA14
R170 * M27 MEM_CALRP0 MAA1_8/MAA_14 J19 VMA_MA14 MAB0_9/MAB_15 U12 VMB_MA15
R105 * AH12 MEM_CALRP2 MAA0_9/MAA_15 M21 VMA_MA15 MAB1_9/RSVD V12
MAA1_9/RSVD M20
+1.5V_GFX +1.5V_GFX DRAM_RST AH11 GPU_DRAM_RST

(0.7*VDDR1) (0.7*VDDR1)
EV_SP@GPU_M2
R185 R38
* EV_SP@GPU_M2 SP : Thames PRO() * SP : Thames PRO()
SP : Thames Pro,XT R=240ohm(CS12402FB03) Thames XT(AJ083300T26) Thames XT(AJ083300T26)
Mars R=120ohm(CS11202FB11) Mars() Mars()

R184 C322
Ball Name Thames Mars R39 C225
* * * *
MEM_CALRN0 240ohm X
MEM_CALRN1 X X
25mm (max) 5mm (max) 25mm (max)

MEM_CALRN2 240ohm X Place MVREF dividers and Caps close to ASIC

GPU_DRAM_RST R49 * R40 *
MEM_RST# 22,23
MEM_CALRP0 240ohm 120ohm
C55
MEM_CALRP1 X X R56
* *

MEM_CALRP2 240ohm X

Place all these componets very close to GPU (within 25mm)

and keep all components close to each other
** This basic topology should be used for DRAM_RAT for DDR3/GDDR5

These Capacitors and Resistor values arre an example only

The series R and || cap values will depend on the DRAM loads
and will have to be calculated for differrent Memory, DRAM loads and board
to pass Reset Signal Spec

Quanta Computer Inc.

PROJECT : ZRP
Size Document Number Rev
A1A
Thames_M2/ MEM Interface
Date: Friday, July 20, 2012 Sheet 21 of 46
 5 4 3 2 1

CHANNEL A: 512MB DDR3 (64M*16*4pcs)

22
VMA_DQ[63..0]
21 VMA_DQ[63..0]
VMA_DM[7..0]
21 VMA_DM[7..0]
VMA_RDQS[7..0] QSA[7..0]
21 VMA_RDQS[7..0]
VMA_WDQS[7..0] QSA#[7..0]
21 VMA_WDQS[7..0]
U33 U19
VMA_MA[15..0] U20 U32
VMA_MA[15..0]
VREFC_VMA3 M8 E3 VMA_DQ49 VREFC_VMA4 M8 E3 VMA_DQ60
VREFC_VMA1 M8 VMA_DQ14 VREFC_VMA2 VMA_DQ3 VREFD_VMA3 VREFCA DQL0 VMA_DQ53 VREFD_VMA4 VREFCA DQL0 VMA_DQ56
VREFCA DQL0 E3 M8 VREFCA DQL0 E3 H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7
VREFD_VMA1 H1 F7 VMA_DQ10 VREFD_VMA2 H1 F7 VMA_DQ5 F2 VMA_DQ51 F2 VMA_DQ63
VREFDQ DQL1 VMA_DQ13 VREFDQ DQL1 VMA_DQ2 VMA_MA0 DQL2 VMA_DQ55 VMA_MA0 DQL2 VMA_DQ59
DQL2 F2 DQL2 F2 N3 A0 DQL3 F8 N3 A0 DQL3 F8
VMA_MA0 N3 F8 VMA_DQ8 VMA_MA0 N3 F8 VMA_DQ7 VMA_MA1 P7 H3 VMA_DQ50 VMA_MA1 P7 H3 VMA_DQ62
21 VMA_MA0 A0 DQL3 A0 DQL3 A1 DQL4 A1 DQL4
VMA_MA1 P7 H3 VMA_DQ12 VMA_MA1 P7 H3 VMA_DQ1 VMA_MA2 P3 H8 VMA_DQ54 VMA_MA2 P3 H8 VMA_DQ57
21 VMA_MA1 A1 DQL4 A1 DQL4 A2 DQL5 A2 DQL5
VMA_MA2 P3 H8 VMA_DQ9 VMA_MA2 P3 H8 VMA_DQ4 VMA_MA3 N2 G2 VMA_DQ48 VMA_MA3 N2 G2 VMA_DQ61
21 VMA_MA2 A2 DQL5 A2 DQL5 A3 DQL6 A3 DQL6
VMA_MA3 N2 G2 VMA_DQ15 VMA_MA3 N2 G2 VMA_DQ0 VMA_MA4 P8 H7 VMA_DQ52 VMA_MA4 P8 H7 VMA_DQ58
D 21 VMA_MA3 A3 DQL6 A3 DQL6 A4 DQL7 A4 DQL7 D
VMA_MA4 P8 H7 VMA_DQ11 VMA_MA4 P8 H7 VMA_DQ6 VMA_MA5 P2 VMA_MA5 P2
21 VMA_MA4 A4 DQL7 A4 DQL7 A5 A5
VMA_MA5 P2 VMA_MA5 P2 VMA_MA6 R8 VMA_MA6 R8
21 VMA_MA5 A5 A5 A6 A6
VMA_MA6 R8 VMA_MA6 R8 VMA_MA7 R2 D7 VMA_DQ37 VMA_MA7 R2 D7 VMA_DQ40
21 VMA_MA6 A6 A6 A7 DQU0 A7 DQU0
VMA_MA7 R2 D7 VMA_DQ24 VMA_MA7 R2 D7 VMA_DQ20 VMA_MA8 T8 C3 VMA_DQ32 VMA_MA8 T8 C3 VMA_DQ46
21 VMA_MA7 A7 DQU0 A7 DQU0 A8 DQU1 A8 DQU1
VMA_MA8 T8 C3 VMA_DQ29 VMA_MA8 T8 C3 VMA_DQ19 VMA_MA9 R3 C8 VMA_DQ39 VMA_MA9 R3 C8 VMA_DQ42
21 VMA_MA8 A8 DQU1 A8 DQU1 A9 DQU2 A9 DQU2
VMA_MA9 R3 C8 VMA_DQ26 VMA_MA9 R3 C8 VMA_DQ23 VMA_MA10 L7 C2 VMA_DQ34 VMA_MA10 L7 C2 VMA_DQ44
21 VMA_MA9 A9 DQU2 A9 DQU2 A10/AP DQU3 A10/AP DQU3
VMA_MA10 L7 C2 VMA_DQ31 VMA_MA10 L7 C2 VMA_DQ17 VMA_MA11 R7 A7 VMA_DQ36 VMA_MA11 R7 A7 VMA_DQ43
21 VMA_MA10 A10/AP DQU3 A10/AP DQU3 A11 DQU4 A11 DQU4
VMA_MA11 R7 A7 VMA_DQ25 VMA_MA11 R7 A7 VMA_DQ22 VMA_MA12 N7 A2 VMA_DQ33 VMA_MA12 N7 A2 VMA_DQ45
21 VMA_MA11 A11 DQU4 A11 DQU4 A12/BC DQU5 A12/BC DQU5
VMA_MA12 N7 A2 VMA_DQ30 VMA_MA12 N7 A2 VMA_DQ16 VMA_MA13 T3 B8 VMA_DQ38 VMA_MA13 T3 B8 VMA_DQ41
21 VMA_MA12 A12/BC DQU5 A12/BC DQU5 A13 DQU6 A13 DQU6
VMA_MA13 T3 B8 VMA_DQ27 VMA_MA13 T3 B8 VMA_DQ21 VMA_MA14 T7 A3 VMA_DQ35 VMA_MA14 T7 A3 VMA_DQ47
21 VMA_MA13 A13 DQU6 A13 DQU6 A14 DQU7 A14 DQU7
VMA_MA14 T7 A3 VMA_DQ28 VMA_MA14 T7 A3 VMA_DQ18 VMA_MA15 M7 VMA_MA15 M7
21 VMA_MA14 A14 DQU7 A14 DQU7 A15 A15
VMA_MA15 M7 VMA_MA15 M7 +1.5V_GFX +1.5V_GFX
21 VMA_MA15 A15 A15
+1.5V_GFX +1.5V_GFX
VMA_BA0 M2 B2 VMA_BA0 M2 B2
VMA_BA0 VMA_BA0 VMA_BA1 BA0 VDD#B2 VMA_BA1 BA0 VDD#B2
21 VMA_BA0 M2 BA0 VDD#B2 B2 M2 BA0 VDD#B2 B2 N8 BA1 VDD#D9 D9 N8 BA1 VDD#D9 D9
VMA_BA1 N8 D9 VMA_BA1 N8 D9 VMA_BA2 M3 G7 VMA_BA2 M3 G7
21 VMA_BA1 BA1 VDD#D9 BA1 VDD#D9 BA2 VDD#G7 BA2 VDD#G7
VMA_BA2 M3 G7 VMA_BA2 M3 G7 K2 K2
21 VMA_BA2 BA2 VDD#G7 BA2 VDD#G7 VDD#K2 VDD#K2
VDD#K2 K2 VDD#K2 K2 VDD#K8 K8 VDD#K8 K8
VDD#K8 K8 VDD#K8 K8 VDD#N1 N1 VDD#N1 N1
N1 N1 VMA_CLK1 J7 N9 VMA_CLK1 J7 N9
VDD#N1 VDD#N1 VMA_CLK1 CK VDD#N9 CK VDD#N9
VMA_CLK0 J7 N9 VMA_CLK0 J7 N9 VMA_CLK1# K7 R1 VMA_CLK1# K7 R1
VMA_CLK0 CK VDD#N9 CK VDD#N9 VMA_CLK1# CK VDD#R1 CK VDD#R1
VMA_CLK0# K7 R1 VMA_CLK0# K7 R1 VMA_CKE1 K9 R9 VMA_CKE1 K9 R9
VMA_CLK0# CK VDD#R1 CK VDD#R1 21 VMA_CKE1 CKE VDD#R9 CKE VDD#R9
VMA_CKE0 K9 R9 VMA_CKE0 K9 R9 +1.5V_GFX +1.5V_GFX
21 VMA_CKE0 CKE VDD#R9 CKE VDD#R9
+1.5V_GFX +1.5V_GFX
VMA_ODT1 K1 A1 VMA_ODT1 K1 A1
21 VMA_ODT1 ODT VDDQ#A1 ODT VDDQ#A1
VMA_ODT0 K1 A1 VMA_ODT0 K1 A1 VMA_CS1# L2 A8 VMA_CS1# L2 A8
21 VMA_ODT0 ODT VDDQ#A1 ODT VDDQ#A1 21 VMA_CS1# CS VDDQ#A8 CS VDDQ#A8
VMA_CS0# L2 A8 VMA_CS0# L2 A8 VMA_RAS1# J3 C1 VMA_RAS1# J3 C1
21 VMA_CS0# CS VDDQ#A8 CS VDDQ#A8 21 VMA_RAS1# RAS VDDQ#C1 RAS VDDQ#C1
VMA_RAS0# J3 C1 VMA_RAS0# J3 C1 VMA_CAS1# K3 C9 VMA_CAS1# K3 C9
21 VMA_RAS0# RAS VDDQ#C1 RAS VDDQ#C1 21 VMA_CAS1# CAS VDDQ#C9 CAS VDDQ#C9
VMA_CAS0# K3 C9 VMA_CAS0# K3 C9 VMA_WE1# L3 D2 VMA_WE1# L3 D2
21 VMA_CAS0# CAS VDDQ#C9 CAS VDDQ#C9 21 VMA_WE1# WE VDDQ#D2 WE VDDQ#D2
VMA_WE0# L3 D2 VMA_WE0# L3 D2 E9 E9
21 VMA_WE0# WE VDDQ#D2 WE VDDQ#D2 VDDQ#E9 VDDQ#E9
VDDQ#E9 E9 VDDQ#E9 E9 VDDQ#F1 F1 VDDQ#F1 F1
F1 F1 VMA_RDQS6 F3 H2 VMA_RDQS7 F3 H2
VMA_RDQS1 VDDQ#F1 VMA_RDQS0 VDDQ#F1 VMA_RDQS4 DQSL VDDQ#H2 VMA_RDQS5 DQSL VDDQ#H2
F3 DQSL VDDQ#H2 H2 F3 DQSL VDDQ#H2 H2 C7 DQSU VDDQ#H9 H9 C7 DQSU VDDQ#H9 H9
VMA_RDQS3 C7 H9 VMA_RDQS2 C7 H9
DQSU VDDQ#H9 DQSU VDDQ#H9
VMA_DM6 E7 A9 VMA_DM7 E7 A9
VMA_DM1 VMA_DM0 VMA_DM4 DML VSS#A9 VMA_DM5 DML VSS#A9
E7 DML VSS#A9 A9 E7 DML VSS#A9 A9 D3 DMU VSS#B3 B3 D3 DMU VSS#B3 B3
C VMA_DM3 D3 B3 VMA_DM2 D3 B3 E1 E1 C
DMU VSS#B3 DMU VSS#B3 VSS#E1 VSS#E1
VSS#E1 E1 VSS#E1 E1 VSS#G8 G8 VSS#G8 G8
G8 G8 VMA_WDQS6 G3 J2 VMA_WDQS7 G3 J2
VMA_WDQS1 VSS#G8 VMA_WDQS0 VSS#G8 VMA_WDQS4 DQSL VSS#J2 VMA_WDQS5 DQSL VSS#J2
G3 DQSL VSS#J2 J2 G3 DQSL VSS#J2 J2 B7 DQSU VSS#J8 J8 B7 DQSU VSS#J8 J8
VMA_WDQS3 B7 J8 VMA_WDQS2 B7 J8 M1 M1
DQSU VSS#J8 DQSU VSS#J8 VSS#M1 VSS#M1
VSS#M1 M1 VSS#M1 M1 VSS#M9 M9 VSS#M9 M9
VSS#M9 M9 VSS#M9 M9 VSS#P1 P1 VSS#P1 P1
P1 P1 MEM_RST# T2 P9 MEM_RST# T2 P9
MEM_RST# VSS#P1 MEM_RST# VSS#P1 RESET VSS#P9 RESET VSS#P9
21,23 MEM_RST# T2 RESET VSS#P9 P9 T2 RESET VSS#P9 P9 VSS#T1 T1 VSS#T1 T1
T1 T1 VMA_ZQ3 L8 T9 VMA_ZQ4 L8 T9
VMA_ZQ1 VSS#T1 VMA_ZQ2 VSS#T1 ZQ VSS#T9 ZQ VSS#T9
L8 ZQ VSS#T9 T9 L8 ZQ VSS#T9 T9

VSSQ#B1 B1 VSSQ#B1 B1
VSSQ#B1 B1 VSSQ#B1 B1 VSSQ#B9 B9 VSSQ#B9 B9
B9 B9 R606 D1 R623 D1
R257 VSSQ#B9 R503 VSSQ#B9 * VSSQ#D1 * VSSQ#D1
VSSQ#D1 D1 VSSQ#D1 D1 VSSQ#D8 D8 VSSQ#D8 D8
* D8 * D8 E2 E2
VSSQ#D8 VSSQ#D8 VSSQ#E2 VSSQ#E2
VSSQ#E2 E2 VSSQ#E2 E2 J1 NC#J1 VSSQ#E8 E8 J1 NC#J1 VSSQ#E8 E8
J1 NC#J1 VSSQ#E8 E8 J1 NC#J1 VSSQ#E8 E8 L1 NC#L1 VSSQ#F9 F9 L1 NC#L1 VSSQ#F9 F9
L1 NC#L1 VSSQ#F9 F9 L1 NC#L1 VSSQ#F9 F9 J9 NC#J9 VSSQ#G1 G1 J9 NC#J9 VSSQ#G1 G1
J9 NC#J9 VSSQ#G1 G1 J9 NC#J9 VSSQ#G1 G1 L9 NC#L9 VSSQ#G9 G9 L9 NC#L9 VSSQ#G9 G9
L9 NC#L9 VSSQ#G9 G9 L9 NC#L9 VSSQ#G9 G9
100-BALL 100-BALL
100-BALL 100-BALL SDRAM DDR3 SDRAM DDR3
SDRAM DDR3 SDRAM DDR3 * *
* * EV_SP@ : HYNIX 64x16(AKD5LZWTW05)
EV_SP@ : HYNIX 64x16(AKD5LZWTW05) HYNIX 128x16(AKD5MGWTW17)
HYNIX 128x16(AKD5MGWTW17)

Group-A0 VREF Group-A1 VREF

+1.5V_GFX +1.5V_GFX +1.5V_GFX +1.5V_GFX
+1.5V_GFX +1.5V_GFX +1.5V_GFX +1.5V_GFX
B B

R271 R620 R621 R619

* * * * R624 R516 R622 R270
* * * *

VREFC_VMA1 VREFD_VMA1 VREFC_VMA2 VREFD_VMA2

VREFC_VMA3 VREFD_VMA3 VREFC_VMA4 VREFD_VMA4

R266 C393 R610 C742 R611 C743 R609 C741

R599 C762 R517 C665 R612 C744 R265 C394
* * * * * * * *
* * * * * * * *

Group-A0 decoupling CAP Group-A1 decoupling CAP

MEM_A0 CLK
MEM_A1 CLK
+1.5V_GFX +1.5V_GFX

VMA_CLK0 VMA_CLK1

VMA_CLK0# VMA_CLK1#
C749 C408 C753 C407 C406 C746 C717 C747 C755 C751 C401 C375 C398 C383 C688 C756
* * * * * * * * * * * * * * * *
R605 R604
* * R607 R608
* *
+1.5V_GFX +1.5V_GFX

C764
* C750 C403 C748 C404 C754 C710 C409 C405 C709 C757 C752 C399 C410 C402 C400 C719 C765
A * * * * * * * * * * * * * * * * * A

+1.5V_GFX +1.5V_GFX EV_SP@ : Thames Pro,XT R=56ohm(CS05602FB15)

EV_SP@ : Thames Pro,XT R=56ohm(CS05602FB15) Mars R=40.2ohm(CS04022FB28)
Mars R=40.2ohm(CS04022FB28)

C770 C758 C736 C768 C707 C759 C760 C761 C414 C413
* * * * * * * * * * Quanta Computer Inc.
PROJECT : ZRP
Size Document Number Rev
A1A
Thames_M2/VRAM_A
Date: Friday, July 20, 2012 Sheet 22 of 46
5 4 3 2 1
 5 4 3 2 1

21 VMB_DQ[63..0]

21 VMB_DM[7..0]

21 VMB_RDQS[7..0]
VMB_DQ[63..0]

VMB_DM[7..0]

VMB_RDQS[7..0] QSA[7..0] EV_128@ and EV_128SP@ : Thames Pro(64bit) sku not stuff
CHANNEL B: 512MB DDR3 (64M*16*4pcs)
23
VMB_WDQS[7..0] QSA#[7..0]
21 VMB_WDQS[7..0]
U28 U13 U10 U23
VMB_MA[15..0]
VMB_MA[15..0]
VREFC_VMB1 M8 E3 VMB_DQ3 VREFC_VMB2 M8 E3 VMB_DQ11 VREFC_VMB3 M8 E3 VMB_DQ53 VREFC_VMB4 M8 E3 VMB_DQ59
VREFD_VMB1 VREFCA DQL0 VMB_DQ5 VREFD_VMB2 VREFCA DQL0 VMB_DQ12 VREFD_VMB3 VREFCA DQL0 VMB_DQ49 VREFD_VMB4 VREFCA DQL0 VMB_DQ61
H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7
F2 VMB_DQ1 F2 VMB_DQ15 F2 VMB_DQ54 F2 VMB_DQ58
VMB_MA0 DQL2 VMB_DQ4 VMB_MA0 DQL2 VMB_DQ8 VMB_MA0 DQL2 VMB_DQ50 VMB_MA0 DQL2 VMB_DQ60
21 VMB_MA0 N3 A0 DQL3 F8 N3 A0 DQL3 F8 N3 A0 DQL3 F8 N3 A0 DQL3 F8
VMB_MA1 P7 H3 VMB_DQ2 VMB_MA1 P7 H3 VMB_DQ14 VMB_MA1 P7 H3 VMB_DQ55 VMB_MA1 P7 H3 VMB_DQ57
21 VMB_MA1 A1 DQL4 A1 DQL4 A1 DQL4 A1 DQL4
VMB_MA2 P3 H8 VMB_DQ6 VMB_MA2 P3 H8 VMB_DQ9 VMB_MA2 P3 H8 VMB_DQ51 VMB_MA2 P3 H8 VMB_DQ63
21 VMB_MA2 A2 DQL5 A2 DQL5 A2 DQL5 A2 DQL5
VMB_MA3 N2 G2 VMB_DQ0 VMB_MA3 N2 G2 VMB_DQ13 VMB_MA3 N2 G2 VMB_DQ52 VMB_MA3 N2 G2 VMB_DQ56
D 21 VMB_MA3 A3 DQL6 A3 DQL6 A3 DQL6 A3 DQL6 D
VMB_MA4 P8 H7 VMB_DQ7 VMB_MA4 P8 H7 VMB_DQ10 VMB_MA4 P8 H7 VMB_DQ48 VMB_MA4 P8 H7 VMB_DQ62
21 VMB_MA4 A4 DQL7 A4 DQL7 A4 DQL7 A4 DQL7
VMB_MA5 P2 VMB_MA5 P2 VMB_MA5 P2 VMB_MA5 P2
21 VMB_MA5 A5 A5 A5 A5
VMB_MA6 R8 VMB_MA6 R8 VMB_MA6 R8 VMB_MA6 R8
21 VMB_MA6 A6 A6 A6 A6
VMB_MA7 R2 D7 VMB_DQ22 VMB_MA7 R2 D7 VMB_DQ28 VMB_MA7 R2 D7 VMB_DQ42 VMB_MA7 R2 D7 VMB_DQ38
21 VMB_MA7 A7 DQU0 A7 DQU0 A7 DQU0 A7 DQU0
VMB_MA8 T8 C3 VMB_DQ18 VMB_MA8 T8 C3 VMB_DQ30 VMB_MA8 T8 C3 VMB_DQ46 VMB_MA8 T8 C3 VMB_DQ32
21 VMB_MA8 A8 DQU1 A8 DQU1 A8 DQU1 A8 DQU1
VMB_MA9 R3 C8 VMB_DQ23 VMB_MA9 R3 C8 VMB_DQ25 VMB_MA9 R3 C8 VMB_DQ43 VMB_MA9 R3 C8 VMB_DQ36
21 VMB_MA9 A9 DQU2 A9 DQU2 A9 DQU2 A9 DQU2
VMB_MA10 L7 C2 VMB_DQ19 VMB_MA10 L7 C2 VMB_DQ29 VMB_MA10 L7 C2 VMB_DQ44 VMB_MA10 L7 C2 VMB_DQ33
21 VMB_MA10 A10/AP DQU3 A10/AP DQU3 A10/AP DQU3 A10/AP DQU3
VMB_MA11 R7 A7 VMB_DQ20 VMB_MA11 R7 A7 VMB_DQ31 VMB_MA11 R7 A7 VMB_DQ40 VMB_MA11 R7 A7 VMB_DQ37
21 VMB_MA11 A11 DQU4 A11 DQU4 A11 DQU4 A11 DQU4
VMB_MA12 N7 A2 VMB_DQ17 VMB_MA12 N7 A2 VMB_DQ27 VMB_MA12 N7 A2 VMB_DQ45 VMB_MA12 N7 A2 VMB_DQ35
21 VMB_MA12 A12/BC DQU5 A12/BC DQU5 A12/BC DQU5 A12/BC DQU5
VMB_MA13 T3 B8 VMB_DQ21 VMB_MA13 T3 B8 VMB_DQ24 VMB_MA13 T3 B8 VMB_DQ41 VMB_MA13 T3 B8 VMB_DQ39
21 VMB_MA13 A13 DQU6 A13 DQU6 A13 DQU6 A13 DQU6
VMB_MA14 T7 A3 VMB_DQ16 VMB_MA14 T7 A3 VMB_DQ26 VMB_MA14 T7 A3 VMB_DQ47 VMB_MA14 T7 A3 VMB_DQ34
21 VMB_MA14 A14 DQU7 A14 DQU7 A14 DQU7 A14 DQU7
VMB_MA15 M7 VMB_MA15 M7 VMB_MA15 M7 VMB_MA15 M7
21 VMB_MA15 A15 A15 A15 A15
+1.5V_GFX +1.5V_GFX +1.5V_GFX +1.5V_GFX

VMB_BA0 M2 B2 VMB_BA0 M2 B2 VMB_BA0 M2 B2 VMB_BA0 M2 B2

21 VMB_BA0 BA0 VDD#B2 BA0 VDD#B2 BA0 VDD#B2 BA0 VDD#B2
VMB_BA1 N8 D9 VMB_BA1 N8 D9 VMB_BA1 N8 D9 VMB_BA1 N8 D9
21 VMB_BA1 BA1 VDD#D9 BA1 VDD#D9 BA1 VDD#D9 BA1 VDD#D9
VMB_BA2 M3 G7 VMB_BA2 M3 G7 VMB_BA2 M3 G7 VMB_BA2 M3 G7
21 VMB_BA2 BA2 VDD#G7 BA2 VDD#G7 BA2 VDD#G7 BA2 VDD#G7
VDD#K2 K2 VDD#K2 K2 VDD#K2 K2 VDD#K2 K2
VDD#K8 K8 VDD#K8 K8 VDD#K8 K8 VDD#K8 K8
VDD#N1 N1 VDD#N1 N1 VDD#N1 N1 VDD#N1 N1
VMB_CLK0 J7 N9 VMB_CLK0 J7 N9 VMB_CLK1 J7 N9 VMB_CLK1 J7 N9
21 VMB_CLK0 CK VDD#N9 CK VDD#N9 21 VMB_CLK1 CK VDD#N9 CK VDD#N9
VMB_CLK0# K7 R1 VMB_CLK0# K7 R1 VMB_CLK1# K7 R1 VMB_CLK1# K7 R1
21 VMB_CLK0# CK VDD#R1 CK VDD#R1 21 VMB_CLK1# CK VDD#R1 CK VDD#R1
VMB_CKE0 K9 R9 VMB_CKE0 K9 R9 VMB_CKE1 K9 R9 VMB_CKE1 K9 R9
21 VMB_CKE0 CKE VDD#R9 CKE VDD#R9 21 VMB_CKE1 CKE VDD#R9 CKE VDD#R9
+1.5V_GFX +1.5V_GFX +1.5V_GFX +1.5V_GFX

VMB_ODT0 K1 A1 VMB_ODT0 K1 A1 VMB_ODT1 K1 A1 VMB_ODT1 K1 A1

21 VMB_ODT0 ODT VDDQ#A1 ODT VDDQ#A1 21 VMB_ODT1 ODT VDDQ#A1 ODT VDDQ#A1
VMB_CS0# L2 A8 VMB_CS0# L2 A8 VMB_CS1# L2 A8 VMB_CS1# L2 A8
21 VMB_CS0# CS VDDQ#A8 CS VDDQ#A8 21 VMB_CS1# CS VDDQ#A8 CS VDDQ#A8
VMB_RAS0# J3 C1 VMB_RAS0# J3 C1 VMB_RAS1# J3 C1 VMB_RAS1# J3 C1
21 VMB_RAS0# RAS VDDQ#C1 RAS VDDQ#C1 21 VMB_RAS1# RAS VDDQ#C1 RAS VDDQ#C1
VMB_CAS0# K3 C9 VMB_CAS0# K3 C9 VMB_CAS1# K3 C9 VMB_CAS1# K3 C9
21 VMB_CAS0# CAS VDDQ#C9 CAS VDDQ#C9 21 VMB_CAS1# CAS VDDQ#C9 CAS VDDQ#C9
VMB_WE0# L3 D2 VMB_WE0# L3 D2 VMB_WE1# L3 D2 VMB_WE1# L3 D2
21 VMB_WE0# WE VDDQ#D2 WE VDDQ#D2 21 VMB_WE1# WE VDDQ#D2 WE VDDQ#D2
VDDQ#E9 E9 VDDQ#E9 E9 VDDQ#E9 E9 VDDQ#E9 E9
VDDQ#F1 F1 VDDQ#F1 F1 VDDQ#F1 F1 VDDQ#F1 F1
VMB_RDQS0 F3 H2 VMB_RDQS1 F3 H2 VMB_RDQS6 F3 H2 VMB_RDQS7 F3 H2
VMB_RDQS2 DQSL VDDQ#H2 VMB_RDQS3 DQSL VDDQ#H2 VMB_RDQS5 DQSL VDDQ#H2 VMB_RDQS4 DQSL VDDQ#H2
C7 DQSU VDDQ#H9 H9 C7 DQSU VDDQ#H9 H9 C7 DQSU VDDQ#H9 H9 C7 DQSU VDDQ#H9 H9

VMB_DM0 E7 A9 VMB_DM1 E7 A9 VMB_DM6 E7 A9 VMB_DM7 E7 A9

VMB_DM2 DML VSS#A9 VMB_DM3 DML VSS#A9 VMB_DM5 DML VSS#A9 VMB_DM4 DML VSS#A9
C D3 DMU VSS#B3 B3 D3 DMU VSS#B3 B3 D3 DMU VSS#B3 B3 D3 DMU VSS#B3 B3 C

VSS#E1 E1 VSS#E1 E1 VSS#E1 E1 VSS#E1 E1

VSS#G8 G8 VSS#G8 G8 VSS#G8 G8 VSS#G8 G8
VMB_WDQS0 G3 J2 VMB_WDQS1 G3 J2 VMB_WDQS6 G3 J2 VMB_WDQS7 G3 J2
VMB_WDQS2 DQSL VSS#J2 VMB_WDQS3 DQSL VSS#J2 VMB_WDQS5 DQSL VSS#J2 VMB_WDQS4 DQSL VSS#J2
B7 DQSU VSS#J8 J8 B7 DQSU VSS#J8 J8 B7 DQSU VSS#J8 J8 B7 DQSU VSS#J8 J8
VSS#M1 M1 VSS#M1 M1 VSS#M1 M1 VSS#M1 M1
VSS#M9 M9 VSS#M9 M9 VSS#M9 M9 VSS#M9 M9
VSS#P1 P1 VSS#P1 P1 VSS#P1 P1 VSS#P1 P1
MEM_RST# T2 P9 MEM_RST# T2 P9 MEM_RST# T2 P9 MEM_RST# T2 P9
21,22 MEM_RST# RESET VSS#P9 RESET VSS#P9 RESET VSS#P9 RESET VSS#P9
VSS#T1 T1 VSS#T1 T1 VSS#T1 T1 VSS#T1 T1
VMB_ZQ1 L8 T9 VMB_ZQ2 L8 T9 VMB_ZQ3 L8 T9 VMB_ZQ4 L8 T9
ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9

VSSQ#B1 B1 VSSQ#B1 B1 VSSQ#B1 B1 VSSQ#B1 B1

VSSQ#B9 B9 VSSQ#B9 B9 VSSQ#B9 B9 VSSQ#B9 B9
R475 D1 R159 D1 R132 D1 R419 D1
* VSSQ#D1 * VSSQ#D1 * VSSQ#D1 * VSSQ#D1
VSSQ#D8 D8 VSSQ#D8 D8 VSSQ#D8 D8 VSSQ#D8 D8
VSSQ#E2 E2 VSSQ#E2 E2 VSSQ#E2 E2 VSSQ#E2 E2
J1 NC#J1 VSSQ#E8 E8 J1 NC#J1 VSSQ#E8 E8 J1 NC#J1 VSSQ#E8 E8 J1 NC#J1 VSSQ#E8 E8
L1 NC#L1 VSSQ#F9 F9 L1 NC#L1 VSSQ#F9 F9 L1 NC#L1 VSSQ#F9 F9 L1 NC#L1 VSSQ#F9 F9
J9 NC#J9 VSSQ#G1 G1 J9 NC#J9 VSSQ#G1 G1 J9 NC#J9 VSSQ#G1 G1 J9 NC#J9 VSSQ#G1 G1
L9 NC#L9 VSSQ#G9 G9 L9 NC#L9 VSSQ#G9 G9 L9 NC#L9 VSSQ#G9 G9 L9 NC#L9 VSSQ#G9 G9

100-BALL 100-BALL 100-BALL 100-BALL

SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
* * * *

BOT Down EV_128SP@ : HYNIX 64x16(AKD5LZWTW05)

HYNIX 128x16(AKD5MGWTW17) TOP Down TOP Up
EV_128SP@ : HYNIX 64x16(AKD5LZWTW05)
HYNIX 128x16(AKD5MGWTW17) BOT Up

Group-B1 VREF
Group-B0 VREF
+1.5V_GFX +1.5V_GFX +1.5V_GFX +1.5V_GFX
B B
+1.5V_GFX +1.5V_GFX +1.5V_GFX +1.5V_GFX

R121 R76 R434 R130

R146 R485 R156 R151 * * * *
* * * *

VREFC_VMB3 VREFD_VMB3 VREFC_VMB4 VREFD_VMB4

VREFC_VMB1 VREFD_VMB1 VREFC_VMB2 VREFD_VMB2

R122 C131 R82 C97 R423 C566 R131 C153

R147 C212 R483 C626 R157 C248 R152 C214
* * * * * * * *
* * * * * * * *

Group-B0 decoupling CAP Group-B1 decoupling CAP

MEM_B0 CLK MEM_B1 CLK
+1.5V_GFX +1.5V_GFX

VMB_CLK1

VMB_CLK0 C605 C54 C338 C642 C580 C343 C600 C533 C40 C493 C491 C104 C84 C536 C515 VMB_CLK1#

VMB_CLK0# * * * * * * * * * * * * * * *
R416 R412
* *
R477 R479
* * +1.5V_GFX +1.5V_GFX

A C339 C675 C588 C370 C647 C576 C337 C674 C46 C69 C573 C525 C539 C530 C597 A
C545
C618 * * * * * * * * * * * * * * * *
*

EV_128SP@ : Thames Pro,XT R=56ohm(CS05602FB15)

+1.5V_GFX +1.5V_GFX
Mars R=40.2ohm(CS04022FB28)

EV_128SP@ : Thames Pro,XT R=56ohm(CS05602FB15) C610 C415 C649 C638 C680 C489 C524 C56 C60 C113 Quanta Computer Inc.
Mars R=40.2ohm(CS04022FB28) * * * * * * * * * *
PROJECT : ZRP
Size Document Number Rev
A1A
Thames_M2/VRAM_B
Date: Friday, July 20, 2012 Sheet 23 of 46
5 4 3 2 1
 5 4 3 2 1

+3V
20mils DVDD33
DVDD12
20mils
L53
+1.2V_TRAVIS

LVDS@HCB1608KF-221T20_2A
24
L2 LVDS@HCB1608KF-221T20_2A C470 C26 C471 C33
C28
C485 C27 LVDS@0.1u/10V_4 LVDS@0.1u/10V_4
LVDS@0.1u/10V_4 LVDS@0.1u/10V_4 LVDS@1u/6.3V_4
LVDS@1u/6.3V_4 LVDS@0.1u/10V_4 U22
+3V AVDD33 +1.2V_TRAVIS
D 20mils 9
20mils D
DVDD12 AVDD12
13 DVDD33 DVDD12 32
L50 LVDS@HCB1608KF-221T20_2A 53 46 L1 LVDS@HCB1608KF-221T20_2A
DVDD33 DVDD12 C31 C34 C36
DVDD12 59
C35 C468 C461 C23 C29 8 AVDD33 LVDS@0.01u/25V_4 LVDS@1u/6.3V_4
25 AVDD33 AVDD12 1
LVDS@1u/6.3V_4 LVDS@0.1u/10V_4 LVDS@0.1u/10V_4 33 LVDS@0.1u/10V_4
LVDS@0.1u/10V_4 LVDS@0.1u/10V_4 AVDD33
39 AVDD33
63 AVDD33 LVDS_L3_P 29
LVDS_L3_N 28
INT_LVDS_TXP1 INT_LVDS_TXP1 6 24 INT_LCD_TXLOUT2+ 25
INT_LVDS_TXN1 DPRX_LN1_P LVDS_L2_P
INT_LVDS_TXN1 7 DPRX_LN1_N LVDS_L2_N 23 INT_LCD_TXLOUT2- 25
LVDS_L1_P 22 INT_LCD_TXLOUT1+ 25
INT_LVDS_TXP0 INT_LVDS_TXP0 3 21 INT_LCD_TXLOUT1- 25
+3V INT_LVDS_TXN0 DPRX_LN0_P LVDS_L1_N
INT_LVDS_TXN0 4 DPRX_LN0_N LVDS_L0_P 20 INT_LCD_TXLOUT0+ 25
LVDS_L0_N 19 INT_LCD_TXLOUT0- 25
R333 *LVDS@1M_4 INT_LVDS_AUXP 5 INT_LVDS_AUXP INT_LVDS_AUXP 61
INT_LVDS_AUXN DPRX_AUX_P
5 INT_LVDS_AUXN 60 DPRX_AUX_N LVDS_CLKL_P 27 INT_LCD_TXLCLKOUT+ 25
R337 *LVDS@1M_4 INT_LVDS_AUXN +3V R31 *LVDS@100K_4 26 INT_LCD_TXLCLKOUT- 25
LVDS_CLKL_N
INT_LVDS_eDP_HPD 58 DPPX_HPD
LVDS_U3_P 45
APU_VARY_BL_Q 48 44
C462 LVDS@0.1u/10V_4 CPU_VARY_BL LVDS_U3_N
LVDS_U2_P 41
+3V R308 LVDS@1M_4 ANX_POR 34 40
POR LVDS_U2_N
LVDS_U1_P 38
TRAVIS_RST# 12 37
R322 *LVDS@10K_4 RESET_L LVDS_U1_N
LVDS_U0_P 36
+3V R320 LVDS@10K_4 ANX_CLKSEL 10 35
CLKSEL LVDS_U0_N

LVDS_CLKU_P 43
C R28 LVDS@12.1K/F_4 64 42 C
C32 LVDS@100p/50V_4 R_BIAS LVDS_CLKU_N

CLK_PCIE_TRAVISP 30 OSC_IN DDC_CLK 49 INT_LCD_EDIDCLK 25

CLK_PCIE_TRAVISN 31 OSC_OUT DDC_DATA 50 INT_LCD_EDIDDATA 25

54 TDO BL_EN 15 TRAVIS_BL_EN 25

55 TDI DIGON 14 TRAVIS_DIGON 25
56 47 VARY_BL
TCK VARY_BL
57 TMS
Care sequenc, S5 - S0, S0 - S3, S3 - S0
R319 *LVDS@10K_4 11 NC1
51 NC2
TP2 52
TP1 NC3
2 AVSS GPIO2 18
5 AVSS GPIO1 17
62 16 R309 LVDS@10K_4
AVSS GPIO0
65 PAD

INT_LVDS_TXP0 R326 * eDP_MLP0 25

LVDS@ANX3111 INT_LVDS_TXN0 R323 * eDP_MLN0 25
INT_LVDS_AUXP R327 * eDP_AUXP 25
INT_LVDS_AUXN R328 * eDP_AUXN 25
+1.5VSUS APU_VARY_BL_Q R335 * VARY_BL_R R331 *
B
VARY_BL 25 B
+1.5VSUS INT_LVDS_eDP_HPD R29 * eDP_HPD 25
R27
2.2K_4
DVDD33 +3V

R26
*2.2K_4
R30 R32
C30 LVDS@4.7K_4 *
2

*0.1u/10V_4
+5V_S5
1 3 APU_VARY_BL_Q +1.2V Q33 +1.2V_TRAVIS
5 APU_VARY_BL
LVDS@PMV45EN_4A

Q7 FDV301N_200MA R330 3 1
+5V_S5
LVDS@100K_4
Q33

2
1st BAM34040001, Rdson=22.5m
R361 2nd BAM2306006, Rdson=38m
+3V +3V

3
LVDS@4.7K_4 C477

5 LVDS@0.1u/10V_4
R25 R334 Q31B
LVDS@10K_4 LVDS@120K/F_4 LVDS@2N7002KDW_115MA
6

PCIE_RST#_TRAVIS D4 *LVDS@BAS316(75V_250MA) TRAVIS_RST# 2

A Q31A A
C25 C480 LVDS@2N7002KDW_115MA
1

8,14,28,32,34 PCIE_RST# 1 2 LVDS@0.1u/10V_4 LVDS@1u/6.3V_4

D2 LVDS@RB500V-40_100MA R356 *LVDS@0_4
TRAVIS_EN# 7
Care TRAVIS_EN# active Hi not active Lo
Quanta Computer Inc.
PROJECT : ZRP
Size Document Number Rev
A1A
TRAVIS ANX3110
Date: Friday, July 20, 2012 Sheet 24 of 46
5 4 3 2 1
 1 2 3 4 5 6 7 8

LVDS(LDS)
EDID_PWR CCD_PWR TP_PWR VIN
LCD PW(LDS) +3V
25
C10 LCDVCC
C459 C460 C13 C15 C21 C22 C18 C14 1u/6.3V_4 U2

*10p/50V_4 1000p/50V_4 *10p/50V_4 1000p/50V_4 *10p/50V_4 1000p/50V_4 4.7u/25V_8 1000p/50V_4 6 1 LCDVCC_R

R9 40mil LCDVCC
IN OUT
*short_8
A
4 IN GND 2 A
C2 C8 C7 C4
R18 LVDS@0_4 3 5
24 TRAVIS_DIGON ON/OFF GND 1u/6.3V_4 *0.1u/10V_4 0.01u/16V_4 10u/6.3V_8

R19 * IC(5P)-G5243T11U
5 eDP_DIGON
CN6 R17

G_0
VIN R20 *short_6 LCD_VIN
R21 *short_6 1 100K_4
2
LCDVCC 3
LCDVCC 4
5
R306 *short_6 EDID_PWR 6
+3V 7
+3V R310 LVDS@4.7K_4 R22 *short_6 CCD_PWR
R321 LVDS@4.7K_4 8
R15 *short_6 TP_PWR 9
+5V 10 G_1
INT_LCD_EDIDDATA
24 INT_LCD_EDIDDATA 11
INT_LCD_EDIDCLK
24 INT_LCD_EDIDCLK 12
R4 0_4 LVDS_BRIGHT
24
34
24
VARY_BL
CONTRAST
eDP_HPD
R5 *0_4 C1 0.1u/10V_4 BL_ON 13
14 Backlight Control(LDS)
15
24 INT_LCD_TXLCLKOUT- 16 +3VPCU
24 INT_LCD_TXLCLKOUT+ 17 +3V
18
24 INT_LCD_TXLOUT0+ 19

1
24 INT_LCD_TXLOUT0- 20
21 R3
LVDS 24 INT_LCD_TXLOUT1+ 22 *100K_4
24 INT_LCD_TXLOUT1- 23
B R1 R2 B

2
24
24 INT_LCD_TXLOUT2+ 25 10K_4 10K_4
24 INT_LCD_TXLOUT2- 26 BL_ON D1 2 1 BAS316 LID591# 34
27
24 eDP_MLP0 28
24 eDP_MLN0 29
eDP R312 *
30

3
eDP_AUXP
24 eDP_AUXP 31 G_4

3
eDP_AUXN
24 eDP_AUXN 32
+3V R313 *
USBP6+_R 33 BL#
34 2 2 EC_FPBACK# 34
USBP6-_R
35

3
Q2 Q3
USBP8+_R 36 2N7002K DTC144EUA

1
R317 *short_4 USBP8-_R 37

1
TP_GND 38 R13 LVDS@0_4
7 USBP6+ 39 24 TRAVIS_BL_EN 2
CCD 7 TP_INT
USBP6- 40

G_5
R314 *short_4 Q1
LVDS_CONN R7 * 2N7002K
5 eDP_BL_EN
R8 R6

1
0_6
100K_4
C467 15p/50V_4 R311 300_4

L52
7 USBP8+ 1 1 2 2 Add for leakage
Touch Panel 7 USBP8- 4 4 3 3
C +3V_S5 +3V +3V C
*TP@DLP11SN900HL2L

Lid Switch (HSR)

C463 *TP@15p/50V_4 R307 *TP@300_4 R665 Q46 R666
*TP@10K_4 *TP@BSN20 *TP@10K_4
2

1 3 TP_INT
7 TP_INT_FCH +3VPCU

C458 1u/10V_4 1 2 LID591#

CRT DB

2
3
D14 HE1 D15
EMI reserve *VPORT_6 OCH1691WAD *VPORT_6
CN17

1
R551 BLM18BB750SN1D FCH_CRT_RED_R 1 EM-6781-T3: AL006781000
9 FCH_CRT_RED
2 APX9132H AI-TRG: AL009132001
R542 BLM18BB750SN1D FCH_CRT_GRE_R 3
9 FCH_CRT_GRE AH9249NTR-G1: AL009249000
4
R536 BLM18BB750SN1D FCH_CRT_BLU_R 5
9 FCH_CRT_BLU
6
D
9 FCH_CRT_HSYNC 7 D
8
9 FCH_CRT_VSYNC 9
10
9 FCH_DDCCLK 11
9 FCH_DDCDAT 12 15
13 16
+5V
+3V 14 Quanta Computer Inc.
PROJECT : ZRP
CRT_DB_CONN Size Document Number Rev
LVDS&CCD&CRT DB&LID A1A

Date: Wednesday, July 25, 2012 Sheet 25 of 46

1 2 3 4 5 6 7 8
 5 4 3 2 1

HDMI
26
ESD3
1 10 INT_HDMI_TXDP2 CN11
5 INT_HDMI_TXDP2 1 10
2 9 INT_HDMI_TXDN2 20
5 INT_HDMI_TXDN2 2 9 SHELL1
3 GND_3/8 SHELL3 22
D INT_HDMI_TXDP1 INT_HDMI_TXDP2 D
5 INT_HDMI_TXDP1 4 4 7 7 1 D2+
5 6 INT_HDMI_TXDN1 2
5 INT_HDMI_TXDN1 5 6 D2 Shield
INT_HDMI_TXDN2 3
*HM@RClamp0524P INT_HDMI_TXDP1 D2-
4 D1+
5 D1 Shield
ESD2 INT_HDMI_TXDN1 6
INT_HDMI_TXDP0 INT_HDMI_TXDP0 D1-
5 INT_HDMI_TXDP0 1 1 10 10 7 D0+
INT_HDMI_TXDN0
ESD 5 INT_HDMI_TXDN0 2
3
2 9 9
INT_HDMI_TXDN0
8
9
D0 Shield
GND_3/8 INT_HDMI_TXCP INT_HDMI_TXCP D0-
5 INT_HDMI_TXCP 4 4 7 7 10 CK+
5 6 INT_HDMI_TXCN 11
5 INT_HDMI_TXCN 5 6 CK Shield
INT_HDMI_TXCN 12
*HM@RClamp0524P CK-
13 CE Remote
14 NC
ESD1 HDMI_DDCCLK 15
HDMI_DDCCLK HDMI_DDCCLK F1 HDMI_DDCDATA DDC CLK
1 1 10 10 16 DDC DATA
HDMI_DDCDATA 2 9 HDMI_DDCDATA *SMD1206P100TF D18 17
2 9 +5V_HDMI_R *SBR2U30SA +5V_HDMI GND
3 GND_3/8 +5V 2 1 18 +5V
HDMI_DET 4 7 HDMI_DET HDMI_DET 19
+5V_HDMI 4 7 +5V_HDMI HP DET
5 5 6 6 SHELL4 23

1
SHELL2 21
*HM@RClamp0524P Q24 RV1
3 1 *EGA_4 HDMI_CONN
IN OUT
2

2
GND C475
AP2331SA-7 C24 D19 *1000p/50V_4
C C
*220p/50V_4 *EGA_4
HDMI_PL_MOS R370 604/F_4 INT_HDMI_TXDP2

R365 604/F_4 INT_HDMI_TXDN2 C472

*1000p/50V_4
3

+5V R362 604/F_4 INT_HDMI_TXDP1

Q35
2N7002K R357 604/F_4 INT_HDMI_TXDN1
2
R353 604/F_4 INT_HDMI_TXDP0

R344 604/F_4 INT_HDMI_TXDN0

1

R341 604/F_4 INT_HDMI_TXCP

R343
R336 604/F_4 INT_HDMI_TXCN

100K_4
EMI reserve for HDMI(EMC)
Close connector
B B

HDMI SDVO I2C Control HDMI HPD SENSE INT_HDMI_TXDP2

+5V +3V R368

*120/F_4
INT_HDMI_TXDN2
2

D16 R305 INT_HDMI_TXDP1

RB501V-40 10K_4
+3V +3V R360
*120/F_4
1

INT_HDMI_TXDN1

R11 Q4 R12 INT_HDMI_TXDP0

2

3
2.2K_4 BSN20 2.2K_4 +3V
R348
1 3 HDMI_DDCCLK *120/F_4
5 INT_HDMI_AUXP
2 HDMI_DET INT_HDMI_TXDN0
R304
+5V 1K_4 Q25 INT_HDMI_TXCP
2N7002K R318
100K_4 R338

1
2

*120/F_4
5 INT_HDMI_HPD
D17 INT_HDMI_TXCN
3

RB501V-40
A +3V +3V A
1

2 HDMI_HPD_EC# 34
Q6
R23 R24 Q23
Quanta Computer Inc.
2

2.2K_4 BSN20 2.2K_4 2N7002K

1

HDMI_DDCDATA
5 INT_HDMI_AUXN 1 3 PROJECT : ZRP
Size Document Number Rev
HDMI A1A

Date: Friday, July 20, 2012 Sheet 26 of 46

5 4 3 2 1
 A B C D E

5 in 1 CARD READER IC (SD,MMC,xD,MS)

27
PIN43=Power saving mode enable.

SD_WP/XD_CLE/MS_CLK
C743 close PIN46, 47
+1.8V_VDD '1' for enable [Default]

SD_D1/XD_D1/MS_D1
SD_D0/XD_D0/MS_D0
CTRL0, CRTL 1 trace length shorter ,

TP50
C708 close PIN48, 47 '0' for disable and surround with GND.

SD_CD#/XD_WE#
+3V

SD_D7/XD_D7
C625 C620
4 4

XTALSEL
0.1u/16V_4 0.1u/16V_4

NBMD
C1_IOP C598 *27p/50V_4 XI

48
47
46
45
44
43
42
41
40
39
38
37
U29 Y2 R469
+3V C646 C641 *12MHZ *270K_4

VDDHM

C1_VSSHM
GND
VDD

HID
NBMD
XTALSEL

CTRL1
CTRL3
DATA1
DATA0
DATA7
0.1u/16V_4 *4.7u/10V_6
C786 33P/50V_4 C608 *27p/50V_4 XO
R473
*100K_4 1 36
LED C1_VDDHM
8 CardReader_48M
R476 0_4 EXT48MHZ_R 2 EXT48IN DATA6 35 SD_D6/XD_D6 PIN45=Clock input selection
R474 *short_4 3 34 SD_CLK/XD_ALE/MS_BS
8,28,34 PLTRST# C606 *0.47u/10V_6 R471 330_4 4
RSTN CTRL0
33 SD_D5/XD_D5 '1' for 48MHz input [Default,Internal PU]
+3V R468 *short_6 +3V_VDD 5
REXT
VD33P
DATA5
CTRL2 32 SD_CMD_/XD_RB# '0' for 12MHz input
USBP5+_R 6 31 SD_D4/XD_D4
USBP5-_R DP AU6435B52-GDL-GR DATA4 SD_D3/XD_D3/MS_D3
7 DM DATA3 30
8 29 SD_D2/XD_D2/MS_D2 *0_4 R482 XTALSEL
C604 C603 XI VS33P DATA2 XD_WP#
9 XI XDWPN 28
C601 XO 10 27 XD_CE#
4.7u/10V_6 *5p/50V_4 *5p/50V_4 XO XDCEN EEPDATA
11 VDD EEPDATA 26
+1.8V_VDD 12 25 EEPCLK TP51

VSSA_SYN
V18 EEPCLK TP29

SDWPEN
AGND5V
AVDD5V

VDDHM
C1_V33
C1_IOP

XDCDN
CTRL4
C615

GND
VDD
V33
4.7u/10V_6 SD write protect
3 1:decided by SDWP[Default] 3
0:disable SD write protect

13
14
15
16
17
18
19
20
21
22
23
24
7 USBP5+ R453 *short_4 USBP5+_R pin13 output 20mils *0_4 R490
R465 *short_4 USBP5-_R VCC_XD XD_CD#
7 USBP5-
XD_RE#/MS_INS#
C1_IOP +1.8V_VDD
C619 0.1u/16V_4 +3V
+3V
C630 2.2u/6.3V_6
C602 *15p/50V_4 R470 *300_4 C623
+3V
C636 4.7u/10V_6 0.1u/16V_4

5 IN 1 CARD READER CONN (SD/MMC)

SD_CLK/XD_ALE/MS_BS and SD_CLK_R trace length
shorter , surround with GND.
VCC_XD
VCC_XD SD_CLK_R
2 2
CN2
C645
11 22
SD-VCC XD-VCC *10p/50V_4
18 MS-VCC

SD_CD#/XD_WE# 1 23 SD_D7/XD_D7
SD_WP/XD_CLE/MS_CLK SD-CD XD-DATA7 SD_D6/XD_D6
2 SD-WP XD-DATA6 24
SD_D1/XD_D1/MS_D1 R480 33_4 SD_D1_R 3 25 SD_D5/XD_D5
SD_D0/XD_D0/MS_D0 R481 33_4 SD_D0_R SD-DAT1 XD-DATA5 SD_D4/XD_D4
4 SD-DAT0 XD-DATA4 26
SD_CLK/XD_ALE/MS_BS R493 33_4 SD_CLK_R 9 27 SD_D3/XD_D3/MS_D3
SD_CMD_/XD_RB# R545 33_4 SD_CMD_R SD-CLK XD-DATA3 SD_D2/XD_D2/MS_D2
16 SD-CMD XD-DATA2 28
SD_D3/XD_D3/MS_D3 R571 33_4 SD_D3_R 19 29 SD_D1/XD_D1/MS_D1
SD_D2/XD_D2/MS_D2 R580 33_4 SD_D2_R SD-CD/DATA3 XD-DATA1 SD_D0/XD_D0/MS_D0
21 SD-DATA2 XD-DATA0 30
VCC_XD

32 XD_WP#
SD_CLK/XD_ALE/MS_BS XD-WP 33 SD_CD#/XD_WE#
7 MS-BS XD-WE
SD_D1/XD_D1/MS_D1 8 34 SD_CLK/XD_ALE/MS_BS
SD_D0/XD_D0/MS_D0 MS-VCC-DATA1 XD-ALE 35 SD_WP/XD_CLE/MS_CLK C628 C622 C698 C669
10 MS-SDIO/DATA0 XD-CLE
SD_D2/XD_D2/MS_D2 12 36 XD_CE# R478
XD_RE#/MS_INS# MS-DATA2 XD-CE XD_RE#/MS_INS# 4.7u/10V_6 0.1u/16V_4 0.1u/16V_4 0.1u/16V_4 5.1K/F_4
14 MS-INS XD-RE 37
SD_D3/XD_D3/MS_D3 15 38 SD_CMD_/XD_RB#
SD_WP/XD_CLE/MS_CLK R552 *short_4 MS_CLK_R MS-DATA3 XD-R/B XD_CD#_R R558 *short_4 XD_CD#
17 MS-SCLK XD-CD 39

C690
XD-GND
31 Reserved for combo connector,
*10p/50V_4 5 MS-VSS1 XD-GND2
40 which has MS adaptor short
6 SD-VSS1 issue with XDCDN
1 13 SD-VSS2 SD-CD/WP-GND1 41 1
20 MS-VSS2 SD-CD/WP-GND2 42

SD_WP/XD_CLE/MS_CLK and MS_CLK_R trace length 144-1300002600

shorter , surround with GND.
Quanta Computer Inc.
PROJECT : ZRP
Size Document Number Rev
CardReader (5 IN 1) A1A

Date: Friday, July 20, 2012 Sheet 27 of 46

A B C D E
 1 2 3 4 5 6 7 8

28
+3V +WL_VDD

MINI-CARD WLAN(MPC) R444 NAC@0_8

+3.3V: 1000mA C648 C593 C592 C596

+3.3Vaux:330mA 10u/10V_8 0.1u/10V_4 *0.1u/10V_4 *0.1u/10V_4
+1.5V:500mA +3VPCU
+WL_VDD Q43
1 3

*
CN15 R464 +WL_1.5V +1.5V

2
34 BT_POWERON# R498 0_4 51 52 +WL_VDD
Reserved +3.3V *AC@4.7K_4 R427 * R455 *0_6
A 49 Reserved GND 50 34 IOAC_LANPWR#
A
R497 *0_4 PCIE_RST#_C 47 48
8,14,24,32,34 PCIE_RST# Reserved +1.5V
R496 *0_4 PCLK_DEBUG_R 45 46 WLAN_OFF_R R451 * C564
8 PCLK_DEBUG Reserved LED_WPAN# WLAN_OFF 34
43 44 TP28 C587 C300 C589
GND LED_WLAN# * *1000p/50V_4 *0.1u/10V_4 *10u/6.3V_8
+WL_VDD 41 +3.3Vaux LED_WWAN# 42
39 +3.3Vaux GND 40
37 GND USB_D+ 38 USBP7+ 7
35 GND USB_D- 36 USBP7- 7
33 34 +WL_VDD
3 PCIE_TXP0_WLAN PETp0 GND
31 32 WL_SMDATA
3 PCIE_TXN0_WLAN PETn0 SMB_DATA
29 30 WL_SMCLK C594 *15p/50V_4 R461 *300_4 USBP7-
GND SMB_CLK
27 GND +1.5V 28 +WL_1.5V

5
25 26 U12
3 PCIE_RXP0_WLAN PERp0 GND
3 PCIE_RXN0_WLAN 23 PERn0 +3.3Vaux 24 +WL_VDD 2 PLTRST# 8,27,34
21 22 PLTRST#_R 4
GND PERST#
19 UIM_C4 W_DISABLE# 20 RF_EN 34 1 IOAC_RST# 34
17 UIM_C8 GND 18
*AC@TC7SH08FU

3
15 16 DEBUG_LFRAME# R460 *short_4
GND UIM_VPP LPC_LFRAME# 8,34
13 14 DEBUG_LAD3 R459 *short_4 LPC_LAD3 8,34
8 CLK_PCIE_WLANP REFCLK+ UIM_RESET
11 12 DEBUG_LAD2 R458 *short_4 LPC_LAD2 8,34 Debug
8 CLK_PCIE_WLANN REFCLK- UIM_CLK
9 10 DEBUG_LAD1 R457 *short_4 LPC_LAD1 8,34 R162 *AC@0_4
PCIE_REQ_WLAN#_R GND UIM_DATA DEBUG_LAD0 R456 *short_4 R161 0_4
7 CLKREQ# UIM_PWR 8 LPC_LAD0 8,34
5 Reserved +1.5V 6 +WL_1.5V
3 4

GND

GND
PCIE_WAKE#_WLAN_R Reserved GND
1 WAKE# +3.3V 2 +WL_VDD
MINI-CARD1 +WL_VDD

53

54
+WL_VDD

B B
R155 R154
R180 R181 Q9 * *
Q11 * * 5
R182 *
EC: +3VPCU +3VPCU 5
3 4 WL_SMDATA
7,12,13 PDAT_SMB
3 4 PCIE_WAKE#_WLAN_R
34 PCIE_WAKE#_WLAN
2
FCH: +3V 2
6 1 WL_SMCLK
7,12,13 PCLK_SMB
6 1 PCIE_REQ_WLAN#_R
7 PCIE_REQ_WLAN#
*
*

R466 NAC@0_4
R172 NAC@0_4
R454 NAC@0_4

MINI-CARD SSD

+3V_SATA

C C
CN3
51 Reserved +3.3V 52
49 Reserved GND 50
47 Reserved +1.5V 48
45 Reserved LED_WPAN# 46
43 GND LED_WLAN# 44
41 42 +3V
+3.3Vaux LED_WWAN#
39 +3.3Vaux GND 40
37 38 R640 *SHORT_8 +3V_SATA
GND USB_D+
35 GND USB_D- 36
C423 * SATA_TXP2_C 33 34
9 SATA_TXP2 PETp0 GND
C429 * SATA_TXN2_C 31 32 C779 C739 C784
9 SATA_TXN2 PETn0 SMB_DATA
29 GND SMB_CLK 30
27 28 * * *SSD@0.1u/10V_4
C436 * SATA_RXN2_C GND +1.5V
9 SATA_RXN2 25 PERp0 GND 26
9 SATA_RXP2 C439 * SATA_RXP2_C 23 24
PERn0 +3.3Vaux
21 GND PERST# 22
19 UIM_C4 W_DISABLE# 20
17 UIM_C8 GND 18
rating = 1000mA @ 128G
15 GND UIM_VPP 16
13 REFCLK+ UIM_RESET 14
11 REFCLK- UIM_CLK 12
9 GND UIM_DATA 10
7 CLKREQ# UIM_PWR 8
5 Reserved +1.5V 6
3 4
GND

GND

Reserved GND
1 WAKE# +3.3V 2

*
53

54

D D

Quanta Computer Inc.

PROJECT : ZRP
Size Document Number Rev
MINI PCIE(WLAN/SSD) A1A

Date: Friday, July 20, 2012 Sheet 28 of 46

1 2 3 4 5 6 7 8
 1 2 3 4

29
SATA HDD
CN9

1 1
2 SATA_TXP0 C483 0.01u/16V_4 SATA_TXP0_C 9
3 SATA_TXN0 C482 0.01u/16V_4 SATA_TXN0_C 9
A 4 A
5 SATA_RXN0_C C464 0.01u/16V_4
SATA_RXN0 9
6 SATA_RXP0_C C465 0.01u/16V_4
SATA_RXP0 9
7
8
9
10
11
12
120mil +5V_HDD R14 *short_8 +5V
13
14 C5 C12 C9 C3
15 +
*100u/6.3V_3528
16 10u/6.3V_6 *0.1u/16V_4 0.01u/25V_4
17
18
19 19

SATA_HDD

B B

SATA ODD Zero Power (ODD)

CN12 Q36
14 +15V +5V *ZD@AO6402A +5V_ODD +5V
GND14

GND1 1 6
2 SATA_TXP1 C590 0.01u/16V_4 SATA_TXP1_C 9 5 4 R366 0_8
RXP SATA_TXN1 C591 0.01u/16V_4
RXN 3 SATA_TXN1_C 9 2
4 +3VPCU 1 R346
GND2 SATA_RXN1_C C552 0.01u/16V_4
TXN 5 SATA_RXN1 9 *ZD@22_8
6 SATA_RXP1_C C553 0.01u/16V_4 R363
SATA_RXP1 9

3
TXP

1
C C

MOD_EN_5V
GND3 7 2 1
R349 *ZD@100K
ODD_PLUGIN# 7

3
*ZD@100K

3
8 ODD_PLUGIN# R408 *1K_4
DP +5V_ODD
9 +5V_ODD

2
+5V ODD_EN_Q 2
+5V 10

1
C484 C505 C516 C57 ODD_EN_Q 2
+

RSVD 11

3
12 9 FCH_ODD_EN R354 *0_4 C492 Q32
GND *100u/6.3V_3528 10u/6.3V_6 *0.1u/16V_4 0.01u/16V_4 Q37 *ZD@0.1u/25V_6 *ZD@DMN601K-7
13

2
GND *ZD@DMN601K-7

1
15 34 ODD_EN R358 *ZD@0_4 2

1
GND15

1
C18534-11305-L Q30
*ZD@DMN601K-7
R44 *Short_4 R345
ODD_EJ_EC 34

1
*100K_4
R42 *0_4
ODD_EJ 7

2
R43 10K_4 +3V

D D

Quanta Computer Inc.

PROJECT : ZRP
Size Document Number Rev
SATA(HDD/ODD) A1A

Date: Friday, July 20, 2012 Sheet 29 of 46

1 2 3 4
 5 4 3 2 1

30
FILT_1.65V
Port Configuration
AUDIO CODEC C728
1u/16V_6
C724

0.1u/10V_4
Notes:
3V_DVDD Port A: Headphone jack (jack shared with S/PDIF)
ADOGND AVDD_3.3 pin is output of
LDO_OUT_3.3V Port B: Internal MIC (mono or stereo)
internal LDO. Do NOT connect
to external supply.
Port C: Microphone/LI/LO jack
C701 C706 C721
C737 C722
Port D: Line Out jack (Optional)
10u/10V_8 0.1u/10V_4 0.1u/10V_4 Port E: Line In jack (Optional)
10u/10V_8 0.1u/10V_4 Port F: Not used.
D D
Port G: Internal stereo speakers
3V_DVDD
Port J: Internal stereo digital mic (Optional)
ADOGND Layout Note: Path from +5V to LPWR_5.0 and
(3.3V or 1.5V) RPWR_5.0 must be very low resistance ( <0.01 ohms).
Port H: S/PDIF (jack shared with headphone)

C670 Place bypass caps very close to device.

C668
1u/16V_6 0.1u/10V_4 3V_DVDD

C662 C678
+5VA
HEADPHONE/Mic combo
10u/10V_8 0.1u/10V_4
FILT_1.8V C699 C685 C695 C730 C694 C738 C687
MIC1_JD
C660 C677 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 *10u/10V_8 *10u/10V_8 10u/10V_8

3
10u/10V_8 0.1u/10V_4

Q44
R628 33K/F_4

21
29

32

30

31

15

18

20
2

4
9
U31 3V_DVDD DMG1012T
C673 *22p/50V_4

VDD_IO

AVDD_5V
AVDD_HP

FILT_1.65
FILT_1.8

VAUX_3.3

DVDD_3.3

AVDD_3.3

LPWR_5.0

RPWR_5.0

CLASSDREF
ADOGND R268 4.7K/F_4
R553 R533 C766

1
11 5.1K/F_4 5.1K/F_4 1u/10V_4
7 ACZ_RESET#_AUDIO RESET# MIC1-VREFO R272 2K/F_4 HPOUT_JD
C671 *33P/50V_4
R507 *Short_4 7 44 SENSEA R544 39.2K/F_4 HPOUT_JD ADOGND
7 ACZ_BITCLK_AUDIO BIT_CLK SENSE_A
10 43 SENSEB R540 20K/F_4 MIC1_JD MIC1-R 2.2u/6.3V_6 C424 MIC2_MIC
C 7 ACZ_SYNC_AUDIO SYNC SENSE_B C
7 ACZ_SDIN0 R506 33_4 8 R547 *10K/F_4
SDATA_IN
7 ACZ_SDOUT_AUDIO 6 SDATA_OUT PORTF_R 42
41 MIC1-L 2.2u/6.3V_6 C418 R273 100/F_4 COMBO_MIC
C663 *22p/50V_4 PORTF_L
40 MIC1-R
PORTB_R

1
39 MIC1-L
PORTB_L MIC1-VREFO D27
D24 38
R504 *Short_4 B_BIAS *14V/38V/100P_4
7 SPKR
PCBEEP_C C679 0.1u/10V_4 PCBEEP_R 13 37 MIC2-VREFO R582 2.2K_4 20120418 change

2
R539 *Short_4 PC_BEEP C_BIAS
36 MIC2_R C726 2.2u/6.3V_6 footprint / PN
34 PCBEEP_EC PORTC_R
48 35 MIC2_L C735 2.2u/6.3V_6 MIC2_INTL1
BAT54C C650 SPDIF PORTC_L
R505
ADOGND Normal Open Jack
47 GPIO0/EAPD#
CX20584-21Z PORTE_R 34
*100p/50V_4 SPK_MUTE# 46 33 CN21
10K_4 GPIO1/SPK_MUTE# PORTE_L
45 GPIO2/SPDIF2 3
PORTD_R 28 6
27 HP-L R603 39.2/F_4 HP-L-1 R596 *short_6 HPL_SYS 1
ACZ_BITCLK_AUDIO PORTD_L
1 26 HP-R HP-R R260 39.2/F_4 HP-R-1 R259 *short_6 HPR_SYS 2
DMIC_3/4 PORTA_R HP-L
2 DMIC_CLK0 PORTA_L 25 4
3 HPOUT_JD 5
DMIC_1/2 AVEE UNIVERSAL JACK

1
C794 AVEE 24
23 010030FR006G119ZR
FLY_N

1
*33P/50V_4
EXT_MUTE#

22 C714 1u/16V_6
FLY_P D26 D9 D25

EP_GND
RIGHT+
C720 C731 *14V/38V/100P_4 *14V/38V/100P_4 *14V/38V/100P_4

2
RIGHT-
LEFT+

LEFT-

2
0.1u/10V_4 10u/10V_8
reserve for EMI
Internal Speaker ADOGND ADOGND
12

14

16

17

19

49
ADOGND

B 3V_DVDD +3V 40mil for each signal B

0.1A L58
34 AMP_MUTE# CN20 +5V
1 2
R_SPK+ BLM18AG601SN1D L16 R_SPK+_1 4 R+
C712

C723

C729

EMI-FILTER-CHIP-HCB2012KF220T60(22-6A) Low Active R_SPK- BLM18AG601SN1D L18 R_SPK-_1 3

L_SPK- BLM18AG601SN1D L22 L_SPK-_1 R- 5 C457
2 L- 6
SPK_MUTE# R518 *0_4 L_SPK+ BLM18AG601SN1D L25 L_SPK+_1 1 L+ 0.1u/25V_4
1u/10V_4
10u/10V_8

0.1u/10V_4

C774 C775 C776 C777 SPEAKER-CONN

1000p/50V_4 1000p/50V_4 1000p/50V_4 1000p/50V_4
change Part Number to IC OTHER(48P) CX20584-21Z(QFN)(AL020584001) 01/05 For layout issues
change L48,L47,L35,L34 to CX08T601000 for EMI
02/15 REV:B
1. The VDD_IO and VAUX_3.3 pins should be connected to same
power supply domain as HDA bus controller so that the HDA controller
and codec bus interface will power-up at the same time. This will avoid

Power (ADO) 2012-05-23 Add short pad

for vendor suggestion.
INT DIP AMIC array bus leakage issues if using HDA controller with bus pull-up strap
options. See other FET option on this page if these supplies are not on
same domain as HDA controler.
R235 *SHORT_8 CN1
+5V DIGITAL ANALOG +5VA R236 *SHORT_8 1 MIC2_INTL1 2. To support Wake-on-Jack, the codec VAUX_3.3 pin must be
1
2 2 powered from a Standby supply.

1
L42 EMI-FILTER-CHIP-HCB2012KF220T60(22-6A) C487
R567 *0_6 DIP_MIC
R588 *0_4 D22 *22p/50V_4 3. C309, C310, C311 are optional.
R616 *0_4 ADOGND TVS/6pF_4 Do not install unless needed for EMI/SI.

2
R629 *0_4
A A
R269 *0_4 ADOGND
R274 *0_4 ADOGND
R569 *0_4
C702 *1000p/50V_4
C740 *1000p/50V_4
C490 *0.1u/10V_4

2012-05-23 delete G923-330T1UF ADOGND

relatived sch & parts. Quanta Computer Inc.
Tied at one point only under ADOGND
PROJECT : ZRP
the codec or near the codec
cap place close to MIC-connector Size Document Number Rev
CONEXANT 20584 1A

Date: Friday, July 20, 2012 Sheet 30 of 46

5 4 3 2 1
 5 4 3 2 1

USB3.0/2.0
20120712
+5V_S5 -> +5VPCU for battery
mode can charger when enter S4/S5
+5VPCU

C94 1u/6.3V_4
2012-06-15
Active High:
1st: AL007534001 (Promate)
2nd: AL000547006 (GMT)
3rd: AL002511002 (DDS)
+3V_S5 R89
30 mils

*short_6
+USB_RE_PWR

C206 C585 C560 C543 C579

31
* * * * *
U8
2 8 USBPWR1
IN1 OUT3
3 IN2 OUT2 7
6 C87
OUT1

1
USB_BC_EN 4
D EN C88 1000p/50V_4 +USB_RE_PWR D
1 GND
OC# 5
100u/6.3V_3528

2
UP7534ARA8-15
7 OC_0#
R126 R109 R129 R128 R133 R134
*RD@4.7K_4 *RD@4.7K_4 *RD@4.7K_4 *RD@4.7K_4 *RD@4.7K_4 *RD@4.7K_4

EQ_A EQ_B DE_A DE_B OSA OSB

C127 15p/50V_4 R125 300_4

R424 R420 R431 R428 R435 R440
USBP10-_C R426 *short_4 USB 3.0 Connector * * *RD@4.7K_4 *RD@4.7K_4 *RD@4.7K_4 *RD@4.7K_4
USBP10+_C R433 *short_4
CN13
USB3.0_CONN
1 1 VBUS
USBP10-_R 2 2 D-
USBP10+_R 3 +USB_RE_PWR R135 *RD@4.7K_4
3 D+
4 4
USB3_RXN0_RE R447 *short_4 USB3_RXN0_R GND R443 *RD@4.7K_4
5 5 SSRX-
USB3_RXP0_RE R441 *short_4 USB3_RXP0_R 6 6 SSRX+
7 7
USB3_TXN0_R GND +USB_RE_PWR
8

EQ_A
DE_A
8 SSTX-

OSA
USB3_TXP0_R 9 9 SSTX+

13
12
11
10
13
12
11
10
C USB3_TXN0_RE R421 *short_4 C

6
5
4
3
2
1
USB3_TXP0_RE R417 *short_4 U24

NC
RXD_EN
NC

EQ_A
DE_A

VDD
7 NC HGND 25
7 USB3_TXN0 C581 * USB3_TXN0_C 8 24
USBP10-_R RV4 1 RXA- NC
2 *EGA_4 7 USB3_TXP0 C582 * USB3_TXP0_C 9 RXA+ TXA- 23 USB3_TXN0_RE_C C548 * USB3_TXN0_NRD_C
SP : 1. Re-Driver stuff 0 ohm(CS00002JB38) 10 EN_A# TXA+ 22 USB3_TXP0_RE_C C549 * USB3_TXP0_NRD_C
2. No Re-Driver stuff 0.1u(CH4102K1B03) USBP10+_R RV5 1 2 *EGA_4 7 USB3_RXN0 C583 * USB3_RXN0_C 11 21
C584 * USB3_RXP0_C TXB- EN_B# USB3_RXN0_RE
7 USB3_RXP0 12 TXB+ RXB- 20
USB3_RXN0_R RV7 1 2 *EGA_4 19 USB3_RXP0_RE
RXB+

EQ_B
DE_B
VDD
USB3_RXP0_R RV6 1 2 *EGA_4

NC
NC

NC
USB3_TXN0_NRD_C C558 SP@0.1u/10V_4 USB3_TXN0_RE
USB3_TXP0_NRD_C C551 SP@0.1u/10V_4 USB3_TXP0_RE *

13
14
15
16
17
18
USB3_TXN0_R RV3 1 2 *EGA_4

USB3_TXP0_R RV2 1 2 *EGA_4

EQ_B
DE_B
OSB
+USB_RE_PWR R138 *RD@4.7K_4

R445 *

USB Charger to 3.0

USB3_TXN0 R145 NRD@0_4 USB3_TXN0_NRD R97 NRD@0_4 USB3_TXN0_NRD_C
USB3_TXP0 R144 NRD@0_4 USB3_TXP0_NRD R96 NRD@0_4 USB3_TXP0_NRD_C
CB SELCDP Funcion
USB3_RXN0 R143 NRD@0_4 USB3_RXN0_NRD R414 NRD@0_4 USB3_RXN0_RE
0 X DCP autodetect with mouse/keyboard wakeup USB3_RXP0 R142 NRD@0_4 USB3_RXP0_NRD R415 NRD@0_4 USB3_RXP0_RE
B B

1 0 S0 charging with SDP only

1 1 S0 charging with CDP or SDP only (depending on external device)

EXT. USB(USB) Active Low:

1st: AL007534000 (Promate)
U11 R103 * 2nd: AL000547005 (GMT)
USB_CHARGE_ON 34
BC_CEN 1 8 R111 *CH@0_4 MAINON 7,34,36,38,43
3rd: AL002501000 (DDS)
USBP10-_C CEN CB1
2 DM TDM 7 USBP10- 7
USBP10+_C 3 6 +5V_S5
DP TDP USBP10+ 7
4 5 C172 * U16 CN16
SELCDP VDD USBP0
Thermal Pad 9 2 IN1 OUT3 8 1

1
3 IN2 OUT2 7 2
* 6 C640 C644 C332 3
OUT1
34 USBON# 4 EN# 4
R137 * +5VPCU 1 470p/50V_4 0.1u/10V_4 *100u/6.3V_3528 5

2
GND USBP0+_R
OC# 5 6
C324 USBP0-_R 7
R425 NCH@0_4 1u/6.3V_4 UP7534BRA8-15 8
R432 NCH@0_4 USBP3+_R 9
USBP3-_R 10 13
7 OC_1# 11 14
12

R499 *short_4 USB_CONN

7 USBP0+
R508 *short_4
+3VPCU 7 USBP0-
CEN:SLG55584A----pull up
A SLG55584----pull low A
R515 *short_4
7 USBP3+
R61 * C66 *CH@0.1u/10V_4 R522 *short_4
7 USBP3-
5

BC_CEN 2
4 USB_BC_EN
34 USB_BC_ON
USB_BC_ON 1 Quanta Computer Inc.
U6
PROJECT : ZRP
3

*
Size Document Number Rev
R64 NCH@0_4
INT&EXT USB A1A

Date: Friday, July 20, 2012 Sheet 31 of 46

5 4 3 2 1
 5 4 3 2 1

POWER M/B (DCD)

32
LAN& Charger DB LED(UIF)

Power
CN10
+3V_S5 +3V_S5 +3VPCU +3V_S5 R295 1M_4
D 1 PCIE_REQ_LAN# D
2 R294 1M_4
+3VPCU 3
8,14,24,28,34 PCIE_RST# 4 C791 C792
+3V_S5
7 PCIE_WAKE# 5 C793
7 PCIE_REQ_LAN# 0.1u/10V_4 0.1u/10V_4 LED1
6 100p/50V_4 R300 422/F_4
7 34 PWRLED# 2 3
3 PCIE_RXN1_LAN 8 VIN
R301 590/F_4 1
3 PCIE_RXP1_LAN 9 CN4 34 SUSLED#
10 LED_AMBER/BLUE
6
3 PCIE_TXN1_LAN 11 Place near CN10 For EMI 5
3 PCIE_TXP1_LAN 12
4
13
8 CLK_PCIE_LANN 3
14
8 CLK_PCIE_LANP 2
15
16
1 Battery
34 ACIN 17 Power_conn
34 ICM 18
+3VPCU R297 1M_4
34 TEMP_MBAT 19
34 D/C# 20 R296 1M_4
7,34 MBCLK 21
7,34 MBDATA 22
PWRLED# +3VPCU
23 25
34 NBSWON# LED2
24 26 R302 422/F_4
C 34 BATLED0# 2 3 C
LAN_CONN
R303 590/F_4 1
34 BATLED1#
LED_AMBER/BLUE

HOLE(OTH)
EE RETURN-PATH CAPACITORS(EMC)

HOLE13 HOLE8 HOLE11 HOLE5

HOLE10 HOLE9 FBAJ2003010 HOLE6 FBAJ2003010 FBAJ2003010 MBUL1003010
*h-c118d118n *h-o157x118d157x118n h-tc236bc142d142p2 *INTEL-CPU-BKT2 h-tc217bc142d142p2 h-tc217bc142d142p2 h-tc236bc122d122p2
1 3
B B
2 4
1

1
HOLE18 HOLE17
FBAJ2003010 FBAJ2003010 HOLE16 HOLE7 HOLE1 HOLE2 HOLE14
*h-tc276bc142d142p2 *h-tc276bc142d142p2 *hg-c276d118p2 *hg-c276d118p2 *hg-c276d118p2 *hg-c276d118p2 *hg-c276d118p2
7 6 7 6 7 6 7 6 7 6
8 5 8 5 8 5 8 5 8 5
9 4 9 4 9 4 9 4 9 4
1

1
2
3

1
2
3

1
2
3

1
2
3

1
2
3
HOLE3 HOLE12 HOLE15 HOLE4
*hg-c276d118p2 *hg-c276d118p2 *hg-c276d118p2 *hg-c276d118p2
7 6 7 6 7 6 7 6
A 8 5 8 5 8 5 8 5 A
9 4 9 4 9 4 9 4

Quanta Computer Inc.

1
2
3

1
2
3

1
2
3

1
2
3

PROJECT : ZRP
Size Document Number Rev
LAN DB/ LED/ EMI/ Hole A1A

Date: Friday, July 20, 2012 Sheet 32 of 46

5 4 3 2 1
 5 4 3 2 1

33
K/B(KBC) MY17
TOUCHPAD BOARD CONN(TPD)
7 8
5 6 MY16
CN7 3 4 MX2
MX7 26 1 2 MX3 +3V
34 MX7
MX6 25 28 CP1 *100p/50Vx4
34 MX6
MX5 24 27 7 8 MX4
34 MX5
MX4 23 5 6 MX5
34 MX4
MX3 22 3 4 MX6
34 MX3
D MX2 21 1 2 MX7 R276 R256 D
34 MX2
MX1 20 CP2 *100p/50Vx4 Q21 2.2K_4 2.2K_4
34 MX1
MX0 19 7 8 MY0 5
34 MX0
MY17 18 5 6 MY1
34 MY17
MY16 17 3 4 MY2 3 4 SDATA1_TP
34 MY16 +3VPCU 7 SDATA1
MY15 16 1 2 MY3
34 MY15
MY14 15 CP3 *100p/50Vx4
34 MY14
MY13 14 7 8 MY4 2
34 MY13
MY12 13 RP4 10K_10P8R 5 6 MY5
34 MY12
MY11 12 10 1 MX3 3 4 MY6 6 1 SCLK1_TP
34 MY11 7 SCLK1
MY10 11 MX6 9 2 MX2 1 2 MY7
34 MY10
MY9 10 MX7 8 3 MX1 CP4 *100p/50Vx4
34 MY9
MY8 9 MX5 7 4 MX0 7 8 MY8 2N7002DW
34 MY8
MY7 8 MX4 6 5 5 6 MY9
34 MY7
MY6 7 3 4 MY10
34 MY6
MY5 6 1 2 MY11 R258 *0_4
34 MY5
MY4 5 CP5 *100p/50Vx4
34 MY4
MY3 4 7 8 MY12 R267 *0_4
34 MY3
MY2 3 5 6 MY13
34 MY2
MY1 2 3 4 MY14
34 MY1
MY0 1 1 2 MY15
34 MY0
CP6 *100p/50Vx4
KB_CONN C20 *100p/50V_4 MX1
C C19 *100p/50V_4 MX0 +3V C

+3V R255 0_4 L39 0_6

+5V +5V L38 *0_6
KB_BL LED +5V R250 *0_4
+5V
C478 *KBL@2.2u/10V_6
R252 R253 C366
1

R329 0.1u/10V_4 50mil

10K_4 10K_4 CN19
KBL@10K_4 Q29
2 KBL@AO3413 +TPVDD 1
L41 *short_6 TPCLK_R 2
34 TPCLK
L40 *short_6 TPDATA_R 3
34 TPDATA
3

4
CN8 SDATA1_TP 5
3

2 +5V_KB R324 *short_4 +5V_KB_R C371 C372 SCLK1_TP 6

34 KB_BL_LED 4 *0.01u/16V_4 *0.01u/16V_4 7 9
3 6 7 SMBALERT#
Q26 C466 C469 8 10
2 5 9 BOARD_ID2
KBL@DTC144EUA
1

KBL@4.7u/6.3V_6 KBL@0.01u/25V_4 1
KBL@KB_backlight TP_CN
LOW=ELAN
HIGH=SYNAPTICS

B B

If need to support XT(25) GPU, need check with thermal +3V

CPU FAN(THM)
R213

+3V
+5V FAN2(SECOND) *10K_4

FAN1(CPU/GPU) R16
34 FANSIG2
C346 *0.01u/16V_4
+5V 10K_4
U17 30 MIL CN18
C352 *2.2u/6.3V_6 2 3 TH_FAN_POWER2
34 FANSIG1 VIN VO 1
GND 5 2
C17 *0.01u/16V_4 SML1ALERT# 1 6
FON# GND 3
U1 30 MIL CN5 4
GND 7
8
C360 C347
*FAN_CONN.
C6 2.2u/6.3V_6 TH_FAN_POWER1 34 CPUFAN#_DAC2 VSET GND *22u/6.3V_8 *1000p/50V_4
2 VIN VO 3 1
5 *LR18115G
GND 2
5,34 SML1ALERT# 1 FON# GND 6 3
7 C11 C16
A GND A
4 8 FAN_CONN.
34 CPUFAN#_DAC1 VSET GND *22u/6.3V_8 1000p/50V_4
LR18115G
Quanta Computer Inc.
PROJECT : ZRP
Size Document Number Rev
KB/TP/FAN A1A

Date: Friday, July 20, 2012 Sheet 33 of 46

5 4 3 2 1
 5 4 3 2 1

34
EC(KBC) L23 PBY160808T-250Y-N/3A/25ohm_6 +A3VPCU

C196 C202
+3V SM BUS PU(KBC)
30mil
0.1u/10V_4 10u/6.3V_6

+3VPCU E775AGND
R403 2.2_6 R107 C142 C159
1 2 +3VPCU_EC 0.03A(30mils) *short_6
4.7u/6.3V_6 0.1u/10V_4
C531 C562 C546 C529 C495 C532 +3VPCU

115

102
19
46
76
88

4
4.7u/6.3V_6 0.1u/10V_4 *0.1u/16V_4 0.1u/10V_4 39p/50V_4 0.1u/10V_4 U7
S5_ON R393 10K_4

VCC1
VCC2
VCC3
VCC4
VCC5

AVCC

VDD
E775AGND C201 10u/6.3V_6 ICM
D D
C195 0.01u/16V_4 MBCLK R392 4.7K_4
3 97 MBDATA R373 4.7K_4
8,28 LPC_LFRAME# LFRAME GPIO90/AD0 TEMP_MBAT 32
8,28 LPC_LAD0 126 LAD0 GPIO91/AD1 98 PCIE_WAKE#_WLAN 28
8,28 LPC_LAD1 127 LAD1 A/D GPIO92/AD2 99 TP27
ICM
8,28 LPC_LAD2 128 LAD2 GPIO93/AD3 100 ICM 32
8,28 LPC_LAD3 1 LAD3
8 CLK_PCI_EC 2 LCLK
CLK_PCI_EC 101 +3V_S5
GPIO94/DA0 CPUFAN#_DAC2 33
8 CLKRUN# 8 GPIO11/CLKRUN D/A GPI95/DA1 105
R139 *
CPUFAN#_DAC1 33
APU_SIC_EC R394 1K_4
GPI96/DA2 106 EC_WLAN_WAKE# 7
121 APU_SID_EC R396 1K_4
7 SIO_A20GATE GPIO85/GA20
R136
7 SIO_RCIN# 122 KBRST/GPIO86
*22_4 64
GPIO01/TB2 ACIN 32
29 LPC 79 BC_EN TP6
7 SIO_EXT_SCI# ECSCI/GPIO54 GPIO02
95 NBSWON#_R R127 *Short_4 +3V_GFX
GPIO03 NBSWON# 32
25 EC_FPBACK# 6 GPIO24/LDRQ GPIO04 96 TP7
C191 108 GPUT_CLK R438 *
GPIO05 IOAC_RST# 28
*10p/50V_4 124 93 GPUT_DATA R439 *
30 AMP_MUTE# GPIO10/LPCPD GPIO06/IOX_DOUT/RTS1 LID591# 25
94 GPU_ID
GPIO07
8,27,28 PLTRST# 7 LREST GPIO16 114 KB_BL_LED 33
GPIO30 109 +1.1V_DUAL_EN 37
EMI reserve 28 RF_EN 123 GPIO67/PWUREQ GPIO36/CTS1 15 TP23
80 VRON TP22
GPIO41 HWPG
8 IRQ_SERIRQ 125 SERIRQ GPIO42/SCL3B/TCK 17
GPIO43/SDA3B/TMS 20 SML1ALERT# 5,33
7 SIO_EXT_SMI# 9 GPIO65/SMI GPIO44/TDI 21 SUSB# 7
GPIO GPO47/SCL4 24 TP5
GPIO50/PSCLK3/TDO 25 D/C# 32
33 MX0 54 KBSIN0 GPIO51 26 S5_ON 35,43
33 MX1 55 KBSIN1 GPIO52/PSDAT3/RDY 27 HDMI_HPD_EC# 26
33 MX2 56 KBSIN2 GPIO53/SDA4 28 TP4
C 33 MX3 57 KBSIN3 GPIO70 73 SUSC# 7 C
33 MX4 58 KBSIN4 GPIO71 74 PWROK_EC 11
33 MX5 59 KBSIN5 GPIO72 75 PCH_RSMRST# 7 H_PROCHOT# 5,8
33 MX6 60 KBSIN6 GPIO75/SPI_SCK 82 MAINON 7,31,36,38,43

3
61 83 PCIE_RST#_EC R407 *AC@0_4
33 MX7 KBSIN7 GPO76/SHBM PCIE_RST# 8,14,24,28,32
84 Q42
GPIO77 ODD_EJ_EC 29
33 MY0 53 KBSOUT0/JENK GPIO81 91 DNBSWON# 7
52 110 TP26 PROCHOT_EC 2
33 MY1 KBSOUT1/TCK GPO82/IOX_LDSH/TEST
33 MY2 51 KBSOUT2/TMS GPO84/IOX_SCLK/XORTR 112 USBON# 31
33 MY3 50 KBSOUT3/TDI GPIO97 107 USB_CHARGE_ON 31
49 KB R422 2N7002K
33 MY4 KBSOUT4/JEN0
33 MY5 48

1
KBSOUT5/TDO 100K_4
33 MY6 47 KBSOUT6/RDY GPIO56/TA1 31 FANSIG2 33
33 MY7 43 KBSOUT7 GPIO20/TA2/IOX_DIN_DIO 117 SUSON 36
33 MY8 42 KBSOUT8 GPIO14/TB1 63 FANSIG1 33
33 MY9 41 KBSOUT9/SDP_VIS
33 MY10 40 KBSOUT10/P80_CLK TIMER GPIO15/A_PWM 32 CONTRAST 25
33 MY11 39 KBSOUT11/P80_DAT GPIO21/B_PWM 118 PCBEEP_EC 30
33 MY12 38 KBSOUT12/GPIO64 GPIO13/C_PWM 62 PWRLED# 32
33 MY13 37 KBSOUT13/GPIO63 GPIO32/D_PWM 65 BATLED0# 32
33 MY14 36 KBSOUT14/GPIO62 GPIO45/E_PWM 22 TP21
35 16 SUSLED#
33 MY15 KBSOUT15/GPIO61/XOR_OUT GPIO40/F_PWM/RI1 SUSLED# 32
33 MY16 34 GPIO60/KBSOUT16 GPIO66/G_PWM 81 WLAN_OFF 28
33 66 +3V_S5
33 MY17 GPIO57/KBSOUT17 GPIO33/H_PWM/SOUT1 BATLED1# 32
PCH_RSMRST# R401 *8.2K_4
MBCLK 70
7,32 MBCLK GPIO17/SCL1
MBDATA 69
7,32 MBDATA GPIO22/SDA1
5 APU_SIC_EC APU_SIC_EC 67 SMB 113
GPIO73/SCL2 GPIO87/CIRRXM/SIN_CR USB_BC_ON 31
5 APU_SID_EC APU_SID_EC 68 14 +3VPCU
GPIO74/SDA2 GPIO34/SIN1/CIRRXL +1.1V_EN 37
GPUT_CLK 119 IR 23
15 GPUT_CLK GPIO23/SCL3 GPIO46/CIRRXM/TRST IOAC_LANPWR# 28
GPUT_DATA 120 111 PROCHOT_EC GPU_ID R120 *
15 GPUT_DATA GPIO31/SDA3 GPO83/SOUT_CR/TRIST
R409 *short_4 GPU_ID : H = Mars
SPI_SDI 9
B 72 86 SPI_SDI_UR R411 100K/F_4 B
33 TPCLK GPIO37/PSCLK1 F_SDI/F_SDIO1 SPI_SDO_UR_R R90 33_4
L = Thames
33 TPDATA 71 GPIO35/PSDAT1 F_SDO/F_SDIO0 87 SPI_SDO 9
10 PS/2 FIU 90 SPI_CS0#_UR R98 33_4
TP25 GPIO26/PSCLK2 F_CS0 SPI_CS 9
11 92 SPI_SCK_UR_R R106 33_4
28 BT_POWERON# GPIO27PSDAT2 F_SCK SPI_SCK 9

29 ODD_EN 77 GPIO00/32KCLKIN GPIO55/CLKOUT/IOX_DIN_DIO 30 TP3

+3V
VCC_POR 85 VCC_POR# R81 47K/F_4 +3VPCU HWPG(KBC)
12
VCORF

VTT
AGND
GND1
GND2
GND3
GND4
GND5
GND6

13 104 +A3VPCU R108

TP24 PECI VREF

NPCE885LA0DX 10K_4
5
18
45
78
89
116

103

VCORF_uR 44

D6 *BAS316 HWPG
36 HWPG_1.5V
SM BUS ARRANGEMENT TABLE D8 BAS316
38 HWPG_1.2V
L24 PBY160808T-250Y-N/3A/25ohm_6 SM Bus 1 Battery, FCH D7 *BAS316
37 HWPG_1.1V_DUAL
C521 D5 *BAS316
35 SYS_HWPG
SM Bus 2 APU
1u/6.3V_4
E775AGND
SM Bus 3 GPU

Placement for EC of VIN power plan

A VIN A

C479 C528 C523 C535

0.1u/25V_4 0.1u/25V_4 0.1u/25V_4 0.1u/25V_4

Quanta Computer Inc.

PROJECT : ZRP
Size Document Number Rev
A1A
NPCE885/FLASH
Date: Saturday, July 21, 2012 Sheet 34 of 46
5 4 3 2 1
 5 4 3 2 1

MAIND
MAIND 36,43
SYS_SHDN#
SYS_SHDN# 5,15,40,43

Ven=7.23V
35
34 SYS_HWPG VIN VIN VL 8223REF VL
+3VPCU

D VIN VIN D

PR143

10u/6.3V_8
4.7u/6.3V_6
PR127 10_8
665K/F_4

1
+ PR111
PC65 *0_4

8223_VIN

PC84
8223_EN
2 PC44 PC82 PC76 PC79 1u/6.3V_4 PC94 PC89

PC71
100u/25V_6X5.8 4.7u/25V_8 2200p/50V_6 PR119 0.1u/25V_4 2200p/50V_6 4.7u/25V_8
*short_4
+5VPCU PR110 PR100
+5VPCU
5 Volt +/- 5% PR116 PR126 PR128 *0_4 *short_4

5
*100K/F_4 330K/F_4 *short_4 +3VPCU
+3VPCU

5
TDC : 6.25A

16

17
8

3
PEAK : 8.3A
PQ30
MDV1528
3.3 Volt +/- 5%

VIN

VREG3

VREG5

REF
OCP : 10A PQ27 SYS_SHDN# +3V_SKIP
4 TDC : 4.2A
4 13 EN SKIPSEL 14
Width : 250mil
MDV1528 PEAK : 5.6A
+3V_PG 23 4 +3V_TON
OCP : 6.8A

3
2
1
PGOOD TONSEL PC70

1
2
3
+5V_DH 21 10 +3V_DH 0.1u/50V_6
UGATE1 UGATE2 Width : 180mil
PL4 PC68 PR122 +5V_B 22 9 +3V_B PR123 PL5
2.2uH_7X7X3 0.1u/50V_6 1/F_6 BOOT1 PU6 BOOT2 1/F_6 2.2uH_7X7X3
+5V_LX 20 RT8223P 11 +3V_LX
PHASE1 PHASE2
+5V_DL 19 12 +3V_DL
LGATE1 LGATE2

5
C PR104 24 7 C

ENTRIP1

ENTRIP2
15.4K/F_4 VOUT1 OUT2 PR106
PQ28 +5V_FB 2 5 +3V_FB PR125 6.81K/F_4

GND

GND
ENC
+ PR124 MDV1595S FB1 FB2 *4.7_6 +
4
*4.7_6 4
PC46 PC57 PC60 PC52

18

25

15
330u/6.3V_6X5.7 0.1u/50V_6 1 PR129 0.1u/50V_6 330u/6.3V_6X5.7
2
3
*short_4 PQ31 PC80

3
2
1
8223_EN MDV1595S *680p/50V_6
PR107 PC78

2
10K/F_4 *680p/50V_6
PR140 PC81 PR108
100K/F_4 0.1u/10V_4 10K/F_4

1
PR109
PR112 82.5K/F_4
124K/F_4

OCP:8A
PC96 L(ripple current)
2 0.1u/50V_6
OCP:10A PD2
3
+3V_DL =(9-3.3)*3.3/(2.2u*0.5M*9)
L(ripple current) 1PS302
PR145
~1.9A
=(9-5)*5/(2.2u*0.4M*9) 1 *short_6 PR101
PC101 *short_6
Iocp=6.8-(1.9/2)=5.85A
B =2.525A 0.1u/50V_6 Vth=5.85A*14mOhm=81.9mV B
2
Iocp=10-(2.525/2)=8.74A PD3
R(Ilim)=(81.9mV*10)/10uA
Vth=8.74A*14mOhm=122.32mV 1PS302 3 ~81.9K
PC120
R(Ilim)=(122.3mV*10)/10uA 1 0.1u/50V_6
~122.3K
+15V_ALWP
+15V
PR189
22_8
PC119
0.1u/50V_6

VIN +3V_S5 +5V_S5 +15V VIN +5VPCU +5VPCU +3VPCU

+3VPCU

PR59 PR63 PR62 PR61 PR60

5

5
1M_6 22_8 22_8 1M_6 *1M_6

3
S5D 4 MAIND 4 MAIND 4 S5D 2
A PQ23 PQ24 PQ33 A
3

MDV1528Q MDV1528Q MDV1528Q

PQ25
3
2
1

3
2
1

3
2
1

2 AO3404
34,43 S5_ON

1
2 2 2
+5V_S5 +5V +3V +3V_S5
PR58 PQ15 PQ14 PQ13
Quanta Computer Inc.
1

PQ16 1M_6 2N7002K 2N7002K 2N7002K

DTC144EU PC25
TDC : 2.25A TDC : 4A TDC : 2A TDC : 0.64A
1

*2.2n/50V_4
PEAK : 3A PEAK : 5.4A PEAK : 2.7A PEAK : 0.85A
PROJECT : ZRP
Size Document Number Rev
Width : 100mil Width : 160mil Width : 80mil Width : 40mil SYSTEM 5V/3V (RT8223P) A1A

Date: Friday, July 20, 2012 Sheet 35 of 46

5 4 3 2 1
 5 4 3 2 1

TDC : 0.75A
PEAK : 1A
Width : 40mil
+0.75V_DDR_VTT

36
PC133 PC131
10u/6.3V_8 10u/6.3V_8
D TDC : 0.38A D
+SMDDR_VREF
PEAK : 0.5A
Width : 20mil
Close to IC
Greater than or equal 40mil
PC141
0.22u/10V_4
+5V_S5

+3V

PC99 PC127

22

21
10u/6.3V_8 1u/10V_4

2
PR155
VIN
100K/F_4

VTTSNS
PAD

PAD

VTTREF

VTTGND

VTT

VLDOIN
+1.5VSUS
1.5 Volt +/- 5%

5
34 HWPG_1.5V 20 PGOOD V5IN 12
C
PC98
4.7u/25V_8
TDC : 11A C

7,31,34,38,43 MAINON
PR152 51216_S3 17 S3 DRVH 14 51216_DRVH 4 PEAK : 14.6A
*short_4 PR165 PC117
2_6 0.1u/50V_6 PC95 PC97 OCP : 18A

1
2
3
PR153 51216_S5 16 15 51216_VBST PQ35 2200p/50V_4 4.7u/25V_8
34 SUSON
*short_4 S5 PU9 VBST RJK03J6DPA Width : 440mil
TPS51216RUKR
PR163 51216_MODE 19 13 51216_SW +1.5VSUS
200K/F_4 MODE SW
PL10

5
PR164 51216_TRIP 18 11 51216_DRVL 0.68uH_7X7X3
53.6K/F_4 TRIP DRVL
VDDQSNS

PR210
26 10 4 *4.7_6
PAD PGND
REFIN

GND
PAD

PAD

PAD
REF

PQ44

1
2
3
RJK03K5DPA + PC108
VREF=1.8V PC144 PC115
6

25

24

23

7 *680p/50V_6 0.1u/50V_6 330u/2V_7343

51216_REF
For customer ID change
51216_REFIN

PC146 PR219
B 0.1u/10V_4 *short_6 RDSon=4.3mohm B
51216_S3 PR159 51216_S5 0.1u MLCC close inductor side
*0_4
PR202
10K/F_4 Close to output cap
+1.5VSUS

SUSON PR137 100K_4

3
TDC : 0.375A
PR203
57.6K/F_4
PC142
0.01u/25V_4
Mode Frequency Discharge mode
MAIND 2
PEAK : 0.5A
35,43 MAIND
Width : 40mil
200K 400K Tracking Discharge
PQ42
AO3404

1
100K 300K Tracking Discharge
+1.5V

OCP=18A
A L ripple current S3 S5 +1.5VSUS REF VTT A
=(19-1.5)*1.5/(0.68u*400k*19)
=5.079A
S0 1 1 ON ON ON
Vtrip=18-(5.079/2)*4.3mohm Quanta Computer Inc.
=0.06647V
S3 (mainon off) 0 1 ON ON OFF PROJECT : ZRP
Rlimit=0.06647/10uA*8~53.183Kohm
Size Document Number Rev
S4/S5 0 0 OFF OFF OFF A1A
DDR 1.5V(TPS51216)
Date: Friday, July 20, 2012 Sheet 36 of 46
5 4 3 2 1
 5 4 3 2 1

37
D D

VIN

+5V_S5

+3V

PC145 PC140 PC151

1u/10V_4 2200p/50V_6 4.7u/25V_8

5
PR176
*100K/F_4

7
PQ46
MDV1528

V5IN
DUAL_DRVH 4
1 9 PC116 +1.1V_DUAL
34 HWPG_1.1V_DUAL PGOOD DRVH 0.1u/50V_6
PR172
PR167 *Short_4 DUAL_EN 3 10 DUAL_VBST *Short_4 PL9
34 +1.1V_DUAL_EN

3
2
1
EN VBST 2.2uH_7X7X3
DUAL_TRIP 2 PU11 8 DUAL_SW
C TRIP TPS51211DSCR SW C
PR171 60.4K/F_4
PR173 DUAL_TST 5 6 DUAL_DRVL
100K/F_4 PR211 464K/F_4 TST DRVL

5
12 GND GND 11
PR217 PR188

GND

GND

GND

GND
*4.7_6 5.76K/F_4
+1.1DUAL

FB
+ PC112
4 1.1 Volt +/- 5%

13

14

15

16

4
PC91 330u/2V_7343
DUAL_FB
PQ47 PC150
0.1u/50V_6 TDC : 3.86A

3
2
1
MDV1595S *680p/50V_6 PR201 For customer ID change PEAK : 5.2A
10K/F_4
OCP : 6.2A
Width : 160mil

OCP=5A
L ripple current
=(19-1.1)*1.1/(2.2u*290k*19) +5V_S5 +15V +1.1V_DUAL
B B
=1.624A
Vtrip=6.2-(1.624/2)*14mohm
=0.07542V

5
PR66 PR220
Rlimit=0.07542/10uA*8~60.34Kohm 10K/F_4 1M_4

4
PQ38
+1.1V

3
MDV1528Q
TDC : 3A

3
2
1
2 PEAK : 4A

3
PQ52
+1.1V Width : 120mil
2N7002K PC152
+3V PR68 *Short_4 2 *2200p/50V_4

1
PQ53
34 +1.1V_EN 2N7002K
1
PR67
A *0_4 A
PC27
*0.1u/10V_4

Quanta Computer Inc.

PROJECT : ZRP
Size Document Number Rev
+1.1V_DUAL(TPS51211) A1A

Date: Friday, July 20, 2012 Sheet 37 of 46

5 4 3 2 1
 5 4 3 2 1

38
VIN
D D
+5V_S5

+3V

PC121 PC137 PC128

1u/10V_4 2200p/50V_6 4.7u/25V_8

5
PR148
100K/F_4

7
PQ40
MDV1528

V5IN
51211V_DRVH 4
1 9 PC90
34 HWPG_1.2V PGOOD DRVH +1.2V
0.1u/50V_6
PR142
VDDA_PWRGD PR130 *Short_4 51211V_EN 3 10 51211V_VBST *Short_4 PL8

3
2
1
EN VBST 2.2uH_7X7X3
51211V_TRIP 2 PU7 8 51211V_SW
PR136 90.9K/F_4 TRIP TPS51211DSCR SW
PR144 51211V_TST 5 6 51211V_DRVL
*100K/F_4 PR174 464K/F_4 TST DRVL

5
C
12 GND GND 11
PR178 PR158 +1.2V C

GND

GND

GND

GND
*4.7_6 7.15K/F_4
1.2 Volt +/- 5%

FB
+
4 TDC : 5.6A

13

14

15

16

4
PC66
51211V_FB 0.1u/50V_6 PEAK : 7.5A
PQ41 PC129 PC67
OCP : 9A

3
2
1
MDV1595S *680p/50V_6 PR169 560u/2.5V_6X5.7
10K/F_4
Width : 240mil

OCP=9A
L ripple current
=(19-1.2)*1.05/(2.2u*290k*19)
=1.762A
B
Vtrip=9-(1.762/2)*14mohm B
=0.1136V
Rlimit=0.1136/10uA*8~90.9Kohm PR13
100K_4
PC1 +5VPCU
+3V
1u/16V_6 PU1
G9661-25ADJF12U
4 VPP PGOOD 1 VDDA_PWRGD 39
PR9 *Short_4 2 6 +2.5V
7,31,34,36,43 MAINON VEN VO
+3VPCU 3 VIN PR5 +2.5V
8 GND R1
ADJ
9 GND NC 5 73.2K/F_4
PC5
2.5 Volt +/- 5%
10u/6.3V_8 TDC : 0.6A
7

PR8
100K_4 PEAK : 0.75A
0.8V PR7 Width : 40mil
PC2 PC3 PC7
10u/6.3V_8 0.1u/50V_6 *0.1u/50V_6
R2 34K/F_4
A A

Vout =0.8(1+R1/R2)
=2.5V Quanta Computer Inc.
PROJECT : ZRP
Size Document Number Rev
+1.2V(TPS51211)/+2.5V A1A

Date: Friday, July 20, 2012 Sheet 38 of 46

5 4 3 2 1
 5 4 3 2 1

+VDDNB_CORE

PC138
330p/50V_4
39
PR64
PR65 10_4 Load line setting
*short_4 PR149
5 APU_VDDNB_RUN_FB_H 2.2/F_6 VIN
+5V_S5 BOOT_NB

2200p/50V_4
PR185 Close with

0.1u/50V_6

4.7u/25V_8

4.7u/25V_8

4.7u/25V_8
3.01K/F_4
PHASE_NB inductor

1
PC126

PC86

PC134

PC77

PC143
Close to the RC time PC93
0.22u/25V_6
D CPU side. PC139 PR208
constant D

2
100p/50V_4 499/F_4 VSUMG+ UGATE_NB 4

1
2
3
PR135

PR134
1/F_6
PC132 PR200 PR120 PQ39 PL6

47n/16V_4
0.15u/10V_4
680p/50V_4 2K/F_4 10K_6_NTC AON6414AL 0.36uH

*short_6
DCR=1.1mOhm

PC149

PC148
PHASE_NB 1 2 +VDDNB_CORE

PR216
11K/F_4

5
PR183 PC130 PR192

4
1u/10V_4

1u/10V_4

PR162
*0_4 150p/50V_4 267K/F_4
+

1000p/50V_6 2.2_6
PR121
2.61K/F_4 LGATE_NB 4
20120531

0.1u/10V_4

10u/6.3V_8
PC123 PR182

62771_VSEN_NB

PC26

PC45
47p/50V_4 768/F_4 PC48

1
2
3

PC100
62771_FB_NB VSUMG- PQ37 330u/2V_7343

62771_VDDP
62771_VDD
AON6780

PC88

PC87

ISUMN_NB
OCP
PC147
62771_COMP_NB 0.1u/10V_4

+3V
VSUMG+ PR218 3.65K/F_6

36

37

38

25

26

40

39
+VDDNB_CORE

COMP_NB

FB_NB

VSEN_NB

VDDP

ISUMP_NB

ISUMN_NB
VDD
PR204
10K/F_4 VSUMG- PR212 1/F_4
TDC : 25A
PR193
*short_4
PEAK : 33A
35 PGOOD_NB LGATE_NB 34 LGATE_NB OCP : 42A
Width : 1320mil
VRM_PWRGD 20 33 PHASE_NB
11 VRM_PWRGD PGOOD PHASE_NB Load Line = 4mV/A
3 32 UGATE_NB
APU_SVC SVC UGATE_NB
C C

TP30 CORE_PWM_PROCHOT# 4 31 BOOT_NB

VR_HOT_L BOOT_NB

APU_SVD 5 SVD BOOT2 30

+1.5VSUS PR205 *short_4 6 29

VDDIO UGATE2
PU8
PR195 *Short_4 7 ISL62771HRZ-T 28
APU_SVT SVT PHASE2

38 VDDA_PWRGD PR196 *Short_4 8 27

ENABLE LGATE2

9 24 LGATE_1
APU_PWRGD_SVID_REG PWROK LGATE1

NTC_NB 1 23 PHASE_1
NTC_NB PHASE1

NTC 11 22 UGATE_1
NTC UGATE1
470K_4_NTC

470K_4_NTC
27.4K/F_4

27.4K/F_4
PR113

PR114

PR141

PR132

IMON_NB 2 21 BOOT_1
IMON_NB BOOT1

IMON 10 41
IMON EP
0.1u/10V_4

0.1u/10V_4

ISUMN

ISUMP
COMP

ISEN1

ISEN2
PC135

PC136

VSEN
133K/F_4

133K/F_4

RTN
PR194

PR197
3.83K/F_4

3.83K/F_4

Add 9 GND VIAs

FB
PR102

PR156

for thermal pad

19

18

16

17

15

14

13

12

PR198 +5V_S5
B B
1K_4
62771_VSEN

62771_RTN

ISEN2
62771_FB

ISUMN

Place NTC close to the Place NTC close to the 62771_COMP PR199 PR146
10K_4 2.2/F_6
VDDNB Hot-Spot. VDDCORE Hot-Spot. PC104 ISEN1 BOOT_1
VIN

2200p/50V_4
47p/50V_4

0.1u/50V_6

4.7u/25V_8

4.7u/25V_8
5

1
PC69

PC63
PC92

PC59

PC56
PR160 PC107 PR168 0.22u/25V_6
*0_4 150p/50V_4 267K/F_4

2
UGATE_1 4

PC114 PR170

1
2
3
680p/50V_4 2K/F_4 PQ26 PL7
VSUM+ AON6414AL 0.36uH DCR=1.1mOhm
PHASE_1 1 2 +VDD_CORE

PR131
PC124 PR186

4
2.2_6
100p/50V_4 499/F_4 PR157
+VDD_CORE
47n/16V_4
0.15u/10V_4

2.61K/F_4
+ +
PC105

PC106

PR161
11K/F_4

LGATE_1 4
20120531

0.1u/10V_4

10u/6.3V_8
PC122 PR177

1000p/50V_6

PC47

PC51
330p/50V_4 1.65K/F_4

1
2
3

PC85
PR147 Close with PQ29 PC61 C373
PR133 10K_6_NTC AON6780 330u/2V_7343 *330u/2V_7343
PR138 PR181
phase1 inductor
10_4 Load line setting
*short_4 665/F_4
5 APU_VDD_RUN_FB_H VSUM-

PR139 1Phase VSUM+ PR154 3.65K/F_6

*short_4 PC111
5 APU_VDD_RUN_FB_L
OCP
1Phase 0.1u/10V_4
+VDD_CORE
RC time TDC : 26A
constant PEAK : 35A
A PR151 VSUM- PR150 1/F_4 A
10_4 OCP : 44A
PC113
0.01u/16V_4 Width : 1400mil
Load Line = 2.1mV/A
Close to the
CPU side.

Quanta Computer Inc.

PROJECT : ZRP
Size Document Number Rev
+VDD_CORE 1+1 (ISL62771) A1A
Date: Friday, July 20, 2012 Sheet 39 of 46
5 4 3 2 1
 5 4 3 2 1

40
2012-07-17
+3V_GFX to +3V +3V

H_VID0
PR42 *EV@10K/F_4 Thames(Pro,XT) VDDC VID TABLE
H_VID1
PR43 *EV@10K/F_4
PWRCNTRL0 PWRCNTRL1
H_VID2
PR44 *
(VID4) (VID3)
VDDC(V)
Default 0.85V POP PR44 ; DNP PR39 (Mars) H_VID3
(GPIO_15) (GPIO_20)
PR45 *EV@10K/F_4
D 0.900 1 0 D

*
Default 0.9V POP PR39 ; DNP PR44 (Thames Pro,XT) H_VID4
PR41 *
H_VID5
1.000 0 1

*
PR46 *

*EV@10K/F_4
+3V

+3V Mars VDDC VID TABLE

2012-07-18 add PR221

*
*EV@100K_4

*EV@10K/F_4

*
PWRCNTRL0 PWRCNTRL1 PWRCNTRL2 PWRCNTRL3 PWRCNTRL4

PR35

PR31

PR39

PR34

PR30
2

PQ54 +5V_S5 (VID4) (VID3) (VID2) (VID1) (VID0)

*
VDDC(V)
(GPIO_15) (GPIO_20) (GPIO_16) (GPIO_29) (GPIO_30)
SYS_SHDN# 5,15,35,43

PR17

PR73

PR89
THAL_GPU_VR 1 3 1.100 0 0 0 0 0
1.075 0 0 0 1 0
PC13
*
1.050 0 0 1 0 0
8 PE_PWRGD 1.025 0 0 1 1 0

26
PU3 *
1.000 0 1 0 0 0
0.975 0 1 0 1 0

V5IN
15 GPU_DPRSLPVR
33 PGD DRVH2 30

34 29
0.950 0 1 1 0 0
PR33 * PG VBST2
C
51728_V5FILT 13 28
0.925 0 1 1 1 0 C

PCNT LL2
Check EN level PR20 *EV@100K/F_4 12 27
0.900 1 0 0 0 0
SLP DRVL2
PR22 *Short_4 51728_EN 35 3
0.875 1 0 0 1 0
7,41,42 DGPU_PWREN EN CSP2
THAL_GPU_VR R104 * 10 4
0.850 1 0 1 0 0
THAL CSN2
H_VID0 20
0.825 1 0 1 1 0
15 PWRCNTRL4 PR84 *short_4 VID0
H_VID1 19 21 51728_DRVH1
0.800 1 1 0 0 0
15 PWRCNTRL3 PR87 *short_4 VID1 DRVH1
H_VID2 18 22 51728_VBST1
15 PWRCNTRL2 PR88 *short_4 VID2 VBST1
H_VID3 17 23 51728_LL1
15 PWRCNTRL1 PR86 *short_4 VID3 LL1
H_VID4 16 24 51728_DRVL1
15 PWRCNTRL0 PR85 *short_4 VID4 DRVL1
H_VID5 15 6 51728_CSP1
VID5 CSP1
14 5 51728_CSN1
VID6 CSN1 +3V
51728_DROOP
PC31 * 25
PGND
PR72 *Short_4 39 PR32
DROOP PR74 * VIN
PR77 *EV@0_4 51728_VBST1
* 36 51728_TONSEL
TONSEL

1
B +3V B

*
51728_V5FILT 51728_VREF 40
VREF

5
+

PC38

PC35

PC14

PC37
TRIPSEL 31 51728_TRIPSEL PC16
* PC40
PC11 PR78 32 51728_OSRSEL 100u/25V_6X5.8

2
* OSRSEL 51728_DRVH1
*EV@113K/F_4 4

PR28
PR27

1
2
3
51728_SLEW 37 PR25 *EV@10K/F_4 PQ18 PL2
PR26 PR23 PR29 PR21 * SLEW * * DCR=1.1mOhm

*Short_4
*Short_4
*EV@0_4 *EV@0_4 51728_LL1 1 2 +VGPU_CORE
*Short_4
9 THRM

*
PR38 1

4
PU

PR24
PR37
51728_TONSEL * * 38 51728_V5FILT + + PC33
V5FILT
TPAD10
TPAD11
TPAD12
TPAD13
TPAD14
TPAD15
TPAD16

*short_4
TPAD1
TPAD2
TPAD3
TPAD4
TPAD5
TPAD6
TPAD7
TPAD8
TPAD9

*
IMON

PwPd

51728_DRVL1 4 4 *
GND
GFB
VFB

PC19

PC18
PC39

PC12
*

1
2
3

1
2
3
PR19

PC10 PR18 PQ17 PQ4

8

11

41

42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57

+VGPU_CORE

PR70

PR76
*EV@0_4

* *EV@0_4 * *EV@AON6780

51728_CSP1 +VGPU_CORE
PR83
Countinue current:18A

*
* 51728_IMON

PR71

PR80
PR82 PR79 *short_8 PC17
*short_4 *EV@0.1u/25V_4 Peak current:24A
51728_VFB Close to the
18 GPUVDDC_SENSE OCP minimum 28A

*
A A
VR side.

PC32
51728_GFB
18 GPUVSS_SENSE Loadline=1.5mV/A
PR81 PR40 PC21
Parallel *short_4 * *
PR36 PC15
* *EV@0.1u/25V_4
51728_CSN1 Quanta Computer Inc.
Close to the PR75
PC36 PC20 * PROJECT : ZRP
GPU side. * * Size Document Number Rev
A1A
+VGPU CORE(TPS51728)
Date: Friday, July 20, 2012 Sheet 40 of 46
5 4 3 2 1
 5 4 3 2 1

41
+3VPCU

+1.8V_GFX
+3V 1.8 Volt +/- 5%
*
PC73
PC72
TDC : 1.4A
* PU5 * PEAK : 1.9A
PR103 16 10
*
VIN PH Width : 60mil
1 11 PL3 +1.8V_GFX
VIN PH *
D
2 VIN PH 12 D

14 13 PR98 *Short_4
PWRGD BOOT
PR117 510/F_4 15 6 PC50
7,40,42 DGPU_PWREN EN VSNS * PR115
R1 *
7 COMP GND 3
PC54 PC53 PC49
8 4 * * *
RT/CLK GND 1.8V_VSNS

PAD
PAD
PAD
PAD
PAD
PAD
PC64 9 5
* PR105 PR99 SS AGND
* * R2 PR118

22
21
20
19
18
17
*
V0=0.8*(R1+R2)/R2
PC62 PC58 PC55
*EV@100p/50V_4
* *

+1.5VSUS +PCIE_VDDC_GFX

5
1
2
1V/+/-5%
+3V +5V_S5
3 TDC : 1.65A
*
PQ32 PC103
*
PEAK : 2.2A

4
C Width : 80mil C
PR175 PC83 PC75
* PU10 * * PR180 PC74
* * *
6 +PCIE_VDDC_GFX
VCC +1.5VSUS
G9334_DRV
Rg
4 PGD DRV 5
1
DGPU_PWREN PR206 *Short_4 1 3 5 2
EN FB
3
GND
PC118 PC102
PQ36
PR166 *EV@10u/6.3V_8 *EV@MDV1528Q *EV@10u/6.3V_8
2

4
* PR179 Vout = (1+Rg/Rh)*0.5
PC109 *
* PR207 PC110 =1V (for Pro & XT) G9334_DRV
*EV@100K_4 Rh
*
Rh change to 110/F_4 (CS11102FB18)
is 0.95V for Mars
VIN +1.5V_GFX +3V_GFX +15V +1.5VSUS SP : Thames Pro,XT Rh=100ohm(CS11002FB22)
Mars Rh=110ohm(CS11102FB18)

5
PR48 PR47 PR51 PR55
* * * *

B B
PX_MODE_D 4 PQ34
*
3

3
2
1
PR50 +1.5V_GFX
DGPU_PWREN 2 * 2 2 2
1

PQ5 PQ6 PQ8 PQ9

* * * *
PC22 PR49
1

* *EV@100K_4
TDC : 1.65A
2

PEAK : 2.2A
VIN +3V
+3V_GFX +15V Width : 80mil

PR54 PR56 PR57

3

* * *

2
3

PQ12
PR52 *
TDC : 0.05A
1

2 * 2 2 +3V_GFX
A PC24
PEAK : 0.06A A
1

PQ7 PQ10 PQ11 *EV@2.2n/50V_4

PR53
*EV@100K_4
* * * Width : 20mil
1

1
2

Quanta Computer Inc.

PROJECT : ZRP
Size Document Number Rev
A1A
GPU_POWER/+1.8V_GPU
Date: Friday, July 20, 2012 Sheet 41 of 46
5 4 3 2 1
 5 4 3 2 1

VIN
42
+5V_S5
D D

+3V
PC8
PC9 PC6 *
* *

5
PR1 PU2
* *

7
PQ2
*

V5IN
VDDCI_DRVH 4
1 9 PC29 +VDDCI_GFX
PGOOD DRVH PR2 *
PR6 *Short_4 VDDCI_EN 3 10 VDDCI_VBST *Short_4 PL1

3
2
1
7,40,41 DGPU_PWREN EN VBST *
VDDCI_TRIP 2 8 VDDCI_SW
PR4 * TRIP SW
PR3 VDDCI_TST 5 6 VDDCI_DRVL +VDDCI
TST DRVL
*EV_SP@100K/F_4 PR16 *
1V +/-5%

5
12 GND GND 11
PR69 PR15 TDC : 6A

GND

GND

GND

GND
*EV_SP@4.7_6 *

FB
C + PEAK : 8A C
4
OCP : 9A

13

14

15

16

4
PC30
VDDCI_FB *
PC34 Width : 360mil

3
2
1
PR12 *
PC28 *
PQ1 *EV_SP@680p/50V_6
*

SP : OCP=9A
L ripple current
1. Thames XT don't stuff all EV_SP@ +3V_S5
=(19-1)*1/(2.2u*290k*19)
2. Thames Pro & Mars stuff all EV_SP@ =1.485A
Vtrip=9-(1.485/2)*14mohm
(1) Thames Pro PR14 = 30.1K(CS33012FB18) PR14 PR10 =0.1156V
(2) Mars PR14 = 12.1K(CS21212FB18) * *EV_SP@10K/F_4 Rlimit=0.1156/10uA*8=92.484Kohm
B B

3
Thames(Pro) VDDCI VID TABLE
PWRCNTRL5 PR11 *Short_4
VDDCI(V) 2 PWRCNTRL5 15
(GPIO_6) PQ3
*
0.9 0 PC4

1
*
1.0 1

Mars VDDCI VID TABLE

PWRCNTRL5
VDDCI(V)
(GPIO_6)
0.90 0
A 0.95 1 A

PR14 change to 12.1K/F_4 Quanta Computer Inc.

(CS21212FB18) for Mars 0.95V PROJECT : ZRP
Size Document Number Rev
A1A
VDDCI(TPS51518)
Date: Friday, July 20, 2012 Sheet 42 of 46
5 4 3 2 1
 5 4 3 2 1

VIN +3V +5V +0.75V_DDR_VTT +1.5V +15V

43
D D
VIN PR191 PR184 PR213 PR214 PR209 PR215
1M_4 22_8 22_8 *22_8 22_8 1M_4

MAINON_G MAIND
PD1 MAIND 35,36

3
DA2J10100L

3
PR190
MAINON 2 PQ45 1M_4 2 2 2 2 2
7,31,34,36,38 MAINON DTC144EUA PC125
PQ43 PQ50 PQ49 PQ48 PQ51 *2200p/50V_4
2N7002K 2N7002K *2N7002K 2N7002K 2N7002K

1
PR94

1
1M_6 PR187
Thermal protection

1
*100K_4
PQ21
AO3409
2

3
C C

3
S5_ON 2
34,35 S5_ON

PQ19 PR97
DTC144EUA 1 *short_6

PR93 for setting TEMP. VL VL

887/F_4 for 86'C
(CS18872FB01) SYS_SHDN# 5,15,35,40
1.5K/F_4 for 70'C
(CS21502FB14) PR96
200K_6
PR92 PC42
PR93 200K/F_4 0.1u/50V_6

3
1.5K/F_4
8

PR95
10K_6_NTC 2.469V 3 +
1 2
2 -
B PQ22 B
3

PU4A 2N7002K
4

BA10393F PC41

1
0.1u/50V_6
S5_ON 2
PR90
PQ20 200K/F_4
2N7002K
1

PR91
100K_4

5 +
7
6 -
PU4B
A BA10393F A

For EC control thermal protection (output 3.3V) Quanta Computer Inc.

PROJECT : ZRP
Size Document Number Rev
A1A
Discharge/Thermal
Date: Friday, July 20, 2012 Sheet 43 of 46
5 4 3 2 1
 5 4 3 2 1

Model ZRP MB BOARD

MODEL REV CHANGE LIST Page From To
1
ZRP M/B A First Release 2
3
D 2012-06-08 4 D
C 5
Update C.R schematic for new C.R connector. (no support MMC 8 bit)
Add header LVDS@ on page8, page24, page25 6
Add header KBL@ on page33 7
Change HE1 P/N from AL009132001 to AL001691000. 8
9
2012-06-11 10
Add header SSD@ on page28 11
Update SMBUS information 12
2012-06-13 13
Change CN6 pin order 14
Connect Hole13 to GND 15
16
2012-06-14 17
Chagne CN6 P/N, footprint & symbol 18
C Change Hole9's footprint 19 C

2012-06-15 20
Add level shift circuitry of TP_INT for leakage 21
22
2012-06-18 23
Change Hole12 ADOGND to GND 24
Modify CN15.pin1 & Q11.pin4's net name from PCIE_WAKE#_WLAN to PCIE_WAKE#_WLAN_R 25
Change to 0402 short pad: PR119, PR128, PR129, PR100, PR152, PR153, PR193, PR205, PR138, PR139, PR65, 26
PR84, PR85, PR86, PR87, PR88, PR81, PR82, PR76 27
Change to 0603 short pad: PR219,PR101,PR145,PR134,PR97 28
2012-06-19 29
NI R162, Stuff R161 for WLAN function 30
Modify U8 symbol 31
Add TP@ for C463,R307,R665,Q46,R666,R15 32
Change CN15 P/N to DFHS52FR044 33
B
Change CN3 P/N to DFHS52FR084 34 B

35
2012-06-20 36
Change CN8's P/N & footprint 37
Change Hole 5, 8 ,11 footprint 38
2012-06-21 39
Change CN4's footprint 40
Add eDP@ for R502 41
Update CN11 symbol (Add 2 pcs GND pin)
2012-06-22
Change Y3 P/N & footprint
Change R334 value from 120k to 665k.
Add xxx@ on GPIO strap pin on page 9.
Change C783, C780 value from 22 pF to 27 pF (x'tal report)
A A
Change C778, C772 value from 18 pF to 22 pF (x'tal report)

Quanta Computer Inc.

PROJECT : ZRP
ZRP PCBA NO : REV: A DOC. NO : Size Document Number Rev
CHANGE LIST A1A
APPROVED BY : CHECK BY : DRAWING BY : DATE : Date: Friday, July 20, 2012 Sheet 44 of 46
5 4 3 2 1
 5 4 3 2 1

MODEL REV CHANGE LIST Model ZRP MB BOARD

ZRP M/B - 6L C 2012-06-25 Page From To

Change CN13 P/N from DFHS09FR036 to DFHS09FR125 1
Change RP1 & PR3 P/N to CJ022042N15 2
Change R655 & R651 P/N to CS03302JB29 3
Change PL6 P/N to CV+36N0MZ02 4
D D
Change PR182 P/N to CS17682FB00 5
2012-06-26 6
Change PC33 P/N to CC7560JMZ15 7
8
2012-06-27 9
Change C351 & C357 P/N to CH6101M9905 10
2012-07-02 11
Define board ID9 VRAM 2G stuff R279, VRAM 1G stuff R525. 12
Change R536,R542,R551 0ohm to 75ohm bead 13
Change PR203 from CS35102FB04(51K) to CS35762FB11(57.6K) 14
15
2012-07-11_Rev1 16
Delete TP26 net name 17
RAMP Add C787, C788 18
C 2012-07-11_Rev2 19 C

Delete PC23, R45 20

21
2012-07-12_Rev1 22
Add D29 23
Change test point's Part Reference from T* to TP* 24
2012-07-12_Rev2 25
Delete PC43, PC40 always stuff 26
27
2012-07-12_Rev3 28
Change U8's power plane from +5V_S5 to +5VPCU 29
2012-07-13_Rev1 30
Change CN15's footprint from minipci-aaa-pci-092-k03-52p-ldv to mipci-c-1759513-52p-ldv-smt 31
Change CN8's pin order 32
Change CN7's P/N 33
B
34 B

2012-07-16_Rev1 35
Change CN8's P/N from DFFC04FR087 to DFFC04FR033 (top contact) 36
Add C789, C790 for APU_PWRGD used 37
2012-07-16_Rev2 38
Change CN8's pin order & footprint from 51529-00401-001-4p-l to 91517-0040n-001-4p-r 39
Add R45 & R124 40
Change R394,R396,R438,R439 from 4.7K to 1K & R50,R57 from 10K to 4.7K 41
2012-07-18_Rev1
Change PR93 P/N to CS21502FB14
Delete L51, L52 (LVDS common mode choke)
2012-07-18_Rev2
Change PR117 to 0 ohm
A
Delete R315, R316 and add L52 (LVDS common mode choke for EMI test) A
Add SYS_SHDN#'s level shift circuit on page 40
2012-07-18_Rev6
Add C791, C792, C793 near CN10 and add C794 for EMI
Change R642, R643, R644, R645 to L16, L18, L22, L25 (BLM18AG601SN1D) Quanta Computer Inc.
PROJECT : ZRP
ZRP PCBA NO : REV: A DOC. NO : Size Document Number Rev
CHANGE LIST A1A
APPROVED BY : CHECK BY : DRAWING BY : DATE : Date: Friday, July 20, 2012 Sheet 45 of 46
5 4 3 2 1
 5 4 3 2 1

MODEL REV CHANGE LIST Model ZRP MB BOARD

ZRP M/B - 6L RAMP 2012-07-20_Rev1 Page From To

Stuff R104 1
Change PR117 from 0 ohm to 510 ohm 2
3
D
4 D
5
6
7
8
9
10
11
12
13
14
15
16
17
18
C 19 C

20
21
22
23
24
25
26
27
28
29
30
31
32
33
B
34 B

35
36
37
38
39
40
41

A A

Quanta Computer Inc.

PROJECT : ZRP
ZRP PCBA NO : REV: A DOC. NO : Size Document Number Rev
CHANGE LIST A1A
APPROVED BY : CHECK BY : DRAWING BY : DATE : Date: Friday, July 20, 2012 Sheet 45 of 46
5 4 3 2 1
 5 4 3 2 1

ZRP Power On Sequence: S5 > S0 45

+3V_RTC
VIN
+5VPCU/+3VPCU/+15V
AC not present equal to LOW; AC present equal to High
ACIN
D
S5_ON active by pull up 10k to +3VPCU D

EC FW download APU Power on sequence required:

EC SPI signals Llano APU:
1.Group A ( +1.5VSUS, +2.5V_VDDA ) ramp before Group B
( +VDD_CORE, +VDDNB_CORE, +1.2V_VDDPR )
Power button from switch to EC
NBSWON#
HUDSON-M3:
S5_ON 1.+3V_S5 ramp before +1.1V_DUAL
2.+3V ramp before +1.1V
3.+3V_S5,+3V ramping down time > 300us
+3V_S5/+5V_S5 4.100uS <= +3V_S5,+3V <= 40mS
5.100uS <= All power rails except +3V_S5,+3V <= 40mS
+1.1V_DUAL_EN
+1.1V_DUAL
+1.1V_DUAL_PG 20ms delay at least

RSMRST#
50ms Max

RTCLK
>16ms Min
Power button from EC to FCH
DNBSWON#
C C

SUSC
SUSON
+1.5VSUS +0.75V_DDR_VTT only will be shut down in S3 mode and for DDR3 SODIMM only
APU GROUP A power +0.75V_DDR_VTT
HWPG_1.5V
SUSB
MAINON
+5V/+3V

+2.5V/+1.5V

+1.1V Controlled by +3.3V

VDDA_PWRGD

APU GROUP B power +VDDNB_CORE

B B

+VDD_CORE

+1.2V

VRM_PWRGD

HWPG_1.2V

98ms < T <150ms

FCH_PWRGD 50ms Max

APU_CLKP/N

38ms Max
APU_PWRGD
101ms < T <113ms
A_RST#(PLTRST#) 75ns < T <100ns

A PCIRST# 1ms < T <2.3ms A

APU_RST#

Quanta Computer Inc.

PROJECT :ZRP
Size Document Number Rev
A1A
POWER SEQUENCE
Date: Friday, July 20, 2012 Sheet 46 of 46
5 4 3 2 1