Acer TravelMate 8200 8210 8202wlmi - QUANTA ZC1 - REV 1A Sec

5 4 3 2 1
EV@: Stuff when external VGA used

ZC1 SYSTEM BLOCK DIAGRAM SH@: Stuff when SATA HDD used
X'TAL PH@: Stuff when PATA HDD used
14.318MHZ
Yonah/Merom 479
Clock Generator CPU
DVI ICS954310BGLF
uFCPGA Thermal Sensor
P2 P3,P4 P5 PCI-Express X 2
P25
D EZ4 Docking D
VRAM X 4(GDDR3) Connector TV out / CRT Switch

TVOUT 256MB/500MHZ 533/667 MHZ FSB P25,26
P23 PCIE1~2 , Lan
P25 Audio
Ser & Par Port Switch
DVI P37
Dual Channel DDR2 DDR II PS2 , VGA, DVI
TFT LCD Panel TVout VGA CALISTOGA-945PM SODIMM0 SPDIF,SM BUS DVI
PCI-Express Switch
15.4" LVDS ATI M56P 533/667 Mhz
16X Lan 1466 DDR II P32 10/100/1G
WSXGA+ MAX4892
VGA FCBGA SODIMM1
P18,P19,P20,P21, P25,P28
P22,P24 P12,P13
P25
P6,P7,P8,P9,P10,P11 USB5
X'TAL
27M
CRT
C
P26 DMI X4 interface MiniCard / New Card C
WLAN
HDD SATA
P29 P33
P35
ICH7-M Digital Home PCI-Express
Bluetooth Media-Bay
USB6 P29
ODD/2nd HDD/2nd Battery
P35 652 BGA
Camera Module(1.3M)
PCI Bus interface
USB 2.0 X'TAL24.576MHZ
X'TAL USB7 P25
6M P14,P15,P16,P17 X'TAL
25M
6 in 1 Cardreader X'TAL
SMBUS 32.768KHZ Intel Tekoa
(SMSC 2228) P31
USB4 PCMCIA+1394 GigaLAN
G-SENSOR +Cardreader
Int MIC P35
B
USB Port x 4 P37 Controller 82573E P27 B
USB0~3 P29
LPC O2 711MP1 SPI FLASH

Azalia Audio Transformer RJ45
X'TAL OSC
Audio Amplifier Controller 32.768K 48MHZ P30,P31 P27 P28 P28
Realtek ALC883 Azalia
Maxim Max 9750
P37 P36 KBC PC97551
P39
IEEE 1394
Smart card PCMCIA Slot
Port Fan Header
P31 P30 P30 P5
MIC Jack Line in
P37 P37 G sensor
BIOS
Primary Battery
P39 P35
Secod Battery
A P45,P46 A
Super I/O TPM 1.2

Speaker Phone Jack Azalia MDC FIR
om
P37 P37 P36 Touch Pad NS PC87383 PROJECT : ZC1
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P38 P38
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(Dual-Point)
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(Option) Quanta Computer Inc.
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P40 P38
RJ11
f@
P28 Size Document Number Rev
in
BLOCK DIAGRAM 1A
xa
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Date: Monday, November 07, 2005 Sheet 1 of 46
5 4 3 2 1
A B C D E
FSC FSB FSA CPU SRC PCI

1 0 1 100 100 33
0 0 1 133 100 33 Default
0 1 1 166 100 33
0 1 0 200 100 33
0 0 0 266 100 33
A1A-change X1,X2 capacitor from 27pf to 33pf(CL=20pf)
1 0 0 333 100 33 VDD_A
4 Close to IC <500mils 4
1 1 0 400 100 33 C807
33P-50V_4
1 1 1 200 100 33 2 1 CG_XIN
Place these termination to close CK410M.
45
46
2
U46
L68 25 mils +-20PPM,20PF C809 Y6 58 60 14M_REF R576 33_4
VDDA
GNDA
X1 REF0 14M_ICH 16
BK2125HS121-T_8 33P-50V_4 14.318MHZ
+3V VDD_SRC_CPU 2 1 CG_XOUT 57 52 RHCLK_CPU 1 2
1
X2 CPUCLKT0 CLK_CPU_BCLK 3
51 RHCLK_CPU# 3 4 C799
CPUCLKC0 CLK_CPU_BCLK# 3
120 ohms@100Mhz C794 C496 C523 C814 C804 +3V R599 *10K_4 CK-410M RP59 33_4P2R_S *10P_4
.1U-10V_4 10U-10V_8 16,41 VR_PWRGD_CK410# 10 49 RHCLK_MCH 1 2
Vtt_PwrGd#/PD CPUCLKT1 CLK_MCH_BCLK 6
.1U-10V_4 .1U-10V_4 .1U-10V_4 16 PM_STPCPU# PM_STPCPU# 62 48 RHCLK_MCH# 3 4
CPU_STOP# CPUCLKC1 CLK_MCH_BCLK# 6
16 PM_STPPCI# PM_STPPCI# 63 RP60 33_4P2R_S
R580 2.2_6 VDD_A PCI/PCIE_STOP#
44
CGCLK_SMB CPUCLKT2/PCIET8
13 CGCLK_SMB 54
SCLK CPUCLKC2/PCIEC8
43 A1A:Remove PCIE clock
C498 C497 CGDAT_SMB 55
13 CGDAT_SMB SDATA
.1U-10V_4 10U-10V_8 R600 33_4 41 CLK_PCIE_EZ2_L 1 2
16 CLKUSB_48 REQ1#/PCIET7 CLK_PCIE_EZ2 32
CLK_BSEL0 R604 4.7K_4 12 40 CLK_PCIE_EZ2#_L 3 4 CLK_CPU_BCLK 1 2
FSA/USB_48MHz REQ2#/PCIEC7 CLK_PCIE_EZ2# 32
CLK_BSEL1 16 RP56 33_4P2R_S CLK_CPU_BCLK# 3 4
CLK_BSEL2 R574 4.7K_4 FSB/TEST_MODE RSRC_MCH RP54 49.9_4P2R_S
61 39 1 2 CLK_PCIE_3GPLL 8
R581 33_4 REF1/FSLC/TEST_SEL PCIET6 RSRC_MCH# CLK_MCH_BCLK
38 3 4 CLK_PCIE_3GPLL# 8 1 2
38 SIO_14M VDD_REF PCIEC6 RP57 33_4P2R_S CLK_MCH_BCLK#
56 3 4
VDD_SRC_CPU VDD_REF CLK_PCIE_EZ1_L RP55 49.9_4P2R_S
50 36 1 2 CLK_PCIE_EZ1 32
C798 VDDCPU PCIET5 CLK_PCIE_EZ1#_L 3
35 4 CLK_PCIE_EZ1# 32
*10P_4 VDD_PCI PCIEC5 RP58 33_4P2R_S
1
VDD_PCI_1 CLK_PCIE_NEW
7 30 3 4 CLK_PCIE_NEW_C 33
VDD_PCI_2 PCIET4 CLK_PCIE_NEW# CLK_PCIE_LAN
25 mils PCIEC4
31 1 2 CLK_PCIE_NEW_C# 33 3 4
VDD_SRC_CPU 21 RP67 33_4P2R_S CLK_PCIE_LAN# 1 2
3 L69 VDD_PCI VDD_PCIE RSRC_SATA RP73 49.9_4P2R_S 3
+3V 28 26 3 4 CLK_PCIE_SATA 14
BK2125HS121-T_8 VDDPCIE SATA_CKT RSRC_SATA# CLK_PCIE_3GPLL
42 27 1 2 CLK_PCIE_SATA# 14 1 2
C813 C526 C805 VDD_PCIE SATA_CKC RP66 33_4P2R_S CLK_PCIE_3GPLL# 3 4
.1U-10V_4 .1U-10V_4 10U-10V_8 VDD_48 11 24 RSRC_ICH 3 4 RP52 49.9_4P2R_S
VDD_48 PCIET3 CLK_PCIE_ICH 15
25 RSRC_ICH# 1 2 CLK_PCIE_SATA 3 4
PCIEC3 CLK_PCIE_ICH# 15
CLKGN_REQ3_PCIE 32 RP65 33_4P2R_S CLK_PCIE_SATA# 1 2
R608 2.2_6 VDD_48 CLKGN_REQ4_PCIE REQ3(PCIE) CLK_PCIE_LAN_L 3 RP75 49.9_4P2R_S
33 22 4 CLK_PCIE_LAN 27
REQ4(PCIE) PCIET2 CLK_PCIE_LAN#_L 1 CLK_PCIE_MINI
23 2 CLK_PCIE_LAN# 27 3 4
C525 C541 Iref=5mA, R575 475/F_6 IREF PCIEC2 RP64 33_4P2R_S CLK_PCIE_MINI#
47 1 2
.1U-10V_4 10U-10V_8 Ioh=4*Iref IREF CLK_PCIE_MINI_ RP72 49.9_4P2R_S
19 3 4 CLK_PCIE_MINI 29
PCIET1 CLK_PCIE_MINI_# 1 CLK_PCIE_ICH
20 2 CLK_PCIE_MINI# 29 3 4
PCIEC1 RP63 33_4P2R_S CLK_PCIE_ICH#
RP61 1 2
DREFCLK 1 2 R_DOT96 14 17 R_DREFSSCLK RP74 49.9_4P2R_S
8 DREFCLK DOT96MHz 27Mfix/LCD_SSCGT/PCIE0T
R577 1_6 VDD_REF DREFCLK# 3 4 R_DOT96# 15 18 R_DREFSSCLK# CLK_PCIE_NEW_C 3 4
8 DREFCLK# DOT96MHz# 27SS/LCD_SSCGC/PCIE0C CLK_PCIE_NEW_C# 1 2
C800 C801 33_4P2R_S 5 R_PCLK_SIO R596 33_4 RP69 49.9_4P2R_S
selPCIEX0_LCD#/PCI5 PCI_CLK_SIO 38
.1U-10V_4 10U-10V_8 34 4 R_PCLK_711 R595 33_4 DREFCLK 3 4
GND_PCI_1
GND_PCI_2
T151 PWRSAVE# PCI4 PCI_CLK_711 30
R_PCLK_TPM R594 33_4 DREFCLK#
GND_SRC
3 PCLK_TPM 38 1 2
PCI3
GND_48
INTERNAL PULL HIGH 64 PCLK_MINI_LPC R588 33_4 RP70 49.9_4P2R_S
PCICLK2/REQ_SEL PCLK_MINI 29
9 R_PCLK_ICH R324 33_4 CLK_PCIE_EZ2 1 2
GND
GND
GND
PCIF1/selLCD_27# PCLK_ICH 15
8 R_PCLK_591 R602 33_4 CLK_PCIE_EZ2# 3 4
PCIF0/ITP_EN PCLK_591 39
RP51 49.9_4P2R_S
ICS954310BGLF CLK_PCIE_EZ1 1 2
53
13
59
2
6
29
37
+3V R597 10K_4 C538 C817 C819 CLK_PCIE_EZ1# 3 4
RP53 49.9_4P2R_S
ITP/SRC7 SELECT *10P_4 *10P_4 *10P_4 CLK_PCIE_M56# 1 2
CLKGN_REQ3_PCIE R590 10K_4 C539 C803 C818 CLK_PCIE_M56 3 4
33 NEW_CLKREQ#
CLKGN_REQ4_PCIE R289 10K_4
0: SRC7 1: ITP RP71 49.9_4P2R_S
32 EZ_CLKREQ#
*10P_4 *10P_4 *10P_4
2 2
PREQ3(PCIE) Latched Select A1A:Change pin 3 PCLK_LAN to PCLK_TPM
"0" : CLK Enable A1A-FSB Frequency Select:by CPU driven
"1" : CLK Disable Control : PCIE 2,4,6,8
+1.05V R328 *56.2/F_4 swap

PREQ4(PCIE) Latched Select
R_DREFSSCLK# 1 2
"0" : CLK Enable R338 0_4 CLK_BSEL0 R339 1K_4 R_DREFSSCLK 3 4
CLK_PCIE_M56# 18
3 CPU_BSEL0 MCH_BSEL0 8 CLK_PCIE_M56 18
"1" : CLK Disable Control : PCIE 1,3,5,7 RP62 EV@33_4P2R_S
R336 *1K_4
+3V +1.05V R327 *1K_4 R_PCLK_SIO R337 10K_4 Latched Select. (Pin 17,18)
+3V
"0" : LCD CLK(UMA)
R325 *10K_4 "1" : PCIEX CLK(M56)
R322 0_4 CLK_BSEL1 R323 1K_4 MCH_BSEL1 8
3 CPU_BSEL1
R326 *0_4 PCLK_MINI_LPC R587 *10K_4 Latched Select. (Pin 40,41)
+3V
Q34 R578 R579 "0" : PCIEX CLK
2
RHU002N06 10K_4 10K_4 R586 10K_4 "1" : PEREQ#

3 1 CGDAT_SMB
16,27,29,32,33,35 PDAT_SMB
R_PCLK_ICH R603 10K_4 SELLCD_27# Select. (Pin 17,18)
+3V
1 Stuff 0 ohm for 533MHz, NC for 667MHz "0" : 27MHzSS/27MHzSS# pair 1
R598 *10K_4 "1" : LCD CLK pair
+3V +1.05V R573 *1K_4
Q35
PROJECT : ZC1
2
RHU002N06 R571 0_4 CLK_BSEL2 R570 1K_4

3 CPU_BSEL2 MCH_BSEL2 8
3 1 CGCLK_SMB R572 *0_4
16,27,29,32,33,35 PCLK_SMB Quanta Computer Inc.
Size Document Number Rev
CLOCK GENERATOR 1A
Date: Friday, December 09, 2005 Sheet 2 of 46

A B C D E
5 4 3 2 1
T116
U43A
6 H_A#[31:3] H_A#3 +1.05V
J4 H1 H_ADS# 6
H_A#4 A[3]# ADS#
L4 E2 H_BNR# 6
H_A#5 A[4]# BNR# +1.05V
M3 G5 H_BPRI# 6 +1.05V 2,4,6,8,9,10,14,17,44
H_A#6 A[5]# BPRI#
K5
H_A#7 A[6]#
M1 H5 H_DEFER# 6
A[7]# DEFER#
ADDR GROUP 0
H_A#8 N2 F21
H_A#9 A[8]# DRDY# H_DRDY# 6
J1 E1 R268 Near to MCH <500mils
H_A#10 A[9]# DBSY# H_DBSY# 6
N3 56.2/F_4
CONTROL
H_A#11 A[10]#
P5 F1 H_BREQ#0 6
D H_A#12 A[11]# BR0# D
P2
H_A#13 A[12]#
L1 D20 6 H_D#[63:0] H_D#[63:0] 6
H_A#14 A[13]# IERR#
P4 B3 H_INIT# 14
H_A#15 A[14]# INIT# T127 U43B
P1
H_A#16 A[15]# H_D#0 E22 H_D#32
R1 H4 H_LOCK# 6 AA23
A[16]# LOCK# H_D#1 F24 D[0]# D[32]# H_D#33
6 H_ADSTB0# L2 H_CPURST# 6 AB24
ADSTB[0]# H_D#2 E26 D[1]# D[33]# H_D#34
6 H_REQ#[4:0] B1 V24
H_REQ#0 K3 RESET# H_RS#0 H_D#3 H22 D[2]# D[34]# H_D#35
F3 V26
REQ[0]# RS[0]# D[3]# D[35]#
DATA GRP 0
H_REQ#1 H2 F4 H_RS#1 H_D#4 F23 W25 H_D#36
DATA GRP 2
H_REQ#2 K2 REQ[1]# RS[1]# H_RS#2 H_D#5 G25 D[4]# D[36]# H_D#37
G3 H_RS#[2:0] 6 U23
H_REQ#3 J3 REQ[2]# RS[2]# H_D#6 E25 D[5]# D[37]# H_D#38
G2 H_TRDY# 6 U25
H_REQ#4 L5 REQ[3]# TRDY# T29 H_D#7 E23 D[6]# D[38]# H_D#39
U22
REQ[4]# H_D#8 K24 D[7]# D[39]# H_D#40
6 H_A#[31:3] G6 H_HIT# 6 AB25
H_A#17 HIT# H_D#9 G24 D[8]# D[40]# H_D#41
Y2 E4 H_HITM# 6 W22
H_A#18 A[17]# HITM# H_D#10 J24 D[9]# D[41]# H_D#42
U5 Y23
H_A#19 A[18]# T31 H_D#11 J23 D[10 D[42]# H_D#43
R3 AD4 AA26
H_A#20 A[19]# BPM[0]# T30 H_D#12H26 D[11]# D[43]# H_D#44
W6
A[20]# BPM[1]#
AD3 XDP PU_R < 0.2" D[12]# D[44]#
Y26
H_A#21 U4 AD1 T119 H_D#13 F26 Y22 H_D#45
XDP/ITP SIGNALS
H_A#22 A[21]# BPM[2]# T33 H_D#14K22 D[13]# D[45]# H_D#46
Y5 AC4 AC26
H_A#23 A[22]# BPM[3]# T118 H_D#15H25 D[14]# D[46]# H_D#47
U2 AC2 AA24
H_A#24 A[23]# PRDY# +1.05V D[15]# D[47]#
R4 AC1 XDP_BPM#5 6 H_DSTBN#0 H23 W24 H_DSTBN#2 6
H_A#25 A[24]# PREQ# XDP_TCK DSTBN[0]# DSTBN[2]#
T5 AC5 6 H_DSTBP#0 G22 Y25 H_DSTBP#2 6
H_A#26 A[25]# TCK XDP_TDI T117 DSTBP[0]# DSTBP[2]#
T3 AA6 6 H_DINV#0 J26 V23 H_DINV#2 6
H_A#27 A[26]# TDI XDP_TDO DINV[0]# DINV[2]#
C W3 AB3 6 H_D#[63:0] H_D#[63:0] 6 C
H_A#28 A[27]# TDO XDP_TMS
W5 AB5
H_A#29 A[28]# TMS XDP_TRST# R274 H_D#16N22 H_D#48
Y4 AB6 AC22
H_A#30 A[29]# TRST# D[16]# D[48]#
W2 C20 XDP_DBRESET# 68_4 H_D#17K25 AC23 H_D#49
H_A#31 A[30]# DBR# H_D#18P26 D[17]# D[49]# H_D#50
Y1 AB22
A[31]# H_PROCHOT_R# R273 0_4 H_D#19R23 D[18]# D[50]# H_D#51
6 H_ADSTB1# V4 D21 H_PROCHOT# 41 AA21
ADSTB[1]# PROCHOT D[19]# D[51]#
DATA GRP 1
A24 H_D#20 L25 AB21 H_D#52
H_THERMDA 5
DATA GRP 3
THERMDA H_D#21 L22 D[20]# D[52]# H_D#53
THERM
14 H_A20M# A6 A25 H_THERMDC 5 AC25

A20M# THERMDC H_D#22 L23 D[21]# D[53]# H_D#54
14 H_FERR# A5 AD20
FERR# D[22]# D[54]#
14 H_IGNNE# C4 C7 THERMTRIP#_PWR R214 0_4
PM_THRMTRIP# 8,14
H_D#23M23 AE22 H_D#55
IGNNE# THERMTRIP# H_D#24P25 D[23]# D[55]# H_D#56
A1A:Stuff R1406 D[24]# D[56]#
AF23
R210 0_4 H_STPCLK_R# D5 H_D#25P22 AD24 H_D#57
14 H_STPCLK# STPCLK# T138 H_D#26P23 D[25]# D[57]# H_D#58
14 H_INTR C6 AE21
H CLK
LINT0 +1.05V H_D#27 T24 D[26]# D[58]# H_D#59

14 H_NMI B4 A22 CLK_CPU_BCLK 2 AD21
LINT1 BCLK[0] H_D#28R24 D[27]# D[59]# H_D#60
14 H_SMI# A3 A21 CLK_CPU_BCLK# 2 AE25
SMI# BCLK[1] H_D#29 L26 D[28]# D[60]# H_D#61
AF25
T112 TP_A32# T137 H_D#30 T25 D[29]# D[61]# H_D#62
AA1 AF22
T114 TP_A33# RSVD[01]# TP_EXTBREF T59 H_D#31N24 D[30]# D[62]# H_D#63
AA4 T22 AF26
T115 TP_A34# RSVD[02]# RSVD[12]# R267 D[31]# D[63]#
AB2 6 H_DSTBN#1 M24 AD23 H_DSTBN#3 6
T113 TP_A35# RSVD[03]# 1K/F_4 DSTBN[1]# DSTBN[3]#
AA3 N25 AE24
RESERVED
RSVD[04]# 6 H_DSTBP#1 DSTBP[1]# DSTBP[3]# H_DSTBP#3 6

T110 TP_A36# M4 D2 TP_SPARE0 T28 M26 AC20
RSVD[05]# RSVD[13]# 6 H_DINV#1 DINV[1]# DINV[3]# H_DINV#3 6 +1.05V
T109 TP_A37# N5 F6 TP_SPARE1 T27
T111 TP_A38# RSVD[06]# RSVD[14]# TP_SPARE2 T32 H_GTLREF COMP0 27.4/F_4 R264
T2 D3 AD26 R26
T26 TP_A39# RSVD[07]# RSVD[15]# TP_SPARE3 T121 D2C:Intel WW46,suggest Stuff R563(CS21002FB24) GTLREF COMP[0] COMP1 54.9/F_4 R265
V3
RSVD[08]# RSVD[16]#
C1 MISC COMP[1]
U26
B T124 TP_APM0# B2 AF1 TP_SPARE4 T120 U1 COMP2 27.4/F_4 R207 B
T125 TP_APM1# RSVD[09]# RSVD[17]# TP_SPARE5 T63 R563 1K/F_4 C26 COMP[2] COMP3 54.9/F_4 R208 25/25mils R212
C3 D22 V1
RSVD[10]# RSVD[18]# TP_SPARE6 T58 20/15mils TEST1 COMP[3] T34 T60 *200/F_6
C23
T145 TP_HFPLL RSVD[19]# TP_SPARE7 T142 R562 51_4 D25
B25 C24 E5 ICH_DPRSTP# 14
RSVD[11]# RSVD[20]# R266 TEST2 DPRSTP#
B5 H_DPSLP# 14
PZ47823-2743-42 2K/F_4 DPSLP#
D24 H_DPWR# 6
DPWR#
2 CPU_BSEL0 B22 D6 H_PWRGD 14
BSEL[0] PWRGOOD
2 CPU_BSEL1 B23 D7 H_CPUSLP# 6,14
+1.05V BSEL[1] SLP#
E2A:Add Q58,remove D42,R554,C338 2 CPU_BSEL2 C21 AE6 PSI# 41
BSEL[2] PSI# H_PWRGD is CMOS driving by ICH
XDP_DBRESET# R275
to resolve System can't boot
*54.9/F_4 PZ47823-2743-42
when battery under 30% issue +1.05V TO VRD
8,16,41 DELAY_VR_PWRGOOD A1A:Intel 2005 WW25 update
XDP_TMS R211 54.9/F_4 +1.05V
R271
+1.05V *330_6
3
XDP_TDI R209 54.9/F_4

1
2
2 D42 R554 Q20
XDP_BPM#5 R206 54.9/F_4 XDP_TCK PD 27.4/1% ? R217 *BAS316 *10K_4
56_4 XDP_DBRESET# 1 3
XDP_TRST PD 510ohm /5% ? Q58 *MMBT3904
SYS_RST# 16
2
A XDP_TDI PU 150ohm /1.05V BSS301 A

1
XDP_TCK R213 54.9/F_4 XDP_TMS PU 39.2/1%? C338 R276 0_4

XDP_TDO PU 54.9ohm?
PROJECT : ZC1
2
*1U-16V_6
For ITP700 R216
XDP_TRST# R215 54.9/F_4 THERMTRIP#_PWR 1 3 1999_SHT# 42
Quanta Computer Inc.
330_4 Q19 MMBT3904 Size Document Number Rev
CPU(1 OF 2 ) 1A
Date: Sunday, December 04, 2005 Sheet 3 of 46
5 4 3 2 1
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5 4 3 2 1
U43D VCC_CORE VCC_CORE

A4 P6 +1.05V +1.05V 2,3,6,8,9,10,14,17,44
VSS[001] VSS[082] U43C VCC_CORE
A8 P21 VCC_CORE 41
VSS[002] VSS[083] +1.5V
A11 P24 A7 AB20 +1.5V 8,10,15,17,29,33,42,43
VSS[003] VSS[084] VCC[001] VCC[68]
A14 R2 A9 AB7
VSS[004] VSS[085] VCC[002] VCC[69]
A16 R5 A10 AC7
VSS[005] VSS[086] VCC[003] VCC[70]
A19 R22 A12 AC9
VSS[006] VSS[087] VCC[004] VCC[71]
A23 R25 A13 AC12
VSS[007] VSS[088] VCC[005] VCC[72]
A26 T1 A15 AC13
VSS[008] VSS[089] VCC[006] VCC[73]
B6 T4 A17 AC15
D VSS[009] VSS[090] VCC[007] VCC[74] D
B8 T23 A18 AC17
VSS[010] VSS[091] VCC[008] VCC[75] VCC_CORE
B11 T26 A20 AC18
VSS[011] VSS[092] VCC[009] VCC[76]
B13 U3 B7 AD7
VSS[012] VSS[093] VCC[010] VCC[77]
B16 U6 B9 AD9
VSS[013] VSS[094] VCC[011] VCC[78]
B19 U21 B10 AD10
VSS[014] VSS[095] VCC_CORE VCC[012] VCC[79]
B21 U24 B12 AD12
VSS[015] VSS[096] VCC[013] VCC[80] C350 C419 C371 C398
B24 V2 B14 AD14
VSS[016] VSS[097] VCC[014] VCC[81] 22U-6.3V_8 22U-6.3V_8 22U-6.3V_8 22U-6.3V_8
C5 V5 B15 AD15
VSS[017] VSS[098] VCC[015] VCC[82]
C8 V22 B17 AD17
VSS[018] VSS[099] VCC[016] VCC[83]
C11 V25 B18 AD18
VSS[019] VSS[100] C370 C340 C402 C420 VCC[017] VCC[84]
C14 W1 B20 AE9
VSS[020] VSS[101] 22U-6.3V_8 22U-6.3V_8 VCC[018] VCC[85]
C16 W4 C9 AE10
VSS[021] VSS[102] 22U-6.3V_8 22U-6.3V_8 VCC[019] VCC[86]
C19 W23 C10 AE12
VSS[022] VSS[103] VCC[020] VCC[87]
C2 W26 C12 AE13
VSS[023] VSS[104] VCC[021] VCC[88]
C22 Y3 C13 AE15
VSS[024] VSS[105] VCC[022] VCC[89]
C25 Y6 C15 AE17
VSS[025] VSS[106] C363 C359 C423 C442 VCC[023] VCC[90]
D1 Y21 C17 AE18
VSS[026] VSS[107] 22U-6.3V_8 22U-6.3V_8 22U-6.3V_8 22U-6.3V_8 VCC[024] VCC[91]
D4 Y24 C18 AE20
VSS[027] VSS[108] VCC[025] VCC[92]
D8 AA2 D9 AF9
VSS[028] VSS[109] VCC[026] VCC[93]
D11 AA5 D10 AF10
VSS[029] VSS[110] VCC[027] VCC[94]
D13 AA8 D12 AF12
VSS[030] VSS[111] VCC[028] VCC[95] +1.05V
D16 AA11 D14 AF14
C VSS[031] VSS[112] C427 C339 C421 C385 VCC[029] VCC[96] C
D19 AA14 D15 AF15
VSS[032] VSS[113] 22U-6.3V_8 22U-6.3V_8 22U-6.3V_8 22U-6.3V_8 VCC[030] VCC[97]
D23 AA16 D17 AF17
VSS[033] VSS[114] VCC[031] VCC[98]
D26 AA19 D18 AF18
VSS[034] VSS[115] VCC[032] VCC[99] +1.05V C449 C361 C360 C448 C450 C362
E3 AA22 E7 AF20
VSS[035] VSS[116] VCC[033] VCC[100] .1U-10V_4 .1U-10V_4 .1U-10V_4
E6 AA25 E9
VSS[036] VSS[117] VCC[034] .1U-10V_4 .1U-10V_4 .1U-10V_4
E8 AB1 E10 V6
VSS[037] VSS[118] C341 C389 C378 C410 VCC[035] VCCP[01] C781
E11 AB4 E12 G21
VSS[038] VSS[119] 22U-6.3V_8 22U-6.3V_8 22U-6.3V_8 22U-6.3V_8 VCC[036] VCCP[02]
E14 AB8 E13 J6
VSS[039] VSS[120] VCC[037] VCCP[03]
330U-2.5V_7343
E16 AB11 E15 K6 + near CPU B26
VSS[040] VSS[121] VCC[038] VCCP[04]
E19 AB13 E17 M6
VSS[041] VSS[122] VCC[039] VCCP[05]
E21 AB16 E18 J21
VSS[042] VSS[123] VCC[040] VCCP[06] +1.5V
E24 AB19 E20 K21
VSS[043] VSS[124] C386 C349 C401 C388 VCC[041] VCCP[07]
F5 AB23 F7 M21
VSS[044] VSS[125] 22U-6.3V_8 22U-6.3V_8 22U-6.3V_8 22U-6.3V_8 VCC[042] VCCP[08]
F8 AB26 F9 N21
VSS[045] VSS[126] VCC[043] VCCP[09]
F11 AC3 F10 N6
VSS[046] VSS[127] VCC[044] VCCP[10]
F13 AC6 F12 R21
VSS[047] VSS[128] VCC[045] VCCP[11]
F16 AC8 F14 R6
VSS[048] VSS[129] VCC[046] VCCP[12] C472 C475
F19 AC11 F15 T21
VSS[049] VSS[130] C409 C399 C422 C372 VCC[047] VCCP[13]
F2 AC14 F17 T6
VSS[050] VSS[131] 22U-6.3V_8 22U-6.3V_8 22U-6.3V_8 22U-6.3V_8 VCC[048] VCCP[14] .01U-16V_4 10U/X5R-6.3V_8
F22 AC16 F18 V21
VSS[051] VSS[132] VCC[049] VCCP[15] +1.5V
F25 AC19 F20 W21
VSS[052] VSS[133] VCC[050] VCCP[16]
G4 AC21 AA7
B VSS[053] VSS[134] VCC[051] B
G1 AC24 AA9 B26
VSS[054] VSS[135] VCC[052] VCCA
G23
VSS[055] VSS[136]
AD2 AA10
VCC[053]
VCCA (1.5v) is a power source required by the PLL clock
G26 AD5 C400 C368 C373 C428 AA12
VSS[056] VSS[137] 22U-6.3V_8 22U-6.3V_8 22U-6.3V_8 22U-6.3V_8 VCC[054]
H3 AD8 AA13 AD6 H_VID0 41
VSS[057] VSS[138] VCC[055] VID[0] VCC_CORE
H6 AD11 AA15 AF5 H_VID1 41
VSS[058] VSS[139] VCC[056] VID[1]
H21 AD13 AA17 AE5 H_VID2 41
VSS[059] VSS[140] VCC[057] VID[2]
H24 AD16 AA18 AF4 H_VID3 41
VSS[060] VSS[141] VCC[058] VID[3]
J2 AD19 AA20 AE3 H_VID4 41
VSS[061] VSS[142] C443 C375 C390 C369 VCC[059] VID[4]
J5 AD22 AB9 AF2 H_VID5 41
VSS[062] VSS[143] 22U-6.3V_8 22U-6.3V_8 22U-6.3V_8 22U-6.3V_8 VCC[060] VID[5]
J22 AD25 AC10 AE2 H_VID6 41
VSS[063] VSS[144] VCC[061] VID[6] R221
J25 AE1 AB10
VSS[064] VSS[145] VCC[062] *100/F_4
K1 AE4 AB12
VSS[065] VSS[146] VCC[063]
K4 AE8 AB14
VSS[066] VSS[147] VCC[064]
K23
VSS[067] VSS[148]
AE11 change to 0805 AB15
VCC[065]VCCSENSE
AF7 VCCSENSE 41
K26 AE14 AB17
VSS[068] VSS[149] VCC[066]
L3 AE16 AB18 AE7 VSSSENSE 41
VSS[069] VSS[150] VCC[067]VSSSENSE R220 *100/F_4
L6 AE19
VSS[070] VSS[151] PZ47823-2743-42
L21 AE23
VSS[071] VSS[152]
L24
VSS[072] VSS[153]
AE26 A1A:Reversed VCCSENSE/VSSSENSE on
M2 AF3 Vcore side
VSS[073] VSS[154]
M5 AF6
VSS[074] VSS[155]
M22 AF8
A VSS[075] VSS[156] A
M25 AF11
VSS[076] VSS[157]
N1 AF13
N4
VSS[077] VSS[158]
VSS[078] VSS[159]
AF16 PROJECT : ZC1
N23 AF19
VSS[079] VSS[160]
N26 AF21
P3
VSS[080] VSS[161]
VSS[081] VSS[162]
AF24 Quanta Computer Inc.
PZ47823-2743-42 Size Document Number Rev
CPU(2 OF 2 ) 1A

5 4 3 2 1
5 4 3 2 1
+3V
+3V
Q17 R193
2
RHU002N06 200_4
D
25mils D
19,39,46 MBCLK 3 1 LM86VCC
C287
R192 R196 .1U-10V_4
+3V 10K_4 10K_4
U12
2
LM86__SMC 8 1 10/20mils
Q18 SCLK VCC H_THERMDA
H_THERMDA 3
19,39,46 MBDATA 3 1 LM86_SMD 7 2 C305
RHU002N06 SDA DXP 2200P-50V_4
1 2 6 3 H_THERMDC
ALERT# DXN H_THERMDC 3
16 THERM_ALERT# R205 *0_4
THERM_OVER# 4 5
OVERT# GND
+3V R776 10K_4
MAX6657/GMT-781
D2B:Add R776 for CPU thermal sensor ADDRESS: 98H
C C
+5V
D2B:Add R545 for VGA thermal sensor CPU FAN
1 2 R81 +3V
19 VGA_THERM#
1
R545 0_4
Q13 10K_4
THERM_OVER# 1 2 G993_VEN R547
R529 0_4 2 THERM_OVER#
*AO3403 10K_4
A1A:Change FAN CONN footprint
U38 39 FANSIG CN28
B B
2 3 TH_FAN_POWER
+5V
3
VIN VO 1 4
GND 5 30 MIL 2
R80 *0_4 G993_VEN 1 6 C112 C732
FON# GND 3 5
GND 7
4 8 .01U-16V_4 *.01U-16V_4 FAN_CON
39 CPUFAN# VSET GND
G995P1U
A1A:Remove FANSIG capacitor

A1A:Change FAN driver to G995
F3B:Add R793,C974 to prevent FAN noise
A PROJECT : ZC1 A

Thermal Sensor,FAN 1A
5 4 3 2 1
om
l.c
ai
tm
ho
f@
in
xa
he
5 4 3 2 1
H_XRCOMP
3 H_D#[63:0] H_A#[31:3] 3
U44A
10 mils/20mils H_D#0 F1 H9 H_A#3
R280 H_D#1 H_D#_0 H_A#_3 H_A#4 +1.05V
J1 C9 +1.05V 2,3,4,8,9,10,14,17,44
24.9/F_4 H_D#2 H_D#_1 H_A#_4 H_A#5
H1 E11
H_D#3 H_D#_2 H_A#_5 H_A#6
J6 G11
H_D#4 H_D#_3 H_A#_6 H_A#7
H3 F11
H_D#5 H_D#_4 H_A#_7 H_A#8
K2 G12
H_D#6 H_D#_5 H_A#_8 H_A#9
G1 F9
H_D#7 H_D#_6 H_A#_9 H_A#10
G2 H11
D H_D#8 H_D#_7 H_A#_10 H_A#11 D
K9 J12
+1.05V H_D#9 H_D#_8 H_A#_11 H_A#12
K1 G14
H_D#10 H_D#_9 H_A#_12 H_A#13
K7 D9
H_D#11 H_D#_10 H_A#_13 H_A#14
J8 J14
H_D#12 H_D#_11 H_A#_14 H_A#15
H4 H13
R278 H_D#13 H_D#_12 H_A#_15 H_A#16
J3 J15
54.9/F_4 H_D#14 H_D#_13 H_A#_16 H_A#17
K11 F14
H_D#15 H_D#_14 H_A#_17 H_A#18
G4 D12
H_XSCOMP H_D#16 H_D#_15 H_A#_18 H_A#19
T10 A11
H_D#17 H_D#_16 H_A#_19 H_A#20
W11 C11
H_D#18 H_D#_17 H_A#_20 H_A#21
T3 A12
H_D#19 H_D#_18 H_A#_21 H_A#22
U7 A13
+1.05V H_D#20 H_D#_19 H_A#_22 H_A#23
U9 E13
H_D#21 H_D#_20 H_A#_23 H_A#24
U11 G13
H_D#22 H_D#_21 H_A#_24 H_A#25
T11 F12
H_D#23 H_D#_22 H_A#_25 H_A#26
W9 B12
H_D#24 H_D#_23 H_A#_26 H_A#27
T1 B14
R272 H_D#25 H_D#_24 H_A#_27 H_A#28
T8 C12
221/F_4 H_D#26 H_D#_25 H_A#_28 H_A#29 +1.05V
T4 A14
H_D#27 H_D#_26 H_A#_29 H_A#30
10 mils/20mils W7
H_D#_27 H_A#_30
C14
H_XSWING H_D#28 U5 D14 H_A#31 H_VREF :10 mils/20 mils space
H_D#29 H_D#_28 H_A#_31
T9 Place within 100 mils
H_D#30 H_D#_29 R261
W6 E8 H_ADS# 3
H_D#31 H_D#_30 H_ADS# 100/F_4
C T5 B9 H_ADSTB0# 3 C
R277 C484 H_D#32 H_D#_31 H_ADSTB#_0
AB7 C13 H_ADSTB1# 3
100/F_4 H_D#33 H_D#_32 H_ADSTB#_1 H_VREF
AA9 J13
.1U-10V_4 H_D#34 H_D#_33 H_VREF_0
W4 C6 H_BNR# 3
H_D#35 H_D#_34 H_BNR#
W3 F6 H_BPRI# 3
HOST
H_D#36 H_D#_35 H_BPRI# C467 R257
Y3 C7 H_BREQ#0 3
H_D#37 H_D#_36 H_BREQ#0 R561 0_4 .1U-10V_4 200/F_4
Y7 B7 H_CPURST# 3
H_D#38 H_D#_37 H_CPURST#
W5 A7 H_DBSY# 3
H_D#39 H_D#_38 H_DBSY#
Y10 C3 H_DEFER# 3
+1.05V H_D#40 H_D#_39 H_DEFER#
AB8 J9 H_DPWR# 3
H_D#41 H_D#_40 H_DPWR#
W2 H8 H_DRDY# 3
H_D#42 H_D#_41 H_DRDY# H_VREF
AA4 K13
H_D#43 H_D#_42 H_VREF_1
AA7 H_DINV#[3:0] 3
R565 H_D#44 H_D#_43 H_DINV#0
AA2 J7
54.9/F_4 H_D#45 H_D#_44 H_DINV#_0 H_DINV#1 C469
AA6 W8
H_D#46 H_D#_45 H_DINV#_1 H_DINV#2 .1U-10V_4
AA10 U3
H_YSCOMP H_D#47 H_D#_46 H_DINV#_2 H_DINV#3
Y8 AB10
H_D#48 H_D#_47 H_DINV#_3
AA1 H_DSTBN#[3:0] 3
H_D#49 H_D#_48 H_DSTBN#0
AB4 K4
H_D#50 H_D#_49 H_DSTBN#_0 H_DSTBN#1
AC9 T7
+1.05V H_D#51 H_D#_50 H_DSTBN#_1 H_DSTBN#2
AB11 Y5
H_D#52 H_D#_51 H_DSTBN#_2 H_DSTBN#3
AC11 AC4
H_D#53 H_D#_52 H_DSTBN#_3
AB3 H_DSTBP#[3:0] 3
H_D#54 H_D#_53 H_DSTBP#0
AC2 K3
H_D#55 H_D#_54 H_DSTBP#_0 H_DSTBP#1
B AD1 T6 B
R566 H_D#56 H_D#_55 H_DSTBP#_1 H_DSTBP#2
AD9 AA5
221/F_4 H_D#57 H_D#_56 H_DSTBP#_2 H_DSTBP#3
10 mils/20mils AC1
H_D#_57 H_DSTBP#_3
AC5
H_D#58 AD7
H_YSWING H_D#59 H_D#_58
AC6
H_D#60 H_D#_59
AB5 D3 H_HIT# 3
H_D#61 H_D#_60 H_HIT#
AD10 D4 H_HITM# 3
H_D#62 H_D#_61 H_HITM#
AD4 B3 H_LOCK# 3
R567 C792 H_D#63 H_D#_62 H_LOCK#
AC8
100/F_4 H_D#_63
.1U-10V_4 H_XRCOMP E1
H_XSCOMP H_XRCOMP H_REQ#0 H_REQ#[4:0] 3
E2 D8
H_XSWING H_XSCOMP H_REQ#_0 H_REQ#1
E4 G8
H_XSWING H_REQ#_1 H_REQ#2
B8
H_YRCOMP H_REQ#_2 H_REQ#3
Y1 F8
H_YSCOMP H_YRCOMP H_REQ#_3 H_REQ#4
10 mils/20mils U1
H_YSCOMP H_REQ#_4
A8
H_YRCOMP H_YSWING W1
H_YSWING H_RS#[2:0] 3
T65 B4 H_RS#0
H_RS#_0 H_RS#1
2 CLK_MCH_BCLK AG2 E6
R568 H_CLKIN H_RS#_1 H_RS#2
2 CLK_MCH_BCLK# AG1 D6
24.9/F_4 T66 H_CLKIN# H_RS#_2
E3 H_CPUSLP# 3,14
H_SLPCPU#
E7 H_TRDY# 3
H_TRDY#
Short Stub < 100mils
A Calistoga(945PM) A
extract from same point
PROJECT : ZC1
GMCH HOST(1 OF 6 ) 1A

5 4 3 2 1
5 4 3 2 1
13 M_B_DQ[63:0]
U44E
M_B_DQ0 AK39
D M_B_DQ1 SB_DQ0 D
AJ37 AT24 M_B_BS#0 12,13
M_B_DQ2 SB_DQ1 SB_BS_0
AP39 AV23 M_B_BS#1 12,13
AR41 AY28 M_B_BS#2 12,13
AJ38 M_B_CAS# 12,13
M_B_DQ5 SB_DQ4
AK38 AR24 M_B_DM[7:0] 13
M_B_DQ6 SB_DQ5 SB_CAS# M_B_DM0
AN41 AK36
M_B_DQ7 SB_DQ6 SB_DM_0 M_B_DM1
AP41 AR38
AT40 AT36
AV41 BA31
AU38 AL17
AV38 AH8
13 M_A_DQ[63:0] AP38 BA5
U44D M_B_DQ13 SB_DQ12 SB_DM_6 M_B_DM7
AR40 AN4
M_A_DQ0 M_A_BS#0 M_B_DQ14 SB_DQ13 SB_DM_7
AJ35 AU12 M_A_BS#0 12,13 AW38 M_B_DQS[7:0] 13
M_A_DQ1 SA_DQ0 SA_BS_0 M_A_BS#1 M_B_DQ15 SB_DQ14 M_B_DQS0
AJ34 AV14 M_A_BS#1 12,13 AY38 AM39
SA_DQ1 SA_BS_1 SB_DQ15 SB_DQS_0
B
M_A_DQ2 AM31 BA20 M_A_BS#2 M_B_DQ16 BA38 AT39 M_B_DQS1
SA_DQ2 SA_BS_2 M_A_BS#2 12,13 SB_DQ16 SB_DQS_1
M_A_DQ3 AM33 M_B_DQ17 AV36 AU35 M_B_DQS2
M_A_DQ4 SA_DQ3 M_A_CAS# M_A_CAS# 12,13 M_B_DQ18 SB_DQ17 SB_DQS_2 M_B_DQS3
AJ36 AY13 M_A_DM[7:0] 13 AR36 AR29
M_A_DQ5 SA_DQ4 SA_CAS# M_A_DM0 M_B_DQ19 SB_DQ18 SB_DQS_3 M_B_DQS4
AK35 AJ33 AP36 AR16
M_A_DQ6 SA_DQ5 SA_DM_0 M_A_DM1 M_B_DQ20 SB_DQ19 SB_DQS_4 M_B_DQS5
AJ32 AM35 BA36 AR10
SA_DQ6 SA_DM_1 SB_DQ20 SB_DQS_5
MEMORY
M_A_DQ7 AH31 AL26 M_A_DM2 M_B_DQ21 AU36 AR7 M_B_DQS6
M_A_DQ8 SA_DQ7 SA_DM_2 M_A_DM3 M_B_DQ22 SB_DQ21 SB_DQS_6 M_B_DQS7
AN35 AN22 AP35 AN5 M_B_DQS#[7:0] 13
M_A_DQ9 SA_DQ8 SA_DM_3 M_A_DM4 M_B_DQ23 SB_DQ22 SB_DQS_7 M_B_DQS#0
AP33 AM14 AP34 AM40
M_A_DQ10 SA_DQ9 SA_DM_4 M_A_DM5 M_B_DQ24 SB_DQ23 SB_DQS#_0 M_B_DQS#1
C AR31 AL9 AY33 AU39 C
AP31 AR3 BA33 AT35
AN38 AH4 AT31 AP29
M_A_DQ13 SA_DQ12 SA_DM_7 M_B_DQ27 SB_DQ26 SB_DQS#_3 M_B_DQS#4
AM36 M_A_DQS[7:0] 13 AU29 AP16
M_A_DQ14 SA_DQ13 M_A_DQS0 M_B_DQ28 SB_DQ27 SB_DQS#_4 M_B_DQS#5
AM34 AK33 AU31 AT10
SA_DQ14 SA_DQS_0 SB_DQ28 SB_DQS#_5
M_A_DQ15
M_A_DQ16
AN33
AK26
SA_DQ15
SA_DQ16
A SA_DQS_1
SA_DQS_2
AT33
AN28
M_A_DQS1
M_A_DQS2
M_B_DQ29
M_B_DQ30
AW31
AV29
SB_DQ29
SB_DQ30
SB_DQS#_6
SB_DQS#_7
AT7
AP5
M_B_DQS#6
M_B_DQS#7
M_A_DQ17 AL27 AM22 M_A_DQS3 M_B_DQ31 AW29
M_A_DQ18 SA_DQ17 SA_DQS_3 M_A_DQS4 M_B_DQ32 SB_DQ31 M_B_A0 M_B_A[13:0] 12,13
AM26 AN12 AM19 AY23
M_A_DQ19 SA_DQ18 SA_DQS_4 M_A_DQS5 M_B_DQ33 SB_DQ32 SB_MA_0 M_B_A1
AN24 AN8 AL19 AW24
SYSTEM
SA_DQ19 SA_DQS_5 SB_DQ33 SB_MA_1
MEMORY
M_A_DQ20 AK28 AP3 M_A_DQS6 M_B_DQ34 AP14 AY24 M_B_A2
M_A_DQ21 SA_DQ20 SA_DQS_6 M_A_DQS7 M_B_DQ35 SB_DQ34 SB_MA_2 M_B_A3
AL28 AG5 M_A_DQS#[7:0] 13 AN14 AR28
M_A_DQ22 SA_DQ21 SA_DQS_7 M_A_DQS#0 M_B_DQ36 SB_DQ35 SB_MA_3 M_B_A4
AM24 AK32 AN17 AT27
M_A_DQ23 SA_DQ22 SA_DQS#_0 M_A_DQS#1 M_B_DQ37 SB_DQ36 SB_MA_4 M_B_A5
AP26 AU33 AM16 AT28
AP23 AN27 AP15 AU27
AL22 AM21 AL15 AV28
AP21 AM12 AJ11 AV27
AN20 AL8 AH10 AW27
AL23 AN3 AJ9 AV24
AP24 AH5 AN10 BA27
M_A_DQ30 SA_DQ29 SA_DQS#_7 M_B_DQ44 SB_DQ43 SB_MA_11 M_B_A12
AP20 M_A_A[13:0] 12,13 AK13 AY27
M_A_DQ31 SA_DQ30 M_A_A0 M_B_DQ45 SB_DQ44 SB_MA_12 M_B_A13
AT21 AY16 AH11 AR23
SA_DQ31 SA_MA_0 SB_DQ45 SB_MA_13
DDR
M_A_DQ32 AR12 AU14 M_A_A1 M_B_DQ46 AK10
SYSTEM
M_A_DQ33 SA_DQ32 SA_MA_1 M_A_A2 M_B_DQ47 SB_DQ46

AR14 AW16 AJ8 AU23 M_B_RAS# 12,13
M_A_DQ34 SA_DQ33 SA_MA_2 M_A_A3 M_B_DQ48 SB_DQ47 SB_RAS# TP_MB_RCVENIN#
B AP13 BA16 BA10 AK16 B
M_A_DQ35 SA_DQ34 SA_MA_3 M_A_A4 M_B_DQ49 SB_DQ48 SB_RCVENIN# TP_MB_RCVENOUT# T52
AP12 BA17 AW10 AK18
M_A_DQ36 SA_DQ35 SA_MA_4 M_A_A5 M_B_DQ50 SB_DQ49 SB_RCVENOUT# T48
AT13 AU16 BA4 AR27 M_B_WE# 12,13
M_A_DQ37 SA_DQ36 SA_MA_5 M_A_A6 M_B_DQ51 SB_DQ50 SB_WE#
AT12 AV17 AW4
AL14 AU17 AY10
AL12 AW17 AY9
AK9 AT16 AW5
AN7 AU13 AY5
AK8 AT17 AV4
AK7 AV20 AR5
AP9 AV12 AK4
SA_DQ44 SA_MA_13 SB_DQ58
DDR
M_A_DQ45 AN9 M_B_DQ59 AK3

M_A_DQ46 SA_DQ45 M_B_DQ60 SB_DQ59
AT5 AW14 M_A_RAS# 12,13 AT4
M_A_DQ47 SA_DQ46 SA_RAS# TP_MA_RCVENIN# M_B_DQ61 SB_DQ60
AL5 AK23 AK5
M_A_DQ48 SA_DQ47 SA_RCVENIN# TP_MA_RCVENOUT# T45 M_B_DQ62 SB_DQ61
AY2 AK24 T44 AJ5
M_A_DQ49 SA_DQ48 SA_RCVENOUT# M_B_DQ63 SB_DQ62
AW2 AY14 M_A_WE# 12,13 AJ3
M_A_DQ50 SA_DQ49 SA_WE# SB_DQ63
AP1
M_A_DQ51 SA_DQ50 Calistoga(945PM)
AN2
M_A_DQ52 SA_DQ51
AV2
M_A_DQ53 SA_DQ52
AT3
M_A_DQ54 SA_DQ53
AN1
M_A_DQ55 SA_DQ54
AL2
M_A_DQ56 SA_DQ55
AG7
M_A_DQ57 SA_DQ56
AF9
A M_A_DQ58 SA_DQ57 A
AG4
M_A_DQ59 SA_DQ58
AF6
M_A_DQ60 SA_DQ59
AG9
M_A_DQ61 AH6
SA_DQ60
SA_DQ61
PROJECT : ZC1
M_A_DQ62 AF4
M_A_DQ63 SA_DQ62
AF8
SA_DQ63 Quanta Computer Inc.
Calistoga(945PM)
GMCH DDR(2 OF 6 ) 1A

5 4 3 2 1
om
l.c
ai
tm
ho
f@
in
xa
he
5 4 3 2 1
U44B +V1.5_PCIE
+V1.5_PCIE 10
T36 CLK_MCH_OE# H32 +3V
RSVD_0 +3V 2,5,10,13,14,15,16,17,18,19,20,24,25,26,27,29,30,31,32,33,34,35,36,37,38,39,40,41,42,44
T37 MCH_RSVD_1 T32 AY35 SMDDR_VREF SMDDR_VREF 13,43 20mils/20mils space
RSVD_1 SM_CK_0 M_CLK_DDR0 13 +V1.5_PCIE
T35 MCH_RSVD_2 R32 AR1 +1.8VSUS
RSVD_2 SM_CK_1 M_CLK_DDR1 13 +1.8VSUS 9,13,20,42,43
T64 MCH_RSVD_3 F3 AW7
RSVD_3 SM_CK_2 M_CLK_DDR2 13
T61 MCH_RSVD_4 F7 AW40 U44C
RSVD_4 SM_CK_3 M_CLK_DDR3 13
RSVD
T54 MCH_RSVD_5 AG11 D32 D40 EXP_A_COMPX R218 24.9/F_4
T57 MCH_RSVD_6 RSVD_5 L_BKLTCTL EXP_A_COMPI
AF11 AW35 M_CLK_DDR#0 13 J30 D38
T62 MCH_RSVD_7 RSVD_6 SM_CK#_0 L_BKLTEN EXP_A_COMPO
H7 AT1 M_CLK_DDR#1 13 H30 PEG_RXN[15:0] 18
T46 MCH_RSVD_8 RSVD_7 SM_CK#_1 L_CLKCTLA PEG_RXN0
J19 AY7 M_CLK_DDR#2 13 H29 F34
T40 TV_DCONSEL0 RSVD_8 SM_CK#_2 If the LVDS interface is L_CLKCTLB EXP_A_RXN_0 PEG_RXN1
K30 AY40 M_CLK_DDR#3 13 G26 G38
T38 TV_DCONSEL1 RSVD_9 SM_CK#_3 L_DDC_CLK EXP_A_RXN_1 PEG_RXN2
J29 not implemented, all G25 H34
T126 MCH_RSVD_11 RSVD_10 L_DDC_DATA EXP_A_RXN_2 PEG_RXN3
A41 AU20 M_CKE0 12,13 signals associated with B38 J38
T132 MCH_RSVD_12 RSVD_11 SM_CKE_0 L_IBG EXP_A_RXN_3 PEG_RXN4
A35 AT20 M_CKE1 12,13 C35 L34
D
T136 MCH_RSVD_13 A34
RSVD_12 SM_CKE_1
BA29
the interface can be left F32
L_VBG EXP_A_RXN_4
M38 PEG_RXN5 D
RSVD_13 SM_CKE_2 M_CKE2 12,13 as No Connects L_VDDEN EXP_A_RXN_5
T39 MCH_RSVD_14 D28 AY29 C33 N34 PEG_RXN6
MCH_RSVD_15 RSVD_14 SM_CKE_3 M_CKE3 12,13 L_VREFH EXP_A_RXN_6 PEG_RXN7
T43 D27 C32 P38
RSVD_15 L_VREFL EXP_A_RXN_7 PEG_RXN8
AW13 M_CS#0 12,13 R34
SM_CS#_0 EXP_A_RXN_8 PEG_RXN9
AW12 M_CS#1 12,13 A33 T38
SM_CS#_1 LA_CLK# EXP_A_RXN_9 PEG_RXN10
K16
MUXING
2 MCH_BSEL0 AY21 M_CS#2 12,13 A32 V34
CFG_0 SM_CS#_2 15mils/15mils LA_CLK EXP_A_RXN_10 PEG_RXN11
2 MCH_BSEL1 K18 AW21 M_CS#3 12,13 E27 W38
CFG_1 SM_CS#_3 LB_CLK# EXP_A_RXN_11 PEG_RXN12
2 MCH_BSEL2 J18 E26 Y34
MCH_CFG_3 CFG_2 M_OCDCOMP_0 LB_CLK EXP_A_RXN_12 PEG_RXN13
F18 AL20 AA38
CFG_3 SM_OCDCOMP_0 EXP_A_RXN_13
LVDS
T47 MCH_CFG_4 E15 AF10 M_OCDCOMP_1 C37 AB34 PEG_RXN14
T56 MCH_CFG_5 CFG_4 SM_OCDCOMP_1 LA_DATA#_0 EXP_A_RXN_14 PEG_RXN15
F15 B35 AC38
MCH_CFG_6 CFG_5 LA_DATA#_1 EXP_A_RXN_15
E18 BA13 M_ODT0 12,13 A37 PEG_RXP[15:0] 18
MCH_CFG_7 CFG_6 SM_ODT_0 R259 R242 LA_DATA#_2 PEG_RXP0
D19 BA12 M_ODT1 12,13 D34
MCH_CFG_8 CFG_7 SM_ODT_1 +1.8VSUS EXP_A_RXP_0 PEG_RXP1
D16 AY20 M_ODT2 12,13 F38
CFG_8 SM_ODT_2 EXP_A_RXP_1
CFG
T50 MCH_CFG_9 *40.2/F_4 *40.2/F_4 PEG_RXP2
GRAPHICS
G16 AU21 M_ODT3 12,13 G34
MCH_CFG_10 CFG_9 SM_ODT_3 EXP_A_RXP_2 PEG_RXP3
E16 B37 H38
DDR
MCH_CFG_11 CFG_10 M_RCOMP# Layout as short as passable LA_DATA_0 EXP_A_RXP_3 PEG_RXP4
D15 AV9 B34 J34
MCH_CFG_12 CFG_11 SM_RCOMP# M_RCOMP NC from WW45 LA_DATA_1 EXP_A_RXP_4 PEG_RXP5
G15 AT9 A36 L38
MCH_CFG_13 CFG_12 SM_RCOMP R262 LA_DATA_2 EXP_A_RXP_5 PEG_RXP6
K15 M34
MCH_CFG_14 CFG_13 EXP_A_RXP_6
C15 AK1 SMDDR_VREF_MCH R569 0_6 SMDDR_VREF 80.6/F_4 N38 PEG_RXP7
T55 MCH_CFG_15 CFG_14 SM_VREF_0 EXP_A_RXP_7 PEG_RXP8
H16 AK41 G30 P34
T49 MCH_CFG_16 CFG_15 SM_VREF_1 15mils/10mils M_RCOMP# LB_DATA#_0 EXP_A_RXP_8 PEG_RXP9
G18 D30 R38
MCH_CFG_17 CFG_16 LB_DATA#_1 EXP_A_RXP_9 PEG_RXP10
H15 F29 T34
T51 MCH_CFG_18 CFG_17 M_RCOMP LB_DATA#_2 EXP_A_RXP_10 PEG_RXP11
J25 AF33 CLK_PCIE_3GPLL# 2 V38
MCH_CFG_19 CFG_18 G_CLKIN# EXP_A_RXP_11 PEG_RXP12
A1A:Change PM_EXTTS#1 K27
CFG_19 G_CLKIN
AG33 CLK_PCIE_3GPLL 2 EXP_A_RXP_12
W34
to DPRSLPVR MCH_CFG_20 J26 A27 Y38 PEG_RXP13
CLK
CFG_20 D_REFCLKIN# DREFCLK# 2 EXP_A_RXP_13
A26 F30 AA34 PEG_RXP14
D_REFCLKIN DREFCLK 2 LB_DATA_0 EXP_A_RXP_14
16 PM_BMBUSY# G28 C40 DREFSSCLK# T184 R263 D29 AB38 PEG_RXP15
PM_BMBUSY# D_REFSSCLKIN# LB_DATA_1 EXP_A_RXP_15
PCI-EXPRESS
13 PM_EXTTS#0 F25 D41 DREFSSCLK T185 80.6/F_4 F28
PM_EXTTS#_0 D_REFSSCLKIN LB_DATA_2
PM
C
16 DPRSLPVR R228 0_4 H26 F36 C_PEG_TXN0C743 EV@.1U-10V_4PEG_TXN0 C
PM_EXTTS#_1 DMI_TXN[3:0] 15 EXP_A_TXN_0
3,14 PM_THRMTRIP# G6 G40 C_PEG_TXN1C775 EV@.1U-10V_4PEG_TXN1
PM_THRMTRIP# DMI_TXN0 EXP_A_TXN_1 C_PEG_TXN2C745 EV@.1U-10V_4PEG_TXN2
3,16,41 DELAY_VR_PWRGOOD AH33 AE35 H36
RST IN# MCH AH34 PWROK DMI_RXN_0 DMI_TXN1 EXP_A_TXN_2 C_PEG_TXN3C777 EV@.1U-10V_4PEG_TXN3
15 PLT_RST-R# AF39 J40
R231 100/F_4 RSTIN# DMI_RXN_1 DMI_TXN2 R737 0_6 EXP_A_TXN_3 C_PEG_TXN4C747 EV@.1U-10V_4PEG_TXN4
AG35 +1.5V A16 L36
DMI_RXN_2 DMI_TXN3 TV_DACA_OUT EXP_A_TXN_4 C_PEG_TXN5C779 EV@.1U-10V_4PEG_TXN5
AH39 C18 M40
DMI_RXN_3 TV_DACB_OUT EXP_A_TXN_5
MISC
T41 SDVO_CTRLCLK H28 B1B:TV disable connect to +1.5V A19 N36 C_PEG_TXN6C749 EV@.1U-10V_4PEG_TXN6
SDVO_CTRLCLK TV_DACC_OUT EXP_A_TXN_6
TV
T42 SDVO_CTRLDATA H27 P40 C_PEG_TXN7C765 EV@.1U-10V_4PEG_TXN7
SDVO_CTRLDATA DMI_TXP0 EXP_A_TXN_7 C_PEG_TXN8C751 EV@.1U-10V_4PEG_TXN8
15 MCH_ICH_SYNC K28 AC35 J20 R36
LT_RESET# DMI_RXP_0 DMI_TXP1 TV_IREF EXP_A_TXN_8 C_PEG_TXN9C767 EV@.1U-10V_4PEG_TXN9
AE39 B16 T40
DMI_RXP_1 DMI_TXP2 TV_IRTNA EXP_A_TXN_9 C_PEG_TXN10
C753 EV@.1U-10V_4PEG_TXN10
AF35 B18 V36
TP_MCH_NC0 DMI_RXP_2 DMI_TXP3 TV_IRTNB EXP_A_TXN_10 C_PEG_TXN11
T150 D1 AG39 DMI_TXP[3:0] 15 B19 W40
TP_MCH_NC1 NC0 DMI_RXP_3 TV_IRTNC EXP_A_TXN_11 C_PEG_TXN12
T123 C41 DMI_RXN[3:0] 15 Y36
TP_MCH_NC2 NC1 EXP_A_TXN_12 C_PEG_TXN13
T149 C1 AA40
TP_MCH_NC3 NC2 EXP_A_TXN_13
T135 BA41 AE37 DMI_RXN0 AB36 C_PEG_TXN14
TP_MCH_NC4 NC3 DMI_TXN_0 EXP_A_TXN_14
T134 BA40 AF41 DMI_RXN1 B1B:CRT disable connect to GMCH VCC Core AC40 C_PEG_TXN15
NC4 DMI_TXN_1 EXP_A_TXN_15
NC
T133 TP_MCH_NC5 BA39 AG37 DMI_RXN2

TP_MCH_NC6 NC5 DMI_TXN_2
T139 BA3 AH41 DMI_RXN3 +1.05V
R738 0_6 E23 D36 C_PEG_TXP0 C742 EV@.1U-10V_4PEG_TXP0
TP_MCH_NC7 NC6 DMI_TXN_3 CRT_BLUE EXP_A_TXP_0 C_PEG_TXP1 C774 EV@.1U-10V_4PEG_TXP1
T140 BA2 D23 F40
DMI
TP_MCH_NC8 NC7 CRT_BLUE# EXP_A_TXP_1 C_PEG_TXP2 C744 EV@.1U-10V_4PEG_TXP2

T143 BA1 C22 G36
NC8 CRT_GREEN EXP_A_TXP_2
VGA
T122 TP_MCH_NC9 B41 AC37 DMI_RXP0 B22 H40 C_PEG_TXP3 C776 EV@.1U-10V_4PEG_TXP3
TP_MCH_NC10 NC9 DMI_TXP_0 DMI_RXP1 CRT_GREEN# EXP_A_TXP_3 C_PEG_TXP4 C746 EV@.1U-10V_4PEG_TXP4
T147 B2 AE41 A21 J36
TP_MCH_NC11 NC10 DMI_TXP_1 DMI_RXP2 CRT_RED EXP_A_TXP_4 C_PEG_TXP5 C778 EV@.1U-10V_4PEG_TXP5
T129 AY41 AF37 B21 L40
TP_MCH_NC12 NC11 DMI_TXP_2 DMI_RXP3 CRT_RED# EXP_A_TXP_5 C_PEG_TXP6 C748 EV@.1U-10V_4PEG_TXP6
T144 AY1 AG41 M36
TP_MCH_NC13 NC12 DMI_TXP_3 EXP_A_TXP_6 C_PEG_TXP7 C764 EV@.1U-10V_4PEG_TXP7
T130 AW41 N40
TP_MCH_NC14 NC13 EXP_A_TXP_7 C_PEG_TXP8 C750 EV@.1U-10V_4PEG_TXP8
T148 AW1 C26 P36
TP_MCH_NC15 NC14 CRT_DDC_CLK EXP_A_TXP_8 C_PEG_TXP9 C766 EV@.1U-10V_4PEG_TXP9
T128 A40 C25 R40
TP_MCH_NC16 NC15 CRT_DDC_DATA EXP_A_TXP_9 C_PEG_TXP10C752 EV@.1U-10V_4PEG_TXP10
T141 A4 DMI_RXP[3:0] 15 G23 T36
TP_MCH_NC17 NC16 CRT_HSYNC EXP_A_TXP_10 C_PEG_TXP11C768 EV@.1U-10V_4PEG_TXP11
T131 A39 J22 V40
+3V TP_MCH_NC18 NC17 CRT_IREF EXP_A_TXP_11 C_PEG_TXP12C754 EV@.1U-10V_4PEG_TXP12
B
T146 A3 H23 W36 B
NC18 CRT_VSYNC EXP_A_TXP_12 C_PEG_TXP13C770 EV@.1U-10V_4PEG_TXP13
Y40
EXP_A_TXP_13 C_PEG_TXP14C756 EV@.1U-10V_4PEG_TXP14
Calistoga(945PM) AA36
R226 10K/F_4 PM_EXTTS#0 EXP_A_TXP_14 C_PEG_TXP15C772 EV@.1U-10V_4PEG_TXP15
< 0.1" . 15mils/15mils space EXP_A_TXP_15
AB40
R224 *10K/F_4 DPRSLPVR A1A:don't stuff PM_EXTTS#1 pull high resistor use 1% R
Calistoga(945PM)
A1A:Reversed for SDVO CLK/DATA
R229 *4.7K_4SDVO_CTRLCLK
GMCH Strap pin If not implemented, the SDVO interface signals can be left as No Connect.
+2.5V
PEG_TXP0 PEG_TXP[15:0] 18
MCH_CFG_5 R248 *2.2K_4
R225 *4.7K_4SDVO_CTRLDATA PEG_TXP1
+2.5V
PEG_TXP2
PEG_TXP3 PEG_TXN[15:0] 18
MCH_CFG_6 R247 *2.2K_4
PEG_TXP4 PEG_TXN0
PULL LOW FOR DVO NOT PRESENT(INTERNAL PULLLOW IN 915GM) PEG_TXP5 PEG_TXN1
MCH_CFG_7 R245 *2.2K_4 PEG_TXP6 PEG_TXN2
1.MCH_CFG_5 Low = DMI X2, High=DMIX4 PEG_TXP7 PEG_TXN3
PEG_TXP8 PEG_TXN4
2.MCH_CFG_6 DDR : Low =Moby Dick, High= Calistoga (Default) MCH_CFG_9 R250 *2.2K_4 PEG_TXP9 PEG_TXN5
PEG_TXP10 PEG_TXN6
3.MCH_CFG_7 CPU Strap Low=RSVD, High=Mobile CPU PEG_TXP11 PEG_TXN7
MCH_CFG_10 R249 *2.2K_4 PEG_TXP12 PEG_TXN8
4.MCH_CFG_9 PCI Exp Graphics Lane: Low =Reserved,High=Mobility PEG_TXP13 PEG_TXN9
A1A:MCH_CFG_11->intel WW31 recommand remove PEG_TXP14 PEG_TXN10
5.MCH_CFG_10 Host PLL VCC Select: Low=Reserved, High=Mobility MCH_CFG_11 R253 *2.2K_4 PEG_TXP15 PEG_TXN11
A1A:intel WW12 recommand remove PEG_TXN12
6.MCH_CFG_11: PSB 4x CLK ENABLE Low=Reserved, High=Calistoga PEG_TXN13
MCH_CFG_12 R252 *2.2K_4 PEG_TXN14
7.MCH_CFG_16 FSB Dynmic ODT: Low=Dynamic ODT Disabled, PEG_TXN15
A High=Dynamic ODT Enabled. A
MCH_CFG_13 R251 *2.2K_4
8.MCH_CFG_18 VCC Select: LOW=1.05V, High=1.5V
9.MCH_CFG_19 DMI LANE Reversal: Low=Normal,High=LANES Reversed. MCH_CFG_16 R246 *2.2K_4 +3V
10.MCH_CFG_20 PCIE Backward interpoerability mode: Low= only

R227 PROJECT : ZC1
SDVO or PCIE x1 is operational (defaults) ,High=SDVO and MCH_CFG_18 R230 1K/F_4 CFG_RSVD_0_R
*0_4
PCIE x1 are operation simultaneously via the PEG port. Quanta Computer Inc.
MCH_CFG_19 R219 *1K/F_4 +3V
GMCH DMI/VEDIO(3 OF 6 ) 1A
MCH_CFG_20 R222 *1K/F_4 +3V Date: Tuesday, December 06, 2005 Sheet 8 of 46
5 4 3 2 1
5 4 3 2 1
1500mA U44G U44F

+1.05V C797 AA33 +1.05V AD27
VCC_0 VCC_NCTF0
W33 AC27 AE27
VCC_1 VCC_NCTF1 VSS_NCTF0
330U-2.5V_7343
P33
VCC_2
25mils + AB27
VCC_NCTF2 VSS_NCTF1
AE26
+ N33 C796 C468 C456 C480 C408 C453 C463 AA27 AE25
VCC_3 C335 .47U-10V_6 10U/X5R-6.3V_8 1U-16V_6 .1U-10V_4 VCC_NCTF3 VSS_NCTF2
L33 AU41 Y27 AE24
VCC_4 VCC_SM_0 VCC_NCTF4 VSS_NCTF3
J33 AT41 VCC_SM1 330U-2.5V_7343 .1U-10V_4 .1U-10V_4 W27 AE23
AA32 AM41 VCC_SM2 C336 .47U-10V_6 V27 AE22
VCC_6 VCC_SM_2 10U/X5R-6.3V_8 VCC_NCTF6 VSS_NCTF5
Y32 AU40 U27 AE21
W32 BA34 T27 AE20
V32 AY34 DDR2 1.8 V, 667 MTs(2 Channel) 3200mA R27 AE19
P32 AW34 AD26 AE18
VCC_10 VCC_SM_6 +1.8VSUS VCC_NCTF10 VSS_NCTF9
N32 AV34 AC26 AC17
D
M32
VCC_12 VCC_SM_8
AU34 120mils AB26
VCC_NCTF12 VSS_NCTF11
Y17 D
L32 AT34 AA26 U17
J32 AR34 Y26
VCC_14 VCC_SM_10 + C416 VCC_NCTF14
AA31 BA30 W26
VCC_15 VCC_SM_11 C376 C461 C432 C477 C406 C465 VCC_NCTF15
W31 AY30 V26
VCC_16 VCC_SM_12 330U-2.5V_7343 10U/X5R-6.3V_8 .47U-10V_6 .1U-10V_4 .1U-10V_4 .1U-10V_4 VCC_NCTF16 +1.5V_AUX
V31 AW30 U26
VCC_17 VCC_SM_13 10U/X5R-6.3V_8 VCC_NCTF17
T31 AV30 T26
VCC_18 VCC_SM_14 VCC_NCTF18
R31 AU30 R26 AG27
VCC_19 VCC_SM_15 VCC_NCTF19 VCCAUX_NCTF0
P31
VCC_20 VCC_SM_16
AT30 AD25
VCC_NCTF20 VCCAUX_NCTF1
AF27 100mils
N31 AR30 AC25 AG26
M31 AP30 AB25 AF26
AA30 AN30 AA25 AG25
Y30 AM30 Y25 AF25
W30 AM29 W25 AG24
V30 AL29 V25 AF24
U30 AK29 U25 AG23
T30 AJ29 T25 AF23
R30 AH29 R25 AG22
P30 AJ28 AD24 AF22
N30 AH28 AC24 AG21
M30 AJ27 AB24 AF21
L30 AH27 AA24 AG20
AA29 BA26 Y24 AF20
Y29 AY26 W24 AG19
W29 AW26 V24 AF19
V29 AV26 U24 R19
U29 AU26 T24 AG18
R29 AT26 R24 AF18
P29 AR26 AD23 R18
M29 AJ26 V23 AG17
C VCC_41 VCC_SM_37 VCC_NCTF41 VCCAUX_NCTF22 C
L29 AH26 U23 AF17
AB28 AJ25 T23 AE17
AA28 AH25 R23 AD17
Y28 AJ24 AD22 AB17
V28 AH24 V22 AA17
U28 BA23 U22 W17
T28 AJ23 T22 V17
VCC_48 VCC_SM_44 C433 VCC_NCTF48 VCCAUX_NCTF29
R28 BA22 R22 T17
VCC_49 VCC_SM_45 C377 .47U-10V_6 VCC_NCTF49 VCCAUX_NCTF30
P28 AY22 AD21 R17
N28
M28
VCC_50
VCC_51
VCC_52
VCC_SM_46
VCC_SM_47
VCC_SM_48
AW22
AV22
.47U-10V_6 V21
U21
VCC_NCTF50
VCC_NCTF51
VCC_NCTF52
NCTF VCCAUX_NCTF31
VCCAUX_NCTF32
VCCAUX_NCTF33
AG16
AF16
L28 AU22 T21 AE16
P27 AT22 R21 AD16
N27 AR22 AD20 AC16
M27 AP22 V20 AB16
L27 AK22 U20 AA16
P26 AJ22 T20 Y16
VCC_58 VCC_SM_54 +1.5V_AUX VCC_NCTF58 VCCAUX_NCTF39
N26 AK21 10 +1.5V_AUX R20 W16
L26 AK20 AD19 V16
VCC_60 VCC_SM_56 +1.05V VCC_NCTF60 VCCAUX_NCTF41
N25 BA19 2,3,4,6,8,10,14,17,44 +1.05V V19 U16
M25 AY19 U19 T16
VCC_62 VCC_SM_58 +1.8VSUS VCC_NCTF62 VCCAUX_NCTF43
L25 AW19 8,13,20,42,43 +1.8VSUS T19 R16
P24 AV19 AD18 AG15
N24 AU19 AC18 AF15
M24 AT19 AB18 AE15
AB23 AR19 AA18 AD15
AA23 AP19 Y18 AC15
Y23
P23
VCC_68
VCC_69
VCC_70
VCC VCC_SM_64
VCC_SM_65
VCC_SM_66
AK19
AJ19
W18
V18
VCC_NCTF68
VCC_NCTF69
VCC_NCTF70
VCCAUX_NCTF49
VCCAUX_NCTF50
VCCAUX_NCTF51
AB15
AA15
B N23 AJ18 U18 Y15 B
M23 AJ17 T18 W15
L23 AH17 V15
VCC_73 VCC_SM_69 VCCAUX_NCTF54
AC22 AJ16 U15
AB22 AH16 T15
Y22 BA15 R15
W22 AY15
VCC_77 VCC_SM_73 C478
P22 AW15 Calistoga(945PM)
VCC_78 VCC_SM_74 .47U-10V_6
N22 AV15
VCC_79 VCC_SM_75
M22 AU15
VCC_80 VCC_SM_76
L22 AT15
VCC_81 VCC_SM_77
AC21 AR15
VCC_82 VCC_SM_78
AA21 AJ15
VCC_83 VCC_SM_79
W21 AJ14
VCC_84 VCC_SM_80
N21 AJ13
VCC_85 VCC_SM_81
M21 AH13
VCC_86 VCC_SM_82
L21 AK12
VCC_87 VCC_SM_83
AC20 AJ12
VCC_88 VCC_SM_84
AB20 AH12
VCC_89 VCC_SM_85
Y20 AG12
VCC_90 VCC_SM_86
W20 AK11
VCC_91 VCC_SM_87
P20 BA8
VCC_92 VCC_SM_88
N20 AY8
VCC_93 VCC_SM_89
M20 AW8
VCC_94 VCC_SM_90
L20 AV8
VCC_95 VCC_SM_91
AB19 AT8
VCC_96 VCC_SM_92
AA19 AR8
VCC_97 VCC_SM_93
Y19 AP8
VCC_98 VCC_SM_94
N19 BA6
VCC_99 VCC_SM_95
M19 AY6
A
VCC_100 VCC_SM_96 A
L19 AW6
VCC_101 VCC_SM_97
N18 AV6
VCC_102 VCC_SM_98
M18 AT6
VCC_103 VCC_SM_99
L18 AR6
VCC_104 VCC_SM_100
P17 AP6
om
VCC_105 VCC_SM_101
N17 AN6
VCC_106 VCC_SM_102 PROJECT : ZC1
l.c
M17 AL6 25mils
VCC_107 VCC_SM_103
N16 AK6
ai
VCC_108 VCC_SM_104
tm
M16 AJ6
L16
VCC_109 VCC_SM_105
AV1 VCC_SM106 C487 .47U-10V_6 Quanta Computer Inc.
ho
VCC_110 VCC_SM_106
AJ1 VCC_SM107
f@
VCC_SM_107 C793 .47U-10V_6 Size Document Number Rev
GMCH PW & STRAP(4 OF 6) 1A
in
Calistoga(945PM)
25mils
xa
he
5 4 3 2 1
5 4 3 2 1
+2.5V +1.05V
+1.5V +V1.5_DPLLA
L66 When the LVDS interface is C379 C356 800mA
10uH_8 not implemented, the U44H
.1U-10V_410U/X5R-6.3V_8 H22 +1.05V
VCCTX_LVDS, VCCD_LVDS, and
1
VCCSYNC
AC14
+ C780 C397 VCCA_LVDS signals of the VTT_0
C30 AB14
.1U-10V_4 interface can be connected A1A:Change to VCC_TXLVDS0 VTT_1
B30 W14
470U-2.5V_7343 A1A:Change to 470UF VCC_TXLVDS1 VTT_2 C795 + C404 C391 C455 C365
to ground ground(LVDS disable) A30 V14
2
VCC_TXLVDS2 VTT_3
T14
+V1.5_DPLLB +2.5V 1500mA VTT_4 330U-2.5V_7343 2.2U-6.3V_6
+V1.5_PCIE AJ41 R14
L32 VCC3G0 VTT_5 4.7U-10V_8 .1U-10V_410U/X5R-6.3V_8
AB41 P14
10uH_8 VCC3G1 VTT_6
D Y41 N14 D
+V1.5_3GPLL C411 VCC3G2 VTT_7
V41 M14
1
.1U-10V_4 R41 VCC3G3 VTT_8 L14

+ C334 C337 A1A:Change to 470UF VCC3G4 VTT_9 +1.05V
N41 AD13
.1U-10V_4 C367 C758 VCC3G5 VTT_10
L41 AC13
470U-2.5V_7343 VCC3G6 VTT_11
AC33 AB13
2
.1U-10V_4 10U/X5R-6.3V_8 VCCA_3GPLL VTT_12

G41 AA13
+V1.5_HPLL VCCA_3GBG VTT_13 C470 C435 C374 C414
H41 Y13
L40 +1.05V VSSA_3GBG VTT_14
W13
BK1608LL121_6 VTT_15 .22U-6.3V_4 .22U-6.3V_4 .47U-10V_6
F21 V13
R739 0_6 VCCA_CRTDAC0 VTT_16 .47U-10V_6
E21 U13
C486 VCCA_CRTDAC1 VTT_17
G21 T13
C490 .1U-10V_4 A1A:Change to 22UF B1B:CRT disable C440 C436 +V1.5_DPLLA VSSA_CRTDAC VTT_18 R13
22U-6.3V_8 +V1.5_DPLLB VTT_19
B26 N13
.1U-10V_4 .022U-16V_4 +V1.5_HPLL VCCA_DPLLA VTT_20
C39 M13
+V1.5_MPLL VCCA_DPLLB VTT_21
AF1 L13
L41 VCCA_HPLL VTT_22
AB12
BK1608LL121_6 VTT_23 +2.5V
A38 AA12
A1A:Change to VCCA_LVDS VTT_24
B39 Y12
C483 +V1.5_MPLL VSSA_LVDS VTT_25
ground(LVDS disable) W12
C491 A1A:Change to 22UF VTT_26
AF2 V12
22U-6.3V_8
.1U-10V_4 VCCA_MPLL VTT_27 C382 C357
U12
VTT_28
H20 T12
+1.5V VCCA_TVBG VTT_29 .1U-10V_4
80mils +V3.3_ATVBG
G20
VSSA_TVBG VTT_30
R12
P12 4.7U-10V_8
R772 0_6 VTT_31
N12
VTT_32
M12
C434 C790 R740 0_6 VTT_33
C +1.5V E19 L12 C
C1C:TV disable VCCA_TVDACA0 VTT_34
F19 R11
.1U-10V_4 .022U-16V_4 B1B:TV disable VCCA_TVDACA1 VTT_35
C20 P11
VCCA_TVDACB0 VTT_36
D20 N11
VCCA_TVDACB1 VTT_37
E20 M11
F20 VCCA_TVDACC0
VCCA_TVDACC1 POWER VTT_38
VTT_39
VTT_40
R10
P10
B1B:Change L30 to CVA9115MN10(91NH+-20% 1.5A),footprint L32x25-22 +1.5V AH1 N10
VCCD_HMPLL0 VTT_41
AH2 M10
+V1.5_PCIE 60mils +1.5V VCCD_HMPLL1 VTT_42
P9
L30 R200 A1A:Change to VTT_43
A28 N9
91nH_20%_1.3A 91nH_L32x25-22 0_8 VCCD_LVDS0 VTT_44
ground(LVDS disable) B28 M9
PCIE_L VCCD_LVDS1 VTT_45
C28 R8
+3V +1.5V +V1.5_TVDAC VCCD_LVDS2 VTT_46
P8
+ C314 VTT_47
D21 N8
C308 C307 220U-6.3V_7343 VCCD_TVDAC VTT_48 M8
10U/X5R-6.3V_8 +3V VTT_49
A23 P7
10U/X5R-6.3V_8 C415 C417 C485 C489 VCC_HV0 VTT_50
B23 N7
.1U-10V_4 VCC_HV1 VTT_51
B25 M7
10U/X5R-6.3V_8 .1U-10V_4 +V1.5_QTVDAC VCC_HV2 VTT_52
R6
10U/X5R-6.3V_8 VTT_53
H19 P6
+1.5V_AUX VCCD_QTVDAC VTT_54
M6
+V1.5_3GPLL 60mils 60mils +1.5V 1900mA VTT_55
AK31 A6
R552 L65 R553 VCCAUX0 VTT_56
AF31 R5
0.5/F_6 1uH_6 0_8 VCCAUX1 VTT_57
AE31 P5
3GPLL_FB_R 3GPLL_FB_L AC31 VCCAUX2 VTT_58 N5
VCCAUX3 VTT_59
AL30 M5
VCCAUX4 VTT_60
B AK30 P4 B
VCCAUX5 VTT_61
AJ30 N4
+V1.5_TVDAC +1.5V VCCAUX6 VTT_62
AH30 M4
+1.5V_AUX +1.5V VCCAUX7 VTT_63
AG30 R3
C1C:TV disable 60mils R241 VCCAUX8 VTT_64
AF30 P3
R282 0_8 0_8 VCCAUX9 VTT_65
AE30 N3
VCCAUX10 VTT_66
AD30 M3
C462 B1B:Remove R282 for +1.5V_AUX VCCAUX11 VTT_67
AC30 R2
.1U-10V_4 C445 C430 AG29 VCCAUX12 VTT_68 P2
VCCAUX13 VTT_69
AF29 M2
.022U-16V_4 .1U-10V_4 VCCAUX14 VTT_70
AE29 D2
VCCAUX15 VTT_71
AD29 AB1
VCCAUX16 VTT_72
AC29 R1
+3V +V1.5_QTVDAC VCCAUX17 VTT_73
AG28 P1
VCCAUX18 VTT_74
AF28 N1
VCCAUX19 VTT_75
AE28 M1
+1.5V VCCAUX20 VTT_76
AH22
30mils VCCAUX21
AJ21
D7 *PDZ5.6B AH21 VCCAUX22
C439 C444 VCCAUX23
AJ20
V1_5SFOLLOW VCCAUX24
1 2 AH20
.022U-16V_4 .1U-10V_4 VCCAUX25
AH19
VCCAUX26
P19
R284 VCCAUX27
P16
+V3.3_TVDAC VCCAUX28
AH15
*10_4 VCCAUX29
P15
VCCAUX30
AH14
R283 *0_8 VCCAUX31
A AG14 A
AF14 VCCAUX32
C1C:Remove +V3.3_TVDAC VCCAUX33
AE14
VCCAUX34
Y14
VCCAUX35
AF13
AE13
VCCAUX36
VCCAUX37
PROJECT : ZC1
+1.05V +1.05V 2,3,4,6,8,9,14,17,44 AF12
+1.5V VCCAUX38
AE12
+V1.5_PCIE
+1.5V 4,8,15,17,29,33,42,43
+V1.5_PCIE 8 AD12
VCCAUX39
VCCAUX40
+2.5V +2.5V 8,19,20,42,43
+3V Size Document Number Rev
+3V 2,5,8,13,14,15,16,17,18,19,20,24,25,26,27,29,30,31,32,33,34,35,36,37,38,39,40,41,42,44
Calistoga(945PM) GMCH POWER (5 OF 6) 1A

5 4 3 2 1
5 4 3 2 1
U44I U44J
AC41 AK34 AT23 J11
VSS_0 VSS_97 VSS_180 VSS_273
AA41 AG34 AN23 D11
W41 AF34 AM23 B11
T41 AE34 AH23 AV10
P41 AC34 AC23 AP10
M41 C34 W23 AL10
J41 AW33 K23 AJ10
F41 AV33 J23 AG10
AV40 AR33 F23 AC10
D AP40 AE33 C23 W10 D
AN40 AB33 AA22 U10
AK40 Y33 K22 BA9
AJ40 V33 G22 AW9
AH40 T33 F22 AR9
AG40 R33 E22 AH9
AF40 M33 D22 AB9
AE40 H33 A22 Y9
B40 G33 BA21 R9
AY39 F33 AV21 G9
AW39 D33 AR21 E9
AV39 B33 AN21 A9
AR39 AH32 AL21 AG8
AN39 AG32 AB21 AD8
AJ39 AF32 Y21 AA8
AC39 AE32 P21 U8
AB39 AC32 K21 K8
AA39 AB32 J21 C8
Y39 G32 H21 BA7
W39 B32 C21 AV7
V39 AY31 AW20 AP7
T39 AV31 AR20 AL7
R39
P39
VSS_30
VSS_31
VSS_32
VSS_127
VSS_128
VSS_129
AN31
AJ31
AM20
AA20
VSS_210
VSS_211
VSS_212
VSS VSS_303
VSS_304
VSS_305
AJ7
AH7
N39 AG31 K20 AF7
M39
L39
VSS_33
VSS_34
VSS_35
VSS VSS_130
VSS_131
VSS_132
AB31
Y31
B20
A20
VSS_213
VSS_214
VSS_215
VSS_306
VSS_307
VSS_308
AC7
R7
C J39 AB30 AN19 G7 C
H39 E30 AC19 D7
G39 AT29 W19 AG6
F39 AN29 K19 AD6
D39 AB29 G19 AB6
AT38 T29 C19 Y6
AM38 N29 AH18 U6
AH38 K29 P18 N6
AG38 G29 H18 K6
AF38 E29 D18 H6
AE38 C29 A18 B6
C38 B29 AY17 AV5
AK37 A29 AR17 AF5
AH37 BA28 AP17 AD5
AB37 AW28 AM17 AY4
AA37 AU28 AK17 AR4
Y37 AP28 AV16 AP4
W37 AM28 AN16 AL4
V37 AD28 AL16 AJ4
T37 AC28 J16 Y4
R37 W28 F16 U4
P37 J28 C16 R4
N37 E28 AN15 J4
M37 AP27 AM15 F4
L37 AM27 AK15 C4
J37 AK27 N15 AY3
H37 J27 M15 AW3
B G37 G27 L15 AV3 B
F37 F27 B15 AL3
D37 C27 A15 AH3
AY36 B27 BA14 AG3
AW36 AN26 AT14 AF3
AN36 M26 AK14 AD3
AH36 K26 AD14 AC3
AG36 F26 AA14 AA3
AF36 D26 U14 G3
AE36 AK25 K14 AT2
AC36 P25 H14 AR2
C36 K25 E14 AP2
B36 H25 AV13 AK2
BA35 E25 AR13 AJ2
AV35 D25 AN13 AD2
AR35 A25 AM13 AB2
AH35 BA24 AL13 Y2
AB35 AU24 AG13 U2
AA35 AL24 P13 T2
Y35 AW23 F13 N2
W35 D13 J2
VSS_83 VSS_263 VSS_356
V35 B13 H2
T35 AY12 F2
R35 AC12 C2
P35 K12 AL1
N35 H12
VSS_88 VSS_268
M35 E12
VSS_89 VSS_269
A L35 AD11 A
VSS_90 VSS_270
J35 AA11
VSS_91 VSS_271
H35 Y11
VSS_92 VSS_272
G35
om
VSS_93
F35
VSS_94 Calistoga(945PM) PROJECT : ZC1
l.c
D35
VSS_95
ai
AN34
tm
VSS_96
ho
f@
Calistoga(945PM)
in
GMCH GND(6 OF 6)
xa
1A
he
5 4 3 2 1
1 2 3 4 5 6 7 8
DDRII DUAL CHANNEL A,B.

A A
DDRII A CHANNEL DDRII B CHANNEL

M_A_A[13..0]
SMDDR_VTERM M_A_A[13..0] 7,13
SMDDR_VTERM 42,43
SMDDR_VTERM
SMDDR_VTERM
SMDDR_VTERM
C317 C457 C347 C437 C413 C381 C315 C447 C342 C438 C454 C452 C316
C343 C446 C344 C346 C429 C387 C418 C403 C393 C348 C354 C441 C431 .1U-10V_4.1U-10V_4.1U-10V_4.1U-10V_4.1U-10V_4.1U-10V_4.1U-10V_4.1U-10V_4.1U-10V_4.1U-10V_4.1U-10V_4.1U-10V_4.1U-10V_4
.1U-10V_4.1U-10V_4.1U-10V_4.1U-10V_4.1U-10V_4.1U-10V_4.1U-10V_4.1U-10V_4.1U-10V_4.1U-10V_4.1U-10V_4.1U-10V_4.1U-10V_4
Layout note: Place one cap close to every 2 pullup resistors terminated to SMDDR_VTERM
B A1A:Swap net A1A:Swap net B
M_B_BS#1 RP23 1 2 56_4P2R_S

7,13 M_B_BS#1
M_A_A13 RP33 1 2 56_4P2R_S M_B_A2 3 4
M_ODT0 3 4 M_B_A1 RP22 1 2 56_4P2R_S
8,13 M_ODT0
M_A_A8 RP19 1 2 56_4P2R_S M_B_A3 3 4
M_A_A5 3 4 M_B_A9 RP18 1 2 56_4P2R_S
M_A_A3 RP25 1 2 56_4P2R_S M_B_A5 3 4 SMDDR_VTERM
M_A_A1 3 4 SMDDR_VTERM
M_B_A0 RP20 1 2 56_4P2R_S
M_CKE1 RP11 1 2 56_4P2R_S M_B_A4 3 4
8,13 M_CKE1
M_A_A6 3 4 M_B_A12 RP14 1 2 56_4P2R_S
M_A_A10 RP26 1 2 56_4P2R_S M_B_A8 3 4
M_A_BS#0 3 4 M_B_A7 RP16 1 2 56_4P2R_S
7,13 M_A_BS#0 M_A_A7 M_B_A6
RP17 1 2 56_4P2R_S 3 4
M_A_A11 3 4 M_CKE2 RP12 1 2 56_4P2R_S
8,13 M_CKE2
M_A_A4 RP21 1 2 56_4P2R_S M_B_BS#2 3 4 SMDDR_VTERM
7,13 M_B_BS#2
M_A_A0 3 4 SMDDR_VTERM
M_CS#2 RP27 1 2 56_4P2R_S
M_A_BS#1 8,13 M_CS#2 M_B_RAS#
RP24 1 2 56_4P2R_S 7,13 M_B_RAS# 3 4
7,13 M_A_BS#1
M_A_A2 3 4 7,13 M_B_WE# M_B_WE# RP32 1 2 56_4P2R_S
M_A_A12 RP15 1 2 56_4P2R_S M_B_CAS# 3 4
7,13 M_B_CAS#
M_A_A9 3 4 M_B_A10 RP28 1 2 56_4P2R_S
M_A_WE# RP29 1 2 56_4P2R_S M_B_BS#0 3 4 SMDDR_VTERM
7,13 M_A_WE# 7,13 M_B_BS#0
C M_A_CAS# 3 4 SMDDR_VTERM C
7,13 M_A_CAS#
A1A:Swap net
M_CS#0 RP30 1 2 56_4P2R_S
8,13 M_CS#0
7,13 M_A_RAS# M_A_RAS# 3 4
M_B_A13 RP31 1 2 56_4P2R_S
M_B_A[13..0] M_ODT2 3 4
M_B_A[13..0] 7,13 8,13 M_ODT2
+1.8VSUS M_ODT3 RP35 1 2 56_4P2R_S
+1.8VSUS 8,9,13,20,42,43 8,13 M_ODT3
+3V M_CS#3 3 4
+3V 2,5,8,10,13,14,15,16,17,18,19,20,24,25,26,27,29,30,31,32,33,34,35,36,37,38,39,40,41,42,44 8,13 M_CS#3
M_CS#1 RP34 1 2 56_4P2R_S
8,13 M_CS#1 M_ODT1
8,13 M_ODT1 3 4
M_CKE3 RP10 1 2 56_4P2R_S
8,13 M_CKE3 M_B_A11 3 4
M_CKE0 RP13 1 2 56_4P2R_S
8,13 M_CKE0
M_A_BS#2 3 4 SMDDR_VTERM
7,13 M_A_BS#2
D D
PROJECT : ZC1
DDR RES. ARRAY 1A

1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
M_A_DM[0..7] 7
+3V SMDDR_VREF_DIMM
+3V 2,5,8,10,14,15,16,17,18,19,20,24,25,26,27,29,30,31,32,33,34,35,36,37,38,39,40,41,42,44 M_A_DQ[0..63] 7 M_B_DM[0..7] 7
+1.8VSUS SMDDR_VREF_DIMM +1.8VSUS
+1.8VSUS 8,9,20,42,43 M_A_DQS[0..7] 7 M_B_DQ[0..63] 7
SMDDR_VREF_DIMM A1A:Swap net Place these Caps near So-Dimm1.
M_A_DQS#[0..7] 7 M_B_DQS[0..7] 7
+1.8VSUS A1A:Swap net +1.8VSUS +1.8VSUS +1.8VSUS
M_A_A[0..13] 7,12 M_B_DQS#[0..7] 7
CN30
M_B_A[0..13] 7,12
CN31 A1A:Change DDRII footprint to same as CT6 1 2
VREF VSS46 M_B_DQ4 C451 C425 C405
1 2 3 4
VREF VSS46 M_A_DQ4 M_B_DQ1 VSS47 DQ4 M_B_DQ0 C355 C352
3 4 5 6
2.2U-6.3V_6
2.2U-6.3V_6
2.2U-6.3V_6
M_A_DQ1 VSS47 DQ4 M_A_DQ0 M_B_DQ5 DQ0 DQ5 2.2U-6.3V_6 2.2U-6.3V_6
5 6 7 8
M_A_DQ5 DQ0 DQ5 DQ1 VSS15 M_B_DM0
7 8 9 10
DQ1 VSS15 M_A_DM0 M_B_DQS#0 VSS37 DM0
9 10 11 12
M_A_DQS#0 VSS37 DM0 M_B_DQS0 DQS#0 VSS5 M_B_DQ7
11 12 13 14
M_A_DQS0 DQS#0 VSS5 M_A_DQ7 DQS0 DQ6 M_B_DQ6 +1.8VSUSPlace
13
DQS0 DQ6
14 15
VSS48 DQ7
16 these Caps near So-Dimm1.
A 15 16 M_A_DQ6 M_B_DQ2 17 18 A
M_A_DQ2 VSS48 DQ7 M_B_DQ3 DQ2 VSS16 M_B_DQ12
17 18 19 20
M_A_DQ3 DQ2 VSS16 M_A_DQ13 DQ3 DQ12 M_B_DQ13
19 20 21 22
DQ3 DQ12 M_A_DQ12 M_B_DQ8 VSS38 DQ13
21 22 23 24
M_A_DQ14 VSS38 DQ13 M_B_DQ9 DQ8 VSS17 M_B_DM1 C396 C424 C358 C395
23 24 25 26
M_A_DQ8 DQ8 VSS17 M_A_DM1 DQ9 DM1 .1U-10V_4 .1U-10V_4 .1U-10V_4 .1U-10V_4
25 26 27 28
DQ9 DM1 M_B_DQS#1 VSS49 VSS53 M_CLK_DDR3
27 28 29 30 M_CLK_DDR3 8
M_A_DQS#1 VSS49 VSS53 M_CLK_DDR0 M_B_DQS1 DQS#1 CK0 M_CLK_DDR#3
29 30 M_CLK_DDR0 8 31 32 M_CLK_DDR#3 8
M_A_DQS1 DQS#1 CK0 M_CLK_DDR#0 DQS1 CK0#
31 32 M_CLK_DDR#0 8 33 34
DQS1 CK0# M_B_DQ11 VSS39 VSS41 M_B_DQ15
33 34 35 36
M_A_DQ9 VSS39 VSS41 M_A_DQ11 M_B_DQ10 DQ10 DQ14 M_B_DQ14
35 36 37 38
M_A_DQ15 DQ10 DQ14 M_A_DQ10 DQ11 DQ15 SMDDR_VREF_DIMM +3V
37
DQ11 DQ15
38 39
VSS50 VSS54
40 A1A:Change SODIMM1 pin 50 from PM_EXTTS#1
39 40 to PM_EXTTS#0(Intel recommend)
VSS50 VSS54
41 42
PC4800 DDR2 SDRAM

M_B_DQ17 VSS18 VSS20 M_B_DQ16
41 42 43 44
43 44 45 46
M_A_DQ17 DQ16 DQ20 M_A_DQ16 DQ17 DQ21 C267 C250 C493 C495
45 46 47 48
PC4800 DDR2 SDRAM

DQ17 DQ21 M_B_DQS#2 VSS1 VSS6 PM_EXTTS#0 .1U-10V_4 2.2U-6.3V_6 2.2U-6.3V_6 .1U-10V_4
47 48 49 50 PM_EXTTS#0 8
M_A_DQS#2 VSS1 VSS6 PM_EXTTS#0 M_B_DQS2 DQS#2 NC3 M_B_DM2
49 50 PM_EXTTS#0 8 51 52
M_A_DQS2 DQS#2 NC3 M_A_DM2 DQS2 DM2
51 52 53 54
SO-DIMM (200P)
DQS2 DM2 M_B_DQ19 VSS19 VSS21 M_B_DQ18
53 54 55 56
55 56 57 58
M_A_DQ19 DQ18 DQ22 M_A_DQ22 DQ19 DQ23
57 58 59
SO-DIMM (200P)
60
59
DQ19
VSS22
DQ23
VSS24
60 M_B_DQ28 61
VSS22
DQ24
VSS24
DQ28
62 M_B_DQ24 Place these Caps near So-Dimm1.
M_A_DQ24 61 62 M_A_DQ28 M_B_DQ29 63 64 M_B_DQ25
M_A_DQ25 63
DQ24 DQ28
64 M_A_DQ29 65
DQ25 DQ29
66 No Vias Between the Trace of PIN to
DQ25 DQ29 M_B_DM3 VSS23 VSS25 M_B_DQS#3
65 66 67 68
M_A_DM3 67
VSS23
DM3
VSS25
DQS#3
68 M_A_DQS#3 69
DM3
NC4
DQS#3
DQS3
70 M_B_DQS3 CAP.
69 70 M_A_DQS3 71 72
B NC4 DQS3 M_B_DQ30 VSS9 VSS10 M_B_DQ26 B
71 72 73 74
73 74 75 76
M_A_DQ31 DQ26 DQ30 M_A_DQ26 DQ27 DQ31 +1.8VSUS
75 76 77 78
DQ27 DQ31 M_CKE2 VSS4 VSS8 M_CKE3
77
VSS4 VSS8
78 8,12 M_CKE2 79
CKE0 CKE1
80 M_CKE3 8,12 Place these Caps near So-Dimm2.
M_CKE0 79 80 M_CKE1 81 82
8,12 M_CKE0 CKE0 CKE1 M_CKE1 8,12 VDD7 VDD8
81 82 83 84
VDD7 VDD8 M_B_BS#2 NC1 A15
83 84 7,12 M_B_BS#2 85 86
M_A_BS#2 NC1 A15 A16_BA2 A14 C351 C353
7,12 M_A_BS#2 85 86 87 88
A16_BA2 A14 M_B_A12 VDD9 VDD11 M_B_A11 C366 C345 C426
87 88 89 90
2.2U-6.3V_6
2.2U-6.3V_6
M_A_A12 VDD9 VDD11 M_A_A11 M_B_A9 A12 A11 M_B_A7 2.2U-6.3V_6 2.2U-6.3V_6
89 90 91 92
2.2U-6.3V_6
M_A_A9 A12 A11 M_A_A7 M_B_A8 A9 A7 M_B_A6
91 92 93 94
M_A_A8 A9 A7 M_A_A6 A8 A6
93 94 95 96
A8 A6 M_B_A5 VDD5 VDD4 M_B_A4
95 96 97 98
M_A_A5 VDD5 VDD4 M_A_A4 M_B_A3 A5 A4 M_B_A2
97 98 99 100
M_A_A3 A5 A4 M_A_A2 M_B_A1 A3 A2 M_B_A0 +1.8VSUSPlace
99
A3 A2
100 101
A1 A0
102 these Caps near So-Dimm1.
M_A_A1 101 102 M_A_A0 103 104
A1 A0 M_B_A10 VDD10 VDD12 M_B_BS#1
103 104 105 106 M_B_BS#1 7,12
M_A_A10 VDD10 VDD12 M_A_BS#1 M_B_BS#0 A10/AP BA1 M_B_RAS#
105 106 M_A_BS#1 7,12 7,12 M_B_BS#0 107 108 M_B_RAS# 7,12
A10/AP BA1 M_A_RAS# M_B_WE# BA0 RAS# M_CS#2
7,12 M_A_BS#0 107 108 M_A_RAS# 7,12 7,12 M_B_WE# 109 110 M_CS#2 8,12
M_A_WE# BA0 RAS# M_CS#0 WE# S0# C384 C407 C383 C394
7,12 M_A_WE# 109 110 M_CS#0 8,12 111 112
WE# S0# M_B_CAS# VDD2 VDD1 M_ODT2 .1U-10V_4 .1U-10V_4 .1U-10V_4 .1U-10V_4
111 112 7,12 M_B_CAS# 113 114 M_ODT2 8,12
M_A_CAS# VDD2 VDD1 M_ODT0 M_CS#3 CAS# ODT0 M_B_A13
7,12 M_A_CAS# 113 114 M_ODT0 8,12 115 116
M_CS#1 CAS# ODT0 M_A_A13 8,12 M_CS#3 S1# A13
8,12 M_CS#1 115 116 117 118
S1# A13 M_ODT3 VDD3 VDD6
117 118 8,12 M_ODT3 119 120
M_ODT1 VDD3 VDD6 ODT1 NC2
8,12 M_ODT1 119 120 121 122
ODT1 NC2 M_B_DQ37 VSS11 VSS12 M_B_DQ32
121 122 123 124
M_A_DQ37 VSS11 VSS12 M_A_DQ36 M_B_DQ36 DQ32 DQ36 M_B_DQ33 SMDDR_VREF_DIMM +3V
123 124 125 126
125 126 127 128
DQ33 DQ37 M_B_DQS#4 VSS26 VSS28 M_B_DM4
C 127 128 129 130 C
M_A_DQS#4 VSS26 VSS28 M_A_DM4 M_B_DQS4 DQS#4 DM4
129 130 131 132
M_A_DQS4 DQS#4 DM4 DQS4 VSS42 M_B_DQ34
131 132 133 134
DQS4 VSS42 M_A_DQ33 M_B_DQ39 VSS2 DQ38 M_B_DQ38 C264 C272 C492 C494
133 134 135 136
M_A_DQ38 VSS2 DQ38 M_A_DQ34 M_B_DQ35 DQ34 DQ39 .1U-10V_4 2.2U-6.3V_6 2.2U-6.3V_6 .1U-10V_4
135 136 137 138
M_A_DQ39 DQ34 DQ39 DQ35 VSS55 M_B_DQ44
137 138 139 140
DQ35 VSS55 M_A_DQ45 M_B_DQ41 VSS27 DQ44 M_B_DQ45
139 140 141 142
M_A_DQ41 VSS27 DQ44 M_A_DQ44 M_B_DQ40 DQ40 DQ45
141 142 143 144
M_A_DQ40 DQ40 DQ45 DQ41 VSS43 M_B_DQS#5
143 144 145 146
DQ41 VSS43 M_A_DQS#5 M_B_DM5 VSS29 DQS#5 M_B_DQS5
145 146 147 148
M_A_DM5 147
VSS29 DQS#5
148 M_A_DQS5 149
DM5 DQS5
150 Place these Caps near So-Dimm2.
DM5 DQS5 M_B_DQ47 VSS51 VSS56 M_B_DQ46
149 150 151 152
M_A_DQ42 151
VSS51
DQ42
VSS56
DQ46
152 M_A_DQ46 M_B_DQ42 153
DQ42
DQ43
DQ46
DQ47
154 M_B_DQ43 No Vias Between the Trace of PIN to
M_A_DQ43 153 154 M_A_DQ47 155 156
155
DQ43
VSS40
DQ47
VSS44
156 M_B_DQ53 157
VSS40
DQ48
VSS44
DQ52
158 M_B_DQ52 CAP.
M_A_DQ53 157 158 M_A_DQ49 M_B_DQ49 159 160 M_B_DQ48
159 160 161 162
DQ49 DQ53 VSS52 VSS57 M_CLK_DDR2
161 162 163 164 M_CLK_DDR2 8
VSS52 VSS57 M_CLK_DDR1 NCTEST CK1 M_CLK_DDR#2
163 164 M_CLK_DDR1 8 165 166 M_CLK_DDR#2 8
NCTEST CK1 M_CLK_DDR#1 M_B_DQS#6 VSS30 CK1# SMDDR_VREF
165 166 M_CLK_DDR#1 8 167 168
M_A_DQS#6 VSS30 CK1# M_B_DQS6 DQS#6 VSS45 M_B_DM6
167 168 169 170
M_A_DQS6 DQS#6 VSS45 M_A_DM6 DQS6 DM6
169 170 171 172
DQS6 DM6 M_B_DQ50 VSS31 VSS32 M_B_DQ54
171 172 173 174
173 174 175 176
M_A_DQ50 DQ50 DQ54 M_A_DQ54 DQ51 DQ55 SMDDR_VREF_DIMM R170 0_4
175 176 177 178 SMDDR_VREF 8,43
DQ51 DQ55 M_B_DQ61 VSS33 VSS35 M_B_DQ60
177 178 179 180 R162
179 180 181 182
M_A_DQ57 DQ56 DQ60 M_A_DQ60 DQ57 DQ61 R160 *10K/F_4
181 182 183 184 +1.8VSUS
DQ57 DQ61 M_B_DM7 VSS3 VSS7 M_B_DQS#7 *10K/F_4
183 184 185 186
D
M_A_DM7 VSS3 VSS7 M_A_DQS#7 DM7 DQS#7 M_B_DQS7 D
185 186 187 188
DM7 DQS#7 M_A_DQS7 M_B_DQ63 VSS34 DQS7
187 188 189 190
M_A_DQ63 VSS34 DQS7 M_B_DQ58 DQ58 VSS36 M_B_DQ59
189 190 191 192
DQ58 VSS36 DQ59 DQ62
om
M_A_DQ59 191 192 M_A_DQ58 193 194 M_B_DQ62
DQ59 DQ62 M_A_DQ62 CGDAT_SMB VSS14 DQ63
193 194 195 196
PROJECT : ZC1
l.c
VSS14 DQ63 2 CGDAT_SMB SDA VSS13
CGDAT_SMB 195 196 CGCLK_SMB 197 198 R286 10K_4
ai
SDA VSS13 2 CGCLK_SMB SCL SA0
CGCLK_SMB 197 198 R285 10K_4 199 200 R288 10K_4
tm
SCL SA0 +3V VDD(SPD) SA1
199 200 R287 10K_4
+3V
ho
VDD(SPD) SA1 DDR2_SODIMM(2-1734073-2) +3V
f@
DDR2_SODIMM(1-1734074-1)
SMbus address A0 SMbus address A4
in
DDRII SO-DIMM(200P) 1A
xa
CLOCK 0,1 CKE 0,1 H 5.2 CLOCK 3,4 CKE 2,3 H 9.2
2nd source:DGMK00000C0 2nd source:DGMK0002610
he
Date: Wednesday, November 30, 2005 Sheet 13 of 46
1 2 3 4 5 6 7 8
5 4 3 2 1
RTC VCCRTC
D9 C533 CKL:C1/C2: 18pF -> CL:12.5pF

VCCRTC
+3VPCU C1/C: 10pF -> CL Value = 8.5pF
CH500H-40
1U-16V_6 A1A:Change RTXC1/RTXC2 from 10pf to 18pf
D10 R340 C516 CLK_32KX1
VCCRTC_3 18P-50V_4 +3V +3V
20K_4
1
CH500H-40
R320 R321 C543 Y3 R313
1K_4 32.768KHZ 10M_6
D D
R300 R299
2
1U-16V_6 U48A 10K_4 10K_4
1M/F_4 AB1 AA6
RTXC1 LAD0 LAD0 38,39
C508 CLK_32KX2 AB2 AB5 RCIN#
RTCX2 LAD1 LAD1 38,39
CN32 18P-50V_4 AC4 GATEA20
LAD2 LAD2 38,39
LPC
RTC
1 RTCRST# AA3 Y6
1 RTCRST# LAD3 LAD3 38,39 +1.05V
2
2 SM_INTRUDER# LDRQ#0
Y5 AC3 LDRQ#0 38
RTC CONN Internal PU ICH_INTVRMEN INTRUDER# LDRQ0# LDRQ#1
W4 AA5 T72
INTVRMEN LDRQ1#/GPIO23
A1A:Change RTC W1 AB3 LFRAME# 38,39
VCCRTC_4 EE_CS LFRAME#
Connector footprint Y1
EE_SHCLK GATEA20 R585 R292 +1.05V
Y2 AE22 GATEA20 39
+5VPCU EE_DOUT A20GATE *56.2/F_4 *56.2/F_4
W3 AH28
20MIL 20MIL EE_DIN A20M# H_A20M# 3
Q21 V3 AG27 TP_H_CPUSLP# R307 *0_4
LAN_CLK CPUSLP# H_CPUSLP# 3,6
R341 VCCRTC_1 R333 VCCRTC_2 3 1 B1B:Per Intel comment,don't stuff R307 for CPUSLP#
1.2K_6 1K_4 U3 AF24 H_DPRSTP#_R R305 0_4 R311
LAN_RSTSYNC TP1/DPRSTP# ICH_DPRSTP# 3
LAN
CPU
MMBT3904 AH25 H_DPSLP#_R R584 0_4 56.2/F_4
TP2/DPSLP# H_DPSLP# 3
R343 U5
2
LAN_RXD0
V4 AG26 H_FERR# 3
4.7K_4 LAN_RXD1 FERR#
T5
LAN_RXD2 R312 0_4
AG24 H_PWRGD 3
GPIO49/CPUPWRGD
U7
LAN_TXD0
V6
LAN_TXD1
V7 AG22 H_IGNNE# 3
R342 LAN_TXD2 IGNNE#
AG21 T154
ACZ_BCLK INIT3_3V#
U1 AF22 H_INIT# 3
15K_4 ACZ_SYNC ACZ_BIT_CLK INIT#
R6 AF25 H_INTR 3
AC-97/AZALIA
C ACZ_SYNC INTR +1.05V C
Internal PU ACZ_RST# R5 AG23 RCIN#
ACZ_RST# RCIN# RCIN# 39
ACZ_SDIN0 T2 AH24
36 ACZ_SDIN0 ACZ_SDIN0 NMI H_NMI 3
ACZ_SDIN1 T3 AF23 H_SMI#_R R304 0_4 R293
36 ACZ_SDIN1 ACZ_SDIN1 SMI# H_SMI# 3
ACZ_SDIN2 T1 56.2/F_4
T157 ACZ_SDIN2
AH22 H_STPCLK# 3
ACZ_SDOUT STPCLK#
T4
ACZ_SDOUT H_THERMTRIP_R R306 24.9/F_4
AF26 PM_THRMTRIP# 3,8
SATA_LED# THERMTRIP#
40 SATA_LED# AF18
SATALED# Should be 2" close ICH7
SATA_RXN0_C PDD0 PDD[15:0] 35
C507 3900P_4 AF3 AB15
34 SATA_RXN0 SATA0RXN DD0
CKL:1n ~ 20nF C506 3900P_4 SATA_RXP0_C AE3 AE14 PDD1
34 SATA_RXP0 SATA0RXP DD1
C502 3900P_4 SATA_TXN0_C AG2 AG13 PDD2
34 SATA_TXN0 SATA0TXN DD2
C503 3900P_4 SATA_TXP0_C AH2 AF13 PDD3
34 SATA_TXP0 SATA0TXP DD3
AD14 PDD4 A series termination resistor is
C505 3900P_4 SATA_RXN2_C DD4 PDD5
35 SATA_RXN2 AF7 AC13 required for the PRIMARY CODEC
C504 3900P_4 SATA_RXP2_C SATA2RXN DD5 PDD6
35 SATA_RXP2 AE7 AD12
C500 3900P_4 SATA_TXN2_C SATA2RXP DD6 PDD7
35 SATA_TXN2 AG6 AC12
C501 3900P_4 SATA_TXP2_C SATA2TXN DD7 PDD8 ACZ_SDOUT R349 39_4
35 SATA_TXP2 AH6 AE12 ACZ_SDOUT_AUDIO 36
SATA2TXP DD8 PDD9
AF12
DD9 PDD10
2 CLK_PCIE_SATA# AF1 AB13
SATA_CLKN DD10
SATA
AE1 AC14 PDD11 C559
2 CLK_PCIE_SATA SATA_CLKP DD11 PDD12
AF14 *10P_4
DD12 PDD13
AH10 AH13
R308 24.9/F_4 SATA_BIAS SATARBIASN DD13 PDD14
AG10 AH14
Place within 500 SATARBIASP DD14 PDD15
AC15
+3V DD15
25mils/15mils mils of ICH7 PDA[2:0] 35
PDA0
35 PDIOR# AF15
AH15
DIOR# IDE DA0
AH17
AE17 PDA1
B 35 PDIOW# DIOW# DA1 B
AF16 AF17 PDA2
35 PDDACK# DDACK# DA2
IRQ14 AH16 ACZ_SYNC R350 39_4
35 IRQ14 IDEIRQ ACZ_SYNC_AUDIO 36
PIORDY AG16 AE16
35 PIORDY IORDY DCS1# PDCS1# 35
R309 R314 AE15 AD16
35 PDDREQ DDREQ DCS3# PDCS3# 35
8.2K_4 4.7K_4 C565
ICH7-M DH *10P_4
PIORDY
IRQ14
ACZ_BCLK R605 39_4

BIT_CLK_AUDIO 36
C816
*10P_4
VCCRTC
ICH7 internal VR
enable strap ACZ_BCLK R719 39_4
BIT_CLK_MODEM 36
R334 B1B:Add R719 for BIT_CLK_MODEM
INTVRMEN 332K/F_6 C957
*10P_4
Enable ICH_INTVRMEN
(default) 1
A Disable 0 R332 A
*0_4 ACZ_RST# R348 39_4
ACZ_RST#_AUDIO 36
PROJECT : ZC1
ICH7-M HOST (1 OF 4) 1A

5 4 3 2 1
5 4 3 2 1
A1A:Change PCIE pin define to meet Acer spec

U48D
F26 V26 +3V
33 PCIE_RXN0 PERn1 DMI0RXN DMI_RXN0 8
New card 33 PCIE_RXP0 F25
PERp1 DMI0RXP
V25 DMI_RXP0 8 RP41
Direct Media Interface

C851 .1U-10V_4PCIE_TXN0_C E28 U28
33 PCIE_TXN0 PETn1 DMI0TXN DMI_TXN0 8
C856 .1U-10V_4 PCIE_TXP0_C E27 U27 REQ2# 6 5
33 PCIE_TXP0 PETp1 DMI0TXP DMI_TXP0 8
FRAME# 7 4 INTG#
H26 Y26 STOP# 8 3 REQ3#
REQ1# REQ4#
GLAN 27 PCIE_RXP1
C841 .1U-10V_4PCIE_TXN1_C
H25
G28
PERp2 DMI1RXP
Y25
W28
DMI_RXP1 8 9
10
2
1 TRDY#
27 PCIE_TXN1 PETn2 DMI1TXN DMI_TXN1 8 +3V
C846 .1U-10V_4 PCIE_TXP1_C G27 W27
27 PCIE_TXP1 PETp2 DMI1TXP DMI_TXP1 8
8.2K_10P8R
PCI-Express
PCIE_RXN2 K26 AB26
T78 PERn3 DMI2RXN DMI_RXN2 8
PCIE_RXP2 K25 AB25
D T77 PERp3 DMI2RXP DMI_RXP2 8 D
C836 .1U-10V_4PCIE_TXN2_C J28 AA28 +3V
T163 PETn3 DMI2TXN DMI_TXN2 8
C832 .1U-10V_4 PCIE_TXP2_C J27 AA27
T162 PETp3 DMI2TXP DMI_TXP2 8 RP38
M26 AD25 LOCK# 6 5
+1.5V SERR#
MINI CARD(WLAN) 29 PCIE_RXP3
C831 .1U-10V_4PCIE_TXN3_C
M25
L28
PERp4 DMI3RXP
AD24
AC28
DMI_RXP3 8 PERR#
7
8
4
3 INTH#
29 PCIE_TXN3 PETn4 DMI3TXN DMI_TXN3 8
C827 .1U-10V_4 PCIE_TXP3_C L27 AC27 DEVSEL# 9 2
29 PCIE_TXP3 PETp4 DMI3TXP DMI_TXP3 8 INTE#
+3V 10 1
32 PCIE_RXN4 P26 AE28 CLK_PCIE_ICH# 2
PERn5 DMI_CLKN R375 8.2K_10P8R
32 PCIE_RXP4 P25 AE27 CLK_PCIE_ICH 2
C823 .1U-10V_4PCIE_TXN4_C PERp5 DMI_CLKP 24.9/F_4
EZ4_1 32 PCIE_TXN4
C822 .1U-10V_4 PCIE_TXP4_C
N28
PETn5
32 PCIE_TXP4 N27
PETp5 DMI_ZCOMP
C25 15/15mils
D25 DRI_IRCOMP_R Place within 500 +3V
DMI_IRCOMP
32 PCIE_RXN5 T25 mils of ICH7 RP40
PERn6
32 PCIE_RXP5 T24 F1 USBP0- 29
C821 .1U-10V_4PCIE_TXN5_C PERp6 USBP0N INTF#
EZ4_2 32 PCIE_TXN5 R28
PETn6 USBP0P
F2 USBP0+ 29 MB USB PORT(RIGHT) 6 5
C820 .1U-10V_4 PCIE_TXP5_C R27 G4 REQ5# 7 4 USBOC#4
32 PCIE_TXP5 PETp6 USBP1N USBP1- 29 REQ0# INTD#
USBP1P
G3 USBP1+ 29 MB USB PORT(RIGHT) 8 3
SPI_SCLK R2 H1 IRDY# 9 2 INTC#
SPI_CLK USBP2N USBP2- 29
SPI_CE# P6 H2 MB USB PORT(REAR) +3V 10 1 USBOC#2
NVM_ARB SPI_CS# USBP2P USBP2+ 29
P1 J4
SPI
SPI_ARB USBP3N USBP3- 29
J3 MB USB PORT(REAR) 8.2K_10P8R
SPI_SI USBP3P USBP3+ 29
P5 K1 USBP4- 31
SPI_SO SPI_MOSI USBP4N
P2 K2 6 in 1 card reader
USB
SPI_MISO USBP4P USBP4+ 31
L4 +3V_S5
USBOC#0 USBP5N USBP5- 33
+3V D3 L5 NEW CARD
OC0# USBP5P USBP5+ 33 RP39
USBOC#1 C4 M1
USBOC#2 OC1# USBP6N USBP6- 29 INTB#
D5
OC2# USBP6P
M2 USBP6+ 29 Bluetooth Module 6 5
USBOC#3 D4 N4 USBOC#1 7 4 USBOC#0
OC3# USBP7N USBP7- 25
C USBOC#4 E5 N3 Camera module USBOC#6 8 3 USBOC#3 C
OC4# USBP7P USBP7+ 25
USBOC#5 C3 INTA# 9 2 USBOC#5
R355 R352 R616 USBOC#6 OC5#/GPIO29 USBOC#7
A2 D2 +3V_S5 10 1
*10K_4 *10K_4 *10K_4 USBOC#7 OC6#/GPIO30 USBRBIAS# USB_RBIAS_PN
B3 D1
OC7#/GPIO31 USBRBIAS 8.2K_10P8R
25mils/15mils D2B:Change to +3V_S5
ICH7-M DH Place within 500
T158 SPI_SCLK mils of ICH7 CKL use 10Kohm
T75 SPI_CE# R381
T160 NVM_ARB 22.6/F_6
T76 SPI_SI
T159 SPI_SO
ICH7 Boot BIOS select
U48B STRAP GNT5# GNT4#

29,30 AD[0..31]
AD0 E18 D7 REQ0#
AD1 AD0 REQ0# GNT0#
REQ0# 30 R1 R2
AD2
C18
A16
AD1 PCI GNT0#
E7
C16 REQ1#
GNT0# 30
AD3 AD2 REQ1# GNT1#
F18
AD3 GNT1#
D16 T166 LPC
AD4 E16 C17 REQ2# 11 UNSTUFF UNSTUFF
AD5 A18
AD4 REQ2#
D17
(default)
AD6 AD5 GNT2# REQ3# GNT2# 29
E17 E13
AD7 AD6 REQ3#
A17 F13
AD8 AD7 GNT3# REQ4#
A15
AD8 REQ4#/GPIO22
A13 PCI 10 UNSTUFF STUFF
AD9 C14 A14
B AD9 GNT4#/GPIO48 B
AD10 E14 C8 REQ5#
AD11 AD10 GPIO1/REQ5#
D14 D8
AD12 AD11 GPIO17/GNT5#
B12
AD12 SPI 01 STUFF UNSTUFF
AD13 C13 B15
AD13 C/BE0# CBE0# 29,30
AD14 G15 C12
AD14 C/BE1# CBE1# 29,30
AD15 G13 D12
AD15 C/BE2# CBE2# 29,30
AD16 E12 C15
AD16 C/BE3# CBE3# 29,30
AD17 C11
AD18 AD17 IRDY# C877 R661
D11 A7 IRDY# 29,30
AD19 AD18 IRDY# PCLK_ICH
A11 E10 PAR 30
AD20 AD19 PAR
A10 B18 PCIRST# 29,30
AD21 AD20 PCIRST# DEVSEL# *10P_4 *22_4
F11 A12 DEVSEL# 29,30
AD22 AD21 DEVSEL# PERR#
F10 C9 PERR# 30
AD23 AD22 PERR# LOCK#
E9 E11
AD24 AD23 PLOCK# SERR#
D9 B10 SERR# 30
AD25 AD24 SERR# STOP#
B9 F15 STOP# 30
AD26 AD25 STOP# TRDY#
A8 F14 TRDY# 29,30
AD27 AD26 TRDY# FRAME#
A6 F16 FRAME# 29,30
AD28 AD27 FRAME#
C7
AD29 AD28 PLT_RST-R#
B6 C26 PLT_RST-R# 8
AD30 AD29 PLTRST# PCLK_ICH PCI DEVICE IDSEL# REQ# / GNT# Interrupts
E6 A9 PCLK_ICH 2
AD31 AD30 PCICLK
D6 B19 PCI_PME# 30
AD31 PME#
Interrupt I/F OZ711MP1 AD25 REQ0# / GNT0# INTE#

INTA# A3 G8 INTE# +3V
PIRQA# GPIO2/PIRQE# INTE# 30
INTB# B4 F7 INTF#
INTC# PIRQB# GPIO3/PIRQF# INTG#
C5 F8
INTD# PIRQC# GPIO4/PIRQG# INTH#
B5 G7
PIRQD# GPIO5/PIRQH# T81
A
MISC C587 A
T153 TP_ICH_RSVD1 AE5 AE9 TP_ICH_RSVD6 T68 .1U-10V_4
TP_ICH_RSVD2 RSVD[1] RSVD[6]
T69 AD5 AG8 TP_ICH_RSVD7 T156 U17
RSVD[2] RSVD[7]
5
T67 TP_ICH_RSVD3 AG4 AH8 TP_ICH_RSVD8 T155

T152 TP_ICH_RSVD4 RSVD[3] RSVD[8] RSVD9 PLT_RST-R#
AH4 F21 2
om
T70 TP_ICH_RSVD5 RSVD[4] RSVD[9]
AD9 AH20 4
RSVD[5] MCH_SYNC# MCH_ICH_SYNC 8 PLTRST# 16,18,27,29,32,33,38,39 PROJECT : ZC1
l.c
1
ICH7-M DH
ai
TC7SH08FU R379
tm
3
R365 A1A:Reserve 100k
ho
*1K/F_4 100K_4 pull low to GND
f@
ICH7-M PCI E (2 OF 4) 1A
in
Don't connect to PCI device / Express card
xa
he
5 4 3 2 1
5 4 3 2 1
+3V_S5 +3V_S5
A1A:Change SMB_ALERT# to MAIN power +3V_S5 +3V
PCLK_SMB R399 2.2K_4 RI# R655 10K_4 CLKRUN# R301 8.2K_4

PDAT_SMB R400 2.2K_4 SMB_LINK_ALERT# R396 10K_4 DNBSWON# R401 10K_4
PCIE_WAKE# R364 1K_4 SMLINK0 R395 10K_4 SYS_RST# R389 10K_4 SERIRQ R295 8.2K_4
SMLINK1 R394 10K_4 PM_BATLOW#_R R408 8.2K_4
EXTSMI#_R R648 *10K_4 A1A:Change to 8.2k RUNTIME_SCI#_R R330 10K_4
SMB_ALERT# R392 10K_4 SATA0GP R315 10K_4

D RBAYID1 R303 10K_4 D
RBAYID0 R296 10K_4 SATA1GP R310 10K_4
+3V
to Clock Gen & DIMM
RSMRST# R316 10K_4
U48C
R405 PCLK_SMB C22 AF19 SATA0GP
2,27,29,32,33,35 PCLK_SMB SMBCLK GPIO21/SATA0GP
*1K/F_4 PDAT_SMB B22 AH18 SATA1GP
SMB
2,27,29,32,33,35 PDAT_SMB SMBDATA GPIO19/SATA1GP
SATA
SMB_LINK_ALERT# A26 RST_HDD#
GPIO
T168 AH19 T108
SMLINK0 LINKALERT# GPIO36/SATA2GP RBAYON#
36 ACZ_SPKR T84 B25 AE19 RBAYON# 35
SMLINK1 SMLINK0 GPIO37/SATA3GP
T167 A25
SMLINK1 14M_ICH
AC1 14M_ICH 2
CLK14
Clocks
RI# A28 B2 CLKUSB_48
30 RI# RI# CLK48 CLKUSB_48 2
+3V
A19 C20 T83
LPC_PD# SPKR SUSCLK
38 LPC_PD# A27
SYS_RST# SUS_STAT# R393 100/F_4
3 SYS_RST# A22 B24 SUSB# 39
R390 *10K_4 SYS_RST# SLP_S3# R402 100/F_4
+3V D23 SUSC# 39
R329 0_4 SLP_S4#
8 PM_BMBUSY# AB18 F22
R294 R290 GPIO0/BM_BUSY# SLP_S5#
A1A:Add for SMB_ALERT#
*10K/F_4 *10K/F_4 SMB_ALERT# B23 AA4 ICH_PWROK
No ASF support 27 SMB_ALERT# GPIO11/SMBALERT# PWROK DPRSLPVR 8
Power MGT
R302 0_4 PM_STPPCI_ICH# AC20 AC22 DPRSLPVR R232 499_4
C 2 PM_STPPCI# GPIO18/STPPCI# GPIO16/DPRSLPVR PM_DPRSLPVR 41 C
R298 0_4 PM_STPCPU_ICH# AF21
GPIO
2 PM_STPCPU# GPIO20/STPCPU# PM_BATLOW#_R
C21 B1B:R232 place near PR54 and change to 500 ohm series resistor
SYS
BOARD_ID0 TP0/BATLOW#
A21
GPIO26 DNBSWON#
C23 DNBSWON# 39
BOARD_ID1 PWRBTN#
Note: Connect to EC; Reserve PH/3V B21
GPIO27
A1A:Change to PLTRST#
E23 R403 *100K_4
T82 GPIO28
C19 R404 0_4
CLKRUN# LAN_RST# PLTRST# 15,18,27,29,32,33,38,39
+3V AG18
30,38,39 CLKRUN# GPIO32/CLKRUN#
Y4 PM_RSMRST#_R R317 100/F_4 RSMRST#
RSMRST# RSMRST# 27,39
AC19
R297 GPIO33/AZ_DOCK_EN# LOW_G_INT
35 RST_RBAY# U2 E20 LOW_G_INT 35,39
10K/F_4 GPIO34/AZ_DOCK_RST# GPIO9 HIGHT_G_INT
A20 HIGHT_G_INT 35,39 A1A:Add for HDD protect(G-sensor)
PCIE_WAKE# GPIO10 EMAIL_LED#
27,29,39 PCIE_WAKE# F20 F19 EMAIL_LED# 40
SERIRQ WAKE# GPIO12
30,38,39 SERIRQ AH21
SERIRQ GPIO13
E19 RST_KXP84 35 C2A:Add for G sensor reset
5 THERM_ALERT# AF20 R4 LID591# 25,39,40
THRM# GPIO14
GPIO15
E22 DOCKIN# 25,28,32 GPIO17 has an internal pull-up(Main)
VR_PWRGD_CK410 AD22 R3 LAN_DISABLE# A1A:Add for Disable LAN circuit
VRMPWRGD GPIO24 LAN_DISABLE# 27
GPIO25
D20
RBAYID1 EXPRCRD_STDBY# 33GPIO24(Not cleared by CF9h reset event
AC21 AD21 RBAYID1 35
R331 0_4 RUNTIME_SCI#_R GPIO6 GPIO35 RBAYID0
39 SCI# AC18 GPIO AD20 RBAYID0 35
R640 0_4 EXTSMI#_R GPIO7 GPIO38
39 KBSMI# E21 AE20
GPIO8 GPIO39 GPIO25 /Suspend rail is a HW strap , don't pull down .
+3V +3V ICH7-M DH
B +3V A1A:Change to inverter B
for VR_PWRGD_CK410
R406 R409 CLKUSB_48 14M_ICH
*10K_4 *10K_4 R318
100K_4 +3V
U15 R378 R589
BOARD_ID0 BOARD_ID1 5 1 *10_4 *33_4
2 VR_PWRGD_CK410# 2,41
VR_PWRGD_CK410 4 3
R407 R410 SN74LVC1G04DCKR C584 C811

10K_4 10K_4 *10P_4 *10P_4
+3VSUS
Note: External pull-up 3V
BOM
C815
ID1 ID0 R593 .022U-16V_4
Board ID (R409/R410) (R406/R407) +3V
6.8K/F_4
5
U47 To Lan pwr ok

Como-P 0 0 3,8,41 DELAY_VR_PWRGOOD 2
4 ICH_PWROK
A
ICH_PWROK 27 A
39 PWROK_EC 1
Reserve 0 1 R319 TC7SH08FU R591
PROJECT : ZC1
3
Reserve
1 100K_4
10K_4
0
Reserve 1 1 Size Document Number Rev
ICH7-M GPIO (3 OF 4) 1A
Date: Tuesday, December 06, 2005 Sheet 16 of 46

5 4 3 2 1
5 4 3 2 1
U48E +5V +3V +1.05V

A4 P28 U48F 860mA
VSS[1] VSS[98] V5REF(1)
A23 R1 G10 L11
2
VSS[2] VSS[99] V5REF[1] Vcc1_05[1]
B1 R11 L12
VSS[3] VSS[100] D8 Vcc1_05[2] + C546
B8 R12 AD17 L14
VSS[4] VSS[101] R291 +5V_S5 +3V_S5 V5REF[2] Vcc1_05[3]
B11 R13 PDZ5.6B L16
VSS[5] VSS[102] 15/15mils 100/F_4 V5REF_SUS Vcc1_05[4] C550 C557 330U-2.5V_7343
B14 R14 F6 L17
VSS[6] VSS[103] 15/15mils V5REF_Sus Vcc1_05[5] .1U-10V_4.1U-10V_4
B17 R15 L18
2
VSS[7] VSS[104] Vcc1_05[6]
B20 R16 AA22 M11
VSS[8] VSS[105] D11 Vcc1_5_B[1] Vcc1_05[7]
B26 R17 AA23 M18
VSS[9] VSS[106] C499 C515 R367 Vcc1_5_B[2] Vcc1_05[8]
CORE
B28 R18 PDZ5.6B AB22 P11
VSS[10] VSS[107] 1U-16V_6 .1U-10V_4 10_4 Vcc1_5_B[3] Vcc1_05[9]
C2 T6 AB23 P18
VSS[11] VSS[108] Vcc1_5_B[4] Vcc1_05[10]
C6 T12 AC23 T11
1
VSS[12] VSS[109] Vcc1_5_B[5] Vcc1_05[11] C563 C537 C540 C544
C27 T13 AC24 T18
D VSS[13] VSS[110] Vcc1_5_B[6] Vcc1_05[12] .1U-10V_4.1U-10V_4.1U-10V_4.1U-10V_4
D
D10 T14 AC25 U11
VSS[14] VSS[111] C582 C579 Vcc1_5_B[7] Vcc1_05[13]
D13 T15 AC26 U18
VSS[15] VSS[112] 1U-16V_6 .1U-10V_4 Vcc1_5_B[8] Vcc1_05[14]
D18 T16 AD26 V11
VSS[16] VSS[113] Vcc1_5_B[9] Vcc1_05[15]
D21 T17 AD27 V12
VSS[17] VSS[114] Vcc1_5_B[10] Vcc1_05[16]
D24 U4 AD28 V14
VSS[18] VSS[115] Vcc1_5_B[11] Vcc1_05[17] C545 C551 C560 C535 C564
E1 U12 D26 V16
VSS[19] VSS[116] Vcc1_5_B[12] Vcc1_05[18] .1U-10V_4.1U-10V_4.1U-10V_4.1U-10V_4.1U-10V_4
E2 U13 D27 V17
VSS[20] VSS[117] +1.5V +1.5V_PCIE_ICH Vcc1_5_B[13] Vcc1_05[19] +3V
E4 U14 D28 V18
VSS[21] VSS[118] Vcc1_5_B[14] VCC PAUX Vcc1_05[20]
E8 U15 L43 E24 B1B:Change +3V_S5 to +3V
VSS[22] VSS[119] Vcc1_5_B[15]
E15 U16 E25 V5
VSS[23] VSS[120] Vcc1_5_B[16] VccSus3_3/VccLAN3_3[1] +3V
F3 U17 E26 V1
VSS[24] VSS[121] Vcc1_5_B[17] VccSus3_3/VccLAN3_3[2]
F4 U24 F23 W2
VSS[25] VSS[122] BK1608HS800_6 Vcc1_5_B[18] VccSus3_3/VccLAN3_3[3] C530
F5 U25 F24 W7
VSS[26] VSS[123] + C562 Vcc1_5_B[19] VccSus3_3/VccLAN3_3[4] .1U-10V_4
F12 U26 G22
VSS[27] VSS[124] C527 C536 C549 Vcc1_5_B[20] +3V_S5
F27 V2 G23 U6
VSS[28] VSS[125] 220U-4V_7343 .1U-10V_4 .1U-10V_4 .1U-10V_4 Vcc1_5_B[21] Vcc3_3/VccHDA C517
F28 V13 H22
VSS[29] VSS[126] Vcc1_5_B[22] .1U-10V_4
G1 V15 H23 R7
VSS[30] VSS[127] Vcc1_5_B[23] VccSus3_3/VccSusHDA C534
G2 V24 J22
VSS[31] VSS[128] Vcc1_5_B[24] .1U-10V_4 +1.05V
G5 V27 J23 AE23
VSS[32] VSS[129] B1B:Change C562 to CH7222KMJ82(ME height limit H=1.8) Vcc1_5_B[25] V_CPU_IO[1]
G6 V28 K22 AE26
VSS[33] VSS[130] Vcc1_5_B[26] V_CPU_IO[2]
G9 W6 K23 AH26
VCCA3GP
VSS[34] VSS[131] Vcc1_5_B[27] V_CPU_IO[3]
G14 W24 L22
VSS[35] VSS[132] Vcc1_5_B[28] +3V
G18 W25 L23 AA7
VSS[36] VSS[133] Vcc1_5_B[29] Vcc3_3[3] C513 C518 C531
G21 W26 M22 AB12
VSS[37] VSS[134] Vcc1_5_B[30] Vcc3_3[4] .1U-10V_4.1U-10V_44.7U-10V_1206
G24 Y3 M23 AB20
VSS[38] VSS[135] Vcc1_5_B[31] Vcc3_3[5]
G25 Y24 N22 AC16
VSS[39] VSS[136] Vcc1_5_B[32] Vcc3_3[6]
G26 Y27 N23 AD13
VSS[40] VSS[137] Vcc1_5_B[33] Vcc3_3[7]
IDE
H3 Y28 P22 AD18 C510
VSS[41] VSS[138] Vcc1_5_B[34] Vcc3_3[8] .1U-10V_4
H4 AA1 P23 AG12
C VSS[42] VSS[139] Vcc1_5_B[35] Vcc3_3[9] C
H5 AA24 R22 AG15
VSS[43] VSS[140] Vcc1_5_B[36] Vcc3_3[10] +3V
H24 AA25 R23 AG19
VSS[44] VSS[141] Vcc1_5_B[37] Vcc3_3[11]
H27 AA26 R24
VSS[45] VSS[142] Vcc1_5_B[38]
H28 AB4 R25 A5
VSS[46] VSS[143] Vcc1_5_B[39] Vcc3_3[12]
J1 AB6 R26 B13
VSS[47] VSS[144] Vcc1_5_B[40] Vcc3_3[13]
J2 AB11 T22 B16
VSS[48] VSS[145] +3V Vcc1_5_B[41] Vcc3_3[14] C577 C572 C583 C591
J5 AB14 T23 B7
VSS[49] VSS[146] Vcc1_5_B[42] Vcc3_3[15] .1U-10V_4 .1U-10V_4 .1U-10V_4 .1U-10V_4
J24 AB16 T26 C10
PCI
VSS[50] VSS[147] Vcc1_5_B[43] Vcc3_3[16]
J25 AB19 T27 D15
VSS[51] VSS[148] Vcc1_5_B[44] Vcc3_3[17]
J26 AB21 T28 F9
VSS[52] VSS[149] Vcc1_5_B[45] Vcc3_3[18]
K24 AB24 U22 G11
VSS[53] VSS[150] C578 Vcc1_5_B[46] Vcc3_3[19]
K27 AB27 U23 G12
VSS[54] VSS[151] .1U-10V_4 Vcc1_5_B[47] Vcc3_3[20] VCCRTC
K28 AB28 V22 G16
VSS[55] VSS[152] Vcc1_5_B[48] Vcc3_3[21]
L13 AC2 V23
VSS[56] VSS[153] Vcc1_5_B[49]
L15 AC5 W22 W5
VSS[57] VSS[154] Vcc1_5_B[50] VccRTC
L24 AC9 W23
VSS[58] VSS[155] Vcc1_5_B[51] +3V_S5
L25 AC11 Y22 P7
VSS[59] VSS[156] Vcc1_5_B[52] VccSus3_3[1] C528 C532
L26 AD1 Y23
VSS[60] VSS[157] +1.5V +1.5V_GPLL_ICH Vcc1_5_B[53] .1U-10V_4 .1U-10V_4
M3
VSS[61] VSS[158]
AD3 30mils VccSus3_3[2]
A24
M4 AD4 L67 B27 C24
VSS[62] VSS[159] R583 R582 1uH_6 Vcc3_3[1] VccSus3_3[3]
M5 AD7 D19
VSS[63] VSS[160] 0_4 1_6 GPLL_R GPLL_R_L VccSus3_3[4] C594 C585
M12 AD8 AG28 D22
VSS[64] VSS[161] VccDMIPLL VccSus3_3[5] .1U-10V_4 .1U-10V_4
M13 AD11 G19
VSS[65] VSS[162] +1.5V VccSus3_3[6]
M14 AD15 AB7
VSS[66] VSS[163] C511 C802 Vcc1_5_A[1]
M15 AD19 AC6 K3
VSS[67] VSS[164] .01U-16V_4 Vcc1_5_A[2] VccSus3_3[7]
M16 AD23 AC7 K4
VSS[68] VSS[165] 10U/X5R-6.3V_8 Vcc1_5_A[3] VccSus3_3[8] +3V_S5
M17 AE2 AD6 K5
VSS[69] VSS[166] Vcc1_5_A[4] VccSus3_3[9]
ARX
M24 AE4 AE6 K6 B1B:Change +3VSUS to +3V_S5
VSS[70] VSS[167] +1.5V C522 Vcc1_5_A[5] VccSus3_3[10]
M27 AE8 AF5 L1 to prevent leakage
VSS[71] VSS[168] 1U-16V_6 Vcc1_5_A[6] VccSus3_3[11]
B M28 AE11 AF6 L2 B
USB
VSS[72] VSS[169] Vcc1_5_A[7] VccSus3_3[12]
N1 AE13 AG5 L3
VSS[73] VSS[170] Vcc1_5_A[8] VccSus3_3[13] C571 C555
N2 AE18 AH5 L6
VSS[74] VSS[171] Vcc1_5_A[9] VccSus3_3[14] .1U-10V_4 .1U-10V_4
N5 AE21 L7
VSS[75] VSS[172] C520 VccSus3_3[15]
N6 AE24 AD2 M6
VSS[76] VSS[173] .1U-10V_4 VccSATAPLL VccSus3_3[16]
N11 AE25 M7
VSS[77] VSS[174] +3V VccSus3_3[17] +1.5V
N12 AF2 AH11 N7
VSS[78] VSS[175] Vcc3_3[2] VccSus3_3[18]
N13 AF4
VSS[79] VSS[176] +1.5V
N14 AF8 AB10 AB17
VSS[80] VSS[177] C521 Vcc1_5_A[10] Vcc1_5_A[19] +1.5V
N15
VSS[81] VSS[178]
AF11 30mils AB9
Vcc1_5_A[11] Vcc1_5_A[20]
AC17
N16 AF27 .1U-10V_4 AC10
VSS[82] VSS[179] Vcc1_5_A[12] C512
N17 AF28 AD10 T7
VSS[83] VSS[180] +3V Vcc1_5_A[13] Vcc1_5_A[21] .1U-10V_4
N18 AG1 AE10 F17
VSS[84] VSS[181] Vcc1_5_A[14] Vcc1_5_A[22]
ATX
N24 AG3 R360 C509 AF10 G17 +1.5V
VSS[85] VSS[182] +3V_S5 *0_4 1U-16V_6 Vcc1_5_A[15] Vcc1_5_A[23] C514 C574
N25 AG7 AF9
VSS[86] VSS[183] R362 Vcc1_5_A[16] .1U-10V_4 .1U-10V_4
N26 AG11 AG9 AB8
VSS[87] VSS[184] 0_4 Vcc1_5_A[17] Vcc1_5_A[24]
P3 AG14 AH9 AC8
VSS[88] VSS[185] Vcc1_5_A[18] Vcc1_5_A[25]
P4 AG17
VSS[89] VSS[186] +1.5V 3VS5_ICH_SUS3 TP_ICHVCCSUS1 C519
P12 AG20 E3 K7 T80
VSS[90] VSS[187] C586 VccSus3_3[19] VccSus1_05[1] .1U-10V_4
P13 AG25
VSS[91] VSS[188] .1U-10V_4 TP_ICHVCCSUS2
P14 AH1 C1 C28 T165
VSS[92] VSS[189] VccUSBPLL VccSus1_05[2] TP_ICHVCCSUS3
P15 AH3 G20 T79
VSS[93] VSS[190] *PAD T71 TPVCCSUSLAN1 VccSus1_05[3]
P16 AH7 AA2
VSS[94] VSS[191] C547 T74 TPVCCSUSLAN2 VccSus1_05/VccLAN1_05[1]
P17 AH12 Y7 A1
VSS[95] VSS[192] .1U-10V_4 *PAD VccSus1_05/VccLAN1_05[2] Vcc1_5_A[26] +1.5V
P24 AH23 H6
VSS[96] VSS[193] Vcc1_5_A[27]
USB CORE
P27 AH27 H7
VSS[97] VSS[194] Vcc1_5_A[28]
J6
ICH7-M DH Vcc1_5_A[29]
J7
Vcc1_5_A[30]
ICH7-M DH C575
A .1U-10V_4 A
om
PROJECT : ZC1
l.c
ai
tm
ho
f@
ICH7-M POWER (4 OF 4) 1A
in
xa
he
5 4 3 2 1
5 4 3 2 1
PCIE TEST PADS 8 PEG_RXP[15:0]

PCIE TEST POINTS MUST BE WITHIN 250 MILS 8 PEG_RXN[15:0]
8 PEG_TXP[15:0]
OF THE ASIC BALL WITH POSITIVE AND NEGATIVE 8 PEG_TXN[15:0]
SIGNALS THE SAME DISTANCE
U41A
PART 1 OF 7
PEG_TXP0 AJ31 AK27 V_GMCHEXP_RXP0 C304 EV@.1U-10V_4 PEG_RXP0
PEG_TXN0 PCIE_RX0P PCIE_TX0P
AH31 AJ27 V_GMCHEXP_RXN0 C303 EV@.1U-10V_4 PEG_RXN0
D PCIE_RX0N PCIE_TX0N D
PEG_TXP1 AH30 P AJ25 V_GMCHEXP_RXP1 C333 EV@.1U-10V_4 PEG_RXP1

AG30 C AH25 V_GMCHEXP_RXN1 C332 EV@.1U-10V_4 PEG_RXN1
PCIE_RX1N PCIE_TX1N
I
PEG_TXP2 AG32 AH28 V_GMCHEXP_RXP2 C302 EV@.1U-10V_4 PEG_RXP2
PEG_TXN2 PCIE_RX2P - PCIE_TX2P
ATI FEATURE NOT ENABLED (M52P,M54P,M56P) AF32 AG28 V_GMCHEXP_RXN2 C301 EV@.1U-10V_4 PEG_RXN2
PCIE_RX2N E PCIE_TX2N
B1B:Don't stuff R153,R166 for PCIE_TEST X
PEG_TXP3 AF31 AG27 V_GMCHEXP_RXP3 C331 EV@.1U-10V_4 PEG_RXP3
PEG_TXN3 PCIE_RX3P P PCIE_TX3P
+3V AE31 AF27 V_GMCHEXP_RXN3 C330 EV@.1U-10V_4 PEG_RXN3
PCIE_RX3N PCIE_TX3N
R
PEG_TXP4 AE30 E AF25 V_GMCHEXP_RXP4 C300 EV@.1U-10V_4 PEG_RXP4
AD30 S AE25 V_GMCHEXP_RXN4 C299 EV@.1U-10V_4 PEG_RXN4
R153 PCIE_RX4N PCIE_TX4N
S
*4.7K_4 PEG_TXP5 AD32 AE28 V_GMCHEXP_RXP5 C329 EV@.1U-10V_4 PEG_RXP5
AC32 I AD28 V_GMCHEXP_RXN5 C328 EV@.1U-10V_4 PEG_RXN5
PCIE_TEST PCIE_RX5N PCIE_TX5N
N
PEG_TXP6 AC31 AD27 V_GMCHEXP_RXP6 C298 EV@.1U-10V_4 PEG_RXP6
PEG_TXN6 PCIE_RX6P T PCIE_TX6P
C
R166 AB31 AC27 V_GMCHEXP_RXN6 C297 EV@.1U-10V_4 PEG_RXN6 C
PCIE_RX6N E PCIE_TX6N
*4.7K_4
R
PEG_TXP7 AB30 AC25 V_GMCHEXP_RXP7 C327 EV@.1U-10V_4 PEG_RXP7
PEG_TXN7 AA30
PCIE_RX7P F PCIE_TX7P
AB25 V_GMCHEXP_RXN7 C326 EV@.1U-10V_4 PEG_RXN7
PCIE_RX7N PCIE_TX7N
A
PEG_TXP8 AA32
C AB28 V_GMCHEXP_RXP8 C296 EV@.1U-10V_4 PEG_RXP8
PCIE_RX8P PCIE_TX8P
PEG_TXN8 Y32
PCIE_RX8N
E PCIE_TX8N
AA28 V_GMCHEXP_RXN8 C295 EV@.1U-10V_4 PEG_RXN8
PEG_TXP9 Y31 AA27 V_GMCHEXP_RXP9 C325 EV@.1U-10V_4 PEG_RXP9

W31 Y27 V_GMCHEXP_RXN9 C324 EV@.1U-10V_4 PEG_RXN9
PCIE_RX9N PCIE_TX9N
PEG_TXP10 W30 Y25 V_GMCHEXP_RXP10 C294 EV@.1U-10V_4 PEG_RXP10

V30 W25 V_GMCHEXP_RXN10 C293 EV@.1U-10V_4 PEG_RXN10
PCIE_RX10N PCIE_TX10N
PEG_TXP11 V32 W28 V_GMCHEXP_RXP11 C323 EV@.1U-10V_4 PEG_RXP11

U32 V28 V_GMCHEXP_RXN11 C322 EV@.1U-10V_4 PEG_RXN11
PEG_TXP12 U31 V27 V_GMCHEXP_RXP12 C292 EV@.1U-10V_4 PEG_RXP12

B T31 U27 V_GMCHEXP_RXN12 C291 EV@.1U-10V_4 PEG_RXN12 B
PEG_TXP13 T30 U25 V_GMCHEXP_RXP13 C321 EV@.1U-10V_4 PEG_RXP13

R30 T25 V_GMCHEXP_RXN13 C320 EV@.1U-10V_4 PEG_RXN13
PEG_TXP14 R32 T28 V_GMCHEXP_RXP14 C290 EV@.1U-10V_4 PEG_RXP14

P32 R28 V_GMCHEXP_RXN14 C289 EV@.1U-10V_4 PEG_RXN14
PEG_TXP15 P31 R27 V_GMCHEXP_RXP15 C319 EV@.1U-10V_4 PEG_RXP15

N31 P27 V_GMCHEXP_RXN15 C318 EV@.1U-10V_4 PEG_RXN15
Clock Calibration
+3V AL28 B1B:PCIE_CALRN(ball AE24) need change to +1.2V_VPCIE
2 CLK_PCIE_M56 PCIE_REFCLKP
2 CLK_PCIE_M56# AK28
PCIE_REFCLKN R156 EV@2K/F_4 +1.2V_VPCIE
AE24
PCIE_CALRN
5
U65 AD24 R172 EV@562/F_4

PLTRST# PCIE_CALRP
15,16,27,29,32,33,38,39 PLTRST# 2
4 PLTRST#_M56 AG24 AB24 R167 EV@1.47K/F_4
PERSTB PCIE_CALI
1
PCIE_TEST AA24 FOR M52P,M54P,M56P
A EV@TC7SH08FU PCIE_TEST A
PCIE_CALRN = 2K
3
PCIE CALRP = 562R

AF24
PERSTB_MASK
Tie To VSS PCIE CALI = 1.47K PROJECT : ZC1
R791 *0_4
EV@M56-P B13 Quanta Computer Inc.
E3A:Add U65 for M56 PLTRST#
M56P 1 OF 7 1A

5 4 3 2 1
5 4 3 2 1
D2B:The TMDS termination resistor values

(330 ohm) are pcb layout dependent
U41B and may require final tuning
PART 2 OF 7
AL9 TXCM_EX 25
Integrated TXCM
AM9 TXCP_EX 25
TMDS TXCP R123 EV@180_4
MEMORY CLOCK SPREAD

AK10 TX0M_EX 25
TX0M
T12 AG8 AL10 TX0P_EX 25
GPIO_34 TX0P R132 EV@180_4
AH7
SPECTRUM
T11 GPIO_33
ANY UNUSED GPIO CAN OPTIONALLY T14 AG9 AL11 TX1M_EX 25
GPIO_32 TX1M
BE MEMORY TYPE CONFIG STRAPS T13 AH8
GPIO_31 V TX1P
AM11 TX1P_EX 25
AJ8 R130 EV@180_4
T107
AH9
GPIO_30 I AL12
T16 GPIO_29 TX2M TX2M_EX 25
T19 AG10
GPIO_28
D TX2P
AM12 TX2P_EX 25
24 MEMTYP_1 AF10 R134 EV@180_4
AH6
GPIO_27 E AK9
24 MEMTYP_0
Expand GPIO
D
MEMTYP_1 R792 *0_4 GPIO_26 O TX3M D
AF8 AJ9
GPIO_25 TX3P
C1C:Change GPIO27 instead of GPIO25 for MEMTYPE_1 T15 AF7 D2B:Change R123,R130,R132,R134 from 330 to 180 for TMDS
GPIO_24
E3A:Add R792 for MEMTYPE_1 T17 AE9 AK11
GPIO_23 & TX4M
AE10 AJ11
GPIO_22 TX4P
AG7
GPIO_21
AF9 AK12
T18
AF13
GPIO_20 M TX5M
AJ12 +TPVDD
T23 GPIO_19 TX5P
T22 AE13
GPIO_18
U +2.5V
AM8 L58 VDD_PNL_PLL25 (2.5V @ 40mA ASIC LPVDD,TPVDD)
L TPVDD EV@BLM18PG181SN1D_6
B1B:Change R177,R181 to 0 ohm for VGA 27MHZ
U11 T AL8 C723 C119
XT_IN XT_OUT L28 EV@BLM18PG181SN1D_6 TPVSS EV@1U-6.3V_4 EV@22U-16V_12
1 8 I FOR M52P,M54P,M56P
XIN XOUT MK1726_VDD C262 C741
2 7 +3V AJ6 CONNECT TO +2.5V
1726_S0 3
VSS VDD
6 MK_PD EV@.1U-10V_4 FOR M52P,M54P,M56P AK4 M TXVDDR_1
AK6
SRS PD NC_DVOVMODE_0 TXVDDR_2
OSC_SPREAD R199 EV@33_4 1726_CKO 4
SSCLK REF
5 MK_27M 27MOUT NOT CONNECTED AL4
NC_DVOVMODE_1
E TXVDDR_3
AL6 TXVDDR
R177 EV@0_4 EV@22U-16V_12 AM6 +2.5V
EV@CY25819 AF2
D TXVDDR_4 L56
DVPCNTL_0 I
MK1726-8 AF1
DVPCNTL_1
EV@BLM18PG181SN1D_6
+3V AF3 AJ7
R550 DVPCNTL_2 A TXVSSR_1 C114 C722 C142
AG1 AK7
27M_IN EV@0_4 VGA27M DVPCLK TXVSSR_2
AG2 AL7
MK_PD DVPDATA_0 TXVSSR_3 EV@22U-16V_12 EV@.1U-10V_4
AG3 AM7
R198 27M_O *0_4 R182 EV@0_4 R181 DVPDATA_1 TXVSSR_4 EV@1U-6.3V_4
AH2 AK8
DVPDATA_2 TXVSSR_5
*10K_4 AH3
C739 R171 DVPDATA_3
AJ2
R551 *10P-50V_4 *10K_4 DVPDATA_4
AJ1 AK24 R_DAC1 26
DVPDATA_5 DAC / CRT R
AK2 AM24 G_DAC1 26
1726_S0 EV@71.5/F_4 DVPDATA_6 G
VIP Host/External TMDS

AK1 AL24 B_DAC1 26
DVPDATA_7 B
AK3
DVPDATA_8
B1B:Don't stuff C739 AL2 AJ23 HSYNC_DAC1 24,26
DVPDATA_9 HSYNC
AL3 AJ22 VSYNC_DAC1 24,26
R197 DVPDATA_10 VSYNC
Voltage divider resistor values R181 AM3 AK22
*10K_4 DVPDATA_11 GENERICA
and R551 to ensure XTALIN/XTALOUT AE6
VID/DVO_R13 DVPDATA_12 R96 EV@0_4 VGA_OVT#
voltage level matches vddc 24 DC_Strap2 AF4 AF23 For m26x,m52p,m54p,m56p thermal interrupt
VID/DVO_R14 DVPDATA_13 GENERICB
24 DC_Strap3 AF5 is low edge and connects to gpio17
VID/DVO_R15 DVPDATA_14 R178 EV@499/F_4
24 DC_Strap4 AG4 AL22
DVPDATA_15 RSET +AVDD L64
AJ3
DVPDATA_16 C261 +2.5V
C AH4 AL25 AVDD_2.5 (2.5V @ 65mA ASIC AVDD) C
R99 EV@0_4 VID/DVO_R18 DVPDATA_17 AVDD_1 AVDD EV@BLM18PG181SN1D_6
A1A:Reversed LVDSCLK,LVDSDATA 25 LVDS_DAT AJ4 AM25 FOR M52P,M54P,M56P
VID/DVO_R19 DVPDATA_18 AVDD_2
pull high to LVDS side 25 LVDS_CLK AG5 CONNECT TO +2.5V
R111 EV@0_4 DVPDATA_19 C265 C738 EV@22U-16V_12
AH5 AK23
DVPDATA_20 AVSSQ
A1A:Change LVDS_DAT/LVDS_CLK 24 DEMUX_SEL AF6 AK25
DVPDATA_21 AVSSN_1 EV@1U-6.3V_4 EV@.1U-10V_4 +VDDDI +2.5V
to DVPDATA18/DVPDATA19 AE7 AJ24
DVPDATA_22 AVSSN_2
AG6 VDDDI_2.5 (2.5V @ 40mA ASIC VDD1DI,VDD2DI)
DVPDATA_23
A1A:Add pull low 10k 24 GPIO[13..0] AM23
GPIO0 VDD1DI L63 EV@BLM18PG181SN1D_6
GPIO15 HI = 1.0V VDDC AD4
GPIO1 GPIO_0 General
AD2 AL23
GPIO15 LO = 1.1V VDDC GPIO2 GPIO_1 Purpose VSS1DI C251 C259 C246
AD1
GPIO_2 I/O
T106 GPIO7 GPIO3 AD3
GPIO_3
AK15 EV@1U-6.3V_4 EV@.1U-10V_4 EV@22U-16V_12 PLACE CLOSE TO ASIC
V_PWRCNTL GPIO4 AC1 DAC2 (TV/CRT2)R2 AM15
GPIO5 GPIO_4 G2
AC2 AL15 E3B:Add R137,R143,R146,R174,R175,R176
GPIO6 GPIO_5 B2
AC3 (150 ohm) for CRT/TV can't detect issue
GPIO7 GPIO_6
AB2 AF15
R127 GPIO8 GPIO_7_BLON H2SYNC R_DAC1 R174 150/F_4
AC6 AG15
10K_4 GPIO9 GPIO_8 V2SYNC G_DAC1 R176 150/F_4
AC5
GPIO10 GPIO_9 EXT_TV_Y/G B_DAC1 R175 150/F_4
AC4 AJ15 Y_DAC2 25
GPIO11 GPIO_10 Y EXT_TV_C/R EXT_TV_Y/G R146 150/F_4
AB3 AJ13 C_DAC2 25
GPIO12 GPIO_11 C EXT_TV_COMP EXT_TV_C/R R137 150/F_4
V_PWRCNTL DRIVEN HI SELECT 1.0V VDDC AB4 AH15 COMP_DAC2 25
GPIO13 GPIO_12 COMP EXT_TV_COMP R143 150/F_4
V_PWRCNTL DRIVEN LO SELECT 1.1V VDDC AB5
GPIO_13 R138 +2.5V
AD5 AK14
V_PWRCNTL GPIO_14 R2SET EV@715/F_4
44 V_PWRCNTL AB8
OSC_SPREAD GPIO_15
For m26x,m52p,m54p,m56p thermal interrupt AA8 AM16
+3V VGA_OVT# GPIO_16 A2VDD_1 C239 C193 C169
is low edge and connects to gpio17 AB7 AL16 FOR M52P,M54P,M56P A2VDDQ
EV@0_4 R120 GPIO_17 A2VDD_2
AB6 IT IS NO CONNECT
EV@499/F_4 R129 EV@499/F_4 R128 NC_AB6 EV@1U-6.3V_4 EV@22U-16V_12
AM17
A2VSSN_1 EV@.1U-10V_4 +A2VDDQ +2.5V
AC8 AL17
C958 *.1U-10V_4 VREFG A2VSSN_2 L59
B1B:Reserved for VREFG
+PVDD VGATHRM+ AG12 AL14
+2.5V DPLUS Thermal NC_A2VDDQ EV@BLM18PG181SN1D_6
FOR M52P,M54P,M56P CONNECT TO +2.5V L60 VGATHRM- AH12 Diode AK13 C726 C178 C140
EV@BLM18PG181SN1D_6 DMINUS A2VSSQ +VDD2DI +2.5V EV@1U-6.3V_4 EV@22U-16V_12
C153 C728 C724 PVDD AJ14 AJ16 L61 EV@.1U-10V_4
EV@1U-6.3V_4 PVDD PLL & VDD2DI EV@BLM18PG181SN1D_6
EV@22U-16V_12 EV@.1U-10V_4
1.2V OR 1.0V @ 20MA ASIC MPVDD +1.1V_VGA 20 mA +MPVDD PVSS AH14 XTAL AJ17 FOR M52P,M54P,M56P
PVSS VSS2DI C196 C209 C218
B
CONNECT TO VDDC CONNECT TO +2.5V B
L20 A6 EV@1U-6.3V_4 EV@.1U-10V_4 EV@22U-16V_12
EV@BLM18PG181SN1D_6 MPVSS MPVDD
A5
C131 C139 C145 C141 C138 MPVSS Monitor AF11 TMDS_HPD 25,32
EV@.1U-10V_4 EV@1U-6.3V_4 27M_IN Interface HPD1
AL26
EV@22U-16V_12 EV@1U-6.3V_4 EV@1U-6.3V_4 27M_O XTALIN
AM26
XTALOUT
AH22 CRT1DDCDATA 26
T21 DDC1DATA
AG14 AH23 CRT1DDCCLK 26
PLLTEST DDC1CLK
C288 XT_IN R191 *33_4 R159 TESTEN AG22 AH13 The DDC2 is for DVI (TMDS) reading EDID data,
TESTEN DDC2DATA TMDS_DDCDATA 32
R185 *33_4 EV@1K_4 Test AG13 which cannot be shared with other I2C devices.
DDC2CLK TMDS_DDCCLK 32
EV@22P-50V_4
AC7 AE12 R125 *0_4 VTHM_DAT_EC
A1A:Reserve for thermal
Y2 ROMCSb ROM DDC3DATA R126 *0_4 VTHM_CLK_EC
AF12
XT_OUT
DDC3CLK sensor CLK/DATA

+-10PPM R186 B1B:Stuff R125,R126 for VGA thermal sensor SMBus
EV@1M_4 D2B:Remove R125,R126 for VGA thermal sensor SMBus
EV@TXC=27MHz External AE23 FOR M52P,M54P,M56P GENERICC
GENERICC GENERICC 24
AK17 SSC IT IS GPIO
LVSSR_1
AJ19 AE18
C278 LVSSR_2 LVDS PLL LPVSS
AF18
LVSSR_3 and I/O
AH17
EV@22P-50V_4 LVSSR_4 GND
AG17 AF22
LVSSR_5 LVDS PLL LVSSR_10
AG19 AF17
LVSSR_6 and I/O LVSSR_9
AH19 AF21
LVSSR_7 GND LVSSR_8
EV@M56-P B13
+3V
15 MIL +3V
L17 3V_THM1 +3V C2A:Stuff Q12,Q31 for VGA thermal sensor
EV@BLM18PG181SN1D_6 B1B:Don't stuff R82,R95 +3V
C113 R82 for thermal sensor
Q12
2
EV@.1U-10V_4 10K_4 D2B:stuff R82 for thermal sensor 2N7002E
A U7 R122 R133 VTHM_DAT_EC 1 3 MBDATA MBDATA 5,39,46 A

1 6 VGA_OVT#
VGATHRM- VCC ALERT# VTHM_DAT_EC 10K_4 10K_4
3 7
DXN SDA VTHM_CLK_EC
2 8
C115 DXP SCLK
10 mil trace / 5 4 VGA_THERM# 5
om
GND OVERT# VTHM_DAT_EC VTHM_CLK_EC MBCLK
1 3
10 mil space EV@2200P-50V_4 EV@G781-1 D2B:Connect U7 OVERT to fan driver MBCLK 5,39,46
l.c
VGATHRM+ VTHM_CLK_EC
2N7002E
ai
Close to pin ASIC SLAVE ADDRESS: 9A A1A:Reserve for VGA
2
Q31
tm
thermal sensor PROJECT : ZC1
ho
D2B:Change R122,R133 to 10K to resolve +3V
f@
Battery can't learning issue B1B:Remove Q12,Q31 for VGA thermal sensor
in
xa
M56P 2 OF 7 1A
he
Date: Saturday, December 10, 2005 Sheet 19 of 46
5 4 3 2 1
5 4 3 2 1
If memory interface has to be up to 600Mhz or above, the
GPU core voltage and memory I/O voltage may need to be
increased to 1.2~1.3V and 2.0V U41E
+1.2V_VPCIE
VGA_MEM_IO PART 5 OF 7 1.2V ASIC PCIE_PVDD_12 @ 100mA, PCIE_VDDR_12 @ 2000mA
A1A:Change to VGA_MEM_IO
C1 V23 FOR M52P,M54P,M56P CONNECT TO +1.2V
VDDR1_1 PCIE_PVDD_12_1
J1 N23
C208 VDDR1_2 PCIE_PVDD_12_2 C313
M1 P23
C283 C156 C150 C247 C124 C277 C129 C130 VDDR1_3 PCIE_PVDD_12_3 C252 C276 C275
R1 U23
EV@22U-16V_12 EV@1U-6.3V_4 EV@1U-6.3V_4 EV@1U-6.3V_4 EV@1U-6.3V_4 VDDR1_4 PCIE_PVDD_12_4 EV@1U-6.3V_4 EV@1U-6.3V_4 EV@1U-6.3V_4 EV@22U-16V_12
V1
EV@1U-6.3V_4 EV@1U-6.3V_4 EV@1U-6.3V_4 EV@1U-6.3V_4 VDDR1_5
AA1 N29
VDDR1_6 PCIE_VDDR_12_10
A3 N28
VDDR1_7 PCIE_VDDR_12_11 +1.2V_VPCIE
P9 N27
J10 N26
N9 N25
C180 C236 C244 C233 C258 C237 VDDR1_10 PCIE_VDDR_12_14
P10
EV@1U-6.3V_4 EV@1U-6.3V_4 EV@1U-6.3V_4 VDDR1_11 C284 C256 C279 C253 C312
A9 AL31
D
EV@22U-16V_12 EV@1U-6.3V_4 EV@1U-6.3V_4 VDDR1_12 PCIE_VDDR_12_1 EV@1U-6.3V_4 EV@1U-6.3V_4
D
PCI-Express
Y10 AM31
VDDR1_13 PCIE_VDDR_12_2 EV@1U-6.3V_4 EV@1U-6.3V_4 EV@22U-16V_12
P8 AM30
R9 AL32
Y9 AL30
VDDR1_16 PCIE_VDDR_12_5 +1.2V_VPCIE
J11 AM28
C162 C152 C163 C166 C171 C257 C282 VDDR1_17 PCIE_VDDR_12_6
A21 AL29
EV@1U-6.3V_4 EV@1U-6.3V_4 EV@1U-6.3V_4 VDDR1_18 PCIE_VDDR_12_7
M10 AM29
Memory I/O
EV@22U-16V_12 EV@1U-6.3V_4 EV@1U-6.3V_4 EV@1U-6.3V_4 N10 AM27
VDDR1_21 PCIE_VDDR_12_9 C266 C271 C274 C263 C255 C309
Y8
VDDR1_22 EV@1U-6.3V_4 EV@1U-6.3V_4 EV@1U-6.3V_4
J18
VDDR1_23 EV@1U-6.3V_4 EV@1U-6.3V_4 EV@22U-16V_12
J19 AC11 1.2V OR 1.0V @ 18A ASIC VDDC,VDDCI
VDDR1_24 VDDC_1
K21 AC12
VDDR1_25 VDDC_2 +1.1V_VGA
A12 P14
C281 C151 C192 C172 C120 C157 C217 C176 C221 VDDR1_26 VDDC_3
H13 U15
EV@1U-6.3V_4 EV@1U-6.3V_4 EV@1U-6.3V_4 EV@1U-6.3V_4 EV@1U-6.3V_4 VDDR1_27 VDDC_4
A15 W14
EV@1U-6.3V_4 EV@1U-6.3V_4 EV@1U-6.3V_4 EV@1U-6.3V_4 VDDR1_28 VDDC_5
J20 W15
VDDR1_29 VDDC_6
J13 R17
VDDR1_30 VDDC_7
K11 R15
VDDR1_31 VDDC_8 C174 C222 C225 C224 C183 C191 C181 C206 C133
K19 V15
VDDR1_32 VDDC_9 EV@1U-6.3V_4 EV@1U-6.3V_4 EV@1U-6.3V_4 EV@1U-6.3V_4 EV@22U-16V_12
A18 V16
VDDR1_33 VDDC_10 EV@1U-6.3V_4 EV@1U-6.3V_4 EV@1U-6.3V_4 EV@1U-6.3V_4
L23 T16
VDDR1_34 VDDC_11
K20 U16
VDDR1_35 VDDC_12
K24 P T17
VDDR1_36 VDDC_13
Core
L24 U17
VDDR1_37 VDDC_14
H19
VDDR1_38 O VDDC_15
V14
C175 C170 C164 C210 C202 C201 C234 C194 C725
A24 R18
VDDR1_39 W VDDC_16 EV@1U-6.3V_4 EV@1U-6.3V_4 EV@1U-6.3V_4 EV@1U-6.3V_4 EV@22U-16V_12
K13 T18
VDDR1_40 VDDC_17 EV@1U-6.3V_4 EV@1U-6.3V_4 EV@1U-6.3V_4 EV@1U-6.3V_4
J32 V18
A30
VDDR1_41 E VDDC_18
P18
VDDR1_42 VDDC_19
C32 P19
F32
VDDR1_43 R VDDC_20
R19
VDDR1_45 VDDC_21
L32 W19
VDDR1_46 VDDC_22
AD11
+3V_S5 +3V VDDC_23 +2.5V
D2B:Add R778,Q56,Q57 for VGA +3V power sequence
R777 *0_6
AC13
VDD25_1
AC16
Q56 VDD25_2
C AC18 C
C127 C205 C212 C240 C219 C214 VDD25_3 L26 +1.2V_VPCIE C203 C249 C730
I/O Internal
1 3 EV@22U-16V_12 EV@1U-6.3V_4 EV@1U-6.3V_4 AB9 AC15 +1.2V_VDDPLL EV@1U-6.3V_4 EV@10U-10V_8
R778 EV@1U-6.3V_4 EV@1U-6.3V_4 EV@1U-6.3V_4 VDDR3_1 VDDPLL EV@BLM18PG181SN1D_6 EV@1U-6.3V_4
AB10
VDDR3_2
AA9 W10
EV@100K/F_4 AO3403 VDDR3_3 VDDCI_1
AC19 T14
2
VDDR3_4 VDDCI_2
AD18 W17
VDDR3_5 VDDCI_3 C195 C243
AC20 P16
VDDR3_6 VDDCI_4
AD19 T23
+VDDR4 VDDR3_7 VDDCI_5 EV@1U-6.3V_4 EV@10U-10V_8 +1.1V_VGA
AD20 K14
VDDR3_8 VDDCI_6 +1.1V_VGA_VDDC
U19
VDDCI_7
I/0
L19 VDDR4 for DVPDATA[12..23] L22 EV@BLM18PG181SN1D_6
3
+2.5V EV@BLM18PG181SN1D_6
Q57 C137 AJ5 VDD_PNL_PLL25 (2.5V @ 40mA ASIC LPVDD,TPVDD) C182 C199 C223 C254 C190
C134 VDDR4_1 +2.5V EV@1U-6.3V_4 EV@1U-6.3V_4 EV@22U-16V_12
EV@1U-6.3V_4 AM5
EV@2N7002 EV@.1U-10V_4 VDDR4_2 +2.5V_LPVDD L62 EV@1U-6.3V_4 EV@1U-6.3V_4
2 AL5 AE19
VDDR4_3 LPVDD/VDDL0 EV@BLM18PG181SN1D_6
AK5
+VDDR5 VDDR4_4
AF20
L57 VDDR5 for DVPDATA[0..11] LVDDR/VDDL0_1 C220 C733
AE2 AE20
EV@BLM18PG181SN1D_6 VDDR5_1 LVDDR/VDDL0_2 EV@22U-16V_12
AE3 AF19 EV@1U-6.3V_4
1
C720 C721 VDDR5_2 LVDDR/VDDL0_3

AE4
LVDS PLL, I/O

VDDR5_3
A1A:Change to VGA_MEM_IO EV@1U-6.3V_4 EV@.1U-10V_4 AE5
VGA_MEM_IO VDDR5_4
AC21
LVDDR/VDDL1_1 +2.5V
AC22
L21 +1.8V_VDDRH LVDDR/VDDL1_2 +2.5V_LVDDR L24
A27 AD22
VDDRH0 LVDDR/VDDL1_3
Clock
I/O
Memory
EV@BLM18PG181SN1D_6 F1 AE21 +2.5V EV@BLM18PG181SN1D_6
C270 C269 C148 C143 VDDRH1 LVDDR/VDDL2_1
AD21
LVDDR/VDDL2_2
AE22
EV@1U-6.3V_4 EV@1U-6.3V_4 EV@1U-6.3V_4 EV@1U-6.3V_4 LVDDR/VDDL2_3
A28
VSSRH0 C197
E1
VSSRH1 C204 C213 C177 C242 C241 C231
EV@1U-6.3V_4 EV@1U-6.3V_4 EV@1U-6.3V_4 EV@.1U-10V_4
EV@M56-P B13 EV@.1U-10V_4 EV@22U-16V_12 EV@1U-6.3V_4
B B
GENERICD : FOR M56P IT IS A BACK
U41G BIAS REGULATOR CONTROL
PART 7 OF 7
RP9 EV@0_4P2R_S
Forward Control and External SSC AD12 3 4
VARY_BL LVDS_BLON 25
AE11 1 2 LVDS_DIGON 25
Compatibility DIGON
AD23 Panel power(LCDVCC) control
GENERICD T24
GENERICD->FOR M56P IT IS A BACK BIAS REGULATOR CONTROL
AJ21 TXUCLKOUT+ 25
R165 0_4 BBN_M56 TXCLK_UP
Y23 AK21 TXUCLKOUT- 25
BBN_4 TXCLK_UN
K15 AH21
+1.1V_VGA BBN_3 TXOUT_U3P
100 mA R10 AG21
BBN_2 TXOUT_U3N
AC17 AG20 TXUOUT2+ 25
R152 0_4 +1.1V_VGA_BBP BBN_1 TXOUT_U2P
AC14 AH20 TXUOUT2- 25
BBP_4 TXOUT_U2N
M23 AK20 TXUOUT1+ 25
C245 C161 C230 BBP_3 TXOUT_U1P
V10 AJ20 TXUOUT1- 25
BBP_2 TXOUT_U1N
EV@22U-16V_12 EV@.1U-10V_4 EV@1U-6.3V_4 K18
BBP_1
LVDS channel
TXOUT_U0P
AG18 TXUOUT0+ 25
AH18 TXUOUT0- 25
TXOUT_U0N
AK19 TXLOUT0- 25
+2.5V TXOUT_L0N
AL19 TXLOUT0+ 25
L29 +2.5V_VDDR25 TXOUT_L0P
L10 AL20 TXLOUT1- 25
EV@BLM18PG181SN1D_6 C160 VDD25_4 TXOUT_L1N
K22 AM20 TXLOUT1+ 25
C260 C248 EV@1U-6.3V_4 AA10 VDD25_5 TXOUT_L1P
AL21 TXLOUT2- 25
VDD25_6 TXOUT_L2N
EV@22U-16V_12 EV@.1U-10V_4 AM21 TXLOUT2+ 25
TXOUT_L2P
AK18
TXOUT_L3N
AJ18
+3V +1.8VSUS TXOUT_L3P
AL18 TXLCLKOUT- 25
TXCLK_LN
AM18 TXLCLKOUT+ 25
TXCLK_LP
E3A:Add R789 for G966_VIN,change
source to +1.8VSUS
R779 R789
EV@M56-P B13
100K/F_4 0_6
A +5V +1.2V_VPCIE +1.2V_VPCIE A

D2B:Add R778,R780 for +1.2V_VPCIE U9
4 6 R548 EV@45.3K/F_4
R780 EV@0_4 G966_VIN VPP VO
44 VDDCPG 3 7
R781 *0_4 VIN ADJ
2 5
32,39,42,43,44 MAINON VEN NC R549 C734 C736
1 8
43 PCIEVDDRPG POK GND EV@10U-10V_8 EV@.1U-10V_4
C729 C198 EV@G966
C972
EV@.1U-10V_4 EV@91K_4
*.1U-10V_4 EV@10U-10V_8 PROJECT : ZC1
M56P POWER 1A
Date: Tuesday, November 29, 2005 Sheet 20 of 46

5 4 3 2 1
5 4 3 2 1
U41F
Part 6 of 7
AH27 AD16
PCIE_VSS_1 VSS_38
AC23 AA6
D PCIE_VSS_2 VSS_39 D
AL27 P7
PCIE_VSS_3 VSS_40
R23 P5
PCIE_VSS_4 VSS_41
P25 M3
PCIE_VSS_5 VSS_42
R25 M9
PCIE_VSS_6 VSS_43
T26 L7
PCIE_VSS_7 VSS_44
U26 M7
PCIE_VSS_8 VSS_45
W26 AD17
PCIE_VSS_9 VSS_46
Y26 AH11
PCIE_VSS_10 VSS_47
AB26 A8
PCIE_VSS_11 VSS_48
AC26 U7
PCIE_VSS_12 VSS_49
AD25 C10
PCIE_VSS_13 VSS_50
AE26 E9
PCIE_VSS_14 VSS_51
AF26 F3
PCIE_VSS_15 VSS_52
AD26 J9
PCIE_VSS_16 VSS_53
AG25 N7
PCIE_VSS_17 VSS_54
AH26 N3
PCIE_VSS_18 VSS_55
AC28 Y5
PCIE_VSS_19 VSS_56
Y28 AM13
PCIE_VSS_20 VSS_57
U28 AC10
PCIE_VSS_21 VSS_58
P28 Y6
PCIE_VSS_22 VSS_59
AH29 U6
PCIE_VSS_23 VSS_60
AF28 E5
PCIE_VSS_24 VSS_61
V29 AL13
PCIE_VSS_25 VSS_62
AC29 A11
PCIE_VSS_26 VSS_63
W27 U8
PCIE_VSS_27 VSS_64
AB27 U9
PCIE_VSS_28 VSS_65
PCI-Express GND
V26 U10
PCIE_VSS_29 VSS_66
AJ26 R6
PCIE_VSS_30 VSS_67
AJ32 AD6
PCIE_VSS_31 VSS_68
AK29 V6
PCIE_VSS_32 VSS_69
P26 AD14
PCIE_VSS_33 VSS_70
P29 AD13
PCIE_VSS_34 VSS_71
R29 D11
PCIE_VSS_35 VSS_72
T29 J12
PCIE_VSS_36 VSS_73
U29 K12
PCIE_VSS_37 VSS_74
W29 A13
PCIE_VSS_38 VSS_75
Y29 F13
PCIE_VSS_39 VSS_76
C AA29 E13 C
PCIE_VSS_40 VSS_77
AB29 F15
PCIE_VSS_41 VSS_78
AD29 K16
PCIE_VSS_42 VSS_79
AE29 J21
PCIE_VSS_43 VSS_80
AF29 H16
PCIE_VSS_44 VSS_81
AG29 T15
PCIE_VSS_45 VSS_82
AJ29 V17
PCIE_VSS_46 VSS_83
AK26 C15
PCIE_VSS_47 VSS_84
AK30 C4
PCIE_VSS_48 VSS_85
AG26 U14
PCIE_VSS_49 VSS_86
N30 P15
PCIE_VSS_50 VSS_87
R31 A16
PCIE_VSS_51 VSS_88
AF30 E16
PCIE_VSS_52 VSS_89
AC30 G13
PCIE_VSS_53 VSS_90
V31 G16
PCIE_VSS_54 VSS_91
P30 P17
PCIE_VSS_55 VSS_92
AA31 R16
PCIE_VSS_56 VSS_93
U30 R14
PCIE_VSS_57 VSS_94
AD31 W16
PCIE_VSS_58 VSS_95
AK32 C18
PCIE_VSS_59 VSS_96
AJ28 F16
PCIE_VSS_60 VSS_97
Y30 W18
PCIE_VSS_61 VSS_98
AJ30 U18
PCIE_VSS_62 VSS_99
AK31 AE16
PCIE_VSS_63 VSS_100
AA23 AE17
PCIE_VSS_64 VSS_101
AG31 A19
PCIE_VSS_65 VSS_102
N24 H32
PCIE_VSS_66 VSS_103
AB23 F19
PCIE_VSS_67 VSS_104
P24 G19
PCIE_VSS_68 VSS_105
R24 N8
PCIE_VSS_69 VSS_106
T24 Y7
PCIE_VSS_70 VSS_107
U24 T19
PCIE_VSS_71 VSS_108
V24 V19
PCIE_VSS_72 VSS_109
W24 G21
PCIE_VSS_73 VSS_110
Y24 C21
PCIE_VSS_74 VSS_111
AC24 F21
PCIE_VSS_75 VSS_112
AH24 AE14
PCIE_VSS_76 VSS_113
V25 AK16
B PCIE_VSS_77 VSS_114 B
AA25 U5
PCIE_VSS_78 VSS_115
R26 F22
PCIE_VSS_79 VSS_116
AA26 F18
PCIE_VSS_80 VSS_117
T27 K30
PCIE_VSS_81 VSS_118
AE27 C24
L27 PCIE_VSS_82 VSS_119
F24
VSS_120
W23 M24
EV@BLM18PG181SN1D_6 PCIE_PVSS VSS_121
A25
VSS_122
B1 D30
VSS_1 VSS_123
H1 E25
VSS_2 VSS_124
L1 G25
VSS_3 VSS_125
P1 G20
VSS_4 VSS_126
U1 G22
VSS_5 VSS_127
Y1 F27
AD7
AE8
VSS_6
VSS_7
VSS_8
CORE GND VSS_128
VSS_129
VSS_130
E28
H21
AL1 C27
VSS_9 VSS_131
A2 E32
VSS_10 VSS_132
AM2 H28
VSS_11 VSS_133
AD10 J30
VSS_12 VSS_134
E8 K17
VSS_13 VSS_135
H5 K27
VSS_14 VSS_136
K10 M32
VSS_15 VSS_137
M8 A22
VSS_16 VSS_138
T10 C20
VSS_17 VSS_139
E12 E19
VSS_18 VSS_140
AC9 H20
VSS_19 VSS_141
AF14 J24
VSS_20 VSS_142
AD8 M28
VSS_21 VSS_143
C5 J28
VSS_22 VSS_144
F10 J16
VSS_23 VSS_145
J3 F30
VSS_24 VSS_146
L6 L29
VSS_25 VSS_147
M6 A31
VSS_26 VSS_148
P6 B32
VSS_27 VSS_149
AA4 E30
VSS_28 VSS_150
AG11 AE15
VSS_29 VSS_151
A V3 AG23 A
VSS_30 VSS_152
AG16 AD9
VSS_31 VSS_153
R3 AF16
VSS_32 VSS_154
C6 AH10
VSS_33 VSS_155
C9 AJ10
om
VSS_34 VSS_156
F6 AD15
VSS_35 VSS_157
H7 AH16
l.c
VSS_36 VSS_158
J6
VSS_37
ai
K23
VSS_159
tm
EV@M56-P B13 PROJECT : ZC1
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M56P 6 OF 7 1A
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Date: Thursday, November 17, 2005 Sheet 21 of 46
5 4 3 2 1
5 4 3 2 1
RV410 MEMORY CHANNELS A and B

Channel B
Channel A
U41D
U41C 23 MDB[0..63]
MAB[0..15] 23
23 MDA[0..63] Part 4 of 7
MAA[0..15] 23
Part 3 of 7
MDB0 B12 G4 MAB0
MDA0 MAA0 MDB1 DQB_0 MAB_0 MAB1
M31 D26 C12 E6 FOR M56P(Channel B)
MDA1 DQA_0 MAA_0 MAA1 MDB2 DQB_1 MAB_1 MAB2
M30 F28 B11 E4 PIN H2 IS MA14 (BA0)
L31 D28 FOR M56P(Channel A) C11 H4
MDA3 DQA_2 MAA_2 MAA3 MDB4 DQB_3 MAB_3 MAB4 PIN H3 IS MA15 (BA1)
L30 D25 PIN B25 IS MA14 (BA0) C8 J5
MDA4 DQA_3 MAA_3 MAA4 MDB5 DQB_4 MAB_4 MAB5 PIN D5 IS MA13 (BA2)
H30 E24 PIN C25 IS MA15 (BA1) B7 G5
MDA5 DQA_4 MAA_4 MAA5 MDB6 DQB_5 MAB_5 MAB6 PIN F5 IS MAB12
G31 E26 C7 F4
D DQA_5 MAA_5 DQB_6 MAB_6 D
MEMORY INTERFACE A
MDA6 G30 D27 MAA6 PIN E29 IS MA13 (BA2) MDB7 B6 H6 MAB7
MEMORY INTERFACE B
MDA7 DQA_6 MAA_6 MAA7 PIN E27 IS MA12 MDB8 DQB_7 MAB_7 MAB8 MAB12
F31 F25 F12 G3 T9
M27 C26 D12 G2
MDA9 DQA_8 MAA_8 MAA9 MAA12 MDB10 DQB_9 MAB_9 MAB10
M29 B26 T25 E11 D4
L28 D29 F11 F2
L27 B27 F9 F5
J27 E27 D8 D5
H29 E29 D7 H2
G29 B25 F7 H3
MDA15 DQA_14 MAA_14 MAA15 MDB16 DQB_15 MAB_15
G27 C25 -DQMA[0..7] 23 G12 -DQMB[0..7] 23
MDA16 DQA_15 MAA_15 MDB17 DQB_16
M26 G11
MDA17 DQA_16 MDB18 DQB_17 -DQMB0
L26 H12 B8
MDA18 DQA_17 -DQMA0 MDB19 DQB_18 DQMBb_0 -DQMB1
M25 H31 H11 D9
MDA19
DQA_18 DQMAb_0 -DQMA1 MDB20
DQB_19 DQMBb_1 -DQMB2
L25 J29 H9 G9
MDA20 DQA_19 DQMAb_1 -DQMA2 MDB21 DQB_20 DQMBb_2 -DQMB3
J25 J26 E7 K7
G28 G23 F8 M5
H27 E21 G8 V2
H26 B15 G6 W4
F26 D14 G7 T9
MDA25 DQA_24 DQMAb_6 -DQMA7 MDB26 DQB_25 DQMBb_7
G26 J17 H8 RDQSB[0..7] 23
MDA26 DQA_25 DQMAb_7 MDB27 DQB_26
H25 RDQSA[0..7] 23 J8
MDA27 DQA_26 MDB28 DQB_27
H24 K8
MDA28 DQA_27 MDB29 DQB_28 RDQSB0
H23 L8 B9
MDA29 DQA_28 RDQSA0 MDB30 DQB_29 QSB_0 RDQSB1
H22 J31 K9 D10
MDA30 DQA_29 QSA_0 RDQSA1 MDB31 DQB_30 QSB_1 RDQSB2
J23 K29 L9 H10
J22 K25 K5 K6
E23 F23 L4 N4
DQA_32 QSA_3 DQB_33 QSB_4
read strobe
read strobe
MDA33 D22 D20 RDQSA4 MDB34 K4 U2 RDQSB5
D23 B16 L5 U4
E22 D16 N5 V8 WDQSB[0..7] 23
MDA36 DQA_35 QSA_6 RDQSA7 MDB37 DQB_36 QSB_7
E20 H15 WDQSA[0..7] 23 N6
MDA37 DQA_36 QSA_7 MDB38 DQB_37
F20 P4
MDA38 DQA_37 MDB39 DQB_38 WDQSB0
D19 R4 B10
MDA39 DQA_38 WDQSA0 MDB40 DQB_39 QSB_0B WDQSB1
D18 K31 P2 E10
MDA40 DQA_39 QSA_0B WDQSA1 MDB41 DQB_40 QSB_1B WDQSB2
B19 K28 R2 G10
write strobe
B18 write strobe K26 T3 J7
C17 G24 T2 M4
C B17 D21 W3 U3 C
C14 C16 W2 V4
B14 D15 Y3 V9
MDA46 DQA_45 QSA_6B WDQSA7 MDB47 DQB_46 QSB_7B
C13 J15 Y2
MDA47 DQA_46 QSA_7B MDB48 DQB_47
B13 T4 D6
MDA48 DQA_47 MDB49 DQB_48 ODTB
D17 F29 R5 J4
MDA49 DQA_48 ODTA MDB50 DQB_49 ODTB1
E18 D24 T5
MDA50 DQA_49 ODTA1 MDB51 DQB_50
E17 T6
MDA51 DQA_50 MDB52 DQB_51
F17 V5 B4 M_CLKB0 23
MDA52 DQA_51 MDB53 DQB_52 CLKB0
E15 D31 M_CLKA0 23 W5 B5 -M_CLKB0 23
MDA53 DQA_52 CLKA0 MDB54 DQB_53 CLKB0b
E14 E31 -M_CLKA0 23 W6
MDA54
DQA_53 CLKA0b MDB55
DQB_54
F14 Y4 C2 CKEB 23
MDA55 DQA_54 MDB56 DQB_55 CKEB0
D13 B30 CKEA 23 R8
MDA56 DQA_55 CKEA0 MDB57 DQB_56
H18 T8 E2 -RASB 23
VGA_MEM_IO MDA57 DQA_56 MDB58 DQB_57 RASB0b
H17 B28 -RASA 23 R7
MDA58 DQA_57 RASA0b MDB59 DQB_58
G18 T7 D3 -CASB 23
MDA59 DQA_58 MDB60 DQB_59 CASB0b
G17 C29 -CASA 23 V7
MDA60 DQA_59 CASA0b VGA_MEM_IO MDB61 DQB_60
G15 W7 B2 -WEB 23
MDA61 DQA_60 MDB62 DQB_61 WEB0b
G14 B31 -WEA 23 W8
R194 MDA62 DQA_61 WEA0b MDB63 DQB_62
H14 W9 D2 -CSB0 23
EV@40.2/F_4 MDA63 DQA_62 R97 DQB_63 CSB0b_0
J14 B29 -CSA0 23 E3
DQA_63 CSA0b_0 EV@40.2/F_4 CSB0b_1
C28
CSA0b_1
VRAM_REF0 C31 N2
MVREFD_0 CLKB1 M_CLKB1 23
C30 B20 VRAM_REF2 B3 P3
MVREFS_0 CLKA1 M_CLKA1 23 MVREFD_1 CLKB1b -M_CLKB1 23
C19 VRAM_REF3 C3
CLKA1b -M_CLKA1 23 MVREFS_1
R187 C286 L3
EV@.1U-10V_4 CKEB1 CKEB1 23
EV@100/F_4 C22 R83 C116
CKEA1 CKEA1 23
EV@100/F_4 23 MEM_RST AA3 J2
EV@.1U-10V_4
DRAM_RST RASB1b -RASB1 23
B24 -RASA1 23
RASA1b TEST_MCLK AA5 L2 -CASB1 23
TEST_MCLK CASB1b
B22 -CASA1 23
VGA_MEM_IO CASA1b TEST_YCLK AA2 M2 -WEB1 23
TEST_YCLK WEB1b
B21 -WEA1 23
WEA1b
AA7 K2 -CSBb0 23
VGA_MEM_IO MEMTEST CSB1b_0
B23 -CSAb0 23 K3
CSA1b_0 CSB1b_1
R110
R102
R121
R189 C23
CSA1b_1
R104
EV@40.2/F_4
B B
R93 EV@M56-P B13
EV@M56-P B13 EV@40.2/F_4
EV@4.7K_4
EV@4.7K_4
EV@4.7K_4
EV@243/F_4
VRAM_REF1 NI
R184 C285
EV@100/F_4 EV@.1U-10V_4
R94 C118
EV@100/F_4 EV@.1U-10V_4
Place VRAM_REF0,VRAM_REF1 parts closed M56

Reference voltage per channel (memory data/strobe)
MVREFD_[0:1] (0.7 * VDDR1) (for GDDR3) Reference voltage per channel (memory data/strobe)
MVREFS_[0:1] (0.7 * VDDR1) (for GDDR3) MVREFD_[0:1] (0.7 * VDDR1) (for GDDR3)
MVREFS_[0:1] (0.7 * VDDR1) (for GDDR3)
A A
PROJECT : ZC1
M56P 3/4 OF 7 1A

5 4 3 2 1
5 4 3 2 1
-DQMB[0..7] 22
RDQSB[0..7] 22
WDQSB[0..7] 22
-DQMA[0..7] 22
RDQSA[0..7] 22
WDQSA[0..7] 22
256/512 Mbit GDDRIII Channels A and B Rank 1 MDB[0..63] 22
MAB[0..15] 22
MDA[0..63] 22
MAA[0..15] 22
VGA_MEM_IO VGA_MEM_IO VGA_MEM_IO
VGA_MEM_IO U40 U37 U6
U10 MDA41 T3 A1 C155 EV@.022U-16V_4 MDB29 T3 A1 C98 EV@.022U-16V_4 MDB38 T3 A1 C99 EV@.022U-16V_4
MDA31 T3 A1 C762 EV@.022U-16V_4 MDA43 T2 DQ31 | DQ23 VDDQ A12 MDB28 T2 DQ31 | DQ23 VDDQ A12 MDB34 T2 DQ31 | DQ23 VDDQ A12
MDA29 DQ31 | DQ23 VDDQ Memory MDA40 DQ30 | DQ22 VDDQ#A12 C147 EV@.022U-16V_4 MDB31 DQ30 | DQ22 VDDQ#A12 C705 EV@.022U-16V_4 MDB39 DQ30 | DQ22 VDDQ#A12 C105 EV@.022U-16V_4
T2 A12 R3 C1 R3 C1 R3 C1
MDA28 R3
DQ30 | DQ22 VDDQ#A12
C1 C740 EV@.022U-16V_4 decoupling MDA42 R2
DQ29 | DQ21 VDDQ#C1
C4 MDB30 R2
DQ29 | DQ21 VDDQ#C1
C4 MDB33 R2
DQ29 | DQ21 VDDQ#C1
C4
MDA30 R2 DQ29 | DQ21 VDDQ#C1 C4 MDA45 M3 DQ28 | DQ20 VDDQ#C4 C9 C158 EV@.022U-16V_4 MDB25 M3 DQ28 | DQ20 VDDQ#C4 C9 C109 EV@.022U-16V_4 MDB32 M3 DQ28 | DQ20 VDDQ#C4 C9 C97 EV@.022U-16V_4
MDA24 M3 DQ28 | DQ20 VDDQ#C4 C9 C760 EV@.022U-16V_4 MDA44 N2 DQ27 | DQ19 VDDQ#C9 C12 MDB27 N2 DQ27 | DQ19 VDDQ#C9 C12 MDB35 N2 DQ27 | DQ19 VDDQ#C9 C12
MDA27 N2 DQ27 | DQ19 VDDQ#C9 C12 MDA47 L3 DQ26 | DQ18 VDDQ#C12 E1 C128 EV@.022U-16V_4 MDB26 L3 DQ26 | DQ18 VDDQ#C12 E1 C100 EV@.022U-16V_4 MDB37 L3 DQ26 | DQ18 VDDQ#C12 E1 C718 EV@.022U-16V_4
MDA25 DQ26 | DQ18 VDDQ#C12 C759 EV@.022U-16V_4 MDA46 DQ25 | DQ17 VDDQ#E1 MDB24 DQ25 | DQ17 VDDQ#E1 MDB36 DQ25 | DQ17 VDDQ#E1
L3 E1 M2 E4 M2 E4 M2 E4
MDA26 M2 DQ25 | DQ17 VDDQ#E1 E4 MDA53 T10 DQ24 | DQ16 VDDQ#E4 E9 C146 EV@.022U-16V_4 MDB7 T10 DQ24 | DQ16 VDDQ#E4 E9 C106 EV@.022U-16V_4 MDB62 T10 DQ24 | DQ16 VDDQ#E4 E9 C702 EV@.022U-16V_4
D MDA9 T10 DQ24 | DQ16 VDDQ#E4 E9 C735 EV@.022U-16V_4 MDA52 T11 DQ23 | DQ31 VDDQ#E9 E12 MDB4 T11 DQ23 | DQ31 VDDQ#E9 E12 MDB63 T11 DQ23 | DQ31 VDDQ#E9 E12 D
MDA13 T11 DQ23 | DQ31 VDDQ#E9 E12 MDA54 R10 DQ22 | DQ30 VDDQ#E12 J4 C123 EV@.022U-16V_4 MDB6 R10 DQ22 | DQ30 VDDQ#E12 J4 C94 EV@22U-10V_8 MDB60 R10 DQ22 | DQ30 VDDQ#E12 J4 C701 EV@22U-10V_8
MDA10 DQ22 | DQ30 VDDQ#E12 C228 EV@.022U-16V_4 MDA55 DQ21 | DQ29 VDDQ#J4 MDB5 DQ21 | DQ29 VDDQ#J4 MDB61 DQ21 | DQ29 VDDQ#J4
R10 J4 R11 J9 R11 J9 R11 J9
MDA14 R11 DQ21 | DQ29 VDDQ#J4 J9 MDA50 M10 DQ20 | DQ28 VDDQ#J9 N1 C144 EV@.022U-16V_4 MDB1 M10 DQ20 | DQ28 VDDQ#J9 N1 C96 EV@.022U-16V_4 MDB58 M10 DQ20 | DQ28 VDDQ#J9 N1 C111 EV@10U-10V_8
MDA8 DQ20 | DQ28 VDDQ#J9 C761 EV@.022U-16V_4 MDA51 DQ19 | DQ27 VDDQ#N1 MDB3 DQ19 | DQ27 VDDQ#N1 MDB59 DQ19 | DQ27 VDDQ#N1
M10 N1 N11 N4 N11 N4 N11 N4
MDA11 N11 DQ19 | DQ27 VDDQ#N1 N4 MDA49 L10 DQ18 | DQ26 VDDQ#N4 N9 C135 EV@.022U-16V_4 MDB2 L10 DQ18 | DQ26 VDDQ#N4 N9 C700 EV@10U-10V_8 MDB57 L10 DQ18 | DQ26 VDDQ#N4 N9 C703 EV@.022U-16V_4
MDA12 L10 DQ18 | DQ26 VDDQ#N4 N9 C737 EV@.022U-16V_4 MDA48 M11 DQ17 | DQ25 VDDQ#N9 N12 MDB0 M11 DQ17 | DQ25 VDDQ#N9 N12 MDB56 M11 DQ17 | DQ25 VDDQ#N9 N12
MDA15 M11 DQ17 | DQ25 VDDQ#N9 N12 MDA58 G10 DQ16 | DQ24 VDDQ#N12 R1 C173 EV@.022U-16V_4 MDB15 G10 DQ16 | DQ24 VDDQ#N12 R1 C707 EV@.022U-16V_4 MDB52 G10 DQ16 | DQ24 VDDQ#N12 R1 C110 EV@.022U-16V_4
MDA2 DQ16 | DQ24 VDDQ#N12 C280 EV@.022U-16V_4 MDA56 DQ15 | DQ7 VDDQ#R1 MDB13 DQ15 | DQ7 VDDQ#R1 MDB53 DQ15 | DQ7 VDDQ#R1
G10 R1 F11 R4 F11 R4 F11 R4
MDA7 DQ15 | DQ7 VDDQ#R1 MDA57 DQ14 | DQ6 VDDQ#R4 C167 EV@10U-10V_8 MDB14 DQ14 | DQ6 VDDQ#R4 C714 EV@.022U-16V_4 MDB55 DQ14 | DQ6 VDDQ#R4 C108 EV@.022U-16V_4
F11 R4 F10 R9 F10 R9 F10 R9
MDA5 F10 DQ14 | DQ6 VDDQ#R4 R9 C268 EV@10U-10V_8 MDA59 E11 DQ13 | DQ5 VDDQ#R9 R12 MDB12 E11 DQ13 | DQ5 VDDQ#R9 R12 MDB54 E11 DQ13 | DQ5 VDDQ#R9 R12
MDA0 E11 DQ13 | DQ5 VDDQ#R9 R12 MDA62 C10 DQ12 | DQ4 VDDQ#R12 V1 C165 EV@22U-10V_8 MDB10 C10 DQ12 | DQ4 VDDQ#R12 V1 C95 EV@220P-50V_4 MDB50 C10 DQ12 | DQ4 VDDQ#R12 V1 C104 EV@220P-50V_4
MDA1 DQ12 | DQ4 VDDQ#R12 C306 EV@22U-10V_8 MDA61 DQ11 | DQ3 VDDQ#V1 MDB11 DQ11 | DQ3 VDDQ#V1 MDB51 DQ11 | DQ3 VDDQ#V1
C10 V1 C11 V12 C11 V12 C11 V12
MDA6 C11 DQ11 | DQ3 VDDQ#V1 V12 MDA60 B10 DQ10 | DQ2 VDDQ#V12 C132 EV@220P-50V_4 MDB9 B10 DQ10 | DQ2 VDDQ#V12 C709 EV@4700P-25V_4 MDB48 B10 DQ10 | DQ2 VDDQ#V12 C715 EV@4700P-25V_4
MDA3 B10 DQ10 | DQ2 VDDQ#V12 C763 EV@220P-50V_4 MDA63 B11 DQ9 | DQ1 A2 MDB8 B11 DQ9 | DQ1 A2 MDB49 B11 DQ9 | DQ1 A2
MDA4 B11 DQ9 | DQ1 A2 MDA34 G3 DQ8 | DQ0 VDD A11 C136 EV@4700P-25V_4 MDB20 G3 DQ8 | DQ0 VDD A11 C704 EV@.1U-10V_4 MDB41 G3 DQ8 | DQ0 VDD A11 C717 EV@.1U-10V_4
MDA19 DQ8 | DQ0 VDD C273 EV@4700P-25V_4 MDA33 DQ7 | DQ15 VDD#A11 MDB23 DQ7 | DQ15 VDD#A11 MDB43 DQ7 | DQ15 VDD#A11
IN ORDER TO USE G3 A11 F2 F1 F2 F1 F2 F1
MDA18 F2 DQ7 | DQ15 VDD#A11 F1 MDA32 F3 DQ6 | DQ14 VDD#F1 F12 C149 EV@.1U-10V_4 MDB22 F3 DQ6 | DQ14 VDD#F1 F12 C92 EV@10U-10V_8 MDB42 F3 DQ6 | DQ14 VDD#F1 F12 C719 EV@10U-10V_8
DDR3 VENDOR/REVISION DQ6 | DQ14 VDD#F1 DQ5 | DQ13 VDD#F12 DQ5 | DQ13 VDD#F12 DQ5 | DQ13 VDD#F12
MDA23 F3 F12 C229 EV@.1U-10V_4 MDA35 E2 M1 MDB21 E2 M1 MDB40 E2 M1
ID FEATURE MDA20 DQ5 | DQ13 VDD#F12 MDA37 DQ4 | DQ12 VDD#M1 MDB16 DQ4 | DQ12 VDD#M1 C107 EV@22U-10V_8 MDB45 DQ4 | DQ12 VDD#M1 C93 EV@22U-10V_8
E2 M1 C3 M12 C3 M12 C3 M12
MEMORY DQ[7:0] MUST MDA16 C3 DQ4 | DQ12 VDD#M1 M12 C216 EV@10U-10V_8 MDA38 C2 DQ3 | DQ11 VDD#M12 V2 C126 EV@10U-10V_8 MDB17 C2 DQ3 | DQ11 VDD#M12 V2 MDB44 C2 DQ3 | DQ11 VDD#M12 V2
MDA21 C2 DQ3 | DQ11 VDD#M12 V2 MDA36 B3 DQ2 | DQ10 VDD#V2 V11 MDB18 B3 DQ2 | DQ10 VDD#V2 V11 C716 EV@.022U-16V_4 MDB47 B3 DQ2 | DQ10 VDD#V2 V11 C706 EV@.022U-16V_4
CONNECT TO EITHER DQ2 | DQ10 VDD#V2 DQ1 | DQ9 VDD#V11 DQ1 | DQ9 VDD#V11 DQ1 | DQ9 VDD#V11
MDA22 B3 V11 C179 EV@22U-10V_8 MDA39 B2 C159 EV@22U-10V_8 MDB19 B2 MDB46 B2
MDA[7:0] OR MDA[15:8] MDA17 DQ1 | DQ9 VDD#V11 DQ0 | DQ8 DQ0 | DQ8 DQ0 | DQ8
B2 B1 B1 B1
DQ0 | DQ8 B1 VSSQ B4 VSSQ B4 VSSQ B4
VSSQ B4 BA2 H10 VSSQ#B4 B9 BBA2 H10 VSSQ#B4 B9 BBA2 H10 VSSQ#B4 B9
BA2 H10 VSSQ#B4 B9 BA1 G9 BA2 | RAS VSSQ#B9 B12 BBA1 G9 BA2 | RAS VSSQ#B9 B12 BBA1 G9 BA2 | RAS VSSQ#B9 B12
BA1 BA2 | RAS VSSQ#B9 BA0 BA1 | BA0 VSSQ#B12 BBA0 BA1 | BA0 VSSQ#B12 BBA0 BA1 | BA0 VSSQ#B12
G9 B12 G4 D1 G4 D1 G4 D1
BA0 G4 BA1 | BA0 VSSQ#B12 D1 BA0 | BA1 VSSQ#D1 D4 BA0 | BA1 VSSQ#D1 D4 BA0 | BA1 VSSQ#D1 D4
BA0 | BA1 VSSQ#D1 D4 MAA11 L4 VSSQ#D4 D9 MAB11 L4 VSSQ#D4 D9 MAB11 L4 VSSQ#D4 D9
MAA11 L4 VSSQ#D4 D9 MAA10 K2 A11 | A7 VSSQ#D9 D12 MAB10 K2 A11 | A7 VSSQ#D9 D12 MAB10 K2 A11 | A7 VSSQ#D9 D12
MAA10 A11 | A7 VSSQ#D9 MAA9 A10 | A8 VSSQ#D12 MAB9 A10 | A8 VSSQ#D12 MAB9 A10 | A8 VSSQ#D12
K2 D12 M9 G2 M9 G2 M9 G2
MAA9 A10 | A8 VSSQ#D12 MAA8 A9 | A3 VSSQ#G2 MAB8 A9 | A3 VSSQ#G2 MAB8 A9 | A3 VSSQ#G2
M9 G2 K11 G11 K11 G11 K11 G11
MAA8 K11 A9 | A3 VSSQ#G2 G11 MAA7 L9 A8/AP | A10 VSSQ#G11 L2 MAB7 L9 A8/AP | A10 VSSQ#G11 L2 MAB7 L9 A8/AP | A10 VSSQ#G11 L2
A8/AP | A10 VSSQ#G11 A7 | A11 VSSQ#L2 A7 | A11 VSSQ#L2 A1A:Change channel B pin define A7 | A11 VSSQ#L2
MAA7 L9 L2 MAA6 K10 L11 MAB6 K10 L11 MAB6 K10 L11
MAA6 K10 A7 | A11 VSSQ#L2 L11 MAA5 H11 A6 | A2 VSSQ#L11 P1 MAB5 H11 A6 | A2 VSSQ#L11 P1 MAB5 H11 A6 | A2 VSSQ#L11 P1
MAA5 H11 A6 | A2 VSSQ#L11 P1 MAA4 K9 A5 | A1 VSSQ#P1 P4 MAB4 K9 A5 | A1 VSSQ#P1 P4 MAB4 K9 A5 | A1 VSSQ#P1 P4
MAA4 A5 | A1 VSSQ#P1 MAA3 A4 | A0 VSSQ#P4 MAB3 A4 | A0 VSSQ#P4 MAB3 A4 | A0 VSSQ#P4
K9 P4 M4 P9 M4 P9 M4 P9
M4 P9 K3 P12 K3 P12 K3 P12
K3 P12 H2 T1 H2 T1 H2 T1
MAA1 H2 A2 | A6 VSSQ#P12 T1 MAA0 K4 A1 | A5 VSSQ#T1 T4 MAB0 K4 A1 | A5 VSSQ#T1 T4 MAB0 K4 A1 | A5 VSSQ#T1 T4
MAA0 A1 | A5 VSSQ#T1 A0 | A4 VSSQ#T4 A0 | A4 VSSQ#T4 A0 | A4 VSSQ#T4
K4 T4 T9 T9 T9
A0 | A4 VSSQ#T4 VSSQ#T9 CSB0_0# VSSQ#T9 VSSQ#T9
T9 F9 T12 F9 T12 F9 T12
VSSQ#T9 22 -CSAb0 CS | CAS VSSQ#T12 22 -CSB0 CS | CAS VSSQ#T12 22 -CSBb0 CS | CAS VSSQ#T12
-CSA0 F9 T12 A3 A3 A3
22 -CSA0 CS | CAS VSSQ#T12 VSS VSS VSS
A3 H9 A10 WEB0# H9 A10 H9 A10
C VSS 22 -WEA1 WE | CKE VSS#A10 22 -WEB WE | CKE VSS#A10 22 -WEB1 WE | CKE VSS#A10 C
-WEA H9 A10 G1 G1 G1
22 -WEA WE | CKE VSS#A10 VSS#G1 VSS#G1 VSS#G1
G1 H3 G12 RASB0# H3 G12 H3 G12
VSS#G1 22 -RASA1 RAS | BA2 VSS#G12 22 -RASB RAS | BA2 VSS#G12 22 -RASB1 RAS | BA2 VSS#G12
-RASA H3 G12 L1 L1 L1
22 -RASA RAS | BA2 VSS#G12 VSS#L1 VSS#L1 VSS#L1
L1 F4 L12 CASB0# F4 L12 F4 L12
VSS#L1 22 -CASA1 CAS | CS VSS#L12 22 -CASB CAS | CS VSS#L12 22 -CASB1 CAS | CS VSS#L12
-CASA F4 L12 V3 VGA_MEM_IO V3 VGA_MEM_IO V3 VGA_MEM_IO
22 -CASA CAS | CS VSS#L12 VSS#V3 VSS#V3 VSS#V3
V3 VGA_MEM_IO H4 V10 CKEB0 H4 V10 H4 V10
VSS#V3 22 CKEA1 CKE | WE VSS#V10 22 CKEB CKE | WE VSS#V10 22 CKEB1 CKE | WE VSS#V10
CKEA H4 V10
22 CKEA CKE | WE VSS#V10 J10 L23 EV@BLM18PG181SN1D_6 CLKB0# J10 L16 EV@BLM18PG181SN1D_6 J10 L54 EV@BLM18PG181SN1D_6
22 -M_CLKA1 CK 22 -M_CLKB0 CK 22 -M_CLKB1 CK
-M_CLKA0 J10 L25 EV@BLM18PG181SN1D_6 J11 K1 GDDR3_VDDA1 CLKB0 J11 K1 GDDR3_VDDA2 J11 K1 GDDR3_VDDA3
22 -M_CLKA0 CK 22 M_CLKA1 CK VDDA 22 M_CLKB0 CK VDDA 22 M_CLKB1 CK VDDA
M_CLKA0 J11 K1 GDDR3_VDDA0 K12 GDDR3_VDDA#1 K12 GDDR3_VDDA#2 K12 GDDR3_VDDA#3
22 M_CLKA0 CK VDDA VDDA#K12 VDDA#K12 VDDA#K12
K12 GDDR3_VDDA#0 RDQSA5 P3 L18 EV@BLM18PG181SN1D_6 RDQSB3 P3 L15 EV@BLM18PG181SN1D_6 RDQSB4 P3 L55 EV@BLM18PG181SN1D_6
RDQSA3 P3 VDDA#K12 L31 EV@BLM18PG181SN1D_6 RDQSA6 P10 RDQS3 | RDQS2 RDQSB0 P10 RDQS3 | RDQS2 RDQSB7 P10 RDQS3 | RDQS2
RDQSA1 P10 RDQS3 | RDQS2 RDQSA7 D10 RDQS2 | RDQS3 C125 C154 RDQSB1 D10 RDQS2 | RDQS3 C102 C103 RDQSB6 D10 RDQS2 | RDQS3 C713 C712
RDQSA0 D10 RDQS2 | RDQS3 C310 C226 RDQSA4 D3 RDQS1 | RDQS0 EV@.1U-10V_4 EV@.1U-10V_4 RDQSB2 D3 RDQS1 | RDQS0 EV@.1U-10V_4 EV@.1U-10V_4 RDQSB5 D3 RDQS1 | RDQS0 EV@.1U-10V_4 EV@.1U-10V_4
RDQSA2 RDQS1 | RDQS0 EV@.1U-10V_4 EV@.1U-10V_4 RDQS0 | RDQS1 RDQS0 | RDQS1 RDQS0 | RDQS1
D3
RDQS0 | RDQS1 WDQSA5 P2 WDQSB3 P2 WDQSB4 P2
WDQSA3 P2 WDQSA6 P11 WDQS3 | WDQS2 J12 WDQSB0 P11 WDQS3 | WDQS2 J12 WDQSB7 P11 WDQS3 | WDQS2 J12
WDQSA1 P11 WDQS3 | WDQS2 J12 WDQSA7 D11 WDQS2 | WDQS3 VSSA#J12 J1 WDQSB1 D11 WDQS2 | WDQS3 VSSA#J12 J1 WDQSB6 D11 WDQS2 | WDQS3 VSSA#J12 J1
WDQSA0 WDQS2 | WDQS3 VSSA#J12 WDQSA4 WDQS1 | WDQS0 VSSA WDQSB2 WDQS1 | WDQS0 VSSA WDQSB5 WDQS1 | WDQS0 VSSA
D11 J1 D2 D2 D2
WDQSA2 WDQS1 | WDQS0 VSSA WDQS0 | WDQS1 WDQS0 | WDQS1 WDQS0 | WDQS1
D2
WDQS0 | WDQS1 -DQMA5 N3 J3 -DQMB3 N3 J3 -DQMB4 N3 J3
-DQMA3 -DQMA6 DM3 | DM2 RFU2 -DQMB0 DM3 | DM2 RFU2 -DQMB7 DM3 | DM2 RFU2
N3 J3 A1A:Change -DQMA4~7 pin define N10 N10 N10
-DQMA1 DM3 | DM2 RFU2 -DQMA7 DM2 | DM3 -DQMB1 DM2 | DM3 -DQMB6 DM2 | DM3
N10 E10 J2 E10 J2 E10 J2
-DQMA0 DM2 | DM3 -DQMA4 DM1 | DM0 RFU1 -DQMB2 DM1 | DM0 RFU1 -DQMB5 DM1 | DM0 RFU1
E10 J2 E3 E3 E3
-DQMA2 DM1 | DM0 RFU1 VGA_MEM_IO DM0 | DM1 VGA_MEM_IO DM0 | DM1 VGA_MEM_IO DM0 | DM1
E3 V4 V4 V4
VGA_MEM_IO DM0 | DM1 V4 MEM_RST V9 RFU0 MEM_RST V9 RFU0 MEM_RST V9 RFU0
RFU0 22 MEM_RST RESET RESET RESET
MEM_RST V9 R66 R67
RESET R136 R119 EV@243/F_4 A4 R75 A4 A4
R149 R151 EV@243/F_4 A4 ZQ EV@243/F_4 ZQ R520 EV@243/F_4 ZQ
ZQ EV@2.37K_4
EV@2.37K_4 EV@2.37K_4 EV@2.37K_4
VREF = .72*VDDQ DDR3_VREF1 H1 R115 EV@0_4 VREF = .72*VDDQ DDR3_VREF2 H1 R60 EV@0_4 VREF = .72*VDDQ DDR3_VREF3 H1 R73 EV@0_4
VREF = .72*VDDQ DDR3_VREF0 R195 EV@0_4 VREF VREF VREF
H1 A9 1 2 A9 1 2 A9 1 2
VREF MF R74 MF MF
A9 1 2 H12 H12 H12
R150 H12 MF R135 C168 VGA_MEM_IO VREF#H12 GND | VDD C101 VGA_MEM_IO VREF#H12 GND | VDD R522 C710 VGA_MEM_IO VREF#H12 GND | VDD
C227 VGA_MEM_IO VREF#H12 GND | VDD EV@.1U-10V_4 EV@.1U-10V_4 EV@.1U-10V_4
136 FBGA(NORMAL) 136 FBGA(NORMAL) 136 FBGA(NORMAL)
EV@5.49K/F_4
EV@.1U-10V_4 136 FBGA(NORMAL) EV@5.49K/F_4 EV@5.49K/F_4 EV@5.49K/F_4

R89 136 FBGA R523 136 FBGA R521 136 FBGA
R201 136 FBGA EV@GDDR3-512M(500MHZ) EV@GDDR3-512M(500MHZ) EV@GDDR3-512M(500MHZ)
EV@2.37K_4 EV@GDDR3-512M(500MHZ) EV@2.37K_4 EV@2.37K_4 EV@2.37K_4 CHAN B DDR3 136BGA 16MX32 MEMORY
DDR3_VREF#1 DDR3_VREF#2 DDR3_VREF#3
DDR3_VREF#0
VREF = .72*VDDQ
VREF = .72*VDDQ
R526
VREF = .72*VDDQ VREF = .72*VDDQ (OPTIONAL MIRRORED LAYOUT
PLACE VREF DIVIDER AND CAP PLACE VREF DIVIDER AND CAP
R202 C311
CLOSE TO MEMORY R90 C117
EV@.1U-10V_4 120 ohm pullups are required on m26x and m56p
C711
EV@.1U-10V_4
CLOSE TO MEMORY R524 C708
EV@.1U-10V_4
EXAMPLE)
B EV@.1U-10V_4 EV@5.49K/F_4 EV@5.49K/F_4 EV@5.49K/F_4 B
control signals.They are not required on M52p,m54p
EV@5.49K/F_4 AKD5FW-T513 SAMSUNG GDDR3 (512M) LF
VGA_MEM_IO VGA_MEM_IO
AKD5JW-T503 SAMSUNG GDDR3 (256M)
M54/M52: BA0, 1, 2=MA12, 13, 15 AKD5FWBT^00 Infineon GDDR3(512M)
PLACE MVREF DIVIDERS M54/M52: BA0, 1, 2=MA12, 13, 15 22 -RASB
R64
R70
EV@120/F_4
EV@120/F_4
22 -RASA
R183
R86
EV@120/F_4
EV@120/F_4
M56: BA0, 1, 2=MA14, 15, 13
AND CAPS CLOSE TO ASIC 22 -RASB1 22 -RASA1
MAB14 R79 1
M56: BA0, 1, 2=MA14, 15, 13 2 EV@0_4 BBA0
R65 EV@120/F_4 R179 EV@120/F_4 MAB15 R77 1 2 EV@0_4 BBA1
22 -CASB 22 -CASA
MAA14 R144 1 2 EV@0_4 BA0 R68 EV@120/F_4 R84 EV@120/F_4 MAB13 R5271 2 EV@0_4 BBA2
22 -CASB1 22 -CASA1
MAA15 R140 1 2 EV@0_4 BA1
MAA13 R148 1 2 EV@0_4 BA2 R62 EV@120/F_4 R188 EV@120/F_4
22 -WEB 22 -WEA
R71 EV@120/F_4 R87 EV@120/F_4
22 -WEB1 22 -WEA1
R61 EV@120/F_4 R190 EV@120/F_4
22 -CSB0 22 -CSA0
R72 EV@120/F_4 R88 EV@120/F_4
22 -CSBb0 22 -CSAb0
R63 EV@120/F_4 R180 EV@120/F_4
22 CKEB 22 CKEA
R69 EV@120/F_4 R85 EV@120/F_4
22 CKEB1 22 CKEA1
+1.8V VGA_MEM_IO
B1B:Remove JP5,connect +1.8V to VGA_MEM_IO
R76 EV@60.4/F_4 R204 EV@60.4/F_4

22 -M_CLKB0 22 M_CLKA0
R78 EV@60.4/F_4 R203 EV@60.4/F_4
22 M_CLKB0 22 -M_CLKA0
R528 EV@60.4/F_4 R91 EV@60.4/F_4

22 -M_CLKB1 22 M_CLKA1
R525 EV@60.4/F_4 R92 EV@60.4/F_4
22 M_CLKB1 22 -M_CLKA1
Use 60 ohm pull-up to VDDQ on memory side(CLOCK)
Pull up resistor must be

close to the memory side
A A
PROJECT : ZC1
VGA(VEDIO MEM A&B-DDR3) 1A

5 4 3 2 1
om
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ai
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ho
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in
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1 2 3 4 5 6 7 8
GPIO[13..0] OPTION STRAPS

19 GPIO[13..0]
GPIO_[13:0] have internal PD
A1A:Change GPIO0 to high M56-P Strap
+3V
GPIO0 R109 EV@10K_4

STRAPS PIN DESCRIPTION OF RECOMMENDED SETTING RECOMMENDED
GPIO1 R536 EV@10K_4 STRAP_B_PTX_PWRS_ENB TRANSMITTER POWER SAVINGS ENABLE INSTALL

Overlap pads to save space GPIO0
- FULL TX OUTPUT SWING 10K RESISTOR
and to prevent assembly of

both resistors. GPIO2 R537 *10K_4 TRANSMITTER DE-EMPHASIS ENABLE
A A
STRAP_B_PTX_DEEMPH_EN GPIO1 FOR M26X,M50P: INSTALL WITH TBD
ATI RS480,RS400,RX480,
RC410,RS482 CHIPSETS
Layout GPIO3 R103 *10K_4 DO NOT INSTALL WITH INTEL 915PM CHIPSET
FOR M5X - INSTALL
RSVD GPIO(3:2) NO ATI FEATURE ENABLED DO NOT INSTALL

10K RESISTORS
Ground High logic voltage GPIO4 R539 *10K_4
Signal B1B:Stuff R540 for GPIO5

GPIO5 R540 10K_4
DO NOT INSTALL
REVERSE LANES GPIO4 NO DEBUG ACCESS (M52P,M54P,M56P) 10K RESISTOR
DEBUG ACCESS
GPIO6 R538 *10K_4
Add Text "Populate to Enable Debug"

Beside JU23 on Silkscreen.
STRAP_FORCE_COMPLIANCE
GPIO8 R117 *10K_4 RSVD GPIO5 sets the desired PCIE PLL bandwidth for M5x parts DO NOT INSTALL
10K RESISTOR
COMMON MODE RANGE GPIO6 NO ATI FEATURE ENABLED (M52P,M54P,M56P) DO NOT INSTALL
GPIO9 R113 EV@10K_4 10K RESISTOR
R107 *10K_4
DEBUG ACCESS DO NOT INSTALL

FORCE_COMPLIANCE GPIO8 DON'T FORCE COMPLIANCE STATE(M52P,M54P,M56P) 10K RESISTOR
GPIO11 R105 EV@10K_4
BOM
B R100 *10K_4 B
GPIO[13:12] = 00:128M memory aperture ROMIDCFG(3:0) GPIO(9,13:11) IF NO ROM GPIO11(M26X) AND GPIO12,13(M52,M54,M56) SET MEMORY APERTURE SIZE A1A:change ROMIDCFG(3:0) to 0010
GPIO[13:12] = 01:256M memory aperture GPIO12 R542 EV@10K_4 MEMORY APERTURE SIZE 000x - No ROM, MEM_AP_SIZE=00(128MB)
GPIO[13:12] = 10:64M memory aperture 001x - No ROM,MEM_AP_SIZE=01(256MB)
R541 EV@10K_4 010x - No Rom, MEM_AP_SIZE=10(64MB)
GPIO[13:12] = 11:Reversed 011x - No ROM,MEM_AP_SIZE=11(Reserved)
GPIO13 R112 EV@10K_4 1000 - Parallel ROM, chip IDis from ROM
1001 - Serial AT25F1024 ROM (Atmel), chip IDis from ROM
R116 EV@10K_4 1010 - Serial AT45DB011 ROM (Atmel), chip IDis from ROM
1011 - Serial M25P10 ROM (ST), chip IDis from ROM
1100 - Serial M25P05 ROM (ST), chip IDis from ROM
R155 EV@10K_4 1100 - Serial NX25F011B ROM (ISSI), chip IDis from ROM
19,26 VSYNC_DAC1
R158 *10K_4
Indicates if any slave VIP host devices drove this pin
low during reset. 0- Slave VIP host port deviced
VIP_DEVICE VSYNC present. 1-No slave VIP port devices reporting presence No default
R164 EV@10K_4 during reset
19,26 HSYNC_DAC1
R168 *10K_4
R531 EV@10K_4
GPIO26 NO STRAP FUNCTION H2SYNC, ATI FEATURE NOT ENABLED (M52P,M54P,M56P) DO NOT INSTALL
R530 EV@10K_4 V2SYNC,GENERICC 10K RESISTOR
19 MEMTYP_0
BOM R131 EV@10K_4

GPIO25
Memory ID VSYNC RSVD
R124 EV@10K_4
19 MEMTYP_1
HSYNC RSVD
R157 *10K_4 RSVD

19 GENERICC
PCIE_TEST
R163 EV@10K_4
C C
Board Straps REV. 0.3

STRAPS PIN DESCRIPTION VALUE
MEMORY TYPE AND SPEED SELECT

MEMTYPE(1:0) GPIO25,26 Memory connected to R420 identification for BIOS 00
00 - Samsung GDDR 3 memory(256Mb) 136 Ball BGA package MEMORY TYPE AND SPEED SELECT
VGA_MEM_IO +3V VGA_MEM_IO 01 - Samsung GDDR 3 memory(512Mb) 136 Ball BGA package
R544 *10K_4 10 - Infineon GDDR 3 memory(256Mb) 136 Ball BGA package
R532 EV@10K_4 R108 EV@10K_4 11 - Infineon GDDR 3 memory(512Mb) 136 Ball BGA package
R535 EV@10K_4 R101 EV@10K_4
DC_Strap1 GPIO(10) Internal TMDS Enabled
0 - Disabled
1 - Enabled
19 DEMUX_SEL 1
DC_Strap4 19 19 DC_Strap3
DC_Strap1
DC_Strap2 19 19 GPIO10
DC_Strap2 LCDDATA(13) Video Capture Enabled
0 - Disabled 1
1 - Enabled
R534 *10K_4 R106 *10K_4
R533 *10K_4 R114 *10K_4
R118 EV@10K_4 DC_Strap3 LCDDATA(14) HDTV out detect 1
0 - Detected
1 - Not detected
D D
DC_Strap4, LCDDATA(15,19) Video capture enable

A1A:change video capture DEMUX_SEL 00 - DAC2 Off
enable setting 01 - DAC2 On as CRT 10
10 - DAC2 On as TVOUT
11 - DAC2 On as TVOUT and CRT
PROJECT : ZC1
PAL/NTSC LCDDATA(18) TVO Standard Default (Resistor pull-up and switch short to GND) 1
0 - PAL (on board resistor pull-down and switch closed)
1 -NTSC (on board resistor pull-up) Quanta Computer Inc.
M56P OPTION STRAPS 1A

1 2 3 4 5 6 7 8
5 4 3 2 1
TV_C/R_SYS TV_Y/G_SYS TV_COMP_SYS

DVI-I CONNECTOR (DVI-D)
+5V For EMI
3
CN22 RP4 0_4P2R_S
TX2-_OB_R 1 2 TX2+_OB_R 3 4 TX2+_OB
1 2 TX2-_OB_R TX2-_OB
3 4 1 2
3 4
5 6 DVI_DDCCLK 32
5 6
2
32 DVI_DDCDATA 7 8
F2 TX1-_OB_R 7 8 TX1+_OB_R TX1+_OB D16 D18 D17
9 10 3 4
9 10 TX1-_OB_R TX1-_OB DA204U DA204U DA204U
11 12 1 2
POLY_SWITCH_1.1A 11 12 +5V_DIN RP3 0_4P2R_S
13 14 +3V +3V +3V
13 14
Place close to 15 16 R8 20K_4 DVI_DET RP2 0_4P2R_S
2
TX0-_OB_R 15 16 TX0+_OB_R TX0+_OB
the connector 17 18 3 4 Reverse type A1A:Change to 75 ohm
BLM18PG181SN1D_6 17 18 TX0-_OB_R TX0-_OB
19 20 1 2
D
L6 19 20 CN20
D
21 22
+5V_DIN_DVI +5V_DIN CLK+_OB_R 21 22 CLK-_OB_R CLK-_OB
23 24 3 4
23 24
5
25 26 CLK+_OB_R 1 2 CLK+_OB L5 BLM18PG181SN1D_6 L3 BLM18PG181SN1D_6
25 26 RP5 0_4P2R_S TV_C/R_SYS TV-CHROMA TV-LUMA TV_Y/G_SYS
6 4
5
6 4
C14 C13 SUYIN 070939FR024S535PR_DVI

.1U-10V_4 B1B:Change DVI connector pin 25,26 to ground S-VIDEO R6 C645 C11 9 8 C9 C647 R4
.1U-10V_4 9 8
6P-50V_4 6P-50V_4 6P-50V_4 6P-50V_4
150/F_4 150/F_4
DVI PORT 3
3 1
2
U5
2
+3V 31
0B1 DVI_CLK- 32
+3V +3V 30
1B1 DVI_CLK+ 32
030107FR007S112FR_TV_OUT
35 26 L4 BLM18PG181SN1D_6
R454 R453 VDD 2B1
3B1
25
DVI_TX0- 32
DVI_TX0+ 32 TO EZ4 TV Out (SVHS) MiniDIN 7-pin TV-COMP TV_COMP_SYS
10K_4 100K_4 36 22 A1A:Change SVIDEO footprint to

19 TXCM_EX A0 4B1 DVI_TX1- 32
1 21 SV-030107FR007S108FU-RVS-7P R5
19 TXCP_EX A1 5B1 DVI_TX1+ 32
TMDS_HPD C10 C646
19,32 TMDS_HPD
2 18 C2A:Change CN20 SVIDEO p/n to DFMD07FR206 150/F_4
19 TX0M_EX A2 6B1 DVI_TX2- 32
3
3 17 6P-50V_4 6P-50V_4
19 TX0P_EX A3 7B1 DVI_TX2+ 32
E3B:Change R4,R5,R6 to 150 ohm for TV can't detect issue
Q25 Q3 7 12
19 TX1M_EX A4 0LED1
2 2 DVI_DET 8 13
19 TX1P_EX A5 1LED1
2N7002 2N7002 14
2LED1
19 TX2M_EX 9
+3V A6 CLK-_OB
19 TX2P_EX 10 29
A7 0B2 CLK+_OB U29
28
1
1B2 +5V
4 16
LED0 TX0-_OB TV_Y/G VCC TV_Y/G_SYS
5 24 4 2
R773 LED1 2B2 TX0+_OB C_A A0 TV_Y/G_PR
6 23 3 TV_Y/G_PR 32
LED2 3B2 TV_C/R A1 TV_C/R_SYS
7 5
D41 BAS316 10K_4 TX1-_OB C_B B0 TV_C/R_PR
C 20 6 TV_C/R_PR 32
C
4B2 TX1+_OB TV_COMP B1 TV_COMP_SYS
16,28,32 DOCKIN# 1 2 27 19 9 11
SEL 5B2 C_C C0 TV_COMP_PR
10 TV_COMP_PR 32
TX2-_OB C1
16 12 14
6B2 TX2+_OB C_D D0
15 13
7B2 PR_INSERT_5V D1
11 26,32 PR_INSERT_5V 1
GND SE
34 15 8
0LED2 EN# GND
D2B:Add D41,R773 to resolve WOL issue 33
1LED2
32
2LED2 SN74CBT3257PWR
MAX4892
A1A:Change to SN74CBT3257PWR(Vin 5V)
SEL FUN
H B2
R464 EV@0_4 TV_Y/G
19 Y_DAC2
L B1
R472 EV@0_4 TV_C/R
19 C_DAC2
R476 EV@0_4 TV_COMP
19 COMP_DAC2
+3V
R10
0_8
+3V A1A:Reserved +2.5V for low power panel
+3V_LCDVCC
C26 U3
TRACE 80MIL
R663
10K_4 EV@.1U-10V_4 6 1 LCDVCC_1 R474 0_8 LCDVCC
IN OUT
Pull high to +3V_S5 at SB internal
D22 4 2 C16 C17 C82 C81 C673
DISPON LID591# IN GND
2 1 LID591# 16,39,40
DISP_ON 3 5 EV@.1U-10V_4 EV@.1U-10V_4 10U-10V_8
B 20 LVDS_DIGON ON/OFF GND B
BAS316 A1A:Change lid sw to button board 10U-10V_8 EV@.01U-16V_4
D2B:Add R676 for LCDVCC power control
D25 E3B:Add R787(LVDS_BLON_EC) to EC IOPD2 for S3 workaround D2C:Change R676 to 1K(CS21002JB34) R676 AAT4280IGU-3-T1
2 1 LVDS_BLON 1 2 for LCDVCC control
LVDS_BLON_EC 39
R787 0_4 1K_4
BAS316
R674 CN4
TXUCLKOUT- TXUOUT2-
20 TXUCLKOUT- 1 21 TXUOUT2- 20
R397 *1K_4 1K_4 C1C:Add for VGA backlight control TXUCLKOUT+ TXUOUT2+
20 TXUCLKOUT+ 2 22 TXUOUT2+ 20
3
D2B:Remove R397 for VGA backlight control 3 23

E3A:Change R397 from 100K to 1K for boot white screen issue 20 TXUOUT0- TXUOUT0- TXUOUT1-
4 24 TXUOUT1- 20
2 20 TXUOUT0+ TXUOUT0+ TXUOUT1+
EC_FPBACK# 39 5 25 TXUOUT1+ 20
Q39
DTC144EUA TXLOUT2-
6 26 INVCC0 R51 0_8 VIN
A1A:Add 100k to ground 20 TXLOUT2-
TXLOUT2+ 7 27
20 TXLOUT2+
1
8 28 VADJ L53
9 29 CONTRAST 39
20 TXLOUT1- TXLOUT1- DISPON BLM18PG181SN1D_6
TXLOUT1+ 10 30 CCD_POWER C699 EV@.1U-10V_4
A1A:Add for prevent panel blinking 20 TXLOUT1+ 11 31 CCDUSBP7-
+3V +3V TXLOUT0- 12 32 CCDUSBP7+ CCDUSBP7+
A1A:Change LVDSCLK,LVDSDATA 20 TXLOUT0- 3 4 USBP7+ 15
TXLOUT0+ 13 33 CCDUSBP7-
pull high voltage 20 TXLOUT0+ 1 2 USBP7- 15
14 34 LCDVCC RP6 0_4P2R_S
TXLCLKOUT- 15 35
20 TXLCLKOUT- 16 36
+3V TXLCLKOUT+
20 TXLCLKOUT+ 17 37 +5V VIN
R662
*10K_4 LCD_EDIDCLK R48 18 38
A1A:change to 4.7K 1 2 0_4
LCD_EDIDDATA R49 19 39
1 2 0_4 +3V
R672 R53 20 40
41 43
1
*10K_4 DISPON C90 C91
45
46
4.7K_4 42 44
+
3
1000P-50V_4
10U-25V_1210
2
2 LCD_EDIDCLK FOXCONN_LVDS
19 LVDS_CLK
Q41 A1A:Change LVDS conn
*DTC144EUA p/n to DFHS40FS736
3
A
20 LVDS_BLON 2 CAMERA MODULE CONNECTOR A
Q42 Q10
*DTC144EUA +3V AO3403
D44
1
A1A:change to 4.7K +5V 2 1 1 3 CCD_POWER
om
R54 C83 10U-10V_8
l.c
*BAS316
C698 1000P-50V_4
2
4.7K_4
ai
+3V R509 0_8
tm
19 LVDS_DAT
LCD_EDIDDATA
CCD_POWERON# 39 PROJECT : ZC1
ho
D2B:Add R509 for camera module +5V
f@
in
xa
LVDS DVI-I TV-OUT CONNECTOR 1A
he
5 4 3 2 1
1 2 3 4 5 6 7 8
+5V
near switch U31
16 +5V
VCC
C683
C51
C666
VGA_RED 4 2 VGA_RED_SYS
C_A A0 VGA_RED_PR
3 VGA_RED_PR 32
VGA_GRN A1 VGA_GRN_SYS
7 5
R463 EV@0_4 VGA_RED C_B B0 VGA_GRN_PR
19 R_DAC1 6 VGA_GRN_PR 32
B1
EV@.1U-10V_4
EV@.1U-10V_4
EV@.1U-10V_4
R462 EV@0_4 VGA_GRN VGA_BLU 9 11 VGA_BLU_SYS
19 G_DAC1 C_C C0
R483 EV@0_4 VGA_BLU 10 VGA_BLU_PR
19 B_DAC1 C1 VGA_BLU_PR 32
12 14
C_D D0
13
PR_INSERT_5V D1
25,32 PR_INSERT_5V 1
SE
15 8
EN# GND
A 19,24 VSYNC_DAC1
RN6 3 4 EV@0_4P2R_S VSYNC A
1 2 HSYNC SN74CBT3257PWR
19,24 HSYNC_DAC1
RN7 3 4 EV@0_4P2R_S CRTDDAT A1A:Change to SN74CBT3257PWR(Vin 5V)

19 CRT1DDCDATA CRTDCLK
19 CRT1DDCCLK 1 2
SEL FUNCTION
LOW IN_B0
HIGH IN_B1
B1B:Remove UMA CRT support
B B
C37 EV@.1U-10V_4
B1B:Change CRT p/n to DFHS15FR057
Reverse type
F3
2 1 CRTVDD2 2 1 CRTVDD3 CN23
16
+5V
D3 SSM14
POLY_SWITCH_1.1A
25 MIL
6
VGA_RED_SYS L2 BLM18BA220SN1_6 CRT_R1 1 11 A1A:delete CRT_SENSE#
T2
7
VGA_GRN_SYS L13 BLM18BA220SN1_6 CRT_G1 2 12
8
VGA_BLU_SYS L14 BLM18BA220SN1_6 CRT_B1 3 13
9
4 14
R2 C642 R18 C34 R24 C39 C677 C672 C643 10
5 15
150/F_4 150/F_4 10P-50V_4 10P-50V_4 10P-50V_4
150/F_4 10P-50V_4 10P-50V_4 10P-50V_4
CRT
C 17 C
A1A:Change to 75 ohm
PLACE RGB TERMINATION RESISTORS,FILTERING CLOSE TO CONNECTOR
E3B:Change R2,R18,R24 to 150 ohm for CRT can't detect issue
+3V VSYNC_EZ4 32
HSYNC_EZ4 32
B1B:Change U30 pin1,8,9,12 to CRTVDD3
U30
R23 R22 CRTVDD3 1 16 L52 BLM18BA220SN1_6 CRTVSYNC
VCC_SYNC SYNC_OUT2 L51 BLM18BA220SN1_6 CRTHSYNC
14
2.2K_4 2.2K_4 SYNC_OUT1
+5V 7
CRTVDD3 VCC_DDC C681 C679
8
BYP VSYNC
15
CRTDCLK SYNC_IN2 HSYNC 10P-50V_4
+3V 2 13
VCC_VIDEO SYNC_IN1 CRTVDD3 10P-50V_4
CRTDDAT
VGA_RED_SYS 3 10 CRTDCLK R482 R3
VGA_GRN_SYS VIDEO_1 DDC_IN1 CRTDDAT
A1A:Pull high to 3.3V 4
VIDEO_2 DDC_IN2
11
VGA_BLU_SYS 5 2.7K_4 2.7K_4
VIDEO_3 DDCCLK_1
9 DDCCLK_1 32
DDC_OUT1 DDCDAT_1
6 12 DDCDAT_1 32
D
GND DDC_OUT2 D
CM2009-02QR
C684 C644
10P-50V_4 10P-50V_4
PROJECT : ZC1
CRT-PORT 1A

1 2 3 4 5 6 7 8
5 4 3 2 1
LANVCC
B1B:Add R723,C959 for LAN_PWR_GOOD A1A:Change GLAN from PCIE5 to PCIE1
U35A C692
PCIE_TXP5 F2 C13 TRD0+ C693
15 PCIE_TXP1 PE_R0p--NC MDI0p--TDP
PCIE_TXN5 F1 C14 TRD0- .1U-10V_4
15 PCIE_TXN1 PE_R0n--NC MDI0n--TDN
Enternet Port
R723 E13 TRD1+ A1A:Place termination resistors and caps as LANMDI3 .1U-10V_4 LANMDI2
100K_4 PCIE_RXP5 C75 .1U-10V_4 MDI1p--RDP TRD1-
D1 E14
PCI Express
15 PCIE_RXP1 PE_T0p--NC MDI1n--RDN close to LAN controller as possible
LAN_PWR_GOOD PCIE_RXN5 C76 .1U-10V_4 C1 F13 TRD2+ R507 R506 R504 R502
15 PCIE_RXN1 PE_T0n--NC MDI2p--NC
F14 TRD2-
C959 CLK_PCIE_LAN MDI2n--NC TRD3+
2 CLK_PCIE_LAN G1 H13
CLK_PCIE_LAN# PE_CLKp--NC MDI3p--NC TRD3- 49.9/F_4 49.9/F_4 49.9/F_4 49.9/F_4
2 CLK_PCIE_LAN# G2 H14
1U-16V_6 PE_CLKn--NC MDI3n--NC TRD3-
TRD3- 28
PLTRST# P7 A1A:Installed R484 when use shared mode TRD3+
15,16,18,29,32,33,38,39 PLTRST# PE_RST#--NC TRD3+ 28
PCIE_WAKE_LAN P10 B10 NVM_CS#
PE_WAKE#--NC NVM_CS#--NC NVM_SK_LAN TRD2-
C9 TRD2- 28
R516 *0_4 LAN_PWR_GOOD NVM_SK--NC NVM_SI_LAN TRD2+
after all power rail OK 80ms 16 ICH_PWROK P5
LAN_PWR_GOOD--NC NVM_SI--NC
A9 TRD2+ 28
R517 *0_4 DEVICE_OFF# L7 B9 NVM_SO_LAN
16,39 RSMRST#
NVM/EEPROM
DEVICE_OFF#--ADV10/LAN_DIS_N NVM_SO--NC R484 *0_4 NAV_ARB TRD1-
Control
B4 T86 TRD1- 28
D
LAN_DISABLE_A13 NVM_REQ--NC TRD1+
D
Stuff R488 for D3 wake up A13
TEST_EN--TEST_EN TRD1+ 28
T3 LAN_DISABLE_D10 D10 Install R487 to disable NVM protection
LANVCC LAN_DISABLE_D12 NC--ISOL_TEX R487 0_4 TRD0-
D12
PHY_REF--ISOL_TI NVM_PROT--NC
A5 Install to use SPI FLASH TRD0- 28
LAN_DISABLE_D14 D14 A6 R31 3.3K_4 TRD0+
R34
T6
*3.3K_4 DOCK_IND NC--ISOL_TCK NVM_TYPE--NC R37 *3.3K_4
(Tekoa only) TRD0+ 28
C3 D3
R488 3.3K_4 AUX_PRESENT DOCK_IND--NC NVM_SHARED--NC_D3 R492 R493 R500 R501
C6
AUX_PRESENT--NC Install when sharing SPI
R35 *3.3K_4 R491 *619 LINK_100_LED#
Flash with the ICH7
B14 B11 LINK_100_LED# 28
R490 *649 PHY_TSTPT--RBIAS10 LED0#--SPDLED LINK/ACT-ACT_LED# 49.9/F_4 49.9/F_4 49.9/F_4 49.9/F_4
B13 C11
LEDs
Test
PHY_HSDACn-RBIAS100 LED1#--ACTLED LINK/ACT-ACT_LED# 28
A1A:Leave ball C3, DOCK_IND,unconnected. This R489 *0_4 B12 A12 LINK_1000-LINK_UP_LED# LANMDI0 LANMDI1
PHY_HSDACp-TOUT LED2#--LILED LINK_1000-LINK_UP_LED# 28
feature is not supported in the 82573. Reserved for82562 N10
ALT_CLK125--NC C689 C690
JTAG 82570EI
R519 0_4 SMB_ALRT#/ASF_PWRGOOD N11 N4 JTAG_TMS
16 SMB_ALERT# SMB_ALRT#/ASF_PWRGOOD--NC JTAG_TMS--NC T104
SMBus
P11 P4 JTAG_TDI .1U-10V_4 .1U-10V_4
SMB_CLK-NC JTAG_TDI--NC T105
R514 *3.3K_4 M11 N5 JTAG_TCK
16 ICH_PWROK SMB_DATA-NC JTAG_TCK--NC T101
P6 JTAG_TDO
JTAG_TDO--NC T98
Monitoring
2,16,29,32,33,35 PCLK_SMB
Thermal
2,16,29,32,33,35 PDAT_SMB L2
R38 *0_4 THERMn--NC
L3 M12 T102
THERMp--NC NC--LAN_RXD[2]
Pull up to +3V_S5 on SB side N13
LAN Connect Interface

NC--LAN_RXD[1] T99
P13 T103
NC--LAN_RXD[0]
A1A:Add PCIE_WAKE# circuit T88 A8
SDP Pins
C697 22P-50V_4 SDP0--NC
T89 B8 L14 T92
SDP1--NC CLK_VIEW--LAN_TXD[2]
T7 C8 L13 T95
SDP2--NC NC--LAN_TXD[2]
1
T5 C7 M14 T94
LANVCC Y5 SDP3--NC NC--LAN_TXD[0]
+-30PPM
25MHZ M13
NC--LAN_RSTSYNC T97
Crystal
XTAL1 K14
2
C696 22P-50V_4 XTAL2 XTAL1--X1 +3V_S5 LANVCC

J14 N14 T96
XTAL1--X2 NC--LAN_CLK
2
R518 PC82573E R19 0_8

4.7K_4
+3V
PCIE_WAKE_LAN 1 3 PCIE_WAKE# 16,29,39
SMB_ALERT# R391 *10K_4
Q30 A1A:No_Stuff R391,It is for Tekoa Validation support only add suport S5 wake up on LAN solution
C C
DTC144EUA LANVCC
Dedicated LAN Flash LAN_1.2V
C38 .1U-10V_4
U35B
A1A:add 47 ohms for SPI EEPROM program A1 A10
U32 VSS--NC_A1 VCC1.2--NC-A10
B3 C5
NVM_CS# VSS--VSS_B3 VCC1.2--NC-C5 C71 C73 C72
1 8 B7 C4
NVM_SK_LAN R28 47_4 NVM_SK CE# VDD R20 NC--VSS_B7 VCC1.2--NC-C4 C87
6 C2 F12
NVM_SI_LAN R29 47_4 NVM_SI SCK 3.3K_4 VSS--NC_C2 VCC1.2--NC-F12 .1U-10V_4 .1U-10V_4 .1U-10V_4 4.7U-10V_6 LANVCC
5 C10 G6
NVM_SO_LAN R21 47_4 NVM_SO SI VSS--VSS_C10 VCC1.2--VCC3.3_G6
2 7 C12 G12
SO HOLD# VSS--VSS_C12 VCC1.2--NC-G12
D2 G13
VSS--NC_D2 VCC1.2--VCC3.3_G13
A1A:These resistors should be 3 4 D4 H6
WP# VSS VSS--VSS_D4 VCC1.2--VCC3.3_H6 L7
placed less than 0.5" from D5 H7
R26 SST25LF080A VSS--VSS_D5 VCC1.2--VCC3.3_H7 FCM2012VF-131DC10_8
D6 H8
the Shared Flash VSS--VSS_D6 VCC1.2--VCC3.3_H8
8.2K_4 D7 H11 130 ohms@100Mhz
R25 3.3K_4 VSS--VSS_D7 VCC1.2--VCC3.3_H11
LANVCC D8 H12
VSS--VSS_D8 VCC1.2--NC_H12
D13 J6
VSS--VSS_D13 VCC1.2--VCC3.3_J6
B1B:Change U32(SST25LF080) WP# to LANVCC E2 J7
VSS--VSS_E2 VCC1.2--VCC3.3_J7 LAN_2.5V_L
E4 J8
VSS--VSS_E4 VCC1.2--VCC3.3_J8
E5 J9
VSS--VSS_E5 VCC1.2--VCC3.3_J9 C678
E6 J10
VSS--VSS_E6 VCC1.2--VCC3.3_J10 C27 C674 C671
E7 J11
NVM_CS# VSS--VSS_E7 VCC1.2--VCC3.3_J11 4.7U-10V_6 22U-6.3V_8
E8 K3
VSS--VSS_E8 VCC1.2--VCC_K3
3
NVM_SK_LAN E9 K4 .1U-10V_4 10U-6.3V_8
NVM_SI_LAN VSS--VSS_E9 VCC1.2--VCC_K4
E10 K5
NVM_SO_LAN VSS--VSS_E10 VCC1.2--VCC3.3_K5 CTRL_2.5 MMJT9435T1G
K6 1
VCC1.2--VCC3.3_K6 Q5 LAN_2.5V
F4 K7 297mA
VSS--VSS_F4 VCC1.2--VCC3.3_K7
F5 K8
F6 K9
2
4
1
C52 C59 C54 C53 F7 K10

VSS--VSS_F7 VCC1.2--VCC3.3_K10 R30
F8 K11 B1B:Change Q5,Q28 footprint to SOT-223(SMT issue)
VSS Pins
VCC Pins
33P-50V_4 33P-50V_4 VSS--VSS_F8 VCC1.2--VCC3.3_K11

F9 L5
2
33P-50V_4 33P-50V_4 VSS--VSS_F9 VCC1.2--VCC3.3_L5 C69 C49

F10 L9
VSS--VSS_F10 VCC1.2--VCC3.3_L9 LANVCC C44 1_12
F11 L10
VSS--VSS_F11 VCC1.2--VCC3.3_L10 10U-6.3V_8 .1U-10V_4 .1U-10V_4
G4 A2
VSS--NC_G4 IREG2.5_IN--NC_A2
A1A:These capacitors should be G7 A3
B VSS--VSS_G7 IREG2.5_IN-A3 C78 C58 C67 C56 C48
B
placed less than 0.5" from G8 A7
VSS--VSS_G8 VCC3.3--VCC_A7 C682 C86 10U-6.3V_8
G9 D9
the LAN Controller VSS--VSS_G9 VCC3.3--NC_D9 10U-6.3V_8 .1U-10V_4 .1U-10V_4
G10 E1
VSS--VSS_G10 NC--VCC_E1 10U-6.3V_8 .1U-10V_4 .1U-10V_4
G11 E11
VSS--VSS_G11 NC--VCCT_E11
G14 E12
VSS--VSS_G14 NC--VCCT_E12 LANVCC
H9 F3
VSS--VSS_H9 VCC3.3--NC_F3 LAN_2.5V
H10 J4
VSS--VSS_H10 VCC3.3--NC_J4
K2 L4
LAN Disable Circuit K12
VSS--VSS_K2 NC--VCC_L4
M2 M2(Fuse Supply). This should be connected L50
NC--VSS_K12 FUSEV--NC FCM2012VF-131DC10_8
L6 M10 to 2.5V for normal operation.
LAN_DISABLE_A13 NC--VSS_L6 VCC3.3--NC_M10
L11
NC--VSS_L11 VCC3.3--VCC_N6
N6 130 ohms@100Mhz
LAN_DISABLE_D12 M6 N8
NC--VSS_M6 VCC3.3--VCC_N8 LAN_1.2V_L
N1 P2
VSS--VSS_N1 VCC3.3--VCC_P2 LAN_2.5V
N12 P12
VSS--VSS_N12 VCC3.3--VCC_P12
P8
VSS--VSS_P8 C676 C675 C669 C664
A11
R33 R36 VCC2.5--VCC_A11 4.7U-10V_6 22U-6.3V_8
B6
3.3K_4 4.99K/F_4 VCC2.5--NC_B6 C70 C79 C88 R473 .1U-10V_4 10U-6.3V_8
G3
VCC2.5--NC_G3 C89 C47 1_12
G5 reduce the ripple
VCC2.5--VCCR_G5 4.7U-10V_6
.1U-10V_4
.1U-10V_4
.1U-10V_4
H4
VCC2.5--NC_H4 4.7U-10V_6
H5
VCC2.5--VCCR_H5
J5
VCC2.5--VCC3.3_J5
J12
VCC2.5--NC_J12
3
K13
LANVCC VCC2.5--VCC_K13 LANVCC
L12
VCC2.5--NC_L12 CTRL_1.2 MMJT9435T1G
Voltage M4 1
VCC2.5--NC_M4 LAN_2.5V Q28
Regulation N7
VCC2.5--NC_N7
No Connects
B1 R485 LAN_1.2V 551mA
2
4
VCC2.5_OUT--NC_B1 *3.3K_4
B2
VCC2.5_OUT--NC_B2 CTRL_1.2
P3
NC--NC_D11
NC--NC_P14
NC--NC_J13
T100
TEST10--NC
TEST11--NC
TEST12--NC
TEST13--NC
TEST14--NC
TEST15--NC
TEST16--NC
CTRL_1.2--NC
NC--NC_M5
NC--NC_M7
NC--NC_M9
NC--NC_N9
NC--NC_L8
TEST0--NC
TEST1--NC
TEST2--NC
TEST3--NC
TEST4--NC
TEST5--NC
TEST6--NC
TEST7--NC
TEST8--NC
TEST9--NC
R55 A4 CTRL_2.5 T4
1K_4 CTRL_2.5--NC R457 C685 C663
B5
EN2.5REG--NC_B5 C665
R56 *0_4 DEVICE_OFF# 4.7U-10V_6 .1U-10V_4 .1U-10V_4
16 LAN_DISABLE#
R486 Install to disable 1_12
PC82573E 3.3K_4 Internal 2.5V regulator compensate for undershoot
H1
H2
H3
J1
J2
J3
K1
L1
M1
M3
N2
P1
N3
M8
P9
E3
A14
D11
J13
L8
M5
M7
M9
N9
P14
A A
R57
*1K_4 C648
10U-6.3V_8
om
l.c
A1A:Stuff R57 and not stuff R55 to disable LAN
ai
GPIO24(Not cleared by CF9h reset event
tm
defaults to high on power up, is powered from
PROJECT : ZC1
ho
the resume well, and retains its value during
f@
PCI reset
in
xa
Gigalan Tekoa 82573E 1A
he
5 4 3 2 1
5 4 3 2 1
A1A:Place capacitor near

LANVCC LAN_2.5V
transformer pin 1,4,7,10
C687 .1U-10V_4 U34
C686 .1U-10V_4 31 X-TX0P-PR
0B1 X-TX0N-PR X-TX0P-PR 32
C688 .1U-10V_4 30 C84 C74 C80 C85
1B1 X-TX0N-PR 32
35 26 X-TX1P-PR .1U-10V_4 .1U-10V_4 .1U-10V_4 .1U-10V_4
VDD 2B1 X-TX1N-PR X-TX1P-PR 32
25 X-TX1N-PR 32
3B1
D TRD0+ X-TX2P-PR D
27 TRD0+ 36 22 X-TX2P-PR 32
TRD0- A0 4B1 X-TX2N-PR
27 TRD0- 1 21 X-TX2N-PR 32
A1 5B1
27 TRD1+ TRD1+ X-TX3P-PR
2 18 X-TX3P-PR 32
TRD1- A2 6B1 X-TX3N-PR LAN_2.5V
27 TRD1- 3 17 X-TX3N-PR 32
A3 7B1 U36
TRD2+ 7 5 100MBPS# 1 24 MCT1
27 TRD2+ TRD2- A4 0LED1_O ACT# 100MBPS# 32 TX0P_SYS TCT1 MCT1 X-TX0P
27 TRD2- 8 13 ACT# 32 2 23
A5 LED Output (SEL = 0) 1LED1_O LINK_1000-LINK_UP_LED#_PR TX0N_SYS TD1+ MX1+ X-TX0N
33 T90 3 22
TRD3+ 2LED1_O TD1- MX1-
27 TRD3+ 9
TRD3- A6 TX0P_SYS MCT2
27 TRD3- 10 29 4 21
A7 0B2 TX0N_SYS TX1P_SYS TCT2 MCT2 X-TX1P
28 5 20
LINK_100_LED# 1B2 TX1N_SYS TD2+ MX2+ X-TX1N
27 LINK_100_LED# 4 6 19
LINK/ACT-ACT_LED# LED0_I TX1P_SYS TD2- MX2-
27 LINK/ACT-ACT_LED# 12 24
LINK_1000-LINK_UP_LED# LED1_I LED Input 2B2 TX1N_SYS MCT3
27 LINK_1000-LINK_UP_LED# 34 23 7 18
LED2_I 3B2 TX2P_SYS TCT3 MCT3 X-TX2P
8 17
TX2P_SYS TX2N_SYS TD3+ MX3+ X-TX2N
20 9 16
DOCKIN# 4B2 TX2N_SYS TD3- MX3-
16,25,32 DOCKIN# 27 19
SEL 5B2 MCT4
10 15
TX3P_SYS TX3P_SYS TCT4 MCT4 X-TX3P
SEL CONNECTION 6B2
16 11
TD4+ MX4+
14
0 Ax to xB1 ; LEDx to xLED1 15 TX3N_SYS TX3N_SYS 12 13 X-TX3N
7B2 TD4- MX4-
11
GND LINK_100_LED#_SYS GST5009 LF
1 Ax to xB2 ; LEDx to xLED2 0LED2_O
6
C
LED Output(SEL = 1) 14 LINK/ACT-ACT_LED#_SYS R515 R512 R42 R39 C
1LED2_O LINK_1000-LINK_UP_LED#_SYS
32
2LED2_O
MAX4892 75/F_4 75/F_4 75/F_4 75/F_4
LED0 Input
0LED1 Output. Connects LED0 to 0LED1 when SEL = 0.
0LED2 Output. Connects LED0 to 0LED2 when SEL = 1. B1B:Change MAX4892 pin define
P/N C68
1000 GST5009 LF DBKN1NLAN03 1500P-2KV_1808
10/100 TST1284A LF DB0MW1LAN09

A1A:Change RJ45 CONN to C100A2-108A4L MGND
A1A:Change RJ45 TX,RX pin define
LANVCC CN25
R503 220_4 11
YELLOW__P
LINK/ACT-ACT_LED#_SYS 12
YELLOW_N
B B
For EMI X-TX3N_CON 1
RX2-
X-TX3P 3 4 X-TX3P_CON X-TX3P_CON 2
X-TX3N X-TX3N_CON RX2+
1 2
RP50 0_4P2R_S X-TX1N_CON 3
RX1-
X-TX1N 3 4 X-TX1N_CON X-TX2N_CON 4 13
X-TX1P X-TX1P_CON TX2- GND1
1 2 swap
RP49 0_4P2R_S X-TX2P_CON 5 14 C66 .1U-10V_4
X-TX2P TX2+ GND2
3 4 X-TX2P_CON
X-TX2N 1 2 X-TX2N_CON X-TX1P_CON 6 C691 .01U-16V_4
RP48 0_4P2R_S RX1+
X-TX0N_CON 7 C57 1500P-2KV_1808
TX1-
X-TX0P 3 4 X-TX0P_CON X-TX0P_CON 8
X-TX0N TX1+
1 2 X-TX0N_CON
RP47 0_4P2R_S LANVCC
R513 220_4 9 MGND

GREEN_P
LINK_100_LED#_SYS 1 2 10
GREEN_N
D5 BAS316
A C100A2-108A4L_RJ45 A
LINK_1000-LINK_UP_LED#_SYS 1 2
D4 BAS316
LED1 A1(+) A2(-) ACT (Tx/Rx) YELLOW BLINKING PROJECT : ZC1
A1A:Add diode for 10/100M LED2 B1(+) B2(-) LINK 10/100/1000 GREEN
& 1000M led control Quanta Computer Inc.
TRANSFORMER/RJ45 A

5 4 3 2 1
1 2 3 4 5 6 7 8
Debug card interface BLUETOOTH MODULE CONNECTOR

BOT contact
CN37 AD[15:0] 15,30 +3VSUS Q43 A1A:Change BT CONN to 5 pin
AD0 AO3403
1 AD1 L72
2 AD2 BT_POWER
1 3
3 AD3
4 AD4 BK2125HS330_8 C904 10U-10V_8
5 AD5 C903 1000P-50V_4
2
6 AD6
7 AD7 CN38
8 BT_POWERON# 39
AD8 BT_POWER
9 AD9 5
A
10 AD11 R710 0_4 BUSBP4+ 4 A
11 15 USBP6+ 3
AD13 R712 0_4 BUSBP4-
12 15 USBP6- 2
AD15 BT_LED
13 40 BT_LED 1
CBE0#
14 CBE0# 15,30
CBE1# BT CONN(EIC 3703-05)
15 CBE1# 15,30
CBE2#
16 CBE2# 15,30
CBE3#
17 CBE3# 15,30
PCIK_MINI
18 PCLK_MINI 2
IRDY# C948 C932 C640
19 IRDY# 15,30
TRDY#
20 TRDY# 15,30
PCIRST# *22P_4 *22P_4 *.01U-16V_4
21 PCIRST# 15,30
GNT2#
22 GNT2# 15
DEVSEL#
23 DEVSEL# 15,30
FRAME#
24 FRAME# 15,30
+3V +3V B1B:Change CN38 p/n to DFHD05MS061
25 +3V
26 +5V +5V D2B:Change CN38 pin define(1~5) to
27 +5V
28 meet vertical connector
GND
29 GND
30
AFN300-N2G1Z_DEBUG A1A:In adapter mode, should be powered during S0~S5.

In battery only mode, should be powered during S0 and S3, and not powered during S5
80mil
+5V_S5 80mil
MB USB PORT(REAR)
U8 A1A:Change footprint to 88231-10001-L
1 8 USBPWR3 D2B:Change CN5 pin 4 to +5V_S5 USBPWR3
GND OUT
2 7
IN OUT
3 6
IN OUT C122 CN5
C121 USBON# R98 0_4 4 5 .1U-10V_4
.1U-10V_4 EN# OUTNC 1
B 2 B
MAX1930ESA-C71091
RP8 0_4P2R_S +5V_S5 3
+3.3V:1000mA
R543 4
3.3Vaux:330mA 15 USBP3- 3 4 USBP3-_CON
*0_4 1 2 USBP3+_CON 5
+1.5V:500mA 15 USBP3+ 6
15 USBP2- 3 4 USBP2-_CON
7
15 USBP2+ 1 2 USBP2+_CON
8
A1A:Change mini card 9
+3V_S5 +3VSUS +3.3Vaux to +3VSUS RP7 0_4P2R_S
10
+3V R47 R44 88231-10001_USB/B
+1.5V *0_6 0_6 1.1 A min

+5V_S5 U42
MiniCard/WLAN
CN24 2 8 USBPWR1
+3.3VAUX_MINI2
IN1 OUT3
51 52 3 7
Reserved +3.3V B1B:Mini card WLAN LED low active(LED5) IN2 OUT2
49 50 6
Reserved GND R559 0_4 OUT1
47 48 39 USBON#
4
Reserved +1.5V EN#
45 46 1
Reserved LED_WPAN# R43 0_4 GND R555 *6.34K/F_4
43 44 WIRELESS_LED 40 9 5
Reserved LED_WLAN# GND-C OC#
41 42 T8
Reserved LED_WWAN# TPS2061DGNR
39 40
D2B:Add C974,C975 for PCIE RX Reserved GND T93
37 38
Reserved USB_D+ T91 +5V_S5 U45
35 36
GND USB_D- +5V_S5 +5V_S5 USBPWR2
15 PCIE_TXP3 33 34 2 8
PETp0 GND IN1 OUT3
15 PCIE_TXN3 31 32 PDAT_SMB 2,16,27,32,33,35 3 7
PETn0 SMB_DATA IN2 OUT2
29 30 PCLK_SMB 2,16,27,32,33,35 6
GND SMB_CLK OUT1
27 28 4
GND +1.5V C791 C782 EN#
15 PCIE_RXP3 25 26 1
PERp0 GND R564 GND R560 *6.34K/F_4
15 PCIE_RXN3 23 24 .1U-10V_4 .1U-10V_4 9 5
PERn0 +3.3Vaux *0_4 GND-C OC#
21 22 PLTRST# 15,16,18,27,32,33,38,39
+3VSUS GND PERST# TPS2061DGNR
19 20 RF_EN 39
Reserved Reserved R41 0_4
17 18
C
Reserved GND C
15 16
GND Reserved
2 CLK_PCIE_MINI 13 14
REFCLK+ Reserved USBPWR1
2 CLK_PCIE_MINI# 11 12
REFCLK- Reserved
2
9 10
R480 7 GND Reserved 8
4.7K_4 5
CLKREQ# Reserved
6
MB USB PORT(RIGHT) C364 + C380 A1A:Change p/n to DFHS04FR342
Reserved +1.5V
3 4
Reserved GND 100U-6.3V_3528 1000P-50V_4
16,27,39 PCIE_WAKE# 3 1 1 2
WAKE# +3.3V
Q29 DTC144EUA AS0B226-S80N-7F_MINI CARD(H=8.0) CN8
Pull up to +3V_S5 on ICH7
CLKREQ# and WAKE# are R236 0_6 BUSBP0- 1 5
15 USBP0- 2 6
open drain signal R234 0_6 BUSBP0+
15 USBP0+ 3 7
C412 C392 4 8
*22P_4
U13 *22P_4 020133MB004S557ZL_USB
CM1293-04SO
1 6 USBPWR2
CH1 CH4
2 5 +5V_S5
VN VP C474 + C479
3 4
CH2 CH3 100U-6.3V_3528 1000P-50V_4
CN9
R281 0_6 BUSBP1- 1 5

15 USBP1- 2 6
R279 0_6 BUSBP1+
15 USBP1+ 3 7
C482 C488 4 8
*22P_4 *22P_4 020133MB004S557ZL_USB

D
D2B:Change CN8,CN9 footprint to D
USB-020133MB004S557ZL-4P-L-H
D2B:Change CN8,CN9 to DFHS04FRD15
om
l.c
ai
tm
PROJECT : ZC1
ho
f@
in
xa
DEBUG CARD&PCI-E card&USB 1A
he
1 2 3 4 5 6 7 8
8 7 6 5 4 3 2 1
+3V Place near U183 K4,P9,E7 ...

+3V
A1A:Connect A_VPP to A_VCC since the Oz711MP1
R613 22K_4 MC_PWR_CTRL_0# do not control the VPP of OZ2211
C833 C860 C850 C858 C861 R615 22K_4
A_VCC A_VPP
10U-10V_8 .1U-10V_4 .1U-10V_4 .1U-10V_4 .1U-10V_4 O2MICRO OZ2211 16PIN SINGLE SLOT PARALLEL
+3V POWER SWITCH(THIS IMPLEMENTATION DOES NOT A1A:Change cardbus headr to 130601-5(H=0)
SUPPORT 12V VPP. TOP MOUNT
CN12
A_VCC
+5V +3V
D U59 1 17 A_VCC D
A_CAD0 GND1 SKTA/VCC1
3 13 2 51
G15
R16
K19
P12
F13
F11
T16
T15
+3.3VIN VCC SKTAAD0/D3 SKTA/VCC2
L14
J15
G6
N5
A_CAD1
E9
K4
P9
E7
L5
4 12 3
J6
U51A A_VCC +3.3VIN VCC A_CAD3 SKTAAD1/D4 A_VPP
11 4 18
VCC A_CAD5 SKTAD3/D5 SKTA/VPP1
5 5 52
GND
GND
GND
GND
GND
GND
PCI_VCC
PCI_VCC
CORE_VCC
CORE_VCC
CORE_VCC
CORE_VCC
CORE_VCC
CORE_VCC
CORE_VCC
VCCD0#/SDATA
VPPD0/SLATCH
VCCD1#/SCLK
AD31 +5VIN A_CAD7 SKTAD5/D6 SKTA/VPP2
F5 D10 6 10 T172 6
AD30 AD31 SKT_VCC +5VIN VPP +3V A_CC/BE0# SKTAAD7/D7
F4 7
AD29 AD30 A_CAD31 A_CAD9 -SKTACBE0/CE1#
G7 E5 9 8 8
AD28 AD29 CAD31 A_CAD30 +12VIN OC# A_CAD11 SKTAAD9/A10
G5 F6 16 9
AD27 AD28 CAD30 A_CAD29 SHDN# A_CAD12 SKTABAD11/OE#
G4 E6 10 69
AD26 AD27 CAD29 A_CAD28 A_CAD14 SKTAAD12/A11 GND5
H7 D6 1 11 70
AD25 AD26 CAD28 A_CAD27 VCC5#(DO) A_CC/BE1# SKTAAD14/A9 GND6
H6 F7 2 12 71
AD24 AD25 CAD27 A_CAD26 VCC3#(D1) A_CPAR -SKTACBE1/A8 GND7
H5 D9 15 13 72
AD23 AD24 CAD26 A_CAD25 VPP_PGM(D0) A_CPERR# SKTAPAR/A13 GND8
J5 G10 14 14
AD22 AD23 CAD25 A_CAD24 VPP_VCC(D1) A_CGNT# -SKTAPERR/A14
J4 F10 15
AD21 AD22 CAD24 A_CAD23 A_CINT# -SKTAGNT/WE#
K5 D11 7 16
AD20 AD21 CAD23 A_CAD22 GND -SKTAINT/RDY
K6 G11
AD19 AD20 CAD22 A_CAD21
L6
AD19 CAD21
D12 OZ2211SN UPPER PIN
AD18 L7 F12 A_CAD20 A_CCLK1 19
AD17 AD18 CAD20 A_CAD19 A_CIRDY# SKTAPCLK/A16
M4 D13 20
AD16 AD17 CAD19 A_CAD18 A_CC/BE2# -SKTAIRDY/A15
M5 E13 21
AD15 AD16 CAD18 A_CAD17 A_CAD18 -SKTACBE2/A12
Reserve for EMI T5
AD15 CAD17
G13 Place near U182(power switch) 22
SKTAAD18/A7
AD14 R6 H15 A_CAD16 A_CAD20 23
PCI_CLK_711 AD13 AD14 CAD16 A_CAD15 A_VCC A_CAD21 SKTAAD20/A6
T6 J13 24
AD12 AD13 CAD15 A_CAD14 A_CAD22 SKTAAD21/A5
N7 H16 25
R7 J16 26
R628 AD10 AD11 CAD13 A_CAD12 A_CAD24 SKTAAD23/A3
N8 J14 27
*68_4 P8 K13 28
AD8 AD9 CAD11 A_CAD10 C926 C934 C929 A_CAD26 SKTAAD25/A1
R8 K14 29
N9 K15 30
AD6 AD7 CAD9 A_CAD8 4.7U-10V_8 .1U-10V_4 .1U-10V_4 A_CAD29 SKTAAD27/D0
R9 L15 31
AD6 CAD8 SKTAAD29/D1
1
C C839 AD5 T9 L13 A_CAD7 A_CRSVD/D2 32 C

AD4 AD5 CAD7 A_CAD6 A_CCLKRUN# SKTARSVD/D2
R10 M14 33
*10P_4 AD3 AD4 CAD6 A_CAD5 -SKTACLKRUN/WP
T10 M15 34
2
AD2 AD3 CAD5 A_CAD4 GND2

P10 N16
AD1 AD2 CAD4 A_CAD3 A_VPP +5V
N10 M13 35
AD0 AD1 CAD3 A_CAD2 A_CCD1# GND3
T11 N13 36
AD0 CAD2 A_CAD1 A_CAD2 -SKTACD1/CD1#
15,29 AD[0..31] N15 37
CAD1 A_CAD0 A_CAD4 SKTAAD2/D11
15,29 CBE3# H4 P16 38
C/BE3# CAD0 A_CAD6 SKTAD4/D12
15,29 CBE2# M6 39
C/BE2# C918 C913 C917 C925 A_RSVD/D14 SKTAAD6/D13
15,29 CBE1# T4 40
C/BE1# A_CCLK R650 33_4 A_CCLK1 A_CAD8 SKTARSVD/D14
15,29 CBE0# T8 E15 41
C/BE0# CCLK A_CFRAME# 4.7U-10V_8 .1U-10V_4 .1U-10V_4 4.7U-10V_8 A_CAD10 SKTAAD8/D15
E14 42
AD25 R634 100_4 CFRAME# A_CIRDY# A_CVS1# SKTAAD10/CE2#
J7 D15 43
IDSEL CIRDY# A_CTRDY# A_CAD13 -SKTAVS1/VS1#
2 PCI_CLK_711 L4 D16 44
PCI_CLK CTRDY# A_CDEVSEL# A_CAD15 SKTAAD13/IORD#
15,29 DEVSEL# P4 E16 45
DEVSEL# CDEVSEL# A_CSTOP# A_CAD16 SKTAAD15/IOWR#
15,29 FRAME# M7 F15 46
FRAME# CSTOP# A_CPAR +3V A_CRSVD/A18 SKTAAD16/A17
15,29 IRDY# N4 G16 47
IRDY# CPAR A_CPERR# A_CBLOCK# -SKTRSVD/A18
15,29 TRDY# N6 F16 48
TRDY# CPERR# A_CSERR# A_CSTOP# -SKTALOCK/A19
15 STOP# P5 D8 49
STOP# CSERR# A_CREQ# A_CDEVSEL# -SKTASTOP/A20
15 PAR R5 E11 50
PAR CREQ# A_CGNT# -SKTADEVSEL/A21
15 PERR# P6 F14
PERR# CGNT# A_CINT# C928 C931
15 SERR# R4
SERR# CINT#
G9 LOWER PIN
15 REQ0# D4 G14 A_CBLOCK# A_CTRDY# 53
REQ# CBLOCK# A_CCLKRUN# .1U-10V_4 4.7U-10V_8 A_CFRAME# -SKTATRDY/A22
15 GNT0# E4 G8 54
GNT# CCLKRUN# A_CRST# A_CAD17 -SKTAFRAME/A23
15,29 PCIRST# K7 E12 55
R624 *0_4 PCI_RST# CRST# A_CRSVD/D2 A_CAD19 SKTAAD17/A24
16 RI# D5 56
711_PME# R626 0_4 R2_D2 A_RSVD/D14 A_CVS2# SKTAAD19/A25
P11 M16 57
RI_OUT#/PME# R2_D14 A_CRSVD/A18 A_CRST# -SKTAVS2VS2#
H13 58
R2_A18 -SKTARST/RESET
XD_CLE/SD/MS_CLK/VPPD1
36 PCMSPK R12 F9 A_CVS1# A_CSERR# 59

SPKR_OUT# CVS1 A_CVS2# A_CREQ# 0SKTASERR/WAIT#
XD_ALE/SD_CMD/MS_BS
T164 H8 G12 60
SKTA_ACTV CVS2 A_CCD1# A_CC/BE3# -SKTAREQ/INPACK#
T161 P14 P15 61
B ODR_ACTV CCD1# A_CCD2# A_CAUDIO -SKTACBE3/REG# B
D7 62
XD_RE#/SD/MS_3V#
CCD2# A_CAUDIO A_CSTSCHG SKTAAUDIO/BVD2

16,38,39 CLKRUN# R14 E8 63
SC_VCC/XD_VCC
XD_WPO/SC_5V#
XD_R/B#/SC_CLK
MF6(CLKRUN#) CAUDIO -SKTASTSCHG/BVD1

XD_WE#/SC_3V#
A_CSTSCHG A_CAD28
XD_WPI/SD_WP
P13 F8 64
XD_D4/SC_FCB
XD_D6/SC_RST
T174 MF4(MS_CD#) CSTSCHG SKTAAD28/D8

A_CAD30
XD_D7/SC_C8
XD/SD/MS_D0
XD/SD/MS_D1
XD/SD/MS_D2
XD/SD/MS_D3
T13 65
XD_D5/SC_IO
16,38,39 SERIRQ MF3(SIRQ#) SKTAAD30/D9

A_CC/BE3# A_CAD31
XD/SC_CD#
15 INTE# N11 E10 66

MF0(INTA#) CC/BE3# A_CC/BE2# A_CCD2# SKTAAD31/D10
D14 67
SD_CD#
CC/BE2# A_CC/BE1# -SKTACD2/CD2#

H14 68
CC/BE1# A_CC/BE0# GND4
L16
CC/BE0#
OZ711MP1BN C1C:Change Smart card schematic CARDBUS SLOT

U5
T7
U11
U7
U9
N12
T14
R15
C5
T12
R11
N14
K16
C7
C15
C9
C13
C11
SANTA-130601-5-68P
+3V +3V 15V +5V
SMARTCARD_711MP1 R751
+3V B1B:Add U63 for Cardbus detect
2
+3V +3V T175 33_4 D2B:Remove U63 for Cardbus detect
T176 T177 T179 T180 T182 R749 200_4 SC_C8 R750
5
T178 T181 T183 R753 R754 R755 U63
R756 200_4 SC_RST A_CCD1#
100K_4 2
R633 4 CARDBUS_DET 39
1
R752 200_4
2
10K_4 SC_IO 10K_4 10K_4 2 Q54 A_CCD2# 1

10K_4
IRLML2502 CN10
R757
3
711_PME# PCI_PME# 200_4 SC_C4 SC_C4 *TC7SH08FU

1 3 1
3
PCI_PME# 15 SC_CLK C4
2
R758 33_4 SC_CLK SC_RST C3
3
1
SC_5V# SMARTCARD_VDD C2
Q36 2N7002 1 2 2 4
SC_DET# C1
5
SMARTCARD_VDD D38 Q55 SW-CD
A 6 A
1SS355 NC
7
2N7002 SW-GND
2 D2B:Add D35,C965,C966 for smart card VCC 8
1
D35 SC_3V# C5
1 2 9
+3V SMARTCARD_711MP1 SC_DET# SC_IO C6
3 10
CH715F D39 SC_C8 C7
11
1SS355 C8
1 12
+5V NC PROJECT : ZC1
C965 C966 85201-12021_SCR_CONN
R759 47K_4 SC_IO R/A Top Contact
4.7U/10V_0805 .1U/10V_0402 D2B:Change R759 From CS34703J901 to CS34702JB21 Quanta Computer Inc.
+3V C2A:Ad R774 for SC_DET# Size Document Number Rev
1A
R774 10K_4 SC_DET#
OZ711MP1-PCMCIA-SMART CARD
8 7 6 5 4 3 2 1
5 4 3 2 1
+3V
A1A:1394 function of OZ711MP1 do not used the EEPROM , and Oz711MP1

put the GUID in PCI register , So , 24Lc02BT can be remove
+3V SD_PWR
C864 C830
TPBIAS0
10U-10V_8
C826 SD_WP R1 10K_4
.1U-10V_4
1U-16V_6 SD_CMD R237 *10K_4
M1
H1
K1
F1
U51B U1
R606 R607 R763 0_6 CARD_USBP4+ 88 99 R347 2.2K_4 5pF attached to SD_D0 and GND
AVCC
AVCC
CORE_VCC
CORE_VCC
15 USBP4+ USBDP ATEST
for 48M compatibility issue
56.2/F_4 56.2/F_4 R762 0_6 CARD_USBP4- 87 98 R346 12K_4
15 USBP4- USBDM RBIAS SD_D0
USB
D D
Secure Digital R240 C944
W13 TPA0P R445 0_4 L1394_TPA0+ SD_CMD 30 26 SD_D0
TPA0+ TPA0N R444 0_4 L1394_TPA0- SD_CMD SD_DAT0 SD_D1 *10K_4 5P-50V_4
W12 27
TPA0- SM_PWR
SD_WP SD_DAT1 SD_D2
W11 25 28
TPB0+ SD_WP SD_DAT2 SD_D3
M19 W10 29
CPS TPB0- TPB0P R442 0_4 L1394_TPB0+ SD_DAT3
R623 5.9K_4 W9 TPB0N R443 0_4 L1394_TPB0- 31 SD_CLK R254 33_4 SD_CLKR
TPA1+ SD_CLK
N19 W8 R370 SM_PWR
RI1 TPA1- Smart Media C1
W7 R345
TPB1+ R610 R611 SM_CD 78 SM_D0
W6 65
TPB1- SM_CD SM_D0 SM_D1 10P_4
10K_4 66
1394_XIN TPBIAS0 56.2/F_4 56.2/F_4 SM_WPS 76 SM_D1 SM_D2
J19 W14 A1A:Change the C1885 filter Cap 10K_4 67
1394_XOUT H19 XI TPBIAS0 CN16 SM_WPS SM_D2 SM_D3
Y7 N1 value from 270 pf to 820 pf 68 R142 R233 R235
XO TPBIAS1 SM_BR
SM_D3 SM_D4
5 77 69
1394_XOUT 1394_XIN L1394_TPB0- SM_B/R SM_D4 SM_D5
1 2 1 70
C828 L1394_TPA0- SM_D5 SM_D6
3 6 71 *10K_4 *10K_4 *2.2K_4
R625 C838 L1394_TPA0+ SM_D6 SM_D7
4 72
C852 C844 1U-16V_6 L1394_TPB0+ SM_D7
2 7
12P-50V_4 24.576MHZ 12P-50V_4 5.1K/F_4 820P_6 8 73 SM_ALE
SM_ALE SM_CLE
G1 75
TEST_PHY SM_CLE SM_RE
81
020204FR004S502ZL_1394 CONN SM_RE SM_WE
82
SM_WE SM_WP_IN
A1A:Change1394 footprint to 74
SM_WP SM_CE
1394-020204fr004s502zx-c-4p-v 83
SM_CE
B1B:Change pin 7,8 to GND Compact Flash
J1 B1B:Change 1394 p/n to DFHS04FS578 53 32 R353 R239 R238
NC CF_CD1 CF_D0
R13 L1 E3A:Change 1394 footprint to 1394-020204fr004s109zl-4p-v8 54 33
NC VR_CPR CF_CD2 CF_D1
U13 L19 34
NC VR_CPR CF_D2
U15 55 35 *10K_4 *10K_4 *2.2K_4
NC CF_IRQ CF_D3
CF_D4
36 External xD
C835 56 37
22U-6.3V_8 CF_IORDY CF_D5
CF_D6
38 resistors
39
GND
GND
GND
GND
GND
CF_D7
40
CF_D8
41
OZ711MP1BN CF_D9
Group 1 and 2 not populated: 45
P1
P7
P19
F19
G19
CF_D10
C
Firmware in Internal ROM 46 C
CF_D11
No unique serial number 48
CF_D12
50
CF_D13
51
CF_D14
52
CF_D15
Group 2 populated: 62
CF_SA0
Firmware in External FLASH 63
CF_SA1
Unique serial number and configuration in FLASH 64
CF_SA2
60
+3V SD_PWR CF_CS0
61
CN14 SM_PWR External FLASH CF_CS1
P10 U49 57
SD_D0 SD-VCC R359 2.2K_4 MA0 MD0 CF_IOR
P3 18 12 13 58
R356 SD_D1 SD-DAT0 XD-VCC MA1 A0 DQ0 MD1 CF_IOW
P2 11 14 59
SD-DAT1 A1 DQ1 CF_RESET
SD/MMC SD_D2 P20
SD-DAT2 XD-CD
1 SM_CD Check GPIO Pin & Det MA2 10
A2 DQ2
15 MD2
SD_D3 P18 2 SM_BR MA3 9 17 MD3 Memory Stick
100K_4 SD_CLKR SD-DAT3 XD-R/B SM_RE MA4 A3 DQ3 MD4 MS_INS MS_D0
P7 3 8 18 18 19
SD_CMD SD-CLK XD-RE SM_CE MA5 A4 DQ4 MD5 MS_INS MS_D0 MS_D1
P15 4 7 19 20
SD_DET R354 10K_4 SD_CD# SD-CMD XD-CE SM_CLE MA6 A5 DQ5 MD6 C945 MS_D1 MS_D2
P21 5 6 20 21
SD_WP SD-CD XD-CLE SM_ALE MA7 A6 DQ6 MD7 MS_D2 MS_D3
P1 6 5 21 22
SD-WP XD-ALE SM_WE MA8 A7 DQ7 .1U-10V_4 MS_D3
D2B:Connect CN14 pin 4,12,22,23 to GND P22 7 27
SD-WP/SDIO GND XD-WE SM_WP_IN MA9 A8 MS_CLK
P23 8 26 23
SD-CD/SDIO GND XD-WP-IN MA10 A9 MS_SCLK MS_BS
P4 9 SM/xD 23 24
MS_PWR SD-GND XD-GND SM_D0 MA11 A10 MS_BS
P12 10 25
SD-GND XD-D0 SM_D1 SM_PWR MA12 A11 Memory Interface
11 4 +3V
XD-D1 SM_D2 MA13 A12 MD0 MA0
P17 12 28 5 116
MS_D0 MS-VCC XD-D2 SM_D3 MA14 A13 MD1 MD0 MA0 MA1
P9 13 29 32 6 117
MS_D1 MS-DATA0 XD-D3 SM_D4 MA15 A14 VCC MD2 MD1 MA1 MA2
MS/MS pro P8 14 3 7 118
MS_D2 MS-DATA1 XD-D4 SM_D5 R767 ROMEN A15 MD3 MD2 MA2 MA3
P11 15 2 8 119
MS_D3
MS-DATA2 XD-D5 SM_D6 100K_4 A16 MD4
MD3 MA3 MA4
P14 16 C867 9 120
MS_CLK R358 33_4 MS_CLKR MS-DATA3 XD-D6 SM_D7 MD5 MD4 MA4 MA5
P16 17 10 121
MS_INS MS-SCLK XD-D7 *.1U-10V_4 MD6 MD5 MA5 MA6
P13 11 122
GND_PAD
MS-INS R361 MD6 MA6

MS_BS P6 19 R369 10K_4 EE_DIO MC0 24 MD7 12 123 MA7
C580 MS-BS XD-GND MC1 OE MD7 MA7 MA8
P19 31 124
MS-GND *10K_4 MC2 WE MA8 MA9
P5 22 16 125
10P_4 MS-GND CE GND MA9 MA10
126
B
R013-000-XX_CARD READER MA10 MA11
B
127
P24
*SST39VF010-70-4C-WHE MA11 MA12

128
+3V 6 IN1 CARD READER MA12 MA13
1
MA13 MA14
(MS,MS pro,SD, MMC,xD,SDIO) +3V 2
MA14 MA15
C2B:Remove U49,C867,R361 4
MA15
Group 1 populated: 13 MC0
MRD MC1
Firmware in Internal ROM R141 14
R765 R766 MWR MC2
Unique serial number and configuration in EEPROM 17
MCE
100K_4 100K_4 100K_4 Miscellaneous
115 114
20 mil 20 mil 20 mil External EEPROM RESET GPIO1
GPIO2
113 EE_CS Check USB2.0 Power
+3V SD_PWR SM_PWR MS_PWR R368 1K_4 96 94 VBUS_DET R335 100K_4
C529 TEST0 GPIO3 +5V
MS_INS 95 111 EE_DIO
SM_CD U16 TEST1 GPIO4 SD_DET
.1U-10V_4 110
GPIO5 ROMEN C961 R764
109
C849 C962 C641 C963 C573 C576 C964 C845 EE_DIO GPIO6/ROMEN EE_CLK
3 4 107 100K_4
DI DO GPIO7
10U-10V_8
+3V 42 MS_PWR 1U-16V_6

18P-50V_4 GPIO8
10U-10V_8
10U-10V_8
10U-6.3V_8 1M_4 .1U-10V_4 .1U-10V_4 1M_4 EE_CLK 2 C553 CARD_XTAL1 102 105
CLK XTAL1 GPIO9 SM_PWR
8 79
VCC C853 GPIO10 SD_PWR
6 44
ORG GPIO11
93
GPIO12
1
EE_CS 1 5 .1U-10V_4 R344 92
CS GND Y1 GPIO13
D2B:Change C641 to 1M_4(CS51002JB21) D2B:Change C845 to 1M_4(CS51002JB21) 91
AT93C66A-10TU-2.7(TSSOP) 24MHz(+-30PPM) 1M_4 GPIO14
90 Place C567 at pin 100, C542 at
2
GPIO15 +3V
H=1.5 pin 108, and C524 at pin 89.
3
C552 18P-50V_4 CARD_XTAL2 VDDIO33 C471 C548 C558
103 43
XTAL2 VDDIO33
80
VDDIO33 .1U-10V_4 .1U-10V_4 10U-6.3V_8
C2B:Stuff U16,R368 15
VSS
16 100
VSS VDDCORE33 +3V
E3A:Change U16 to AR0ZC1C1009 47 108
VSS VDDCORE33
84 89
VSS VDDA33
85
VSS CARD_VDD18 C524 C567
97 49 C556 C542
VSS VDD18
A 112 106 A
VSS VDD18 .1U-10V_4 10U-6.3V_8
86 .1U-10V_4 .1U-10V_4
VSSA
104 101
VSSPLL VDD18PLL C946
USB2228-NU-XX_VTQFP128 4.7U-10V_8
om
C569
4.7U-10V_8
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PROJECT : ZC1
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OZ711MP1-IEEE1394-SMART CARD 1A
he
Date: Wednesday, November 30, 2005 Sheet 31 of 46
5 4 3 2 1
5 4 3 2 1
CN21-4 CN21-3 L9 BK1608LL121_6 CN21-2 CN21-1

CRTHSYNC PR_CRTHSYNC 78
26 HSYNC_EZ4 CRT_HS
8 100 CRTVSYNC PR_CRTVSYNC 79 64 R460 0_4
28 100MBPS# LANLED_LINK GND100 26 VSYNC_EZ4 CRT_VS DVI_HPD TMDS_HPD 19,25
R455 0_4 31 101 TV_COMP_PR DDCCLK_1 L8 BK1608LL121_6 81 98
28 ACT# LANLED_ACT TV_COMPS TV_COMP_PR 25 26 DDCCLK_1 CRT_DDCK DVI_CLK- DVI_CLK- 25
33 102 TV_Y/G_PR DDCDAT_1 80 97
GND33 TV_LUMA TV_Y/G_PR 25 26 DDCDAT_1 CRT_DDCDT DVI_CLK+ DVI_CLK+ 25
103 TV_C/R_PR 105 99
TV_CRMA TV_C/R_PR 25 GND105 GND99
SUSON_PR 55 104 BK1608LL121_6 L12 PR_RED 106 94 R14
SUSON GND104 26 VGA_RED_PR VGA_R DVI_D0- DVI_TX0- 25
MAINON_PR 56 BK1608LL121_6 L11 PR_GRN 107 95 100K_4
MAINON 26 VGA_GRN_PR VGA_G DVI_D0+ DVI_TX0+ 25
DOCKPRG 85 9 STRB# BK1608LL121_6 L10 PR_BLU 108 96
BRG_PWROK STRB# STRB# 38 26 VGA_BLU_PR VGA_B GND96
11 PD0 109 91
PD0 GND109 DVI_D1- DVI_TX1- 25
KPCLK 52 13 PD1 117 92
39 KPCLK PS2KBCK PD1 GND117 DVI_D1+ DVI_TX1+ 25
KPDATA 51 15 PD2 119 93
39 KPDATA PS2KBDT PD2 2 CLK_PCIE_EZ1 PCIE1_CLK+ GND93
MSCLK 54 17 PD3 120 61
39 MSCLK PS2MSCK PD3 2 CLK_PCIE_EZ1# PCIE1_CLK- DVI_D2- DVI_TX2- 25
D MSDATA 53 18 PD4 118 62 D
39 MSDATA PS2MSDT PD4 PD[0..7] 38 GND118 DVI_D2+ DVI_TX2+ 25
19 PD5 115 63
MDSR1# PD5 PD6 15 PCIE_TXP4 PCIE1_TP GND63
38 MDSR1# 48 20 116
MRTS1# DSR# PD6 PD7 15 PCIE_TXN4 PCIE1_TN 0_4 R461 DVI_DDCCLK
38 MRTS1# 46 21 114 67
MCTS1# RTS# PD7 PE GND114 DVI_DDCCK 0_4 R459 DVI_DDCDATA
38 MCTS1# 44 24 PE 38 15 PCIE_RXP4 111 65
MRI1 CTS# PE AFD# PCIE1_RP DVI_DDCDT
38 MRI1 42 10 AFD# 38 15 PCIE_RXN4 112 66
MDCD1# RI AFD# ERROR# PCIE1_RN GND66
38 MDCD1# 49
DCD# ERROR#
12 ERROR# 38
A1A:Change EZ1 from PCIE1 to PCIE4 113
GND113
MRXD1 47 14 INIT# 29 37 X-TX3P-PR
38 MRXD1 RXD# INIT# INIT# 38 2 CLK_PCIE_EZ2 PCIE2_CLK+ TX3P X-TX3P-PR 28
MTXD1 45 16 SLIN# 30 38 X-TX3N-PR
38 MTXD1 TXD# SLIN# SLIN# 38 2 CLK_PCIE_EZ2# PCIE2_CLK- TX3N X-TX3N-PR 28
MDTR1# 43 22 ACK# A1A:Change EZ2 from PCIE1 to PCIE5 27 39
38 MDTR1# DTR# ACK# ACK# 38 GND27 GND39
50 23 BUSY 59 34 X-TX2P-PR
GND50 BUSY BUSY 38 15 PCIE_TXP5 PCIE2_TP TX2P X-TX2P-PR 28
25 SLCT 60 35 X-TX2N-PR
SLCT SLCT 38 15 PCIE_TXN5 PCIE2_TN TX2N X-TX2N-PR 28
R15 0_6 41 28 36
36,37 SPDIF_OUT SPDIF_OUT GND28 GND36 X-TX1P-PR
AUDGND1 72 58 15 PCIE_RXP5 89 4 X-TX1P-PR 28
R745 0_4 SPKR_DOCK 74 AGND72 GND58 PCIE2_RP TX1P X-TX1N-PR
37 SPKR_SYS 77 15 PCIE_RXN5 90 5 X-TX1N-PR 28
R744 0_4 SPKL_DOCK 75 LINEOUT_R GND77 PCIE2_RN TX1N
37 SPKL_SYS 110 88 6
R746 0_4 LINEINR_DOCK70 LINEOUT_L GND110 D19 1 GND88 GND6
37 LINEINR_PR 15,16,18,27,29,33,38,39 PLTRST# 2 BAS316 R12 0_4 57 1 X-TX0P-PR
X-TX0P-PR 28
R747 0_4 LINEINL_DOCK71 LINEIN_R PCIERST TX0P X-TX0N-PR
37 LINEINL_PR 32 26 2 X-TX0N-PR 28
R748 0_4 PR_MIC_DOCK73 LINEIN_L RESERVE32 PCIEWAKE TX0N
37 PR_MIC 82 +5V 2,16,27,29,33,35 PDAT_SMB 86 3
MICIN RESERVE82 PCIESMBDT GND3
AUDGND1 76 2,16,27,29,33,35 PCLK_SMB 83 7
AGND76 PCIESMBCK GND7 DOCKIN#
37 PR_MIC_IN 69 2 EZ_CLKREQ# 87 68
PRMIC_DET C18 PCIEREQ# DOCK_IN# R13 1K_4
37 HPSENCE_PR 40 84
HPSENSE_PR DOCKED#
124 123 .1U-10V_4
G2 G1
126 VA 122
GND126 P2
125 121 VA
GND125 P1
EZ4_Acer_define EZ4_Acer_define
+3V +5V EZ4_Acer_define EZ4_Acer_define
C R456 0_4 C
VA
AUDGND1
+3V_S5
+3V_S5 R471 R452
2.2K_4 10K_4 C5 C2
C15 .1U-50V_6 .1U-50V_6
2
R7 Q26
.1U-10V_4
1 3 DVI_DDCDATA
19 TMDS_DDCDATA DVI_DDCDATA 25
5
10K_4 DOCKPRG 1 FDV301N

4 DOCKIN#
PR_STS 39
DOCKIN 2
U2 +3V
3
TC7SH08FU
3
+5V
B: CHANGE TO FDV301N
7
R9
DOCKIN# 1M/F_4
2
SUSON_PR 3 5 SUSON 39,42,43
Q2 R458
2N7002 R11 10K_4
2.2K_4 U4B
1
TC7W125FU
2
Q4
DOCKIN#
B DVI_DDCCLK B
19 TMDS_DDCCLK 1 3 DVI_DDCCLK 25
FDV301N +3V_S5
D2B:Reserve 100pf for KPCLK,KPDATA,MSCLK,MSDATA
PR_CRTHSYNC C661 *10P_4
KPCLK C968 *100P-50V_6 PR_CRTVSYNC C662 *10P_4 C28
KPDATA C969 *100P-50V_6 PR_BLU C660 10P-50V_4 +5V
8
MSCLK C970 *100P-50V_6 PR_GRN C659 10P-50V_4 .1U-10V_4
MSDATA C971 *100P-50V_6 PR_RED C658 10P-50V_4
CRTHSYNC C667 *10P_4
SPKL_SYS C19 220P-50V_4 CRTVSYNC C668 *10P_4 MAINON_PR 6 2
16,25,28 DOCKIN# MAINON 20,39,42,43,44
SPKR_SYS C20 220P-50V_4
LINEINL_PR C23 220P-50V_4 DDCCLK_1 C657 10P-50V_4 +3V_S5
LINEINR_PR C22 220P-50V_4 DDCDAT_1 C656 10P-50V_4 R465 U4A
4
PR_MIC_IN C655 47P-50V_4 X-TX1P-PR C12 10P-50V_4 TC7W125FU
PR_MIC C21 47P-50V_4 X-TX1N-PR C8 10P-50V_4 10K_4
100MBPS# C653 1000P-50V_4 X-TX0P-PR C3 10P-50V_4 A1A:Change footprint to SSOP8-4-65
PR_INSERT_5V 25,26
ACT# C649 1000P-50V_4 X-TX0N-PR C4 10P-50V_4 R475
3
TV_COMP_PR C650 10P-50V_4 X-TX3P-PR C25 10P-50V_4
TV_C/R_PR C652 10P-50V_4 X-TX3N-PR C24 10P-50V_4 100K_4
TV_Y/G_PR C651 10P-50V_4 X-TX2P-PR C6 10P-50V_4
X-TX2N-PR C7 10P-50V_4 DOCKIN# 2
C654 Q27
2N7002
.1U-10V_4
1
A A
PROJECT : ZC1
EZ4 CONN 1A

5 4 3 2 1
5 4 3 2 1
+NEW_1.5V Max. 650mA, Average 500mA. A1A:Change New card to small type(130832-1)
+NEW_3V Max. 1300mA, Average 1000mA. Reverse
CN35
A1A:Change New card power sw to Oz27c10
26
GND1
25
+1.5V +3V +3VSUS +NEW_3VAUX +NEW_3V +NEW_1.5V 15 PCIE_TXP0 PETp0
24
U20 +NEW_3VAUX 15 PCIE_TXN0 PETn0
Place near U20 23
GND2
C869 .1U-10V_4 PERP0 22
15 PCIE_RXP0 PERp0
17 15 C868 .1U-10V_4 PERN0 21
D AUXIN AUXOUT 15 PCIE_RXN0 PERn0 D
2 3 C597 20
3.3VIN_0 3.3VOUT_0 GND3
4 5 2 CLK_PCIE_NEW_C 19
3.3VIN_1 3.3VOUT_1 .1U-10V_4 REFCLK+
12 11 2 CLK_PCIE_NEW_C# 18
1.5VIN_0 1.5VOUT_0 CPPE# REFCLK-
14 13 17
1.5VIN_1 1.5VOUT_1 CPPE#
2 NEW_CLKREQ# 16
R398 100K_4 +NEW_3V CLKREQ#
15
+3VSUS +3.3V1
+3VSUS 2 1 ExpressSwitch 14
+3.3V2
+NEW_3V +NEW_1.5V PERST# 13
PERST# +NEW_3VAUX PERST#
20 8 12
SHDN# PERST# CPPE# +3.3VAUX
16 EXPRCRD_STDBY# 1 R413 2 *0_4 1 10 R386 2 1 100K_4 11
STBY# CPPE# CPUSB# R387 +NEW_1.5V WAKE#
6 9 2 1 100K_4 C611 C600 10
15,16,18,27,29,32,38,39 PLTRST# SYSRST# CPUSB# +1.5V1
19 9
OC# .1U-10V_4 .1U-10V_4 NEW_SMDATA +1.5V2
16 8
NC NEW_SMCLK SMB_DATA
7 18 7
GND RCLKEN SMB_CLK
6
RESERVED1
5
R5538D001-TR-F/OZ27C10LN CPUSB# RESERVED2
4
USBP5-_CARD USBP5+_CARD CPUSB#
15 USBP5- 1 2 3
+NEW_3V USBP5+_CARD USBP5-_CARD USB_D+
15 USBP5+ 3 4 2
USB_D-
1
RP68 0_4P2R_S GND4
Place near U20
+3VSUS +3V +1.5V
130832-1_NEW CARD
4
2
C C
RP44 +NEW_3VAUX Place near CN35
C603 C613 C612 C598 C599
.1U-10V_4 .1U-10V_4 .1U-10V_4 .1U-10V_4 .1U-10V_4 10K_4P2R
C837
3
1
.1U-10V_4
3 1 NEW_SMDATA
2,16,27,29,32,35 PDAT_SMB
Q23 2N7002
+NEW_3V +NEW_1.5V
+NEW_3V
D2B:Remove HOLE6
C857 C843 C847 C829 C834
HOLE22 HOLE21
*H-C79D79N *H-C236D146I226A226P2 4.7U-10V_8 .1U-10V_4 .1U-10V_4 4.7U-10V_8 .1U-10V_4
2
3 1 NEW_SMCLK
2,16,27,29,32,35 PCLK_SMB
1
Q24 2N7002
TPM
B PAD13 PAD14 PAD11 PAD8 PAD16 PAD17 PAD4 PAD18 PAD19 PAD6 PAD3 PAD10 B
HOLE19 HOLE26 HOLE24 HOLE25 HOLE23 HOLE17 HOLE10 *EMIPAD *EMIPAD *EMIPAD *EMIPAD *EMIPAD *EMIPAD *EMIPAD *EMIPAD *EMIPAD *EMIPAD *EMIPAD *EMIPAD
*H-C276D106I186A186P2 *H-C276D106I186A186P2 *H-C276D106I186A186P2 *H-C276D106I186A186P2 *H-C276D106I186A186P2 *H-C276D106I186A186P2 *H-C315D146I226A226P2 CPU
1
1
1
PAD25 PAD21 PAD22 PAD24 PAD23 PAD20 PAD15 PAD12 PAD9 PAD7 PAD2 PAD5
HOLE14 HOLE12 HOLE13 HOLE3 HOLE2 HOLE4 HOLE15 HOLE16
*H-C256D106I186A186P2 *H-C276D106I186A186P2 *H-C79D79N *H-C276D106I186A186P2 *H-C276D106I186A186P2 *H-C276D106I186A186P2 *H-C315D146I226A226P2 *H-C315D146I226A226P2
*EMIPAD *EMIPAD *EMIPAD *EMIPAD *EMIPAD *EMIPAD *EMIPAD *EMIPAD *EMIPAD *EMIPAD *EMIPAD *EMIPAD
1
1
1
ADOGND ADOGND
HOLE18 HOLE20 HOLE8 HOLE27 HOLE5 HOLE7 HOLE9 HOLE11 PAD26 PAD27 PAD28 PAD29 PAD30 PAD31
*H-C236D146I226A226P2 *H-C236D146I226A226P2 *H-C276D169P2 *H-C276D67P2 *H-C236D146I226A226P2 *H-C236D146I226A226P2 *H-C236D67I147A147P2 *H-C236D67I147A147P2
A *EMIPAD *EMIPAD *EMIPAD *EMIPAD *EMIPAD *EMIPAD A
PROJECT : ZC1
1
1
MDC POWER/B MINI CARD Thermal module Quanta Computer Inc.

B1B:Change HOLE8,27 footprint Size Document Number Rev
NEW CARD &HOLE C

5 4 3 2 1
om
l.c
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tm
ho
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5 4 3 2 1
+3V +1.8V
+3V
C825 C848 C592
R617
R618
R619
R620
R621
C593 C824 C566
SATA TO PATA PH@1U-6.3V_4 PH@1U-6.3V_4 PH@1U-6.3V_4 PH@1U-6.3V_4
PH@1U-6.3V_4
PH@1U-6.3V_4
ULI@0_4
ULI@0_4
ULI@0_4
ULI@0_4
ULI@0_4
D D
B_PDCS1#
B_PDCS3#
Close to power pins(pin4,17,44,52) Close to power pins(pin9,41,56)
+3V +1.8V B_PDD0 B_PDD[0..15] 35
Stuff all when use B_PDD1
ULI M5285 B_PDD2
B_PDD3
A1A:Change p/n to AL003811010 +1.8V +3V B_PDD4
B_PDD5
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
U50 B_PDD6
L42 L44 B_PDD7
IDE_CS0_b
IDE_CS1_b
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
VDDO
VDDI
VSS
VSS
ODCS
PH@BLM11A05_6 ULI@BLM11A05_6 B_PDD8
B_PDD9
Unstuff R629 when SATA AC coupling is 0.01UF B_PDD10
use ULI M5285 B_PDD11
RP76 PH@0_4P2R_S B_PDD12
B_PDA2 49 32 SATA_RXP0_R 1 2 SATA_RXP0 14 B_PDD13
B_PDA0 IDE_DA2 TxP SATA_RXN0_R B_PDD14
50
IDE_DA0 TxN
31 3 4 SATA_RXN0 14 145mA
+3V
R629
B_PDA1
PH@0_4
B_IRQ14
51
52
53
IDE_DA1
VDDO
SPIF3811-HV096 GNDA
VDDA
30
29
28
AVDDL_1.8
SATA_TXN0_R
RP78 PH@0_4P2R_S VDDA_3.3_1.8
B_PDD15
B_PDCS1#
1 2 SATA_TXN0 14 B_PDCS1# 35
IDE_INTRQ RxN
B_PDDACK#
B_PIORDY
54
55 64pin QFN
IDE_DMACK_b
IDE_IORDY
RxP
REXT
27
26
SATA_TXP0_R
R627
3
PH@1K/F_4
4 SATA_TXP0 14
B_PDA0
B_PDA2
B_PDCS3#
B_PDA0 35
B_PDA2 35
+1.8V 56 25 B_PDCS3# 35
VDDI GNDA VDDA_3.3_1.8 R366 PH@0_4 B_PDA1
C 57 24 B_PDA1 35 C
B_PDIOR# VSS VDDA XTALO B_IRQ14
58 23 B_IRQ14 35
B_PDIOW# IDE_DIOR_b XTALO XTALI C570 C568 B_PDDACK#
59
IDE_DIOW_b XTALI/CLKI
22 Unstuff R366 when B_PDDACK# 35
B_PDDREQ 60 21 R639 PH@10K_6 B_PIORDY
IDE_DMARQ DD_DISABLE_B +3V use ULI M5285 B_PIORDY 35
B_PDD15 61 20 R651 PH@10K_6 PH@.1U-10V_4 ULI@.1U_4 B_PDIOR#
IDE_DD15 IOINSEL1 B_PDIOR# 35
B_PDD0 62 19 B_PDIOW#
IDE_DD00 IOINPIN B_PDIOW# 35
B_PDD14 63 18 R382 PH@10K_6
B_PDD1 IDE_DD14 IOINSEL0 R374 ULI@0_4
64 17
IDE_DD01 SYS_RESET_b R652 PH@100K_4 B_PDDREQ
65
IDE_RESET_b
THERMAL_PAD B_PDDREQ 35
R653 ULI@0_4 PORn B_-IDERST
B_-IDERST 35
IDE_DD13
IDE_DD02
IDE_DD12
IDE_DD03
IDE_DD11
IDE_DD04
IDE_DD10
IDE_DD05
IDE_DD09
IDE_DD06
IDE_DD08
IDE_DD07
Stuff L448, C568

Stuff R374, R653 when use ULI M5285
VDDO
C595
VDDI
when use ULI M5285

VSS
ULI@1U-6.3V_4
Unstuff R382,
R651, R652 when A1A:Add 1UF for SYS_RESET
1
2
3
4
5
6
7
8
9
B_PDD10 10
11
12
13
14
15
B_-IDERST 16
PH@SPIF3811_QFN64 B2B:Unstuff C595 when use SPIF3811

use ULI M5285
B_PDD13
B_PDD12
B_PDD11
A1A:Change Pin 21 (DD_DISABLE#) RP77 3 4 SH@0_4P2R_S Reference clock select

B_PDD2
B_PDD3
B_PDD4
B_PDD5
B_PDD9
B_PDD6
B_PDD8
B_PDD7
35 SATA_RXP0_SH SATA_RXP0 14
10K ohm PU to +3.3V 35 SATA_RXN0_SH 1 2 SATA_RXN0 14
ATAIOEN Note
0 disable PATA output
RP79 3 4 SH@0_4P2R_S 1 enable PATA output
35 SATA_TXN0_SH SATA_TXN0 14
35 SATA_TXP0_SH 1 2 SATA_TXP0 14 Operation Mode
B B
MODE[2..0]
0 0 0 Device mode 100MB/S
+3V +1.8V +3V 0 0 1 Device mode 133MB/S
XTALI 0 1 0 Device mode 150MB/S
0 1 1 RESERVE
B_PDDREQ R637 PH@5.6K_4 U53 1 0 0 Host mode 100MB/S
C871 R635 PH@10M/F_4 XTALO 1 0 1 Host mode 133MB/S
5
ULI@NC7SZ14 1 1 0 Host mode 150MB/S

B_IRQ14 R363 PH@10K_6 ULI@.1U_4 1 1 1 RESERVED
2 4 PORn Y8 PH@25MHZ Reference clock select
B_PDD7 R654 PH@10K_6 CLKSEL[1..0] External clock
C870 R649 0 0 20 MHZ
3
ULI@.1U_4 +-30PPM 0 1 25 MHZ

ULI@10K_6 C859 C842
B_PIORDY R632 PH@4.7K_6 +3V PH@27P-50V_4 PH@27P-50V_4
close to IDE Connector
Stuff all when use
ULI M5285
1.8 V Supply current for PHY blocks 120 mA
1.8 V Supply current for core logic 90 mA
A R351 PH@0_4 A
3.3 V Supply current ( for I/O) 55 mA
PROJECT : ZC1
SATA_GND

SATA/PATA A

5 4 3 2 1
1 2 3 4
CN33 +3VSUS +3V

BOM CN34 A1A:Change PATA to C178D4-14401-L A1A:Change SATA to C16654-122A4-L A1A:Add for HDD protect(G-sensor)
B_-IDERST R736 *0_4
From SATA -> PATA bridge SH@,PH@ B_PDD7 1 2 B_PDD8 E3B:Change U14 to KXP84-2050(new version IC)
B_PDD6 3 4 B_PDD9 R722 0_4 KXP84_VDD
1
B_PDD5 5 6 B_PDD10 GND1
2 SATA_TXP0_SH 34
34 B_PDD[0..15] B_PDD0 B_PDD4 7 8 B_PDD11 RXP C464 C466
9 10 RXN
3 SATA_TXN0_SH 34 B1B:Reserved +3V for
B_PDD1 B_PDD3 B_PDD12 4 security alarm cicuit
B_PDD2 B_PDD2 11 12 B_PDD13 GND2 4.7U-10V_8 .1U-10V_4
5 SATA_RXN0_SH 34
B_PDD3 B_PDD1 13 14 B_PDD14 TXN
6 SATA_RXP0_SH 34
B_PDD4 B_PDD0 15 16 B_PDD15 TXP
7 U14
B_PDD5 17 18 GND3
B_PDD6 B_PDDREQ 19 20
1 14 T53
B_PDD7 B_PDIOW# 21 22 +3.3VSATA R376 GND DNC KXP84_VDD
23 24 CSEL: 3.3V
8 +3V 2
VDD IO Vdd
13
B_PDD8 B_PDIOR# 9 SH@0_8 3 12 KXP84_SCL
25 26 0 DRIVE0 3.3V 16,39 HIGHT_G_INT MOT SCL/SCLK
A B_PDD9 B_PIORDY PSEL R614 470_4 10 4 11 KXP84_SDA A
27 28 3.3V 16,39 LOW_G_INT FF SDA/SDO
B_PDD10 B_PDDACK#
29 30
1 DRIVE1 GND
11 5
X Output ADDR0/SDI
10 ADDR0
B_PDD11 B_IRQ14 12 6 9 KXP84_CS#
B_PDD12 B_PDA1 31 32 B_-PDIAG R601 10K_4 GND +5V Z Output CS# RST_KXP84_R R270 *0_4
+5V 13 7 8 RST_KXP84 16
B_PDD13 B_PDA0 33 34 B_PDA2 GND HDD_VDD Y Output RESET
14
B_PDD14 B_PDCS1# 35 36 B_PDCS3# 5V R357 SH@0_8 C473 C476 C481 R508 *0_4
15 RST_KXP84_EC 39
B_PDD15 R592 PH@0_4 HDLED# 37 38 5V KXP84-2050
40 IDELED# 16
39 40 5V
.022U-16V_4
.022U-16V_4
.022U-16V_4
HDD_VDD HDD_VDD 17
41 42 GND
18
L70 43 44 RSVD KXP84_VDD KXP84_VDD
19
B_PDCS1# PH@C178D4-14401-L_HDD_CON HDD_VDD GND R255
+5V HDD_VDD 20
34 B_PDCS1# B_PDA0 12V 10K_4 R258
21
34 B_PDA0 B_PDA2 BK2125HS121-T_8 12V 10K_4
34 B_PDA2 22
B_PDCS3# 12V
34 B_PDCS3# B_PDA1 C808 C810 C812 C806 C554 C561 ADDR0 KXP84_CS#
34 B_PDA1 B_IRQ14
.1U-10V_4
.1U-10V_4
.1U-10V_4
150U-6.3V_7343
34 B_IRQ14 B_PDDACK# SH@C16654-122A4-L_Serial_ATA R256 R260
1000P-50V_4
.1U-10V_4
34 B_PDDACK# B_PIORDY +3.3VSATA *10K_4 *10K_4
34 B_PIORDY
Bandwidth control(250HZ)
B_PDIOR#
34 B_PDIOR# B_PDIOW#
34 B_PDIOW# B_PDDREQ C590 C596 C581
34 B_PDDREQ B_-IDERST SH@4.7U-10V_8 SH@4.7U-10V_8 SH@.1U-10V_4
34 B_-IDERST
I2C/SPI mode selection (1
Slave Address = 001100XX = 0x30 = I2C mode, 0 = SPI mode)
+3VSUS
From ICH7 bridge BAY ID STATUS Q48

R269
GS@10K_4
2
B RBAYID0/ RBAYID1/ GS@RHU002N06 B
PDD0 PDD[0..15] 14 Media Bay Connector
PDD1 LBAYID0 LBAYID1 STATUS R373 GS@*0_4 3 1 KXP84_SCL
2,16,27,29,32,33 PCLK_SMB
PDD2 CN29
PDD3
14 SATA_RXN2 1
1 2
2
SATA_RXP2 14
0 0 FDD 39 G_MBCLK
R411 GS@0_4
PDD4 3 4
PDD5
14 SATA_TXN2
16 RST_RBAY#
LBAYRST# 5
3
5
4
6
6 PDD8 SATA_TXP2 14 0 1 HDD +3VSUS
PDD6 PDD7 7 8 PDD9
PDD7 PDD6 9
7
9
8
10
10 PDD10 1 0 CD/DVD
PDD8 PDD5 11 12 PDD11
PDD9 PDD4 11 12 RBAYVCC
13 14
PDD10 +5V 13 14 PDD12 R434
15 16 B1B:Remove R141,R545,Q32 for -IDERST
PDD11 PDD3 15 16 PDD13 GS@10K_4
17 18
17 18
2
PDD12 PDD2 19 20 PDD14
PDD13 PDD1 19 20 PDD15 C200 C235 C187 C189 Q49
21 22
PDD14 PDD0 21 22 PDDREQ R429 GS@*0_4 KXP84_SDA
23 24 2,16,27,29,32,33 PDAT_SMB 3 1
PDD15 C727 PDIOW# 23 24 PDIOR# 1000P-50V_4 .1U-10V_4 .1U-10V_4 .1U-10V_4 GS@RHU002N06
25 26
+3V PIORDY 25 26 R433 GS@0_4
27 28 39 G_MBDATA
.1U-10V_4 27 28 PDDACK#
29 30
PDIOR# IRQ14 29 30 PDA2
PDIOR# 14 31
31 32
32 B1B:Add MOS for G sensor SMBUS
PDIOW# R169 PDA1 33 34 PDCS3# D2B:Change Q48,Q49 VCC to +3VSUS
PDIOW# 14 33 34
PDDACK# PDA0 35 36 RBAYID0 D2B:Add R269,R434 for SMBUS PU resistor
PDDACK# 14 35 36 RBAYID0 16
IRQ14 10K_4 PDCS1# 37 38 RBAYID1 D2B:Add R411,R433 for SMBUS
IRQ14 14 37 38 RBAYID1 16
PIORDY IDELED# 39 40 RCSEL
PIORDY 14 39 40
PDDREQ -RBAYINS 41 42 D2B:Add C967,R775,D43 for G sensor reset
PDDREQ 14 39 -RBAYINS 41 42 RBAYVCC +3VSUS
43 44
43 44
PDA[2:0] 14 45 46
PDA0 45 46 B_-PDIAG R161 R173
47 48
PDA1 47 48 C967
+3V 49 50 +3V *0_4
PDA2 49 50 470_4 GS@1U-16V_6
51 53 NC FOR SLAVE
C PDCS1# 52 54 RST_KXP84_R C
PDCS1# 14
PDCS3# BAYCON_50P
PDCS3# 14
1
A1A:change -PDIAG to B_-PDIAG D43 R775
C2A:Stuff R161,set ODD to Master
+5V C2A:Remove R173 for RBAYID GS@10K_4
GS@BAS316
2
R546
+5V LBAYON_HDD# C207 C215 C238 C232
3
10K_4 .1U-10V_4 .1U-10V_4 .1U-10V_4 .1U-10V_4

Q33
RBAYVCC 2
PDTC143TT
RBAYVCC
C2A:Remove R139,R145 for RBAYVCC(FDD)
1
+5V
ADD DISCHARGE CIRCUIT
R147 22_8
R145 F@0_8
3
R139 F@0_8
Q14
Q15
AO4414 2 RBAYON#
8 1
7 2
6 3 2N7002
5
1
D D
R154
4
Z1422
15V
3
10K_4
Q16 C211 C185 C731 C186 C184 C188
2 .1U-50V_8 1000P-50V_4 .1U-10V_4 .1U-10V_4 .1U-10V_4 PROJECT : ZC1
om
16 RBAYON# 150U-6.3V_7343
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2N7002 Quanta Computer Inc.
ai
tm
1
ho
HDD & CDROM & MEDIA BAY C
f@
in
1 2 3 4
xa
he
1 2 3 4 5 6 7 8
Option of External Volume

Control or Standby
+5V +5V_ADO
Mode/De-Pop
L71 *TI321611U480_1206
+3V_S5
C890 C892 C615 C622 C619 C907 +5V_ADO For MDC Module
.1U-10V_4 10U-25V_1206 .1U-10V_4 .1U-10V_4 .1U-10V_4 10U-25V_1206 R415 10K_4 MIC1-VREFO-L
MIC1-VREFO-L 37
A1A:Change to 39 ohm CN11 C862
+5V_ADO 1 2
ACZ_SDOUT_AUDIO GND RSV .1U-10V_4
3 4
ADOGND FRONT-L C905 10U-25V_1206 AC_SDO RSV
37 FRONT-L 5 6
ACZ_SYNC_AUDIO GND 3.3V
7 8
+5V +5V_ADO FRONT-R 14 ACZ_SDIN1 ACZ_SDIN1 R631 39_4 AC_SYNC GND
C1C:Add regulator for +5V_ADO 37 FRONT-R 9 10
ACZ_RST#_AUDIO AC_SDI GND BIT_CLK_MODEM
U19 11 12 BIT_CLK_MODEM 14
R705 0_6 ADOGND AC_RST# AC_BCLK
4 3
VEN VOUT U24 MDC R641
36
35
34
33
32
31
30
29
28
27
26
25
A A
5 C908 C840
GND
VIN
ADJ
VREF
Sense B
FRONT-R
MIC1-VREFO-R
FRONT-L
DCVOL
LINE2-VREFO
MIC2-VREFO
LINE1-VREFO-L
MIC1-VREFO-L
AVSS1
AVDD1
R372 10U-25V_1206 *10P_4 *22_4
36K_4 55mA(AVDD=5.0V)
2
G961-18ADJTEU(SOT89-5) 1 C863
+5V_ADO 37 24 LINE1-R
LINE1-VREFO-R LINE1-R LINE1-R 37
*10P_4
38 23 LINE1-L
AVDD2 LINE1-L LINE1-L 37
R371
12K_4 B1B:Change R414 p/n to CS32003F933 39 22 MIC1-R
SURR-L MIC1-R MIC1-R 37
B1B:Change MDC module pin
R414 20K/F_6 40 21 MIC1-L 12 to BIT_CLK_MODEM
JDREF/NC MIC1-L MIC1-L 37
41 20 C633 .1U-10V_4
SURR-R CD-R
Vo=1.2*(R371+R372)/R371= 4.8V
+3V
42
AVSS2
ALC883 CD-GND
19 C632 .1U-10V_4
ADOGND
43 18 C631 .1U-10V_4
ADOGND SURR-VREFO-L CD-L
44 17 C630 .1U-10V_4
C900 C909 C896 C911 SURR-VREFO-R MIC2-R
45 16 C629 .1U-10V_4
.1U-10V_4 .1U-10V_4 .1U-10V_4 10U-25V_1206 MIC2-VREFO-R MIC2-L
46 15 C628 .1U-10V_4
LINE2-VREFO-R LINE2-R
47 14 C627 .1U-10V_4
R416 SPDIFI/EAPD LINE2-L
32,37 SPDIF_OUT SPDIF_OUT 0_4 SPDIF_OUT_883 48 13
SDATA-OUT
SPDIFO Sense A
SDATA-IN
PCBEEP
BIT-CLK
RESET#
DVDD1
DVDD2
DVSS1
DVSS2
GPIO0
GPIO1
SYNC
A1A:Add 10k for PCMSPK
noise reduction
C952 *100P_6 35mA(DVDD=3.3V)
10
11
12
C891 *100P_6
R700 0_6 +3V
R713 0_6 C1C:Add C960 for ALC883 DVDD +3V R422 10K_4
B R717 0_6 C960 10U-10V_8 B
U22
5
1 PCMSPK
PCMSPK 30
ADOGND 883_AMP_MUTE# PCBEEP C620 1U-16V_6 BEEP_1 R425 10K_4 BEEP 4
37 883_AMP_MUTE#
Tied at one point only 2 ACZ_SPKR
ACZ_SPKR 16
under the codec or near
3
C616 R424 SN74LVC1G86DCKR
ACZ_SDOUT_AUDIO
CODEC-BITCLK
ACZ_SDIN0_R
ACZ_SYNC_AUDIO
CODEC-RESET#
the codec
CODEC-RESET# 100P-50V_6 1K_4 A1A:Change p/n to AL07SZ86021

ACZ_SYNC_AUDIO
CODEC-BITCLK
R702 0_4
ACZ_RST#_AUDIO 14
C915 C910 C906
ACZ_SYNC_AUDIO 14
*22P_4 *22P_4 *22P_4
R427 39_4
ACZ_SDIN0 14
R697 0_4
BIT_CLK_AUDIO 14
ACZ_SDOUT_AUDIO 14
B1B:Change R697 to 0 ohm
C C
D D
PROJECT : ZC1
ALC883 & MDC 1A

1 2 3 4 5 6 7 8
5 4 3 2 1
+5V_ADO
Audio amplifier HPPLG R430

A1A:Change audio amplifier to MAX9750
3
A1A:Change footprint to tqfn28-5x5-5-33p 1K_4
+5V_ADO +5V_ADO
Q44 LINE OUT/SPDIF
+5V_ADO 2 HPPLG# BLACK
HPPLG#: Pin5 connect to
2N7002 HP not insert->H
C902 C625 C922 C624
Pin3 on Jack
HP insert->L
1
R417 +5V_SPD
1U-16V_6
.1U-10V_4 10U-25V_1206 1U-16V_6 CN17
*6.2K_4 ADOGND HPPLG# 5 6
VOL_CTRL 4 11
D2C:Change R693,R699 from 0 to 5.1K to HPL R769 0_6 HPOUTL R703 330_4 HPOUTL_1 L73 BK1608LL121_6 HPL_SYS 2
D D
solve audio performance issue. ADOGND Low--->Speak Mode HPR R768 0_6 HPOUTR R708 330_4 HPOUTR_1 L74 BK1608LL121_6 HPR_SYS 3
R696 MAX : 0 V 1 10
32
25
15
10
31
U25 Hi ---->HP
7
ADOGND R711 R709 C933 C930
1K_4 R699 5.1K/F_6 FRONT-L_1 FRONT-L_2 1 20 HPS 8
C1P
VDD
HPVDD
C1N
CPVDD
GND4
GND3
36 FRONT-L INL HPS +3V +5V LED
MIN : 2.8 V C617 1U-16V_6 R706 0_4 SPDIFO_R 7 Drive
R693 5.1K/F_6 FRONT-R_1 FRONT-R_2 27 14 HPL 1K_4 1K_4 470P-50V_4 470P-50V_4 9 IC
( 1.5K ) 36 FRONT-R INR HPL
R423 *100K_4 C614 1U-16V_6
ADOGND R418 *100K_4 2 13 HPR C2A:Change Line out schematic R428 R707
BEEP HPR ADOGND 2FB540L-BRBTC-7F_SPDIF ADOGND
+5V_ADO VOL_CTRL 28 4 INSPKL+ ADOGND
ADOGND VOL OUTL+ INSPKL- 10K_4 1K_4
ADOGND 33 5 D2B:Change CN17 to DFTJ10FR356
SPDIFO
GND5 OUTL- INSPKR-
17
OUTR-
2
R421 GAIN1 24 18 INSPKR+ +5V_ADO Q47
GAIN1 OUTR+
GAIN2 23 6 1 3
GAIN2 PVDDL 32,36 SPDIF_OUT
10K_4 3
EC_AMP_MUTE# MUTE PGNDL C916 C914 C901 MMBT3904 +5V
1 2 22 16
CPGND
39 EC_AMP_MUTE#
CPVSS
/SHDN PVDDR D15
GND2
D23 MTW355 19
GND
PGNDR
VSS
21 29 .1U-10V_4 .1U-10V_4 10U-25V_1206
883_AMP_MUTE# VBIAS GND1 1
36 883_AMP_MUTE# 1 2
D13 *MTW355 C912 MAX9750CETI HPPLG#
26
11
12
30
3
E3B:Remove D13 for Audio Bo Bo sound 1U-16V_6
2
3
+5V +5V_SPD DA204U
C921
ADOGND ADOGND Q46 C621
1U-16V_6 R790 0_6 C927 .1U-10V_4 HPPLG# 2 For ESD close to audio out connecter
+5V_ADO
*.1U_4
GAIN2 GAIN1 SPKR HP 2N7002
ADOGND E3A:Remove Q45,add R790 for SPDIF can't use issue
1
MODE MODE R420 R695
1K_4 1K_4
0 0 6 GAIN1
C
0 C
0 1 7.5 GAIN2 +5V_ADO
1 0 9 R694 R419
R698
*1K_4 *1K_4
3
1 1 10.5 100K_4 C2A:Change Line out schematic
5
U23
ADOGND ADOGND
HPPLG 2 D14 MTW355
4 HPPLG_SYS 1 2 HPS
HPSENCE_PR 1 HPL_SYS R770 0_6
32 HPSENCE_PR SPKL_SYS 32
HPR_SYS R771 0_6
SPKR_SYS 32
R426
SN74AHC1G32DCKR
3
100K_4
ADOGND
LINEINL_SYS L78 BK1608LL121_6 LINEINL_PR

LINEINL_PR 32
D2B:Change R435 to 2.2K to meet MIC voltage reference
MIC
LINEINR_SYS L76 BK1608LL121_6 LINEINR_PR
LINEINR_PR 32 LINE IN 36 MIC1-VREFO-L
R435 2.2K_4 CN19
PINK
BLUE 1 7
CN18 C634 1U-16V_6 MIC1 MIC1_M L49 BK1608LL121_6 MIC1_SYS 2
36 MIC1-L
1 7 INT_MIC R725 0_4 6
B B
C941 1U-16V_6 LINE1-L_1 L75 BK1608LL121_6 LINEINL_SYS 2 C635 1U-16V_6 3
36 LINE1-L 36 MIC1-R
6 4
C940 1U-16V_6 LINE1-R_1 L77 BK1608LL121_6 LINEINR_SYS 3 5 8
36 LINE1-R
4
C943 C942 5 8 C639 JA6033L-P5S2-7F _MIC
JA6033L- U5S2-7F _LINEIN

470P-50V_4 470P-50V_4 470P-50V_4
C2A:Change CN18 to DFTJ06MS716 ADOGND

ADOGND
C2A:Change CN19 to DFTJ06MS724
+5V_ADO
SEL FUNCTION
LOW IN_B0 R505 0_6
C939
HIGH IN_B1 INT MIC
.1U-10V_4 MIC_GND
D2B:Reserve R726 for EMI request
U60 CN2
SPEAKER CONNECTOR ADOGND 5
VCC SEL
6 PR_MIC_IN
PR_MIC_IN 32 1
R726 0_4 INT_MIC
PR_MIC MIC1 2
1 4
CN15 32 PR_MIC IN_B1 COM R704 85204-0200L_INT_MIC C695 R510
INSPKR+ L45 BK1608LL121_6 INSPKR+N MIC1_M 3
INSPKR- L46 BK1608LL121_6 INSPKR-N 1 R716 0_6 IN_B0 22P-50V_4*1K_4
2
INSPKL+ L47 BK1608LL121_6 INSPKL+N 25 R715 0_6 GND 100K_4
INSPKL- L48 BK1608LL121_6 INSPKL-N 36 C951 .1U-10V_4
4 C950 1000P-50V_4 NC7SB3157P6X MIC_GND MIC_GND MIC_GND
C935 C936 C937 C938 ADOGND ADOGND
47P-50V_4 47P-50V_4 47P-50V_4 47P-50V_4 ADOGND

A A
85204-04001_SPEAKER-CON
ADOGND C1C:Reversed for ESD(MIC)

A1A:Change Speaker conn footprint +5V
D40
om
B1B:Change speaker p/n to DFHD04MR701
l.c
1
INT_MIC
ai
3
tm
2
PROJECT : ZC1
ho
f@
*DA204U
in
For ESD close to audio out connecter Size Document Number Rev
xa
AUDIO AMP(MAX9750) / JACK 1A
he
5 4 3 2 1
5 4 3 2 1
+3V STRAP PINS
MDTR1# R481 *10K_4

C680 C670 C50
MRTS1# R494 *10K_4
.1U-10V_4 .1U-10V_4 10U-10V_8
MTXD1 R495 *10K_4
18
17
11
32
45
U33
1
NC
NC
NC
NC
VDD
VDD
VDD
C35 R477
PCI_CLK_SIO LAD0 42 15 C64 *180P_4 PD0
14,39 LAD0 LAD0 GPIO00
D C65 *180P_4 PD1 D
*10P_4 *22_4 LAD1 46 16 C46 *180P_4 PD2
14,39 LAD1 LAD1 GPIO01 C43 *180P_4 PD3
LAD2 51 19 C45 *180P_4 PD4
14,39 LAD2 LAD2 GPIO02 C42 *180P_4 PD5
LAD3 53 23 C40 *180P_4 PD6
14,39 LAD3 LAD3 GPIO20 C33 *180P_4 PD7
PCI_CLK_SIO 33 20 C29 *180P_4 SLCT
2 PCI_CLK_SIO LCLK NS PC87383 GPIO03 C63 *180P_4 ERROR#
+3V LDRQ#0 22 21 C62 *180P_4 SLIN#
14 LDRQ#0 LDRQ/XOR_OUT GPIO04 C30 *180P_4 PE
LFRAME# 38 40 C61 *180P_4 INIT#
14,39 LFRAME# LFRAME GPIO05
R17 C60 *180P_4 AFD#
PLTRST# 35 7 C36 *180P_4 STRB#
15,16,18,27,29,32,33,39 PLTRST# LRESET GPIO06
10K_4 C32 *180P_4 ACK#
SERIRQ 36 41 C31 *180P_4 BUSY
D2 16,30,39 SERIRQ SERIRQ GPIO07
LPC_PD# 1 2 SUS_STAT_3V# 29
16 LPC_PD# LPCPD/GPIO21
CLKRUN# 27
16,30,39 CLKRUN# CLKRUN/GPO22
*BAS316
58 SIO_14M
+5V CLKIN SIO_14M 2
RN8
3 4 PD0 INIT# 56 R479 R32
32 INIT# INIT
1 2 PD1 8 IRRX *22_4
IRRX1 +3V
ERROR# 54
32 ERROR# ERR
4.7K_4P2R_S 9 IRTXOUT 10K_4
RN5 BUSY IRTX C55
32 BUSY 26
PD2 BUSY_WAIT IRMODE
3 4 10 *10P_4
PD4 AFD# IRRX2_IRSL0/GPIO17
1 2 32 AFD# 57
AFD_DSTRB/TRIS
C 4.7K_4P2R_S ACK# 28 C
32 ACK# ACK/GPO24
RN4
3 4 PD5 STRB# 14
32 STRB# STB_WRITE/TEST
1 2 PD6
SLIN# 55 3
32 SLIN# SLIN_ASTRB CTS1/GPIO11 MCTS1# 32
4.7K_4P2R_S
SLCT 24 59
32 SLCT SLCT DCD1/GPIO16 MDCD1# 32
R27 4.7K_4 PD3
R466 4.7K_4 PD7 PE 25 60
32 PE PE DSR1/GPIO15 MDSR1# 32
PD7 30 62
PD7/PGIO23 RTS1/GPIO13 MRTS1# 32
R470 4.7K_4 SLCT
PD6 34 61
PD6 SIN1/GPIO14 MRXD1 32
R496 4.7K_4 ERROR#
PD5 37 63
PD5 SOUT1/GPIO12 MTXD1 32
R497 4.7K_4 SLIN#
PD4 39 5
PD4 RI1/GPIO10 MRI1 32
R469 4.7K_4 PE
PD3 6 4
PD3 DTR1_BOUT1/BADDR MDTR1# 32
R498 4.7K_4 INIT#
PD2 43
R499 4.7K_4 AFD# PD2
PD1 50
R478 4.7K_4 STRB# PD1
PD0
VCORF
52
R467 4.7K_4 ACK# PD0
VSS
VSS
VSS
32 PD[0..7]
NC
NC
NC
NC
R468 4.7K_4 BUSY
PC87383-VS
12
31
44
13
47
48
49
64
B
C41 B
.1U-10V_4
FIR
+3V
+3V
U28
T = 20mil
R701 6
IRTXOUT VCC
3 7
TPM@10K_4 +3VSUS +3V IRRX TXD MODE C953 C955 C954
MB TO TPM1.2 MODULE 4
IRMODE RXD
5 2
D24 TPM@*BAS316 CN36 SD LED_C .1U-10V_4 10U-10V_8 10U-10V_8
8 1
LAD0 GND LED_A
16 LPC_PD# 1 2 LAD0 14,39
SERIRQ 1 2 VISHAY_TFDU6102_8P
16,30,39 SERIRQ 3 4
+3V +3V C920 C924 C919 C923
5 6 LAD1
+5V_FIR
7 8 LAD1 14,39
+3VSUS LFRAME# .1U-10V_41U-16V_6 .1U-10V_4 1U-16V_6
9 10 LFRAME# 14,39 +5V
11 12 PCLK_TPM
13 14 PCLK_TPM 2 T = 20mil
PLTRST# 15 16 LAD2 R449 5.6_1206
15,16,18,27,29,32,33,39 PLTRST# 17 18 LAD2 14,39
CLKRUN# LAD3
16,30,39 CLKRUN# 19 20 LAD3 14,39
R718 5.6_1206
TPM@88018-204G_TPM1.2
C956
A A
A1A:Change TPM CONN to 88018-204G(Pitch=0.8,H=2.65)
10U-10V_8
B1B:Change TPM pin define to same as ZH2
PROJECT : ZC1
SIO (87383),TPM 1.2 1A
5 4 3 2 1
5 4 3 2 1
Adapter ID
Watt Voltage
VCCRTC +3VPCU
65W 0.66 +/- 0.1V
+3VPCU 90W 1.32 +/- 0.1V
CN13 C618 C601 C637 C609 C623
1
135W 1.98 +/- 0.1V
RX_551 R412 10U-10V_8 .1U-10V_4 .1U-10V_4 .1U-10V_4 .1U-10V_4
52 TX_551
63 0_4 150W 2.64 +/- 0.1V
+3VPCU
4
Un-define 3.3 +/- 0.1V
*551_DEBUG
R441 Should have a 0.1uF capacitor close to every
+3VPCU +3VPCU GND-VCC pair + one larger cap on the supply.
U18
591_AVCC
MBCLK 6 1 C872 0_4 C638 C610 +3VPCU
D
MBDATA SCL A0 .1U-10V_4 .1U-10V_4 *.1U_4
D
5 2 I/O Address
SDA A1 C606 ENV1 R437 10K_4
3 BADDR1-0 Index Data
A2 0 0 2E 2F
.1U-10V_4 +3V
7 8 0 1 4E 4F
WP VCC C589 1 0 (HCFGBAH, HCFGBAL) (HCFGBAH, HCFGBAL)+1 BADDR0 R438 *10K_4
4
GND
123
136
157
166
161
.1U-10V_4 1 1 Reserved
16
34
45
95
24LC08BT_SOIC U21
A1A:Reserved GSENSOR-X/Y/Z for BADDR1 R439 *10K_4
VBAT
VDD
AVCC
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
security alarm cicuit +3V
LDRQ#(pin 8) internal is no use SHBM R440 10K_4
+3VPCU SERIRQ 7 81 TEMP_MBAT R436 SHBM=1: Enable shared memory with host BIOS
16,30,38 SERIRQ SERIRQ AD0 TEMP_MBAT 46
8 82 TEMP_ABAT +3VPCU
LDRQ AD1 TEMP_ABAT 46
LFRAME#/FWH4 9 83 10K_4
14,38 LFRAME# LFRAME AD2
R380 LAD0/FWH0 15 84 MBCLK R677 4.7K_4
14,38 LAD0 LAD0 AD3
LAD1/FWH1 14 Host interface 87 WIRELESS_SW# MBDATA R675 4.7K_4
14,38 LAD1 LAD1 IOPE0AD4 WIRELESS_SW# 40
470K_4 LAD2/FWH2 13 88 BLUETOOTH_SW#
14,38 LAD2 LAD2 IOPE1/AD5 BLUETOOTH_SW# 40
LAD3/FWH3 10 89 SUSC#
14,38 LAD3 LAD3 IOPE2/AD6 SUSC# 16
PCLK_591 PCLK_591 18 AD Input 90
2 PCLK_591 LCLK IOPE3/AD7 HWPG 42,43,44
19 93
KBSMI# LREST DP/AD8 +3V
16 KBSMI# 22 94
SMI DN/AD9
23
R656 PWUREQ CC-SET
99 CC-SET 45
DA0 CV-SET WIRELESS_SW# R431 4.7K_4
*22_4 100 CV-SET 45 A1A:Remove REFON pin ( DA3 pin 102 )
SCI# DA1 CONTRAST
16 SCI# 31 DA output 101 CONTRAST 25
IOPD3/ECSCI DA2 BLUETOOTH_SW# R432 4.7K_4
102 T85
DA3
CPUFAN# 5
GATEA20 2 1 5 32
14 GATEA20 GA20/IOPB5 IOPA0/PWM0
D20 BAS316 6 33 VFAN U56
KBRST/IOPB6 IOPA1/PWM1 T87
C873 RCIN# 2 1 36 -RBAYINS ENV0 21 25 D0
14 RCIN# IOPA2/PWM2 -RBAYINS 35 A0 D0
*10P_4 D21 BAS316 PWM 37 ENV1 20 26 D1
IOPA3/PWM3 EC_AMP_MUTE# 37 A1 D1
MX0 71 or PORTA 38 R384 0_4 BADDR0 19 27 D2
40 MX0 KBSIN0 IOPA4/PWM4 HIGHT_G_INT 16,35 A2 D2
MX1 72 39 R383 0_4 BADDR1 18 28 D3
40 MX1 KBSIN1 IOPA5/PWM5 LOW_G_INT 16,35 A3 D3
MX2 73 40 TRIS 17 32 D4
40 MX2 KBSIN2 IOPA6/PWM6 RST_KXP84_EC 35 A4 D4
MX3 74 43 SHBM 16 33 D5
40 MX3 KBSIN3 IOPA7/PWM7 A5 D5
MX4 77 D2B:Add RST_KXP84_EC for G sensor reset(IOPA6) A6 15 34 D6
40 MX4 KBSIN4 A6 D6
MX5 78 153 RX_551 A7 14 35 D7
40 MX5 KBSIN5 IOPB0/URXD A7 D7
C MX6 79 154 TX_551 A8 8 C
40 MX6 KBSIN6 IOPB1/UTXD A8
MX7 80 Key matrix scan 162 LID591# A9 7 10 VCC1_PWROK
40 MX7 KBSIN7 IOPB2/USCLK LID591# 16,25,40 A9 RESET#/NC
163 MBCLK A10 36 12
IOPB3/SCL1 MBCLK 5,19,46 A10 RY/BY#/NC T169
MY0 49 PORTB 164 MBDATA A11 6 29
40 MY0 KBSOUT0 IOPB4/SDA1 MBDATA 5,19,46 A11 NC1
MY1 50 165 PLTRST# A12 5 38
40 MY1 KBSOUT1 IOPB7/RING/PFAIL PLTRST# 15,16,18,27,29,32,33,38 A12 NC2
MY2 51 D2B:Add G-sensor SMBUS to EC(SCL2,SDA2) A13 4 11
40 MY2 KBSOUT2 A13 NC3
MY3 52 168 591_PME# A14 3
40 MY3 KBSOUT3 IOPC0 A14
MY4 53 169 A15 2 31 +3VPCU
40 MY4 KBSOUT4 IOPC1/SCL2 G_MBCLK 35 A15 VCC
MY5 56 170 A16 1 30
40 MY5 KBSOUT5 IOPC2/SDA2 G_MBDATA 35 A16 VCC
MY6 57 171 D12 1 BAS316
2 A17 40
40 MY6 KBSOUT6 IOPC3/TA1 DNBSWON# 16 A17
MY7 58 PORTC 172 FANSIG A18 13
40 MY7 KBSOUT7 IOPC4/TB1/EXWINT22 FANSIG 5 A18
MY8 59 175 R761 0_4 BUZZER D2B:Change EC_FPBACK# to IOPC6 A19 37
40 MY8 KBSOUT8 IOPC5/TA2 A19
MY9 60 176 EC_FPBACK# 23
40 MY9 KBSOUT9 IOPC6/TB2/EXWINT23 EC_FPBACK# 25 GND
MY10 61 1 PWROK_1 R385 0_4 CS# 22 39
40 MY10 KBSOUT10 IOPC7/CLKOUT PWROK_EC 16 CE# GND
MY11 64 RD# 24
40 MY11 KBSOUT11 OE#
MY12 65 26 CARDBUS_DET WR# 9
40 MY12 KBSOUT12 IOPD0/RI1/EXWINT20 CARDBUS_DET 30 WE#
MY13 66 PORTD-1 29 ACIN SST 1MB BIOS
40 MY13 KBSOUT13 IOPD1/RI2/EXWINT21 ACIN 45
+5V MY14 67 30 (AKE35ZAKK17)
40 MY14 KBSOUT14 IOPD2/EXWINT24 LVDS_BLON_EC 25
MY15 68 D2B:Change Cardbus detect to IOPD0 SST39VF080-70-4C-EIE_1M BIOS
40 MY15 KBSOUT15
2 NBSWON# ST Micro M29W008AB/AMD-29LV081B/SST39VF080
IOPE4/SWIN NBSWON# 40
105 44 SUSB#
TINT IOPE5/EXWINT40 SUSB# 16
8
6
4
2
106 PORTE 24 +3VPCU

RP46 TCK IOPE6/LPCPD/EXWIN45 CLKRUN# +5V_S5
107 25 CLKRUN# 16,30,38
TDO IOPE7/CLKRUN/EXWINT46 R692
108 JTAG debug port
4.7K_8P4R_S TDI ENV0
109 124 B1B:Reversed for G sensor buzzer
TMS IOPH0/A0/ENV0 ENV1 *10K_4
125
7
5
3
1
IOPH1/A1/ENV1 BADDR0 R743

32 MSCLK 110 126 D2B:Change buzzer power to
PSCLK1/IOPF0 IOPH2/A2/BADDR0 BADDR1
32 MSDATA 111
PSDAT1/IOPF1 IOPH3/A3/BADDR1
127 +5V,increase volume 0_4 BZ1
114 128 TRIS VCC1_PWROK
32 KPCLK PSCLK2/IOPF2 IOPH4/A4/TRIS
115 PORTH 131 SHBM 1
32 KPDATA PSDAT2/IOPF3 IOPH5/A5/SHBM 1
1
TBCLK 116 PS2 interface 132 A6 C897
40 TBCLK PSCLK3/IOPF4 IOPH6/A6
TBDATA 117 133 A7 *.1U_4
40 TBDATA PSDAT3/IOPF5 IOPH7/A7
CAPSLED# 118 2
40 CAPSLED#
2
NUMLED# PSCLK4/IOPF6 D0 2
40 NUMLED# 119 138
PSDAT4/IOPF7 IOPI0/D0 D1
139
IOPI1/D1 D2 KCVG084B16_BUZZER
140
IOPI2/D2
3
141 D3 330_4
591_32KX1 PORTI IOPI3/D3 D4 BUZZER R742 Q32
158 144 2
B 32KX1/32KCLKOUT IOPI4/D4 D5
B
145 MMBT3904
R686 20M_6 591_32KX2 IOPI5/D5 D6
160 146
1
32KX2 IOPI6/D6 D7
147
R680 IOPI7/D7
150 RD#
PORTJ-1 IOPJ0/RD WR# U57
151
IOPJ1/WR0
1
2
121K/F_6 12 13 D0
Y10 A0 D0 D1
152 11 14
SELIO A1 D1 D2
32.768KHZ 10 15
M/A# A2 D2 D3
40 PWRLED# 62 41 M/A# 46 9 17
CHANGED FROM PR_INSERT# PR_STS IOPJ2/BST0 IOPD4 CELL-SET A3 D3 D4
32 PR_STS 63 42 CELL-SET 46 8 18
4
3
IOPJ3/BST1 PORTD-2 IOPD5 D/C# A4 D4 D5

29 USBON# 69 54 D/C# 46 7 19
IOPJ4/BST2 IOPD6 BL/C# A5 D5 D6
40 SUSLED# 70 PORTJ-2 55 BL/C# 46 6 20
IOPJ5/PFS IOPD7 A6 D6 D7
40 BATLED0# 75 5 21
C895 C885 IOPJ6/PLI A8 A7 D7
40 BATLED1# 76 143 27
10P-50V_4 10P-50V_4 IOPJ7/BRKL_RSTO IOPK0/A8 A9 A8
142 26
IOPK1/A9 A10 A9 A18
29 RF_EN 148 135 23 1
BT_POWERON# IOPM0/D8 PORTK IOPK2/A10 A11 A10 VPP
29 BT_POWERON# 149 134 25
IOPM1/D9 IOPK3/A11 A12 A11
16,27 RSMRST# 155 130 4
IOPM2/D10 PORTM IOPK4/A12 A13 A12
25 CCD_POWERON# 156 129 28
VRON IOPM3/D11 IOPK5/A13/BE0 A14 A13
41 VRON 3 121 29
MAINON IOPM4/D12 IOPK6/A14/BE1 A15 A14 +3VPCU
20,32,42,43,44 MAINON 4 120 3
SUSON IOPM5/D13 IOPK7/A15/CBRD A15
32,42,43 SUSON 27 2
S5_ON IOPM6/D14 A16 A16
42 S5_ON 28 113 30 32
IOPM7/D15 IOPL0/A16 A17 A17 VCC
112
CS# IOPL1/A17 A18 CS# C875
173 PORTL 104 22
SEL0 IOPL2/A18 A19 RD# CE#
174 103 24
SEL1 IOPL3/A19 WR# OE# .1U-10V_4
47 48 31 16
CLK IOPL4/WR1 WE# GND
A1A:Reserved for debug use *PLCC32_BIOS
AGND
GND1
GND2
GND3
GND4
GND5
GND6
GND7
+3VPCU
NC10
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
BIU configuration should match flash speed used

LED6 PC97551
17
35
46
122
159
167
137
96
11
12
20
21
85
86
91
92
97
98
R684 330_4 ECPWRLED 2 1 PWRLED# 40

LED_G_LTST-C190KGKT
A A
C588
1U-16V_6
FOR 97551 ONLY
om
SW4
NBSWON# 1 3
40 NBSWON#
l.c
2 4 +3V_S5 +3V_S5 +3VPCU
ai
tm
PROJECT : ZC1
ho
R377 2 R388
f@
B1B:Change SW4 p/n to DHP00BB1J03 *4.7K_4 *4.7K_4
INTERNAL PULLUP IN SB Q22
in
PDTC143TT Size Document Number Rev
xa
16,27,29 PCIE_WAKE# 1 3 591_PME# 97551 & FLASH 1A
he
5 4 3 2 1
5 4 3 2 1
+3VPCU
INT K/B REVB P/N&FT CHANGE
CN6 RP42 CA3 220P-50V_8P4C CA4 220P-50V_8P4C
MY15 MX7 10 1 MY3 MY1 1 2 1 2 MY7
39 MY15 1
MY14 MX6 MY4 9 2 MY2 MY2 3 4 3 4 MY6
39 MY14 2
MY13 MX5 MY5 8 3 MY1 MX4 5 6 5 6 MY5
39 MY13 3
MY12 MY0 MY6 7 4 MY0 MY3 7 8 7 8 MY4
39 MY12 4
MY11 MY1 MY7 6 5
39 MY11 5
MY10 MY2
39 MY10 6
MY9 MX4 10K_10P8R
39 MY9 7
MY8 MY3 CA7 220P-50V_8P4C CA5 220P-50V_8P4C
39 MY8 8
MY7 MY4 RP43 MY12 1 2 1 2 MX2
39 MY7 9
MY6 MY5 10 1 MY11 MY13 3 4 3 4 MY9
39 MY6 10
MY5 MY6 MY12 9 2 MY10 MY14 5 6 5 6 MX3
39 MY5 11
D MY4 MY7 MY13 8 3 MY9 MY15 7 8 7 8 MY8 D
39 MY4 12
MY3 MY8 MY14 7 4 MY8
39 MY3 13
MX7 MX3 MY15 6 5
39 MX7 14
MX6 MY9
39 MX6 15 +3VPCU
MY2 MX2 10K_10P8R CA6 220P-50V_8P4C CA2 220P-50V_8P4C
39 MY2 16
MX5 MX1 MX1 1 2 1 2 MY0
39 MX5 17
MX4 MY10 RP45 MY10 3 4 3 4 MX5
39 MX4 18
MX3 MY11 10 1 MX3 MY11 5 6 5 6 MX6
39 MX3 19
MX2 MX0 MX4 9 2 MX2 MX0 7 8 7 8 MX7
39 MX2 20
MY1 MY12 MX5 8 3 MX1
39 MY1 21
MY0 MY13 MX6 7 4 MX0
39 MY0 22
MX1 MY14 MX7 6 5
39 MX1 23
MX0 MY15
39 MX0 24
10K_10P8R
25
PTWO_KB
TOUCH PAD
A1A:Change SW p/n
20 MIL SW3 SLIDE_SWITCH_WL To BUTTON board
L35 +3VPCU +3VPCU
+5V_TP C460 .1U-10V_4 WIRELESS_SW# 4 1 CN3
+5V 39 WIRELESS_SW#
BK2125HS330_8 C77 1
3
2
2 MX0
3 MX0 39 eManager
SW2 SLIDE_SWITCH_BT .1U-10V_4 MX1 Launch Manager
4 MX2 MX1 39
5 MX2 39 Internet
R244 R243 BLUETOOTH_SW# 4 1 MX3 E-mail
39 BLUETOOTH_SW# 6 MX3 39
C TOP CONTACT MY10 C
10K_4 10K_4 7 NBSWON# MY10 39
Power
3
2
8 CAPSLED NBSWON# 39
CONNECT TO TP/B 9 EMAIL_LED
CN7 10 IDE_LED
B1B:Mini card WLAN LED low active(LED5) 11 NUMLED
L38 LZA10-2ACB104MT_6 TP_DATA 1 LED5 R448 330_4 12 PWRLED#
39 TBDATA 29 WIRELESS_LED 1 2 +3V PWRLED# 39
L37 TP_CLK 2 LED_Y_LTST-C190KFKT 13 LID591#
39 TBCLK 3 6 14 LID591# 16,25,39
LZA10-2ACB104MT_6
4 5 R447 330_4 LED4 15
1 2
C459 C458 LED_B_LTST-C190TBKT BT_LED 29 16
85201-0405L_MB TO TP/B 88502-1601_BUTTON
*.1U_4 *.1U_4 A1A:Change footprint to LEDLTST-C190TGKT
A1A:Change p/n to 85201-16051
+3V D2B:Change CN3 to DFFC16FR089
D2B:Change CN7 to
DFFC04FR175(88264-0401) TOP CONTACT
D2B:Change R40,R46,R52 from 330 to +5V R40
220,increase LED brightness 150_4
R59 IDELED R786 *0_4
3
E3A:Change R40,R46,R52,R785 from 220 to IDELED 1 2 IDE_LED
150(CS11502JB22) increase LED brightness 10K_4
Q9
IDELED# 2
35 IDELED# 2N7002
+3V
+3V
1
B B
5
R52 U64
+3V
150_4 IDELED 2
NUMLED 4 IDE_LED
3
SATALED 1
+3V R785
+3VPCU LED2 150_4
1 SUSLED# NUMLED# 2 2N7002 SATALED SN74AHC1G32DCKR
SUSLED# 39
3
R450 330_4 39 NUMLED# Q8 R50
3
3
2 PWRLED#
PWRLED# 39
SH@10K_4
1
LED_G/Y_LTST-S326KGJSKT 2 Q7
14 SATA_LED#
D2B:Add U64,R785 for IDELED function
LED3 SH@2N7002
1 BATLED1# +3V
BATLED1# 39
R451 330_4 3
1
2 BATLED0#
BATLED0# 39
R58 +3V
LED_G/Y_LTST-S326KGJSKT 330_4
EMAIL_LED R46
3
150_4 CAPSLED
3
EMAIL_LED# 2 2N7002
16 EMAIL_LED# Q11
CAPSLED# 2 2N7002
39 CAPSLED# Q6
1
A A
1
PROJECT : ZC1
SWITCH,LED,K/B,TP 1A

5 4 3 2 1
1
8736VCC +5VPCU
VIN_8736_1
B1B:Change PC53 p/n CH5222K9A09
D2B:Change PR71 143K to 178K(CS41783F918) B1B:Change PC109 footprint to CC0805 HI0805R800R-10_8
D2C:Change PR71 to 178K(CS41783F900) PR64 PL10
VIN
10/F_4
1
PC59 PC53 PC118
2.2U_8 2.2U_8 PD18
21
30
+
MTW355 PC103 PC104
PC101 10U/X7R-25V_1210
VCC
VDD
2
.01U-50V_6 10U/X7R-25V_1210
PR71 178K/F_6 14 25 2 1 470U-25V_ECAP
OSC BST1
B1B:Change PR70 p/n to CS37153F917 PR104 0_6
5
PR70 71.5K_6 15 PC109 PQ23
TIME .22U-50V_8 NTMS4707 8/1 Add for Acer request
B1B:Change PC118 p/n to CC74704MZ18
PC61 470P-50V_4 17 27 4 E3B:PC118 change to CC74704MZ26
CCV DH1
1
2
3
PR68 249K/F_4 16 C1C:Change PQ23,PQ22 p/n
ILIM
PC62 .22U-50V_8 19 PL8

REF
Max Current 36A
26 VCC_CORE
1.5K/F_6 LX1 0.36uH
PR69 18
1
TRC
5
PQ22 + +
B1B:Change PC62 footprint to CC0805(BOM) NTMS4108 PC51
PC60 470U-2.5V_7343
2
8/1 modify for accompany with choke 32 4 .01U-50V_6
DL1
1
2
3
PC50
470U-2.5V_7343
9/28 change
31
PGND
4 H_VID0 34
D0
6
CSP1
4 H_VID1 35
D1
36 PR105
4 H_VID2 D2
37 NTC_10K_6 PR59 1.62K/F_6
4 H_VID3 D3 PC55
38 PR56 0_4 +5VPCU
4 H_VID4 D4 .22U-10V_4 PR103 VIN_8736_2 PL11
39 B1B:Change PC63 footprint to CC0805 HI0805R800R-10_8
4 H_VID5 D5 3.01K/F_4
VIN
4 H_VID6 40
D6
5
CSN1
PC108 PC64 PC107 PC110
1
4700P-25V_4 PU9 2.2U_8 PD10 PC106 10U/X7R-25V_1210 10U/X7R-25V_1210
MTW355 .01U-50V_6
VCC
5
PQ24
4 10 NTMS4707
GND BST PR75
0_4 4
29 PC63
PWM3 .22U-50V_8 C1C:Change PQ24,PQ25 p/n
1
2
3
10 PR66 0_4 5 9
A CSP3 8736VCC DLY DH A
PR74
9 5.1K/F_4
CSN3
PL9
8 VCC_CORE
PR55 0_4 8736EN LX 0.36uH
39 VRON 4
SHDN
1
PC54 33 DRSKP# PR73 0_4 7 + PC56 + PC57
DRSKP EN
5
100P-50V_6 2 PQ25
DL NTMS4108 PC52 470U-2.5V_7343
2
28 PWM2_8552 6 .01U-50V_6
PWM2 PR72 PWM
4
0_4
3 470U-2.5V_7343
1
2
3
PGND
9/28 change
8 PR65 *0_4 MAX8552

CSP2 8736VCC
PR54 0_4 3
16 PM_DPRSLPVR DPRSLPVR
A1A:Change p/n to AL008552004
PR53 PR108 PR63 1.62K/F_6
*100K_4 NTC_10K_6
PC58
.22U-10V_4 PR62 0_4
PR52 0_4 2 PR107

3 PSI# PSI 3.01K/F_4
PR51 7
*100K_4 CSN2
+3V PC111
B1B:Change PR58 p/n to CS21912FB13 4700P-25V_4
VCC_CORE +3V
PR61 PR43 PR58
100K/F_4 100K/F_4 1.91K_4
2 1 H_VID0
PR57 0_4 24 PR113 PR50 *100K/F_4
3,8,16 DELAY_VR_PWRGOOD IMVPOK
13 PR67 10.5K/F_4 100/F_6
PR42 0_4 VPS H_VID1
2,16 VR_PWRGD_CK410# 1 2 1
CLKEN PR111 10/F_4 PR49 *100K/F_4
12
PR60 0_4 FBS
3 H_PROCHOT# 22
VR_HOT H_VID2
2 1
PR48 *100K/F_4
PC117 PR115 VCCSENSE 4
1000P-50V_4 *27.4_4 VSSSENSE 4 2 1 H_VID3
PR47 *100K/F_4
2 1 H_VID4
23 11 PR110 10/F_4 PR46 *100K/F_4
+3V THRM GNDS
PR109
1K/F_6 2 1 H_VID5
PC116 PR45 *100K/F_4
PR106 PC112
*10K_4 100P-50V_6 1000P-50V_4 PR114 PR112 2 1 H_VID6
20 *27.4_4 100/F_6 PR44 *100K/F_4
GND
PU8 MAX8736
om
PROJECT : ZC1
l.c
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VCORE (MAX8736) 1A
f@
in
1
xa
he
5 4 3 2 1
D D
PCN2
1 2
3 4 +3VSUS
5 6
7 8
9 10
11 12
A1A:Change to HWPG 39 S5_ON +3VPCU
13 14
39,43,44 HWPG 15 16 +3V_S5
43 MAIND 17 18 +3V
3 1999_SHT# 19 20
SUSD
21 22
15V 23 24
VL 25 26
+5VPCU 27 28
+5V_S5 29 30
31 32 +5V_S5
33 34
35 36 +5V
+5V 37 38
39 40
41 42
43 44
VIN 45 46 VIN
47 48
49 50
88075-05001_POWER
C C
8/2 UPDATE CONN PIN DEFINE
A1A:Del +5VSUS discharge
VIN +1.8VSUS +3VSUS 15V
PR139 PR141 PR142 PR138

1M/F_4 22_8 22_8 1M/F_4
SUSD
3
3
2 2 2 2
32,39,43 SUSON
PR140 PC139
PQ35 1M/F_4 PQ36 PQ37 PQ34 *2200P_6
DTC144EUA 1 2N7002 2N7002 2N7002
1
B B
VIN SMDDR_VTERM +1.8V +2.5V +1.5V +1.1V_VGA +3V +5V 15V
PR137 PR145 PR144 PR143 PR147 PR148 PR146 PR136 PR135

1M/F_4 22_8 22_8 22_8 22_8 22_8 22_8 22_8 1M/F_4
MAIND
MAIND 43
3
3
3
2 PR133 2 2 2 2 2 2 2 2
20,32,39,43,44 MAINON
PC132
1M/F_4
PQ30 PQ40 PQ39 PQ38 PQ42 PQ43 PQ41 PQ32 PQ31 *2200P_6
1
DTC144EUA 2N7002 2N7002 2N7002 2N7002 2N7002 2N7002 2N7002 2N7002

1
1
A A
PROJECT : ZC1
1A
DISCHARGE/CONNECTOR
5 4 3 2 1
5 4 3 2 1
VIN8743 VIN
PL15
1
8743DL1 HI0805R800R-10_8
VIN8743 PD11
DAP202U
D PC129 PC137 D
1
Max Current 15A 10U/X7R-25V_1210
D1
D1
S2
G2
4.7U-6.3V_8 +5VPCU
PC128 PR129
VIN8743 8743VCC
10U/X7R-25V_1210 PQ29
4
FDD8876 10/F_4
22
4
Max Current 6A
S1/D2
PC73 PU13 PC134
B1B:Remove JP3,4 for +1.8VSUS 1 8743BST2 19 21 4.7U-6.3V_8 PQ33
V+
VCC
G1
BST2 VDD PC133 SI4914DY
3
+1.8VSUS PL14 .1U-50V_8 8743DH2 18 25 8743BST1
8
1.5UH_CDRH125S-1R5_13A DH2 BST1 8743DH1 +1.5V
8743LX2 17 26 8743DH1
LX2 DH1 .1U-50V_8 PL16
4
16 27 8743LX1
1
PC68 PC69 PC71 PC70 PQ28 CS2 LX1 3R8UH_CDRH104R-3R8_6A

1
+ + FDD8896_NL 1 8743DL2 20 24 8743DL1
1
DL2 DL1 PC74 PC136 PC138
1
15 28 + PC135
.1U-50V_6
10U-25V_1206
470U-2.5V_7343
470U-2.5V_7343
2
OUT2 CS1
8743FB2 14 1 10U-25V_1206
.1U-50V_6
10U-25V_1206
470U-2.5V_7343
2
2
FB2 OUT1
1
2 8743FB1
HWPG FB1
7
1
PR134 PC131 PGOOD PC130
5
2
82K_6 *100P_6 MAINON TON PR131
11
ON1 MAX8743 8743REF *100P_6 5.1K/F_4
2
C
B1B:Change PQ28 to BAM88960010 32,39,42 SUSON 12
ON2 C
B1B:Change PR134 p/n to CS38063F911 REF
10
+1.8VSUS +1.8V 8743ILIM213 6
PQ7 PR132 ILIM2 SKIP PC72
FDS6676AS_NL 100K/F_4 8743ILIM1 3 1U-10V_6
ILIM1 PR125 8743REF
8 1 23
OVP
UVP
GND 10K/F_4
7 2 D2B:Change PR126 10K CS31002FB26 to 220K CS42202FB10
6 3
5 D2B:Change PR134 to 82K CS38203F911
8
1
PC47 8743VCC
+3V_S5 15V PR126 PR128
4
10U-25V_1206 220K/F_4 10K/F_4

2
+3VSUS
8743ILIM1 8743ILIM2
PR152 PR153
E3B:Change PQ7 p/n to FDS6676(BAM66760018)
100K/F_4 100K/F_4 PR127
S5_ON PR124 100K/F_4
39,42 S5_ON
R782 *0_4 PR130 150K/F_6
MAIND 42
*100K/F_4
3
HWPG
39,42,44 HWPG
+2.5V 2 2
B1B:Remove PR130 for HWPG
PQ45 PQ46
Max Current 2A
2N7002E 2N7002E D2B:Add R783,remove PR38 for VGA +2.5V power sequence
B D2B:Add PR152,PR153,PQ45,PQ46 for VGA +1.8V power sequence B
1
R783 0_4
Max Power Consumption 1.6W
20 PCIEVDDRPG PU6
PR38 *0_6 1 5 B1B:Remove JP2 for +2.5V
20,32,39,42,44 MAINON NC0 NC2
B1B:Need add voltage divider for pin 2(SD)
2 6 VTT_SRC +2.5V
SMDDR_VREF EN VO
PU11 G2996
2 4 PC114 +3VSUS 3 8
20,32,39,42,44 MAINON SD VREF VIN GND0
PC44
+1.8VSUS 5 .1U-50V_6 *.1U_6 4
ADJ
VDDQ NC1
6 3
AVIN VSENSE SC4215 PC91 PC42 PC89
7
TGND
8 PC36 PC88 10U-10V_8 10U-10V_8 .1U-50V_6

GND
VTT SMDDR_VTERM
+1.8V 7 10U-10V_8 .1U-50V_6
PVIN
0.8V R1
1
VTT-ADJ
PC102 PC105 +
2
10U-10V_8 .1U-50V_6 PC113 PC115 PC100 PR100
.1U-50V_6 10U-10V_8 150U-4V_3528 32.4K/F_4
2
PR101
15K_4 R2 B1B:Change PU6 p/n CS33242FB19
1
A
B1B:Stuff PC100 for SMDDR_VTERM A
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PROJECT : ZC1
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+2.5V/+1.8VSUS / +1.5V A
xa
he
5 4 3 2 1
1 2 3 4 5
VIN1V05
PL12
VIN
1
PC122 PC123 HI0805R800R-10_8
B1B:Change PU12(VDD) to +5VPCU
10U/X7R-25V_1210
2
+5VPCU 10U/X7R-25V_1210
5
6
7
8
A PQ26 A
FDS6612A
2
4
1
PC121 PC124 PR77 PD19
+3V 4.7U-6.3V_8 .1U-50V_6 22_6 MTW355
2
PU12
1
14 17
VDD V+
3
2
1
B1B:Remove PR123 for HWPG PR123 2 1 VCCA-1V05 15 19 PR119 0_6 PC119 .1U-50V_8
VCC BST
Max Current 8A
PC65 4.7U-6.3V_8
A1A:Change to HWPG *100K/F_6 18 1 DH-1V05 PL13
SKIP DH CHOKE 1.5UH +-20% 13A(PCMC104T-1R5MN)EP
39,42,43 HWPG PR122 0_4 1714PG 10 20 LX-1V05
PGOOD LX +1.05V
1
PR116 0_6 3 13 DL-1V05 PC67 PC66
20,32,39,42,43 MAINON
5
6
7
8
SHDN DL PC126
+ + + PC127
A1A:Change to MAINON 6 12 PQ27
ILIM PGND FDS6690AS .1U-50V_6 10U-10V_8
2
2 9 4 470U-2.5V_7343 470U-2.5V_7343
PR121 34K/F_6 N/C N/C_1
1714REF-1V05 7 11
REF N/C_2
VCCA-1V05 PR76 *0_4 16 5 C1C:Change PL13,PC66,PC67 to improve 1.05 efficiency over 80%
PR120 TON OUT
PC125 8 4
3
2
1
100K/F_6 AGND FB PR118 PC120
1U-10V_6 MAX1714A
6.49K/F_4 .1U-50V_6
PR117
118K/F_4
B1B:Change PR117 p/n to CS41182FB10
B B
+5VPCU
VIN_1993
PL4
HI0805R800R-10_8
PR21 20_6 VGA_P_VCC
VIN
+3V
1
PC16 D2B:Add R777 for VDDCPG
1
1
PC15
PC75 PC76 PC78 PD3 1U-10V_6 1U-10V_6
2
.1U-50V_6 2200P-50V_4 PC77 MTW355
2
2
R784 220_4
VDDCPG 20
19
24
22
VIN_1993
VGA_BST
PR8
10U/X7R-25V_1210 10U/X7R-25V_1210 PR18 100K/F_4
OVP/UVP
VDD
VCC
9
8
7
6
5
0_6 14 C973 *.1U-10V_4
V+
17
BST 1993PG PR9 0_4
4 HWPG 39,42,43
PQ9 4 1993_DH 15 POK
SI7392DP DH
9/30 Modify PL5 rating to 17A 3
1
PC9 LSAT
3
2
1
1.2V OR 1.0V @ 18A ASIC VDDC,VDDCI PL5 .1U-50V_6 23 PR20 0_4

SHDN MAINON 20,32,39,42,43
1.5UH_SIQH126-1R5PF_17A
2
1993_LX 16 21 PR19 0_4
+1.1V_VGA LX GATE V_PWRCNTL 19
7 VGA_REFIN PR5 75K/F_6 VGA_P_REF PC17
1
PU2 REFIN *.1U_6

1
9
8
7
6
5
+ + 1993_DL 18
1
PC2 DL MAX1993
.1U-50V_6 PR6 PC5
2
PR3 4 20 75K/F_6 470P-50V_4
2
698/F_6 GND
8 V_PWRCNTL M56
3
2
1
PC3 PC4 PQ8 OD

11
CSP
470U-2.5V_7343 470U-2.5V_7343 SI7336ADP
PR16 LO 1.2V
1 2
12
CSN
*0_6 PR2 HI 1.0V
PC6 1 39K/F_4
VGA_CSP 10 TON
OUT
FBLANK
C .47U-10V_6 6 VGA_P_REF +1.1V_VGA=2*(PR2+PR6)/(PR2+PR5+PR6) C
PR4 0_6 VGA_OUT_R REF
9
SKIP
ILIM
FB
9/30 chnage PR2 to 39K(VGA HI voltage to 1.2V)
1
PR7 PC7
13
140K/F_4 1U-10V_6
2
1
PC8 PR11
470P-50V_4 100K/F_4
2
D D
B1B:Change PR39 p/n to CS32003F933

D2B:Remove PR39,PR40,PR41,PC46,PC48,PC49,PC98,PC99,PU7 for +1.2V_VPCIE PROJECT : ZC1
Custom +1.05V/+1.2V_VGA/+1.2V 1A

1 2 3 4 5
8 7 6 5 4 3 2 1
A1A:Change footprint to 20277-05XX-5P-L

C2B:Change PJ2 to DFHD04MS988(4 PIN)
D2B:Change PJ2 footprint to 4 pin PR99 B1B:Change PD17 p/n to LF
VA 0.01_1W_3720
PJ2 C1C:Remove fuse,bead 1
D
1 1 2 3 VA2 46 D
2
2 PD17
PC97
1P
2P
SBM1040
3 .1U-50V_6
4 PC37 PC38 PC43
.1U-50V_6 .1U-50V_6 .1U-50V_6 7/29 Modify for 3 cell setting

20277-044L_POWER_CONN
PD8
VAD PR30
MTW355
VREFIN
8724CELLS
PL7
10K/F_4 HI0805R800R-10_8
2
PC40 PR94
PR34
10K/F_4 2 PD7 1U/25V_8 10K/F_4
1
DA204U
PC35 .01U-50V_6 3 +3VPCU
CSSN
CSSP
1 VH
6
PC41
PQ6 PR95 PR31 33_6
5
6
7
8
IMZ2 .1U-50V_6 PC29 PC27
0_4
IMD .1U-50V_6 10U/X7R-25V_1210
2
PU5
27
26
PR96 MAX8724 8724DH 4
1
PC39 PC87
CSSP
CSSN
1
46 REF3V
1 17 1U-10V_6 1U-10V_6 PC26
0_6 PR149 PC30 DCIN CELLS 10U/X7R-25V_1210
7/29 modife connect REFP to VIN 7/29 modife connect REF3V to +3VPCU *0_6 2 8724LDO PQ20
8/16 Change for 5R6 choke
C PD9 USE DEFAULT 4.2V/CELL .1U-50V_6 LDO AO4422 PR93 C
MTW355 22 0.01_1W_3720
3
2
1
PD15 VAD DLOV
8724LDO PR98 0_6 10 PD16 PL6
ACIN
VIN 24 8724BST 1 2 BAT-V 46
BST
PC96 PR97 *0_4 15 MTW355 5.6U(PLC-1055-5R6)L-F
MTW355 39 CV-SET VCTL
PR25 PC34 PC85
1P
2P
.1U-50V_6 13 25 .1U-50V_6 8724DH PC86 PC33 PC32
39 CC-SET ICTL DHI
5
6
7
8
47K/F_6 PC25
PR150 VREFIN 12 23 8724LX PQ18 .01U-50V_6
PC31 PC28 REFIN LX AO4704
10U/X7R-25V_1210
10U/X7R-25V_1210
10U/X7R-25V_1210
10U/X7R-25V_1210
PR22 47K/F_6 *0_6 11 21 8724DL 4
1000P-50V_41000P-50V_4 PR151 ACOK DLO
*0_6 9 20
ICHG PGND
PU4A
8
28 19 CSIP
PR32 IINP CSIP
3 18 CSIN
+ 8724LDO CSIN
1 8
3
2
1
SHDN
2 7/29 change from 4422 to 4704
- PR24 0_4 BAT-V
16
LM393 BATT
7
4
PR23 10K/F_4 CCV 8724REF

4
REF
22K/F_4 6
CCI PR37 6.65K/F_6
3
CLS
5
GND
GND
CCS
2
PC18 OSC PR33 PR36 PR35 PR102 PC95
200KHz 10K/F_6
14
29
220P-50V_4 1K/F_6 0_4 0_4 1U-10V_6
1
PC90 PC93 PC94
.1U-50V_6 .01U-50V_6 .01U-50V_6 Charge Current max setting = 0.8C

B CURRNT LIMIT POINT = 4.5A (95% adapter power) B
E3B:PR37 change from 8.25K to 6.65K(CS26653D900)

E3B:PR102 change from 14K to 10K(CS31003B919)
PR80 10K/F_4
39 ACIN
VAD 1 2
PR79 PD12 ZD12V
6.8K/F_4
PR81
10K/F_4 7/29 delete
A A
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PROJECT : ZC1
ho
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BATTERY CHARGER 1A
he
8 7 6 5 4 3 2 1
1 2 3 4 5
A1A:Change p/n to DFHD07MR391

B1B:Change CN26 footprint to 20175A-07G1-7P-R
1ST_BATT_CONN
C1C:Remove fuse D2B:Change PQ12 to FDS6679(BAM66790014)
CN26
PQ12 PQ16
1 MBAT+ 1 8 8 1
2 TEMP_MBAT
TEMP_MBAT 39 2 7 7 2
3
3 6 6 3
PC11
8 4
PC13
4 5 5 4
9 5
1
PR89
6
1
FDS6679 AO4411 10K/F_4
7 PC12 PC79 PC19
A A
2
MAIN_BATTERY 47P-50V_4 47P-50V_4 10U/X7R-25V_1210
.1U-50V_6
PQ4
2
47P-50V_4
3
PDTC143TT
PR14 PR13
330_4 330_4 2 MDISCHG
1
PQ11
1
MBDATA_MBAT ADISCHG 2 IMD2
MBCLK 5,19,39
1
1
PQ10 VH VH
PD2 PDTC143TT
PD4
1
RLZ5.6B
6
ZD5.6V PC81
PR83
2
2
.1U-50V_6 1M/F_4
PU10A
8
ACHG PR86 LM358ADR
10K/F_4 PR85 3 MCHG
+
CLOSE TO BATTERY CON 1
- 2
470K_6
4
1
REF3V E3B:PQ19 change to FDS6676(BAM66760018) PD13
PQ19 RLZ15B
AO4414-LF
VIN
8 1 VH
2
45 BAT-V PU10B
7 2
1
6 3 LM358ADR
3
2
1
B PR12 5 PR84 5 ACHG PC92 PC80 B
+
10K/F_4 PC83 7 10U/X7R-25V_1210 PQ21 .01U-50V_6
2
.01U-50V_6 6 PR15
4
470K_6 - FDS6612A
10K/F_4
TEMP_MBAT
1
PR82 PC84
4
1
PD14 100K/F_4 1 2
PC14 RLZ15B
3
.01U-50V_6
2
.01U-50V_6
5
6
7
8
PQ44 PQ2
2
AO4414-LF VA2
VA2 45
C1C:Add PQ44 for charger 8 1 PDTC143TT
7 2
1
6 3
5 REFP VIN
VL VL
200mil
16
15
14
13
12
11
10
4
9
7
PU3
VDD
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
ADISCHG PU4B PR91
2ND_BATT_CONN PR92 74HCT237 LM393 160K/F_6
10K/F_4 PR17
GND
CN27 TEMP_ABAT 39
C1C:Remove fuse 10K/F_4
GL
G1
G2
C
A
B
PQ17 PQ15 5 REF3V
1 ABAT+ +
1 8 8 1 7
1
2
3
6
5
8
2
3
TEMP_ABAT 2 7 7 2 6
3 -
3 6 6 3
8 4
4 5 5 4 2
9 5
6
1
C PR28 PC21 PC24 PC22 AO4411 AO4411 PQ5 PC10 C

7 PC82 PDTC143TT .1U-50V_6 PR10
1
1
SECOND_BATTERY PR27 PC20 330_4 47P-50V_4 .1U-50V_6 47P-50V_4 100K/F_4

2
10U/X7R-25V_1210
3
330_4 47P-50V_4 PQ14

39 CELL-SET
2
3
IMD2
MDISCHG 2
39 D/C#
MBCLK PQ13 2
PDTC143TT 39 BL/C#
PQ3 PR26
1
MBDATA_ABAT 2N7002 120K/F_4

1
1
PD6 PD5 MCHG
ZD5.6V ZD5.6V PR90
10K/F_4
2
CLOSE TO BATTERY CON
REF3V +3VPCU SEL FUNCTION

REF3V 45
D LOW IN_B0 D
PR88 PR87 HIGH IN_B1

PR29
10K/F_4 10K/F_4 10K/F_4
U39
TEMP_ABAT 5 6 M/A#
1ST_BATT VCC SEL M/A# 39 PROJECT : ZC1
1
MBDATA_MBAT 1 4 MBDATA 5,19,39

PC23 IN_B1 COM
.01U-50V_6 MBDATA_ABAT 3 Quanta Computer Inc.
2
IN_B0
2ND_BATT 2
GND Size Document Number Rev
BATTERY SELECT A
NC7SB3157P6X
1 2 3 4 5

Acer TravelMate 8200 8210 8202wlmi - QUANTA ZC1 - REV 1A Sec

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Acer TravelMate 8200 8210 8202wlmi - QUANTA ZC1 - REV 1A Sec

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Available Formats

5 4 3 2 1

EV@: Stuff when external VGA used

VRAM X 4(GDDR3) Connector TV out / CRT Switch

LPC O2 711MP1 SPI FLASH

Super I/O TPM 1.2

FSC FSB FSA CPU SRC PCI

+1.05V R328 *56.2/F_4 swap

RHU002N06 10K_4 10K_4 R586 10K_4 "1" : PEREQ#

RHU002N06 R571 0_4 CLK_BSEL2 R570 1K_4

Date: Friday, December 09, 2005 Sheet 2 of 46

14 H_A20M# A6 A25 H_THERMDC 5 AC25

LINT0 +1.05V H_D#27 T24 D[26]# D[58]# H_D#59

RSVD[04]# 6 H_DSTBP#1 DSTBP[1]# DSTBP[3]# H_DSTBP#3 6

XDP_TDI R209 54.9/F_4

A XDP_TDI PU 150ohm /1.05V BSS301 A

XDP_TCK R213 54.9/F_4 XDP_TMS PU 39.2/1%? C338 R276 0_4

Date: Sunday, December 04, 2005 Sheet 3 of 46

U43D VCC_CORE VCC_CORE

Date: Monday, November 28, 2005 Sheet 4 of 46

A1A:Remove FANSIG capacitor

Quanta Computer Inc.

Date: Friday, December 02, 2005 Sheet 6 of 46

M_A_DQ33 SA_DQ32 SA_MA_1 M_A_A2 M_B_DQ47 SB_DQ46

M_A_DQ45 AN9 M_B_DQ59 AK3

Date: Friday, December 02, 2005 Sheet 7 of 46

T133 TP_MCH_NC5 BA39 AG37 DMI_RXN2

TP_MCH_NC8 NC7 CRT_BLUE# EXP_A_TXP_1 C_PEG_TXP2 C744 EV@.1U-10V_4PEG_TXP2

10.MCH_CFG_20 PCIE Backward interpoerability mode: Low= only

1500mA U44G U44F

.1U-10V_4 R41 VCC3G3 VTT_8 L14

.1U-10V_4 10U/X5R-6.3V_8 VCCA_3GPLL VTT_12

Date: Friday, December 02, 2005 Sheet 10 of 46

DDRII DUAL CHANNEL A,B.

DDRII A CHANNEL DDRII B CHANNEL

B A1A:Swap net A1A:Swap net B

M_B_BS#1 RP23 1 2 56_4P2R_S

Date: Monday, November 28, 2005 Sheet 12 of 46

PC4800 DDR2 SDRAM

PC4800 DDR2 SDRAM

D9 C533 CKL:C1/C2: 18pF -> CL:12.5pF

ACZ_BCLK R605 39_4

Date: Friday, December 02, 2005 Sheet 14 of 46

A1A:Change PCIE pin define to meet Acer spec

Direct Media Interface

ICH7 Boot BIOS select

U48B STRAP GNT5# GNT4#

Interrupt I/F OZ711MP1 AD25 REQ0# / GNT0# INTE#

T67 TP_ICH_RSVD3 AG4 AH8 TP_ICH_RSVD8 T155

R365 A1A:Reserve 100k

PCLK_SMB R399 2.2K_4 RI# R655 10K_4 CLKRUN# R301 8.2K_4

SMB_ALERT# R392 10K_4 SATA0GP R315 10K_4

R407 R410 SN74LVC1G04DCKR C584 C811

U47 To Lan pwr ok

Date: Tuesday, December 06, 2005 Sheet 16 of 46

U48E +5V +3V +1.05V

PCIE TEST PADS 8 PEG_RXP[15:0]

PEG_TXP1 AH30 P AJ25 V_GMCHEXP_RXP1 C333 EV@.1U-10V_4 PEG_RXP1

PEG_TXP9 Y31 AA27 V_GMCHEXP_RXP9 C325 EV@.1U-10V_4 PEG_RXP9

PEG_TXP10 W30 Y25 V_GMCHEXP_RXP10 C294 EV@.1U-10V_4 PEG_RXP10

PEG_TXP11 V32 W28 V_GMCHEXP_RXP11 C323 EV@.1U-10V_4 PEG_RXP11

PEG_TXP12 U31 V27 V_GMCHEXP_RXP12 C292 EV@.1U-10V_4 PEG_RXP12

PEG_TXP13 T30 U25 V_GMCHEXP_RXP13 C321 EV@.1U-10V_4 PEG_RXP13

PEG_TXP14 R32 T28 V_GMCHEXP_RXP14 C290 EV@.1U-10V_4 PEG_RXP14

PEG_TXP15 P31 R27 V_GMCHEXP_RXP15 C319 EV@.1U-10V_4 PEG_RXP15

22P_4 22P_4 020133MB004S557ZL_USB