Acer Emachines g520 g720 Quanta Zy6d Laptop SCH PDF

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vn/ 3 2 1
ZY6D SYSTEM BLOCK DIAGRAM

BOM MARK X'TAL
14.318MHZ
CPU
E@ EXT VGA
Penryn 479
D
268@ AUDIO 268 CLOCK GENERATOR uFCPGA P3,P4 Thermal Sensor P3 D
D@ DOCK ICS: ICS9LPRS365BGLFT

D2@ DDR2 SELGO: SLG8SP512K05
SP@ (EXT VGA OR DDR2) P2
ED2@ EXT VGA & DDR2
CB@ CARDBUS FSB 667/800/1067 Mhz
NSF@ Non ASF
DDRII
I@ INT VGA
888@ AUDIO 888
SO-DIMM 0 Dual Channel DDR2
D3@ DDR3 SO-DIMM 1 667/800 MHz NB
P16 CRT
ND@ NON DOCK
Cantiga Page:19
ID2@ INT VGA & DDR2
ED3@ EXT VGA & DDR3 PM965 LVDS
ID3@ INT VGA & DDR3
Page:19
C ASF@ ASF P5,P6,P7,P8,P9,P10,P11 C
NCB@ NON CARDBUS
X4 DMI interface
HDD (SATA)*2
LOW COST
1. MINI CARD 1 SLOT P25
2. NON DOCK
3. NON CARDBUS
4. NON ASF
5. NON HDMI SATA0 PCI-Express
SATA1
ODD (SATA)
SATA4 SB
P25 PCIE-4
WLAN
ICH9M
USB 2.0 PCIE-6
P23
B
P12,P13,P14,P15 B
X'TAL X'TAL
Azalia 32.768KHZ 25M
USB Port x 4
USB0~3 P25 BROADCOM
Int MIC 10/100/1G LAN
P27 LPC
CCD 5764M P21
USB7 P19
EC (WPC8769LDG)
Azalia Audio SWITCH CIRCUIT LAN
P32 Page:22
Audio Amplifier Controller X'TAL Page: 33
32.768K
P27 & 28 P27
ALC268 & 888
Transformer
P22
SPI ROM
P32
A RJ45 A
Touch Pad P22

Connector
P32
Quanta Computer Inc.
K/B COON. PROJECT : ZY6D

Speaker Phone Jack SPDIF Line in MIC Jack Fan Header
P28 P28 P28 P28 P28 http://hobi-elektronika.net
P32 P31 Size Document Number
Block Diagram
Rev
1A
Date: Thursday, August 28, 2008 Sheet 1 of 40

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Clock Generator
U25 CLK VDD power range 1.05V~3.3V
+3V R255 BKP1608HS181-T +3V_CLK 2 12 +1V05_CLK BKP1608HS181-T R219 +1.05V

VDD_PCI VDD_I/O
9 VDD_48 VDD_PLL3_I/O 20
16 26 C272 C213 C265 C214 C212 C261 C267
C216 C219 C215 C257 C262 C260 C263 VDD_PLL3 VDD_SRC_I/O_1
39 VDD_SRC VDD_SRC_I/O_2 36
55 45 10U/6.3V_8 .1U/10V_4 .1U/10V_4 .1U/10V_4 .1U/10V_4 .1U/10V_4 .1U/10V_4
.1U/10V_4 .1U/10V_4 .1U/10V_4 .1U/10V_4 .1U/10V_4 .1U/10V_4 *10U/6.3V_8 VDD_CPU VDD_SRC_I/O_3
D 61 VDD_REF VDD_CPU_I/O 49 D
CPU_STOP# 37 PM_STPCPU# <14>

PCI_STOP# 38 PM_STPPCI# <14>
56 Pin 56 : It acts as a
CKPWRGD/PD# CK_PWRGD <14>
level sensitive strobe
R254 Change from 33 to 475 CG_XOUT 59 54 CLK_CPU_BCLK_R RP13 1 2 0X2_4 to latch the FS pins
XTAL_OUT CPU_0 CLK_CPU_BCLK <3> and other multiplexed
CG_XIN 60 53 CLK_CPU_BCLK#_R 3 4
XTAL_IN CPU_0# CLK_CPU_BCLK# <3> inputs.
<14> SATACLKREQ# R246 475/F_4 SATACLKREQ#_R 1 51 CLK_MCH_BCLK_R RP12 1 2 0X2_4
PCI_0/CLKREQ_A# CPU_1_MCH CLK_MCH_BCLK <5>
R254 *475/F_4 NEW_CLKREQ#_R 3 50 CLK_MCH_BCLK#_R 3 4
<29> NEW_CLKREQ# PCI_1/CLKREQ_B# CPU_1_MCH# CLK_MCH_BCLK# <5>
R253 33_4 PCLK_MINI_R 4 47 CLK_PCIE_CARD_R RP11 1 2 *0X2_4
<23> PCLK_DEBUG PCI_2 SRC_8/CPU_ITP CLK_PCIE_CARD <28>
R252 33_4 PCLK_591_R 5 46 CLK_PCIE_CARD#_R 3 4
<32> PCLK_591 PCI_3 SRC_8#/CPU_ITP# CLK_PCIE_CARD# <28>
R264 *33_4 PCLK_PCM_R 6
<27> PCLK_PCM ^PCI_4/LCDCLK_SEL
PCLK_ICH R263 33_4 PCLK_ICH_R 7
<13> PCLK_ICH PCIF_5/ITP_EN
NC 48
CPU_BSEL0 R258 2.2K_4
R261 33_4 FSA 10
<14> CLKUSB_48 MCH_BSEL1 USB_48MHz/FS_A
57 FS_B/TEST_MODE
17 CLK_DREFSSCLK_R RP15 3 4 I@0X2
LCDCLK/27M CLK_DREFSSCLK <6>
CPU_BSEL2 R230 10K_4 18 CLK_DREFSSCLK#_R 1 2
LCDCLK#/27M_SS CLK_DREFSSCLK# <6>
R229 33_4 FSC 62
<14> 14M_ICH REF/FS_C/TEST_SEL
*30P/50V_4 C209
RP16 4 3 I@0X2 DREFCLK_R 13 21 CLK_PCIE_SATA_R RP18 3 4 0X2_4

<6> CLK_DREFCLK SRC_0/DOT_96 SRC_2 CLK_PCIE_SATA <12>
2 1 DREFCLK#_R 14 22 CLK_PCIE_SATA#_R 1 2
<6> CLK_DREFCLK# SRC_0#/DOT_96# SRC_2# CLK_PCIE_SATA# <12>
24 CLK_PCIE_LAN_R RP17 3 4 0X2_4
SRC_3/CLKREQ_C# CLK_PCIE_LAN <21>
CGCLK_SMB 64 25 CLK_PCIE_LAN#_R 1 2
C SCL SRC_3#/CLKREQ_D# CLK_PCIE_LAN# <21> C
CGDAT_SMB 63 27 CLK_PCIE_NEW_C_R RP20 3 4 *0X2_4
SDA SRC_4 CLK_PCIE_NEW_C <29>
28 CLK_PCIE_NEW_C#_R 1 2
SRC_4# CLK_PCIE_NEW_C# <29>
41 CLK_PCIE_ICH_R RP9 1 2 0X2_4
SRC_6 CLK_PCIE_ICH <13>
40 CLK_PCIE_ICH#_R 3 4
SRC_6# CLK_PCIE_ICH# <13>
44 PECLK_VGA_R RP10 1 2 *E@0X2 Rev:B Swap SRC9 & SRC4
SRC_7/CLKREQ_F# CLK_MXM <18>
8 43 PECLK_VGA#_R 3 4
VSS_PCI SRC_7#/CLKREQ_E# CLK_MXM# <18>
11 30 CLK_PCIE_MINI1_R RP19 3 4 *0X2_4
VSS_48 SRC_9 CLK_PCIE_MINI1 <23>
15 31 CLK_PCIE_MINI1#_R 1 2
VSS_I/O SRC_9# CLK_PCIE_MINI1# <23>
19 34 CLK_PCIE_3GPLL_R RP8 3 4 0X2_4
VSS_PLL3 SRC_10 CLK_PCIE_3GPLL <6>
23 35 CLK_PCIE_3GPLL#_R 1 2
VSS_SRC_1 SRC_10# CLK_PCIE_3GPLL# <6>
29 33 CLK_PCIE_TV_R RP14 1 2 0X2_4
VSS_SRC_2 SRC_11/CLKREQ_H# CLK_PCIE_TV <23>
42 32 CLK_PCIE_TV#_R 3 4
VSS_SRC_3 SRC_11#/CLKREQ_G# CLK_PCIE_TV# <23>
+3V 52 VSS_CPU
Clock Gen I2C
58 VSS_REF
Q26 R237 R243 SLG8SP512 Rev:C Change C 205 & C204 P/N to CH03306JB04 +3V
RHU002N06
2
10K_4 10K_4 SATACLKREQ#_R R475 10K_4

C205 33P/50V_4 CG_XIN
3 1 CGDAT_SMB NEW_CLKREQ#_R R531 *10K_4
<14,16,20,21,23,29> PDAT_SMB
QCI P/N Y8 PCLK_MINI_R R532 10K_4
14.318MHz
+3V
B SLG8SP512 AL8SP512K05 C204 33P/50V_4 CG_XOUT Rev:B for vendor request B
Q27
RHU002N06
2
ICS9LPRS365BGLFT ALPRS365K13
Strap table
3 1 CGCLK_SMB
<14,16,20,21,23,29> PCLK_SMB
PCLK_PCM_R R260 10K_4
CPU Clock select BSEL Frequency Select Table
FSC FSB FSA Frequency Pin 6 : For Pin 13/14 and 17/18 selection
0 = LCDCLK & DOT96 for internal graphic controller support
1 = 27M & 27M_SS &SRC_0 for external graphic controller support
Pin 10/57/62 : For Pin CPU frequency selection 0 0 0 266Mhz
0 0 1 133Mhz PCLK_ICH_R R259 10K_4

R262 0_4
<3> CPU_BSEL0 MCH_BSEL0 <6>
0 1 1 166Mhz
Pin 7 : For Pin 46/47 selection
1 = CPU_ITP
0 = SRC_8
A 0 1 0 200Mhz A
R226 0_4
1 1 0 400Mhz
CRB Rev0.7 : 110(CBA) 1 1 1 Reserved
PROJECT : ZY2 & ZY6
R231 0_4 1 0 1 100Mhz
Size Document Number Rev
http://hobi-elektronika.net CLOCK GENERATOR CK505 W/REGULATOR 1A

1 0 0 333Mhz
5 4 3 2 1

<5> H_A#[3..16]
U40A
H_A#3 J4 H1 U40B
A[3]# ADS# H_ADS# <5>
ADDR GROUP_0
H_A#4 L5 E2 H_D#[0..15] H_D#[32..47]
H_A#5 A[4]# BNR# H_BNR# <5> <5> H_D#[0..15] H_D#0 H_D#32 H_D#[32..47] <5>
L4 A[5]# BPRI# G5 H_BPRI# <5> E22 D[0]# D[32]# Y22
H_A#6 K5 H_D#1 F24 AB24 H_D#33
H_A#7 A[6]# H_D#2 D[1]# D[33]# H_D#34
M3 A[7]# DEFER# H5 H_DEFER# <5> E26 D[2]# D[34]# V24
DATA GRP 0
H_A#8 N2 F21 H_D#3 G22 V26 H_D#35
A[8]# DRDY# H_DRDY# <5> D[3]# D[35]#
DATA GRP 2
H_A#9 J1 E1 H_D#4 F23 V23 H_D#36
H_A#10 A[9]# DBSY# H_DBSY# <5> +1.05V H_D#5 D[4]# D[36]# H_D#37
N3 A[10]# G25 D[5]# D[37]# T22
H_A#11 P5 F1 H_D#6 E25 U25 H_D#38
A[11]# BR0# H_BREQ# <5> D[6]# D[38]#
H_A#12 P2 H_D#7 E23 U23 H_D#39
D A[12]# D[7]# D[39]# D
CONTROL
H_A#13 L2 D20 H_IERR# R162 56.2/F_4 H_D#8 K24 Y25 H_D#40
H_A#14 A[13]# IERR# H_D#9 D[8]# D[40]# H_D#41
P4 A[14]# INIT# B3 H_INIT# <12> G24 D[9]# D[41]# W22
H_A#15 P1 H_D#10 J24 Y23 H_D#42
A[15]# H_LOCK# <5> D[10]# D[42]#
H_A#16 R1 H4 T16 H_D#11 J23 W24 H_D#43
A[16]# LOCK# H_D#12 D[11]# D[43]# H_D#44
<5> H_ADSTB#0 M1 ADSTB[0]# H_CPURST# <5> H22 D[12]# D[44]# W25
C1 H_D#13 F26 AA23 H_D#45
<5> H_REQ#[0..4] RESET# H_RS#[0..2] <5> D[13]# D[45]#
H_REQ#0 K3 F3 H_RS#0 H_D#14 K22 AA24 H_D#46
H_REQ#1 REQ[0]# RS[0]# H_RS#1 H_D#15 D[14]# D[46]# H_D#47
H2 REQ[1]# RS[1]# F4 H23 D[15]# D[47]# AB25
H_REQ#2 K2 G3 H_RS#2 J26 Y26
REQ[2]# RS[2]# <5> H_DSTBN#0 DSTBN[0]# DSTBN[2]# H_DSTBN#2 <5>
H_REQ#3 J3 G2 H26 AA26
REQ[3]# TRDY# H_TRDY# <5> <5> H_DSTBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 <5>
H_REQ#4 L1 H25 U22
REQ[4]# <5> H_DINV#0 DINV[0]# DINV[2]# H_DINV#2 <5>
<5> H_A#[17..35] HIT# G6 H_HIT# <5>
H_A#17 Y2 E4 H_D#[16..31] H_D#[48..63]
A[17]# HITM# H_HITM# <5> <5> H_D#[16..31] H_D#[48..63] <5>
H_A#18 U5 H_D#16 N22 AE24 H_D#48
H_A#19 A[18]# XDP_BPM#0 H_D#17 D[16]# D[48]# H_D#49
R3 A[19]# BPM[0]# AD4 T10 K25 D[17]# D[49]# AD24
ADDR GROUP_1
H_A#20 W6 AD3 XDP_BPM#1 T15 H_D#18 P26 AA21 H_D#50
H_A#21 A[20]# BPM[1]# XDP_BPM#2 H_D#19 D[18]# D[50]# H_D#51
U4 A[21]# BPM[2]# AD1 T13 R23 D[19]# D[51]# AB22
H_A#22 Y5 AC4 XDP_BPM#3 T11 H_D#20 L23 AB21 H_D#52
A[22]# BPM[3]# D[20]# D[52]#
XDP/ITP SIGNALS
DATA GRP 1
H_A#23 U1 AC2 XDP_BPM#4 H_D#21 M24 AC26 H_D#53
T14
DATA GRP 3
H_A#24 A[23]# PRDY# XDP_BPM#5 H_D#22 D[21]# D[53]# H_D#54
R4 A[24]# PREQ# AC1 L22 D[22]# D[54]# AD20
H_A#25 T5 AC5 XDP_TCK H_D#23 M23 AE22 H_D#55
H_A#26 A[25]# TCK XDP_TDI Connect it to CPU DBR# is for ITP debug port H_D#24 D[23]# D[55]# H_D#56
T3 A[26]# TDI AA6 P25 D[24]# D[56]# AF23
H_A#27 W2 AB3 XDP_TDO or CPU interposer (like ICE) to reset the system H_D#25 P23 AC25 H_D#57
H_A#28 A[27]# TDO XDP_TMS H_D#26 D[25]# D[57]# H_D#58
W5 A[28]# TMS AB5 P22 D[26]# D[58]# AE21
H_A#29 Y4 AB6 XDP_TRST# H_D#27 T24 AD21 H_D#59
H_A#30 A[29]# TRST# XDP_DBRESET# R491 0_4 +1.05V H_D#28 D[27]# D[59]# H_D#60
U2 A[30]# DBR# C20 SYS_RST# <14> R24 D[28]# D[60]# AC22
H_A#31 V4 H_D#29 L25 AD23 H_D#61
H_A#32 A[31]# H_D#30 D[29]# D[61]# H_D#62
W3 A[32]# T25 D[30]# D[62]# AF22
H_A#33 AA4 THERMAL H_D#31 N25 AC23 H_D#63
H_A#34 A[33]# D[31]# D[63]#
C AB2 A[34]# <5> H_DSTBN#1 L26 DSTBN[1]# DSTBN[3]# AE25 H_DSTBN#3 <5>
C
H_A#35 AA3 D21 H_PROCHOT#_D R113 M26 AF24 Layout note:
A[35]# PROCHOT# <5> H_DSTBP#1 DSTBP[1]# DSTBP[3]# H_DSTBP#3 <5> comp0,2: Zo=27.4ohm, L<0.5"
V1 A24 H_THERMDA 1K/F_4 N24 AC20
<5> H_ADSTB#1 ADSTB[1]# THERMDA <5> H_DINV#1 DINV[1]# DINV[3]# H_DINV#3 <5> comp1,3: Zo=55ohm, L<0.5"
B25 H_THERMDC
THERMDC H_GTLREF COMP0 R500 27.4/F_6
<12> H_A20M# A6 A20M# AD26 GTLREF COMP[0] R26
ICH
A5 C7 PM_THRMTRIP# CPU_TEST1 C23 MISC U26 COMP1 R501 54.9/F_4

<12> H_FERR# FERR# THERMTRIP# T18 TEST1 COMP[1]
C4 T17 CPU_TEST2 D25 AA1 COMP2 R144 27.4/F_6 Layout note:
<12> H_IGNNE# IGNNE# Layout note: TEST2 COMP[2] DPRSTP# , Daisy Chain
CPU_TEST3 C24 Y1 COMP3 R147 54.9/F_4
H_GTLREF: Zo=55 ohm T19 TEST3 COMP[3] (SB>Power>NB>CPU)
R494 0_4 D5 CPU_TEST4 AF26
<12> H_STPCLK# STPCLK# L<0.5", 2/3*VCCP+-2% T72 TEST4
C6 H CLK R115 CPU_TEST5 AF1 E5
<12> H_INTR LINT0 T12 TEST5 DPRSTP# ICH_DPRSTP# <6,12,35>
B4 A22 2K/F_6 CPU_TEST6 A26 B5
<12> H_NMI LINT1 BCLK[0] CLK_CPU_BCLK <2> T70 TEST6 DPSLP# H_DPSLP# <12>
A3 A21 T71 CPU_TEST7 C3 D24
<12> H_SMI# SMI# BCLK[1] CLK_CPU_BCLK# <2> TEST7 DPWR# H_DPWR# <5>
<2> CPU_BSEL0 B22 BSEL[0] PWRGOOD D6 H_PWRGD <12>
M4 RSVD[01] <2> CPU_BSEL1 B23 BSEL[1] SLP# D7 H_CPUSLP# <5>
N5 RSVD[02] <2> CPU_BSEL2 C21 BSEL[2] PSI# AE6 PSI# <35>
T2 RSVD[03]
V3 Penryn
RSVD[04]
RESERVED
B2 RSVD[05]
D2 RSVD[06]
D22 RSVD[07]
D3 RSVD[08]
F6 RSVD[09]
Penryn
Thermal Trip CPU Thermal monitor XDP PU/PD +3V

B B
+1.05V
XDP_DBRESET# R492 *1K_4
Rev:B Add R540 +3V
3
XDP_DBRESET# and XDP_TDO +1.05V

reserve for XDP
2 Q41 R490
<6,14,32,35> DELAY_VR_PWRGOOD
+3V XDP_TDO R128 *54.9/F_4
FDV301N R466 R467 R540 200_6
Q39 XDP_TDI R149 54.9/F_4
2
RHU002N06 10K_4 10K_4 10K_4 LM86VCC

1
+1.05V XDP_TMS R131 54.9/F_4

<32> 2ND_MBCLK 3 1 C552
XDP_BPM#5 R121 54.9/F_4
.1U/10V_4
R495 XDP_TCK R127 54.9/F_4
+3V
2
56.2/F_4 U39 XDP_TRST# R124 54.9/F_4

Q40 Q38 H_THERMDA
2
PM_THRMTRIP# 1 3 MMBT3904 SYS_SHDN# <34,38>

RHU002N06 8 SCLK VCC 1
<32> 2ND_MBDATA 3 1 7 2 C551

PM_THRMTRIP# <6,12> SDA DXP
6 3 100P/X7R/50V_4
No use Thermal trip CPU side still PU 56ohm. ALERT# DXN
Use Thermal trip can share PU at SB side R465 *0_4 4 5 H_THERMDC
<14,18> THERM_ALERT# OVERT# GND
A Processor hot G780 A

ADDRESS: 98H
+1.05V
No use PROCHOT CPU side still PU 56ohm. +5V R493 *10K_4 CPUFAN#_ON
Use PROCHOT to optional receiver CPU side PU
68ohm and through isolat 2.2K ohm to receiver
R163 side
56_4
<31> CPUFAN#_ON Quanta Computer Inc.
PROJECT : ZY2 & ZY6
http://hobi-elektronika.net
H_PROCHOT#_D R164 *0_4 Size Document Number Rev
H_PROCHOT# <35>
1A
CPU Host Bus
5 4 3 2 1

U40D VCC_CORE VCC_CORE

A4 VSS[001] VSS[082] P6
A8 P21 U40C
VSS[002] VSS[083] VCC:38A
A11 VSS[003] VSS[084] P24 A7 VCC[001] VCC[068] AB20
A14 VSS[004] VSS[085] R2 A9 VCC[002] VCC[069] AB7
A16 VSS[005] VSS[086] R5 A10 VCC[003] VCC[070] AC7
A19 R22 C557 C156 C154 C155 C558 C568 C566 C157 A12 AC9
VSS[006] VSS[087] VCC[004] VCC[071]
A23 VSS[007] VSS[088] R25 A13 VCC[005] VCC[072] AC12
D *10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 *10U/6.3V_8 10U/6.3V_8 *10U/6.3V_8 *10U/6.3V_8 *10U/6.3V_8 D
AF2 VSS[008] VSS[089] T1 A15 VCC[006] VCC[073] AC13
B6 VSS[009] VSS[090] T4 A17 VCC[007] VCC[074] AC15
B13 VSS[012] VSS[093] U3 B7 VCC[010] VCC[077] AD7
B19 U21 B10 AD10 Layout Note:
VSS[014] VSS[095] VCC[012] VCC[079] Inside CPU center cavity in 2 rows
B24 VSS[016] VSS[097] V2 B14 VCC[014] VCC[081] AD14
C5 V5 C565 C573 C572 C571 C553 C556 C119 C559 B15 AD15
VSS[017] VSS[098] VCC[015] VCC[082]
C8 VSS[018] VSS[099] V22 B17 VCC[016] VCC[083] AD17
C11 V25 10U/6.3V_8 *10U/6.3V_8 10U/6.3V_8 *10U/6.3V_8 *10U/6.3V_8 10U/6.3V_8 *10U/6.3V_8 *10U/6.3V_8 B18 AD18
VSS[019] VSS[100] VCC[017] VCC[084] C129 C135 C147
C14 VSS[020] VSS[101] W1 B20 VCC[018] VCC[085] AE9
C16 VSS[021] VSS[102] W4 C9 VCC[019] VCC[086] AE10
C19 W23 C10 AE12 .1U/16V_6 .1U/16V_6 .1U/16V_6
VSS[022] VSS[103] VCC[020] VCC[087]
C2 VSS[023] VSS[104] W26 C12 VCC[021] VCC[088] AE13
C22 VSS[024] VSS[105] Y3 C13 VCC[022] VCC[089] AE15
C25 VSS[025] VSS[106] Y6 C15 VCC[023] VCC[090] AE17
D1 VSS[026] VSS[107] Y21 C17 VCC[024] VCC[091] AE18
D4 VSS[027] VSS[108] Y24 C18 VCC[025] VCC[092] AE20
D8 AA2 D9 AF9 C128 C136 C148
VSS[028] VSS[109] C140 C141 C139 C560 C118 VCC[026] VCC[093]
D11 VSS[029] VSS[110] AA5 D10 VCC[027] VCC[094] AF10
D13 AA8 D12 AF12 .1U/16V_6 .1U/16V_6 .1U/16V_6
VSS[030] VSS[111] *10U/6.3V_8 *10U/6.3V_8 *10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 VCC[028] VCC[095]
C D16 VSS[031] VSS[112] AA11 D14 VCC[029] VCC[096] AF14 C
E3 AA22 E7 AF20 VCCP:130mA +1.05V
VSS[035] VSS[116] Layout Note: VCC[033] VCC[100]
E6 VSS[036] VSS[117] AA25 E9 VCC[034]
E8 AB1 Place these parts E10 G21
VSS[037] VSS[118] reference to Intel demo VCC[035] VCCP[01]
E11 VSS[038] VSS[119] AB4 E12 VCC[036] VCCP[02] V6
board.
E14 VSS[039] VSS[120] AB8 E13 VCC[037] VCCP[03] J6
E16 AB11 C142 C120 C121 E15 K6 + C575
VSS[040] VSS[121] VCC[038] VCCP[04]
E19 VSS[041] VSS[122] AB13 E17 VCC[039] VCCP[05] M6
E21 AB16 *10U/6.3V_8 *10U/6.3V_8 10U/6.3V_8 E18 J21 330U/2V_7
VSS[042] VSS[123] VCC[040] VCCP[06]
E24 VSS[043] VSS[124] AB19 E20 VCC[041] VCCP[07] K21
F5 VSS[044] VSS[125] AB23 F7 VCC[042] VCCP[08] M21
F8 VSS[045] VSS[126] AB26 F9 VCC[043] VCCP[09] N21
F11 VSS[046] VSS[127] AC3 F10 VCC[044] VCCP[10] N6
F13 AC6 F12 R21 Layout Note:
VSS[047] VSS[128] VCC[045] VCCP[11] VCCA CAP closr to Pin
F16 VSS[048] VSS[129] AC8 F14 VCC[046] VCCP[12] R6
F19 AC11 F15 T21 VCCA : 2.5A(Supply after VCC Stable)
VSS[049] VSS[130] VCC[047] VCCP[13] 4.5A(Supply before VCC Stable)
F2 VSS[050] VSS[131] AC14 F17 VCC[048] VCCP[14] T6
F22 AC16 C158 C153 C152 C151 C567 C564 F18 V21
VSS[051] VSS[132] VCC[049] VCCP[15] +1.5V
F25 VSS[052] VSS[133] AC19 F20 VCC[050] VCCP[16] W21
G4 AC21 *10U/6.3V_8 *10U/6.3V_8 10U/6.3V_8 *10U/6.3V_8 10U/6.3V_8 *10U/6.3V_8 AA7
VSS[053] VSS[134] VCC[051]
G1 VSS[054] VSS[135] AC24 AA9 VCC[052] VCCA[01] B26
B G23 VSS[055] VSS[136] AD2 AA10 VCC[053] VCCA[02] C26 B
G26 VSS[056] VSS[137] AD5 AA12 VCC[054]
H3 AD8 AA13 AD6 C562 C561
VSS[057] VSS[138] VCC[055] VID[0] H_VID0 <35>
H6 VSS[058] VSS[139] AD11 AA15 VCC[056] VID[1] AF5 H_VID1 <35>
H21 AD13 AA17 AE5 .01U/16V_4 10U/6.3V_8
H24 VSS[060] VSS[141] AD16 AA18 VCC[058] VID[3] AF4 H_VID3 <35>
J2 VSS[061] VSS[142] AD19 AA20 VCC[059] VID[4] AE3 H_VID4 <35>
J5 AD22 C563 C574 C570 C569 C554 C555 AB9 AF3
J22 VSS[063] VSS[144] AD25 AC10 VCC[061] VID[6] AE2 H_VID6 <35>
J25 AE1 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 *10U/6.3V_8 10U/6.3V_8 *10U/6.3V_8 AB10 R84 100/F_6 VCC_CORE
VSS[064] VSS[145] VCC[062]
K1 VSS[065] VSS[146] AE4 AB12 VCC[063]
K4 VSS[066] VSS[147] AE8 AB14 VCC[064] VCCSENSE AF7 VCCSENSE <35>
K23 VSS[067] VSS[148] AE11 AB15 VCC[065]
K26 VSS[068] VSS[149] AE14 AB17 VCC[066]
L3 VSS[069] VSS[150] AE16 AB18 VCC[067] VSSSENSE AE7 VSSSENSE <35>
L6 VSS[070] VSS[151] AE19
L21 AE23 10/12 :Modify BOM Penryn R77
VSS[071] VSS[152] Layout Note:
L24 VSS[072] VSS[153] AE26 .
M2 A2 + C80 + C576 + C81 + C577 100/F_6 Z0=27.4,PU/PD L<1"
VSS[073] VSS[154] VCCA : 2.5A(Supply after VCC Stable)
M5 VSS[074] VSS[155] AF6
M22 AF8 *330U/2V_7343 330U/2V_7343 330U/2V_7343 *330U/2V_7343 4.5A(Supply before VCC Stable)
VSS[075] VSS[156]
M25 VSS[076] VSS[157] AF11
N1 VSS[077] VSS[158] AF13
N4 VSS[078] VSS[159] AF16
A N23 AF19 A
VSS[079] VSS[160] Montevina platform : Early Reference Board Schematics Feb 2007. Rev 1.0
N26 VSS[080] VSS[161] AF21
P3 A25 stuff 22U*34, NC 22U*2
VSS[081] VSS[162] stuff 330U*2, NC330U*2
AF25
Penryn
VSS[163] Quanta Computer Inc.
. PROJECT : ZY2 & ZY6
1A
CPU Power
5 4 3 2 1

H_A#[3..35] <3>
U38A
<3> H_D#[0..63]
A14 H_A#3
H_D#0 H_A#_3 H_A#4
F2 H_D#_0 H_A#_4 C15
H_D#1 G8 F16 H_A#5
H_D#2 H_D#_1 H_A#_5 H_A#6
F8 H_D#_2 H_A#_6 H13
H_D#3 E6 C18 H_A#7
H_D#4 H_D#_3 H_A#_7 H_A#8
G2 H_D#_4 H_A#_8 M16
H_D#5 H6 J13 H_A#9
D H_D#6 H_D#_5 H_A#_9 H_A#10 D
H2 H_D#_6 H_A#_10 P16
H_D#7 F6 R16 H_A#11
H_D#8 H_D#_7 H_A#_11 H_A#12
QCI P/N D4 H_D#_8 H_A#_12 N17
H_D#9 H3 M13 H_A#13
H_D#10 H_D#_9 H_A#_13 H_A#14
M9 H_D#_10 H_A#_14 E17
Intel Cantiga (G)M AJSLB940T04 H_D#11 M11 P17 H_A#15
H_D#12 H_D#_11 H_A#_15 H_A#16
J1 H_D#_12 H_A#_16 F17
H_D#13 J2 G20 H_A#17
H_D#14 H_D#_13 H_A#_17 H_A#18
Intel Cantiga (P)M AJSLB970T06 N12 H_D#_14 H_A#_18 B19
H_D#15 J6 J16 H_A#19
H_D#16 H_D#_15 H_A#_19 H_A#20
P2 H_D#_16 H_A#_20 E20
H_D#17 L2 H16 H_A#21
H_D#18 H_D#_17 H_A#_21 H_A#22
R2 H_D#_18 H_A#_22 J20
H_D#19 N9 L17 H_A#23
H_D#20 H_D#_19 H_A#_23 H_A#24
L6 H_D#_20 H_A#_24 A17
H_D#21 M5 B17 H_A#25
H_D#22 H_D#_21 H_A#_25 H_A#26
J3 H_D#_22 H_A#_26 L16
H_D#23 N2 C21 H_A#27
H_D#24 H_D#_23 H_A#_27 H_A#28
R1 H_D#_24 H_A#_28 J17
H_D#25 N5 H20 H_A#29
H_D#26 H_D#_25 H_A#_29 H_A#30
N6 H_D#_26 H_A#_30 B18
+1.05V H_D#27 P13 K17 H_A#31
H_D#28 H_D#_27 H_A#_31 H_A#32
N8 H_D#_28 H_A#_32 B20
H_D#29 L7 F21 H_A#33
C H_D#30 H_D#_29 H_A#_33 H_A#34 C
0.3125*VCCP N10 H_D#_30 H_A#_34 K21
WIDE(10):SPACING(20) , H_D#31 M3 L20 H_A#35
R177 H_D#32 H_D#_31 H_A#_35
Y3
L<0.5" H_D#33 AD14
H_D#_32
H12
H_D#_33 H_ADS# H_ADS# <3>
221/F_4 H_D#34 Y6 B16
H_D#_34 H_ADSTB#_0 H_ADSTB#0 <3>
H_D#35 Y10 G17
H_D#_35 H_ADSTB#_1 H_ADSTB#1 <3>
H_SWING H_D#36 Y12 A9
H_D#_36 H_BNR# H_BNR# <3>
H_D#37 Y14 F11
H_D#_37 H_BPRI# H_BPRI# <3>
Capacitor close H_D#38 Y7 G12
HOST
H_D#_38 H_BREQ# H_BREQ# <3>
R175 C178 to the pin H_D#39 W2 E9
H_D#_39 H_DEFER# H_DEFER# <3>
H_D#40 AA8 B10
H_D#_40 H_DBSY# H_DBSY# <3>
100/F_4 0.1U/10V_4 H_D#41 Y9 AH7
H_D#_41 HPLL_CLK CLK_MCH_BCLK <2>
H_D#42 AA13 AH6
H_D#_42 HPLL_CLK# CLK_MCH_BCLK# <2>
H_D#43 AA9 J11
H_D#_43 H_DPWR# H_DPWR# <3>
H_D#44 AA11 F9
H_D#_44 H_DRDY# H_DRDY# <3>
H_D#45 AD11 H9
H_D#_45 H_HIT# H_HIT# <3>
H_D#46 AD10 E12
H_D#_46 H_HITM# H_HITM# <3>
H_D#47 AD13 H11
H_D#_47 H_LOCK# H_LOCK# <3>
H_D#48 AE12 C9
H_D#_48 H_TRDY# H_TRDY# <3>
H_D#49 AE9
H_D#50 H_D#_49
AA2 H_D#_50
H_D#51 AD8
H_RCOMP H_D#52 H_D#_51
AA3 H_D#_52 H_DINV#[3..0] <3>
H_D#53 AD3 J8 H_DINV#0
B H_D#54 H_D#_53 H_DINV#_0 H_DINV#1 B
AD7 H_D#_54 H_DINV#_1 L3
H_D#55 AE14 Y13 H_DINV#2
R464 H_D#56 H_D#_55 H_DINV#_2 H_DINV#3
WIDE(10):SPACING(20) , AF3 H_D#_56 H_DINV#_3 Y1
L<0.5" H_D#57 AC1 H_D#_57 H_DSTBN#[3..0] <3>
24.9/F_4 H_D#58 AE3 L10 H_DSTBN#0
H_D#59 H_D#_58 H_DSTBN#_0 H_DSTBN#1
AC3 H_D#_59 H_DSTBN#_1 M7
H_D#60 AE11 AA5 H_DSTBN#2
H_D#61 H_D#_60 H_DSTBN#_2 H_DSTBN#3
AE8 H_D#_61 H_DSTBN#_3 AE6
H_D#62 AG2 H_D#_62 H_DSTBP#[3..0] <3>
H_D#63 AD6 L9 H_DSTBP#0
H_D#_63 H_DSTBP#_0 H_DSTBP#1
H_DSTBP#_1 M8
AA6 H_DSTBP#2
H_SWING H_DSTBP#_2 H_DSTBP#3
C5 H_SWING H_DSTBP#_3 AE5
H_RCOMP E3
+1.05V H_RCOMP H_REQ#[0..4] <3>
B15 H_REQ#0
H_REQ#_0 H_REQ#1
H_REQ#_1 K13
F13 H_REQ#2
H_REQ#_2 H_REQ#3
H_REQ#_3 B13
C12 B14 H_REQ#4
<3> H_CPURST# H_CPURST# H_REQ#_4
R484 E11
<3> H_CPUSLP# H_CPUSLP# H_RS#[0..2] <3>
2/3*VCCP B6 H_RS#0
1K/F_4 H_RS#_0 H_RS#1
WIDE(10):SPACING(20), H_RS#_1 F12
C8 H_RS#2
L<0.5" H_AVREF H_RS#_2
A11 H_AVREF
A A
B11 H_DVREF
R482 SP@CANTIGA_1p2
2K/F_4 Quanta Computer Inc.

PROJECT : ZY2 & ZY6
http://hobi-elektronika.net GMCH HOST 1A

5 4 3 2 1

Strap table
Pin Name Strap description Configuration

000= FSB 1066MHz
CFG[2:0] FSB Frequency Select 010 = FSB 800MHz
011 = FSB 667MHz SM_VREF.Default use voltage divider
CFG[4:3] Reserved for poor layout cause +SMDDR_VREF not
meet spec.And Intel circuit PU/PD is
0 = DMI X2 U38B 1K,But Check list PU/PD is 10K.
CFG5 DMI X2 Select 1 = DMI X4(Default)
M36
0 = iTPM Host Interface is enabled RSVD1 M_CLK0
N36 AP24 M_CLK0 <16,17>
RSVD2 SA_CK_0
DDR CLK/ CONTROL/COMPENSATION

CFG6 iTPM Host Interface 1 = iTPM Host Interface is disabled(Default) R33 AT21 M_CLK1
RSVD3 SA_CK_1 M_CLK1 <16,17>
T33 AV24 M_CLK2
D RSVD4 SB_CK_0 M_CLK2 <16,17> D
0 = AMT Firmware will use TLS cipher suite AH9 AU20 M_CLK3
RSVD5 SB_CK_1 M_CLK3 <16,17>
with no confidentiality AH10
CFG7 ME TLS Confidentiality RSVD6 M_CLK#0
1 = AMT Firmware will use TLS cipher suite AH12 AR24 M_CLK#0 <16,17>
RSVD7 SA_CK#_0 M_CLK#1 +VDR_SUS
AH13 AR21 M_CLK#1 <16,17>
with confidentiality(Default) RSVD8 SA_CK#_1 M_CLK#2
K12 AU24 M_CLK#2 <16,17>
RSVD9 SB_CK#_0 M_CLK#3 M_RCOMP R458 80.6/F_4
AV20 M_CLK#3 <16,17>
CFG8 Reserved SB_CK#_1 M_RCOMP# R457 80.6/F_4
BC28 M_CKE0 <16,17>
0 = Reverse Lanes SA_CKE_0
AY28 M_CKE1 <16,17>
CFG9 PCIE Graphics Lane Reversal 1 = Normal operation(Default) SA_CKE_1
T24 AY36 M_CKE2 <16,17>
RSVD14 SB_CKE_0
BB36 M_CKE3 <16,17>
SB_CKE_1
RSVD
0 = Enabled B31
CFG10 PCIE Loopback enable RSVD15 +VDR_SUS
1 = Disabled (Default) SA_CS#_0
BA17 M_CS#0 <16,17>
M1 AY16 M_CS#1 <16,17>
CFG11 Reserved RSVD17 SA_CS#_1 SM_VREF R250 10K/F_4
AV16 M_CS#2 <16,17>
SB_CS#_0 R249 10K/F_4
AR13 M_CS#3 <16,17>
0 = ALLZ mode enable SB_CS#_1
AY21
CFG12 ALLZ RSVD20
1 = disable(Default) BD17 M_ODT0 <16,17>
SA_ODT_0
AY17 M_ODT1 <16,17>
0 = XOR mode enable SA_ODT_1
B2 BF15 M_ODT2 <16,17>
CFG13 XOR RSVD21 SB_ODT_0 SM_PWROK R251 *D3@10K/F_4
1 = disable(Default) BG23 AY13 M_ODT3 <16,17> HWPG_VDR <32,37>
RSVD22 SB_ODT_1 R248 10K/F_4
BF23
RSVD23 M_RCOMP
BH18 BG22
CFG[15:14] Reserved RSVD24 SM_RCOMP M_RCOMP#
BF18 BH21
RSVD25 SM_RCOMP# SM_VREF=0.5*VCC_SM
0 = Dynamic ODT disable BF28 SM_RCOMP_VOH
CFG16 FSB Dynamic ODT SM_RCOMP_VOH SM_RCOMP_VOL SM_PWROK only for
1 = Dynamic ODT Enable(Default) BH28
SM_RCOMP_VOL DDR3.DDR2 PD only
CFG[18:17] Reserved AV42 SM_VREF
SM_VREF SM_PWROK SM_DRAMRST# only
AR36
0 = Normal (Default) SM_PWROK SM_REXT R256 499/F_4 for DDR3.DDR2 NC. INTEL FAE Suggest PD for Ext graphics
BF17
CFG19 DMI Lane Reversal SM_REXT R257 *D3@0_4
1 = Lanes Reversed BC36 DDR3_DRAMRST# <17>
SM_DRAMRST# CLK_DREFCLK# R174 *E@0_4
0 = Only Digital Display port (SDVO/DP/iHDMI) B38 CLK_DREFCLK CLK_DREFCLK R182 *E@0_4
DPLL_REF_CLK CLK_DREFCLK <2>
Digital Display Port or PCIE is operational (Default) A38 CLK_DREFCLK# CLK_DREFSSCLK# R193 *E@0_4
DPLL_REF_CLK# CLK_DREFCLK# <2>
(SDVO/DP/iHDMI) 1 = Digital Display port (SDVO/DP/iHDMI) and E41 CLK_DREFSSCLK CLK_DREFSSCLK R183 *E@0_4
C DPLL_REF_SSCLK CLK_DREFSSCLK <2> C
CFG20 Concurrent with PCIE F41 CLK_DREFSSCLK#
PCIE are operating simultaneously via PEG DPLL_REF_SSCLK# CLK_DREFSSCLK# <2>
port
ME JTAG
F43 CLK_PCIE_3GPLL
CLK
PEG_CLK CLK_PCIE_3GPLL <2>
JTAG_TCK AL34 E43 CLK_PCIE_3GPLL#
T30 ME_JTAG_TCK PEG_CLK# CLK_PCIE_3GPLL# <2>
0 = No SDVO/HDMI Device Present(Default)
SDVO_CTRLDATA SDVO Present 1 = SDVO/HDMI Device present JTAG_TDI AK34
T28 ME_JTAG_TDI DMI_TXN[3:0] <13>
0 = Digital display(HDMI/DP) device JTAG_TDO AN35 AE41 DMI_TXN0 +VDR_SUS
T31 ME_JTAG_TDO DMI_RXN_0
DDPC_CTRLDATA Digital Display Present absent(Default) AE37 DMI_TXN1
JTAG_TMS DMI_RXN_1 DMI_TXN2 SM_RCOMP_VOH 1K/F_4 R454
1 = Digital display(HDMI/DP) device present T29 AM35 AE47
ME_JTAG_TMS DMI_RXN_2 DMI_TXN3
AH39 DMI_TXP[3:0] <13>
DMI_RXN_3 C516 C517
AE40 DMI_TXP0 R453
DMI_RXP_0 DMI_TXP1 2.2U/6V_6 0.01U/16V_4
<2> MCH_BSEL0 T25 AE38
CFG_0 DMI_RXP_1 DMI_TXP2 3.01K/F_4
<2> MCH_BSEL1 R25 AE48
CFG_1 DMI_RXP_2 DMI_TXP3
<2> MCH_BSEL2 P25 AH40 DMI_RXN[3:0] <13>
MCH_CFG_3 CFG_2 DMI_RXP_3
T25 P20
MCH_CFG_4 CFG_3 DMI_RXN0 SM_RCOMP_VOL
T27 P24 AE35
MCH_CFG_5 CFG_4 DMI_TXN_0 DMI_RXN1
C25 AE43
MCH_CFG_6 CFG_5 DMI_TXN_1 DMI_RXN2
<13> MCH_CFG_6 N24 AE46
MCH_CFG_7 CFG_6 DMI_TXN_2 DMI_RXN3 C514 C515 R452
M24 AH42 DMI_RXP[3:0] <13>
MCH_CFG_8 CFG_7 DMI_TXN_3
T21 E21
CFG_8
CFG
MCH_CFG_9 DMI_RXP0 2.2U/6V_6 0.01U/16V_4 1K/F_4
DMI
C23 AD35
CFG_9 DMI_TXP_0
Strap pin
MCH_CFG_10 C24 AE44 DMI_RXP1
MCH_CFG_11 CFG_10 DMI_TXP_1 DMI_RXP2
T24 N21 AF46
MCH_CFG_12 CFG_11 DMI_TXP_2 DMI_RXP3
P21 AH43
MCH_CFG_13 CFG_12 DMI_TXP_3
T21
MCH_CFG_14 CFG_13
T26 R20
+3V MCH_CFG_15 CFG_14
T20 M20
MCH_CFG_16 CFG_15
L21
R477 *4.02K/F_4 MCH_CFG_19 MCH_CFG_17 CFG_16
T22 H21
R478 *4.02K/F_4 MCH_CFG_20 MCH_CFG_18 CFG_17
P29
GRAPHICS VID
T23 CFG_18
MCH_CFG_19 R28
MCH_CFG_20 CFG_19
T28 B33
CFG_20 GFX_VID_0
B32
R207 *TPM@2.21K/F_4 GFX_VID_1
B MCH_CFG_6_R <13> G33 B
R479 *4.02K/F_4 MCH_CFG_5 GFX_VID_2
F33
R196 *4.02K/F_4 MCH_CFG_7 R213 0_4 PM_SYNC#_R GFX_VID_3
<14> PM_SYNC# R29 E33
R487 *4.02K/F_4 MCH_CFG_9 R483 0_4 ICH_DPRSTP#_R PM_SYNC# GFX_VID_4
<3,12,35> ICH_DPRSTP# B7
R488 *4.02K/F_4 MCH_CFG_10 R470 0_4 PM_EXTTS#0_1_EC_R PM_DPRSTP#
<16,17> PM_EXTTS#0 N33
R222 *4.02K/F_4 MCH_CFG_12 R212 0_4 TS#DIMM0_1_R PM_EXT_TS#_0
<16,17> PM_EXTTS#1 P32
PM_EXT_TS#_1
PM
R216 *4.02K/F_4 MCH_CFG_13 <3,14,32,35> DELAY_VR_PWRGOOD AT40 C34
R200 *4.02K/F_4 MCH_CFG_16 R247 100/F_4 RST_IN#_MCH PWROK GFX_VR_EN +1.05V
<13> PLT_RST# AT11
R221 *0_4 THRMTRIP#_R RSTIN#
<3,12> PM_THRMTRIP# T20
R218 0_4 DPRSLPVR_R THERMTRIP#
<14,35> PM_DPRSLPVR R32
DPRSLPVR
AH37 R224
CL_CLK CL_CLK0 <14>
AH36 CL_DATA0 <14>
CL_DATA 1K/F_4
REV: E Modify TPM (R207) BG48
NC_1 CL_PWROK
AN36 MPWROK <14,32>
NB Thermal trip pin BF48 AJ35 Check list note : CL_REF=0.35V
NC_2 CL_RST# CL_RST#0 <14>
ME
No use Thermal trip NB side can BD48 AH34 MCH_CLVREF_R
NC.(NB has ODT) NC_3 CL_VREF
BC48
NC_4
BH47
NC_5 C207 R233
BG47
PM_DPRSTP# NC_6 DDPC_CTRLCLK
BE47 N28
The Daisy chain topology should NC_7 DDPC_CTRLCLK DDPC_DDCDATA 0.1U/10V_4 511/F_4
BH46 M28
be routed from ICH9M to IMVP , NC_8 DDPC_CTRLDATA
BF46 G36 SDVO_CTRLCLK <20>
NC_9 SDVO_CTRLCLK
NC
then to (G)MCH and CPU, in that BG45 E36

+3V order. NC_10 SDVO_CTRLDATA SDVO_CTRLDATA <20>
BH44 K36 CLK_MCH_OE#
NC_11 CLKREQ#
BH43 H36 MCH_ICH_SYNC# <14>
R184 *I@2.21K/F_4 SDVO_CTRLDATA NC_12 ICH_SYNC# +1.05V
BH6
MISC
R188 *I@2.21K/F_4 SDVO_CTRLCLK NC_13

BH5
R206 *2.21K/F_4 DDPC_DDCDATA NC_14 TSATN# R180 56_4 DDPC_CTRL for HDMI port C
BG4 B12
R217 *2.21K/F_4 DDPC_CTRLCLK NC_15 TSATN# SDVO_CTRL for HDMI port B
BH3
R481 10K_4 CLK_MCH_OE# NC_16
BF3
R485 10K_4 PM_EXTTS#0 NC_17
BH2
R209 10K_4 PM_EXTTS#1 NC_18 HDA_BIT_CLK_HDMI <Checklist ver0.8>
BG2 B28 HDA_BIT_CLK_HDMI <12>
NC_19 HDA_BCLK HDA_RST#_HDMI If HDMI not support If TSATN# is not used, then it must be terminated
BE2 B30 HDA_RST#_HDMI <12>
NC_20 HDA_RST# HDA_SDIN_HDMI HDA --> NC with a 56- pull-up resistor to VCCP.
BG1 B29 HDA_SDIN_HDMI <12>
NC_21 HDA_SDI HDA_SDOUT_HDMI VCC_HDA-->GND
BF1 C29 HDA_SDOUT_HDMI <12>
NC_22 HDA_SDO HDA_SYNC_HDMI Differential signal-->NC <Pin out check issue>
BD1 A28
HDA
A NC_23 HDA_SYNC HDA_SYNC_HDMI <12> Cantiga EDS 0.7 change Ball B12 to TSATN# from TSATN A
BC1
NC_24
F1
NC_25
Impact ICH9M VCCHDA and VCCSUSHDA supply 1.5V/3.3V
SP@CANTIGA_1p2
NOTE:
If (G)MCH's HD Audio signals are connected to ICH9M
for iHDMI, VCCHDA and VCCSUSHDA on ICH9M should be
only on 1.5V. These power pins on ICH9M can be
supplied with 3.3V if and only if (G)MCH's HDA is not
connected to ICH9M. Consequently, only 1.5V
audio/modem codecs can be used on the platform.
PROJECT : ZY2 & ZY6
http://hobi-elektronika.net Size Document Number
GMCH DMI
Rev
1A

5 4 3 2 1

Rev: B Change P/N

IV&EV Dis/Enable setting U38C
L<0.5" , If PCIE not support
If LVDS no use,all signal can NC still connect to +VCC_PEG IV&EV Dis/Enable setting
+1.05V
L32 <5/31>Montevina_Schematics_Checklist_Rev0_8
<19> L_BKLT_CTRL L_BKLT_CTRL a)For TVOUT Disabled, TV_DCONSEL[1:0] Connect to GND. But
G32 T37 EXP_A_COMPX R215 49.9/F_4
<19> INT_LVDS_BLON L_BKLT_EN PEG_COMPI design guide Rev0.7 show NC.What is correct.
R203 I@10K_4 L_CTRL_CLK M32 T36
L_CTRL_CLK PEG_COMPO b)For CRT DAC Disable, CRT_DDC_CLK, CRT_DDC_DATA .
D +3V CRT_HSYNC, CRT_VSYNCThese signals should be connected to D
R469 I@10K_4 L_CTRL_DATA M33 GND. But design guide Rev0.7 show NC, Intel suggest follow
L_CTRL_DATA PEG_RXN[15:0] <18>
K33 H44 PEG_RXN0 Design guide.
<19> INT_LVDS_EDIDCLK L_DDC_CLK PEG_RX#_0
J33 J46 PEG_RXN1
<19> INT_LVDS_EDIDDATA L_DDC_DATA PEG_RX#_1
L44 PEG_RXN2 <check list> <check list>
PEG_RX#_2 PEG_RXN3
PEG_RX#_3 L40 For EV@ For IV@
M29 N41 PEG_RXN4 Can support reversal routing.If CFG9=1, PCI
<19> INT_LVDS_DIGON L_VDD_EN PEG_RX#_4 Express is normal operation. If CFG9=0, Connect to GND Connect to 150ohm
R178 I@2.37K/F_4 C44 P48 PEG_RXN5
10/15: R178 Change to I@ LVDS_IBG PEG_RX#_5 PEG_RXN6 then PEG_TXP0 becomes PEG_TXP15, PEG_TXP1 CRT R/G/B CRT R/G/B
B43 LVDS_VBG PEG_RX#_6 N44
E37 T43 PEG_RXN7 becomes PEG_TXP14, PEG_TXP2 becomes
LVDS_VREFH PEG_RX#_7 PEG_TXP13, etc. similarly for PEG_RXP[15:0] HSYNC/VSYNC Connect to 1.02Kohm
E38 U43 PEG_RXN8
LVDS_VREFL PEG_RX#_8 and PEG_RXN[15:0] CRTIREF CRTIREF
LVDS
<18> INT_TXLCLKOUT- INT_TXLCLKOUT- C41 Y43 PEG_RXN9
INT_TXLCLKOUT+ LVDSA_CLK# PEG_RX#_9 PEG_RXN10
<18> INT_TXLCLKOUT+ C40 LVDSA_CLK PEG_RX#_10 Y48
INT_TXUCLKOUT- B37 Y36 PEG_RXN11
<18> INT_TXUCLKOUT- LVDSB_CLK# PEG_RX#_11
INT_TXUCLKOUT+ A37 AA43 PEG_RXN12 R181 SP@0 & 1.02K/F_4 CRTIREF
<18> INT_TXUCLKOUT+ LVDSB_CLK PEG_RX#_12
AD37 PEG_RXN13
INT_TXLOUT0- PEG_RX#_13 PEG_RXN14 11/28: Change R181 1.02K ohm P/N
<18> INT_TXLOUT0- H47 LVDSA_DATA#_0 PEG_RX#_14 AC47
INT_TXLOUT1- E46 AD39 PEG_RXN15
<18> INT_TXLOUT1- LVDSA_DATA#_1 PEG_RX#_15
INT_TXLOUT2- G40
<18> INT_TXLOUT2- LVDSA_DATA#_2 PEG_RXP[15:0] <18>
A40 H43 PEG_RXP0 R472 *E@0_4 HSYNC_G
LVDSA_DATA#_3 PEG_RX_0
GRAPHICS
J44 PEG_RXP1
INT_TXLOUT0+ PEG_RX_1 PEG_RXP2 R468 *E@0_4 VSYNC_G
<18> INT_TXLOUT0+ H48 LVDSA_DATA_0 PEG_RX_2 L43
<18> INT_TXLOUT1+ INT_TXLOUT1+ D45 L41 PEG_RXP3
INT_TXLOUT2+ LVDSA_DATA_1 PEG_RX_3 PEG_RXP4
<18> INT_TXLOUT2+ F40 LVDSA_DATA_2 PEG_RX_4 N40
B40 P47 PEG_RXP5 R186 SP@150_4 INT_CRT_BLU
C LVDSA_DATA_3 PEG_RX_5 PEG_RXP6 C
PEG_RX_6 N43
INT_TXUOUT0- A41 T42 PEG_RXP7 R190 SP@150_4 INT_CRT_GRN
<18> INT_TXUOUT0- LVDSB_DATA#_0 PEG_RX_7
INT_TXUOUT1- H38 U42 PEG_RXP8
INT_TXUOUT2- G37 Y42 PEG_RXP9 R197 SP@150_4 INT_CRT_RED
J37 W47 PEG_RXP10
LVDSB_DATA#_3 PEG_RX_10 PEG_RXP11 10/15: Change to SP@
PEG_RX_11 Y37
INT_TXUOUT0+ B42 AA42 PEG_RXP12
<18> INT_TXUOUT0+ LVDSB_DATA_0 PEG_RX_12
INT_TXUOUT1+ G38 AD36 PEG_RXP13
<18> INT_TXUOUT1+ LVDSB_DATA_1 PEG_RX_13
INT_TXUOUT2+ F37 AC48 PEG_RXP14
<18> INT_TXUOUT2+ LVDSB_DATA_2 PEG_RX_14 PEG_RXP15
PCI-EXPRESS
K37 LVDSB_DATA_3 PEG_RX_15 AD40
PEG_TXN[15:0] <18>
J41 C_PEG_TXN0 C189 *.1U/10V_4 PEG_TXN0
PEG_TX#_0 C_PEG_TXN1 C196 *.1U/10V_4 PEG_TXN1
IV&EV Dis/Enable setting PEG_TX#_1 M46
R189 75_4 INT_TV_COMP F25 M47 C_PEG_TXN2 C197 *.1U/10V_4 PEG_TXN2
R195 75_4 INT_TV_Y/G TVA_DAC PEG_TX#_2 C_PEG_TXN3 C208 *.1U/10V_4 PEG_TXN3
H25 TVB_DAC PEG_TX#_3 M40
R205 75_4 INT_TV_C/R K25 M42 C_PEG_TXN4 C218 *E@.1U/10V_4 PEG_TXN4
TVC_DAC PEG_TX#_4
TV
R48 C_PEG_TXN5 C228 *E@.1U/10V_4 PEG_TXN5
PEG_TX#_5 C_PEG_TXN6 C233 *E@.1U/10V_4 PEG_TXN6
H24 TV_RTN PEG_TX#_6 N38
T40 C_PEG_TXN7 C242 *E@.1U/10V_4 PEG_TXN7
PEG_TX#_8 U37
U40 C_PEG_TXN9 C250 *E@.1U/10V_4 PEG_TXN9
Note :REV B: remove R475 PEG_TX#_9 C_PEG_TXN10 C252 *E@.1U/10V_4 PEG_TXN10
C31 TV_DCONSEL_0 PEG_TX#_10 Y40
& R471 short to GND E32 AA46 C_PEG_TXN11 C264 *E@.1U/10V_4 PEG_TXN11
TV_DCONSEL_1 PEG_TX#_11 C_PEG_TXN12 C269 *E@.1U/10V_4 PEG_TXN12
PEG_TX#_12 AA37
B AA40 C_PEG_TXN13 C270 *E@.1U/10V_4 PEG_TXN13 B
PEG_TX#_14 AD43
AC46 C_PEG_TXN15 C276 *E@.1U/10V_4 PEG_TXN15
PEG_TX#_15
PEG_TXP[15:0] <18>
INT_CRT_BLU E28 J42 C_PEG_TXP0 C188 *.1U/10V_4 PEG_TXP0
<18> INT_CRT_BLU CRT_BLUE PEG_TX_0
L46 C_PEG_TXP1 C194 *.1U/10V_4 PEG_TXP1
INT_CRT_GRN G28 PEG_TX_1 C_PEG_TXP2 C195 *.1U/10V_4 PEG_TXP2
<18> INT_CRT_GRN CRT_GREEN PEG_TX_2 M48
M39 C_PEG_TXP3 C206 *.1U/10V_4 PEG_TXP3
INT_CRT_RED J28 PEG_TX_3 C_PEG_TXP4 C220 *E@.1U/10V_4 PEG_TXP4
<18> INT_CRT_RED CRT_RED PEG_TX_4 M43
VGA
R47 C_PEG_TXP5 C224 *E@.1U/10V_4 PEG_TXP5

PEG_TX_5 C_PEG_TXP6 C230 *E@.1U/10V_4 PEG_TXP6
G29 CRT_IRTN PEG_TX_6 N37
T39 C_PEG_TXP7 C236 *E@.1U/10V_4 PEG_TXP7
PEG_TX_7 C_PEG_TXP8 C245 *E@.1U/10V_4 PEG_TXP8
<18> INT_CRT_DDCCLK H32 CRT_DDC_CLK PEG_TX_8 U36
J32 U39 C_PEG_TXP9 C251 *E@.1U/10V_4 PEG_TXP9
<18> INT_CRT_DDCDAT CRT_DDC_DATA PEG_TX_9
R473 I@30.1_4 HSYNC_G J29 Y39 C_PEG_TXP10 C254 *E@.1U/10V_4 PEG_TXP10
<18> INT_HSYNC CRT_HSYNC PEG_TX_10
CRTIREF E29 Y46 C_PEG_TXP11 C256 *E@.1U/10V_4 PEG_TXP11
R474 I@30.1_4 VSYNC_G CRT_TVO_IREF PEG_TX_11 C_PEG_TXP12 C259 *E@.1U/10V_4 PEG_TXP12
<18> INT_VSYNC L29 CRT_VSYNC PEG_TX_12 AA36
AA39 C_PEG_TXP13 C271 *E@.1U/10V_4 PEG_TXP13
HSYNC/VSYNC serial R place close to NB CRTIREF pull down PEG_TX_13 C_PEG_TXP14 C275 *E@.1U/10V_4 PEG_TXP14
PEG_TX_14 AD42
for Teenah 1.3k ohm/F AD46 C_PEG_TXP15 C277 *E@.1U/10V_4 PEG_TXP15
for cantiga 1.02k ohm/F PEG_TX_15
SP@CANTIGA_1p2
A A

PROJECT : ZY2 & ZY6
1A
GMCH VGA
5 4 3 2 1

<16,17> M_A_DQ[63:0] <16,17> M_B_DQ[63:0]

U38D U38E
M_A_DQ0 AJ38 BD21 M_B_DQ0 AK47 BC16
SA_DQ_0 SA_BS_0 M_A_BS0 <16,17> SB_DQ_0 SB_BS_0 M_B_BS0 <16,17>
M_A_DQ1 AJ41 BG18 M_B_DQ1 AH46 BB17
SA_DQ_1 SA_BS_1 M_A_BS1 <16,17> SB_DQ_1 SB_BS_1 M_B_BS1 <16,17>
M_A_DQ2 AN38 AT25 M_B_DQ2 AP47 BB33
D SA_DQ_2 SA_BS_2 M_A_BS2 <16,17> SB_DQ_2 SB_BS_2 M_B_BS2 <16,17> D
M_A_DQ3 AM38 M_B_DQ3 AP46
M_A_DQ4 SA_DQ_3 M_B_DQ4 SB_DQ_3
AJ36 SA_DQ_4 SA_RAS# BB20 M_A_RAS# <16,17> AJ46 SB_DQ_4
M_A_DQ5 AJ40 BD20 M_B_DQ5 AJ48 AU17
SA_DQ_5 SA_CAS# M_A_CAS# <16,17> SB_DQ_5 SB_RAS# M_B_RAS# <16,17>
M_A_DQ6 AM44 AY20 M_B_DQ6 AM48 BG16
SA_DQ_6 SA_WE# M_A_WE# <16,17> SB_DQ_6 SB_CAS# M_B_CAS# <16,17>
M_A_DQ7 AM42 M_B_DQ7 AP48 BF14
SA_DQ_7 SB_DQ_7 SB_WE# M_B_WE# <16,17>
M_A_DQ8 AN43 M_B_DQ8 AU47
AN44 SA_DQ_9 AU46 SB_DQ_9
M_A_DQ10 AU40 M_B_DQ10 BA48
SA_DQ_10 M_A_DM[7:0] <16,17> SB_DQ_10
M_A_DQ11 AT38 AM37 M_A_DM0 M_B_DQ11 AY48
SA_DQ_11 SA_DM_0 SB_DQ_11 M_B_DM[7:0] <16,17>
M_A_DQ12 AN41 AT41 M_A_DM1 M_B_DQ12 AT47 AM47 M_B_DM0
M_A_DQ13 SA_DQ_12 SA_DM_1 M_A_DM2 M_B_DQ13 SB_DQ_12 SB_DM_0 M_B_DM1
AN39 SA_DQ_13 SA_DM_2 AY41 AR47 SB_DQ_13 SB_DM_1 AY47
M_A_DQ14 AU44 AU39 M_A_DM3 M_B_DQ14 BA47 BD40 M_B_DM2
AU42 SA_DQ_15 SA_DM_4 BB12 BC47 SB_DQ_15 SB_DM_3 BF35
M_A_DQ16 AV39 AY6 M_A_DM5 M_B_DQ16 BC46 BG11 M_B_DM4
AY44 SA_DQ_17 SA_DM_6 AT7 BC44 SB_DQ_17 SB_DM_5 BA3
A
M_A_DQ18 BA40 AJ5 M_A_DM7 M_B_DQ18 BG43 AP1 M_B_DM6
B
M_A_DQ19 SA_DQ_18 SA_DM_7 M_B_DQ19 SB_DQ_18 SB_DM_6 M_B_DM7
BD43 SA_DQ_19 M_A_DQS[7:0] <16,17> BF43 SB_DQ_19 SB_DM_7 AK2
M_A_DQ20 AV41 AJ44 M_A_DQS0 M_B_DQ20 BE45
SA_DQ_20 SA_DQS_0 SB_DQ_20 M_B_DQS[7:0] <16,17>
M_A_DQ21 AY43 AT44 M_A_DQS1 M_B_DQ21 BC41 AL47 M_B_DQS0
M_A_DQ22 SA_DQ_21 SA_DQS_1 M_A_DQS2 M_B_DQ22 SB_DQ_21 SB_DQS_0 M_B_DQS1
BB41 BA43 BF40 AV48
MEMORY
MEMORY
BC40 SA_DQ_23 SA_DQS_3 BC37 BF41 SB_DQ_23 SB_DQS_2 BG41
M_A_DQ24 AY37 AW12 M_A_DQS4 M_B_DQ24 BG38 BG37 M_B_DQS3
BD38 SA_DQ_25 SA_DQS_5 BC8 BF38 SB_DQ_25 SB_DQS_4 BH9
M_A_DQ26 AV37 AU8 M_A_DQS6 M_B_DQ26 BH35 BB2 M_B_DQS5
AT36 SA_DQ_27 SA_DQS_7 AM7 M_A_DQS#[7:0] <16,17> BG35 SB_DQ_27 SB_DQS_6 AU1
M_A_DQ28 AY38 AJ43 M_A_DQS#0 M_B_DQ28 BH40 AN6 M_B_DQS7
C SA_DQ_28 SA_DQS#_0 SB_DQ_28 SB_DQS_7 M_B_DQS#[7:0] <16,17> C
M_A_DQ29 BB38 AT43 M_A_DQS#1 M_B_DQ29 BG39 AL46 M_B_DQS#0
M_A_DQ30 SA_DQ_29 SA_DQS#_1 M_A_DQS#2 M_B_DQ30 SB_DQ_29 SB_DQS#_0 M_B_DQS#1
AV36 SA_DQ_30 SA_DQS#_2 BA44 BG34 SB_DQ_30 SB_DQS#_1 AV47
M_A_DQ31 AW36 BD37 M_A_DQS#3 M_B_DQ31 BH34 BH41 M_B_DQS#2
BD13 SA_DQ_32 SA_DQS#_4 AY12 BH14 SB_DQ_32 SB_DQS#_3 BH37
M_A_DQ33 AU11 BD8 M_A_DQS#5 M_B_DQ33 BG12 BG9 M_B_DQS#4
BC11 SA_DQ_34 SA_DQS#_6 AU9 BH11 SB_DQ_34 SB_DQS#_5 BC2
M_A_DQ35 BA12 AM8 M_A_DQS#7 M_B_DQ35 BG8 AT2 M_B_DQS#6
SYSTEM
M_A_DQ36 SA_DQ_35 SA_DQS#_7 M_B_DQ36 SB_DQ_35 SB_DQS#_6 M_B_DQS#7
SYSTEM
AU13 SA_DQ_36 M_A_A[14:0] <16,17> BH12 SB_DQ_36 SB_DQS#_7 AN5
M_A_DQ37 AV13 BA21 M_A_A0 M_B_DQ37 BF11
SA_DQ_37 SA_MA_0 SB_DQ_37 M_B_A[14:0] <16,17>
M_A_DQ38 BD12 BC24 M_A_A1 M_B_DQ38 BF8 AV17 M_B_A0
M_A_DQ39 SA_DQ_38 SA_MA_1 M_A_A2 M_B_DQ39 SB_DQ_38 SB_MA_0 M_B_A1
BC12 SA_DQ_39 SA_MA_2 BG24 BG7 SB_DQ_39 SB_MA_1 BA25
M_A_DQ40 BB9 BH24 M_A_A3 M_B_DQ40 BC5 BC25 M_B_A2
BA9 SA_DQ_41 SA_MA_4 BG25 BC6 SB_DQ_41 SB_MA_3 AU25
M_A_DQ42 AU10 BA24 M_A_A5 M_B_DQ42 AY3 AW25 M_B_A4
AV9 SA_DQ_43 SA_MA_6 BD24 AY1 SB_DQ_43 SB_MA_5 BB28
M_A_DQ44 BA11 BG27 M_A_A7 M_B_DQ44 BF6 AU28 M_B_A6
BD9 SA_DQ_45 SA_MA_8 BF25 BF5 SB_DQ_45 SB_MA_7 AW28
M_A_DQ46 AY8 AW24 M_A_A9 M_B_DQ46 BA1 AT33 M_B_A8
BA6 SA_DQ_47 SA_MA_10 BC21 BD3 SB_DQ_47 SB_MA_9 BD33
M_A_DQ48 M_A_A11 M_B_DQ48 M_B_A10
DDR
AV5 SA_DQ_48 SA_MA_11 BG26 AV2 SB_DQ_48 SB_MA_10 BB16
DDR
M_A_DQ49 AV7 BH26 M_A_A12 M_B_DQ49 AU3 AW33 M_B_A11
AT9 SA_DQ_50 SA_MA_13 BH17 AR3 SB_DQ_50 SB_MA_12 AY33
M_A_DQ51 AN8 AY25 M_A_A14 M_B_DQ51 AN2 BH15 M_B_A13
M_A_DQ52 SA_DQ_51 SA_MA_14 M_B_DQ52 SB_DQ_51 SB_MA_13 M_B_A14
AU5 SA_DQ_52 AY2 SB_DQ_52 SB_MA_14 AU33
M_A_DQ53 AU6 M_B_DQ53 AV1
B AT5 SA_DQ_54 AP3 SB_DQ_54 B
M_A_DQ55 AN10 M_B_DQ55 AR1
AM11 SA_DQ_56 AL1 SB_DQ_56
M_A_DQ57 AM5 M_B_DQ57 AL2
AJ9 SA_DQ_58 AJ1 SB_DQ_58
M_A_DQ59 AJ8 M_B_DQ59 AH1
AN12 SA_DQ_60 AM2 SB_DQ_60
M_A_DQ61 AM13 M_B_DQ61 AM3
AJ11 SA_DQ_62 AH3 SB_DQ_62
M_A_DQ63 AJ12 M_B_DQ63 AJ3
SA_DQ_63 SB_DQ_63
SP@CANTIGA_1p2 SP@CANTIGA_1p2
A A

PROJECT : ZY2 & ZY6
1A
GMCH DDRII
5 4 3 2 1

Power consumption reference to Intel

644135 Cantiga chipset EDS Volume1.
Section 10
GM TDP 10.5~12W
GS TDP 7~8W VCC
PM TDP 7W VCC_NCTF
Intel check list(Rev 0.8)
270U*1 near to power(+V1.05M). 1210.34mA_EV
270U*2 near to NB
D
Intel CRB(Rev 0.7) 1930.4mA_IV D
Intel check list(Rev 0.8) 270U*3 near to power(+V1.05M). ME Engine

No description for VCC_SM bulk CAP 270U*1 near to NB
+1.05V_AXG Intel CRB(Rev 0.7) ESR=12m ohm 508.12mA
U38G 330U*1 Reserve near to power Total Max=2438.52mA
+VDR_SUS 330U*1 near to NB
AP33 W28
VCC_SM_1 VCC_AXG_NCTF_1 +1.05V U38F
AN33 V28
VCC_SM_2 VCC_AXG_NCTF_2
BH32 W26
BG32 V26
C519 C521 C244 + C518 VCC_SM_4 VCC_AXG_NCTF_4
BF32 W25
BD32 V25 AG34
22U/6V_8 22U/6V_8 0.1U/10V_4 330U/2V_7 VCC_SM_6 VCC_AXG_NCTF_6 VCC_1
BC32 W24 AC34
VCC_SM_7 VCC_AXG_NCTF_7 VCC_2
BB32 V24 AB34
VCC_SM_8 VCC_AXG_NCTF_8 C231 C225 C226 C210 + C524 VCC_3
BA32 W23 AA34
AY32 V23 Y34
Place on the edga VCC_SM_10 VCC_AXG_NCTF_10 .1U/10V_4 .22U/6V_4 .22U/6V_4 22U/6V_8 330U/2V_7 VCC_5
AW32 AM21 V34
AV32 AL21 U34
VCC_SM_12 VCC_AXG_NCTF_12 Place close to VCC_7
AU32 AK21 AM33
VCC_SM_13 VCC_AXG_NCTF_13 the GMCH VCC_8
AT32 W21 AK33
AR32 V21 AJ33
AP32 U21 AG33
POWER
AN32 AM20 AF33
BH31 AK20
BG31 W20 AE33
VCC CORE
BF31 U20 AC33
BG30 AM19 AA33
VCC_SM(1.8V) BH29
AL19 Y33
VCC_16
BG29 AK19 W33
DDR2(800M) VCC_SM_23 VCC_AXG_NCTF_23 VCC_17
BF29 AJ19 V33
3000mA_S0 , 1mA_S3 BD29
VCC_SM_25 VCC SM VCC_AXG_NCTF_25
AH19 U33
VCC_19
BC29 AG19 AH28
DDR2(667M) : 2600mA_S0 VCC_SM_26 VCC_AXG_NCTF_26 VCC_20
BB29 AF19 AF28
DDR3(1067M) : 4140mA_S0 BA29 AE19 AC28
AY29 AB19 AA28
AW29 AA19 AJ26
C AV29 Y19 AG26 C
AU29 W19 AE26
AT29 V19 AC26
AR29 U19 AH25
AP29 AM17 AG25
AK17 AF25
VCC_AXG_NCTF_36 VCC_30
BA36 AH17 AG24
VCC_SM_36/NC VCC_AXG_NCTF_37 VCC_31
BB24 AG17 AJ23
VCC_SM_37/NC VCC_AXG_NCTF_38 VCC_32 +1.05V
BD16 AF17 AH23
BB21 AE17 AF23
POWER
AW16 AC17 AM32
VCC_SM_40/NC VCC_AXG_NCTF_41 +1.05V +1.05V_AXG VCC_NCTF_1
AW13 AB17 T32 AL32
VCC_SM_41/NC VCC_AXG_NCTF_42 VCC_35 VCC_NCTF_2
AT13 Y17 AK32
VCC_SM_42/NC VCC_AXG_NCTF_43 R227 I@0_8 VCC_NCTF_3
W17 AJ32
+1.05V_AXG VCC_AXG_NCTF_44 VCC_NCTF_4
V17 AH32
VCC GFX NCTF
VCC_AXG_NCTF_45 R228 I@0_8 VCC_NCTF_5

AM16 AG32
VCC_AXG_NCTF_46 VCC_NCTF_6
Y26 AL16 AE32
VCC_AXG_1 VCC_AXG_NCTF_47 VCC_NCTF_7
1.05V AE25 AK16 AC32
AB25 AJ16 AA32
Graphics core VCC_AXG_3 VCC_AXG_NCTF_49 VCC_NCTF_9
AA25 AH16 Y32
VCC_AXG AE24 AG16 W32
AC24 AF16 U32
VCC_AXG_NCTF VCC_AXG_6 VCC_AXG_NCTF_52 VCC_NCTF_12
AA24 AE16 AM30
VCC_AXG_7 VCC_AXG_NCTF_53 SP@:INT 1 U VCC_NCTF_13
6326.84mA Y24
VCC_AXG_8 VCC_AXG_NCTF_54
AC16
+1.05V_AXG
IV&EV Dis/Enable setting VCC_NCTF_14
AL30
AE23 AB16 EXT 0 ohm AK30
VCC_AXG_9 VCC_AXG_NCTF_55 Design guide(Table 72) VCC_NCTF_15
AC23 AA16 AH30
VCC_AXG_10 VCC_AXG_NCTF_56 For INT VGA diasble.VCC_AXG power can connect to GND VCC_NCTF_16
AB23 Y16 AG30
AA23 W16 AF30
AJ21 V16 AE30
VCC_AXG_13 VCC_AXG_NCTF_59 + C191 + C192 C200 C237 C217 C201 C247 C203 VCC_NCTF_19
AG21 U16 AC30
Voltage regulator is VCC_AXG_14 VCC_AXG_NCTF_60 VCC_NCTF_20
AE21 AB30
shared between the VCC_AXG_15 I@330U/2.5V_7343 I@330U/2.5V_7343 I@.47U/6V_4 SP@0_6 I@10U/10V_8 I@22U/6V_8 I@.1U/10V_4 I@.1U/10V_4 VCC_NCTF_21
AC21 AA30
Graphics Core Rail, VCC_AXG_16 VCC_NCTF_22
AA21 Y30
VCCA_HPLL, VCCA_MPLL, VCC_AXG_17 VCC_NCTF_23
Y21 W30
VCCA_PEG_PLLVCCD_PEG_PLL, VCC_AXG_18 VCC_NCTF_24
VCC NCTF
AH20 V30
VCCA_SM_CK, VCCA_DPLLA, VCC_AXG_19 Place close to the GMCH Cavity Capacitors VCC_NCTF_25
AF20 U30
VCCA_DPLLB, VCCD_HPLL, VCC_AXG_20 VCC_NCTF_26
AE20 AL29
VCCA_SM, VCC_AXF VCC_AXG_21 Intel check list(Rev 0.8) VCC_NCTF_27
AC20 AK29
B VCC_AXG_22 220U*2 near to NB(ESR=15m ohm) VCC_NCTF_28 B
AB20 AJ29
VCC_AXG_23 Intel CRB(Rev 0.7) VCC_NCTF_29
AA20 AH29
VCC_AXG_24 270U*4 near to power(+V1.05S). VCC_NCTF_30
T17 AG29
VCC_AXG_25 330U*2 near to NB VCC_NCTF_31
T16 AE29
VCC_AXG_26 VCC_NCTF_32
AM15 AC29
AL15 AA29
AE15 Y29
AJ15 W29
AH15 V29
AG15 AL28
AF15 AK28
AB15 AL26
AA15 AK26
VCC GFX
Y15
VCC_AXG_36 1.8V VCC_NCTF_42
AK25
V15 AK24
VCC_AXG_37 Internal connect to power VCC_NCTF_43
U15 AK23
AN14
VCC_AXG_39
AM14
VCC_AXG_40 VCC_SM_LF1
U14 AV44
VCC_AXG_41 VCC_SM_LF1 VCC_SM_LF2
VCC SM LF
T14 BA37
VCC_AXG_42 VCC_SM_LF2 VCC_SM_LF3
AM40
VCC_SM_LF3 VCC_SM_LF4
AV21
VCC_SM_LF4 VCC_SM_LF5 SP@CANTIGA_1p2
AY5
VCC_SM_LF5 VCC_SM_LF6
AM10
+1.05V_AXG VCC_SM_LF6 VCC_SM_LF7
BB13
VCC_SM_LF7
C268 C239 C255 C253 C238 C266 C258
R242 I@10/F_4 AJ14
R238 I@10/F_4 VCC_AXG_SENSE .1U/10V_4 .1U/10V_4 .22U/6V_4 .22U/6V_4 .47U/6V_4 1U/6V_4 1U/6V_4
AH14
VSS_AXG_SENSE
1. Route VCC_AXG_SENSE and VSS_AXG_SENSE differentially

2. VCC_AXG_SENSE PU to +VGFX_CORE_INT with 10ohm
and VSS_AXG_SENSE PD with 10ohm for Intel suggest
A SP@CANTIGA_1p2 A

PROJECT : ZY2 & ZY6
Rev
1A
GMCH VCC,NCTF
5 4 3 2 1

Design guide Table 72

IV&EV Dis/Enable setting
Power consumption reference to Intel External Graphics
+3V R480 I@0_6 +3V_A_CRT_DAC (GMCH Integrated Graphics Disable)
644135 Cantiga chipset EDS Volume1.
Section 10 C542 C540 VCCSYNC_CRT GND
I@.1U/10V_4 SP@0_4 VCCA_CRT_DAC GND
VCCD_LVDS GND
1210 10UH, 10% SP@:INT 0.01U
0.45A DCR_max = 0.39 EXT 0 ohm VCC_TX_LVDS GND
R476 I@0_6 +3V_A_DAC_BG VCCA_LVDS GND
C543 C179 VCCA_TVDAC GND
D D
+1.05V L48 I@10UH_8 I@.1U/10V_4 SP@0_4 VCCD_QDAC GND
3.3V U38H
VCCA_DAC_BG GND
+ C550 C546 73mA U13 +1.05V
VTT_1
VTT_2
T13 VCC_AXG GND
I@220U/2.5V_7343 SP@0_4 B27 U12 1.05V
VCCA_CRT_DAC_1 VTT_3 + C180
3.3V A26 T12 C198 C193 C199 C190 VCC_AXG_NCTF GND
ESR=15 m VCCA_CRT_DAC_2 VTT_4 FSB-1067
U11
2.68mA VTT_5 .47U/6V_4 2.2U/6V_6 4.7U/10V_6 4.7U/10V_6 330U/2.5V_7
1.05V VTT_6
T11 852mA
A25 U10
CRT
64.8mA for A/B VCCA_DAC_BG VTT_7 ESR= 12m ohm
B25 T10
VSSA_DAC_BG VTT_8
SP@:INT 0.1U U9
Design guide table 72 VTT_9
EXT 0 ohm T9
1210 10UH, 10% VCCA_DPLLA/B always keep to +1.05V(If no use IV dynamic core power) VTT_10
U8
0.45A DCR_max = 0.39 +1.05VM_DPLLA VTT_11
F47 T8
VCCA_DPLLA VTT_12
U7
VTT
L44 I@10UH_8 +1.05VM_DPLLB VTT_13
+1.05V L48 T7
VCCA_DPLLB VTT_14
U6
+ C535 C533 +1.05VM_HPLL VTT_15
AD1 T6
PLL
VCCA_HPLL VTT_16
U5
I@220U/2.5V_7343 SP@.1U/10V_4 +1.05VM_MPLL VTT_17
AE1 T5
VCCA_MPLL VTT_18
V3
ESR=15 m +1.8VSUS_TXLVDS VTT_19 Check list : 0.1UH
U3
VTT_20 CRB : 0 ohm
IV&EV Dis/Enable setting J48
VCCA_LVDS VTT_21
V2
C538 U2 1210 0.1 ?H, 20% 1A
A LVDS
VTT_22 DCR max = 78 m
1.8V J47
VSSA_LVDS VTT_23
T2
+1.05V R245 0_6 R244 0_6 I@1000P/50V_4 V1
13.2mA VTT_24
+1.05VM_MCH_PLL2
U1
C229 C223 VTT_25
1.05V
R462 0_8 +VCCA_PEG_BG AD48 +1.05VM_AXF L46 1UH_8
24mA +1.5V VCCA_PEG_BG +1.05V
4.7U/10V_6 .1U/10V_4 1.5V
C528 1.05V C545 C547
1.05V 414uA 1.05V
A PEG
.1U/10V_4 50mA 1U/6V_4 *10U/10V_8
139.2mA 3.9 nH, 0.2 nH, 1A +1.05VM_PEGPLL AA48 321.35mA 0805 1UH , Rdc = 0.14 - 0.26.
L29 BLM18PG181SN1D_6 , DCR_max=32 m VCCA_PEG_PLL VCCA_PEG_PLL ESR = 60 m Max rated current = 220 mA
+1.25V for Teenah use(100mA)
C 1210 0.1uH, 20%, 1A,
+1.05V R240 0_6 +1.05VM_A_SM AR20 C
DCR_max=0.078 VCCA_SM_1 +1.8VSUS_VCC_SM_CK L42 1UH_8
AP20 +VDR_SUS
C248 C246 C240 VCCA_SM_2
AN20
+1.05VM_MPLL_RC R234 0.5/F_6
22U/6V_8 4.7U/10V_6 1U/6V_4
AR17
AP17
VCCA_SM_3
VCCA_SM_4
VCCA_SM_5
POWER C522
1/F_4 R455 +1.8VSUS_SMCK_RC C520 10U/10V_8 1.8V
1.05V AN17 .1U/10V_4
C227 C221 VCCA_SM_6 DDR2-800
AT16
DDR2-800 VCCA_SM_7
AR16 124mA
A SM
22U/6V_8 .1U/10V_4 VCCA_SM_8
720mA AP16
VCCA_SM_9
IV&EV Dis/Enable setting 0805 100 nH, DCR=160 m

+1.8VSUS_TXLVDS L45 I@0.1UH_1.5 +1.8V
1.05V SP@:INT 1000 P 1.8V

R241 0_6 +1.05VM_A_SM_CK AP28 EXT 0 ohm C537 C536
DDR2-800 +1.05V VCCA_SM_CK_1 118.8mA
AN28 B22
CRB : 0 ohm C241 C235 C243 VCCA_SM_CK_2 VCC_AXF_1 SP@1000P/50V_4 I@22U/6V_8
26mA AP25 B21
AXF
Check list : 2.2nH VCCA_SM_CK_3 VCC_AXF_2
AN25 A21
*2.2U/10V_6 22U/6V_8 .1U/10V_4 VCCA_SM_CK_4 VCC_AXF_3
AN24
VCCA_SM_CK_5
AM28 3.3V
FB 180@100 MHz, 25% 1.5A VCCA_SM_CK_NCTF_1
IV&EV Dis/Enable setting AM26
A CK
DCR_max=90 m VCCA_SM_CK_NCTF_2 105.3mA
AM25
VCCA_SM_CK_NCTF_3
AL25 BF21
L47 I@BLM18PG181SN1D_6 VCCA_SM_CK_NCTF_4 VCC_SM_CK_1
AM24 BH20
SM CK
+3V VCCA_SM_CK_NCTF_5 VCC_SM_CK_2 +3V
AL24 BG20
VCCA_SM_CK_NCTF_6 VCC_SM_CK_3
3.3V SP@:INT 0.01U AM23 BF20
C549 C544 C541 VCCA_SM_CK_NCTF_7 VCC_SM_CK_4 R489 10_4 +1.05V_SD D38
24.15mA for VCCA_TVA_DAC EXT 0 ohm AL23 1 2 BAT54 +1.05V
VCCA_SM_CK_NCTF_8
I@10U/6.3V_8 39.48mA for VCCA_TVB_DAC I@.1U/10V_4 SP@0_4 C182
24.15mA for VCCA_TVC_DAC VCC_TX_LVDS
K47
+3V_TV_DAC B24 .1U/10V_4
Total 87.78mA VCCA_TV_DAC_1
A24 C35
VCCA_TV_DAC_2 VCC_HV_1
TV
CRB no 10U B35
Check list need min 10U~100U for VCCA_TV_DAC VCC_HV_2
A35
HV
VCC_HV_3 +1.05V
+1.5V R486 I@0_6 +VCC_HDA A32 1.05V
VCC_HDA
HDA
1.5V V48
B
SP@:INT 0.1U C175 +1.5V_TVDAC VCC_PEG_1 1782mA B
U48
50mA VCC_PEG_2
EXT 0 ohm V47
PEG
SP@0_4 VCC_PEG_3 C530 C525 + C532 ESL=2.4 nH
U47
VCC_PEG_4
D TV/CRT
VCCD_QDAC share to TV and CRT M25 U46 ESR =15 m
VCCD_TVDAC VCC_PEG_5 4.7U/10V_6 22U/6V_8 220U/6_7343
+1.5V_QDAC L28
Design guide table 72 VCCD_QDAC
VCCD_TVDAC always keep 0.1U/0.022U/10U to +1.5V
1.5V VCC_DMI_1
AH48
+1.05VM_MCH_PLL2 AF1 AF48
58.67mA VCCD_HPLL VCC_DMI_2 C526
AH47
DMI
R179 0_6 C234 +1.05VM_PEGPLL VCC_DMI_3
+1.5V AA47 AG47
VCCD_PEG_PLL VCC_DMI_4 .1U/10V_4
1.05V
.1U/10V_4 C531 1.05V
C185 C183 157.2mA M38
VCCD_LVDS_1 456mA
LVDS
.1U/10V_4 L37 A8
.1U/10V_4 .01U/16V_4 VCCD_LVDS_2 VTTLF1
L1
VTTLF2
VTTLF
1.5V VTTLF3
AB2
48.363mA for CRT C211 C534 C539
5mA for TV
SP@CANTIGA_1p2 .47U/6V_4 .47U/6V_4 .47U/6V_4 1.05V
L49 I@BLM18PG181SN1D_6
Internal connect to power
C548 FB 180@100 MHz, 25% 1.5A
DCR_max=90 m C184 C181 Power Rail Differences between
10U/6.3V_8 the Teenah and Cantiga Chipset Family
CRB no 10U I@.1U/10V_4 SP@0_4
Check list need min 10U~100U
for VCCA_QDAC SP@:INT 0.01U Power Net Name Cantiga(V) Tennah(V) Tennah Current
EXT 0 ohm
VCC_AXG_# 1.05V 1.25V 6326.84mA
VCC_AXG_NCTF_# Cantiga use
VCCA_PEG_BG 1.5V 3.3V 400uA

FB 220 @100 MHz, 25%, 2A VCCA_DPLLA 1.05V 1.25V 100mA
A 1.05V +1.05V L43 BLM18PG181SN1D_6 VCCA_DPLLB 1.05V 1.25V 100mA A
50mA C529 VCCA_SM_# 1.05V 1.25V 1065mA

.1U/10V_4 VCCA_HPLL 1.05V 1.25V 50mA
IV&EV Dis/Enable setting
+1.05VM_PEGPLL_RC R463 1/F_4 VCCA_MPLL 1.05V 1.25V 150mA
R176 I@0_6 +1.8VSUS_DLVDS
+1.8V
C527 VCCA_SM_CK_# 1.05V 1.25V 35mA
1.8V
10U/10V_8 C187 VCCA_PEG_PLL 1.05V 1.25V 100mA
ESR=60m ohm
60.31mA Quanta Computer Inc.
SP@0_4 VCC_AXF_# 1.05V 1.25V 495mA
SP@:INT 1 U PROJECT : ZY2 & ZY6
EXT 0 ohm VCCD_HPLL 1.05V 1.25V 250mA
VCCD_PEG_PLL 1.05V 1.25V 100mA GMCH POWER 1A

5 4 3 2 1

5 4 http://laptopblue.vn/
3 2 1
U38I U38J
BG21 VSS_199 VSS_297 AH8
AU48 VSS_1 VSS_100 AM36 L12 VSS_200 VSS_298 Y8
AR48 VSS_2 VSS_101 AE36 AW21 VSS_201 VSS_299 L8
AL48 VSS_3 VSS_102 P36 AU21 VSS_202 VSS_300 E8
BB47 VSS_4 VSS_103 L36 AP21 VSS_203 VSS_301 B8
AW47 VSS_5 VSS_104 J36 AN21 VSS_204 VSS_302 AY7
AN47 VSS_6 VSS_105 F36 AH21 VSS_205 VSS_303 AU7
AJ47 VSS_7 VSS_106 B36 AF21 VSS_206 VSS_304 AN7
AF47 VSS_8 VSS_107 AH35 AB21 VSS_207 VSS_305 AJ7
D
AD47 VSS_9 VSS_108 AA35 R21 VSS_208 VSS_306 AE7 D
AB47 VSS_10 VSS_109 Y35 M21 VSS_209 VSS_307 AA7
Y47 VSS_11 VSS_110 U35 J21 VSS_210 VSS_308 N7
T47 VSS_12 VSS_111 T35 G21 VSS_211 VSS_309 J7
N47 VSS_13 VSS_112 BF34 BC20 VSS_212 VSS_310 BG6
L47 VSS_14 VSS_113 AM34 BA20 VSS_213 VSS_311 BD6
G47 VSS_15 VSS_114 AJ34 AW20 VSS_214 VSS_312 AV6
BD46 VSS_16 VSS_115 AF34 AT20 VSS_215 VSS_313 AT6
BA46 VSS_17 VSS_116 AE34 AJ20 VSS_216 VSS_314 AM6
AY46 VSS_18 VSS_117 W34 AG20 VSS_217 VSS_315 M6
AV46 VSS_19 VSS_118 B34 Y20 VSS_218 VSS_316 C6
AR46 VSS_20 VSS_119 A34 N20 VSS_219 VSS_317 BA5
AM46 VSS_21 VSS_120 BG33 K20 VSS_220 VSS_318 AH5
V46 VSS_22 VSS_121 BC33 F20 VSS_221 VSS_319 AD5
R46 VSS_23 VSS_122 BA33 C20 VSS_222 VSS_320 Y5
P46 VSS_24 VSS_123 AV33 A20 VSS_223 VSS_321 L5
H46 VSS_25 VSS_124 AR33 BG19 VSS_224 VSS_322 J5
F46 VSS_26 VSS_125 AL33 A18 VSS_225 VSS_323 H5
BF44 VSS_27 VSS_126 AH33 BG17 VSS_226 VSS_324 F5
AH44 VSS_28 VSS_127 AB33 BC17 VSS_227 VSS_325 BE4
AD44 VSS_29 VSS_128 P33 AW17 VSS_228
AA44 L33 AT17 BC3
Y44
U44
VSS_30
VSS_31
VSS_32
VSS_129
VSS_130
VSS_131
H33
N32
R17
M17
VSS_229
VSS_230
VSS_231
VSS VSS_327
VSS_328
VSS_329
AV3
AL3
T44 K32 H17 R3
M44
F44
VSS_33
VSS_34
VSS_35
VSS VSS_132
VSS_133
VSS_134
F32
C32
C17
VSS_232
VSS_233
VSS_330
VSS_331
VSS_332
P3
F3
BC43 VSS_36 VSS_135 A31 BA16 VSS_235 VSS_333 BA2
AV43 VSS_37 VSS_136 AN29 VSS_334 AW2
AU43 VSS_38 VSS_137 T29 AU16 VSS_237 VSS_335 AU2
C AM43 VSS_39 VSS_138 N29 AN16 VSS_238 VSS_336 AR2 C
J43 VSS_40 VSS_139 K29 N16 VSS_239 VSS_337 AP2
C43 VSS_41 VSS_140 H29 K16 VSS_240 VSS_338 AJ2
BG42 VSS_42 VSS_141 F29 G16 VSS_241 VSS_339 AH2
AY42 VSS_43 VSS_142 A29 E16 VSS_242 VSS_340 AF2
AT42 VSS_44 VSS_143 BG28 BG15 VSS_243 VSS_341 AE2
AN42 VSS_45 VSS_144 BD28 AC15 VSS_244 VSS_342 AD2
AJ42 VSS_46 VSS_145 BA28 W15 VSS_245 VSS_343 AC2
AE42 VSS_47 VSS_146 AV28 A15 VSS_246 VSS_344 Y2
N42 VSS_48 VSS_147 AT28 BG14 VSS_247 VSS_345 M2
L42 VSS_49 VSS_148 AR28 AA14 VSS_248 VSS_346 K2
BD41 VSS_50 VSS_149 AJ28 C14 VSS_249 VSS_347 AM1
AU41 VSS_51 VSS_150 AG28 BG13 VSS_250 VSS_348 AA1
AM41 VSS_52 VSS_151 AE28 BC13 VSS_251 VSS_349 P1
AH41 VSS_53 VSS_152 AB28 BA13 VSS_252 VSS_350 H1
AD41 VSS_54 VSS_153 Y28
AA41 VSS_55 VSS_154 P28 VSS_351 U24
Y41 VSS_56 VSS_155 K28 AN13 VSS_255 VSS_352 U28
U41 VSS_57 VSS_156 H28 AJ13 VSS_256 VSS_353 U25
T41 VSS_58 VSS_157 F28 AE13 VSS_257 VSS_354 U29
M41 VSS_59 VSS_158 C28 N13 VSS_258 VSS_355 AJ6
G41 VSS_60 VSS_159 BF26 L13 VSS_259
B41 VSS_61 VSS_160 AH26 G13 VSS_260 VSS_NCTF_1 AF32
BG40 VSS_62 VSS_161 AF26 E13 VSS_261 VSS_NCTF_2 AB32
BB40 VSS_63 VSS_162 AB26 BF12 VSS_262 VSS_NCTF_3 V32
AV40 VSS_64 VSS_163 AA26 AV12 VSS_263 VSS_NCTF_4 AJ30
AN40 VSS_65 VSS_164 C26 AT12 VSS_264 VSS_NCTF_5 AM29
H40 VSS_66 VSS_165 B26 AM12 VSS_265 VSS_NCTF_6 AF29
E40 BH25 AA12 AB29
VSS NCTF
VSS_67 VSS_166 VSS_266 VSS_NCTF_7
B
AT39 VSS_68 VSS_167 BD25 J12 VSS_267 VSS_NCTF_8 U26 B
AM39 VSS_69 VSS_168 BB25 A12 VSS_268 VSS_NCTF_9 U23
AJ39 VSS_70 VSS_169 AV25 BD11 VSS_269 VSS_NCTF_10 AL20
AE39 VSS_71 VSS_170 AR25 BB11 VSS_270 VSS_NCTF_11 V20
N39 VSS_72 VSS_171 AJ25 AY11 VSS_271 VSS_NCTF_12 AC19
L39 VSS_73 VSS_172 AC25 AN11 VSS_272 VSS_NCTF_13 AL17
B39 VSS_74 VSS_173 Y25 AH11 VSS_273 VSS_NCTF_14 AJ17
BH38 VSS_75 VSS_174 N25 VSS_NCTF_15 AA17
BC38 VSS_76 VSS_175 L25 Y11 VSS_275 VSS_NCTF_16 U17
BA38 VSS_77 VSS_176 J25 N11 VSS_276
AU38 VSS_78 VSS_177 G25 G11 VSS_277 VSS_SCB_1 BH48
AH38 E25 C11 BH1
VSS SCB
VSS_79 VSS_178 VSS_278 VSS_SCB_2
AD38 VSS_80 VSS_179 BF24 BG10 VSS_279 VSS_SCB_3 A48
AA38 VSS_81 VSS_180 AD12 AV10 VSS_280 VSS_SCB_4 C1
Y38 VSS_82 VSS_181 AY24 AT10 VSS_281
U38 VSS_83 VSS_182 AT24 AJ10 VSS_282 VSS_SCB_6 A3
T38 VSS_84 VSS_183 AJ24 AE10 VSS_283
J38 VSS_85 VSS_184 AH24 AA10 VSS_284 NC_26 E1
F38 VSS_86 VSS_185 AF24 M10 VSS_285 NC_27 D2
C38 VSS_87 VSS_186 AB24 BF9 VSS_286 NC_28 C3
BF37 VSS_88 VSS_187 R24 BC9 VSS_287 NC_29 B4
BB37 VSS_89 VSS_188 L24 AN9 VSS_288 NC_30 A5
AW37 VSS_90 VSS_189 K24 AM9 VSS_289 NC_31 A6
AT37 VSS_91 VSS_190 J24 AD9 VSS_290 NC_32 A43
AN37 VSS_92 VSS_191 G24 G9 VSS_291 NC_33 A44
AJ37 F24 B9 B45
NC
VSS_93 VSS_192 VSS_292 NC_34
H37 VSS_94 VSS_193 E24 BH8 VSS_293 NC_35 C46
C37 VSS_95 VSS_194 BH23 BB8 VSS_294 NC_36 D47
BG36 VSS_96 VSS_195 AG23 AV8 VSS_295 NC_37 B47
BD36 VSS_97 VSS_196 Y23 AT8 VSS_296 NC_38 A46
A AK15 VSS_98 VSS_197 B23 NC_39 F48 A
AU36 VSS_99 VSS_198 A23 NC_40 E48
NC_41 C48
NC_42 B48
SP@CANTIGA_1p2 A47
NC_43
SP@CANTIGA_1p2
PROJECT : ZY2 & ZY6
1A
GMCH VSS
5 4 3 2 1

5 4
11/8 REV:B Y9 change footprint

http://laptopblue.vn/ 3 2 1
C410 15P/50V_4 11/26 REV:B C410 &C409 change to 15p

97/03/25 REV: C Change to NPO
2
1
Y9 R368
32.768KHZ U35A
10M_6 CLK_32KX1 C23 K5
RTCX1 FWH0/LAD0 LAD0 <23,32>
CLK_32KX2 C24 K4
3
4
RTCX2 FWH1/LAD1 LAD1 <23,32>
C409 15P/50V_4 L6
RTC_RST# FWH2/LAD2 LAD2 <23,32> +1.05V
A25 RTCRST# FWH3/LAD3 K2 LAD3 <23,32>
RTC
LPC
SRTC_RST# F20
R360 1M/F_6 SM_INTRUDER# SRTCRST#
+VCCRTC C22 INTRUDER# FWH4/LFRAME# K3 LFRAME# <23,32>
R393 332K/F_4 ICH_INTVRMEN B22 J3 T44
LDRQ0/1# : Internal PU
D INTVRMEN LDRQ0# R434 R298 +1.05V D
A22 LAN100_SLP LDRQ1#/GPIO23 J1 T65
Internal VRM enabled for R326 8.2K_4 Layout note:
VccSus1_05, VccSus1_5, +3V DPRSTP# , Daisy Chain
E25 N7 GATEA20 <32> *56_4 *56_4
VccCL1_5, VccLAN1_05 and GLAN_CLK A20GATE (SB>Power>NB>CPU)
A20M# AJ27 H_A20M# <3>
VccCL1_05. C13 R433
LAN_RSTSYNC H_DPRSTP#_R R435 0_4
DPRSTP# AJ25 ICH_DPRSTP# <3,6,35>
LAN / GLAN
F14 AE23 H_DPSLP#_R R312 0_4 56_4
LAN_RXD0 DPSLP# H_DPSLP# <3>
G13 LAN_RXD1
D14 AJ26 H_FERR#_R R432 56_4
24.9 Ohm pull up to 1.5V LAN_RXD2 FERR# H_FERR# <3>
for GLAN_COMPI/O is D13 AD22
required, no matter LAN_TXD0 CPUPWRGD H_PWRGD <3>
D12 LAN_TXD1
intel LAN is used or +3V_S5 E13 AF25
LAN_TXD2 IGNNE# H_IGNNE# <3>
CPU
not.
R376 10K_4 ICH_GPIO56 B10 AE22
GLAN_DOCK#/GPIO56 INIT# H_INIT# <3>
INTR AG25 H_INTR <3>
+1.5V R351 24.9/F_4 B28 L3 R343 10K_4 +3V
GLAN_COMPI RCIN#
B27 GLAN_COMPO RCIN# <32>
NMI AF23 H_NMI <3>
HDA_BIT_CLK_R AF6 AF24 H_SMI#_R R299 0_4
Internal pull-down HDA_SYNC_R HDA_BIT_CLK SMI# H_SMI# <3>
AH4 HDA_SYNC
resistors that are AH27 R297 56.2/F_4
always enabled STPCLK# H_STPCLK# <3> +1.05V
HDA_RST#_R AE7 HDA_RST# H_THERMTRIP_R R311 54.9/F_4 H_THERMTRIP_RR R296 *0_4
THRMTRIP# AG26 PM_THRMTRIP# <3,6>
<25> ACZ_SDIN0 AF4 HDA_SDIN0
AG4 AG27 No use Thermal trip SB side still PU 56ohm.(Serial R use 0ohm)
<25> ACZ_SDIN1 HDA_SDIN1 TP8 T39
Use Thermal trip can share PU for CPU and SB side(And Serial R use 54.9 ohm)
IHDA
HDA_SDIN2 AH3
HDA_SDIN3 HDA_SDIN2 PU L<2"
AE5 HDA_SDIN3
SATA4RXN AH11 SATA_RXN4 <24>
C HDA_SDOUT_R AG5 AJ11 SATA_RXP4 <24> C
HDA_SDOUT SATA4RXP
SATA4TXN AG12 SATA_TXN4 <24>
T38 AG7 HDA_DOCK_EN#/GPIO33 SATA4TXP AF12 SATA_TXP4 <24>
T40 AE8 HDA_DOCK_RST#/GPIO34
OC Pin need PU, ZS2 PU at LED side. AH9
SATA5RXN
<31> SATA_LED# AG8 SATALED# SATA5RXP AJ9
SATA5TXN AE10
<24> SATA_RXN0 AJ16 SATA0RXN SATA5TXP AF10
AH16
SATA
<24> SATA_RXP0 SATA0RXP
<24> SATA_TXN0 AF17 SATA0TXN SATA_CLKN AH18 CLK_PCIE_SATA# <2>
<24> SATA_TXP0 AG17 SATA0TXP SATA_CLKP AJ18 CLK_PCIE_SATA <2>
AH13 AJ7 SATA_RBIAS_PN
<24> SATA_RXN1 SATA1RXN SATARBIAS#
<24> SATA_RXP1 AJ13 SATA1RXP SATARBIAS AH7
AG14 SATABIAS L<0.5"
<24> SATA_TXN1 SATA1TXN
AF14 R426
<24> SATA_TXP1 SATA1TXP
ICH9M REV 1.0 24.9/F_4
HD Audio 10/16: R517 Change to E@ RTC

R517 *E@33_4
MXM_BIT_CLK_HDMI <18>
R513 *E@33_4 R285 *I@33_4
MXM_SDOUT_HDMI <18> HDA_BIT_CLK_HDMI <6>
R279 *I@33_4
HDA_SDOUT_HDMI <6>
R282 33_4
BIT_CLK_MDC <25> 20MIL +VCCRTC
R295 33_4 HDA_BIT_CLK_R R309 33_4 +3VPCU
B ACZ_SDOUT_MDC <25> BIT_CLK_AUDIO <25> B
HDA_SDOUT_R R294 33_4
ACZ_SDOUT_AUDIO <25>
C354 C402 C330 D19 CH500H R440 20K_6 SRTC_RST#
C344
1
*10P/50V_4 *10P/50V_4 *10P/50V_4 VCCRTC_1 D20 CH500H C391 G8
Weak integrated PD on the HDA_SDOUT pin. *10P/50V_4 20MIL
24.000 MHz is output from the ICH9M. C314 1U/6V_4 *SHORT_ PAD
2
R272 1U/10V_4
R514 *E@33_4 R516 *E@33_4
MXM_SYNC_HDMI <18> MXM_RST#_HDMI <18>
R427 *I@33_4 R308 *I@33_4 1K_4
HDA_SYNC_HDMI <6> HDA_RST#_HDMI <6>
R429 33_4 R307 33_4 R439 20K_6 RTC_RST#
ACZ_SYNC_MDC <25> ACZ_RST#_MDC <25>
HDA_SYNC_R R428 33_4 HDA_RST#_R R306 33_4
ACZ_SYNC_AUDIO <25> ACZ_RST#_AUDIO <25>
1
C458 G7
C479
1 3 RTC_N01 R271 16K_6
+5VPCU
1U/6V_4 *SHORT_ PAD
Weak integrated PD on the HDA_SYNC pins *10P/50V_4 HDA_SDIN3 R515 *E@0_4
VCCRTC_2
MXM_SDIN_HDMI <18>
2
HDA_SDIN2 R289 *I@0_4 Q28 R270
HDA_SDIN_HDMI <6>
South Bridge Strap Pin (1/3) 20MIL
MMBT3904 68.1K/F_4
2
RTC_N03
Pin Name Strap description Sampled Configuration PU/PD
1
0 = The Flash Descriptor Security will be overridden. R268
HDA_DOCK_EN/ Flash Descriptor Security This strap should only be enabled in manufacturing CN26
PWROK 1 = The security measures defined 150K/F_6
GPIO33 Override Strap in the Flash Descriptor will be in effect environments using an external pull-up resistor.
RTC_CONN
A PCI Express Lane Reversal A
2
SATALED# PWROK Internal PU
(Lanes 1-4)
ICH_TP3 HDA_SDOUT Description

TP3 XOR Chain Entrance PWROK ICH_TP3 R406 *1K_4
0 0 RSVD
<14> ICH_TP3
0 1 Enter XOR Chain PROJECT : ZY2 & ZY6
XOR Chain Entrance /PCI Express*
HDA_SDOUT
1 0 Normal opration(Default) HDA_SDOUT_R R310 *1K_4 Size Document Number Rev
Port Config 1 bit 1(Port 1-4) PWROK +3V
1A
1 1 Set PCIE port config bit 1
ICH9M HOST
5 4 3 2 1

U35D
<29> PCIE_RXN1 N29 V27 DMI_RXN0 <6>
PERN1 DMI0RXN
Direct Media Interface

<29> PCIE_RXP1 N28 V26 DMI_RXP0 <6>
C378 .1U/10V_4 PCIE_TXN1_C PERP1 DMI0RXP
NEW CARD <29> PCIE_TXN1 P27
PETN1 DMI0TXN
U29 DMI_TXN0 <6>
<29> PCIE_TXP1 C376 .1U/10V_4 PCIE_TXP1_C P26 U28
PETP1 DMI0TXP DMI_TXP0 <6>
<27> AD[0..31]
U35B L29 Y27
<23> PCIE_RXN2 PERN2 DMI1RXN DMI_RXN1 <6>
AD0 D11 F1 REQ0# L28 Y26
AD0 REQ0# REQ0# <27> <23> PCIE_RXP2 PERP2 DMI1RXP DMI_RXP1 <6>
AD1 GNT0# TV CARD C385 .1U/10V_4 PCIE_TXN2_C M27
D
AD2
C8
D9
AD1 PCI GNT0#
G4
B6 REQ1#
GNT0# <27> <23> PCIE_TXN2
C387 .1U/10V_4 PCIE_TXP2_C M26 PETN2 DMI1TXN
W29
W28
DMI_TXN1 <6> D
AD2 REQ1#/GPIO50 <23> PCIE_TXP2 PETP2 DMI1TXP DMI_TXP1 <6>
AD3 E12 A7 GNT1# T59
AD4 AD3 GNT1#/GPIO51 REQ2#
E9 F13 <28> JMB_RXN J29 AB27 DMI_RXN2 <6>
AD5 AD4 REQ2#/GPIO52 GNT2# PERN3 DMI2RXN
C9 F12 J28 AB26
PCI-Express
AD5 GNT2#/GPIO53 T46 <28> JMB_RXP PERP3 DMI2RXP DMI_RXP2 <6>
AD6 E10 E6 REQ3# CARD READER C386 .1U/10V_4 PCIE_TXN3_C K27 AA29
AD6 REQ3#/GPIO54 <28> JMB_TXN PETN3 DMI2TXN DMI_TXN2 <6>
AD7 B7 F6 GNT3# GNT3# C392 .1U/10V_4 PCIE_TXP3_C K26 AA28
AD7 GNT3#/GPIO55 <28> JMB_TXP PETP3 DMI2TXP DMI_TXP2 <6>
AD8 C7
AD9 AD8
C5 D8 CBE0# <27> <23> PCIE_RXN4 G29 AD27 DMI_RXN3 <6>
AD10 AD9 C/BE0# PERN4 DMI3RXN
G11 B4 CBE1# <27> <23> PCIE_RXP4 G28 AD26 DMI_RXP3 <6>
AD11 AD10 C/BE1# C393 .1U/10V_4 PCIE_TXN4_C PERP4 DMI3RXP
F8
AD11 C/BE2#
D6 CBE2# <27> Wireless <23> PCIE_TXN4
H27
PETN4 DMI3TXN
AC29 DMI_TXN3 <6>
AD12 F11 A5 CBE3# <27> C397 .1U/10V_4 PCIE_TXP4_C H26 AC28
AD12 C/BE3# <23> PCIE_TXP4 PETP4 DMI3TXP DMI_TXP3 <6>
AD13 E7
AD14 AD13 IRDY#
A3 D3 IRDY# <27> E29 T26 CLK_PCIE_ICH# <2>
AD15 AD14 IRDY# PAR PERN5 DMI_CLKN
D2 E3 PAR <27> E28 T25 CLK_PCIE_ICH <2>
AD16 AD15 PAR PCIRST# PERP5 DMI_CLKP
F10 R1 PCIRST# <23,27> F27
AD17 AD16 PCIRST# DEVSEL# PETN5
D5 C6 DEVSEL# <27> F26 AF29
AD18 AD17 DEVSEL# PERR# PETP5 DMI_ZCOMP DMI_IRCOMP_R R423 24.9/F_4
D10 E4 AF28 +1.5V
AD19 AD18 PERR# LOCK# DMI_IRCOMP
B3 C2 <21> GLAN_RXN C29
AD20 AD19 PLOCK# SERR# PERN6/GLAN_RXN
F7 J4 <21> GLAN_RXP C28 AC5 USBP0- <30>
AD21 AD20 SERR# STOP# C464 .1U/10V_4 GLAN_TXN_SB D27 PERP6/GLAN_RXP USBP0N
C3
AD21 STOP#
A4 STOP# <27> GLAN <21> GLAN_TXN PETN6/GLAN_TXN USBP0P
AC4 USBP0+ <30> M/B USB Port
AD22 F3 F5 TRDY# C463 .1U/10V_4 GLAN_TXP_SB D26 AD3
AD22 TRDY# TRDY# <27> <21> GLAN_TXP PETP6/GLAN_TXP USBP1N USBP1- <30>
AD23 F4 D7 FRAME# AD2 M/B USB Port
AD23 FRAME# FRAME# <27> USBP1P USBP1+ <30>
AD24 C1 SPI_CLK_R R369 *15_4 SPI_CLK D23 AC1
AD24 SPI_CLK USBP2N USBP2- <23>
AD25 G7 C14 PLT_RST-R# R367 0_4 SPI_CS0#_R R350 *15_4 SPI_CS0# D24 AC2 Wireless
AD25 PLTRST# PLT_RST# <6> SPI_CS0# USBP2P USBP2+ <23>
AD26 H7 D4 PCLK_ICH <2> SPI_CS1# F23 AA5
AD26 PCICLK SPI_CS1#/GPIO58/CLGPIO6 USBP3N USBP3- <23>
AD27 D1 R2 PCI_PME# AA4 MINI_TV
AD27 PME# PCI_PME# <27> USBP3P USBP3+ <23>
AD28 G5 SPI_MOSI_R R348 *15_4 SPI_MOSI D25 AB2
AD28 SPI_MOSI USBP4N
SPI
AD29 H6 SPI_MOSO E23 AB3
AD30 AD29 PME# internal PU 18K~42K SPI_MISO USBP4P
G1 AA1 USBP5- <22>
AD31 AD30 USBOC#0 USBP5N
H3
AD31
N4
OC0#/GPIO59 USBP5P
AA2 USBP5+ <22> BLUETOOTH
USBOC#1 N5 W5 USBP6- <29>
USBOC#2 OC1#/GPIO40 USBP6N
Interrupt I/F N6
OC2#/GPIO41 USB USBP6P
W4 USBP6+ <29> NEW CARD
<27> INTA# INTA# J5 H4 INTE# USBOC#3 P6 Y3
PIRQA# PIRQE#/GPIO2 OC3#/GPIO42 USBP7N USBP7- <29>
INTB# E1 K6 INTF# USBOC#4 M1 Y2 D/B USB Port
PIRQB# PIRQF#/GPIO3 OC4#/GPIO43 USBP7P USBP7+ <29>
C INTC# J6 F2 INTG# USBOC#5 N2 W1 USBP8- C
PIRQC# PIRQG#/GPIO4 OC5#/GPIO29 USBP8N USBP8- <29>
INTD# C4 G2 INTH# USBOC#6 M4 W2 USBP8+ D/B USB Port
PIRQD# PIRQH#/GPIO5 OC6#/GPIO30 USBP8P USBP8+ <29>
USBOC#7 M3 V2 USBP9-
OC7#/GPIO31 USBP9N USBP9- <30>
ICH9M REV 1.0 USBOC#8 N3 V3 USBP9+ Finger Printer
OC8#/GPIO44 USBP9P USBP9+ <30>
USBOC#9 N1 U5
TM & AS Y USBOC#10 P5 U4 DOCKING
OC10#/GPIO46 USBP10P USBP10+ <31>
USBOC#11 P3 U1
USBP11P
U2 USBP11+ <19> CCD
LOW COST N SB_USBBIAS AG2
USBRBIAS
AG1
USBRBIAS#
ICH9M REV 1.0
R301
22.6/F_4
L<0.5",Avoid routing next to clock/high speed signals.
TPM SPI FLASH

+3V
+3V_S5
U31
C408 SPI_MOSO R370 *15_4 SPI_MOSO_R 2 8
SO VDD
.1U/50V_6 SPI_MOSI_R 5
SI HOLD
7 C411
PCI ROUTING
TABLE IDSEL INTERUPT DEVICE
5
SPI_CLK_R 6 3 *.1U/16V_4
SCK WP
PLT_RST-R# 2
SPI_CS0#_R
REQ0# / GNT0# AD20 INTA# OZ601T
4 PLTRST# <18,21,23,28,29,32> 1 4
CE VSS
1
*W25X16VSSIG
U30 R357
3
TC7SH08FU 100K_6
B
TPM SW B
+3V
RN25
MCH_CFG_6 R564 *0_4 MCH_CFG_6_R MCH_CFG_6_R <6> STOP# 6 5
<6> MCH_CFG_6
REQ2# 7 4 REQ3#
FRAME# 8 3 INTD#
REQ1# 9 2 DEVSEL#
U44 +3V 10 1 TRDY#
South Bridge Strap Pin (2/3) 1
OFF ON
4
8.2K_10P8R
2 3
OFF ON
Pin Name Strap description Sampled Configuration PU/PD *TPM@DHN-02F-T-V-T/R
RN23
+3V
SERR# 6 5
PCI Express Port 0 = Default SPI_MOSI_H R563 *0_4 SPI_MOSI INTA# 7 4
HDA_SYNC PWROK INTE# 8 3
Config 1 bit 0 (Port 1-4) 1 = Setting bit 0 INTC# 9 2 INTG#
+3V 10 1 INTF#
PCI Express Port 0 = Setting bit 2 8.2K_10P8R

GNT2# / GPIO53 PWROK
Config 2 bit 2 (Port 5-6) 1 = Default
+3V
RN24
ESI Strap(Server Only) 0 = DMI for ESI-compatible INTH# 6 5

GNT1# / GPIO51 PWROK 7 4 IRDY#
1 = Default REQ0# 8 3 PERR#
9 2 INTB#
+3V 10 1 LOCK#
RN22
PWROK 0 = "top-block swap" mode
GNT3# / GPIO55 Top-Block Swap Override GNT3# R347 *1K_4 USBOC#6 6 5 +3V_S5 8.2K_10P8R
1 = Default USBOC#3 7 4 USBOC#0
USBOC#2 8 3 USBOC#7
A USBOC#4 9 2 USBOC#1 A
0 = INT TPM disable(Default) +3V_S5 10 1 USBOC#5
SPI_MOSI Integrated TPM Enable CLPWROK SPI_MOSI_H R329 *TPM@10K_4 +3V_S5
1 = INT TPM enable
10K_10P8R
PCI_GNT#0 SPI_CS#1 Boot Location

GNT0# Boot BIOS Selection 0 PWROK GNT0# R344 *1K_4
RN21
0 1 SPI(Default) USBOC#8 8 7
USBOC#9
USBOC#10
6 5
+3V_S5
4 3
1 0 PCI USBOC#11 2 1
SPI_CS1# /
Boot BIOS Selection 1 CLPWROK SPI_CS1# R340 *1K_4 PROJECT : ZY2 & ZY6
GPIO58 / CLGPIO6 10K_8P4R Size Document Number Rev
1 1 LPC 1A
ICH9M PCIE / PCI / USB
5 4 3 2 1

+3V_S5
D3A:(1/31) ASF issue:when iAMT is not implemented, SATA[x]GP pins if unused require
R397 2.2K_4 SMB_CLK_ME ICH8M SMBus and SMLink should be connected together to support slave mode 8.2-k to 10-k pull-up to Vcc3_3 or
Connect SMLINK0 to SMBCLK and SMLINK1 to SMBDATA (Add R474,R475 for debug use) 8.2-k to 10-k pull-down to ground
R398 2.2K_4 SMB_DATA_ME +3V +3V_S5
A1A:(9/29) no support iAMT, remove SMB_CLK_ME,SMB_DATA_ME U35C DELAY_VR_PWRGOOD need PU 2K to +3V.
R336 2.2K_4 PCLK_SMB PCLK_SMB G16 AH23 ICH_GPIO21 R437 10K_4 C472 .1U/16V_4 ZS2 PU at power side
<2,16,20,21,23,29> PCLK_SMB SMBCLK SATA0GP/GPIO21
PDAT_SMB A13 AF19 BOARD_ID2
<2,16,20,21,23,29> PDAT_SMB SMBDATA SATA1GP/GPIO19
R401 2.2K_4 PDAT_SMB ICH_GPIO60 E17 AE21 ICH_GPIO36 R316 10K_4
SATA
LINKALERT#/GPIO60/CLGPIO4 SATA4GP/GPIO36
5
GPIO
SMB
PCLK_SMB R384 *0_4 SMB_CLK_ME C17 AD20 ICH_GPIO37 R318 10K_4 1
SMLINK0 SATA5GP/GPIO37 DELAY_VR_PWRGOOD <3,6,32,35>
R332 10K_4 RI# PDAT_SMB R385 *0_4 SMB_DATA_ME B18 ICH_PWROK 4
SMLINK1 PWROK_EC
H1 14M_ICH <2> 2 PWROK_EC <32>
R338 10K_4 ICH_GPIO60 RI# CLK14 U36
F19 AF3
Clocks
CLKUSB_48 <2>
3
RI# CLK48 R420 100K_4
R331 10K_4 SYS_RST# T43 R4 P1 T66 TC7SH08FU
D SYS_RST# SUS_STAT#/LPCPD# SUSCLK D
<3> SYS_RST# G19
R399 10K_4 SMB_ALERT# SYS_RESET# SUSBR# R349 0_4
C16 SUSB# <32>
SLP_S3# SUSCR# R366 0_4
<6> PM_SYNC# M6 E16 SUSC# <32>
R342 10K_4 PCIE_WAKE# PMSYNC#/GPIO0 SLP_S4#
G17 T47
SMB_ALERT# SLP_S5#
A17
R395 8.2K_4 PM_BATLOW# SMBALERT#/GPIO11
C10 T48
S4_STATE#/GPIO26 <Checklist ver0.8>
<2> PM_STPPCI# A14
PWRBTN : 16 ms of internal debounce STP_PCI# If integrated LAN is not used LAN_RST# tie it to GND.NC serial R from RSMRST#.
SYS GPIO
E19 G20 ICH_PWROK
logic on this pin and internal PU 24K <2> PM_STPCPU# STP_CPU# PWROK If Intel LAN is used with Wake On LAN, tie LAN_RST# to RSMRST# and NC 0ohm.
L4 M2 PM_DPRSLPVR_R R327 0_4
<27,32> CLKRUN# CLKRUN# DPRSLPVR/GPIO16 PM_DPRSLPVR <6,35>
R323 *10K_4 DNBSWON#
Power MGT
PCIE_WAKE# E20 B13 PM_BATLOW#
<21,23,32> PCIE_WAKE# WAKE# BATLOW#
<27,32> SERIRQ M5 SERIRQ
THERM_ALERT# AJ23 R3
<3,18> THERM_ALERT# THRM# PWRBTN# DNBSWON# <32> CL_PWROK must not assert after PWROK asserts for IAMT.
+3V VR_PWRGD_CLKEN D21 D20 PM_LAN_ENABLE_R R364 0_4 CL_PWROK to the NB and SB should be connected to existing PWROK inputs
VRMPWRGD LAN_RST# on the NB and SB on a platform with no IAMT
R337 8.2K_4 CLKRUN# T62 A20 D22 PM_RSMRST#_R R361 *0_4 PM_RSMRST#_R
TP12 RSMRST#
R325 10K_4 SERIRQ D24 BAS316 KBSMI#_ICH AG19 R5
<32> KBSMI# GPIO1 CK_PWRGD CK_PWRGD <2>
D23 BAS316 LID591#_ICH AH21
<19,29,32> LID591# GPIO6
R430 8.2K_4 THERM_ALERT# T34 AG21 R6 R421 0_4
GPIO7 CLPWROK MPWROK <6,32>
<32> EC_SCI# A21 GPIO8
R394 10K_4 EC_SCI# T49 C12 B16 T53
LAN_PHY_PWR_CTRL/GPIO12 SLP_M#
T52 C21 ENERGY_DETECT/GPIO13
R431 10K_4 ICH_GPIO22 Rev:B ,support Intel low BOARD_ID0 AE18 F24
GPIO17 CL_CLK0 CL_CLK0 <6>
power ECR solution BOARD_ID1 K1 B19 T58
R328 10K_4 SATACLKREQ# BOARD_ID3 GPIO18 CL_CLK1
AF8 GPIO20
ICH_GPIO22 AJ22 F22
SCLOCK/GPIO22 CL_DATA0 CL_DATA0 <6>
R438 *10K_4 MCH_ICH_SYNC#_R
Controller Link
A9 C19
GPIO
T60 GPIO27 CL_DATA1 T51
OC Pin need PU R535 *0_4 D19
<25> LP_ECR GPIO28
R288 10K_4 KBSMI#_ICH SATACLKREQ# L1 C25 CL_VREF0_SB
C <2> SATACLKREQ# SATACLKREQ#/GPIO35 CL_VREF0 <Checklist ver0.8> C
CR_WAKE# AE19 A19 CL_VREF1_SB
<28> CR_WAKE# SLOAD/GPIO38 CL_VREF1 The ICH9M Controller
R287 10K_4 LID591#_ICH T36 AG22 SDATAOUT0/GPIO39 Link 1 VREF circuit is
T37 AF21 SDATAOUT1/GPIO48 CL_RST0# F21 CL_RST#0 <6>
R402 *10K_4 PM_STPPCI# Rev: B new ADD. CR_WAKE# DMI_TERM_SEL AH24 +3V required only if Intel +3V
GPIO49 CL_RST1# D18 T50 AMT is to be supported.
ICH_GPIO57 A8
R362 *10K_4 PM_STPCPU# GPIO57/CLGPIO5 VREF1 CRB connect to
MEM_LED/GPIO24 A16 T61
M7 C18 ICH_GPIO10 R335 10K_4 +3V_S5
<25> PCSPK SPKR GPIO10/SUS_PWR_ACK +3V_S5 Checklist connect to
R436 0_4 MCH_ICH_SYNC#_R AJ24 C11 ICH_GPIO14 R334 10K_4 R355 R363
<6> MCH_ICH_SYNC# MCH_SYNC# GPIO14/AC_PRESENT +3V(ZS2 follow)
ICH_TP3 B21 C20 ICH_GPIO9 R324 10K_4
<12> ICH_TP3 TP3 WOL_EN/GPIO9
MISC
T69 AH20 *3.24K/F_6 3.24K/F_6
TP9 ZS2 Default not
T67 AJ20
TPM Physical TP10 support IAMT. So CL_VREF1_SB CL_VREF0_SB
T68 AJ21
Presence for TP11 this interface
iTPM. ICH9M REV 1.0 follow CRB/Checklist
+3V_S5 PU only R389 C456 R359 C405
R403 10K_4 *453/F_4 *.1U/10V_4 453/F_4 .1U/10V_4

ICH_GPIO57
R404 *100/F_4
+3V
+3V +3V +3V +3V

C406
.1U/10V_4
R320 10K_4 CR_WAKE# ICH9M CRB connect to EC directly R283 R303 R333 R304
U29
R341 10K_4 ICH_PWROK 1 5 R388 *0_4 *10K_4 10K_4 SP@10K_4 *SP@10K_4
<35> VR_PWRGD_CK410# 2
3 4 VR_PWRGD_CLKEN BOARD_ID3 BOARD_ID2 BOARD_ID1 BOARD_ID0
B B
NC7SZ04 R356
R284 R302 R330 R305
100K_4 PM_RSMRST#_R 3 1 RSMRST# <32>
Q33 10K_4 *10K_4 *SP@10K_4 SP@10K_4
R396 MMBT3906
2
10K_4 R382 4.7K_4 +3VSUS
2
D27 Board ID ID3 ID2 ID1 ID0
3 BAV99
ZY2 0 0 0 0
1
ZY6 0 0 1 0
ZD1 INTEL FAE (08/17)
2
D26 "Add RSMRST# isolation (important!!! See
ww22 Santa Rosa MoW)"
Default stuff for Teenah(Interposer) ZY2 LOW COST 0 0 0 1
3 BAV99
chipset
ZS2 Intel FAE suggestion to add for to
protect RTC/CMOS data from corruption ZY6 LOW COST 0 0 1 1
R352 when system encounters an abnormal power
1
down sequence
South Bridge Strap Pin (3/3) 2.2K_4
ZY2 eMachine 0 1 0 0
ZY6 eMachine 0 1 1 0
Pin Name Strap description Sampled Configuration PU/PD
A A
GPIO20 Reserved PWROK
0 = Default
SPKR No Reboot PWROK PCSPK R346 *1K_4
1 = No Reboot mode +3V
DMI Termination
0 = for desktop applications PROJECT : ZY2 & ZY6
1 = for mobile applications
GPIO49 PWROK DMI_TERM_SEL R400 *1K_4 Size Document Number Rev
Voltage Internal PU 1A
ICH9M GPIO
5 4 3 2 1

Power consumption reference to Intel

642879 ICH9 Family EDS Rev 1.5
U35E
U35F AA26 H5
VSS[001] VSS[107]
2~3.456v +VCCRTC A23
VCCRTC VCC1_05[01]
A15 +1.05V AA27
VSS[002] VSS[108]
J23
B15 1.05V AA3 J26
3.6uA_G3 C460 C455 VCC1_05[02] C375 C373 VSS[003] VSS[109]
A6 C15 AA6 J27
V5REF VCC1_05[03] 1634mA VSS[004] VSS[110]
D15 AB1 AC22
.1U/10V_4 .1U/10V_4 VCC1_05[04] .1U/10V_4 .1U/10V_4 VSS[005] VSS[111]
AE1 E15 AA23 K28
V5REF_SUS VCC1_05[05] VSS[006] VSS[112]
F15 AB28 K29
VCC1_05[06] VSS[007] VSS[113]
AA24 L11 AB29 L13
D VCC1_5_B[01] VCC1_05[07] VSS[008] VSS[114] D
AA25 L12 AB4 L15
D29 SB_V5REF VCC1_5_B[02] VCC1_05[08] +1.5V_ICH_VCCDMIPLL VSS[009] VSS[115]
5V +3V 2 1 BAT54 AB24 L14 L38 1UH_6 +1.5V AB5 L2
VCC1_5_B[03] VCC1_05[09] VSS[010] VSS[116]
AB25 L16 1.5V AC17 L26
2mA C454 VCC1_5_B[04] VCC1_05[10] C471 C470 500 mA, 20% VSS[011] VSS[117]
AC24 L17 AC26 L27
R405 10_6 C137 VCC1_5_B[05] VCC1_05[11] 23mA VSS[012] VSS[118]
+5V AC25 L18 AC27 L5
.1U/10V_4 VCC1_5_B[06] VCC1_05[12] .01U/16V_4 10U/10V_8 VSS[013] VSS[119]
*1U/16V_6 AD24 M11 AC3 L7
VCC1_5_B[07] VCC1_05[13] VSS[014] VSS[120]
AD25 M18 AD1 M12
VCC1_5_B[08] VCC1_05[14] VSS[015] VSS[121]
AE25 P11 AD10 M13
D25 +5VPCU_ICH_V5REF_SUS VCC1_5_B[09] VCC1_05[15] VSS[016] VSS[122]
+3V_S5 2 1 BAT54 AE26 P18 AD12 M14
VCC1_5_B[10] VCC1_05[16] VSS[017] VSS[123]
5V AE27 T11 AD13 M15
C361 VCC1_5_B[11] VCC1_05[17] +1.05V_ICH_DMI L31 NBQ160808T-100Y-N VSS[018] VSS[124]
2mA_S0
AE28
VCC1_5_B[12] VCC1_05[18]
T18 +1.05V 1.05V AD14
VSS[019] VSS[125]
M16
+5V_S5 R315 10_6 C138 AE29 U11 AD17 M17
.1U/10V_4 VCC1_5_B[13] VCC1_05[19] C371 C374 5 Ohms @ 100 MHz , 0.7A 50mA VSS[020] VSS[126]
1mA_S3/S4/S5 *1U/16V_6 F25 U18 AD18 M23
CORE
VCC1_5_B[14] VCC1_05[20] VSS[021] VSS[127]
G25 V11 AD21 M28
VCC1_5_B[15] VCC1_05[21] 4.7U/10V_6 22U/6V_8 Checklist stuff 22U,but CRB no VSS[022] VSS[128]
H24 V12 AD28 M29
330 Ohms@ 100 MHz , 0805 VCC1_5_B[16] VCC1_05[22] VSS[023] VSS[129]
H25 V14 AD29 N11
VCC1_5_B[17] VCC1_05[23] +1.05V VSS[024] VSS[130]
J24 V16 AD4 N12
L39 VCC1_5_B[18] VCC1_05[24] VSS[025] VSS[131]
+1.5V 1 2 BLM21PG331SN1D J25 V17 AD5 N13
VCC1_5_B[19] VCC1_05[25] VSS[026] VSS[132]
K24 V18 AD6 N14
VCC1_5_B[20] VCC1_05[26] VSS[027] VSS[133]
K25 VCCP AD7 N15
+ C473 C365 C377 C389 VCC1_5_B[21] VSS[028] VSS[134]
1.5V L23
VCC1_5_B[22] VCCDMIPLL
R29
2mA
AD9
VSS[029] VSS[135]
N16
L24 C368 C366 C367 AE12 N17
646mA 220U/6_7343 22U/6V_8 22U/6V_8 2.2U/10V_6 VCC1_5_B[23] VSS[030] VSS[136]
L25 W23 AE13 N18
VCC1_5_B[24] VCC_DMI[1] .1U/10V_4 .1U/10V_4 4.7U/10V_6 VSS[031] VSS[137]
M24 Y23 AE14 N26
VCC1_5_B[25] VCC_DMI[2] VSS[032] VSS[138]
M25 AE16 N27
VCC1_5_B[26] VSS[033] VSS[139]
N23 AB23 AE17 P12
VCC1_5_B[27] V_CPU_IO[1] VSS[034] VSS[140]
N24 AC23 AE2 P13
VCC1_5_B[28] V_CPU_IO[2] VSS[035] VSS[141]
N25 AE20 P14
VCC1_5_B[29] VSS[036] VSS[142]
P24 AG29 +3V AE24 P15
VCC1_5_B[30] VCC3_3[01] VSS[037] VSS[143]
P25 VCC3_3 AE3 P16
VCC1_5_B[31] VSS[038] VSS[144]
VCCA3GP
R24 AJ6 C474 AE4 P17
VCC1_5_B[32] VCC3_3[02] 3.3V VSS[039] VSS[145]
R25 AE6 P2
VCC1_5_B[33] C476 .1U/10V_4 VSS[040] VSS[146]
R26 AC10 308mA AE9 P23
VCC1_5_B[34] VCC3_3[07] VSS[041] VSS[147]
R27 AF13 P28
VCC1_5_B[35] C350 .1U/10V_4 VSS[042] VSS[148]
T24 AD19 AF16 P29
VCC1_5_B[36] VCC3_3[03] VSS[043] VSS[149]
T27
VCC1_5_B[37] VCC3_3[04]
AF20 ZS2 Default not AF18
VSS[044] VSS[150]
P4
T28 AG24 .1U/10V_4 AF22 P7
VCC1_5_B[38]
VCCP_CORE
VCC3_3[05] support INT HDMI VSS[045] VSS[151]
C T29 AC20 AH26 R11 C
VCC1_5_B[39] VCC3_3[06] VSS[046] VSS[152]
U24
VCC1_5_B[40] interface AF26
VSS[047] VSS[153]
R12
U25 B9 AF27 R13
VCC1_5_B[41] VCC3_3[08] VSS[048] VSS[154]
V24 F9 AF5 R14
VCC1_5_B[42] VCC3_3[09] C401 C395 C381 Impact ICH9M VCCHDA and VSS[049] VSS[155]
V25 G3 AF7 R15
VCC1_5_B[43] VCC3_3[10] R290 *E@0_6 +3V VCCSUSHDA supply 1.5V/3.3V VSS[050] VSS[156]
U23 G6 AF9 R16
VCC1_5_B[44] VCC3_3[11] .1U/10V_4 .1U/10V_4 .1U/10V_4 VSS[051] VSS[157]
W24 J2 AG13 R17
VCC1_5_B[45] VCC3_3[12] C351 R291 I@0_6 Support INT HDMI HDA VSS[052] VSS[158]
W25 J7 +1.5V 1.5V / 3.3V AG16 R18
PCI
VCC1_5_B[46] VCC3_3[13] interface. These power VSS[053] VSS[159]
1.5V K23
VCC1_5_B[47] VCC3_3[14]
K7
11mA only support 1.5V.Device
AG18
VSS[054] VSS[160]
R28
Y24 .1U/10V_4 AG20 T12
47mA VCC1_5_B[48] +3V_HDA_IO_ICH
must to meet. VSS[055] VSS[161]
Y25 AJ4 AG23 T13
VCC1_5_B[49] VCCHDA VSS[056] VSS[162]
AG3 T14
L40 10UH_8 +1.5V_APLL_ICH +3V_VCCSUSHDA R292 *E@0_6 NOTE: VSS[057] VSS[163]
+1.5V AJ19 AJ3 +3V_S5 AG6 T15
VCCSATAPLL VCCSUSHDA If (G)MCH's HD Audio signals are connected to ICH9M VSS[058] VSS[164]
AG9 T16
C480 C478 TP_VCCSUS1_05_ICH_1 C352 R293 I@0_6 for iHDMI, VCCHDA and VCCSUSHDA on ICH9M should be VSS[059] VSS[165]
AC16 AC8 T42 +1.5V_S5 AH12 T17
VCC1_5_A[01] VCCSUS1_05[1] TP_VCCSUS1_05_ICH_2 only on 1.5V. These power pins on ICH9M can be VSS[060] VSS[166]
AD15 F17 T45 AH14 T23
10U/10V_8 1U/6V_4 VCC1_5_A[02] VCCSUS1_05[2] .1U/10V_4 supplied with 3.3V if and only if (G)MCH's HDA is not VSS[061] VSS[167]
AD16 AH17 B26
VCC1_5_A[03] VSS[062] VSS[168]
ARX
AE15 AD8 TP_VCCSUS1_5_ICH_1 connected to ICH9M. Consequently, only 1.5V AH19 U12
VCC1_5_A[04] VCCSUS1_5[1] T41 1.5V / 3.3V audio/modem codecs can be used on the platform. VSS[063] VSS[169]
AF15 AH2 U13
VCC1_5_A[05] VCCSUS1_5_INT_ICH 11mA_S0 , 1mA_S3/S4/S5 VSS[064] VSS[170]
AG15 F18 AH22 U14
VCC1_5_A[06] VCCSUS1_5[2] VSS[065] VSS[171]
AH15 AH25 U15
VCC1_5_A[07] C380 VSS[066] VSS[172]
AJ15 AH28 U16
C362 VCC1_5_A[08] VSS[067] VSS[173]
VCC1_5_A A18 VCCSUS1_05 power by VCC1_05 in S0 / VCCSUS3_3 in S3/S4/S5 AH5 U17
VCCSUS3_3[01] .1U/10V_4 VSS[068] VSS[174]
AC11 D16 AH8 AD23
VCCPSUS
1.5V 1U/6V_4 VCC1_5_A[09] VCCSUS3_3[02] VCCSUS1_5 power by VCC1_5_A in S0 / VCCSUS3_3 in S3/S4/S5 VSS[069] VSS[175]
AD11 D17 AJ12 U26
1342mA AE11 E22 AJ14 U27
ATX
AF11 AJ17 U3
VCC1_5_A[12] VSS[072] VSS[178]
AG10 AJ8 V1
VCC1_5_A[13] VSS[073] VSS[179]
AG11
VCC1_5_A[14] VCCSUS3_3[05]
AF1 +3V_S5 3.3V B11
VSS[074] VSS[180]
V13
AH10 B14 V15
C363 VCC1_5_A[15] 212mA_S0 , 53mA_S3/S4/S5 VSS[075] VSS[181]
AJ10 T1 B17 V23
T2 B2 V28
1U/6V_4 VCCSUS3_3[07] VSS[077] VSS[183]
AC9 T3 B20 V29
VCC1_5_A[17] VCCSUS3_3[08] C370 C372 C369 VSS[078] VSS[184]
T4 B23 V4
VCCSUS3_3[09] VSS[079] VSS[185]
AC18 T5 B5 V5
VCC1_5_A[18] VCCSUS3_3[10] .022U/10V_4 .022U/16V_4 .1U/10V_4 VSS[080] VSS[186]
AC19 T6 B8 W26
U6 C26 W27
VCCSUS3_3[12] Check list: VSS[082] VSS[188]
1.5V AC21 U7 C27 W3
VCCPUSB
B VCC1_5_A[20] VCCSUS3_3[13] 0.1U for Pin AF1 VSS[083] VSS[189] B

V6 E11 Y1
11mA VCCSUS3_3[14] VSS[084] VSS[190]
G10 V7 E14 Y28
G9 W6 E18 Y29
W7 E2 Y4
VCCSUS3_3[17] VSS[087] VSS[193]
AC12 Y6 E21 Y5
C364 VCC1_5_A[23] VCCSUS3_3[18] VSS[088] VSS[194]
AC13 Y7 E24 AG28
AC14 T7 E5 AH6
.1U/10V_4 VCC1_5_A[25] VCCSUS3_3[20] VSS[090] VSS[196]
E8 AF2
VCCCL1_05_INT_ICH VSS[091] VSS[197]
AJ5 G22 F16 B25
VCCUSBPLL VCCCL1_05 VSS[092] VSS[198]
F28
VCCCL1_5_INT_ICH C390 VSS[093]
AA7
VCC1_5_A[26] VCCCL1_5
G23 VCCCL1_05 power by VCC1_05_A in S0 F29
VSS[094] VSS_NCTF[01]
A1
USB CORE
AB6 G12 A2
C388 VCC1_5_A[27] C383 C382 .1U/10V_4 VCCCL1_5 power by VCC1_5_A in S0 VSS[095] VSS_NCTF[02]
AB7 A24 G14 A28
VCC1_5_A[28] VCCCL3_3[1] VSS[096] VSS_NCTF[03]
AC6 B24 G18 A29
.1U/10V_4 VCC1_5_A[29] VCCCL3_3[2] *1U/10V_4 *.1U/10V_4 VSS[097] VSS_NCTF[04]
1.05V , Powered by VCC1_05 in S0 AC7 G21 AH1
VCC1_5_A[30] VSS[098] VSS_NCTF[05]
G24 AH29
A10 G26 AJ1
C400 .1U/10V_4 VCCLAN1_05_INT_ICH VCCLAN1_05[1] VSS[100] VSS_NCTF[07]
A11 G27 AJ2
VCCLAN1_05[2] VSS[101] VSS_NCTF[08]
G8 AJ28
A12 H2 AJ29
R392 0_6 +3VM_VCCPAUX VCCLAN3_3[1] VSS[103] VSS_NCTF[10]
+3V B12
VCCLAN3_3[2] +3V 3.3V H23
B1
H28 B29
If use SB MAC for LAN function. C459 19mA_S0 , 73mA_S3/S4/S5 VSS[105] VSS_NCTF[12]
3.3V A27 H29
And support wake up need VCCGLANPLL VSS[106]
19mA_S0 ,
GLAN POWER
connect to relation power. .1U/10V_4 D28 ICH9M REV 1.0

VCCGLAN1_5[1] If use SB MAC for LAN function. And
78mA_S3/S4/S5 D29
VCCGLAN1_5[2] support wake up need connect to
E26
L35 1UH_6 +1.5V_ICH_GLANPLL_R VCCGLAN1_5[3] relation power.
+1.5V E27
VCCGLAN1_5[4]
1.5V C407 A26
C404 VCCGLAN3_3
23mA 10U/10V_8 2.2U/10V_6 ICH9M REV 1.0
+1.5V
A 1.5V C465 A
80mA 4.7U/10V_6
+3V
3.3V
1mA
PROJECT : ZY2 & ZY6
Rev
1A
ICH9 POWER
5 4 3 2 1

+VDR_VTT
+VDR_VREF +VDR_SUS +VDR_SUS +VDR_VTT +VDR_VREF +VDR_SUS +VDR_SUS
CN24 CN25 M_CS#2 RP21 1 2 D2@56X2_4 M2_CLK#0 RN31 2 1 D2@0_4P2R M_CLK#0
1 2 1 2 M_ODT2 3 4 M2_CLK0 4 3 M_CLK0
VREF VSS46 M_A_DQ4 M_A_BS0 RP43 1 VREF VSS46
3 4 2 D2@56X2_4 3 4 M_B_DQ4 M2_CLK#1 RN29 2 1 D2@0_4P2R M_CLK#1
M_A_DQ0 VSS47 DQ4 M_A_DQ5 M_A_A10 M_B_DQ0 VSS47 DQ4 M_B_DQ5 M_B_A8 RP28 1
5 6 3 4 5 6 2 D2@56X2_4 M2_CLK1 4 3 M_CLK1
M_A_DQ1 DQ0 DQ5 M_B_DQ1 DQ0 DQ5 M_B_A5
7 8 7 8 3 4
DQ1 VSS15 M_A_DM0 M_A_A2 RP40 1 DQ1 VSS15
9 10 2 D2@56X2_4 9 10 M_B_DM0 M2_CLK#2 RN20 4 3 D2@0_4P2R M_CLK#2
M_A_DQS#0 VSS37 DM0 M_A_A4 M_B_DQS#0 VSS37 DM0 M_B_A6 RP24 1
11 12 3 4 11 12 2 D2@56X2_4 M2_CLK2 2 1 M_CLK2
M_A_DQS0 DQS#0 VSS5 M_A_DQ6 M_B_DQS0 DQS#0 VSS5 M_B_DQ6 M_B_A4 M2_CLK#3 RN19
13 14 13 14 3 4 4 3 D2@0_4P2R M_CLK#3
DQS0 DQ6 M_A_DQ7 M_A_A5 RP45 1 DQS0 DQ6
15 16 2 D2@56X2_4 15 16 M_B_DQ7 M2_CLK3 2 1 M_CLK3
M_A_DQ2 VSS48 DQ7 M_A_A8 M_B_DQ2 VSS48 DQ7 M_B_A11 RP25 1
17 18 3 4 17 18 2 D2@56X2_4
D
M_A_DQ3 DQ2 VSS16 M_A_DQ12 M_B_DQ3 DQ2 VSS16 M_B_DQ12 M_B_A7 D
19 20 19 20 3 4
DQ3 DQ12 M_A_DQ13 M_A_A6 RP38 1 DQ3 DQ12
21
VSS38 DQ13
22 2 D2@56X2_4 21
VSS38 DQ13
22 M_B_DQ13
M_A_DQ8 23 24 M_A_A7 3 4 M_B_DQ8 23 24 M_B_A12 RP29 1 2 D2@56X2_4
M_A_DQ9 DQ8 VSS17 M_A_DM1 M_B_DQ9 DQ8 VSS17 M_B_DM1 M_B_A9
25 26 25 26 3 4
DQ9 DM1 M_A_A1 RP44 1 DQ9 DM1
27
VSS49 VSS53
28 2 D2@56X2_4 27
VSS49 VSS53
28
M_A_DQS#1 29 30 M2_CLK0 M_A_A3 3 4 M_B_DQS#1 29 30 M2_CLK2 M_B_A2 RP23 1 2 D2@56X2_4
M_A_DQS1 DQS#1 CK0 M2_CLK#0 M_B_DQS1 DQS#1 CK0 M2_CLK#2 M_B_A0
31 32 31 32 3 4
DQS1 CK0# M_A_A9 RP46 1 DQS1 CK0#
33 34 2 D2@56X2_4 33 34
M_A_DQ10 VSS39 VSS41 M_A_DQ14 M_A_A12 M_B_DQ10 VSS39 VSS41 M_B_DQ14 M_B_A3 RP32 1
35 DQ10 DQ14 36 3 4 35 DQ10 DQ14 36 2 D2@56X2_4
M_A_DQ11 37 38 M_A_DQ15 M_B_DQ11 37 38 M_B_DQ15 M_B_A1 3 4
DQ11 DQ15 M_ODT0 RP36 1 DQ11 DQ15
39 40 2 D2@56X2_4 39 40
VSS50 VSS54 M_ODT1 VSS50 VSS54 M_B_A10 RP31 1
3 4 2 D2@56X2_4 <6,17> PM_EXTTS#1 PM_EXTTS#1
41 42 41 42 M_B_BS0 3 4
M_A_DQ16 VSS18 VSS20 M_A_DQ20 M_A_RAS# RP37 1 VSS18 VSS20
43 DQ16 DQ20 44 2 D2@56X2_4 M_B_DQ16 43 DQ16 DQ20 44 M_B_DQ20 <6,17> PM_EXTTS#0 PM_EXTTS#0
M_A_DQ17 45 46 M_A_DQ21 M_CS#0 3 4 M_B_DQ17 45 46 M_B_DQ21 M_B_BS2 RP34 1 2 D2@56X2_4
DQ17 DQ21 DQ17 DQ21 M_CKE2
47 VSS1 VSS6 48 47 VSS1 VSS6 48 3 4
M_A_DQS#2 49 50 PM_EXTTS#0 M_A_BS2 RP47 1 2 D2@56X2_4 M_B_DQS#2 49 50 PM_EXTTS#1 M_CS#[3:0]
DQS#2 NC3 DQS#2 NC3 <6,17> M_CS#[3:0]
M_A_DQS2 51 52 M_A_DM2 M_CKE0 3 4 M_B_DQS2 51 52 M_B_DM2 M_B_A13 RP30 1 2 D2@56X2_4
DQS2 DM2 DQS2 DM2 M_CS#3 M_ODT[3:0]
53 54 53 54 3 4 <6,17> M_ODT[3:0]
PC4800 DDR2 SDRAM
PC4800 DDR2 SDRAM

M_A_DQ18 VSS19 VSS21 M_A_DQ22 M_A_CAS# RP42 1 VSS19 VSS21
55 56 2 D2@56X2_4 M_B_DQ18 55 56 M_B_DQ22
M_A_DQ19 DQ18 DQ22 M_A_DQ23 M_A_WE# M_B_DQ19 DQ18 DQ22 M_B_DQ23 M_B_BS1 RP22 1 M_CKE[3:0]
57 DQ19 DQ23 58 3 4 57 DQ19 DQ23 58 2 D2@56X2_4 <6,17> M_CKE[3:0]
59 60 59 60 M_B_RAS# 3 4
M_A_DQ24 VSS22 VSS24 M_A_DQ28 M_A_BS1 RP39 1 VSS22 VSS24 M_CLK#[3:0]
61 62 2 D2@56X2_4 M_B_DQ24 61 62 M_B_DQ28
<6,17> M_CLK#[3:0]
M_A_DQ25 DQ24 DQ28 M_A_DQ29 M_A_A0 M_B_DQ25 DQ24 DQ28 M_B_DQ29 M_CKE3 RP26 1
63 DQ25 DQ29 64 3 4 63 DQ25 DQ29 64 2 D2@56X2_4
65 66 65 66 M_B_A14 3 4 M_CLK[3:0]
SO-DIMM (200P)
SO-DIMM (200P)
VSS23 VSS25 VSS23 VSS25 <6,17> M_CLK[3:0]
M_A_DM3 67 68 M_A_DQS#3 M_CKE1 RP35 1 2 D2@56X2_4 M_B_DM3 67 68 M_B_DQS#3
DM3 DQS#3 M_A_DQS3 M_A_A14 DM3 DQS#3 M_B_DQS3 M_B_CAS# RP33 1
69 NC4 DQS3 70 3 4 69 NC4 DQS3 70 2 D2@56X2_4
71 72 71 72 M_B_WE# 3 4
M_A_DQ26 VSS9 VSS10 M_A_DQ30 M_CS#1 RP41 1 VSS9 VSS10
73 DQ26 DQ30 74 2 D2@56X2_4 M_B_DQ26 73 DQ26 DQ30 74 M_B_DQ30
<8,17> M_A_CAS#
M_A_CAS#
M_A_DQ27 75 76 M_A_DQ31 M_A_A13 3 4 M_B_DQ27 75 76 M_B_DQ31 M_ODT3 R269 D2@56_4
DQ27 DQ31 DQ27 DQ31 M_A_RAS#
77 VSS4 VSS8 78 77 VSS4 VSS8 78 <8,17> M_A_RAS#
C M_CKE0 79 80 M_CKE1 M_A_A11 R275 D2@56_4 M_CKE2 79 80 M_CKE3 C
CKE0 CKE1 CKE0 CKE1 M_A_WE#
81 VDD7 VDD8 82 81 VDD7 VDD8 82 <8,17> M_A_WE#
83 84 83 84 +VDR_VTT
M_A_BS2 NC1 A15 M_A_A14 M_B_BS2 NC1 A15 M_B_A14 M_A_BS[2:0]
85 A16_BA2 A14 86 85 A16_BA2 A14 86 <8,17> M_A_BS[2:0]
87 88 +VDR_VTT 87 88 C309 D2@.1U/16V_4
M_A_A12 VDD9 VDD11 M_A_A11 M_B_A12 VDD9 VDD11 M_B_A11 C301 D2@.1U/16V_4 M_A_DM[7:0]
89 A12 A11 90 89 A12 A11 90 <8,17> M_A_DM[7:0]
M_A_A9 91 92 M_A_A7 C318 D2@.1U/16V_4 M_B_A9 91 92 M_B_A7 C303 D2@.1U/16V_4
M_A_A8 A9 A7 M_A_A6 C335 D2@.1U/16V_4 M_B_A8 A9 A7 M_B_A6 C311 D2@.1U/16V_4 M_A_DQS#[7:0]
93 94 93 94 <8,17> M_A_DQS#[7:0]
A8 A6 C319 D2@.1U/16V_4 A8 A6 C302 D2@.1U/16V_4
95 96 95 96
M_A_A5 VDD5 VDD4 M_A_A4 C341 D2@.1U/16V_4 M_B_A5 VDD5 VDD4 M_B_A4 C306 D2@.1U/16V_4 M_A_DQS[7:0]
97 98 97 98 <8,17> M_A_DQS[7:0]
M_A_A3 A5 A4 M_A_A2 C340 D2@.1U/16V_4 M_B_A3 A5 A4 M_B_A2 C307 D2@.1U/16V_4
99 100 99 100
M_A_A1 A3 A2 M_A_A0 C339 D2@.1U/16V_4 M_B_A1 A3 A2 M_B_A0 C315 D2@.1U/16V_4 M_A_A[14:0]
101 102 101 102 <8,17> M_A_A[14:0]
A1 A0 C337 D2@.1U/16V_4 A1 A0 C312 D2@.1U/16V_4
103 104 103 104
M_A_A10 VDD10 VDD12 M_A_BS1 C342 D2@.1U/16V_4 M_B_A10 VDD10 VDD12 M_B_BS1 C304 D2@.1U/16V_4 M_A_DQ[63:0]
105 106 105 106 <8,17> M_A_DQ[63:0]
M_A_BS0 A10/AP BA1 M_A_RAS# C332 D2@.1U/16V_4 M_B_BS0 A10/AP BA1 M_B_RAS# C313 D2@.1U/16V_4
107 108 107 108
M_A_WE# BA0 RAS# M_CS#0 C333 D2@.1U/16V_4 M_B_WE# BA0 RAS# M_CS#2 C305 D2@.1U/16V_4
109 110 109 110
WE# S0# C334 D2@.1U/16V_4 WE# S0# C310 D2@.1U/16V_4
111 112 111 112
M_A_CAS# VDD2 VDD1 M_ODT0 C338 D2@.1U/16V_4 M_B_CAS# VDD2 VDD1 M_ODT2 C308 D2@.1U/16V_4 M_B_CAS#
113 114 113 114 <8,17> M_B_CAS#
M_CS#1 CAS# ODT0 M_A_A13 C331 D2@.1U/16V_4 M_CS#3 CAS# ODT0 M_B_A13
115 116 115 116
S1# A13 C336 D2@.1U/16V_4 S1# A13 M_B_RAS#
117 118 117 118 <8,17> M_B_RAS#
M_ODT1 VDD3 VDD6 M_ODT3 VDD3 VDD6
119 120 119 120
ODT1 NC2 ODT1 NC2 M_B_WE#
121 122 121 122 <8,17> M_B_WE#
M_A_DQ32 VSS11 VSS12 M_A_DQ36 M_B_DQ32 VSS11 VSS12 M_B_DQ36
123 124 123 124
M_A_DQ33 DQ32 DQ36 M_A_DQ37 M_B_DQ33 DQ32 DQ36 M_B_DQ37 SP@:DDR2 2.2U M_B_BS[2:0]
125 126 125 126 <8,17> M_B_BS[2:0]
DQ33 DQ37 DQ33 DQ37
127 128 127 128 DDR3 10U
M_A_DQS#4 VSS26 VSS28 M_A_DM4 +VDR_VREF M_B_DQS#4 VSS26 VSS28 M_B_DM4 +VDR_SUS M_B_DM[7:0]
129 130 129 130 <8,17> M_B_DM[7:0]
M_A_DQS4 DQS#4 DM4 M_B_DQS4 DQS#4 DM4
131 132 131 132
DQS4 VSS42 M_A_DQ38 C316 D2@.1U/16V_4 DQS4 VSS42 M_B_DQ38 C511 SP@2.2U/10V_6 M_B_DQS#[7:0]
133 134 133 134 <8,17> M_B_DQS#[7:0]
M_A_DQ34 VSS2 DQ38 M_A_DQ39 M_B_DQ34 VSS2 DQ38 M_B_DQ39 C506 .1U/16V_4
135 136 135 136
M_A_DQ35 DQ34 DQ39 C504 2.2U/10V_6 M_B_DQ35 DQ34 DQ39 C507 .1U/16V_4 M_B_DQS[7:0]
137 138 137 138 <8,17> M_B_DQS[7:0]
DQ35 VSS55 M_A_DQ44 DQ35 VSS55 M_B_DQ44 C508 .1U/16V_4
139 140 139 140
M_A_DQ40 VSS27 DQ44 M_A_DQ45 M_B_DQ40 VSS27 DQ44 M_B_DQ45 C503 .1U/16V_4 M_B_A[14:0]
141 142 141 142 <8,17> M_B_A[14:0]
B
M_A_DQ41 DQ40 DQ45 M_B_DQ41 DQ40 DQ45 B
143 144 143 144
DQ41 VSS43 M_A_DQS#5 DQ41 VSS43 M_B_DQS#5 M_B_DQ[63:0]
145 146 145 146 <8,17> M_B_DQ[63:0]
M_A_DM5 VSS29 DQS#5 M_A_DQS5 M_B_DM5 VSS29 DQS#5 M_B_DQS5
147 148 147 148
DM5 DQS5 +VDR_SUS DM5 DQS5
149 150 149 150
151 152 151 152
M_A_DQ43 DQ42 DQ46 M_A_DQ47 C357 D2@330U/2.5V_7 M_B_DQ43 DQ42 DQ46 M_B_DQ47 +3V
153 154 153 154
DQ43 DQ47 DQ43 DQ47
+
155 156 155 156

M_A_DQ48 VSS40 VSS44 M_A_DQ52 C323 D2@2.2U/10V_6 M_B_DQ48 VSS40 VSS44 M_B_DQ52 C502 .1U/16V_4
157 158 157 158
M_A_DQ49 DQ48 DQ52 M_A_DQ53 C324 D2@2.2U/10V_6 M_B_DQ49 DQ48 DQ52 M_B_DQ53
159 160 159 160
DQ49 DQ53 C321 D2@2.2U/10V_6 DQ49 DQ53 C505 1U/10V_4
161 162 161 162
VSS52 VSS57 M2_CLK1 C322 D2@2.2U/10V_6 VSS52 VSS57 M2_CLK3
163 164 163 164
NCTEST CK1 M2_CLK#1 C509 SP@2.2U/10V_6 NCTEST CK1 M2_CLK#3
165 166 165 166
M_A_DQS#6 VSS30 CK1# M_B_DQS#6 VSS30 CK1# +3V
167 168 167 168
M_A_DQS6 DQS#6 VSS45 M_A_DM6 SP@:DDR2 2.2U M_B_DQS6 DQS#6 VSS45 M_B_DM6
169 170 169 170
DQS6 DM6 DQS6 DM6
171 172 DDR3 10U 171 172
173 174 173 174
M_A_DQ51 DQ50 DQ54 M_A_DQ55 M_B_DQ51 DQ50 DQ54 M_B_DQ55
175 176 175 176
DQ51 DQ55 DQ51 DQ55 R353 R354
177 178 177 178
179 180 179 180
DQ56 DQ60 DQ56 DQ60
2
M_A_DQ57 181 182 M_A_DQ61 M_B_DQ57 181 182 M_B_DQ61 10K_4 10K_4
DQ57 DQ61 DQ57 DQ61
183 184 183 184
M_A_DM7 VSS3 VSS7 M_A_DQS#7 M_B_DM7 VSS3 VSS7 M_B_DQS#7
185 186 185 186 <2,14,20,21,23,29> PDAT_SMB 3 1 SDA_DDR <17>
DM7 DQS#7 M_A_DQS7 DM7 DQS#7 M_B_DQS7
187 188 187 188
M_A_DQ58 VSS34 DQS7 M_B_DQ58 VSS34 DQS7 Q31
189 190 189 190
M_A_DQ59 DQ58 VSS36 M_A_DQ62 M_B_DQ59 DQ58 VSS36 M_B_DQ62
191 192 191 192
DQ59 DQ62 M_A_DQ63 DQ59 DQ62 M_B_DQ63 +3V RHU002N06
193 194 193 194
SDA_DDR VSS14 DQ63 SDA_DDR VSS14 DQ63
195 196 195 196
SCL_DDR SDA VSS13 A_SA0 SCL_DDR SDA VSS13 B_SA0
197 198 197 198
SCL SA0 A_SA1 SCL SA0 B_SA1
199 200 199 200
VDD(SPD) SA1 VDD(SPD) SA1
2
+3V +3V
D2@DDR2_DIMM_H5.2_Stand D2@DDR2_DIMM_H9.2_Stand
A
<2,14,20,21,23,29> PCLK_SMB 3 1 SCL_DDR <17> A
SMbus address A0 SMbus address A2 Q30
SO-DIMM0 NOTE:Place one cap close to every 2 pull-up resistors
terminated to +SMDDR_VTERM
SO-DIMM1 RHU002N06
+3V
<17> A_SA0 R522 D2@10K_4 <17> B_SA1 R273 D2@10K_4 Quanta Computer Inc.
<17> A_SA1 R521 D2@10K_4 <17> B_SA0 R274 D2@10K_4
PROJECT : ZY2 & ZY6
Close to DIMM0 10/16: Change to D2@ Close to DIMM1 1A
DDRII SO-DIMM
5 4 3 2 1

+VDR_SUS +VDR_SUS +VDR_SUS CN11 +VDR_SUS
CN13 75
81
VDD1 VDD2 76
82
FOR DDR3
VDD3 VDD4
75 VDD1 VDD2 76 87 VDD5 VDD6 88
81 VDD3 VDD4 82 93 VDD7 VDD8 94
+VDR_VREF 87 88 +VDR_VREF +VDR_VREF 99 100 +VDR_VREF M3_CLK0 RN28 2 1 *D3@0_4P2R M_CLK0
VDD5 VDD6 VDD9 VDD10 M3_CLK#0 M_CLK#0
93 VDD7 VDD8 94 105 VDD11 VDD12 106 4 3
99 100 111 112 M3_CLK1 RN30 2 1 *D3@0_4P2R M_CLK1
+3V VDD9 VDD10 +3V VDD13 VDD14 M3_CLK#1 M_CLK#1
105 VDD11 VDD12 106 117 VDD15 VDD16 118 4 3
111 VDD13 VDD14 112 123 VDD17 VDD18 124
117 118 1 126 M3_CLK2 RN26 2 1 *D3@0_4P2R M_CLK2
VDD15 VDD16 VREF_DQ VREF_CA M3_CLK#2 M_CLK#2
123 VDD17 VDD18 124 199 VDD(SPD) 4 3
1 126 M3_CLK3 RN27 2 1 *D3@0_4P2R M_CLK3
VREF_DQ VREF_CA M_B_DQ0 M_B_DQ4 M3_CLK#3 M_CLK#3
D 199 VDD(SPD) 5 DQ0 DQ4 4 4 3 D
M_B_DQ1 7 6 M_B_DQ5
M_A_DQ0 M_A_DQ4 M_B_DQ2 DQ1 DQ5 M_B_DQ6
5 DQ0 DQ4 4 15 DQ2 DQ6 16
M_A_DQ1 7 6 M_A_DQ5 M_B_DQ3 17 18 M_B_DQ7
M_A_DQ2 DQ1 DQ5 M_A_DQ6 M_B_DM0 DQ3 DQ7 M_B_DQS#0
15 DQ2 DQ6 16 11 DM0 DQS#0 10
M_A_DQ3 17 18 M_A_DQ7 12 M_B_DQS0
M_A_DM0 DQ3 DQ7 M_A_DQS#0 M_B_DQ8 DQS0
11 DM0 DQS#0 10 21 DQ8
12 M_A_DQS0 M_B_DQ9 23 22 M_B_DQ12
M_A_DQ8 DQS0 M_B_DQ10 DQ9 DQ12 M_B_DQ13
21 DQ8 33 DQ10 DQ13 24
M_A_DQ10 DQ9 DQ12 M_A_DQ13 M_B_DQS#1 DQ11 DQ14 M_B_DQ15
33 DQ10 DQ13 24 27 DQS#1 DQ15 36
M_A_DQ11 35 34 M_A_DQ14 M_B_DQS1 29 28 M_B_DM1
M_A_DQS#1 DQ11 DQ14 M_A_DQ15 DQS1 DM1 PM_EXTTS#1
27 DQS#1 DQ15 36 <6,16> PM_EXTTS#1
M_A_DQS1 29 28 M_A_DM1 M_B_DQ16 39 40 M_B_DQ20
DQS1 DM1 M_B_DQ17 DQ16 DQ20 M_B_DQ21 PM_EXTTS#0
41 DQ17 DQ21 42 <6,16> PM_EXTTS#0
M_A_DQ17 DQ16 DQ20 M_A_DQ21 M_B_DQ19 DQ18 DQ22 M_B_DQ23
41 DQ17 DQ21 42 53 DQ19 DQ23 52
M_A_DQ18 51 50 M_A_DQ22 M_B_DQS#2 45 46 M_B_DM2 M_CS#[3:0]
DQ18 DQ22 DQS#2 DM2 <6,16> M_CS#[3:0]
M_A_DQ19 53 52 M_A_DQ23 M_B_DQS2 47
M_A_DQS#2 DQ19 DQ23 M_A_DM2 DQS2 M_B_DQ28 M_ODT[3:0]
45 DQS#2 DM2 46 DQ28 56 <6,16> M_ODT[3:0]
M_A_DQS2 47 M_B_DQ24 57 58 M_B_DQ29
DQS2 M_A_DQ28 M_B_DQ25 DQ24 DQ29 M_B_DQ30 M_CKE[3:0]
DQ28 56 59 DQ25 DQ30 68 <6,16> M_CKE[3:0]
M_A_DQ25 DQ24 DQ29 M_A_DQ30 M_B_DQ27 DQ26 DQ31 M_B_DQS#3 M_CLK#[3:0]
59 DQ25 DQ30 68 69 DQ27 DQS#3 62 <6,16> M_CLK#[3:0]
M_A_DQ26 67 70 M_A_DQ31 M_B_DM3 63 64 M_B_DQS3
M_A_DQ27 DQ26 DQ31 M_A_DQS#3 DM3 DQS3 M_CLK[3:0]
69 DQ27 DQS#3 62 <6,16> M_CLK[3:0]
M_A_DM3 63 64 M_A_DQS3 M_CKE2 73 74 M_CKE3
DM3 DQS3 CKE0 CKE1
M_CKE0 73 74 M_CKE1 M_B_BS2 79 108 M_B_BS1
CKE0 CKE1 M_B_BS0 BA2 BA1
109 BA0
M_A_BS2 79 108 M_A_BS1 80 M_B_A14
M_A_BS0 BA2 BA1 M_B_A12 A14 M_B_A11 M_A_CAS#
109 BA0 83 A12/BC# A11 84 <8,16> M_A_CAS#
80 M_A_A14 M_B_A9 85 86 M_B_A7
M_A_A12 A14 M_A_A11 M_B_A8 A9 A7 M_B_A6 M_A_RAS#
83 A12/BC# A11 84 89 A8 A6 90 <8,16> M_A_RAS#
C M_A_A9 M_A_A7 M_B_A5 M_B_A4 C
85 A9 A7 86 91 A5 A4 92
M_A_A8 89 90 M_A_A6 M_B_A3 95 96 M_B_A2 M_A_WE#
A8 A6 A3 A2 <8,16> M_A_WE#
M_A_A5 91 92 M_A_A4 M_B_A1 97 98 M_B_A0
M_A_A3 A5 A4 M_A_A2 M_B_A10 A1 A0 M_A_BS[2:0]
95 A3 A2 96 107 A10/AP <8,16> M_A_BS[2:0]
M_A_A1 97 98 M_A_A0 M_B_A13 119 30
A1 A0 +VDR_SUS A13 RESET# DDR3_DRAMRST# <6> M_A_DM[7:0]
M_A_A10 107 A10/AP <8,16> M_A_DM[7:0]
M_A_A13 119 30 DDR3_DRAMRST# M3_CLK2 101 102 M3_CLK3
A13 RESET# CK0 CK1
SO-DIMM (204P)
C489 *D3@.1U/16V_4 M3_CLK#2 103 104 M3_CLK#3 M_A_DQS#[7:0]
CK0# CK1# <8,16> M_A_DQS#[7:0]
M3_CLK0 101 102 M3_CLK1 C488 *D3@.1U/16V_4
CK0 CK1
SO-DIMM (204P)
M3_CLK#0 M3_CLK#1 C487 *D3@.1U/16V_4 M_CS#3 M_CS#2 M_A_DQS[7:0]
DDR3 SDRAM
103 CK0# CK1# 104 121 CS1# CS#0 114 <8,16> M_A_DQS[7:0]
C486 *D3@.1U/16V_4
M_CS#1 M_CS#0 M_B_WE# M_B_RAS# M_A_A[14:0]
DDR3 SDRAM
121 CS1# CS#0 114 113 WE# RAS# 110 <8,16> M_A_A[14:0]
M_B_CAS# 115
M_A_WE# M_A_RAS# CAS# M_ODT2 M_A_DQ[63:0]
113 WE# RAS# 110 ODT0 116 <8,16> M_A_DQ[63:0]
M_A_CAS# 115 M_B_DQ32 129 120 M_ODT3
CAS# M_ODT0 M_B_DQ33 DQ32 ODT1
ODT0 116 131 DQ33
M_A_DQ32 129 120 M_ODT1 M_B_DQ34 141 130 M_B_DQ36
M_A_DQ33 DQ32 ODT1 M_B_DQ35 DQ34 DQ36 M_B_DQ37
131 DQ33 143 DQ35 DQ37 132
M_A_DQ34 141 130 M_A_DQ36 +VDR_SUS M_B_DQS#4 135 140 M_B_DQ38
M_A_DQ35 DQ34 DQ36 M_A_DQ37 M_B_DQS4 DQS#4 DQ38 M_B_DQ39
143 DQ35 DQ37 132 137 DQS4 DQ39 142
M_A_DQS#4 135 140 M_A_DQ38 C475 *D3@330U/2.5V_7 136 M_B_DM4 M_B_CAS#
DQS#4 DQ38 DM4 <8,16> M_B_CAS#
M_A_DQS4 137 142 M_A_DQ39 + M_B_DQ40 147
DQS4 DQ39 M_A_DM4 C482 *D3@2.2U/16V_6 M_B_DQ41 DQ40 M_B_DQ44 M_B_RAS#
DM4 136 149 DQ41 DQ44 146 <8,16> M_B_RAS#
M_A_DQ40 147 C481 *D3@2.2U/16V_6 M_B_DQ42 157 148 M_B_DQ45
M_A_DQ41 DQ40 M_A_DQ44 C484 *D3@2.2U/16V_6 M_B_DQ43 DQ42 DQ45 M_B_DQ46 M_B_WE#
149 DQ41 DQ44 146 159 DQ43 DQ46 158 <8,16> M_B_WE#
M_A_DQ42 157 148 M_A_DQ45 C485 *D3@2.2U/16V_6 M_B_DM5 153 160 M_B_DQ47
M_A_DQ43 DQ42 DQ45 M_A_DQ46 DM5 DQ47 M_B_DQS#5 M_B_BS[2:0]
159 DQ43 DQ46 158 DQS#5 152 <8,16> M_B_BS[2:0]
M_A_DM5 153 160 M_A_DQ47 M_B_DQ48 163 154 M_B_DQS5
DM5 DQ47 M_A_DQS#5 M_B_DQ49 DQ48 DQS5 M_B_DM[7:0]
DQS#5 152 165 DQ49 <8,16> M_B_DM[7:0]
M_A_DQ48 163 154 M_A_DQS5 M_B_DQ50 175 164 M_B_DQ52
M_A_DQ49 DQ48 DQS5 M_B_DQ51 DQ50 DQ52 M_B_DQ53 M_B_DQS#[7:0]
165 DQ49 177 DQ51 DQ53 166 <8,16> M_B_DQS#[7:0]
M_A_DQ50 175 164 M_A_DQ52 +3V M_B_DQS#6 169 174 M_B_DQ54
M_A_DQ51 DQ50 DQ52 M_A_DQ53 M_B_DQS6 DQS#6 DQ54 M_B_DQ55 M_B_DQS[7:0]
177 DQ51 DQ53 166 171 DQS6 DQ55 176 <8,16> M_B_DQS[7:0]
B M_A_DQS#6 169 174 M_A_DQ54 C496 .1U/16V_4 170 M_B_DM6 B
M_A_DQS6 DQS#6 DQ54 M_A_DQ55 M_B_DQ56 DM6 M_B_A[14:0]
171 DQS6 DQ55 176 181 DQ56 <8,16> M_B_A[14:0]
170 M_A_DM6 C495 1U/10V_4 M_B_DQ57 183 180 M_B_DQ60
M_A_DQ56 DM6 M_B_DQ58 DQ57 DQ60 M_B_DQ61 M_B_DQ[63:0]
181 DQ56 191 DQ58 DQ61 182 <8,16> M_B_DQ[63:0]
M_A_DQ58 DQ57 DQ60 M_A_DQ61 M_B_DM7 DQ59 DQ62 M_B_DQ63
191 DQ58 DQ61 182 187 DM7 DQ63 194
M_A_DQ59 193 192 M_A_DQ62 10/16: ADD 186 M_B_DQS#7
M_A_DM7 DQ59 DQ62 M_A_DQ63 PM_EXTTS#1 DQS#7 M_B_DQS7
187 DM7 DQ63 194 198 EVENT# DQS7 188
186 M_A_DQS#7 +VDR_VREF
PM_EXTTS#0 DQS#7 M_A_DQS7 B_SA0 SDA_DDR
198 EVENT# DQS7 188 197 SA0 SDA 200 SDA_DDR <16>
C483 *D3@.1U/16V_4 B_SA1 201 202 SCL_DDR
SA1 SCL SCL_DDR <16>
A_SA0 197 200 SDA_DDR
A_SA1 SA0 SDA SCL_DDR C477 *D3@2.2U/10V_6
201 SA1 SCL 202 77 NC1 A15 78
+VDR_VTT +VDR_VTT +VDR_VTT 125 122 +VDR_VTT +3V
NCTEST NC2
77 NC1 A15 78
125 122 203 204 <16> B_SA1 R524 *D3@10K_4
NCTEST NC2 VTT1 VTT2 R523 *D3@10K_4
<16> B_SA0
C490 203 204 C492 C497 3 2 C501
VTT1 VTT2 VSS2 VSS1
9 VSS4 VSS3 8
*D3@2.2U/10V_6 3 2 *D3@2.2U/10V_6 *D3@2.2U/10V_6 13 14 *D3@2.2U/10V_6
VSS2 VSS1 VSS5 VSS6
9 VSS4 VSS3 8 19 VSS7 VSS8 20 Close to DIMM1
13 VSS5 VSS6 14 25 VSS9 VSS10 26
19 VSS7 VSS8 20 31 VSS11 VSS12 32
10/16: Change to D3@ 25 26 37 38
VSS9 VSS10 VSS13 VSS14
31 VSS11 VSS12 32 43 VSS15 VSS16 44
37 VSS13 VSS14 38 49 VSS18 VSS17 48
43 VSS15 VSS16 44 55 VSS20 VSS19 54
49 VSS18 VSS17 48 61 VSS22 VSS21 60
55 54 65 66 <16> A_SA0 R425 *D3@10K_4
VSS20 VSS19 VSS23 VSS24 R424 *D3@10K_4
61 VSS22 VSS21 60 71 VSS25 VSS26 72 <16> A_SA1
65 VSS23 VSS24 66 127 VSS27 VSS28 128
71 VSS25 VSS26 72 133 VSS29 VSS30 134
127 VSS27 VSS28 128 139 VSS32 VSS31 138
A 133 VSS29 VSS30 134 145 VSS34 VSS33 144 Close to DIMM0 A
139 VSS32 VSS31 138 151 VSS36 VSS35 150
145 VSS34 VSS33 144 155 VSS37 VSS38 156
151 VSS36 VSS35 150 161 VSS39 VSS40 162
155 VSS37 VSS38 156 167 VSS41 VSS42 168
161 VSS39 VSS40 162 173 VSS44 VSS43 172
167 VSS41 VSS42 168 179 VSS46 VSS45 178
173 VSS44 VSS43 172 185 VSS48 VSS47 184
179 178 189 190
185
VSS46
VSS48
VSS45
VSS47 184 195
VSS49
VSS51
VSS50
VSS52 196 Quanta Computer Inc.
189 VSS49 VSS50 190
*D3@DDR3_SODIMM_H5.2_RVS
195 VSS51 VSS52 196 PROJECT : ZY2 & ZY6
SO-DIMM1
*D3@DDR3_SODIMM_H4_RVS Size Document Number Rev
1A
DDRIII SO-DIMM
SO-DIMM0 SMbus address A0 SMbus address A2 Date: Thursday, August 28, 2008 Sheet 17 of 40
5 4 3 2 1

0C Change footprint 0103

VIN CN29A
CN29B
1 125
PWR_SRC CLK_REQ# TXUCLKOUT- HDMI_CLK-
3 148 207 HDMI_CLK- <20>
PWR_SRC TXUCLKOUT+ LVDS_UCLK# DVI_A_CLK# HDMI_CLK+
5 150 209 HDMI_CLK+ <20>
PWR_SRC LVDS_UCLK DVI_A_CLK
7
PWR_SRC PLTRST#
4Amp 9
PWR_SRC PEX_RST#
127 PLTRST# <13,21,23,28,29,32>
11 TXUOUT0- 172 225 HDMI_TX0N
PWR_SRC LVDS_UTX0# DVI_A_TX0# HDMI_TX0N <20>
121 CLK_MXM# 154
DVI-A
+5V PEX_REFCLK# CLK_MXM# <2> LVDS_UTX3# +3V
123 CLK_MXM
PEX_REFCLK CLK_MXM <2>
0.5Amp 227 HDMI_TX0P
PEG_RXN[15:0] DVI_A_TX0 HDMI_TX0P <20>
18 TXUOUT0+ 174 221 HDMI_TX1P
5VRUN PEG_RXN[15:0] <7> LVDS_UTX0 DVI_A_TX1 HDMI_TX1P <20>
D TXUOUT1+ 168 215 HDMI_TX2P D
+3V LVDS_UTX1 DVI_A_TX2 HDMI_TX2P <20>
115 PEG_RXN0 TXUOUT2+ 162 R498 +3V
PEX_RX0# PEG_RXN1 LVDS_UTX2 HDMI_HP_A
109 156 205 HDMI_HP_A <20,31>
PEX_RX1# PEG_RXN2 LVDS_UTX3 DVI_A_HPD *E@4.7K_4
1.5Amp 226
3V3RUN PEX_RX2#
103
2
228 97 PEG_RXN3
3V3RUN PEX_RX3#
LVDS
230 91 PEG_RXN4 TXLCLKOUT- 178
3V3RUN PEX_RX4# PEG_RXN5 TXLCLKOUT+ LVDS_LCLK# MXM_DDCCK MXM_DDCCK
85 180 220 1 3 HDMI_DDCCLK <20,31>
+2.5V PEX_RX5# LVDS_LCLK DDCB_CLK
DVI
79 PEG_RXN6 218 MXM_DDCDAT
PEX_RX6# PEG_RXN7 DDCB_DAT Q43
0.5Amp PEX_RX7#
73
222 67 PEG_RXN8 TXLOUT0- 202 159
2V5RUN PEX_RX8# PEG_RXN9 TXLOUT1- LVDS_LTX0# DP_AUX# *E@RHU002N06
61 196 161
+1.8V PEX_RX9# PEG_RXN10 TXLOUT2- LVDS_LTX1# DP_AUX
55 190
PEX_RX10# PEG_RXN11 LVDS_LTX2# R499 *0_4
3.5Amp PEX_RX11#
49 184
LVDS_LTX3# DP_L0
177
2 43 PEG_RXN12 179
0C Change power 1V8RUN PEX_RX12# PEG_RXN13 DP_L0#
4 37
name from +1.8V to 1V8RUN PEX_RX13#
DVI-B
6 31 PEG_RXN14 TXLOUT0+ 204
+1.8V_MXM 0108 1V8RUN PEX_RX14# PEG_RXN15 TXLOUT1+ LVDS_LTX0
8 25 198 201
1V8RUN PEX_RX15# TXLOUT2+ LVDS_LTX1 DP_L1 +3V
10 192 195
1V8RUN PEG_RXP[15:0] LVDS_LTX2 DP_L2
12 PEG_RXP[15:0] <7> 186 189
1V8RUN LVDS_LTX3 DP_L3
14
1V8RUN PEG_RXP0 EV_LVDS_VDDEN
117 <19> EV_LVDS_VDDEN 212
PEX_RX0 PEG_RXP1 EV_LVDS_BLON LVDS_PPEN R496 +3V
111 <19> EV_LVDS_BLON 216 203
PEX_RX1 PEG_RXP2 EV_LVDS_BL_BRGHT LVDS_BLEN DP_L1#
17 105 <19> EV_LVDS_BL_BRGHT 214 197
GND PEX_RX2 PEG_RXP3 LVDS_BL_BRGHT DP_L2# *E@4.7K_4
19 99 191
GND PEX_RX3 DP_L3#
2
20 93 PEG_RXP4 EV_LVDS_DDCCLK 210
GND PEX_RX4 <19> EV_LVDS_DDCCLK DDCC_CLK
21 87 PEG_RXP5 EV_LVDS_DDCDAT 208 181
GND PEX_RX5 <19> EV_LVDS_DDCDAT DDCC_DAT DP_HPD
22 81 PEG_RXP6 MXM_DDCDAT 1 3
GND PEX_RX6 HDMI_DDCDATA <20,31>
23 75 PEG_RXP7
GND PEX_RX7 PEG_RXP8 Q42
24 69 183
GND PEX_RX8 PEG_RXP9 HSYNC RSVD
29 63 139 185
GND PEX_RX9 PEG_RXP10 VSYNC VGA_HSYNC RSVD *E@RHU002N06
32 57 141
GND PEX_RX10 PEG_RXP11 VGA_VSYNC
35 51 151
GND PEX_RX11 IGP
CRT
38 45 PEG_RXP12 VGA_RED 136 153 R497 *0_4
GND PEX_RX12 PEG_RXP13 VGA_GRN VGA_RED IGP
41 39 140 155
GND PEX_RX13 PEG_RXP14 VGA_BLU VGA_GREEN IGP
44 33 144 163
GND PEX_RX14 PEG_RXP15 VGA_BLUE IGP
C 47 27 165 C
GND PEX_RX15 CRTDCLK IGP
50 143 167
GND CRTDDAT DDCA_CLK IGP
53 145 169
GND DDCA_DAT IGP
56 171
GND PEG_TXN[15:0] IGP
59 PEG_TXN[15:0] <7> 173 HDA_RST# PIN change from 151 to 134
GND IGP +3V
62
GND PEG_TXN0
65 118 128
GND PEX_TX0# PEG_TXN1 TV_Y/HDTV_Y/TV_CVBS
68 112 129 MXM_SYNC_HDMI <12>
GND PEX_TX1# HDA_SYNC
TV
71 106 PEG_TXN2 124 131
GND PEX_TX2# TV_C/HDTV_Pr HDA_BCLK MXM_BIT_CLK_HDMI <12>
74 100 PEG_TXN3 134 R520 *E@0_4 R201
GND PEX_TX3# HDA_RST# MXM_RST#_HDMI <12>
77 94 PEG_TXN4 132 147
GND PEX_TX4# TV_CVBS/HDTV_Pb HDA_SDI MXM_SDIN_HDMI <12> +3V
80 88 PEG_TXN5 149 *10K_4
GND PEX_TX5# HDA_SDO MXM_SDOUT_HDMI <12>
83 82 PEG_TXN6
GND PEX_TX6# PEG_TXN7 MXM_ACIN
86 76 3 1
47K
GND PEX_TX7# PEG_TXN8 R210 *E@0_4 THERM# MXM_PWROK R265 *E@0_4
89 70 <3,14> THERM_ALERT# 137 16 PWROK_MXM <32>
GND PEX_TX8# PEG_TXN9 THERM# RUNPWROK
92 64
10K
GND PEX_TX9# PEG_TXN10 MXMDATA MXM_ACIN R192
95 58 133 157
GND PEX_TX10# PEG_TXN11 MXMCLK SMB_DAT AC/BATT#
98 52 135
GND PEX_TX11# PEG_TXN12 SMB_CLK Q25 *10K_4
101 46
2
GND PEX_TX12# PEG_TXN13
104 40
GND PEX_TX13# PEG_TXN14 *E@MXM CONNECTOR_2 *E@DTA114YUA
107 34
GND PEX_TX14#
3
110 28 PEG_TXN15
GND PEX_TX15#
113
GND PEG_TXP[15:0]
116 PEG_TXP[15:0] <7>
GND
119 2 ACIN <32,33>
GND PEG_TXP0
126 120
GND PEX_TX0 PEG_TXP1 Q23
130 114
GND PEX_TX1 PEG_TXP2
138 108
GND PEX_TX2 PEG_TXP3 +3V *E@2N7002E
142 102
1
146 96
152 90
164 84
170 78
GND PEX_TX7 PEG_TXP8 R191 R199
175 72
GND PEX_TX8 PEG_TXP9 Q22
176 66
GND PEX_TX9 PEG_TXP10 *E@4.7K_4 *E@4.7K_4
182 60
B GND PEX_TX10 CRT B
2
187 54 PEG_TXP11 *E@RHU002N06
GND PEX_TX11 PEG_TXP12 VGA_RED R202 I@0_4
188 48 <19> VGA_RED INT_CRT_RED <7>
GND PEX_TX12 PEG_TXP13 MXMCLK
193 42 <20,32> MXM_SMCLK 3 1
GND PEX_TX13 PEG_TXP14 VGA_GRN R185 I@0_4
194 36 <19> VGA_GRN INT_CRT_GRN <7>
199 30
GND PEX_TX15 VGA_BLU R187 I@0_4
200 <19> VGA_BLU INT_CRT_BLU <7>
GND +3V
206
GND Q24 HSYNC R208 I@0_4
211 <19> HSYNC INT_HSYNC <7>
GND
217
2
GND MXM_SPDIF_OUT *E@RHU002N06 VSYNC R204 I@0_4
223 158 <19> VSYNC INT_VSYNC <7>
GND SPDIF
224
GND MXMDATA CRTDCLK R198 I@0_4
229 <20,32> MXM_SMDATA 3 1 <19> CRTDCLK INT_CRT_DDCCLK <7>
GND EVPRSNT1# R220 *E@0_4
231 122
GND PRSNT1# CRTDDAT R194 I@0_4
232 26 <19> CRTDDAT INT_CRT_DDCDAT <7>
GND PRSNT2#
*E@MXM CONNECTOR_2
Rev: B Net:TX0 &TX2
LVDS
<19> TXLCLKOUT-
TXLCLKOUT- RN36 1 2 I@0_4P2R INT_TXLCLKOUT- INT_TXLCLKOUT- <7>
HDMI
TXLCLKOUT+ 3 4 INT_TXLCLKOUT+ INT_TXLCLKOUT+ <7> PEG_RXP3 R235 *I@0_4 TMDS_HPD <20>
<19> TXLCLKOUT+
+1.8V +2.5V +5V TXLOUT0- RN39 1 2 I@0_4P2R INT_TXLOUT0-
<19> TXLOUT0- INT_TXLOUT0- <7>
TXLOUT0+ 3 4 INT_TXLOUT0+ INT_TXLOUT0+ <7> PEG_TXN2 RN15 1 2 *I@0_4P2R INT_HDMITXN0 <20>
<19> TXLOUT0+
PEG_TXP2 3 4 INT_HDMITXP0 <20>
TXLOUT1- RN38 1 2 I@0_4P2R INT_TXLOUT1- PEG_TXN1 RN16 1 2 *I@0_4P2R INT_HDMITXN1 <20>
MXM_SPDIF_OUT + C300 C283 C280 C170 C278 TXLOUT1+ 3 4 INT_TXLOUT1+ INT_TXLOUT1+ <7> PEG_TXP1 3 4 INT_HDMITXP1 <20>
<25> MXM_SPDIF_OUT <19> TXLOUT1+
PEG_TXN0 RN17 1 2 *I@0_4P2R INT_HDMITXN2 <20>
*E@330U/2.5V_7 *E@10U/10V_8 *E@.1U/16V_4 *E@1U/10V_4 *E@1U/10V_4 TXLOUT2- RN37 1 2 I@0_4P2R INT_TXLOUT2- PEG_TXP0 3 4 INT_HDMITXP2 <20>
TXLOUT2+ 3 4 INT_TXLOUT2+ PEG_TXN3 RN18 1 2 *I@0_4P2R INT_HDMITXN3 <20>
<19> TXLOUT2+ INT_TXLOUT2+ <7>
PEG_TXP3 3 4 INT_HDMITXP3 <20>
0C Change power name from +1.8V to +1.8V_MXM
0108
A TXUCLKOUT- RN32 1 2 I@0_4P2R INT_TXUCLKOUT- A
<19> TXUCLKOUT- INT_TXUCLKOUT- <7>
TXUCLKOUT+ 3 4 INT_TXUCLKOUT+
<19> TXUCLKOUT+ INT_TXUCLKOUT+ <7>
VIN +3V TXUOUT0- RN35 1 2 I@0_4P2R INT_TXUOUT0-
<19> TXUOUT0-
<19> TXUOUT0+
TXUOUT0+ 3 4 INT_TXUOUT0+
INT_TXUOUT0-
INT_TXUOUT0+
<7>
<7>
TXUOUT1- RN34 1 2 I@0_4P2R INT_TXUOUT1-
C299 C298 C284 C282 C281 C279 C604 C162 C167 C165
<19> TXUOUT1-
<19> TXUOUT1+
TXUOUT1+ 3 4 INT_TXUOUT1+
INT_TXUOUT1-
INT_TXUOUT1+
<7>
<7>
PROJECT : ZY2 & ZY6
*E@4.7U/25V_8 *E@4.7U/25V_8 *4.7U/25V_8 *.1U/25V_4 *E@.1U/25V_4 *E@.1U/25V_4 *10U/25V_1206 *E@10U/10V_8 *E@.1U/16V_4 *.1U/16V_4 TXUOUT2- RN33 1 2 I@0_4P2R INT_TXUOUT2- Size Document Number Rev
<19> TXUOUT2- INT_TXUOUT2- <7>
TXUOUT2+ 3 4 INT_TXUOUT2+ MXM 1A
<19> TXUOUT2+ INT_TXUOUT2+ <7>
Rev: B New add.
Rev: B New add.
5 4 3 2 1

1 2 3 http://laptopblue.vn/ 4 5 6 7 8
CRT Select
CRT CONNECTOR AND ESD
10/15 :Rev: C CN40 Change footprint same as ZY5
D42 SSM14 CRTVDD3 CN40
16
+5V
10/15 :Change BOM
CRT SWITCH VGA_RED_SYS L12 BLM18BA750SN1D CRT_R1
6
CRT
CRT_11 +3V
1 11 T7
7
VGA_GRN_SYS L11 BLM18BA750SN1D CRT_G1 2 12 DDCDAT_1
DDCDAT_1 <31>
1
U42 8
A 16 +5V VGA_BLU_SYS L10 BLM18BA750SN1D CRT_B1 3 13 CRTHSYNC A
VGA_RED 4 VCC VGA_RED_SYS CRT_SENSE# D11
<18> VGA_RED C_A A0 2 9 3
3 VGA_RED_PR 4 14 CRTVSYNC
A1 VGA_RED_PR <31>
VGA_GRN 7 5 VGA_GRN_SYS R16 R15 R14 C18 C17 C16 C10 C11 C12 10 DA204U
<18> VGA_GRN C_B B0
6 VGA_GRN_PR 5 15 DDCCLK_1
VGA_GRN_PR <31> DDCCLK_1 <31>
2
VGA_BLU 9 B1 VGA_BLU_SYS 150/F_4 150/F_4 150/F_4 10P/50V_4 10P/50V_4 10P/50V_4 10P/50V_4 10P/50V_4 10P/50V_4
<18> VGA_BLU C_C C0 11
10 VGA_BLU_PR
C1 VGA_BLU_PR <31>
12 14
17
C_D D0
D1 13
<20,31> PR_INSERT_5V 1 SE
15 EN# GND 8
D10 MTW355 CRT_SENSE# <31,32>

*D@SN74CBTLV3257PWR
CRT_VSYNC1 <31>
CRT_HSYNC1 <31>
VGA_RED R34 ND@0_4 VGA_RED_SYS C599 .1U/10V_4 CRTVDD3
+5V
VGA_GRN R35 ND@0_4 VGA_GRN_SYS C19 U10 C589 *10P/50V_4 CRTVSYNC
CRTVDD3 1 16 CRT_VSYNC1 L52 BLM18BA220SN1 CRTVSYNC
VGA_BLU R29 ND@0_4 VGA_BLU_SYS .1U/10V_4 VCC_SYNC SYNC_OUT2 CRT_HSYNC1 L53 BLM18BA220SN1 CRTHSYNC C590 *10P/50V_4 CRTHSYNC
SYNC_OUT1 14
7 VCC_DDC
C15 .22U/25V_6 CRT_BYP 8 C584 10P/50V_4 DDCCLK_1
BYP VSYNC CRTVDD3
SYNC_IN2 15 VSYNC <18>
2 13 HSYNC C583 10P/50V_4 DDCDAT_1
+3V VCC_VIDEO SYNC_IN1 HSYNC <18>
C600 R507 R506
CRT_R1 3 10 CRTDCLK
VIDEO_1 DDC_IN1 CRTDCLK <18>
.1U/10V_4 CRT_G1 4 11 CRTDDAT 2.7K_4 2.7K_4
VIDEO_2 DDC_IN2 CRTDDAT <18>
CRT_B1 5 VIDEO_3 DDCCLK_1 +3V
DDC_OUT1 9
B 6 12 DDCDAT_1 B
GND DDC_OUT2 CRTDCLK R505 2.7K_4
IP4772 CRTDDAT R504 2.7K_4
LVDS
INVCC0
CN7
VIN R167 0_8 INVCC0 LCDVCC
1 2 +3V
3 4 LCD_EDIDDATA R123 *0_4
5 6 EV_LVDS_BL_BRGHT <18>
+3V LCD_EDIDCLK R130 *0_4
7 8 L_BKLT_CTRL <7>
CCD_POWER LVDS_VADJ R129 0_4
9 10 CONTRAST <32>
C146 U22
11 12 USBP11+_R RP7
13 14 3 4 0X2_4 USBP11+ <13>
BL_ON USBP11-_R 1 2 .1U/10V_4 6 1 LCDVCC_1 R165 0_8 LCDVCC
15 16 USBP11- <13> IN OUT
TXLCLKOUT+ 17 18 TXUCLKOUT+
<18> TXLCLKOUT+ 19 20 TXUCLKOUT+ <18> 4 IN GND 2
TXLCLKOUT- TXUCLKOUT- C166 C161 C163 C164 C160
<18> TXLCLKOUT- 21 22 TXUCLKOUT- <18>
R168 I@0_4 DISP_ON 3 5
23 24 <7> INT_LVDS_DIGON ON/OFF GND
TXLOUT0+ TXUOUT0+ .1U/10V_4 2.2U/10V_8 .1U/10V_4 .01U/16V_4 2.2U/10V_1206
<18> TXLOUT0+ 25 26 TXUOUT0+ <18>
TXLOUT0- TXUOUT0- R169 *E@0_4
<18> TXLOUT0- 27 28 TXUOUT0- <18> <18> EV_LVDS_VDDEN
AAT4280
TXLOUT1+ 29 30 TXUOUT1+
<18> TXLOUT1+ 31 32 TXUOUT1+ <18>
TXLOUT1- TXUOUT1-
<18> TXLOUT1- 33 34 TXUOUT1- <18>
R166
TXLOUT2+ 35 36 TXUOUT2+
<18> TXLOUT2+ 37 38 TXUOUT2+ <18>
TXLOUT2- TXUOUT2- <Check list ver:0.8>
<18> TXLOUT2- 39 40 TXUOUT2- <18>
UMA: 100K pull-down to GND I@100K_4
41 42
C C
Rev:B, Modify QCI P/N. ACES_88242-40XX_LVDS
Rev:C, Change to 4.7U 0805

+3V
+5V +3V VIN
Backlight Control
R145
C39 C159
2.2K_4 C169 C168 +3V
R172 *E@0_4 LCD_EDIDCLK 1000P/50V_4 1000P/50V_4
<18> EV_LVDS_DDCCLK
4.7U/25V_8 1000P/X7R/50V_4
R173 I@0_4
<7> INT_LVDS_EDIDCLK
R116 R117
+3V 10K_4 10K_4

BL_ON D17 2 1 BAS316 LID591# <14,29,32>
3
R146
CAMERA MODULE CONNECTOR
3
2.2K_4 BL# 2
R171 *E@0_4 LCD_EDIDDATA 2
<18> EV_LVDS_DDCDAT EC_FPBACK# <32>
3
CCD_POWER Q16
R170 I@0_4 +3V Q14
<7> INT_LVDS_EDIDDATA
2N7002
1
1 3 +3V I@0_4 R122 2 DTC144EUA
<7> INT_LVDS_BLON
Q21 *E@0_4 R125 Q17
D <18> EV_LVDS_BLON D
C149 2.2U/10V_8
+
2
AO3413 R160 2N7002
1
C145 1000P/50V_4 4.7K_4
R112
<Check list ver:0.8>
UMA: 100K pull-down to GND I@100K/F_6
3

2 CCD_POWERON <32>
Q19 PROJECT : ZY2 & ZY6
1
DTC144EU Size Document Number Rev

CRT 1A

1 2 3 4 5 6 7 8

5 4 http://laptopblue.vn/ 3
+3V
2 1
DVI-I CONNECTOR (DVI-D)
2
R555 D1
*0_6 *D@B0520LW U9
U21 PN
1
QCI P/N 39 22 HDMITX0P 2 47 MB_HDMICLK+
<18> INT_HDMITXP0 IN_D1+ OUT_D1+ VDD D0+A
38 23 HDMITX0N 6 46 MB_HDMICLK-
<18> INT_HDMITXN0 IN_D1- OUT_D1- VDD D0-A
C585 C586 C29 C30 11 44 MB_HDMITX2P
PI3VDP411LS ALP411LS000 HDMITX1P VDD D1+A MB_HDMITX2N
<18> INT_HDMITXP1 42 19 15 43
IN_D2+ OUT_D2+ HDMITX1N *D@.1U/10V_4 *D@.1U/10V_4 *D@.22U/25V_6 *D@.1U/10V_4 VDD D1-A MB_HDMITX1P
<18> INT_HDMITXN1 41 20 24 41
IN_D2- OUT_D2- VDD D2+A MB_HDMITX1N
36 40
Ch7318A AL007318000 HDMITX2P VDD D2-A MB_HDMITX0P
<18> INT_HDMITXP2 45 16 48 38
D IN_D3+ OUT_D3+ HDMITX2N VDD CLK+A MB_HDMITX0N D
<18> INT_HDMITXN2 44 17 22 37
IN_D3- OUT_D3- AVDD CLK-A
PS8101 48 13 HDMICLK+ HDMICLK+ 4 35
<18> INT_HDMITXP3 IN_D4+ OUT_D4+ +5V D0+ D0+B D_DVICLK+ <31>
47 14 HDMICLK- HDMICLK- 5 34
<18> INT_HDMITXN3 IN_D4- OUT_D4- D0- D0-B D_DVICLK- <31>
HDMITX2P 7 32
D1+ D1+B D_DVITX2+ <31>
9 28 HDMI_DDCCLK R102 *10K_4 +3V HDMITX2N 8 31
<6> SDVO_CTRLCLK SCL SCL_SINK D1- D1-B D_DVITX2- <31>
8 29 HDMI_DDCDATA R103 *10K_4 HDMITX1P 9 29
<6> SDVO_CTRLDATA SDA SDA_SINK D2+ D2+B D_DVITX1+ <31>
+3V R3 *4.7K_4 HS_A0/S4 HDMITX1N 10 28
D2- D2-B D_DVITX1- <31>
TMDS_HPD_1 7 30 HDMI_HP_A R4 *4.7K_4 HS_A1/S5 HDMITX0P 12 26
HPD HPD_SINK CLK+ CLK+B D_DVITX0+ <31>
R5 *4.7K_4 HS_A2/S6 HDMITX0N 13 25
CLK- CLK-B D_DVITX0- <31>
+3V 2 R6 *4.7K_4 HS_A3/S7
VCC[1] HDMICLK
VCC[2] 11 19 SCL/S3 GND 3
R161 R107 *I@10K_4 32 15 R549 *D@0_4 HS_A0/S4 HDMIDATA 20 14
I2C_EN# VCC[3] R546 *D@0_4 HS_A1/S5 SDA/S2 GND
*I@20K/F VCC[4] 21 GND 27
26 +3V R547 *D@0_4 HS_A2/S6 HS_MS 1 30
R109 *I@0_4 VCC[5] R548 *D@0_4 HS_A3/S7 MS GND
25 OE# VCC[6] 33 GND 33
<18> TMDS_HPD TMDS_HPD 40 HS_A0/S4 49 39
Q20 R151 *I@499/F_4 VCC[7] HS_A1/S5 A0/S4 GND
6 REXT VCC[8] 46 50 A1/S5 GND 42
3
HS_A2/S6 51 45
*I@2N7002 HS_A3/S7 A2/S6 GND
27 PRE GND[1] 1 52 A3/S7 GND 53
5 C127 C117 C107 C134 57
R158 TMDS_HPD_1 GND[2] +3V GND
2 GND[3] 12 17 TEST_OUT GND 21
18 *I@.1U/10V_4 *I@.1U/10V_4 *I@.1U/10V_4 *I@.1U/10V_4 16 23
*I@7.5K/F_4 RT_EN# 10 GND[4] R95 *D@4.7K_4 SEL_OUT AGND
RT_EN# GND[5] 24 18 NC TEST_IN 54
R159 PC0 3 31 R550 *0_4 HS_MS +3V
PC1 PC0 GND[6] HS_SEL_IN
4 36 55
1
TEST1 PC1 GND[7] SEL_IN D2 1

34 TEST1 GND[8] 37 OE 56 2 *D@BAS316
*I@100K_4 TEST2 35 43
Rev:B Add PU TEST2 GND[9] R81 *D@4.7K_4
GND[10] 49
+3V I@ N MS FUN *D@PI3HDMI412AD
C *SP@PERICOM_PI3VDP411LS H I2C CONTROL C
R527 *0_4 PC0 E@ Y +3V
R528 *0_4 PC1 L DOCK (port A)
R529 *0_4 TEST1
R530 *0_4 TEST2 R41
R539 *0_4 RT_EN#
LOW COST N
R148 *0_4 RT_EN# *4.7K_4
R153 *0_4 PC0 D_DVICLK+ R566 *100/F_4 D_DVICLK-
R152 *0_4 PC1 TM & AS Y D13 1 2 *BAS316 HS_SEL_IN C612 *2.2P/50V_4
<19,31> PR_INSERT_5V
R104 *0_4 TEST1
R105 *0_4 TEST2 R97 *0_4 D_DVITX0+ R567 *100/F_4 D_DVITX0-
C616 *2.2P/50V_4
<18> HDMI_TX0P HDMI_TX0P RN11 1 2 *E@0_4P2R HDMITX0P
<18> HDMI_TX0N HDMI_TX0N 3 4 HDMITX0N D_DVITX1+ R568 *100/F_4 D_DVITX1-
C617 *2.2P/50V_4
<18> HDMI_TX1P HDMI_TX1P RN12 1 2 *E@0_4P2R HDMITX1P
<18> HDMI_TX1N HDMI_TX1N 3 4 HDMITX1N SEL_IN FUN D_DVITX2+ R569 *100/F_4 D_DVITX2-
C618 *2.2P/50V_4
U43 <18> HDMI_TX2P HDMI_TX2P RN13 1 2 *E@0_4P2R HDMITX2P H DOCK (port B)
16 +5V <18> HDMI_TX2N HDMI_TX2N 3 4 HDMITX2N
HDMI_DDCCLK VCC HDMI_MBCLK
<18,31> HDMI_DDCCLK 4
C_A A0
2 L MB (port A)
3 <18> HDMI_CLK- HDMI_CLK- RN14 3 4 *E@0_4P2R HDMICLK-
HDMI_DDCDATA 7 A1 HDMI_MBDATA HDMI_CLK+ HDMICLK+
<18,31> HDMI_DDCDATA 5 <18> HDMI_CLK+ 1 2
C_B B0
6 Rev:B ,change IC
HDMI_HP_A B1 HDMI_MB_A
<18,31> HDMI_HP_A 9 11
C_C C0
10
C1 HDMICLK+ MB_HDMICLK+
12 14 4 3
C_D D0 HDMICLK- MB_HDMICLK-
13 2 1
D1 RP51 *ND@0_4P2R_S
<19,31> PR_INSERT_5V 1
SE HDMITX0P MB_HDMITX0P +3V
15 8 2 1
EN# GND HDMITX0N MB_HDMITX0N
B
4 3 B
RP52 *ND@0_4P2R_S
*D@SN74CBTLV3257PWR HDMITX1P 2 1 MB_HDMITX1P
HDMITX1N 4 3 MB_HDMITX1N
RP53 *ND@0_4P2R_S R544 R545
HDMITX2P 2 1 MB_HDMITX2P
2
HDMITX2N 4 3 MB_HDMITX2N *D@4.7K_4 *D@4.7K_4
RP54 *ND@0_4P2R_S R552 *0_4
<2,14,16,21,23,29> PDAT_SMB
HDMI_DDCCLK R32 *ND@0_4 HDMI_MBCLK <18,32> MXM_SMCLK R551 *D@0_4 3 1 HDMICLK
HDMI_DDCDATA R33 *ND@0_4 HDMI_MBDATA Q45
HDMI_HP_A R19 *ND@0_4 HDMI_MB_A +3V *D@RHU002N06

+5V 0C Change footprint 0103
CN36 Q44
2
20 R554 *0_4 *D@RHU002N06
SHELL1 <2,14,16,21,23,29> PCLK_SMB
MB_HDMITX2P 19 <18,32> MXM_SMDATA R553 *D@0_4 3 1 HDMIDATA
+5V D2+
18
MB_HDMITX2N D2 Shield
NV suggestion near 17
D2-
MB_HDMITX1P 16
HDMI connector 15
D1+
MB_HDMITX1N D1 Shield
14
R10 R11 MB_HDMITX0P D1-
13
D0+
12
*2K_4 *2K_4 MB_HDMITX0N D0 Shield
11 23
MB_HDMICLK+ D0- GND
10
CK+
9 22
MB_HDMICLK- CK Shield GND
8
CK- LOW COST N
HDMI_MBCLK L7 *220R_100MHZ_6 MB_HDMI_DDCCLK 7 +5V
CE Remote
6
MB_HDMI_DDCCLK NC
5
DDC CLK TM & AS Y
A C7 MB_HDMI_DDCDATA 4 A
DDC DATA C601
3
*.1U/10V_4 GND
2
HDMI_MB_A R512 *SP@1K_4 HP_DET +5V *.1U/16V_4
1 HP DET
SHELL2 21
<check list>
HDMI_MBDATA L8 *220R_100MHZ_6MB_HDMI_DDCDATA HDMI monitor default R511
have PU to 5V.So ZY3
R497 *SP@HDMI CON
*SP@10K_4 For EV@
C8 PD for level Connect to 1K
change.And serial R For IV@ PROJECT : ZY2 & ZY6
*.1U/10V_4 Connect to 0ohm
for current limited
LVDS/HDMI/CAMERA/LID 1A
Date: Tuesday, August 12, 2008 Sheet 20 of 40

5 4 3 2 1

LAN
+3V_S5 VDDCIO_12
VDDCIO_12 +PWR_TRANSF
Q13 C83 C143
2
R61 L21 *BLM11A601S
DTC144EUA .1U/16V_4 .1U/16V_4
4.7K_4
<14,23,32> PCIE_WAKE# 3 1 PCIE_WAKE_R# FOR DOCK

D D
+3V_S5
+3V_S5
VAUX_12 VDDCIO_12
20mil
U19 BIASVDD L28 BLM11A601S
15
19
56
61
38
52
68
6
C131
5
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
AVDD/DC
AVDD/DC
VDDP/DC
VDDC/VDDCIO .1U/16V_4
55 36
Rev:B ,Add VDDC/VDDCIO BIASVDD XTALVDD L20 BLM11A601S
13
VAUX_12 VDDC
20
VDDC C89
34 23
20mil 60
VDDC
VDDC
XTALVDD
.1U/16V_4 EEPROM Strapping
L26 BLM11A601S LAN_AVDDL 39 48 AVDDH L27 BLM11A601S
AVDDL AVDDH
45
C610 C125 C123 51
AVDD
AVDDL
BCM5764M
10mm X 10mm AVDDH
42 C115 C124 SO SI CS# SCLK
.1U/16V_4 4.7u/6.3V_6 .1U/16V_4 68-Pin QFN .1U/16V_4 .1U/16V_4
24c64 1 1 0 1
L25 BLM11A601S GPHY_PLLVDD 35 50 LAN_TRD3P
GPHY_PLLVDD TRD3+ LAN_TRD3P <22>
C130 C132 49 LAN_TRD3N
TRD3- LAN_TRD3N <22>
Rev:B ,change to 0603 AT45DB011B 1 0 1 1
4.7u/6.3V_6 .1U/16V_4 47 LAN_TRD2N
TRD2N LAN_TRD2N <22>
46 LAN_TRD2P
TRD2P LAN_TRD2P <22>
L24 BLM11A601S PCIE_PLLVDD 30
C104 C110 PCIE_PLLVDD/PCIE_PLLVDDL
C C
4.7u/6.3V_6 .1U/16V_4 27
PCIE_VDD/PCIE_PLLVDDL LAN_TRD1P
44 LAN_TRD1P <22>
TRD1P LAN_TRD1N
43 LAN_TRD1N <22>
L23 BLM11A601S PCIE_SDS_VDD TRD1N
33
PCIE_VDD/PCIE_VDDL LAN_TRD0N
41 LAN_TRD0N <22>
C92 C99 TRD0- LAN_TRD0P +3V_S5
40 LAN_TRD0P <22>
TRD0+ Rev: B remove
24
4.7U/10V_8 .1U/16V_4 PCIE_GND/PCIE_VDDL
2 LINKLED# R71 0_4 LAN_LINKLED#
LINKLED# LAN_LINKLED# <22>
1 100# R70 0_4
SPD100LED# 1000# R82 0_4 R62 R63 R64 C87 R73 R66
67
SPD1000LED# LAN_ACTLED#
66 LAN_ACTLED# <22>
C96 .1U/16V_4 GLAN_TXP_5787 TRAFFICLED# 4.7K_4 *4.7K_4 4.7K_4 .1U/16V_4 *ASF@4.7K_4 *ASF@4.7K_4
<13> GLAN_RXP 26
C93 .1U/16V_4 GLAN_TXN_5787 PCIE_TXDP
<13> GLAN_RXN 25 8 T8
PCIE_TXDN GPIO2 WP
31
<13> GLAN_TXP PCIE_RXDP
32
<13> GLAN_TXN PCIE_WAKE_R# PCIE_RXDN BCM_RESET#
12 9
R74 0_4 -LAN_RST WAKE# UART_MODE BCM_WP U15
10 7
<13,18,23,28,29,32> PLTRST# PERST# GPIO1_SERIALDI
29 4 T9
<2> CLK_PCIE_LAN REFCLK+ GPIO0_SERIALDO
28 8 1
<2> CLK_PCIE_LAN# REFCLK- VCC A0
7 2
+3V +3V_S5 BCM_SCL WP A1
65 6 3
SCLK SI SCL NC
63 5 4
R114 1K_4 AUX_PRES SI BCM_SDA SDA GND
54 64
R120 1K_4 VMA_PRES VAUXPRSNT SO CS#
53 62
R72 4.7K_4 VMAINPRSNT CS# NASF@AT24C64
3
LOW_PWR
SI,SO,CS#,SCLK have internal pull up
FAE:When 24C64 is used,Stuff
PCLK_SMB R99 0_4 58 59 R91 0_4 ENERGY_DET R204,R88,R212,R215
<2,14,16,20,23,29> PCLK_SMB SMB_CLK NC/(ENERGY_DET) ENERGY_DET <32>
PDAT_SMB R101 0_4 57 not stuff R85 ,R84
<2,14,16,20,23,29> PDAT_SMB SMB_DATA
B CLK_LAN_X2 VDDCIO_12 B
22
CLK_LAN_X1 XTALO
21
XTALI AT45DB011B-SC(LAN FLASH): Stuff U6,R46,R45
RDAC 37 17
RDAC VDDP/VDDCIO
R150 18
C69 27P/50V_4 CLK_LAN_X1 REGCTL25/REGOUT12IO +3V_S5 U17
1.2K/F_6 11
NC(CLK_REQ#)
2
Y7 14 LAN REGCTL12 R51 1.5_12 BCM_SDA 1 8 SI

REGCTL12 BCM_SCL SI SO
2 7
25MHZ BCM_RESET# SCK GND
3 6 +3V_S5
RESET# VCC
3
16 Q12 C46 C47 CS# 4 5 WP
GND
1
C68 27P/50V_4 R68 200_4 CLK_LAN_X2 Rev:B Change to 1.21K REG_GND/SUPER_IDDQ CS# WP# C114
1 MMJT9435 .1U/16V_4 4.7U/10V_8
*ASF@AT45DB011B-SC(LAN FLASH) *ASF@.1U/16V_4
69
Rev:B R68 change to CLK_LAN_X2

BCM5764MA0KMLG
2
4
VAUX_12
C44 C48
.1U/16V_4 10U/6.3V_8
R60 39K_6
BCM_SCL R85 *4.7K_4
SI R106 *ASF@4.7K_4
20mil CS# R80 NASF@4.7K_4

VAUX_12 +3V_S5
A A
C98 C108 C122 C111 C95 C116 C74 C75 C109 C144 C76 C94 C113 C67
.1U/16V_4 .1U/16V_4 .1U/16V_4 .1U/16V_4 .1U/16V_4 .1U/16V_4 .1U/16V_4 .1U/16V_4 4.7U/10V_8 .1U/16V_4 .1U/16V_4 .1U/16V_4 .1U/16V_4 4.7U/10V_8

Low is normal, H->Turn Off 1.2V,
H(>0.7V <2.5V)->L will internal
reset PROJECT : ZY2 & ZY6
BCM5787 & 5764 LAN
Rev
1A

5 4 3 2 1

Transfomer
LAN SWITCH Source 1: DELTA LFE9249 DB0ZR1LAN11
Source 2: Bothand GST5009 DBKN1NLAN03
+3V_S5
C103 C91
10
18
27
38
50
56
4
1
6
9
A U18 to Docking A
*D@10U_8 *D@.1U/16V_4
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
GND11
GND12
GND13
LAN_TRD0P 2 48 TX0P_PR VAUX_25_R
<21> LAN_TRD0P A0 0B1 TX0P_PR <31>
47 TX0N_PR U14
1B1 TX0N_PR <31>
LAN_TRD0N 3 1 24
<21> LAN_TRD0N A1 TCT1 MCT1
43 TX1P_PR TX0P_SYS 2 23 X-TX0P
2B1 TX1P_PR <31> TD1+ MX1+
42 TX1N_PR TX0N_SYS 3 22 X-TX0N
3B1 TX1N_PR <31> TD1- MX1-
LAN_TRD1P 7 37 TX2P_PR 4 21
<21> LAN_TRD1P A2 4B1 TX2P_PR <31> TCT2 MCT2
36 TX2N_PR TX1P_SYS 5 20 X-TX1P
5B1 TX2N_PR <31> TD2+ MX2+
LAN_TRD1N 8 TX1N_SYS 6 19 X-TX1N
<21> LAN_TRD1N A3 TD2- MX2-
32 TX3P_PR
6B1 TX3P_PR <31>
TX3N_PR
PI3L500 7B1
31 TX3N_PR <31>
TX2P_SYS
7
8
TCT3 MCT3
18
17 X-TX2P
LAN_TRD2P TX2N_SYS TD3+ MX3+ X-TX2N
<21> LAN_TRD2P 11 22 D_ACTLED# <31> 9 16
A4 0LED1 TD3- MX3-
23 D_LINKLED# <31>
LAN_TRD2N 1LED1
<21> LAN_TRD2N 12 52 10 15
A5 2LED1 TX3P_SYS TCT4 MCT4 X-TX3P
11 14
TX0P_SYS TX3N_SYS TD4+ MX4+ X-TX3N
46 12 13
0B2 TX0N_SYS TD4- MX4-
45
LAN_TRD3P 1B2 GST-5009 LF
<21> LAN_TRD3P 14
A6 TX1P_SYS
41
LAN_TRD3N 2B2 TX1N_SYS R36 R39 R38 R37
<21> LAN_TRD3N 15 40
A7 3B2
75/F_8 75/F_8 75/F_8 75/F_8
+3V_S5 35 TX2P_SYS
4B2 TX2N_SYS
34
LAN_ACTLED# 5B2
<21> LAN_ACTLED# 19
LED0 TX3P_SYS
6B2
30
VAUX_25_R
change r36,r37,r38,r39 to c0805 for burn out issue July 12th
R118 LAN_LINKLED# 20 29 TX3N_SYS
<21> LAN_LINKLED# LED1 7B2 C35
*D@10K_4 54 25 LAN_ACTLED#_SYS 1500P/2KV_1808
LED2 0LED2
26 LAN_LINKLED#_SYS
D18 *D@BAS316 LAN_DOCKIN# 1LED2
<25,31,32> DOCKIN# 17 51
SEL 2LED2 C85 C88 MGND
GND00
GND01
GND02
GND03
GND04
GND05
GND06
GND07
GND08
GND09
GND10
GND10
B B
0: A to B1 5 .01U/16V_4 .01U/16V_4
NC
1: A to B2
13
16
21
24
28
33
39
44
49
53
55
57
Close Transformer RESET TIMING
*D@PI3L500 (LAN SW)
LAN_TRD0N RN7 1 2 ND@0_4P2R TX0N_SYS

POWER
LAN_TRD0P 3 4 TX0P_SYS
LAN_TRD1N RN8 2 ND@0_4P2R TX1N_SYS

LAN_TRD1P
1
3 4 TX1P_SYS
PERSTn
LAN_TRD2N RN10 1 2 ND@0_4P2R TX2N_SYS 110 ms
min
LAN_TRD3N RN9 1 2 ND@0_4P2R TX3N_SYS
LAN_ACTLED# R89 ND@0_4 LAN_ACTLED#_SYS
LAN_LINKLED# R87 ND@0_4 LAN_LINKLED#_SYS
C C
RJ45-11 BLUETOOTH MODULE CONNECTOR
+3VSUS 1 3 BT_POWER
Q32 C428 *2.2U/10V_8
+
2
*AO3413 C414 *1000P/X7R/50V_4
+3V_S5 CN39
LAN_LINKLED#_SYS 10
GREEN_N BT_POWERON# <32>
R40 220_8 9
GREEN_P
X-TX3N 8
X-TX3P TX1-
7
X-TX1N TX1+
6
X-TX2N RX1- CN18
5 14
X-TX2P TX2- GND2
4
X-TX1P TX2+ C26 .1U/10V_4 BT_POWER
3 13 1
X-TX0N RX1+ GND1 C34 .01U/16V_4
2 2
X-TX0P RX2- C33 1500P/2KV_1808 RP49 1 USBP5+_R
1 <13> USBP5+ 2 *0X2_4 3
RX2+ USBP5-_R
<13> USBP5- 3 4 4
+3V_S5 BT_LED 5
D <29> BT_LED D
LAN_ACTLED#_SYS 12 6
R43 220_8 YELLOW_N MGND
11 7
YELLOW_P
FOXCONN_RJ45
*Aces 88266-0500
C427 C426 C412
*22P/50V_4 *22P/50V_4 *.01U/16V_4

9/29: change footprint
11/27 :change footprint
11/28 : R43 & R40 Change to 0805 PROJECT : ZY2 & ZY6
1/31 :Rev: C change PIN define about 9,10,11 & 12 Size Document Number Rev
BT/CCD/RJ45-11/CIR/2nd FAN 1A

1 2 3 4 5 6 7 8

MINI-CARD +3V
MODULE 'A' TV card
R449 10K_4
Rev:B PIN36,38 Add USB3
2
PIN69 Add R536
MODULE 'B' Wireless card PIN1, 53 Add R537 & R538
3 1 MINI_SMCLK
<2,14,16,20,21,29> PCLK_SMB
Q35
Double Stack MINI CARD
A 2N7002 A
+3V
MODULE 'A' MODULE 'B' +3V
CN27 +3V
R542 *0_8 +3V_MINI_A 92 52 +3V_MINI_B R543 0_8 R451
A_+3.3V B_+3.3V
71 A_+3.3Vaux B_+3.3Vaux 24
54 A_+3.3V B_+3.3V 2
10K_4
2
87 A_LED_WPAN# B_LED_WPAN# 46
RF_LED# R536 *0_4 RF_LED#_A 85 44 RF_LED#_B R447 0_4 RF_LED#
A_LED_WLAN# B_LED_WLAN# RF_LED# <29>
83 42 3 1 MINI_SMDATA
A_LED_WWAN# B_LED_WWAN# <2,14,16,20,21,29> PDAT_SMB
USBP2+ RP27 3 4 *0X2_4 USBP2+_C 80 38 USBP3+_C RP57 2 1 0X2_4 USBP3+ Q36
<13> USBP2+ A_USB_D+ B_USB_D+ USBP3+ <13>
USBP2- 1 2 USBP2-_C 78 36 USBP3-_C 4 3 USBP3-
<13> USBP2- A_USB_D- B_USB_D- USBP3- <13>
MINI_SMDATA 76 32 MINI_SMDATA 2N7002
MINI_SMCLK A_SMB_DATA B_SMB_DATA MINI_SMCLK
74 A_SMB_CLK B_SMB_CLK 30
PCIE_TXP2 33 77
<13> PCIE_TXP2 A_PETp0 B_PETp0 PCIE_TXP4 <13>
PCIE_TXN2 31 75
<13> PCIE_TXN2 A_PETn0 B_PETn0 PCIE_TXN4 <13>
PCIE_RXP2 25 72
<13> PCIE_RXP2 A_PERp0 B_PERp0 PCIE_RXP4 <13>
PCIE_RXN2 23 70
<13> PCIE_RXN2 A_PERn0 B_PERn0 PCIE_RXN4 <13>
PLTRST# 69 22
A_PERST# B_PERST# PLTRST# <13,18,21,28,29,32>
CLK_PCIE_TV 13 63
<2> CLK_PCIE_TV A_REFCLK+ B_REFCLK+ CLK_PCIE_MINI1 <2>
CLK_PCIE_TV# 11 61
<2> CLK_PCIE_TV# A_REFCLK- B_REFCLK- CLK_PCIE_MINI1# <2>
7 A_CLKREQ# B_CLKREQ# 58
PCIE_WAKE#_R R538 *0_4 PCIE_WAKE#_R_A 1 53 PCIE_WAKE#_R_B R537 *0_4 PCIE_WAKE#_R
A_WAKE# B_WAKE# +3VSUS
B B
+1.5V +1.5V
2
89 48 Q34
A_+1.5V B_+1.5V
73 A_+1.5V B_+1.5V 28
57 6 *DTC144EUA
A_+1.5V B_+1.5V PCIE_WAKE#_R
<14,21,32> PCIE_WAKE# 3 1
R445 *0_4 A_LFRAME#_R 65 16 B_LFRAME#_R R561 0_4 LFRAME#

<12,32> LFRAME# NC NC
R444 *0_4 A_LAD3_R 64 14 B_LAD3_R R559 0_4 LAD3
<12,32> LAD3 NC NC
<12,32> LAD2 NC NC
<12,32> LAD1 NC NC
<12,32> LAD0 NC NC
Debug 51 NC NC 91
49 C-Link_RST C-Link_RST 90
<13,27> PCIRST# R450 *0_4 47 88
R448 *0_4 C-Link_DAT C-Link_DAT
<2> PCLK_DEBUG 45 C-Link_CLK C-Link_CLK 86
R446 *SP@0_6 +3V_MINI_R 41 82

+3V NC NC
39 NC NC 81
TV use +3V C510
.1U/16V_4 19 67
NC NC
17 NC NC 66
RF_EN R557 *0_4 A_RF_EN 68 20 B_RF_EN R556 0_4

A_W_DISABLE# B_W_DISABLE# RF_EN <32>
C C
+5V L41 *SP@FBJ3216HS800_12 +5V_TV-CARD 5 56
A_BT_CHCLK B_BT_CHCLK
3 A_BT_DATA B_BT_DATA 55
C494 C493
500mA, 25mil 4.7U/6.3V_6 .1U/16V_4
43
37
26
GND
GND
GND
GND
GND
GND
84
79
50
FOR EMI
21 GND GND 40
FOR R446 & L41 18 35 +5V VCC_CORE VIN +3V +1.05V
GND GND
15 GND GND 34
9 29
GND
GND
GND GND C605 C70 C150 C613 C614

LOW COST N 4 GND GND 27
1U/10V_4 1U/10V_4 1U/25V_6 .1U/16V_4 .1U/16V_4

93
94
TM & AS Y
A/B MODULE Share pin
LC@ LOW COST +3V_S5
SP@ single QUASAR-CA0404-071N21_92P
INVCC0 +VDR_SUS +VDR_SUS +1.8V
C607 C273 C394 C615
+3V +3V_S5 for WWAN card is 2.75A +1.5V

1U/25V_6 1U/10V_4 1U/10V_4 .1U/16V_4
D D
C513 C499 C491 C498 C512 C317 C500

4.7U/6.3V_6 4.7U/6.3V_6 .1U/16V_4 .1U/16V_4 .1U/16V_4 .1U/16V_4 10U/6.3V_8
PROJECT : ZY2 & ZY6

MINI PCI-E card/TV/TPM 1A
1 2 3
4 5 6
Date: Tuesday, August 12, 2008
7
Sheet 23
8
of 40

1 http://laptopblue.vn/
2 3 4
SATA HDD
2ND SATA HDD
11/8 REV:B Conn. CN28 & CN19
Main
A CN19 A
CN28
GND23 23
GND23 23
GND1 1
2 SATA_TXP0_C C416 .01U/25V_4 1
RXP SATA_TXP0 <12> GND1
3 SATA_TXN0_C C417 .01U/25V_4 2 SATA_TXP4_C C290 .01U/25V_4
RXN SATA_TXN0 <12> RXP SATA_TXP4 <12>
4 3 SATA_TXN4_C C291 .01U/25V_4
GND2 RXN SATA_TXN4 <12>
5 SATA_RXN0_C C418 .01U/25V_4 SATA_RXN0 <12> 4
TXN SATA_RXP0_C C419 .01U/25V_4 GND2 SATA_RXN4_C C292 .01U/25V_4
TXP 6 SATA_RXP0 <12> TXN 5 SATA_RXN4 <12>
7 6 SATA_RXP4_C C293 .01U/25V_4 SATA_RXP4 <12>
GND3 TXP
GND3 7
8 +3.3VSATA2 R374 0_8 +3V

3.3V +3.3VSATA1 R267 0_8
3.3V 9 3.3V 8 +3V
3.3V 10 3.3V 9
GND 11 3.3V 10
GND 12 GND 11
GND 13 GND 12
14 HDDB5V 13
5V GND HDDA5V
5V 15 5V 14
5V 16 5V 15
GND 17 5V 16
RSVD 18 GND 17
GND 19 RSVD 18
12V 20 GND 19
12V 21 12V 20
B +3.3VSATA2 B
12V 22 12V 21
12V 22
24 C429 C425 C415 +3.3VSATA1
GND24
GND24 24
C16654-122A4-L_Serial_ATA 10U/10V_8 10U/10V_8 .1U/10V_4 C296 C297 C294
C16654-122A4-L_Serial_ATA
10U/10V_8 10U/10V_8 .1U/10V_4
R371 0_8 HDDB5V

+5V
R266 0_8 HDDA5V
+5V
C413 C424 C420 C421 C422 C423
+
C289 C295 C285 C286 C287 C288
100U/6.3_3528 10U/10V_8 .1U/16V_4 .1U/16V_4 .01U/16V_4 .01U/16V_4
150U/6.3V_7343 10U/10V_8 .1U/16V_4 .1U/16V_4 .01U/16V_4 .01U/16V_4
Rev:B ,C413 change footprint to 3528
C C
ODD (SATA)
CN20
GND14 14
GND 1
2 SATA_TXP1_C C433 .01U/25V_4
A+ SATA_TXP1 <12>
3 SATA_TXN1_C C432 .01U/25V_4
A- SATA_TXN1 <12>
GND 4
5 SATA_RXN1_C C431 .01U/25V_4 SATA_RXN1 <12>
B- SATA_RXP1_C C430 .01U/25V_4
B+ 6 SATA_RXP1 <12>
GND 7
+5V
8 SATA_DP R373 1K_4
DP HDDC5V R372 0_8
5V 9
5V 10
C436 C434 C435 C437 C438 C439
+
MD 11
GND 12
D .01U/16V_4 .01U/16V_4 .1U/16V_4 .1U/16V_4 10U/10V_8 150U/6.3V_7343 D
GND 13
GND15 15
C16654-122A4-L_Serial_ATA Quanta Computer Inc.

PROJECT : ZY2 & ZY6
SATA-HDD & ODD 1A
Date: Wednesday, August 13, 2008 Sheet 24 of 40

1 2 3 4

CODEC(ALC268) R44 10K_6

LINE OUT Amplifier
+5V +5V_ADO C42 47P/50V_4
L22 TI321611U480_1206
Gain = -(Rf/Ri)
C97 C106 C62 C73 C63 C61 U13
C79 C78
C84 C71
.1U/10V_4 10U/10V_8 .1U/10V_4 .1U/10V_4 .1U/10V_4 4.7U/10V_8 1000P/50V_4 1000P/50V_4 10P/50V_4 10P/50V_4
FRONT-L C38 10U/10V_8 R42 10K_6 7 - 2 HPL
INL OUTL HPL <26>
+
ADOGND MIC1-VREFO-R
D MIC1-VREFO-R <26> D
+3V_AVDD 8
MIC2-VREFO R46 100K_4 PVDD
MIC2-VREFO <26> +3V_AVDD
MIC1-VREFO-L +NVDD 3 1
MIC1-VREFO-L <26> NVDD PGND
<26> MUTE# 1 2 GND
9
D15 MTW355
1 2 1412MUTE# 5
<26> SECNTL SHDN#
D16 *MTW355 ADOGND
C64 C65 + 4
.1U/10V_4 10U/10V_8 FRONT-R C60 10U/10V_8 R55 10K_6 OUTR
6 INR -
<26> SURR-L SURR-L
<26> SURR-R SURR-R G1412

+5V_ADO ADOGND
C55 47P/50V_4
L16 1 2 BLM11A601S
36
35
34
33
32
31
30
29
28
27
26
25
+3V +3V_AVDD
U16 R48 10K_6 HPR
HPR <26>
C28 C53 C41
VREF
Sense B
FRONT-R
NC/Sense C
MIC1-VREFO-R
FRONT-L
GPIO1/LINE2- REFO
MIC2-VREFO
LINE1-VREFO
MIC1-VREFO-L
AVSS1
AVDD1
*4.7U/10V_8 4.7U/6.3V_6 .1U/10V_4
C619 1U/16V_6 R58 *268@0_4 MONO_OUT_268 37 24 LINE1-R

<26> MONO_OUT_L MONO-OUT/VREFO LINE1-R LINE1-R <26>
ADOGND ADOGND
+5V_ADO 38 23 LINE1-L
AVDD2 LINE1-L LINE1-L <26> 0C Change size to 0603 0111
FRONT-L 39 22 MIC1-R
HP-OUT-L/SURR-L MIC1-R MIC1-R <26>
C578 4.7U/6.3V_6
ADOGND R67 20K/F_6 40 21 MIC1-L
JDREF MIC1-L MIC1-L <26> +NVDD
C FRONT-R 41 20 C72 *.1U/16V_4 +3V_AVDD +NVDD U41 C
HP-OUT-R/SURR-R CD-R
ADOGND 42 19 C77 *.1U/16V_4 C582 1 6

AVSS2 CD-GND ADOGND VOUT C+
43
SP@ALC268/ALC888S-VC 18 C82 *.1U/16V_4 4.7U/6.3V_6 2 5 1412MUTE#
NC/CENTER CD-L VIN /SHDN
44 17 MIC2_INT_R C86 1U/16V_6 3 4
NC/LFE MIC2-R C- GND
R75 888@1U_4 MONO_OUT_888
45 16 MIC2_INT_L C90 1U/16V_6 ADOGND
NC/SIDE-L MIC2-L MIC2_INTL1 <26>
G5930
46 15 ADOGND
DMIC_CLK/SIDE-R NC/LINE2-R
DVSS1/DMIC_DATA
GPIO3/DMIC_CLK
EAPD_268 47 14
DMIC-1/2/GPIO0
EAPD NC/LINE2-L
SPDIF_OUT 48 13 SENSEA R28 20K/F_6
SDATA-OUT
<26> SPDIF_OUT SPDIFO Sense A MIC1_JD <26,31>

SDATA-IN
PCBEEP
RESET#
BIT-CLK
R31 10K/F_6 TM N
DVDD1
DVDD2
DVSS2
LINEIN_JD <26,31>
SYNC
R86 *D@0_4
<31> SPDIF_DOUT
R25 39.2K/F_6
LINE_JD <26,31>
VR
AS & LOW COST Y
1
10
11
12 VR7
11/8 REV:B Remove R97, R98 +3V
R119 *10K_4 DIGVOL_UP 2 1
<32> DIGVOL_UP A C
R94
+AZA_VDD
4
4
5
1 PCMSPK
+3V PCMSPK <27>
PCBEEP C102 1U/16V_6 BEEP_1 R110 10K_4 BEEP 4 DIGVOL_DN 3 5
<32> DIGVOL_DN B 5
7
2 PCSPK
PCSPK <14>
*268@0_4
C112 R111 U20 *SP@VR_XRE094_NOBLE
3
BEEP_1 100P/50V_6 1K_4 *CB@SN74LVC1G86DCKR
B B
C105 C101
10U/10V_8 .1U/10V_4
3
ACZ_SDIN268
BIT_CLK268
2 MUTE_BEEP
MUTE_BEEP <32> ACZ_RST#_AUDIO <12>
Q15
ACZ_SYNC_AUDIO <12> 0C Change power from +3V
+3V_S5 +1.5V_S5
to +3v_S5 to slove wake on
2N7002 ring issue 0111
1
R92 22_4
ACZ_SDIN0 <12> R377 R383
MDC +3V_S5
R93 22_4 *E@0_6 *I@0_6
BIT_CLK_AUDIO <12>
C100 22P/50V_4 CN16
1 2 C452 *.1U/10V_4 C443
ACZ_SDOUT_MDC GND RSV
ACZ_SDOUT_AUDIO <12> <12> ACZ_SDOUT_MDC 3 4
AC_SDO RSV *.1U/10V_4
5 6
ACZ_SYNC_MDC GND 3.3V
REV:B Add R541 <12> ACZ_SYNC_MDC 7 8
R541 *10K_4 R386 *22_4 MDC_SDIN1 AC_SYNC GND
+3V <12> ACZ_SDIN1 9 10
AC_SDI GND
<12> ACZ_RST#_MDC 11 12 BIT_CLK_MDC <12>
R534 0_4 D45 *D@BAS316 AC_RST# AC_BCLK
DOCKIN# <22,31,32> 15 16
GND GND
*MDC
+5V_ADO R96 888@0_4 MXM_SPDIF_OUT <18> C449 R358
*10P/50V_4 *22_4
5
REV:B, Please modify U16.PIN9.same as ZD1 C403
A EAPD_268 2 *10P/50V_4 A
4 EAPD <26> +3V R525 *E@0_6
<14> LP_ECR 1
U50 10/10 : ADD. FOR NO CARDBUS +1.5V R526 I@0_6 +AZA_VDD

R533
3
*SN74AHC1G32DCKR
*10K_4 BEEP R519 NCB@0_4 PCSPK Quanta Computer Inc.
C602 C603
4.7U/10V .1U/10V_4
PROJECT : ZY2 & ZY6
ADOGND Size Document Number Rev
REALTEK ALC268&888/MDC/VR 1A

5 4 3 2 1

SYSTEM LINE OUT/SPDIF

Speaker Amplifier +5V_ADO
+3V_AVDD
C36 1U/16V_6
+3V_SPD
C40 C45
ADOGND LINEOUT_JD:
10U/10V_8 .1U/10V_4 HP not insert->H
SECNTL HP insert->L C27
SECNTL <25>
.1U/10V_4
Gain = -(Rf/Ri) BLACK
ADOGND
15
14
23
4
6
8
U12 CN35
C66 2.2U/10V_8 SURR-L-1 R57 10K_6 SURR-L-2 1 20 LINEOUT_JD 5 9
VDD3
SECNTL
LVDD
RVDD
NC
CT
D <25> SURR-L LIN1 VOL D
4
C56 2.2U/10V_8 SURR-R-1 R50 10K_6 18 10
<25> SURR-R RIN1
SURR-R-2 HPL R13 75/F_4 L9 BK1608LL121_6 HPL_SYS 3
<25> HPL
INSPKL+ R54 10K_6 2 13 ADOGND HPR R26 75/F_4 L14 BK1608LL121_6 HPR_SYS 2 ADOGND
LIN2 IN1/IN2 <25> HPR
C57 330P/25V_4 17 1
+5V_ADO INSPKR+ R49 10K_6 RIN2 INSPKR+ R21 R9 C14 C9
19
C54 330P/25V_4 ROUT+ INSPKR-
12 7 LED
ROUT- INSPKL+ SPDIF_OUT Drive
24 *1K_4 *1K_4 47N/25V_4 47N/25V_4 <25> SPDIF_OUT 8
4.7U/6.3V_6 C50 LOUT+ INSPKL- IC
ADOGND 16 7 6
R45 RBYPASS LOUT-
3
4.7U/6.3V_6 C51 LBYPASS
SP@2SJ1371-0010A1_SPDIF
THRMPAD
100K_4 ADOGND ADOGND
GND/HS
GND/HS
GND/HS
GND/HS
1441 MUTE 5 Normal OPEN Jack
1441 MUTE SHDN
11
SE/BTL
3
D2C: NEW ADD FOR ESD

G1441 +5V_ADO
25
22
21
10
9
Q11
MUTE# 2 ADOGND
2N7002 1
LINEOUT_JD
3
+3V 1 3 +3V_SPD
1
D9 2
ADOGND Q10
ADOGND DA204U ADOGND
2
LINEOUT_JD ME2347
+3V_AVDD
EC MUTE
R508 Foxconn DFTJ10FR470 2FB5441-BKMC-7F
1 2 +5V
<32> AMP_MUTE# Singatron DFTJ10FR437 2SJ1371-0010A1
D41 MTW355 10K_4
LINE_JD
MUTE# LINE_JD <25,31>
<25> EAPD 1 2 MUTE# <25>
D40 MTW355 R12
3
C +5V 10K_4 C
SPEAKER R18
R7
0_8
0_8 R8
2
Q8
Docking LINE OUT/SPDIF
3
R88 0_8
CN30 R27 0_8 22K_4 2N7002
INSPKR- L50 0_6 INSPKR-N R79 0_8
1
INSPKR+ L17 0_6 INSPKR+N 1 R30 0_8 LINEOUT_JD
25 2
INSPKL- L51 0_6 INSPKL-N R65 0_8 Q7
INSPKL+ L18 0_6 INSPKL+N 36 R52 0_8 HPL L13 *D@BK1608LL121_6AU_LINEOUT_L
4 AU_LINEOUT_L <31>
2N7002 HPR L15 *D@BK1608LL121_6AU_LINEOUT_R
0C Change to 0 0122 AU_LINEOUT_R <31>
C59 C581 C58 C580
1
ADOGND
47P/50V_4 47P/50V_4 47P/50V_4 47P/50V_4
ADOGND
85204-04001_SPEAKER-CON
ADOGND
SYSTEM LINE IN/SUBWOOFER MIC

R509 2.2K_4 CN42
<25> MIC1-VREFO-L
1 7
C591 4.7U/6.3V_6 MIC1_L1 L60 BK1608LL121 MIC1_L 2
<25> MIC1-L
6
BLUE R510 2.2K_4 MIC1_R1 L61 BK1608LL121 MIC1_R 3
<25> MIC1-VREFO-R
CN41 <25,31> MIC1_JD 4
1 7 C592 4.7U/6.3V_6 8
<25> MIC1-R
C587 10U/10V_8 LINE1-L_1 L58 BK1608LL121 LINEINL_SYS 2 5
<25> LINE1-L
6 2SJ-T351-S11
C588 10U/10V_8 LINE1-R_1 L59 BK1608LL121 LINEINR_SYS 3 C598 C597
B <25> LINE1-R B
<25,31> LINEIN_JD 4 Normal OPEN Jack
8 470P/50V_4 470P/50V_4
C596 C595 5
470P/50V_4 470P/50V_4 2SJ-T351-S15

ADOGND
Normal OPEN Jack

For ESD close to audio out connecter
ADOGND D2C: NEW ADD FOR ESD +5V_ADO
+5V_ADO
1
D2C: NEW ADD FOR ESD
1 MIC1_JD
LINEIN_JD 3
3 D7
2 ADOGND
D8
2 DA204U
DA204U
For ESD close to audio out connecter ADOGND INT MIC array
Singatron DFTJ06FR732 2SJ-T351-S15 Singatron DFTJ06FR741 2SJ-T351-S11
R503 4.7K_4 1 2 MIC2-VREFO
Foxconn DFTJ06FRA21 JA6233L-U3T4-7F MIC2-VREFO <25> Foxconn DFTJ06FRA39 JA6233L-P3T4-7F
D39 MTW355
Alltop DFTJ06FR902 C12107-906A9-L Alltop DFTJ06FR899 C12107-D06A9-L
CN32
1 MIC2_INTL2 R502 1K_4
MIC2_INTL1 <25>
2
3
4 C579
+5V_ADO INT_MIC *22P/50V_4

CN31
1441 MUTE 1 Docking LINE IN ADOGND ADOGND

A
2 A
<25> MONO_OUT_L 3 6
4 7
5 LINE1-L_1 L56 *D@BK1608LL121_6 AU_LINEIN_L
AU_LINEIN_L <31>
*SP@SUBWOOFER
ADOGND ADOGND LINE1-R_1 L57 *D@BK1608LL121_6 AU_LINEIN_R
AU_LINEIN_R <31>
C594 C593
TM & LOW COST N Quanta Computer Inc.
*.1U/10V_4 *.1U/10V_4 MIC1_L1 L54 *D@BK1608LL121_6 AU_MIC_IN_L
AU_MIC_IN_L <31>
PROJECT : ZY2 & ZY6
AS Y MIC1_R1 L55 *D@BK1608LL121_6 AU_MIC_IN_R
AU_MIC_IN_R <31>
ADOGND ADOGND AMP /AUDIO JACK CONN 1A

5 4 3 2 1

IDSEL SELECT POWER-ON-STRAPPING

(SEE NOTE & TABLE FOR OPTIONS)
+3V R236 *CB@33K/F_6
C186 C232 C222 C202 R232 *CB@33K/F_6
*CB@4.7U/10V_6 *CB@.1U/10V_4 *CB@.1U/10V_4 *CB@.1U/10V_4

U24 PCMCIA SOCKET SKT_VCC
PCMCIA SOCKET SKT_VCC
*CB@OZ601T CN44
CN9
64 124 VCCD0 1 17
CORE_VCC VCC5#/VCCD0#/SDATA VCCD1 A_CAD0 GND1 SKTA/VCC1
77 CORE_VCC VCC3#/VCCD1#/SCLK 125 1 GND1 SKTA/VCC1 17 2 SKTAAD0/D3 SKTA/VCC2 51
97 123 A_CAD0 2 51 A_CAD1 3
CORE_VCC VPP_PGM/VPPD0/SLATCH A_CAD1 SKTAAD0/D3 SKTA/VCC2 A_CAD3 SKTAAD1/D4
115 3 4 18
D
NOTE: IDSEL SELECTION! CORE_VCC
A_CAD31
A_CAD3
A_CAD5
4
SKTAAD1/D4
SKTAD3/D5 SKTA/VPP1 18 A_CAD5
A_CAD7
5
SKTAD3/D5
SKTAD5/D6
SKTA/VPP1
SKTA/VPP2 52
D
1 PCI_VCC CAD31 103 5 SKTAD5/D6 SKTA/VPP2 52 6 SKTAAD7/D7

THIS DEVICE UTILIZES A "SELECTABLE IDSEL" SCHEME. 20 102 A_CAD30 A_CAD7 6 A_CC/BE0# 7
IDSEL CAN BE CONNECTED INTERNALLY TO ONE OF THREE AD[31..0] PCI_VCC CAD30 A_CAD29 A_CC/BE0# SKTAAD7/D7 A_CAD9 -SKTACBE0/CE1#
<13> AD[31..0] 33 PCI_VCC CAD29 101 7 -SKTACBE0/CE1# 8 SKTAAD9/A10
PCI AD LINES OR EXTERNAL IDSEL SIGNAL. 100 A_CAD28 A_CAD9 8 A_CAD11 9 69
AD31 CAD28 A_CAD27 A_CAD11 SKTAAD9/A10 A_CAD12 SKTABAD11/OE# GND5
4 AD31 CAD27 99 9 SKTABAD11/OE# GND5 69 10 SKTAAD12/A11 GND6 70
22K TO 47K PULL-UP & PULL-DOWN RESISTORS ARE AD30 5 110 A_CAD26 A_CAD12 10 70 A_CAD14 11 71
REQUIRED TO BE CONNECTED TO PINS 123 & 124 TO AD29 AD30 CAD26 A_CAD25 A_CAD14 SKTAAD12/A11 GND6 A_CC/BE1# SKTAAD14/A9 GND7
6 AD29 CAD25 109 11 SKTAAD14/A9 GND7 71 12 -SKTACBE1/A8 GND8 72
SELECT ONE OF THE 4 POSSIBLE IDSEL CONNECTIONS. AD28 7 108 A_CAD24 A_CC/BE1# 12 72 A_CPAR 13 73
THE TABLE BELOW SHOWS THE 4 POSSIBLE COMBINATIONS. AD27 AD28 CAD24 A_CAD23 A_CPAR -SKTACBE1/A8 GND8 A_CPERR# SKTAPAR/A13 GND9
8 AD27 CAD23 106 13 SKTAPAR/A13 GND9 73 14 -SKTAPERR/A14 GND10 74
AD26 9 105 A_CAD22 A_CPERR# 14 74 A_CGNT# 15 75
CONFIGURING IDSEL TO BE INTERNALLY CONNECTED ALLOWS AD25 AD26 CAD22 A_CAD21 A_CGNT# -SKTAPERR/A14 GND10 A_CINT# -SKTAGNT/WE# GND11
10 AD25 CAD21 104 15 -SKTAGNT/WE# GND11 75 16 -SKTAINT/RDY GND12 76
FOR A FULL PARALLEL POWER MODE. IF AN EXTERNALLY AD24 13 118 A_CAD20 A_CINT# 16 76 77
CONNECTED IDSEL IS REQUIRED THEN AN INVERTER MUST AD23 AD24 CAD20 A_CAD19 -SKTAINT/RDY GND12 GND13
14 AD23 CAD19 95 GND13 77 UPPER PIN GND14 78
BE CONNECTED TO VPP_PGM TO CREATE VPP_VCC. AD22 15 94 A_CAD18 UPPER PIN 78 A_CCLK 19 79
AD21 AD22 CAD18 A_CAD17 A_CCLK GND14 A_CIRDY# SKTAPCLK/A16 GND15
16 AD21 CAD17 93 19 SKTAPCLK/A16 GND15 79 20 -SKTAIRDY/A15 GND16 80
AD20 17 75 A_CAD16 A_CIRDY# 20 80 A_CC/BE2# 21 81
AD19 AD20 CAD16 A_CAD15 A_CC/BE2# -SKTAIRDY/A15 GND16 A_CAD18 -SKTACBE2/A12 GND17
VCC5# VPP_PGM IDSEL SELECT 18 73 21 81 22 82
AD18 AD19 CAD15 A_CAD14 A_CAD18 -SKTACBE2/A12 GND17 A_CAD20 SKTAAD18/A7 GND18
19 AD18 CAD14 74 22 SKTAAD18/A7 GND18 82 23 SKTAAD20/A6 GND19 83
(124) (123) AD17 21 71 A_CAD13 A_CAD20 23 83 A_CAD21 24 84
AD16 AD17 CAD13 A_CAD12 A_CAD21 SKTAAD20/A6 GND19 A_CAD22 SKTAAD21/A5 GND20
22 AD16 CAD12 72 24 SKTAAD21/A5 GND20 84 25 SKTAAD22/A4
AD15 28 70 A_CAD11 A_CAD22 25 A_CAD23 26
DOWN DOWN AD18 AD14 AD15 CAD11 A_CAD10 A_CAD23 SKTAAD22/A4 A_CAD24 SKTAAD23/A3
29 AD14 CAD10 69 26 SKTAAD23/A3 27 SKTAAD24/A2
AD13 30 68 A_CAD9 A_CAD24 27 A_CAD25 28
AD12 AD13 CAD9 A_CAD8 A_CAD25 SKTAAD24/A2 A_CAD26 SKTAAD25/A1
31 AD12 CAD8 85 28 SKTAAD25/A1 29 SKTAAD26/A0 NC 85
DOWN UP AD20 AD11 34 84 A_CAD7 A_CAD26 29 85 A_CAD27 30 86
AD10 AD11 CAD7 A_CAD6 A_CAD27 SKTAAD26/A0 NC A_CAD29 SKTAAD27/D0 NC
35 AD10 CAD6 82 30 SKTAAD27/D0 NC 86 31 SKTAAD29/D1 NC 87
AD9 36 83 A_CAD5 A_CAD29 31 87 A_CRSVD/D2 32 88
UP DOWN AD25 AD8 AD9 CAD5 A_CAD4 A_CRSVD/D2 SKTAAD29/D1 NC A_CCLKRUN# SKTARSVD/D2 NC
37 AD8 CAD4 80 32 SKTARSVD/D2 NC 88 33 -SKTACLKRUN/WP
AD7 38 81 A_CAD3 A_CCLKRUN# 33 34
AD6 AD7 CAD3 A_CAD2 -SKTACLKRUN/WP GND2
39 AD6 CAD2 78 34 GND2
UP UP PIN 127 AD5 40 79 A_CAD1 35
C
AD4 AD5 CAD1 A_CAD0 A_CCD1# GND3 C
41 AD4 CAD0 76 35 GND3 36 -SKTACD1/CD1#
AD3 42 A_CCD1# 36 A_CAD2 37
AD2 AD3 R211 *CB@33_4 A_CCLK A_CAD2 -SKTACD1/CD1# A_CAD4 SKTAAD2/D11
43 AD2 37 SKTAAD2/D11 38 SKTAD4/D12
AD1 44 107 A_CAD4 38 A_CAD6 39
AD0 AD1 CCLK A_CFRAME# A_CAD6 SKTAD4/D12 A_CRSVD/D14 SKTAAD6/D13
46 AD0 CFRAME# 114 39 SKTAAD6/D13 40 SKTARSVD/D14
AD20 R239 *CB@100/F_4 PCM_IDSEL PCM_IDSEL 127 117 A_CIRDY# A_CRSVD/D14 40 A_CAD8 41
CBE3# IDSEL CIRDY# A_CTRDY# A_CAD8 SKTARSVD/D14 A_CAD10 SKTAAD8/D15
<13> CBE3# 11 C/BE3# CTRDY# 116 41 SKTAAD8/D15 42 SKTAAD10/CE2#
ID Select : AD20 CBE2# 12 113 A_CDEVSEL# A_CAD10 42 A_CVS1# 43
<13> CBE2# C/BE2# CDEVSEL# SKTAAD10/CE2# -SKTAVS1/VS1#
CBE1# 49 61 A_CSTOP# A_CVS1# 43 A_CAD13 44
<13> CBE1# C/BE1# CSTOP# -SKTAVS1/VS1# SKTAAD13/IORD#
Interrupt Pin : INTA# CBE0# 50 58 A_CPAR A_CAD13 44 A_CAD15 45
<13> CBE0# C/BE0# CPAR SKTAAD13/IORD# SKTAAD15/IOWR#
60 A_CPERR# A_CAD15 45 A_CAD16 46
CPERR# A_CSERR# A_CAD16 SKTAAD15/IOWR# A_CRSVD/A18 SKTAAD16/A17
Request Indicate : REQ0# <2> PCLK_PCM 26 PCI_CLK CSERR# 91 46 SKTAAD16/A17 47 -SKTRSVD/A18
DEVSEL# 27 89 A_CREQ# A_CRSVD/A18 47 A_CBLOCK# 48
<13> DEVSEL# DEVSEL# CREQ# -SKTRSVD/A18 -SKTALOCK/A19
Grant Indicate : GNT0# FRAME# 23 62 A_CGNT# A_CBLOCK# 48 A_CSTOP# 49
<13> FRAME# FRAME# CGNT# -SKTALOCK/A19 -SKTASTOP/A20
IRDY# 24 88 A_CINT# A_CSTOP# 49 A_CDEVSEL# 50
<13> IRDY# IRDY# CINT# SKT_VCC -SKTASTOP/A20 -SKTADEVSEL/A21
TRDY# 25 59 A_CBLOCK# A_CDEVSEL# 50
<13> TRDY# TRDY# CBLOCK# -SKTADEVSEL/A21
STOP# 47 87 A_CCLKRUN# LOWER PIN
<13> STOP# STOP# CCLKRUN#
PAR 48 119 A_CRST# R223 *CB@47K_6 LOWER PIN A_CTRDY# 53
<13> PAR PAR CRST# -SKTATRDY/A22
98 A_CRSVD/D2 A_CTRDY# 53 A_CFRAME# 54
R214 *CB@0_4 PCMSPK R2_D2 A_CRSVD/D14 A_CFRAME# -SKTATRDY/A22 A_CAD17 -SKTAFRAME/A23
<25> PCMSPK 51 PERR#/SPKR_OUT R2_D14 86 54 -SKTAFRAME/A23 55 SKTAAD17/A24
63 A_CRSVD/A18 A_CAD17 55 A_CAD19 56
REQ0# R2_A18 A_CVS1# A_CAD19 SKTAAD17/A24 A_CVS2# SKTAAD19/A25
<13> REQ0# 2 REQ# CVS1 57 56 SKTAAD19/A25 57 -SKTAVS2VS2#
GNT0# 3 121 A_CVS2# A_CVS2# 57 A_CRST# 58
<13> GNT0# GNT# CVS2 -SKTAVS2VS2# -SKTARST/RESET
56 A_CCD1# A_CRST# 58 A_CSERR# 59
PCIRST# CCD1# A_CCD2# A_CSERR# -SKTARST/RESET A_CREQ# 0SKTASERR/WAIT#
<13,23> PCIRST# 126 RST# CCD2# 122 59 0SKTASERR/WAIT# 60 -SKTAREQ/INPACK#
SKT_VCC R225 *CB@0_4 PCM_PME# 120 92 A_CAUDIO A_CREQ# 60 A_CC/BE3# 61
<13> PCI_PME# PME#/RI_OUT# CAUDIO -SKTAREQ/INPACK# -SKTACBE3/REG#
90 A_CSTSCHG A_CC/BE3# 61 A_CAUDIO 62
CSTSCHG A_CAUDIO -SKTACBE3/REG# A_CSTSCHG SKTAAUDIO/BVD2
<14,32> CLKRUN# 55 MF6 (CLKRUN#) 62 SKTAAUDIO/BVD2 63 -SKTASTSCHG/BVD1
54 111 A_CC/BE3# A_CSTSCHG 63 A_CAD28 64
C173 C171 SERIRQ MF4 (RI_OUT#) CC/BE3# A_CC/BE2# A_CAD28 -SKTASTSCHG/BVD1 A_CAD30 SKTAAD28/D8
<14,32> SERIRQ 53 MF3 (SERIRQ#) CC/BE2# 112 64 SKTAAD28/D8 65 SKTAAD30/D9
52 66 A_CC/BE1# A_CAD30 65 A_CAD31 66
<13> INTA# MF0 (INTA#) CC/BE1# SKTAAD30/D9 SKTAAD31/D10
*CB@4.7U/10V_6 *CB@.1U/10V_4 67 A_CC/BE0# A_CAD31 66 A_CCD2# 67
CC/BE0# A_CCD2# SKTAAD31/D10 -SKTACD2/CD2#
B 67 68 B
GND
GND
GND
GND
GND
-SKTACD2/CD2# GND4
68 GND4
22K TO 47K PULL-UPS MUST BE PLACED
ON INTA#, PME#, SERIRQ# & CLKRUN#. *CB@PCMCIA_SOCKET
32
45
65
96
128
*CB@PCMCIA_SOCKET
+3V
C172 C174
*CB@4.7U/10V_6 *CB@.1U/10V_4
SKT_VCC
U23
6 1 +5V
VCC1 +3.3
5 VCC2 +3.3 2
VCCD0 7 3
VCCD1 VCC5# +5V
8 VCC3# GND 4
C176 C177
*CB@OZ2210G
*CB@4.7U/10V_6 *CB@.1U/10V_4
O2MICRO OZ2210 8PIN

SINGLE SLOT PARALLEL
POWER SWITCH
A A

PROJECT : ZY2 & ZY6
PCMCIA(OZ601) 1A

5 4 3 2 1

A B http://laptopblue.vn/ C D E
+1.8V_VDD
L30 *BK1608HS220_6_1A
+1.8V +3V
7 IN 1 CARD READER
C347 C327 C325 C355 C326 C358 C353 C346 C348 C349
*10U/6.3V_8 *.1U/16V_4 *.1U/16V_4 *.1U/16V_4 *1000P/X7R/50V_4 *10U/6.3V_8 *.1U/16V_4 *.1U/16V_4 *.1U/16V_4 *.1U/16V_4
4 4
C640 & C639 close to APVDD(pin5)
(length must under 120mil) and +3V VCC_XD VCC_XD
trace width = 20mil, after C640,
XD_D4/SD_D4
XD_D5/SD_D5
XD_D6/SD_D6
XD_D7/SD_D7
CN21
pls put one more 0.1uF for it.
23 (4)SD-VCC
XD_D0/MS_D0/SD_D0 25
XD_RE#
XD_D1/MS_D1/SD_D1 (7)SD-DAT0
29 (8)SD-DAT1
XD_D2/MS_D2/SD_D2 10 33
XD_D3/MS_D3/SD_D3 (9)SD-DAT2 (18)XD-VCC
11 (1)SD-DAT3
XD_CE#/MS_SCLK/SD_CLK 24 34 XD_CD#
XD_WE#/MS_BS/SD_CMD (5)SD-CLK (19)XD-CD XD_R/B#
12 (2)SD-CMD (2)XD-R/B 1
+3V +1.8V_VDD +3V +1.8V_VDD SD_CD# XD_RE#
36
35
34
33
32
31
30
29
28
27
26
25
U27 36 SD-CD (3)XD-RE 2
XD_WP#/SD_WP# 35 3 XD_CE#/MS_SCLK/SD_CLK
SD-WP (4)XD-CE XD_CLE
4
NC
NC
NC
GND
GND
GND
TAV33
MDIO8
MDIO9
MDIO10
MDIO11
MDIO12
(5)XD-CLE XD_ALE
(6)XD-ALE 5
6 XD_WE#/MS_BS/SD_CMD
(7)XD-WE XD_WP#/SD_WP#
37 DV18 GND 24 (8)XD-WP 7
38 23 XD_R/B#
PCIES_EN MDIO13 XD_ALE XD_D0/MS_D0/SD_D0
39 PCIES MDIO14 22 14 (9)MS-VCC (10)XD-D0 8
XD_CLE 40 21 XD_D0/MS_D0/SD_D0 19 9 XD_D1/MS_D1/SD_D1
XD_WP#/SD_WP# MDIO7 CR1_LEDN XD_D1/MS_D1/SD_D1 (4)MS-DATA0 (11)XD-D1 XD_D2/MS_D2/SD_D2
41 MDIO6 DV33 20 20 (3)MS-DATA1 (12)XD-D2 26
XD_CE#/MS_SCLK/SD_CLK_L 42 19 XD_D2/MS_D2/SD_D2 18 27 XD_D3/MS_D3/SD_D3
XD_WE#/MS_BS/SD_CMD MDIO5 DV33 XD_D3/MS_D3/SD_D3 (5)MS-DATA2 (13)XD-D3 XD_D4/SD_D4
+3V
43
44
MDIO4
DV33
JMB385 DV18
CR1_PCTLN
18
17 MC_PWR_CTRL# XD_CE#/MS_SCLK/SD_CLK
16
15
(7)MS-DATA3
(8)MS-SCLK
(14)XD-D4
(15)XD-D5
28
30 XD_D5/SD_D5
XD_D3/MS_D3/SD_D3 45 16 SD_CD# MS_CD# 17 31 XD_D6/SD_D6
3 XD_D2/MS_D2/SD_D2 MDIO3 CR1_CD0N MS_CD# XD_WE#/MS_BS/SD_CMD (6)MS-INS (16)XD-D6 XD_D7/SD_D7 3
46 MDIO2 CR1_CD1N 15 21 (2)MS-BS (17)XD-D7 32
XD_D1/MS_D1/SD_D1 47 14 T33
XD_D0/MS_D0/SD_D0 MDIO1 SEECLK
48 MDIO0 SEEDAT 13 T32
APCLKN
APREXT
APCLKP
APGND
APVDD
APRXN
13 37
XRSTN
APRXP
APTXN
APTXP
XTEST
APV18
(3)SD/(1)MS/(1)XD-GND SDIO-GND
22 (6)SD/(10)MS/(9)XD-GND SDIO-GND1 38
+1.8V_VDD *CARD_READER_TTN
1
2
3
4
5
6
7
8
9
10
11
12
*JMICRON
<13,18,21,23,29,32> PLTRST#
APTXP_C C329 *.1U/10V_4 VCC_XD VCC_XD
JMB_RXP <13>
PREXT
APTXN_C C328 *.1U/10V_4

JMB_RXN <13>
CN22
<2> CLK_PCIE_CARD#
<2> CLK_PCIE_CARD JMB_TXN <13> 21 SD-VCC
R276 *8.2K_4 XD_D0/MS_D0/SD_D0 31
JMB_TXP <13> SD-DAT0
XD_D1/MS_D1/SD_D1 34
Trace width = 12mil" at PREXT XD_D2/MS_D2/SD_D2 SD-DAT1
9 SD-DAT2 XD-VCC 38
Rev: B Add. for Vendor request XD_D3/MS_D3/SD_D3 11
XD_CE#/MS_SCLK/SD_CLK SD-DAT3 XD_CD#
25 SD-CLK XD-CD 2
XD_WE#/MS_BS/SD_CMD 15 3 XD_R/B#
XD_CE#/MS_SCLK/SD_CLK_L R471 *22_4 XD_CE#/MS_SCLK/SD_CLK SD_CD# SD-CMD XD-R/B XD_RE#
39 SD-C/D XD-RE 4
XD_WP#/SD_WP# 41 5 XD_CE#/MS_SCLK/SD_CLK
VCC_XD SD-WP XD-CE XD_CLE
XD-CLE 6
REV:B Modify 2 1 19 7 XD_ALE
2 CR_WAKE# <14> SD-VSS1 XD-ALE 2
+3V D44 *BAS316 29 8 XD_WE#/MS_BS/SD_CMD
R313 *10K_4 XD_R/B# SD-VSS2 XD-WE XD_WP#/SD_WP#
40 SD-GND XD-WP 13
R281 *4.7K_4 SD_CD# 2 1 R286 *10K_4 XD_WP#/SD_WP#
D22 *BAS316 XD_CD# 12 23 XD_D0/MS_D0/SD_D0
R277 *4.7K_4 MS_CD# XD_D0/MS_D0/SD_D0 MS-VCC XD-D0 XD_D1/MS_D1/SD_D1
2 1 22 MS-DATA0 XD-D1 27
D21 *BAS316 C343 XD_RE# R319 *200K_4 XD_D1/MS_D1/SD_D1 24 30 XD_D2/MS_D2/SD_D2
R300 *10K_4 XD_CLE XD_D2/MS_D2/SD_D2 MS-DATA1 XD-D2 XD_D3/MS_D3/SD_D3
20 MS-DATA2 XD-D3 32
*270P/25V_4 XD_ALE R314 *200K_4 XD_D3/MS_D3/SD_D3 16 33 XD_D4/SD_D4
XD_CE#/MS_SCLK/SD_CLK MS-DATA3 XD-D4 XD_D5/SD_D5
14 MS-SCLK XD-D5 35
MS_CD# 18 36 XD_D6/SD_D6
XD_WE#/MS_BS/SD_CMD MS-INS XD-D6 XD_D7/SD_D7
26 MS-BS XD-D7 37
43 GND
10
Memory Card Power Supply 10/12 : BOM modify
+3V
28
42
MS-VSS1
MS-VSS2
GND
XG-GND1
XD-GND2
1
17
*CARD_READER_PROCONN
250mA VCC_XD R321

1
MC_PWR_CTRL# R317 *0_8 *10K_4

Q29
MC_PWR_CTRL# 2
Use 0805 type and *AO3403

Trace width = 30 mil" C360
1 1
at MC_PWR_CTRL#,
3
VCC_XD *.1U/16V_4
30mil VCC_XD
C320 C345 C356

R322 C359 Quanta Computer Inc.
*100K_4 *4.7U/6.3V_6
*.01U/16V_4 *.01U/16V_4 *10U/6.3V_8 PROJECT : ZY2 & ZY6
1A
CARD READER JMB385
A B C D E

To NEW-CARD & EXT. USB 650mA 2A 1.3A 275mA

+1.5V +5VPCU +3V +3V_S5
REV:B, CN10 change footprint
CN17
+3VPCU +3V +5V 2 1
D CN10 2 1 D
4 4 3 3
1 1 6 6 5 5
2 2 8 8 7 7
3 3 10 10 9 9
4 4 12 12 11 11
<32> NBSWON# 5 5 14 14 13 13
6 PDAT_SMB 16 15 PLTRST# <13,18,21,23,28,32>
<31,32> MX0 6 <2,14,16,20,21,23> PDAT_SMB 16 15
7 PCLK_SMB 18 17
<31,32> MX5 7 <2,14,16,20,21,23> PCLK_SMB 18 17 NC_EN# <32>
8 USBON# 20 19
<31,32> MX6 8 <30,31,32> USBON# 20 19 NEW_CLKREQ# <2>
<31,32> MX7 9 9 22 22 21 21
<31,32> MY0 10 10 <13> USBP6- 24 24 23 23 CLK_PCIE_NEW_C# <2>
<31,32> MY4 11 11 <13> USBP6+ 26 26 25 25
CLK_PCIE_NEW_C <2>
<32> NUMLED# 12 12 28 28 27 27
<32> CAPSLED# 13 13 <13> USBP7- 30 30 29 29 PCIE_RXN1 <13>
<31> SATA_LED#_R 14 14 <13> USBP7+ 32 32 31 31 PCIE_RXP1 <13>
PWRLED# 15 34 33
<31,32> PWRLED# 15 34 33
SUSLED# 16 36 35
<31,32> SUSLED# 16 <13> USBP8- 36 35 PCIE_TXN1 <13>
<14,19,32> LID591# 17 17 <13> USBP8+ 38 38 37 37 PCIE_TXP1 <13>
C 21 21 18 18 40 40 39 39 C
22 22 19 19 42 42 41 41
20 20
*NEW CARD_CON20X2
SW-20P
+3V
CN43
1
REV:B, Please change PIN define.same as ZY5 C611 25
36
CN8 change footprint 4
B
*.1U/10V_4 B
*KEYBOARD LED
+3V CN8
Fnction Keyboard Matrix
1
RF_LED# 2 E-KEY MX0/ MY0 Rev:B Add CN43 For backlight KB
<23> RF_LED#
BT_LED 3
<22> BT_LED
MX4 4 E-Mail MX1/ MY0
<31,32> MX4
MX5 5
<31,32> MX5
<31,32> MX2
MX2 6 E-WWW MX2/ MY0 Rev:B Change to to PAD
MX1 7 C255,C234,C221,C199,R217,C198,R183,
<31,32> MX1
MX6 8 3G/TV MX3/ MY0 R182,R174,R257,R324,R335,R334,R349,C395
<31,32> MX6
MY0 9
<31,32> MY0
Arcade_key 10 13 Wireless MX4/ MY0
<32> ARCADE_KEY
11 14
12 BlueTooth MX5/ MY0
P-KEY MX6/ MY0
A Aces 88501-120N Quanta Computer Inc. A
Presentation MX5/ MY4
Lock MX6/ MY4 PROJECT : ZY2 & ZY6
Sync MX7/ MY4 Size Document Number Rev
BTB CONN. 1A
http://hobi-elektronika.net Date: Tuesday, August 12, 2008 Sheet 29 of 40
5 4 3 2 1

TM & AS Y USB
Finger Printer +5V_S5 +5V_S5
USBP0-_R D47 2 1 MLVG06031R
LOW COST N U8 USBP0+_R D48 2 1 MLVG06031R

2 8 USBPWR1
+3VSUS IN1 OUT3 C31 USBP1-_R D49
3 IN2 OUT2 7 2 1 MLVG06031R
CN15 6
OUT1 10U/10V_8 USBP1+_R D50
4 <29,31,32> USBON#
4 EN# 2 1 MLVG06031R
<13> USBP9- RP50 3 4 *0X2_4 USBP9-_R 1
USBP9+_R 3 6 GND
<13> USBP9+ 1 2 2 5 9 GND-C OC# 5 R17 *6.34K/F REV:C Modify
D D
1 G548A2P8U
*SP@Finger Printer
USBPWR1
10/16: Change BOM
C25 C24
100U/6.3_3528 1000P/X7R/50V_4
CN38
1 5
HOLES CPU NUT (BOT) <13> USBP0-
RP56 2 1 0X2_4 USBP0-_R 2
1
2
5
6 6
4 3 USBP0+_R 3 7
<13> USBP0+ 3 7
4 4 8 8
HOLE12 HOLE11 HOLE13 U7
H-c256d142p2-8 H-c256d142p2-8 H-c256d142p2-8 CM1293-04SO Alltop_USB
2 5 2 5 2 5 1 6 +5V_S5
CH1 CH4 USBPWR1
3 6 3 6 3 6
4 7 4 7 4 7 2 VN VP 5
C23 C22
3 4
8
1
9
8
1
9
8
1
9
CH2 CH3 100U/6.3_3528 1000P/X7R/50V_4
C C
CN37
1 1 5 5
RP55 2 1 0X2_4 USBP1-_R 2 6
<13> USBP1- 2 6
Rev : B Add MINI NUT <13> USBP1+ 4 3 USBP1+_R 3 7
3 7
4 4 8 8
HOLE33 HOLE34 HOLE25 HOLE22 Alltop_USB

H-C197D142P2 H-C197D142P2 *H-C177D142p2 H-C177D142p2
PAD1 PAD2
1
HOLE9 HOLE8 HOLE17 HOLE24 HOLE31 HOLE10

*Pad-obs *Pad-obs *H-TC256BC315D118P2-8 *H-TC256BC315D118P2-8 *H-TC256BC315D118P2-8 *H-TC256BC315D118P2-8 *H-TC256BC315D118P2-8 *H-TC256BC315D118P2-8
2 5 2 5 2 5 2 5 2 5 2 5
3 6 3 6 3 6 3 6 3 6 3 6
4 7 4 7 4 7 4 7 4 7 4 7
1
8
1
9
8
1
9
8
1
9
8
1
9
8
1
9
8
1
9
MXM NUT (BOT)
B B
HOLE14 HOLE15 HOLE16 HOLE19 HOLE20
*H-c256d142p2-8 *H-c256d142p2-8 *H-c256d142p2-8 *H-c256d142p2-8 *H-c256d142p2-8
2 5 2 5 2 5 2 5 2 5 HOLE30 HOLE27 HOLE23 HOLE21 HOLE29
3 6 3 6 3 6 3 6 3 6 *H-c256d118p2-8 *H-TC256BC315D118P2-8 *H-tc276bc315d118p2-8 *H-tc276bc315d118p2-8 *H-tc276bc315d118p2-8
4 7 4 7 4 7 4 7 4 7 2 5 2 5 2 5 2 5 2 5
3 6 3 6 3 6 3 6 3 6
4 7 4 7 4 7 4 7 4 7
8
1
9
8
1
9
8
1
9
8
1
9
8
1
9
8
1
9
8
1
9
8
1
9
8
1
9
8
1
9
MDC NUT (TOP)
HOLE32 HOLE35 HOLE7
HOLE26 HOLE28 *h-c256d142p2-8 H-BC256D138P2 *H-C276D118PT-8 HOLE18
H-TC256BC295D63P2-8 H-TC256D63PT-8 2 5 *H-tc256bc315d118p2-8
2 5 2 5 3 6 2 5 2 5
3 6 3 6 4 7 3 6 3 6
4 7 4 7 4 7 4 7
8
1
9
A A
8
1
9
8
1
9
8
1
9
8
1
9
Rev:B New add HOLE32 HOLE35 BOT PROJECT : ZY2 & ZY6
HOLE26 & 28 Change footprint
http://hobi-elektronika.net Date:
USB/FINGER PRINTER
Tuesday, August 12, 2008 Sheet 30 of 40
1A
5 4 3 2 1

5 4 http://laptopblue.vn/ 3 2
+3V
1
INT K/B CPU FAN

Rev:B change footprint
CN12
MY0 1 R47
MY15 MY1 2
<32> MY15 MY14 MY2
CA5 CA6 3 10K_4
<32> MY14
MY13 MY9 1 2 2 1 MY13 MY3 4
<32> MY13
MY12 MY8 3 4 4 3 MY12 MY4 5
<32> MY12 MY11 MY7 MY11 MY5
<32> MY11 5 6 6 5 6 <32> FANSIG
MY10 MY6 7 8 8 7 MY10 MY6 7
<32> MY10 MY9 MY7 +5V
<32> MY9 8
MY8 180PX4 180PX4 MY8 9 U11 CN33
<32> MY8
MY7 MY9 10 2 3 TH_FAN_POWER
D <32> MY7 MY6 MY10 VIN VO 1 D
CA9 CA7 11 5
<32> MY6 GND 2
MY5 MX0 2 1 1 2 MY17 MY11 12 1 6
<32> MY5 <3> CPUFAN#_ON /FON GND 3 6
MY4 MX1 4 3 3 4 MY16 MY12 13 7 C52 C43 C49
<29,32> MY4 GND 4 7
MY3 MX2 6 5 5 6 MY15 MY13 14 4 8 <38> Thermistor_CTRL
<32> MY3 <32> CPUFAN# VSET GND 5
MX7 MX3 8 7 7 8 MY14 MY14 15 2.2U/10V_8 .01U/16V_4 *.01U/16V_4
<29,32> MX7
MX6 MY15 16 G995 FAN_CON
<29,32> MX6
MY2 180PX4 180PX4 MY16 17
<32> MY2 MX5 MY17
<29,32> MX5 18 FANPWR = 1.6*VSET
MX4 CA8 CA4 MX7 19 +5V
<29,32> MX4
MX3 MX4 2 1 2 1 MY5 MX6 20
<32> MX3
MX2 MX5 4 3 4 3 MY4 MX5 21
<29,32> MX2
MY1 MX6 6 5 6 5 MY3 MX4 22 C37
<32> MY1 MY0 MX7 MY2 MX3
<29,32> MY0 8 7 8 7 23
MX1 MX2 24 27 2.2U/10V_8
<29,32> MX1
MX0 180PX4 180PX4 MX1 25 28
<29,32> MX0 MY16 MX0
<32> MY16 26
MY17
<32> MY17
Aces 88502-2641
LED CABLE DOCK CN34
LIN_IN_DT# 33 LINEIN_JD <25,26>

+3V <20> D_DVICLK+ 2 DVI_CLK LIN_IN_L 34 AU_LINEIN_L <26>
R574 *D@390_6D_LINEOUT_L 3 35
<26> AU_LINEOUT_L <20> D_DVICLK- DVI_CLK# LIN_IN_R AU_LINEIN_R <26>
C R280 R575 *D@390_6D_LINEOUT_R 5 C
<26> AU_LINEOUT_R <20> D_DVITX0+ DVI_TX0
<20> D_DVITX0- 6 DVI_TX0# MIC_DT# 36 MIC1_JD <25,26>
5
10K_4 1 8 37
<20> D_DVITX1+ DVI_TX1 MIC_L AU_MIC_IN_L <26>
4 SATA_LED#_R 9 38
SATA_LED#_R <29> <20> D_DVITX1- DVI_TX1# MIC_R AU_MIC_IN_R <26>
<12> SATA_LED# 2 <20> D_DVITX2+ 11 DVI_TX2
U26 12 41
3
<20> D_DVITX2- DVI_TX2# SPDIF SPDIF_DOUT <25>

<18,20> HDMI_HP_A 25 DVI_DT
TC7SH08FU 26 56
<18,20> HDMI_DDCDATA DVI_DDCDT LAN_0 TX0P_PR <22>
<18,20> HDMI_DDCCLK 27 DVI_DDCCK LAN_0# 57 TX0N_PR <22>
LAN_1 59 TX1P_PR <22>
R278 *0_4 14 60
<19> VGA_RED_PR VGA_R LAN_1# TX1N_PR <22>
HDMI_HP_A R20 *D@100K_4
<19> VGA_GRN_PR 16
18
VGA_G LAN_2 43
44
TX2P_PR <22> To LAN
<19> VGA_BLU_PR VGA_B LAN_2# TX2N_PR <22>
<19> CRT_VSYNC1 28 VGA_VS LAN_3 62 TX3P_PR <22>
<19> CRT_HSYNC1 29 VGA_HS LAN_3# 63 TX3N_PR <22>
<19> DDCCLK_1 30 VGA_DDCCK LAN_PWR 52
+PWR_TRANSF
TM & LOW COST BEGA0017ZA0 <19> DDCDAT_1 31 VGA_DDCDT LAN_ACT 53 D_ACTLED# <22>
10/03: Follow ZY5 54 D_LINKLED# <22>
LAN_LINK
,Add R7432 & R580 <25,26> LINE_JD 23 HP_DT#
AS BEAB0019ZA0 D_LINEOUT_L 21 64
+3VPCU D_LINEOUT_R HP_L GND
22 HP_R GND 1
GND 4
Rev:B LED7 Change to SP@ <22,25,32> DOCKIN# 40 7
10/12 : BOM modify R22 *D@1K_4 DOCKIN2# 20 DOCK_DT1# GND
DOCK_DT2# GND 10
LED7 13
R53 330_6 GND
1 4 SUSLED# <29,32> GND 15
<19,32> CRT_SENSE# D43 *D@MTW355 51 17
VGA_DT# GND
2 3 PWRLED# <29,32> GND 19
Rev:B ,Add D43 for <29,30,32> USBON# 49 USB_EN# GND 42
SP@LED_DUAL_LIGHT customer request 48 45
B <13> USBP10- USB# GND B
<13> USBP10+ 47 USB GND 46
GND 55
LED8 DCIN +5V 32 58
R56 330_6 5V_S0 GND
1 4 BATLED1# <32> +5V_S5 68 P3-5V_USB, 3A GND 61
1 2 VA1 67 69
D12 *D@SW1010C P4-19V, 5A GND
2 3 BATLED0# <32> GND 70
VA2 71
C32 C20 C13 GND
LED_DUAL_LIGHT 2 72
GND
3 GNDA 24
1 *D@.1U/25V_4 *D@.1U/25V_4 *10U/25V_8 39
D14 *D@PDS1040S GNDA
P1-GND 65
50 RESERVED P2-GND 66
GND 73
GND 74
Rev:B ,change 0603 to 0402
REV:B, CN14 change footprint Rev:C ,change
1208 to 0805 *D@JAE CONN +PWR_TRANSF
T/P
+5V
+5V
Rev:B ,Add
L32 C133 C126
+5V
BLM21P300S C609 +5V *D@.01U/16V_4 *D@.01U/16V_4
*D@.1U/10V_4
+TPVDD
+3V_S5 R24
C379 Close Dock
R339 R345 *D@10K_4
A .1U/16V_4 CN14 A
10K_4 10K_4 R23
1 +5V_S5 PR_INSERT_5V <19,20>
2
3
L33 LZA10-2ACB104MT TPDATA_R *D@100K_4
<32> TPDATA TPCLK_R 3
L34 LZA10-2ACB104MT
<32> TPCLK 4
5
6
7
8
C606 C608 DOCKIN# 2 Q9 Quanta Computer Inc.
C396 C384
ACES_88058-0601 *D@.1U/10V_4 *D@.1U/10V_4 C21 *D@2N7002
*.01U/16V_4 *.01U/16V_4 PROJECT : ZY2 & ZY6
*D@.1U/10V_4 1
FAN,LED,KB,DEBUG PORT,TP
Tuesday, August 12, 2008 Sheet 31 of 40
1A
5 4 3 2 1

+3VPCU L36 BK1608HS220_6_1A +A3VPCU I/O ADDRESS SETTING

C441 C440 +3V I/O Address
30mil
.1U/16V_4 *10U/6.3V_8 BADDR1-0 Index Data
+3VPCU E775AGND 00 XOR TREE TEST MODE
C453 C457
01 CORE DEFINED
4.7U/6.3V_6 .1U/16V_4
C442 C461 C447 C399 C468 C398 10 2Eh 2Fh
115
102
U33
19
46
76
88
4
4.7U/6.3V_6 .1U/16V_4 .1U/16V_4 .1U/16V_4 .1U/16V_4 .1U/16V_4 11 164Eh 164Fh
VCC1
VCC2
VCC3
VCC4
VCC5
AVCC
VDD
D
SHBM=0: Enable shared memory with host BIOS D
LFRAME# 3 97 BADDR0 CCD_POWERON R380 10K_4

<12,23> LFRAME# LFRAME GPI90/AD0 TEMP_MBAT <33>
LAD0 126 98 TEMP_ABAT T57
<12,23> LAD0 LAD1 LAD0 GPI91/AD1 uR_SOUT_CR
127 99 BADDR1 R365 *10K_4
<12,23> LAD1 LAD1 GPI92/AD2 PCIE_WAKE# <14,21,23>
LAD2 128 A/D 100
<12,23> LAD2 LAD3 LAD2 GPI93/AD3 DIGVOL_UP ICMNT <33> RF_EN
1 108 SHBM R411 10K_4
<12,23> LAD3 PCLK_591 LAD3 GPIO05/AD4 DIGVOL_DN DIGVOL_UP <25>
For PCICLK <2> PCLK_591 2 LCLK GPIO04/AD5 96 DIGVOL_DN <25>
C451 .1U/16V_4
8 C448 .1U/16V_4 1/13 Comfirm by vendor mail :
<14,27> CLKRUN# GPIO11/CLKRUN
101 CC-SET <33> Disabled ('1') if using FWH device on LPC.
PCLK_591 GPI94/DA0
<12> GATEA20 121 105 CPUFAN# <31>
GA20 GPI95/DA1 Enabled ('0') if using SPI flash for both system BIOS and EC firmware
D/A GPI96/DA2
106 NC_EN# <29>
<12> RCIN# 122 107 CV-SET <33>
KBRST GPI97/DA3
SM BUS PU
R387 PU +3V for SCI D37 2 1 BAS316 SCI#_uR 29 LPC
<14> EC_SCI# ECSCI/GPIO54
64 +3VPCU
EC_FPBACK# GPIO01/TB2 ACIN <18,33>
22_4 6 95
<19> EC_FPBACK# GPIO24/LDRQ GPIO03/AD6 NBSWON# <29>
93 MBCLK R416 4.7K_4
ARCADE_KEY GPIO06 LID591# <14,19,29> MBDATA
124 94 R417 4.7K_4
<29> ARCADE_KEY GPIO10/LPCPD GPIO07/AD7 SUSB# <14>
119 MXM_SMCLK <18,20>
C450 PLTRST# GPIO23/SCL3 2ND_MBCLK R418 4.7K_4
<13,18,21,23,28,29> PLTRST# 7 LREST GPIO30/CIRTX2
109 SUSLED# <29,31>
10P_4 120 2ND_MBDATA R375 4.7K_4
GPIO31/SDA3 MXM_SMDATA <18,20>
USBON# 123 65
<29,30,31> USBON# GPIO67/PWUREQ GPIO32/D_PWM BATLED0# <31>
66 MXM_SMCLK R378 *4.7K_4
GPIO33/H_PWM BATLED1# <31>
SERIRQ 125 15 MXM_SMDATA R379 *4.7K_4
<14,27> SERIRQ SERIRQ GPIO36/TB3 VRON <35>
16 MAINON <36,37,38,39>
GPIO40/F_PWM PWROK_MXM +3V
PU +3V for SMI <14> KBSMI# 9
GPIO65/SMI GPIO42/TCK
17 PWROK_MXM <18>
GPIO GPIO43/TMS
20 AMP_MUTE# <26>
CRT_SENSE#
21 R410 4.7K_4
MX0 GPIO44/TDI
<29,31> MX0 54 22 SUSON <37,39>
MX1 KBSIN0 GPIO45/E_PWM
<29,31> MX1 55 23 ENERGY_DET <21>
MX2 KBSIN1 GPIO46/CIRRXM/TRST HP_MUTE#
<29,31> MX2 56 24 T63
MX3 KBSIN2 GPO47/SCL4
C <31> MX3 57 25 D/C# <33> C
MX4 KBSIN3 GPIO50/TDO
<29,31> MX4 58 26 S5_ON <34,39>
KBSIN4 GPIO51/TA3
ACER ID
MX5 59 27
<29,31> MX5 MX6 KBSIN5 GPIO52/CIRTX2/RDY HWPG
60 28 +3VPCU
<29,31> MX6 MX7 KBSIN6 GPIO53/SDA4 DNBSWON#_uR U34
61 91 D30 BAS316
<29,31> MX7 KBSIN7 GPIO81 DNBSWON# <14>
110 2ND_MBCLK 6 1
GPO82/TRIS BT_POWERON# <22> SCL A0
MY0 53 112 CCD_POWERON 2ND_MBDATA 5 2
<29,31> MY0 KBSOUT0/JENK GPO84/BADDR0 CCD_POWERON <19> SDA A1
MY1 52 80 3
<31> MY1 KBSOUT1/TCK GPIO41 DOCKIN# <22,25,31> A2
MY2 51
<31> MY2 MY3 KBSOUT2/TMS
<31> MY3 50 7 8
MY4 KBSOUT3/TDI WP VCC
<29,31> MY4 MY5
49
KBSOUT4/JEN0 KB GPIO56/TA1
31 MUTE_BEEP <25> GND
4
48 117 C469
<31> MY5 KBSOUT5/TDO GPIO20/TA2
MY6 47 63 24LC08
<31> MY6 KBSOUT6/RDY GPIO14/TB1 FANSIG <31>
MY7 43 .1U/16V_4
<31> MY7 KBSOUT7
MY8 42 TIMER 32
<31> MY8 KBSOUT8 GPIO15/A_PWM CONTRAST <19>
MY9 41 118
<31> MY9 KBSOUT9 GPIO21/B_PWM NUMLED# <29>
MY10 40 62
<31> MY10 KBSOUT10 GPIO13/C_PWM PWRLED# <29,31>
MY11 39 81
<31> MY11 KBSOUT11 GPIO66/G_PWM CAPSLED# <29>
MY12 38
<31> MY12 KBSOUT12/GPIO64
SPI FLASH
MY13 37
<31> MY13 KBSOUT13/GPIO63 +3VPCU
MY14 36 84 CRT_SENSE#
<31> MY14 KBSOUT14/GPIO62 GPIO77/SPI_DI CRT_SENSE# <19,31> +3VPCU
MY15 35 SPI 83 RF_EN
<31> MY15 KBSOUT15/GPIO61/XOR_OUT GPO76/SPI_DO/SHBM RF_EN <23>
MY16 34 82 U32
<31> MY16 GPIO60/KBSOUT16 GPIO75/SPI_SCK CELL-SET <33>
MY17 33 SPI_SDI_uR 2 8
<31> MY17 GPIO57/KBSOUT17 SO VDD
75 RSMRST#_uR R414 0_4 R390 SPI_SDO_uR 5 7 C444
MBCLK GPIO72/IRRX1/SIN2 RSMRST# <14> SI HOLD
<33> MBCLK 70 73 SUSC# <14>
MBDATA GPIO17/SCL1 GPIO70/IRRX2_IRSL0 PWROK_EC_uR R415 0_4 10K_4 SPI_SCK_uR .1U/16V_4
<33> MBDATA 69 74 PWROK_EC <14> 6 3
FOLLOW INTEL ME-EC INTERFACE SPECIFICATION, 2ND_MBCLK GPIO22/SDA1 GPIO71/IRTX/SOUT2 R518 0_4 SCK WP
2ND_SMB IS DEDICATED FOR ICH8 CONTROLLER LINK BUS. <3> 2ND_MBCLK
2ND_MBDATA
67
GPIO73/SCL2 SMB IR GPIO87/CIRRXM/SIN_CR
113
CIRRX2 NC_TEMP <38> SPI_CS0#_uR
<3> 2ND_MBDATA 68 14 1 4
GPIO74/SDA2 GPIO34/CIRRXL CE VSS
114
GPIO16/CIRTX uR_SOUT_CR 1009: Add. W25X80VSSIG
111
TPCLK GPO83/SOUT_CR/BADDR1
<31> TPCLK 72
+3VSUS TPDATA GPIO37/PSCLK1
<31> TPDATA 71
GPIO35/PSDAT1 1/13 Comfirm by vendor mail :
RP48 10K_10P8R 10 86 SPI_SDI_uR_R
B <33> CHG-EN GPIO26/PSCLK2 F_SDI If the Southbridge enables 'Long Wait Abort' by default, the B
10 1 MX3 T55 TB2DATA 11 PS/2 87 SPI_SDO_uR_R R407 22_4 SPI_SDO_uR Near Flash
MX4 9 2 MX2
GPIO27PSDAT2 F_SDO SPI_CS0#_uR flash device should be 50MHz (or faster)
MX5 8
12
GPIO25/PSCLK3 FIU F_CS0
90
3 MX1 13 92 SPI_SCK_uR_R R391 22_4 SPI_SCK_uR SPI_SDI_uR_R R565 22_4 SPI_SDI_uR
MX6 7 GPIO12/PSDAT3 F_SCK
4 MX0
MX7 6 5 E775_32KX1 77 30 ECDB_CLOCK
32KX1/32KCLKIN GPIO55/CLKOUT T64
85 VCC_POR# R409 4.7K_4 +3V
VCC_POR +3VPCU
H/W POWER GOOD
+3VSUS
VCORF
AGND
GND1
GND2
GND3
GND4
GND5
GND6
R413 20M_6 E775_32KX2 79 104 VREF_uR R381 0_4 +A3VPCU

32KX2 VREF R408
REV: B D34 Change to E@
R412 WPCE775
5
18
45
78
89
116
103
VCORF_uR 44
10K_4
Y10 33K/F_4
1 4 D34 *E@BAS316
<39> HWPG_2.5V
C445 .1U/16V_4 D28 D2@BAS316
<39> HWPG_1.5V
C446 .1U/16V_4
C466 32.768KHz C462 C467 D36 *D3@BAS316 HWPG
<38,39> HWPG_1.8V
L37
18P_4 18P_4 1U/10V_4 D35 BAS316
<36> HWPG_1.05V
R422
E775AGND BK1608HS220_6_1A D31 BAS316
<6,37> HWPG_VDR
0_4
D32 BAS316
<34> SYS_HWPG
MPWROK <6,14>
E775AGND D33 *BAS316
<3,6,14,35> DELAY_VR_PWRGOOD
+3VPCU +3VPCU REV: B remove D33
CIR
08/10 FAE:
L43 CAN CHANGE FROM BEAD TO
TM & LOW COST N
INTERNAL KEYBOARD STRIP SET
R459 R460
A SHORT. AS Y A
BUT, PLEASE PUT AGND & 32K CAP & *10K_4 *10K_4 +3VPCU
AVCC CAP AT ONE POINT.
Q37 U37 MY0 R419 10K_4
+5VPCU
ZS1 STILL USE BEAD FOR SAFE.
2
*RHU002N06 CIRR_X2 1
R456 *SP@47_6 2
CIRR_X2 3 1 CIRRX2 3
C523 4
*SP@4.7U/10V_8
5 Quanta Computer Inc.
R461 *SP@0_4
PROJECT : ZY2 & ZY6
*SP@EVER_IRM-V038_TRI-P Size Document Number Rev
1A
WPCE775C_0DG & FLASH
5 4 3 2 1

Rev. B for EMI

PJ7 PF7 PL8
VA PD7
PDS1040S-13
VA2 PR14
0.02_7520
R1 PQ9 PC181 PC179 PC180 VIN PQ43
DCJK-2DC-G756-X06-5P-H LITTLE-7A-1206 HI0805R800R-00_8 1 FDD6685 1U/25V_6 1U/25V_6 1U/25V_6 FDD6685
1 1 2 3 1 2 3 4 3 4
2 2
3 PC164
PC7 PC9 PC8 0.1U/50V_6 PR187
1
1
PC10 PC11 PC16 PR18 PC122
33K_6
0.1U/50V_6 0.1U/50V_6 2200P/50V_6 PL7 0.1U/50V_6 0.1U/50V_6 0.1U/50V_6 220K/F_6 PC178 PC177 PC176 PC175 2200P/50V_6
5
4
SP@POWER_JACK
HI0805R800R-00_8
Rev. B 1U/25V_6 1U/25V_6 1U/25V_6 10U/25V_1206
D D
2
Rev. B PR188
1 6
PD9 PR189 0_6 10K_6
SW1010CPT PD11 PR19 2 5 D/C# <32>
220K/F_6
PR7 PD8 *ZD12V DCIN P4SMAJ20A 3 4
3
*10K/F_6
ACIN_1 2 1 PQ7
<18,32> ACIN
IMD2AT108
2
PR9
PR10 *10K/F_6 PQ44
*6.8K/F_6 DMN601K-7
+3VPCU
1
PL13 VIN
HI0805R800R-00_8
PC71 VA3
2.2u/10V_8
PR196 ISL6251_VDD 1 2
4.7K/F_6 PR98 PR99
2.2/F_6 20/F_6
PR96
PC68 4.7_6 PC67
Input sense resistor and Constant PR197 0.1U/50V_6 4.7U/10V_8
100K/F_6 ISL6251_VDDP 1 2
power setting table
3
PC154 PC155
C CSIP CSIN 0.1U/50V_6 10U/25V_1206 C
5
6
7
8
Rev. B PD16 PC153
19
20
15
1
2 Rev. B PR100
RB500V-40 2200P/50V_6
65W 90W
CSIP
VDDP
CSIN
VDD
PQ49 20/F_6 PR101 PC66 4
DMN601K-7 6251LR CSOP 21 2.7_6 .1U/50V_8 PQ42
CSOP
20m Ohm 20m Ohm 16 6251B_2 6251B_1 FDS8878
1
BOOT
2
PC69 PR186
R1 47N/25V_6 0.03_3720
CS+020AGM00 CS+020AGM00 17 ISL6251_UGATE PL14
1
BAT-V CSON 22 UGATE 6R8UH
3
2
1
PR97 20/F_6 CSON 6251LR 1 BAT-V
71.5K Ohm 6.19K Ohm ISL6251_PHASE
2
R2 PHASE
18
5
6
7
8
CS37153F917 CS26193F929
PC162 10U/25V_1206
2
PU11
ISL6251A LGATE
14 ISL6251_LGATE
PR183
Rev. B PC160
10K Ohm 10K Ohm PR201 0_6 PC70
23
ACPRN
4
.01U/50V_6
R3 PR102 0.1U/50V_6 PQ41 *2.2_6
CS31003F949 CS31003F949 6251EN 10/F_6 PGND
13
1
24 12 FDS6690AS
PR202 DCIN GND PC156 PC161
<32> CHG-EN 100K/F_6 PR103 2200P/50V_6 PC163
3
2
1
82.5K/F_6 11 *2200P/50V_6 10U/25V_1206
VADJ
Rev. B 6251ACSET 2
ACSET
PC158 10 VREF
ACLIM
100P/50V_6
Rev. B PR104 3
EN
VCOMP
TEMP_MBAT 10K/F_6
ICOMP
CELLS
CHLIM
B TEMP_MBAT <32> B
VRFE
PR111 PR120
R2
ICM
HI0805R800R-00_8 *514K/F_6
CN23 PF8 PL15 SP@71.5K/F_6
MBAT+ 1 2 BAT-V Float = 4.2V / CELL
6251ICOMP 5
9
1 PD21 RB500V-40 VADJ
2 BUS-10A-1206 PR133 CV-SET <32>
3 PL16 *10K/F_6 ACLIM PR121 *0_6
8 4
PC159
HI0805R800R-00_8 ISL6251_VDD 6251EN VREF

9 5
PC64 47P/50V_6
PC79 .01U/50V_6
PR184
6251VCOMP1
6 CC-SET <32>
1
PC65 47P/50V_6
PR195 *0_6 100K/F_6 PR131 PR114 PR119

7
SUYIN_BATTERY
Rev. B +3VPCU
10K/F_6
6251CELLS_1 PC77
R3 10K/F_6
*514K/F_6
2
0.1U/50V_6
100P/50V_6
6251CELLS_1
10mil PR132
3
10K/F_6
PR110
PR115 100_4
PR95 PR94 *0_6 6251CELLS_2 2 6251VCOMP2 ICMNT
ICMNT <32>
100_4 100_4
3
PR112 LIM = (1/R1)*(((0.05/VREF=2.39)VACLM)+0.050)

PC78 *100P/50V_6
MBCLK <32> PQ26 3.3K/F_6

DMN601K-7 CURRNT LIMIT POINT =(90w/19v)*0.85= 4.026A
1
2
<32> CELL-SET 2
MBDATA <32> PR127 PC81 4.026A=(1/0.02)((0.05/2.365)Vaclm+0.05)
PQ27 100K/F_6 PC82 3300P/50V_4
1
PR122 DMN601K-7 .01U/50V_6 Vaclm=((R3//152)/(R3//152+R2//152))*Vref
1
+3VPCU 100K/F_6
1
A A
R1=adapter current sense resistnece
1
PR185 PC157
1
PD15 PD14 *100K/F_6 .01U/50V_6

ZD3.6V ZD3.6V
2
3TEMP_MBAT
PD20 PROJECT : ZY2/ZY6

*DA204U
2

Add ESD diode base on CELL-SET = Hi ----> Cells = VDD ---->4S Size Document Number Rev
EC FAE suggestion CELL-SET = Low ----> Cells = GND ---->3S Custom 1A
CHARGER (ISL6251A)
5 4 3 2 1

MAIND
5 4 http://laptopblue.vn/ 3
+3VPCU
2 1
MAIND <37,39>
SUSD PR123
SUSD <39>
10K/F_6
1 2 DDPWRGD_R 1 2
<3,38> SYS_SHDN# SYS_HWPG <32>
PR124 0_4 PR130 0_4
D VIN VIN D
VL
+ VL PC116
10U/25V_1206
2
PC128
PC139 10U/25V_1206 PC89
2
100U/25V_6X7.7 PR136 4.7U/10V_8
1
390K_4 PR142
1
0_4
PR126
39K/F_4 PC96 PC118 PC119
1
2
PC117 PC120 PC123 PC92 PC94 1U/16V_6 0.1U/50V_6 2200P50V_4
0.1U/50V_6 2200P/50V_6 *10U/25V_1206 0.1U/50V_6
*.01U/16V_4
5
6
7
8
1
REFIN2
PR141
*0_6
PR147
0_4
PC99
Rev. C for Margin TEST
0.1U/50V_6
3V5V_EN 4
REF 2 1 3V_DH PQ28
1
8
7
6
5
AO4468
PR138 *0_4
115K_4 PR203
8
7
6
5
4
3
2
1
4 5V_DH +3VPCU
PQ33 PL9
LDO
ONLDO
LDOREFIN
VIN
NC
VCC
TON
REF
3
2
1
AO4468 2R2UH-5.8mR
+3VPCU
PR153 3V_LX
5
6
7
8
+5VPCU +5VPCU
9 32 REFIN2 249K/F_6
BYP REFIN2
1
PL11 10 31 1 2
1
2
3
2R2UH-5.8mR OUT1 PU13 ILIM2 PR166
C 11 FB1 OUT2 30 C
+5VPCU 5V_LX 1 2 12 29 SKIP 4 *2.2_6
PR125 237K/F_6 DDPWRGD_R 13 ILIM1 ISL6237 SKIP# DDPWRGD_R
PGOOD1 PGOOD2 28
2
8
7
6
5
PR175 3V5V_EN 14 27 3V5V_EN PR154 +
2
EN1 EN2
PC76 *330U/6.3V_7343
PR128 15 26 0_6 PC126

DH1 DH2
PC148 330U/6.3V_6X5.7
PC151
*0_4 *2.2_6 16 25 0.1U/50V_6 PC121

+ + 5V_DL LX1 LX2 PC115 330U/6.3V_6X5.7
4 37 PAD
36 PQ29 *2200P/50V_6
1
3
2
1
PAD
PGND
PVCC
PC144 PQ34 AO4712
BST1
BST2
GND
PAD
PAD
PAD
DL1
DL2
0.1U/50V_6
10U/25V_1206 AO4712 PC86 PC100
NC
2
PC137 0.1U/50V_6 0.1U/50V_6

PR129 *2200P/50V_6 PR148
35
34
33
17
18
19
20
21
22
23
24
0_4 PR134 1/F_6
1
2
3
1/F_6 1 2
1 2 3V_DL PR150
1
*0_6
VL PR140 SKIP PR155 *0_6 REF

PC84 0_6
2 0.1U/50V_6
PC93 PR152 0_6
3 1U/16V_6
PD17
1 CHN217
PC85
0.1U/50V_6
PC72
0.1U/50V_6 2
3 PR118 *0_6 REFIN2

B B
PD18
1 CHN217
+15V_ALWP 1 2 +3VPCU
+15V
1
PR116 22_8 PR113 PR117
PC73 *200K_4 *39K_4
0.1U/50V_6
+5VPCU
2
VIN +15V
1
2
5
6
+5VPCU +3VPCU +3VPCU SUSD 3 PQ36
PR179 PR180 FDC653N_NL
1M_6 1M_6
5
6
7
8
4
S5D 4
5
6
7
8
5
6
7
8
1
2
5
6
3
+3VSUS
PQ40 S5D 3 PQ37
2 FDS8884 MAIND 4 MAIND 4 FDC653N_NL
<32,39> S5_ON
2
PR176
3
2
1
4
PQ38 1M_6 PQ39 PQ24 PQ30
1
DTC144EU DMN601K-7 FDS8884 FDS8884

+3V_S5
1
A A
3
2
1
3
2
1
+5V_S5
+5V +3V

PC182
1U/25V_6 Rev. B for EMI PROJECT : ZY2 / ZY6
SYSTEM 5V/3V (ISL6237)
Thursday, August 28, 2008 Sheet 34 of 40
1A
5 4 3 2 1

+3VPCU +3VPCU PC19

2200P/50V_6
VIN
1
PR20 PR21 PR22 PR24 PR25 PR26 PR28 + PC171
*0_6 *0_6 *0_6 *0_6 *0_6 *0_6 *0_6 PC17 100U/25V_6X7.7
2
0.1U/50V_6
2
DELAY_VR_PWRGOOD <3,6,14,32>
5
D D
PC24
H_VID6 H_VID5 H_VID4 H_VID3 H_VID2 H_VID1 H_VID0 10U/25V_1206 PC21
6266A_UG1 4 10U/25V_1206
VCC_CORE
1
2
3
PR80 4.99K/F_6 VIN +3V PQ12
PWR_MON 2 1 PGD_IN AO1414 PC174
PL19 0.36uH *560U/2V_7
6266A_PH1 1 2
1
1
PR46
1
PC52 10/F_6 PR60 PR63
4
5
5
0.1U/50V_6 10_4 1.91K/F_4 PR192 + PC15 +
2
+5V_S5 2.2_6
330U/2V_7343
2
1
6266A_LG1 4 6266A_LG1 4
2
<3> PSI# PSI# PC33
1
PR42 0.1U/50V_6
1
2
3
1
2
3
10/F_6 PC39 PQ50 PQ48 PC173
0.1U/50V_6 *AO1412 AO1412 2200P/100V_6
2
PR32 PR33
22
20
48
2
1
PR82 0_8 0_6 0_6
PC32
3V3
VCC
VIN
PGOOD
1U/25V_8
1 PR36 3.65K/F_6
VSUM
21 35
GND UGATE1 PR44 2.2_6 PR35 10K/F_6
Close to Phase 1 Inductor 49
GND_T BOOT1
36 1 2
1
Throttling temp. PR38 1/F_6
+3V_S5 PC30
105 degree C 0.22u/25V_8
2
C 34 PR37 *0_6 C
PSI# PR66 0_4 PSI#_1 PHASE1 ISEN2
2
PSI#
32
PR64 VR_ON PR65 *0_4 PGD_IN LGATE1
3 VIN
*10K/F_4 PGD_IN
33
PR68 147K/F_6 PGND1
4
RBIAS
1
24 ISEN1 PC22
ISEN1
1
<3> H_PROCHOT# 5 2200P/50V_6
VR_TT#
2
PR194 470K_4 NTC PR79 4.02K/F_4 6
2
NTC
+5V_S5
2
2 1 PC45 7 Rev:C Change PC29
PC51 1 0.033U/50V_6 SOFT PC27 0.22u/25V_6 PC25 PC28 PC20
2
5
.01U/16V_4 31 1 2 10U/25V_1206 10U/25V_1206 0.1U/50V_6
H_VID0 PVCC
Panasonic 37
VID0
<4> H_VID0 4.7U/25V_8
ERT-J0EV474J H_VID1 38 PU8 27 6266A_UG2 4
<4> H_VID1 VID1 UGATE2
ISL6262A PR40 2.2_6
H_VID2 39 26 1 2
<4> H_VID2
1
2
3
VID2 BOOT2 PQ14
1
PSI#_1 H_VID3 40 AO1414
<4> H_VID3 VID3 PC26
H_VID4 41 0.22u/25V_8 PL18 0.36uH
<4> H_VID4
2
VID4 6266A_PH2
28 1 2
H_VID5 PHASE2
<4> H_VID5 42
VID5
1
PR69 30 6266A_LG2
4
H_VID6 LGATE2 PR191
*0_6 <4> H_VID6 43
VID6
29 2.2_6
PR87 0_4 VR_ON PGND2 6266A_LG2 + PC18 + PC14
<32> VRON 44 4 4
VR_ON ISEN2
23
2
PR86 499/F_4 DPRSLPVR ISEN2 *560U/2V_7 330U/2V_7343
<6,14> PM_DPRSLPVR 45
1
2
3
1
2
3
DPRSLPVR
1
DPRSLPVR PQ47 PQ51 PC172
PR84 0_4 46 PC31 AO1412 *AO1412 2200P/100V_6
<3,6,12> ICH_DPRSTP# DPRSTP# 0.22u/25V_6
2
PR83 0_4 CLKEN# 47 PR49 PR55
<14> VR_PWRGD_CK410# CLK_EN# 0_6
PC43 1000P/50V_4 0_6
B PR67 1K/F_4 25 2 1 B
NC
VR_ON 8
OCSET PR76 13.3K/F_4
1 2 13
VDIFF
PR78 PC44 19 VSUM
PR198 255/F_4 1000P/50V_6 VSUM
10K/F_4 PR62 1K/F_4
12
FB2
1
Rev:C Change PR51 PR47

Rev:C Change 11K/F_4 2.7K/F_4
PC36 0.22u/10V_6
11 PC34
2
1
FB 68N/25V_6 PR50 3.65K/F_6

PR81 97.6K/F_4 PC50 470P/X7R/50V_4 VSUM
Rev. B 2 1
2
PR193 PR48 10K/F_6

10 10K _6 NTC
PC49 Rev:C Change COMP
2 1 PR56 1/F_6
18
220P/NPO/50V_4 PR70 6.81K/F_4 VO
Panasonic
DROOP
9 PR58 *0_6
VW ERT-J1VR103J
VSEN
ISEN1
RTN
DFB
Rev:C Change
1
Rev:C Change 1 2 PR52

1K/F_4 PC35 Close to Phase 1 Inductor
15
14
16
17
PC42 1000P/50V_6 0.22U/X5R/25V_6

2
PR54
PC40 2 1 3.48K/F_4 Rev:C Change
10n/X7R/16V_4
Rev:C Change Rev:C Change

PC37 180P/50V_4
2 1 ISL6262_VO
2
A PC38 PC41 A
10n/X7R/16V_4 .01U/16V_4
1
Rev:C Change Parallel

PR59 0_4
VCCSENSE <4>
VSSSENSE <4>
PR57 0_4

PROJECT : ZY2 / ZY6
Custom CPU CORE(ISL6266) 1A

5 4 3 2 1

A A
VIN
+5V_S5
PR71 10_6
PD13
Rev. B
RB500V-40
PC57
5
PR72 PC59
B 1M/F_6 *.1U/50V_6 B
4.7U/10V_8
2
PR88 4 PC168 PC170 PC169
0_6 0.1U/50V_6 10U/25V_1206 10U/25V_1206
1
2
3
PR85 47K_6 PC56 PQ46
<32,37,38,39> MAINON 15 13 .1U/50V_8 AO1414 Rev:B Change footprint
EN/DEM BOOT
+3V 16 12 UGATE-1.05V PL17
PC54 TON UGATE 1R5UH-3.9mR
0.1U/50V_6 1 11 PHASE-1.05V
VOUT PHASE +1.05V
5
2 10 PR93 3.24K/F_6
VDD OC OCP=14A
2
PR75 PU9
1
*10K/F_6 RT8202 PR190
3
FB VDDP
9 R1 LGATE-1.05V 4 2.2_6 +
PR73
<32> HWPG_1.05V 4
PGOOD LGATE
8 R2 PC47
1
2
3
2
6 7 PQ45 PC167 4.02K/F_6 *33P/50V_6
GND PGND AO1412
2200P/50V_6
5
NC TPAD
17 Rds*OCP=RILIM*20uA Rev:B ,Remove it.
14 R3
GND
GND
GND
GND
NC
1
PC46 PC53 PC55 PC165 PC166 PR74

1U/16V_6
AO1412 Rds=4.6mOhm 560U/2.5V_6X5.7 10U/10V_8 10K/F_6
2
18
19
20
21
14A OCP --- R1=3.24K(CS23243F930)
*1000P/50V_6 .01U/50V_6 VOUT=(1+R2/R3)*0.75

C 1.05V_FB C
TON=3.85p*RTON*Vout/(Vin-0.5)
Frequency=Vout/(Vin*TON)
D D

PROJECT : ZY2 / ZY6
VTT 1.05V (RT8202) 1A

1 2 3 4 5

D D
VIN
+VDR_SUS
5
PC88
10U/10V_1206 4
PU14
TPS51116 PC133 PC132 PC124
1
2
3
1 19 PQ32 Rev:B Change footprint 2200P/50V_6 10U/25V_1206 10U/25V_1206
VLDOIN DRVH AO1414
2 20 PC106 0.1U/50V_6
+VDR_VTT VTT VBST PL12
4 18 +VDR_SUS
PC91 PC87 VTTSNS LL
10U/10V_8 10U/10V_8 5 17 1.0UH-3.0mR
GND DRVL Rev:C 2.2/F_6 change to 1/F_6
3 16 +
VTTGND PGND PR170
5
DIS_MODE 6 11 S3_1.8V PR151 0_6
C MODE S3 MAINON <32,36,38,39> C
1/F_6
7 12 S5_1.8V PR163 0_6
+VDR_VREF VTTREF S5 SUSON <32,39>
4
PR135 5VIN 8 14 5VIN
0_6 PC90 COMP V5IN PR200 *10K/F_6 PC129 PC150 PC147
1
2
3
0.033U/50V_6 9 13 +3VPCU +3VPCU PQ35 1000P/50V_6 560U/2.5V_6X5.7 10U/10V_8
VDDSNS PGOOD AO1412
GND
GND
GND
GND
GND
GND
GND
5VIN 10
VDDQSET CS
15 PR164
SP@100K/F_6
Rev. B Rev:C 2200P change to 1000p
DDR2 -- OCP=14.25A
PR162
PR149
21
22
23
24
25
26
27
*0_6 PC104
R4 Rev: B D3@ change to 2K
R3 *1000P/50V_6 D2@ 100K DDR3 -- OCP=13.94A
5.62K/F_6
PR144 *0_6 DIS_MODE
+5VPCU
5VIN
HWPG_VDR <6,32>
(10u*R4)/Rdson+Delta_I/2=Iocp
1
PR165 PC108
0_6
+VDR_SUS PR137 0_6 4.7U/6.3V_6
2
PR139
PC95
R2 SP@110K/F_6 *33P/50V_6
S3_1.8V S5_1.8V
DDR2(1.8V) DDR3(1.5V) PR143

B R1 SP@76.8K/F_6 PC102 PC105 DDR3 -- NC B
*.1U/50V_6 *.1U/50V_6
76.8K 75K +VDR_SUS DDR2 -- NC
R1
CS37683F927 CS37503F919 +VDR_SUS
Rev. B
110K 76.8K
R2
CS41103F910 CS37683F927
5
6
7
8
1
2
5
6
4 PQ25
R1=(100*Vout-R2)K <34,39> MAIND PR108 3
ID2@0_8 <34,39> MAIND *D3@FDC653N_NL
PQ23
if tune Vout R3 un-mount, R1 and R2 mount *ED2@FDS8884
4
3
2
1
+1.5V
+1.8V
A A

PROJECT : ZY2 / ZY6
VDR (TPS51116) 1A

5 4 3 2 1

VIN
+5VPCU
PR172
A LGATE-1.8V A
*ED3@10_6
PD19
Rev. B PC134 PC125
*ED3@RB500V-40 *ED3@0.1U/50V_6 *ED3@10U/25V_1206
1
PC131
D1
D1
S2
G2
PR156 PC130
*ED3@1M/F_6 *.1U/50V_6
*ED3@4.7U/10V_8
2
PR174 PQ31
PU16 *ED3@0_6 *ED3@FDS6900AS
*ED3@RT8202
S1/D2
PC138
G1
PR145 *ED3@47K_6 15 13 *ED3@.1U/50V_8 OCP: 4A
<32,36,37,39> MAINON EN/DEM BOOT Rev:C Change footprint
8
+3V 16 12 UGATE-1.8V UGATE-1.8V PL10
PR146 PC98 TON UGATE *ED3@2.5UH_7.5A Rev.C for EMI 3.5A
*ED3@0.1U/50V_6 1 11 PHASE-1.8V
VOUT PHASE +1.8V
*10K/F_6 2 10 PR171 *ED3@3.01K/F_6
PR167 VDD OC
1
*ED3@10K/F_6 3
FB VDDP
9 R1 PR173 +
4 8 LGATE-1.8V PR169 PC127
<32,39> HWPG_1.8V PGOOD LGATE *2.2_6 PC183
R2
2
6 7 *ED3@14K/F_6 *ED3@33P/50V_6
1
GND PGND
5 17
Rds*OCP=R1*20uA PC136
NC TPAD *ED3@.1U/50V_8
*2200P/50V_6
14 4A OCP --- R1=3.01K
GND
GND
GND
GND
NC
1
1
PC135 PC101 PC97 PC140 PC146 PR168
*ED3@1U/16V_6 *ED3@10U/10V_8
R3
*ED3@560U/2.5V_6X5.7 *ED3@10K/F_6
B FDS6690AS Rds=15mOhm B
2
18
19
20
21
*1000P/50V_6 *ED3@.01U/50V_6 VOUT=(1+R2/R3)*0.75
1.8V_FB
TON=3.85p*RTON*Vout/(Vin-0.5)
Frequency=Vout/(Vin*TON)
thermal protection --0928
VL VL VIN VIN
PD22
Rev. B
RB500V-40
SYS_SHDN# <3,34>
C C
PR13 PR17
1.74K/F_4 200K/F_4 PR15
200K/_6
PC12
0.1U/50V_6
3
8
2.469V 3
+
1 2
<31> Thermistor_CTRL 2
- PQ8
PU7A DMN601K-7
4
LM393 PC13
1
0.1U/50V_6
PR16
200K/F_4
+3VPCU
VL
PR8
100K/F_6
PR11
Rev. B
10K/F_6 PU7B
PD10
5
+
7 NC_TEMP <32>
D 4.95V 6 D
-
RB500V-40
LM393
For EC control thermal protection (output 3.3V)
PR12
1M/F_6
PROJECT : ZY2 / ZY6
1.8V (RT8202) 1A

1 2 3 4 5

DDR3 -- NC
for DDR3 and UMA
+VDR_SUS
+3V_S5
+3VSUS
1
PR161
D D
PC113 PC112 100K_4
PR106
2
+5VPCU D2@10U/6.3V_8 D2@0.1U/10V_4 PU15
*ID3@100K_4 5 7
VIN POK HWPG_1.5V <32>
PU12
PC83 *ID3@0.1U/50V_6 4 1 9 1
VPP PGOOD HWPG_1.8V <32,38> VIN1 GND +1.5V
MAINON PR107 *ID3@10K/F_6 2 6
VEN VO +1.8V
+3VPCU 3 0.5A <32,36,37,38> MAINON PR157 D2@0_6 8 3 +1.5V <4,10,12,13,15,23,25,29,37>

VIN PC149 EN VOUT
8 GND
ADJ
+5V_S5
9 GND NC 5 R1 2.6A
1
PC80 PC75 PC74 PR109 6 4
*ID3@RT9025-25PSP PR159 PC103 VCNTL VOUT
FB
7
2
*ID3@10U/4V_8 *ID3@0.1U/50V_6 *ID3@0.1U/50V_6 *ID3@30.1K/F_6 PC184 PC110
100K_4 *.1U/50V_6 D2@APL5913
2
0.8V *ID3@10U/10V_8 *ID3@.1U/50V_8
Rev. B D2@1U/10V_4
1
PR160 D2@88.7K/F_4
R2
PR105 PR158
R1 PC111 PC114 PC109
Vout =0.8(1+R1/R2) Rev.C for EMI
=1.8V R2 *ID3@24K/F_6 D2@100K/F_4 10U/6.3V_8 10U/6.3V_8 0.1U/10V_4
Vout =0.8(1+R1/R2) PC107
1 2
D2@47NF/16V_4
=1.5V
C C
REV:B change to E@ +3VSUS
VIN +VDR_VREF +VDR_SUS +3VSUS +15V +5VPCU PR89
*E@100K_4
PU10 *E@RT9025-25PSP
PR31 PR23 PR27 PR29 PR34 PC63 *E@0.1U/50V_6 4
VPP PGOOD 1 HWPG_2.5V <32>
1M_6 22_8 22_8 22_8 1M_6
MAINON PR90 *E@10K/F_6 2 6
VEN VO +2.5V
SUS_ON_G SUSD +3VSUS 3 0.25A
SUSD <34> VIN
8
GND
ADJ
3
9 5
GND NC
3
PR91 PC61
PR30
R1
7
2 1M_6 2 2 2 2 *E@73.2K/F_6 *E@10U/10V_8
<32,37> SUSON PC23
PQ10 PQ11 PQ13 PQ16 *2200P/50V_4 0.8V
PQ15 DMN601K-7 DMN601K-7 DMN601K-7 DMN601K-7
1
DTC144EU PC62 PC60 PC58

1
*E@10U/4V_8 *E@0.1U/50V_6 *.1U/50V_6

PR92
Vout =0.8(1+R1/R2) R2 *E@34K/F_6
B
=2.5V B
+3VPCU
REV:B change to I@
+5VPCU PR178
*I@100K_4
PU17 *I@RT9025-25PSP
PC145 *I@0.1U/50V_6 4 1 HWPG_1.5VS5
VPP PGOOD
<32,34> S5_ON PR177 *I@10K/F_6 2 6
VEN VO +1.5V_S5
VIN +3VPCU 3
VIN 0.3A
+3V +5V +VDR_VTT +1.8V +15V 8 PR182 PC152
GND
ADJ
PR199
*10K/F_6
9
GND NC
5 R1 *I@88.7K/F_4 *I@10u/10V_8
7
PR43 PR39 PR45 PR53 PR61 PR77 0.8V
1M_6 22_8 22_8 22_8 *E@22_8 1M_6
PC141 PC143 PC142

MAINON_ON_G MAIND *I@10U/4V_8 *I@0.1U/50V_6 *I@0.1U/50V_6 PR181
MAIND <34,37>
Rev. B R2
3
*I@100K/F_4
Vout =0.8(1+R1/R2)
3
A A
PR41
1M_6
=1.5V
<32,36,37,38> MAINON 2 2 2 2 2 2
PC48
PQ17 PQ19 PQ20 PQ21 PQ22 *2200P/50V_4
PQ18 DMN601K-7 DMN601K-7 DMN601K-7 *E@DMN601K-7 DMN601K-7
1
DTC144EU
1

REV:B change to E@ PROJECT : ZY2 / ZY6
Discharge (2.5V/1.5V) 1A

5 4 3 2 1

Power Tree Table 2 DDR2 --> 1, 2, 3, 4, 5, 7, 8, 9, 10, 11, 12, 13, 16

ISL6262A VCC_CORE
P.36 VRON enable DDR3 & UMA --> 1, 2, 3, 4, 5, 7, 8, 9, 10, 11, 14, 15, 16
1 7
AC System FDS8884 +5V_S5
+5VPCU P.35 S5_ON enable DDR3 & MXM --> 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 14, 16
Charger AC/DC Insert enable
ISL6251A
DC P.34
D 8 D
3 FDS8884 +5V
ISL6237 P.35 MAINON enable +1.8V
P.35 15 MAINON enable
RT9025-25PSP
+3VPCU P.40
AC/DC Insert enable 9
FDS8884 +3V
P.35 MAINON enable
4
10
RT8202 +1.05V FDS653N_NL +3V_S5
P.37 MAINON enable P.35 S5_ON enable
+VDR_VTT +3VSUS
11 SUSON enable 16
5 MAINON enable FDS653N_NL RT9025-25PSP +2.5V
TPS51116 +VDR_VREF P.35 P.40 MAINON enable
C C
P.38 MAINON enable

+VDR_SUS +1.8V
12 MAINON enable
SUSON enable FDS8884 +1.8V
P.38 MAINON enable
13
APL5913 +1.5V
P.40 MAINON enable
14
FDS653N_NL
+1.8V P.38
6 MAINON enable
RT8202
P.39
B
Power Distribution List B
Power Distribution
VCC_CORE CPU
+5VPCU ICH8M, RJ45/USB /B, USB/eSATA, Satellite LED, CIR
+3VPCU RTC, HALL SENSOR, KB, TP/FP/LED /B, Power /B, Kill SW, EC, ID, SPI Flash, CIR
+1.5V CPU, GMCH, ICH9M, Mini Card, New Card
+VDR_SUS GMCH, DDR
+VDR_VREF GMCH, DDR
+VDR_VTT DDR
+1.05V CPU, CLK, Thermal Trip, GMCH, ICH8M
+5V_S5 ICH8M, G-SENSOR, Felica, USB/eSATA
+5V CPU, ICH8M, VGA, Camera, CRT, HDMI, SATA HDD, PATA ODD, PCMCIA, TP/FP/LED /B, EC, Speaker, Headphone
A
CLK, CPU Thermal Monitor, FAN, GMCH, DDR, ICH8M, VGA, LCD/LED Panel, HALL SENSOR, CRT, HDMI, SATA HDD, PATA ODD, PCMCIA, Cardreader (OZ129T) A
+3V
Mini Card, KB, TP/FP/LED /B, RJ45/USB /B, Bluetooth, MMB, New Card, PC BEEP, EC, Codec (CX20561), VR, Headphone, MDC
+3V_S5 ICH8M, Mini Card, RJ45/USB /B, New Card
+3VSUS ICH8M, FP
+1.8V Cardreader Quanta Computer Inc.
+2.5V MXM http://hobi-elektronika.net Size Document Number
PROJECT : ZY6D
Rev
1A
Power Tree Table
5 4 3 2 1

5 4 http://laptopblue.vn/
3 2 1
MODEL
ZY2
Model REV CHANGE LIST FROM To
X 1A
1A FIRST RELEASED: E200610-3793 (PCB: ) X 1A
ZY2 MB Page2 : Add R475 ,531 & R532 to avoid active error. (follow CK505 design guideline)
1A 2A
1A 2A
Page2 : Swap SRC4 & SRC9, because NEW_CLKREQ# is only to control SRC1 or 4
. 1A 2A
Page3 : Add R540 to avoid active error. (CPU Thermal monitor)
D 1A 2A D
Page6 : Follow DDR3 spec R251 change to 10K.
1B 1A 2A
Page18 : POP C282 &C284 and RSVD. C604 for DDR3 PCB boot issue.
1A 2A
Page18 : HDA_RST# PIN change from 151 to 134 for customer request.
1A 2A
Page18 : Swap Net:TX0 &TX2 (RN15 & RN17) For HDMI no function issue.
1A 2A
Page20 : Add R527 ,R528 ,R529 ,R530 ,R539 ,R148 ,R153 ,R152 ,R104 & R105 for vendor request.(HDMI level shifter)
1A 2A
Page20 : Change HDMI SW IC ( U9 ) & schematic
1A 2A
Page23 : Add R536 ,R542 ,R538 ,RP57 ,R537 customer request.(MINI PCI-E card function)
1A 2A
Page25 : Add Intel Low Power ECR Solution(Audio)
1A 2A
Page28 : Add part for D3 Enhanced (D3E).(cerd reader)
1A 2A
Page29 : Add Keyboard LED function for customer request.
1A 2A
Page30 : Location :C25 & C23 change to 100U & POP it for customer request.(USB)
1A 2A
Page31 : Add D43 for customer request( FOR Dock :CRT _SENSE#)
1A 2A
Page31 : CN12 & CN14 change footprint.(K/B & T/P CONN.)
1A 2A
Page31 : Add C609 ,C606 & C608.(FOR DOCK : +5V & +5V_S5)
1A 2A
1A 2A
Page19 : change U22 LVDS PWR SW IC to TI for display isuue
1A 2A
Page21 : remove 5787 schematic
2A 1A 2A
Page23 : Add C605 ,C70 ,C150 ,C613 &C614 for EMI request
1A 2A
C Page23 : Change CN27 CONN. & schematic for intel WL burnout issue C
1A 2A
Page25 : Change U13 packing from TQFN to TDFN for vendor request
1A 2A
Page20 : Add R566 ,R567 ,R568 ,R569 ,C612 ,C616 ,C617 ,C618 solve the HDMI EMI issue. 1A 2A
2B
Page26 : Change CN41 PIN 7 & 8 from ADOGND to NC solve the ESD issue. 1A 2A
Change CN42 PIN 7 & 8 from ADOGND to NC solve the ESD issue. 1A 2A
Page30 : Add D47 ,D48, D49 & D50 solve the USB ESD issue. 2A 2B
Page31 : Add R574 & R575 (390 )solve Docking audio noise issue. 2A 2B
Page32 : Add EMI resistor (R565) in SPI flash interface. 2A 2B
2A 2B
2A 2B
2A 2B
2A 2B
2A 2B
2B 3A
2B 3A
2B 3A
2B 3A
2B 3A
B 2B 3A B
2B 3A
A A
PROJECT : ZY2
DOC NO. PROJECT MODEL : ZY2 APPROVED BY: DATE: 2007/ 2/15
Change list
1A
PART NUMBER: DRAWING BY: REVISON: 3A
5 4 3 2 1

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5 4 http://laptopblue.

ZY6D SYSTEM BLOCK DIAGRAM

D@ DOCK ICS: ICS9LPRS365BGLFT

NCB@ NON CARDBUS

Touch Pad P22

Quanta Computer Inc.

K/B COON. PROJECT : ZY6D

Date: Thursday, August 28, 2008 Sheet 1 of 40

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+3V R255 BKP1608HS181-T +3V_CLK 2 12 +1V05_CLK BKP1608HS181-T R219 +1.05V

CPU_STOP# 37 PM_STPCPU# <14>

RP16 4 3 I@0X2 DREFCLK_R 13 21 CLK_PCIE_SATA_R RP18 3 4 0X2_4

10K_4 10K_4 SATACLKREQ#_R R475 10K_4

PCLK_PCM_R R260 10K_4

CPU Clock select BSEL Frequency Select Table

0 0 1 133Mhz PCLK_ICH_R R259 10K_4

http://hobi-elektronika.net CLOCK GENERATOR CK505 W/REGULATOR 1A

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A5 C7 PM_THRMTRIP# CPU_TEST1 C23 MISC U26 COMP1 R501 54.9/F_4

Thermal Trip CPU Thermal monitor XDP PU/PD +3V

XDP_DBRESET# and XDP_TDO +1.05V

RHU002N06 10K_4 10K_4 10K_4 LM86VCC

+1.05V XDP_TMS R131 54.9/F_4

56.2/F_4 U39 XDP_TRST# R124 54.9/F_4

PM_THRMTRIP# 1 3 MMBT3904 SYS_SHDN# <34,38>

<32> 2ND_MBDATA 3 1 7 2 C551

A Processor hot G780 A

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U40D VCC_CORE VCC_CORE

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2K/F_4 Quanta Computer Inc.

Date: Thursday, August 28, 2008 Sheet 5 of 40

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Pin Name Strap description Configuration

DDR CLK/ CONTROL/COMPENSATION

then to (G)MCH and CPU, in that BG45 E36

R188 *I@2.21K/F_4 SDVO_CTRLCLK NC_13

Date: Thursday, August 28, 2008 Sheet 6 of 40

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Rev: B Change P/N

R47 C_PEG_TXP5 C224 *E@.1U/10V_4 PEG_TXP5

Quanta Computer Inc.

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<16,17> M_A_DQ[63:0] <16,17> M_B_DQ[63:0]

M_A_DQ36 SA_DQ_35 SA_DQS#_7 M_B_DQ36 SB_DQ_35 SB_DQS#_6 M_B_DQS#7

AV5 SA_DQ_48 SA_MA_11 BG26 AV2 SB_DQ_48 SB_MA_10 BB16

Quanta Computer Inc.

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Power consumption reference to Intel

Intel check list(Rev 0.8) 270U*3 near to power(+V1.05M). ME Engine

VCC_AXG_NCTF_45 R228 I@0_8 VCC_NCTF_5

1. Route VCC_AXG_SENSE and VSS_AXG_SENSE differentially

Quanta Computer Inc.

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Design guide Table 72

IV&EV Dis/Enable setting 0805 100 nH, DCR=160 m

1.05V SP@:INT 1000 P 1.8V

VCCA_PEG_BG 1.5V 3.3V 400uA

50mA C529 VCCA_SM_# 1.05V 1.25V 1065mA

Date: Thursday, August 28, 2008 Sheet 10 of 40

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11/8 REV:B Y9 change footprint

R403 10K_4 453/F_4 .1U/10V_4 453/F_4 .1U/10V_4

HDMI_HP_A R19 ND@0_4 HDMI_MB_A +3V D@RHU002N06

22P/50V_4 22P/50V_4 *.01U/16V_4